diff options
Diffstat (limited to '')
| -rw-r--r-- | tools/perf/pmu-events/arch/x86/ivybridge/cache.json | 1102 | ||||
| -rw-r--r-- | tools/perf/pmu-events/arch/x86/ivybridge/floating-point.json | 151 | ||||
| -rw-r--r-- | tools/perf/pmu-events/arch/x86/ivybridge/frontend.json | 305 | ||||
| -rw-r--r-- | tools/perf/pmu-events/arch/x86/ivybridge/ivb-metrics.json | 340 | ||||
| -rw-r--r-- | tools/perf/pmu-events/arch/x86/ivybridge/memory.json | 236 | ||||
| -rw-r--r-- | tools/perf/pmu-events/arch/x86/ivybridge/other.json | 44 | ||||
| -rw-r--r-- | tools/perf/pmu-events/arch/x86/ivybridge/pipeline.json | 1305 | ||||
| -rw-r--r-- | tools/perf/pmu-events/arch/x86/ivybridge/uncore.json | 314 | ||||
| -rw-r--r-- | tools/perf/pmu-events/arch/x86/ivybridge/virtual-memory.json | 180 |
9 files changed, 3977 insertions, 0 deletions
diff --git a/tools/perf/pmu-events/arch/x86/ivybridge/cache.json b/tools/perf/pmu-events/arch/x86/ivybridge/cache.json new file mode 100644 index 000000000..5f6cb2abc --- /dev/null +++ b/tools/perf/pmu-events/arch/x86/ivybridge/cache.json @@ -0,0 +1,1102 @@ +[ + { + "PublicDescription": "Demand Data Read requests that hit L2 cache.", + "EventCode": "0x24", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "L2_RQSTS.DEMAND_DATA_RD_HIT", + "SampleAfterValue": "200003", + "BriefDescription": "Demand Data Read requests that hit L2 cache", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Counts any demand and L1 HW prefetch data load requests to L2.", + "EventCode": "0x24", + "Counter": "0,1,2,3", + "UMask": "0x3", + "EventName": "L2_RQSTS.ALL_DEMAND_DATA_RD", + "SampleAfterValue": "200003", + "BriefDescription": "Demand Data Read requests", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "RFO requests that hit L2 cache.", + "EventCode": "0x24", + "Counter": "0,1,2,3", + "UMask": "0x4", + "EventName": "L2_RQSTS.RFO_HIT", + "SampleAfterValue": "200003", + "BriefDescription": "RFO requests that hit L2 cache", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Counts the number of store RFO requests that miss the L2 cache.", + "EventCode": "0x24", + "Counter": "0,1,2,3", + "UMask": "0x8", + "EventName": "L2_RQSTS.RFO_MISS", + "SampleAfterValue": "200003", + "BriefDescription": "RFO requests that miss L2 cache", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Counts all L2 store RFO requests.", + "EventCode": "0x24", + "Counter": "0,1,2,3", + "UMask": "0xc", + "EventName": "L2_RQSTS.ALL_RFO", + "SampleAfterValue": "200003", + "BriefDescription": "RFO requests to L2 cache", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Number of instruction fetches that hit the L2 cache.", + "EventCode": "0x24", + "Counter": "0,1,2,3", + "UMask": "0x10", + "EventName": "L2_RQSTS.CODE_RD_HIT", + "SampleAfterValue": "200003", + "BriefDescription": "L2 cache hits when fetching instructions, code reads.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Number of instruction fetches that missed the L2 cache.", + "EventCode": "0x24", + "Counter": "0,1,2,3", + "UMask": "0x20", + "EventName": "L2_RQSTS.CODE_RD_MISS", + "SampleAfterValue": "200003", + "BriefDescription": "L2 cache misses when fetching instructions", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Counts all L2 code requests.", + "EventCode": "0x24", + "Counter": "0,1,2,3", + "UMask": "0x30", + "EventName": "L2_RQSTS.ALL_CODE_RD", + "SampleAfterValue": "200003", + "BriefDescription": "L2 code requests", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Counts all L2 HW prefetcher requests that hit L2.", + "EventCode": "0x24", + "Counter": "0,1,2,3", + "UMask": "0x40", + "EventName": "L2_RQSTS.PF_HIT", + "SampleAfterValue": "200003", + "BriefDescription": "Requests from the L2 hardware prefetchers that hit L2 cache", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Counts all L2 HW prefetcher requests that missed L2.", + "EventCode": "0x24", + "Counter": "0,1,2,3", + "UMask": "0x80", + "EventName": "L2_RQSTS.PF_MISS", + "SampleAfterValue": "200003", + "BriefDescription": "Requests from the L2 hardware prefetchers that miss L2 cache", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Counts all L2 HW prefetcher requests.", + "EventCode": "0x24", + "Counter": "0,1,2,3", + "UMask": "0xc0", + "EventName": "L2_RQSTS.ALL_PF", + "SampleAfterValue": "200003", + "BriefDescription": "Requests from L2 hardware prefetchers", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "RFOs that miss cache lines.", + "EventCode": "0x27", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "L2_STORE_LOCK_RQSTS.MISS", + "SampleAfterValue": "200003", + "BriefDescription": "RFOs that miss cache lines", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "RFOs that hit cache lines in M state.", + "EventCode": "0x27", + "Counter": "0,1,2,3", + "UMask": "0x8", + "EventName": "L2_STORE_LOCK_RQSTS.HIT_M", + "SampleAfterValue": "200003", + "BriefDescription": "RFOs that hit cache lines in M state", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "RFOs that access cache lines in any state.", + "EventCode": "0x27", + "Counter": "0,1,2,3", + "UMask": "0xf", + "EventName": "L2_STORE_LOCK_RQSTS.ALL", + "SampleAfterValue": "200003", + "BriefDescription": "RFOs that access cache lines in any state", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Not rejected writebacks that missed LLC.", + "EventCode": "0x28", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "L2_L1D_WB_RQSTS.MISS", + "SampleAfterValue": "200003", + "BriefDescription": "Count the number of modified Lines evicted from L1 and missed L2. (Non-rejected WBs from the DCU.)", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Not rejected writebacks from L1D to L2 cache lines in E state.", + "EventCode": "0x28", + "Counter": "0,1,2,3", + "UMask": "0x4", + "EventName": "L2_L1D_WB_RQSTS.HIT_E", + "SampleAfterValue": "200003", + "BriefDescription": "Not rejected writebacks from L1D to L2 cache lines in E state", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Not rejected writebacks from L1D to L2 cache lines in M state.", + "EventCode": "0x28", + "Counter": "0,1,2,3", + "UMask": "0x8", + "EventName": "L2_L1D_WB_RQSTS.HIT_M", + "SampleAfterValue": "200003", + "BriefDescription": "Not rejected writebacks from L1D to L2 cache lines in M state", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x28", + "Counter": "0,1,2,3", + "UMask": "0xf", + "EventName": "L2_L1D_WB_RQSTS.ALL", + "SampleAfterValue": "200003", + "BriefDescription": "Not rejected writebacks from L1D to L2 cache lines in any state.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "This event counts each cache miss condition for references to the last level cache.", + "EventCode": "0x2E", + "Counter": "0,1,2,3", + "UMask": "0x41", + "EventName": "LONGEST_LAT_CACHE.MISS", + "SampleAfterValue": "100003", + "BriefDescription": "Core-originated cacheable demand requests missed LLC", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "This event counts requests originating from the core that reference a cache line in the last level cache.", + "EventCode": "0x2E", + "Counter": "0,1,2,3", + "UMask": "0x4f", + "EventName": "LONGEST_LAT_CACHE.REFERENCE", + "SampleAfterValue": "100003", + "BriefDescription": "Core-originated cacheable demand requests that refer to LLC", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Increments the number of outstanding L1D misses every cycle. Set Cmask = 1 and Edge =1 to count occurrences.", + "EventCode": "0x48", + "Counter": "2", + "UMask": "0x1", + "EventName": "L1D_PEND_MISS.PENDING", + "SampleAfterValue": "2000003", + "BriefDescription": "L1D miss oustandings duration in cycles", + "CounterHTOff": "2" + }, + { + "EventCode": "0x48", + "Counter": "2", + "UMask": "0x1", + "EventName": "L1D_PEND_MISS.PENDING_CYCLES", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles with L1D load Misses outstanding.", + "CounterMask": "1", + "CounterHTOff": "2" + }, + { + "PublicDescription": "Cycles with L1D load Misses outstanding from any thread on physical core.", + "EventCode": "0x48", + "Counter": "2", + "UMask": "0x1", + "AnyThread": "1", + "EventName": "L1D_PEND_MISS.PENDING_CYCLES_ANY", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles with L1D load Misses outstanding from any thread on physical core", + "CounterMask": "1", + "CounterHTOff": "2" + }, + { + "PublicDescription": "Cycles a demand request was blocked due to Fill Buffers inavailability.", + "EventCode": "0x48", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "L1D_PEND_MISS.FB_FULL", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles a demand request was blocked due to Fill Buffers inavailability", + "CounterMask": "1", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Counts the number of lines brought into the L1 data cache.", + "EventCode": "0x51", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "L1D.REPLACEMENT", + "SampleAfterValue": "2000003", + "BriefDescription": "L1D data line replacements", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Offcore outstanding Demand Data Read transactions in SQ to uncore. Set Cmask=1 to count cycles.", + "EventCode": "0x60", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD", + "SampleAfterValue": "2000003", + "BriefDescription": "Offcore outstanding Demand Data Read transactions in uncore queue.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Cycles when offcore outstanding Demand Data Read transactions are present in SuperQueue (SQ), queue to uncore.", + "EventCode": "0x60", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_DATA_RD", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles when offcore outstanding Demand Data Read transactions are present in SuperQueue (SQ), queue to uncore", + "CounterMask": "1", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Cycles with at least 6 offcore outstanding Demand Data Read transactions in uncore queue.", + "EventCode": "0x60", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD_GE_6", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles with at least 6 offcore outstanding Demand Data Read transactions in uncore queue", + "CounterMask": "6", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Offcore outstanding Demand Code Read transactions in SQ to uncore. Set Cmask=1 to count cycles.", + "EventCode": "0x60", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_CODE_RD", + "SampleAfterValue": "2000003", + "BriefDescription": "Offcore outstanding code reads transactions in SuperQueue (SQ), queue to uncore, every cycle", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Offcore outstanding code reads transactions in SuperQueue (SQ), queue to uncore, every cycle.", + "EventCode": "0x60", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_CODE_RD", + "SampleAfterValue": "2000003", + "BriefDescription": "Offcore outstanding code reads transactions in SuperQueue (SQ), queue to uncore, every cycle", + "CounterMask": "1", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Offcore outstanding RFO store transactions in SQ to uncore. Set Cmask=1 to count cycles.", + "EventCode": "0x60", + "Counter": "0,1,2,3", + "UMask": "0x4", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_RFO", + "SampleAfterValue": "2000003", + "BriefDescription": "Offcore outstanding RFO store transactions in SuperQueue (SQ), queue to uncore", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Offcore outstanding demand rfo reads transactions in SuperQueue (SQ), queue to uncore, every cycle.", + "EventCode": "0x60", + "Counter": "0,1,2,3", + "UMask": "0x4", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO", + "SampleAfterValue": "2000003", + "BriefDescription": "Offcore outstanding demand rfo reads transactions in SuperQueue (SQ), queue to uncore, every cycle", + "CounterMask": "1", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Offcore outstanding cacheable data read transactions in SQ to uncore. Set Cmask=1 to count cycles.", + "EventCode": "0x60", + "Counter": "0,1,2,3", + "UMask": "0x8", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD", + "SampleAfterValue": "2000003", + "BriefDescription": "Offcore outstanding cacheable Core Data Read transactions in SuperQueue (SQ), queue to uncore", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Cycles when offcore outstanding cacheable Core Data Read transactions are present in SuperQueue (SQ), queue to uncore.", + "EventCode": "0x60", + "Counter": "0,1,2,3", + "UMask": "0x8", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles when offcore outstanding cacheable Core Data Read transactions are present in SuperQueue (SQ), queue to uncore", + "CounterMask": "1", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Cycles in which the L1D is locked.", + "EventCode": "0x63", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "LOCK_CYCLES.CACHE_LOCK_DURATION", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles when L1D is locked", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Demand data read requests sent to uncore.", + "EventCode": "0xB0", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_REQUESTS.DEMAND_DATA_RD", + "SampleAfterValue": "100003", + "BriefDescription": "Demand Data Read requests sent to uncore", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Demand code read requests sent to uncore.", + "EventCode": "0xB0", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "OFFCORE_REQUESTS.DEMAND_CODE_RD", + "SampleAfterValue": "100003", + "BriefDescription": "Cacheable and noncachaeble code read requests", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Demand RFO read requests sent to uncore, including regular RFOs, locks, ItoM.", + "EventCode": "0xB0", + "Counter": "0,1,2,3", + "UMask": "0x4", + "EventName": "OFFCORE_REQUESTS.DEMAND_RFO", + "SampleAfterValue": "100003", + "BriefDescription": "Demand RFO requests including regular RFOs, locks, ItoM", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Data read requests sent to uncore (demand and prefetch).", + "EventCode": "0xB0", + "Counter": "0,1,2,3", + "UMask": "0x8", + "EventName": "OFFCORE_REQUESTS.ALL_DATA_RD", + "SampleAfterValue": "100003", + "BriefDescription": "Demand and prefetch data reads", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Cases when offcore requests buffer cannot take more entries for core.", + "EventCode": "0xB2", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "OFFCORE_REQUESTS_BUFFER.SQ_FULL", + "SampleAfterValue": "2000003", + "BriefDescription": "Cases when offcore requests buffer cannot take more entries for core", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PEBS": "1", + "EventCode": "0xD0", + "Counter": "0,1,2,3", + "UMask": "0x11", + "EventName": "MEM_UOPS_RETIRED.STLB_MISS_LOADS", + "SampleAfterValue": "100003", + "BriefDescription": "Retired load uops that miss the STLB. (Precise Event)", + "CounterHTOff": "0,1,2,3" + }, + { + "PEBS": "1", + "EventCode": "0xD0", + "Counter": "0,1,2,3", + "UMask": "0x12", + "EventName": "MEM_UOPS_RETIRED.STLB_MISS_STORES", + "SampleAfterValue": "100003", + "BriefDescription": "Retired store uops that miss the STLB. (Precise Event)", + "CounterHTOff": "0,1,2,3" + }, + { + "PEBS": "1", + "EventCode": "0xD0", + "Counter": "0,1,2,3", + "UMask": "0x21", + "EventName": "MEM_UOPS_RETIRED.LOCK_LOADS", + "SampleAfterValue": "100007", + "BriefDescription": "Retired load uops with locked access. (Precise Event)", + "CounterHTOff": "0,1,2,3" + }, + { + "PEBS": "1", + "EventCode": "0xD0", + "Counter": "0,1,2,3", + "UMask": "0x41", + "EventName": "MEM_UOPS_RETIRED.SPLIT_LOADS", + "SampleAfterValue": "100003", + "BriefDescription": "Retired load uops that split across a cacheline boundary. (Precise Event)", + "CounterHTOff": "0,1,2,3" + }, + { + "PEBS": "1", + "EventCode": "0xD0", + "Counter": "0,1,2,3", + "UMask": "0x42", + "EventName": "MEM_UOPS_RETIRED.SPLIT_STORES", + "SampleAfterValue": "100003", + "BriefDescription": "Retired store uops that split across a cacheline boundary. (Precise Event)", + "CounterHTOff": "0,1,2,3" + }, + { + "PEBS": "1", + "EventCode": "0xD0", + "Counter": "0,1,2,3", + "UMask": "0x81", + "EventName": "MEM_UOPS_RETIRED.ALL_LOADS", + "SampleAfterValue": "2000003", + "BriefDescription": "All retired load uops. (Precise Event)", + "CounterHTOff": "0,1,2,3" + }, + { + "PEBS": "1", + "EventCode": "0xD0", + "Counter": "0,1,2,3", + "UMask": "0x82", + "EventName": "MEM_UOPS_RETIRED.ALL_STORES", + "SampleAfterValue": "2000003", + "BriefDescription": "All retired store uops. (Precise Event)", + "CounterHTOff": "0,1,2,3" + }, + { + "PEBS": "1", + "EventCode": "0xD1", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "MEM_LOAD_UOPS_RETIRED.L1_HIT", + "SampleAfterValue": "2000003", + "BriefDescription": "Retired load uops with L1 cache hits as data sources.", + "CounterHTOff": "0,1,2,3" + }, + { + "PEBS": "1", + "EventCode": "0xD1", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "MEM_LOAD_UOPS_RETIRED.L2_HIT", + "SampleAfterValue": "100003", + "BriefDescription": "Retired load uops with L2 cache hits as data sources.", + "CounterHTOff": "0,1,2,3" + }, + { + "PEBS": "1", + "EventCode": "0xD1", + "Counter": "0,1,2,3", + "UMask": "0x4", + "EventName": "MEM_LOAD_UOPS_RETIRED.LLC_HIT", + "SampleAfterValue": "50021", + "BriefDescription": "Retired load uops which data sources were data hits in LLC without snoops required.", + "CounterHTOff": "0,1,2,3" + }, + { + "PEBS": "1", + "EventCode": "0xD1", + "Counter": "0,1,2,3", + "UMask": "0x8", + "EventName": "MEM_LOAD_UOPS_RETIRED.L1_MISS", + "SampleAfterValue": "100003", + "BriefDescription": "Retired load uops which data sources following L1 data-cache miss.", + "CounterHTOff": "0,1,2,3" + }, + { + "PEBS": "1", + "EventCode": "0xD1", + "Counter": "0,1,2,3", + "UMask": "0x10", + "EventName": "MEM_LOAD_UOPS_RETIRED.L2_MISS", + "SampleAfterValue": "50021", + "BriefDescription": "Retired load uops with L2 cache misses as data sources.", + "CounterHTOff": "0,1,2,3" + }, + { + "PEBS": "1", + "EventCode": "0xD1", + "Counter": "0,1,2,3", + "UMask": "0x20", + "EventName": "MEM_LOAD_UOPS_RETIRED.LLC_MISS", + "SampleAfterValue": "100007", + "BriefDescription": "Miss in last-level (L3) cache. Excludes Unknown data-source.", + "CounterHTOff": "0,1,2,3" + }, + { + "PEBS": "1", + "EventCode": "0xD1", + "Counter": "0,1,2,3", + "UMask": "0x40", + "EventName": "MEM_LOAD_UOPS_RETIRED.HIT_LFB", + "SampleAfterValue": "100003", + "BriefDescription": "Retired load uops which data sources were load uops missed L1 but hit FB due to preceding miss to the same cache line with data not ready.", + "CounterHTOff": "0,1,2,3" + }, + { + "PEBS": "1", + "EventCode": "0xD2", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_MISS", + "SampleAfterValue": "20011", + "BriefDescription": "Retired load uops which data sources were LLC hit and cross-core snoop missed in on-pkg core cache.", + "CounterHTOff": "0,1,2,3" + }, + { + "PEBS": "1", + "EventCode": "0xD2", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HIT", + "SampleAfterValue": "20011", + "BriefDescription": "Retired load uops which data sources were LLC and cross-core snoop hits in on-pkg core cache.", + "CounterHTOff": "0,1,2,3" + }, + { + "PEBS": "1", + "EventCode": "0xD2", + "Counter": "0,1,2,3", + "UMask": "0x4", + "EventName": "MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HITM", + "SampleAfterValue": "20011", + "BriefDescription": "Retired load uops which data sources were HitM responses from shared LLC.", + "CounterHTOff": "0,1,2,3" + }, + { + "PEBS": "1", + "EventCode": "0xD2", + "Counter": "0,1,2,3", + "UMask": "0x8", + "EventName": "MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_NONE", + "SampleAfterValue": "100003", + "BriefDescription": "Retired load uops which data sources were hits in LLC without snoops required.", + "CounterHTOff": "0,1,2,3" + }, + { + "PublicDescription": "Retired load uops whose data source was local memory (cross-socket snoop not needed or missed).", + "EventCode": "0xD3", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "MEM_LOAD_UOPS_LLC_MISS_RETIRED.LOCAL_DRAM", + "SampleAfterValue": "100007", + "BriefDescription": "Retired load uops which data sources missed LLC but serviced from local dram.", + "CounterHTOff": "0,1,2,3" + }, + { + "PublicDescription": "Demand Data Read requests that access L2 cache.", + "EventCode": "0xF0", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "L2_TRANS.DEMAND_DATA_RD", + "SampleAfterValue": "200003", + "BriefDescription": "Demand Data Read requests that access L2 cache", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "RFO requests that access L2 cache.", + "EventCode": "0xF0", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "L2_TRANS.RFO", + "SampleAfterValue": "200003", + "BriefDescription": "RFO requests that access L2 cache", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "L2 cache accesses when fetching instructions.", + "EventCode": "0xF0", + "Counter": "0,1,2,3", + "UMask": "0x4", + "EventName": "L2_TRANS.CODE_RD", + "SampleAfterValue": "200003", + "BriefDescription": "L2 cache accesses when fetching instructions", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Any MLC or LLC HW prefetch accessing L2, including rejects.", + "EventCode": "0xF0", + "Counter": "0,1,2,3", + "UMask": "0x8", + "EventName": "L2_TRANS.ALL_PF", + "SampleAfterValue": "200003", + "BriefDescription": "L2 or LLC HW prefetches that access L2 cache", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "L1D writebacks that access L2 cache.", + "EventCode": "0xF0", + "Counter": "0,1,2,3", + "UMask": "0x10", + "EventName": "L2_TRANS.L1D_WB", + "SampleAfterValue": "200003", + "BriefDescription": "L1D writebacks that access L2 cache", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "L2 fill requests that access L2 cache.", + "EventCode": "0xF0", + "Counter": "0,1,2,3", + "UMask": "0x20", + "EventName": "L2_TRANS.L2_FILL", + "SampleAfterValue": "200003", + "BriefDescription": "L2 fill requests that access L2 cache", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "L2 writebacks that access L2 cache.", + "EventCode": "0xF0", + "Counter": "0,1,2,3", + "UMask": "0x40", + "EventName": "L2_TRANS.L2_WB", + "SampleAfterValue": "200003", + "BriefDescription": "L2 writebacks that access L2 cache", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Transactions accessing L2 pipe.", + "EventCode": "0xF0", + "Counter": "0,1,2,3", + "UMask": "0x80", + "EventName": "L2_TRANS.ALL_REQUESTS", + "SampleAfterValue": "200003", + "BriefDescription": "Transactions accessing L2 pipe", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "L2 cache lines in I state filling L2.", + "EventCode": "0xF1", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "L2_LINES_IN.I", + "SampleAfterValue": "100003", + "BriefDescription": "L2 cache lines in I state filling L2", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "L2 cache lines in S state filling L2.", + "EventCode": "0xF1", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "L2_LINES_IN.S", + "SampleAfterValue": "100003", + "BriefDescription": "L2 cache lines in S state filling L2", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "L2 cache lines in E state filling L2.", + "EventCode": "0xF1", + "Counter": "0,1,2,3", + "UMask": "0x4", + "EventName": "L2_LINES_IN.E", + "SampleAfterValue": "100003", + "BriefDescription": "L2 cache lines in E state filling L2", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "L2 cache lines filling L2.", + "EventCode": "0xF1", + "Counter": "0,1,2,3", + "UMask": "0x7", + "EventName": "L2_LINES_IN.ALL", + "SampleAfterValue": "100003", + "BriefDescription": "L2 cache lines filling L2", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Clean L2 cache lines evicted by demand.", + "EventCode": "0xF2", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "L2_LINES_OUT.DEMAND_CLEAN", + "SampleAfterValue": "100003", + "BriefDescription": "Clean L2 cache lines evicted by demand", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Dirty L2 cache lines evicted by demand.", + "EventCode": "0xF2", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "L2_LINES_OUT.DEMAND_DIRTY", + "SampleAfterValue": "100003", + "BriefDescription": "Dirty L2 cache lines evicted by demand", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Clean L2 cache lines evicted by the MLC prefetcher.", + "EventCode": "0xF2", + "Counter": "0,1,2,3", + "UMask": "0x4", + "EventName": "L2_LINES_OUT.PF_CLEAN", + "SampleAfterValue": "100003", + "BriefDescription": "Clean L2 cache lines evicted by L2 prefetch", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Dirty L2 cache lines evicted by the MLC prefetcher.", + "EventCode": "0xF2", + "Counter": "0,1,2,3", + "UMask": "0x8", + "EventName": "L2_LINES_OUT.PF_DIRTY", + "SampleAfterValue": "100003", + "BriefDescription": "Dirty L2 cache lines evicted by L2 prefetch", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Dirty L2 cache lines filling the L2.", + "EventCode": "0xF2", + "Counter": "0,1,2,3", + "UMask": "0xa", + "EventName": "L2_LINES_OUT.DIRTY_ALL", + "SampleAfterValue": "100003", + "BriefDescription": "Dirty L2 cache lines filling the L2", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xF4", + "Counter": "0,1,2,3", + "UMask": "0x10", + "EventName": "SQ_MISC.SPLIT_LOCK", + "SampleAfterValue": "100003", + "BriefDescription": "Split locks in SQ", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x3f803c0244", + "Counter": "0,1,2,3", + "UMask": "0x1", + "Offcore": "1", + "EventName": "OFFCORE_RESPONSE.ALL_CODE_RD.LLC_HIT.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts all demand & prefetch code reads that hit in the LLC", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x1003c0244", + "Counter": "0,1,2,3", + "UMask": "0x1", + "Offcore": "1", + "EventName": "OFFCORE_RESPONSE.ALL_CODE_RD.LLC_HIT.NO_SNOOP_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts demand & prefetch code reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x3f803c0091", + "Counter": "0,1,2,3", + "UMask": "0x1", + "Offcore": "1", + "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_HIT.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts all demand & prefetch data reads that hit in the LLC", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x4003c0091", + "Counter": "0,1,2,3", + "UMask": "0x1", + "Offcore": "1", + "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts demand & prefetch data reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x10003c0091", + "Counter": "0,1,2,3", + "UMask": "0x1", + "Offcore": "1", + "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_HIT.HITM_OTHER_CORE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts demand & prefetch data reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x1003c0091", + "Counter": "0,1,2,3", + "UMask": "0x1", + "Offcore": "1", + "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_HIT.NO_SNOOP_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts demand & prefetch data reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x3f803c0122", + "Counter": "0,1,2,3", + "UMask": "0x1", + "Offcore": "1", + "EventName": "OFFCORE_RESPONSE.ALL_RFO.LLC_HIT.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts all demand & prefetch RFOs that hit in the LLC", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x1003c0122", + "Counter": "0,1,2,3", + "UMask": "0x1", + "Offcore": "1", + "EventName": "OFFCORE_RESPONSE.ALL_RFO.LLC_HIT.NO_SNOOP_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts demand & prefetch RFOs that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x10008", + "Counter": "0,1,2,3", + "UMask": "0x1", + "Offcore": "1", + "EventName": "OFFCORE_RESPONSE.COREWB.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts all writebacks from the core to the LLC", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x3f803c0004", + "Counter": "0,1,2,3", + "UMask": "0x1", + "Offcore": "1", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_HIT.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts all demand code reads that hit in the LLC", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x1003c0004", + "Counter": "0,1,2,3", + "UMask": "0x1", + "Offcore": "1", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_HIT.NO_SNOOP_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts demand code reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x3f803c0001", + "Counter": "0,1,2,3", + "UMask": "0x1", + "Offcore": "1", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts all demand data reads that hit in the LLC", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x4003c0001", + "Counter": "0,1,2,3", + "UMask": "0x1", + "Offcore": "1", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts demand data reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x10003c0001", + "Counter": "0,1,2,3", + "UMask": "0x1", + "Offcore": "1", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.HITM_OTHER_CORE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts demand data reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x1003c0001", + "Counter": "0,1,2,3", + "UMask": "0x1", + "Offcore": "1", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.NO_SNOOP_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts demand data reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x3f803c0002", + "Counter": "0,1,2,3", + "UMask": "0x1", + "Offcore": "1", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts all demand data writes (RFOs) that hit in the LLC", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x10003c0002", + "Counter": "0,1,2,3", + "UMask": "0x1", + "Offcore": "1", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT.HITM_OTHER_CORE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts demand data writes (RFOs) that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x1003c0002", + "Counter": "0,1,2,3", + "UMask": "0x1", + "Offcore": "1", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT.NO_SNOOP_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts demand data writes (RFOs) that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x18000", + "Counter": "0,1,2,3", + "UMask": "0x1", + "Offcore": "1", + "EventName": "OFFCORE_RESPONSE.OTHER.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts miscellaneous accesses that include port i/o, MMIO and uncacheable memory accesses. It also includes L2 hints sent to LLC to keep a line from being evicted out of the core caches", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x10400", + "Counter": "0,1,2,3", + "UMask": "0x1", + "Offcore": "1", + "EventName": "OFFCORE_RESPONSE.SPLIT_LOCK_UC_LOCK.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts requests where the address of an atomic lock instruction spans a cache line boundary or the lock instruction is executed on uncacheable address", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x10800", + "Counter": "0,1,2,3", + "UMask": "0x1", + "Offcore": "1", + "EventName": "OFFCORE_RESPONSE.STREAMING_STORES.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts non-temporal stores", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x00010001", + "Counter": "0,1,2,3", + "UMask": "0x1", + "Offcore": "1", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts all demand data reads", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x00010002", + "Counter": "0,1,2,3", + "UMask": "0x1", + "Offcore": "1", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts all demand rfo's", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x00010004", + "Counter": "0,1,2,3", + "UMask": "0x1", + "Offcore": "1", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts all demand code reads", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x000105B3", + "Counter": "0,1,2,3", + "UMask": "0x1", + "Offcore": "1", + "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts all demand & prefetch data reads", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x00010122", + "Counter": "0,1,2,3", + "UMask": "0x1", + "Offcore": "1", + "EventName": "OFFCORE_RESPONSE.ALL_RFO.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts all demand & prefetch prefetch RFOs", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x000107F7", + "Counter": "0,1,2,3", + "UMask": "0x1", + "Offcore": "1", + "EventName": "OFFCORE_RESPONSE.ALL_READS.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts all data/code/rfo references (demand & prefetch)", + "CounterHTOff": "0,1,2,3" + } +]
\ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/ivybridge/floating-point.json b/tools/perf/pmu-events/arch/x86/ivybridge/floating-point.json new file mode 100644 index 000000000..950b62c09 --- /dev/null +++ b/tools/perf/pmu-events/arch/x86/ivybridge/floating-point.json @@ -0,0 +1,151 @@ +[ + { + "PublicDescription": "Counts number of X87 uops executed.", + "EventCode": "0x10", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "FP_COMP_OPS_EXE.X87", + "SampleAfterValue": "2000003", + "BriefDescription": "Number of FP Computational Uops Executed this cycle. The number of FADD, FSUB, FCOM, FMULs, integer MULsand IMULs, FDIVs, FPREMs, FSQRTS, integer DIVs, and IDIVs. This event does not distinguish an FADD used in the middle of a transcendental flow from a s", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Number of SSE* or AVX-128 FP Computational packed double-precision uops issued this cycle.", + "EventCode": "0x10", + "Counter": "0,1,2,3", + "UMask": "0x10", + "EventName": "FP_COMP_OPS_EXE.SSE_PACKED_DOUBLE", + "SampleAfterValue": "2000003", + "BriefDescription": "Number of SSE* or AVX-128 FP Computational packed double-precision uops issued this cycle", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Number of SSE* or AVX-128 FP Computational scalar single-precision uops issued this cycle.", + "EventCode": "0x10", + "Counter": "0,1,2,3", + "UMask": "0x20", + "EventName": "FP_COMP_OPS_EXE.SSE_SCALAR_SINGLE", + "SampleAfterValue": "2000003", + "BriefDescription": "Number of SSE* or AVX-128 FP Computational scalar single-precision uops issued this cycle", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Number of SSE* or AVX-128 FP Computational packed single-precision uops issued this cycle.", + "EventCode": "0x10", + "Counter": "0,1,2,3", + "UMask": "0x40", + "EventName": "FP_COMP_OPS_EXE.SSE_PACKED_SINGLE", + "SampleAfterValue": "2000003", + "BriefDescription": "Number of SSE* or AVX-128 FP Computational packed single-precision uops issued this cycle", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Counts number of SSE* or AVX-128 double precision FP scalar uops executed.", + "EventCode": "0x10", + "Counter": "0,1,2,3", + "UMask": "0x80", + "EventName": "FP_COMP_OPS_EXE.SSE_SCALAR_DOUBLE", + "SampleAfterValue": "2000003", + "BriefDescription": "Number of SSE* or AVX-128 FP Computational scalar double-precision uops issued this cycle", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Counts 256-bit packed single-precision floating-point instructions.", + "EventCode": "0x11", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "SIMD_FP_256.PACKED_SINGLE", + "SampleAfterValue": "2000003", + "BriefDescription": "number of GSSE-256 Computational FP single precision uops issued this cycle", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Counts 256-bit packed double-precision floating-point instructions.", + "EventCode": "0x11", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "SIMD_FP_256.PACKED_DOUBLE", + "SampleAfterValue": "2000003", + "BriefDescription": "number of AVX-256 Computational FP double precision uops issued this cycle", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Number of assists associated with 256-bit AVX store operations.", + "EventCode": "0xC1", + "Counter": "0,1,2,3", + "UMask": "0x8", + "EventName": "OTHER_ASSISTS.AVX_STORE", + "SampleAfterValue": "100003", + "BriefDescription": "Number of GSSE memory assist for stores. GSSE microcode assist is being invoked whenever the hardware is unable to properly handle GSSE-256b operations.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xC1", + "Counter": "0,1,2,3", + "UMask": "0x10", + "EventName": "OTHER_ASSISTS.AVX_TO_SSE", + "SampleAfterValue": "100003", + "BriefDescription": "Number of transitions from AVX-256 to legacy SSE when penalty applicable.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xC1", + "Counter": "0,1,2,3", + "UMask": "0x20", + "EventName": "OTHER_ASSISTS.SSE_TO_AVX", + "SampleAfterValue": "100003", + "BriefDescription": "Number of transitions from SSE to AVX-256 when penalty applicable.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Number of X87 FP assists due to output values.", + "EventCode": "0xCA", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "FP_ASSIST.X87_OUTPUT", + "SampleAfterValue": "100003", + "BriefDescription": "Number of X87 assists due to output value.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Number of X87 FP assists due to input values.", + "EventCode": "0xCA", + "Counter": "0,1,2,3", + "UMask": "0x4", + "EventName": "FP_ASSIST.X87_INPUT", + "SampleAfterValue": "100003", + "BriefDescription": "Number of X87 assists due to input value.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Number of SIMD FP assists due to output values.", + "EventCode": "0xCA", + "Counter": "0,1,2,3", + "UMask": "0x8", + "EventName": "FP_ASSIST.SIMD_OUTPUT", + "SampleAfterValue": "100003", + "BriefDescription": "Number of SIMD FP assists due to Output values", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Number of SIMD FP assists due to input values.", + "EventCode": "0xCA", + "Counter": "0,1,2,3", + "UMask": "0x10", + "EventName": "FP_ASSIST.SIMD_INPUT", + "SampleAfterValue": "100003", + "BriefDescription": "Number of SIMD FP assists due to input values", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Cycles with any input/output SSE* or FP assists.", + "EventCode": "0xCA", + "Counter": "0,1,2,3", + "UMask": "0x1e", + "EventName": "FP_ASSIST.ANY", + "SampleAfterValue": "100003", + "BriefDescription": "Cycles with any input/output SSE or FP assist", + "CounterMask": "1", + "CounterHTOff": "0,1,2,3" + } +]
\ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/ivybridge/frontend.json b/tools/perf/pmu-events/arch/x86/ivybridge/frontend.json new file mode 100644 index 000000000..efaa949ea --- /dev/null +++ b/tools/perf/pmu-events/arch/x86/ivybridge/frontend.json @@ -0,0 +1,305 @@ +[ + { + "PublicDescription": "Counts cycles the IDQ is empty.", + "EventCode": "0x79", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "IDQ.EMPTY", + "SampleAfterValue": "2000003", + "BriefDescription": "Instruction Decode Queue (IDQ) empty cycles", + "CounterHTOff": "0,1,2,3" + }, + { + "PublicDescription": "Increment each cycle # of uops delivered to IDQ from MITE path. Set Cmask = 1 to count cycles.", + "EventCode": "0x79", + "Counter": "0,1,2,3", + "UMask": "0x4", + "EventName": "IDQ.MITE_UOPS", + "SampleAfterValue": "2000003", + "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from MITE path", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from MITE path.", + "EventCode": "0x79", + "Counter": "0,1,2,3", + "UMask": "0x4", + "EventName": "IDQ.MITE_CYCLES", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from MITE path", + "CounterMask": "1", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Increment each cycle. # of uops delivered to IDQ from DSB path. Set Cmask = 1 to count cycles.", + "EventCode": "0x79", + "Counter": "0,1,2,3", + "UMask": "0x8", + "EventName": "IDQ.DSB_UOPS", + "SampleAfterValue": "2000003", + "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from Decode Stream Buffer (DSB) path.", + "EventCode": "0x79", + "Counter": "0,1,2,3", + "UMask": "0x8", + "EventName": "IDQ.DSB_CYCLES", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from Decode Stream Buffer (DSB) path", + "CounterMask": "1", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Increment each cycle # of uops delivered to IDQ when MS_busy by DSB. Set Cmask = 1 to count cycles. Add Edge=1 to count # of delivery.", + "EventCode": "0x79", + "Counter": "0,1,2,3", + "UMask": "0x10", + "EventName": "IDQ.MS_DSB_UOPS", + "SampleAfterValue": "2000003", + "BriefDescription": "Uops initiated by Decode Stream Buffer (DSB) that are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Cycles when uops initiated by Decode Stream Buffer (DSB) are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy.", + "EventCode": "0x79", + "Counter": "0,1,2,3", + "UMask": "0x10", + "EventName": "IDQ.MS_DSB_CYCLES", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles when uops initiated by Decode Stream Buffer (DSB) are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy", + "CounterMask": "1", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Deliveries to Instruction Decode Queue (IDQ) initiated by Decode Stream Buffer (DSB) while Microcode Sequenser (MS) is busy.", + "EventCode": "0x79", + "Counter": "0,1,2,3", + "UMask": "0x10", + "EdgeDetect": "1", + "EventName": "IDQ.MS_DSB_OCCUR", + "SampleAfterValue": "2000003", + "BriefDescription": "Deliveries to Instruction Decode Queue (IDQ) initiated by Decode Stream Buffer (DSB) while Microcode Sequenser (MS) is busy", + "CounterMask": "1", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Counts cycles DSB is delivered four uops. Set Cmask = 4.", + "EventCode": "0x79", + "Counter": "0,1,2,3", + "UMask": "0x18", + "EventName": "IDQ.ALL_DSB_CYCLES_4_UOPS", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering 4 Uops", + "CounterMask": "4", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Counts cycles DSB is delivered at least one uops. Set Cmask = 1.", + "EventCode": "0x79", + "Counter": "0,1,2,3", + "UMask": "0x18", + "EventName": "IDQ.ALL_DSB_CYCLES_ANY_UOPS", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering any Uop", + "CounterMask": "1", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Increment each cycle # of uops delivered to IDQ when MS_busy by MITE. Set Cmask = 1 to count cycles.", + "EventCode": "0x79", + "Counter": "0,1,2,3", + "UMask": "0x20", + "EventName": "IDQ.MS_MITE_UOPS", + "SampleAfterValue": "2000003", + "BriefDescription": "Uops initiated by MITE and delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Counts cycles MITE is delivered four uops. Set Cmask = 4.", + "EventCode": "0x79", + "Counter": "0,1,2,3", + "UMask": "0x24", + "EventName": "IDQ.ALL_MITE_CYCLES_4_UOPS", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles MITE is delivering 4 Uops", + "CounterMask": "4", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Counts cycles MITE is delivered at least one uops. Set Cmask = 1.", + "EventCode": "0x79", + "Counter": "0,1,2,3", + "UMask": "0x24", + "EventName": "IDQ.ALL_MITE_CYCLES_ANY_UOPS", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles MITE is delivering any Uop", + "CounterMask": "1", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Increment each cycle # of uops delivered to IDQ from MS by either DSB or MITE. Set Cmask = 1 to count cycles.", + "EventCode": "0x79", + "Counter": "0,1,2,3", + "UMask": "0x30", + "EventName": "IDQ.MS_UOPS", + "SampleAfterValue": "2000003", + "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy.", + "EventCode": "0x79", + "Counter": "0,1,2,3", + "UMask": "0x30", + "EventName": "IDQ.MS_CYCLES", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy", + "CounterMask": "1", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Number of switches from DSB (Decode Stream Buffer) or MITE (legacy decode pipeline) to the Microcode Sequencer.", + "EventCode": "0x79", + "Counter": "0,1,2,3", + "UMask": "0x30", + "EdgeDetect": "1", + "EventName": "IDQ.MS_SWITCHES", + "SampleAfterValue": "2000003", + "BriefDescription": "Number of switches from DSB (Decode Stream Buffer) or MITE (legacy decode pipeline) to the Microcode Sequencer", + "CounterMask": "1", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Number of uops delivered to IDQ from any path.", + "EventCode": "0x79", + "Counter": "0,1,2,3", + "UMask": "0x3c", + "EventName": "IDQ.MITE_ALL_UOPS", + "SampleAfterValue": "2000003", + "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from MITE path", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Number of Instruction Cache, Streaming Buffer and Victim Cache Reads. both cacheable and noncacheable, including UC fetches.", + "EventCode": "0x80", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "ICACHE.HIT", + "SampleAfterValue": "2000003", + "BriefDescription": "Number of Instruction Cache, Streaming Buffer and Victim Cache Reads. both cacheable and noncacheable, including UC fetches", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Number of Instruction Cache, Streaming Buffer and Victim Cache Misses. Includes UC accesses.", + "EventCode": "0x80", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "ICACHE.MISSES", + "SampleAfterValue": "200003", + "BriefDescription": "Instruction cache, streaming buffer and victim cache misses", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Cycles where a code-fetch stalled due to L1 instruction-cache miss or an iTLB miss.", + "EventCode": "0x80", + "Counter": "0,1,2,3", + "UMask": "0x4", + "EventName": "ICACHE.IFETCH_STALL", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles where a code-fetch stalled due to L1 instruction-cache miss or an iTLB miss", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Count issue pipeline slots where no uop was delivered from the front end to the back end when there is no back-end stall.", + "EventCode": "0x9C", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "IDQ_UOPS_NOT_DELIVERED.CORE", + "SampleAfterValue": "2000003", + "BriefDescription": "Uops not delivered to Resource Allocation Table (RAT) per thread when backend of the machine is not stalled", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0x9C", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles per thread when 4 or more uops are not delivered to Resource Allocation Table (RAT) when backend of the machine is not stalled.", + "CounterMask": "4", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0x9C", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_1_UOP_DELIV.CORE", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles per thread when 3 or more uops are not delivered to Resource Allocation Table (RAT) when backend of the machine is not stalled.", + "CounterMask": "3", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0x9C", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_2_UOP_DELIV.CORE", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles with less than 2 uops delivered by the front end.", + "CounterMask": "2", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0x9C", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_3_UOP_DELIV.CORE", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles with less than 3 uops delivered by the front end.", + "CounterMask": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0x9C", + "Invert": "1", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_FE_WAS_OK", + "SampleAfterValue": "2000003", + "BriefDescription": "Counts cycles FE delivered 4 uops or Resource Allocation Table (RAT) was stalling FE.", + "CounterMask": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "PublicDescription": "Number of DSB to MITE switches.", + "EventCode": "0xAB", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "DSB2MITE_SWITCHES.COUNT", + "SampleAfterValue": "2000003", + "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switches", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Cycles DSB to MITE switches caused delay.", + "EventCode": "0xAB", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "DSB2MITE_SWITCHES.PENALTY_CYCLES", + "SampleAfterValue": "2000003", + "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "DSB Fill encountered > 3 DSB lines.", + "EventCode": "0xAC", + "Counter": "0,1,2,3", + "UMask": "0x8", + "EventName": "DSB_FILL.EXCEED_DSB_LINES", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles when Decode Stream Buffer (DSB) fill encounter more than 3 Decode Stream Buffer (DSB) lines", + "CounterHTOff": "0,1,2,3,4,5,6,7" + } +]
\ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/ivybridge/ivb-metrics.json b/tools/perf/pmu-events/arch/x86/ivybridge/ivb-metrics.json new file mode 100644 index 000000000..28e25447d --- /dev/null +++ b/tools/perf/pmu-events/arch/x86/ivybridge/ivb-metrics.json @@ -0,0 +1,340 @@ +[ + { + "BriefDescription": "This category represents fraction of slots where the processor's Frontend undersupplies its Backend", + "MetricExpr": "IDQ_UOPS_NOT_DELIVERED.CORE / (4 * cycles)", + "MetricGroup": "TopdownL1", + "MetricName": "Frontend_Bound", + "PublicDescription": "This category represents fraction of slots where the processor's Frontend undersupplies its Backend. Frontend denotes the first part of the processor core responsible to fetch operations that are executed later on by the Backend part. Within the Frontend; a branch predictor predicts the next address to fetch; cache-lines are fetched from the memory subsystem; parsed into instructions; and lastly decoded into micro-ops (uops). Ideally the Frontend can issue 4 uops every cycle to the Backend. Frontend Bound denotes unutilized issue-slots when there is no Backend stall; i.e. bubbles where Frontend delivered no uops while Backend could have accepted them. For example; stalls due to instruction-cache misses would be categorized under Frontend Bound." + }, + { + "BriefDescription": "This category represents fraction of slots where the processor's Frontend undersupplies its Backend. SMT version; use when SMT is enabled and measuring per logical CPU.", + "MetricExpr": "IDQ_UOPS_NOT_DELIVERED.CORE / (4 * (( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )))", + "MetricGroup": "TopdownL1_SMT", + "MetricName": "Frontend_Bound_SMT", + "PublicDescription": "This category represents fraction of slots where the processor's Frontend undersupplies its Backend. Frontend denotes the first part of the processor core responsible to fetch operations that are executed later on by the Backend part. Within the Frontend; a branch predictor predicts the next address to fetch; cache-lines are fetched from the memory subsystem; parsed into instructions; and lastly decoded into micro-ops (uops). Ideally the Frontend can issue 4 uops every cycle to the Backend. Frontend Bound denotes unutilized issue-slots when there is no Backend stall; i.e. bubbles where Frontend delivered no uops while Backend could have accepted them. For example; stalls due to instruction-cache misses would be categorized under Frontend Bound. SMT version; use when SMT is enabled and measuring per logical CPU." + }, + { + "BriefDescription": "This category represents fraction of slots wasted due to incorrect speculations", + "MetricExpr": "( UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 * INT_MISC.RECOVERY_CYCLES ) / (4 * cycles)", + "MetricGroup": "TopdownL1", + "MetricName": "Bad_Speculation", + "PublicDescription": "This category represents fraction of slots wasted due to incorrect speculations. This include slots used to issue uops that do not eventually get retired and slots for which the issue-pipeline was blocked due to recovery from earlier incorrect speculation. For example; wasted work due to miss-predicted branches are categorized under Bad Speculation category. Incorrect data speculation followed by Memory Ordering Nukes is another example." + }, + { + "BriefDescription": "This category represents fraction of slots wasted due to incorrect speculations. SMT version; use when SMT is enabled and measuring per logical CPU.", + "MetricExpr": "( UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 * (( INT_MISC.RECOVERY_CYCLES_ANY / 2 )) ) / (4 * (( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )))", + "MetricGroup": "TopdownL1_SMT", + "MetricName": "Bad_Speculation_SMT", + "PublicDescription": "This category represents fraction of slots wasted due to incorrect speculations. This include slots used to issue uops that do not eventually get retired and slots for which the issue-pipeline was blocked due to recovery from earlier incorrect speculation. For example; wasted work due to miss-predicted branches are categorized under Bad Speculation category. Incorrect data speculation followed by Memory Ordering Nukes is another example. SMT version; use when SMT is enabled and measuring per logical CPU." + }, + { + "BriefDescription": "This category represents fraction of slots where no uops are being delivered due to a lack of required resources for accepting new uops in the Backend", + "MetricExpr": "1 - ( (IDQ_UOPS_NOT_DELIVERED.CORE / (4 * cycles)) + (( UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 * INT_MISC.RECOVERY_CYCLES ) / (4 * cycles)) + (UOPS_RETIRED.RETIRE_SLOTS / (4 * cycles)) )", + "MetricGroup": "TopdownL1", + "MetricName": "Backend_Bound", + "PublicDescription": "This category represents fraction of slots where no uops are being delivered due to a lack of required resources for accepting new uops in the Backend. Backend is the portion of the processor core where the out-of-order scheduler dispatches ready uops into their respective execution units; and once completed these uops get retired according to program order. For example; stalls due to data-cache misses or stalls due to the divider unit being overloaded are both categorized under Backend Bound. Backend Bound is further divided into two main categories: Memory Bound and Core Bound." + }, + { + "BriefDescription": "This category represents fraction of slots where no uops are being delivered due to a lack of required resources for accepting new uops in the Backend. SMT version; use when SMT is enabled and measuring per logical CPU.", + "MetricExpr": "1 - ( (IDQ_UOPS_NOT_DELIVERED.CORE / (4 * (( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )))) + (( UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 * (( INT_MISC.RECOVERY_CYCLES_ANY / 2 )) ) / (4 * (( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )))) + (UOPS_RETIRED.RETIRE_SLOTS / (4 * (( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )))) )", + "MetricGroup": "TopdownL1_SMT", + "MetricName": "Backend_Bound_SMT", + "PublicDescription": "This category represents fraction of slots where no uops are being delivered due to a lack of required resources for accepting new uops in the Backend. Backend is the portion of the processor core where the out-of-order scheduler dispatches ready uops into their respective execution units; and once completed these uops get retired according to program order. For example; stalls due to data-cache misses or stalls due to the divider unit being overloaded are both categorized under Backend Bound. Backend Bound is further divided into two main categories: Memory Bound and Core Bound. SMT version; use when SMT is enabled and measuring per logical CPU." + }, + { + "BriefDescription": "This category represents fraction of slots utilized by useful work i.e. issued uops that eventually get retired", + "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / (4 * cycles)", + "MetricGroup": "TopdownL1", + "MetricName": "Retiring", + "PublicDescription": "This category represents fraction of slots utilized by useful work i.e. issued uops that eventually get retired. Ideally; all pipeline slots would be attributed to the Retiring category. Retiring of 100% would indicate the maximum 4 uops retired per cycle has been achieved. Maximizing Retiring typically increases the Instruction-Per-Cycle metric. Note that a high Retiring value does not necessary mean there is no room for more performance. For example; Microcode assists are categorized under Retiring. They hurt performance and can often be avoided. " + }, + { + "BriefDescription": "This category represents fraction of slots utilized by useful work i.e. issued uops that eventually get retired. SMT version; use when SMT is enabled and measuring per logical CPU.", + "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / (4 * (( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )))", + "MetricGroup": "TopdownL1_SMT", + "MetricName": "Retiring_SMT", + "PublicDescription": "This category represents fraction of slots utilized by useful work i.e. issued uops that eventually get retired. Ideally; all pipeline slots would be attributed to the Retiring category. Retiring of 100% would indicate the maximum 4 uops retired per cycle has been achieved. Maximizing Retiring typically increases the Instruction-Per-Cycle metric. Note that a high Retiring value does not necessary mean there is no room for more performance. For example; Microcode assists are categorized under Retiring. They hurt performance and can often be avoided. SMT version; use when SMT is enabled and measuring per logical CPU." + }, + { + "BriefDescription": "Instructions Per Cycle (per Logical Processor)", + "MetricExpr": "INST_RETIRED.ANY / CPU_CLK_UNHALTED.THREAD", + "MetricGroup": "TopDownL1", + "MetricName": "IPC" + }, + { + "BriefDescription": "Uops Per Instruction", + "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / INST_RETIRED.ANY", + "MetricGroup": "Pipeline;Retire", + "MetricName": "UPI" + }, + { + "BriefDescription": "Instruction per taken branch", + "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.NEAR_TAKEN", + "MetricGroup": "Branches;Fetch_BW;PGO", + "MetricName": "IpTB" + }, + { + "BriefDescription": "Branch instructions per taken branch. ", + "MetricExpr": "BR_INST_RETIRED.ALL_BRANCHES / BR_INST_RETIRED.NEAR_TAKEN", + "MetricGroup": "Branches;PGO", + "MetricName": "BpTB" + }, + { + "BriefDescription": "Rough Estimation of fraction of fetched lines bytes that were likely (includes speculatively fetches) consumed by program instructions", + "MetricExpr": "min( 1 , UOPS_ISSUED.ANY / ( (UOPS_RETIRED.RETIRE_SLOTS / INST_RETIRED.ANY) * 32 * ( ICACHE.HIT + ICACHE.MISSES ) / 4 ) )", + "MetricGroup": "PGO;IcMiss", + "MetricName": "IFetch_Line_Utilization" + }, + { + "BriefDescription": "Fraction of Uops delivered by the DSB (aka Decoded ICache; or Uop Cache)", + "MetricExpr": "IDQ.DSB_UOPS / (( IDQ.DSB_UOPS + LSD.UOPS + IDQ.MITE_UOPS + IDQ.MS_UOPS ) )", + "MetricGroup": "DSB;Fetch_BW", + "MetricName": "DSB_Coverage" + }, + { + "BriefDescription": "Cycles Per Instruction (per Logical Processor)", + "MetricExpr": "1 / (INST_RETIRED.ANY / cycles)", + "MetricGroup": "Pipeline;Summary", + "MetricName": "CPI" + }, + { + "BriefDescription": "Per-Logical Processor actual clocks when the Logical Processor is active.", + "MetricExpr": "CPU_CLK_UNHALTED.THREAD", + "MetricGroup": "Summary", + "MetricName": "CLKS" + }, + { + "BriefDescription": "Total issue-pipeline slots (per-Physical Core)", + "MetricExpr": "4 * cycles", + "MetricGroup": "TopDownL1", + "MetricName": "SLOTS" + }, + { + "BriefDescription": "Total issue-pipeline slots (per-Physical Core)", + "MetricExpr": "4 * (( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))", + "MetricGroup": "TopDownL1_SMT", + "MetricName": "SLOTS_SMT" + }, + { + "BriefDescription": "Instructions per Load (lower number means higher occurance rate)", + "MetricExpr": "INST_RETIRED.ANY / MEM_UOPS_RETIRED.ALL_LOADS", + "MetricGroup": "Instruction_Type", + "MetricName": "IpL" + }, + { + "BriefDescription": "Instructions per Store (lower number means higher occurance rate)", + "MetricExpr": "INST_RETIRED.ANY / MEM_UOPS_RETIRED.ALL_STORES", + "MetricGroup": "Instruction_Type", + "MetricName": "IpS" + }, + { + "BriefDescription": "Instructions per Branch (lower number means higher occurance rate)", + "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.ALL_BRANCHES", + "MetricGroup": "Branches;Instruction_Type", + "MetricName": "IpB" + }, + { + "BriefDescription": "Instruction per (near) call (lower number means higher occurance rate)", + "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.NEAR_CALL", + "MetricGroup": "Branches", + "MetricName": "IpCall" + }, + { + "BriefDescription": "Total number of retired Instructions", + "MetricExpr": "INST_RETIRED.ANY", + "MetricGroup": "Summary", + "MetricName": "Instructions" + }, + { + "BriefDescription": "Instructions Per Cycle (per physical core)", + "MetricExpr": "INST_RETIRED.ANY / cycles", + "MetricGroup": "SMT", + "MetricName": "CoreIPC" + }, + { + "BriefDescription": "Instructions Per Cycle (per physical core)", + "MetricExpr": "INST_RETIRED.ANY / (( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))", + "MetricGroup": "SMT", + "MetricName": "CoreIPC_SMT" + }, + { + "BriefDescription": "Floating Point Operations Per Cycle", + "MetricExpr": "(( 1 * ( FP_COMP_OPS_EXE.SSE_SCALAR_SINGLE + FP_COMP_OPS_EXE.SSE_SCALAR_DOUBLE ) + 2 * FP_COMP_OPS_EXE.SSE_PACKED_DOUBLE + 4 * ( FP_COMP_OPS_EXE.SSE_PACKED_SINGLE + SIMD_FP_256.PACKED_DOUBLE ) + 8 * SIMD_FP_256.PACKED_SINGLE )) / cycles", + "MetricGroup": "FLOPS", + "MetricName": "FLOPc" + }, + { + "BriefDescription": "Floating Point Operations Per Cycle", + "MetricExpr": "(( 1 * ( FP_COMP_OPS_EXE.SSE_SCALAR_SINGLE + FP_COMP_OPS_EXE.SSE_SCALAR_DOUBLE ) + 2 * FP_COMP_OPS_EXE.SSE_PACKED_DOUBLE + 4 * ( FP_COMP_OPS_EXE.SSE_PACKED_SINGLE + SIMD_FP_256.PACKED_DOUBLE ) + 8 * SIMD_FP_256.PACKED_SINGLE )) / (( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))", + "MetricGroup": "FLOPS_SMT", + "MetricName": "FLOPc_SMT" + }, + { + "BriefDescription": "Instruction-Level-Parallelism (average number of uops executed when there is at least 1 uop executed)", + "MetricExpr": "UOPS_EXECUTED.THREAD / (( cpu@UOPS_EXECUTED.CORE\\,cmask\\=1@ / 2 ) if #SMT_on else UOPS_EXECUTED.CYCLES_GE_1_UOP_EXEC)", + "MetricGroup": "Pipeline", + "MetricName": "ILP" + }, + { + "BriefDescription": "Number of Instructions per non-speculative Branch Misprediction (JEClear)", + "MetricExpr": "INST_RETIRED.ANY / BR_MISP_RETIRED.ALL_BRANCHES", + "MetricGroup": "BrMispredicts", + "MetricName": "IpMispredict" + }, + { + "BriefDescription": "Core actual clocks when any Logical Processor is active on the Physical Core", + "MetricExpr": "( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )", + "MetricGroup": "SMT", + "MetricName": "CORE_CLKS" + }, + { + "BriefDescription": "Actual Average Latency for L1 data-cache miss demand loads (in core cycles)", + "MetricExpr": "L1D_PEND_MISS.PENDING / ( MEM_LOAD_UOPS_RETIRED.L1_MISS + mem_load_uops_retired.hit_lfb )", + "MetricGroup": "Memory_Bound;Memory_Lat", + "MetricName": "Load_Miss_Real_Latency" + }, + { + "BriefDescription": "Memory-Level-Parallelism (average number of L1 miss demand load when there is at least one such miss. Per-Logical Processor)", + "MetricExpr": "L1D_PEND_MISS.PENDING / L1D_PEND_MISS.PENDING_CYCLES", + "MetricGroup": "Memory_Bound;Memory_BW", + "MetricName": "MLP" + }, + { + "BriefDescription": "Utilization of the core's Page Walker(s) serving STLB misses triggered by instruction/Load/Store accesses", + "MetricExpr": "( ITLB_MISSES.WALK_DURATION + DTLB_LOAD_MISSES.WALK_DURATION + DTLB_STORE_MISSES.WALK_DURATION ) / cycles", + "MetricGroup": "TLB", + "MetricName": "Page_Walks_Utilization" + }, + { + "BriefDescription": "Utilization of the core's Page Walker(s) serving STLB misses triggered by instruction/Load/Store accesses", + "MetricExpr": "( ITLB_MISSES.WALK_DURATION + DTLB_LOAD_MISSES.WALK_DURATION + DTLB_STORE_MISSES.WALK_DURATION ) / (( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))", + "MetricGroup": "TLB_SMT", + "MetricName": "Page_Walks_Utilization_SMT" + }, + { + "BriefDescription": "Average data fill bandwidth to the L1 data cache [GB / sec]", + "MetricExpr": "64 * L1D.REPLACEMENT / 1000000000 / duration_time", + "MetricGroup": "Memory_BW", + "MetricName": "L1D_Cache_Fill_BW" + }, + { + "BriefDescription": "Average data fill bandwidth to the L2 cache [GB / sec]", + "MetricExpr": "64 * L2_LINES_IN.ALL / 1000000000 / duration_time", + "MetricGroup": "Memory_BW", + "MetricName": "L2_Cache_Fill_BW" + }, + { + "BriefDescription": "Average per-core data fill bandwidth to the L3 cache [GB / sec]", + "MetricExpr": "64 * LONGEST_LAT_CACHE.MISS / 1000000000 / duration_time", + "MetricGroup": "Memory_BW", + "MetricName": "L3_Cache_Fill_BW" + }, + { + "BriefDescription": "L1 cache true misses per kilo instruction for retired demand loads", + "MetricExpr": "1000 * MEM_LOAD_UOPS_RETIRED.L1_MISS / INST_RETIRED.ANY", + "MetricGroup": "Cache_Misses", + "MetricName": "L1MPKI" + }, + { + "BriefDescription": "L2 cache true misses per kilo instruction for retired demand loads", + "MetricExpr": "1000 * MEM_LOAD_UOPS_RETIRED.L2_MISS / INST_RETIRED.ANY", + "MetricGroup": "Cache_Misses", + "MetricName": "L2MPKI" + }, + { + "BriefDescription": "L2 cache misses per kilo instruction for all request types (including speculative)", + "MetricExpr": "1000 * MEM_LOAD_UOPS_RETIRED.L2_MISS / INST_RETIRED.ANY", + "MetricGroup": "Cache_Misses", + "MetricName": "L2MPKI_All" + }, + { + "BriefDescription": "L2 cache hits per kilo instruction for all request types (including speculative)", + "MetricExpr": "1000 * MEM_LOAD_UOPS_RETIRED.L2_MISS / INST_RETIRED.ANY", + "MetricGroup": "Cache_Misses", + "MetricName": "L2HPKI_All" + }, + { + "BriefDescription": "L3 cache true misses per kilo instruction for retired demand loads", + "MetricExpr": "1000 * MEM_LOAD_UOPS_RETIRED.LLC_MISS / INST_RETIRED.ANY", + "MetricGroup": "Cache_Misses", + "MetricName": "L3MPKI" + }, + { + "BriefDescription": "Average CPU Utilization", + "MetricExpr": "CPU_CLK_UNHALTED.REF_TSC / msr@tsc@", + "MetricGroup": "Summary", + "MetricName": "CPU_Utilization" + }, + { + "BriefDescription": "Giga Floating Point Operations Per Second", + "MetricExpr": "( (( 1 * ( FP_COMP_OPS_EXE.SSE_SCALAR_SINGLE + FP_COMP_OPS_EXE.SSE_SCALAR_DOUBLE ) + 2 * FP_COMP_OPS_EXE.SSE_PACKED_DOUBLE + 4 * ( FP_COMP_OPS_EXE.SSE_PACKED_SINGLE + SIMD_FP_256.PACKED_DOUBLE ) + 8 * SIMD_FP_256.PACKED_SINGLE )) / 1000000000 ) / duration_time", + "MetricGroup": "FLOPS;Summary", + "MetricName": "GFLOPs" + }, + { + "BriefDescription": "Average Frequency Utilization relative nominal frequency", + "MetricExpr": "CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC", + "MetricGroup": "Power", + "MetricName": "Turbo_Utilization" + }, + { + "BriefDescription": "Fraction of cycles where both hardware Logical Processors were active", + "MetricExpr": "1 - CPU_CLK_THREAD_UNHALTED.ONE_THREAD_ACTIVE / ( CPU_CLK_THREAD_UNHALTED.REF_XCLK_ANY / 2 ) if #SMT_on else 0", + "MetricGroup": "SMT;Summary", + "MetricName": "SMT_2T_Utilization" + }, + { + "BriefDescription": "Fraction of cycles spent in Kernel mode", + "MetricExpr": "CPU_CLK_UNHALTED.THREAD:k / CPU_CLK_UNHALTED.THREAD", + "MetricGroup": "Summary", + "MetricName": "Kernel_Utilization" + }, + { + "BriefDescription": "Average external Memory Bandwidth Use for reads and writes [GB / sec]", + "MetricExpr": "64 * ( arb@event\\=0x81\\,umask\\=0x1@ + arb@event\\=0x84\\,umask\\=0x1@ ) / 1000000 / duration_time / 1000", + "MetricGroup": "Memory_BW", + "MetricName": "DRAM_BW_Use" + }, + { + "BriefDescription": "C3 residency percent per core", + "MetricExpr": "(cstate_core@c3\\-residency@ / msr@tsc@) * 100", + "MetricGroup": "Power", + "MetricName": "C3_Core_Residency" + }, + { + "BriefDescription": "C6 residency percent per core", + "MetricExpr": "(cstate_core@c6\\-residency@ / msr@tsc@) * 100", + "MetricGroup": "Power", + "MetricName": "C6_Core_Residency" + }, + { + "BriefDescription": "C7 residency percent per core", + "MetricExpr": "(cstate_core@c7\\-residency@ / msr@tsc@) * 100", + "MetricGroup": "Power", + "MetricName": "C7_Core_Residency" + }, + { + "BriefDescription": "C2 residency percent per package", + "MetricExpr": "(cstate_pkg@c2\\-residency@ / msr@tsc@) * 100", + "MetricGroup": "Power", + "MetricName": "C2_Pkg_Residency" + }, + { + "BriefDescription": "C3 residency percent per package", + "MetricExpr": "(cstate_pkg@c3\\-residency@ / msr@tsc@) * 100", + "MetricGroup": "Power", + "MetricName": "C3_Pkg_Residency" + }, + { + "BriefDescription": "C6 residency percent per package", + "MetricExpr": "(cstate_pkg@c6\\-residency@ / msr@tsc@) * 100", + "MetricGroup": "Power", + "MetricName": "C6_Pkg_Residency" + }, + { + "BriefDescription": "C7 residency percent per package", + "MetricExpr": "(cstate_pkg@c7\\-residency@ / msr@tsc@) * 100", + "MetricGroup": "Power", + "MetricName": "C7_Pkg_Residency" + } +] diff --git a/tools/perf/pmu-events/arch/x86/ivybridge/memory.json b/tools/perf/pmu-events/arch/x86/ivybridge/memory.json new file mode 100644 index 000000000..a74d54f56 --- /dev/null +++ b/tools/perf/pmu-events/arch/x86/ivybridge/memory.json @@ -0,0 +1,236 @@ +[ + { + "PublicDescription": "Speculative cache-line split load uops dispatched to L1D.", + "EventCode": "0x05", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "MISALIGN_MEM_REF.LOADS", + "SampleAfterValue": "2000003", + "BriefDescription": "Speculative cache line split load uops dispatched to L1 cache", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Speculative cache-line split Store-address uops dispatched to L1D.", + "EventCode": "0x05", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "MISALIGN_MEM_REF.STORES", + "SampleAfterValue": "2000003", + "BriefDescription": "Speculative cache line split STA uops dispatched to L1 cache", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xBE", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "PAGE_WALKS.LLC_MISS", + "SampleAfterValue": "100003", + "BriefDescription": "Number of any page walk that had a miss in LLC.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xC3", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "MACHINE_CLEARS.MEMORY_ORDERING", + "SampleAfterValue": "100003", + "BriefDescription": "Counts the number of machine clears due to memory order conflicts.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PEBS": "2", + "PublicDescription": "Loads with latency value being above 4.", + "EventCode": "0xCD", + "MSRValue": "0x4", + "Counter": "3", + "UMask": "0x1", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_4", + "MSRIndex": "0x3F6", + "SampleAfterValue": "100003", + "BriefDescription": "Loads with latency value being above 4", + "TakenAlone": "1", + "CounterHTOff": "3" + }, + { + "PEBS": "2", + "PublicDescription": "Loads with latency value being above 8.", + "EventCode": "0xCD", + "MSRValue": "0x8", + "Counter": "3", + "UMask": "0x1", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_8", + "MSRIndex": "0x3F6", + "SampleAfterValue": "50021", + "BriefDescription": "Loads with latency value being above 8", + "TakenAlone": "1", + "CounterHTOff": "3" + }, + { + "PEBS": "2", + "PublicDescription": "Loads with latency value being above 16.", + "EventCode": "0xCD", + "MSRValue": "0x10", + "Counter": "3", + "UMask": "0x1", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_16", + "MSRIndex": "0x3F6", + "SampleAfterValue": "20011", + "BriefDescription": "Loads with latency value being above 16", + "TakenAlone": "1", + "CounterHTOff": "3" + }, + { + "PEBS": "2", + "PublicDescription": "Loads with latency value being above 32.", + "EventCode": "0xCD", + "MSRValue": "0x20", + "Counter": "3", + "UMask": "0x1", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_32", + "MSRIndex": "0x3F6", + "SampleAfterValue": "100007", + "BriefDescription": "Loads with latency value being above 32", + "TakenAlone": "1", + "CounterHTOff": "3" + }, + { + "PEBS": "2", + "PublicDescription": "Loads with latency value being above 64.", + "EventCode": "0xCD", + "MSRValue": "0x40", + "Counter": "3", + "UMask": "0x1", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_64", + "MSRIndex": "0x3F6", + "SampleAfterValue": "2003", + "BriefDescription": "Loads with latency value being above 64", + "TakenAlone": "1", + "CounterHTOff": "3" + }, + { + "PEBS": "2", + "PublicDescription": "Loads with latency value being above 128.", + "EventCode": "0xCD", + "MSRValue": "0x80", + "Counter": "3", + "UMask": "0x1", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_128", + "MSRIndex": "0x3F6", + "SampleAfterValue": "1009", + "BriefDescription": "Loads with latency value being above 128", + "TakenAlone": "1", + "CounterHTOff": "3" + }, + { + "PEBS": "2", + "PublicDescription": "Loads with latency value being above 256.", + "EventCode": "0xCD", + "MSRValue": "0x100", + "Counter": "3", + "UMask": "0x1", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_256", + "MSRIndex": "0x3F6", + "SampleAfterValue": "503", + "BriefDescription": "Loads with latency value being above 256", + "TakenAlone": "1", + "CounterHTOff": "3" + }, + { + "PEBS": "2", + "PublicDescription": "Loads with latency value being above 512.", + "EventCode": "0xCD", + "MSRValue": "0x200", + "Counter": "3", + "UMask": "0x1", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_512", + "MSRIndex": "0x3F6", + "SampleAfterValue": "101", + "BriefDescription": "Loads with latency value being above 512", + "TakenAlone": "1", + "CounterHTOff": "3" + }, + { + "PEBS": "2", + "EventCode": "0xCD", + "Counter": "3", + "UMask": "0x2", + "EventName": "MEM_TRANS_RETIRED.PRECISE_STORE", + "SampleAfterValue": "2000003", + "BriefDescription": "Sample stores and collect precise store operation via PEBS record. PMC3 only.", + "PRECISE_STORE": "1", + "TakenAlone": "1", + "CounterHTOff": "3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x300400244", + "Counter": "0,1,2,3", + "UMask": "0x1", + "Offcore": "1", + "EventName": "OFFCORE_RESPONSE.ALL_CODE_RD.LLC_MISS.DRAM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts all demand & prefetch code reads that miss the LLC and the data returned from dram", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x300400091", + "Counter": "0,1,2,3", + "UMask": "0x1", + "Offcore": "1", + "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_MISS.DRAM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts all demand & prefetch data reads that miss the LLC and the data returned from dram", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x3004003f7", + "Counter": "0,1,2,3", + "UMask": "0x1", + "Offcore": "1", + "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_MISS.DRAM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) that miss the LLC and the data returned from dram", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x300400004", + "Counter": "0,1,2,3", + "UMask": "0x1", + "Offcore": "1", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_MISS.DRAM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts demand code reads that miss the LLC and the data returned from dram", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x300400001", + "Counter": "0,1,2,3", + "UMask": "0x1", + "Offcore": "1", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_MISS.DRAM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts demand data reads that miss the LLC and the data returned from dram", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xB7, 0xBB", + "MSRValue": "0x6004001b3", + "Counter": "0,1,2,3", + "UMask": "0x1", + "Offcore": "1", + "EventName": "OFFCORE_RESPONSE.DATA_IN_SOCKET.LLC_MISS.LOCAL_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "SampleAfterValue": "100003", + "BriefDescription": "Counts LLC replacements", + "CounterHTOff": "0,1,2,3" + } +]
\ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/ivybridge/other.json b/tools/perf/pmu-events/arch/x86/ivybridge/other.json new file mode 100644 index 000000000..4eb83ee40 --- /dev/null +++ b/tools/perf/pmu-events/arch/x86/ivybridge/other.json @@ -0,0 +1,44 @@ +[ + { + "PublicDescription": "Unhalted core cycles when the thread is in ring 0.", + "EventCode": "0x5C", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "CPL_CYCLES.RING0", + "SampleAfterValue": "2000003", + "BriefDescription": "Unhalted core cycles when the thread is in ring 0", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Number of intervals between processor halts while thread is in ring 0.", + "EventCode": "0x5C", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EdgeDetect": "1", + "EventName": "CPL_CYCLES.RING0_TRANS", + "SampleAfterValue": "100007", + "BriefDescription": "Number of intervals between processor halts while thread is in ring 0", + "CounterMask": "1", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Unhalted core cycles when the thread is not in ring 0.", + "EventCode": "0x5C", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "CPL_CYCLES.RING123", + "SampleAfterValue": "2000003", + "BriefDescription": "Unhalted core cycles when thread is in rings 1, 2, or 3", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Cycles in which the L1D and L2 are locked, due to a UC lock or split lock.", + "EventCode": "0x63", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "LOCK_CYCLES.SPLIT_LOCK_UC_LOCK_DURATION", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles when L1 and L2 are locked due to UC or split lock", + "CounterHTOff": "0,1,2,3,4,5,6,7" + } +]
\ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/ivybridge/pipeline.json b/tools/perf/pmu-events/arch/x86/ivybridge/pipeline.json new file mode 100644 index 000000000..2a0aad91d --- /dev/null +++ b/tools/perf/pmu-events/arch/x86/ivybridge/pipeline.json @@ -0,0 +1,1305 @@ +[ + { + "Counter": "Fixed counter 0", + "UMask": "0x1", + "EventName": "INST_RETIRED.ANY", + "SampleAfterValue": "2000003", + "BriefDescription": "Instructions retired from execution.", + "CounterHTOff": "Fixed counter 0" + }, + { + "Counter": "Fixed counter 1", + "UMask": "0x2", + "EventName": "CPU_CLK_UNHALTED.THREAD", + "SampleAfterValue": "2000003", + "BriefDescription": "Core cycles when the thread is not in halt state.", + "CounterHTOff": "Fixed counter 1" + }, + { + "PublicDescription": "Core cycles when at least one thread on the physical core is not in halt state.", + "Counter": "Fixed counter 1", + "UMask": "0x2", + "AnyThread": "1", + "EventName": "CPU_CLK_UNHALTED.THREAD_ANY", + "SampleAfterValue": "2000003", + "BriefDescription": "Core cycles when at least one thread on the physical core is not in halt state", + "CounterHTOff": "Fixed counter 1" + }, + { + "Counter": "Fixed counter 2", + "UMask": "0x3", + "EventName": "CPU_CLK_UNHALTED.REF_TSC", + "SampleAfterValue": "2000003", + "BriefDescription": "Reference cycles when the core is not in halt state.", + "CounterHTOff": "Fixed counter 2" + }, + { + "PublicDescription": "Loads blocked by overlapping with store buffer that cannot be forwarded.", + "EventCode": "0x03", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "LD_BLOCKS.STORE_FORWARD", + "SampleAfterValue": "100003", + "BriefDescription": "Cases when loads get true Block-on-Store blocking code preventing store forwarding", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "The number of times that split load operations are temporarily blocked because all resources for handling the split accesses are in use.", + "EventCode": "0x03", + "Counter": "0,1,2,3", + "UMask": "0x8", + "EventName": "LD_BLOCKS.NO_SR", + "SampleAfterValue": "100003", + "BriefDescription": "This event counts the number of times that split load operations are temporarily blocked because all resources for handling the split accesses are in use.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "False dependencies in MOB due to partial compare on address.", + "EventCode": "0x07", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "LD_BLOCKS_PARTIAL.ADDRESS_ALIAS", + "SampleAfterValue": "100003", + "BriefDescription": "False dependencies in MOB due to partial compare on address", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x0D", + "Counter": "0,1,2,3", + "UMask": "0x3", + "EventName": "INT_MISC.RECOVERY_CYCLES", + "SampleAfterValue": "2000003", + "BriefDescription": "Number of cycles waiting for the checkpoints in Resource Allocation Table (RAT) to be recovered after Nuke due to all other cases except JEClear (e.g. whenever a ucode assist is needed like SSE exception, memory disambiguation, etc.)", + "CounterMask": "1", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x0D", + "Counter": "0,1,2,3", + "UMask": "0x3", + "EdgeDetect": "1", + "EventName": "INT_MISC.RECOVERY_STALLS_COUNT", + "SampleAfterValue": "2000003", + "BriefDescription": "Number of occurences waiting for the checkpoints in Resource Allocation Table (RAT) to be recovered after Nuke due to all other cases except JEClear (e.g. whenever a ucode assist is needed like SSE exception, memory disambiguation, etc.)", + "CounterMask": "1", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x0D", + "Counter": "0,1,2,3", + "UMask": "0x3", + "AnyThread": "1", + "EventName": "INT_MISC.RECOVERY_CYCLES_ANY", + "SampleAfterValue": "2000003", + "BriefDescription": "Core cycles the allocator was stalled due to recovery from earlier clear event for any thread running on the physical core (e.g. misprediction or memory nuke).", + "CounterMask": "1", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Increments each cycle the # of Uops issued by the RAT to RS. Set Cmask = 1, Inv = 1, Any= 1to count stalled cycles of this core.", + "EventCode": "0x0E", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "UOPS_ISSUED.ANY", + "SampleAfterValue": "2000003", + "BriefDescription": "Uops that Resource Allocation Table (RAT) issues to Reservation Station (RS)", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Cycles when Resource Allocation Table (RAT) does not issue Uops to Reservation Station (RS) for the thread.", + "EventCode": "0x0E", + "Invert": "1", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "UOPS_ISSUED.STALL_CYCLES", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles when Resource Allocation Table (RAT) does not issue Uops to Reservation Station (RS) for the thread", + "CounterMask": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "PublicDescription": "Cycles when Resource Allocation Table (RAT) does not issue Uops to Reservation Station (RS) for all threads.", + "EventCode": "0x0E", + "Invert": "1", + "Counter": "0,1,2,3", + "UMask": "0x1", + "AnyThread": "1", + "EventName": "UOPS_ISSUED.CORE_STALL_CYCLES", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles when Resource Allocation Table (RAT) does not issue Uops to Reservation Station (RS) for all threads", + "CounterMask": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "PublicDescription": "Number of flags-merge uops allocated. Such uops adds delay.", + "EventCode": "0x0E", + "Counter": "0,1,2,3", + "UMask": "0x10", + "EventName": "UOPS_ISSUED.FLAGS_MERGE", + "SampleAfterValue": "2000003", + "BriefDescription": "Number of flags-merge uops being allocated.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Number of slow LEA or similar uops allocated. Such uop has 3 sources (e.g. 2 sources + immediate) regardless if as a result of LEA instruction or not.", + "EventCode": "0x0E", + "Counter": "0,1,2,3", + "UMask": "0x20", + "EventName": "UOPS_ISSUED.SLOW_LEA", + "SampleAfterValue": "2000003", + "BriefDescription": "Number of slow LEA uops being allocated. A uop is generally considered SlowLea if it has 3 sources (e.g. 2 sources + immediate) regardless if as a result of LEA instruction or not.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Number of multiply packed/scalar single precision uops allocated.", + "EventCode": "0x0E", + "Counter": "0,1,2,3", + "UMask": "0x40", + "EventName": "UOPS_ISSUED.SINGLE_MUL", + "SampleAfterValue": "2000003", + "BriefDescription": "Number of Multiply packed/scalar single precision uops allocated", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Cycles that the divider is active, includes INT and FP. Set 'edge =1, cmask=1' to count the number of divides.", + "EventCode": "0x14", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "ARITH.FPU_DIV_ACTIVE", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles when divider is busy executing divide operations", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Divide operations executed.", + "EventCode": "0x14", + "Counter": "0,1,2,3", + "UMask": "0x4", + "EdgeDetect": "1", + "EventName": "ARITH.FPU_DIV", + "SampleAfterValue": "100003", + "BriefDescription": "Divide operations executed", + "CounterMask": "1", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Counts the number of thread cycles while the thread is not in a halt state. The thread enters the halt state when it is running the HLT instruction. The core frequency may change from time to time due to power or thermal throttling.", + "EventCode": "0x3C", + "Counter": "0,1,2,3", + "UMask": "0x0", + "EventName": "CPU_CLK_UNHALTED.THREAD_P", + "SampleAfterValue": "2000003", + "BriefDescription": "Thread cycles when thread is not in halt state", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Core cycles when at least one thread on the physical core is not in halt state.", + "EventCode": "0x3C", + "Counter": "0,1,2,3", + "UMask": "0x0", + "AnyThread": "1", + "EventName": "CPU_CLK_UNHALTED.THREAD_P_ANY", + "SampleAfterValue": "2000003", + "BriefDescription": "Core cycles when at least one thread on the physical core is not in halt state", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Increments at the frequency of XCLK (100 MHz) when not halted.", + "EventCode": "0x3C", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "CPU_CLK_THREAD_UNHALTED.REF_XCLK", + "SampleAfterValue": "2000003", + "BriefDescription": "Reference cycles when the thread is unhalted (counts at 100 MHz rate)", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x3C", + "Counter": "0,1,2,3", + "UMask": "0x1", + "AnyThread": "1", + "EventName": "CPU_CLK_THREAD_UNHALTED.REF_XCLK_ANY", + "SampleAfterValue": "2000003", + "BriefDescription": "Reference cycles when the at least one thread on the physical core is unhalted. (counts at 100 MHz rate)", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Reference cycles when the thread is unhalted. (counts at 100 MHz rate)", + "EventCode": "0x3C", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "CPU_CLK_UNHALTED.REF_XCLK", + "SampleAfterValue": "2000003", + "BriefDescription": "Reference cycles when the thread is unhalted (counts at 100 MHz rate)", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x3C", + "Counter": "0,1,2,3", + "UMask": "0x1", + "AnyThread": "1", + "EventName": "CPU_CLK_UNHALTED.REF_XCLK_ANY", + "SampleAfterValue": "2000003", + "BriefDescription": "Reference cycles when the at least one thread on the physical core is unhalted. (counts at 100 MHz rate)", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x3C", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "CPU_CLK_THREAD_UNHALTED.ONE_THREAD_ACTIVE", + "SampleAfterValue": "2000003", + "BriefDescription": "Count XClk pulses when this thread is unhalted and the other is halted.", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0x3C", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE", + "SampleAfterValue": "2000003", + "BriefDescription": "Count XClk pulses when this thread is unhalted and the other thread is halted.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Non-SW-prefetch load dispatches that hit fill buffer allocated for S/W prefetch.", + "EventCode": "0x4C", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "LOAD_HIT_PRE.SW_PF", + "SampleAfterValue": "100003", + "BriefDescription": "Not software-prefetch load dispatches that hit FB allocated for software prefetch", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Non-SW-prefetch load dispatches that hit fill buffer allocated for H/W prefetch.", + "EventCode": "0x4C", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "LOAD_HIT_PRE.HW_PF", + "SampleAfterValue": "100003", + "BriefDescription": "Not software-prefetch load dispatches that hit FB allocated for hardware prefetch", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x58", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "MOVE_ELIMINATION.INT_ELIMINATED", + "SampleAfterValue": "1000003", + "BriefDescription": "Number of integer Move Elimination candidate uops that were eliminated.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x58", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "MOVE_ELIMINATION.SIMD_ELIMINATED", + "SampleAfterValue": "1000003", + "BriefDescription": "Number of SIMD Move Elimination candidate uops that were eliminated.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x58", + "Counter": "0,1,2,3", + "UMask": "0x4", + "EventName": "MOVE_ELIMINATION.INT_NOT_ELIMINATED", + "SampleAfterValue": "1000003", + "BriefDescription": "Number of integer Move Elimination candidate uops that were not eliminated.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x58", + "Counter": "0,1,2,3", + "UMask": "0x8", + "EventName": "MOVE_ELIMINATION.SIMD_NOT_ELIMINATED", + "SampleAfterValue": "1000003", + "BriefDescription": "Number of SIMD Move Elimination candidate uops that were not eliminated.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Cycles the RS is empty for the thread.", + "EventCode": "0x5E", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "RS_EVENTS.EMPTY_CYCLES", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles when Reservation Station (RS) is empty for the thread", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x5E", + "Invert": "1", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EdgeDetect": "1", + "EventName": "RS_EVENTS.EMPTY_END", + "SampleAfterValue": "200003", + "BriefDescription": "Counts end of periods where the Reservation Station (RS) was empty. Could be useful to precisely locate Frontend Latency Bound issues.", + "CounterMask": "1", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x87", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "ILD_STALL.LCP", + "SampleAfterValue": "2000003", + "BriefDescription": "Stalls caused by changing prefix length of the instruction.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Stall cycles due to IQ is full.", + "EventCode": "0x87", + "Counter": "0,1,2,3", + "UMask": "0x4", + "EventName": "ILD_STALL.IQ_FULL", + "SampleAfterValue": "2000003", + "BriefDescription": "Stall cycles because IQ is full", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Not taken macro-conditional branches.", + "EventCode": "0x88", + "Counter": "0,1,2,3", + "UMask": "0x41", + "EventName": "BR_INST_EXEC.NONTAKEN_CONDITIONAL", + "SampleAfterValue": "200003", + "BriefDescription": "Not taken macro-conditional branches", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Taken speculative and retired macro-conditional branches.", + "EventCode": "0x88", + "Counter": "0,1,2,3", + "UMask": "0x81", + "EventName": "BR_INST_EXEC.TAKEN_CONDITIONAL", + "SampleAfterValue": "200003", + "BriefDescription": "Taken speculative and retired macro-conditional branches", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Taken speculative and retired macro-conditional branch instructions excluding calls and indirects.", + "EventCode": "0x88", + "Counter": "0,1,2,3", + "UMask": "0x82", + "EventName": "BR_INST_EXEC.TAKEN_DIRECT_JUMP", + "SampleAfterValue": "200003", + "BriefDescription": "Taken speculative and retired macro-conditional branch instructions excluding calls and indirects", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Taken speculative and retired indirect branches excluding calls and returns.", + "EventCode": "0x88", + "Counter": "0,1,2,3", + "UMask": "0x84", + "EventName": "BR_INST_EXEC.TAKEN_INDIRECT_JUMP_NON_CALL_RET", + "SampleAfterValue": "200003", + "BriefDescription": "Taken speculative and retired indirect branches excluding calls and returns", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Taken speculative and retired indirect branches with return mnemonic.", + "EventCode": "0x88", + "Counter": "0,1,2,3", + "UMask": "0x88", + "EventName": "BR_INST_EXEC.TAKEN_INDIRECT_NEAR_RETURN", + "SampleAfterValue": "200003", + "BriefDescription": "Taken speculative and retired indirect branches with return mnemonic", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Taken speculative and retired direct near calls.", + "EventCode": "0x88", + "Counter": "0,1,2,3", + "UMask": "0x90", + "EventName": "BR_INST_EXEC.TAKEN_DIRECT_NEAR_CALL", + "SampleAfterValue": "200003", + "BriefDescription": "Taken speculative and retired direct near calls", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Taken speculative and retired indirect calls.", + "EventCode": "0x88", + "Counter": "0,1,2,3", + "UMask": "0xa0", + "EventName": "BR_INST_EXEC.TAKEN_INDIRECT_NEAR_CALL", + "SampleAfterValue": "200003", + "BriefDescription": "Taken speculative and retired indirect calls", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Speculative and retired macro-conditional branches.", + "EventCode": "0x88", + "Counter": "0,1,2,3", + "UMask": "0xc1", + "EventName": "BR_INST_EXEC.ALL_CONDITIONAL", + "SampleAfterValue": "200003", + "BriefDescription": "Speculative and retired macro-conditional branches", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Speculative and retired macro-unconditional branches excluding calls and indirects.", + "EventCode": "0x88", + "Counter": "0,1,2,3", + "UMask": "0xc2", + "EventName": "BR_INST_EXEC.ALL_DIRECT_JMP", + "SampleAfterValue": "200003", + "BriefDescription": "Speculative and retired macro-unconditional branches excluding calls and indirects", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Speculative and retired indirect branches excluding calls and returns.", + "EventCode": "0x88", + "Counter": "0,1,2,3", + "UMask": "0xc4", + "EventName": "BR_INST_EXEC.ALL_INDIRECT_JUMP_NON_CALL_RET", + "SampleAfterValue": "200003", + "BriefDescription": "Speculative and retired indirect branches excluding calls and returns", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x88", + "Counter": "0,1,2,3", + "UMask": "0xc8", + "EventName": "BR_INST_EXEC.ALL_INDIRECT_NEAR_RETURN", + "SampleAfterValue": "200003", + "BriefDescription": "Speculative and retired indirect return branches.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Speculative and retired direct near calls.", + "EventCode": "0x88", + "Counter": "0,1,2,3", + "UMask": "0xd0", + "EventName": "BR_INST_EXEC.ALL_DIRECT_NEAR_CALL", + "SampleAfterValue": "200003", + "BriefDescription": "Speculative and retired direct near calls", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Counts all near executed branches (not necessarily retired).", + "EventCode": "0x88", + "Counter": "0,1,2,3", + "UMask": "0xff", + "EventName": "BR_INST_EXEC.ALL_BRANCHES", + "SampleAfterValue": "200003", + "BriefDescription": "Speculative and retired branches", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Not taken speculative and retired mispredicted macro conditional branches.", + "EventCode": "0x89", + "Counter": "0,1,2,3", + "UMask": "0x41", + "EventName": "BR_MISP_EXEC.NONTAKEN_CONDITIONAL", + "SampleAfterValue": "200003", + "BriefDescription": "Not taken speculative and retired mispredicted macro conditional branches", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Taken speculative and retired mispredicted macro conditional branches.", + "EventCode": "0x89", + "Counter": "0,1,2,3", + "UMask": "0x81", + "EventName": "BR_MISP_EXEC.TAKEN_CONDITIONAL", + "SampleAfterValue": "200003", + "BriefDescription": "Taken speculative and retired mispredicted macro conditional branches", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Taken speculative and retired mispredicted indirect branches excluding calls and returns.", + "EventCode": "0x89", + "Counter": "0,1,2,3", + "UMask": "0x84", + "EventName": "BR_MISP_EXEC.TAKEN_INDIRECT_JUMP_NON_CALL_RET", + "SampleAfterValue": "200003", + "BriefDescription": "Taken speculative and retired mispredicted indirect branches excluding calls and returns", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Taken speculative and retired mispredicted indirect branches with return mnemonic.", + "EventCode": "0x89", + "Counter": "0,1,2,3", + "UMask": "0x88", + "EventName": "BR_MISP_EXEC.TAKEN_RETURN_NEAR", + "SampleAfterValue": "200003", + "BriefDescription": "Taken speculative and retired mispredicted indirect branches with return mnemonic", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Taken speculative and retired mispredicted indirect calls.", + "EventCode": "0x89", + "Counter": "0,1,2,3", + "UMask": "0xa0", + "EventName": "BR_MISP_EXEC.TAKEN_INDIRECT_NEAR_CALL", + "SampleAfterValue": "200003", + "BriefDescription": "Taken speculative and retired mispredicted indirect calls", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Speculative and retired mispredicted macro conditional branches.", + "EventCode": "0x89", + "Counter": "0,1,2,3", + "UMask": "0xc1", + "EventName": "BR_MISP_EXEC.ALL_CONDITIONAL", + "SampleAfterValue": "200003", + "BriefDescription": "Speculative and retired mispredicted macro conditional branches", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Mispredicted indirect branches excluding calls and returns.", + "EventCode": "0x89", + "Counter": "0,1,2,3", + "UMask": "0xc4", + "EventName": "BR_MISP_EXEC.ALL_INDIRECT_JUMP_NON_CALL_RET", + "SampleAfterValue": "200003", + "BriefDescription": "Mispredicted indirect branches excluding calls and returns", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Counts all near executed branches (not necessarily retired).", + "EventCode": "0x89", + "Counter": "0,1,2,3", + "UMask": "0xff", + "EventName": "BR_MISP_EXEC.ALL_BRANCHES", + "SampleAfterValue": "200003", + "BriefDescription": "Speculative and retired mispredicted macro conditional branches", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Cycles which a Uop is dispatched on port 0.", + "EventCode": "0xA1", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "UOPS_DISPATCHED_PORT.PORT_0", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles per thread when uops are dispatched to port 0", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Cycles per core when uops are dispatched to port 0.", + "EventCode": "0xA1", + "Counter": "0,1,2,3", + "UMask": "0x1", + "AnyThread": "1", + "EventName": "UOPS_DISPATCHED_PORT.PORT_0_CORE", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles per core when uops are dispatched to port 0", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Cycles which a Uop is dispatched on port 1.", + "EventCode": "0xA1", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "UOPS_DISPATCHED_PORT.PORT_1", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles per thread when uops are dispatched to port 1", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Cycles per core when uops are dispatched to port 1.", + "EventCode": "0xA1", + "Counter": "0,1,2,3", + "UMask": "0x2", + "AnyThread": "1", + "EventName": "UOPS_DISPATCHED_PORT.PORT_1_CORE", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles per core when uops are dispatched to port 1", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Cycles which a Uop is dispatched on port 2.", + "EventCode": "0xA1", + "Counter": "0,1,2,3", + "UMask": "0xc", + "EventName": "UOPS_DISPATCHED_PORT.PORT_2", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles per thread when load or STA uops are dispatched to port 2", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xA1", + "Counter": "0,1,2,3", + "UMask": "0xc", + "AnyThread": "1", + "EventName": "UOPS_DISPATCHED_PORT.PORT_2_CORE", + "SampleAfterValue": "2000003", + "BriefDescription": "Uops dispatched to port 2, loads and stores per core (speculative and retired).", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Cycles which a Uop is dispatched on port 3.", + "EventCode": "0xA1", + "Counter": "0,1,2,3", + "UMask": "0x30", + "EventName": "UOPS_DISPATCHED_PORT.PORT_3", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles per thread when load or STA uops are dispatched to port 3", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Cycles per core when load or STA uops are dispatched to port 3.", + "EventCode": "0xA1", + "Counter": "0,1,2,3", + "UMask": "0x30", + "AnyThread": "1", + "EventName": "UOPS_DISPATCHED_PORT.PORT_3_CORE", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles per core when load or STA uops are dispatched to port 3", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Cycles which a Uop is dispatched on port 4.", + "EventCode": "0xA1", + "Counter": "0,1,2,3", + "UMask": "0x40", + "EventName": "UOPS_DISPATCHED_PORT.PORT_4", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles per thread when uops are dispatched to port 4", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Cycles per core when uops are dispatched to port 4.", + "EventCode": "0xA1", + "Counter": "0,1,2,3", + "UMask": "0x40", + "AnyThread": "1", + "EventName": "UOPS_DISPATCHED_PORT.PORT_4_CORE", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles per core when uops are dispatched to port 4", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Cycles which a Uop is dispatched on port 5.", + "EventCode": "0xA1", + "Counter": "0,1,2,3", + "UMask": "0x80", + "EventName": "UOPS_DISPATCHED_PORT.PORT_5", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles per thread when uops are dispatched to port 5", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Cycles per core when uops are dispatched to port 5.", + "EventCode": "0xA1", + "Counter": "0,1,2,3", + "UMask": "0x80", + "AnyThread": "1", + "EventName": "UOPS_DISPATCHED_PORT.PORT_5_CORE", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles per core when uops are dispatched to port 5", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Cycles Allocation is stalled due to Resource Related reason.", + "EventCode": "0xA2", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "RESOURCE_STALLS.ANY", + "SampleAfterValue": "2000003", + "BriefDescription": "Resource-related stall cycles", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xA2", + "Counter": "0,1,2,3", + "UMask": "0x4", + "EventName": "RESOURCE_STALLS.RS", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles stalled due to no eligible RS entry available.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Cycles stalled due to no store buffers available (not including draining form sync).", + "EventCode": "0xA2", + "Counter": "0,1,2,3", + "UMask": "0x8", + "EventName": "RESOURCE_STALLS.SB", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles stalled due to no store buffers available. (not including draining form sync).", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xA2", + "Counter": "0,1,2,3", + "UMask": "0x10", + "EventName": "RESOURCE_STALLS.ROB", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles stalled due to re-order buffer full.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Cycles with pending L2 miss loads. Set AnyThread to count per core.", + "EventCode": "0xA3", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "CYCLE_ACTIVITY.CYCLES_L2_PENDING", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles with pending L2 cache miss loads.", + "CounterMask": "1", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xA3", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "CYCLE_ACTIVITY.CYCLES_L2_MISS", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles while L2 cache miss load* is outstanding.", + "CounterMask": "1", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Cycles with pending memory loads. Set AnyThread to count per core.", + "EventCode": "0xA3", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "CYCLE_ACTIVITY.CYCLES_LDM_PENDING", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles with pending memory loads.", + "CounterMask": "2", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xA3", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "CYCLE_ACTIVITY.CYCLES_MEM_ANY", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles while memory subsystem has an outstanding load.", + "CounterMask": "2", + "CounterHTOff": "0,1,2,3" + }, + { + "PublicDescription": "Total execution stalls.", + "EventCode": "0xA3", + "Counter": "0,1,2,3", + "UMask": "0x4", + "EventName": "CYCLE_ACTIVITY.CYCLES_NO_EXECUTE", + "SampleAfterValue": "2000003", + "BriefDescription": "This event increments by 1 for every cycle where there was no execute for this thread.", + "CounterMask": "4", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xA3", + "Counter": "0,1,2,3", + "UMask": "0x4", + "EventName": "CYCLE_ACTIVITY.STALLS_TOTAL", + "SampleAfterValue": "2000003", + "BriefDescription": "Total execution stalls.", + "CounterMask": "4", + "CounterHTOff": "0,1,2,3" + }, + { + "PublicDescription": "Number of loads missed L2.", + "EventCode": "0xA3", + "Counter": "0,1,2,3", + "UMask": "0x5", + "EventName": "CYCLE_ACTIVITY.STALLS_L2_PENDING", + "SampleAfterValue": "2000003", + "BriefDescription": "Execution stalls due to L2 cache misses.", + "CounterMask": "5", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xA3", + "Counter": "0,1,2,3", + "UMask": "0x5", + "EventName": "CYCLE_ACTIVITY.STALLS_L2_MISS", + "SampleAfterValue": "2000003", + "BriefDescription": "Execution stalls while L2 cache miss load* is outstanding.", + "CounterMask": "5", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xA3", + "Counter": "0,1,2,3", + "UMask": "0x6", + "EventName": "CYCLE_ACTIVITY.STALLS_LDM_PENDING", + "SampleAfterValue": "2000003", + "BriefDescription": "Execution stalls due to memory subsystem.", + "CounterMask": "6", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xA3", + "Counter": "0,1,2,3", + "UMask": "0x6", + "EventName": "CYCLE_ACTIVITY.STALLS_MEM_ANY", + "SampleAfterValue": "2000003", + "BriefDescription": "Execution stalls while memory subsystem has an outstanding load.", + "CounterMask": "6", + "CounterHTOff": "0,1,2,3" + }, + { + "PublicDescription": "Cycles with pending L1 cache miss loads. Set AnyThread to count per core.", + "EventCode": "0xA3", + "Counter": "2", + "UMask": "0x8", + "EventName": "CYCLE_ACTIVITY.CYCLES_L1D_PENDING", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles with pending L1 cache miss loads.", + "CounterMask": "8", + "CounterHTOff": "2" + }, + { + "EventCode": "0xA3", + "Counter": "2", + "UMask": "0x8", + "EventName": "CYCLE_ACTIVITY.CYCLES_L1D_MISS", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles while L1 cache miss demand load is outstanding.", + "CounterMask": "8", + "CounterHTOff": "2" + }, + { + "PublicDescription": "Execution stalls due to L1 data cache miss loads. Set Cmask=0CH.", + "EventCode": "0xA3", + "Counter": "2", + "UMask": "0xc", + "EventName": "CYCLE_ACTIVITY.STALLS_L1D_PENDING", + "SampleAfterValue": "2000003", + "BriefDescription": "Execution stalls due to L1 data cache misses", + "CounterMask": "12", + "CounterHTOff": "2" + }, + { + "EventCode": "0xA3", + "Counter": "2", + "UMask": "0xc", + "EventName": "CYCLE_ACTIVITY.STALLS_L1D_MISS", + "SampleAfterValue": "2000003", + "BriefDescription": "Execution stalls while L1 cache miss demand load is outstanding.", + "CounterMask": "12", + "CounterHTOff": "2" + }, + { + "EventCode": "0xA8", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "LSD.UOPS", + "SampleAfterValue": "2000003", + "BriefDescription": "Number of Uops delivered by the LSD.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Cycles Uops delivered by the LSD, but didn't come from the decoder.", + "EventCode": "0xA8", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "LSD.CYCLES_ACTIVE", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles Uops delivered by the LSD, but didn't come from the decoder", + "CounterMask": "1", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Cycles 4 Uops delivered by the LSD, but didn't come from the decoder.", + "EventCode": "0xA8", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "LSD.CYCLES_4_UOPS", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles 4 Uops delivered by the LSD, but didn't come from the decoder", + "CounterMask": "4", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Counts total number of uops to be executed per-thread each cycle. Set Cmask = 1, INV =1 to count stall cycles.", + "EventCode": "0xB1", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "UOPS_EXECUTED.THREAD", + "SampleAfterValue": "2000003", + "BriefDescription": "Counts the number of uops to be executed per-thread each cycle.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xB1", + "Invert": "1", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "UOPS_EXECUTED.STALL_CYCLES", + "SampleAfterValue": "2000003", + "BriefDescription": "Counts number of cycles no uops were dispatched to be executed on this thread.", + "CounterMask": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "PublicDescription": "Cycles where at least 1 uop was executed per-thread.", + "EventCode": "0xB1", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "UOPS_EXECUTED.CYCLES_GE_1_UOP_EXEC", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles where at least 1 uop was executed per-thread", + "CounterMask": "1", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Cycles where at least 2 uops were executed per-thread.", + "EventCode": "0xB1", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "UOPS_EXECUTED.CYCLES_GE_2_UOPS_EXEC", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles where at least 2 uops were executed per-thread", + "CounterMask": "2", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Cycles where at least 3 uops were executed per-thread.", + "EventCode": "0xB1", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "UOPS_EXECUTED.CYCLES_GE_3_UOPS_EXEC", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles where at least 3 uops were executed per-thread", + "CounterMask": "3", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Cycles where at least 4 uops were executed per-thread.", + "EventCode": "0xB1", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "UOPS_EXECUTED.CYCLES_GE_4_UOPS_EXEC", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles where at least 4 uops were executed per-thread", + "CounterMask": "4", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Counts total number of uops to be executed per-core each cycle.", + "EventCode": "0xB1", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "UOPS_EXECUTED.CORE", + "SampleAfterValue": "2000003", + "BriefDescription": "Number of uops executed on the core.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Cycles at least 1 micro-op is executed from any thread on physical core.", + "EventCode": "0xB1", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_1", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles at least 1 micro-op is executed from any thread on physical core", + "CounterMask": "1", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Cycles at least 2 micro-op is executed from any thread on physical core.", + "EventCode": "0xB1", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_2", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles at least 2 micro-op is executed from any thread on physical core", + "CounterMask": "2", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Cycles at least 3 micro-op is executed from any thread on physical core.", + "EventCode": "0xB1", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_3", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles at least 3 micro-op is executed from any thread on physical core", + "CounterMask": "3", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Cycles at least 4 micro-op is executed from any thread on physical core.", + "EventCode": "0xB1", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_4", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles at least 4 micro-op is executed from any thread on physical core", + "CounterMask": "4", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Cycles with no micro-ops executed from any thread on physical core.", + "EventCode": "0xB1", + "Invert": "1", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "UOPS_EXECUTED.CORE_CYCLES_NONE", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles with no micro-ops executed from any thread on physical core", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Number of instructions at retirement.", + "EventCode": "0xC0", + "Counter": "0,1,2,3", + "UMask": "0x0", + "EventName": "INST_RETIRED.ANY_P", + "SampleAfterValue": "2000003", + "BriefDescription": "Number of instructions retired. General Counter - architectural event", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PEBS": "2", + "PublicDescription": "Precise instruction retired event with HW to reduce effect of PEBS shadow in IP distribution.", + "EventCode": "0xC0", + "Counter": "1", + "UMask": "0x1", + "EventName": "INST_RETIRED.PREC_DIST", + "SampleAfterValue": "2000003", + "BriefDescription": "Precise instruction retired event with HW to reduce effect of PEBS shadow in IP distribution", + "CounterHTOff": "1" + }, + { + "EventCode": "0xC1", + "Counter": "0,1,2,3", + "UMask": "0x80", + "EventName": "OTHER_ASSISTS.ANY_WB_ASSIST", + "SampleAfterValue": "100003", + "BriefDescription": "Number of times any microcode assist is invoked by HW upon uop writeback.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PEBS": "1", + "EventCode": "0xC2", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "UOPS_RETIRED.ALL", + "SampleAfterValue": "2000003", + "BriefDescription": "Retired uops.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xC2", + "Invert": "1", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "UOPS_RETIRED.STALL_CYCLES", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles without actually retired uops.", + "CounterMask": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xC2", + "Invert": "1", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "UOPS_RETIRED.TOTAL_CYCLES", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles with less than 10 actually retired uops.", + "CounterMask": "10", + "CounterHTOff": "0,1,2,3" + }, + { + "EventCode": "0xC2", + "Invert": "1", + "Counter": "0,1,2,3", + "UMask": "0x1", + "AnyThread": "1", + "EventName": "UOPS_RETIRED.CORE_STALL_CYCLES", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles without actually retired uops.", + "CounterMask": "1", + "CounterHTOff": "0,1,2,3" + }, + { + "PEBS": "1", + "EventCode": "0xC2", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "UOPS_RETIRED.RETIRE_SLOTS", + "SampleAfterValue": "2000003", + "BriefDescription": "Retirement slots used.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0xC3", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EdgeDetect": "1", + "EventName": "MACHINE_CLEARS.COUNT", + "SampleAfterValue": "100003", + "BriefDescription": "Number of machine clears (nukes) of any type.", + "CounterMask": "1", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Number of self-modifying-code machine clears detected.", + "EventCode": "0xC3", + "Counter": "0,1,2,3", + "UMask": "0x4", + "EventName": "MACHINE_CLEARS.SMC", + "SampleAfterValue": "100003", + "BriefDescription": "Self-modifying code (SMC) detected.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Counts the number of executed AVX masked load operations that refer to an illegal address range with the mask bits set to 0.", + "EventCode": "0xC3", + "Counter": "0,1,2,3", + "UMask": "0x20", + "EventName": "MACHINE_CLEARS.MASKMOV", + "SampleAfterValue": "100003", + "BriefDescription": "This event counts the number of executed Intel AVX masked load operations that refer to an illegal address range with the mask bits set to 0.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Branch instructions at retirement.", + "EventCode": "0xC4", + "Counter": "0,1,2,3", + "UMask": "0x0", + "EventName": "BR_INST_RETIRED.ALL_BRANCHES", + "SampleAfterValue": "400009", + "BriefDescription": "All (macro) branch instructions retired.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PEBS": "1", + "EventCode": "0xC4", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "BR_INST_RETIRED.CONDITIONAL", + "SampleAfterValue": "400009", + "BriefDescription": "Conditional branch instructions retired.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PEBS": "1", + "EventCode": "0xC4", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "BR_INST_RETIRED.NEAR_CALL", + "SampleAfterValue": "100007", + "BriefDescription": "Direct and indirect near call instructions retired.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PEBS": "1", + "EventCode": "0xC4", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "BR_INST_RETIRED.NEAR_CALL_R3", + "SampleAfterValue": "100007", + "BriefDescription": "Direct and indirect macro near call instructions retired (captured in ring 3).", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PEBS": "2", + "EventCode": "0xC4", + "Counter": "0,1,2,3", + "UMask": "0x4", + "EventName": "BR_INST_RETIRED.ALL_BRANCHES_PEBS", + "SampleAfterValue": "400009", + "BriefDescription": "All (macro) branch instructions retired.", + "CounterHTOff": "0,1,2,3" + }, + { + "PEBS": "1", + "EventCode": "0xC4", + "Counter": "0,1,2,3", + "UMask": "0x8", + "EventName": "BR_INST_RETIRED.NEAR_RETURN", + "SampleAfterValue": "100007", + "BriefDescription": "Return instructions retired.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Counts the number of not taken branch instructions retired.", + "EventCode": "0xC4", + "Counter": "0,1,2,3", + "UMask": "0x10", + "EventName": "BR_INST_RETIRED.NOT_TAKEN", + "SampleAfterValue": "400009", + "BriefDescription": "Not taken branch instructions retired.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PEBS": "1", + "EventCode": "0xC4", + "Counter": "0,1,2,3", + "UMask": "0x20", + "EventName": "BR_INST_RETIRED.NEAR_TAKEN", + "SampleAfterValue": "400009", + "BriefDescription": "Taken branch instructions retired.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Number of far branches retired.", + "EventCode": "0xC4", + "Counter": "0,1,2,3", + "UMask": "0x40", + "EventName": "BR_INST_RETIRED.FAR_BRANCH", + "SampleAfterValue": "100007", + "BriefDescription": "Far branch instructions retired.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Mispredicted branch instructions at retirement.", + "EventCode": "0xC5", + "Counter": "0,1,2,3", + "UMask": "0x0", + "EventName": "BR_MISP_RETIRED.ALL_BRANCHES", + "SampleAfterValue": "400009", + "BriefDescription": "All mispredicted macro branch instructions retired.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PEBS": "1", + "EventCode": "0xC5", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "BR_MISP_RETIRED.CONDITIONAL", + "SampleAfterValue": "400009", + "BriefDescription": "Mispredicted conditional branch instructions retired.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PEBS": "2", + "EventCode": "0xC5", + "Counter": "0,1,2,3", + "UMask": "0x4", + "EventName": "BR_MISP_RETIRED.ALL_BRANCHES_PEBS", + "SampleAfterValue": "400009", + "BriefDescription": "Mispredicted macro branch instructions retired.", + "CounterHTOff": "0,1,2,3" + }, + { + "PEBS": "1", + "EventCode": "0xC5", + "Counter": "0,1,2,3", + "UMask": "0x20", + "EventName": "BR_MISP_RETIRED.NEAR_TAKEN", + "SampleAfterValue": "400009", + "BriefDescription": "number of near branch instructions retired that were mispredicted and taken.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Count cases of saving new LBR records by hardware.", + "EventCode": "0xCC", + "Counter": "0,1,2,3", + "UMask": "0x20", + "EventName": "ROB_MISC_EVENTS.LBR_INSERTS", + "SampleAfterValue": "2000003", + "BriefDescription": "Count cases of saving new LBR", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Number of front end re-steers due to BPU misprediction.", + "EventCode": "0xE6", + "Counter": "0,1,2,3", + "UMask": "0x1f", + "EventName": "BACLEARS.ANY", + "SampleAfterValue": "100003", + "BriefDescription": "Counts the total number when the front end is resteered, mainly when the BPU cannot provide a correct prediction and this is corrected by other branch handling mechanisms at the front end.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + } +]
\ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/ivybridge/uncore.json b/tools/perf/pmu-events/arch/x86/ivybridge/uncore.json new file mode 100644 index 000000000..42c70eed0 --- /dev/null +++ b/tools/perf/pmu-events/arch/x86/ivybridge/uncore.json @@ -0,0 +1,314 @@ +[ + { + "Unit": "CBO", + "EventCode": "0x22", + "UMask": "0x01", + "EventName": "UNC_CBO_XSNP_RESPONSE.MISS", + "BriefDescription": "A snoop misses in some processor core.", + "PublicDescription": "A snoop misses in some processor core.", + "Counter": "0,1", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0" + }, + { + "Unit": "CBO", + "EventCode": "0x22", + "UMask": "0x02", + "EventName": "UNC_CBO_XSNP_RESPONSE.INVAL", + "BriefDescription": "A snoop invalidates a non-modified line in some processor core.", + "PublicDescription": "A snoop invalidates a non-modified line in some processor core.", + "Counter": "0,1", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0" + }, + { + "Unit": "CBO", + "EventCode": "0x22", + "UMask": "0x04", + "EventName": "UNC_CBO_XSNP_RESPONSE.HIT", + "BriefDescription": "A snoop hits a non-modified line in some processor core.", + "PublicDescription": "A snoop hits a non-modified line in some processor core.", + "Counter": "0,1", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0" + }, + { + "Unit": "CBO", + "EventCode": "0x22", + "UMask": "0x08", + "EventName": "UNC_CBO_XSNP_RESPONSE.HITM", + "BriefDescription": "A snoop hits a modified line in some processor core.", + "PublicDescription": "A snoop hits a modified line in some processor core.", + "Counter": "0,1", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0" + }, + { + "Unit": "CBO", + "EventCode": "0x22", + "UMask": "0x10", + "EventName": "UNC_CBO_XSNP_RESPONSE.INVAL_M", + "BriefDescription": "A snoop invalidates a modified line in some processor core.", + "PublicDescription": "A snoop invalidates a modified line in some processor core.", + "Counter": "0,1", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0" + }, + { + "Unit": "CBO", + "EventCode": "0x22", + "UMask": "0x20", + "EventName": "UNC_CBO_XSNP_RESPONSE.EXTERNAL_FILTER", + "BriefDescription": "Filter on cross-core snoops initiated by this Cbox due to external snoop request.", + "PublicDescription": "Filter on cross-core snoops initiated by this Cbox due to external snoop request.", + "Counter": "0,1", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0" + }, + { + "Unit": "CBO", + "EventCode": "0x22", + "UMask": "0x40", + "EventName": "UNC_CBO_XSNP_RESPONSE.XCORE_FILTER", + "BriefDescription": "Filter on cross-core snoops initiated by this Cbox due to processor core memory request.", + "PublicDescription": "Filter on cross-core snoops initiated by this Cbox due to processor core memory request.", + "Counter": "0,1", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0" + }, + { + "Unit": "CBO", + "EventCode": "0x22", + "UMask": "0x80", + "EventName": "UNC_CBO_XSNP_RESPONSE.EVICTION_FILTER", + "BriefDescription": "Filter on cross-core snoops initiated by this Cbox due to LLC eviction.", + "PublicDescription": "Filter on cross-core snoops initiated by this Cbox due to LLC eviction.", + "Counter": "0,1", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0" + }, + { + "Unit": "CBO", + "EventCode": "0x34", + "UMask": "0x01", + "EventName": "UNC_CBO_CACHE_LOOKUP.M", + "BriefDescription": "LLC lookup request that access cache and found line in M-state.", + "PublicDescription": "LLC lookup request that access cache and found line in M-state.", + "Counter": "0,1", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0" + }, + { + "Unit": "CBO", + "EventCode": "0x34", + "UMask": "0x02", + "EventName": "UNC_CBO_CACHE_LOOKUP.E", + "BriefDescription": "LLC lookup request that access cache and found line in E-state.", + "PublicDescription": "LLC lookup request that access cache and found line in E-state.", + "Counter": "0,1", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0" + }, + { + "Unit": "CBO", + "EventCode": "0x34", + "UMask": "0x04", + "EventName": "UNC_CBO_CACHE_LOOKUP.S", + "BriefDescription": "LLC lookup request that access cache and found line in S-state.", + "PublicDescription": "LLC lookup request that access cache and found line in S-state.", + "Counter": "0,1", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0" + }, + { + "Unit": "CBO", + "EventCode": "0x34", + "UMask": "0x08", + "EventName": "UNC_CBO_CACHE_LOOKUP.I", + "BriefDescription": "LLC lookup request that access cache and found line in I-state.", + "PublicDescription": "LLC lookup request that access cache and found line in I-state.", + "Counter": "0,1", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0" + }, + { + "Unit": "CBO", + "EventCode": "0x34", + "UMask": "0x10", + "EventName": "UNC_CBO_CACHE_LOOKUP.READ_FILTER", + "BriefDescription": "Filter on processor core initiated cacheable read requests.", + "PublicDescription": "Filter on processor core initiated cacheable read requests.", + "Counter": "0,1", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0" + }, + { + "Unit": "CBO", + "EventCode": "0x34", + "UMask": "0x20", + "EventName": "UNC_CBO_CACHE_LOOKUP.WRITE_FILTER", + "BriefDescription": "Filter on processor core initiated cacheable write requests.", + "PublicDescription": "Filter on processor core initiated cacheable write requests.", + "Counter": "0,1", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0" + }, + { + "Unit": "CBO", + "EventCode": "0x34", + "UMask": "0x40", + "EventName": "UNC_CBO_CACHE_LOOKUP.EXTSNP_FILTER", + "BriefDescription": "Filter on external snoop requests.", + "PublicDescription": "Filter on external snoop requests.", + "Counter": "0,1", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0" + }, + { + "Unit": "CBO", + "EventCode": "0x34", + "UMask": "0x80", + "EventName": "UNC_CBO_CACHE_LOOKUP.ANY_REQUEST_FILTER", + "BriefDescription": "Filter on any IRQ or IPQ initiated requests including uncacheable, non-coherent requests.", + "PublicDescription": "Filter on any IRQ or IPQ initiated requests including uncacheable, non-coherent requests.", + "Counter": "0,1", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0" + }, + { + "Unit": "ARB", + "EventCode": "0x80", + "UMask": "0x01", + "EventName": "UNC_ARB_TRK_OCCUPANCY.ALL", + "BriefDescription": "Counts cycles weighted by the number of requests waiting for data returning from the memory controller. Accounts for coherent and non-coherent requests initiated by IA cores, processor graphic units, or LLC.", + "PublicDescription": "Counts cycles weighted by the number of requests waiting for data returning from the memory controller. Accounts for coherent and non-coherent requests initiated by IA cores, processor graphic units, or LLC.", + "Counter": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0" + }, + { + "Unit": "ARB", + "EventCode": "0x81", + "UMask": "0x01", + "EventName": "UNC_ARB_TRK_REQUESTS.ALL", + "BriefDescription": "Counts the number of coherent and in-coherent requests initiated by IA cores, processor graphic units, or LLC.", + "PublicDescription": "Counts the number of coherent and in-coherent requests initiated by IA cores, processor graphic units, or LLC.", + "Counter": "0,1", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0" + }, + { + "Unit": "ARB", + "EventCode": "0x81", + "UMask": "0x20", + "EventName": "UNC_ARB_TRK_REQUESTS.WRITES", + "BriefDescription": "Counts the number of allocated write entries, include full, partial, and LLC evictions.", + "PublicDescription": "Counts the number of allocated write entries, include full, partial, and LLC evictions.", + "Counter": "0,1", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0" + }, + { + "Unit": "ARB", + "EventCode": "0x81", + "UMask": "0x80", + "EventName": "UNC_ARB_TRK_REQUESTS.EVICTIONS", + "BriefDescription": "Counts the number of LLC evictions allocated.", + "PublicDescription": "Counts the number of LLC evictions allocated.", + "Counter": "0,1", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0" + }, + { + "Unit": "ARB", + "EventCode": "0x83", + "UMask": "0x01", + "EventName": "UNC_ARB_COH_TRK_OCCUPANCY.ALL", + "BriefDescription": "Cycles weighted by number of requests pending in Coherency Tracker.", + "PublicDescription": "Cycles weighted by number of requests pending in Coherency Tracker.", + "Counter": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0" + }, + { + "Unit": "ARB", + "EventCode": "0x84", + "UMask": "0x01", + "EventName": "UNC_ARB_COH_TRK_REQUESTS.ALL", + "BriefDescription": "Number of requests allocated in Coherency Tracker.", + "PublicDescription": "Number of requests allocated in Coherency Tracker.", + "Counter": "0,1", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0" + }, + { + "Unit": "ARB", + "EventCode": "0x80", + "UMask": "0x01", + "EventName": "UNC_ARB_TRK_OCCUPANCY.CYCLES_WITH_ANY_REQUEST", + "BriefDescription": "Cycles with at least one request outstanding is waiting for data return from memory controller. Account for coherent and non-coherent requests initiated by IA Cores, Processor Graphics Unit, or LLC.", + "PublicDescription": "Cycles with at least one request outstanding is waiting for data return from memory controller. Account for coherent and non-coherent requests initiated by IA Cores, Processor Graphics Unit, or LLC.", + "Counter": "0,1", + "CounterMask": "1", + "Invert": "0", + "EdgeDetect": "0" + }, + { + "Unit": "ARB", + "EventCode": "0x80", + "UMask": "0x01", + "EventName": "UNC_ARB_TRK_OCCUPANCY.CYCLES_OVER_HALF_FULL", + "BriefDescription": "Cycles with at least half of the requests outstanding are waiting for data return from memory controller. Account for coherent and non-coherent requests initiated by IA Cores, Processor Graphics Unit, or LLC.", + "PublicDescription": "Cycles with at least half of the requests outstanding are waiting for data return from memory controller. Account for coherent and non-coherent requests initiated by IA Cores, Processor Graphics Unit, or LLC.", + "Counter": "0,1", + "CounterMask": "10", + "Invert": "0", + "EdgeDetect": "0" + }, + { + "Unit": "ARB", + "EventCode": "0x0", + "UMask": "0x01", + "EventName": "UNC_CLOCK.SOCKET", + "BriefDescription": "This 48-bit fixed counter counts the UCLK cycles.", + "PublicDescription": "This 48-bit fixed counter counts the UCLK cycles.", + "Counter": "Fixed", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0" + }, + { + "Unit": "CBO", + "EventCode": "0x34", + "UMask": "0x06", + "EventName": "UNC_CBO_CACHE_LOOKUP.ES", + "BriefDescription": "LLC lookup request that access cache and found line in E-state or S-state.", + "PublicDescription": "LLC lookup request that access cache and found line in E-state or S-state.", + "Counter": "0,1", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0" + } +]
\ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/ivybridge/virtual-memory.json b/tools/perf/pmu-events/arch/x86/ivybridge/virtual-memory.json new file mode 100644 index 000000000..f243551b4 --- /dev/null +++ b/tools/perf/pmu-events/arch/x86/ivybridge/virtual-memory.json @@ -0,0 +1,180 @@ +[ + { + "PublicDescription": "Misses in all TLB levels that cause a page walk of any page size from demand loads.", + "EventCode": "0x08", + "Counter": "0,1,2,3", + "UMask": "0x81", + "EventName": "DTLB_LOAD_MISSES.MISS_CAUSES_A_WALK", + "SampleAfterValue": "100003", + "BriefDescription": "Demand load Miss in all translation lookaside buffer (TLB) levels causes an page walk of any page size.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Misses in all TLB levels that caused page walk completed of any size by demand loads.", + "EventCode": "0x08", + "Counter": "0,1,2,3", + "UMask": "0x82", + "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED", + "SampleAfterValue": "100003", + "BriefDescription": "Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that completes of any page size.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Cycle PMH is busy with a walk due to demand loads.", + "EventCode": "0x08", + "Counter": "0,1,2,3", + "UMask": "0x84", + "EventName": "DTLB_LOAD_MISSES.WALK_DURATION", + "SampleAfterValue": "2000003", + "BriefDescription": "Demand load cycles page miss handler (PMH) is busy with this walk.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x08", + "Counter": "0,1,2,3", + "UMask": "0x88", + "EventName": "DTLB_LOAD_MISSES.LARGE_PAGE_WALK_COMPLETED", + "SampleAfterValue": "100003", + "BriefDescription": "Page walk for a large page completed for Demand load.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Miss in all TLB levels causes a page walk of any page size (4K/2M/4M/1G).", + "EventCode": "0x49", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "DTLB_STORE_MISSES.MISS_CAUSES_A_WALK", + "SampleAfterValue": "100003", + "BriefDescription": "Store misses in all DTLB levels that cause page walks", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Miss in all TLB levels causes a page walk that completes of any page size (4K/2M/4M/1G).", + "EventCode": "0x49", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED", + "SampleAfterValue": "100003", + "BriefDescription": "Store misses in all DTLB levels that cause completed page walks", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Cycles PMH is busy with this walk.", + "EventCode": "0x49", + "Counter": "0,1,2,3", + "UMask": "0x4", + "EventName": "DTLB_STORE_MISSES.WALK_DURATION", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles when PMH is busy with page walks", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Store operations that miss the first TLB level but hit the second and do not cause page walks.", + "EventCode": "0x49", + "Counter": "0,1,2,3", + "UMask": "0x10", + "EventName": "DTLB_STORE_MISSES.STLB_HIT", + "SampleAfterValue": "100003", + "BriefDescription": "Store operations that miss the first TLB level but hit the second and do not cause page walks", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "EventCode": "0x4F", + "Counter": "0,1,2,3", + "UMask": "0x10", + "EventName": "EPT.WALK_CYCLES", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycle count for an Extended Page table walk. The Extended Page Directory cache is used by Virtual Machine operating systems while the guest operating systems use the standard TLB caches.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Counts load operations that missed 1st level DTLB but hit the 2nd level.", + "EventCode": "0x5F", + "Counter": "0,1,2,3", + "UMask": "0x4", + "EventName": "DTLB_LOAD_MISSES.STLB_HIT", + "SampleAfterValue": "100003", + "BriefDescription": "Load operations that miss the first DTLB level but hit the second and do not cause page walks", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Misses in all ITLB levels that cause page walks.", + "EventCode": "0x85", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "ITLB_MISSES.MISS_CAUSES_A_WALK", + "SampleAfterValue": "100003", + "BriefDescription": "Misses at all ITLB levels that cause page walks", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Misses in all ITLB levels that cause completed page walks.", + "EventCode": "0x85", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "ITLB_MISSES.WALK_COMPLETED", + "SampleAfterValue": "100003", + "BriefDescription": "Misses in all ITLB levels that cause completed page walks", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Cycle PMH is busy with a walk.", + "EventCode": "0x85", + "Counter": "0,1,2,3", + "UMask": "0x4", + "EventName": "ITLB_MISSES.WALK_DURATION", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles when PMH is busy with page walks", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Number of cache load STLB hits. No page walk.", + "EventCode": "0x85", + "Counter": "0,1,2,3", + "UMask": "0x10", + "EventName": "ITLB_MISSES.STLB_HIT", + "SampleAfterValue": "100003", + "BriefDescription": "Operations that miss the first ITLB level but hit the second and do not cause any page walks", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Completed page walks in ITLB due to STLB load misses for large pages.", + "EventCode": "0x85", + "Counter": "0,1,2,3", + "UMask": "0x80", + "EventName": "ITLB_MISSES.LARGE_PAGE_WALK_COMPLETED", + "SampleAfterValue": "100003", + "BriefDescription": "Completed page walks in ITLB due to STLB load misses for large pages", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Counts the number of ITLB flushes, includes 4k/2M/4M pages.", + "EventCode": "0xAE", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "ITLB.ITLB_FLUSH", + "SampleAfterValue": "100007", + "BriefDescription": "Flushing of the Instruction TLB (ITLB) pages, includes 4k/2M/4M pages.", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "DTLB flush attempts of the thread-specific entries.", + "EventCode": "0xBD", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "TLB_FLUSH.DTLB_THREAD", + "SampleAfterValue": "100007", + "BriefDescription": "DTLB flush attempts of the thread-specific entries", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Count number of STLB flush attempts.", + "EventCode": "0xBD", + "Counter": "0,1,2,3", + "UMask": "0x20", + "EventName": "TLB_FLUSH.STLB_ANY", + "SampleAfterValue": "100007", + "BriefDescription": "STLB flush attempts", + "CounterHTOff": "0,1,2,3,4,5,6,7" + } +]
\ No newline at end of file |