From 5d1646d90e1f2cceb9f0828f4b28318cd0ec7744 Mon Sep 17 00:00:00 2001 From: Daniel Baumann Date: Sat, 27 Apr 2024 12:05:51 +0200 Subject: Adding upstream version 5.10.209. Signed-off-by: Daniel Baumann --- .../devicetree/bindings/media/rockchip-rga.yaml | 83 ++++++++++++++++++++++ 1 file changed, 83 insertions(+) create mode 100644 Documentation/devicetree/bindings/media/rockchip-rga.yaml (limited to 'Documentation/devicetree/bindings/media/rockchip-rga.yaml') diff --git a/Documentation/devicetree/bindings/media/rockchip-rga.yaml b/Documentation/devicetree/bindings/media/rockchip-rga.yaml new file mode 100644 index 000000000..dd645ddcc --- /dev/null +++ b/Documentation/devicetree/bindings/media/rockchip-rga.yaml @@ -0,0 +1,83 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/media/rockchip-rga.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Rockchip 2D raster graphic acceleration controller (RGA) + +description: + RGA is a standalone 2D raster graphic acceleration unit. It accelerates 2D + graphics operations, such as point/line drawing, image scaling, rotation, + BitBLT, alpha blending and image blur/sharpness. + +maintainers: + - Jacob Chen + - Ezequiel Garcia + +properties: + compatible: + oneOf: + - const: rockchip,rk3288-rga + - const: rockchip,rk3399-rga + - items: + - const: rockchip,rk3228-rga + - const: rockchip,rk3288-rga + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + maxItems: 3 + + clock-names: + items: + - const: aclk + - const: hclk + - const: sclk + + power-domains: + maxItems: 1 + + resets: + maxItems: 3 + + reset-names: + items: + - const: core + - const: axi + - const: ahb + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + - resets + - reset-names + +additionalProperties: false + +examples: + - | + #include + #include + #include + rga: rga@ff680000 { + compatible = "rockchip,rk3399-rga"; + reg = <0xff680000 0x10000>; + interrupts = ; + clocks = <&cru ACLK_RGA>, + <&cru HCLK_RGA>, + <&cru SCLK_RGA_CORE>; + clock-names = "aclk", "hclk", "sclk"; + power-domains = <&power RK3399_PD_RGA>; + resets = <&cru SRST_RGA_CORE>, + <&cru SRST_A_RGA>, + <&cru SRST_H_RGA>; + reset-names = "core", "axi", "ahb"; + }; -- cgit v1.2.3