From 5d1646d90e1f2cceb9f0828f4b28318cd0ec7744 Mon Sep 17 00:00:00 2001 From: Daniel Baumann Date: Sat, 27 Apr 2024 12:05:51 +0200 Subject: Adding upstream version 5.10.209. Signed-off-by: Daniel Baumann --- arch/arm/boot/dts/imx6qp.dtsi | 120 ++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 120 insertions(+) create mode 100644 arch/arm/boot/dts/imx6qp.dtsi (limited to 'arch/arm/boot/dts/imx6qp.dtsi') diff --git a/arch/arm/boot/dts/imx6qp.dtsi b/arch/arm/boot/dts/imx6qp.dtsi new file mode 100644 index 000000000..4d23c92aa --- /dev/null +++ b/arch/arm/boot/dts/imx6qp.dtsi @@ -0,0 +1,120 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +// +// Copyright 2016 Freescale Semiconductor, Inc. + +#include "imx6q.dtsi" + +/ { + soc { + ocram2: sram@940000 { + compatible = "mmio-sram"; + reg = <0x00940000 0x20000>; + ranges = <0 0x00940000 0x20000>; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&clks IMX6QDL_CLK_OCRAM>; + }; + + ocram3: sram@960000 { + compatible = "mmio-sram"; + reg = <0x00960000 0x20000>; + ranges = <0 0x00960000 0x20000>; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&clks IMX6QDL_CLK_OCRAM>; + }; + + bus@2100000 { + pre1: pre@21c8000 { + compatible = "fsl,imx6qp-pre"; + reg = <0x021c8000 0x1000>; + interrupts = ; + clocks = <&clks IMX6QDL_CLK_PRE0>; + clock-names = "axi"; + fsl,iram = <&ocram2>; + }; + + pre2: pre@21c9000 { + compatible = "fsl,imx6qp-pre"; + reg = <0x021c9000 0x1000>; + interrupts = ; + clocks = <&clks IMX6QDL_CLK_PRE1>; + clock-names = "axi"; + fsl,iram = <&ocram2>; + }; + + pre3: pre@21ca000 { + compatible = "fsl,imx6qp-pre"; + reg = <0x021ca000 0x1000>; + interrupts = ; + clocks = <&clks IMX6QDL_CLK_PRE2>; + clock-names = "axi"; + fsl,iram = <&ocram3>; + }; + + pre4: pre@21cb000 { + compatible = "fsl,imx6qp-pre"; + reg = <0x021cb000 0x1000>; + interrupts = ; + clocks = <&clks IMX6QDL_CLK_PRE3>; + clock-names = "axi"; + fsl,iram = <&ocram3>; + }; + + prg1: prg@21cc000 { + compatible = "fsl,imx6qp-prg"; + reg = <0x021cc000 0x1000>; + clocks = <&clks IMX6QDL_CLK_PRG0_APB>, + <&clks IMX6QDL_CLK_PRG0_AXI>; + clock-names = "ipg", "axi"; + fsl,pres = <&pre1>, <&pre2>, <&pre3>; + }; + + prg2: prg@21cd000 { + compatible = "fsl,imx6qp-prg"; + reg = <0x021cd000 0x1000>; + clocks = <&clks IMX6QDL_CLK_PRG1_APB>, + <&clks IMX6QDL_CLK_PRG1_AXI>; + clock-names = "ipg", "axi"; + fsl,pres = <&pre4>, <&pre2>, <&pre3>; + }; + }; + }; +}; + +&fec { + interrupts = <0 118 IRQ_TYPE_LEVEL_HIGH>, + <0 119 IRQ_TYPE_LEVEL_HIGH>; +}; + +&gpc { + compatible = "fsl,imx6qp-gpc", "fsl,imx6q-gpc"; +}; + +&ipu1 { + compatible = "fsl,imx6qp-ipu", "fsl,imx6q-ipu"; + fsl,prg = <&prg1>; +}; + +&ipu2 { + compatible = "fsl,imx6qp-ipu", "fsl,imx6q-ipu"; + fsl,prg = <&prg2>; +}; + +&ldb { + clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, <&clks IMX6QDL_CLK_LDB_DI1_SEL>, + <&clks IMX6QDL_CLK_IPU1_DI0_SEL>, <&clks IMX6QDL_CLK_IPU1_DI1_SEL>, + <&clks IMX6QDL_CLK_IPU2_DI0_SEL>, <&clks IMX6QDL_CLK_IPU2_DI1_SEL>, + <&clks IMX6QDL_CLK_LDB_DI0_PODF>, <&clks IMX6QDL_CLK_LDB_DI1_PODF>; + clock-names = "di0_pll", "di1_pll", + "di0_sel", "di1_sel", "di2_sel", "di3_sel", + "di0", "di1"; +}; + +&mmdc0 { + compatible = "fsl,imx6qp-mmdc", "fsl,imx6q-mmdc"; +}; + +&pcie { + compatible = "fsl,imx6qp-pcie", "snps,dw-pcie"; +}; -- cgit v1.2.3