From 5d1646d90e1f2cceb9f0828f4b28318cd0ec7744 Mon Sep 17 00:00:00 2001 From: Daniel Baumann Date: Sat, 27 Apr 2024 12:05:51 +0200 Subject: Adding upstream version 5.10.209. Signed-off-by: Daniel Baumann --- .../arm64/boot/dts/broadcom/stingray/stingray.dtsi | 722 +++++++++++++++++++++ 1 file changed, 722 insertions(+) create mode 100644 arch/arm64/boot/dts/broadcom/stingray/stingray.dtsi (limited to 'arch/arm64/boot/dts/broadcom/stingray/stingray.dtsi') diff --git a/arch/arm64/boot/dts/broadcom/stingray/stingray.dtsi b/arch/arm64/boot/dts/broadcom/stingray/stingray.dtsi new file mode 100644 index 000000000..b425b12c3 --- /dev/null +++ b/arch/arm64/boot/dts/broadcom/stingray/stingray.dtsi @@ -0,0 +1,722 @@ +/* + * BSD LICENSE + * + * Copyright(c) 2015-2017 Broadcom. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name of Broadcom nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include + +/ { + compatible = "brcm,stingray"; + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + + cpus { + #address-cells = <2>; + #size-cells = <0>; + + cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a72"; + reg = <0x0 0x0>; + enable-method = "psci"; + next-level-cache = <&CLUSTER0_L2>; + }; + + cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a72"; + reg = <0x0 0x1>; + enable-method = "psci"; + next-level-cache = <&CLUSTER0_L2>; + }; + + cpu@100 { + device_type = "cpu"; + compatible = "arm,cortex-a72"; + reg = <0x0 0x100>; + enable-method = "psci"; + next-level-cache = <&CLUSTER1_L2>; + }; + + cpu@101 { + device_type = "cpu"; + compatible = "arm,cortex-a72"; + reg = <0x0 0x101>; + enable-method = "psci"; + next-level-cache = <&CLUSTER1_L2>; + }; + + cpu@200 { + device_type = "cpu"; + compatible = "arm,cortex-a72"; + reg = <0x0 0x200>; + enable-method = "psci"; + next-level-cache = <&CLUSTER2_L2>; + }; + + cpu@201 { + device_type = "cpu"; + compatible = "arm,cortex-a72"; + reg = <0x0 0x201>; + enable-method = "psci"; + next-level-cache = <&CLUSTER2_L2>; + }; + + cpu@300 { + device_type = "cpu"; + compatible = "arm,cortex-a72"; + reg = <0x0 0x300>; + enable-method = "psci"; + next-level-cache = <&CLUSTER3_L2>; + }; + + cpu@301 { + device_type = "cpu"; + compatible = "arm,cortex-a72"; + reg = <0x0 0x301>; + enable-method = "psci"; + next-level-cache = <&CLUSTER3_L2>; + }; + + CLUSTER0_L2: l2-cache@0 { + compatible = "cache"; + }; + + CLUSTER1_L2: l2-cache@100 { + compatible = "cache"; + }; + + CLUSTER2_L2: l2-cache@200 { + compatible = "cache"; + }; + + CLUSTER3_L2: l2-cache@300 { + compatible = "cache"; + }; + }; + + memory: memory@80000000 { + device_type = "memory"; + reg = <0x00000000 0x80000000 0 0x40000000>; + }; + + psci { + compatible = "arm,psci-0.2"; + method = "smc"; + }; + + pmu { + compatible = "arm,armv8-pmuv3"; + interrupts = ; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = , + , + , + ; + }; + + mhb: syscon@60401000 { + compatible = "brcm,sr-mhb", "syscon"; + reg = <0 0x60401000 0 0x38c>; + }; + + scr { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x0 0x61000000 0x05000000>; + + ccn: ccn@0 { + compatible = "arm,ccn-502"; + reg = <0x00000000 0x900000>; + interrupts = ; + }; + + gic: interrupt-controller@2c00000 { + compatible = "arm,gic-v3"; + #interrupt-cells = <3>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + interrupt-controller; + reg = <0x02c00000 0x010000>, /* GICD */ + <0x02e00000 0x600000>; /* GICR */ + interrupts = ; + + gic_its: gic-its@63c20000 { + compatible = "arm,gic-v3-its"; + msi-controller; + #msi-cells = <1>; + reg = <0x02c20000 0x10000>; + }; + }; + + smmu: mmu@3000000 { + compatible = "arm,mmu-500"; + reg = <0x03000000 0x80000>; + #global-interrupts = <1>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + #iommu-cells = <2>; + }; + }; + + crmu: crmu { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x0 0x66400000 0x100000>; + + #include "stingray-clock.dtsi" + + otp: otp@1c400 { + compatible = "brcm,ocotp-v2"; + reg = <0x0001c400 0x68>; + brcm,ocotp-size = <2048>; + status = "okay"; + }; + + cdru: syscon@1d000 { + compatible = "brcm,sr-cdru", "syscon"; + reg = <0x0001d000 0x400>; + }; + + gpio_crmu: gpio@24800 { + compatible = "brcm,iproc-gpio"; + reg = <0x00024800 0x4c>; + ngpios = <6>; + #gpio-cells = <2>; + gpio-controller; + }; + }; + + #include "stingray-fs4.dtsi" + #include "stingray-sata.dtsi" + #include "stingray-pcie.dtsi" + #include "stingray-usb.dtsi" + + hsls { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x0 0x68900000 0x17700000>; + + #include "stingray-pinctrl.dtsi" + + mdio_mux_iproc: mdio-mux@20000 { + compatible = "brcm,mdio-mux-iproc"; + reg = <0x00020000 0x250>; + #address-cells = <1>; + #size-cells = <0>; + + mdio@0 { /* PCIe serdes */ + reg = <0x0>; + #address-cells = <1>; + #size-cells = <0>; + }; + + mdio@2 { /* SATA */ + reg = <0x2>; + #address-cells = <1>; + #size-cells = <0>; + }; + + mdio@3 { /* USB */ + reg = <0x3>; + #address-cells = <1>; + #size-cells = <0>; + }; + + mdio@10 { /* RGMII */ + reg = <0x10>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + + pwm: pwm@10000 { + compatible = "brcm,iproc-pwm"; + reg = <0x00010000 0x1000>; + clocks = <&crmu_ref25m>; + #pwm-cells = <3>; + status = "disabled"; + }; + + timer0: timer@30000 { + compatible = "arm,sp804", "arm,primecell"; + reg = <0x00030000 0x1000>; + interrupts = ; + clocks = <&hsls_25m_div2_clk>, + <&hsls_25m_div2_clk>, + <&hsls_div4_clk>; + clock-names = "timer1", "timer2", "apb_pclk"; + status = "disabled"; + }; + + timer1: timer@40000 { + compatible = "arm,sp804", "arm,primecell"; + reg = <0x00040000 0x1000>; + interrupts = ; + clocks = <&hsls_25m_div2_clk>, + <&hsls_25m_div2_clk>, + <&hsls_div4_clk>; + clock-names = "timer1", "timer2", "apb_pclk"; + }; + + timer2: timer@50000 { + compatible = "arm,sp804", "arm,primecell"; + reg = <0x00050000 0x1000>; + interrupts = ; + clocks = <&hsls_25m_div2_clk>, + <&hsls_25m_div2_clk>, + <&hsls_div4_clk>; + clock-names = "timer1", "timer2", "apb_pclk"; + status = "disabled"; + }; + + timer3: timer@60000 { + compatible = "arm,sp804", "arm,primecell"; + reg = <0x00060000 0x1000>; + interrupts = ; + clocks = <&hsls_25m_div2_clk>, + <&hsls_25m_div2_clk>, + <&hsls_div4_clk>; + clock-names = "timer1", "timer2", "apb_pclk"; + status = "disabled"; + }; + + timer4: timer@70000 { + compatible = "arm,sp804", "arm,primecell"; + reg = <0x00070000 0x1000>; + interrupts = ; + clocks = <&hsls_25m_div2_clk>, + <&hsls_25m_div2_clk>, + <&hsls_div4_clk>; + clock-names = "timer1", "timer2", "apb_pclk"; + status = "disabled"; + }; + + timer5: timer@80000 { + compatible = "arm,sp804", "arm,primecell"; + reg = <0x00080000 0x1000>; + interrupts = ; + clocks = <&hsls_25m_div2_clk>, + <&hsls_25m_div2_clk>, + <&hsls_div4_clk>; + clock-names = "timer1", "timer2", "apb_pclk"; + status = "disabled"; + }; + + timer6: timer@90000 { + compatible = "arm,sp804", "arm,primecell"; + reg = <0x00090000 0x1000>; + interrupts = ; + clocks = <&hsls_25m_div2_clk>, + <&hsls_25m_div2_clk>, + <&hsls_div4_clk>; + clock-names = "timer1", "timer2", "apb_pclk"; + status = "disabled"; + }; + + timer7: timer@a0000 { + compatible = "arm,sp804", "arm,primecell"; + reg = <0x000a0000 0x1000>; + interrupts = ; + clocks = <&hsls_25m_div2_clk>, + <&hsls_25m_div2_clk>, + <&hsls_div4_clk>; + clock-names = "timer1", "timer2", "apb_pclk"; + status = "disabled"; + }; + + i2c0: i2c@b0000 { + compatible = "brcm,iproc-i2c"; + reg = <0x000b0000 0x100>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clock-frequency = <100000>; + status = "disabled"; + }; + + wdt0: watchdog@c0000 { + compatible = "arm,sp805", "arm,primecell"; + reg = <0x000c0000 0x1000>; + interrupts = ; + clocks = <&hsls_25m_div2_clk>, <&hsls_div4_clk>; + clock-names = "wdog_clk", "apb_pclk"; + timeout-sec = <60>; + }; + + gpio_hsls: gpio@d0000 { + compatible = "brcm,iproc-gpio"; + reg = <0x000d0000 0x864>; + ngpios = <151>; + #gpio-cells = <2>; + gpio-controller; + interrupt-controller; + interrupts = ; + gpio-ranges = <&pinmux 0 0 16>, + <&pinmux 16 71 2>, + <&pinmux 18 131 8>, + <&pinmux 26 83 6>, + <&pinmux 32 123 4>, + <&pinmux 36 43 24>, + <&pinmux 60 89 2>, + <&pinmux 62 73 4>, + <&pinmux 66 95 28>, + <&pinmux 94 127 4>, + <&pinmux 98 139 10>, + <&pinmux 108 16 27>, + <&pinmux 135 77 6>, + <&pinmux 141 67 4>, + <&pinmux 145 149 6>; + }; + + i2c1: i2c@e0000 { + compatible = "brcm,iproc-i2c"; + reg = <0x000e0000 0x100>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clock-frequency = <100000>; + status = "disabled"; + }; + + uart0: uart@100000 { + device_type = "serial"; + compatible = "snps,dw-apb-uart"; + reg = <0x00100000 0x1000>; + reg-shift = <2>; + clock-frequency = <25000000>; + interrupt-parent = <&gic>; + interrupts = ; + status = "disabled"; + }; + + uart1: uart@110000 { + device_type = "serial"; + compatible = "snps,dw-apb-uart"; + reg = <0x00110000 0x1000>; + reg-shift = <2>; + clock-frequency = <25000000>; + interrupt-parent = <&gic>; + interrupts = ; + status = "disabled"; + }; + + uart2: uart@120000 { + device_type = "serial"; + compatible = "snps,dw-apb-uart"; + reg = <0x00120000 0x1000>; + reg-shift = <2>; + clock-frequency = <25000000>; + interrupt-parent = <&gic>; + interrupts = ; + status = "disabled"; + }; + + uart3: uart@130000 { + device_type = "serial"; + compatible = "snps,dw-apb-uart"; + reg = <0x00130000 0x1000>; + reg-shift = <2>; + clock-frequency = <25000000>; + interrupt-parent = <&gic>; + interrupts = ; + status = "disabled"; + }; + + ssp0: spi@180000 { + compatible = "arm,pl022", "arm,primecell"; + reg = <0x00180000 0x1000>; + interrupts = ; + clocks = <&hsls_div2_clk>, <&hsls_div2_clk>; + clock-names = "spiclk", "apb_pclk"; + num-cs = <1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + ssp1: spi@190000 { + compatible = "arm,pl022", "arm,primecell"; + reg = <0x00190000 0x1000>; + interrupts = ; + clocks = <&hsls_div2_clk>, <&hsls_div2_clk>; + clock-names = "spiclk", "apb_pclk"; + num-cs = <1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + hwrng: hwrng@220000 { + compatible = "brcm,iproc-rng200"; + reg = <0x00220000 0x28>; + }; + + dma0: dma@310000 { + compatible = "arm,pl330", "arm,primecell"; + reg = <0x00310000 0x1000>; + interrupts = , + , + , + , + , + , + , + , + ; + #dma-cells = <1>; + #dma-channels = <8>; + #dma-requests = <32>; + clocks = <&hsls_div2_clk>; + clock-names = "apb_pclk"; + iommus = <&smmu 0x6000 0x0000>; + }; + + enet: ethernet@340000{ + compatible = "brcm,amac"; + reg = <0x00340000 0x1000>; + reg-names = "amac_base"; + dma-coherent; + interrupts = ; + status= "disabled"; + }; + + nand: nand@360000 { + compatible = "brcm,nand-iproc", "brcm,brcmnand-v6.1"; + reg = <0x00360000 0x600>, + <0x0050a408 0x600>, + <0x00360f00 0x20>; + reg-names = "nand", "iproc-idm", "iproc-ext"; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + brcm,nand-has-wp; + status = "disabled"; + }; + + sdio0: sdhci@3f1000 { + compatible = "brcm,sdhci-iproc"; + reg = <0x003f1000 0x100>; + interrupts = ; + bus-width = <8>; + clocks = <&sdio0_clk>; + iommus = <&smmu 0x6002 0x0000>; + status = "disabled"; + }; + + sdio1: sdhci@3f2000 { + compatible = "brcm,sdhci-iproc"; + reg = <0x003f2000 0x100>; + interrupts = ; + bus-width = <8>; + clocks = <&sdio1_clk>; + iommus = <&smmu 0x6003 0x0000>; + status = "disabled"; + }; + }; + + tmons { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x0 0x8f100000 0x100>; + + tmon: tmon@0 { + compatible = "brcm,sr-thermal"; + reg = <0x0 0x40>; + brcm,tmon-mask = <0x3f>; + #thermal-sensor-cells = <1>; + }; + }; + + thermal-zones { + ihost0_thermal: ihost0-thermal { + polling-delay-passive = <0>; + polling-delay = <1000>; + thermal-sensors = <&tmon 0>; + trips { + cpu-crit { + temperature = <105000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + ihost1_thermal: ihost1-thermal { + polling-delay-passive = <0>; + polling-delay = <1000>; + thermal-sensors = <&tmon 1>; + trips { + cpu-crit { + temperature = <105000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + ihost2_thermal: ihost2-thermal { + polling-delay-passive = <0>; + polling-delay = <1000>; + thermal-sensors = <&tmon 2>; + trips { + cpu-crit { + temperature = <105000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + ihost3_thermal: ihost3-thermal { + polling-delay-passive = <0>; + polling-delay = <1000>; + thermal-sensors = <&tmon 3>; + trips { + cpu-crit { + temperature = <105000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + crmu_thermal: crmu-thermal { + polling-delay-passive = <0>; + polling-delay = <1000>; + thermal-sensors = <&tmon 4>; + trips { + cpu-crit { + temperature = <105000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + nitro_thermal: nitro-thermal { + polling-delay-passive = <0>; + polling-delay = <1000>; + thermal-sensors = <&tmon 5>; + trips { + cpu-crit { + temperature = <105000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + }; + + nic-hsls { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x0 0x0 0x7fffffff>; + + nic_i2c0: i2c@60826100 { + compatible = "brcm,iproc-nic-i2c"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x60826100 0x100>, + <0x60e00408 0x1000>; + brcm,ape-hsls-addr-mask = <0x03400000>; + clock-frequency = <100000>; + status = "disabled"; + }; + }; +}; -- cgit v1.2.3