From 5d1646d90e1f2cceb9f0828f4b28318cd0ec7744 Mon Sep 17 00:00:00 2001 From: Daniel Baumann Date: Sat, 27 Apr 2024 12:05:51 +0200 Subject: Adding upstream version 5.10.209. Signed-off-by: Daniel Baumann --- arch/m68k/68000/Makefile | 19 + arch/m68k/68000/bootlogo-vz.h | 3207 ++++ arch/m68k/68000/bootlogo.h | 273 + arch/m68k/68000/entry.S | 246 + arch/m68k/68000/head.S | 241 + arch/m68k/68000/ints.c | 186 + arch/m68k/68000/m68328.c | 56 + arch/m68k/68000/m68EZ328.c | 77 + arch/m68k/68000/m68VZ328.c | 189 + arch/m68k/68000/romvec.S | 35 + arch/m68k/68000/timers.c | 136 + arch/m68k/Kbuild | 19 + arch/m68k/Kconfig | 146 + arch/m68k/Kconfig.bus | 71 + arch/m68k/Kconfig.cpu | 514 + arch/m68k/Kconfig.debug | 50 + arch/m68k/Kconfig.devices | 146 + arch/m68k/Kconfig.machine | 463 + arch/m68k/Makefile | 146 + arch/m68k/amiga/Makefile | 8 + arch/m68k/amiga/amiints.c | 174 + arch/m68k/amiga/amisound.c | 116 + arch/m68k/amiga/chipram.c | 124 + arch/m68k/amiga/cia.c | 195 + arch/m68k/amiga/config.c | 859 + arch/m68k/amiga/pcmcia.c | 122 + arch/m68k/amiga/platform.c | 255 + arch/m68k/apollo/Makefile | 6 + arch/m68k/apollo/config.c | 270 + arch/m68k/apollo/dn_ints.c | 48 + arch/m68k/atari/Makefile | 11 + arch/m68k/atari/ataints.c | 391 + arch/m68k/atari/atakeyb.c | 570 + arch/m68k/atari/atasound.c | 109 + arch/m68k/atari/config.c | 945 + arch/m68k/atari/debug.c | 329 + arch/m68k/atari/nvram.c | 272 + arch/m68k/atari/stdma.c | 220 + arch/m68k/atari/stram.c | 202 + arch/m68k/atari/time.c | 325 + arch/m68k/bvme6000/Makefile | 6 + arch/m68k/bvme6000/config.c | 327 + arch/m68k/bvme6000/rtc.c | 175 + arch/m68k/coldfire/Makefile | 44 + arch/m68k/coldfire/amcore.c | 156 + arch/m68k/coldfire/cache.c | 49 + arch/m68k/coldfire/clk.c | 161 + arch/m68k/coldfire/device.c | 646 + arch/m68k/coldfire/dma.c | 43 + arch/m68k/coldfire/dma_timer.c | 82 + arch/m68k/coldfire/entry.S | 205 + arch/m68k/coldfire/firebee.c | 87 + arch/m68k/coldfire/gpio.c | 173 + arch/m68k/coldfire/head.S | 299 + arch/m68k/coldfire/intc-2.c | 212 + arch/m68k/coldfire/intc-5249.c | 61 + arch/m68k/coldfire/intc-525x.c | 91 + arch/m68k/coldfire/intc-5272.c | 185 + arch/m68k/coldfire/intc-simr.c | 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arch/m68k/tools/amiga/dmesg.c (limited to 'arch/m68k') diff --git a/arch/m68k/68000/Makefile b/arch/m68k/68000/Makefile new file mode 100644 index 000000000..4f7d4b45a --- /dev/null +++ b/arch/m68k/68000/Makefile @@ -0,0 +1,19 @@ +# SPDX-License-Identifier: GPL-2.0 +################################################## +# +# Makefile for 68000 core based cpus +# +# 2012.10.21, Luis Alves +# Merged all 68000 based cpu's config +# files into a single directory. +# + +# 68328, 68EZ328, 68VZ328 + +obj-y += entry.o ints.o timers.o +obj-$(CONFIG_M68328) += m68328.o +obj-$(CONFIG_M68EZ328) += m68EZ328.o +obj-$(CONFIG_M68VZ328) += m68VZ328.o +obj-$(CONFIG_ROM) += romvec.o + +extra-y := head.o diff --git a/arch/m68k/68000/bootlogo-vz.h b/arch/m68k/68000/bootlogo-vz.h new file mode 100644 index 000000000..1afa33955 --- /dev/null +++ b/arch/m68k/68000/bootlogo-vz.h @@ -0,0 +1,3207 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#include + +#define splash_width 640 +#define splash_height 480 +unsigned char __aligned(16) bootlogo_bits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 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0x00, 0x00, + 0x00, 0x00, 0x40, 0x02, 0x00, 0x00, 0x00, 0x00, 0x24, 0x80, 0x48, 0x02, + 0xc0, 0x1f, 0x00, 0x08, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x4e, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x0a, 0x00, 0x05, 0xf0, 0x3f, 0x09, 0x00, + 0x00, 0x10, 0x24, 0x48, 0x10, 0x12, 0x41, 0x52, 0x24, 0x09, 0x46, 0x71, + 0x90, 0x20, 0x02, 0xfc, 0xff, 0x1f, 0x80, 0x22, 0x00, 0x90, 0x24, 0x49, + 0x12, 0x92, 0x40, 0xb2, 0x24, 0x09, 0xc9, 0x49, 0x04, 0x80, 0x90, 0xfc, + 0xff, 0xbf, 0x24, 0x00, 0x00, 0x90, 0x24, 0x49, 0x12, 0x92, 0x40, 0x92, + 0x24, 0x06, 0x49, 0x48, 0x50, 0x0a, 0x02, 0xfe, 0xff, 0x3f, 0x00, 0x05, + 0x00, 0x50, 0xa5, 0x4a, 0x15, 0x92, 0x40, 0x92, 0x24, 0x06, 0x49, 0x48, + 0x80, 0x40, 0x48, 0xfe, 0xff, 0x3f, 0x49, 0x00, 0x00, 0x20, 0x42, 0x84, + 0x88, 0x1a, 0x41, 0x92, 0x34, 0x49, 0x49, 0x68, 0x00, 0x38, 0x10, 0x07, + 0x00, 0x60, 0x80, 0x00, 0x00, 0x20, 0x42, 0x84, 0x88, 0x14, 0x4e, 0x92, + 0x28, 0x49, 0x46, 0x50, 0x00, 0x80, 0x83, 0x01, 0x00, 0xa0, 0x6a, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, + 0x00, 0x00, 0xfc, 0x00, 0x00, 0xc0, 0x3b, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, }; diff --git a/arch/m68k/68000/entry.S b/arch/m68k/68000/entry.S new file mode 100644 index 000000000..94abf3d8a --- /dev/null +++ b/arch/m68k/68000/entry.S @@ -0,0 +1,246 @@ +/* + * entry.S -- non-mmu 68000 interrupt and exception entry points + * + * Copyright (C) 1991, 1992 Linus Torvalds + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file README.legal in the main directory of this archive + * for more details. + * + * Linux/m68k support by Hamish Macdonald + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +.text + +.globl system_call +.globl resume +.globl ret_from_exception +.globl ret_from_signal +.globl sys_call_table +.globl bad_interrupt +.globl inthandler1 +.globl inthandler2 +.globl inthandler3 +.globl inthandler4 +.globl inthandler5 +.globl inthandler6 +.globl inthandler7 + +badsys: + movel #-ENOSYS,%sp@(PT_OFF_D0) + jra ret_from_exception + +do_trace: + movel #-ENOSYS,%sp@(PT_OFF_D0) /* needed for strace*/ + subql #4,%sp + SAVE_SWITCH_STACK + jbsr syscall_trace_enter + RESTORE_SWITCH_STACK + addql #4,%sp + addql #1,%d0 + jeq ret_from_exception + movel %sp@(PT_OFF_ORIG_D0),%d1 + movel #-ENOSYS,%d0 + cmpl #NR_syscalls,%d1 + jcc 1f + lsl #2,%d1 + lea sys_call_table, %a0 + jbsr %a0@(%d1) + +1: movel %d0,%sp@(PT_OFF_D0) /* save the return value */ + subql #4,%sp /* dummy return address */ + SAVE_SWITCH_STACK + jbsr syscall_trace_leave + +ret_from_signal: + RESTORE_SWITCH_STACK + addql #4,%sp + jra ret_from_exception + +ENTRY(system_call) + SAVE_ALL_SYS + + /* save top of frame*/ + pea %sp@ + jbsr set_esp0 + addql #4,%sp + + movel %sp@(PT_OFF_ORIG_D0),%d0 + + movel %sp,%d1 /* get thread_info pointer */ + andl #-THREAD_SIZE,%d1 + movel %d1,%a2 + btst #(TIF_SYSCALL_TRACE%8),%a2@(TINFO_FLAGS+(31-TIF_SYSCALL_TRACE)/8) + jne do_trace + cmpl #NR_syscalls,%d0 + jcc badsys + lsl #2,%d0 + lea sys_call_table,%a0 + movel %a0@(%d0), %a0 + jbsr %a0@ + movel %d0,%sp@(PT_OFF_D0) /* save the return value*/ + +ret_from_exception: + btst #5,%sp@(PT_OFF_SR) /* check if returning to kernel*/ + jeq Luser_return /* if so, skip resched, signals*/ + +Lkernel_return: + RESTORE_ALL + +Luser_return: + /* only allow interrupts when we are really the last one on the*/ + /* kernel stack, otherwise stack overflow can occur during*/ + /* heavy interrupt load*/ + andw #ALLOWINT,%sr + + movel %sp,%d1 /* get thread_info pointer */ + andl #-THREAD_SIZE,%d1 + movel %d1,%a2 +1: + move %a2@(TINFO_FLAGS),%d1 /* thread_info->flags */ + jne Lwork_to_do + RESTORE_ALL + +Lwork_to_do: + movel %a2@(TINFO_FLAGS),%d1 /* thread_info->flags */ + btst #TIF_NEED_RESCHED,%d1 + jne reschedule + +Lsignal_return: + subql #4,%sp /* dummy return address*/ + SAVE_SWITCH_STACK + pea %sp@(SWITCH_STACK_SIZE) + bsrw do_notify_resume + addql #4,%sp + RESTORE_SWITCH_STACK + addql #4,%sp + jra 1b + +/* + * This is the main interrupt handler, responsible for calling process_int() + */ +inthandler1: + SAVE_ALL_INT + movew %sp@(PT_OFF_FORMATVEC), %d0 + and #0x3ff, %d0 + + movel %sp,%sp@- + movel #65,%sp@- /* put vector # on stack*/ + jbsr process_int /* process the IRQ*/ +3: addql #8,%sp /* pop parameters off stack*/ + bra ret_from_exception + +inthandler2: + SAVE_ALL_INT + movew %sp@(PT_OFF_FORMATVEC), %d0 + and #0x3ff, %d0 + + movel %sp,%sp@- + movel #66,%sp@- /* put vector # on stack*/ + jbsr process_int /* process the IRQ*/ +3: addql #8,%sp /* pop parameters off stack*/ + bra ret_from_exception + +inthandler3: + SAVE_ALL_INT + movew %sp@(PT_OFF_FORMATVEC), %d0 + and #0x3ff, %d0 + + movel %sp,%sp@- + movel #67,%sp@- /* put vector # on stack*/ + jbsr process_int /* process the IRQ*/ +3: addql #8,%sp /* pop parameters off stack*/ + bra ret_from_exception + +inthandler4: + SAVE_ALL_INT + movew %sp@(PT_OFF_FORMATVEC), %d0 + and #0x3ff, %d0 + + movel %sp,%sp@- + movel #68,%sp@- /* put vector # on stack*/ + jbsr process_int /* process the IRQ*/ +3: addql #8,%sp /* pop parameters off stack*/ + bra ret_from_exception + +inthandler5: + SAVE_ALL_INT + movew %sp@(PT_OFF_FORMATVEC), %d0 + and #0x3ff, %d0 + + movel %sp,%sp@- + movel #69,%sp@- /* put vector # on stack*/ + jbsr process_int /* process the IRQ*/ +3: addql #8,%sp /* pop parameters off stack*/ + bra ret_from_exception + +inthandler6: + SAVE_ALL_INT + movew %sp@(PT_OFF_FORMATVEC), %d0 + and #0x3ff, %d0 + + movel %sp,%sp@- + movel #70,%sp@- /* put vector # on stack*/ + jbsr process_int /* process the IRQ*/ +3: addql #8,%sp /* pop parameters off stack*/ + bra ret_from_exception + +inthandler7: + SAVE_ALL_INT + movew %sp@(PT_OFF_FORMATVEC), %d0 + and #0x3ff, %d0 + + movel %sp,%sp@- + movel #71,%sp@- /* put vector # on stack*/ + jbsr process_int /* process the IRQ*/ +3: addql #8,%sp /* pop parameters off stack*/ + bra ret_from_exception + +inthandler: + SAVE_ALL_INT + movew %sp@(PT_OFF_FORMATVEC), %d0 + and #0x3ff, %d0 + + movel %sp,%sp@- + movel %d0,%sp@- /* put vector # on stack*/ + jbsr process_int /* process the IRQ*/ +3: addql #8,%sp /* pop parameters off stack*/ + bra ret_from_exception + +/* + * Handler for uninitialized and spurious interrupts. + */ +ENTRY(bad_interrupt) + addql #1,irq_err_count + rte + +/* + * Beware - when entering resume, prev (the current task) is + * in a0, next (the new task) is in a1, so don't change these + * registers until their contents are no longer needed. + */ +ENTRY(resume) + movel %a0,%d1 /* save prev thread in d1 */ + movew %sr,%a0@(TASK_THREAD+THREAD_SR) /* save sr */ + SAVE_SWITCH_STACK + movel %sp,%a0@(TASK_THREAD+THREAD_KSP) /* save kernel stack */ + movel %usp,%a3 /* save usp */ + movel %a3,%a0@(TASK_THREAD+THREAD_USP) + + movel %a1@(TASK_THREAD+THREAD_USP),%a3 /* restore user stack */ + movel %a3,%usp + movel %a1@(TASK_THREAD+THREAD_KSP),%sp /* restore new thread stack */ + RESTORE_SWITCH_STACK + movew %a1@(TASK_THREAD+THREAD_SR),%sr /* restore thread status reg */ + rts + diff --git a/arch/m68k/68000/head.S b/arch/m68k/68000/head.S new file mode 100644 index 000000000..140220662 --- /dev/null +++ b/arch/m68k/68000/head.S @@ -0,0 +1,241 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * head.S - Common startup code for 68000 core based CPU's + * + * 2012.10.21, Luis Alves , Single head.S file for all + * 68000 core based CPU's. Based on the sources from: + * Coldfire by Greg Ungerer + * 68328 by D. Jeff Dionne , + * Kenneth Albanowski , + * The Silver Hammer Group, Ltd. + * + */ + +#include +#include +#include +#include + + +/***************************************************************************** + * UCSIMM and UCDIMM use CONFIG_MEMORY_RESERVE to reserve some RAM + *****************************************************************************/ +#ifdef CONFIG_MEMORY_RESERVE +#define RAMEND (CONFIG_RAMBASE+CONFIG_RAMSIZE)-(CONFIG_MEMORY_RESERVE*0x100000) +#else +#define RAMEND (CONFIG_RAMBASE+CONFIG_RAMSIZE) +#endif +/*****************************************************************************/ + +.global _start +.global _rambase +.global _ramvec +.global _ramstart +.global _ramend + +#if defined(CONFIG_PILOT) || defined(CONFIG_INIT_LCD) +.global bootlogo_bits +#endif + +/* Defining DEBUG_HEAD_CODE, serial port in 68x328 is inited */ +/* #define DEBUG_HEAD_CODE */ +#undef DEBUG_HEAD_CODE + +.data + +/***************************************************************************** + * RAM setup pointers. Used by the kernel to determine RAM location and size. + *****************************************************************************/ + +_rambase: + .long 0 +_ramvec: + .long 0 +_ramstart: + .long 0 +_ramend: + .long 0 + +__HEAD + +/***************************************************************************** + * Entry point, where all begins! + *****************************************************************************/ + +_start: + +/* Pilot need this specific signature at the start of ROM */ +#ifdef CONFIG_PILOT + .byte 0x4e, 0xfa, 0x00, 0x0a /* bra opcode (jmp 10 bytes) */ + .byte 'b', 'o', 'o', 't' + .word 10000 + nop + moveq #0, %d0 + movew %d0, 0xfffff618 /* Watchdog off */ + movel #0x00011f07, 0xfffff114 /* CS A1 Mask */ +#endif /* CONFIG_PILOT */ + + movew #0x2700, %sr /* disable all interrupts */ + +/***************************************************************************** + * Setup PLL and wait for it to settle (in 68x328 cpu's). + * Also, if enabled, init serial port. + *****************************************************************************/ +#if defined(CONFIG_M68328) || \ + defined(CONFIG_M68EZ328) || \ + defined(CONFIG_M68VZ328) + +/* Serial port setup. Should only be needed if debugging this startup code. */ +#ifdef DEBUG_HEAD_CODE + movew #0x0800, 0xfffff906 /* Ignore CTS */ + movew #0x010b, 0xfffff902 /* BAUD to 9600 */ + movew #0xe100, 0xfffff900 /* enable */ +#endif /* DEBUG_HEAD */ + +#ifdef CONFIG_PILOT + movew #0x2410, 0xfffff200 /* PLLCR */ +#else + movew #0x2400, 0xfffff200 /* PLLCR */ +#endif + movew #0x0123, 0xfffff202 /* PLLFSR */ + moveq #0, %d0 + movew #16384, %d0 /* PLL settle wait loop */ +_pll_settle: + subw #1, %d0 + bne _pll_settle +#endif /* CONFIG_M68x328 */ + + +/***************************************************************************** + * If running kernel from ROM some specific initialization has to be done. + * (Assuming that everything is already init'ed when running from RAM) + *****************************************************************************/ +#ifdef CONFIG_ROMKERNEL + +/***************************************************************************** + * Init chip registers (uCsimm specific) + *****************************************************************************/ +#ifdef CONFIG_UCSIMM + moveb #0x00, 0xfffffb0b /* Watchdog off */ + moveb #0x10, 0xfffff000 /* SCR */ + moveb #0x00, 0xfffff40b /* enable chip select */ + moveb #0x00, 0xfffff423 /* enable /DWE */ + moveb #0x08, 0xfffffd0d /* disable hardmap */ + moveb #0x07, 0xfffffd0e /* level 7 interrupt clear */ + movew #0x8600, 0xfffff100 /* FLASH at 0x10c00000 */ + movew #0x018b, 0xfffff110 /* 2Meg, enable, 0ws */ + movew #0x8f00, 0xfffffc00 /* DRAM configuration */ + movew #0x9667, 0xfffffc02 /* DRAM control */ + movew #0x0000, 0xfffff106 /* DRAM at 0x00000000 */ + movew #0x068f, 0xfffff116 /* 8Meg, enable, 0ws */ + moveb #0x40, 0xfffff300 /* IVR */ + movel #0x007FFFFF, %d0 /* IMR */ + movel %d0, 0xfffff304 + moveb 0xfffff42b, %d0 + andb #0xe0, %d0 + moveb %d0, 0xfffff42b +#endif + +/***************************************************************************** + * Init LCD controller. + * (Assuming that LCD controller is already init'ed when running from RAM) + *****************************************************************************/ +#ifdef CONFIG_INIT_LCD +#ifdef CONFIG_PILOT + moveb #0, 0xfffffA27 /* LCKCON */ + movel #_start, 0xfffffA00 /* LSSA */ + moveb #0xa, 0xfffffA05 /* LVPW */ + movew #0x9f, 0xFFFFFa08 /* LXMAX */ + movew #0x9f, 0xFFFFFa0a /* LYMAX */ + moveb #9, 0xfffffa29 /* LBAR */ + moveb #0, 0xfffffa25 /* LPXCD */ + moveb #0x04, 0xFFFFFa20 /* LPICF */ + moveb #0x58, 0xfffffA27 /* LCKCON */ + moveb #0x85, 0xfffff429 /* PFDATA */ + moveb #0xd8, 0xfffffA27 /* LCKCON */ + moveb #0xc5, 0xfffff429 /* PFDATA */ + moveb #0xd5, 0xfffff429 /* PFDATA */ + movel #bootlogo_bits, 0xFFFFFA00 /* LSSA */ + moveb #10, 0xFFFFFA05 /* LVPW */ + movew #160, 0xFFFFFA08 /* LXMAX */ + movew #160, 0xFFFFFA0A /* LYMAX */ +#else /* CONFIG_PILOT */ + movel #bootlogo_bits, 0xfffffA00 /* LSSA */ + moveb #0x28, 0xfffffA05 /* LVPW */ + movew #0x280, 0xFFFFFa08 /* LXMAX */ + movew #0x1df, 0xFFFFFa0a /* LYMAX */ + moveb #0, 0xfffffa29 /* LBAR */ + moveb #0, 0xfffffa25 /* LPXCD */ + moveb #0x08, 0xFFFFFa20 /* LPICF */ + moveb #0x01, 0xFFFFFA21 /* -ve pol */ + moveb #0x81, 0xfffffA27 /* LCKCON */ + movew #0xff00, 0xfffff412 /* LCD pins */ +#endif /* CONFIG_PILOT */ +#endif /* CONFIG_INIT_LCD */ + +/***************************************************************************** + * Kernel is running from FLASH/ROM (XIP) + * Copy init text & data to RAM + *****************************************************************************/ + moveal #_etext, %a0 + moveal #_sdata, %a1 + moveal #__bss_start, %a2 +_copy_initmem: + movel %a0@+, %a1@+ + cmpal %a1, %a2 + bhi _copy_initmem +#endif /* CONFIG_ROMKERNEL */ + +/***************************************************************************** + * Setup basic memory information for kernel + *****************************************************************************/ + movel #CONFIG_VECTORBASE,_ramvec /* set vector base location */ + movel #CONFIG_RAMBASE,_rambase /* set the base of RAM */ + movel #RAMEND, _ramend /* set end ram addr */ + lea __bss_stop,%a1 + movel %a1,_ramstart + +/***************************************************************************** + * If the kernel is in RAM, move romfs to right above bss and + * adjust _ramstart to where romfs ends. + * + * (Do this only if CONFIG_MTD_UCLINUX is true) + *****************************************************************************/ + +#if defined(CONFIG_ROMFS_FS) && defined(CONFIG_RAMKERNEL) && \ + defined(CONFIG_MTD_UCLINUX) + lea __bss_start, %a0 /* get start of bss */ + lea __bss_stop, %a1 /* set up destination */ + movel %a0, %a2 /* copy of bss start */ + + movel 8(%a0), %d0 /* get size of ROMFS */ + addql #8, %d0 /* allow for rounding */ + andl #0xfffffffc, %d0 /* whole words */ + + addl %d0, %a0 /* copy from end */ + addl %d0, %a1 /* copy from end */ + movel %a1, _ramstart /* set start of ram */ +_copy_romfs: + movel -(%a0), -(%a1) /* copy dword */ + cmpl %a0, %a2 /* check if at end */ + bne _copy_romfs +#endif /* CONFIG_ROMFS_FS && CONFIG_RAMKERNEL && CONFIG_MTD_UCLINUX */ + +/***************************************************************************** + * Clear bss region + *****************************************************************************/ + lea __bss_start, %a0 /* get start of bss */ + lea __bss_stop, %a1 /* get end of bss */ +_clear_bss: + movel #0, (%a0)+ /* clear each word */ + cmpl %a0, %a1 /* check if at end */ + bne _clear_bss + +/***************************************************************************** + * Load the current task pointer and stack. + *****************************************************************************/ + lea init_thread_union,%a0 + lea THREAD_SIZE(%a0),%sp + jsr start_kernel /* start Linux kernel */ +_exit: + jmp _exit /* should never get here */ diff --git a/arch/m68k/68000/ints.c b/arch/m68k/68000/ints.c new file mode 100644 index 000000000..cda49b12d --- /dev/null +++ b/arch/m68k/68000/ints.c @@ -0,0 +1,186 @@ +/* + * ints.c - Generic interrupt controller support + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file COPYING in the main directory of this archive + * for more details. + * + * Copyright 1996 Roman Zippel + * Copyright 1999 D. Jeff Dionne + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#if defined(CONFIG_M68328) +#include +#elif defined(CONFIG_M68EZ328) +#include +#elif defined(CONFIG_M68VZ328) +#include +#endif + +/* assembler routines */ +asmlinkage void system_call(void); +asmlinkage void buserr(void); +asmlinkage void trap(void); +asmlinkage void trap3(void); +asmlinkage void trap4(void); +asmlinkage void trap5(void); +asmlinkage void trap6(void); +asmlinkage void trap7(void); +asmlinkage void trap8(void); +asmlinkage void trap9(void); +asmlinkage void trap10(void); +asmlinkage void trap11(void); +asmlinkage void trap12(void); +asmlinkage void trap13(void); +asmlinkage void trap14(void); +asmlinkage void trap15(void); +asmlinkage void trap33(void); +asmlinkage void trap34(void); +asmlinkage void trap35(void); +asmlinkage void trap36(void); +asmlinkage void trap37(void); +asmlinkage void trap38(void); +asmlinkage void trap39(void); +asmlinkage void trap40(void); +asmlinkage void trap41(void); +asmlinkage void trap42(void); +asmlinkage void trap43(void); +asmlinkage void trap44(void); +asmlinkage void trap45(void); +asmlinkage void trap46(void); +asmlinkage void trap47(void); +asmlinkage irqreturn_t bad_interrupt(int, void *); +asmlinkage irqreturn_t inthandler(void); +asmlinkage irqreturn_t inthandler1(void); +asmlinkage irqreturn_t inthandler2(void); +asmlinkage irqreturn_t inthandler3(void); +asmlinkage irqreturn_t inthandler4(void); +asmlinkage irqreturn_t inthandler5(void); +asmlinkage irqreturn_t inthandler6(void); +asmlinkage irqreturn_t inthandler7(void); + +/* The 68k family did not have a good way to determine the source + * of interrupts until later in the family. The EC000 core does + * not provide the vector number on the stack, we vector everything + * into one vector and look in the blasted mask register... + * This code is designed to be fast, almost constant time, not clean! + */ +void process_int(int vec, struct pt_regs *fp) +{ + int irq; + int mask; + + unsigned long pend = ISR; + + while (pend) { + if (pend & 0x0000ffff) { + if (pend & 0x000000ff) { + if (pend & 0x0000000f) { + mask = 0x00000001; + irq = 0; + } else { + mask = 0x00000010; + irq = 4; + } + } else { + if (pend & 0x00000f00) { + mask = 0x00000100; + irq = 8; + } else { + mask = 0x00001000; + irq = 12; + } + } + } else { + if (pend & 0x00ff0000) { + if (pend & 0x000f0000) { + mask = 0x00010000; + irq = 16; + } else { + mask = 0x00100000; + irq = 20; + } + } else { + if (pend & 0x0f000000) { + mask = 0x01000000; + irq = 24; + } else { + mask = 0x10000000; + irq = 28; + } + } + } + + while (! (mask & pend)) { + mask <<=1; + irq++; + } + + do_IRQ(irq, fp); + pend &= ~mask; + } +} + +static void intc_irq_unmask(struct irq_data *d) +{ + IMR &= ~(1 << d->irq); +} + +static void intc_irq_mask(struct irq_data *d) +{ + IMR |= (1 << d->irq); +} + +static struct irq_chip intc_irq_chip = { + .name = "M68K-INTC", + .irq_mask = intc_irq_mask, + .irq_unmask = intc_irq_unmask, +}; + +/* + * This function should be called during kernel startup to initialize + * the machine vector table. + */ +void __init trap_init(void) +{ + int i; + + /* set up the vectors */ + for (i = 72; i < 256; ++i) + _ramvec[i] = (e_vector) bad_interrupt; + + _ramvec[32] = system_call; + + _ramvec[65] = (e_vector) inthandler1; + _ramvec[66] = (e_vector) inthandler2; + _ramvec[67] = (e_vector) inthandler3; + _ramvec[68] = (e_vector) inthandler4; + _ramvec[69] = (e_vector) inthandler5; + _ramvec[70] = (e_vector) inthandler6; + _ramvec[71] = (e_vector) inthandler7; +} + +void __init init_IRQ(void) +{ + int i; + + IVR = 0x40; /* Set DragonBall IVR (interrupt base) to 64 */ + + /* turn off all interrupts */ + IMR = ~0; + + for (i = 0; (i < NR_IRQS); i++) { + irq_set_chip(i, &intc_irq_chip); + irq_set_handler(i, handle_level_irq); + } +} + diff --git a/arch/m68k/68000/m68328.c b/arch/m68k/68000/m68328.c new file mode 100644 index 000000000..419751b15 --- /dev/null +++ b/arch/m68k/68000/m68328.c @@ -0,0 +1,56 @@ +/***************************************************************************/ + +/* + * m68328.c - 68328 specific config + * + * Copyright (C) 1993 Hamish Macdonald + * Copyright (C) 1999 D. Jeff Dionne + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file COPYING in the main directory of this archive + * for more details. + * + * VZ Support/Fixes Evan Stawnyczy + */ + +/***************************************************************************/ + +#include +#include +#include +#include +#include +#include +#if defined(CONFIG_PILOT) || defined(CONFIG_INIT_LCD) +#include "bootlogo.h" +#endif + +/***************************************************************************/ + +int m68328_hwclk(int set, struct rtc_time *t); + +/***************************************************************************/ + +void m68328_reset (void) +{ + local_irq_disable(); + asm volatile ("moveal #0x10c00000, %a0;\n\t" + "moveb #0, 0xFFFFF300;\n\t" + "moveal 0(%a0), %sp;\n\t" + "moveal 4(%a0), %a0;\n\t" + "jmp (%a0);"); +} + +/***************************************************************************/ + +void __init config_BSP(char *command, int len) +{ + pr_info("68328 support D. Jeff Dionne \n"); + pr_info("68328 support Kenneth Albanowski \n"); + pr_info("68328/Pilot support Bernhard Kuhn \n"); + + mach_hwclk = m68328_hwclk; + mach_reset = m68328_reset; +} + +/***************************************************************************/ diff --git a/arch/m68k/68000/m68EZ328.c b/arch/m68k/68000/m68EZ328.c new file mode 100644 index 000000000..05f137dc2 --- /dev/null +++ b/arch/m68k/68000/m68EZ328.c @@ -0,0 +1,77 @@ +/***************************************************************************/ + +/* + * m68EZ328.c - 68EZ328 specific config + * + * Copyright (C) 1993 Hamish Macdonald + * Copyright (C) 1999 D. Jeff Dionne + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file COPYING in the main directory of this archive + * for more details. + */ + +/***************************************************************************/ + +#include +#include +#include +#include +#include +#include +#include +#ifdef CONFIG_UCSIMM +#include +#endif + +/***************************************************************************/ + +int m68328_hwclk(int set, struct rtc_time *t); + +/***************************************************************************/ + +void m68ez328_reset(void) +{ + local_irq_disable(); + asm volatile ( + "moveal #0x10c00000, %a0;\n" + "moveb #0, 0xFFFFF300;\n" + "moveal 0(%a0), %sp;\n" + "moveal 4(%a0), %a0;\n" + "jmp (%a0);\n" + ); +} + +/***************************************************************************/ + +unsigned char *cs8900a_hwaddr; +static int errno; + +#ifdef CONFIG_UCSIMM +_bsc0(char *, getserialnum) +_bsc1(unsigned char *, gethwaddr, int, a) +_bsc1(char *, getbenv, char *, a) +#endif + +void __init config_BSP(char *command, int len) +{ + unsigned char *p; + + pr_info("68EZ328 DragonBallEZ support (C) 1999 Rt-Control, Inc\n"); + +#ifdef CONFIG_UCSIMM + pr_info("uCsimm serial string [%s]\n", getserialnum()); + p = cs8900a_hwaddr = gethwaddr(0); + pr_info("uCsimm hwaddr %pM\n", p); + + p = getbenv("APPEND"); + if (p) strcpy(p,command); + else command[0] = 0; +#endif + + mach_sched_init = hw_timer_init; + mach_hwclk = m68328_hwclk; + mach_reset = m68ez328_reset; +} + +/***************************************************************************/ diff --git a/arch/m68k/68000/m68VZ328.c b/arch/m68k/68000/m68VZ328.c new file mode 100644 index 000000000..ada87b23a --- /dev/null +++ b/arch/m68k/68000/m68VZ328.c @@ -0,0 +1,189 @@ +/***************************************************************************/ + +/* + * m68VZ328.c - 68VZ328 specific config + * + * Copyright (C) 1993 Hamish Macdonald + * Copyright (C) 1999 D. Jeff Dionne + * Copyright (C) 2001 Georges Menie, Ken Desmet + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file COPYING in the main directory of this archive + * for more details. + */ + +/***************************************************************************/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +#ifdef CONFIG_INIT_LCD +#include "bootlogo-vz.h" +#endif + +/***************************************************************************/ + +int m68328_hwclk(int set, struct rtc_time *t); + +/***************************************************************************/ +/* Init Drangon Engine hardware */ +/***************************************************************************/ +#if defined(CONFIG_DRAGEN2) + +static void m68vz328_reset(void) +{ + local_irq_disable(); + +#ifdef CONFIG_INIT_LCD + PBDATA |= 0x20; /* disable CCFL light */ + PKDATA |= 0x4; /* disable LCD controller */ + LCKCON = 0; +#endif + + __asm__ __volatile__( + "reset\n\t" + "moveal #0x04000000, %a0\n\t" + "moveal 0(%a0), %sp\n\t" + "moveal 4(%a0), %a0\n\t" + "jmp (%a0)" + ); +} + +static void __init init_hardware(char *command, int size) +{ +#ifdef CONFIG_DIRECT_IO_ACCESS + SCR = 0x10; /* allow user access to internal registers */ +#endif + + /* CSGB Init */ + CSGBB = 0x4000; + CSB = 0x1a1; + + /* CS8900 init */ + /* PK3: hardware sleep function pin, active low */ + PKSEL |= PK(3); /* select pin as I/O */ + PKDIR |= PK(3); /* select pin as output */ + PKDATA |= PK(3); /* set pin high */ + + /* PF5: hardware reset function pin, active high */ + PFSEL |= PF(5); /* select pin as I/O */ + PFDIR |= PF(5); /* select pin as output */ + PFDATA &= ~PF(5); /* set pin low */ + + /* cs8900 hardware reset */ + PFDATA |= PF(5); + { int i; for (i = 0; i < 32000; ++i); } + PFDATA &= ~PF(5); + + /* INT1 enable (cs8900 IRQ) */ + PDPOL &= ~PD(1); /* active high signal */ + PDIQEG &= ~PD(1); + PDIRQEN |= PD(1); /* IRQ enabled */ + +#ifdef CONFIG_INIT_LCD + /* initialize LCD controller */ + LSSA = (long) screen_bits; + LVPW = 0x14; + LXMAX = 0x140; + LYMAX = 0xef; + LRRA = 0; + LPXCD = 3; + LPICF = 0x08; + LPOLCF = 0; + LCKCON = 0x80; + PCPDEN = 0xff; + PCSEL = 0; + + /* Enable LCD controller */ + PKDIR |= 0x4; + PKSEL |= 0x4; + PKDATA &= ~0x4; + + /* Enable CCFL backlighting circuit */ + PBDIR |= 0x20; + PBSEL |= 0x20; + PBDATA &= ~0x20; + + /* contrast control register */ + PFDIR |= 0x1; + PFSEL &= ~0x1; + PWMR = 0x037F; +#endif +} + +/***************************************************************************/ +/* Init RT-Control uCdimm hardware */ +/***************************************************************************/ +#elif defined(CONFIG_UCDIMM) + +static void m68vz328_reset(void) +{ + local_irq_disable(); + asm volatile ( + "moveal #0x10c00000, %a0;\n\t" + "moveb #0, 0xFFFFF300;\n\t" + "moveal 0(%a0), %sp;\n\t" + "moveal 4(%a0), %a0;\n\t" + "jmp (%a0);\n" + ); +} + +unsigned char *cs8900a_hwaddr; +static int errno; + +_bsc0(char *, getserialnum) +_bsc1(unsigned char *, gethwaddr, int, a) +_bsc1(char *, getbenv, char *, a) + +static void __init init_hardware(char *command, int size) +{ + char *p; + + pr_info("uCdimm serial string [%s]\n", getserialnum()); + p = cs8900a_hwaddr = gethwaddr(0); + pr_info("uCdimm hwaddr %pM\n", p); + p = getbenv("APPEND"); + if (p) + strcpy(p, command); + else + command[0] = 0; +} + +/***************************************************************************/ +#else + +static void m68vz328_reset(void) +{ +} + +static void __init init_hardware(char *command, int size) +{ +} + +/***************************************************************************/ +#endif +/***************************************************************************/ + +void __init config_BSP(char *command, int size) +{ + pr_info("68VZ328 DragonBallVZ support (c) 2001 Lineo, Inc.\n"); + + init_hardware(command, size); + + mach_sched_init = hw_timer_init; + mach_hwclk = m68328_hwclk; + mach_reset = m68vz328_reset; +} + +/***************************************************************************/ diff --git a/arch/m68k/68000/romvec.S b/arch/m68k/68000/romvec.S new file mode 100644 index 000000000..15c70cd64 --- /dev/null +++ b/arch/m68k/68000/romvec.S @@ -0,0 +1,35 @@ +/* + * romvec.S - Vector table for 68000 cpus + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file COPYING in the main directory of this archive + * for more details. + * + * Copyright 1996 Roman Zippel + * Copyright 1999 D. Jeff Dionne + * Copyright 2006 Greg Ungerer + */ + +.global _start +.global _buserr +.global trap +.global system_call + +.section .romvec + +e_vectors: +.long CONFIG_RAMBASE+CONFIG_RAMSIZE-4, _start, buserr, trap +.long trap, trap, trap, trap +.long trap, trap, trap, trap +.long trap, trap, trap, trap +.long trap, trap, trap, trap +.long trap, trap, trap, trap +.long trap, trap, trap, trap +.long trap, trap, trap, trap +/* TRAP #0-15 */ +.long system_call, trap, trap, trap +.long trap, trap, trap, trap +.long trap, trap, trap, trap +.long trap, trap, trap, trap +.long 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 + diff --git a/arch/m68k/68000/timers.c b/arch/m68k/68000/timers.c new file mode 100644 index 000000000..e8dfdd255 --- /dev/null +++ b/arch/m68k/68000/timers.c @@ -0,0 +1,136 @@ +/***************************************************************************/ + +/* + * timers.c - Generic hardware timer support. + * + * Copyright (C) 1993 Hamish Macdonald + * Copyright (C) 1999 D. Jeff Dionne + * Copyright (C) 2001 Georges Menie, Ken Desmet + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file COPYING in the main directory of this archive + * for more details. + */ + +/***************************************************************************/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/***************************************************************************/ + +#if defined(CONFIG_DRAGEN2) +/* with a 33.16 MHz clock, this will give usec resolution to the time functions */ +#define CLOCK_SOURCE TCTL_CLKSOURCE_SYSCLK +#define CLOCK_PRE 7 +#define TICKS_PER_JIFFY 41450 + +#elif defined(CONFIG_XCOPILOT_BUGS) +/* + * The only thing I know is that CLK32 is not available on Xcopilot + * I have little idea about what frequency SYSCLK has on Xcopilot. + * The values for prescaler and compare registers were simply + * taken from the original source + */ +#define CLOCK_SOURCE TCTL_CLKSOURCE_SYSCLK +#define CLOCK_PRE 2 +#define TICKS_PER_JIFFY 0xd7e4 + +#else +/* default to using the 32Khz clock */ +#define CLOCK_SOURCE TCTL_CLKSOURCE_32KHZ +#define CLOCK_PRE 31 +#define TICKS_PER_JIFFY 10 +#endif + +static u32 m68328_tick_cnt; +static irq_handler_t timer_interrupt; + +/***************************************************************************/ + +static irqreturn_t hw_tick(int irq, void *dummy) +{ + /* Reset Timer1 */ + TSTAT &= 0; + + m68328_tick_cnt += TICKS_PER_JIFFY; + return timer_interrupt(irq, dummy); +} + +/***************************************************************************/ + +static u64 m68328_read_clk(struct clocksource *cs) +{ + unsigned long flags; + u32 cycles; + + local_irq_save(flags); + cycles = m68328_tick_cnt + TCN; + local_irq_restore(flags); + + return cycles; +} + +/***************************************************************************/ + +static struct clocksource m68328_clk = { + .name = "timer", + .rating = 250, + .read = m68328_read_clk, + .mask = CLOCKSOURCE_MASK(32), + .flags = CLOCK_SOURCE_IS_CONTINUOUS, +}; + +/***************************************************************************/ + +void hw_timer_init(irq_handler_t handler) +{ + int ret; + + /* disable timer 1 */ + TCTL = 0; + + /* set ISR */ + ret = request_irq(TMR_IRQ_NUM, hw_tick, IRQF_TIMER, "timer", NULL); + if (ret) { + pr_err("Failed to request irq %d (timer): %pe\n", TMR_IRQ_NUM, + ERR_PTR(ret)); + } + + /* Restart mode, Enable int, Set clock source */ + TCTL = TCTL_OM | TCTL_IRQEN | CLOCK_SOURCE; + TPRER = CLOCK_PRE; + TCMP = TICKS_PER_JIFFY; + + /* Enable timer 1 */ + TCTL |= TCTL_TEN; + clocksource_register_hz(&m68328_clk, TICKS_PER_JIFFY*HZ); + timer_interrupt = handler; +} + +/***************************************************************************/ + +int m68328_hwclk(int set, struct rtc_time *t) +{ + if (!set) { + long now = RTCTIME; + t->tm_year = 1; + t->tm_mon = 0; + t->tm_mday = 1; + t->tm_hour = (now >> 24) % 24; + t->tm_min = (now >> 16) % 60; + t->tm_sec = now % 60; + } + + return 0; +} + +/***************************************************************************/ diff --git a/arch/m68k/Kbuild b/arch/m68k/Kbuild new file mode 100644 index 000000000..18abb35c2 --- /dev/null +++ b/arch/m68k/Kbuild @@ -0,0 +1,19 @@ +# SPDX-License-Identifier: GPL-2.0-only +obj-y += kernel/ mm/ +obj-$(CONFIG_Q40) += q40/ +obj-$(CONFIG_AMIGA) += amiga/ +obj-$(CONFIG_ATARI) += atari/ +obj-$(CONFIG_MAC) += mac/ +obj-$(CONFIG_HP300) += hp300/ +obj-$(CONFIG_APOLLO) += apollo/ +obj-$(CONFIG_MVME147) += mvme147/ +obj-$(CONFIG_MVME16x) += mvme16x/ +obj-$(CONFIG_BVME6000) += bvme6000/ +obj-$(CONFIG_SUN3X) += sun3x/ sun3/ +obj-$(CONFIG_SUN3) += sun3/ +obj-$(CONFIG_NATFEAT) += emu/ +obj-$(CONFIG_M68040) += fpsp040/ +obj-$(CONFIG_M68060) += ifpsp060/ +obj-$(CONFIG_M68KFPU_EMU) += math-emu/ +obj-$(CONFIG_M68000) += 68000/ +obj-$(CONFIG_COLDFIRE) += coldfire/ diff --git a/arch/m68k/Kconfig b/arch/m68k/Kconfig new file mode 100644 index 000000000..ad7a4ffd6 --- /dev/null +++ b/arch/m68k/Kconfig @@ -0,0 +1,146 @@ +# SPDX-License-Identifier: GPL-2.0 +config M68K + bool + default y + select ARCH_32BIT_OFF_T + select ARCH_HAS_BINFMT_FLAT + select ARCH_HAS_CPU_FINALIZE_INIT if MMU + select ARCH_HAS_DMA_PREP_COHERENT if HAS_DMA && MMU && !COLDFIRE + select ARCH_HAS_SYNC_DMA_FOR_DEVICE if HAS_DMA + select ARCH_HAVE_NMI_SAFE_CMPXCHG if RMW_INSNS + select ARCH_MIGHT_HAVE_PC_PARPORT if ISA + select ARCH_NO_PREEMPT if !COLDFIRE + select ARCH_WANT_IPC_PARSE_VERSION + select BINFMT_FLAT_ARGVP_ENVP_ON_STACK + select DMA_DIRECT_REMAP if HAS_DMA && MMU && !COLDFIRE + select GENERIC_ATOMIC64 + select GENERIC_CPU_DEVICES + select GENERIC_IOMAP + select GENERIC_IRQ_SHOW + select GENERIC_STRNCPY_FROM_USER if MMU + select GENERIC_STRNLEN_USER if MMU + select HAVE_AOUT if MMU + select HAVE_ASM_MODVERSIONS + select HAVE_DEBUG_BUGVERBOSE + select HAVE_FUTEX_CMPXCHG if MMU && FUTEX + select HAVE_IDE + select HAVE_MOD_ARCH_SPECIFIC + select HAVE_UID16 + select MMU_GATHER_NO_RANGE if MMU + select MODULES_USE_ELF_REL + select MODULES_USE_ELF_RELA + select NO_DMA if !MMU && !COLDFIRE + select OLD_SIGACTION + select OLD_SIGSUSPEND3 + select SET_FS + select UACCESS_MEMCPY if !MMU + select VIRT_TO_BUS + +config CPU_BIG_ENDIAN + def_bool y + +config ARCH_HAS_ILOG2_U32 + bool + +config ARCH_HAS_ILOG2_U64 + bool + +config GENERIC_HWEIGHT + bool + default y + +config GENERIC_CALIBRATE_DELAY + bool + default y + +config GENERIC_CSUM + bool + +config TIME_LOW_RES + bool + default y + +config NO_IOPORT_MAP + def_bool y + +config ZONE_DMA + bool + default y + +config HZ + int + default 1000 if CLEOPATRA + default 100 + +config PGTABLE_LEVELS + default 2 if SUN3 || COLDFIRE + default 3 + +config MMU + bool "MMU-based Paged Memory Management Support" + default y + help + Select if you want MMU-based virtualised addressing space + support by paged memory management. If unsure, say 'Y'. + +config MMU_MOTOROLA + bool + +config MMU_COLDFIRE + bool + +config MMU_SUN3 + bool + depends on MMU && !MMU_MOTOROLA && !MMU_COLDFIRE + +config KEXEC + bool "kexec system call" + depends on M68KCLASSIC + select KEXEC_CORE + help + kexec is a system call that implements the ability to shutdown your + current kernel, and to start another kernel. It is like a reboot + but it is independent of the system firmware. And like a reboot + you can start any kernel with it, not just Linux. + + The name comes from the similarity to the exec system call. + + It is an ongoing process to be certain the hardware in a machine + is properly shutdown, so do not be surprised if this code does not + initially work for you. As of this writing the exact hardware + interface is strongly in flux, so no good recommendation can be + made. + +config BOOTINFO_PROC + bool "Export bootinfo in procfs" + depends on KEXEC && M68KCLASSIC + help + Say Y to export the bootinfo used to boot the kernel in a + "bootinfo" file in procfs. This is useful with kexec. + +menu "Platform setup" + +source "arch/m68k/Kconfig.cpu" + +source "arch/m68k/Kconfig.machine" + +source "arch/m68k/Kconfig.bus" + +endmenu + +menu "Kernel Features" + +endmenu + +if !MMU +menu "Power management options" + +config PM + bool "Power Management support" + help + Support processor power management modes + +endmenu +endif + +source "arch/m68k/Kconfig.devices" diff --git a/arch/m68k/Kconfig.bus b/arch/m68k/Kconfig.bus new file mode 100644 index 000000000..f1be832e2 --- /dev/null +++ b/arch/m68k/Kconfig.bus @@ -0,0 +1,71 @@ +# SPDX-License-Identifier: GPL-2.0 +if MMU + +comment "Bus Support" + +config DIO + bool "DIO bus support" + depends on HP300 + default y + help + Say Y here to enable support for the "DIO" expansion bus used in + HP300 machines. If you are using such a system you almost certainly + want this. + +config NUBUS + bool + depends on MAC + default y + +config ZORRO + bool "Amiga Zorro (AutoConfig) bus support" + depends on AMIGA + help + This enables support for the Zorro bus in the Amiga. If you have + expansion cards in your Amiga that conform to the Amiga + AutoConfig(tm) specification, say Y, otherwise N. Note that even + expansion cards that do not fit in the Zorro slots but fit in e.g. + the CPU slot may fall in this category, so you have to say Y to let + Linux use these. + +config AMIGA_PCMCIA + bool "Amiga 1200/600 PCMCIA support" + depends on AMIGA + help + Include support in the kernel for pcmcia on Amiga 1200 and Amiga + 600. If you intend to use pcmcia cards say Y; otherwise say N. + +config ISA + bool + depends on Q40 || AMIGA_PCMCIA + default y + help + Find out whether you have ISA slots on your motherboard. ISA is the + name of a bus system, i.e. the way the CPU talks to the other stuff + inside your box. Other bus systems are PCI, EISA, MicroChannel + (MCA) or VESA. ISA is an older system, now being displaced by PCI; + newer boards don't support it. If you have ISA, say Y, otherwise N. + +config ATARI_ROM_ISA + bool "Atari ROM port ISA adapter support" + depends on ATARI + help + This option enables support for the ROM port ISA adapter used to + operate ISA cards on Atari. Only 8 bit cards are supported, and + no interrupt lines are connected. + The only driver currently using this adapter is the EtherNEC + driver for RTL8019AS based NE2000 compatible network cards. + +config GENERIC_ISA_DMA + def_bool ISA + +source "drivers/zorro/Kconfig" + +endif + +if !MMU + +config ISA_DMA_API + def_bool !M5272 + +endif diff --git a/arch/m68k/Kconfig.cpu b/arch/m68k/Kconfig.cpu new file mode 100644 index 000000000..936cd9619 --- /dev/null +++ b/arch/m68k/Kconfig.cpu @@ -0,0 +1,514 @@ +# SPDX-License-Identifier: GPL-2.0 +comment "Processor Type" + +choice + prompt "CPU family support" + default M68KCLASSIC if MMU + default COLDFIRE if !MMU + help + The Freescale (was Motorola) M68K family of processors implements + the full 68000 processor instruction set. + The Freescale ColdFire family of processors is a modern derivative + of the 68000 processor family. They are mainly targeted at embedded + applications, and are all System-On-Chip (SOC) devices, as opposed + to stand alone CPUs. They implement a subset of the original 68000 + processor instruction set. + If you anticipate running this kernel on a computer with a classic + MC68xxx processor, select M68KCLASSIC. + If you anticipate running this kernel on a computer with a ColdFire + processor, select COLDFIRE. + +config M68KCLASSIC + bool "Classic M68K CPU family support" + +config COLDFIRE + bool "Coldfire CPU family support" + select ARCH_HAVE_CUSTOM_GPIO_H + select CPU_HAS_NO_BITFIELDS + select CPU_HAS_NO_CAS + select CPU_HAS_NO_MULDIV64 + select GENERIC_CSUM + select GPIOLIB + select HAVE_LEGACY_CLK + +endchoice + +if M68KCLASSIC + +config M68000 + bool "MC68000" + depends on !MMU + select CPU_HAS_NO_BITFIELDS + select CPU_HAS_NO_CAS + select CPU_HAS_NO_MULDIV64 + select CPU_HAS_NO_UNALIGNED + select GENERIC_CSUM + select CPU_NO_EFFICIENT_FFS + select HAVE_ARCH_HASH + help + The Freescale (was Motorola) 68000 CPU is the first generation of + the well known M68K family of processors. The CPU core as well as + being available as a stand alone CPU was also used in many + System-On-Chip devices (eg 68328, 68302, etc). It does not contain + a paging MMU. + +config MCPU32 + bool + select CPU_HAS_NO_BITFIELDS + select CPU_HAS_NO_CAS + select CPU_HAS_NO_UNALIGNED + select CPU_NO_EFFICIENT_FFS + help + The Freescale (was then Motorola) CPU32 is a CPU core that is + based on the 68020 processor. For the most part it is used in + System-On-Chip parts, and does not contain a paging MMU. + +config M68020 + bool "68020 support" + depends on MMU + select FPU + select CPU_HAS_ADDRESS_SPACES + help + If you anticipate running this kernel on a computer with a MC68020 + processor, say Y. Otherwise, say N. Note that the 68020 requires a + 68851 MMU (Memory Management Unit) to run Linux/m68k, except on the + Sun 3, which provides its own version. + +config M68030 + bool "68030 support" + depends on MMU && !MMU_SUN3 + select FPU + select CPU_HAS_ADDRESS_SPACES + help + If you anticipate running this kernel on a computer with a MC68030 + processor, say Y. Otherwise, say N. Note that a MC68EC030 will not + work, as it does not include an MMU (Memory Management Unit). + +config M68040 + bool "68040 support" + depends on MMU && !MMU_SUN3 + select FPU + select CPU_HAS_ADDRESS_SPACES + help + If you anticipate running this kernel on a computer with a MC68LC040 + or MC68040 processor, say Y. Otherwise, say N. Note that an + MC68EC040 will not work, as it does not include an MMU (Memory + Management Unit). + +config M68060 + bool "68060 support" + depends on MMU && !MMU_SUN3 + select FPU + select CPU_HAS_ADDRESS_SPACES + help + If you anticipate running this kernel on a computer with a MC68060 + processor, say Y. Otherwise, say N. + +config M68328 + bool "MC68328" + depends on !MMU + select M68000 + help + Motorola 68328 processor support. + +config M68EZ328 + bool "MC68EZ328" + depends on !MMU + select M68000 + help + Motorola 68EX328 processor support. + +config M68VZ328 + bool "MC68VZ328" + depends on !MMU + select M68000 + help + Motorola 68VZ328 processor support. + +endif # M68KCLASSIC + +if COLDFIRE + +choice + prompt "ColdFire SoC type" + default M520x + help + Select the type of ColdFire System-on-Chip (SoC) that you want + to build for. + +config M5206 + bool "MCF5206" + depends on !MMU + select COLDFIRE_SW_A7 + select HAVE_MBAR + select CPU_NO_EFFICIENT_FFS + help + Motorola ColdFire 5206 processor support. + +config M5206e + bool "MCF5206e" + depends on !MMU + select COLDFIRE_SW_A7 + select HAVE_MBAR + select CPU_NO_EFFICIENT_FFS + help + Motorola ColdFire 5206e processor support. + +config M520x + bool "MCF520x" + depends on !MMU + select GENERIC_CLOCKEVENTS + select HAVE_CACHE_SPLIT + help + Freescale Coldfire 5207/5208 processor support. + +config M523x + bool "MCF523x" + depends on !MMU + select GENERIC_CLOCKEVENTS + select HAVE_CACHE_SPLIT + select HAVE_IPSBAR + help + Freescale Coldfire 5230/1/2/4/5 processor support + +config M5249 + bool "MCF5249" + depends on !MMU + select COLDFIRE_SW_A7 + select HAVE_MBAR + select CPU_NO_EFFICIENT_FFS + help + Motorola ColdFire 5249 processor support. + +config M525x + bool "MCF525x" + depends on !MMU + select COLDFIRE_SW_A7 + select HAVE_MBAR + select CPU_NO_EFFICIENT_FFS + help + Freescale (Motorola) Coldfire 5251/5253 processor support. + +config M5271 + bool "MCF5271" + depends on !MMU + select M527x + select HAVE_CACHE_SPLIT + select HAVE_IPSBAR + select GENERIC_CLOCKEVENTS + help + Freescale (Motorola) ColdFire 5270/5271 processor support. + +config M5272 + bool "MCF5272" + depends on !MMU + select COLDFIRE_SW_A7 + select HAVE_MBAR + select CPU_NO_EFFICIENT_FFS + help + Motorola ColdFire 5272 processor support. + +config M5275 + bool "MCF5275" + depends on !MMU + select M527x + select HAVE_CACHE_SPLIT + select HAVE_IPSBAR + select GENERIC_CLOCKEVENTS + help + Freescale (Motorola) ColdFire 5274/5275 processor support. + +config M528x + bool "MCF528x" + depends on !MMU + select GENERIC_CLOCKEVENTS + select HAVE_CACHE_SPLIT + select HAVE_IPSBAR + help + Motorola ColdFire 5280/5282 processor support. + +config M5307 + bool "MCF5307" + depends on !MMU + select COLDFIRE_SW_A7 + select HAVE_CACHE_CB + select HAVE_MBAR + select CPU_NO_EFFICIENT_FFS + help + Motorola ColdFire 5307 processor support. + +config M532x + bool "MCF532x" + depends on !MMU + select M53xx + select HAVE_CACHE_CB + help + Freescale (Motorola) ColdFire 532x processor support. + +config M537x + bool "MCF537x" + depends on !MMU + select M53xx + select HAVE_CACHE_CB + help + Freescale ColdFire 537x processor support. + +config M5407 + bool "MCF5407" + depends on !MMU + select COLDFIRE_SW_A7 + select HAVE_CACHE_CB + select HAVE_MBAR + select CPU_NO_EFFICIENT_FFS + help + Motorola ColdFire 5407 processor support. + +config M547x + bool "MCF547x" + select M54xx + select MMU_COLDFIRE if MMU + select FPU if MMU + select HAVE_CACHE_CB + select HAVE_MBAR + select CPU_NO_EFFICIENT_FFS + help + Freescale ColdFire 5470/5471/5472/5473/5474/5475 processor support. + +config M548x + bool "MCF548x" + select MMU_COLDFIRE if MMU + select FPU if MMU + select M54xx + select HAVE_CACHE_CB + select HAVE_MBAR + select CPU_NO_EFFICIENT_FFS + help + Freescale ColdFire 5480/5481/5482/5483/5484/5485 processor support. + +config M5441x + bool "MCF5441x" + select MMU_COLDFIRE if MMU + select GENERIC_CLOCKEVENTS + select HAVE_CACHE_CB + help + Freescale Coldfire 54410/54415/54416/54417/54418 processor support. + +endchoice + +config M527x + bool + +config M53xx + bool + +config M54xx + select HAVE_PCI + bool + +endif # COLDFIRE + + +comment "Processor Specific Options" + +config M68KFPU_EMU + bool "Math emulation support" + depends on M68KCLASSIC && FPU + help + At some point in the future, this will cause floating-point math + instructions to be emulated by the kernel on machines that lack a + floating-point math coprocessor. Thrill-seekers and chronically + sleep-deprived psychotic hacker types can say Y now, everyone else + should probably wait a while. + +config M68KFPU_EMU_EXTRAPREC + bool "Math emulation extra precision" + depends on M68KFPU_EMU + help + The fpu uses normally a few bit more during calculations for + correct rounding, the emulator can (often) do the same but this + extra calculation can cost quite some time, so you can disable + it here. The emulator will then "only" calculate with a 64 bit + mantissa and round slightly incorrect, what is more than enough + for normal usage. + +config M68KFPU_EMU_ONLY + bool "Math emulation only kernel" + depends on M68KFPU_EMU + help + This option prevents any floating-point instructions from being + compiled into the kernel, thereby the kernel doesn't save any + floating point context anymore during task switches, so this + kernel will only be usable on machines without a floating-point + math coprocessor. This makes the kernel a bit faster as no tests + needs to be executed whether a floating-point instruction in the + kernel should be executed or not. + +config ADVANCED + bool "Advanced configuration options" + depends on MMU + help + This gives you access to some advanced options for the CPU. The + defaults should be fine for most users, but these options may make + it possible for you to improve performance somewhat if you know what + you are doing. + + Note that the answer to this question won't directly affect the + kernel: saying N will just cause the configurator to skip all + the questions about these options. + + Most users should say N to this question. + +config RMW_INSNS + bool "Use read-modify-write instructions" + depends on ADVANCED && !CPU_HAS_NO_CAS + help + This allows to use certain instructions that work with indivisible + read-modify-write bus cycles. While this is faster than the + workaround of disabling interrupts, it can conflict with DMA + ( = direct memory access) on many Amiga systems, and it is also said + to destabilize other machines. It is very likely that this will + cause serious problems on any Amiga or Atari Medusa if set. The only + configuration where it should work are 68030-based Ataris, where it + apparently improves performance. But you've been warned! Unless you + really know what you are doing, say N. Try Y only if you're quite + adventurous. + +config SINGLE_MEMORY_CHUNK + bool "Use one physical chunk of memory only" if ADVANCED && !SUN3 + depends on MMU + default y if SUN3 + select NEED_MULTIPLE_NODES + help + Ignore all but the first contiguous chunk of physical memory for VM + purposes. This will save a few bytes kernel size and may speed up + some operations. Say N if not sure. + +config ARCH_DISCONTIGMEM_ENABLE + def_bool MMU && !SINGLE_MEMORY_CHUNK + +config 060_WRITETHROUGH + bool "Use write-through caching for 68060 supervisor accesses" + depends on ADVANCED && M68060 + help + The 68060 generally uses copyback caching of recently accessed data. + Copyback caching means that memory writes will be held in an on-chip + cache and only written back to memory some time later. Saying Y + here will force supervisor (kernel) accesses to use writethrough + caching. Writethrough caching means that data is written to memory + straight away, so that cache and memory data always agree. + Writethrough caching is less efficient, but is needed for some + drivers on 68060 based systems where the 68060 bus snooping signal + is hardwired on. The 53c710 SCSI driver is known to suffer from + this problem. + +config M68K_L2_CACHE + bool + depends on MAC + default y + +config NODES_SHIFT + int + default "3" + depends on !SINGLE_MEMORY_CHUNK + +config CPU_HAS_NO_BITFIELDS + bool + +config CPU_HAS_NO_CAS + bool + +config CPU_HAS_NO_MULDIV64 + bool + +config CPU_HAS_NO_UNALIGNED + bool + +config CPU_HAS_ADDRESS_SPACES + bool + +config FPU + bool + +config COLDFIRE_SW_A7 + bool + +config HAVE_CACHE_SPLIT + bool + +config HAVE_CACHE_CB + bool + +config HAVE_MBAR + bool + +config HAVE_IPSBAR + bool + +config CLOCK_FREQ + int "Set the core clock frequency" + default "25000000" if M5206 + default "54000000" if M5206e + default "166666666" if M520x + default "140000000" if M5249 + default "150000000" if M527x || M523x + default "90000000" if M5307 + default "50000000" if M5407 + default "266000000" if M54xx + default "66666666" + depends on COLDFIRE + help + Define the CPU clock frequency in use. This is the core clock + frequency, it may or may not be the same as the external clock + crystal fitted to your board. Some processors have an internal + PLL and can have their frequency programmed at run time, others + use internal dividers. In general the kernel won't setup a PLL + if it is fitted (there are some exceptions). This value will be + specific to the exact CPU that you are using. + +config OLDMASK + bool "Old mask 5307 (1H55J) silicon" + depends on M5307 + help + Build support for the older revision ColdFire 5307 silicon. + Specifically this is the 1H55J mask revision. + +if HAVE_CACHE_SPLIT +choice + prompt "Split Cache Configuration" + default CACHE_I + +config CACHE_I + bool "Instruction" + help + Use all of the ColdFire CPU cache memory as an instruction cache. + +config CACHE_D + bool "Data" + help + Use all of the ColdFire CPU cache memory as a data cache. + +config CACHE_BOTH + bool "Both" + help + Split the ColdFire CPU cache, and use half as an instruction cache + and half as a data cache. +endchoice +endif + +if HAVE_CACHE_CB +choice + prompt "Data cache mode" + default CACHE_WRITETHRU + +config CACHE_WRITETHRU + bool "Write-through" + help + The ColdFire CPU cache is set into Write-through mode. + +config CACHE_COPYBACK + bool "Copy-back" + help + The ColdFire CPU cache is set into Copy-back mode. +endchoice +endif + diff --git a/arch/m68k/Kconfig.debug b/arch/m68k/Kconfig.debug new file mode 100644 index 000000000..11b306bdd --- /dev/null +++ b/arch/m68k/Kconfig.debug @@ -0,0 +1,50 @@ +# SPDX-License-Identifier: GPL-2.0 + +config BOOTPARAM + bool 'Compiled-in Kernel Boot Parameter' + +config BOOTPARAM_STRING + string 'Kernel Boot Parameter' + default 'console=ttyS0,19200' + depends on BOOTPARAM + +config EARLY_PRINTK + bool "Early printk" + depends on !(SUN3 || M68000 || COLDFIRE) + help + Write kernel log output directly to a serial port. + Where implemented, output goes to the framebuffer as well. + PROM console functionality on Sun 3x is not affected by this option. + + Pass "earlyprintk" on the kernel command line to get a + boot console. + + This is useful for kernel debugging when your machine crashes very + early, i.e. before the normal console driver is loaded. + You should normally say N here, unless you want to debug such a crash. + +if !MMU + +config FULLDEBUG + bool "Full Symbolic/Source Debugging support" + help + Enable debugging symbols on kernel build. + +config HIGHPROFILE + bool "Use fast second timer for profiling" + depends on COLDFIRE + help + Use a fast secondary clock to produce profiling information. + +config NO_KERNEL_MSG + bool "Suppress Kernel BUG Messages" + help + Do not output any debug BUG messages within the kernel. + +config BDM_DISABLE + bool "Disable BDM signals" + depends on COLDFIRE + help + Disable the ColdFire CPU's BDM signals. + +endif diff --git a/arch/m68k/Kconfig.devices b/arch/m68k/Kconfig.devices new file mode 100644 index 000000000..e6e3efac1 --- /dev/null +++ b/arch/m68k/Kconfig.devices @@ -0,0 +1,146 @@ +# SPDX-License-Identifier: GPL-2.0 +if MMU + +config ARCH_MAY_HAVE_PC_FDC + bool + depends on BROKEN && (Q40 || SUN3X) + default y + +menu "Platform devices" + +config HEARTBEAT + bool "Use power LED as a heartbeat" if AMIGA || APOLLO || ATARI || Q40 + default y if !AMIGA && !APOLLO && !ATARI && !Q40 && HP300 + help + Use the power-on LED on your machine as a load meter. The exact + behavior is platform-dependent, but normally the flash frequency is + a hyperbolic function of the 5-minute load average. + +# We have a dedicated heartbeat LED. :-) +config PROC_HARDWARE + bool "/proc/hardware support" + depends on PROC_FS + help + Say Y here to support the /proc/hardware file, which gives you + access to information about the machine you're running on, + including the model, CPU, MMU, clock speed, BogoMIPS rating, + and memory size. + +config NATFEAT + bool "ARAnyM emulator support" + depends on ATARI + help + This option enables support for ARAnyM native features, such as + access to a disk image as /dev/hda. + +config NFBLOCK + tristate "NatFeat block device support" + depends on BLOCK && NATFEAT + help + Say Y to include support for the ARAnyM NatFeat block device + which allows direct access to the hard drives without using + the hardware emulation. + +config NFCON + tristate "NatFeat console driver" + depends on TTY && NATFEAT + help + Say Y to include support for the ARAnyM NatFeat console driver + which allows the console output to be redirected to the stderr + output of ARAnyM. + +config NFETH + tristate "NatFeat Ethernet support" + depends on ETHERNET && NATFEAT + help + Say Y to include support for the ARAnyM NatFeat network device + which will emulate a regular ethernet device while presenting an + ethertap device to the host system. + +config ATARI_ETHERNAT + bool "Atari EtherNAT Ethernet support" + depends on ATARI + help + Say Y to include support for the EtherNAT network adapter for the + CT/60 extension port. + + To compile the actual ethernet driver, choose Y or M for the SMC91X + option in the network device section; the module will be called smc91x. + +config ATARI_ETHERNEC + bool "Atari EtherNEC Ethernet support" + depends on ATARI_ROM_ISA + help + Say Y to include support for the EtherNEC network adapter for the + ROM port. The driver works by polling instead of interrupts, so it + is quite slow. + + This driver also supports the ethernet part of the NetUSBee ROM + port combined Ethernet/USB adapter. + + To compile the actual ethernet driver, choose Y or M in for the NE2000 + option in the network device section; the module will be called ne. + +endmenu + +menu "Character devices" + +config ATARI_DSP56K + tristate "Atari DSP56k support" + depends on ATARI + help + If you want to be able to use the DSP56001 in Falcons, say Y. This + driver is still experimental, and if you don't know what it is, or + if you don't have this processor, just say N. + + To compile this driver as a module, choose M here. + +config AMIGA_BUILTIN_SERIAL + tristate "Amiga builtin serial support" + depends on AMIGA && TTY + help + If you want to use your Amiga's built-in serial port in Linux, + answer Y. + + To compile this driver as a module, choose M here. + +config HPDCA + tristate "HP DCA serial support" + depends on DIO && SERIAL_8250 + help + If you want to use the internal "DCA" serial ports on an HP300 + machine, say Y here. + +config HPAPCI + tristate "HP APCI serial support" + depends on HP300 && SERIAL_8250 + help + If you want to use the internal "APCI" serial ports on an HP400 + machine, say Y here. + +config SERIAL_CONSOLE + bool "Support for serial port console" + depends on AMIGA_BUILTIN_SERIAL=y + help + If you say Y here, it will be possible to use a serial port as the + system console (the system console is the device which receives all + kernel messages and warnings and which allows logins in single user + mode). This could be useful if some terminal or printer is connected + to that serial port. + + Even if you say Y here, the currently visible virtual console + (/dev/tty0) will still be used as the system console by default, but + you can alter that using a kernel command line option such as + "console=ttyS1". (Try "man bootparam" or see the documentation of + your boot loader about how to pass options to the kernel at boot + time.) + + If you don't have a graphical console and you say Y here, the + kernel will automatically use the first serial line, /dev/ttyS0, as + system console. + + If unsure, say N. + +endmenu + +endif diff --git a/arch/m68k/Kconfig.machine b/arch/m68k/Kconfig.machine new file mode 100644 index 000000000..16730561d --- /dev/null +++ b/arch/m68k/Kconfig.machine @@ -0,0 +1,463 @@ +# SPDX-License-Identifier: GPL-2.0 +comment "Machine Types" + +if M68KCLASSIC + +config AMIGA + bool "Amiga support" + depends on MMU + select MMU_MOTOROLA if MMU + help + This option enables support for the Amiga series of computers. If + you plan to use this kernel on an Amiga, say Y here and browse the + material available in ; otherwise say N. + +config ATARI + bool "Atari support" + depends on MMU + select MMU_MOTOROLA if MMU + select HAVE_ARCH_NVRAM_OPS + help + This option enables support for the 68000-based Atari series of + computers (including the TT, Falcon and Medusa). If you plan to use + this kernel on an Atari, say Y here and browse the material + available in ; otherwise say N. + +config ATARI_KBD_CORE + bool + +config MAC + bool "Macintosh support" + depends on MMU + select MMU_MOTOROLA if MMU + select HAVE_ARCH_NVRAM_OPS + help + This option enables support for the Apple Macintosh series of + computers (yes, there is experimental support now, at least for part + of the series). + + Say N unless you're willing to code the remaining necessary support. + ;) + +config APOLLO + bool "Apollo support" + depends on MMU + select MMU_MOTOROLA if MMU + help + Say Y here if you want to run Linux on an MC680x0-based Apollo + Domain workstation such as the DN3500. + +config VME + bool "VME (Motorola and BVM) support" + depends on MMU + select MMU_MOTOROLA if MMU + help + Say Y here if you want to build a kernel for a 680x0 based VME + board. Boards currently supported include Motorola boards MVME147, + MVME162, MVME166, MVME167, MVME172, and MVME177. BVME4000 and + BVME6000 boards from BVM Ltd are also supported. + +config MVME147 + bool "MVME147 support" + depends on MMU + depends on VME + help + Say Y to include support for early Motorola VME boards. This will + build a kernel which can run on MVME147 single-board computers. If + you select this option you will have to select the appropriate + drivers for SCSI, Ethernet and serial ports later on. + +config MVME16x + bool "MVME162, 166 and 167 support" + depends on MMU + depends on VME + help + Say Y to include support for Motorola VME boards. This will build a + kernel which can run on MVME162, MVME166, MVME167, MVME172, and + MVME177 boards. If you select this option you will have to select + the appropriate drivers for SCSI, Ethernet and serial ports later + on. + +config BVME6000 + bool "BVME4000 and BVME6000 support" + depends on MMU + depends on VME + help + Say Y to include support for VME boards from BVM Ltd. This will + build a kernel which can run on BVME4000 and BVME6000 boards. If + you select this option you will have to select the appropriate + drivers for SCSI, Ethernet and serial ports later on. + +config HP300 + bool "HP9000/300 and HP9000/400 support" + depends on MMU + select MMU_MOTOROLA if MMU + help + This option enables support for the HP9000/300 and HP9000/400 series + of workstations. Support for these machines is still somewhat + experimental. If you plan to try to use the kernel on such a machine + say Y here. + Everybody else says N. + +config SUN3X + bool "Sun3x support" + depends on MMU + select MMU_MOTOROLA if MMU + select M68030 + help + This option enables support for the Sun 3x series of workstations. + Be warned that this support is very experimental. + Note that Sun 3x kernels are not compatible with Sun 3 hardware. + General Linux information on the Sun 3x series (now discontinued) + is at . + + If you don't want to compile a kernel for a Sun 3x, say N. + +config Q40 + bool "Q40/Q60 support" + depends on MMU + select MMU_MOTOROLA if MMU + help + The Q40 is a Motorola 68040-based successor to the Sinclair QL + manufactured in Germany. There is an official Q40 home page at + . This option enables support for the Q40 and + Q60. Select your CPU below. For 68LC060 don't forget to enable FPU + emulation. + +config SUN3 + bool "Sun3 support" + depends on MMU + depends on !MMU_MOTOROLA + select MMU_SUN3 if MMU + select NO_DMA + select M68020 + help + This option enables support for the Sun 3 series of workstations + (3/50, 3/60, 3/1xx, 3/2xx systems). Enabling this option requires + that all other hardware types must be disabled, as Sun 3 kernels + are incompatible with all other m68k targets (including Sun 3x!). + + If you don't want to compile a kernel exclusively for a Sun 3, say N. + +endif # M68KCLASSIC + +config PILOT + bool + +config PILOT3 + bool "Pilot 1000/5000, PalmPilot Personal/Pro, or PalmIII support" + depends on M68328 + select PILOT + help + Support for the Palm Pilot 1000/5000, Personal/Pro and PalmIII. + +config XCOPILOT_BUGS + bool "(X)Copilot support" + depends on PILOT3 + help + Support the bugs of Xcopilot. + +config UCSIMM + bool "uCsimm module support" + depends on M68EZ328 + help + Support for the Arcturus Networks uCsimm module. + +config UCDIMM + bool "uDsimm module support" + depends on M68VZ328 + help + Support for the Arcturus Networks uDsimm module. + +config DRAGEN2 + bool "DragenEngine II board support" + depends on M68VZ328 + help + Support for the DragenEngine II board. + +config DIRECT_IO_ACCESS + bool "Allow user to access IO directly" + depends on (UCSIMM || UCDIMM || DRAGEN2) + help + Disable the CPU internal registers protection in user mode, + to allow a user application to read/write them. + +config INIT_LCD + bool "Initialize LCD" + depends on (UCSIMM || UCDIMM || DRAGEN2) + help + Initialize the LCD controller of the 68x328 processor. + +config MEMORY_RESERVE + int "Memory reservation (MiB)" + depends on (UCSIMM || UCDIMM) + default 0 + help + Reserve certain memory regions on 68x328 based boards. + +config ARN5206 + bool "Arnewsh 5206 board support" + depends on M5206 + help + Support for the Arnewsh 5206 board. + +config M5206eC3 + bool "Motorola M5206eC3 board support" + depends on M5206e + help + Support for the Motorola M5206eC3 board. + +config ELITE + bool "Motorola M5206eLITE board support" + depends on M5206e + help + Support for the Motorola M5206eLITE board. + +config M5235EVB + bool "Freescale M5235EVB support" + depends on M523x + help + Support for the Freescale M5235EVB board. + +config M5249C3 + bool "Motorola M5249C3 board support" + depends on M5249 + help + Support for the Motorola M5249C3 board. + +config M5272C3 + bool "Motorola M5272C3 board support" + depends on M5272 + help + Support for the Motorola M5272C3 board. + +config WILDFIRE + bool "Intec Automation Inc. WildFire board support" + depends on M528x + help + Support for the Intec Automation Inc. WildFire. + +config WILDFIREMOD + bool "Intec Automation Inc. WildFire module support" + depends on M528x + help + Support for the Intec Automation Inc. WildFire module. + +config ARN5307 + bool "Arnewsh 5307 board support" + depends on M5307 + help + Support for the Arnewsh 5307 board. + +config M5307C3 + bool "Motorola M5307C3 board support" + depends on M5307 + help + Support for the Motorola M5307C3 board. + +config SECUREEDGEMP3 + bool "SnapGear SecureEdge/MP3 platform support" + depends on M5307 + help + Support for the SnapGear SecureEdge/MP3 platform. + +config M5407C3 + bool "Motorola M5407C3 board support" + depends on M5407 + help + Support for the Motorola M5407C3 board. + +config AMCORE + bool "Sysam AMCORE board support" + depends on M5307 + help + Support for the Sysam AMCORE open-hardware generic board. + +config STMARK2 + bool "Sysam stmark2 board support" + depends on M5441x + help + Support for the Sysam stmark2 open-hardware generic board. + +config FIREBEE + bool "FireBee board support" + depends on M547x + help + Support for the FireBee ColdFire 5475 based board. + +config CLEOPATRA + bool "Feith CLEOPATRA board support" + depends on (M5307 || M5407) + help + Support for the Feith Cleopatra boards. + +config CANCam + bool "Feith CANCam board support" + depends on M5272 + help + Support for the Feith CANCam board. + +config SCALES + bool "Feith SCALES board support" + depends on M5272 + help + Support for the Feith SCALES board. + +config NETtel + bool "SecureEdge/NETtel board support" + depends on (M5206e || M5272 || M5307) + help + Support for the SnapGear NETtel/SecureEdge/SnapGear boards. + +config MOD5272 + bool "Netburner MOD-5272 board support" + depends on M5272 + help + Support for the Netburner MOD-5272 board. + +if !MMU || COLDFIRE + +comment "Machine Options" + +config UBOOT + bool "Support for U-Boot command line parameters" + depends on COLDFIRE + help + If you say Y here kernel will try to collect command + line parameters from the initial u-boot stack. + +config 4KSTACKS + bool "Use 4Kb for kernel stacks instead of 8Kb" + default y + help + If you say Y here the kernel will use a 4Kb stacksize for the + kernel stack attached to each process/thread. This facilitates + running more threads on a system and also reduces the pressure + on the VM subsystem for higher order allocations. + +comment "RAM configuration" + +config RAMBASE + hex "Address of the base of RAM" + default "0" + help + Define the address that RAM starts at. On many platforms this is + 0, the base of the address space. And this is the default. Some + platforms choose to setup their RAM at other addresses within the + processor address space. + +config RAMSIZE + hex "Size of RAM (in bytes), or 0 for automatic" + default "0x400000" + help + Define the size of the system RAM. If you select 0 then the + kernel will try to probe the RAM size at runtime. This is not + supported on all CPU types. + +config VECTORBASE + hex "Address of the base of system vectors" + default "0" + help + Define the address of the system vectors. Commonly this is + put at the start of RAM, but it doesn't have to be. On ColdFire + platforms this address is programmed into the VBR register, thus + actually setting the address to use. + +config MBAR + hex "Address of the MBAR (internal peripherals)" + default "0x10000000" + depends on HAVE_MBAR + help + Define the address of the internal system peripherals. This value + is set in the processors MBAR register. This is generally setup by + the boot loader, and will not be written by the kernel. By far most + ColdFire boards use the default 0x10000000 value, so if unsure then + use this. + +config IPSBAR + hex "Address of the IPSBAR (internal peripherals)" + default "0x40000000" + depends on HAVE_IPSBAR + help + Define the address of the internal system peripherals. This value + is set in the processors IPSBAR register. This is generally setup by + the boot loader, and will not be written by the kernel. By far most + ColdFire boards use the default 0x40000000 value, so if unsure then + use this. + +config KERNELBASE + hex "Address of the base of kernel code" + default "0x400" + help + Typically on m68k systems the kernel will not start at the base + of RAM, but usually some small offset from it. Define the start + address of the kernel here. The most common setup will have the + processor vectors at the base of RAM and then the start of the + kernel. On some platforms some RAM is reserved for boot loaders + and the kernel starts after that. The 0x400 default was based on + a system with the RAM based at address 0, and leaving enough room + for the theoretical maximum number of 256 vectors. + +comment "ROM configuration" + +config ROM + bool "Specify ROM linker regions" + help + Define a ROM region for the linker script. This creates a kernel + that can be stored in flash, with possibly the text, and data + regions being copied out to RAM at startup. + +config ROMBASE + hex "Address of the base of ROM device" + default "0" + depends on ROM + help + Define the address that the ROM region starts at. Some platforms + use this to set their chip select region accordingly for the boot + device. + +config ROMVEC + hex "Address of the base of the ROM vectors" + default "0" + depends on ROM + help + This is almost always the same as the base of the ROM. Since on all + 68000 type variants the vectors are at the base of the boot device + on system startup. + +config ROMSTART + hex "Address of the base of system image in ROM" + default "0x400" + depends on ROM + help + Define the start address of the system image in ROM. Commonly this + is strait after the ROM vectors. + +config ROMSIZE + hex "Size of the ROM device" + default "0x100000" + depends on ROM + help + Size of the ROM device. On some platforms this is used to setup + the chip select that controls the boot ROM device. + +choice + prompt "Kernel executes from" + help + Choose the memory type that the kernel will be running in. + +config RAMKERNEL + bool "RAM" + help + The kernel will be resident in RAM when running. + +config ROMKERNEL + bool "ROM" + help + The kernel will be resident in FLASH/ROM when running. This is + often referred to as Execute-in-Place (XIP), since the kernel + code executes from the position it is stored in the FLASH/ROM. + +endchoice + +endif diff --git a/arch/m68k/Makefile b/arch/m68k/Makefile new file mode 100644 index 000000000..ea14f2046 --- /dev/null +++ b/arch/m68k/Makefile @@ -0,0 +1,146 @@ +# +# m68k/Makefile +# +# This file is included by the global makefile so that you can add your own +# architecture-specific flags and dependencies. Remember to do have actions +# for "archclean" and "archdep" for cleaning up and making dependencies for +# this architecture +# +# This file is subject to the terms and conditions of the GNU General Public +# License. See the file "COPYING" in the main directory of this archive +# for more details. +# +# Copyright (C) 1994 by Hamish Macdonald +# Copyright (C) 2002,2011 Greg Ungerer +# + +KBUILD_DEFCONFIG := multi_defconfig + +ifneq ($(SUBARCH),$(ARCH)) + ifeq ($(CROSS_COMPILE),) + CROSS_COMPILE := $(call cc-cross-prefix, \ + m68k-linux-gnu- m68k-linux- m68k-unknown-linux-gnu-) + endif +endif + +# +# Enable processor type. Ordering of these is important - we want to +# use the minimum processor type of the range we support. The logic +# for 680x0 will only allow use of the -m68060 or -m68040 if no other +# 680x0 type is specified - and no option is specified for 68030 or +# 68020. The other m68k/ColdFire types always specify some type of +# compiler cpu type flag. +# +ifndef CONFIG_M68040 +cpuflags-$(CONFIG_M68060) = -m68060 +endif +ifndef CONFIG_M68060 +cpuflags-$(CONFIG_M68040) = -m68040 +endif +cpuflags-$(CONFIG_M68030) = +cpuflags-$(CONFIG_M68020) = +cpuflags-$(CONFIG_M68000) = -m68000 +cpuflags-$(CONFIG_M5441x) = $(call cc-option,-mcpu=54455,-mcfv4e) +cpuflags-$(CONFIG_M54xx) = $(call cc-option,-mcpu=5475,-m5200) +cpuflags-$(CONFIG_M5407) = $(call cc-option,-mcpu=5407,-m5200) +cpuflags-$(CONFIG_M532x) = $(call cc-option,-mcpu=532x,-m5307) +cpuflags-$(CONFIG_M537x) = $(call cc-option,-mcpu=537x,-m5307) +cpuflags-$(CONFIG_M5307) = $(call cc-option,-mcpu=5307,-m5200) +cpuflags-$(CONFIG_M528x) = $(call cc-option,-mcpu=528x,-m5307) +cpuflags-$(CONFIG_M5275) = $(call cc-option,-mcpu=5275,-m5307) +cpuflags-$(CONFIG_M5272) = $(call cc-option,-mcpu=5272,-m5307) +cpuflags-$(CONFIG_M5271) = $(call cc-option,-mcpu=5271,-m5307) +cpuflags-$(CONFIG_M523x) = $(call cc-option,-mcpu=523x,-m5307) +cpuflags-$(CONFIG_M525x) = $(call cc-option,-mcpu=5253,-m5200) +cpuflags-$(CONFIG_M5249) = $(call cc-option,-mcpu=5249,-m5200) +cpuflags-$(CONFIG_M520x) = $(call cc-option,-mcpu=5208,-m5200) +cpuflags-$(CONFIG_M5206e) = $(call cc-option,-mcpu=5206e,-m5200) +cpuflags-$(CONFIG_M5206) = $(call cc-option,-mcpu=5206,-m5200) + +# Evaluate tune cc-option calls now +cpuflags-y := $(cpuflags-y) + +KBUILD_AFLAGS += $(cpuflags-y) +KBUILD_CFLAGS += $(cpuflags-y) + +KBUILD_CFLAGS += -pipe -ffreestanding + +ifdef CONFIG_MMU +# without -fno-strength-reduce the 53c7xx.c driver fails ;-( +KBUILD_CFLAGS += -fno-strength-reduce -ffixed-a2 +else +# we can use a m68k-linux-gcc toolchain with these in place +KBUILD_CPPFLAGS += -DUTS_SYSNAME=\"uClinux\" +KBUILD_CPPFLAGS += -D__uClinux__ +endif + +KBUILD_LDFLAGS := -m m68kelf + +ifdef CONFIG_SUN3 +LDFLAGS_vmlinux = -N +endif + +CHECKFLAGS += -D__mc68000__ + + +ifdef CONFIG_KGDB +# If configured for kgdb support, include debugging infos and keep the +# frame pointer +KBUILD_CFLAGS := $(subst -fomit-frame-pointer,,$(KBUILD_CFLAGS)) -g +endif + +# +# Select the assembler head startup code. Order is important. The default +# head code is first, processor specific selections can override it after. +# +head-y := arch/m68k/kernel/head.o +head-$(CONFIG_SUN3) := arch/m68k/kernel/sun3-head.o +head-$(CONFIG_M68000) := arch/m68k/68000/head.o +head-$(CONFIG_COLDFIRE) := arch/m68k/coldfire/head.o + +core-y += arch/m68k/ +libs-y += arch/m68k/lib/ + + +all: zImage + +lilo: vmlinux + if [ -f $(INSTALL_PATH)/vmlinux ]; then mv -f $(INSTALL_PATH)/vmlinux $(INSTALL_PATH)/vmlinux.old; fi + if [ -f $(INSTALL_PATH)/System.map ]; then mv -f $(INSTALL_PATH)/System.map $(INSTALL_PATH)/System.old; fi + cat vmlinux > $(INSTALL_PATH)/vmlinux + cp System.map $(INSTALL_PATH)/System.map + if [ -x /sbin/lilo ]; then /sbin/lilo; else /etc/lilo/install; fi + +zImage compressed: vmlinux.gz + +vmlinux.gz: vmlinux + +ifndef CONFIG_KGDB + cp vmlinux vmlinux.tmp + $(STRIP) vmlinux.tmp + $(KGZIP) -9c vmlinux.tmp >vmlinux.gz + rm vmlinux.tmp +else + $(KGZIP) -9c vmlinux >vmlinux.gz +endif + +bzImage: vmlinux.bz2 + +vmlinux.bz2: vmlinux + +ifndef CONFIG_KGDB + cp vmlinux vmlinux.tmp + $(STRIP) vmlinux.tmp + $(KBZIP2) -1c vmlinux.tmp >vmlinux.bz2 + rm vmlinux.tmp +else + $(KBZIP2) -1c vmlinux >vmlinux.bz2 +endif + +CLEAN_FILES += vmlinux.gz vmlinux.bz2 + +archheaders: + $(Q)$(MAKE) $(build)=arch/m68k/kernel/syscalls all + +install: + sh $(srctree)/arch/m68k/install.sh $(KERNELRELEASE) vmlinux.gz System.map "$(INSTALL_PATH)" diff --git a/arch/m68k/amiga/Makefile b/arch/m68k/amiga/Makefile new file mode 100644 index 000000000..d17934237 --- /dev/null +++ b/arch/m68k/amiga/Makefile @@ -0,0 +1,8 @@ +# SPDX-License-Identifier: GPL-2.0-only +# +# Makefile for Linux arch/m68k/amiga source directory +# + +obj-y := config.o amiints.o cia.o chipram.o amisound.o platform.o + +obj-$(CONFIG_AMIGA_PCMCIA) += pcmcia.o diff --git a/arch/m68k/amiga/amiints.c b/arch/m68k/amiga/amiints.c new file mode 100644 index 000000000..7ff739e94 --- /dev/null +++ b/arch/m68k/amiga/amiints.c @@ -0,0 +1,174 @@ +/* + * Amiga Linux interrupt handling code + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file COPYING in the main directory of this archive + * for more details. + */ + +#include +#include +#include +#include + +#include +#include +#include +#include +#include + + +/* + * Enable/disable a particular machine specific interrupt source. + * Note that this may affect other interrupts in case of a shared interrupt. + * This function should only be called for a _very_ short time to change some + * internal data, that may not be changed by the interrupt at the same time. + */ + +static void amiga_irq_enable(struct irq_data *data) +{ + amiga_custom.intena = IF_SETCLR | (1 << (data->irq - IRQ_USER)); +} + +static void amiga_irq_disable(struct irq_data *data) +{ + amiga_custom.intena = 1 << (data->irq - IRQ_USER); +} + +static struct irq_chip amiga_irq_chip = { + .name = "amiga", + .irq_enable = amiga_irq_enable, + .irq_disable = amiga_irq_disable, +}; + + +/* + * The builtin Amiga hardware interrupt handlers. + */ + +static void ami_int1(struct irq_desc *desc) +{ + unsigned short ints = amiga_custom.intreqr & amiga_custom.intenar; + + /* if serial transmit buffer empty, interrupt */ + if (ints & IF_TBE) { + amiga_custom.intreq = IF_TBE; + generic_handle_irq(IRQ_AMIGA_TBE); + } + + /* if floppy disk transfer complete, interrupt */ + if (ints & IF_DSKBLK) { + amiga_custom.intreq = IF_DSKBLK; + generic_handle_irq(IRQ_AMIGA_DSKBLK); + } + + /* if software interrupt set, interrupt */ + if (ints & IF_SOFT) { + amiga_custom.intreq = IF_SOFT; + generic_handle_irq(IRQ_AMIGA_SOFT); + } +} + +static void ami_int3(struct irq_desc *desc) +{ + unsigned short ints = amiga_custom.intreqr & amiga_custom.intenar; + + /* if a blitter interrupt */ + if (ints & IF_BLIT) { + amiga_custom.intreq = IF_BLIT; + generic_handle_irq(IRQ_AMIGA_BLIT); + } + + /* if a copper interrupt */ + if (ints & IF_COPER) { + amiga_custom.intreq = IF_COPER; + generic_handle_irq(IRQ_AMIGA_COPPER); + } + + /* if a vertical blank interrupt */ + if (ints & IF_VERTB) { + amiga_custom.intreq = IF_VERTB; + generic_handle_irq(IRQ_AMIGA_VERTB); + } +} + +static void ami_int4(struct irq_desc *desc) +{ + unsigned short ints = amiga_custom.intreqr & amiga_custom.intenar; + + /* if audio 0 interrupt */ + if (ints & IF_AUD0) { + amiga_custom.intreq = IF_AUD0; + generic_handle_irq(IRQ_AMIGA_AUD0); + } + + /* if audio 1 interrupt */ + if (ints & IF_AUD1) { + amiga_custom.intreq = IF_AUD1; + generic_handle_irq(IRQ_AMIGA_AUD1); + } + + /* if audio 2 interrupt */ + if (ints & IF_AUD2) { + amiga_custom.intreq = IF_AUD2; + generic_handle_irq(IRQ_AMIGA_AUD2); + } + + /* if audio 3 interrupt */ + if (ints & IF_AUD3) { + amiga_custom.intreq = IF_AUD3; + generic_handle_irq(IRQ_AMIGA_AUD3); + } +} + +static void ami_int5(struct irq_desc *desc) +{ + unsigned short ints = amiga_custom.intreqr & amiga_custom.intenar; + + /* if serial receive buffer full interrupt */ + if (ints & IF_RBF) { + /* acknowledge of IF_RBF must be done by the serial interrupt */ + generic_handle_irq(IRQ_AMIGA_RBF); + } + + /* if a disk sync interrupt */ + if (ints & IF_DSKSYN) { + amiga_custom.intreq = IF_DSKSYN; + generic_handle_irq(IRQ_AMIGA_DSKSYN); + } +} + + +/* + * void amiga_init_IRQ(void) + * + * Parameters: None + * + * Returns: Nothing + * + * This function should be called during kernel startup to initialize + * the amiga IRQ handling routines. + */ + +void __init amiga_init_IRQ(void) +{ + m68k_setup_irq_controller(&amiga_irq_chip, handle_simple_irq, IRQ_USER, + AMI_STD_IRQS); + + irq_set_chained_handler(IRQ_AUTO_1, ami_int1); + irq_set_chained_handler(IRQ_AUTO_3, ami_int3); + irq_set_chained_handler(IRQ_AUTO_4, ami_int4); + irq_set_chained_handler(IRQ_AUTO_5, ami_int5); + + /* turn off PCMCIA interrupts */ + if (AMIGAHW_PRESENT(PCMCIA)) + gayle.inten = GAYLE_IRQ_IDE; + + /* turn off all interrupts and enable the master interrupt bit */ + amiga_custom.intena = 0x7fff; + amiga_custom.intreq = 0x7fff; + amiga_custom.intena = IF_SETCLR | IF_INTEN; + + cia_init_IRQ(&ciaa_base); + cia_init_IRQ(&ciab_base); +} diff --git a/arch/m68k/amiga/amisound.c b/arch/m68k/amiga/amisound.c new file mode 100644 index 000000000..442bdeee6 --- /dev/null +++ b/arch/m68k/amiga/amisound.c @@ -0,0 +1,116 @@ +/* + * linux/arch/m68k/amiga/amisound.c + * + * amiga sound driver for Linux/m68k + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file COPYING in the main directory of this archive + * for more details. + */ + +#include +#include +#include +#include +#include + +#include + +static unsigned short *snd_data; +static const signed char sine_data[] = { + 0, 39, 75, 103, 121, 127, 121, 103, 75, 39, + 0, -39, -75, -103, -121, -127, -121, -103, -75, -39 +}; +#define DATA_SIZE ARRAY_SIZE(sine_data) + +#define custom amiga_custom + + /* + * The minimum period for audio may be modified by the frame buffer + * device since it depends on htotal (for OCS/ECS/AGA) + */ + +volatile unsigned short amiga_audio_min_period = 124; /* Default for pre-OCS */ +EXPORT_SYMBOL(amiga_audio_min_period); + +#define MAX_PERIOD (65535) + + + /* + * Current period (set by dmasound.c) + */ + +unsigned short amiga_audio_period = MAX_PERIOD; +EXPORT_SYMBOL(amiga_audio_period); + +static unsigned long clock_constant; + +void __init amiga_init_sound(void) +{ + static struct resource beep_res = { .name = "Beep" }; + + snd_data = amiga_chip_alloc_res(sizeof(sine_data), &beep_res); + if (!snd_data) { + pr_crit("amiga init_sound: failed to allocate chipmem\n"); + return; + } + memcpy (snd_data, sine_data, sizeof(sine_data)); + + /* setup divisor */ + clock_constant = (amiga_colorclock+DATA_SIZE/2)/DATA_SIZE; + + /* without amifb, turn video off and enable high quality sound */ +#ifndef CONFIG_FB_AMIGA + amifb_video_off(); +#endif +} + +static void nosound(struct timer_list *unused); +static DEFINE_TIMER(sound_timer, nosound); + +void amiga_mksound( unsigned int hz, unsigned int ticks ) +{ + unsigned long flags; + + if (!snd_data) + return; + + local_irq_save(flags); + del_timer( &sound_timer ); + + if (hz > 20 && hz < 32767) { + unsigned long period = (clock_constant / hz); + + if (period < amiga_audio_min_period) + period = amiga_audio_min_period; + if (period > MAX_PERIOD) + period = MAX_PERIOD; + + /* setup pointer to data, period, length and volume */ + custom.aud[2].audlc = snd_data; + custom.aud[2].audlen = sizeof(sine_data)/2; + custom.aud[2].audper = (unsigned short)period; + custom.aud[2].audvol = 32; /* 50% of maxvol */ + + if (ticks) { + sound_timer.expires = jiffies + ticks; + add_timer( &sound_timer ); + } + + /* turn on DMA for audio channel 2 */ + custom.dmacon = DMAF_SETCLR | DMAF_AUD2; + + } else + nosound( 0 ); + + local_irq_restore(flags); +} + + +static void nosound(struct timer_list *unused) +{ + /* turn off DMA for audio channel 2 */ + custom.dmacon = DMAF_AUD2; + /* restore period to previous value after beeping */ + custom.aud[2].audper = amiga_audio_period; +} diff --git a/arch/m68k/amiga/chipram.c b/arch/m68k/amiga/chipram.c new file mode 100644 index 000000000..a537953bc --- /dev/null +++ b/arch/m68k/amiga/chipram.c @@ -0,0 +1,124 @@ +// SPDX-License-Identifier: GPL-2.0 +/* +** linux/amiga/chipram.c +** +** Modified 03-May-94 by Geert Uytterhoeven +** - 64-bit aligned allocations for full AGA compatibility +** +** Rewritten 15/9/2000 by Geert to use resource management +*/ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +unsigned long amiga_chip_size; +EXPORT_SYMBOL(amiga_chip_size); + +static struct resource chipram_res = { + .name = "Chip RAM", .start = CHIP_PHYSADDR +}; +static atomic_t chipavail; + + +void __init amiga_chip_init(void) +{ + if (!AMIGAHW_PRESENT(CHIP_RAM)) + return; + + chipram_res.end = CHIP_PHYSADDR + amiga_chip_size - 1; + request_resource(&iomem_resource, &chipram_res); + + atomic_set(&chipavail, amiga_chip_size); +} + + +void *amiga_chip_alloc(unsigned long size, const char *name) +{ + struct resource *res; + void *p; + + res = kzalloc(sizeof(struct resource), GFP_KERNEL); + if (!res) + return NULL; + + res->name = name; + p = amiga_chip_alloc_res(size, res); + if (!p) { + kfree(res); + return NULL; + } + + return p; +} +EXPORT_SYMBOL(amiga_chip_alloc); + + + /* + * Warning: + * amiga_chip_alloc_res is meant only for drivers that need to + * allocate Chip RAM before kmalloc() is functional. As a consequence, + * those drivers must not free that Chip RAM afterwards. + */ + +void *amiga_chip_alloc_res(unsigned long size, struct resource *res) +{ + int error; + + /* round up */ + size = PAGE_ALIGN(size); + + pr_debug("amiga_chip_alloc_res: allocate %lu bytes\n", size); + error = allocate_resource(&chipram_res, res, size, 0, UINT_MAX, + PAGE_SIZE, NULL, NULL); + if (error < 0) { + pr_err("amiga_chip_alloc_res: allocate_resource() failed %d!\n", + error); + return NULL; + } + + atomic_sub(size, &chipavail); + pr_debug("amiga_chip_alloc_res: returning %pR\n", res); + return ZTWO_VADDR(res->start); +} + +void amiga_chip_free(void *ptr) +{ + unsigned long start = ZTWO_PADDR(ptr); + struct resource *res; + unsigned long size; + + res = lookup_resource(&chipram_res, start); + if (!res) { + pr_err("amiga_chip_free: trying to free nonexistent region at " + "%p\n", ptr); + return; + } + + size = resource_size(res); + pr_debug("amiga_chip_free: free %lu bytes at %p\n", size, ptr); + atomic_add(size, &chipavail); + release_resource(res); + kfree(res); +} +EXPORT_SYMBOL(amiga_chip_free); + + +unsigned long amiga_chip_avail(void) +{ + unsigned long n = atomic_read(&chipavail); + + pr_debug("amiga_chip_avail : %lu bytes\n", n); + return n; +} +EXPORT_SYMBOL(amiga_chip_avail); + diff --git a/arch/m68k/amiga/cia.c b/arch/m68k/amiga/cia.c new file mode 100644 index 000000000..b9aee983e --- /dev/null +++ b/arch/m68k/amiga/cia.c @@ -0,0 +1,195 @@ +/* + * linux/arch/m68k/amiga/cia.c - CIA support + * + * Copyright (C) 1996 Roman Zippel + * + * The concept of some functions bases on the original Amiga OS function + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file COPYING in the main directory of this archive + * for more details. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +struct ciabase { + volatile struct CIA *cia; + unsigned char icr_mask, icr_data; + unsigned short int_mask; + int handler_irq, cia_irq, server_irq; + char *name; +} ciaa_base = { + .cia = &ciaa, + .int_mask = IF_PORTS, + .handler_irq = IRQ_AMIGA_PORTS, + .cia_irq = IRQ_AMIGA_CIAA, + .name = "CIAA" +}, ciab_base = { + .cia = &ciab, + .int_mask = IF_EXTER, + .handler_irq = IRQ_AMIGA_EXTER, + .cia_irq = IRQ_AMIGA_CIAB, + .name = "CIAB" +}; + +/* + * Cause or clear CIA interrupts, return old interrupt status. + */ + +unsigned char cia_set_irq(struct ciabase *base, unsigned char mask) +{ + unsigned char old; + + old = (base->icr_data |= base->cia->icr); + if (mask & CIA_ICR_SETCLR) + base->icr_data |= mask; + else + base->icr_data &= ~mask; + if (base->icr_data & base->icr_mask) + amiga_custom.intreq = IF_SETCLR | base->int_mask; + return old & base->icr_mask; +} + +/* + * Enable or disable CIA interrupts, return old interrupt mask, + */ + +unsigned char cia_able_irq(struct ciabase *base, unsigned char mask) +{ + unsigned char old; + + old = base->icr_mask; + base->icr_data |= base->cia->icr; + base->cia->icr = mask; + if (mask & CIA_ICR_SETCLR) + base->icr_mask |= mask; + else + base->icr_mask &= ~mask; + base->icr_mask &= CIA_ICR_ALL; + if (base->icr_data & base->icr_mask) + amiga_custom.intreq = IF_SETCLR | base->int_mask; + return old; +} + +static irqreturn_t cia_handler(int irq, void *dev_id) +{ + struct ciabase *base = dev_id; + int mach_irq; + unsigned char ints; + unsigned long flags; + + /* Interrupts get disabled while the timer irq flag is cleared and + * the timer interrupt serviced. + */ + mach_irq = base->cia_irq; + local_irq_save(flags); + ints = cia_set_irq(base, CIA_ICR_ALL); + amiga_custom.intreq = base->int_mask; + if (ints & 1) + generic_handle_irq(mach_irq); + local_irq_restore(flags); + mach_irq++, ints >>= 1; + for (; ints; mach_irq++, ints >>= 1) { + if (ints & 1) + generic_handle_irq(mach_irq); + } + return IRQ_HANDLED; +} + +static void cia_irq_enable(struct irq_data *data) +{ + unsigned int irq = data->irq; + unsigned char mask; + + if (irq >= IRQ_AMIGA_CIAB) { + mask = 1 << (irq - IRQ_AMIGA_CIAB); + cia_set_irq(&ciab_base, mask); + cia_able_irq(&ciab_base, CIA_ICR_SETCLR | mask); + } else { + mask = 1 << (irq - IRQ_AMIGA_CIAA); + cia_set_irq(&ciaa_base, mask); + cia_able_irq(&ciaa_base, CIA_ICR_SETCLR | mask); + } +} + +static void cia_irq_disable(struct irq_data *data) +{ + unsigned int irq = data->irq; + + if (irq >= IRQ_AMIGA_CIAB) + cia_able_irq(&ciab_base, 1 << (irq - IRQ_AMIGA_CIAB)); + else + cia_able_irq(&ciaa_base, 1 << (irq - IRQ_AMIGA_CIAA)); +} + +static struct irq_chip cia_irq_chip = { + .name = "cia", + .irq_enable = cia_irq_enable, + .irq_disable = cia_irq_disable, +}; + +/* + * Override auto irq 2 & 6 and use them as general chain + * for external interrupts, we link the CIA interrupt sources + * into this chain. + */ + +static void auto_irq_enable(struct irq_data *data) +{ + switch (data->irq) { + case IRQ_AUTO_2: + amiga_custom.intena = IF_SETCLR | IF_PORTS; + break; + case IRQ_AUTO_6: + amiga_custom.intena = IF_SETCLR | IF_EXTER; + break; + } +} + +static void auto_irq_disable(struct irq_data *data) +{ + switch (data->irq) { + case IRQ_AUTO_2: + amiga_custom.intena = IF_PORTS; + break; + case IRQ_AUTO_6: + amiga_custom.intena = IF_EXTER; + break; + } +} + +static struct irq_chip auto_irq_chip = { + .name = "auto", + .irq_enable = auto_irq_enable, + .irq_disable = auto_irq_disable, +}; + +void __init cia_init_IRQ(struct ciabase *base) +{ + m68k_setup_irq_controller(&cia_irq_chip, handle_simple_irq, + base->cia_irq, CIA_IRQS); + + /* clear any pending interrupt and turn off all interrupts */ + cia_set_irq(base, CIA_ICR_ALL); + cia_able_irq(base, CIA_ICR_ALL); + + /* override auto int and install CIA handler */ + m68k_setup_irq_controller(&auto_irq_chip, handle_simple_irq, + base->handler_irq, 1); + m68k_irq_startup_irq(base->handler_irq); + if (request_irq(base->handler_irq, cia_handler, IRQF_SHARED, + base->name, base)) + pr_err("Couldn't register %s interrupt\n", base->name); +} diff --git a/arch/m68k/amiga/config.c b/arch/m68k/amiga/config.c new file mode 100644 index 000000000..bee9f240f --- /dev/null +++ b/arch/m68k/amiga/config.c @@ -0,0 +1,859 @@ +/* + * linux/arch/m68k/amiga/config.c + * + * Copyright (C) 1993 Hamish Macdonald + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file COPYING in the main directory of this archive + * for more details. + */ + +/* + * Miscellaneous Amiga stuff + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +static unsigned long amiga_model; + +unsigned long amiga_eclock; +EXPORT_SYMBOL(amiga_eclock); + +unsigned long amiga_colorclock; +EXPORT_SYMBOL(amiga_colorclock); + +unsigned long amiga_chipset; +EXPORT_SYMBOL(amiga_chipset); + +unsigned char amiga_vblank; +EXPORT_SYMBOL(amiga_vblank); + +static unsigned char amiga_psfreq; + +struct amiga_hw_present amiga_hw_present; +EXPORT_SYMBOL(amiga_hw_present); + +static char s_a500[] __initdata = "A500"; +static char s_a500p[] __initdata = "A500+"; +static char s_a600[] __initdata = "A600"; +static char s_a1000[] __initdata = "A1000"; +static char s_a1200[] __initdata = "A1200"; +static char s_a2000[] __initdata = "A2000"; +static char s_a2500[] __initdata = "A2500"; +static char s_a3000[] __initdata = "A3000"; +static char s_a3000t[] __initdata = "A3000T"; +static char s_a3000p[] __initdata = "A3000+"; +static char s_a4000[] __initdata = "A4000"; +static char s_a4000t[] __initdata = "A4000T"; +static char s_cdtv[] __initdata = "CDTV"; +static char s_cd32[] __initdata = "CD32"; +static char s_draco[] __initdata = "Draco"; +static char *amiga_models[] __initdata = { + [AMI_500-AMI_500] = s_a500, + [AMI_500PLUS-AMI_500] = s_a500p, + [AMI_600-AMI_500] = s_a600, + [AMI_1000-AMI_500] = s_a1000, + [AMI_1200-AMI_500] = s_a1200, + [AMI_2000-AMI_500] = s_a2000, + [AMI_2500-AMI_500] = s_a2500, + [AMI_3000-AMI_500] = s_a3000, + [AMI_3000T-AMI_500] = s_a3000t, + [AMI_3000PLUS-AMI_500] = s_a3000p, + [AMI_4000-AMI_500] = s_a4000, + [AMI_4000T-AMI_500] = s_a4000t, + [AMI_CDTV-AMI_500] = s_cdtv, + [AMI_CD32-AMI_500] = s_cd32, + [AMI_DRACO-AMI_500] = s_draco, +}; + +static char amiga_model_name[13] = "Amiga "; + +static void amiga_sched_init(irq_handler_t handler); +static void amiga_get_model(char *model); +static void amiga_get_hardware_list(struct seq_file *m); +extern void amiga_mksound(unsigned int count, unsigned int ticks); +static void amiga_reset(void); +extern void amiga_init_sound(void); +static void amiga_mem_console_write(struct console *co, const char *b, + unsigned int count); +#ifdef CONFIG_HEARTBEAT +static void amiga_heartbeat(int on); +#endif + +static struct console amiga_console_driver = { + .name = "debug", + .flags = CON_PRINTBUFFER, + .index = -1, +}; + + + /* + * Motherboard Resources present in all Amiga models + */ + +static struct { + struct resource _ciab, _ciaa, _custom, _kickstart; +} mb_resources = { + ._ciab = { + .name = "CIA B", .start = 0x00bfd000, .end = 0x00bfdfff + }, + ._ciaa = { + .name = "CIA A", .start = 0x00bfe000, .end = 0x00bfefff + }, + ._custom = { + .name = "Custom I/O", .start = 0x00dff000, .end = 0x00dfffff + }, + ._kickstart = { + .name = "Kickstart ROM", .start = 0x00f80000, .end = 0x00ffffff + } +}; + +static struct resource ram_resource[NUM_MEMINFO]; + + + /* + * Parse an Amiga-specific record in the bootinfo + */ + +int __init amiga_parse_bootinfo(const struct bi_record *record) +{ + int unknown = 0; + const void *data = record->data; + + switch (be16_to_cpu(record->tag)) { + case BI_AMIGA_MODEL: + amiga_model = be32_to_cpup(data); + break; + + case BI_AMIGA_ECLOCK: + amiga_eclock = be32_to_cpup(data); + break; + + case BI_AMIGA_CHIPSET: + amiga_chipset = be32_to_cpup(data); + break; + + case BI_AMIGA_CHIP_SIZE: + amiga_chip_size = be32_to_cpup(data); + break; + + case BI_AMIGA_VBLANK: + amiga_vblank = *(const __u8 *)data; + break; + + case BI_AMIGA_PSFREQ: + amiga_psfreq = *(const __u8 *)data; + break; + + case BI_AMIGA_AUTOCON: +#ifdef CONFIG_ZORRO + if (zorro_num_autocon < ZORRO_NUM_AUTO) { + const struct ConfigDev *cd = data; + struct zorro_dev_init *dev = &zorro_autocon_init[zorro_num_autocon++]; + dev->rom = cd->cd_Rom; + dev->slotaddr = be16_to_cpu(cd->cd_SlotAddr); + dev->slotsize = be16_to_cpu(cd->cd_SlotSize); + dev->boardaddr = be32_to_cpu(cd->cd_BoardAddr); + dev->boardsize = be32_to_cpu(cd->cd_BoardSize); + } else + pr_warn("amiga_parse_bootinfo: too many AutoConfig devices\n"); +#endif /* CONFIG_ZORRO */ + break; + + case BI_AMIGA_SERPER: + /* serial port period: ignored here */ + break; + + default: + unknown = 1; + } + return unknown; +} + + /* + * Identify builtin hardware + */ + +static void __init amiga_identify(void) +{ + /* Fill in some default values, if necessary */ + if (amiga_eclock == 0) + amiga_eclock = 709379; + + memset(&amiga_hw_present, 0, sizeof(amiga_hw_present)); + + pr_info("Amiga hardware found: "); + if (amiga_model >= AMI_500 && amiga_model <= AMI_DRACO) { + pr_cont("[%s] ", amiga_models[amiga_model-AMI_500]); + strcat(amiga_model_name, amiga_models[amiga_model-AMI_500]); + } + + switch (amiga_model) { + case AMI_UNKNOWN: + break; + + case AMI_600: + case AMI_1200: + AMIGAHW_SET(A1200_IDE); + AMIGAHW_SET(PCMCIA); + fallthrough; + case AMI_500: + case AMI_500PLUS: + case AMI_1000: + case AMI_2000: + case AMI_2500: + AMIGAHW_SET(A2000_CLK); /* Is this correct for all models? */ + break; + + case AMI_3000: + case AMI_3000T: + AMIGAHW_SET(AMBER_FF); + AMIGAHW_SET(MAGIC_REKICK); + fallthrough; + case AMI_3000PLUS: + AMIGAHW_SET(A3000_SCSI); + AMIGAHW_SET(A3000_CLK); + AMIGAHW_SET(ZORRO3); + break; + + case AMI_4000T: + AMIGAHW_SET(A4000_SCSI); + fallthrough; + case AMI_4000: + AMIGAHW_SET(A4000_IDE); + AMIGAHW_SET(A3000_CLK); + AMIGAHW_SET(ZORRO3); + break; + + case AMI_CDTV: + case AMI_CD32: + AMIGAHW_SET(CD_ROM); + AMIGAHW_SET(A2000_CLK); /* Is this correct? */ + break; + + case AMI_DRACO: + panic("No support for Draco yet"); + + default: + panic("Unknown Amiga Model"); + } + + AMIGAHW_SET(AMI_VIDEO); + AMIGAHW_SET(AMI_BLITTER); + AMIGAHW_SET(AMI_AUDIO); + AMIGAHW_SET(AMI_FLOPPY); + AMIGAHW_SET(AMI_KEYBOARD); + AMIGAHW_SET(AMI_MOUSE); + AMIGAHW_SET(AMI_SERIAL); + AMIGAHW_SET(AMI_PARALLEL); + AMIGAHW_SET(CHIP_RAM); + AMIGAHW_SET(PAULA); + + switch (amiga_chipset) { + case CS_OCS: + case CS_ECS: + case CS_AGA: + switch (amiga_custom.deniseid & 0xf) { + case 0x0c: + AMIGAHW_SET(DENISE_HR); + break; + case 0x08: + AMIGAHW_SET(LISA); + break; + default: + AMIGAHW_SET(DENISE); + break; + } + break; + } + switch ((amiga_custom.vposr>>8) & 0x7f) { + case 0x00: + AMIGAHW_SET(AGNUS_PAL); + break; + case 0x10: + AMIGAHW_SET(AGNUS_NTSC); + break; + case 0x20: + case 0x21: + AMIGAHW_SET(AGNUS_HR_PAL); + break; + case 0x30: + case 0x31: + AMIGAHW_SET(AGNUS_HR_NTSC); + break; + case 0x22: + case 0x23: + AMIGAHW_SET(ALICE_PAL); + break; + case 0x32: + case 0x33: + AMIGAHW_SET(ALICE_NTSC); + break; + } + AMIGAHW_SET(ZORRO); + +#define AMIGAHW_ANNOUNCE(name, str) \ + if (AMIGAHW_PRESENT(name)) \ + pr_cont(str) + + AMIGAHW_ANNOUNCE(AMI_VIDEO, "VIDEO "); + AMIGAHW_ANNOUNCE(AMI_BLITTER, "BLITTER "); + AMIGAHW_ANNOUNCE(AMBER_FF, "AMBER_FF "); + AMIGAHW_ANNOUNCE(AMI_AUDIO, "AUDIO "); + AMIGAHW_ANNOUNCE(AMI_FLOPPY, "FLOPPY "); + AMIGAHW_ANNOUNCE(A3000_SCSI, "A3000_SCSI "); + AMIGAHW_ANNOUNCE(A4000_SCSI, "A4000_SCSI "); + AMIGAHW_ANNOUNCE(A1200_IDE, "A1200_IDE "); + AMIGAHW_ANNOUNCE(A4000_IDE, "A4000_IDE "); + AMIGAHW_ANNOUNCE(CD_ROM, "CD_ROM "); + AMIGAHW_ANNOUNCE(AMI_KEYBOARD, "KEYBOARD "); + AMIGAHW_ANNOUNCE(AMI_MOUSE, "MOUSE "); + AMIGAHW_ANNOUNCE(AMI_SERIAL, "SERIAL "); + AMIGAHW_ANNOUNCE(AMI_PARALLEL, "PARALLEL "); + AMIGAHW_ANNOUNCE(A2000_CLK, "A2000_CLK "); + AMIGAHW_ANNOUNCE(A3000_CLK, "A3000_CLK "); + AMIGAHW_ANNOUNCE(CHIP_RAM, "CHIP_RAM "); + AMIGAHW_ANNOUNCE(PAULA, "PAULA "); + AMIGAHW_ANNOUNCE(DENISE, "DENISE "); + AMIGAHW_ANNOUNCE(DENISE_HR, "DENISE_HR "); + AMIGAHW_ANNOUNCE(LISA, "LISA "); + AMIGAHW_ANNOUNCE(AGNUS_PAL, "AGNUS_PAL "); + AMIGAHW_ANNOUNCE(AGNUS_NTSC, "AGNUS_NTSC "); + AMIGAHW_ANNOUNCE(AGNUS_HR_PAL, "AGNUS_HR_PAL "); + AMIGAHW_ANNOUNCE(AGNUS_HR_NTSC, "AGNUS_HR_NTSC "); + AMIGAHW_ANNOUNCE(ALICE_PAL, "ALICE_PAL "); + AMIGAHW_ANNOUNCE(ALICE_NTSC, "ALICE_NTSC "); + AMIGAHW_ANNOUNCE(MAGIC_REKICK, "MAGIC_REKICK "); + AMIGAHW_ANNOUNCE(PCMCIA, "PCMCIA "); + if (AMIGAHW_PRESENT(ZORRO)) + pr_cont("ZORRO%s ", AMIGAHW_PRESENT(ZORRO3) ? "3" : ""); + pr_cont("\n"); + +#undef AMIGAHW_ANNOUNCE +} + + +static unsigned long amiga_random_get_entropy(void) +{ + /* VPOSR/VHPOSR provide at least 17 bits of data changing at 1.79 MHz */ + return *(unsigned long *)&amiga_custom.vposr; +} + + + /* + * Setup the Amiga configuration info + */ + +void __init config_amiga(void) +{ + int i; + + amiga_identify(); + + /* Yuk, we don't have PCI memory */ + iomem_resource.name = "Memory"; + for (i = 0; i < 4; i++) + request_resource(&iomem_resource, &((struct resource *)&mb_resources)[i]); + + mach_sched_init = amiga_sched_init; + mach_init_IRQ = amiga_init_IRQ; + mach_get_model = amiga_get_model; + mach_get_hardware_list = amiga_get_hardware_list; + + /* + * default MAX_DMA=0xffffffff on all machines. If we don't do so, the SCSI + * code will not be able to allocate any mem for transfers, unless we are + * dealing with a Z2 mem only system. /Jes + */ + mach_max_dma_address = 0xffffffff; + + mach_reset = amiga_reset; +#if IS_ENABLED(CONFIG_INPUT_M68K_BEEP) + mach_beep = amiga_mksound; +#endif + +#ifdef CONFIG_HEARTBEAT + mach_heartbeat = amiga_heartbeat; +#endif + + mach_random_get_entropy = amiga_random_get_entropy; + + /* Fill in the clock value (based on the 700 kHz E-Clock) */ + amiga_colorclock = 5*amiga_eclock; /* 3.5 MHz */ + + /* clear all DMA bits */ + amiga_custom.dmacon = DMAF_ALL; + /* ensure that the DMA master bit is set */ + amiga_custom.dmacon = DMAF_SETCLR | DMAF_MASTER; + + /* don't use Z2 RAM as system memory on Z3 capable machines */ + if (AMIGAHW_PRESENT(ZORRO3)) { + int i, j; + u32 disabled_z2mem = 0; + + for (i = 0; i < m68k_num_memory; i++) { + if (m68k_memory[i].addr < 16*1024*1024) { + if (i == 0) { + /* don't cut off the branch we're sitting on */ + pr_warn("Warning: kernel runs in Zorro II memory\n"); + continue; + } + disabled_z2mem += m68k_memory[i].size; + m68k_num_memory--; + for (j = i; j < m68k_num_memory; j++) + m68k_memory[j] = m68k_memory[j+1]; + i--; + } + } + if (disabled_z2mem) + pr_info("%dK of Zorro II memory will not be used as system memory\n", + disabled_z2mem>>10); + } + + /* request all RAM */ + for (i = 0; i < m68k_num_memory; i++) { + ram_resource[i].name = + (m68k_memory[i].addr >= 0x01000000) ? "32-bit Fast RAM" : + (m68k_memory[i].addr < 0x00c00000) ? "16-bit Fast RAM" : + "16-bit Slow RAM"; + ram_resource[i].start = m68k_memory[i].addr; + ram_resource[i].end = m68k_memory[i].addr+m68k_memory[i].size-1; + request_resource(&iomem_resource, &ram_resource[i]); + } + + /* initialize chipram allocator */ + amiga_chip_init(); + + /* our beloved beeper */ + if (AMIGAHW_PRESENT(AMI_AUDIO)) + amiga_init_sound(); + + /* + * if it is an A3000, set the magic bit that forces + * a hard rekick + */ + if (AMIGAHW_PRESENT(MAGIC_REKICK)) + *(unsigned char *)ZTWO_VADDR(0xde0002) |= 0x80; +} + +static u64 amiga_read_clk(struct clocksource *cs); + +static struct clocksource amiga_clk = { + .name = "ciab", + .rating = 250, + .read = amiga_read_clk, + .mask = CLOCKSOURCE_MASK(32), + .flags = CLOCK_SOURCE_IS_CONTINUOUS, +}; + +static unsigned short jiffy_ticks; +static u32 clk_total, clk_offset; + +static irqreturn_t ciab_timer_handler(int irq, void *dev_id) +{ + irq_handler_t timer_routine = dev_id; + + clk_total += jiffy_ticks; + clk_offset = 0; + timer_routine(0, NULL); + + return IRQ_HANDLED; +} + +static void __init amiga_sched_init(irq_handler_t timer_routine) +{ + static struct resource sched_res = { + .name = "timer", .start = 0x00bfd400, .end = 0x00bfd5ff, + }; + jiffy_ticks = DIV_ROUND_CLOSEST(amiga_eclock, HZ); + + if (request_resource(&mb_resources._ciab, &sched_res)) + pr_warn("Cannot allocate ciab.ta{lo,hi}\n"); + ciab.cra &= 0xC0; /* turn off timer A, continuous mode, from Eclk */ + ciab.talo = jiffy_ticks % 256; + ciab.tahi = jiffy_ticks / 256; + + /* install interrupt service routine for CIAB Timer A + * + * Please don't change this to use ciaa, as it interferes with the + * SCSI code. We'll have to take a look at this later + */ + if (request_irq(IRQ_AMIGA_CIAB_TA, ciab_timer_handler, IRQF_TIMER, + "timer", timer_routine)) + pr_err("Couldn't register timer interrupt\n"); + /* start timer */ + ciab.cra |= 0x11; + + clocksource_register_hz(&amiga_clk, amiga_eclock); +} + +static u64 amiga_read_clk(struct clocksource *cs) +{ + unsigned short hi, lo, hi2; + unsigned long flags; + u32 ticks; + + local_irq_save(flags); + + /* read CIA B timer A current value */ + hi = ciab.tahi; + lo = ciab.talo; + hi2 = ciab.tahi; + + if (hi != hi2) { + lo = ciab.talo; + hi = hi2; + } + + ticks = hi << 8 | lo; + + if (ticks > jiffy_ticks / 2) + /* check for pending interrupt */ + if (cia_set_irq(&ciab_base, 0) & CIA_ICR_TA) + clk_offset = jiffy_ticks; + + ticks = jiffy_ticks - ticks; + ticks += clk_offset + clk_total; + + local_irq_restore(flags); + + return ticks; +} + +static void amiga_reset(void) __noreturn; + +static void amiga_reset(void) +{ + unsigned long jmp_addr040 = virt_to_phys(&&jmp_addr_label040); + unsigned long jmp_addr = virt_to_phys(&&jmp_addr_label); + + local_irq_disable(); + if (CPU_IS_040_OR_060) + /* Setup transparent translation registers for mapping + * of 16 MB kernel segment before disabling translation + */ + asm volatile ("\n" + " move.l %0,%%d0\n" + " and.l #0xff000000,%%d0\n" + " or.w #0xe020,%%d0\n" /* map 16 MB, enable, cacheable */ + " .chip 68040\n" + " movec %%d0,%%itt0\n" + " movec %%d0,%%dtt0\n" + " .chip 68k\n" + " jmp %0@\n" + : /* no outputs */ + : "a" (jmp_addr040) + : "d0"); + else + /* for 680[23]0, just disable translation and jump to the physical + * address of the label + */ + asm volatile ("\n" + " pmove %%tc,%@\n" + " bclr #7,%@\n" + " pmove %@,%%tc\n" + " jmp %0@\n" + : /* no outputs */ + : "a" (jmp_addr)); +jmp_addr_label040: + /* disable translation on '040 now */ + asm volatile ("\n" + " moveq #0,%%d0\n" + " .chip 68040\n" + " movec %%d0,%%tc\n" /* disable MMU */ + " .chip 68k\n" + : /* no outputs */ + : /* no inputs */ + : "d0"); + + jmp_addr_label: + /* pickup reset address from AmigaOS ROM, reset devices and jump + * to reset address + */ + asm volatile ("\n" + " move.w #0x2700,%sr\n" + " lea 0x01000000,%a0\n" + " sub.l %a0@(-0x14),%a0\n" + " move.l %a0@(4),%a0\n" + " subq.l #2,%a0\n" + " jra 1f\n" + /* align on a longword boundary */ + " " __ALIGN_STR "\n" + "1:\n" + " reset\n" + " jmp %a0@"); + + for (;;) + ; +} + + + /* + * Debugging + */ + +#define SAVEKMSG_MAXMEM 128*1024 + +#define SAVEKMSG_MAGIC1 0x53415645 /* 'SAVE' */ +#define SAVEKMSG_MAGIC2 0x4B4D5347 /* 'KMSG' */ + +struct savekmsg { + unsigned long magic1; /* SAVEKMSG_MAGIC1 */ + unsigned long magic2; /* SAVEKMSG_MAGIC2 */ + unsigned long magicptr; /* address of magic1 */ + unsigned long size; + char data[]; +}; + +static struct savekmsg *savekmsg; + +static void amiga_mem_console_write(struct console *co, const char *s, + unsigned int count) +{ + if (savekmsg->size + count <= SAVEKMSG_MAXMEM-sizeof(struct savekmsg)) { + memcpy(savekmsg->data + savekmsg->size, s, count); + savekmsg->size += count; + } +} + +static int __init amiga_savekmsg_setup(char *arg) +{ + bool registered; + + if (!MACH_IS_AMIGA || strcmp(arg, "mem")) + return 0; + + if (amiga_chip_size < SAVEKMSG_MAXMEM) { + pr_err("Not enough chipram for debugging\n"); + return -ENOMEM; + } + + /* Just steal the block, the chipram allocator isn't functional yet */ + amiga_chip_size -= SAVEKMSG_MAXMEM; + savekmsg = ZTWO_VADDR(CHIP_PHYSADDR + amiga_chip_size); + savekmsg->magic1 = SAVEKMSG_MAGIC1; + savekmsg->magic2 = SAVEKMSG_MAGIC2; + savekmsg->magicptr = ZTWO_PADDR(savekmsg); + savekmsg->size = 0; + + registered = !!amiga_console_driver.write; + amiga_console_driver.write = amiga_mem_console_write; + if (!registered) + register_console(&amiga_console_driver); + return 0; +} + +early_param("debug", amiga_savekmsg_setup); + +static void amiga_serial_putc(char c) +{ + amiga_custom.serdat = (unsigned char)c | 0x100; + while (!(amiga_custom.serdatr & 0x2000)) + ; +} + +static void amiga_serial_console_write(struct console *co, const char *s, + unsigned int count) +{ + while (count--) { + if (*s == '\n') + amiga_serial_putc('\r'); + amiga_serial_putc(*s++); + } +} + +#if 0 +void amiga_serial_puts(const char *s) +{ + amiga_serial_console_write(NULL, s, strlen(s)); +} + +int amiga_serial_console_wait_key(struct console *co) +{ + int ch; + + while (!(amiga_custom.intreqr & IF_RBF)) + barrier(); + ch = amiga_custom.serdatr & 0xff; + /* clear the interrupt, so that another character can be read */ + amiga_custom.intreq = IF_RBF; + return ch; +} + +void amiga_serial_gets(struct console *co, char *s, int len) +{ + int ch, cnt = 0; + + while (1) { + ch = amiga_serial_console_wait_key(co); + + /* Check for backspace. */ + if (ch == 8 || ch == 127) { + if (cnt == 0) { + amiga_serial_putc('\007'); + continue; + } + cnt--; + amiga_serial_puts("\010 \010"); + continue; + } + + /* Check for enter. */ + if (ch == 10 || ch == 13) + break; + + /* See if line is too long. */ + if (cnt >= len + 1) { + amiga_serial_putc(7); + cnt--; + continue; + } + + /* Store and echo character. */ + s[cnt++] = ch; + amiga_serial_putc(ch); + } + /* Print enter. */ + amiga_serial_puts("\r\n"); + s[cnt] = 0; +} +#endif + +static int __init amiga_debug_setup(char *arg) +{ + bool registered; + + if (!MACH_IS_AMIGA || strcmp(arg, "ser")) + return 0; + + /* no initialization required (?) */ + registered = !!amiga_console_driver.write; + amiga_console_driver.write = amiga_serial_console_write; + if (!registered) + register_console(&amiga_console_driver); + return 0; +} + +early_param("debug", amiga_debug_setup); + +#ifdef CONFIG_HEARTBEAT +static void amiga_heartbeat(int on) +{ + if (on) + ciaa.pra &= ~2; + else + ciaa.pra |= 2; +} +#endif + + /* + * Amiga specific parts of /proc + */ + +static void amiga_get_model(char *model) +{ + strcpy(model, amiga_model_name); +} + + +static void amiga_get_hardware_list(struct seq_file *m) +{ + if (AMIGAHW_PRESENT(CHIP_RAM)) + seq_printf(m, "Chip RAM:\t%ldK\n", amiga_chip_size>>10); + seq_printf(m, "PS Freq:\t%dHz\nEClock Freq:\t%ldHz\n", + amiga_psfreq, amiga_eclock); + if (AMIGAHW_PRESENT(AMI_VIDEO)) { + char *type; + switch (amiga_chipset) { + case CS_OCS: + type = "OCS"; + break; + case CS_ECS: + type = "ECS"; + break; + case CS_AGA: + type = "AGA"; + break; + default: + type = "Old or Unknown"; + break; + } + seq_printf(m, "Graphics:\t%s\n", type); + } + +#define AMIGAHW_ANNOUNCE(name, str) \ + if (AMIGAHW_PRESENT(name)) \ + seq_printf (m, "\t%s\n", str) + + seq_puts(m, "Detected hardware:\n"); + AMIGAHW_ANNOUNCE(AMI_VIDEO, "Amiga Video"); + AMIGAHW_ANNOUNCE(AMI_BLITTER, "Blitter"); + AMIGAHW_ANNOUNCE(AMBER_FF, "Amber Flicker Fixer"); + AMIGAHW_ANNOUNCE(AMI_AUDIO, "Amiga Audio"); + AMIGAHW_ANNOUNCE(AMI_FLOPPY, "Floppy Controller"); + AMIGAHW_ANNOUNCE(A3000_SCSI, "SCSI Controller WD33C93 (A3000 style)"); + AMIGAHW_ANNOUNCE(A4000_SCSI, "SCSI Controller NCR53C710 (A4000T style)"); + AMIGAHW_ANNOUNCE(A1200_IDE, "IDE Interface (A1200 style)"); + AMIGAHW_ANNOUNCE(A4000_IDE, "IDE Interface (A4000 style)"); + AMIGAHW_ANNOUNCE(CD_ROM, "Internal CD ROM drive"); + AMIGAHW_ANNOUNCE(AMI_KEYBOARD, "Keyboard"); + AMIGAHW_ANNOUNCE(AMI_MOUSE, "Mouse Port"); + AMIGAHW_ANNOUNCE(AMI_SERIAL, "Serial Port"); + AMIGAHW_ANNOUNCE(AMI_PARALLEL, "Parallel Port"); + AMIGAHW_ANNOUNCE(A2000_CLK, "Hardware Clock (A2000 style)"); + AMIGAHW_ANNOUNCE(A3000_CLK, "Hardware Clock (A3000 style)"); + AMIGAHW_ANNOUNCE(CHIP_RAM, "Chip RAM"); + AMIGAHW_ANNOUNCE(PAULA, "Paula 8364"); + AMIGAHW_ANNOUNCE(DENISE, "Denise 8362"); + AMIGAHW_ANNOUNCE(DENISE_HR, "Denise 8373"); + AMIGAHW_ANNOUNCE(LISA, "Lisa 8375"); + AMIGAHW_ANNOUNCE(AGNUS_PAL, "Normal/Fat PAL Agnus 8367/8371"); + AMIGAHW_ANNOUNCE(AGNUS_NTSC, "Normal/Fat NTSC Agnus 8361/8370"); + AMIGAHW_ANNOUNCE(AGNUS_HR_PAL, "Fat Hires PAL Agnus 8372"); + AMIGAHW_ANNOUNCE(AGNUS_HR_NTSC, "Fat Hires NTSC Agnus 8372"); + AMIGAHW_ANNOUNCE(ALICE_PAL, "PAL Alice 8374"); + AMIGAHW_ANNOUNCE(ALICE_NTSC, "NTSC Alice 8374"); + AMIGAHW_ANNOUNCE(MAGIC_REKICK, "Magic Hard Rekick"); + AMIGAHW_ANNOUNCE(PCMCIA, "PCMCIA Slot"); +#ifdef CONFIG_ZORRO + if (AMIGAHW_PRESENT(ZORRO)) + seq_printf(m, "\tZorro II%s AutoConfig: %d Expansion " + "Device%s\n", + AMIGAHW_PRESENT(ZORRO3) ? "I" : "", + zorro_num_autocon, zorro_num_autocon == 1 ? "" : "s"); +#endif /* CONFIG_ZORRO */ + +#undef AMIGAHW_ANNOUNCE +} + +/* + * The Amiga keyboard driver needs key_maps, but we cannot export it in + * drivers/char/defkeymap.c, as it is autogenerated + */ +#ifdef CONFIG_HW_CONSOLE +EXPORT_SYMBOL_GPL(key_maps); +#endif diff --git a/arch/m68k/amiga/pcmcia.c b/arch/m68k/amiga/pcmcia.c new file mode 100644 index 000000000..7106f0c36 --- /dev/null +++ b/arch/m68k/amiga/pcmcia.c @@ -0,0 +1,122 @@ +/* +** asm-m68k/pcmcia.c -- Amiga Linux PCMCIA support +** most information was found by disassembling card.resource +** I'm still looking for an official doc ! +** +** Copyright 1997 by Alain Malek +** +** This file is subject to the terms and conditions of the GNU General Public +** License. See the file COPYING in the main directory of this archive +** for more details. +** +** Created: 12/10/97 by Alain Malek +*/ + +#include +#include +#include +#include + +#include +#include + +/* gayle config byte for program voltage and access speed */ +static unsigned char cfg_byte = GAYLE_CFG_0V|GAYLE_CFG_150NS; + +void pcmcia_reset(void) +{ + unsigned long reset_start_time = jiffies; + unsigned char b; + + gayle_reset = 0x00; + while (time_before(jiffies, reset_start_time + 1*HZ/100)); + b = gayle_reset; +} +EXPORT_SYMBOL(pcmcia_reset); + + +/* copy a tuple, including tuple header. return nb bytes copied */ +/* be careful as this may trigger a GAYLE_IRQ_WR interrupt ! */ + +int pcmcia_copy_tuple(unsigned char tuple_id, void *tuple, int max_len) +{ + unsigned char id, *dest; + int cnt, pos, len; + + dest = tuple; + pos = 0; + + id = gayle_attribute[pos]; + + while((id != CISTPL_END) && (pos < 0x10000)) { + len = (int)gayle_attribute[pos+2] + 2; + if (id == tuple_id) { + len = (len > max_len)?max_len:len; + for (cnt = 0; cnt < len; cnt++) { + *dest++ = gayle_attribute[pos+(cnt<<1)]; + } + + return len; + } + pos += len<<1; + id = gayle_attribute[pos]; + } + + return 0; +} +EXPORT_SYMBOL(pcmcia_copy_tuple); + +void pcmcia_program_voltage(int voltage) +{ + unsigned char v; + + switch (voltage) { + case PCMCIA_0V: + v = GAYLE_CFG_0V; + break; + case PCMCIA_5V: + v = GAYLE_CFG_5V; + break; + case PCMCIA_12V: + v = GAYLE_CFG_12V; + break; + default: + v = GAYLE_CFG_0V; + } + + cfg_byte = (cfg_byte & 0xfc) | v; + gayle.config = cfg_byte; + +} +EXPORT_SYMBOL(pcmcia_program_voltage); + +void pcmcia_access_speed(int speed) +{ + unsigned char s; + + if (speed <= PCMCIA_SPEED_100NS) + s = GAYLE_CFG_100NS; + else if (speed <= PCMCIA_SPEED_150NS) + s = GAYLE_CFG_150NS; + else if (speed <= PCMCIA_SPEED_250NS) + s = GAYLE_CFG_250NS; + else + s = GAYLE_CFG_720NS; + + cfg_byte = (cfg_byte & 0xf3) | s; + gayle.config = cfg_byte; +} +EXPORT_SYMBOL(pcmcia_access_speed); + +void pcmcia_write_enable(void) +{ + gayle.cardstatus = GAYLE_CS_WR|GAYLE_CS_DA; +} +EXPORT_SYMBOL(pcmcia_write_enable); + +void pcmcia_write_disable(void) +{ + gayle.cardstatus = 0; +} +EXPORT_SYMBOL(pcmcia_write_disable); + diff --git a/arch/m68k/amiga/platform.c b/arch/m68k/amiga/platform.c new file mode 100644 index 000000000..d34029d7b --- /dev/null +++ b/arch/m68k/amiga/platform.c @@ -0,0 +1,255 @@ +/* + * Copyright (C) 2007-2009 Geert Uytterhoeven + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file COPYING in the main directory of this archive + * for more details. + */ + +#include +#include +#include +#include + +#include +#include +#include + + +#ifdef CONFIG_ZORRO + +static const struct resource zorro_resources[] __initconst = { + /* Zorro II regions (on Zorro II/III) */ + { + .name = "Zorro II exp", + .start = 0x00e80000, + .end = 0x00efffff, + .flags = IORESOURCE_MEM, + }, { + .name = "Zorro II mem", + .start = 0x00200000, + .end = 0x009fffff, + .flags = IORESOURCE_MEM, + }, + /* Zorro III regions (on Zorro III only) */ + { + .name = "Zorro III exp", + .start = 0xff000000, + .end = 0xffffffff, + .flags = IORESOURCE_MEM, + }, { + .name = "Zorro III cfg", + .start = 0x40000000, + .end = 0x7fffffff, + .flags = IORESOURCE_MEM, + } +}; + + +static int __init amiga_init_bus(void) +{ + struct platform_device *pdev; + unsigned int n; + + if (!MACH_IS_AMIGA || !AMIGAHW_PRESENT(ZORRO)) + return -ENODEV; + + n = AMIGAHW_PRESENT(ZORRO3) ? 4 : 2; + pdev = platform_device_register_simple("amiga-zorro", -1, + zorro_resources, n); + return PTR_ERR_OR_ZERO(pdev); +} + +subsys_initcall(amiga_init_bus); + + +static int __init z_dev_present(zorro_id id) +{ + unsigned int i; + + for (i = 0; i < zorro_num_autocon; i++) { + const struct ExpansionRom *rom = &zorro_autocon_init[i].rom; + if (be16_to_cpu(rom->er_Manufacturer) == ZORRO_MANUF(id) && + rom->er_Product == ZORRO_PROD(id)) + return 1; + } + + return 0; +} + +#else /* !CONFIG_ZORRO */ + +static inline int z_dev_present(zorro_id id) { return 0; } + +#endif /* !CONFIG_ZORRO */ + + +static const struct resource a3000_scsi_resource __initconst = { + .start = 0xdd0000, + .end = 0xdd00ff, + .flags = IORESOURCE_MEM, +}; + + +static const struct resource a4000t_scsi_resource __initconst = { + .start = 0xdd0000, + .end = 0xdd0fff, + .flags = IORESOURCE_MEM, +}; + + +static const struct resource a1200_ide_resource __initconst = { + .start = 0xda0000, + .end = 0xda1fff, + .flags = IORESOURCE_MEM, +}; + +static const struct gayle_ide_platform_data a1200_ide_pdata __initconst = { + .base = 0xda0000, + .irqport = 0xda9000, + .explicit_ack = 1, +}; + + +static const struct resource a4000_ide_resource __initconst = { + .start = 0xdd2000, + .end = 0xdd3fff, + .flags = IORESOURCE_MEM, +}; + +static const struct gayle_ide_platform_data a4000_ide_pdata __initconst = { + .base = 0xdd2020, + .irqport = 0xdd3020, + .explicit_ack = 0, +}; + + +static const struct resource amiga_rtc_resource __initconst = { + .start = 0x00dc0000, + .end = 0x00dcffff, + .flags = IORESOURCE_MEM, +}; + + +static int __init amiga_init_devices(void) +{ + struct platform_device *pdev; + int error; + + if (!MACH_IS_AMIGA) + return -ENODEV; + + /* video hardware */ + if (AMIGAHW_PRESENT(AMI_VIDEO)) { + pdev = platform_device_register_simple("amiga-video", -1, NULL, + 0); + if (IS_ERR(pdev)) + return PTR_ERR(pdev); + } + + + /* sound hardware */ + if (AMIGAHW_PRESENT(AMI_AUDIO)) { + pdev = platform_device_register_simple("amiga-audio", -1, NULL, + 0); + if (IS_ERR(pdev)) + return PTR_ERR(pdev); + } + + + /* storage interfaces */ + if (AMIGAHW_PRESENT(AMI_FLOPPY)) { + pdev = platform_device_register_simple("amiga-floppy", -1, + NULL, 0); + if (IS_ERR(pdev)) + return PTR_ERR(pdev); + } + + if (AMIGAHW_PRESENT(A3000_SCSI)) { + pdev = platform_device_register_simple("amiga-a3000-scsi", -1, + &a3000_scsi_resource, 1); + if (IS_ERR(pdev)) + return PTR_ERR(pdev); + } + + if (AMIGAHW_PRESENT(A4000_SCSI)) { + pdev = platform_device_register_simple("amiga-a4000t-scsi", -1, + &a4000t_scsi_resource, + 1); + if (IS_ERR(pdev)) + return PTR_ERR(pdev); + } + + if (AMIGAHW_PRESENT(A1200_IDE) || + z_dev_present(ZORRO_PROD_MTEC_VIPER_MK_V_E_MATRIX_530_SCSI_IDE)) { + pdev = platform_device_register_simple("amiga-gayle-ide", -1, + &a1200_ide_resource, 1); + if (IS_ERR(pdev)) + return PTR_ERR(pdev); + error = platform_device_add_data(pdev, &a1200_ide_pdata, + sizeof(a1200_ide_pdata)); + if (error) + return error; + } + + if (AMIGAHW_PRESENT(A4000_IDE)) { + pdev = platform_device_register_simple("amiga-gayle-ide", -1, + &a4000_ide_resource, 1); + if (IS_ERR(pdev)) + return PTR_ERR(pdev); + error = platform_device_add_data(pdev, &a4000_ide_pdata, + sizeof(a4000_ide_pdata)); + if (error) + return error; + } + + + /* other I/O hardware */ + if (AMIGAHW_PRESENT(AMI_KEYBOARD)) { + pdev = platform_device_register_simple("amiga-keyboard", -1, + NULL, 0); + if (IS_ERR(pdev)) + return PTR_ERR(pdev); + } + + if (AMIGAHW_PRESENT(AMI_MOUSE)) { + pdev = platform_device_register_simple("amiga-mouse", -1, NULL, + 0); + if (IS_ERR(pdev)) + return PTR_ERR(pdev); + } + + if (AMIGAHW_PRESENT(AMI_SERIAL)) { + pdev = platform_device_register_simple("amiga-serial", -1, + NULL, 0); + if (IS_ERR(pdev)) + return PTR_ERR(pdev); + } + + if (AMIGAHW_PRESENT(AMI_PARALLEL)) { + pdev = platform_device_register_simple("amiga-parallel", -1, + NULL, 0); + if (IS_ERR(pdev)) + return PTR_ERR(pdev); + } + + + /* real time clocks */ + if (AMIGAHW_PRESENT(A2000_CLK)) { + pdev = platform_device_register_simple("rtc-msm6242", -1, + &amiga_rtc_resource, 1); + if (IS_ERR(pdev)) + return PTR_ERR(pdev); + } + + if (AMIGAHW_PRESENT(A3000_CLK)) { + pdev = platform_device_register_simple("rtc-rp5c01", -1, + &amiga_rtc_resource, 1); + if (IS_ERR(pdev)) + return PTR_ERR(pdev); + } + + return 0; +} + +arch_initcall(amiga_init_devices); diff --git a/arch/m68k/apollo/Makefile b/arch/m68k/apollo/Makefile new file mode 100644 index 000000000..676c74b26 --- /dev/null +++ b/arch/m68k/apollo/Makefile @@ -0,0 +1,6 @@ +# SPDX-License-Identifier: GPL-2.0-only +# +# Makefile for Linux arch/m68k/apollo source directory +# + +obj-y := config.o dn_ints.o diff --git a/arch/m68k/apollo/config.c b/arch/m68k/apollo/config.c new file mode 100644 index 000000000..762da5d7a --- /dev/null +++ b/arch/m68k/apollo/config.c @@ -0,0 +1,270 @@ +// SPDX-License-Identifier: GPL-2.0 +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include + +u_long sio01_physaddr; +u_long sio23_physaddr; +u_long rtc_physaddr; +u_long pica_physaddr; +u_long picb_physaddr; +u_long cpuctrl_physaddr; +u_long timer_physaddr; +u_long apollo_model; + +extern void dn_sched_init(irq_handler_t handler); +extern void dn_init_IRQ(void); +extern int dn_dummy_hwclk(int, struct rtc_time *); +extern void dn_dummy_reset(void); +#ifdef CONFIG_HEARTBEAT +static void dn_heartbeat(int on); +#endif +static irqreturn_t dn_timer_int(int irq,void *); +static void dn_get_model(char *model); +static const char *apollo_models[] = { + [APOLLO_DN3000-APOLLO_DN3000] = "DN3000 (Otter)", + [APOLLO_DN3010-APOLLO_DN3000] = "DN3010 (Otter)", + [APOLLO_DN3500-APOLLO_DN3000] = "DN3500 (Cougar II)", + [APOLLO_DN4000-APOLLO_DN3000] = "DN4000 (Mink)", + [APOLLO_DN4500-APOLLO_DN3000] = "DN4500 (Roadrunner)" +}; + +int __init apollo_parse_bootinfo(const struct bi_record *record) +{ + int unknown = 0; + const void *data = record->data; + + switch (be16_to_cpu(record->tag)) { + case BI_APOLLO_MODEL: + apollo_model = be32_to_cpup(data); + break; + + default: + unknown=1; + } + + return unknown; +} + +static void __init dn_setup_model(void) +{ + pr_info("Apollo hardware found: [%s]\n", + apollo_models[apollo_model - APOLLO_DN3000]); + + switch(apollo_model) { + case APOLLO_UNKNOWN: + panic("Unknown apollo model"); + break; + case APOLLO_DN3000: + case APOLLO_DN3010: + sio01_physaddr=SAU8_SIO01_PHYSADDR; + rtc_physaddr=SAU8_RTC_PHYSADDR; + pica_physaddr=SAU8_PICA; + picb_physaddr=SAU8_PICB; + cpuctrl_physaddr=SAU8_CPUCTRL; + timer_physaddr=SAU8_TIMER; + break; + case APOLLO_DN4000: + sio01_physaddr=SAU7_SIO01_PHYSADDR; + sio23_physaddr=SAU7_SIO23_PHYSADDR; + rtc_physaddr=SAU7_RTC_PHYSADDR; + pica_physaddr=SAU7_PICA; + picb_physaddr=SAU7_PICB; + cpuctrl_physaddr=SAU7_CPUCTRL; + timer_physaddr=SAU7_TIMER; + break; + case APOLLO_DN4500: + panic("Apollo model not yet supported"); + break; + case APOLLO_DN3500: + sio01_physaddr=SAU7_SIO01_PHYSADDR; + sio23_physaddr=SAU7_SIO23_PHYSADDR; + rtc_physaddr=SAU7_RTC_PHYSADDR; + pica_physaddr=SAU7_PICA; + picb_physaddr=SAU7_PICB; + cpuctrl_physaddr=SAU7_CPUCTRL; + timer_physaddr=SAU7_TIMER; + break; + default: + panic("Undefined apollo model"); + break; + } + + +} + +int dn_serial_console_wait_key(struct console *co) { + + while(!(sio01.srb_csrb & 1)) + barrier(); + return sio01.rhrb_thrb; +} + +void dn_serial_console_write (struct console *co, const char *str,unsigned int count) +{ + while(count--) { + if (*str == '\n') { + sio01.rhrb_thrb = (unsigned char)'\r'; + while (!(sio01.srb_csrb & 0x4)) + ; + } + sio01.rhrb_thrb = (unsigned char)*str++; + while (!(sio01.srb_csrb & 0x4)) + ; + } +} + +void dn_serial_print (const char *str) +{ + while (*str) { + if (*str == '\n') { + sio01.rhrb_thrb = (unsigned char)'\r'; + while (!(sio01.srb_csrb & 0x4)) + ; + } + sio01.rhrb_thrb = (unsigned char)*str++; + while (!(sio01.srb_csrb & 0x4)) + ; + } +} + +void __init config_apollo(void) +{ + int i; + + dn_setup_model(); + + mach_sched_init=dn_sched_init; /* */ + mach_init_IRQ=dn_init_IRQ; + mach_max_dma_address = 0xffffffff; + mach_hwclk = dn_dummy_hwclk; /* */ + mach_reset = dn_dummy_reset; /* */ +#ifdef CONFIG_HEARTBEAT + mach_heartbeat = dn_heartbeat; +#endif + mach_get_model = dn_get_model; + + cpuctrl=0xaa00; + + /* clear DMA translation table */ + for(i=0;i<0x400;i++) + addr_xlat_map[i]=0; + +} + +irqreturn_t dn_timer_int(int irq, void *dev_id) +{ + irq_handler_t timer_handler = dev_id; + + volatile unsigned char x; + + timer_handler(irq, dev_id); + + x = *(volatile unsigned char *)(apollo_timer + 3); + x = *(volatile unsigned char *)(apollo_timer + 5); + + return IRQ_HANDLED; +} + +void dn_sched_init(irq_handler_t timer_routine) +{ + /* program timer 1 */ + *(volatile unsigned char *)(apollo_timer + 3) = 0x01; + *(volatile unsigned char *)(apollo_timer + 1) = 0x40; + *(volatile unsigned char *)(apollo_timer + 5) = 0x09; + *(volatile unsigned char *)(apollo_timer + 7) = 0xc4; + + /* enable IRQ of PIC B */ + *(volatile unsigned char *)(pica+1)&=(~8); + +#if 0 + pr_info("*(0x10803) %02x\n", + *(volatile unsigned char *)(apollo_timer + 0x3)); + pr_info("*(0x10803) %02x\n", + *(volatile unsigned char *)(apollo_timer + 0x3)); +#endif + + if (request_irq(IRQ_APOLLO, dn_timer_int, 0, "time", timer_routine)) + pr_err("Couldn't register timer interrupt\n"); +} + +int dn_dummy_hwclk(int op, struct rtc_time *t) { + + + if(!op) { /* read */ + t->tm_sec=rtc->second; + t->tm_min=rtc->minute; + t->tm_hour=rtc->hours; + t->tm_mday=rtc->day_of_month; + t->tm_wday=rtc->day_of_week; + t->tm_mon = rtc->month - 1; + t->tm_year=rtc->year; + if (t->tm_year < 70) + t->tm_year += 100; + } else { + rtc->second=t->tm_sec; + rtc->minute=t->tm_min; + rtc->hours=t->tm_hour; + rtc->day_of_month=t->tm_mday; + if(t->tm_wday!=-1) + rtc->day_of_week=t->tm_wday; + rtc->month = t->tm_mon + 1; + rtc->year = t->tm_year % 100; + } + + return 0; + +} + +void dn_dummy_reset(void) { + + dn_serial_print("The end !\n"); + + for(;;); + +} + +void dn_dummy_waitbut(void) { + + dn_serial_print("waitbut\n"); + +} + +static void dn_get_model(char *model) +{ + strcpy(model, "Apollo "); + if (apollo_model >= APOLLO_DN3000 && apollo_model <= APOLLO_DN4500) + strcat(model, apollo_models[apollo_model - APOLLO_DN3000]); +} + +#ifdef CONFIG_HEARTBEAT +static int dn_cpuctrl=0xff00; + +static void dn_heartbeat(int on) { + + if(on) { + dn_cpuctrl&=~0x100; + cpuctrl=dn_cpuctrl; + } + else { + dn_cpuctrl&=~0x100; + dn_cpuctrl|=0x100; + cpuctrl=dn_cpuctrl; + } +} +#endif + diff --git a/arch/m68k/apollo/dn_ints.c b/arch/m68k/apollo/dn_ints.c new file mode 100644 index 000000000..02cff7efc --- /dev/null +++ b/arch/m68k/apollo/dn_ints.c @@ -0,0 +1,48 @@ +// SPDX-License-Identifier: GPL-2.0 +#include +#include + +#include +#include + +unsigned int apollo_irq_startup(struct irq_data *data) +{ + unsigned int irq = data->irq; + + if (irq < 8) + *(volatile unsigned char *)(pica+1) &= ~(1 << irq); + else + *(volatile unsigned char *)(picb+1) &= ~(1 << (irq - 8)); + return 0; +} + +void apollo_irq_shutdown(struct irq_data *data) +{ + unsigned int irq = data->irq; + + if (irq < 8) + *(volatile unsigned char *)(pica+1) |= (1 << irq); + else + *(volatile unsigned char *)(picb+1) |= (1 << (irq - 8)); +} + +void apollo_irq_eoi(struct irq_data *data) +{ + *(volatile unsigned char *)(pica) = 0x20; + *(volatile unsigned char *)(picb) = 0x20; +} + +static struct irq_chip apollo_irq_chip = { + .name = "apollo", + .irq_startup = apollo_irq_startup, + .irq_shutdown = apollo_irq_shutdown, + .irq_eoi = apollo_irq_eoi, +}; + + +void __init dn_init_IRQ(void) +{ + m68k_setup_user_interrupt(VEC_USER + 96, 16); + m68k_setup_irq_controller(&apollo_irq_chip, handle_fasteoi_irq, + IRQ_APOLLO, 16); +} diff --git a/arch/m68k/atari/Makefile b/arch/m68k/atari/Makefile new file mode 100644 index 000000000..2e3607f97 --- /dev/null +++ b/arch/m68k/atari/Makefile @@ -0,0 +1,11 @@ +# SPDX-License-Identifier: GPL-2.0-only +# +# Makefile for Linux arch/m68k/atari source directory +# + +obj-y := config.o time.o debug.o ataints.o stdma.o \ + atasound.o stram.o + +obj-$(CONFIG_ATARI_KBD_CORE) += atakeyb.o + +obj-$(CONFIG_NVRAM:m=y) += nvram.o diff --git a/arch/m68k/atari/ataints.c b/arch/m68k/atari/ataints.c new file mode 100644 index 000000000..56f02ea2c --- /dev/null +++ b/arch/m68k/atari/ataints.c @@ -0,0 +1,391 @@ +/* + * arch/m68k/atari/ataints.c -- Atari Linux interrupt handling code + * + * 5/2/94 Roman Hodek: + * Added support for TT interrupts; setup for TT SCU (may someone has + * twiddled there and we won't get the right interrupts :-() + * + * Major change: The device-independent code in m68k/ints.c didn't know + * about non-autovec ints yet. It hardcoded the number of possible ints to + * 7 (IRQ1...IRQ7). But the Atari has lots of non-autovec ints! I made the + * number of possible ints a constant defined in interrupt.h, which is + * 47 for the Atari. So we can call request_irq() for all Atari interrupts + * just the normal way. Additionally, all vectors >= 48 are initialized to + * call trap() instead of inthandler(). This must be changed here, too. + * + * 1995-07-16 Lars Brinkhoff : + * Corrected a bug in atari_add_isr() which rejected all SCC + * interrupt sources if there were no TT MFP! + * + * 12/13/95: New interface functions atari_level_triggered_int() and + * atari_register_vme_int() as support for level triggered VME interrupts. + * + * 02/12/96: (Roman) + * Total rewrite of Atari interrupt handling, for new scheme see comments + * below. + * + * 1996-09-03 lars brinkhoff : + * Added new function atari_unregister_vme_int(), and + * modified atari_register_vme_int() as well as IS_VALID_INTNO() + * to work with it. + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file COPYING in the main directory of this archive + * for more details. + * + */ + +#include +#include +#include +#include +#include +#include +#include + +#include + +#include +#include +#include +#include +#include +#include + + +/* + * Atari interrupt handling scheme: + * -------------------------------- + * + * All interrupt source have an internal number (defined in + * ): Autovector interrupts are 1..7, then follow ST-MFP, + * TT-MFP, SCC, and finally VME interrupts. Vector numbers for the latter can + * be allocated by atari_register_vme_int(). + */ + +/* + * Bitmap for free interrupt vector numbers + * (new vectors starting from 0x70 can be allocated by + * atari_register_vme_int()) + */ +static int free_vme_vec_bitmap; + +/* GK: + * HBL IRQ handler for Falcon. Nobody needs it :-) + * ++andreas: raise ipl to disable further HBLANK interrupts. + */ +asmlinkage void falcon_hblhandler(void); +asm(".text\n" +__ALIGN_STR "\n\t" +"falcon_hblhandler:\n\t" + "orw #0x200,%sp@\n\t" /* set saved ipl to 2 */ + "rte"); + +extern void atari_microwire_cmd(int cmd); + +static unsigned int atari_irq_startup(struct irq_data *data) +{ + unsigned int irq = data->irq; + + m68k_irq_startup(data); + atari_turnon_irq(irq); + atari_enable_irq(irq); + return 0; +} + +static void atari_irq_shutdown(struct irq_data *data) +{ + unsigned int irq = data->irq; + + atari_disable_irq(irq); + atari_turnoff_irq(irq); + m68k_irq_shutdown(data); + + if (irq == IRQ_AUTO_4) + vectors[VEC_INT4] = falcon_hblhandler; +} + +static void atari_irq_enable(struct irq_data *data) +{ + atari_enable_irq(data->irq); +} + +static void atari_irq_disable(struct irq_data *data) +{ + atari_disable_irq(data->irq); +} + +static struct irq_chip atari_irq_chip = { + .name = "atari", + .irq_startup = atari_irq_startup, + .irq_shutdown = atari_irq_shutdown, + .irq_enable = atari_irq_enable, + .irq_disable = atari_irq_disable, +}; + +/* + * ST-MFP timer D chained interrupts - each driver gets its own timer + * interrupt instance. + */ + +struct mfptimerbase { + volatile struct MFP *mfp; + unsigned char mfp_mask, mfp_data; + unsigned short int_mask; + int handler_irq, mfptimer_irq, server_irq; + char *name; +} stmfp_base = { + .mfp = &st_mfp, + .int_mask = 0x0, + .handler_irq = IRQ_MFP_TIMD, + .mfptimer_irq = IRQ_MFP_TIMER1, + .name = "MFP Timer D" +}; + +static irqreturn_t mfp_timer_d_handler(int irq, void *dev_id) +{ + struct mfptimerbase *base = dev_id; + int mach_irq; + unsigned char ints; + + mach_irq = base->mfptimer_irq; + ints = base->int_mask; + for (; ints; mach_irq++, ints >>= 1) { + if (ints & 1) + generic_handle_irq(mach_irq); + } + return IRQ_HANDLED; +} + + +static void atari_mfptimer_enable(struct irq_data *data) +{ + int mfp_num = data->irq - IRQ_MFP_TIMER1; + stmfp_base.int_mask |= 1 << mfp_num; + atari_enable_irq(IRQ_MFP_TIMD); +} + +static void atari_mfptimer_disable(struct irq_data *data) +{ + int mfp_num = data->irq - IRQ_MFP_TIMER1; + stmfp_base.int_mask &= ~(1 << mfp_num); + if (!stmfp_base.int_mask) + atari_disable_irq(IRQ_MFP_TIMD); +} + +static struct irq_chip atari_mfptimer_chip = { + .name = "timer_d", + .irq_enable = atari_mfptimer_enable, + .irq_disable = atari_mfptimer_disable, +}; + + +/* + * EtherNAT CPLD interrupt handling + * CPLD interrupt register is at phys. 0x80000023 + * Need this mapped in at interrupt startup time + * Possibly need this mapped on demand anyway - + * EtherNAT USB driver needs to disable IRQ before + * startup! + */ + +static unsigned char *enat_cpld; + +static unsigned int atari_ethernat_startup(struct irq_data *data) +{ + int enat_num = 140 - data->irq + 1; + + m68k_irq_startup(data); + /* + * map CPLD interrupt register + */ + if (!enat_cpld) + enat_cpld = (unsigned char *)ioremap((ATARI_ETHERNAT_PHYS_ADDR+0x23), 0x2); + /* + * do _not_ enable the USB chip interrupt here - causes interrupt storm + * and triggers dead interrupt watchdog + * Need to reset the USB chip to a sane state in early startup before + * removing this hack + */ + if (enat_num == 1) + *enat_cpld |= 1 << enat_num; + + return 0; +} + +static void atari_ethernat_enable(struct irq_data *data) +{ + int enat_num = 140 - data->irq + 1; + /* + * map CPLD interrupt register + */ + if (!enat_cpld) + enat_cpld = (unsigned char *)ioremap((ATARI_ETHERNAT_PHYS_ADDR+0x23), 0x2); + *enat_cpld |= 1 << enat_num; +} + +static void atari_ethernat_disable(struct irq_data *data) +{ + int enat_num = 140 - data->irq + 1; + /* + * map CPLD interrupt register + */ + if (!enat_cpld) + enat_cpld = (unsigned char *)ioremap((ATARI_ETHERNAT_PHYS_ADDR+0x23), 0x2); + *enat_cpld &= ~(1 << enat_num); +} + +static void atari_ethernat_shutdown(struct irq_data *data) +{ + int enat_num = 140 - data->irq + 1; + if (enat_cpld) { + *enat_cpld &= ~(1 << enat_num); + iounmap(enat_cpld); + enat_cpld = NULL; + } +} + +static struct irq_chip atari_ethernat_chip = { + .name = "ethernat", + .irq_startup = atari_ethernat_startup, + .irq_shutdown = atari_ethernat_shutdown, + .irq_enable = atari_ethernat_enable, + .irq_disable = atari_ethernat_disable, +}; + +/* + * void atari_init_IRQ (void) + * + * Parameters: None + * + * Returns: Nothing + * + * This function should be called during kernel startup to initialize + * the atari IRQ handling routines. + */ + +void __init atari_init_IRQ(void) +{ + m68k_setup_user_interrupt(VEC_USER, NUM_ATARI_SOURCES - IRQ_USER); + m68k_setup_irq_controller(&atari_irq_chip, handle_simple_irq, 1, + NUM_ATARI_SOURCES - 1); + + /* Initialize the MFP(s) */ + +#ifdef ATARI_USE_SOFTWARE_EOI + st_mfp.vec_adr = 0x48; /* Software EOI-Mode */ +#else + st_mfp.vec_adr = 0x40; /* Automatic EOI-Mode */ +#endif + st_mfp.int_en_a = 0x00; /* turn off MFP-Ints */ + st_mfp.int_en_b = 0x00; + st_mfp.int_mk_a = 0xff; /* no Masking */ + st_mfp.int_mk_b = 0xff; + + if (ATARIHW_PRESENT(TT_MFP)) { +#ifdef ATARI_USE_SOFTWARE_EOI + tt_mfp.vec_adr = 0x58; /* Software EOI-Mode */ +#else + tt_mfp.vec_adr = 0x50; /* Automatic EOI-Mode */ +#endif + tt_mfp.int_en_a = 0x00; /* turn off MFP-Ints */ + tt_mfp.int_en_b = 0x00; + tt_mfp.int_mk_a = 0xff; /* no Masking */ + tt_mfp.int_mk_b = 0xff; + } + + if (ATARIHW_PRESENT(SCC) && !atari_SCC_reset_done) { + atari_scc.cha_a_ctrl = 9; + MFPDELAY(); + atari_scc.cha_a_ctrl = (char) 0xc0; /* hardware reset */ + } + + if (ATARIHW_PRESENT(SCU)) { + /* init the SCU if present */ + tt_scu.sys_mask = 0x10; /* enable VBL (for the cursor) and + * disable HSYNC interrupts (who + * needs them?) MFP and SCC are + * enabled in VME mask + */ + tt_scu.vme_mask = 0x60; /* enable MFP and SCC ints */ + } else { + /* If no SCU and no Hades, the HSYNC interrupt needs to be + * disabled this way. (Else _inthandler in kernel/sys_call.S + * gets overruns) + */ + + vectors[VEC_INT2] = falcon_hblhandler; + vectors[VEC_INT4] = falcon_hblhandler; + } + + if (ATARIHW_PRESENT(PCM_8BIT) && ATARIHW_PRESENT(MICROWIRE)) { + /* Initialize the LM1992 Sound Controller to enable + the PSG sound. This is misplaced here, it should + be in an atasound_init(), that doesn't exist yet. */ + atari_microwire_cmd(MW_LM1992_PSG_HIGH); + } + + stdma_init(); + + /* Initialize the PSG: all sounds off, both ports output */ + sound_ym.rd_data_reg_sel = 7; + sound_ym.wd_data = 0xff; + + m68k_setup_irq_controller(&atari_mfptimer_chip, handle_simple_irq, + IRQ_MFP_TIMER1, 8); + + irq_set_status_flags(IRQ_MFP_TIMER1, IRQ_IS_POLLED); + irq_set_status_flags(IRQ_MFP_TIMER2, IRQ_IS_POLLED); + + /* prepare timer D data for use as poll interrupt */ + /* set Timer D data Register - needs to be > 0 */ + st_mfp.tim_dt_d = 254; /* < 100 Hz */ + /* start timer D, div = 1:100 */ + st_mfp.tim_ct_cd = (st_mfp.tim_ct_cd & 0xf0) | 0x6; + + /* request timer D dispatch handler */ + if (request_irq(IRQ_MFP_TIMD, mfp_timer_d_handler, IRQF_SHARED, + stmfp_base.name, &stmfp_base)) + pr_err("Couldn't register %s interrupt\n", stmfp_base.name); + + /* + * EtherNAT ethernet / USB interrupt handlers + */ + + m68k_setup_irq_controller(&atari_ethernat_chip, handle_simple_irq, + 139, 2); +} + + +/* + * atari_register_vme_int() returns the number of a free interrupt vector for + * hardware with a programmable int vector (probably a VME board). + */ + +unsigned int atari_register_vme_int(void) +{ + int i; + + for (i = 0; i < 32; i++) + if ((free_vme_vec_bitmap & (1 << i)) == 0) + break; + + if (i == 16) + return 0; + + free_vme_vec_bitmap |= 1 << i; + return VME_SOURCE_BASE + i; +} +EXPORT_SYMBOL(atari_register_vme_int); + + +void atari_unregister_vme_int(unsigned int irq) +{ + if (irq >= VME_SOURCE_BASE && irq < VME_SOURCE_BASE + VME_MAX_SOURCES) { + irq -= VME_SOURCE_BASE; + free_vme_vec_bitmap &= ~(1 << irq); + } +} +EXPORT_SYMBOL(atari_unregister_vme_int); + + diff --git a/arch/m68k/atari/atakeyb.c b/arch/m68k/atari/atakeyb.c new file mode 100644 index 000000000..5e0e682f9 --- /dev/null +++ b/arch/m68k/atari/atakeyb.c @@ -0,0 +1,570 @@ +/* + * Atari Keyboard driver for 680x0 Linux + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file COPYING in the main directory of this archive + * for more details. + */ + +/* + * Atari support by Robert de Vries + * enhanced by Bjoern Brauel and Roman Hodek + * + * 2.6 and input cleanup (removed autorepeat stuff) for 2.6.21 + * 06/07 Michael Schmitz + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include + + +/* Hook for MIDI serial driver */ +void (*atari_MIDI_interrupt_hook) (void); +/* Hook for keyboard inputdev driver */ +void (*atari_input_keyboard_interrupt_hook) (unsigned char, char); +/* Hook for mouse inputdev driver */ +void (*atari_input_mouse_interrupt_hook) (char *); +EXPORT_SYMBOL(atari_input_keyboard_interrupt_hook); +EXPORT_SYMBOL(atari_input_mouse_interrupt_hook); + +/* variables for IKBD self test: */ + +/* state: 0: off; >0: in progress; >1: 0xf1 received */ +static volatile int ikbd_self_test; +/* timestamp when last received a char */ +static volatile unsigned long self_test_last_rcv; +/* bitmap of keys reported as broken */ +static unsigned long broken_keys[128/(sizeof(unsigned long)*8)] = { 0, }; + +#define BREAK_MASK (0x80) + +/* + * ++roman: The following changes were applied manually: + * + * - The Alt (= Meta) key works in combination with Shift and + * Control, e.g. Alt+Shift+a sends Meta-A (0xc1), Alt+Control+A sends + * Meta-Ctrl-A (0x81) ... + * + * - The parentheses on the keypad send '(' and ')' with all + * modifiers (as would do e.g. keypad '+'), but they cannot be used as + * application keys (i.e. sending Esc O c). + * + * - HELP and UNDO are mapped to be F21 and F24, resp, that send the + * codes "\E[M" and "\E[P". (This is better than the old mapping to + * F11 and F12, because these codes are on Shift+F1/2 anyway.) This + * way, applications that allow their own keyboard mappings + * (e.g. tcsh, X Windows) can be configured to use them in the way + * the label suggests (providing help or undoing). + * + * - Console switching is done with Alt+Fx (consoles 1..10) and + * Shift+Alt+Fx (consoles 11..20). + * + * - The misc. special function implemented in the kernel are mapped + * to the following key combinations: + * + * ClrHome -> Home/Find + * Shift + ClrHome -> End/Select + * Shift + Up -> Page Up + * Shift + Down -> Page Down + * Alt + Help -> show system status + * Shift + Help -> show memory info + * Ctrl + Help -> show registers + * Ctrl + Alt + Del -> Reboot + * Alt + Undo -> switch to last console + * Shift + Undo -> send interrupt + * Alt + Insert -> stop/start output (same as ^S/^Q) + * Alt + Up -> Scroll back console (if implemented) + * Alt + Down -> Scroll forward console (if implemented) + * Alt + CapsLock -> NumLock + * + * ++Andreas: + * + * - Help mapped to K_HELP + * - Undo mapped to K_UNDO (= K_F246) + * - Keypad Left/Right Parenthesis mapped to new K_PPAREN[LR] + */ + +typedef enum kb_state_t { + KEYBOARD, AMOUSE, RMOUSE, JOYSTICK, CLOCK, RESYNC +} KB_STATE_T; + +#define IS_SYNC_CODE(sc) ((sc) >= 0x04 && (sc) <= 0xfb) + +typedef struct keyboard_state { + unsigned char buf[6]; + int len; + KB_STATE_T state; +} KEYBOARD_STATE; + +KEYBOARD_STATE kb_state; + +/* ++roman: If a keyboard overrun happened, we can't tell in general how much + * bytes have been lost and in which state of the packet structure we are now. + * This usually causes keyboards bytes to be interpreted as mouse movements + * and vice versa, which is very annoying. It seems better to throw away some + * bytes (that are usually mouse bytes) than to misinterpret them. Therefore I + * introduced the RESYNC state for IKBD data. In this state, the bytes up to + * one that really looks like a key event (0x04..0xf2) or the start of a mouse + * packet (0xf8..0xfb) are thrown away, but at most 2 bytes. This at least + * speeds up the resynchronization of the event structure, even if maybe a + * mouse movement is lost. However, nothing is perfect. For bytes 0x01..0x03, + * it's really hard to decide whether they're mouse or keyboard bytes. Since + * overruns usually occur when moving the Atari mouse rapidly, they're seen as + * mouse bytes here. If this is wrong, only a make code of the keyboard gets + * lost, which isn't too bad. Losing a break code would be disastrous, + * because then the keyboard repeat strikes... + */ + +static irqreturn_t atari_keyboard_interrupt(int irq, void *dummy) +{ + u_char acia_stat; + int scancode; + int break_flag; + +repeat: + if (acia.mid_ctrl & ACIA_IRQ) + if (atari_MIDI_interrupt_hook) + atari_MIDI_interrupt_hook(); + acia_stat = acia.key_ctrl; + /* check out if the interrupt came from this ACIA */ + if (!((acia_stat | acia.mid_ctrl) & ACIA_IRQ)) + return IRQ_HANDLED; + + if (acia_stat & ACIA_OVRN) { + /* a very fast typist or a slow system, give a warning */ + /* ...happens often if interrupts were disabled for too long */ + pr_debug("Keyboard overrun\n"); + scancode = acia.key_data; + if (ikbd_self_test) + /* During self test, don't do resyncing, just process the code */ + goto interpret_scancode; + else if (IS_SYNC_CODE(scancode)) { + /* This code seem already to be the start of a new packet or a + * single scancode */ + kb_state.state = KEYBOARD; + goto interpret_scancode; + } else { + /* Go to RESYNC state and skip this byte */ + kb_state.state = RESYNC; + kb_state.len = 1; /* skip max. 1 another byte */ + goto repeat; + } + } + + if (acia_stat & ACIA_RDRF) { + /* received a character */ + scancode = acia.key_data; /* get it or reset the ACIA, I'll get it! */ + interpret_scancode: + switch (kb_state.state) { + case KEYBOARD: + switch (scancode) { + case 0xF7: + kb_state.state = AMOUSE; + kb_state.len = 0; + break; + + case 0xF8: + case 0xF9: + case 0xFA: + case 0xFB: + kb_state.state = RMOUSE; + kb_state.len = 1; + kb_state.buf[0] = scancode; + break; + + case 0xFC: + kb_state.state = CLOCK; + kb_state.len = 0; + break; + + case 0xFE: + case 0xFF: + kb_state.state = JOYSTICK; + kb_state.len = 1; + kb_state.buf[0] = scancode; + break; + + case 0xF1: + /* during self-test, note that 0xf1 received */ + if (ikbd_self_test) { + ++ikbd_self_test; + self_test_last_rcv = jiffies; + break; + } + fallthrough; + + default: + break_flag = scancode & BREAK_MASK; + scancode &= ~BREAK_MASK; + if (ikbd_self_test) { + /* Scancodes sent during the self-test stand for broken + * keys (keys being down). The code *should* be a break + * code, but nevertheless some AT keyboard interfaces send + * make codes instead. Therefore, simply ignore + * break_flag... + */ + int keyval, keytyp; + + set_bit(scancode, broken_keys); + self_test_last_rcv = jiffies; + /* new Linux scancodes; approx. */ + keyval = scancode; + keytyp = KTYP(keyval) - 0xf0; + keyval = KVAL(keyval); + + pr_warn("Key with scancode %d ", scancode); + if (keytyp == KT_LATIN || keytyp == KT_LETTER) { + if (keyval < ' ') + pr_cont("('^%c') ", keyval + '@'); + else + pr_cont("('%c') ", keyval); + } + pr_cont("is broken -- will be ignored.\n"); + break; + } else if (test_bit(scancode, broken_keys)) + break; + + if (atari_input_keyboard_interrupt_hook) + atari_input_keyboard_interrupt_hook((unsigned char)scancode, !break_flag); + break; + } + break; + + case AMOUSE: + kb_state.buf[kb_state.len++] = scancode; + if (kb_state.len == 5) { + kb_state.state = KEYBOARD; + /* not yet used */ + /* wake up someone waiting for this */ + } + break; + + case RMOUSE: + kb_state.buf[kb_state.len++] = scancode; + if (kb_state.len == 3) { + kb_state.state = KEYBOARD; + if (atari_input_mouse_interrupt_hook) + atari_input_mouse_interrupt_hook(kb_state.buf); + } + break; + + case JOYSTICK: + kb_state.buf[1] = scancode; + kb_state.state = KEYBOARD; +#ifdef FIXED_ATARI_JOYSTICK + atari_joystick_interrupt(kb_state.buf); +#endif + break; + + case CLOCK: + kb_state.buf[kb_state.len++] = scancode; + if (kb_state.len == 6) { + kb_state.state = KEYBOARD; + /* wake up someone waiting for this. + But will this ever be used, as Linux keeps its own time. + Perhaps for synchronization purposes? */ + /* wake_up_interruptible(&clock_wait); */ + } + break; + + case RESYNC: + if (kb_state.len <= 0 || IS_SYNC_CODE(scancode)) { + kb_state.state = KEYBOARD; + goto interpret_scancode; + } + kb_state.len--; + break; + } + } + +#if 0 + if (acia_stat & ACIA_CTS) + /* cannot happen */; +#endif + + if (acia_stat & (ACIA_FE | ACIA_PE)) { + pr_err("Error in keyboard communication\n"); + } + + /* handle_scancode() can take a lot of time, so check again if + * some character arrived + */ + goto repeat; +} + +/* + * I write to the keyboard without using interrupts, I poll instead. + * This takes for the maximum length string allowed (7) at 7812.5 baud + * 8 data 1 start 1 stop bit: 9.0 ms + * If this takes too long for normal operation, interrupt driven writing + * is the solution. (I made a feeble attempt in that direction but I + * kept it simple for now.) + */ +void ikbd_write(const char *str, int len) +{ + u_char acia_stat; + + if ((len < 1) || (len > 7)) + panic("ikbd: maximum string length exceeded"); + while (len) { + acia_stat = acia.key_ctrl; + if (acia_stat & ACIA_TDRE) { + acia.key_data = *str++; + len--; + } + } +} + +/* Reset (without touching the clock) */ +void ikbd_reset(void) +{ + static const char cmd[2] = { 0x80, 0x01 }; + + ikbd_write(cmd, 2); + + /* + * if all's well code 0xF1 is returned, else the break codes of + * all keys making contact + */ +} + +/* Set mouse button action */ +void ikbd_mouse_button_action(int mode) +{ + char cmd[2] = { 0x07, mode }; + + ikbd_write(cmd, 2); +} + +/* Set relative mouse position reporting */ +void ikbd_mouse_rel_pos(void) +{ + static const char cmd[1] = { 0x08 }; + + ikbd_write(cmd, 1); +} +EXPORT_SYMBOL(ikbd_mouse_rel_pos); + +/* Set absolute mouse position reporting */ +void ikbd_mouse_abs_pos(int xmax, int ymax) +{ + char cmd[5] = { 0x09, xmax>>8, xmax&0xFF, ymax>>8, ymax&0xFF }; + + ikbd_write(cmd, 5); +} + +/* Set mouse keycode mode */ +void ikbd_mouse_kbd_mode(int dx, int dy) +{ + char cmd[3] = { 0x0A, dx, dy }; + + ikbd_write(cmd, 3); +} + +/* Set mouse threshold */ +void ikbd_mouse_thresh(int x, int y) +{ + char cmd[3] = { 0x0B, x, y }; + + ikbd_write(cmd, 3); +} +EXPORT_SYMBOL(ikbd_mouse_thresh); + +/* Set mouse scale */ +void ikbd_mouse_scale(int x, int y) +{ + char cmd[3] = { 0x0C, x, y }; + + ikbd_write(cmd, 3); +} + +/* Interrogate mouse position */ +void ikbd_mouse_pos_get(int *x, int *y) +{ + static const char cmd[1] = { 0x0D }; + + ikbd_write(cmd, 1); + + /* wait for returning bytes */ +} + +/* Load mouse position */ +void ikbd_mouse_pos_set(int x, int y) +{ + char cmd[6] = { 0x0E, 0x00, x>>8, x&0xFF, y>>8, y&0xFF }; + + ikbd_write(cmd, 6); +} + +/* Set Y=0 at bottom */ +void ikbd_mouse_y0_bot(void) +{ + static const char cmd[1] = { 0x0F }; + + ikbd_write(cmd, 1); +} + +/* Set Y=0 at top */ +void ikbd_mouse_y0_top(void) +{ + static const char cmd[1] = { 0x10 }; + + ikbd_write(cmd, 1); +} +EXPORT_SYMBOL(ikbd_mouse_y0_top); + +/* Disable mouse */ +void ikbd_mouse_disable(void) +{ + static const char cmd[1] = { 0x12 }; + + ikbd_write(cmd, 1); +} +EXPORT_SYMBOL(ikbd_mouse_disable); + +/* Set joystick event reporting */ +void ikbd_joystick_event_on(void) +{ + static const char cmd[1] = { 0x14 }; + + ikbd_write(cmd, 1); +} + +/* Set joystick interrogation mode */ +void ikbd_joystick_event_off(void) +{ + static const char cmd[1] = { 0x15 }; + + ikbd_write(cmd, 1); +} + +/* Joystick interrogation */ +void ikbd_joystick_get_state(void) +{ + static const char cmd[1] = { 0x16 }; + + ikbd_write(cmd, 1); +} + +#if 0 +/* This disables all other ikbd activities !!!! */ +/* Set joystick monitoring */ +void ikbd_joystick_monitor(int rate) +{ + static const char cmd[2] = { 0x17, rate }; + + ikbd_write(cmd, 2); + + kb_state.state = JOYSTICK_MONITOR; +} +#endif + +/* some joystick routines not in yet (0x18-0x19) */ + +/* Disable joysticks */ +void ikbd_joystick_disable(void) +{ + static const char cmd[1] = { 0x1A }; + + ikbd_write(cmd, 1); +} + +/* + * The original code sometimes left the interrupt line of + * the ACIAs low forever. I hope, it is fixed now. + * + * Martin Rogge, 20 Aug 1995 + */ + +static int atari_keyb_done = 0; + +int atari_keyb_init(void) +{ + int error; + + if (atari_keyb_done) + return 0; + + kb_state.state = KEYBOARD; + kb_state.len = 0; + + error = request_irq(IRQ_MFP_ACIA, atari_keyboard_interrupt, 0, + "keyboard,mouse,MIDI", atari_keyboard_interrupt); + if (error) + return error; + + atari_turnoff_irq(IRQ_MFP_ACIA); + do { + /* reset IKBD ACIA */ + acia.key_ctrl = ACIA_RESET | + ((atari_switches & ATARI_SWITCH_IKBD) ? + ACIA_RHTID : 0); + (void)acia.key_ctrl; + (void)acia.key_data; + + /* reset MIDI ACIA */ + acia.mid_ctrl = ACIA_RESET | + ((atari_switches & ATARI_SWITCH_MIDI) ? + ACIA_RHTID : 0); + (void)acia.mid_ctrl; + (void)acia.mid_data; + + /* divide 500kHz by 64 gives 7812.5 baud */ + /* 8 data no parity 1 start 1 stop bit */ + /* receive interrupt enabled */ + /* RTS low (except if switch selected), transmit interrupt disabled */ + acia.key_ctrl = (ACIA_DIV64|ACIA_D8N1S|ACIA_RIE) | + ((atari_switches & ATARI_SWITCH_IKBD) ? + ACIA_RHTID : ACIA_RLTID); + + acia.mid_ctrl = ACIA_DIV16 | ACIA_D8N1S | + ((atari_switches & ATARI_SWITCH_MIDI) ? + ACIA_RHTID : 0); + + /* make sure the interrupt line is up */ + } while ((st_mfp.par_dt_reg & 0x10) == 0); + + /* enable ACIA Interrupts */ + st_mfp.active_edge &= ~0x10; + atari_turnon_irq(IRQ_MFP_ACIA); + + ikbd_self_test = 1; + ikbd_reset(); + /* wait for a period of inactivity (here: 0.25s), then assume the IKBD's + * self-test is finished */ + self_test_last_rcv = jiffies; + while (time_before(jiffies, self_test_last_rcv + HZ/4)) + barrier(); + /* if not incremented: no 0xf1 received */ + if (ikbd_self_test == 1) + pr_err("Keyboard self test failed!\n"); + ikbd_self_test = 0; + + ikbd_mouse_disable(); + ikbd_joystick_disable(); + +#ifdef FIXED_ATARI_JOYSTICK + atari_joystick_init(); +#endif + + // flag init done + atari_keyb_done = 1; + return 0; +} +EXPORT_SYMBOL_GPL(atari_keyb_init); diff --git a/arch/m68k/atari/atasound.c b/arch/m68k/atari/atasound.c new file mode 100644 index 000000000..a8724d998 --- /dev/null +++ b/arch/m68k/atari/atasound.c @@ -0,0 +1,109 @@ +/* + * linux/arch/m68k/atari/atasound.c + * + * ++Geert: Moved almost all stuff to linux/drivers/sound/ + * + * The author of atari_nosound, atari_mksound and atari_microwire_cmd is + * unknown. (++roman: That's me... :-) + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file COPYING in the main directory of this archive + * for more details. + * + * 1998-05-31 ++andreas: atari_mksound rewritten to always use the envelope, + * no timer, atari_nosound removed. + * + */ + + +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include + + +/* + * stuff from the old atasound.c + */ + +void atari_microwire_cmd (int cmd) +{ + tt_microwire.mask = 0x7ff; + tt_microwire.data = MW_LM1992_ADDR | cmd; + + /* Busy wait for data being completely sent :-( */ + while( tt_microwire.mask != 0x7ff) + ; +} +EXPORT_SYMBOL(atari_microwire_cmd); + + +/* PSG base frequency */ +#define PSG_FREQ 125000 +/* PSG envelope base frequency times 10 */ +#define PSG_ENV_FREQ_10 78125 + +void atari_mksound (unsigned int hz, unsigned int ticks) +{ + /* Generates sound of some frequency for some number of clock + ticks. */ + unsigned long flags; + unsigned char tmp; + int period; + + local_irq_save(flags); + + + /* Disable generator A in mixer control. */ + sound_ym.rd_data_reg_sel = 7; + tmp = sound_ym.rd_data_reg_sel; + tmp |= 011; + sound_ym.wd_data = tmp; + + if (hz) { + /* Convert from frequency value to PSG period value (base + frequency 125 kHz). */ + + period = PSG_FREQ / hz; + + if (period > 0xfff) period = 0xfff; + + /* Set generator A frequency to hz. */ + sound_ym.rd_data_reg_sel = 0; + sound_ym.wd_data = period & 0xff; + sound_ym.rd_data_reg_sel = 1; + sound_ym.wd_data = (period >> 8) & 0xf; + if (ticks) { + /* Set length of envelope (max 8 sec). */ + int length = (ticks * PSG_ENV_FREQ_10) / HZ / 10; + + if (length > 0xffff) length = 0xffff; + sound_ym.rd_data_reg_sel = 11; + sound_ym.wd_data = length & 0xff; + sound_ym.rd_data_reg_sel = 12; + sound_ym.wd_data = length >> 8; + /* Envelope form: max -> min single. */ + sound_ym.rd_data_reg_sel = 13; + sound_ym.wd_data = 0; + /* Use envelope for generator A. */ + sound_ym.rd_data_reg_sel = 8; + sound_ym.wd_data = 0x10; + } else { + /* Set generator A level to maximum, no envelope. */ + sound_ym.rd_data_reg_sel = 8; + sound_ym.wd_data = 15; + } + /* Turn on generator A in mixer control. */ + sound_ym.rd_data_reg_sel = 7; + tmp &= ~1; + sound_ym.wd_data = tmp; + } + local_irq_restore(flags); +} diff --git a/arch/m68k/atari/config.c b/arch/m68k/atari/config.c new file mode 100644 index 000000000..7ec3161e8 --- /dev/null +++ b/arch/m68k/atari/config.c @@ -0,0 +1,945 @@ +/* + * linux/arch/m68k/atari/config.c + * + * Copyright (C) 1994 Bjoern Brauel + * + * 5/2/94 Roman Hodek: + * Added setting of time_adj to get a better clock. + * + * 5/14/94 Roman Hodek: + * gettod() for TT + * + * 5/15/94 Roman Hodek: + * hard_reset_now() for Atari (and others?) + * + * 94/12/30 Andreas Schwab: + * atari_sched_init fixed to get precise clock. + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file COPYING in the main directory of this archive + * for more details. + */ + +/* + * Miscellaneous atari stuff + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +u_long atari_mch_cookie; +EXPORT_SYMBOL(atari_mch_cookie); + +u_long atari_mch_type; +EXPORT_SYMBOL(atari_mch_type); + +struct atari_hw_present atari_hw_present; +EXPORT_SYMBOL(atari_hw_present); + +u_long atari_switches; +EXPORT_SYMBOL(atari_switches); + +int atari_dont_touch_floppy_select; +EXPORT_SYMBOL(atari_dont_touch_floppy_select); + +int atari_rtc_year_offset; + +/* local function prototypes */ +static void atari_reset(void); +static void atari_get_model(char *model); +static void atari_get_hardware_list(struct seq_file *m); + +/* atari specific irq functions */ +extern void atari_init_IRQ (void); +extern void atari_mksound(unsigned int count, unsigned int ticks); +#ifdef CONFIG_HEARTBEAT +static void atari_heartbeat(int on); +#endif + +/* atari specific timer functions (in time.c) */ +extern void atari_sched_init(irq_handler_t); +extern int atari_mste_hwclk (int, struct rtc_time *); +extern int atari_tt_hwclk (int, struct rtc_time *); + +/* ++roman: This is a more elaborate test for an SCC chip, since the plain + * Medusa board generates DTACK at the SCC's standard addresses, but a SCC + * board in the Medusa is possible. Also, the addresses where the ST_ESCC + * resides generate DTACK without the chip, too. + * The method is to write values into the interrupt vector register, that + * should be readable without trouble (from channel A!). + */ + +static int __init scc_test(volatile char *ctla) +{ + if (!hwreg_present(ctla)) + return 0; + MFPDELAY(); + + *ctla = 2; + MFPDELAY(); + *ctla = 0x40; + MFPDELAY(); + + *ctla = 2; + MFPDELAY(); + if (*ctla != 0x40) + return 0; + MFPDELAY(); + + *ctla = 2; + MFPDELAY(); + *ctla = 0x60; + MFPDELAY(); + + *ctla = 2; + MFPDELAY(); + if (*ctla != 0x60) + return 0; + + return 1; +} + + + /* + * Parse an Atari-specific record in the bootinfo + */ + +int __init atari_parse_bootinfo(const struct bi_record *record) +{ + int unknown = 0; + const void *data = record->data; + + switch (be16_to_cpu(record->tag)) { + case BI_ATARI_MCH_COOKIE: + atari_mch_cookie = be32_to_cpup(data); + break; + case BI_ATARI_MCH_TYPE: + atari_mch_type = be32_to_cpup(data); + break; + default: + unknown = 1; + break; + } + return unknown; +} + + +/* Parse the Atari-specific switches= option. */ +static int __init atari_switches_setup(char *str) +{ + char switches[COMMAND_LINE_SIZE]; + char *p; + int ovsc_shift; + char *args = switches; + + if (!MACH_IS_ATARI) + return 0; + + /* copy string to local array, strsep works destructively... */ + strcpy(switches, str); + atari_switches = 0; + + /* parse the options */ + while ((p = strsep(&args, ",")) != NULL) { + if (!*p) + continue; + ovsc_shift = 0; + if (strncmp(p, "ov_", 3) == 0) { + p += 3; + ovsc_shift = ATARI_SWITCH_OVSC_SHIFT; + } + + if (strcmp(p, "ikbd") == 0) { + /* RTS line of IKBD ACIA */ + atari_switches |= ATARI_SWITCH_IKBD << ovsc_shift; + } else if (strcmp(p, "midi") == 0) { + /* RTS line of MIDI ACIA */ + atari_switches |= ATARI_SWITCH_MIDI << ovsc_shift; + } else if (strcmp(p, "snd6") == 0) { + atari_switches |= ATARI_SWITCH_SND6 << ovsc_shift; + } else if (strcmp(p, "snd7") == 0) { + atari_switches |= ATARI_SWITCH_SND7 << ovsc_shift; + } + } + return 0; +} + +early_param("switches", atari_switches_setup); + + + /* + * Setup the Atari configuration info + */ + +void __init config_atari(void) +{ + unsigned short tos_version; + + memset(&atari_hw_present, 0, sizeof(atari_hw_present)); + + /* Change size of I/O space from 64KB to 4GB. */ + ioport_resource.end = 0xFFFFFFFF; + + mach_sched_init = atari_sched_init; + mach_init_IRQ = atari_init_IRQ; + mach_get_model = atari_get_model; + mach_get_hardware_list = atari_get_hardware_list; + mach_reset = atari_reset; + mach_max_dma_address = 0xffffff; +#if IS_ENABLED(CONFIG_INPUT_M68K_BEEP) + mach_beep = atari_mksound; +#endif +#ifdef CONFIG_HEARTBEAT + mach_heartbeat = atari_heartbeat; +#endif + + /* Set switches as requested by the user */ + if (atari_switches & ATARI_SWITCH_IKBD) + acia.key_ctrl = ACIA_DIV64 | ACIA_D8N1S | ACIA_RHTID; + if (atari_switches & ATARI_SWITCH_MIDI) + acia.mid_ctrl = ACIA_DIV16 | ACIA_D8N1S | ACIA_RHTID; + if (atari_switches & (ATARI_SWITCH_SND6|ATARI_SWITCH_SND7)) { + sound_ym.rd_data_reg_sel = 14; + sound_ym.wd_data = sound_ym.rd_data_reg_sel | + ((atari_switches&ATARI_SWITCH_SND6) ? 0x40 : 0) | + ((atari_switches&ATARI_SWITCH_SND7) ? 0x80 : 0); + } + + /* ++bjoern: + * Determine hardware present + */ + + pr_info("Atari hardware found:"); + if (MACH_IS_MEDUSA) { + /* There's no Atari video hardware on the Medusa, but all the + * addresses below generate a DTACK so no bus error occurs! */ + } else if (hwreg_present(f030_xreg)) { + ATARIHW_SET(VIDEL_SHIFTER); + pr_cont(" VIDEL"); + /* This is a temporary hack: If there is Falcon video + * hardware, we assume that the ST-DMA serves SCSI instead of + * ACSI. In the future, there should be a better method for + * this... + */ + ATARIHW_SET(ST_SCSI); + pr_cont(" STDMA-SCSI"); + } else if (hwreg_present(tt_palette)) { + ATARIHW_SET(TT_SHIFTER); + pr_cont(" TT_SHIFTER"); + } else if (hwreg_present(&shifter_st.bas_hi)) { + if (hwreg_present(&shifter_st.bas_lo) && + (shifter_st.bas_lo = 0x0aau, shifter_st.bas_lo == 0x0aau)) { + ATARIHW_SET(EXTD_SHIFTER); + pr_cont(" EXTD_SHIFTER"); + } else { + ATARIHW_SET(STND_SHIFTER); + pr_cont(" STND_SHIFTER"); + } + } + if (hwreg_present(&st_mfp.par_dt_reg)) { + ATARIHW_SET(ST_MFP); + pr_cont(" ST_MFP"); + } + if (hwreg_present(&tt_mfp.par_dt_reg)) { + ATARIHW_SET(TT_MFP); + pr_cont(" TT_MFP"); + } + if (hwreg_present(&tt_scsi_dma.dma_addr_hi)) { + ATARIHW_SET(SCSI_DMA); + pr_cont(" TT_SCSI_DMA"); + } + /* + * The ST-DMA address registers aren't readable + * on all Medusas, so the test below may fail + */ + if (MACH_IS_MEDUSA || + (hwreg_present(&st_dma.dma_vhi) && + (st_dma.dma_vhi = 0x55) && (st_dma.dma_hi = 0xaa) && + st_dma.dma_vhi == 0x55 && st_dma.dma_hi == 0xaa && + (st_dma.dma_vhi = 0xaa) && (st_dma.dma_hi = 0x55) && + st_dma.dma_vhi == 0xaa && st_dma.dma_hi == 0x55)) { + ATARIHW_SET(EXTD_DMA); + pr_cont(" EXTD_DMA"); + } + if (hwreg_present(&tt_scsi.scsi_data)) { + ATARIHW_SET(TT_SCSI); + pr_cont(" TT_SCSI"); + } + if (hwreg_present(&sound_ym.rd_data_reg_sel)) { + ATARIHW_SET(YM_2149); + pr_cont(" YM2149"); + } + if (!MACH_IS_MEDUSA && hwreg_present(&tt_dmasnd.ctrl)) { + ATARIHW_SET(PCM_8BIT); + pr_cont(" PCM"); + } + if (hwreg_present(&falcon_codec.unused5)) { + ATARIHW_SET(CODEC); + pr_cont(" CODEC"); + } + if (hwreg_present(&dsp56k_host_interface.icr)) { + ATARIHW_SET(DSP56K); + pr_cont(" DSP56K"); + } + if (hwreg_present(&tt_scc_dma.dma_ctrl) && +#if 0 + /* This test sucks! Who knows some better? */ + (tt_scc_dma.dma_ctrl = 0x01, (tt_scc_dma.dma_ctrl & 1) == 1) && + (tt_scc_dma.dma_ctrl = 0x00, (tt_scc_dma.dma_ctrl & 1) == 0) +#else + !MACH_IS_MEDUSA +#endif + ) { + ATARIHW_SET(SCC_DMA); + pr_cont(" SCC_DMA"); + } + if (scc_test(&atari_scc.cha_a_ctrl)) { + ATARIHW_SET(SCC); + pr_cont(" SCC"); + } + if (scc_test(&st_escc.cha_b_ctrl)) { + ATARIHW_SET(ST_ESCC); + pr_cont(" ST_ESCC"); + } + if (hwreg_present(&tt_scu.sys_mask)) { + ATARIHW_SET(SCU); + /* Assume a VME bus if there's a SCU */ + ATARIHW_SET(VME); + pr_cont(" VME SCU"); + } + if (hwreg_present((void *)(0xffff9210))) { + ATARIHW_SET(ANALOG_JOY); + pr_cont(" ANALOG_JOY"); + } + if (hwreg_present(blitter.halftone)) { + ATARIHW_SET(BLITTER); + pr_cont(" BLITTER"); + } + if (hwreg_present((void *)0xfff00039)) { + ATARIHW_SET(IDE); + pr_cont(" IDE"); + } +#if 1 /* This maybe wrong */ + if (!MACH_IS_MEDUSA && hwreg_present(&tt_microwire.data) && + hwreg_present(&tt_microwire.mask) && + (tt_microwire.mask = 0x7ff, + udelay(1), + tt_microwire.data = MW_LM1992_PSG_HIGH | MW_LM1992_ADDR, + udelay(1), + tt_microwire.data != 0)) { + ATARIHW_SET(MICROWIRE); + while (tt_microwire.mask != 0x7ff) + ; + pr_cont(" MICROWIRE"); + } +#endif + if (hwreg_present(&tt_rtc.regsel)) { + ATARIHW_SET(TT_CLK); + pr_cont(" TT_CLK"); + mach_hwclk = atari_tt_hwclk; + } + if (hwreg_present(&mste_rtc.sec_ones)) { + ATARIHW_SET(MSTE_CLK); + pr_cont(" MSTE_CLK"); + mach_hwclk = atari_mste_hwclk; + } + if (!MACH_IS_MEDUSA && hwreg_present(&dma_wd.fdc_speed) && + hwreg_write(&dma_wd.fdc_speed, 0)) { + ATARIHW_SET(FDCSPEED); + pr_cont(" FDC_SPEED"); + } + if (!ATARIHW_PRESENT(ST_SCSI)) { + ATARIHW_SET(ACSI); + pr_cont(" ACSI"); + } + pr_cont("\n"); + + if (CPU_IS_040_OR_060) + /* Now it seems to be safe to turn of the tt0 transparent + * translation (the one that must not be turned off in + * head.S...) + */ + asm volatile ("\n" + " moveq #0,%%d0\n" + " .chip 68040\n" + " movec %%d0,%%itt0\n" + " movec %%d0,%%dtt0\n" + " .chip 68k" + : /* no outputs */ + : /* no inputs */ + : "d0"); + + /* allocator for memory that must reside in st-ram */ + atari_stram_init(); + + /* Set up a mapping for the VMEbus address region: + * + * VME is either at phys. 0xfexxxxxx (TT) or 0xa00000..0xdfffff + * (MegaSTE) In both cases, the whole 16 MB chunk is mapped at + * 0xfe000000 virt., because this can be done with a single + * transparent translation. On the 68040, lots of often unused + * page tables would be needed otherwise. On a MegaSTE or similar, + * the highest byte is stripped off by hardware due to the 24 bit + * design of the bus. + */ + + if (CPU_IS_020_OR_030) { + unsigned long tt1_val; + tt1_val = 0xfe008543; /* Translate 0xfexxxxxx, enable, cache + * inhibit, read and write, FDC mask = 3, + * FDC val = 4 -> Supervisor only */ + asm volatile ("\n" + " .chip 68030\n" + " pmove %0,%/tt1\n" + " .chip 68k" + : : "m" (tt1_val)); + } else { + asm volatile ("\n" + " .chip 68040\n" + " movec %0,%%itt1\n" + " movec %0,%%dtt1\n" + " .chip 68k" + : + : "d" (0xfe00a040)); /* Translate 0xfexxxxxx, enable, + * supervisor only, non-cacheable/ + * serialized, writable */ + + } + + /* Fetch tos version at Physical 2 */ + /* + * We my not be able to access this address if the kernel is + * loaded to st ram, since the first page is unmapped. On the + * Medusa this is always the case and there is nothing we can do + * about this, so we just assume the smaller offset. For the TT + * we use the fact that in head.S we have set up a mapping + * 0xFFxxxxxx -> 0x00xxxxxx, so that the first 16MB is accessible + * in the last 16MB of the address space. + */ + tos_version = (MACH_IS_MEDUSA) ? + 0xfff : *(unsigned short *)0xff000002; + atari_rtc_year_offset = (tos_version < 0x306) ? 70 : 68; +} + +#ifdef CONFIG_HEARTBEAT +static void atari_heartbeat(int on) +{ + unsigned char tmp; + unsigned long flags; + + if (atari_dont_touch_floppy_select) + return; + + local_irq_save(flags); + sound_ym.rd_data_reg_sel = 14; /* Select PSG Port A */ + tmp = sound_ym.rd_data_reg_sel; + sound_ym.wd_data = on ? (tmp & ~0x02) : (tmp | 0x02); + local_irq_restore(flags); +} +#endif + +/* ++roman: + * + * This function does a reset on machines that lack the ability to + * assert the processor's _RESET signal somehow via hardware. It is + * based on the fact that you can find the initial SP and PC values + * after a reset at physical addresses 0 and 4. This works pretty well + * for Atari machines, since the lowest 8 bytes of physical memory are + * really ROM (mapped by hardware). For other 680x0 machines: don't + * know if it works... + * + * To get the values at addresses 0 and 4, the MMU better is turned + * off first. After that, we have to jump into physical address space + * (the PC before the pmove statement points to the virtual address of + * the code). Getting that physical address is not hard, but the code + * becomes a bit complex since I've tried to ensure that the jump + * statement after the pmove is in the cache already (otherwise the + * processor can't fetch it!). For that, the code first jumps to the + * jump statement with the (virtual) address of the pmove section in + * an address register . The jump statement is surely in the cache + * now. After that, that physical address of the reset code is loaded + * into the same address register, pmove is done and the same jump + * statements goes to the reset code. Since there are not many + * statements between the two jumps, I hope it stays in the cache. + * + * The C code makes heavy use of the GCC features that you can get the + * address of a C label. No hope to compile this with another compiler + * than GCC! + */ + +/* ++andreas: no need for complicated code, just depend on prefetch */ + +static void atari_reset(void) +{ + long tc_val = 0; + long reset_addr; + + /* + * On the Medusa, phys. 0x4 may contain garbage because it's no + * ROM. See above for explanation why we cannot use PTOV(4). + */ + reset_addr = MACH_IS_MEDUSA || MACH_IS_AB40 ? 0xe00030 : + *(unsigned long *) 0xff000004; + + /* reset ACIA for switch off OverScan, if it's active */ + if (atari_switches & ATARI_SWITCH_OVSC_IKBD) + acia.key_ctrl = ACIA_RESET; + if (atari_switches & ATARI_SWITCH_OVSC_MIDI) + acia.mid_ctrl = ACIA_RESET; + + /* processor independent: turn off interrupts and reset the VBR; + * the caches must be left enabled, else prefetching the final jump + * instruction doesn't work. + */ + local_irq_disable(); + asm volatile ("movec %0,%%vbr" + : : "d" (0)); + + if (CPU_IS_040_OR_060) { + unsigned long jmp_addr040 = virt_to_phys(&&jmp_addr_label040); + if (CPU_IS_060) { + /* 68060: clear PCR to turn off superscalar operation */ + asm volatile ("\n" + " .chip 68060\n" + " movec %0,%%pcr\n" + " .chip 68k" + : : "d" (0)); + } + + asm volatile ("\n" + " move.l %0,%%d0\n" + " and.l #0xff000000,%%d0\n" + " or.w #0xe020,%%d0\n" /* map 16 MB, enable, cacheable */ + " .chip 68040\n" + " movec %%d0,%%itt0\n" + " movec %%d0,%%dtt0\n" + " .chip 68k\n" + " jmp %0@" + : : "a" (jmp_addr040) + : "d0"); + jmp_addr_label040: + asm volatile ("\n" + " moveq #0,%%d0\n" + " nop\n" + " .chip 68040\n" + " cinva %%bc\n" + " nop\n" + " pflusha\n" + " nop\n" + " movec %%d0,%%tc\n" + " nop\n" + /* the following setup of transparent translations is needed on the + * Afterburner040 to successfully reboot. Other machines shouldn't + * care about a different tt regs setup, they also didn't care in + * the past that the regs weren't turned off. */ + " move.l #0xffc000,%%d0\n" /* whole insn space cacheable */ + " movec %%d0,%%itt0\n" + " movec %%d0,%%itt1\n" + " or.w #0x40,%/d0\n" /* whole data space non-cacheable/ser. */ + " movec %%d0,%%dtt0\n" + " movec %%d0,%%dtt1\n" + " .chip 68k\n" + " jmp %0@" + : /* no outputs */ + : "a" (reset_addr) + : "d0"); + } else + asm volatile ("\n" + " pmove %0,%%tc\n" + " jmp %1@" + : /* no outputs */ + : "m" (tc_val), "a" (reset_addr)); +} + + +static void atari_get_model(char *model) +{ + strcpy(model, "Atari "); + switch (atari_mch_cookie >> 16) { + case ATARI_MCH_ST: + if (ATARIHW_PRESENT(MSTE_CLK)) + strcat(model, "Mega ST"); + else + strcat(model, "ST"); + break; + case ATARI_MCH_STE: + if (MACH_IS_MSTE) + strcat(model, "Mega STE"); + else + strcat(model, "STE"); + break; + case ATARI_MCH_TT: + if (MACH_IS_MEDUSA) + /* Medusa has TT _MCH cookie */ + strcat(model, "Medusa"); + else + strcat(model, "TT"); + break; + case ATARI_MCH_FALCON: + strcat(model, "Falcon"); + if (MACH_IS_AB40) + strcat(model, " (with Afterburner040)"); + break; + default: + sprintf(model + strlen(model), "(unknown mach cookie 0x%lx)", + atari_mch_cookie); + break; + } +} + + +static void atari_get_hardware_list(struct seq_file *m) +{ + int i; + + for (i = 0; i < m68k_num_memory; i++) + seq_printf(m, "\t%3ld MB at 0x%08lx (%s)\n", + m68k_memory[i].size >> 20, m68k_memory[i].addr, + (m68k_memory[i].addr & 0xff000000 ? + "alternate RAM" : "ST-RAM")); + +#define ATARIHW_ANNOUNCE(name, str) \ + if (ATARIHW_PRESENT(name)) \ + seq_printf(m, "\t%s\n", str) + + seq_puts(m, "Detected hardware:\n"); + ATARIHW_ANNOUNCE(STND_SHIFTER, "ST Shifter"); + ATARIHW_ANNOUNCE(EXTD_SHIFTER, "STe Shifter"); + ATARIHW_ANNOUNCE(TT_SHIFTER, "TT Shifter"); + ATARIHW_ANNOUNCE(VIDEL_SHIFTER, "Falcon Shifter"); + ATARIHW_ANNOUNCE(YM_2149, "Programmable Sound Generator"); + ATARIHW_ANNOUNCE(PCM_8BIT, "PCM 8 Bit Sound"); + ATARIHW_ANNOUNCE(CODEC, "CODEC Sound"); + ATARIHW_ANNOUNCE(TT_SCSI, "SCSI Controller NCR5380 (TT style)"); + ATARIHW_ANNOUNCE(ST_SCSI, "SCSI Controller NCR5380 (Falcon style)"); + ATARIHW_ANNOUNCE(ACSI, "ACSI Interface"); + ATARIHW_ANNOUNCE(IDE, "IDE Interface"); + ATARIHW_ANNOUNCE(FDCSPEED, "8/16 Mhz Switch for FDC"); + ATARIHW_ANNOUNCE(ST_MFP, "Multi Function Peripheral MFP 68901"); + ATARIHW_ANNOUNCE(TT_MFP, "Second Multi Function Peripheral MFP 68901"); + ATARIHW_ANNOUNCE(SCC, "Serial Communications Controller SCC 8530"); + ATARIHW_ANNOUNCE(ST_ESCC, "Extended Serial Communications Controller SCC 85230"); + ATARIHW_ANNOUNCE(ANALOG_JOY, "Paddle Interface"); + ATARIHW_ANNOUNCE(MICROWIRE, "MICROWIRE(tm) Interface"); + ATARIHW_ANNOUNCE(STND_DMA, "DMA Controller (24 bit)"); + ATARIHW_ANNOUNCE(EXTD_DMA, "DMA Controller (32 bit)"); + ATARIHW_ANNOUNCE(SCSI_DMA, "DMA Controller for NCR5380"); + ATARIHW_ANNOUNCE(SCC_DMA, "DMA Controller for SCC"); + ATARIHW_ANNOUNCE(TT_CLK, "Clock Chip MC146818A"); + ATARIHW_ANNOUNCE(MSTE_CLK, "Clock Chip RP5C15"); + ATARIHW_ANNOUNCE(SCU, "System Control Unit"); + ATARIHW_ANNOUNCE(BLITTER, "Blitter"); + ATARIHW_ANNOUNCE(VME, "VME Bus"); + ATARIHW_ANNOUNCE(DSP56K, "DSP56001 processor"); +} + +/* + * MSch: initial platform device support for Atari, + * required for EtherNAT/EtherNEC/NetUSBee drivers + */ + +#if defined(CONFIG_ATARI_ETHERNAT) || defined(CONFIG_ATARI_ETHERNEC) +static void isp1160_delay(struct device *dev, int delay) +{ + ndelay(delay); +} +#endif + +#ifdef CONFIG_ATARI_ETHERNAT +/* + * EtherNAT: SMC91C111 Ethernet chipset, handled by smc91x driver + */ + +#define ATARI_ETHERNAT_IRQ 140 + +static struct resource smc91x_resources[] = { + [0] = { + .name = "smc91x-regs", + .start = ATARI_ETHERNAT_PHYS_ADDR, + .end = ATARI_ETHERNAT_PHYS_ADDR + 0xfffff, + .flags = IORESOURCE_MEM, + }, + [1] = { + .name = "smc91x-irq", + .start = ATARI_ETHERNAT_IRQ, + .end = ATARI_ETHERNAT_IRQ, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device smc91x_device = { + .name = "smc91x", + .id = -1, + .num_resources = ARRAY_SIZE(smc91x_resources), + .resource = smc91x_resources, +}; + +/* + * ISP 1160 - using the isp116x-hcd module + */ + +#define ATARI_USB_PHYS_ADDR 0x80000012 +#define ATARI_USB_IRQ 139 + +static struct resource isp1160_resources[] = { + [0] = { + .name = "isp1160-data", + .start = ATARI_USB_PHYS_ADDR, + .end = ATARI_USB_PHYS_ADDR + 0x1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .name = "isp1160-regs", + .start = ATARI_USB_PHYS_ADDR + 0x4, + .end = ATARI_USB_PHYS_ADDR + 0x5, + .flags = IORESOURCE_MEM, + }, + [2] = { + .name = "isp1160-irq", + .start = ATARI_USB_IRQ, + .end = ATARI_USB_IRQ, + .flags = IORESOURCE_IRQ, + }, +}; + +/* (DataBusWidth16|AnalogOCEnable|DREQOutputPolarity|DownstreamPort15KRSel ) */ +static struct isp116x_platform_data isp1160_platform_data = { + /* Enable internal resistors on downstream ports */ + .sel15Kres = 1, + /* On-chip overcurrent protection */ + .oc_enable = 1, + /* INT output polarity */ + .int_act_high = 1, + /* INT edge or level triggered */ + .int_edge_triggered = 0, + + /* WAKEUP pin connected - NOT SUPPORTED */ + /* .remote_wakeup_connected = 0, */ + /* Wakeup by devices on usb bus enabled */ + .remote_wakeup_enable = 0, + .delay = isp1160_delay, +}; + +static struct platform_device isp1160_device = { + .name = "isp116x-hcd", + .id = 0, + .num_resources = ARRAY_SIZE(isp1160_resources), + .resource = isp1160_resources, + .dev = { + .platform_data = &isp1160_platform_data, + }, +}; + +static struct platform_device *atari_ethernat_devices[] __initdata = { + &smc91x_device, + &isp1160_device +}; +#endif /* CONFIG_ATARI_ETHERNAT */ + +#ifdef CONFIG_ATARI_ETHERNEC +/* + * EtherNEC: RTL8019 (NE2000 compatible) Ethernet chipset, + * handled by ne.c driver + */ + +#define ATARI_ETHERNEC_PHYS_ADDR 0xfffa0000 +#define ATARI_ETHERNEC_BASE 0x300 +#define ATARI_ETHERNEC_IRQ IRQ_MFP_TIMER1 + +static struct resource rtl8019_resources[] = { + [0] = { + .name = "rtl8019-regs", + .start = ATARI_ETHERNEC_BASE, + .end = ATARI_ETHERNEC_BASE + 0x20 - 1, + .flags = IORESOURCE_IO, + }, + [1] = { + .name = "rtl8019-irq", + .start = ATARI_ETHERNEC_IRQ, + .end = ATARI_ETHERNEC_IRQ, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device rtl8019_device = { + .name = "ne", + .id = -1, + .num_resources = ARRAY_SIZE(rtl8019_resources), + .resource = rtl8019_resources, +}; + +/* + * NetUSBee: ISP1160 USB host adapter via ROM-port adapter + */ + +#define ATARI_NETUSBEE_PHYS_ADDR 0xfffa8000 +#define ATARI_NETUSBEE_BASE 0x340 +#define ATARI_NETUSBEE_IRQ IRQ_MFP_TIMER2 + +static struct resource netusbee_resources[] = { + [0] = { + .name = "isp1160-data", + .start = ATARI_NETUSBEE_BASE, + .end = ATARI_NETUSBEE_BASE + 0x1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .name = "isp1160-regs", + .start = ATARI_NETUSBEE_BASE + 0x20, + .end = ATARI_NETUSBEE_BASE + 0x21, + .flags = IORESOURCE_MEM, + }, + [2] = { + .name = "isp1160-irq", + .start = ATARI_NETUSBEE_IRQ, + .end = ATARI_NETUSBEE_IRQ, + .flags = IORESOURCE_IRQ, + }, +}; + +/* (DataBusWidth16|AnalogOCEnable|DREQOutputPolarity|DownstreamPort15KRSel ) */ +static struct isp116x_platform_data netusbee_platform_data = { + /* Enable internal resistors on downstream ports */ + .sel15Kres = 1, + /* On-chip overcurrent protection */ + .oc_enable = 1, + /* INT output polarity */ + .int_act_high = 1, + /* INT edge or level triggered */ + .int_edge_triggered = 0, + + /* WAKEUP pin connected - NOT SUPPORTED */ + /* .remote_wakeup_connected = 0, */ + /* Wakeup by devices on usb bus enabled */ + .remote_wakeup_enable = 0, + .delay = isp1160_delay, +}; + +static struct platform_device netusbee_device = { + .name = "isp116x-hcd", + .id = 1, + .num_resources = ARRAY_SIZE(netusbee_resources), + .resource = netusbee_resources, + .dev = { + .platform_data = &netusbee_platform_data, + }, +}; + +static struct platform_device *atari_netusbee_devices[] __initdata = { + &rtl8019_device, + &netusbee_device +}; +#endif /* CONFIG_ATARI_ETHERNEC */ + +#if IS_ENABLED(CONFIG_ATARI_SCSI) +static const struct resource atari_scsi_st_rsrc[] __initconst = { + { + .flags = IORESOURCE_IRQ, + .start = IRQ_MFP_FSCSI, + .end = IRQ_MFP_FSCSI, + }, +}; + +static const struct resource atari_scsi_tt_rsrc[] __initconst = { + { + .flags = IORESOURCE_IRQ, + .start = IRQ_TT_MFP_SCSI, + .end = IRQ_TT_MFP_SCSI, + }, +}; +#endif + +/* + * Falcon IDE interface + */ + +#define FALCON_IDE_BASE 0xfff00000 + +static const struct resource atari_falconide_rsrc[] __initconst = { + { + .flags = IORESOURCE_MEM, + .start = FALCON_IDE_BASE, + .end = FALCON_IDE_BASE + 0x39, + }, + { + .flags = IORESOURCE_IRQ, + .start = IRQ_MFP_FSCSI, + .end = IRQ_MFP_FSCSI, + }, +}; + +int __init atari_platform_init(void) +{ + struct platform_device *pdev; + int rv = 0; + + if (!MACH_IS_ATARI) + return -ENODEV; + +#ifdef CONFIG_ATARI_ETHERNAT + { + unsigned char *enatc_virt; + enatc_virt = (unsigned char *)ioremap((ATARI_ETHERNAT_PHYS_ADDR+0x23), 0xf); + if (hwreg_present(enatc_virt)) { + rv = platform_add_devices(atari_ethernat_devices, + ARRAY_SIZE(atari_ethernat_devices)); + } + iounmap(enatc_virt); + } +#endif + +#ifdef CONFIG_ATARI_ETHERNEC + { + int error; + unsigned char *enec_virt; + enec_virt = (unsigned char *)ioremap((ATARI_ETHERNEC_PHYS_ADDR), 0xf); + if (hwreg_present(enec_virt)) { + error = platform_add_devices(atari_netusbee_devices, + ARRAY_SIZE(atari_netusbee_devices)); + if (error && !rv) + rv = error; + } + iounmap(enec_virt); + } +#endif + +#if IS_ENABLED(CONFIG_ATARI_SCSI) + if (ATARIHW_PRESENT(ST_SCSI)) + platform_device_register_simple("atari_scsi", -1, + atari_scsi_st_rsrc, ARRAY_SIZE(atari_scsi_st_rsrc)); + else if (ATARIHW_PRESENT(TT_SCSI)) + platform_device_register_simple("atari_scsi", -1, + atari_scsi_tt_rsrc, ARRAY_SIZE(atari_scsi_tt_rsrc)); +#endif + + if (ATARIHW_PRESENT(IDE)) { + pdev = platform_device_register_simple("atari-falcon-ide", -1, + atari_falconide_rsrc, ARRAY_SIZE(atari_falconide_rsrc)); + if (IS_ERR(pdev)) + rv = PTR_ERR(pdev); + } + + return rv; +} + +arch_initcall(atari_platform_init); diff --git a/arch/m68k/atari/debug.c b/arch/m68k/atari/debug.c new file mode 100644 index 000000000..03cb5e08d --- /dev/null +++ b/arch/m68k/atari/debug.c @@ -0,0 +1,329 @@ +/* + * linux/arch/m68k/atari/debug.c + * + * Atari debugging and serial console stuff + * + * Assembled of parts of former atari/config.c 97-12-18 by Roman Hodek + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file COPYING in the main directory of this archive + * for more details. + */ + +#include +#include +#include +#include +#include +#include + +#include +#include + +/* Can be set somewhere, if a SCC master reset has already be done and should + * not be repeated; used by kgdb */ +int atari_SCC_reset_done; +EXPORT_SYMBOL(atari_SCC_reset_done); + +static struct console atari_console_driver = { + .name = "debug", + .flags = CON_PRINTBUFFER, + .index = -1, +}; + + +static inline void ata_mfp_out(char c) +{ + while (!(st_mfp.trn_stat & 0x80)) /* wait for tx buf empty */ + barrier(); + st_mfp.usart_dta = c; +} + +static void atari_mfp_console_write(struct console *co, const char *str, + unsigned int count) +{ + while (count--) { + if (*str == '\n') + ata_mfp_out('\r'); + ata_mfp_out(*str++); + } +} + +static inline void ata_scc_out(char c) +{ + do { + MFPDELAY(); + } while (!(atari_scc.cha_b_ctrl & 0x04)); /* wait for tx buf empty */ + MFPDELAY(); + atari_scc.cha_b_data = c; +} + +static void atari_scc_console_write(struct console *co, const char *str, + unsigned int count) +{ + while (count--) { + if (*str == '\n') + ata_scc_out('\r'); + ata_scc_out(*str++); + } +} + +static inline void ata_midi_out(char c) +{ + while (!(acia.mid_ctrl & ACIA_TDRE)) /* wait for tx buf empty */ + barrier(); + acia.mid_data = c; +} + +static void atari_midi_console_write(struct console *co, const char *str, + unsigned int count) +{ + while (count--) { + if (*str == '\n') + ata_midi_out('\r'); + ata_midi_out(*str++); + } +} + +static int ata_par_out(char c) +{ + unsigned char tmp; + /* This a some-seconds timeout in case no printer is connected */ + unsigned long i = loops_per_jiffy > 1 ? loops_per_jiffy : 10000000/HZ; + + while ((st_mfp.par_dt_reg & 1) && --i) /* wait for BUSY == L */ + ; + if (!i) + return 0; + + sound_ym.rd_data_reg_sel = 15; /* select port B */ + sound_ym.wd_data = c; /* put char onto port */ + sound_ym.rd_data_reg_sel = 14; /* select port A */ + tmp = sound_ym.rd_data_reg_sel; + sound_ym.wd_data = tmp & ~0x20; /* set strobe L */ + MFPDELAY(); /* wait a bit */ + sound_ym.wd_data = tmp | 0x20; /* set strobe H */ + return 1; +} + +static void atari_par_console_write(struct console *co, const char *str, + unsigned int count) +{ + static int printer_present = 1; + + if (!printer_present) + return; + + while (count--) { + if (*str == '\n') { + if (!ata_par_out('\r')) { + printer_present = 0; + return; + } + } + if (!ata_par_out(*str++)) { + printer_present = 0; + return; + } + } +} + +#if 0 +int atari_mfp_console_wait_key(struct console *co) +{ + while (!(st_mfp.rcv_stat & 0x80)) /* wait for rx buf filled */ + barrier(); + return st_mfp.usart_dta; +} + +int atari_scc_console_wait_key(struct console *co) +{ + do { + MFPDELAY(); + } while (!(atari_scc.cha_b_ctrl & 0x01)); /* wait for rx buf filled */ + MFPDELAY(); + return atari_scc.cha_b_data; +} + +int atari_midi_console_wait_key(struct console *co) +{ + while (!(acia.mid_ctrl & ACIA_RDRF)) /* wait for rx buf filled */ + barrier(); + return acia.mid_data; +} +#endif + +/* + * The following two functions do a quick'n'dirty initialization of the MFP or + * SCC serial ports. They're used by the debugging interface, kgdb, and the + * serial console code. + */ +static void __init atari_init_mfp_port(int cflag) +{ + /* + * timer values for 1200...115200 bps; > 38400 select 110, 134, or 150 + * bps, resp., and work only correct if there's a RSVE or RSSPEED + */ + static int baud_table[9] = { 16, 11, 8, 4, 2, 1, 175, 143, 128 }; + int baud = cflag & CBAUD; + int parity = (cflag & PARENB) ? ((cflag & PARODD) ? 0x04 : 0x06) : 0; + int csize = ((cflag & CSIZE) == CS7) ? 0x20 : 0x00; + + if (cflag & CBAUDEX) + baud += B38400; + if (baud < B1200 || baud > B38400+2) + baud = B9600; /* use default 9600bps for non-implemented rates */ + baud -= B1200; /* baud_table[] starts at 1200bps */ + + st_mfp.trn_stat &= ~0x01; /* disable TX */ + st_mfp.usart_ctr = parity | csize | 0x88; /* 1:16 clk mode, 1 stop bit */ + st_mfp.tim_ct_cd &= 0x70; /* stop timer D */ + st_mfp.tim_dt_d = baud_table[baud]; + st_mfp.tim_ct_cd |= 0x01; /* start timer D, 1:4 */ + st_mfp.trn_stat |= 0x01; /* enable TX */ +} + +#define SCC_WRITE(reg, val) \ + do { \ + atari_scc.cha_b_ctrl = (reg); \ + MFPDELAY(); \ + atari_scc.cha_b_ctrl = (val); \ + MFPDELAY(); \ + } while (0) + +/* loops_per_jiffy isn't initialized yet, so we can't use udelay(). This does a + * delay of ~ 60us. */ +#define LONG_DELAY() \ + do { \ + int i; \ + for (i = 100; i > 0; --i) \ + MFPDELAY(); \ + } while (0) + +static void __init atari_init_scc_port(int cflag) +{ + static int clksrc_table[9] = + /* reg 11: 0x50 = BRG, 0x00 = RTxC, 0x28 = TRxC */ + { 0x50, 0x50, 0x50, 0x50, 0x50, 0x50, 0x50, 0x00, 0x00 }; + static int brgsrc_table[9] = + /* reg 14: 0 = RTxC, 2 = PCLK */ + { 2, 2, 2, 2, 2, 2, 0, 2, 2 }; + static int clkmode_table[9] = + /* reg 4: 0x40 = x16, 0x80 = x32, 0xc0 = x64 */ + { 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0xc0, 0x80 }; + static int div_table[9] = + /* reg12 (BRG low) */ + { 208, 138, 103, 50, 24, 11, 1, 0, 0 }; + + int baud = cflag & CBAUD; + int clksrc, clkmode, div, reg3, reg5; + + if (cflag & CBAUDEX) + baud += B38400; + if (baud < B1200 || baud > B38400+2) + baud = B9600; /* use default 9600bps for non-implemented rates */ + baud -= B1200; /* tables starts at 1200bps */ + + clksrc = clksrc_table[baud]; + clkmode = clkmode_table[baud]; + div = div_table[baud]; + if (ATARIHW_PRESENT(TT_MFP) && baud >= 6) { + /* special treatment for TT, where rates >= 38400 are done via TRxC */ + clksrc = 0x28; /* TRxC */ + clkmode = baud == 6 ? 0xc0 : + baud == 7 ? 0x80 : /* really 76800bps */ + 0x40; /* really 153600bps */ + div = 0; + } + + reg3 = (cflag & CSIZE) == CS8 ? 0xc0 : 0x40; + reg5 = (cflag & CSIZE) == CS8 ? 0x60 : 0x20 | 0x82 /* assert DTR/RTS */; + + (void)atari_scc.cha_b_ctrl; /* reset reg pointer */ + SCC_WRITE(9, 0xc0); /* reset */ + LONG_DELAY(); /* extra delay after WR9 access */ + SCC_WRITE(4, (cflag & PARENB) ? ((cflag & PARODD) ? 0x01 : 0x03) + : 0 | 0x04 /* 1 stopbit */ | clkmode); + SCC_WRITE(3, reg3); + SCC_WRITE(5, reg5); + SCC_WRITE(9, 0); /* no interrupts */ + LONG_DELAY(); /* extra delay after WR9 access */ + SCC_WRITE(10, 0); /* NRZ mode */ + SCC_WRITE(11, clksrc); /* main clock source */ + SCC_WRITE(12, div); /* BRG value */ + SCC_WRITE(13, 0); /* BRG high byte */ + SCC_WRITE(14, brgsrc_table[baud]); + SCC_WRITE(14, brgsrc_table[baud] | (div ? 1 : 0)); + SCC_WRITE(3, reg3 | 1); + SCC_WRITE(5, reg5 | 8); + + atari_SCC_reset_done = 1; +} + +static void __init atari_init_midi_port(int cflag) +{ + int baud = cflag & CBAUD; + int csize = ((cflag & CSIZE) == CS8) ? 0x10 : 0x00; + /* warning 7N1 isn't possible! (instead 7O2 is used...) */ + int parity = (cflag & PARENB) ? ((cflag & PARODD) ? 0x0c : 0x08) : 0x04; + int div; + + /* 4800 selects 7812.5, 115200 selects 500000, all other (incl. 9600 as + * default) the standard MIDI speed 31250. */ + if (cflag & CBAUDEX) + baud += B38400; + if (baud == B4800) + div = ACIA_DIV64; /* really 7812.5 bps */ + else if (baud == B38400+2 /* 115200 */) + div = ACIA_DIV1; /* really 500 kbps (does that work??) */ + else + div = ACIA_DIV16; /* 31250 bps, standard for MIDI */ + + /* RTS low, ints disabled */ + acia.mid_ctrl = div | csize | parity | + ((atari_switches & ATARI_SWITCH_MIDI) ? + ACIA_RHTID : ACIA_RLTID); +} + +static int __init atari_debug_setup(char *arg) +{ + bool registered; + + if (!MACH_IS_ATARI) + return 0; + + if (!strcmp(arg, "ser")) + /* defaults to ser2 for a Falcon and ser1 otherwise */ + arg = MACH_IS_FALCON ? "ser2" : "ser1"; + + registered = !!atari_console_driver.write; + if (!strcmp(arg, "ser1")) { + /* ST-MFP Modem1 serial port */ + atari_init_mfp_port(B9600|CS8); + atari_console_driver.write = atari_mfp_console_write; + } else if (!strcmp(arg, "ser2")) { + /* SCC Modem2 serial port */ + atari_init_scc_port(B9600|CS8); + atari_console_driver.write = atari_scc_console_write; + } else if (!strcmp(arg, "midi")) { + /* MIDI port */ + atari_init_midi_port(B9600|CS8); + atari_console_driver.write = atari_midi_console_write; + } else if (!strcmp(arg, "par")) { + /* parallel printer */ + atari_turnoff_irq(IRQ_MFP_BUSY); /* avoid ints */ + sound_ym.rd_data_reg_sel = 7; /* select mixer control */ + sound_ym.wd_data = 0xff; /* sound off, ports are output */ + sound_ym.rd_data_reg_sel = 15; /* select port B */ + sound_ym.wd_data = 0; /* no char */ + sound_ym.rd_data_reg_sel = 14; /* select port A */ + sound_ym.wd_data = sound_ym.rd_data_reg_sel | 0x20; /* strobe H */ + atari_console_driver.write = atari_par_console_write; + } + if (atari_console_driver.write && !registered) + register_console(&atari_console_driver); + + return 0; +} + +early_param("debug", atari_debug_setup); diff --git a/arch/m68k/atari/nvram.c b/arch/m68k/atari/nvram.c new file mode 100644 index 000000000..7000d2443 --- /dev/null +++ b/arch/m68k/atari/nvram.c @@ -0,0 +1,272 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * CMOS/NV-RAM driver for Atari. Adapted from drivers/char/nvram.c. + * Copyright (C) 1997 Roman Hodek + * idea by and with help from Richard Jelinek + * Portions copyright (c) 2001,2002 Sun Microsystems (thockin@sun.com) + * Further contributions from Cesar Barros, Erik Gilling, Tim Hockin and + * Wim Van Sebroeck. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define NVRAM_BYTES 50 + +/* It is worth noting that these functions all access bytes of general + * purpose memory in the NVRAM - that is to say, they all add the + * NVRAM_FIRST_BYTE offset. Pass them offsets into NVRAM as if you did not + * know about the RTC cruft. + */ + +/* Note that *all* calls to CMOS_READ and CMOS_WRITE must be done with + * rtc_lock held. Due to the index-port/data-port design of the RTC, we + * don't want two different things trying to get to it at once. (e.g. the + * periodic 11 min sync from kernel/time/ntp.c vs. this driver.) + */ + +static unsigned char __nvram_read_byte(int i) +{ + return CMOS_READ(NVRAM_FIRST_BYTE + i); +} + +/* This races nicely with trying to read with checksum checking */ +static void __nvram_write_byte(unsigned char c, int i) +{ + CMOS_WRITE(c, NVRAM_FIRST_BYTE + i); +} + +/* On Ataris, the checksum is over all bytes except the checksum bytes + * themselves; these are at the very end. + */ +#define ATARI_CKS_RANGE_START 0 +#define ATARI_CKS_RANGE_END 47 +#define ATARI_CKS_LOC 48 + +static int __nvram_check_checksum(void) +{ + int i; + unsigned char sum = 0; + + for (i = ATARI_CKS_RANGE_START; i <= ATARI_CKS_RANGE_END; ++i) + sum += __nvram_read_byte(i); + return (__nvram_read_byte(ATARI_CKS_LOC) == (~sum & 0xff)) && + (__nvram_read_byte(ATARI_CKS_LOC + 1) == (sum & 0xff)); +} + +static void __nvram_set_checksum(void) +{ + int i; + unsigned char sum = 0; + + for (i = ATARI_CKS_RANGE_START; i <= ATARI_CKS_RANGE_END; ++i) + sum += __nvram_read_byte(i); + __nvram_write_byte(~sum, ATARI_CKS_LOC); + __nvram_write_byte(sum, ATARI_CKS_LOC + 1); +} + +long atari_nvram_set_checksum(void) +{ + spin_lock_irq(&rtc_lock); + __nvram_set_checksum(); + spin_unlock_irq(&rtc_lock); + return 0; +} + +long atari_nvram_initialize(void) +{ + loff_t i; + + spin_lock_irq(&rtc_lock); + for (i = 0; i < NVRAM_BYTES; ++i) + __nvram_write_byte(0, i); + __nvram_set_checksum(); + spin_unlock_irq(&rtc_lock); + return 0; +} + +ssize_t atari_nvram_read(char *buf, size_t count, loff_t *ppos) +{ + char *p = buf; + loff_t i; + + spin_lock_irq(&rtc_lock); + if (!__nvram_check_checksum()) { + spin_unlock_irq(&rtc_lock); + return -EIO; + } + for (i = *ppos; count > 0 && i < NVRAM_BYTES; --count, ++i, ++p) + *p = __nvram_read_byte(i); + spin_unlock_irq(&rtc_lock); + + *ppos = i; + return p - buf; +} + +ssize_t atari_nvram_write(char *buf, size_t count, loff_t *ppos) +{ + char *p = buf; + loff_t i; + + spin_lock_irq(&rtc_lock); + if (!__nvram_check_checksum()) { + spin_unlock_irq(&rtc_lock); + return -EIO; + } + for (i = *ppos; count > 0 && i < NVRAM_BYTES; --count, ++i, ++p) + __nvram_write_byte(*p, i); + __nvram_set_checksum(); + spin_unlock_irq(&rtc_lock); + + *ppos = i; + return p - buf; +} + +ssize_t atari_nvram_get_size(void) +{ + return NVRAM_BYTES; +} + +#ifdef CONFIG_PROC_FS +static struct { + unsigned char val; + const char *name; +} boot_prefs[] = { + { 0x80, "TOS" }, + { 0x40, "ASV" }, + { 0x20, "NetBSD (?)" }, + { 0x10, "Linux" }, + { 0x00, "unspecified" }, +}; + +static const char * const languages[] = { + "English (US)", + "German", + "French", + "English (UK)", + "Spanish", + "Italian", + "6 (undefined)", + "Swiss (French)", + "Swiss (German)", +}; + +static const char * const dateformat[] = { + "MM%cDD%cYY", + "DD%cMM%cYY", + "YY%cMM%cDD", + "YY%cDD%cMM", + "4 (undefined)", + "5 (undefined)", + "6 (undefined)", + "7 (undefined)", +}; + +static const char * const colors[] = { + "2", "4", "16", "256", "65536", "??", "??", "??" +}; + +static void atari_nvram_proc_read(unsigned char *nvram, struct seq_file *seq, + void *offset) +{ + int checksum; + int i; + unsigned int vmode; + + spin_lock_irq(&rtc_lock); + checksum = __nvram_check_checksum(); + spin_unlock_irq(&rtc_lock); + + seq_printf(seq, "Checksum status : %svalid\n", checksum ? "" : "not "); + + seq_puts(seq, "Boot preference : "); + for (i = ARRAY_SIZE(boot_prefs) - 1; i >= 0; --i) + if (nvram[1] == boot_prefs[i].val) { + seq_printf(seq, "%s\n", boot_prefs[i].name); + break; + } + if (i < 0) + seq_printf(seq, "0x%02x (undefined)\n", nvram[1]); + + seq_printf(seq, "SCSI arbitration : %s\n", + (nvram[16] & 0x80) ? "on" : "off"); + seq_puts(seq, "SCSI host ID : "); + if (nvram[16] & 0x80) + seq_printf(seq, "%d\n", nvram[16] & 7); + else + seq_puts(seq, "n/a\n"); + + if (!MACH_IS_FALCON) + return; + + seq_puts(seq, "OS language : "); + if (nvram[6] < ARRAY_SIZE(languages)) + seq_printf(seq, "%s\n", languages[nvram[6]]); + else + seq_printf(seq, "%u (undefined)\n", nvram[6]); + seq_puts(seq, "Keyboard language: "); + if (nvram[7] < ARRAY_SIZE(languages)) + seq_printf(seq, "%s\n", languages[nvram[7]]); + else + seq_printf(seq, "%u (undefined)\n", nvram[7]); + seq_puts(seq, "Date format : "); + seq_printf(seq, dateformat[nvram[8] & 7], + nvram[9] ? nvram[9] : '/', nvram[9] ? nvram[9] : '/'); + seq_printf(seq, ", %dh clock\n", nvram[8] & 16 ? 24 : 12); + seq_puts(seq, "Boot delay : "); + if (nvram[10] == 0) + seq_puts(seq, "default\n"); + else + seq_printf(seq, "%ds%s\n", nvram[10], + nvram[10] < 8 ? ", no memory test" : ""); + + vmode = (nvram[14] << 8) | nvram[15]; + seq_printf(seq, + "Video mode : %s colors, %d columns, %s %s monitor\n", + colors[vmode & 7], vmode & 8 ? 80 : 40, + vmode & 16 ? "VGA" : "TV", vmode & 32 ? "PAL" : "NTSC"); + seq_printf(seq, + " %soverscan, compat. mode %s%s\n", + vmode & 64 ? "" : "no ", vmode & 128 ? "on" : "off", + vmode & 256 ? + (vmode & 16 ? ", line doubling" : ", half screen") : ""); +} + +static int nvram_proc_read(struct seq_file *seq, void *offset) +{ + unsigned char contents[NVRAM_BYTES]; + int i; + + spin_lock_irq(&rtc_lock); + for (i = 0; i < NVRAM_BYTES; ++i) + contents[i] = __nvram_read_byte(i); + spin_unlock_irq(&rtc_lock); + + atari_nvram_proc_read(contents, seq, offset); + + return 0; +} + +static int __init atari_nvram_init(void) +{ + if (!(MACH_IS_ATARI && ATARIHW_PRESENT(TT_CLK))) + return -ENODEV; + + if (!proc_create_single("driver/nvram", 0, NULL, nvram_proc_read)) { + pr_err("nvram: can't create /proc/driver/nvram\n"); + return -ENOMEM; + } + + return 0; +} +device_initcall(atari_nvram_init); +#endif /* CONFIG_PROC_FS */ diff --git a/arch/m68k/atari/stdma.c b/arch/m68k/atari/stdma.c new file mode 100644 index 000000000..ba65f942d --- /dev/null +++ b/arch/m68k/atari/stdma.c @@ -0,0 +1,220 @@ +/* + * linux/arch/m68k/atari/stmda.c + * + * Copyright (C) 1994 Roman Hodek + * + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file COPYING in the main directory of this archive + * for more details. + */ + + +/* This file contains some function for controlling the access to the */ +/* ST-DMA chip that may be shared between devices. Currently we have: */ +/* TT: Floppy and ACSI bus */ +/* Falcon: Floppy and SCSI */ +/* */ +/* The controlling functions set up a wait queue for access to the */ +/* ST-DMA chip. Callers to stdma_lock() that cannot granted access are */ +/* put onto a queue and waked up later if the owner calls */ +/* stdma_release(). Additionally, the caller gives his interrupt */ +/* service routine to stdma_lock(). */ +/* */ +/* On the Falcon, the IDE bus uses just the ACSI/Floppy interrupt, but */ +/* not the ST-DMA chip itself. So falhd.c needs not to lock the */ +/* chip. The interrupt is routed to falhd.c if IDE is configured, the */ +/* model is a Falcon and the interrupt was caused by the HD controller */ +/* (can be determined by looking at its status register). */ + + +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include + +static int stdma_locked; /* the semaphore */ + /* int func to be called */ +static irq_handler_t stdma_isr; +static void *stdma_isr_data; /* data passed to isr */ +static DECLARE_WAIT_QUEUE_HEAD(stdma_wait); /* wait queue for ST-DMA */ + + + + +/***************************** Prototypes *****************************/ + +static irqreturn_t stdma_int (int irq, void *dummy); + +/************************* End of Prototypes **************************/ + + +/** + * stdma_try_lock - attempt to acquire ST DMA interrupt "lock" + * @handler: interrupt handler to use after acquisition + * + * Returns !0 if lock was acquired; otherwise 0. + */ + +int stdma_try_lock(irq_handler_t handler, void *data) +{ + unsigned long flags; + + local_irq_save(flags); + if (stdma_locked) { + local_irq_restore(flags); + return 0; + } + + stdma_locked = 1; + stdma_isr = handler; + stdma_isr_data = data; + local_irq_restore(flags); + return 1; +} +EXPORT_SYMBOL(stdma_try_lock); + + +/* + * Function: void stdma_lock( isrfunc isr, void *data ) + * + * Purpose: Tries to get a lock on the ST-DMA chip that is used by more + * then one device driver. Waits on stdma_wait until lock is free. + * stdma_lock() may not be called from an interrupt! You have to + * get the lock in your main routine and release it when your + * request is finished. + * + * Inputs: A interrupt function that is called until the lock is + * released. + * + * Returns: nothing + * + */ + +void stdma_lock(irq_handler_t handler, void *data) +{ + /* Since the DMA is used for file system purposes, we + have to sleep uninterruptible (there may be locked + buffers) */ + wait_event(stdma_wait, stdma_try_lock(handler, data)); +} +EXPORT_SYMBOL(stdma_lock); + + +/* + * Function: void stdma_release( void ) + * + * Purpose: Releases the lock on the ST-DMA chip. + * + * Inputs: none + * + * Returns: nothing + * + */ + +void stdma_release(void) +{ + unsigned long flags; + + local_irq_save(flags); + + stdma_locked = 0; + stdma_isr = NULL; + stdma_isr_data = NULL; + wake_up(&stdma_wait); + + local_irq_restore(flags); +} +EXPORT_SYMBOL(stdma_release); + + +/** + * stdma_is_locked_by - allow lock holder to check whether it needs to release. + * @handler: interrupt handler previously used to acquire lock. + * + * Returns !0 if locked for the given handler; 0 otherwise. + */ + +int stdma_is_locked_by(irq_handler_t handler) +{ + unsigned long flags; + int result; + + local_irq_save(flags); + result = stdma_locked && (stdma_isr == handler); + local_irq_restore(flags); + + return result; +} +EXPORT_SYMBOL(stdma_is_locked_by); + + +/* + * Function: int stdma_islocked( void ) + * + * Purpose: Check if the ST-DMA is currently locked. + * Note: Returned status is only valid if ints are disabled while calling and + * as long as they remain disabled. + * If called with ints enabled, status can change only from locked to + * unlocked, because ints may not lock the ST-DMA. + * + * Inputs: none + * + * Returns: != 0 if locked, 0 otherwise + * + */ + +int stdma_islocked(void) +{ + return stdma_locked; +} +EXPORT_SYMBOL(stdma_islocked); + + +/* + * Function: void stdma_init( void ) + * + * Purpose: Initialize the ST-DMA chip access controlling. + * It sets up the interrupt and its service routine. The int is registered + * as slow int, client devices have to live with that (no problem + * currently). + * + * Inputs: none + * + * Return: nothing + * + */ + +void __init stdma_init(void) +{ + stdma_isr = NULL; + if (request_irq(IRQ_MFP_FDC, stdma_int, IRQF_SHARED, + "ST-DMA floppy,ACSI,IDE,Falcon-SCSI", stdma_int)) + pr_err("Couldn't register ST-DMA interrupt\n"); +} + + +/* + * Function: void stdma_int() + * + * Purpose: The interrupt routine for the ST-DMA. It calls the isr + * registered by stdma_lock(). + * + */ + +static irqreturn_t stdma_int(int irq, void *dummy) +{ + if (stdma_isr) + (*stdma_isr)(irq, stdma_isr_data); + return IRQ_HANDLED; +} diff --git a/arch/m68k/atari/stram.c b/arch/m68k/atari/stram.c new file mode 100644 index 000000000..ce79b322a --- /dev/null +++ b/arch/m68k/atari/stram.c @@ -0,0 +1,202 @@ +/* + * Functions for ST-RAM allocations + * + * Copyright 1994-97 Roman Hodek + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file COPYING in the main directory of this archive + * for more details. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include + + +/* + * The ST-RAM allocator allocates memory from a pool of reserved ST-RAM of + * configurable size, set aside on ST-RAM init. + * As long as this pool is not exhausted, allocation of real ST-RAM can be + * guaranteed. + */ + +/* set if kernel is in ST-RAM */ +static int kernel_in_stram; + +static struct resource stram_pool = { + .name = "ST-RAM Pool" +}; + +static unsigned long pool_size = 1024*1024; + +static unsigned long stram_virt_offset; + +static int __init atari_stram_setup(char *arg) +{ + if (!MACH_IS_ATARI) + return 0; + + pool_size = memparse(arg, NULL); + return 0; +} + +early_param("stram_pool", atari_stram_setup); + + +/* + * This init function is called very early by atari/config.c + * It initializes some internal variables needed for stram_alloc() + */ +void __init atari_stram_init(void) +{ + int i; + + /* + * determine whether kernel code resides in ST-RAM + * (then ST-RAM is the first memory block at virtual 0x0) + */ + kernel_in_stram = (m68k_memory[0].addr == 0); + + for (i = 0; i < m68k_num_memory; ++i) { + if (m68k_memory[i].addr == 0) { + return; + } + } + + /* Should never come here! (There is always ST-Ram!) */ + panic("atari_stram_init: no ST-RAM found!"); +} + + +/* + * This function is called from setup_arch() to reserve the pages needed for + * ST-RAM management, if the kernel resides in ST-RAM. + */ +void __init atari_stram_reserve_pages(void *start_mem) +{ + if (kernel_in_stram) { + pr_debug("atari_stram pool: kernel in ST-RAM, using alloc_bootmem!\n"); + stram_pool.start = (resource_size_t)memblock_alloc_low(pool_size, + PAGE_SIZE); + if (!stram_pool.start) + panic("%s: Failed to allocate %lu bytes align=%lx\n", + __func__, pool_size, PAGE_SIZE); + + stram_pool.end = stram_pool.start + pool_size - 1; + request_resource(&iomem_resource, &stram_pool); + stram_virt_offset = 0; + pr_debug("atari_stram pool: size = %lu bytes, resource = %pR\n", + pool_size, &stram_pool); + pr_debug("atari_stram pool: stram_virt_offset = %lx\n", + stram_virt_offset); + } +} + + +/* + * This function is called as arch initcall to reserve the pages needed for + * ST-RAM management, if the kernel does not reside in ST-RAM. + */ +int __init atari_stram_map_pages(void) +{ + if (!kernel_in_stram) { + /* + * Skip page 0, as the fhe first 2 KiB are supervisor-only! + */ + pr_debug("atari_stram pool: kernel not in ST-RAM, using ioremap!\n"); + stram_pool.start = PAGE_SIZE; + stram_pool.end = stram_pool.start + pool_size - 1; + request_resource(&iomem_resource, &stram_pool); + stram_virt_offset = (unsigned long) ioremap(stram_pool.start, + resource_size(&stram_pool)) - stram_pool.start; + pr_debug("atari_stram pool: size = %lu bytes, resource = %pR\n", + pool_size, &stram_pool); + pr_debug("atari_stram pool: stram_virt_offset = %lx\n", + stram_virt_offset); + } + return 0; +} +arch_initcall(atari_stram_map_pages); + + +void *atari_stram_to_virt(unsigned long phys) +{ + return (void *)(phys + stram_virt_offset); +} +EXPORT_SYMBOL(atari_stram_to_virt); + + +unsigned long atari_stram_to_phys(void *virt) +{ + return (unsigned long)(virt - stram_virt_offset); +} +EXPORT_SYMBOL(atari_stram_to_phys); + + +void *atari_stram_alloc(unsigned long size, const char *owner) +{ + struct resource *res; + int error; + + pr_debug("atari_stram_alloc: allocate %lu bytes\n", size); + + /* round up */ + size = PAGE_ALIGN(size); + + res = kzalloc(sizeof(struct resource), GFP_KERNEL); + if (!res) + return NULL; + + res->name = owner; + error = allocate_resource(&stram_pool, res, size, 0, UINT_MAX, + PAGE_SIZE, NULL, NULL); + if (error < 0) { + pr_err("atari_stram_alloc: allocate_resource() failed %d!\n", + error); + kfree(res); + return NULL; + } + + pr_debug("atari_stram_alloc: returning %pR\n", res); + return atari_stram_to_virt(res->start); +} +EXPORT_SYMBOL(atari_stram_alloc); + + +void atari_stram_free(void *addr) +{ + unsigned long start = atari_stram_to_phys(addr); + struct resource *res; + unsigned long size; + + res = lookup_resource(&stram_pool, start); + if (!res) { + pr_err("atari_stram_free: trying to free nonexistent region " + "at %p\n", addr); + return; + } + + size = resource_size(res); + pr_debug("atari_stram_free: free %lu bytes at %p\n", size, addr); + release_resource(res); + kfree(res); +} +EXPORT_SYMBOL(atari_stram_free); diff --git a/arch/m68k/atari/time.c b/arch/m68k/atari/time.c new file mode 100644 index 000000000..ce923a523 --- /dev/null +++ b/arch/m68k/atari/time.c @@ -0,0 +1,325 @@ +/* + * linux/arch/m68k/atari/time.c + * + * Atari time and real time clock stuff + * + * Assembled of parts of former atari/config.c 97-12-18 by Roman Hodek + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file COPYING in the main directory of this archive + * for more details. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +DEFINE_SPINLOCK(rtc_lock); +EXPORT_SYMBOL_GPL(rtc_lock); + +static u64 atari_read_clk(struct clocksource *cs); + +static struct clocksource atari_clk = { + .name = "mfp", + .rating = 100, + .read = atari_read_clk, + .mask = CLOCKSOURCE_MASK(32), + .flags = CLOCK_SOURCE_IS_CONTINUOUS, +}; + +static u32 clk_total; +static u8 last_timer_count; + +static irqreturn_t mfp_timer_c_handler(int irq, void *dev_id) +{ + irq_handler_t timer_routine = dev_id; + unsigned long flags; + + local_irq_save(flags); + do { + last_timer_count = st_mfp.tim_dt_c; + } while (last_timer_count == 1); + clk_total += INT_TICKS; + timer_routine(0, NULL); + local_irq_restore(flags); + + return IRQ_HANDLED; +} + +void __init +atari_sched_init(irq_handler_t timer_routine) +{ + /* set Timer C data Register */ + st_mfp.tim_dt_c = INT_TICKS; + /* start timer C, div = 1:100 */ + st_mfp.tim_ct_cd = (st_mfp.tim_ct_cd & 15) | 0x60; + /* install interrupt service routine for MFP Timer C */ + if (request_irq(IRQ_MFP_TIMC, mfp_timer_c_handler, IRQF_TIMER, "timer", + timer_routine)) + pr_err("Couldn't register timer interrupt\n"); + + clocksource_register_hz(&atari_clk, INT_CLK); +} + +/* ++andreas: gettimeoffset fixed to check for pending interrupt */ + +static u64 atari_read_clk(struct clocksource *cs) +{ + unsigned long flags; + u8 count; + u32 ticks; + + local_irq_save(flags); + /* Ensure that the count is monotonically decreasing, even though + * the result may briefly stop changing after counter wrap-around. + */ + count = min(st_mfp.tim_dt_c, last_timer_count); + last_timer_count = count; + + ticks = INT_TICKS - count; + ticks += clk_total; + local_irq_restore(flags); + + return ticks; +} + + +static void mste_read(struct MSTE_RTC *val) +{ +#define COPY(v) val->v=(mste_rtc.v & 0xf) + do { + COPY(sec_ones) ; COPY(sec_tens) ; COPY(min_ones) ; + COPY(min_tens) ; COPY(hr_ones) ; COPY(hr_tens) ; + COPY(weekday) ; COPY(day_ones) ; COPY(day_tens) ; + COPY(mon_ones) ; COPY(mon_tens) ; COPY(year_ones) ; + COPY(year_tens) ; + /* prevent from reading the clock while it changed */ + } while (val->sec_ones != (mste_rtc.sec_ones & 0xf)); +#undef COPY +} + +static void mste_write(struct MSTE_RTC *val) +{ +#define COPY(v) mste_rtc.v=val->v + do { + COPY(sec_ones) ; COPY(sec_tens) ; COPY(min_ones) ; + COPY(min_tens) ; COPY(hr_ones) ; COPY(hr_tens) ; + COPY(weekday) ; COPY(day_ones) ; COPY(day_tens) ; + COPY(mon_ones) ; COPY(mon_tens) ; COPY(year_ones) ; + COPY(year_tens) ; + /* prevent from writing the clock while it changed */ + } while (val->sec_ones != (mste_rtc.sec_ones & 0xf)); +#undef COPY +} + +#define RTC_READ(reg) \ + ({ unsigned char __val; \ + (void) atari_writeb(reg,&tt_rtc.regsel); \ + __val = tt_rtc.data; \ + __val; \ + }) + +#define RTC_WRITE(reg,val) \ + do { \ + atari_writeb(reg,&tt_rtc.regsel); \ + tt_rtc.data = (val); \ + } while(0) + + +#define HWCLK_POLL_INTERVAL 5 + +int atari_mste_hwclk( int op, struct rtc_time *t ) +{ + int hour, year; + int hr24=0; + struct MSTE_RTC val; + + mste_rtc.mode=(mste_rtc.mode | 1); + hr24=mste_rtc.mon_tens & 1; + mste_rtc.mode=(mste_rtc.mode & ~1); + + if (op) { + /* write: prepare values */ + + val.sec_ones = t->tm_sec % 10; + val.sec_tens = t->tm_sec / 10; + val.min_ones = t->tm_min % 10; + val.min_tens = t->tm_min / 10; + hour = t->tm_hour; + if (!hr24) { + if (hour > 11) + hour += 20 - 12; + if (hour == 0 || hour == 20) + hour += 12; + } + val.hr_ones = hour % 10; + val.hr_tens = hour / 10; + val.day_ones = t->tm_mday % 10; + val.day_tens = t->tm_mday / 10; + val.mon_ones = (t->tm_mon+1) % 10; + val.mon_tens = (t->tm_mon+1) / 10; + year = t->tm_year - 80; + val.year_ones = year % 10; + val.year_tens = year / 10; + val.weekday = t->tm_wday; + mste_write(&val); + mste_rtc.mode=(mste_rtc.mode | 1); + val.year_ones = (year % 4); /* leap year register */ + mste_rtc.mode=(mste_rtc.mode & ~1); + } + else { + mste_read(&val); + t->tm_sec = val.sec_ones + val.sec_tens * 10; + t->tm_min = val.min_ones + val.min_tens * 10; + hour = val.hr_ones + val.hr_tens * 10; + if (!hr24) { + if (hour == 12 || hour == 12 + 20) + hour -= 12; + if (hour >= 20) + hour += 12 - 20; + } + t->tm_hour = hour; + t->tm_mday = val.day_ones + val.day_tens * 10; + t->tm_mon = val.mon_ones + val.mon_tens * 10 - 1; + t->tm_year = val.year_ones + val.year_tens * 10 + 80; + t->tm_wday = val.weekday; + } + return 0; +} + +int atari_tt_hwclk( int op, struct rtc_time *t ) +{ + int sec=0, min=0, hour=0, day=0, mon=0, year=0, wday=0; + unsigned long flags; + unsigned char ctrl; + int pm = 0; + + ctrl = RTC_READ(RTC_CONTROL); /* control registers are + * independent from the UIP */ + + if (op) { + /* write: prepare values */ + + sec = t->tm_sec; + min = t->tm_min; + hour = t->tm_hour; + day = t->tm_mday; + mon = t->tm_mon + 1; + year = t->tm_year - atari_rtc_year_offset; + wday = t->tm_wday + (t->tm_wday >= 0); + + if (!(ctrl & RTC_24H)) { + if (hour > 11) { + pm = 0x80; + if (hour != 12) + hour -= 12; + } + else if (hour == 0) + hour = 12; + } + + if (!(ctrl & RTC_DM_BINARY)) { + sec = bin2bcd(sec); + min = bin2bcd(min); + hour = bin2bcd(hour); + day = bin2bcd(day); + mon = bin2bcd(mon); + year = bin2bcd(year); + if (wday >= 0) + wday = bin2bcd(wday); + } + } + + /* Reading/writing the clock registers is a bit critical due to + * the regular update cycle of the RTC. While an update is in + * progress, registers 0..9 shouldn't be touched. + * The problem is solved like that: If an update is currently in + * progress (the UIP bit is set), the process sleeps for a while + * (50ms). This really should be enough, since the update cycle + * normally needs 2 ms. + * If the UIP bit reads as 0, we have at least 244 usecs until the + * update starts. This should be enough... But to be sure, + * additionally the RTC_SET bit is set to prevent an update cycle. + */ + + while( RTC_READ(RTC_FREQ_SELECT) & RTC_UIP ) { + if (in_atomic() || irqs_disabled()) + mdelay(1); + else + schedule_timeout_interruptible(HWCLK_POLL_INTERVAL); + } + + local_irq_save(flags); + RTC_WRITE( RTC_CONTROL, ctrl | RTC_SET ); + if (!op) { + sec = RTC_READ( RTC_SECONDS ); + min = RTC_READ( RTC_MINUTES ); + hour = RTC_READ( RTC_HOURS ); + day = RTC_READ( RTC_DAY_OF_MONTH ); + mon = RTC_READ( RTC_MONTH ); + year = RTC_READ( RTC_YEAR ); + wday = RTC_READ( RTC_DAY_OF_WEEK ); + } + else { + RTC_WRITE( RTC_SECONDS, sec ); + RTC_WRITE( RTC_MINUTES, min ); + RTC_WRITE( RTC_HOURS, hour + pm); + RTC_WRITE( RTC_DAY_OF_MONTH, day ); + RTC_WRITE( RTC_MONTH, mon ); + RTC_WRITE( RTC_YEAR, year ); + if (wday >= 0) RTC_WRITE( RTC_DAY_OF_WEEK, wday ); + } + RTC_WRITE( RTC_CONTROL, ctrl & ~RTC_SET ); + local_irq_restore(flags); + + if (!op) { + /* read: adjust values */ + + if (hour & 0x80) { + hour &= ~0x80; + pm = 1; + } + + if (!(ctrl & RTC_DM_BINARY)) { + sec = bcd2bin(sec); + min = bcd2bin(min); + hour = bcd2bin(hour); + day = bcd2bin(day); + mon = bcd2bin(mon); + year = bcd2bin(year); + wday = bcd2bin(wday); + } + + if (!(ctrl & RTC_24H)) { + if (!pm && hour == 12) + hour = 0; + else if (pm && hour != 12) + hour += 12; + } + + t->tm_sec = sec; + t->tm_min = min; + t->tm_hour = hour; + t->tm_mday = day; + t->tm_mon = mon - 1; + t->tm_year = year + atari_rtc_year_offset; + t->tm_wday = wday - 1; + } + + return( 0 ); +} + +/* + * Local variables: + * c-indent-level: 4 + * tab-width: 8 + * End: + */ diff --git a/arch/m68k/bvme6000/Makefile b/arch/m68k/bvme6000/Makefile new file mode 100644 index 000000000..41bd4fad3 --- /dev/null +++ b/arch/m68k/bvme6000/Makefile @@ -0,0 +1,6 @@ +# SPDX-License-Identifier: GPL-2.0-only +# +# Makefile for Linux arch/m68k/bvme6000 source directory +# + +obj-y := config.o rtc.o diff --git a/arch/m68k/bvme6000/config.c b/arch/m68k/bvme6000/config.c new file mode 100644 index 000000000..50f4d0136 --- /dev/null +++ b/arch/m68k/bvme6000/config.c @@ -0,0 +1,327 @@ +/* + * arch/m68k/bvme6000/config.c + * + * Copyright (C) 1997 Richard Hirst [richard@sleepie.demon.co.uk] + * + * Based on: + * + * linux/amiga/config.c + * + * Copyright (C) 1993 Hamish Macdonald + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file README.legal in the main directory of this archive + * for more details. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include + +static void bvme6000_get_model(char *model); +extern void bvme6000_sched_init(irq_handler_t handler); +extern int bvme6000_hwclk (int, struct rtc_time *); +extern void bvme6000_reset (void); +void bvme6000_set_vectors (void); + + +int __init bvme6000_parse_bootinfo(const struct bi_record *bi) +{ + if (be16_to_cpu(bi->tag) == BI_VME_TYPE) + return 0; + else + return 1; +} + +void bvme6000_reset(void) +{ + volatile PitRegsPtr pit = (PitRegsPtr)BVME_PIT_BASE; + + pr_info("\r\n\nCalled bvme6000_reset\r\n" + "\r\r\r\r\r\r\r\r\r\r\r\r\r\r\r\r\r\r"); + /* The string of returns is to delay the reset until the whole + * message is output. */ + /* Enable the watchdog, via PIT port C bit 4 */ + + pit->pcddr |= 0x10; /* WDOG enable */ + + while(1) + ; +} + +static void bvme6000_get_model(char *model) +{ + sprintf(model, "BVME%d000", m68k_cputype == CPU_68060 ? 6 : 4); +} + +/* + * This function is called during kernel startup to initialize + * the bvme6000 IRQ handling routines. + */ +static void __init bvme6000_init_IRQ(void) +{ + m68k_setup_user_interrupt(VEC_USER, 192); +} + +void __init config_bvme6000(void) +{ + volatile PitRegsPtr pit = (PitRegsPtr)BVME_PIT_BASE; + + /* Board type is only set by newer versions of vmelilo/tftplilo */ + if (!vme_brdtype) { + if (m68k_cputype == CPU_68060) + vme_brdtype = VME_TYPE_BVME6000; + else + vme_brdtype = VME_TYPE_BVME4000; + } +#if 0 + /* Call bvme6000_set_vectors() so ABORT will work, along with BVMBug + * debugger. Note trap_init() will splat the abort vector, but + * bvme6000_init_IRQ() will put it back again. Hopefully. */ + + bvme6000_set_vectors(); +#endif + + mach_max_dma_address = 0xffffffff; + mach_sched_init = bvme6000_sched_init; + mach_init_IRQ = bvme6000_init_IRQ; + mach_hwclk = bvme6000_hwclk; + mach_reset = bvme6000_reset; + mach_get_model = bvme6000_get_model; + + pr_info("Board is %sconfigured as a System Controller\n", + *config_reg_ptr & BVME_CONFIG_SW1 ? "" : "not "); + + /* Now do the PIT configuration */ + + pit->pgcr = 0x00; /* Unidirectional 8 bit, no handshake for now */ + pit->psrr = 0x18; /* PIACK and PIRQ functions enabled */ + pit->pacr = 0x00; /* Sub Mode 00, H2 i/p, no DMA */ + pit->padr = 0x00; /* Just to be tidy! */ + pit->paddr = 0x00; /* All inputs for now (safest) */ + pit->pbcr = 0x80; /* Sub Mode 1x, H4 i/p, no DMA */ + pit->pbdr = 0xbc | (*config_reg_ptr & BVME_CONFIG_SW1 ? 0 : 0x40); + /* PRI, SYSCON?, Level3, SCC clks from xtal */ + pit->pbddr = 0xf3; /* Mostly outputs */ + pit->pcdr = 0x01; /* PA transceiver disabled */ + pit->pcddr = 0x03; /* WDOG disable */ + + /* Disable snooping for Ethernet and VME accesses */ + + bvme_acr_addrctl = 0; +} + + +irqreturn_t bvme6000_abort_int (int irq, void *dev_id) +{ + unsigned long *new = (unsigned long *)vectors; + unsigned long *old = (unsigned long *)0xf8000000; + + /* Wait for button release */ + while (*(volatile unsigned char *)BVME_LOCAL_IRQ_STAT & BVME_ABORT_STATUS) + ; + + *(new+4) = *(old+4); /* Illegal instruction */ + *(new+9) = *(old+9); /* Trace */ + *(new+47) = *(old+47); /* Trap #15 */ + *(new+0x1f) = *(old+0x1f); /* ABORT switch */ + return IRQ_HANDLED; +} + +static u64 bvme6000_read_clk(struct clocksource *cs); + +static struct clocksource bvme6000_clk = { + .name = "rtc", + .rating = 250, + .read = bvme6000_read_clk, + .mask = CLOCKSOURCE_MASK(32), + .flags = CLOCK_SOURCE_IS_CONTINUOUS, +}; + +static u32 clk_total, clk_offset; + +#define RTC_TIMER_CLOCK_FREQ 8000000 +#define RTC_TIMER_CYCLES (RTC_TIMER_CLOCK_FREQ / HZ) +#define RTC_TIMER_COUNT ((RTC_TIMER_CYCLES / 2) - 1) + +static irqreturn_t bvme6000_timer_int (int irq, void *dev_id) +{ + irq_handler_t timer_routine = dev_id; + unsigned long flags; + volatile RtcPtr_t rtc = (RtcPtr_t)BVME_RTC_BASE; + unsigned char msr; + + local_irq_save(flags); + msr = rtc->msr & 0xc0; + rtc->msr = msr | 0x20; /* Ack the interrupt */ + clk_total += RTC_TIMER_CYCLES; + clk_offset = 0; + timer_routine(0, NULL); + local_irq_restore(flags); + + return IRQ_HANDLED; +} + +/* + * Set up the RTC timer 1 to mode 2, so T1 output toggles every 5ms + * (40000 x 125ns). It will interrupt every 10ms, when T1 goes low. + * So, when reading the elapsed time, you should read timer1, + * subtract it from 39999, and then add 40000 if T1 is high. + * That gives you the number of 125ns ticks in to the 10ms period, + * so divide by 8 to get the microsecond result. + */ + +void bvme6000_sched_init (irq_handler_t timer_routine) +{ + volatile RtcPtr_t rtc = (RtcPtr_t)BVME_RTC_BASE; + unsigned char msr = rtc->msr & 0xc0; + + rtc->msr = 0; /* Ensure timer registers accessible */ + + if (request_irq(BVME_IRQ_RTC, bvme6000_timer_int, IRQF_TIMER, "timer", + timer_routine)) + panic ("Couldn't register timer int"); + + rtc->t1cr_omr = 0x04; /* Mode 2, ext clk */ + rtc->t1msb = RTC_TIMER_COUNT >> 8; + rtc->t1lsb = RTC_TIMER_COUNT & 0xff; + rtc->irr_icr1 &= 0xef; /* Route timer 1 to INTR pin */ + rtc->msr = 0x40; /* Access int.cntrl, etc */ + rtc->pfr_icr0 = 0x80; /* Just timer 1 ints enabled */ + rtc->irr_icr1 = 0; + rtc->t1cr_omr = 0x0a; /* INTR+T1 active lo, push-pull */ + rtc->t0cr_rtmr &= 0xdf; /* Stop timers in standby */ + rtc->msr = 0; /* Access timer 1 control */ + rtc->t1cr_omr = 0x05; /* Mode 2, ext clk, GO */ + + rtc->msr = msr; + + clocksource_register_hz(&bvme6000_clk, RTC_TIMER_CLOCK_FREQ); + + if (request_irq(BVME_IRQ_ABORT, bvme6000_abort_int, 0, + "abort", bvme6000_abort_int)) + panic ("Couldn't register abort int"); +} + + +/* + * NOTE: Don't accept any readings within 5us of rollover, as + * the T1INT bit may be a little slow getting set. There is also + * a fault in the chip, meaning that reads may produce invalid + * results... + */ + +static u64 bvme6000_read_clk(struct clocksource *cs) +{ + unsigned long flags; + volatile RtcPtr_t rtc = (RtcPtr_t)BVME_RTC_BASE; + volatile PitRegsPtr pit = (PitRegsPtr)BVME_PIT_BASE; + unsigned char msr, msb; + unsigned char t1int, t1op; + u32 v = 800000, ov; + + local_irq_save(flags); + + msr = rtc->msr & 0xc0; + rtc->msr = 0; /* Ensure timer registers accessible */ + + do { + ov = v; + t1int = rtc->msr & 0x20; + t1op = pit->pcdr & 0x04; + rtc->t1cr_omr |= 0x40; /* Latch timer1 */ + msb = rtc->t1msb; /* Read timer1 */ + v = (msb << 8) | rtc->t1lsb; /* Read timer1 */ + } while (t1int != (rtc->msr & 0x20) || + t1op != (pit->pcdr & 0x04) || + abs(ov-v) > 80 || + v > RTC_TIMER_COUNT - (RTC_TIMER_COUNT / 100)); + + v = RTC_TIMER_COUNT - v; + if (!t1op) /* If in second half cycle.. */ + v += RTC_TIMER_CYCLES / 2; + if (msb > 0 && t1int) + clk_offset = RTC_TIMER_CYCLES; + rtc->msr = msr; + + v += clk_offset + clk_total; + + local_irq_restore(flags); + + return v; +} + +/* + * Looks like op is non-zero for setting the clock, and zero for + * reading the clock. + * + * struct hwclk_time { + * unsigned sec; 0..59 + * unsigned min; 0..59 + * unsigned hour; 0..23 + * unsigned day; 1..31 + * unsigned mon; 0..11 + * unsigned year; 00... + * int wday; 0..6, 0 is Sunday, -1 means unknown/don't set + * }; + */ + +int bvme6000_hwclk(int op, struct rtc_time *t) +{ + volatile RtcPtr_t rtc = (RtcPtr_t)BVME_RTC_BASE; + unsigned char msr = rtc->msr & 0xc0; + + rtc->msr = 0x40; /* Ensure clock and real-time-mode-register + * are accessible */ + if (op) + { /* Write.... */ + rtc->t0cr_rtmr = t->tm_year%4; + rtc->bcd_tenms = 0; + rtc->bcd_sec = bin2bcd(t->tm_sec); + rtc->bcd_min = bin2bcd(t->tm_min); + rtc->bcd_hr = bin2bcd(t->tm_hour); + rtc->bcd_dom = bin2bcd(t->tm_mday); + rtc->bcd_mth = bin2bcd(t->tm_mon + 1); + rtc->bcd_year = bin2bcd(t->tm_year%100); + if (t->tm_wday >= 0) + rtc->bcd_dow = bin2bcd(t->tm_wday+1); + rtc->t0cr_rtmr = t->tm_year%4 | 0x08; + } + else + { /* Read.... */ + do { + t->tm_sec = bcd2bin(rtc->bcd_sec); + t->tm_min = bcd2bin(rtc->bcd_min); + t->tm_hour = bcd2bin(rtc->bcd_hr); + t->tm_mday = bcd2bin(rtc->bcd_dom); + t->tm_mon = bcd2bin(rtc->bcd_mth)-1; + t->tm_year = bcd2bin(rtc->bcd_year); + if (t->tm_year < 70) + t->tm_year += 100; + t->tm_wday = bcd2bin(rtc->bcd_dow)-1; + } while (t->tm_sec != bcd2bin(rtc->bcd_sec)); + } + + rtc->msr = msr; + + return 0; +} diff --git a/arch/m68k/bvme6000/rtc.c b/arch/m68k/bvme6000/rtc.c new file mode 100644 index 000000000..b43eeef09 --- /dev/null +++ b/arch/m68k/bvme6000/rtc.c @@ -0,0 +1,175 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Real Time Clock interface for Linux on the BVME6000 + * + * Based on the PC driver by Paul Gortmaker. + */ + +#define RTC_VERSION "1.00" + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include /* For struct rtc_time and ioctls, etc */ +#include +#include + +#include +#include +#include + +/* + * We sponge a minor off of the misc major. No need slurping + * up another valuable major dev number for this. If you add + * an ioctl, make sure you don't conflict with SPARC's RTC + * ioctls. + */ + +static unsigned char days_in_mo[] = +{0, 31, 28, 31, 30, 31, 30, 31, 31, 30, 31, 30, 31}; + +static atomic_t rtc_status = ATOMIC_INIT(1); + +static long rtc_ioctl(struct file *file, unsigned int cmd, unsigned long arg) +{ + volatile RtcPtr_t rtc = (RtcPtr_t)BVME_RTC_BASE; + unsigned char msr; + unsigned long flags; + struct rtc_time wtime; + void __user *argp = (void __user *)arg; + + switch (cmd) { + case RTC_RD_TIME: /* Read the time/date from RTC */ + { + local_irq_save(flags); + /* Ensure clock and real-time-mode-register are accessible */ + msr = rtc->msr & 0xc0; + rtc->msr = 0x40; + memset(&wtime, 0, sizeof(struct rtc_time)); + do { + wtime.tm_sec = bcd2bin(rtc->bcd_sec); + wtime.tm_min = bcd2bin(rtc->bcd_min); + wtime.tm_hour = bcd2bin(rtc->bcd_hr); + wtime.tm_mday = bcd2bin(rtc->bcd_dom); + wtime.tm_mon = bcd2bin(rtc->bcd_mth)-1; + wtime.tm_year = bcd2bin(rtc->bcd_year); + if (wtime.tm_year < 70) + wtime.tm_year += 100; + wtime.tm_wday = bcd2bin(rtc->bcd_dow)-1; + } while (wtime.tm_sec != bcd2bin(rtc->bcd_sec)); + rtc->msr = msr; + local_irq_restore(flags); + return copy_to_user(argp, &wtime, sizeof wtime) ? + -EFAULT : 0; + } + case RTC_SET_TIME: /* Set the RTC */ + { + struct rtc_time rtc_tm; + unsigned char mon, day, hrs, min, sec, leap_yr; + unsigned int yrs; + + if (!capable(CAP_SYS_ADMIN)) + return -EACCES; + + if (copy_from_user(&rtc_tm, argp, sizeof(struct rtc_time))) + return -EFAULT; + + yrs = rtc_tm.tm_year; + if (yrs < 1900) + yrs += 1900; + mon = rtc_tm.tm_mon + 1; /* tm_mon starts at zero */ + day = rtc_tm.tm_mday; + hrs = rtc_tm.tm_hour; + min = rtc_tm.tm_min; + sec = rtc_tm.tm_sec; + + leap_yr = ((!(yrs % 4) && (yrs % 100)) || !(yrs % 400)); + + if ((mon > 12) || (mon < 1) || (day == 0)) + return -EINVAL; + + if (day > (days_in_mo[mon] + ((mon == 2) && leap_yr))) + return -EINVAL; + + if ((hrs >= 24) || (min >= 60) || (sec >= 60)) + return -EINVAL; + + if (yrs >= 2070) + return -EINVAL; + + local_irq_save(flags); + /* Ensure clock and real-time-mode-register are accessible */ + msr = rtc->msr & 0xc0; + rtc->msr = 0x40; + + rtc->t0cr_rtmr = yrs%4; + rtc->bcd_tenms = 0; + rtc->bcd_sec = bin2bcd(sec); + rtc->bcd_min = bin2bcd(min); + rtc->bcd_hr = bin2bcd(hrs); + rtc->bcd_dom = bin2bcd(day); + rtc->bcd_mth = bin2bcd(mon); + rtc->bcd_year = bin2bcd(yrs%100); + if (rtc_tm.tm_wday >= 0) + rtc->bcd_dow = bin2bcd(rtc_tm.tm_wday+1); + rtc->t0cr_rtmr = yrs%4 | 0x08; + + rtc->msr = msr; + local_irq_restore(flags); + return 0; + } + default: + return -EINVAL; + } +} + +/* + * We enforce only one user at a time here with the open/close. + */ +static int rtc_open(struct inode *inode, struct file *file) +{ + if (!atomic_dec_and_test(&rtc_status)) { + atomic_inc(&rtc_status); + return -EBUSY; + } + return 0; +} + +static int rtc_release(struct inode *inode, struct file *file) +{ + atomic_inc(&rtc_status); + return 0; +} + +/* + * The various file operations we support. + */ + +static const struct file_operations rtc_fops = { + .unlocked_ioctl = rtc_ioctl, + .open = rtc_open, + .release = rtc_release, + .llseek = noop_llseek, +}; + +static struct miscdevice rtc_dev = { + .minor = RTC_MINOR, + .name = "rtc", + .fops = &rtc_fops +}; + +static int __init rtc_DP8570A_init(void) +{ + if (!MACH_IS_BVME6000) + return -ENODEV; + + pr_info("DP8570A Real Time Clock Driver v%s\n", RTC_VERSION); + return misc_register(&rtc_dev); +} +module_init(rtc_DP8570A_init); diff --git a/arch/m68k/coldfire/Makefile b/arch/m68k/coldfire/Makefile new file mode 100644 index 000000000..573eabca1 --- /dev/null +++ b/arch/m68k/coldfire/Makefile @@ -0,0 +1,44 @@ +# SPDX-License-Identifier: GPL-2.0 +# +# Makefile for the m68knommu kernel. +# + +# +# If you want to play with the HW breakpoints then you will +# need to add define this, which will give you a stack backtrace +# on the console port whenever a DBG interrupt occurs. You have to +# set up you HW breakpoints to trigger a DBG interrupt: +# +# ccflags-y := -DTRAP_DBG_INTERRUPT +# asflags-y := -DTRAP_DBG_INTERRUPT +# + +asflags-$(CONFIG_FULLDEBUG) := -DDEBUGGER_COMPATIBLE_CACHE=1 + +obj-$(CONFIG_COLDFIRE) += cache.o clk.o device.o dma.o entry.o vectors.o +obj-$(CONFIG_M5206) += m5206.o timers.o intc.o reset.o +obj-$(CONFIG_M5206e) += m5206.o timers.o intc.o reset.o +obj-$(CONFIG_M520x) += m520x.o pit.o intc-simr.o reset.o +obj-$(CONFIG_M523x) += m523x.o pit.o dma_timer.o intc-2.o reset.o +obj-$(CONFIG_M5249) += m5249.o timers.o intc.o intc-5249.o reset.o +obj-$(CONFIG_M525x) += m525x.o timers.o intc.o intc-525x.o reset.o +obj-$(CONFIG_M527x) += m527x.o pit.o intc-2.o reset.o +obj-$(CONFIG_M5272) += m5272.o intc-5272.o timers.o +obj-$(CONFIG_M528x) += m528x.o pit.o intc-2.o reset.o +obj-$(CONFIG_M5307) += m5307.o timers.o intc.o reset.o +obj-$(CONFIG_M53xx) += m53xx.o timers.o intc-simr.o reset.o +obj-$(CONFIG_M5407) += m5407.o timers.o intc.o reset.o +obj-$(CONFIG_M54xx) += m54xx.o sltimers.o intc-2.o +obj-$(CONFIG_M5441x) += m5441x.o pit.o intc-simr.o reset.o + +obj-$(CONFIG_NETtel) += nettel.o +obj-$(CONFIG_CLEOPATRA) += nettel.o +obj-$(CONFIG_FIREBEE) += firebee.o +obj-$(CONFIG_MCF8390) += mcf8390.o +obj-$(CONFIG_AMCORE) += amcore.o +obj-$(CONFIG_STMARK2) += stmark2.o + +obj-$(CONFIG_PCI) += pci.o + +obj-y += gpio.o +extra-y := head.o diff --git a/arch/m68k/coldfire/amcore.c b/arch/m68k/coldfire/amcore.c new file mode 100644 index 000000000..c6cb1a5cc --- /dev/null +++ b/arch/m68k/coldfire/amcore.c @@ -0,0 +1,156 @@ +/* + * amcore.c -- Support for Sysam AMCORE open board + * + * (C) Copyright 2016, Angelo Dureghello + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file COPYING in the main directory of this archive + * for more details. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +#if IS_ENABLED(CONFIG_DM9000) + +#define DM9000_IRQ 25 +#define DM9000_ADDR 0x30000000 + +/* + * DEVICES and related device RESOURCES + */ +static struct resource dm9000_resources[] = { + /* physical address of the address register (CMD [A2] to 0)*/ + [0] = { + .start = DM9000_ADDR, + .end = DM9000_ADDR, + .flags = IORESOURCE_MEM, + }, + /* + * physical address of the data register (CMD [A2] to 1), + * driver wants a range >=4 to assume a 32bit data bus + */ + [1] = { + .start = DM9000_ADDR + 4, + .end = DM9000_ADDR + 7, + .flags = IORESOURCE_MEM, + }, + /* IRQ line the device's interrupt pin is connected to */ + [2] = { + .start = DM9000_IRQ, + .end = DM9000_IRQ, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct dm9000_plat_data dm9000_platdata = { + .flags = DM9000_PLATF_32BITONLY, +}; + +static struct platform_device dm9000_device = { + .name = "dm9000", + .id = 0, + .num_resources = ARRAY_SIZE(dm9000_resources), + .resource = dm9000_resources, + .dev = { + .platform_data = &dm9000_platdata, + } +}; +#endif + +static void __init dm9000_pre_init(void) +{ + /* Set the dm9000 interrupt to be auto-vectored */ + mcf_autovector(DM9000_IRQ); +} + +/* + * Partitioning of parallel NOR flash (39VF3201B) + */ +static struct mtd_partition amcore_partitions[] = { + { + .name = "U-Boot (128K)", + .size = 0x20000, + .offset = 0x0 + }, + { + .name = "Kernel+ROMfs (2994K)", + .size = 0x2E0000, + .offset = MTDPART_OFS_APPEND + }, + { + .name = "Flash Free Space (1024K)", + .size = MTDPART_SIZ_FULL, + .offset = MTDPART_OFS_APPEND + } +}; + +static struct physmap_flash_data flash_data = { + .parts = amcore_partitions, + .nr_parts = ARRAY_SIZE(amcore_partitions), + .width = 2, +}; + +static struct resource flash_resource = { + .start = 0xffc00000, + .end = 0xffffffff, + .flags = IORESOURCE_MEM, +}; + +static struct platform_device flash_device = { + .name = "physmap-flash", + .id = -1, + .resource = &flash_resource, + .num_resources = 1, + .dev = { + .platform_data = &flash_data, + }, +}; + +static struct platform_device rtc_device = { + .name = "rtc-ds1307", + .id = -1, +}; + +static struct i2c_board_info amcore_i2c_info[] __initdata = { + { + I2C_BOARD_INFO("ds1338", 0x68), + }, +}; + +static struct platform_device *amcore_devices[] __initdata = { +#if IS_ENABLED(CONFIG_DM9000) + &dm9000_device, +#endif + &flash_device, + &rtc_device, +}; + +static int __init init_amcore(void) +{ +#if IS_ENABLED(CONFIG_DM9000) + dm9000_pre_init(); +#endif + + /* Add i2c RTC Dallas chip supprt */ + i2c_register_board_info(0, amcore_i2c_info, + ARRAY_SIZE(amcore_i2c_info)); + + platform_add_devices(amcore_devices, ARRAY_SIZE(amcore_devices)); + + return 0; +} + +arch_initcall(init_amcore); diff --git a/arch/m68k/coldfire/cache.c b/arch/m68k/coldfire/cache.c new file mode 100644 index 000000000..98ee89b87 --- /dev/null +++ b/arch/m68k/coldfire/cache.c @@ -0,0 +1,49 @@ +// SPDX-License-Identifier: GPL-2.0 +/***************************************************************************/ + +/* + * cache.c -- general ColdFire Cache maintenance code + * + * Copyright (C) 2010, Greg Ungerer (gerg@snapgear.com) + */ + +/***************************************************************************/ + +#include +#include +#include + +/***************************************************************************/ +#ifdef CACHE_PUSH +/***************************************************************************/ + +/* + * Use cpushl to push all dirty cache lines back to memory. + * Older versions of GAS don't seem to know how to generate the + * ColdFire cpushl instruction... Oh well, bit stuff it for now. + */ + +void mcf_cache_push(void) +{ + __asm__ __volatile__ ( + "clrl %%d0\n\t" + "1:\n\t" + "movel %%d0,%%a0\n\t" + "2:\n\t" + ".word 0xf468\n\t" + "addl %0,%%a0\n\t" + "cmpl %1,%%a0\n\t" + "blt 2b\n\t" + "addql #1,%%d0\n\t" + "cmpil %2,%%d0\n\t" + "bne 1b\n\t" + : /* No output */ + : "i" (CACHE_LINE_SIZE), + "i" (DCACHE_SIZE / CACHE_WAYS), + "i" (CACHE_WAYS) + : "d0", "a0" ); +} + +/***************************************************************************/ +#endif /* CACHE_PUSH */ +/***************************************************************************/ diff --git a/arch/m68k/coldfire/clk.c b/arch/m68k/coldfire/clk.c new file mode 100644 index 000000000..7bc666e48 --- /dev/null +++ b/arch/m68k/coldfire/clk.c @@ -0,0 +1,161 @@ +// SPDX-License-Identifier: GPL-2.0 +/***************************************************************************/ + +/* + * clk.c -- general ColdFire CPU kernel clk handling + * + * Copyright (C) 2009, Greg Ungerer (gerg@snapgear.com) + */ + +/***************************************************************************/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +static DEFINE_SPINLOCK(clk_lock); + +#ifdef MCFPM_PPMCR0 +/* + * For more advanced ColdFire parts that have clocks that can be enabled + * we supply enable/disable functions. These must properly define their + * clocks in their platform specific code. + */ +void __clk_init_enabled(struct clk *clk) +{ + clk->enabled = 1; + clk->clk_ops->enable(clk); +} + +void __clk_init_disabled(struct clk *clk) +{ + clk->enabled = 0; + clk->clk_ops->disable(clk); +} + +static void __clk_enable0(struct clk *clk) +{ + __raw_writeb(clk->slot, MCFPM_PPMCR0); +} + +static void __clk_disable0(struct clk *clk) +{ + __raw_writeb(clk->slot, MCFPM_PPMSR0); +} + +struct clk_ops clk_ops0 = { + .enable = __clk_enable0, + .disable = __clk_disable0, +}; + +#ifdef MCFPM_PPMCR1 +static void __clk_enable1(struct clk *clk) +{ + __raw_writeb(clk->slot, MCFPM_PPMCR1); +} + +static void __clk_disable1(struct clk *clk) +{ + __raw_writeb(clk->slot, MCFPM_PPMSR1); +} + +struct clk_ops clk_ops1 = { + .enable = __clk_enable1, + .disable = __clk_disable1, +}; +#endif /* MCFPM_PPMCR1 */ +#endif /* MCFPM_PPMCR0 */ + +struct clk *clk_get(struct device *dev, const char *id) +{ + const char *clk_name = dev ? dev_name(dev) : id ? id : NULL; + struct clk *clk; + unsigned i; + + for (i = 0; (clk = mcf_clks[i]) != NULL; ++i) + if (!strcmp(clk->name, clk_name)) + return clk; + pr_warn("clk_get: didn't find clock %s\n", clk_name); + return ERR_PTR(-ENOENT); +} +EXPORT_SYMBOL(clk_get); + +int clk_enable(struct clk *clk) +{ + unsigned long flags; + spin_lock_irqsave(&clk_lock, flags); + if ((clk->enabled++ == 0) && clk->clk_ops) + clk->clk_ops->enable(clk); + spin_unlock_irqrestore(&clk_lock, flags); + + return 0; +} +EXPORT_SYMBOL(clk_enable); + +void clk_disable(struct clk *clk) +{ + unsigned long flags; + + if (!clk) + return; + + spin_lock_irqsave(&clk_lock, flags); + if ((--clk->enabled == 0) && clk->clk_ops) + clk->clk_ops->disable(clk); + spin_unlock_irqrestore(&clk_lock, flags); +} +EXPORT_SYMBOL(clk_disable); + +void clk_put(struct clk *clk) +{ + if (clk->enabled != 0) + pr_warn("clk_put %s still enabled\n", clk->name); +} +EXPORT_SYMBOL(clk_put); + +unsigned long clk_get_rate(struct clk *clk) +{ + if (!clk) + return 0; + + return clk->rate; +} +EXPORT_SYMBOL(clk_get_rate); + +/* dummy functions, should not be called */ +long clk_round_rate(struct clk *clk, unsigned long rate) +{ + WARN_ON(clk); + return 0; +} +EXPORT_SYMBOL(clk_round_rate); + +int clk_set_rate(struct clk *clk, unsigned long rate) +{ + WARN_ON(clk); + return 0; +} +EXPORT_SYMBOL(clk_set_rate); + +int clk_set_parent(struct clk *clk, struct clk *parent) +{ + WARN_ON(clk); + return 0; +} +EXPORT_SYMBOL(clk_set_parent); + +struct clk *clk_get_parent(struct clk *clk) +{ + WARN_ON(clk); + return NULL; +} +EXPORT_SYMBOL(clk_get_parent); + +/***************************************************************************/ diff --git a/arch/m68k/coldfire/device.c b/arch/m68k/coldfire/device.c new file mode 100644 index 000000000..a05561694 --- /dev/null +++ b/arch/m68k/coldfire/device.c @@ -0,0 +1,646 @@ +/* + * device.c -- common ColdFire SoC device support + * + * (C) Copyright 2011, Greg Ungerer + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file COPYING in the main directory of this archive + * for more details. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* + * All current ColdFire parts contain from 2, 3, 4 or 10 UARTS. + */ +static struct mcf_platform_uart mcf_uart_platform_data[] = { + { + .mapbase = MCFUART_BASE0, + .irq = MCF_IRQ_UART0, + }, + { + .mapbase = MCFUART_BASE1, + .irq = MCF_IRQ_UART1, + }, +#ifdef MCFUART_BASE2 + { + .mapbase = MCFUART_BASE2, + .irq = MCF_IRQ_UART2, + }, +#endif +#ifdef MCFUART_BASE3 + { + .mapbase = MCFUART_BASE3, + .irq = MCF_IRQ_UART3, + }, +#endif +#ifdef MCFUART_BASE4 + { + .mapbase = MCFUART_BASE4, + .irq = MCF_IRQ_UART4, + }, +#endif +#ifdef MCFUART_BASE5 + { + .mapbase = MCFUART_BASE5, + .irq = MCF_IRQ_UART5, + }, +#endif +#ifdef MCFUART_BASE6 + { + .mapbase = MCFUART_BASE6, + .irq = MCF_IRQ_UART6, + }, +#endif +#ifdef MCFUART_BASE7 + { + .mapbase = MCFUART_BASE7, + .irq = MCF_IRQ_UART7, + }, +#endif +#ifdef MCFUART_BASE8 + { + .mapbase = MCFUART_BASE8, + .irq = MCF_IRQ_UART8, + }, +#endif +#ifdef MCFUART_BASE9 + { + .mapbase = MCFUART_BASE9, + .irq = MCF_IRQ_UART9, + }, +#endif + { }, +}; + +static struct platform_device mcf_uart = { + .name = "mcfuart", + .id = 0, + .dev.platform_data = mcf_uart_platform_data, +}; + +#if IS_ENABLED(CONFIG_FEC) + +#ifdef CONFIG_M5441x +#define FEC_NAME "enet-fec" +static struct fec_platform_data fec_pdata = { + .phy = PHY_INTERFACE_MODE_RMII, +}; +#define FEC_PDATA (&fec_pdata) +#else +#define FEC_NAME "fec" +#define FEC_PDATA NULL +#endif + +/* + * Some ColdFire cores contain the Fast Ethernet Controller (FEC) + * block. It is Freescale's own hardware block. Some ColdFires + * have 2 of these. + */ +static struct resource mcf_fec0_resources[] = { + { + .start = MCFFEC_BASE0, + .end = MCFFEC_BASE0 + MCFFEC_SIZE0 - 1, + .flags = IORESOURCE_MEM, + }, + { + .start = MCF_IRQ_FECRX0, + .end = MCF_IRQ_FECRX0, + .flags = IORESOURCE_IRQ, + }, + { + .start = MCF_IRQ_FECTX0, + .end = MCF_IRQ_FECTX0, + .flags = IORESOURCE_IRQ, + }, + { + .start = MCF_IRQ_FECENTC0, + .end = MCF_IRQ_FECENTC0, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device mcf_fec0 = { + .name = FEC_NAME, + .id = 0, + .num_resources = ARRAY_SIZE(mcf_fec0_resources), + .resource = mcf_fec0_resources, + .dev = { + .dma_mask = &mcf_fec0.dev.coherent_dma_mask, + .coherent_dma_mask = DMA_BIT_MASK(32), + .platform_data = FEC_PDATA, + } +}; + +#ifdef MCFFEC_BASE1 +static struct resource mcf_fec1_resources[] = { + { + .start = MCFFEC_BASE1, + .end = MCFFEC_BASE1 + MCFFEC_SIZE1 - 1, + .flags = IORESOURCE_MEM, + }, + { + .start = MCF_IRQ_FECRX1, + .end = MCF_IRQ_FECRX1, + .flags = IORESOURCE_IRQ, + }, + { + .start = MCF_IRQ_FECTX1, + .end = MCF_IRQ_FECTX1, + .flags = IORESOURCE_IRQ, + }, + { + .start = MCF_IRQ_FECENTC1, + .end = MCF_IRQ_FECENTC1, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device mcf_fec1 = { + .name = FEC_NAME, + .id = 1, + .num_resources = ARRAY_SIZE(mcf_fec1_resources), + .resource = mcf_fec1_resources, + .dev = { + .dma_mask = &mcf_fec1.dev.coherent_dma_mask, + .coherent_dma_mask = DMA_BIT_MASK(32), + .platform_data = FEC_PDATA, + } +}; +#endif /* MCFFEC_BASE1 */ +#endif /* CONFIG_FEC */ + +#if IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI) +/* + * The ColdFire QSPI module is an SPI protocol hardware block used + * on a number of different ColdFire CPUs. + */ +static struct resource mcf_qspi_resources[] = { + { + .start = MCFQSPI_BASE, + .end = MCFQSPI_BASE + MCFQSPI_SIZE - 1, + .flags = IORESOURCE_MEM, + }, + { + .start = MCF_IRQ_QSPI, + .end = MCF_IRQ_QSPI, + .flags = IORESOURCE_IRQ, + }, +}; + +static int mcf_cs_setup(struct mcfqspi_cs_control *cs_control) +{ + int status; + + status = gpio_request(MCFQSPI_CS0, "MCFQSPI_CS0"); + if (status) { + pr_debug("gpio_request for MCFQSPI_CS0 failed\n"); + goto fail0; + } + status = gpio_direction_output(MCFQSPI_CS0, 1); + if (status) { + pr_debug("gpio_direction_output for MCFQSPI_CS0 failed\n"); + goto fail1; + } + + status = gpio_request(MCFQSPI_CS1, "MCFQSPI_CS1"); + if (status) { + pr_debug("gpio_request for MCFQSPI_CS1 failed\n"); + goto fail1; + } + status = gpio_direction_output(MCFQSPI_CS1, 1); + if (status) { + pr_debug("gpio_direction_output for MCFQSPI_CS1 failed\n"); + goto fail2; + } + + status = gpio_request(MCFQSPI_CS2, "MCFQSPI_CS2"); + if (status) { + pr_debug("gpio_request for MCFQSPI_CS2 failed\n"); + goto fail2; + } + status = gpio_direction_output(MCFQSPI_CS2, 1); + if (status) { + pr_debug("gpio_direction_output for MCFQSPI_CS2 failed\n"); + goto fail3; + } + +#ifdef MCFQSPI_CS3 + status = gpio_request(MCFQSPI_CS3, "MCFQSPI_CS3"); + if (status) { + pr_debug("gpio_request for MCFQSPI_CS3 failed\n"); + goto fail3; + } + status = gpio_direction_output(MCFQSPI_CS3, 1); + if (status) { + pr_debug("gpio_direction_output for MCFQSPI_CS3 failed\n"); + gpio_free(MCFQSPI_CS3); + goto fail3; + } +#endif + + return 0; + +fail3: + gpio_free(MCFQSPI_CS2); +fail2: + gpio_free(MCFQSPI_CS1); +fail1: + gpio_free(MCFQSPI_CS0); +fail0: + return status; +} + +static void mcf_cs_teardown(struct mcfqspi_cs_control *cs_control) +{ +#ifdef MCFQSPI_CS3 + gpio_free(MCFQSPI_CS3); +#endif + gpio_free(MCFQSPI_CS2); + gpio_free(MCFQSPI_CS1); + gpio_free(MCFQSPI_CS0); +} + +static void mcf_cs_select(struct mcfqspi_cs_control *cs_control, + u8 chip_select, bool cs_high) +{ + switch (chip_select) { + case 0: + gpio_set_value(MCFQSPI_CS0, cs_high); + break; + case 1: + gpio_set_value(MCFQSPI_CS1, cs_high); + break; + case 2: + gpio_set_value(MCFQSPI_CS2, cs_high); + break; +#ifdef MCFQSPI_CS3 + case 3: + gpio_set_value(MCFQSPI_CS3, cs_high); + break; +#endif + } +} + +static void mcf_cs_deselect(struct mcfqspi_cs_control *cs_control, + u8 chip_select, bool cs_high) +{ + switch (chip_select) { + case 0: + gpio_set_value(MCFQSPI_CS0, !cs_high); + break; + case 1: + gpio_set_value(MCFQSPI_CS1, !cs_high); + break; + case 2: + gpio_set_value(MCFQSPI_CS2, !cs_high); + break; +#ifdef MCFQSPI_CS3 + case 3: + gpio_set_value(MCFQSPI_CS3, !cs_high); + break; +#endif + } +} + +static struct mcfqspi_cs_control mcf_cs_control = { + .setup = mcf_cs_setup, + .teardown = mcf_cs_teardown, + .select = mcf_cs_select, + .deselect = mcf_cs_deselect, +}; + +static struct mcfqspi_platform_data mcf_qspi_data = { + .bus_num = 0, + .num_chipselect = 4, + .cs_control = &mcf_cs_control, +}; + +static struct platform_device mcf_qspi = { + .name = "mcfqspi", + .id = 0, + .num_resources = ARRAY_SIZE(mcf_qspi_resources), + .resource = mcf_qspi_resources, + .dev.platform_data = &mcf_qspi_data, +}; +#endif /* IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI) */ + +#if IS_ENABLED(CONFIG_I2C_IMX) +static struct resource mcf_i2c0_resources[] = { + { + .start = MCFI2C_BASE0, + .end = MCFI2C_BASE0 + MCFI2C_SIZE0 - 1, + .flags = IORESOURCE_MEM, + }, + { + .start = MCF_IRQ_I2C0, + .end = MCF_IRQ_I2C0, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device mcf_i2c0 = { + .name = "imx1-i2c", + .id = 0, + .num_resources = ARRAY_SIZE(mcf_i2c0_resources), + .resource = mcf_i2c0_resources, +}; +#ifdef MCFI2C_BASE1 + +static struct resource mcf_i2c1_resources[] = { + { + .start = MCFI2C_BASE1, + .end = MCFI2C_BASE1 + MCFI2C_SIZE1 - 1, + .flags = IORESOURCE_MEM, + }, + { + .start = MCF_IRQ_I2C1, + .end = MCF_IRQ_I2C1, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device mcf_i2c1 = { + .name = "imx1-i2c", + .id = 1, + .num_resources = ARRAY_SIZE(mcf_i2c1_resources), + .resource = mcf_i2c1_resources, +}; + +#endif /* MCFI2C_BASE1 */ + +#ifdef MCFI2C_BASE2 + +static struct resource mcf_i2c2_resources[] = { + { + .start = MCFI2C_BASE2, + .end = MCFI2C_BASE2 + MCFI2C_SIZE2 - 1, + .flags = IORESOURCE_MEM, + }, + { + .start = MCF_IRQ_I2C2, + .end = MCF_IRQ_I2C2, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device mcf_i2c2 = { + .name = "imx1-i2c", + .id = 2, + .num_resources = ARRAY_SIZE(mcf_i2c2_resources), + .resource = mcf_i2c2_resources, +}; + +#endif /* MCFI2C_BASE2 */ + +#ifdef MCFI2C_BASE3 + +static struct resource mcf_i2c3_resources[] = { + { + .start = MCFI2C_BASE3, + .end = MCFI2C_BASE3 + MCFI2C_SIZE3 - 1, + .flags = IORESOURCE_MEM, + }, + { + .start = MCF_IRQ_I2C3, + .end = MCF_IRQ_I2C3, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device mcf_i2c3 = { + .name = "imx1-i2c", + .id = 3, + .num_resources = ARRAY_SIZE(mcf_i2c3_resources), + .resource = mcf_i2c3_resources, +}; + +#endif /* MCFI2C_BASE3 */ + +#ifdef MCFI2C_BASE4 + +static struct resource mcf_i2c4_resources[] = { + { + .start = MCFI2C_BASE4, + .end = MCFI2C_BASE4 + MCFI2C_SIZE4 - 1, + .flags = IORESOURCE_MEM, + }, + { + .start = MCF_IRQ_I2C4, + .end = MCF_IRQ_I2C4, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device mcf_i2c4 = { + .name = "imx1-i2c", + .id = 4, + .num_resources = ARRAY_SIZE(mcf_i2c4_resources), + .resource = mcf_i2c4_resources, +}; + +#endif /* MCFI2C_BASE4 */ + +#ifdef MCFI2C_BASE5 + +static struct resource mcf_i2c5_resources[] = { + { + .start = MCFI2C_BASE5, + .end = MCFI2C_BASE5 + MCFI2C_SIZE5 - 1, + .flags = IORESOURCE_MEM, + }, + { + .start = MCF_IRQ_I2C5, + .end = MCF_IRQ_I2C5, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device mcf_i2c5 = { + .name = "imx1-i2c", + .id = 5, + .num_resources = ARRAY_SIZE(mcf_i2c5_resources), + .resource = mcf_i2c5_resources, +}; + +#endif /* MCFI2C_BASE5 */ +#endif /* IS_ENABLED(CONFIG_I2C_IMX) */ + +#ifdef MCFEDMA_BASE + +static const struct dma_slave_map mcf_edma_map[] = { + { "dreq0", "rx-tx", MCF_EDMA_FILTER_PARAM(0) }, + { "dreq1", "rx-tx", MCF_EDMA_FILTER_PARAM(1) }, + { "uart.0", "rx", MCF_EDMA_FILTER_PARAM(2) }, + { "uart.0", "tx", MCF_EDMA_FILTER_PARAM(3) }, + { "uart.1", "rx", MCF_EDMA_FILTER_PARAM(4) }, + { "uart.1", "tx", MCF_EDMA_FILTER_PARAM(5) }, + { "uart.2", "rx", MCF_EDMA_FILTER_PARAM(6) }, + { "uart.2", "tx", MCF_EDMA_FILTER_PARAM(7) }, + { "timer0", "rx-tx", MCF_EDMA_FILTER_PARAM(8) }, + { "timer1", "rx-tx", MCF_EDMA_FILTER_PARAM(9) }, + { "timer2", "rx-tx", MCF_EDMA_FILTER_PARAM(10) }, + { "timer3", "rx-tx", MCF_EDMA_FILTER_PARAM(11) }, + { "fsl-dspi.0", "rx", MCF_EDMA_FILTER_PARAM(12) }, + { "fsl-dspi.0", "tx", MCF_EDMA_FILTER_PARAM(13) }, + { "fsl-dspi.1", "rx", MCF_EDMA_FILTER_PARAM(14) }, + { "fsl-dspi.1", "tx", MCF_EDMA_FILTER_PARAM(15) }, +}; + +static struct mcf_edma_platform_data mcf_edma_data = { + .dma_channels = 64, + .slave_map = mcf_edma_map, + .slavecnt = ARRAY_SIZE(mcf_edma_map), +}; + +static struct resource mcf_edma_resources[] = { + { + .start = MCFEDMA_BASE, + .end = MCFEDMA_BASE + MCFEDMA_SIZE - 1, + .flags = IORESOURCE_MEM, + }, + { + .start = MCFEDMA_IRQ_INTR0, + .end = MCFEDMA_IRQ_INTR0 + 15, + .flags = IORESOURCE_IRQ, + .name = "edma-tx-00-15", + }, + { + .start = MCFEDMA_IRQ_INTR16, + .end = MCFEDMA_IRQ_INTR16 + 39, + .flags = IORESOURCE_IRQ, + .name = "edma-tx-16-55", + }, + { + .start = MCFEDMA_IRQ_INTR56, + .end = MCFEDMA_IRQ_INTR56, + .flags = IORESOURCE_IRQ, + .name = "edma-tx-56-63", + }, + { + .start = MCFEDMA_IRQ_ERR, + .end = MCFEDMA_IRQ_ERR, + .flags = IORESOURCE_IRQ, + .name = "edma-err", + }, +}; + +static u64 mcf_edma_dmamask = DMA_BIT_MASK(32); + +static struct platform_device mcf_edma = { + .name = "mcf-edma", + .id = 0, + .num_resources = ARRAY_SIZE(mcf_edma_resources), + .resource = mcf_edma_resources, + .dev = { + .dma_mask = &mcf_edma_dmamask, + .coherent_dma_mask = DMA_BIT_MASK(32), + .platform_data = &mcf_edma_data, + } +}; +#endif /* MCFEDMA_BASE */ + +#ifdef MCFSDHC_BASE +static struct mcf_esdhc_platform_data mcf_esdhc_data = { + .max_bus_width = 4, + .cd_type = ESDHC_CD_NONE, +}; + +static struct resource mcf_esdhc_resources[] = { + { + .start = MCFSDHC_BASE, + .end = MCFSDHC_BASE + MCFSDHC_SIZE - 1, + .flags = IORESOURCE_MEM, + }, { + .start = MCF_IRQ_SDHC, + .end = MCF_IRQ_SDHC, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device mcf_esdhc = { + .name = "sdhci-esdhc-mcf", + .id = 0, + .num_resources = ARRAY_SIZE(mcf_esdhc_resources), + .resource = mcf_esdhc_resources, + .dev.platform_data = &mcf_esdhc_data, +}; +#endif /* MCFSDHC_BASE */ + +static struct platform_device *mcf_devices[] __initdata = { + &mcf_uart, +#if IS_ENABLED(CONFIG_FEC) + &mcf_fec0, +#ifdef MCFFEC_BASE1 + &mcf_fec1, +#endif +#endif +#if IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI) + &mcf_qspi, +#endif +#if IS_ENABLED(CONFIG_I2C_IMX) + &mcf_i2c0, +#ifdef MCFI2C_BASE1 + &mcf_i2c1, +#endif +#ifdef MCFI2C_BASE2 + &mcf_i2c2, +#endif +#ifdef MCFI2C_BASE3 + &mcf_i2c3, +#endif +#ifdef MCFI2C_BASE4 + &mcf_i2c4, +#endif +#ifdef MCFI2C_BASE5 + &mcf_i2c5, +#endif +#endif +#ifdef MCFEDMA_BASE + &mcf_edma, +#endif +#ifdef MCFSDHC_BASE + &mcf_esdhc, +#endif +}; + +/* + * Some ColdFire UARTs let you set the IRQ line to use. + */ +static void __init mcf_uart_set_irq(void) +{ +#ifdef MCFUART_UIVR + /* UART0 interrupt setup */ + writeb(MCFSIM_ICR_LEVEL6 | MCFSIM_ICR_PRI1, MCFSIM_UART1ICR); + writeb(MCF_IRQ_UART0, MCFUART_BASE0 + MCFUART_UIVR); + mcf_mapirq2imr(MCF_IRQ_UART0, MCFINTC_UART0); + + /* UART1 interrupt setup */ + writeb(MCFSIM_ICR_LEVEL6 | MCFSIM_ICR_PRI2, MCFSIM_UART2ICR); + writeb(MCF_IRQ_UART1, MCFUART_BASE1 + MCFUART_UIVR); + mcf_mapirq2imr(MCF_IRQ_UART1, MCFINTC_UART1); +#endif +} + +static int __init mcf_init_devices(void) +{ + mcf_uart_set_irq(); + platform_add_devices(mcf_devices, ARRAY_SIZE(mcf_devices)); + return 0; +} + +arch_initcall(mcf_init_devices); diff --git a/arch/m68k/coldfire/dma.c b/arch/m68k/coldfire/dma.c new file mode 100644 index 000000000..c3279f746 --- /dev/null +++ b/arch/m68k/coldfire/dma.c @@ -0,0 +1,43 @@ +// SPDX-License-Identifier: GPL-2.0 +/***************************************************************************/ + +/* + * dma.c -- Freescale ColdFire DMA support + * + * Copyright (C) 2007, Greg Ungerer (gerg@snapgear.com) + */ + +/***************************************************************************/ + +#include +#include +#include +#include +#include +#include + +/***************************************************************************/ + +/* + * DMA channel base address table. + */ +unsigned int dma_base_addr[MAX_M68K_DMA_CHANNELS] = { +#ifdef MCFDMA_BASE0 + MCFDMA_BASE0, +#endif +#ifdef MCFDMA_BASE1 + MCFDMA_BASE1, +#endif +#ifdef MCFDMA_BASE2 + MCFDMA_BASE2, +#endif +#ifdef MCFDMA_BASE3 + MCFDMA_BASE3, +#endif +}; +EXPORT_SYMBOL(dma_base_addr); + +unsigned int dma_device_address[MAX_M68K_DMA_CHANNELS]; +EXPORT_SYMBOL(dma_device_address); + +/***************************************************************************/ diff --git a/arch/m68k/coldfire/dma_timer.c b/arch/m68k/coldfire/dma_timer.c new file mode 100644 index 000000000..cbb289439 --- /dev/null +++ b/arch/m68k/coldfire/dma_timer.c @@ -0,0 +1,82 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * dma_timer.c -- Freescale ColdFire DMA Timer. + * + * Copyright (C) 2007, Benedikt Spranger + * Copyright (C) 2008. Sebastian Siewior, Linutronix + * + */ + +#include +#include + +#include +#include +#include +#include + +#define DMA_TIMER_0 (0x00) +#define DMA_TIMER_1 (0x40) +#define DMA_TIMER_2 (0x80) +#define DMA_TIMER_3 (0xc0) + +#define DTMR0 (MCF_IPSBAR + DMA_TIMER_0 + 0x400) +#define DTXMR0 (MCF_IPSBAR + DMA_TIMER_0 + 0x402) +#define DTER0 (MCF_IPSBAR + DMA_TIMER_0 + 0x403) +#define DTRR0 (MCF_IPSBAR + DMA_TIMER_0 + 0x404) +#define DTCR0 (MCF_IPSBAR + DMA_TIMER_0 + 0x408) +#define DTCN0 (MCF_IPSBAR + DMA_TIMER_0 + 0x40c) + +#define DMA_FREQ ((MCF_CLK / 2) / 16) + +/* DTMR */ +#define DMA_DTMR_RESTART (1 << 3) +#define DMA_DTMR_CLK_DIV_1 (1 << 1) +#define DMA_DTMR_CLK_DIV_16 (2 << 1) +#define DMA_DTMR_ENABLE (1 << 0) + +static u64 cf_dt_get_cycles(struct clocksource *cs) +{ + return __raw_readl(DTCN0); +} + +static struct clocksource clocksource_cf_dt = { + .name = "coldfire_dma_timer", + .rating = 200, + .read = cf_dt_get_cycles, + .mask = CLOCKSOURCE_MASK(32), + .flags = CLOCK_SOURCE_IS_CONTINUOUS, +}; + +static int __init init_cf_dt_clocksource(void) +{ + /* + * We setup DMA timer 0 in free run mode. This incrementing counter is + * used as a highly precious clock source. With MCF_CLOCK = 150 MHz we + * get a ~213 ns resolution and the 32bit register will overflow almost + * every 15 minutes. + */ + __raw_writeb(0x00, DTXMR0); + __raw_writeb(0x00, DTER0); + __raw_writel(0x00000000, DTRR0); + __raw_writew(DMA_DTMR_CLK_DIV_16 | DMA_DTMR_ENABLE, DTMR0); + return clocksource_register_hz(&clocksource_cf_dt, DMA_FREQ); +} + +arch_initcall(init_cf_dt_clocksource); + +#define CYC2NS_SCALE_FACTOR 10 /* 2^10, carefully chosen */ +#define CYC2NS_SCALE ((1000000 << CYC2NS_SCALE_FACTOR) / (DMA_FREQ / 1000)) + +static unsigned long long cycles2ns(unsigned long cycl) +{ + return (unsigned long long) ((unsigned long long)cycl * + CYC2NS_SCALE) >> CYC2NS_SCALE_FACTOR; +} + +unsigned long long sched_clock(void) +{ + unsigned long cycl = __raw_readl(DTCN0); + + return cycles2ns(cycl); +} diff --git a/arch/m68k/coldfire/entry.S b/arch/m68k/coldfire/entry.S new file mode 100644 index 000000000..f1d41a932 --- /dev/null +++ b/arch/m68k/coldfire/entry.S @@ -0,0 +1,205 @@ +/* + * entry.S -- interrupt and exception processing for ColdFire + * + * Copyright (C) 1999-2007, Greg Ungerer (gerg@snapgear.com) + * Copyright (C) 1998 D. Jeff Dionne , + * Kenneth Albanowski , + * Copyright (C) 2000 Lineo Inc. (www.lineo.com) + * Copyright (C) 2004-2006 Macq Electronique SA. (www.macqel.com) + * + * Based on: + * + * linux/arch/m68k/kernel/entry.S + * + * Copyright (C) 1991, 1992 Linus Torvalds + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file README.legal in the main directory of this archive + * for more details. + * + * Linux/m68k support by Hamish Macdonald + * + * 68060 fixes by Jesper Skov + * ColdFire support by Greg Ungerer (gerg@snapgear.com) + * 5307 fixes by David W. Miller + * linux 2.4 support David McCullough + * Bug, speed and maintainability fixes by Philippe De Muyter + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#ifdef CONFIG_COLDFIRE_SW_A7 +/* + * Define software copies of the supervisor and user stack pointers. + */ +.bss +sw_ksp: +.long 0 +sw_usp: +.long 0 +#endif /* CONFIG_COLDFIRE_SW_A7 */ + +.text + +.globl system_call +.globl resume +.globl ret_from_exception +.globl ret_from_signal +.globl sys_call_table +.globl inthandler + +enosys: + mov.l #sys_ni_syscall,%d3 + bra 1f + +ENTRY(system_call) + SAVE_ALL_SYS + move #0x2000,%sr /* enable intrs again */ + GET_CURRENT(%d2) + + cmpl #NR_syscalls,%d0 + jcc enosys + lea sys_call_table,%a0 + lsll #2,%d0 /* movel %a0@(%d0:l:4),%d3 */ + movel %a0@(%d0),%d3 + jeq enosys + +1: + movel %sp,%d2 /* get thread_info pointer */ + andl #-THREAD_SIZE,%d2 /* at start of kernel stack */ + movel %d2,%a0 + movel %a0@,%a1 /* save top of frame */ + movel %sp,%a1@(TASK_THREAD+THREAD_ESP0) + btst #(TIF_SYSCALL_TRACE%8),%a0@(TINFO_FLAGS+(31-TIF_SYSCALL_TRACE)/8) + bnes 1f + + movel %d3,%a0 + jbsr %a0@ + movel %d0,%sp@(PT_OFF_D0) /* save the return value */ + jra ret_from_exception +1: + movel #-ENOSYS,%d2 /* strace needs -ENOSYS in PT_OFF_D0 */ + movel %d2,PT_OFF_D0(%sp) /* on syscall entry */ + subql #4,%sp + SAVE_SWITCH_STACK + jbsr syscall_trace_enter + RESTORE_SWITCH_STACK + addql #4,%sp + addql #1,%d0 + jeq ret_from_exception + movel %d3,%a0 + jbsr %a0@ + movel %d0,%sp@(PT_OFF_D0) /* save the return value */ + subql #4,%sp /* dummy return address */ + SAVE_SWITCH_STACK + jbsr syscall_trace_leave + +ret_from_signal: + RESTORE_SWITCH_STACK + addql #4,%sp + +ret_from_exception: + move #0x2700,%sr /* disable intrs */ + btst #5,%sp@(PT_OFF_SR) /* check if returning to kernel */ + jeq Luser_return /* if so, skip resched, signals */ + +#ifdef CONFIG_PREEMPTION + movel %sp,%d1 /* get thread_info pointer */ + andl #-THREAD_SIZE,%d1 /* at base of kernel stack */ + movel %d1,%a0 + movel %a0@(TINFO_FLAGS),%d1 /* get thread_info->flags */ + andl #(1<flags (low 8 bits) */ + jne Lwork_to_do /* still work to do */ + +Lreturn: + RESTORE_USER + +Lwork_to_do: + movel %a0@(TINFO_FLAGS),%d1 /* get thread_info->flags */ + move #0x2000,%sr /* enable intrs again */ + btst #TIF_NEED_RESCHED,%d1 + jne reschedule + +Lsignal_return: + subql #4,%sp /* dummy return address */ + SAVE_SWITCH_STACK + pea %sp@(SWITCH_STACK_SIZE) + jsr do_notify_resume + addql #4,%sp + RESTORE_SWITCH_STACK + addql #4,%sp + jmp Luser_return + +/* + * This is the generic interrupt handler (for all hardware interrupt + * sources). Calls up to high level code to do all the work. + */ +ENTRY(inthandler) + SAVE_ALL_INT + GET_CURRENT(%d2) + + movew %sp@(PT_OFF_FORMATVEC),%d0 /* put exception # in d0 */ + andl #0x03fc,%d0 /* mask out vector only */ + + movel %sp,%sp@- /* push regs arg */ + lsrl #2,%d0 /* calculate real vector # */ + movel %d0,%sp@- /* push vector number */ + jbsr do_IRQ /* call high level irq handler */ + lea %sp@(8),%sp /* pop args off stack */ + + bra ret_from_exception + +/* + * Beware - when entering resume, prev (the current task) is + * in a0, next (the new task) is in a1, so don't change these + * registers until their contents are no longer needed. + */ +ENTRY(resume) + movew %sr,%d1 /* save current status */ + movew %d1,%a0@(TASK_THREAD+THREAD_SR) + movel %a0,%d1 /* get prev thread in d1 */ + SAVE_SWITCH_STACK + movel %sp,%a0@(TASK_THREAD+THREAD_KSP) /* save kernel stack pointer */ + RDUSP /* movel %usp,%a3 */ + movel %a3,%a0@(TASK_THREAD+THREAD_USP) /* save thread user stack */ +#ifdef CONFIG_MMU + movel %a1,%a2 /* set new current */ +#endif + movel %a1@(TASK_THREAD+THREAD_USP),%a3 /* restore thread user stack */ + WRUSP /* movel %a3,%usp */ + movel %a1@(TASK_THREAD+THREAD_KSP),%sp /* restore new kernel stack */ + movew %a1@(TASK_THREAD+THREAD_SR),%d7 /* restore new status */ + movew %d7,%sr + RESTORE_SWITCH_STACK + rts + diff --git a/arch/m68k/coldfire/firebee.c b/arch/m68k/coldfire/firebee.c new file mode 100644 index 000000000..3b9d4fc6f --- /dev/null +++ b/arch/m68k/coldfire/firebee.c @@ -0,0 +1,87 @@ +// SPDX-License-Identifier: GPL-2.0 +/***************************************************************************/ + +/* + * firebee.c -- extra startup code support for the FireBee boards + * + * Copyright (C) 2011, Greg Ungerer (gerg@snapgear.com) + */ + +/***************************************************************************/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/***************************************************************************/ + +/* + * 8MB of NOR flash fitted to the FireBee board. + */ +#define FLASH_PHYS_ADDR 0xe0000000 /* Physical address of flash */ +#define FLASH_PHYS_SIZE 0x00800000 /* Size of flash */ + +#define PART_BOOT_START 0x00000000 /* Start at bottom of flash */ +#define PART_BOOT_SIZE 0x00040000 /* 256k in size */ +#define PART_IMAGE_START 0x00040000 /* Start after boot loader */ +#define PART_IMAGE_SIZE 0x006c0000 /* Most of flash */ +#define PART_FPGA_START 0x00700000 /* Start at offset 7MB */ +#define PART_FPGA_SIZE 0x00100000 /* 1MB in size */ + +static struct mtd_partition firebee_flash_parts[] = { + { + .name = "dBUG", + .offset = PART_BOOT_START, + .size = PART_BOOT_SIZE, + }, + { + .name = "FPGA", + .offset = PART_FPGA_START, + .size = PART_FPGA_SIZE, + }, + { + .name = "image", + .offset = PART_IMAGE_START, + .size = PART_IMAGE_SIZE, + }, +}; + +static struct physmap_flash_data firebee_flash_data = { + .width = 2, + .nr_parts = ARRAY_SIZE(firebee_flash_parts), + .parts = firebee_flash_parts, +}; + +static struct resource firebee_flash_resource = { + .start = FLASH_PHYS_ADDR, + .end = FLASH_PHYS_ADDR + FLASH_PHYS_SIZE, + .flags = IORESOURCE_MEM, +}; + +static struct platform_device firebee_flash = { + .name = "physmap-flash", + .id = 0, + .dev = { + .platform_data = &firebee_flash_data, + }, + .num_resources = 1, + .resource = &firebee_flash_resource, +}; + +/***************************************************************************/ + +static int __init init_firebee(void) +{ + platform_device_register(&firebee_flash); + return 0; +} + +arch_initcall(init_firebee); + +/***************************************************************************/ diff --git a/arch/m68k/coldfire/gpio.c b/arch/m68k/coldfire/gpio.c new file mode 100644 index 000000000..ca26de257 --- /dev/null +++ b/arch/m68k/coldfire/gpio.c @@ -0,0 +1,173 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Coldfire generic GPIO support. + * + * (C) Copyright 2009, Steven King + */ + +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +int __mcfgpio_get_value(unsigned gpio) +{ + return mcfgpio_read(__mcfgpio_ppdr(gpio)) & mcfgpio_bit(gpio); +} +EXPORT_SYMBOL(__mcfgpio_get_value); + +void __mcfgpio_set_value(unsigned gpio, int value) +{ + if (gpio < MCFGPIO_SCR_START) { + unsigned long flags; + MCFGPIO_PORTTYPE data; + + local_irq_save(flags); + data = mcfgpio_read(__mcfgpio_podr(gpio)); + if (value) + data |= mcfgpio_bit(gpio); + else + data &= ~mcfgpio_bit(gpio); + mcfgpio_write(data, __mcfgpio_podr(gpio)); + local_irq_restore(flags); + } else { + if (value) + mcfgpio_write(mcfgpio_bit(gpio), + MCFGPIO_SETR_PORT(gpio)); + else + mcfgpio_write(~mcfgpio_bit(gpio), + MCFGPIO_CLRR_PORT(gpio)); + } +} +EXPORT_SYMBOL(__mcfgpio_set_value); + +int __mcfgpio_direction_input(unsigned gpio) +{ + unsigned long flags; + MCFGPIO_PORTTYPE dir; + + local_irq_save(flags); + dir = mcfgpio_read(__mcfgpio_pddr(gpio)); + dir &= ~mcfgpio_bit(gpio); + mcfgpio_write(dir, __mcfgpio_pddr(gpio)); + local_irq_restore(flags); + + return 0; +} +EXPORT_SYMBOL(__mcfgpio_direction_input); + +int __mcfgpio_direction_output(unsigned gpio, int value) +{ + unsigned long flags; + MCFGPIO_PORTTYPE data; + + local_irq_save(flags); + data = mcfgpio_read(__mcfgpio_pddr(gpio)); + data |= mcfgpio_bit(gpio); + mcfgpio_write(data, __mcfgpio_pddr(gpio)); + + /* now set the data to output */ + if (gpio < MCFGPIO_SCR_START) { + data = mcfgpio_read(__mcfgpio_podr(gpio)); + if (value) + data |= mcfgpio_bit(gpio); + else + data &= ~mcfgpio_bit(gpio); + mcfgpio_write(data, __mcfgpio_podr(gpio)); + } else { + if (value) + mcfgpio_write(mcfgpio_bit(gpio), + MCFGPIO_SETR_PORT(gpio)); + else + mcfgpio_write(~mcfgpio_bit(gpio), + MCFGPIO_CLRR_PORT(gpio)); + } + local_irq_restore(flags); + return 0; +} +EXPORT_SYMBOL(__mcfgpio_direction_output); + +int __mcfgpio_request(unsigned gpio) +{ + return 0; +} +EXPORT_SYMBOL(__mcfgpio_request); + +void __mcfgpio_free(unsigned gpio) +{ + __mcfgpio_direction_input(gpio); +} +EXPORT_SYMBOL(__mcfgpio_free); + +#ifdef CONFIG_GPIOLIB + +static int mcfgpio_direction_input(struct gpio_chip *chip, unsigned offset) +{ + return __mcfgpio_direction_input(offset); +} + +static int mcfgpio_get_value(struct gpio_chip *chip, unsigned offset) +{ + return !!__mcfgpio_get_value(offset); +} + +static int mcfgpio_direction_output(struct gpio_chip *chip, unsigned offset, + int value) +{ + return __mcfgpio_direction_output(offset, value); +} + +static void mcfgpio_set_value(struct gpio_chip *chip, unsigned offset, + int value) +{ + __mcfgpio_set_value(offset, value); +} + +static int mcfgpio_request(struct gpio_chip *chip, unsigned offset) +{ + return __mcfgpio_request(offset); +} + +static void mcfgpio_free(struct gpio_chip *chip, unsigned offset) +{ + __mcfgpio_free(offset); +} + +static int mcfgpio_to_irq(struct gpio_chip *chip, unsigned offset) +{ +#if defined(MCFGPIO_IRQ_MIN) + if ((offset >= MCFGPIO_IRQ_MIN) && (offset < MCFGPIO_IRQ_MAX)) +#else + if (offset < MCFGPIO_IRQ_MAX) +#endif + return MCFGPIO_IRQ_VECBASE + offset; + else + return -EINVAL; +} + +static struct gpio_chip mcfgpio_chip = { + .label = "mcfgpio", + .request = mcfgpio_request, + .free = mcfgpio_free, + .direction_input = mcfgpio_direction_input, + .direction_output = mcfgpio_direction_output, + .get = mcfgpio_get_value, + .set = mcfgpio_set_value, + .to_irq = mcfgpio_to_irq, + .base = 0, + .ngpio = MCFGPIO_PIN_MAX, +}; + +static int __init mcfgpio_sysinit(void) +{ + return gpiochip_add_data(&mcfgpio_chip, NULL); +} + +core_initcall(mcfgpio_sysinit); +#endif diff --git a/arch/m68k/coldfire/head.S b/arch/m68k/coldfire/head.S new file mode 100644 index 000000000..c6d7fd28c --- /dev/null +++ b/arch/m68k/coldfire/head.S @@ -0,0 +1,299 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/*****************************************************************************/ + +/* + * head.S -- common startup code for ColdFire CPUs. + * + * (C) Copyright 1999-2011, Greg Ungerer . + */ + +/*****************************************************************************/ + +#include +#include +#include +#include +#include +#include +#include + +/*****************************************************************************/ + +/* + * If we don't have a fixed memory size, then lets build in code + * to auto detect the DRAM size. Obviously this is the preferred + * method, and should work for most boards. It won't work for those + * that do not have their RAM starting at address 0, and it only + * works on SDRAM (not boards fitted with SRAM). + */ +#if CONFIG_RAMSIZE != 0 +.macro GET_MEM_SIZE + movel #CONFIG_RAMSIZE,%d0 /* hard coded memory size */ +.endm + +#elif defined(CONFIG_M5206) || defined(CONFIG_M5206e) || \ + defined(CONFIG_M5249) || defined(CONFIG_M525x) || \ + defined(CONFIG_M527x) || defined(CONFIG_M528x) || \ + defined(CONFIG_M5307) || defined(CONFIG_M5407) +/* + * Not all these devices have exactly the same DRAM controller, + * but the DCMR register is virtually identical - give or take + * a couple of bits. The only exception is the 5272 devices, their + * DRAM controller is quite different. + */ +.macro GET_MEM_SIZE + movel MCFSIM_DMR0,%d0 /* get mask for 1st bank */ + btst #0,%d0 /* check if region enabled */ + beq 1f + andl #0xfffc0000,%d0 + beq 1f + addl #0x00040000,%d0 /* convert mask to size */ +1: + movel MCFSIM_DMR1,%d1 /* get mask for 2nd bank */ + btst #0,%d1 /* check if region enabled */ + beq 2f + andl #0xfffc0000,%d1 + beq 2f + addl #0x00040000,%d1 + addl %d1,%d0 /* total mem size in d0 */ +2: +.endm + +#elif defined(CONFIG_M5272) +.macro GET_MEM_SIZE + movel MCFSIM_CSOR7,%d0 /* get SDRAM address mask */ + andil #0xfffff000,%d0 /* mask out chip select options */ + negl %d0 /* negate bits */ +.endm + +#elif defined(CONFIG_M520x) +.macro GET_MEM_SIZE + clrl %d0 + movel MCFSIM_SDCS0, %d2 /* Get SDRAM chip select 0 config */ + andl #0x1f, %d2 /* Get only the chip select size */ + beq 3f /* Check if it is enabled */ + addql #1, %d2 /* Form exponent */ + moveql #1, %d0 + lsll %d2, %d0 /* 2 ^ exponent */ +3: + movel MCFSIM_SDCS1, %d2 /* Get SDRAM chip select 1 config */ + andl #0x1f, %d2 /* Get only the chip select size */ + beq 4f /* Check if it is enabled */ + addql #1, %d2 /* Form exponent */ + moveql #1, %d1 + lsll %d2, %d1 /* 2 ^ exponent */ + addl %d1, %d0 /* Total size of SDRAM in d0 */ +4: +.endm + +#else +#error "ERROR: I don't know how to probe your boards memory size?" +#endif + +/*****************************************************************************/ + +/* + * Boards and platforms can do specific early hardware setup if + * they need to. Most don't need this, define away if not required. + */ +#ifndef PLATFORM_SETUP +#define PLATFORM_SETUP +#endif + +/*****************************************************************************/ + +.global _start +.global _rambase +.global _ramvec +.global _ramstart +.global _ramend +#if defined(CONFIG_UBOOT) +.global _init_sp +#endif + +/*****************************************************************************/ + +.data + +/* + * During startup we store away the RAM setup. These are not in the + * bss, since their values are determined and written before the bss + * has been cleared. + */ +_rambase: +.long 0 +_ramvec: +.long 0 +_ramstart: +.long 0 +_ramend: +.long 0 +#if defined(CONFIG_UBOOT) +_init_sp: +.long 0 +#endif + +/*****************************************************************************/ + +__HEAD + +#ifdef CONFIG_MMU +_start0: + jmp _start +.global kernel_pg_dir +.equ kernel_pg_dir,_start0 +.equ .,_start0+0x1000 +#endif + +/* + * This is the codes first entry point. This is where it all + * begins... + */ + +_start: + nop /* filler */ + movew #0x2700, %sr /* no interrupts */ + movel #CACHE_INIT,%d0 /* disable cache */ + movec %d0,%CACR + nop +#if defined(CONFIG_UBOOT) + movel %sp,_init_sp /* save initial stack pointer */ +#endif +#ifdef CONFIG_MBAR + movel #CONFIG_MBAR+1,%d0 /* configured MBAR address */ + movec %d0,%MBAR /* set it */ +#endif + + /* + * Do any platform or board specific setup now. Most boards + * don't need anything. Those exceptions are define this in + * their board specific includes. + */ + PLATFORM_SETUP + + /* + * Create basic memory configuration. Set VBR accordingly, + * and size memory. + */ + movel #CONFIG_VECTORBASE,%a7 + movec %a7,%VBR /* set vectors addr */ + movel %a7,_ramvec + + movel #CONFIG_RAMBASE,%a7 /* mark the base of RAM */ + movel %a7,_rambase + + GET_MEM_SIZE /* macro code determines size */ + addl %a7,%d0 + movel %d0,_ramend /* set end ram addr */ + + /* + * Now that we know what the memory is, lets enable cache + * and get things moving. This is Coldfire CPU specific. Not + * all version cores have identical cache register setup. But + * it is very similar. Define the exact settings in the headers + * then the code here is the same for all. + */ + movel #ACR0_MODE,%d0 /* set RAM region for caching */ + movec %d0,%ACR0 + movel #ACR1_MODE,%d0 /* anything else to cache? */ + movec %d0,%ACR1 +#ifdef ACR2_MODE + movel #ACR2_MODE,%d0 + movec %d0,%ACR2 + movel #ACR3_MODE,%d0 + movec %d0,%ACR3 +#endif + movel #CACHE_MODE,%d0 /* enable cache */ + movec %d0,%CACR + nop + +#ifdef CONFIG_MMU + /* + * Identity mapping for the kernel region. + */ + movel #(MMUBASE+1),%d0 /* enable MMUBAR registers */ + movec %d0,%MMUBAR + movel #MMUOR_CA,%d0 /* clear TLB entries */ + movel %d0,MMUOR + movel #0,%d0 /* set ASID to 0 */ + movec %d0,%asid + + movel #MMUCR_EN,%d0 /* Enable the identity map */ + movel %d0,MMUCR + nop /* sync i-pipeline */ + + movel #_vstart,%a0 /* jump to "virtual" space */ + jmp %a0@ +_vstart: +#endif /* CONFIG_MMU */ + +#ifdef CONFIG_ROMFS_FS + /* + * Move ROM filesystem above bss :-) + */ + lea __bss_start,%a0 /* get start of bss */ + lea __bss_stop,%a1 /* set up destination */ + movel %a0,%a2 /* copy of bss start */ + + movel 8(%a0),%d0 /* get size of ROMFS */ + addql #8,%d0 /* allow for rounding */ + andl #0xfffffffc, %d0 /* whole words */ + + addl %d0,%a0 /* copy from end */ + addl %d0,%a1 /* copy from end */ + movel %a1,_ramstart /* set start of ram */ + +_copy_romfs: + movel -(%a0),%d0 /* copy dword */ + movel %d0,-(%a1) + cmpl %a0,%a2 /* check if at end */ + bne _copy_romfs + +#else /* CONFIG_ROMFS_FS */ + lea __bss_stop,%a1 + movel %a1,_ramstart +#endif /* CONFIG_ROMFS_FS */ + + + /* + * Zero out the bss region. + */ + lea __bss_start,%a0 /* get start of bss */ + lea __bss_stop,%a1 /* get end of bss */ + clrl %d0 /* set value */ +_clear_bss: + movel %d0,(%a0)+ /* clear each word */ + cmpl %a0,%a1 /* check if at end */ + bne _clear_bss + + /* + * Load the current task pointer and stack. + */ + lea init_thread_union,%a0 + lea THREAD_SIZE(%a0),%sp + +#ifdef CONFIG_MMU +.global m68k_cputype +.global m68k_mmutype +.global m68k_fputype +.global m68k_machtype + movel #CPU_COLDFIRE,%d0 + movel %d0,m68k_cputype /* Mark us as a ColdFire */ + movel #MMU_COLDFIRE,%d0 + movel %d0,m68k_mmutype + movel #FPUTYPE,%d0 + movel %d0,m68k_fputype /* Mark FPU type */ + movel #MACHINE,%d0 + movel %d0,m68k_machtype /* Mark machine type */ + lea init_task,%a2 /* Set "current" init task */ +#endif + + /* + * Assembler start up done, start code proper. + */ + jsr start_kernel /* start Linux kernel */ + +_exit: + jmp _exit /* should never get here */ + +/*****************************************************************************/ diff --git a/arch/m68k/coldfire/intc-2.c b/arch/m68k/coldfire/intc-2.c new file mode 100644 index 000000000..995093357 --- /dev/null +++ b/arch/m68k/coldfire/intc-2.c @@ -0,0 +1,212 @@ +/* + * intc-2.c + * + * General interrupt controller code for the many ColdFire cores that use + * interrupt controllers with 63 interrupt sources, organized as 56 fully- + * programmable + 7 fixed-level interrupt sources. This includes the 523x + * family, the 5270, 5271, 5274, 5275, and the 528x family which have two such + * controllers, and the 547x and 548x families which have only one of them. + * + * The external 7 fixed interrupts are part the the Edge Port unit of these + * ColdFire parts. They can be configured as level or edge triggered. + * + * (C) Copyright 2009-2011, Greg Ungerer + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file COPYING in the main directory of this archive + * for more details. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* + * Bit definitions for the ICR family of registers. + */ +#define MCFSIM_ICR_LEVEL(l) ((l)<<3) /* Level l intr */ +#define MCFSIM_ICR_PRI(p) (p) /* Priority p intr */ + +/* + * The EDGE Port interrupts are the fixed 7 external interrupts. + * They need some special treatment, for example they need to be acked. + */ +#define EINT0 64 /* Is not actually used, but spot reserved for it */ +#define EINT1 65 /* EDGE Port interrupt 1 */ +#define EINT7 71 /* EDGE Port interrupt 7 */ + +#ifdef MCFICM_INTC1 +#define NR_VECS 128 +#else +#define NR_VECS 64 +#endif + +static void intc_irq_mask(struct irq_data *d) +{ + unsigned int irq = d->irq - MCFINT_VECBASE; + unsigned long imraddr; + u32 val, imrbit; + +#ifdef MCFICM_INTC1 + imraddr = (irq & 0x40) ? MCFICM_INTC1 : MCFICM_INTC0; +#else + imraddr = MCFICM_INTC0; +#endif + imraddr += (irq & 0x20) ? MCFINTC_IMRH : MCFINTC_IMRL; + imrbit = 0x1 << (irq & 0x1f); + + val = __raw_readl(imraddr); + __raw_writel(val | imrbit, imraddr); +} + +static void intc_irq_unmask(struct irq_data *d) +{ + unsigned int irq = d->irq - MCFINT_VECBASE; + unsigned long imraddr; + u32 val, imrbit; + +#ifdef MCFICM_INTC1 + imraddr = (irq & 0x40) ? MCFICM_INTC1 : MCFICM_INTC0; +#else + imraddr = MCFICM_INTC0; +#endif + imraddr += ((irq & 0x20) ? MCFINTC_IMRH : MCFINTC_IMRL); + imrbit = 0x1 << (irq & 0x1f); + + /* Don't set the "maskall" bit! */ + if ((irq & 0x20) == 0) + imrbit |= 0x1; + + val = __raw_readl(imraddr); + __raw_writel(val & ~imrbit, imraddr); +} + +/* + * Only the external (or EDGE Port) interrupts need to be acknowledged + * here, as part of the IRQ handler. They only really need to be ack'ed + * if they are in edge triggered mode, but there is no harm in doing it + * for all types. + */ +static void intc_irq_ack(struct irq_data *d) +{ + unsigned int irq = d->irq; + + __raw_writeb(0x1 << (irq - EINT0), MCFEPORT_EPFR); +} + +/* + * Each vector needs a unique priority and level associated with it. + * We don't really care so much what they are, we don't rely on the + * traditional priority interrupt scheme of the m68k/ColdFire. This + * only needs to be set once for an interrupt, and we will never change + * these values once we have set them. + */ +static u8 intc_intpri = MCFSIM_ICR_LEVEL(6) | MCFSIM_ICR_PRI(6); + +static unsigned int intc_irq_startup(struct irq_data *d) +{ + unsigned int irq = d->irq - MCFINT_VECBASE; + unsigned long icraddr; + +#ifdef MCFICM_INTC1 + icraddr = (irq & 0x40) ? MCFICM_INTC1 : MCFICM_INTC0; +#else + icraddr = MCFICM_INTC0; +#endif + icraddr += MCFINTC_ICR0 + (irq & 0x3f); + if (__raw_readb(icraddr) == 0) + __raw_writeb(intc_intpri--, icraddr); + + irq = d->irq; + if ((irq >= EINT1) && (irq <= EINT7)) { + u8 v; + + irq -= EINT0; + + /* Set EPORT line as input */ + v = __raw_readb(MCFEPORT_EPDDR); + __raw_writeb(v & ~(0x1 << irq), MCFEPORT_EPDDR); + + /* Set EPORT line as interrupt source */ + v = __raw_readb(MCFEPORT_EPIER); + __raw_writeb(v | (0x1 << irq), MCFEPORT_EPIER); + } + + intc_irq_unmask(d); + return 0; +} + +static int intc_irq_set_type(struct irq_data *d, unsigned int type) +{ + unsigned int irq = d->irq; + u16 pa, tb; + + switch (type) { + case IRQ_TYPE_EDGE_RISING: + tb = 0x1; + break; + case IRQ_TYPE_EDGE_FALLING: + tb = 0x2; + break; + case IRQ_TYPE_EDGE_BOTH: + tb = 0x3; + break; + default: + /* Level triggered */ + tb = 0; + break; + } + + if (tb) + irq_set_handler(irq, handle_edge_irq); + + irq -= EINT0; + pa = __raw_readw(MCFEPORT_EPPAR); + pa = (pa & ~(0x3 << (irq * 2))) | (tb << (irq * 2)); + __raw_writew(pa, MCFEPORT_EPPAR); + + return 0; +} + +static struct irq_chip intc_irq_chip = { + .name = "CF-INTC", + .irq_startup = intc_irq_startup, + .irq_mask = intc_irq_mask, + .irq_unmask = intc_irq_unmask, +}; + +static struct irq_chip intc_irq_chip_edge_port = { + .name = "CF-INTC-EP", + .irq_startup = intc_irq_startup, + .irq_mask = intc_irq_mask, + .irq_unmask = intc_irq_unmask, + .irq_ack = intc_irq_ack, + .irq_set_type = intc_irq_set_type, +}; + +void __init init_IRQ(void) +{ + int irq; + + /* Mask all interrupt sources */ + __raw_writel(0x1, MCFICM_INTC0 + MCFINTC_IMRL); +#ifdef MCFICM_INTC1 + __raw_writel(0x1, MCFICM_INTC1 + MCFINTC_IMRL); +#endif + + for (irq = MCFINT_VECBASE; (irq < MCFINT_VECBASE + NR_VECS); irq++) { + if ((irq >= EINT1) && (irq <=EINT7)) + irq_set_chip(irq, &intc_irq_chip_edge_port); + else + irq_set_chip(irq, &intc_irq_chip); + irq_set_irq_type(irq, IRQ_TYPE_LEVEL_HIGH); + irq_set_handler(irq, handle_level_irq); + } +} + diff --git a/arch/m68k/coldfire/intc-5249.c b/arch/m68k/coldfire/intc-5249.c new file mode 100644 index 000000000..b0d164105 --- /dev/null +++ b/arch/m68k/coldfire/intc-5249.c @@ -0,0 +1,61 @@ +/* + * intc2.c -- support for the 2nd INTC controller of the 5249 + * + * (C) Copyright 2009, Greg Ungerer + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file COPYING in the main directory of this archive + * for more details. + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +static void intc2_irq_gpio_mask(struct irq_data *d) +{ + u32 imr; + imr = readl(MCFSIM2_GPIOINTENABLE); + imr &= ~(0x1 << (d->irq - MCF_IRQ_GPIO0)); + writel(imr, MCFSIM2_GPIOINTENABLE); +} + +static void intc2_irq_gpio_unmask(struct irq_data *d) +{ + u32 imr; + imr = readl(MCFSIM2_GPIOINTENABLE); + imr |= (0x1 << (d->irq - MCF_IRQ_GPIO0)); + writel(imr, MCFSIM2_GPIOINTENABLE); +} + +static void intc2_irq_gpio_ack(struct irq_data *d) +{ + writel(0x1 << (d->irq - MCF_IRQ_GPIO0), MCFSIM2_GPIOINTCLEAR); +} + +static struct irq_chip intc2_irq_gpio_chip = { + .name = "CF-INTC2", + .irq_mask = intc2_irq_gpio_mask, + .irq_unmask = intc2_irq_gpio_unmask, + .irq_ack = intc2_irq_gpio_ack, +}; + +static int __init mcf_intc2_init(void) +{ + int irq; + + /* GPIO interrupt sources */ + for (irq = MCF_IRQ_GPIO0; (irq <= MCF_IRQ_GPIO7); irq++) { + irq_set_chip(irq, &intc2_irq_gpio_chip); + irq_set_handler(irq, handle_edge_irq); + } + + return 0; +} + +arch_initcall(mcf_intc2_init); diff --git a/arch/m68k/coldfire/intc-525x.c b/arch/m68k/coldfire/intc-525x.c new file mode 100644 index 000000000..b23204d05 --- /dev/null +++ b/arch/m68k/coldfire/intc-525x.c @@ -0,0 +1,91 @@ +/* + * intc2.c -- support for the 2nd INTC controller of the 525x + * + * (C) Copyright 2012, Steven King + * (C) Copyright 2009, Greg Ungerer + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file COPYING in the main directory of this archive + * for more details. + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +static void intc2_irq_gpio_mask(struct irq_data *d) +{ + u32 imr = readl(MCFSIM2_GPIOINTENABLE); + u32 type = irqd_get_trigger_type(d); + int irq = d->irq - MCF_IRQ_GPIO0; + + if (type & IRQ_TYPE_EDGE_RISING) + imr &= ~(0x001 << irq); + if (type & IRQ_TYPE_EDGE_FALLING) + imr &= ~(0x100 << irq); + writel(imr, MCFSIM2_GPIOINTENABLE); +} + +static void intc2_irq_gpio_unmask(struct irq_data *d) +{ + u32 imr = readl(MCFSIM2_GPIOINTENABLE); + u32 type = irqd_get_trigger_type(d); + int irq = d->irq - MCF_IRQ_GPIO0; + + if (type & IRQ_TYPE_EDGE_RISING) + imr |= (0x001 << irq); + if (type & IRQ_TYPE_EDGE_FALLING) + imr |= (0x100 << irq); + writel(imr, MCFSIM2_GPIOINTENABLE); +} + +static void intc2_irq_gpio_ack(struct irq_data *d) +{ + u32 imr = 0; + u32 type = irqd_get_trigger_type(d); + int irq = d->irq - MCF_IRQ_GPIO0; + + if (type & IRQ_TYPE_EDGE_RISING) + imr |= (0x001 << irq); + if (type & IRQ_TYPE_EDGE_FALLING) + imr |= (0x100 << irq); + writel(imr, MCFSIM2_GPIOINTCLEAR); +} + +static int intc2_irq_gpio_set_type(struct irq_data *d, unsigned int f) +{ + if (f & ~IRQ_TYPE_EDGE_BOTH) + return -EINVAL; + return 0; +} + +static struct irq_chip intc2_irq_gpio_chip = { + .name = "CF-INTC2", + .irq_mask = intc2_irq_gpio_mask, + .irq_unmask = intc2_irq_gpio_unmask, + .irq_ack = intc2_irq_gpio_ack, + .irq_set_type = intc2_irq_gpio_set_type, +}; + +static int __init mcf_intc2_init(void) +{ + int irq; + + /* set the interrupt base for the second interrupt controller */ + writel(MCFINTC2_VECBASE, MCFINTC2_INTBASE); + + /* GPIO interrupt sources */ + for (irq = MCF_IRQ_GPIO0; (irq <= MCF_IRQ_GPIO6); irq++) { + irq_set_chip(irq, &intc2_irq_gpio_chip); + irq_set_handler(irq, handle_edge_irq); + } + + return 0; +} + +arch_initcall(mcf_intc2_init); diff --git a/arch/m68k/coldfire/intc-5272.c b/arch/m68k/coldfire/intc-5272.c new file mode 100644 index 000000000..b0a19e207 --- /dev/null +++ b/arch/m68k/coldfire/intc-5272.c @@ -0,0 +1,185 @@ +/* + * intc.c -- interrupt controller or ColdFire 5272 SoC + * + * (C) Copyright 2009, Greg Ungerer + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file COPYING in the main directory of this archive + * for more details. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* + * The 5272 ColdFire interrupt controller is nothing like any other + * ColdFire interrupt controller - it truly is completely different. + * Given its age it is unlikely to be used on any other ColdFire CPU. + */ + +/* + * The masking and priproty setting of interrupts on the 5272 is done + * via a set of 4 "Interrupt Controller Registers" (ICR). There is a + * loose mapping of vector number to register and internal bits, but + * a table is the easiest and quickest way to map them. + * + * Note that the external interrupts are edge triggered (unlike the + * internal interrupt sources which are level triggered). Which means + * they also need acknowledging via acknowledge bits. + */ +struct irqmap { + unsigned int icr; + unsigned char index; + unsigned char ack; +}; + +static struct irqmap intc_irqmap[MCFINT_VECMAX - MCFINT_VECBASE] = { + /*MCF_IRQ_SPURIOUS*/ { .icr = 0, .index = 0, .ack = 0, }, + /*MCF_IRQ_EINT1*/ { .icr = MCFSIM_ICR1, .index = 28, .ack = 1, }, + /*MCF_IRQ_EINT2*/ { .icr = MCFSIM_ICR1, .index = 24, .ack = 1, }, + /*MCF_IRQ_EINT3*/ { .icr = MCFSIM_ICR1, .index = 20, .ack = 1, }, + /*MCF_IRQ_EINT4*/ { .icr = MCFSIM_ICR1, .index = 16, .ack = 1, }, + /*MCF_IRQ_TIMER1*/ { .icr = MCFSIM_ICR1, .index = 12, .ack = 0, }, + /*MCF_IRQ_TIMER2*/ { .icr = MCFSIM_ICR1, .index = 8, .ack = 0, }, + /*MCF_IRQ_TIMER3*/ { .icr = MCFSIM_ICR1, .index = 4, .ack = 0, }, + /*MCF_IRQ_TIMER4*/ { .icr = MCFSIM_ICR1, .index = 0, .ack = 0, }, + /*MCF_IRQ_UART1*/ { .icr = MCFSIM_ICR2, .index = 28, .ack = 0, }, + /*MCF_IRQ_UART2*/ { .icr = MCFSIM_ICR2, .index = 24, .ack = 0, }, + /*MCF_IRQ_PLIP*/ { .icr = MCFSIM_ICR2, .index = 20, .ack = 0, }, + /*MCF_IRQ_PLIA*/ { .icr = MCFSIM_ICR2, .index = 16, .ack = 0, }, + /*MCF_IRQ_USB0*/ { .icr = MCFSIM_ICR2, .index = 12, .ack = 0, }, + /*MCF_IRQ_USB1*/ { .icr = MCFSIM_ICR2, .index = 8, .ack = 0, }, + /*MCF_IRQ_USB2*/ { .icr = MCFSIM_ICR2, .index = 4, .ack = 0, }, + /*MCF_IRQ_USB3*/ { .icr = MCFSIM_ICR2, .index = 0, .ack = 0, }, + /*MCF_IRQ_USB4*/ { .icr = MCFSIM_ICR3, .index = 28, .ack = 0, }, + /*MCF_IRQ_USB5*/ { .icr = MCFSIM_ICR3, .index = 24, .ack = 0, }, + /*MCF_IRQ_USB6*/ { .icr = MCFSIM_ICR3, .index = 20, .ack = 0, }, + /*MCF_IRQ_USB7*/ { .icr = MCFSIM_ICR3, .index = 16, .ack = 0, }, + /*MCF_IRQ_DMA*/ { .icr = MCFSIM_ICR3, .index = 12, .ack = 0, }, + /*MCF_IRQ_ERX*/ { .icr = MCFSIM_ICR3, .index = 8, .ack = 0, }, + /*MCF_IRQ_ETX*/ { .icr = MCFSIM_ICR3, .index = 4, .ack = 0, }, + /*MCF_IRQ_ENTC*/ { .icr = MCFSIM_ICR3, .index = 0, .ack = 0, }, + /*MCF_IRQ_QSPI*/ { .icr = MCFSIM_ICR4, .index = 28, .ack = 0, }, + /*MCF_IRQ_EINT5*/ { .icr = MCFSIM_ICR4, .index = 24, .ack = 1, }, + /*MCF_IRQ_EINT6*/ { .icr = MCFSIM_ICR4, .index = 20, .ack = 1, }, + /*MCF_IRQ_SWTO*/ { .icr = MCFSIM_ICR4, .index = 16, .ack = 0, }, +}; + +/* + * The act of masking the interrupt also has a side effect of 'ack'ing + * an interrupt on this irq (for the external irqs). So this mask function + * is also an ack_mask function. + */ +static void intc_irq_mask(struct irq_data *d) +{ + unsigned int irq = d->irq; + + if ((irq >= MCFINT_VECBASE) && (irq <= MCFINT_VECMAX)) { + u32 v; + irq -= MCFINT_VECBASE; + v = 0x8 << intc_irqmap[irq].index; + writel(v, intc_irqmap[irq].icr); + } +} + +static void intc_irq_unmask(struct irq_data *d) +{ + unsigned int irq = d->irq; + + if ((irq >= MCFINT_VECBASE) && (irq <= MCFINT_VECMAX)) { + u32 v; + irq -= MCFINT_VECBASE; + v = 0xd << intc_irqmap[irq].index; + writel(v, intc_irqmap[irq].icr); + } +} + +static void intc_irq_ack(struct irq_data *d) +{ + unsigned int irq = d->irq; + + /* Only external interrupts are acked */ + if ((irq >= MCFINT_VECBASE) && (irq <= MCFINT_VECMAX)) { + irq -= MCFINT_VECBASE; + if (intc_irqmap[irq].ack) { + u32 v; + v = readl(intc_irqmap[irq].icr); + v &= (0x7 << intc_irqmap[irq].index); + v |= (0x8 << intc_irqmap[irq].index); + writel(v, intc_irqmap[irq].icr); + } + } +} + +static int intc_irq_set_type(struct irq_data *d, unsigned int type) +{ + unsigned int irq = d->irq; + + if ((irq >= MCFINT_VECBASE) && (irq <= MCFINT_VECMAX)) { + irq -= MCFINT_VECBASE; + if (intc_irqmap[irq].ack) { + u32 v; + v = readl(MCFSIM_PITR); + if (type == IRQ_TYPE_EDGE_FALLING) + v &= ~(0x1 << (32 - irq)); + else + v |= (0x1 << (32 - irq)); + writel(v, MCFSIM_PITR); + } + } + return 0; +} + +/* + * Simple flow handler to deal with the external edge triggered interrupts. + * We need to be careful with the masking/acking due to the side effects + * of masking an interrupt. + */ +static void intc_external_irq(struct irq_desc *desc) +{ + irq_desc_get_chip(desc)->irq_ack(&desc->irq_data); + handle_simple_irq(desc); +} + +static struct irq_chip intc_irq_chip = { + .name = "CF-INTC", + .irq_mask = intc_irq_mask, + .irq_unmask = intc_irq_unmask, + .irq_mask_ack = intc_irq_mask, + .irq_ack = intc_irq_ack, + .irq_set_type = intc_irq_set_type, +}; + +void __init init_IRQ(void) +{ + int irq, edge; + + /* Mask all interrupt sources */ + writel(0x88888888, MCFSIM_ICR1); + writel(0x88888888, MCFSIM_ICR2); + writel(0x88888888, MCFSIM_ICR3); + writel(0x88888888, MCFSIM_ICR4); + + for (irq = 0; (irq < NR_IRQS); irq++) { + irq_set_chip(irq, &intc_irq_chip); + edge = 0; + if ((irq >= MCFINT_VECBASE) && (irq <= MCFINT_VECMAX)) + edge = intc_irqmap[irq - MCFINT_VECBASE].ack; + if (edge) { + irq_set_irq_type(irq, IRQ_TYPE_EDGE_RISING); + irq_set_handler(irq, intc_external_irq); + } else { + irq_set_irq_type(irq, IRQ_TYPE_LEVEL_HIGH); + irq_set_handler(irq, handle_level_irq); + } + } +} + diff --git a/arch/m68k/coldfire/intc-simr.c b/arch/m68k/coldfire/intc-simr.c new file mode 100644 index 000000000..15c4b7a6e --- /dev/null +++ b/arch/m68k/coldfire/intc-simr.c @@ -0,0 +1,199 @@ +/* + * intc-simr.c + * + * Interrupt controller code for the ColdFire 5208, 5207 & 532x parts. + * + * (C) Copyright 2009-2011, Greg Ungerer + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file COPYING in the main directory of this archive + * for more details. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* + * The EDGE Port interrupts are the fixed 7 external interrupts. + * They need some special treatment, for example they need to be acked. + */ +#ifdef CONFIG_M520x +/* + * The 520x parts only support a limited range of these external + * interrupts, only 1, 4 and 7 (as interrupts 65, 66 and 67). + */ +#define EINT0 64 /* Is not actually used, but spot reserved for it */ +#define EINT1 65 /* EDGE Port interrupt 1 */ +#define EINT4 66 /* EDGE Port interrupt 4 */ +#define EINT7 67 /* EDGE Port interrupt 7 */ + +static unsigned int irqebitmap[] = { 0, 1, 4, 7 }; +static inline unsigned int irq2ebit(unsigned int irq) +{ + return irqebitmap[irq - EINT0]; +} + +#else + +/* + * Most of the ColdFire parts with the EDGE Port module just have + * a strait direct mapping of the 7 external interrupts. Although + * there is a bit reserved for 0, it is not used. + */ +#define EINT0 64 /* Is not actually used, but spot reserved for it */ +#define EINT1 65 /* EDGE Port interrupt 1 */ +#define EINT7 71 /* EDGE Port interrupt 7 */ + +static inline unsigned int irq2ebit(unsigned int irq) +{ + return irq - EINT0; +} + +#endif + +/* + * There maybe one, two or three interrupt control units, each has 64 + * interrupts. If there is no second or third unit then MCFINTC1_* or + * MCFINTC2_* defines will be 0 (and code for them optimized away). + */ + +static void intc_irq_mask(struct irq_data *d) +{ + unsigned int irq = d->irq - MCFINT_VECBASE; + + if (MCFINTC2_SIMR && (irq > 128)) + __raw_writeb(irq - 128, MCFINTC2_SIMR); + else if (MCFINTC1_SIMR && (irq > 64)) + __raw_writeb(irq - 64, MCFINTC1_SIMR); + else + __raw_writeb(irq, MCFINTC0_SIMR); +} + +static void intc_irq_unmask(struct irq_data *d) +{ + unsigned int irq = d->irq - MCFINT_VECBASE; + + if (MCFINTC2_CIMR && (irq > 128)) + __raw_writeb(irq - 128, MCFINTC2_CIMR); + else if (MCFINTC1_CIMR && (irq > 64)) + __raw_writeb(irq - 64, MCFINTC1_CIMR); + else + __raw_writeb(irq, MCFINTC0_CIMR); +} + +static void intc_irq_ack(struct irq_data *d) +{ + unsigned int ebit = irq2ebit(d->irq); + + __raw_writeb(0x1 << ebit, MCFEPORT_EPFR); +} + +static unsigned int intc_irq_startup(struct irq_data *d) +{ + unsigned int irq = d->irq; + + if ((irq >= EINT1) && (irq <= EINT7)) { + unsigned int ebit = irq2ebit(irq); + u8 v; + +#if defined(MCFEPORT_EPDDR) + /* Set EPORT line as input */ + v = __raw_readb(MCFEPORT_EPDDR); + __raw_writeb(v & ~(0x1 << ebit), MCFEPORT_EPDDR); +#endif + + /* Set EPORT line as interrupt source */ + v = __raw_readb(MCFEPORT_EPIER); + __raw_writeb(v | (0x1 << ebit), MCFEPORT_EPIER); + } + + irq -= MCFINT_VECBASE; + if (MCFINTC2_ICR0 && (irq > 128)) + __raw_writeb(5, MCFINTC2_ICR0 + irq - 128); + else if (MCFINTC1_ICR0 && (irq > 64)) + __raw_writeb(5, MCFINTC1_ICR0 + irq - 64); + else + __raw_writeb(5, MCFINTC0_ICR0 + irq); + + intc_irq_unmask(d); + return 0; +} + +static int intc_irq_set_type(struct irq_data *d, unsigned int type) +{ + unsigned int ebit, irq = d->irq; + u16 pa, tb; + + switch (type) { + case IRQ_TYPE_EDGE_RISING: + tb = 0x1; + break; + case IRQ_TYPE_EDGE_FALLING: + tb = 0x2; + break; + case IRQ_TYPE_EDGE_BOTH: + tb = 0x3; + break; + default: + /* Level triggered */ + tb = 0; + break; + } + + if (tb) + irq_set_handler(irq, handle_edge_irq); + + ebit = irq2ebit(irq) * 2; + pa = __raw_readw(MCFEPORT_EPPAR); + pa = (pa & ~(0x3 << ebit)) | (tb << ebit); + __raw_writew(pa, MCFEPORT_EPPAR); + + return 0; +} + +static struct irq_chip intc_irq_chip = { + .name = "CF-INTC", + .irq_startup = intc_irq_startup, + .irq_mask = intc_irq_mask, + .irq_unmask = intc_irq_unmask, +}; + +static struct irq_chip intc_irq_chip_edge_port = { + .name = "CF-INTC-EP", + .irq_startup = intc_irq_startup, + .irq_mask = intc_irq_mask, + .irq_unmask = intc_irq_unmask, + .irq_ack = intc_irq_ack, + .irq_set_type = intc_irq_set_type, +}; + +void __init init_IRQ(void) +{ + int irq, eirq; + + /* Mask all interrupt sources */ + __raw_writeb(0xff, MCFINTC0_SIMR); + if (MCFINTC1_SIMR) + __raw_writeb(0xff, MCFINTC1_SIMR); + if (MCFINTC2_SIMR) + __raw_writeb(0xff, MCFINTC2_SIMR); + + eirq = MCFINT_VECBASE + 64 + (MCFINTC1_ICR0 ? 64 : 0) + + (MCFINTC2_ICR0 ? 64 : 0); + for (irq = MCFINT_VECBASE; (irq < eirq); irq++) { + if ((irq >= EINT1) && (irq <= EINT7)) + irq_set_chip(irq, &intc_irq_chip_edge_port); + else + irq_set_chip(irq, &intc_irq_chip); + irq_set_irq_type(irq, IRQ_TYPE_LEVEL_HIGH); + irq_set_handler(irq, handle_level_irq); + } +} + diff --git a/arch/m68k/coldfire/intc.c b/arch/m68k/coldfire/intc.c new file mode 100644 index 000000000..cce257420 --- /dev/null +++ b/arch/m68k/coldfire/intc.c @@ -0,0 +1,150 @@ +/* + * intc.c -- support for the old ColdFire interrupt controller + * + * (C) Copyright 2009, Greg Ungerer + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file COPYING in the main directory of this archive + * for more details. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* + * The mapping of irq number to a mask register bit is not one-to-one. + * The irq numbers are either based on "level" of interrupt or fixed + * for an autovector-able interrupt. So we keep a local data structure + * that maps from irq to mask register. Not all interrupts will have + * an IMR bit. + */ +unsigned char mcf_irq2imr[NR_IRQS]; + +/* + * Define the miniumun and maximum external interrupt numbers. + * This is also used as the "level" interrupt numbers. + */ +#define EIRQ1 25 +#define EIRQ7 31 + +/* + * In the early version 2 core ColdFire parts the IMR register was 16 bits + * in size. Version 3 (and later version 2) core parts have a 32 bit + * sized IMR register. Provide some size independent methods to access the + * IMR register. + */ +#ifdef MCFSIM_IMR_IS_16BITS + +void mcf_setimr(int index) +{ + u16 imr; + imr = __raw_readw(MCFSIM_IMR); + __raw_writew(imr | (0x1 << index), MCFSIM_IMR); +} + +void mcf_clrimr(int index) +{ + u16 imr; + imr = __raw_readw(MCFSIM_IMR); + __raw_writew(imr & ~(0x1 << index), MCFSIM_IMR); +} + +void mcf_maskimr(unsigned int mask) +{ + u16 imr; + imr = __raw_readw(MCFSIM_IMR); + imr |= mask; + __raw_writew(imr, MCFSIM_IMR); +} + +#else + +void mcf_setimr(int index) +{ + u32 imr; + imr = __raw_readl(MCFSIM_IMR); + __raw_writel(imr | (0x1 << index), MCFSIM_IMR); +} + +void mcf_clrimr(int index) +{ + u32 imr; + imr = __raw_readl(MCFSIM_IMR); + __raw_writel(imr & ~(0x1 << index), MCFSIM_IMR); +} + +void mcf_maskimr(unsigned int mask) +{ + u32 imr; + imr = __raw_readl(MCFSIM_IMR); + imr |= mask; + __raw_writel(imr, MCFSIM_IMR); +} + +#endif + +/* + * Interrupts can be "vectored" on the ColdFire cores that support this old + * interrupt controller. That is, the device raising the interrupt can also + * supply the vector number to interrupt through. The AVR register of the + * interrupt controller enables or disables this for each external interrupt, + * so provide generic support for this. Setting this up is out-of-band for + * the interrupt system API's, and needs to be done by the driver that + * supports this device. Very few devices actually use this. + */ +void mcf_autovector(int irq) +{ +#ifdef MCFSIM_AVR + if ((irq >= EIRQ1) && (irq <= EIRQ7)) { + u8 avec; + avec = __raw_readb(MCFSIM_AVR); + avec |= (0x1 << (irq - EIRQ1 + 1)); + __raw_writeb(avec, MCFSIM_AVR); + } +#endif +} + +static void intc_irq_mask(struct irq_data *d) +{ + if (mcf_irq2imr[d->irq]) + mcf_setimr(mcf_irq2imr[d->irq]); +} + +static void intc_irq_unmask(struct irq_data *d) +{ + if (mcf_irq2imr[d->irq]) + mcf_clrimr(mcf_irq2imr[d->irq]); +} + +static int intc_irq_set_type(struct irq_data *d, unsigned int type) +{ + return 0; +} + +static struct irq_chip intc_irq_chip = { + .name = "CF-INTC", + .irq_mask = intc_irq_mask, + .irq_unmask = intc_irq_unmask, + .irq_set_type = intc_irq_set_type, +}; + +void __init init_IRQ(void) +{ + int irq; + + mcf_maskimr(0xffffffff); + + for (irq = 0; (irq < NR_IRQS); irq++) { + irq_set_chip(irq, &intc_irq_chip); + irq_set_irq_type(irq, IRQ_TYPE_LEVEL_HIGH); + irq_set_handler(irq, handle_level_irq); + } +} + diff --git a/arch/m68k/coldfire/m5206.c b/arch/m68k/coldfire/m5206.c new file mode 100644 index 000000000..2f14ea95c --- /dev/null +++ b/arch/m68k/coldfire/m5206.c @@ -0,0 +1,71 @@ +// SPDX-License-Identifier: GPL-2.0 +/***************************************************************************/ + +/* + * m5206.c -- platform support for ColdFire 5206 based boards + * + * Copyright (C) 1999-2002, Greg Ungerer (gerg@snapgear.com) + * Copyright (C) 2000-2001, Lineo Inc. (www.lineo.com) + */ + +/***************************************************************************/ + +#include +#include +#include +#include +#include +#include +#include +#include + +/***************************************************************************/ + +DEFINE_CLK(pll, "pll.0", MCF_CLK); +DEFINE_CLK(sys, "sys.0", MCF_BUSCLK); +DEFINE_CLK(mcftmr0, "mcftmr.0", MCF_BUSCLK); +DEFINE_CLK(mcftmr1, "mcftmr.1", MCF_BUSCLK); +DEFINE_CLK(mcfuart0, "mcfuart.0", MCF_BUSCLK); +DEFINE_CLK(mcfuart1, "mcfuart.1", MCF_BUSCLK); +DEFINE_CLK(mcfi2c0, "imx1-i2c.0", MCF_BUSCLK); + +struct clk *mcf_clks[] = { + &clk_pll, + &clk_sys, + &clk_mcftmr0, + &clk_mcftmr1, + &clk_mcfuart0, + &clk_mcfuart1, + &clk_mcfi2c0, + NULL +}; + +/***************************************************************************/ + +static void __init m5206_i2c_init(void) +{ +#if IS_ENABLED(CONFIG_I2C_IMX) + writeb(MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL5 | MCFSIM_ICR_PRI0, + MCFSIM_I2CICR); + mcf_mapirq2imr(MCF_IRQ_I2C0, MCFINTC_I2C); +#endif /* IS_ENABLED(CONFIG_I2C_IMX) */ +} + +void __init config_BSP(char *commandp, int size) +{ +#if defined(CONFIG_NETtel) + /* Copy command line from FLASH to local buffer... */ + memcpy(commandp, (char *) 0xf0004000, size); + commandp[size-1] = 0; +#endif /* CONFIG_NETtel */ + + mach_sched_init = hw_timer_init; + + /* Only support the external interrupts on their primary level */ + mcf_mapirq2imr(25, MCFINTC_EINT1); + mcf_mapirq2imr(28, MCFINTC_EINT4); + mcf_mapirq2imr(31, MCFINTC_EINT7); + m5206_i2c_init(); +} + +/***************************************************************************/ diff --git a/arch/m68k/coldfire/m520x.c b/arch/m68k/coldfire/m520x.c new file mode 100644 index 000000000..b5b2a267d --- /dev/null +++ b/arch/m68k/coldfire/m520x.c @@ -0,0 +1,197 @@ +// SPDX-License-Identifier: GPL-2.0 +/***************************************************************************/ + +/* + * m520x.c -- platform support for ColdFire 520x based boards + * + * Copyright (C) 2005, Freescale (www.freescale.com) + * Copyright (C) 2005, Intec Automation (mike@steroidmicros.com) + * Copyright (C) 1999-2007, Greg Ungerer (gerg@snapgear.com) + * Copyright (C) 2001-2003, SnapGear Inc. (www.snapgear.com) + */ + +/***************************************************************************/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/***************************************************************************/ + +DEFINE_CLK(0, "flexbus", 2, MCF_CLK); +DEFINE_CLK(0, "fec.0", 12, MCF_CLK); +DEFINE_CLK(0, "edma", 17, MCF_CLK); +DEFINE_CLK(0, "intc.0", 18, MCF_CLK); +DEFINE_CLK(0, "iack.0", 21, MCF_CLK); +DEFINE_CLK(0, "imx1-i2c.0", 22, MCF_CLK); +DEFINE_CLK(0, "mcfqspi.0", 23, MCF_CLK); +DEFINE_CLK(0, "mcfuart.0", 24, MCF_BUSCLK); +DEFINE_CLK(0, "mcfuart.1", 25, MCF_BUSCLK); +DEFINE_CLK(0, "mcfuart.2", 26, MCF_BUSCLK); +DEFINE_CLK(0, "mcftmr.0", 28, MCF_CLK); +DEFINE_CLK(0, "mcftmr.1", 29, MCF_CLK); +DEFINE_CLK(0, "mcftmr.2", 30, MCF_CLK); +DEFINE_CLK(0, "mcftmr.3", 31, MCF_CLK); + +DEFINE_CLK(0, "mcfpit.0", 32, MCF_CLK); +DEFINE_CLK(0, "mcfpit.1", 33, MCF_CLK); +DEFINE_CLK(0, "mcfeport.0", 34, MCF_CLK); +DEFINE_CLK(0, "mcfwdt.0", 35, MCF_CLK); +DEFINE_CLK(0, "pll.0", 36, MCF_CLK); +DEFINE_CLK(0, "sys.0", 40, MCF_BUSCLK); +DEFINE_CLK(0, "gpio.0", 41, MCF_BUSCLK); +DEFINE_CLK(0, "sdram.0", 42, MCF_CLK); + +struct clk *mcf_clks[] = { + &__clk_0_2, /* flexbus */ + &__clk_0_12, /* fec.0 */ + &__clk_0_17, /* edma */ + &__clk_0_18, /* intc.0 */ + &__clk_0_21, /* iack.0 */ + &__clk_0_22, /* imx1-i2c.0 */ + &__clk_0_23, /* mcfqspi.0 */ + &__clk_0_24, /* mcfuart.0 */ + &__clk_0_25, /* mcfuart.1 */ + &__clk_0_26, /* mcfuart.2 */ + &__clk_0_28, /* mcftmr.0 */ + &__clk_0_29, /* mcftmr.1 */ + &__clk_0_30, /* mcftmr.2 */ + &__clk_0_31, /* mcftmr.3 */ + + &__clk_0_32, /* mcfpit.0 */ + &__clk_0_33, /* mcfpit.1 */ + &__clk_0_34, /* mcfeport.0 */ + &__clk_0_35, /* mcfwdt.0 */ + &__clk_0_36, /* pll.0 */ + &__clk_0_40, /* sys.0 */ + &__clk_0_41, /* gpio.0 */ + &__clk_0_42, /* sdram.0 */ + NULL, +}; + +static struct clk * const enable_clks[] __initconst = { + &__clk_0_2, /* flexbus */ + &__clk_0_18, /* intc.0 */ + &__clk_0_21, /* iack.0 */ + &__clk_0_24, /* mcfuart.0 */ + &__clk_0_25, /* mcfuart.1 */ + &__clk_0_26, /* mcfuart.2 */ + + &__clk_0_32, /* mcfpit.0 */ + &__clk_0_33, /* mcfpit.1 */ + &__clk_0_34, /* mcfeport.0 */ + &__clk_0_36, /* pll.0 */ + &__clk_0_40, /* sys.0 */ + &__clk_0_41, /* gpio.0 */ + &__clk_0_42, /* sdram.0 */ +}; + +static struct clk * const disable_clks[] __initconst = { + &__clk_0_12, /* fec.0 */ + &__clk_0_17, /* edma */ + &__clk_0_22, /* imx1-i2c.0 */ + &__clk_0_23, /* mcfqspi.0 */ + &__clk_0_28, /* mcftmr.0 */ + &__clk_0_29, /* mcftmr.1 */ + &__clk_0_30, /* mcftmr.2 */ + &__clk_0_31, /* mcftmr.3 */ + &__clk_0_35, /* mcfwdt.0 */ +}; + + +static void __init m520x_clk_init(void) +{ + unsigned i; + + /* make sure these clocks are enabled */ + for (i = 0; i < ARRAY_SIZE(enable_clks); ++i) + __clk_init_enabled(enable_clks[i]); + /* make sure these clocks are disabled */ + for (i = 0; i < ARRAY_SIZE(disable_clks); ++i) + __clk_init_disabled(disable_clks[i]); +} + +/***************************************************************************/ + +static void __init m520x_qspi_init(void) +{ +#if IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI) + u16 par; + /* setup Port QS for QSPI with gpio CS control */ + writeb(0x3f, MCF_GPIO_PAR_QSPI); + /* make U1CTS and U2RTS gpio for cs_control */ + par = readw(MCF_GPIO_PAR_UART); + par &= 0x00ff; + writew(par, MCF_GPIO_PAR_UART); +#endif /* IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI) */ +} + +/***************************************************************************/ + +static void __init m520x_i2c_init(void) +{ +#if IS_ENABLED(CONFIG_I2C_IMX) + u8 par; + + /* setup Port FECI2C Pin Assignment Register for I2C */ + /* set PAR_SCL to SCL and PAR_SDA to SDA */ + par = readb(MCF_GPIO_PAR_FECI2C); + par |= 0x0f; + writeb(par, MCF_GPIO_PAR_FECI2C); +#endif /* IS_ENABLED(CONFIG_I2C_IMX) */ +} + +/***************************************************************************/ + +static void __init m520x_uarts_init(void) +{ + u16 par; + u8 par2; + + /* UART0 and UART1 GPIO pin setup */ + par = readw(MCF_GPIO_PAR_UART); + par |= MCF_GPIO_PAR_UART_PAR_UTXD0 | MCF_GPIO_PAR_UART_PAR_URXD0; + par |= MCF_GPIO_PAR_UART_PAR_UTXD1 | MCF_GPIO_PAR_UART_PAR_URXD1; + writew(par, MCF_GPIO_PAR_UART); + + /* UART1 GPIO pin setup */ + par2 = readb(MCF_GPIO_PAR_FECI2C); + par2 &= ~0x0F; + par2 |= MCF_GPIO_PAR_FECI2C_PAR_SCL_UTXD2 | + MCF_GPIO_PAR_FECI2C_PAR_SDA_URXD2; + writeb(par2, MCF_GPIO_PAR_FECI2C); +} + +/***************************************************************************/ + +static void __init m520x_fec_init(void) +{ + u8 v; + + /* Set multi-function pins to ethernet mode */ + v = readb(MCF_GPIO_PAR_FEC); + writeb(v | 0xf0, MCF_GPIO_PAR_FEC); + + v = readb(MCF_GPIO_PAR_FECI2C); + writeb(v | 0x0f, MCF_GPIO_PAR_FECI2C); +} + +/***************************************************************************/ + +void __init config_BSP(char *commandp, int size) +{ + mach_sched_init = hw_timer_init; + m520x_clk_init(); + m520x_uarts_init(); + m520x_fec_init(); + m520x_qspi_init(); + m520x_i2c_init(); +} + +/***************************************************************************/ diff --git a/arch/m68k/coldfire/m523x.c b/arch/m68k/coldfire/m523x.c new file mode 100644 index 000000000..ddf2496ed --- /dev/null +++ b/arch/m68k/coldfire/m523x.c @@ -0,0 +1,105 @@ +// SPDX-License-Identifier: GPL-2.0 +/***************************************************************************/ + +/* + * m523x.c -- platform support for ColdFire 523x based boards + * + * Sub-architcture dependent initialization code for the Freescale + * 523x CPUs. + * + * Copyright (C) 1999-2005, Greg Ungerer (gerg@snapgear.com) + * Copyright (C) 2001-2003, SnapGear Inc. (www.snapgear.com) + */ + +/***************************************************************************/ + +#include +#include +#include +#include +#include +#include +#include +#include + +/***************************************************************************/ + +DEFINE_CLK(pll, "pll.0", MCF_CLK); +DEFINE_CLK(sys, "sys.0", MCF_BUSCLK); +DEFINE_CLK(mcfpit0, "mcfpit.0", MCF_CLK); +DEFINE_CLK(mcfpit1, "mcfpit.1", MCF_CLK); +DEFINE_CLK(mcfpit2, "mcfpit.2", MCF_CLK); +DEFINE_CLK(mcfpit3, "mcfpit.3", MCF_CLK); +DEFINE_CLK(mcfuart0, "mcfuart.0", MCF_BUSCLK); +DEFINE_CLK(mcfuart1, "mcfuart.1", MCF_BUSCLK); +DEFINE_CLK(mcfuart2, "mcfuart.2", MCF_BUSCLK); +DEFINE_CLK(mcfqspi0, "mcfqspi.0", MCF_BUSCLK); +DEFINE_CLK(fec0, "fec.0", MCF_BUSCLK); +DEFINE_CLK(mcfi2c0, "imx1-i2c.0", MCF_BUSCLK); + +struct clk *mcf_clks[] = { + &clk_pll, + &clk_sys, + &clk_mcfpit0, + &clk_mcfpit1, + &clk_mcfpit2, + &clk_mcfpit3, + &clk_mcfuart0, + &clk_mcfuart1, + &clk_mcfuart2, + &clk_mcfqspi0, + &clk_fec0, + &clk_mcfi2c0, + NULL +}; + +/***************************************************************************/ + +static void __init m523x_qspi_init(void) +{ +#if IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI) + u16 par; + + /* setup QSPS pins for QSPI with gpio CS control */ + writeb(0x1f, MCFGPIO_PAR_QSPI); + /* and CS2 & CS3 as gpio */ + par = readw(MCFGPIO_PAR_TIMER); + par &= 0x3f3f; + writew(par, MCFGPIO_PAR_TIMER); +#endif /* IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI) */ +} + +/***************************************************************************/ + +static void __init m523x_i2c_init(void) +{ +#if IS_ENABLED(CONFIG_I2C_IMX) + u8 par; + + /* setup Port AS Pin Assignment Register for I2C */ + /* set PASPA0 to SCL and PASPA1 to SDA */ + par = readb(MCFGPIO_PAR_FECI2C); + par |= 0x0f; + writeb(par, MCFGPIO_PAR_FECI2C); +#endif /* IS_ENABLED(CONFIG_I2C_IMX) */ +} + +/***************************************************************************/ + +static void __init m523x_fec_init(void) +{ + /* Set multi-function pins to ethernet use */ + writeb(readb(MCFGPIO_PAR_FECI2C) | 0xf0, MCFGPIO_PAR_FECI2C); +} + +/***************************************************************************/ + +void __init config_BSP(char *commandp, int size) +{ + mach_sched_init = hw_timer_init; + m523x_fec_init(); + m523x_qspi_init(); + m523x_i2c_init(); +} + +/***************************************************************************/ diff --git a/arch/m68k/coldfire/m5249.c b/arch/m68k/coldfire/m5249.c new file mode 100644 index 000000000..0590f8c42 --- /dev/null +++ b/arch/m68k/coldfire/m5249.c @@ -0,0 +1,152 @@ +// SPDX-License-Identifier: GPL-2.0 +/***************************************************************************/ + +/* + * m5249.c -- platform support for ColdFire 5249 based boards + * + * Copyright (C) 2002, Greg Ungerer (gerg@snapgear.com) + */ + +/***************************************************************************/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/***************************************************************************/ + +DEFINE_CLK(pll, "pll.0", MCF_CLK); +DEFINE_CLK(sys, "sys.0", MCF_BUSCLK); +DEFINE_CLK(mcftmr0, "mcftmr.0", MCF_BUSCLK); +DEFINE_CLK(mcftmr1, "mcftmr.1", MCF_BUSCLK); +DEFINE_CLK(mcfuart0, "mcfuart.0", MCF_BUSCLK); +DEFINE_CLK(mcfuart1, "mcfuart.1", MCF_BUSCLK); +DEFINE_CLK(mcfqspi0, "mcfqspi.0", MCF_BUSCLK); +DEFINE_CLK(mcfi2c0, "imx1-i2c.0", MCF_BUSCLK); +DEFINE_CLK(mcfi2c1, "imx1-i2c.1", MCF_BUSCLK); + +struct clk *mcf_clks[] = { + &clk_pll, + &clk_sys, + &clk_mcftmr0, + &clk_mcftmr1, + &clk_mcfuart0, + &clk_mcfuart1, + &clk_mcfqspi0, + &clk_mcfi2c0, + &clk_mcfi2c1, + NULL +}; + +/***************************************************************************/ + +#ifdef CONFIG_M5249C3 + +static struct resource m5249_smc91x_resources[] = { + { + .start = 0xe0000300, + .end = 0xe0000300 + 0x100, + .flags = IORESOURCE_MEM, + }, + { + .start = MCF_IRQ_GPIO6, + .end = MCF_IRQ_GPIO6, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device m5249_smc91x = { + .name = "smc91x", + .id = 0, + .num_resources = ARRAY_SIZE(m5249_smc91x_resources), + .resource = m5249_smc91x_resources, +}; + +#endif /* CONFIG_M5249C3 */ + +static struct platform_device *m5249_devices[] __initdata = { +#ifdef CONFIG_M5249C3 + &m5249_smc91x, +#endif +}; + +/***************************************************************************/ + +static void __init m5249_qspi_init(void) +{ +#if IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI) + /* QSPI irq setup */ + writeb(MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL4 | MCFSIM_ICR_PRI0, + MCFSIM_QSPIICR); + mcf_mapirq2imr(MCF_IRQ_QSPI, MCFINTC_QSPI); +#endif /* IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI) */ +} + +/***************************************************************************/ + +static void __init m5249_i2c_init(void) +{ +#if IS_ENABLED(CONFIG_I2C_IMX) + u32 r; + + /* first I2C controller uses regular irq setup */ + writeb(MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL5 | MCFSIM_ICR_PRI0, + MCFSIM_I2CICR); + mcf_mapirq2imr(MCF_IRQ_I2C0, MCFINTC_I2C); + + /* second I2C controller is completely different */ + r = readl(MCFINTC2_INTPRI_REG(MCF_IRQ_I2C1)); + r &= ~MCFINTC2_INTPRI_BITS(0xf, MCF_IRQ_I2C1); + r |= MCFINTC2_INTPRI_BITS(0x5, MCF_IRQ_I2C1); + writel(r, MCFINTC2_INTPRI_REG(MCF_IRQ_I2C1)); +#endif /* CONFIG_I2C_IMX */ +} + +/***************************************************************************/ + +#ifdef CONFIG_M5249C3 + +static void __init m5249_smc91x_init(void) +{ + u32 gpio; + + /* Set the GPIO line as interrupt source for smc91x device */ + gpio = readl(MCFSIM2_GPIOINTENABLE); + writel(gpio | 0x40, MCFSIM2_GPIOINTENABLE); + + gpio = readl(MCFINTC2_INTPRI5); + writel(gpio | 0x04000000, MCFINTC2_INTPRI5); +} + +#endif /* CONFIG_M5249C3 */ + +/***************************************************************************/ + +void __init config_BSP(char *commandp, int size) +{ + mach_sched_init = hw_timer_init; + +#ifdef CONFIG_M5249C3 + m5249_smc91x_init(); +#endif + m5249_qspi_init(); + m5249_i2c_init(); +} + +/***************************************************************************/ + +static int __init init_BSP(void) +{ + platform_add_devices(m5249_devices, ARRAY_SIZE(m5249_devices)); + return 0; +} + +arch_initcall(init_BSP); + +/***************************************************************************/ diff --git a/arch/m68k/coldfire/m525x.c b/arch/m68k/coldfire/m525x.c new file mode 100644 index 000000000..1772359c4 --- /dev/null +++ b/arch/m68k/coldfire/m525x.c @@ -0,0 +1,93 @@ +// SPDX-License-Identifier: GPL-2.0 +/***************************************************************************/ + +/* + * 525x.c -- platform support for ColdFire 525x based boards + * + * Copyright (C) 2012, Steven King + */ + +/***************************************************************************/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/***************************************************************************/ + +DEFINE_CLK(pll, "pll.0", MCF_CLK); +DEFINE_CLK(sys, "sys.0", MCF_BUSCLK); +DEFINE_CLK(mcftmr0, "mcftmr.0", MCF_BUSCLK); +DEFINE_CLK(mcftmr1, "mcftmr.1", MCF_BUSCLK); +DEFINE_CLK(mcfuart0, "mcfuart.0", MCF_BUSCLK); +DEFINE_CLK(mcfuart1, "mcfuart.1", MCF_BUSCLK); +DEFINE_CLK(mcfqspi0, "mcfqspi.0", MCF_BUSCLK); +DEFINE_CLK(mcfi2c0, "imx1-i2c.0", MCF_BUSCLK); +DEFINE_CLK(mcfi2c1, "imx1-i2c.1", MCF_BUSCLK); + +struct clk *mcf_clks[] = { + &clk_pll, + &clk_sys, + &clk_mcftmr0, + &clk_mcftmr1, + &clk_mcfuart0, + &clk_mcfuart1, + &clk_mcfqspi0, + &clk_mcfi2c0, + &clk_mcfi2c1, + NULL +}; + +/***************************************************************************/ + +static void __init m525x_qspi_init(void) +{ +#if IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI) + /* set the GPIO function for the qspi cs gpios */ + /* FIXME: replace with pinmux/pinctl support */ + u32 f = readl(MCFSIM2_GPIOFUNC); + f |= (1 << MCFQSPI_CS2) | (1 << MCFQSPI_CS1) | (1 << MCFQSPI_CS0); + writel(f, MCFSIM2_GPIOFUNC); + + /* QSPI irq setup */ + writeb(MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL4 | MCFSIM_ICR_PRI0, + MCFSIM_QSPIICR); + mcf_mapirq2imr(MCF_IRQ_QSPI, MCFINTC_QSPI); +#endif /* IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI) */ +} + +static void __init m525x_i2c_init(void) +{ +#if IS_ENABLED(CONFIG_I2C_IMX) + u32 r; + + /* first I2C controller uses regular irq setup */ + writeb(MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL5 | MCFSIM_ICR_PRI0, + MCFSIM_I2CICR); + mcf_mapirq2imr(MCF_IRQ_I2C0, MCFINTC_I2C); + + /* second I2C controller is completely different */ + r = readl(MCFINTC2_INTPRI_REG(MCF_IRQ_I2C1)); + r &= ~MCFINTC2_INTPRI_BITS(0xf, MCF_IRQ_I2C1); + r |= MCFINTC2_INTPRI_BITS(0x5, MCF_IRQ_I2C1); + writel(r, MCFINTC2_INTPRI_REG(MCF_IRQ_I2C1)); +#endif /* IS_ENABLED(CONFIG_I2C_IMX) */ +} + +/***************************************************************************/ + +void __init config_BSP(char *commandp, int size) +{ + mach_sched_init = hw_timer_init; + + m525x_qspi_init(); + m525x_i2c_init(); +} + +/***************************************************************************/ diff --git a/arch/m68k/coldfire/m5272.c b/arch/m68k/coldfire/m5272.c new file mode 100644 index 000000000..6b3ab583c --- /dev/null +++ b/arch/m68k/coldfire/m5272.c @@ -0,0 +1,136 @@ +// SPDX-License-Identifier: GPL-2.0 +/***************************************************************************/ + +/* + * m5272.c -- platform support for ColdFire 5272 based boards + * + * Copyright (C) 1999-2002, Greg Ungerer (gerg@snapgear.com) + * Copyright (C) 2001-2002, SnapGear Inc. (www.snapgear.com) + */ + +/***************************************************************************/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/***************************************************************************/ + +/* + * Some platforms need software versions of the GPIO data registers. + */ +unsigned short ppdata; +unsigned char ledbank = 0xff; + +/***************************************************************************/ + +DEFINE_CLK(pll, "pll.0", MCF_CLK); +DEFINE_CLK(sys, "sys.0", MCF_BUSCLK); +DEFINE_CLK(mcftmr0, "mcftmr.0", MCF_BUSCLK); +DEFINE_CLK(mcftmr1, "mcftmr.1", MCF_BUSCLK); +DEFINE_CLK(mcftmr2, "mcftmr.2", MCF_BUSCLK); +DEFINE_CLK(mcftmr3, "mcftmr.3", MCF_BUSCLK); +DEFINE_CLK(mcfuart0, "mcfuart.0", MCF_BUSCLK); +DEFINE_CLK(mcfuart1, "mcfuart.1", MCF_BUSCLK); +DEFINE_CLK(mcfqspi0, "mcfqspi.0", MCF_BUSCLK); +DEFINE_CLK(fec0, "fec.0", MCF_BUSCLK); + +struct clk *mcf_clks[] = { + &clk_pll, + &clk_sys, + &clk_mcftmr0, + &clk_mcftmr1, + &clk_mcftmr2, + &clk_mcftmr3, + &clk_mcfuart0, + &clk_mcfuart1, + &clk_mcfqspi0, + &clk_fec0, + NULL +}; + +/***************************************************************************/ + +static void __init m5272_uarts_init(void) +{ + u32 v; + + /* Enable the output lines for the serial ports */ + v = readl(MCFSIM_PBCNT); + v = (v & ~0x000000ff) | 0x00000055; + writel(v, MCFSIM_PBCNT); + + v = readl(MCFSIM_PDCNT); + v = (v & ~0x000003fc) | 0x000002a8; + writel(v, MCFSIM_PDCNT); +} + +/***************************************************************************/ + +static void m5272_cpu_reset(void) +{ + local_irq_disable(); + /* Set watchdog to reset, and enabled */ + __raw_writew(0, MCFSIM_WIRR); + __raw_writew(1, MCFSIM_WRRR); + __raw_writew(0, MCFSIM_WCR); + for (;;) + /* wait for watchdog to timeout */; +} + +/***************************************************************************/ + +void __init config_BSP(char *commandp, int size) +{ +#if defined (CONFIG_MOD5272) + /* Set base of device vectors to be 64 */ + writeb(0x40, MCFSIM_PIVR); +#endif + +#if defined(CONFIG_NETtel) || defined(CONFIG_SCALES) + /* Copy command line from FLASH to local buffer... */ + memcpy(commandp, (char *) 0xf0004000, size); + commandp[size-1] = 0; +#elif defined(CONFIG_CANCam) + /* Copy command line from FLASH to local buffer... */ + memcpy(commandp, (char *) 0xf0010000, size); + commandp[size-1] = 0; +#endif + + mach_reset = m5272_cpu_reset; + mach_sched_init = hw_timer_init; +} + +/***************************************************************************/ + +/* + * Some 5272 based boards have the FEC ethernet directly connected to + * an ethernet switch. In this case we need to use the fixed phy type, + * and we need to declare it early in boot. + */ +static struct fixed_phy_status nettel_fixed_phy_status __initdata = { + .link = 1, + .speed = 100, + .duplex = 0, +}; + +/***************************************************************************/ + +static int __init init_BSP(void) +{ + m5272_uarts_init(); + fixed_phy_add(PHY_POLL, 0, &nettel_fixed_phy_status); + return 0; +} + +arch_initcall(init_BSP); + +/***************************************************************************/ diff --git a/arch/m68k/coldfire/m527x.c b/arch/m68k/coldfire/m527x.c new file mode 100644 index 000000000..cad462df6 --- /dev/null +++ b/arch/m68k/coldfire/m527x.c @@ -0,0 +1,156 @@ +// SPDX-License-Identifier: GPL-2.0 +/***************************************************************************/ + +/* + * m527x.c -- platform support for ColdFire 527x based boards + * + * Sub-architcture dependent initialization code for the Freescale + * 5270/5271 and 5274/5275 CPUs. + * + * Copyright (C) 1999-2004, Greg Ungerer (gerg@snapgear.com) + * Copyright (C) 2001-2004, SnapGear Inc. (www.snapgear.com) + */ + +/***************************************************************************/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/***************************************************************************/ + +DEFINE_CLK(pll, "pll.0", MCF_CLK); +DEFINE_CLK(sys, "sys.0", MCF_BUSCLK); +DEFINE_CLK(mcfpit0, "mcfpit.0", MCF_CLK); +DEFINE_CLK(mcfpit1, "mcfpit.1", MCF_CLK); +DEFINE_CLK(mcfpit2, "mcfpit.2", MCF_CLK); +DEFINE_CLK(mcfpit3, "mcfpit.3", MCF_CLK); +DEFINE_CLK(mcfuart0, "mcfuart.0", MCF_BUSCLK); +DEFINE_CLK(mcfuart1, "mcfuart.1", MCF_BUSCLK); +DEFINE_CLK(mcfuart2, "mcfuart.2", MCF_BUSCLK); +DEFINE_CLK(mcfqspi0, "mcfqspi.0", MCF_BUSCLK); +DEFINE_CLK(fec0, "fec.0", MCF_BUSCLK); +DEFINE_CLK(fec1, "fec.1", MCF_BUSCLK); +DEFINE_CLK(mcfi2c0, "imx1-i2c.0", MCF_BUSCLK); + +struct clk *mcf_clks[] = { + &clk_pll, + &clk_sys, + &clk_mcfpit0, + &clk_mcfpit1, + &clk_mcfpit2, + &clk_mcfpit3, + &clk_mcfuart0, + &clk_mcfuart1, + &clk_mcfuart2, + &clk_mcfqspi0, + &clk_fec0, + &clk_fec1, + &clk_mcfi2c0, + NULL +}; + +/***************************************************************************/ + +static void __init m527x_qspi_init(void) +{ +#if IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI) +#if defined(CONFIG_M5271) + u16 par; + + /* setup QSPS pins for QSPI with gpio CS control */ + writeb(0x1f, MCFGPIO_PAR_QSPI); + /* and CS2 & CS3 as gpio */ + par = readw(MCFGPIO_PAR_TIMER); + par &= 0x3f3f; + writew(par, MCFGPIO_PAR_TIMER); +#elif defined(CONFIG_M5275) + /* setup QSPS pins for QSPI with gpio CS control */ + writew(0x003e, MCFGPIO_PAR_QSPI); +#endif +#endif /* IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI) */ +} + +/***************************************************************************/ + +static void __init m527x_i2c_init(void) +{ +#if IS_ENABLED(CONFIG_I2C_IMX) +#if defined(CONFIG_M5271) + u8 par; + + /* setup Port FECI2C Pin Assignment Register for I2C */ + /* set PAR_SCL to SCL and PAR_SDA to SDA */ + par = readb(MCFGPIO_PAR_FECI2C); + par |= 0x0f; + writeb(par, MCFGPIO_PAR_FECI2C); +#elif defined(CONFIG_M5275) + u16 par; + + /* setup Port FECI2C Pin Assignment Register for I2C */ + /* set PAR_SCL to SCL and PAR_SDA to SDA */ + par = readw(MCFGPIO_PAR_FECI2C); + par |= 0x0f; + writew(par, MCFGPIO_PAR_FECI2C); +#endif +#endif /* IS_ENABLED(CONFIG_I2C_IMX) */ +} + +/***************************************************************************/ + +static void __init m527x_uarts_init(void) +{ + u16 sepmask; + + /* + * External Pin Mask Setting & Enable External Pin for Interface + */ + sepmask = readw(MCFGPIO_PAR_UART); + sepmask |= UART0_ENABLE_MASK | UART1_ENABLE_MASK | UART2_ENABLE_MASK; + writew(sepmask, MCFGPIO_PAR_UART); +} + +/***************************************************************************/ + +static void __init m527x_fec_init(void) +{ + u8 v; + + /* Set multi-function pins to ethernet mode for fec0 */ +#if defined(CONFIG_M5271) + v = readb(MCFGPIO_PAR_FECI2C); + writeb(v | 0xf0, MCFGPIO_PAR_FECI2C); +#else + u16 par; + + par = readw(MCFGPIO_PAR_FECI2C); + writew(par | 0xf00, MCFGPIO_PAR_FECI2C); + v = readb(MCFGPIO_PAR_FEC0HL); + writeb(v | 0xc0, MCFGPIO_PAR_FEC0HL); + + /* Set multi-function pins to ethernet mode for fec1 */ + par = readw(MCFGPIO_PAR_FECI2C); + writew(par | 0xa0, MCFGPIO_PAR_FECI2C); + v = readb(MCFGPIO_PAR_FEC1HL); + writeb(v | 0xc0, MCFGPIO_PAR_FEC1HL); +#endif +} + +/***************************************************************************/ + +void __init config_BSP(char *commandp, int size) +{ + mach_sched_init = hw_timer_init; + m527x_uarts_init(); + m527x_fec_init(); + m527x_qspi_init(); + m527x_i2c_init(); +} + +/***************************************************************************/ diff --git a/arch/m68k/coldfire/m528x.c b/arch/m68k/coldfire/m528x.c new file mode 100644 index 000000000..7ad319388 --- /dev/null +++ b/arch/m68k/coldfire/m528x.c @@ -0,0 +1,151 @@ +// SPDX-License-Identifier: GPL-2.0 +/***************************************************************************/ + +/* + * m528x.c -- platform support for ColdFire 528x based boards + * + * Sub-architcture dependent initialization code for the Freescale + * 5280, 5281 and 5282 CPUs. + * + * Copyright (C) 1999-2003, Greg Ungerer (gerg@snapgear.com) + * Copyright (C) 2001-2003, SnapGear Inc. (www.snapgear.com) + */ + +/***************************************************************************/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/***************************************************************************/ + +DEFINE_CLK(pll, "pll.0", MCF_CLK); +DEFINE_CLK(sys, "sys.0", MCF_BUSCLK); +DEFINE_CLK(mcfpit0, "mcfpit.0", MCF_CLK); +DEFINE_CLK(mcfpit1, "mcfpit.1", MCF_CLK); +DEFINE_CLK(mcfpit2, "mcfpit.2", MCF_CLK); +DEFINE_CLK(mcfpit3, "mcfpit.3", MCF_CLK); +DEFINE_CLK(mcfuart0, "mcfuart.0", MCF_BUSCLK); +DEFINE_CLK(mcfuart1, "mcfuart.1", MCF_BUSCLK); +DEFINE_CLK(mcfuart2, "mcfuart.2", MCF_BUSCLK); +DEFINE_CLK(mcfqspi0, "mcfqspi.0", MCF_BUSCLK); +DEFINE_CLK(fec0, "fec.0", MCF_BUSCLK); +DEFINE_CLK(mcfi2c0, "imx1-i2c.0", MCF_BUSCLK); + +struct clk *mcf_clks[] = { + &clk_pll, + &clk_sys, + &clk_mcfpit0, + &clk_mcfpit1, + &clk_mcfpit2, + &clk_mcfpit3, + &clk_mcfuart0, + &clk_mcfuart1, + &clk_mcfuart2, + &clk_mcfqspi0, + &clk_fec0, + &clk_mcfi2c0, + NULL +}; + +/***************************************************************************/ + +static void __init m528x_qspi_init(void) +{ +#if IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI) + /* setup Port QS for QSPI with gpio CS control */ + __raw_writeb(0x07, MCFGPIO_PQSPAR); +#endif /* IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI) */ +} + +/***************************************************************************/ + +static void __init m528x_i2c_init(void) +{ +#if IS_ENABLED(CONFIG_I2C_IMX) + u16 paspar; + + /* setup Port AS Pin Assignment Register for I2C */ + /* set PASPA0 to SCL and PASPA1 to SDA */ + paspar = readw(MCFGPIO_PASPAR); + paspar |= 0xF; + writew(paspar, MCFGPIO_PASPAR); +#endif /* IS_ENABLED(CONFIG_I2C_IMX) */ +} + +/***************************************************************************/ + +static void __init m528x_uarts_init(void) +{ + u8 port; + + /* make sure PUAPAR is set for UART0 and UART1 */ + port = readb(MCFGPIO_PUAPAR); + port |= 0x03 | (0x03 << 2); + writeb(port, MCFGPIO_PUAPAR); +} + +/***************************************************************************/ + +static void __init m528x_fec_init(void) +{ + u16 v16; + + /* Set multi-function pins to ethernet mode for fec0 */ + v16 = readw(MCFGPIO_PASPAR); + writew(v16 | 0xf00, MCFGPIO_PASPAR); + writeb(0xc0, MCFGPIO_PEHLPAR); +} + +/***************************************************************************/ + +#ifdef CONFIG_WILDFIRE +void wildfire_halt(void) +{ + writeb(0, 0x30000007); + writeb(0x2, 0x30000007); +} +#endif + +#ifdef CONFIG_WILDFIREMOD +void wildfiremod_halt(void) +{ + printk(KERN_INFO "WildFireMod hibernating...\n"); + + /* Set portE.5 to Digital IO */ + writew(readw(MCFGPIO_PEPAR) & ~(1 << (5 * 2)), MCFGPIO_PEPAR); + + /* Make portE.5 an output */ + writeb(readb(MCFGPIO_PDDR_E) | (1 << 5), MCFGPIO_PDDR_E); + + /* Now toggle portE.5 from low to high */ + writeb(readb(MCFGPIO_PODR_E) & ~(1 << 5), MCFGPIO_PODR_E); + writeb(readb(MCFGPIO_PODR_E) | (1 << 5), MCFGPIO_PODR_E); + + printk(KERN_EMERG "Failed to hibernate. Halting!\n"); +} +#endif + +void __init config_BSP(char *commandp, int size) +{ +#ifdef CONFIG_WILDFIRE + mach_halt = wildfire_halt; +#endif +#ifdef CONFIG_WILDFIREMOD + mach_halt = wildfiremod_halt; +#endif + mach_sched_init = hw_timer_init; + m528x_uarts_init(); + m528x_fec_init(); + m528x_qspi_init(); + m528x_i2c_init(); +} + +/***************************************************************************/ diff --git a/arch/m68k/coldfire/m5307.c b/arch/m68k/coldfire/m5307.c new file mode 100644 index 000000000..64b4b1fd3 --- /dev/null +++ b/arch/m68k/coldfire/m5307.c @@ -0,0 +1,93 @@ +// SPDX-License-Identifier: GPL-2.0 +/***************************************************************************/ + +/* + * m5307.c -- platform support for ColdFire 5307 based boards + * + * Copyright (C) 1999-2002, Greg Ungerer (gerg@snapgear.com) + * Copyright (C) 2000, Lineo (www.lineo.com) + */ + +/***************************************************************************/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/***************************************************************************/ + +/* + * Some platforms need software versions of the GPIO data registers. + */ +unsigned short ppdata; +unsigned char ledbank = 0xff; + +/***************************************************************************/ + +DEFINE_CLK(pll, "pll.0", MCF_CLK); +DEFINE_CLK(sys, "sys.0", MCF_BUSCLK); +DEFINE_CLK(mcftmr0, "mcftmr.0", MCF_BUSCLK); +DEFINE_CLK(mcftmr1, "mcftmr.1", MCF_BUSCLK); +DEFINE_CLK(mcfuart0, "mcfuart.0", MCF_BUSCLK); +DEFINE_CLK(mcfuart1, "mcfuart.1", MCF_BUSCLK); +DEFINE_CLK(mcfi2c0, "imx1-i2c.0", MCF_BUSCLK); + +struct clk *mcf_clks[] = { + &clk_pll, + &clk_sys, + &clk_mcftmr0, + &clk_mcftmr1, + &clk_mcfuart0, + &clk_mcfuart1, + &clk_mcfi2c0, + NULL +}; + +/***************************************************************************/ + +static void __init m5307_i2c_init(void) +{ +#if IS_ENABLED(CONFIG_I2C_IMX) + writeb(MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL5 | MCFSIM_ICR_PRI0, + MCFSIM_I2CICR); + mcf_mapirq2imr(MCF_IRQ_I2C0, MCFINTC_I2C); +#endif /* IS_ENABLED(CONFIG_I2C_IMX) */ +} + +/***************************************************************************/ + +void __init config_BSP(char *commandp, int size) +{ +#if defined(CONFIG_NETtel) || \ + defined(CONFIG_SECUREEDGEMP3) || defined(CONFIG_CLEOPATRA) + /* Copy command line from FLASH to local buffer... */ + memcpy(commandp, (char *) 0xf0004000, size); + commandp[size-1] = 0; +#endif + + mach_sched_init = hw_timer_init; + + /* Only support the external interrupts on their primary level */ + mcf_mapirq2imr(25, MCFINTC_EINT1); + mcf_mapirq2imr(27, MCFINTC_EINT3); + mcf_mapirq2imr(29, MCFINTC_EINT5); + mcf_mapirq2imr(31, MCFINTC_EINT7); + +#ifdef CONFIG_BDM_DISABLE + /* + * Disable the BDM clocking. This also turns off most of the rest of + * the BDM device. This is good for EMC reasons. This option is not + * incompatible with the memory protection option. + */ + wdebug(MCFDEBUG_CSR, MCFDEBUG_CSR_PSTCLK); +#endif + m5307_i2c_init(); +} + +/***************************************************************************/ diff --git a/arch/m68k/coldfire/m53xx.c b/arch/m68k/coldfire/m53xx.c new file mode 100644 index 000000000..075722c0c --- /dev/null +++ b/arch/m68k/coldfire/m53xx.c @@ -0,0 +1,594 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/***************************************************************************/ + +/* + * m53xx.c -- platform support for ColdFire 53xx based boards + * + * Copyright (C) 1999-2002, Greg Ungerer (gerg@snapgear.com) + * Copyright (C) 2000, Lineo (www.lineo.com) + * Yaroslav Vinogradov yaroslav.vinogradov@freescale.com + * Copyright Freescale Semiconductor, Inc 2006 + * Copyright (c) 2006, emlix, Sebastian Hess + */ + +/***************************************************************************/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/***************************************************************************/ + +DEFINE_CLK(0, "flexbus", 2, MCF_CLK); +DEFINE_CLK(0, "mcfcan.0", 8, MCF_CLK); +DEFINE_CLK(0, "fec.0", 12, MCF_CLK); +DEFINE_CLK(0, "edma", 17, MCF_CLK); +DEFINE_CLK(0, "intc.0", 18, MCF_CLK); +DEFINE_CLK(0, "intc.1", 19, MCF_CLK); +DEFINE_CLK(0, "iack.0", 21, MCF_CLK); +DEFINE_CLK(0, "imx1-i2c.0", 22, MCF_CLK); +DEFINE_CLK(0, "mcfqspi.0", 23, MCF_CLK); +DEFINE_CLK(0, "mcfuart.0", 24, MCF_BUSCLK); +DEFINE_CLK(0, "mcfuart.1", 25, MCF_BUSCLK); +DEFINE_CLK(0, "mcfuart.2", 26, MCF_BUSCLK); +DEFINE_CLK(0, "mcftmr.0", 28, MCF_CLK); +DEFINE_CLK(0, "mcftmr.1", 29, MCF_CLK); +DEFINE_CLK(0, "mcftmr.2", 30, MCF_CLK); +DEFINE_CLK(0, "mcftmr.3", 31, MCF_CLK); + +DEFINE_CLK(0, "mcfpit.0", 32, MCF_CLK); +DEFINE_CLK(0, "mcfpit.1", 33, MCF_CLK); +DEFINE_CLK(0, "mcfpit.2", 34, MCF_CLK); +DEFINE_CLK(0, "mcfpit.3", 35, MCF_CLK); +DEFINE_CLK(0, "mcfpwm.0", 36, MCF_CLK); +DEFINE_CLK(0, "mcfeport.0", 37, MCF_CLK); +DEFINE_CLK(0, "mcfwdt.0", 38, MCF_CLK); +DEFINE_CLK(0, "sys.0", 40, MCF_BUSCLK); +DEFINE_CLK(0, "gpio.0", 41, MCF_BUSCLK); +DEFINE_CLK(0, "mcfrtc.0", 42, MCF_CLK); +DEFINE_CLK(0, "mcflcd.0", 43, MCF_CLK); +DEFINE_CLK(0, "mcfusb-otg.0", 44, MCF_CLK); +DEFINE_CLK(0, "mcfusb-host.0", 45, MCF_CLK); +DEFINE_CLK(0, "sdram.0", 46, MCF_CLK); +DEFINE_CLK(0, "ssi.0", 47, MCF_CLK); +DEFINE_CLK(0, "pll.0", 48, MCF_CLK); + +DEFINE_CLK(1, "mdha.0", 32, MCF_CLK); +DEFINE_CLK(1, "skha.0", 33, MCF_CLK); +DEFINE_CLK(1, "rng.0", 34, MCF_CLK); + +struct clk *mcf_clks[] = { + &__clk_0_2, /* flexbus */ + &__clk_0_8, /* mcfcan.0 */ + &__clk_0_12, /* fec.0 */ + &__clk_0_17, /* edma */ + &__clk_0_18, /* intc.0 */ + &__clk_0_19, /* intc.1 */ + &__clk_0_21, /* iack.0 */ + &__clk_0_22, /* imx1-i2c.0 */ + &__clk_0_23, /* mcfqspi.0 */ + &__clk_0_24, /* mcfuart.0 */ + &__clk_0_25, /* mcfuart.1 */ + &__clk_0_26, /* mcfuart.2 */ + &__clk_0_28, /* mcftmr.0 */ + &__clk_0_29, /* mcftmr.1 */ + &__clk_0_30, /* mcftmr.2 */ + &__clk_0_31, /* mcftmr.3 */ + + &__clk_0_32, /* mcfpit.0 */ + &__clk_0_33, /* mcfpit.1 */ + &__clk_0_34, /* mcfpit.2 */ + &__clk_0_35, /* mcfpit.3 */ + &__clk_0_36, /* mcfpwm.0 */ + &__clk_0_37, /* mcfeport.0 */ + &__clk_0_38, /* mcfwdt.0 */ + &__clk_0_40, /* sys.0 */ + &__clk_0_41, /* gpio.0 */ + &__clk_0_42, /* mcfrtc.0 */ + &__clk_0_43, /* mcflcd.0 */ + &__clk_0_44, /* mcfusb-otg.0 */ + &__clk_0_45, /* mcfusb-host.0 */ + &__clk_0_46, /* sdram.0 */ + &__clk_0_47, /* ssi.0 */ + &__clk_0_48, /* pll.0 */ + + &__clk_1_32, /* mdha.0 */ + &__clk_1_33, /* skha.0 */ + &__clk_1_34, /* rng.0 */ + NULL, +}; + +static struct clk * const enable_clks[] __initconst = { + &__clk_0_2, /* flexbus */ + &__clk_0_18, /* intc.0 */ + &__clk_0_19, /* intc.1 */ + &__clk_0_21, /* iack.0 */ + &__clk_0_24, /* mcfuart.0 */ + &__clk_0_25, /* mcfuart.1 */ + &__clk_0_26, /* mcfuart.2 */ + &__clk_0_28, /* mcftmr.0 */ + &__clk_0_29, /* mcftmr.1 */ + &__clk_0_32, /* mcfpit.0 */ + &__clk_0_33, /* mcfpit.1 */ + &__clk_0_37, /* mcfeport.0 */ + &__clk_0_40, /* sys.0 */ + &__clk_0_41, /* gpio.0 */ + &__clk_0_46, /* sdram.0 */ + &__clk_0_48, /* pll.0 */ +}; + +static struct clk * const disable_clks[] __initconst = { + &__clk_0_8, /* mcfcan.0 */ + &__clk_0_12, /* fec.0 */ + &__clk_0_17, /* edma */ + &__clk_0_22, /* imx1-i2c.0 */ + &__clk_0_23, /* mcfqspi.0 */ + &__clk_0_30, /* mcftmr.2 */ + &__clk_0_31, /* mcftmr.3 */ + &__clk_0_34, /* mcfpit.2 */ + &__clk_0_35, /* mcfpit.3 */ + &__clk_0_36, /* mcfpwm.0 */ + &__clk_0_38, /* mcfwdt.0 */ + &__clk_0_42, /* mcfrtc.0 */ + &__clk_0_43, /* mcflcd.0 */ + &__clk_0_44, /* mcfusb-otg.0 */ + &__clk_0_45, /* mcfusb-host.0 */ + &__clk_0_47, /* ssi.0 */ + &__clk_1_32, /* mdha.0 */ + &__clk_1_33, /* skha.0 */ + &__clk_1_34, /* rng.0 */ +}; + + +static void __init m53xx_clk_init(void) +{ + unsigned i; + + /* make sure these clocks are enabled */ + for (i = 0; i < ARRAY_SIZE(enable_clks); ++i) + __clk_init_enabled(enable_clks[i]); + /* make sure these clocks are disabled */ + for (i = 0; i < ARRAY_SIZE(disable_clks); ++i) + __clk_init_disabled(disable_clks[i]); +} + +/***************************************************************************/ + +static void __init m53xx_qspi_init(void) +{ +#if IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI) + /* setup QSPS pins for QSPI with gpio CS control */ + writew(0x01f0, MCFGPIO_PAR_QSPI); +#endif /* IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI) */ +} + +/***************************************************************************/ + +static void __init m53xx_i2c_init(void) +{ +#if IS_ENABLED(CONFIG_I2C_IMX) + /* setup Port AS Pin Assignment Register for I2C */ + /* set PASPA0 to SCL and PASPA1 to SDA */ + u8 r = readb(MCFGPIO_PAR_FECI2C); + r |= 0x0f; + writeb(r, MCFGPIO_PAR_FECI2C); +#endif /* IS_ENABLED(CONFIG_I2C_IMX) */ +} + +/***************************************************************************/ + +static void __init m53xx_uarts_init(void) +{ + /* UART GPIO initialization */ + writew(readw(MCFGPIO_PAR_UART) | 0x0FFF, MCFGPIO_PAR_UART); +} + +/***************************************************************************/ + +static void __init m53xx_fec_init(void) +{ + u8 v; + + /* Set multi-function pins to ethernet mode for fec0 */ + v = readb(MCFGPIO_PAR_FECI2C); + v |= MCF_GPIO_PAR_FECI2C_PAR_MDC_EMDC | + MCF_GPIO_PAR_FECI2C_PAR_MDIO_EMDIO; + writeb(v, MCFGPIO_PAR_FECI2C); + + v = readb(MCFGPIO_PAR_FEC); + v = MCF_GPIO_PAR_FEC_PAR_FEC_7W_FEC | MCF_GPIO_PAR_FEC_PAR_FEC_MII_FEC; + writeb(v, MCFGPIO_PAR_FEC); +} + +/***************************************************************************/ + +void __init config_BSP(char *commandp, int size) +{ +#if !defined(CONFIG_BOOTPARAM) + /* Copy command line from FLASH to local buffer... */ + memcpy(commandp, (char *) 0x4000, 4); + if(strncmp(commandp, "kcl ", 4) == 0){ + memcpy(commandp, (char *) 0x4004, size); + commandp[size-1] = 0; + } else { + memset(commandp, 0, size); + } +#endif + mach_sched_init = hw_timer_init; + m53xx_clk_init(); + m53xx_uarts_init(); + m53xx_fec_init(); + m53xx_qspi_init(); + m53xx_i2c_init(); + +#ifdef CONFIG_BDM_DISABLE + /* + * Disable the BDM clocking. This also turns off most of the rest of + * the BDM device. This is good for EMC reasons. This option is not + * incompatible with the memory protection option. + */ + wdebug(MCFDEBUG_CSR, MCFDEBUG_CSR_PSTCLK); +#endif +} + +/***************************************************************************/ +/* Board initialization */ +/***************************************************************************/ +/* + * PLL min/max specifications + */ +#define MAX_FVCO 500000 /* KHz */ +#define MAX_FSYS 80000 /* KHz */ +#define MIN_FSYS 58333 /* KHz */ +#define FREF 16000 /* KHz */ + + +#define MAX_MFD 135 /* Multiplier */ +#define MIN_MFD 88 /* Multiplier */ +#define BUSDIV 6 /* Divider */ + +/* + * Low Power Divider specifications + */ +#define MIN_LPD (1 << 0) /* Divider (not encoded) */ +#define MAX_LPD (1 << 15) /* Divider (not encoded) */ +#define DEFAULT_LPD (1 << 1) /* Divider (not encoded) */ + +#define SYS_CLK_KHZ 80000 +#define SYSTEM_PERIOD 12.5 +/* + * SDRAM Timing Parameters + */ +#define SDRAM_BL 8 /* # of beats in a burst */ +#define SDRAM_TWR 2 /* in clocks */ +#define SDRAM_CASL 2.5 /* CASL in clocks */ +#define SDRAM_TRCD 2 /* in clocks */ +#define SDRAM_TRP 2 /* in clocks */ +#define SDRAM_TRFC 7 /* in clocks */ +#define SDRAM_TREFI 7800 /* in ns */ + +#define EXT_SRAM_ADDRESS (0xC0000000) +#define FLASH_ADDRESS (0x00000000) +#define SDRAM_ADDRESS (0x40000000) + +#define NAND_FLASH_ADDRESS (0xD0000000) + +void wtm_init(void); +void scm_init(void); +void gpio_init(void); +void fbcs_init(void); +void sdramc_init(void); +int clock_pll (int fsys, int flags); +int clock_limp (int); +int clock_exit_limp (void); +int get_sys_clock (void); + +asmlinkage void __init sysinit(void) +{ + clock_pll(0, 0); + + wtm_init(); + scm_init(); + gpio_init(); + fbcs_init(); + sdramc_init(); +} + +void wtm_init(void) +{ + /* Disable watchdog timer */ + writew(0, MCF_WTM_WCR); +} + +#define MCF_SCM_BCR_GBW (0x00000100) +#define MCF_SCM_BCR_GBR (0x00000200) + +void scm_init(void) +{ + /* All masters are trusted */ + writel(0x77777777, MCF_SCM_MPR); + + /* Allow supervisor/user, read/write, and trusted/untrusted + access to all slaves */ + writel(0, MCF_SCM_PACRA); + writel(0, MCF_SCM_PACRB); + writel(0, MCF_SCM_PACRC); + writel(0, MCF_SCM_PACRD); + writel(0, MCF_SCM_PACRE); + writel(0, MCF_SCM_PACRF); + + /* Enable bursts */ + writel(MCF_SCM_BCR_GBR | MCF_SCM_BCR_GBW, MCF_SCM_BCR); +} + + +void fbcs_init(void) +{ + writeb(0x3E, MCFGPIO_PAR_CS); + + /* Latch chip select */ + writel(0x10080000, MCF_FBCS1_CSAR); + + writel(0x002A3780, MCF_FBCS1_CSCR); + writel(MCF_FBCS_CSMR_BAM_2M | MCF_FBCS_CSMR_V, MCF_FBCS1_CSMR); + + /* Initialize latch to drive signals to inactive states */ + writew(0xffff, 0x10080000); + + /* External SRAM */ + writel(EXT_SRAM_ADDRESS, MCF_FBCS1_CSAR); + writel(MCF_FBCS_CSCR_PS_16 | + MCF_FBCS_CSCR_AA | + MCF_FBCS_CSCR_SBM | + MCF_FBCS_CSCR_WS(1), + MCF_FBCS1_CSCR); + writel(MCF_FBCS_CSMR_BAM_512K | MCF_FBCS_CSMR_V, MCF_FBCS1_CSMR); + + /* Boot Flash connected to FBCS0 */ + writel(FLASH_ADDRESS, MCF_FBCS0_CSAR); + writel(MCF_FBCS_CSCR_PS_16 | + MCF_FBCS_CSCR_BEM | + MCF_FBCS_CSCR_AA | + MCF_FBCS_CSCR_SBM | + MCF_FBCS_CSCR_WS(7), + MCF_FBCS0_CSCR); + writel(MCF_FBCS_CSMR_BAM_32M | MCF_FBCS_CSMR_V, MCF_FBCS0_CSMR); +} + +void sdramc_init(void) +{ + /* + * Check to see if the SDRAM has already been initialized + * by a run control tool + */ + if (!(readl(MCF_SDRAMC_SDCR) & MCF_SDRAMC_SDCR_REF)) { + /* SDRAM chip select initialization */ + + /* Initialize SDRAM chip select */ + writel(MCF_SDRAMC_SDCS_BA(SDRAM_ADDRESS) | + MCF_SDRAMC_SDCS_CSSZ(MCF_SDRAMC_SDCS_CSSZ_32MBYTE), + MCF_SDRAMC_SDCS0); + + /* + * Basic configuration and initialization + */ + writel(MCF_SDRAMC_SDCFG1_SRD2RW((int)((SDRAM_CASL + 2) + 0.5)) | + MCF_SDRAMC_SDCFG1_SWT2RD(SDRAM_TWR + 1) | + MCF_SDRAMC_SDCFG1_RDLAT((int)((SDRAM_CASL * 2) + 2)) | + MCF_SDRAMC_SDCFG1_ACT2RW((int)(SDRAM_TRCD + 0.5)) | + MCF_SDRAMC_SDCFG1_PRE2ACT((int)(SDRAM_TRP + 0.5)) | + MCF_SDRAMC_SDCFG1_REF2ACT((int)(SDRAM_TRFC + 0.5)) | + MCF_SDRAMC_SDCFG1_WTLAT(3), + MCF_SDRAMC_SDCFG1); + writel(MCF_SDRAMC_SDCFG2_BRD2PRE(SDRAM_BL / 2 + 1) | + MCF_SDRAMC_SDCFG2_BWT2RW(SDRAM_BL / 2 + SDRAM_TWR) | + MCF_SDRAMC_SDCFG2_BRD2WT((int)((SDRAM_CASL + SDRAM_BL / 2 - 1.0) + 0.5)) | + MCF_SDRAMC_SDCFG2_BL(SDRAM_BL - 1), + MCF_SDRAMC_SDCFG2); + + + /* + * Precharge and enable write to SDMR + */ + writel(MCF_SDRAMC_SDCR_MODE_EN | + MCF_SDRAMC_SDCR_CKE | + MCF_SDRAMC_SDCR_DDR | + MCF_SDRAMC_SDCR_MUX(1) | + MCF_SDRAMC_SDCR_RCNT((int)(((SDRAM_TREFI / (SYSTEM_PERIOD * 64)) - 1) + 0.5)) | + MCF_SDRAMC_SDCR_PS_16 | + MCF_SDRAMC_SDCR_IPALL, + MCF_SDRAMC_SDCR); + + /* + * Write extended mode register + */ + writel(MCF_SDRAMC_SDMR_BNKAD_LEMR | + MCF_SDRAMC_SDMR_AD(0x0) | + MCF_SDRAMC_SDMR_CMD, + MCF_SDRAMC_SDMR); + + /* + * Write mode register and reset DLL + */ + writel(MCF_SDRAMC_SDMR_BNKAD_LMR | + MCF_SDRAMC_SDMR_AD(0x163) | + MCF_SDRAMC_SDMR_CMD, + MCF_SDRAMC_SDMR); + + /* + * Execute a PALL command + */ + writel(readl(MCF_SDRAMC_SDCR) | MCF_SDRAMC_SDCR_IPALL, MCF_SDRAMC_SDCR); + + /* + * Perform two REF cycles + */ + writel(readl(MCF_SDRAMC_SDCR) | MCF_SDRAMC_SDCR_IREF, MCF_SDRAMC_SDCR); + writel(readl(MCF_SDRAMC_SDCR) | MCF_SDRAMC_SDCR_IREF, MCF_SDRAMC_SDCR); + + /* + * Write mode register and clear reset DLL + */ + writel(MCF_SDRAMC_SDMR_BNKAD_LMR | + MCF_SDRAMC_SDMR_AD(0x063) | + MCF_SDRAMC_SDMR_CMD, + MCF_SDRAMC_SDMR); + + /* + * Enable auto refresh and lock SDMR + */ + writel(readl(MCF_SDRAMC_SDCR) & ~MCF_SDRAMC_SDCR_MODE_EN, + MCF_SDRAMC_SDCR); + writel(MCF_SDRAMC_SDCR_REF | MCF_SDRAMC_SDCR_DQS_OE(0xC), + MCF_SDRAMC_SDCR); + } +} + +void gpio_init(void) +{ + /* Enable UART0 pins */ + writew(MCF_GPIO_PAR_UART_PAR_URXD0 | MCF_GPIO_PAR_UART_PAR_UTXD0, + MCFGPIO_PAR_UART); + + /* + * Initialize TIN3 as a GPIO output to enable the write + * half of the latch. + */ + writeb(0x00, MCFGPIO_PAR_TIMER); + writeb(0x08, MCFGPIO_PDDR_TIMER); + writeb(0x00, MCFGPIO_PCLRR_TIMER); +} + +int clock_pll(int fsys, int flags) +{ + int fref, temp, fout, mfd; + u32 i; + + fref = FREF; + + if (fsys == 0) { + /* Return current PLL output */ + mfd = readb(MCF_PLL_PFDR); + + return (fref * mfd / (BUSDIV * 4)); + } + + /* Check bounds of requested system clock */ + if (fsys > MAX_FSYS) + fsys = MAX_FSYS; + if (fsys < MIN_FSYS) + fsys = MIN_FSYS; + + /* Multiplying by 100 when calculating the temp value, + and then dividing by 100 to calculate the mfd allows + for exact values without needing to include floating + point libraries. */ + temp = 100 * fsys / fref; + mfd = 4 * BUSDIV * temp / 100; + + /* Determine the output frequency for selected values */ + fout = (fref * mfd / (BUSDIV * 4)); + + /* + * Check to see if the SDRAM has already been initialized. + * If it has then the SDRAM needs to be put into self refresh + * mode before reprogramming the PLL. + */ + if (readl(MCF_SDRAMC_SDCR) & MCF_SDRAMC_SDCR_REF) + /* Put SDRAM into self refresh mode */ + writel(readl(MCF_SDRAMC_SDCR) & ~MCF_SDRAMC_SDCR_CKE, + MCF_SDRAMC_SDCR); + + /* + * Initialize the PLL to generate the new system clock frequency. + * The device must be put into LIMP mode to reprogram the PLL. + */ + + /* Enter LIMP mode */ + clock_limp(DEFAULT_LPD); + + /* Reprogram PLL for desired fsys */ + writeb(MCF_PLL_PODR_CPUDIV(BUSDIV/3) | MCF_PLL_PODR_BUSDIV(BUSDIV), + MCF_PLL_PODR); + + writeb(mfd, MCF_PLL_PFDR); + + /* Exit LIMP mode */ + clock_exit_limp(); + + /* + * Return the SDRAM to normal operation if it is in use. + */ + if (readl(MCF_SDRAMC_SDCR) & MCF_SDRAMC_SDCR_REF) + /* Exit self refresh mode */ + writel(readl(MCF_SDRAMC_SDCR) | MCF_SDRAMC_SDCR_CKE, + MCF_SDRAMC_SDCR); + + /* Errata - workaround for SDRAM opeartion after exiting LIMP mode */ + writel(MCF_SDRAMC_REFRESH, MCF_SDRAMC_LIMP_FIX); + + /* wait for DQS logic to relock */ + for (i = 0; i < 0x200; i++) + ; + + return fout; +} + +int clock_limp(int div) +{ + u32 temp; + + /* Check bounds of divider */ + if (div < MIN_LPD) + div = MIN_LPD; + if (div > MAX_LPD) + div = MAX_LPD; + + /* Save of the current value of the SSIDIV so we don't + overwrite the value*/ + temp = readw(MCF_CCM_CDR) & MCF_CCM_CDR_SSIDIV(0xF); + + /* Apply the divider to the system clock */ + writew(MCF_CCM_CDR_LPDIV(div) | MCF_CCM_CDR_SSIDIV(temp), MCF_CCM_CDR); + + writew(readw(MCF_CCM_MISCCR) | MCF_CCM_MISCCR_LIMP, MCF_CCM_MISCCR); + + return (FREF/(3*(1 << div))); +} + +int clock_exit_limp(void) +{ + int fout; + + /* Exit LIMP mode */ + writew(readw(MCF_CCM_MISCCR) & ~MCF_CCM_MISCCR_LIMP, MCF_CCM_MISCCR); + + /* Wait for PLL to lock */ + while (!(readw(MCF_CCM_MISCCR) & MCF_CCM_MISCCR_PLL_LOCK)) + ; + + fout = get_sys_clock(); + + return fout; +} + +int get_sys_clock(void) +{ + int divider; + + /* Test to see if device is in LIMP mode */ + if (readw(MCF_CCM_MISCCR) & MCF_CCM_MISCCR_LIMP) { + divider = readw(MCF_CCM_CDR) & MCF_CCM_CDR_LPDIV(0xF); + return (FREF/(2 << divider)); + } + else + return (FREF * readb(MCF_PLL_PFDR)) / (BUSDIV * 4); +} diff --git a/arch/m68k/coldfire/m5407.c b/arch/m68k/coldfire/m5407.c new file mode 100644 index 000000000..0400d7611 --- /dev/null +++ b/arch/m68k/coldfire/m5407.c @@ -0,0 +1,68 @@ +// SPDX-License-Identifier: GPL-2.0 +/***************************************************************************/ + +/* + * m5407.c -- platform support for ColdFire 5407 based boards + * + * Copyright (C) 1999-2002, Greg Ungerer (gerg@snapgear.com) + * Copyright (C) 2000, Lineo (www.lineo.com) + */ + +/***************************************************************************/ + +#include +#include +#include +#include +#include +#include +#include +#include + +/***************************************************************************/ + +DEFINE_CLK(pll, "pll.0", MCF_CLK); +DEFINE_CLK(sys, "sys.0", MCF_BUSCLK); +DEFINE_CLK(mcftmr0, "mcftmr.0", MCF_BUSCLK); +DEFINE_CLK(mcftmr1, "mcftmr.1", MCF_BUSCLK); +DEFINE_CLK(mcfuart0, "mcfuart.0", MCF_BUSCLK); +DEFINE_CLK(mcfuart1, "mcfuart.1", MCF_BUSCLK); +DEFINE_CLK(mcfi2c0, "imx1-i2c.0", MCF_BUSCLK); + +struct clk *mcf_clks[] = { + &clk_pll, + &clk_sys, + &clk_mcftmr0, + &clk_mcftmr1, + &clk_mcfuart0, + &clk_mcfuart1, + &clk_mcfi2c0, + NULL +}; + +/***************************************************************************/ + +static void __init m5407_i2c_init(void) +{ +#if IS_ENABLED(CONFIG_I2C_IMX) + writeb(MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL5 | MCFSIM_ICR_PRI0, + MCFSIM_I2CICR); + mcf_mapirq2imr(MCF_IRQ_I2C0, MCFINTC_I2C); +#endif /* IS_ENABLED(CONFIG_I2C_IMX) */ +} + +/***************************************************************************/ + +void __init config_BSP(char *commandp, int size) +{ + mach_sched_init = hw_timer_init; + + /* Only support the external interrupts on their primary level */ + mcf_mapirq2imr(25, MCFINTC_EINT1); + mcf_mapirq2imr(27, MCFINTC_EINT3); + mcf_mapirq2imr(29, MCFINTC_EINT5); + mcf_mapirq2imr(31, MCFINTC_EINT7); + m5407_i2c_init(); +} + +/***************************************************************************/ diff --git a/arch/m68k/coldfire/m5441x.c b/arch/m68k/coldfire/m5441x.c new file mode 100644 index 000000000..1e5259a65 --- /dev/null +++ b/arch/m68k/coldfire/m5441x.c @@ -0,0 +1,251 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * m5441x.c -- support for Coldfire m5441x processors + * + * (C) Copyright Steven King + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +DEFINE_CLK(0, "flexbus", 2, MCF_CLK); +DEFINE_CLK(0, "mcfcan.0", 8, MCF_CLK); +DEFINE_CLK(0, "mcfcan.1", 9, MCF_CLK); +DEFINE_CLK(0, "imx1-i2c.1", 14, MCF_CLK); +DEFINE_CLK(0, "mcfdspi.1", 15, MCF_CLK); +DEFINE_CLK(0, "edma", 17, MCF_CLK); +DEFINE_CLK(0, "intc.0", 18, MCF_CLK); +DEFINE_CLK(0, "intc.1", 19, MCF_CLK); +DEFINE_CLK(0, "intc.2", 20, MCF_CLK); +DEFINE_CLK(0, "imx1-i2c.0", 22, MCF_CLK); +DEFINE_CLK(0, "fsl-dspi.0", 23, MCF_CLK); +DEFINE_CLK(0, "mcfuart.0", 24, MCF_BUSCLK); +DEFINE_CLK(0, "mcfuart.1", 25, MCF_BUSCLK); +DEFINE_CLK(0, "mcfuart.2", 26, MCF_BUSCLK); +DEFINE_CLK(0, "mcfuart.3", 27, MCF_BUSCLK); +DEFINE_CLK(0, "mcftmr.0", 28, MCF_CLK); +DEFINE_CLK(0, "mcftmr.1", 29, MCF_CLK); +DEFINE_CLK(0, "mcftmr.2", 30, MCF_CLK); +DEFINE_CLK(0, "mcftmr.3", 31, MCF_CLK); +DEFINE_CLK(0, "mcfpit.0", 32, MCF_CLK); +DEFINE_CLK(0, "mcfpit.1", 33, MCF_CLK); +DEFINE_CLK(0, "mcfpit.2", 34, MCF_CLK); +DEFINE_CLK(0, "mcfpit.3", 35, MCF_CLK); +DEFINE_CLK(0, "mcfeport.0", 37, MCF_CLK); +DEFINE_CLK(0, "mcfadc.0", 38, MCF_CLK); +DEFINE_CLK(0, "mcfdac.0", 39, MCF_CLK); +DEFINE_CLK(0, "mcfrtc.0", 42, MCF_CLK); +DEFINE_CLK(0, "mcfsim.0", 43, MCF_CLK); +DEFINE_CLK(0, "mcfusb-otg.0", 44, MCF_CLK); +DEFINE_CLK(0, "mcfusb-host.0", 45, MCF_CLK); +DEFINE_CLK(0, "mcfddr-sram.0", 46, MCF_CLK); +DEFINE_CLK(0, "mcfssi.0", 47, MCF_CLK); +DEFINE_CLK(0, "pll.0", 48, MCF_CLK); +DEFINE_CLK(0, "mcfrng.0", 49, MCF_CLK); +DEFINE_CLK(0, "mcfssi.1", 50, MCF_CLK); +DEFINE_CLK(0, "sdhci-esdhc-mcf.0", 51, MCF_CLK); +DEFINE_CLK(0, "enet-fec.0", 53, MCF_CLK); +DEFINE_CLK(0, "enet-fec.1", 54, MCF_CLK); +DEFINE_CLK(0, "switch.0", 55, MCF_CLK); +DEFINE_CLK(0, "switch.1", 56, MCF_CLK); +DEFINE_CLK(0, "nand.0", 63, MCF_CLK); + +DEFINE_CLK(1, "mcfow.0", 2, MCF_CLK); +DEFINE_CLK(1, "imx1-i2c.2", 4, MCF_CLK); +DEFINE_CLK(1, "imx1-i2c.3", 5, MCF_CLK); +DEFINE_CLK(1, "imx1-i2c.4", 6, MCF_CLK); +DEFINE_CLK(1, "imx1-i2c.5", 7, MCF_CLK); +DEFINE_CLK(1, "mcfuart.4", 24, MCF_BUSCLK); +DEFINE_CLK(1, "mcfuart.5", 25, MCF_BUSCLK); +DEFINE_CLK(1, "mcfuart.6", 26, MCF_BUSCLK); +DEFINE_CLK(1, "mcfuart.7", 27, MCF_BUSCLK); +DEFINE_CLK(1, "mcfuart.8", 28, MCF_BUSCLK); +DEFINE_CLK(1, "mcfuart.9", 29, MCF_BUSCLK); +DEFINE_CLK(1, "mcfpwm.0", 34, MCF_BUSCLK); +DEFINE_CLK(1, "sys.0", 36, MCF_BUSCLK); +DEFINE_CLK(1, "gpio.0", 37, MCF_BUSCLK); + +DEFINE_CLK(2, "ipg.0", 0, MCF_CLK); +DEFINE_CLK(2, "ahb.0", 1, MCF_CLK); +DEFINE_CLK(2, "per.0", 2, MCF_CLK); + +struct clk *mcf_clks[] = { + &__clk_0_2, + &__clk_0_8, + &__clk_0_9, + &__clk_0_14, + &__clk_0_15, + &__clk_0_17, + &__clk_0_18, + &__clk_0_19, + &__clk_0_20, + &__clk_0_22, + &__clk_0_23, + &__clk_0_24, + &__clk_0_25, + &__clk_0_26, + &__clk_0_27, + &__clk_0_28, + &__clk_0_29, + &__clk_0_30, + &__clk_0_31, + &__clk_0_32, + &__clk_0_33, + &__clk_0_34, + &__clk_0_35, + &__clk_0_37, + &__clk_0_38, + &__clk_0_39, + &__clk_0_42, + &__clk_0_43, + &__clk_0_44, + &__clk_0_45, + &__clk_0_46, + &__clk_0_47, + &__clk_0_48, + &__clk_0_49, + &__clk_0_50, + &__clk_0_51, + &__clk_0_53, + &__clk_0_54, + &__clk_0_55, + &__clk_0_56, + &__clk_0_63, + + &__clk_1_2, + &__clk_1_4, + &__clk_1_5, + &__clk_1_6, + &__clk_1_7, + &__clk_1_24, + &__clk_1_25, + &__clk_1_26, + &__clk_1_27, + &__clk_1_28, + &__clk_1_29, + &__clk_1_34, + &__clk_1_36, + &__clk_1_37, + + &__clk_2_0, + &__clk_2_1, + &__clk_2_2, + + NULL, +}; + + +static struct clk * const enable_clks[] __initconst = { + /* make sure these clocks are enabled */ + &__clk_0_15, /* dspi.1 */ + &__clk_0_17, /* eDMA */ + &__clk_0_18, /* intc0 */ + &__clk_0_19, /* intc0 */ + &__clk_0_20, /* intc0 */ + &__clk_0_23, /* dspi.0 */ + &__clk_0_24, /* uart0 */ + &__clk_0_25, /* uart1 */ + &__clk_0_26, /* uart2 */ + &__clk_0_27, /* uart3 */ + + &__clk_0_33, /* pit.1 */ + &__clk_0_37, /* eport */ + &__clk_0_48, /* pll */ + &__clk_0_51, /* esdhc */ + + &__clk_1_36, /* CCM/reset module/Power management */ + &__clk_1_37, /* gpio */ +}; +static struct clk * const disable_clks[] __initconst = { + &__clk_0_8, /* can.0 */ + &__clk_0_9, /* can.1 */ + &__clk_0_14, /* i2c.1 */ + &__clk_0_22, /* i2c.0 */ + &__clk_0_23, /* dspi.0 */ + &__clk_0_28, /* tmr.1 */ + &__clk_0_29, /* tmr.2 */ + &__clk_0_30, /* tmr.2 */ + &__clk_0_31, /* tmr.3 */ + &__clk_0_32, /* pit.0 */ + &__clk_0_34, /* pit.2 */ + &__clk_0_35, /* pit.3 */ + &__clk_0_38, /* adc */ + &__clk_0_39, /* dac */ + &__clk_0_44, /* usb otg */ + &__clk_0_45, /* usb host */ + &__clk_0_47, /* ssi.0 */ + &__clk_0_49, /* rng */ + &__clk_0_50, /* ssi.1 */ + &__clk_0_51, /* eSDHC */ + &__clk_0_53, /* enet-fec */ + &__clk_0_54, /* enet-fec */ + &__clk_0_55, /* switch.0 */ + &__clk_0_56, /* switch.1 */ + + &__clk_1_2, /* 1-wire */ + &__clk_1_4, /* i2c.2 */ + &__clk_1_5, /* i2c.3 */ + &__clk_1_6, /* i2c.4 */ + &__clk_1_7, /* i2c.5 */ + &__clk_1_24, /* uart 4 */ + &__clk_1_25, /* uart 5 */ + &__clk_1_26, /* uart 6 */ + &__clk_1_27, /* uart 7 */ + &__clk_1_28, /* uart 8 */ + &__clk_1_29, /* uart 9 */ +}; + +static void __clk_enable2(struct clk *clk) +{ + __raw_writel(__raw_readl(MCFSDHC_CLK) | (1 << clk->slot), MCFSDHC_CLK); +} + +static void __clk_disable2(struct clk *clk) +{ + __raw_writel(__raw_readl(MCFSDHC_CLK) & ~(1 << clk->slot), MCFSDHC_CLK); +} + +struct clk_ops clk_ops2 = { + .enable = __clk_enable2, + .disable = __clk_disable2, +}; + +static void __init m5441x_clk_init(void) +{ + unsigned i; + + for (i = 0; i < ARRAY_SIZE(enable_clks); ++i) + __clk_init_enabled(enable_clks[i]); + /* make sure these clocks are disabled */ + for (i = 0; i < ARRAY_SIZE(disable_clks); ++i) + __clk_init_disabled(disable_clks[i]); +} + +static void __init m5441x_uarts_init(void) +{ + __raw_writeb(0x0f, MCFGPIO_PAR_UART0); + __raw_writeb(0x00, MCFGPIO_PAR_UART1); + __raw_writeb(0x00, MCFGPIO_PAR_UART2); +} + +static void __init m5441x_fec_init(void) +{ + __raw_writeb(0x03, MCFGPIO_PAR_FEC); +} + +void __init config_BSP(char *commandp, int size) +{ + m5441x_clk_init(); + mach_sched_init = hw_timer_init; + m5441x_uarts_init(); + m5441x_fec_init(); +} diff --git a/arch/m68k/coldfire/m54xx.c b/arch/m68k/coldfire/m54xx.c new file mode 100644 index 000000000..360c723c0 --- /dev/null +++ b/arch/m68k/coldfire/m54xx.c @@ -0,0 +1,105 @@ +// SPDX-License-Identifier: GPL-2.0 +/***************************************************************************/ + +/* + * m54xx.c -- platform support for ColdFire 54xx based boards + * + * Copyright (C) 2010, Philippe De Muyter + */ + +/***************************************************************************/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#ifdef CONFIG_MMU +#include +#endif + +/***************************************************************************/ + +DEFINE_CLK(pll, "pll.0", MCF_CLK); +DEFINE_CLK(sys, "sys.0", MCF_BUSCLK); +DEFINE_CLK(mcfslt0, "mcfslt.0", MCF_BUSCLK); +DEFINE_CLK(mcfslt1, "mcfslt.1", MCF_BUSCLK); +DEFINE_CLK(mcfuart0, "mcfuart.0", MCF_BUSCLK); +DEFINE_CLK(mcfuart1, "mcfuart.1", MCF_BUSCLK); +DEFINE_CLK(mcfuart2, "mcfuart.2", MCF_BUSCLK); +DEFINE_CLK(mcfuart3, "mcfuart.3", MCF_BUSCLK); +DEFINE_CLK(mcfi2c0, "imx1-i2c.0", MCF_BUSCLK); + +struct clk *mcf_clks[] = { + &clk_pll, + &clk_sys, + &clk_mcfslt0, + &clk_mcfslt1, + &clk_mcfuart0, + &clk_mcfuart1, + &clk_mcfuart2, + &clk_mcfuart3, + &clk_mcfi2c0, + NULL +}; + +/***************************************************************************/ + +static void __init m54xx_uarts_init(void) +{ + /* enable io pins */ + __raw_writeb(MCF_PAR_PSC_TXD | MCF_PAR_PSC_RXD, MCFGPIO_PAR_PSC0); + __raw_writeb(MCF_PAR_PSC_TXD | MCF_PAR_PSC_RXD | MCF_PAR_PSC_RTS_RTS, + MCFGPIO_PAR_PSC1); + __raw_writeb(MCF_PAR_PSC_TXD | MCF_PAR_PSC_RXD | MCF_PAR_PSC_RTS_RTS | + MCF_PAR_PSC_CTS_CTS, MCFGPIO_PAR_PSC2); + __raw_writeb(MCF_PAR_PSC_TXD | MCF_PAR_PSC_RXD, MCFGPIO_PAR_PSC3); +} + +/***************************************************************************/ + +static void __init m54xx_i2c_init(void) +{ +#if IS_ENABLED(CONFIG_I2C_IMX) + u32 r; + + /* set the fec/i2c/irq pin assignment register for i2c */ + r = readl(MCF_PAR_FECI2CIRQ); + r |= MCF_PAR_FECI2CIRQ_SDA | MCF_PAR_FECI2CIRQ_SCL; + writel(r, MCF_PAR_FECI2CIRQ); +#endif /* IS_ENABLED(CONFIG_I2C_IMX) */ +} + +/***************************************************************************/ + +static void mcf54xx_reset(void) +{ + /* disable interrupts and enable the watchdog */ + asm("movew #0x2700, %sr\n"); + __raw_writel(0, MCF_GPT_GMS0); + __raw_writel(MCF_GPT_GCIR_CNT(1), MCF_GPT_GCIR0); + __raw_writel(MCF_GPT_GMS_WDEN | MCF_GPT_GMS_CE | MCF_GPT_GMS_TMS(4), + MCF_GPT_GMS0); +} + +/***************************************************************************/ + +void __init config_BSP(char *commandp, int size) +{ + mach_reset = mcf54xx_reset; + mach_sched_init = hw_timer_init; + m54xx_uarts_init(); + m54xx_i2c_init(); +} + +/***************************************************************************/ diff --git a/arch/m68k/coldfire/mcf8390.c b/arch/m68k/coldfire/mcf8390.c new file mode 100644 index 000000000..23a6874a3 --- /dev/null +++ b/arch/m68k/coldfire/mcf8390.c @@ -0,0 +1,38 @@ +/* + * mcf8390.c -- platform support for 8390 ethernet on many boards + * + * (C) Copyright 2012, Greg Ungerer + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file COPYING in the main directory of this archive + * for more details. + */ + +#include +#include +#include +#include +#include +#include + +static struct resource mcf8390_resources[] = { + { + .start = NE2000_ADDR, + .end = NE2000_ADDR + NE2000_ADDRSIZE - 1, + .flags = IORESOURCE_MEM, + }, + { + .start = NE2000_IRQ_VECTOR, + .end = NE2000_IRQ_VECTOR, + .flags = IORESOURCE_IRQ, + }, +}; + +static int __init mcf8390_platform_init(void) +{ + platform_device_register_simple("mcf8390", -1, mcf8390_resources, + ARRAY_SIZE(mcf8390_resources)); + return 0; +} + +arch_initcall(mcf8390_platform_init); diff --git a/arch/m68k/coldfire/nettel.c b/arch/m68k/coldfire/nettel.c new file mode 100644 index 000000000..ea8df6e7a --- /dev/null +++ b/arch/m68k/coldfire/nettel.c @@ -0,0 +1,154 @@ +// SPDX-License-Identifier: GPL-2.0 +/***************************************************************************/ + +/* + * nettel.c -- startup code support for the NETtel boards + * + * Copyright (C) 2009, Greg Ungerer (gerg@snapgear.com) + */ + +/***************************************************************************/ + +#include +#include +#include +#include +#include +#include +#include +#include + +/***************************************************************************/ + +/* + * Define the IO and interrupt resources of the 2 SMC9196 interfaces. + */ +#define NETTEL_SMC0_ADDR 0x30600300 +#define NETTEL_SMC0_IRQ 29 + +#define NETTEL_SMC1_ADDR 0x30600000 +#define NETTEL_SMC1_IRQ 27 + +/* + * We need some access into the SMC9196 registers. Define those registers + * we will need here (including the smc91x.h doesn't seem to give us these + * in a simple form). + */ +#define SMC91xx_BANKSELECT 14 +#define SMC91xx_BASEADDR 2 +#define SMC91xx_BASEMAC 4 + +/***************************************************************************/ + +static struct resource nettel_smc91x_0_resources[] = { + { + .start = NETTEL_SMC0_ADDR, + .end = NETTEL_SMC0_ADDR + 0x20, + .flags = IORESOURCE_MEM, + }, + { + .start = NETTEL_SMC0_IRQ, + .end = NETTEL_SMC0_IRQ, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct resource nettel_smc91x_1_resources[] = { + { + .start = NETTEL_SMC1_ADDR, + .end = NETTEL_SMC1_ADDR + 0x20, + .flags = IORESOURCE_MEM, + }, + { + .start = NETTEL_SMC1_IRQ, + .end = NETTEL_SMC1_IRQ, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device nettel_smc91x[] = { + { + .name = "smc91x", + .id = 0, + .num_resources = ARRAY_SIZE(nettel_smc91x_0_resources), + .resource = nettel_smc91x_0_resources, + }, + { + .name = "smc91x", + .id = 1, + .num_resources = ARRAY_SIZE(nettel_smc91x_1_resources), + .resource = nettel_smc91x_1_resources, + }, +}; + +static struct platform_device *nettel_devices[] __initdata = { + &nettel_smc91x[0], + &nettel_smc91x[1], +}; + +/***************************************************************************/ + +static u8 nettel_macdefault[] __initdata = { + 0x00, 0xd0, 0xcf, 0x00, 0x00, 0x01, +}; + +/* + * Set flash contained MAC address into SMC9196 core. Make sure the flash + * MAC address is sane, and not an empty flash. If no good use the Moreton + * Bay default MAC address instead. + */ + +static void __init nettel_smc91x_setmac(unsigned int ioaddr, unsigned int flashaddr) +{ + u16 *macp; + + macp = (u16 *) flashaddr; + if ((macp[0] == 0xffff) && (macp[1] == 0xffff) && (macp[2] == 0xffff)) + macp = (u16 *) &nettel_macdefault[0]; + + writew(1, NETTEL_SMC0_ADDR + SMC91xx_BANKSELECT); + writew(macp[0], ioaddr + SMC91xx_BASEMAC); + writew(macp[1], ioaddr + SMC91xx_BASEMAC + 2); + writew(macp[2], ioaddr + SMC91xx_BASEMAC + 4); +} + +/***************************************************************************/ + +/* + * Re-map the address space of at least one of the SMC ethernet + * parts. Both parts power up decoding the same address, so we + * need to move one of them first, before doing anything else. + */ + +static void __init nettel_smc91x_init(void) +{ + writew(0x00ec, MCFSIM_PADDR); + mcf_setppdata(0, 0x0080); + writew(1, NETTEL_SMC0_ADDR + SMC91xx_BANKSELECT); + writew(0x0067, NETTEL_SMC0_ADDR + SMC91xx_BASEADDR); + mcf_setppdata(0x0080, 0); + + /* Set correct chip select timing for SMC9196 accesses */ + writew(0x1180, MCFSIM_CSCR3); + + /* Set the SMC interrupts to be auto-vectored */ + mcf_autovector(NETTEL_SMC0_IRQ); + mcf_autovector(NETTEL_SMC1_IRQ); + + /* Set MAC addresses from flash for both interfaces */ + nettel_smc91x_setmac(NETTEL_SMC0_ADDR, 0xf0006000); + nettel_smc91x_setmac(NETTEL_SMC1_ADDR, 0xf0006006); +} + +/***************************************************************************/ + +static int __init init_nettel(void) +{ + nettel_smc91x_init(); + platform_add_devices(nettel_devices, ARRAY_SIZE(nettel_devices)); + return 0; +} + +arch_initcall(init_nettel); + +/***************************************************************************/ diff --git a/arch/m68k/coldfire/pci.c b/arch/m68k/coldfire/pci.c new file mode 100644 index 000000000..84eab0f5e --- /dev/null +++ b/arch/m68k/coldfire/pci.c @@ -0,0 +1,259 @@ +/* + * pci.c -- PCI bus support for ColdFire processors + * + * (C) Copyright 2012, Greg Ungerer + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file COPYING in the main directory of this archive + * for more details. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* + * Memory and IO mappings. We use a 1:1 mapping for local host memory to + * PCI bus memory (no reason not to really). IO space is mapped in its own + * separate address region. The device configuration space is mapped over + * the IO map space when we enable it in the PCICAR register. + */ +static struct pci_bus *rootbus; +static unsigned long iospace; + +/* + * We need to be carefull probing on bus 0 (directly connected to host + * bridge). We should only access the well defined possible devices in + * use, ignore aliases and the like. + */ +static unsigned char mcf_host_slot2sid[32] = { + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 1, 2, 0, 3, 4, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, +}; + +static unsigned char mcf_host_irq[] = { + 0, 69, 69, 71, 71, +}; + +/* + * Configuration space access functions. Configuration space access is + * through the IO mapping window, enabling it via the PCICAR register. + */ +static unsigned long mcf_mk_pcicar(int bus, unsigned int devfn, int where) +{ + return (bus << PCICAR_BUSN) | (devfn << PCICAR_DEVFNN) | (where & 0xfc); +} + +static int mcf_pci_readconfig(struct pci_bus *bus, unsigned int devfn, + int where, int size, u32 *value) +{ + unsigned long addr; + + *value = 0xffffffff; + + if (bus->number == 0) { + if (mcf_host_slot2sid[PCI_SLOT(devfn)] == 0) + return PCIBIOS_SUCCESSFUL; + } + + addr = mcf_mk_pcicar(bus->number, devfn, where); + __raw_writel(PCICAR_E | addr, PCICAR); + __raw_readl(PCICAR); + addr = iospace + (where & 0x3); + + switch (size) { + case 1: + *value = __raw_readb(addr); + break; + case 2: + *value = le16_to_cpu(__raw_readw(addr)); + break; + default: + *value = le32_to_cpu(__raw_readl(addr)); + break; + } + + __raw_writel(0, PCICAR); + __raw_readl(PCICAR); + return PCIBIOS_SUCCESSFUL; +} + +static int mcf_pci_writeconfig(struct pci_bus *bus, unsigned int devfn, + int where, int size, u32 value) +{ + unsigned long addr; + + if (bus->number == 0) { + if (mcf_host_slot2sid[PCI_SLOT(devfn)] == 0) + return PCIBIOS_SUCCESSFUL; + } + + addr = mcf_mk_pcicar(bus->number, devfn, where); + __raw_writel(PCICAR_E | addr, PCICAR); + __raw_readl(PCICAR); + addr = iospace + (where & 0x3); + + switch (size) { + case 1: + __raw_writeb(value, addr); + break; + case 2: + __raw_writew(cpu_to_le16(value), addr); + break; + default: + __raw_writel(cpu_to_le32(value), addr); + break; + } + + __raw_writel(0, PCICAR); + __raw_readl(PCICAR); + return PCIBIOS_SUCCESSFUL; +} + +static struct pci_ops mcf_pci_ops = { + .read = mcf_pci_readconfig, + .write = mcf_pci_writeconfig, +}; + +/* + * Initialize the PCI bus registers, and scan the bus. + */ +static struct resource mcf_pci_mem = { + .name = "PCI Memory space", + .start = PCI_MEM_PA, + .end = PCI_MEM_PA + PCI_MEM_SIZE - 1, + .flags = IORESOURCE_MEM, +}; + +static struct resource mcf_pci_io = { + .name = "PCI IO space", + .start = 0x400, + .end = 0x10000 - 1, + .flags = IORESOURCE_IO, +}; + +static struct resource busn_resource = { + .name = "PCI busn", + .start = 0, + .end = 255, + .flags = IORESOURCE_BUS, +}; + +/* + * Interrupt mapping and setting. + */ +static int mcf_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) +{ + int sid; + + sid = mcf_host_slot2sid[slot]; + if (sid) + return mcf_host_irq[sid]; + return 0; +} + +static int __init mcf_pci_init(void) +{ + struct pci_host_bridge *bridge; + int ret; + + bridge = pci_alloc_host_bridge(0); + if (!bridge) + return -ENOMEM; + + pr_info("ColdFire: PCI bus initialization...\n"); + + /* Reset the external PCI bus */ + __raw_writel(PCIGSCR_RESET, PCIGSCR); + __raw_writel(0, PCITCR); + + request_resource(&iomem_resource, &mcf_pci_mem); + request_resource(&iomem_resource, &mcf_pci_io); + + /* Configure PCI arbiter */ + __raw_writel(PACR_INTMPRI | PACR_INTMINTE | PACR_EXTMPRI(0x1f) | + PACR_EXTMINTE(0x1f), PACR); + + /* Set required multi-function pins for PCI bus use */ + __raw_writew(0x3ff, MCFGPIO_PAR_PCIBG); + __raw_writew(0x3ff, MCFGPIO_PAR_PCIBR); + + /* Set up config space for local host bus controller */ + __raw_writel(PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | + PCI_COMMAND_INVALIDATE, PCISCR); + __raw_writel(PCICR1_LT(32) | PCICR1_CL(8), PCICR1); + __raw_writel(0, PCICR2); + + /* + * Set up the initiator windows for memory and IO mapping. + * These give the CPU bus access onto the PCI bus. One for each of + * PCI memory and IO address spaces. + */ + __raw_writel(WXBTAR(PCI_MEM_PA, PCI_MEM_BA, PCI_MEM_SIZE), + PCIIW0BTAR); + __raw_writel(WXBTAR(PCI_IO_PA, PCI_IO_BA, PCI_IO_SIZE), + PCIIW1BTAR); + __raw_writel(PCIIWCR_W0_MEM /*| PCIIWCR_W0_MRDL*/ | PCIIWCR_W0_E | + PCIIWCR_W1_IO | PCIIWCR_W1_E, PCIIWCR); + + /* + * Set up the target windows for access from the PCI bus back to the + * CPU bus. All we need is access to system RAM (for mastering). + */ + __raw_writel(CONFIG_RAMBASE, PCIBAR1); + __raw_writel(CONFIG_RAMBASE | PCITBATR1_E, PCITBATR1); + + /* Keep a virtual mapping to IO/config space active */ + iospace = (unsigned long) ioremap(PCI_IO_PA, PCI_IO_SIZE); + if (iospace == 0) { + pci_free_host_bridge(bridge); + return -ENODEV; + } + pr_info("Coldfire: PCI IO/config window mapped to 0x%x\n", + (u32) iospace); + + /* Turn of PCI reset, and wait for devices to settle */ + __raw_writel(0, PCIGSCR); + set_current_state(TASK_UNINTERRUPTIBLE); + schedule_timeout(msecs_to_jiffies(200)); + + + pci_add_resource(&bridge->windows, &ioport_resource); + pci_add_resource(&bridge->windows, &iomem_resource); + pci_add_resource(&bridge->windows, &busn_resource); + bridge->dev.parent = NULL; + bridge->sysdata = NULL; + bridge->busnr = 0; + bridge->ops = &mcf_pci_ops; + bridge->swizzle_irq = pci_common_swizzle; + bridge->map_irq = mcf_pci_map_irq; + + ret = pci_scan_root_bus_bridge(bridge); + if (ret) { + pci_free_host_bridge(bridge); + return ret; + } + + rootbus = bridge->bus; + + rootbus->resource[0] = &mcf_pci_io; + rootbus->resource[1] = &mcf_pci_mem; + + pci_bus_size_bridges(rootbus); + pci_bus_assign_resources(rootbus); + pci_bus_add_devices(rootbus); + return 0; +} + +subsys_initcall(mcf_pci_init); diff --git a/arch/m68k/coldfire/pit.c b/arch/m68k/coldfire/pit.c new file mode 100644 index 000000000..fd1d9c915 --- /dev/null +++ b/arch/m68k/coldfire/pit.c @@ -0,0 +1,162 @@ +// SPDX-License-Identifier: GPL-2.0 +/***************************************************************************/ + +/* + * pit.c -- Freescale ColdFire PIT timer. Currently this type of + * hardware timer only exists in the Freescale ColdFire + * 5270/5271, 5282 and 5208 CPUs. No doubt newer ColdFire + * family members will probably use it too. + * + * Copyright (C) 1999-2008, Greg Ungerer (gerg@snapgear.com) + * Copyright (C) 2001-2004, SnapGear Inc. (www.snapgear.com) + */ + +/***************************************************************************/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/***************************************************************************/ + +/* + * By default use timer1 as the system clock timer. + */ +#define FREQ ((MCF_CLK / 2) / 64) +#define TA(a) (MCFPIT_BASE1 + (a)) +#define PIT_CYCLES_PER_JIFFY (FREQ / HZ) + +static u32 pit_cnt; + +/* + * Initialize the PIT timer. + * + * This is also called after resume to bring the PIT into operation again. + */ + +static int cf_pit_set_periodic(struct clock_event_device *evt) +{ + __raw_writew(MCFPIT_PCSR_DISABLE, TA(MCFPIT_PCSR)); + __raw_writew(PIT_CYCLES_PER_JIFFY, TA(MCFPIT_PMR)); + __raw_writew(MCFPIT_PCSR_EN | MCFPIT_PCSR_PIE | + MCFPIT_PCSR_OVW | MCFPIT_PCSR_RLD | + MCFPIT_PCSR_CLK64, TA(MCFPIT_PCSR)); + return 0; +} + +static int cf_pit_set_oneshot(struct clock_event_device *evt) +{ + __raw_writew(MCFPIT_PCSR_DISABLE, TA(MCFPIT_PCSR)); + __raw_writew(MCFPIT_PCSR_EN | MCFPIT_PCSR_PIE | + MCFPIT_PCSR_OVW | MCFPIT_PCSR_CLK64, TA(MCFPIT_PCSR)); + return 0; +} + +static int cf_pit_shutdown(struct clock_event_device *evt) +{ + __raw_writew(MCFPIT_PCSR_DISABLE, TA(MCFPIT_PCSR)); + return 0; +} + +/* + * Program the next event in oneshot mode + * + * Delta is given in PIT ticks + */ +static int cf_pit_next_event(unsigned long delta, + struct clock_event_device *evt) +{ + __raw_writew(delta, TA(MCFPIT_PMR)); + return 0; +} + +struct clock_event_device cf_pit_clockevent = { + .name = "pit", + .features = CLOCK_EVT_FEAT_PERIODIC | + CLOCK_EVT_FEAT_ONESHOT, + .set_state_shutdown = cf_pit_shutdown, + .set_state_periodic = cf_pit_set_periodic, + .set_state_oneshot = cf_pit_set_oneshot, + .set_next_event = cf_pit_next_event, + .shift = 32, + .irq = MCF_IRQ_PIT1, +}; + + + +/***************************************************************************/ + +static irqreturn_t pit_tick(int irq, void *dummy) +{ + struct clock_event_device *evt = &cf_pit_clockevent; + u16 pcsr; + + /* Reset the ColdFire timer */ + pcsr = __raw_readw(TA(MCFPIT_PCSR)); + __raw_writew(pcsr | MCFPIT_PCSR_PIF, TA(MCFPIT_PCSR)); + + pit_cnt += PIT_CYCLES_PER_JIFFY; + evt->event_handler(evt); + return IRQ_HANDLED; +} + +/***************************************************************************/ + +static u64 pit_read_clk(struct clocksource *cs) +{ + unsigned long flags; + u32 cycles; + u16 pcntr; + + local_irq_save(flags); + pcntr = __raw_readw(TA(MCFPIT_PCNTR)); + cycles = pit_cnt; + local_irq_restore(flags); + + return cycles + PIT_CYCLES_PER_JIFFY - pcntr; +} + +/***************************************************************************/ + +static struct clocksource pit_clk = { + .name = "pit", + .rating = 100, + .read = pit_read_clk, + .mask = CLOCKSOURCE_MASK(32), +}; + +/***************************************************************************/ + +void hw_timer_init(irq_handler_t handler) +{ + int ret; + + cf_pit_clockevent.cpumask = cpumask_of(smp_processor_id()); + cf_pit_clockevent.mult = div_sc(FREQ, NSEC_PER_SEC, 32); + cf_pit_clockevent.max_delta_ns = + clockevent_delta2ns(0xFFFF, &cf_pit_clockevent); + cf_pit_clockevent.max_delta_ticks = 0xFFFF; + cf_pit_clockevent.min_delta_ns = + clockevent_delta2ns(0x3f, &cf_pit_clockevent); + cf_pit_clockevent.min_delta_ticks = 0x3f; + clockevents_register_device(&cf_pit_clockevent); + + ret = request_irq(MCF_IRQ_PIT1, pit_tick, IRQF_TIMER, "timer", NULL); + if (ret) { + pr_err("Failed to request irq %d (timer): %pe\n", MCF_IRQ_PIT1, + ERR_PTR(ret)); + } + + clocksource_register_hz(&pit_clk, FREQ); +} + +/***************************************************************************/ diff --git a/arch/m68k/coldfire/reset.c b/arch/m68k/coldfire/reset.c new file mode 100644 index 000000000..f30952f0c --- /dev/null +++ b/arch/m68k/coldfire/reset.c @@ -0,0 +1,50 @@ +/* + * reset.c -- common ColdFire SoC reset support + * + * (C) Copyright 2012, Greg Ungerer + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file COPYING in the main directory of this archive + * for more details. + */ + +#include +#include +#include +#include +#include +#include + +/* + * There are 2 common methods amongst the ColdFure parts for reseting + * the CPU. But there are couple of exceptions, the 5272 and the 547x + * have something completely special to them, and we let their specific + * subarch code handle them. + */ + +#ifdef MCFSIM_SYPCR +static void mcf_cpu_reset(void) +{ + local_irq_disable(); + /* Set watchdog to soft reset, and enabled */ + __raw_writeb(0xc0, MCFSIM_SYPCR); + for (;;) + /* wait for watchdog to timeout */; +} +#endif + +#ifdef MCF_RCR +static void mcf_cpu_reset(void) +{ + local_irq_disable(); + __raw_writeb(MCF_RCR_SWRESET, MCF_RCR); +} +#endif + +static int __init mcf_setup_reset(void) +{ + mach_reset = mcf_cpu_reset; + return 0; +} + +arch_initcall(mcf_setup_reset); diff --git a/arch/m68k/coldfire/sltimers.c b/arch/m68k/coldfire/sltimers.c new file mode 100644 index 000000000..5ab81c9c5 --- /dev/null +++ b/arch/m68k/coldfire/sltimers.c @@ -0,0 +1,151 @@ +// SPDX-License-Identifier: GPL-2.0 +/***************************************************************************/ + +/* + * sltimers.c -- generic ColdFire slice timer support. + * + * Copyright (C) 2009-2010, Philippe De Muyter + * based on + * timers.c -- generic ColdFire hardware timer support. + * Copyright (C) 1999-2008, Greg Ungerer + */ + +/***************************************************************************/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/***************************************************************************/ + +#ifdef CONFIG_HIGHPROFILE + +/* + * By default use Slice Timer 1 as the profiler clock timer. + */ +#define PA(a) (MCFSLT_TIMER1 + (a)) + +/* + * Choose a reasonably fast profile timer. Make it an odd value to + * try and get good coverage of kernel operations. + */ +#define PROFILEHZ 1013 + +irqreturn_t mcfslt_profile_tick(int irq, void *dummy) +{ + /* Reset Slice Timer 1 */ + __raw_writel(MCFSLT_SSR_BE | MCFSLT_SSR_TE, PA(MCFSLT_SSR)); + if (current->pid) + profile_tick(CPU_PROFILING); + return IRQ_HANDLED; +} + +void mcfslt_profile_init(void) +{ + int ret; + + printk(KERN_INFO "PROFILE: lodging TIMER 1 @ %dHz as profile timer\n", + PROFILEHZ); + + ret = request_irq(MCF_IRQ_PROFILER, mcfslt_profile_tick, IRQF_TIMER, + "profile timer", NULL); + if (ret) { + pr_err("Failed to request irq %d (profile timer): %pe\n", + MCF_IRQ_PROFILER, ERR_PTR(ret)); + } + + /* Set up TIMER 2 as high speed profile clock */ + __raw_writel(MCF_BUSCLK / PROFILEHZ - 1, PA(MCFSLT_STCNT)); + __raw_writel(MCFSLT_SCR_RUN | MCFSLT_SCR_IEN | MCFSLT_SCR_TEN, + PA(MCFSLT_SCR)); + +} + +#endif /* CONFIG_HIGHPROFILE */ + +/***************************************************************************/ + +/* + * By default use Slice Timer 0 as the system clock timer. + */ +#define TA(a) (MCFSLT_TIMER0 + (a)) + +static u32 mcfslt_cycles_per_jiffy; +static u32 mcfslt_cnt; + +static irq_handler_t timer_interrupt; + +static irqreturn_t mcfslt_tick(int irq, void *dummy) +{ + /* Reset Slice Timer 0 */ + __raw_writel(MCFSLT_SSR_BE | MCFSLT_SSR_TE, TA(MCFSLT_SSR)); + mcfslt_cnt += mcfslt_cycles_per_jiffy; + return timer_interrupt(irq, dummy); +} + +static u64 mcfslt_read_clk(struct clocksource *cs) +{ + unsigned long flags; + u32 cycles, scnt; + + local_irq_save(flags); + scnt = __raw_readl(TA(MCFSLT_SCNT)); + cycles = mcfslt_cnt; + if (__raw_readl(TA(MCFSLT_SSR)) & MCFSLT_SSR_TE) { + cycles += mcfslt_cycles_per_jiffy; + scnt = __raw_readl(TA(MCFSLT_SCNT)); + } + local_irq_restore(flags); + + /* subtract because slice timers count down */ + return cycles + ((mcfslt_cycles_per_jiffy - 1) - scnt); +} + +static struct clocksource mcfslt_clk = { + .name = "slt", + .rating = 250, + .read = mcfslt_read_clk, + .mask = CLOCKSOURCE_MASK(32), + .flags = CLOCK_SOURCE_IS_CONTINUOUS, +}; + +void hw_timer_init(irq_handler_t handler) +{ + int r; + + mcfslt_cycles_per_jiffy = MCF_BUSCLK / HZ; + /* + * The coldfire slice timer (SLT) runs from STCNT to 0 included, + * then STCNT again and so on. It counts thus actually + * STCNT + 1 steps for 1 tick, not STCNT. So if you want + * n cycles, initialize STCNT with n - 1. + */ + __raw_writel(mcfslt_cycles_per_jiffy - 1, TA(MCFSLT_STCNT)); + __raw_writel(MCFSLT_SCR_RUN | MCFSLT_SCR_IEN | MCFSLT_SCR_TEN, + TA(MCFSLT_SCR)); + /* initialize mcfslt_cnt knowing that slice timers count down */ + mcfslt_cnt = mcfslt_cycles_per_jiffy; + + timer_interrupt = handler; + r = request_irq(MCF_IRQ_TIMER, mcfslt_tick, IRQF_TIMER, "timer", NULL); + if (r) { + pr_err("Failed to request irq %d (timer): %pe\n", MCF_IRQ_TIMER, + ERR_PTR(r)); + } + + clocksource_register_hz(&mcfslt_clk, MCF_BUSCLK); + +#ifdef CONFIG_HIGHPROFILE + mcfslt_profile_init(); +#endif +} diff --git a/arch/m68k/coldfire/stmark2.c b/arch/m68k/coldfire/stmark2.c new file mode 100644 index 000000000..8b5af9c83 --- /dev/null +++ b/arch/m68k/coldfire/stmark2.c @@ -0,0 +1,124 @@ +/* + * stmark2.c -- Support for Sysam AMCORE open board + * + * (C) Copyright 2017, Angelo Dureghello + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file COPYING in the main directory of this archive + * for more details. + */ + +#include +#include +#include +#include +#include +#include +#include + +/* + * Partitioning of parallel NOR flash (39VF3201B) + */ +static struct mtd_partition stmark2_partitions[] = { + { + .name = "U-Boot (1024K)", + .size = 0x100000, + .offset = 0x0 + }, { + .name = "Kernel+initramfs (7168K)", + .size = 0x700000, + .offset = MTDPART_OFS_APPEND + }, { + .name = "Flash Free Space (8192K)", + .size = MTDPART_SIZ_FULL, + .offset = MTDPART_OFS_APPEND + } +}; + +static struct flash_platform_data stmark2_spi_flash_data = { + .name = "is25lp128", + .parts = stmark2_partitions, + .nr_parts = ARRAY_SIZE(stmark2_partitions), + .type = "is25lp128", +}; + +static struct spi_board_info stmark2_board_info[] __initdata = { + { + .modalias = "m25p80", + .max_speed_hz = 5000000, + .bus_num = 0, + .chip_select = 1, + .platform_data = &stmark2_spi_flash_data, + .mode = SPI_MODE_3, + } +}; + +/* SPI controller data, SPI (0) */ +static struct fsl_dspi_platform_data dspi_spi0_info = { + .cs_num = 4, + .bus_num = 0, + .sck_cs_delay = 100, + .cs_sck_delay = 100, +}; + +static struct resource dspi_spi0_resource[] = { + [0] = { + .start = MCFDSPI_BASE0, + .end = MCFDSPI_BASE0 + 0xFF, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = 12, + .end = 13, + .flags = IORESOURCE_DMA, + }, + [2] = { + .start = MCF_IRQ_DSPI0, + .end = MCF_IRQ_DSPI0, + .flags = IORESOURCE_IRQ, + }, +}; + +static u64 stmark2_dspi_mask = DMA_BIT_MASK(32); + +/* SPI controller, id = bus number */ +static struct platform_device dspi_spi0_device = { + .name = "fsl-dspi", + .id = 0, + .num_resources = ARRAY_SIZE(dspi_spi0_resource), + .resource = dspi_spi0_resource, + .dev = { + .platform_data = &dspi_spi0_info, + .dma_mask = &stmark2_dspi_mask, + .coherent_dma_mask = DMA_BIT_MASK(32), + }, +}; + +static struct platform_device *stmark2_devices[] __initdata = { + &dspi_spi0_device, +}; + +/* + * Note: proper pin-mux setup is mandatory for proper SPI functionality. + */ +static int __init init_stmark2(void) +{ + /* DSPI0, all pins as DSPI, and using CS1 */ + __raw_writeb(0x80, MCFGPIO_PAR_DSPIOWL); + __raw_writeb(0xfc, MCFGPIO_PAR_DSPIOWH); + + /* Board gpio setup */ + __raw_writeb(0x00, MCFGPIO_PAR_BE); + __raw_writeb(0x00, MCFGPIO_PAR_FBCTL); + __raw_writeb(0x00, MCFGPIO_PAR_CS); + __raw_writeb(0x00, MCFGPIO_PAR_CANI2C); + + platform_add_devices(stmark2_devices, ARRAY_SIZE(stmark2_devices)); + + spi_register_board_info(stmark2_board_info, + ARRAY_SIZE(stmark2_board_info)); + + return 0; +} + +late_initcall(init_stmark2); diff --git a/arch/m68k/coldfire/timers.c b/arch/m68k/coldfire/timers.c new file mode 100644 index 000000000..b8301fddf --- /dev/null +++ b/arch/m68k/coldfire/timers.c @@ -0,0 +1,195 @@ +// SPDX-License-Identifier: GPL-2.0 +/***************************************************************************/ + +/* + * timers.c -- generic ColdFire hardware timer support. + * + * Copyright (C) 1999-2008, Greg Ungerer + */ + +/***************************************************************************/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/***************************************************************************/ + +/* + * By default use timer1 as the system clock timer. + */ +#define FREQ (MCF_BUSCLK / 16) +#define TA(a) (MCFTIMER_BASE1 + (a)) + +/* + * These provide the underlying interrupt vector support. + * Unfortunately it is a little different on each ColdFire. + */ +void coldfire_profile_init(void); + +#if defined(CONFIG_M53xx) || defined(CONFIG_M5441x) +#define __raw_readtrr __raw_readl +#define __raw_writetrr __raw_writel +#else +#define __raw_readtrr __raw_readw +#define __raw_writetrr __raw_writew +#endif + +static u32 mcftmr_cycles_per_jiffy; +static u32 mcftmr_cnt; + +static irq_handler_t timer_interrupt; + +/***************************************************************************/ + +static void init_timer_irq(void) +{ +#ifdef MCFSIM_ICR_AUTOVEC + /* Timer1 is always used as system timer */ + writeb(MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL6 | MCFSIM_ICR_PRI3, + MCFSIM_TIMER1ICR); + mcf_mapirq2imr(MCF_IRQ_TIMER, MCFINTC_TIMER1); + +#ifdef CONFIG_HIGHPROFILE + /* Timer2 is to be used as a high speed profile timer */ + writeb(MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL7 | MCFSIM_ICR_PRI3, + MCFSIM_TIMER2ICR); + mcf_mapirq2imr(MCF_IRQ_PROFILER, MCFINTC_TIMER2); +#endif +#endif /* MCFSIM_ICR_AUTOVEC */ +} + +/***************************************************************************/ + +static irqreturn_t mcftmr_tick(int irq, void *dummy) +{ + /* Reset the ColdFire timer */ + __raw_writeb(MCFTIMER_TER_CAP | MCFTIMER_TER_REF, TA(MCFTIMER_TER)); + + mcftmr_cnt += mcftmr_cycles_per_jiffy; + return timer_interrupt(irq, dummy); +} + +/***************************************************************************/ + +static u64 mcftmr_read_clk(struct clocksource *cs) +{ + unsigned long flags; + u32 cycles; + u16 tcn; + + local_irq_save(flags); + tcn = __raw_readw(TA(MCFTIMER_TCN)); + cycles = mcftmr_cnt; + local_irq_restore(flags); + + return cycles + tcn; +} + +/***************************************************************************/ + +static struct clocksource mcftmr_clk = { + .name = "tmr", + .rating = 250, + .read = mcftmr_read_clk, + .mask = CLOCKSOURCE_MASK(32), + .flags = CLOCK_SOURCE_IS_CONTINUOUS, +}; + +/***************************************************************************/ + +void hw_timer_init(irq_handler_t handler) +{ + int r; + + __raw_writew(MCFTIMER_TMR_DISABLE, TA(MCFTIMER_TMR)); + mcftmr_cycles_per_jiffy = FREQ / HZ; + /* + * The coldfire timer runs from 0 to TRR included, then 0 + * again and so on. It counts thus actually TRR + 1 steps + * for 1 tick, not TRR. So if you want n cycles, + * initialize TRR with n - 1. + */ + __raw_writetrr(mcftmr_cycles_per_jiffy - 1, TA(MCFTIMER_TRR)); + __raw_writew(MCFTIMER_TMR_ENORI | MCFTIMER_TMR_CLK16 | + MCFTIMER_TMR_RESTART | MCFTIMER_TMR_ENABLE, TA(MCFTIMER_TMR)); + + clocksource_register_hz(&mcftmr_clk, FREQ); + + timer_interrupt = handler; + init_timer_irq(); + r = request_irq(MCF_IRQ_TIMER, mcftmr_tick, IRQF_TIMER, "timer", NULL); + if (r) { + pr_err("Failed to request irq %d (timer): %pe\n", MCF_IRQ_TIMER, + ERR_PTR(r)); + } + +#ifdef CONFIG_HIGHPROFILE + coldfire_profile_init(); +#endif +} + +/***************************************************************************/ +#ifdef CONFIG_HIGHPROFILE +/***************************************************************************/ + +/* + * By default use timer2 as the profiler clock timer. + */ +#define PA(a) (MCFTIMER_BASE2 + (a)) + +/* + * Choose a reasonably fast profile timer. Make it an odd value to + * try and get good coverage of kernel operations. + */ +#define PROFILEHZ 1013 + +/* + * Use the other timer to provide high accuracy profiling info. + */ +irqreturn_t coldfire_profile_tick(int irq, void *dummy) +{ + /* Reset ColdFire timer2 */ + __raw_writeb(MCFTIMER_TER_CAP | MCFTIMER_TER_REF, PA(MCFTIMER_TER)); + if (current->pid) + profile_tick(CPU_PROFILING); + return IRQ_HANDLED; +} + +/***************************************************************************/ + +void coldfire_profile_init(void) +{ + int ret; + + printk(KERN_INFO "PROFILE: lodging TIMER2 @ %dHz as profile timer\n", + PROFILEHZ); + + /* Set up TIMER 2 as high speed profile clock */ + __raw_writew(MCFTIMER_TMR_DISABLE, PA(MCFTIMER_TMR)); + + __raw_writetrr(((MCF_BUSCLK / 16) / PROFILEHZ), PA(MCFTIMER_TRR)); + __raw_writew(MCFTIMER_TMR_ENORI | MCFTIMER_TMR_CLK16 | + MCFTIMER_TMR_RESTART | MCFTIMER_TMR_ENABLE, PA(MCFTIMER_TMR)); + + ret = request_irq(MCF_IRQ_PROFILER, coldfire_profile_tick, IRQF_TIMER, + "profile timer", NULL); + if (ret) { + pr_err("Failed to request irq %d (profile timer): %pe\n", + MCF_IRQ_PROFILER, ERR_PTR(ret)); + } +} + +/***************************************************************************/ +#endif /* CONFIG_HIGHPROFILE */ +/***************************************************************************/ diff --git a/arch/m68k/coldfire/vectors.c b/arch/m68k/coldfire/vectors.c new file mode 100644 index 000000000..3bf0d69ee --- /dev/null +++ b/arch/m68k/coldfire/vectors.c @@ -0,0 +1,71 @@ +// SPDX-License-Identifier: GPL-2.0 +/***************************************************************************/ + +/* + * vectors.c -- high level trap setup for ColdFire + * + * Copyright (C) 1999-2007, Greg Ungerer + */ + +/***************************************************************************/ + +#include +#include +#include +#include +#include +#include +#include +#include + +/***************************************************************************/ + +#ifdef TRAP_DBG_INTERRUPT + +asmlinkage void dbginterrupt_c(struct frame *fp) +{ + extern void dump(struct pt_regs *fp); + printk(KERN_DEBUG "%s(%d): BUS ERROR TRAP\n", __FILE__, __LINE__); + dump((struct pt_regs *) fp); + asm("halt"); +} + +#endif + +/***************************************************************************/ + +/* Assembler routines */ +asmlinkage void buserr(void); +asmlinkage void trap(void); +asmlinkage void system_call(void); +asmlinkage void inthandler(void); + +void __init trap_init(void) +{ + int i; + + /* + * There is a common trap handler and common interrupt + * handler that handle almost every vector. We treat + * the system call and bus error special, they get their + * own first level handlers. + */ + for (i = 3; (i <= 23); i++) + _ramvec[i] = trap; + for (i = 33; (i <= 63); i++) + _ramvec[i] = trap; + for (i = 24; (i <= 31); i++) + _ramvec[i] = inthandler; + for (i = 64; (i < 255); i++) + _ramvec[i] = inthandler; + _ramvec[255] = 0; + + _ramvec[2] = buserr; + _ramvec[32] = system_call; + +#ifdef TRAP_DBG_INTERRUPT + _ramvec[12] = dbginterrupt; +#endif +} + +/***************************************************************************/ diff --git a/arch/m68k/configs/amcore_defconfig b/arch/m68k/configs/amcore_defconfig new file mode 100644 index 000000000..3a84f24d4 --- /dev/null +++ b/arch/m68k/configs/amcore_defconfig @@ -0,0 +1,97 @@ +CONFIG_LOCALVERSION="amcore-002" +CONFIG_DEFAULT_HOSTNAME="amcore" +CONFIG_SYSVIPC=y +# CONFIG_FHANDLE is not set +# CONFIG_USELIB is not set +CONFIG_LOG_BUF_SHIFT=14 +CONFIG_CC_OPTIMIZE_FOR_SIZE=y +# CONFIG_AIO is not set +# CONFIG_ADVISE_SYSCALLS is not set +# CONFIG_MEMBARRIER is not set +CONFIG_EMBEDDED=y +# CONFIG_VM_EVENT_COUNTERS is not set +# CONFIG_SLUB_DEBUG is not set +# CONFIG_COMPAT_BRK is not set +# CONFIG_BLK_DEV_BSG is not set +# CONFIG_MMU is not set +CONFIG_M5307=y +CONFIG_AMCORE=y +CONFIG_UBOOT=y +CONFIG_RAMSIZE=0x1000000 +CONFIG_KERNELBASE=0x20000 +CONFIG_NOMMU_INITIAL_TRIM_EXCESS=0 +CONFIG_BINFMT_FLAT=y +# CONFIG_COREDUMP is not set +CONFIG_NET=y +CONFIG_PACKET=y +CONFIG_UNIX=y +CONFIG_INET=y +CONFIG_SYN_COOKIES=y +# CONFIG_INET_XFRM_MODE_TRANSPORT is not set +# CONFIG_INET_XFRM_MODE_TUNNEL is not set +# CONFIG_INET_XFRM_MODE_BEET is not set +# CONFIG_IPV6 is not set +# CONFIG_WIRELESS is not set +# CONFIG_UEVENT_HELPER is not set +# CONFIG_FW_LOADER is not set +# CONFIG_ALLOW_DEV_COREDUMP is not set +CONFIG_CONNECTOR=y +CONFIG_MTD=y +CONFIG_MTD_BLOCK=y +CONFIG_MTD_CFI=y +CONFIG_MTD_JEDECPROBE=y +CONFIG_MTD_CFI_ADV_OPTIONS=y +CONFIG_MTD_CFI_LE_BYTE_SWAP=y +CONFIG_MTD_CFI_GEOMETRY=y +# CONFIG_MTD_CFI_I2 is not set +CONFIG_MTD_CFI_AMDSTD=y +CONFIG_MTD_CFI_STAA=y +CONFIG_MTD_ROM=y +CONFIG_MTD_COMPLEX_MAPPINGS=y +CONFIG_MTD_PHYSMAP=y +CONFIG_MTD_UCLINUX=y +CONFIG_MTD_PLATRAM=y +CONFIG_BLK_DEV_RAM=y +CONFIG_NETDEVICES=y +CONFIG_DM9000=y +# CONFIG_WLAN is not set +# CONFIG_INPUT is not set +# CONFIG_SERIO is not set +# CONFIG_VT is not set +# CONFIG_UNIX98_PTYS is not set +# CONFIG_DEVMEM is not set +# CONFIG_DEVKMEM is not set +CONFIG_SERIAL_MCF=y +CONFIG_SERIAL_MCF_BAUDRATE=115200 +CONFIG_SERIAL_MCF_CONSOLE=y +# CONFIG_HW_RANDOM is not set +CONFIG_I2C=y +# CONFIG_I2C_COMPAT is not set +CONFIG_I2C_CHARDEV=y +# CONFIG_I2C_HELPER_AUTO is not set +CONFIG_I2C_IMX=y +CONFIG_GPIO_SYSFS=y +# CONFIG_HWMON is not set +# CONFIG_USB_SUPPORT is not set +CONFIG_RTC_CLASS=y +# CONFIG_RTC_SYSTOHC is not set +CONFIG_RTC_DRV_DS1307=y +# CONFIG_FILE_LOCKING is not set +# CONFIG_DNOTIFY is not set +# CONFIG_INOTIFY_USER is not set +CONFIG_FSCACHE=y +# CONFIG_PROC_SYSCTL is not set +CONFIG_JFFS2_FS=y +CONFIG_ROMFS_FS=y +CONFIG_ROMFS_BACKED_BY_BOTH=y +# CONFIG_NETWORK_FILESYSTEMS is not set +CONFIG_PRINTK_TIME=y +# CONFIG_ENABLE_MUST_CHECK is not set +# CONFIG_SECTION_MISMATCH_WARN_ONLY is not set +CONFIG_PANIC_ON_OOPS=y +# CONFIG_SCHED_DEBUG is not set +# CONFIG_DEBUG_BUGVERBOSE is not set +# CONFIG_CRYPTO_ECHAINIV is not set +CONFIG_CRYPTO_ANSI_CPRNG=y +# CONFIG_CRYPTO_HW is not set +CONFIG_CRC16=y diff --git a/arch/m68k/configs/amiga_defconfig b/arch/m68k/configs/amiga_defconfig new file mode 100644 index 000000000..f9f4fa595 --- /dev/null +++ b/arch/m68k/configs/amiga_defconfig @@ -0,0 +1,661 @@ +CONFIG_LOCALVERSION="-amiga" +CONFIG_SYSVIPC=y +CONFIG_POSIX_MQUEUE=y +CONFIG_BSD_PROCESS_ACCT=y +CONFIG_BSD_PROCESS_ACCT_V3=y +CONFIG_LOG_BUF_SHIFT=16 +# CONFIG_UTS_NS is not set +# CONFIG_IPC_NS is not set +# CONFIG_PID_NS is not set +# CONFIG_NET_NS is not set +CONFIG_BLK_DEV_INITRD=y +CONFIG_CC_OPTIMIZE_FOR_SIZE=y +CONFIG_USERFAULTFD=y +CONFIG_SLAB=y +CONFIG_KEXEC=y +CONFIG_BOOTINFO_PROC=y +CONFIG_M68020=y +CONFIG_M68030=y +CONFIG_M68040=y +CONFIG_M68060=y +CONFIG_AMIGA=y +CONFIG_ZORRO=y +CONFIG_AMIGA_PCMCIA=y +CONFIG_ZORRO_NAMES=y +CONFIG_HEARTBEAT=y +CONFIG_PROC_HARDWARE=y +CONFIG_AMIGA_BUILTIN_SERIAL=y +CONFIG_SERIAL_CONSOLE=y +CONFIG_MODULES=y +CONFIG_MODULE_UNLOAD=y +CONFIG_PARTITION_ADVANCED=y +CONFIG_ATARI_PARTITION=y +CONFIG_MAC_PARTITION=y +CONFIG_BSD_DISKLABEL=y +CONFIG_MINIX_SUBPARTITION=y +CONFIG_SOLARIS_X86_PARTITION=y +CONFIG_UNIXWARE_DISKLABEL=y +CONFIG_SUN_PARTITION=y +# CONFIG_EFI_PARTITION is not set +CONFIG_SYSV68_PARTITION=y +CONFIG_MQ_IOSCHED_DEADLINE=m +CONFIG_MQ_IOSCHED_KYBER=m +CONFIG_IOSCHED_BFQ=m +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +CONFIG_BINFMT_AOUT=m +CONFIG_BINFMT_MISC=m +# CONFIG_COMPACTION is not set +CONFIG_CLEANCACHE=y +CONFIG_ZPOOL=m +CONFIG_NET=y +CONFIG_PACKET=y +CONFIG_PACKET_DIAG=m +CONFIG_UNIX=y +CONFIG_UNIX_DIAG=m +CONFIG_TLS=m +CONFIG_XFRM_MIGRATE=y +CONFIG_NET_KEY=y +CONFIG_XDP_SOCKETS=y +CONFIG_XDP_SOCKETS_DIAG=m +CONFIG_INET=y +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +CONFIG_IP_PNP_BOOTP=y +CONFIG_IP_PNP_RARP=y +CONFIG_NET_IPIP=m +CONFIG_NET_IPGRE_DEMUX=m +CONFIG_NET_IPGRE=m +CONFIG_NET_IPVTI=m +CONFIG_NET_FOU_IP_TUNNELS=y +CONFIG_INET_AH=m +CONFIG_INET_ESP=m +CONFIG_INET_ESP_OFFLOAD=m +CONFIG_INET_IPCOMP=m +CONFIG_INET_DIAG=m +CONFIG_INET_UDP_DIAG=m +CONFIG_INET_RAW_DIAG=m +CONFIG_IPV6=m +CONFIG_IPV6_ROUTER_PREF=y +CONFIG_INET6_AH=m +CONFIG_INET6_ESP=m +CONFIG_INET6_ESP_OFFLOAD=m +CONFIG_INET6_IPCOMP=m +CONFIG_IPV6_ILA=m +CONFIG_IPV6_VTI=m +CONFIG_IPV6_GRE=m +CONFIG_NETFILTER=y +CONFIG_NF_CONNTRACK=m +CONFIG_NF_LOG_NETDEV=m +CONFIG_NF_CONNTRACK_ZONES=y +# CONFIG_NF_CONNTRACK_PROCFS is not set +# CONFIG_NF_CT_PROTO_DCCP is not set +CONFIG_NF_CONNTRACK_AMANDA=m +CONFIG_NF_CONNTRACK_FTP=m +CONFIG_NF_CONNTRACK_H323=m +CONFIG_NF_CONNTRACK_IRC=m +CONFIG_NF_CONNTRACK_NETBIOS_NS=m +CONFIG_NF_CONNTRACK_SNMP=m +CONFIG_NF_CONNTRACK_PPTP=m +CONFIG_NF_CONNTRACK_SANE=m +CONFIG_NF_CONNTRACK_SIP=m +CONFIG_NF_CONNTRACK_TFTP=m +CONFIG_NF_TABLES=m +CONFIG_NF_TABLES_INET=y +CONFIG_NF_TABLES_NETDEV=y +CONFIG_NFT_NUMGEN=m +CONFIG_NFT_CT=m +CONFIG_NFT_FLOW_OFFLOAD=m +CONFIG_NFT_COUNTER=m +CONFIG_NFT_CONNLIMIT=m +CONFIG_NFT_LOG=m +CONFIG_NFT_LIMIT=m +CONFIG_NFT_MASQ=m +CONFIG_NFT_REDIR=m +CONFIG_NFT_NAT=m +CONFIG_NFT_TUNNEL=m +CONFIG_NFT_OBJREF=m +CONFIG_NFT_QUEUE=m +CONFIG_NFT_QUOTA=m +CONFIG_NFT_REJECT=m +CONFIG_NFT_COMPAT=m +CONFIG_NFT_HASH=m +CONFIG_NFT_FIB_INET=m +CONFIG_NFT_XFRM=m +CONFIG_NFT_SOCKET=m +CONFIG_NFT_OSF=m +CONFIG_NFT_TPROXY=m +CONFIG_NFT_SYNPROXY=m +CONFIG_NFT_DUP_NETDEV=m +CONFIG_NFT_FWD_NETDEV=m +CONFIG_NFT_FIB_NETDEV=m +CONFIG_NF_FLOW_TABLE_INET=m +CONFIG_NF_FLOW_TABLE=m +CONFIG_NETFILTER_XT_SET=m +CONFIG_NETFILTER_XT_TARGET_CHECKSUM=m +CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m +CONFIG_NETFILTER_XT_TARGET_CONNMARK=m +CONFIG_NETFILTER_XT_TARGET_DSCP=m +CONFIG_NETFILTER_XT_TARGET_HMARK=m +CONFIG_NETFILTER_XT_TARGET_IDLETIMER=m +CONFIG_NETFILTER_XT_TARGET_LOG=m +CONFIG_NETFILTER_XT_TARGET_MARK=m +CONFIG_NETFILTER_XT_TARGET_NFLOG=m +CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m +CONFIG_NETFILTER_XT_TARGET_NOTRACK=m +CONFIG_NETFILTER_XT_TARGET_TEE=m +CONFIG_NETFILTER_XT_TARGET_TPROXY=m +CONFIG_NETFILTER_XT_TARGET_TRACE=m +CONFIG_NETFILTER_XT_TARGET_TCPMSS=m +CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP=m +CONFIG_NETFILTER_XT_MATCH_ADDRTYPE=m +CONFIG_NETFILTER_XT_MATCH_BPF=m +CONFIG_NETFILTER_XT_MATCH_CLUSTER=m +CONFIG_NETFILTER_XT_MATCH_COMMENT=m +CONFIG_NETFILTER_XT_MATCH_CONNBYTES=m +CONFIG_NETFILTER_XT_MATCH_CONNLABEL=m +CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=m +CONFIG_NETFILTER_XT_MATCH_CONNMARK=m +CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m +CONFIG_NETFILTER_XT_MATCH_DEVGROUP=m +CONFIG_NETFILTER_XT_MATCH_DSCP=m +CONFIG_NETFILTER_XT_MATCH_ESP=m +CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=m +CONFIG_NETFILTER_XT_MATCH_HELPER=m +CONFIG_NETFILTER_XT_MATCH_IPCOMP=m +CONFIG_NETFILTER_XT_MATCH_IPRANGE=m +CONFIG_NETFILTER_XT_MATCH_LENGTH=m +CONFIG_NETFILTER_XT_MATCH_LIMIT=m +CONFIG_NETFILTER_XT_MATCH_MAC=m +CONFIG_NETFILTER_XT_MATCH_MARK=m +CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m +CONFIG_NETFILTER_XT_MATCH_NFACCT=m +CONFIG_NETFILTER_XT_MATCH_OSF=m +CONFIG_NETFILTER_XT_MATCH_OWNER=m +CONFIG_NETFILTER_XT_MATCH_POLICY=m +CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m +CONFIG_NETFILTER_XT_MATCH_QUOTA=m +CONFIG_NETFILTER_XT_MATCH_RATEEST=m +CONFIG_NETFILTER_XT_MATCH_REALM=m +CONFIG_NETFILTER_XT_MATCH_RECENT=m +CONFIG_NETFILTER_XT_MATCH_SOCKET=m +CONFIG_NETFILTER_XT_MATCH_STATE=m +CONFIG_NETFILTER_XT_MATCH_STATISTIC=m +CONFIG_NETFILTER_XT_MATCH_STRING=m +CONFIG_NETFILTER_XT_MATCH_TCPMSS=m +CONFIG_NETFILTER_XT_MATCH_TIME=m +CONFIG_NETFILTER_XT_MATCH_U32=m +CONFIG_IP_SET=m +CONFIG_IP_SET_BITMAP_IP=m +CONFIG_IP_SET_BITMAP_IPMAC=m +CONFIG_IP_SET_BITMAP_PORT=m +CONFIG_IP_SET_HASH_IP=m +CONFIG_IP_SET_HASH_IPMARK=m +CONFIG_IP_SET_HASH_IPPORT=m +CONFIG_IP_SET_HASH_IPPORTIP=m +CONFIG_IP_SET_HASH_IPPORTNET=m +CONFIG_IP_SET_HASH_IPMAC=m +CONFIG_IP_SET_HASH_MAC=m +CONFIG_IP_SET_HASH_NETPORTNET=m +CONFIG_IP_SET_HASH_NET=m +CONFIG_IP_SET_HASH_NETNET=m +CONFIG_IP_SET_HASH_NETPORT=m +CONFIG_IP_SET_HASH_NETIFACE=m +CONFIG_IP_SET_LIST_SET=m +CONFIG_NFT_DUP_IPV4=m +CONFIG_NFT_FIB_IPV4=m +CONFIG_NF_TABLES_ARP=y +CONFIG_NF_FLOW_TABLE_IPV4=m +CONFIG_NF_LOG_ARP=m +CONFIG_IP_NF_IPTABLES=m +CONFIG_IP_NF_MATCH_AH=m +CONFIG_IP_NF_MATCH_ECN=m +CONFIG_IP_NF_MATCH_RPFILTER=m +CONFIG_IP_NF_MATCH_TTL=m +CONFIG_IP_NF_FILTER=m +CONFIG_IP_NF_TARGET_REJECT=m +CONFIG_IP_NF_TARGET_SYNPROXY=m +CONFIG_IP_NF_NAT=m +CONFIG_IP_NF_TARGET_MASQUERADE=m +CONFIG_IP_NF_TARGET_NETMAP=m +CONFIG_IP_NF_TARGET_REDIRECT=m +CONFIG_IP_NF_MANGLE=m +CONFIG_IP_NF_TARGET_CLUSTERIP=m +CONFIG_IP_NF_TARGET_ECN=m +CONFIG_IP_NF_TARGET_TTL=m +CONFIG_IP_NF_RAW=m +CONFIG_IP_NF_ARPTABLES=m +CONFIG_IP_NF_ARPFILTER=m +CONFIG_IP_NF_ARP_MANGLE=m +CONFIG_NFT_DUP_IPV6=m +CONFIG_NFT_FIB_IPV6=m +CONFIG_NF_FLOW_TABLE_IPV6=m +CONFIG_IP6_NF_IPTABLES=m +CONFIG_IP6_NF_MATCH_AH=m +CONFIG_IP6_NF_MATCH_EUI64=m +CONFIG_IP6_NF_MATCH_FRAG=m +CONFIG_IP6_NF_MATCH_OPTS=m +CONFIG_IP6_NF_MATCH_HL=m +CONFIG_IP6_NF_MATCH_IPV6HEADER=m +CONFIG_IP6_NF_MATCH_MH=m +CONFIG_IP6_NF_MATCH_RPFILTER=m +CONFIG_IP6_NF_MATCH_RT=m +CONFIG_IP6_NF_MATCH_SRH=m +CONFIG_IP6_NF_TARGET_HL=m +CONFIG_IP6_NF_FILTER=m +CONFIG_IP6_NF_TARGET_REJECT=m +CONFIG_IP6_NF_TARGET_SYNPROXY=m +CONFIG_IP6_NF_MANGLE=m +CONFIG_IP6_NF_RAW=m +CONFIG_IP6_NF_NAT=m +CONFIG_IP6_NF_TARGET_MASQUERADE=m +CONFIG_IP6_NF_TARGET_NPT=m +CONFIG_NF_TABLES_BRIDGE=m +CONFIG_NFT_BRIDGE_META=m +CONFIG_NFT_BRIDGE_REJECT=m +CONFIG_NF_LOG_BRIDGE=m +CONFIG_NF_CONNTRACK_BRIDGE=m +CONFIG_BRIDGE_NF_EBTABLES=m +CONFIG_BRIDGE_EBT_BROUTE=m +CONFIG_BRIDGE_EBT_T_FILTER=m +CONFIG_BRIDGE_EBT_T_NAT=m +CONFIG_BRIDGE_EBT_802_3=m +CONFIG_BRIDGE_EBT_AMONG=m +CONFIG_BRIDGE_EBT_ARP=m +CONFIG_BRIDGE_EBT_IP=m +CONFIG_BRIDGE_EBT_IP6=m +CONFIG_BRIDGE_EBT_LIMIT=m +CONFIG_BRIDGE_EBT_MARK=m +CONFIG_BRIDGE_EBT_PKTTYPE=m +CONFIG_BRIDGE_EBT_STP=m +CONFIG_BRIDGE_EBT_VLAN=m +CONFIG_BRIDGE_EBT_ARPREPLY=m +CONFIG_BRIDGE_EBT_DNAT=m +CONFIG_BRIDGE_EBT_MARK_T=m +CONFIG_BRIDGE_EBT_REDIRECT=m +CONFIG_BRIDGE_EBT_SNAT=m +CONFIG_BRIDGE_EBT_LOG=m +CONFIG_BRIDGE_EBT_NFLOG=m +CONFIG_IP_DCCP=m +# CONFIG_IP_DCCP_CCID3 is not set +CONFIG_SCTP_COOKIE_HMAC_SHA1=y +CONFIG_RDS=m +CONFIG_RDS_TCP=m +CONFIG_L2TP=m +CONFIG_BRIDGE=m +CONFIG_ATALK=m +CONFIG_6LOWPAN=m +CONFIG_6LOWPAN_GHC_EXT_HDR_HOP=m +CONFIG_6LOWPAN_GHC_UDP=m +CONFIG_6LOWPAN_GHC_ICMPV6=m +CONFIG_6LOWPAN_GHC_EXT_HDR_DEST=m +CONFIG_6LOWPAN_GHC_EXT_HDR_FRAG=m +CONFIG_6LOWPAN_GHC_EXT_HDR_ROUTE=m +CONFIG_DNS_RESOLVER=y +CONFIG_BATMAN_ADV=m +# CONFIG_BATMAN_ADV_BATMAN_V is not set +CONFIG_BATMAN_ADV_NC=y +CONFIG_NETLINK_DIAG=m +CONFIG_MPLS=y +CONFIG_NET_MPLS_GSO=m +CONFIG_MPLS_ROUTING=m +CONFIG_MPLS_IPTUNNEL=m +CONFIG_NET_NSH=m +CONFIG_AF_KCM=m +# CONFIG_WIRELESS is not set +CONFIG_PSAMPLE=m +CONFIG_NET_IFE=m +CONFIG_DEVTMPFS=y +CONFIG_DEVTMPFS_MOUNT=y +CONFIG_TEST_ASYNC_DRIVER_PROBE=m +CONFIG_CONNECTOR=m +CONFIG_PARPORT=m +CONFIG_PARPORT_AMIGA=m +CONFIG_PARPORT_MFC3=m +CONFIG_PARPORT_1284=y +CONFIG_AMIGA_FLOPPY=y +CONFIG_AMIGA_Z2RAM=y +CONFIG_BLK_DEV_LOOP=y +CONFIG_BLK_DEV_CRYPTOLOOP=m +CONFIG_BLK_DEV_DRBD=m +CONFIG_BLK_DEV_NBD=m +CONFIG_BLK_DEV_RAM=y +CONFIG_CDROM_PKTCDVD=m +CONFIG_ATA_OVER_ETH=m +CONFIG_DUMMY_IRQ=m +CONFIG_IDE=y +CONFIG_IDE_GD_ATAPI=y +CONFIG_BLK_DEV_IDECD=y +CONFIG_BLK_DEV_GAYLE=y +CONFIG_BLK_DEV_BUDDHA=y +CONFIG_RAID_ATTRS=m +CONFIG_SCSI=y +CONFIG_BLK_DEV_SD=y +CONFIG_CHR_DEV_ST=m +CONFIG_BLK_DEV_SR=y +CONFIG_CHR_DEV_SG=m +CONFIG_SCSI_CONSTANTS=y +CONFIG_SCSI_SAS_ATTRS=m +CONFIG_ISCSI_TCP=m +CONFIG_ISCSI_BOOT_SYSFS=m +CONFIG_A3000_SCSI=y +CONFIG_A2091_SCSI=y +CONFIG_GVP11_SCSI=y +CONFIG_SCSI_A4000T=y +CONFIG_SCSI_ZORRO7XX=y +CONFIG_SCSI_ZORRO_ESP=y +CONFIG_MD=y +CONFIG_MD_LINEAR=m +CONFIG_BLK_DEV_DM=m +CONFIG_DM_UNSTRIPED=m +CONFIG_DM_CRYPT=m +CONFIG_DM_SNAPSHOT=m +CONFIG_DM_THIN_PROVISIONING=m +CONFIG_DM_WRITECACHE=m +CONFIG_DM_ERA=m +CONFIG_DM_CLONE=m +CONFIG_DM_MIRROR=m +CONFIG_DM_RAID=m +CONFIG_DM_ZERO=m +CONFIG_DM_MULTIPATH=m +CONFIG_DM_UEVENT=y +CONFIG_DM_LOG_WRITES=m +CONFIG_DM_INTEGRITY=m +CONFIG_TARGET_CORE=m +CONFIG_TCM_IBLOCK=m +CONFIG_TCM_FILEIO=m +CONFIG_TCM_PSCSI=m +CONFIG_NETDEVICES=y +CONFIG_DUMMY=m +CONFIG_WIREGUARD=m +CONFIG_EQUALIZER=m +CONFIG_NET_TEAM=m +CONFIG_NET_TEAM_MODE_BROADCAST=m +CONFIG_NET_TEAM_MODE_ROUNDROBIN=m +CONFIG_NET_TEAM_MODE_RANDOM=m +CONFIG_NET_TEAM_MODE_ACTIVEBACKUP=m +CONFIG_NET_TEAM_MODE_LOADBALANCE=m +CONFIG_MACVLAN=m +CONFIG_MACVTAP=m +CONFIG_IPVLAN=m +CONFIG_IPVTAP=m +CONFIG_VXLAN=m +CONFIG_GENEVE=m +CONFIG_BAREUDP=m +CONFIG_GTP=m +CONFIG_MACSEC=m +CONFIG_NETCONSOLE=m +CONFIG_NETCONSOLE_DYNAMIC=y +CONFIG_VETH=m +CONFIG_A2065=y +CONFIG_ARIADNE=y +CONFIG_XSURF100=y +CONFIG_HYDRA=y +CONFIG_APNE=y +CONFIG_ZORRO8390=y +CONFIG_PPP=m +CONFIG_PPP_BSDCOMP=m +CONFIG_PPP_DEFLATE=m +CONFIG_PPP_FILTER=y +CONFIG_PPP_MPPE=m +CONFIG_PPPOE=m +CONFIG_PPTP=m +CONFIG_PPPOL2TP=m +CONFIG_PPP_ASYNC=m +CONFIG_PPP_SYNC_TTY=m +CONFIG_SLIP=m +CONFIG_SLIP_COMPRESSED=y +CONFIG_SLIP_SMART=y +CONFIG_SLIP_MODE_SLIP6=y +# CONFIG_WLAN is not set +CONFIG_INPUT_EVDEV=m +CONFIG_KEYBOARD_AMIGA=y +# CONFIG_KEYBOARD_ATKBD is not set +# CONFIG_MOUSE_PS2 is not set +CONFIG_MOUSE_AMIGA=m +CONFIG_INPUT_JOYSTICK=y +CONFIG_JOYSTICK_AMIGA=m +CONFIG_INPUT_MISC=y +CONFIG_INPUT_M68K_BEEP=m +# CONFIG_SERIO is not set +# CONFIG_LEGACY_PTYS is not set +CONFIG_PRINTER=m +# CONFIG_HW_RANDOM is not set +CONFIG_I2C=m +CONFIG_I2C_CHARDEV=m +CONFIG_I2C_ICY=m +CONFIG_NTP_PPS=y +CONFIG_PPS_CLIENT_LDISC=m +CONFIG_PPS_CLIENT_PARPORT=m +CONFIG_PTP_1588_CLOCK=m +CONFIG_HWMON=m +CONFIG_SENSORS_LTC2990=m +CONFIG_FB=y +CONFIG_FB_CIRRUS=y +CONFIG_FB_AMIGA=y +CONFIG_FB_AMIGA_OCS=y +CONFIG_FB_AMIGA_ECS=y +CONFIG_FB_AMIGA_AGA=y +CONFIG_FB_FM2=y +CONFIG_FRAMEBUFFER_CONSOLE=y +CONFIG_LOGO=y +CONFIG_SOUND=m +CONFIG_DMASOUND_PAULA=m +CONFIG_HID=m +CONFIG_HIDRAW=y +CONFIG_UHID=m +# CONFIG_HID_GENERIC is not set +# CONFIG_HID_ITE is not set +# CONFIG_HID_REDRAGON is not set +# CONFIG_USB_SUPPORT is not set +CONFIG_RTC_CLASS=y +# CONFIG_RTC_NVMEM is not set +CONFIG_RTC_DRV_MSM6242=m +CONFIG_RTC_DRV_RP5C01=m +# CONFIG_VIRTIO_MENU is not set +# CONFIG_VHOST_MENU is not set +# CONFIG_IOMMU_SUPPORT is not set +CONFIG_DAX=m +CONFIG_EXT4_FS=y +CONFIG_REISERFS_FS=m +CONFIG_JFS_FS=m +CONFIG_OCFS2_FS=m +# CONFIG_OCFS2_DEBUG_MASKLOG is not set +CONFIG_FANOTIFY=y +CONFIG_QUOTA_NETLINK_INTERFACE=y +# CONFIG_PRINT_QUOTA_WARNING is not set +CONFIG_AUTOFS_FS=m +CONFIG_FUSE_FS=m +CONFIG_CUSE=m +CONFIG_OVERLAY_FS=m +CONFIG_ISO9660_FS=y +CONFIG_JOLIET=y +CONFIG_ZISOFS=y +CONFIG_UDF_FS=m +CONFIG_MSDOS_FS=m +CONFIG_VFAT_FS=m +CONFIG_EXFAT_FS=m +CONFIG_PROC_KCORE=y +CONFIG_PROC_CHILDREN=y +CONFIG_TMPFS=y +CONFIG_ORANGEFS_FS=m +CONFIG_AFFS_FS=m +CONFIG_ECRYPT_FS=m +CONFIG_ECRYPT_FS_MESSAGING=y +CONFIG_HFS_FS=m +CONFIG_HFSPLUS_FS=m +CONFIG_CRAMFS=m +CONFIG_SQUASHFS=m +CONFIG_SQUASHFS_LZ4=y +CONFIG_SQUASHFS_LZO=y +CONFIG_MINIX_FS=m +CONFIG_OMFS_FS=m +CONFIG_HPFS_FS=m +CONFIG_QNX4FS_FS=m +CONFIG_QNX6FS_FS=m +CONFIG_SYSV_FS=m +CONFIG_UFS_FS=m +CONFIG_EROFS_FS=m +CONFIG_NFS_FS=y +CONFIG_NFS_V4=m +CONFIG_NFS_SWAP=y +CONFIG_ROOT_NFS=y +CONFIG_NFSD=m +CONFIG_NFSD_V3=y +CONFIG_CIFS=m +# CONFIG_CIFS_DEBUG is not set +CONFIG_CODA_FS=m +CONFIG_NLS_CODEPAGE_437=y +CONFIG_NLS_CODEPAGE_737=m +CONFIG_NLS_CODEPAGE_775=m +CONFIG_NLS_CODEPAGE_850=m +CONFIG_NLS_CODEPAGE_852=m +CONFIG_NLS_CODEPAGE_855=m +CONFIG_NLS_CODEPAGE_857=m +CONFIG_NLS_CODEPAGE_860=m +CONFIG_NLS_CODEPAGE_861=m +CONFIG_NLS_CODEPAGE_862=m +CONFIG_NLS_CODEPAGE_863=m +CONFIG_NLS_CODEPAGE_864=m +CONFIG_NLS_CODEPAGE_865=m +CONFIG_NLS_CODEPAGE_866=m +CONFIG_NLS_CODEPAGE_869=m +CONFIG_NLS_CODEPAGE_936=m +CONFIG_NLS_CODEPAGE_950=m +CONFIG_NLS_CODEPAGE_932=m +CONFIG_NLS_CODEPAGE_949=m +CONFIG_NLS_CODEPAGE_874=m +CONFIG_NLS_ISO8859_8=m +CONFIG_NLS_CODEPAGE_1250=m +CONFIG_NLS_CODEPAGE_1251=m +CONFIG_NLS_ASCII=m +CONFIG_NLS_ISO8859_1=y +CONFIG_NLS_ISO8859_2=m +CONFIG_NLS_ISO8859_3=m +CONFIG_NLS_ISO8859_4=m +CONFIG_NLS_ISO8859_5=m +CONFIG_NLS_ISO8859_6=m +CONFIG_NLS_ISO8859_7=m +CONFIG_NLS_ISO8859_9=m +CONFIG_NLS_ISO8859_13=m +CONFIG_NLS_ISO8859_14=m +CONFIG_NLS_ISO8859_15=m +CONFIG_NLS_KOI8_R=m +CONFIG_NLS_KOI8_U=m +CONFIG_NLS_MAC_ROMAN=m +CONFIG_NLS_MAC_CELTIC=m +CONFIG_NLS_MAC_CENTEURO=m +CONFIG_NLS_MAC_CROATIAN=m +CONFIG_NLS_MAC_CYRILLIC=m +CONFIG_NLS_MAC_GAELIC=m +CONFIG_NLS_MAC_GREEK=m +CONFIG_NLS_MAC_ICELAND=m +CONFIG_NLS_MAC_INUIT=m +CONFIG_NLS_MAC_ROMANIAN=m +CONFIG_NLS_MAC_TURKISH=m +CONFIG_DLM=m +CONFIG_ENCRYPTED_KEYS=m +CONFIG_HARDENED_USERCOPY=y +CONFIG_CRYPTO_MANAGER=y +CONFIG_CRYPTO_USER=m +CONFIG_CRYPTO_CRYPTD=m +CONFIG_CRYPTO_TEST=m +CONFIG_CRYPTO_RSA=m +CONFIG_CRYPTO_DH=m +CONFIG_CRYPTO_ECDH=m +CONFIG_CRYPTO_ECRDSA=m +CONFIG_CRYPTO_CURVE25519=m +CONFIG_CRYPTO_CHACHA20POLY1305=m +CONFIG_CRYPTO_AEGIS128=m +CONFIG_CRYPTO_CFB=m +CONFIG_CRYPTO_CTS=m +CONFIG_CRYPTO_LRW=m +CONFIG_CRYPTO_OFB=m +CONFIG_CRYPTO_PCBC=m +CONFIG_CRYPTO_XTS=m +CONFIG_CRYPTO_KEYWRAP=m +CONFIG_CRYPTO_ADIANTUM=m +CONFIG_CRYPTO_XCBC=m +CONFIG_CRYPTO_VMAC=m +CONFIG_CRYPTO_BLAKE2S=m +CONFIG_CRYPTO_MICHAEL_MIC=m +CONFIG_CRYPTO_RMD128=m +CONFIG_CRYPTO_RMD160=m +CONFIG_CRYPTO_RMD256=m +CONFIG_CRYPTO_RMD320=m +CONFIG_CRYPTO_SHA3=m +CONFIG_CRYPTO_SM3=m +CONFIG_CRYPTO_TGR192=m +CONFIG_CRYPTO_WP512=m +CONFIG_CRYPTO_AES=y +CONFIG_CRYPTO_AES_TI=m +CONFIG_CRYPTO_ANUBIS=m +CONFIG_CRYPTO_ARC4=m +CONFIG_CRYPTO_BLOWFISH=m +CONFIG_CRYPTO_CAMELLIA=m +CONFIG_CRYPTO_CAST5=m +CONFIG_CRYPTO_CAST6=m +CONFIG_CRYPTO_DES=m +CONFIG_CRYPTO_FCRYPT=m +CONFIG_CRYPTO_KHAZAD=m +CONFIG_CRYPTO_SALSA20=m +CONFIG_CRYPTO_SEED=m +CONFIG_CRYPTO_SERPENT=m +CONFIG_CRYPTO_SM4=m +CONFIG_CRYPTO_TEA=m +CONFIG_CRYPTO_TWOFISH=m +CONFIG_CRYPTO_LZO=m +CONFIG_CRYPTO_842=m +CONFIG_CRYPTO_LZ4=m +CONFIG_CRYPTO_LZ4HC=m +CONFIG_CRYPTO_ZSTD=m +CONFIG_CRYPTO_ANSI_CPRNG=m +CONFIG_CRYPTO_DRBG_HASH=y +CONFIG_CRYPTO_DRBG_CTR=y +CONFIG_CRYPTO_USER_API_HASH=m +CONFIG_CRYPTO_USER_API_SKCIPHER=m +CONFIG_CRYPTO_USER_API_RNG=m +CONFIG_CRYPTO_USER_API_AEAD=m +# CONFIG_CRYPTO_HW is not set +CONFIG_PRIME_NUMBERS=m +CONFIG_CRC32_SELFTEST=m +CONFIG_CRC64=m +CONFIG_XZ_DEC_TEST=m +CONFIG_STRING_SELFTEST=m +# CONFIG_SECTION_MISMATCH_WARN_ONLY is not set +CONFIG_MAGIC_SYSRQ=y +CONFIG_TEST_LOCKUP=m +CONFIG_WW_MUTEX_SELFTEST=m +CONFIG_EARLY_PRINTK=y +CONFIG_TEST_LIST_SORT=m +CONFIG_TEST_MIN_HEAP=m +CONFIG_TEST_SORT=m +CONFIG_REED_SOLOMON_TEST=m +CONFIG_ATOMIC64_SELFTEST=m +CONFIG_ASYNC_RAID6_TEST=m +CONFIG_TEST_HEXDUMP=m +CONFIG_TEST_STRING_HELPERS=m +CONFIG_TEST_STRSCPY=m +CONFIG_TEST_KSTRTOX=m +CONFIG_TEST_PRINTF=m +CONFIG_TEST_BITMAP=m +CONFIG_TEST_BITFIELD=m +CONFIG_TEST_UUID=m +CONFIG_TEST_XARRAY=m +CONFIG_TEST_OVERFLOW=m +CONFIG_TEST_RHASHTABLE=m +CONFIG_TEST_HASH=m +CONFIG_TEST_IDA=m +CONFIG_TEST_BITOPS=m +CONFIG_TEST_VMALLOC=m +CONFIG_TEST_USER_COPY=m +CONFIG_TEST_BPF=m +CONFIG_TEST_BLACKHOLE_DEV=m +CONFIG_FIND_BIT_BENCHMARK=m +CONFIG_TEST_FIRMWARE=m +CONFIG_TEST_SYSCTL=m +CONFIG_TEST_UDELAY=m +CONFIG_TEST_STATIC_KEYS=m +CONFIG_TEST_KMOD=m +CONFIG_TEST_MEMCAT_P=m +CONFIG_TEST_STACKINIT=m +CONFIG_TEST_MEMINIT=m diff --git a/arch/m68k/configs/apollo_defconfig b/arch/m68k/configs/apollo_defconfig new file mode 100644 index 000000000..f4828e86d --- /dev/null +++ b/arch/m68k/configs/apollo_defconfig @@ -0,0 +1,617 @@ +CONFIG_LOCALVERSION="-apollo" +CONFIG_SYSVIPC=y +CONFIG_POSIX_MQUEUE=y +CONFIG_BSD_PROCESS_ACCT=y +CONFIG_BSD_PROCESS_ACCT_V3=y +CONFIG_LOG_BUF_SHIFT=16 +# CONFIG_UTS_NS is not set +# CONFIG_IPC_NS is not set +# CONFIG_PID_NS is not set +# CONFIG_NET_NS is not set +CONFIG_BLK_DEV_INITRD=y +CONFIG_CC_OPTIMIZE_FOR_SIZE=y +CONFIG_USERFAULTFD=y +CONFIG_SLAB=y +CONFIG_KEXEC=y +CONFIG_BOOTINFO_PROC=y +CONFIG_M68020=y +CONFIG_M68030=y +CONFIG_M68040=y +CONFIG_M68060=y +CONFIG_APOLLO=y +CONFIG_HEARTBEAT=y +CONFIG_PROC_HARDWARE=y +CONFIG_MODULES=y +CONFIG_MODULE_UNLOAD=y +CONFIG_PARTITION_ADVANCED=y +CONFIG_AMIGA_PARTITION=y +CONFIG_ATARI_PARTITION=y +CONFIG_MAC_PARTITION=y +CONFIG_BSD_DISKLABEL=y +CONFIG_MINIX_SUBPARTITION=y +CONFIG_SOLARIS_X86_PARTITION=y +CONFIG_UNIXWARE_DISKLABEL=y +CONFIG_SUN_PARTITION=y +# CONFIG_EFI_PARTITION is not set +CONFIG_SYSV68_PARTITION=y +CONFIG_MQ_IOSCHED_DEADLINE=m +CONFIG_MQ_IOSCHED_KYBER=m +CONFIG_IOSCHED_BFQ=m +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +CONFIG_BINFMT_AOUT=m +CONFIG_BINFMT_MISC=m +# CONFIG_COMPACTION is not set +CONFIG_CLEANCACHE=y +CONFIG_ZPOOL=m +CONFIG_NET=y +CONFIG_PACKET=y +CONFIG_PACKET_DIAG=m +CONFIG_UNIX=y +CONFIG_UNIX_DIAG=m +CONFIG_TLS=m +CONFIG_XFRM_MIGRATE=y +CONFIG_NET_KEY=y +CONFIG_XDP_SOCKETS=y +CONFIG_XDP_SOCKETS_DIAG=m +CONFIG_INET=y +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +CONFIG_IP_PNP_BOOTP=y +CONFIG_IP_PNP_RARP=y +CONFIG_NET_IPIP=m +CONFIG_NET_IPGRE_DEMUX=m +CONFIG_NET_IPGRE=m +CONFIG_NET_IPVTI=m +CONFIG_NET_FOU_IP_TUNNELS=y +CONFIG_INET_AH=m +CONFIG_INET_ESP=m +CONFIG_INET_ESP_OFFLOAD=m +CONFIG_INET_IPCOMP=m +CONFIG_INET_DIAG=m +CONFIG_INET_UDP_DIAG=m +CONFIG_INET_RAW_DIAG=m +CONFIG_IPV6=m +CONFIG_IPV6_ROUTER_PREF=y +CONFIG_INET6_AH=m +CONFIG_INET6_ESP=m +CONFIG_INET6_ESP_OFFLOAD=m +CONFIG_INET6_IPCOMP=m +CONFIG_IPV6_ILA=m +CONFIG_IPV6_VTI=m +CONFIG_IPV6_GRE=m +CONFIG_NETFILTER=y +CONFIG_NF_CONNTRACK=m +CONFIG_NF_LOG_NETDEV=m +CONFIG_NF_CONNTRACK_ZONES=y +# CONFIG_NF_CONNTRACK_PROCFS is not set +# CONFIG_NF_CT_PROTO_DCCP is not set +CONFIG_NF_CONNTRACK_AMANDA=m +CONFIG_NF_CONNTRACK_FTP=m +CONFIG_NF_CONNTRACK_H323=m +CONFIG_NF_CONNTRACK_IRC=m +CONFIG_NF_CONNTRACK_NETBIOS_NS=m +CONFIG_NF_CONNTRACK_SNMP=m +CONFIG_NF_CONNTRACK_PPTP=m +CONFIG_NF_CONNTRACK_SANE=m +CONFIG_NF_CONNTRACK_SIP=m +CONFIG_NF_CONNTRACK_TFTP=m +CONFIG_NF_TABLES=m +CONFIG_NF_TABLES_INET=y +CONFIG_NF_TABLES_NETDEV=y +CONFIG_NFT_NUMGEN=m +CONFIG_NFT_CT=m +CONFIG_NFT_FLOW_OFFLOAD=m +CONFIG_NFT_COUNTER=m +CONFIG_NFT_CONNLIMIT=m +CONFIG_NFT_LOG=m +CONFIG_NFT_LIMIT=m +CONFIG_NFT_MASQ=m +CONFIG_NFT_REDIR=m +CONFIG_NFT_NAT=m +CONFIG_NFT_TUNNEL=m +CONFIG_NFT_OBJREF=m +CONFIG_NFT_QUEUE=m +CONFIG_NFT_QUOTA=m +CONFIG_NFT_REJECT=m +CONFIG_NFT_COMPAT=m +CONFIG_NFT_HASH=m +CONFIG_NFT_FIB_INET=m +CONFIG_NFT_XFRM=m +CONFIG_NFT_SOCKET=m +CONFIG_NFT_OSF=m +CONFIG_NFT_TPROXY=m +CONFIG_NFT_SYNPROXY=m +CONFIG_NFT_DUP_NETDEV=m +CONFIG_NFT_FWD_NETDEV=m +CONFIG_NFT_FIB_NETDEV=m +CONFIG_NF_FLOW_TABLE_INET=m +CONFIG_NF_FLOW_TABLE=m +CONFIG_NETFILTER_XT_SET=m +CONFIG_NETFILTER_XT_TARGET_CHECKSUM=m +CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m +CONFIG_NETFILTER_XT_TARGET_CONNMARK=m +CONFIG_NETFILTER_XT_TARGET_DSCP=m +CONFIG_NETFILTER_XT_TARGET_HMARK=m +CONFIG_NETFILTER_XT_TARGET_IDLETIMER=m +CONFIG_NETFILTER_XT_TARGET_LOG=m +CONFIG_NETFILTER_XT_TARGET_MARK=m +CONFIG_NETFILTER_XT_TARGET_NFLOG=m +CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m +CONFIG_NETFILTER_XT_TARGET_NOTRACK=m +CONFIG_NETFILTER_XT_TARGET_TEE=m +CONFIG_NETFILTER_XT_TARGET_TPROXY=m +CONFIG_NETFILTER_XT_TARGET_TRACE=m +CONFIG_NETFILTER_XT_TARGET_TCPMSS=m +CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP=m +CONFIG_NETFILTER_XT_MATCH_ADDRTYPE=m +CONFIG_NETFILTER_XT_MATCH_BPF=m +CONFIG_NETFILTER_XT_MATCH_CLUSTER=m +CONFIG_NETFILTER_XT_MATCH_COMMENT=m +CONFIG_NETFILTER_XT_MATCH_CONNBYTES=m +CONFIG_NETFILTER_XT_MATCH_CONNLABEL=m +CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=m +CONFIG_NETFILTER_XT_MATCH_CONNMARK=m +CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m +CONFIG_NETFILTER_XT_MATCH_DEVGROUP=m +CONFIG_NETFILTER_XT_MATCH_DSCP=m +CONFIG_NETFILTER_XT_MATCH_ESP=m +CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=m +CONFIG_NETFILTER_XT_MATCH_HELPER=m +CONFIG_NETFILTER_XT_MATCH_IPCOMP=m +CONFIG_NETFILTER_XT_MATCH_IPRANGE=m +CONFIG_NETFILTER_XT_MATCH_LENGTH=m +CONFIG_NETFILTER_XT_MATCH_LIMIT=m +CONFIG_NETFILTER_XT_MATCH_MAC=m +CONFIG_NETFILTER_XT_MATCH_MARK=m +CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m +CONFIG_NETFILTER_XT_MATCH_NFACCT=m +CONFIG_NETFILTER_XT_MATCH_OSF=m +CONFIG_NETFILTER_XT_MATCH_OWNER=m +CONFIG_NETFILTER_XT_MATCH_POLICY=m +CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m +CONFIG_NETFILTER_XT_MATCH_QUOTA=m +CONFIG_NETFILTER_XT_MATCH_RATEEST=m +CONFIG_NETFILTER_XT_MATCH_REALM=m +CONFIG_NETFILTER_XT_MATCH_RECENT=m +CONFIG_NETFILTER_XT_MATCH_SOCKET=m +CONFIG_NETFILTER_XT_MATCH_STATE=m +CONFIG_NETFILTER_XT_MATCH_STATISTIC=m +CONFIG_NETFILTER_XT_MATCH_STRING=m +CONFIG_NETFILTER_XT_MATCH_TCPMSS=m +CONFIG_NETFILTER_XT_MATCH_TIME=m +CONFIG_NETFILTER_XT_MATCH_U32=m +CONFIG_IP_SET=m +CONFIG_IP_SET_BITMAP_IP=m +CONFIG_IP_SET_BITMAP_IPMAC=m +CONFIG_IP_SET_BITMAP_PORT=m +CONFIG_IP_SET_HASH_IP=m +CONFIG_IP_SET_HASH_IPMARK=m +CONFIG_IP_SET_HASH_IPPORT=m +CONFIG_IP_SET_HASH_IPPORTIP=m +CONFIG_IP_SET_HASH_IPPORTNET=m +CONFIG_IP_SET_HASH_IPMAC=m +CONFIG_IP_SET_HASH_MAC=m +CONFIG_IP_SET_HASH_NETPORTNET=m +CONFIG_IP_SET_HASH_NET=m +CONFIG_IP_SET_HASH_NETNET=m +CONFIG_IP_SET_HASH_NETPORT=m +CONFIG_IP_SET_HASH_NETIFACE=m +CONFIG_IP_SET_LIST_SET=m +CONFIG_NFT_DUP_IPV4=m +CONFIG_NFT_FIB_IPV4=m +CONFIG_NF_TABLES_ARP=y +CONFIG_NF_FLOW_TABLE_IPV4=m +CONFIG_NF_LOG_ARP=m +CONFIG_IP_NF_IPTABLES=m +CONFIG_IP_NF_MATCH_AH=m +CONFIG_IP_NF_MATCH_ECN=m +CONFIG_IP_NF_MATCH_RPFILTER=m +CONFIG_IP_NF_MATCH_TTL=m +CONFIG_IP_NF_FILTER=m +CONFIG_IP_NF_TARGET_REJECT=m +CONFIG_IP_NF_TARGET_SYNPROXY=m +CONFIG_IP_NF_NAT=m +CONFIG_IP_NF_TARGET_MASQUERADE=m +CONFIG_IP_NF_TARGET_NETMAP=m +CONFIG_IP_NF_TARGET_REDIRECT=m +CONFIG_IP_NF_MANGLE=m +CONFIG_IP_NF_TARGET_CLUSTERIP=m +CONFIG_IP_NF_TARGET_ECN=m +CONFIG_IP_NF_TARGET_TTL=m +CONFIG_IP_NF_RAW=m +CONFIG_IP_NF_ARPTABLES=m +CONFIG_IP_NF_ARPFILTER=m +CONFIG_IP_NF_ARP_MANGLE=m +CONFIG_NFT_DUP_IPV6=m +CONFIG_NFT_FIB_IPV6=m +CONFIG_NF_FLOW_TABLE_IPV6=m +CONFIG_IP6_NF_IPTABLES=m +CONFIG_IP6_NF_MATCH_AH=m +CONFIG_IP6_NF_MATCH_EUI64=m +CONFIG_IP6_NF_MATCH_FRAG=m +CONFIG_IP6_NF_MATCH_OPTS=m +CONFIG_IP6_NF_MATCH_HL=m +CONFIG_IP6_NF_MATCH_IPV6HEADER=m +CONFIG_IP6_NF_MATCH_MH=m +CONFIG_IP6_NF_MATCH_RPFILTER=m +CONFIG_IP6_NF_MATCH_RT=m +CONFIG_IP6_NF_MATCH_SRH=m +CONFIG_IP6_NF_TARGET_HL=m +CONFIG_IP6_NF_FILTER=m +CONFIG_IP6_NF_TARGET_REJECT=m +CONFIG_IP6_NF_TARGET_SYNPROXY=m +CONFIG_IP6_NF_MANGLE=m +CONFIG_IP6_NF_RAW=m +CONFIG_IP6_NF_NAT=m +CONFIG_IP6_NF_TARGET_MASQUERADE=m +CONFIG_IP6_NF_TARGET_NPT=m +CONFIG_NF_TABLES_BRIDGE=m +CONFIG_NFT_BRIDGE_META=m +CONFIG_NFT_BRIDGE_REJECT=m +CONFIG_NF_LOG_BRIDGE=m +CONFIG_NF_CONNTRACK_BRIDGE=m +CONFIG_BRIDGE_NF_EBTABLES=m +CONFIG_BRIDGE_EBT_BROUTE=m +CONFIG_BRIDGE_EBT_T_FILTER=m +CONFIG_BRIDGE_EBT_T_NAT=m +CONFIG_BRIDGE_EBT_802_3=m +CONFIG_BRIDGE_EBT_AMONG=m +CONFIG_BRIDGE_EBT_ARP=m +CONFIG_BRIDGE_EBT_IP=m +CONFIG_BRIDGE_EBT_IP6=m +CONFIG_BRIDGE_EBT_LIMIT=m +CONFIG_BRIDGE_EBT_MARK=m +CONFIG_BRIDGE_EBT_PKTTYPE=m +CONFIG_BRIDGE_EBT_STP=m +CONFIG_BRIDGE_EBT_VLAN=m +CONFIG_BRIDGE_EBT_ARPREPLY=m +CONFIG_BRIDGE_EBT_DNAT=m +CONFIG_BRIDGE_EBT_MARK_T=m +CONFIG_BRIDGE_EBT_REDIRECT=m +CONFIG_BRIDGE_EBT_SNAT=m +CONFIG_BRIDGE_EBT_LOG=m +CONFIG_BRIDGE_EBT_NFLOG=m +CONFIG_IP_DCCP=m +# CONFIG_IP_DCCP_CCID3 is not set +CONFIG_SCTP_COOKIE_HMAC_SHA1=y +CONFIG_RDS=m +CONFIG_RDS_TCP=m +CONFIG_L2TP=m +CONFIG_BRIDGE=m +CONFIG_ATALK=m +CONFIG_6LOWPAN=m +CONFIG_6LOWPAN_GHC_EXT_HDR_HOP=m +CONFIG_6LOWPAN_GHC_UDP=m +CONFIG_6LOWPAN_GHC_ICMPV6=m +CONFIG_6LOWPAN_GHC_EXT_HDR_DEST=m +CONFIG_6LOWPAN_GHC_EXT_HDR_FRAG=m +CONFIG_6LOWPAN_GHC_EXT_HDR_ROUTE=m +CONFIG_DNS_RESOLVER=y +CONFIG_BATMAN_ADV=m +# CONFIG_BATMAN_ADV_BATMAN_V is not set +CONFIG_BATMAN_ADV_NC=y +CONFIG_NETLINK_DIAG=m +CONFIG_MPLS=y +CONFIG_NET_MPLS_GSO=m +CONFIG_MPLS_ROUTING=m +CONFIG_MPLS_IPTUNNEL=m +CONFIG_NET_NSH=m +CONFIG_AF_KCM=m +# CONFIG_WIRELESS is not set +CONFIG_PSAMPLE=m +CONFIG_NET_IFE=m +CONFIG_DEVTMPFS=y +CONFIG_DEVTMPFS_MOUNT=y +CONFIG_TEST_ASYNC_DRIVER_PROBE=m +CONFIG_CONNECTOR=m +CONFIG_BLK_DEV_LOOP=y +CONFIG_BLK_DEV_CRYPTOLOOP=m +CONFIG_BLK_DEV_DRBD=m +CONFIG_BLK_DEV_NBD=m +CONFIG_BLK_DEV_RAM=y +CONFIG_CDROM_PKTCDVD=m +CONFIG_ATA_OVER_ETH=m +CONFIG_DUMMY_IRQ=m +CONFIG_RAID_ATTRS=m +CONFIG_SCSI=y +CONFIG_BLK_DEV_SD=y +CONFIG_CHR_DEV_ST=m +CONFIG_BLK_DEV_SR=y +CONFIG_CHR_DEV_SG=m +CONFIG_SCSI_CONSTANTS=y +CONFIG_SCSI_SAS_ATTRS=m +CONFIG_ISCSI_TCP=m +CONFIG_ISCSI_BOOT_SYSFS=m +CONFIG_MD=y +CONFIG_MD_LINEAR=m +CONFIG_BLK_DEV_DM=m +CONFIG_DM_UNSTRIPED=m +CONFIG_DM_CRYPT=m +CONFIG_DM_SNAPSHOT=m +CONFIG_DM_THIN_PROVISIONING=m +CONFIG_DM_WRITECACHE=m +CONFIG_DM_ERA=m +CONFIG_DM_CLONE=m +CONFIG_DM_MIRROR=m +CONFIG_DM_RAID=m +CONFIG_DM_ZERO=m +CONFIG_DM_MULTIPATH=m +CONFIG_DM_UEVENT=y +CONFIG_DM_LOG_WRITES=m +CONFIG_DM_INTEGRITY=m +CONFIG_TARGET_CORE=m +CONFIG_TCM_IBLOCK=m +CONFIG_TCM_FILEIO=m +CONFIG_TCM_PSCSI=m +CONFIG_NETDEVICES=y +CONFIG_DUMMY=m +CONFIG_WIREGUARD=m +CONFIG_EQUALIZER=m +CONFIG_NET_TEAM=m +CONFIG_NET_TEAM_MODE_BROADCAST=m +CONFIG_NET_TEAM_MODE_ROUNDROBIN=m +CONFIG_NET_TEAM_MODE_RANDOM=m +CONFIG_NET_TEAM_MODE_ACTIVEBACKUP=m +CONFIG_NET_TEAM_MODE_LOADBALANCE=m +CONFIG_MACVLAN=m +CONFIG_MACVTAP=m +CONFIG_IPVLAN=m +CONFIG_IPVTAP=m +CONFIG_VXLAN=m +CONFIG_GENEVE=m +CONFIG_BAREUDP=m +CONFIG_GTP=m +CONFIG_MACSEC=m +CONFIG_NETCONSOLE=m +CONFIG_NETCONSOLE_DYNAMIC=y +CONFIG_VETH=m +CONFIG_PPP=m +CONFIG_PPP_BSDCOMP=m +CONFIG_PPP_DEFLATE=m +CONFIG_PPP_FILTER=y +CONFIG_PPP_MPPE=m +CONFIG_PPPOE=m +CONFIG_PPTP=m +CONFIG_PPPOL2TP=m +CONFIG_PPP_ASYNC=m +CONFIG_PPP_SYNC_TTY=m +CONFIG_SLIP=m +CONFIG_SLIP_COMPRESSED=y +CONFIG_SLIP_SMART=y +CONFIG_SLIP_MODE_SLIP6=y +# CONFIG_WLAN is not set +CONFIG_INPUT_EVDEV=m +# CONFIG_KEYBOARD_ATKBD is not set +# CONFIG_MOUSE_PS2 is not set +CONFIG_MOUSE_SERIAL=m +CONFIG_SERIO=m +CONFIG_USERIO=m +# CONFIG_LEGACY_PTYS is not set +# CONFIG_HW_RANDOM is not set +CONFIG_NTP_PPS=y +CONFIG_PPS_CLIENT_LDISC=m +CONFIG_PTP_1588_CLOCK=m +# CONFIG_HWMON is not set +CONFIG_FB=y +CONFIG_FRAMEBUFFER_CONSOLE=y +CONFIG_LOGO=y +# CONFIG_LOGO_LINUX_VGA16 is not set +# CONFIG_LOGO_LINUX_CLUT224 is not set +CONFIG_HID=m +CONFIG_HIDRAW=y +CONFIG_UHID=m +# CONFIG_HID_GENERIC is not set +# CONFIG_HID_ITE is not set +# CONFIG_HID_REDRAGON is not set +# CONFIG_USB_SUPPORT is not set +CONFIG_RTC_CLASS=y +# CONFIG_RTC_NVMEM is not set +CONFIG_RTC_DRV_GENERIC=m +# CONFIG_VIRTIO_MENU is not set +# CONFIG_VHOST_MENU is not set +# CONFIG_IOMMU_SUPPORT is not set +CONFIG_DAX=m +CONFIG_EXT4_FS=y +CONFIG_REISERFS_FS=m +CONFIG_JFS_FS=m +CONFIG_OCFS2_FS=m +# CONFIG_OCFS2_DEBUG_MASKLOG is not set +CONFIG_FANOTIFY=y +CONFIG_QUOTA_NETLINK_INTERFACE=y +# CONFIG_PRINT_QUOTA_WARNING is not set +CONFIG_AUTOFS_FS=m +CONFIG_FUSE_FS=m +CONFIG_CUSE=m +CONFIG_OVERLAY_FS=m +CONFIG_ISO9660_FS=y +CONFIG_JOLIET=y +CONFIG_ZISOFS=y +CONFIG_UDF_FS=m +CONFIG_MSDOS_FS=m +CONFIG_VFAT_FS=m +CONFIG_EXFAT_FS=m +CONFIG_PROC_KCORE=y +CONFIG_PROC_CHILDREN=y +CONFIG_TMPFS=y +CONFIG_ORANGEFS_FS=m +CONFIG_AFFS_FS=m +CONFIG_ECRYPT_FS=m +CONFIG_ECRYPT_FS_MESSAGING=y +CONFIG_HFS_FS=m +CONFIG_HFSPLUS_FS=m +CONFIG_CRAMFS=m +CONFIG_SQUASHFS=m +CONFIG_SQUASHFS_LZ4=y +CONFIG_SQUASHFS_LZO=y +CONFIG_MINIX_FS=m +CONFIG_OMFS_FS=m +CONFIG_HPFS_FS=m +CONFIG_QNX4FS_FS=m +CONFIG_QNX6FS_FS=m +CONFIG_SYSV_FS=m +CONFIG_UFS_FS=m +CONFIG_EROFS_FS=m +CONFIG_NFS_FS=y +CONFIG_NFS_V4=m +CONFIG_NFS_SWAP=y +CONFIG_ROOT_NFS=y +CONFIG_NFSD=m +CONFIG_NFSD_V3=y +CONFIG_CIFS=m +# CONFIG_CIFS_DEBUG is not set +CONFIG_CODA_FS=m +CONFIG_NLS_CODEPAGE_437=y +CONFIG_NLS_CODEPAGE_737=m +CONFIG_NLS_CODEPAGE_775=m +CONFIG_NLS_CODEPAGE_850=m +CONFIG_NLS_CODEPAGE_852=m +CONFIG_NLS_CODEPAGE_855=m +CONFIG_NLS_CODEPAGE_857=m +CONFIG_NLS_CODEPAGE_860=m +CONFIG_NLS_CODEPAGE_861=m +CONFIG_NLS_CODEPAGE_862=m +CONFIG_NLS_CODEPAGE_863=m +CONFIG_NLS_CODEPAGE_864=m +CONFIG_NLS_CODEPAGE_865=m +CONFIG_NLS_CODEPAGE_866=m +CONFIG_NLS_CODEPAGE_869=m +CONFIG_NLS_CODEPAGE_936=m +CONFIG_NLS_CODEPAGE_950=m +CONFIG_NLS_CODEPAGE_932=m +CONFIG_NLS_CODEPAGE_949=m +CONFIG_NLS_CODEPAGE_874=m +CONFIG_NLS_ISO8859_8=m +CONFIG_NLS_CODEPAGE_1250=m +CONFIG_NLS_CODEPAGE_1251=m +CONFIG_NLS_ASCII=m +CONFIG_NLS_ISO8859_1=y +CONFIG_NLS_ISO8859_2=m +CONFIG_NLS_ISO8859_3=m +CONFIG_NLS_ISO8859_4=m +CONFIG_NLS_ISO8859_5=m +CONFIG_NLS_ISO8859_6=m +CONFIG_NLS_ISO8859_7=m +CONFIG_NLS_ISO8859_9=m +CONFIG_NLS_ISO8859_13=m +CONFIG_NLS_ISO8859_14=m +CONFIG_NLS_ISO8859_15=m +CONFIG_NLS_KOI8_R=m +CONFIG_NLS_KOI8_U=m +CONFIG_NLS_MAC_ROMAN=m +CONFIG_NLS_MAC_CELTIC=m +CONFIG_NLS_MAC_CENTEURO=m +CONFIG_NLS_MAC_CROATIAN=m +CONFIG_NLS_MAC_CYRILLIC=m +CONFIG_NLS_MAC_GAELIC=m +CONFIG_NLS_MAC_GREEK=m +CONFIG_NLS_MAC_ICELAND=m +CONFIG_NLS_MAC_INUIT=m +CONFIG_NLS_MAC_ROMANIAN=m +CONFIG_NLS_MAC_TURKISH=m +CONFIG_DLM=m +CONFIG_ENCRYPTED_KEYS=m +CONFIG_HARDENED_USERCOPY=y +CONFIG_CRYPTO_MANAGER=y +CONFIG_CRYPTO_USER=m +CONFIG_CRYPTO_CRYPTD=m +CONFIG_CRYPTO_TEST=m +CONFIG_CRYPTO_RSA=m +CONFIG_CRYPTO_DH=m +CONFIG_CRYPTO_ECDH=m +CONFIG_CRYPTO_ECRDSA=m +CONFIG_CRYPTO_CURVE25519=m +CONFIG_CRYPTO_CHACHA20POLY1305=m +CONFIG_CRYPTO_AEGIS128=m +CONFIG_CRYPTO_CFB=m +CONFIG_CRYPTO_CTS=m +CONFIG_CRYPTO_LRW=m +CONFIG_CRYPTO_OFB=m +CONFIG_CRYPTO_PCBC=m +CONFIG_CRYPTO_XTS=m +CONFIG_CRYPTO_KEYWRAP=m +CONFIG_CRYPTO_ADIANTUM=m +CONFIG_CRYPTO_XCBC=m +CONFIG_CRYPTO_VMAC=m +CONFIG_CRYPTO_BLAKE2S=m +CONFIG_CRYPTO_MICHAEL_MIC=m +CONFIG_CRYPTO_RMD128=m +CONFIG_CRYPTO_RMD160=m +CONFIG_CRYPTO_RMD256=m +CONFIG_CRYPTO_RMD320=m +CONFIG_CRYPTO_SHA3=m +CONFIG_CRYPTO_SM3=m +CONFIG_CRYPTO_TGR192=m +CONFIG_CRYPTO_WP512=m +CONFIG_CRYPTO_AES=y +CONFIG_CRYPTO_AES_TI=m +CONFIG_CRYPTO_ANUBIS=m +CONFIG_CRYPTO_ARC4=m +CONFIG_CRYPTO_BLOWFISH=m +CONFIG_CRYPTO_CAMELLIA=m +CONFIG_CRYPTO_CAST5=m +CONFIG_CRYPTO_CAST6=m +CONFIG_CRYPTO_DES=m +CONFIG_CRYPTO_FCRYPT=m +CONFIG_CRYPTO_KHAZAD=m +CONFIG_CRYPTO_SALSA20=m +CONFIG_CRYPTO_SEED=m +CONFIG_CRYPTO_SERPENT=m +CONFIG_CRYPTO_SM4=m +CONFIG_CRYPTO_TEA=m +CONFIG_CRYPTO_TWOFISH=m +CONFIG_CRYPTO_LZO=m +CONFIG_CRYPTO_842=m +CONFIG_CRYPTO_LZ4=m +CONFIG_CRYPTO_LZ4HC=m +CONFIG_CRYPTO_ZSTD=m +CONFIG_CRYPTO_ANSI_CPRNG=m +CONFIG_CRYPTO_DRBG_HASH=y +CONFIG_CRYPTO_DRBG_CTR=y +CONFIG_CRYPTO_USER_API_HASH=m +CONFIG_CRYPTO_USER_API_SKCIPHER=m +CONFIG_CRYPTO_USER_API_RNG=m +CONFIG_CRYPTO_USER_API_AEAD=m +# CONFIG_CRYPTO_HW is not set +CONFIG_PRIME_NUMBERS=m +CONFIG_CRC32_SELFTEST=m +CONFIG_CRC64=m +CONFIG_XZ_DEC_TEST=m +CONFIG_STRING_SELFTEST=m +# CONFIG_SECTION_MISMATCH_WARN_ONLY is not set +CONFIG_MAGIC_SYSRQ=y +CONFIG_TEST_LOCKUP=m +CONFIG_WW_MUTEX_SELFTEST=m +CONFIG_EARLY_PRINTK=y +CONFIG_TEST_LIST_SORT=m +CONFIG_TEST_MIN_HEAP=m +CONFIG_TEST_SORT=m +CONFIG_REED_SOLOMON_TEST=m +CONFIG_ATOMIC64_SELFTEST=m +CONFIG_ASYNC_RAID6_TEST=m +CONFIG_TEST_HEXDUMP=m +CONFIG_TEST_STRING_HELPERS=m +CONFIG_TEST_STRSCPY=m +CONFIG_TEST_KSTRTOX=m +CONFIG_TEST_PRINTF=m +CONFIG_TEST_BITMAP=m +CONFIG_TEST_BITFIELD=m +CONFIG_TEST_UUID=m +CONFIG_TEST_XARRAY=m +CONFIG_TEST_OVERFLOW=m +CONFIG_TEST_RHASHTABLE=m +CONFIG_TEST_HASH=m +CONFIG_TEST_IDA=m +CONFIG_TEST_BITOPS=m +CONFIG_TEST_VMALLOC=m +CONFIG_TEST_USER_COPY=m +CONFIG_TEST_BPF=m +CONFIG_TEST_BLACKHOLE_DEV=m +CONFIG_FIND_BIT_BENCHMARK=m +CONFIG_TEST_FIRMWARE=m +CONFIG_TEST_SYSCTL=m +CONFIG_TEST_UDELAY=m +CONFIG_TEST_STATIC_KEYS=m +CONFIG_TEST_KMOD=m +CONFIG_TEST_MEMCAT_P=m +CONFIG_TEST_STACKINIT=m +CONFIG_TEST_MEMINIT=m diff --git a/arch/m68k/configs/atari_defconfig b/arch/m68k/configs/atari_defconfig new file mode 100644 index 000000000..e7911f141 --- /dev/null +++ b/arch/m68k/configs/atari_defconfig @@ -0,0 +1,639 @@ +CONFIG_LOCALVERSION="-atari" +CONFIG_SYSVIPC=y +CONFIG_POSIX_MQUEUE=y +CONFIG_BSD_PROCESS_ACCT=y +CONFIG_BSD_PROCESS_ACCT_V3=y +CONFIG_LOG_BUF_SHIFT=16 +# CONFIG_UTS_NS is not set +# CONFIG_IPC_NS is not set +# CONFIG_PID_NS is not set +# CONFIG_NET_NS is not set +CONFIG_BLK_DEV_INITRD=y +CONFIG_CC_OPTIMIZE_FOR_SIZE=y +CONFIG_USERFAULTFD=y +CONFIG_SLAB=y +CONFIG_KEXEC=y +CONFIG_BOOTINFO_PROC=y +CONFIG_M68020=y +CONFIG_M68030=y +CONFIG_M68040=y +CONFIG_M68060=y +CONFIG_ATARI=y +CONFIG_ATARI_ROM_ISA=y +CONFIG_HEARTBEAT=y +CONFIG_PROC_HARDWARE=y +CONFIG_NATFEAT=y +CONFIG_NFBLOCK=y +CONFIG_NFCON=y +CONFIG_NFETH=y +CONFIG_ATARI_ETHERNAT=y +CONFIG_ATARI_ETHERNEC=y +CONFIG_ATARI_DSP56K=m +CONFIG_MODULES=y +CONFIG_MODULE_UNLOAD=y +CONFIG_PARTITION_ADVANCED=y +CONFIG_AMIGA_PARTITION=y +CONFIG_MAC_PARTITION=y +CONFIG_BSD_DISKLABEL=y +CONFIG_MINIX_SUBPARTITION=y +CONFIG_SOLARIS_X86_PARTITION=y +CONFIG_UNIXWARE_DISKLABEL=y +CONFIG_SUN_PARTITION=y +# CONFIG_EFI_PARTITION is not set +CONFIG_SYSV68_PARTITION=y +CONFIG_MQ_IOSCHED_DEADLINE=m +CONFIG_MQ_IOSCHED_KYBER=m +CONFIG_IOSCHED_BFQ=m +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +CONFIG_BINFMT_AOUT=m +CONFIG_BINFMT_MISC=m +# CONFIG_COMPACTION is not set +CONFIG_CLEANCACHE=y +CONFIG_ZPOOL=m +CONFIG_NET=y +CONFIG_PACKET=y +CONFIG_PACKET_DIAG=m +CONFIG_UNIX=y +CONFIG_UNIX_DIAG=m +CONFIG_TLS=m +CONFIG_XFRM_MIGRATE=y +CONFIG_NET_KEY=y +CONFIG_XDP_SOCKETS=y +CONFIG_XDP_SOCKETS_DIAG=m +CONFIG_INET=y +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +CONFIG_IP_PNP_BOOTP=y +CONFIG_IP_PNP_RARP=y +CONFIG_NET_IPIP=m +CONFIG_NET_IPGRE_DEMUX=m +CONFIG_NET_IPGRE=m +CONFIG_NET_IPVTI=m +CONFIG_NET_FOU_IP_TUNNELS=y +CONFIG_INET_AH=m +CONFIG_INET_ESP=m +CONFIG_INET_ESP_OFFLOAD=m +CONFIG_INET_IPCOMP=m +CONFIG_INET_DIAG=m +CONFIG_INET_UDP_DIAG=m +CONFIG_INET_RAW_DIAG=m +CONFIG_IPV6=m +CONFIG_IPV6_ROUTER_PREF=y +CONFIG_INET6_AH=m +CONFIG_INET6_ESP=m +CONFIG_INET6_ESP_OFFLOAD=m +CONFIG_INET6_IPCOMP=m +CONFIG_IPV6_ILA=m +CONFIG_IPV6_VTI=m +CONFIG_IPV6_GRE=m +CONFIG_NETFILTER=y +CONFIG_NF_CONNTRACK=m +CONFIG_NF_LOG_NETDEV=m +CONFIG_NF_CONNTRACK_ZONES=y +# CONFIG_NF_CONNTRACK_PROCFS is not set +# CONFIG_NF_CT_PROTO_DCCP is not set +CONFIG_NF_CONNTRACK_AMANDA=m +CONFIG_NF_CONNTRACK_FTP=m +CONFIG_NF_CONNTRACK_H323=m +CONFIG_NF_CONNTRACK_IRC=m +CONFIG_NF_CONNTRACK_NETBIOS_NS=m +CONFIG_NF_CONNTRACK_SNMP=m +CONFIG_NF_CONNTRACK_PPTP=m +CONFIG_NF_CONNTRACK_SANE=m +CONFIG_NF_CONNTRACK_SIP=m +CONFIG_NF_CONNTRACK_TFTP=m +CONFIG_NF_TABLES=m +CONFIG_NF_TABLES_INET=y +CONFIG_NF_TABLES_NETDEV=y +CONFIG_NFT_NUMGEN=m +CONFIG_NFT_CT=m +CONFIG_NFT_FLOW_OFFLOAD=m +CONFIG_NFT_COUNTER=m +CONFIG_NFT_CONNLIMIT=m +CONFIG_NFT_LOG=m +CONFIG_NFT_LIMIT=m +CONFIG_NFT_MASQ=m +CONFIG_NFT_REDIR=m +CONFIG_NFT_NAT=m +CONFIG_NFT_TUNNEL=m +CONFIG_NFT_OBJREF=m +CONFIG_NFT_QUEUE=m +CONFIG_NFT_QUOTA=m +CONFIG_NFT_REJECT=m +CONFIG_NFT_COMPAT=m +CONFIG_NFT_HASH=m +CONFIG_NFT_FIB_INET=m +CONFIG_NFT_XFRM=m +CONFIG_NFT_SOCKET=m +CONFIG_NFT_OSF=m +CONFIG_NFT_TPROXY=m +CONFIG_NFT_SYNPROXY=m +CONFIG_NFT_DUP_NETDEV=m +CONFIG_NFT_FWD_NETDEV=m +CONFIG_NFT_FIB_NETDEV=m +CONFIG_NF_FLOW_TABLE_INET=m +CONFIG_NF_FLOW_TABLE=m +CONFIG_NETFILTER_XT_SET=m +CONFIG_NETFILTER_XT_TARGET_CHECKSUM=m +CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m +CONFIG_NETFILTER_XT_TARGET_CONNMARK=m +CONFIG_NETFILTER_XT_TARGET_DSCP=m +CONFIG_NETFILTER_XT_TARGET_HMARK=m +CONFIG_NETFILTER_XT_TARGET_IDLETIMER=m +CONFIG_NETFILTER_XT_TARGET_LOG=m +CONFIG_NETFILTER_XT_TARGET_MARK=m +CONFIG_NETFILTER_XT_TARGET_NFLOG=m +CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m +CONFIG_NETFILTER_XT_TARGET_NOTRACK=m +CONFIG_NETFILTER_XT_TARGET_TEE=m +CONFIG_NETFILTER_XT_TARGET_TPROXY=m +CONFIG_NETFILTER_XT_TARGET_TRACE=m +CONFIG_NETFILTER_XT_TARGET_TCPMSS=m +CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP=m +CONFIG_NETFILTER_XT_MATCH_ADDRTYPE=m +CONFIG_NETFILTER_XT_MATCH_BPF=m +CONFIG_NETFILTER_XT_MATCH_CLUSTER=m +CONFIG_NETFILTER_XT_MATCH_COMMENT=m +CONFIG_NETFILTER_XT_MATCH_CONNBYTES=m +CONFIG_NETFILTER_XT_MATCH_CONNLABEL=m +CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=m +CONFIG_NETFILTER_XT_MATCH_CONNMARK=m +CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m +CONFIG_NETFILTER_XT_MATCH_DEVGROUP=m +CONFIG_NETFILTER_XT_MATCH_DSCP=m +CONFIG_NETFILTER_XT_MATCH_ESP=m +CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=m +CONFIG_NETFILTER_XT_MATCH_HELPER=m +CONFIG_NETFILTER_XT_MATCH_IPCOMP=m +CONFIG_NETFILTER_XT_MATCH_IPRANGE=m +CONFIG_NETFILTER_XT_MATCH_LENGTH=m +CONFIG_NETFILTER_XT_MATCH_LIMIT=m +CONFIG_NETFILTER_XT_MATCH_MAC=m +CONFIG_NETFILTER_XT_MATCH_MARK=m +CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m +CONFIG_NETFILTER_XT_MATCH_NFACCT=m +CONFIG_NETFILTER_XT_MATCH_OSF=m +CONFIG_NETFILTER_XT_MATCH_OWNER=m +CONFIG_NETFILTER_XT_MATCH_POLICY=m +CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m +CONFIG_NETFILTER_XT_MATCH_QUOTA=m +CONFIG_NETFILTER_XT_MATCH_RATEEST=m +CONFIG_NETFILTER_XT_MATCH_REALM=m +CONFIG_NETFILTER_XT_MATCH_RECENT=m +CONFIG_NETFILTER_XT_MATCH_SOCKET=m +CONFIG_NETFILTER_XT_MATCH_STATE=m +CONFIG_NETFILTER_XT_MATCH_STATISTIC=m +CONFIG_NETFILTER_XT_MATCH_STRING=m +CONFIG_NETFILTER_XT_MATCH_TCPMSS=m +CONFIG_NETFILTER_XT_MATCH_TIME=m +CONFIG_NETFILTER_XT_MATCH_U32=m +CONFIG_IP_SET=m +CONFIG_IP_SET_BITMAP_IP=m +CONFIG_IP_SET_BITMAP_IPMAC=m +CONFIG_IP_SET_BITMAP_PORT=m +CONFIG_IP_SET_HASH_IP=m +CONFIG_IP_SET_HASH_IPMARK=m +CONFIG_IP_SET_HASH_IPPORT=m +CONFIG_IP_SET_HASH_IPPORTIP=m +CONFIG_IP_SET_HASH_IPPORTNET=m +CONFIG_IP_SET_HASH_IPMAC=m +CONFIG_IP_SET_HASH_MAC=m +CONFIG_IP_SET_HASH_NETPORTNET=m +CONFIG_IP_SET_HASH_NET=m +CONFIG_IP_SET_HASH_NETNET=m +CONFIG_IP_SET_HASH_NETPORT=m +CONFIG_IP_SET_HASH_NETIFACE=m +CONFIG_IP_SET_LIST_SET=m +CONFIG_NFT_DUP_IPV4=m +CONFIG_NFT_FIB_IPV4=m +CONFIG_NF_TABLES_ARP=y +CONFIG_NF_FLOW_TABLE_IPV4=m +CONFIG_NF_LOG_ARP=m +CONFIG_IP_NF_IPTABLES=m +CONFIG_IP_NF_MATCH_AH=m +CONFIG_IP_NF_MATCH_ECN=m +CONFIG_IP_NF_MATCH_RPFILTER=m +CONFIG_IP_NF_MATCH_TTL=m +CONFIG_IP_NF_FILTER=m +CONFIG_IP_NF_TARGET_REJECT=m +CONFIG_IP_NF_TARGET_SYNPROXY=m +CONFIG_IP_NF_NAT=m +CONFIG_IP_NF_TARGET_MASQUERADE=m +CONFIG_IP_NF_TARGET_NETMAP=m +CONFIG_IP_NF_TARGET_REDIRECT=m +CONFIG_IP_NF_MANGLE=m +CONFIG_IP_NF_TARGET_CLUSTERIP=m +CONFIG_IP_NF_TARGET_ECN=m +CONFIG_IP_NF_TARGET_TTL=m +CONFIG_IP_NF_RAW=m +CONFIG_IP_NF_ARPTABLES=m +CONFIG_IP_NF_ARPFILTER=m +CONFIG_IP_NF_ARP_MANGLE=m +CONFIG_NFT_DUP_IPV6=m +CONFIG_NFT_FIB_IPV6=m +CONFIG_NF_FLOW_TABLE_IPV6=m +CONFIG_IP6_NF_IPTABLES=m +CONFIG_IP6_NF_MATCH_AH=m +CONFIG_IP6_NF_MATCH_EUI64=m +CONFIG_IP6_NF_MATCH_FRAG=m +CONFIG_IP6_NF_MATCH_OPTS=m +CONFIG_IP6_NF_MATCH_HL=m +CONFIG_IP6_NF_MATCH_IPV6HEADER=m +CONFIG_IP6_NF_MATCH_MH=m +CONFIG_IP6_NF_MATCH_RPFILTER=m +CONFIG_IP6_NF_MATCH_RT=m +CONFIG_IP6_NF_MATCH_SRH=m +CONFIG_IP6_NF_TARGET_HL=m +CONFIG_IP6_NF_FILTER=m +CONFIG_IP6_NF_TARGET_REJECT=m +CONFIG_IP6_NF_TARGET_SYNPROXY=m +CONFIG_IP6_NF_MANGLE=m +CONFIG_IP6_NF_RAW=m +CONFIG_IP6_NF_NAT=m +CONFIG_IP6_NF_TARGET_MASQUERADE=m +CONFIG_IP6_NF_TARGET_NPT=m +CONFIG_NF_TABLES_BRIDGE=m +CONFIG_NFT_BRIDGE_META=m +CONFIG_NFT_BRIDGE_REJECT=m +CONFIG_NF_LOG_BRIDGE=m +CONFIG_NF_CONNTRACK_BRIDGE=m +CONFIG_BRIDGE_NF_EBTABLES=m +CONFIG_BRIDGE_EBT_BROUTE=m +CONFIG_BRIDGE_EBT_T_FILTER=m +CONFIG_BRIDGE_EBT_T_NAT=m +CONFIG_BRIDGE_EBT_802_3=m +CONFIG_BRIDGE_EBT_AMONG=m +CONFIG_BRIDGE_EBT_ARP=m +CONFIG_BRIDGE_EBT_IP=m +CONFIG_BRIDGE_EBT_IP6=m +CONFIG_BRIDGE_EBT_LIMIT=m +CONFIG_BRIDGE_EBT_MARK=m +CONFIG_BRIDGE_EBT_PKTTYPE=m +CONFIG_BRIDGE_EBT_STP=m +CONFIG_BRIDGE_EBT_VLAN=m +CONFIG_BRIDGE_EBT_ARPREPLY=m +CONFIG_BRIDGE_EBT_DNAT=m +CONFIG_BRIDGE_EBT_MARK_T=m +CONFIG_BRIDGE_EBT_REDIRECT=m +CONFIG_BRIDGE_EBT_SNAT=m +CONFIG_BRIDGE_EBT_LOG=m +CONFIG_BRIDGE_EBT_NFLOG=m +CONFIG_IP_DCCP=m +# CONFIG_IP_DCCP_CCID3 is not set +CONFIG_SCTP_COOKIE_HMAC_SHA1=y +CONFIG_RDS=m +CONFIG_RDS_TCP=m +CONFIG_L2TP=m +CONFIG_BRIDGE=m +CONFIG_ATALK=m +CONFIG_6LOWPAN=m +CONFIG_6LOWPAN_GHC_EXT_HDR_HOP=m +CONFIG_6LOWPAN_GHC_UDP=m +CONFIG_6LOWPAN_GHC_ICMPV6=m +CONFIG_6LOWPAN_GHC_EXT_HDR_DEST=m +CONFIG_6LOWPAN_GHC_EXT_HDR_FRAG=m +CONFIG_6LOWPAN_GHC_EXT_HDR_ROUTE=m +CONFIG_DNS_RESOLVER=y +CONFIG_BATMAN_ADV=m +# CONFIG_BATMAN_ADV_BATMAN_V is not set +CONFIG_BATMAN_ADV_NC=y +CONFIG_NETLINK_DIAG=m +CONFIG_MPLS=y +CONFIG_NET_MPLS_GSO=m +CONFIG_MPLS_ROUTING=m +CONFIG_MPLS_IPTUNNEL=m +CONFIG_NET_NSH=m +CONFIG_AF_KCM=m +# CONFIG_WIRELESS is not set +CONFIG_PSAMPLE=m +CONFIG_NET_IFE=m +CONFIG_DEVTMPFS=y +CONFIG_DEVTMPFS_MOUNT=y +CONFIG_TEST_ASYNC_DRIVER_PROBE=m +CONFIG_CONNECTOR=m +CONFIG_PARPORT=m +CONFIG_PARPORT_ATARI=m +CONFIG_PARPORT_1284=y +CONFIG_ATARI_FLOPPY=y +CONFIG_BLK_DEV_LOOP=y +CONFIG_BLK_DEV_CRYPTOLOOP=m +CONFIG_BLK_DEV_DRBD=m +CONFIG_BLK_DEV_NBD=m +CONFIG_BLK_DEV_RAM=y +CONFIG_CDROM_PKTCDVD=m +CONFIG_ATA_OVER_ETH=m +CONFIG_DUMMY_IRQ=m +CONFIG_IDE=y +CONFIG_IDE_GD_ATAPI=y +CONFIG_BLK_DEV_IDECD=y +CONFIG_BLK_DEV_FALCON_IDE=y +CONFIG_RAID_ATTRS=m +CONFIG_SCSI=y +CONFIG_BLK_DEV_SD=y +CONFIG_CHR_DEV_ST=m +CONFIG_BLK_DEV_SR=y +CONFIG_CHR_DEV_SG=m +CONFIG_SCSI_CONSTANTS=y +CONFIG_SCSI_SAS_ATTRS=m +CONFIG_ISCSI_TCP=m +CONFIG_ISCSI_BOOT_SYSFS=m +CONFIG_ATARI_SCSI=y +CONFIG_MD=y +CONFIG_MD_LINEAR=m +CONFIG_BLK_DEV_DM=m +CONFIG_DM_UNSTRIPED=m +CONFIG_DM_CRYPT=m +CONFIG_DM_SNAPSHOT=m +CONFIG_DM_THIN_PROVISIONING=m +CONFIG_DM_WRITECACHE=m +CONFIG_DM_ERA=m +CONFIG_DM_CLONE=m +CONFIG_DM_MIRROR=m +CONFIG_DM_RAID=m +CONFIG_DM_ZERO=m +CONFIG_DM_MULTIPATH=m +CONFIG_DM_UEVENT=y +CONFIG_DM_LOG_WRITES=m +CONFIG_DM_INTEGRITY=m +CONFIG_TARGET_CORE=m +CONFIG_TCM_IBLOCK=m +CONFIG_TCM_FILEIO=m +CONFIG_TCM_PSCSI=m +CONFIG_NETDEVICES=y +CONFIG_DUMMY=m +CONFIG_WIREGUARD=m +CONFIG_EQUALIZER=m +CONFIG_NET_TEAM=m +CONFIG_NET_TEAM_MODE_BROADCAST=m +CONFIG_NET_TEAM_MODE_ROUNDROBIN=m +CONFIG_NET_TEAM_MODE_RANDOM=m +CONFIG_NET_TEAM_MODE_ACTIVEBACKUP=m +CONFIG_NET_TEAM_MODE_LOADBALANCE=m +CONFIG_MACVLAN=m +CONFIG_MACVTAP=m +CONFIG_IPVLAN=m +CONFIG_IPVTAP=m +CONFIG_VXLAN=m +CONFIG_GENEVE=m +CONFIG_BAREUDP=m +CONFIG_GTP=m +CONFIG_MACSEC=m +CONFIG_NETCONSOLE=m +CONFIG_NETCONSOLE_DYNAMIC=y +CONFIG_VETH=m +CONFIG_ATARILANCE=y +CONFIG_NE2000=y +CONFIG_SMC91X=y +CONFIG_PPP=m +CONFIG_PPP_BSDCOMP=m +CONFIG_PPP_DEFLATE=m +CONFIG_PPP_FILTER=y +CONFIG_PPP_MPPE=m +CONFIG_PPPOE=m +CONFIG_PPTP=m +CONFIG_PPPOL2TP=m +CONFIG_PPP_ASYNC=m +CONFIG_PPP_SYNC_TTY=m +CONFIG_SLIP=m +CONFIG_SLIP_COMPRESSED=y +CONFIG_SLIP_SMART=y +CONFIG_SLIP_MODE_SLIP6=y +# CONFIG_WLAN is not set +CONFIG_INPUT_EVDEV=m +CONFIG_KEYBOARD_ATARI=y +# CONFIG_KEYBOARD_ATKBD is not set +# CONFIG_MOUSE_PS2 is not set +CONFIG_MOUSE_ATARI=m +CONFIG_INPUT_MISC=y +CONFIG_INPUT_M68K_BEEP=m +# CONFIG_SERIO is not set +# CONFIG_LEGACY_PTYS is not set +CONFIG_PRINTER=m +# CONFIG_HW_RANDOM is not set +CONFIG_NTP_PPS=y +CONFIG_PPS_CLIENT_LDISC=m +CONFIG_PPS_CLIENT_PARPORT=m +CONFIG_PTP_1588_CLOCK=m +# CONFIG_HWMON is not set +CONFIG_FB=y +CONFIG_FB_ATARI=y +CONFIG_FRAMEBUFFER_CONSOLE=y +CONFIG_LOGO=y +CONFIG_SOUND=m +CONFIG_DMASOUND_ATARI=m +CONFIG_HID=m +CONFIG_HIDRAW=y +CONFIG_UHID=m +# CONFIG_HID_GENERIC is not set +# CONFIG_HID_ITE is not set +CONFIG_RTC_CLASS=y +# CONFIG_RTC_NVMEM is not set +CONFIG_RTC_DRV_GENERIC=m +# CONFIG_VIRTIO_MENU is not set +# CONFIG_VHOST_MENU is not set +# CONFIG_IOMMU_SUPPORT is not set +CONFIG_DAX=m +CONFIG_EXT4_FS=y +CONFIG_REISERFS_FS=m +CONFIG_JFS_FS=m +CONFIG_OCFS2_FS=m +# CONFIG_OCFS2_DEBUG_MASKLOG is not set +CONFIG_FANOTIFY=y +CONFIG_QUOTA_NETLINK_INTERFACE=y +# CONFIG_PRINT_QUOTA_WARNING is not set +CONFIG_AUTOFS_FS=m +CONFIG_FUSE_FS=m +CONFIG_CUSE=m +CONFIG_OVERLAY_FS=m +CONFIG_ISO9660_FS=y +CONFIG_JOLIET=y +CONFIG_ZISOFS=y +CONFIG_UDF_FS=m +CONFIG_MSDOS_FS=m +CONFIG_VFAT_FS=m +CONFIG_EXFAT_FS=m +CONFIG_PROC_KCORE=y +CONFIG_PROC_CHILDREN=y +CONFIG_TMPFS=y +CONFIG_ORANGEFS_FS=m +CONFIG_AFFS_FS=m +CONFIG_ECRYPT_FS=m +CONFIG_ECRYPT_FS_MESSAGING=y +CONFIG_HFS_FS=m +CONFIG_HFSPLUS_FS=m +CONFIG_CRAMFS=m +CONFIG_SQUASHFS=m +CONFIG_SQUASHFS_LZ4=y +CONFIG_SQUASHFS_LZO=y +CONFIG_MINIX_FS=m +CONFIG_OMFS_FS=m +CONFIG_HPFS_FS=m +CONFIG_QNX4FS_FS=m +CONFIG_QNX6FS_FS=m +CONFIG_SYSV_FS=m +CONFIG_UFS_FS=m +CONFIG_EROFS_FS=m +CONFIG_NFS_FS=y +CONFIG_NFS_V4=m +CONFIG_NFS_SWAP=y +CONFIG_ROOT_NFS=y +CONFIG_NFSD=m +CONFIG_NFSD_V3=y +CONFIG_CIFS=m +# CONFIG_CIFS_DEBUG is not set +CONFIG_CODA_FS=m +CONFIG_NLS_CODEPAGE_437=y +CONFIG_NLS_CODEPAGE_737=m +CONFIG_NLS_CODEPAGE_775=m +CONFIG_NLS_CODEPAGE_850=m +CONFIG_NLS_CODEPAGE_852=m +CONFIG_NLS_CODEPAGE_855=m +CONFIG_NLS_CODEPAGE_857=m +CONFIG_NLS_CODEPAGE_860=m +CONFIG_NLS_CODEPAGE_861=m +CONFIG_NLS_CODEPAGE_862=m +CONFIG_NLS_CODEPAGE_863=m +CONFIG_NLS_CODEPAGE_864=m +CONFIG_NLS_CODEPAGE_865=m +CONFIG_NLS_CODEPAGE_866=m +CONFIG_NLS_CODEPAGE_869=m +CONFIG_NLS_CODEPAGE_936=m +CONFIG_NLS_CODEPAGE_950=m +CONFIG_NLS_CODEPAGE_932=m +CONFIG_NLS_CODEPAGE_949=m +CONFIG_NLS_CODEPAGE_874=m +CONFIG_NLS_ISO8859_8=m +CONFIG_NLS_CODEPAGE_1250=m +CONFIG_NLS_CODEPAGE_1251=m +CONFIG_NLS_ASCII=m +CONFIG_NLS_ISO8859_1=y +CONFIG_NLS_ISO8859_2=m +CONFIG_NLS_ISO8859_3=m +CONFIG_NLS_ISO8859_4=m +CONFIG_NLS_ISO8859_5=m +CONFIG_NLS_ISO8859_6=m +CONFIG_NLS_ISO8859_7=m +CONFIG_NLS_ISO8859_9=m +CONFIG_NLS_ISO8859_13=m +CONFIG_NLS_ISO8859_14=m +CONFIG_NLS_ISO8859_15=m +CONFIG_NLS_KOI8_R=m +CONFIG_NLS_KOI8_U=m +CONFIG_NLS_MAC_ROMAN=m +CONFIG_NLS_MAC_CELTIC=m +CONFIG_NLS_MAC_CENTEURO=m +CONFIG_NLS_MAC_CROATIAN=m +CONFIG_NLS_MAC_CYRILLIC=m +CONFIG_NLS_MAC_GAELIC=m +CONFIG_NLS_MAC_GREEK=m +CONFIG_NLS_MAC_ICELAND=m +CONFIG_NLS_MAC_INUIT=m +CONFIG_NLS_MAC_ROMANIAN=m +CONFIG_NLS_MAC_TURKISH=m +CONFIG_DLM=m +CONFIG_ENCRYPTED_KEYS=m +CONFIG_HARDENED_USERCOPY=y +CONFIG_CRYPTO_MANAGER=y +CONFIG_CRYPTO_USER=m +CONFIG_CRYPTO_CRYPTD=m +CONFIG_CRYPTO_TEST=m +CONFIG_CRYPTO_RSA=m +CONFIG_CRYPTO_DH=m +CONFIG_CRYPTO_ECDH=m +CONFIG_CRYPTO_ECRDSA=m +CONFIG_CRYPTO_CURVE25519=m +CONFIG_CRYPTO_CHACHA20POLY1305=m +CONFIG_CRYPTO_AEGIS128=m +CONFIG_CRYPTO_CFB=m +CONFIG_CRYPTO_CTS=m +CONFIG_CRYPTO_LRW=m +CONFIG_CRYPTO_OFB=m +CONFIG_CRYPTO_PCBC=m +CONFIG_CRYPTO_XTS=m +CONFIG_CRYPTO_KEYWRAP=m +CONFIG_CRYPTO_ADIANTUM=m +CONFIG_CRYPTO_XCBC=m +CONFIG_CRYPTO_VMAC=m +CONFIG_CRYPTO_BLAKE2S=m +CONFIG_CRYPTO_MICHAEL_MIC=m +CONFIG_CRYPTO_RMD128=m +CONFIG_CRYPTO_RMD160=m +CONFIG_CRYPTO_RMD256=m +CONFIG_CRYPTO_RMD320=m +CONFIG_CRYPTO_SHA3=m +CONFIG_CRYPTO_SM3=m +CONFIG_CRYPTO_TGR192=m +CONFIG_CRYPTO_WP512=m +CONFIG_CRYPTO_AES=y +CONFIG_CRYPTO_AES_TI=m +CONFIG_CRYPTO_ANUBIS=m +CONFIG_CRYPTO_ARC4=m +CONFIG_CRYPTO_BLOWFISH=m +CONFIG_CRYPTO_CAMELLIA=m +CONFIG_CRYPTO_CAST5=m +CONFIG_CRYPTO_CAST6=m +CONFIG_CRYPTO_DES=m +CONFIG_CRYPTO_FCRYPT=m +CONFIG_CRYPTO_KHAZAD=m +CONFIG_CRYPTO_SALSA20=m +CONFIG_CRYPTO_SEED=m +CONFIG_CRYPTO_SERPENT=m +CONFIG_CRYPTO_SM4=m +CONFIG_CRYPTO_TEA=m +CONFIG_CRYPTO_TWOFISH=m +CONFIG_CRYPTO_LZO=m +CONFIG_CRYPTO_842=m +CONFIG_CRYPTO_LZ4=m +CONFIG_CRYPTO_LZ4HC=m +CONFIG_CRYPTO_ZSTD=m +CONFIG_CRYPTO_ANSI_CPRNG=m +CONFIG_CRYPTO_DRBG_HASH=y +CONFIG_CRYPTO_DRBG_CTR=y +CONFIG_CRYPTO_USER_API_HASH=m +CONFIG_CRYPTO_USER_API_SKCIPHER=m +CONFIG_CRYPTO_USER_API_RNG=m +CONFIG_CRYPTO_USER_API_AEAD=m +# CONFIG_CRYPTO_HW is not set +CONFIG_PRIME_NUMBERS=m +CONFIG_CRC32_SELFTEST=m +CONFIG_CRC64=m +CONFIG_XZ_DEC_TEST=m +CONFIG_STRING_SELFTEST=m +# CONFIG_SECTION_MISMATCH_WARN_ONLY is not set +CONFIG_MAGIC_SYSRQ=y +CONFIG_TEST_LOCKUP=m +CONFIG_WW_MUTEX_SELFTEST=m +CONFIG_EARLY_PRINTK=y +CONFIG_TEST_LIST_SORT=m +CONFIG_TEST_MIN_HEAP=m +CONFIG_TEST_SORT=m +CONFIG_REED_SOLOMON_TEST=m +CONFIG_ATOMIC64_SELFTEST=m +CONFIG_ASYNC_RAID6_TEST=m +CONFIG_TEST_HEXDUMP=m +CONFIG_TEST_STRING_HELPERS=m +CONFIG_TEST_STRSCPY=m +CONFIG_TEST_KSTRTOX=m +CONFIG_TEST_PRINTF=m +CONFIG_TEST_BITMAP=m +CONFIG_TEST_BITFIELD=m +CONFIG_TEST_UUID=m +CONFIG_TEST_XARRAY=m +CONFIG_TEST_OVERFLOW=m +CONFIG_TEST_RHASHTABLE=m +CONFIG_TEST_HASH=m +CONFIG_TEST_IDA=m +CONFIG_TEST_BITOPS=m +CONFIG_TEST_VMALLOC=m +CONFIG_TEST_USER_COPY=m +CONFIG_TEST_BPF=m +CONFIG_TEST_BLACKHOLE_DEV=m +CONFIG_FIND_BIT_BENCHMARK=m +CONFIG_TEST_FIRMWARE=m +CONFIG_TEST_SYSCTL=m +CONFIG_TEST_UDELAY=m +CONFIG_TEST_STATIC_KEYS=m +CONFIG_TEST_KMOD=m +CONFIG_TEST_MEMCAT_P=m +CONFIG_TEST_STACKINIT=m +CONFIG_TEST_MEMINIT=m diff --git a/arch/m68k/configs/bvme6000_defconfig b/arch/m68k/configs/bvme6000_defconfig new file mode 100644 index 000000000..d574e438e --- /dev/null +++ b/arch/m68k/configs/bvme6000_defconfig @@ -0,0 +1,610 @@ +CONFIG_LOCALVERSION="-bvme6000" +CONFIG_SYSVIPC=y +CONFIG_POSIX_MQUEUE=y +CONFIG_BSD_PROCESS_ACCT=y +CONFIG_BSD_PROCESS_ACCT_V3=y +CONFIG_LOG_BUF_SHIFT=16 +# CONFIG_UTS_NS is not set +# CONFIG_IPC_NS is not set +# CONFIG_PID_NS is not set +# CONFIG_NET_NS is not set +CONFIG_BLK_DEV_INITRD=y +CONFIG_CC_OPTIMIZE_FOR_SIZE=y +CONFIG_USERFAULTFD=y +CONFIG_SLAB=y +CONFIG_KEXEC=y +CONFIG_BOOTINFO_PROC=y +CONFIG_M68040=y +CONFIG_M68060=y +CONFIG_VME=y +CONFIG_BVME6000=y +CONFIG_PROC_HARDWARE=y +CONFIG_MODULES=y +CONFIG_MODULE_UNLOAD=y +CONFIG_PARTITION_ADVANCED=y +CONFIG_AMIGA_PARTITION=y +CONFIG_ATARI_PARTITION=y +CONFIG_MAC_PARTITION=y +CONFIG_BSD_DISKLABEL=y +CONFIG_MINIX_SUBPARTITION=y +CONFIG_SOLARIS_X86_PARTITION=y +CONFIG_UNIXWARE_DISKLABEL=y +CONFIG_SUN_PARTITION=y +# CONFIG_EFI_PARTITION is not set +CONFIG_MQ_IOSCHED_DEADLINE=m +CONFIG_MQ_IOSCHED_KYBER=m +CONFIG_IOSCHED_BFQ=m +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +CONFIG_BINFMT_AOUT=m +CONFIG_BINFMT_MISC=m +# CONFIG_COMPACTION is not set +CONFIG_CLEANCACHE=y +CONFIG_ZPOOL=m +CONFIG_NET=y +CONFIG_PACKET=y +CONFIG_PACKET_DIAG=m +CONFIG_UNIX=y +CONFIG_UNIX_DIAG=m +CONFIG_TLS=m +CONFIG_XFRM_MIGRATE=y +CONFIG_NET_KEY=y +CONFIG_XDP_SOCKETS=y +CONFIG_XDP_SOCKETS_DIAG=m +CONFIG_INET=y +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +CONFIG_IP_PNP_BOOTP=y +CONFIG_IP_PNP_RARP=y +CONFIG_NET_IPIP=m +CONFIG_NET_IPGRE_DEMUX=m +CONFIG_NET_IPGRE=m +CONFIG_NET_IPVTI=m +CONFIG_NET_FOU_IP_TUNNELS=y +CONFIG_INET_AH=m +CONFIG_INET_ESP=m +CONFIG_INET_ESP_OFFLOAD=m +CONFIG_INET_IPCOMP=m +CONFIG_INET_DIAG=m +CONFIG_INET_UDP_DIAG=m +CONFIG_INET_RAW_DIAG=m +CONFIG_IPV6=m +CONFIG_IPV6_ROUTER_PREF=y +CONFIG_INET6_AH=m +CONFIG_INET6_ESP=m +CONFIG_INET6_ESP_OFFLOAD=m +CONFIG_INET6_IPCOMP=m +CONFIG_IPV6_ILA=m +CONFIG_IPV6_VTI=m +CONFIG_IPV6_GRE=m +CONFIG_NETFILTER=y +CONFIG_NF_CONNTRACK=m +CONFIG_NF_LOG_NETDEV=m +CONFIG_NF_CONNTRACK_ZONES=y +# CONFIG_NF_CONNTRACK_PROCFS is not set +# CONFIG_NF_CT_PROTO_DCCP is not set +CONFIG_NF_CONNTRACK_AMANDA=m +CONFIG_NF_CONNTRACK_FTP=m +CONFIG_NF_CONNTRACK_H323=m +CONFIG_NF_CONNTRACK_IRC=m +CONFIG_NF_CONNTRACK_NETBIOS_NS=m +CONFIG_NF_CONNTRACK_SNMP=m +CONFIG_NF_CONNTRACK_PPTP=m +CONFIG_NF_CONNTRACK_SANE=m +CONFIG_NF_CONNTRACK_SIP=m +CONFIG_NF_CONNTRACK_TFTP=m +CONFIG_NF_TABLES=m +CONFIG_NF_TABLES_INET=y +CONFIG_NF_TABLES_NETDEV=y +CONFIG_NFT_NUMGEN=m +CONFIG_NFT_CT=m +CONFIG_NFT_FLOW_OFFLOAD=m +CONFIG_NFT_COUNTER=m +CONFIG_NFT_CONNLIMIT=m +CONFIG_NFT_LOG=m +CONFIG_NFT_LIMIT=m +CONFIG_NFT_MASQ=m +CONFIG_NFT_REDIR=m +CONFIG_NFT_NAT=m +CONFIG_NFT_TUNNEL=m +CONFIG_NFT_OBJREF=m +CONFIG_NFT_QUEUE=m +CONFIG_NFT_QUOTA=m +CONFIG_NFT_REJECT=m +CONFIG_NFT_COMPAT=m +CONFIG_NFT_HASH=m +CONFIG_NFT_FIB_INET=m +CONFIG_NFT_XFRM=m +CONFIG_NFT_SOCKET=m +CONFIG_NFT_OSF=m +CONFIG_NFT_TPROXY=m +CONFIG_NFT_SYNPROXY=m +CONFIG_NFT_DUP_NETDEV=m +CONFIG_NFT_FWD_NETDEV=m +CONFIG_NFT_FIB_NETDEV=m +CONFIG_NF_FLOW_TABLE_INET=m +CONFIG_NF_FLOW_TABLE=m +CONFIG_NETFILTER_XT_SET=m +CONFIG_NETFILTER_XT_TARGET_CHECKSUM=m +CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m +CONFIG_NETFILTER_XT_TARGET_CONNMARK=m +CONFIG_NETFILTER_XT_TARGET_DSCP=m +CONFIG_NETFILTER_XT_TARGET_HMARK=m +CONFIG_NETFILTER_XT_TARGET_IDLETIMER=m +CONFIG_NETFILTER_XT_TARGET_LOG=m +CONFIG_NETFILTER_XT_TARGET_MARK=m +CONFIG_NETFILTER_XT_TARGET_NFLOG=m +CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m +CONFIG_NETFILTER_XT_TARGET_NOTRACK=m +CONFIG_NETFILTER_XT_TARGET_TEE=m +CONFIG_NETFILTER_XT_TARGET_TPROXY=m +CONFIG_NETFILTER_XT_TARGET_TRACE=m +CONFIG_NETFILTER_XT_TARGET_TCPMSS=m +CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP=m +CONFIG_NETFILTER_XT_MATCH_ADDRTYPE=m +CONFIG_NETFILTER_XT_MATCH_BPF=m +CONFIG_NETFILTER_XT_MATCH_CLUSTER=m +CONFIG_NETFILTER_XT_MATCH_COMMENT=m +CONFIG_NETFILTER_XT_MATCH_CONNBYTES=m +CONFIG_NETFILTER_XT_MATCH_CONNLABEL=m +CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=m +CONFIG_NETFILTER_XT_MATCH_CONNMARK=m +CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m +CONFIG_NETFILTER_XT_MATCH_DEVGROUP=m +CONFIG_NETFILTER_XT_MATCH_DSCP=m +CONFIG_NETFILTER_XT_MATCH_ESP=m +CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=m +CONFIG_NETFILTER_XT_MATCH_HELPER=m +CONFIG_NETFILTER_XT_MATCH_IPCOMP=m +CONFIG_NETFILTER_XT_MATCH_IPRANGE=m +CONFIG_NETFILTER_XT_MATCH_LENGTH=m +CONFIG_NETFILTER_XT_MATCH_LIMIT=m +CONFIG_NETFILTER_XT_MATCH_MAC=m +CONFIG_NETFILTER_XT_MATCH_MARK=m +CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m +CONFIG_NETFILTER_XT_MATCH_NFACCT=m +CONFIG_NETFILTER_XT_MATCH_OSF=m +CONFIG_NETFILTER_XT_MATCH_OWNER=m +CONFIG_NETFILTER_XT_MATCH_POLICY=m +CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m +CONFIG_NETFILTER_XT_MATCH_QUOTA=m +CONFIG_NETFILTER_XT_MATCH_RATEEST=m +CONFIG_NETFILTER_XT_MATCH_REALM=m +CONFIG_NETFILTER_XT_MATCH_RECENT=m +CONFIG_NETFILTER_XT_MATCH_SOCKET=m +CONFIG_NETFILTER_XT_MATCH_STATE=m +CONFIG_NETFILTER_XT_MATCH_STATISTIC=m +CONFIG_NETFILTER_XT_MATCH_STRING=m +CONFIG_NETFILTER_XT_MATCH_TCPMSS=m +CONFIG_NETFILTER_XT_MATCH_TIME=m +CONFIG_NETFILTER_XT_MATCH_U32=m +CONFIG_IP_SET=m +CONFIG_IP_SET_BITMAP_IP=m +CONFIG_IP_SET_BITMAP_IPMAC=m +CONFIG_IP_SET_BITMAP_PORT=m +CONFIG_IP_SET_HASH_IP=m +CONFIG_IP_SET_HASH_IPMARK=m +CONFIG_IP_SET_HASH_IPPORT=m +CONFIG_IP_SET_HASH_IPPORTIP=m +CONFIG_IP_SET_HASH_IPPORTNET=m +CONFIG_IP_SET_HASH_IPMAC=m +CONFIG_IP_SET_HASH_MAC=m +CONFIG_IP_SET_HASH_NETPORTNET=m +CONFIG_IP_SET_HASH_NET=m +CONFIG_IP_SET_HASH_NETNET=m +CONFIG_IP_SET_HASH_NETPORT=m +CONFIG_IP_SET_HASH_NETIFACE=m +CONFIG_IP_SET_LIST_SET=m +CONFIG_NFT_DUP_IPV4=m +CONFIG_NFT_FIB_IPV4=m +CONFIG_NF_TABLES_ARP=y +CONFIG_NF_FLOW_TABLE_IPV4=m +CONFIG_NF_LOG_ARP=m +CONFIG_IP_NF_IPTABLES=m +CONFIG_IP_NF_MATCH_AH=m +CONFIG_IP_NF_MATCH_ECN=m +CONFIG_IP_NF_MATCH_RPFILTER=m +CONFIG_IP_NF_MATCH_TTL=m +CONFIG_IP_NF_FILTER=m +CONFIG_IP_NF_TARGET_REJECT=m +CONFIG_IP_NF_TARGET_SYNPROXY=m +CONFIG_IP_NF_NAT=m +CONFIG_IP_NF_TARGET_MASQUERADE=m +CONFIG_IP_NF_TARGET_NETMAP=m +CONFIG_IP_NF_TARGET_REDIRECT=m +CONFIG_IP_NF_MANGLE=m +CONFIG_IP_NF_TARGET_CLUSTERIP=m +CONFIG_IP_NF_TARGET_ECN=m +CONFIG_IP_NF_TARGET_TTL=m +CONFIG_IP_NF_RAW=m +CONFIG_IP_NF_ARPTABLES=m +CONFIG_IP_NF_ARPFILTER=m +CONFIG_IP_NF_ARP_MANGLE=m +CONFIG_NFT_DUP_IPV6=m +CONFIG_NFT_FIB_IPV6=m +CONFIG_NF_FLOW_TABLE_IPV6=m +CONFIG_IP6_NF_IPTABLES=m +CONFIG_IP6_NF_MATCH_AH=m +CONFIG_IP6_NF_MATCH_EUI64=m +CONFIG_IP6_NF_MATCH_FRAG=m +CONFIG_IP6_NF_MATCH_OPTS=m +CONFIG_IP6_NF_MATCH_HL=m +CONFIG_IP6_NF_MATCH_IPV6HEADER=m +CONFIG_IP6_NF_MATCH_MH=m +CONFIG_IP6_NF_MATCH_RPFILTER=m +CONFIG_IP6_NF_MATCH_RT=m +CONFIG_IP6_NF_MATCH_SRH=m +CONFIG_IP6_NF_TARGET_HL=m +CONFIG_IP6_NF_FILTER=m +CONFIG_IP6_NF_TARGET_REJECT=m +CONFIG_IP6_NF_TARGET_SYNPROXY=m +CONFIG_IP6_NF_MANGLE=m +CONFIG_IP6_NF_RAW=m +CONFIG_IP6_NF_NAT=m +CONFIG_IP6_NF_TARGET_MASQUERADE=m +CONFIG_IP6_NF_TARGET_NPT=m +CONFIG_NF_TABLES_BRIDGE=m +CONFIG_NFT_BRIDGE_META=m +CONFIG_NFT_BRIDGE_REJECT=m +CONFIG_NF_LOG_BRIDGE=m +CONFIG_NF_CONNTRACK_BRIDGE=m +CONFIG_BRIDGE_NF_EBTABLES=m +CONFIG_BRIDGE_EBT_BROUTE=m +CONFIG_BRIDGE_EBT_T_FILTER=m +CONFIG_BRIDGE_EBT_T_NAT=m +CONFIG_BRIDGE_EBT_802_3=m +CONFIG_BRIDGE_EBT_AMONG=m +CONFIG_BRIDGE_EBT_ARP=m +CONFIG_BRIDGE_EBT_IP=m +CONFIG_BRIDGE_EBT_IP6=m +CONFIG_BRIDGE_EBT_LIMIT=m +CONFIG_BRIDGE_EBT_MARK=m +CONFIG_BRIDGE_EBT_PKTTYPE=m +CONFIG_BRIDGE_EBT_STP=m +CONFIG_BRIDGE_EBT_VLAN=m +CONFIG_BRIDGE_EBT_ARPREPLY=m +CONFIG_BRIDGE_EBT_DNAT=m +CONFIG_BRIDGE_EBT_MARK_T=m +CONFIG_BRIDGE_EBT_REDIRECT=m +CONFIG_BRIDGE_EBT_SNAT=m +CONFIG_BRIDGE_EBT_LOG=m +CONFIG_BRIDGE_EBT_NFLOG=m +CONFIG_IP_DCCP=m +# CONFIG_IP_DCCP_CCID3 is not set +CONFIG_SCTP_COOKIE_HMAC_SHA1=y +CONFIG_RDS=m +CONFIG_RDS_TCP=m +CONFIG_L2TP=m +CONFIG_BRIDGE=m +CONFIG_ATALK=m +CONFIG_6LOWPAN=m +CONFIG_6LOWPAN_GHC_EXT_HDR_HOP=m +CONFIG_6LOWPAN_GHC_UDP=m +CONFIG_6LOWPAN_GHC_ICMPV6=m +CONFIG_6LOWPAN_GHC_EXT_HDR_DEST=m +CONFIG_6LOWPAN_GHC_EXT_HDR_FRAG=m +CONFIG_6LOWPAN_GHC_EXT_HDR_ROUTE=m +CONFIG_DNS_RESOLVER=y +CONFIG_BATMAN_ADV=m +# CONFIG_BATMAN_ADV_BATMAN_V is not set +CONFIG_BATMAN_ADV_NC=y +CONFIG_NETLINK_DIAG=m +CONFIG_MPLS=y +CONFIG_NET_MPLS_GSO=m +CONFIG_MPLS_ROUTING=m +CONFIG_MPLS_IPTUNNEL=m +CONFIG_NET_NSH=m +CONFIG_AF_KCM=m +# CONFIG_WIRELESS is not set +CONFIG_PSAMPLE=m +CONFIG_NET_IFE=m +CONFIG_DEVTMPFS=y +CONFIG_DEVTMPFS_MOUNT=y +CONFIG_TEST_ASYNC_DRIVER_PROBE=m +CONFIG_CONNECTOR=m +CONFIG_BLK_DEV_LOOP=y +CONFIG_BLK_DEV_CRYPTOLOOP=m +CONFIG_BLK_DEV_DRBD=m +CONFIG_BLK_DEV_NBD=m +CONFIG_BLK_DEV_RAM=y +CONFIG_CDROM_PKTCDVD=m +CONFIG_ATA_OVER_ETH=m +CONFIG_DUMMY_IRQ=m +CONFIG_RAID_ATTRS=m +CONFIG_SCSI=y +CONFIG_BLK_DEV_SD=y +CONFIG_CHR_DEV_ST=m +CONFIG_BLK_DEV_SR=y +CONFIG_CHR_DEV_SG=m +CONFIG_SCSI_CONSTANTS=y +CONFIG_SCSI_SAS_ATTRS=m +CONFIG_ISCSI_TCP=m +CONFIG_ISCSI_BOOT_SYSFS=m +CONFIG_BVME6000_SCSI=y +CONFIG_MD=y +CONFIG_MD_LINEAR=m +CONFIG_BLK_DEV_DM=m +CONFIG_DM_UNSTRIPED=m +CONFIG_DM_CRYPT=m +CONFIG_DM_SNAPSHOT=m +CONFIG_DM_THIN_PROVISIONING=m +CONFIG_DM_WRITECACHE=m +CONFIG_DM_ERA=m +CONFIG_DM_CLONE=m +CONFIG_DM_MIRROR=m +CONFIG_DM_RAID=m +CONFIG_DM_ZERO=m +CONFIG_DM_MULTIPATH=m +CONFIG_DM_UEVENT=y +CONFIG_DM_LOG_WRITES=m +CONFIG_DM_INTEGRITY=m +CONFIG_TARGET_CORE=m +CONFIG_TCM_IBLOCK=m +CONFIG_TCM_FILEIO=m +CONFIG_TCM_PSCSI=m +CONFIG_NETDEVICES=y +CONFIG_DUMMY=m +CONFIG_WIREGUARD=m +CONFIG_EQUALIZER=m +CONFIG_NET_TEAM=m +CONFIG_NET_TEAM_MODE_BROADCAST=m +CONFIG_NET_TEAM_MODE_ROUNDROBIN=m +CONFIG_NET_TEAM_MODE_RANDOM=m +CONFIG_NET_TEAM_MODE_ACTIVEBACKUP=m +CONFIG_NET_TEAM_MODE_LOADBALANCE=m +CONFIG_MACVLAN=m +CONFIG_MACVTAP=m +CONFIG_IPVLAN=m +CONFIG_IPVTAP=m +CONFIG_VXLAN=m +CONFIG_GENEVE=m +CONFIG_BAREUDP=m +CONFIG_GTP=m +CONFIG_MACSEC=m +CONFIG_NETCONSOLE=m +CONFIG_NETCONSOLE_DYNAMIC=y +CONFIG_VETH=m +CONFIG_BVME6000_NET=y +CONFIG_PPP=m +CONFIG_PPP_BSDCOMP=m +CONFIG_PPP_DEFLATE=m +CONFIG_PPP_FILTER=y +CONFIG_PPP_MPPE=m +CONFIG_PPPOE=m +CONFIG_PPTP=m +CONFIG_PPPOL2TP=m +CONFIG_PPP_ASYNC=m +CONFIG_PPP_SYNC_TTY=m +CONFIG_SLIP=m +CONFIG_SLIP_COMPRESSED=y +CONFIG_SLIP_SMART=y +CONFIG_SLIP_MODE_SLIP6=y +# CONFIG_WLAN is not set +CONFIG_INPUT_EVDEV=m +# CONFIG_KEYBOARD_ATKBD is not set +# CONFIG_MOUSE_PS2 is not set +# CONFIG_SERIO is not set +CONFIG_VT_HW_CONSOLE_BINDING=y +# CONFIG_LEGACY_PTYS is not set +# CONFIG_HW_RANDOM is not set +CONFIG_NTP_PPS=y +CONFIG_PPS_CLIENT_LDISC=m +CONFIG_PTP_1588_CLOCK=m +# CONFIG_HWMON is not set +CONFIG_HID=m +CONFIG_HIDRAW=y +CONFIG_UHID=m +# CONFIG_HID_GENERIC is not set +# CONFIG_HID_ITE is not set +# CONFIG_HID_REDRAGON is not set +# CONFIG_USB_SUPPORT is not set +CONFIG_RTC_CLASS=y +# CONFIG_RTC_NVMEM is not set +CONFIG_RTC_DRV_GENERIC=m +# CONFIG_VIRTIO_MENU is not set +# CONFIG_VHOST_MENU is not set +# CONFIG_IOMMU_SUPPORT is not set +CONFIG_DAX=m +CONFIG_EXT4_FS=y +CONFIG_REISERFS_FS=m +CONFIG_JFS_FS=m +CONFIG_OCFS2_FS=m +# CONFIG_OCFS2_DEBUG_MASKLOG is not set +CONFIG_FANOTIFY=y +CONFIG_QUOTA_NETLINK_INTERFACE=y +# CONFIG_PRINT_QUOTA_WARNING is not set +CONFIG_AUTOFS_FS=m +CONFIG_FUSE_FS=m +CONFIG_CUSE=m +CONFIG_OVERLAY_FS=m +CONFIG_ISO9660_FS=y +CONFIG_JOLIET=y +CONFIG_ZISOFS=y +CONFIG_UDF_FS=m +CONFIG_MSDOS_FS=m +CONFIG_VFAT_FS=m +CONFIG_EXFAT_FS=m +CONFIG_PROC_KCORE=y +CONFIG_PROC_CHILDREN=y +CONFIG_TMPFS=y +CONFIG_ORANGEFS_FS=m +CONFIG_AFFS_FS=m +CONFIG_ECRYPT_FS=m +CONFIG_ECRYPT_FS_MESSAGING=y +CONFIG_HFS_FS=m +CONFIG_HFSPLUS_FS=m +CONFIG_CRAMFS=m +CONFIG_SQUASHFS=m +CONFIG_SQUASHFS_LZ4=y +CONFIG_SQUASHFS_LZO=y +CONFIG_MINIX_FS=m +CONFIG_OMFS_FS=m +CONFIG_HPFS_FS=m +CONFIG_QNX4FS_FS=m +CONFIG_QNX6FS_FS=m +CONFIG_SYSV_FS=m +CONFIG_UFS_FS=m +CONFIG_EROFS_FS=m +CONFIG_NFS_FS=y +CONFIG_NFS_V4=m +CONFIG_NFS_SWAP=y +CONFIG_ROOT_NFS=y +CONFIG_NFSD=m +CONFIG_NFSD_V3=y +CONFIG_CIFS=m +# CONFIG_CIFS_DEBUG is not set +CONFIG_CODA_FS=m +CONFIG_NLS_CODEPAGE_437=y +CONFIG_NLS_CODEPAGE_737=m +CONFIG_NLS_CODEPAGE_775=m +CONFIG_NLS_CODEPAGE_850=m +CONFIG_NLS_CODEPAGE_852=m +CONFIG_NLS_CODEPAGE_855=m +CONFIG_NLS_CODEPAGE_857=m +CONFIG_NLS_CODEPAGE_860=m +CONFIG_NLS_CODEPAGE_861=m +CONFIG_NLS_CODEPAGE_862=m +CONFIG_NLS_CODEPAGE_863=m +CONFIG_NLS_CODEPAGE_864=m +CONFIG_NLS_CODEPAGE_865=m +CONFIG_NLS_CODEPAGE_866=m +CONFIG_NLS_CODEPAGE_869=m +CONFIG_NLS_CODEPAGE_936=m +CONFIG_NLS_CODEPAGE_950=m +CONFIG_NLS_CODEPAGE_932=m +CONFIG_NLS_CODEPAGE_949=m +CONFIG_NLS_CODEPAGE_874=m +CONFIG_NLS_ISO8859_8=m +CONFIG_NLS_CODEPAGE_1250=m +CONFIG_NLS_CODEPAGE_1251=m +CONFIG_NLS_ASCII=m +CONFIG_NLS_ISO8859_1=y +CONFIG_NLS_ISO8859_2=m +CONFIG_NLS_ISO8859_3=m +CONFIG_NLS_ISO8859_4=m +CONFIG_NLS_ISO8859_5=m +CONFIG_NLS_ISO8859_6=m +CONFIG_NLS_ISO8859_7=m +CONFIG_NLS_ISO8859_9=m +CONFIG_NLS_ISO8859_13=m +CONFIG_NLS_ISO8859_14=m +CONFIG_NLS_ISO8859_15=m +CONFIG_NLS_KOI8_R=m +CONFIG_NLS_KOI8_U=m +CONFIG_NLS_MAC_ROMAN=m +CONFIG_NLS_MAC_CELTIC=m +CONFIG_NLS_MAC_CENTEURO=m +CONFIG_NLS_MAC_CROATIAN=m +CONFIG_NLS_MAC_CYRILLIC=m +CONFIG_NLS_MAC_GAELIC=m +CONFIG_NLS_MAC_GREEK=m +CONFIG_NLS_MAC_ICELAND=m +CONFIG_NLS_MAC_INUIT=m +CONFIG_NLS_MAC_ROMANIAN=m +CONFIG_NLS_MAC_TURKISH=m +CONFIG_DLM=m +CONFIG_ENCRYPTED_KEYS=m +CONFIG_HARDENED_USERCOPY=y +CONFIG_CRYPTO_MANAGER=y +CONFIG_CRYPTO_USER=m +CONFIG_CRYPTO_CRYPTD=m +CONFIG_CRYPTO_TEST=m +CONFIG_CRYPTO_RSA=m +CONFIG_CRYPTO_DH=m +CONFIG_CRYPTO_ECDH=m +CONFIG_CRYPTO_ECRDSA=m +CONFIG_CRYPTO_CURVE25519=m +CONFIG_CRYPTO_CHACHA20POLY1305=m +CONFIG_CRYPTO_AEGIS128=m +CONFIG_CRYPTO_CFB=m +CONFIG_CRYPTO_CTS=m +CONFIG_CRYPTO_LRW=m +CONFIG_CRYPTO_OFB=m +CONFIG_CRYPTO_PCBC=m +CONFIG_CRYPTO_XTS=m +CONFIG_CRYPTO_KEYWRAP=m +CONFIG_CRYPTO_ADIANTUM=m +CONFIG_CRYPTO_XCBC=m +CONFIG_CRYPTO_VMAC=m +CONFIG_CRYPTO_BLAKE2S=m +CONFIG_CRYPTO_MICHAEL_MIC=m +CONFIG_CRYPTO_RMD128=m +CONFIG_CRYPTO_RMD160=m +CONFIG_CRYPTO_RMD256=m +CONFIG_CRYPTO_RMD320=m +CONFIG_CRYPTO_SHA3=m +CONFIG_CRYPTO_SM3=m +CONFIG_CRYPTO_TGR192=m +CONFIG_CRYPTO_WP512=m +CONFIG_CRYPTO_AES=y +CONFIG_CRYPTO_AES_TI=m +CONFIG_CRYPTO_ANUBIS=m +CONFIG_CRYPTO_ARC4=m +CONFIG_CRYPTO_BLOWFISH=m +CONFIG_CRYPTO_CAMELLIA=m +CONFIG_CRYPTO_CAST5=m +CONFIG_CRYPTO_CAST6=m +CONFIG_CRYPTO_DES=m +CONFIG_CRYPTO_FCRYPT=m +CONFIG_CRYPTO_KHAZAD=m +CONFIG_CRYPTO_SALSA20=m +CONFIG_CRYPTO_SEED=m +CONFIG_CRYPTO_SERPENT=m +CONFIG_CRYPTO_SM4=m +CONFIG_CRYPTO_TEA=m +CONFIG_CRYPTO_TWOFISH=m +CONFIG_CRYPTO_LZO=m +CONFIG_CRYPTO_842=m +CONFIG_CRYPTO_LZ4=m +CONFIG_CRYPTO_LZ4HC=m +CONFIG_CRYPTO_ZSTD=m +CONFIG_CRYPTO_ANSI_CPRNG=m +CONFIG_CRYPTO_DRBG_HASH=y +CONFIG_CRYPTO_DRBG_CTR=y +CONFIG_CRYPTO_USER_API_HASH=m +CONFIG_CRYPTO_USER_API_SKCIPHER=m +CONFIG_CRYPTO_USER_API_RNG=m +CONFIG_CRYPTO_USER_API_AEAD=m +# CONFIG_CRYPTO_HW is not set +CONFIG_PRIME_NUMBERS=m +CONFIG_CRC32_SELFTEST=m +CONFIG_CRC64=m +CONFIG_XZ_DEC_TEST=m +CONFIG_STRING_SELFTEST=m +# CONFIG_SECTION_MISMATCH_WARN_ONLY is not set +CONFIG_MAGIC_SYSRQ=y +CONFIG_TEST_LOCKUP=m +CONFIG_WW_MUTEX_SELFTEST=m +CONFIG_EARLY_PRINTK=y +CONFIG_TEST_LIST_SORT=m +CONFIG_TEST_MIN_HEAP=m +CONFIG_TEST_SORT=m +CONFIG_REED_SOLOMON_TEST=m +CONFIG_ATOMIC64_SELFTEST=m +CONFIG_ASYNC_RAID6_TEST=m +CONFIG_TEST_HEXDUMP=m +CONFIG_TEST_STRING_HELPERS=m +CONFIG_TEST_STRSCPY=m +CONFIG_TEST_KSTRTOX=m +CONFIG_TEST_PRINTF=m +CONFIG_TEST_BITMAP=m +CONFIG_TEST_BITFIELD=m +CONFIG_TEST_UUID=m +CONFIG_TEST_XARRAY=m +CONFIG_TEST_OVERFLOW=m +CONFIG_TEST_RHASHTABLE=m +CONFIG_TEST_HASH=m +CONFIG_TEST_IDA=m +CONFIG_TEST_BITOPS=m +CONFIG_TEST_VMALLOC=m +CONFIG_TEST_USER_COPY=m +CONFIG_TEST_BPF=m +CONFIG_TEST_BLACKHOLE_DEV=m +CONFIG_FIND_BIT_BENCHMARK=m +CONFIG_TEST_FIRMWARE=m +CONFIG_TEST_SYSCTL=m +CONFIG_TEST_UDELAY=m +CONFIG_TEST_STATIC_KEYS=m +CONFIG_TEST_KMOD=m +CONFIG_TEST_MEMCAT_P=m +CONFIG_TEST_STACKINIT=m +CONFIG_TEST_MEMINIT=m diff --git a/arch/m68k/configs/hp300_defconfig b/arch/m68k/configs/hp300_defconfig new file mode 100644 index 000000000..c7ce206e6 --- /dev/null +++ b/arch/m68k/configs/hp300_defconfig @@ -0,0 +1,619 @@ +CONFIG_LOCALVERSION="-hp300" +CONFIG_SYSVIPC=y +CONFIG_POSIX_MQUEUE=y +CONFIG_BSD_PROCESS_ACCT=y +CONFIG_BSD_PROCESS_ACCT_V3=y +CONFIG_LOG_BUF_SHIFT=16 +# CONFIG_UTS_NS is not set +# CONFIG_IPC_NS is not set +# CONFIG_PID_NS is not set +# CONFIG_NET_NS is not set +CONFIG_BLK_DEV_INITRD=y +CONFIG_CC_OPTIMIZE_FOR_SIZE=y +CONFIG_USERFAULTFD=y +CONFIG_SLAB=y +CONFIG_KEXEC=y +CONFIG_BOOTINFO_PROC=y +CONFIG_M68020=y +CONFIG_M68030=y +CONFIG_M68040=y +CONFIG_M68060=y +CONFIG_HP300=y +CONFIG_PROC_HARDWARE=y +CONFIG_MODULES=y +CONFIG_MODULE_UNLOAD=y +CONFIG_PARTITION_ADVANCED=y +CONFIG_AMIGA_PARTITION=y +CONFIG_ATARI_PARTITION=y +CONFIG_MAC_PARTITION=y +CONFIG_BSD_DISKLABEL=y +CONFIG_MINIX_SUBPARTITION=y +CONFIG_SOLARIS_X86_PARTITION=y +CONFIG_UNIXWARE_DISKLABEL=y +CONFIG_SUN_PARTITION=y +# CONFIG_EFI_PARTITION is not set +CONFIG_SYSV68_PARTITION=y +CONFIG_MQ_IOSCHED_DEADLINE=m +CONFIG_MQ_IOSCHED_KYBER=m +CONFIG_IOSCHED_BFQ=m +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +CONFIG_BINFMT_AOUT=m +CONFIG_BINFMT_MISC=m +# CONFIG_COMPACTION is not set +CONFIG_CLEANCACHE=y +CONFIG_ZPOOL=m +CONFIG_NET=y +CONFIG_PACKET=y +CONFIG_PACKET_DIAG=m +CONFIG_UNIX=y +CONFIG_UNIX_DIAG=m +CONFIG_TLS=m +CONFIG_XFRM_MIGRATE=y +CONFIG_NET_KEY=y +CONFIG_XDP_SOCKETS=y +CONFIG_XDP_SOCKETS_DIAG=m +CONFIG_INET=y +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +CONFIG_IP_PNP_BOOTP=y +CONFIG_IP_PNP_RARP=y +CONFIG_NET_IPIP=m +CONFIG_NET_IPGRE_DEMUX=m +CONFIG_NET_IPGRE=m +CONFIG_NET_IPVTI=m +CONFIG_NET_FOU_IP_TUNNELS=y +CONFIG_INET_AH=m +CONFIG_INET_ESP=m +CONFIG_INET_ESP_OFFLOAD=m +CONFIG_INET_IPCOMP=m +CONFIG_INET_DIAG=m +CONFIG_INET_UDP_DIAG=m +CONFIG_INET_RAW_DIAG=m +CONFIG_IPV6=m +CONFIG_IPV6_ROUTER_PREF=y +CONFIG_INET6_AH=m +CONFIG_INET6_ESP=m +CONFIG_INET6_ESP_OFFLOAD=m +CONFIG_INET6_IPCOMP=m +CONFIG_IPV6_ILA=m +CONFIG_IPV6_VTI=m +CONFIG_IPV6_GRE=m +CONFIG_NETFILTER=y +CONFIG_NF_CONNTRACK=m +CONFIG_NF_LOG_NETDEV=m +CONFIG_NF_CONNTRACK_ZONES=y +# CONFIG_NF_CONNTRACK_PROCFS is not set +# CONFIG_NF_CT_PROTO_DCCP is not set +CONFIG_NF_CONNTRACK_AMANDA=m +CONFIG_NF_CONNTRACK_FTP=m +CONFIG_NF_CONNTRACK_H323=m +CONFIG_NF_CONNTRACK_IRC=m +CONFIG_NF_CONNTRACK_NETBIOS_NS=m +CONFIG_NF_CONNTRACK_SNMP=m +CONFIG_NF_CONNTRACK_PPTP=m +CONFIG_NF_CONNTRACK_SANE=m +CONFIG_NF_CONNTRACK_SIP=m +CONFIG_NF_CONNTRACK_TFTP=m +CONFIG_NF_TABLES=m +CONFIG_NF_TABLES_INET=y +CONFIG_NF_TABLES_NETDEV=y +CONFIG_NFT_NUMGEN=m +CONFIG_NFT_CT=m +CONFIG_NFT_FLOW_OFFLOAD=m +CONFIG_NFT_COUNTER=m +CONFIG_NFT_CONNLIMIT=m +CONFIG_NFT_LOG=m +CONFIG_NFT_LIMIT=m +CONFIG_NFT_MASQ=m +CONFIG_NFT_REDIR=m +CONFIG_NFT_NAT=m +CONFIG_NFT_TUNNEL=m +CONFIG_NFT_OBJREF=m +CONFIG_NFT_QUEUE=m +CONFIG_NFT_QUOTA=m +CONFIG_NFT_REJECT=m +CONFIG_NFT_COMPAT=m +CONFIG_NFT_HASH=m +CONFIG_NFT_FIB_INET=m +CONFIG_NFT_XFRM=m +CONFIG_NFT_SOCKET=m +CONFIG_NFT_OSF=m +CONFIG_NFT_TPROXY=m +CONFIG_NFT_SYNPROXY=m +CONFIG_NFT_DUP_NETDEV=m +CONFIG_NFT_FWD_NETDEV=m +CONFIG_NFT_FIB_NETDEV=m +CONFIG_NF_FLOW_TABLE_INET=m +CONFIG_NF_FLOW_TABLE=m +CONFIG_NETFILTER_XT_SET=m +CONFIG_NETFILTER_XT_TARGET_CHECKSUM=m +CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m +CONFIG_NETFILTER_XT_TARGET_CONNMARK=m +CONFIG_NETFILTER_XT_TARGET_DSCP=m +CONFIG_NETFILTER_XT_TARGET_HMARK=m +CONFIG_NETFILTER_XT_TARGET_IDLETIMER=m +CONFIG_NETFILTER_XT_TARGET_LOG=m +CONFIG_NETFILTER_XT_TARGET_MARK=m +CONFIG_NETFILTER_XT_TARGET_NFLOG=m +CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m +CONFIG_NETFILTER_XT_TARGET_NOTRACK=m +CONFIG_NETFILTER_XT_TARGET_TEE=m +CONFIG_NETFILTER_XT_TARGET_TPROXY=m +CONFIG_NETFILTER_XT_TARGET_TRACE=m +CONFIG_NETFILTER_XT_TARGET_TCPMSS=m +CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP=m +CONFIG_NETFILTER_XT_MATCH_ADDRTYPE=m +CONFIG_NETFILTER_XT_MATCH_BPF=m +CONFIG_NETFILTER_XT_MATCH_CLUSTER=m +CONFIG_NETFILTER_XT_MATCH_COMMENT=m +CONFIG_NETFILTER_XT_MATCH_CONNBYTES=m +CONFIG_NETFILTER_XT_MATCH_CONNLABEL=m +CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=m +CONFIG_NETFILTER_XT_MATCH_CONNMARK=m +CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m +CONFIG_NETFILTER_XT_MATCH_DEVGROUP=m +CONFIG_NETFILTER_XT_MATCH_DSCP=m +CONFIG_NETFILTER_XT_MATCH_ESP=m +CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=m +CONFIG_NETFILTER_XT_MATCH_HELPER=m +CONFIG_NETFILTER_XT_MATCH_IPCOMP=m +CONFIG_NETFILTER_XT_MATCH_IPRANGE=m +CONFIG_NETFILTER_XT_MATCH_LENGTH=m +CONFIG_NETFILTER_XT_MATCH_LIMIT=m +CONFIG_NETFILTER_XT_MATCH_MAC=m +CONFIG_NETFILTER_XT_MATCH_MARK=m +CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m +CONFIG_NETFILTER_XT_MATCH_NFACCT=m +CONFIG_NETFILTER_XT_MATCH_OSF=m +CONFIG_NETFILTER_XT_MATCH_OWNER=m +CONFIG_NETFILTER_XT_MATCH_POLICY=m +CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m +CONFIG_NETFILTER_XT_MATCH_QUOTA=m +CONFIG_NETFILTER_XT_MATCH_RATEEST=m +CONFIG_NETFILTER_XT_MATCH_REALM=m +CONFIG_NETFILTER_XT_MATCH_RECENT=m +CONFIG_NETFILTER_XT_MATCH_SOCKET=m +CONFIG_NETFILTER_XT_MATCH_STATE=m +CONFIG_NETFILTER_XT_MATCH_STATISTIC=m +CONFIG_NETFILTER_XT_MATCH_STRING=m +CONFIG_NETFILTER_XT_MATCH_TCPMSS=m +CONFIG_NETFILTER_XT_MATCH_TIME=m +CONFIG_NETFILTER_XT_MATCH_U32=m +CONFIG_IP_SET=m +CONFIG_IP_SET_BITMAP_IP=m +CONFIG_IP_SET_BITMAP_IPMAC=m +CONFIG_IP_SET_BITMAP_PORT=m +CONFIG_IP_SET_HASH_IP=m +CONFIG_IP_SET_HASH_IPMARK=m +CONFIG_IP_SET_HASH_IPPORT=m +CONFIG_IP_SET_HASH_IPPORTIP=m +CONFIG_IP_SET_HASH_IPPORTNET=m +CONFIG_IP_SET_HASH_IPMAC=m +CONFIG_IP_SET_HASH_MAC=m +CONFIG_IP_SET_HASH_NETPORTNET=m +CONFIG_IP_SET_HASH_NET=m +CONFIG_IP_SET_HASH_NETNET=m +CONFIG_IP_SET_HASH_NETPORT=m +CONFIG_IP_SET_HASH_NETIFACE=m +CONFIG_IP_SET_LIST_SET=m +CONFIG_NFT_DUP_IPV4=m +CONFIG_NFT_FIB_IPV4=m +CONFIG_NF_TABLES_ARP=y +CONFIG_NF_FLOW_TABLE_IPV4=m +CONFIG_NF_LOG_ARP=m +CONFIG_IP_NF_IPTABLES=m +CONFIG_IP_NF_MATCH_AH=m +CONFIG_IP_NF_MATCH_ECN=m +CONFIG_IP_NF_MATCH_RPFILTER=m +CONFIG_IP_NF_MATCH_TTL=m +CONFIG_IP_NF_FILTER=m +CONFIG_IP_NF_TARGET_REJECT=m +CONFIG_IP_NF_TARGET_SYNPROXY=m +CONFIG_IP_NF_NAT=m +CONFIG_IP_NF_TARGET_MASQUERADE=m +CONFIG_IP_NF_TARGET_NETMAP=m +CONFIG_IP_NF_TARGET_REDIRECT=m +CONFIG_IP_NF_MANGLE=m +CONFIG_IP_NF_TARGET_CLUSTERIP=m +CONFIG_IP_NF_TARGET_ECN=m +CONFIG_IP_NF_TARGET_TTL=m +CONFIG_IP_NF_RAW=m +CONFIG_IP_NF_ARPTABLES=m +CONFIG_IP_NF_ARPFILTER=m +CONFIG_IP_NF_ARP_MANGLE=m +CONFIG_NFT_DUP_IPV6=m +CONFIG_NFT_FIB_IPV6=m +CONFIG_NF_FLOW_TABLE_IPV6=m +CONFIG_IP6_NF_IPTABLES=m +CONFIG_IP6_NF_MATCH_AH=m +CONFIG_IP6_NF_MATCH_EUI64=m +CONFIG_IP6_NF_MATCH_FRAG=m +CONFIG_IP6_NF_MATCH_OPTS=m +CONFIG_IP6_NF_MATCH_HL=m +CONFIG_IP6_NF_MATCH_IPV6HEADER=m +CONFIG_IP6_NF_MATCH_MH=m +CONFIG_IP6_NF_MATCH_RPFILTER=m +CONFIG_IP6_NF_MATCH_RT=m +CONFIG_IP6_NF_MATCH_SRH=m +CONFIG_IP6_NF_TARGET_HL=m +CONFIG_IP6_NF_FILTER=m +CONFIG_IP6_NF_TARGET_REJECT=m +CONFIG_IP6_NF_TARGET_SYNPROXY=m +CONFIG_IP6_NF_MANGLE=m +CONFIG_IP6_NF_RAW=m +CONFIG_IP6_NF_NAT=m +CONFIG_IP6_NF_TARGET_MASQUERADE=m +CONFIG_IP6_NF_TARGET_NPT=m +CONFIG_NF_TABLES_BRIDGE=m +CONFIG_NFT_BRIDGE_META=m +CONFIG_NFT_BRIDGE_REJECT=m +CONFIG_NF_LOG_BRIDGE=m +CONFIG_NF_CONNTRACK_BRIDGE=m +CONFIG_BRIDGE_NF_EBTABLES=m +CONFIG_BRIDGE_EBT_BROUTE=m +CONFIG_BRIDGE_EBT_T_FILTER=m +CONFIG_BRIDGE_EBT_T_NAT=m +CONFIG_BRIDGE_EBT_802_3=m +CONFIG_BRIDGE_EBT_AMONG=m +CONFIG_BRIDGE_EBT_ARP=m +CONFIG_BRIDGE_EBT_IP=m +CONFIG_BRIDGE_EBT_IP6=m +CONFIG_BRIDGE_EBT_LIMIT=m +CONFIG_BRIDGE_EBT_MARK=m +CONFIG_BRIDGE_EBT_PKTTYPE=m +CONFIG_BRIDGE_EBT_STP=m +CONFIG_BRIDGE_EBT_VLAN=m +CONFIG_BRIDGE_EBT_ARPREPLY=m +CONFIG_BRIDGE_EBT_DNAT=m +CONFIG_BRIDGE_EBT_MARK_T=m +CONFIG_BRIDGE_EBT_REDIRECT=m +CONFIG_BRIDGE_EBT_SNAT=m +CONFIG_BRIDGE_EBT_LOG=m +CONFIG_BRIDGE_EBT_NFLOG=m +CONFIG_IP_DCCP=m +# CONFIG_IP_DCCP_CCID3 is not set +CONFIG_SCTP_COOKIE_HMAC_SHA1=y +CONFIG_RDS=m +CONFIG_RDS_TCP=m +CONFIG_L2TP=m +CONFIG_BRIDGE=m +CONFIG_ATALK=m +CONFIG_6LOWPAN=m +CONFIG_6LOWPAN_GHC_EXT_HDR_HOP=m +CONFIG_6LOWPAN_GHC_UDP=m +CONFIG_6LOWPAN_GHC_ICMPV6=m +CONFIG_6LOWPAN_GHC_EXT_HDR_DEST=m +CONFIG_6LOWPAN_GHC_EXT_HDR_FRAG=m +CONFIG_6LOWPAN_GHC_EXT_HDR_ROUTE=m +CONFIG_DNS_RESOLVER=y +CONFIG_BATMAN_ADV=m +# CONFIG_BATMAN_ADV_BATMAN_V is not set +CONFIG_BATMAN_ADV_NC=y +CONFIG_NETLINK_DIAG=m +CONFIG_MPLS=y +CONFIG_NET_MPLS_GSO=m +CONFIG_MPLS_ROUTING=m +CONFIG_MPLS_IPTUNNEL=m +CONFIG_NET_NSH=m +CONFIG_AF_KCM=m +# CONFIG_WIRELESS is not set +CONFIG_PSAMPLE=m +CONFIG_NET_IFE=m +CONFIG_DEVTMPFS=y +CONFIG_DEVTMPFS_MOUNT=y +CONFIG_TEST_ASYNC_DRIVER_PROBE=m +CONFIG_CONNECTOR=m +CONFIG_BLK_DEV_LOOP=y +CONFIG_BLK_DEV_CRYPTOLOOP=m +CONFIG_BLK_DEV_DRBD=m +CONFIG_BLK_DEV_NBD=m +CONFIG_BLK_DEV_RAM=y +CONFIG_CDROM_PKTCDVD=m +CONFIG_ATA_OVER_ETH=m +CONFIG_DUMMY_IRQ=m +CONFIG_RAID_ATTRS=m +CONFIG_SCSI=y +CONFIG_BLK_DEV_SD=y +CONFIG_CHR_DEV_ST=m +CONFIG_BLK_DEV_SR=y +CONFIG_CHR_DEV_SG=m +CONFIG_SCSI_CONSTANTS=y +CONFIG_SCSI_SAS_ATTRS=m +CONFIG_ISCSI_TCP=m +CONFIG_ISCSI_BOOT_SYSFS=m +CONFIG_MD=y +CONFIG_MD_LINEAR=m +CONFIG_BLK_DEV_DM=m +CONFIG_DM_UNSTRIPED=m +CONFIG_DM_CRYPT=m +CONFIG_DM_SNAPSHOT=m +CONFIG_DM_THIN_PROVISIONING=m +CONFIG_DM_WRITECACHE=m +CONFIG_DM_ERA=m +CONFIG_DM_CLONE=m +CONFIG_DM_MIRROR=m +CONFIG_DM_RAID=m +CONFIG_DM_ZERO=m +CONFIG_DM_MULTIPATH=m +CONFIG_DM_UEVENT=y +CONFIG_DM_LOG_WRITES=m +CONFIG_DM_INTEGRITY=m +CONFIG_TARGET_CORE=m +CONFIG_TCM_IBLOCK=m +CONFIG_TCM_FILEIO=m +CONFIG_TCM_PSCSI=m +CONFIG_NETDEVICES=y +CONFIG_DUMMY=m +CONFIG_WIREGUARD=m +CONFIG_EQUALIZER=m +CONFIG_NET_TEAM=m +CONFIG_NET_TEAM_MODE_BROADCAST=m +CONFIG_NET_TEAM_MODE_ROUNDROBIN=m +CONFIG_NET_TEAM_MODE_RANDOM=m +CONFIG_NET_TEAM_MODE_ACTIVEBACKUP=m +CONFIG_NET_TEAM_MODE_LOADBALANCE=m +CONFIG_MACVLAN=m +CONFIG_MACVTAP=m +CONFIG_IPVLAN=m +CONFIG_IPVTAP=m +CONFIG_VXLAN=m +CONFIG_GENEVE=m +CONFIG_BAREUDP=m +CONFIG_GTP=m +CONFIG_MACSEC=m +CONFIG_NETCONSOLE=m +CONFIG_NETCONSOLE_DYNAMIC=y +CONFIG_VETH=m +CONFIG_HPLANCE=y +CONFIG_PPP=m +CONFIG_PPP_BSDCOMP=m +CONFIG_PPP_DEFLATE=m +CONFIG_PPP_FILTER=y +CONFIG_PPP_MPPE=m +CONFIG_PPPOE=m +CONFIG_PPTP=m +CONFIG_PPPOL2TP=m +CONFIG_PPP_ASYNC=m +CONFIG_PPP_SYNC_TTY=m +CONFIG_SLIP=m +CONFIG_SLIP_COMPRESSED=y +CONFIG_SLIP_SMART=y +CONFIG_SLIP_MODE_SLIP6=y +# CONFIG_WLAN is not set +CONFIG_INPUT_EVDEV=m +# CONFIG_KEYBOARD_ATKBD is not set +# CONFIG_MOUSE_PS2 is not set +CONFIG_MOUSE_SERIAL=m +CONFIG_INPUT_MISC=y +CONFIG_HP_SDC_RTC=m +CONFIG_SERIO_SERPORT=m +CONFIG_USERIO=m +# CONFIG_LEGACY_PTYS is not set +# CONFIG_HW_RANDOM is not set +CONFIG_NTP_PPS=y +CONFIG_PPS_CLIENT_LDISC=m +CONFIG_PTP_1588_CLOCK=m +# CONFIG_HWMON is not set +CONFIG_FB=y +CONFIG_FRAMEBUFFER_CONSOLE=y +CONFIG_LOGO=y +# CONFIG_LOGO_LINUX_MONO is not set +# CONFIG_LOGO_LINUX_VGA16 is not set +CONFIG_HID=m +CONFIG_HIDRAW=y +CONFIG_UHID=m +# CONFIG_HID_GENERIC is not set +# CONFIG_HID_ITE is not set +# CONFIG_HID_REDRAGON is not set +# CONFIG_USB_SUPPORT is not set +CONFIG_RTC_CLASS=y +# CONFIG_RTC_NVMEM is not set +CONFIG_RTC_DRV_GENERIC=m +# CONFIG_VIRTIO_MENU is not set +# CONFIG_VHOST_MENU is not set +# CONFIG_IOMMU_SUPPORT is not set +CONFIG_DAX=m +CONFIG_EXT4_FS=y +CONFIG_REISERFS_FS=m +CONFIG_JFS_FS=m +CONFIG_OCFS2_FS=m +# CONFIG_OCFS2_DEBUG_MASKLOG is not set +CONFIG_FANOTIFY=y +CONFIG_QUOTA_NETLINK_INTERFACE=y +# CONFIG_PRINT_QUOTA_WARNING is not set +CONFIG_AUTOFS_FS=m +CONFIG_FUSE_FS=m +CONFIG_CUSE=m +CONFIG_OVERLAY_FS=m +CONFIG_ISO9660_FS=y +CONFIG_JOLIET=y +CONFIG_ZISOFS=y +CONFIG_UDF_FS=m +CONFIG_MSDOS_FS=m +CONFIG_VFAT_FS=m +CONFIG_EXFAT_FS=m +CONFIG_PROC_KCORE=y +CONFIG_PROC_CHILDREN=y +CONFIG_TMPFS=y +CONFIG_ORANGEFS_FS=m +CONFIG_AFFS_FS=m +CONFIG_ECRYPT_FS=m +CONFIG_ECRYPT_FS_MESSAGING=y +CONFIG_HFS_FS=m +CONFIG_HFSPLUS_FS=m +CONFIG_CRAMFS=m +CONFIG_SQUASHFS=m +CONFIG_SQUASHFS_LZ4=y +CONFIG_SQUASHFS_LZO=y +CONFIG_MINIX_FS=m +CONFIG_OMFS_FS=m +CONFIG_HPFS_FS=m +CONFIG_QNX4FS_FS=m +CONFIG_QNX6FS_FS=m +CONFIG_SYSV_FS=m +CONFIG_UFS_FS=m +CONFIG_EROFS_FS=m +CONFIG_NFS_FS=y +CONFIG_NFS_V4=m +CONFIG_NFS_SWAP=y +CONFIG_ROOT_NFS=y +CONFIG_NFSD=m +CONFIG_NFSD_V3=y +CONFIG_CIFS=m +# CONFIG_CIFS_DEBUG is not set +CONFIG_CODA_FS=m +CONFIG_NLS_CODEPAGE_437=y +CONFIG_NLS_CODEPAGE_737=m +CONFIG_NLS_CODEPAGE_775=m +CONFIG_NLS_CODEPAGE_850=m +CONFIG_NLS_CODEPAGE_852=m +CONFIG_NLS_CODEPAGE_855=m +CONFIG_NLS_CODEPAGE_857=m +CONFIG_NLS_CODEPAGE_860=m +CONFIG_NLS_CODEPAGE_861=m +CONFIG_NLS_CODEPAGE_862=m +CONFIG_NLS_CODEPAGE_863=m +CONFIG_NLS_CODEPAGE_864=m +CONFIG_NLS_CODEPAGE_865=m +CONFIG_NLS_CODEPAGE_866=m +CONFIG_NLS_CODEPAGE_869=m +CONFIG_NLS_CODEPAGE_936=m +CONFIG_NLS_CODEPAGE_950=m +CONFIG_NLS_CODEPAGE_932=m +CONFIG_NLS_CODEPAGE_949=m +CONFIG_NLS_CODEPAGE_874=m +CONFIG_NLS_ISO8859_8=m +CONFIG_NLS_CODEPAGE_1250=m +CONFIG_NLS_CODEPAGE_1251=m +CONFIG_NLS_ASCII=m +CONFIG_NLS_ISO8859_1=y +CONFIG_NLS_ISO8859_2=m +CONFIG_NLS_ISO8859_3=m +CONFIG_NLS_ISO8859_4=m +CONFIG_NLS_ISO8859_5=m +CONFIG_NLS_ISO8859_6=m +CONFIG_NLS_ISO8859_7=m +CONFIG_NLS_ISO8859_9=m +CONFIG_NLS_ISO8859_13=m +CONFIG_NLS_ISO8859_14=m +CONFIG_NLS_ISO8859_15=m +CONFIG_NLS_KOI8_R=m +CONFIG_NLS_KOI8_U=m +CONFIG_NLS_MAC_ROMAN=m +CONFIG_NLS_MAC_CELTIC=m +CONFIG_NLS_MAC_CENTEURO=m +CONFIG_NLS_MAC_CROATIAN=m +CONFIG_NLS_MAC_CYRILLIC=m +CONFIG_NLS_MAC_GAELIC=m +CONFIG_NLS_MAC_GREEK=m +CONFIG_NLS_MAC_ICELAND=m +CONFIG_NLS_MAC_INUIT=m +CONFIG_NLS_MAC_ROMANIAN=m +CONFIG_NLS_MAC_TURKISH=m +CONFIG_DLM=m +CONFIG_ENCRYPTED_KEYS=m +CONFIG_HARDENED_USERCOPY=y +CONFIG_CRYPTO_MANAGER=y +CONFIG_CRYPTO_USER=m +CONFIG_CRYPTO_CRYPTD=m +CONFIG_CRYPTO_TEST=m +CONFIG_CRYPTO_RSA=m +CONFIG_CRYPTO_DH=m +CONFIG_CRYPTO_ECDH=m +CONFIG_CRYPTO_ECRDSA=m +CONFIG_CRYPTO_CURVE25519=m +CONFIG_CRYPTO_CHACHA20POLY1305=m +CONFIG_CRYPTO_AEGIS128=m +CONFIG_CRYPTO_CFB=m +CONFIG_CRYPTO_CTS=m +CONFIG_CRYPTO_LRW=m +CONFIG_CRYPTO_OFB=m +CONFIG_CRYPTO_PCBC=m +CONFIG_CRYPTO_XTS=m +CONFIG_CRYPTO_KEYWRAP=m +CONFIG_CRYPTO_ADIANTUM=m +CONFIG_CRYPTO_XCBC=m +CONFIG_CRYPTO_VMAC=m +CONFIG_CRYPTO_BLAKE2S=m +CONFIG_CRYPTO_MICHAEL_MIC=m +CONFIG_CRYPTO_RMD128=m +CONFIG_CRYPTO_RMD160=m +CONFIG_CRYPTO_RMD256=m +CONFIG_CRYPTO_RMD320=m +CONFIG_CRYPTO_SHA3=m +CONFIG_CRYPTO_SM3=m +CONFIG_CRYPTO_TGR192=m +CONFIG_CRYPTO_WP512=m +CONFIG_CRYPTO_AES=y +CONFIG_CRYPTO_AES_TI=m +CONFIG_CRYPTO_ANUBIS=m +CONFIG_CRYPTO_ARC4=m +CONFIG_CRYPTO_BLOWFISH=m +CONFIG_CRYPTO_CAMELLIA=m +CONFIG_CRYPTO_CAST5=m +CONFIG_CRYPTO_CAST6=m +CONFIG_CRYPTO_DES=m +CONFIG_CRYPTO_FCRYPT=m +CONFIG_CRYPTO_KHAZAD=m +CONFIG_CRYPTO_SALSA20=m +CONFIG_CRYPTO_SEED=m +CONFIG_CRYPTO_SERPENT=m +CONFIG_CRYPTO_SM4=m +CONFIG_CRYPTO_TEA=m +CONFIG_CRYPTO_TWOFISH=m +CONFIG_CRYPTO_LZO=m +CONFIG_CRYPTO_842=m +CONFIG_CRYPTO_LZ4=m +CONFIG_CRYPTO_LZ4HC=m +CONFIG_CRYPTO_ZSTD=m +CONFIG_CRYPTO_ANSI_CPRNG=m +CONFIG_CRYPTO_DRBG_HASH=y +CONFIG_CRYPTO_DRBG_CTR=y +CONFIG_CRYPTO_USER_API_HASH=m +CONFIG_CRYPTO_USER_API_SKCIPHER=m +CONFIG_CRYPTO_USER_API_RNG=m +CONFIG_CRYPTO_USER_API_AEAD=m +# CONFIG_CRYPTO_HW is not set +CONFIG_PRIME_NUMBERS=m +CONFIG_CRC32_SELFTEST=m +CONFIG_CRC64=m +CONFIG_XZ_DEC_TEST=m +CONFIG_STRING_SELFTEST=m +# CONFIG_SECTION_MISMATCH_WARN_ONLY is not set +CONFIG_MAGIC_SYSRQ=y +CONFIG_TEST_LOCKUP=m +CONFIG_WW_MUTEX_SELFTEST=m +CONFIG_EARLY_PRINTK=y +CONFIG_TEST_LIST_SORT=m +CONFIG_TEST_MIN_HEAP=m +CONFIG_TEST_SORT=m +CONFIG_REED_SOLOMON_TEST=m +CONFIG_ATOMIC64_SELFTEST=m +CONFIG_ASYNC_RAID6_TEST=m +CONFIG_TEST_HEXDUMP=m +CONFIG_TEST_STRING_HELPERS=m +CONFIG_TEST_STRSCPY=m +CONFIG_TEST_KSTRTOX=m +CONFIG_TEST_PRINTF=m +CONFIG_TEST_BITMAP=m +CONFIG_TEST_BITFIELD=m +CONFIG_TEST_UUID=m +CONFIG_TEST_XARRAY=m +CONFIG_TEST_OVERFLOW=m +CONFIG_TEST_RHASHTABLE=m +CONFIG_TEST_HASH=m +CONFIG_TEST_IDA=m +CONFIG_TEST_BITOPS=m +CONFIG_TEST_VMALLOC=m +CONFIG_TEST_USER_COPY=m +CONFIG_TEST_BPF=m +CONFIG_TEST_BLACKHOLE_DEV=m +CONFIG_FIND_BIT_BENCHMARK=m +CONFIG_TEST_FIRMWARE=m +CONFIG_TEST_SYSCTL=m +CONFIG_TEST_UDELAY=m +CONFIG_TEST_STATIC_KEYS=m +CONFIG_TEST_KMOD=m +CONFIG_TEST_MEMCAT_P=m +CONFIG_TEST_STACKINIT=m +CONFIG_TEST_MEMINIT=m diff --git a/arch/m68k/configs/m5208evb_defconfig b/arch/m68k/configs/m5208evb_defconfig new file mode 100644 index 000000000..0ee3079f6 --- /dev/null +++ b/arch/m68k/configs/m5208evb_defconfig @@ -0,0 +1,56 @@ +CONFIG_LOG_BUF_SHIFT=14 +CONFIG_EXPERT=y +# CONFIG_KALLSYMS is not set +# CONFIG_FUTEX is not set +# CONFIG_EPOLL is not set +# CONFIG_SIGNALFD is not set +# CONFIG_TIMERFD is not set +# CONFIG_EVENTFD is not set +# CONFIG_AIO is not set +# CONFIG_VM_EVENT_COUNTERS is not set +# CONFIG_COMPAT_BRK is not set +# CONFIG_BLK_DEV_BSG is not set +# CONFIG_MMU is not set +# CONFIG_4KSTACKS is not set +CONFIG_RAMBASE=0x40000000 +CONFIG_RAMSIZE=0x2000000 +CONFIG_VECTORBASE=0x40000000 +CONFIG_KERNELBASE=0x40020000 +CONFIG_BINFMT_FLAT=y +CONFIG_NET=y +CONFIG_PACKET=y +CONFIG_UNIX=y +CONFIG_INET=y +# CONFIG_INET_XFRM_MODE_TRANSPORT is not set +# CONFIG_INET_XFRM_MODE_TUNNEL is not set +# CONFIG_INET_XFRM_MODE_BEET is not set +# CONFIG_INET_DIAG is not set +# CONFIG_IPV6 is not set +# CONFIG_FW_LOADER is not set +CONFIG_MTD=y +CONFIG_MTD_BLOCK=y +CONFIG_MTD_RAM=y +CONFIG_MTD_UCLINUX=y +CONFIG_BLK_DEV_RAM=y +CONFIG_NETDEVICES=y +CONFIG_FEC=y +# CONFIG_INPUT is not set +# CONFIG_SERIO is not set +# CONFIG_VT is not set +# CONFIG_UNIX98_PTYS is not set +CONFIG_SERIAL_MCF=y +CONFIG_SERIAL_MCF_BAUDRATE=115200 +CONFIG_SERIAL_MCF_CONSOLE=y +# CONFIG_HW_RANDOM is not set +# CONFIG_HWMON is not set +# CONFIG_USB_SUPPORT is not set +CONFIG_EXT2_FS=y +# CONFIG_FILE_LOCKING is not set +# CONFIG_DNOTIFY is not set +# CONFIG_SYSFS is not set +CONFIG_ROMFS_FS=y +CONFIG_ROMFS_BACKED_BY_MTD=y +# CONFIG_NETWORK_FILESYSTEMS is not set +CONFIG_BOOTPARAM=y +CONFIG_BOOTPARAM_STRING="root=/dev/mtdblock0" +CONFIG_FULLDEBUG=y diff --git a/arch/m68k/configs/m5249evb_defconfig b/arch/m68k/configs/m5249evb_defconfig new file mode 100644 index 000000000..f84f68c04 --- /dev/null +++ b/arch/m68k/configs/m5249evb_defconfig @@ -0,0 +1,52 @@ +CONFIG_LOG_BUF_SHIFT=14 +CONFIG_EXPERT=y +# CONFIG_KALLSYMS is not set +# CONFIG_FUTEX is not set +# CONFIG_EPOLL is not set +# CONFIG_SIGNALFD is not set +# CONFIG_TIMERFD is not set +# CONFIG_EVENTFD is not set +# CONFIG_AIO is not set +# CONFIG_VM_EVENT_COUNTERS is not set +# CONFIG_SLUB_DEBUG is not set +# CONFIG_BLK_DEV_BSG is not set +# CONFIG_MMU is not set +CONFIG_M5249=y +CONFIG_M5249C3=y +CONFIG_RAMBASE=0x00000000 +CONFIG_RAMSIZE=0x00800000 +CONFIG_VECTORBASE=0x00000000 +CONFIG_KERNELBASE=0x00020000 +CONFIG_BINFMT_FLAT=y +CONFIG_NET=y +CONFIG_PACKET=y +CONFIG_UNIX=y +CONFIG_INET=y +# CONFIG_INET_XFRM_MODE_TRANSPORT is not set +# CONFIG_INET_XFRM_MODE_TUNNEL is not set +# CONFIG_INET_XFRM_MODE_BEET is not set +# CONFIG_INET_DIAG is not set +# CONFIG_IPV6 is not set +# CONFIG_FW_LOADER is not set +CONFIG_MTD=y +CONFIG_MTD_BLOCK=y +CONFIG_MTD_RAM=y +CONFIG_MTD_UCLINUX=y +CONFIG_BLK_DEV_RAM=y +CONFIG_NETDEVICES=y +CONFIG_PPP=y +# CONFIG_INPUT is not set +# CONFIG_SERIO is not set +# CONFIG_VT is not set +# CONFIG_UNIX98_PTYS is not set +CONFIG_SERIAL_MCF=y +CONFIG_SERIAL_MCF_CONSOLE=y +# CONFIG_HWMON is not set +# CONFIG_USB_SUPPORT is not set +CONFIG_EXT2_FS=y +# CONFIG_FILE_LOCKING is not set +CONFIG_ROMFS_FS=y +CONFIG_ROMFS_BACKED_BY_MTD=y +# CONFIG_NETWORK_FILESYSTEMS is not set +CONFIG_BOOTPARAM=y +CONFIG_BOOTPARAM_STRING="root=/dev/mtdblock0" diff --git a/arch/m68k/configs/m5272c3_defconfig b/arch/m68k/configs/m5272c3_defconfig new file mode 100644 index 000000000..eca65020a --- /dev/null +++ b/arch/m68k/configs/m5272c3_defconfig @@ -0,0 +1,53 @@ +CONFIG_LOG_BUF_SHIFT=14 +CONFIG_EXPERT=y +# CONFIG_KALLSYMS is not set +# CONFIG_FUTEX is not set +# CONFIG_EPOLL is not set +# CONFIG_SIGNALFD is not set +# CONFIG_TIMERFD is not set +# CONFIG_EVENTFD is not set +# CONFIG_AIO is not set +# CONFIG_VM_EVENT_COUNTERS is not set +# CONFIG_SLUB_DEBUG is not set +# CONFIG_BLK_DEV_BSG is not set +# CONFIG_MMU is not set +CONFIG_M5272=y +CONFIG_M5272C3=y +CONFIG_RAMBASE=0x00000000 +CONFIG_RAMSIZE=0x00800000 +CONFIG_VECTORBASE=0x00000000 +CONFIG_KERNELBASE=0x00020000 +CONFIG_BINFMT_FLAT=y +CONFIG_NET=y +CONFIG_PACKET=y +CONFIG_UNIX=y +CONFIG_INET=y +# CONFIG_INET_XFRM_MODE_TRANSPORT is not set +# CONFIG_INET_XFRM_MODE_TUNNEL is not set +# CONFIG_INET_XFRM_MODE_BEET is not set +# CONFIG_INET_DIAG is not set +# CONFIG_IPV6 is not set +# CONFIG_FW_LOADER is not set +CONFIG_MTD=y +CONFIG_MTD_BLOCK=y +CONFIG_MTD_RAM=y +CONFIG_MTD_UCLINUX=y +CONFIG_BLK_DEV_RAM=y +CONFIG_NETDEVICES=y +CONFIG_FEC=y +# CONFIG_INPUT is not set +# CONFIG_SERIO is not set +# CONFIG_VT is not set +# CONFIG_UNIX98_PTYS is not set +CONFIG_SERIAL_MCF=y +CONFIG_SERIAL_MCF_CONSOLE=y +# CONFIG_HWMON is not set +# CONFIG_USB_SUPPORT is not set +CONFIG_EXT2_FS=y +# CONFIG_FILE_LOCKING is not set +# CONFIG_DNOTIFY is not set +CONFIG_ROMFS_FS=y +CONFIG_ROMFS_BACKED_BY_MTD=y +# CONFIG_NETWORK_FILESYSTEMS is not set +CONFIG_BOOTPARAM=y +CONFIG_BOOTPARAM_STRING="root=/dev/mtdblock0" diff --git a/arch/m68k/configs/m5275evb_defconfig b/arch/m68k/configs/m5275evb_defconfig new file mode 100644 index 000000000..9402c7a3e --- /dev/null +++ b/arch/m68k/configs/m5275evb_defconfig @@ -0,0 +1,54 @@ +CONFIG_LOG_BUF_SHIFT=14 +CONFIG_EXPERT=y +# CONFIG_KALLSYMS is not set +# CONFIG_FUTEX is not set +# CONFIG_EPOLL is not set +# CONFIG_SIGNALFD is not set +# CONFIG_TIMERFD is not set +# CONFIG_EVENTFD is not set +# CONFIG_AIO is not set +# CONFIG_VM_EVENT_COUNTERS is not set +# CONFIG_SLUB_DEBUG is not set +# CONFIG_BLK_DEV_BSG is not set +# CONFIG_MMU is not set +CONFIG_M5275=y +# CONFIG_4KSTACKS is not set +CONFIG_RAMBASE=0x00000000 +CONFIG_RAMSIZE=0x00000000 +CONFIG_VECTORBASE=0x00000000 +CONFIG_KERNELBASE=0x00020000 +CONFIG_BINFMT_FLAT=y +CONFIG_NET=y +CONFIG_PACKET=y +CONFIG_UNIX=y +CONFIG_INET=y +# CONFIG_INET_XFRM_MODE_TRANSPORT is not set +# CONFIG_INET_XFRM_MODE_TUNNEL is not set +# CONFIG_INET_XFRM_MODE_BEET is not set +# CONFIG_INET_DIAG is not set +# CONFIG_IPV6 is not set +# CONFIG_FW_LOADER is not set +CONFIG_MTD=y +CONFIG_MTD_BLOCK=y +CONFIG_MTD_RAM=y +CONFIG_MTD_UCLINUX=y +CONFIG_BLK_DEV_RAM=y +CONFIG_NETDEVICES=y +CONFIG_FEC=y +CONFIG_PPP=y +# CONFIG_INPUT is not set +# CONFIG_SERIO is not set +# CONFIG_VT is not set +# CONFIG_UNIX98_PTYS is not set +CONFIG_SERIAL_MCF=y +CONFIG_SERIAL_MCF_CONSOLE=y +# CONFIG_HWMON is not set +# CONFIG_USB_SUPPORT is not set +CONFIG_EXT2_FS=y +# CONFIG_FILE_LOCKING is not set +# CONFIG_DNOTIFY is not set +CONFIG_ROMFS_FS=y +CONFIG_ROMFS_BACKED_BY_MTD=y +# CONFIG_NETWORK_FILESYSTEMS is not set +CONFIG_BOOTPARAM=y +CONFIG_BOOTPARAM_STRING="root=/dev/mtdblock0" diff --git a/arch/m68k/configs/m5307c3_defconfig b/arch/m68k/configs/m5307c3_defconfig new file mode 100644 index 000000000..bb8b0eb4b --- /dev/null +++ b/arch/m68k/configs/m5307c3_defconfig @@ -0,0 +1,58 @@ +CONFIG_LOG_BUF_SHIFT=14 +CONFIG_EXPERT=y +# CONFIG_KALLSYMS is not set +# CONFIG_FUTEX is not set +# CONFIG_EPOLL is not set +# CONFIG_SIGNALFD is not set +# CONFIG_TIMERFD is not set +# CONFIG_EVENTFD is not set +# CONFIG_AIO is not set +# CONFIG_VM_EVENT_COUNTERS is not set +# CONFIG_SLUB_DEBUG is not set +# CONFIG_BLK_DEV_BSG is not set +# CONFIG_MMU is not set +CONFIG_M5307=y +CONFIG_M5307C3=y +CONFIG_RAMBASE=0x00000000 +CONFIG_RAMSIZE=0x00800000 +CONFIG_VECTORBASE=0x00000000 +CONFIG_KERNELBASE=0x00020000 +CONFIG_BINFMT_FLAT=y +CONFIG_NET=y +CONFIG_PACKET=y +CONFIG_UNIX=y +CONFIG_INET=y +# CONFIG_INET_XFRM_MODE_TRANSPORT is not set +# CONFIG_INET_XFRM_MODE_TUNNEL is not set +# CONFIG_INET_XFRM_MODE_BEET is not set +# CONFIG_INET_DIAG is not set +# CONFIG_IPV6 is not set +# CONFIG_FW_LOADER is not set +CONFIG_MTD=y +CONFIG_MTD_BLOCK=y +CONFIG_MTD_RAM=y +CONFIG_MTD_UCLINUX=y +CONFIG_BLK_DEV_RAM=y +CONFIG_NETDEVICES=y +CONFIG_PPP=y +CONFIG_SLIP=y +CONFIG_SLIP_COMPRESSED=y +# CONFIG_INPUT_MOUSEDEV is not set +# CONFIG_INPUT_KEYBOARD is not set +# CONFIG_INPUT_MOUSE is not set +# CONFIG_SERIO is not set +# CONFIG_VT is not set +# CONFIG_LEGACY_PTYS is not set +CONFIG_SERIAL_MCF=y +CONFIG_SERIAL_MCF_CONSOLE=y +# CONFIG_HW_RANDOM is not set +# CONFIG_HWMON is not set +# CONFIG_USB_SUPPORT is not set +CONFIG_EXT2_FS=y +# CONFIG_DNOTIFY is not set +CONFIG_ROMFS_FS=y +CONFIG_ROMFS_BACKED_BY_MTD=y +# CONFIG_NETWORK_FILESYSTEMS is not set +CONFIG_BOOTPARAM=y +CONFIG_BOOTPARAM_STRING="root=/dev/mtdblock0" +CONFIG_FULLDEBUG=y diff --git a/arch/m68k/configs/m5407c3_defconfig b/arch/m68k/configs/m5407c3_defconfig new file mode 100644 index 000000000..ce9ccf13c --- /dev/null +++ b/arch/m68k/configs/m5407c3_defconfig @@ -0,0 +1,54 @@ +CONFIG_LOG_BUF_SHIFT=14 +CONFIG_EXPERT=y +# CONFIG_KALLSYMS is not set +# CONFIG_FUTEX is not set +# CONFIG_EPOLL is not set +# CONFIG_SIGNALFD is not set +# CONFIG_TIMERFD is not set +# CONFIG_EVENTFD is not set +# CONFIG_AIO is not set +# CONFIG_VM_EVENT_COUNTERS is not set +CONFIG_MODULES=y +CONFIG_MODULE_UNLOAD=y +# CONFIG_BLK_DEV_BSG is not set +# CONFIG_MMU is not set +CONFIG_M5407=y +CONFIG_M5407C3=y +CONFIG_RAMBASE=0x00000000 +CONFIG_RAMSIZE=0x00000000 +CONFIG_VECTORBASE=0x00000000 +CONFIG_KERNELBASE=0x00020000 +CONFIG_BINFMT_FLAT=y +CONFIG_NET=y +CONFIG_PACKET=y +CONFIG_UNIX=y +CONFIG_INET=y +# CONFIG_INET_XFRM_MODE_TRANSPORT is not set +# CONFIG_INET_XFRM_MODE_TUNNEL is not set +# CONFIG_INET_XFRM_MODE_BEET is not set +# CONFIG_INET_DIAG is not set +# CONFIG_IPV6 is not set +# CONFIG_FW_LOADER is not set +CONFIG_MTD=y +CONFIG_MTD_BLOCK=y +CONFIG_MTD_RAM=y +CONFIG_MTD_UCLINUX=y +CONFIG_BLK_DEV_RAM=y +CONFIG_NETDEVICES=y +CONFIG_PPP=y +# CONFIG_INPUT is not set +# CONFIG_VT is not set +# CONFIG_UNIX98_PTYS is not set +CONFIG_SERIAL_MCF=y +CONFIG_SERIAL_MCF_CONSOLE=y +# CONFIG_HW_RANDOM is not set +# CONFIG_HWMON is not set +# CONFIG_USB_SUPPORT is not set +CONFIG_EXT2_FS=y +# CONFIG_FILE_LOCKING is not set +# CONFIG_DNOTIFY is not set +CONFIG_ROMFS_FS=y +CONFIG_ROMFS_BACKED_BY_MTD=y +# CONFIG_NETWORK_FILESYSTEMS is not set +CONFIG_BOOTPARAM=y +CONFIG_BOOTPARAM_STRING="root=/dev/mtdblock0" diff --git a/arch/m68k/configs/m5475evb_defconfig b/arch/m68k/configs/m5475evb_defconfig new file mode 100644 index 000000000..93f7c7a07 --- /dev/null +++ b/arch/m68k/configs/m5475evb_defconfig @@ -0,0 +1,51 @@ +# CONFIG_SWAP is not set +CONFIG_LOG_BUF_SHIFT=14 +# CONFIG_KALLSYMS is not set +# CONFIG_FUTEX is not set +# CONFIG_EPOLL is not set +# CONFIG_SIGNALFD is not set +# CONFIG_TIMERFD is not set +# CONFIG_EVENTFD is not set +# CONFIG_SHMEM is not set +# CONFIG_AIO is not set +CONFIG_EMBEDDED=y +CONFIG_MODULES=y +# CONFIG_BLK_DEV_BSG is not set +CONFIG_COLDFIRE=y +# CONFIG_4KSTACKS is not set +CONFIG_RAMBASE=0x0 +CONFIG_RAMSIZE=0x2000000 +CONFIG_VECTORBASE=0x0 +CONFIG_MBAR=0xff000000 +CONFIG_KERNELBASE=0x20000 +CONFIG_PCI=y +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +# CONFIG_FW_LOADER is not set +CONFIG_MTD=y +CONFIG_MTD_BLOCK=y +CONFIG_MTD_CFI=y +CONFIG_MTD_JEDECPROBE=y +CONFIG_MTD_CFI_AMDSTD=y +CONFIG_MTD_RAM=y +CONFIG_MTD_PHYSMAP=y +CONFIG_MTD_UCLINUX=y +CONFIG_BLK_DEV_RAM=y +# CONFIG_INPUT is not set +# CONFIG_VT is not set +# CONFIG_UNIX98_PTYS is not set +CONFIG_SERIAL_MCF=y +CONFIG_SERIAL_MCF_CONSOLE=y +# CONFIG_HW_RANDOM is not set +# CONFIG_HWMON is not set +# CONFIG_USB_SUPPORT is not set +# CONFIG_IOMMU_SUPPORT is not set +CONFIG_EXT2_FS=y +# CONFIG_FILE_LOCKING is not set +# CONFIG_DNOTIFY is not set +# CONFIG_INOTIFY_USER is not set +# CONFIG_PROC_PAGE_MONITOR is not set +CONFIG_ROMFS_FS=y +CONFIG_ROMFS_BACKED_BY_MTD=y +# CONFIG_SCHED_DEBUG is not set +CONFIG_BOOTPARAM=y +CONFIG_BOOTPARAM_STRING="root=/dev/mtdblock0" diff --git a/arch/m68k/configs/mac_defconfig b/arch/m68k/configs/mac_defconfig new file mode 100644 index 000000000..3cd76bfae --- /dev/null +++ b/arch/m68k/configs/mac_defconfig @@ -0,0 +1,642 @@ +CONFIG_LOCALVERSION="-mac" +CONFIG_SYSVIPC=y +CONFIG_POSIX_MQUEUE=y +CONFIG_BSD_PROCESS_ACCT=y +CONFIG_BSD_PROCESS_ACCT_V3=y +CONFIG_LOG_BUF_SHIFT=16 +# CONFIG_UTS_NS is not set +# CONFIG_IPC_NS is not set +# CONFIG_PID_NS is not set +# CONFIG_NET_NS is not set +CONFIG_BLK_DEV_INITRD=y +CONFIG_CC_OPTIMIZE_FOR_SIZE=y +CONFIG_USERFAULTFD=y +CONFIG_SLAB=y +CONFIG_KEXEC=y +CONFIG_BOOTINFO_PROC=y +CONFIG_M68020=y +CONFIG_M68030=y +CONFIG_M68040=y +CONFIG_M68KFPU_EMU=y +CONFIG_MAC=y +CONFIG_PROC_HARDWARE=y +CONFIG_MODULES=y +CONFIG_MODULE_UNLOAD=y +CONFIG_PARTITION_ADVANCED=y +CONFIG_AMIGA_PARTITION=y +CONFIG_ATARI_PARTITION=y +CONFIG_BSD_DISKLABEL=y +CONFIG_MINIX_SUBPARTITION=y +CONFIG_SOLARIS_X86_PARTITION=y +CONFIG_UNIXWARE_DISKLABEL=y +CONFIG_SUN_PARTITION=y +# CONFIG_EFI_PARTITION is not set +CONFIG_SYSV68_PARTITION=y +CONFIG_MQ_IOSCHED_DEADLINE=m +CONFIG_MQ_IOSCHED_KYBER=m +CONFIG_IOSCHED_BFQ=m +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +CONFIG_BINFMT_AOUT=m +CONFIG_BINFMT_MISC=m +# CONFIG_COMPACTION is not set +CONFIG_CLEANCACHE=y +CONFIG_ZPOOL=m +CONFIG_NET=y +CONFIG_PACKET=y +CONFIG_PACKET_DIAG=m +CONFIG_UNIX=y +CONFIG_UNIX_DIAG=m +CONFIG_TLS=m +CONFIG_XFRM_MIGRATE=y +CONFIG_NET_KEY=y +CONFIG_XDP_SOCKETS=y +CONFIG_XDP_SOCKETS_DIAG=m +CONFIG_INET=y +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +CONFIG_IP_PNP_BOOTP=y +CONFIG_IP_PNP_RARP=y +CONFIG_NET_IPIP=m +CONFIG_NET_IPGRE_DEMUX=m +CONFIG_NET_IPGRE=m +CONFIG_NET_IPVTI=m +CONFIG_NET_FOU_IP_TUNNELS=y +CONFIG_INET_AH=m +CONFIG_INET_ESP=m +CONFIG_INET_ESP_OFFLOAD=m +CONFIG_INET_IPCOMP=m +CONFIG_INET_DIAG=m +CONFIG_INET_UDP_DIAG=m +CONFIG_INET_RAW_DIAG=m +CONFIG_IPV6=m +CONFIG_IPV6_ROUTER_PREF=y +CONFIG_INET6_AH=m +CONFIG_INET6_ESP=m +CONFIG_INET6_ESP_OFFLOAD=m +CONFIG_INET6_IPCOMP=m +CONFIG_IPV6_ILA=m +CONFIG_IPV6_VTI=m +CONFIG_IPV6_GRE=m +CONFIG_NETFILTER=y +CONFIG_NF_CONNTRACK=m +CONFIG_NF_LOG_NETDEV=m +CONFIG_NF_CONNTRACK_ZONES=y +# CONFIG_NF_CONNTRACK_PROCFS is not set +# CONFIG_NF_CT_PROTO_DCCP is not set +CONFIG_NF_CONNTRACK_AMANDA=m +CONFIG_NF_CONNTRACK_FTP=m +CONFIG_NF_CONNTRACK_H323=m +CONFIG_NF_CONNTRACK_IRC=m +CONFIG_NF_CONNTRACK_NETBIOS_NS=m +CONFIG_NF_CONNTRACK_SNMP=m +CONFIG_NF_CONNTRACK_PPTP=m +CONFIG_NF_CONNTRACK_SANE=m +CONFIG_NF_CONNTRACK_SIP=m +CONFIG_NF_CONNTRACK_TFTP=m +CONFIG_NF_TABLES=m +CONFIG_NF_TABLES_INET=y +CONFIG_NF_TABLES_NETDEV=y +CONFIG_NFT_NUMGEN=m +CONFIG_NFT_CT=m +CONFIG_NFT_FLOW_OFFLOAD=m +CONFIG_NFT_COUNTER=m +CONFIG_NFT_CONNLIMIT=m +CONFIG_NFT_LOG=m +CONFIG_NFT_LIMIT=m +CONFIG_NFT_MASQ=m +CONFIG_NFT_REDIR=m +CONFIG_NFT_NAT=m +CONFIG_NFT_TUNNEL=m +CONFIG_NFT_OBJREF=m +CONFIG_NFT_QUEUE=m +CONFIG_NFT_QUOTA=m +CONFIG_NFT_REJECT=m +CONFIG_NFT_COMPAT=m +CONFIG_NFT_HASH=m +CONFIG_NFT_FIB_INET=m +CONFIG_NFT_XFRM=m +CONFIG_NFT_SOCKET=m +CONFIG_NFT_OSF=m +CONFIG_NFT_TPROXY=m +CONFIG_NFT_SYNPROXY=m +CONFIG_NFT_DUP_NETDEV=m +CONFIG_NFT_FWD_NETDEV=m +CONFIG_NFT_FIB_NETDEV=m +CONFIG_NF_FLOW_TABLE_INET=m +CONFIG_NF_FLOW_TABLE=m +CONFIG_NETFILTER_XT_SET=m +CONFIG_NETFILTER_XT_TARGET_CHECKSUM=m +CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m +CONFIG_NETFILTER_XT_TARGET_CONNMARK=m +CONFIG_NETFILTER_XT_TARGET_DSCP=m +CONFIG_NETFILTER_XT_TARGET_HMARK=m +CONFIG_NETFILTER_XT_TARGET_IDLETIMER=m +CONFIG_NETFILTER_XT_TARGET_LOG=m +CONFIG_NETFILTER_XT_TARGET_MARK=m +CONFIG_NETFILTER_XT_TARGET_NFLOG=m +CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m +CONFIG_NETFILTER_XT_TARGET_NOTRACK=m +CONFIG_NETFILTER_XT_TARGET_TEE=m +CONFIG_NETFILTER_XT_TARGET_TPROXY=m +CONFIG_NETFILTER_XT_TARGET_TRACE=m +CONFIG_NETFILTER_XT_TARGET_TCPMSS=m +CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP=m +CONFIG_NETFILTER_XT_MATCH_ADDRTYPE=m +CONFIG_NETFILTER_XT_MATCH_BPF=m +CONFIG_NETFILTER_XT_MATCH_CLUSTER=m +CONFIG_NETFILTER_XT_MATCH_COMMENT=m +CONFIG_NETFILTER_XT_MATCH_CONNBYTES=m +CONFIG_NETFILTER_XT_MATCH_CONNLABEL=m +CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=m +CONFIG_NETFILTER_XT_MATCH_CONNMARK=m +CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m +CONFIG_NETFILTER_XT_MATCH_DEVGROUP=m +CONFIG_NETFILTER_XT_MATCH_DSCP=m +CONFIG_NETFILTER_XT_MATCH_ESP=m +CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=m +CONFIG_NETFILTER_XT_MATCH_HELPER=m +CONFIG_NETFILTER_XT_MATCH_IPCOMP=m +CONFIG_NETFILTER_XT_MATCH_IPRANGE=m +CONFIG_NETFILTER_XT_MATCH_LENGTH=m +CONFIG_NETFILTER_XT_MATCH_LIMIT=m +CONFIG_NETFILTER_XT_MATCH_MAC=m +CONFIG_NETFILTER_XT_MATCH_MARK=m +CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m +CONFIG_NETFILTER_XT_MATCH_NFACCT=m +CONFIG_NETFILTER_XT_MATCH_OSF=m +CONFIG_NETFILTER_XT_MATCH_OWNER=m +CONFIG_NETFILTER_XT_MATCH_POLICY=m +CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m +CONFIG_NETFILTER_XT_MATCH_QUOTA=m +CONFIG_NETFILTER_XT_MATCH_RATEEST=m +CONFIG_NETFILTER_XT_MATCH_REALM=m +CONFIG_NETFILTER_XT_MATCH_RECENT=m +CONFIG_NETFILTER_XT_MATCH_SOCKET=m +CONFIG_NETFILTER_XT_MATCH_STATE=m +CONFIG_NETFILTER_XT_MATCH_STATISTIC=m +CONFIG_NETFILTER_XT_MATCH_STRING=m +CONFIG_NETFILTER_XT_MATCH_TCPMSS=m +CONFIG_NETFILTER_XT_MATCH_TIME=m +CONFIG_NETFILTER_XT_MATCH_U32=m +CONFIG_IP_SET=m +CONFIG_IP_SET_BITMAP_IP=m +CONFIG_IP_SET_BITMAP_IPMAC=m +CONFIG_IP_SET_BITMAP_PORT=m +CONFIG_IP_SET_HASH_IP=m +CONFIG_IP_SET_HASH_IPMARK=m +CONFIG_IP_SET_HASH_IPPORT=m +CONFIG_IP_SET_HASH_IPPORTIP=m +CONFIG_IP_SET_HASH_IPPORTNET=m +CONFIG_IP_SET_HASH_IPMAC=m +CONFIG_IP_SET_HASH_MAC=m +CONFIG_IP_SET_HASH_NETPORTNET=m +CONFIG_IP_SET_HASH_NET=m +CONFIG_IP_SET_HASH_NETNET=m +CONFIG_IP_SET_HASH_NETPORT=m +CONFIG_IP_SET_HASH_NETIFACE=m +CONFIG_IP_SET_LIST_SET=m +CONFIG_NFT_DUP_IPV4=m +CONFIG_NFT_FIB_IPV4=m +CONFIG_NF_TABLES_ARP=y +CONFIG_NF_FLOW_TABLE_IPV4=m +CONFIG_NF_LOG_ARP=m +CONFIG_IP_NF_IPTABLES=m +CONFIG_IP_NF_MATCH_AH=m +CONFIG_IP_NF_MATCH_ECN=m +CONFIG_IP_NF_MATCH_RPFILTER=m +CONFIG_IP_NF_MATCH_TTL=m +CONFIG_IP_NF_FILTER=m +CONFIG_IP_NF_TARGET_REJECT=m +CONFIG_IP_NF_TARGET_SYNPROXY=m +CONFIG_IP_NF_NAT=m +CONFIG_IP_NF_TARGET_MASQUERADE=m +CONFIG_IP_NF_TARGET_NETMAP=m +CONFIG_IP_NF_TARGET_REDIRECT=m +CONFIG_IP_NF_MANGLE=m +CONFIG_IP_NF_TARGET_CLUSTERIP=m +CONFIG_IP_NF_TARGET_ECN=m +CONFIG_IP_NF_TARGET_TTL=m +CONFIG_IP_NF_RAW=m +CONFIG_IP_NF_ARPTABLES=m +CONFIG_IP_NF_ARPFILTER=m +CONFIG_IP_NF_ARP_MANGLE=m +CONFIG_NFT_DUP_IPV6=m +CONFIG_NFT_FIB_IPV6=m +CONFIG_NF_FLOW_TABLE_IPV6=m +CONFIG_IP6_NF_IPTABLES=m +CONFIG_IP6_NF_MATCH_AH=m +CONFIG_IP6_NF_MATCH_EUI64=m +CONFIG_IP6_NF_MATCH_FRAG=m +CONFIG_IP6_NF_MATCH_OPTS=m +CONFIG_IP6_NF_MATCH_HL=m +CONFIG_IP6_NF_MATCH_IPV6HEADER=m +CONFIG_IP6_NF_MATCH_MH=m +CONFIG_IP6_NF_MATCH_RPFILTER=m +CONFIG_IP6_NF_MATCH_RT=m +CONFIG_IP6_NF_MATCH_SRH=m +CONFIG_IP6_NF_TARGET_HL=m +CONFIG_IP6_NF_FILTER=m +CONFIG_IP6_NF_TARGET_REJECT=m +CONFIG_IP6_NF_TARGET_SYNPROXY=m +CONFIG_IP6_NF_MANGLE=m +CONFIG_IP6_NF_RAW=m +CONFIG_IP6_NF_NAT=m +CONFIG_IP6_NF_TARGET_MASQUERADE=m +CONFIG_IP6_NF_TARGET_NPT=m +CONFIG_NF_TABLES_BRIDGE=m +CONFIG_NFT_BRIDGE_META=m +CONFIG_NFT_BRIDGE_REJECT=m +CONFIG_NF_LOG_BRIDGE=m +CONFIG_NF_CONNTRACK_BRIDGE=m +CONFIG_BRIDGE_NF_EBTABLES=m +CONFIG_BRIDGE_EBT_BROUTE=m +CONFIG_BRIDGE_EBT_T_FILTER=m +CONFIG_BRIDGE_EBT_T_NAT=m +CONFIG_BRIDGE_EBT_802_3=m +CONFIG_BRIDGE_EBT_AMONG=m +CONFIG_BRIDGE_EBT_ARP=m +CONFIG_BRIDGE_EBT_IP=m +CONFIG_BRIDGE_EBT_IP6=m +CONFIG_BRIDGE_EBT_LIMIT=m +CONFIG_BRIDGE_EBT_MARK=m +CONFIG_BRIDGE_EBT_PKTTYPE=m +CONFIG_BRIDGE_EBT_STP=m +CONFIG_BRIDGE_EBT_VLAN=m +CONFIG_BRIDGE_EBT_ARPREPLY=m +CONFIG_BRIDGE_EBT_DNAT=m +CONFIG_BRIDGE_EBT_MARK_T=m +CONFIG_BRIDGE_EBT_REDIRECT=m +CONFIG_BRIDGE_EBT_SNAT=m +CONFIG_BRIDGE_EBT_LOG=m +CONFIG_BRIDGE_EBT_NFLOG=m +CONFIG_IP_DCCP=m +# CONFIG_IP_DCCP_CCID3 is not set +CONFIG_SCTP_COOKIE_HMAC_SHA1=y +CONFIG_RDS=m +CONFIG_RDS_TCP=m +CONFIG_L2TP=m +CONFIG_BRIDGE=m +CONFIG_ATALK=m +CONFIG_DEV_APPLETALK=m +CONFIG_IPDDP=m +CONFIG_IPDDP_ENCAP=y +CONFIG_6LOWPAN=m +CONFIG_6LOWPAN_GHC_EXT_HDR_HOP=m +CONFIG_6LOWPAN_GHC_UDP=m +CONFIG_6LOWPAN_GHC_ICMPV6=m +CONFIG_6LOWPAN_GHC_EXT_HDR_DEST=m +CONFIG_6LOWPAN_GHC_EXT_HDR_FRAG=m +CONFIG_6LOWPAN_GHC_EXT_HDR_ROUTE=m +CONFIG_DNS_RESOLVER=y +CONFIG_BATMAN_ADV=m +# CONFIG_BATMAN_ADV_BATMAN_V is not set +CONFIG_BATMAN_ADV_NC=y +CONFIG_NETLINK_DIAG=m +CONFIG_MPLS=y +CONFIG_NET_MPLS_GSO=m +CONFIG_MPLS_ROUTING=m +CONFIG_MPLS_IPTUNNEL=m +CONFIG_NET_NSH=m +CONFIG_AF_KCM=m +# CONFIG_WIRELESS is not set +CONFIG_PSAMPLE=m +CONFIG_NET_IFE=m +CONFIG_DEVTMPFS=y +CONFIG_DEVTMPFS_MOUNT=y +CONFIG_TEST_ASYNC_DRIVER_PROBE=m +CONFIG_CONNECTOR=m +CONFIG_BLK_DEV_SWIM=m +CONFIG_BLK_DEV_LOOP=y +CONFIG_BLK_DEV_CRYPTOLOOP=m +CONFIG_BLK_DEV_DRBD=m +CONFIG_BLK_DEV_NBD=m +CONFIG_BLK_DEV_RAM=y +CONFIG_CDROM_PKTCDVD=m +CONFIG_ATA_OVER_ETH=m +CONFIG_DUMMY_IRQ=m +CONFIG_IDE=y +CONFIG_IDE_GD_ATAPI=y +CONFIG_BLK_DEV_IDECD=y +CONFIG_BLK_DEV_PLATFORM=y +CONFIG_BLK_DEV_MAC_IDE=y +CONFIG_RAID_ATTRS=m +CONFIG_SCSI=y +CONFIG_BLK_DEV_SD=y +CONFIG_CHR_DEV_ST=m +CONFIG_BLK_DEV_SR=y +CONFIG_CHR_DEV_SG=m +CONFIG_SCSI_CONSTANTS=y +CONFIG_SCSI_SAS_ATTRS=m +CONFIG_ISCSI_TCP=m +CONFIG_ISCSI_BOOT_SYSFS=m +CONFIG_MAC_SCSI=y +CONFIG_SCSI_MAC_ESP=y +CONFIG_MD=y +CONFIG_MD_LINEAR=m +CONFIG_BLK_DEV_DM=m +CONFIG_DM_UNSTRIPED=m +CONFIG_DM_CRYPT=m +CONFIG_DM_SNAPSHOT=m +CONFIG_DM_THIN_PROVISIONING=m +CONFIG_DM_WRITECACHE=m +CONFIG_DM_ERA=m +CONFIG_DM_CLONE=m +CONFIG_DM_MIRROR=m +CONFIG_DM_RAID=m +CONFIG_DM_ZERO=m +CONFIG_DM_MULTIPATH=m +CONFIG_DM_UEVENT=y +CONFIG_DM_LOG_WRITES=m +CONFIG_DM_INTEGRITY=m +CONFIG_TARGET_CORE=m +CONFIG_TCM_IBLOCK=m +CONFIG_TCM_FILEIO=m +CONFIG_TCM_PSCSI=m +CONFIG_ADB=y +CONFIG_ADB_MACII=y +CONFIG_ADB_IOP=y +CONFIG_ADB_CUDA=y +CONFIG_ADB_PMU=y +CONFIG_INPUT_ADBHID=y +CONFIG_MAC_EMUMOUSEBTN=y +CONFIG_NETDEVICES=y +CONFIG_DUMMY=m +CONFIG_WIREGUARD=m +CONFIG_EQUALIZER=m +CONFIG_NET_TEAM=m +CONFIG_NET_TEAM_MODE_BROADCAST=m +CONFIG_NET_TEAM_MODE_ROUNDROBIN=m +CONFIG_NET_TEAM_MODE_RANDOM=m +CONFIG_NET_TEAM_MODE_ACTIVEBACKUP=m +CONFIG_NET_TEAM_MODE_LOADBALANCE=m +CONFIG_MACVLAN=m +CONFIG_MACVTAP=m +CONFIG_IPVLAN=m +CONFIG_IPVTAP=m +CONFIG_VXLAN=m +CONFIG_GENEVE=m +CONFIG_BAREUDP=m +CONFIG_GTP=m +CONFIG_MACSEC=m +CONFIG_NETCONSOLE=m +CONFIG_NETCONSOLE_DYNAMIC=y +CONFIG_VETH=m +CONFIG_MACMACE=y +CONFIG_MAC89x0=y +CONFIG_MACSONIC=y +CONFIG_MAC8390=y +CONFIG_PPP=m +CONFIG_PPP_BSDCOMP=m +CONFIG_PPP_DEFLATE=m +CONFIG_PPP_FILTER=y +CONFIG_PPP_MPPE=m +CONFIG_PPPOE=m +CONFIG_PPTP=m +CONFIG_PPPOL2TP=m +CONFIG_PPP_ASYNC=m +CONFIG_PPP_SYNC_TTY=m +CONFIG_SLIP=m +CONFIG_SLIP_COMPRESSED=y +CONFIG_SLIP_SMART=y +CONFIG_SLIP_MODE_SLIP6=y +# CONFIG_WLAN is not set +CONFIG_INPUT_EVDEV=m +# CONFIG_KEYBOARD_ATKBD is not set +# CONFIG_MOUSE_PS2 is not set +CONFIG_MOUSE_SERIAL=m +CONFIG_INPUT_MISC=y +CONFIG_INPUT_M68K_BEEP=m +CONFIG_SERIO=m +CONFIG_USERIO=m +# CONFIG_LEGACY_PTYS is not set +CONFIG_SERIAL_PMACZILOG=y +CONFIG_SERIAL_PMACZILOG_TTYS=y +CONFIG_SERIAL_PMACZILOG_CONSOLE=y +# CONFIG_HW_RANDOM is not set +CONFIG_NTP_PPS=y +CONFIG_PPS_CLIENT_LDISC=m +CONFIG_PTP_1588_CLOCK=m +# CONFIG_HWMON is not set +CONFIG_FB=y +CONFIG_FB_VALKYRIE=y +CONFIG_FB_MAC=y +CONFIG_FRAMEBUFFER_CONSOLE=y +CONFIG_LOGO=y +CONFIG_HID=m +CONFIG_HIDRAW=y +CONFIG_UHID=m +# CONFIG_HID_GENERIC is not set +# CONFIG_HID_ITE is not set +# CONFIG_HID_REDRAGON is not set +# CONFIG_USB_SUPPORT is not set +CONFIG_RTC_CLASS=y +# CONFIG_RTC_NVMEM is not set +CONFIG_RTC_DRV_GENERIC=m +# CONFIG_VIRTIO_MENU is not set +# CONFIG_VHOST_MENU is not set +# CONFIG_IOMMU_SUPPORT is not set +CONFIG_DAX=m +CONFIG_EXT4_FS=y +CONFIG_REISERFS_FS=m +CONFIG_JFS_FS=m +CONFIG_OCFS2_FS=m +# CONFIG_OCFS2_DEBUG_MASKLOG is not set +CONFIG_FANOTIFY=y +CONFIG_QUOTA_NETLINK_INTERFACE=y +# CONFIG_PRINT_QUOTA_WARNING is not set +CONFIG_AUTOFS_FS=m +CONFIG_FUSE_FS=m +CONFIG_CUSE=m +CONFIG_OVERLAY_FS=m +CONFIG_ISO9660_FS=y +CONFIG_JOLIET=y +CONFIG_ZISOFS=y +CONFIG_UDF_FS=m +CONFIG_MSDOS_FS=m +CONFIG_VFAT_FS=m +CONFIG_EXFAT_FS=m +CONFIG_PROC_KCORE=y +CONFIG_PROC_CHILDREN=y +CONFIG_TMPFS=y +CONFIG_ORANGEFS_FS=m +CONFIG_AFFS_FS=m +CONFIG_ECRYPT_FS=m +CONFIG_ECRYPT_FS_MESSAGING=y +CONFIG_HFS_FS=m +CONFIG_HFSPLUS_FS=m +CONFIG_CRAMFS=m +CONFIG_SQUASHFS=m +CONFIG_SQUASHFS_LZ4=y +CONFIG_SQUASHFS_LZO=y +CONFIG_MINIX_FS=m +CONFIG_OMFS_FS=m +CONFIG_HPFS_FS=m +CONFIG_QNX4FS_FS=m +CONFIG_QNX6FS_FS=m +CONFIG_SYSV_FS=m +CONFIG_UFS_FS=m +CONFIG_EROFS_FS=m +CONFIG_NFS_FS=y +CONFIG_NFS_V4=m +CONFIG_NFS_SWAP=y +CONFIG_ROOT_NFS=y +CONFIG_NFSD=m +CONFIG_NFSD_V3=y +CONFIG_CIFS=m +# CONFIG_CIFS_DEBUG is not set +CONFIG_CODA_FS=m +CONFIG_NLS_CODEPAGE_437=y +CONFIG_NLS_CODEPAGE_737=m +CONFIG_NLS_CODEPAGE_775=m +CONFIG_NLS_CODEPAGE_850=m +CONFIG_NLS_CODEPAGE_852=m +CONFIG_NLS_CODEPAGE_855=m +CONFIG_NLS_CODEPAGE_857=m +CONFIG_NLS_CODEPAGE_860=m +CONFIG_NLS_CODEPAGE_861=m +CONFIG_NLS_CODEPAGE_862=m +CONFIG_NLS_CODEPAGE_863=m +CONFIG_NLS_CODEPAGE_864=m +CONFIG_NLS_CODEPAGE_865=m +CONFIG_NLS_CODEPAGE_866=m +CONFIG_NLS_CODEPAGE_869=m +CONFIG_NLS_CODEPAGE_936=m +CONFIG_NLS_CODEPAGE_950=m +CONFIG_NLS_CODEPAGE_932=m +CONFIG_NLS_CODEPAGE_949=m +CONFIG_NLS_CODEPAGE_874=m +CONFIG_NLS_ISO8859_8=m +CONFIG_NLS_CODEPAGE_1250=m +CONFIG_NLS_CODEPAGE_1251=m +CONFIG_NLS_ASCII=m +CONFIG_NLS_ISO8859_1=y +CONFIG_NLS_ISO8859_2=m +CONFIG_NLS_ISO8859_3=m +CONFIG_NLS_ISO8859_4=m +CONFIG_NLS_ISO8859_5=m +CONFIG_NLS_ISO8859_6=m +CONFIG_NLS_ISO8859_7=m +CONFIG_NLS_ISO8859_9=m +CONFIG_NLS_ISO8859_13=m +CONFIG_NLS_ISO8859_14=m +CONFIG_NLS_ISO8859_15=m +CONFIG_NLS_KOI8_R=m +CONFIG_NLS_KOI8_U=m +CONFIG_NLS_MAC_ROMAN=m +CONFIG_NLS_MAC_CELTIC=m +CONFIG_NLS_MAC_CENTEURO=m +CONFIG_NLS_MAC_CROATIAN=m +CONFIG_NLS_MAC_CYRILLIC=m +CONFIG_NLS_MAC_GAELIC=m +CONFIG_NLS_MAC_GREEK=m +CONFIG_NLS_MAC_ICELAND=m +CONFIG_NLS_MAC_INUIT=m +CONFIG_NLS_MAC_ROMANIAN=m +CONFIG_NLS_MAC_TURKISH=m +CONFIG_DLM=m +CONFIG_ENCRYPTED_KEYS=m +CONFIG_HARDENED_USERCOPY=y +CONFIG_CRYPTO_MANAGER=y +CONFIG_CRYPTO_USER=m +CONFIG_CRYPTO_CRYPTD=m +CONFIG_CRYPTO_TEST=m +CONFIG_CRYPTO_RSA=m +CONFIG_CRYPTO_DH=m +CONFIG_CRYPTO_ECDH=m +CONFIG_CRYPTO_ECRDSA=m +CONFIG_CRYPTO_CURVE25519=m +CONFIG_CRYPTO_CHACHA20POLY1305=m +CONFIG_CRYPTO_AEGIS128=m +CONFIG_CRYPTO_CFB=m +CONFIG_CRYPTO_CTS=m +CONFIG_CRYPTO_LRW=m +CONFIG_CRYPTO_OFB=m +CONFIG_CRYPTO_PCBC=m +CONFIG_CRYPTO_XTS=m +CONFIG_CRYPTO_KEYWRAP=m +CONFIG_CRYPTO_ADIANTUM=m +CONFIG_CRYPTO_XCBC=m +CONFIG_CRYPTO_VMAC=m +CONFIG_CRYPTO_BLAKE2S=m +CONFIG_CRYPTO_MICHAEL_MIC=m +CONFIG_CRYPTO_RMD128=m +CONFIG_CRYPTO_RMD160=m +CONFIG_CRYPTO_RMD256=m +CONFIG_CRYPTO_RMD320=m +CONFIG_CRYPTO_SHA3=m +CONFIG_CRYPTO_SM3=m +CONFIG_CRYPTO_TGR192=m +CONFIG_CRYPTO_WP512=m +CONFIG_CRYPTO_AES=y +CONFIG_CRYPTO_AES_TI=m +CONFIG_CRYPTO_ANUBIS=m +CONFIG_CRYPTO_ARC4=m +CONFIG_CRYPTO_BLOWFISH=m +CONFIG_CRYPTO_CAMELLIA=m +CONFIG_CRYPTO_CAST5=m +CONFIG_CRYPTO_CAST6=m +CONFIG_CRYPTO_DES=m +CONFIG_CRYPTO_FCRYPT=m +CONFIG_CRYPTO_KHAZAD=m +CONFIG_CRYPTO_SALSA20=m +CONFIG_CRYPTO_SEED=m +CONFIG_CRYPTO_SERPENT=m +CONFIG_CRYPTO_SM4=m +CONFIG_CRYPTO_TEA=m +CONFIG_CRYPTO_TWOFISH=m +CONFIG_CRYPTO_LZO=m +CONFIG_CRYPTO_842=m +CONFIG_CRYPTO_LZ4=m +CONFIG_CRYPTO_LZ4HC=m +CONFIG_CRYPTO_ZSTD=m +CONFIG_CRYPTO_ANSI_CPRNG=m +CONFIG_CRYPTO_DRBG_HASH=y +CONFIG_CRYPTO_DRBG_CTR=y +CONFIG_CRYPTO_USER_API_HASH=m +CONFIG_CRYPTO_USER_API_SKCIPHER=m +CONFIG_CRYPTO_USER_API_RNG=m +CONFIG_CRYPTO_USER_API_AEAD=m +# CONFIG_CRYPTO_HW is not set +CONFIG_PRIME_NUMBERS=m +CONFIG_CRC32_SELFTEST=m +CONFIG_CRC64=m +CONFIG_XZ_DEC_TEST=m +CONFIG_STRING_SELFTEST=m +# CONFIG_SECTION_MISMATCH_WARN_ONLY is not set +CONFIG_MAGIC_SYSRQ=y +CONFIG_TEST_LOCKUP=m +CONFIG_WW_MUTEX_SELFTEST=m +CONFIG_EARLY_PRINTK=y +CONFIG_TEST_LIST_SORT=m +CONFIG_TEST_MIN_HEAP=m +CONFIG_TEST_SORT=m +CONFIG_REED_SOLOMON_TEST=m +CONFIG_ATOMIC64_SELFTEST=m +CONFIG_ASYNC_RAID6_TEST=m +CONFIG_TEST_HEXDUMP=m +CONFIG_TEST_STRING_HELPERS=m +CONFIG_TEST_STRSCPY=m +CONFIG_TEST_KSTRTOX=m +CONFIG_TEST_PRINTF=m +CONFIG_TEST_BITMAP=m +CONFIG_TEST_BITFIELD=m +CONFIG_TEST_UUID=m +CONFIG_TEST_XARRAY=m +CONFIG_TEST_OVERFLOW=m +CONFIG_TEST_RHASHTABLE=m +CONFIG_TEST_HASH=m +CONFIG_TEST_IDA=m +CONFIG_TEST_BITOPS=m +CONFIG_TEST_VMALLOC=m +CONFIG_TEST_USER_COPY=m +CONFIG_TEST_BPF=m +CONFIG_TEST_BLACKHOLE_DEV=m +CONFIG_FIND_BIT_BENCHMARK=m +CONFIG_TEST_FIRMWARE=m +CONFIG_TEST_SYSCTL=m +CONFIG_TEST_UDELAY=m +CONFIG_TEST_STATIC_KEYS=m +CONFIG_TEST_KMOD=m +CONFIG_TEST_MEMCAT_P=m +CONFIG_TEST_STACKINIT=m +CONFIG_TEST_MEMINIT=m diff --git a/arch/m68k/configs/multi_defconfig b/arch/m68k/configs/multi_defconfig new file mode 100644 index 000000000..c3d6faa78 --- /dev/null +++ b/arch/m68k/configs/multi_defconfig @@ -0,0 +1,728 @@ +CONFIG_LOCALVERSION="-multi" +CONFIG_SYSVIPC=y +CONFIG_POSIX_MQUEUE=y +CONFIG_BSD_PROCESS_ACCT=y +CONFIG_BSD_PROCESS_ACCT_V3=y +CONFIG_LOG_BUF_SHIFT=16 +# CONFIG_UTS_NS is not set +# CONFIG_IPC_NS is not set +# CONFIG_PID_NS is not set +# CONFIG_NET_NS is not set +CONFIG_BLK_DEV_INITRD=y +CONFIG_CC_OPTIMIZE_FOR_SIZE=y +CONFIG_USERFAULTFD=y +CONFIG_SLAB=y +CONFIG_KEXEC=y +CONFIG_BOOTINFO_PROC=y +CONFIG_M68020=y +CONFIG_M68040=y +CONFIG_M68060=y +CONFIG_M68KFPU_EMU=y +CONFIG_AMIGA=y +CONFIG_ATARI=y +CONFIG_MAC=y +CONFIG_APOLLO=y +CONFIG_VME=y +CONFIG_MVME147=y +CONFIG_MVME16x=y +CONFIG_BVME6000=y +CONFIG_HP300=y +CONFIG_SUN3X=y +CONFIG_Q40=y +CONFIG_ZORRO=y +CONFIG_AMIGA_PCMCIA=y +CONFIG_ATARI_ROM_ISA=y +CONFIG_ZORRO_NAMES=y +CONFIG_HEARTBEAT=y +CONFIG_PROC_HARDWARE=y +CONFIG_NATFEAT=y +CONFIG_NFBLOCK=y +CONFIG_NFCON=y +CONFIG_NFETH=y +CONFIG_ATARI_ETHERNAT=y +CONFIG_ATARI_ETHERNEC=y +CONFIG_ATARI_DSP56K=m +CONFIG_AMIGA_BUILTIN_SERIAL=y +CONFIG_SERIAL_CONSOLE=y +CONFIG_MODULES=y +CONFIG_MODULE_UNLOAD=y +CONFIG_PARTITION_ADVANCED=y +CONFIG_BSD_DISKLABEL=y +CONFIG_MINIX_SUBPARTITION=y +CONFIG_SOLARIS_X86_PARTITION=y +CONFIG_UNIXWARE_DISKLABEL=y +# CONFIG_EFI_PARTITION is not set +CONFIG_MQ_IOSCHED_DEADLINE=m +CONFIG_MQ_IOSCHED_KYBER=m +CONFIG_IOSCHED_BFQ=m +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +CONFIG_BINFMT_AOUT=m +CONFIG_BINFMT_MISC=m +# CONFIG_COMPACTION is not set +CONFIG_CLEANCACHE=y +CONFIG_ZPOOL=m +CONFIG_NET=y +CONFIG_PACKET=y +CONFIG_PACKET_DIAG=m +CONFIG_UNIX=y +CONFIG_UNIX_DIAG=m +CONFIG_TLS=m +CONFIG_XFRM_MIGRATE=y +CONFIG_NET_KEY=y +CONFIG_XDP_SOCKETS=y +CONFIG_XDP_SOCKETS_DIAG=m +CONFIG_INET=y +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +CONFIG_IP_PNP_BOOTP=y +CONFIG_IP_PNP_RARP=y +CONFIG_NET_IPIP=m +CONFIG_NET_IPGRE_DEMUX=m +CONFIG_NET_IPGRE=m +CONFIG_NET_IPVTI=m +CONFIG_NET_FOU_IP_TUNNELS=y +CONFIG_INET_AH=m +CONFIG_INET_ESP=m +CONFIG_INET_ESP_OFFLOAD=m +CONFIG_INET_IPCOMP=m +CONFIG_INET_DIAG=m +CONFIG_INET_UDP_DIAG=m +CONFIG_INET_RAW_DIAG=m +CONFIG_IPV6=m +CONFIG_IPV6_ROUTER_PREF=y +CONFIG_INET6_AH=m +CONFIG_INET6_ESP=m +CONFIG_INET6_ESP_OFFLOAD=m +CONFIG_INET6_IPCOMP=m +CONFIG_IPV6_ILA=m +CONFIG_IPV6_VTI=m +CONFIG_IPV6_GRE=m +CONFIG_NETFILTER=y +CONFIG_NF_CONNTRACK=m +CONFIG_NF_LOG_NETDEV=m +CONFIG_NF_CONNTRACK_ZONES=y +# CONFIG_NF_CONNTRACK_PROCFS is not set +# CONFIG_NF_CT_PROTO_DCCP is not set +CONFIG_NF_CONNTRACK_AMANDA=m +CONFIG_NF_CONNTRACK_FTP=m +CONFIG_NF_CONNTRACK_H323=m +CONFIG_NF_CONNTRACK_IRC=m +CONFIG_NF_CONNTRACK_NETBIOS_NS=m +CONFIG_NF_CONNTRACK_SNMP=m +CONFIG_NF_CONNTRACK_PPTP=m +CONFIG_NF_CONNTRACK_SANE=m +CONFIG_NF_CONNTRACK_SIP=m +CONFIG_NF_CONNTRACK_TFTP=m +CONFIG_NF_TABLES=m +CONFIG_NF_TABLES_INET=y +CONFIG_NF_TABLES_NETDEV=y +CONFIG_NFT_NUMGEN=m +CONFIG_NFT_CT=m +CONFIG_NFT_FLOW_OFFLOAD=m +CONFIG_NFT_COUNTER=m +CONFIG_NFT_CONNLIMIT=m +CONFIG_NFT_LOG=m +CONFIG_NFT_LIMIT=m +CONFIG_NFT_MASQ=m +CONFIG_NFT_REDIR=m +CONFIG_NFT_NAT=m +CONFIG_NFT_TUNNEL=m +CONFIG_NFT_OBJREF=m +CONFIG_NFT_QUEUE=m +CONFIG_NFT_QUOTA=m +CONFIG_NFT_REJECT=m +CONFIG_NFT_COMPAT=m +CONFIG_NFT_HASH=m +CONFIG_NFT_FIB_INET=m +CONFIG_NFT_XFRM=m +CONFIG_NFT_SOCKET=m +CONFIG_NFT_OSF=m +CONFIG_NFT_TPROXY=m +CONFIG_NFT_SYNPROXY=m +CONFIG_NFT_DUP_NETDEV=m +CONFIG_NFT_FWD_NETDEV=m +CONFIG_NFT_FIB_NETDEV=m +CONFIG_NF_FLOW_TABLE_INET=m +CONFIG_NF_FLOW_TABLE=m +CONFIG_NETFILTER_XT_SET=m +CONFIG_NETFILTER_XT_TARGET_CHECKSUM=m +CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m +CONFIG_NETFILTER_XT_TARGET_CONNMARK=m +CONFIG_NETFILTER_XT_TARGET_DSCP=m +CONFIG_NETFILTER_XT_TARGET_HMARK=m +CONFIG_NETFILTER_XT_TARGET_IDLETIMER=m +CONFIG_NETFILTER_XT_TARGET_LOG=m +CONFIG_NETFILTER_XT_TARGET_MARK=m +CONFIG_NETFILTER_XT_TARGET_NFLOG=m +CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m +CONFIG_NETFILTER_XT_TARGET_NOTRACK=m +CONFIG_NETFILTER_XT_TARGET_TEE=m +CONFIG_NETFILTER_XT_TARGET_TPROXY=m +CONFIG_NETFILTER_XT_TARGET_TRACE=m +CONFIG_NETFILTER_XT_TARGET_TCPMSS=m +CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP=m +CONFIG_NETFILTER_XT_MATCH_ADDRTYPE=m +CONFIG_NETFILTER_XT_MATCH_BPF=m +CONFIG_NETFILTER_XT_MATCH_CLUSTER=m +CONFIG_NETFILTER_XT_MATCH_COMMENT=m +CONFIG_NETFILTER_XT_MATCH_CONNBYTES=m +CONFIG_NETFILTER_XT_MATCH_CONNLABEL=m +CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=m +CONFIG_NETFILTER_XT_MATCH_CONNMARK=m +CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m +CONFIG_NETFILTER_XT_MATCH_DEVGROUP=m +CONFIG_NETFILTER_XT_MATCH_DSCP=m +CONFIG_NETFILTER_XT_MATCH_ESP=m +CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=m +CONFIG_NETFILTER_XT_MATCH_HELPER=m +CONFIG_NETFILTER_XT_MATCH_IPCOMP=m +CONFIG_NETFILTER_XT_MATCH_IPRANGE=m +CONFIG_NETFILTER_XT_MATCH_LENGTH=m +CONFIG_NETFILTER_XT_MATCH_LIMIT=m +CONFIG_NETFILTER_XT_MATCH_MAC=m +CONFIG_NETFILTER_XT_MATCH_MARK=m +CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m +CONFIG_NETFILTER_XT_MATCH_NFACCT=m +CONFIG_NETFILTER_XT_MATCH_OSF=m +CONFIG_NETFILTER_XT_MATCH_OWNER=m +CONFIG_NETFILTER_XT_MATCH_POLICY=m +CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m +CONFIG_NETFILTER_XT_MATCH_QUOTA=m +CONFIG_NETFILTER_XT_MATCH_RATEEST=m +CONFIG_NETFILTER_XT_MATCH_REALM=m +CONFIG_NETFILTER_XT_MATCH_RECENT=m +CONFIG_NETFILTER_XT_MATCH_SOCKET=m +CONFIG_NETFILTER_XT_MATCH_STATE=m +CONFIG_NETFILTER_XT_MATCH_STATISTIC=m +CONFIG_NETFILTER_XT_MATCH_STRING=m +CONFIG_NETFILTER_XT_MATCH_TCPMSS=m +CONFIG_NETFILTER_XT_MATCH_TIME=m +CONFIG_NETFILTER_XT_MATCH_U32=m +CONFIG_IP_SET=m +CONFIG_IP_SET_BITMAP_IP=m +CONFIG_IP_SET_BITMAP_IPMAC=m +CONFIG_IP_SET_BITMAP_PORT=m +CONFIG_IP_SET_HASH_IP=m +CONFIG_IP_SET_HASH_IPMARK=m +CONFIG_IP_SET_HASH_IPPORT=m +CONFIG_IP_SET_HASH_IPPORTIP=m +CONFIG_IP_SET_HASH_IPPORTNET=m +CONFIG_IP_SET_HASH_IPMAC=m +CONFIG_IP_SET_HASH_MAC=m +CONFIG_IP_SET_HASH_NETPORTNET=m +CONFIG_IP_SET_HASH_NET=m +CONFIG_IP_SET_HASH_NETNET=m +CONFIG_IP_SET_HASH_NETPORT=m +CONFIG_IP_SET_HASH_NETIFACE=m +CONFIG_IP_SET_LIST_SET=m +CONFIG_NFT_DUP_IPV4=m +CONFIG_NFT_FIB_IPV4=m +CONFIG_NF_TABLES_ARP=y +CONFIG_NF_FLOW_TABLE_IPV4=m +CONFIG_NF_LOG_ARP=m +CONFIG_IP_NF_IPTABLES=m +CONFIG_IP_NF_MATCH_AH=m +CONFIG_IP_NF_MATCH_ECN=m +CONFIG_IP_NF_MATCH_RPFILTER=m +CONFIG_IP_NF_MATCH_TTL=m +CONFIG_IP_NF_FILTER=m +CONFIG_IP_NF_TARGET_REJECT=m +CONFIG_IP_NF_TARGET_SYNPROXY=m +CONFIG_IP_NF_NAT=m +CONFIG_IP_NF_TARGET_MASQUERADE=m +CONFIG_IP_NF_TARGET_NETMAP=m +CONFIG_IP_NF_TARGET_REDIRECT=m +CONFIG_IP_NF_MANGLE=m +CONFIG_IP_NF_TARGET_CLUSTERIP=m +CONFIG_IP_NF_TARGET_ECN=m +CONFIG_IP_NF_TARGET_TTL=m +CONFIG_IP_NF_RAW=m +CONFIG_IP_NF_ARPTABLES=m +CONFIG_IP_NF_ARPFILTER=m +CONFIG_IP_NF_ARP_MANGLE=m +CONFIG_NFT_DUP_IPV6=m +CONFIG_NFT_FIB_IPV6=m +CONFIG_NF_FLOW_TABLE_IPV6=m +CONFIG_IP6_NF_IPTABLES=m +CONFIG_IP6_NF_MATCH_AH=m +CONFIG_IP6_NF_MATCH_EUI64=m +CONFIG_IP6_NF_MATCH_FRAG=m +CONFIG_IP6_NF_MATCH_OPTS=m +CONFIG_IP6_NF_MATCH_HL=m +CONFIG_IP6_NF_MATCH_IPV6HEADER=m +CONFIG_IP6_NF_MATCH_MH=m +CONFIG_IP6_NF_MATCH_RPFILTER=m +CONFIG_IP6_NF_MATCH_RT=m +CONFIG_IP6_NF_MATCH_SRH=m +CONFIG_IP6_NF_TARGET_HL=m +CONFIG_IP6_NF_FILTER=m +CONFIG_IP6_NF_TARGET_REJECT=m +CONFIG_IP6_NF_TARGET_SYNPROXY=m +CONFIG_IP6_NF_MANGLE=m +CONFIG_IP6_NF_RAW=m +CONFIG_IP6_NF_NAT=m +CONFIG_IP6_NF_TARGET_MASQUERADE=m +CONFIG_IP6_NF_TARGET_NPT=m +CONFIG_NF_TABLES_BRIDGE=m +CONFIG_NFT_BRIDGE_META=m +CONFIG_NFT_BRIDGE_REJECT=m +CONFIG_NF_LOG_BRIDGE=m +CONFIG_NF_CONNTRACK_BRIDGE=m +CONFIG_BRIDGE_NF_EBTABLES=m +CONFIG_BRIDGE_EBT_BROUTE=m +CONFIG_BRIDGE_EBT_T_FILTER=m +CONFIG_BRIDGE_EBT_T_NAT=m +CONFIG_BRIDGE_EBT_802_3=m +CONFIG_BRIDGE_EBT_AMONG=m +CONFIG_BRIDGE_EBT_ARP=m +CONFIG_BRIDGE_EBT_IP=m +CONFIG_BRIDGE_EBT_IP6=m +CONFIG_BRIDGE_EBT_LIMIT=m +CONFIG_BRIDGE_EBT_MARK=m +CONFIG_BRIDGE_EBT_PKTTYPE=m +CONFIG_BRIDGE_EBT_STP=m +CONFIG_BRIDGE_EBT_VLAN=m +CONFIG_BRIDGE_EBT_ARPREPLY=m +CONFIG_BRIDGE_EBT_DNAT=m +CONFIG_BRIDGE_EBT_MARK_T=m +CONFIG_BRIDGE_EBT_REDIRECT=m +CONFIG_BRIDGE_EBT_SNAT=m +CONFIG_BRIDGE_EBT_LOG=m +CONFIG_BRIDGE_EBT_NFLOG=m +CONFIG_IP_DCCP=m +# CONFIG_IP_DCCP_CCID3 is not set +CONFIG_SCTP_COOKIE_HMAC_SHA1=y +CONFIG_RDS=m +CONFIG_RDS_TCP=m +CONFIG_L2TP=m +CONFIG_BRIDGE=m +CONFIG_ATALK=m +CONFIG_DEV_APPLETALK=m +CONFIG_IPDDP=m +CONFIG_IPDDP_ENCAP=y +CONFIG_6LOWPAN=m +CONFIG_6LOWPAN_GHC_EXT_HDR_HOP=m +CONFIG_6LOWPAN_GHC_UDP=m +CONFIG_6LOWPAN_GHC_ICMPV6=m +CONFIG_6LOWPAN_GHC_EXT_HDR_DEST=m +CONFIG_6LOWPAN_GHC_EXT_HDR_FRAG=m +CONFIG_6LOWPAN_GHC_EXT_HDR_ROUTE=m +CONFIG_DNS_RESOLVER=y +CONFIG_BATMAN_ADV=m +# CONFIG_BATMAN_ADV_BATMAN_V is not set +CONFIG_BATMAN_ADV_NC=y +CONFIG_NETLINK_DIAG=m +CONFIG_MPLS=y +CONFIG_NET_MPLS_GSO=m +CONFIG_MPLS_ROUTING=m +CONFIG_MPLS_IPTUNNEL=m +CONFIG_NET_NSH=m +CONFIG_AF_KCM=m +# CONFIG_WIRELESS is not set +CONFIG_PSAMPLE=m +CONFIG_NET_IFE=m +CONFIG_DEVTMPFS=y +CONFIG_DEVTMPFS_MOUNT=y +CONFIG_TEST_ASYNC_DRIVER_PROBE=m +CONFIG_CONNECTOR=m +CONFIG_PARPORT=m +CONFIG_PARPORT_PC=m +CONFIG_PARPORT_AMIGA=m +CONFIG_PARPORT_MFC3=m +CONFIG_PARPORT_ATARI=m +CONFIG_PARPORT_1284=y +CONFIG_AMIGA_FLOPPY=y +CONFIG_ATARI_FLOPPY=y +CONFIG_BLK_DEV_SWIM=m +CONFIG_AMIGA_Z2RAM=y +CONFIG_BLK_DEV_LOOP=y +CONFIG_BLK_DEV_CRYPTOLOOP=m +CONFIG_BLK_DEV_DRBD=m +CONFIG_BLK_DEV_NBD=m +CONFIG_BLK_DEV_RAM=y +CONFIG_CDROM_PKTCDVD=m +CONFIG_ATA_OVER_ETH=m +CONFIG_DUMMY_IRQ=m +CONFIG_IDE=y +CONFIG_IDE_GD_ATAPI=y +CONFIG_BLK_DEV_IDECD=y +CONFIG_BLK_DEV_PLATFORM=y +CONFIG_BLK_DEV_GAYLE=y +CONFIG_BLK_DEV_BUDDHA=y +CONFIG_BLK_DEV_FALCON_IDE=y +CONFIG_BLK_DEV_MAC_IDE=y +CONFIG_BLK_DEV_Q40IDE=y +CONFIG_RAID_ATTRS=m +CONFIG_SCSI=y +CONFIG_BLK_DEV_SD=y +CONFIG_CHR_DEV_ST=m +CONFIG_BLK_DEV_SR=y +CONFIG_CHR_DEV_SG=m +CONFIG_SCSI_CONSTANTS=y +CONFIG_SCSI_SAS_ATTRS=m +CONFIG_ISCSI_TCP=m +CONFIG_ISCSI_BOOT_SYSFS=m +CONFIG_A3000_SCSI=y +CONFIG_A2091_SCSI=y +CONFIG_GVP11_SCSI=y +CONFIG_SCSI_A4000T=y +CONFIG_SCSI_ZORRO7XX=y +CONFIG_SCSI_ZORRO_ESP=y +CONFIG_ATARI_SCSI=y +CONFIG_MAC_SCSI=y +CONFIG_SCSI_MAC_ESP=y +CONFIG_MVME147_SCSI=y +CONFIG_MVME16x_SCSI=y +CONFIG_BVME6000_SCSI=y +CONFIG_SUN3X_ESP=y +CONFIG_MD=y +CONFIG_MD_LINEAR=m +CONFIG_BLK_DEV_DM=m +CONFIG_DM_UNSTRIPED=m +CONFIG_DM_CRYPT=m +CONFIG_DM_SNAPSHOT=m +CONFIG_DM_THIN_PROVISIONING=m +CONFIG_DM_WRITECACHE=m +CONFIG_DM_ERA=m +CONFIG_DM_CLONE=m +CONFIG_DM_MIRROR=m +CONFIG_DM_RAID=m +CONFIG_DM_ZERO=m +CONFIG_DM_MULTIPATH=m +CONFIG_DM_UEVENT=y +CONFIG_DM_LOG_WRITES=m +CONFIG_DM_INTEGRITY=m +CONFIG_TARGET_CORE=m +CONFIG_TCM_IBLOCK=m +CONFIG_TCM_FILEIO=m +CONFIG_TCM_PSCSI=m +CONFIG_ADB=y +CONFIG_ADB_MACII=y +CONFIG_ADB_IOP=y +CONFIG_ADB_CUDA=y +CONFIG_ADB_PMU=y +CONFIG_INPUT_ADBHID=y +CONFIG_MAC_EMUMOUSEBTN=y +CONFIG_NETDEVICES=y +CONFIG_DUMMY=m +CONFIG_WIREGUARD=m +CONFIG_EQUALIZER=m +CONFIG_NET_TEAM=m +CONFIG_NET_TEAM_MODE_BROADCAST=m +CONFIG_NET_TEAM_MODE_ROUNDROBIN=m +CONFIG_NET_TEAM_MODE_RANDOM=m +CONFIG_NET_TEAM_MODE_ACTIVEBACKUP=m +CONFIG_NET_TEAM_MODE_LOADBALANCE=m +CONFIG_MACVLAN=m +CONFIG_MACVTAP=m +CONFIG_IPVLAN=m +CONFIG_IPVTAP=m +CONFIG_VXLAN=m +CONFIG_GENEVE=m +CONFIG_BAREUDP=m +CONFIG_GTP=m +CONFIG_MACSEC=m +CONFIG_NETCONSOLE=m +CONFIG_NETCONSOLE_DYNAMIC=y +CONFIG_VETH=m +CONFIG_A2065=y +CONFIG_ARIADNE=y +CONFIG_ATARILANCE=y +CONFIG_HPLANCE=y +CONFIG_MVME147_NET=y +CONFIG_SUN3LANCE=y +CONFIG_MACMACE=y +CONFIG_MAC89x0=y +CONFIG_BVME6000_NET=y +CONFIG_MVME16x_NET=y +CONFIG_MACSONIC=y +CONFIG_XSURF100=y +CONFIG_HYDRA=y +CONFIG_MAC8390=y +CONFIG_NE2000=y +CONFIG_APNE=y +CONFIG_ZORRO8390=y +CONFIG_SMC91X=y +CONFIG_PLIP=m +CONFIG_PPP=m +CONFIG_PPP_BSDCOMP=m +CONFIG_PPP_DEFLATE=m +CONFIG_PPP_FILTER=y +CONFIG_PPP_MPPE=m +CONFIG_PPPOE=m +CONFIG_PPTP=m +CONFIG_PPPOL2TP=m +CONFIG_PPP_ASYNC=m +CONFIG_PPP_SYNC_TTY=m +CONFIG_SLIP=m +CONFIG_SLIP_COMPRESSED=y +CONFIG_SLIP_SMART=y +CONFIG_SLIP_MODE_SLIP6=y +# CONFIG_WLAN is not set +CONFIG_INPUT_EVDEV=m +CONFIG_KEYBOARD_AMIGA=y +CONFIG_KEYBOARD_ATARI=y +# CONFIG_KEYBOARD_ATKBD is not set +CONFIG_KEYBOARD_SUNKBD=y +# CONFIG_MOUSE_PS2 is not set +CONFIG_MOUSE_SERIAL=m +CONFIG_MOUSE_AMIGA=m +CONFIG_MOUSE_ATARI=m +CONFIG_INPUT_JOYSTICK=y +CONFIG_JOYSTICK_AMIGA=m +CONFIG_INPUT_MISC=y +CONFIG_INPUT_M68K_BEEP=m +CONFIG_HP_SDC_RTC=m +CONFIG_SERIO_Q40KBD=y +CONFIG_USERIO=m +# CONFIG_LEGACY_PTYS is not set +CONFIG_SERIAL_PMACZILOG=y +CONFIG_SERIAL_PMACZILOG_TTYS=y +CONFIG_SERIAL_PMACZILOG_CONSOLE=y +CONFIG_PRINTER=m +# CONFIG_HW_RANDOM is not set +CONFIG_I2C=m +CONFIG_I2C_CHARDEV=m +CONFIG_I2C_ICY=m +CONFIG_NTP_PPS=y +CONFIG_PPS_CLIENT_LDISC=m +CONFIG_PPS_CLIENT_PARPORT=m +CONFIG_PTP_1588_CLOCK=m +CONFIG_HWMON=m +CONFIG_SENSORS_LTC2990=m +CONFIG_FB=y +CONFIG_FB_CIRRUS=y +CONFIG_FB_AMIGA=y +CONFIG_FB_AMIGA_OCS=y +CONFIG_FB_AMIGA_ECS=y +CONFIG_FB_AMIGA_AGA=y +CONFIG_FB_FM2=y +CONFIG_FB_ATARI=y +CONFIG_FB_VALKYRIE=y +CONFIG_FB_MAC=y +CONFIG_FRAMEBUFFER_CONSOLE=y +CONFIG_LOGO=y +CONFIG_SOUND=m +CONFIG_DMASOUND_ATARI=m +CONFIG_DMASOUND_PAULA=m +CONFIG_DMASOUND_Q40=m +CONFIG_HID=m +CONFIG_HIDRAW=y +CONFIG_UHID=m +# CONFIG_HID_GENERIC is not set +# CONFIG_HID_ITE is not set +# CONFIG_HID_REDRAGON is not set +# CONFIG_USB_SUPPORT is not set +CONFIG_RTC_CLASS=y +# CONFIG_RTC_NVMEM is not set +CONFIG_RTC_DRV_MSM6242=m +CONFIG_RTC_DRV_RP5C01=m +CONFIG_RTC_DRV_GENERIC=m +# CONFIG_VIRTIO_MENU is not set +# CONFIG_VHOST_MENU is not set +# CONFIG_IOMMU_SUPPORT is not set +CONFIG_DAX=m +CONFIG_EXT4_FS=y +CONFIG_REISERFS_FS=m +CONFIG_JFS_FS=m +CONFIG_OCFS2_FS=m +# CONFIG_OCFS2_DEBUG_MASKLOG is not set +CONFIG_FANOTIFY=y +CONFIG_QUOTA_NETLINK_INTERFACE=y +# CONFIG_PRINT_QUOTA_WARNING is not set +CONFIG_AUTOFS_FS=m +CONFIG_FUSE_FS=m +CONFIG_CUSE=m +CONFIG_OVERLAY_FS=m +CONFIG_ISO9660_FS=y +CONFIG_JOLIET=y +CONFIG_ZISOFS=y +CONFIG_UDF_FS=m +CONFIG_MSDOS_FS=m +CONFIG_VFAT_FS=m +CONFIG_EXFAT_FS=m +CONFIG_PROC_KCORE=y +CONFIG_PROC_CHILDREN=y +CONFIG_TMPFS=y +CONFIG_ORANGEFS_FS=m +CONFIG_AFFS_FS=m +CONFIG_ECRYPT_FS=m +CONFIG_ECRYPT_FS_MESSAGING=y +CONFIG_HFS_FS=m +CONFIG_HFSPLUS_FS=m +CONFIG_CRAMFS=m +CONFIG_SQUASHFS=m +CONFIG_SQUASHFS_LZ4=y +CONFIG_SQUASHFS_LZO=y +CONFIG_MINIX_FS=m +CONFIG_OMFS_FS=m +CONFIG_HPFS_FS=m +CONFIG_QNX4FS_FS=m +CONFIG_QNX6FS_FS=m +CONFIG_SYSV_FS=m +CONFIG_UFS_FS=m +CONFIG_EROFS_FS=m +CONFIG_NFS_FS=y +CONFIG_NFS_V4=m +CONFIG_NFS_SWAP=y +CONFIG_ROOT_NFS=y +CONFIG_NFSD=m +CONFIG_NFSD_V3=y +CONFIG_CIFS=m +# CONFIG_CIFS_DEBUG is not set +CONFIG_CODA_FS=m +CONFIG_NLS_CODEPAGE_437=y +CONFIG_NLS_CODEPAGE_737=m +CONFIG_NLS_CODEPAGE_775=m +CONFIG_NLS_CODEPAGE_850=m +CONFIG_NLS_CODEPAGE_852=m +CONFIG_NLS_CODEPAGE_855=m +CONFIG_NLS_CODEPAGE_857=m +CONFIG_NLS_CODEPAGE_860=m +CONFIG_NLS_CODEPAGE_861=m +CONFIG_NLS_CODEPAGE_862=m +CONFIG_NLS_CODEPAGE_863=m +CONFIG_NLS_CODEPAGE_864=m +CONFIG_NLS_CODEPAGE_865=m +CONFIG_NLS_CODEPAGE_866=m +CONFIG_NLS_CODEPAGE_869=m +CONFIG_NLS_CODEPAGE_936=m +CONFIG_NLS_CODEPAGE_950=m +CONFIG_NLS_CODEPAGE_932=m +CONFIG_NLS_CODEPAGE_949=m +CONFIG_NLS_CODEPAGE_874=m +CONFIG_NLS_ISO8859_8=m +CONFIG_NLS_CODEPAGE_1250=m +CONFIG_NLS_CODEPAGE_1251=m +CONFIG_NLS_ASCII=m +CONFIG_NLS_ISO8859_1=y +CONFIG_NLS_ISO8859_2=m +CONFIG_NLS_ISO8859_3=m +CONFIG_NLS_ISO8859_4=m +CONFIG_NLS_ISO8859_5=m +CONFIG_NLS_ISO8859_6=m +CONFIG_NLS_ISO8859_7=m +CONFIG_NLS_ISO8859_9=m +CONFIG_NLS_ISO8859_13=m +CONFIG_NLS_ISO8859_14=m +CONFIG_NLS_ISO8859_15=m +CONFIG_NLS_KOI8_R=m +CONFIG_NLS_KOI8_U=m +CONFIG_NLS_MAC_ROMAN=m +CONFIG_NLS_MAC_CELTIC=m +CONFIG_NLS_MAC_CENTEURO=m +CONFIG_NLS_MAC_CROATIAN=m +CONFIG_NLS_MAC_CYRILLIC=m +CONFIG_NLS_MAC_GAELIC=m +CONFIG_NLS_MAC_GREEK=m +CONFIG_NLS_MAC_ICELAND=m +CONFIG_NLS_MAC_INUIT=m +CONFIG_NLS_MAC_ROMANIAN=m +CONFIG_NLS_MAC_TURKISH=m +CONFIG_DLM=m +CONFIG_ENCRYPTED_KEYS=m +CONFIG_HARDENED_USERCOPY=y +CONFIG_CRYPTO_MANAGER=y +CONFIG_CRYPTO_USER=m +CONFIG_CRYPTO_CRYPTD=m +CONFIG_CRYPTO_TEST=m +CONFIG_CRYPTO_RSA=m +CONFIG_CRYPTO_DH=m +CONFIG_CRYPTO_ECDH=m +CONFIG_CRYPTO_ECRDSA=m +CONFIG_CRYPTO_CURVE25519=m +CONFIG_CRYPTO_CHACHA20POLY1305=m +CONFIG_CRYPTO_AEGIS128=m +CONFIG_CRYPTO_CFB=m +CONFIG_CRYPTO_CTS=m +CONFIG_CRYPTO_LRW=m +CONFIG_CRYPTO_OFB=m +CONFIG_CRYPTO_PCBC=m +CONFIG_CRYPTO_XTS=m +CONFIG_CRYPTO_KEYWRAP=m +CONFIG_CRYPTO_ADIANTUM=m +CONFIG_CRYPTO_XCBC=m +CONFIG_CRYPTO_VMAC=m +CONFIG_CRYPTO_BLAKE2S=m +CONFIG_CRYPTO_MICHAEL_MIC=m +CONFIG_CRYPTO_RMD128=m +CONFIG_CRYPTO_RMD160=m +CONFIG_CRYPTO_RMD256=m +CONFIG_CRYPTO_RMD320=m +CONFIG_CRYPTO_SHA3=m +CONFIG_CRYPTO_SM3=m +CONFIG_CRYPTO_TGR192=m +CONFIG_CRYPTO_WP512=m +CONFIG_CRYPTO_AES=y +CONFIG_CRYPTO_AES_TI=m +CONFIG_CRYPTO_ANUBIS=m +CONFIG_CRYPTO_ARC4=m +CONFIG_CRYPTO_BLOWFISH=m +CONFIG_CRYPTO_CAMELLIA=m +CONFIG_CRYPTO_CAST5=m +CONFIG_CRYPTO_CAST6=m +CONFIG_CRYPTO_DES=m +CONFIG_CRYPTO_FCRYPT=m +CONFIG_CRYPTO_KHAZAD=m +CONFIG_CRYPTO_SALSA20=m +CONFIG_CRYPTO_SEED=m +CONFIG_CRYPTO_SERPENT=m +CONFIG_CRYPTO_SM4=m +CONFIG_CRYPTO_TEA=m +CONFIG_CRYPTO_TWOFISH=m +CONFIG_CRYPTO_LZO=m +CONFIG_CRYPTO_842=m +CONFIG_CRYPTO_LZ4=m +CONFIG_CRYPTO_LZ4HC=m +CONFIG_CRYPTO_ZSTD=m +CONFIG_CRYPTO_ANSI_CPRNG=m +CONFIG_CRYPTO_DRBG_HASH=y +CONFIG_CRYPTO_DRBG_CTR=y +CONFIG_CRYPTO_USER_API_HASH=m +CONFIG_CRYPTO_USER_API_SKCIPHER=m +CONFIG_CRYPTO_USER_API_RNG=m +CONFIG_CRYPTO_USER_API_AEAD=m +# CONFIG_CRYPTO_HW is not set +CONFIG_PRIME_NUMBERS=m +CONFIG_CRC32_SELFTEST=m +CONFIG_CRC64=m +CONFIG_XZ_DEC_TEST=m +CONFIG_STRING_SELFTEST=m +# CONFIG_SECTION_MISMATCH_WARN_ONLY is not set +CONFIG_MAGIC_SYSRQ=y +CONFIG_TEST_LOCKUP=m +CONFIG_WW_MUTEX_SELFTEST=m +CONFIG_EARLY_PRINTK=y +CONFIG_TEST_LIST_SORT=m +CONFIG_TEST_MIN_HEAP=m +CONFIG_TEST_SORT=m +CONFIG_REED_SOLOMON_TEST=m +CONFIG_ATOMIC64_SELFTEST=m +CONFIG_ASYNC_RAID6_TEST=m +CONFIG_TEST_HEXDUMP=m +CONFIG_TEST_STRING_HELPERS=m +CONFIG_TEST_STRSCPY=m +CONFIG_TEST_KSTRTOX=m +CONFIG_TEST_PRINTF=m +CONFIG_TEST_BITMAP=m +CONFIG_TEST_BITFIELD=m +CONFIG_TEST_UUID=m +CONFIG_TEST_XARRAY=m +CONFIG_TEST_OVERFLOW=m +CONFIG_TEST_RHASHTABLE=m +CONFIG_TEST_HASH=m +CONFIG_TEST_IDA=m +CONFIG_TEST_BITOPS=m +CONFIG_TEST_VMALLOC=m +CONFIG_TEST_USER_COPY=m +CONFIG_TEST_BPF=m +CONFIG_TEST_BLACKHOLE_DEV=m +CONFIG_FIND_BIT_BENCHMARK=m +CONFIG_TEST_FIRMWARE=m +CONFIG_TEST_SYSCTL=m +CONFIG_TEST_UDELAY=m +CONFIG_TEST_STATIC_KEYS=m +CONFIG_TEST_KMOD=m +CONFIG_TEST_MEMCAT_P=m +CONFIG_TEST_STACKINIT=m +CONFIG_TEST_MEMINIT=m diff --git a/arch/m68k/configs/mvme147_defconfig b/arch/m68k/configs/mvme147_defconfig new file mode 100644 index 000000000..5568aa7d9 --- /dev/null +++ b/arch/m68k/configs/mvme147_defconfig @@ -0,0 +1,609 @@ +CONFIG_LOCALVERSION="-mvme147" +CONFIG_SYSVIPC=y +CONFIG_POSIX_MQUEUE=y +CONFIG_BSD_PROCESS_ACCT=y +CONFIG_BSD_PROCESS_ACCT_V3=y +CONFIG_LOG_BUF_SHIFT=16 +# CONFIG_UTS_NS is not set +# CONFIG_IPC_NS is not set +# CONFIG_PID_NS is not set +# CONFIG_NET_NS is not set +CONFIG_BLK_DEV_INITRD=y +CONFIG_CC_OPTIMIZE_FOR_SIZE=y +CONFIG_USERFAULTFD=y +CONFIG_SLAB=y +CONFIG_KEXEC=y +CONFIG_BOOTINFO_PROC=y +CONFIG_M68030=y +CONFIG_VME=y +CONFIG_MVME147=y +CONFIG_PROC_HARDWARE=y +CONFIG_MODULES=y +CONFIG_MODULE_UNLOAD=y +CONFIG_PARTITION_ADVANCED=y +CONFIG_AMIGA_PARTITION=y +CONFIG_ATARI_PARTITION=y +CONFIG_MAC_PARTITION=y +CONFIG_BSD_DISKLABEL=y +CONFIG_MINIX_SUBPARTITION=y +CONFIG_SOLARIS_X86_PARTITION=y +CONFIG_UNIXWARE_DISKLABEL=y +CONFIG_SUN_PARTITION=y +# CONFIG_EFI_PARTITION is not set +CONFIG_MQ_IOSCHED_DEADLINE=m +CONFIG_MQ_IOSCHED_KYBER=m +CONFIG_IOSCHED_BFQ=m +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +CONFIG_BINFMT_AOUT=m +CONFIG_BINFMT_MISC=m +# CONFIG_COMPACTION is not set +CONFIG_CLEANCACHE=y +CONFIG_ZPOOL=m +CONFIG_NET=y +CONFIG_PACKET=y +CONFIG_PACKET_DIAG=m +CONFIG_UNIX=y +CONFIG_UNIX_DIAG=m +CONFIG_TLS=m +CONFIG_XFRM_MIGRATE=y +CONFIG_NET_KEY=y +CONFIG_XDP_SOCKETS=y +CONFIG_XDP_SOCKETS_DIAG=m +CONFIG_INET=y +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +CONFIG_IP_PNP_BOOTP=y +CONFIG_IP_PNP_RARP=y +CONFIG_NET_IPIP=m +CONFIG_NET_IPGRE_DEMUX=m +CONFIG_NET_IPGRE=m +CONFIG_NET_IPVTI=m +CONFIG_NET_FOU_IP_TUNNELS=y +CONFIG_INET_AH=m +CONFIG_INET_ESP=m +CONFIG_INET_ESP_OFFLOAD=m +CONFIG_INET_IPCOMP=m +CONFIG_INET_DIAG=m +CONFIG_INET_UDP_DIAG=m +CONFIG_INET_RAW_DIAG=m +CONFIG_IPV6=m +CONFIG_IPV6_ROUTER_PREF=y +CONFIG_INET6_AH=m +CONFIG_INET6_ESP=m +CONFIG_INET6_ESP_OFFLOAD=m +CONFIG_INET6_IPCOMP=m +CONFIG_IPV6_ILA=m +CONFIG_IPV6_VTI=m +CONFIG_IPV6_GRE=m +CONFIG_NETFILTER=y +CONFIG_NF_CONNTRACK=m +CONFIG_NF_LOG_NETDEV=m +CONFIG_NF_CONNTRACK_ZONES=y +# CONFIG_NF_CONNTRACK_PROCFS is not set +# CONFIG_NF_CT_PROTO_DCCP is not set +CONFIG_NF_CONNTRACK_AMANDA=m +CONFIG_NF_CONNTRACK_FTP=m +CONFIG_NF_CONNTRACK_H323=m +CONFIG_NF_CONNTRACK_IRC=m +CONFIG_NF_CONNTRACK_NETBIOS_NS=m +CONFIG_NF_CONNTRACK_SNMP=m +CONFIG_NF_CONNTRACK_PPTP=m +CONFIG_NF_CONNTRACK_SANE=m +CONFIG_NF_CONNTRACK_SIP=m +CONFIG_NF_CONNTRACK_TFTP=m +CONFIG_NF_TABLES=m +CONFIG_NF_TABLES_INET=y +CONFIG_NF_TABLES_NETDEV=y +CONFIG_NFT_NUMGEN=m +CONFIG_NFT_CT=m +CONFIG_NFT_FLOW_OFFLOAD=m +CONFIG_NFT_COUNTER=m +CONFIG_NFT_CONNLIMIT=m +CONFIG_NFT_LOG=m +CONFIG_NFT_LIMIT=m +CONFIG_NFT_MASQ=m +CONFIG_NFT_REDIR=m +CONFIG_NFT_NAT=m +CONFIG_NFT_TUNNEL=m +CONFIG_NFT_OBJREF=m +CONFIG_NFT_QUEUE=m +CONFIG_NFT_QUOTA=m +CONFIG_NFT_REJECT=m +CONFIG_NFT_COMPAT=m +CONFIG_NFT_HASH=m +CONFIG_NFT_FIB_INET=m +CONFIG_NFT_XFRM=m +CONFIG_NFT_SOCKET=m +CONFIG_NFT_OSF=m +CONFIG_NFT_TPROXY=m +CONFIG_NFT_SYNPROXY=m +CONFIG_NFT_DUP_NETDEV=m +CONFIG_NFT_FWD_NETDEV=m +CONFIG_NFT_FIB_NETDEV=m +CONFIG_NF_FLOW_TABLE_INET=m +CONFIG_NF_FLOW_TABLE=m +CONFIG_NETFILTER_XT_SET=m +CONFIG_NETFILTER_XT_TARGET_CHECKSUM=m +CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m +CONFIG_NETFILTER_XT_TARGET_CONNMARK=m +CONFIG_NETFILTER_XT_TARGET_DSCP=m +CONFIG_NETFILTER_XT_TARGET_HMARK=m +CONFIG_NETFILTER_XT_TARGET_IDLETIMER=m +CONFIG_NETFILTER_XT_TARGET_LOG=m +CONFIG_NETFILTER_XT_TARGET_MARK=m +CONFIG_NETFILTER_XT_TARGET_NFLOG=m +CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m +CONFIG_NETFILTER_XT_TARGET_NOTRACK=m +CONFIG_NETFILTER_XT_TARGET_TEE=m +CONFIG_NETFILTER_XT_TARGET_TPROXY=m +CONFIG_NETFILTER_XT_TARGET_TRACE=m +CONFIG_NETFILTER_XT_TARGET_TCPMSS=m +CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP=m +CONFIG_NETFILTER_XT_MATCH_ADDRTYPE=m +CONFIG_NETFILTER_XT_MATCH_BPF=m +CONFIG_NETFILTER_XT_MATCH_CLUSTER=m +CONFIG_NETFILTER_XT_MATCH_COMMENT=m +CONFIG_NETFILTER_XT_MATCH_CONNBYTES=m +CONFIG_NETFILTER_XT_MATCH_CONNLABEL=m +CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=m +CONFIG_NETFILTER_XT_MATCH_CONNMARK=m +CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m +CONFIG_NETFILTER_XT_MATCH_DEVGROUP=m +CONFIG_NETFILTER_XT_MATCH_DSCP=m +CONFIG_NETFILTER_XT_MATCH_ESP=m +CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=m +CONFIG_NETFILTER_XT_MATCH_HELPER=m +CONFIG_NETFILTER_XT_MATCH_IPCOMP=m +CONFIG_NETFILTER_XT_MATCH_IPRANGE=m +CONFIG_NETFILTER_XT_MATCH_LENGTH=m +CONFIG_NETFILTER_XT_MATCH_LIMIT=m +CONFIG_NETFILTER_XT_MATCH_MAC=m +CONFIG_NETFILTER_XT_MATCH_MARK=m +CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m +CONFIG_NETFILTER_XT_MATCH_NFACCT=m +CONFIG_NETFILTER_XT_MATCH_OSF=m +CONFIG_NETFILTER_XT_MATCH_OWNER=m +CONFIG_NETFILTER_XT_MATCH_POLICY=m +CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m +CONFIG_NETFILTER_XT_MATCH_QUOTA=m +CONFIG_NETFILTER_XT_MATCH_RATEEST=m +CONFIG_NETFILTER_XT_MATCH_REALM=m +CONFIG_NETFILTER_XT_MATCH_RECENT=m +CONFIG_NETFILTER_XT_MATCH_SOCKET=m +CONFIG_NETFILTER_XT_MATCH_STATE=m +CONFIG_NETFILTER_XT_MATCH_STATISTIC=m +CONFIG_NETFILTER_XT_MATCH_STRING=m +CONFIG_NETFILTER_XT_MATCH_TCPMSS=m +CONFIG_NETFILTER_XT_MATCH_TIME=m +CONFIG_NETFILTER_XT_MATCH_U32=m +CONFIG_IP_SET=m +CONFIG_IP_SET_BITMAP_IP=m +CONFIG_IP_SET_BITMAP_IPMAC=m +CONFIG_IP_SET_BITMAP_PORT=m +CONFIG_IP_SET_HASH_IP=m +CONFIG_IP_SET_HASH_IPMARK=m +CONFIG_IP_SET_HASH_IPPORT=m +CONFIG_IP_SET_HASH_IPPORTIP=m +CONFIG_IP_SET_HASH_IPPORTNET=m +CONFIG_IP_SET_HASH_IPMAC=m +CONFIG_IP_SET_HASH_MAC=m +CONFIG_IP_SET_HASH_NETPORTNET=m +CONFIG_IP_SET_HASH_NET=m +CONFIG_IP_SET_HASH_NETNET=m +CONFIG_IP_SET_HASH_NETPORT=m +CONFIG_IP_SET_HASH_NETIFACE=m +CONFIG_IP_SET_LIST_SET=m +CONFIG_NFT_DUP_IPV4=m +CONFIG_NFT_FIB_IPV4=m +CONFIG_NF_TABLES_ARP=y +CONFIG_NF_FLOW_TABLE_IPV4=m +CONFIG_NF_LOG_ARP=m +CONFIG_IP_NF_IPTABLES=m +CONFIG_IP_NF_MATCH_AH=m +CONFIG_IP_NF_MATCH_ECN=m +CONFIG_IP_NF_MATCH_RPFILTER=m +CONFIG_IP_NF_MATCH_TTL=m +CONFIG_IP_NF_FILTER=m +CONFIG_IP_NF_TARGET_REJECT=m +CONFIG_IP_NF_TARGET_SYNPROXY=m +CONFIG_IP_NF_NAT=m +CONFIG_IP_NF_TARGET_MASQUERADE=m +CONFIG_IP_NF_TARGET_NETMAP=m +CONFIG_IP_NF_TARGET_REDIRECT=m +CONFIG_IP_NF_MANGLE=m +CONFIG_IP_NF_TARGET_CLUSTERIP=m +CONFIG_IP_NF_TARGET_ECN=m +CONFIG_IP_NF_TARGET_TTL=m +CONFIG_IP_NF_RAW=m +CONFIG_IP_NF_ARPTABLES=m +CONFIG_IP_NF_ARPFILTER=m +CONFIG_IP_NF_ARP_MANGLE=m +CONFIG_NFT_DUP_IPV6=m +CONFIG_NFT_FIB_IPV6=m +CONFIG_NF_FLOW_TABLE_IPV6=m +CONFIG_IP6_NF_IPTABLES=m +CONFIG_IP6_NF_MATCH_AH=m +CONFIG_IP6_NF_MATCH_EUI64=m +CONFIG_IP6_NF_MATCH_FRAG=m +CONFIG_IP6_NF_MATCH_OPTS=m +CONFIG_IP6_NF_MATCH_HL=m +CONFIG_IP6_NF_MATCH_IPV6HEADER=m +CONFIG_IP6_NF_MATCH_MH=m +CONFIG_IP6_NF_MATCH_RPFILTER=m +CONFIG_IP6_NF_MATCH_RT=m +CONFIG_IP6_NF_MATCH_SRH=m +CONFIG_IP6_NF_TARGET_HL=m +CONFIG_IP6_NF_FILTER=m +CONFIG_IP6_NF_TARGET_REJECT=m +CONFIG_IP6_NF_TARGET_SYNPROXY=m +CONFIG_IP6_NF_MANGLE=m +CONFIG_IP6_NF_RAW=m +CONFIG_IP6_NF_NAT=m +CONFIG_IP6_NF_TARGET_MASQUERADE=m +CONFIG_IP6_NF_TARGET_NPT=m +CONFIG_NF_TABLES_BRIDGE=m +CONFIG_NFT_BRIDGE_META=m +CONFIG_NFT_BRIDGE_REJECT=m +CONFIG_NF_LOG_BRIDGE=m +CONFIG_NF_CONNTRACK_BRIDGE=m +CONFIG_BRIDGE_NF_EBTABLES=m +CONFIG_BRIDGE_EBT_BROUTE=m +CONFIG_BRIDGE_EBT_T_FILTER=m +CONFIG_BRIDGE_EBT_T_NAT=m +CONFIG_BRIDGE_EBT_802_3=m +CONFIG_BRIDGE_EBT_AMONG=m +CONFIG_BRIDGE_EBT_ARP=m +CONFIG_BRIDGE_EBT_IP=m +CONFIG_BRIDGE_EBT_IP6=m +CONFIG_BRIDGE_EBT_LIMIT=m +CONFIG_BRIDGE_EBT_MARK=m +CONFIG_BRIDGE_EBT_PKTTYPE=m +CONFIG_BRIDGE_EBT_STP=m +CONFIG_BRIDGE_EBT_VLAN=m +CONFIG_BRIDGE_EBT_ARPREPLY=m +CONFIG_BRIDGE_EBT_DNAT=m +CONFIG_BRIDGE_EBT_MARK_T=m +CONFIG_BRIDGE_EBT_REDIRECT=m +CONFIG_BRIDGE_EBT_SNAT=m +CONFIG_BRIDGE_EBT_LOG=m +CONFIG_BRIDGE_EBT_NFLOG=m +CONFIG_IP_DCCP=m +# CONFIG_IP_DCCP_CCID3 is not set +CONFIG_SCTP_COOKIE_HMAC_SHA1=y +CONFIG_RDS=m +CONFIG_RDS_TCP=m +CONFIG_L2TP=m +CONFIG_BRIDGE=m +CONFIG_ATALK=m +CONFIG_6LOWPAN=m +CONFIG_6LOWPAN_GHC_EXT_HDR_HOP=m +CONFIG_6LOWPAN_GHC_UDP=m +CONFIG_6LOWPAN_GHC_ICMPV6=m +CONFIG_6LOWPAN_GHC_EXT_HDR_DEST=m +CONFIG_6LOWPAN_GHC_EXT_HDR_FRAG=m +CONFIG_6LOWPAN_GHC_EXT_HDR_ROUTE=m +CONFIG_DNS_RESOLVER=y +CONFIG_BATMAN_ADV=m +# CONFIG_BATMAN_ADV_BATMAN_V is not set +CONFIG_BATMAN_ADV_NC=y +CONFIG_NETLINK_DIAG=m +CONFIG_MPLS=y +CONFIG_NET_MPLS_GSO=m +CONFIG_MPLS_ROUTING=m +CONFIG_MPLS_IPTUNNEL=m +CONFIG_NET_NSH=m +CONFIG_AF_KCM=m +# CONFIG_WIRELESS is not set +CONFIG_PSAMPLE=m +CONFIG_NET_IFE=m +CONFIG_DEVTMPFS=y +CONFIG_DEVTMPFS_MOUNT=y +CONFIG_TEST_ASYNC_DRIVER_PROBE=m +CONFIG_CONNECTOR=m +CONFIG_BLK_DEV_LOOP=y +CONFIG_BLK_DEV_CRYPTOLOOP=m +CONFIG_BLK_DEV_DRBD=m +CONFIG_BLK_DEV_NBD=m +CONFIG_BLK_DEV_RAM=y +CONFIG_CDROM_PKTCDVD=m +CONFIG_ATA_OVER_ETH=m +CONFIG_DUMMY_IRQ=m +CONFIG_RAID_ATTRS=m +CONFIG_SCSI=y +CONFIG_BLK_DEV_SD=y +CONFIG_CHR_DEV_ST=m +CONFIG_BLK_DEV_SR=y +CONFIG_CHR_DEV_SG=m +CONFIG_SCSI_CONSTANTS=y +CONFIG_SCSI_SAS_ATTRS=m +CONFIG_ISCSI_TCP=m +CONFIG_ISCSI_BOOT_SYSFS=m +CONFIG_MVME147_SCSI=y +CONFIG_MD=y +CONFIG_MD_LINEAR=m +CONFIG_BLK_DEV_DM=m +CONFIG_DM_UNSTRIPED=m +CONFIG_DM_CRYPT=m +CONFIG_DM_SNAPSHOT=m +CONFIG_DM_THIN_PROVISIONING=m +CONFIG_DM_WRITECACHE=m +CONFIG_DM_ERA=m +CONFIG_DM_CLONE=m +CONFIG_DM_MIRROR=m +CONFIG_DM_RAID=m +CONFIG_DM_ZERO=m +CONFIG_DM_MULTIPATH=m +CONFIG_DM_UEVENT=y +CONFIG_DM_LOG_WRITES=m +CONFIG_DM_INTEGRITY=m +CONFIG_TARGET_CORE=m +CONFIG_TCM_IBLOCK=m +CONFIG_TCM_FILEIO=m +CONFIG_TCM_PSCSI=m +CONFIG_NETDEVICES=y +CONFIG_DUMMY=m +CONFIG_WIREGUARD=m +CONFIG_EQUALIZER=m +CONFIG_NET_TEAM=m +CONFIG_NET_TEAM_MODE_BROADCAST=m +CONFIG_NET_TEAM_MODE_ROUNDROBIN=m +CONFIG_NET_TEAM_MODE_RANDOM=m +CONFIG_NET_TEAM_MODE_ACTIVEBACKUP=m +CONFIG_NET_TEAM_MODE_LOADBALANCE=m +CONFIG_MACVLAN=m +CONFIG_MACVTAP=m +CONFIG_IPVLAN=m +CONFIG_IPVTAP=m +CONFIG_VXLAN=m +CONFIG_GENEVE=m +CONFIG_BAREUDP=m +CONFIG_GTP=m +CONFIG_MACSEC=m +CONFIG_NETCONSOLE=m +CONFIG_NETCONSOLE_DYNAMIC=y +CONFIG_VETH=m +CONFIG_MVME147_NET=y +CONFIG_PPP=m +CONFIG_PPP_BSDCOMP=m +CONFIG_PPP_DEFLATE=m +CONFIG_PPP_FILTER=y +CONFIG_PPP_MPPE=m +CONFIG_PPPOE=m +CONFIG_PPTP=m +CONFIG_PPPOL2TP=m +CONFIG_PPP_ASYNC=m +CONFIG_PPP_SYNC_TTY=m +CONFIG_SLIP=m +CONFIG_SLIP_COMPRESSED=y +CONFIG_SLIP_SMART=y +CONFIG_SLIP_MODE_SLIP6=y +# CONFIG_WLAN is not set +CONFIG_INPUT_EVDEV=m +# CONFIG_KEYBOARD_ATKBD is not set +# CONFIG_MOUSE_PS2 is not set +# CONFIG_SERIO is not set +CONFIG_VT_HW_CONSOLE_BINDING=y +# CONFIG_LEGACY_PTYS is not set +# CONFIG_HW_RANDOM is not set +CONFIG_NTP_PPS=y +CONFIG_PPS_CLIENT_LDISC=m +CONFIG_PTP_1588_CLOCK=m +# CONFIG_HWMON is not set +CONFIG_HID=m +CONFIG_HIDRAW=y +CONFIG_UHID=m +# CONFIG_HID_GENERIC is not set +# CONFIG_HID_ITE is not set +# CONFIG_HID_REDRAGON is not set +# CONFIG_USB_SUPPORT is not set +CONFIG_RTC_CLASS=y +# CONFIG_RTC_NVMEM is not set +CONFIG_RTC_DRV_GENERIC=m +# CONFIG_VIRTIO_MENU is not set +# CONFIG_VHOST_MENU is not set +# CONFIG_IOMMU_SUPPORT is not set +CONFIG_DAX=m +CONFIG_EXT4_FS=y +CONFIG_REISERFS_FS=m +CONFIG_JFS_FS=m +CONFIG_OCFS2_FS=m +# CONFIG_OCFS2_DEBUG_MASKLOG is not set +CONFIG_FANOTIFY=y +CONFIG_QUOTA_NETLINK_INTERFACE=y +# CONFIG_PRINT_QUOTA_WARNING is not set +CONFIG_AUTOFS_FS=m +CONFIG_FUSE_FS=m +CONFIG_CUSE=m +CONFIG_OVERLAY_FS=m +CONFIG_ISO9660_FS=y +CONFIG_JOLIET=y +CONFIG_ZISOFS=y +CONFIG_UDF_FS=m +CONFIG_MSDOS_FS=m +CONFIG_VFAT_FS=m +CONFIG_EXFAT_FS=m +CONFIG_PROC_KCORE=y +CONFIG_PROC_CHILDREN=y +CONFIG_TMPFS=y +CONFIG_ORANGEFS_FS=m +CONFIG_AFFS_FS=m +CONFIG_ECRYPT_FS=m +CONFIG_ECRYPT_FS_MESSAGING=y +CONFIG_HFS_FS=m +CONFIG_HFSPLUS_FS=m +CONFIG_CRAMFS=m +CONFIG_SQUASHFS=m +CONFIG_SQUASHFS_LZ4=y +CONFIG_SQUASHFS_LZO=y +CONFIG_MINIX_FS=m +CONFIG_OMFS_FS=m +CONFIG_HPFS_FS=m +CONFIG_QNX4FS_FS=m +CONFIG_QNX6FS_FS=m +CONFIG_SYSV_FS=m +CONFIG_UFS_FS=m +CONFIG_EROFS_FS=m +CONFIG_NFS_FS=y +CONFIG_NFS_V4=m +CONFIG_NFS_SWAP=y +CONFIG_ROOT_NFS=y +CONFIG_NFSD=m +CONFIG_NFSD_V3=y +CONFIG_CIFS=m +# CONFIG_CIFS_DEBUG is not set +CONFIG_CODA_FS=m +CONFIG_NLS_CODEPAGE_437=y +CONFIG_NLS_CODEPAGE_737=m +CONFIG_NLS_CODEPAGE_775=m +CONFIG_NLS_CODEPAGE_850=m +CONFIG_NLS_CODEPAGE_852=m +CONFIG_NLS_CODEPAGE_855=m +CONFIG_NLS_CODEPAGE_857=m +CONFIG_NLS_CODEPAGE_860=m +CONFIG_NLS_CODEPAGE_861=m +CONFIG_NLS_CODEPAGE_862=m +CONFIG_NLS_CODEPAGE_863=m +CONFIG_NLS_CODEPAGE_864=m +CONFIG_NLS_CODEPAGE_865=m +CONFIG_NLS_CODEPAGE_866=m +CONFIG_NLS_CODEPAGE_869=m +CONFIG_NLS_CODEPAGE_936=m +CONFIG_NLS_CODEPAGE_950=m +CONFIG_NLS_CODEPAGE_932=m +CONFIG_NLS_CODEPAGE_949=m +CONFIG_NLS_CODEPAGE_874=m +CONFIG_NLS_ISO8859_8=m +CONFIG_NLS_CODEPAGE_1250=m +CONFIG_NLS_CODEPAGE_1251=m +CONFIG_NLS_ASCII=m +CONFIG_NLS_ISO8859_1=y +CONFIG_NLS_ISO8859_2=m +CONFIG_NLS_ISO8859_3=m +CONFIG_NLS_ISO8859_4=m +CONFIG_NLS_ISO8859_5=m +CONFIG_NLS_ISO8859_6=m +CONFIG_NLS_ISO8859_7=m +CONFIG_NLS_ISO8859_9=m +CONFIG_NLS_ISO8859_13=m +CONFIG_NLS_ISO8859_14=m +CONFIG_NLS_ISO8859_15=m +CONFIG_NLS_KOI8_R=m +CONFIG_NLS_KOI8_U=m +CONFIG_NLS_MAC_ROMAN=m +CONFIG_NLS_MAC_CELTIC=m +CONFIG_NLS_MAC_CENTEURO=m +CONFIG_NLS_MAC_CROATIAN=m +CONFIG_NLS_MAC_CYRILLIC=m +CONFIG_NLS_MAC_GAELIC=m +CONFIG_NLS_MAC_GREEK=m +CONFIG_NLS_MAC_ICELAND=m +CONFIG_NLS_MAC_INUIT=m +CONFIG_NLS_MAC_ROMANIAN=m +CONFIG_NLS_MAC_TURKISH=m +CONFIG_DLM=m +CONFIG_ENCRYPTED_KEYS=m +CONFIG_HARDENED_USERCOPY=y +CONFIG_CRYPTO_MANAGER=y +CONFIG_CRYPTO_USER=m +CONFIG_CRYPTO_CRYPTD=m +CONFIG_CRYPTO_TEST=m +CONFIG_CRYPTO_RSA=m +CONFIG_CRYPTO_DH=m +CONFIG_CRYPTO_ECDH=m +CONFIG_CRYPTO_ECRDSA=m +CONFIG_CRYPTO_CURVE25519=m +CONFIG_CRYPTO_CHACHA20POLY1305=m +CONFIG_CRYPTO_AEGIS128=m +CONFIG_CRYPTO_CFB=m +CONFIG_CRYPTO_CTS=m +CONFIG_CRYPTO_LRW=m +CONFIG_CRYPTO_OFB=m +CONFIG_CRYPTO_PCBC=m +CONFIG_CRYPTO_XTS=m +CONFIG_CRYPTO_KEYWRAP=m +CONFIG_CRYPTO_ADIANTUM=m +CONFIG_CRYPTO_XCBC=m +CONFIG_CRYPTO_VMAC=m +CONFIG_CRYPTO_BLAKE2S=m +CONFIG_CRYPTO_MICHAEL_MIC=m +CONFIG_CRYPTO_RMD128=m +CONFIG_CRYPTO_RMD160=m +CONFIG_CRYPTO_RMD256=m +CONFIG_CRYPTO_RMD320=m +CONFIG_CRYPTO_SHA3=m +CONFIG_CRYPTO_SM3=m +CONFIG_CRYPTO_TGR192=m +CONFIG_CRYPTO_WP512=m +CONFIG_CRYPTO_AES=y +CONFIG_CRYPTO_AES_TI=m +CONFIG_CRYPTO_ANUBIS=m +CONFIG_CRYPTO_ARC4=m +CONFIG_CRYPTO_BLOWFISH=m +CONFIG_CRYPTO_CAMELLIA=m +CONFIG_CRYPTO_CAST5=m +CONFIG_CRYPTO_CAST6=m +CONFIG_CRYPTO_DES=m +CONFIG_CRYPTO_FCRYPT=m +CONFIG_CRYPTO_KHAZAD=m +CONFIG_CRYPTO_SALSA20=m +CONFIG_CRYPTO_SEED=m +CONFIG_CRYPTO_SERPENT=m +CONFIG_CRYPTO_SM4=m +CONFIG_CRYPTO_TEA=m +CONFIG_CRYPTO_TWOFISH=m +CONFIG_CRYPTO_LZO=m +CONFIG_CRYPTO_842=m +CONFIG_CRYPTO_LZ4=m +CONFIG_CRYPTO_LZ4HC=m +CONFIG_CRYPTO_ZSTD=m +CONFIG_CRYPTO_ANSI_CPRNG=m +CONFIG_CRYPTO_DRBG_HASH=y +CONFIG_CRYPTO_DRBG_CTR=y +CONFIG_CRYPTO_USER_API_HASH=m +CONFIG_CRYPTO_USER_API_SKCIPHER=m +CONFIG_CRYPTO_USER_API_RNG=m +CONFIG_CRYPTO_USER_API_AEAD=m +# CONFIG_CRYPTO_HW is not set +CONFIG_PRIME_NUMBERS=m +CONFIG_CRC32_SELFTEST=m +CONFIG_CRC64=m +CONFIG_XZ_DEC_TEST=m +CONFIG_STRING_SELFTEST=m +# CONFIG_SECTION_MISMATCH_WARN_ONLY is not set +CONFIG_MAGIC_SYSRQ=y +CONFIG_TEST_LOCKUP=m +CONFIG_WW_MUTEX_SELFTEST=m +CONFIG_EARLY_PRINTK=y +CONFIG_TEST_LIST_SORT=m +CONFIG_TEST_MIN_HEAP=m +CONFIG_TEST_SORT=m +CONFIG_REED_SOLOMON_TEST=m +CONFIG_ATOMIC64_SELFTEST=m +CONFIG_ASYNC_RAID6_TEST=m +CONFIG_TEST_HEXDUMP=m +CONFIG_TEST_STRING_HELPERS=m +CONFIG_TEST_STRSCPY=m +CONFIG_TEST_KSTRTOX=m +CONFIG_TEST_PRINTF=m +CONFIG_TEST_BITMAP=m +CONFIG_TEST_BITFIELD=m +CONFIG_TEST_UUID=m +CONFIG_TEST_XARRAY=m +CONFIG_TEST_OVERFLOW=m +CONFIG_TEST_RHASHTABLE=m +CONFIG_TEST_HASH=m +CONFIG_TEST_IDA=m +CONFIG_TEST_BITOPS=m +CONFIG_TEST_VMALLOC=m +CONFIG_TEST_USER_COPY=m +CONFIG_TEST_BPF=m +CONFIG_TEST_BLACKHOLE_DEV=m +CONFIG_FIND_BIT_BENCHMARK=m +CONFIG_TEST_FIRMWARE=m +CONFIG_TEST_SYSCTL=m +CONFIG_TEST_UDELAY=m +CONFIG_TEST_STATIC_KEYS=m +CONFIG_TEST_KMOD=m +CONFIG_TEST_MEMCAT_P=m +CONFIG_TEST_STACKINIT=m +CONFIG_TEST_MEMINIT=m diff --git a/arch/m68k/configs/mvme16x_defconfig b/arch/m68k/configs/mvme16x_defconfig new file mode 100644 index 000000000..5b1e72ce5 --- /dev/null +++ b/arch/m68k/configs/mvme16x_defconfig @@ -0,0 +1,610 @@ +CONFIG_LOCALVERSION="-mvme16x" +CONFIG_SYSVIPC=y +CONFIG_POSIX_MQUEUE=y +CONFIG_BSD_PROCESS_ACCT=y +CONFIG_BSD_PROCESS_ACCT_V3=y +CONFIG_LOG_BUF_SHIFT=16 +# CONFIG_UTS_NS is not set +# CONFIG_IPC_NS is not set +# CONFIG_PID_NS is not set +# CONFIG_NET_NS is not set +CONFIG_BLK_DEV_INITRD=y +CONFIG_CC_OPTIMIZE_FOR_SIZE=y +CONFIG_USERFAULTFD=y +CONFIG_SLAB=y +CONFIG_KEXEC=y +CONFIG_BOOTINFO_PROC=y +CONFIG_M68040=y +CONFIG_M68060=y +CONFIG_VME=y +CONFIG_MVME16x=y +CONFIG_PROC_HARDWARE=y +CONFIG_MODULES=y +CONFIG_MODULE_UNLOAD=y +CONFIG_PARTITION_ADVANCED=y +CONFIG_AMIGA_PARTITION=y +CONFIG_ATARI_PARTITION=y +CONFIG_MAC_PARTITION=y +CONFIG_BSD_DISKLABEL=y +CONFIG_MINIX_SUBPARTITION=y +CONFIG_SOLARIS_X86_PARTITION=y +CONFIG_UNIXWARE_DISKLABEL=y +CONFIG_SUN_PARTITION=y +# CONFIG_EFI_PARTITION is not set +CONFIG_MQ_IOSCHED_DEADLINE=m +CONFIG_MQ_IOSCHED_KYBER=m +CONFIG_IOSCHED_BFQ=m +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +CONFIG_BINFMT_AOUT=m +CONFIG_BINFMT_MISC=m +# CONFIG_COMPACTION is not set +CONFIG_CLEANCACHE=y +CONFIG_ZPOOL=m +CONFIG_NET=y +CONFIG_PACKET=y +CONFIG_PACKET_DIAG=m +CONFIG_UNIX=y +CONFIG_UNIX_DIAG=m +CONFIG_TLS=m +CONFIG_XFRM_MIGRATE=y +CONFIG_NET_KEY=y +CONFIG_XDP_SOCKETS=y +CONFIG_XDP_SOCKETS_DIAG=m +CONFIG_INET=y +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +CONFIG_IP_PNP_BOOTP=y +CONFIG_IP_PNP_RARP=y +CONFIG_NET_IPIP=m +CONFIG_NET_IPGRE_DEMUX=m +CONFIG_NET_IPGRE=m +CONFIG_NET_IPVTI=m +CONFIG_NET_FOU_IP_TUNNELS=y +CONFIG_INET_AH=m +CONFIG_INET_ESP=m +CONFIG_INET_ESP_OFFLOAD=m +CONFIG_INET_IPCOMP=m +CONFIG_INET_DIAG=m +CONFIG_INET_UDP_DIAG=m +CONFIG_INET_RAW_DIAG=m +CONFIG_IPV6=m +CONFIG_IPV6_ROUTER_PREF=y +CONFIG_INET6_AH=m +CONFIG_INET6_ESP=m +CONFIG_INET6_ESP_OFFLOAD=m +CONFIG_INET6_IPCOMP=m +CONFIG_IPV6_ILA=m +CONFIG_IPV6_VTI=m +CONFIG_IPV6_GRE=m +CONFIG_NETFILTER=y +CONFIG_NF_CONNTRACK=m +CONFIG_NF_LOG_NETDEV=m +CONFIG_NF_CONNTRACK_ZONES=y +# CONFIG_NF_CONNTRACK_PROCFS is not set +# CONFIG_NF_CT_PROTO_DCCP is not set +CONFIG_NF_CONNTRACK_AMANDA=m +CONFIG_NF_CONNTRACK_FTP=m +CONFIG_NF_CONNTRACK_H323=m +CONFIG_NF_CONNTRACK_IRC=m +CONFIG_NF_CONNTRACK_NETBIOS_NS=m +CONFIG_NF_CONNTRACK_SNMP=m +CONFIG_NF_CONNTRACK_PPTP=m +CONFIG_NF_CONNTRACK_SANE=m +CONFIG_NF_CONNTRACK_SIP=m +CONFIG_NF_CONNTRACK_TFTP=m +CONFIG_NF_TABLES=m +CONFIG_NF_TABLES_INET=y +CONFIG_NF_TABLES_NETDEV=y +CONFIG_NFT_NUMGEN=m +CONFIG_NFT_CT=m +CONFIG_NFT_FLOW_OFFLOAD=m +CONFIG_NFT_COUNTER=m +CONFIG_NFT_CONNLIMIT=m +CONFIG_NFT_LOG=m +CONFIG_NFT_LIMIT=m +CONFIG_NFT_MASQ=m +CONFIG_NFT_REDIR=m +CONFIG_NFT_NAT=m +CONFIG_NFT_TUNNEL=m +CONFIG_NFT_OBJREF=m +CONFIG_NFT_QUEUE=m +CONFIG_NFT_QUOTA=m +CONFIG_NFT_REJECT=m +CONFIG_NFT_COMPAT=m +CONFIG_NFT_HASH=m +CONFIG_NFT_FIB_INET=m +CONFIG_NFT_XFRM=m +CONFIG_NFT_SOCKET=m +CONFIG_NFT_OSF=m +CONFIG_NFT_TPROXY=m +CONFIG_NFT_SYNPROXY=m +CONFIG_NFT_DUP_NETDEV=m +CONFIG_NFT_FWD_NETDEV=m +CONFIG_NFT_FIB_NETDEV=m +CONFIG_NF_FLOW_TABLE_INET=m +CONFIG_NF_FLOW_TABLE=m +CONFIG_NETFILTER_XT_SET=m +CONFIG_NETFILTER_XT_TARGET_CHECKSUM=m +CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m +CONFIG_NETFILTER_XT_TARGET_CONNMARK=m +CONFIG_NETFILTER_XT_TARGET_DSCP=m +CONFIG_NETFILTER_XT_TARGET_HMARK=m +CONFIG_NETFILTER_XT_TARGET_IDLETIMER=m +CONFIG_NETFILTER_XT_TARGET_LOG=m +CONFIG_NETFILTER_XT_TARGET_MARK=m +CONFIG_NETFILTER_XT_TARGET_NFLOG=m +CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m +CONFIG_NETFILTER_XT_TARGET_NOTRACK=m +CONFIG_NETFILTER_XT_TARGET_TEE=m +CONFIG_NETFILTER_XT_TARGET_TPROXY=m +CONFIG_NETFILTER_XT_TARGET_TRACE=m +CONFIG_NETFILTER_XT_TARGET_TCPMSS=m +CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP=m +CONFIG_NETFILTER_XT_MATCH_ADDRTYPE=m +CONFIG_NETFILTER_XT_MATCH_BPF=m +CONFIG_NETFILTER_XT_MATCH_CLUSTER=m +CONFIG_NETFILTER_XT_MATCH_COMMENT=m +CONFIG_NETFILTER_XT_MATCH_CONNBYTES=m +CONFIG_NETFILTER_XT_MATCH_CONNLABEL=m +CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=m +CONFIG_NETFILTER_XT_MATCH_CONNMARK=m +CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m +CONFIG_NETFILTER_XT_MATCH_DEVGROUP=m +CONFIG_NETFILTER_XT_MATCH_DSCP=m +CONFIG_NETFILTER_XT_MATCH_ESP=m +CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=m +CONFIG_NETFILTER_XT_MATCH_HELPER=m +CONFIG_NETFILTER_XT_MATCH_IPCOMP=m +CONFIG_NETFILTER_XT_MATCH_IPRANGE=m +CONFIG_NETFILTER_XT_MATCH_LENGTH=m +CONFIG_NETFILTER_XT_MATCH_LIMIT=m +CONFIG_NETFILTER_XT_MATCH_MAC=m +CONFIG_NETFILTER_XT_MATCH_MARK=m +CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m +CONFIG_NETFILTER_XT_MATCH_NFACCT=m +CONFIG_NETFILTER_XT_MATCH_OSF=m +CONFIG_NETFILTER_XT_MATCH_OWNER=m +CONFIG_NETFILTER_XT_MATCH_POLICY=m +CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m +CONFIG_NETFILTER_XT_MATCH_QUOTA=m +CONFIG_NETFILTER_XT_MATCH_RATEEST=m +CONFIG_NETFILTER_XT_MATCH_REALM=m +CONFIG_NETFILTER_XT_MATCH_RECENT=m +CONFIG_NETFILTER_XT_MATCH_SOCKET=m +CONFIG_NETFILTER_XT_MATCH_STATE=m +CONFIG_NETFILTER_XT_MATCH_STATISTIC=m +CONFIG_NETFILTER_XT_MATCH_STRING=m +CONFIG_NETFILTER_XT_MATCH_TCPMSS=m +CONFIG_NETFILTER_XT_MATCH_TIME=m +CONFIG_NETFILTER_XT_MATCH_U32=m +CONFIG_IP_SET=m +CONFIG_IP_SET_BITMAP_IP=m +CONFIG_IP_SET_BITMAP_IPMAC=m +CONFIG_IP_SET_BITMAP_PORT=m +CONFIG_IP_SET_HASH_IP=m +CONFIG_IP_SET_HASH_IPMARK=m +CONFIG_IP_SET_HASH_IPPORT=m +CONFIG_IP_SET_HASH_IPPORTIP=m +CONFIG_IP_SET_HASH_IPPORTNET=m +CONFIG_IP_SET_HASH_IPMAC=m +CONFIG_IP_SET_HASH_MAC=m +CONFIG_IP_SET_HASH_NETPORTNET=m +CONFIG_IP_SET_HASH_NET=m +CONFIG_IP_SET_HASH_NETNET=m +CONFIG_IP_SET_HASH_NETPORT=m +CONFIG_IP_SET_HASH_NETIFACE=m +CONFIG_IP_SET_LIST_SET=m +CONFIG_NFT_DUP_IPV4=m +CONFIG_NFT_FIB_IPV4=m +CONFIG_NF_TABLES_ARP=y +CONFIG_NF_FLOW_TABLE_IPV4=m +CONFIG_NF_LOG_ARP=m +CONFIG_IP_NF_IPTABLES=m +CONFIG_IP_NF_MATCH_AH=m +CONFIG_IP_NF_MATCH_ECN=m +CONFIG_IP_NF_MATCH_RPFILTER=m +CONFIG_IP_NF_MATCH_TTL=m +CONFIG_IP_NF_FILTER=m +CONFIG_IP_NF_TARGET_REJECT=m +CONFIG_IP_NF_TARGET_SYNPROXY=m +CONFIG_IP_NF_NAT=m +CONFIG_IP_NF_TARGET_MASQUERADE=m +CONFIG_IP_NF_TARGET_NETMAP=m +CONFIG_IP_NF_TARGET_REDIRECT=m +CONFIG_IP_NF_MANGLE=m +CONFIG_IP_NF_TARGET_CLUSTERIP=m +CONFIG_IP_NF_TARGET_ECN=m +CONFIG_IP_NF_TARGET_TTL=m +CONFIG_IP_NF_RAW=m +CONFIG_IP_NF_ARPTABLES=m +CONFIG_IP_NF_ARPFILTER=m +CONFIG_IP_NF_ARP_MANGLE=m +CONFIG_NFT_DUP_IPV6=m +CONFIG_NFT_FIB_IPV6=m +CONFIG_NF_FLOW_TABLE_IPV6=m +CONFIG_IP6_NF_IPTABLES=m +CONFIG_IP6_NF_MATCH_AH=m +CONFIG_IP6_NF_MATCH_EUI64=m +CONFIG_IP6_NF_MATCH_FRAG=m +CONFIG_IP6_NF_MATCH_OPTS=m +CONFIG_IP6_NF_MATCH_HL=m +CONFIG_IP6_NF_MATCH_IPV6HEADER=m +CONFIG_IP6_NF_MATCH_MH=m +CONFIG_IP6_NF_MATCH_RPFILTER=m +CONFIG_IP6_NF_MATCH_RT=m +CONFIG_IP6_NF_MATCH_SRH=m +CONFIG_IP6_NF_TARGET_HL=m +CONFIG_IP6_NF_FILTER=m +CONFIG_IP6_NF_TARGET_REJECT=m +CONFIG_IP6_NF_TARGET_SYNPROXY=m +CONFIG_IP6_NF_MANGLE=m +CONFIG_IP6_NF_RAW=m +CONFIG_IP6_NF_NAT=m +CONFIG_IP6_NF_TARGET_MASQUERADE=m +CONFIG_IP6_NF_TARGET_NPT=m +CONFIG_NF_TABLES_BRIDGE=m +CONFIG_NFT_BRIDGE_META=m +CONFIG_NFT_BRIDGE_REJECT=m +CONFIG_NF_LOG_BRIDGE=m +CONFIG_NF_CONNTRACK_BRIDGE=m +CONFIG_BRIDGE_NF_EBTABLES=m +CONFIG_BRIDGE_EBT_BROUTE=m +CONFIG_BRIDGE_EBT_T_FILTER=m +CONFIG_BRIDGE_EBT_T_NAT=m +CONFIG_BRIDGE_EBT_802_3=m +CONFIG_BRIDGE_EBT_AMONG=m +CONFIG_BRIDGE_EBT_ARP=m +CONFIG_BRIDGE_EBT_IP=m +CONFIG_BRIDGE_EBT_IP6=m +CONFIG_BRIDGE_EBT_LIMIT=m +CONFIG_BRIDGE_EBT_MARK=m +CONFIG_BRIDGE_EBT_PKTTYPE=m +CONFIG_BRIDGE_EBT_STP=m +CONFIG_BRIDGE_EBT_VLAN=m +CONFIG_BRIDGE_EBT_ARPREPLY=m +CONFIG_BRIDGE_EBT_DNAT=m +CONFIG_BRIDGE_EBT_MARK_T=m +CONFIG_BRIDGE_EBT_REDIRECT=m +CONFIG_BRIDGE_EBT_SNAT=m +CONFIG_BRIDGE_EBT_LOG=m +CONFIG_BRIDGE_EBT_NFLOG=m +CONFIG_IP_DCCP=m +# CONFIG_IP_DCCP_CCID3 is not set +CONFIG_SCTP_COOKIE_HMAC_SHA1=y +CONFIG_RDS=m +CONFIG_RDS_TCP=m +CONFIG_L2TP=m +CONFIG_BRIDGE=m +CONFIG_ATALK=m +CONFIG_6LOWPAN=m +CONFIG_6LOWPAN_GHC_EXT_HDR_HOP=m +CONFIG_6LOWPAN_GHC_UDP=m +CONFIG_6LOWPAN_GHC_ICMPV6=m +CONFIG_6LOWPAN_GHC_EXT_HDR_DEST=m +CONFIG_6LOWPAN_GHC_EXT_HDR_FRAG=m +CONFIG_6LOWPAN_GHC_EXT_HDR_ROUTE=m +CONFIG_DNS_RESOLVER=y +CONFIG_BATMAN_ADV=m +# CONFIG_BATMAN_ADV_BATMAN_V is not set +CONFIG_BATMAN_ADV_NC=y +CONFIG_NETLINK_DIAG=m +CONFIG_MPLS=y +CONFIG_NET_MPLS_GSO=m +CONFIG_MPLS_ROUTING=m +CONFIG_MPLS_IPTUNNEL=m +CONFIG_NET_NSH=m +CONFIG_AF_KCM=m +# CONFIG_WIRELESS is not set +CONFIG_PSAMPLE=m +CONFIG_NET_IFE=m +CONFIG_DEVTMPFS=y +CONFIG_DEVTMPFS_MOUNT=y +CONFIG_TEST_ASYNC_DRIVER_PROBE=m +CONFIG_CONNECTOR=m +CONFIG_BLK_DEV_LOOP=y +CONFIG_BLK_DEV_CRYPTOLOOP=m +CONFIG_BLK_DEV_DRBD=m +CONFIG_BLK_DEV_NBD=m +CONFIG_BLK_DEV_RAM=y +CONFIG_CDROM_PKTCDVD=m +CONFIG_ATA_OVER_ETH=m +CONFIG_DUMMY_IRQ=m +CONFIG_RAID_ATTRS=m +CONFIG_SCSI=y +CONFIG_BLK_DEV_SD=y +CONFIG_CHR_DEV_ST=m +CONFIG_BLK_DEV_SR=y +CONFIG_CHR_DEV_SG=m +CONFIG_SCSI_CONSTANTS=y +CONFIG_SCSI_SAS_ATTRS=m +CONFIG_ISCSI_TCP=m +CONFIG_ISCSI_BOOT_SYSFS=m +CONFIG_MVME16x_SCSI=y +CONFIG_MD=y +CONFIG_MD_LINEAR=m +CONFIG_BLK_DEV_DM=m +CONFIG_DM_UNSTRIPED=m +CONFIG_DM_CRYPT=m +CONFIG_DM_SNAPSHOT=m +CONFIG_DM_THIN_PROVISIONING=m +CONFIG_DM_WRITECACHE=m +CONFIG_DM_ERA=m +CONFIG_DM_CLONE=m +CONFIG_DM_MIRROR=m +CONFIG_DM_RAID=m +CONFIG_DM_ZERO=m +CONFIG_DM_MULTIPATH=m +CONFIG_DM_UEVENT=y +CONFIG_DM_LOG_WRITES=m +CONFIG_DM_INTEGRITY=m +CONFIG_TARGET_CORE=m +CONFIG_TCM_IBLOCK=m +CONFIG_TCM_FILEIO=m +CONFIG_TCM_PSCSI=m +CONFIG_NETDEVICES=y +CONFIG_DUMMY=m +CONFIG_WIREGUARD=m +CONFIG_EQUALIZER=m +CONFIG_NET_TEAM=m +CONFIG_NET_TEAM_MODE_BROADCAST=m +CONFIG_NET_TEAM_MODE_ROUNDROBIN=m +CONFIG_NET_TEAM_MODE_RANDOM=m +CONFIG_NET_TEAM_MODE_ACTIVEBACKUP=m +CONFIG_NET_TEAM_MODE_LOADBALANCE=m +CONFIG_MACVLAN=m +CONFIG_MACVTAP=m +CONFIG_IPVLAN=m +CONFIG_IPVTAP=m +CONFIG_VXLAN=m +CONFIG_GENEVE=m +CONFIG_BAREUDP=m +CONFIG_GTP=m +CONFIG_MACSEC=m +CONFIG_NETCONSOLE=m +CONFIG_NETCONSOLE_DYNAMIC=y +CONFIG_VETH=m +CONFIG_MVME16x_NET=y +CONFIG_PPP=m +CONFIG_PPP_BSDCOMP=m +CONFIG_PPP_DEFLATE=m +CONFIG_PPP_FILTER=y +CONFIG_PPP_MPPE=m +CONFIG_PPPOE=m +CONFIG_PPTP=m +CONFIG_PPPOL2TP=m +CONFIG_PPP_ASYNC=m +CONFIG_PPP_SYNC_TTY=m +CONFIG_SLIP=m +CONFIG_SLIP_COMPRESSED=y +CONFIG_SLIP_SMART=y +CONFIG_SLIP_MODE_SLIP6=y +# CONFIG_WLAN is not set +CONFIG_INPUT_EVDEV=m +# CONFIG_KEYBOARD_ATKBD is not set +# CONFIG_MOUSE_PS2 is not set +# CONFIG_SERIO is not set +CONFIG_VT_HW_CONSOLE_BINDING=y +# CONFIG_LEGACY_PTYS is not set +# CONFIG_HW_RANDOM is not set +CONFIG_NTP_PPS=y +CONFIG_PPS_CLIENT_LDISC=m +CONFIG_PTP_1588_CLOCK=m +# CONFIG_HWMON is not set +CONFIG_HID=m +CONFIG_HIDRAW=y +CONFIG_UHID=m +# CONFIG_HID_GENERIC is not set +# CONFIG_HID_ITE is not set +# CONFIG_HID_REDRAGON is not set +# CONFIG_USB_SUPPORT is not set +CONFIG_RTC_CLASS=y +# CONFIG_RTC_NVMEM is not set +CONFIG_RTC_DRV_GENERIC=m +# CONFIG_VIRTIO_MENU is not set +# CONFIG_VHOST_MENU is not set +# CONFIG_IOMMU_SUPPORT is not set +CONFIG_DAX=m +CONFIG_EXT4_FS=y +CONFIG_REISERFS_FS=m +CONFIG_JFS_FS=m +CONFIG_OCFS2_FS=m +# CONFIG_OCFS2_DEBUG_MASKLOG is not set +CONFIG_FANOTIFY=y +CONFIG_QUOTA_NETLINK_INTERFACE=y +# CONFIG_PRINT_QUOTA_WARNING is not set +CONFIG_AUTOFS_FS=m +CONFIG_FUSE_FS=m +CONFIG_CUSE=m +CONFIG_OVERLAY_FS=m +CONFIG_ISO9660_FS=y +CONFIG_JOLIET=y +CONFIG_ZISOFS=y +CONFIG_UDF_FS=m +CONFIG_MSDOS_FS=m +CONFIG_VFAT_FS=m +CONFIG_EXFAT_FS=m +CONFIG_PROC_KCORE=y +CONFIG_PROC_CHILDREN=y +CONFIG_TMPFS=y +CONFIG_ORANGEFS_FS=m +CONFIG_AFFS_FS=m +CONFIG_ECRYPT_FS=m +CONFIG_ECRYPT_FS_MESSAGING=y +CONFIG_HFS_FS=m +CONFIG_HFSPLUS_FS=m +CONFIG_CRAMFS=m +CONFIG_SQUASHFS=m +CONFIG_SQUASHFS_LZ4=y +CONFIG_SQUASHFS_LZO=y +CONFIG_MINIX_FS=m +CONFIG_OMFS_FS=m +CONFIG_HPFS_FS=m +CONFIG_QNX4FS_FS=m +CONFIG_QNX6FS_FS=m +CONFIG_SYSV_FS=m +CONFIG_UFS_FS=m +CONFIG_EROFS_FS=m +CONFIG_NFS_FS=y +CONFIG_NFS_V4=m +CONFIG_NFS_SWAP=y +CONFIG_ROOT_NFS=y +CONFIG_NFSD=m +CONFIG_NFSD_V3=y +CONFIG_CIFS=m +# CONFIG_CIFS_DEBUG is not set +CONFIG_CODA_FS=m +CONFIG_NLS_CODEPAGE_437=y +CONFIG_NLS_CODEPAGE_737=m +CONFIG_NLS_CODEPAGE_775=m +CONFIG_NLS_CODEPAGE_850=m +CONFIG_NLS_CODEPAGE_852=m +CONFIG_NLS_CODEPAGE_855=m +CONFIG_NLS_CODEPAGE_857=m +CONFIG_NLS_CODEPAGE_860=m +CONFIG_NLS_CODEPAGE_861=m +CONFIG_NLS_CODEPAGE_862=m +CONFIG_NLS_CODEPAGE_863=m +CONFIG_NLS_CODEPAGE_864=m +CONFIG_NLS_CODEPAGE_865=m +CONFIG_NLS_CODEPAGE_866=m +CONFIG_NLS_CODEPAGE_869=m +CONFIG_NLS_CODEPAGE_936=m +CONFIG_NLS_CODEPAGE_950=m +CONFIG_NLS_CODEPAGE_932=m +CONFIG_NLS_CODEPAGE_949=m +CONFIG_NLS_CODEPAGE_874=m +CONFIG_NLS_ISO8859_8=m +CONFIG_NLS_CODEPAGE_1250=m +CONFIG_NLS_CODEPAGE_1251=m +CONFIG_NLS_ASCII=m +CONFIG_NLS_ISO8859_1=y +CONFIG_NLS_ISO8859_2=m +CONFIG_NLS_ISO8859_3=m +CONFIG_NLS_ISO8859_4=m +CONFIG_NLS_ISO8859_5=m +CONFIG_NLS_ISO8859_6=m +CONFIG_NLS_ISO8859_7=m +CONFIG_NLS_ISO8859_9=m +CONFIG_NLS_ISO8859_13=m +CONFIG_NLS_ISO8859_14=m +CONFIG_NLS_ISO8859_15=m +CONFIG_NLS_KOI8_R=m +CONFIG_NLS_KOI8_U=m +CONFIG_NLS_MAC_ROMAN=m +CONFIG_NLS_MAC_CELTIC=m +CONFIG_NLS_MAC_CENTEURO=m +CONFIG_NLS_MAC_CROATIAN=m +CONFIG_NLS_MAC_CYRILLIC=m +CONFIG_NLS_MAC_GAELIC=m +CONFIG_NLS_MAC_GREEK=m +CONFIG_NLS_MAC_ICELAND=m +CONFIG_NLS_MAC_INUIT=m +CONFIG_NLS_MAC_ROMANIAN=m +CONFIG_NLS_MAC_TURKISH=m +CONFIG_DLM=m +CONFIG_ENCRYPTED_KEYS=m +CONFIG_HARDENED_USERCOPY=y +CONFIG_CRYPTO_MANAGER=y +CONFIG_CRYPTO_USER=m +CONFIG_CRYPTO_CRYPTD=m +CONFIG_CRYPTO_TEST=m +CONFIG_CRYPTO_RSA=m +CONFIG_CRYPTO_DH=m +CONFIG_CRYPTO_ECDH=m +CONFIG_CRYPTO_ECRDSA=m +CONFIG_CRYPTO_CURVE25519=m +CONFIG_CRYPTO_CHACHA20POLY1305=m +CONFIG_CRYPTO_AEGIS128=m +CONFIG_CRYPTO_CFB=m +CONFIG_CRYPTO_CTS=m +CONFIG_CRYPTO_LRW=m +CONFIG_CRYPTO_OFB=m +CONFIG_CRYPTO_PCBC=m +CONFIG_CRYPTO_XTS=m +CONFIG_CRYPTO_KEYWRAP=m +CONFIG_CRYPTO_ADIANTUM=m +CONFIG_CRYPTO_XCBC=m +CONFIG_CRYPTO_VMAC=m +CONFIG_CRYPTO_BLAKE2S=m +CONFIG_CRYPTO_MICHAEL_MIC=m +CONFIG_CRYPTO_RMD128=m +CONFIG_CRYPTO_RMD160=m +CONFIG_CRYPTO_RMD256=m +CONFIG_CRYPTO_RMD320=m +CONFIG_CRYPTO_SHA3=m +CONFIG_CRYPTO_SM3=m +CONFIG_CRYPTO_TGR192=m +CONFIG_CRYPTO_WP512=m +CONFIG_CRYPTO_AES=y +CONFIG_CRYPTO_AES_TI=m +CONFIG_CRYPTO_ANUBIS=m +CONFIG_CRYPTO_ARC4=m +CONFIG_CRYPTO_BLOWFISH=m +CONFIG_CRYPTO_CAMELLIA=m +CONFIG_CRYPTO_CAST5=m +CONFIG_CRYPTO_CAST6=m +CONFIG_CRYPTO_DES=m +CONFIG_CRYPTO_FCRYPT=m +CONFIG_CRYPTO_KHAZAD=m +CONFIG_CRYPTO_SALSA20=m +CONFIG_CRYPTO_SEED=m +CONFIG_CRYPTO_SERPENT=m +CONFIG_CRYPTO_SM4=m +CONFIG_CRYPTO_TEA=m +CONFIG_CRYPTO_TWOFISH=m +CONFIG_CRYPTO_LZO=m +CONFIG_CRYPTO_842=m +CONFIG_CRYPTO_LZ4=m +CONFIG_CRYPTO_LZ4HC=m +CONFIG_CRYPTO_ZSTD=m +CONFIG_CRYPTO_ANSI_CPRNG=m +CONFIG_CRYPTO_DRBG_HASH=y +CONFIG_CRYPTO_DRBG_CTR=y +CONFIG_CRYPTO_USER_API_HASH=m +CONFIG_CRYPTO_USER_API_SKCIPHER=m +CONFIG_CRYPTO_USER_API_RNG=m +CONFIG_CRYPTO_USER_API_AEAD=m +# CONFIG_CRYPTO_HW is not set +CONFIG_PRIME_NUMBERS=m +CONFIG_CRC32_SELFTEST=m +CONFIG_CRC64=m +CONFIG_XZ_DEC_TEST=m +CONFIG_STRING_SELFTEST=m +# CONFIG_SECTION_MISMATCH_WARN_ONLY is not set +CONFIG_MAGIC_SYSRQ=y +CONFIG_TEST_LOCKUP=m +CONFIG_WW_MUTEX_SELFTEST=m +CONFIG_EARLY_PRINTK=y +CONFIG_TEST_LIST_SORT=m +CONFIG_TEST_MIN_HEAP=m +CONFIG_TEST_SORT=m +CONFIG_REED_SOLOMON_TEST=m +CONFIG_ATOMIC64_SELFTEST=m +CONFIG_ASYNC_RAID6_TEST=m +CONFIG_TEST_HEXDUMP=m +CONFIG_TEST_STRING_HELPERS=m +CONFIG_TEST_STRSCPY=m +CONFIG_TEST_KSTRTOX=m +CONFIG_TEST_PRINTF=m +CONFIG_TEST_BITMAP=m +CONFIG_TEST_BITFIELD=m +CONFIG_TEST_UUID=m +CONFIG_TEST_XARRAY=m +CONFIG_TEST_OVERFLOW=m +CONFIG_TEST_RHASHTABLE=m +CONFIG_TEST_HASH=m +CONFIG_TEST_IDA=m +CONFIG_TEST_BITOPS=m +CONFIG_TEST_VMALLOC=m +CONFIG_TEST_USER_COPY=m +CONFIG_TEST_BPF=m +CONFIG_TEST_BLACKHOLE_DEV=m +CONFIG_FIND_BIT_BENCHMARK=m +CONFIG_TEST_FIRMWARE=m +CONFIG_TEST_SYSCTL=m +CONFIG_TEST_UDELAY=m +CONFIG_TEST_STATIC_KEYS=m +CONFIG_TEST_KMOD=m +CONFIG_TEST_MEMCAT_P=m +CONFIG_TEST_STACKINIT=m +CONFIG_TEST_MEMINIT=m diff --git a/arch/m68k/configs/q40_defconfig b/arch/m68k/configs/q40_defconfig new file mode 100644 index 000000000..c3a3dcf30 --- /dev/null +++ b/arch/m68k/configs/q40_defconfig @@ -0,0 +1,628 @@ +CONFIG_LOCALVERSION="-q40" +CONFIG_SYSVIPC=y +CONFIG_POSIX_MQUEUE=y +CONFIG_BSD_PROCESS_ACCT=y +CONFIG_BSD_PROCESS_ACCT_V3=y +CONFIG_LOG_BUF_SHIFT=16 +# CONFIG_UTS_NS is not set +# CONFIG_IPC_NS is not set +# CONFIG_PID_NS is not set +# CONFIG_NET_NS is not set +CONFIG_BLK_DEV_INITRD=y +CONFIG_CC_OPTIMIZE_FOR_SIZE=y +CONFIG_USERFAULTFD=y +CONFIG_SLAB=y +CONFIG_KEXEC=y +CONFIG_BOOTINFO_PROC=y +CONFIG_M68040=y +CONFIG_M68060=y +CONFIG_Q40=y +CONFIG_HEARTBEAT=y +CONFIG_PROC_HARDWARE=y +CONFIG_MODULES=y +CONFIG_MODULE_UNLOAD=y +CONFIG_PARTITION_ADVANCED=y +CONFIG_AMIGA_PARTITION=y +CONFIG_ATARI_PARTITION=y +CONFIG_MAC_PARTITION=y +CONFIG_BSD_DISKLABEL=y +CONFIG_MINIX_SUBPARTITION=y +CONFIG_SOLARIS_X86_PARTITION=y +CONFIG_UNIXWARE_DISKLABEL=y +CONFIG_SUN_PARTITION=y +# CONFIG_EFI_PARTITION is not set +CONFIG_SYSV68_PARTITION=y +CONFIG_MQ_IOSCHED_DEADLINE=m +CONFIG_MQ_IOSCHED_KYBER=m +CONFIG_IOSCHED_BFQ=m +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +CONFIG_BINFMT_AOUT=m +CONFIG_BINFMT_MISC=m +# CONFIG_COMPACTION is not set +CONFIG_CLEANCACHE=y +CONFIG_ZPOOL=m +CONFIG_NET=y +CONFIG_PACKET=y +CONFIG_PACKET_DIAG=m +CONFIG_UNIX=y +CONFIG_UNIX_DIAG=m +CONFIG_TLS=m +CONFIG_XFRM_MIGRATE=y +CONFIG_NET_KEY=y +CONFIG_XDP_SOCKETS=y +CONFIG_XDP_SOCKETS_DIAG=m +CONFIG_INET=y +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +CONFIG_IP_PNP_BOOTP=y +CONFIG_IP_PNP_RARP=y +CONFIG_NET_IPIP=m +CONFIG_NET_IPGRE_DEMUX=m +CONFIG_NET_IPGRE=m +CONFIG_NET_IPVTI=m +CONFIG_NET_FOU_IP_TUNNELS=y +CONFIG_INET_AH=m +CONFIG_INET_ESP=m +CONFIG_INET_ESP_OFFLOAD=m +CONFIG_INET_IPCOMP=m +CONFIG_INET_DIAG=m +CONFIG_INET_UDP_DIAG=m +CONFIG_INET_RAW_DIAG=m +CONFIG_IPV6=m +CONFIG_IPV6_ROUTER_PREF=y +CONFIG_INET6_AH=m +CONFIG_INET6_ESP=m +CONFIG_INET6_ESP_OFFLOAD=m +CONFIG_INET6_IPCOMP=m +CONFIG_IPV6_ILA=m +CONFIG_IPV6_VTI=m +CONFIG_IPV6_GRE=m +CONFIG_NETFILTER=y +CONFIG_NF_CONNTRACK=m +CONFIG_NF_LOG_NETDEV=m +CONFIG_NF_CONNTRACK_ZONES=y +# CONFIG_NF_CONNTRACK_PROCFS is not set +# CONFIG_NF_CT_PROTO_DCCP is not set +CONFIG_NF_CONNTRACK_AMANDA=m +CONFIG_NF_CONNTRACK_FTP=m +CONFIG_NF_CONNTRACK_H323=m +CONFIG_NF_CONNTRACK_IRC=m +CONFIG_NF_CONNTRACK_NETBIOS_NS=m +CONFIG_NF_CONNTRACK_SNMP=m +CONFIG_NF_CONNTRACK_PPTP=m +CONFIG_NF_CONNTRACK_SANE=m +CONFIG_NF_CONNTRACK_SIP=m +CONFIG_NF_CONNTRACK_TFTP=m +CONFIG_NF_TABLES=m +CONFIG_NF_TABLES_INET=y +CONFIG_NF_TABLES_NETDEV=y +CONFIG_NFT_NUMGEN=m +CONFIG_NFT_CT=m +CONFIG_NFT_FLOW_OFFLOAD=m +CONFIG_NFT_COUNTER=m +CONFIG_NFT_CONNLIMIT=m +CONFIG_NFT_LOG=m +CONFIG_NFT_LIMIT=m +CONFIG_NFT_MASQ=m +CONFIG_NFT_REDIR=m +CONFIG_NFT_NAT=m +CONFIG_NFT_TUNNEL=m +CONFIG_NFT_OBJREF=m +CONFIG_NFT_QUEUE=m +CONFIG_NFT_QUOTA=m +CONFIG_NFT_REJECT=m +CONFIG_NFT_COMPAT=m +CONFIG_NFT_HASH=m +CONFIG_NFT_FIB_INET=m +CONFIG_NFT_XFRM=m +CONFIG_NFT_SOCKET=m +CONFIG_NFT_OSF=m +CONFIG_NFT_TPROXY=m +CONFIG_NFT_SYNPROXY=m +CONFIG_NFT_DUP_NETDEV=m +CONFIG_NFT_FWD_NETDEV=m +CONFIG_NFT_FIB_NETDEV=m +CONFIG_NF_FLOW_TABLE_INET=m +CONFIG_NF_FLOW_TABLE=m +CONFIG_NETFILTER_XT_SET=m +CONFIG_NETFILTER_XT_TARGET_CHECKSUM=m +CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m +CONFIG_NETFILTER_XT_TARGET_CONNMARK=m +CONFIG_NETFILTER_XT_TARGET_DSCP=m +CONFIG_NETFILTER_XT_TARGET_HMARK=m +CONFIG_NETFILTER_XT_TARGET_IDLETIMER=m +CONFIG_NETFILTER_XT_TARGET_LOG=m +CONFIG_NETFILTER_XT_TARGET_MARK=m +CONFIG_NETFILTER_XT_TARGET_NFLOG=m +CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m +CONFIG_NETFILTER_XT_TARGET_NOTRACK=m +CONFIG_NETFILTER_XT_TARGET_TEE=m +CONFIG_NETFILTER_XT_TARGET_TPROXY=m +CONFIG_NETFILTER_XT_TARGET_TRACE=m +CONFIG_NETFILTER_XT_TARGET_TCPMSS=m +CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP=m +CONFIG_NETFILTER_XT_MATCH_ADDRTYPE=m +CONFIG_NETFILTER_XT_MATCH_BPF=m +CONFIG_NETFILTER_XT_MATCH_CLUSTER=m +CONFIG_NETFILTER_XT_MATCH_COMMENT=m +CONFIG_NETFILTER_XT_MATCH_CONNBYTES=m +CONFIG_NETFILTER_XT_MATCH_CONNLABEL=m +CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=m +CONFIG_NETFILTER_XT_MATCH_CONNMARK=m +CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m +CONFIG_NETFILTER_XT_MATCH_DEVGROUP=m +CONFIG_NETFILTER_XT_MATCH_DSCP=m +CONFIG_NETFILTER_XT_MATCH_ESP=m +CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=m +CONFIG_NETFILTER_XT_MATCH_HELPER=m +CONFIG_NETFILTER_XT_MATCH_IPCOMP=m +CONFIG_NETFILTER_XT_MATCH_IPRANGE=m +CONFIG_NETFILTER_XT_MATCH_LENGTH=m +CONFIG_NETFILTER_XT_MATCH_LIMIT=m +CONFIG_NETFILTER_XT_MATCH_MAC=m +CONFIG_NETFILTER_XT_MATCH_MARK=m +CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m +CONFIG_NETFILTER_XT_MATCH_NFACCT=m +CONFIG_NETFILTER_XT_MATCH_OSF=m +CONFIG_NETFILTER_XT_MATCH_OWNER=m +CONFIG_NETFILTER_XT_MATCH_POLICY=m +CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m +CONFIG_NETFILTER_XT_MATCH_QUOTA=m +CONFIG_NETFILTER_XT_MATCH_RATEEST=m +CONFIG_NETFILTER_XT_MATCH_REALM=m +CONFIG_NETFILTER_XT_MATCH_RECENT=m +CONFIG_NETFILTER_XT_MATCH_SOCKET=m +CONFIG_NETFILTER_XT_MATCH_STATE=m +CONFIG_NETFILTER_XT_MATCH_STATISTIC=m +CONFIG_NETFILTER_XT_MATCH_STRING=m +CONFIG_NETFILTER_XT_MATCH_TCPMSS=m +CONFIG_NETFILTER_XT_MATCH_TIME=m +CONFIG_NETFILTER_XT_MATCH_U32=m +CONFIG_IP_SET=m +CONFIG_IP_SET_BITMAP_IP=m +CONFIG_IP_SET_BITMAP_IPMAC=m +CONFIG_IP_SET_BITMAP_PORT=m +CONFIG_IP_SET_HASH_IP=m +CONFIG_IP_SET_HASH_IPMARK=m +CONFIG_IP_SET_HASH_IPPORT=m +CONFIG_IP_SET_HASH_IPPORTIP=m +CONFIG_IP_SET_HASH_IPPORTNET=m +CONFIG_IP_SET_HASH_IPMAC=m +CONFIG_IP_SET_HASH_MAC=m +CONFIG_IP_SET_HASH_NETPORTNET=m +CONFIG_IP_SET_HASH_NET=m +CONFIG_IP_SET_HASH_NETNET=m +CONFIG_IP_SET_HASH_NETPORT=m +CONFIG_IP_SET_HASH_NETIFACE=m +CONFIG_IP_SET_LIST_SET=m +CONFIG_NFT_DUP_IPV4=m +CONFIG_NFT_FIB_IPV4=m +CONFIG_NF_TABLES_ARP=y +CONFIG_NF_FLOW_TABLE_IPV4=m +CONFIG_NF_LOG_ARP=m +CONFIG_IP_NF_IPTABLES=m +CONFIG_IP_NF_MATCH_AH=m +CONFIG_IP_NF_MATCH_ECN=m +CONFIG_IP_NF_MATCH_RPFILTER=m +CONFIG_IP_NF_MATCH_TTL=m +CONFIG_IP_NF_FILTER=m +CONFIG_IP_NF_TARGET_REJECT=m +CONFIG_IP_NF_TARGET_SYNPROXY=m +CONFIG_IP_NF_NAT=m +CONFIG_IP_NF_TARGET_MASQUERADE=m +CONFIG_IP_NF_TARGET_NETMAP=m +CONFIG_IP_NF_TARGET_REDIRECT=m +CONFIG_IP_NF_MANGLE=m +CONFIG_IP_NF_TARGET_CLUSTERIP=m +CONFIG_IP_NF_TARGET_ECN=m +CONFIG_IP_NF_TARGET_TTL=m +CONFIG_IP_NF_RAW=m +CONFIG_IP_NF_ARPTABLES=m +CONFIG_IP_NF_ARPFILTER=m +CONFIG_IP_NF_ARP_MANGLE=m +CONFIG_NFT_DUP_IPV6=m +CONFIG_NFT_FIB_IPV6=m +CONFIG_NF_FLOW_TABLE_IPV6=m +CONFIG_IP6_NF_IPTABLES=m +CONFIG_IP6_NF_MATCH_AH=m +CONFIG_IP6_NF_MATCH_EUI64=m +CONFIG_IP6_NF_MATCH_FRAG=m +CONFIG_IP6_NF_MATCH_OPTS=m +CONFIG_IP6_NF_MATCH_HL=m +CONFIG_IP6_NF_MATCH_IPV6HEADER=m +CONFIG_IP6_NF_MATCH_MH=m +CONFIG_IP6_NF_MATCH_RPFILTER=m +CONFIG_IP6_NF_MATCH_RT=m +CONFIG_IP6_NF_MATCH_SRH=m +CONFIG_IP6_NF_TARGET_HL=m +CONFIG_IP6_NF_FILTER=m +CONFIG_IP6_NF_TARGET_REJECT=m +CONFIG_IP6_NF_TARGET_SYNPROXY=m +CONFIG_IP6_NF_MANGLE=m +CONFIG_IP6_NF_RAW=m +CONFIG_IP6_NF_NAT=m +CONFIG_IP6_NF_TARGET_MASQUERADE=m +CONFIG_IP6_NF_TARGET_NPT=m +CONFIG_NF_TABLES_BRIDGE=m +CONFIG_NFT_BRIDGE_META=m +CONFIG_NFT_BRIDGE_REJECT=m +CONFIG_NF_LOG_BRIDGE=m +CONFIG_NF_CONNTRACK_BRIDGE=m +CONFIG_BRIDGE_NF_EBTABLES=m +CONFIG_BRIDGE_EBT_BROUTE=m +CONFIG_BRIDGE_EBT_T_FILTER=m +CONFIG_BRIDGE_EBT_T_NAT=m +CONFIG_BRIDGE_EBT_802_3=m +CONFIG_BRIDGE_EBT_AMONG=m +CONFIG_BRIDGE_EBT_ARP=m +CONFIG_BRIDGE_EBT_IP=m +CONFIG_BRIDGE_EBT_IP6=m +CONFIG_BRIDGE_EBT_LIMIT=m +CONFIG_BRIDGE_EBT_MARK=m +CONFIG_BRIDGE_EBT_PKTTYPE=m +CONFIG_BRIDGE_EBT_STP=m +CONFIG_BRIDGE_EBT_VLAN=m +CONFIG_BRIDGE_EBT_ARPREPLY=m +CONFIG_BRIDGE_EBT_DNAT=m +CONFIG_BRIDGE_EBT_MARK_T=m +CONFIG_BRIDGE_EBT_REDIRECT=m +CONFIG_BRIDGE_EBT_SNAT=m +CONFIG_BRIDGE_EBT_LOG=m +CONFIG_BRIDGE_EBT_NFLOG=m +CONFIG_IP_DCCP=m +# CONFIG_IP_DCCP_CCID3 is not set +CONFIG_SCTP_COOKIE_HMAC_SHA1=y +CONFIG_RDS=m +CONFIG_RDS_TCP=m +CONFIG_L2TP=m +CONFIG_BRIDGE=m +CONFIG_ATALK=m +CONFIG_6LOWPAN=m +CONFIG_6LOWPAN_GHC_EXT_HDR_HOP=m +CONFIG_6LOWPAN_GHC_UDP=m +CONFIG_6LOWPAN_GHC_ICMPV6=m +CONFIG_6LOWPAN_GHC_EXT_HDR_DEST=m +CONFIG_6LOWPAN_GHC_EXT_HDR_FRAG=m +CONFIG_6LOWPAN_GHC_EXT_HDR_ROUTE=m +CONFIG_DNS_RESOLVER=y +CONFIG_BATMAN_ADV=m +# CONFIG_BATMAN_ADV_BATMAN_V is not set +CONFIG_BATMAN_ADV_NC=y +CONFIG_NETLINK_DIAG=m +CONFIG_MPLS=y +CONFIG_NET_MPLS_GSO=m +CONFIG_MPLS_ROUTING=m +CONFIG_MPLS_IPTUNNEL=m +CONFIG_NET_NSH=m +CONFIG_AF_KCM=m +# CONFIG_WIRELESS is not set +CONFIG_PSAMPLE=m +CONFIG_NET_IFE=m +CONFIG_DEVTMPFS=y +CONFIG_DEVTMPFS_MOUNT=y +CONFIG_TEST_ASYNC_DRIVER_PROBE=m +CONFIG_CONNECTOR=m +CONFIG_PARPORT=m +CONFIG_PARPORT_PC=m +CONFIG_PARPORT_1284=y +CONFIG_BLK_DEV_LOOP=y +CONFIG_BLK_DEV_CRYPTOLOOP=m +CONFIG_BLK_DEV_DRBD=m +CONFIG_BLK_DEV_NBD=m +CONFIG_BLK_DEV_RAM=y +CONFIG_CDROM_PKTCDVD=m +CONFIG_ATA_OVER_ETH=m +CONFIG_DUMMY_IRQ=m +CONFIG_IDE=y +CONFIG_IDE_GD_ATAPI=y +CONFIG_BLK_DEV_IDECD=y +CONFIG_BLK_DEV_Q40IDE=y +CONFIG_RAID_ATTRS=m +CONFIG_SCSI=y +CONFIG_BLK_DEV_SD=y +CONFIG_CHR_DEV_ST=m +CONFIG_BLK_DEV_SR=y +CONFIG_CHR_DEV_SG=m +CONFIG_SCSI_CONSTANTS=y +CONFIG_SCSI_SAS_ATTRS=m +CONFIG_ISCSI_TCP=m +CONFIG_ISCSI_BOOT_SYSFS=m +CONFIG_MD=y +CONFIG_MD_LINEAR=m +CONFIG_BLK_DEV_DM=m +CONFIG_DM_UNSTRIPED=m +CONFIG_DM_CRYPT=m +CONFIG_DM_SNAPSHOT=m +CONFIG_DM_THIN_PROVISIONING=m +CONFIG_DM_WRITECACHE=m +CONFIG_DM_ERA=m +CONFIG_DM_CLONE=m +CONFIG_DM_MIRROR=m +CONFIG_DM_RAID=m +CONFIG_DM_ZERO=m +CONFIG_DM_MULTIPATH=m +CONFIG_DM_UEVENT=y +CONFIG_DM_LOG_WRITES=m +CONFIG_DM_INTEGRITY=m +CONFIG_TARGET_CORE=m +CONFIG_TCM_IBLOCK=m +CONFIG_TCM_FILEIO=m +CONFIG_TCM_PSCSI=m +CONFIG_NETDEVICES=y +CONFIG_DUMMY=m +CONFIG_WIREGUARD=m +CONFIG_EQUALIZER=m +CONFIG_NET_TEAM=m +CONFIG_NET_TEAM_MODE_BROADCAST=m +CONFIG_NET_TEAM_MODE_ROUNDROBIN=m +CONFIG_NET_TEAM_MODE_RANDOM=m +CONFIG_NET_TEAM_MODE_ACTIVEBACKUP=m +CONFIG_NET_TEAM_MODE_LOADBALANCE=m +CONFIG_MACVLAN=m +CONFIG_MACVTAP=m +CONFIG_IPVLAN=m +CONFIG_IPVTAP=m +CONFIG_VXLAN=m +CONFIG_GENEVE=m +CONFIG_BAREUDP=m +CONFIG_GTP=m +CONFIG_MACSEC=m +CONFIG_NETCONSOLE=m +CONFIG_NETCONSOLE_DYNAMIC=y +CONFIG_VETH=m +CONFIG_NE2000=y +CONFIG_PLIP=m +CONFIG_PPP=m +CONFIG_PPP_BSDCOMP=m +CONFIG_PPP_DEFLATE=m +CONFIG_PPP_FILTER=y +CONFIG_PPP_MPPE=m +CONFIG_PPPOE=m +CONFIG_PPTP=m +CONFIG_PPPOL2TP=m +CONFIG_PPP_ASYNC=m +CONFIG_PPP_SYNC_TTY=m +CONFIG_SLIP=m +CONFIG_SLIP_COMPRESSED=y +CONFIG_SLIP_SMART=y +CONFIG_SLIP_MODE_SLIP6=y +# CONFIG_WLAN is not set +CONFIG_INPUT_EVDEV=m +# CONFIG_KEYBOARD_ATKBD is not set +# CONFIG_MOUSE_PS2 is not set +CONFIG_MOUSE_SERIAL=m +CONFIG_INPUT_MISC=y +CONFIG_INPUT_M68K_BEEP=m +CONFIG_SERIO_Q40KBD=y +CONFIG_USERIO=m +# CONFIG_LEGACY_PTYS is not set +CONFIG_PRINTER=m +# CONFIG_HW_RANDOM is not set +CONFIG_NTP_PPS=y +CONFIG_PPS_CLIENT_LDISC=m +CONFIG_PPS_CLIENT_PARPORT=m +CONFIG_PTP_1588_CLOCK=m +# CONFIG_HWMON is not set +CONFIG_FB=y +CONFIG_FRAMEBUFFER_CONSOLE=y +CONFIG_LOGO=y +CONFIG_SOUND=m +CONFIG_DMASOUND_Q40=m +CONFIG_HID=m +CONFIG_HIDRAW=y +CONFIG_UHID=m +# CONFIG_HID_GENERIC is not set +# CONFIG_HID_ITE is not set +# CONFIG_HID_REDRAGON is not set +# CONFIG_USB_SUPPORT is not set +CONFIG_RTC_CLASS=y +# CONFIG_RTC_NVMEM is not set +CONFIG_RTC_DRV_GENERIC=m +# CONFIG_VIRTIO_MENU is not set +# CONFIG_VHOST_MENU is not set +# CONFIG_IOMMU_SUPPORT is not set +CONFIG_DAX=m +CONFIG_EXT4_FS=y +CONFIG_REISERFS_FS=m +CONFIG_JFS_FS=m +CONFIG_OCFS2_FS=m +# CONFIG_OCFS2_DEBUG_MASKLOG is not set +CONFIG_FANOTIFY=y +CONFIG_QUOTA_NETLINK_INTERFACE=y +# CONFIG_PRINT_QUOTA_WARNING is not set +CONFIG_AUTOFS_FS=m +CONFIG_FUSE_FS=m +CONFIG_CUSE=m +CONFIG_OVERLAY_FS=m +CONFIG_ISO9660_FS=y +CONFIG_JOLIET=y +CONFIG_ZISOFS=y +CONFIG_UDF_FS=m +CONFIG_MSDOS_FS=m +CONFIG_VFAT_FS=m +CONFIG_EXFAT_FS=m +CONFIG_PROC_KCORE=y +CONFIG_PROC_CHILDREN=y +CONFIG_TMPFS=y +CONFIG_ORANGEFS_FS=m +CONFIG_AFFS_FS=m +CONFIG_ECRYPT_FS=m +CONFIG_ECRYPT_FS_MESSAGING=y +CONFIG_HFS_FS=m +CONFIG_HFSPLUS_FS=m +CONFIG_CRAMFS=m +CONFIG_SQUASHFS=m +CONFIG_SQUASHFS_LZ4=y +CONFIG_SQUASHFS_LZO=y +CONFIG_MINIX_FS=m +CONFIG_OMFS_FS=m +CONFIG_HPFS_FS=m +CONFIG_QNX4FS_FS=m +CONFIG_QNX6FS_FS=m +CONFIG_SYSV_FS=m +CONFIG_UFS_FS=m +CONFIG_EROFS_FS=m +CONFIG_NFS_FS=y +CONFIG_NFS_V4=m +CONFIG_NFS_SWAP=y +CONFIG_ROOT_NFS=y +CONFIG_NFSD=m +CONFIG_NFSD_V3=y +CONFIG_CIFS=m +# CONFIG_CIFS_DEBUG is not set +CONFIG_CODA_FS=m +CONFIG_NLS_CODEPAGE_437=y +CONFIG_NLS_CODEPAGE_737=m +CONFIG_NLS_CODEPAGE_775=m +CONFIG_NLS_CODEPAGE_850=m +CONFIG_NLS_CODEPAGE_852=m +CONFIG_NLS_CODEPAGE_855=m +CONFIG_NLS_CODEPAGE_857=m +CONFIG_NLS_CODEPAGE_860=m +CONFIG_NLS_CODEPAGE_861=m +CONFIG_NLS_CODEPAGE_862=m +CONFIG_NLS_CODEPAGE_863=m +CONFIG_NLS_CODEPAGE_864=m +CONFIG_NLS_CODEPAGE_865=m +CONFIG_NLS_CODEPAGE_866=m +CONFIG_NLS_CODEPAGE_869=m +CONFIG_NLS_CODEPAGE_936=m +CONFIG_NLS_CODEPAGE_950=m +CONFIG_NLS_CODEPAGE_932=m +CONFIG_NLS_CODEPAGE_949=m +CONFIG_NLS_CODEPAGE_874=m +CONFIG_NLS_ISO8859_8=m +CONFIG_NLS_CODEPAGE_1250=m +CONFIG_NLS_CODEPAGE_1251=m +CONFIG_NLS_ASCII=m +CONFIG_NLS_ISO8859_1=y +CONFIG_NLS_ISO8859_2=m +CONFIG_NLS_ISO8859_3=m +CONFIG_NLS_ISO8859_4=m +CONFIG_NLS_ISO8859_5=m +CONFIG_NLS_ISO8859_6=m +CONFIG_NLS_ISO8859_7=m +CONFIG_NLS_ISO8859_9=m +CONFIG_NLS_ISO8859_13=m +CONFIG_NLS_ISO8859_14=m +CONFIG_NLS_ISO8859_15=m +CONFIG_NLS_KOI8_R=m +CONFIG_NLS_KOI8_U=m +CONFIG_NLS_MAC_ROMAN=m +CONFIG_NLS_MAC_CELTIC=m +CONFIG_NLS_MAC_CENTEURO=m +CONFIG_NLS_MAC_CROATIAN=m +CONFIG_NLS_MAC_CYRILLIC=m +CONFIG_NLS_MAC_GAELIC=m +CONFIG_NLS_MAC_GREEK=m +CONFIG_NLS_MAC_ICELAND=m +CONFIG_NLS_MAC_INUIT=m +CONFIG_NLS_MAC_ROMANIAN=m +CONFIG_NLS_MAC_TURKISH=m +CONFIG_DLM=m +CONFIG_ENCRYPTED_KEYS=m +CONFIG_HARDENED_USERCOPY=y +CONFIG_CRYPTO_MANAGER=y +CONFIG_CRYPTO_USER=m +CONFIG_CRYPTO_CRYPTD=m +CONFIG_CRYPTO_TEST=m +CONFIG_CRYPTO_RSA=m +CONFIG_CRYPTO_DH=m +CONFIG_CRYPTO_ECDH=m +CONFIG_CRYPTO_ECRDSA=m +CONFIG_CRYPTO_CURVE25519=m +CONFIG_CRYPTO_CHACHA20POLY1305=m +CONFIG_CRYPTO_AEGIS128=m +CONFIG_CRYPTO_CFB=m +CONFIG_CRYPTO_CTS=m +CONFIG_CRYPTO_LRW=m +CONFIG_CRYPTO_OFB=m +CONFIG_CRYPTO_PCBC=m +CONFIG_CRYPTO_XTS=m +CONFIG_CRYPTO_KEYWRAP=m +CONFIG_CRYPTO_ADIANTUM=m +CONFIG_CRYPTO_XCBC=m +CONFIG_CRYPTO_VMAC=m +CONFIG_CRYPTO_BLAKE2S=m +CONFIG_CRYPTO_MICHAEL_MIC=m +CONFIG_CRYPTO_RMD128=m +CONFIG_CRYPTO_RMD160=m +CONFIG_CRYPTO_RMD256=m +CONFIG_CRYPTO_RMD320=m +CONFIG_CRYPTO_SHA3=m +CONFIG_CRYPTO_SM3=m +CONFIG_CRYPTO_TGR192=m +CONFIG_CRYPTO_WP512=m +CONFIG_CRYPTO_AES=y +CONFIG_CRYPTO_AES_TI=m +CONFIG_CRYPTO_ANUBIS=m +CONFIG_CRYPTO_ARC4=m +CONFIG_CRYPTO_BLOWFISH=m +CONFIG_CRYPTO_CAMELLIA=m +CONFIG_CRYPTO_CAST5=m +CONFIG_CRYPTO_CAST6=m +CONFIG_CRYPTO_DES=m +CONFIG_CRYPTO_FCRYPT=m +CONFIG_CRYPTO_KHAZAD=m +CONFIG_CRYPTO_SALSA20=m +CONFIG_CRYPTO_SEED=m +CONFIG_CRYPTO_SERPENT=m +CONFIG_CRYPTO_SM4=m +CONFIG_CRYPTO_TEA=m +CONFIG_CRYPTO_TWOFISH=m +CONFIG_CRYPTO_LZO=m +CONFIG_CRYPTO_842=m +CONFIG_CRYPTO_LZ4=m +CONFIG_CRYPTO_LZ4HC=m +CONFIG_CRYPTO_ZSTD=m +CONFIG_CRYPTO_ANSI_CPRNG=m +CONFIG_CRYPTO_DRBG_HASH=y +CONFIG_CRYPTO_DRBG_CTR=y +CONFIG_CRYPTO_USER_API_HASH=m +CONFIG_CRYPTO_USER_API_SKCIPHER=m +CONFIG_CRYPTO_USER_API_RNG=m +CONFIG_CRYPTO_USER_API_AEAD=m +# CONFIG_CRYPTO_HW is not set +CONFIG_PRIME_NUMBERS=m +CONFIG_CRC32_SELFTEST=m +CONFIG_CRC64=m +CONFIG_XZ_DEC_TEST=m +CONFIG_STRING_SELFTEST=m +# CONFIG_SECTION_MISMATCH_WARN_ONLY is not set +CONFIG_MAGIC_SYSRQ=y +CONFIG_TEST_LOCKUP=m +CONFIG_WW_MUTEX_SELFTEST=m +CONFIG_EARLY_PRINTK=y +CONFIG_TEST_LIST_SORT=m +CONFIG_TEST_MIN_HEAP=m +CONFIG_TEST_SORT=m +CONFIG_REED_SOLOMON_TEST=m +CONFIG_ATOMIC64_SELFTEST=m +CONFIG_ASYNC_RAID6_TEST=m +CONFIG_TEST_HEXDUMP=m +CONFIG_TEST_STRING_HELPERS=m +CONFIG_TEST_STRSCPY=m +CONFIG_TEST_KSTRTOX=m +CONFIG_TEST_PRINTF=m +CONFIG_TEST_BITMAP=m +CONFIG_TEST_BITFIELD=m +CONFIG_TEST_UUID=m +CONFIG_TEST_XARRAY=m +CONFIG_TEST_OVERFLOW=m +CONFIG_TEST_RHASHTABLE=m +CONFIG_TEST_HASH=m +CONFIG_TEST_IDA=m +CONFIG_TEST_BITOPS=m +CONFIG_TEST_VMALLOC=m +CONFIG_TEST_USER_COPY=m +CONFIG_TEST_BPF=m +CONFIG_TEST_BLACKHOLE_DEV=m +CONFIG_FIND_BIT_BENCHMARK=m +CONFIG_TEST_FIRMWARE=m +CONFIG_TEST_SYSCTL=m +CONFIG_TEST_UDELAY=m +CONFIG_TEST_STATIC_KEYS=m +CONFIG_TEST_KMOD=m +CONFIG_TEST_MEMCAT_P=m +CONFIG_TEST_STACKINIT=m +CONFIG_TEST_MEMINIT=m diff --git a/arch/m68k/configs/stmark2_defconfig b/arch/m68k/configs/stmark2_defconfig new file mode 100644 index 000000000..d92306472 --- /dev/null +++ b/arch/m68k/configs/stmark2_defconfig @@ -0,0 +1,95 @@ +CONFIG_LOCALVERSION="stmark2-001" +CONFIG_DEFAULT_HOSTNAME="stmark2" +CONFIG_SYSVIPC=y +CONFIG_LOG_BUF_SHIFT=14 +CONFIG_NAMESPACES=y +CONFIG_BLK_DEV_INITRD=y +CONFIG_CC_OPTIMIZE_FOR_SIZE=y +# CONFIG_FHANDLE is not set +# CONFIG_AIO is not set +# CONFIG_ADVISE_SYSCALLS is not set +# CONFIG_MEMBARRIER is not set +CONFIG_EMBEDDED=y +# CONFIG_VM_EVENT_COUNTERS is not set +# CONFIG_COMPAT_BRK is not set +CONFIG_COLDFIRE=y +CONFIG_M5441x=y +CONFIG_CLOCK_FREQ=240000000 +CONFIG_STMARK2=y +CONFIG_UBOOT=y +CONFIG_RAMBASE=0x40000000 +CONFIG_RAMSIZE=0x8000000 +CONFIG_VECTORBASE=0x40000000 +CONFIG_KERNELBASE=0x40001000 +# CONFIG_BLK_DEV_BSG is not set +CONFIG_BLK_CMDLINE_PARSER=y +CONFIG_BINFMT_FLAT=y +CONFIG_BINFMT_ZFLAT=y +CONFIG_BINFMT_MISC=y +CONFIG_DEVTMPFS=y +CONFIG_DEVTMPFS_MOUNT=y +# CONFIG_ALLOW_DEV_COREDUMP is not set +CONFIG_MTD=y +CONFIG_MTD_CMDLINE_PARTS=y +CONFIG_MTD_BLOCK=y +CONFIG_MTD_CFI=y +CONFIG_MTD_JEDECPROBE=y +CONFIG_MTD_CFI_ADV_OPTIONS=y +CONFIG_MTD_CFI_LE_BYTE_SWAP=y +CONFIG_MTD_CFI_GEOMETRY=y +# CONFIG_MTD_CFI_I2 is not set +CONFIG_MTD_CFI_AMDSTD=y +CONFIG_MTD_CFI_STAA=y +CONFIG_MTD_ROM=y +CONFIG_MTD_COMPLEX_MAPPINGS=y +CONFIG_MTD_PLATRAM=y +CONFIG_MTD_SPI_NOR=y +# CONFIG_INPUT_KEYBOARD is not set +# CONFIG_INPUT_MOUSE is not set +CONFIG_SERIO_LIBPS2=y +# CONFIG_UNIX98_PTYS is not set +# CONFIG_DEVMEM is not set +CONFIG_SERIAL_MCF=y +CONFIG_SERIAL_MCF_BAUDRATE=115200 +CONFIG_SERIAL_MCF_CONSOLE=y +# CONFIG_HW_RANDOM is not set +CONFIG_SPI=y +CONFIG_SPI_DEBUG=y +CONFIG_SPI_FSL_DSPI=y +CONFIG_DEBUG_GPIO=y +CONFIG_GPIO_SYSFS=y +CONFIG_GPIO_GENERIC_PLATFORM=y +# CONFIG_HWMON is not set +# CONFIG_HID is not set +# CONFIG_USB_SUPPORT is not set +CONFIG_MMC=y +CONFIG_MMC_DEBUG=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_PLTFM=y +CONFIG_MMC_SDHCI_ESDHC_MCF=y +CONFIG_DMADEVICES=y +CONFIG_MCF_EDMA=y +CONFIG_EXT2_FS=y +CONFIG_EXT2_FS_XATTR=y +CONFIG_EXT2_FS_POSIX_ACL=y +CONFIG_EXT2_FS_SECURITY=y +CONFIG_EXT3_FS=y +CONFIG_EXT3_FS_POSIX_ACL=y +CONFIG_EXT3_FS_SECURITY=y +# CONFIG_FILE_LOCKING is not set +# CONFIG_DNOTIFY is not set +# CONFIG_INOTIFY_USER is not set +CONFIG_OVERLAY_FS=y +CONFIG_FSCACHE=y +# CONFIG_PROC_SYSCTL is not set +CONFIG_CRAMFS=y +CONFIG_SQUASHFS=y +CONFIG_ROMFS_FS=y +CONFIG_CRYPTO_ANSI_CPRNG=y +# CONFIG_CRYPTO_HW is not set +CONFIG_PRINTK_TIME=y +# CONFIG_DEBUG_BUGVERBOSE is not set +# CONFIG_SECTION_MISMATCH_WARN_ONLY is not set +CONFIG_SLUB_DEBUG_ON=y +CONFIG_PANIC_ON_OOPS=y +# CONFIG_SCHED_DEBUG is not set diff --git a/arch/m68k/configs/sun3_defconfig b/arch/m68k/configs/sun3_defconfig new file mode 100644 index 000000000..3c00e52f1 --- /dev/null +++ b/arch/m68k/configs/sun3_defconfig @@ -0,0 +1,611 @@ +CONFIG_LOCALVERSION="-sun3" +CONFIG_SYSVIPC=y +CONFIG_POSIX_MQUEUE=y +CONFIG_BSD_PROCESS_ACCT=y +CONFIG_BSD_PROCESS_ACCT_V3=y +CONFIG_LOG_BUF_SHIFT=16 +# CONFIG_UTS_NS is not set +# CONFIG_IPC_NS is not set +# CONFIG_PID_NS is not set +# CONFIG_NET_NS is not set +CONFIG_BLK_DEV_INITRD=y +CONFIG_CC_OPTIMIZE_FOR_SIZE=y +CONFIG_USERFAULTFD=y +CONFIG_SLAB=y +CONFIG_KEXEC=y +CONFIG_BOOTINFO_PROC=y +CONFIG_SUN3=y +CONFIG_PROC_HARDWARE=y +CONFIG_MODULES=y +CONFIG_MODULE_UNLOAD=y +CONFIG_PARTITION_ADVANCED=y +CONFIG_AMIGA_PARTITION=y +CONFIG_ATARI_PARTITION=y +CONFIG_MAC_PARTITION=y +CONFIG_BSD_DISKLABEL=y +CONFIG_MINIX_SUBPARTITION=y +CONFIG_SOLARIS_X86_PARTITION=y +CONFIG_UNIXWARE_DISKLABEL=y +# CONFIG_EFI_PARTITION is not set +CONFIG_SYSV68_PARTITION=y +CONFIG_MQ_IOSCHED_DEADLINE=m +CONFIG_MQ_IOSCHED_KYBER=m +CONFIG_IOSCHED_BFQ=m +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +CONFIG_BINFMT_AOUT=m +CONFIG_BINFMT_MISC=m +# CONFIG_COMPACTION is not set +CONFIG_CLEANCACHE=y +CONFIG_ZPOOL=m +CONFIG_NET=y +CONFIG_PACKET=y +CONFIG_PACKET_DIAG=m +CONFIG_UNIX=y +CONFIG_UNIX_DIAG=m +CONFIG_TLS=m +CONFIG_XFRM_MIGRATE=y +CONFIG_NET_KEY=y +CONFIG_XDP_SOCKETS=y +CONFIG_XDP_SOCKETS_DIAG=m +CONFIG_INET=y +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +CONFIG_IP_PNP_BOOTP=y +CONFIG_IP_PNP_RARP=y +CONFIG_NET_IPIP=m +CONFIG_NET_IPGRE_DEMUX=m +CONFIG_NET_IPGRE=m +CONFIG_NET_IPVTI=m +CONFIG_NET_FOU_IP_TUNNELS=y +CONFIG_INET_AH=m +CONFIG_INET_ESP=m +CONFIG_INET_ESP_OFFLOAD=m +CONFIG_INET_IPCOMP=m +CONFIG_INET_DIAG=m +CONFIG_INET_UDP_DIAG=m +CONFIG_INET_RAW_DIAG=m +CONFIG_IPV6=m +CONFIG_IPV6_ROUTER_PREF=y +CONFIG_INET6_AH=m +CONFIG_INET6_ESP=m +CONFIG_INET6_ESP_OFFLOAD=m +CONFIG_INET6_IPCOMP=m +CONFIG_IPV6_ILA=m +CONFIG_IPV6_VTI=m +CONFIG_IPV6_GRE=m +CONFIG_NETFILTER=y +CONFIG_NF_CONNTRACK=m +CONFIG_NF_LOG_NETDEV=m +CONFIG_NF_CONNTRACK_ZONES=y +# CONFIG_NF_CONNTRACK_PROCFS is not set +# CONFIG_NF_CT_PROTO_DCCP is not set +CONFIG_NF_CONNTRACK_AMANDA=m +CONFIG_NF_CONNTRACK_FTP=m +CONFIG_NF_CONNTRACK_H323=m +CONFIG_NF_CONNTRACK_IRC=m +CONFIG_NF_CONNTRACK_NETBIOS_NS=m +CONFIG_NF_CONNTRACK_SNMP=m +CONFIG_NF_CONNTRACK_PPTP=m +CONFIG_NF_CONNTRACK_SANE=m +CONFIG_NF_CONNTRACK_SIP=m +CONFIG_NF_CONNTRACK_TFTP=m +CONFIG_NF_TABLES=m +CONFIG_NF_TABLES_INET=y +CONFIG_NF_TABLES_NETDEV=y +CONFIG_NFT_NUMGEN=m +CONFIG_NFT_CT=m +CONFIG_NFT_FLOW_OFFLOAD=m +CONFIG_NFT_COUNTER=m +CONFIG_NFT_CONNLIMIT=m +CONFIG_NFT_LOG=m +CONFIG_NFT_LIMIT=m +CONFIG_NFT_MASQ=m +CONFIG_NFT_REDIR=m +CONFIG_NFT_NAT=m +CONFIG_NFT_TUNNEL=m +CONFIG_NFT_OBJREF=m +CONFIG_NFT_QUEUE=m +CONFIG_NFT_QUOTA=m +CONFIG_NFT_REJECT=m +CONFIG_NFT_COMPAT=m +CONFIG_NFT_HASH=m +CONFIG_NFT_FIB_INET=m +CONFIG_NFT_XFRM=m +CONFIG_NFT_SOCKET=m +CONFIG_NFT_OSF=m +CONFIG_NFT_TPROXY=m +CONFIG_NFT_SYNPROXY=m +CONFIG_NFT_DUP_NETDEV=m +CONFIG_NFT_FWD_NETDEV=m +CONFIG_NFT_FIB_NETDEV=m +CONFIG_NF_FLOW_TABLE_INET=m +CONFIG_NF_FLOW_TABLE=m +CONFIG_NETFILTER_XT_SET=m +CONFIG_NETFILTER_XT_TARGET_CHECKSUM=m +CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m +CONFIG_NETFILTER_XT_TARGET_CONNMARK=m +CONFIG_NETFILTER_XT_TARGET_DSCP=m +CONFIG_NETFILTER_XT_TARGET_HMARK=m +CONFIG_NETFILTER_XT_TARGET_IDLETIMER=m +CONFIG_NETFILTER_XT_TARGET_LOG=m +CONFIG_NETFILTER_XT_TARGET_MARK=m +CONFIG_NETFILTER_XT_TARGET_NFLOG=m +CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m +CONFIG_NETFILTER_XT_TARGET_NOTRACK=m +CONFIG_NETFILTER_XT_TARGET_TEE=m +CONFIG_NETFILTER_XT_TARGET_TPROXY=m +CONFIG_NETFILTER_XT_TARGET_TRACE=m +CONFIG_NETFILTER_XT_TARGET_TCPMSS=m +CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP=m +CONFIG_NETFILTER_XT_MATCH_ADDRTYPE=m +CONFIG_NETFILTER_XT_MATCH_BPF=m +CONFIG_NETFILTER_XT_MATCH_CLUSTER=m +CONFIG_NETFILTER_XT_MATCH_COMMENT=m +CONFIG_NETFILTER_XT_MATCH_CONNBYTES=m +CONFIG_NETFILTER_XT_MATCH_CONNLABEL=m +CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=m +CONFIG_NETFILTER_XT_MATCH_CONNMARK=m +CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m +CONFIG_NETFILTER_XT_MATCH_DEVGROUP=m +CONFIG_NETFILTER_XT_MATCH_DSCP=m +CONFIG_NETFILTER_XT_MATCH_ESP=m +CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=m +CONFIG_NETFILTER_XT_MATCH_HELPER=m +CONFIG_NETFILTER_XT_MATCH_IPCOMP=m +CONFIG_NETFILTER_XT_MATCH_IPRANGE=m +CONFIG_NETFILTER_XT_MATCH_LENGTH=m +CONFIG_NETFILTER_XT_MATCH_LIMIT=m +CONFIG_NETFILTER_XT_MATCH_MAC=m +CONFIG_NETFILTER_XT_MATCH_MARK=m +CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m +CONFIG_NETFILTER_XT_MATCH_NFACCT=m +CONFIG_NETFILTER_XT_MATCH_OSF=m +CONFIG_NETFILTER_XT_MATCH_OWNER=m +CONFIG_NETFILTER_XT_MATCH_POLICY=m +CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m +CONFIG_NETFILTER_XT_MATCH_QUOTA=m +CONFIG_NETFILTER_XT_MATCH_RATEEST=m +CONFIG_NETFILTER_XT_MATCH_REALM=m +CONFIG_NETFILTER_XT_MATCH_RECENT=m +CONFIG_NETFILTER_XT_MATCH_SOCKET=m +CONFIG_NETFILTER_XT_MATCH_STATE=m +CONFIG_NETFILTER_XT_MATCH_STATISTIC=m +CONFIG_NETFILTER_XT_MATCH_STRING=m +CONFIG_NETFILTER_XT_MATCH_TCPMSS=m +CONFIG_NETFILTER_XT_MATCH_TIME=m +CONFIG_NETFILTER_XT_MATCH_U32=m +CONFIG_IP_SET=m +CONFIG_IP_SET_BITMAP_IP=m +CONFIG_IP_SET_BITMAP_IPMAC=m +CONFIG_IP_SET_BITMAP_PORT=m +CONFIG_IP_SET_HASH_IP=m +CONFIG_IP_SET_HASH_IPMARK=m +CONFIG_IP_SET_HASH_IPPORT=m +CONFIG_IP_SET_HASH_IPPORTIP=m +CONFIG_IP_SET_HASH_IPPORTNET=m +CONFIG_IP_SET_HASH_IPMAC=m +CONFIG_IP_SET_HASH_MAC=m +CONFIG_IP_SET_HASH_NETPORTNET=m +CONFIG_IP_SET_HASH_NET=m +CONFIG_IP_SET_HASH_NETNET=m +CONFIG_IP_SET_HASH_NETPORT=m +CONFIG_IP_SET_HASH_NETIFACE=m +CONFIG_IP_SET_LIST_SET=m +CONFIG_NFT_DUP_IPV4=m +CONFIG_NFT_FIB_IPV4=m +CONFIG_NF_TABLES_ARP=y +CONFIG_NF_FLOW_TABLE_IPV4=m +CONFIG_NF_LOG_ARP=m +CONFIG_IP_NF_IPTABLES=m +CONFIG_IP_NF_MATCH_AH=m +CONFIG_IP_NF_MATCH_ECN=m +CONFIG_IP_NF_MATCH_RPFILTER=m +CONFIG_IP_NF_MATCH_TTL=m +CONFIG_IP_NF_FILTER=m +CONFIG_IP_NF_TARGET_REJECT=m +CONFIG_IP_NF_TARGET_SYNPROXY=m +CONFIG_IP_NF_NAT=m +CONFIG_IP_NF_TARGET_MASQUERADE=m +CONFIG_IP_NF_TARGET_NETMAP=m +CONFIG_IP_NF_TARGET_REDIRECT=m +CONFIG_IP_NF_MANGLE=m +CONFIG_IP_NF_TARGET_CLUSTERIP=m +CONFIG_IP_NF_TARGET_ECN=m +CONFIG_IP_NF_TARGET_TTL=m +CONFIG_IP_NF_RAW=m +CONFIG_IP_NF_ARPTABLES=m +CONFIG_IP_NF_ARPFILTER=m +CONFIG_IP_NF_ARP_MANGLE=m +CONFIG_NFT_DUP_IPV6=m +CONFIG_NFT_FIB_IPV6=m +CONFIG_NF_FLOW_TABLE_IPV6=m +CONFIG_IP6_NF_IPTABLES=m +CONFIG_IP6_NF_MATCH_AH=m +CONFIG_IP6_NF_MATCH_EUI64=m +CONFIG_IP6_NF_MATCH_FRAG=m +CONFIG_IP6_NF_MATCH_OPTS=m +CONFIG_IP6_NF_MATCH_HL=m +CONFIG_IP6_NF_MATCH_IPV6HEADER=m +CONFIG_IP6_NF_MATCH_MH=m +CONFIG_IP6_NF_MATCH_RPFILTER=m +CONFIG_IP6_NF_MATCH_RT=m +CONFIG_IP6_NF_MATCH_SRH=m +CONFIG_IP6_NF_TARGET_HL=m +CONFIG_IP6_NF_FILTER=m +CONFIG_IP6_NF_TARGET_REJECT=m +CONFIG_IP6_NF_TARGET_SYNPROXY=m +CONFIG_IP6_NF_MANGLE=m +CONFIG_IP6_NF_RAW=m +CONFIG_IP6_NF_NAT=m +CONFIG_IP6_NF_TARGET_MASQUERADE=m +CONFIG_IP6_NF_TARGET_NPT=m +CONFIG_NF_TABLES_BRIDGE=m +CONFIG_NFT_BRIDGE_META=m +CONFIG_NFT_BRIDGE_REJECT=m +CONFIG_NF_LOG_BRIDGE=m +CONFIG_NF_CONNTRACK_BRIDGE=m +CONFIG_BRIDGE_NF_EBTABLES=m +CONFIG_BRIDGE_EBT_BROUTE=m +CONFIG_BRIDGE_EBT_T_FILTER=m +CONFIG_BRIDGE_EBT_T_NAT=m +CONFIG_BRIDGE_EBT_802_3=m +CONFIG_BRIDGE_EBT_AMONG=m +CONFIG_BRIDGE_EBT_ARP=m +CONFIG_BRIDGE_EBT_IP=m +CONFIG_BRIDGE_EBT_IP6=m +CONFIG_BRIDGE_EBT_LIMIT=m +CONFIG_BRIDGE_EBT_MARK=m +CONFIG_BRIDGE_EBT_PKTTYPE=m +CONFIG_BRIDGE_EBT_STP=m +CONFIG_BRIDGE_EBT_VLAN=m +CONFIG_BRIDGE_EBT_ARPREPLY=m +CONFIG_BRIDGE_EBT_DNAT=m +CONFIG_BRIDGE_EBT_MARK_T=m +CONFIG_BRIDGE_EBT_REDIRECT=m +CONFIG_BRIDGE_EBT_SNAT=m +CONFIG_BRIDGE_EBT_LOG=m +CONFIG_BRIDGE_EBT_NFLOG=m +CONFIG_IP_DCCP=m +# CONFIG_IP_DCCP_CCID3 is not set +CONFIG_SCTP_COOKIE_HMAC_SHA1=y +CONFIG_RDS=m +CONFIG_RDS_TCP=m +CONFIG_L2TP=m +CONFIG_BRIDGE=m +CONFIG_ATALK=m +CONFIG_6LOWPAN=m +CONFIG_6LOWPAN_GHC_EXT_HDR_HOP=m +CONFIG_6LOWPAN_GHC_UDP=m +CONFIG_6LOWPAN_GHC_ICMPV6=m +CONFIG_6LOWPAN_GHC_EXT_HDR_DEST=m +CONFIG_6LOWPAN_GHC_EXT_HDR_FRAG=m +CONFIG_6LOWPAN_GHC_EXT_HDR_ROUTE=m +CONFIG_DNS_RESOLVER=y +CONFIG_BATMAN_ADV=m +# CONFIG_BATMAN_ADV_BATMAN_V is not set +CONFIG_BATMAN_ADV_NC=y +CONFIG_NETLINK_DIAG=m +CONFIG_MPLS=y +CONFIG_NET_MPLS_GSO=m +CONFIG_MPLS_ROUTING=m +CONFIG_MPLS_IPTUNNEL=m +CONFIG_NET_NSH=m +CONFIG_AF_KCM=m +# CONFIG_WIRELESS is not set +CONFIG_PSAMPLE=m +CONFIG_NET_IFE=m +CONFIG_DEVTMPFS=y +CONFIG_DEVTMPFS_MOUNT=y +CONFIG_TEST_ASYNC_DRIVER_PROBE=m +CONFIG_CONNECTOR=m +CONFIG_BLK_DEV_LOOP=y +CONFIG_BLK_DEV_CRYPTOLOOP=m +CONFIG_BLK_DEV_DRBD=m +CONFIG_BLK_DEV_NBD=m +CONFIG_BLK_DEV_RAM=y +CONFIG_CDROM_PKTCDVD=m +CONFIG_ATA_OVER_ETH=m +CONFIG_DUMMY_IRQ=m +CONFIG_RAID_ATTRS=m +CONFIG_SCSI=y +CONFIG_BLK_DEV_SD=y +CONFIG_CHR_DEV_ST=m +CONFIG_BLK_DEV_SR=y +CONFIG_CHR_DEV_SG=m +CONFIG_SCSI_CONSTANTS=y +CONFIG_SCSI_SAS_ATTRS=m +CONFIG_ISCSI_TCP=m +CONFIG_ISCSI_BOOT_SYSFS=m +CONFIG_SUN3_SCSI=y +CONFIG_MD=y +CONFIG_MD_LINEAR=m +CONFIG_BLK_DEV_DM=m +CONFIG_DM_UNSTRIPED=m +CONFIG_DM_CRYPT=m +CONFIG_DM_SNAPSHOT=m +CONFIG_DM_THIN_PROVISIONING=m +CONFIG_DM_WRITECACHE=m +CONFIG_DM_ERA=m +CONFIG_DM_CLONE=m +CONFIG_DM_MIRROR=m +CONFIG_DM_RAID=m +CONFIG_DM_ZERO=m +CONFIG_DM_MULTIPATH=m +CONFIG_DM_UEVENT=y +CONFIG_DM_LOG_WRITES=m +CONFIG_DM_INTEGRITY=m +CONFIG_TARGET_CORE=m +CONFIG_TCM_IBLOCK=m +CONFIG_TCM_FILEIO=m +CONFIG_TCM_PSCSI=m +CONFIG_NETDEVICES=y +CONFIG_DUMMY=m +CONFIG_WIREGUARD=m +CONFIG_EQUALIZER=m +CONFIG_NET_TEAM=m +CONFIG_NET_TEAM_MODE_BROADCAST=m +CONFIG_NET_TEAM_MODE_ROUNDROBIN=m +CONFIG_NET_TEAM_MODE_RANDOM=m +CONFIG_NET_TEAM_MODE_ACTIVEBACKUP=m +CONFIG_NET_TEAM_MODE_LOADBALANCE=m +CONFIG_MACVLAN=m +CONFIG_MACVTAP=m +CONFIG_IPVLAN=m +CONFIG_IPVTAP=m +CONFIG_VXLAN=m +CONFIG_GENEVE=m +CONFIG_BAREUDP=m +CONFIG_GTP=m +CONFIG_MACSEC=m +CONFIG_NETCONSOLE=m +CONFIG_NETCONSOLE_DYNAMIC=y +CONFIG_VETH=m +CONFIG_SUN3LANCE=y +CONFIG_SUN3_82586=y +CONFIG_PPP=m +CONFIG_PPP_BSDCOMP=m +CONFIG_PPP_DEFLATE=m +CONFIG_PPP_FILTER=y +CONFIG_PPP_MPPE=m +CONFIG_PPPOE=m +CONFIG_PPTP=m +CONFIG_PPPOL2TP=m +CONFIG_PPP_ASYNC=m +CONFIG_PPP_SYNC_TTY=m +CONFIG_SLIP=m +CONFIG_SLIP_COMPRESSED=y +CONFIG_SLIP_SMART=y +CONFIG_SLIP_MODE_SLIP6=y +# CONFIG_WLAN is not set +CONFIG_INPUT_EVDEV=m +# CONFIG_KEYBOARD_ATKBD is not set +CONFIG_KEYBOARD_SUNKBD=y +# CONFIG_MOUSE_PS2 is not set +CONFIG_MOUSE_SERIAL=m +CONFIG_USERIO=m +# CONFIG_LEGACY_PTYS is not set +# CONFIG_HW_RANDOM is not set +CONFIG_NTP_PPS=y +CONFIG_PPS_CLIENT_LDISC=m +CONFIG_PTP_1588_CLOCK=m +# CONFIG_HWMON is not set +CONFIG_FB=y +CONFIG_FRAMEBUFFER_CONSOLE=y +CONFIG_LOGO=y +CONFIG_HID=m +CONFIG_HIDRAW=y +CONFIG_UHID=m +# CONFIG_HID_GENERIC is not set +# CONFIG_HID_ITE is not set +# CONFIG_HID_REDRAGON is not set +# CONFIG_USB_SUPPORT is not set +CONFIG_RTC_CLASS=y +# CONFIG_RTC_NVMEM is not set +CONFIG_RTC_DRV_GENERIC=m +# CONFIG_VIRTIO_MENU is not set +# CONFIG_VHOST_MENU is not set +# CONFIG_IOMMU_SUPPORT is not set +CONFIG_DAX=m +CONFIG_EXT4_FS=y +CONFIG_REISERFS_FS=m +CONFIG_JFS_FS=m +CONFIG_OCFS2_FS=m +# CONFIG_OCFS2_DEBUG_MASKLOG is not set +CONFIG_FANOTIFY=y +CONFIG_QUOTA_NETLINK_INTERFACE=y +# CONFIG_PRINT_QUOTA_WARNING is not set +CONFIG_AUTOFS_FS=m +CONFIG_FUSE_FS=m +CONFIG_CUSE=m +CONFIG_OVERLAY_FS=m +CONFIG_ISO9660_FS=y +CONFIG_JOLIET=y +CONFIG_ZISOFS=y +CONFIG_UDF_FS=m +CONFIG_MSDOS_FS=m +CONFIG_VFAT_FS=m +CONFIG_EXFAT_FS=m +CONFIG_PROC_KCORE=y +CONFIG_PROC_CHILDREN=y +CONFIG_TMPFS=y +CONFIG_ORANGEFS_FS=m +CONFIG_AFFS_FS=m +CONFIG_ECRYPT_FS=m +CONFIG_ECRYPT_FS_MESSAGING=y +CONFIG_HFS_FS=m +CONFIG_HFSPLUS_FS=m +CONFIG_CRAMFS=m +CONFIG_SQUASHFS=m +CONFIG_SQUASHFS_LZ4=y +CONFIG_SQUASHFS_LZO=y +CONFIG_MINIX_FS=m +CONFIG_OMFS_FS=m +CONFIG_HPFS_FS=m +CONFIG_QNX4FS_FS=m +CONFIG_QNX6FS_FS=m +CONFIG_SYSV_FS=m +CONFIG_UFS_FS=m +CONFIG_EROFS_FS=m +CONFIG_NFS_FS=y +CONFIG_NFS_V4=m +CONFIG_NFS_SWAP=y +CONFIG_ROOT_NFS=y +CONFIG_NFSD=m +CONFIG_NFSD_V3=y +CONFIG_CIFS=m +# CONFIG_CIFS_DEBUG is not set +CONFIG_CODA_FS=m +CONFIG_NLS_CODEPAGE_437=y +CONFIG_NLS_CODEPAGE_737=m +CONFIG_NLS_CODEPAGE_775=m +CONFIG_NLS_CODEPAGE_850=m +CONFIG_NLS_CODEPAGE_852=m +CONFIG_NLS_CODEPAGE_855=m +CONFIG_NLS_CODEPAGE_857=m +CONFIG_NLS_CODEPAGE_860=m +CONFIG_NLS_CODEPAGE_861=m +CONFIG_NLS_CODEPAGE_862=m +CONFIG_NLS_CODEPAGE_863=m +CONFIG_NLS_CODEPAGE_864=m +CONFIG_NLS_CODEPAGE_865=m +CONFIG_NLS_CODEPAGE_866=m +CONFIG_NLS_CODEPAGE_869=m +CONFIG_NLS_CODEPAGE_936=m +CONFIG_NLS_CODEPAGE_950=m +CONFIG_NLS_CODEPAGE_932=m +CONFIG_NLS_CODEPAGE_949=m +CONFIG_NLS_CODEPAGE_874=m +CONFIG_NLS_ISO8859_8=m +CONFIG_NLS_CODEPAGE_1250=m +CONFIG_NLS_CODEPAGE_1251=m +CONFIG_NLS_ASCII=m +CONFIG_NLS_ISO8859_1=y +CONFIG_NLS_ISO8859_2=m +CONFIG_NLS_ISO8859_3=m +CONFIG_NLS_ISO8859_4=m +CONFIG_NLS_ISO8859_5=m +CONFIG_NLS_ISO8859_6=m +CONFIG_NLS_ISO8859_7=m +CONFIG_NLS_ISO8859_9=m +CONFIG_NLS_ISO8859_13=m +CONFIG_NLS_ISO8859_14=m +CONFIG_NLS_ISO8859_15=m +CONFIG_NLS_KOI8_R=m +CONFIG_NLS_KOI8_U=m +CONFIG_NLS_MAC_ROMAN=m +CONFIG_NLS_MAC_CELTIC=m +CONFIG_NLS_MAC_CENTEURO=m +CONFIG_NLS_MAC_CROATIAN=m +CONFIG_NLS_MAC_CYRILLIC=m +CONFIG_NLS_MAC_GAELIC=m +CONFIG_NLS_MAC_GREEK=m +CONFIG_NLS_MAC_ICELAND=m +CONFIG_NLS_MAC_INUIT=m +CONFIG_NLS_MAC_ROMANIAN=m +CONFIG_NLS_MAC_TURKISH=m +CONFIG_DLM=m +CONFIG_ENCRYPTED_KEYS=m +CONFIG_HARDENED_USERCOPY=y +CONFIG_CRYPTO_MANAGER=y +CONFIG_CRYPTO_USER=m +CONFIG_CRYPTO_CRYPTD=m +CONFIG_CRYPTO_TEST=m +CONFIG_CRYPTO_RSA=m +CONFIG_CRYPTO_DH=m +CONFIG_CRYPTO_ECDH=m +CONFIG_CRYPTO_ECRDSA=m +CONFIG_CRYPTO_CURVE25519=m +CONFIG_CRYPTO_CHACHA20POLY1305=m +CONFIG_CRYPTO_AEGIS128=m +CONFIG_CRYPTO_CFB=m +CONFIG_CRYPTO_CTS=m +CONFIG_CRYPTO_LRW=m +CONFIG_CRYPTO_OFB=m +CONFIG_CRYPTO_PCBC=m +CONFIG_CRYPTO_XTS=m +CONFIG_CRYPTO_KEYWRAP=m +CONFIG_CRYPTO_ADIANTUM=m +CONFIG_CRYPTO_XCBC=m +CONFIG_CRYPTO_VMAC=m +CONFIG_CRYPTO_BLAKE2S=m +CONFIG_CRYPTO_MICHAEL_MIC=m +CONFIG_CRYPTO_RMD128=m +CONFIG_CRYPTO_RMD160=m +CONFIG_CRYPTO_RMD256=m +CONFIG_CRYPTO_RMD320=m +CONFIG_CRYPTO_SHA3=m +CONFIG_CRYPTO_SM3=m +CONFIG_CRYPTO_TGR192=m +CONFIG_CRYPTO_WP512=m +CONFIG_CRYPTO_AES=y +CONFIG_CRYPTO_AES_TI=m +CONFIG_CRYPTO_ANUBIS=m +CONFIG_CRYPTO_ARC4=m +CONFIG_CRYPTO_BLOWFISH=m +CONFIG_CRYPTO_CAMELLIA=m +CONFIG_CRYPTO_CAST5=m +CONFIG_CRYPTO_CAST6=m +CONFIG_CRYPTO_DES=m +CONFIG_CRYPTO_FCRYPT=m +CONFIG_CRYPTO_KHAZAD=m +CONFIG_CRYPTO_SALSA20=m +CONFIG_CRYPTO_SEED=m +CONFIG_CRYPTO_SERPENT=m +CONFIG_CRYPTO_SM4=m +CONFIG_CRYPTO_TEA=m +CONFIG_CRYPTO_TWOFISH=m +CONFIG_CRYPTO_LZO=m +CONFIG_CRYPTO_842=m +CONFIG_CRYPTO_LZ4=m +CONFIG_CRYPTO_LZ4HC=m +CONFIG_CRYPTO_ZSTD=m +CONFIG_CRYPTO_ANSI_CPRNG=m +CONFIG_CRYPTO_DRBG_HASH=y +CONFIG_CRYPTO_DRBG_CTR=y +CONFIG_CRYPTO_USER_API_HASH=m +CONFIG_CRYPTO_USER_API_SKCIPHER=m +CONFIG_CRYPTO_USER_API_RNG=m +CONFIG_CRYPTO_USER_API_AEAD=m +# CONFIG_CRYPTO_HW is not set +CONFIG_PRIME_NUMBERS=m +CONFIG_CRC32_SELFTEST=m +CONFIG_CRC64=m +CONFIG_XZ_DEC_TEST=m +CONFIG_STRING_SELFTEST=m +# CONFIG_SECTION_MISMATCH_WARN_ONLY is not set +CONFIG_MAGIC_SYSRQ=y +CONFIG_TEST_LOCKUP=m +CONFIG_WW_MUTEX_SELFTEST=m +CONFIG_TEST_LIST_SORT=m +CONFIG_TEST_MIN_HEAP=m +CONFIG_TEST_SORT=m +CONFIG_REED_SOLOMON_TEST=m +CONFIG_ATOMIC64_SELFTEST=m +CONFIG_ASYNC_RAID6_TEST=m +CONFIG_TEST_HEXDUMP=m +CONFIG_TEST_STRING_HELPERS=m +CONFIG_TEST_STRSCPY=m +CONFIG_TEST_KSTRTOX=m +CONFIG_TEST_PRINTF=m +CONFIG_TEST_BITMAP=m +CONFIG_TEST_BITFIELD=m +CONFIG_TEST_UUID=m +CONFIG_TEST_XARRAY=m +CONFIG_TEST_OVERFLOW=m +CONFIG_TEST_RHASHTABLE=m +CONFIG_TEST_HASH=m +CONFIG_TEST_IDA=m +CONFIG_TEST_BITOPS=m +CONFIG_TEST_VMALLOC=m +CONFIG_TEST_USER_COPY=m +CONFIG_TEST_BPF=m +CONFIG_TEST_BLACKHOLE_DEV=m +CONFIG_FIND_BIT_BENCHMARK=m +CONFIG_TEST_FIRMWARE=m +CONFIG_TEST_SYSCTL=m +CONFIG_TEST_UDELAY=m +CONFIG_TEST_STATIC_KEYS=m +CONFIG_TEST_KMOD=m +CONFIG_TEST_MEMCAT_P=m +CONFIG_TEST_STACKINIT=m +CONFIG_TEST_MEMINIT=m diff --git a/arch/m68k/configs/sun3x_defconfig b/arch/m68k/configs/sun3x_defconfig new file mode 100644 index 000000000..241242d73 --- /dev/null +++ b/arch/m68k/configs/sun3x_defconfig @@ -0,0 +1,611 @@ +CONFIG_LOCALVERSION="-sun3x" +CONFIG_SYSVIPC=y +CONFIG_POSIX_MQUEUE=y +CONFIG_BSD_PROCESS_ACCT=y +CONFIG_BSD_PROCESS_ACCT_V3=y +CONFIG_LOG_BUF_SHIFT=16 +# CONFIG_UTS_NS is not set +# CONFIG_IPC_NS is not set +# CONFIG_PID_NS is not set +# CONFIG_NET_NS is not set +CONFIG_BLK_DEV_INITRD=y +CONFIG_CC_OPTIMIZE_FOR_SIZE=y +CONFIG_USERFAULTFD=y +CONFIG_SLAB=y +CONFIG_KEXEC=y +CONFIG_BOOTINFO_PROC=y +CONFIG_SUN3X=y +CONFIG_PROC_HARDWARE=y +CONFIG_MODULES=y +CONFIG_MODULE_UNLOAD=y +CONFIG_PARTITION_ADVANCED=y +CONFIG_AMIGA_PARTITION=y +CONFIG_ATARI_PARTITION=y +CONFIG_MAC_PARTITION=y +CONFIG_BSD_DISKLABEL=y +CONFIG_MINIX_SUBPARTITION=y +CONFIG_SOLARIS_X86_PARTITION=y +CONFIG_UNIXWARE_DISKLABEL=y +# CONFIG_EFI_PARTITION is not set +CONFIG_SYSV68_PARTITION=y +CONFIG_MQ_IOSCHED_DEADLINE=m +CONFIG_MQ_IOSCHED_KYBER=m +CONFIG_IOSCHED_BFQ=m +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +CONFIG_BINFMT_AOUT=m +CONFIG_BINFMT_MISC=m +# CONFIG_COMPACTION is not set +CONFIG_CLEANCACHE=y +CONFIG_ZPOOL=m +CONFIG_NET=y +CONFIG_PACKET=y +CONFIG_PACKET_DIAG=m +CONFIG_UNIX=y +CONFIG_UNIX_DIAG=m +CONFIG_TLS=m +CONFIG_XFRM_MIGRATE=y +CONFIG_NET_KEY=y +CONFIG_XDP_SOCKETS=y +CONFIG_XDP_SOCKETS_DIAG=m +CONFIG_INET=y +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +CONFIG_IP_PNP_BOOTP=y +CONFIG_IP_PNP_RARP=y +CONFIG_NET_IPIP=m +CONFIG_NET_IPGRE_DEMUX=m +CONFIG_NET_IPGRE=m +CONFIG_NET_IPVTI=m +CONFIG_NET_FOU_IP_TUNNELS=y +CONFIG_INET_AH=m +CONFIG_INET_ESP=m +CONFIG_INET_ESP_OFFLOAD=m +CONFIG_INET_IPCOMP=m +CONFIG_INET_DIAG=m +CONFIG_INET_UDP_DIAG=m +CONFIG_INET_RAW_DIAG=m +CONFIG_IPV6=m +CONFIG_IPV6_ROUTER_PREF=y +CONFIG_INET6_AH=m +CONFIG_INET6_ESP=m +CONFIG_INET6_ESP_OFFLOAD=m +CONFIG_INET6_IPCOMP=m +CONFIG_IPV6_ILA=m +CONFIG_IPV6_VTI=m +CONFIG_IPV6_GRE=m +CONFIG_NETFILTER=y +CONFIG_NF_CONNTRACK=m +CONFIG_NF_LOG_NETDEV=m +CONFIG_NF_CONNTRACK_ZONES=y +# CONFIG_NF_CONNTRACK_PROCFS is not set +# CONFIG_NF_CT_PROTO_DCCP is not set +CONFIG_NF_CONNTRACK_AMANDA=m +CONFIG_NF_CONNTRACK_FTP=m +CONFIG_NF_CONNTRACK_H323=m +CONFIG_NF_CONNTRACK_IRC=m +CONFIG_NF_CONNTRACK_NETBIOS_NS=m +CONFIG_NF_CONNTRACK_SNMP=m +CONFIG_NF_CONNTRACK_PPTP=m +CONFIG_NF_CONNTRACK_SANE=m +CONFIG_NF_CONNTRACK_SIP=m +CONFIG_NF_CONNTRACK_TFTP=m +CONFIG_NF_TABLES=m +CONFIG_NF_TABLES_INET=y +CONFIG_NF_TABLES_NETDEV=y +CONFIG_NFT_NUMGEN=m +CONFIG_NFT_CT=m +CONFIG_NFT_FLOW_OFFLOAD=m +CONFIG_NFT_COUNTER=m +CONFIG_NFT_CONNLIMIT=m +CONFIG_NFT_LOG=m +CONFIG_NFT_LIMIT=m +CONFIG_NFT_MASQ=m +CONFIG_NFT_REDIR=m +CONFIG_NFT_NAT=m +CONFIG_NFT_TUNNEL=m +CONFIG_NFT_OBJREF=m +CONFIG_NFT_QUEUE=m +CONFIG_NFT_QUOTA=m +CONFIG_NFT_REJECT=m +CONFIG_NFT_COMPAT=m +CONFIG_NFT_HASH=m +CONFIG_NFT_FIB_INET=m +CONFIG_NFT_XFRM=m +CONFIG_NFT_SOCKET=m +CONFIG_NFT_OSF=m +CONFIG_NFT_TPROXY=m +CONFIG_NFT_SYNPROXY=m +CONFIG_NFT_DUP_NETDEV=m +CONFIG_NFT_FWD_NETDEV=m +CONFIG_NFT_FIB_NETDEV=m +CONFIG_NF_FLOW_TABLE_INET=m +CONFIG_NF_FLOW_TABLE=m +CONFIG_NETFILTER_XT_SET=m +CONFIG_NETFILTER_XT_TARGET_CHECKSUM=m +CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m +CONFIG_NETFILTER_XT_TARGET_CONNMARK=m +CONFIG_NETFILTER_XT_TARGET_DSCP=m +CONFIG_NETFILTER_XT_TARGET_HMARK=m +CONFIG_NETFILTER_XT_TARGET_IDLETIMER=m +CONFIG_NETFILTER_XT_TARGET_LOG=m +CONFIG_NETFILTER_XT_TARGET_MARK=m +CONFIG_NETFILTER_XT_TARGET_NFLOG=m +CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m +CONFIG_NETFILTER_XT_TARGET_NOTRACK=m +CONFIG_NETFILTER_XT_TARGET_TEE=m +CONFIG_NETFILTER_XT_TARGET_TPROXY=m +CONFIG_NETFILTER_XT_TARGET_TRACE=m +CONFIG_NETFILTER_XT_TARGET_TCPMSS=m +CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP=m +CONFIG_NETFILTER_XT_MATCH_ADDRTYPE=m +CONFIG_NETFILTER_XT_MATCH_BPF=m +CONFIG_NETFILTER_XT_MATCH_CLUSTER=m +CONFIG_NETFILTER_XT_MATCH_COMMENT=m +CONFIG_NETFILTER_XT_MATCH_CONNBYTES=m +CONFIG_NETFILTER_XT_MATCH_CONNLABEL=m +CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=m +CONFIG_NETFILTER_XT_MATCH_CONNMARK=m +CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m +CONFIG_NETFILTER_XT_MATCH_DEVGROUP=m +CONFIG_NETFILTER_XT_MATCH_DSCP=m +CONFIG_NETFILTER_XT_MATCH_ESP=m +CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=m +CONFIG_NETFILTER_XT_MATCH_HELPER=m +CONFIG_NETFILTER_XT_MATCH_IPCOMP=m +CONFIG_NETFILTER_XT_MATCH_IPRANGE=m +CONFIG_NETFILTER_XT_MATCH_LENGTH=m +CONFIG_NETFILTER_XT_MATCH_LIMIT=m +CONFIG_NETFILTER_XT_MATCH_MAC=m +CONFIG_NETFILTER_XT_MATCH_MARK=m +CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m +CONFIG_NETFILTER_XT_MATCH_NFACCT=m +CONFIG_NETFILTER_XT_MATCH_OSF=m +CONFIG_NETFILTER_XT_MATCH_OWNER=m +CONFIG_NETFILTER_XT_MATCH_POLICY=m +CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m +CONFIG_NETFILTER_XT_MATCH_QUOTA=m +CONFIG_NETFILTER_XT_MATCH_RATEEST=m +CONFIG_NETFILTER_XT_MATCH_REALM=m +CONFIG_NETFILTER_XT_MATCH_RECENT=m +CONFIG_NETFILTER_XT_MATCH_SOCKET=m +CONFIG_NETFILTER_XT_MATCH_STATE=m +CONFIG_NETFILTER_XT_MATCH_STATISTIC=m +CONFIG_NETFILTER_XT_MATCH_STRING=m +CONFIG_NETFILTER_XT_MATCH_TCPMSS=m +CONFIG_NETFILTER_XT_MATCH_TIME=m +CONFIG_NETFILTER_XT_MATCH_U32=m +CONFIG_IP_SET=m +CONFIG_IP_SET_BITMAP_IP=m +CONFIG_IP_SET_BITMAP_IPMAC=m +CONFIG_IP_SET_BITMAP_PORT=m +CONFIG_IP_SET_HASH_IP=m +CONFIG_IP_SET_HASH_IPMARK=m +CONFIG_IP_SET_HASH_IPPORT=m +CONFIG_IP_SET_HASH_IPPORTIP=m +CONFIG_IP_SET_HASH_IPPORTNET=m +CONFIG_IP_SET_HASH_IPMAC=m +CONFIG_IP_SET_HASH_MAC=m +CONFIG_IP_SET_HASH_NETPORTNET=m +CONFIG_IP_SET_HASH_NET=m +CONFIG_IP_SET_HASH_NETNET=m +CONFIG_IP_SET_HASH_NETPORT=m +CONFIG_IP_SET_HASH_NETIFACE=m +CONFIG_IP_SET_LIST_SET=m +CONFIG_NFT_DUP_IPV4=m +CONFIG_NFT_FIB_IPV4=m +CONFIG_NF_TABLES_ARP=y +CONFIG_NF_FLOW_TABLE_IPV4=m +CONFIG_NF_LOG_ARP=m +CONFIG_IP_NF_IPTABLES=m +CONFIG_IP_NF_MATCH_AH=m +CONFIG_IP_NF_MATCH_ECN=m +CONFIG_IP_NF_MATCH_RPFILTER=m +CONFIG_IP_NF_MATCH_TTL=m +CONFIG_IP_NF_FILTER=m +CONFIG_IP_NF_TARGET_REJECT=m +CONFIG_IP_NF_TARGET_SYNPROXY=m +CONFIG_IP_NF_NAT=m +CONFIG_IP_NF_TARGET_MASQUERADE=m +CONFIG_IP_NF_TARGET_NETMAP=m +CONFIG_IP_NF_TARGET_REDIRECT=m +CONFIG_IP_NF_MANGLE=m +CONFIG_IP_NF_TARGET_CLUSTERIP=m +CONFIG_IP_NF_TARGET_ECN=m +CONFIG_IP_NF_TARGET_TTL=m +CONFIG_IP_NF_RAW=m +CONFIG_IP_NF_ARPTABLES=m +CONFIG_IP_NF_ARPFILTER=m +CONFIG_IP_NF_ARP_MANGLE=m +CONFIG_NFT_DUP_IPV6=m +CONFIG_NFT_FIB_IPV6=m +CONFIG_NF_FLOW_TABLE_IPV6=m +CONFIG_IP6_NF_IPTABLES=m +CONFIG_IP6_NF_MATCH_AH=m +CONFIG_IP6_NF_MATCH_EUI64=m +CONFIG_IP6_NF_MATCH_FRAG=m +CONFIG_IP6_NF_MATCH_OPTS=m +CONFIG_IP6_NF_MATCH_HL=m +CONFIG_IP6_NF_MATCH_IPV6HEADER=m +CONFIG_IP6_NF_MATCH_MH=m +CONFIG_IP6_NF_MATCH_RPFILTER=m +CONFIG_IP6_NF_MATCH_RT=m +CONFIG_IP6_NF_MATCH_SRH=m +CONFIG_IP6_NF_TARGET_HL=m +CONFIG_IP6_NF_FILTER=m +CONFIG_IP6_NF_TARGET_REJECT=m +CONFIG_IP6_NF_TARGET_SYNPROXY=m +CONFIG_IP6_NF_MANGLE=m +CONFIG_IP6_NF_RAW=m +CONFIG_IP6_NF_NAT=m +CONFIG_IP6_NF_TARGET_MASQUERADE=m +CONFIG_IP6_NF_TARGET_NPT=m +CONFIG_NF_TABLES_BRIDGE=m +CONFIG_NFT_BRIDGE_META=m +CONFIG_NFT_BRIDGE_REJECT=m +CONFIG_NF_LOG_BRIDGE=m +CONFIG_NF_CONNTRACK_BRIDGE=m +CONFIG_BRIDGE_NF_EBTABLES=m +CONFIG_BRIDGE_EBT_BROUTE=m +CONFIG_BRIDGE_EBT_T_FILTER=m +CONFIG_BRIDGE_EBT_T_NAT=m +CONFIG_BRIDGE_EBT_802_3=m +CONFIG_BRIDGE_EBT_AMONG=m +CONFIG_BRIDGE_EBT_ARP=m +CONFIG_BRIDGE_EBT_IP=m +CONFIG_BRIDGE_EBT_IP6=m +CONFIG_BRIDGE_EBT_LIMIT=m +CONFIG_BRIDGE_EBT_MARK=m +CONFIG_BRIDGE_EBT_PKTTYPE=m +CONFIG_BRIDGE_EBT_STP=m +CONFIG_BRIDGE_EBT_VLAN=m +CONFIG_BRIDGE_EBT_ARPREPLY=m +CONFIG_BRIDGE_EBT_DNAT=m +CONFIG_BRIDGE_EBT_MARK_T=m +CONFIG_BRIDGE_EBT_REDIRECT=m +CONFIG_BRIDGE_EBT_SNAT=m +CONFIG_BRIDGE_EBT_LOG=m +CONFIG_BRIDGE_EBT_NFLOG=m +CONFIG_IP_DCCP=m +# CONFIG_IP_DCCP_CCID3 is not set +CONFIG_SCTP_COOKIE_HMAC_SHA1=y +CONFIG_RDS=m +CONFIG_RDS_TCP=m +CONFIG_L2TP=m +CONFIG_BRIDGE=m +CONFIG_ATALK=m +CONFIG_6LOWPAN=m +CONFIG_6LOWPAN_GHC_EXT_HDR_HOP=m +CONFIG_6LOWPAN_GHC_UDP=m +CONFIG_6LOWPAN_GHC_ICMPV6=m +CONFIG_6LOWPAN_GHC_EXT_HDR_DEST=m +CONFIG_6LOWPAN_GHC_EXT_HDR_FRAG=m +CONFIG_6LOWPAN_GHC_EXT_HDR_ROUTE=m +CONFIG_DNS_RESOLVER=y +CONFIG_BATMAN_ADV=m +# CONFIG_BATMAN_ADV_BATMAN_V is not set +CONFIG_BATMAN_ADV_NC=y +CONFIG_NETLINK_DIAG=m +CONFIG_MPLS=y +CONFIG_NET_MPLS_GSO=m +CONFIG_MPLS_ROUTING=m +CONFIG_MPLS_IPTUNNEL=m +CONFIG_NET_NSH=m +CONFIG_AF_KCM=m +# CONFIG_WIRELESS is not set +CONFIG_PSAMPLE=m +CONFIG_NET_IFE=m +CONFIG_DEVTMPFS=y +CONFIG_DEVTMPFS_MOUNT=y +CONFIG_TEST_ASYNC_DRIVER_PROBE=m +CONFIG_CONNECTOR=m +CONFIG_BLK_DEV_LOOP=y +CONFIG_BLK_DEV_CRYPTOLOOP=m +CONFIG_BLK_DEV_DRBD=m +CONFIG_BLK_DEV_NBD=m +CONFIG_BLK_DEV_RAM=y +CONFIG_CDROM_PKTCDVD=m +CONFIG_ATA_OVER_ETH=m +CONFIG_DUMMY_IRQ=m +CONFIG_RAID_ATTRS=m +CONFIG_SCSI=y +CONFIG_BLK_DEV_SD=y +CONFIG_CHR_DEV_ST=m +CONFIG_BLK_DEV_SR=y +CONFIG_CHR_DEV_SG=m +CONFIG_SCSI_CONSTANTS=y +CONFIG_SCSI_SAS_ATTRS=m +CONFIG_ISCSI_TCP=m +CONFIG_ISCSI_BOOT_SYSFS=m +CONFIG_SUN3X_ESP=y +CONFIG_MD=y +CONFIG_MD_LINEAR=m +CONFIG_BLK_DEV_DM=m +CONFIG_DM_UNSTRIPED=m +CONFIG_DM_CRYPT=m +CONFIG_DM_SNAPSHOT=m +CONFIG_DM_THIN_PROVISIONING=m +CONFIG_DM_WRITECACHE=m +CONFIG_DM_ERA=m +CONFIG_DM_CLONE=m +CONFIG_DM_MIRROR=m +CONFIG_DM_RAID=m +CONFIG_DM_ZERO=m +CONFIG_DM_MULTIPATH=m +CONFIG_DM_UEVENT=y +CONFIG_DM_LOG_WRITES=m +CONFIG_DM_INTEGRITY=m +CONFIG_TARGET_CORE=m +CONFIG_TCM_IBLOCK=m +CONFIG_TCM_FILEIO=m +CONFIG_TCM_PSCSI=m +CONFIG_NETDEVICES=y +CONFIG_DUMMY=m +CONFIG_WIREGUARD=m +CONFIG_EQUALIZER=m +CONFIG_NET_TEAM=m +CONFIG_NET_TEAM_MODE_BROADCAST=m +CONFIG_NET_TEAM_MODE_ROUNDROBIN=m +CONFIG_NET_TEAM_MODE_RANDOM=m +CONFIG_NET_TEAM_MODE_ACTIVEBACKUP=m +CONFIG_NET_TEAM_MODE_LOADBALANCE=m +CONFIG_MACVLAN=m +CONFIG_MACVTAP=m +CONFIG_IPVLAN=m +CONFIG_IPVTAP=m +CONFIG_VXLAN=m +CONFIG_GENEVE=m +CONFIG_BAREUDP=m +CONFIG_GTP=m +CONFIG_MACSEC=m +CONFIG_NETCONSOLE=m +CONFIG_NETCONSOLE_DYNAMIC=y +CONFIG_VETH=m +CONFIG_SUN3LANCE=y +CONFIG_PPP=m +CONFIG_PPP_BSDCOMP=m +CONFIG_PPP_DEFLATE=m +CONFIG_PPP_FILTER=y +CONFIG_PPP_MPPE=m +CONFIG_PPPOE=m +CONFIG_PPTP=m +CONFIG_PPPOL2TP=m +CONFIG_PPP_ASYNC=m +CONFIG_PPP_SYNC_TTY=m +CONFIG_SLIP=m +CONFIG_SLIP_COMPRESSED=y +CONFIG_SLIP_SMART=y +CONFIG_SLIP_MODE_SLIP6=y +# CONFIG_WLAN is not set +CONFIG_INPUT_EVDEV=m +# CONFIG_KEYBOARD_ATKBD is not set +CONFIG_KEYBOARD_SUNKBD=y +# CONFIG_MOUSE_PS2 is not set +CONFIG_MOUSE_SERIAL=m +CONFIG_USERIO=m +# CONFIG_LEGACY_PTYS is not set +# CONFIG_HW_RANDOM is not set +CONFIG_NTP_PPS=y +CONFIG_PPS_CLIENT_LDISC=m +CONFIG_PTP_1588_CLOCK=m +# CONFIG_HWMON is not set +CONFIG_FB=y +CONFIG_FRAMEBUFFER_CONSOLE=y +CONFIG_LOGO=y +CONFIG_HID=m +CONFIG_HIDRAW=y +CONFIG_UHID=m +# CONFIG_HID_GENERIC is not set +# CONFIG_HID_ITE is not set +# CONFIG_HID_REDRAGON is not set +# CONFIG_USB_SUPPORT is not set +CONFIG_RTC_CLASS=y +# CONFIG_RTC_NVMEM is not set +CONFIG_RTC_DRV_GENERIC=m +# CONFIG_VIRTIO_MENU is not set +# CONFIG_VHOST_MENU is not set +# CONFIG_IOMMU_SUPPORT is not set +CONFIG_DAX=m +CONFIG_EXT4_FS=y +CONFIG_REISERFS_FS=m +CONFIG_JFS_FS=m +CONFIG_OCFS2_FS=m +# CONFIG_OCFS2_DEBUG_MASKLOG is not set +CONFIG_FANOTIFY=y +CONFIG_QUOTA_NETLINK_INTERFACE=y +# CONFIG_PRINT_QUOTA_WARNING is not set +CONFIG_AUTOFS_FS=m +CONFIG_FUSE_FS=m +CONFIG_CUSE=m +CONFIG_OVERLAY_FS=m +CONFIG_ISO9660_FS=y +CONFIG_JOLIET=y +CONFIG_ZISOFS=y +CONFIG_UDF_FS=m +CONFIG_MSDOS_FS=m +CONFIG_VFAT_FS=m +CONFIG_EXFAT_FS=m +CONFIG_PROC_KCORE=y +CONFIG_PROC_CHILDREN=y +CONFIG_TMPFS=y +CONFIG_ORANGEFS_FS=m +CONFIG_AFFS_FS=m +CONFIG_ECRYPT_FS=m +CONFIG_ECRYPT_FS_MESSAGING=y +CONFIG_HFS_FS=m +CONFIG_HFSPLUS_FS=m +CONFIG_CRAMFS=m +CONFIG_SQUASHFS=m +CONFIG_SQUASHFS_LZ4=y +CONFIG_SQUASHFS_LZO=y +CONFIG_MINIX_FS=m +CONFIG_OMFS_FS=m +CONFIG_HPFS_FS=m +CONFIG_QNX4FS_FS=m +CONFIG_QNX6FS_FS=m +CONFIG_SYSV_FS=m +CONFIG_UFS_FS=m +CONFIG_EROFS_FS=m +CONFIG_NFS_FS=y +CONFIG_NFS_V4=m +CONFIG_NFS_SWAP=y +CONFIG_ROOT_NFS=y +CONFIG_NFSD=m +CONFIG_NFSD_V3=y +CONFIG_CIFS=m +# CONFIG_CIFS_DEBUG is not set +CONFIG_CODA_FS=m +CONFIG_NLS_CODEPAGE_437=y +CONFIG_NLS_CODEPAGE_737=m +CONFIG_NLS_CODEPAGE_775=m +CONFIG_NLS_CODEPAGE_850=m +CONFIG_NLS_CODEPAGE_852=m +CONFIG_NLS_CODEPAGE_855=m +CONFIG_NLS_CODEPAGE_857=m +CONFIG_NLS_CODEPAGE_860=m +CONFIG_NLS_CODEPAGE_861=m +CONFIG_NLS_CODEPAGE_862=m +CONFIG_NLS_CODEPAGE_863=m +CONFIG_NLS_CODEPAGE_864=m +CONFIG_NLS_CODEPAGE_865=m +CONFIG_NLS_CODEPAGE_866=m +CONFIG_NLS_CODEPAGE_869=m +CONFIG_NLS_CODEPAGE_936=m +CONFIG_NLS_CODEPAGE_950=m +CONFIG_NLS_CODEPAGE_932=m +CONFIG_NLS_CODEPAGE_949=m +CONFIG_NLS_CODEPAGE_874=m +CONFIG_NLS_ISO8859_8=m +CONFIG_NLS_CODEPAGE_1250=m +CONFIG_NLS_CODEPAGE_1251=m +CONFIG_NLS_ASCII=m +CONFIG_NLS_ISO8859_1=y +CONFIG_NLS_ISO8859_2=m +CONFIG_NLS_ISO8859_3=m +CONFIG_NLS_ISO8859_4=m +CONFIG_NLS_ISO8859_5=m +CONFIG_NLS_ISO8859_6=m +CONFIG_NLS_ISO8859_7=m +CONFIG_NLS_ISO8859_9=m +CONFIG_NLS_ISO8859_13=m +CONFIG_NLS_ISO8859_14=m +CONFIG_NLS_ISO8859_15=m +CONFIG_NLS_KOI8_R=m +CONFIG_NLS_KOI8_U=m +CONFIG_NLS_MAC_ROMAN=m +CONFIG_NLS_MAC_CELTIC=m +CONFIG_NLS_MAC_CENTEURO=m +CONFIG_NLS_MAC_CROATIAN=m +CONFIG_NLS_MAC_CYRILLIC=m +CONFIG_NLS_MAC_GAELIC=m +CONFIG_NLS_MAC_GREEK=m +CONFIG_NLS_MAC_ICELAND=m +CONFIG_NLS_MAC_INUIT=m +CONFIG_NLS_MAC_ROMANIAN=m +CONFIG_NLS_MAC_TURKISH=m +CONFIG_DLM=m +CONFIG_ENCRYPTED_KEYS=m +CONFIG_HARDENED_USERCOPY=y +CONFIG_CRYPTO_MANAGER=y +CONFIG_CRYPTO_USER=m +CONFIG_CRYPTO_CRYPTD=m +CONFIG_CRYPTO_TEST=m +CONFIG_CRYPTO_RSA=m +CONFIG_CRYPTO_DH=m +CONFIG_CRYPTO_ECDH=m +CONFIG_CRYPTO_ECRDSA=m +CONFIG_CRYPTO_CURVE25519=m +CONFIG_CRYPTO_CHACHA20POLY1305=m +CONFIG_CRYPTO_AEGIS128=m +CONFIG_CRYPTO_CFB=m +CONFIG_CRYPTO_CTS=m +CONFIG_CRYPTO_LRW=m +CONFIG_CRYPTO_OFB=m +CONFIG_CRYPTO_PCBC=m +CONFIG_CRYPTO_XTS=m +CONFIG_CRYPTO_KEYWRAP=m +CONFIG_CRYPTO_ADIANTUM=m +CONFIG_CRYPTO_XCBC=m +CONFIG_CRYPTO_VMAC=m +CONFIG_CRYPTO_BLAKE2S=m +CONFIG_CRYPTO_MICHAEL_MIC=m +CONFIG_CRYPTO_RMD128=m +CONFIG_CRYPTO_RMD160=m +CONFIG_CRYPTO_RMD256=m +CONFIG_CRYPTO_RMD320=m +CONFIG_CRYPTO_SHA3=m +CONFIG_CRYPTO_SM3=m +CONFIG_CRYPTO_TGR192=m +CONFIG_CRYPTO_WP512=m +CONFIG_CRYPTO_AES=y +CONFIG_CRYPTO_AES_TI=m +CONFIG_CRYPTO_ANUBIS=m +CONFIG_CRYPTO_ARC4=m +CONFIG_CRYPTO_BLOWFISH=m +CONFIG_CRYPTO_CAMELLIA=m +CONFIG_CRYPTO_CAST5=m +CONFIG_CRYPTO_CAST6=m +CONFIG_CRYPTO_DES=m +CONFIG_CRYPTO_FCRYPT=m +CONFIG_CRYPTO_KHAZAD=m +CONFIG_CRYPTO_SALSA20=m +CONFIG_CRYPTO_SEED=m +CONFIG_CRYPTO_SERPENT=m +CONFIG_CRYPTO_SM4=m +CONFIG_CRYPTO_TEA=m +CONFIG_CRYPTO_TWOFISH=m +CONFIG_CRYPTO_LZO=m +CONFIG_CRYPTO_842=m +CONFIG_CRYPTO_LZ4=m +CONFIG_CRYPTO_LZ4HC=m +CONFIG_CRYPTO_ZSTD=m +CONFIG_CRYPTO_ANSI_CPRNG=m +CONFIG_CRYPTO_DRBG_HASH=y +CONFIG_CRYPTO_DRBG_CTR=y +CONFIG_CRYPTO_USER_API_HASH=m +CONFIG_CRYPTO_USER_API_SKCIPHER=m +CONFIG_CRYPTO_USER_API_RNG=m +CONFIG_CRYPTO_USER_API_AEAD=m +# CONFIG_CRYPTO_HW is not set +CONFIG_PRIME_NUMBERS=m +CONFIG_CRC32_SELFTEST=m +CONFIG_CRC64=m +CONFIG_XZ_DEC_TEST=m +CONFIG_STRING_SELFTEST=m +# CONFIG_SECTION_MISMATCH_WARN_ONLY is not set +CONFIG_MAGIC_SYSRQ=y +CONFIG_TEST_LOCKUP=m +CONFIG_WW_MUTEX_SELFTEST=m +CONFIG_EARLY_PRINTK=y +CONFIG_TEST_LIST_SORT=m +CONFIG_TEST_MIN_HEAP=m +CONFIG_TEST_SORT=m +CONFIG_REED_SOLOMON_TEST=m +CONFIG_ATOMIC64_SELFTEST=m +CONFIG_ASYNC_RAID6_TEST=m +CONFIG_TEST_HEXDUMP=m +CONFIG_TEST_STRING_HELPERS=m +CONFIG_TEST_STRSCPY=m +CONFIG_TEST_KSTRTOX=m +CONFIG_TEST_PRINTF=m +CONFIG_TEST_BITMAP=m +CONFIG_TEST_BITFIELD=m +CONFIG_TEST_UUID=m +CONFIG_TEST_XARRAY=m +CONFIG_TEST_OVERFLOW=m +CONFIG_TEST_RHASHTABLE=m +CONFIG_TEST_HASH=m +CONFIG_TEST_IDA=m +CONFIG_TEST_BITOPS=m +CONFIG_TEST_VMALLOC=m +CONFIG_TEST_USER_COPY=m +CONFIG_TEST_BPF=m +CONFIG_TEST_BLACKHOLE_DEV=m +CONFIG_FIND_BIT_BENCHMARK=m +CONFIG_TEST_FIRMWARE=m +CONFIG_TEST_SYSCTL=m +CONFIG_TEST_UDELAY=m +CONFIG_TEST_STATIC_KEYS=m +CONFIG_TEST_KMOD=m +CONFIG_TEST_MEMCAT_P=m +CONFIG_TEST_STACKINIT=m +CONFIG_TEST_MEMINIT=m diff --git a/arch/m68k/emu/Makefile b/arch/m68k/emu/Makefile new file mode 100644 index 000000000..4c16e3e6c --- /dev/null +++ b/arch/m68k/emu/Makefile @@ -0,0 +1,10 @@ +# SPDX-License-Identifier: GPL-2.0-only +# +# Makefile for Linux arch/m68k/emu source directory +# + +obj-y += natfeat.o + +obj-$(CONFIG_NFBLOCK) += nfblock.o +obj-$(CONFIG_NFCON) += nfcon.o +obj-$(CONFIG_NFETH) += nfeth.o diff --git a/arch/m68k/emu/natfeat.c b/arch/m68k/emu/natfeat.c new file mode 100644 index 000000000..71b78ecee --- /dev/null +++ b/arch/m68k/emu/natfeat.c @@ -0,0 +1,94 @@ +/* + * natfeat.c - ARAnyM hardware support via Native Features (natfeats) + * + * Copyright (c) 2005 Petr Stehlik of ARAnyM dev team + * + * Reworked for Linux by Roman Zippel + * + * This software may be used and distributed according to the terms of + * the GNU General Public License (GPL), incorporated herein by reference. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +extern long nf_get_id_phys(unsigned long feature_name); + +asm("\n" +" .global nf_get_id_phys,nf_call\n" +"nf_get_id_phys:\n" +" .short 0x7300\n" +" rts\n" +"nf_call:\n" +" .short 0x7301\n" +" rts\n" +"1: moveq.l #0,%d0\n" +" rts\n" +" .section __ex_table,\"a\"\n" +" .long nf_get_id_phys,1b\n" +" .long nf_call,1b\n" +" .previous"); +EXPORT_SYMBOL_GPL(nf_call); + +long nf_get_id(const char *feature_name) +{ + /* feature_name may be in vmalloc()ed memory, so make a copy */ + char name_copy[32]; + size_t n; + + n = strlcpy(name_copy, feature_name, sizeof(name_copy)); + if (n >= sizeof(name_copy)) + return 0; + + return nf_get_id_phys(virt_to_phys(name_copy)); +} +EXPORT_SYMBOL_GPL(nf_get_id); + +void nfprint(const char *fmt, ...) +{ + static char buf[256]; + va_list ap; + int n; + + va_start(ap, fmt); + n = vsnprintf(buf, 256, fmt, ap); + nf_call(nf_get_id("NF_STDERR"), virt_to_phys(buf)); + va_end(ap); +} + +static void nf_poweroff(void) +{ + long id = nf_get_id("NF_SHUTDOWN"); + + if (id) + nf_call(id); +} + +void __init nf_init(void) +{ + unsigned long id, version; + char buf[256]; + + id = nf_get_id("NF_VERSION"); + if (!id) + return; + version = nf_call(id); + + id = nf_get_id("NF_NAME"); + if (!id) + return; + nf_call(id, virt_to_phys(buf), 256); + buf[255] = 0; + + pr_info("NatFeats found (%s, %lu.%lu)\n", buf, version >> 16, + version & 0xffff); + + mach_power_off = nf_poweroff; +} diff --git a/arch/m68k/emu/nfblock.c b/arch/m68k/emu/nfblock.c new file mode 100644 index 000000000..92d26c812 --- /dev/null +++ b/arch/m68k/emu/nfblock.c @@ -0,0 +1,199 @@ +/* + * ARAnyM block device driver + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file COPYING in the main directory of this archive + * for more details. + */ + +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include + +#include + +static long nfhd_id; + +enum { + /* emulation entry points */ + NFHD_READ_WRITE = 10, + NFHD_GET_CAPACITY = 14, + + /* skip ACSI devices */ + NFHD_DEV_OFFSET = 8, +}; + +static inline s32 nfhd_read_write(u32 major, u32 minor, u32 rwflag, u32 recno, + u32 count, u32 buf) +{ + return nf_call(nfhd_id + NFHD_READ_WRITE, major, minor, rwflag, recno, + count, buf); +} + +static inline s32 nfhd_get_capacity(u32 major, u32 minor, u32 *blocks, + u32 *blocksize) +{ + return nf_call(nfhd_id + NFHD_GET_CAPACITY, major, minor, + virt_to_phys(blocks), virt_to_phys(blocksize)); +} + +static LIST_HEAD(nfhd_list); + +static int major_num; +module_param(major_num, int, 0); + +struct nfhd_device { + struct list_head list; + int id; + u32 blocks, bsize; + int bshift; + struct request_queue *queue; + struct gendisk *disk; +}; + +static blk_qc_t nfhd_submit_bio(struct bio *bio) +{ + struct nfhd_device *dev = bio->bi_disk->private_data; + struct bio_vec bvec; + struct bvec_iter iter; + int dir, len, shift; + sector_t sec = bio->bi_iter.bi_sector; + + dir = bio_data_dir(bio); + shift = dev->bshift; + bio_for_each_segment(bvec, bio, iter) { + len = bvec.bv_len; + len >>= 9; + nfhd_read_write(dev->id, 0, dir, sec >> shift, len >> shift, + page_to_phys(bvec.bv_page) + bvec.bv_offset); + sec += len; + } + bio_endio(bio); + return BLK_QC_T_NONE; +} + +static int nfhd_getgeo(struct block_device *bdev, struct hd_geometry *geo) +{ + struct nfhd_device *dev = bdev->bd_disk->private_data; + + geo->cylinders = dev->blocks >> (6 - dev->bshift); + geo->heads = 4; + geo->sectors = 16; + + return 0; +} + +static const struct block_device_operations nfhd_ops = { + .owner = THIS_MODULE, + .submit_bio = nfhd_submit_bio, + .getgeo = nfhd_getgeo, +}; + +static int __init nfhd_init_one(int id, u32 blocks, u32 bsize) +{ + struct nfhd_device *dev; + int dev_id = id - NFHD_DEV_OFFSET; + + pr_info("nfhd%u: found device with %u blocks (%u bytes)\n", dev_id, + blocks, bsize); + + if (bsize < 512 || (bsize & (bsize - 1))) { + pr_warn("nfhd%u: invalid block size\n", dev_id); + return -EINVAL; + } + + dev = kmalloc(sizeof(struct nfhd_device), GFP_KERNEL); + if (!dev) + goto out; + + dev->id = id; + dev->blocks = blocks; + dev->bsize = bsize; + dev->bshift = ffs(bsize) - 10; + + dev->queue = blk_alloc_queue(NUMA_NO_NODE); + if (dev->queue == NULL) + goto free_dev; + + blk_queue_logical_block_size(dev->queue, bsize); + + dev->disk = alloc_disk(16); + if (!dev->disk) + goto free_queue; + + dev->disk->major = major_num; + dev->disk->first_minor = dev_id * 16; + dev->disk->fops = &nfhd_ops; + dev->disk->private_data = dev; + sprintf(dev->disk->disk_name, "nfhd%u", dev_id); + set_capacity(dev->disk, (sector_t)blocks * (bsize / 512)); + dev->disk->queue = dev->queue; + + add_disk(dev->disk); + + list_add_tail(&dev->list, &nfhd_list); + + return 0; + +free_queue: + blk_cleanup_queue(dev->queue); +free_dev: + kfree(dev); +out: + return -ENOMEM; +} + +static int __init nfhd_init(void) +{ + u32 blocks, bsize; + int ret; + int i; + + nfhd_id = nf_get_id("XHDI"); + if (!nfhd_id) + return -ENODEV; + + ret = register_blkdev(major_num, "nfhd"); + if (ret < 0) { + pr_warn("nfhd: unable to get major number\n"); + return ret; + } + + if (!major_num) + major_num = ret; + + for (i = NFHD_DEV_OFFSET; i < 24; i++) { + if (nfhd_get_capacity(i, 0, &blocks, &bsize)) + continue; + nfhd_init_one(i, blocks, bsize); + } + + return 0; +} + +static void __exit nfhd_exit(void) +{ + struct nfhd_device *dev, *next; + + list_for_each_entry_safe(dev, next, &nfhd_list, list) { + list_del(&dev->list); + del_gendisk(dev->disk); + put_disk(dev->disk); + blk_cleanup_queue(dev->queue); + kfree(dev); + } + unregister_blkdev(major_num, "nfhd"); +} + +module_init(nfhd_init); +module_exit(nfhd_exit); + +MODULE_LICENSE("GPL"); diff --git a/arch/m68k/emu/nfcon.c b/arch/m68k/emu/nfcon.c new file mode 100644 index 000000000..57e8c8fb5 --- /dev/null +++ b/arch/m68k/emu/nfcon.c @@ -0,0 +1,169 @@ +/* + * ARAnyM console driver + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file COPYING in the main directory of this archive + * for more details. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +static int stderr_id; +static struct tty_port nfcon_tty_port; +static struct tty_driver *nfcon_tty_driver; + +static void nfputs(const char *str, unsigned int count) +{ + char buf[68]; + unsigned long phys = virt_to_phys(buf); + + buf[64] = 0; + while (count > 64) { + memcpy(buf, str, 64); + nf_call(stderr_id, phys); + str += 64; + count -= 64; + } + memcpy(buf, str, count); + buf[count] = 0; + nf_call(stderr_id, phys); +} + +static void nfcon_write(struct console *con, const char *str, + unsigned int count) +{ + nfputs(str, count); +} + +static struct tty_driver *nfcon_device(struct console *con, int *index) +{ + *index = 0; + return (con->flags & CON_ENABLED) ? nfcon_tty_driver : NULL; +} + +static struct console nf_console = { + .name = "nfcon", + .write = nfcon_write, + .device = nfcon_device, + .flags = CON_PRINTBUFFER, + .index = -1, +}; + + +static int nfcon_tty_open(struct tty_struct *tty, struct file *filp) +{ + return 0; +} + +static void nfcon_tty_close(struct tty_struct *tty, struct file *filp) +{ +} + +static int nfcon_tty_write(struct tty_struct *tty, const unsigned char *buf, + int count) +{ + nfputs(buf, count); + return count; +} + +static int nfcon_tty_put_char(struct tty_struct *tty, unsigned char ch) +{ + char temp[2] = { ch, 0 }; + + nf_call(stderr_id, virt_to_phys(temp)); + return 1; +} + +static int nfcon_tty_write_room(struct tty_struct *tty) +{ + return 64; +} + +static const struct tty_operations nfcon_tty_ops = { + .open = nfcon_tty_open, + .close = nfcon_tty_close, + .write = nfcon_tty_write, + .put_char = nfcon_tty_put_char, + .write_room = nfcon_tty_write_room, +}; + +#ifndef MODULE + +static int __init nf_debug_setup(char *arg) +{ + if (strcmp(arg, "nfcon")) + return 0; + + stderr_id = nf_get_id("NF_STDERR"); + if (stderr_id) { + nf_console.flags |= CON_ENABLED; + register_console(&nf_console); + } + + return 0; +} + +early_param("debug", nf_debug_setup); + +#endif /* !MODULE */ + +static int __init nfcon_init(void) +{ + int res; + + stderr_id = nf_get_id("NF_STDERR"); + if (!stderr_id) + return -ENODEV; + + nfcon_tty_driver = alloc_tty_driver(1); + if (!nfcon_tty_driver) + return -ENOMEM; + + tty_port_init(&nfcon_tty_port); + + nfcon_tty_driver->driver_name = "nfcon"; + nfcon_tty_driver->name = "nfcon"; + nfcon_tty_driver->type = TTY_DRIVER_TYPE_SYSTEM; + nfcon_tty_driver->subtype = SYSTEM_TYPE_TTY; + nfcon_tty_driver->init_termios = tty_std_termios; + nfcon_tty_driver->flags = TTY_DRIVER_REAL_RAW; + + tty_set_operations(nfcon_tty_driver, &nfcon_tty_ops); + tty_port_link_device(&nfcon_tty_port, nfcon_tty_driver, 0); + res = tty_register_driver(nfcon_tty_driver); + if (res) { + pr_err("failed to register nfcon tty driver\n"); + put_tty_driver(nfcon_tty_driver); + tty_port_destroy(&nfcon_tty_port); + return res; + } + + if (!(nf_console.flags & CON_ENABLED)) + register_console(&nf_console); + + return 0; +} + +static void __exit nfcon_exit(void) +{ + unregister_console(&nf_console); + tty_unregister_driver(nfcon_tty_driver); + put_tty_driver(nfcon_tty_driver); + tty_port_destroy(&nfcon_tty_port); +} + +module_init(nfcon_init); +module_exit(nfcon_exit); + +MODULE_LICENSE("GPL"); diff --git a/arch/m68k/emu/nfeth.c b/arch/m68k/emu/nfeth.c new file mode 100644 index 000000000..79e55421c --- /dev/null +++ b/arch/m68k/emu/nfeth.c @@ -0,0 +1,265 @@ +/* + * atari_nfeth.c - ARAnyM ethernet card driver for GNU/Linux + * + * Copyright (c) 2005 Milan Jurik, Petr Stehlik of ARAnyM dev team + * + * Based on ARAnyM driver for FreeMiNT written by Standa Opichal + * + * This software may be used and distributed according to the terms of + * the GNU General Public License (GPL), incorporated herein by reference. + */ + +#define DRV_VERSION "0.3" +#define DRV_RELDATE "10/12/2005" + +#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt + +#include +#include +#include +#include +#include +#include + +enum { + GET_VERSION = 0,/* no parameters, return NFAPI_VERSION in d0 */ + XIF_INTLEVEL, /* no parameters, return Interrupt Level in d0 */ + XIF_IRQ, /* acknowledge interrupt from host */ + XIF_START, /* (ethX), called on 'ifup', start receiver thread */ + XIF_STOP, /* (ethX), called on 'ifdown', stop the thread */ + XIF_READLENGTH, /* (ethX), return size of network data block to read */ + XIF_READBLOCK, /* (ethX, buffer, size), read block of network data */ + XIF_WRITEBLOCK, /* (ethX, buffer, size), write block of network data */ + XIF_GET_MAC, /* (ethX, buffer, size), return MAC HW addr in buffer */ + XIF_GET_IPHOST, /* (ethX, buffer, size), return IP address of host */ + XIF_GET_IPATARI,/* (ethX, buffer, size), return IP address of atari */ + XIF_GET_NETMASK /* (ethX, buffer, size), return IP netmask */ +}; + +#define MAX_UNIT 8 + +/* These identify the driver base version and may not be removed. */ +static const char version[] = + KERN_INFO KBUILD_MODNAME ".c:v" DRV_VERSION " " DRV_RELDATE + " S.Opichal, M.Jurik, P.Stehlik\n" + KERN_INFO " http://aranym.org/\n"; + +MODULE_AUTHOR("Milan Jurik"); +MODULE_DESCRIPTION("Atari NFeth driver"); +MODULE_LICENSE("GPL"); + + +static long nfEtherID; +static int nfEtherIRQ; + +struct nfeth_private { + int ethX; +}; + +static struct net_device *nfeth_dev[MAX_UNIT]; + +static int nfeth_open(struct net_device *dev) +{ + struct nfeth_private *priv = netdev_priv(dev); + int res; + + res = nf_call(nfEtherID + XIF_START, priv->ethX); + netdev_dbg(dev, "%s: %d\n", __func__, res); + + /* Ready for data */ + netif_start_queue(dev); + + return 0; +} + +static int nfeth_stop(struct net_device *dev) +{ + struct nfeth_private *priv = netdev_priv(dev); + + /* No more data */ + netif_stop_queue(dev); + + nf_call(nfEtherID + XIF_STOP, priv->ethX); + + return 0; +} + +/* + * Read a packet out of the adapter and pass it to the upper layers + */ +static inline void recv_packet(struct net_device *dev) +{ + struct nfeth_private *priv = netdev_priv(dev); + unsigned short pktlen; + struct sk_buff *skb; + + /* read packet length (excluding 32 bit crc) */ + pktlen = nf_call(nfEtherID + XIF_READLENGTH, priv->ethX); + + netdev_dbg(dev, "%s: %u\n", __func__, pktlen); + + if (!pktlen) { + netdev_dbg(dev, "%s: pktlen == 0\n", __func__); + dev->stats.rx_errors++; + return; + } + + skb = dev_alloc_skb(pktlen + 2); + if (!skb) { + netdev_dbg(dev, "%s: out of mem (buf_alloc failed)\n", + __func__); + dev->stats.rx_dropped++; + return; + } + + skb->dev = dev; + skb_reserve(skb, 2); /* 16 Byte align */ + skb_put(skb, pktlen); /* make room */ + nf_call(nfEtherID + XIF_READBLOCK, priv->ethX, virt_to_phys(skb->data), + pktlen); + + skb->protocol = eth_type_trans(skb, dev); + netif_rx(skb); + dev->stats.rx_packets++; + dev->stats.rx_bytes += pktlen; + + /* and enqueue packet */ + return; +} + +static irqreturn_t nfeth_interrupt(int irq, void *dev_id) +{ + int i, m, mask; + + mask = nf_call(nfEtherID + XIF_IRQ, 0); + for (i = 0, m = 1; i < MAX_UNIT; m <<= 1, i++) { + if (mask & m && nfeth_dev[i]) { + recv_packet(nfeth_dev[i]); + nf_call(nfEtherID + XIF_IRQ, m); + } + } + return IRQ_HANDLED; +} + +static int nfeth_xmit(struct sk_buff *skb, struct net_device *dev) +{ + unsigned int len; + char *data, shortpkt[ETH_ZLEN]; + struct nfeth_private *priv = netdev_priv(dev); + + data = skb->data; + len = skb->len; + if (len < ETH_ZLEN) { + memset(shortpkt, 0, ETH_ZLEN); + memcpy(shortpkt, data, len); + data = shortpkt; + len = ETH_ZLEN; + } + + netdev_dbg(dev, "%s: send %u bytes\n", __func__, len); + nf_call(nfEtherID + XIF_WRITEBLOCK, priv->ethX, virt_to_phys(data), + len); + + dev->stats.tx_packets++; + dev->stats.tx_bytes += len; + + dev_kfree_skb(skb); + return 0; +} + +static void nfeth_tx_timeout(struct net_device *dev, unsigned int txqueue) +{ + dev->stats.tx_errors++; + netif_wake_queue(dev); +} + +static const struct net_device_ops nfeth_netdev_ops = { + .ndo_open = nfeth_open, + .ndo_stop = nfeth_stop, + .ndo_start_xmit = nfeth_xmit, + .ndo_tx_timeout = nfeth_tx_timeout, + .ndo_validate_addr = eth_validate_addr, + .ndo_set_mac_address = eth_mac_addr, +}; + +static struct net_device * __init nfeth_probe(int unit) +{ + struct net_device *dev; + struct nfeth_private *priv; + char mac[ETH_ALEN], host_ip[32], local_ip[32]; + int err; + + if (!nf_call(nfEtherID + XIF_GET_MAC, unit, virt_to_phys(mac), + ETH_ALEN)) + return NULL; + + dev = alloc_etherdev(sizeof(struct nfeth_private)); + if (!dev) + return NULL; + + dev->irq = nfEtherIRQ; + dev->netdev_ops = &nfeth_netdev_ops; + + memcpy(dev->dev_addr, mac, ETH_ALEN); + + priv = netdev_priv(dev); + priv->ethX = unit; + + err = register_netdev(dev); + if (err) { + free_netdev(dev); + return NULL; + } + + nf_call(nfEtherID + XIF_GET_IPHOST, unit, + virt_to_phys(host_ip), sizeof(host_ip)); + nf_call(nfEtherID + XIF_GET_IPATARI, unit, + virt_to_phys(local_ip), sizeof(local_ip)); + + netdev_info(dev, KBUILD_MODNAME " addr:%s (%s) HWaddr:%pM\n", host_ip, + local_ip, mac); + + return dev; +} + +static int __init nfeth_init(void) +{ + long ver; + int error, i; + + nfEtherID = nf_get_id("ETHERNET"); + if (!nfEtherID) + return -ENODEV; + + ver = nf_call(nfEtherID + GET_VERSION); + pr_info("API %lu\n", ver); + + nfEtherIRQ = nf_call(nfEtherID + XIF_INTLEVEL); + error = request_irq(nfEtherIRQ, nfeth_interrupt, IRQF_SHARED, + "eth emu", nfeth_interrupt); + if (error) { + pr_err("request for irq %d failed %d", nfEtherIRQ, error); + return error; + } + + for (i = 0; i < MAX_UNIT; i++) + nfeth_dev[i] = nfeth_probe(i); + + return 0; +} + +static void __exit nfeth_cleanup(void) +{ + int i; + + for (i = 0; i < MAX_UNIT; i++) { + if (nfeth_dev[i]) { + unregister_netdev(nfeth_dev[i]); + free_netdev(nfeth_dev[i]); + } + } + free_irq(nfEtherIRQ, nfeth_interrupt); +} + +module_init(nfeth_init); +module_exit(nfeth_cleanup); diff --git a/arch/m68k/fpsp040/Makefile b/arch/m68k/fpsp040/Makefile new file mode 100644 index 000000000..aab04d372 --- /dev/null +++ b/arch/m68k/fpsp040/Makefile @@ -0,0 +1,16 @@ +# SPDX-License-Identifier: GPL-2.0 +# +# Makefile for Linux arch/m68k/fpsp040 source directory +# + +obj-y := bindec.o binstr.o decbin.o do_func.o gen_except.o get_op.o \ + kernel_ex.o res_func.o round.o sacos.o sasin.o satan.o satanh.o \ + scosh.o setox.o sgetem.o sint.o slog2.o slogn.o \ + smovecr.o srem_mod.o scale.o \ + ssin.o ssinh.o stan.o stanh.o sto_res.o stwotox.o tbldo.o util.o \ + x_bsun.o x_fline.o x_operr.o x_ovfl.o x_snan.o x_store.o \ + x_unfl.o x_unimp.o x_unsupp.o bugfix.o skeleton.o + +EXTRA_LDFLAGS := -x + +$(OS_OBJS): fpsp.h diff --git a/arch/m68k/fpsp040/README b/arch/m68k/fpsp040/README new file mode 100644 index 000000000..f57494460 --- /dev/null +++ b/arch/m68k/fpsp040/README @@ -0,0 +1,30 @@ + +MOTOROLA MICROPROCESSOR & MEMORY TECHNOLOGY GROUP +M68000 Hi-Performance Microprocessor Division +M68040 Software Package + +M68040 Software Package Copyright (c) 1993, 1994 Motorola Inc. +All rights reserved. + +THE SOFTWARE is provided on an "AS IS" basis and without warranty. +To the maximum extent permitted by applicable law, +MOTOROLA DISCLAIMS ALL WARRANTIES WHETHER EXPRESS OR IMPLIED, +INCLUDING IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A +PARTICULAR PURPOSE and any warranty against infringement with +regard to the SOFTWARE (INCLUDING ANY MODIFIED VERSIONS THEREOF) +and any accompanying written materials. + +To the maximum extent permitted by applicable law, +IN NO EVENT SHALL MOTOROLA BE LIABLE FOR ANY DAMAGES WHATSOEVER +(INCLUDING WITHOUT LIMITATION, DAMAGES FOR LOSS OF BUSINESS +PROFITS, BUSINESS INTERRUPTION, LOSS OF BUSINESS INFORMATION, OR +OTHER PECUNIARY LOSS) ARISING OF THE USE OR INABILITY TO USE THE +SOFTWARE. Motorola assumes no responsibility for the maintenance +and support of the SOFTWARE. + +You are hereby granted a copyright license to use, modify, and +distribute the SOFTWARE so long as this entire notice is retained +without alteration in any modified and/or redistributed versions, +and that such modified versions are clearly identified as such. +No licenses are granted by implication, estoppel or otherwise +under any patents or trademarks of Motorola, Inc. diff --git a/arch/m68k/fpsp040/bindec.S b/arch/m68k/fpsp040/bindec.S new file mode 100644 index 000000000..f2e795231 --- /dev/null +++ b/arch/m68k/fpsp040/bindec.S @@ -0,0 +1,919 @@ +| +| bindec.sa 3.4 1/3/91 +| +| bindec +| +| Description: +| Converts an input in extended precision format +| to bcd format. +| +| Input: +| a0 points to the input extended precision value +| value in memory; d0 contains the k-factor sign-extended +| to 32-bits. The input may be either normalized, +| unnormalized, or denormalized. +| +| Output: result in the FP_SCR1 space on the stack. +| +| Saves and Modifies: D2-D7,A2,FP2 +| +| Algorithm: +| +| A1. Set RM and size ext; Set SIGMA = sign of input. +| The k-factor is saved for use in d7. Clear the +| BINDEC_FLG for separating normalized/denormalized +| input. If input is unnormalized or denormalized, +| normalize it. +| +| A2. Set X = abs(input). +| +| A3. Compute ILOG. +| ILOG is the log base 10 of the input value. It is +| approximated by adding e + 0.f when the original +| value is viewed as 2^^e * 1.f in extended precision. +| This value is stored in d6. +| +| A4. Clr INEX bit. +| The operation in A3 above may have set INEX2. +| +| A5. Set ICTR = 0; +| ICTR is a flag used in A13. It must be set before the +| loop entry A6. +| +| A6. Calculate LEN. +| LEN is the number of digits to be displayed. The +| k-factor can dictate either the total number of digits, +| if it is a positive number, or the number of digits +| after the decimal point which are to be included as +| significant. See the 68882 manual for examples. +| If LEN is computed to be greater than 17, set OPERR in +| USER_FPSR. LEN is stored in d4. +| +| A7. Calculate SCALE. +| SCALE is equal to 10^ISCALE, where ISCALE is the number +| of decimal places needed to insure LEN integer digits +| in the output before conversion to bcd. LAMBDA is the +| sign of ISCALE, used in A9. Fp1 contains +| 10^^(abs(ISCALE)) using a rounding mode which is a +| function of the original rounding mode and the signs +| of ISCALE and X. A table is given in the code. +| +| A8. Clr INEX; Force RZ. +| The operation in A3 above may have set INEX2. +| RZ mode is forced for the scaling operation to insure +| only one rounding error. The grs bits are collected in +| the INEX flag for use in A10. +| +| A9. Scale X -> Y. +| The mantissa is scaled to the desired number of +| significant digits. The excess digits are collected +| in INEX2. +| +| A10. Or in INEX. +| If INEX is set, round error occurred. This is +| compensated for by 'or-ing' in the INEX2 flag to +| the lsb of Y. +| +| A11. Restore original FPCR; set size ext. +| Perform FINT operation in the user's rounding mode. +| Keep the size to extended. +| +| A12. Calculate YINT = FINT(Y) according to user's rounding +| mode. The FPSP routine sintd0 is used. The output +| is in fp0. +| +| A13. Check for LEN digits. +| If the int operation results in more than LEN digits, +| or less than LEN -1 digits, adjust ILOG and repeat from +| A6. This test occurs only on the first pass. If the +| result is exactly 10^LEN, decrement ILOG and divide +| the mantissa by 10. +| +| A14. Convert the mantissa to bcd. +| The binstr routine is used to convert the LEN digit +| mantissa to bcd in memory. The input to binstr is +| to be a fraction; i.e. (mantissa)/10^LEN and adjusted +| such that the decimal point is to the left of bit 63. +| The bcd digits are stored in the correct position in +| the final string area in memory. +| +| A15. Convert the exponent to bcd. +| As in A14 above, the exp is converted to bcd and the +| digits are stored in the final string. +| Test the length of the final exponent string. If the +| length is 4, set operr. +| +| A16. Write sign bits to final string. +| +| Implementation Notes: +| +| The registers are used as follows: +| +| d0: scratch; LEN input to binstr +| d1: scratch +| d2: upper 32-bits of mantissa for binstr +| d3: scratch;lower 32-bits of mantissa for binstr +| d4: LEN +| d5: LAMBDA/ICTR +| d6: ILOG +| d7: k-factor +| a0: ptr for original operand/final result +| a1: scratch pointer +| a2: pointer to FP_X; abs(original value) in ext +| fp0: scratch +| fp1: scratch +| fp2: scratch +| F_SCR1: +| F_SCR2: +| L_SCR1: +| L_SCR2: + +| Copyright (C) Motorola, Inc. 1990 +| All Rights Reserved +| +| For details on the license for this file, please see the +| file, README, in this same directory. + +|BINDEC idnt 2,1 | Motorola 040 Floating Point Software Package + +#include "fpsp.h" + + |section 8 + +| Constants in extended precision +LOG2: .long 0x3FFD0000,0x9A209A84,0xFBCFF798,0x00000000 +LOG2UP1: .long 0x3FFD0000,0x9A209A84,0xFBCFF799,0x00000000 + +| Constants in single precision +FONE: .long 0x3F800000,0x00000000,0x00000000,0x00000000 +FTWO: .long 0x40000000,0x00000000,0x00000000,0x00000000 +FTEN: .long 0x41200000,0x00000000,0x00000000,0x00000000 +F4933: .long 0x459A2800,0x00000000,0x00000000,0x00000000 + +RBDTBL: .byte 0,0,0,0 + .byte 3,3,2,2 + .byte 3,2,2,3 + .byte 2,3,3,2 + + |xref binstr + |xref sintdo + |xref ptenrn,ptenrm,ptenrp + + .global bindec + .global sc_mul +bindec: + moveml %d2-%d7/%a2,-(%a7) + fmovemx %fp0-%fp2,-(%a7) + +| A1. Set RM and size ext. Set SIGMA = sign input; +| The k-factor is saved for use in d7. Clear BINDEC_FLG for +| separating normalized/denormalized input. If the input +| is a denormalized number, set the BINDEC_FLG memory word +| to signal denorm. If the input is unnormalized, normalize +| the input and test for denormalized result. +| + fmovel #rm_mode,%FPCR |set RM and ext + movel (%a0),L_SCR2(%a6) |save exponent for sign check + movel %d0,%d7 |move k-factor to d7 + clrb BINDEC_FLG(%a6) |clr norm/denorm flag + movew STAG(%a6),%d0 |get stag + andiw #0xe000,%d0 |isolate stag bits + beq A2_str |if zero, input is norm +| +| Normalize the denorm +| +un_de_norm: + movew (%a0),%d0 + andiw #0x7fff,%d0 |strip sign of normalized exp + movel 4(%a0),%d1 + movel 8(%a0),%d2 +norm_loop: + subw #1,%d0 + lsll #1,%d2 + roxll #1,%d1 + tstl %d1 + bges norm_loop +| +| Test if the normalized input is denormalized +| + tstw %d0 + bgts pos_exp |if greater than zero, it is a norm + st BINDEC_FLG(%a6) |set flag for denorm +pos_exp: + andiw #0x7fff,%d0 |strip sign of normalized exp + movew %d0,(%a0) + movel %d1,4(%a0) + movel %d2,8(%a0) + +| A2. Set X = abs(input). +| +A2_str: + movel (%a0),FP_SCR2(%a6) | move input to work space + movel 4(%a0),FP_SCR2+4(%a6) | move input to work space + movel 8(%a0),FP_SCR2+8(%a6) | move input to work space + andil #0x7fffffff,FP_SCR2(%a6) |create abs(X) + +| A3. Compute ILOG. +| ILOG is the log base 10 of the input value. It is approx- +| imated by adding e + 0.f when the original value is viewed +| as 2^^e * 1.f in extended precision. This value is stored +| in d6. +| +| Register usage: +| Input/Output +| d0: k-factor/exponent +| d2: x/x +| d3: x/x +| d4: x/x +| d5: x/x +| d6: x/ILOG +| d7: k-factor/Unchanged +| a0: ptr for original operand/final result +| a1: x/x +| a2: x/x +| fp0: x/float(ILOG) +| fp1: x/x +| fp2: x/x +| F_SCR1:x/x +| F_SCR2:Abs(X)/Abs(X) with $3fff exponent +| L_SCR1:x/x +| L_SCR2:first word of X packed/Unchanged + + tstb BINDEC_FLG(%a6) |check for denorm + beqs A3_cont |if clr, continue with norm + movel #-4933,%d6 |force ILOG = -4933 + bras A4_str +A3_cont: + movew FP_SCR2(%a6),%d0 |move exp to d0 + movew #0x3fff,FP_SCR2(%a6) |replace exponent with 0x3fff + fmovex FP_SCR2(%a6),%fp0 |now fp0 has 1.f + subw #0x3fff,%d0 |strip off bias + faddw %d0,%fp0 |add in exp + fsubs FONE,%fp0 |subtract off 1.0 + fbge pos_res |if pos, branch + fmulx LOG2UP1,%fp0 |if neg, mul by LOG2UP1 + fmovel %fp0,%d6 |put ILOG in d6 as a lword + bras A4_str |go move out ILOG +pos_res: + fmulx LOG2,%fp0 |if pos, mul by LOG2 + fmovel %fp0,%d6 |put ILOG in d6 as a lword + + +| A4. Clr INEX bit. +| The operation in A3 above may have set INEX2. + +A4_str: + fmovel #0,%FPSR |zero all of fpsr - nothing needed + + +| A5. Set ICTR = 0; +| ICTR is a flag used in A13. It must be set before the +| loop entry A6. The lower word of d5 is used for ICTR. + + clrw %d5 |clear ICTR + + +| A6. Calculate LEN. +| LEN is the number of digits to be displayed. The k-factor +| can dictate either the total number of digits, if it is +| a positive number, or the number of digits after the +| original decimal point which are to be included as +| significant. See the 68882 manual for examples. +| If LEN is computed to be greater than 17, set OPERR in +| USER_FPSR. LEN is stored in d4. +| +| Register usage: +| Input/Output +| d0: exponent/Unchanged +| d2: x/x/scratch +| d3: x/x +| d4: exc picture/LEN +| d5: ICTR/Unchanged +| d6: ILOG/Unchanged +| d7: k-factor/Unchanged +| a0: ptr for original operand/final result +| a1: x/x +| a2: x/x +| fp0: float(ILOG)/Unchanged +| fp1: x/x +| fp2: x/x +| F_SCR1:x/x +| F_SCR2:Abs(X) with $3fff exponent/Unchanged +| L_SCR1:x/x +| L_SCR2:first word of X packed/Unchanged + +A6_str: + tstl %d7 |branch on sign of k + bles k_neg |if k <= 0, LEN = ILOG + 1 - k + movel %d7,%d4 |if k > 0, LEN = k + bras len_ck |skip to LEN check +k_neg: + movel %d6,%d4 |first load ILOG to d4 + subl %d7,%d4 |subtract off k + addql #1,%d4 |add in the 1 +len_ck: + tstl %d4 |LEN check: branch on sign of LEN + bles LEN_ng |if neg, set LEN = 1 + cmpl #17,%d4 |test if LEN > 17 + bles A7_str |if not, forget it + movel #17,%d4 |set max LEN = 17 + tstl %d7 |if negative, never set OPERR + bles A7_str |if positive, continue + orl #opaop_mask,USER_FPSR(%a6) |set OPERR & AIOP in USER_FPSR + bras A7_str |finished here +LEN_ng: + moveql #1,%d4 |min LEN is 1 + + +| A7. Calculate SCALE. +| SCALE is equal to 10^ISCALE, where ISCALE is the number +| of decimal places needed to insure LEN integer digits +| in the output before conversion to bcd. LAMBDA is the sign +| of ISCALE, used in A9. Fp1 contains 10^^(abs(ISCALE)) using +| the rounding mode as given in the following table (see +| Coonen, p. 7.23 as ref.; however, the SCALE variable is +| of opposite sign in bindec.sa from Coonen). +| +| Initial USE +| FPCR[6:5] LAMBDA SIGN(X) FPCR[6:5] +| ---------------------------------------------- +| RN 00 0 0 00/0 RN +| RN 00 0 1 00/0 RN +| RN 00 1 0 00/0 RN +| RN 00 1 1 00/0 RN +| RZ 01 0 0 11/3 RP +| RZ 01 0 1 11/3 RP +| RZ 01 1 0 10/2 RM +| RZ 01 1 1 10/2 RM +| RM 10 0 0 11/3 RP +| RM 10 0 1 10/2 RM +| RM 10 1 0 10/2 RM +| RM 10 1 1 11/3 RP +| RP 11 0 0 10/2 RM +| RP 11 0 1 11/3 RP +| RP 11 1 0 11/3 RP +| RP 11 1 1 10/2 RM +| +| Register usage: +| Input/Output +| d0: exponent/scratch - final is 0 +| d2: x/0 or 24 for A9 +| d3: x/scratch - offset ptr into PTENRM array +| d4: LEN/Unchanged +| d5: 0/ICTR:LAMBDA +| d6: ILOG/ILOG or k if ((k<=0)&(ILOG 0, skip this + cmpl %d6,%d7 |test k - ILOG + blts k_pos |if ILOG >= k, skip this + movel %d7,%d6 |if ((k<0) & (ILOG < k)) ILOG = k +k_pos: + movel %d6,%d0 |calc ILOG + 1 - LEN in d0 + addql #1,%d0 |add the 1 + subl %d4,%d0 |sub off LEN + swap %d5 |use upper word of d5 for LAMBDA + clrw %d5 |set it zero initially + clrw %d2 |set up d2 for very small case + tstl %d0 |test sign of ISCALE + bges iscale |if pos, skip next inst + addqw #1,%d5 |if neg, set LAMBDA true + cmpl #0xffffecd4,%d0 |test iscale <= -4908 + bgts no_inf |if false, skip rest + addil #24,%d0 |add in 24 to iscale + movel #24,%d2 |put 24 in d2 for A9 +no_inf: + negl %d0 |and take abs of ISCALE +iscale: + fmoves FONE,%fp1 |init fp1 to 1 + bfextu USER_FPCR(%a6){#26:#2},%d1 |get initial rmode bits + lslw #1,%d1 |put them in bits 2:1 + addw %d5,%d1 |add in LAMBDA + lslw #1,%d1 |put them in bits 3:1 + tstl L_SCR2(%a6) |test sign of original x + bges x_pos |if pos, don't set bit 0 + addql #1,%d1 |if neg, set bit 0 +x_pos: + leal RBDTBL,%a2 |load rbdtbl base + moveb (%a2,%d1),%d3 |load d3 with new rmode + lsll #4,%d3 |put bits in proper position + fmovel %d3,%fpcr |load bits into fpu + lsrl #4,%d3 |put bits in proper position + tstb %d3 |decode new rmode for pten table + bnes not_rn |if zero, it is RN + leal PTENRN,%a1 |load a1 with RN table base + bras rmode |exit decode +not_rn: + lsrb #1,%d3 |get lsb in carry + bccs not_rp |if carry clear, it is RM + leal PTENRP,%a1 |load a1 with RP table base + bras rmode |exit decode +not_rp: + leal PTENRM,%a1 |load a1 with RM table base +rmode: + clrl %d3 |clr table index +e_loop: + lsrl #1,%d0 |shift next bit into carry + bccs e_next |if zero, skip the mul + fmulx (%a1,%d3),%fp1 |mul by 10**(d3_bit_no) +e_next: + addl #12,%d3 |inc d3 to next pwrten table entry + tstl %d0 |test if ISCALE is zero + bnes e_loop |if not, loop + + +| A8. Clr INEX; Force RZ. +| The operation in A3 above may have set INEX2. +| RZ mode is forced for the scaling operation to insure +| only one rounding error. The grs bits are collected in +| the INEX flag for use in A10. +| +| Register usage: +| Input/Output + + fmovel #0,%FPSR |clr INEX + fmovel #rz_mode,%FPCR |set RZ rounding mode + + +| A9. Scale X -> Y. +| The mantissa is scaled to the desired number of significant +| digits. The excess digits are collected in INEX2. If mul, +| Check d2 for excess 10 exponential value. If not zero, +| the iscale value would have caused the pwrten calculation +| to overflow. Only a negative iscale can cause this, so +| multiply by 10^(d2), which is now only allowed to be 24, +| with a multiply by 10^8 and 10^16, which is exact since +| 10^24 is exact. If the input was denormalized, we must +| create a busy stack frame with the mul command and the +| two operands, and allow the fpu to complete the multiply. +| +| Register usage: +| Input/Output +| d0: FPCR with RZ mode/Unchanged +| d2: 0 or 24/unchanged +| d3: x/x +| d4: LEN/Unchanged +| d5: ICTR:LAMBDA +| d6: ILOG/Unchanged +| d7: k-factor/Unchanged +| a0: ptr for original operand/final result +| a1: ptr to PTENRM array/Unchanged +| a2: x/x +| fp0: float(ILOG)/X adjusted for SCALE (Y) +| fp1: 10^ISCALE/Unchanged +| fp2: x/x +| F_SCR1:x/x +| F_SCR2:Abs(X) with $3fff exponent/Unchanged +| L_SCR1:x/x +| L_SCR2:first word of X packed/Unchanged + +A9_str: + fmovex (%a0),%fp0 |load X from memory + fabsx %fp0 |use abs(X) + tstw %d5 |LAMBDA is in lower word of d5 + bne sc_mul |if neg (LAMBDA = 1), scale by mul + fdivx %fp1,%fp0 |calculate X / SCALE -> Y to fp0 + bras A10_st |branch to A10 + +sc_mul: + tstb BINDEC_FLG(%a6) |check for denorm + beqs A9_norm |if norm, continue with mul + fmovemx %fp1-%fp1,-(%a7) |load ETEMP with 10^ISCALE + movel 8(%a0),-(%a7) |load FPTEMP with input arg + movel 4(%a0),-(%a7) + movel (%a0),-(%a7) + movel #18,%d3 |load count for busy stack +A9_loop: + clrl -(%a7) |clear lword on stack + dbf %d3,A9_loop + moveb VER_TMP(%a6),(%a7) |write current version number + moveb #BUSY_SIZE-4,1(%a7) |write current busy size + moveb #0x10,0x44(%a7) |set fcefpte[15] bit + movew #0x0023,0x40(%a7) |load cmdreg1b with mul command + moveb #0xfe,0x8(%a7) |load all 1s to cu savepc + frestore (%a7)+ |restore frame to fpu for completion + fmulx 36(%a1),%fp0 |multiply fp0 by 10^8 + fmulx 48(%a1),%fp0 |multiply fp0 by 10^16 + bras A10_st +A9_norm: + tstw %d2 |test for small exp case + beqs A9_con |if zero, continue as normal + fmulx 36(%a1),%fp0 |multiply fp0 by 10^8 + fmulx 48(%a1),%fp0 |multiply fp0 by 10^16 +A9_con: + fmulx %fp1,%fp0 |calculate X * SCALE -> Y to fp0 + + +| A10. Or in INEX. +| If INEX is set, round error occurred. This is compensated +| for by 'or-ing' in the INEX2 flag to the lsb of Y. +| +| Register usage: +| Input/Output +| d0: FPCR with RZ mode/FPSR with INEX2 isolated +| d2: x/x +| d3: x/x +| d4: LEN/Unchanged +| d5: ICTR:LAMBDA +| d6: ILOG/Unchanged +| d7: k-factor/Unchanged +| a0: ptr for original operand/final result +| a1: ptr to PTENxx array/Unchanged +| a2: x/ptr to FP_SCR2(a6) +| fp0: Y/Y with lsb adjusted +| fp1: 10^ISCALE/Unchanged +| fp2: x/x + +A10_st: + fmovel %FPSR,%d0 |get FPSR + fmovex %fp0,FP_SCR2(%a6) |move Y to memory + leal FP_SCR2(%a6),%a2 |load a2 with ptr to FP_SCR2 + btstl #9,%d0 |check if INEX2 set + beqs A11_st |if clear, skip rest + oril #1,8(%a2) |or in 1 to lsb of mantissa + fmovex FP_SCR2(%a6),%fp0 |write adjusted Y back to fpu + + +| A11. Restore original FPCR; set size ext. +| Perform FINT operation in the user's rounding mode. Keep +| the size to extended. The sintdo entry point in the sint +| routine expects the FPCR value to be in USER_FPCR for +| mode and precision. The original FPCR is saved in L_SCR1. + +A11_st: + movel USER_FPCR(%a6),L_SCR1(%a6) |save it for later + andil #0x00000030,USER_FPCR(%a6) |set size to ext, +| ;block exceptions + + +| A12. Calculate YINT = FINT(Y) according to user's rounding mode. +| The FPSP routine sintd0 is used. The output is in fp0. +| +| Register usage: +| Input/Output +| d0: FPSR with AINEX cleared/FPCR with size set to ext +| d2: x/x/scratch +| d3: x/x +| d4: LEN/Unchanged +| d5: ICTR:LAMBDA/Unchanged +| d6: ILOG/Unchanged +| d7: k-factor/Unchanged +| a0: ptr for original operand/src ptr for sintdo +| a1: ptr to PTENxx array/Unchanged +| a2: ptr to FP_SCR2(a6)/Unchanged +| a6: temp pointer to FP_SCR2(a6) - orig value saved and restored +| fp0: Y/YINT +| fp1: 10^ISCALE/Unchanged +| fp2: x/x +| F_SCR1:x/x +| F_SCR2:Y adjusted for inex/Y with original exponent +| L_SCR1:x/original USER_FPCR +| L_SCR2:first word of X packed/Unchanged + +A12_st: + moveml %d0-%d1/%a0-%a1,-(%a7) |save regs used by sintd0 + movel L_SCR1(%a6),-(%a7) + movel L_SCR2(%a6),-(%a7) + leal FP_SCR2(%a6),%a0 |a0 is ptr to F_SCR2(a6) + fmovex %fp0,(%a0) |move Y to memory at FP_SCR2(a6) + tstl L_SCR2(%a6) |test sign of original operand + bges do_fint |if pos, use Y + orl #0x80000000,(%a0) |if neg, use -Y +do_fint: + movel USER_FPSR(%a6),-(%a7) + bsr sintdo |sint routine returns int in fp0 + moveb (%a7),USER_FPSR(%a6) + addl #4,%a7 + movel (%a7)+,L_SCR2(%a6) + movel (%a7)+,L_SCR1(%a6) + moveml (%a7)+,%d0-%d1/%a0-%a1 |restore regs used by sint + movel L_SCR2(%a6),FP_SCR2(%a6) |restore original exponent + movel L_SCR1(%a6),USER_FPCR(%a6) |restore user's FPCR + + +| A13. Check for LEN digits. +| If the int operation results in more than LEN digits, +| or less than LEN -1 digits, adjust ILOG and repeat from +| A6. This test occurs only on the first pass. If the +| result is exactly 10^LEN, decrement ILOG and divide +| the mantissa by 10. The calculation of 10^LEN cannot +| be inexact, since all powers of ten up to 10^27 are exact +| in extended precision, so the use of a previous power-of-ten +| table will introduce no error. +| +| +| Register usage: +| Input/Output +| d0: FPCR with size set to ext/scratch final = 0 +| d2: x/x +| d3: x/scratch final = x +| d4: LEN/LEN adjusted +| d5: ICTR:LAMBDA/LAMBDA:ICTR +| d6: ILOG/ILOG adjusted +| d7: k-factor/Unchanged +| a0: pointer into memory for packed bcd string formation +| a1: ptr to PTENxx array/Unchanged +| a2: ptr to FP_SCR2(a6)/Unchanged +| fp0: int portion of Y/abs(YINT) adjusted +| fp1: 10^ISCALE/Unchanged +| fp2: x/10^LEN +| F_SCR1:x/x +| F_SCR2:Y with original exponent/Unchanged +| L_SCR1:original USER_FPCR/Unchanged +| L_SCR2:first word of X packed/Unchanged + +A13_st: + swap %d5 |put ICTR in lower word of d5 + tstw %d5 |check if ICTR = 0 + bne not_zr |if non-zero, go to second test +| +| Compute 10^(LEN-1) +| + fmoves FONE,%fp2 |init fp2 to 1.0 + movel %d4,%d0 |put LEN in d0 + subql #1,%d0 |d0 = LEN -1 + clrl %d3 |clr table index +l_loop: + lsrl #1,%d0 |shift next bit into carry + bccs l_next |if zero, skip the mul + fmulx (%a1,%d3),%fp2 |mul by 10**(d3_bit_no) +l_next: + addl #12,%d3 |inc d3 to next pwrten table entry + tstl %d0 |test if LEN is zero + bnes l_loop |if not, loop +| +| 10^LEN-1 is computed for this test and A14. If the input was +| denormalized, check only the case in which YINT > 10^LEN. +| + tstb BINDEC_FLG(%a6) |check if input was norm + beqs A13_con |if norm, continue with checking + fabsx %fp0 |take abs of YINT + bra test_2 +| +| Compare abs(YINT) to 10^(LEN-1) and 10^LEN +| +A13_con: + fabsx %fp0 |take abs of YINT + fcmpx %fp2,%fp0 |compare abs(YINT) with 10^(LEN-1) + fbge test_2 |if greater, do next test + subql #1,%d6 |subtract 1 from ILOG + movew #1,%d5 |set ICTR + fmovel #rm_mode,%FPCR |set rmode to RM + fmuls FTEN,%fp2 |compute 10^LEN + bra A6_str |return to A6 and recompute YINT +test_2: + fmuls FTEN,%fp2 |compute 10^LEN + fcmpx %fp2,%fp0 |compare abs(YINT) with 10^LEN + fblt A14_st |if less, all is ok, go to A14 + fbgt fix_ex |if greater, fix and redo + fdivs FTEN,%fp0 |if equal, divide by 10 + addql #1,%d6 | and inc ILOG + bras A14_st | and continue elsewhere +fix_ex: + addql #1,%d6 |increment ILOG by 1 + movew #1,%d5 |set ICTR + fmovel #rm_mode,%FPCR |set rmode to RM + bra A6_str |return to A6 and recompute YINT +| +| Since ICTR <> 0, we have already been through one adjustment, +| and shouldn't have another; this is to check if abs(YINT) = 10^LEN +| 10^LEN is again computed using whatever table is in a1 since the +| value calculated cannot be inexact. +| +not_zr: + fmoves FONE,%fp2 |init fp2 to 1.0 + movel %d4,%d0 |put LEN in d0 + clrl %d3 |clr table index +z_loop: + lsrl #1,%d0 |shift next bit into carry + bccs z_next |if zero, skip the mul + fmulx (%a1,%d3),%fp2 |mul by 10**(d3_bit_no) +z_next: + addl #12,%d3 |inc d3 to next pwrten table entry + tstl %d0 |test if LEN is zero + bnes z_loop |if not, loop + fabsx %fp0 |get abs(YINT) + fcmpx %fp2,%fp0 |check if abs(YINT) = 10^LEN + fbne A14_st |if not, skip this + fdivs FTEN,%fp0 |divide abs(YINT) by 10 + addql #1,%d6 |and inc ILOG by 1 + addql #1,%d4 | and inc LEN + fmuls FTEN,%fp2 | if LEN++, the get 10^^LEN + + +| A14. Convert the mantissa to bcd. +| The binstr routine is used to convert the LEN digit +| mantissa to bcd in memory. The input to binstr is +| to be a fraction; i.e. (mantissa)/10^LEN and adjusted +| such that the decimal point is to the left of bit 63. +| The bcd digits are stored in the correct position in +| the final string area in memory. +| +| +| Register usage: +| Input/Output +| d0: x/LEN call to binstr - final is 0 +| d1: x/0 +| d2: x/ms 32-bits of mant of abs(YINT) +| d3: x/ls 32-bits of mant of abs(YINT) +| d4: LEN/Unchanged +| d5: ICTR:LAMBDA/LAMBDA:ICTR +| d6: ILOG +| d7: k-factor/Unchanged +| a0: pointer into memory for packed bcd string formation +| /ptr to first mantissa byte in result string +| a1: ptr to PTENxx array/Unchanged +| a2: ptr to FP_SCR2(a6)/Unchanged +| fp0: int portion of Y/abs(YINT) adjusted +| fp1: 10^ISCALE/Unchanged +| fp2: 10^LEN/Unchanged +| F_SCR1:x/Work area for final result +| F_SCR2:Y with original exponent/Unchanged +| L_SCR1:original USER_FPCR/Unchanged +| L_SCR2:first word of X packed/Unchanged + +A14_st: + fmovel #rz_mode,%FPCR |force rz for conversion + fdivx %fp2,%fp0 |divide abs(YINT) by 10^LEN + leal FP_SCR1(%a6),%a0 + fmovex %fp0,(%a0) |move abs(YINT)/10^LEN to memory + movel 4(%a0),%d2 |move 2nd word of FP_RES to d2 + movel 8(%a0),%d3 |move 3rd word of FP_RES to d3 + clrl 4(%a0) |zero word 2 of FP_RES + clrl 8(%a0) |zero word 3 of FP_RES + movel (%a0),%d0 |move exponent to d0 + swap %d0 |put exponent in lower word + beqs no_sft |if zero, don't shift + subil #0x3ffd,%d0 |sub bias less 2 to make fract + tstl %d0 |check if > 1 + bgts no_sft |if so, don't shift + negl %d0 |make exp positive +m_loop: + lsrl #1,%d2 |shift d2:d3 right, add 0s + roxrl #1,%d3 |the number of places + dbf %d0,m_loop |given in d0 +no_sft: + tstl %d2 |check for mantissa of zero + bnes no_zr |if not, go on + tstl %d3 |continue zero check + beqs zer_m |if zero, go directly to binstr +no_zr: + clrl %d1 |put zero in d1 for addx + addil #0x00000080,%d3 |inc at bit 7 + addxl %d1,%d2 |continue inc + andil #0xffffff80,%d3 |strip off lsb not used by 882 +zer_m: + movel %d4,%d0 |put LEN in d0 for binstr call + addql #3,%a0 |a0 points to M16 byte in result + bsr binstr |call binstr to convert mant + + +| A15. Convert the exponent to bcd. +| As in A14 above, the exp is converted to bcd and the +| digits are stored in the final string. +| +| Digits are stored in L_SCR1(a6) on return from BINDEC as: +| +| 32 16 15 0 +| ----------------------------------------- +| | 0 | e3 | e2 | e1 | e4 | X | X | X | +| ----------------------------------------- +| +| And are moved into their proper places in FP_SCR1. If digit e4 +| is non-zero, OPERR is signaled. In all cases, all 4 digits are +| written as specified in the 881/882 manual for packed decimal. +| +| Register usage: +| Input/Output +| d0: x/LEN call to binstr - final is 0 +| d1: x/scratch (0);shift count for final exponent packing +| d2: x/ms 32-bits of exp fraction/scratch +| d3: x/ls 32-bits of exp fraction +| d4: LEN/Unchanged +| d5: ICTR:LAMBDA/LAMBDA:ICTR +| d6: ILOG +| d7: k-factor/Unchanged +| a0: ptr to result string/ptr to L_SCR1(a6) +| a1: ptr to PTENxx array/Unchanged +| a2: ptr to FP_SCR2(a6)/Unchanged +| fp0: abs(YINT) adjusted/float(ILOG) +| fp1: 10^ISCALE/Unchanged +| fp2: 10^LEN/Unchanged +| F_SCR1:Work area for final result/BCD result +| F_SCR2:Y with original exponent/ILOG/10^4 +| L_SCR1:original USER_FPCR/Exponent digits on return from binstr +| L_SCR2:first word of X packed/Unchanged + +A15_st: + tstb BINDEC_FLG(%a6) |check for denorm + beqs not_denorm + ftstx %fp0 |test for zero + fbeq den_zero |if zero, use k-factor or 4933 + fmovel %d6,%fp0 |float ILOG + fabsx %fp0 |get abs of ILOG + bras convrt +den_zero: + tstl %d7 |check sign of the k-factor + blts use_ilog |if negative, use ILOG + fmoves F4933,%fp0 |force exponent to 4933 + bras convrt |do it +use_ilog: + fmovel %d6,%fp0 |float ILOG + fabsx %fp0 |get abs of ILOG + bras convrt +not_denorm: + ftstx %fp0 |test for zero + fbne not_zero |if zero, force exponent + fmoves FONE,%fp0 |force exponent to 1 + bras convrt |do it +not_zero: + fmovel %d6,%fp0 |float ILOG + fabsx %fp0 |get abs of ILOG +convrt: + fdivx 24(%a1),%fp0 |compute ILOG/10^4 + fmovex %fp0,FP_SCR2(%a6) |store fp0 in memory + movel 4(%a2),%d2 |move word 2 to d2 + movel 8(%a2),%d3 |move word 3 to d3 + movew (%a2),%d0 |move exp to d0 + beqs x_loop_fin |if zero, skip the shift + subiw #0x3ffd,%d0 |subtract off bias + negw %d0 |make exp positive +x_loop: + lsrl #1,%d2 |shift d2:d3 right + roxrl #1,%d3 |the number of places + dbf %d0,x_loop |given in d0 +x_loop_fin: + clrl %d1 |put zero in d1 for addx + addil #0x00000080,%d3 |inc at bit 6 + addxl %d1,%d2 |continue inc + andil #0xffffff80,%d3 |strip off lsb not used by 882 + movel #4,%d0 |put 4 in d0 for binstr call + leal L_SCR1(%a6),%a0 |a0 is ptr to L_SCR1 for exp digits + bsr binstr |call binstr to convert exp + movel L_SCR1(%a6),%d0 |load L_SCR1 lword to d0 + movel #12,%d1 |use d1 for shift count + lsrl %d1,%d0 |shift d0 right by 12 + bfins %d0,FP_SCR1(%a6){#4:#12} |put e3:e2:e1 in FP_SCR1 + lsrl %d1,%d0 |shift d0 right by 12 + bfins %d0,FP_SCR1(%a6){#16:#4} |put e4 in FP_SCR1 + tstb %d0 |check if e4 is zero + beqs A16_st |if zero, skip rest + orl #opaop_mask,USER_FPSR(%a6) |set OPERR & AIOP in USER_FPSR + + +| A16. Write sign bits to final string. +| Sigma is bit 31 of initial value; RHO is bit 31 of d6 (ILOG). +| +| Register usage: +| Input/Output +| d0: x/scratch - final is x +| d2: x/x +| d3: x/x +| d4: LEN/Unchanged +| d5: ICTR:LAMBDA/LAMBDA:ICTR +| d6: ILOG/ILOG adjusted +| d7: k-factor/Unchanged +| a0: ptr to L_SCR1(a6)/Unchanged +| a1: ptr to PTENxx array/Unchanged +| a2: ptr to FP_SCR2(a6)/Unchanged +| fp0: float(ILOG)/Unchanged +| fp1: 10^ISCALE/Unchanged +| fp2: 10^LEN/Unchanged +| F_SCR1:BCD result with correct signs +| F_SCR2:ILOG/10^4 +| L_SCR1:Exponent digits on return from binstr +| L_SCR2:first word of X packed/Unchanged + +A16_st: + clrl %d0 |clr d0 for collection of signs + andib #0x0f,FP_SCR1(%a6) |clear first nibble of FP_SCR1 + tstl L_SCR2(%a6) |check sign of original mantissa + bges mant_p |if pos, don't set SM + moveql #2,%d0 |move 2 in to d0 for SM +mant_p: + tstl %d6 |check sign of ILOG + bges wr_sgn |if pos, don't set SE + addql #1,%d0 |set bit 0 in d0 for SE +wr_sgn: + bfins %d0,FP_SCR1(%a6){#0:#2} |insert SM and SE into FP_SCR1 + +| Clean up and restore all registers used. + + fmovel #0,%FPSR |clear possible inex2/ainex bits + fmovemx (%a7)+,%fp0-%fp2 + moveml (%a7)+,%d2-%d7/%a2 + rts + + |end diff --git a/arch/m68k/fpsp040/binstr.S b/arch/m68k/fpsp040/binstr.S new file mode 100644 index 000000000..8a05ba92a --- /dev/null +++ b/arch/m68k/fpsp040/binstr.S @@ -0,0 +1,139 @@ +| +| binstr.sa 3.3 12/19/90 +| +| +| Description: Converts a 64-bit binary integer to bcd. +| +| Input: 64-bit binary integer in d2:d3, desired length (LEN) in +| d0, and a pointer to start in memory for bcd characters +| in d0. (This pointer must point to byte 4 of the first +| lword of the packed decimal memory string.) +| +| Output: LEN bcd digits representing the 64-bit integer. +| +| Algorithm: +| The 64-bit binary is assumed to have a decimal point before +| bit 63. The fraction is multiplied by 10 using a mul by 2 +| shift and a mul by 8 shift. The bits shifted out of the +| msb form a decimal digit. This process is iterated until +| LEN digits are formed. +| +| A1. Init d7 to 1. D7 is the byte digit counter, and if 1, the +| digit formed will be assumed the least significant. This is +| to force the first byte formed to have a 0 in the upper 4 bits. +| +| A2. Beginning of the loop: +| Copy the fraction in d2:d3 to d4:d5. +| +| A3. Multiply the fraction in d2:d3 by 8 using bit-field +| extracts and shifts. The three msbs from d2 will go into +| d1. +| +| A4. Multiply the fraction in d4:d5 by 2 using shifts. The msb +| will be collected by the carry. +| +| A5. Add using the carry the 64-bit quantities in d2:d3 and d4:d5 +| into d2:d3. D1 will contain the bcd digit formed. +| +| A6. Test d7. If zero, the digit formed is the ms digit. If non- +| zero, it is the ls digit. Put the digit in its place in the +| upper word of d0. If it is the ls digit, write the word +| from d0 to memory. +| +| A7. Decrement d6 (LEN counter) and repeat the loop until zero. +| +| Implementation Notes: +| +| The registers are used as follows: +| +| d0: LEN counter +| d1: temp used to form the digit +| d2: upper 32-bits of fraction for mul by 8 +| d3: lower 32-bits of fraction for mul by 8 +| d4: upper 32-bits of fraction for mul by 2 +| d5: lower 32-bits of fraction for mul by 2 +| d6: temp for bit-field extracts +| d7: byte digit formation word;digit count {0,1} +| a0: pointer into memory for packed bcd string formation +| + +| Copyright (C) Motorola, Inc. 1990 +| All Rights Reserved +| +| For details on the license for this file, please see the +| file, README, in this same directory. + +|BINSTR idnt 2,1 | Motorola 040 Floating Point Software Package + + |section 8 + +#include "fpsp.h" + + .global binstr +binstr: + moveml %d0-%d7,-(%a7) +| +| A1: Init d7 +| + moveql #1,%d7 |init d7 for second digit + subql #1,%d0 |for dbf d0 would have LEN+1 passes +| +| A2. Copy d2:d3 to d4:d5. Start loop. +| +loop: + movel %d2,%d4 |copy the fraction before muls + movel %d3,%d5 |to d4:d5 +| +| A3. Multiply d2:d3 by 8; extract msbs into d1. +| + bfextu %d2{#0:#3},%d1 |copy 3 msbs of d2 into d1 + asll #3,%d2 |shift d2 left by 3 places + bfextu %d3{#0:#3},%d6 |copy 3 msbs of d3 into d6 + asll #3,%d3 |shift d3 left by 3 places + orl %d6,%d2 |or in msbs from d3 into d2 +| +| A4. Multiply d4:d5 by 2; add carry out to d1. +| + asll #1,%d5 |mul d5 by 2 + roxll #1,%d4 |mul d4 by 2 + swap %d6 |put 0 in d6 lower word + addxw %d6,%d1 |add in extend from mul by 2 +| +| A5. Add mul by 8 to mul by 2. D1 contains the digit formed. +| + addl %d5,%d3 |add lower 32 bits + nop |ERRATA ; FIX #13 (Rev. 1.2 6/6/90) + addxl %d4,%d2 |add with extend upper 32 bits + nop |ERRATA ; FIX #13 (Rev. 1.2 6/6/90) + addxw %d6,%d1 |add in extend from add to d1 + swap %d6 |with d6 = 0; put 0 in upper word +| +| A6. Test d7 and branch. +| + tstw %d7 |if zero, store digit & to loop + beqs first_d |if non-zero, form byte & write +sec_d: + swap %d7 |bring first digit to word d7b + aslw #4,%d7 |first digit in upper 4 bits d7b + addw %d1,%d7 |add in ls digit to d7b + moveb %d7,(%a0)+ |store d7b byte in memory + swap %d7 |put LEN counter in word d7a + clrw %d7 |set d7a to signal no digits done + dbf %d0,loop |do loop some more! + bras end_bstr |finished, so exit +first_d: + swap %d7 |put digit word in d7b + movew %d1,%d7 |put new digit in d7b + swap %d7 |put LEN counter in word d7a + addqw #1,%d7 |set d7a to signal first digit done + dbf %d0,loop |do loop some more! + swap %d7 |put last digit in string + lslw #4,%d7 |move it to upper 4 bits + moveb %d7,(%a0)+ |store it in memory string +| +| Clean up and return with result in fp0. +| +end_bstr: + moveml (%a7)+,%d0-%d7 + rts + |end diff --git a/arch/m68k/fpsp040/bugfix.S b/arch/m68k/fpsp040/bugfix.S new file mode 100644 index 000000000..3bb9c84bb --- /dev/null +++ b/arch/m68k/fpsp040/bugfix.S @@ -0,0 +1,495 @@ +| +| bugfix.sa 3.2 1/31/91 +| +| +| This file contains workarounds for bugs in the 040 +| relating to the Floating-Point Software Package (FPSP) +| +| Fixes for bugs: 1238 +| +| Bug: 1238 +| +| +| /* The following dirty_bit clear should be left in +| * the handler permanently to improve throughput. +| * The dirty_bits are located at bits [23:16] in +| * longword $08 in the busy frame $4x60. Bit 16 +| * corresponds to FP0, bit 17 corresponds to FP1, +| * and so on. +| */ +| if (E3_exception_just_serviced) { +| dirty_bit[cmdreg3b[9:7]] = 0; +| } +| +| if (fsave_format_version != $40) {goto NOFIX} +| +| if !(E3_exception_just_serviced) {goto NOFIX} +| if (cupc == 0000000) {goto NOFIX} +| if ((cmdreg1b[15:13] != 000) && +| (cmdreg1b[15:10] != 010001)) {goto NOFIX} +| if (((cmdreg1b[15:13] != 000) || ((cmdreg1b[12:10] != cmdreg2b[9:7]) && +| (cmdreg1b[12:10] != cmdreg3b[9:7])) ) && +| ((cmdreg1b[ 9: 7] != cmdreg2b[9:7]) && +| (cmdreg1b[ 9: 7] != cmdreg3b[9:7])) ) {goto NOFIX} +| +| /* Note: for 6d43b or 8d43b, you may want to add the following code +| * to get better coverage. (If you do not insert this code, the part +| * won't lock up; it will simply get the wrong answer.) +| * Do NOT insert this code for 10d43b or later parts. +| * +| * if (fpiarcu == integer stack return address) { +| * cupc = 0000000; +| * goto NOFIX; +| * } +| */ +| +| if (cmdreg1b[15:13] != 000) {goto FIX_OPCLASS2} +| FIX_OPCLASS0: +| if (((cmdreg1b[12:10] == cmdreg2b[9:7]) || +| (cmdreg1b[ 9: 7] == cmdreg2b[9:7])) && +| (cmdreg1b[12:10] != cmdreg3b[9:7]) && +| (cmdreg1b[ 9: 7] != cmdreg3b[9:7])) { /* xu conflict only */ +| /* We execute the following code if there is an +| xu conflict and NOT an nu conflict */ +| +| /* first save some values on the fsave frame */ +| stag_temp = STAG[fsave_frame]; +| cmdreg1b_temp = CMDREG1B[fsave_frame]; +| dtag_temp = DTAG[fsave_frame]; +| ete15_temp = ETE15[fsave_frame]; +| +| CUPC[fsave_frame] = 0000000; +| FRESTORE +| FSAVE +| +| /* If the xu instruction is exceptional, we punt. +| * Otherwise, we would have to include OVFL/UNFL handler +| * code here to get the correct answer. +| */ +| if (fsave_frame_format == $4060) {goto KILL_PROCESS} +| +| fsave_frame = /* build a long frame of all zeros */ +| fsave_frame_format = $4060; /* label it as long frame */ +| +| /* load it with the temps we saved */ +| STAG[fsave_frame] = stag_temp; +| CMDREG1B[fsave_frame] = cmdreg1b_temp; +| DTAG[fsave_frame] = dtag_temp; +| ETE15[fsave_frame] = ete15_temp; +| +| /* Make sure that the cmdreg3b dest reg is not going to +| * be destroyed by a FMOVEM at the end of all this code. +| * If it is, you should move the current value of the reg +| * onto the stack so that the reg will loaded with that value. +| */ +| +| /* All done. Proceed with the code below */ +| } +| +| etemp = FP_reg_[cmdreg1b[12:10]]; +| ete15 = ~ete14; +| cmdreg1b[15:10] = 010010; +| clear(bug_flag_procIDxxxx); +| FRESTORE and return; +| +| +| FIX_OPCLASS2: +| if ((cmdreg1b[9:7] == cmdreg2b[9:7]) && +| (cmdreg1b[9:7] != cmdreg3b[9:7])) { /* xu conflict only */ +| /* We execute the following code if there is an +| xu conflict and NOT an nu conflict */ +| +| /* first save some values on the fsave frame */ +| stag_temp = STAG[fsave_frame]; +| cmdreg1b_temp = CMDREG1B[fsave_frame]; +| dtag_temp = DTAG[fsave_frame]; +| ete15_temp = ETE15[fsave_frame]; +| etemp_temp = ETEMP[fsave_frame]; +| +| CUPC[fsave_frame] = 0000000; +| FRESTORE +| FSAVE +| +| +| /* If the xu instruction is exceptional, we punt. +| * Otherwise, we would have to include OVFL/UNFL handler +| * code here to get the correct answer. +| */ +| if (fsave_frame_format == $4060) {goto KILL_PROCESS} +| +| fsave_frame = /* build a long frame of all zeros */ +| fsave_frame_format = $4060; /* label it as long frame */ +| +| /* load it with the temps we saved */ +| STAG[fsave_frame] = stag_temp; +| CMDREG1B[fsave_frame] = cmdreg1b_temp; +| DTAG[fsave_frame] = dtag_temp; +| ETE15[fsave_frame] = ete15_temp; +| ETEMP[fsave_frame] = etemp_temp; +| +| /* Make sure that the cmdreg3b dest reg is not going to +| * be destroyed by a FMOVEM at the end of all this code. +| * If it is, you should move the current value of the reg +| * onto the stack so that the reg will loaded with that value. +| */ +| +| /* All done. Proceed with the code below */ +| } +| +| if (etemp_exponent == min_sgl) etemp_exponent = min_dbl; +| if (etemp_exponent == max_sgl) etemp_exponent = max_dbl; +| cmdreg1b[15:10] = 010101; +| clear(bug_flag_procIDxxxx); +| FRESTORE and return; +| +| +| NOFIX: +| clear(bug_flag_procIDxxxx); +| FRESTORE and return; +| + + +| Copyright (C) Motorola, Inc. 1990 +| All Rights Reserved +| +| For details on the license for this file, please see the +| file, README, in this same directory. + +|BUGFIX idnt 2,1 | Motorola 040 Floating Point Software Package + + |section 8 + +#include "fpsp.h" + + |xref fpsp_fmt_error + + .global b1238_fix +b1238_fix: +| +| This code is entered only on completion of the handling of an +| nu-generated ovfl, unfl, or inex exception. If the version +| number of the fsave is not $40, this handler is not necessary. +| Simply branch to fix_done and exit normally. +| + cmpib #VER_40,4(%a7) + bne fix_done +| +| Test for cu_savepc equal to zero. If not, this is not a bug +| #1238 case. +| + moveb CU_SAVEPC(%a6),%d0 + andib #0xFE,%d0 + beq fix_done |if zero, this is not bug #1238 + +| +| Test the register conflict aspect. If opclass0, check for +| cu src equal to xu dest or equal to nu dest. If so, go to +| op0. Else, or if opclass2, check for cu dest equal to +| xu dest or equal to nu dest. If so, go to tst_opcl. Else, +| exit, it is not the bug case. +| +| Check for opclass 0. If not, go and check for opclass 2 and sgl. +| + movew CMDREG1B(%a6),%d0 + andiw #0xE000,%d0 |strip all but opclass + bne op2sgl |not opclass 0, check op2 +| +| Check for cu and nu register conflict. If one exists, this takes +| priority over a cu and xu conflict. +| + bfextu CMDREG1B(%a6){#3:#3},%d0 |get 1st src + bfextu CMDREG3B(%a6){#6:#3},%d1 |get 3rd dest + cmpb %d0,%d1 + beqs op0 |if equal, continue bugfix +| +| Check for cu dest equal to nu dest. If so, go and fix the +| bug condition. Otherwise, exit. +| + bfextu CMDREG1B(%a6){#6:#3},%d0 |get 1st dest + cmpb %d0,%d1 |cmp 1st dest with 3rd dest + beqs op0 |if equal, continue bugfix +| +| Check for cu and xu register conflict. +| + bfextu CMDREG2B(%a6){#6:#3},%d1 |get 2nd dest + cmpb %d0,%d1 |cmp 1st dest with 2nd dest + beqs op0_xu |if equal, continue bugfix + bfextu CMDREG1B(%a6){#3:#3},%d0 |get 1st src + cmpb %d0,%d1 |cmp 1st src with 2nd dest + beq op0_xu + bne fix_done |if the reg checks fail, exit +| +| We have the opclass 0 situation. +| +op0: + bfextu CMDREG1B(%a6){#3:#3},%d0 |get source register no + movel #7,%d1 + subl %d0,%d1 + clrl %d0 + bsetl %d1,%d0 + fmovemx %d0,ETEMP(%a6) |load source to ETEMP + + moveb #0x12,%d0 + bfins %d0,CMDREG1B(%a6){#0:#6} |opclass 2, extended +| +| Set ETEMP exponent bit 15 as the opposite of ete14 +| + btst #6,ETEMP_EX(%a6) |check etemp exponent bit 14 + beq setete15 + bclr #etemp15_bit,STAG(%a6) + bra finish +setete15: + bset #etemp15_bit,STAG(%a6) + bra finish + +| +| We have the case in which a conflict exists between the cu src or +| dest and the dest of the xu. We must clear the instruction in +| the cu and restore the state, allowing the instruction in the +| xu to complete. Remember, the instruction in the nu +| was exceptional, and was completed by the appropriate handler. +| If the result of the xu instruction is not exceptional, we can +| restore the instruction from the cu to the frame and continue +| processing the original exception. If the result is also +| exceptional, we choose to kill the process. +| +| Items saved from the stack: +| +| $3c stag - L_SCR1 +| $40 cmdreg1b - L_SCR2 +| $44 dtag - L_SCR3 +| +| The cu savepc is set to zero, and the frame is restored to the +| fpu. +| +op0_xu: + movel STAG(%a6),L_SCR1(%a6) + movel CMDREG1B(%a6),L_SCR2(%a6) + movel DTAG(%a6),L_SCR3(%a6) + andil #0xe0000000,L_SCR3(%a6) + moveb #0,CU_SAVEPC(%a6) + movel (%a7)+,%d1 |save return address from bsr + frestore (%a7)+ + fsave -(%a7) +| +| Check if the instruction which just completed was exceptional. +| + cmpw #0x4060,(%a7) + beq op0_xb +| +| It is necessary to isolate the result of the instruction in the +| xu if it is to fp0 - fp3 and write that value to the USER_FPn +| locations on the stack. The correct destination register is in +| cmdreg2b. +| + bfextu CMDREG2B(%a6){#6:#3},%d0 |get dest register no + cmpil #3,%d0 + bgts op0_xi + beqs op0_fp3 + cmpil #1,%d0 + blts op0_fp0 + beqs op0_fp1 +op0_fp2: + fmovemx %fp2-%fp2,USER_FP2(%a6) + bras op0_xi +op0_fp1: + fmovemx %fp1-%fp1,USER_FP1(%a6) + bras op0_xi +op0_fp0: + fmovemx %fp0-%fp0,USER_FP0(%a6) + bras op0_xi +op0_fp3: + fmovemx %fp3-%fp3,USER_FP3(%a6) +| +| The frame returned is idle. We must build a busy frame to hold +| the cu state information and setup etemp. +| +op0_xi: + movel #22,%d0 |clear 23 lwords + clrl (%a7) +op0_loop: + clrl -(%a7) + dbf %d0,op0_loop + movel #0x40600000,-(%a7) + movel L_SCR1(%a6),STAG(%a6) + movel L_SCR2(%a6),CMDREG1B(%a6) + movel L_SCR3(%a6),DTAG(%a6) + moveb #0x6,CU_SAVEPC(%a6) + movel %d1,-(%a7) |return bsr return address + bfextu CMDREG1B(%a6){#3:#3},%d0 |get source register no + movel #7,%d1 + subl %d0,%d1 + clrl %d0 + bsetl %d1,%d0 + fmovemx %d0,ETEMP(%a6) |load source to ETEMP + + moveb #0x12,%d0 + bfins %d0,CMDREG1B(%a6){#0:#6} |opclass 2, extended +| +| Set ETEMP exponent bit 15 as the opposite of ete14 +| + btst #6,ETEMP_EX(%a6) |check etemp exponent bit 14 + beq op0_sete15 + bclr #etemp15_bit,STAG(%a6) + bra finish +op0_sete15: + bset #etemp15_bit,STAG(%a6) + bra finish + +| +| The frame returned is busy. It is not possible to reconstruct +| the code sequence to allow completion. We will jump to +| fpsp_fmt_error and allow the kernel to kill the process. +| +op0_xb: + jmp fpsp_fmt_error + +| +| Check for opclass 2 and single size. If not both, exit. +| +op2sgl: + movew CMDREG1B(%a6),%d0 + andiw #0xFC00,%d0 |strip all but opclass and size + cmpiw #0x4400,%d0 |test for opclass 2 and size=sgl + bne fix_done |if not, it is not bug 1238 +| +| Check for cu dest equal to nu dest or equal to xu dest, with +| a cu and nu conflict taking priority an nu conflict. If either, +| go and fix the bug condition. Otherwise, exit. +| + bfextu CMDREG1B(%a6){#6:#3},%d0 |get 1st dest + bfextu CMDREG3B(%a6){#6:#3},%d1 |get 3rd dest + cmpb %d0,%d1 |cmp 1st dest with 3rd dest + beq op2_com |if equal, continue bugfix + bfextu CMDREG2B(%a6){#6:#3},%d1 |get 2nd dest + cmpb %d0,%d1 |cmp 1st dest with 2nd dest + bne fix_done |if the reg checks fail, exit +| +| We have the case in which a conflict exists between the cu src or +| dest and the dest of the xu. We must clear the instruction in +| the cu and restore the state, allowing the instruction in the +| xu to complete. Remember, the instruction in the nu +| was exceptional, and was completed by the appropriate handler. +| If the result of the xu instruction is not exceptional, we can +| restore the instruction from the cu to the frame and continue +| processing the original exception. If the result is also +| exceptional, we choose to kill the process. +| +| Items saved from the stack: +| +| $3c stag - L_SCR1 +| $40 cmdreg1b - L_SCR2 +| $44 dtag - L_SCR3 +| etemp - FP_SCR2 +| +| The cu savepc is set to zero, and the frame is restored to the +| fpu. +| +op2_xu: + movel STAG(%a6),L_SCR1(%a6) + movel CMDREG1B(%a6),L_SCR2(%a6) + movel DTAG(%a6),L_SCR3(%a6) + andil #0xe0000000,L_SCR3(%a6) + moveb #0,CU_SAVEPC(%a6) + movel ETEMP(%a6),FP_SCR2(%a6) + movel ETEMP_HI(%a6),FP_SCR2+4(%a6) + movel ETEMP_LO(%a6),FP_SCR2+8(%a6) + movel (%a7)+,%d1 |save return address from bsr + frestore (%a7)+ + fsave -(%a7) +| +| Check if the instruction which just completed was exceptional. +| + cmpw #0x4060,(%a7) + beq op2_xb +| +| It is necessary to isolate the result of the instruction in the +| xu if it is to fp0 - fp3 and write that value to the USER_FPn +| locations on the stack. The correct destination register is in +| cmdreg2b. +| + bfextu CMDREG2B(%a6){#6:#3},%d0 |get dest register no + cmpil #3,%d0 + bgts op2_xi + beqs op2_fp3 + cmpil #1,%d0 + blts op2_fp0 + beqs op2_fp1 +op2_fp2: + fmovemx %fp2-%fp2,USER_FP2(%a6) + bras op2_xi +op2_fp1: + fmovemx %fp1-%fp1,USER_FP1(%a6) + bras op2_xi +op2_fp0: + fmovemx %fp0-%fp0,USER_FP0(%a6) + bras op2_xi +op2_fp3: + fmovemx %fp3-%fp3,USER_FP3(%a6) +| +| The frame returned is idle. We must build a busy frame to hold +| the cu state information and fix up etemp. +| +op2_xi: + movel #22,%d0 |clear 23 lwords + clrl (%a7) +op2_loop: + clrl -(%a7) + dbf %d0,op2_loop + movel #0x40600000,-(%a7) + movel L_SCR1(%a6),STAG(%a6) + movel L_SCR2(%a6),CMDREG1B(%a6) + movel L_SCR3(%a6),DTAG(%a6) + moveb #0x6,CU_SAVEPC(%a6) + movel FP_SCR2(%a6),ETEMP(%a6) + movel FP_SCR2+4(%a6),ETEMP_HI(%a6) + movel FP_SCR2+8(%a6),ETEMP_LO(%a6) + movel %d1,-(%a7) + bra op2_com + +| +| We have the opclass 2 single source situation. +| +op2_com: + moveb #0x15,%d0 + bfins %d0,CMDREG1B(%a6){#0:#6} |opclass 2, double + + cmpw #0x407F,ETEMP_EX(%a6) |single +max + bnes case2 + movew #0x43FF,ETEMP_EX(%a6) |to double +max + bra finish +case2: + cmpw #0xC07F,ETEMP_EX(%a6) |single -max + bnes case3 + movew #0xC3FF,ETEMP_EX(%a6) |to double -max + bra finish +case3: + cmpw #0x3F80,ETEMP_EX(%a6) |single +min + bnes case4 + movew #0x3C00,ETEMP_EX(%a6) |to double +min + bra finish +case4: + cmpw #0xBF80,ETEMP_EX(%a6) |single -min + bne fix_done + movew #0xBC00,ETEMP_EX(%a6) |to double -min + bra finish +| +| The frame returned is busy. It is not possible to reconstruct +| the code sequence to allow completion. fpsp_fmt_error causes +| an fline illegal instruction to be executed. +| +| You should replace the jump to fpsp_fmt_error with a jump +| to the entry point used to kill a process. +| +op2_xb: + jmp fpsp_fmt_error + +| +| Enter here if the case is not of the situations affected by +| bug #1238, or if the fix is completed, and exit. +| +finish: +fix_done: + rts + + |end diff --git a/arch/m68k/fpsp040/decbin.S b/arch/m68k/fpsp040/decbin.S new file mode 100644 index 000000000..16ed796ba --- /dev/null +++ b/arch/m68k/fpsp040/decbin.S @@ -0,0 +1,505 @@ +| +| decbin.sa 3.3 12/19/90 +| +| Description: Converts normalized packed bcd value pointed to by +| register A6 to extended-precision value in FP0. +| +| Input: Normalized packed bcd value in ETEMP(a6). +| +| Output: Exact floating-point representation of the packed bcd value. +| +| Saves and Modifies: D2-D5 +| +| Speed: The program decbin takes ??? cycles to execute. +| +| Object Size: +| +| External Reference(s): None. +| +| Algorithm: +| Expected is a normal bcd (i.e. non-exceptional; all inf, zero, +| and NaN operands are dispatched without entering this routine) +| value in 68881/882 format at location ETEMP(A6). +| +| A1. Convert the bcd exponent to binary by successive adds and muls. +| Set the sign according to SE. Subtract 16 to compensate +| for the mantissa which is to be interpreted as 17 integer +| digits, rather than 1 integer and 16 fraction digits. +| Note: this operation can never overflow. +| +| A2. Convert the bcd mantissa to binary by successive +| adds and muls in FP0. Set the sign according to SM. +| The mantissa digits will be converted with the decimal point +| assumed following the least-significant digit. +| Note: this operation can never overflow. +| +| A3. Count the number of leading/trailing zeros in the +| bcd string. If SE is positive, count the leading zeros; +| if negative, count the trailing zeros. Set the adjusted +| exponent equal to the exponent from A1 and the zero count +| added if SM = 1 and subtracted if SM = 0. Scale the +| mantissa the equivalent of forcing in the bcd value: +| +| SM = 0 a non-zero digit in the integer position +| SM = 1 a non-zero digit in Mant0, lsd of the fraction +| +| this will insure that any value, regardless of its +| representation (ex. 0.1E2, 1E1, 10E0, 100E-1), is converted +| consistently. +| +| A4. Calculate the factor 10^exp in FP1 using a table of +| 10^(2^n) values. To reduce the error in forming factors +| greater than 10^27, a directed rounding scheme is used with +| tables rounded to RN, RM, and RP, according to the table +| in the comments of the pwrten section. +| +| A5. Form the final binary number by scaling the mantissa by +| the exponent factor. This is done by multiplying the +| mantissa in FP0 by the factor in FP1 if the adjusted +| exponent sign is positive, and dividing FP0 by FP1 if +| it is negative. +| +| Clean up and return. Check if the final mul or div resulted +| in an inex2 exception. If so, set inex1 in the fpsr and +| check if the inex1 exception is enabled. If so, set d7 upper +| word to $0100. This will signal unimp.sa that an enabled inex1 +| exception occurred. Unimp will fix the stack. +| + +| Copyright (C) Motorola, Inc. 1990 +| All Rights Reserved +| +| For details on the license for this file, please see the +| file, README, in this same directory. + +|DECBIN idnt 2,1 | Motorola 040 Floating Point Software Package + + |section 8 + +#include "fpsp.h" + +| +| PTENRN, PTENRM, and PTENRP are arrays of powers of 10 rounded +| to nearest, minus, and plus, respectively. The tables include +| 10**{1,2,4,8,16,32,64,128,256,512,1024,2048,4096}. No rounding +| is required until the power is greater than 27, however, all +| tables include the first 5 for ease of indexing. +| + |xref PTENRN + |xref PTENRM + |xref PTENRP + +RTABLE: .byte 0,0,0,0 + .byte 2,3,2,3 + .byte 2,3,3,2 + .byte 3,2,2,3 + + .global decbin + .global calc_e + .global pwrten + .global calc_m + .global norm + .global ap_st_z + .global ap_st_n +| + .set FNIBS,7 + .set FSTRT,0 +| + .set ESTRT,4 + .set EDIGITS,2 | +| +| Constants in single precision +FZERO: .long 0x00000000 +FONE: .long 0x3F800000 +FTEN: .long 0x41200000 + + .set TEN,10 + +| +decbin: + | fmovel #0,FPCR ;clr real fpcr + moveml %d2-%d5,-(%a7) +| +| Calculate exponent: +| 1. Copy bcd value in memory for use as a working copy. +| 2. Calculate absolute value of exponent in d1 by mul and add. +| 3. Correct for exponent sign. +| 4. Subtract 16 to compensate for interpreting the mant as all integer digits. +| (i.e., all digits assumed left of the decimal point.) +| +| Register usage: +| +| calc_e: +| (*) d0: temp digit storage +| (*) d1: accumulator for binary exponent +| (*) d2: digit count +| (*) d3: offset pointer +| ( ) d4: first word of bcd +| ( ) a0: pointer to working bcd value +| ( ) a6: pointer to original bcd value +| (*) FP_SCR1: working copy of original bcd value +| (*) L_SCR1: copy of original exponent word +| +calc_e: + movel #EDIGITS,%d2 |# of nibbles (digits) in fraction part + moveql #ESTRT,%d3 |counter to pick up digits + leal FP_SCR1(%a6),%a0 |load tmp bcd storage address + movel ETEMP(%a6),(%a0) |save input bcd value + movel ETEMP_HI(%a6),4(%a0) |save words 2 and 3 + movel ETEMP_LO(%a6),8(%a0) |and work with these + movel (%a0),%d4 |get first word of bcd + clrl %d1 |zero d1 for accumulator +e_gd: + mulul #TEN,%d1 |mul partial product by one digit place + bfextu %d4{%d3:#4},%d0 |get the digit and zero extend into d0 + addl %d0,%d1 |d1 = d1 + d0 + addqb #4,%d3 |advance d3 to the next digit + dbf %d2,e_gd |if we have used all 3 digits, exit loop + btst #30,%d4 |get SE + beqs e_pos |don't negate if pos + negl %d1 |negate before subtracting +e_pos: + subl #16,%d1 |sub to compensate for shift of mant + bges e_save |if still pos, do not neg + negl %d1 |now negative, make pos and set SE + orl #0x40000000,%d4 |set SE in d4, + orl #0x40000000,(%a0) |and in working bcd +e_save: + movel %d1,L_SCR1(%a6) |save exp in memory +| +| +| Calculate mantissa: +| 1. Calculate absolute value of mantissa in fp0 by mul and add. +| 2. Correct for mantissa sign. +| (i.e., all digits assumed left of the decimal point.) +| +| Register usage: +| +| calc_m: +| (*) d0: temp digit storage +| (*) d1: lword counter +| (*) d2: digit count +| (*) d3: offset pointer +| ( ) d4: words 2 and 3 of bcd +| ( ) a0: pointer to working bcd value +| ( ) a6: pointer to original bcd value +| (*) fp0: mantissa accumulator +| ( ) FP_SCR1: working copy of original bcd value +| ( ) L_SCR1: copy of original exponent word +| +calc_m: + moveql #1,%d1 |word counter, init to 1 + fmoves FZERO,%fp0 |accumulator +| +| +| Since the packed number has a long word between the first & second parts, +| get the integer digit then skip down & get the rest of the +| mantissa. We will unroll the loop once. +| + bfextu (%a0){#28:#4},%d0 |integer part is ls digit in long word + faddb %d0,%fp0 |add digit to sum in fp0 +| +| +| Get the rest of the mantissa. +| +loadlw: + movel (%a0,%d1.L*4),%d4 |load mantissa longword into d4 + moveql #FSTRT,%d3 |counter to pick up digits + moveql #FNIBS,%d2 |reset number of digits per a0 ptr +md2b: + fmuls FTEN,%fp0 |fp0 = fp0 * 10 + bfextu %d4{%d3:#4},%d0 |get the digit and zero extend + faddb %d0,%fp0 |fp0 = fp0 + digit +| +| +| If all the digits (8) in that long word have been converted (d2=0), +| then inc d1 (=2) to point to the next long word and reset d3 to 0 +| to initialize the digit offset, and set d2 to 7 for the digit count; +| else continue with this long word. +| + addqb #4,%d3 |advance d3 to the next digit + dbf %d2,md2b |check for last digit in this lw +nextlw: + addql #1,%d1 |inc lw pointer in mantissa + cmpl #2,%d1 |test for last lw + ble loadlw |if not, get last one + +| +| Check the sign of the mant and make the value in fp0 the same sign. +| +m_sign: + btst #31,(%a0) |test sign of the mantissa + beq ap_st_z |if clear, go to append/strip zeros + fnegx %fp0 |if set, negate fp0 + +| +| Append/strip zeros: +| +| For adjusted exponents which have an absolute value greater than 27*, +| this routine calculates the amount needed to normalize the mantissa +| for the adjusted exponent. That number is subtracted from the exp +| if the exp was positive, and added if it was negative. The purpose +| of this is to reduce the value of the exponent and the possibility +| of error in calculation of pwrten. +| +| 1. Branch on the sign of the adjusted exponent. +| 2p.(positive exp) +| 2. Check M16 and the digits in lwords 2 and 3 in descending order. +| 3. Add one for each zero encountered until a non-zero digit. +| 4. Subtract the count from the exp. +| 5. Check if the exp has crossed zero in #3 above; make the exp abs +| and set SE. +| 6. Multiply the mantissa by 10**count. +| 2n.(negative exp) +| 2. Check the digits in lwords 3 and 2 in descending order. +| 3. Add one for each zero encountered until a non-zero digit. +| 4. Add the count to the exp. +| 5. Check if the exp has crossed zero in #3 above; clear SE. +| 6. Divide the mantissa by 10**count. +| +| *Why 27? If the adjusted exponent is within -28 < expA < 28, than +| any adjustment due to append/strip zeros will drive the resultant +| exponent towards zero. Since all pwrten constants with a power +| of 27 or less are exact, there is no need to use this routine to +| attempt to lessen the resultant exponent. +| +| Register usage: +| +| ap_st_z: +| (*) d0: temp digit storage +| (*) d1: zero count +| (*) d2: digit count +| (*) d3: offset pointer +| ( ) d4: first word of bcd +| (*) d5: lword counter +| ( ) a0: pointer to working bcd value +| ( ) FP_SCR1: working copy of original bcd value +| ( ) L_SCR1: copy of original exponent word +| +| +| First check the absolute value of the exponent to see if this +| routine is necessary. If so, then check the sign of the exponent +| and do append (+) or strip (-) zeros accordingly. +| This section handles a positive adjusted exponent. +| +ap_st_z: + movel L_SCR1(%a6),%d1 |load expA for range test + cmpl #27,%d1 |test is with 27 + ble pwrten |if abs(expA) <28, skip ap/st zeros + btst #30,(%a0) |check sign of exp + bne ap_st_n |if neg, go to neg side + clrl %d1 |zero count reg + movel (%a0),%d4 |load lword 1 to d4 + bfextu %d4{#28:#4},%d0 |get M16 in d0 + bnes ap_p_fx |if M16 is non-zero, go fix exp + addql #1,%d1 |inc zero count + moveql #1,%d5 |init lword counter + movel (%a0,%d5.L*4),%d4 |get lword 2 to d4 + bnes ap_p_cl |if lw 2 is zero, skip it + addql #8,%d1 |and inc count by 8 + addql #1,%d5 |inc lword counter + movel (%a0,%d5.L*4),%d4 |get lword 3 to d4 +ap_p_cl: + clrl %d3 |init offset reg + moveql #7,%d2 |init digit counter +ap_p_gd: + bfextu %d4{%d3:#4},%d0 |get digit + bnes ap_p_fx |if non-zero, go to fix exp + addql #4,%d3 |point to next digit + addql #1,%d1 |inc digit counter + dbf %d2,ap_p_gd |get next digit +ap_p_fx: + movel %d1,%d0 |copy counter to d2 + movel L_SCR1(%a6),%d1 |get adjusted exp from memory + subl %d0,%d1 |subtract count from exp + bges ap_p_fm |if still pos, go to pwrten + negl %d1 |now its neg; get abs + movel (%a0),%d4 |load lword 1 to d4 + orl #0x40000000,%d4 | and set SE in d4 + orl #0x40000000,(%a0) | and in memory +| +| Calculate the mantissa multiplier to compensate for the striping of +| zeros from the mantissa. +| +ap_p_fm: + movel #PTENRN,%a1 |get address of power-of-ten table + clrl %d3 |init table index + fmoves FONE,%fp1 |init fp1 to 1 + moveql #3,%d2 |init d2 to count bits in counter +ap_p_el: + asrl #1,%d0 |shift lsb into carry + bccs ap_p_en |if 1, mul fp1 by pwrten factor + fmulx (%a1,%d3),%fp1 |mul by 10**(d3_bit_no) +ap_p_en: + addl #12,%d3 |inc d3 to next rtable entry + tstl %d0 |check if d0 is zero + bnes ap_p_el |if not, get next bit + fmulx %fp1,%fp0 |mul mantissa by 10**(no_bits_shifted) + bra pwrten |go calc pwrten +| +| This section handles a negative adjusted exponent. +| +ap_st_n: + clrl %d1 |clr counter + moveql #2,%d5 |set up d5 to point to lword 3 + movel (%a0,%d5.L*4),%d4 |get lword 3 + bnes ap_n_cl |if not zero, check digits + subl #1,%d5 |dec d5 to point to lword 2 + addql #8,%d1 |inc counter by 8 + movel (%a0,%d5.L*4),%d4 |get lword 2 +ap_n_cl: + movel #28,%d3 |point to last digit + moveql #7,%d2 |init digit counter +ap_n_gd: + bfextu %d4{%d3:#4},%d0 |get digit + bnes ap_n_fx |if non-zero, go to exp fix + subql #4,%d3 |point to previous digit + addql #1,%d1 |inc digit counter + dbf %d2,ap_n_gd |get next digit +ap_n_fx: + movel %d1,%d0 |copy counter to d0 + movel L_SCR1(%a6),%d1 |get adjusted exp from memory + subl %d0,%d1 |subtract count from exp + bgts ap_n_fm |if still pos, go fix mantissa + negl %d1 |take abs of exp and clr SE + movel (%a0),%d4 |load lword 1 to d4 + andl #0xbfffffff,%d4 | and clr SE in d4 + andl #0xbfffffff,(%a0) | and in memory +| +| Calculate the mantissa multiplier to compensate for the appending of +| zeros to the mantissa. +| +ap_n_fm: + movel #PTENRN,%a1 |get address of power-of-ten table + clrl %d3 |init table index + fmoves FONE,%fp1 |init fp1 to 1 + moveql #3,%d2 |init d2 to count bits in counter +ap_n_el: + asrl #1,%d0 |shift lsb into carry + bccs ap_n_en |if 1, mul fp1 by pwrten factor + fmulx (%a1,%d3),%fp1 |mul by 10**(d3_bit_no) +ap_n_en: + addl #12,%d3 |inc d3 to next rtable entry + tstl %d0 |check if d0 is zero + bnes ap_n_el |if not, get next bit + fdivx %fp1,%fp0 |div mantissa by 10**(no_bits_shifted) +| +| +| Calculate power-of-ten factor from adjusted and shifted exponent. +| +| Register usage: +| +| pwrten: +| (*) d0: temp +| ( ) d1: exponent +| (*) d2: {FPCR[6:5],SM,SE} as index in RTABLE; temp +| (*) d3: FPCR work copy +| ( ) d4: first word of bcd +| (*) a1: RTABLE pointer +| calc_p: +| (*) d0: temp +| ( ) d1: exponent +| (*) d3: PWRTxx table index +| ( ) a0: pointer to working copy of bcd +| (*) a1: PWRTxx pointer +| (*) fp1: power-of-ten accumulator +| +| Pwrten calculates the exponent factor in the selected rounding mode +| according to the following table: +| +| Sign of Mant Sign of Exp Rounding Mode PWRTEN Rounding Mode +| +| ANY ANY RN RN +| +| + + RP RP +| - + RP RM +| + - RP RM +| - - RP RP +| +| + + RM RM +| - + RM RP +| + - RM RP +| - - RM RM +| +| + + RZ RM +| - + RZ RM +| + - RZ RP +| - - RZ RP +| +| +pwrten: + movel USER_FPCR(%a6),%d3 |get user's FPCR + bfextu %d3{#26:#2},%d2 |isolate rounding mode bits + movel (%a0),%d4 |reload 1st bcd word to d4 + asll #2,%d2 |format d2 to be + bfextu %d4{#0:#2},%d0 | {FPCR[6],FPCR[5],SM,SE} + addl %d0,%d2 |in d2 as index into RTABLE + leal RTABLE,%a1 |load rtable base + moveb (%a1,%d2),%d0 |load new rounding bits from table + clrl %d3 |clear d3 to force no exc and extended + bfins %d0,%d3{#26:#2} |stuff new rounding bits in FPCR + fmovel %d3,%FPCR |write new FPCR + asrl #1,%d0 |write correct PTENxx table + bccs not_rp |to a1 + leal PTENRP,%a1 |it is RP + bras calc_p |go to init section +not_rp: + asrl #1,%d0 |keep checking + bccs not_rm + leal PTENRM,%a1 |it is RM + bras calc_p |go to init section +not_rm: + leal PTENRN,%a1 |it is RN +calc_p: + movel %d1,%d0 |copy exp to d0;use d0 + bpls no_neg |if exp is negative, + negl %d0 |invert it + orl #0x40000000,(%a0) |and set SE bit +no_neg: + clrl %d3 |table index + fmoves FONE,%fp1 |init fp1 to 1 +e_loop: + asrl #1,%d0 |shift next bit into carry + bccs e_next |if zero, skip the mul + fmulx (%a1,%d3),%fp1 |mul by 10**(d3_bit_no) +e_next: + addl #12,%d3 |inc d3 to next rtable entry + tstl %d0 |check if d0 is zero + bnes e_loop |not zero, continue shifting +| +| +| Check the sign of the adjusted exp and make the value in fp0 the +| same sign. If the exp was pos then multiply fp1*fp0; +| else divide fp0/fp1. +| +| Register Usage: +| norm: +| ( ) a0: pointer to working bcd value +| (*) fp0: mantissa accumulator +| ( ) fp1: scaling factor - 10**(abs(exp)) +| +norm: + btst #30,(%a0) |test the sign of the exponent + beqs mul |if clear, go to multiply +div: + fdivx %fp1,%fp0 |exp is negative, so divide mant by exp + bras end_dec +mul: + fmulx %fp1,%fp0 |exp is positive, so multiply by exp +| +| +| Clean up and return with result in fp0. +| +| If the final mul/div in decbin incurred an inex exception, +| it will be inex2, but will be reported as inex1 by get_op. +| +end_dec: + fmovel %FPSR,%d0 |get status register + bclrl #inex2_bit+8,%d0 |test for inex2 and clear it + fmovel %d0,%FPSR |return status reg w/o inex2 + beqs no_exc |skip this if no exc + orl #inx1a_mask,USER_FPSR(%a6) |set inex1/ainex +no_exc: + moveml (%a7)+,%d2-%d5 + rts + |end diff --git a/arch/m68k/fpsp040/do_func.S b/arch/m68k/fpsp040/do_func.S new file mode 100644 index 000000000..3eff99a80 --- /dev/null +++ b/arch/m68k/fpsp040/do_func.S @@ -0,0 +1,558 @@ +| +| do_func.sa 3.4 2/18/91 +| +| Do_func performs the unimplemented operation. The operation +| to be performed is determined from the lower 7 bits of the +| extension word (except in the case of fmovecr and fsincos). +| The opcode and tag bits form an index into a jump table in +| tbldo.sa. Cases of zero, infinity and NaN are handled in +| do_func by forcing the default result. Normalized and +| denormalized (there are no unnormalized numbers at this +| point) are passed onto the emulation code. +| +| CMDREG1B and STAG are extracted from the fsave frame +| and combined to form the table index. The function called +| will start with a0 pointing to the ETEMP operand. Dyadic +| functions can find FPTEMP at -12(a0). +| +| Called functions return their result in fp0. Sincos returns +| sin(x) in fp0 and cos(x) in fp1. +| + +| Copyright (C) Motorola, Inc. 1990 +| All Rights Reserved +| +| For details on the license for this file, please see the +| file, README, in this same directory. + +DO_FUNC: |idnt 2,1 | Motorola 040 Floating Point Software Package + + |section 8 + +#include "fpsp.h" + + |xref t_dz2 + |xref t_operr + |xref t_inx2 + |xref t_resdnrm + |xref dst_nan + |xref src_nan + |xref nrm_set + |xref sto_cos + + |xref tblpre + |xref slognp1,slogn,slog10,slog2 + |xref slognd,slog10d,slog2d + |xref smod,srem + |xref sscale + |xref smovcr + +PONE: .long 0x3fff0000,0x80000000,0x00000000 |+1 +MONE: .long 0xbfff0000,0x80000000,0x00000000 |-1 +PZERO: .long 0x00000000,0x00000000,0x00000000 |+0 +MZERO: .long 0x80000000,0x00000000,0x00000000 |-0 +PINF: .long 0x7fff0000,0x00000000,0x00000000 |+inf +MINF: .long 0xffff0000,0x00000000,0x00000000 |-inf +QNAN: .long 0x7fff0000,0xffffffff,0xffffffff |non-signaling nan +PPIBY2: .long 0x3FFF0000,0xC90FDAA2,0x2168C235 |+PI/2 +MPIBY2: .long 0xbFFF0000,0xC90FDAA2,0x2168C235 |-PI/2 + + .global do_func +do_func: + clrb CU_ONLY(%a6) +| +| Check for fmovecr. It does not follow the format of fp gen +| unimplemented instructions. The test is on the upper 6 bits; +| if they are $17, the inst is fmovecr. Call entry smovcr +| directly. +| + bfextu CMDREG1B(%a6){#0:#6},%d0 |get opclass and src fields + cmpil #0x17,%d0 |if op class and size fields are $17, +| ;it is FMOVECR; if not, continue + bnes not_fmovecr + jmp smovcr |fmovecr; jmp directly to emulation + +not_fmovecr: + movew CMDREG1B(%a6),%d0 + andl #0x7F,%d0 + cmpil #0x38,%d0 |if the extension is >= $38, + bge serror |it is illegal + bfextu STAG(%a6){#0:#3},%d1 + lsll #3,%d0 |make room for STAG + addl %d1,%d0 |combine for final index into table + leal tblpre,%a1 |start of monster jump table + movel (%a1,%d0.w*4),%a1 |real target address + leal ETEMP(%a6),%a0 |a0 is pointer to src op + movel USER_FPCR(%a6),%d1 + andl #0xFF,%d1 | discard all but rounding mode/prec + fmovel #0,%fpcr + jmp (%a1) +| +| ERROR +| + .global serror +serror: + st STORE_FLG(%a6) + rts +| +| These routines load forced values into fp0. They are called +| by index into tbldo. +| +| Load a signed zero to fp0 and set inex2/ainex +| + .global snzrinx +snzrinx: + btstb #sign_bit,LOCAL_EX(%a0) |get sign of source operand + bnes ld_mzinx |if negative, branch + bsr ld_pzero |bsr so we can return and set inx + bra t_inx2 |now, set the inx for the next inst +ld_mzinx: + bsr ld_mzero |if neg, load neg zero, return here + bra t_inx2 |now, set the inx for the next inst +| +| Load a signed zero to fp0; do not set inex2/ainex +| + .global szero +szero: + btstb #sign_bit,LOCAL_EX(%a0) |get sign of source operand + bne ld_mzero |if neg, load neg zero + bra ld_pzero |load positive zero +| +| Load a signed infinity to fp0; do not set inex2/ainex +| + .global sinf +sinf: + btstb #sign_bit,LOCAL_EX(%a0) |get sign of source operand + bne ld_minf |if negative branch + bra ld_pinf +| +| Load a signed one to fp0; do not set inex2/ainex +| + .global sone +sone: + btstb #sign_bit,LOCAL_EX(%a0) |check sign of source + bne ld_mone + bra ld_pone +| +| Load a signed pi/2 to fp0; do not set inex2/ainex +| + .global spi_2 +spi_2: + btstb #sign_bit,LOCAL_EX(%a0) |check sign of source + bne ld_mpi2 + bra ld_ppi2 +| +| Load either a +0 or +inf for plus/minus operand +| + .global szr_inf +szr_inf: + btstb #sign_bit,LOCAL_EX(%a0) |check sign of source + bne ld_pzero + bra ld_pinf +| +| Result is either an operr or +inf for plus/minus operand +| [Used by slogn, slognp1, slog10, and slog2] +| + .global sopr_inf +sopr_inf: + btstb #sign_bit,LOCAL_EX(%a0) |check sign of source + bne t_operr + bra ld_pinf +| +| FLOGNP1 +| + .global sslognp1 +sslognp1: + fmovemx (%a0),%fp0-%fp0 + fcmpb #-1,%fp0 + fbgt slognp1 + fbeq t_dz2 |if = -1, divide by zero exception + fmovel #0,%FPSR |clr N flag + bra t_operr |take care of operands < -1 +| +| FETOXM1 +| + .global setoxm1i +setoxm1i: + btstb #sign_bit,LOCAL_EX(%a0) |check sign of source + bne ld_mone + bra ld_pinf +| +| FLOGN +| +| Test for 1.0 as an input argument, returning +zero. Also check +| the sign and return operr if negative. +| + .global sslogn +sslogn: + btstb #sign_bit,LOCAL_EX(%a0) + bne t_operr |take care of operands < 0 + cmpiw #0x3fff,LOCAL_EX(%a0) |test for 1.0 input + bne slogn + cmpil #0x80000000,LOCAL_HI(%a0) + bne slogn + tstl LOCAL_LO(%a0) + bne slogn + fmovex PZERO,%fp0 + rts + + .global sslognd +sslognd: + btstb #sign_bit,LOCAL_EX(%a0) + beq slognd + bra t_operr |take care of operands < 0 + +| +| FLOG10 +| + .global sslog10 +sslog10: + btstb #sign_bit,LOCAL_EX(%a0) + bne t_operr |take care of operands < 0 + cmpiw #0x3fff,LOCAL_EX(%a0) |test for 1.0 input + bne slog10 + cmpil #0x80000000,LOCAL_HI(%a0) + bne slog10 + tstl LOCAL_LO(%a0) + bne slog10 + fmovex PZERO,%fp0 + rts + + .global sslog10d +sslog10d: + btstb #sign_bit,LOCAL_EX(%a0) + beq slog10d + bra t_operr |take care of operands < 0 + +| +| FLOG2 +| + .global sslog2 +sslog2: + btstb #sign_bit,LOCAL_EX(%a0) + bne t_operr |take care of operands < 0 + cmpiw #0x3fff,LOCAL_EX(%a0) |test for 1.0 input + bne slog2 + cmpil #0x80000000,LOCAL_HI(%a0) + bne slog2 + tstl LOCAL_LO(%a0) + bne slog2 + fmovex PZERO,%fp0 + rts + + .global sslog2d +sslog2d: + btstb #sign_bit,LOCAL_EX(%a0) + beq slog2d + bra t_operr |take care of operands < 0 + +| +| FMOD +| +pmodt: +| ;$21 fmod +| ;dtag,stag + .long smod | 00,00 norm,norm = normal + .long smod_oper | 00,01 norm,zero = nan with operr + .long smod_fpn | 00,10 norm,inf = fpn + .long smod_snan | 00,11 norm,nan = nan + .long smod_zro | 01,00 zero,norm = +-zero + .long smod_oper | 01,01 zero,zero = nan with operr + .long smod_zro | 01,10 zero,inf = +-zero + .long smod_snan | 01,11 zero,nan = nan + .long smod_oper | 10,00 inf,norm = nan with operr + .long smod_oper | 10,01 inf,zero = nan with operr + .long smod_oper | 10,10 inf,inf = nan with operr + .long smod_snan | 10,11 inf,nan = nan + .long smod_dnan | 11,00 nan,norm = nan + .long smod_dnan | 11,01 nan,zero = nan + .long smod_dnan | 11,10 nan,inf = nan + .long smod_dnan | 11,11 nan,nan = nan + + .global pmod +pmod: + clrb FPSR_QBYTE(%a6) | clear quotient field + bfextu STAG(%a6){#0:#3},%d0 |stag = d0 + bfextu DTAG(%a6){#0:#3},%d1 |dtag = d1 + +| +| Alias extended denorms to norms for the jump table. +| + bclrl #2,%d0 + bclrl #2,%d1 + + lslb #2,%d1 + orb %d0,%d1 |d1{3:2} = dtag, d1{1:0} = stag +| ;Tag values: +| ;00 = norm or denorm +| ;01 = zero +| ;10 = inf +| ;11 = nan + lea pmodt,%a1 + movel (%a1,%d1.w*4),%a1 + jmp (%a1) + +smod_snan: + bra src_nan +smod_dnan: + bra dst_nan +smod_oper: + bra t_operr +smod_zro: + moveb ETEMP(%a6),%d1 |get sign of src op + moveb FPTEMP(%a6),%d0 |get sign of dst op + eorb %d0,%d1 |get exor of sign bits + btstl #7,%d1 |test for sign + beqs smod_zsn |if clr, do not set sign big + bsetb #q_sn_bit,FPSR_QBYTE(%a6) |set q-byte sign bit +smod_zsn: + btstl #7,%d0 |test if + or - + beq ld_pzero |if pos then load +0 + bra ld_mzero |else neg load -0 + +smod_fpn: + moveb ETEMP(%a6),%d1 |get sign of src op + moveb FPTEMP(%a6),%d0 |get sign of dst op + eorb %d0,%d1 |get exor of sign bits + btstl #7,%d1 |test for sign + beqs smod_fsn |if clr, do not set sign big + bsetb #q_sn_bit,FPSR_QBYTE(%a6) |set q-byte sign bit +smod_fsn: + tstb DTAG(%a6) |filter out denormal destination case + bpls smod_nrm | + leal FPTEMP(%a6),%a0 |a0<- addr(FPTEMP) + bra t_resdnrm |force UNFL(but exact) result +smod_nrm: + fmovel USER_FPCR(%a6),%fpcr |use user's rmode and precision + fmovex FPTEMP(%a6),%fp0 |return dest to fp0 + rts + +| +| FREM +| +premt: +| ;$25 frem +| ;dtag,stag + .long srem | 00,00 norm,norm = normal + .long srem_oper | 00,01 norm,zero = nan with operr + .long srem_fpn | 00,10 norm,inf = fpn + .long srem_snan | 00,11 norm,nan = nan + .long srem_zro | 01,00 zero,norm = +-zero + .long srem_oper | 01,01 zero,zero = nan with operr + .long srem_zro | 01,10 zero,inf = +-zero + .long srem_snan | 01,11 zero,nan = nan + .long srem_oper | 10,00 inf,norm = nan with operr + .long srem_oper | 10,01 inf,zero = nan with operr + .long srem_oper | 10,10 inf,inf = nan with operr + .long srem_snan | 10,11 inf,nan = nan + .long srem_dnan | 11,00 nan,norm = nan + .long srem_dnan | 11,01 nan,zero = nan + .long srem_dnan | 11,10 nan,inf = nan + .long srem_dnan | 11,11 nan,nan = nan + + .global prem +prem: + clrb FPSR_QBYTE(%a6) |clear quotient field + bfextu STAG(%a6){#0:#3},%d0 |stag = d0 + bfextu DTAG(%a6){#0:#3},%d1 |dtag = d1 +| +| Alias extended denorms to norms for the jump table. +| + bclr #2,%d0 + bclr #2,%d1 + + lslb #2,%d1 + orb %d0,%d1 |d1{3:2} = dtag, d1{1:0} = stag +| ;Tag values: +| ;00 = norm or denorm +| ;01 = zero +| ;10 = inf +| ;11 = nan + lea premt,%a1 + movel (%a1,%d1.w*4),%a1 + jmp (%a1) + +srem_snan: + bra src_nan +srem_dnan: + bra dst_nan +srem_oper: + bra t_operr +srem_zro: + moveb ETEMP(%a6),%d1 |get sign of src op + moveb FPTEMP(%a6),%d0 |get sign of dst op + eorb %d0,%d1 |get exor of sign bits + btstl #7,%d1 |test for sign + beqs srem_zsn |if clr, do not set sign big + bsetb #q_sn_bit,FPSR_QBYTE(%a6) |set q-byte sign bit +srem_zsn: + btstl #7,%d0 |test if + or - + beq ld_pzero |if pos then load +0 + bra ld_mzero |else neg load -0 + +srem_fpn: + moveb ETEMP(%a6),%d1 |get sign of src op + moveb FPTEMP(%a6),%d0 |get sign of dst op + eorb %d0,%d1 |get exor of sign bits + btstl #7,%d1 |test for sign + beqs srem_fsn |if clr, do not set sign big + bsetb #q_sn_bit,FPSR_QBYTE(%a6) |set q-byte sign bit +srem_fsn: + tstb DTAG(%a6) |filter out denormal destination case + bpls srem_nrm | + leal FPTEMP(%a6),%a0 |a0<- addr(FPTEMP) + bra t_resdnrm |force UNFL(but exact) result +srem_nrm: + fmovel USER_FPCR(%a6),%fpcr |use user's rmode and precision + fmovex FPTEMP(%a6),%fp0 |return dest to fp0 + rts +| +| FSCALE +| +pscalet: +| ;$26 fscale +| ;dtag,stag + .long sscale | 00,00 norm,norm = result + .long sscale | 00,01 norm,zero = fpn + .long scl_opr | 00,10 norm,inf = nan with operr + .long scl_snan | 00,11 norm,nan = nan + .long scl_zro | 01,00 zero,norm = +-zero + .long scl_zro | 01,01 zero,zero = +-zero + .long scl_opr | 01,10 zero,inf = nan with operr + .long scl_snan | 01,11 zero,nan = nan + .long scl_inf | 10,00 inf,norm = +-inf + .long scl_inf | 10,01 inf,zero = +-inf + .long scl_opr | 10,10 inf,inf = nan with operr + .long scl_snan | 10,11 inf,nan = nan + .long scl_dnan | 11,00 nan,norm = nan + .long scl_dnan | 11,01 nan,zero = nan + .long scl_dnan | 11,10 nan,inf = nan + .long scl_dnan | 11,11 nan,nan = nan + + .global pscale +pscale: + bfextu STAG(%a6){#0:#3},%d0 |stag in d0 + bfextu DTAG(%a6){#0:#3},%d1 |dtag in d1 + bclrl #2,%d0 |alias denorm into norm + bclrl #2,%d1 |alias denorm into norm + lslb #2,%d1 + orb %d0,%d1 |d1{4:2} = dtag, d1{1:0} = stag +| ;dtag values stag values: +| ;000 = norm 00 = norm +| ;001 = zero 01 = zero +| ;010 = inf 10 = inf +| ;011 = nan 11 = nan +| ;100 = dnrm +| +| + leal pscalet,%a1 |load start of jump table + movel (%a1,%d1.w*4),%a1 |load a1 with label depending on tag + jmp (%a1) |go to the routine + +scl_opr: + bra t_operr + +scl_dnan: + bra dst_nan + +scl_zro: + btstb #sign_bit,FPTEMP_EX(%a6) |test if + or - + beq ld_pzero |if pos then load +0 + bra ld_mzero |if neg then load -0 +scl_inf: + btstb #sign_bit,FPTEMP_EX(%a6) |test if + or - + beq ld_pinf |if pos then load +inf + bra ld_minf |else neg load -inf +scl_snan: + bra src_nan +| +| FSINCOS +| + .global ssincosz +ssincosz: + btstb #sign_bit,ETEMP(%a6) |get sign + beqs sincosp + fmovex MZERO,%fp0 + bras sincoscom +sincosp: + fmovex PZERO,%fp0 +sincoscom: + fmovemx PONE,%fp1-%fp1 |do not allow FPSR to be affected + bra sto_cos |store cosine result + + .global ssincosi +ssincosi: + fmovex QNAN,%fp1 |load NAN + bsr sto_cos |store cosine result + fmovex QNAN,%fp0 |load NAN + bra t_operr + + .global ssincosnan +ssincosnan: + movel ETEMP_EX(%a6),FP_SCR1(%a6) + movel ETEMP_HI(%a6),FP_SCR1+4(%a6) + movel ETEMP_LO(%a6),FP_SCR1+8(%a6) + bsetb #signan_bit,FP_SCR1+4(%a6) + fmovemx FP_SCR1(%a6),%fp1-%fp1 + bsr sto_cos + bra src_nan +| +| This code forces default values for the zero, inf, and nan cases +| in the transcendentals code. The CC bits must be set in the +| stacked FPSR to be correctly reported. +| +|**Returns +PI/2 + .global ld_ppi2 +ld_ppi2: + fmovex PPIBY2,%fp0 |load +pi/2 + bra t_inx2 |set inex2 exc + +|**Returns -PI/2 + .global ld_mpi2 +ld_mpi2: + fmovex MPIBY2,%fp0 |load -pi/2 + orl #neg_mask,USER_FPSR(%a6) |set N bit + bra t_inx2 |set inex2 exc + +|**Returns +inf + .global ld_pinf +ld_pinf: + fmovex PINF,%fp0 |load +inf + orl #inf_mask,USER_FPSR(%a6) |set I bit + rts + +|**Returns -inf + .global ld_minf +ld_minf: + fmovex MINF,%fp0 |load -inf + orl #neg_mask+inf_mask,USER_FPSR(%a6) |set N and I bits + rts + +|**Returns +1 + .global ld_pone +ld_pone: + fmovex PONE,%fp0 |load +1 + rts + +|**Returns -1 + .global ld_mone +ld_mone: + fmovex MONE,%fp0 |load -1 + orl #neg_mask,USER_FPSR(%a6) |set N bit + rts + +|**Returns +0 + .global ld_pzero +ld_pzero: + fmovex PZERO,%fp0 |load +0 + orl #z_mask,USER_FPSR(%a6) |set Z bit + rts + +|**Returns -0 + .global ld_mzero +ld_mzero: + fmovex MZERO,%fp0 |load -0 + orl #neg_mask+z_mask,USER_FPSR(%a6) |set N and Z bits + rts + + |end diff --git a/arch/m68k/fpsp040/fpsp.h b/arch/m68k/fpsp040/fpsp.h new file mode 100644 index 000000000..5df4cd772 --- /dev/null +++ b/arch/m68k/fpsp040/fpsp.h @@ -0,0 +1,347 @@ +| +| fpsp.h 3.3 3.3 +| + +| Copyright (C) Motorola, Inc. 1990 +| All Rights Reserved +| +| For details on the license for this file, please see the +| file, README, in this same directory. + +| fpsp.h --- stack frame offsets during FPSP exception handling +| +| These equates are used to access the exception frame, the fsave +| frame and any local variables needed by the FPSP package. +| +| All FPSP handlers begin by executing: +| +| link a6,#-LOCAL_SIZE +| fsave -(a7) +| movem.l d0-d1/a0-a1,USER_DA(a6) +| fmovem.x fp0-fp3,USER_FP0(a6) +| fmove.l fpsr/fpcr/fpiar,USER_FPSR(a6) +| +| After initialization, the stack looks like this: +| +| A7 ---> +-------------------------------+ +| | | +| | FPU fsave area | +| | | +| +-------------------------------+ +| | | +| | FPSP Local Variables | +| | including | +| | saved registers | +| | | +| +-------------------------------+ +| A6 ---> | Saved A6 | +| +-------------------------------+ +| | | +| | Exception Frame | +| | | +| | | +| +| Positive offsets from A6 refer to the exception frame. Negative +| offsets refer to the Local Variable area and the fsave area. +| The fsave frame is also accessible from the top via A7. +| +| On exit, the handlers execute: +| +| movem.l USER_DA(a6),d0-d1/a0-a1 +| fmovem.x USER_FP0(a6),fp0-fp3 +| fmove.l USER_FPSR(a6),fpsr/fpcr/fpiar +| frestore (a7)+ +| unlk a6 +| +| and then either "bra fpsp_done" if the exception was completely +| handled by the package, or "bra real_xxxx" which is an external +| label to a routine that will process a real exception of the +| type that was generated. Some handlers may omit the "frestore" +| if the FPU state after the exception is idle. +| +| Sometimes the exception handler will transform the fsave area +| because it needs to report an exception back to the user. This +| can happen if the package is entered for an unimplemented float +| instruction that generates (say) an underflow. Alternatively, +| a second fsave frame can be pushed onto the stack and the +| handler exit code will reload the new frame and discard the old. +| +| The registers d0, d1, a0, a1 and fp0-fp3 are always saved and +| restored from the "local variable" area and can be used as +| temporaries. If a routine needs to change any +| of these registers, it should modify the saved copy and let +| the handler exit code restore the value. +| +|---------------------------------------------------------------------- +| +| Local Variables on the stack +| + .set LOCAL_SIZE,192 | bytes needed for local variables + .set LV,-LOCAL_SIZE | convenient base value +| + .set USER_DA,LV+0 | save space for D0-D1,A0-A1 + .set USER_D0,LV+0 | saved user D0 + .set USER_D1,LV+4 | saved user D1 + .set USER_A0,LV+8 | saved user A0 + .set USER_A1,LV+12 | saved user A1 + .set USER_FP0,LV+16 | saved user FP0 + .set USER_FP1,LV+28 | saved user FP1 + .set USER_FP2,LV+40 | saved user FP2 + .set USER_FP3,LV+52 | saved user FP3 + .set USER_FPCR,LV+64 | saved user FPCR + .set FPCR_ENABLE,USER_FPCR+2 | FPCR exception enable + .set FPCR_MODE,USER_FPCR+3 | FPCR rounding mode control + .set USER_FPSR,LV+68 | saved user FPSR + .set FPSR_CC,USER_FPSR+0 | FPSR condition code + .set FPSR_QBYTE,USER_FPSR+1 | FPSR quotient + .set FPSR_EXCEPT,USER_FPSR+2 | FPSR exception + .set FPSR_AEXCEPT,USER_FPSR+3 | FPSR accrued exception + .set USER_FPIAR,LV+72 | saved user FPIAR + .set FP_SCR1,LV+76 | room for a temporary float value + .set FP_SCR2,LV+92 | room for a temporary float value + .set L_SCR1,LV+108 | room for a temporary long value + .set L_SCR2,LV+112 | room for a temporary long value + .set STORE_FLG,LV+116 + .set BINDEC_FLG,LV+117 | used in bindec + .set DNRM_FLG,LV+118 | used in res_func + .set RES_FLG,LV+119 | used in res_func + .set DY_MO_FLG,LV+120 | dyadic/monadic flag + .set UFLG_TMP,LV+121 | temporary for uflag errata + .set CU_ONLY,LV+122 | cu-only flag + .set VER_TMP,LV+123 | temp holding for version number + .set L_SCR3,LV+124 | room for a temporary long value + .set FP_SCR3,LV+128 | room for a temporary float value + .set FP_SCR4,LV+144 | room for a temporary float value + .set FP_SCR5,LV+160 | room for a temporary float value + .set FP_SCR6,LV+176 +| +|NEXT equ LV+192 ;need to increase LOCAL_SIZE +| +|-------------------------------------------------------------------------- +| +| fsave offsets and bit definitions +| +| Offsets are defined from the end of an fsave because the last 10 +| words of a busy frame are the same as the unimplemented frame. +| + .set CU_SAVEPC,LV-92 | micro-pc for CU (1 byte) + .set FPR_DIRTY_BITS,LV-91 | fpr dirty bits +| + .set WBTEMP,LV-76 | write back temp (12 bytes) + .set WBTEMP_EX,WBTEMP | wbtemp sign and exponent (2 bytes) + .set WBTEMP_HI,WBTEMP+4 | wbtemp mantissa [63:32] (4 bytes) + .set WBTEMP_LO,WBTEMP+8 | wbtemp mantissa [31:00] (4 bytes) +| + .set WBTEMP_SGN,WBTEMP+2 | used to store sign +| + .set FPSR_SHADOW,LV-64 | fpsr shadow reg +| + .set FPIARCU,LV-60 | Instr. addr. reg. for CU (4 bytes) +| + .set CMDREG2B,LV-52 | cmd reg for machine 2 + .set CMDREG3B,LV-48 | cmd reg for E3 exceptions (2 bytes) +| + .set NMNEXC,LV-44 | NMNEXC (unsup,snan bits only) + .set nmn_unsup_bit,1 | + .set nmn_snan_bit,0 | +| + .set NMCEXC,LV-43 | NMNEXC & NMCEXC + .set nmn_operr_bit,7 + .set nmn_ovfl_bit,6 + .set nmn_unfl_bit,5 + .set nmc_unsup_bit,4 + .set nmc_snan_bit,3 + .set nmc_operr_bit,2 + .set nmc_ovfl_bit,1 + .set nmc_unfl_bit,0 +| + .set STAG,LV-40 | source tag (1 byte) + .set WBTEMP_GRS,LV-40 | alias wbtemp guard, round, sticky + .set guard_bit,1 | guard bit is bit number 1 + .set round_bit,0 | round bit is bit number 0 + .set stag_mask,0xE0 | upper 3 bits are source tag type + .set denorm_bit,7 | bit determines if denorm or unnorm + .set etemp15_bit,4 | etemp exponent bit #15 + .set wbtemp66_bit,2 | wbtemp mantissa bit #66 + .set wbtemp1_bit,1 | wbtemp mantissa bit #1 + .set wbtemp0_bit,0 | wbtemp mantissa bit #0 +| + .set STICKY,LV-39 | holds sticky bit + .set sticky_bit,7 +| + .set CMDREG1B,LV-36 | cmd reg for E1 exceptions (2 bytes) + .set kfact_bit,12 | distinguishes static/dynamic k-factor +| ;on packed move outs. NOTE: this +| ;equate only works when CMDREG1B is in +| ;a register. +| + .set CMDWORD,LV-35 | command word in cmd1b + .set direction_bit,5 | bit 0 in opclass + .set size_bit2,12 | bit 2 in size field +| + .set DTAG,LV-32 | dest tag (1 byte) + .set dtag_mask,0xE0 | upper 3 bits are dest type tag + .set fptemp15_bit,4 | fptemp exponent bit #15 +| + .set WB_BYTE,LV-31 | holds WBTE15 bit (1 byte) + .set wbtemp15_bit,4 | wbtemp exponent bit #15 +| + .set E_BYTE,LV-28 | holds E1 and E3 bits (1 byte) + .set E1,2 | which bit is E1 flag + .set E3,1 | which bit is E3 flag + .set SFLAG,0 | which bit is S flag +| + .set T_BYTE,LV-27 | holds T and U bits (1 byte) + .set XFLAG,7 | which bit is X flag + .set UFLAG,5 | which bit is U flag + .set TFLAG,4 | which bit is T flag +| + .set FPTEMP,LV-24 | fptemp (12 bytes) + .set FPTEMP_EX,FPTEMP | fptemp sign and exponent (2 bytes) + .set FPTEMP_HI,FPTEMP+4 | fptemp mantissa [63:32] (4 bytes) + .set FPTEMP_LO,FPTEMP+8 | fptemp mantissa [31:00] (4 bytes) +| + .set FPTEMP_SGN,FPTEMP+2 | used to store sign +| + .set ETEMP,LV-12 | etemp (12 bytes) + .set ETEMP_EX,ETEMP | etemp sign and exponent (2 bytes) + .set ETEMP_HI,ETEMP+4 | etemp mantissa [63:32] (4 bytes) + .set ETEMP_LO,ETEMP+8 | etemp mantissa [31:00] (4 bytes) +| + .set ETEMP_SGN,ETEMP+2 | used to store sign +| + .set EXC_SR,4 | exception frame status register + .set EXC_PC,6 | exception frame program counter + .set EXC_VEC,10 | exception frame vector (format+vector#) + .set EXC_EA,12 | exception frame effective address +| +|-------------------------------------------------------------------------- +| +| FPSR/FPCR bits +| + .set neg_bit,3 | negative result + .set z_bit,2 | zero result + .set inf_bit,1 | infinity result + .set nan_bit,0 | not-a-number result +| + .set q_sn_bit,7 | sign bit of quotient byte +| + .set bsun_bit,7 | branch on unordered + .set snan_bit,6 | signalling nan + .set operr_bit,5 | operand error + .set ovfl_bit,4 | overflow + .set unfl_bit,3 | underflow + .set dz_bit,2 | divide by zero + .set inex2_bit,1 | inexact result 2 + .set inex1_bit,0 | inexact result 1 +| + .set aiop_bit,7 | accrued illegal operation + .set aovfl_bit,6 | accrued overflow + .set aunfl_bit,5 | accrued underflow + .set adz_bit,4 | accrued divide by zero + .set ainex_bit,3 | accrued inexact +| +| FPSR individual bit masks +| + .set neg_mask,0x08000000 + .set z_mask,0x04000000 + .set inf_mask,0x02000000 + .set nan_mask,0x01000000 +| + .set bsun_mask,0x00008000 | + .set snan_mask,0x00004000 + .set operr_mask,0x00002000 + .set ovfl_mask,0x00001000 + .set unfl_mask,0x00000800 + .set dz_mask,0x00000400 + .set inex2_mask,0x00000200 + .set inex1_mask,0x00000100 +| + .set aiop_mask,0x00000080 | accrued illegal operation + .set aovfl_mask,0x00000040 | accrued overflow + .set aunfl_mask,0x00000020 | accrued underflow + .set adz_mask,0x00000010 | accrued divide by zero + .set ainex_mask,0x00000008 | accrued inexact +| +| FPSR combinations used in the FPSP +| + .set dzinf_mask,inf_mask+dz_mask+adz_mask + .set opnan_mask,nan_mask+operr_mask+aiop_mask + .set nzi_mask,0x01ffffff | clears N, Z, and I + .set unfinx_mask,unfl_mask+inex2_mask+aunfl_mask+ainex_mask + .set unf2inx_mask,unfl_mask+inex2_mask+ainex_mask + .set ovfinx_mask,ovfl_mask+inex2_mask+aovfl_mask+ainex_mask + .set inx1a_mask,inex1_mask+ainex_mask + .set inx2a_mask,inex2_mask+ainex_mask + .set snaniop_mask,nan_mask+snan_mask+aiop_mask + .set naniop_mask,nan_mask+aiop_mask + .set neginf_mask,neg_mask+inf_mask + .set infaiop_mask,inf_mask+aiop_mask + .set negz_mask,neg_mask+z_mask + .set opaop_mask,operr_mask+aiop_mask + .set unfl_inx_mask,unfl_mask+aunfl_mask+ainex_mask + .set ovfl_inx_mask,ovfl_mask+aovfl_mask+ainex_mask +| +|-------------------------------------------------------------------------- +| +| FPCR rounding modes +| + .set x_mode,0x00 | round to extended + .set s_mode,0x40 | round to single + .set d_mode,0x80 | round to double +| + .set rn_mode,0x00 | round nearest + .set rz_mode,0x10 | round to zero + .set rm_mode,0x20 | round to minus infinity + .set rp_mode,0x30 | round to plus infinity +| +|-------------------------------------------------------------------------- +| +| Miscellaneous equates +| + .set signan_bit,6 | signalling nan bit in mantissa + .set sign_bit,7 +| + .set rnd_stky_bit,29 | round/sticky bit of mantissa +| this can only be used if in a data register + .set sx_mask,0x01800000 | set s and x bits in word $48 +| + .set LOCAL_EX,0 + .set LOCAL_SGN,2 + .set LOCAL_HI,4 + .set LOCAL_LO,8 + .set LOCAL_GRS,12 | valid ONLY for FP_SCR1, FP_SCR2 +| +| + .set norm_tag,0x00 | tag bits in {7:5} position + .set zero_tag,0x20 + .set inf_tag,0x40 + .set nan_tag,0x60 + .set dnrm_tag,0x80 +| +| fsave sizes and formats +| + .set VER_4,0x40 | fpsp compatible version numbers +| are in the $40s {$40-$4f} + .set VER_40,0x40 | original version number + .set VER_41,0x41 | revision version number +| + .set BUSY_SIZE,100 | size of busy frame + .set BUSY_FRAME,LV-BUSY_SIZE | start of busy frame +| + .set UNIMP_40_SIZE,44 | size of orig unimp frame + .set UNIMP_41_SIZE,52 | size of rev unimp frame +| + .set IDLE_SIZE,4 | size of idle frame + .set IDLE_FRAME,LV-IDLE_SIZE | start of idle frame +| +| exception vectors +| + .set TRACE_VEC,0x2024 | trace trap + .set FLINE_VEC,0x002C | real F-line + .set UNIMP_VEC,0x202C | unimplemented + .set INEX_VEC,0x00C4 +| + .set dbl_thresh,0x3C01 + .set sgl_thresh,0x3F81 +| diff --git a/arch/m68k/fpsp040/gen_except.S b/arch/m68k/fpsp040/gen_except.S new file mode 100644 index 000000000..3642cb7e3 --- /dev/null +++ b/arch/m68k/fpsp040/gen_except.S @@ -0,0 +1,467 @@ +| +| gen_except.sa 3.7 1/16/92 +| +| gen_except --- FPSP routine to detect reportable exceptions +| +| This routine compares the exception enable byte of the +| user_fpcr on the stack with the exception status byte +| of the user_fpsr. +| +| Any routine which may report an exceptions must load +| the stack frame in memory with the exceptional operand(s). +| +| Priority for exceptions is: +| +| Highest: bsun +| snan +| operr +| ovfl +| unfl +| dz +| inex2 +| Lowest: inex1 +| +| Note: The IEEE standard specifies that inex2 is to be +| reported if ovfl occurs and the ovfl enable bit is not +| set but the inex2 enable bit is. +| +| +| Copyright (C) Motorola, Inc. 1990 +| All Rights Reserved +| +| For details on the license for this file, please see the +| file, README, in this same directory. + +GEN_EXCEPT: |idnt 2,1 | Motorola 040 Floating Point Software Package + + |section 8 + +#include "fpsp.h" + + |xref real_trace + |xref fpsp_done + |xref fpsp_fmt_error + +exc_tbl: + .long bsun_exc + .long commonE1 + .long commonE1 + .long ovfl_unfl + .long ovfl_unfl + .long commonE1 + .long commonE3 + .long commonE3 + .long no_match + + .global gen_except +gen_except: + cmpib #IDLE_SIZE-4,1(%a7) |test for idle frame + beq do_check |go handle idle frame + cmpib #UNIMP_40_SIZE-4,1(%a7) |test for orig unimp frame + beqs unimp_x |go handle unimp frame + cmpib #UNIMP_41_SIZE-4,1(%a7) |test for rev unimp frame + beqs unimp_x |go handle unimp frame + cmpib #BUSY_SIZE-4,1(%a7) |if size <> $60, fmt error + bnel fpsp_fmt_error + leal BUSY_SIZE+LOCAL_SIZE(%a7),%a1 |init a1 so fpsp.h +| ;equates will work +| Fix up the new busy frame with entries from the unimp frame +| + movel ETEMP_EX(%a6),ETEMP_EX(%a1) |copy etemp from unimp + movel ETEMP_HI(%a6),ETEMP_HI(%a1) |frame to busy frame + movel ETEMP_LO(%a6),ETEMP_LO(%a1) + movel CMDREG1B(%a6),CMDREG1B(%a1) |set inst in frame to unimp + movel CMDREG1B(%a6),%d0 |fix cmd1b to make it + andl #0x03c30000,%d0 |work for cmd3b + bfextu CMDREG1B(%a6){#13:#1},%d1 |extract bit 2 + lsll #5,%d1 + swap %d1 + orl %d1,%d0 |put it in the right place + bfextu CMDREG1B(%a6){#10:#3},%d1 |extract bit 3,4,5 + lsll #2,%d1 + swap %d1 + orl %d1,%d0 |put them in the right place + movel %d0,CMDREG3B(%a1) |in the busy frame +| +| Or in the FPSR from the emulation with the USER_FPSR on the stack. +| + fmovel %FPSR,%d0 + orl %d0,USER_FPSR(%a6) + movel USER_FPSR(%a6),FPSR_SHADOW(%a1) |set exc bits + orl #sx_mask,E_BYTE(%a1) + bra do_clean + +| +| Frame is an unimp frame possible resulting from an fmove ,fp0 +| that caused an exception +| +| a1 is modified to point into the new frame allowing fpsp equates +| to be valid. +| +unimp_x: + cmpib #UNIMP_40_SIZE-4,1(%a7) |test for orig unimp frame + bnes test_rev + leal UNIMP_40_SIZE+LOCAL_SIZE(%a7),%a1 + bras unimp_con +test_rev: + cmpib #UNIMP_41_SIZE-4,1(%a7) |test for rev unimp frame + bnel fpsp_fmt_error |if not $28 or $30 + leal UNIMP_41_SIZE+LOCAL_SIZE(%a7),%a1 + +unimp_con: +| +| Fix up the new unimp frame with entries from the old unimp frame +| + movel CMDREG1B(%a6),CMDREG1B(%a1) |set inst in frame to unimp +| +| Or in the FPSR from the emulation with the USER_FPSR on the stack. +| + fmovel %FPSR,%d0 + orl %d0,USER_FPSR(%a6) + bra do_clean + +| +| Frame is idle, so check for exceptions reported through +| USER_FPSR and set the unimp frame accordingly. +| A7 must be incremented to the point before the +| idle fsave vector to the unimp vector. +| + +do_check: + addl #4,%a7 |point A7 back to unimp frame +| +| Or in the FPSR from the emulation with the USER_FPSR on the stack. +| + fmovel %FPSR,%d0 + orl %d0,USER_FPSR(%a6) +| +| On a busy frame, we must clear the nmnexc bits. +| + cmpib #BUSY_SIZE-4,1(%a7) |check frame type + bnes check_fr |if busy, clr nmnexc + clrw NMNEXC(%a6) |clr nmnexc & nmcexc + btstb #5,CMDREG1B(%a6) |test for fmove out + bnes frame_com + movel USER_FPSR(%a6),FPSR_SHADOW(%a6) |set exc bits + orl #sx_mask,E_BYTE(%a6) + bras frame_com +check_fr: + cmpb #UNIMP_40_SIZE-4,1(%a7) + beqs frame_com + clrw NMNEXC(%a6) +frame_com: + moveb FPCR_ENABLE(%a6),%d0 |get fpcr enable byte + andb FPSR_EXCEPT(%a6),%d0 |and in the fpsr exc byte + bfffo %d0{#24:#8},%d1 |test for first set bit + leal exc_tbl,%a0 |load jmp table address + subib #24,%d1 |normalize bit offset to 0-8 + movel (%a0,%d1.w*4),%a0 |load routine address based +| ;based on first enabled exc + jmp (%a0) |jump to routine +| +| Bsun is not possible in unimp or unsupp +| +bsun_exc: + bra do_clean +| +| The typical work to be done to the unimp frame to report an +| exception is to set the E1/E3 byte and clr the U flag. +| commonE1 does this for E1 exceptions, which are snan, +| operr, and dz. commonE3 does this for E3 exceptions, which +| are inex2 and inex1, and also clears the E1 exception bit +| left over from the unimp exception. +| +commonE1: + bsetb #E1,E_BYTE(%a6) |set E1 flag + bra commonE |go clean and exit + +commonE3: + tstb UFLG_TMP(%a6) |test flag for unsup/unimp state + bnes unsE3 +uniE3: + bsetb #E3,E_BYTE(%a6) |set E3 flag + bclrb #E1,E_BYTE(%a6) |clr E1 from unimp + bra commonE + +unsE3: + tstb RES_FLG(%a6) + bnes unsE3_0 +unsE3_1: + bsetb #E3,E_BYTE(%a6) |set E3 flag +unsE3_0: + bclrb #E1,E_BYTE(%a6) |clr E1 flag + movel CMDREG1B(%a6),%d0 + andl #0x03c30000,%d0 |work for cmd3b + bfextu CMDREG1B(%a6){#13:#1},%d1 |extract bit 2 + lsll #5,%d1 + swap %d1 + orl %d1,%d0 |put it in the right place + bfextu CMDREG1B(%a6){#10:#3},%d1 |extract bit 3,4,5 + lsll #2,%d1 + swap %d1 + orl %d1,%d0 |put them in the right place + movel %d0,CMDREG3B(%a6) |in the busy frame + +commonE: + bclrb #UFLAG,T_BYTE(%a6) |clr U flag from unimp + bra do_clean |go clean and exit +| +| No bits in the enable byte match existing exceptions. Check for +| the case of the ovfl exc without the ovfl enabled, but with +| inex2 enabled. +| +no_match: + btstb #inex2_bit,FPCR_ENABLE(%a6) |check for ovfl/inex2 case + beqs no_exc |if clear, exit + btstb #ovfl_bit,FPSR_EXCEPT(%a6) |now check ovfl + beqs no_exc |if clear, exit + bras ovfl_unfl |go to unfl_ovfl to determine if +| ;it is an unsupp or unimp exc + +| No exceptions are to be reported. If the instruction was +| unimplemented, no FPU restore is necessary. If it was +| unsupported, we must perform the restore. +no_exc: + tstb UFLG_TMP(%a6) |test flag for unsupp/unimp state + beqs uni_no_exc +uns_no_exc: + tstb RES_FLG(%a6) |check if frestore is needed + bne do_clean |if clear, no frestore needed +uni_no_exc: + moveml USER_DA(%a6),%d0-%d1/%a0-%a1 + fmovemx USER_FP0(%a6),%fp0-%fp3 + fmoveml USER_FPCR(%a6),%fpcr/%fpsr/%fpiar + unlk %a6 + bra finish_up +| +| Unsupported Data Type Handler: +| Ovfl: +| An fmoveout that results in an overflow is reported this way. +| Unfl: +| An fmoveout that results in an underflow is reported this way. +| +| Unimplemented Instruction Handler: +| Ovfl: +| Only scosh, setox, ssinh, stwotox, and scale can set overflow in +| this manner. +| Unfl: +| Stwotox, setox, and scale can set underflow in this manner. +| Any of the other Library Routines such that f(x)=x in which +| x is an extended denorm can report an underflow exception. +| It is the responsibility of the exception-causing exception +| to make sure that WBTEMP is correct. +| +| The exceptional operand is in FP_SCR1. +| +ovfl_unfl: + tstb UFLG_TMP(%a6) |test flag for unsupp/unimp state + beqs ofuf_con +| +| The caller was from an unsupported data type trap. Test if the +| caller set CU_ONLY. If so, the exceptional operand is expected in +| FPTEMP, rather than WBTEMP. +| + tstb CU_ONLY(%a6) |test if inst is cu-only + beq unsE3 +| move.w #$fe,CU_SAVEPC(%a6) + clrb CU_SAVEPC(%a6) + bsetb #E1,E_BYTE(%a6) |set E1 exception flag + movew ETEMP_EX(%a6),FPTEMP_EX(%a6) + movel ETEMP_HI(%a6),FPTEMP_HI(%a6) + movel ETEMP_LO(%a6),FPTEMP_LO(%a6) + bsetb #fptemp15_bit,DTAG(%a6) |set fpte15 + bclrb #UFLAG,T_BYTE(%a6) |clr U flag from unimp + bra do_clean |go clean and exit + +ofuf_con: + moveb (%a7),VER_TMP(%a6) |save version number + cmpib #BUSY_SIZE-4,1(%a7) |check for busy frame + beqs busy_fr |if unimp, grow to busy + cmpib #VER_40,(%a7) |test for orig unimp frame + bnes try_41 |if not, test for rev frame + moveql #13,%d0 |need to zero 14 lwords + bras ofuf_fin +try_41: + cmpib #VER_41,(%a7) |test for rev unimp frame + bnel fpsp_fmt_error |if neither, exit with error + moveql #11,%d0 |need to zero 12 lwords + +ofuf_fin: + clrl (%a7) +loop1: + clrl -(%a7) |clear and dec a7 + dbra %d0,loop1 + moveb VER_TMP(%a6),(%a7) + moveb #BUSY_SIZE-4,1(%a7) |write busy fmt word. +busy_fr: + movel FP_SCR1(%a6),WBTEMP_EX(%a6) |write + movel FP_SCR1+4(%a6),WBTEMP_HI(%a6) |exceptional op to + movel FP_SCR1+8(%a6),WBTEMP_LO(%a6) |wbtemp + bsetb #E3,E_BYTE(%a6) |set E3 flag + bclrb #E1,E_BYTE(%a6) |make sure E1 is clear + bclrb #UFLAG,T_BYTE(%a6) |clr U flag + movel USER_FPSR(%a6),FPSR_SHADOW(%a6) + orl #sx_mask,E_BYTE(%a6) + movel CMDREG1B(%a6),%d0 |fix cmd1b to make it + andl #0x03c30000,%d0 |work for cmd3b + bfextu CMDREG1B(%a6){#13:#1},%d1 |extract bit 2 + lsll #5,%d1 + swap %d1 + orl %d1,%d0 |put it in the right place + bfextu CMDREG1B(%a6){#10:#3},%d1 |extract bit 3,4,5 + lsll #2,%d1 + swap %d1 + orl %d1,%d0 |put them in the right place + movel %d0,CMDREG3B(%a6) |in the busy frame + +| +| Check if the frame to be restored is busy or unimp. +|** NOTE *** Bug fix for errata (0d43b #3) +| If the frame is unimp, we must create a busy frame to +| fix the bug with the nmnexc bits in cases in which they +| are set by a previous instruction and not cleared by +| the save. The frame will be unimp only if the final +| instruction in an emulation routine caused the exception +| by doing an fmove ,fp0. The exception operand, in +| internal format, is in fptemp. +| +do_clean: + cmpib #UNIMP_40_SIZE-4,1(%a7) + bnes do_con + moveql #13,%d0 |in orig, need to zero 14 lwords + bras do_build +do_con: + cmpib #UNIMP_41_SIZE-4,1(%a7) + bnes do_restore |frame must be busy + moveql #11,%d0 |in rev, need to zero 12 lwords + +do_build: + moveb (%a7),VER_TMP(%a6) + clrl (%a7) +loop2: + clrl -(%a7) |clear and dec a7 + dbra %d0,loop2 +| +| Use a1 as pointer into new frame. a6 is not correct if an unimp or +| busy frame was created as the result of an exception on the final +| instruction of an emulation routine. +| +| We need to set the nmcexc bits if the exception is E1. Otherwise, +| the exc taken will be inex2. +| + leal BUSY_SIZE+LOCAL_SIZE(%a7),%a1 |init a1 for new frame + moveb VER_TMP(%a6),(%a7) |write busy fmt word + moveb #BUSY_SIZE-4,1(%a7) + movel FP_SCR1(%a6),WBTEMP_EX(%a1) |write + movel FP_SCR1+4(%a6),WBTEMP_HI(%a1) |exceptional op to + movel FP_SCR1+8(%a6),WBTEMP_LO(%a1) |wbtemp +| btst.b #E1,E_BYTE(%a1) +| beq.b do_restore + bfextu USER_FPSR(%a6){#17:#4},%d0 |get snan/operr/ovfl/unfl bits + bfins %d0,NMCEXC(%a1){#4:#4} |and insert them in nmcexc + movel USER_FPSR(%a6),FPSR_SHADOW(%a1) |set exc bits + orl #sx_mask,E_BYTE(%a1) + +do_restore: + moveml USER_DA(%a6),%d0-%d1/%a0-%a1 + fmovemx USER_FP0(%a6),%fp0-%fp3 + fmoveml USER_FPCR(%a6),%fpcr/%fpsr/%fpiar + frestore (%a7)+ + tstb RES_FLG(%a6) |RES_FLG indicates a "continuation" frame + beq cont + bsr bug1384 +cont: + unlk %a6 +| +| If trace mode enabled, then go to trace handler. This handler +| cannot have any fp instructions. If there are fp inst's and an +| exception has been restored into the machine then the exception +| will occur upon execution of the fp inst. This is not desirable +| in the kernel (supervisor mode). See MC68040 manual Section 9.3.8. +| +finish_up: + btstb #7,(%a7) |test T1 in SR + bnes g_trace + btstb #6,(%a7) |test T0 in SR + bnes g_trace + bral fpsp_done +| +| Change integer stack to look like trace stack +| The address of the instruction that caused the +| exception is already in the integer stack (is +| the same as the saved friar) +| +| If the current frame is already a 6-word stack then all +| that needs to be done is to change the vector# to TRACE. +| If the frame is only a 4-word stack (meaning we got here +| on an Unsupported data type exception), then we need to grow +| the stack an extra 2 words and get the FPIAR from the FPU. +| +g_trace: + bftst EXC_VEC-4(%sp){#0:#4} + bne g_easy + + subw #4,%sp | make room + movel 4(%sp),(%sp) + movel 8(%sp),4(%sp) + subw #BUSY_SIZE,%sp + fsave (%sp) + fmovel %fpiar,BUSY_SIZE+EXC_EA-4(%sp) + frestore (%sp) + addw #BUSY_SIZE,%sp + +g_easy: + movew #TRACE_VEC,EXC_VEC-4(%a7) + bral real_trace +| +| This is a work-around for hardware bug 1384. +| +bug1384: + link %a5,#0 + fsave -(%sp) + cmpib #0x41,(%sp) | check for correct frame + beq frame_41 + bgt nofix | if more advanced mask, do nada + +frame_40: + tstb 1(%sp) | check to see if idle + bne notidle +idle40: + clrl (%sp) | get rid of old fsave frame + movel %d1,USER_D1(%a6) | save d1 + movew #8,%d1 | place unimp frame instead +loop40: clrl -(%sp) + dbra %d1,loop40 + movel USER_D1(%a6),%d1 | restore d1 + movel #0x40280000,-(%sp) + frestore (%sp)+ + unlk %a5 + rts + +frame_41: + tstb 1(%sp) | check to see if idle + bne notidle +idle41: + clrl (%sp) | get rid of old fsave frame + movel %d1,USER_D1(%a6) | save d1 + movew #10,%d1 | place unimp frame instead +loop41: clrl -(%sp) + dbra %d1,loop41 + movel USER_D1(%a6),%d1 | restore d1 + movel #0x41300000,-(%sp) + frestore (%sp)+ + unlk %a5 + rts + +notidle: + bclrb #etemp15_bit,-40(%a5) + frestore (%sp)+ + unlk %a5 + rts + +nofix: + frestore (%sp)+ + unlk %a5 + rts + + |end diff --git a/arch/m68k/fpsp040/get_op.S b/arch/m68k/fpsp040/get_op.S new file mode 100644 index 000000000..64c36d79e --- /dev/null +++ b/arch/m68k/fpsp040/get_op.S @@ -0,0 +1,675 @@ +| +| get_op.sa 3.6 5/19/92 +| +| get_op.sa 3.5 4/26/91 +| +| Description: This routine is called by the unsupported format/data +| type exception handler ('unsupp' - vector 55) and the unimplemented +| instruction exception handler ('unimp' - vector 11). 'get_op' +| determines the opclass (0, 2, or 3) and branches to the +| opclass handler routine. See 68881/2 User's Manual table 4-11 +| for a description of the opclasses. +| +| For UNSUPPORTED data/format (exception vector 55) and for +| UNIMPLEMENTED instructions (exception vector 11) the following +| applies: +| +| - For unnormalized numbers (opclass 0, 2, or 3) the +| number(s) is normalized and the operand type tag is updated. +| +| - For a packed number (opclass 2) the number is unpacked and the +| operand type tag is updated. +| +| - For denormalized numbers (opclass 0 or 2) the number(s) is not +| changed but passed to the next module. The next module for +| unimp is do_func, the next module for unsupp is res_func. +| +| For UNSUPPORTED data/format (exception vector 55) only the +| following applies: +| +| - If there is a move out with a packed number (opclass 3) the +| number is packed and written to user memory. For the other +| opclasses the number(s) are written back to the fsave stack +| and the instruction is then restored back into the '040. The +| '040 is then able to complete the instruction. +| +| For example: +| fadd.x fpm,fpn where the fpm contains an unnormalized number. +| The '040 takes an unsupported data trap and gets to this +| routine. The number is normalized, put back on the stack and +| then an frestore is done to restore the instruction back into +| the '040. The '040 then re-executes the fadd.x fpm,fpn with +| a normalized number in the source and the instruction is +| successful. +| +| Next consider if in the process of normalizing the un- +| normalized number it becomes a denormalized number. The +| routine which converts the unnorm to a norm (called mk_norm) +| detects this and tags the number as a denorm. The routine +| res_func sees the denorm tag and converts the denorm to a +| norm. The instruction is then restored back into the '040 +| which re_executes the instruction. +| +| +| Copyright (C) Motorola, Inc. 1990 +| All Rights Reserved +| +| For details on the license for this file, please see the +| file, README, in this same directory. + +GET_OP: |idnt 2,1 | Motorola 040 Floating Point Software Package + + |section 8 + +#include "fpsp.h" + + .global PIRN,PIRZRM,PIRP + .global SMALRN,SMALRZRM,SMALRP + .global BIGRN,BIGRZRM,BIGRP + +PIRN: + .long 0x40000000,0xc90fdaa2,0x2168c235 |pi +PIRZRM: + .long 0x40000000,0xc90fdaa2,0x2168c234 |pi +PIRP: + .long 0x40000000,0xc90fdaa2,0x2168c235 |pi + +|round to nearest +SMALRN: + .long 0x3ffd0000,0x9a209a84,0xfbcff798 |log10(2) + .long 0x40000000,0xadf85458,0xa2bb4a9a |e + .long 0x3fff0000,0xb8aa3b29,0x5c17f0bc |log2(e) + .long 0x3ffd0000,0xde5bd8a9,0x37287195 |log10(e) + .long 0x00000000,0x00000000,0x00000000 |0.0 +| round to zero;round to negative infinity +SMALRZRM: + .long 0x3ffd0000,0x9a209a84,0xfbcff798 |log10(2) + .long 0x40000000,0xadf85458,0xa2bb4a9a |e + .long 0x3fff0000,0xb8aa3b29,0x5c17f0bb |log2(e) + .long 0x3ffd0000,0xde5bd8a9,0x37287195 |log10(e) + .long 0x00000000,0x00000000,0x00000000 |0.0 +| round to positive infinity +SMALRP: + .long 0x3ffd0000,0x9a209a84,0xfbcff799 |log10(2) + .long 0x40000000,0xadf85458,0xa2bb4a9b |e + .long 0x3fff0000,0xb8aa3b29,0x5c17f0bc |log2(e) + .long 0x3ffd0000,0xde5bd8a9,0x37287195 |log10(e) + .long 0x00000000,0x00000000,0x00000000 |0.0 + +|round to nearest +BIGRN: + .long 0x3ffe0000,0xb17217f7,0xd1cf79ac |ln(2) + .long 0x40000000,0x935d8ddd,0xaaa8ac17 |ln(10) + .long 0x3fff0000,0x80000000,0x00000000 |10 ^ 0 + + .global PTENRN +PTENRN: + .long 0x40020000,0xA0000000,0x00000000 |10 ^ 1 + .long 0x40050000,0xC8000000,0x00000000 |10 ^ 2 + .long 0x400C0000,0x9C400000,0x00000000 |10 ^ 4 + .long 0x40190000,0xBEBC2000,0x00000000 |10 ^ 8 + .long 0x40340000,0x8E1BC9BF,0x04000000 |10 ^ 16 + .long 0x40690000,0x9DC5ADA8,0x2B70B59E |10 ^ 32 + .long 0x40D30000,0xC2781F49,0xFFCFA6D5 |10 ^ 64 + .long 0x41A80000,0x93BA47C9,0x80E98CE0 |10 ^ 128 + .long 0x43510000,0xAA7EEBFB,0x9DF9DE8E |10 ^ 256 + .long 0x46A30000,0xE319A0AE,0xA60E91C7 |10 ^ 512 + .long 0x4D480000,0xC9767586,0x81750C17 |10 ^ 1024 + .long 0x5A920000,0x9E8B3B5D,0xC53D5DE5 |10 ^ 2048 + .long 0x75250000,0xC4605202,0x8A20979B |10 ^ 4096 +|round to minus infinity +BIGRZRM: + .long 0x3ffe0000,0xb17217f7,0xd1cf79ab |ln(2) + .long 0x40000000,0x935d8ddd,0xaaa8ac16 |ln(10) + .long 0x3fff0000,0x80000000,0x00000000 |10 ^ 0 + + .global PTENRM +PTENRM: + .long 0x40020000,0xA0000000,0x00000000 |10 ^ 1 + .long 0x40050000,0xC8000000,0x00000000 |10 ^ 2 + .long 0x400C0000,0x9C400000,0x00000000 |10 ^ 4 + .long 0x40190000,0xBEBC2000,0x00000000 |10 ^ 8 + .long 0x40340000,0x8E1BC9BF,0x04000000 |10 ^ 16 + .long 0x40690000,0x9DC5ADA8,0x2B70B59D |10 ^ 32 + .long 0x40D30000,0xC2781F49,0xFFCFA6D5 |10 ^ 64 + .long 0x41A80000,0x93BA47C9,0x80E98CDF |10 ^ 128 + .long 0x43510000,0xAA7EEBFB,0x9DF9DE8D |10 ^ 256 + .long 0x46A30000,0xE319A0AE,0xA60E91C6 |10 ^ 512 + .long 0x4D480000,0xC9767586,0x81750C17 |10 ^ 1024 + .long 0x5A920000,0x9E8B3B5D,0xC53D5DE5 |10 ^ 2048 + .long 0x75250000,0xC4605202,0x8A20979A |10 ^ 4096 +|round to positive infinity +BIGRP: + .long 0x3ffe0000,0xb17217f7,0xd1cf79ac |ln(2) + .long 0x40000000,0x935d8ddd,0xaaa8ac17 |ln(10) + .long 0x3fff0000,0x80000000,0x00000000 |10 ^ 0 + + .global PTENRP +PTENRP: + .long 0x40020000,0xA0000000,0x00000000 |10 ^ 1 + .long 0x40050000,0xC8000000,0x00000000 |10 ^ 2 + .long 0x400C0000,0x9C400000,0x00000000 |10 ^ 4 + .long 0x40190000,0xBEBC2000,0x00000000 |10 ^ 8 + .long 0x40340000,0x8E1BC9BF,0x04000000 |10 ^ 16 + .long 0x40690000,0x9DC5ADA8,0x2B70B59E |10 ^ 32 + .long 0x40D30000,0xC2781F49,0xFFCFA6D6 |10 ^ 64 + .long 0x41A80000,0x93BA47C9,0x80E98CE0 |10 ^ 128 + .long 0x43510000,0xAA7EEBFB,0x9DF9DE8E |10 ^ 256 + .long 0x46A30000,0xE319A0AE,0xA60E91C7 |10 ^ 512 + .long 0x4D480000,0xC9767586,0x81750C18 |10 ^ 1024 + .long 0x5A920000,0x9E8B3B5D,0xC53D5DE6 |10 ^ 2048 + .long 0x75250000,0xC4605202,0x8A20979B |10 ^ 4096 + + |xref nrm_zero + |xref decbin + |xref round + + .global get_op + .global uns_getop + .global uni_getop +get_op: + clrb DY_MO_FLG(%a6) + tstb UFLG_TMP(%a6) |test flag for unsupp/unimp state + beq uni_getop + +uns_getop: + btstb #direction_bit,CMDREG1B(%a6) + bne opclass3 |branch if a fmove out (any kind) + btstb #6,CMDREG1B(%a6) + beqs uns_notpacked + + bfextu CMDREG1B(%a6){#3:#3},%d0 + cmpb #3,%d0 + beq pack_source |check for a packed src op, branch if so +uns_notpacked: + bsr chk_dy_mo |set the dyadic/monadic flag + tstb DY_MO_FLG(%a6) + beqs src_op_ck |if monadic, go check src op +| ;else, check dst op (fall through) + + btstb #7,DTAG(%a6) + beqs src_op_ck |if dst op is norm, check src op + bras dst_ex_dnrm |else, handle destination unnorm/dnrm + +uni_getop: + bfextu CMDREG1B(%a6){#0:#6},%d0 |get opclass and src fields + cmpil #0x17,%d0 |if op class and size fields are $17, +| ;it is FMOVECR; if not, continue +| +| If the instruction is fmovecr, exit get_op. It is handled +| in do_func and smovecr.sa. +| + bne not_fmovecr |handle fmovecr as an unimplemented inst + rts + +not_fmovecr: + btstb #E1,E_BYTE(%a6) |if set, there is a packed operand + bne pack_source |check for packed src op, branch if so + +| The following lines of are coded to optimize on normalized operands + moveb STAG(%a6),%d0 + orb DTAG(%a6),%d0 |check if either of STAG/DTAG msb set + bmis dest_op_ck |if so, some op needs to be fixed + rts + +dest_op_ck: + btstb #7,DTAG(%a6) |check for unsupported data types in + beqs src_op_ck |the destination, if not, check src op + bsr chk_dy_mo |set dyadic/monadic flag + tstb DY_MO_FLG(%a6) | + beqs src_op_ck |if monadic, check src op +| +| At this point, destination has an extended denorm or unnorm. +| +dst_ex_dnrm: + movew FPTEMP_EX(%a6),%d0 |get destination exponent + andiw #0x7fff,%d0 |mask sign, check if exp = 0000 + beqs src_op_ck |if denorm then check source op. +| ;denorms are taken care of in res_func +| ;(unsupp) or do_func (unimp) +| ;else unnorm fall through + leal FPTEMP(%a6),%a0 |point a0 to dop - used in mk_norm + bsr mk_norm |go normalize - mk_norm returns: +| ;L_SCR1{7:5} = operand tag +| ; (000 = norm, 100 = denorm) +| ;L_SCR1{4} = fpte15 or ete15 +| ; 0 = exp > $3fff +| ; 1 = exp <= $3fff +| ;and puts the normalized num back +| ;on the fsave stack +| + moveb L_SCR1(%a6),DTAG(%a6) |write the new tag & fpte15 +| ;to the fsave stack and fall +| ;through to check source operand +| +src_op_ck: + btstb #7,STAG(%a6) + beq end_getop |check for unsupported data types on the +| ;source operand + btstb #5,STAG(%a6) + bnes src_sd_dnrm |if bit 5 set, handle sgl/dbl denorms +| +| At this point only unnorms or extended denorms are possible. +| +src_ex_dnrm: + movew ETEMP_EX(%a6),%d0 |get source exponent + andiw #0x7fff,%d0 |mask sign, check if exp = 0000 + beq end_getop |if denorm then exit, denorms are +| ;handled in do_func + leal ETEMP(%a6),%a0 |point a0 to sop - used in mk_norm + bsr mk_norm |go normalize - mk_norm returns: +| ;L_SCR1{7:5} = operand tag +| ; (000 = norm, 100 = denorm) +| ;L_SCR1{4} = fpte15 or ete15 +| ; 0 = exp > $3fff +| ; 1 = exp <= $3fff +| ;and puts the normalized num back +| ;on the fsave stack +| + moveb L_SCR1(%a6),STAG(%a6) |write the new tag & ete15 + rts |end_getop + +| +| At this point, only single or double denorms are possible. +| If the inst is not fmove, normalize the source. If it is, +| do nothing to the input. +| +src_sd_dnrm: + btstb #4,CMDREG1B(%a6) |differentiate between sgl/dbl denorm + bnes is_double +is_single: + movew #0x3f81,%d1 |write bias for sgl denorm + bras common |goto the common code +is_double: + movew #0x3c01,%d1 |write the bias for a dbl denorm +common: + btstb #sign_bit,ETEMP_EX(%a6) |grab sign bit of mantissa + beqs pos + bset #15,%d1 |set sign bit because it is negative +pos: + movew %d1,ETEMP_EX(%a6) +| ;put exponent on stack + + movew CMDREG1B(%a6),%d1 + andw #0xe3ff,%d1 |clear out source specifier + orw #0x0800,%d1 |set source specifier to extended prec + movew %d1,CMDREG1B(%a6) |write back to the command word in stack +| ;this is needed to fix unsupp data stack + leal ETEMP(%a6),%a0 |point a0 to sop + + bsr mk_norm |convert sgl/dbl denorm to norm + moveb L_SCR1(%a6),STAG(%a6) |put tag into source tag reg - d0 + rts |end_getop +| +| At this point, the source is definitely packed, whether +| instruction is dyadic or monadic is still unknown +| +pack_source: + movel FPTEMP_LO(%a6),ETEMP(%a6) |write ms part of packed +| ;number to etemp slot + bsr chk_dy_mo |set dyadic/monadic flag + bsr unpack + + tstb DY_MO_FLG(%a6) + beqs end_getop |if monadic, exit +| ;else, fix FPTEMP +pack_dya: + bfextu CMDREG1B(%a6){#6:#3},%d0 |extract dest fp reg + movel #7,%d1 + subl %d0,%d1 + clrl %d0 + bsetl %d1,%d0 |set up d0 as a dynamic register mask + fmovemx %d0,FPTEMP(%a6) |write to FPTEMP + + btstb #7,DTAG(%a6) |check dest tag for unnorm or denorm + bne dst_ex_dnrm |else, handle the unnorm or ext denorm +| +| Dest is not denormalized. Check for norm, and set fpte15 +| accordingly. +| + moveb DTAG(%a6),%d0 + andib #0xf0,%d0 |strip to only dtag:fpte15 + tstb %d0 |check for normalized value + bnes end_getop |if inf/nan/zero leave get_op + movew FPTEMP_EX(%a6),%d0 + andiw #0x7fff,%d0 + cmpiw #0x3fff,%d0 |check if fpte15 needs setting + bges end_getop |if >= $3fff, leave fpte15=0 + orb #0x10,DTAG(%a6) + bras end_getop + +| +| At this point, it is either an fmoveout packed, unnorm or denorm +| +opclass3: + clrb DY_MO_FLG(%a6) |set dyadic/monadic flag to monadic + bfextu CMDREG1B(%a6){#4:#2},%d0 + cmpib #3,%d0 + bne src_ex_dnrm |if not equal, must be unnorm or denorm +| ;else it is a packed move out +| ;exit +end_getop: + rts + +| +| Sets the DY_MO_FLG correctly. This is used only on if it is an +| unsupported data type exception. Set if dyadic. +| +chk_dy_mo: + movew CMDREG1B(%a6),%d0 + btstl #5,%d0 |testing extension command word + beqs set_mon |if bit 5 = 0 then monadic + btstl #4,%d0 |know that bit 5 = 1 + beqs set_dya |if bit 4 = 0 then dyadic + andiw #0x007f,%d0 |get rid of all but extension bits {6:0} + cmpiw #0x0038,%d0 |if extension = $38 then fcmp (dyadic) + bnes set_mon +set_dya: + st DY_MO_FLG(%a6) |set the inst flag type to dyadic + rts +set_mon: + clrb DY_MO_FLG(%a6) |set the inst flag type to monadic + rts +| +| MK_NORM +| +| Normalizes unnormalized numbers, sets tag to norm or denorm, sets unfl +| exception if denorm. +| +| CASE opclass 0x0 unsupp +| mk_norm till msb set +| set tag = norm +| +| CASE opclass 0x0 unimp +| mk_norm till msb set or exp = 0 +| if integer bit = 0 +| tag = denorm +| else +| tag = norm +| +| CASE opclass 011 unsupp +| mk_norm till msb set or exp = 0 +| if integer bit = 0 +| tag = denorm +| set unfl_nmcexe = 1 +| else +| tag = norm +| +| if exp <= $3fff +| set ete15 or fpte15 = 1 +| else set ete15 or fpte15 = 0 + +| input: +| a0 = points to operand to be normalized +| output: +| L_SCR1{7:5} = operand tag (000 = norm, 100 = denorm) +| L_SCR1{4} = fpte15 or ete15 (0 = exp > $3fff, 1 = exp <=$3fff) +| the normalized operand is placed back on the fsave stack +mk_norm: + clrl L_SCR1(%a6) + bclrb #sign_bit,LOCAL_EX(%a0) + sne LOCAL_SGN(%a0) |transform into internal extended format + + cmpib #0x2c,1+EXC_VEC(%a6) |check if unimp + bnes uns_data |branch if unsupp + bsr uni_inst |call if unimp (opclass 0x0) + bras reload +uns_data: + btstb #direction_bit,CMDREG1B(%a6) |check transfer direction + bnes bit_set |branch if set (opclass 011) + bsr uns_opx |call if opclass 0x0 + bras reload +bit_set: + bsr uns_op3 |opclass 011 +reload: + cmpw #0x3fff,LOCAL_EX(%a0) |if exp > $3fff + bgts end_mk | fpte15/ete15 already set to 0 + bsetb #4,L_SCR1(%a6) |else set fpte15/ete15 to 1 +| ;calling routine actually sets the +| ;value on the stack (along with the +| ;tag), since this routine doesn't +| ;know if it should set ete15 or fpte15 +| ;ie, it doesn't know if this is the +| ;src op or dest op. +end_mk: + bfclr LOCAL_SGN(%a0){#0:#8} + beqs end_mk_pos + bsetb #sign_bit,LOCAL_EX(%a0) |convert back to IEEE format +end_mk_pos: + rts +| +| CASE opclass 011 unsupp +| +uns_op3: + bsr nrm_zero |normalize till msb = 1 or exp = zero + btstb #7,LOCAL_HI(%a0) |if msb = 1 + bnes no_unfl |then branch +set_unfl: + orw #dnrm_tag,L_SCR1(%a6) |set denorm tag + bsetb #unfl_bit,FPSR_EXCEPT(%a6) |set unfl exception bit +no_unfl: + rts +| +| CASE opclass 0x0 unsupp +| +uns_opx: + bsr nrm_zero |normalize the number + btstb #7,LOCAL_HI(%a0) |check if integer bit (j-bit) is set + beqs uns_den |if clear then now have a denorm +uns_nrm: + orb #norm_tag,L_SCR1(%a6) |set tag to norm + rts +uns_den: + orb #dnrm_tag,L_SCR1(%a6) |set tag to denorm + rts +| +| CASE opclass 0x0 unimp +| +uni_inst: + bsr nrm_zero + btstb #7,LOCAL_HI(%a0) |check if integer bit (j-bit) is set + beqs uni_den |if clear then now have a denorm +uni_nrm: + orb #norm_tag,L_SCR1(%a6) |set tag to norm + rts +uni_den: + orb #dnrm_tag,L_SCR1(%a6) |set tag to denorm + rts + +| +| Decimal to binary conversion +| +| Special cases of inf and NaNs are completed outside of decbin. +| If the input is an snan, the snan bit is not set. +| +| input: +| ETEMP(a6) - points to packed decimal string in memory +| output: +| fp0 - contains packed string converted to extended precision +| ETEMP - same as fp0 +unpack: + movew CMDREG1B(%a6),%d0 |examine command word, looking for fmove's + andw #0x3b,%d0 + beq move_unpack |special handling for fmove: must set FPSR_CC + + movew ETEMP(%a6),%d0 |get word with inf information + bfextu %d0{#20:#12},%d1 |get exponent into d1 + cmpiw #0x0fff,%d1 |test for inf or NaN + bnes try_zero |if not equal, it is not special + bfextu %d0{#17:#3},%d1 |get SE and y bits into d1 + cmpiw #7,%d1 |SE and y bits must be on for special + bnes try_zero |if not on, it is not special +|input is of the special cases of inf and NaN + tstl ETEMP_HI(%a6) |check ms mantissa + bnes fix_nan |if non-zero, it is a NaN + tstl ETEMP_LO(%a6) |check ls mantissa + bnes fix_nan |if non-zero, it is a NaN + bra finish |special already on stack +fix_nan: + btstb #signan_bit,ETEMP_HI(%a6) |test for snan + bne finish + orl #snaniop_mask,USER_FPSR(%a6) |always set snan if it is so + bra finish +try_zero: + movew ETEMP_EX+2(%a6),%d0 |get word 4 + andiw #0x000f,%d0 |clear all but last ni(y)bble + tstw %d0 |check for zero. + bne not_spec + tstl ETEMP_HI(%a6) |check words 3 and 2 + bne not_spec + tstl ETEMP_LO(%a6) |check words 1 and 0 + bne not_spec + tstl ETEMP(%a6) |test sign of the zero + bges pos_zero + movel #0x80000000,ETEMP(%a6) |write neg zero to etemp + clrl ETEMP_HI(%a6) + clrl ETEMP_LO(%a6) + bra finish +pos_zero: + clrl ETEMP(%a6) + clrl ETEMP_HI(%a6) + clrl ETEMP_LO(%a6) + bra finish + +not_spec: + fmovemx %fp0-%fp1,-(%a7) |save fp0 - decbin returns in it + bsr decbin + fmovex %fp0,ETEMP(%a6) |put the unpacked sop in the fsave stack + fmovemx (%a7)+,%fp0-%fp1 + fmovel #0,%FPSR |clr fpsr from decbin + bra finish + +| +| Special handling for packed move in: Same results as all other +| packed cases, but we must set the FPSR condition codes properly. +| +move_unpack: + movew ETEMP(%a6),%d0 |get word with inf information + bfextu %d0{#20:#12},%d1 |get exponent into d1 + cmpiw #0x0fff,%d1 |test for inf or NaN + bnes mtry_zero |if not equal, it is not special + bfextu %d0{#17:#3},%d1 |get SE and y bits into d1 + cmpiw #7,%d1 |SE and y bits must be on for special + bnes mtry_zero |if not on, it is not special +|input is of the special cases of inf and NaN + tstl ETEMP_HI(%a6) |check ms mantissa + bnes mfix_nan |if non-zero, it is a NaN + tstl ETEMP_LO(%a6) |check ls mantissa + bnes mfix_nan |if non-zero, it is a NaN +|input is inf + orl #inf_mask,USER_FPSR(%a6) |set I bit + tstl ETEMP(%a6) |check sign + bge finish + orl #neg_mask,USER_FPSR(%a6) |set N bit + bra finish |special already on stack +mfix_nan: + orl #nan_mask,USER_FPSR(%a6) |set NaN bit + moveb #nan_tag,STAG(%a6) |set stag to NaN + btstb #signan_bit,ETEMP_HI(%a6) |test for snan + bnes mn_snan + orl #snaniop_mask,USER_FPSR(%a6) |set snan bit + btstb #snan_bit,FPCR_ENABLE(%a6) |test for snan enabled + bnes mn_snan + bsetb #signan_bit,ETEMP_HI(%a6) |force snans to qnans +mn_snan: + tstl ETEMP(%a6) |check for sign + bge finish |if clr, go on + orl #neg_mask,USER_FPSR(%a6) |set N bit + bra finish + +mtry_zero: + movew ETEMP_EX+2(%a6),%d0 |get word 4 + andiw #0x000f,%d0 |clear all but last ni(y)bble + tstw %d0 |check for zero. + bnes mnot_spec + tstl ETEMP_HI(%a6) |check words 3 and 2 + bnes mnot_spec + tstl ETEMP_LO(%a6) |check words 1 and 0 + bnes mnot_spec + tstl ETEMP(%a6) |test sign of the zero + bges mpos_zero + orl #neg_mask+z_mask,USER_FPSR(%a6) |set N and Z + movel #0x80000000,ETEMP(%a6) |write neg zero to etemp + clrl ETEMP_HI(%a6) + clrl ETEMP_LO(%a6) + bras finish +mpos_zero: + orl #z_mask,USER_FPSR(%a6) |set Z + clrl ETEMP(%a6) + clrl ETEMP_HI(%a6) + clrl ETEMP_LO(%a6) + bras finish + +mnot_spec: + fmovemx %fp0-%fp1,-(%a7) |save fp0 ,fp1 - decbin returns in fp0 + bsr decbin + fmovex %fp0,ETEMP(%a6) +| ;put the unpacked sop in the fsave stack + fmovemx (%a7)+,%fp0-%fp1 + +finish: + movew CMDREG1B(%a6),%d0 |get the command word + andw #0xfbff,%d0 |change the source specifier field to +| ;extended (was packed). + movew %d0,CMDREG1B(%a6) |write command word back to fsave stack +| ;we need to do this so the 040 will +| ;re-execute the inst. without taking +| ;another packed trap. + +fix_stag: +|Converted result is now in etemp on fsave stack, now set the source +|tag (stag) +| if (ete =$7fff) then INF or NAN +| if (etemp = $x.0----0) then +| stag = INF +| else +| stag = NAN +| else +| if (ete = $0000) then +| stag = ZERO +| else +| stag = NORM +| +| Note also that the etemp_15 bit (just right of the stag) must +| be set accordingly. +| + movew ETEMP_EX(%a6),%d1 + andiw #0x7fff,%d1 |strip sign + cmpw #0x7fff,%d1 + bnes z_or_nrm + movel ETEMP_HI(%a6),%d1 + bnes is_nan + movel ETEMP_LO(%a6),%d1 + bnes is_nan +is_inf: + moveb #0x40,STAG(%a6) + movel #0x40,%d0 + rts +is_nan: + moveb #0x60,STAG(%a6) + movel #0x60,%d0 + rts +z_or_nrm: + tstw %d1 + bnes is_nrm +is_zro: +| For a zero, set etemp_15 + moveb #0x30,STAG(%a6) + movel #0x20,%d0 + rts +is_nrm: +| For a norm, check if the exp <= $3fff; if so, set etemp_15 + cmpiw #0x3fff,%d1 + bles set_bit15 + moveb #0,STAG(%a6) + bras end_is_nrm +set_bit15: + moveb #0x10,STAG(%a6) +end_is_nrm: + movel #0,%d0 +end_fix: + rts + +end_get: + rts + |end diff --git a/arch/m68k/fpsp040/kernel_ex.S b/arch/m68k/fpsp040/kernel_ex.S new file mode 100644 index 000000000..45bcf3455 --- /dev/null +++ b/arch/m68k/fpsp040/kernel_ex.S @@ -0,0 +1,493 @@ +| +| kernel_ex.sa 3.3 12/19/90 +| +| This file contains routines to force exception status in the +| fpu for exceptional cases detected or reported within the +| transcendental functions. Typically, the t_xx routine will +| set the appropriate bits in the USER_FPSR word on the stack. +| The bits are tested in gen_except.sa to determine if an exceptional +| situation needs to be created on return from the FPSP. +| + +| Copyright (C) Motorola, Inc. 1990 +| All Rights Reserved +| +| For details on the license for this file, please see the +| file, README, in this same directory. + +KERNEL_EX: |idnt 2,1 | Motorola 040 Floating Point Software Package + + |section 8 + +#include "fpsp.h" + +mns_inf: .long 0xffff0000,0x00000000,0x00000000 +pls_inf: .long 0x7fff0000,0x00000000,0x00000000 +nan: .long 0x7fff0000,0xffffffff,0xffffffff +huge: .long 0x7ffe0000,0xffffffff,0xffffffff + + |xref ovf_r_k + |xref unf_sub + |xref nrm_set + + .global t_dz + .global t_dz2 + .global t_operr + .global t_unfl + .global t_ovfl + .global t_ovfl2 + .global t_inx2 + .global t_frcinx + .global t_extdnrm + .global t_resdnrm + .global dst_nan + .global src_nan +| +| DZ exception +| +| +| if dz trap disabled +| store properly signed inf (use sign of etemp) into fp0 +| set FPSR exception status dz bit, condition code +| inf bit, and accrued dz bit +| return +| frestore the frame into the machine (done by unimp_hd) +| +| else dz trap enabled +| set exception status bit & accrued bits in FPSR +| set flag to disable sto_res from corrupting fp register +| return +| frestore the frame into the machine (done by unimp_hd) +| +| t_dz2 is used by monadic functions such as flogn (from do_func). +| t_dz is used by monadic functions such as satanh (from the +| transcendental function). +| +t_dz2: + bsetb #neg_bit,FPSR_CC(%a6) |set neg bit in FPSR + fmovel #0,%FPSR |clr status bits (Z set) + btstb #dz_bit,FPCR_ENABLE(%a6) |test FPCR for dz exc enabled + bnes dz_ena_end + bras m_inf |flogx always returns -inf +t_dz: + fmovel #0,%FPSR |clr status bits (Z set) + btstb #dz_bit,FPCR_ENABLE(%a6) |test FPCR for dz exc enabled + bnes dz_ena +| +| dz disabled +| + btstb #sign_bit,ETEMP_EX(%a6) |check sign for neg or pos + beqs p_inf |branch if pos sign + +m_inf: + fmovemx mns_inf,%fp0-%fp0 |load -inf + bsetb #neg_bit,FPSR_CC(%a6) |set neg bit in FPSR + bras set_fpsr +p_inf: + fmovemx pls_inf,%fp0-%fp0 |load +inf +set_fpsr: + orl #dzinf_mask,USER_FPSR(%a6) |set I,DZ,ADZ + rts +| +| dz enabled +| +dz_ena: + btstb #sign_bit,ETEMP_EX(%a6) |check sign for neg or pos + beqs dz_ena_end + bsetb #neg_bit,FPSR_CC(%a6) |set neg bit in FPSR +dz_ena_end: + orl #dzinf_mask,USER_FPSR(%a6) |set I,DZ,ADZ + st STORE_FLG(%a6) + rts +| +| OPERR exception +| +| if (operr trap disabled) +| set FPSR exception status operr bit, condition code +| nan bit; Store default NAN into fp0 +| frestore the frame into the machine (done by unimp_hd) +| +| else (operr trap enabled) +| set FPSR exception status operr bit, accrued operr bit +| set flag to disable sto_res from corrupting fp register +| frestore the frame into the machine (done by unimp_hd) +| +t_operr: + orl #opnan_mask,USER_FPSR(%a6) |set NaN, OPERR, AIOP + + btstb #operr_bit,FPCR_ENABLE(%a6) |test FPCR for operr enabled + bnes op_ena + + fmovemx nan,%fp0-%fp0 |load default nan + rts +op_ena: + st STORE_FLG(%a6) |do not corrupt destination + rts + +| +| t_unfl --- UNFL exception +| +| This entry point is used by all routines requiring unfl, inex2, +| aunfl, and ainex to be set on exit. +| +| On entry, a0 points to the exceptional operand. The final exceptional +| operand is built in FP_SCR1 and only the sign from the original operand +| is used. +| +t_unfl: + clrl FP_SCR1(%a6) |set exceptional operand to zero + clrl FP_SCR1+4(%a6) + clrl FP_SCR1+8(%a6) + tstb (%a0) |extract sign from caller's exop + bpls unfl_signok + bset #sign_bit,FP_SCR1(%a6) +unfl_signok: + leal FP_SCR1(%a6),%a0 + orl #unfinx_mask,USER_FPSR(%a6) +| ;set UNFL, INEX2, AUNFL, AINEX +unfl_con: + btstb #unfl_bit,FPCR_ENABLE(%a6) + beqs unfl_dis + +unfl_ena: + bfclr STAG(%a6){#5:#3} |clear wbtm66,wbtm1,wbtm0 + bsetb #wbtemp15_bit,WB_BYTE(%a6) |set wbtemp15 + bsetb #sticky_bit,STICKY(%a6) |set sticky bit + + bclrb #E1,E_BYTE(%a6) + +unfl_dis: + bfextu FPCR_MODE(%a6){#0:#2},%d0 |get round precision + + bclrb #sign_bit,LOCAL_EX(%a0) + sne LOCAL_SGN(%a0) |convert to internal ext format + + bsr unf_sub |returns IEEE result at a0 +| ;and sets FPSR_CC accordingly + + bfclr LOCAL_SGN(%a0){#0:#8} |convert back to IEEE ext format + beqs unfl_fin + + bsetb #sign_bit,LOCAL_EX(%a0) + bsetb #sign_bit,FP_SCR1(%a6) |set sign bit of exc operand + +unfl_fin: + fmovemx (%a0),%fp0-%fp0 |store result in fp0 + rts + + +| +| t_ovfl2 --- OVFL exception (without inex2 returned) +| +| This entry is used by scale to force catastrophic overflow. The +| ovfl, aovfl, and ainex bits are set, but not the inex2 bit. +| +t_ovfl2: + orl #ovfl_inx_mask,USER_FPSR(%a6) + movel ETEMP(%a6),FP_SCR1(%a6) + movel ETEMP_HI(%a6),FP_SCR1+4(%a6) + movel ETEMP_LO(%a6),FP_SCR1+8(%a6) +| +| Check for single or double round precision. If single, check if +| the lower 40 bits of ETEMP are zero; if not, set inex2. If double, +| check if the lower 21 bits are zero; if not, set inex2. +| + moveb FPCR_MODE(%a6),%d0 + andib #0xc0,%d0 + beq t_work |if extended, finish ovfl processing + cmpib #0x40,%d0 |test for single + bnes t_dbl +t_sgl: + tstb ETEMP_LO(%a6) + bnes t_setinx2 + movel ETEMP_HI(%a6),%d0 + andil #0xff,%d0 |look at only lower 8 bits + bnes t_setinx2 + bra t_work +t_dbl: + movel ETEMP_LO(%a6),%d0 + andil #0x7ff,%d0 |look at only lower 11 bits + beq t_work +t_setinx2: + orl #inex2_mask,USER_FPSR(%a6) + bras t_work +| +| t_ovfl --- OVFL exception +| +|** Note: the exc operand is returned in ETEMP. +| +t_ovfl: + orl #ovfinx_mask,USER_FPSR(%a6) +t_work: + btstb #ovfl_bit,FPCR_ENABLE(%a6) |test FPCR for ovfl enabled + beqs ovf_dis + +ovf_ena: + clrl FP_SCR1(%a6) |set exceptional operand + clrl FP_SCR1+4(%a6) + clrl FP_SCR1+8(%a6) + + bfclr STAG(%a6){#5:#3} |clear wbtm66,wbtm1,wbtm0 + bclrb #wbtemp15_bit,WB_BYTE(%a6) |clear wbtemp15 + bsetb #sticky_bit,STICKY(%a6) |set sticky bit + + bclrb #E1,E_BYTE(%a6) +| ;fall through to disabled case + +| For disabled overflow call 'ovf_r_k'. This routine loads the +| correct result based on the rounding precision, destination +| format, rounding mode and sign. +| +ovf_dis: + bsr ovf_r_k |returns unsigned ETEMP_EX +| ;and sets FPSR_CC accordingly. + bfclr ETEMP_SGN(%a6){#0:#8} |fix sign + beqs ovf_pos + bsetb #sign_bit,ETEMP_EX(%a6) + bsetb #sign_bit,FP_SCR1(%a6) |set exceptional operand sign +ovf_pos: + fmovemx ETEMP(%a6),%fp0-%fp0 |move the result to fp0 + rts + + +| +| INEX2 exception +| +| The inex2 and ainex bits are set. +| +t_inx2: + orl #inx2a_mask,USER_FPSR(%a6) |set INEX2, AINEX + rts + +| +| Force Inex2 +| +| This routine is called by the transcendental routines to force +| the inex2 exception bits set in the FPSR. If the underflow bit +| is set, but the underflow trap was not taken, the aunfl bit in +| the FPSR must be set. +| +t_frcinx: + orl #inx2a_mask,USER_FPSR(%a6) |set INEX2, AINEX + btstb #unfl_bit,FPSR_EXCEPT(%a6) |test for unfl bit set + beqs no_uacc1 |if clear, do not set aunfl + bsetb #aunfl_bit,FPSR_AEXCEPT(%a6) +no_uacc1: + rts + +| +| DST_NAN +| +| Determine if the destination nan is signalling or non-signalling, +| and set the FPSR bits accordingly. See the MC68040 User's Manual +| section 3.2.2.5 NOT-A-NUMBERS. +| +dst_nan: + btstb #sign_bit,FPTEMP_EX(%a6) |test sign of nan + beqs dst_pos |if clr, it was positive + bsetb #neg_bit,FPSR_CC(%a6) |set N bit +dst_pos: + btstb #signan_bit,FPTEMP_HI(%a6) |check if signalling + beqs dst_snan |branch if signalling + + fmovel %d1,%fpcr |restore user's rmode/prec + fmovex FPTEMP(%a6),%fp0 |return the non-signalling nan +| +| Check the source nan. If it is signalling, snan will be reported. +| + moveb STAG(%a6),%d0 + andib #0xe0,%d0 + cmpib #0x60,%d0 + bnes no_snan + btstb #signan_bit,ETEMP_HI(%a6) |check if signalling + bnes no_snan + orl #snaniop_mask,USER_FPSR(%a6) |set NAN, SNAN, AIOP +no_snan: + rts + +dst_snan: + btstb #snan_bit,FPCR_ENABLE(%a6) |check if trap enabled + beqs dst_dis |branch if disabled + + orb #nan_tag,DTAG(%a6) |set up dtag for nan + st STORE_FLG(%a6) |do not store a result + orl #snaniop_mask,USER_FPSR(%a6) |set NAN, SNAN, AIOP + rts + +dst_dis: + bsetb #signan_bit,FPTEMP_HI(%a6) |set SNAN bit in sop + fmovel %d1,%fpcr |restore user's rmode/prec + fmovex FPTEMP(%a6),%fp0 |load non-sign. nan + orl #snaniop_mask,USER_FPSR(%a6) |set NAN, SNAN, AIOP + rts + +| +| SRC_NAN +| +| Determine if the source nan is signalling or non-signalling, +| and set the FPSR bits accordingly. See the MC68040 User's Manual +| section 3.2.2.5 NOT-A-NUMBERS. +| +src_nan: + btstb #sign_bit,ETEMP_EX(%a6) |test sign of nan + beqs src_pos |if clr, it was positive + bsetb #neg_bit,FPSR_CC(%a6) |set N bit +src_pos: + btstb #signan_bit,ETEMP_HI(%a6) |check if signalling + beqs src_snan |branch if signalling + fmovel %d1,%fpcr |restore user's rmode/prec + fmovex ETEMP(%a6),%fp0 |return the non-signalling nan + rts + +src_snan: + btstb #snan_bit,FPCR_ENABLE(%a6) |check if trap enabled + beqs src_dis |branch if disabled + bsetb #signan_bit,ETEMP_HI(%a6) |set SNAN bit in sop + orb #norm_tag,DTAG(%a6) |set up dtag for norm + orb #nan_tag,STAG(%a6) |set up stag for nan + st STORE_FLG(%a6) |do not store a result + orl #snaniop_mask,USER_FPSR(%a6) |set NAN, SNAN, AIOP + rts + +src_dis: + bsetb #signan_bit,ETEMP_HI(%a6) |set SNAN bit in sop + fmovel %d1,%fpcr |restore user's rmode/prec + fmovex ETEMP(%a6),%fp0 |load non-sign. nan + orl #snaniop_mask,USER_FPSR(%a6) |set NAN, SNAN, AIOP + rts + +| +| For all functions that have a denormalized input and that f(x)=x, +| this is the entry point +| +t_extdnrm: + orl #unfinx_mask,USER_FPSR(%a6) +| ;set UNFL, INEX2, AUNFL, AINEX + bras xdnrm_con +| +| Entry point for scale with extended denorm. The function does +| not set inex2, aunfl, or ainex. +| +t_resdnrm: + orl #unfl_mask,USER_FPSR(%a6) + +xdnrm_con: + btstb #unfl_bit,FPCR_ENABLE(%a6) + beqs xdnrm_dis + +| +| If exceptions are enabled, the additional task of setting up WBTEMP +| is needed so that when the underflow exception handler is entered, +| the user perceives no difference between what the 040 provides vs. +| what the FPSP provides. +| +xdnrm_ena: + movel %a0,-(%a7) + + movel LOCAL_EX(%a0),FP_SCR1(%a6) + movel LOCAL_HI(%a0),FP_SCR1+4(%a6) + movel LOCAL_LO(%a0),FP_SCR1+8(%a6) + + lea FP_SCR1(%a6),%a0 + + bclrb #sign_bit,LOCAL_EX(%a0) + sne LOCAL_SGN(%a0) |convert to internal ext format + tstw LOCAL_EX(%a0) |check if input is denorm + beqs xdnrm_dn |if so, skip nrm_set + bsr nrm_set |normalize the result (exponent +| ;will be negative +xdnrm_dn: + bclrb #sign_bit,LOCAL_EX(%a0) |take off false sign + bfclr LOCAL_SGN(%a0){#0:#8} |change back to IEEE ext format + beqs xdep + bsetb #sign_bit,LOCAL_EX(%a0) +xdep: + bfclr STAG(%a6){#5:#3} |clear wbtm66,wbtm1,wbtm0 + bsetb #wbtemp15_bit,WB_BYTE(%a6) |set wbtemp15 + bclrb #sticky_bit,STICKY(%a6) |clear sticky bit + bclrb #E1,E_BYTE(%a6) + movel (%a7)+,%a0 +xdnrm_dis: + bfextu FPCR_MODE(%a6){#0:#2},%d0 |get round precision + bnes not_ext |if not round extended, store +| ;IEEE defaults +is_ext: + btstb #sign_bit,LOCAL_EX(%a0) + beqs xdnrm_store + + bsetb #neg_bit,FPSR_CC(%a6) |set N bit in FPSR_CC + + bras xdnrm_store + +not_ext: + bclrb #sign_bit,LOCAL_EX(%a0) + sne LOCAL_SGN(%a0) |convert to internal ext format + bsr unf_sub |returns IEEE result pointed by +| ;a0; sets FPSR_CC accordingly + bfclr LOCAL_SGN(%a0){#0:#8} |convert back to IEEE ext format + beqs xdnrm_store + bsetb #sign_bit,LOCAL_EX(%a0) +xdnrm_store: + fmovemx (%a0),%fp0-%fp0 |store result in fp0 + rts + +| +| This subroutine is used for dyadic operations that use an extended +| denorm within the kernel. The approach used is to capture the frame, +| fix/restore. +| + .global t_avoid_unsupp +t_avoid_unsupp: + link %a2,#-LOCAL_SIZE |so that a2 fpsp.h negative +| ;offsets may be used + fsave -(%a7) + tstb 1(%a7) |check if idle, exit if so + beq idle_end + btstb #E1,E_BYTE(%a2) |check for an E1 exception if +| ;enabled, there is an unsupp + beq end_avun |else, exit + btstb #7,DTAG(%a2) |check for denorm destination + beqs src_den |else, must be a source denorm +| +| handle destination denorm +| + lea FPTEMP(%a2),%a0 + btstb #sign_bit,LOCAL_EX(%a0) + sne LOCAL_SGN(%a0) |convert to internal ext format + bclrb #7,DTAG(%a2) |set DTAG to norm + bsr nrm_set |normalize result, exponent +| ;will become negative + bclrb #sign_bit,LOCAL_EX(%a0) |get rid of fake sign + bfclr LOCAL_SGN(%a0){#0:#8} |convert back to IEEE ext format + beqs ck_src_den |check if source is also denorm + bsetb #sign_bit,LOCAL_EX(%a0) +ck_src_den: + btstb #7,STAG(%a2) + beqs end_avun +src_den: + lea ETEMP(%a2),%a0 + btstb #sign_bit,LOCAL_EX(%a0) + sne LOCAL_SGN(%a0) |convert to internal ext format + bclrb #7,STAG(%a2) |set STAG to norm + bsr nrm_set |normalize result, exponent +| ;will become negative + bclrb #sign_bit,LOCAL_EX(%a0) |get rid of fake sign + bfclr LOCAL_SGN(%a0){#0:#8} |convert back to IEEE ext format + beqs den_com + bsetb #sign_bit,LOCAL_EX(%a0) +den_com: + moveb #0xfe,CU_SAVEPC(%a2) |set continue frame + clrw NMNEXC(%a2) |clear NMNEXC + bclrb #E1,E_BYTE(%a2) +| fmove.l %FPSR,FPSR_SHADOW(%a2) +| bset.b #SFLAG,E_BYTE(%a2) +| bset.b #XFLAG,T_BYTE(%a2) +end_avun: + frestore (%a7)+ + unlk %a2 + rts +idle_end: + addl #4,%a7 + unlk %a2 + rts + |end diff --git a/arch/m68k/fpsp040/res_func.S b/arch/m68k/fpsp040/res_func.S new file mode 100644 index 000000000..d9cdf4383 --- /dev/null +++ b/arch/m68k/fpsp040/res_func.S @@ -0,0 +1,2039 @@ +| +| res_func.sa 3.9 7/29/91 +| +| Normalizes denormalized numbers if necessary and updates the +| stack frame. The function is then restored back into the +| machine and the 040 completes the operation. This routine +| is only used by the unsupported data type/format handler. +| (Exception vector 55). +| +| For packed move out (fmove.p fpm,) the operation is +| completed here; data is packed and moved to user memory. +| The stack is restored to the 040 only in the case of a +| reportable exception in the conversion. +| +| +| Copyright (C) Motorola, Inc. 1990 +| All Rights Reserved +| +| For details on the license for this file, please see the +| file, README, in this same directory. + +RES_FUNC: |idnt 2,1 | Motorola 040 Floating Point Software Package + + |section 8 + +#include "fpsp.h" + +sp_bnds: .short 0x3f81,0x407e + .short 0x3f6a,0x0000 +dp_bnds: .short 0x3c01,0x43fe + .short 0x3bcd,0x0000 + + |xref mem_write + |xref bindec + |xref get_fline + |xref round + |xref denorm + |xref dest_ext + |xref dest_dbl + |xref dest_sgl + |xref unf_sub + |xref nrm_set + |xref dnrm_lp + |xref ovf_res + |xref reg_dest + |xref t_ovfl + |xref t_unfl + + .global res_func + .global p_move + +res_func: + clrb DNRM_FLG(%a6) + clrb RES_FLG(%a6) + clrb CU_ONLY(%a6) + tstb DY_MO_FLG(%a6) + beqs monadic +dyadic: + btstb #7,DTAG(%a6) |if dop = norm=000, zero=001, +| ;inf=010 or nan=011 + beqs monadic |then branch +| ;else denorm +| HANDLE DESTINATION DENORM HERE +| ;set dtag to norm +| ;write the tag & fpte15 to the fstack + leal FPTEMP(%a6),%a0 + + bclrb #sign_bit,LOCAL_EX(%a0) + sne LOCAL_SGN(%a0) + + bsr nrm_set |normalize number (exp will go negative) + bclrb #sign_bit,LOCAL_EX(%a0) |get rid of false sign + bfclr LOCAL_SGN(%a0){#0:#8} |change back to IEEE ext format + beqs dpos + bsetb #sign_bit,LOCAL_EX(%a0) +dpos: + bfclr DTAG(%a6){#0:#4} |set tag to normalized, FPTE15 = 0 + bsetb #4,DTAG(%a6) |set FPTE15 + orb #0x0f,DNRM_FLG(%a6) +monadic: + leal ETEMP(%a6),%a0 + btstb #direction_bit,CMDREG1B(%a6) |check direction + bne opclass3 |it is a mv out +| +| At this point, only opclass 0 and 2 possible +| + btstb #7,STAG(%a6) |if sop = norm=000, zero=001, +| ;inf=010 or nan=011 + bne mon_dnrm |else denorm + tstb DY_MO_FLG(%a6) |all cases of dyadic instructions would + bne normal |require normalization of denorm + +| At this point: +| monadic instructions: fabs = $18 fneg = $1a ftst = $3a +| fmove = $00 fsmove = $40 fdmove = $44 +| fsqrt = $05* fssqrt = $41 fdsqrt = $45 +| (*fsqrt reencoded to $05) +| + movew CMDREG1B(%a6),%d0 |get command register + andil #0x7f,%d0 |strip to only command word +| +| At this point, fabs, fneg, fsmove, fdmove, ftst, fsqrt, fssqrt, and +| fdsqrt are possible. +| For cases fabs, fneg, fsmove, and fdmove goto spos (do not normalize) +| For cases fsqrt, fssqrt, and fdsqrt goto nrm_src (do normalize) +| + btstl #0,%d0 + bne normal |weed out fsqrt instructions +| +| cu_norm handles fmove in instructions with normalized inputs. +| The routine round is used to correctly round the input for the +| destination precision and mode. +| +cu_norm: + st CU_ONLY(%a6) |set cu-only inst flag + movew CMDREG1B(%a6),%d0 + andib #0x3b,%d0 |isolate bits to select inst + tstb %d0 + beql cu_nmove |if zero, it is an fmove + cmpib #0x18,%d0 + beql cu_nabs |if $18, it is fabs + cmpib #0x1a,%d0 + beql cu_nneg |if $1a, it is fneg +| +| Inst is ftst. Check the source operand and set the cc's accordingly. +| No write is done, so simply rts. +| +cu_ntst: + movew LOCAL_EX(%a0),%d0 + bclrl #15,%d0 + sne LOCAL_SGN(%a0) + beqs cu_ntpo + orl #neg_mask,USER_FPSR(%a6) |set N +cu_ntpo: + cmpiw #0x7fff,%d0 |test for inf/nan + bnes cu_ntcz + tstl LOCAL_HI(%a0) + bnes cu_ntn + tstl LOCAL_LO(%a0) + bnes cu_ntn + orl #inf_mask,USER_FPSR(%a6) + rts +cu_ntn: + orl #nan_mask,USER_FPSR(%a6) + movel ETEMP_EX(%a6),FPTEMP_EX(%a6) |set up fptemp sign for +| ;snan handler + + rts +cu_ntcz: + tstl LOCAL_HI(%a0) + bnel cu_ntsx + tstl LOCAL_LO(%a0) + bnel cu_ntsx + orl #z_mask,USER_FPSR(%a6) +cu_ntsx: + rts +| +| Inst is fabs. Execute the absolute value function on the input. +| Branch to the fmove code. If the operand is NaN, do nothing. +| +cu_nabs: + moveb STAG(%a6),%d0 + btstl #5,%d0 |test for NaN or zero + bne wr_etemp |if either, simply write it + bclrb #7,LOCAL_EX(%a0) |do abs + bras cu_nmove |fmove code will finish +| +| Inst is fneg. Execute the negate value function on the input. +| Fall though to the fmove code. If the operand is NaN, do nothing. +| +cu_nneg: + moveb STAG(%a6),%d0 + btstl #5,%d0 |test for NaN or zero + bne wr_etemp |if either, simply write it + bchgb #7,LOCAL_EX(%a0) |do neg +| +| Inst is fmove. This code also handles all result writes. +| If bit 2 is set, round is forced to double. If it is clear, +| and bit 6 is set, round is forced to single. If both are clear, +| the round precision is found in the fpcr. If the rounding precision +| is double or single, round the result before the write. +| +cu_nmove: + moveb STAG(%a6),%d0 + andib #0xe0,%d0 |isolate stag bits + bne wr_etemp |if not norm, simply write it + btstb #2,CMDREG1B+1(%a6) |check for rd + bne cu_nmrd + btstb #6,CMDREG1B+1(%a6) |check for rs + bne cu_nmrs +| +| The move or operation is not with forced precision. Test for +| nan or inf as the input; if so, simply write it to FPn. Use the +| FPCR_MODE byte to get rounding on norms and zeros. +| +cu_nmnr: + bfextu FPCR_MODE(%a6){#0:#2},%d0 + tstb %d0 |check for extended + beq cu_wrexn |if so, just write result + cmpib #1,%d0 |check for single + beq cu_nmrs |fall through to double +| +| The move is fdmove or round precision is double. +| +cu_nmrd: + movel #2,%d0 |set up the size for denorm + movew LOCAL_EX(%a0),%d1 |compare exponent to double threshold + andw #0x7fff,%d1 + cmpw #0x3c01,%d1 + bls cu_nunfl + bfextu FPCR_MODE(%a6){#2:#2},%d1 |get rmode + orl #0x00020000,%d1 |or in rprec (double) + clrl %d0 |clear g,r,s for round + bclrb #sign_bit,LOCAL_EX(%a0) |convert to internal format + sne LOCAL_SGN(%a0) + bsrl round + bfclr LOCAL_SGN(%a0){#0:#8} + beqs cu_nmrdc + bsetb #sign_bit,LOCAL_EX(%a0) +cu_nmrdc: + movew LOCAL_EX(%a0),%d1 |check for overflow + andw #0x7fff,%d1 + cmpw #0x43ff,%d1 + bge cu_novfl |take care of overflow case + bra cu_wrexn +| +| The move is fsmove or round precision is single. +| +cu_nmrs: + movel #1,%d0 + movew LOCAL_EX(%a0),%d1 + andw #0x7fff,%d1 + cmpw #0x3f81,%d1 + bls cu_nunfl + bfextu FPCR_MODE(%a6){#2:#2},%d1 + orl #0x00010000,%d1 + clrl %d0 + bclrb #sign_bit,LOCAL_EX(%a0) + sne LOCAL_SGN(%a0) + bsrl round + bfclr LOCAL_SGN(%a0){#0:#8} + beqs cu_nmrsc + bsetb #sign_bit,LOCAL_EX(%a0) +cu_nmrsc: + movew LOCAL_EX(%a0),%d1 + andw #0x7FFF,%d1 + cmpw #0x407f,%d1 + blt cu_wrexn +| +| The operand is above precision boundaries. Use t_ovfl to +| generate the correct value. +| +cu_novfl: + bsr t_ovfl + bra cu_wrexn +| +| The operand is below precision boundaries. Use denorm to +| generate the correct value. +| +cu_nunfl: + bclrb #sign_bit,LOCAL_EX(%a0) + sne LOCAL_SGN(%a0) + bsr denorm + bfclr LOCAL_SGN(%a0){#0:#8} |change back to IEEE ext format + beqs cu_nucont + bsetb #sign_bit,LOCAL_EX(%a0) +cu_nucont: + bfextu FPCR_MODE(%a6){#2:#2},%d1 + btstb #2,CMDREG1B+1(%a6) |check for rd + bne inst_d + btstb #6,CMDREG1B+1(%a6) |check for rs + bne inst_s + swap %d1 + moveb FPCR_MODE(%a6),%d1 + lsrb #6,%d1 + swap %d1 + bra inst_sd +inst_d: + orl #0x00020000,%d1 + bra inst_sd +inst_s: + orl #0x00010000,%d1 +inst_sd: + bclrb #sign_bit,LOCAL_EX(%a0) + sne LOCAL_SGN(%a0) + bsrl round + bfclr LOCAL_SGN(%a0){#0:#8} + beqs cu_nuflp + bsetb #sign_bit,LOCAL_EX(%a0) +cu_nuflp: + btstb #inex2_bit,FPSR_EXCEPT(%a6) + beqs cu_nuninx + orl #aunfl_mask,USER_FPSR(%a6) |if the round was inex, set AUNFL +cu_nuninx: + tstl LOCAL_HI(%a0) |test for zero + bnes cu_nunzro + tstl LOCAL_LO(%a0) + bnes cu_nunzro +| +| The mantissa is zero from the denorm loop. Check sign and rmode +| to see if rounding should have occurred which would leave the lsb. +| + movel USER_FPCR(%a6),%d0 + andil #0x30,%d0 |isolate rmode + cmpil #0x20,%d0 + blts cu_nzro + bnes cu_nrp +cu_nrm: + tstw LOCAL_EX(%a0) |if positive, set lsb + bges cu_nzro + btstb #7,FPCR_MODE(%a6) |check for double + beqs cu_nincs + bras cu_nincd +cu_nrp: + tstw LOCAL_EX(%a0) |if positive, set lsb + blts cu_nzro + btstb #7,FPCR_MODE(%a6) |check for double + beqs cu_nincs +cu_nincd: + orl #0x800,LOCAL_LO(%a0) |inc for double + bra cu_nunzro +cu_nincs: + orl #0x100,LOCAL_HI(%a0) |inc for single + bra cu_nunzro +cu_nzro: + orl #z_mask,USER_FPSR(%a6) + moveb STAG(%a6),%d0 + andib #0xe0,%d0 + cmpib #0x40,%d0 |check if input was tagged zero + beqs cu_numv +cu_nunzro: + orl #unfl_mask,USER_FPSR(%a6) |set unfl +cu_numv: + movel (%a0),ETEMP(%a6) + movel 4(%a0),ETEMP_HI(%a6) + movel 8(%a0),ETEMP_LO(%a6) +| +| Write the result to memory, setting the fpsr cc bits. NaN and Inf +| bypass cu_wrexn. +| +cu_wrexn: + tstw LOCAL_EX(%a0) |test for zero + beqs cu_wrzero + cmpw #0x8000,LOCAL_EX(%a0) |test for zero + bnes cu_wreon +cu_wrzero: + orl #z_mask,USER_FPSR(%a6) |set Z bit +cu_wreon: + tstw LOCAL_EX(%a0) + bpl wr_etemp + orl #neg_mask,USER_FPSR(%a6) + bra wr_etemp + +| +| HANDLE SOURCE DENORM HERE +| +| ;clear denorm stag to norm +| ;write the new tag & ete15 to the fstack +mon_dnrm: +| +| At this point, check for the cases in which normalizing the +| denorm produces incorrect results. +| + tstb DY_MO_FLG(%a6) |all cases of dyadic instructions would + bnes nrm_src |require normalization of denorm + +| At this point: +| monadic instructions: fabs = $18 fneg = $1a ftst = $3a +| fmove = $00 fsmove = $40 fdmove = $44 +| fsqrt = $05* fssqrt = $41 fdsqrt = $45 +| (*fsqrt reencoded to $05) +| + movew CMDREG1B(%a6),%d0 |get command register + andil #0x7f,%d0 |strip to only command word +| +| At this point, fabs, fneg, fsmove, fdmove, ftst, fsqrt, fssqrt, and +| fdsqrt are possible. +| For cases fabs, fneg, fsmove, and fdmove goto spos (do not normalize) +| For cases fsqrt, fssqrt, and fdsqrt goto nrm_src (do normalize) +| + btstl #0,%d0 + bnes nrm_src |weed out fsqrt instructions + st CU_ONLY(%a6) |set cu-only inst flag + bra cu_dnrm |fmove, fabs, fneg, ftst +| ;cases go to cu_dnrm +nrm_src: + bclrb #sign_bit,LOCAL_EX(%a0) + sne LOCAL_SGN(%a0) + bsr nrm_set |normalize number (exponent will go +| ; negative) + bclrb #sign_bit,LOCAL_EX(%a0) |get rid of false sign + + bfclr LOCAL_SGN(%a0){#0:#8} |change back to IEEE ext format + beqs spos + bsetb #sign_bit,LOCAL_EX(%a0) +spos: + bfclr STAG(%a6){#0:#4} |set tag to normalized, FPTE15 = 0 + bsetb #4,STAG(%a6) |set ETE15 + orb #0xf0,DNRM_FLG(%a6) +normal: + tstb DNRM_FLG(%a6) |check if any of the ops were denorms + bne ck_wrap |if so, check if it is a potential +| ;wrap-around case +fix_stk: + moveb #0xfe,CU_SAVEPC(%a6) + bclrb #E1,E_BYTE(%a6) + + clrw NMNEXC(%a6) + + st RES_FLG(%a6) |indicate that a restore is needed + rts + +| +| cu_dnrm handles all cu-only instructions (fmove, fabs, fneg, and +| ftst) completely in software without an frestore to the 040. +| +cu_dnrm: + st CU_ONLY(%a6) + movew CMDREG1B(%a6),%d0 + andib #0x3b,%d0 |isolate bits to select inst + tstb %d0 + beql cu_dmove |if zero, it is an fmove + cmpib #0x18,%d0 + beql cu_dabs |if $18, it is fabs + cmpib #0x1a,%d0 + beql cu_dneg |if $1a, it is fneg +| +| Inst is ftst. Check the source operand and set the cc's accordingly. +| No write is done, so simply rts. +| +cu_dtst: + movew LOCAL_EX(%a0),%d0 + bclrl #15,%d0 + sne LOCAL_SGN(%a0) + beqs cu_dtpo + orl #neg_mask,USER_FPSR(%a6) |set N +cu_dtpo: + cmpiw #0x7fff,%d0 |test for inf/nan + bnes cu_dtcz + tstl LOCAL_HI(%a0) + bnes cu_dtn + tstl LOCAL_LO(%a0) + bnes cu_dtn + orl #inf_mask,USER_FPSR(%a6) + rts +cu_dtn: + orl #nan_mask,USER_FPSR(%a6) + movel ETEMP_EX(%a6),FPTEMP_EX(%a6) |set up fptemp sign for +| ;snan handler + rts +cu_dtcz: + tstl LOCAL_HI(%a0) + bnel cu_dtsx + tstl LOCAL_LO(%a0) + bnel cu_dtsx + orl #z_mask,USER_FPSR(%a6) +cu_dtsx: + rts +| +| Inst is fabs. Execute the absolute value function on the input. +| Branch to the fmove code. +| +cu_dabs: + bclrb #7,LOCAL_EX(%a0) |do abs + bras cu_dmove |fmove code will finish +| +| Inst is fneg. Execute the negate value function on the input. +| Fall though to the fmove code. +| +cu_dneg: + bchgb #7,LOCAL_EX(%a0) |do neg +| +| Inst is fmove. This code also handles all result writes. +| If bit 2 is set, round is forced to double. If it is clear, +| and bit 6 is set, round is forced to single. If both are clear, +| the round precision is found in the fpcr. If the rounding precision +| is double or single, the result is zero, and the mode is checked +| to determine if the lsb of the result should be set. +| +cu_dmove: + btstb #2,CMDREG1B+1(%a6) |check for rd + bne cu_dmrd + btstb #6,CMDREG1B+1(%a6) |check for rs + bne cu_dmrs +| +| The move or operation is not with forced precision. Use the +| FPCR_MODE byte to get rounding. +| +cu_dmnr: + bfextu FPCR_MODE(%a6){#0:#2},%d0 + tstb %d0 |check for extended + beq cu_wrexd |if so, just write result + cmpib #1,%d0 |check for single + beq cu_dmrs |fall through to double +| +| The move is fdmove or round precision is double. Result is zero. +| Check rmode for rp or rm and set lsb accordingly. +| +cu_dmrd: + bfextu FPCR_MODE(%a6){#2:#2},%d1 |get rmode + tstw LOCAL_EX(%a0) |check sign + blts cu_dmdn + cmpib #3,%d1 |check for rp + bne cu_dpd |load double pos zero + bra cu_dpdr |load double pos zero w/lsb +cu_dmdn: + cmpib #2,%d1 |check for rm + bne cu_dnd |load double neg zero + bra cu_dndr |load double neg zero w/lsb +| +| The move is fsmove or round precision is single. Result is zero. +| Check for rp or rm and set lsb accordingly. +| +cu_dmrs: + bfextu FPCR_MODE(%a6){#2:#2},%d1 |get rmode + tstw LOCAL_EX(%a0) |check sign + blts cu_dmsn + cmpib #3,%d1 |check for rp + bne cu_spd |load single pos zero + bra cu_spdr |load single pos zero w/lsb +cu_dmsn: + cmpib #2,%d1 |check for rm + bne cu_snd |load single neg zero + bra cu_sndr |load single neg zero w/lsb +| +| The precision is extended, so the result in etemp is correct. +| Simply set unfl (not inex2 or aunfl) and write the result to +| the correct fp register. +cu_wrexd: + orl #unfl_mask,USER_FPSR(%a6) + tstw LOCAL_EX(%a0) + beq wr_etemp + orl #neg_mask,USER_FPSR(%a6) + bra wr_etemp +| +| These routines write +/- zero in double format. The routines +| cu_dpdr and cu_dndr set the double lsb. +| +cu_dpd: + movel #0x3c010000,LOCAL_EX(%a0) |force pos double zero + clrl LOCAL_HI(%a0) + clrl LOCAL_LO(%a0) + orl #z_mask,USER_FPSR(%a6) + orl #unfinx_mask,USER_FPSR(%a6) + bra wr_etemp +cu_dpdr: + movel #0x3c010000,LOCAL_EX(%a0) |force pos double zero + clrl LOCAL_HI(%a0) + movel #0x800,LOCAL_LO(%a0) |with lsb set + orl #unfinx_mask,USER_FPSR(%a6) + bra wr_etemp +cu_dnd: + movel #0xbc010000,LOCAL_EX(%a0) |force pos double zero + clrl LOCAL_HI(%a0) + clrl LOCAL_LO(%a0) + orl #z_mask,USER_FPSR(%a6) + orl #neg_mask,USER_FPSR(%a6) + orl #unfinx_mask,USER_FPSR(%a6) + bra wr_etemp +cu_dndr: + movel #0xbc010000,LOCAL_EX(%a0) |force pos double zero + clrl LOCAL_HI(%a0) + movel #0x800,LOCAL_LO(%a0) |with lsb set + orl #neg_mask,USER_FPSR(%a6) + orl #unfinx_mask,USER_FPSR(%a6) + bra wr_etemp +| +| These routines write +/- zero in single format. The routines +| cu_dpdr and cu_dndr set the single lsb. +| +cu_spd: + movel #0x3f810000,LOCAL_EX(%a0) |force pos single zero + clrl LOCAL_HI(%a0) + clrl LOCAL_LO(%a0) + orl #z_mask,USER_FPSR(%a6) + orl #unfinx_mask,USER_FPSR(%a6) + bra wr_etemp +cu_spdr: + movel #0x3f810000,LOCAL_EX(%a0) |force pos single zero + movel #0x100,LOCAL_HI(%a0) |with lsb set + clrl LOCAL_LO(%a0) + orl #unfinx_mask,USER_FPSR(%a6) + bra wr_etemp +cu_snd: + movel #0xbf810000,LOCAL_EX(%a0) |force pos single zero + clrl LOCAL_HI(%a0) + clrl LOCAL_LO(%a0) + orl #z_mask,USER_FPSR(%a6) + orl #neg_mask,USER_FPSR(%a6) + orl #unfinx_mask,USER_FPSR(%a6) + bra wr_etemp +cu_sndr: + movel #0xbf810000,LOCAL_EX(%a0) |force pos single zero + movel #0x100,LOCAL_HI(%a0) |with lsb set + clrl LOCAL_LO(%a0) + orl #neg_mask,USER_FPSR(%a6) + orl #unfinx_mask,USER_FPSR(%a6) + bra wr_etemp + +| +| This code checks for 16-bit overflow conditions on dyadic +| operations which are not restorable into the floating-point +| unit and must be completed in software. Basically, this +| condition exists with a very large norm and a denorm. One +| of the operands must be denormalized to enter this code. +| +| Flags used: +| DY_MO_FLG contains 0 for monadic op, $ff for dyadic +| DNRM_FLG contains $00 for neither op denormalized +| $0f for the destination op denormalized +| $f0 for the source op denormalized +| $ff for both ops denormalized +| +| The wrap-around condition occurs for add, sub, div, and cmp +| when +| +| abs(dest_exp - src_exp) >= $8000 +| +| and for mul when +| +| (dest_exp + src_exp) < $0 +| +| we must process the operation here if this case is true. +| +| The rts following the frcfpn routine is the exit from res_func +| for this condition. The restore flag (RES_FLG) is left clear. +| No frestore is done unless an exception is to be reported. +| +| For fadd: +| if(sign_of(dest) != sign_of(src)) +| replace exponent of src with $3fff (keep sign) +| use fpu to perform dest+new_src (user's rmode and X) +| clr sticky +| else +| set sticky +| call round with user's precision and mode +| move result to fpn and wbtemp +| +| For fsub: +| if(sign_of(dest) == sign_of(src)) +| replace exponent of src with $3fff (keep sign) +| use fpu to perform dest+new_src (user's rmode and X) +| clr sticky +| else +| set sticky +| call round with user's precision and mode +| move result to fpn and wbtemp +| +| For fdiv/fsgldiv: +| if(both operands are denorm) +| restore_to_fpu; +| if(dest is norm) +| force_ovf; +| else(dest is denorm) +| force_unf: +| +| For fcmp: +| if(dest is norm) +| N = sign_of(dest); +| else(dest is denorm) +| N = sign_of(src); +| +| For fmul: +| if(both operands are denorm) +| force_unf; +| if((dest_exp + src_exp) < 0) +| force_unf: +| else +| restore_to_fpu; +| +| local equates: + .set addcode,0x22 + .set subcode,0x28 + .set mulcode,0x23 + .set divcode,0x20 + .set cmpcode,0x38 +ck_wrap: + | tstb DY_MO_FLG(%a6) ;check for fsqrt + beq fix_stk |if zero, it is fsqrt + movew CMDREG1B(%a6),%d0 + andiw #0x3b,%d0 |strip to command bits + cmpiw #addcode,%d0 + beq wrap_add + cmpiw #subcode,%d0 + beq wrap_sub + cmpiw #mulcode,%d0 + beq wrap_mul + cmpiw #cmpcode,%d0 + beq wrap_cmp +| +| Inst is fdiv. +| +wrap_div: + cmpb #0xff,DNRM_FLG(%a6) |if both ops denorm, + beq fix_stk |restore to fpu +| +| One of the ops is denormalized. Test for wrap condition +| and force the result. +| + cmpb #0x0f,DNRM_FLG(%a6) |check for dest denorm + bnes div_srcd +div_destd: + bsrl ckinf_ns + bne fix_stk + bfextu ETEMP_EX(%a6){#1:#15},%d0 |get src exp (always pos) + bfexts FPTEMP_EX(%a6){#1:#15},%d1 |get dest exp (always neg) + subl %d1,%d0 |subtract dest from src + cmpl #0x7fff,%d0 + blt fix_stk |if less, not wrap case + clrb WBTEMP_SGN(%a6) + movew ETEMP_EX(%a6),%d0 |find the sign of the result + movew FPTEMP_EX(%a6),%d1 + eorw %d1,%d0 + andiw #0x8000,%d0 + beq force_unf + st WBTEMP_SGN(%a6) + bra force_unf + +ckinf_ns: + moveb STAG(%a6),%d0 |check source tag for inf or nan + bra ck_in_com +ckinf_nd: + moveb DTAG(%a6),%d0 |check destination tag for inf or nan +ck_in_com: + andib #0x60,%d0 |isolate tag bits + cmpb #0x40,%d0 |is it inf? + beq nan_or_inf |not wrap case + cmpb #0x60,%d0 |is it nan? + beq nan_or_inf |yes, not wrap case? + cmpb #0x20,%d0 |is it a zero? + beq nan_or_inf |yes + clrl %d0 + rts |then ; it is either a zero of norm, +| ;check wrap case +nan_or_inf: + moveql #-1,%d0 + rts + + + +div_srcd: + bsrl ckinf_nd + bne fix_stk + bfextu FPTEMP_EX(%a6){#1:#15},%d0 |get dest exp (always pos) + bfexts ETEMP_EX(%a6){#1:#15},%d1 |get src exp (always neg) + subl %d1,%d0 |subtract src from dest + cmpl #0x8000,%d0 + blt fix_stk |if less, not wrap case + clrb WBTEMP_SGN(%a6) + movew ETEMP_EX(%a6),%d0 |find the sign of the result + movew FPTEMP_EX(%a6),%d1 + eorw %d1,%d0 + andiw #0x8000,%d0 + beqs force_ovf + st WBTEMP_SGN(%a6) +| +| This code handles the case of the instruction resulting in +| an overflow condition. +| +force_ovf: + bclrb #E1,E_BYTE(%a6) + orl #ovfl_inx_mask,USER_FPSR(%a6) + clrw NMNEXC(%a6) + leal WBTEMP(%a6),%a0 |point a0 to memory location + movew CMDREG1B(%a6),%d0 + btstl #6,%d0 |test for forced precision + beqs frcovf_fpcr + btstl #2,%d0 |check for double + bnes frcovf_dbl + movel #0x1,%d0 |inst is forced single + bras frcovf_rnd +frcovf_dbl: + movel #0x2,%d0 |inst is forced double + bras frcovf_rnd +frcovf_fpcr: + bfextu FPCR_MODE(%a6){#0:#2},%d0 |inst not forced - use fpcr prec +frcovf_rnd: + +| The 881/882 does not set inex2 for the following case, so the +| line is commented out to be compatible with 881/882 +| tst.b %d0 +| beq.b frcovf_x +| or.l #inex2_mask,USER_FPSR(%a6) ;if prec is s or d, set inex2 + +|frcovf_x: + bsrl ovf_res |get correct result based on +| ;round precision/mode. This +| ;sets FPSR_CC correctly +| ;returns in external format + bfclr WBTEMP_SGN(%a6){#0:#8} + beq frcfpn + bsetb #sign_bit,WBTEMP_EX(%a6) + bra frcfpn +| +| Inst is fadd. +| +wrap_add: + cmpb #0xff,DNRM_FLG(%a6) |if both ops denorm, + beq fix_stk |restore to fpu +| +| One of the ops is denormalized. Test for wrap condition +| and complete the instruction. +| + cmpb #0x0f,DNRM_FLG(%a6) |check for dest denorm + bnes add_srcd +add_destd: + bsrl ckinf_ns + bne fix_stk + bfextu ETEMP_EX(%a6){#1:#15},%d0 |get src exp (always pos) + bfexts FPTEMP_EX(%a6){#1:#15},%d1 |get dest exp (always neg) + subl %d1,%d0 |subtract dest from src + cmpl #0x8000,%d0 + blt fix_stk |if less, not wrap case + bra add_wrap +add_srcd: + bsrl ckinf_nd + bne fix_stk + bfextu FPTEMP_EX(%a6){#1:#15},%d0 |get dest exp (always pos) + bfexts ETEMP_EX(%a6){#1:#15},%d1 |get src exp (always neg) + subl %d1,%d0 |subtract src from dest + cmpl #0x8000,%d0 + blt fix_stk |if less, not wrap case +| +| Check the signs of the operands. If they are unlike, the fpu +| can be used to add the norm and 1.0 with the sign of the +| denorm and it will correctly generate the result in extended +| precision. We can then call round with no sticky and the result +| will be correct for the user's rounding mode and precision. If +| the signs are the same, we call round with the sticky bit set +| and the result will be correct for the user's rounding mode and +| precision. +| +add_wrap: + movew ETEMP_EX(%a6),%d0 + movew FPTEMP_EX(%a6),%d1 + eorw %d1,%d0 + andiw #0x8000,%d0 + beq add_same +| +| The signs are unlike. +| + cmpb #0x0f,DNRM_FLG(%a6) |is dest the denorm? + bnes add_u_srcd + movew FPTEMP_EX(%a6),%d0 + andiw #0x8000,%d0 + orw #0x3fff,%d0 |force the exponent to +/- 1 + movew %d0,FPTEMP_EX(%a6) |in the denorm + movel USER_FPCR(%a6),%d0 + andil #0x30,%d0 + fmovel %d0,%fpcr |set up users rmode and X + fmovex ETEMP(%a6),%fp0 + faddx FPTEMP(%a6),%fp0 + leal WBTEMP(%a6),%a0 |point a0 to wbtemp in frame + fmovel %fpsr,%d1 + orl %d1,USER_FPSR(%a6) |capture cc's and inex from fadd + fmovex %fp0,WBTEMP(%a6) |write result to memory + lsrl #4,%d0 |put rmode in lower 2 bits + movel USER_FPCR(%a6),%d1 + andil #0xc0,%d1 + lsrl #6,%d1 |put precision in upper word + swap %d1 + orl %d0,%d1 |set up for round call + clrl %d0 |force sticky to zero + bclrb #sign_bit,WBTEMP_EX(%a6) + sne WBTEMP_SGN(%a6) + bsrl round |round result to users rmode & prec + bfclr WBTEMP_SGN(%a6){#0:#8} |convert back to IEEE ext format + beq frcfpnr + bsetb #sign_bit,WBTEMP_EX(%a6) + bra frcfpnr +add_u_srcd: + movew ETEMP_EX(%a6),%d0 + andiw #0x8000,%d0 + orw #0x3fff,%d0 |force the exponent to +/- 1 + movew %d0,ETEMP_EX(%a6) |in the denorm + movel USER_FPCR(%a6),%d0 + andil #0x30,%d0 + fmovel %d0,%fpcr |set up users rmode and X + fmovex ETEMP(%a6),%fp0 + faddx FPTEMP(%a6),%fp0 + fmovel %fpsr,%d1 + orl %d1,USER_FPSR(%a6) |capture cc's and inex from fadd + leal WBTEMP(%a6),%a0 |point a0 to wbtemp in frame + fmovex %fp0,WBTEMP(%a6) |write result to memory + lsrl #4,%d0 |put rmode in lower 2 bits + movel USER_FPCR(%a6),%d1 + andil #0xc0,%d1 + lsrl #6,%d1 |put precision in upper word + swap %d1 + orl %d0,%d1 |set up for round call + clrl %d0 |force sticky to zero + bclrb #sign_bit,WBTEMP_EX(%a6) + sne WBTEMP_SGN(%a6) |use internal format for round + bsrl round |round result to users rmode & prec + bfclr WBTEMP_SGN(%a6){#0:#8} |convert back to IEEE ext format + beq frcfpnr + bsetb #sign_bit,WBTEMP_EX(%a6) + bra frcfpnr +| +| Signs are alike: +| +add_same: + cmpb #0x0f,DNRM_FLG(%a6) |is dest the denorm? + bnes add_s_srcd +add_s_destd: + leal ETEMP(%a6),%a0 + movel USER_FPCR(%a6),%d0 + andil #0x30,%d0 + lsrl #4,%d0 |put rmode in lower 2 bits + movel USER_FPCR(%a6),%d1 + andil #0xc0,%d1 + lsrl #6,%d1 |put precision in upper word + swap %d1 + orl %d0,%d1 |set up for round call + movel #0x20000000,%d0 |set sticky for round + bclrb #sign_bit,ETEMP_EX(%a6) + sne ETEMP_SGN(%a6) + bsrl round |round result to users rmode & prec + bfclr ETEMP_SGN(%a6){#0:#8} |convert back to IEEE ext format + beqs add_s_dclr + bsetb #sign_bit,ETEMP_EX(%a6) +add_s_dclr: + leal WBTEMP(%a6),%a0 + movel ETEMP(%a6),(%a0) |write result to wbtemp + movel ETEMP_HI(%a6),4(%a0) + movel ETEMP_LO(%a6),8(%a0) + tstw ETEMP_EX(%a6) + bgt add_ckovf + orl #neg_mask,USER_FPSR(%a6) + bra add_ckovf +add_s_srcd: + leal FPTEMP(%a6),%a0 + movel USER_FPCR(%a6),%d0 + andil #0x30,%d0 + lsrl #4,%d0 |put rmode in lower 2 bits + movel USER_FPCR(%a6),%d1 + andil #0xc0,%d1 + lsrl #6,%d1 |put precision in upper word + swap %d1 + orl %d0,%d1 |set up for round call + movel #0x20000000,%d0 |set sticky for round + bclrb #sign_bit,FPTEMP_EX(%a6) + sne FPTEMP_SGN(%a6) + bsrl round |round result to users rmode & prec + bfclr FPTEMP_SGN(%a6){#0:#8} |convert back to IEEE ext format + beqs add_s_sclr + bsetb #sign_bit,FPTEMP_EX(%a6) +add_s_sclr: + leal WBTEMP(%a6),%a0 + movel FPTEMP(%a6),(%a0) |write result to wbtemp + movel FPTEMP_HI(%a6),4(%a0) + movel FPTEMP_LO(%a6),8(%a0) + tstw FPTEMP_EX(%a6) + bgt add_ckovf + orl #neg_mask,USER_FPSR(%a6) +add_ckovf: + movew WBTEMP_EX(%a6),%d0 + andiw #0x7fff,%d0 + cmpiw #0x7fff,%d0 + bne frcfpnr +| +| The result has overflowed to $7fff exponent. Set I, ovfl, +| and aovfl, and clr the mantissa (incorrectly set by the +| round routine.) +| + orl #inf_mask+ovfl_inx_mask,USER_FPSR(%a6) + clrl 4(%a0) + bra frcfpnr +| +| Inst is fsub. +| +wrap_sub: + cmpb #0xff,DNRM_FLG(%a6) |if both ops denorm, + beq fix_stk |restore to fpu +| +| One of the ops is denormalized. Test for wrap condition +| and complete the instruction. +| + cmpb #0x0f,DNRM_FLG(%a6) |check for dest denorm + bnes sub_srcd +sub_destd: + bsrl ckinf_ns + bne fix_stk + bfextu ETEMP_EX(%a6){#1:#15},%d0 |get src exp (always pos) + bfexts FPTEMP_EX(%a6){#1:#15},%d1 |get dest exp (always neg) + subl %d1,%d0 |subtract src from dest + cmpl #0x8000,%d0 + blt fix_stk |if less, not wrap case + bra sub_wrap +sub_srcd: + bsrl ckinf_nd + bne fix_stk + bfextu FPTEMP_EX(%a6){#1:#15},%d0 |get dest exp (always pos) + bfexts ETEMP_EX(%a6){#1:#15},%d1 |get src exp (always neg) + subl %d1,%d0 |subtract dest from src + cmpl #0x8000,%d0 + blt fix_stk |if less, not wrap case +| +| Check the signs of the operands. If they are alike, the fpu +| can be used to subtract from the norm 1.0 with the sign of the +| denorm and it will correctly generate the result in extended +| precision. We can then call round with no sticky and the result +| will be correct for the user's rounding mode and precision. If +| the signs are unlike, we call round with the sticky bit set +| and the result will be correct for the user's rounding mode and +| precision. +| +sub_wrap: + movew ETEMP_EX(%a6),%d0 + movew FPTEMP_EX(%a6),%d1 + eorw %d1,%d0 + andiw #0x8000,%d0 + bne sub_diff +| +| The signs are alike. +| + cmpb #0x0f,DNRM_FLG(%a6) |is dest the denorm? + bnes sub_u_srcd + movew FPTEMP_EX(%a6),%d0 + andiw #0x8000,%d0 + orw #0x3fff,%d0 |force the exponent to +/- 1 + movew %d0,FPTEMP_EX(%a6) |in the denorm + movel USER_FPCR(%a6),%d0 + andil #0x30,%d0 + fmovel %d0,%fpcr |set up users rmode and X + fmovex FPTEMP(%a6),%fp0 + fsubx ETEMP(%a6),%fp0 + fmovel %fpsr,%d1 + orl %d1,USER_FPSR(%a6) |capture cc's and inex from fadd + leal WBTEMP(%a6),%a0 |point a0 to wbtemp in frame + fmovex %fp0,WBTEMP(%a6) |write result to memory + lsrl #4,%d0 |put rmode in lower 2 bits + movel USER_FPCR(%a6),%d1 + andil #0xc0,%d1 + lsrl #6,%d1 |put precision in upper word + swap %d1 + orl %d0,%d1 |set up for round call + clrl %d0 |force sticky to zero + bclrb #sign_bit,WBTEMP_EX(%a6) + sne WBTEMP_SGN(%a6) + bsrl round |round result to users rmode & prec + bfclr WBTEMP_SGN(%a6){#0:#8} |convert back to IEEE ext format + beq frcfpnr + bsetb #sign_bit,WBTEMP_EX(%a6) + bra frcfpnr +sub_u_srcd: + movew ETEMP_EX(%a6),%d0 + andiw #0x8000,%d0 + orw #0x3fff,%d0 |force the exponent to +/- 1 + movew %d0,ETEMP_EX(%a6) |in the denorm + movel USER_FPCR(%a6),%d0 + andil #0x30,%d0 + fmovel %d0,%fpcr |set up users rmode and X + fmovex FPTEMP(%a6),%fp0 + fsubx ETEMP(%a6),%fp0 + fmovel %fpsr,%d1 + orl %d1,USER_FPSR(%a6) |capture cc's and inex from fadd + leal WBTEMP(%a6),%a0 |point a0 to wbtemp in frame + fmovex %fp0,WBTEMP(%a6) |write result to memory + lsrl #4,%d0 |put rmode in lower 2 bits + movel USER_FPCR(%a6),%d1 + andil #0xc0,%d1 + lsrl #6,%d1 |put precision in upper word + swap %d1 + orl %d0,%d1 |set up for round call + clrl %d0 |force sticky to zero + bclrb #sign_bit,WBTEMP_EX(%a6) + sne WBTEMP_SGN(%a6) + bsrl round |round result to users rmode & prec + bfclr WBTEMP_SGN(%a6){#0:#8} |convert back to IEEE ext format + beq frcfpnr + bsetb #sign_bit,WBTEMP_EX(%a6) + bra frcfpnr +| +| Signs are unlike: +| +sub_diff: + cmpb #0x0f,DNRM_FLG(%a6) |is dest the denorm? + bnes sub_s_srcd +sub_s_destd: + leal ETEMP(%a6),%a0 + movel USER_FPCR(%a6),%d0 + andil #0x30,%d0 + lsrl #4,%d0 |put rmode in lower 2 bits + movel USER_FPCR(%a6),%d1 + andil #0xc0,%d1 + lsrl #6,%d1 |put precision in upper word + swap %d1 + orl %d0,%d1 |set up for round call + movel #0x20000000,%d0 |set sticky for round +| +| Since the dest is the denorm, the sign is the opposite of the +| norm sign. +| + eoriw #0x8000,ETEMP_EX(%a6) |flip sign on result + tstw ETEMP_EX(%a6) + bgts sub_s_dwr + orl #neg_mask,USER_FPSR(%a6) +sub_s_dwr: + bclrb #sign_bit,ETEMP_EX(%a6) + sne ETEMP_SGN(%a6) + bsrl round |round result to users rmode & prec + bfclr ETEMP_SGN(%a6){#0:#8} |convert back to IEEE ext format + beqs sub_s_dclr + bsetb #sign_bit,ETEMP_EX(%a6) +sub_s_dclr: + leal WBTEMP(%a6),%a0 + movel ETEMP(%a6),(%a0) |write result to wbtemp + movel ETEMP_HI(%a6),4(%a0) + movel ETEMP_LO(%a6),8(%a0) + bra sub_ckovf +sub_s_srcd: + leal FPTEMP(%a6),%a0 + movel USER_FPCR(%a6),%d0 + andil #0x30,%d0 + lsrl #4,%d0 |put rmode in lower 2 bits + movel USER_FPCR(%a6),%d1 + andil #0xc0,%d1 + lsrl #6,%d1 |put precision in upper word + swap %d1 + orl %d0,%d1 |set up for round call + movel #0x20000000,%d0 |set sticky for round + bclrb #sign_bit,FPTEMP_EX(%a6) + sne FPTEMP_SGN(%a6) + bsrl round |round result to users rmode & prec + bfclr FPTEMP_SGN(%a6){#0:#8} |convert back to IEEE ext format + beqs sub_s_sclr + bsetb #sign_bit,FPTEMP_EX(%a6) +sub_s_sclr: + leal WBTEMP(%a6),%a0 + movel FPTEMP(%a6),(%a0) |write result to wbtemp + movel FPTEMP_HI(%a6),4(%a0) + movel FPTEMP_LO(%a6),8(%a0) + tstw FPTEMP_EX(%a6) + bgt sub_ckovf + orl #neg_mask,USER_FPSR(%a6) +sub_ckovf: + movew WBTEMP_EX(%a6),%d0 + andiw #0x7fff,%d0 + cmpiw #0x7fff,%d0 + bne frcfpnr +| +| The result has overflowed to $7fff exponent. Set I, ovfl, +| and aovfl, and clr the mantissa (incorrectly set by the +| round routine.) +| + orl #inf_mask+ovfl_inx_mask,USER_FPSR(%a6) + clrl 4(%a0) + bra frcfpnr +| +| Inst is fcmp. +| +wrap_cmp: + cmpb #0xff,DNRM_FLG(%a6) |if both ops denorm, + beq fix_stk |restore to fpu +| +| One of the ops is denormalized. Test for wrap condition +| and complete the instruction. +| + cmpb #0x0f,DNRM_FLG(%a6) |check for dest denorm + bnes cmp_srcd +cmp_destd: + bsrl ckinf_ns + bne fix_stk + bfextu ETEMP_EX(%a6){#1:#15},%d0 |get src exp (always pos) + bfexts FPTEMP_EX(%a6){#1:#15},%d1 |get dest exp (always neg) + subl %d1,%d0 |subtract dest from src + cmpl #0x8000,%d0 + blt fix_stk |if less, not wrap case + tstw ETEMP_EX(%a6) |set N to ~sign_of(src) + bge cmp_setn + rts +cmp_srcd: + bsrl ckinf_nd + bne fix_stk + bfextu FPTEMP_EX(%a6){#1:#15},%d0 |get dest exp (always pos) + bfexts ETEMP_EX(%a6){#1:#15},%d1 |get src exp (always neg) + subl %d1,%d0 |subtract src from dest + cmpl #0x8000,%d0 + blt fix_stk |if less, not wrap case + tstw FPTEMP_EX(%a6) |set N to sign_of(dest) + blt cmp_setn + rts +cmp_setn: + orl #neg_mask,USER_FPSR(%a6) + rts + +| +| Inst is fmul. +| +wrap_mul: + cmpb #0xff,DNRM_FLG(%a6) |if both ops denorm, + beq force_unf |force an underflow (really!) +| +| One of the ops is denormalized. Test for wrap condition +| and complete the instruction. +| + cmpb #0x0f,DNRM_FLG(%a6) |check for dest denorm + bnes mul_srcd +mul_destd: + bsrl ckinf_ns + bne fix_stk + bfextu ETEMP_EX(%a6){#1:#15},%d0 |get src exp (always pos) + bfexts FPTEMP_EX(%a6){#1:#15},%d1 |get dest exp (always neg) + addl %d1,%d0 |subtract dest from src + bgt fix_stk + bra force_unf +mul_srcd: + bsrl ckinf_nd + bne fix_stk + bfextu FPTEMP_EX(%a6){#1:#15},%d0 |get dest exp (always pos) + bfexts ETEMP_EX(%a6){#1:#15},%d1 |get src exp (always neg) + addl %d1,%d0 |subtract src from dest + bgt fix_stk + +| +| This code handles the case of the instruction resulting in +| an underflow condition. +| +force_unf: + bclrb #E1,E_BYTE(%a6) + orl #unfinx_mask,USER_FPSR(%a6) + clrw NMNEXC(%a6) + clrb WBTEMP_SGN(%a6) + movew ETEMP_EX(%a6),%d0 |find the sign of the result + movew FPTEMP_EX(%a6),%d1 + eorw %d1,%d0 + andiw #0x8000,%d0 + beqs frcunfcont + st WBTEMP_SGN(%a6) +frcunfcont: + lea WBTEMP(%a6),%a0 |point a0 to memory location + movew CMDREG1B(%a6),%d0 + btstl #6,%d0 |test for forced precision + beqs frcunf_fpcr + btstl #2,%d0 |check for double + bnes frcunf_dbl + movel #0x1,%d0 |inst is forced single + bras frcunf_rnd +frcunf_dbl: + movel #0x2,%d0 |inst is forced double + bras frcunf_rnd +frcunf_fpcr: + bfextu FPCR_MODE(%a6){#0:#2},%d0 |inst not forced - use fpcr prec +frcunf_rnd: + bsrl unf_sub |get correct result based on +| ;round precision/mode. This +| ;sets FPSR_CC correctly + bfclr WBTEMP_SGN(%a6){#0:#8} |convert back to IEEE ext format + beqs frcfpn + bsetb #sign_bit,WBTEMP_EX(%a6) + bra frcfpn + +| +| Write the result to the user's fpn. All results must be HUGE to be +| written; otherwise the results would have overflowed or underflowed. +| If the rounding precision is single or double, the ovf_res routine +| is needed to correctly supply the max value. +| +frcfpnr: + movew CMDREG1B(%a6),%d0 + btstl #6,%d0 |test for forced precision + beqs frcfpn_fpcr + btstl #2,%d0 |check for double + bnes frcfpn_dbl + movel #0x1,%d0 |inst is forced single + bras frcfpn_rnd +frcfpn_dbl: + movel #0x2,%d0 |inst is forced double + bras frcfpn_rnd +frcfpn_fpcr: + bfextu FPCR_MODE(%a6){#0:#2},%d0 |inst not forced - use fpcr prec + tstb %d0 + beqs frcfpn |if extended, write what you got +frcfpn_rnd: + bclrb #sign_bit,WBTEMP_EX(%a6) + sne WBTEMP_SGN(%a6) + bsrl ovf_res |get correct result based on +| ;round precision/mode. This +| ;sets FPSR_CC correctly + bfclr WBTEMP_SGN(%a6){#0:#8} |convert back to IEEE ext format + beqs frcfpn_clr + bsetb #sign_bit,WBTEMP_EX(%a6) +frcfpn_clr: + orl #ovfinx_mask,USER_FPSR(%a6) +| +| Perform the write. +| +frcfpn: + bfextu CMDREG1B(%a6){#6:#3},%d0 |extract fp destination register + cmpib #3,%d0 + bles frc0123 |check if dest is fp0-fp3 + movel #7,%d1 + subl %d0,%d1 + clrl %d0 + bsetl %d1,%d0 + fmovemx WBTEMP(%a6),%d0 + rts +frc0123: + cmpib #0,%d0 + beqs frc0_dst + cmpib #1,%d0 + beqs frc1_dst + cmpib #2,%d0 + beqs frc2_dst +frc3_dst: + movel WBTEMP_EX(%a6),USER_FP3(%a6) + movel WBTEMP_HI(%a6),USER_FP3+4(%a6) + movel WBTEMP_LO(%a6),USER_FP3+8(%a6) + rts +frc2_dst: + movel WBTEMP_EX(%a6),USER_FP2(%a6) + movel WBTEMP_HI(%a6),USER_FP2+4(%a6) + movel WBTEMP_LO(%a6),USER_FP2+8(%a6) + rts +frc1_dst: + movel WBTEMP_EX(%a6),USER_FP1(%a6) + movel WBTEMP_HI(%a6),USER_FP1+4(%a6) + movel WBTEMP_LO(%a6),USER_FP1+8(%a6) + rts +frc0_dst: + movel WBTEMP_EX(%a6),USER_FP0(%a6) + movel WBTEMP_HI(%a6),USER_FP0+4(%a6) + movel WBTEMP_LO(%a6),USER_FP0+8(%a6) + rts + +| +| Write etemp to fpn. +| A check is made on enabled and signalled snan exceptions, +| and the destination is not overwritten if this condition exists. +| This code is designed to make fmoveins of unsupported data types +| faster. +| +wr_etemp: + btstb #snan_bit,FPSR_EXCEPT(%a6) |if snan is set, and + beqs fmoveinc |enabled, force restore + btstb #snan_bit,FPCR_ENABLE(%a6) |and don't overwrite + beqs fmoveinc |the dest + movel ETEMP_EX(%a6),FPTEMP_EX(%a6) |set up fptemp sign for +| ;snan handler + tstb ETEMP(%a6) |check for negative + blts snan_neg + rts +snan_neg: + orl #neg_bit,USER_FPSR(%a6) |snan is negative; set N + rts +fmoveinc: + clrw NMNEXC(%a6) + bclrb #E1,E_BYTE(%a6) + moveb STAG(%a6),%d0 |check if stag is inf + andib #0xe0,%d0 + cmpib #0x40,%d0 + bnes fminc_cnan + orl #inf_mask,USER_FPSR(%a6) |if inf, nothing yet has set I + tstw LOCAL_EX(%a0) |check sign + bges fminc_con + orl #neg_mask,USER_FPSR(%a6) + bra fminc_con +fminc_cnan: + cmpib #0x60,%d0 |check if stag is NaN + bnes fminc_czero + orl #nan_mask,USER_FPSR(%a6) |if nan, nothing yet has set NaN + movel ETEMP_EX(%a6),FPTEMP_EX(%a6) |set up fptemp sign for +| ;snan handler + tstw LOCAL_EX(%a0) |check sign + bges fminc_con + orl #neg_mask,USER_FPSR(%a6) + bra fminc_con +fminc_czero: + cmpib #0x20,%d0 |check if zero + bnes fminc_con + orl #z_mask,USER_FPSR(%a6) |if zero, set Z + tstw LOCAL_EX(%a0) |check sign + bges fminc_con + orl #neg_mask,USER_FPSR(%a6) +fminc_con: + bfextu CMDREG1B(%a6){#6:#3},%d0 |extract fp destination register + cmpib #3,%d0 + bles fp0123 |check if dest is fp0-fp3 + movel #7,%d1 + subl %d0,%d1 + clrl %d0 + bsetl %d1,%d0 + fmovemx ETEMP(%a6),%d0 + rts + +fp0123: + cmpib #0,%d0 + beqs fp0_dst + cmpib #1,%d0 + beqs fp1_dst + cmpib #2,%d0 + beqs fp2_dst +fp3_dst: + movel ETEMP_EX(%a6),USER_FP3(%a6) + movel ETEMP_HI(%a6),USER_FP3+4(%a6) + movel ETEMP_LO(%a6),USER_FP3+8(%a6) + rts +fp2_dst: + movel ETEMP_EX(%a6),USER_FP2(%a6) + movel ETEMP_HI(%a6),USER_FP2+4(%a6) + movel ETEMP_LO(%a6),USER_FP2+8(%a6) + rts +fp1_dst: + movel ETEMP_EX(%a6),USER_FP1(%a6) + movel ETEMP_HI(%a6),USER_FP1+4(%a6) + movel ETEMP_LO(%a6),USER_FP1+8(%a6) + rts +fp0_dst: + movel ETEMP_EX(%a6),USER_FP0(%a6) + movel ETEMP_HI(%a6),USER_FP0+4(%a6) + movel ETEMP_LO(%a6),USER_FP0+8(%a6) + rts + +opclass3: + st CU_ONLY(%a6) + movew CMDREG1B(%a6),%d0 |check if packed moveout + andiw #0x0c00,%d0 |isolate last 2 bits of size field + cmpiw #0x0c00,%d0 |if size is 011 or 111, it is packed + beq pack_out |else it is norm or denorm + bra mv_out + + +| +| MOVE OUT +| + +mv_tbl: + .long li + .long sgp + .long xp + .long mvout_end |should never be taken + .long wi + .long dp + .long bi + .long mvout_end |should never be taken +mv_out: + bfextu CMDREG1B(%a6){#3:#3},%d1 |put source specifier in d1 + leal mv_tbl,%a0 + movel %a0@(%d1:l:4),%a0 + jmp (%a0) + +| +| This exit is for move-out to memory. The aunfl bit is +| set if the result is inex and unfl is signalled. +| +mvout_end: + btstb #inex2_bit,FPSR_EXCEPT(%a6) + beqs no_aufl + btstb #unfl_bit,FPSR_EXCEPT(%a6) + beqs no_aufl + bsetb #aunfl_bit,FPSR_AEXCEPT(%a6) +no_aufl: + clrw NMNEXC(%a6) + bclrb #E1,E_BYTE(%a6) + fmovel #0,%FPSR |clear any cc bits from res_func +| +| Return ETEMP to extended format from internal extended format so +| that gen_except will have a correctly signed value for ovfl/unfl +| handlers. +| + bfclr ETEMP_SGN(%a6){#0:#8} + beqs mvout_con + bsetb #sign_bit,ETEMP_EX(%a6) +mvout_con: + rts +| +| This exit is for move-out to int register. The aunfl bit is +| not set in any case for this move. +| +mvouti_end: + clrw NMNEXC(%a6) + bclrb #E1,E_BYTE(%a6) + fmovel #0,%FPSR |clear any cc bits from res_func +| +| Return ETEMP to extended format from internal extended format so +| that gen_except will have a correctly signed value for ovfl/unfl +| handlers. +| + bfclr ETEMP_SGN(%a6){#0:#8} + beqs mvouti_con + bsetb #sign_bit,ETEMP_EX(%a6) +mvouti_con: + rts +| +| li is used to handle a long integer source specifier +| + +li: + moveql #4,%d0 |set byte count + + btstb #7,STAG(%a6) |check for extended denorm + bne int_dnrm |if so, branch + + fmovemx ETEMP(%a6),%fp0-%fp0 + fcmpd #0x41dfffffffc00000,%fp0 +| 41dfffffffc00000 in dbl prec = 401d0000fffffffe00000000 in ext prec + fbge lo_plrg + fcmpd #0xc1e0000000000000,%fp0 +| c1e0000000000000 in dbl prec = c01e00008000000000000000 in ext prec + fble lo_nlrg +| +| at this point, the answer is between the largest pos and neg values +| + movel USER_FPCR(%a6),%d1 |use user's rounding mode + andil #0x30,%d1 + fmovel %d1,%fpcr + fmovel %fp0,L_SCR1(%a6) |let the 040 perform conversion + fmovel %fpsr,%d1 + orl %d1,USER_FPSR(%a6) |capture inex2/ainex if set + bra int_wrt + + +lo_plrg: + movel #0x7fffffff,L_SCR1(%a6) |answer is largest positive int + fbeq int_wrt |exact answer + fcmpd #0x41dfffffffe00000,%fp0 +| 41dfffffffe00000 in dbl prec = 401d0000ffffffff00000000 in ext prec + fbge int_operr |set operr + bra int_inx |set inexact + +lo_nlrg: + movel #0x80000000,L_SCR1(%a6) + fbeq int_wrt |exact answer + fcmpd #0xc1e0000000100000,%fp0 +| c1e0000000100000 in dbl prec = c01e00008000000080000000 in ext prec + fblt int_operr |set operr + bra int_inx |set inexact + +| +| wi is used to handle a word integer source specifier +| + +wi: + moveql #2,%d0 |set byte count + + btstb #7,STAG(%a6) |check for extended denorm + bne int_dnrm |branch if so + + fmovemx ETEMP(%a6),%fp0-%fp0 + fcmps #0x46fffe00,%fp0 +| 46fffe00 in sgl prec = 400d0000fffe000000000000 in ext prec + fbge wo_plrg + fcmps #0xc7000000,%fp0 +| c7000000 in sgl prec = c00e00008000000000000000 in ext prec + fble wo_nlrg + +| +| at this point, the answer is between the largest pos and neg values +| + movel USER_FPCR(%a6),%d1 |use user's rounding mode + andil #0x30,%d1 + fmovel %d1,%fpcr + fmovew %fp0,L_SCR1(%a6) |let the 040 perform conversion + fmovel %fpsr,%d1 + orl %d1,USER_FPSR(%a6) |capture inex2/ainex if set + bra int_wrt + +wo_plrg: + movew #0x7fff,L_SCR1(%a6) |answer is largest positive int + fbeq int_wrt |exact answer + fcmps #0x46ffff00,%fp0 +| 46ffff00 in sgl prec = 400d0000ffff000000000000 in ext prec + fbge int_operr |set operr + bra int_inx |set inexact + +wo_nlrg: + movew #0x8000,L_SCR1(%a6) + fbeq int_wrt |exact answer + fcmps #0xc7000080,%fp0 +| c7000080 in sgl prec = c00e00008000800000000000 in ext prec + fblt int_operr |set operr + bra int_inx |set inexact + +| +| bi is used to handle a byte integer source specifier +| + +bi: + moveql #1,%d0 |set byte count + + btstb #7,STAG(%a6) |check for extended denorm + bne int_dnrm |branch if so + + fmovemx ETEMP(%a6),%fp0-%fp0 + fcmps #0x42fe0000,%fp0 +| 42fe0000 in sgl prec = 40050000fe00000000000000 in ext prec + fbge by_plrg + fcmps #0xc3000000,%fp0 +| c3000000 in sgl prec = c00600008000000000000000 in ext prec + fble by_nlrg + +| +| at this point, the answer is between the largest pos and neg values +| + movel USER_FPCR(%a6),%d1 |use user's rounding mode + andil #0x30,%d1 + fmovel %d1,%fpcr + fmoveb %fp0,L_SCR1(%a6) |let the 040 perform conversion + fmovel %fpsr,%d1 + orl %d1,USER_FPSR(%a6) |capture inex2/ainex if set + bra int_wrt + +by_plrg: + moveb #0x7f,L_SCR1(%a6) |answer is largest positive int + fbeq int_wrt |exact answer + fcmps #0x42ff0000,%fp0 +| 42ff0000 in sgl prec = 40050000ff00000000000000 in ext prec + fbge int_operr |set operr + bra int_inx |set inexact + +by_nlrg: + moveb #0x80,L_SCR1(%a6) + fbeq int_wrt |exact answer + fcmps #0xc3008000,%fp0 +| c3008000 in sgl prec = c00600008080000000000000 in ext prec + fblt int_operr |set operr + bra int_inx |set inexact + +| +| Common integer routines +| +| int_drnrm---account for possible nonzero result for round up with positive +| operand and round down for negative answer. In the first case (result = 1) +| byte-width (store in d0) of result must be honored. In the second case, +| -1 in L_SCR1(a6) will cover all contingencies (FMOVE.B/W/L out). + +int_dnrm: + movel #0,L_SCR1(%a6) | initialize result to 0 + bfextu FPCR_MODE(%a6){#2:#2},%d1 | d1 is the rounding mode + cmpb #2,%d1 + bmis int_inx | if RN or RZ, done + bnes int_rp | if RP, continue below + tstw ETEMP(%a6) | RM: store -1 in L_SCR1 if src is negative + bpls int_inx | otherwise result is 0 + movel #-1,L_SCR1(%a6) + bras int_inx +int_rp: + tstw ETEMP(%a6) | RP: store +1 of proper width in L_SCR1 if +| ; source is greater than 0 + bmis int_inx | otherwise, result is 0 + lea L_SCR1(%a6),%a1 | a1 is address of L_SCR1 + addal %d0,%a1 | offset by destination width -1 + subal #1,%a1 + bsetb #0,(%a1) | set low bit at a1 address +int_inx: + oril #inx2a_mask,USER_FPSR(%a6) + bras int_wrt +int_operr: + fmovemx %fp0-%fp0,FPTEMP(%a6) |FPTEMP must contain the extended +| ;precision source that needs to be +| ;converted to integer this is required +| ;if the operr exception is enabled. +| ;set operr/aiop (no inex2 on int ovfl) + + oril #opaop_mask,USER_FPSR(%a6) +| ;fall through to perform int_wrt +int_wrt: + movel EXC_EA(%a6),%a1 |load destination address + tstl %a1 |check to see if it is a dest register + beqs wrt_dn |write data register + lea L_SCR1(%a6),%a0 |point to supervisor source address + bsrl mem_write + bra mvouti_end + +wrt_dn: + movel %d0,-(%sp) |d0 currently contains the size to write + bsrl get_fline |get_fline returns Dn in d0 + andiw #0x7,%d0 |isolate register + movel (%sp)+,%d1 |get size + cmpil #4,%d1 |most frequent case + beqs sz_long + cmpil #2,%d1 + bnes sz_con + orl #8,%d0 |add 'word' size to register# + bras sz_con +sz_long: + orl #0x10,%d0 |add 'long' size to register# +sz_con: + movel %d0,%d1 |reg_dest expects size:reg in d1 + bsrl reg_dest |load proper data register + bra mvouti_end +xp: + lea ETEMP(%a6),%a0 + bclrb #sign_bit,LOCAL_EX(%a0) + sne LOCAL_SGN(%a0) + btstb #7,STAG(%a6) |check for extended denorm + bne xdnrm + clrl %d0 + bras do_fp |do normal case +sgp: + lea ETEMP(%a6),%a0 + bclrb #sign_bit,LOCAL_EX(%a0) + sne LOCAL_SGN(%a0) + btstb #7,STAG(%a6) |check for extended denorm + bne sp_catas |branch if so + movew LOCAL_EX(%a0),%d0 + lea sp_bnds,%a1 + cmpw (%a1),%d0 + blt sp_under + cmpw 2(%a1),%d0 + bgt sp_over + movel #1,%d0 |set destination format to single + bras do_fp |do normal case +dp: + lea ETEMP(%a6),%a0 + bclrb #sign_bit,LOCAL_EX(%a0) + sne LOCAL_SGN(%a0) + + btstb #7,STAG(%a6) |check for extended denorm + bne dp_catas |branch if so + + movew LOCAL_EX(%a0),%d0 + lea dp_bnds,%a1 + + cmpw (%a1),%d0 + blt dp_under + cmpw 2(%a1),%d0 + bgt dp_over + + movel #2,%d0 |set destination format to double +| ;fall through to do_fp +| +do_fp: + bfextu FPCR_MODE(%a6){#2:#2},%d1 |rnd mode in d1 + swap %d0 |rnd prec in upper word + addl %d0,%d1 |d1 has PREC/MODE info + + clrl %d0 |clear g,r,s + + bsrl round |round + + movel %a0,%a1 + movel EXC_EA(%a6),%a0 + + bfextu CMDREG1B(%a6){#3:#3},%d1 |extract destination format +| ;at this point only the dest +| ;formats sgl, dbl, ext are +| ;possible + cmpb #2,%d1 + bgts ddbl |double=5, extended=2, single=1 + bnes dsgl +| ;fall through to dext +dext: + bsrl dest_ext + bra mvout_end +dsgl: + bsrl dest_sgl + bra mvout_end +ddbl: + bsrl dest_dbl + bra mvout_end + +| +| Handle possible denorm or catastrophic underflow cases here +| +xdnrm: + bsr set_xop |initialize WBTEMP + bsetb #wbtemp15_bit,WB_BYTE(%a6) |set wbtemp15 + + movel %a0,%a1 + movel EXC_EA(%a6),%a0 |a0 has the destination pointer + bsrl dest_ext |store to memory + bsetb #unfl_bit,FPSR_EXCEPT(%a6) + bra mvout_end + +sp_under: + bsetb #etemp15_bit,STAG(%a6) + + cmpw 4(%a1),%d0 + blts sp_catas |catastrophic underflow case + + movel #1,%d0 |load in round precision + movel #sgl_thresh,%d1 |load in single denorm threshold + bsrl dpspdnrm |expects d1 to have the proper +| ;denorm threshold + bsrl dest_sgl |stores value to destination + bsetb #unfl_bit,FPSR_EXCEPT(%a6) + bra mvout_end |exit + +dp_under: + bsetb #etemp15_bit,STAG(%a6) + + cmpw 4(%a1),%d0 + blts dp_catas |catastrophic underflow case + + movel #dbl_thresh,%d1 |load in double precision threshold + movel #2,%d0 + bsrl dpspdnrm |expects d1 to have proper +| ;denorm threshold +| ;expects d0 to have round precision + bsrl dest_dbl |store value to destination + bsetb #unfl_bit,FPSR_EXCEPT(%a6) + bra mvout_end |exit + +| +| Handle catastrophic underflow cases here +| +sp_catas: +| Temp fix for z bit set in unf_sub + movel USER_FPSR(%a6),-(%a7) + + movel #1,%d0 |set round precision to sgl + + bsrl unf_sub |a0 points to result + + movel (%a7)+,USER_FPSR(%a6) + + movel #1,%d0 + subw %d0,LOCAL_EX(%a0) |account for difference between +| ;denorm/norm bias + + movel %a0,%a1 |a1 has the operand input + movel EXC_EA(%a6),%a0 |a0 has the destination pointer + + bsrl dest_sgl |store the result + oril #unfinx_mask,USER_FPSR(%a6) + bra mvout_end + +dp_catas: +| Temp fix for z bit set in unf_sub + movel USER_FPSR(%a6),-(%a7) + + movel #2,%d0 |set round precision to dbl + bsrl unf_sub |a0 points to result + + movel (%a7)+,USER_FPSR(%a6) + + movel #1,%d0 + subw %d0,LOCAL_EX(%a0) |account for difference between +| ;denorm/norm bias + + movel %a0,%a1 |a1 has the operand input + movel EXC_EA(%a6),%a0 |a0 has the destination pointer + + bsrl dest_dbl |store the result + oril #unfinx_mask,USER_FPSR(%a6) + bra mvout_end + +| +| Handle catastrophic overflow cases here +| +sp_over: +| Temp fix for z bit set in unf_sub + movel USER_FPSR(%a6),-(%a7) + + movel #1,%d0 + leal FP_SCR1(%a6),%a0 |use FP_SCR1 for creating result + movel ETEMP_EX(%a6),(%a0) + movel ETEMP_HI(%a6),4(%a0) + movel ETEMP_LO(%a6),8(%a0) + bsrl ovf_res + + movel (%a7)+,USER_FPSR(%a6) + + movel %a0,%a1 + movel EXC_EA(%a6),%a0 + bsrl dest_sgl + orl #ovfinx_mask,USER_FPSR(%a6) + bra mvout_end + +dp_over: +| Temp fix for z bit set in ovf_res + movel USER_FPSR(%a6),-(%a7) + + movel #2,%d0 + leal FP_SCR1(%a6),%a0 |use FP_SCR1 for creating result + movel ETEMP_EX(%a6),(%a0) + movel ETEMP_HI(%a6),4(%a0) + movel ETEMP_LO(%a6),8(%a0) + bsrl ovf_res + + movel (%a7)+,USER_FPSR(%a6) + + movel %a0,%a1 + movel EXC_EA(%a6),%a0 + bsrl dest_dbl + orl #ovfinx_mask,USER_FPSR(%a6) + bra mvout_end + +| +| DPSPDNRM +| +| This subroutine takes an extended normalized number and denormalizes +| it to the given round precision. This subroutine also decrements +| the input operand's exponent by 1 to account for the fact that +| dest_sgl or dest_dbl expects a normalized number's bias. +| +| Input: a0 points to a normalized number in internal extended format +| d0 is the round precision (=1 for sgl; =2 for dbl) +| d1 is the single precision or double precision +| denorm threshold +| +| Output: (In the format for dest_sgl or dest_dbl) +| a0 points to the destination +| a1 points to the operand +| +| Exceptions: Reports inexact 2 exception by setting USER_FPSR bits +| +dpspdnrm: + movel %d0,-(%a7) |save round precision + clrl %d0 |clear initial g,r,s + bsrl dnrm_lp |careful with d0, it's needed by round + + bfextu FPCR_MODE(%a6){#2:#2},%d1 |get rounding mode + swap %d1 + movew 2(%a7),%d1 |set rounding precision + swap %d1 |at this point d1 has PREC/MODE info + bsrl round |round result, sets the inex bit in +| ;USER_FPSR if needed + + movew #1,%d0 + subw %d0,LOCAL_EX(%a0) |account for difference in denorm +| ;vs norm bias + + movel %a0,%a1 |a1 has the operand input + movel EXC_EA(%a6),%a0 |a0 has the destination pointer + addw #4,%a7 |pop stack + rts +| +| SET_XOP initialized WBTEMP with the value pointed to by a0 +| input: a0 points to input operand in the internal extended format +| +set_xop: + movel LOCAL_EX(%a0),WBTEMP_EX(%a6) + movel LOCAL_HI(%a0),WBTEMP_HI(%a6) + movel LOCAL_LO(%a0),WBTEMP_LO(%a6) + bfclr WBTEMP_SGN(%a6){#0:#8} + beqs sxop + bsetb #sign_bit,WBTEMP_EX(%a6) +sxop: + bfclr STAG(%a6){#5:#4} |clear wbtm66,wbtm1,wbtm0,sbit + rts +| +| P_MOVE +| +p_movet: + .long p_move + .long p_movez + .long p_movei + .long p_moven + .long p_move +p_regd: + .long p_dyd0 + .long p_dyd1 + .long p_dyd2 + .long p_dyd3 + .long p_dyd4 + .long p_dyd5 + .long p_dyd6 + .long p_dyd7 + +pack_out: + leal p_movet,%a0 |load jmp table address + movew STAG(%a6),%d0 |get source tag + bfextu %d0{#16:#3},%d0 |isolate source bits + movel (%a0,%d0.w*4),%a0 |load a0 with routine label for tag + jmp (%a0) |go to the routine + +p_write: + movel #0x0c,%d0 |get byte count + movel EXC_EA(%a6),%a1 |get the destination address + bsr mem_write |write the user's destination + moveb #0,CU_SAVEPC(%a6) |set the cu save pc to all 0's + +| +| Also note that the dtag must be set to norm here - this is because +| the 040 uses the dtag to execute the correct microcode. +| + bfclr DTAG(%a6){#0:#3} |set dtag to norm + + rts + +| Notes on handling of special case (zero, inf, and nan) inputs: +| 1. Operr is not signalled if the k-factor is greater than 18. +| 2. Per the manual, status bits are not set. +| + +p_move: + movew CMDREG1B(%a6),%d0 + btstl #kfact_bit,%d0 |test for dynamic k-factor + beqs statick |if clear, k-factor is static +dynamick: + bfextu %d0{#25:#3},%d0 |isolate register for dynamic k-factor + lea p_regd,%a0 + movel %a0@(%d0:l:4),%a0 + jmp (%a0) +statick: + andiw #0x007f,%d0 |get k-factor + bfexts %d0{#25:#7},%d0 |sign extend d0 for bindec + leal ETEMP(%a6),%a0 |a0 will point to the packed decimal + bsrl bindec |perform the convert; data at a6 + leal FP_SCR1(%a6),%a0 |load a0 with result address + bral p_write +p_movez: + leal ETEMP(%a6),%a0 |a0 will point to the packed decimal + clrw 2(%a0) |clear lower word of exp + clrl 4(%a0) |load second lword of ZERO + clrl 8(%a0) |load third lword of ZERO + bra p_write |go write results +p_movei: + fmovel #0,%FPSR |clear aiop + leal ETEMP(%a6),%a0 |a0 will point to the packed decimal + clrw 2(%a0) |clear lower word of exp + bra p_write |go write the result +p_moven: + leal ETEMP(%a6),%a0 |a0 will point to the packed decimal + clrw 2(%a0) |clear lower word of exp + bra p_write |go write the result + +| +| Routines to read the dynamic k-factor from Dn. +| +p_dyd0: + movel USER_D0(%a6),%d0 + bras statick +p_dyd1: + movel USER_D1(%a6),%d0 + bras statick +p_dyd2: + movel %d2,%d0 + bras statick +p_dyd3: + movel %d3,%d0 + bras statick +p_dyd4: + movel %d4,%d0 + bras statick +p_dyd5: + movel %d5,%d0 + bras statick +p_dyd6: + movel %d6,%d0 + bra statick +p_dyd7: + movel %d7,%d0 + bra statick + + |end diff --git a/arch/m68k/fpsp040/round.S b/arch/m68k/fpsp040/round.S new file mode 100644 index 000000000..f84ae0dd4 --- /dev/null +++ b/arch/m68k/fpsp040/round.S @@ -0,0 +1,648 @@ +| +| round.sa 3.4 7/29/91 +| +| handle rounding and normalization tasks +| +| +| +| Copyright (C) Motorola, Inc. 1990 +| All Rights Reserved +| +| For details on the license for this file, please see the +| file, README, in this same directory. + +|ROUND idnt 2,1 | Motorola 040 Floating Point Software Package + + |section 8 + +#include "fpsp.h" + +| +| round --- round result according to precision/mode +| +| a0 points to the input operand in the internal extended format +| d1(high word) contains rounding precision: +| ext = $0000xxxx +| sgl = $0001xxxx +| dbl = $0002xxxx +| d1(low word) contains rounding mode: +| RN = $xxxx0000 +| RZ = $xxxx0001 +| RM = $xxxx0010 +| RP = $xxxx0011 +| d0{31:29} contains the g,r,s bits (extended) +| +| On return the value pointed to by a0 is correctly rounded, +| a0 is preserved and the g-r-s bits in d0 are cleared. +| The result is not typed - the tag field is invalid. The +| result is still in the internal extended format. +| +| The INEX bit of USER_FPSR will be set if the rounded result was +| inexact (i.e. if any of the g-r-s bits were set). +| + + .global round +round: +| If g=r=s=0 then result is exact and round is done, else set +| the inex flag in status reg and continue. +| + bsrs ext_grs |this subroutine looks at the +| :rounding precision and sets +| ;the appropriate g-r-s bits. + tstl %d0 |if grs are zero, go force + bne rnd_cont |lower bits to zero for size + + swap %d1 |set up d1.w for round prec. + bra truncate + +rnd_cont: +| +| Use rounding mode as an index into a jump table for these modes. +| + orl #inx2a_mask,USER_FPSR(%a6) |set inex2/ainex + lea mode_tab,%a1 + movel (%a1,%d1.w*4),%a1 + jmp (%a1) +| +| Jump table indexed by rounding mode in d1.w. All following assumes +| grs != 0. +| +mode_tab: + .long rnd_near + .long rnd_zero + .long rnd_mnus + .long rnd_plus +| +| ROUND PLUS INFINITY +| +| If sign of fp number = 0 (positive), then add 1 to l. +| +rnd_plus: + swap %d1 |set up d1 for round prec. + tstb LOCAL_SGN(%a0) |check for sign + bmi truncate |if positive then truncate + movel #0xffffffff,%d0 |force g,r,s to be all f's + lea add_to_l,%a1 + movel (%a1,%d1.w*4),%a1 + jmp (%a1) +| +| ROUND MINUS INFINITY +| +| If sign of fp number = 1 (negative), then add 1 to l. +| +rnd_mnus: + swap %d1 |set up d1 for round prec. + tstb LOCAL_SGN(%a0) |check for sign + bpl truncate |if negative then truncate + movel #0xffffffff,%d0 |force g,r,s to be all f's + lea add_to_l,%a1 + movel (%a1,%d1.w*4),%a1 + jmp (%a1) +| +| ROUND ZERO +| +| Always truncate. +rnd_zero: + swap %d1 |set up d1 for round prec. + bra truncate +| +| +| ROUND NEAREST +| +| If (g=1), then add 1 to l and if (r=s=0), then clear l +| Note that this will round to even in case of a tie. +| +rnd_near: + swap %d1 |set up d1 for round prec. + asll #1,%d0 |shift g-bit to c-bit + bcc truncate |if (g=1) then + lea add_to_l,%a1 + movel (%a1,%d1.w*4),%a1 + jmp (%a1) + +| +| ext_grs --- extract guard, round and sticky bits +| +| Input: d1 = PREC:ROUND +| Output: d0{31:29}= guard, round, sticky +| +| The ext_grs extract the guard/round/sticky bits according to the +| selected rounding precision. It is called by the round subroutine +| only. All registers except d0 are kept intact. d0 becomes an +| updated guard,round,sticky in d0{31:29} +| +| Notes: the ext_grs uses the round PREC, and therefore has to swap d1 +| prior to usage, and needs to restore d1 to original. +| +ext_grs: + swap %d1 |have d1.w point to round precision + cmpiw #0,%d1 + bnes sgl_or_dbl + bras end_ext_grs + +sgl_or_dbl: + moveml %d2/%d3,-(%a7) |make some temp registers + cmpiw #1,%d1 + bnes grs_dbl +grs_sgl: + bfextu LOCAL_HI(%a0){#24:#2},%d3 |sgl prec. g-r are 2 bits right + movel #30,%d2 |of the sgl prec. limits + lsll %d2,%d3 |shift g-r bits to MSB of d3 + movel LOCAL_HI(%a0),%d2 |get word 2 for s-bit test + andil #0x0000003f,%d2 |s bit is the or of all other + bnes st_stky |bits to the right of g-r + tstl LOCAL_LO(%a0) |test lower mantissa + bnes st_stky |if any are set, set sticky + tstl %d0 |test original g,r,s + bnes st_stky |if any are set, set sticky + bras end_sd |if words 3 and 4 are clr, exit +grs_dbl: + bfextu LOCAL_LO(%a0){#21:#2},%d3 |dbl-prec. g-r are 2 bits right + movel #30,%d2 |of the dbl prec. limits + lsll %d2,%d3 |shift g-r bits to the MSB of d3 + movel LOCAL_LO(%a0),%d2 |get lower mantissa for s-bit test + andil #0x000001ff,%d2 |s bit is the or-ing of all + bnes st_stky |other bits to the right of g-r + tstl %d0 |test word original g,r,s + bnes st_stky |if any are set, set sticky + bras end_sd |if clear, exit +st_stky: + bset #rnd_stky_bit,%d3 +end_sd: + movel %d3,%d0 |return grs to d0 + moveml (%a7)+,%d2/%d3 |restore scratch registers +end_ext_grs: + swap %d1 |restore d1 to original + rts + +|******************* Local Equates + .set ad_1_sgl,0x00000100 | constant to add 1 to l-bit in sgl prec + .set ad_1_dbl,0x00000800 | constant to add 1 to l-bit in dbl prec + + +|Jump table for adding 1 to the l-bit indexed by rnd prec + +add_to_l: + .long add_ext + .long add_sgl + .long add_dbl + .long add_dbl +| +| ADD SINGLE +| +add_sgl: + addl #ad_1_sgl,LOCAL_HI(%a0) + bccs scc_clr |no mantissa overflow + roxrw LOCAL_HI(%a0) |shift v-bit back in + roxrw LOCAL_HI+2(%a0) |shift v-bit back in + addw #0x1,LOCAL_EX(%a0) |and incr exponent +scc_clr: + tstl %d0 |test for rs = 0 + bnes sgl_done + andiw #0xfe00,LOCAL_HI+2(%a0) |clear the l-bit +sgl_done: + andil #0xffffff00,LOCAL_HI(%a0) |truncate bits beyond sgl limit + clrl LOCAL_LO(%a0) |clear d2 + rts + +| +| ADD EXTENDED +| +add_ext: + addql #1,LOCAL_LO(%a0) |add 1 to l-bit + bccs xcc_clr |test for carry out + addql #1,LOCAL_HI(%a0) |propagate carry + bccs xcc_clr + roxrw LOCAL_HI(%a0) |mant is 0 so restore v-bit + roxrw LOCAL_HI+2(%a0) |mant is 0 so restore v-bit + roxrw LOCAL_LO(%a0) + roxrw LOCAL_LO+2(%a0) + addw #0x1,LOCAL_EX(%a0) |and inc exp +xcc_clr: + tstl %d0 |test rs = 0 + bnes add_ext_done + andib #0xfe,LOCAL_LO+3(%a0) |clear the l bit +add_ext_done: + rts +| +| ADD DOUBLE +| +add_dbl: + addl #ad_1_dbl,LOCAL_LO(%a0) + bccs dcc_clr + addql #1,LOCAL_HI(%a0) |propagate carry + bccs dcc_clr + roxrw LOCAL_HI(%a0) |mant is 0 so restore v-bit + roxrw LOCAL_HI+2(%a0) |mant is 0 so restore v-bit + roxrw LOCAL_LO(%a0) + roxrw LOCAL_LO+2(%a0) + addw #0x1,LOCAL_EX(%a0) |incr exponent +dcc_clr: + tstl %d0 |test for rs = 0 + bnes dbl_done + andiw #0xf000,LOCAL_LO+2(%a0) |clear the l-bit + +dbl_done: + andil #0xfffff800,LOCAL_LO(%a0) |truncate bits beyond dbl limit + rts + +error: + rts +| +| Truncate all other bits +| +trunct: + .long end_rnd + .long sgl_done + .long dbl_done + .long dbl_done + +truncate: + lea trunct,%a1 + movel (%a1,%d1.w*4),%a1 + jmp (%a1) + +end_rnd: + rts + +| +| NORMALIZE +| +| These routines (nrm_zero & nrm_set) normalize the unnorm. This +| is done by shifting the mantissa left while decrementing the +| exponent. +| +| NRM_SET shifts and decrements until there is a 1 set in the integer +| bit of the mantissa (msb in d1). +| +| NRM_ZERO shifts and decrements until there is a 1 set in the integer +| bit of the mantissa (msb in d1) unless this would mean the exponent +| would go less than 0. In that case the number becomes a denorm - the +| exponent (d0) is set to 0 and the mantissa (d1 & d2) is not +| normalized. +| +| Note that both routines have been optimized (for the worst case) and +| therefore do not have the easy to follow decrement/shift loop. +| +| NRM_ZERO +| +| Distance to first 1 bit in mantissa = X +| Distance to 0 from exponent = Y +| If X < Y +| Then +| nrm_set +| Else +| shift mantissa by Y +| set exponent = 0 +| +|input: +| FP_SCR1 = exponent, ms mantissa part, ls mantissa part +|output: +| L_SCR1{4} = fpte15 or ete15 bit +| + .global nrm_zero +nrm_zero: + movew LOCAL_EX(%a0),%d0 + cmpw #64,%d0 |see if exp > 64 + bmis d0_less + bsr nrm_set |exp > 64 so exp won't exceed 0 + rts +d0_less: + moveml %d2/%d3/%d5/%d6,-(%a7) + movel LOCAL_HI(%a0),%d1 + movel LOCAL_LO(%a0),%d2 + + bfffo %d1{#0:#32},%d3 |get the distance to the first 1 +| ;in ms mant + beqs ms_clr |branch if no bits were set + cmpw %d3,%d0 |of X>Y + bmis greater |then exp will go past 0 (neg) if +| ;it is just shifted + bsr nrm_set |else exp won't go past 0 + moveml (%a7)+,%d2/%d3/%d5/%d6 + rts +greater: + movel %d2,%d6 |save ls mant in d6 + lsll %d0,%d2 |shift ls mant by count + lsll %d0,%d1 |shift ms mant by count + movel #32,%d5 + subl %d0,%d5 |make op a denorm by shifting bits + lsrl %d5,%d6 |by the number in the exp, then +| ;set exp = 0. + orl %d6,%d1 |shift the ls mant bits into the ms mant + movel #0,%d0 |same as if decremented exp to 0 +| ;while shifting + movew %d0,LOCAL_EX(%a0) + movel %d1,LOCAL_HI(%a0) + movel %d2,LOCAL_LO(%a0) + moveml (%a7)+,%d2/%d3/%d5/%d6 + rts +ms_clr: + bfffo %d2{#0:#32},%d3 |check if any bits set in ls mant + beqs all_clr |branch if none set + addw #32,%d3 + cmpw %d3,%d0 |if X>Y + bmis greater |then branch + bsr nrm_set |else exp won't go past 0 + moveml (%a7)+,%d2/%d3/%d5/%d6 + rts +all_clr: + movew #0,LOCAL_EX(%a0) |no mantissa bits set. Set exp = 0. + moveml (%a7)+,%d2/%d3/%d5/%d6 + rts +| +| NRM_SET +| + .global nrm_set +nrm_set: + movel %d7,-(%a7) + bfffo LOCAL_HI(%a0){#0:#32},%d7 |find first 1 in ms mant to d7) + beqs lower |branch if ms mant is all 0's + + movel %d6,-(%a7) + + subw %d7,LOCAL_EX(%a0) |sub exponent by count + movel LOCAL_HI(%a0),%d0 |d0 has ms mant + movel LOCAL_LO(%a0),%d1 |d1 has ls mant + + lsll %d7,%d0 |shift first 1 to j bit position + movel %d1,%d6 |copy ls mant into d6 + lsll %d7,%d6 |shift ls mant by count + movel %d6,LOCAL_LO(%a0) |store ls mant into memory + moveql #32,%d6 + subl %d7,%d6 |continue shift + lsrl %d6,%d1 |shift off all bits but those that will +| ;be shifted into ms mant + orl %d1,%d0 |shift the ls mant bits into the ms mant + movel %d0,LOCAL_HI(%a0) |store ms mant into memory + moveml (%a7)+,%d7/%d6 |restore registers + rts + +| +| We get here if ms mant was = 0, and we assume ls mant has bits +| set (otherwise this would have been tagged a zero not a denorm). +| +lower: + movew LOCAL_EX(%a0),%d0 |d0 has exponent + movel LOCAL_LO(%a0),%d1 |d1 has ls mant + subw #32,%d0 |account for ms mant being all zeros + bfffo %d1{#0:#32},%d7 |find first 1 in ls mant to d7) + subw %d7,%d0 |subtract shift count from exp + lsll %d7,%d1 |shift first 1 to integer bit in ms mant + movew %d0,LOCAL_EX(%a0) |store ms mant + movel %d1,LOCAL_HI(%a0) |store exp + clrl LOCAL_LO(%a0) |clear ls mant + movel (%a7)+,%d7 + rts +| +| denorm --- denormalize an intermediate result +| +| Used by underflow. +| +| Input: +| a0 points to the operand to be denormalized +| (in the internal extended format) +| +| d0: rounding precision +| Output: +| a0 points to the denormalized result +| (in the internal extended format) +| +| d0 is guard,round,sticky +| +| d0 comes into this routine with the rounding precision. It +| is then loaded with the denormalized exponent threshold for the +| rounding precision. +| + + .global denorm +denorm: + btstb #6,LOCAL_EX(%a0) |check for exponents between $7fff-$4000 + beqs no_sgn_ext + bsetb #7,LOCAL_EX(%a0) |sign extend if it is so +no_sgn_ext: + + cmpib #0,%d0 |if 0 then extended precision + bnes not_ext |else branch + + clrl %d1 |load d1 with ext threshold + clrl %d0 |clear the sticky flag + bsr dnrm_lp |denormalize the number + tstb %d1 |check for inex + beq no_inex |if clr, no inex + bras dnrm_inex |if set, set inex + +not_ext: + cmpil #1,%d0 |if 1 then single precision + beqs load_sgl |else must be 2, double prec + +load_dbl: + movew #dbl_thresh,%d1 |put copy of threshold in d1 + movel %d1,%d0 |copy d1 into d0 + subw LOCAL_EX(%a0),%d0 |diff = threshold - exp + cmpw #67,%d0 |if diff > 67 (mant + grs bits) + bpls chk_stky |then branch (all bits would be +| ; shifted off in denorm routine) + clrl %d0 |else clear the sticky flag + bsr dnrm_lp |denormalize the number + tstb %d1 |check flag + beqs no_inex |if clr, no inex + bras dnrm_inex |if set, set inex + +load_sgl: + movew #sgl_thresh,%d1 |put copy of threshold in d1 + movel %d1,%d0 |copy d1 into d0 + subw LOCAL_EX(%a0),%d0 |diff = threshold - exp + cmpw #67,%d0 |if diff > 67 (mant + grs bits) + bpls chk_stky |then branch (all bits would be +| ; shifted off in denorm routine) + clrl %d0 |else clear the sticky flag + bsr dnrm_lp |denormalize the number + tstb %d1 |check flag + beqs no_inex |if clr, no inex + bras dnrm_inex |if set, set inex + +chk_stky: + tstl LOCAL_HI(%a0) |check for any bits set + bnes set_stky + tstl LOCAL_LO(%a0) |check for any bits set + bnes set_stky + bras clr_mant +set_stky: + orl #inx2a_mask,USER_FPSR(%a6) |set inex2/ainex + movel #0x20000000,%d0 |set sticky bit in return value +clr_mant: + movew %d1,LOCAL_EX(%a0) |load exp with threshold + movel #0,LOCAL_HI(%a0) |set d1 = 0 (ms mantissa) + movel #0,LOCAL_LO(%a0) |set d2 = 0 (ms mantissa) + rts +dnrm_inex: + orl #inx2a_mask,USER_FPSR(%a6) |set inex2/ainex +no_inex: + rts + +| +| dnrm_lp --- normalize exponent/mantissa to specified threshold +| +| Input: +| a0 points to the operand to be denormalized +| d0{31:29} initial guard,round,sticky +| d1{15:0} denormalization threshold +| Output: +| a0 points to the denormalized operand +| d0{31:29} final guard,round,sticky +| d1.b inexact flag: all ones means inexact result +| +| The LOCAL_LO and LOCAL_GRS parts of the value are copied to FP_SCR2 +| so that bfext can be used to extract the new low part of the mantissa. +| Dnrm_lp can be called with a0 pointing to ETEMP or WBTEMP and there +| is no LOCAL_GRS scratch word following it on the fsave frame. +| + .global dnrm_lp +dnrm_lp: + movel %d2,-(%sp) |save d2 for temp use + btstb #E3,E_BYTE(%a6) |test for type E3 exception + beqs not_E3 |not type E3 exception + bfextu WBTEMP_GRS(%a6){#6:#3},%d2 |extract guard,round, sticky bit + movel #29,%d0 + lsll %d0,%d2 |shift g,r,s to their positions + movel %d2,%d0 +not_E3: + movel (%sp)+,%d2 |restore d2 + movel LOCAL_LO(%a0),FP_SCR2+LOCAL_LO(%a6) + movel %d0,FP_SCR2+LOCAL_GRS(%a6) + movel %d1,%d0 |copy the denorm threshold + subw LOCAL_EX(%a0),%d1 |d1 = threshold - uns exponent + bles no_lp |d1 <= 0 + cmpw #32,%d1 + blts case_1 |0 = d1 < 32 + cmpw #64,%d1 + blts case_2 |32 <= d1 < 64 + bra case_3 |d1 >= 64 +| +| No normalization necessary +| +no_lp: + clrb %d1 |set no inex2 reported + movel FP_SCR2+LOCAL_GRS(%a6),%d0 |restore original g,r,s + rts +| +| case (0= 64 Force the exponent to be the denorm threshold with the +| correct sign. +| +case_3: + movew %d0,LOCAL_EX(%a0) + tstw LOCAL_SGN(%a0) + bges c3con +c3neg: + orl #0x80000000,LOCAL_EX(%a0) +c3con: + cmpw #64,%d1 + beqs sixty_four + cmpw #65,%d1 + beqs sixty_five +| +| Shift value is out of range. Set d1 for inex2 flag and +| return a zero with the given threshold. +| + clrl LOCAL_HI(%a0) + clrl LOCAL_LO(%a0) + movel #0x20000000,%d0 + st %d1 + rts + +sixty_four: + movel LOCAL_HI(%a0),%d0 + bfextu %d0{#2:#30},%d1 + andil #0xc0000000,%d0 + bras c3com + +sixty_five: + movel LOCAL_HI(%a0),%d0 + bfextu %d0{#1:#31},%d1 + andil #0x80000000,%d0 + lsrl #1,%d0 |shift high bit into R bit + +c3com: + tstl %d1 + bnes c3ssticky + tstl LOCAL_LO(%a0) + bnes c3ssticky + tstb FP_SCR2+LOCAL_GRS(%a6) + bnes c3ssticky + clrb %d1 + bras c3end + +c3ssticky: + bsetl #rnd_stky_bit,%d0 + st %d1 +c3end: + clrl LOCAL_HI(%a0) + clrl LOCAL_LO(%a0) + rts + + |end diff --git a/arch/m68k/fpsp040/sacos.S b/arch/m68k/fpsp040/sacos.S new file mode 100644 index 000000000..513c7cca7 --- /dev/null +++ b/arch/m68k/fpsp040/sacos.S @@ -0,0 +1,114 @@ +| +| sacos.sa 3.3 12/19/90 +| +| Description: The entry point sAcos computes the inverse cosine of +| an input argument; sAcosd does the same except for denormalized +| input. +| +| Input: Double-extended number X in location pointed to +| by address register a0. +| +| Output: The value arccos(X) returned in floating-point register Fp0. +| +| Accuracy and Monotonicity: The returned result is within 3 ulps in +| 64 significant bit, i.e. within 0.5001 ulp to 53 bits if the +| result is subsequently rounded to double precision. The +| result is provably monotonic in double precision. +| +| Speed: The program sCOS takes approximately 310 cycles. +| +| Algorithm: +| +| ACOS +| 1. If |X| >= 1, go to 3. +| +| 2. (|X| < 1) Calculate acos(X) by +| z := (1-X) / (1+X) +| acos(X) = 2 * atan( sqrt(z) ). +| Exit. +| +| 3. If |X| > 1, go to 5. +| +| 4. (|X| = 1) If X > 0, return 0. Otherwise, return Pi. Exit. +| +| 5. (|X| > 1) Generate an invalid operation by 0 * infinity. +| Exit. +| + +| Copyright (C) Motorola, Inc. 1990 +| All Rights Reserved +| +| For details on the license for this file, please see the +| file, README, in this same directory. + +|SACOS idnt 2,1 | Motorola 040 Floating Point Software Package + + |section 8 + +PI: .long 0x40000000,0xC90FDAA2,0x2168C235,0x00000000 +PIBY2: .long 0x3FFF0000,0xC90FDAA2,0x2168C235,0x00000000 + + |xref t_operr + |xref t_frcinx + |xref satan + + .global sacosd +sacosd: +|--ACOS(X) = PI/2 FOR DENORMALIZED X + fmovel %d1,%fpcr | ...load user's rounding mode/precision + fmovex PIBY2,%fp0 + bra t_frcinx + + .global sacos +sacos: + fmovex (%a0),%fp0 | ...LOAD INPUT + + movel (%a0),%d0 | ...pack exponent with upper 16 fraction + movew 4(%a0),%d0 + andil #0x7FFFFFFF,%d0 + cmpil #0x3FFF8000,%d0 + bges ACOSBIG + +|--THIS IS THE USUAL CASE, |X| < 1 +|--ACOS(X) = 2 * ATAN( SQRT( (1-X)/(1+X) ) ) + + fmoves #0x3F800000,%fp1 + faddx %fp0,%fp1 | ...1+X + fnegx %fp0 | ... -X + fadds #0x3F800000,%fp0 | ...1-X + fdivx %fp1,%fp0 | ...(1-X)/(1+X) + fsqrtx %fp0 | ...SQRT((1-X)/(1+X)) + fmovemx %fp0-%fp0,(%a0) | ...overwrite input + movel %d1,-(%sp) |save original users fpcr + clrl %d1 + bsr satan | ...ATAN(SQRT([1-X]/[1+X])) + fmovel (%sp)+,%fpcr |restore users exceptions + faddx %fp0,%fp0 | ...2 * ATAN( STUFF ) + bra t_frcinx + +ACOSBIG: + fabsx %fp0 + fcmps #0x3F800000,%fp0 + fbgt t_operr |cause an operr exception + +|--|X| = 1, ACOS(X) = 0 OR PI + movel (%a0),%d0 | ...pack exponent with upper 16 fraction + movew 4(%a0),%d0 + cmpl #0,%d0 |D0 has original exponent+fraction + bgts ACOSP1 + +|--X = -1 +|Returns PI and inexact exception + fmovex PI,%fp0 + fmovel %d1,%FPCR + fadds #0x00800000,%fp0 |cause an inexact exception to be put +| ;into the 040 - will not trap until next +| ;fp inst. + bra t_frcinx + +ACOSP1: + fmovel %d1,%FPCR + fmoves #0x00000000,%fp0 + rts |Facos ; of +1 is exact + + |end diff --git a/arch/m68k/fpsp040/sasin.S b/arch/m68k/fpsp040/sasin.S new file mode 100644 index 000000000..2a269a58c --- /dev/null +++ b/arch/m68k/fpsp040/sasin.S @@ -0,0 +1,103 @@ +| +| sasin.sa 3.3 12/19/90 +| +| Description: The entry point sAsin computes the inverse sine of +| an input argument; sAsind does the same except for denormalized +| input. +| +| Input: Double-extended number X in location pointed to +| by address register a0. +| +| Output: The value arcsin(X) returned in floating-point register Fp0. +| +| Accuracy and Monotonicity: The returned result is within 3 ulps in +| 64 significant bit, i.e. within 0.5001 ulp to 53 bits if the +| result is subsequently rounded to double precision. The +| result is provably monotonic in double precision. +| +| Speed: The program sASIN takes approximately 310 cycles. +| +| Algorithm: +| +| ASIN +| 1. If |X| >= 1, go to 3. +| +| 2. (|X| < 1) Calculate asin(X) by +| z := sqrt( [1-X][1+X] ) +| asin(X) = atan( x / z ). +| Exit. +| +| 3. If |X| > 1, go to 5. +| +| 4. (|X| = 1) sgn := sign(X), return asin(X) := sgn * Pi/2. Exit. +| +| 5. (|X| > 1) Generate an invalid operation by 0 * infinity. +| Exit. +| + +| Copyright (C) Motorola, Inc. 1990 +| All Rights Reserved +| +| For details on the license for this file, please see the +| file, README, in this same directory. + +|SASIN idnt 2,1 | Motorola 040 Floating Point Software Package + + |section 8 + +PIBY2: .long 0x3FFF0000,0xC90FDAA2,0x2168C235,0x00000000 + + |xref t_operr + |xref t_frcinx + |xref t_extdnrm + |xref satan + + .global sasind +sasind: +|--ASIN(X) = X FOR DENORMALIZED X + + bra t_extdnrm + + .global sasin +sasin: + fmovex (%a0),%fp0 | ...LOAD INPUT + + movel (%a0),%d0 + movew 4(%a0),%d0 + andil #0x7FFFFFFF,%d0 + cmpil #0x3FFF8000,%d0 + bges asinbig + +|--THIS IS THE USUAL CASE, |X| < 1 +|--ASIN(X) = ATAN( X / SQRT( (1-X)(1+X) ) ) + + fmoves #0x3F800000,%fp1 + fsubx %fp0,%fp1 | ...1-X + fmovemx %fp2-%fp2,-(%a7) + fmoves #0x3F800000,%fp2 + faddx %fp0,%fp2 | ...1+X + fmulx %fp2,%fp1 | ...(1+X)(1-X) + fmovemx (%a7)+,%fp2-%fp2 + fsqrtx %fp1 | ...SQRT([1-X][1+X]) + fdivx %fp1,%fp0 | ...X/SQRT([1-X][1+X]) + fmovemx %fp0-%fp0,(%a0) + bsr satan + bra t_frcinx + +asinbig: + fabsx %fp0 | ...|X| + fcmps #0x3F800000,%fp0 + fbgt t_operr |cause an operr exception + +|--|X| = 1, ASIN(X) = +- PI/2. + + fmovex PIBY2,%fp0 + movel (%a0),%d0 + andil #0x80000000,%d0 | ...SIGN BIT OF X + oril #0x3F800000,%d0 | ...+-1 IN SGL FORMAT + movel %d0,-(%sp) | ...push SIGN(X) IN SGL-FMT + fmovel %d1,%FPCR + fmuls (%sp)+,%fp0 + bra t_frcinx + + |end diff --git a/arch/m68k/fpsp040/satan.S b/arch/m68k/fpsp040/satan.S new file mode 100644 index 000000000..c8a664998 --- /dev/null +++ b/arch/m68k/fpsp040/satan.S @@ -0,0 +1,477 @@ +| +| satan.sa 3.3 12/19/90 +| +| The entry point satan computes the arctangent of an +| input value. satand does the same except the input value is a +| denormalized number. +| +| Input: Double-extended value in memory location pointed to by address +| register a0. +| +| Output: Arctan(X) returned in floating-point register Fp0. +| +| Accuracy and Monotonicity: The returned result is within 2 ulps in +| 64 significant bit, i.e. within 0.5001 ulp to 53 bits if the +| result is subsequently rounded to double precision. The +| result is provably monotonic in double precision. +| +| Speed: The program satan takes approximately 160 cycles for input +| argument X such that 1/16 < |X| < 16. For the other arguments, +| the program will run no worse than 10% slower. +| +| Algorithm: +| Step 1. If |X| >= 16 or |X| < 1/16, go to Step 5. +| +| Step 2. Let X = sgn * 2**k * 1.xxxxxxxx...x. Note that k = -4, -3,..., or 3. +| Define F = sgn * 2**k * 1.xxxx1, i.e. the first 5 significant bits +| of X with a bit-1 attached at the 6-th bit position. Define u +| to be u = (X-F) / (1 + X*F). +| +| Step 3. Approximate arctan(u) by a polynomial poly. +| +| Step 4. Return arctan(F) + poly, arctan(F) is fetched from a table of values +| calculated beforehand. Exit. +| +| Step 5. If |X| >= 16, go to Step 7. +| +| Step 6. Approximate arctan(X) by an odd polynomial in X. Exit. +| +| Step 7. Define X' = -1/X. Approximate arctan(X') by an odd polynomial in X'. +| Arctan(X) = sign(X)*Pi/2 + arctan(X'). Exit. +| + +| Copyright (C) Motorola, Inc. 1990 +| All Rights Reserved +| +| For details on the license for this file, please see the +| file, README, in this same directory. + +|satan idnt 2,1 | Motorola 040 Floating Point Software Package + + |section 8 + +#include "fpsp.h" + +BOUNDS1: .long 0x3FFB8000,0x4002FFFF + +ONE: .long 0x3F800000 + + .long 0x00000000 + +ATANA3: .long 0xBFF6687E,0x314987D8 +ATANA2: .long 0x4002AC69,0x34A26DB3 + +ATANA1: .long 0xBFC2476F,0x4E1DA28E +ATANB6: .long 0x3FB34444,0x7F876989 + +ATANB5: .long 0xBFB744EE,0x7FAF45DB +ATANB4: .long 0x3FBC71C6,0x46940220 + +ATANB3: .long 0xBFC24924,0x921872F9 +ATANB2: .long 0x3FC99999,0x99998FA9 + +ATANB1: .long 0xBFD55555,0x55555555 +ATANC5: .long 0xBFB70BF3,0x98539E6A + +ATANC4: .long 0x3FBC7187,0x962D1D7D +ATANC3: .long 0xBFC24924,0x827107B8 + +ATANC2: .long 0x3FC99999,0x9996263E +ATANC1: .long 0xBFD55555,0x55555536 + +PPIBY2: .long 0x3FFF0000,0xC90FDAA2,0x2168C235,0x00000000 +NPIBY2: .long 0xBFFF0000,0xC90FDAA2,0x2168C235,0x00000000 +PTINY: .long 0x00010000,0x80000000,0x00000000,0x00000000 +NTINY: .long 0x80010000,0x80000000,0x00000000,0x00000000 + +ATANTBL: + .long 0x3FFB0000,0x83D152C5,0x060B7A51,0x00000000 + .long 0x3FFB0000,0x8BC85445,0x65498B8B,0x00000000 + .long 0x3FFB0000,0x93BE4060,0x17626B0D,0x00000000 + .long 0x3FFB0000,0x9BB3078D,0x35AEC202,0x00000000 + .long 0x3FFB0000,0xA3A69A52,0x5DDCE7DE,0x00000000 + .long 0x3FFB0000,0xAB98E943,0x62765619,0x00000000 + .long 0x3FFB0000,0xB389E502,0xF9C59862,0x00000000 + .long 0x3FFB0000,0xBB797E43,0x6B09E6FB,0x00000000 + .long 0x3FFB0000,0xC367A5C7,0x39E5F446,0x00000000 + .long 0x3FFB0000,0xCB544C61,0xCFF7D5C6,0x00000000 + .long 0x3FFB0000,0xD33F62F8,0x2488533E,0x00000000 + .long 0x3FFB0000,0xDB28DA81,0x62404C77,0x00000000 + .long 0x3FFB0000,0xE310A407,0x8AD34F18,0x00000000 + .long 0x3FFB0000,0xEAF6B0A8,0x188EE1EB,0x00000000 + .long 0x3FFB0000,0xF2DAF194,0x9DBE79D5,0x00000000 + .long 0x3FFB0000,0xFABD5813,0x61D47E3E,0x00000000 + .long 0x3FFC0000,0x8346AC21,0x0959ECC4,0x00000000 + .long 0x3FFC0000,0x8B232A08,0x304282D8,0x00000000 + .long 0x3FFC0000,0x92FB70B8,0xD29AE2F9,0x00000000 + .long 0x3FFC0000,0x9ACF476F,0x5CCD1CB4,0x00000000 + .long 0x3FFC0000,0xA29E7630,0x4954F23F,0x00000000 + .long 0x3FFC0000,0xAA68C5D0,0x8AB85230,0x00000000 + .long 0x3FFC0000,0xB22DFFFD,0x9D539F83,0x00000000 + .long 0x3FFC0000,0xB9EDEF45,0x3E900EA5,0x00000000 + .long 0x3FFC0000,0xC1A85F1C,0xC75E3EA5,0x00000000 + .long 0x3FFC0000,0xC95D1BE8,0x28138DE6,0x00000000 + .long 0x3FFC0000,0xD10BF300,0x840D2DE4,0x00000000 + .long 0x3FFC0000,0xD8B4B2BA,0x6BC05E7A,0x00000000 + .long 0x3FFC0000,0xE0572A6B,0xB42335F6,0x00000000 + .long 0x3FFC0000,0xE7F32A70,0xEA9CAA8F,0x00000000 + .long 0x3FFC0000,0xEF888432,0x64ECEFAA,0x00000000 + .long 0x3FFC0000,0xF7170A28,0xECC06666,0x00000000 + .long 0x3FFD0000,0x812FD288,0x332DAD32,0x00000000 + .long 0x3FFD0000,0x88A8D1B1,0x218E4D64,0x00000000 + .long 0x3FFD0000,0x9012AB3F,0x23E4AEE8,0x00000000 + .long 0x3FFD0000,0x976CC3D4,0x11E7F1B9,0x00000000 + .long 0x3FFD0000,0x9EB68949,0x3889A227,0x00000000 + .long 0x3FFD0000,0xA5EF72C3,0x4487361B,0x00000000 + .long 0x3FFD0000,0xAD1700BA,0xF07A7227,0x00000000 + .long 0x3FFD0000,0xB42CBCFA,0xFD37EFB7,0x00000000 + .long 0x3FFD0000,0xBB303A94,0x0BA80F89,0x00000000 + .long 0x3FFD0000,0xC22115C6,0xFCAEBBAF,0x00000000 + .long 0x3FFD0000,0xC8FEF3E6,0x86331221,0x00000000 + .long 0x3FFD0000,0xCFC98330,0xB4000C70,0x00000000 + .long 0x3FFD0000,0xD6807AA1,0x102C5BF9,0x00000000 + .long 0x3FFD0000,0xDD2399BC,0x31252AA3,0x00000000 + .long 0x3FFD0000,0xE3B2A855,0x6B8FC517,0x00000000 + .long 0x3FFD0000,0xEA2D764F,0x64315989,0x00000000 + .long 0x3FFD0000,0xF3BF5BF8,0xBAD1A21D,0x00000000 + .long 0x3FFE0000,0x801CE39E,0x0D205C9A,0x00000000 + .long 0x3FFE0000,0x8630A2DA,0xDA1ED066,0x00000000 + .long 0x3FFE0000,0x8C1AD445,0xF3E09B8C,0x00000000 + .long 0x3FFE0000,0x91DB8F16,0x64F350E2,0x00000000 + .long 0x3FFE0000,0x97731420,0x365E538C,0x00000000 + .long 0x3FFE0000,0x9CE1C8E6,0xA0B8CDBA,0x00000000 + .long 0x3FFE0000,0xA22832DB,0xCADAAE09,0x00000000 + .long 0x3FFE0000,0xA746F2DD,0xB7602294,0x00000000 + .long 0x3FFE0000,0xAC3EC0FB,0x997DD6A2,0x00000000 + .long 0x3FFE0000,0xB110688A,0xEBDC6F6A,0x00000000 + .long 0x3FFE0000,0xB5BCC490,0x59ECC4B0,0x00000000 + .long 0x3FFE0000,0xBA44BC7D,0xD470782F,0x00000000 + .long 0x3FFE0000,0xBEA94144,0xFD049AAC,0x00000000 + .long 0x3FFE0000,0xC2EB4ABB,0x661628B6,0x00000000 + .long 0x3FFE0000,0xC70BD54C,0xE602EE14,0x00000000 + .long 0x3FFE0000,0xCD000549,0xADEC7159,0x00000000 + .long 0x3FFE0000,0xD48457D2,0xD8EA4EA3,0x00000000 + .long 0x3FFE0000,0xDB948DA7,0x12DECE3B,0x00000000 + .long 0x3FFE0000,0xE23855F9,0x69E8096A,0x00000000 + .long 0x3FFE0000,0xE8771129,0xC4353259,0x00000000 + .long 0x3FFE0000,0xEE57C16E,0x0D379C0D,0x00000000 + .long 0x3FFE0000,0xF3E10211,0xA87C3779,0x00000000 + .long 0x3FFE0000,0xF919039D,0x758B8D41,0x00000000 + .long 0x3FFE0000,0xFE058B8F,0x64935FB3,0x00000000 + .long 0x3FFF0000,0x8155FB49,0x7B685D04,0x00000000 + .long 0x3FFF0000,0x83889E35,0x49D108E1,0x00000000 + .long 0x3FFF0000,0x859CFA76,0x511D724B,0x00000000 + .long 0x3FFF0000,0x87952ECF,0xFF8131E7,0x00000000 + .long 0x3FFF0000,0x89732FD1,0x9557641B,0x00000000 + .long 0x3FFF0000,0x8B38CAD1,0x01932A35,0x00000000 + .long 0x3FFF0000,0x8CE7A8D8,0x301EE6B5,0x00000000 + .long 0x3FFF0000,0x8F46A39E,0x2EAE5281,0x00000000 + .long 0x3FFF0000,0x922DA7D7,0x91888487,0x00000000 + .long 0x3FFF0000,0x94D19FCB,0xDEDF5241,0x00000000 + .long 0x3FFF0000,0x973AB944,0x19D2A08B,0x00000000 + .long 0x3FFF0000,0x996FF00E,0x08E10B96,0x00000000 + .long 0x3FFF0000,0x9B773F95,0x12321DA7,0x00000000 + .long 0x3FFF0000,0x9D55CC32,0x0F935624,0x00000000 + .long 0x3FFF0000,0x9F100575,0x006CC571,0x00000000 + .long 0x3FFF0000,0xA0A9C290,0xD97CC06C,0x00000000 + .long 0x3FFF0000,0xA22659EB,0xEBC0630A,0x00000000 + .long 0x3FFF0000,0xA388B4AF,0xF6EF0EC9,0x00000000 + .long 0x3FFF0000,0xA4D35F10,0x61D292C4,0x00000000 + .long 0x3FFF0000,0xA60895DC,0xFBE3187E,0x00000000 + .long 0x3FFF0000,0xA72A51DC,0x7367BEAC,0x00000000 + .long 0x3FFF0000,0xA83A5153,0x0956168F,0x00000000 + .long 0x3FFF0000,0xA93A2007,0x7539546E,0x00000000 + .long 0x3FFF0000,0xAA9E7245,0x023B2605,0x00000000 + .long 0x3FFF0000,0xAC4C84BA,0x6FE4D58F,0x00000000 + .long 0x3FFF0000,0xADCE4A4A,0x606B9712,0x00000000 + .long 0x3FFF0000,0xAF2A2DCD,0x8D263C9C,0x00000000 + .long 0x3FFF0000,0xB0656F81,0xF22265C7,0x00000000 + .long 0x3FFF0000,0xB1846515,0x0F71496A,0x00000000 + .long 0x3FFF0000,0xB28AAA15,0x6F9ADA35,0x00000000 + .long 0x3FFF0000,0xB37B44FF,0x3766B895,0x00000000 + .long 0x3FFF0000,0xB458C3DC,0xE9630433,0x00000000 + .long 0x3FFF0000,0xB525529D,0x562246BD,0x00000000 + .long 0x3FFF0000,0xB5E2CCA9,0x5F9D88CC,0x00000000 + .long 0x3FFF0000,0xB692CADA,0x7ACA1ADA,0x00000000 + .long 0x3FFF0000,0xB736AEA7,0xA6925838,0x00000000 + .long 0x3FFF0000,0xB7CFAB28,0x7E9F7B36,0x00000000 + .long 0x3FFF0000,0xB85ECC66,0xCB219835,0x00000000 + .long 0x3FFF0000,0xB8E4FD5A,0x20A593DA,0x00000000 + .long 0x3FFF0000,0xB99F41F6,0x4AFF9BB5,0x00000000 + .long 0x3FFF0000,0xBA7F1E17,0x842BBE7B,0x00000000 + .long 0x3FFF0000,0xBB471285,0x7637E17D,0x00000000 + .long 0x3FFF0000,0xBBFABE8A,0x4788DF6F,0x00000000 + .long 0x3FFF0000,0xBC9D0FAD,0x2B689D79,0x00000000 + .long 0x3FFF0000,0xBD306A39,0x471ECD86,0x00000000 + .long 0x3FFF0000,0xBDB6C731,0x856AF18A,0x00000000 + .long 0x3FFF0000,0xBE31CAC5,0x02E80D70,0x00000000 + .long 0x3FFF0000,0xBEA2D55C,0xE33194E2,0x00000000 + .long 0x3FFF0000,0xBF0B10B7,0xC03128F0,0x00000000 + .long 0x3FFF0000,0xBF6B7A18,0xDACB778D,0x00000000 + .long 0x3FFF0000,0xBFC4EA46,0x63FA18F6,0x00000000 + .long 0x3FFF0000,0xC0181BDE,0x8B89A454,0x00000000 + .long 0x3FFF0000,0xC065B066,0xCFBF6439,0x00000000 + .long 0x3FFF0000,0xC0AE345F,0x56340AE6,0x00000000 + .long 0x3FFF0000,0xC0F22291,0x9CB9E6A7,0x00000000 + + .set X,FP_SCR1 + .set XDCARE,X+2 + .set XFRAC,X+4 + .set XFRACLO,X+8 + + .set ATANF,FP_SCR2 + .set ATANFHI,ATANF+4 + .set ATANFLO,ATANF+8 + + + | xref t_frcinx + |xref t_extdnrm + + .global satand +satand: +|--ENTRY POINT FOR ATAN(X) FOR DENORMALIZED ARGUMENT + + bra t_extdnrm + + .global satan +satan: +|--ENTRY POINT FOR ATAN(X), HERE X IS FINITE, NON-ZERO, AND NOT NAN'S + + fmovex (%a0),%fp0 | ...LOAD INPUT + + movel (%a0),%d0 + movew 4(%a0),%d0 + fmovex %fp0,X(%a6) + andil #0x7FFFFFFF,%d0 + + cmpil #0x3FFB8000,%d0 | ...|X| >= 1/16? + bges ATANOK1 + bra ATANSM + +ATANOK1: + cmpil #0x4002FFFF,%d0 | ...|X| < 16 ? + bles ATANMAIN + bra ATANBIG + + +|--THE MOST LIKELY CASE, |X| IN [1/16, 16). WE USE TABLE TECHNIQUE +|--THE IDEA IS ATAN(X) = ATAN(F) + ATAN( [X-F] / [1+XF] ). +|--SO IF F IS CHOSEN TO BE CLOSE TO X AND ATAN(F) IS STORED IN +|--A TABLE, ALL WE NEED IS TO APPROXIMATE ATAN(U) WHERE +|--U = (X-F)/(1+XF) IS SMALL (REMEMBER F IS CLOSE TO X). IT IS +|--TRUE THAT A DIVIDE IS NOW NEEDED, BUT THE APPROXIMATION FOR +|--ATAN(U) IS A VERY SHORT POLYNOMIAL AND THE INDEXING TO +|--FETCH F AND SAVING OF REGISTERS CAN BE ALL HIDED UNDER THE +|--DIVIDE. IN THE END THIS METHOD IS MUCH FASTER THAN A TRADITIONAL +|--ONE. NOTE ALSO THAT THE TRADITIONAL SCHEME THAT APPROXIMATE +|--ATAN(X) DIRECTLY WILL NEED TO USE A RATIONAL APPROXIMATION +|--(DIVISION NEEDED) ANYWAY BECAUSE A POLYNOMIAL APPROXIMATION +|--WILL INVOLVE A VERY LONG POLYNOMIAL. + +|--NOW WE SEE X AS +-2^K * 1.BBBBBBB....B <- 1. + 63 BITS +|--WE CHOSE F TO BE +-2^K * 1.BBBB1 +|--THAT IS IT MATCHES THE EXPONENT AND FIRST 5 BITS OF X, THE +|--SIXTH BITS IS SET TO BE 1. SINCE K = -4, -3, ..., 3, THERE +|--ARE ONLY 8 TIMES 16 = 2^7 = 128 |F|'S. SINCE ATAN(-|F|) IS +|-- -ATAN(|F|), WE NEED TO STORE ONLY ATAN(|F|). + +ATANMAIN: + + movew #0x0000,XDCARE(%a6) | ...CLEAN UP X JUST IN CASE + andil #0xF8000000,XFRAC(%a6) | ...FIRST 5 BITS + oril #0x04000000,XFRAC(%a6) | ...SET 6-TH BIT TO 1 + movel #0x00000000,XFRACLO(%a6) | ...LOCATION OF X IS NOW F + + fmovex %fp0,%fp1 | ...FP1 IS X + fmulx X(%a6),%fp1 | ...FP1 IS X*F, NOTE THAT X*F > 0 + fsubx X(%a6),%fp0 | ...FP0 IS X-F + fadds #0x3F800000,%fp1 | ...FP1 IS 1 + X*F + fdivx %fp1,%fp0 | ...FP0 IS U = (X-F)/(1+X*F) + +|--WHILE THE DIVISION IS TAKING ITS TIME, WE FETCH ATAN(|F|) +|--CREATE ATAN(F) AND STORE IT IN ATANF, AND +|--SAVE REGISTERS FP2. + + movel %d2,-(%a7) | ...SAVE d2 TEMPORARILY + movel %d0,%d2 | ...THE EXPO AND 16 BITS OF X + andil #0x00007800,%d0 | ...4 VARYING BITS OF F'S FRACTION + andil #0x7FFF0000,%d2 | ...EXPONENT OF F + subil #0x3FFB0000,%d2 | ...K+4 + asrl #1,%d2 + addl %d2,%d0 | ...THE 7 BITS IDENTIFYING F + asrl #7,%d0 | ...INDEX INTO TBL OF ATAN(|F|) + lea ATANTBL,%a1 + addal %d0,%a1 | ...ADDRESS OF ATAN(|F|) + movel (%a1)+,ATANF(%a6) + movel (%a1)+,ATANFHI(%a6) + movel (%a1)+,ATANFLO(%a6) | ...ATANF IS NOW ATAN(|F|) + movel X(%a6),%d0 | ...LOAD SIGN AND EXPO. AGAIN + andil #0x80000000,%d0 | ...SIGN(F) + orl %d0,ATANF(%a6) | ...ATANF IS NOW SIGN(F)*ATAN(|F|) + movel (%a7)+,%d2 | ...RESTORE d2 + +|--THAT'S ALL I HAVE TO DO FOR NOW, +|--BUT ALAS, THE DIVIDE IS STILL CRANKING! + +|--U IN FP0, WE ARE NOW READY TO COMPUTE ATAN(U) AS +|--U + A1*U*V*(A2 + V*(A3 + V)), V = U*U +|--THE POLYNOMIAL MAY LOOK STRANGE, BUT IS NEVERTHELESS CORRECT. +|--THE NATURAL FORM IS U + U*V*(A1 + V*(A2 + V*A3)) +|--WHAT WE HAVE HERE IS MERELY A1 = A3, A2 = A1/A3, A3 = A2/A3. +|--THE REASON FOR THIS REARRANGEMENT IS TO MAKE THE INDEPENDENT +|--PARTS A1*U*V AND (A2 + ... STUFF) MORE LOAD-BALANCED + + + fmovex %fp0,%fp1 + fmulx %fp1,%fp1 + fmoved ATANA3,%fp2 + faddx %fp1,%fp2 | ...A3+V + fmulx %fp1,%fp2 | ...V*(A3+V) + fmulx %fp0,%fp1 | ...U*V + faddd ATANA2,%fp2 | ...A2+V*(A3+V) + fmuld ATANA1,%fp1 | ...A1*U*V + fmulx %fp2,%fp1 | ...A1*U*V*(A2+V*(A3+V)) + + faddx %fp1,%fp0 | ...ATAN(U), FP1 RELEASED + fmovel %d1,%FPCR |restore users exceptions + faddx ATANF(%a6),%fp0 | ...ATAN(X) + bra t_frcinx + +ATANBORS: +|--|X| IS IN d0 IN COMPACT FORM. FP1, d0 SAVED. +|--FP0 IS X AND |X| <= 1/16 OR |X| >= 16. + cmpil #0x3FFF8000,%d0 + bgt ATANBIG | ...I.E. |X| >= 16 + +ATANSM: +|--|X| <= 1/16 +|--IF |X| < 2^(-40), RETURN X AS ANSWER. OTHERWISE, APPROXIMATE +|--ATAN(X) BY X + X*Y*(B1+Y*(B2+Y*(B3+Y*(B4+Y*(B5+Y*B6))))) +|--WHICH IS X + X*Y*( [B1+Z*(B3+Z*B5)] + [Y*(B2+Z*(B4+Z*B6)] ) +|--WHERE Y = X*X, AND Z = Y*Y. + + cmpil #0x3FD78000,%d0 + blt ATANTINY +|--COMPUTE POLYNOMIAL + fmulx %fp0,%fp0 | ...FP0 IS Y = X*X + + + movew #0x0000,XDCARE(%a6) + + fmovex %fp0,%fp1 + fmulx %fp1,%fp1 | ...FP1 IS Z = Y*Y + + fmoved ATANB6,%fp2 + fmoved ATANB5,%fp3 + + fmulx %fp1,%fp2 | ...Z*B6 + fmulx %fp1,%fp3 | ...Z*B5 + + faddd ATANB4,%fp2 | ...B4+Z*B6 + faddd ATANB3,%fp3 | ...B3+Z*B5 + + fmulx %fp1,%fp2 | ...Z*(B4+Z*B6) + fmulx %fp3,%fp1 | ...Z*(B3+Z*B5) + + faddd ATANB2,%fp2 | ...B2+Z*(B4+Z*B6) + faddd ATANB1,%fp1 | ...B1+Z*(B3+Z*B5) + + fmulx %fp0,%fp2 | ...Y*(B2+Z*(B4+Z*B6)) + fmulx X(%a6),%fp0 | ...X*Y + + faddx %fp2,%fp1 | ...[B1+Z*(B3+Z*B5)]+[Y*(B2+Z*(B4+Z*B6))] + + + fmulx %fp1,%fp0 | ...X*Y*([B1+Z*(B3+Z*B5)]+[Y*(B2+Z*(B4+Z*B6))]) + + fmovel %d1,%FPCR |restore users exceptions + faddx X(%a6),%fp0 + + bra t_frcinx + +ATANTINY: +|--|X| < 2^(-40), ATAN(X) = X + movew #0x0000,XDCARE(%a6) + + fmovel %d1,%FPCR |restore users exceptions + fmovex X(%a6),%fp0 |last inst - possible exception set + + bra t_frcinx + +ATANBIG: +|--IF |X| > 2^(100), RETURN SIGN(X)*(PI/2 - TINY). OTHERWISE, +|--RETURN SIGN(X)*PI/2 + ATAN(-1/X). + cmpil #0x40638000,%d0 + bgt ATANHUGE + +|--APPROXIMATE ATAN(-1/X) BY +|--X'+X'*Y*(C1+Y*(C2+Y*(C3+Y*(C4+Y*C5)))), X' = -1/X, Y = X'*X' +|--THIS CAN BE RE-WRITTEN AS +|--X'+X'*Y*( [C1+Z*(C3+Z*C5)] + [Y*(C2+Z*C4)] ), Z = Y*Y. + + fmoves #0xBF800000,%fp1 | ...LOAD -1 + fdivx %fp0,%fp1 | ...FP1 IS -1/X + + +|--DIVIDE IS STILL CRANKING + + fmovex %fp1,%fp0 | ...FP0 IS X' + fmulx %fp0,%fp0 | ...FP0 IS Y = X'*X' + fmovex %fp1,X(%a6) | ...X IS REALLY X' + + fmovex %fp0,%fp1 + fmulx %fp1,%fp1 | ...FP1 IS Z = Y*Y + + fmoved ATANC5,%fp3 + fmoved ATANC4,%fp2 + + fmulx %fp1,%fp3 | ...Z*C5 + fmulx %fp1,%fp2 | ...Z*B4 + + faddd ATANC3,%fp3 | ...C3+Z*C5 + faddd ATANC2,%fp2 | ...C2+Z*C4 + + fmulx %fp3,%fp1 | ...Z*(C3+Z*C5), FP3 RELEASED + fmulx %fp0,%fp2 | ...Y*(C2+Z*C4) + + faddd ATANC1,%fp1 | ...C1+Z*(C3+Z*C5) + fmulx X(%a6),%fp0 | ...X'*Y + + faddx %fp2,%fp1 | ...[Y*(C2+Z*C4)]+[C1+Z*(C3+Z*C5)] + + + fmulx %fp1,%fp0 | ...X'*Y*([B1+Z*(B3+Z*B5)] +| ... +[Y*(B2+Z*(B4+Z*B6))]) + faddx X(%a6),%fp0 + + fmovel %d1,%FPCR |restore users exceptions + + btstb #7,(%a0) + beqs pos_big + +neg_big: + faddx NPIBY2,%fp0 + bra t_frcinx + +pos_big: + faddx PPIBY2,%fp0 + bra t_frcinx + +ATANHUGE: +|--RETURN SIGN(X)*(PIBY2 - TINY) = SIGN(X)*PIBY2 - SIGN(X)*TINY + btstb #7,(%a0) + beqs pos_huge + +neg_huge: + fmovex NPIBY2,%fp0 + fmovel %d1,%fpcr + fsubx NTINY,%fp0 + bra t_frcinx + +pos_huge: + fmovex PPIBY2,%fp0 + fmovel %d1,%fpcr + fsubx PTINY,%fp0 + bra t_frcinx + + |end diff --git a/arch/m68k/fpsp040/satanh.S b/arch/m68k/fpsp040/satanh.S new file mode 100644 index 000000000..ba91f77a7 --- /dev/null +++ b/arch/m68k/fpsp040/satanh.S @@ -0,0 +1,103 @@ +| +| satanh.sa 3.3 12/19/90 +| +| The entry point satanh computes the inverse +| hyperbolic tangent of +| an input argument; satanhd does the same except for denormalized +| input. +| +| Input: Double-extended number X in location pointed to +| by address register a0. +| +| Output: The value arctanh(X) returned in floating-point register Fp0. +| +| Accuracy and Monotonicity: The returned result is within 3 ulps in +| 64 significant bit, i.e. within 0.5001 ulp to 53 bits if the +| result is subsequently rounded to double precision. The +| result is provably monotonic in double precision. +| +| Speed: The program satanh takes approximately 270 cycles. +| +| Algorithm: +| +| ATANH +| 1. If |X| >= 1, go to 3. +| +| 2. (|X| < 1) Calculate atanh(X) by +| sgn := sign(X) +| y := |X| +| z := 2y/(1-y) +| atanh(X) := sgn * (1/2) * logp1(z) +| Exit. +| +| 3. If |X| > 1, go to 5. +| +| 4. (|X| = 1) Generate infinity with an appropriate sign and +| divide-by-zero by +| sgn := sign(X) +| atan(X) := sgn / (+0). +| Exit. +| +| 5. (|X| > 1) Generate an invalid operation by 0 * infinity. +| Exit. +| + +| Copyright (C) Motorola, Inc. 1990 +| All Rights Reserved +| +| For details on the license for this file, please see the +| file, README, in this same directory. + +|satanh idnt 2,1 | Motorola 040 Floating Point Software Package + + |section 8 + + |xref t_dz + |xref t_operr + |xref t_frcinx + |xref t_extdnrm + |xref slognp1 + + .global satanhd +satanhd: +|--ATANH(X) = X FOR DENORMALIZED X + + bra t_extdnrm + + .global satanh +satanh: + movel (%a0),%d0 + movew 4(%a0),%d0 + andil #0x7FFFFFFF,%d0 + cmpil #0x3FFF8000,%d0 + bges ATANHBIG + +|--THIS IS THE USUAL CASE, |X| < 1 +|--Y = |X|, Z = 2Y/(1-Y), ATANH(X) = SIGN(X) * (1/2) * LOG1P(Z). + + fabsx (%a0),%fp0 | ...Y = |X| + fmovex %fp0,%fp1 + fnegx %fp1 | ...-Y + faddx %fp0,%fp0 | ...2Y + fadds #0x3F800000,%fp1 | ...1-Y + fdivx %fp1,%fp0 | ...2Y/(1-Y) + movel (%a0),%d0 + andil #0x80000000,%d0 + oril #0x3F000000,%d0 | ...SIGN(X)*HALF + movel %d0,-(%sp) + + fmovemx %fp0-%fp0,(%a0) | ...overwrite input + movel %d1,-(%sp) + clrl %d1 + bsr slognp1 | ...LOG1P(Z) + fmovel (%sp)+,%fpcr + fmuls (%sp)+,%fp0 + bra t_frcinx + +ATANHBIG: + fabsx (%a0),%fp0 | ...|X| + fcmps #0x3F800000,%fp0 + fbgt t_operr + bra t_dz + + |end diff --git a/arch/m68k/fpsp040/scale.S b/arch/m68k/fpsp040/scale.S new file mode 100644 index 000000000..04829dd4f --- /dev/null +++ b/arch/m68k/fpsp040/scale.S @@ -0,0 +1,370 @@ +| +| scale.sa 3.3 7/30/91 +| +| The entry point sSCALE computes the destination operand +| scaled by the source operand. If the absolute value of +| the source operand is (>= 2^14) an overflow or underflow +| is returned. +| +| The entry point sscale is called from do_func to emulate +| the fscale unimplemented instruction. +| +| Input: Double-extended destination operand in FPTEMP, +| double-extended source operand in ETEMP. +| +| Output: The function returns scale(X,Y) to fp0. +| +| Modifies: fp0. +| +| Algorithm: +| +| Copyright (C) Motorola, Inc. 1990 +| All Rights Reserved +| +| For details on the license for this file, please see the +| file, README, in this same directory. + +|SCALE idnt 2,1 | Motorola 040 Floating Point Software Package + + |section 8 + +#include "fpsp.h" + + |xref t_ovfl2 + |xref t_unfl + |xref round + |xref t_resdnrm + +SRC_BNDS: .short 0x3fff,0x400c + +| +| This entry point is used by the unimplemented instruction exception +| handler. +| +| +| +| FSCALE +| + .global sscale +sscale: + fmovel #0,%fpcr |clr user enabled exc + clrl %d1 + movew FPTEMP(%a6),%d1 |get dest exponent + smi L_SCR1(%a6) |use L_SCR1 to hold sign + andil #0x7fff,%d1 |strip sign + movew ETEMP(%a6),%d0 |check src bounds + andiw #0x7fff,%d0 |clr sign bit + cmp2w SRC_BNDS,%d0 + bccs src_in + cmpiw #0x400c,%d0 |test for too large + bge src_out +| +| The source input is below 1, so we check for denormalized numbers +| and set unfl. +| +src_small: + moveb DTAG(%a6),%d0 + andib #0xe0,%d0 + tstb %d0 + beqs no_denorm + st STORE_FLG(%a6) |dest already contains result + orl #unfl_mask,USER_FPSR(%a6) |set UNFL +den_done: + leal FPTEMP(%a6),%a0 + bra t_resdnrm +no_denorm: + fmovel USER_FPCR(%a6),%FPCR + fmovex FPTEMP(%a6),%fp0 |simply return dest + rts + + +| +| Source is within 2^14 range. To perform the int operation, +| move it to d0. +| +src_in: + fmovex ETEMP(%a6),%fp0 |move in src for int + fmovel #rz_mode,%fpcr |force rz for src conversion + fmovel %fp0,%d0 |int src to d0 + fmovel #0,%FPSR |clr status from above + tstw ETEMP(%a6) |check src sign + blt src_neg +| +| Source is positive. Add the src to the dest exponent. +| The result can be denormalized, if src = 0, or overflow, +| if the result of the add sets a bit in the upper word. +| +src_pos: + tstw %d1 |check for denorm + beq dst_dnrm + addl %d0,%d1 |add src to dest exp + beqs denorm |if zero, result is denorm + cmpil #0x7fff,%d1 |test for overflow + bges ovfl + tstb L_SCR1(%a6) + beqs spos_pos + orw #0x8000,%d1 +spos_pos: + movew %d1,FPTEMP(%a6) |result in FPTEMP + fmovel USER_FPCR(%a6),%FPCR + fmovex FPTEMP(%a6),%fp0 |write result to fp0 + rts +ovfl: + tstb L_SCR1(%a6) + beqs sovl_pos + orw #0x8000,%d1 +sovl_pos: + movew FPTEMP(%a6),ETEMP(%a6) |result in ETEMP + movel FPTEMP_HI(%a6),ETEMP_HI(%a6) + movel FPTEMP_LO(%a6),ETEMP_LO(%a6) + bra t_ovfl2 + +denorm: + tstb L_SCR1(%a6) + beqs den_pos + orw #0x8000,%d1 +den_pos: + tstl FPTEMP_HI(%a6) |check j bit + blts nden_exit |if set, not denorm + movew %d1,ETEMP(%a6) |input expected in ETEMP + movel FPTEMP_HI(%a6),ETEMP_HI(%a6) + movel FPTEMP_LO(%a6),ETEMP_LO(%a6) + orl #unfl_bit,USER_FPSR(%a6) |set unfl + leal ETEMP(%a6),%a0 + bra t_resdnrm +nden_exit: + movew %d1,FPTEMP(%a6) |result in FPTEMP + fmovel USER_FPCR(%a6),%FPCR + fmovex FPTEMP(%a6),%fp0 |write result to fp0 + rts + +| +| Source is negative. Add the src to the dest exponent. +| (The result exponent will be reduced). The result can be +| denormalized. +| +src_neg: + addl %d0,%d1 |add src to dest + beqs denorm |if zero, result is denorm + blts fix_dnrm |if negative, result is +| ;needing denormalization + tstb L_SCR1(%a6) + beqs sneg_pos + orw #0x8000,%d1 +sneg_pos: + movew %d1,FPTEMP(%a6) |result in FPTEMP + fmovel USER_FPCR(%a6),%FPCR + fmovex FPTEMP(%a6),%fp0 |write result to fp0 + rts + + +| +| The result exponent is below denorm value. Test for catastrophic +| underflow and force zero if true. If not, try to shift the +| mantissa right until a zero exponent exists. +| +fix_dnrm: + cmpiw #0xffc0,%d1 |lower bound for normalization + blt fix_unfl |if lower, catastrophic unfl + movew %d1,%d0 |use d0 for exp + movel %d2,-(%a7) |free d2 for norm + movel FPTEMP_HI(%a6),%d1 + movel FPTEMP_LO(%a6),%d2 + clrl L_SCR2(%a6) +fix_loop: + addw #1,%d0 |drive d0 to 0 + lsrl #1,%d1 |while shifting the + roxrl #1,%d2 |mantissa to the right + bccs no_carry + st L_SCR2(%a6) |use L_SCR2 to capture inex +no_carry: + tstw %d0 |it is finished when + blts fix_loop |d0 is zero or the mantissa + tstb L_SCR2(%a6) + beqs tst_zero + orl #unfl_inx_mask,USER_FPSR(%a6) +| ;set unfl, aunfl, ainex +| +| Test for zero. If zero, simply use fmove to return +/- zero +| to the fpu. +| +tst_zero: + clrw FPTEMP_EX(%a6) + tstb L_SCR1(%a6) |test for sign + beqs tst_con + orw #0x8000,FPTEMP_EX(%a6) |set sign bit +tst_con: + movel %d1,FPTEMP_HI(%a6) + movel %d2,FPTEMP_LO(%a6) + movel (%a7)+,%d2 + tstl %d1 + bnes not_zero + tstl FPTEMP_LO(%a6) + bnes not_zero +| +| Result is zero. Check for rounding mode to set lsb. If the +| mode is rp, and the zero is positive, return smallest denorm. +| If the mode is rm, and the zero is negative, return smallest +| negative denorm. +| + btstb #5,FPCR_MODE(%a6) |test if rm or rp + beqs no_dir + btstb #4,FPCR_MODE(%a6) |check which one + beqs zer_rm +zer_rp: + tstb L_SCR1(%a6) |check sign + bnes no_dir |if set, neg op, no inc + movel #1,FPTEMP_LO(%a6) |set lsb + bras sm_dnrm +zer_rm: + tstb L_SCR1(%a6) |check sign + beqs no_dir |if clr, neg op, no inc + movel #1,FPTEMP_LO(%a6) |set lsb + orl #neg_mask,USER_FPSR(%a6) |set N + bras sm_dnrm +no_dir: + fmovel USER_FPCR(%a6),%FPCR + fmovex FPTEMP(%a6),%fp0 |use fmove to set cc's + rts + +| +| The rounding mode changed the zero to a smallest denorm. Call +| t_resdnrm with exceptional operand in ETEMP. +| +sm_dnrm: + movel FPTEMP_EX(%a6),ETEMP_EX(%a6) + movel FPTEMP_HI(%a6),ETEMP_HI(%a6) + movel FPTEMP_LO(%a6),ETEMP_LO(%a6) + leal ETEMP(%a6),%a0 + bra t_resdnrm + +| +| Result is still denormalized. +| +not_zero: + orl #unfl_mask,USER_FPSR(%a6) |set unfl + tstb L_SCR1(%a6) |check for sign + beqs fix_exit + orl #neg_mask,USER_FPSR(%a6) |set N +fix_exit: + bras sm_dnrm + + +| +| The result has underflowed to zero. Return zero and set +| unfl, aunfl, and ainex. +| +fix_unfl: + orl #unfl_inx_mask,USER_FPSR(%a6) + btstb #5,FPCR_MODE(%a6) |test if rm or rp + beqs no_dir2 + btstb #4,FPCR_MODE(%a6) |check which one + beqs zer_rm2 +zer_rp2: + tstb L_SCR1(%a6) |check sign + bnes no_dir2 |if set, neg op, no inc + clrl FPTEMP_EX(%a6) + clrl FPTEMP_HI(%a6) + movel #1,FPTEMP_LO(%a6) |set lsb + bras sm_dnrm |return smallest denorm +zer_rm2: + tstb L_SCR1(%a6) |check sign + beqs no_dir2 |if clr, neg op, no inc + movew #0x8000,FPTEMP_EX(%a6) + clrl FPTEMP_HI(%a6) + movel #1,FPTEMP_LO(%a6) |set lsb + orl #neg_mask,USER_FPSR(%a6) |set N + bra sm_dnrm |return smallest denorm + +no_dir2: + tstb L_SCR1(%a6) + bges pos_zero +neg_zero: + clrl FP_SCR1(%a6) |clear the exceptional operand + clrl FP_SCR1+4(%a6) |for gen_except. + clrl FP_SCR1+8(%a6) + fmoves #0x80000000,%fp0 + rts +pos_zero: + clrl FP_SCR1(%a6) |clear the exceptional operand + clrl FP_SCR1+4(%a6) |for gen_except. + clrl FP_SCR1+8(%a6) + fmoves #0x00000000,%fp0 + rts + +| +| The destination is a denormalized number. It must be handled +| by first shifting the bits in the mantissa until it is normalized, +| then adding the remainder of the source to the exponent. +| +dst_dnrm: + moveml %d2/%d3,-(%a7) + movew FPTEMP_EX(%a6),%d1 + movel FPTEMP_HI(%a6),%d2 + movel FPTEMP_LO(%a6),%d3 +dst_loop: + tstl %d2 |test for normalized result + blts dst_norm |exit loop if so + tstl %d0 |otherwise, test shift count + beqs dst_fin |if zero, shifting is done + subil #1,%d0 |dec src + lsll #1,%d3 + roxll #1,%d2 + bras dst_loop +| +| Destination became normalized. Simply add the remaining +| portion of the src to the exponent. +| +dst_norm: + addw %d0,%d1 |dst is normalized; add src + tstb L_SCR1(%a6) + beqs dnrm_pos + orl #0x8000,%d1 +dnrm_pos: + movemw %d1,FPTEMP_EX(%a6) + moveml %d2,FPTEMP_HI(%a6) + moveml %d3,FPTEMP_LO(%a6) + fmovel USER_FPCR(%a6),%FPCR + fmovex FPTEMP(%a6),%fp0 + moveml (%a7)+,%d2/%d3 + rts + +| +| Destination remained denormalized. Call t_excdnrm with +| exceptional operand in ETEMP. +| +dst_fin: + tstb L_SCR1(%a6) |check for sign + beqs dst_exit + orl #neg_mask,USER_FPSR(%a6) |set N + orl #0x8000,%d1 +dst_exit: + movemw %d1,ETEMP_EX(%a6) + moveml %d2,ETEMP_HI(%a6) + moveml %d3,ETEMP_LO(%a6) + orl #unfl_mask,USER_FPSR(%a6) |set unfl + moveml (%a7)+,%d2/%d3 + leal ETEMP(%a6),%a0 + bra t_resdnrm + +| +| Source is outside of 2^14 range. Test the sign and branch +| to the appropriate exception handler. +| +src_out: + tstb L_SCR1(%a6) + beqs scro_pos + orl #0x8000,%d1 +scro_pos: + movel FPTEMP_HI(%a6),ETEMP_HI(%a6) + movel FPTEMP_LO(%a6),ETEMP_LO(%a6) + tstw ETEMP(%a6) + blts res_neg +res_pos: + movew %d1,ETEMP(%a6) |result in ETEMP + bra t_ovfl2 +res_neg: + movew %d1,ETEMP(%a6) |result in ETEMP + leal ETEMP(%a6),%a0 + bra t_unfl + |end diff --git a/arch/m68k/fpsp040/scosh.S b/arch/m68k/fpsp040/scosh.S new file mode 100644 index 000000000..07d3a4d7c --- /dev/null +++ b/arch/m68k/fpsp040/scosh.S @@ -0,0 +1,131 @@ +| +| scosh.sa 3.1 12/10/90 +| +| The entry point sCosh computes the hyperbolic cosine of +| an input argument; sCoshd does the same except for denormalized +| input. +| +| Input: Double-extended number X in location pointed to +| by address register a0. +| +| Output: The value cosh(X) returned in floating-point register Fp0. +| +| Accuracy and Monotonicity: The returned result is within 3 ulps in +| 64 significant bit, i.e. within 0.5001 ulp to 53 bits if the +| result is subsequently rounded to double precision. The +| result is provably monotonic in double precision. +| +| Speed: The program sCOSH takes approximately 250 cycles. +| +| Algorithm: +| +| COSH +| 1. If |X| > 16380 log2, go to 3. +| +| 2. (|X| <= 16380 log2) Cosh(X) is obtained by the formulae +| y = |X|, z = exp(Y), and +| cosh(X) = (1/2)*( z + 1/z ). +| Exit. +| +| 3. (|X| > 16380 log2). If |X| > 16480 log2, go to 5. +| +| 4. (16380 log2 < |X| <= 16480 log2) +| cosh(X) = sign(X) * exp(|X|)/2. +| However, invoking exp(|X|) may cause premature overflow. +| Thus, we calculate sinh(X) as follows: +| Y := |X| +| Fact := 2**(16380) +| Y' := Y - 16381 log2 +| cosh(X) := Fact * exp(Y'). +| Exit. +| +| 5. (|X| > 16480 log2) sinh(X) must overflow. Return +| Huge*Huge to generate overflow and an infinity with +| the appropriate sign. Huge is the largest finite number in +| extended format. Exit. +| +| + +| Copyright (C) Motorola, Inc. 1990 +| All Rights Reserved +| +| For details on the license for this file, please see the +| file, README, in this same directory. + +|SCOSH idnt 2,1 | Motorola 040 Floating Point Software Package + + |section 8 + + |xref t_ovfl + |xref t_frcinx + |xref setox + +T1: .long 0x40C62D38,0xD3D64634 | ... 16381 LOG2 LEAD +T2: .long 0x3D6F90AE,0xB1E75CC7 | ... 16381 LOG2 TRAIL + +TWO16380: .long 0x7FFB0000,0x80000000,0x00000000,0x00000000 + + .global scoshd +scoshd: +|--COSH(X) = 1 FOR DENORMALIZED X + + fmoves #0x3F800000,%fp0 + + fmovel %d1,%FPCR + fadds #0x00800000,%fp0 + bra t_frcinx + + .global scosh +scosh: + fmovex (%a0),%fp0 | ...LOAD INPUT + + movel (%a0),%d0 + movew 4(%a0),%d0 + andil #0x7FFFFFFF,%d0 + cmpil #0x400CB167,%d0 + bgts COSHBIG + +|--THIS IS THE USUAL CASE, |X| < 16380 LOG2 +|--COSH(X) = (1/2) * ( EXP(X) + 1/EXP(X) ) + + fabsx %fp0 | ...|X| + + movel %d1,-(%sp) + clrl %d1 + fmovemx %fp0-%fp0,(%a0) |pass parameter to setox + bsr setox | ...FP0 IS EXP(|X|) + fmuls #0x3F000000,%fp0 | ...(1/2)EXP(|X|) + movel (%sp)+,%d1 + + fmoves #0x3E800000,%fp1 | ...(1/4) + fdivx %fp0,%fp1 | ...1/(2 EXP(|X|)) + + fmovel %d1,%FPCR + faddx %fp1,%fp0 + + bra t_frcinx + +COSHBIG: + cmpil #0x400CB2B3,%d0 + bgts COSHHUGE + + fabsx %fp0 + fsubd T1(%pc),%fp0 | ...(|X|-16381LOG2_LEAD) + fsubd T2(%pc),%fp0 | ...|X| - 16381 LOG2, ACCURATE + + movel %d1,-(%sp) + clrl %d1 + fmovemx %fp0-%fp0,(%a0) + bsr setox + fmovel (%sp)+,%fpcr + + fmulx TWO16380(%pc),%fp0 + bra t_frcinx + +COSHHUGE: + fmovel #0,%fpsr |clr N bit if set by source + bclrb #7,(%a0) |always return positive value + fmovemx (%a0),%fp0-%fp0 + bra t_ovfl + + |end diff --git a/arch/m68k/fpsp040/setox.S b/arch/m68k/fpsp040/setox.S new file mode 100644 index 000000000..f1acf7e36 --- /dev/null +++ b/arch/m68k/fpsp040/setox.S @@ -0,0 +1,864 @@ +| +| setox.sa 3.1 12/10/90 +| +| The entry point setox computes the exponential of a value. +| setoxd does the same except the input value is a denormalized +| number. setoxm1 computes exp(X)-1, and setoxm1d computes +| exp(X)-1 for denormalized X. +| +| INPUT +| ----- +| Double-extended value in memory location pointed to by address +| register a0. +| +| OUTPUT +| ------ +| exp(X) or exp(X)-1 returned in floating-point register fp0. +| +| ACCURACY and MONOTONICITY +| ------------------------- +| The returned result is within 0.85 ulps in 64 significant bit, i.e. +| within 0.5001 ulp to 53 bits if the result is subsequently rounded +| to double precision. The result is provably monotonic in double +| precision. +| +| SPEED +| ----- +| Two timings are measured, both in the copy-back mode. The +| first one is measured when the function is invoked the first time +| (so the instructions and data are not in cache), and the +| second one is measured when the function is reinvoked at the same +| input argument. +| +| The program setox takes approximately 210/190 cycles for input +| argument X whose magnitude is less than 16380 log2, which +| is the usual situation. For the less common arguments, +| depending on their values, the program may run faster or slower -- +| but no worse than 10% slower even in the extreme cases. +| +| The program setoxm1 takes approximately ??? / ??? cycles for input +| argument X, 0.25 <= |X| < 70log2. For |X| < 0.25, it takes +| approximately ??? / ??? cycles. For the less common arguments, +| depending on their values, the program may run faster or slower -- +| but no worse than 10% slower even in the extreme cases. +| +| ALGORITHM and IMPLEMENTATION NOTES +| ---------------------------------- +| +| setoxd +| ------ +| Step 1. Set ans := 1.0 +| +| Step 2. Return ans := ans + sign(X)*2^(-126). Exit. +| Notes: This will always generate one exception -- inexact. +| +| +| setox +| ----- +| +| Step 1. Filter out extreme cases of input argument. +| 1.1 If |X| >= 2^(-65), go to Step 1.3. +| 1.2 Go to Step 7. +| 1.3 If |X| < 16380 log(2), go to Step 2. +| 1.4 Go to Step 8. +| Notes: The usual case should take the branches 1.1 -> 1.3 -> 2. +| To avoid the use of floating-point comparisons, a +| compact representation of |X| is used. This format is a +| 32-bit integer, the upper (more significant) 16 bits are +| the sign and biased exponent field of |X|; the lower 16 +| bits are the 16 most significant fraction (including the +| explicit bit) bits of |X|. Consequently, the comparisons +| in Steps 1.1 and 1.3 can be performed by integer comparison. +| Note also that the constant 16380 log(2) used in Step 1.3 +| is also in the compact form. Thus taking the branch +| to Step 2 guarantees |X| < 16380 log(2). There is no harm +| to have a small number of cases where |X| is less than, +| but close to, 16380 log(2) and the branch to Step 9 is +| taken. +| +| Step 2. Calculate N = round-to-nearest-int( X * 64/log2 ). +| 2.1 Set AdjFlag := 0 (indicates the branch 1.3 -> 2 was taken) +| 2.2 N := round-to-nearest-integer( X * 64/log2 ). +| 2.3 Calculate J = N mod 64; so J = 0,1,2,..., or 63. +| 2.4 Calculate M = (N - J)/64; so N = 64M + J. +| 2.5 Calculate the address of the stored value of 2^(J/64). +| 2.6 Create the value Scale = 2^M. +| Notes: The calculation in 2.2 is really performed by +| +| Z := X * constant +| N := round-to-nearest-integer(Z) +| +| where +| +| constant := single-precision( 64/log 2 ). +| +| Using a single-precision constant avoids memory access. +| Another effect of using a single-precision "constant" is +| that the calculated value Z is +| +| Z = X*(64/log2)*(1+eps), |eps| <= 2^(-24). +| +| This error has to be considered later in Steps 3 and 4. +| +| Step 3. Calculate X - N*log2/64. +| 3.1 R := X + N*L1, where L1 := single-precision(-log2/64). +| 3.2 R := R + N*L2, L2 := extended-precision(-log2/64 - L1). +| Notes: a) The way L1 and L2 are chosen ensures L1+L2 approximate +| the value -log2/64 to 88 bits of accuracy. +| b) N*L1 is exact because N is no longer than 22 bits and +| L1 is no longer than 24 bits. +| c) The calculation X+N*L1 is also exact due to cancellation. +| Thus, R is practically X+N(L1+L2) to full 64 bits. +| d) It is important to estimate how large can |R| be after +| Step 3.2. +| +| N = rnd-to-int( X*64/log2 (1+eps) ), |eps|<=2^(-24) +| X*64/log2 (1+eps) = N + f, |f| <= 0.5 +| X*64/log2 - N = f - eps*X 64/log2 +| X - N*log2/64 = f*log2/64 - eps*X +| +| +| Now |X| <= 16446 log2, thus +| +| |X - N*log2/64| <= (0.5 + 16446/2^(18))*log2/64 +| <= 0.57 log2/64. +| This bound will be used in Step 4. +| +| Step 4. Approximate exp(R)-1 by a polynomial +| p = R + R*R*(A1 + R*(A2 + R*(A3 + R*(A4 + R*A5)))) +| Notes: a) In order to reduce memory access, the coefficients are +| made as "short" as possible: A1 (which is 1/2), A4 and A5 +| are single precision; A2 and A3 are double precision. +| b) Even with the restrictions above, +| |p - (exp(R)-1)| < 2^(-68.8) for all |R| <= 0.0062. +| Note that 0.0062 is slightly bigger than 0.57 log2/64. +| c) To fully utilize the pipeline, p is separated into +| two independent pieces of roughly equal complexities +| p = [ R + R*S*(A2 + S*A4) ] + +| [ S*(A1 + S*(A3 + S*A5)) ] +| where S = R*R. +| +| Step 5. Compute 2^(J/64)*exp(R) = 2^(J/64)*(1+p) by +| ans := T + ( T*p + t) +| where T and t are the stored values for 2^(J/64). +| Notes: 2^(J/64) is stored as T and t where T+t approximates +| 2^(J/64) to roughly 85 bits; T is in extended precision +| and t is in single precision. Note also that T is rounded +| to 62 bits so that the last two bits of T are zero. The +| reason for such a special form is that T-1, T-2, and T-8 +| will all be exact --- a property that will give much +| more accurate computation of the function EXPM1. +| +| Step 6. Reconstruction of exp(X) +| exp(X) = 2^M * 2^(J/64) * exp(R). +| 6.1 If AdjFlag = 0, go to 6.3 +| 6.2 ans := ans * AdjScale +| 6.3 Restore the user FPCR +| 6.4 Return ans := ans * Scale. Exit. +| Notes: If AdjFlag = 0, we have X = Mlog2 + Jlog2/64 + R, +| |M| <= 16380, and Scale = 2^M. Moreover, exp(X) will +| neither overflow nor underflow. If AdjFlag = 1, that +| means that +| X = (M1+M)log2 + Jlog2/64 + R, |M1+M| >= 16380. +| Hence, exp(X) may overflow or underflow or neither. +| When that is the case, AdjScale = 2^(M1) where M1 is +| approximately M. Thus 6.2 will never cause over/underflow. +| Possible exception in 6.4 is overflow or underflow. +| The inexact exception is not generated in 6.4. Although +| one can argue that the inexact flag should always be +| raised, to simulate that exception cost to much than the +| flag is worth in practical uses. +| +| Step 7. Return 1 + X. +| 7.1 ans := X +| 7.2 Restore user FPCR. +| 7.3 Return ans := 1 + ans. Exit +| Notes: For non-zero X, the inexact exception will always be +| raised by 7.3. That is the only exception raised by 7.3. +| Note also that we use the FMOVEM instruction to move X +| in Step 7.1 to avoid unnecessary trapping. (Although +| the FMOVEM may not seem relevant since X is normalized, +| the precaution will be useful in the library version of +| this code where the separate entry for denormalized inputs +| will be done away with.) +| +| Step 8. Handle exp(X) where |X| >= 16380log2. +| 8.1 If |X| > 16480 log2, go to Step 9. +| (mimic 2.2 - 2.6) +| 8.2 N := round-to-integer( X * 64/log2 ) +| 8.3 Calculate J = N mod 64, J = 0,1,...,63 +| 8.4 K := (N-J)/64, M1 := truncate(K/2), M = K-M1, AdjFlag := 1. +| 8.5 Calculate the address of the stored value 2^(J/64). +| 8.6 Create the values Scale = 2^M, AdjScale = 2^M1. +| 8.7 Go to Step 3. +| Notes: Refer to notes for 2.2 - 2.6. +| +| Step 9. Handle exp(X), |X| > 16480 log2. +| 9.1 If X < 0, go to 9.3 +| 9.2 ans := Huge, go to 9.4 +| 9.3 ans := Tiny. +| 9.4 Restore user FPCR. +| 9.5 Return ans := ans * ans. Exit. +| Notes: Exp(X) will surely overflow or underflow, depending on +| X's sign. "Huge" and "Tiny" are respectively large/tiny +| extended-precision numbers whose square over/underflow +| with an inexact result. Thus, 9.5 always raises the +| inexact together with either overflow or underflow. +| +| +| setoxm1d +| -------- +| +| Step 1. Set ans := 0 +| +| Step 2. Return ans := X + ans. Exit. +| Notes: This will return X with the appropriate rounding +| precision prescribed by the user FPCR. +| +| setoxm1 +| ------- +| +| Step 1. Check |X| +| 1.1 If |X| >= 1/4, go to Step 1.3. +| 1.2 Go to Step 7. +| 1.3 If |X| < 70 log(2), go to Step 2. +| 1.4 Go to Step 10. +| Notes: The usual case should take the branches 1.1 -> 1.3 -> 2. +| However, it is conceivable |X| can be small very often +| because EXPM1 is intended to evaluate exp(X)-1 accurately +| when |X| is small. For further details on the comparisons, +| see the notes on Step 1 of setox. +| +| Step 2. Calculate N = round-to-nearest-int( X * 64/log2 ). +| 2.1 N := round-to-nearest-integer( X * 64/log2 ). +| 2.2 Calculate J = N mod 64; so J = 0,1,2,..., or 63. +| 2.3 Calculate M = (N - J)/64; so N = 64M + J. +| 2.4 Calculate the address of the stored value of 2^(J/64). +| 2.5 Create the values Sc = 2^M and OnebySc := -2^(-M). +| Notes: See the notes on Step 2 of setox. +| +| Step 3. Calculate X - N*log2/64. +| 3.1 R := X + N*L1, where L1 := single-precision(-log2/64). +| 3.2 R := R + N*L2, L2 := extended-precision(-log2/64 - L1). +| Notes: Applying the analysis of Step 3 of setox in this case +| shows that |R| <= 0.0055 (note that |X| <= 70 log2 in +| this case). +| +| Step 4. Approximate exp(R)-1 by a polynomial +| p = R+R*R*(A1+R*(A2+R*(A3+R*(A4+R*(A5+R*A6))))) +| Notes: a) In order to reduce memory access, the coefficients are +| made as "short" as possible: A1 (which is 1/2), A5 and A6 +| are single precision; A2, A3 and A4 are double precision. +| b) Even with the restriction above, +| |p - (exp(R)-1)| < |R| * 2^(-72.7) +| for all |R| <= 0.0055. +| c) To fully utilize the pipeline, p is separated into +| two independent pieces of roughly equal complexity +| p = [ R*S*(A2 + S*(A4 + S*A6)) ] + +| [ R + S*(A1 + S*(A3 + S*A5)) ] +| where S = R*R. +| +| Step 5. Compute 2^(J/64)*p by +| p := T*p +| where T and t are the stored values for 2^(J/64). +| Notes: 2^(J/64) is stored as T and t where T+t approximates +| 2^(J/64) to roughly 85 bits; T is in extended precision +| and t is in single precision. Note also that T is rounded +| to 62 bits so that the last two bits of T are zero. The +| reason for such a special form is that T-1, T-2, and T-8 +| will all be exact --- a property that will be exploited +| in Step 6 below. The total relative error in p is no +| bigger than 2^(-67.7) compared to the final result. +| +| Step 6. Reconstruction of exp(X)-1 +| exp(X)-1 = 2^M * ( 2^(J/64) + p - 2^(-M) ). +| 6.1 If M <= 63, go to Step 6.3. +| 6.2 ans := T + (p + (t + OnebySc)). Go to 6.6 +| 6.3 If M >= -3, go to 6.5. +| 6.4 ans := (T + (p + t)) + OnebySc. Go to 6.6 +| 6.5 ans := (T + OnebySc) + (p + t). +| 6.6 Restore user FPCR. +| 6.7 Return ans := Sc * ans. Exit. +| Notes: The various arrangements of the expressions give accurate +| evaluations. +| +| Step 7. exp(X)-1 for |X| < 1/4. +| 7.1 If |X| >= 2^(-65), go to Step 9. +| 7.2 Go to Step 8. +| +| Step 8. Calculate exp(X)-1, |X| < 2^(-65). +| 8.1 If |X| < 2^(-16312), goto 8.3 +| 8.2 Restore FPCR; return ans := X - 2^(-16382). Exit. +| 8.3 X := X * 2^(140). +| 8.4 Restore FPCR; ans := ans - 2^(-16382). +| Return ans := ans*2^(140). Exit +| Notes: The idea is to return "X - tiny" under the user +| precision and rounding modes. To avoid unnecessary +| inefficiency, we stay away from denormalized numbers the +| best we can. For |X| >= 2^(-16312), the straightforward +| 8.2 generates the inexact exception as the case warrants. +| +| Step 9. Calculate exp(X)-1, |X| < 1/4, by a polynomial +| p = X + X*X*(B1 + X*(B2 + ... + X*B12)) +| Notes: a) In order to reduce memory access, the coefficients are +| made as "short" as possible: B1 (which is 1/2), B9 to B12 +| are single precision; B3 to B8 are double precision; and +| B2 is double extended. +| b) Even with the restriction above, +| |p - (exp(X)-1)| < |X| 2^(-70.6) +| for all |X| <= 0.251. +| Note that 0.251 is slightly bigger than 1/4. +| c) To fully preserve accuracy, the polynomial is computed +| as X + ( S*B1 + Q ) where S = X*X and +| Q = X*S*(B2 + X*(B3 + ... + X*B12)) +| d) To fully utilize the pipeline, Q is separated into +| two independent pieces of roughly equal complexity +| Q = [ X*S*(B2 + S*(B4 + ... + S*B12)) ] + +| [ S*S*(B3 + S*(B5 + ... + S*B11)) ] +| +| Step 10. Calculate exp(X)-1 for |X| >= 70 log 2. +| 10.1 If X >= 70log2 , exp(X) - 1 = exp(X) for all practical +| purposes. Therefore, go to Step 1 of setox. +| 10.2 If X <= -70log2, exp(X) - 1 = -1 for all practical purposes. +| ans := -1 +| Restore user FPCR +| Return ans := ans + 2^(-126). Exit. +| Notes: 10.2 will always create an inexact and return -1 + tiny +| in the user rounding precision and mode. +| +| + +| Copyright (C) Motorola, Inc. 1990 +| All Rights Reserved +| +| For details on the license for this file, please see the +| file, README, in this same directory. + +|setox idnt 2,1 | Motorola 040 Floating Point Software Package + + |section 8 + +#include "fpsp.h" + +L2: .long 0x3FDC0000,0x82E30865,0x4361C4C6,0x00000000 + +EXPA3: .long 0x3FA55555,0x55554431 +EXPA2: .long 0x3FC55555,0x55554018 + +HUGE: .long 0x7FFE0000,0xFFFFFFFF,0xFFFFFFFF,0x00000000 +TINY: .long 0x00010000,0xFFFFFFFF,0xFFFFFFFF,0x00000000 + +EM1A4: .long 0x3F811111,0x11174385 +EM1A3: .long 0x3FA55555,0x55554F5A + +EM1A2: .long 0x3FC55555,0x55555555,0x00000000,0x00000000 + +EM1B8: .long 0x3EC71DE3,0xA5774682 +EM1B7: .long 0x3EFA01A0,0x19D7CB68 + +EM1B6: .long 0x3F2A01A0,0x1A019DF3 +EM1B5: .long 0x3F56C16C,0x16C170E2 + +EM1B4: .long 0x3F811111,0x11111111 +EM1B3: .long 0x3FA55555,0x55555555 + +EM1B2: .long 0x3FFC0000,0xAAAAAAAA,0xAAAAAAAB + .long 0x00000000 + +TWO140: .long 0x48B00000,0x00000000 +TWON140: .long 0x37300000,0x00000000 + +EXPTBL: + .long 0x3FFF0000,0x80000000,0x00000000,0x00000000 + .long 0x3FFF0000,0x8164D1F3,0xBC030774,0x9F841A9B + .long 0x3FFF0000,0x82CD8698,0xAC2BA1D8,0x9FC1D5B9 + .long 0x3FFF0000,0x843A28C3,0xACDE4048,0xA0728369 + .long 0x3FFF0000,0x85AAC367,0xCC487B14,0x1FC5C95C + .long 0x3FFF0000,0x871F6196,0x9E8D1010,0x1EE85C9F + .long 0x3FFF0000,0x88980E80,0x92DA8528,0x9FA20729 + .long 0x3FFF0000,0x8A14D575,0x496EFD9C,0xA07BF9AF + .long 0x3FFF0000,0x8B95C1E3,0xEA8BD6E8,0xA0020DCF + .long 0x3FFF0000,0x8D1ADF5B,0x7E5BA9E4,0x205A63DA + .long 0x3FFF0000,0x8EA4398B,0x45CD53C0,0x1EB70051 + .long 0x3FFF0000,0x9031DC43,0x1466B1DC,0x1F6EB029 + .long 0x3FFF0000,0x91C3D373,0xAB11C338,0xA0781494 + .long 0x3FFF0000,0x935A2B2F,0x13E6E92C,0x9EB319B0 + .long 0x3FFF0000,0x94F4EFA8,0xFEF70960,0x2017457D + .long 0x3FFF0000,0x96942D37,0x20185A00,0x1F11D537 + .long 0x3FFF0000,0x9837F051,0x8DB8A970,0x9FB952DD + .long 0x3FFF0000,0x99E04593,0x20B7FA64,0x1FE43087 + .long 0x3FFF0000,0x9B8D39B9,0xD54E5538,0x1FA2A818 + .long 0x3FFF0000,0x9D3ED9A7,0x2CFFB750,0x1FDE494D + .long 0x3FFF0000,0x9EF53260,0x91A111AC,0x20504890 + .long 0x3FFF0000,0xA0B0510F,0xB9714FC4,0xA073691C + .long 0x3FFF0000,0xA2704303,0x0C496818,0x1F9B7A05 + .long 0x3FFF0000,0xA43515AE,0x09E680A0,0xA0797126 + .long 0x3FFF0000,0xA5FED6A9,0xB15138EC,0xA071A140 + .long 0x3FFF0000,0xA7CD93B4,0xE9653568,0x204F62DA + .long 0x3FFF0000,0xA9A15AB4,0xEA7C0EF8,0x1F283C4A + .long 0x3FFF0000,0xAB7A39B5,0xA93ED338,0x9F9A7FDC + .long 0x3FFF0000,0xAD583EEA,0x42A14AC8,0xA05B3FAC + .long 0x3FFF0000,0xAF3B78AD,0x690A4374,0x1FDF2610 + .long 0x3FFF0000,0xB123F581,0xD2AC2590,0x9F705F90 + .long 0x3FFF0000,0xB311C412,0xA9112488,0x201F678A + .long 0x3FFF0000,0xB504F333,0xF9DE6484,0x1F32FB13 + .long 0x3FFF0000,0xB6FD91E3,0x28D17790,0x20038B30 + .long 0x3FFF0000,0xB8FBAF47,0x62FB9EE8,0x200DC3CC + .long 0x3FFF0000,0xBAFF5AB2,0x133E45FC,0x9F8B2AE6 + .long 0x3FFF0000,0xBD08A39F,0x580C36C0,0xA02BBF70 + .long 0x3FFF0000,0xBF1799B6,0x7A731084,0xA00BF518 + .long 0x3FFF0000,0xC12C4CCA,0x66709458,0xA041DD41 + .long 0x3FFF0000,0xC346CCDA,0x24976408,0x9FDF137B + .long 0x3FFF0000,0xC5672A11,0x5506DADC,0x201F1568 + .long 0x3FFF0000,0xC78D74C8,0xABB9B15C,0x1FC13A2E + .long 0x3FFF0000,0xC9B9BD86,0x6E2F27A4,0xA03F8F03 + .long 0x3FFF0000,0xCBEC14FE,0xF2727C5C,0x1FF4907D + .long 0x3FFF0000,0xCE248C15,0x1F8480E4,0x9E6E53E4 + .long 0x3FFF0000,0xD06333DA,0xEF2B2594,0x1FD6D45C + .long 0x3FFF0000,0xD2A81D91,0xF12AE45C,0xA076EDB9 + .long 0x3FFF0000,0xD4F35AAB,0xCFEDFA20,0x9FA6DE21 + .long 0x3FFF0000,0xD744FCCA,0xD69D6AF4,0x1EE69A2F + .long 0x3FFF0000,0xD99D15C2,0x78AFD7B4,0x207F439F + .long 0x3FFF0000,0xDBFBB797,0xDAF23754,0x201EC207 + .long 0x3FFF0000,0xDE60F482,0x5E0E9124,0x9E8BE175 + .long 0x3FFF0000,0xE0CCDEEC,0x2A94E110,0x20032C4B + .long 0x3FFF0000,0xE33F8972,0xBE8A5A50,0x2004DFF5 + .long 0x3FFF0000,0xE5B906E7,0x7C8348A8,0x1E72F47A + .long 0x3FFF0000,0xE8396A50,0x3C4BDC68,0x1F722F22 + .long 0x3FFF0000,0xEAC0C6E7,0xDD243930,0xA017E945 + .long 0x3FFF0000,0xED4F301E,0xD9942B84,0x1F401A5B + .long 0x3FFF0000,0xEFE4B99B,0xDCDAF5CC,0x9FB9A9E3 + .long 0x3FFF0000,0xF281773C,0x59FFB138,0x20744C05 + .long 0x3FFF0000,0xF5257D15,0x2486CC2C,0x1F773A19 + .long 0x3FFF0000,0xF7D0DF73,0x0AD13BB8,0x1FFE90D5 + .long 0x3FFF0000,0xFA83B2DB,0x722A033C,0xA041ED22 + .long 0x3FFF0000,0xFD3E0C0C,0xF486C174,0x1F853F3A + + .set ADJFLAG,L_SCR2 + .set SCALE,FP_SCR1 + .set ADJSCALE,FP_SCR2 + .set SC,FP_SCR3 + .set ONEBYSC,FP_SCR4 + + | xref t_frcinx + |xref t_extdnrm + |xref t_unfl + |xref t_ovfl + + .global setoxd +setoxd: +|--entry point for EXP(X), X is denormalized + movel (%a0),%d0 + andil #0x80000000,%d0 + oril #0x00800000,%d0 | ...sign(X)*2^(-126) + movel %d0,-(%sp) + fmoves #0x3F800000,%fp0 + fmovel %d1,%fpcr + fadds (%sp)+,%fp0 + bra t_frcinx + + .global setox +setox: +|--entry point for EXP(X), here X is finite, non-zero, and not NaN's + +|--Step 1. + movel (%a0),%d0 | ...load part of input X + andil #0x7FFF0000,%d0 | ...biased expo. of X + cmpil #0x3FBE0000,%d0 | ...2^(-65) + bges EXPC1 | ...normal case + bra EXPSM + +EXPC1: +|--The case |X| >= 2^(-65) + movew 4(%a0),%d0 | ...expo. and partial sig. of |X| + cmpil #0x400CB167,%d0 | ...16380 log2 trunc. 16 bits + blts EXPMAIN | ...normal case + bra EXPBIG + +EXPMAIN: +|--Step 2. +|--This is the normal branch: 2^(-65) <= |X| < 16380 log2. + fmovex (%a0),%fp0 | ...load input from (a0) + + fmovex %fp0,%fp1 + fmuls #0x42B8AA3B,%fp0 | ...64/log2 * X + fmovemx %fp2-%fp2/%fp3,-(%a7) | ...save fp2 + movel #0,ADJFLAG(%a6) + fmovel %fp0,%d0 | ...N = int( X * 64/log2 ) + lea EXPTBL,%a1 + fmovel %d0,%fp0 | ...convert to floating-format + + movel %d0,L_SCR1(%a6) | ...save N temporarily + andil #0x3F,%d0 | ...D0 is J = N mod 64 + lsll #4,%d0 + addal %d0,%a1 | ...address of 2^(J/64) + movel L_SCR1(%a6),%d0 + asrl #6,%d0 | ...D0 is M + addiw #0x3FFF,%d0 | ...biased expo. of 2^(M) + movew L2,L_SCR1(%a6) | ...prefetch L2, no need in CB + +EXPCONT1: +|--Step 3. +|--fp1,fp2 saved on the stack. fp0 is N, fp1 is X, +|--a0 points to 2^(J/64), D0 is biased expo. of 2^(M) + fmovex %fp0,%fp2 + fmuls #0xBC317218,%fp0 | ...N * L1, L1 = lead(-log2/64) + fmulx L2,%fp2 | ...N * L2, L1+L2 = -log2/64 + faddx %fp1,%fp0 | ...X + N*L1 + faddx %fp2,%fp0 | ...fp0 is R, reduced arg. +| MOVE.W #$3FA5,EXPA3 ...load EXPA3 in cache + +|--Step 4. +|--WE NOW COMPUTE EXP(R)-1 BY A POLYNOMIAL +|-- R + R*R*(A1 + R*(A2 + R*(A3 + R*(A4 + R*A5)))) +|--TO FULLY UTILIZE THE PIPELINE, WE COMPUTE S = R*R +|--[R+R*S*(A2+S*A4)] + [S*(A1+S*(A3+S*A5))] + + fmovex %fp0,%fp1 + fmulx %fp1,%fp1 | ...fp1 IS S = R*R + + fmoves #0x3AB60B70,%fp2 | ...fp2 IS A5 +| MOVE.W #0,2(%a1) ...load 2^(J/64) in cache + + fmulx %fp1,%fp2 | ...fp2 IS S*A5 + fmovex %fp1,%fp3 + fmuls #0x3C088895,%fp3 | ...fp3 IS S*A4 + + faddd EXPA3,%fp2 | ...fp2 IS A3+S*A5 + faddd EXPA2,%fp3 | ...fp3 IS A2+S*A4 + + fmulx %fp1,%fp2 | ...fp2 IS S*(A3+S*A5) + movew %d0,SCALE(%a6) | ...SCALE is 2^(M) in extended + clrw SCALE+2(%a6) + movel #0x80000000,SCALE+4(%a6) + clrl SCALE+8(%a6) + + fmulx %fp1,%fp3 | ...fp3 IS S*(A2+S*A4) + + fadds #0x3F000000,%fp2 | ...fp2 IS A1+S*(A3+S*A5) + fmulx %fp0,%fp3 | ...fp3 IS R*S*(A2+S*A4) + + fmulx %fp1,%fp2 | ...fp2 IS S*(A1+S*(A3+S*A5)) + faddx %fp3,%fp0 | ...fp0 IS R+R*S*(A2+S*A4), +| ...fp3 released + + fmovex (%a1)+,%fp1 | ...fp1 is lead. pt. of 2^(J/64) + faddx %fp2,%fp0 | ...fp0 is EXP(R) - 1 +| ...fp2 released + +|--Step 5 +|--final reconstruction process +|--EXP(X) = 2^M * ( 2^(J/64) + 2^(J/64)*(EXP(R)-1) ) + + fmulx %fp1,%fp0 | ...2^(J/64)*(Exp(R)-1) + fmovemx (%a7)+,%fp2-%fp2/%fp3 | ...fp2 restored + fadds (%a1),%fp0 | ...accurate 2^(J/64) + + faddx %fp1,%fp0 | ...2^(J/64) + 2^(J/64)*... + movel ADJFLAG(%a6),%d0 + +|--Step 6 + tstl %d0 + beqs NORMAL +ADJUST: + fmulx ADJSCALE(%a6),%fp0 +NORMAL: + fmovel %d1,%FPCR | ...restore user FPCR + fmulx SCALE(%a6),%fp0 | ...multiply 2^(M) + bra t_frcinx + +EXPSM: +|--Step 7 + fmovemx (%a0),%fp0-%fp0 | ...in case X is denormalized + fmovel %d1,%FPCR + fadds #0x3F800000,%fp0 | ...1+X in user mode + bra t_frcinx + +EXPBIG: +|--Step 8 + cmpil #0x400CB27C,%d0 | ...16480 log2 + bgts EXP2BIG +|--Steps 8.2 -- 8.6 + fmovex (%a0),%fp0 | ...load input from (a0) + + fmovex %fp0,%fp1 + fmuls #0x42B8AA3B,%fp0 | ...64/log2 * X + fmovemx %fp2-%fp2/%fp3,-(%a7) | ...save fp2 + movel #1,ADJFLAG(%a6) + fmovel %fp0,%d0 | ...N = int( X * 64/log2 ) + lea EXPTBL,%a1 + fmovel %d0,%fp0 | ...convert to floating-format + movel %d0,L_SCR1(%a6) | ...save N temporarily + andil #0x3F,%d0 | ...D0 is J = N mod 64 + lsll #4,%d0 + addal %d0,%a1 | ...address of 2^(J/64) + movel L_SCR1(%a6),%d0 + asrl #6,%d0 | ...D0 is K + movel %d0,L_SCR1(%a6) | ...save K temporarily + asrl #1,%d0 | ...D0 is M1 + subl %d0,L_SCR1(%a6) | ...a1 is M + addiw #0x3FFF,%d0 | ...biased expo. of 2^(M1) + movew %d0,ADJSCALE(%a6) | ...ADJSCALE := 2^(M1) + clrw ADJSCALE+2(%a6) + movel #0x80000000,ADJSCALE+4(%a6) + clrl ADJSCALE+8(%a6) + movel L_SCR1(%a6),%d0 | ...D0 is M + addiw #0x3FFF,%d0 | ...biased expo. of 2^(M) + bra EXPCONT1 | ...go back to Step 3 + +EXP2BIG: +|--Step 9 + fmovel %d1,%FPCR + movel (%a0),%d0 + bclrb #sign_bit,(%a0) | ...setox always returns positive + cmpil #0,%d0 + blt t_unfl + bra t_ovfl + + .global setoxm1d +setoxm1d: +|--entry point for EXPM1(X), here X is denormalized +|--Step 0. + bra t_extdnrm + + + .global setoxm1 +setoxm1: +|--entry point for EXPM1(X), here X is finite, non-zero, non-NaN + +|--Step 1. +|--Step 1.1 + movel (%a0),%d0 | ...load part of input X + andil #0x7FFF0000,%d0 | ...biased expo. of X + cmpil #0x3FFD0000,%d0 | ...1/4 + bges EM1CON1 | ...|X| >= 1/4 + bra EM1SM + +EM1CON1: +|--Step 1.3 +|--The case |X| >= 1/4 + movew 4(%a0),%d0 | ...expo. and partial sig. of |X| + cmpil #0x4004C215,%d0 | ...70log2 rounded up to 16 bits + bles EM1MAIN | ...1/4 <= |X| <= 70log2 + bra EM1BIG + +EM1MAIN: +|--Step 2. +|--This is the case: 1/4 <= |X| <= 70 log2. + fmovex (%a0),%fp0 | ...load input from (a0) + + fmovex %fp0,%fp1 + fmuls #0x42B8AA3B,%fp0 | ...64/log2 * X + fmovemx %fp2-%fp2/%fp3,-(%a7) | ...save fp2 +| MOVE.W #$3F81,EM1A4 ...prefetch in CB mode + fmovel %fp0,%d0 | ...N = int( X * 64/log2 ) + lea EXPTBL,%a1 + fmovel %d0,%fp0 | ...convert to floating-format + + movel %d0,L_SCR1(%a6) | ...save N temporarily + andil #0x3F,%d0 | ...D0 is J = N mod 64 + lsll #4,%d0 + addal %d0,%a1 | ...address of 2^(J/64) + movel L_SCR1(%a6),%d0 + asrl #6,%d0 | ...D0 is M + movel %d0,L_SCR1(%a6) | ...save a copy of M +| MOVE.W #$3FDC,L2 ...prefetch L2 in CB mode + +|--Step 3. +|--fp1,fp2 saved on the stack. fp0 is N, fp1 is X, +|--a0 points to 2^(J/64), D0 and a1 both contain M + fmovex %fp0,%fp2 + fmuls #0xBC317218,%fp0 | ...N * L1, L1 = lead(-log2/64) + fmulx L2,%fp2 | ...N * L2, L1+L2 = -log2/64 + faddx %fp1,%fp0 | ...X + N*L1 + faddx %fp2,%fp0 | ...fp0 is R, reduced arg. +| MOVE.W #$3FC5,EM1A2 ...load EM1A2 in cache + addiw #0x3FFF,%d0 | ...D0 is biased expo. of 2^M + +|--Step 4. +|--WE NOW COMPUTE EXP(R)-1 BY A POLYNOMIAL +|-- R + R*R*(A1 + R*(A2 + R*(A3 + R*(A4 + R*(A5 + R*A6))))) +|--TO FULLY UTILIZE THE PIPELINE, WE COMPUTE S = R*R +|--[R*S*(A2+S*(A4+S*A6))] + [R+S*(A1+S*(A3+S*A5))] + + fmovex %fp0,%fp1 + fmulx %fp1,%fp1 | ...fp1 IS S = R*R + + fmoves #0x3950097B,%fp2 | ...fp2 IS a6 +| MOVE.W #0,2(%a1) ...load 2^(J/64) in cache + + fmulx %fp1,%fp2 | ...fp2 IS S*A6 + fmovex %fp1,%fp3 + fmuls #0x3AB60B6A,%fp3 | ...fp3 IS S*A5 + + faddd EM1A4,%fp2 | ...fp2 IS A4+S*A6 + faddd EM1A3,%fp3 | ...fp3 IS A3+S*A5 + movew %d0,SC(%a6) | ...SC is 2^(M) in extended + clrw SC+2(%a6) + movel #0x80000000,SC+4(%a6) + clrl SC+8(%a6) + + fmulx %fp1,%fp2 | ...fp2 IS S*(A4+S*A6) + movel L_SCR1(%a6),%d0 | ...D0 is M + negw %d0 | ...D0 is -M + fmulx %fp1,%fp3 | ...fp3 IS S*(A3+S*A5) + addiw #0x3FFF,%d0 | ...biased expo. of 2^(-M) + faddd EM1A2,%fp2 | ...fp2 IS A2+S*(A4+S*A6) + fadds #0x3F000000,%fp3 | ...fp3 IS A1+S*(A3+S*A5) + + fmulx %fp1,%fp2 | ...fp2 IS S*(A2+S*(A4+S*A6)) + oriw #0x8000,%d0 | ...signed/expo. of -2^(-M) + movew %d0,ONEBYSC(%a6) | ...OnebySc is -2^(-M) + clrw ONEBYSC+2(%a6) + movel #0x80000000,ONEBYSC+4(%a6) + clrl ONEBYSC+8(%a6) + fmulx %fp3,%fp1 | ...fp1 IS S*(A1+S*(A3+S*A5)) +| ...fp3 released + + fmulx %fp0,%fp2 | ...fp2 IS R*S*(A2+S*(A4+S*A6)) + faddx %fp1,%fp0 | ...fp0 IS R+S*(A1+S*(A3+S*A5)) +| ...fp1 released + + faddx %fp2,%fp0 | ...fp0 IS EXP(R)-1 +| ...fp2 released + fmovemx (%a7)+,%fp2-%fp2/%fp3 | ...fp2 restored + +|--Step 5 +|--Compute 2^(J/64)*p + + fmulx (%a1),%fp0 | ...2^(J/64)*(Exp(R)-1) + +|--Step 6 +|--Step 6.1 + movel L_SCR1(%a6),%d0 | ...retrieve M + cmpil #63,%d0 + bles MLE63 +|--Step 6.2 M >= 64 + fmoves 12(%a1),%fp1 | ...fp1 is t + faddx ONEBYSC(%a6),%fp1 | ...fp1 is t+OnebySc + faddx %fp1,%fp0 | ...p+(t+OnebySc), fp1 released + faddx (%a1),%fp0 | ...T+(p+(t+OnebySc)) + bras EM1SCALE +MLE63: +|--Step 6.3 M <= 63 + cmpil #-3,%d0 + bges MGEN3 +MLTN3: +|--Step 6.4 M <= -4 + fadds 12(%a1),%fp0 | ...p+t + faddx (%a1),%fp0 | ...T+(p+t) + faddx ONEBYSC(%a6),%fp0 | ...OnebySc + (T+(p+t)) + bras EM1SCALE +MGEN3: +|--Step 6.5 -3 <= M <= 63 + fmovex (%a1)+,%fp1 | ...fp1 is T + fadds (%a1),%fp0 | ...fp0 is p+t + faddx ONEBYSC(%a6),%fp1 | ...fp1 is T+OnebySc + faddx %fp1,%fp0 | ...(T+OnebySc)+(p+t) + +EM1SCALE: +|--Step 6.6 + fmovel %d1,%FPCR + fmulx SC(%a6),%fp0 + + bra t_frcinx + +EM1SM: +|--Step 7 |X| < 1/4. + cmpil #0x3FBE0000,%d0 | ...2^(-65) + bges EM1POLY + +EM1TINY: +|--Step 8 |X| < 2^(-65) + cmpil #0x00330000,%d0 | ...2^(-16312) + blts EM12TINY +|--Step 8.2 + movel #0x80010000,SC(%a6) | ...SC is -2^(-16382) + movel #0x80000000,SC+4(%a6) + clrl SC+8(%a6) + fmovex (%a0),%fp0 + fmovel %d1,%FPCR + faddx SC(%a6),%fp0 + + bra t_frcinx + +EM12TINY: +|--Step 8.3 + fmovex (%a0),%fp0 + fmuld TWO140,%fp0 + movel #0x80010000,SC(%a6) + movel #0x80000000,SC+4(%a6) + clrl SC+8(%a6) + faddx SC(%a6),%fp0 + fmovel %d1,%FPCR + fmuld TWON140,%fp0 + + bra t_frcinx + +EM1POLY: +|--Step 9 exp(X)-1 by a simple polynomial + fmovex (%a0),%fp0 | ...fp0 is X + fmulx %fp0,%fp0 | ...fp0 is S := X*X + fmovemx %fp2-%fp2/%fp3,-(%a7) | ...save fp2 + fmoves #0x2F30CAA8,%fp1 | ...fp1 is B12 + fmulx %fp0,%fp1 | ...fp1 is S*B12 + fmoves #0x310F8290,%fp2 | ...fp2 is B11 + fadds #0x32D73220,%fp1 | ...fp1 is B10+S*B12 + + fmulx %fp0,%fp2 | ...fp2 is S*B11 + fmulx %fp0,%fp1 | ...fp1 is S*(B10 + ... + + fadds #0x3493F281,%fp2 | ...fp2 is B9+S*... + faddd EM1B8,%fp1 | ...fp1 is B8+S*... + + fmulx %fp0,%fp2 | ...fp2 is S*(B9+... + fmulx %fp0,%fp1 | ...fp1 is S*(B8+... + + faddd EM1B7,%fp2 | ...fp2 is B7+S*... + faddd EM1B6,%fp1 | ...fp1 is B6+S*... + + fmulx %fp0,%fp2 | ...fp2 is S*(B7+... + fmulx %fp0,%fp1 | ...fp1 is S*(B6+... + + faddd EM1B5,%fp2 | ...fp2 is B5+S*... + faddd EM1B4,%fp1 | ...fp1 is B4+S*... + + fmulx %fp0,%fp2 | ...fp2 is S*(B5+... + fmulx %fp0,%fp1 | ...fp1 is S*(B4+... + + faddd EM1B3,%fp2 | ...fp2 is B3+S*... + faddx EM1B2,%fp1 | ...fp1 is B2+S*... + + fmulx %fp0,%fp2 | ...fp2 is S*(B3+... + fmulx %fp0,%fp1 | ...fp1 is S*(B2+... + + fmulx %fp0,%fp2 | ...fp2 is S*S*(B3+...) + fmulx (%a0),%fp1 | ...fp1 is X*S*(B2... + + fmuls #0x3F000000,%fp0 | ...fp0 is S*B1 + faddx %fp2,%fp1 | ...fp1 is Q +| ...fp2 released + + fmovemx (%a7)+,%fp2-%fp2/%fp3 | ...fp2 restored + + faddx %fp1,%fp0 | ...fp0 is S*B1+Q +| ...fp1 released + + fmovel %d1,%FPCR + faddx (%a0),%fp0 + + bra t_frcinx + +EM1BIG: +|--Step 10 |X| > 70 log2 + movel (%a0),%d0 + cmpil #0,%d0 + bgt EXPC1 +|--Step 10.2 + fmoves #0xBF800000,%fp0 | ...fp0 is -1 + fmovel %d1,%FPCR + fadds #0x00800000,%fp0 | ...-1 + 2^(-126) + + bra t_frcinx + + |end diff --git a/arch/m68k/fpsp040/sgetem.S b/arch/m68k/fpsp040/sgetem.S new file mode 100644 index 000000000..d9234f4ae --- /dev/null +++ b/arch/m68k/fpsp040/sgetem.S @@ -0,0 +1,140 @@ +| +| sgetem.sa 3.1 12/10/90 +| +| The entry point sGETEXP returns the exponent portion +| of the input argument. The exponent bias is removed +| and the exponent value is returned as an extended +| precision number in fp0. sGETEXPD handles denormalized +| numbers. +| +| The entry point sGETMAN extracts the mantissa of the +| input argument. The mantissa is converted to an +| extended precision number and returned in fp0. The +| range of the result is [1.0 - 2.0). +| +| +| Input: Double-extended number X in the ETEMP space in +| the floating-point save stack. +| +| Output: The functions return exp(X) or man(X) in fp0. +| +| Modified: fp0. +| +| +| Copyright (C) Motorola, Inc. 1990 +| All Rights Reserved +| +| For details on the license for this file, please see the +| file, README, in this same directory. + +|SGETEM idnt 2,1 | Motorola 040 Floating Point Software Package + + |section 8 + +#include "fpsp.h" + + |xref nrm_set + +| +| This entry point is used by the unimplemented instruction exception +| handler. It points a0 to the input operand. +| +| +| +| SGETEXP +| + + .global sgetexp +sgetexp: + movew LOCAL_EX(%a0),%d0 |get the exponent + bclrl #15,%d0 |clear the sign bit + subw #0x3fff,%d0 |subtract off the bias + fmovew %d0,%fp0 |move the exp to fp0 + rts + + .global sgetexpd +sgetexpd: + bclrb #sign_bit,LOCAL_EX(%a0) + bsr nrm_set |normalize (exp will go negative) + movew LOCAL_EX(%a0),%d0 |load resulting exponent into d0 + subw #0x3fff,%d0 |subtract off the bias + fmovew %d0,%fp0 |move the exp to fp0 + rts +| +| +| This entry point is used by the unimplemented instruction exception +| handler. It points a0 to the input operand. +| +| +| +| SGETMAN +| +| +| For normalized numbers, leave the mantissa alone, simply load +| with an exponent of +/- $3fff. +| + .global sgetman +sgetman: + movel USER_FPCR(%a6),%d0 + andil #0xffffff00,%d0 |clear rounding precision and mode + fmovel %d0,%fpcr |this fpcr setting is used by the 882 + movew LOCAL_EX(%a0),%d0 |get the exp (really just want sign bit) + orw #0x7fff,%d0 |clear old exp + bclrl #14,%d0 |make it the new exp +-3fff + movew %d0,LOCAL_EX(%a0) |move the sign & exp back to fsave stack + fmovex (%a0),%fp0 |put new value back in fp0 + rts + +| +| For denormalized numbers, shift the mantissa until the j-bit = 1, +| then load the exponent with +/1 $3fff. +| + .global sgetmand +sgetmand: + movel LOCAL_HI(%a0),%d0 |load ms mant in d0 + movel LOCAL_LO(%a0),%d1 |load ls mant in d1 + bsr shft |shift mantissa bits till msbit is set + movel %d0,LOCAL_HI(%a0) |put ms mant back on stack + movel %d1,LOCAL_LO(%a0) |put ls mant back on stack + bras sgetman + +| +| SHFT +| +| Shifts the mantissa bits until msbit is set. +| input: +| ms mantissa part in d0 +| ls mantissa part in d1 +| output: +| shifted bits in d0 and d1 +shft: + tstl %d0 |if any bits set in ms mant + bnes upper |then branch +| ;else no bits set in ms mant + tstl %d1 |test if any bits set in ls mant + bnes cont |if set then continue + bras shft_end |else return +cont: + movel %d3,-(%a7) |save d3 + exg %d0,%d1 |shift ls mant to ms mant + bfffo %d0{#0:#32},%d3 |find first 1 in ls mant to d0 + lsll %d3,%d0 |shift first 1 to integer bit in ms mant + movel (%a7)+,%d3 |restore d3 + bras shft_end +upper: + + moveml %d3/%d5/%d6,-(%a7) |save registers + bfffo %d0{#0:#32},%d3 |find first 1 in ls mant to d0 + lsll %d3,%d0 |shift ms mant until j-bit is set + movel %d1,%d6 |save ls mant in d6 + lsll %d3,%d1 |shift ls mant by count + movel #32,%d5 + subl %d3,%d5 |sub 32 from shift for ls mant + lsrl %d5,%d6 |shift off all bits but those that will +| ;be shifted into ms mant + orl %d6,%d0 |shift the ls mant bits into the ms mant + moveml (%a7)+,%d3/%d5/%d6 |restore registers +shft_end: + rts + + |end diff --git a/arch/m68k/fpsp040/sint.S b/arch/m68k/fpsp040/sint.S new file mode 100644 index 000000000..0e92d4e5d --- /dev/null +++ b/arch/m68k/fpsp040/sint.S @@ -0,0 +1,246 @@ +| +| sint.sa 3.1 12/10/90 +| +| The entry point sINT computes the rounded integer +| equivalent of the input argument, sINTRZ computes +| the integer rounded to zero of the input argument. +| +| Entry points sint and sintrz are called from do_func +| to emulate the fint and fintrz unimplemented instructions, +| respectively. Entry point sintdo is used by bindec. +| +| Input: (Entry points sint and sintrz) Double-extended +| number X in the ETEMP space in the floating-point +| save stack. +| (Entry point sintdo) Double-extended number X in +| location pointed to by the address register a0. +| (Entry point sintd) Double-extended denormalized +| number X in the ETEMP space in the floating-point +| save stack. +| +| Output: The function returns int(X) or intrz(X) in fp0. +| +| Modifies: fp0. +| +| Algorithm: (sint and sintrz) +| +| 1. If exp(X) >= 63, return X. +| If exp(X) < 0, return +/- 0 or +/- 1, according to +| the rounding mode. +| +| 2. (X is in range) set rsc = 63 - exp(X). Unnormalize the +| result to the exponent $403e. +| +| 3. Round the result in the mode given in USER_FPCR. For +| sintrz, force round-to-zero mode. +| +| 4. Normalize the rounded result; store in fp0. +| +| For the denormalized cases, force the correct result +| for the given sign and rounding mode. +| +| Sign(X) +| RMODE + - +| ----- -------- +| RN +0 -0 +| RZ +0 -0 +| RM +0 -1 +| RP +1 -0 +| +| +| Copyright (C) Motorola, Inc. 1990 +| All Rights Reserved +| +| For details on the license for this file, please see the +| file, README, in this same directory. + +|SINT idnt 2,1 | Motorola 040 Floating Point Software Package + + |section 8 + +#include "fpsp.h" + + |xref dnrm_lp + |xref nrm_set + |xref round + |xref t_inx2 + |xref ld_pone + |xref ld_mone + |xref ld_pzero + |xref ld_mzero + |xref snzrinx + +| +| FINT +| + .global sint +sint: + bfextu FPCR_MODE(%a6){#2:#2},%d1 |use user's mode for rounding +| ;implicitly has extend precision +| ;in upper word. + movel %d1,L_SCR1(%a6) |save mode bits + bras sintexc + +| +| FINT with extended denorm inputs. +| + .global sintd +sintd: + btstb #5,FPCR_MODE(%a6) + beq snzrinx |if round nearest or round zero, +/- 0 + btstb #4,FPCR_MODE(%a6) + beqs rnd_mns +rnd_pls: + btstb #sign_bit,LOCAL_EX(%a0) + bnes sintmz + bsr ld_pone |if round plus inf and pos, answer is +1 + bra t_inx2 +rnd_mns: + btstb #sign_bit,LOCAL_EX(%a0) + beqs sintpz + bsr ld_mone |if round mns inf and neg, answer is -1 + bra t_inx2 +sintpz: + bsr ld_pzero + bra t_inx2 +sintmz: + bsr ld_mzero + bra t_inx2 + +| +| FINTRZ +| + .global sintrz +sintrz: + movel #1,L_SCR1(%a6) |use rz mode for rounding +| ;implicitly has extend precision +| ;in upper word. + bras sintexc +| +| SINTDO +| +| Input: a0 points to an IEEE extended format operand +| Output: fp0 has the result +| +| Exceptions: +| +| If the subroutine results in an inexact operation, the inx2 and +| ainx bits in the USER_FPSR are set. +| +| + .global sintdo +sintdo: + bfextu FPCR_MODE(%a6){#2:#2},%d1 |use user's mode for rounding +| ;implicitly has ext precision +| ;in upper word. + movel %d1,L_SCR1(%a6) |save mode bits +| +| Real work of sint is in sintexc +| +sintexc: + bclrb #sign_bit,LOCAL_EX(%a0) |convert to internal extended +| ;format + sne LOCAL_SGN(%a0) + cmpw #0x403e,LOCAL_EX(%a0) |check if (unbiased) exp > 63 + bgts out_rnge |branch if exp < 63 + cmpw #0x3ffd,LOCAL_EX(%a0) |check if (unbiased) exp < 0 + bgt in_rnge |if 63 >= exp > 0, do calc +| +| Input is less than zero. Restore sign, and check for directed +| rounding modes. L_SCR1 contains the rmode in the lower byte. +| +un_rnge: + btstb #1,L_SCR1+3(%a6) |check for rn and rz + beqs un_rnrz + tstb LOCAL_SGN(%a0) |check for sign + bnes un_rmrp_neg +| +| Sign is +. If rp, load +1.0, if rm, load +0.0 +| + cmpib #3,L_SCR1+3(%a6) |check for rp + beqs un_ldpone |if rp, load +1.0 + bsr ld_pzero |if rm, load +0.0 + bra t_inx2 +un_ldpone: + bsr ld_pone + bra t_inx2 +| +| Sign is -. If rm, load -1.0, if rp, load -0.0 +| +un_rmrp_neg: + cmpib #2,L_SCR1+3(%a6) |check for rm + beqs un_ldmone |if rm, load -1.0 + bsr ld_mzero |if rp, load -0.0 + bra t_inx2 +un_ldmone: + bsr ld_mone + bra t_inx2 +| +| Rmode is rn or rz; return signed zero +| +un_rnrz: + tstb LOCAL_SGN(%a0) |check for sign + bnes un_rnrz_neg + bsr ld_pzero + bra t_inx2 +un_rnrz_neg: + bsr ld_mzero + bra t_inx2 + +| +| Input is greater than 2^63. All bits are significant. Return +| the input. +| +out_rnge: + bfclr LOCAL_SGN(%a0){#0:#8} |change back to IEEE ext format + beqs intps + bsetb #sign_bit,LOCAL_EX(%a0) +intps: + fmovel %fpcr,-(%sp) + fmovel #0,%fpcr + fmovex LOCAL_EX(%a0),%fp0 |if exp > 63 +| ;then return X to the user +| ;there are no fraction bits + fmovel (%sp)+,%fpcr + rts + +in_rnge: +| ;shift off fraction bits + clrl %d0 |clear d0 - initial g,r,s for +| ;dnrm_lp + movel #0x403e,%d1 |set threshold for dnrm_lp +| ;assumes a0 points to operand + bsr dnrm_lp +| ;returns unnormalized number +| ;pointed by a0 +| ;output d0 supplies g,r,s +| ;used by round + movel L_SCR1(%a6),%d1 |use selected rounding mode +| +| + bsr round |round the unnorm based on users +| ;input a0 ptr to ext X +| ; d0 g,r,s bits +| ; d1 PREC/MODE info +| ;output a0 ptr to rounded result +| ;inexact flag set in USER_FPSR +| ;if initial grs set +| +| normalize the rounded result and store value in fp0 +| + bsr nrm_set |normalize the unnorm +| ;Input: a0 points to operand to +| ;be normalized +| ;Output: a0 points to normalized +| ;result + bfclr LOCAL_SGN(%a0){#0:#8} + beqs nrmrndp + bsetb #sign_bit,LOCAL_EX(%a0) |return to IEEE extended format +nrmrndp: + fmovel %fpcr,-(%sp) + fmovel #0,%fpcr + fmovex LOCAL_EX(%a0),%fp0 |move result to fp0 + fmovel (%sp)+,%fpcr + rts + + |end diff --git a/arch/m68k/fpsp040/skeleton.S b/arch/m68k/fpsp040/skeleton.S new file mode 100644 index 000000000..31a9c634c --- /dev/null +++ b/arch/m68k/fpsp040/skeleton.S @@ -0,0 +1,513 @@ +| +| skeleton.sa 3.2 4/26/91 +| +| This file contains code that is system dependent and will +| need to be modified to install the FPSP. +| +| Each entry point for exception 'xxxx' begins with a 'jmp fpsp_xxxx'. +| Put any target system specific handling that must be done immediately +| before the jump instruction. If there no handling necessary, then +| the 'fpsp_xxxx' handler entry point should be placed in the exception +| table so that the 'jmp' can be eliminated. If the FPSP determines that the +| exception is one that must be reported then there will be a +| return from the package by a 'jmp real_xxxx'. At that point +| the machine state will be identical to the state before +| the FPSP was entered. In particular, whatever condition +| that caused the exception will still be pending when the FPSP +| package returns. Thus, there will be system specific code +| to handle the exception. +| +| If the exception was completely handled by the package, then +| the return will be via a 'jmp fpsp_done'. Unless there is +| OS specific work to be done (such as handling a context switch or +| interrupt) the user program can be resumed via 'rte'. +| +| In the following skeleton code, some typical 'real_xxxx' handling +| code is shown. This code may need to be moved to an appropriate +| place in the target system, or rewritten. +| + +| Copyright (C) Motorola, Inc. 1990 +| All Rights Reserved +| +| For details on the license for this file, please see the +| file, README, in this same directory. + +| +| Modified for Linux-1.3.x by Jes Sorensen (jds@kom.auc.dk) +| + +#include +#include +#include + +|SKELETON idnt 2,1 | Motorola 040 Floating Point Software Package + + |section 15 +| +| The following counters are used for standalone testing +| + + |section 8 + +#include "fpsp.h" + + |xref b1238_fix + +| +| Divide by Zero exception +| +| All dz exceptions are 'real', hence no fpsp_dz entry point. +| + .global dz + .global real_dz +dz: +real_dz: + link %a6,#-LOCAL_SIZE + fsave -(%sp) + bclrb #E1,E_BYTE(%a6) + frestore (%sp)+ + unlk %a6 + + SAVE_ALL_INT + GET_CURRENT(%d0) + movel %sp,%sp@- | stack frame pointer argument + bsrl trap_c + addql #4,%sp + bral ret_from_exception + +| +| Inexact exception +| +| All inexact exceptions are real, but the 'real' handler +| will probably want to clear the pending exception. +| The provided code will clear the E3 exception (if pending), +| otherwise clear the E1 exception. The frestore is not really +| necessary for E1 exceptions. +| +| Code following the 'inex' label is to handle bug #1232. In this +| bug, if an E1 snan, ovfl, or unfl occurred, and the process was +| swapped out before taking the exception, the exception taken on +| return was inex, rather than the correct exception. The snan, ovfl, +| and unfl exception to be taken must not have been enabled. The +| fix is to check for E1, and the existence of one of snan, ovfl, +| or unfl bits set in the fpsr. If any of these are set, branch +| to the appropriate handler for the exception in the fpsr. Note +| that this fix is only for d43b parts, and is skipped if the +| version number is not $40. +| +| + .global real_inex + .global inex +inex: + link %a6,#-LOCAL_SIZE + fsave -(%sp) + cmpib #VER_40,(%sp) |test version number + bnes not_fmt40 + fmovel %fpsr,-(%sp) + btstb #E1,E_BYTE(%a6) |test for E1 set + beqs not_b1232 + btstb #snan_bit,2(%sp) |test for snan + beq inex_ckofl + addl #4,%sp + frestore (%sp)+ + unlk %a6 + bra snan +inex_ckofl: + btstb #ovfl_bit,2(%sp) |test for ovfl + beq inex_ckufl + addl #4,%sp + frestore (%sp)+ + unlk %a6 + bra ovfl +inex_ckufl: + btstb #unfl_bit,2(%sp) |test for unfl + beq not_b1232 + addl #4,%sp + frestore (%sp)+ + unlk %a6 + bra unfl + +| +| We do not have the bug 1232 case. Clean up the stack and call +| real_inex. +| +not_b1232: + addl #4,%sp + frestore (%sp)+ + unlk %a6 + +real_inex: + + link %a6,#-LOCAL_SIZE + fsave -(%sp) +not_fmt40: + bclrb #E3,E_BYTE(%a6) |clear and test E3 flag + beqs inex_cke1 +| +| Clear dirty bit on dest resister in the frame before branching +| to b1238_fix. +| + moveml %d0/%d1,USER_DA(%a6) + bfextu CMDREG1B(%a6){#6:#3},%d0 |get dest reg no + bclrb %d0,FPR_DIRTY_BITS(%a6) |clr dest dirty bit + bsrl b1238_fix |test for bug1238 case + moveml USER_DA(%a6),%d0/%d1 + bras inex_done +inex_cke1: + bclrb #E1,E_BYTE(%a6) +inex_done: + frestore (%sp)+ + unlk %a6 + + SAVE_ALL_INT + GET_CURRENT(%d0) + movel %sp,%sp@- | stack frame pointer argument + bsrl trap_c + addql #4,%sp + bral ret_from_exception + +| +| Overflow exception +| + |xref fpsp_ovfl + .global real_ovfl + .global ovfl +ovfl: + jmp fpsp_ovfl +real_ovfl: + + link %a6,#-LOCAL_SIZE + fsave -(%sp) + bclrb #E3,E_BYTE(%a6) |clear and test E3 flag + bnes ovfl_done + bclrb #E1,E_BYTE(%a6) +ovfl_done: + frestore (%sp)+ + unlk %a6 + + SAVE_ALL_INT + GET_CURRENT(%d0) + movel %sp,%sp@- | stack frame pointer argument + bsrl trap_c + addql #4,%sp + bral ret_from_exception + +| +| Underflow exception +| + |xref fpsp_unfl + .global real_unfl + .global unfl +unfl: + jmp fpsp_unfl +real_unfl: + + link %a6,#-LOCAL_SIZE + fsave -(%sp) + bclrb #E3,E_BYTE(%a6) |clear and test E3 flag + bnes unfl_done + bclrb #E1,E_BYTE(%a6) +unfl_done: + frestore (%sp)+ + unlk %a6 + + SAVE_ALL_INT + GET_CURRENT(%d0) + movel %sp,%sp@- | stack frame pointer argument + bsrl trap_c + addql #4,%sp + bral ret_from_exception + +| +| Signalling NAN exception +| + |xref fpsp_snan + .global real_snan + .global snan +snan: + jmp fpsp_snan +real_snan: + link %a6,#-LOCAL_SIZE + fsave -(%sp) + bclrb #E1,E_BYTE(%a6) |snan is always an E1 exception + frestore (%sp)+ + unlk %a6 + + SAVE_ALL_INT + GET_CURRENT(%d0) + movel %sp,%sp@- | stack frame pointer argument + bsrl trap_c + addql #4,%sp + bral ret_from_exception + +| +| Operand Error exception +| + |xref fpsp_operr + .global real_operr + .global operr +operr: + jmp fpsp_operr +real_operr: + link %a6,#-LOCAL_SIZE + fsave -(%sp) + bclrb #E1,E_BYTE(%a6) |operr is always an E1 exception + frestore (%sp)+ + unlk %a6 + + SAVE_ALL_INT + GET_CURRENT(%d0) + movel %sp,%sp@- | stack frame pointer argument + bsrl trap_c + addql #4,%sp + bral ret_from_exception + + +| +| BSUN exception +| +| This sample handler simply clears the nan bit in the FPSR. +| + |xref fpsp_bsun + .global real_bsun + .global bsun +bsun: + jmp fpsp_bsun +real_bsun: + link %a6,#-LOCAL_SIZE + fsave -(%sp) + bclrb #E1,E_BYTE(%a6) |bsun is always an E1 exception + fmovel %FPSR,-(%sp) + bclrb #nan_bit,(%sp) + fmovel (%sp)+,%FPSR + frestore (%sp)+ + unlk %a6 + + SAVE_ALL_INT + GET_CURRENT(%d0) + movel %sp,%sp@- | stack frame pointer argument + bsrl trap_c + addql #4,%sp + bral ret_from_exception + +| +| F-line exception +| +| A 'real' F-line exception is one that the FPSP isn't supposed to +| handle. E.g. an instruction with a co-processor ID that is not 1. +| +| + |xref fpsp_fline + .global real_fline + .global fline +fline: + jmp fpsp_fline +real_fline: + + SAVE_ALL_INT + GET_CURRENT(%d0) + movel %sp,%sp@- | stack frame pointer argument + bsrl trap_c + addql #4,%sp + bral ret_from_exception + +| +| Unsupported data type exception +| + |xref fpsp_unsupp + .global real_unsupp + .global unsupp +unsupp: + jmp fpsp_unsupp +real_unsupp: + link %a6,#-LOCAL_SIZE + fsave -(%sp) + bclrb #E1,E_BYTE(%a6) |unsupp is always an E1 exception + frestore (%sp)+ + unlk %a6 + + SAVE_ALL_INT + GET_CURRENT(%d0) + movel %sp,%sp@- | stack frame pointer argument + bsrl trap_c + addql #4,%sp + bral ret_from_exception + +| +| Trace exception +| + .global real_trace +real_trace: + | + bral trap + +| +| fpsp_fmt_error --- exit point for frame format error +| +| The fpu stack frame does not match the frames existing +| or planned at the time of this writing. The fpsp is +| unable to handle frame sizes not in the following +| version:size pairs: +| +| {4060, 4160} - busy frame +| {4028, 4130} - unimp frame +| {4000, 4100} - idle frame +| +| This entry point simply holds an f-line illegal value. +| Replace this with a call to your kernel panic code or +| code to handle future revisions of the fpu. +| + .global fpsp_fmt_error +fpsp_fmt_error: + + .long 0xf27f0000 |f-line illegal + +| +| fpsp_done --- FPSP exit point +| +| The exception has been handled by the package and we are ready +| to return to user mode, but there may be OS specific code +| to execute before we do. If there is, do it now. +| +| + + .global fpsp_done +fpsp_done: + btst #0x5,%sp@ | supervisor bit set in saved SR? + beq .Lnotkern + rte +.Lnotkern: + SAVE_ALL_INT + GET_CURRENT(%d0) + | deliver signals, reschedule etc.. + jra ret_from_exception + +| +| mem_write --- write to user or supervisor address space +| +| Writes to memory while in supervisor mode. copyout accomplishes +| this via a 'moves' instruction. copyout is a UNIX SVR3 (and later) function. +| If you don't have copyout, use the local copy of the function below. +| +| a0 - supervisor source address +| a1 - user destination address +| d0 - number of bytes to write (maximum count is 12) +| +| The supervisor source address is guaranteed to point into the supervisor +| stack. The result is that a UNIX +| process is allowed to sleep as a consequence of a page fault during +| copyout. The probability of a page fault is exceedingly small because +| the 68040 always reads the destination address and thus the page +| faults should have already been handled. +| +| If the EXC_SR shows that the exception was from supervisor space, +| then just do a dumb (and slow) memory move. In a UNIX environment +| there shouldn't be any supervisor mode floating point exceptions. +| + .global mem_write +mem_write: + btstb #5,EXC_SR(%a6) |check for supervisor state + beqs user_write +super_write: + moveb (%a0)+,(%a1)+ + subql #1,%d0 + bnes super_write + rts +user_write: + movel %d1,-(%sp) |preserve d1 just in case + movel %d0,-(%sp) + movel %a1,-(%sp) + movel %a0,-(%sp) + jsr copyout + addw #12,%sp + movel (%sp)+,%d1 + rts +| +| mem_read --- read from user or supervisor address space +| +| Reads from memory while in supervisor mode. copyin accomplishes +| this via a 'moves' instruction. copyin is a UNIX SVR3 (and later) function. +| If you don't have copyin, use the local copy of the function below. +| +| The FPSP calls mem_read to read the original F-line instruction in order +| to extract the data register number when the 'Dn' addressing mode is +| used. +| +|Input: +| a0 - user source address +| a1 - supervisor destination address +| d0 - number of bytes to read (maximum count is 12) +| +| Like mem_write, mem_read always reads with a supervisor +| destination address on the supervisor stack. Also like mem_write, +| the EXC_SR is checked and a simple memory copy is done if reading +| from supervisor space is indicated. +| + .global mem_read +mem_read: + btstb #5,EXC_SR(%a6) |check for supervisor state + beqs user_read +super_read: + moveb (%a0)+,(%a1)+ + subql #1,%d0 + bnes super_read + rts +user_read: + movel %d1,-(%sp) |preserve d1 just in case + movel %d0,-(%sp) + movel %a1,-(%sp) + movel %a0,-(%sp) + jsr copyin + addw #12,%sp + movel (%sp)+,%d1 + rts + +| +| Use these routines if your kernel doesn't have copyout/copyin equivalents. +| Assumes that D0/D1/A0/A1 are scratch registers. copyout overwrites DFC, +| and copyin overwrites SFC. +| +copyout: + movel 4(%sp),%a0 | source + movel 8(%sp),%a1 | destination + movel 12(%sp),%d0 | count + subl #1,%d0 | dec count by 1 for dbra + movel #1,%d1 + +| DFC is already set +| movec %d1,%DFC | set dfc for user data space +moreout: + moveb (%a0)+,%d1 | fetch supervisor byte +out_ea: + movesb %d1,(%a1)+ | write user byte + dbf %d0,moreout + rts + +copyin: + movel 4(%sp),%a0 | source + movel 8(%sp),%a1 | destination + movel 12(%sp),%d0 | count + subl #1,%d0 | dec count by 1 for dbra + movel #1,%d1 +| SFC is already set +| movec %d1,%SFC | set sfc for user space +morein: +in_ea: + movesb (%a0)+,%d1 | fetch user byte + moveb %d1,(%a1)+ | write supervisor byte + dbf %d0,morein + rts + + .section .fixup,"ax" + .even +1: + jbra fpsp040_die + + .section __ex_table,"a" + .align 4 + + .long in_ea,1b + .long out_ea,1b + + |end diff --git a/arch/m68k/fpsp040/slog2.S b/arch/m68k/fpsp040/slog2.S new file mode 100644 index 000000000..fac2c7383 --- /dev/null +++ b/arch/m68k/fpsp040/slog2.S @@ -0,0 +1,187 @@ +| +| slog2.sa 3.1 12/10/90 +| +| The entry point slog10 computes the base-10 +| logarithm of an input argument X. +| slog10d does the same except the input value is a +| denormalized number. +| sLog2 and sLog2d are the base-2 analogues. +| +| INPUT: Double-extended value in memory location pointed to +| by address register a0. +| +| OUTPUT: log_10(X) or log_2(X) returned in floating-point +| register fp0. +| +| ACCURACY and MONOTONICITY: The returned result is within 1.7 +| ulps in 64 significant bit, i.e. within 0.5003 ulp +| to 53 bits if the result is subsequently rounded +| to double precision. The result is provably monotonic +| in double precision. +| +| SPEED: Two timings are measured, both in the copy-back mode. +| The first one is measured when the function is invoked +| the first time (so the instructions and data are not +| in cache), and the second one is measured when the +| function is reinvoked at the same input argument. +| +| ALGORITHM and IMPLEMENTATION NOTES: +| +| slog10d: +| +| Step 0. If X < 0, create a NaN and raise the invalid operation +| flag. Otherwise, save FPCR in D1; set FpCR to default. +| Notes: Default means round-to-nearest mode, no floating-point +| traps, and precision control = double extended. +| +| Step 1. Call slognd to obtain Y = log(X), the natural log of X. +| Notes: Even if X is denormalized, log(X) is always normalized. +| +| Step 2. Compute log_10(X) = log(X) * (1/log(10)). +| 2.1 Restore the user FPCR +| 2.2 Return ans := Y * INV_L10. +| +| +| slog10: +| +| Step 0. If X < 0, create a NaN and raise the invalid operation +| flag. Otherwise, save FPCR in D1; set FpCR to default. +| Notes: Default means round-to-nearest mode, no floating-point +| traps, and precision control = double extended. +| +| Step 1. Call sLogN to obtain Y = log(X), the natural log of X. +| +| Step 2. Compute log_10(X) = log(X) * (1/log(10)). +| 2.1 Restore the user FPCR +| 2.2 Return ans := Y * INV_L10. +| +| +| sLog2d: +| +| Step 0. If X < 0, create a NaN and raise the invalid operation +| flag. Otherwise, save FPCR in D1; set FpCR to default. +| Notes: Default means round-to-nearest mode, no floating-point +| traps, and precision control = double extended. +| +| Step 1. Call slognd to obtain Y = log(X), the natural log of X. +| Notes: Even if X is denormalized, log(X) is always normalized. +| +| Step 2. Compute log_10(X) = log(X) * (1/log(2)). +| 2.1 Restore the user FPCR +| 2.2 Return ans := Y * INV_L2. +| +| +| sLog2: +| +| Step 0. If X < 0, create a NaN and raise the invalid operation +| flag. Otherwise, save FPCR in D1; set FpCR to default. +| Notes: Default means round-to-nearest mode, no floating-point +| traps, and precision control = double extended. +| +| Step 1. If X is not an integer power of two, i.e., X != 2^k, +| go to Step 3. +| +| Step 2. Return k. +| 2.1 Get integer k, X = 2^k. +| 2.2 Restore the user FPCR. +| 2.3 Return ans := convert-to-double-extended(k). +| +| Step 3. Call sLogN to obtain Y = log(X), the natural log of X. +| +| Step 4. Compute log_2(X) = log(X) * (1/log(2)). +| 4.1 Restore the user FPCR +| 4.2 Return ans := Y * INV_L2. +| + +| Copyright (C) Motorola, Inc. 1990 +| All Rights Reserved +| +| For details on the license for this file, please see the +| file, README, in this same directory. + +|SLOG2 idnt 2,1 | Motorola 040 Floating Point Software Package + + |section 8 + + |xref t_frcinx + |xref t_operr + |xref slogn + |xref slognd + +INV_L10: .long 0x3FFD0000,0xDE5BD8A9,0x37287195,0x00000000 + +INV_L2: .long 0x3FFF0000,0xB8AA3B29,0x5C17F0BC,0x00000000 + + .global slog10d +slog10d: +|--entry point for Log10(X), X is denormalized + movel (%a0),%d0 + blt invalid + movel %d1,-(%sp) + clrl %d1 + bsr slognd | ...log(X), X denorm. + fmovel (%sp)+,%fpcr + fmulx INV_L10,%fp0 + bra t_frcinx + + .global slog10 +slog10: +|--entry point for Log10(X), X is normalized + + movel (%a0),%d0 + blt invalid + movel %d1,-(%sp) + clrl %d1 + bsr slogn | ...log(X), X normal. + fmovel (%sp)+,%fpcr + fmulx INV_L10,%fp0 + bra t_frcinx + + + .global slog2d +slog2d: +|--entry point for Log2(X), X is denormalized + + movel (%a0),%d0 + blt invalid + movel %d1,-(%sp) + clrl %d1 + bsr slognd | ...log(X), X denorm. + fmovel (%sp)+,%fpcr + fmulx INV_L2,%fp0 + bra t_frcinx + + .global slog2 +slog2: +|--entry point for Log2(X), X is normalized + movel (%a0),%d0 + blt invalid + + movel 8(%a0),%d0 + bnes continue | ...X is not 2^k + + movel 4(%a0),%d0 + andl #0x7FFFFFFF,%d0 + tstl %d0 + bnes continue + +|--X = 2^k. + movew (%a0),%d0 + andl #0x00007FFF,%d0 + subl #0x3FFF,%d0 + fmovel %d1,%fpcr + fmovel %d0,%fp0 + bra t_frcinx + +continue: + movel %d1,-(%sp) + clrl %d1 + bsr slogn | ...log(X), X normal. + fmovel (%sp)+,%fpcr + fmulx INV_L2,%fp0 + bra t_frcinx + +invalid: + bra t_operr + + |end diff --git a/arch/m68k/fpsp040/slogn.S b/arch/m68k/fpsp040/slogn.S new file mode 100644 index 000000000..d98eaf641 --- /dev/null +++ b/arch/m68k/fpsp040/slogn.S @@ -0,0 +1,591 @@ +| +| slogn.sa 3.1 12/10/90 +| +| slogn computes the natural logarithm of an +| input value. slognd does the same except the input value is a +| denormalized number. slognp1 computes log(1+X), and slognp1d +| computes log(1+X) for denormalized X. +| +| Input: Double-extended value in memory location pointed to by address +| register a0. +| +| Output: log(X) or log(1+X) returned in floating-point register Fp0. +| +| Accuracy and Monotonicity: The returned result is within 2 ulps in +| 64 significant bit, i.e. within 0.5001 ulp to 53 bits if the +| result is subsequently rounded to double precision. The +| result is provably monotonic in double precision. +| +| Speed: The program slogn takes approximately 190 cycles for input +| argument X such that |X-1| >= 1/16, which is the usual +| situation. For those arguments, slognp1 takes approximately +| 210 cycles. For the less common arguments, the program will +| run no worse than 10% slower. +| +| Algorithm: +| LOGN: +| Step 1. If |X-1| < 1/16, approximate log(X) by an odd polynomial in +| u, where u = 2(X-1)/(X+1). Otherwise, move on to Step 2. +| +| Step 2. X = 2**k * Y where 1 <= Y < 2. Define F to be the first seven +| significant bits of Y plus 2**(-7), i.e. F = 1.xxxxxx1 in base +| 2 where the six "x" match those of Y. Note that |Y-F| <= 2**(-7). +| +| Step 3. Define u = (Y-F)/F. Approximate log(1+u) by a polynomial in u, +| log(1+u) = poly. +| +| Step 4. Reconstruct log(X) = log( 2**k * Y ) = k*log(2) + log(F) + log(1+u) +| by k*log(2) + (log(F) + poly). The values of log(F) are calculated +| beforehand and stored in the program. +| +| lognp1: +| Step 1: If |X| < 1/16, approximate log(1+X) by an odd polynomial in +| u where u = 2X/(2+X). Otherwise, move on to Step 2. +| +| Step 2: Let 1+X = 2**k * Y, where 1 <= Y < 2. Define F as done in Step 2 +| of the algorithm for LOGN and compute log(1+X) as +| k*log(2) + log(F) + poly where poly approximates log(1+u), +| u = (Y-F)/F. +| +| Implementation Notes: +| Note 1. There are 64 different possible values for F, thus 64 log(F)'s +| need to be tabulated. Moreover, the values of 1/F are also +| tabulated so that the division in (Y-F)/F can be performed by a +| multiplication. +| +| Note 2. In Step 2 of lognp1, in order to preserved accuracy, the value +| Y-F has to be calculated carefully when 1/2 <= X < 3/2. +| +| Note 3. To fully exploit the pipeline, polynomials are usually separated +| into two parts evaluated independently before being added up. +| + +| Copyright (C) Motorola, Inc. 1990 +| All Rights Reserved +| +| For details on the license for this file, please see the +| file, README, in this same directory. + +|slogn idnt 2,1 | Motorola 040 Floating Point Software Package + + |section 8 + +#include "fpsp.h" + +BOUNDS1: .long 0x3FFEF07D,0x3FFF8841 +BOUNDS2: .long 0x3FFE8000,0x3FFFC000 + +LOGOF2: .long 0x3FFE0000,0xB17217F7,0xD1CF79AC,0x00000000 + +one: .long 0x3F800000 +zero: .long 0x00000000 +infty: .long 0x7F800000 +negone: .long 0xBF800000 + +LOGA6: .long 0x3FC2499A,0xB5E4040B +LOGA5: .long 0xBFC555B5,0x848CB7DB + +LOGA4: .long 0x3FC99999,0x987D8730 +LOGA3: .long 0xBFCFFFFF,0xFF6F7E97 + +LOGA2: .long 0x3FD55555,0x555555a4 +LOGA1: .long 0xBFE00000,0x00000008 + +LOGB5: .long 0x3F175496,0xADD7DAD6 +LOGB4: .long 0x3F3C71C2,0xFE80C7E0 + +LOGB3: .long 0x3F624924,0x928BCCFF +LOGB2: .long 0x3F899999,0x999995EC + +LOGB1: .long 0x3FB55555,0x55555555 +TWO: .long 0x40000000,0x00000000 + +LTHOLD: .long 0x3f990000,0x80000000,0x00000000,0x00000000 + +LOGTBL: + .long 0x3FFE0000,0xFE03F80F,0xE03F80FE,0x00000000 + .long 0x3FF70000,0xFF015358,0x833C47E2,0x00000000 + .long 0x3FFE0000,0xFA232CF2,0x52138AC0,0x00000000 + .long 0x3FF90000,0xBDC8D83E,0xAD88D549,0x00000000 + .long 0x3FFE0000,0xF6603D98,0x0F6603DA,0x00000000 + .long 0x3FFA0000,0x9CF43DCF,0xF5EAFD48,0x00000000 + .long 0x3FFE0000,0xF2B9D648,0x0F2B9D65,0x00000000 + .long 0x3FFA0000,0xDA16EB88,0xCB8DF614,0x00000000 + .long 0x3FFE0000,0xEF2EB71F,0xC4345238,0x00000000 + .long 0x3FFB0000,0x8B29B775,0x1BD70743,0x00000000 + .long 0x3FFE0000,0xEBBDB2A5,0xC1619C8C,0x00000000 + .long 0x3FFB0000,0xA8D839F8,0x30C1FB49,0x00000000 + .long 0x3FFE0000,0xE865AC7B,0x7603A197,0x00000000 + .long 0x3FFB0000,0xC61A2EB1,0x8CD907AD,0x00000000 + .long 0x3FFE0000,0xE525982A,0xF70C880E,0x00000000 + .long 0x3FFB0000,0xE2F2A47A,0xDE3A18AF,0x00000000 + .long 0x3FFE0000,0xE1FC780E,0x1FC780E2,0x00000000 + .long 0x3FFB0000,0xFF64898E,0xDF55D551,0x00000000 + .long 0x3FFE0000,0xDEE95C4C,0xA037BA57,0x00000000 + .long 0x3FFC0000,0x8DB956A9,0x7B3D0148,0x00000000 + .long 0x3FFE0000,0xDBEB61EE,0xD19C5958,0x00000000 + .long 0x3FFC0000,0x9B8FE100,0xF47BA1DE,0x00000000 + .long 0x3FFE0000,0xD901B203,0x6406C80E,0x00000000 + .long 0x3FFC0000,0xA9372F1D,0x0DA1BD17,0x00000000 + .long 0x3FFE0000,0xD62B80D6,0x2B80D62C,0x00000000 + .long 0x3FFC0000,0xB6B07F38,0xCE90E46B,0x00000000 + .long 0x3FFE0000,0xD3680D36,0x80D3680D,0x00000000 + .long 0x3FFC0000,0xC3FD0329,0x06488481,0x00000000 + .long 0x3FFE0000,0xD0B69FCB,0xD2580D0B,0x00000000 + .long 0x3FFC0000,0xD11DE0FF,0x15AB18CA,0x00000000 + .long 0x3FFE0000,0xCE168A77,0x25080CE1,0x00000000 + .long 0x3FFC0000,0xDE1433A1,0x6C66B150,0x00000000 + .long 0x3FFE0000,0xCB8727C0,0x65C393E0,0x00000000 + .long 0x3FFC0000,0xEAE10B5A,0x7DDC8ADD,0x00000000 + .long 0x3FFE0000,0xC907DA4E,0x871146AD,0x00000000 + .long 0x3FFC0000,0xF7856E5E,0xE2C9B291,0x00000000 + .long 0x3FFE0000,0xC6980C69,0x80C6980C,0x00000000 + .long 0x3FFD0000,0x82012CA5,0xA68206D7,0x00000000 + .long 0x3FFE0000,0xC4372F85,0x5D824CA6,0x00000000 + .long 0x3FFD0000,0x882C5FCD,0x7256A8C5,0x00000000 + .long 0x3FFE0000,0xC1E4BBD5,0x95F6E947,0x00000000 + .long 0x3FFD0000,0x8E44C60B,0x4CCFD7DE,0x00000000 + .long 0x3FFE0000,0xBFA02FE8,0x0BFA02FF,0x00000000 + .long 0x3FFD0000,0x944AD09E,0xF4351AF6,0x00000000 + .long 0x3FFE0000,0xBD691047,0x07661AA3,0x00000000 + .long 0x3FFD0000,0x9A3EECD4,0xC3EAA6B2,0x00000000 + .long 0x3FFE0000,0xBB3EE721,0xA54D880C,0x00000000 + .long 0x3FFD0000,0xA0218434,0x353F1DE8,0x00000000 + .long 0x3FFE0000,0xB92143FA,0x36F5E02E,0x00000000 + .long 0x3FFD0000,0xA5F2FCAB,0xBBC506DA,0x00000000 + .long 0x3FFE0000,0xB70FBB5A,0x19BE3659,0x00000000 + .long 0x3FFD0000,0xABB3B8BA,0x2AD362A5,0x00000000 + .long 0x3FFE0000,0xB509E68A,0x9B94821F,0x00000000 + .long 0x3FFD0000,0xB1641795,0xCE3CA97B,0x00000000 + .long 0x3FFE0000,0xB30F6352,0x8917C80B,0x00000000 + .long 0x3FFD0000,0xB7047551,0x5D0F1C61,0x00000000 + .long 0x3FFE0000,0xB11FD3B8,0x0B11FD3C,0x00000000 + .long 0x3FFD0000,0xBC952AFE,0xEA3D13E1,0x00000000 + .long 0x3FFE0000,0xAF3ADDC6,0x80AF3ADE,0x00000000 + .long 0x3FFD0000,0xC2168ED0,0xF458BA4A,0x00000000 + .long 0x3FFE0000,0xAD602B58,0x0AD602B6,0x00000000 + .long 0x3FFD0000,0xC788F439,0xB3163BF1,0x00000000 + .long 0x3FFE0000,0xAB8F69E2,0x8359CD11,0x00000000 + .long 0x3FFD0000,0xCCECAC08,0xBF04565D,0x00000000 + .long 0x3FFE0000,0xA9C84A47,0xA07F5638,0x00000000 + .long 0x3FFD0000,0xD2420487,0x2DD85160,0x00000000 + .long 0x3FFE0000,0xA80A80A8,0x0A80A80B,0x00000000 + .long 0x3FFD0000,0xD7894992,0x3BC3588A,0x00000000 + .long 0x3FFE0000,0xA655C439,0x2D7B73A8,0x00000000 + .long 0x3FFD0000,0xDCC2C4B4,0x9887DACC,0x00000000 + .long 0x3FFE0000,0xA4A9CF1D,0x96833751,0x00000000 + .long 0x3FFD0000,0xE1EEBD3E,0x6D6A6B9E,0x00000000 + .long 0x3FFE0000,0xA3065E3F,0xAE7CD0E0,0x00000000 + .long 0x3FFD0000,0xE70D785C,0x2F9F5BDC,0x00000000 + .long 0x3FFE0000,0xA16B312E,0xA8FC377D,0x00000000 + .long 0x3FFD0000,0xEC1F392C,0x5179F283,0x00000000 + .long 0x3FFE0000,0x9FD809FD,0x809FD80A,0x00000000 + .long 0x3FFD0000,0xF12440D3,0xE36130E6,0x00000000 + .long 0x3FFE0000,0x9E4CAD23,0xDD5F3A20,0x00000000 + .long 0x3FFD0000,0xF61CCE92,0x346600BB,0x00000000 + .long 0x3FFE0000,0x9CC8E160,0xC3FB19B9,0x00000000 + .long 0x3FFD0000,0xFB091FD3,0x8145630A,0x00000000 + .long 0x3FFE0000,0x9B4C6F9E,0xF03A3CAA,0x00000000 + .long 0x3FFD0000,0xFFE97042,0xBFA4C2AD,0x00000000 + .long 0x3FFE0000,0x99D722DA,0xBDE58F06,0x00000000 + .long 0x3FFE0000,0x825EFCED,0x49369330,0x00000000 + .long 0x3FFE0000,0x9868C809,0x868C8098,0x00000000 + .long 0x3FFE0000,0x84C37A7A,0xB9A905C9,0x00000000 + .long 0x3FFE0000,0x97012E02,0x5C04B809,0x00000000 + .long 0x3FFE0000,0x87224C2E,0x8E645FB7,0x00000000 + .long 0x3FFE0000,0x95A02568,0x095A0257,0x00000000 + .long 0x3FFE0000,0x897B8CAC,0x9F7DE298,0x00000000 + .long 0x3FFE0000,0x94458094,0x45809446,0x00000000 + .long 0x3FFE0000,0x8BCF55DE,0xC4CD05FE,0x00000000 + .long 0x3FFE0000,0x92F11384,0x0497889C,0x00000000 + .long 0x3FFE0000,0x8E1DC0FB,0x89E125E5,0x00000000 + .long 0x3FFE0000,0x91A2B3C4,0xD5E6F809,0x00000000 + .long 0x3FFE0000,0x9066E68C,0x955B6C9B,0x00000000 + .long 0x3FFE0000,0x905A3863,0x3E06C43B,0x00000000 + .long 0x3FFE0000,0x92AADE74,0xC7BE59E0,0x00000000 + .long 0x3FFE0000,0x8F1779D9,0xFDC3A219,0x00000000 + .long 0x3FFE0000,0x94E9BFF6,0x15845643,0x00000000 + .long 0x3FFE0000,0x8DDA5202,0x37694809,0x00000000 + .long 0x3FFE0000,0x9723A1B7,0x20134203,0x00000000 + .long 0x3FFE0000,0x8CA29C04,0x6514E023,0x00000000 + .long 0x3FFE0000,0x995899C8,0x90EB8990,0x00000000 + .long 0x3FFE0000,0x8B70344A,0x139BC75A,0x00000000 + .long 0x3FFE0000,0x9B88BDAA,0x3A3DAE2F,0x00000000 + .long 0x3FFE0000,0x8A42F870,0x5669DB46,0x00000000 + .long 0x3FFE0000,0x9DB4224F,0xFFE1157C,0x00000000 + .long 0x3FFE0000,0x891AC73A,0xE9819B50,0x00000000 + .long 0x3FFE0000,0x9FDADC26,0x8B7A12DA,0x00000000 + .long 0x3FFE0000,0x87F78087,0xF78087F8,0x00000000 + .long 0x3FFE0000,0xA1FCFF17,0xCE733BD4,0x00000000 + .long 0x3FFE0000,0x86D90544,0x7A34ACC6,0x00000000 + .long 0x3FFE0000,0xA41A9E8F,0x5446FB9F,0x00000000 + .long 0x3FFE0000,0x85BF3761,0x2CEE3C9B,0x00000000 + .long 0x3FFE0000,0xA633CD7E,0x6771CD8B,0x00000000 + .long 0x3FFE0000,0x84A9F9C8,0x084A9F9D,0x00000000 + .long 0x3FFE0000,0xA8489E60,0x0B435A5E,0x00000000 + .long 0x3FFE0000,0x83993052,0x3FBE3368,0x00000000 + .long 0x3FFE0000,0xAA59233C,0xCCA4BD49,0x00000000 + .long 0x3FFE0000,0x828CBFBE,0xB9A020A3,0x00000000 + .long 0x3FFE0000,0xAC656DAE,0x6BCC4985,0x00000000 + .long 0x3FFE0000,0x81848DA8,0xFAF0D277,0x00000000 + .long 0x3FFE0000,0xAE6D8EE3,0x60BB2468,0x00000000 + .long 0x3FFE0000,0x80808080,0x80808081,0x00000000 + .long 0x3FFE0000,0xB07197A2,0x3C46C654,0x00000000 + + .set ADJK,L_SCR1 + + .set X,FP_SCR1 + .set XDCARE,X+2 + .set XFRAC,X+4 + + .set F,FP_SCR2 + .set FFRAC,F+4 + + .set KLOG2,FP_SCR3 + + .set SAVEU,FP_SCR4 + + | xref t_frcinx + |xref t_extdnrm + |xref t_operr + |xref t_dz + + .global slognd +slognd: +|--ENTRY POINT FOR LOG(X) FOR DENORMALIZED INPUT + + movel #-100,ADJK(%a6) | ...INPUT = 2^(ADJK) * FP0 + +|----normalize the input value by left shifting k bits (k to be determined +|----below), adjusting exponent and storing -k to ADJK +|----the value TWOTO100 is no longer needed. +|----Note that this code assumes the denormalized input is NON-ZERO. + + moveml %d2-%d7,-(%a7) | ...save some registers + movel #0x00000000,%d3 | ...D3 is exponent of smallest norm. # + movel 4(%a0),%d4 + movel 8(%a0),%d5 | ...(D4,D5) is (Hi_X,Lo_X) + clrl %d2 | ...D2 used for holding K + + tstl %d4 + bnes HiX_not0 + +HiX_0: + movel %d5,%d4 + clrl %d5 + movel #32,%d2 + clrl %d6 + bfffo %d4{#0:#32},%d6 + lsll %d6,%d4 + addl %d6,%d2 | ...(D3,D4,D5) is normalized + + movel %d3,X(%a6) + movel %d4,XFRAC(%a6) + movel %d5,XFRAC+4(%a6) + negl %d2 + movel %d2,ADJK(%a6) + fmovex X(%a6),%fp0 + moveml (%a7)+,%d2-%d7 | ...restore registers + lea X(%a6),%a0 + bras LOGBGN | ...begin regular log(X) + + +HiX_not0: + clrl %d6 + bfffo %d4{#0:#32},%d6 | ...find first 1 + movel %d6,%d2 | ...get k + lsll %d6,%d4 + movel %d5,%d7 | ...a copy of D5 + lsll %d6,%d5 + negl %d6 + addil #32,%d6 + lsrl %d6,%d7 + orl %d7,%d4 | ...(D3,D4,D5) normalized + + movel %d3,X(%a6) + movel %d4,XFRAC(%a6) + movel %d5,XFRAC+4(%a6) + negl %d2 + movel %d2,ADJK(%a6) + fmovex X(%a6),%fp0 + moveml (%a7)+,%d2-%d7 | ...restore registers + lea X(%a6),%a0 + bras LOGBGN | ...begin regular log(X) + + + .global slogn +slogn: +|--ENTRY POINT FOR LOG(X) FOR X FINITE, NON-ZERO, NOT NAN'S + + fmovex (%a0),%fp0 | ...LOAD INPUT + movel #0x00000000,ADJK(%a6) + +LOGBGN: +|--FPCR SAVED AND CLEARED, INPUT IS 2^(ADJK)*FP0, FP0 CONTAINS +|--A FINITE, NON-ZERO, NORMALIZED NUMBER. + + movel (%a0),%d0 + movew 4(%a0),%d0 + + movel (%a0),X(%a6) + movel 4(%a0),X+4(%a6) + movel 8(%a0),X+8(%a6) + + cmpil #0,%d0 | ...CHECK IF X IS NEGATIVE + blt LOGNEG | ...LOG OF NEGATIVE ARGUMENT IS INVALID + cmp2l BOUNDS1,%d0 | ...X IS POSITIVE, CHECK IF X IS NEAR 1 + bcc LOGNEAR1 | ...BOUNDS IS ROUGHLY [15/16, 17/16] + +LOGMAIN: +|--THIS SHOULD BE THE USUAL CASE, X NOT VERY CLOSE TO 1 + +|--X = 2^(K) * Y, 1 <= Y < 2. THUS, Y = 1.XXXXXXXX....XX IN BINARY. +|--WE DEFINE F = 1.XXXXXX1, I.E. FIRST 7 BITS OF Y AND ATTACH A 1. +|--THE IDEA IS THAT LOG(X) = K*LOG2 + LOG(Y) +|-- = K*LOG2 + LOG(F) + LOG(1 + (Y-F)/F). +|--NOTE THAT U = (Y-F)/F IS VERY SMALL AND THUS APPROXIMATING +|--LOG(1+U) CAN BE VERY EFFICIENT. +|--ALSO NOTE THAT THE VALUE 1/F IS STORED IN A TABLE SO THAT NO +|--DIVISION IS NEEDED TO CALCULATE (Y-F)/F. + +|--GET K, Y, F, AND ADDRESS OF 1/F. + asrl #8,%d0 + asrl #8,%d0 | ...SHIFTED 16 BITS, BIASED EXPO. OF X + subil #0x3FFF,%d0 | ...THIS IS K + addl ADJK(%a6),%d0 | ...ADJUST K, ORIGINAL INPUT MAY BE DENORM. + lea LOGTBL,%a0 | ...BASE ADDRESS OF 1/F AND LOG(F) + fmovel %d0,%fp1 | ...CONVERT K TO FLOATING-POINT FORMAT + +|--WHILE THE CONVERSION IS GOING ON, WE GET F AND ADDRESS OF 1/F + movel #0x3FFF0000,X(%a6) | ...X IS NOW Y, I.E. 2^(-K)*X + movel XFRAC(%a6),FFRAC(%a6) + andil #0xFE000000,FFRAC(%a6) | ...FIRST 7 BITS OF Y + oril #0x01000000,FFRAC(%a6) | ...GET F: ATTACH A 1 AT THE EIGHTH BIT + movel FFRAC(%a6),%d0 | ...READY TO GET ADDRESS OF 1/F + andil #0x7E000000,%d0 + asrl #8,%d0 + asrl #8,%d0 + asrl #4,%d0 | ...SHIFTED 20, D0 IS THE DISPLACEMENT + addal %d0,%a0 | ...A0 IS THE ADDRESS FOR 1/F + + fmovex X(%a6),%fp0 + movel #0x3fff0000,F(%a6) + clrl F+8(%a6) + fsubx F(%a6),%fp0 | ...Y-F + fmovemx %fp2-%fp2/%fp3,-(%sp) | ...SAVE FP2 WHILE FP0 IS NOT READY +|--SUMMARY: FP0 IS Y-F, A0 IS ADDRESS OF 1/F, FP1 IS K +|--REGISTERS SAVED: FPCR, FP1, FP2 + +LP1CONT1: +|--AN RE-ENTRY POINT FOR LOGNP1 + fmulx (%a0),%fp0 | ...FP0 IS U = (Y-F)/F + fmulx LOGOF2,%fp1 | ...GET K*LOG2 WHILE FP0 IS NOT READY + fmovex %fp0,%fp2 + fmulx %fp2,%fp2 | ...FP2 IS V=U*U + fmovex %fp1,KLOG2(%a6) | ...PUT K*LOG2 IN MEMORY, FREE FP1 + +|--LOG(1+U) IS APPROXIMATED BY +|--U + V*(A1+U*(A2+U*(A3+U*(A4+U*(A5+U*A6))))) WHICH IS +|--[U + V*(A1+V*(A3+V*A5))] + [U*V*(A2+V*(A4+V*A6))] + + fmovex %fp2,%fp3 + fmovex %fp2,%fp1 + + fmuld LOGA6,%fp1 | ...V*A6 + fmuld LOGA5,%fp2 | ...V*A5 + + faddd LOGA4,%fp1 | ...A4+V*A6 + faddd LOGA3,%fp2 | ...A3+V*A5 + + fmulx %fp3,%fp1 | ...V*(A4+V*A6) + fmulx %fp3,%fp2 | ...V*(A3+V*A5) + + faddd LOGA2,%fp1 | ...A2+V*(A4+V*A6) + faddd LOGA1,%fp2 | ...A1+V*(A3+V*A5) + + fmulx %fp3,%fp1 | ...V*(A2+V*(A4+V*A6)) + addal #16,%a0 | ...ADDRESS OF LOG(F) + fmulx %fp3,%fp2 | ...V*(A1+V*(A3+V*A5)), FP3 RELEASED + + fmulx %fp0,%fp1 | ...U*V*(A2+V*(A4+V*A6)) + faddx %fp2,%fp0 | ...U+V*(A1+V*(A3+V*A5)), FP2 RELEASED + + faddx (%a0),%fp1 | ...LOG(F)+U*V*(A2+V*(A4+V*A6)) + fmovemx (%sp)+,%fp2-%fp2/%fp3 | ...RESTORE FP2 + faddx %fp1,%fp0 | ...FP0 IS LOG(F) + LOG(1+U) + + fmovel %d1,%fpcr + faddx KLOG2(%a6),%fp0 | ...FINAL ADD + bra t_frcinx + + +LOGNEAR1: +|--REGISTERS SAVED: FPCR, FP1. FP0 CONTAINS THE INPUT. + fmovex %fp0,%fp1 + fsubs one,%fp1 | ...FP1 IS X-1 + fadds one,%fp0 | ...FP0 IS X+1 + faddx %fp1,%fp1 | ...FP1 IS 2(X-1) +|--LOG(X) = LOG(1+U/2)-LOG(1-U/2) WHICH IS AN ODD POLYNOMIAL +|--IN U, U = 2(X-1)/(X+1) = FP1/FP0 + +LP1CONT2: +|--THIS IS AN RE-ENTRY POINT FOR LOGNP1 + fdivx %fp0,%fp1 | ...FP1 IS U + fmovemx %fp2-%fp2/%fp3,-(%sp) | ...SAVE FP2 +|--REGISTERS SAVED ARE NOW FPCR,FP1,FP2,FP3 +|--LET V=U*U, W=V*V, CALCULATE +|--U + U*V*(B1 + V*(B2 + V*(B3 + V*(B4 + V*B5)))) BY +|--U + U*V*( [B1 + W*(B3 + W*B5)] + [V*(B2 + W*B4)] ) + fmovex %fp1,%fp0 + fmulx %fp0,%fp0 | ...FP0 IS V + fmovex %fp1,SAVEU(%a6) | ...STORE U IN MEMORY, FREE FP1 + fmovex %fp0,%fp1 + fmulx %fp1,%fp1 | ...FP1 IS W + + fmoved LOGB5,%fp3 + fmoved LOGB4,%fp2 + + fmulx %fp1,%fp3 | ...W*B5 + fmulx %fp1,%fp2 | ...W*B4 + + faddd LOGB3,%fp3 | ...B3+W*B5 + faddd LOGB2,%fp2 | ...B2+W*B4 + + fmulx %fp3,%fp1 | ...W*(B3+W*B5), FP3 RELEASED + + fmulx %fp0,%fp2 | ...V*(B2+W*B4) + + faddd LOGB1,%fp1 | ...B1+W*(B3+W*B5) + fmulx SAVEU(%a6),%fp0 | ...FP0 IS U*V + + faddx %fp2,%fp1 | ...B1+W*(B3+W*B5) + V*(B2+W*B4), FP2 RELEASED + fmovemx (%sp)+,%fp2-%fp2/%fp3 | ...FP2 RESTORED + + fmulx %fp1,%fp0 | ...U*V*( [B1+W*(B3+W*B5)] + [V*(B2+W*B4)] ) + + fmovel %d1,%fpcr + faddx SAVEU(%a6),%fp0 + bra t_frcinx + rts + +LOGNEG: +|--REGISTERS SAVED FPCR. LOG(-VE) IS INVALID + bra t_operr + + .global slognp1d +slognp1d: +|--ENTRY POINT FOR LOG(1+Z) FOR DENORMALIZED INPUT +| Simply return the denorm + + bra t_extdnrm + + .global slognp1 +slognp1: +|--ENTRY POINT FOR LOG(1+X) FOR X FINITE, NON-ZERO, NOT NAN'S + + fmovex (%a0),%fp0 | ...LOAD INPUT + fabsx %fp0 |test magnitude + fcmpx LTHOLD,%fp0 |compare with min threshold + fbgt LP1REAL |if greater, continue + fmovel #0,%fpsr |clr N flag from compare + fmovel %d1,%fpcr + fmovex (%a0),%fp0 |return signed argument + bra t_frcinx + +LP1REAL: + fmovex (%a0),%fp0 | ...LOAD INPUT + movel #0x00000000,ADJK(%a6) + fmovex %fp0,%fp1 | ...FP1 IS INPUT Z + fadds one,%fp0 | ...X := ROUND(1+Z) + fmovex %fp0,X(%a6) + movew XFRAC(%a6),XDCARE(%a6) + movel X(%a6),%d0 + cmpil #0,%d0 + ble LP1NEG0 | ...LOG OF ZERO OR -VE + cmp2l BOUNDS2,%d0 + bcs LOGMAIN | ...BOUNDS2 IS [1/2,3/2] +|--IF 1+Z > 3/2 OR 1+Z < 1/2, THEN X, WHICH IS ROUNDING 1+Z, +|--CONTAINS AT LEAST 63 BITS OF INFORMATION OF Z. IN THAT CASE, +|--SIMPLY INVOKE LOG(X) FOR LOG(1+Z). + +LP1NEAR1: +|--NEXT SEE IF EXP(-1/16) < X < EXP(1/16) + cmp2l BOUNDS1,%d0 + bcss LP1CARE + +LP1ONE16: +|--EXP(-1/16) < X < EXP(1/16). LOG(1+Z) = LOG(1+U/2) - LOG(1-U/2) +|--WHERE U = 2Z/(2+Z) = 2Z/(1+X). + faddx %fp1,%fp1 | ...FP1 IS 2Z + fadds one,%fp0 | ...FP0 IS 1+X +|--U = FP1/FP0 + bra LP1CONT2 + +LP1CARE: +|--HERE WE USE THE USUAL TABLE DRIVEN APPROACH. CARE HAS TO BE +|--TAKEN BECAUSE 1+Z CAN HAVE 67 BITS OF INFORMATION AND WE MUST +|--PRESERVE ALL THE INFORMATION. BECAUSE 1+Z IS IN [1/2,3/2], +|--THERE ARE ONLY TWO CASES. +|--CASE 1: 1+Z < 1, THEN K = -1 AND Y-F = (2-F) + 2Z +|--CASE 2: 1+Z > 1, THEN K = 0 AND Y-F = (1-F) + Z +|--ON RETURNING TO LP1CONT1, WE MUST HAVE K IN FP1, ADDRESS OF +|--(1/F) IN A0, Y-F IN FP0, AND FP2 SAVED. + + movel XFRAC(%a6),FFRAC(%a6) + andil #0xFE000000,FFRAC(%a6) + oril #0x01000000,FFRAC(%a6) | ...F OBTAINED + cmpil #0x3FFF8000,%d0 | ...SEE IF 1+Z > 1 + bges KISZERO + +KISNEG1: + fmoves TWO,%fp0 + movel #0x3fff0000,F(%a6) + clrl F+8(%a6) + fsubx F(%a6),%fp0 | ...2-F + movel FFRAC(%a6),%d0 + andil #0x7E000000,%d0 + asrl #8,%d0 + asrl #8,%d0 + asrl #4,%d0 | ...D0 CONTAINS DISPLACEMENT FOR 1/F + faddx %fp1,%fp1 | ...GET 2Z + fmovemx %fp2-%fp2/%fp3,-(%sp) | ...SAVE FP2 + faddx %fp1,%fp0 | ...FP0 IS Y-F = (2-F)+2Z + lea LOGTBL,%a0 | ...A0 IS ADDRESS OF 1/F + addal %d0,%a0 + fmoves negone,%fp1 | ...FP1 IS K = -1 + bra LP1CONT1 + +KISZERO: + fmoves one,%fp0 + movel #0x3fff0000,F(%a6) + clrl F+8(%a6) + fsubx F(%a6),%fp0 | ...1-F + movel FFRAC(%a6),%d0 + andil #0x7E000000,%d0 + asrl #8,%d0 + asrl #8,%d0 + asrl #4,%d0 + faddx %fp1,%fp0 | ...FP0 IS Y-F + fmovemx %fp2-%fp2/%fp3,-(%sp) | ...FP2 SAVED + lea LOGTBL,%a0 + addal %d0,%a0 | ...A0 IS ADDRESS OF 1/F + fmoves zero,%fp1 | ...FP1 IS K = 0 + bra LP1CONT1 + +LP1NEG0: +|--FPCR SAVED. D0 IS X IN COMPACT FORM. + cmpil #0,%d0 + blts LP1NEG +LP1ZERO: + fmoves negone,%fp0 + + fmovel %d1,%fpcr + bra t_dz + +LP1NEG: + fmoves zero,%fp0 + + fmovel %d1,%fpcr + bra t_operr + + |end diff --git a/arch/m68k/fpsp040/smovecr.S b/arch/m68k/fpsp040/smovecr.S new file mode 100644 index 000000000..73c365120 --- /dev/null +++ b/arch/m68k/fpsp040/smovecr.S @@ -0,0 +1,161 @@ +| +| smovecr.sa 3.1 12/10/90 +| +| The entry point sMOVECR returns the constant at the +| offset given in the instruction field. +| +| Input: An offset in the instruction word. +| +| Output: The constant rounded to the user's rounding +| mode unchecked for overflow. +| +| Modified: fp0. +| +| +| Copyright (C) Motorola, Inc. 1990 +| All Rights Reserved +| +| For details on the license for this file, please see the +| file, README, in this same directory. + +|SMOVECR idnt 2,1 | Motorola 040 Floating Point Software Package + + |section 8 + +#include "fpsp.h" + + |xref nrm_set + |xref round + |xref PIRN + |xref PIRZRM + |xref PIRP + |xref SMALRN + |xref SMALRZRM + |xref SMALRP + |xref BIGRN + |xref BIGRZRM + |xref BIGRP + +FZERO: .long 00000000 +| +| FMOVECR +| + .global smovcr +smovcr: + bfextu CMDREG1B(%a6){#9:#7},%d0 |get offset + bfextu USER_FPCR(%a6){#26:#2},%d1 |get rmode +| +| check range of offset +| + tstb %d0 |if zero, offset is to pi + beqs PI_TBL |it is pi + cmpib #0x0a,%d0 |check range $01 - $0a + bles Z_VAL |if in this range, return zero + cmpib #0x0e,%d0 |check range $0b - $0e + bles SM_TBL |valid constants in this range + cmpib #0x2f,%d0 |check range $10 - $2f + bles Z_VAL |if in this range, return zero + cmpib #0x3f,%d0 |check range $30 - $3f + ble BG_TBL |valid constants in this range +Z_VAL: + fmoves FZERO,%fp0 + rts +PI_TBL: + tstb %d1 |offset is zero, check for rmode + beqs PI_RN |if zero, rn mode + cmpib #0x3,%d1 |check for rp + beqs PI_RP |if 3, rp mode +PI_RZRM: + leal PIRZRM,%a0 |rmode is rz or rm, load PIRZRM in a0 + bra set_finx +PI_RN: + leal PIRN,%a0 |rmode is rn, load PIRN in a0 + bra set_finx +PI_RP: + leal PIRP,%a0 |rmode is rp, load PIRP in a0 + bra set_finx +SM_TBL: + subil #0xb,%d0 |make offset in 0 - 4 range + tstb %d1 |check for rmode + beqs SM_RN |if zero, rn mode + cmpib #0x3,%d1 |check for rp + beqs SM_RP |if 3, rp mode +SM_RZRM: + leal SMALRZRM,%a0 |rmode is rz or rm, load SMRZRM in a0 + cmpib #0x2,%d0 |check if result is inex + ble set_finx |if 0 - 2, it is inexact + bra no_finx |if 3, it is exact +SM_RN: + leal SMALRN,%a0 |rmode is rn, load SMRN in a0 + cmpib #0x2,%d0 |check if result is inex + ble set_finx |if 0 - 2, it is inexact + bra no_finx |if 3, it is exact +SM_RP: + leal SMALRP,%a0 |rmode is rp, load SMRP in a0 + cmpib #0x2,%d0 |check if result is inex + ble set_finx |if 0 - 2, it is inexact + bra no_finx |if 3, it is exact +BG_TBL: + subil #0x30,%d0 |make offset in 0 - f range + tstb %d1 |check for rmode + beqs BG_RN |if zero, rn mode + cmpib #0x3,%d1 |check for rp + beqs BG_RP |if 3, rp mode +BG_RZRM: + leal BIGRZRM,%a0 |rmode is rz or rm, load BGRZRM in a0 + cmpib #0x1,%d0 |check if result is inex + ble set_finx |if 0 - 1, it is inexact + cmpib #0x7,%d0 |second check + ble no_finx |if 0 - 7, it is exact + bra set_finx |if 8 - f, it is inexact +BG_RN: + leal BIGRN,%a0 |rmode is rn, load BGRN in a0 + cmpib #0x1,%d0 |check if result is inex + ble set_finx |if 0 - 1, it is inexact + cmpib #0x7,%d0 |second check + ble no_finx |if 0 - 7, it is exact + bra set_finx |if 8 - f, it is inexact +BG_RP: + leal BIGRP,%a0 |rmode is rp, load SMRP in a0 + cmpib #0x1,%d0 |check if result is inex + ble set_finx |if 0 - 1, it is inexact + cmpib #0x7,%d0 |second check + ble no_finx |if 0 - 7, it is exact +| bra set_finx ;if 8 - f, it is inexact +set_finx: + orl #inx2a_mask,USER_FPSR(%a6) |set inex2/ainex +no_finx: + mulul #12,%d0 |use offset to point into tables + movel %d1,L_SCR1(%a6) |load mode for round call + bfextu USER_FPCR(%a6){#24:#2},%d1 |get precision + tstl %d1 |check if extended precision +| +| Precision is extended +| + bnes not_ext |if extended, do not call round + fmovemx (%a0,%d0),%fp0-%fp0 |return result in fp0 + rts +| +| Precision is single or double +| +not_ext: + swap %d1 |rnd prec in upper word of d1 + addl L_SCR1(%a6),%d1 |merge rmode in low word of d1 + movel (%a0,%d0),FP_SCR1(%a6) |load first word to temp storage + movel 4(%a0,%d0),FP_SCR1+4(%a6) |load second word + movel 8(%a0,%d0),FP_SCR1+8(%a6) |load third word + clrl %d0 |clear g,r,s + lea FP_SCR1(%a6),%a0 + btstb #sign_bit,LOCAL_EX(%a0) + sne LOCAL_SGN(%a0) |convert to internal ext. format + + bsr round |go round the mantissa + + bfclr LOCAL_SGN(%a0){#0:#8} |convert back to IEEE ext format + beqs fin_fcr + bsetb #sign_bit,LOCAL_EX(%a0) +fin_fcr: + fmovemx (%a0),%fp0-%fp0 + rts + + |end diff --git a/arch/m68k/fpsp040/srem_mod.S b/arch/m68k/fpsp040/srem_mod.S new file mode 100644 index 000000000..a27e70c9a --- /dev/null +++ b/arch/m68k/fpsp040/srem_mod.S @@ -0,0 +1,421 @@ +| +| srem_mod.sa 3.1 12/10/90 +| +| The entry point sMOD computes the floating point MOD of the +| input values X and Y. The entry point sREM computes the floating +| point (IEEE) REM of the input values X and Y. +| +| INPUT +| ----- +| Double-extended value Y is pointed to by address in register +| A0. Double-extended value X is located in -12(A0). The values +| of X and Y are both nonzero and finite; although either or both +| of them can be denormalized. The special cases of zeros, NaNs, +| and infinities are handled elsewhere. +| +| OUTPUT +| ------ +| FREM(X,Y) or FMOD(X,Y), depending on entry point. +| +| ALGORITHM +| --------- +| +| Step 1. Save and strip signs of X and Y: signX := sign(X), +| signY := sign(Y), X := |X|, Y := |Y|, +| signQ := signX EOR signY. Record whether MOD or REM +| is requested. +| +| Step 2. Set L := expo(X)-expo(Y), k := 0, Q := 0. +| If (L < 0) then +| R := X, go to Step 4. +| else +| R := 2^(-L)X, j := L. +| endif +| +| Step 3. Perform MOD(X,Y) +| 3.1 If R = Y, go to Step 9. +| 3.2 If R > Y, then { R := R - Y, Q := Q + 1} +| 3.3 If j = 0, go to Step 4. +| 3.4 k := k + 1, j := j - 1, Q := 2Q, R := 2R. Go to +| Step 3.1. +| +| Step 4. At this point, R = X - QY = MOD(X,Y). Set +| Last_Subtract := false (used in Step 7 below). If +| MOD is requested, go to Step 6. +| +| Step 5. R = MOD(X,Y), but REM(X,Y) is requested. +| 5.1 If R < Y/2, then R = MOD(X,Y) = REM(X,Y). Go to +| Step 6. +| 5.2 If R > Y/2, then { set Last_Subtract := true, +| Q := Q + 1, Y := signY*Y }. Go to Step 6. +| 5.3 This is the tricky case of R = Y/2. If Q is odd, +| then { Q := Q + 1, signX := -signX }. +| +| Step 6. R := signX*R. +| +| Step 7. If Last_Subtract = true, R := R - Y. +| +| Step 8. Return signQ, last 7 bits of Q, and R as required. +| +| Step 9. At this point, R = 2^(-j)*X - Q Y = Y. Thus, +| X = 2^(j)*(Q+1)Y. set Q := 2^(j)*(Q+1), +| R := 0. Return signQ, last 7 bits of Q, and R. +| +| + +| Copyright (C) Motorola, Inc. 1990 +| All Rights Reserved +| +| For details on the license for this file, please see the +| file, README, in this same directory. + +SREM_MOD: |idnt 2,1 | Motorola 040 Floating Point Software Package + + |section 8 + +#include "fpsp.h" + + .set Mod_Flag,L_SCR3 + .set SignY,FP_SCR3+4 + .set SignX,FP_SCR3+8 + .set SignQ,FP_SCR3+12 + .set Sc_Flag,FP_SCR4 + + .set Y,FP_SCR1 + .set Y_Hi,Y+4 + .set Y_Lo,Y+8 + + .set R,FP_SCR2 + .set R_Hi,R+4 + .set R_Lo,R+8 + + +Scale: .long 0x00010000,0x80000000,0x00000000,0x00000000 + + |xref t_avoid_unsupp + + .global smod +smod: + + movel #0,Mod_Flag(%a6) + bras Mod_Rem + + .global srem +srem: + + movel #1,Mod_Flag(%a6) + +Mod_Rem: +|..Save sign of X and Y + moveml %d2-%d7,-(%a7) | ...save data registers + movew (%a0),%d3 + movew %d3,SignY(%a6) + andil #0x00007FFF,%d3 | ...Y := |Y| + +| + movel 4(%a0),%d4 + movel 8(%a0),%d5 | ...(D3,D4,D5) is |Y| + + tstl %d3 + bnes Y_Normal + + movel #0x00003FFE,%d3 | ...$3FFD + 1 + tstl %d4 + bnes HiY_not0 + +HiY_0: + movel %d5,%d4 + clrl %d5 + subil #32,%d3 + clrl %d6 + bfffo %d4{#0:#32},%d6 + lsll %d6,%d4 + subl %d6,%d3 | ...(D3,D4,D5) is normalized +| ...with bias $7FFD + bras Chk_X + +HiY_not0: + clrl %d6 + bfffo %d4{#0:#32},%d6 + subl %d6,%d3 + lsll %d6,%d4 + movel %d5,%d7 | ...a copy of D5 + lsll %d6,%d5 + negl %d6 + addil #32,%d6 + lsrl %d6,%d7 + orl %d7,%d4 | ...(D3,D4,D5) normalized +| ...with bias $7FFD + bras Chk_X + +Y_Normal: + addil #0x00003FFE,%d3 | ...(D3,D4,D5) normalized +| ...with bias $7FFD + +Chk_X: + movew -12(%a0),%d0 + movew %d0,SignX(%a6) + movew SignY(%a6),%d1 + eorl %d0,%d1 + andil #0x00008000,%d1 + movew %d1,SignQ(%a6) | ...sign(Q) obtained + andil #0x00007FFF,%d0 + movel -8(%a0),%d1 + movel -4(%a0),%d2 | ...(D0,D1,D2) is |X| + tstl %d0 + bnes X_Normal + movel #0x00003FFE,%d0 + tstl %d1 + bnes HiX_not0 + +HiX_0: + movel %d2,%d1 + clrl %d2 + subil #32,%d0 + clrl %d6 + bfffo %d1{#0:#32},%d6 + lsll %d6,%d1 + subl %d6,%d0 | ...(D0,D1,D2) is normalized +| ...with bias $7FFD + bras Init + +HiX_not0: + clrl %d6 + bfffo %d1{#0:#32},%d6 + subl %d6,%d0 + lsll %d6,%d1 + movel %d2,%d7 | ...a copy of D2 + lsll %d6,%d2 + negl %d6 + addil #32,%d6 + lsrl %d6,%d7 + orl %d7,%d1 | ...(D0,D1,D2) normalized +| ...with bias $7FFD + bras Init + +X_Normal: + addil #0x00003FFE,%d0 | ...(D0,D1,D2) normalized +| ...with bias $7FFD + +Init: +| + movel %d3,L_SCR1(%a6) | ...save biased expo(Y) + movel %d0,L_SCR2(%a6) |save d0 + subl %d3,%d0 | ...L := expo(X)-expo(Y) +| Move.L D0,L ...D0 is j + clrl %d6 | ...D6 := carry <- 0 + clrl %d3 | ...D3 is Q + moveal #0,%a1 | ...A1 is k; j+k=L, Q=0 + +|..(Carry,D1,D2) is R + tstl %d0 + bges Mod_Loop + +|..expo(X) < expo(Y). Thus X = mod(X,Y) +| + movel L_SCR2(%a6),%d0 |restore d0 + bra Get_Mod + +|..At this point R = 2^(-L)X; Q = 0; k = 0; and k+j = L + + +Mod_Loop: + tstl %d6 | ...test carry bit + bgts R_GT_Y + +|..At this point carry = 0, R = (D1,D2), Y = (D4,D5) + cmpl %d4,%d1 | ...compare hi(R) and hi(Y) + bnes R_NE_Y + cmpl %d5,%d2 | ...compare lo(R) and lo(Y) + bnes R_NE_Y + +|..At this point, R = Y + bra Rem_is_0 + +R_NE_Y: +|..use the borrow of the previous compare + bcss R_LT_Y | ...borrow is set iff R < Y + +R_GT_Y: +|..If Carry is set, then Y < (Carry,D1,D2) < 2Y. Otherwise, Carry = 0 +|..and Y < (D1,D2) < 2Y. Either way, perform R - Y + subl %d5,%d2 | ...lo(R) - lo(Y) + subxl %d4,%d1 | ...hi(R) - hi(Y) + clrl %d6 | ...clear carry + addql #1,%d3 | ...Q := Q + 1 + +R_LT_Y: +|..At this point, Carry=0, R < Y. R = 2^(k-L)X - QY; k+j = L; j >= 0. + tstl %d0 | ...see if j = 0. + beqs PostLoop + + addl %d3,%d3 | ...Q := 2Q + addl %d2,%d2 | ...lo(R) = 2lo(R) + roxll #1,%d1 | ...hi(R) = 2hi(R) + carry + scs %d6 | ...set Carry if 2(R) overflows + addql #1,%a1 | ...k := k+1 + subql #1,%d0 | ...j := j - 1 +|..At this point, R=(Carry,D1,D2) = 2^(k-L)X - QY, j+k=L, j >= 0, R < 2Y. + + bras Mod_Loop + +PostLoop: +|..k = L, j = 0, Carry = 0, R = (D1,D2) = X - QY, R < Y. + +|..normalize R. + movel L_SCR1(%a6),%d0 | ...new biased expo of R + tstl %d1 + bnes HiR_not0 + +HiR_0: + movel %d2,%d1 + clrl %d2 + subil #32,%d0 + clrl %d6 + bfffo %d1{#0:#32},%d6 + lsll %d6,%d1 + subl %d6,%d0 | ...(D0,D1,D2) is normalized +| ...with bias $7FFD + bras Get_Mod + +HiR_not0: + clrl %d6 + bfffo %d1{#0:#32},%d6 + bmis Get_Mod | ...already normalized + subl %d6,%d0 + lsll %d6,%d1 + movel %d2,%d7 | ...a copy of D2 + lsll %d6,%d2 + negl %d6 + addil #32,%d6 + lsrl %d6,%d7 + orl %d7,%d1 | ...(D0,D1,D2) normalized + +| +Get_Mod: + cmpil #0x000041FE,%d0 + bges No_Scale +Do_Scale: + movew %d0,R(%a6) + clrw R+2(%a6) + movel %d1,R_Hi(%a6) + movel %d2,R_Lo(%a6) + movel L_SCR1(%a6),%d6 + movew %d6,Y(%a6) + clrw Y+2(%a6) + movel %d4,Y_Hi(%a6) + movel %d5,Y_Lo(%a6) + fmovex R(%a6),%fp0 | ...no exception + movel #1,Sc_Flag(%a6) + bras ModOrRem +No_Scale: + movel %d1,R_Hi(%a6) + movel %d2,R_Lo(%a6) + subil #0x3FFE,%d0 + movew %d0,R(%a6) + clrw R+2(%a6) + movel L_SCR1(%a6),%d6 + subil #0x3FFE,%d6 + movel %d6,L_SCR1(%a6) + fmovex R(%a6),%fp0 + movew %d6,Y(%a6) + movel %d4,Y_Hi(%a6) + movel %d5,Y_Lo(%a6) + movel #0,Sc_Flag(%a6) + +| + + +ModOrRem: + movel Mod_Flag(%a6),%d6 + beqs Fix_Sign + + movel L_SCR1(%a6),%d6 | ...new biased expo(Y) + subql #1,%d6 | ...biased expo(Y/2) + cmpl %d6,%d0 + blts Fix_Sign + bgts Last_Sub + + cmpl %d4,%d1 + bnes Not_EQ + cmpl %d5,%d2 + bnes Not_EQ + bra Tie_Case + +Not_EQ: + bcss Fix_Sign + +Last_Sub: +| + fsubx Y(%a6),%fp0 | ...no exceptions + addql #1,%d3 | ...Q := Q + 1 + +| + +Fix_Sign: +|..Get sign of X + movew SignX(%a6),%d6 + bges Get_Q + fnegx %fp0 + +|..Get Q +| +Get_Q: + clrl %d6 + movew SignQ(%a6),%d6 | ...D6 is sign(Q) + movel #8,%d7 + lsrl %d7,%d6 + andil #0x0000007F,%d3 | ...7 bits of Q + orl %d6,%d3 | ...sign and bits of Q + swap %d3 + fmovel %fpsr,%d6 + andil #0xFF00FFFF,%d6 + orl %d3,%d6 + fmovel %d6,%fpsr | ...put Q in fpsr + +| +Restore: + moveml (%a7)+,%d2-%d7 + fmovel USER_FPCR(%a6),%fpcr + movel Sc_Flag(%a6),%d0 + beqs Finish + fmulx Scale(%pc),%fp0 | ...may cause underflow + bra t_avoid_unsupp |check for denorm as a +| ;result of the scaling + +Finish: + fmovex %fp0,%fp0 |capture exceptions & round + rts + +Rem_is_0: +|..R = 2^(-j)X - Q Y = Y, thus R = 0 and quotient = 2^j (Q+1) + addql #1,%d3 + cmpil #8,%d0 | ...D0 is j + bges Q_Big + + lsll %d0,%d3 + bras Set_R_0 + +Q_Big: + clrl %d3 + +Set_R_0: + fmoves #0x00000000,%fp0 + movel #0,Sc_Flag(%a6) + bra Fix_Sign + +Tie_Case: +|..Check parity of Q + movel %d3,%d6 + andil #0x00000001,%d6 + tstl %d6 + beq Fix_Sign | ...Q is even + +|..Q is odd, Q := Q + 1, signX := -signX + addql #1,%d3 + movew SignX(%a6),%d6 + eoril #0x00008000,%d6 + movew %d6,SignX(%a6) + bra Fix_Sign + + |end diff --git a/arch/m68k/fpsp040/ssin.S b/arch/m68k/fpsp040/ssin.S new file mode 100644 index 000000000..a1ef8e01b --- /dev/null +++ b/arch/m68k/fpsp040/ssin.S @@ -0,0 +1,745 @@ +| +| ssin.sa 3.3 7/29/91 +| +| The entry point sSIN computes the sine of an input argument +| sCOS computes the cosine, and sSINCOS computes both. The +| corresponding entry points with a "d" computes the same +| corresponding function values for denormalized inputs. +| +| Input: Double-extended number X in location pointed to +| by address register a0. +| +| Output: The function value sin(X) or cos(X) returned in Fp0 if SIN or +| COS is requested. Otherwise, for SINCOS, sin(X) is returned +| in Fp0, and cos(X) is returned in Fp1. +| +| Modifies: Fp0 for SIN or COS; both Fp0 and Fp1 for SINCOS. +| +| Accuracy and Monotonicity: The returned result is within 1 ulp in +| 64 significant bit, i.e. within 0.5001 ulp to 53 bits if the +| result is subsequently rounded to double precision. The +| result is provably monotonic in double precision. +| +| Speed: The programs sSIN and sCOS take approximately 150 cycles for +| input argument X such that |X| < 15Pi, which is the usual +| situation. The speed for sSINCOS is approximately 190 cycles. +| +| Algorithm: +| +| SIN and COS: +| 1. If SIN is invoked, set AdjN := 0; otherwise, set AdjN := 1. +| +| 2. If |X| >= 15Pi or |X| < 2**(-40), go to 7. +| +| 3. Decompose X as X = N(Pi/2) + r where |r| <= Pi/4. Let +| k = N mod 4, so in particular, k = 0,1,2,or 3. Overwrite +| k by k := k + AdjN. +| +| 4. If k is even, go to 6. +| +| 5. (k is odd) Set j := (k-1)/2, sgn := (-1)**j. Return sgn*cos(r) +| where cos(r) is approximated by an even polynomial in r, +| 1 + r*r*(B1+s*(B2+ ... + s*B8)), s = r*r. +| Exit. +| +| 6. (k is even) Set j := k/2, sgn := (-1)**j. Return sgn*sin(r) +| where sin(r) is approximated by an odd polynomial in r +| r + r*s*(A1+s*(A2+ ... + s*A7)), s = r*r. +| Exit. +| +| 7. If |X| > 1, go to 9. +| +| 8. (|X|<2**(-40)) If SIN is invoked, return X; otherwise return 1. +| +| 9. Overwrite X by X := X rem 2Pi. Now that |X| <= Pi, go back to 3. +| +| SINCOS: +| 1. If |X| >= 15Pi or |X| < 2**(-40), go to 6. +| +| 2. Decompose X as X = N(Pi/2) + r where |r| <= Pi/4. Let +| k = N mod 4, so in particular, k = 0,1,2,or 3. +| +| 3. If k is even, go to 5. +| +| 4. (k is odd) Set j1 := (k-1)/2, j2 := j1 (EOR) (k mod 2), i.e. +| j1 exclusive or with the l.s.b. of k. +| sgn1 := (-1)**j1, sgn2 := (-1)**j2. +| SIN(X) = sgn1 * cos(r) and COS(X) = sgn2*sin(r) where +| sin(r) and cos(r) are computed as odd and even polynomials +| in r, respectively. Exit +| +| 5. (k is even) Set j1 := k/2, sgn1 := (-1)**j1. +| SIN(X) = sgn1 * sin(r) and COS(X) = sgn1*cos(r) where +| sin(r) and cos(r) are computed as odd and even polynomials +| in r, respectively. Exit +| +| 6. If |X| > 1, go to 8. +| +| 7. (|X|<2**(-40)) SIN(X) = X and COS(X) = 1. Exit. +| +| 8. Overwrite X by X := X rem 2Pi. Now that |X| <= Pi, go back to 2. +| + +| Copyright (C) Motorola, Inc. 1990 +| All Rights Reserved +| +| For details on the license for this file, please see the +| file, README, in this same directory. + +|SSIN idnt 2,1 | Motorola 040 Floating Point Software Package + + |section 8 + +#include "fpsp.h" + +BOUNDS1: .long 0x3FD78000,0x4004BC7E +TWOBYPI: .long 0x3FE45F30,0x6DC9C883 + +SINA7: .long 0xBD6AAA77,0xCCC994F5 +SINA6: .long 0x3DE61209,0x7AAE8DA1 + +SINA5: .long 0xBE5AE645,0x2A118AE4 +SINA4: .long 0x3EC71DE3,0xA5341531 + +SINA3: .long 0xBF2A01A0,0x1A018B59,0x00000000,0x00000000 + +SINA2: .long 0x3FF80000,0x88888888,0x888859AF,0x00000000 + +SINA1: .long 0xBFFC0000,0xAAAAAAAA,0xAAAAAA99,0x00000000 + +COSB8: .long 0x3D2AC4D0,0xD6011EE3 +COSB7: .long 0xBDA9396F,0x9F45AC19 + +COSB6: .long 0x3E21EED9,0x0612C972 +COSB5: .long 0xBE927E4F,0xB79D9FCF + +COSB4: .long 0x3EFA01A0,0x1A01D423,0x00000000,0x00000000 + +COSB3: .long 0xBFF50000,0xB60B60B6,0x0B61D438,0x00000000 + +COSB2: .long 0x3FFA0000,0xAAAAAAAA,0xAAAAAB5E +COSB1: .long 0xBF000000 + +INVTWOPI: .long 0x3FFC0000,0xA2F9836E,0x4E44152A + +TWOPI1: .long 0x40010000,0xC90FDAA2,0x00000000,0x00000000 +TWOPI2: .long 0x3FDF0000,0x85A308D4,0x00000000,0x00000000 + + |xref PITBL + + .set INARG,FP_SCR4 + + .set X,FP_SCR5 + .set XDCARE,X+2 + .set XFRAC,X+4 + + .set RPRIME,FP_SCR1 + .set SPRIME,FP_SCR2 + + .set POSNEG1,L_SCR1 + .set TWOTO63,L_SCR1 + + .set ENDFLAG,L_SCR2 + .set N,L_SCR2 + + .set ADJN,L_SCR3 + + | xref t_frcinx + |xref t_extdnrm + |xref sto_cos + + .global ssind +ssind: +|--SIN(X) = X FOR DENORMALIZED X + bra t_extdnrm + + .global scosd +scosd: +|--COS(X) = 1 FOR DENORMALIZED X + + fmoves #0x3F800000,%fp0 +| +| 9D25B Fix: Sometimes the previous fmove.s sets fpsr bits +| + fmovel #0,%fpsr +| + bra t_frcinx + + .global ssin +ssin: +|--SET ADJN TO 0 + movel #0,ADJN(%a6) + bras SINBGN + + .global scos +scos: +|--SET ADJN TO 1 + movel #1,ADJN(%a6) + +SINBGN: +|--SAVE FPCR, FP1. CHECK IF |X| IS TOO SMALL OR LARGE + + fmovex (%a0),%fp0 | ...LOAD INPUT + + movel (%a0),%d0 + movew 4(%a0),%d0 + fmovex %fp0,X(%a6) + andil #0x7FFFFFFF,%d0 | ...COMPACTIFY X + + cmpil #0x3FD78000,%d0 | ...|X| >= 2**(-40)? + bges SOK1 + bra SINSM + +SOK1: + cmpil #0x4004BC7E,%d0 | ...|X| < 15 PI? + blts SINMAIN + bra REDUCEX + +SINMAIN: +|--THIS IS THE USUAL CASE, |X| <= 15 PI. +|--THE ARGUMENT REDUCTION IS DONE BY TABLE LOOK UP. + fmovex %fp0,%fp1 + fmuld TWOBYPI,%fp1 | ...X*2/PI + +|--HIDE THE NEXT THREE INSTRUCTIONS + lea PITBL+0x200,%a1 | ...TABLE OF N*PI/2, N = -32,...,32 + + +|--FP1 IS NOW READY + fmovel %fp1,N(%a6) | ...CONVERT TO INTEGER + + movel N(%a6),%d0 + asll #4,%d0 + addal %d0,%a1 | ...A1 IS THE ADDRESS OF N*PIBY2 +| ...WHICH IS IN TWO PIECES Y1 & Y2 + + fsubx (%a1)+,%fp0 | ...X-Y1 +|--HIDE THE NEXT ONE + fsubs (%a1),%fp0 | ...FP0 IS R = (X-Y1)-Y2 + +SINCONT: +|--continuation from REDUCEX + +|--GET N+ADJN AND SEE IF SIN(R) OR COS(R) IS NEEDED + movel N(%a6),%d0 + addl ADJN(%a6),%d0 | ...SEE IF D0 IS ODD OR EVEN + rorl #1,%d0 | ...D0 WAS ODD IFF D0 IS NEGATIVE + cmpil #0,%d0 + blt COSPOLY + +SINPOLY: +|--LET J BE THE LEAST SIG. BIT OF D0, LET SGN := (-1)**J. +|--THEN WE RETURN SGN*SIN(R). SGN*SIN(R) IS COMPUTED BY +|--R' + R'*S*(A1 + S(A2 + S(A3 + S(A4 + ... + SA7)))), WHERE +|--R' = SGN*R, S=R*R. THIS CAN BE REWRITTEN AS +|--R' + R'*S*( [A1+T(A3+T(A5+TA7))] + [S(A2+T(A4+TA6))]) +|--WHERE T=S*S. +|--NOTE THAT A3 THROUGH A7 ARE STORED IN DOUBLE PRECISION +|--WHILE A1 AND A2 ARE IN DOUBLE-EXTENDED FORMAT. + fmovex %fp0,X(%a6) | ...X IS R + fmulx %fp0,%fp0 | ...FP0 IS S +|---HIDE THE NEXT TWO WHILE WAITING FOR FP0 + fmoved SINA7,%fp3 + fmoved SINA6,%fp2 +|--FP0 IS NOW READY + fmovex %fp0,%fp1 + fmulx %fp1,%fp1 | ...FP1 IS T +|--HIDE THE NEXT TWO WHILE WAITING FOR FP1 + + rorl #1,%d0 + andil #0x80000000,%d0 +| ...LEAST SIG. BIT OF D0 IN SIGN POSITION + eorl %d0,X(%a6) | ...X IS NOW R'= SGN*R + + fmulx %fp1,%fp3 | ...TA7 + fmulx %fp1,%fp2 | ...TA6 + + faddd SINA5,%fp3 | ...A5+TA7 + faddd SINA4,%fp2 | ...A4+TA6 + + fmulx %fp1,%fp3 | ...T(A5+TA7) + fmulx %fp1,%fp2 | ...T(A4+TA6) + + faddd SINA3,%fp3 | ...A3+T(A5+TA7) + faddx SINA2,%fp2 | ...A2+T(A4+TA6) + + fmulx %fp3,%fp1 | ...T(A3+T(A5+TA7)) + + fmulx %fp0,%fp2 | ...S(A2+T(A4+TA6)) + faddx SINA1,%fp1 | ...A1+T(A3+T(A5+TA7)) + fmulx X(%a6),%fp0 | ...R'*S + + faddx %fp2,%fp1 | ...[A1+T(A3+T(A5+TA7))]+[S(A2+T(A4+TA6))] +|--FP3 RELEASED, RESTORE NOW AND TAKE SOME ADVANTAGE OF HIDING +|--FP2 RELEASED, RESTORE NOW AND TAKE FULL ADVANTAGE OF HIDING + + + fmulx %fp1,%fp0 | ...SIN(R')-R' +|--FP1 RELEASED. + + fmovel %d1,%FPCR |restore users exceptions + faddx X(%a6),%fp0 |last inst - possible exception set + bra t_frcinx + + +COSPOLY: +|--LET J BE THE LEAST SIG. BIT OF D0, LET SGN := (-1)**J. +|--THEN WE RETURN SGN*COS(R). SGN*COS(R) IS COMPUTED BY +|--SGN + S'*(B1 + S(B2 + S(B3 + S(B4 + ... + SB8)))), WHERE +|--S=R*R AND S'=SGN*S. THIS CAN BE REWRITTEN AS +|--SGN + S'*([B1+T(B3+T(B5+TB7))] + [S(B2+T(B4+T(B6+TB8)))]) +|--WHERE T=S*S. +|--NOTE THAT B4 THROUGH B8 ARE STORED IN DOUBLE PRECISION +|--WHILE B2 AND B3 ARE IN DOUBLE-EXTENDED FORMAT, B1 IS -1/2 +|--AND IS THEREFORE STORED AS SINGLE PRECISION. + + fmulx %fp0,%fp0 | ...FP0 IS S +|---HIDE THE NEXT TWO WHILE WAITING FOR FP0 + fmoved COSB8,%fp2 + fmoved COSB7,%fp3 +|--FP0 IS NOW READY + fmovex %fp0,%fp1 + fmulx %fp1,%fp1 | ...FP1 IS T +|--HIDE THE NEXT TWO WHILE WAITING FOR FP1 + fmovex %fp0,X(%a6) | ...X IS S + rorl #1,%d0 + andil #0x80000000,%d0 +| ...LEAST SIG. BIT OF D0 IN SIGN POSITION + + fmulx %fp1,%fp2 | ...TB8 +|--HIDE THE NEXT TWO WHILE WAITING FOR THE XU + eorl %d0,X(%a6) | ...X IS NOW S'= SGN*S + andil #0x80000000,%d0 + + fmulx %fp1,%fp3 | ...TB7 +|--HIDE THE NEXT TWO WHILE WAITING FOR THE XU + oril #0x3F800000,%d0 | ...D0 IS SGN IN SINGLE + movel %d0,POSNEG1(%a6) + + faddd COSB6,%fp2 | ...B6+TB8 + faddd COSB5,%fp3 | ...B5+TB7 + + fmulx %fp1,%fp2 | ...T(B6+TB8) + fmulx %fp1,%fp3 | ...T(B5+TB7) + + faddd COSB4,%fp2 | ...B4+T(B6+TB8) + faddx COSB3,%fp3 | ...B3+T(B5+TB7) + + fmulx %fp1,%fp2 | ...T(B4+T(B6+TB8)) + fmulx %fp3,%fp1 | ...T(B3+T(B5+TB7)) + + faddx COSB2,%fp2 | ...B2+T(B4+T(B6+TB8)) + fadds COSB1,%fp1 | ...B1+T(B3+T(B5+TB7)) + + fmulx %fp2,%fp0 | ...S(B2+T(B4+T(B6+TB8))) +|--FP3 RELEASED, RESTORE NOW AND TAKE SOME ADVANTAGE OF HIDING +|--FP2 RELEASED. + + + faddx %fp1,%fp0 +|--FP1 RELEASED + + fmulx X(%a6),%fp0 + + fmovel %d1,%FPCR |restore users exceptions + fadds POSNEG1(%a6),%fp0 |last inst - possible exception set + bra t_frcinx + + +SINBORS: +|--IF |X| > 15PI, WE USE THE GENERAL ARGUMENT REDUCTION. +|--IF |X| < 2**(-40), RETURN X OR 1. + cmpil #0x3FFF8000,%d0 + bgts REDUCEX + + +SINSM: + movel ADJN(%a6),%d0 + cmpil #0,%d0 + bgts COSTINY + +SINTINY: + movew #0x0000,XDCARE(%a6) | ...JUST IN CASE + fmovel %d1,%FPCR |restore users exceptions + fmovex X(%a6),%fp0 |last inst - possible exception set + bra t_frcinx + + +COSTINY: + fmoves #0x3F800000,%fp0 + + fmovel %d1,%FPCR |restore users exceptions + fsubs #0x00800000,%fp0 |last inst - possible exception set + bra t_frcinx + + +REDUCEX: +|--WHEN REDUCEX IS USED, THE CODE WILL INEVITABLY BE SLOW. +|--THIS REDUCTION METHOD, HOWEVER, IS MUCH FASTER THAN USING +|--THE REMAINDER INSTRUCTION WHICH IS NOW IN SOFTWARE. + + fmovemx %fp2-%fp5,-(%a7) | ...save FP2 through FP5 + movel %d2,-(%a7) + fmoves #0x00000000,%fp1 +|--If compact form of abs(arg) in d0=$7ffeffff, argument is so large that +|--there is a danger of unwanted overflow in first LOOP iteration. In this +|--case, reduce argument by one remainder step to make subsequent reduction +|--safe. + cmpil #0x7ffeffff,%d0 |is argument dangerously large? + bnes LOOP + movel #0x7ffe0000,FP_SCR2(%a6) |yes +| ;create 2**16383*PI/2 + movel #0xc90fdaa2,FP_SCR2+4(%a6) + clrl FP_SCR2+8(%a6) + ftstx %fp0 |test sign of argument + movel #0x7fdc0000,FP_SCR3(%a6) |create low half of 2**16383* +| ;PI/2 at FP_SCR3 + movel #0x85a308d3,FP_SCR3+4(%a6) + clrl FP_SCR3+8(%a6) + fblt red_neg + orw #0x8000,FP_SCR2(%a6) |positive arg + orw #0x8000,FP_SCR3(%a6) +red_neg: + faddx FP_SCR2(%a6),%fp0 |high part of reduction is exact + fmovex %fp0,%fp1 |save high result in fp1 + faddx FP_SCR3(%a6),%fp0 |low part of reduction + fsubx %fp0,%fp1 |determine low component of result + faddx FP_SCR3(%a6),%fp1 |fp0/fp1 are reduced argument. + +|--ON ENTRY, FP0 IS X, ON RETURN, FP0 IS X REM PI/2, |X| <= PI/4. +|--integer quotient will be stored in N +|--Intermediate remainder is 66-bit long; (R,r) in (FP0,FP1) + +LOOP: + fmovex %fp0,INARG(%a6) | ...+-2**K * F, 1 <= F < 2 + movew INARG(%a6),%d0 + movel %d0,%a1 | ...save a copy of D0 + andil #0x00007FFF,%d0 + subil #0x00003FFF,%d0 | ...D0 IS K + cmpil #28,%d0 + bles LASTLOOP +CONTLOOP: + subil #27,%d0 | ...D0 IS L := K-27 + movel #0,ENDFLAG(%a6) + bras WORK +LASTLOOP: + clrl %d0 | ...D0 IS L := 0 + movel #1,ENDFLAG(%a6) + +WORK: +|--FIND THE REMAINDER OF (R,r) W.R.T. 2**L * (PI/2). L IS SO CHOSEN +|--THAT INT( X * (2/PI) / 2**(L) ) < 2**29. + +|--CREATE 2**(-L) * (2/PI), SIGN(INARG)*2**(63), +|--2**L * (PIby2_1), 2**L * (PIby2_2) + + movel #0x00003FFE,%d2 | ...BIASED EXPO OF 2/PI + subl %d0,%d2 | ...BIASED EXPO OF 2**(-L)*(2/PI) + + movel #0xA2F9836E,FP_SCR1+4(%a6) + movel #0x4E44152A,FP_SCR1+8(%a6) + movew %d2,FP_SCR1(%a6) | ...FP_SCR1 is 2**(-L)*(2/PI) + + fmovex %fp0,%fp2 + fmulx FP_SCR1(%a6),%fp2 +|--WE MUST NOW FIND INT(FP2). SINCE WE NEED THIS VALUE IN +|--FLOATING POINT FORMAT, THE TWO FMOVE'S FMOVE.L FP <--> N +|--WILL BE TOO INEFFICIENT. THE WAY AROUND IT IS THAT +|--(SIGN(INARG)*2**63 + FP2) - SIGN(INARG)*2**63 WILL GIVE +|--US THE DESIRED VALUE IN FLOATING POINT. + +|--HIDE SIX CYCLES OF INSTRUCTION + movel %a1,%d2 + swap %d2 + andil #0x80000000,%d2 + oril #0x5F000000,%d2 | ...D2 IS SIGN(INARG)*2**63 IN SGL + movel %d2,TWOTO63(%a6) + + movel %d0,%d2 + addil #0x00003FFF,%d2 | ...BIASED EXPO OF 2**L * (PI/2) + +|--FP2 IS READY + fadds TWOTO63(%a6),%fp2 | ...THE FRACTIONAL PART OF FP1 IS ROUNDED + +|--HIDE 4 CYCLES OF INSTRUCTION; creating 2**(L)*Piby2_1 and 2**(L)*Piby2_2 + movew %d2,FP_SCR2(%a6) + clrw FP_SCR2+2(%a6) + movel #0xC90FDAA2,FP_SCR2+4(%a6) + clrl FP_SCR2+8(%a6) | ...FP_SCR2 is 2**(L) * Piby2_1 + +|--FP2 IS READY + fsubs TWOTO63(%a6),%fp2 | ...FP2 is N + + addil #0x00003FDD,%d0 + movew %d0,FP_SCR3(%a6) + clrw FP_SCR3+2(%a6) + movel #0x85A308D3,FP_SCR3+4(%a6) + clrl FP_SCR3+8(%a6) | ...FP_SCR3 is 2**(L) * Piby2_2 + + movel ENDFLAG(%a6),%d0 + +|--We are now ready to perform (R+r) - N*P1 - N*P2, P1 = 2**(L) * Piby2_1 and +|--P2 = 2**(L) * Piby2_2 + fmovex %fp2,%fp4 + fmulx FP_SCR2(%a6),%fp4 | ...W = N*P1 + fmovex %fp2,%fp5 + fmulx FP_SCR3(%a6),%fp5 | ...w = N*P2 + fmovex %fp4,%fp3 +|--we want P+p = W+w but |p| <= half ulp of P +|--Then, we need to compute A := R-P and a := r-p + faddx %fp5,%fp3 | ...FP3 is P + fsubx %fp3,%fp4 | ...W-P + + fsubx %fp3,%fp0 | ...FP0 is A := R - P + faddx %fp5,%fp4 | ...FP4 is p = (W-P)+w + + fmovex %fp0,%fp3 | ...FP3 A + fsubx %fp4,%fp1 | ...FP1 is a := r - p + +|--Now we need to normalize (A,a) to "new (R,r)" where R+r = A+a but +|--|r| <= half ulp of R. + faddx %fp1,%fp0 | ...FP0 is R := A+a +|--No need to calculate r if this is the last loop + cmpil #0,%d0 + bgt RESTORE + +|--Need to calculate r + fsubx %fp0,%fp3 | ...A-R + faddx %fp3,%fp1 | ...FP1 is r := (A-R)+a + bra LOOP + +RESTORE: + fmovel %fp2,N(%a6) + movel (%a7)+,%d2 + fmovemx (%a7)+,%fp2-%fp5 + + + movel ADJN(%a6),%d0 + cmpil #4,%d0 + + blt SINCONT + bras SCCONT + + .global ssincosd +ssincosd: +|--SIN AND COS OF X FOR DENORMALIZED X + + fmoves #0x3F800000,%fp1 + bsr sto_cos |store cosine result + bra t_extdnrm + + .global ssincos +ssincos: +|--SET ADJN TO 4 + movel #4,ADJN(%a6) + + fmovex (%a0),%fp0 | ...LOAD INPUT + + movel (%a0),%d0 + movew 4(%a0),%d0 + fmovex %fp0,X(%a6) + andil #0x7FFFFFFF,%d0 | ...COMPACTIFY X + + cmpil #0x3FD78000,%d0 | ...|X| >= 2**(-40)? + bges SCOK1 + bra SCSM + +SCOK1: + cmpil #0x4004BC7E,%d0 | ...|X| < 15 PI? + blts SCMAIN + bra REDUCEX + + +SCMAIN: +|--THIS IS THE USUAL CASE, |X| <= 15 PI. +|--THE ARGUMENT REDUCTION IS DONE BY TABLE LOOK UP. + fmovex %fp0,%fp1 + fmuld TWOBYPI,%fp1 | ...X*2/PI + +|--HIDE THE NEXT THREE INSTRUCTIONS + lea PITBL+0x200,%a1 | ...TABLE OF N*PI/2, N = -32,...,32 + + +|--FP1 IS NOW READY + fmovel %fp1,N(%a6) | ...CONVERT TO INTEGER + + movel N(%a6),%d0 + asll #4,%d0 + addal %d0,%a1 | ...ADDRESS OF N*PIBY2, IN Y1, Y2 + + fsubx (%a1)+,%fp0 | ...X-Y1 + fsubs (%a1),%fp0 | ...FP0 IS R = (X-Y1)-Y2 + +SCCONT: +|--continuation point from REDUCEX + +|--HIDE THE NEXT TWO + movel N(%a6),%d0 + rorl #1,%d0 + + cmpil #0,%d0 | ...D0 < 0 IFF N IS ODD + bge NEVEN + +NODD: +|--REGISTERS SAVED SO FAR: D0, A0, FP2. + + fmovex %fp0,RPRIME(%a6) + fmulx %fp0,%fp0 | ...FP0 IS S = R*R + fmoved SINA7,%fp1 | ...A7 + fmoved COSB8,%fp2 | ...B8 + fmulx %fp0,%fp1 | ...SA7 + movel %d2,-(%a7) + movel %d0,%d2 + fmulx %fp0,%fp2 | ...SB8 + rorl #1,%d2 + andil #0x80000000,%d2 + + faddd SINA6,%fp1 | ...A6+SA7 + eorl %d0,%d2 + andil #0x80000000,%d2 + faddd COSB7,%fp2 | ...B7+SB8 + + fmulx %fp0,%fp1 | ...S(A6+SA7) + eorl %d2,RPRIME(%a6) + movel (%a7)+,%d2 + fmulx %fp0,%fp2 | ...S(B7+SB8) + rorl #1,%d0 + andil #0x80000000,%d0 + + faddd SINA5,%fp1 | ...A5+S(A6+SA7) + movel #0x3F800000,POSNEG1(%a6) + eorl %d0,POSNEG1(%a6) + faddd COSB6,%fp2 | ...B6+S(B7+SB8) + + fmulx %fp0,%fp1 | ...S(A5+S(A6+SA7)) + fmulx %fp0,%fp2 | ...S(B6+S(B7+SB8)) + fmovex %fp0,SPRIME(%a6) + + faddd SINA4,%fp1 | ...A4+S(A5+S(A6+SA7)) + eorl %d0,SPRIME(%a6) + faddd COSB5,%fp2 | ...B5+S(B6+S(B7+SB8)) + + fmulx %fp0,%fp1 | ...S(A4+...) + fmulx %fp0,%fp2 | ...S(B5+...) + + faddd SINA3,%fp1 | ...A3+S(A4+...) + faddd COSB4,%fp2 | ...B4+S(B5+...) + + fmulx %fp0,%fp1 | ...S(A3+...) + fmulx %fp0,%fp2 | ...S(B4+...) + + faddx SINA2,%fp1 | ...A2+S(A3+...) + faddx COSB3,%fp2 | ...B3+S(B4+...) + + fmulx %fp0,%fp1 | ...S(A2+...) + fmulx %fp0,%fp2 | ...S(B3+...) + + faddx SINA1,%fp1 | ...A1+S(A2+...) + faddx COSB2,%fp2 | ...B2+S(B3+...) + + fmulx %fp0,%fp1 | ...S(A1+...) + fmulx %fp2,%fp0 | ...S(B2+...) + + + + fmulx RPRIME(%a6),%fp1 | ...R'S(A1+...) + fadds COSB1,%fp0 | ...B1+S(B2...) + fmulx SPRIME(%a6),%fp0 | ...S'(B1+S(B2+...)) + + movel %d1,-(%sp) |restore users mode & precision + andil #0xff,%d1 |mask off all exceptions + fmovel %d1,%FPCR + faddx RPRIME(%a6),%fp1 | ...COS(X) + bsr sto_cos |store cosine result + fmovel (%sp)+,%FPCR |restore users exceptions + fadds POSNEG1(%a6),%fp0 | ...SIN(X) + + bra t_frcinx + + +NEVEN: +|--REGISTERS SAVED SO FAR: FP2. + + fmovex %fp0,RPRIME(%a6) + fmulx %fp0,%fp0 | ...FP0 IS S = R*R + fmoved COSB8,%fp1 | ...B8 + fmoved SINA7,%fp2 | ...A7 + fmulx %fp0,%fp1 | ...SB8 + fmovex %fp0,SPRIME(%a6) + fmulx %fp0,%fp2 | ...SA7 + rorl #1,%d0 + andil #0x80000000,%d0 + faddd COSB7,%fp1 | ...B7+SB8 + faddd SINA6,%fp2 | ...A6+SA7 + eorl %d0,RPRIME(%a6) + eorl %d0,SPRIME(%a6) + fmulx %fp0,%fp1 | ...S(B7+SB8) + oril #0x3F800000,%d0 + movel %d0,POSNEG1(%a6) + fmulx %fp0,%fp2 | ...S(A6+SA7) + + faddd COSB6,%fp1 | ...B6+S(B7+SB8) + faddd SINA5,%fp2 | ...A5+S(A6+SA7) + + fmulx %fp0,%fp1 | ...S(B6+S(B7+SB8)) + fmulx %fp0,%fp2 | ...S(A5+S(A6+SA7)) + + faddd COSB5,%fp1 | ...B5+S(B6+S(B7+SB8)) + faddd SINA4,%fp2 | ...A4+S(A5+S(A6+SA7)) + + fmulx %fp0,%fp1 | ...S(B5+...) + fmulx %fp0,%fp2 | ...S(A4+...) + + faddd COSB4,%fp1 | ...B4+S(B5+...) + faddd SINA3,%fp2 | ...A3+S(A4+...) + + fmulx %fp0,%fp1 | ...S(B4+...) + fmulx %fp0,%fp2 | ...S(A3+...) + + faddx COSB3,%fp1 | ...B3+S(B4+...) + faddx SINA2,%fp2 | ...A2+S(A3+...) + + fmulx %fp0,%fp1 | ...S(B3+...) + fmulx %fp0,%fp2 | ...S(A2+...) + + faddx COSB2,%fp1 | ...B2+S(B3+...) + faddx SINA1,%fp2 | ...A1+S(A2+...) + + fmulx %fp0,%fp1 | ...S(B2+...) + fmulx %fp2,%fp0 | ...s(a1+...) + + + + fadds COSB1,%fp1 | ...B1+S(B2...) + fmulx RPRIME(%a6),%fp0 | ...R'S(A1+...) + fmulx SPRIME(%a6),%fp1 | ...S'(B1+S(B2+...)) + + movel %d1,-(%sp) |save users mode & precision + andil #0xff,%d1 |mask off all exceptions + fmovel %d1,%FPCR + fadds POSNEG1(%a6),%fp1 | ...COS(X) + bsr sto_cos |store cosine result + fmovel (%sp)+,%FPCR |restore users exceptions + faddx RPRIME(%a6),%fp0 | ...SIN(X) + + bra t_frcinx + +SCBORS: + cmpil #0x3FFF8000,%d0 + bgt REDUCEX + + +SCSM: + movew #0x0000,XDCARE(%a6) + fmoves #0x3F800000,%fp1 + + movel %d1,-(%sp) |save users mode & precision + andil #0xff,%d1 |mask off all exceptions + fmovel %d1,%FPCR + fsubs #0x00800000,%fp1 + bsr sto_cos |store cosine result + fmovel (%sp)+,%FPCR |restore users exceptions + fmovex X(%a6),%fp0 + bra t_frcinx + + |end diff --git a/arch/m68k/fpsp040/ssinh.S b/arch/m68k/fpsp040/ssinh.S new file mode 100644 index 000000000..8a560edc7 --- /dev/null +++ b/arch/m68k/fpsp040/ssinh.S @@ -0,0 +1,134 @@ +| +| ssinh.sa 3.1 12/10/90 +| +| The entry point sSinh computes the hyperbolic sine of +| an input argument; sSinhd does the same except for denormalized +| input. +| +| Input: Double-extended number X in location pointed to +| by address register a0. +| +| Output: The value sinh(X) returned in floating-point register Fp0. +| +| Accuracy and Monotonicity: The returned result is within 3 ulps in +| 64 significant bit, i.e. within 0.5001 ulp to 53 bits if the +| result is subsequently rounded to double precision. The +| result is provably monotonic in double precision. +| +| Speed: The program sSINH takes approximately 280 cycles. +| +| Algorithm: +| +| SINH +| 1. If |X| > 16380 log2, go to 3. +| +| 2. (|X| <= 16380 log2) Sinh(X) is obtained by the formulae +| y = |X|, sgn = sign(X), and z = expm1(Y), +| sinh(X) = sgn*(1/2)*( z + z/(1+z) ). +| Exit. +| +| 3. If |X| > 16480 log2, go to 5. +| +| 4. (16380 log2 < |X| <= 16480 log2) +| sinh(X) = sign(X) * exp(|X|)/2. +| However, invoking exp(|X|) may cause premature overflow. +| Thus, we calculate sinh(X) as follows: +| Y := |X| +| sgn := sign(X) +| sgnFact := sgn * 2**(16380) +| Y' := Y - 16381 log2 +| sinh(X) := sgnFact * exp(Y'). +| Exit. +| +| 5. (|X| > 16480 log2) sinh(X) must overflow. Return +| sign(X)*Huge*Huge to generate overflow and an infinity with +| the appropriate sign. Huge is the largest finite number in +| extended format. Exit. +| + +| Copyright (C) Motorola, Inc. 1990 +| All Rights Reserved +| +| For details on the license for this file, please see the +| file, README, in this same directory. + +|SSINH idnt 2,1 | Motorola 040 Floating Point Software Package + + |section 8 + +T1: .long 0x40C62D38,0xD3D64634 | ... 16381 LOG2 LEAD +T2: .long 0x3D6F90AE,0xB1E75CC7 | ... 16381 LOG2 TRAIL + + |xref t_frcinx + |xref t_ovfl + |xref t_extdnrm + |xref setox + |xref setoxm1 + + .global ssinhd +ssinhd: +|--SINH(X) = X FOR DENORMALIZED X + + bra t_extdnrm + + .global ssinh +ssinh: + fmovex (%a0),%fp0 | ...LOAD INPUT + + movel (%a0),%d0 + movew 4(%a0),%d0 + movel %d0,%a1 | save a copy of original (compacted) operand + andl #0x7FFFFFFF,%d0 + cmpl #0x400CB167,%d0 + bgts SINHBIG + +|--THIS IS THE USUAL CASE, |X| < 16380 LOG2 +|--Y = |X|, Z = EXPM1(Y), SINH(X) = SIGN(X)*(1/2)*( Z + Z/(1+Z) ) + + fabsx %fp0 | ...Y = |X| + + moveml %a1/%d1,-(%sp) + fmovemx %fp0-%fp0,(%a0) + clrl %d1 + bsr setoxm1 | ...FP0 IS Z = EXPM1(Y) + fmovel #0,%fpcr + moveml (%sp)+,%a1/%d1 + + fmovex %fp0,%fp1 + fadds #0x3F800000,%fp1 | ...1+Z + fmovex %fp0,-(%sp) + fdivx %fp1,%fp0 | ...Z/(1+Z) + movel %a1,%d0 + andl #0x80000000,%d0 + orl #0x3F000000,%d0 + faddx (%sp)+,%fp0 + movel %d0,-(%sp) + + fmovel %d1,%fpcr + fmuls (%sp)+,%fp0 |last fp inst - possible exceptions set + + bra t_frcinx + +SINHBIG: + cmpl #0x400CB2B3,%d0 + bgt t_ovfl + fabsx %fp0 + fsubd T1(%pc),%fp0 | ...(|X|-16381LOG2_LEAD) + movel #0,-(%sp) + movel #0x80000000,-(%sp) + movel %a1,%d0 + andl #0x80000000,%d0 + orl #0x7FFB0000,%d0 + movel %d0,-(%sp) | ...EXTENDED FMT + fsubd T2(%pc),%fp0 | ...|X| - 16381 LOG2, ACCURATE + + movel %d1,-(%sp) + clrl %d1 + fmovemx %fp0-%fp0,(%a0) + bsr setox + fmovel (%sp)+,%fpcr + + fmulx (%sp)+,%fp0 |possible exception + bra t_frcinx + + |end diff --git a/arch/m68k/fpsp040/stan.S b/arch/m68k/fpsp040/stan.S new file mode 100644 index 000000000..f8553aaec --- /dev/null +++ b/arch/m68k/fpsp040/stan.S @@ -0,0 +1,454 @@ +| +| stan.sa 3.3 7/29/91 +| +| The entry point stan computes the tangent of +| an input argument; +| stand does the same except for denormalized input. +| +| Input: Double-extended number X in location pointed to +| by address register a0. +| +| Output: The value tan(X) returned in floating-point register Fp0. +| +| Accuracy and Monotonicity: The returned result is within 3 ulp in +| 64 significant bit, i.e. within 0.5001 ulp to 53 bits if the +| result is subsequently rounded to double precision. The +| result is provably monotonic in double precision. +| +| Speed: The program sTAN takes approximately 170 cycles for +| input argument X such that |X| < 15Pi, which is the usual +| situation. +| +| Algorithm: +| +| 1. If |X| >= 15Pi or |X| < 2**(-40), go to 6. +| +| 2. Decompose X as X = N(Pi/2) + r where |r| <= Pi/4. Let +| k = N mod 2, so in particular, k = 0 or 1. +| +| 3. If k is odd, go to 5. +| +| 4. (k is even) Tan(X) = tan(r) and tan(r) is approximated by a +| rational function U/V where +| U = r + r*s*(P1 + s*(P2 + s*P3)), and +| V = 1 + s*(Q1 + s*(Q2 + s*(Q3 + s*Q4))), s = r*r. +| Exit. +| +| 4. (k is odd) Tan(X) = -cot(r). Since tan(r) is approximated by a +| rational function U/V where +| U = r + r*s*(P1 + s*(P2 + s*P3)), and +| V = 1 + s*(Q1 + s*(Q2 + s*(Q3 + s*Q4))), s = r*r, +| -Cot(r) = -V/U. Exit. +| +| 6. If |X| > 1, go to 8. +| +| 7. (|X|<2**(-40)) Tan(X) = X. Exit. +| +| 8. Overwrite X by X := X rem 2Pi. Now that |X| <= Pi, go back to 2. +| + +| Copyright (C) Motorola, Inc. 1990 +| All Rights Reserved +| +| For details on the license for this file, please see the +| file, README, in this same directory. + +|STAN idnt 2,1 | Motorola 040 Floating Point Software Package + + |section 8 + +#include "fpsp.h" + +BOUNDS1: .long 0x3FD78000,0x4004BC7E +TWOBYPI: .long 0x3FE45F30,0x6DC9C883 + +TANQ4: .long 0x3EA0B759,0xF50F8688 +TANP3: .long 0xBEF2BAA5,0xA8924F04 + +TANQ3: .long 0xBF346F59,0xB39BA65F,0x00000000,0x00000000 + +TANP2: .long 0x3FF60000,0xE073D3FC,0x199C4A00,0x00000000 + +TANQ2: .long 0x3FF90000,0xD23CD684,0x15D95FA1,0x00000000 + +TANP1: .long 0xBFFC0000,0x8895A6C5,0xFB423BCA,0x00000000 + +TANQ1: .long 0xBFFD0000,0xEEF57E0D,0xA84BC8CE,0x00000000 + +INVTWOPI: .long 0x3FFC0000,0xA2F9836E,0x4E44152A,0x00000000 + +TWOPI1: .long 0x40010000,0xC90FDAA2,0x00000000,0x00000000 +TWOPI2: .long 0x3FDF0000,0x85A308D4,0x00000000,0x00000000 + +|--N*PI/2, -32 <= N <= 32, IN A LEADING TERM IN EXT. AND TRAILING +|--TERM IN SGL. NOTE THAT PI IS 64-BIT LONG, THUS N*PI/2 IS AT +|--MOST 69 BITS LONG. + .global PITBL +PITBL: + .long 0xC0040000,0xC90FDAA2,0x2168C235,0x21800000 + .long 0xC0040000,0xC2C75BCD,0x105D7C23,0xA0D00000 + .long 0xC0040000,0xBC7EDCF7,0xFF523611,0xA1E80000 + .long 0xC0040000,0xB6365E22,0xEE46F000,0x21480000 + .long 0xC0040000,0xAFEDDF4D,0xDD3BA9EE,0xA1200000 + .long 0xC0040000,0xA9A56078,0xCC3063DD,0x21FC0000 + .long 0xC0040000,0xA35CE1A3,0xBB251DCB,0x21100000 + .long 0xC0040000,0x9D1462CE,0xAA19D7B9,0xA1580000 + .long 0xC0040000,0x96CBE3F9,0x990E91A8,0x21E00000 + .long 0xC0040000,0x90836524,0x88034B96,0x20B00000 + .long 0xC0040000,0x8A3AE64F,0x76F80584,0xA1880000 + .long 0xC0040000,0x83F2677A,0x65ECBF73,0x21C40000 + .long 0xC0030000,0xFB53D14A,0xA9C2F2C2,0x20000000 + .long 0xC0030000,0xEEC2D3A0,0x87AC669F,0x21380000 + .long 0xC0030000,0xE231D5F6,0x6595DA7B,0xA1300000 + .long 0xC0030000,0xD5A0D84C,0x437F4E58,0x9FC00000 + .long 0xC0030000,0xC90FDAA2,0x2168C235,0x21000000 + .long 0xC0030000,0xBC7EDCF7,0xFF523611,0xA1680000 + .long 0xC0030000,0xAFEDDF4D,0xDD3BA9EE,0xA0A00000 + .long 0xC0030000,0xA35CE1A3,0xBB251DCB,0x20900000 + .long 0xC0030000,0x96CBE3F9,0x990E91A8,0x21600000 + .long 0xC0030000,0x8A3AE64F,0x76F80584,0xA1080000 + .long 0xC0020000,0xFB53D14A,0xA9C2F2C2,0x1F800000 + .long 0xC0020000,0xE231D5F6,0x6595DA7B,0xA0B00000 + .long 0xC0020000,0xC90FDAA2,0x2168C235,0x20800000 + .long 0xC0020000,0xAFEDDF4D,0xDD3BA9EE,0xA0200000 + .long 0xC0020000,0x96CBE3F9,0x990E91A8,0x20E00000 + .long 0xC0010000,0xFB53D14A,0xA9C2F2C2,0x1F000000 + .long 0xC0010000,0xC90FDAA2,0x2168C235,0x20000000 + .long 0xC0010000,0x96CBE3F9,0x990E91A8,0x20600000 + .long 0xC0000000,0xC90FDAA2,0x2168C235,0x1F800000 + .long 0xBFFF0000,0xC90FDAA2,0x2168C235,0x1F000000 + .long 0x00000000,0x00000000,0x00000000,0x00000000 + .long 0x3FFF0000,0xC90FDAA2,0x2168C235,0x9F000000 + .long 0x40000000,0xC90FDAA2,0x2168C235,0x9F800000 + .long 0x40010000,0x96CBE3F9,0x990E91A8,0xA0600000 + .long 0x40010000,0xC90FDAA2,0x2168C235,0xA0000000 + .long 0x40010000,0xFB53D14A,0xA9C2F2C2,0x9F000000 + .long 0x40020000,0x96CBE3F9,0x990E91A8,0xA0E00000 + .long 0x40020000,0xAFEDDF4D,0xDD3BA9EE,0x20200000 + .long 0x40020000,0xC90FDAA2,0x2168C235,0xA0800000 + .long 0x40020000,0xE231D5F6,0x6595DA7B,0x20B00000 + .long 0x40020000,0xFB53D14A,0xA9C2F2C2,0x9F800000 + .long 0x40030000,0x8A3AE64F,0x76F80584,0x21080000 + .long 0x40030000,0x96CBE3F9,0x990E91A8,0xA1600000 + .long 0x40030000,0xA35CE1A3,0xBB251DCB,0xA0900000 + .long 0x40030000,0xAFEDDF4D,0xDD3BA9EE,0x20A00000 + .long 0x40030000,0xBC7EDCF7,0xFF523611,0x21680000 + .long 0x40030000,0xC90FDAA2,0x2168C235,0xA1000000 + .long 0x40030000,0xD5A0D84C,0x437F4E58,0x1FC00000 + .long 0x40030000,0xE231D5F6,0x6595DA7B,0x21300000 + .long 0x40030000,0xEEC2D3A0,0x87AC669F,0xA1380000 + .long 0x40030000,0xFB53D14A,0xA9C2F2C2,0xA0000000 + .long 0x40040000,0x83F2677A,0x65ECBF73,0xA1C40000 + .long 0x40040000,0x8A3AE64F,0x76F80584,0x21880000 + .long 0x40040000,0x90836524,0x88034B96,0xA0B00000 + .long 0x40040000,0x96CBE3F9,0x990E91A8,0xA1E00000 + .long 0x40040000,0x9D1462CE,0xAA19D7B9,0x21580000 + .long 0x40040000,0xA35CE1A3,0xBB251DCB,0xA1100000 + .long 0x40040000,0xA9A56078,0xCC3063DD,0xA1FC0000 + .long 0x40040000,0xAFEDDF4D,0xDD3BA9EE,0x21200000 + .long 0x40040000,0xB6365E22,0xEE46F000,0xA1480000 + .long 0x40040000,0xBC7EDCF7,0xFF523611,0x21E80000 + .long 0x40040000,0xC2C75BCD,0x105D7C23,0x20D00000 + .long 0x40040000,0xC90FDAA2,0x2168C235,0xA1800000 + + .set INARG,FP_SCR4 + + .set TWOTO63,L_SCR1 + .set ENDFLAG,L_SCR2 + .set N,L_SCR3 + + | xref t_frcinx + |xref t_extdnrm + + .global stand +stand: +|--TAN(X) = X FOR DENORMALIZED X + + bra t_extdnrm + + .global stan +stan: + fmovex (%a0),%fp0 | ...LOAD INPUT + + movel (%a0),%d0 + movew 4(%a0),%d0 + andil #0x7FFFFFFF,%d0 + + cmpil #0x3FD78000,%d0 | ...|X| >= 2**(-40)? + bges TANOK1 + bra TANSM +TANOK1: + cmpil #0x4004BC7E,%d0 | ...|X| < 15 PI? + blts TANMAIN + bra REDUCEX + + +TANMAIN: +|--THIS IS THE USUAL CASE, |X| <= 15 PI. +|--THE ARGUMENT REDUCTION IS DONE BY TABLE LOOK UP. + fmovex %fp0,%fp1 + fmuld TWOBYPI,%fp1 | ...X*2/PI + +|--HIDE THE NEXT TWO INSTRUCTIONS + leal PITBL+0x200,%a1 | ...TABLE OF N*PI/2, N = -32,...,32 + +|--FP1 IS NOW READY + fmovel %fp1,%d0 | ...CONVERT TO INTEGER + + asll #4,%d0 + addal %d0,%a1 | ...ADDRESS N*PIBY2 IN Y1, Y2 + + fsubx (%a1)+,%fp0 | ...X-Y1 +|--HIDE THE NEXT ONE + + fsubs (%a1),%fp0 | ...FP0 IS R = (X-Y1)-Y2 + + rorl #5,%d0 + andil #0x80000000,%d0 | ...D0 WAS ODD IFF D0 < 0 + +TANCONT: + + cmpil #0,%d0 + blt NODD + + fmovex %fp0,%fp1 + fmulx %fp1,%fp1 | ...S = R*R + + fmoved TANQ4,%fp3 + fmoved TANP3,%fp2 + + fmulx %fp1,%fp3 | ...SQ4 + fmulx %fp1,%fp2 | ...SP3 + + faddd TANQ3,%fp3 | ...Q3+SQ4 + faddx TANP2,%fp2 | ...P2+SP3 + + fmulx %fp1,%fp3 | ...S(Q3+SQ4) + fmulx %fp1,%fp2 | ...S(P2+SP3) + + faddx TANQ2,%fp3 | ...Q2+S(Q3+SQ4) + faddx TANP1,%fp2 | ...P1+S(P2+SP3) + + fmulx %fp1,%fp3 | ...S(Q2+S(Q3+SQ4)) + fmulx %fp1,%fp2 | ...S(P1+S(P2+SP3)) + + faddx TANQ1,%fp3 | ...Q1+S(Q2+S(Q3+SQ4)) + fmulx %fp0,%fp2 | ...RS(P1+S(P2+SP3)) + + fmulx %fp3,%fp1 | ...S(Q1+S(Q2+S(Q3+SQ4))) + + + faddx %fp2,%fp0 | ...R+RS(P1+S(P2+SP3)) + + + fadds #0x3F800000,%fp1 | ...1+S(Q1+...) + + fmovel %d1,%fpcr |restore users exceptions + fdivx %fp1,%fp0 |last inst - possible exception set + + bra t_frcinx + +NODD: + fmovex %fp0,%fp1 + fmulx %fp0,%fp0 | ...S = R*R + + fmoved TANQ4,%fp3 + fmoved TANP3,%fp2 + + fmulx %fp0,%fp3 | ...SQ4 + fmulx %fp0,%fp2 | ...SP3 + + faddd TANQ3,%fp3 | ...Q3+SQ4 + faddx TANP2,%fp2 | ...P2+SP3 + + fmulx %fp0,%fp3 | ...S(Q3+SQ4) + fmulx %fp0,%fp2 | ...S(P2+SP3) + + faddx TANQ2,%fp3 | ...Q2+S(Q3+SQ4) + faddx TANP1,%fp2 | ...P1+S(P2+SP3) + + fmulx %fp0,%fp3 | ...S(Q2+S(Q3+SQ4)) + fmulx %fp0,%fp2 | ...S(P1+S(P2+SP3)) + + faddx TANQ1,%fp3 | ...Q1+S(Q2+S(Q3+SQ4)) + fmulx %fp1,%fp2 | ...RS(P1+S(P2+SP3)) + + fmulx %fp3,%fp0 | ...S(Q1+S(Q2+S(Q3+SQ4))) + + + faddx %fp2,%fp1 | ...R+RS(P1+S(P2+SP3)) + fadds #0x3F800000,%fp0 | ...1+S(Q1+...) + + + fmovex %fp1,-(%sp) + eoril #0x80000000,(%sp) + + fmovel %d1,%fpcr |restore users exceptions + fdivx (%sp)+,%fp0 |last inst - possible exception set + + bra t_frcinx + +TANBORS: +|--IF |X| > 15PI, WE USE THE GENERAL ARGUMENT REDUCTION. +|--IF |X| < 2**(-40), RETURN X OR 1. + cmpil #0x3FFF8000,%d0 + bgts REDUCEX + +TANSM: + + fmovex %fp0,-(%sp) + fmovel %d1,%fpcr |restore users exceptions + fmovex (%sp)+,%fp0 |last inst - possible exception set + + bra t_frcinx + + +REDUCEX: +|--WHEN REDUCEX IS USED, THE CODE WILL INEVITABLY BE SLOW. +|--THIS REDUCTION METHOD, HOWEVER, IS MUCH FASTER THAN USING +|--THE REMAINDER INSTRUCTION WHICH IS NOW IN SOFTWARE. + + fmovemx %fp2-%fp5,-(%a7) | ...save FP2 through FP5 + movel %d2,-(%a7) + fmoves #0x00000000,%fp1 + +|--If compact form of abs(arg) in d0=$7ffeffff, argument is so large that +|--there is a danger of unwanted overflow in first LOOP iteration. In this +|--case, reduce argument by one remainder step to make subsequent reduction +|--safe. + cmpil #0x7ffeffff,%d0 |is argument dangerously large? + bnes LOOP + movel #0x7ffe0000,FP_SCR2(%a6) |yes +| ;create 2**16383*PI/2 + movel #0xc90fdaa2,FP_SCR2+4(%a6) + clrl FP_SCR2+8(%a6) + ftstx %fp0 |test sign of argument + movel #0x7fdc0000,FP_SCR3(%a6) |create low half of 2**16383* +| ;PI/2 at FP_SCR3 + movel #0x85a308d3,FP_SCR3+4(%a6) + clrl FP_SCR3+8(%a6) + fblt red_neg + orw #0x8000,FP_SCR2(%a6) |positive arg + orw #0x8000,FP_SCR3(%a6) +red_neg: + faddx FP_SCR2(%a6),%fp0 |high part of reduction is exact + fmovex %fp0,%fp1 |save high result in fp1 + faddx FP_SCR3(%a6),%fp0 |low part of reduction + fsubx %fp0,%fp1 |determine low component of result + faddx FP_SCR3(%a6),%fp1 |fp0/fp1 are reduced argument. + +|--ON ENTRY, FP0 IS X, ON RETURN, FP0 IS X REM PI/2, |X| <= PI/4. +|--integer quotient will be stored in N +|--Intermediate remainder is 66-bit long; (R,r) in (FP0,FP1) + +LOOP: + fmovex %fp0,INARG(%a6) | ...+-2**K * F, 1 <= F < 2 + movew INARG(%a6),%d0 + movel %d0,%a1 | ...save a copy of D0 + andil #0x00007FFF,%d0 + subil #0x00003FFF,%d0 | ...D0 IS K + cmpil #28,%d0 + bles LASTLOOP +CONTLOOP: + subil #27,%d0 | ...D0 IS L := K-27 + movel #0,ENDFLAG(%a6) + bras WORK +LASTLOOP: + clrl %d0 | ...D0 IS L := 0 + movel #1,ENDFLAG(%a6) + +WORK: +|--FIND THE REMAINDER OF (R,r) W.R.T. 2**L * (PI/2). L IS SO CHOSEN +|--THAT INT( X * (2/PI) / 2**(L) ) < 2**29. + +|--CREATE 2**(-L) * (2/PI), SIGN(INARG)*2**(63), +|--2**L * (PIby2_1), 2**L * (PIby2_2) + + movel #0x00003FFE,%d2 | ...BIASED EXPO OF 2/PI + subl %d0,%d2 | ...BIASED EXPO OF 2**(-L)*(2/PI) + + movel #0xA2F9836E,FP_SCR1+4(%a6) + movel #0x4E44152A,FP_SCR1+8(%a6) + movew %d2,FP_SCR1(%a6) | ...FP_SCR1 is 2**(-L)*(2/PI) + + fmovex %fp0,%fp2 + fmulx FP_SCR1(%a6),%fp2 +|--WE MUST NOW FIND INT(FP2). SINCE WE NEED THIS VALUE IN +|--FLOATING POINT FORMAT, THE TWO FMOVE'S FMOVE.L FP <--> N +|--WILL BE TOO INEFFICIENT. THE WAY AROUND IT IS THAT +|--(SIGN(INARG)*2**63 + FP2) - SIGN(INARG)*2**63 WILL GIVE +|--US THE DESIRED VALUE IN FLOATING POINT. + +|--HIDE SIX CYCLES OF INSTRUCTION + movel %a1,%d2 + swap %d2 + andil #0x80000000,%d2 + oril #0x5F000000,%d2 | ...D2 IS SIGN(INARG)*2**63 IN SGL + movel %d2,TWOTO63(%a6) + + movel %d0,%d2 + addil #0x00003FFF,%d2 | ...BIASED EXPO OF 2**L * (PI/2) + +|--FP2 IS READY + fadds TWOTO63(%a6),%fp2 | ...THE FRACTIONAL PART OF FP1 IS ROUNDED + +|--HIDE 4 CYCLES OF INSTRUCTION; creating 2**(L)*Piby2_1 and 2**(L)*Piby2_2 + movew %d2,FP_SCR2(%a6) + clrw FP_SCR2+2(%a6) + movel #0xC90FDAA2,FP_SCR2+4(%a6) + clrl FP_SCR2+8(%a6) | ...FP_SCR2 is 2**(L) * Piby2_1 + +|--FP2 IS READY + fsubs TWOTO63(%a6),%fp2 | ...FP2 is N + + addil #0x00003FDD,%d0 + movew %d0,FP_SCR3(%a6) + clrw FP_SCR3+2(%a6) + movel #0x85A308D3,FP_SCR3+4(%a6) + clrl FP_SCR3+8(%a6) | ...FP_SCR3 is 2**(L) * Piby2_2 + + movel ENDFLAG(%a6),%d0 + +|--We are now ready to perform (R+r) - N*P1 - N*P2, P1 = 2**(L) * Piby2_1 and +|--P2 = 2**(L) * Piby2_2 + fmovex %fp2,%fp4 + fmulx FP_SCR2(%a6),%fp4 | ...W = N*P1 + fmovex %fp2,%fp5 + fmulx FP_SCR3(%a6),%fp5 | ...w = N*P2 + fmovex %fp4,%fp3 +|--we want P+p = W+w but |p| <= half ulp of P +|--Then, we need to compute A := R-P and a := r-p + faddx %fp5,%fp3 | ...FP3 is P + fsubx %fp3,%fp4 | ...W-P + + fsubx %fp3,%fp0 | ...FP0 is A := R - P + faddx %fp5,%fp4 | ...FP4 is p = (W-P)+w + + fmovex %fp0,%fp3 | ...FP3 A + fsubx %fp4,%fp1 | ...FP1 is a := r - p + +|--Now we need to normalize (A,a) to "new (R,r)" where R+r = A+a but +|--|r| <= half ulp of R. + faddx %fp1,%fp0 | ...FP0 is R := A+a +|--No need to calculate r if this is the last loop + cmpil #0,%d0 + bgt RESTORE + +|--Need to calculate r + fsubx %fp0,%fp3 | ...A-R + faddx %fp3,%fp1 | ...FP1 is r := (A-R)+a + bra LOOP + +RESTORE: + fmovel %fp2,N(%a6) + movel (%a7)+,%d2 + fmovemx (%a7)+,%fp2-%fp5 + + + movel N(%a6),%d0 + rorl #1,%d0 + + + bra TANCONT + + |end diff --git a/arch/m68k/fpsp040/stanh.S b/arch/m68k/fpsp040/stanh.S new file mode 100644 index 000000000..7e12e59ee --- /dev/null +++ b/arch/m68k/fpsp040/stanh.S @@ -0,0 +1,184 @@ +| +| stanh.sa 3.1 12/10/90 +| +| The entry point sTanh computes the hyperbolic tangent of +| an input argument; sTanhd does the same except for denormalized +| input. +| +| Input: Double-extended number X in location pointed to +| by address register a0. +| +| Output: The value tanh(X) returned in floating-point register Fp0. +| +| Accuracy and Monotonicity: The returned result is within 3 ulps in +| 64 significant bit, i.e. within 0.5001 ulp to 53 bits if the +| result is subsequently rounded to double precision. The +| result is provably monotonic in double precision. +| +| Speed: The program stanh takes approximately 270 cycles. +| +| Algorithm: +| +| TANH +| 1. If |X| >= (5/2) log2 or |X| <= 2**(-40), go to 3. +| +| 2. (2**(-40) < |X| < (5/2) log2) Calculate tanh(X) by +| sgn := sign(X), y := 2|X|, z := expm1(Y), and +| tanh(X) = sgn*( z/(2+z) ). +| Exit. +| +| 3. (|X| <= 2**(-40) or |X| >= (5/2) log2). If |X| < 1, +| go to 7. +| +| 4. (|X| >= (5/2) log2) If |X| >= 50 log2, go to 6. +| +| 5. ((5/2) log2 <= |X| < 50 log2) Calculate tanh(X) by +| sgn := sign(X), y := 2|X|, z := exp(Y), +| tanh(X) = sgn - [ sgn*2/(1+z) ]. +| Exit. +| +| 6. (|X| >= 50 log2) Tanh(X) = +-1 (round to nearest). Thus, we +| calculate Tanh(X) by +| sgn := sign(X), Tiny := 2**(-126), +| tanh(X) := sgn - sgn*Tiny. +| Exit. +| +| 7. (|X| < 2**(-40)). Tanh(X) = X. Exit. +| + +| Copyright (C) Motorola, Inc. 1990 +| All Rights Reserved +| +| For details on the license for this file, please see the +| file, README, in this same directory. + +|STANH idnt 2,1 | Motorola 040 Floating Point Software Package + + |section 8 + +#include "fpsp.h" + + .set X,FP_SCR5 + .set XDCARE,X+2 + .set XFRAC,X+4 + + .set SGN,L_SCR3 + + .set V,FP_SCR6 + +BOUNDS1: .long 0x3FD78000,0x3FFFDDCE | ... 2^(-40), (5/2)LOG2 + + |xref t_frcinx + |xref t_extdnrm + |xref setox + |xref setoxm1 + + .global stanhd +stanhd: +|--TANH(X) = X FOR DENORMALIZED X + + bra t_extdnrm + + .global stanh +stanh: + fmovex (%a0),%fp0 | ...LOAD INPUT + + fmovex %fp0,X(%a6) + movel (%a0),%d0 + movew 4(%a0),%d0 + movel %d0,X(%a6) + andl #0x7FFFFFFF,%d0 + cmp2l BOUNDS1(%pc),%d0 | ...2**(-40) < |X| < (5/2)LOG2 ? + bcss TANHBORS + +|--THIS IS THE USUAL CASE +|--Y = 2|X|, Z = EXPM1(Y), TANH(X) = SIGN(X) * Z / (Z+2). + + movel X(%a6),%d0 + movel %d0,SGN(%a6) + andl #0x7FFF0000,%d0 + addl #0x00010000,%d0 | ...EXPONENT OF 2|X| + movel %d0,X(%a6) + andl #0x80000000,SGN(%a6) + fmovex X(%a6),%fp0 | ...FP0 IS Y = 2|X| + + movel %d1,-(%a7) + clrl %d1 + fmovemx %fp0-%fp0,(%a0) + bsr setoxm1 | ...FP0 IS Z = EXPM1(Y) + movel (%a7)+,%d1 + + fmovex %fp0,%fp1 + fadds #0x40000000,%fp1 | ...Z+2 + movel SGN(%a6),%d0 + fmovex %fp1,V(%a6) + eorl %d0,V(%a6) + + fmovel %d1,%FPCR |restore users exceptions + fdivx V(%a6),%fp0 + bra t_frcinx + +TANHBORS: + cmpl #0x3FFF8000,%d0 + blt TANHSM + + cmpl #0x40048AA1,%d0 + bgt TANHHUGE + +|-- (5/2) LOG2 < |X| < 50 LOG2, +|--TANH(X) = 1 - (2/[EXP(2X)+1]). LET Y = 2|X|, SGN = SIGN(X), +|--TANH(X) = SGN - SGN*2/[EXP(Y)+1]. + + movel X(%a6),%d0 + movel %d0,SGN(%a6) + andl #0x7FFF0000,%d0 + addl #0x00010000,%d0 | ...EXPO OF 2|X| + movel %d0,X(%a6) | ...Y = 2|X| + andl #0x80000000,SGN(%a6) + movel SGN(%a6),%d0 + fmovex X(%a6),%fp0 | ...Y = 2|X| + + movel %d1,-(%a7) + clrl %d1 + fmovemx %fp0-%fp0,(%a0) + bsr setox | ...FP0 IS EXP(Y) + movel (%a7)+,%d1 + movel SGN(%a6),%d0 + fadds #0x3F800000,%fp0 | ...EXP(Y)+1 + + eorl #0xC0000000,%d0 | ...-SIGN(X)*2 + fmoves %d0,%fp1 | ...-SIGN(X)*2 IN SGL FMT + fdivx %fp0,%fp1 | ...-SIGN(X)2 / [EXP(Y)+1 ] + + movel SGN(%a6),%d0 + orl #0x3F800000,%d0 | ...SGN + fmoves %d0,%fp0 | ...SGN IN SGL FMT + + fmovel %d1,%FPCR |restore users exceptions + faddx %fp1,%fp0 + + bra t_frcinx + +TANHSM: + movew #0x0000,XDCARE(%a6) + + fmovel %d1,%FPCR |restore users exceptions + fmovex X(%a6),%fp0 |last inst - possible exception set + + bra t_frcinx + +TANHHUGE: +|---RETURN SGN(X) - SGN(X)EPS + movel X(%a6),%d0 + andl #0x80000000,%d0 + orl #0x3F800000,%d0 + fmoves %d0,%fp0 + andl #0x80000000,%d0 + eorl #0x80800000,%d0 | ...-SIGN(X)*EPS + + fmovel %d1,%FPCR |restore users exceptions + fadds %d0,%fp0 + + bra t_frcinx + + |end diff --git a/arch/m68k/fpsp040/sto_res.S b/arch/m68k/fpsp040/sto_res.S new file mode 100644 index 000000000..484b47d4e --- /dev/null +++ b/arch/m68k/fpsp040/sto_res.S @@ -0,0 +1,97 @@ +| +| sto_res.sa 3.1 12/10/90 +| +| Takes the result and puts it in where the user expects it. +| Library functions return result in fp0. If fp0 is not the +| users destination register then fp0 is moved to the +| correct floating-point destination register. fp0 and fp1 +| are then restored to the original contents. +| +| Input: result in fp0,fp1 +| +| d2 & a0 should be kept unmodified +| +| Output: moves the result to the true destination reg or mem +| +| Modifies: destination floating point register +| + +| Copyright (C) Motorola, Inc. 1990 +| All Rights Reserved +| +| For details on the license for this file, please see the +| file, README, in this same directory. + +STO_RES: |idnt 2,1 | Motorola 040 Floating Point Software Package + + + |section 8 + +#include "fpsp.h" + + .global sto_cos +sto_cos: + bfextu CMDREG1B(%a6){#13:#3},%d0 |extract cos destination + cmpib #3,%d0 |check for fp0/fp1 cases + bles c_fp0123 + fmovemx %fp1-%fp1,-(%a7) + moveql #7,%d1 + subl %d0,%d1 |d1 = 7- (dest. reg. no.) + clrl %d0 + bsetl %d1,%d0 |d0 is dynamic register mask + fmovemx (%a7)+,%d0 + rts +c_fp0123: + cmpib #0,%d0 + beqs c_is_fp0 + cmpib #1,%d0 + beqs c_is_fp1 + cmpib #2,%d0 + beqs c_is_fp2 +c_is_fp3: + fmovemx %fp1-%fp1,USER_FP3(%a6) + rts +c_is_fp2: + fmovemx %fp1-%fp1,USER_FP2(%a6) + rts +c_is_fp1: + fmovemx %fp1-%fp1,USER_FP1(%a6) + rts +c_is_fp0: + fmovemx %fp1-%fp1,USER_FP0(%a6) + rts + + + .global sto_res +sto_res: + bfextu CMDREG1B(%a6){#6:#3},%d0 |extract destination register + cmpib #3,%d0 |check for fp0/fp1 cases + bles fp0123 + fmovemx %fp0-%fp0,-(%a7) + moveql #7,%d1 + subl %d0,%d1 |d1 = 7- (dest. reg. no.) + clrl %d0 + bsetl %d1,%d0 |d0 is dynamic register mask + fmovemx (%a7)+,%d0 + rts +fp0123: + cmpib #0,%d0 + beqs is_fp0 + cmpib #1,%d0 + beqs is_fp1 + cmpib #2,%d0 + beqs is_fp2 +is_fp3: + fmovemx %fp0-%fp0,USER_FP3(%a6) + rts +is_fp2: + fmovemx %fp0-%fp0,USER_FP2(%a6) + rts +is_fp1: + fmovemx %fp0-%fp0,USER_FP1(%a6) + rts +is_fp0: + fmovemx %fp0-%fp0,USER_FP0(%a6) + rts + + |end diff --git a/arch/m68k/fpsp040/stwotox.S b/arch/m68k/fpsp040/stwotox.S new file mode 100644 index 000000000..0d5e6a143 --- /dev/null +++ b/arch/m68k/fpsp040/stwotox.S @@ -0,0 +1,426 @@ +| +| stwotox.sa 3.1 12/10/90 +| +| stwotox --- 2**X +| stwotoxd --- 2**X for denormalized X +| stentox --- 10**X +| stentoxd --- 10**X for denormalized X +| +| Input: Double-extended number X in location pointed to +| by address register a0. +| +| Output: The function values are returned in Fp0. +| +| Accuracy and Monotonicity: The returned result is within 2 ulps in +| 64 significant bit, i.e. within 0.5001 ulp to 53 bits if the +| result is subsequently rounded to double precision. The +| result is provably monotonic in double precision. +| +| Speed: The program stwotox takes approximately 190 cycles and the +| program stentox takes approximately 200 cycles. +| +| Algorithm: +| +| twotox +| 1. If |X| > 16480, go to ExpBig. +| +| 2. If |X| < 2**(-70), go to ExpSm. +| +| 3. Decompose X as X = N/64 + r where |r| <= 1/128. Furthermore +| decompose N as +| N = 64(M + M') + j, j = 0,1,2,...,63. +| +| 4. Overwrite r := r * log2. Then +| 2**X = 2**(M') * 2**(M) * 2**(j/64) * exp(r). +| Go to expr to compute that expression. +| +| tentox +| 1. If |X| > 16480*log_10(2) (base 10 log of 2), go to ExpBig. +| +| 2. If |X| < 2**(-70), go to ExpSm. +| +| 3. Set y := X*log_2(10)*64 (base 2 log of 10). Set +| N := round-to-int(y). Decompose N as +| N = 64(M + M') + j, j = 0,1,2,...,63. +| +| 4. Define r as +| r := ((X - N*L1)-N*L2) * L10 +| where L1, L2 are the leading and trailing parts of log_10(2)/64 +| and L10 is the natural log of 10. Then +| 10**X = 2**(M') * 2**(M) * 2**(j/64) * exp(r). +| Go to expr to compute that expression. +| +| expr +| 1. Fetch 2**(j/64) from table as Fact1 and Fact2. +| +| 2. Overwrite Fact1 and Fact2 by +| Fact1 := 2**(M) * Fact1 +| Fact2 := 2**(M) * Fact2 +| Thus Fact1 + Fact2 = 2**(M) * 2**(j/64). +| +| 3. Calculate P where 1 + P approximates exp(r): +| P = r + r*r*(A1+r*(A2+...+r*A5)). +| +| 4. Let AdjFact := 2**(M'). Return +| AdjFact * ( Fact1 + ((Fact1*P) + Fact2) ). +| Exit. +| +| ExpBig +| 1. Generate overflow by Huge * Huge if X > 0; otherwise, generate +| underflow by Tiny * Tiny. +| +| ExpSm +| 1. Return 1 + X. +| + +| Copyright (C) Motorola, Inc. 1990 +| All Rights Reserved +| +| For details on the license for this file, please see the +| file, README, in this same directory. + +|STWOTOX idnt 2,1 | Motorola 040 Floating Point Software Package + + |section 8 + +#include "fpsp.h" + +BOUNDS1: .long 0x3FB98000,0x400D80C0 | ... 2^(-70),16480 +BOUNDS2: .long 0x3FB98000,0x400B9B07 | ... 2^(-70),16480 LOG2/LOG10 + +L2TEN64: .long 0x406A934F,0x0979A371 | ... 64LOG10/LOG2 +L10TWO1: .long 0x3F734413,0x509F8000 | ... LOG2/64LOG10 + +L10TWO2: .long 0xBFCD0000,0xC0219DC1,0xDA994FD2,0x00000000 + +LOG10: .long 0x40000000,0x935D8DDD,0xAAA8AC17,0x00000000 + +LOG2: .long 0x3FFE0000,0xB17217F7,0xD1CF79AC,0x00000000 + +EXPA5: .long 0x3F56C16D,0x6F7BD0B2 +EXPA4: .long 0x3F811112,0x302C712C +EXPA3: .long 0x3FA55555,0x55554CC1 +EXPA2: .long 0x3FC55555,0x55554A54 +EXPA1: .long 0x3FE00000,0x00000000,0x00000000,0x00000000 + +HUGE: .long 0x7FFE0000,0xFFFFFFFF,0xFFFFFFFF,0x00000000 +TINY: .long 0x00010000,0xFFFFFFFF,0xFFFFFFFF,0x00000000 + +EXPTBL: + .long 0x3FFF0000,0x80000000,0x00000000,0x3F738000 + .long 0x3FFF0000,0x8164D1F3,0xBC030773,0x3FBEF7CA + .long 0x3FFF0000,0x82CD8698,0xAC2BA1D7,0x3FBDF8A9 + .long 0x3FFF0000,0x843A28C3,0xACDE4046,0x3FBCD7C9 + .long 0x3FFF0000,0x85AAC367,0xCC487B15,0xBFBDE8DA + .long 0x3FFF0000,0x871F6196,0x9E8D1010,0x3FBDE85C + .long 0x3FFF0000,0x88980E80,0x92DA8527,0x3FBEBBF1 + .long 0x3FFF0000,0x8A14D575,0x496EFD9A,0x3FBB80CA + .long 0x3FFF0000,0x8B95C1E3,0xEA8BD6E7,0xBFBA8373 + .long 0x3FFF0000,0x8D1ADF5B,0x7E5BA9E6,0xBFBE9670 + .long 0x3FFF0000,0x8EA4398B,0x45CD53C0,0x3FBDB700 + .long 0x3FFF0000,0x9031DC43,0x1466B1DC,0x3FBEEEB0 + .long 0x3FFF0000,0x91C3D373,0xAB11C336,0x3FBBFD6D + .long 0x3FFF0000,0x935A2B2F,0x13E6E92C,0xBFBDB319 + .long 0x3FFF0000,0x94F4EFA8,0xFEF70961,0x3FBDBA2B + .long 0x3FFF0000,0x96942D37,0x20185A00,0x3FBE91D5 + .long 0x3FFF0000,0x9837F051,0x8DB8A96F,0x3FBE8D5A + .long 0x3FFF0000,0x99E04593,0x20B7FA65,0xBFBCDE7B + .long 0x3FFF0000,0x9B8D39B9,0xD54E5539,0xBFBEBAAF + .long 0x3FFF0000,0x9D3ED9A7,0x2CFFB751,0xBFBD86DA + .long 0x3FFF0000,0x9EF53260,0x91A111AE,0xBFBEBEDD + .long 0x3FFF0000,0xA0B0510F,0xB9714FC2,0x3FBCC96E + .long 0x3FFF0000,0xA2704303,0x0C496819,0xBFBEC90B + .long 0x3FFF0000,0xA43515AE,0x09E6809E,0x3FBBD1DB + .long 0x3FFF0000,0xA5FED6A9,0xB15138EA,0x3FBCE5EB + .long 0x3FFF0000,0xA7CD93B4,0xE965356A,0xBFBEC274 + .long 0x3FFF0000,0xA9A15AB4,0xEA7C0EF8,0x3FBEA83C + .long 0x3FFF0000,0xAB7A39B5,0xA93ED337,0x3FBECB00 + .long 0x3FFF0000,0xAD583EEA,0x42A14AC6,0x3FBE9301 + .long 0x3FFF0000,0xAF3B78AD,0x690A4375,0xBFBD8367 + .long 0x3FFF0000,0xB123F581,0xD2AC2590,0xBFBEF05F + .long 0x3FFF0000,0xB311C412,0xA9112489,0x3FBDFB3C + .long 0x3FFF0000,0xB504F333,0xF9DE6484,0x3FBEB2FB + .long 0x3FFF0000,0xB6FD91E3,0x28D17791,0x3FBAE2CB + .long 0x3FFF0000,0xB8FBAF47,0x62FB9EE9,0x3FBCDC3C + .long 0x3FFF0000,0xBAFF5AB2,0x133E45FB,0x3FBEE9AA + .long 0x3FFF0000,0xBD08A39F,0x580C36BF,0xBFBEAEFD + .long 0x3FFF0000,0xBF1799B6,0x7A731083,0xBFBCBF51 + .long 0x3FFF0000,0xC12C4CCA,0x66709456,0x3FBEF88A + .long 0x3FFF0000,0xC346CCDA,0x24976407,0x3FBD83B2 + .long 0x3FFF0000,0xC5672A11,0x5506DADD,0x3FBDF8AB + .long 0x3FFF0000,0xC78D74C8,0xABB9B15D,0xBFBDFB17 + .long 0x3FFF0000,0xC9B9BD86,0x6E2F27A3,0xBFBEFE3C + .long 0x3FFF0000,0xCBEC14FE,0xF2727C5D,0xBFBBB6F8 + .long 0x3FFF0000,0xCE248C15,0x1F8480E4,0xBFBCEE53 + .long 0x3FFF0000,0xD06333DA,0xEF2B2595,0xBFBDA4AE + .long 0x3FFF0000,0xD2A81D91,0xF12AE45A,0x3FBC9124 + .long 0x3FFF0000,0xD4F35AAB,0xCFEDFA1F,0x3FBEB243 + .long 0x3FFF0000,0xD744FCCA,0xD69D6AF4,0x3FBDE69A + .long 0x3FFF0000,0xD99D15C2,0x78AFD7B6,0xBFB8BC61 + .long 0x3FFF0000,0xDBFBB797,0xDAF23755,0x3FBDF610 + .long 0x3FFF0000,0xDE60F482,0x5E0E9124,0xBFBD8BE1 + .long 0x3FFF0000,0xE0CCDEEC,0x2A94E111,0x3FBACB12 + .long 0x3FFF0000,0xE33F8972,0xBE8A5A51,0x3FBB9BFE + .long 0x3FFF0000,0xE5B906E7,0x7C8348A8,0x3FBCF2F4 + .long 0x3FFF0000,0xE8396A50,0x3C4BDC68,0x3FBEF22F + .long 0x3FFF0000,0xEAC0C6E7,0xDD24392F,0xBFBDBF4A + .long 0x3FFF0000,0xED4F301E,0xD9942B84,0x3FBEC01A + .long 0x3FFF0000,0xEFE4B99B,0xDCDAF5CB,0x3FBE8CAC + .long 0x3FFF0000,0xF281773C,0x59FFB13A,0xBFBCBB3F + .long 0x3FFF0000,0xF5257D15,0x2486CC2C,0x3FBEF73A + .long 0x3FFF0000,0xF7D0DF73,0x0AD13BB9,0xBFB8B795 + .long 0x3FFF0000,0xFA83B2DB,0x722A033A,0x3FBEF84B + .long 0x3FFF0000,0xFD3E0C0C,0xF486C175,0xBFBEF581 + + .set N,L_SCR1 + + .set X,FP_SCR1 + .set XDCARE,X+2 + .set XFRAC,X+4 + + .set ADJFACT,FP_SCR2 + + .set FACT1,FP_SCR3 + .set FACT1HI,FACT1+4 + .set FACT1LOW,FACT1+8 + + .set FACT2,FP_SCR4 + .set FACT2HI,FACT2+4 + .set FACT2LOW,FACT2+8 + + | xref t_unfl + |xref t_ovfl + |xref t_frcinx + + .global stwotoxd +stwotoxd: +|--ENTRY POINT FOR 2**(X) FOR DENORMALIZED ARGUMENT + + fmovel %d1,%fpcr | ...set user's rounding mode/precision + fmoves #0x3F800000,%fp0 | ...RETURN 1 + X + movel (%a0),%d0 + orl #0x00800001,%d0 + fadds %d0,%fp0 + bra t_frcinx + + .global stwotox +stwotox: +|--ENTRY POINT FOR 2**(X), HERE X IS FINITE, NON-ZERO, AND NOT NAN'S + fmovemx (%a0),%fp0-%fp0 | ...LOAD INPUT, do not set cc's + + movel (%a0),%d0 + movew 4(%a0),%d0 + fmovex %fp0,X(%a6) + andil #0x7FFFFFFF,%d0 + + cmpil #0x3FB98000,%d0 | ...|X| >= 2**(-70)? + bges TWOOK1 + bra EXPBORS + +TWOOK1: + cmpil #0x400D80C0,%d0 | ...|X| > 16480? + bles TWOMAIN + bra EXPBORS + + +TWOMAIN: +|--USUAL CASE, 2^(-70) <= |X| <= 16480 + + fmovex %fp0,%fp1 + fmuls #0x42800000,%fp1 | ...64 * X + + fmovel %fp1,N(%a6) | ...N = ROUND-TO-INT(64 X) + movel %d2,-(%sp) + lea EXPTBL,%a1 | ...LOAD ADDRESS OF TABLE OF 2^(J/64) + fmovel N(%a6),%fp1 | ...N --> FLOATING FMT + movel N(%a6),%d0 + movel %d0,%d2 + andil #0x3F,%d0 | ...D0 IS J + asll #4,%d0 | ...DISPLACEMENT FOR 2^(J/64) + addal %d0,%a1 | ...ADDRESS FOR 2^(J/64) + asrl #6,%d2 | ...d2 IS L, N = 64L + J + movel %d2,%d0 + asrl #1,%d0 | ...D0 IS M + subl %d0,%d2 | ...d2 IS M', N = 64(M+M') + J + addil #0x3FFF,%d2 + movew %d2,ADJFACT(%a6) | ...ADJFACT IS 2^(M') + movel (%sp)+,%d2 +|--SUMMARY: a1 IS ADDRESS FOR THE LEADING PORTION OF 2^(J/64), +|--D0 IS M WHERE N = 64(M+M') + J. NOTE THAT |M| <= 16140 BY DESIGN. +|--ADJFACT = 2^(M'). +|--REGISTERS SAVED SO FAR ARE (IN ORDER) FPCR, D0, FP1, a1, AND FP2. + + fmuls #0x3C800000,%fp1 | ...(1/64)*N + movel (%a1)+,FACT1(%a6) + movel (%a1)+,FACT1HI(%a6) + movel (%a1)+,FACT1LOW(%a6) + movew (%a1)+,FACT2(%a6) + clrw FACT2+2(%a6) + + fsubx %fp1,%fp0 | ...X - (1/64)*INT(64 X) + + movew (%a1)+,FACT2HI(%a6) + clrw FACT2HI+2(%a6) + clrl FACT2LOW(%a6) + addw %d0,FACT1(%a6) + + fmulx LOG2,%fp0 | ...FP0 IS R + addw %d0,FACT2(%a6) + + bra expr + +EXPBORS: +|--FPCR, D0 SAVED + cmpil #0x3FFF8000,%d0 + bgts EXPBIG + +EXPSM: +|--|X| IS SMALL, RETURN 1 + X + + fmovel %d1,%FPCR |restore users exceptions + fadds #0x3F800000,%fp0 | ...RETURN 1 + X + + bra t_frcinx + +EXPBIG: +|--|X| IS LARGE, GENERATE OVERFLOW IF X > 0; ELSE GENERATE UNDERFLOW +|--REGISTERS SAVE SO FAR ARE FPCR AND D0 + movel X(%a6),%d0 + cmpil #0,%d0 + blts EXPNEG + + bclrb #7,(%a0) |t_ovfl expects positive value + bra t_ovfl + +EXPNEG: + bclrb #7,(%a0) |t_unfl expects positive value + bra t_unfl + + .global stentoxd +stentoxd: +|--ENTRY POINT FOR 10**(X) FOR DENORMALIZED ARGUMENT + + fmovel %d1,%fpcr | ...set user's rounding mode/precision + fmoves #0x3F800000,%fp0 | ...RETURN 1 + X + movel (%a0),%d0 + orl #0x00800001,%d0 + fadds %d0,%fp0 + bra t_frcinx + + .global stentox +stentox: +|--ENTRY POINT FOR 10**(X), HERE X IS FINITE, NON-ZERO, AND NOT NAN'S + fmovemx (%a0),%fp0-%fp0 | ...LOAD INPUT, do not set cc's + + movel (%a0),%d0 + movew 4(%a0),%d0 + fmovex %fp0,X(%a6) + andil #0x7FFFFFFF,%d0 + + cmpil #0x3FB98000,%d0 | ...|X| >= 2**(-70)? + bges TENOK1 + bra EXPBORS + +TENOK1: + cmpil #0x400B9B07,%d0 | ...|X| <= 16480*log2/log10 ? + bles TENMAIN + bra EXPBORS + +TENMAIN: +|--USUAL CASE, 2^(-70) <= |X| <= 16480 LOG 2 / LOG 10 + + fmovex %fp0,%fp1 + fmuld L2TEN64,%fp1 | ...X*64*LOG10/LOG2 + + fmovel %fp1,N(%a6) | ...N=INT(X*64*LOG10/LOG2) + movel %d2,-(%sp) + lea EXPTBL,%a1 | ...LOAD ADDRESS OF TABLE OF 2^(J/64) + fmovel N(%a6),%fp1 | ...N --> FLOATING FMT + movel N(%a6),%d0 + movel %d0,%d2 + andil #0x3F,%d0 | ...D0 IS J + asll #4,%d0 | ...DISPLACEMENT FOR 2^(J/64) + addal %d0,%a1 | ...ADDRESS FOR 2^(J/64) + asrl #6,%d2 | ...d2 IS L, N = 64L + J + movel %d2,%d0 + asrl #1,%d0 | ...D0 IS M + subl %d0,%d2 | ...d2 IS M', N = 64(M+M') + J + addil #0x3FFF,%d2 + movew %d2,ADJFACT(%a6) | ...ADJFACT IS 2^(M') + movel (%sp)+,%d2 + +|--SUMMARY: a1 IS ADDRESS FOR THE LEADING PORTION OF 2^(J/64), +|--D0 IS M WHERE N = 64(M+M') + J. NOTE THAT |M| <= 16140 BY DESIGN. +|--ADJFACT = 2^(M'). +|--REGISTERS SAVED SO FAR ARE (IN ORDER) FPCR, D0, FP1, a1, AND FP2. + + fmovex %fp1,%fp2 + + fmuld L10TWO1,%fp1 | ...N*(LOG2/64LOG10)_LEAD + movel (%a1)+,FACT1(%a6) + + fmulx L10TWO2,%fp2 | ...N*(LOG2/64LOG10)_TRAIL + + movel (%a1)+,FACT1HI(%a6) + movel (%a1)+,FACT1LOW(%a6) + fsubx %fp1,%fp0 | ...X - N L_LEAD + movew (%a1)+,FACT2(%a6) + + fsubx %fp2,%fp0 | ...X - N L_TRAIL + + clrw FACT2+2(%a6) + movew (%a1)+,FACT2HI(%a6) + clrw FACT2HI+2(%a6) + clrl FACT2LOW(%a6) + + fmulx LOG10,%fp0 | ...FP0 IS R + + addw %d0,FACT1(%a6) + addw %d0,FACT2(%a6) + +expr: +|--FPCR, FP2, FP3 ARE SAVED IN ORDER AS SHOWN. +|--ADJFACT CONTAINS 2**(M'), FACT1 + FACT2 = 2**(M) * 2**(J/64). +|--FP0 IS R. THE FOLLOWING CODE COMPUTES +|-- 2**(M'+M) * 2**(J/64) * EXP(R) + + fmovex %fp0,%fp1 + fmulx %fp1,%fp1 | ...FP1 IS S = R*R + + fmoved EXPA5,%fp2 | ...FP2 IS A5 + fmoved EXPA4,%fp3 | ...FP3 IS A4 + + fmulx %fp1,%fp2 | ...FP2 IS S*A5 + fmulx %fp1,%fp3 | ...FP3 IS S*A4 + + faddd EXPA3,%fp2 | ...FP2 IS A3+S*A5 + faddd EXPA2,%fp3 | ...FP3 IS A2+S*A4 + + fmulx %fp1,%fp2 | ...FP2 IS S*(A3+S*A5) + fmulx %fp1,%fp3 | ...FP3 IS S*(A2+S*A4) + + faddd EXPA1,%fp2 | ...FP2 IS A1+S*(A3+S*A5) + fmulx %fp0,%fp3 | ...FP3 IS R*S*(A2+S*A4) + + fmulx %fp1,%fp2 | ...FP2 IS S*(A1+S*(A3+S*A5)) + faddx %fp3,%fp0 | ...FP0 IS R+R*S*(A2+S*A4) + + faddx %fp2,%fp0 | ...FP0 IS EXP(R) - 1 + + +|--FINAL RECONSTRUCTION PROCESS +|--EXP(X) = 2^M*2^(J/64) + 2^M*2^(J/64)*(EXP(R)-1) - (1 OR 0) + + fmulx FACT1(%a6),%fp0 + faddx FACT2(%a6),%fp0 + faddx FACT1(%a6),%fp0 + + fmovel %d1,%FPCR |restore users exceptions + clrw ADJFACT+2(%a6) + movel #0x80000000,ADJFACT+4(%a6) + clrl ADJFACT+8(%a6) + fmulx ADJFACT(%a6),%fp0 | ...FINAL ADJUSTMENT + + bra t_frcinx + + |end diff --git a/arch/m68k/fpsp040/tbldo.S b/arch/m68k/fpsp040/tbldo.S new file mode 100644 index 000000000..fd5c37a5a --- /dev/null +++ b/arch/m68k/fpsp040/tbldo.S @@ -0,0 +1,553 @@ +| +| tbldo.sa 3.1 12/10/90 +| +| Modified: +| 8/16/90 chinds The table was constructed to use only one level +| of indirection in do_func for monadic +| functions. Dyadic functions require two +| levels, and the tables are still contained +| in do_func. The table is arranged for +| index with a 10-bit index, with the first +| 7 bits the opcode, and the remaining 3 +| the stag. For dyadic functions, all +| valid addresses are to the generic entry +| point. +| + +| Copyright (C) Motorola, Inc. 1990 +| All Rights Reserved +| +| For details on the license for this file, please see the +| file, README, in this same directory. + +|TBLDO idnt 2,1 | Motorola 040 Floating Point Software Package + + |section 8 + + |xref ld_pinf,ld_pone,ld_ppi2 + |xref t_dz2,t_operr + |xref serror,sone,szero,sinf,snzrinx + |xref sopr_inf,spi_2,src_nan,szr_inf + + |xref smovcr + |xref pmod,prem,pscale + |xref satanh,satanhd + |xref sacos,sacosd,sasin,sasind,satan,satand + |xref setox,setoxd,setoxm1,setoxm1d,setoxm1i + |xref sgetexp,sgetexpd,sgetman,sgetmand + |xref sint,sintd,sintrz + |xref ssincos,ssincosd,ssincosi,ssincosnan,ssincosz + |xref scos,scosd,ssin,ssind,stan,stand + |xref scosh,scoshd,ssinh,ssinhd,stanh,stanhd + |xref sslog10,sslog2,sslogn,sslognp1 + |xref sslog10d,sslog2d,sslognd,slognp1d + |xref stentox,stentoxd,stwotox,stwotoxd + +| instruction ;opcode-stag Notes + .global tblpre +tblpre: + .long smovcr |$00-0 fmovecr all + .long smovcr |$00-1 fmovecr all + .long smovcr |$00-2 fmovecr all + .long smovcr |$00-3 fmovecr all + .long smovcr |$00-4 fmovecr all + .long smovcr |$00-5 fmovecr all + .long smovcr |$00-6 fmovecr all + .long smovcr |$00-7 fmovecr all + + .long sint |$01-0 fint norm + .long szero |$01-1 fint zero + .long sinf |$01-2 fint inf + .long src_nan |$01-3 fint nan + .long sintd |$01-4 fint denorm inx + .long serror |$01-5 fint ERROR + .long serror |$01-6 fint ERROR + .long serror |$01-7 fint ERROR + + .long ssinh |$02-0 fsinh norm + .long szero |$02-1 fsinh zero + .long sinf |$02-2 fsinh inf + .long src_nan |$02-3 fsinh nan + .long ssinhd |$02-4 fsinh denorm + .long serror |$02-5 fsinh ERROR + .long serror |$02-6 fsinh ERROR + .long serror |$02-7 fsinh ERROR + + .long sintrz |$03-0 fintrz norm + .long szero |$03-1 fintrz zero + .long sinf |$03-2 fintrz inf + .long src_nan |$03-3 fintrz nan + .long snzrinx |$03-4 fintrz denorm inx + .long serror |$03-5 fintrz ERROR + .long serror |$03-6 fintrz ERROR + .long serror |$03-7 fintrz ERROR + + .long serror |$04-0 ERROR - illegal extension + .long serror |$04-1 ERROR - illegal extension + .long serror |$04-2 ERROR - illegal extension + .long serror |$04-3 ERROR - illegal extension + .long serror |$04-4 ERROR - illegal extension + .long serror |$04-5 ERROR - illegal extension + .long serror |$04-6 ERROR - illegal extension + .long serror |$04-7 ERROR - illegal extension + + .long serror |$05-0 ERROR - illegal extension + .long serror |$05-1 ERROR - illegal extension + .long serror |$05-2 ERROR - illegal extension + .long serror |$05-3 ERROR - illegal extension + .long serror |$05-4 ERROR - illegal extension + .long serror |$05-5 ERROR - illegal extension + .long serror |$05-6 ERROR - illegal extension + .long serror |$05-7 ERROR - illegal extension + + .long sslognp1 |$06-0 flognp1 norm + .long szero |$06-1 flognp1 zero + .long sopr_inf |$06-2 flognp1 inf + .long src_nan |$06-3 flognp1 nan + .long slognp1d |$06-4 flognp1 denorm + .long serror |$06-5 flognp1 ERROR + .long serror |$06-6 flognp1 ERROR + .long serror |$06-7 flognp1 ERROR + + .long serror |$07-0 ERROR - illegal extension + .long serror |$07-1 ERROR - illegal extension + .long serror |$07-2 ERROR - illegal extension + .long serror |$07-3 ERROR - illegal extension + .long serror |$07-4 ERROR - illegal extension + .long serror |$07-5 ERROR - illegal extension + .long serror |$07-6 ERROR - illegal extension + .long serror |$07-7 ERROR - illegal extension + + .long setoxm1 |$08-0 fetoxm1 norm + .long szero |$08-1 fetoxm1 zero + .long setoxm1i |$08-2 fetoxm1 inf + .long src_nan |$08-3 fetoxm1 nan + .long setoxm1d |$08-4 fetoxm1 denorm + .long serror |$08-5 fetoxm1 ERROR + .long serror |$08-6 fetoxm1 ERROR + .long serror |$08-7 fetoxm1 ERROR + + .long stanh |$09-0 ftanh norm + .long szero |$09-1 ftanh zero + .long sone |$09-2 ftanh inf + .long src_nan |$09-3 ftanh nan + .long stanhd |$09-4 ftanh denorm + .long serror |$09-5 ftanh ERROR + .long serror |$09-6 ftanh ERROR + .long serror |$09-7 ftanh ERROR + + .long satan |$0a-0 fatan norm + .long szero |$0a-1 fatan zero + .long spi_2 |$0a-2 fatan inf + .long src_nan |$0a-3 fatan nan + .long satand |$0a-4 fatan denorm + .long serror |$0a-5 fatan ERROR + .long serror |$0a-6 fatan ERROR + .long serror |$0a-7 fatan ERROR + + .long serror |$0b-0 ERROR - illegal extension + .long serror |$0b-1 ERROR - illegal extension + .long serror |$0b-2 ERROR - illegal extension + .long serror |$0b-3 ERROR - illegal extension + .long serror |$0b-4 ERROR - illegal extension + .long serror |$0b-5 ERROR - illegal extension + .long serror |$0b-6 ERROR - illegal extension + .long serror |$0b-7 ERROR - illegal extension + + .long sasin |$0c-0 fasin norm + .long szero |$0c-1 fasin zero + .long t_operr |$0c-2 fasin inf + .long src_nan |$0c-3 fasin nan + .long sasind |$0c-4 fasin denorm + .long serror |$0c-5 fasin ERROR + .long serror |$0c-6 fasin ERROR + .long serror |$0c-7 fasin ERROR + + .long satanh |$0d-0 fatanh norm + .long szero |$0d-1 fatanh zero + .long t_operr |$0d-2 fatanh inf + .long src_nan |$0d-3 fatanh nan + .long satanhd |$0d-4 fatanh denorm + .long serror |$0d-5 fatanh ERROR + .long serror |$0d-6 fatanh ERROR + .long serror |$0d-7 fatanh ERROR + + .long ssin |$0e-0 fsin norm + .long szero |$0e-1 fsin zero + .long t_operr |$0e-2 fsin inf + .long src_nan |$0e-3 fsin nan + .long ssind |$0e-4 fsin denorm + .long serror |$0e-5 fsin ERROR + .long serror |$0e-6 fsin ERROR + .long serror |$0e-7 fsin ERROR + + .long stan |$0f-0 ftan norm + .long szero |$0f-1 ftan zero + .long t_operr |$0f-2 ftan inf + .long src_nan |$0f-3 ftan nan + .long stand |$0f-4 ftan denorm + .long serror |$0f-5 ftan ERROR + .long serror |$0f-6 ftan ERROR + .long serror |$0f-7 ftan ERROR + + .long setox |$10-0 fetox norm + .long ld_pone |$10-1 fetox zero + .long szr_inf |$10-2 fetox inf + .long src_nan |$10-3 fetox nan + .long setoxd |$10-4 fetox denorm + .long serror |$10-5 fetox ERROR + .long serror |$10-6 fetox ERROR + .long serror |$10-7 fetox ERROR + + .long stwotox |$11-0 ftwotox norm + .long ld_pone |$11-1 ftwotox zero + .long szr_inf |$11-2 ftwotox inf + .long src_nan |$11-3 ftwotox nan + .long stwotoxd |$11-4 ftwotox denorm + .long serror |$11-5 ftwotox ERROR + .long serror |$11-6 ftwotox ERROR + .long serror |$11-7 ftwotox ERROR + + .long stentox |$12-0 ftentox norm + .long ld_pone |$12-1 ftentox zero + .long szr_inf |$12-2 ftentox inf + .long src_nan |$12-3 ftentox nan + .long stentoxd |$12-4 ftentox denorm + .long serror |$12-5 ftentox ERROR + .long serror |$12-6 ftentox ERROR + .long serror |$12-7 ftentox ERROR + + .long serror |$13-0 ERROR - illegal extension + .long serror |$13-1 ERROR - illegal extension + .long serror |$13-2 ERROR - illegal extension + .long serror |$13-3 ERROR - illegal extension + .long serror |$13-4 ERROR - illegal extension + .long serror |$13-5 ERROR - illegal extension + .long serror |$13-6 ERROR - illegal extension + .long serror |$13-7 ERROR - illegal extension + + .long sslogn |$14-0 flogn norm + .long t_dz2 |$14-1 flogn zero + .long sopr_inf |$14-2 flogn inf + .long src_nan |$14-3 flogn nan + .long sslognd |$14-4 flogn denorm + .long serror |$14-5 flogn ERROR + .long serror |$14-6 flogn ERROR + .long serror |$14-7 flogn ERROR + + .long sslog10 |$15-0 flog10 norm + .long t_dz2 |$15-1 flog10 zero + .long sopr_inf |$15-2 flog10 inf + .long src_nan |$15-3 flog10 nan + .long sslog10d |$15-4 flog10 denorm + .long serror |$15-5 flog10 ERROR + .long serror |$15-6 flog10 ERROR + .long serror |$15-7 flog10 ERROR + + .long sslog2 |$16-0 flog2 norm + .long t_dz2 |$16-1 flog2 zero + .long sopr_inf |$16-2 flog2 inf + .long src_nan |$16-3 flog2 nan + .long sslog2d |$16-4 flog2 denorm + .long serror |$16-5 flog2 ERROR + .long serror |$16-6 flog2 ERROR + .long serror |$16-7 flog2 ERROR + + .long serror |$17-0 ERROR - illegal extension + .long serror |$17-1 ERROR - illegal extension + .long serror |$17-2 ERROR - illegal extension + .long serror |$17-3 ERROR - illegal extension + .long serror |$17-4 ERROR - illegal extension + .long serror |$17-5 ERROR - illegal extension + .long serror |$17-6 ERROR - illegal extension + .long serror |$17-7 ERROR - illegal extension + + .long serror |$18-0 ERROR - illegal extension + .long serror |$18-1 ERROR - illegal extension + .long serror |$18-2 ERROR - illegal extension + .long serror |$18-3 ERROR - illegal extension + .long serror |$18-4 ERROR - illegal extension + .long serror |$18-5 ERROR - illegal extension + .long serror |$18-6 ERROR - illegal extension + .long serror |$18-7 ERROR - illegal extension + + .long scosh |$19-0 fcosh norm + .long ld_pone |$19-1 fcosh zero + .long ld_pinf |$19-2 fcosh inf + .long src_nan |$19-3 fcosh nan + .long scoshd |$19-4 fcosh denorm + .long serror |$19-5 fcosh ERROR + .long serror |$19-6 fcosh ERROR + .long serror |$19-7 fcosh ERROR + + .long serror |$1a-0 ERROR - illegal extension + .long serror |$1a-1 ERROR - illegal extension + .long serror |$1a-2 ERROR - illegal extension + .long serror |$1a-3 ERROR - illegal extension + .long serror |$1a-4 ERROR - illegal extension + .long serror |$1a-5 ERROR - illegal extension + .long serror |$1a-6 ERROR - illegal extension + .long serror |$1a-7 ERROR - illegal extension + + .long serror |$1b-0 ERROR - illegal extension + .long serror |$1b-1 ERROR - illegal extension + .long serror |$1b-2 ERROR - illegal extension + .long serror |$1b-3 ERROR - illegal extension + .long serror |$1b-4 ERROR - illegal extension + .long serror |$1b-5 ERROR - illegal extension + .long serror |$1b-6 ERROR - illegal extension + .long serror |$1b-7 ERROR - illegal extension + + .long sacos |$1c-0 facos norm + .long ld_ppi2 |$1c-1 facos zero + .long t_operr |$1c-2 facos inf + .long src_nan |$1c-3 facos nan + .long sacosd |$1c-4 facos denorm + .long serror |$1c-5 facos ERROR + .long serror |$1c-6 facos ERROR + .long serror |$1c-7 facos ERROR + + .long scos |$1d-0 fcos norm + .long ld_pone |$1d-1 fcos zero + .long t_operr |$1d-2 fcos inf + .long src_nan |$1d-3 fcos nan + .long scosd |$1d-4 fcos denorm + .long serror |$1d-5 fcos ERROR + .long serror |$1d-6 fcos ERROR + .long serror |$1d-7 fcos ERROR + + .long sgetexp |$1e-0 fgetexp norm + .long szero |$1e-1 fgetexp zero + .long t_operr |$1e-2 fgetexp inf + .long src_nan |$1e-3 fgetexp nan + .long sgetexpd |$1e-4 fgetexp denorm + .long serror |$1e-5 fgetexp ERROR + .long serror |$1e-6 fgetexp ERROR + .long serror |$1e-7 fgetexp ERROR + + .long sgetman |$1f-0 fgetman norm + .long szero |$1f-1 fgetman zero + .long t_operr |$1f-2 fgetman inf + .long src_nan |$1f-3 fgetman nan + .long sgetmand |$1f-4 fgetman denorm + .long serror |$1f-5 fgetman ERROR + .long serror |$1f-6 fgetman ERROR + .long serror |$1f-7 fgetman ERROR + + .long serror |$20-0 ERROR - illegal extension + .long serror |$20-1 ERROR - illegal extension + .long serror |$20-2 ERROR - illegal extension + .long serror |$20-3 ERROR - illegal extension + .long serror |$20-4 ERROR - illegal extension + .long serror |$20-5 ERROR - illegal extension + .long serror |$20-6 ERROR - illegal extension + .long serror |$20-7 ERROR - illegal extension + + .long pmod |$21-0 fmod all + .long pmod |$21-1 fmod all + .long pmod |$21-2 fmod all + .long pmod |$21-3 fmod all + .long pmod |$21-4 fmod all + .long serror |$21-5 fmod ERROR + .long serror |$21-6 fmod ERROR + .long serror |$21-7 fmod ERROR + + .long serror |$22-0 ERROR - illegal extension + .long serror |$22-1 ERROR - illegal extension + .long serror |$22-2 ERROR - illegal extension + .long serror |$22-3 ERROR - illegal extension + .long serror |$22-4 ERROR - illegal extension + .long serror |$22-5 ERROR - illegal extension + .long serror |$22-6 ERROR - illegal extension + .long serror |$22-7 ERROR - illegal extension + + .long serror |$23-0 ERROR - illegal extension + .long serror |$23-1 ERROR - illegal extension + .long serror |$23-2 ERROR - illegal extension + .long serror |$23-3 ERROR - illegal extension + .long serror |$23-4 ERROR - illegal extension + .long serror |$23-5 ERROR - illegal extension + .long serror |$23-6 ERROR - illegal extension + .long serror |$23-7 ERROR - illegal extension + + .long serror |$24-0 ERROR - illegal extension + .long serror |$24-1 ERROR - illegal extension + .long serror |$24-2 ERROR - illegal extension + .long serror |$24-3 ERROR - illegal extension + .long serror |$24-4 ERROR - illegal extension + .long serror |$24-5 ERROR - illegal extension + .long serror |$24-6 ERROR - illegal extension + .long serror |$24-7 ERROR - illegal extension + + .long prem |$25-0 frem all + .long prem |$25-1 frem all + .long prem |$25-2 frem all + .long prem |$25-3 frem all + .long prem |$25-4 frem all + .long serror |$25-5 frem ERROR + .long serror |$25-6 frem ERROR + .long serror |$25-7 frem ERROR + + .long pscale |$26-0 fscale all + .long pscale |$26-1 fscale all + .long pscale |$26-2 fscale all + .long pscale |$26-3 fscale all + .long pscale |$26-4 fscale all + .long serror |$26-5 fscale ERROR + .long serror |$26-6 fscale ERROR + .long serror |$26-7 fscale ERROR + + .long serror |$27-0 ERROR - illegal extension + .long serror |$27-1 ERROR - illegal extension + .long serror |$27-2 ERROR - illegal extension + .long serror |$27-3 ERROR - illegal extension + .long serror |$27-4 ERROR - illegal extension + .long serror |$27-5 ERROR - illegal extension + .long serror |$27-6 ERROR - illegal extension + .long serror |$27-7 ERROR - illegal extension + + .long serror |$28-0 ERROR - illegal extension + .long serror |$28-1 ERROR - illegal extension + .long serror |$28-2 ERROR - illegal extension + .long serror |$28-3 ERROR - illegal extension + .long serror |$28-4 ERROR - illegal extension + .long serror |$28-5 ERROR - illegal extension + .long serror |$28-6 ERROR - illegal extension + .long serror |$28-7 ERROR - illegal extension + + .long serror |$29-0 ERROR - illegal extension + .long serror |$29-1 ERROR - illegal extension + .long serror |$29-2 ERROR - illegal extension + .long serror |$29-3 ERROR - illegal extension + .long serror |$29-4 ERROR - illegal extension + .long serror |$29-5 ERROR - illegal extension + .long serror |$29-6 ERROR - illegal extension + .long serror |$29-7 ERROR - illegal extension + + .long serror |$2a-0 ERROR - illegal extension + .long serror |$2a-1 ERROR - illegal extension + .long serror |$2a-2 ERROR - illegal extension + .long serror |$2a-3 ERROR - illegal extension + .long serror |$2a-4 ERROR - illegal extension + .long serror |$2a-5 ERROR - illegal extension + .long serror |$2a-6 ERROR - illegal extension + .long serror |$2a-7 ERROR - illegal extension + + .long serror |$2b-0 ERROR - illegal extension + .long serror |$2b-1 ERROR - illegal extension + .long serror |$2b-2 ERROR - illegal extension + .long serror |$2b-3 ERROR - illegal extension + .long serror |$2b-4 ERROR - illegal extension + .long serror |$2b-5 ERROR - illegal extension + .long serror |$2b-6 ERROR - illegal extension + .long serror |$2b-7 ERROR - illegal extension + + .long serror |$2c-0 ERROR - illegal extension + .long serror |$2c-1 ERROR - illegal extension + .long serror |$2c-2 ERROR - illegal extension + .long serror |$2c-3 ERROR - illegal extension + .long serror |$2c-4 ERROR - illegal extension + .long serror |$2c-5 ERROR - illegal extension + .long serror |$2c-6 ERROR - illegal extension + .long serror |$2c-7 ERROR - illegal extension + + .long serror |$2d-0 ERROR - illegal extension + .long serror |$2d-1 ERROR - illegal extension + .long serror |$2d-2 ERROR - illegal extension + .long serror |$2d-3 ERROR - illegal extension + .long serror |$2d-4 ERROR - illegal extension + .long serror |$2d-5 ERROR - illegal extension + .long serror |$2d-6 ERROR - illegal extension + .long serror |$2d-7 ERROR - illegal extension + + .long serror |$2e-0 ERROR - illegal extension + .long serror |$2e-1 ERROR - illegal extension + .long serror |$2e-2 ERROR - illegal extension + .long serror |$2e-3 ERROR - illegal extension + .long serror |$2e-4 ERROR - illegal extension + .long serror |$2e-5 ERROR - illegal extension + .long serror |$2e-6 ERROR - illegal extension + .long serror |$2e-7 ERROR - illegal extension + + .long serror |$2f-0 ERROR - illegal extension + .long serror |$2f-1 ERROR - illegal extension + .long serror |$2f-2 ERROR - illegal extension + .long serror |$2f-3 ERROR - illegal extension + .long serror |$2f-4 ERROR - illegal extension + .long serror |$2f-5 ERROR - illegal extension + .long serror |$2f-6 ERROR - illegal extension + .long serror |$2f-7 ERROR - illegal extension + + .long ssincos |$30-0 fsincos norm + .long ssincosz |$30-1 fsincos zero + .long ssincosi |$30-2 fsincos inf + .long ssincosnan |$30-3 fsincos nan + .long ssincosd |$30-4 fsincos denorm + .long serror |$30-5 fsincos ERROR + .long serror |$30-6 fsincos ERROR + .long serror |$30-7 fsincos ERROR + + .long ssincos |$31-0 fsincos norm + .long ssincosz |$31-1 fsincos zero + .long ssincosi |$31-2 fsincos inf + .long ssincosnan |$31-3 fsincos nan + .long ssincosd |$31-4 fsincos denorm + .long serror |$31-5 fsincos ERROR + .long serror |$31-6 fsincos ERROR + .long serror |$31-7 fsincos ERROR + + .long ssincos |$32-0 fsincos norm + .long ssincosz |$32-1 fsincos zero + .long ssincosi |$32-2 fsincos inf + .long ssincosnan |$32-3 fsincos nan + .long ssincosd |$32-4 fsincos denorm + .long serror |$32-5 fsincos ERROR + .long serror |$32-6 fsincos ERROR + .long serror |$32-7 fsincos ERROR + + .long ssincos |$33-0 fsincos norm + .long ssincosz |$33-1 fsincos zero + .long ssincosi |$33-2 fsincos inf + .long ssincosnan |$33-3 fsincos nan + .long ssincosd |$33-4 fsincos denorm + .long serror |$33-5 fsincos ERROR + .long serror |$33-6 fsincos ERROR + .long serror |$33-7 fsincos ERROR + + .long ssincos |$34-0 fsincos norm + .long ssincosz |$34-1 fsincos zero + .long ssincosi |$34-2 fsincos inf + .long ssincosnan |$34-3 fsincos nan + .long ssincosd |$34-4 fsincos denorm + .long serror |$34-5 fsincos ERROR + .long serror |$34-6 fsincos ERROR + .long serror |$34-7 fsincos ERROR + + .long ssincos |$35-0 fsincos norm + .long ssincosz |$35-1 fsincos zero + .long ssincosi |$35-2 fsincos inf + .long ssincosnan |$35-3 fsincos nan + .long ssincosd |$35-4 fsincos denorm + .long serror |$35-5 fsincos ERROR + .long serror |$35-6 fsincos ERROR + .long serror |$35-7 fsincos ERROR + + .long ssincos |$36-0 fsincos norm + .long ssincosz |$36-1 fsincos zero + .long ssincosi |$36-2 fsincos inf + .long ssincosnan |$36-3 fsincos nan + .long ssincosd |$36-4 fsincos denorm + .long serror |$36-5 fsincos ERROR + .long serror |$36-6 fsincos ERROR + .long serror |$36-7 fsincos ERROR + + .long ssincos |$37-0 fsincos norm + .long ssincosz |$37-1 fsincos zero + .long ssincosi |$37-2 fsincos inf + .long ssincosnan |$37-3 fsincos nan + .long ssincosd |$37-4 fsincos denorm + .long serror |$37-5 fsincos ERROR + .long serror |$37-6 fsincos ERROR + .long serror |$37-7 fsincos ERROR + + |end diff --git a/arch/m68k/fpsp040/util.S b/arch/m68k/fpsp040/util.S new file mode 100644 index 000000000..65b26fa88 --- /dev/null +++ b/arch/m68k/fpsp040/util.S @@ -0,0 +1,747 @@ +| +| util.sa 3.7 7/29/91 +| +| This file contains routines used by other programs. +| +| ovf_res: used by overflow to force the correct +| result. ovf_r_k, ovf_r_x2, ovf_r_x3 are +| derivatives of this routine. +| get_fline: get user's opcode word +| g_dfmtou: returns the destination format. +| g_opcls: returns the opclass of the float instruction. +| g_rndpr: returns the rounding precision. +| reg_dest: write byte, word, or long data to Dn +| +| +| Copyright (C) Motorola, Inc. 1990 +| All Rights Reserved +| +| For details on the license for this file, please see the +| file, README, in this same directory. + +|UTIL idnt 2,1 | Motorola 040 Floating Point Software Package + + |section 8 + +#include "fpsp.h" + + |xref mem_read + + .global g_dfmtou + .global g_opcls + .global g_rndpr + .global get_fline + .global reg_dest + +| +| Final result table for ovf_res. Note that the negative counterparts +| are unnecessary as ovf_res always returns the sign separately from +| the exponent. +| ;+inf +EXT_PINF: .long 0x7fff0000,0x00000000,0x00000000,0x00000000 +| ;largest +ext +EXT_PLRG: .long 0x7ffe0000,0xffffffff,0xffffffff,0x00000000 +| ;largest magnitude +sgl in ext +SGL_PLRG: .long 0x407e0000,0xffffff00,0x00000000,0x00000000 +| ;largest magnitude +dbl in ext +DBL_PLRG: .long 0x43fe0000,0xffffffff,0xfffff800,0x00000000 +| ;largest -ext + +tblovfl: + .long EXT_RN + .long EXT_RZ + .long EXT_RM + .long EXT_RP + .long SGL_RN + .long SGL_RZ + .long SGL_RM + .long SGL_RP + .long DBL_RN + .long DBL_RZ + .long DBL_RM + .long DBL_RP + .long error + .long error + .long error + .long error + + +| +| ovf_r_k --- overflow result calculation +| +| This entry point is used by kernel_ex. +| +| This forces the destination precision to be extended +| +| Input: operand in ETEMP +| Output: a result is in ETEMP (internal extended format) +| + .global ovf_r_k +ovf_r_k: + lea ETEMP(%a6),%a0 |a0 points to source operand + bclrb #sign_bit,ETEMP_EX(%a6) + sne ETEMP_SGN(%a6) |convert to internal IEEE format + +| +| ovf_r_x2 --- overflow result calculation +| +| This entry point used by x_ovfl. (opclass 0 and 2) +| +| Input a0 points to an operand in the internal extended format +| Output a0 points to the result in the internal extended format +| +| This sets the round precision according to the user's FPCR unless the +| instruction is fsgldiv or fsglmul or fsadd, fdadd, fsub, fdsub, fsmul, +| fdmul, fsdiv, fddiv, fssqrt, fsmove, fdmove, fsabs, fdabs, fsneg, fdneg. +| If the instruction is fsgldiv of fsglmul, the rounding precision must be +| extended. If the instruction is not fsgldiv or fsglmul but a force- +| precision instruction, the rounding precision is then set to the force +| precision. + + .global ovf_r_x2 +ovf_r_x2: + btstb #E3,E_BYTE(%a6) |check for nu exception + beql ovf_e1_exc |it is cu exception +ovf_e3_exc: + movew CMDREG3B(%a6),%d0 |get the command word + andiw #0x00000060,%d0 |clear all bits except 6 and 5 + cmpil #0x00000040,%d0 + beql ovff_sgl |force precision is single + cmpil #0x00000060,%d0 + beql ovff_dbl |force precision is double + movew CMDREG3B(%a6),%d0 |get the command word again + andil #0x7f,%d0 |clear all except operation + cmpil #0x33,%d0 + beql ovf_fsgl |fsglmul or fsgldiv + cmpil #0x30,%d0 + beql ovf_fsgl + bra ovf_fpcr |instruction is none of the above +| ;use FPCR +ovf_e1_exc: + movew CMDREG1B(%a6),%d0 |get command word + andil #0x00000044,%d0 |clear all bits except 6 and 2 + cmpil #0x00000040,%d0 + beql ovff_sgl |the instruction is force single + cmpil #0x00000044,%d0 + beql ovff_dbl |the instruction is force double + movew CMDREG1B(%a6),%d0 |again get the command word + andil #0x0000007f,%d0 |clear all except the op code + cmpil #0x00000027,%d0 + beql ovf_fsgl |fsglmul + cmpil #0x00000024,%d0 + beql ovf_fsgl |fsgldiv + bra ovf_fpcr |none of the above, use FPCR +| +| +| Inst is either fsgldiv or fsglmul. Force extended precision. +| +ovf_fsgl: + clrl %d0 + bra ovf_res + +ovff_sgl: + movel #0x00000001,%d0 |set single + bra ovf_res +ovff_dbl: + movel #0x00000002,%d0 |set double + bra ovf_res +| +| The precision is in the fpcr. +| +ovf_fpcr: + bfextu FPCR_MODE(%a6){#0:#2},%d0 |set round precision + bra ovf_res + +| +| +| ovf_r_x3 --- overflow result calculation +| +| This entry point used by x_ovfl. (opclass 3 only) +| +| Input a0 points to an operand in the internal extended format +| Output a0 points to the result in the internal extended format +| +| This sets the round precision according to the destination size. +| + .global ovf_r_x3 +ovf_r_x3: + bsr g_dfmtou |get dest fmt in d0{1:0} +| ;for fmovout, the destination format +| ;is the rounding precision + +| +| ovf_res --- overflow result calculation +| +| Input: +| a0 points to operand in internal extended format +| Output: +| a0 points to result in internal extended format +| + .global ovf_res +ovf_res: + lsll #2,%d0 |move round precision to d0{3:2} + bfextu FPCR_MODE(%a6){#2:#2},%d1 |set round mode + orl %d1,%d0 |index is fmt:mode in d0{3:0} + leal tblovfl,%a1 |load a1 with table address + movel %a1@(%d0:l:4),%a1 |use d0 as index to the table + jmp (%a1) |go to the correct routine +| +|case DEST_FMT = EXT +| +EXT_RN: + leal EXT_PINF,%a1 |answer is +/- infinity + bsetb #inf_bit,FPSR_CC(%a6) + bra set_sign |now go set the sign +EXT_RZ: + leal EXT_PLRG,%a1 |answer is +/- large number + bra set_sign |now go set the sign +EXT_RM: + tstb LOCAL_SGN(%a0) |if negative overflow + beqs e_rm_pos +e_rm_neg: + leal EXT_PINF,%a1 |answer is negative infinity + orl #neginf_mask,USER_FPSR(%a6) + bra end_ovfr +e_rm_pos: + leal EXT_PLRG,%a1 |answer is large positive number + bra end_ovfr +EXT_RP: + tstb LOCAL_SGN(%a0) |if negative overflow + beqs e_rp_pos +e_rp_neg: + leal EXT_PLRG,%a1 |answer is large negative number + bsetb #neg_bit,FPSR_CC(%a6) + bra end_ovfr +e_rp_pos: + leal EXT_PINF,%a1 |answer is positive infinity + bsetb #inf_bit,FPSR_CC(%a6) + bra end_ovfr +| +|case DEST_FMT = DBL +| +DBL_RN: + leal EXT_PINF,%a1 |answer is +/- infinity + bsetb #inf_bit,FPSR_CC(%a6) + bra set_sign +DBL_RZ: + leal DBL_PLRG,%a1 |answer is +/- large number + bra set_sign |now go set the sign +DBL_RM: + tstb LOCAL_SGN(%a0) |if negative overflow + beqs d_rm_pos +d_rm_neg: + leal EXT_PINF,%a1 |answer is negative infinity + orl #neginf_mask,USER_FPSR(%a6) + bra end_ovfr |inf is same for all precisions (ext,dbl,sgl) +d_rm_pos: + leal DBL_PLRG,%a1 |answer is large positive number + bra end_ovfr +DBL_RP: + tstb LOCAL_SGN(%a0) |if negative overflow + beqs d_rp_pos +d_rp_neg: + leal DBL_PLRG,%a1 |answer is large negative number + bsetb #neg_bit,FPSR_CC(%a6) + bra end_ovfr +d_rp_pos: + leal EXT_PINF,%a1 |answer is positive infinity + bsetb #inf_bit,FPSR_CC(%a6) + bra end_ovfr +| +|case DEST_FMT = SGL +| +SGL_RN: + leal EXT_PINF,%a1 |answer is +/- infinity + bsetb #inf_bit,FPSR_CC(%a6) + bras set_sign +SGL_RZ: + leal SGL_PLRG,%a1 |answer is +/- large number + bras set_sign +SGL_RM: + tstb LOCAL_SGN(%a0) |if negative overflow + beqs s_rm_pos +s_rm_neg: + leal EXT_PINF,%a1 |answer is negative infinity + orl #neginf_mask,USER_FPSR(%a6) + bras end_ovfr +s_rm_pos: + leal SGL_PLRG,%a1 |answer is large positive number + bras end_ovfr +SGL_RP: + tstb LOCAL_SGN(%a0) |if negative overflow + beqs s_rp_pos +s_rp_neg: + leal SGL_PLRG,%a1 |answer is large negative number + bsetb #neg_bit,FPSR_CC(%a6) + bras end_ovfr +s_rp_pos: + leal EXT_PINF,%a1 |answer is positive infinity + bsetb #inf_bit,FPSR_CC(%a6) + bras end_ovfr + +set_sign: + tstb LOCAL_SGN(%a0) |if negative overflow + beqs end_ovfr +neg_sign: + bsetb #neg_bit,FPSR_CC(%a6) + +end_ovfr: + movew LOCAL_EX(%a1),LOCAL_EX(%a0) |do not overwrite sign + movel LOCAL_HI(%a1),LOCAL_HI(%a0) + movel LOCAL_LO(%a1),LOCAL_LO(%a0) + rts + + +| +| ERROR +| +error: + rts +| +| get_fline --- get f-line opcode of interrupted instruction +| +| Returns opcode in the low word of d0. +| +get_fline: + movel USER_FPIAR(%a6),%a0 |opcode address + movel #0,-(%a7) |reserve a word on the stack + leal 2(%a7),%a1 |point to low word of temporary + movel #2,%d0 |count + bsrl mem_read + movel (%a7)+,%d0 + rts +| +| g_rndpr --- put rounding precision in d0{1:0} +| +| valid return codes are: +| 00 - extended +| 01 - single +| 10 - double +| +| begin +| get rounding precision (cmdreg3b{6:5}) +| begin +| case opclass = 011 (move out) +| get destination format - this is the also the rounding precision +| +| case opclass = 0x0 +| if E3 +| *case RndPr(from cmdreg3b{6:5} = 11 then RND_PREC = DBL +| *case RndPr(from cmdreg3b{6:5} = 10 then RND_PREC = SGL +| case RndPr(from cmdreg3b{6:5} = 00 | 01 +| use precision from FPCR{7:6} +| case 00 then RND_PREC = EXT +| case 01 then RND_PREC = SGL +| case 10 then RND_PREC = DBL +| else E1 +| use precision in FPCR{7:6} +| case 00 then RND_PREC = EXT +| case 01 then RND_PREC = SGL +| case 10 then RND_PREC = DBL +| end +| +g_rndpr: + bsr g_opcls |get opclass in d0{2:0} + cmpw #0x0003,%d0 |check for opclass 011 + bnes op_0x0 + +| +| For move out instructions (opclass 011) the destination format +| is the same as the rounding precision. Pass results from g_dfmtou. +| + bsr g_dfmtou + rts +op_0x0: + btstb #E3,E_BYTE(%a6) + beql unf_e1_exc |branch to e1 underflow +unf_e3_exc: + movel CMDREG3B(%a6),%d0 |rounding precision in d0{10:9} + bfextu %d0{#9:#2},%d0 |move the rounding prec bits to d0{1:0} + cmpil #0x2,%d0 + beql unff_sgl |force precision is single + cmpil #0x3,%d0 |force precision is double + beql unff_dbl + movew CMDREG3B(%a6),%d0 |get the command word again + andil #0x7f,%d0 |clear all except operation + cmpil #0x33,%d0 + beql unf_fsgl |fsglmul or fsgldiv + cmpil #0x30,%d0 + beql unf_fsgl |fsgldiv or fsglmul + bra unf_fpcr +unf_e1_exc: + movel CMDREG1B(%a6),%d0 |get 32 bits off the stack, 1st 16 bits +| ;are the command word + andil #0x00440000,%d0 |clear all bits except bits 6 and 2 + cmpil #0x00400000,%d0 + beql unff_sgl |force single + cmpil #0x00440000,%d0 |force double + beql unff_dbl + movel CMDREG1B(%a6),%d0 |get the command word again + andil #0x007f0000,%d0 |clear all bits except the operation + cmpil #0x00270000,%d0 + beql unf_fsgl |fsglmul + cmpil #0x00240000,%d0 + beql unf_fsgl |fsgldiv + bra unf_fpcr + +| +| Convert to return format. The values from cmdreg3b and the return +| values are: +| cmdreg3b return precision +| -------- ------ --------- +| 00,01 0 ext +| 10 1 sgl +| 11 2 dbl +| Force single +| +unff_sgl: + movel #1,%d0 |return 1 + rts +| +| Force double +| +unff_dbl: + movel #2,%d0 |return 2 + rts +| +| Force extended +| +unf_fsgl: + movel #0,%d0 + rts +| +| Get rounding precision set in FPCR{7:6}. +| +unf_fpcr: + movel USER_FPCR(%a6),%d0 |rounding precision bits in d0{7:6} + bfextu %d0{#24:#2},%d0 |move the rounding prec bits to d0{1:0} + rts +| +| g_opcls --- put opclass in d0{2:0} +| +g_opcls: + btstb #E3,E_BYTE(%a6) + beqs opc_1b |if set, go to cmdreg1b +opc_3b: + clrl %d0 |if E3, only opclass 0x0 is possible + rts +opc_1b: + movel CMDREG1B(%a6),%d0 + bfextu %d0{#0:#3},%d0 |shift opclass bits d0{31:29} to d0{2:0} + rts +| +| g_dfmtou --- put destination format in d0{1:0} +| +| If E1, the format is from cmdreg1b{12:10} +| If E3, the format is extended. +| +| Dest. Fmt. +| extended 010 -> 00 +| single 001 -> 01 +| double 101 -> 10 +| +g_dfmtou: + btstb #E3,E_BYTE(%a6) + beqs op011 + clrl %d0 |if E1, size is always ext + rts +op011: + movel CMDREG1B(%a6),%d0 + bfextu %d0{#3:#3},%d0 |dest fmt from cmdreg1b{12:10} + cmpb #1,%d0 |check for single + bnes not_sgl + movel #1,%d0 + rts +not_sgl: + cmpb #5,%d0 |check for double + bnes not_dbl + movel #2,%d0 + rts +not_dbl: + clrl %d0 |must be extended + rts + +| +| +| Final result table for unf_sub. Note that the negative counterparts +| are unnecessary as unf_sub always returns the sign separately from +| the exponent. +| ;+zero +EXT_PZRO: .long 0x00000000,0x00000000,0x00000000,0x00000000 +| ;+zero +SGL_PZRO: .long 0x3f810000,0x00000000,0x00000000,0x00000000 +| ;+zero +DBL_PZRO: .long 0x3c010000,0x00000000,0x00000000,0x00000000 +| ;smallest +ext denorm +EXT_PSML: .long 0x00000000,0x00000000,0x00000001,0x00000000 +| ;smallest +sgl denorm +SGL_PSML: .long 0x3f810000,0x00000100,0x00000000,0x00000000 +| ;smallest +dbl denorm +DBL_PSML: .long 0x3c010000,0x00000000,0x00000800,0x00000000 +| +| UNF_SUB --- underflow result calculation +| +| Input: +| d0 contains round precision +| a0 points to input operand in the internal extended format +| +| Output: +| a0 points to correct internal extended precision result. +| + +tblunf: + .long uEXT_RN + .long uEXT_RZ + .long uEXT_RM + .long uEXT_RP + .long uSGL_RN + .long uSGL_RZ + .long uSGL_RM + .long uSGL_RP + .long uDBL_RN + .long uDBL_RZ + .long uDBL_RM + .long uDBL_RP + .long uDBL_RN + .long uDBL_RZ + .long uDBL_RM + .long uDBL_RP + + .global unf_sub +unf_sub: + lsll #2,%d0 |move round precision to d0{3:2} + bfextu FPCR_MODE(%a6){#2:#2},%d1 |set round mode + orl %d1,%d0 |index is fmt:mode in d0{3:0} + leal tblunf,%a1 |load a1 with table address + movel %a1@(%d0:l:4),%a1 |use d0 as index to the table + jmp (%a1) |go to the correct routine +| +|case DEST_FMT = EXT +| +uEXT_RN: + leal EXT_PZRO,%a1 |answer is +/- zero + bsetb #z_bit,FPSR_CC(%a6) + bra uset_sign |now go set the sign +uEXT_RZ: + leal EXT_PZRO,%a1 |answer is +/- zero + bsetb #z_bit,FPSR_CC(%a6) + bra uset_sign |now go set the sign +uEXT_RM: + tstb LOCAL_SGN(%a0) |if negative underflow + beqs ue_rm_pos +ue_rm_neg: + leal EXT_PSML,%a1 |answer is negative smallest denorm + bsetb #neg_bit,FPSR_CC(%a6) + bra end_unfr +ue_rm_pos: + leal EXT_PZRO,%a1 |answer is positive zero + bsetb #z_bit,FPSR_CC(%a6) + bra end_unfr +uEXT_RP: + tstb LOCAL_SGN(%a0) |if negative underflow + beqs ue_rp_pos +ue_rp_neg: + leal EXT_PZRO,%a1 |answer is negative zero + oril #negz_mask,USER_FPSR(%a6) + bra end_unfr +ue_rp_pos: + leal EXT_PSML,%a1 |answer is positive smallest denorm + bra end_unfr +| +|case DEST_FMT = DBL +| +uDBL_RN: + leal DBL_PZRO,%a1 |answer is +/- zero + bsetb #z_bit,FPSR_CC(%a6) + bra uset_sign +uDBL_RZ: + leal DBL_PZRO,%a1 |answer is +/- zero + bsetb #z_bit,FPSR_CC(%a6) + bra uset_sign |now go set the sign +uDBL_RM: + tstb LOCAL_SGN(%a0) |if negative overflow + beqs ud_rm_pos +ud_rm_neg: + leal DBL_PSML,%a1 |answer is smallest denormalized negative + bsetb #neg_bit,FPSR_CC(%a6) + bra end_unfr +ud_rm_pos: + leal DBL_PZRO,%a1 |answer is positive zero + bsetb #z_bit,FPSR_CC(%a6) + bra end_unfr +uDBL_RP: + tstb LOCAL_SGN(%a0) |if negative overflow + beqs ud_rp_pos +ud_rp_neg: + leal DBL_PZRO,%a1 |answer is negative zero + oril #negz_mask,USER_FPSR(%a6) + bra end_unfr +ud_rp_pos: + leal DBL_PSML,%a1 |answer is smallest denormalized negative + bra end_unfr +| +|case DEST_FMT = SGL +| +uSGL_RN: + leal SGL_PZRO,%a1 |answer is +/- zero + bsetb #z_bit,FPSR_CC(%a6) + bras uset_sign +uSGL_RZ: + leal SGL_PZRO,%a1 |answer is +/- zero + bsetb #z_bit,FPSR_CC(%a6) + bras uset_sign +uSGL_RM: + tstb LOCAL_SGN(%a0) |if negative overflow + beqs us_rm_pos +us_rm_neg: + leal SGL_PSML,%a1 |answer is smallest denormalized negative + bsetb #neg_bit,FPSR_CC(%a6) + bras end_unfr +us_rm_pos: + leal SGL_PZRO,%a1 |answer is positive zero + bsetb #z_bit,FPSR_CC(%a6) + bras end_unfr +uSGL_RP: + tstb LOCAL_SGN(%a0) |if negative overflow + beqs us_rp_pos +us_rp_neg: + leal SGL_PZRO,%a1 |answer is negative zero + oril #negz_mask,USER_FPSR(%a6) + bras end_unfr +us_rp_pos: + leal SGL_PSML,%a1 |answer is smallest denormalized positive + bras end_unfr + +uset_sign: + tstb LOCAL_SGN(%a0) |if negative overflow + beqs end_unfr +uneg_sign: + bsetb #neg_bit,FPSR_CC(%a6) + +end_unfr: + movew LOCAL_EX(%a1),LOCAL_EX(%a0) |be careful not to overwrite sign + movel LOCAL_HI(%a1),LOCAL_HI(%a0) + movel LOCAL_LO(%a1),LOCAL_LO(%a0) + rts +| +| reg_dest --- write byte, word, or long data to Dn +| +| +| Input: +| L_SCR1: Data +| d1: data size and dest register number formatted as: +| +| 32 5 4 3 2 1 0 +| ----------------------------------------------- +| | 0 | Size | Dest Reg # | +| ----------------------------------------------- +| +| Size is: +| 0 - Byte +| 1 - Word +| 2 - Long/Single +| +pregdst: + .long byte_d0 + .long byte_d1 + .long byte_d2 + .long byte_d3 + .long byte_d4 + .long byte_d5 + .long byte_d6 + .long byte_d7 + .long word_d0 + .long word_d1 + .long word_d2 + .long word_d3 + .long word_d4 + .long word_d5 + .long word_d6 + .long word_d7 + .long long_d0 + .long long_d1 + .long long_d2 + .long long_d3 + .long long_d4 + .long long_d5 + .long long_d6 + .long long_d7 + +reg_dest: + leal pregdst,%a0 + movel %a0@(%d1:l:4),%a0 + jmp (%a0) + +byte_d0: + moveb L_SCR1(%a6),USER_D0+3(%a6) + rts +byte_d1: + moveb L_SCR1(%a6),USER_D1+3(%a6) + rts +byte_d2: + moveb L_SCR1(%a6),%d2 + rts +byte_d3: + moveb L_SCR1(%a6),%d3 + rts +byte_d4: + moveb L_SCR1(%a6),%d4 + rts +byte_d5: + moveb L_SCR1(%a6),%d5 + rts +byte_d6: + moveb L_SCR1(%a6),%d6 + rts +byte_d7: + moveb L_SCR1(%a6),%d7 + rts +word_d0: + movew L_SCR1(%a6),USER_D0+2(%a6) + rts +word_d1: + movew L_SCR1(%a6),USER_D1+2(%a6) + rts +word_d2: + movew L_SCR1(%a6),%d2 + rts +word_d3: + movew L_SCR1(%a6),%d3 + rts +word_d4: + movew L_SCR1(%a6),%d4 + rts +word_d5: + movew L_SCR1(%a6),%d5 + rts +word_d6: + movew L_SCR1(%a6),%d6 + rts +word_d7: + movew L_SCR1(%a6),%d7 + rts +long_d0: + movel L_SCR1(%a6),USER_D0(%a6) + rts +long_d1: + movel L_SCR1(%a6),USER_D1(%a6) + rts +long_d2: + movel L_SCR1(%a6),%d2 + rts +long_d3: + movel L_SCR1(%a6),%d3 + rts +long_d4: + movel L_SCR1(%a6),%d4 + rts +long_d5: + movel L_SCR1(%a6),%d5 + rts +long_d6: + movel L_SCR1(%a6),%d6 + rts +long_d7: + movel L_SCR1(%a6),%d7 + rts + |end diff --git a/arch/m68k/fpsp040/x_bsun.S b/arch/m68k/fpsp040/x_bsun.S new file mode 100644 index 000000000..d5a576bfa --- /dev/null +++ b/arch/m68k/fpsp040/x_bsun.S @@ -0,0 +1,46 @@ +| +| x_bsun.sa 3.3 7/1/91 +| +| fpsp_bsun --- FPSP handler for branch/set on unordered exception +| +| Copy the PC to FPIAR to maintain 881/882 compatibility +| +| The real_bsun handler will need to perform further corrective +| measures as outlined in the 040 User's Manual on pages +| 9-41f, section 9.8.3. +| + +| Copyright (C) Motorola, Inc. 1990 +| All Rights Reserved +| +| For details on the license for this file, please see the +| file, README, in this same directory. + +X_BSUN: |idnt 2,1 | Motorola 040 Floating Point Software Package + + |section 8 + +#include "fpsp.h" + + |xref real_bsun + + .global fpsp_bsun +fpsp_bsun: +| + link %a6,#-LOCAL_SIZE + fsave -(%a7) + moveml %d0-%d1/%a0-%a1,USER_DA(%a6) + fmovemx %fp0-%fp3,USER_FP0(%a6) + fmoveml %fpcr/%fpsr/%fpiar,USER_FPCR(%a6) + +| + movel EXC_PC(%a6),USER_FPIAR(%a6) +| + moveml USER_DA(%a6),%d0-%d1/%a0-%a1 + fmovemx USER_FP0(%a6),%fp0-%fp3 + fmoveml USER_FPCR(%a6),%fpcr/%fpsr/%fpiar + frestore (%a7)+ + unlk %a6 + bral real_bsun +| + |end diff --git a/arch/m68k/fpsp040/x_fline.S b/arch/m68k/fpsp040/x_fline.S new file mode 100644 index 000000000..264e126d1 --- /dev/null +++ b/arch/m68k/fpsp040/x_fline.S @@ -0,0 +1,103 @@ +| +| x_fline.sa 3.3 1/10/91 +| +| fpsp_fline --- FPSP handler for fline exception +| +| First determine if the exception is one of the unimplemented +| floating point instructions. If so, let fpsp_unimp handle it. +| Next, determine if the instruction is an fmovecr with a non-zero +| field. If so, handle here and return. Otherwise, it +| must be a real F-line exception. +| + +| Copyright (C) Motorola, Inc. 1990 +| All Rights Reserved +| +| For details on the license for this file, please see the +| file, README, in this same directory. + +X_FLINE: |idnt 2,1 | Motorola 040 Floating Point Software Package + + |section 8 + +#include "fpsp.h" + + |xref real_fline + |xref fpsp_unimp + |xref uni_2 + |xref mem_read + |xref fpsp_fmt_error + + .global fpsp_fline +fpsp_fline: +| +| check for unimplemented vector first. Use EXC_VEC-4 because +| the equate is valid only after a 'link a6' has pushed one more +| long onto the stack. +| + cmpw #UNIMP_VEC,EXC_VEC-4(%a7) + beql fpsp_unimp + +| +| fmovecr with non-zero handling here +| + subl #4,%a7 |4 accounts for 2-word difference +| ;between six word frame (unimp) and +| ;four word frame + link %a6,#-LOCAL_SIZE + fsave -(%a7) + moveml %d0-%d1/%a0-%a1,USER_DA(%a6) + moveal EXC_PC+4(%a6),%a0 |get address of fline instruction + leal L_SCR1(%a6),%a1 |use L_SCR1 as scratch + movel #4,%d0 + addl #4,%a6 |to offset the sub.l #4,a7 above so that +| ;a6 can point correctly to the stack frame +| ;before branching to mem_read + bsrl mem_read + subl #4,%a6 + movel L_SCR1(%a6),%d0 |d0 contains the fline and command word + bfextu %d0{#4:#3},%d1 |extract coprocessor id + cmpib #1,%d1 |check if cpid=1 + bne not_mvcr |exit if not + bfextu %d0{#16:#6},%d1 + cmpib #0x17,%d1 |check if it is an FMOVECR encoding + bne not_mvcr +| ;if an FMOVECR instruction, fix stack +| ;and go to FPSP_UNIMP +fix_stack: + cmpib #VER_40,(%a7) |test for orig unimp frame + bnes ck_rev + subl #UNIMP_40_SIZE-4,%a7 |emulate an orig fsave + moveb #VER_40,(%a7) + moveb #UNIMP_40_SIZE-4,1(%a7) + clrw 2(%a7) + bras fix_con +ck_rev: + cmpib #VER_41,(%a7) |test for rev unimp frame + bnel fpsp_fmt_error |if not $40 or $41, exit with error + subl #UNIMP_41_SIZE-4,%a7 |emulate a rev fsave + moveb #VER_41,(%a7) + moveb #UNIMP_41_SIZE-4,1(%a7) + clrw 2(%a7) +fix_con: + movew EXC_SR+4(%a6),EXC_SR(%a6) |move stacked sr to new position + movel EXC_PC+4(%a6),EXC_PC(%a6) |move stacked pc to new position + fmovel EXC_PC(%a6),%FPIAR |point FPIAR to fline inst + movel #4,%d1 + addl %d1,EXC_PC(%a6) |increment stacked pc value to next inst + movew #0x202c,EXC_VEC(%a6) |reformat vector to unimp + clrl EXC_EA(%a6) |clear the EXC_EA field + movew %d0,CMDREG1B(%a6) |move the lower word into CMDREG1B + clrl E_BYTE(%a6) + bsetb #UFLAG,T_BYTE(%a6) + moveml USER_DA(%a6),%d0-%d1/%a0-%a1 |restore data registers + bral uni_2 + +not_mvcr: + moveml USER_DA(%a6),%d0-%d1/%a0-%a1 |restore data registers + frestore (%a7)+ + unlk %a6 + addl #4,%a7 + bral real_fline + + |end diff --git a/arch/m68k/fpsp040/x_operr.S b/arch/m68k/fpsp040/x_operr.S new file mode 100644 index 000000000..e2c371c3a --- /dev/null +++ b/arch/m68k/fpsp040/x_operr.S @@ -0,0 +1,355 @@ +| +| x_operr.sa 3.5 7/1/91 +| +| fpsp_operr --- FPSP handler for operand error exception +| +| See 68040 User's Manual pp. 9-44f +| +| Note 1: For trap disabled 040 does the following: +| If the dest is a fp reg, then an extended precision non_signaling +| NAN is stored in the dest reg. If the dest format is b, w, or l and +| the source op is a NAN, then garbage is stored as the result (actually +| the upper 32 bits of the mantissa are sent to the integer unit). If +| the dest format is integer (b, w, l) and the operr is caused by +| integer overflow, or the source op is inf, then the result stored is +| garbage. +| There are three cases in which operr is incorrectly signaled on the +| 040. This occurs for move_out of format b, w, or l for the largest +| negative integer (-2^7 for b, -2^15 for w, -2^31 for l). +| +| On opclass = 011 fmove.(b,w,l) that causes a conversion +| overflow -> OPERR, the exponent in wbte (and fpte) is: +| byte 56 - (62 - exp) +| word 48 - (62 - exp) +| long 32 - (62 - exp) +| +| where exp = (true exp) - 1 +| +| So, wbtemp and fptemp will contain the following on erroneously +| signalled operr: +| fpts = 1 +| fpte = $4000 (15 bit externally) +| byte fptm = $ffffffff ffffff80 +| word fptm = $ffffffff ffff8000 +| long fptm = $ffffffff 80000000 +| +| Note 2: For trap enabled 040 does the following: +| If the inst is move_out, then same as Note 1. +| If the inst is not move_out, the dest is not modified. +| The exceptional operand is not defined for integer overflow +| during a move_out. +| + +| Copyright (C) Motorola, Inc. 1990 +| All Rights Reserved +| +| For details on the license for this file, please see the +| file, README, in this same directory. + +X_OPERR: |idnt 2,1 | Motorola 040 Floating Point Software Package + + |section 8 + +#include "fpsp.h" + + |xref mem_write + |xref real_operr + |xref real_inex + |xref get_fline + |xref fpsp_done + |xref reg_dest + + .global fpsp_operr +fpsp_operr: +| + link %a6,#-LOCAL_SIZE + fsave -(%a7) + moveml %d0-%d1/%a0-%a1,USER_DA(%a6) + fmovemx %fp0-%fp3,USER_FP0(%a6) + fmoveml %fpcr/%fpsr/%fpiar,USER_FPCR(%a6) + +| +| Check if this is an opclass 3 instruction. +| If so, fall through, else branch to operr_end +| + btstb #TFLAG,T_BYTE(%a6) + beqs operr_end + +| +| If the destination size is B,W,or L, the operr must be +| handled here. +| + movel CMDREG1B(%a6),%d0 + bfextu %d0{#3:#3},%d0 |0=long, 4=word, 6=byte + cmpib #0,%d0 |determine size; check long + beq operr_long + cmpib #4,%d0 |check word + beq operr_word + cmpib #6,%d0 |check byte + beq operr_byte + +| +| The size is not B,W,or L, so the operr is handled by the +| kernel handler. Set the operr bits and clean up, leaving +| only the integer exception frame on the stack, and the +| fpu in the original exceptional state. +| +operr_end: + bsetb #operr_bit,FPSR_EXCEPT(%a6) + bsetb #aiop_bit,FPSR_AEXCEPT(%a6) + + moveml USER_DA(%a6),%d0-%d1/%a0-%a1 + fmovemx USER_FP0(%a6),%fp0-%fp3 + fmoveml USER_FPCR(%a6),%fpcr/%fpsr/%fpiar + frestore (%a7)+ + unlk %a6 + bral real_operr + +operr_long: + moveql #4,%d1 |write size to d1 + moveb STAG(%a6),%d0 |test stag for nan + andib #0xe0,%d0 |clr all but tag + cmpib #0x60,%d0 |check for nan + beq operr_nan + cmpil #0x80000000,FPTEMP_LO(%a6) |test if ls lword is special + bnes chklerr |if not equal, check for incorrect operr + bsr check_upper |check if exp and ms mant are special + tstl %d0 + bnes chklerr |if d0 is true, check for incorrect operr + movel #0x80000000,%d0 |store special case result + bsr operr_store + bra not_enabled |clean and exit +| +| CHECK FOR INCORRECTLY GENERATED OPERR EXCEPTION HERE +| +chklerr: + movew FPTEMP_EX(%a6),%d0 + andw #0x7FFF,%d0 |ignore sign bit + cmpw #0x3FFE,%d0 |this is the only possible exponent value + bnes chklerr2 +fixlong: + movel FPTEMP_LO(%a6),%d0 + bsr operr_store + bra not_enabled +chklerr2: + movew FPTEMP_EX(%a6),%d0 + andw #0x7FFF,%d0 |ignore sign bit + cmpw #0x4000,%d0 + bcc store_max |exponent out of range + + movel FPTEMP_LO(%a6),%d0 + andl #0x7FFF0000,%d0 |look for all 1's on bits 30-16 + cmpl #0x7FFF0000,%d0 + beqs fixlong + + tstl FPTEMP_LO(%a6) + bpls chklepos + cmpl #0xFFFFFFFF,FPTEMP_HI(%a6) + beqs fixlong + bra store_max +chklepos: + tstl FPTEMP_HI(%a6) + beqs fixlong + bra store_max + +operr_word: + moveql #2,%d1 |write size to d1 + moveb STAG(%a6),%d0 |test stag for nan + andib #0xe0,%d0 |clr all but tag + cmpib #0x60,%d0 |check for nan + beq operr_nan + cmpil #0xffff8000,FPTEMP_LO(%a6) |test if ls lword is special + bnes chkwerr |if not equal, check for incorrect operr + bsr check_upper |check if exp and ms mant are special + tstl %d0 + bnes chkwerr |if d0 is true, check for incorrect operr + movel #0x80000000,%d0 |store special case result + bsr operr_store + bra not_enabled |clean and exit +| +| CHECK FOR INCORRECTLY GENERATED OPERR EXCEPTION HERE +| +chkwerr: + movew FPTEMP_EX(%a6),%d0 + andw #0x7FFF,%d0 |ignore sign bit + cmpw #0x3FFE,%d0 |this is the only possible exponent value + bnes store_max + movel FPTEMP_LO(%a6),%d0 + swap %d0 + bsr operr_store + bra not_enabled + +operr_byte: + moveql #1,%d1 |write size to d1 + moveb STAG(%a6),%d0 |test stag for nan + andib #0xe0,%d0 |clr all but tag + cmpib #0x60,%d0 |check for nan + beqs operr_nan + cmpil #0xffffff80,FPTEMP_LO(%a6) |test if ls lword is special + bnes chkberr |if not equal, check for incorrect operr + bsr check_upper |check if exp and ms mant are special + tstl %d0 + bnes chkberr |if d0 is true, check for incorrect operr + movel #0x80000000,%d0 |store special case result + bsr operr_store + bra not_enabled |clean and exit +| +| CHECK FOR INCORRECTLY GENERATED OPERR EXCEPTION HERE +| +chkberr: + movew FPTEMP_EX(%a6),%d0 + andw #0x7FFF,%d0 |ignore sign bit + cmpw #0x3FFE,%d0 |this is the only possible exponent value + bnes store_max + movel FPTEMP_LO(%a6),%d0 + asll #8,%d0 + swap %d0 + bsr operr_store + bra not_enabled + +| +| This operr condition is not of the special case. Set operr +| and aiop and write the portion of the nan to memory for the +| given size. +| +operr_nan: + orl #opaop_mask,USER_FPSR(%a6) |set operr & aiop + + movel ETEMP_HI(%a6),%d0 |output will be from upper 32 bits + bsr operr_store + bra end_operr +| +| Store_max loads the max pos or negative for the size, sets +| the operr and aiop bits, and clears inex and ainex, incorrectly +| set by the 040. +| +store_max: + orl #opaop_mask,USER_FPSR(%a6) |set operr & aiop + bclrb #inex2_bit,FPSR_EXCEPT(%a6) + bclrb #ainex_bit,FPSR_AEXCEPT(%a6) + fmovel #0,%FPSR + + tstw FPTEMP_EX(%a6) |check sign + blts load_neg + movel #0x7fffffff,%d0 + bsr operr_store + bra end_operr +load_neg: + movel #0x80000000,%d0 + bsr operr_store + bra end_operr + +| +| This routine stores the data in d0, for the given size in d1, +| to memory or data register as required. A read of the fline +| is required to determine the destination. +| +operr_store: + movel %d0,L_SCR1(%a6) |move write data to L_SCR1 + movel %d1,-(%a7) |save register size + bsrl get_fline |fline returned in d0 + movel (%a7)+,%d1 + bftst %d0{#26:#3} |if mode is zero, dest is Dn + bnes dest_mem +| +| Destination is Dn. Get register number from d0. Data is on +| the stack at (a7). D1 has size: 1=byte,2=word,4=long/single +| + andil #7,%d0 |isolate register number + cmpil #4,%d1 + beqs op_long |the most frequent case + cmpil #2,%d1 + bnes op_con + orl #8,%d0 + bras op_con +op_long: + orl #0x10,%d0 +op_con: + movel %d0,%d1 |format size:reg for reg_dest + bral reg_dest |call to reg_dest returns to caller +| ;of operr_store +| +| Destination is memory. Get from integer exception frame +| and call mem_write. +| +dest_mem: + leal L_SCR1(%a6),%a0 |put ptr to write data in a0 + movel EXC_EA(%a6),%a1 |put user destination address in a1 + movel %d1,%d0 |put size in d0 + bsrl mem_write + rts +| +| Check the exponent for $c000 and the upper 32 bits of the +| mantissa for $ffffffff. If both are true, return d0 clr +| and store the lower n bits of the least lword of FPTEMP +| to d0 for write out. If not, it is a real operr, and set d0. +| +check_upper: + cmpil #0xffffffff,FPTEMP_HI(%a6) |check if first byte is all 1's + bnes true_operr |if not all 1's then was true operr + cmpiw #0xc000,FPTEMP_EX(%a6) |check if incorrectly signalled + beqs not_true_operr |branch if not true operr + cmpiw #0xbfff,FPTEMP_EX(%a6) |check if incorrectly signalled + beqs not_true_operr |branch if not true operr +true_operr: + movel #1,%d0 |signal real operr + rts +not_true_operr: + clrl %d0 |signal no real operr + rts + +| +| End_operr tests for operr enabled. If not, it cleans up the stack +| and does an rte. If enabled, it cleans up the stack and branches +| to the kernel operr handler with only the integer exception +| frame on the stack and the fpu in the original exceptional state +| with correct data written to the destination. +| +end_operr: + btstb #operr_bit,FPCR_ENABLE(%a6) + beqs not_enabled +enabled: + moveml USER_DA(%a6),%d0-%d1/%a0-%a1 + fmovemx USER_FP0(%a6),%fp0-%fp3 + fmoveml USER_FPCR(%a6),%fpcr/%fpsr/%fpiar + frestore (%a7)+ + unlk %a6 + bral real_operr + +not_enabled: +| +| It is possible to have either inex2 or inex1 exceptions with the +| operr. If the inex enable bit is set in the FPCR, and either +| inex2 or inex1 occurred, we must clean up and branch to the +| real inex handler. +| +ck_inex: + moveb FPCR_ENABLE(%a6),%d0 + andb FPSR_EXCEPT(%a6),%d0 + andib #0x3,%d0 + beq operr_exit +| +| Inexact enabled and reported, and we must take an inexact exception. +| +take_inex: + moveb #INEX_VEC,EXC_VEC+1(%a6) + movel USER_FPSR(%a6),FPSR_SHADOW(%a6) + orl #sx_mask,E_BYTE(%a6) + moveml USER_DA(%a6),%d0-%d1/%a0-%a1 + fmovemx USER_FP0(%a6),%fp0-%fp3 + fmoveml USER_FPCR(%a6),%fpcr/%fpsr/%fpiar + frestore (%a7)+ + unlk %a6 + bral real_inex +| +| Since operr is only an E1 exception, there is no need to frestore +| any state back to the fpu. +| +operr_exit: + moveml USER_DA(%a6),%d0-%d1/%a0-%a1 + fmovemx USER_FP0(%a6),%fp0-%fp3 + fmoveml USER_FPCR(%a6),%fpcr/%fpsr/%fpiar + unlk %a6 + bral fpsp_done + + |end diff --git a/arch/m68k/fpsp040/x_ovfl.S b/arch/m68k/fpsp040/x_ovfl.S new file mode 100644 index 000000000..6fe4989ee --- /dev/null +++ b/arch/m68k/fpsp040/x_ovfl.S @@ -0,0 +1,185 @@ +| +| x_ovfl.sa 3.5 7/1/91 +| +| fpsp_ovfl --- FPSP handler for overflow exception +| +| Overflow occurs when a floating-point intermediate result is +| too large to be represented in a floating-point data register, +| or when storing to memory, the contents of a floating-point +| data register are too large to be represented in the +| destination format. +| +| Trap disabled results +| +| If the instruction is move_out, then garbage is stored in the +| destination. If the instruction is not move_out, then the +| destination is not affected. For 68881 compatibility, the +| following values should be stored at the destination, based +| on the current rounding mode: +| +| RN Infinity with the sign of the intermediate result. +| RZ Largest magnitude number, with the sign of the +| intermediate result. +| RM For pos overflow, the largest pos number. For neg overflow, +| -infinity +| RP For pos overflow, +infinity. For neg overflow, the largest +| neg number +| +| Trap enabled results +| All trap disabled code applies. In addition the exceptional +| operand needs to be made available to the users exception handler +| with a bias of $6000 subtracted from the exponent. +| +| + +| Copyright (C) Motorola, Inc. 1990 +| All Rights Reserved +| +| For details on the license for this file, please see the +| file, README, in this same directory. + +X_OVFL: |idnt 2,1 | Motorola 040 Floating Point Software Package + + |section 8 + +#include "fpsp.h" + + |xref ovf_r_x2 + |xref ovf_r_x3 + |xref store + |xref real_ovfl + |xref real_inex + |xref fpsp_done + |xref g_opcls + |xref b1238_fix + + .global fpsp_ovfl +fpsp_ovfl: + link %a6,#-LOCAL_SIZE + fsave -(%a7) + moveml %d0-%d1/%a0-%a1,USER_DA(%a6) + fmovemx %fp0-%fp3,USER_FP0(%a6) + fmoveml %fpcr/%fpsr/%fpiar,USER_FPCR(%a6) + +| +| The 040 doesn't set the AINEX bit in the FPSR, the following +| line temporarily rectifies this error. +| + bsetb #ainex_bit,FPSR_AEXCEPT(%a6) +| + bsrl ovf_adj |denormalize, round & store interm op +| +| if overflow traps not enabled check for inexact exception +| + btstb #ovfl_bit,FPCR_ENABLE(%a6) + beqs ck_inex +| + btstb #E3,E_BYTE(%a6) + beqs no_e3_1 + bfextu CMDREG3B(%a6){#6:#3},%d0 |get dest reg no + bclrb %d0,FPR_DIRTY_BITS(%a6) |clr dest dirty bit + bsrl b1238_fix + movel USER_FPSR(%a6),FPSR_SHADOW(%a6) + orl #sx_mask,E_BYTE(%a6) +no_e3_1: + moveml USER_DA(%a6),%d0-%d1/%a0-%a1 + fmovemx USER_FP0(%a6),%fp0-%fp3 + fmoveml USER_FPCR(%a6),%fpcr/%fpsr/%fpiar + frestore (%a7)+ + unlk %a6 + bral real_ovfl +| +| It is possible to have either inex2 or inex1 exceptions with the +| ovfl. If the inex enable bit is set in the FPCR, and either +| inex2 or inex1 occurred, we must clean up and branch to the +| real inex handler. +| +ck_inex: +| move.b FPCR_ENABLE(%a6),%d0 +| and.b FPSR_EXCEPT(%a6),%d0 +| andi.b #$3,%d0 + btstb #inex2_bit,FPCR_ENABLE(%a6) + beqs ovfl_exit +| +| Inexact enabled and reported, and we must take an inexact exception. +| +take_inex: + btstb #E3,E_BYTE(%a6) + beqs no_e3_2 + bfextu CMDREG3B(%a6){#6:#3},%d0 |get dest reg no + bclrb %d0,FPR_DIRTY_BITS(%a6) |clr dest dirty bit + bsrl b1238_fix + movel USER_FPSR(%a6),FPSR_SHADOW(%a6) + orl #sx_mask,E_BYTE(%a6) +no_e3_2: + moveb #INEX_VEC,EXC_VEC+1(%a6) + moveml USER_DA(%a6),%d0-%d1/%a0-%a1 + fmovemx USER_FP0(%a6),%fp0-%fp3 + fmoveml USER_FPCR(%a6),%fpcr/%fpsr/%fpiar + frestore (%a7)+ + unlk %a6 + bral real_inex + +ovfl_exit: + bclrb #E3,E_BYTE(%a6) |test and clear E3 bit + beqs e1_set +| +| Clear dirty bit on dest resister in the frame before branching +| to b1238_fix. +| + bfextu CMDREG3B(%a6){#6:#3},%d0 |get dest reg no + bclrb %d0,FPR_DIRTY_BITS(%a6) |clr dest dirty bit + bsrl b1238_fix |test for bug1238 case + + movel USER_FPSR(%a6),FPSR_SHADOW(%a6) + orl #sx_mask,E_BYTE(%a6) + moveml USER_DA(%a6),%d0-%d1/%a0-%a1 + fmovemx USER_FP0(%a6),%fp0-%fp3 + fmoveml USER_FPCR(%a6),%fpcr/%fpsr/%fpiar + frestore (%a7)+ + unlk %a6 + bral fpsp_done +e1_set: + moveml USER_DA(%a6),%d0-%d1/%a0-%a1 + fmovemx USER_FP0(%a6),%fp0-%fp3 + fmoveml USER_FPCR(%a6),%fpcr/%fpsr/%fpiar + unlk %a6 + bral fpsp_done + +| +| ovf_adj +| +ovf_adj: +| +| Have a0 point to the correct operand. +| + btstb #E3,E_BYTE(%a6) |test E3 bit + beqs ovf_e1 + + lea WBTEMP(%a6),%a0 + bras ovf_com +ovf_e1: + lea ETEMP(%a6),%a0 + +ovf_com: + bclrb #sign_bit,LOCAL_EX(%a0) + sne LOCAL_SGN(%a0) + + bsrl g_opcls |returns opclass in d0 + cmpiw #3,%d0 |check for opclass3 + bnes not_opc011 + +| +| FPSR_CC is saved and restored because ovf_r_x3 affects it. The +| CCs are defined to be 'not affected' for the opclass3 instruction. +| + moveb FPSR_CC(%a6),L_SCR1(%a6) + bsrl ovf_r_x3 |returns a0 pointing to result + moveb L_SCR1(%a6),FPSR_CC(%a6) + bral store |stores to memory or register + +not_opc011: + bsrl ovf_r_x2 |returns a0 pointing to result + bral store |stores to memory or register + + |end diff --git a/arch/m68k/fpsp040/x_snan.S b/arch/m68k/fpsp040/x_snan.S new file mode 100644 index 000000000..4ed766416 --- /dev/null +++ b/arch/m68k/fpsp040/x_snan.S @@ -0,0 +1,276 @@ +| +| x_snan.sa 3.3 7/1/91 +| +| fpsp_snan --- FPSP handler for signalling NAN exception +| +| SNAN for float -> integer conversions (integer conversion of +| an SNAN) is a non-maskable run-time exception. +| +| For trap disabled the 040 does the following: +| If the dest data format is s, d, or x, then the SNAN bit in the NAN +| is set to one and the resulting non-signaling NAN (truncated if +| necessary) is transferred to the dest. If the dest format is b, w, +| or l, then garbage is written to the dest (actually the upper 32 bits +| of the mantissa are sent to the integer unit). +| +| For trap enabled the 040 does the following: +| If the inst is move_out, then the results are the same as for trap +| disabled with the exception posted. If the instruction is not move_ +| out, the dest. is not modified, and the exception is posted. +| + +| Copyright (C) Motorola, Inc. 1990 +| All Rights Reserved +| +| For details on the license for this file, please see the +| file, README, in this same directory. + +X_SNAN: |idnt 2,1 | Motorola 040 Floating Point Software Package + + |section 8 + +#include "fpsp.h" + + |xref get_fline + |xref mem_write + |xref real_snan + |xref real_inex + |xref fpsp_done + |xref reg_dest + + .global fpsp_snan +fpsp_snan: + link %a6,#-LOCAL_SIZE + fsave -(%a7) + moveml %d0-%d1/%a0-%a1,USER_DA(%a6) + fmovemx %fp0-%fp3,USER_FP0(%a6) + fmoveml %fpcr/%fpsr/%fpiar,USER_FPCR(%a6) + +| +| Check if trap enabled +| + btstb #snan_bit,FPCR_ENABLE(%a6) + bnes ena |If enabled, then branch + + bsrl move_out |else SNAN disabled +| +| It is possible to have an inex1 exception with the +| snan. If the inex enable bit is set in the FPCR, and either +| inex2 or inex1 occurred, we must clean up and branch to the +| real inex handler. +| +ck_inex: + moveb FPCR_ENABLE(%a6),%d0 + andb FPSR_EXCEPT(%a6),%d0 + andib #0x3,%d0 + beq end_snan +| +| Inexact enabled and reported, and we must take an inexact exception. +| +take_inex: + moveb #INEX_VEC,EXC_VEC+1(%a6) + moveml USER_DA(%a6),%d0-%d1/%a0-%a1 + fmovemx USER_FP0(%a6),%fp0-%fp3 + fmoveml USER_FPCR(%a6),%fpcr/%fpsr/%fpiar + frestore (%a7)+ + unlk %a6 + bral real_inex +| +| SNAN is enabled. Check if inst is move_out. +| Make any corrections to the 040 output as necessary. +| +ena: + btstb #5,CMDREG1B(%a6) |if set, inst is move out + beq not_out + + bsrl move_out + +report_snan: + moveb (%a7),VER_TMP(%a6) + cmpib #VER_40,(%a7) |test for orig unimp frame + bnes ck_rev + moveql #13,%d0 |need to zero 14 lwords + bras rep_con +ck_rev: + moveql #11,%d0 |need to zero 12 lwords +rep_con: + clrl (%a7) +loop1: + clrl -(%a7) |clear and dec a7 + dbra %d0,loop1 + moveb VER_TMP(%a6),(%a7) |format a busy frame + moveb #BUSY_SIZE-4,1(%a7) + movel USER_FPSR(%a6),FPSR_SHADOW(%a6) + orl #sx_mask,E_BYTE(%a6) + moveml USER_DA(%a6),%d0-%d1/%a0-%a1 + fmovemx USER_FP0(%a6),%fp0-%fp3 + fmoveml USER_FPCR(%a6),%fpcr/%fpsr/%fpiar + frestore (%a7)+ + unlk %a6 + bral real_snan +| +| Exit snan handler by expanding the unimp frame into a busy frame +| +end_snan: + bclrb #E1,E_BYTE(%a6) + + moveb (%a7),VER_TMP(%a6) + cmpib #VER_40,(%a7) |test for orig unimp frame + bnes ck_rev2 + moveql #13,%d0 |need to zero 14 lwords + bras rep_con2 +ck_rev2: + moveql #11,%d0 |need to zero 12 lwords +rep_con2: + clrl (%a7) +loop2: + clrl -(%a7) |clear and dec a7 + dbra %d0,loop2 + moveb VER_TMP(%a6),(%a7) |format a busy frame + moveb #BUSY_SIZE-4,1(%a7) |write busy size + movel USER_FPSR(%a6),FPSR_SHADOW(%a6) + orl #sx_mask,E_BYTE(%a6) + moveml USER_DA(%a6),%d0-%d1/%a0-%a1 + fmovemx USER_FP0(%a6),%fp0-%fp3 + fmoveml USER_FPCR(%a6),%fpcr/%fpsr/%fpiar + frestore (%a7)+ + unlk %a6 + bral fpsp_done + +| +| Move_out +| +move_out: + movel EXC_EA(%a6),%a0 |get from exc frame + + bfextu CMDREG1B(%a6){#3:#3},%d0 |move rx field to d0{2:0} + cmpil #0,%d0 |check for long + beqs sto_long |branch if move_out long + + cmpil #4,%d0 |check for word + beqs sto_word |branch if move_out word + + cmpil #6,%d0 |check for byte + beqs sto_byte |branch if move_out byte + +| +| Not byte, word or long +| + rts +| +| Get the 32 most significant bits of etemp mantissa +| +sto_long: + movel ETEMP_HI(%a6),%d1 + movel #4,%d0 |load byte count +| +| Set signalling nan bit +| + bsetl #30,%d1 +| +| Store to the users destination address +| + tstl %a0 |check if is 0 + beqs wrt_dn |destination is a data register + + movel %d1,-(%a7) |move the snan onto the stack + movel %a0,%a1 |load dest addr into a1 + movel %a7,%a0 |load src addr of snan into a0 + bsrl mem_write |write snan to user memory + movel (%a7)+,%d1 |clear off stack + rts +| +| Get the 16 most significant bits of etemp mantissa +| +sto_word: + movel ETEMP_HI(%a6),%d1 + movel #2,%d0 |load byte count +| +| Set signalling nan bit +| + bsetl #30,%d1 +| +| Store to the users destination address +| + tstl %a0 |check if is 0 + beqs wrt_dn |destination is a data register + + movel %d1,-(%a7) |move the snan onto the stack + movel %a0,%a1 |load dest addr into a1 + movel %a7,%a0 |point to low word + bsrl mem_write |write snan to user memory + movel (%a7)+,%d1 |clear off stack + rts +| +| Get the 8 most significant bits of etemp mantissa +| +sto_byte: + movel ETEMP_HI(%a6),%d1 + movel #1,%d0 |load byte count +| +| Set signalling nan bit +| + bsetl #30,%d1 +| +| Store to the users destination address +| + tstl %a0 |check if is 0 + beqs wrt_dn |destination is a data register + movel %d1,-(%a7) |move the snan onto the stack + movel %a0,%a1 |load dest addr into a1 + movel %a7,%a0 |point to source byte + bsrl mem_write |write snan to user memory + movel (%a7)+,%d1 |clear off stack + rts + +| +| wrt_dn --- write to a data register +| +| We get here with D1 containing the data to write and D0 the +| number of bytes to write: 1=byte,2=word,4=long. +| +wrt_dn: + movel %d1,L_SCR1(%a6) |data + movel %d0,-(%a7) |size + bsrl get_fline |returns fline word in d0 + movel %d0,%d1 + andil #0x7,%d1 |d1 now holds register number + movel (%sp)+,%d0 |get original size + cmpil #4,%d0 + beqs wrt_long + cmpil #2,%d0 + bnes wrt_byte +wrt_word: + orl #0x8,%d1 + bral reg_dest +wrt_long: + orl #0x10,%d1 + bral reg_dest +wrt_byte: + bral reg_dest +| +| Check if it is a src nan or dst nan +| +not_out: + movel DTAG(%a6),%d0 + bfextu %d0{#0:#3},%d0 |isolate dtag in lsbs + + cmpib #3,%d0 |check for nan in destination + bnes issrc |destination nan has priority +dst_nan: + btstb #6,FPTEMP_HI(%a6) |check if dest nan is an snan + bnes issrc |no, so check source for snan + movew FPTEMP_EX(%a6),%d0 + bras cont +issrc: + movew ETEMP_EX(%a6),%d0 +cont: + btstl #15,%d0 |test for sign of snan + beqs clr_neg + bsetb #neg_bit,FPSR_CC(%a6) + bra report_snan +clr_neg: + bclrb #neg_bit,FPSR_CC(%a6) + bra report_snan + + |end diff --git a/arch/m68k/fpsp040/x_store.S b/arch/m68k/fpsp040/x_store.S new file mode 100644 index 000000000..402dc0c0e --- /dev/null +++ b/arch/m68k/fpsp040/x_store.S @@ -0,0 +1,255 @@ +| +| x_store.sa 3.2 1/24/91 +| +| store --- store operand to memory or register +| +| Used by underflow and overflow handlers. +| +| a6 = points to fp value to be stored. +| + +| Copyright (C) Motorola, Inc. 1990 +| All Rights Reserved +| +| For details on the license for this file, please see the +| file, README, in this same directory. + +X_STORE: |idnt 2,1 | Motorola 040 Floating Point Software Package + + |section 8 + +fpreg_mask: + .byte 0x80,0x40,0x20,0x10,0x08,0x04,0x02,0x01 + +#include "fpsp.h" + + |xref mem_write + |xref get_fline + |xref g_opcls + |xref g_dfmtou + |xref reg_dest + + .global dest_ext + .global dest_dbl + .global dest_sgl + + .global store +store: + btstb #E3,E_BYTE(%a6) + beqs E1_sto +E3_sto: + movel CMDREG3B(%a6),%d0 + bfextu %d0{#6:#3},%d0 |isolate dest. reg from cmdreg3b +sto_fp: + lea fpreg_mask,%a1 + moveb (%a1,%d0.w),%d0 |convert reg# to dynamic register mask + tstb LOCAL_SGN(%a0) + beqs is_pos + bsetb #sign_bit,LOCAL_EX(%a0) +is_pos: + fmovemx (%a0),%d0 |move to correct register +| +| if fp0-fp3 is being modified, we must put a copy +| in the USER_FPn variable on the stack because all exception +| handlers restore fp0-fp3 from there. +| + cmpb #0x80,%d0 + bnes not_fp0 + fmovemx %fp0-%fp0,USER_FP0(%a6) + rts +not_fp0: + cmpb #0x40,%d0 + bnes not_fp1 + fmovemx %fp1-%fp1,USER_FP1(%a6) + rts +not_fp1: + cmpb #0x20,%d0 + bnes not_fp2 + fmovemx %fp2-%fp2,USER_FP2(%a6) + rts +not_fp2: + cmpb #0x10,%d0 + bnes not_fp3 + fmovemx %fp3-%fp3,USER_FP3(%a6) + rts +not_fp3: + rts + +E1_sto: + bsrl g_opcls |returns opclass in d0 + cmpib #3,%d0 + beq opc011 |branch if opclass 3 + movel CMDREG1B(%a6),%d0 + bfextu %d0{#6:#3},%d0 |extract destination register + bras sto_fp + +opc011: + bsrl g_dfmtou |returns dest format in d0 +| ;ext=00, sgl=01, dbl=10 + movel %a0,%a1 |save source addr in a1 + movel EXC_EA(%a6),%a0 |get the address + cmpil #0,%d0 |if dest format is extended + beq dest_ext |then branch + cmpil #1,%d0 |if dest format is single + beq dest_sgl |then branch +| +| fall through to dest_dbl +| + +| +| dest_dbl --- write double precision value to user space +| +|Input +| a0 -> destination address +| a1 -> source in extended precision +|Output +| a0 -> destroyed +| a1 -> destroyed +| d0 -> 0 +| +|Changes extended precision to double precision. +| Note: no attempt is made to round the extended value to double. +| dbl_sign = ext_sign +| dbl_exp = ext_exp - $3fff(ext bias) + $7ff(dbl bias) +| get rid of ext integer bit +| dbl_mant = ext_mant{62:12} +| +| --------------- --------------- --------------- +| extended -> |s| exp | |1| ms mant | | ls mant | +| --------------- --------------- --------------- +| 95 64 63 62 32 31 11 0 +| | | +| | | +| | | +| v v +| --------------- --------------- +| double -> |s|exp| mant | | mant | +| --------------- --------------- +| 63 51 32 31 0 +| +dest_dbl: + clrl %d0 |clear d0 + movew LOCAL_EX(%a1),%d0 |get exponent + subw #0x3fff,%d0 |subtract extended precision bias + cmpw #0x4000,%d0 |check if inf + beqs inf |if so, special case + addw #0x3ff,%d0 |add double precision bias + swap %d0 |d0 now in upper word + lsll #4,%d0 |d0 now in proper place for dbl prec exp + tstb LOCAL_SGN(%a1) + beqs get_mant |if positive, go process mantissa + bsetl #31,%d0 |if negative, put in sign information +| ; before continuing + bras get_mant |go process mantissa +inf: + movel #0x7ff00000,%d0 |load dbl inf exponent + clrl LOCAL_HI(%a1) |clear msb + tstb LOCAL_SGN(%a1) + beqs dbl_inf |if positive, go ahead and write it + bsetl #31,%d0 |if negative put in sign information +dbl_inf: + movel %d0,LOCAL_EX(%a1) |put the new exp back on the stack + bras dbl_wrt +get_mant: + movel LOCAL_HI(%a1),%d1 |get ms mantissa + bfextu %d1{#1:#20},%d1 |get upper 20 bits of ms + orl %d1,%d0 |put these bits in ms word of double + movel %d0,LOCAL_EX(%a1) |put the new exp back on the stack + movel LOCAL_HI(%a1),%d1 |get ms mantissa + movel #21,%d0 |load shift count + lsll %d0,%d1 |put lower 11 bits in upper bits + movel %d1,LOCAL_HI(%a1) |build lower lword in memory + movel LOCAL_LO(%a1),%d1 |get ls mantissa + bfextu %d1{#0:#21},%d0 |get ls 21 bits of double + orl %d0,LOCAL_HI(%a1) |put them in double result +dbl_wrt: + movel #0x8,%d0 |byte count for double precision number + exg %a0,%a1 |a0=supervisor source, a1=user dest + bsrl mem_write |move the number to the user's memory + rts +| +| dest_sgl --- write single precision value to user space +| +|Input +| a0 -> destination address +| a1 -> source in extended precision +| +|Output +| a0 -> destroyed +| a1 -> destroyed +| d0 -> 0 +| +|Changes extended precision to single precision. +| sgl_sign = ext_sign +| sgl_exp = ext_exp - $3fff(ext bias) + $7f(sgl bias) +| get rid of ext integer bit +| sgl_mant = ext_mant{62:12} +| +| --------------- --------------- --------------- +| extended -> |s| exp | |1| ms mant | | ls mant | +| --------------- --------------- --------------- +| 95 64 63 62 40 32 31 12 0 +| | | +| | | +| | | +| v v +| --------------- +| single -> |s|exp| mant | +| --------------- +| 31 22 0 +| +dest_sgl: + clrl %d0 + movew LOCAL_EX(%a1),%d0 |get exponent + subw #0x3fff,%d0 |subtract extended precision bias + cmpw #0x4000,%d0 |check if inf + beqs sinf |if so, special case + addw #0x7f,%d0 |add single precision bias + swap %d0 |put exp in upper word of d0 + lsll #7,%d0 |shift it into single exp bits + tstb LOCAL_SGN(%a1) + beqs get_sman |if positive, continue + bsetl #31,%d0 |if negative, put in sign first + bras get_sman |get mantissa +sinf: + movel #0x7f800000,%d0 |load single inf exp to d0 + tstb LOCAL_SGN(%a1) + beqs sgl_wrt |if positive, continue + bsetl #31,%d0 |if negative, put in sign info + bras sgl_wrt + +get_sman: + movel LOCAL_HI(%a1),%d1 |get ms mantissa + bfextu %d1{#1:#23},%d1 |get upper 23 bits of ms + orl %d1,%d0 |put these bits in ms word of single + +sgl_wrt: + movel %d0,L_SCR1(%a6) |put the new exp back on the stack + movel #0x4,%d0 |byte count for single precision number + tstl %a0 |users destination address + beqs sgl_Dn |destination is a data register + exg %a0,%a1 |a0=supervisor source, a1=user dest + leal L_SCR1(%a6),%a0 |point a0 to data + bsrl mem_write |move the number to the user's memory + rts +sgl_Dn: + bsrl get_fline |returns fline word in d0 + andw #0x7,%d0 |isolate register number + movel %d0,%d1 |d1 has size:reg formatted for reg_dest + orl #0x10,%d1 |reg_dest wants size added to reg# + bral reg_dest |size is X, rts in reg_dest will +| ;return to caller of dest_sgl + +dest_ext: + tstb LOCAL_SGN(%a1) |put back sign into exponent word + beqs dstx_cont + bsetb #sign_bit,LOCAL_EX(%a1) +dstx_cont: + clrb LOCAL_SGN(%a1) |clear out the sign byte + + movel #0x0c,%d0 |byte count for extended number + exg %a0,%a1 |a0=supervisor source, a1=user dest + bsrl mem_write |move the number to the user's memory + rts + + |end diff --git a/arch/m68k/fpsp040/x_unfl.S b/arch/m68k/fpsp040/x_unfl.S new file mode 100644 index 000000000..eb772ff3b --- /dev/null +++ b/arch/m68k/fpsp040/x_unfl.S @@ -0,0 +1,268 @@ +| +| x_unfl.sa 3.4 7/1/91 +| +| fpsp_unfl --- FPSP handler for underflow exception +| +| Trap disabled results +| For 881/2 compatibility, sw must denormalize the intermediate +| result, then store the result. Denormalization is accomplished +| by taking the intermediate result (which is always normalized) and +| shifting the mantissa right while incrementing the exponent until +| it is equal to the denormalized exponent for the destination +| format. After denormalization, the result is rounded to the +| destination format. +| +| Trap enabled results +| All trap disabled code applies. In addition the exceptional +| operand needs to made available to the user with a bias of $6000 +| added to the exponent. +| + +| Copyright (C) Motorola, Inc. 1990 +| All Rights Reserved +| +| For details on the license for this file, please see the +| file, README, in this same directory. + +X_UNFL: |idnt 2,1 | Motorola 040 Floating Point Software Package + + |section 8 + +#include "fpsp.h" + + |xref denorm + |xref round + |xref store + |xref g_rndpr + |xref g_opcls + |xref g_dfmtou + |xref real_unfl + |xref real_inex + |xref fpsp_done + |xref b1238_fix + + .global fpsp_unfl +fpsp_unfl: + link %a6,#-LOCAL_SIZE + fsave -(%a7) + moveml %d0-%d1/%a0-%a1,USER_DA(%a6) + fmovemx %fp0-%fp3,USER_FP0(%a6) + fmoveml %fpcr/%fpsr/%fpiar,USER_FPCR(%a6) + +| + bsrl unf_res |denormalize, round & store interm op +| +| If underflow exceptions are not enabled, check for inexact +| exception +| + btstb #unfl_bit,FPCR_ENABLE(%a6) + beqs ck_inex + + btstb #E3,E_BYTE(%a6) + beqs no_e3_1 +| +| Clear dirty bit on dest resister in the frame before branching +| to b1238_fix. +| + bfextu CMDREG3B(%a6){#6:#3},%d0 |get dest reg no + bclrb %d0,FPR_DIRTY_BITS(%a6) |clr dest dirty bit + bsrl b1238_fix |test for bug1238 case + movel USER_FPSR(%a6),FPSR_SHADOW(%a6) + orl #sx_mask,E_BYTE(%a6) +no_e3_1: + moveml USER_DA(%a6),%d0-%d1/%a0-%a1 + fmovemx USER_FP0(%a6),%fp0-%fp3 + fmoveml USER_FPCR(%a6),%fpcr/%fpsr/%fpiar + frestore (%a7)+ + unlk %a6 + bral real_unfl +| +| It is possible to have either inex2 or inex1 exceptions with the +| unfl. If the inex enable bit is set in the FPCR, and either +| inex2 or inex1 occurred, we must clean up and branch to the +| real inex handler. +| +ck_inex: + moveb FPCR_ENABLE(%a6),%d0 + andb FPSR_EXCEPT(%a6),%d0 + andib #0x3,%d0 + beqs unfl_done + +| +| Inexact enabled and reported, and we must take an inexact exception +| +take_inex: + btstb #E3,E_BYTE(%a6) + beqs no_e3_2 +| +| Clear dirty bit on dest resister in the frame before branching +| to b1238_fix. +| + bfextu CMDREG3B(%a6){#6:#3},%d0 |get dest reg no + bclrb %d0,FPR_DIRTY_BITS(%a6) |clr dest dirty bit + bsrl b1238_fix |test for bug1238 case + movel USER_FPSR(%a6),FPSR_SHADOW(%a6) + orl #sx_mask,E_BYTE(%a6) +no_e3_2: + moveb #INEX_VEC,EXC_VEC+1(%a6) + moveml USER_DA(%a6),%d0-%d1/%a0-%a1 + fmovemx USER_FP0(%a6),%fp0-%fp3 + fmoveml USER_FPCR(%a6),%fpcr/%fpsr/%fpiar + frestore (%a7)+ + unlk %a6 + bral real_inex + +unfl_done: + bclrb #E3,E_BYTE(%a6) + beqs e1_set |if set then branch +| +| Clear dirty bit on dest resister in the frame before branching +| to b1238_fix. +| + bfextu CMDREG3B(%a6){#6:#3},%d0 |get dest reg no + bclrb %d0,FPR_DIRTY_BITS(%a6) |clr dest dirty bit + bsrl b1238_fix |test for bug1238 case + movel USER_FPSR(%a6),FPSR_SHADOW(%a6) + orl #sx_mask,E_BYTE(%a6) + moveml USER_DA(%a6),%d0-%d1/%a0-%a1 + fmovemx USER_FP0(%a6),%fp0-%fp3 + fmoveml USER_FPCR(%a6),%fpcr/%fpsr/%fpiar + frestore (%a7)+ + unlk %a6 + bral fpsp_done +e1_set: + moveml USER_DA(%a6),%d0-%d1/%a0-%a1 + fmovemx USER_FP0(%a6),%fp0-%fp3 + fmoveml USER_FPCR(%a6),%fpcr/%fpsr/%fpiar + unlk %a6 + bral fpsp_done +| +| unf_res --- underflow result calculation +| +unf_res: + bsrl g_rndpr |returns RND_PREC in d0 0=ext, +| ;1=sgl, 2=dbl +| ;we need the RND_PREC in the +| ;upper word for round + movew #0,-(%a7) + movew %d0,-(%a7) |copy RND_PREC to stack +| +| +| If the exception bit set is E3, the exceptional operand from the +| fpu is in WBTEMP; else it is in FPTEMP. +| + btstb #E3,E_BYTE(%a6) + beqs unf_E1 +unf_E3: + lea WBTEMP(%a6),%a0 |a0 now points to operand +| +| Test for fsgldiv and fsglmul. If the inst was one of these, then +| force the precision to extended for the denorm routine. Use +| the user's precision for the round routine. +| + movew CMDREG3B(%a6),%d1 |check for fsgldiv or fsglmul + andiw #0x7f,%d1 + cmpiw #0x30,%d1 |check for sgldiv + beqs unf_sgl + cmpiw #0x33,%d1 |check for sglmul + bnes unf_cont |if not, use fpcr prec in round +unf_sgl: + clrl %d0 + movew #0x1,(%a7) |override g_rndpr precision +| ;force single + bras unf_cont +unf_E1: + lea FPTEMP(%a6),%a0 |a0 now points to operand +unf_cont: + bclrb #sign_bit,LOCAL_EX(%a0) |clear sign bit + sne LOCAL_SGN(%a0) |store sign + + bsrl denorm |returns denorm, a0 points to it +| +| WARNING: +| ;d0 has guard,round sticky bit +| ;make sure that it is not corrupted +| ;before it reaches the round subroutine +| ;also ensure that a0 isn't corrupted + +| +| Set up d1 for round subroutine d1 contains the PREC/MODE +| information respectively on upper/lower register halves. +| + bfextu FPCR_MODE(%a6){#2:#2},%d1 |get mode from FPCR +| ;mode in lower d1 + addl (%a7)+,%d1 |merge PREC/MODE +| +| WARNING: a0 and d0 are assumed to be intact between the denorm and +| round subroutines. All code between these two subroutines +| must not corrupt a0 and d0. +| +| +| Perform Round +| Input: a0 points to input operand +| d0{31:29} has guard, round, sticky +| d1{01:00} has rounding mode +| d1{17:16} has rounding precision +| Output: a0 points to rounded operand +| + + bsrl round |returns rounded denorm at (a0) +| +| Differentiate between store to memory vs. store to register +| +unf_store: + bsrl g_opcls |returns opclass in d0{2:0} + cmpib #0x3,%d0 + bnes not_opc011 +| +| At this point, a store to memory is pending +| +opc011: + bsrl g_dfmtou + tstb %d0 + beqs ext_opc011 |If extended, do not subtract +| ;If destination format is sgl/dbl, + tstb LOCAL_HI(%a0) |If rounded result is normal,don't +| ;subtract + bmis ext_opc011 + subqw #1,LOCAL_EX(%a0) |account for denorm bias vs. +| ;normalized bias +| ; normalized denormalized +| ;single $7f $7e +| ;double $3ff $3fe +| +ext_opc011: + bsrl store |stores to memory + bras unf_done |finish up + +| +| At this point, a store to a float register is pending +| +not_opc011: + bsrl store |stores to float register +| ;a0 is not corrupted on a store to a +| ;float register. +| +| Set the condition codes according to result +| + tstl LOCAL_HI(%a0) |check upper mantissa + bnes ck_sgn + tstl LOCAL_LO(%a0) |check lower mantissa + bnes ck_sgn + bsetb #z_bit,FPSR_CC(%a6) |set condition codes if zero +ck_sgn: + btstb #sign_bit,LOCAL_EX(%a0) |check the sign bit + beqs unf_done + bsetb #neg_bit,FPSR_CC(%a6) + +| +| Finish. +| +unf_done: + btstb #inex2_bit,FPSR_EXCEPT(%a6) + beqs no_aunfl + bsetb #aunfl_bit,FPSR_AEXCEPT(%a6) +no_aunfl: + rts + + |end diff --git a/arch/m68k/fpsp040/x_unimp.S b/arch/m68k/fpsp040/x_unimp.S new file mode 100644 index 000000000..6f382b212 --- /dev/null +++ b/arch/m68k/fpsp040/x_unimp.S @@ -0,0 +1,76 @@ +| +| x_unimp.sa 3.3 7/1/91 +| +| fpsp_unimp --- FPSP handler for unimplemented instruction +| exception. +| +| Invoked when the user program encounters a floating-point +| op-code that hardware does not support. Trap vector# 11 +| (See table 8-1 MC68030 User's Manual). +| +| +| Note: An fsave for an unimplemented inst. will create a short +| fsave stack. +| +| Input: 1. Six word stack frame for unimplemented inst, four word +| for illegal +| (See table 8-7 MC68030 User's Manual). +| 2. Unimp (short) fsave state frame created here by fsave +| instruction. +| +| +| Copyright (C) Motorola, Inc. 1990 +| All Rights Reserved +| +| For details on the license for this file, please see the +| file, README, in this same directory. + +X_UNIMP: |idnt 2,1 | Motorola 040 Floating Point Software Package + + |section 8 + +#include "fpsp.h" + + |xref get_op + |xref do_func + |xref sto_res + |xref gen_except + |xref fpsp_fmt_error + + .global fpsp_unimp + .global uni_2 +fpsp_unimp: + link %a6,#-LOCAL_SIZE + fsave -(%a7) +uni_2: + moveml %d0-%d1/%a0-%a1,USER_DA(%a6) + fmovemx %fp0-%fp3,USER_FP0(%a6) + fmoveml %fpcr/%fpsr/%fpiar,USER_FPCR(%a6) + moveb (%a7),%d0 |test for valid version num + andib #0xf0,%d0 |test for $4x + cmpib #VER_4,%d0 |must be $4x or exit + bnel fpsp_fmt_error +| +| Temporary D25B Fix +| The following lines are used to ensure that the FPSR +| exception byte and condition codes are clear before proceeding +| + movel USER_FPSR(%a6),%d0 + andl #0xFF00FF,%d0 |clear all but accrued exceptions + movel %d0,USER_FPSR(%a6) + fmovel #0,%FPSR |clear all user bits + fmovel #0,%FPCR |clear all user exceptions for FPSP + + clrb UFLG_TMP(%a6) |clr flag for unsupp data + + bsrl get_op |go get operand(s) + clrb STORE_FLG(%a6) + bsrl do_func |do the function + fsave -(%a7) |capture possible exc state + tstb STORE_FLG(%a6) + bnes no_store |if STORE_FLG is set, no store + bsrl sto_res |store the result in user space +no_store: + bral gen_except |post any exceptions and return + + |end diff --git a/arch/m68k/fpsp040/x_unsupp.S b/arch/m68k/fpsp040/x_unsupp.S new file mode 100644 index 000000000..d7cf46208 --- /dev/null +++ b/arch/m68k/fpsp040/x_unsupp.S @@ -0,0 +1,82 @@ +| +| x_unsupp.sa 3.3 7/1/91 +| +| fpsp_unsupp --- FPSP handler for unsupported data type exception +| +| Trap vector #55 (See table 8-1 Mc68030 User's manual). +| Invoked when the user program encounters a data format (packed) that +| hardware does not support or a data type (denormalized numbers or un- +| normalized numbers). +| Normalizes denorms and unnorms, unpacks packed numbers then stores +| them back into the machine to let the 040 finish the operation. +| +| Unsupp calls two routines: +| 1. get_op - gets the operand(s) +| 2. res_func - restore the function back into the 040 or +| if fmove.p fpm, then pack source (fpm) +| and store in users memory . +| +| Input: Long fsave stack frame +| +| + +| Copyright (C) Motorola, Inc. 1990 +| All Rights Reserved +| +| For details on the license for this file, please see the +| file, README, in this same directory. + +X_UNSUPP: |idnt 2,1 | Motorola 040 Floating Point Software Package + + |section 8 + +#include "fpsp.h" + + |xref get_op + |xref res_func + |xref gen_except + |xref fpsp_fmt_error + + .global fpsp_unsupp +fpsp_unsupp: +| + link %a6,#-LOCAL_SIZE + fsave -(%a7) + moveml %d0-%d1/%a0-%a1,USER_DA(%a6) + fmovemx %fp0-%fp3,USER_FP0(%a6) + fmoveml %fpcr/%fpsr/%fpiar,USER_FPCR(%a6) + + + moveb (%a7),VER_TMP(%a6) |save version number + moveb (%a7),%d0 |test for valid version num + andib #0xf0,%d0 |test for $4x + cmpib #VER_4,%d0 |must be $4x or exit + bnel fpsp_fmt_error + + fmovel #0,%FPSR |clear all user status bits + fmovel #0,%FPCR |clear all user control bits +| +| The following lines are used to ensure that the FPSR +| exception byte and condition codes are clear before proceeding, +| except in the case of fmove, which leaves the cc's intact. +| +unsupp_con: + movel USER_FPSR(%a6),%d1 + btst #5,CMDREG1B(%a6) |looking for fmove out + bne fmove_con + andl #0xFF00FF,%d1 |clear all but aexcs and qbyte + bras end_fix +fmove_con: + andl #0x0FFF40FF,%d1 |clear all but cc's, snan bit, aexcs, and qbyte +end_fix: + movel %d1,USER_FPSR(%a6) + + st UFLG_TMP(%a6) |set flag for unsupp data + + bsrl get_op |everything okay, go get operand(s) + bsrl res_func |fix up stack frame so can restore it + clrl -(%a7) + moveb VER_TMP(%a6),(%a7) |move idle fmt word to top of stack + bral gen_except +| + |end diff --git a/arch/m68k/hp300/Makefile b/arch/m68k/hp300/Makefile new file mode 100644 index 000000000..d87376156 --- /dev/null +++ b/arch/m68k/hp300/Makefile @@ -0,0 +1,6 @@ +# SPDX-License-Identifier: GPL-2.0-only +# +# Makefile for Linux arch/m68k/hp300 source directory +# + +obj-y := config.o time.o reboot.o diff --git a/arch/m68k/hp300/README.hp300 b/arch/m68k/hp300/README.hp300 new file mode 100644 index 000000000..47073fbd4 --- /dev/null +++ b/arch/m68k/hp300/README.hp300 @@ -0,0 +1,14 @@ +HP300 notes +----------- + +The Linux/HP web page is at + +Currently only 9000/340 machines have been tested. Any amount of RAM should +work now but I've only tried 16MB and 12MB. + +The serial console is probably broken at the moment but the Topcat/HIL keyboard +combination seems to work for me. Your mileage may vary. + +The LANCE driver works after a fashion but only if you reset the chip before +every packet. This doesn't make for very speedy operation. + diff --git a/arch/m68k/hp300/config.c b/arch/m68k/hp300/config.c new file mode 100644 index 000000000..a161d44fd --- /dev/null +++ b/arch/m68k/hp300/config.c @@ -0,0 +1,276 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * linux/arch/m68k/hp300/config.c + * + * Copyright (C) 1998 Philip Blundell + * + * This file contains the HP300-specific initialisation code. It gets + * called by setup.c. + */ + +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include /* readb() and writeb() */ +#include + +#include "time.h" + +unsigned long hp300_model; +unsigned long hp300_uart_scode = -1; +unsigned char hp300_ledstate; +EXPORT_SYMBOL(hp300_ledstate); + +static char s_hp330[] __initdata = "330"; +static char s_hp340[] __initdata = "340"; +static char s_hp345[] __initdata = "345"; +static char s_hp360[] __initdata = "360"; +static char s_hp370[] __initdata = "370"; +static char s_hp375[] __initdata = "375"; +static char s_hp380[] __initdata = "380"; +static char s_hp385[] __initdata = "385"; +static char s_hp400[] __initdata = "400"; +static char s_hp425t[] __initdata = "425t"; +static char s_hp425s[] __initdata = "425s"; +static char s_hp425e[] __initdata = "425e"; +static char s_hp433t[] __initdata = "433t"; +static char s_hp433s[] __initdata = "433s"; +static char *hp300_models[] __initdata = { + [HP_320] = NULL, + [HP_330] = s_hp330, + [HP_340] = s_hp340, + [HP_345] = s_hp345, + [HP_350] = NULL, + [HP_360] = s_hp360, + [HP_370] = s_hp370, + [HP_375] = s_hp375, + [HP_380] = s_hp380, + [HP_385] = s_hp385, + [HP_400] = s_hp400, + [HP_425T] = s_hp425t, + [HP_425S] = s_hp425s, + [HP_425E] = s_hp425e, + [HP_433T] = s_hp433t, + [HP_433S] = s_hp433s, +}; + +static char hp300_model_name[13] = "HP9000/"; + +extern void hp300_reset(void); +#ifdef CONFIG_SERIAL_8250_CONSOLE +extern int hp300_setup_serial_console(void) __init; +#endif + +int __init hp300_parse_bootinfo(const struct bi_record *record) +{ + int unknown = 0; + const void *data = record->data; + + switch (be16_to_cpu(record->tag)) { + case BI_HP300_MODEL: + hp300_model = be32_to_cpup(data); + break; + + case BI_HP300_UART_SCODE: + hp300_uart_scode = be32_to_cpup(data); + break; + + case BI_HP300_UART_ADDR: + /* serial port address: ignored here */ + break; + + default: + unknown = 1; + } + + return unknown; +} + +#ifdef CONFIG_HEARTBEAT +static void hp300_pulse(int x) +{ + if (x) + blinken_leds(0x10, 0); + else + blinken_leds(0, 0x10); +} +#endif + +static void hp300_get_model(char *model) +{ + strcpy(model, hp300_model_name); +} + +#define RTCBASE 0xf0420000 +#define RTC_DATA 0x1 +#define RTC_CMD 0x3 + +#define RTC_BUSY 0x02 +#define RTC_DATA_RDY 0x01 + +#define rtc_busy() (in_8(RTCBASE + RTC_CMD) & RTC_BUSY) +#define rtc_data_available() (in_8(RTCBASE + RTC_CMD) & RTC_DATA_RDY) +#define rtc_status() (in_8(RTCBASE + RTC_CMD)) +#define rtc_command(x) out_8(RTCBASE + RTC_CMD, (x)) +#define rtc_read_data() (in_8(RTCBASE + RTC_DATA)) +#define rtc_write_data(x) out_8(RTCBASE + RTC_DATA, (x)) + +#define RTC_SETREG 0xe0 +#define RTC_WRITEREG 0xc2 +#define RTC_READREG 0xc3 + +#define RTC_REG_SEC2 0 +#define RTC_REG_SEC1 1 +#define RTC_REG_MIN2 2 +#define RTC_REG_MIN1 3 +#define RTC_REG_HOUR2 4 +#define RTC_REG_HOUR1 5 +#define RTC_REG_WDAY 6 +#define RTC_REG_DAY2 7 +#define RTC_REG_DAY1 8 +#define RTC_REG_MON2 9 +#define RTC_REG_MON1 10 +#define RTC_REG_YEAR2 11 +#define RTC_REG_YEAR1 12 + +#define RTC_HOUR1_24HMODE 0x8 + +#define RTC_STAT_MASK 0xf0 +#define RTC_STAT_RDY 0x40 + +static inline unsigned char hp300_rtc_read(unsigned char reg) +{ + unsigned char s, ret; + unsigned long flags; + + local_irq_save(flags); + + while (rtc_busy()); + rtc_command(RTC_SETREG); + while (rtc_busy()); + rtc_write_data(reg); + while (rtc_busy()); + rtc_command(RTC_READREG); + + do { + while (!rtc_data_available()); + s = rtc_status(); + ret = rtc_read_data(); + } while ((s & RTC_STAT_MASK) != RTC_STAT_RDY); + + local_irq_restore(flags); + + return ret; +} + +static inline unsigned char hp300_rtc_write(unsigned char reg, + unsigned char val) +{ + unsigned char s, ret; + unsigned long flags; + + local_irq_save(flags); + + while (rtc_busy()); + rtc_command(RTC_SETREG); + while (rtc_busy()); + rtc_write_data((val << 4) | reg); + while (rtc_busy()); + rtc_command(RTC_WRITEREG); + while (rtc_busy()); + rtc_command(RTC_READREG); + + do { + while (!rtc_data_available()); + s = rtc_status(); + ret = rtc_read_data(); + } while ((s & RTC_STAT_MASK) != RTC_STAT_RDY); + + local_irq_restore(flags); + + return ret; +} + +static int hp300_hwclk(int op, struct rtc_time *t) +{ + if (!op) { /* read */ + t->tm_sec = hp300_rtc_read(RTC_REG_SEC1) * 10 + + hp300_rtc_read(RTC_REG_SEC2); + t->tm_min = hp300_rtc_read(RTC_REG_MIN1) * 10 + + hp300_rtc_read(RTC_REG_MIN2); + t->tm_hour = (hp300_rtc_read(RTC_REG_HOUR1) & 3) * 10 + + hp300_rtc_read(RTC_REG_HOUR2); + t->tm_wday = -1; + t->tm_mday = hp300_rtc_read(RTC_REG_DAY1) * 10 + + hp300_rtc_read(RTC_REG_DAY2); + t->tm_mon = hp300_rtc_read(RTC_REG_MON1) * 10 + + hp300_rtc_read(RTC_REG_MON2) - 1; + t->tm_year = hp300_rtc_read(RTC_REG_YEAR1) * 10 + + hp300_rtc_read(RTC_REG_YEAR2); + if (t->tm_year <= 69) + t->tm_year += 100; + } else { + hp300_rtc_write(RTC_REG_SEC1, t->tm_sec / 10); + hp300_rtc_write(RTC_REG_SEC2, t->tm_sec % 10); + hp300_rtc_write(RTC_REG_MIN1, t->tm_min / 10); + hp300_rtc_write(RTC_REG_MIN2, t->tm_min % 10); + hp300_rtc_write(RTC_REG_HOUR1, + ((t->tm_hour / 10) & 3) | RTC_HOUR1_24HMODE); + hp300_rtc_write(RTC_REG_HOUR2, t->tm_hour % 10); + hp300_rtc_write(RTC_REG_DAY1, t->tm_mday / 10); + hp300_rtc_write(RTC_REG_DAY2, t->tm_mday % 10); + hp300_rtc_write(RTC_REG_MON1, (t->tm_mon + 1) / 10); + hp300_rtc_write(RTC_REG_MON2, (t->tm_mon + 1) % 10); + if (t->tm_year >= 100) + t->tm_year -= 100; + hp300_rtc_write(RTC_REG_YEAR1, t->tm_year / 10); + hp300_rtc_write(RTC_REG_YEAR2, t->tm_year % 10); + } + + return 0; +} + +static unsigned int hp300_get_ss(void) +{ + return hp300_rtc_read(RTC_REG_SEC1) * 10 + + hp300_rtc_read(RTC_REG_SEC2); +} + +static void __init hp300_init_IRQ(void) +{ +} + +void __init config_hp300(void) +{ + mach_sched_init = hp300_sched_init; + mach_init_IRQ = hp300_init_IRQ; + mach_get_model = hp300_get_model; + mach_hwclk = hp300_hwclk; + mach_get_ss = hp300_get_ss; + mach_reset = hp300_reset; +#ifdef CONFIG_HEARTBEAT + mach_heartbeat = hp300_pulse; +#endif + mach_max_dma_address = 0xffffffff; + + if (hp300_model >= HP_330 && hp300_model <= HP_433S && + hp300_model != HP_350) { + pr_info("Detected HP9000 model %s\n", + hp300_models[hp300_model-HP_320]); + strcat(hp300_model_name, hp300_models[hp300_model-HP_320]); + } else { + panic("Unknown HP9000 Model"); + } +#ifdef CONFIG_SERIAL_8250_CONSOLE + hp300_setup_serial_console(); +#endif +} diff --git a/arch/m68k/hp300/hp300map.map b/arch/m68k/hp300/hp300map.map new file mode 100644 index 000000000..6b45f0abc --- /dev/null +++ b/arch/m68k/hp300/hp300map.map @@ -0,0 +1,252 @@ +# HP300 kernel keymap. This uses 7 modifier combinations. +keymaps 0-2,4-5,8,12 +# Change the above line into +# keymaps 0-2,4-6,8,12 +# in case you want the entries +# altgr control keycode 83 = Boot +# altgr control keycode 111 = Boot +# below. +# +# In fact AltGr is used very little, and one more keymap can +# be saved by mapping AltGr to Alt (and adapting a few entries): +# keycode 100 = Alt +# +keycode 1 = +keycode 2 = Alt +keycode 3 = Alt +keycode 4 = Shift +keycode 5 = Shift +keycode 6 = Control +keycode 7 = +keycode 8 = +keycode 9 = +keycode 10 = +keycode 11 = +keycode 12 = +keycode 13 = +keycode 14 = +keycode 15 = +keycode 16 = +keycode 17 = +keycode 18 = +keycode 19 = +keycode 20 = +keycode 21 = +keycode 22 = +keycode 23 = +keycode 24 = b +keycode 25 = v +keycode 26 = c +keycode 27 = x +keycode 28 = z +keycode 29 = +keycode 30 = +keycode 31 = Escape Delete +keycode 32 = +keycode 33 = +keycode 34 = +keycode 35 = +keycode 36 = +keycode 37 = +keycode 38 = +keycode 39 = +keycode 40 = h +keycode 41 = g +keycode 42 = f +keycode 43 = d +keycode 44 = s +keycode 45 = a +keycode 46 = +keycode 47 = Caps_Lock +keycode 48 = u +keycode 49 = y +keycode 50 = t +keycode 51 = r +keycode 52 = e +keycode 53 = w +keycode 54 = q +keycode 55 = Tab Tab + alt keycode 55 = Meta_Tab +keycode 56 = seven ampersand +keycode 57 = six asciicircum +keycode 58 = five percent +keycode 59 = four dollar +keycode 60 = three numbersign +keycode 61 = two at at +keycode 62 = one exclam exclam +keycode 63 = grave asciitilde + control keycode 63 = nul + alt keycode 63 = Meta_grave +keycode 64 = +keycode 65 = +keycode 66 = +keycode 67 = +keycode 68 = +keycode 69 = +keycode 70 = +keycode 71 = +keycode 72 = +keycode 73 = F4 + control keycode 73 = Console_4 +keycode 74 = F3 + control keycode 74 = Console_3 +keycode 75 = F2 + control keycode 75 = Console_2 +keycode 76 = F1 + control keycode 76 = Console_1 +keycode 77 = +keycode 78 = +keycode 79 = +keycode 80 = +keycode 81 = F5 + control keycode 81 = Console_5 +keycode 82 = F6 + control keycode 82 = Console_6 +keycode 83 = F7 + control keycode 83 = Console_7 +keycode 84 = F8 + control keycode 84 = Console_8 +keycode 85 = +keycode 86 = +keycode 87 = +keycode 88 = eight asterisk asterisk +keycode 89 = nine parenleft bracketleft +keycode 90 = zero parenright bracketright +keycode 91 = minus underscore +keycode 92 = equal plus +keycode 93 = BackSpace +keycode 94 = +keycode 95 = +keycode 96 = i +keycode 97 = o +keycode 98 = p +keycode 99 = bracketleft braceleft +keycode 100 = bracketright braceright +keycode 101 = backslash bar + control keycode 101 = Control_backslash + alt keycode 101 = Meta_backslash +keycode 102 = +keycode 103 = +keycode 104 = j +keycode 105 = k +keycode 106 = l +keycode 107 = semicolon colon + alt keycode 107 = Meta_semicolon +keycode 108 = apostrophe quotedbl + control keycode 108 = Control_g + alt keycode 108 = Meta_apostrophe +keycode 109 = Return +keycode 110 = +keycode 111 = +keycode 112 = m +keycode 113 = comma less +keycode 114 = period greater +keycode 115 = slash question +keycode 116 = +keycode 117 = +keycode 118 = +keycode 119 = +keycode 120 = n +keycode 121 = space space +keycode 122 = +keycode 123 = +keycode 124 = Left +keycode 125 = Down +keycode 126 = Up +keycode 127 = Right +string F1 = "\033[[A" +string F2 = "\033[[B" +string F3 = "\033[[C" +string F4 = "\033[[D" +string F5 = "\033[[E" +string F6 = "\033[17~" +string F7 = "\033[18~" +string F8 = "\033[19~" +string F9 = "\033[20~" +string F10 = "\033[21~" +string F11 = "\033[23~" +string F12 = "\033[24~" +string F13 = "\033[25~" +string F14 = "\033[26~" +string F15 = "\033[28~" +string F16 = "\033[29~" +string F17 = "\033[31~" +string F18 = "\033[32~" +string F19 = "\033[33~" +string F20 = "\033[34~" +string Find = "\033[1~" +string Insert = "\033[2~" +string Remove = "\033[3~" +string Select = "\033[4~" +string Prior = "\033[5~" +string Next = "\033[6~" +string Macro = "\033[M" +string Pause = "\033[P" +compose '`' 'A' to 'À' +compose '`' 'a' to 'à' +compose '\'' 'A' to 'Á' +compose '\'' 'a' to 'á' +compose '^' 'A' to 'Â' +compose '^' 'a' to 'â' +compose '~' 'A' to 'Ã' +compose '~' 'a' to 'ã' +compose '"' 'A' to 'Ä' +compose '"' 'a' to 'ä' +compose 'O' 'A' to 'Å' +compose 'o' 'a' to 'å' +compose '0' 'A' to 'Å' +compose '0' 'a' to 'å' +compose 'A' 'A' to 'Å' +compose 'a' 'a' to 'å' +compose 'A' 'E' to 'Æ' +compose 'a' 'e' to 'æ' +compose ',' 'C' to 'Ç' +compose ',' 'c' to 'ç' +compose '`' 'E' to 'È' +compose '`' 'e' to 'è' +compose '\'' 'E' to 'É' +compose '\'' 'e' to 'é' +compose '^' 'E' to 'Ê' +compose '^' 'e' to 'ê' +compose '"' 'E' to 'Ë' +compose '"' 'e' to 'ë' +compose '`' 'I' to 'Ì' +compose '`' 'i' to 'ì' +compose '\'' 'I' to 'Í' +compose '\'' 'i' to 'í' +compose '^' 'I' to 'Î' +compose '^' 'i' to 'î' +compose '"' 'I' to 'Ï' +compose '"' 'i' to 'ï' +compose '-' 'D' to 'Ð' +compose '-' 'd' to 'ð' +compose '~' 'N' to 'Ñ' +compose '~' 'n' to 'ñ' +compose '`' 'O' to 'Ò' +compose '`' 'o' to 'ò' +compose '\'' 'O' to 'Ó' +compose '\'' 'o' to 'ó' +compose '^' 'O' to 'Ô' +compose '^' 'o' to 'ô' +compose '~' 'O' to 'Õ' +compose '~' 'o' to 'õ' +compose '"' 'O' to 'Ö' +compose '"' 'o' to 'ö' +compose '/' 'O' to 'Ø' +compose '/' 'o' to 'ø' +compose '`' 'U' to 'Ù' +compose '`' 'u' to 'ù' +compose '\'' 'U' to 'Ú' +compose '\'' 'u' to 'ú' +compose '^' 'U' to 'Û' +compose '^' 'u' to 'û' +compose '"' 'U' to 'Ü' +compose '"' 'u' to 'ü' +compose '\'' 'Y' to 'Ý' +compose '\'' 'y' to 'ý' +compose 'T' 'H' to 'Þ' +compose 't' 'h' to 'þ' +compose 's' 's' to 'ß' +compose '"' 'y' to 'ÿ' +compose 's' 'z' to 'ß' +compose 'i' 'j' to 'ÿ' diff --git a/arch/m68k/hp300/reboot.S b/arch/m68k/hp300/reboot.S new file mode 100644 index 000000000..52eb852e6 --- /dev/null +++ b/arch/m68k/hp300/reboot.S @@ -0,0 +1,16 @@ +/* + * linux/arch/m68k/hp300/reboot.S + * + * Copyright (C) 1998 Philip Blundell + * + * Do the dirty work of rebooting the machine. Basically we need to undo all the + * good stuff that head.S did when we started up. The caches and MMU must be + * disabled and then we jump back to the PROM. This is a bit gruesome but we put + * a brave face on it. + */ + +/* XXX Doesn't work yet. Not sure why and can't be bothered to fix it at the moment. */ + + .globl hp300_reset +hp300_reset: + jmp hp300_reset diff --git a/arch/m68k/hp300/time.c b/arch/m68k/hp300/time.c new file mode 100644 index 000000000..bfee13e1d --- /dev/null +++ b/arch/m68k/hp300/time.c @@ -0,0 +1,115 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * linux/arch/m68k/hp300/time.c + * + * Copyright (C) 1998 Philip Blundell + * + * This file contains the HP300-specific time handling code. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +static u64 hp300_read_clk(struct clocksource *cs); + +static struct clocksource hp300_clk = { + .name = "timer", + .rating = 250, + .read = hp300_read_clk, + .mask = CLOCKSOURCE_MASK(32), + .flags = CLOCK_SOURCE_IS_CONTINUOUS, +}; + +static u32 clk_total, clk_offset; + +/* Clock hardware definitions */ + +#define CLOCKBASE 0xf05f8000 + +#define CLKCR1 0x1 +#define CLKCR2 0x3 +#define CLKCR3 CLKCR1 +#define CLKSR CLKCR2 +#define CLKMSB1 0x5 +#define CLKLSB1 0x7 +#define CLKMSB2 0x9 +#define CLKMSB3 0xD + +#define CLKSR_INT1 BIT(0) + +/* This is for machines which generate the exact clock. */ + +#define HP300_TIMER_CLOCK_FREQ 250000 +#define HP300_TIMER_CYCLES (HP300_TIMER_CLOCK_FREQ / HZ) +#define INTVAL (HP300_TIMER_CYCLES - 1) + +static irqreturn_t hp300_tick(int irq, void *dev_id) +{ + irq_handler_t timer_routine = dev_id; + unsigned long flags; + unsigned long tmp; + + local_irq_save(flags); + in_8(CLOCKBASE + CLKSR); + asm volatile ("movpw %1@(5),%0" : "=d" (tmp) : "a" (CLOCKBASE)); + clk_total += INTVAL; + clk_offset = 0; + timer_routine(0, NULL); + local_irq_restore(flags); + + /* Turn off the network and SCSI leds */ + blinken_leds(0, 0xe0); + return IRQ_HANDLED; +} + +static u64 hp300_read_clk(struct clocksource *cs) +{ + unsigned long flags; + unsigned char lsb, msb, msb_new; + u32 ticks; + + local_irq_save(flags); + /* Read current timer 1 value */ + msb = in_8(CLOCKBASE + CLKMSB1); +again: + if ((in_8(CLOCKBASE + CLKSR) & CLKSR_INT1) && msb > 0) + clk_offset = INTVAL; + lsb = in_8(CLOCKBASE + CLKLSB1); + msb_new = in_8(CLOCKBASE + CLKMSB1); + if (msb_new != msb) { + msb = msb_new; + goto again; + } + + ticks = INTVAL - ((msb << 8) | lsb); + ticks += clk_offset + clk_total; + local_irq_restore(flags); + + return ticks; +} + +void __init hp300_sched_init(irq_handler_t vector) +{ + out_8(CLOCKBASE + CLKCR2, 0x1); /* select CR1 */ + out_8(CLOCKBASE + CLKCR1, 0x1); /* reset */ + + asm volatile(" movpw %0,%1@(5)" : : "d" (INTVAL), "a" (CLOCKBASE)); + + if (request_irq(IRQ_AUTO_6, hp300_tick, IRQF_TIMER, "timer tick", vector)) + pr_err("Couldn't register timer interrupt\n"); + + out_8(CLOCKBASE + CLKCR2, 0x1); /* select CR1 */ + out_8(CLOCKBASE + CLKCR1, 0x40); /* enable irq */ + + clocksource_register_hz(&hp300_clk, HP300_TIMER_CLOCK_FREQ); +} diff --git a/arch/m68k/hp300/time.h b/arch/m68k/hp300/time.h new file mode 100644 index 000000000..1d77b55cc --- /dev/null +++ b/arch/m68k/hp300/time.h @@ -0,0 +1 @@ +extern void hp300_sched_init(irq_handler_t vector); diff --git a/arch/m68k/ifpsp060/CHANGES b/arch/m68k/ifpsp060/CHANGES new file mode 100644 index 000000000..ba9659691 --- /dev/null +++ b/arch/m68k/ifpsp060/CHANGES @@ -0,0 +1,120 @@ +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +MOTOROLA MICROPROCESSOR & MEMORY TECHNOLOGY GROUP +M68000 Hi-Performance Microprocessor Division +M68060 Software Package +Production Release P1.00 -- October 10, 1994 + +M68060 Software Package Copyright © 1993, 1994 Motorola Inc. All rights reserved. + +THE SOFTWARE is provided on an "AS IS" basis and without warranty. +To the maximum extent permitted by applicable law, +MOTOROLA DISCLAIMS ALL WARRANTIES WHETHER EXPRESS OR IMPLIED, +INCLUDING IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE +and any warranty against infringement with regard to the SOFTWARE +(INCLUDING ANY MODIFIED VERSIONS THEREOF) and any accompanying written materials. + +To the maximum extent permitted by applicable law, +IN NO EVENT SHALL MOTOROLA BE LIABLE FOR ANY DAMAGES WHATSOEVER +(INCLUDING WITHOUT LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, +BUSINESS INTERRUPTION, LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY LOSS) +ARISING OF THE USE OR INABILITY TO USE THE SOFTWARE. +Motorola assumes no responsibility for the maintenance and support of the SOFTWARE. + +You are hereby granted a copyright license to use, modify, and distribute the SOFTWARE +so long as this entire notice is retained without alteration in any modified and/or +redistributed versions, and that such modified versions are clearly identified as such. +No licenses are granted by implication, estoppel or otherwise under any patents +or trademarks of Motorola, Inc. +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +CHANGES SINCE LAST RELEASE: +--------------------------- + +1) "movep" emulation where data was being read from memory +was reading the intermediate bytes. Emulation now only +reads the required bytes. + +2) "flogn", "flog2", and "flog10" of "1" was setting the +Inexact FPSR bit. Emulation now does not set Inexact for +this case. + +3) For an opclass three FP instruction where the effective addressing +mode was pre-decrement or post-increment and the address register +was A0 or A1, the address register was not being updated as a result +of the operation. This has been corrected. + +4) Beta B.2 version had the following erratum: + + Scenario: + --------- + If {i,d}mem_{read,write}_{byte,word,long}() returns + a failing value to the 68060SP, the package ignores + this return value and continues with program execution + as if it never received a failing value. + + Effect: + ------- + For example, if a user executed "fsin.x ADDR,fp0" where + ADDR should cause a "segmentation violation", the memory read + requested by the package should return a failing value + to the package. Since the package currently ignores this + return value, the user program will continue to the + next instruction, and the result created in fp0 will be + undefined. + + Fix: + ---- + This has been fixed in the current release. + + Notes: + ------ + Upon receiving a non-zero (failing) return value from + a {i,d}mem_{read,write}_{byte,word,long}() "call-out", + the package creates a 16-byte access error stack frame + from the current exception stack frame and exits + through the "call-out" _real_access(). This is the process + as described in the MC68060 User's Manual. + + For instruction read access errors, the info stacked is: + SR = SR at time of exception + PC = PC of instruction being emulated + VOFF = $4008 (stack frame format type) + ADDRESS = PC of instruction being emulated + FSLW = FAULT STATUS LONGWORD + + The valid FSLW bits are: + bit 27 = 1 (misaligned bit) + bit 24 = 1 (read) + bit 23 = 0 (write) + bit 22:21 = 10 (SIZE = word) + bit 20:19 = 00 (TT) + bit 18:16 = x10 (TM; x = 1 for supervisor mode) + bit 15 = 1 (IO) + bit 0 = 1 (Software Emulation Error) + + all other bits are EQUAL TO ZERO and can be set by the _real_access() + "call-out" stub by the user as appropriate. The MC68060 User's Manual + stated that ONLY "bit 0" would be set. The 060SP attempts to set a few + other bits. + + For data read/write access errors, the info stacked is: + SR = SR at time of exception + PC = PC of instruction being emulated + VOFF = $4008 (stack frame format type) + ADDRESS = Address of source or destination operand + FSLW = FAULT STATUS LONGWORD + + The valid FSLW bits are: + bit 27 = 0 (misaligned bit) + bit 24 = x (read; 1 if read, 0 if write) + bit 23 = x (write; 1 if write, 0 if read) + bit 22:21 = xx (SIZE; see MC68060 User's Manual) + bit 20:19 = 00 (TT) + bit 18:16 = x01 (TM; x = 1 for supervisor mode) + bit 15 = 0 (IO) + bit 0 = 1 (Software Emulation Error) + + all other bits are EQUAL TO ZERO and can be set by the _real_access() + "call-out" stub by the user as appropriate. The MC68060 User's Manual + stated that ONLY "bit 0" would be set. The 060SP attempts to set a few + other bits. diff --git a/arch/m68k/ifpsp060/MISC b/arch/m68k/ifpsp060/MISC new file mode 100644 index 000000000..1a63913da --- /dev/null +++ b/arch/m68k/ifpsp060/MISC @@ -0,0 +1,201 @@ +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +MOTOROLA MICROPROCESSOR & MEMORY TECHNOLOGY GROUP +M68000 Hi-Performance Microprocessor Division +M68060 Software Package +Production Release P1.00 -- October 10, 1994 + +M68060 Software Package Copyright © 1993, 1994 Motorola Inc. All rights reserved. + +THE SOFTWARE is provided on an "AS IS" basis and without warranty. +To the maximum extent permitted by applicable law, +MOTOROLA DISCLAIMS ALL WARRANTIES WHETHER EXPRESS OR IMPLIED, +INCLUDING IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE +and any warranty against infringement with regard to the SOFTWARE +(INCLUDING ANY MODIFIED VERSIONS THEREOF) and any accompanying written materials. + +To the maximum extent permitted by applicable law, +IN NO EVENT SHALL MOTOROLA BE LIABLE FOR ANY DAMAGES WHATSOEVER +(INCLUDING WITHOUT LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, +BUSINESS INTERRUPTION, LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY LOSS) +ARISING OF THE USE OR INABILITY TO USE THE SOFTWARE. +Motorola assumes no responsibility for the maintenance and support of the SOFTWARE. + +You are hereby granted a copyright license to use, modify, and distribute the SOFTWARE +so long as this entire notice is retained without alteration in any modified and/or +redistributed versions, and that such modified versions are clearly identified as such. +No licenses are granted by implication, estoppel or otherwise under any patents +or trademarks of Motorola, Inc. +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +RELEASE FILE VERSIONS: +----------------------- + +fpsp.sa +---------- +freal.s : 2.4 +hdr.fpu : 2.4 +x_fovfl.s : 2.16 +x_funfl.s : 2.19 +x_funsupp.s : 2.27 +x_effadd.s : 2.21 +x_foperr.s : 2.9 +x_fsnan.s : 2.12 +x_finex.s : 2.14 +x_fdz.s : 2.5 +x_fline.s : 2.5 +x_funimp.s : 2.27 +fsin.s : 2.6 +ftan.s : 2.6 +fatan.s : 2.3 +fasin.s : 2.3 +facos.s : 2.5 +fetox.s : 2.4 +fgetem.s : 2.5 +fcosh.s : 2.4 +fsinh.s : 2.5 +ftanh.s : 2.3 +flogn.s : 2.6 +fatanh.s : 2.4 +flog2.s : 2.4 +ftwotox.s : 2.4 +fmovecr.s : 2.5 +fscale.s : 2.5 +frem_mod.s : 2.6 +fkern.s : 2.6 +fkern2.s : 2.5 +fgen_except.s: 2.7 +foptbl.s : 2.3 +fmul.s : 2.5 +fin.s : 2.4 +fdiv.s : 2.5 +fneg.s : 2.4 +ftst.s : 2.3 +fint.s : 2.3 +fintrz.s : 2.3 +fabs.s : 2.4 +fcmp.s : 2.4 +fsglmul.s : 2.5 +fsgldiv.s : 2.8 +fadd.s : 2.6 +fsub.s : 2.6 +fsqrt.s : 2.4 +fmisc.s : 2.3 +fdbcc.s : 2.8 +ftrapcc.s : 2.5 +fscc.s : 2.6 +fmovm.s : 2.15 +fctrl.s : 2.6 +fcalc_ea.s : 2.7 +fmem.s : 2.9 +fout.s : 2.9 +ireg.s : 2.6 +fdenorm.s : 2.3 +fround.s : 2.4 +fnorm.s : 2.3 +foptag_set.s: 2.4 +fresult.s : 2.3 +fpack.s : 2.6 +fdecbin.s : 2.4 +fbindec.s : 2.5 +fbinstr.s : 2.3 +faccess.s : 2.3 + +pfpsp.sa +---------- +freal.s : 2.4 +hdr.fpu : 2.4 +x_fovfl.s : 2.16 +x_funfl.s : 2.19 +x_funsupp.s : 2.27 +x_effadd.s : 2.21 +x_foperr.s : 2.9 +x_fsnan.s : 2.12 +x_finex.s : 2.14 +x_fdz.s : 2.5 +x_fline2.s : 2.3 +fcalc_ea.s : 2.7 +foptbl2.s : 2.4 +fmovm.s : 2.15 +fctrl.s : 2.6 +fmisc.s : 2.3 +fdenorm.s : 2.3 +fround.s : 2.4 +fnorm.s : 2.3 +foptag_set.s: 2.4 +fresult.s : 2.3 +fout.s : 2.9 +fmul.s : 2.5 +fin.s : 2.4 +fdiv.s : 2.5 +fneg.s : 2.4 +ftst.s : 2.3 +fint.s : 2.3 +fintrz.s : 2.3 +fabs.s : 2.4 +fcmp.s : 2.4 +fsglmul.s : 2.5 +fsgldiv.s : 2.8 +fadd.s : 2.6 +fsub.s : 2.6 +fsqrt.s : 2.4 +ireg.s : 2.6 +fpack.s : 2.6 +fdecbin.s : 2.4 +fbindec.s : 2.5 +fbinstr.s : 2.3 +faccess.s : 2.3 + +fplsp.sa +---------- +lfptop.s : 2.3 +hdr.fpu : 2.4 +fsin.s : 2.6 +ftan.s : 2.6 +fatan.s : 2.3 +fasin.s : 2.3 +facos.s : 2.5 +fetox.s : 2.4 +fgetem.s : 2.5 +fcosh.s : 2.4 +fsinh.s : 2.5 +ftanh.s : 2.3 +flogn.s : 2.6 +fatanh.s : 2.4 +flog2.s : 2.4 +ftwotox.s : 2.4 +fscale.s : 2.5 +frem_mod.s : 2.6 +l_support.s : 2.15 +fnorm.s : 2.3 + +isp.sa +---------- +ireal.s : 2.4 +hdr.int : 2.4 +x_uieh.s : 2.13 +icalc_ea.s : 2.11 +imovep.s : 2.8 +ichk2cmp2.s : 2.6 +idiv64.s : 2.10 +imul64.s : +icas2.s : 2.11 +icas.s : 2.12 +icas2_core.s: 2.6 +icas_core.s : 2.6 + +ilsp.sa +---------- +litop.s : 2.2 +l_idiv64.s : 2.8 +l_imul64.s : 2.6 +l_ichk2cmp2.s: 2.5 + +ex. files +---------- +wrk/fskeleton.s: 2.2 +wrk/iskeleton.s: 2.2 +wrk/os.s : 2.1 + +tests +---------- +itest.s : 2.2 +ftest.s : 2.1 diff --git a/arch/m68k/ifpsp060/Makefile b/arch/m68k/ifpsp060/Makefile new file mode 100644 index 000000000..43b435049 --- /dev/null +++ b/arch/m68k/ifpsp060/Makefile @@ -0,0 +1,9 @@ +# Makefile for 680x0 Linux 68060 integer/floating point support package +# +# This file is subject to the terms and conditions of the GNU General Public +# License. See the file "README.legal" in the main directory of this archive +# for more details. + +obj-y := fskeleton.o iskeleton.o os.o + +EXTRA_LDFLAGS := -x diff --git a/arch/m68k/ifpsp060/README b/arch/m68k/ifpsp060/README new file mode 100644 index 000000000..f6f8f5c59 --- /dev/null +++ b/arch/m68k/ifpsp060/README @@ -0,0 +1,71 @@ +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +MOTOROLA MICROPROCESSOR & MEMORY TECHNOLOGY GROUP +M68000 Hi-Performance Microprocessor Division +M68060 Software Package +Production Release P1.00 -- October 10, 1994 + +M68060 Software Package Copyright © 1993, 1994 Motorola Inc. All rights reserved. + +THE SOFTWARE is provided on an "AS IS" basis and without warranty. +To the maximum extent permitted by applicable law, +MOTOROLA DISCLAIMS ALL WARRANTIES WHETHER EXPRESS OR IMPLIED, +INCLUDING IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE +and any warranty against infringement with regard to the SOFTWARE +(INCLUDING ANY MODIFIED VERSIONS THEREOF) and any accompanying written materials. + +To the maximum extent permitted by applicable law, +IN NO EVENT SHALL MOTOROLA BE LIABLE FOR ANY DAMAGES WHATSOEVER +(INCLUDING WITHOUT LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, +BUSINESS INTERRUPTION, LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY LOSS) +ARISING OF THE USE OR INABILITY TO USE THE SOFTWARE. +Motorola assumes no responsibility for the maintenance and support of the SOFTWARE. + +You are hereby granted a copyright license to use, modify, and distribute the SOFTWARE +so long as this entire notice is retained without alteration in any modified and/or +redistributed versions, and that such modified versions are clearly identified as such. +No licenses are granted by implication, estoppel or otherwise under any patents +or trademarks of Motorola, Inc. +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +Files in this directory: +------------------------- + +fpsp.sa Full FP Kernel Module - hex image +fpsp.s Full FP Kernel Module - source code +fpsp.doc Full FP Kernel Module - on-line documentation + +pfpsp.sa Partial FP Kernel Module - hex image +pfpsp.s Partial FP Kernel Module - source code + +fplsp.sa FP Library Module - hex image +fplsp.s FP Library Module - source code +fplsp.doc FP Library Module - on-line documentation + +isp.sa Integer Unimplemented Kernel Module - hex image +isp.s Integer Unimplemented Kernel Module - source code +isp.doc Integer Unimplemented Kernel Module - on-line doc + +ilsp.sa Integer Unimplemented Library Module - hex image +ilsp.s Integer Unimplemented Library Module - source code +ilsp.doc Integer Unimplemented Library Module - on-line doc + +fskeleton.s Sample Call-outs needed by fpsp.sa and pfpsp.sa + +iskeleton.s Sample Call-outs needed by isp.sa + +os.s Sample Call-outs needed by fpsp.sa, pfpsp.sa, and isp.sa + +ftest.sa Simple test program to test that {p}fpsp.sa + was connected properly; hex image +ftest.s above test; source code + +itest.sa Simple test program to test that isp.sa was + connected properly; hex image +itest.s above test; source code + +test.doc on-line documentation for {i,f}test.sa + +README This file + +ERRATA Known errata for this release + +MISC Release file version numbers diff --git a/arch/m68k/ifpsp060/TEST.DOC b/arch/m68k/ifpsp060/TEST.DOC new file mode 100644 index 000000000..1ba3aef15 --- /dev/null +++ b/arch/m68k/ifpsp060/TEST.DOC @@ -0,0 +1,208 @@ +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +MOTOROLA MICROPROCESSOR & MEMORY TECHNOLOGY GROUP +M68000 Hi-Performance Microprocessor Division +M68060 Software Package +Production Release P1.00 -- October 10, 1994 + +M68060 Software Package Copyright © 1993, 1994 Motorola Inc. All rights reserved. + +THE SOFTWARE is provided on an "AS IS" basis and without warranty. +To the maximum extent permitted by applicable law, +MOTOROLA DISCLAIMS ALL WARRANTIES WHETHER EXPRESS OR IMPLIED, +INCLUDING IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE +and any warranty against infringement with regard to the SOFTWARE +(INCLUDING ANY MODIFIED VERSIONS THEREOF) and any accompanying written materials. + +To the maximum extent permitted by applicable law, +IN NO EVENT SHALL MOTOROLA BE LIABLE FOR ANY DAMAGES WHATSOEVER +(INCLUDING WITHOUT LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, +BUSINESS INTERRUPTION, LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY LOSS) +ARISING OF THE USE OR INABILITY TO USE THE SOFTWARE. +Motorola assumes no responsibility for the maintenance and support of the SOFTWARE. + +You are hereby granted a copyright license to use, modify, and distribute the SOFTWARE +so long as this entire notice is retained without alteration in any modified and/or +redistributed versions, and that such modified versions are clearly identified as such. +No licenses are granted by implication, estoppel or otherwise under any patents +or trademarks of Motorola, Inc. +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +68060 SOFTWARE PACKAGE (Kernel version) SIMPLE TESTS +----------------------------------------------------- + +The files itest.sa and ftest.sa contain simple tests to check +the state of the 68060ISP and 68060FPSP once they have been installed. + +Release file format: +-------------------- +The release files itest.sa and ftest.sa are essentially +hexadecimal images of the actual tests. This format is the +ONLY format that will be supported. The hex images were created +by assembling the source code and then converting the resulting +binary output images into ASCII text files. The hexadecimal +numbers are listed using the Motorola Assembly syntax assembler +directive "dc.l" (define constant longword). The files can be +converted to other assembly syntaxes by using any word processor +with a global search and replace function. + +To assist in assembling and linking these modules with other modules, +the installer should add symbolic labels to the top of the files. +This will allow the calling routines to access the entry points +of these packages. + +The source code itest.s and ftest.s have been included but only +for documentation purposes. + +Release file structure: +----------------------- + +(top of module) + ----------------- + | | - 128 byte-sized section + (1) | Call-Out | - 4 bytes per entry (user fills these in) + | | + ----------------- + | | - 8 bytes per entry + (2) | Entry Point | - user does "bsr" or "jsr" to this address + | | + ----------------- + | | - code section + (3) ~ ~ + | | + ----------------- +(bottom of module) + +The first section of this module is the "Call-out" section. This section +is NOT INCLUDED in {i,f}test.sa (an example "Call-out" section is provided at +the end of this file). The purpose of this section is to allow the test +routines to reference external printing functions that must be provided +by the host operating system. This section MUST be exactly 128 bytes in +size. There are 32 fields, each 4 bytes in size. Each field corresponds +to a function required by the test packages (these functions and their +location are listed in "68060{ISP,FPSP}-TEST call-outs" below). Each field +entry should contain the address of the corresponding function RELATIVE to +the starting address of the "call-out" section. The "Call-out" section must +sit adjacent to the {i,f}test.sa image in memory. Since itest.sa and ftest.sa +are individual tests, they each require their own "Call-out" sections. + +The second section, the "Entry-point" section, is used by external routines +to access the test routines. Since the {i,f}test.sa hex files contain +no symbol names, this section contains function entry points that are fixed +with respect to the top of the package. The currently defined entry-points +are listed in section "68060{ISP,FPSP}-TEST entry points" below. A calling +routine would simply execute a "bsr" or "jsr" that jumped to the selected +function entry-point. + +For example, to run the 060ISP test, write a program that includes the +itest.sa data and execute something similar to: + + bsr _060ISP_TEST+128+0 + +(_060ISP_TEST is the starting address of the "Call-out" section; the "Call-out" +section is 128 bytes long; and the 68060ISP test entry point is located +0 bytes from the top of the "Entry-point" section.) + +The third section is the code section. After entering through an "Entry-point", +the entry code jumps to the appropriate test code within the code section. + +68060ISP-TEST Call-outs: +------------------------ +0x0: _print_string() +0x4: _print_number() + +68060FPSP-TEST Call-outs: +------------------------- +0x0: _print_string() +0x4: _print_number() + +The test packages call _print_string() and _print_number() +as subroutines and expect the main program to print a string +or a number to a file or to the screen. +In "C"-like fashion, the test program calls: + + print_string("Test passed"); + + or + + print_number(20); + +For _print_string(), the test programs pass a longword address +of the string on the stack. For _print_number(), the test programs pass +a longword number to be printed. + +For debugging purposes, after the main program performs a "print" +for a test package, it should flush the output so that it's not +buffered. In this way, if the test program crashes, at least the previous +statements printed will be seen. + +68060ISP-TEST Entry-points: +--------------------------- +0x0: integer test + +68060FPSP-TEST Entry-points: +---------------------------- +0x00: main fp test +0x08: FP unimplemented test +0x10: FP enabled snan/operr/ovfl/unfl/dz/inex + +The floating-point unit test has 3 entry points which will require +3 different calls to the package if each of the three following tests +is desired: + +main fp test: tests (1) unimp effective address exception + (2) unsupported data type exceptions + (3) non-maskable overflow/underflow exceptions + +FP unimplemented: tests FP unimplemented exception. this one is + separate from the previous tests for systems that don't + want FP unimplemented instructions. + +FP enabled: tests enabled snan/operr/ovfl/unfl/dz/inex. + basically, it enables each of these exceptions and forces + each using an implemented FP instruction. this process + exercises _fpsp_{snan,operr,ovfl,unfl,dz,inex}() and + _real_{snan,operr,ovfl,unfl,dz,inex}(). the test expects + _real_XXXX() to do nothing except clear the exception + and "rte". if a system's _real_XXXX() handler creates an + alternate result, the test will print "failed" but this + is acceptable. + +Miscellaneous: +-------------- +Again, itest.sa and ftest.sa are simple tests and do not thoroughly +test all 68060SP connections. For example, they do not test connections +to _real_access(), _real_trace(), _real_trap(), etc. because these +will be system-implemented several different ways and the test packages +must remain system independent. + +Example test package set-up: +---------------------------- +_print_str: + . # provided by system + rts + +_print_num: + . # provided by system + rts + + . + . + bsr _060FPSP_TEST+128+0 + . + . + rts + +# beginning of "Call-out" section; provided by integrator. +# MUST be 128 bytes long. +_060FPSP_TEST: + long _print_str - _060FPSP_TEST + long _print_num - _060FPSP_TEST + space 120 + +# ftest.sa starts here; start of "Entry-point" section. + long 0x60ff0000, 0x00002346 + long 0x60ff0000, 0x00018766 + long 0x60ff0000, 0x00023338 + long 0x24377299, 0xab2643ea + . + . + . diff --git a/arch/m68k/ifpsp060/fplsp.doc b/arch/m68k/ifpsp060/fplsp.doc new file mode 100644 index 000000000..89730a934 --- /dev/null +++ b/arch/m68k/ifpsp060/fplsp.doc @@ -0,0 +1,231 @@ +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +MOTOROLA MICROPROCESSOR & MEMORY TECHNOLOGY GROUP +M68000 Hi-Performance Microprocessor Division +M68060 Software Package +Production Release P1.00 -- October 10, 1994 + +M68060 Software Package Copyright © 1993, 1994 Motorola Inc. All rights reserved. + +THE SOFTWARE is provided on an "AS IS" basis and without warranty. +To the maximum extent permitted by applicable law, +MOTOROLA DISCLAIMS ALL WARRANTIES WHETHER EXPRESS OR IMPLIED, +INCLUDING IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE +and any warranty against infringement with regard to the SOFTWARE +(INCLUDING ANY MODIFIED VERSIONS THEREOF) and any accompanying written materials. + +To the maximum extent permitted by applicable law, +IN NO EVENT SHALL MOTOROLA BE LIABLE FOR ANY DAMAGES WHATSOEVER +(INCLUDING WITHOUT LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, +BUSINESS INTERRUPTION, LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY LOSS) +ARISING OF THE USE OR INABILITY TO USE THE SOFTWARE. +Motorola assumes no responsibility for the maintenance and support of the SOFTWARE. + +You are hereby granted a copyright license to use, modify, and distribute the SOFTWARE +so long as this entire notice is retained without alteration in any modified and/or +redistributed versions, and that such modified versions are clearly identified as such. +No licenses are granted by implication, estoppel or otherwise under any patents +or trademarks of Motorola, Inc. +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +68060 FLOATING-POINT SOFTWARE PACKAGE (Library version) +-------------------------------------------------------- + +The file fplsp.sa contains the "Library version" of the +68060SP Floating-Point Software Package. The routines +included in this module can be used to emulate the +FP instructions not implemented in 68060 hardware. These +instructions normally take exception vector #11 +"FP Unimplemented Instruction". + +By re-compiling a program that uses these instructions, and +making subroutine calls in place of the unimplemented +instructions, a program can avoid the overhead associated +with taking the exception. + +Release file format: +-------------------- +The file fplsp.sa is essentially a hexadecimal image of the +release package. This is the ONLY format which will be supported. +The hex image was created by assembling the source code and +then converting the resulting binary output image into an +ASCII text file. The hexadecimal numbers are listed +using the Motorola Assembly Syntax assembler directive "dc.l" +(define constant longword). The file can be converted to other +assembly syntaxes by using any word processor with a global +search and replace function. + +To assist in assembling and linking this module with other modules, +the installer should add a symbolic label to the top of the file. +This will allow calling routines to access the entry points +of this package. + +The source code fplsp.s has also been included but only for +documentation purposes. + +Release file structure: +----------------------- +The file fplsp.sa contains an "Entry-Point" section and a +code section. The FPLSP has no "Call-Out" section. The first section +is the "Entry-Point" section. In order to access a function in the +package, a program must "bsr" or "jsr" to the location listed +below in "68060FPLSP entry points" that corresponds to the desired +function. A branch instruction located at the selected entry point +within the package will then enter the correct emulation code routine. + +The entry point addresses at the beginning of the package will remain +fixed so that a program calling the routines will not have to be +re-compiled with every new 68060FPLSP release. + +There are 3 entry-points for each instruction type: single precision, +double precision, and extended precision. + +As an example, the "fsin" library instruction can be passed an +extended precision operand if program executes: + +# fsin.x fp0 + + fmovm.x &0x01,-(%sp) # pass operand on stack + bsr.l _060FPLSP_TOP+0x1a8 # branch to fsin routine + add.l &0xc,%sp # clear operand from stack + +Upon return, fp0 holds the correct result. The FPSR is +set correctly. The FPCR is unchanged. The FPIAR is undefined. + +Another example. This time, a dyadic operation: + +# frem.s %fp1,%fp0 + + fmov.s %fp1,-(%sp) # pass src operand + fmov.s %fp0,-(%sp) # pass dst operand + bsr.l _060FPLSP_TOP+0x168 # branch to frem routine + addq.l &0x8,%sp # clear operands from stack + +Again, the result is returned in fp0. Note that BOTH operands +are passed in single precision format. + +Exception reporting: +-------------------- +The package takes exceptions according to the FPCR value upon subroutine +entry. If an exception should be reported, then the package forces +this exception using implemented floating-point instructions. +For example, if the instruction being emulated should cause a +floating-point Operand Error exception, then the library routine +executes an FMUL of a zero and an infinity to force the OPERR +exception. Although the FPIAR will be undefined for the enabled +Operand Error exception handler, the user will at least be able +to record that the event occurred. + +Miscellaneous: +-------------- +The package does not attempt to correctly emulate instructions +with Signalling NAN inputs. Use of SNANs should be avoided with +this package. + +The fabs/fadd/fdiv/fint/fintrz/fmul/fneg/fsqrt/fsub entry points +are provided for the convenience of older compilers that make +subroutine calls for all fp instructions. The code does NOT emulate +the instruction but rather simply executes it. + +68060FPLSP entry points: +------------------------ +_060FPLSP_TOP: +0x000: _060LSP__facoss_ +0x008: _060LSP__facosd_ +0x010: _060LSP__facosx_ +0x018: _060LSP__fasins_ +0x020: _060LSP__fasind_ +0x028: _060LSP__fasinx_ +0x030: _060LSP__fatans_ +0x038: _060LSP__fatand_ +0x040: _060LSP__fatanx_ +0x048: _060LSP__fatanhs_ +0x050: _060LSP__fatanhd_ +0x058: _060LSP__fatanhx_ +0x060: _060LSP__fcoss_ +0x068: _060LSP__fcosd_ +0x070: _060LSP__fcosx_ +0x078: _060LSP__fcoshs_ +0x080: _060LSP__fcoshd_ +0x088: _060LSP__fcoshx_ +0x090: _060LSP__fetoxs_ +0x098: _060LSP__fetoxd_ +0x0a0: _060LSP__fetoxx_ +0x0a8: _060LSP__fetoxm1s_ +0x0b0: _060LSP__fetoxm1d_ +0x0b8: _060LSP__fetoxm1x_ +0x0c0: _060LSP__fgetexps_ +0x0c8: _060LSP__fgetexpd_ +0x0d0: _060LSP__fgetexpx_ +0x0d8: _060LSP__fgetmans_ +0x0e0: _060LSP__fgetmand_ +0x0e8: _060LSP__fgetmanx_ +0x0f0: _060LSP__flog10s_ +0x0f8: _060LSP__flog10d_ +0x100: _060LSP__flog10x_ +0x108: _060LSP__flog2s_ +0x110: _060LSP__flog2d_ +0x118: _060LSP__flog2x_ +0x120: _060LSP__flogns_ +0x128: _060LSP__flognd_ +0x130: _060LSP__flognx_ +0x138: _060LSP__flognp1s_ +0x140: _060LSP__flognp1d_ +0x148: _060LSP__flognp1x_ +0x150: _060LSP__fmods_ +0x158: _060LSP__fmodd_ +0x160: _060LSP__fmodx_ +0x168: _060LSP__frems_ +0x170: _060LSP__fremd_ +0x178: _060LSP__fremx_ +0x180: _060LSP__fscales_ +0x188: _060LSP__fscaled_ +0x190: _060LSP__fscalex_ +0x198: _060LSP__fsins_ +0x1a0: _060LSP__fsind_ +0x1a8: _060LSP__fsinx_ +0x1b0: _060LSP__fsincoss_ +0x1b8: _060LSP__fsincosd_ +0x1c0: _060LSP__fsincosx_ +0x1c8: _060LSP__fsinhs_ +0x1d0: _060LSP__fsinhd_ +0x1d8: _060LSP__fsinhx_ +0x1e0: _060LSP__ftans_ +0x1e8: _060LSP__ftand_ +0x1f0: _060LSP__ftanx_ +0x1f8: _060LSP__ftanhs_ +0x200: _060LSP__ftanhd_ +0x208: _060LSP__ftanhx_ +0x210: _060LSP__ftentoxs_ +0x218: _060LSP__ftentoxd_ +0x220: _060LSP__ftentoxx_ +0x228: _060LSP__ftwotoxs_ +0x230: _060LSP__ftwotoxd_ +0x238: _060LSP__ftwotoxx_ + +0x240: _060LSP__fabss_ +0x248: _060LSP__fabsd_ +0x250: _060LSP__fabsx_ +0x258: _060LSP__fadds_ +0x260: _060LSP__faddd_ +0x268: _060LSP__faddx_ +0x270: _060LSP__fdivs_ +0x278: _060LSP__fdivd_ +0x280: _060LSP__fdivx_ +0x288: _060LSP__fints_ +0x290: _060LSP__fintd_ +0x298: _060LSP__fintx_ +0x2a0: _060LSP__fintrzs_ +0x2a8: _060LSP__fintrzd_ +0x2b0: _060LSP__fintrzx_ +0x2b8: _060LSP__fmuls_ +0x2c0: _060LSP__fmuld_ +0x2c8: _060LSP__fmulx_ +0x2d0: _060LSP__fnegs_ +0x2d8: _060LSP__fnegd_ +0x2e0: _060LSP__fnegx_ +0x2e8: _060LSP__fsqrts_ +0x2f0: _060LSP__fsqrtd_ +0x2f8: _060LSP__fsqrtx_ +0x300: _060LSP__fsubs_ +0x308: _060LSP__fsubd_ +0x310: _060LSP__fsubx_ diff --git a/arch/m68k/ifpsp060/fplsp.sa b/arch/m68k/ifpsp060/fplsp.sa new file mode 100644 index 000000000..8826df032 --- /dev/null +++ b/arch/m68k/ifpsp060/fplsp.sa @@ -0,0 +1,1946 @@ + dc.l $60ff0000,$238e0000,$60ff0000,$24200000 + dc.l $60ff0000,$24b60000,$60ff0000,$11060000 + dc.l $60ff0000,$11980000,$60ff0000,$122e0000 + dc.l $60ff0000,$0f160000,$60ff0000,$0fa80000 + dc.l $60ff0000,$103e0000,$60ff0000,$12ae0000 + dc.l $60ff0000,$13400000,$60ff0000,$13d60000 + dc.l $60ff0000,$05ae0000,$60ff0000,$06400000 + dc.l $60ff0000,$06d60000,$60ff0000,$213e0000 + dc.l $60ff0000,$21d00000,$60ff0000,$22660000 + dc.l $60ff0000,$16160000,$60ff0000,$16a80000 + dc.l $60ff0000,$173e0000,$60ff0000,$0aee0000 + dc.l $60ff0000,$0b800000,$60ff0000,$0c160000 + dc.l $60ff0000,$24a60000,$60ff0000,$25380000 + dc.l $60ff0000,$25ce0000,$60ff0000,$26660000 + dc.l $60ff0000,$26f80000,$60ff0000,$278e0000 + dc.l $60ff0000,$1d160000,$60ff0000,$1da80000 + dc.l $60ff0000,$1e3e0000,$60ff0000,$1ed60000 + dc.l $60ff0000,$1f680000,$60ff0000,$1ffe0000 + dc.l $60ff0000,$1b0e0000,$60ff0000,$1ba00000 + dc.l $60ff0000,$1c360000,$60ff0000,$08860000 + dc.l $60ff0000,$09180000,$60ff0000,$09ae0000 + dc.l $60ff0000,$2bf00000,$60ff0000,$2ca40000 + dc.l $60ff0000,$2d580000,$60ff0000,$29980000 + dc.l $60ff0000,$2a4c0000,$60ff0000,$2b000000 + dc.l $60ff0000,$2e000000,$60ff0000,$2eb40000 + dc.l $60ff0000,$2f680000,$60ff0000,$029e0000 + dc.l $60ff0000,$03300000,$60ff0000,$03c60000 + dc.l $60ff0000,$27660000,$60ff0000,$27fe0000 + dc.l $60ff0000,$289a0000,$60ff0000,$061e0000 + dc.l $60ff0000,$06b00000,$60ff0000,$07460000 + dc.l $60ff0000,$12ee0000,$60ff0000,$13800000 + dc.l $60ff0000,$14160000,$60ff0000,$0b760000 + dc.l $60ff0000,$0c080000,$60ff0000,$0c9e0000 + dc.l $60ff0000,$18460000,$60ff0000,$18d80000 + dc.l $60ff0000,$196e0000,$60ff0000,$16560000 + dc.l $60ff0000,$16e80000,$60ff0000,$177e0000 + dc.l $60ff0000,$72fe0000,$60ff0000,$72fe0000 + dc.l $60ff0000,$72fe0000,$60ff0000,$71be0000 + dc.l $60ff0000,$71d40000,$60ff0000,$71ea0000 + dc.l $60ff0000,$72840000,$60ff0000,$729a0000 + dc.l $60ff0000,$72b00000,$60ff0000,$72fe0000 + dc.l $60ff0000,$72fe0000,$60ff0000,$72fe0000 + dc.l $60ff0000,$72fe0000,$60ff0000,$72fe0000 + dc.l $60ff0000,$72fe0000,$60ff0000,$71f20000 + dc.l $60ff0000,$72080000,$60ff0000,$721e0000 + dc.l $60ff0000,$72860000,$60ff0000,$72860000 + dc.l $60ff0000,$72860000,$60ff0000,$72860000 + dc.l $60ff0000,$72860000,$60ff0000,$72860000 + dc.l $60ff0000,$71600000,$60ff0000,$71760000 + dc.l $60ff0000,$718c0000,$51fc51fc,$51fc51fc + dc.l $51fc51fc,$51fc51fc,$51fc51fc,$51fc51fc + dc.l $51fc51fc,$51fc51fc,$51fc51fc,$51fc51fc + dc.l $51fc51fc,$51fc51fc,$51fc51fc,$51fc51fc + dc.l $51fc51fc,$51fc51fc,$51fc51fc,$51fc51fc + dc.l $51fc51fc,$51fc51fc,$51fc51fc,$51fc51fc + dc.l $51fc51fc,$51fc51fc,$51fc51fc,$51fc51fc + dc.l $51fc51fc,$51fc51fc,$51fc51fc,$51fc51fc + dc.l $51fc51fc,$51fc51fc,$51fc51fc,$51fc51fc + dc.l $51fc51fc,$51fc51fc,$51fc51fc,$51fc51fc + dc.l $51fc51fc,$51fc51fc,$51fc51fc,$51fc51fc + dc.l $51fc51fc,$51fc51fc,$51fc51fc,$51fc51fc + dc.l $51fc51fc,$51fc51fc,$51fc51fc,$51fc51fc + dc.l $51fc51fc,$51fc51fc,$51fc51fc,$51fc51fc + dc.l $51fc51fc,$51fc51fc,$51fc51fc,$51fc51fc + dc.l $40c62d38,$d3d64634,$3d6f90ae,$b1e75cc7 + dc.l $40000000,$c90fdaa2,$2168c235,$00000000 + dc.l $3fff0000,$c90fdaa2,$2168c235,$00000000 + dc.l $3fe45f30,$6dc9c883,$4e56ff40,$48ee0303 + dc.l $ff9cf22e,$b800ff60,$f22ef0c0,$ffdcf23c + dc.l $90000000,$0000f22e,$44000008,$f22e6800 + dc.l $ff6c41ee,$ff6c61ff,$00006c76,$1d40ff4e + dc.l $120002ae,$00ff00ff,$ff644280,$102eff63 + dc.l $4a016608,$61ff0000,$2ddc6030,$0c010001 + dc.l $660861ff,$00007124,$60220c01,$00026608 + dc.l $61ff0000,$6d226014,$0c010003,$660861ff + dc.l $00006f4c,$600661ff,$00002f8e,$4cee0303 + dc.l $ff9cf22e,$9800ff60,$f22ed040,$ffe84e5e + dc.l $4e754e56,$ff4048ee,$0303ff9c,$f22eb800 + dc.l $ff60f22e,$f0c0ffdc,$f23c9000,$00000000 + dc.l $f22e5400,$0008f22e,$6800ff6c,$41eeff6c + dc.l $61ff0000,$6bdc1d40,$ff4e1200,$02ae00ff + dc.l $00ffff64,$4280102e,$ff631d41,$ff4e4a01 + dc.l $660861ff,$00002d3e,$60300c01,$00016608 + dc.l $61ff0000,$70866022,$0c010002,$660861ff + dc.l $00006c84,$60140c01,$00036608,$61ff0000 + dc.l $6eae6006,$61ff0000,$2ef04cee,$0303ff9c + dc.l $f22e9800,$ff60f22e,$d040ffe8,$4e5e4e75 + dc.l $4e56ff40,$48ee0303,$ff9cf22e,$b800ff60 + dc.l $f22ef0c0,$ffdcf23c,$90000000,$000041ee + dc.l $ff6c216e,$00080000,$216e000c,$0004216e + dc.l $00100008,$61ff0000,$6b381d40,$ff4e1200 + dc.l $02ae00ff,$00ffff64,$4280102e,$ff634a01 + dc.l $660861ff,$00002c9e,$60300c01,$00016608 + dc.l $61ff0000,$6fe66022,$0c010002,$660861ff + dc.l $00006be4,$60140c01,$00036608,$61ff0000 + dc.l $6e0e6006,$61ff0000,$2e504cee,$0303ff9c + dc.l $f22e9800,$ff60f22e,$d040ffe8,$4e5e4e75 + dc.l $4e56ff40,$48ee0303,$ff9cf22e,$b800ff60 + dc.l $f22ef0c0,$ffdcf23c,$90000000,$0000f22e + dc.l $44000008,$f22e6800,$ff6c41ee,$ff6c61ff + dc.l $00006a9e,$1d40ff4e,$120002ae,$00ff00ff + dc.l $ff644280,$102eff63,$4a016608,$61ff0000 + dc.l $2c0e6030,$0c010001,$660861ff,$00006fc8 + dc.l $60220c01,$00026608,$61ff0000,$6b4a6014 + dc.l $0c010003,$660861ff,$00006d74,$600661ff + dc.l $00002dbc,$4cee0303,$ff9cf22e,$9800ff60 + dc.l $f22ed040,$ffe84e5e,$4e754e56,$ff4048ee + dc.l $0303ff9c,$f22eb800,$ff60f22e,$f0c0ffdc + dc.l $f23c9000,$00000000,$f22e5400,$0008f22e + dc.l $6800ff6c,$41eeff6c,$61ff0000,$6a041d40 + dc.l $ff4e1200,$02ae00ff,$00ffff64,$4280102e + dc.l $ff631d41,$ff4e4a01,$660861ff,$00002b70 + dc.l $60300c01,$00016608,$61ff0000,$6f2a6022 + dc.l $0c010002,$660861ff,$00006aac,$60140c01 + dc.l $00036608,$61ff0000,$6cd66006,$61ff0000 + dc.l $2d1e4cee,$0303ff9c,$f22e9800,$ff60f22e + dc.l $d040ffe8,$4e5e4e75,$4e56ff40,$48ee0303 + dc.l $ff9cf22e,$b800ff60,$f22ef0c0,$ffdcf23c + dc.l $90000000,$000041ee,$ff6c216e,$00080000 + dc.l $216e000c,$0004216e,$00100008,$61ff0000 + dc.l $69601d40,$ff4e1200,$02ae00ff,$00ffff64 + dc.l $4280102e,$ff634a01,$660861ff,$00002ad0 + dc.l $60300c01,$00016608,$61ff0000,$6e8a6022 + dc.l $0c010002,$660861ff,$00006a0c,$60140c01 + dc.l $00036608,$61ff0000,$6c366006,$61ff0000 + dc.l $2c7e4cee,$0303ff9c,$f22e9800,$ff60f22e + dc.l $d040ffe8,$4e5e4e75,$4e56ff40,$48ee0303 + dc.l $ff9cf22e,$b800ff60,$f22ef0c0,$ffdcf23c + dc.l $90000000,$0000f22e,$44000008,$f22e6800 + dc.l $ff6c41ee,$ff6c61ff,$000068c6,$1d40ff4e + dc.l $120002ae,$00ff00ff,$ff644280,$102eff63 + dc.l $4a016608,$61ff0000,$4e686030,$0c010001 + dc.l $660861ff,$00006d74,$60220c01,$00026608 + dc.l $61ff0000,$6d946014,$0c010003,$660861ff + dc.l $00006b9c,$600661ff,$00004f14,$4cee0303 + dc.l $ff9cf22e,$9800ff60,$f22ed040,$ffe84e5e + dc.l $4e754e56,$ff4048ee,$0303ff9c,$f22eb800 + dc.l $ff60f22e,$f0c0ffdc,$f23c9000,$00000000 + dc.l $f22e5400,$0008f22e,$6800ff6c,$41eeff6c + dc.l $61ff0000,$682c1d40,$ff4e1200,$02ae00ff + dc.l $00ffff64,$4280102e,$ff631d41,$ff4e4a01 + dc.l $660861ff,$00004dca,$60300c01,$00016608 + dc.l $61ff0000,$6cd66022,$0c010002,$660861ff + dc.l $00006cf6,$60140c01,$00036608,$61ff0000 + dc.l $6afe6006,$61ff0000,$4e764cee,$0303ff9c + dc.l $f22e9800,$ff60f22e,$d040ffe8,$4e5e4e75 + dc.l $4e56ff40,$48ee0303,$ff9cf22e,$b800ff60 + dc.l $f22ef0c0,$ffdcf23c,$90000000,$000041ee + dc.l $ff6c216e,$00080000,$216e000c,$0004216e + dc.l $00100008,$61ff0000,$67881d40,$ff4e1200 + dc.l $02ae00ff,$00ffff64,$4280102e,$ff634a01 + dc.l $660861ff,$00004d2a,$60300c01,$00016608 + dc.l $61ff0000,$6c366022,$0c010002,$660861ff + dc.l $00006c56,$60140c01,$00036608,$61ff0000 + dc.l $6a5e6006,$61ff0000,$4dd64cee,$0303ff9c + dc.l $f22e9800,$ff60f22e,$d040ffe8,$4e5e4e75 + dc.l $4e56ff40,$48ee0303,$ff9cf22e,$b800ff60 + dc.l $f22ef0c0,$ffdcf23c,$90000000,$0000f22e + dc.l $44000008,$f22e6800,$ff6c41ee,$ff6c61ff + dc.l $000066ee,$1d40ff4e,$120002ae,$00ff00ff + dc.l $ff644280,$102eff63,$4a016608,$61ff0000 + dc.l $59b26030,$0c010001,$660861ff,$00006b9c + dc.l $60220c01,$00026608,$61ff0000,$6bf26014 + dc.l $0c010003,$660861ff,$000069c4,$600661ff + dc.l $00005ad4,$4cee0303,$ff9cf22e,$9800ff60 + dc.l $f22ed040,$ffe84e5e,$4e754e56,$ff4048ee + dc.l $0303ff9c,$f22eb800,$ff60f22e,$f0c0ffdc + dc.l $f23c9000,$00000000,$f22e5400,$0008f22e + dc.l $6800ff6c,$41eeff6c,$61ff0000,$66541d40 + dc.l $ff4e1200,$02ae00ff,$00ffff64,$4280102e + dc.l $ff631d41,$ff4e4a01,$660861ff,$00005914 + dc.l $60300c01,$00016608,$61ff0000,$6afe6022 + dc.l $0c010002,$660861ff,$00006b54,$60140c01 + dc.l $00036608,$61ff0000,$69266006,$61ff0000 + dc.l $5a364cee,$0303ff9c,$f22e9800,$ff60f22e + dc.l $d040ffe8,$4e5e4e75,$4e56ff40,$48ee0303 + dc.l $ff9cf22e,$b800ff60,$f22ef0c0,$ffdcf23c + dc.l $90000000,$000041ee,$ff6c216e,$00080000 + dc.l $216e000c,$0004216e,$00100008,$61ff0000 + dc.l $65b01d40,$ff4e1200,$02ae00ff,$00ffff64 + dc.l $4280102e,$ff634a01,$660861ff,$00005874 + dc.l $60300c01,$00016608,$61ff0000,$6a5e6022 + dc.l $0c010002,$660861ff,$00006ab4,$60140c01 + dc.l $00036608,$61ff0000,$68866006,$61ff0000 + dc.l $59964cee,$0303ff9c,$f22e9800,$ff60f22e + dc.l $d040ffe8,$4e5e4e75,$4e56ff40,$48ee0303 + dc.l $ff9cf22e,$b800ff60,$f22ef0c0,$ffdcf23c + dc.l $90000000,$0000f22e,$44000008,$f22e6800 + dc.l $ff6c41ee,$ff6c61ff,$00006516,$1d40ff4e + dc.l $120002ae,$00ff00ff,$ff644280,$102eff63 + dc.l $4a016608,$61ff0000,$46c46030,$0c010001 + dc.l $660861ff,$000069c4,$60220c01,$00026608 + dc.l $61ff0000,$6a246014,$0c010003,$660861ff + dc.l $000067ec,$600661ff,$00004948,$4cee0303 + dc.l $ff9cf22e,$9800ff60,$f22ed040,$ffe84e5e + dc.l $4e754e56,$ff4048ee,$0303ff9c,$f22eb800 + dc.l $ff60f22e,$f0c0ffdc,$f23c9000,$00000000 + dc.l $f22e5400,$0008f22e,$6800ff6c,$41eeff6c + dc.l $61ff0000,$647c1d40,$ff4e1200,$02ae00ff + dc.l $00ffff64,$4280102e,$ff631d41,$ff4e4a01 + dc.l $660861ff,$00004626,$60300c01,$00016608 + dc.l $61ff0000,$69266022,$0c010002,$660861ff + dc.l $00006986,$60140c01,$00036608,$61ff0000 + dc.l $674e6006,$61ff0000,$48aa4cee,$0303ff9c + dc.l $f22e9800,$ff60f22e,$d040ffe8,$4e5e4e75 + dc.l $4e56ff40,$48ee0303,$ff9cf22e,$b800ff60 + dc.l $f22ef0c0,$ffdcf23c,$90000000,$000041ee + dc.l $ff6c216e,$00080000,$216e000c,$0004216e + dc.l $00100008,$61ff0000,$63d81d40,$ff4e1200 + dc.l $02ae00ff,$00ffff64,$4280102e,$ff634a01 + dc.l $660861ff,$00004586,$60300c01,$00016608 + dc.l $61ff0000,$68866022,$0c010002,$660861ff + dc.l $000068e6,$60140c01,$00036608,$61ff0000 + dc.l $66ae6006,$61ff0000,$480a4cee,$0303ff9c + dc.l $f22e9800,$ff60f22e,$d040ffe8,$4e5e4e75 + dc.l $4e56ff40,$48ee0303,$ff9cf22e,$b800ff60 + dc.l $f22ef0c0,$ffdcf23c,$90000000,$0000f22e + dc.l $44000008,$f22e6800,$ff6c41ee,$ff6c61ff + dc.l $0000633e,$1d40ff4e,$120002ae,$00ff00ff + dc.l $ff644280,$102eff63,$4a016608,$61ff0000 + dc.l $49c46030,$0c010001,$660861ff,$000067ec + dc.l $60220c01,$00026608,$61ff0000,$68546014 + dc.l $0c010003,$660861ff,$00006614,$600661ff + dc.l $00004afa,$4cee0303,$ff9cf22e,$9800ff60 + dc.l $f22ed040,$ffe84e5e,$4e754e56,$ff4048ee + dc.l $0303ff9c,$f22eb800,$ff60f22e,$f0c0ffdc + dc.l $f23c9000,$00000000,$f22e5400,$0008f22e + dc.l $6800ff6c,$41eeff6c,$61ff0000,$62a41d40 + dc.l $ff4e1200,$02ae00ff,$00ffff64,$4280102e + dc.l $ff631d41,$ff4e4a01,$660861ff,$00004926 + dc.l $60300c01,$00016608,$61ff0000,$674e6022 + dc.l $0c010002,$660861ff,$000067b6,$60140c01 + dc.l $00036608,$61ff0000,$65766006,$61ff0000 + dc.l $4a5c4cee,$0303ff9c,$f22e9800,$ff60f22e + dc.l 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All rights reserved. + +THE SOFTWARE is provided on an "AS IS" basis and without warranty. +To the maximum extent permitted by applicable law, +MOTOROLA DISCLAIMS ALL WARRANTIES WHETHER EXPRESS OR IMPLIED, +INCLUDING IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE +and any warranty against infringement with regard to the SOFTWARE +(INCLUDING ANY MODIFIED VERSIONS THEREOF) and any accompanying written materials. + +To the maximum extent permitted by applicable law, +IN NO EVENT SHALL MOTOROLA BE LIABLE FOR ANY DAMAGES WHATSOEVER +(INCLUDING WITHOUT LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, +BUSINESS INTERRUPTION, LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY LOSS) +ARISING OF THE USE OR INABILITY TO USE THE SOFTWARE. +Motorola assumes no responsibility for the maintenance and support of the SOFTWARE. + +You are hereby granted a copyright license to use, modify, and distribute the SOFTWARE +so long as this entire notice is retained without alteration in any modified and/or +redistributed versions, and that such modified versions are clearly identified as such. +No licenses are granted by implication, estoppel or otherwise under any patents +or trademarks of Motorola, Inc. +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +68060 FLOATING-POINT SOFTWARE PACKAGE (Kernel version) +------------------------------------------------------- + +The file fpsp.sa contains the 68060 Floating-Point Software +Package. This package is essentially a set of exception handlers +that can be integrated into an operating system. +These exception handlers emulate Unimplemented FP instructions, +instructions using unimplemented data types, and instructions +using unimplemented addressing modes. In addition, this package +includes exception handlers to provide full IEEE-754 compliant +exception handling. + +Release file format: +-------------------- +The file fpsp.sa is essentially a hexadecimal image of the +release package. This is the ONLY format which will be supported. +The hex image was created by assembling the source code and +then converting the resulting binary output image into an +ASCII text file. The hexadecimal numbers are listed +using the Motorola Assembly Syntax assembler directive "dc.l" +(define constant longword). The file can be converted to other +assembly syntaxes by using any word processor with a global +search and replace function. + +To assist in assembling and linking this module with other modules, +the installer should add a symbolic label to the top of the file. +This will allow calling routines to access the entry points +of this package. + +The source code fpsp.s has also been included but only for +documentation purposes. + +Release file structure: +----------------------- + +(top of module) + ----------------- + | | - 128 byte-sized section + (1) | Call-Out | - 4 bytes per entry (user fills these in) + | | - example routines in fskeleton.s + ----------------- + | | - 8 bytes per entry + (2) | Entry Point | - user does "bra" or "jmp" to this address + | | + ----------------- + | | - code section + (3) ~ ~ + | | + ----------------- +(bottom of module) + +The first section of this module is the "Call-out" section. This section +is NOT INCLUDED in fpsp.sa (an example "Call-out" section is provided at +the end of the file fskeleton.s). The purpose of this section is to allow +the FPSP routines to reference external functions that must be provided +by the host operating system. This section MUST be exactly 128 bytes in +size. There are 32 fields, each 4 bytes in size. Each field corresponds +to a function required by the FPSP (these functions and their location are +listed in "68060FPSP call-outs" below). Each field entry should contain +the address of the corresponding function RELATIVE to the starting address +of the "call-out" section. The "Call-out" section must sit adjacent to the +fpsp.sa image in memory. + +The second section, the "Entry-point" section, is used by external routines +to access the functions within the FPSP. Since the fpsp.sa hex file contains +no symbol names, this section contains function entry points that are fixed +with respect to the top of the package. The currently defined entry-points +are listed in section "68060 FPSP entry points" below. A calling routine +would simply execute a "bra" or "jmp" that jumped to the selected function +entry-point. + +For example, if the 68060 hardware took a "Line-F Emulator" exception +(vector #11), the operating system should execute something similar to: + + bra _060FPSP_TOP+128+48 + +(_060FPSP_TOP is the starting address of the "Call-out" section; the "Call-out" +section is 128 bytes long; and the F-Line FPSP handler entry point is located +48 bytes from the top of the "Entry-point" section.) + +The third section is the code section. After entering through an "Entry-point", +the entry code jumps to the appropriate emulation code within the code section. + +68060FPSP call-outs: (details in fskeleton.s) +-------------------- +0x000: _060_real_bsun +0x004: _060_real_snan +0x008: _060_real_operr +0x00c: _060_real_ovfl +0x010: _060_real_unfl +0x014: _060_real_dz +0x018: _060_real_inex +0x01c: _060_real_fline +0x020: _060_real_fpu_disabled +0x024: _060_real_trap +0x028: _060_real_trace +0x02c: _060_real_access +0x030: _060_fpsp_done + +0x034: (Motorola reserved) +0x038: (Motorola reserved) +0x03c: (Motorola reserved) + +0x040: _060_imem_read +0x044: _060_dmem_read +0x048: _060_dmem_write +0x04c: _060_imem_read_word +0x050: _060_imem_read_long +0x054: _060_dmem_read_byte +0x058: _060_dmem_read_word +0x05c: _060_dmem_read_long +0x060: _060_dmem_write_byte +0x064: _060_dmem_write_word +0x068: _060_dmem_write_long + +0x06c: (Motorola reserved) +0x070: (Motorola reserved) +0x074: (Motorola reserved) +0x078: (Motorola reserved) +0x07c: (Motorola reserved) + +68060FPSP entry points: +----------------------- +0x000: _060_fpsp_snan +0x008: _060_fpsp_operr +0x010: _060_fpsp_ovfl +0x018: _060_fpsp_unfl +0x020: _060_fpsp_dz +0x028: _060_fpsp_inex +0x030: _060_fpsp_fline +0x038: _060_fpsp_unsupp +0x040: _060_fpsp_effadd + + + +Miscellaneous: +-------------- + +_060_fpsp_snan: +---------------- +- documented in 3.5 of 060SP spec. +- Basic flow: + exception taken ---> enter _060_fpsp_snan --| + | + always exits through _060_real_snan <---- + +_060_fpsp_operr: +---------------- +- documented in 3.5 of 060SP spec. +- Basic flow: + exception taken ---> enter _060_fpsp_operr --| + | + always exits through _060_real_operr <----- + +_060_fpsp_dz: +---------------- +- documented in 3.7 of 060SP spec. +- Basic flow: + exception taken ---> enter _060_fpsp_dz --| + | + always exits through _060_real_dz <---- + +_060_fpsp_inex: +---------------- +- documented in 3.6 of 060SP spec. +- Basic flow: + exception taken ---> enter _060_fpsp_inex --| + | + always exits through _060_real_inex <---- + + +_060_fpsp_ovfl: +---------------- +- documented in 3.4 of 060SP spec. +- Basic flow: + exception taken ---> enter _060_fpsp_ovfl --| + | + may exit through _060_real_inex <---| + or | + may exit through _060_real_ovfl <---| + or | + may exit through _060_fpsp_done <---| + +_060_fpsp_unfl: +---------------- +- documented in 3.4 of 060SP spec. +- Basic flow: + exception taken ---> enter _060_fpsp_unfl --| + | + may exit through _060_real_inex <---| + or | + may exit through _060_real_unfl <---| + or | + may exit through _060_fpsp_done <---| + + +_060_fpsp_fline: +----------------- +- not fully documented in 060SP spec. +- Basic flow: + exception taken ---> enter _060_fpsp_fline --| + | + ------------------------------------------- + | | | + v v v + (unimplemented (fpu disabled) (possible F-line illegal) + stack frame) | v + | v special case "fmovecr"? + | exit through | + | _060_real_fpu_disabled ------------- + | | | + | ^ v v + | | (yes) (no) + | | v v + | | fpu disabled? exit through + | | | _060_real_fline + v | ------------- + | | | | + | | v v + | |-----------(yes) (no) + | | + |----<------------------------------------| + | + | + |----> may exit through _060_real_trace + | + |----> may exit through _060_real_trap + | + |----> may exit through _060_real_bsun + | + |----> may exit through _060_fpsp_done + + +_060_fpsp_unsupp: +------------------ +- documented in 3.1 of 060SP spec. +- Basic flow: + exception taken ---> enter _060_fpsp_unsupp --| + | + | + may exit through _060_real_snan <----| + or | + may exit through _060_real_operr <----| + or | + may exit through _060_real_ovfl <----| + or | + may exit through _060_real_unfl <----| + or | + may exit through _060_real_inex <----| + or | + may exit through _060_real_trace <----| + or | + may exit through _060_fpsp_done <----| + + +_060_fpsp_effadd: +------------------ +- documented in 3.3 of 060 spec. +- Basic flow: + exception taken ---> enter _060_fpsp_effadd --| + | + | + may exit through _060_real_trace <----| + or | + may exit through _060_real_fpu_disabled <----| + or | + may exit through _060_fpsp_done <----| diff --git a/arch/m68k/ifpsp060/fpsp.sa b/arch/m68k/ifpsp060/fpsp.sa new file mode 100644 index 000000000..d69486a44 --- /dev/null +++ b/arch/m68k/ifpsp060/fpsp.sa @@ -0,0 +1,3401 @@ + .long 0x60ff0000,0x17400000,0x60ff0000,0x15f40000 + .long 0x60ff0000,0x02b60000,0x60ff0000,0x04700000 + .long 0x60ff0000,0x1b100000,0x60ff0000,0x19aa0000 + .long 0x60ff0000,0x1b5a0000,0x60ff0000,0x062e0000 + .long 0x60ff0000,0x102c0000,0x51fc51fc,0x51fc51fc + .long 0x51fc51fc,0x51fc51fc,0x51fc51fc,0x51fc51fc + .long 0x51fc51fc,0x51fc51fc,0x51fc51fc,0x51fc51fc + .long 0x51fc51fc,0x51fc51fc,0x51fc51fc,0x51fc51fc + .long 0x2f00203a,0xff2c487b,0x0930ffff,0xfef8202f + .long 0x00044e74,0x00042f00,0x203afef2,0x487b0930 + .long 0xfffffee2,0x202f0004,0x4e740004,0x2f00203a + .long 0xfee0487b,0x0930ffff,0xfecc202f,0x00044e74 + .long 0x00042f00,0x203afed2,0x487b0930,0xfffffeb6 + .long 0x202f0004,0x4e740004,0x2f00203a,0xfea4487b + .long 0x0930ffff,0xfea0202f,0x00044e74,0x00042f00 + .long 0x203afe96,0x487b0930,0xfffffe8a,0x202f0004 + .long 0x4e740004,0x2f00203a,0xfe7c487b,0x0930ffff + .long 0xfe74202f,0x00044e74,0x00042f00,0x203afe76 + .long 0x487b0930,0xfffffe5e,0x202f0004,0x4e740004 + .long 0x2f00203a,0xfe68487b,0x0930ffff,0xfe48202f + .long 0x00044e74,0x00042f00,0x203afe56,0x487b0930 + .long 0xfffffe32,0x202f0004,0x4e740004,0x2f00203a + .long 0xfe44487b,0x0930ffff,0xfe1c202f,0x00044e74 + .long 0x00042f00,0x203afe32,0x487b0930,0xfffffe06 + .long 0x202f0004,0x4e740004,0x2f00203a,0xfe20487b + .long 0x0930ffff,0xfdf0202f,0x00044e74,0x00042f00 + .long 0x203afe1e,0x487b0930,0xfffffdda,0x202f0004 + .long 0x4e740004,0x2f00203a,0xfe0c487b,0x0930ffff + .long 0xfdc4202f,0x00044e74,0x00042f00,0x203afdfa + .long 0x487b0930,0xfffffdae,0x202f0004,0x4e740004 + .long 0x2f00203a,0xfde8487b,0x0930ffff,0xfd98202f + .long 0x00044e74,0x00042f00,0x203afdd6,0x487b0930 + .long 0xfffffd82,0x202f0004,0x4e740004,0x2f00203a + .long 0xfdc4487b,0x0930ffff,0xfd6c202f,0x00044e74 + .long 0x00042f00,0x203afdb2,0x487b0930,0xfffffd56 + .long 0x202f0004,0x4e740004,0x2f00203a,0xfda0487b + .long 0x0930ffff,0xfd40202f,0x00044e74,0x00042f00 + .long 0x203afd8e,0x487b0930,0xfffffd2a,0x202f0004 + .long 0x4e740004,0x2f00203a,0xfd7c487b,0x0930ffff + .long 0xfd14202f,0x00044e74,0x00042f00,0x203afd6a + .long 0x487b0930,0xfffffcfe,0x202f0004,0x4e740004 + .long 0x40c62d38,0xd3d64634,0x3d6f90ae,0xb1e75cc7 + .long 0x40000000,0xc90fdaa2,0x2168c235,0x00000000 + .long 0x3fff0000,0xc90fdaa2,0x2168c235,0x00000000 + .long 0x3fe45f30,0x6dc9c883,0x4e56ff40,0xf32eff6c + .long 0x48ee0303,0xff9cf22e,0xbc00ff60,0xf22ef0c0 + .long 0xffdc2d6e,0xff68ff44,0x206eff44,0x58aeff44 + .long 0x61ffffff,0xff042d40,0xff40082e,0x0005ff42 + .long 0x66000116,0x41eeff6c,0x61ff0000,0x051c41ee + .long 0xff6c61ff,0x0000c1dc,0x1d40ff4e,0x082e0005 + .long 0xff436726,0xe9ee0183,0xff4261ff,0x0000bd22 + .long 0x41eeff78,0x61ff0000,0xc1ba0c00,0x00066606 + .long 0x61ff0000,0xc11e1d40,0xff4f4280,0x102eff63 + .long 0x122eff43,0x0241007f,0x02ae00ff,0x01ffff64 + .long 0xf23c9000,0x00000000,0xf23c8800,0x00000000 + .long 0x41eeff6c,0x43eeff78,0x223b1530,0x00007112 + .long 0x4ebb1930,0x0000710a,0xe9ee0183,0xff4261ff + .long 0x0000bd4e,0x082e0004,0xff626622,0x082e0001 + .long 0xff626644,0xf22ed0c0,0xffdcf22e,0x9c00ff60 + .long 0x4cee0303,0xff9c4e5e,0x60ffffff,0xfcc6f22e + .long 0xf040ff6c,0x3d7ce005,0xff6ef22e,0xd0c0ffdc + .long 0xf22e9c00,0xff604cee,0x0303ff9c,0xf36eff6c + .long 0x4e5e60ff,0xfffffcb2,0xf22ef040,0xff6c1d7c + .long 0x00c4000b,0x3d7ce001,0xff6ef22e,0xd0c0ffdc + .long 0xf22e9c00,0xff604cee,0x0303ff9c,0xf36eff6c + .long 0x4e5e60ff,0xfffffcae,0x1d7c0000,0xff4e4280 + .long 0x102eff63,0x02aeffff,0x00ffff64,0xf23c9000 + .long 0x00000000,0xf23c8800,0x00000000,0x41eeff6c + .long 0x61ff0000,0xb2ce082e,0x0004ff62,0x6600ff70 + .long 0x082e0001,0xff626600,0xff90f22e,0xd0c0ffdc + .long 0xf22e9c00,0xff604cee,0x0303ff9c,0x4e5e0817 + .long 0x000767ff,0xfffffc0c,0xf22fa400,0x00083f7c + .long 0x20240006,0x60ffffff,0xfcec4e56,0xff40f32e + .long 0xff6c48ee,0x0303ff9c,0xf22ebc00,0xff60f22e + .long 0xf0c0ffdc,0x2d6eff68,0xff44206e,0xff4458ae + .long 0xff4461ff,0xfffffd42,0x2d40ff40,0x082e0005 + .long 0xff426600,0x013241ee,0xff6c61ff,0x0000035a + .long 0x41eeff6c,0x61ff0000,0xc01a1d40,0xff4e082e + .long 0x0005ff43,0x672e082e,0x0004ff43,0x6626e9ee + .long 0x0183ff42,0x61ff0000,0xbb5841ee,0xff7861ff + .long 0x0000bff0,0x0c000006,0x660661ff,0x0000bf54 + .long 0x1d40ff4f,0x4280102e,0xff63122e,0xff430241 + .long 0x007f02ae,0x00ff01ff,0xff64f23c,0x90000000 + .long 0x0000f23c,0x88000000,0x000041ee,0xff6c43ee + .long 0xff78223b,0x15300000,0x6f484ebb,0x19300000 + .long 0x6f40e9ee,0x0183ff42,0x61ff0000,0xbb84082e + .long 0x0003ff62,0x6622082e,0x0001ff62,0x664ef22e + .long 0xd0c0ffdc,0xf22e9c00,0xff604cee,0x0303ff9c + .long 0x4e5e60ff,0xfffffafc,0x082e0003,0xff666700 + .long 0xffd6f22e,0xf040ff6c,0x3d7ce003,0xff6ef22e + .long 0xd0c0ffdc,0xf22e9c00,0xff604cee,0x0303ff9c + .long 0xf36eff6c,0x4e5e60ff,0xfffffaf4,0x082e0001 + .long 0xff666700,0xffaaf22e,0xf040ff6c,0x1d7c00c4 + .long 0x000b3d7c,0xe001ff6e,0xf22ed0c0,0xffdcf22e + .long 0x9c00ff60,0x4cee0303,0xff9cf36e,0xff6c4e5e + .long 0x60ffffff,0xfad01d7c,0x0000ff4e,0x4280102e + .long 0xff6302ae,0xffff00ff,0xff64f23c,0x90000000 + .long 0x0000f23c,0x88000000,0x000041ee,0xff6c61ff + .long 0x0000b0f0,0x082e0003,0xff626600,0xff66082e + .long 0x0001ff62,0x6600ff90,0xf22ed0c0,0xffdcf22e + .long 0x9c00ff60,0x4cee0303,0xff9c4e5e,0x08170007 + .long 0x67ffffff,0xfa2ef22f,0xa4000008,0x3f7c2024 + .long 0x000660ff,0xfffffb0e,0x4e56ff40,0xf32eff6c + .long 0x48ee0303,0xff9cf22e,0xbc00ff60,0xf22ef0c0 + .long 0xffdc082e,0x00050004,0x66084e68,0x2d48ffd8 + .long 0x600841ee,0x00102d48,0xffd82d6e,0xff68ff44 + .long 0x206eff44,0x58aeff44,0x61ffffff,0xfb4c2d40 + .long 0xff40422e,0xff4a082e,0x0005ff42,0x66000208 + .long 0xe9ee0006,0xff420c00,0x00136700,0x049e02ae + .long 0x00ff00ff,0xff64f23c,0x90000000,0x0000f23c + .long 0x88000000,0x000041ee,0xff6c61ff,0x0000013a + .long 0x41eeff6c,0x61ff0000,0xbdfa0c00,0x00066606 + .long 0x61ff0000,0xbd5e1d40,0xff4ee9ee,0x0183ff42 + .long 0x082e0005,0xff436728,0x0c2e003a,0xff436720 + .long 0x61ff0000,0xb92c41ee,0xff7861ff,0x0000bdc4 + .long 0x0c000006,0x660661ff,0x0000bd28,0x1d40ff4f + .long 0x4280102e,0xff63e9ee,0x1047ff43,0x41eeff6c + .long 0x43eeff78,0x223b1d30,0x00006d36,0x4ebb1930 + .long 0x00006d2e,0x102eff62,0x6634102e,0xff430200 + .long 0x00380c00,0x0038670c,0xe9ee0183,0xff4261ff + .long 0x0000b95e,0xf22ed0c0,0xffdcf22e,0x9c00ff60 + .long 0x4cee0303,0xff9c4e5e,0x60ffffff,0xf8e6c02e + .long 0xff66edc0,0x06086614,0x082e0004,0xff6667ba + .long 0x082e0001,0xff6267b2,0x60000066,0x04800000 + .long 0x00180c00,0x00066614,0x082e0003,0xff666600 + .long 0x004a082e,0x0004ff66,0x66000046,0x2f0061ff + .long 0x000007e0,0x201f3d7b,0x0222ff6e,0xf22ed0c0 + .long 0xffdcf22e,0x9c00ff60,0x4cee0303,0xff9cf36e + .long 0xff6c4e5e,0x60ffffff,0xf87ae000,0xe006e004 + .long 0xe005e003,0xe002e001,0xe001303c,0x000460bc + .long 0x303c0003,0x60b6e9ee,0x0006ff42,0x0c000011 + .long 0x67080c00,0x00156750,0x4e753028,0x00000240 + .long 0x7fff0c40,0x3f806708,0x0c40407f,0x672c4e75 + .long 0x02a87fff,0xffff0004,0x671861ff,0x0000bbbc + .long 0x44400640,0x3f810268,0x80000000,0x81680000 + .long 0x4e750268,0x80000000,0x4e750228,0x007f0004 + .long 0x00687fff,0x00004e75,0x30280000,0x02407fff + .long 0x0c403c00,0x67080c40,0x43ff67de,0x4e7502a8 + .long 0x7fffffff,0x00046606,0x4aa80008,0x67c461ff + .long 0x0000bb68,0x44400640,0x3c010268,0x80000000 + .long 0x81680000,0x4e75e9ee,0x00c3ff42,0x0c000003 + .long 0x670004a2,0x0c000007,0x6700049a,0x02aeffff + .long 0x00ffff64,0xf23c9000,0x00000000,0xf23c8800 + .long 0x00000000,0x302eff6c,0x02407fff,0x671041ee + .long 0xff6c61ff,0x0000bb5c,0x1d40ff4e,0x60061d7c + .long 0x0004ff4e,0x4280102e,0xff6341ee,0xff6c2d56 + .long 0xffd461ff,0x0000adec,0x102eff62,0x66000086 + .long 0x2caeffd4,0x082e0005,0x00046626,0x206effd8 + .long 0x4e60f22e,0xd0c0ffdc,0xf22e9c00,0xff604cee + .long 0x0303ff9c,0x4e5e0817,0x0007667a,0x60ffffff + .long 0xf7220c2e,0x0008ff4a,0x66d8f22e,0xf080ff6c + .long 0xf22ed0c0,0xffdcf22e,0x9c00ff60,0x4cee0303 + .long 0xff9c2c56,0x2f6f00c4,0x00b82f6f,0x00c800bc + .long 0x2f6f002c,0x00c42f6f,0x003000c8,0x2f6f0034 + .long 0x00ccdffc,0x000000b8,0x08170007,0x662860ff + .long 0xfffff6d0,0xc02eff66,0xedc00608,0x662a082e + .long 0x0004ff66,0x6700ff6a,0x082e0001,0xff626700 + .long 0xff606000,0x01663f7c,0x20240006,0xf22fa400 + .long 0x000860ff,0xfffff78e,0x04800000,0x0018303b + .long 0x020a4efb,0x00064afc,0x00080000,0x0000003a + .long 0x00640094,0x00000140,0x0000f22e,0xd0c0ffdc + .long 0xf22e9c00,0xff604cee,0x0303ff9c,0x3d7c30d8 + .long 0x000a3d7c,0xe006ff6e,0xf36eff6c,0x4e5e60ff + .long 0xfffff6d4,0xf22ed0c0,0xffdcf22e,0x9c00ff60 + .long 0x4cee0303,0xff9c3d7c,0x30d0000a,0x3d7ce004 + .long 0xff6ef36e,0xff6c4e5e,0x60ffffff,0xf694f22e + .long 0xf040ff6c,0xf22ed0c0,0xffdcf22e,0x9c00ff60 + .long 0x4cee0303,0xff9c3d7c,0x30d4000a,0x3d7ce005 + .long 0xff6ef36e,0xff6c4e5e,0x60ffffff,0xf60c2cae + .long 0xffd4082e,0x00050004,0x66000038,0x206effd8 + .long 0x4e60f22e,0xf040ff6c,0xf22ed0c0,0xffdcf22e + .long 0x9c00ff60,0x4cee0303,0xff9c3d7c,0x30cc000a + .long 0x3d7ce003,0xff6ef36e,0xff6c4e5e,0x60ffffff + .long 0xf5de0c2e,0x0008ff4a,0x66c8f22e,0xf080ff6c + .long 0xf22ef040,0xff78f22e,0xd0c0ffdc,0xf22e9c00 + .long 0xff604cee,0x0303ff9c,0x3d7c30cc,0x000a3d7c + .long 0xe003ff7a,0xf36eff78,0x2c562f6f,0x00c400b8 + .long 0x2f6f00c8,0x00bc2f6f,0x00cc00c0,0x2f6f002c + .long 0x00c42f6f,0x003000c8,0x2f6f0034,0x00ccdffc + .long 0x000000b8,0x60ffffff,0xf576f22e,0xf040ff6c + .long 0xf22ed0c0,0xffdcf22e,0x9c00ff60,0x4cee0303 + .long 0xff9c3d7c,0x30c4000a,0x3d7ce001,0xff6ef36e + .long 0xff6c4e5e,0x60ffffff,0xf55c02ae,0x00ff00ff + .long 0xff64f23c,0x90000000,0x0000f23c,0x88000000 + .long 0x000061ff,0x0000bdba,0x41eeff6c,0x61ff0000 + .long 0xb9621d40,0xff4ee9ee,0x0183ff42,0x082e0005 + .long 0xff436728,0x0c2e003a,0xff436720,0x61ff0000 + .long 0xb4a041ee,0xff7861ff,0x0000b938,0x0c000006 + .long 0x660661ff,0x0000b89c,0x1d40ff4f,0x4280102e + .long 0xff63e9ee,0x1047ff43,0x41eeff6c,0x43eeff78 + .long 0x223b1d30,0x000068aa,0x4ebb1930,0x000068a2 + .long 0x102eff62,0x6600008a,0x102eff43,0x02000038 + .long 0x0c000038,0x670ce9ee,0x0183ff42,0x61ff0000 + .long 0xb4d0082e,0x00050004,0x6600002a,0x206effd8 + .long 0x4e60f22e,0xd0c0ffdc,0xf22e9c00,0xff604cee + .long 0x0303ff9c,0x4e5e0817,0x00076600,0x012660ff + .long 0xfffff440,0x082e0002,0xff4a67d6,0xf22ed0c0 + .long 0xffdcf22e,0x9c00ff60,0x4cee0303,0xff9c4e5e + .long 0x2f6f0004,0x00102f6f,0x0000000c,0xdffc0000 + .long 0x000c0817,0x00076600,0x00ea60ff,0xfffff404 + .long 0xc02eff66,0xedc00608,0x6618082e,0x0004ff66 + .long 0x6700ff66,0x082e0001,0xff626700,0xff5c6000 + .long 0x006e0480,0x00000018,0x0c000006,0x6d14082e + .long 0x0003ff66,0x66000060,0x082e0004,0xff666600 + .long 0x004e082e,0x00050004,0x66000054,0x206effd8 + .long 0x4e603d7b,0x022aff6e,0xf22ed0c0,0xffdcf22e + .long 0x9c00ff60,0x4cee0303,0xff9cf36e,0xff6c4e5e + .long 0x08170007,0x6600006c,0x60ffffff,0xf386e000 + .long 0xe006e004,0xe005e003,0xe002e001,0xe001303c + .long 0x00036000,0xffae303c,0x00046000,0xffa6082e + .long 0x0002ff4a,0x67ac3d7b,0x02d6ff6e,0xf22ed0c0 + .long 0xffdcf22e,0x9c00ff60,0x4cee0303,0xff9cf36e + .long 0xff6c4e5e,0x2f6f0004,0x00102f6f,0x0000000c + .long 0xdffc0000,0x000c0817,0x00076606,0x60ffffff + .long 0xf3223f7c,0x20240006,0xf22fa400,0x000860ff + .long 0xfffff402,0x02aeffff,0x00ffff64,0xf23c9000 + .long 0x00000000,0xf23c8800,0x00000000,0xe9ee0183 + .long 0xff4261ff,0x0000b22a,0x41eeff6c,0x61ff0000 + .long 0xb7520c00,0x00066606,0x61ff0000,0xb6b61d40 + .long 0xff4e4280,0x102eff63,0x41eeff6c,0x2d56ffd4 + .long 0x61ff0000,0xa94e102e,0xff626600,0x00842cae + .long 0xffd4082e,0x00050004,0x6628206e,0xffd84e60 + .long 0xf22ed0c0,0xffdcf22e,0x9c00ff60,0x4cee0303 + .long 0xff9c4e5e,0x08170007,0x6600ff68,0x60ffffff + .long 0xf282082e,0x0003ff4a,0x67d6f22e,0xd0c0ffdc + .long 0xf22e9c00,0xff604cee,0x0303ff9c,0x2c562f6f + .long 0x00c400b8,0x2f6f00c8,0x00bc2f6f,0x003800c4 + .long 0x2f6f003c,0x00c82f6f,0x004000cc,0xdffc0000 + .long 0x00b80817,0x00076600,0xff1a60ff,0xfffff234 + .long 0xc02eff66,0xedc00608,0x6700ff74,0x2caeffd4 + .long 0x0c00001a,0x6e0000e8,0x67000072,0x082e0005 + .long 0x0004660a,0x206effd8,0x4e606000,0xfb8e0c2e + .long 0x0008ff4a,0x6600fb84,0xf22ed0c0,0xffdcf22e + .long 0x9c00ff60,0x4cee0303,0xff9c3d7c,0x30d8000a + .long 0x3d7ce006,0xff6ef36e,0xff6c2c56,0x2f6f00c4 + .long 0x00b82f6f,0x00c800bc,0x2f6f00cc,0x00c02f6f + .long 0x003800c4,0x2f6f003c,0x00c82f6f,0x004000cc + .long 0xdffc0000,0x00b860ff,0xfffff22c,0x082e0005 + .long 0x00046600,0x000c206e,0xffd84e60,0x6000fb46 + .long 0x0c2e0008,0xff4a6600,0xfb3cf22e,0xd0c0ffdc + .long 0xf22e9c00,0xff604cee,0x0303ff9c,0x3d7c30d0 + .long 0x000a3d7c,0xe004ff6e,0xf36eff6c,0x2c562f6f + .long 0x00c400b8,0x2f6f00c8,0x00bc2f6f,0x00cc00c0 + .long 0x2f6f0038,0x00c42f6f,0x003c00c8,0x2f6f0040 + .long 0x00ccdffc,0x000000b8,0x60ffffff,0xf1a4082e + .long 0x00050004,0x6600000c,0x206effd8,0x4e606000 + .long 0xfbda0c2e,0x0008ff4a,0x6600fbd0,0xf22ed0c0 + .long 0xffdcf22e,0x9c00ff60,0x4cee0303,0xff9c3d7c + .long 0x30c4000a,0x3d7ce001,0xff6ef36e,0xff6c2c56 + .long 0x2f6f00c4,0x00b82f6f,0x00c800bc,0x2f6f00cc + .long 0x00c02f6f,0x003800c4,0x2f6f003c,0x00c82f6f + .long 0x004000cc,0xdffc0000,0x00b860ff,0xfffff106 + .long 0xe9ee00c3,0xff420c00,0x00016708,0x0c000005 + .long 0x67344e75,0x302eff6c,0x02407fff,0x67260c40 + .long 0x3f806e20,0x44400640,0x3f81222e,0xff70e0a9 + .long 0x08c1001f,0x2d41ff70,0x026e8000,0xff6c006e + .long 0x3f80ff6c,0x4e75302e,0xff6c0240,0x7fff673a + .long 0x0c403c00,0x6e344a2e,0xff6c5bee,0xff6e3d40 + .long 0xff6c4280,0x41eeff6c,0x323c3c01,0x61ff0000 + .long 0xb156303c,0x3c004a2e,0xff6e6704,0x08c0000f + .long 0x08ee0007,0xff703d40,0xff6c4e75,0x082e0005 + .long 0x000467ff,0xfffff176,0x2d680000,0xff782d68 + .long 0x0004ff7c,0x2d680008,0xff804281,0x4e752f00 + .long 0x4e7a0808,0x08000001,0x66000460,0x201f4e56 + .long 0xff4048ee,0x0303ff9c,0xf22ebc00,0xff60f22e + .long 0xf0c0ffdc,0x2d6e0006,0xff44206e,0xff4458ae + .long 0xff4461ff,0xfffff152,0x2d40ff40,0x4a406b00 + .long 0x020e02ae,0x00ff00ff,0xff640800,0x000a6618 + .long 0x206eff44,0x43eeff6c,0x700c61ff,0xfffff0d2 + .long 0x4a816600,0x04926048,0x206eff44,0x43eeff6c + .long 0x700c61ff,0xfffff0ba,0x4a816600,0x047ae9ee + .long 0x004fff6c,0x0c407fff,0x6726102e,0xff6f0200 + .long 0x000f660c,0x4aaeff70,0x66064aae,0xff746710 + .long 0x41eeff6c,0x61ff0000,0xb88cf22e,0xf080ff6c + .long 0x06ae0000,0x000cff44,0x41eeff6c,0x61ff0000 + .long 0xb3c21d40,0xff4e0c00,0x0006660a,0x61ff0000 + .long 0xb3221d40,0xff4e422e,0xff53082e,0x0005ff43 + .long 0x6748082e,0x0004ff43,0x662ce9ee,0x0183ff42 + .long 0x61ff0000,0xaeec41ee,0xff7861ff,0x0000b384 + .long 0x1d40ff4f,0x0c000006,0x662061ff,0x0000b2e4 + .long 0x1d40ff4f,0x6014082e,0x0003ff43,0x670c50ee + .long 0xff53082e,0x0001ff43,0x67c04280,0x102eff63 + .long 0x122eff43,0x0241007f,0xf23c9000,0x00000000 + .long 0xf23c8800,0x00000000,0x41eeff6c,0x43eeff78 + .long 0x223b1530,0x000062ca,0x4ebb1930,0x000062c2 + .long 0x102eff62,0x66404a2e,0xff53660c,0xe9ee0183 + .long 0xff4261ff,0x0000aefa,0x2d6e0006,0xff682d6e + .long 0xff440006,0xf22ed0c0,0xffdcf22e,0x9c00ff60 + .long 0x4cee0303,0xff9c4e5e,0x08170007,0x66000096 + .long 0x60ffffff,0xee6ec02e,0xff66edc0,0x06086612 + .long 0x082e0004,0xff6667ae,0x082e0001,0xff6267ac + .long 0x60340480,0x00000018,0x0c000006,0x6610082e + .long 0x0004ff66,0x6620082e,0x0003ff66,0x66203d7b + .long 0x0206ff6e,0x601ee002,0xe006e004,0xe005e003 + .long 0xe002e001,0xe0013d7c,0xe005ff6e,0x60063d7c + .long 0xe003ff6e,0x2d6e0006,0xff682d6e,0xff440006 + .long 0xf22ed0c0,0xffdcf22e,0x9c00ff60,0x4cee0303 + .long 0xff9cf36e,0xff6c4e5e,0x08170007,0x660660ff + .long 0xffffede0,0x2f173f6f,0x00080004,0x3f7c2024 + .long 0x0006f22f,0xa4000008,0x60ffffff,0xeeb80800 + .long 0x000e6700,0x01c2082e,0x00050004,0x66164e68 + .long 0x2d48ffd8,0x61ff0000,0x9564206e,0xffd84e60 + .long 0x600001aa,0x422eff4a,0x41ee000c,0x2d48ffd8 + .long 0x61ff0000,0x95480c2e,0x0008ff4a,0x67000086 + .long 0x0c2e0004,0xff4a6600,0x0184082e,0x00070004 + .long 0x66363dae,0x00040804,0x2daeff44,0x08063dbc + .long 0x00f0080a,0x41f60804,0x2d480004,0xf22ed0c0 + .long 0xffdcf22e,0x9c00ff60,0x4cee0303,0xff9c4e5e + .long 0x2e5f60ff,0xffffed3c,0x3dae0004,0x08002dae + .long 0xff440802,0x3dbc2024,0x08062dae,0x00060808 + .long 0x41f60800,0x2d480004,0xf22ed0c0,0xffdcf22e + .long 0x9c00ff60,0x4cee0303,0xff9c4e5e,0x2e5f60ff + .long 0xffffedf2,0x1d41000a,0x1d40000b,0xf22ed0c0 + .long 0xffdcf22e,0x9c00ff60,0x4cee0303,0xff9c2f16 + .long 0x2f002f01,0x2f2eff44,0x4280102e,0x000b4480 + .long 0x082e0007,0x0004671c,0x3dae0004,0x08002dae + .long 0x00060808,0x2d9f0802,0x3dbc2024,0x08064876 + .long 0x08006014,0x3dae0004,0x08042d9f,0x08063dbc + .long 0x00f0080a,0x48760804,0x4281122e,0x000a4a01 + .long 0x6a0cf236,0xf080080c,0x06800000,0x000ce309 + .long 0x6a0cf236,0xf040080c,0x06800000,0x000ce309 + .long 0x6a0cf236,0xf020080c,0x06800000,0x000ce309 + .long 0x6a0cf236,0xf010080c,0x06800000,0x000ce309 + .long 0x6a0cf236,0xf008080c,0x06800000,0x000ce309 + .long 0x6a0cf236,0xf004080c,0x06800000,0x000ce309 + .long 0x6a0cf236,0xf002080c,0x06800000,0x000ce309 + .long 0x6a06f236,0xf001080c,0x222f0004,0x202f0008 + .long 0x2c6f000c,0x2e5f0817,0x000767ff,0xffffec04 + .long 0x60ffffff,0xecf061ff,0x00009bda,0xf22ed0c0 + .long 0xffdcf22e,0x9c00ff60,0x4cee0303,0xff9c082e + .long 0x00070004,0x660e2d6e,0xff440006,0x4e5e60ff + .long 0xffffebd0,0x2c563f6f,0x00c400c0,0x2f6f00c6 + .long 0x00c82f6f,0x000400c2,0x3f7c2024,0x00c6dffc + .long 0x000000c0,0x60ffffff,0xec9c201f,0x4e56ff40 + .long 0x48ee0303,0xff9c2d6e,0x0006ff44,0x206eff44 + .long 0x58aeff44,0x61ffffff,0xed002d40,0xff404a40 + .long 0x6b047010,0x60260800,0x000e6610,0xe9c014c3 + .long 0x700c0c01,0x00076614,0x58806010,0x428061ff + .long 0x0000967c,0x202eff44,0x90ae0006,0x3d40000a + .long 0x4cee0303,0xff9c4e5e,0x518f2f00,0x3f6f000c + .long 0x00042f6f,0x000e0006,0x4280302f,0x00122f6f + .long 0x00060010,0xd1af0006,0x3f7c402c,0x000a201f + .long 0x60ffffff,0xebe44e7a,0x08080800,0x0001660c + .long 0xf22e9c00,0xff60f22e,0xd0c0ffdc,0x4cee0303 + .long 0xff9c4e5e,0x514f2eaf,0x00083f6f,0x000c0004 + .long 0x3f7c4008,0x00062f6f,0x00020008,0x2f7c0942 + .long 0x8001000c,0x08170005,0x670608ef,0x0002000d + .long 0x60ffffff,0xebd64fee,0xff404e7a,0x18080801 + .long 0x0001660c,0xf22ed0c0,0xffdcf22f,0x9c000020 + .long 0x2c562f6f,0x00c400bc,0x3f6f00c8,0x00c03f7c + .long 0x400800c2,0x2f4800c4,0x3f4000c8,0x3f7c0001 + .long 0x00ca4cef,0x0303005c,0xdefc00bc,0x60a64e56 + .long 0xff40f32e,0xff6c48ee,0x0303ff9c,0xf22ebc00 + .long 0xff60f22e,0xf0c0ffdc,0x2d6eff68,0xff44206e + .long 0xff4458ae,0xff4461ff,0xffffebce,0x2d40ff40 + .long 0x0800000d,0x662841ee,0xff6c61ff,0xfffff1ea + .long 0xf22ed0c0,0xffdcf22e,0x9c00ff60,0x4cee0303 + .long 0xff9cf36e,0xff6c4e5e,0x60ffffff,0xea94322e + .long 0xff6c0241,0x7fff0c41,0x7fff661a,0x4aaeff74 + .long 0x660c222e,0xff700281,0x7fffffff,0x67082d6e + .long 0xff70ff54,0x6012223c,0x7fffffff,0x4a2eff6c + .long 0x6a025281,0x2d41ff54,0xe9c004c3,0x122eff41 + .long 0x307b0206,0x4efb8802,0x006c0000,0x0000ff98 + .long 0x003e0000,0x00100000,0x102eff54,0x0c010007 + .long 0x6f16206e,0x000c61ff,0xffffeb86,0x4a8166ff + .long 0x0000bca8,0x6000ff6a,0x02410007,0x61ff0000 + .long 0xa8046000,0xff5c302e,0xff540c01,0x00076f16 + .long 0x206e000c,0x61ffffff,0xeb6e4a81,0x66ff0000 + .long 0xbc886000,0xff3c0241,0x000761ff,0x0000a79a + .long 0x6000ff2e,0x202eff54,0x0c010007,0x6f16206e + .long 0x000c61ff,0xffffeb56,0x4a8166ff,0x0000bc68 + .long 0x6000ff0e,0x02410007,0x61ff0000,0xa7306000 + .long 0xff004e56,0xff40f32e,0xff6c48ee,0x0303ff9c + .long 0xf22ebc00,0xff60f22e,0xf0c0ffdc,0x2d6eff68 + .long 0xff44206e,0xff4458ae,0xff4461ff,0xffffea8a + .long 0x2d40ff40,0x0800000d,0x6600002a,0x41eeff6c + .long 0x61ffffff,0xf0a4f22e,0xd0c0ffdc,0xf22e9c00 + .long 0xff604cee,0x0303ff9c,0xf36eff6c,0x4e5e60ff + .long 0xffffe964,0xe9c004c3,0x122eff41,0x307b0206 + .long 0x4efb8802,0x007400a6,0x015a0000,0x00420104 + .long 0x00100000,0x102eff70,0x08c00006,0x0c010007 + .long 0x6f16206e,0x000c61ff,0xffffea76,0x4a8166ff + .long 0x0000bb98,0x6000ffa0,0x02410007,0x61ff0000 + .long 0xa6f46000,0xff92302e,0xff7008c0,0x000e0c01 + .long 0x00076f16,0x206e000c,0x61ffffff,0xea5a4a81 + .long 0x66ff0000,0xbb746000,0xff6e0241,0x000761ff + .long 0x0000a686,0x6000ff60,0x202eff70,0x08c0001e + .long 0x0c010007,0x6f16206e,0x000c61ff,0xffffea3e + .long 0x4a8166ff,0x0000bb50,0x6000ff3c,0x02410007 + .long 0x61ff0000,0xa6186000,0xff2e0c01,0x00076f2e + .long 0x202eff6c,0x02808000,0x00000080,0x7fc00000 + .long 0x222eff70,0xe0898081,0x206e000c,0x61ffffff + .long 0xe9fc4a81,0x66ff0000,0xbb0e6000,0xfefa202e + .long 0xff6c0280,0x80000000,0x00807fc0,0x00002f01 + .long 0x222eff70,0xe0898081,0x221f0241,0x000761ff + .long 0x0000a5ba,0x6000fed0,0x202eff6c,0x02808000 + .long 0x00000080,0x7ff80000,0x222eff70,0x2d40ff84 + .long 0x700be0a9,0x83aeff84,0x222eff70,0x02810000 + .long 0x07ffe0b9,0x2d41ff88,0x222eff74,0xe0a983ae + .long 0xff8841ee,0xff84226e,0x000c7008,0x61ffffff + .long 0xe8cc4a81,0x66ff0000,0xba9c6000,0xfe7a422e + .long 0xff4a3d6e,0xff6cff84,0x426eff86,0x202eff70 + .long 0x08c0001e,0x2d40ff88,0x2d6eff74,0xff8c082e + .long 0x00050004,0x66384e68,0x2d48ffd8,0x2d56ffd4 + .long 0x61ff0000,0x98922248,0x2d48000c,0x206effd8 + .long 0x4e602cae,0xffd441ee,0xff84700c,0x61ffffff + .long 0xe86c4a81,0x66ff0000,0xba4a6000,0xfe1a2d56 + .long 0xffd461ff,0x00009860,0x22482d48,0x000c2cae + .long 0xffd40c2e,0x0008ff4a,0x66ccf22e,0xd0c0ffdc + .long 0xf22e9c00,0xff604cee,0x0303ff9c,0xf36eff6c + .long 0x2c6effd4,0x2f6f00c4,0x00b82f6f,0x00c800bc + .long 0x2f6f00cc,0x00c02f6f,0x004400c4,0x2f6f0048 + .long 0x00c82f6f,0x004c00cc,0xdffc0000,0x00b860ff + .long 0xffffe734,0x4e56ff40,0xf32eff6c,0x48ee0303 + .long 0xff9cf22e,0xbc00ff60,0xf22ef0c0,0xffdc2d6e + .long 0xff68ff44,0x206eff44,0x58aeff44,0x61ffffff + .long 0xe7f82d40,0xff400800,0x000d6600,0x0106e9c0 + .long 0x04c36622,0x0c6e401e,0xff6c661a,0xf23c9000 + .long 0x00000000,0xf22e4000,0xff70f22e,0x6800ff6c + .long 0x3d7ce001,0xff6e41ee,0xff6c61ff,0xffffedea + .long 0x02ae00ff,0x01ffff64,0xf23c9000,0x00000000 + .long 0xf23c8800,0x00000000,0xe9ee1006,0xff420c01 + .long 0x00176700,0x009641ee,0xff6c61ff,0x0000aa84 + .long 0x1d40ff4e,0x082e0005,0xff43672e,0x082e0004 + .long 0xff436626,0xe9ee0183,0xff4261ff,0x0000a5c2 + .long 0x41eeff78,0x61ff0000,0xaa5a0c00,0x00066606 + .long 0x61ff0000,0xa9be1d40,0xff4f4280,0x102eff63 + .long 0x122eff43,0x0241007f,0x41eeff6c,0x43eeff78 + .long 0x223b1530,0x000059ca,0x4ebb1930,0x000059c2 + .long 0xe9ee0183,0xff4261ff,0x0000a606,0xf22ed0c0 + .long 0xffdcf22e,0x9c00ff60,0x4cee0303,0xff9cf36e + .long 0xff6c4e5e,0x60ffffff,0xe5cc4280,0x102eff63 + .long 0x122eff43,0x02810000,0x007f61ff,0x000043ce + .long 0x60be1d7c,0x0000ff4e,0x4280102e,0xff6302ae + .long 0xffff00ff,0xff6441ee,0xff6c61ff,0x00009be4 + .long 0x60aa4e56,0xff40f32e,0xff6c48ee,0x0303ff9c + .long 0xf22ebc00,0xff60f22e,0xf0c0ffdc,0x2d6eff68 + .long 0xff44206e,0xff4458ae,0xff4461ff,0xffffe69a + .long 0x2d40ff40,0x41eeff6c,0x61ffffff,0xecbcf22e + .long 0xd0c0ffdc,0xf22e9c00,0xff604cee,0x0303ff9c + .long 0xf36eff6c,0x4e5e60ff,0xffffe592,0x0c6f202c + .long 0x000667ff,0x000000aa,0x0c6f402c,0x000667ff + .long 0xffffe5a6,0x4e56ff40,0x48ee0303,0xff9c2d6e + .long 0x0006ff44,0x206eff44,0x58aeff44,0x61ffffff + .long 0xe638e9c0,0x100a0c41,0x03c86664,0xe9c01406 + .long 0x0c010017,0x665a4e7a,0x08080800,0x0001672a + .long 0x4cee0303,0xff9c4e5e,0x518f3eaf,0x00082f6f + .long 0x000a0002,0x3f7c402c,0x00062f6f,0x0002000c + .long 0x58af0002,0x60ffffff,0xe5404cee,0x0303ff9c + .long 0x4e5ef22f,0x84000002,0x58af0002,0x2f172f6f + .long 0x00080004,0x1f7c0020,0x000660ff,0x00000012 + .long 0x4cee0303,0xff9c4e5e,0x60ffffff,0xe4f64e56 + .long 0xff4048ee,0x0303ff9c,0xf22ebc00,0xff60f22e + .long 0xf0c0ffdc,0x082e0005,0x00046608,0x4e682d48 + .long 0xffd8600c,0x41ee0010,0x2d48ffd8,0x2d48ffd4 + .long 0x2d6eff68,0xff44206e,0xff4458ae,0xff4461ff + .long 0xffffe576,0x2d40ff40,0xf23c9000,0x00000000 + .long 0xf23c8800,0x00000000,0x422eff4a,0x08000016 + .long 0x66000182,0x422eff53,0x02ae00ff,0x00ffff64 + .long 0xe9c01406,0x0c010017,0x670000be,0x61ff0000 + .long 0x95fc4280,0x102eff63,0x122eff43,0x0241003f + .long 0xe749822e,0xff4e43ee,0xff7841ee,0xff6c323b + .long 0x132002b2,0x4ebb1120,0x02ac102e,0xff626600 + .long 0x00a2e9ee,0x0183ff42,0x61ff0000,0xa3e4f22e + .long 0xd0c0ffdc,0xf22e9c00,0xff604cee,0x0303ff9c + .long 0x0c2e0004,0xff4a672a,0x0c2e0008,0xff4a6722 + .long 0x4e5e0817,0x000767ff,0xffffe358,0xf327f22f + .long 0xa4000014,0xf35f3f7c,0x20240006,0x60ffffff + .long 0xe434082e,0x00050004,0x660c2f08,0x206effd8 + .long 0x4e60205f,0x60ca2f00,0x202effd8,0x90aeffd4 + .long 0x2dae0008,0x08082dae,0x00040804,0x3d400004 + .long 0x201f4e5e,0xded760aa,0x4280102e,0xff63122e + .long 0xff430281,0x0000007f,0x61ff0000,0x41506000 + .long 0xff5ac02e,0xff66edc0,0x06086616,0x082e0004 + .long 0xff666700,0xff4e082e,0x0001ff62,0x6700ff44 + .long 0x603e0480,0x00000018,0x0c000006,0x6610082e + .long 0x0004ff66,0x662a082e,0x0003ff66,0x66302f00 + .long 0x61ffffff,0xf1ee201f,0x3d7b0206,0xff6e602a + .long 0xe002e006,0xe004e005,0xe003e002,0xe001e001 + .long 0x61ffffff,0xf1ce3d7c,0xe005ff6e,0x600c61ff + .long 0xfffff1c0,0x3d7ce003,0xff6ef22e,0xd0c0ffdc + .long 0xf22e9c00,0xff604cee,0x0303ff9c,0xf36eff6c + .long 0x6000feee,0xe9c01283,0x0c010001,0x67000056 + .long 0x0c010007,0x66000078,0xe9c01343,0x0c010002 + .long 0x6d00006c,0x61ff0000,0x82780c2e,0x0002ff4a + .long 0x670000d2,0x0c2e0001,0xff4a6600,0x01002d6e + .long 0xff68000c,0x3d7c201c,0x000af22e,0xd0c0ffdc + .long 0xf22e9c00,0xff604cee,0x0303ff9c,0x4e5e60ff + .long 0xffffe2dc,0x206eff44,0x54aeff44,0x61ffffff + .long 0xe3524a81,0x6600047c,0x48c061ff,0x00007e60 + .long 0x0c2e0002,0xff4a6700,0x007c6000,0x00b061ff + .long 0x00008562,0x0c2e0002,0xff4a6700,0x0068082e + .long 0x00050004,0x660a206e,0xffd84e60,0x6000008e + .long 0x0c2e0008,0xff4a6600,0x0084f22e,0xd0c0ffdc + .long 0xf22e9c00,0xff604cee,0x0303ff9c,0x4e5e0817 + .long 0x00076612,0x558f2eaf,0x00022f6f,0x00060004 + .long 0x60ffffff,0xe17e558f,0x2eaf0002,0x3f6f0006 + .long 0x00043f7c,0x20240006,0xf22fa400,0x000860ff + .long 0xffffe252,0x3d7c00c0,0x000e2d6e,0xff68000a + .long 0x3d6e0004,0x00083d7c,0xe000ff6e,0xf22ed0c0 + .long 0xffdcf22e,0x9c00ff60,0x4cee0303,0xff9cf36e + .long 0xff6c4e5e,0x588f60ff,0xffffe180,0xf22ed0c0 + .long 0xffdcf22e,0x9c00ff60,0x4cee0303,0xff9c4e5e + .long 0x08170007,0x660660ff,0xffffe108,0xf22fa400 + .long 0x00081f7c,0x00240007,0x60ffffff,0xe1e84afc + .long 0x01c00000,0x00000000,0x00000000,0x00000000 + .long 0x00000000,0x00000000,0x00000000,0x00000000 + .long 0x000028a4,0x4b1e4b4c,0x4f4c2982,0x4f3c0000 + .long 0x00000000,0x00000000,0x00000000,0x00000000 + .long 0x00000000,0x00000000,0x00000000,0x00000000 + .long 0x00000000,0x00000000,0x00000000,0x00000000 + .long 0x000035c6,0x4b1e4b82,0x4f4c371a,0x4f3c0000 + .long 0x00000000,0x00000000,0x00000000,0x00000000 + .long 0x000024b0,0x4b1e4b8c,0x4f4c2766,0x4f3c0000 + .long 0x00002988,0x4b1e4b94,0x4f4c2af0,0x4f3c0000 + .long 0x00001ab8,0x4b1e4bd0,0x4f4c1cf6,0x4f3c0000 + .long 0x00000000,0x00000000,0x00000000,0x00000000 + .long 0x00001cfc,0x4b1e4744,0x4f4c1daa,0x4f3c0000 + .long 0x00003720,0x4b1e4744,0x4f4c37a2,0x4f3c0000 + .long 0x00000468,0x4b1e4744,0x4f4c064c,0x4f3c0000 + .long 0x00000f2a,0x4b1e4744,0x4f4c108e,0x4f3c0000 + .long 0x000022e0,0x4b9a4b7a,0x4f4c248c,0x4f3c0000 + .long 0x00003d02,0x4b9a4b7a,0x4f4c3ddc,0x4f3c0000 + .long 0x00003dfa,0x4b9a4b7a,0x4f4c3f2a,0x4f3c0000 + .long 0x00000000,0x00000000,0x00000000,0x00000000 + .long 0x00003386,0x47324b82,0x4f4c3538,0x4f3c0000 + .long 0x000037c8,0x47324b82,0x4f4c37f8,0x4f3c0000 + .long 0x00003818,0x47324b82,0x4f4c3872,0x4f3c0000 + .long 0x00000000,0x00000000,0x00000000,0x00000000 + .long 0x00000000,0x00000000,0x00000000,0x00000000 + .long 0x000027e6,0x4b9a4b52,0x4f4c288a,0x4f3c0000 + .long 0x00000000,0x00000000,0x00000000,0x00000000 + .long 0x00000000,0x00000000,0x00000000,0x00000000 + .long 0x00001db0,0x4bd64744,0x4f4c1e40,0x4f3c0000 + .long 0x00000472,0x4b9a4744,0x4f4c0652,0x4f3c0000 + .long 0x0000276c,0x4b1e4744,0x4f4c2788,0x4f3c0000 + .long 0x000027a0,0x4b1e4744,0x4f4c27ce,0x4f3c0000 + .long 0x00000000,0x00000000,0x00000000,0x00000000 + .long 0x00004ca4,0x4cda4d12,0x4ee24ca4,0x4ef40000 + .long 0x00000000,0x00000000,0x00000000,0x00000000 + .long 0x00000000,0x00000000,0x00000000,0x00000000 + .long 0x00000000,0x00000000,0x00000000,0x00000000 + .long 0x00004dac,0x4de24e1a,0x4ee24dac,0x4ef40000 + .long 0x00004e4e,0x4e864ebe,0x4ee24e4e,0x4ef40000 + .long 0x00000000,0x00000000,0x00000000,0x00000000 + .long 0x00000000,0x00000000,0x00000000,0x00000000 + .long 0x00000000,0x00000000,0x00000000,0x00000000 + .long 0x00000000,0x00000000,0x00000000,0x00000000 + .long 0x00000000,0x00000000,0x00000000,0x00000000 + .long 0x00000000,0x00000000,0x00000000,0x00000000 + .long 0x00000000,0x00000000,0x00000000,0x00000000 + .long 0x00000000,0x00000000,0x00000000,0x00000000 + .long 0x00000000,0x00000000,0x00000000,0x00000000 + .long 0x00000660,0x4bf24c20,0x4c3008f6,0x4c400000 + .long 0x00000660,0x4bf24c20,0x4c3008f6,0x4c400000 + .long 0x00000660,0x4bf24c20,0x4c3008f6,0x4c400000 + .long 0x00000660,0x4bf24c20,0x4c3008f6,0x4c400000 + .long 0x00000660,0x4bf24c20,0x4c3008f6,0x4c400000 + .long 0x00000660,0x4bf24c20,0x4c3008f6,0x4c400000 + .long 0x00000660,0x4bf24c20,0x4c3008f6,0x4c400000 + .long 0x00000660,0x4bf24c20,0x4c3008f6,0x4c400000 + .long 0x00004cee,0x0303ff9c,0xf22e9c00,0xff60f22e + .long 0xd0c0ffdc,0x2d6eff68,0x00064e5e,0x2f173f6f + .long 0x00080004,0x3f7c4008,0x00062f6f,0x00020008 + .long 0x2f7c0942,0x8001000c,0x08170005,0x670608ef + .long 0x0002000d,0x60ffffff,0xde32bd6a,0xaa77ccc9 + .long 0x94f53de6,0x12097aae,0x8da1be5a,0xe6452a11 + .long 0x8ae43ec7,0x1de3a534,0x1531bf2a,0x01a01a01 + .long 0x8b590000,0x00000000,0x00003ff8,0x00008888 + .long 0x88888888,0x59af0000,0x0000bffc,0x0000aaaa + .long 0xaaaaaaaa,0xaa990000,0x00003d2a,0xc4d0d601 + .long 0x1ee3bda9,0x396f9f45,0xac193e21,0xeed90612 + .long 0xc972be92,0x7e4fb79d,0x9fcf3efa,0x01a01a01 + .long 0xd4230000,0x00000000,0x0000bff5,0x0000b60b + .long 0x60b60b61,0xd4380000,0x00003ffa,0x0000aaaa + .long 0xaaaaaaaa,0xab5ebf00,0x00002d7c,0x00000000 + .long 0xff5c6008,0x2d7c0000,0x0001ff5c,0xf2104800 + .long 0xf22e6800,0xff842210,0x32280004,0x02817fff + .long 0xffff0c81,0x3fd78000,0x6c046000,0x01780c81 + .long 0x4004bc7e,0x6d046000,0x0468f200,0x0080f23a + .long 0x54a3de7e,0x43fb0170,0x00000866,0xf22e6080 + .long 0xff58222e,0xff58e981,0xd3c1f219,0x4828f211 + .long 0x4428222e,0xff58d2ae,0xff5ce299,0x0c810000 + .long 0x00006d00,0x0088f227,0xe00cf22e,0x6800ff84 + .long 0xf2000023,0xf23a5580,0xfed2f23a,0x5500fed4 + .long 0xf2000080,0xf20004a3,0xe2990281,0x80000000 + .long 0xb3aeff84,0xf20005a3,0xf2000523,0xf23a55a2 + .long 0xfebaf23a,0x5522febc,0xf20005a3,0xf2000523 + .long 0xf23a55a2,0xfeb6f23a,0x4922fec0,0xf2000ca3 + .long 0xf2000123,0xf23a48a2,0xfec2f22e,0x4823ff84 + .long 0xf20008a2,0xf2000423,0xf21fd030,0xf2009000 + .long 0xf22e4822,0xff8460ff,0x00004364,0xf227e00c + .long 0xf2000023,0xf23a5500,0xfea2f23a,0x5580fea4 + .long 0xf2000080,0xf20004a3,0xf22e6800,0xff84e299 + .long 0x02818000,0x0000f200,0x0523b3ae,0xff840281 + .long 0x80000000,0xf20005a3,0x00813f80,0x00002d41 + .long 0xff54f23a,0x5522fe74,0xf23a55a2,0xfe76f200 + .long 0x0523f200,0x05a3f23a,0x5522fe70,0xf23a49a2 + .long 0xfe7af200,0x0523f200,0x0ca3f23a,0x4922fe7c + .long 0xf23a44a2,0xfe82f200,0x0823f200,0x0422f22e + .long 0x4823ff84,0xf21fd030,0xf2009000,0xf22e4422 + .long 0xff5460ff,0x000042c8,0x0c813fff,0x80006eff + .long 0x00000300,0x222eff5c,0x0c810000,0x00006e14 + .long 0xf2009000,0x123c0003,0xf22e4800,0xff8460ff + .long 0x0000428e,0xf23c4400,0x3f800000,0xf2009000 + .long 0xf23c4422,0x80800000,0x60ff0000,0x428a60ff + .long 0x00004110,0xf23c4400,0x3f800000,0x60ff0000 + .long 0x42762d7c,0x00000004,0xff5cf210,0x4800f22e + .long 0x6800ff84,0x22103228,0x00040281,0x7fffffff + .long 0x0c813fd7,0x80006c04,0x60000240,0x0c814004 + .long 0xbc7e6d04,0x6000027a,0xf2000080,0xf23a54a3 + .long 0xdc9043fb,0x01700000,0x0678f22e,0x6080ff58 + .long 0x222eff58,0xe981d3c1,0xf2194828,0xf2114428 + .long 0x222eff58,0xe2990c81,0x00000000,0x6c000106 + .long 0xf227e004,0xf22e6800,0xff84f200,0x0023f23a + .long 0x5480fce8,0xf23a5500,0xfd32f200,0x00a3f200 + .long 0x01232f02,0x2401e29a,0x02828000,0x0000b382 + .long 0x02828000,0x0000f23a,0x54a2fcc8,0xf23a5522 + .long 0xfd12f200,0x00a3b5ae,0xff84241f,0xf2000123 + .long 0xe2990281,0x80000000,0x2d7c3f80,0x0000ff54 + .long 0xb3aeff54,0xf23a54a2,0xfca2f23a,0x5522fcec + .long 0xf20000a3,0xf2000123,0xf22e6800,0xff90f23a + .long 0x54a2fc90,0xb3aeff90,0xf23a5522,0xfcd6f200 + .long 0x00a3f200,0x0123f23a,0x54a2fc80,0xf23a5522 + .long 0xfccaf200,0x00a3f200,0x0123f23a,0x48a2fc7c + .long 0xf23a4922,0xfcc6f200,0x00a3f200,0x0123f23a + .long 0x48a2fc78,0xf23a4922,0xfcc2f200,0x00a3f200 + .long 0x0823f22e,0x48a3ff84,0xf23a4422,0xfcbaf22e + .long 0x4823ff90,0xf21fd020,0xf2009000,0xf22e48a2 + .long 0xff8461ff,0x0000448e,0xf22e4422,0xff5460ff + .long 0x000040fc,0xf227e004,0xf22e6800,0xff84f200 + .long 0x0023f23a,0x5480fc34,0xf23a5500,0xfbdef200 + .long 0x00a3f22e,0x6800ff90,0xf2000123,0xe2990281 + .long 0x80000000,0xf23a54a2,0xfc1af23a,0x5522fbc4 + .long 0xb3aeff84,0xb3aeff90,0xf20000a3,0x00813f80 + .long 0x00002d41,0xff54f200,0x0123f23a,0x54a2fbfc + .long 0xf23a5522,0xfba6f200,0x00a3f200,0x0123f23a + .long 0x54a2fbf0,0xf23a5522,0xfb9af200,0x00a3f200 + .long 0x0123f23a,0x54a2fbe4,0xf23a5522,0xfb8ef200 + .long 0x00a3f200,0x0123f23a,0x48a2fbe0,0xf23a4922 + .long 0xfb8af200,0x00a3f200,0x0123f23a,0x48a2fbdc + .long 0xf23a4922,0xfb86f200,0x00a3f200,0x0823f23a + .long 0x44a2fbd4,0xf22e4823,0xff84f22e,0x48a3ff90 + .long 0xf21fd020,0xf2009000,0xf22e44a2,0xff5461ff + .long 0x000043a2,0xf22e4822,0xff8460ff,0x00004010 + .long 0x0c813fff,0x80006e00,0x0048f23c,0x44803f80 + .long 0x0000f200,0x9000f23c,0x44a80080,0x000061ff + .long 0x00004372,0xf200b000,0x123c0003,0xf22e4800 + .long 0xff8460ff,0x00003fca,0x2f00f23c,0x44803f80 + .long 0x000061ff,0x0000434e,0x201f60ff,0x00003e54 + .long 0xf227e03c,0x2f02f23c,0x44800000,0x00000c81 + .long 0x7ffeffff,0x66523d7c,0x7ffeff84,0x2d7cc90f + .long 0xdaa2ff88,0x42aeff8c,0x3d7c7fdc,0xff902d7c + .long 0x85a308d3,0xff9442ae,0xff98f200,0x003af294 + .long 0x000e002e,0x0080ff84,0x002e0080,0xff90f22e + .long 0x4822ff84,0xf2000080,0xf22e4822,0xff90f200 + .long 0x00a8f22e,0x48a2ff90,0xf22e6800,0xff84322e + .long 0xff842241,0x02810000,0x7fff0481,0x00003fff + .long 0x0c810000,0x001c6f0e,0x04810000,0x001b1d7c + .long 0x0000ff58,0x60084281,0x1d7c0001,0xff58243c + .long 0x00003ffe,0x94812d7c,0xa2f9836e,0xff882d7c + .long 0x4e44152a,0xff8c3d42,0xff84f200,0x0100f22e + .long 0x4923ff84,0x24094842,0x02828000,0x00000082 + .long 0x5f000000,0x2d42ff54,0xf22e4522,0xff54f22e + .long 0x4528ff54,0x24010682,0x00003fff,0x3d42ff84 + .long 0x2d7cc90f,0xdaa2ff88,0x42aeff8c,0x06810000 + .long 0x3fdd3d41,0xff902d7c,0x85a308d3,0xff9442ae + .long 0xff98122e,0xff58f200,0x0a00f22e,0x4a23ff84 + .long 0xf2000a80,0xf22e4aa3,0xff90f200,0x1180f200 + .long 0x15a2f200,0x0e28f200,0x0c28f200,0x1622f200 + .long 0x0180f200,0x10a8f200,0x04220c01,0x00006e00 + .long 0x000ef200,0x01a8f200,0x0ca26000,0xff0cf22e + .long 0x6100ff58,0x241ff21f,0xd03c222e,0xff5c0c81 + .long 0x00000004,0x6d00fa4c,0x6000fc36,0x3ea0b759 + .long 0xf50f8688,0xbef2baa5,0xa8924f04,0xbf346f59 + .long 0xb39ba65f,0x00000000,0x00000000,0x3ff60000 + .long 0xe073d3fc,0x199c4a00,0x00000000,0x3ff90000 + .long 0xd23cd684,0x15d95fa1,0x00000000,0xbffc0000 + .long 0x8895a6c5,0xfb423bca,0x00000000,0xbffd0000 + .long 0xeef57e0d,0xa84bc8ce,0x00000000,0x3ffc0000 + .long 0xa2f9836e,0x4e44152a,0x00000000,0x40010000 + .long 0xc90fdaa2,0x00000000,0x00000000,0x3fdf0000 + .long 0x85a308d4,0x00000000,0x00000000,0xc0040000 + .long 0xc90fdaa2,0x2168c235,0x21800000,0xc0040000 + .long 0xc2c75bcd,0x105d7c23,0xa0d00000,0xc0040000 + .long 0xbc7edcf7,0xff523611,0xa1e80000,0xc0040000 + .long 0xb6365e22,0xee46f000,0x21480000,0xc0040000 + .long 0xafeddf4d,0xdd3ba9ee,0xa1200000,0xc0040000 + .long 0xa9a56078,0xcc3063dd,0x21fc0000,0xc0040000 + .long 0xa35ce1a3,0xbb251dcb,0x21100000,0xc0040000 + .long 0x9d1462ce,0xaa19d7b9,0xa1580000,0xc0040000 + .long 0x96cbe3f9,0x990e91a8,0x21e00000,0xc0040000 + .long 0x90836524,0x88034b96,0x20b00000,0xc0040000 + .long 0x8a3ae64f,0x76f80584,0xa1880000,0xc0040000 + .long 0x83f2677a,0x65ecbf73,0x21c40000,0xc0030000 + .long 0xfb53d14a,0xa9c2f2c2,0x20000000,0xc0030000 + .long 0xeec2d3a0,0x87ac669f,0x21380000,0xc0030000 + .long 0xe231d5f6,0x6595da7b,0xa1300000,0xc0030000 + .long 0xd5a0d84c,0x437f4e58,0x9fc00000,0xc0030000 + .long 0xc90fdaa2,0x2168c235,0x21000000,0xc0030000 + .long 0xbc7edcf7,0xff523611,0xa1680000,0xc0030000 + .long 0xafeddf4d,0xdd3ba9ee,0xa0a00000,0xc0030000 + .long 0xa35ce1a3,0xbb251dcb,0x20900000,0xc0030000 + .long 0x96cbe3f9,0x990e91a8,0x21600000,0xc0030000 + .long 0x8a3ae64f,0x76f80584,0xa1080000,0xc0020000 + .long 0xfb53d14a,0xa9c2f2c2,0x1f800000,0xc0020000 + .long 0xe231d5f6,0x6595da7b,0xa0b00000,0xc0020000 + .long 0xc90fdaa2,0x2168c235,0x20800000,0xc0020000 + .long 0xafeddf4d,0xdd3ba9ee,0xa0200000,0xc0020000 + .long 0x96cbe3f9,0x990e91a8,0x20e00000,0xc0010000 + .long 0xfb53d14a,0xa9c2f2c2,0x1f000000,0xc0010000 + .long 0xc90fdaa2,0x2168c235,0x20000000,0xc0010000 + .long 0x96cbe3f9,0x990e91a8,0x20600000,0xc0000000 + .long 0xc90fdaa2,0x2168c235,0x1f800000,0xbfff0000 + .long 0xc90fdaa2,0x2168c235,0x1f000000,0x00000000 + .long 0x00000000,0x00000000,0x00000000,0x3fff0000 + .long 0xc90fdaa2,0x2168c235,0x9f000000,0x40000000 + .long 0xc90fdaa2,0x2168c235,0x9f800000,0x40010000 + .long 0x96cbe3f9,0x990e91a8,0xa0600000,0x40010000 + .long 0xc90fdaa2,0x2168c235,0xa0000000,0x40010000 + .long 0xfb53d14a,0xa9c2f2c2,0x9f000000,0x40020000 + .long 0x96cbe3f9,0x990e91a8,0xa0e00000,0x40020000 + .long 0xafeddf4d,0xdd3ba9ee,0x20200000,0x40020000 + .long 0xc90fdaa2,0x2168c235,0xa0800000,0x40020000 + .long 0xe231d5f6,0x6595da7b,0x20b00000,0x40020000 + .long 0xfb53d14a,0xa9c2f2c2,0x9f800000,0x40030000 + .long 0x8a3ae64f,0x76f80584,0x21080000,0x40030000 + .long 0x96cbe3f9,0x990e91a8,0xa1600000,0x40030000 + .long 0xa35ce1a3,0xbb251dcb,0xa0900000,0x40030000 + .long 0xafeddf4d,0xdd3ba9ee,0x20a00000,0x40030000 + .long 0xbc7edcf7,0xff523611,0x21680000,0x40030000 + .long 0xc90fdaa2,0x2168c235,0xa1000000,0x40030000 + .long 0xd5a0d84c,0x437f4e58,0x1fc00000,0x40030000 + .long 0xe231d5f6,0x6595da7b,0x21300000,0x40030000 + .long 0xeec2d3a0,0x87ac669f,0xa1380000,0x40030000 + .long 0xfb53d14a,0xa9c2f2c2,0xa0000000,0x40040000 + .long 0x83f2677a,0x65ecbf73,0xa1c40000,0x40040000 + .long 0x8a3ae64f,0x76f80584,0x21880000,0x40040000 + .long 0x90836524,0x88034b96,0xa0b00000,0x40040000 + .long 0x96cbe3f9,0x990e91a8,0xa1e00000,0x40040000 + .long 0x9d1462ce,0xaa19d7b9,0x21580000,0x40040000 + .long 0xa35ce1a3,0xbb251dcb,0xa1100000,0x40040000 + .long 0xa9a56078,0xcc3063dd,0xa1fc0000,0x40040000 + .long 0xafeddf4d,0xdd3ba9ee,0x21200000,0x40040000 + .long 0xb6365e22,0xee46f000,0xa1480000,0x40040000 + .long 0xbc7edcf7,0xff523611,0x21e80000,0x40040000 + .long 0xc2c75bcd,0x105d7c23,0x20d00000,0x40040000 + .long 0xc90fdaa2,0x2168c235,0xa1800000,0xf2104800 + .long 0x22103228,0x00040281,0x7fffffff,0x0c813fd7 + .long 0x80006c04,0x60000134,0x0c814004,0xbc7e6d04 + .long 0x60000144,0xf2000080,0xf23a54a3,0xd3d443fa + .long 0xfdbcf201,0x6080e981,0xd3c1f219,0x4828f211 + .long 0x4428ea99,0x02818000,0x0000f227,0xe00c0c81 + .long 0x00000000,0x6d000072,0xf2000080,0xf20004a3 + .long 0xf23a5580,0xfaf8f23a,0x5500fafa,0xf20005a3 + .long 0xf2000523,0xf23a55a2,0xfaf4f23a,0x4922fafe + .long 0xf20005a3,0xf2000523,0xf23a49a2,0xfb00f23a + .long 0x4922fb0a,0xf20005a3,0xf2000523,0xf23a49a2 + .long 0xfb0cf200,0x0123f200,0x0ca3f200,0x0822f23c + .long 0x44a23f80,0x0000f21f,0xd030f200,0x9000f200 + .long 0x042060ff,0x000038d8,0xf2000080,0xf2000023 + .long 0xf23a5580,0xfa88f23a,0x5500fa8a,0xf20001a3 + .long 0xf2000123,0xf23a55a2,0xfa84f23a,0x4922fa8e + .long 0xf20001a3,0xf2000123,0xf23a49a2,0xfa90f23a + .long 0x4922fa9a,0xf20001a3,0xf2000123,0xf23a49a2 + .long 0xfa9cf200,0x0523f200,0x0c23f200,0x08a2f23c + .long 0x44223f80,0x0000f21f,0xd030f227,0x68800a97 + .long 0x80000000,0xf2009000,0xf21f4820,0x60ff0000 + .long 0x385e0c81,0x3fff8000,0x6e1cf227,0x6800f200 + .long 0x9000123c,0x0003f21f,0x480060ff,0x00003832 + .long 0x60ff0000,0x36cef227,0xe03c2f02,0xf23c4480 + .long 0x00000000,0x0c817ffe,0xffff6652,0x3d7c7ffe + .long 0xff842d7c,0xc90fdaa2,0xff8842ae,0xff8c3d7c + .long 0x7fdcff90,0x2d7c85a3,0x08d3ff94,0x42aeff98 + .long 0xf200003a,0xf294000e,0x002e0080,0xff84002e + .long 0x0080ff90,0xf22e4822,0xff84f200,0x0080f22e + .long 0x4822ff90,0xf20000a8,0xf22e48a2,0xff90f22e + .long 0x6800ff84,0x322eff84,0x22410281,0x00007fff + .long 0x04810000,0x3fff0c81,0x0000001c,0x6f0e0481 + .long 0x0000001b,0x1d7c0000,0xff586008,0x42811d7c + .long 0x0001ff58,0x243c0000,0x3ffe9481,0x2d7ca2f9 + .long 0x836eff88,0x2d7c4e44,0x152aff8c,0x3d42ff84 + .long 0xf2000100,0xf22e4923,0xff842409,0x48420282 + .long 0x80000000,0x00825f00,0x00002d42,0xff54f22e + .long 0x4522ff54,0xf22e4528,0xff542401,0x06820000 + .long 0x3fff3d42,0xff842d7c,0xc90fdaa2,0xff8842ae + .long 0xff8c0681,0x00003fdd,0x3d41ff90,0x2d7c85a3 + .long 0x08d3ff94,0x42aeff98,0x122eff58,0xf2000a00 + .long 0xf22e4a23,0xff84f200,0x0a80f22e,0x4aa3ff90 + .long 0xf2001180,0xf20015a2,0xf2000e28,0xf2000c28 + .long 0xf2001622,0xf2000180,0xf20010a8,0xf2000422 + .long 0x0c010000,0x6e00000e,0xf20001a8,0xf2000ca2 + .long 0x6000ff0c,0xf22e6100,0xff54241f,0xf21fd03c + .long 0x222eff54,0xe2996000,0xfd72bff6,0x687e3149 + .long 0x87d84002,0xac6934a2,0x6db3bfc2,0x476f4e1d + .long 0xa28e3fb3,0x44447f87,0x6989bfb7,0x44ee7faf + .long 0x45db3fbc,0x71c64694,0x0220bfc2,0x49249218 + .long 0x72f93fc9,0x99999999,0x8fa9bfd5,0x55555555 + .long 0x5555bfb7,0x0bf39853,0x9e6a3fbc,0x7187962d + .long 0x1d7dbfc2,0x49248271,0x07b83fc9,0x99999996 + .long 0x263ebfd5,0x55555555,0x55363fff,0x0000c90f + .long 0xdaa22168,0xc2350000,0x0000bfff,0x0000c90f + .long 0xdaa22168,0xc2350000,0x00000001,0x00008000 + .long 0x00000000,0x00000000,0x00008001,0x00008000 + .long 0x00000000,0x00000000,0x00003ffb,0x000083d1 + .long 0x52c5060b,0x7a510000,0x00003ffb,0x00008bc8 + .long 0x54456549,0x8b8b0000,0x00003ffb,0x000093be + .long 0x40601762,0x6b0d0000,0x00003ffb,0x00009bb3 + .long 0x078d35ae,0xc2020000,0x00003ffb,0x0000a3a6 + .long 0x9a525ddc,0xe7de0000,0x00003ffb,0x0000ab98 + .long 0xe9436276,0x56190000,0x00003ffb,0x0000b389 + .long 0xe502f9c5,0x98620000,0x00003ffb,0x0000bb79 + .long 0x7e436b09,0xe6fb0000,0x00003ffb,0x0000c367 + .long 0xa5c739e5,0xf4460000,0x00003ffb,0x0000cb54 + .long 0x4c61cff7,0xd5c60000,0x00003ffb,0x0000d33f + .long 0x62f82488,0x533e0000,0x00003ffb,0x0000db28 + .long 0xda816240,0x4c770000,0x00003ffb,0x0000e310 + .long 0xa4078ad3,0x4f180000,0x00003ffb,0x0000eaf6 + .long 0xb0a8188e,0xe1eb0000,0x00003ffb,0x0000f2da + .long 0xf1949dbe,0x79d50000,0x00003ffb,0x0000fabd + .long 0x581361d4,0x7e3e0000,0x00003ffc,0x00008346 + .long 0xac210959,0xecc40000,0x00003ffc,0x00008b23 + .long 0x2a083042,0x82d80000,0x00003ffc,0x000092fb + .long 0x70b8d29a,0xe2f90000,0x00003ffc,0x00009acf + .long 0x476f5ccd,0x1cb40000,0x00003ffc,0x0000a29e + .long 0x76304954,0xf23f0000,0x00003ffc,0x0000aa68 + .long 0xc5d08ab8,0x52300000,0x00003ffc,0x0000b22d + .long 0xfffd9d53,0x9f830000,0x00003ffc,0x0000b9ed + .long 0xef453e90,0x0ea50000,0x00003ffc,0x0000c1a8 + .long 0x5f1cc75e,0x3ea50000,0x00003ffc,0x0000c95d + .long 0x1be82813,0x8de60000,0x00003ffc,0x0000d10b + .long 0xf300840d,0x2de40000,0x00003ffc,0x0000d8b4 + .long 0xb2ba6bc0,0x5e7a0000,0x00003ffc,0x0000e057 + .long 0x2a6bb423,0x35f60000,0x00003ffc,0x0000e7f3 + .long 0x2a70ea9c,0xaa8f0000,0x00003ffc,0x0000ef88 + .long 0x843264ec,0xefaa0000,0x00003ffc,0x0000f717 + .long 0x0a28ecc0,0x66660000,0x00003ffd,0x0000812f + .long 0xd288332d,0xad320000,0x00003ffd,0x000088a8 + .long 0xd1b1218e,0x4d640000,0x00003ffd,0x00009012 + .long 0xab3f23e4,0xaee80000,0x00003ffd,0x0000976c + .long 0xc3d411e7,0xf1b90000,0x00003ffd,0x00009eb6 + .long 0x89493889,0xa2270000,0x00003ffd,0x0000a5ef + .long 0x72c34487,0x361b0000,0x00003ffd,0x0000ad17 + .long 0x00baf07a,0x72270000,0x00003ffd,0x0000b42c + .long 0xbcfafd37,0xefb70000,0x00003ffd,0x0000bb30 + .long 0x3a940ba8,0x0f890000,0x00003ffd,0x0000c221 + .long 0x15c6fcae,0xbbaf0000,0x00003ffd,0x0000c8fe + .long 0xf3e68633,0x12210000,0x00003ffd,0x0000cfc9 + .long 0x8330b400,0x0c700000,0x00003ffd,0x0000d680 + .long 0x7aa1102c,0x5bf90000,0x00003ffd,0x0000dd23 + .long 0x99bc3125,0x2aa30000,0x00003ffd,0x0000e3b2 + .long 0xa8556b8f,0xc5170000,0x00003ffd,0x0000ea2d + .long 0x764f6431,0x59890000,0x00003ffd,0x0000f3bf + .long 0x5bf8bad1,0xa21d0000,0x00003ffe,0x0000801c + .long 0xe39e0d20,0x5c9a0000,0x00003ffe,0x00008630 + .long 0xa2dada1e,0xd0660000,0x00003ffe,0x00008c1a + .long 0xd445f3e0,0x9b8c0000,0x00003ffe,0x000091db + .long 0x8f1664f3,0x50e20000,0x00003ffe,0x00009773 + .long 0x1420365e,0x538c0000,0x00003ffe,0x00009ce1 + .long 0xc8e6a0b8,0xcdba0000,0x00003ffe,0x0000a228 + .long 0x32dbcada,0xae090000,0x00003ffe,0x0000a746 + .long 0xf2ddb760,0x22940000,0x00003ffe,0x0000ac3e + .long 0xc0fb997d,0xd6a20000,0x00003ffe,0x0000b110 + .long 0x688aebdc,0x6f6a0000,0x00003ffe,0x0000b5bc + .long 0xc49059ec,0xc4b00000,0x00003ffe,0x0000ba44 + .long 0xbc7dd470,0x782f0000,0x00003ffe,0x0000bea9 + .long 0x4144fd04,0x9aac0000,0x00003ffe,0x0000c2eb + .long 0x4abb6616,0x28b60000,0x00003ffe,0x0000c70b + .long 0xd54ce602,0xee140000,0x00003ffe,0x0000cd00 + .long 0x0549adec,0x71590000,0x00003ffe,0x0000d484 + .long 0x57d2d8ea,0x4ea30000,0x00003ffe,0x0000db94 + .long 0x8da712de,0xce3b0000,0x00003ffe,0x0000e238 + .long 0x55f969e8,0x096a0000,0x00003ffe,0x0000e877 + .long 0x1129c435,0x32590000,0x00003ffe,0x0000ee57 + .long 0xc16e0d37,0x9c0d0000,0x00003ffe,0x0000f3e1 + .long 0x0211a87c,0x37790000,0x00003ffe,0x0000f919 + .long 0x039d758b,0x8d410000,0x00003ffe,0x0000fe05 + .long 0x8b8f6493,0x5fb30000,0x00003fff,0x00008155 + .long 0xfb497b68,0x5d040000,0x00003fff,0x00008388 + .long 0x9e3549d1,0x08e10000,0x00003fff,0x0000859c + .long 0xfa76511d,0x724b0000,0x00003fff,0x00008795 + .long 0x2ecfff81,0x31e70000,0x00003fff,0x00008973 + .long 0x2fd19557,0x641b0000,0x00003fff,0x00008b38 + .long 0xcad10193,0x2a350000,0x00003fff,0x00008ce7 + .long 0xa8d8301e,0xe6b50000,0x00003fff,0x00008f46 + .long 0xa39e2eae,0x52810000,0x00003fff,0x0000922d + .long 0xa7d79188,0x84870000,0x00003fff,0x000094d1 + .long 0x9fcbdedf,0x52410000,0x00003fff,0x0000973a + .long 0xb94419d2,0xa08b0000,0x00003fff,0x0000996f + .long 0xf00e08e1,0x0b960000,0x00003fff,0x00009b77 + .long 0x3f951232,0x1da70000,0x00003fff,0x00009d55 + .long 0xcc320f93,0x56240000,0x00003fff,0x00009f10 + .long 0x0575006c,0xc5710000,0x00003fff,0x0000a0a9 + .long 0xc290d97c,0xc06c0000,0x00003fff,0x0000a226 + .long 0x59ebebc0,0x630a0000,0x00003fff,0x0000a388 + .long 0xb4aff6ef,0x0ec90000,0x00003fff,0x0000a4d3 + .long 0x5f1061d2,0x92c40000,0x00003fff,0x0000a608 + .long 0x95dcfbe3,0x187e0000,0x00003fff,0x0000a72a + .long 0x51dc7367,0xbeac0000,0x00003fff,0x0000a83a + .long 0x51530956,0x168f0000,0x00003fff,0x0000a93a + .long 0x20077539,0x546e0000,0x00003fff,0x0000aa9e + .long 0x7245023b,0x26050000,0x00003fff,0x0000ac4c + .long 0x84ba6fe4,0xd58f0000,0x00003fff,0x0000adce + .long 0x4a4a606b,0x97120000,0x00003fff,0x0000af2a + .long 0x2dcd8d26,0x3c9c0000,0x00003fff,0x0000b065 + .long 0x6f81f222,0x65c70000,0x00003fff,0x0000b184 + .long 0x65150f71,0x496a0000,0x00003fff,0x0000b28a + .long 0xaa156f9a,0xda350000,0x00003fff,0x0000b37b + .long 0x44ff3766,0xb8950000,0x00003fff,0x0000b458 + .long 0xc3dce963,0x04330000,0x00003fff,0x0000b525 + .long 0x529d5622,0x46bd0000,0x00003fff,0x0000b5e2 + .long 0xcca95f9d,0x88cc0000,0x00003fff,0x0000b692 + .long 0xcada7aca,0x1ada0000,0x00003fff,0x0000b736 + .long 0xaea7a692,0x58380000,0x00003fff,0x0000b7cf + .long 0xab287e9f,0x7b360000,0x00003fff,0x0000b85e + .long 0xcc66cb21,0x98350000,0x00003fff,0x0000b8e4 + .long 0xfd5a20a5,0x93da0000,0x00003fff,0x0000b99f + .long 0x41f64aff,0x9bb50000,0x00003fff,0x0000ba7f + .long 0x1e17842b,0xbe7b0000,0x00003fff,0x0000bb47 + .long 0x12857637,0xe17d0000,0x00003fff,0x0000bbfa + .long 0xbe8a4788,0xdf6f0000,0x00003fff,0x0000bc9d + .long 0x0fad2b68,0x9d790000,0x00003fff,0x0000bd30 + .long 0x6a39471e,0xcd860000,0x00003fff,0x0000bdb6 + .long 0xc731856a,0xf18a0000,0x00003fff,0x0000be31 + .long 0xcac502e8,0x0d700000,0x00003fff,0x0000bea2 + .long 0xd55ce331,0x94e20000,0x00003fff,0x0000bf0b + .long 0x10b7c031,0x28f00000,0x00003fff,0x0000bf6b + .long 0x7a18dacb,0x778d0000,0x00003fff,0x0000bfc4 + .long 0xea4663fa,0x18f60000,0x00003fff,0x0000c018 + .long 0x1bde8b89,0xa4540000,0x00003fff,0x0000c065 + .long 0xb066cfbf,0x64390000,0x00003fff,0x0000c0ae + .long 0x345f5634,0x0ae60000,0x00003fff,0x0000c0f2 + .long 0x22919cb9,0xe6a70000,0x0000f210,0x48002210 + .long 0x32280004,0xf22e6800,0xff840281,0x7fffffff + .long 0x0c813ffb,0x80006c04,0x600000d0,0x0c814002 + .long 0xffff6f04,0x6000014c,0x02aef800,0x0000ff88 + .long 0x00ae0400,0x0000ff88,0x2d7c0000,0x0000ff8c + .long 0xf2000080,0xf22e48a3,0xff84f22e,0x4828ff84 + .long 0xf23c44a2,0x3f800000,0xf2000420,0x2f022401 + .long 0x02810000,0x78000282,0x7fff0000,0x04823ffb + .long 0x0000e282,0xd282ee81,0x43faf780,0xd3c12d59 + .long 0xff902d59,0xff942d59,0xff98222e,0xff840281 + .long 0x80000000,0x83aeff90,0x241ff227,0xe004f200 + .long 0x0080f200,0x04a3f23a,0x5500f6a0,0xf2000522 + .long 0xf2000523,0xf20000a3,0xf23a5522,0xf696f23a + .long 0x54a3f698,0xf20008a3,0xf2000422,0xf21fd020 + .long 0xf2009000,0xf22e4822,0xff9060ff,0x00002d30 + .long 0x0c813fff,0x80006e00,0x008a0c81,0x3fd78000 + .long 0x6d00006c,0xf227e00c,0xf2000023,0xf2000080 + .long 0xf20004a3,0xf23a5500,0xf65af23a,0x5580f65c + .long 0xf2000523,0xf20005a3,0xf23a5522,0xf656f23a + .long 0x55a2f658,0xf2000523,0xf2000ca3,0xf23a5522 + .long 0xf652f23a,0x54a2f654,0xf2000123,0xf22e4823 + .long 0xff84f200,0x08a2f200,0x0423f21f,0xd030f200 + .long 0x9000f22e,0x4822ff84,0x60ff0000,0x2cb2f200 + .long 0x9000123c,0x0003f22e,0x4800ff84,0x60ff0000 + .long 0x2c900c81,0x40638000,0x6e00008e,0xf227e00c + .long 0xf23c4480,0xbf800000,0xf20000a0,0xf2000400 + .long 0xf2000023,0xf22e6880,0xff84f200,0x0080f200 + .long 0x04a3f23a,0x5580f5ec,0xf23a5500,0xf5eef200 + .long 0x05a3f200,0x0523f23a,0x55a2f5e8,0xf23a5522 + .long 0xf5eaf200,0x0ca3f200,0x0123f23a,0x54a2f5e4 + .long 0xf22e4823,0xff84f200,0x08a2f200,0x0423f22e + .long 0x4822ff84,0xf21fd030,0xf2009000,0x4a106a0c + .long 0xf23a4822,0xf5d660ff,0x00002c24,0xf23a4822 + .long 0xf5ba60ff,0x00002c10,0x4a106a16,0xf23a4800 + .long 0xf5baf200,0x9000f23a,0x4822f5c0,0x60ff0000 + .long 0x2bfef23a,0x4800f594,0xf2009000,0xf23a4822 + .long 0xf5ba60ff,0x00002be0,0x60ff0000,0x2a66f210 + .long 0x48002210,0x32280004,0x02817fff,0xffff0c81 + .long 0x3fff8000,0x6c4e0c81,0x3fd78000,0x6d00007c + .long 0xf23c4480,0x3f800000,0xf20000a8,0xf227e004 + .long 0xf23c4500,0x3f800000,0xf2000122,0xf20008a3 + .long 0xf21fd020,0xf2000484,0xf2000420,0xf227e001 + .long 0x41d761ff,0xfffffd66,0xdffc0000,0x000c60ff + .long 0x00002b6c,0xf2000018,0xf23c4438,0x3f800000 + .long 0xf2d20000,0x29d4f23a,0x4800c5a6,0x22100281 + .long 0x80000000,0x00813f80,0x00002f01,0xf2009000 + .long 0xf21f4423,0x60ff0000,0x2b36f200,0x9000123c + .long 0x0003f210,0x480060ff,0x00002b16,0x60ff0000 + .long 0x29b2f210,0x48002210,0x32280004,0x02817fff + .long 0xffff0c81,0x3fff8000,0x6c44f23c,0x44803f80 + .long 0x0000f200,0x00a2f200,0x001af23c,0x44223f80 + .long 0x0000f200,0x0420f200,0x00042f00,0x4280f227 + .long 0xe00141d7,0x61ffffff,0xfcc4dffc,0x0000000c + .long 0xf21f9000,0xf2000022,0x60ff0000,0x2acaf200 + .long 0x0018f23c,0x44383f80,0x0000f2d2,0x0000292a + .long 0x4a106a18,0xf23a4800,0xc4e8f200,0x9000f23c + .long 0x44220080,0x000060ff,0x00002a9c,0x60ff0000 + .long 0x2ce8f200,0x9000f23a,0x4800c4d6,0x60ff0000 + .long 0x2a863fdc,0x000082e3,0x08654361,0xc4c60000 + .long 0x00003fa5,0x55555555,0x4cc13fc5,0x55555555 + .long 0x4a543f81,0x11111117,0x43853fa5,0x55555555 + .long 0x4f5a3fc5,0x55555555,0x55550000,0x00000000 + .long 0x00003ec7,0x1de3a577,0x46823efa,0x01a019d7 + .long 0xcb683f2a,0x01a01a01,0x9df33f56,0xc16c16c1 + .long 0x70e23f81,0x11111111,0x11113fa5,0x55555555 + .long 0x55553ffc,0x0000aaaa,0xaaaaaaaa,0xaaab0000 + .long 0x000048b0,0x00000000,0x00003730,0x00000000 + .long 0x00003fff,0x00008000,0x00000000,0x00000000 + .long 0x00003fff,0x00008164,0xd1f3bc03,0x07749f84 + .long 0x1a9b3fff,0x000082cd,0x8698ac2b,0xa1d89fc1 + .long 0xd5b93fff,0x0000843a,0x28c3acde,0x4048a072 + .long 0x83693fff,0x000085aa,0xc367cc48,0x7b141fc5 + .long 0xc95c3fff,0x0000871f,0x61969e8d,0x10101ee8 + .long 0x5c9f3fff,0x00008898,0x0e8092da,0x85289fa2 + .long 0x07293fff,0x00008a14,0xd575496e,0xfd9ca07b + .long 0xf9af3fff,0x00008b95,0xc1e3ea8b,0xd6e8a002 + .long 0x0dcf3fff,0x00008d1a,0xdf5b7e5b,0xa9e4205a + .long 0x63da3fff,0x00008ea4,0x398b45cd,0x53c01eb7 + .long 0x00513fff,0x00009031,0xdc431466,0xb1dc1f6e + .long 0xb0293fff,0x000091c3,0xd373ab11,0xc338a078 + .long 0x14943fff,0x0000935a,0x2b2f13e6,0xe92c9eb3 + .long 0x19b03fff,0x000094f4,0xefa8fef7,0x09602017 + .long 0x457d3fff,0x00009694,0x2d372018,0x5a001f11 + .long 0xd5373fff,0x00009837,0xf0518db8,0xa9709fb9 + .long 0x52dd3fff,0x000099e0,0x459320b7,0xfa641fe4 + .long 0x30873fff,0x00009b8d,0x39b9d54e,0x55381fa2 + .long 0xa8183fff,0x00009d3e,0xd9a72cff,0xb7501fde + .long 0x494d3fff,0x00009ef5,0x326091a1,0x11ac2050 + .long 0x48903fff,0x0000a0b0,0x510fb971,0x4fc4a073 + .long 0x691c3fff,0x0000a270,0x43030c49,0x68181f9b + .long 0x7a053fff,0x0000a435,0x15ae09e6,0x80a0a079 + .long 0x71263fff,0x0000a5fe,0xd6a9b151,0x38eca071 + .long 0xa1403fff,0x0000a7cd,0x93b4e965,0x3568204f + .long 0x62da3fff,0x0000a9a1,0x5ab4ea7c,0x0ef81f28 + .long 0x3c4a3fff,0x0000ab7a,0x39b5a93e,0xd3389f9a + .long 0x7fdc3fff,0x0000ad58,0x3eea42a1,0x4ac8a05b + .long 0x3fac3fff,0x0000af3b,0x78ad690a,0x43741fdf + .long 0x26103fff,0x0000b123,0xf581d2ac,0x25909f70 + .long 0x5f903fff,0x0000b311,0xc412a911,0x2488201f + .long 0x678a3fff,0x0000b504,0xf333f9de,0x64841f32 + .long 0xfb133fff,0x0000b6fd,0x91e328d1,0x77902003 + .long 0x8b303fff,0x0000b8fb,0xaf4762fb,0x9ee8200d + .long 0xc3cc3fff,0x0000baff,0x5ab2133e,0x45fc9f8b + .long 0x2ae63fff,0x0000bd08,0xa39f580c,0x36c0a02b + .long 0xbf703fff,0x0000bf17,0x99b67a73,0x1084a00b + .long 0xf5183fff,0x0000c12c,0x4cca6670,0x9458a041 + .long 0xdd413fff,0x0000c346,0xccda2497,0x64089fdf + .long 0x137b3fff,0x0000c567,0x2a115506,0xdadc201f + .long 0x15683fff,0x0000c78d,0x74c8abb9,0xb15c1fc1 + .long 0x3a2e3fff,0x0000c9b9,0xbd866e2f,0x27a4a03f + .long 0x8f033fff,0x0000cbec,0x14fef272,0x7c5c1ff4 + .long 0x907d3fff,0x0000ce24,0x8c151f84,0x80e49e6e + .long 0x53e43fff,0x0000d063,0x33daef2b,0x25941fd6 + .long 0xd45c3fff,0x0000d2a8,0x1d91f12a,0xe45ca076 + .long 0xedb93fff,0x0000d4f3,0x5aabcfed,0xfa209fa6 + .long 0xde213fff,0x0000d744,0xfccad69d,0x6af41ee6 + .long 0x9a2f3fff,0x0000d99d,0x15c278af,0xd7b4207f + .long 0x439f3fff,0x0000dbfb,0xb797daf2,0x3754201e + .long 0xc2073fff,0x0000de60,0xf4825e0e,0x91249e8b + .long 0xe1753fff,0x0000e0cc,0xdeec2a94,0xe1102003 + .long 0x2c4b3fff,0x0000e33f,0x8972be8a,0x5a502004 + .long 0xdff53fff,0x0000e5b9,0x06e77c83,0x48a81e72 + .long 0xf47a3fff,0x0000e839,0x6a503c4b,0xdc681f72 + .long 0x2f223fff,0x0000eac0,0xc6e7dd24,0x3930a017 + .long 0xe9453fff,0x0000ed4f,0x301ed994,0x2b841f40 + .long 0x1a5b3fff,0x0000efe4,0xb99bdcda,0xf5cc9fb9 + .long 0xa9e33fff,0x0000f281,0x773c59ff,0xb1382074 + .long 0x4c053fff,0x0000f525,0x7d152486,0xcc2c1f77 + .long 0x3a193fff,0x0000f7d0,0xdf730ad1,0x3bb81ffe + .long 0x90d53fff,0x0000fa83,0xb2db722a,0x033ca041 + .long 0xed223fff,0x0000fd3e,0x0c0cf486,0xc1741f85 + .long 0x3f3a2210,0x02817fff,0x00000c81,0x3fbe0000 + .long 0x6c0660ff,0x00000108,0x32280004,0x0c81400c + .long 0xb1676d06,0x60ff0000,0x010cf210,0x4800f200 + .long 0x0080f23c,0x442342b8,0xaa3bf227,0xe00c2d7c + .long 0x00000000,0xff58f201,0x600043fa,0xfbb6f201 + .long 0x40002d41,0xff540281,0x0000003f,0xe989d3c1 + .long 0x222eff54,0xec810641,0x3fff3d7a,0xfb06ff54 + .long 0xf2000100,0xf23c4423,0xbc317218,0xf23a4923 + .long 0xfaf2f200,0x0422f200,0x0822f200,0x0080f200 + .long 0x04a3f23c,0x45003ab6,0x0b70f200,0x0523f200 + .long 0x0580f23c,0x45a33c08,0x8895f23a,0x5522fad4 + .long 0xf23a55a2,0xfad6f200,0x05233d41,0xff842d7c + .long 0x80000000,0xff8842ae,0xff8cf200,0x05a3f23c + .long 0x45223f00,0x0000f200,0x01a3f200,0x0523f200 + .long 0x0c22f219,0x4880f200,0x0822f200,0x0423f21f + .long 0xd030f211,0x4422f200,0x0422222e,0xff584a81 + .long 0x6706f22e,0x4823ff90,0xf2009000,0x123c0000 + .long 0xf22e4823,0xff8460ff,0x000024c6,0xf210d080 + .long 0xf2009000,0xf23c4422,0x3f800000,0x60ff0000 + .long 0x24c60c81,0x400cb27c,0x6e66f210,0x4800f200 + .long 0x0080f23c,0x442342b8,0xaa3bf227,0xe00c2d7c + .long 0x00000001,0xff58f201,0x600043fa,0xfaa6f201 + .long 0x40002d41,0xff540281,0x0000003f,0xe989d3c1 + .long 0x222eff54,0xec812d41,0xff54e281,0x93aeff54 + .long 0x06413fff,0x3d41ff90,0x2d7c8000,0x0000ff94 + .long 0x42aeff98,0x222eff54,0x06413fff,0x6000fed2 + .long 0x4a106bff,0x00002370,0x60ff0000,0x24122f10 + .long 0x02978000,0x00000097,0x00800000,0xf23c4400 + .long 0x3f800000,0xf2009000,0xf21f4422,0x60ff0000 + .long 0x24262210,0x02817fff,0x00000c81,0x3ffd0000 + .long 0x6c0660ff,0x0000015e,0x32280004,0x0c814004 + .long 0xc2156f06,0x60ff0000,0x026cf210,0x4800f200 + .long 0x0080f23c,0x442342b8,0xaa3bf227,0xe00cf201 + .long 0x600043fa,0xf9eef201,0x40002d41,0xff540281 + .long 0x0000003f,0xe989d3c1,0x222eff54,0xec812d41 + .long 0xff54f200,0x0100f23c,0x4423bc31,0x7218f23a + .long 0x4923f930,0xf2000422,0xf2000822,0x06413fff + .long 0xf2000080,0xf20004a3,0xf23c4500,0x3950097b + .long 0xf2000523,0xf2000580,0xf23c45a3,0x3ab60b6a + .long 0xf23a5522,0xf91ef23a,0x55a2f920,0x3d41ff84 + .long 0x2d7c8000,0x0000ff88,0x42aeff8c,0xf2000523 + .long 0x222eff54,0x4441f200,0x05a30641,0x3ffff23a + .long 0x5522f900,0xf23c45a2,0x3f000000,0xf2000523 + .long 0x00418000,0x3d41ff90,0x2d7c8000,0x0000ff94 + .long 0x42aeff98,0xf2000ca3,0xf2000123,0xf2000422 + .long 0xf2000822,0xf21fd030,0xf2114823,0x222eff54 + .long 0x0c810000,0x003f6f1a,0xf2294480,0x000cf22e + .long 0x48a2ff90,0xf2000422,0xf2114822,0x60ff0000 + .long 0x00340c81,0xfffffffd,0x6c16f229,0x4422000c + .long 0xf2114822,0xf22e4822,0xff9060ff,0x00000016 + .long 0xf2194880,0xf2114422,0xf22e48a2,0xff90f200 + .long 0x0422f200,0x9000f22e,0x4823ff84,0x60ff0000 + .long 0x22ae0c81,0x3fbe0000,0x6c6c0c81,0x00330000 + .long 0x6d2c2d7c,0x80010000,0xff842d7c,0x80000000 + .long 0xff8842ae,0xff8cf210,0x4800f200,0x9000123c + .long 0x0002f22e,0x4822ff84,0x60ff0000,0x2264f210 + .long 0x4800f23a,0x5423f86c,0x2d7c8001,0x0000ff84 + .long 0x2d7c8000,0x0000ff88,0x42aeff8c,0xf22e4822 + .long 0xff84f200,0x9000123c,0x0000f23a,0x5423f84c + .long 0x60ff0000,0x222cf210,0x4800f200,0x0023f227 + .long 0xe00cf23c,0x44802f30,0xcaa8f200,0x00a3f23c + .long 0x4500310f,0x8290f23c,0x44a232d7,0x3220f200 + .long 0x0123f200,0x00a3f23c,0x45223493,0xf281f23a + .long 0x54a2f7c0,0xf2000123,0xf20000a3,0xf23a5522 + .long 0xf7baf23a,0x54a2f7bc,0xf2000123,0xf20000a3 + .long 0xf23a5522,0xf7b6f23a,0x54a2f7b8,0xf2000123 + .long 0xf20000a3,0xf23a5522,0xf7b2f23a,0x48a2f7b4 + .long 0xf2000123,0xf20000a3,0xf2000123,0xf21048a3 + .long 0xf23c4423,0x3f000000,0xf20008a2,0xf21fd030 + .long 0xf2000422,0xf2009000,0xf2104822,0x60ff0000 + .long 0x218e2210,0x0c810000,0x00006e00,0xfbacf23c + .long 0x4400bf80,0x0000f200,0x9000f23c,0x44220080 + .long 0x000060ff,0x00002178,0x60ff0000,0x1ff63028 + .long 0x00000880,0x000f0440,0x3ffff200,0x50006d02 + .long 0x4e751d7c,0x0008ff64,0x4e7561ff,0x00007cfc + .long 0x44400440,0x3ffff200,0x50001d7c,0x0008ff64 + .long 0x4e753028,0x00000040,0x7fff0880,0x000e2d68 + .long 0x0004ff88,0x2d680008,0xff8c3d40,0xff84f22e + .long 0x4800ff84,0x6b024e75,0x1d7c0008,0xff644e75 + .long 0x61ff0000,0x7cb660ca,0x7ffb0000,0x80000000 + .long 0x00000000,0x00000000,0xf2104800,0x22103228 + .long 0x00040281,0x7fffffff,0x0c81400c,0xb1676e42 + .long 0xf2000018,0x2f004280,0xf227e001,0x41d761ff + .long 0xfffffad2,0xdffc0000,0x000cf23c,0x44233f00 + .long 0x0000201f,0xf23c4480,0x3e800000,0xf20000a0 + .long 0xf2009000,0x123c0002,0xf2000422,0x60ff0000 + .long 0x20800c81,0x400cb2b3,0x6e3cf200,0x0018f23a + .long 0x5428baae,0xf23a5428,0xbab02f00,0x4280f227 + .long 0xe00141d7,0x61ffffff,0xfa7cdffc,0x0000000c + .long 0x201ff200,0x9000123c,0x0000f23a,0x4823ff5a + .long 0x60ff0000,0x203c60ff,0x00002014,0xf23c4400 + .long 0x3f800000,0xf2009000,0xf23c4422,0x00800000 + .long 0x60ff0000,0x2032f210,0x48002210,0x32280004 + .long 0x22410281,0x7fffffff,0x0c81400c,0xb1676e62 + .long 0xf2000018,0x48e78040,0xf227e001,0x41d74280 + .long 0x61ffffff,0xfbe0dffc,0x0000000c,0xf23c9000 + .long 0x00000000,0x4cdf0201,0xf2000080,0xf23c44a2 + .long 0x3f800000,0xf2276800,0xf2000420,0x22090281 + .long 0x80000000,0x00813f00,0x0000f21f,0x48222f01 + .long 0xf2009000,0x123c0000,0xf21f4423,0x60ff0000 + .long 0x1fa00c81,0x400cb2b3,0x6eff0000,0x1f4cf200 + .long 0x0018f23a,0x5428b9ca,0x2f3c0000,0x00002f3c + .long 0x80000000,0x22090281,0x80000000,0x00817ffb + .long 0x00002f01,0xf23a5428,0xb9b02f00,0x4280f227 + .long 0xe00141d7,0x61ffffff,0xf97cdffc,0x0000000c + .long 0x201ff200,0x9000123c,0x0000f21f,0x482360ff + .long 0x00001f3e,0x60ff0000,0x1ddaf210,0x4800f22e + .long 0x6800ff84,0x22103228,0x00042d41,0xff840281 + .long 0x7fffffff,0x0c813fd7,0x80006d00,0x00740c81 + .long 0x3fffddce,0x6e00006a,0x222eff84,0x2d41ff5c + .long 0x02817fff,0x00000681,0x00010000,0x2d41ff84 + .long 0x02ae8000,0x0000ff5c,0xf22e4800,0xff842f00 + .long 0x4280f227,0xe00141d7,0x61ffffff,0xfac8dffc + .long 0x0000000c,0x201ff200,0x0080f23c,0x44a24000 + .long 0x0000222e,0xff5cf22e,0x6880ff84,0xb3aeff84 + .long 0xf2009000,0xf22e4820,0xff8460ff,0x00001eb0 + .long 0x0c813fff,0x80006d00,0x00880c81,0x40048aa1 + .long 0x6e000092,0x222eff84,0x2d41ff5c,0x02817fff + .long 0x00000681,0x00010000,0x2d41ff84,0x02ae8000 + .long 0x0000ff5c,0x222eff5c,0xf22e4800,0xff842f00 + .long 0x4280f227,0xe00141d7,0x61ffffff,0xf878dffc + .long 0x0000000c,0x201f222e,0xff5cf23c,0x44223f80 + .long 0x00000a81,0xc0000000,0xf2014480,0xf20000a0 + .long 0x222eff5c,0x00813f80,0x0000f201,0x4400f200 + .long 0x9000123c,0x0002f200,0x042260ff,0x00001e20 + .long 0xf2009000,0x123c0003,0xf22e4800,0xff8460ff + .long 0x00001dfe,0x222eff84,0x02818000,0x00000081 + .long 0x3f800000,0xf2014400,0x02818000,0x00000a81 + .long 0x80800000,0xf2009000,0xf2014422,0x60ff0000 + .long 0x1dde60ff,0x00001c6c,0x3ffe0000,0xb17217f7 + .long 0xd1cf79ac,0x00000000,0x3f800000,0x00000000 + .long 0x7f800000,0xbf800000,0x3fc2499a,0xb5e4040b + .long 0xbfc555b5,0x848cb7db,0x3fc99999,0x987d8730 + .long 0xbfcfffff,0xff6f7e97,0x3fd55555,0x555555a4 + .long 0xbfe00000,0x00000008,0x3f175496,0xadd7dad6 + .long 0x3f3c71c2,0xfe80c7e0,0x3f624924,0x928bccff + .long 0x3f899999,0x999995ec,0x3fb55555,0x55555555 + .long 0x40000000,0x00000000,0x3f990000,0x80000000 + .long 0x00000000,0x00000000,0x3ffe0000,0xfe03f80f + .long 0xe03f80fe,0x00000000,0x3ff70000,0xff015358 + .long 0x833c47e2,0x00000000,0x3ffe0000,0xfa232cf2 + .long 0x52138ac0,0x00000000,0x3ff90000,0xbdc8d83e + .long 0xad88d549,0x00000000,0x3ffe0000,0xf6603d98 + .long 0x0f6603da,0x00000000,0x3ffa0000,0x9cf43dcf + .long 0xf5eafd48,0x00000000,0x3ffe0000,0xf2b9d648 + .long 0x0f2b9d65,0x00000000,0x3ffa0000,0xda16eb88 + .long 0xcb8df614,0x00000000,0x3ffe0000,0xef2eb71f + .long 0xc4345238,0x00000000,0x3ffb0000,0x8b29b775 + .long 0x1bd70743,0x00000000,0x3ffe0000,0xebbdb2a5 + .long 0xc1619c8c,0x00000000,0x3ffb0000,0xa8d839f8 + .long 0x30c1fb49,0x00000000,0x3ffe0000,0xe865ac7b + .long 0x7603a197,0x00000000,0x3ffb0000,0xc61a2eb1 + .long 0x8cd907ad,0x00000000,0x3ffe0000,0xe525982a + .long 0xf70c880e,0x00000000,0x3ffb0000,0xe2f2a47a + .long 0xde3a18af,0x00000000,0x3ffe0000,0xe1fc780e + .long 0x1fc780e2,0x00000000,0x3ffb0000,0xff64898e + .long 0xdf55d551,0x00000000,0x3ffe0000,0xdee95c4c + .long 0xa037ba57,0x00000000,0x3ffc0000,0x8db956a9 + .long 0x7b3d0148,0x00000000,0x3ffe0000,0xdbeb61ee + .long 0xd19c5958,0x00000000,0x3ffc0000,0x9b8fe100 + .long 0xf47ba1de,0x00000000,0x3ffe0000,0xd901b203 + .long 0x6406c80e,0x00000000,0x3ffc0000,0xa9372f1d + .long 0x0da1bd17,0x00000000,0x3ffe0000,0xd62b80d6 + .long 0x2b80d62c,0x00000000,0x3ffc0000,0xb6b07f38 + .long 0xce90e46b,0x00000000,0x3ffe0000,0xd3680d36 + .long 0x80d3680d,0x00000000,0x3ffc0000,0xc3fd0329 + .long 0x06488481,0x00000000,0x3ffe0000,0xd0b69fcb + .long 0xd2580d0b,0x00000000,0x3ffc0000,0xd11de0ff + .long 0x15ab18ca,0x00000000,0x3ffe0000,0xce168a77 + .long 0x25080ce1,0x00000000,0x3ffc0000,0xde1433a1 + .long 0x6c66b150,0x00000000,0x3ffe0000,0xcb8727c0 + .long 0x65c393e0,0x00000000,0x3ffc0000,0xeae10b5a + .long 0x7ddc8add,0x00000000,0x3ffe0000,0xc907da4e + .long 0x871146ad,0x00000000,0x3ffc0000,0xf7856e5e + .long 0xe2c9b291,0x00000000,0x3ffe0000,0xc6980c69 + .long 0x80c6980c,0x00000000,0x3ffd0000,0x82012ca5 + .long 0xa68206d7,0x00000000,0x3ffe0000,0xc4372f85 + .long 0x5d824ca6,0x00000000,0x3ffd0000,0x882c5fcd + .long 0x7256a8c5,0x00000000,0x3ffe0000,0xc1e4bbd5 + .long 0x95f6e947,0x00000000,0x3ffd0000,0x8e44c60b + .long 0x4ccfd7de,0x00000000,0x3ffe0000,0xbfa02fe8 + .long 0x0bfa02ff,0x00000000,0x3ffd0000,0x944ad09e + .long 0xf4351af6,0x00000000,0x3ffe0000,0xbd691047 + .long 0x07661aa3,0x00000000,0x3ffd0000,0x9a3eecd4 + .long 0xc3eaa6b2,0x00000000,0x3ffe0000,0xbb3ee721 + .long 0xa54d880c,0x00000000,0x3ffd0000,0xa0218434 + .long 0x353f1de8,0x00000000,0x3ffe0000,0xb92143fa + .long 0x36f5e02e,0x00000000,0x3ffd0000,0xa5f2fcab + .long 0xbbc506da,0x00000000,0x3ffe0000,0xb70fbb5a + .long 0x19be3659,0x00000000,0x3ffd0000,0xabb3b8ba + .long 0x2ad362a5,0x00000000,0x3ffe0000,0xb509e68a + .long 0x9b94821f,0x00000000,0x3ffd0000,0xb1641795 + .long 0xce3ca97b,0x00000000,0x3ffe0000,0xb30f6352 + .long 0x8917c80b,0x00000000,0x3ffd0000,0xb7047551 + .long 0x5d0f1c61,0x00000000,0x3ffe0000,0xb11fd3b8 + .long 0x0b11fd3c,0x00000000,0x3ffd0000,0xbc952afe + .long 0xea3d13e1,0x00000000,0x3ffe0000,0xaf3addc6 + .long 0x80af3ade,0x00000000,0x3ffd0000,0xc2168ed0 + .long 0xf458ba4a,0x00000000,0x3ffe0000,0xad602b58 + .long 0x0ad602b6,0x00000000,0x3ffd0000,0xc788f439 + .long 0xb3163bf1,0x00000000,0x3ffe0000,0xab8f69e2 + .long 0x8359cd11,0x00000000,0x3ffd0000,0xccecac08 + .long 0xbf04565d,0x00000000,0x3ffe0000,0xa9c84a47 + .long 0xa07f5638,0x00000000,0x3ffd0000,0xd2420487 + .long 0x2dd85160,0x00000000,0x3ffe0000,0xa80a80a8 + .long 0x0a80a80b,0x00000000,0x3ffd0000,0xd7894992 + .long 0x3bc3588a,0x00000000,0x3ffe0000,0xa655c439 + .long 0x2d7b73a8,0x00000000,0x3ffd0000,0xdcc2c4b4 + .long 0x9887dacc,0x00000000,0x3ffe0000,0xa4a9cf1d + .long 0x96833751,0x00000000,0x3ffd0000,0xe1eebd3e + .long 0x6d6a6b9e,0x00000000,0x3ffe0000,0xa3065e3f + .long 0xae7cd0e0,0x00000000,0x3ffd0000,0xe70d785c + .long 0x2f9f5bdc,0x00000000,0x3ffe0000,0xa16b312e + .long 0xa8fc377d,0x00000000,0x3ffd0000,0xec1f392c + .long 0x5179f283,0x00000000,0x3ffe0000,0x9fd809fd + .long 0x809fd80a,0x00000000,0x3ffd0000,0xf12440d3 + .long 0xe36130e6,0x00000000,0x3ffe0000,0x9e4cad23 + .long 0xdd5f3a20,0x00000000,0x3ffd0000,0xf61cce92 + .long 0x346600bb,0x00000000,0x3ffe0000,0x9cc8e160 + .long 0xc3fb19b9,0x00000000,0x3ffd0000,0xfb091fd3 + .long 0x8145630a,0x00000000,0x3ffe0000,0x9b4c6f9e + .long 0xf03a3caa,0x00000000,0x3ffd0000,0xffe97042 + .long 0xbfa4c2ad,0x00000000,0x3ffe0000,0x99d722da + .long 0xbde58f06,0x00000000,0x3ffe0000,0x825efced + .long 0x49369330,0x00000000,0x3ffe0000,0x9868c809 + .long 0x868c8098,0x00000000,0x3ffe0000,0x84c37a7a + .long 0xb9a905c9,0x00000000,0x3ffe0000,0x97012e02 + .long 0x5c04b809,0x00000000,0x3ffe0000,0x87224c2e + .long 0x8e645fb7,0x00000000,0x3ffe0000,0x95a02568 + .long 0x095a0257,0x00000000,0x3ffe0000,0x897b8cac + .long 0x9f7de298,0x00000000,0x3ffe0000,0x94458094 + .long 0x45809446,0x00000000,0x3ffe0000,0x8bcf55de + .long 0xc4cd05fe,0x00000000,0x3ffe0000,0x92f11384 + .long 0x0497889c,0x00000000,0x3ffe0000,0x8e1dc0fb + .long 0x89e125e5,0x00000000,0x3ffe0000,0x91a2b3c4 + .long 0xd5e6f809,0x00000000,0x3ffe0000,0x9066e68c + .long 0x955b6c9b,0x00000000,0x3ffe0000,0x905a3863 + .long 0x3e06c43b,0x00000000,0x3ffe0000,0x92aade74 + .long 0xc7be59e0,0x00000000,0x3ffe0000,0x8f1779d9 + .long 0xfdc3a219,0x00000000,0x3ffe0000,0x94e9bff6 + .long 0x15845643,0x00000000,0x3ffe0000,0x8dda5202 + .long 0x37694809,0x00000000,0x3ffe0000,0x9723a1b7 + .long 0x20134203,0x00000000,0x3ffe0000,0x8ca29c04 + .long 0x6514e023,0x00000000,0x3ffe0000,0x995899c8 + .long 0x90eb8990,0x00000000,0x3ffe0000,0x8b70344a + .long 0x139bc75a,0x00000000,0x3ffe0000,0x9b88bdaa + .long 0x3a3dae2f,0x00000000,0x3ffe0000,0x8a42f870 + .long 0x5669db46,0x00000000,0x3ffe0000,0x9db4224f + .long 0xffe1157c,0x00000000,0x3ffe0000,0x891ac73a + .long 0xe9819b50,0x00000000,0x3ffe0000,0x9fdadc26 + .long 0x8b7a12da,0x00000000,0x3ffe0000,0x87f78087 + .long 0xf78087f8,0x00000000,0x3ffe0000,0xa1fcff17 + .long 0xce733bd4,0x00000000,0x3ffe0000,0x86d90544 + .long 0x7a34acc6,0x00000000,0x3ffe0000,0xa41a9e8f + .long 0x5446fb9f,0x00000000,0x3ffe0000,0x85bf3761 + .long 0x2cee3c9b,0x00000000,0x3ffe0000,0xa633cd7e + .long 0x6771cd8b,0x00000000,0x3ffe0000,0x84a9f9c8 + .long 0x084a9f9d,0x00000000,0x3ffe0000,0xa8489e60 + .long 0x0b435a5e,0x00000000,0x3ffe0000,0x83993052 + .long 0x3fbe3368,0x00000000,0x3ffe0000,0xaa59233c + .long 0xcca4bd49,0x00000000,0x3ffe0000,0x828cbfbe + .long 0xb9a020a3,0x00000000,0x3ffe0000,0xac656dae + .long 0x6bcc4985,0x00000000,0x3ffe0000,0x81848da8 + .long 0xfaf0d277,0x00000000,0x3ffe0000,0xae6d8ee3 + .long 0x60bb2468,0x00000000,0x3ffe0000,0x80808080 + .long 0x80808081,0x00000000,0x3ffe0000,0xb07197a2 + .long 0x3c46c654,0x00000000,0xf2104800,0x2d7c0000 + .long 0x0000ff54,0x22103228,0x00042d50,0xff842d68 + .long 0x0004ff88,0x2d680008,0xff8c0c81,0x00000000 + .long 0x6d000182,0x0c813ffe,0xf07d6d0a,0x0c813fff + .long 0x88416f00,0x00e2e081,0xe0810481,0x00003fff + .long 0xd2aeff54,0x41faf7b2,0xf2014080,0x2d7c3fff + .long 0x0000ff84,0x2d6eff88,0xff9402ae,0xfe000000 + .long 0xff9400ae,0x01000000,0xff94222e,0xff940281 + .long 0x7e000000,0xe081e081,0xe881d1c1,0xf22e4800 + .long 0xff842d7c,0x3fff0000,0xff9042ae,0xff98f22e + .long 0x4828ff90,0xf227e00c,0xf2104823,0xf23a48a3 + .long 0xf6c8f200,0x0100f200,0x0923f22e,0x6880ff84 + .long 0xf2000980,0xf2000880,0xf23a54a3,0xf6ccf23a + .long 0x5523f6ce,0xf23a54a2,0xf6d0f23a,0x5522f6d2 + .long 0xf2000ca3,0xf2000d23,0xf23a54a2,0xf6ccf23a + .long 0x5522f6ce,0xf2000ca3,0xd1fc0000,0x0010f200 + .long 0x0d23f200,0x00a3f200,0x0822f210,0x48a2f21f + .long 0xd030f200,0x0422f200,0x9000f22e,0x4822ff84 + .long 0x60ff0000,0x142af23c,0x58380001,0xf2c10000 + .long 0x1678f200,0x0080f23a,0x44a8f64e,0xf23a4422 + .long 0xf648f200,0x04a2f200,0x00a0f227,0xe00cf200 + .long 0x0400f200,0x0023f22e,0x6880ff84,0xf2000080 + .long 0xf20004a3,0xf23a5580,0xf660f23a,0x5500f662 + .long 0xf20005a3,0xf2000523,0xf23a55a2,0xf65cf23a + .long 0x5522f65e,0xf2000ca3,0xf2000123,0xf23a54a2 + .long 0xf658f22e,0x4823ff84,0xf20008a2,0xf21fd030 + .long 0xf2000423,0xf2009000,0xf22e4822,0xff8460ff + .long 0x0000139c,0x60ff0000,0x12102d7c,0xffffff9c + .long 0xff5448e7,0x3f002610,0x28280004,0x2a280008 + .long 0x42824a84,0x66342805,0x42857420,0x4286edc4 + .long 0x6000edac,0xd4862d43,0xff842d44,0xff882d45 + .long 0xff8c4482,0x2d42ff54,0xf22e4800,0xff844cdf + .long 0x00fc41ee,0xff846000,0xfe0c4286,0xedc46000 + .long 0x2406edac,0x2e05edad,0x44860686,0x00000020 + .long 0xecaf8887,0x2d43ff84,0x2d44ff88,0x2d45ff8c + .long 0x44822d42,0xff54f22e,0x4800ff84,0x4cdf00fc + .long 0x41eeff84,0x6000fdce,0xf2104800,0xf2000018 + .long 0xf23a4838,0xf5a4f292,0x0014f200,0x9000123c + .long 0x0003f210,0x480060ff,0x000012d6,0xf2104800 + .long 0x2d7c0000,0x0000ff54,0xf2000080,0xf23a4422 + .long 0xf508f22e,0x6800ff84,0x3d6eff88,0xff86222e + .long 0xff840c81,0x00000000,0x6f0000da,0x0c813ffe + .long 0x80006d00,0xfda20c81,0x3fffc000,0x6e00fd98 + .long 0x0c813ffe,0xf07d6d00,0x001a0c81,0x3fff8841 + .long 0x6e000010,0xf20004a2,0xf23a4422,0xf4bc6000 + .long 0xfe762d6e,0xff88ff94,0x02aefe00,0x0000ff94 + .long 0x00ae0100,0x0000ff94,0x0c813fff,0x80006c44 + .long 0xf23a4400,0xf4fc2d7c,0x3fff0000,0xff9042ae + .long 0xff98f22e,0x4828ff90,0x222eff94,0x02817e00 + .long 0x0000e081,0xe081e881,0xf20004a2,0xf227e00c + .long 0xf2000422,0x41faf4e2,0xd1c1f23a,0x4480f466 + .long 0x6000fd76,0xf23a4400,0xf4502d7c,0x3fff0000 + .long 0xff9042ae,0xff98f22e,0x4828ff90,0x222eff94 + .long 0x02817e00,0x0000e081,0xe081e881,0xf2000422 + .long 0xf227e00c,0x41faf4a2,0xd1c1f23a,0x4480f41e + .long 0x6000fd36,0x0c810000,0x00006d10,0xf23a4400 + .long 0xf414f200,0x900060ff,0x00001014,0xf23a4400 + .long 0xf3fcf200,0x900060ff,0x0000102e,0x60ff0000 + .long 0x10422210,0x32280004,0x02817fff,0xffff0c81 + .long 0x3fff8000,0x6c56f210,0x4818f200,0x0080f200 + .long 0x049af200,0x0022f23c,0x44a23f80,0x0000f200 + .long 0x04202210,0x02818000,0x00000081,0x3f000000 + .long 0x2f012f00,0x4280f227,0xe00141d7,0x61ffffff + .long 0xfe5adffc,0x0000000c,0x201ff200,0x9000123c + .long 0x0000f21f,0x442360ff,0x00001136,0xf2104818 + .long 0xf23c4438,0x3f800000,0xf2d20000,0x0fac60ff + .long 0x00000f7c,0x60ff0000,0x0fba3ffd,0x0000de5b + .long 0xd8a93728,0x71950000,0x00003fff,0x0000b8aa + .long 0x3b295c17,0xf0bc0000,0x0000f23c,0x58000001 + .long 0xf2104838,0xf2c10000,0x13502210,0x6d000090 + .long 0x2f004280,0x61ffffff,0xfba2f21f,0x9000f23a + .long 0x4823ffb8,0x60ff0000,0x10d62210,0x6d000070 + .long 0x2f004280,0x61ffffff,0xfd34f21f,0x9000f23a + .long 0x4823ff98,0x60ff0000,0x10c62210,0x6d000050 + .long 0x22280008,0x662e2228,0x00040281,0x7fffffff + .long 0x66223210,0x02810000,0x7fff0481,0x00003fff + .long 0x67ff0000,0x12e4f200,0x9000f201,0x400060ff + .long 0x0000107c,0x2f004280,0x61ffffff,0xfb2ef21f + .long 0x9000f23a,0x4823ff54,0x60ff0000,0x106260ff + .long 0x00000ed6,0x22106d00,0xfff62f00,0x428061ff + .long 0xfffffcba,0xf21f9000,0xf23a4823,0xff2e60ff + .long 0x0000104c,0x406a934f,0x0979a371,0x3f734413 + .long 0x509f8000,0xbfcd0000,0xc0219dc1,0xda994fd2 + .long 0x00000000,0x40000000,0x935d8ddd,0xaaa8ac17 + .long 0x00000000,0x3ffe0000,0xb17217f7,0xd1cf79ac + .long 0x00000000,0x3f56c16d,0x6f7bd0b2,0x3f811112 + .long 0x302c712c,0x3fa55555,0x55554cc1,0x3fc55555 + .long 0x55554a54,0x3fe00000,0x00000000,0x00000000 + .long 0x00000000,0x3fff0000,0x80000000,0x00000000 + .long 0x3f738000,0x3fff0000,0x8164d1f3,0xbc030773 + .long 0x3fbef7ca,0x3fff0000,0x82cd8698,0xac2ba1d7 + .long 0x3fbdf8a9,0x3fff0000,0x843a28c3,0xacde4046 + .long 0x3fbcd7c9,0x3fff0000,0x85aac367,0xcc487b15 + .long 0xbfbde8da,0x3fff0000,0x871f6196,0x9e8d1010 + .long 0x3fbde85c,0x3fff0000,0x88980e80,0x92da8527 + .long 0x3fbebbf1,0x3fff0000,0x8a14d575,0x496efd9a + .long 0x3fbb80ca,0x3fff0000,0x8b95c1e3,0xea8bd6e7 + .long 0xbfba8373,0x3fff0000,0x8d1adf5b,0x7e5ba9e6 + .long 0xbfbe9670,0x3fff0000,0x8ea4398b,0x45cd53c0 + .long 0x3fbdb700,0x3fff0000,0x9031dc43,0x1466b1dc + .long 0x3fbeeeb0,0x3fff0000,0x91c3d373,0xab11c336 + .long 0x3fbbfd6d,0x3fff0000,0x935a2b2f,0x13e6e92c + .long 0xbfbdb319,0x3fff0000,0x94f4efa8,0xfef70961 + .long 0x3fbdba2b,0x3fff0000,0x96942d37,0x20185a00 + .long 0x3fbe91d5,0x3fff0000,0x9837f051,0x8db8a96f + .long 0x3fbe8d5a,0x3fff0000,0x99e04593,0x20b7fa65 + .long 0xbfbcde7b,0x3fff0000,0x9b8d39b9,0xd54e5539 + .long 0xbfbebaaf,0x3fff0000,0x9d3ed9a7,0x2cffb751 + .long 0xbfbd86da,0x3fff0000,0x9ef53260,0x91a111ae + .long 0xbfbebedd,0x3fff0000,0xa0b0510f,0xb9714fc2 + .long 0x3fbcc96e,0x3fff0000,0xa2704303,0x0c496819 + .long 0xbfbec90b,0x3fff0000,0xa43515ae,0x09e6809e + .long 0x3fbbd1db,0x3fff0000,0xa5fed6a9,0xb15138ea + .long 0x3fbce5eb,0x3fff0000,0xa7cd93b4,0xe965356a + .long 0xbfbec274,0x3fff0000,0xa9a15ab4,0xea7c0ef8 + .long 0x3fbea83c,0x3fff0000,0xab7a39b5,0xa93ed337 + .long 0x3fbecb00,0x3fff0000,0xad583eea,0x42a14ac6 + .long 0x3fbe9301,0x3fff0000,0xaf3b78ad,0x690a4375 + .long 0xbfbd8367,0x3fff0000,0xb123f581,0xd2ac2590 + .long 0xbfbef05f,0x3fff0000,0xb311c412,0xa9112489 + .long 0x3fbdfb3c,0x3fff0000,0xb504f333,0xf9de6484 + .long 0x3fbeb2fb,0x3fff0000,0xb6fd91e3,0x28d17791 + .long 0x3fbae2cb,0x3fff0000,0xb8fbaf47,0x62fb9ee9 + .long 0x3fbcdc3c,0x3fff0000,0xbaff5ab2,0x133e45fb + .long 0x3fbee9aa,0x3fff0000,0xbd08a39f,0x580c36bf + .long 0xbfbeaefd,0x3fff0000,0xbf1799b6,0x7a731083 + .long 0xbfbcbf51,0x3fff0000,0xc12c4cca,0x66709456 + .long 0x3fbef88a,0x3fff0000,0xc346ccda,0x24976407 + .long 0x3fbd83b2,0x3fff0000,0xc5672a11,0x5506dadd + .long 0x3fbdf8ab,0x3fff0000,0xc78d74c8,0xabb9b15d + .long 0xbfbdfb17,0x3fff0000,0xc9b9bd86,0x6e2f27a3 + .long 0xbfbefe3c,0x3fff0000,0xcbec14fe,0xf2727c5d + .long 0xbfbbb6f8,0x3fff0000,0xce248c15,0x1f8480e4 + .long 0xbfbcee53,0x3fff0000,0xd06333da,0xef2b2595 + .long 0xbfbda4ae,0x3fff0000,0xd2a81d91,0xf12ae45a + .long 0x3fbc9124,0x3fff0000,0xd4f35aab,0xcfedfa1f + .long 0x3fbeb243,0x3fff0000,0xd744fcca,0xd69d6af4 + .long 0x3fbde69a,0x3fff0000,0xd99d15c2,0x78afd7b6 + .long 0xbfb8bc61,0x3fff0000,0xdbfbb797,0xdaf23755 + .long 0x3fbdf610,0x3fff0000,0xde60f482,0x5e0e9124 + .long 0xbfbd8be1,0x3fff0000,0xe0ccdeec,0x2a94e111 + .long 0x3fbacb12,0x3fff0000,0xe33f8972,0xbe8a5a51 + .long 0x3fbb9bfe,0x3fff0000,0xe5b906e7,0x7c8348a8 + .long 0x3fbcf2f4,0x3fff0000,0xe8396a50,0x3c4bdc68 + .long 0x3fbef22f,0x3fff0000,0xeac0c6e7,0xdd24392f + .long 0xbfbdbf4a,0x3fff0000,0xed4f301e,0xd9942b84 + .long 0x3fbec01a,0x3fff0000,0xefe4b99b,0xdcdaf5cb + .long 0x3fbe8cac,0x3fff0000,0xf281773c,0x59ffb13a + .long 0xbfbcbb3f,0x3fff0000,0xf5257d15,0x2486cc2c + .long 0x3fbef73a,0x3fff0000,0xf7d0df73,0x0ad13bb9 + .long 0xbfb8b795,0x3fff0000,0xfa83b2db,0x722a033a + .long 0x3fbef84b,0x3fff0000,0xfd3e0c0c,0xf486c175 + .long 0xbfbef581,0xf210d080,0x22103228,0x0004f22e + .long 0x6800ff84,0x02817fff,0xffff0c81,0x3fb98000 + .long 0x6c046000,0x00880c81,0x400d80c0,0x6f046000 + .long 0x007cf200,0x0080f23c,0x44a34280,0x0000f22e + .long 0x6080ff54,0x2f0243fa,0xfbbcf22e,0x4080ff54 + .long 0x222eff54,0x24010281,0x0000003f,0xe981d3c1 + .long 0xec822202,0xe2819481,0x06820000,0x3ffff227 + .long 0xe00cf23c,0x44a33c80,0x00002d59,0xff842d59 + .long 0xff882d59,0xff8c3d59,0xff90f200,0x04283d59 + .long 0xff94426e,0xff9642ae,0xff98d36e,0xff84f23a + .long 0x4823fb22,0xd36eff90,0x60000100,0x0c813fff + .long 0x80006e12,0xf2009000,0xf23c4422,0x3f800000 + .long 0x60ff0000,0x0b12222e,0xff840c81,0x00000000 + .long 0x6d0660ff,0x00000ac8,0x60ff0000,0x0a1af200 + .long 0x9000f23c,0x44003f80,0x00002210,0x00810080 + .long 0x0001f201,0x442260ff,0x00000adc,0xf210d080 + .long 0x22103228,0x0004f22e,0x6800ff84,0x02817fff + .long 0xffff0c81,0x3fb98000,0x6c046000,0xff900c81 + .long 0x400b9b07,0x6f046000,0xff84f200,0x0080f23a + .long 0x54a3fa62,0xf22e6080,0xff542f02,0x43fafac6 + .long 0xf22e4080,0xff54222e,0xff542401,0x02810000 + .long 0x003fe981,0xd3c1ec82,0x2202e281,0x94810682 + .long 0x00003fff,0xf227e00c,0xf2000500,0xf23a54a3 + .long 0xfa2c2d59,0xff84f23a,0x4923fa2a,0x2d59ff88 + .long 0x2d59ff8c,0xf2000428,0x3d59ff90,0xf2000828 + .long 0x3d59ff94,0x426eff96,0x42aeff98,0xf23a4823 + .long 0xfa14d36e,0xff84d36e,0xff90f200,0x0080f200 + .long 0x04a3f23a,0x5500fa1e,0xf23a5580,0xfa20f200 + .long 0x0523f200,0x05a3f23a,0x5522fa1a,0xf23a55a2 + .long 0xfa1cf200,0x0523f200,0x05a3f23a,0x5522fa16 + .long 0xf20001a3,0xf2000523,0xf2000c22,0xf2000822 + .long 0xf21fd030,0xf22e4823,0xff84f22e,0x4822ff90 + .long 0xf22e4822,0xff84f200,0x90003d42,0xff84241f + .long 0x2d7c8000,0x0000ff88,0x42aeff8c,0x123c0000 + .long 0xf22e4823,0xff8460ff,0x00000996,0xf2009000 + .long 0xf23c4400,0x3f800000,0x22100081,0x00800001 + .long 0xf2014422,0x60ff0000,0x098e2f01,0xe8082200 + .long 0x02410003,0x0240000c,0x48403001,0x221f4a01 + .long 0x671e0c01,0x000a6f12,0x0c01000e,0x6f3c0c01 + .long 0x002f6f06,0x0c01003f,0x6f6260ff,0x00000baa + .long 0x4a00660c,0x41fb0170,0x000000d6,0x60000086 + .long 0x0c000003,0x670a41fb,0x01700000,0x00d06074 + .long 0x41fb0170,0x000000d2,0x606a0401,0x000b4a00 + .long 0x661041fb,0x01700000,0x00cc0c01,0x00026f54 + .long 0x605a0c00,0x0003670a,0x41fb0170,0x000000f2 + .long 0x60e841fb,0x01700000,0x012460de,0x04010030 + .long 0x4a006616,0x41fb0170,0x0000014e,0x0c010001 + .long 0x6f220c01,0x00076f24,0x601a0c00,0x0003670a + .long 0x41fb0170,0x000001f2,0x60e241fb,0x01700000 + .long 0x02a860d8,0x00ae0000,0x0208ff64,0xc2fc000c + .long 0x48404a00,0x6608f230,0xd0801000,0x4e754840 + .long 0x3d701000,0xff902d70,0x1004ff94,0x2d701008 + .long 0xff982200,0x428041ee,0xff904268,0x000261ff + .long 0x000062c6,0xf210d080,0x4e7551fc,0x40000000 + .long 0xc90fdaa2,0x2168c235,0x40000000,0xc90fdaa2 + .long 0x2168c234,0x40000000,0xc90fdaa2,0x2168c235 + .long 0x3ffd0000,0x9a209a84,0xfbcff798,0x40000000 + .long 0xadf85458,0xa2bb4a9a,0x3fff0000,0xb8aa3b29 + .long 0x5c17f0bc,0x3ffd0000,0xde5bd8a9,0x37287195 + .long 0x00000000,0x00000000,0x00000000,0x3ffd0000 + .long 0x9a209a84,0xfbcff798,0x40000000,0xadf85458 + .long 0xa2bb4a9a,0x3fff0000,0xb8aa3b29,0x5c17f0bb + .long 0x3ffd0000,0xde5bd8a9,0x37287195,0x00000000 + .long 0x00000000,0x00000000,0x3ffd0000,0x9a209a84 + .long 0xfbcff799,0x40000000,0xadf85458,0xa2bb4a9b + .long 0x3fff0000,0xb8aa3b29,0x5c17f0bc,0x3ffd0000 + .long 0xde5bd8a9,0x37287195,0x00000000,0x00000000 + .long 0x00000000,0x3ffe0000,0xb17217f7,0xd1cf79ac + .long 0x40000000,0x935d8ddd,0xaaa8ac17,0x3fff0000 + .long 0x80000000,0x00000000,0x40020000,0xa0000000 + .long 0x00000000,0x40050000,0xc8000000,0x00000000 + .long 0x400c0000,0x9c400000,0x00000000,0x40190000 + .long 0xbebc2000,0x00000000,0x40340000,0x8e1bc9bf + .long 0x04000000,0x40690000,0x9dc5ada8,0x2b70b59e + .long 0x40d30000,0xc2781f49,0xffcfa6d5,0x41a80000 + .long 0x93ba47c9,0x80e98ce0,0x43510000,0xaa7eebfb + .long 0x9df9de8e,0x46a30000,0xe319a0ae,0xa60e91c7 + .long 0x4d480000,0xc9767586,0x81750c17,0x5a920000 + .long 0x9e8b3b5d,0xc53d5de5,0x75250000,0xc4605202 + .long 0x8a20979b,0x3ffe0000,0xb17217f7,0xd1cf79ab + .long 0x40000000,0x935d8ddd,0xaaa8ac16,0x3fff0000 + .long 0x80000000,0x00000000,0x40020000,0xa0000000 + .long 0x00000000,0x40050000,0xc8000000,0x00000000 + .long 0x400c0000,0x9c400000,0x00000000,0x40190000 + .long 0xbebc2000,0x00000000,0x40340000,0x8e1bc9bf + .long 0x04000000,0x40690000,0x9dc5ada8,0x2b70b59d + .long 0x40d30000,0xc2781f49,0xffcfa6d5,0x41a80000 + .long 0x93ba47c9,0x80e98cdf,0x43510000,0xaa7eebfb + .long 0x9df9de8d,0x46a30000,0xe319a0ae,0xa60e91c6 + .long 0x4d480000,0xc9767586,0x81750c17,0x5a920000 + .long 0x9e8b3b5d,0xc53d5de4,0x75250000,0xc4605202 + .long 0x8a20979a,0x3ffe0000,0xb17217f7,0xd1cf79ac + .long 0x40000000,0x935d8ddd,0xaaa8ac17,0x3fff0000 + .long 0x80000000,0x00000000,0x40020000,0xa0000000 + .long 0x00000000,0x40050000,0xc8000000,0x00000000 + .long 0x400c0000,0x9c400000,0x00000000,0x40190000 + .long 0xbebc2000,0x00000000,0x40340000,0x8e1bc9bf + .long 0x04000000,0x40690000,0x9dc5ada8,0x2b70b59e + .long 0x40d30000,0xc2781f49,0xffcfa6d6,0x41a80000 + .long 0x93ba47c9,0x80e98ce0,0x43510000,0xaa7eebfb + .long 0x9df9de8e,0x46a30000,0xe319a0ae,0xa60e91c7 + .long 0x4d480000,0xc9767586,0x81750c18,0x5a920000 + .long 0x9e8b3b5d,0xc53d5de5,0x75250000,0xc4605202 + .long 0x8a20979b,0x2f003229,0x00005bee,0xff540281 + .long 0x00007fff,0x30280000,0x02407fff,0x0c403fff + .long 0x6d0000c0,0x0c40400c,0x6e0000a4,0xf2284803 + .long 0x0000f200,0x6000f23c,0x88000000,0x00004a29 + .long 0x00046b5e,0x2f003d69,0x0000ff84,0x2d690004 + .long 0xff882d69,0x0008ff8c,0x41eeff84,0x61ff0000 + .long 0x60ba4480,0xd09ff22e,0xd080ff84,0x0c40c001 + .long 0x6c36f21f,0x9000223c,0x80000000,0x0480ffff + .long 0xc0014480,0x0c000020,0x6c0ae0a9,0x42a72f01 + .long 0x42a76028,0x04000020,0xe0a92f01,0x42a742a7 + .long 0x601af229,0xd0800000,0xf21f9000,0x06403fff + .long 0x484042a7,0x2f3c8000,0x00002f00,0xf200b000 + .long 0x123c0000,0xf21f4823,0x60ff0000,0x04ce201f + .long 0xc1494a29,0x00006bff,0x0000038c,0x60ff0000 + .long 0x03c44a29,0x00046a16,0x201ff200,0x9000123c + .long 0x0003f229,0x48000000,0x60ff0000,0x049e201f + .long 0x204960ff,0x000002e2,0x00010000,0x80000000 + .long 0x00000000,0x00000000,0x422eff65,0x2f00422e + .long 0xff5c600c,0x422eff65,0x2f001d7c,0x0001ff5c + .long 0x48e73f00,0x36280000,0x3d43ff58,0x02830000 + .long 0x7fff2828,0x00042a28,0x00084a83,0x663c263c + .long 0x00003ffe,0x4a846616,0x28054285,0x04830000 + .long 0x00204286,0xedc46000,0xedac9686,0x60224286 + .long 0xedc46000,0x9686edac,0x2e05edad,0x44860686 + .long 0x00000020,0xecaf8887,0x60060683,0x00003ffe + .long 0x30290000,0x3d40ff5a,0x322eff58,0xb1810281 + .long 0x00008000,0x3d41ff5e,0x02800000,0x7fff2229 + .long 0x00042429,0x00084a80,0x663c203c,0x00003ffe + .long 0x4a816616,0x22024282,0x04800000,0x00204286 + .long 0xedc16000,0xeda99086,0x60224286,0xedc16000 + .long 0x9086eda9,0x2e02edaa,0x44860686,0x00000020 + .long 0xecaf8287,0x60060680,0x00003ffe,0x2d43ff54 + .long 0x2f009083,0x42864283,0x227c0000,0x00004a80 + .long 0x6c06201f,0x6000006a,0x588f4a86,0x6e0eb284 + .long 0x6608b485,0x66046000,0x01366508,0x94859384 + .long 0x42865283,0x4a80670e,0xd683d482,0xe39155c6 + .long 0x52895380,0x60d4202e,0xff544a81,0x66162202 + .long 0x42820480,0x00000020,0x4286edc1,0x6000eda9 + .long 0x9086601c,0x4286edc1,0x60006b14,0x9086eda9 + .long 0x2e02edaa,0x44860686,0x00000020,0xecaf8287 + .long 0x0c800000,0x41fe6c2a,0x3d40ff90,0x2d41ff94 + .long 0x2d42ff98,0x2c2eff54,0x3d46ff84,0x2d44ff88 + .long 0x2d45ff8c,0xf22e4800,0xff901d7c,0x0001ff5d + .long 0x60362d41,0xff942d42,0xff980480,0x00003ffe + .long 0x3d40ff90,0x2c2eff54,0x04860000,0x3ffe2d46 + .long 0xff54f22e,0x4800ff90,0x3d46ff84,0x2d44ff88 + .long 0x2d45ff8c,0x422eff5d,0x4a2eff5c,0x67222c2e + .long 0xff545386,0xb0866d18,0x6e0eb284,0x6608b485 + .long 0x66046000,0x007a6508,0xf22e4828,0xff845283 + .long 0x3c2eff5a,0x6c04f200,0x001a4286,0x3c2eff5e + .long 0x7e08eeae,0x02830000,0x007f8686,0x1d43ff65 + .long 0x4cdf00fc,0x201ff200,0x90004a2e,0xff5d6710 + .long 0x123c0000,0xf23a4823,0xfdc060ff,0x0000024c + .long 0x123c0003,0xf2000000,0x60ff0000,0x023e5283 + .long 0x0c800000,0x00086c04,0xe1ab6002,0x4283f23c + .long 0x44000000,0x0000422e,0xff5d6000,0xff942c03 + .long 0x02860000,0x00014a86,0x6700ff86,0x52833c2e + .long 0xff5a0a86,0x00008000,0x3d46ff5a,0x6000ff72 + .long 0x7fff0000,0xffffffff,0xffffffff,0x4a280000 + .long 0x6b12f23c,0x44007f80,0x000000ae,0x02000410 + .long 0xff644e75,0xf23c4400,0xff800000,0x00ae0a00 + .long 0x0410ff64,0x4e7500ae,0x01002080,0xff64f23a + .long 0xd080ffbe,0x4e7500ae,0x00000800,0xff646008 + .long 0x00ae0000,0x0a28ff64,0x22482200,0x020100c0 + .long 0x660e4a28,0x00006a18,0x08ee0003,0xff646010 + .long 0x2f094a28,0x00005bc1,0x61ff0000,0x0196225f + .long 0xf210d080,0x102eff62,0x0200000a,0x66024e75 + .long 0x3d690000,0xff842d69,0x0004ff88,0x2d690008 + .long 0xff8c41ee,0xff8461ff,0x00005cd0,0x06800000 + .long 0x6000026e,0x8000ff84,0x816eff84,0xf22ed040 + .long 0xff844e75,0x00ae0000,0x0a28ff64,0x4a105bc1 + .long 0x61ff0000,0x013ef210,0xd080f23c,0x44800000 + .long 0x00004e75,0x00ae0000,0x0a28ff64,0x51c161ff + .long 0x00000120,0xf210d080,0xf23c4480,0x00000000 + .long 0x4e7500ae,0x00001048,0xff641200,0x020100c0 + .long 0x675c4a28,0x00046b24,0x3d680000,0xff842d68 + .long 0x0004ff88,0x2d680008,0xff8c41ee,0xff8448e7 + .long 0xc08061ff,0x00005c44,0x4cdf0103,0x0c010040 + .long 0x660e4aa8,0x00086614,0x4a280007,0x660e601e + .long 0x22280008,0x02810000,0x07ff6712,0x00ae0000 + .long 0x0200ff64,0x600800ae,0x00001248,0xff644a28 + .long 0x00005bc1,0x61ff0000,0x5f261d40,0xff64f210 + .long 0xd080f23c,0x44800000,0x00004e75,0x00ae0000 + .long 0x1248ff64,0x51c161ff,0x00005f04,0x1d40ff64 + .long 0xf210d080,0xf23c4480,0x00000000,0x4e75f327 + .long 0x4a2f0002,0x6b2edffc,0x0000000c,0xf294000e + .long 0xf2810014,0x006e0208,0xff664e75,0x00ae0800 + .long 0x0208ff64,0x4e751d7c,0x0004ff64,0x006e0208 + .long 0xff664e75,0x006e0208,0xff6661ff,0x00000bae + .long 0xdffc0000,0x000c4e75,0xf3274a2f,0x00026bea + .long 0xdffc0000,0x000cf200,0xa80081ae,0xff644e75 + .long 0x00ae0000,0x0a28ff64,0x02410010,0xe8080200 + .long 0x000f8001,0x2200e309,0x1d7b000a,0xff6441fb + .long 0x16204e75,0x04040400,0x04040400,0x04040400 + .long 0x00000000,0x0c0c080c,0x0c0c080c,0x0c0c080c + .long 0x00000000,0x00000000,0x00000000,0x00000000 + .long 0x00000000,0x00000000,0x00000000,0x00000000 + .long 0x00000000,0x00000000,0x00000000,0x00000000 + .long 0x00000000,0x00000000,0x00000001,0x00000000 + .long 0x3f810000,0x00000000,0x00000000,0x00000000 + .long 0x3f810000,0x00000000,0x00000000,0x00000000 + .long 0x3f810000,0x00000000,0x00000000,0x00000000 + .long 0x3f810000,0x00000100,0x00000000,0x00000000 + .long 0x3c010000,0x00000000,0x00000000,0x00000000 + .long 0x3c010000,0x00000000,0x00000000,0x00000000 + .long 0x3c010000,0x00000000,0x00000000,0x00000000 + .long 0x3c010000,0x00000000,0x00000800,0x00000000 + .long 0x00000000,0x00000000,0x00000000,0x00000000 + .long 0x00000000,0x00000000,0x00000000,0x00000000 + .long 0x00000000,0x00000000,0x00000000,0x00000000 + .long 0x00000000,0x00000000,0x00000000,0x00000000 + .long 0x80000000,0x00000000,0x00000000,0x00000000 + .long 0x80000000,0x00000000,0x00000000,0x00000000 + .long 0x80000000,0x00000000,0x00000001,0x00000000 + .long 0x80000000,0x00000000,0x00000000,0x00000000 + .long 0xbf810000,0x00000000,0x00000000,0x00000000 + .long 0xbf810000,0x00000000,0x00000000,0x00000000 + .long 0xbf810000,0x00000100,0x00000000,0x00000000 + .long 0xbf810000,0x00000000,0x00000000,0x00000000 + .long 0xbc010000,0x00000000,0x00000000,0x00000000 + .long 0xbc010000,0x00000000,0x00000000,0x00000000 + .long 0xbc010000,0x00000000,0x00000800,0x00000000 + .long 0xbc010000,0x00000000,0x00000000,0x00000000 + .long 0x4a280000,0x6b10f23c,0x44000000,0x00001d7c + .long 0x0004ff64,0x4e75f23c,0x44008000,0x00001d7c + .long 0x000cff64,0x4e754a29,0x00006bea,0x60d84a28 + .long 0x00006b10,0xf23c4400,0x7f800000,0x1d7c0002 + .long 0xff644e75,0xf23c4400,0xff800000,0x1d7c000a + .long 0xff644e75,0x4a290000,0x6bea60d8,0x4a280000 + .long 0x6ba460d0,0x4a280000,0x6b00fbbc,0x60c64a28 + .long 0x00006b16,0x60be4a28,0x00006b0e,0xf23c4400 + .long 0x3f800000,0x422eff64,0x4e75f23c,0x4400bf80 + .long 0x00001d7c,0x0008ff64,0x4e753fff,0x0000c90f + .long 0xdaa22168,0xc235bfff,0x0000c90f,0xdaa22168 + .long 0xc2354a28,0x00006b0e,0xf2009000,0xf23a4800 + .long 0xffda6000,0xfcf0f200,0x9000f23a,0x4800ffd8 + .long 0x6000fcea,0xf23c4480,0x3f800000,0x4a280000 + .long 0x6a10f23c,0x44008000,0x00001d7c,0x000cff64 + .long 0x6040f23c,0x44000000,0x00001d7c,0x0004ff64 + .long 0x6030f23a,0x4880faea,0x61ff0000,0x00286000 + .long 0xfb16f228,0x48800000,0x61ff0000,0x00186000 + .long 0x030ef228,0x48800000,0x61ff0000,0x00086000 + .long 0x02ee102e,0xff430240,0x0007303b,0x02064efb + .long 0x00020010,0x00180020,0x0026002c,0x00320038 + .long 0x003ef22e,0xf040ffdc,0x4e75f22e,0xf040ffe8 + .long 0x4e75f200,0x05004e75,0xf2000580,0x4e75f200 + .long 0x06004e75,0xf2000680,0x4e75f200,0x07004e75 + .long 0xf2000780,0x4e75122e,0xff4f67ff,0xfffff7dc + .long 0x0c010001,0x67000096,0x0c010002,0x67ffffff + .long 0xfa880c01,0x000467ff,0xfffff7c0,0x0c010005 + .long 0x67ff0000,0x024060ff,0x0000024a,0x122eff4f + .long 0x67ffffff,0xfa640c01,0x000167ff,0xfffffa5a + .long 0x0c010002,0x67ffffff,0xfa500c01,0x000467ff + .long 0xfffffa46,0x0c010003,0x67ff0000,0x021860ff + .long 0x00000202,0x122eff4f,0x67ff0000,0x004e0c01 + .long 0x000167ff,0x00000028,0x0c010002,0x67ffffff + .long 0xfa180c01,0x000467ff,0x00000030,0x0c010003 + .long 0x67ff0000,0x01e060ff,0x000001ca,0x12280000 + .long 0x10290000,0xb1010201,0x00801d41,0xff654a00 + .long 0x6a00fdc4,0x6000fdd0,0x422eff65,0x2f001228 + .long 0x00001029,0x0000b101,0x02010080,0x1d41ff65 + .long 0x0c2e0004,0xff4f660c,0x41e90000,0x201f60ff + .long 0xfffff9c6,0xf21f9000,0xf2294800,0x00004a29 + .long 0x00006b02,0x4e751d7c,0x0008ff64,0x4e75122e + .long 0xff4f67ff,0xfffff6e0,0x0c010001,0x6700ff8e + .long 0x0c010002,0x67ffffff,0xf9800c01,0x000467ff + .long 0xfffff6c4,0x0c010003,0x67ff0000,0x014860ff + .long 0x00000132,0x122eff4f,0x67ffffff,0xf95c0c01 + .long 0x000167ff,0xfffff952,0x0c010002,0x67ffffff + .long 0xf9480c01,0x000467ff,0xfffff93e,0x0c010003 + .long 0x67ff0000,0x011060ff,0x000000fa,0x122eff4f + .long 0x6700ff46,0x0c010001,0x6700ff22,0x0c010002 + .long 0x67ffffff,0xf9140c01,0x000467ff,0xffffff2c + .long 0x0c010003,0x67ff0000,0x00dc60ff,0x000000c6 + .long 0x122eff4f,0x67ffffff,0xf51e0c01,0x000167ff + .long 0xfffffce6,0x0c010002,0x67ffffff,0xfd0a0c01 + .long 0x000467ff,0xfffff500,0x0c010003,0x67ff0000 + .long 0x00a460ff,0x0000008e,0x122eff4f,0x67ffffff + .long 0xf4e60c01,0x000167ff,0xfffffcae,0x0c010002 + .long 0x67ffffff,0xfcd20c01,0x000467ff,0xfffff4c8 + .long 0x0c010003,0x67ff0000,0x006c60ff,0x00000056 + .long 0x122eff4f,0x67ffffff,0xf8800c01,0x000367ff + .long 0x00000052,0x0c010005,0x67ff0000,0x003860ff + .long 0xfffff866,0x122eff4f,0x0c010003,0x67340c01 + .long 0x0005671e,0x6058122e,0xff4f0c01,0x00036708 + .long 0x0c010005,0x670c6036,0x00ae0100,0x4080ff64 + .long 0x6010f229,0x48000000,0xf200a800,0x81aeff64 + .long 0x4e75f229,0x48000000,0x4a290000,0x6b081d7c + .long 0x0001ff64,0x4e751d7c,0x0009ff64,0x4e75f228 + .long 0x48000000,0xf200a800,0x81aeff64,0x4e75f228 + .long 0x48000000,0x4a280000,0x6bdc1d7c,0x0001ff64 + .long 0x4e751d7c,0x0009ff64,0x4e75122e,0xff4e67ff + .long 0xffffd936,0x0c010001,0x67ffffff,0xfba60c01 + .long 0x000267ff,0xfffffbca,0x0c010004,0x67ffffff + .long 0xd9f60c01,0x000367ff,0xffffffb6,0x60ffffff + .long 0xffa0122e,0xff4e67ff,0xffffe620,0x0c010001 + .long 0x67ffffff,0xfb6e0c01,0x000267ff,0xfffffbc8 + .long 0x0c010004,0x67ffffff,0xe7560c01,0x000367ff + .long 0xffffff7e,0x60ffffff,0xff68122e,0xff4e67ff + .long 0xffffd4d2,0x0c010001,0x67ffffff,0xfb360c01 + .long 0x000267ff,0xfffffb9a,0x0c010004,0x67ffffff + .long 0xd76a0c01,0x000367ff,0xffffff46,0x60ffffff + .long 0xff30122e,0xff4e67ff,0xffffd972,0x0c010001 + .long 0x67ffffff,0xfafe0c01,0x000267ff,0xfffffb6a + .long 0x0c010004,0x67ffffff,0xdabc0c01,0x000367ff + .long 0xffffff0e,0x60ffffff,0xfef8122e,0xff4e67ff + .long 0xffffca6a,0x0c010001,0x67ffffff,0xfac60c01 + .long 0x000267ff,0xfffffb6e,0x0c010004,0x67ffffff + .long 0xcc8a0c01,0x000367ff,0xfffffed6,0x60ffffff + .long 0xfec0122e,0xff4e67ff,0xffffcc76,0x0c010001 + .long 0x67ffffff,0xfa8e0c01,0x000267ff,0xfffff6aa + .long 0x0c010004,0x67ffffff,0xcd060c01,0x000367ff + .long 0xfffffe9e,0x60ffffff,0xfe88122e,0xff4e67ff + .long 0xffffe662,0x0c010001,0x67ffffff,0xfa560c01 + .long 0x000267ff,0xfffff672,0x0c010004,0x67ffffff + .long 0xe6c60c01,0x000367ff,0xfffffe66,0x60ffffff + .long 0xfe50122e,0xff4e67ff,0xffffb372,0x0c010001 + .long 0x67ffffff,0xfa1e0c01,0x000267ff,0xfffff63a + .long 0x0c010004,0x67ffffff,0xb5380c01,0x000367ff + .long 0xfffffe2e,0x60ffffff,0xfe18122e,0xff4e67ff + .long 0xffffbdfc,0x0c010001,0x67ffffff,0xf9e60c01 + .long 0x000267ff,0xfffff602,0x0c010004,0x67ffffff + .long 0xbf420c01,0x000367ff,0xfffffdf6,0x60ffffff + .long 0xfde0122e,0xff4e67ff,0xffffd17a,0x0c010001 + .long 0x67ffffff,0xfa2a0c01,0x000267ff,0xfffffa00 + .long 0x0c010004,0x67ffffff,0xd3080c01,0x000367ff + .long 0xfffffdbe,0x60ffffff,0xfda8122e,0xff4e67ff + .long 0xffffeb64,0x0c010001,0x67ffffff,0xf9f20c01 + .long 0x000267ff,0xfffff9c8,0x0c010004,0x67ffffff + .long 0xec200c01,0x000367ff,0xfffffd86,0x60ffffff + .long 0xfd70122e,0xff4e67ff,0xffffec24,0x0c010001 + .long 0x67ffffff,0xf9ba0c01,0x000267ff,0xfffff990 + .long 0x0c010004,0x67ffffff,0xed360c01,0x000367ff + .long 0xfffffd4e,0x60ffffff,0xfd38122e,0xff4e67ff + .long 0xffffe178,0x0c010001,0x67ffffff,0xf51a0c01 + .long 0x000267ff,0xfffff960,0x0c010004,0x67ffffff + .long 0xe30c0c01,0x000367ff,0xfffffd16,0x60ffffff + .long 0xfd00122e,0xff4e67ff,0xffffe582,0x0c010001 + .long 0x67ffffff,0xf4e20c01,0x000267ff,0xfffff928 + .long 0x0c010004,0x67ffffff,0xe5940c01,0x000367ff + .long 0xfffffcde,0x60ffffff,0xfcc8122e,0xff4e67ff + .long 0xffffe59a,0x0c010001,0x67ffffff,0xf4aa0c01 + .long 0x000267ff,0xfffff8f0,0x0c010004,0x67ffffff + .long 0xe5d60c01,0x000367ff,0xfffffca6,0x60ffffff + .long 0xfc90122e,0xff4e67ff,0xffffd530,0x0c010001 + .long 0x67ffffff,0xf8da0c01,0x000267ff,0xfffff888 + .long 0x0c010004,0x67ffffff,0xd5b60c01,0x000367ff + .long 0xfffffc6e,0x60ffffff,0xfc58122e,0xff4e67ff + .long 0xffffcac2,0x0c010001,0x67ffffff,0xf8de0c01 + .long 0x000267ff,0xfffff442,0x0c010004,0x67ffffff + .long 0xcb340c01,0x000367ff,0xfffffc36,0x60ffffff + .long 0xfc20122e,0xff4e67ff,0xffffb14c,0x0c010001 + .long 0x67ffffff,0xf86a0c01,0x000267ff,0xfffff40a + .long 0x0c010004,0x67ffffff,0xb30e0c01,0x000367ff + .long 0xfffffbfe,0x60ffffff,0xfbe8122e,0xff4e67ff + .long 0xffffd40e,0x0c010001,0x67ffffff,0xf7b60c01 + .long 0x000267ff,0xfffff3d2,0x0c010004,0x67ffffff + .long 0xd40c0c01,0x000367ff,0xfffffbc6,0x60ffffff + .long 0xfbb0122e,0xff4e67ff,0xffffd40a,0x0c010001 + .long 0x67ffffff,0xf77e0c01,0x000267ff,0xfffff39a + .long 0x0c010004,0x67ffffff,0xd41a0c01,0x000367ff + .long 0xfffffb8e,0x60ffffff,0xfb78122e,0xff4e67ff + .long 0xffffb292,0x0c010001,0x67ffffff,0xf81a0c01 + .long 0x000267ff,0xfffff83e,0x0c010004,0x67ffffff + .long 0xb50a0c01,0x000367ff,0xfffff83a,0x60ffffff + .long 0xf844122e,0xff4e67ff,0xfffff89e,0x0c010001 + .long 0x67ffffff,0xf8ca0c01,0x000267ff,0xfffff8f8 + .long 0x0c010004,0x67ffffff,0xf8800c01,0x000367ff + .long 0xfffffab4,0x60ffffff,0xfac0122e,0xff4e67ff + .long 0xfffff96e,0x0c010001,0x67ffffff,0xf99a0c01 + .long 0x000267ff,0xfffff9c8,0x0c010004,0x67ffffff + .long 0xf9500c01,0x000367ff,0xfffffa7c,0x60ffffff + .long 0xfa88122e,0xff4e67ff,0xfffff9d8,0x0c010001 + .long 0x67ffffff,0xfa060c01,0x000267ff,0xfffffa34 + .long 0x0c010004,0x67ffffff,0xf9ba0c01,0x000367ff + .long 0xfffffa44,0x60ffffff,0xfa500c2f,0x00070003 + .long 0x673e1d7c,0x0000ff4e,0x1d7c0000,0xff4ff22e + .long 0xf080ff78,0x41ef0004,0x43eeff78,0x0c010003 + .long 0x67160c01,0x00026708,0x61ff0000,0x02004e75 + .long 0x61ff0000,0x1b9e4e75,0x61ff0000,0x05e44e75 + .long 0x1d7c0004,0xff4e60c0,0x4afc006d,0x000005d2 + .long 0x00000fc8,0xfffffa6e,0x0000106c,0x00002314 + .long 0x00000000,0xfffffaa6,0x00000000,0xfffffade + .long 0xfffffb16,0xfffffb4e,0x00000000,0xfffffb86 + .long 0xfffffbbe,0xfffffbf6,0xfffffc2e,0xfffffc66 + .long 0xfffffc9e,0xfffffcd6,0x00000000,0xfffffd0e + .long 0xfffffd46,0xfffffd7e,0x00000000,0x00001112 + .long 0xfffffdb6,0x00000ca8,0x00000000,0xfffffdee + .long 0xfffffe26,0xfffffe5e,0xfffffe96,0x0000089e + .long 0xffffff06,0x00001b84,0x000001de,0x00001854 + .long 0xffffff3e,0xffffff76,0x00001512,0x00001f4c + .long 0x00000000,0x00000000,0x00000000,0x00000000 + .long 0x00000000,0x00000000,0x00000000,0xfffffece + .long 0xfffffece,0xfffffece,0xfffffece,0xfffffece + .long 0xfffffece,0xfffffece,0xfffffece,0x000013b0 + .long 0x00000000,0x00000f56,0x00000000,0x00000000 + .long 0x00000000,0x00000000,0x00000000,0x000005c0 + .long 0x00002302,0x00000000,0x00000000,0x000005ca + .long 0x0000230c,0x00000000,0x00000000,0x00000000 + .long 0x00000000,0x00000000,0x00000000,0x00000000 + .long 0x00000000,0x00000000,0x00000000,0x00000000 + .long 0x00000000,0x00000000,0x00000000,0x00000000 + .long 0x00000000,0x00000000,0x00000000,0x00001100 + .long 0x00000000,0x00000c96,0x00000000,0x0000110a + .long 0x00000000,0x00000ca0,0x00000000,0x0000088c + .long 0x00000000,0x00001b72,0x000001cc,0x00000896 + .long 0x00000000,0x00001b7c,0x000001d6,0x00001f3a + .long 0x00000000,0x00000000,0x00000000,0x00001f44 + .long 0xffffc001,0xffffff81,0xfffffc01,0x00004000 + .long 0x0000007f,0x000003ff,0x02000030,0x00000040 + .long 0x60080200,0x00300000,0x00802d40,0xff5c4241 + .long 0x122eff4f,0xe709822e,0xff4e6600,0x02e43d69 + .long 0x0000ff90,0x2d690004,0xff942d69,0x0008ff98 + .long 0x3d680000,0xff842d68,0x0004ff88,0x2d680008 + .long 0xff8c61ff,0x000024ce,0x2f0061ff,0x00002572 + .long 0xd197322e,0xff5eec09,0x201fb0bb,0x14846700 + .long 0x011e6d00,0x0062b0bb,0x14846700,0x021a6e00 + .long 0x014af22e,0xd080ff90,0xf22e9000,0xff5cf23c + .long 0x88000000,0x0000f22e,0x4823ff84,0xf201a800 + .long 0xf23c9000,0x00000000,0x83aeff64,0xf22ef080 + .long 0xff842f02,0x322eff84,0x24010281,0x00007fff + .long 0x02428000,0x92808242,0x3d41ff84,0x241ff22e + .long 0xd080ff84,0x4e75f22e,0xd080ff90,0xf22e9000 + .long 0xff5cf23c,0x88000000,0x0000f22e,0x4823ff84 + .long 0xf201a800,0xf23c9000,0x00000000,0x83aeff64 + .long 0x00ae0000,0x1048ff64,0x122eff62,0x02010013 + .long 0x661c082e,0x0003ff64,0x56c1202e,0xff5c61ff + .long 0x00004fcc,0x812eff64,0xf210d080,0x4e75222e + .long 0xff5c0201,0x00c06634,0xf22ef080,0xff842f02 + .long 0x322eff84,0x34010281,0x00007fff,0x92800481 + .long 0x00006000,0x02417fff,0x02428000,0x82423d41 + .long 0xff84241f,0xf22ed040,0xff8460a6,0xf22ed080 + .long 0xff90222e,0xff5c0201,0x0030f201,0x9000f22e + .long 0x4823ff84,0xf23c9000,0x00000000,0x60aaf22e + .long 0xd080ff90,0xf22e9000,0xff5cf23c,0x88000000 + .long 0x0000f22e,0x4823ff84,0xf201a800,0xf23c9000 + .long 0x00000000,0x83aeff64,0xf2000098,0xf23c58b8 + .long 0x0002f293,0xff3c6000,0xfee408ee,0x0003ff66 + .long 0xf22ed080,0xff90f23c,0x90000000,0x0010f23c + .long 0x88000000,0x0000f22e,0x4823ff84,0xf201a800 + .long 0xf23c9000,0x00000000,0x83aeff64,0x122eff62 + .long 0x0201000b,0x6620f22e,0xf080ff84,0x41eeff84 + .long 0x222eff5c,0x61ff0000,0x4dd8812e,0xff64f22e + .long 0xd080ff84,0x4e75f22e,0xd040ff90,0x222eff5c + .long 0x020100c0,0x6652f22e,0x9000ff5c,0xf23c8800 + .long 0x00000000,0xf22e48a3,0xff84f23c,0x90000000 + .long 0x0000f22e,0xf040ff84,0x2f02322e,0xff842401 + .long 0x02810000,0x7fff0242,0x80009280,0x06810000 + .long 0x60000241,0x7fff8242,0x3d41ff84,0x241ff22e + .long 0xd040ff84,0x6000ff80,0x222eff5c,0x02010030 + .long 0xf2019000,0x60a6f22e,0xd080ff90,0xf22e9000 + .long 0xff5cf23c,0x88000000,0x0000f22e,0x4823ff84 + .long 0xf201a800,0xf23c9000,0x00000000,0x83aeff64 + .long 0xf2000098,0xf23c58b8,0x0002f292,0xfde0f294 + .long 0xfefaf22e,0xd040ff90,0x222eff5c,0x020100c0 + .long 0x00010010,0xf2019000,0xf23c8800,0x00000000 + .long 0xf22e48a3,0xff84f23c,0x90000000,0x0000f200 + .long 0x0498f23c,0x58b80002,0xf293fda2,0x6000febc + .long 0x323b120a,0x4efb1006,0x4afc0030,0xfd120072 + .long 0x00cc006c,0xfd120066,0x00000000,0x00720072 + .long 0x0060006c,0x00720066,0x00000000,0x009e0060 + .long 0x009e006c,0x009e0066,0x00000000,0x006c006c + .long 0x006c006c,0x006c0066,0x00000000,0xfd120072 + .long 0x00cc006c,0xfd120066,0x00000000,0x00660066 + .long 0x00660066,0x00660066,0x00000000,0x60ff0000 + .long 0x230e60ff,0x00002284,0x60ff0000,0x227e1028 + .long 0x00001229,0x0000b101,0x6a10f23c,0x44008000 + .long 0x00001d7c,0x000cff64,0x4e75f23c,0x44000000 + .long 0x00001d7c,0x0004ff64,0x4e75f229,0xd0800000 + .long 0x10280000,0x12290000,0xb1016a10,0xf2000018 + .long 0xf200001a,0x1d7c000a,0xff644e75,0xf2000018 + .long 0x1d7c0002,0xff644e75,0xf228d080,0x00001028 + .long 0x00001229,0x0000b101,0x6ae260d0,0x02000030 + .long 0x00000040,0x60080200,0x00300000,0x00802d40 + .long 0xff5c122e,0xff4e6600,0x02620200,0x00c06600 + .long 0x007c4a28,0x00006a06,0x08ee0003,0xff64f228 + .long 0xd0800000,0x4e750200,0x00c06600,0x006008ee + .long 0x0003ff66,0x4a280000,0x6a0608ee,0x0003ff64 + .long 0xf228d080,0x0000082e,0x0003ff62,0x66024e75 + .long 0x3d680000,0xff842d68,0x0004ff88,0x2d680008 + .long 0xff8c41ee,0xff8461ff,0x00004950,0x44400640 + .long 0x6000322e,0xff840241,0x80000240,0x7fff8041 + .long 0x3d40ff84,0xf22ed040,0xff844e75,0x0c000040 + .long 0x667e3d68,0x0000ff84,0x2d680004,0xff882d68 + .long 0x0008ff8c,0x61ff0000,0x206c0c80,0x0000007f + .long 0x6c000092,0x0c80ffff,0xff816700,0x01786d00 + .long 0x00f4f23c,0x88000000,0x0000f22e,0x9000ff5c + .long 0xf22e4800,0xff84f201,0xa800f23c,0x90000000 + .long 0x000083ae,0xff642f02,0xf22ef080,0xff84322e + .long 0xff843401,0x02810000,0x7fff9280,0x02428000 + .long 0x84413d42,0xff84241f,0xf22ed080,0xff844e75 + .long 0x3d680000,0xff842d68,0x0004ff88,0x2d680008 + .long 0xff8c61ff,0x00001fee,0x0c800000,0x03ff6c00 + .long 0x00140c80,0xfffffc01,0x670000fa,0x6d000076 + .long 0x6000ff80,0x08ee0003,0xff664a2e,0xff846a06 + .long 0x08ee0003,0xff64122e,0xff620201,0x000b661a + .long 0x41eeff84,0x222eff5c,0x61ff0000,0x4a74812e + .long 0xff64f22e,0xd080ff84,0x4e752d6e,0xff88ff94 + .long 0x2d6eff8c,0xff98322e,0xff842f02,0x34010281 + .long 0x00007fff,0x92800242,0x80000681,0x00006000 + .long 0x02417fff,0x84413d42,0xff90f22e,0xd040ff90 + .long 0x241f60ac,0xf23c8800,0x00000000,0xf22e9000 + .long 0xff5cf22e,0x4800ff84,0xf23c9000,0x00000000 + .long 0xf201a800,0x83aeff64,0x00ae0000,0x1048ff64 + .long 0x122eff62,0x02010013,0x661c082e,0x0003ff64 + .long 0x56c1202e,0xff5c61ff,0x00004ae4,0x812eff64 + .long 0xf210d080,0x4e752f02,0x322eff84,0x24010281 + .long 0x00007fff,0x02428000,0x92800481,0x00006000 + .long 0x02417fff,0x82423d41,0xff84241f,0xf22ed040 + .long 0xff8460b6,0xf23c8800,0x00000000,0xf22e9000 + .long 0xff5cf22e,0x4800ff84,0xf201a800,0xf23c9000 + .long 0x00000000,0x83aeff64,0xf2000098,0xf23c58b8 + .long 0x0002f293,0xff746000,0xfe7e0c01,0x00046700 + .long 0xfdb60c01,0x000567ff,0x00001f98,0x0c010003 + .long 0x67ff0000,0x1fa2f228,0x48000000,0xf200a800 + .long 0xe1981d40,0xff644e75,0x51fc51fc,0x51fc51fc + .long 0x00003fff,0x0000007e,0x000003fe,0xffffc001 + .long 0xffffff81,0xfffffc01,0x02000030,0x00000040 + .long 0x60080200,0x00300000,0x00802d40,0xff5c4241 + .long 0x122eff4f,0xe709822e,0xff4e6600,0x02d63d69 + .long 0x0000ff90,0x2d690004,0xff942d69,0x0008ff98 + .long 0x3d680000,0xff842d68,0x0004ff88,0x2d680008 + .long 0xff8c61ff,0x00001e0e,0x2f0061ff,0x00001eb2 + .long 0x4497d197,0x322eff5e,0xec09201f,0xb0bb148e + .long 0x6f000074,0xb0bb1520,0xff7a6700,0x020c6e00 + .long 0x013cf22e,0xd080ff90,0xf22e9000,0xff5cf23c + .long 0x88000000,0x0000f22e,0x4820ff84,0xf201a800 + .long 0xf23c9000,0x00000000,0x83aeff64,0xf22ef080 + .long 0xff842f02,0x322eff84,0x24010281,0x00007fff + .long 0x02428000,0x92808242,0x3d41ff84,0x241ff22e + .long 0xd080ff84,0x4e750000,0x7fff0000,0x407f0000 + .long 0x43ff201f,0x60c62f00,0xf22ed080,0xff90f22e + .long 0x9000ff5c,0xf23c8800,0x00000000,0xf22e4820 + .long 0xff84f200,0xa800f23c,0x90000000,0x000081ae + .long 0xff64f227,0xe0013017,0xdffc0000,0x000c0280 + .long 0x00007fff,0x9097b0bb,0x14ae6db6,0x201f00ae + .long 0x00001048,0xff64122e,0xff620201,0x0013661c + .long 0x082e0003,0xff6456c1,0x202eff5c,0x61ff0000 + .long 0x48de812e,0xff64f210,0xd0804e75,0x222eff5c + .long 0x020100c0,0x6634f22e,0xf080ff84,0x2f02322e + .long 0xff843401,0x02810000,0x7fff9280,0x04810000 + .long 0x60000241,0x7fff0242,0x80008242,0x3d41ff84 + .long 0x241ff22e,0xd040ff84,0x60a6f22e,0xd080ff90 + .long 0x222eff5c,0x02010030,0xf2019000,0xf22e4820 + .long 0xff84f23c,0x90000000,0x000060aa,0x08ee0003 + .long 0xff66f22e,0xd080ff90,0xf23c9000,0x00000010 + .long 0xf23c8800,0x00000000,0xf22e4820,0xff84f201 + .long 0xa800f23c,0x90000000,0x000083ae,0xff64122e + .long 0xff620201,0x000b6620,0xf22ef080,0xff8441ee + .long 0xff84222e,0xff5c61ff,0x00004726,0x812eff64 + .long 0xf22ed080,0xff844e75,0xf22ed040,0xff90222e + .long 0xff5c0201,0x00c06652,0xf22e9000,0xff5cf23c + .long 0x88000000,0x0000f22e,0x48a0ff84,0xf23c9000 + .long 0x00000000,0xf22ef040,0xff842f02,0x322eff84 + .long 0x24010281,0x00007fff,0x02428000,0x92800681 + .long 0x00006000,0x02417fff,0x82423d41,0xff84241f + .long 0xf22ed040,0xff846000,0xff80222e,0xff5c0201 + .long 0x0030f201,0x900060a6,0xf22ed080,0xff90f22e + .long 0x9000ff5c,0xf23c8800,0x00000000,0xf22e4820 + .long 0xff84f201,0xa800f23c,0x90000000,0x000083ae + .long 0xff64f200,0x0098f23c,0x58b80001,0xf292fdee + .long 0xf294fefa,0xf22ed040,0xff90222e,0xff5c0201 + .long 0x00c00001,0x0010f201,0x9000f23c,0x88000000 + .long 0x0000f22e,0x48a0ff84,0xf23c9000,0x00000000 + .long 0xf2000498,0xf23c58b8,0x0001f293,0xfdb06000 + .long 0xfebc323b,0x120a4efb,0x10064afc,0x0030fd20 + .long 0x009e0072,0x0060fd20,0x00660000,0x00000072 + .long 0x006c0072,0x00600072,0x00660000,0x000000d0 + .long 0x00d0006c,0x006000d0,0x00660000,0x00000060 + .long 0x00600060,0x00600060,0x00660000,0x0000fd20 + .long 0x009e0072,0x0060fd20,0x00660000,0x00000066 + .long 0x00660066,0x00660066,0x00660000,0x000060ff + .long 0x00001bd8,0x60ff0000,0x1bd260ff,0x00001c50 + .long 0x10280000,0x12290000,0xb1016a10,0xf23c4400 + .long 0x80000000,0x1d7c000c,0xff644e75,0xf23c4400 + .long 0x00000000,0x1d7c0004,0xff644e75,0x006e0410 + .long 0xff661028,0x00001229,0x0000b101,0x6a10f23c + .long 0x4400ff80,0x00001d7c,0x000aff64,0x4e75f23c + .long 0x44007f80,0x00001d7c,0x0002ff64,0x4e751029 + .long 0x00001228,0x0000b101,0x6a16f229,0xd0800000 + .long 0xf2000018,0xf200001a,0x1d7c000a,0xff644e75 + .long 0xf229d080,0x0000f200,0x00181d7c,0x0002ff64 + .long 0x4e750200,0x00300000,0x00406008,0x02000030 + .long 0x00000080,0x2d40ff5c,0x122eff4e,0x66000276 + .long 0x020000c0,0x66000090,0x2d680004,0xff882d68 + .long 0x0008ff8c,0x30280000,0x0a408000,0x6a061d7c + .long 0x0008ff64,0x3d40ff84,0xf22ed080,0xff844e75 + .long 0x020000c0,0x666008ee,0x0003ff66,0x2d680004 + .long 0xff882d68,0x0008ff8c,0x30280000,0x0a408000 + .long 0x6a061d7c,0x0008ff64,0x3d40ff84,0xf22ed080 + .long 0xff84082e,0x0003ff62,0x66024e75,0x41eeff84 + .long 0x61ff0000,0x42664440,0x06406000,0x322eff84 + .long 0x02418000,0x02407fff,0x80413d40,0xff84f22e + .long 0xd040ff84,0x4e750c00,0x0040667e,0x3d680000 + .long 0xff842d68,0x0004ff88,0x2d680008,0xff8c61ff + .long 0x00001982,0x0c800000,0x007f6c00,0x00900c80 + .long 0xffffff81,0x67000178,0x6d0000f4,0xf23c8800 + .long 0x00000000,0xf22e9000,0xff5cf22e,0x481aff84 + .long 0xf201a800,0xf23c9000,0x00000000,0x83aeff64 + .long 0x2f02f22e,0xf080ff84,0x322eff84,0x34010281 + .long 0x00007fff,0x92800242,0x80008441,0x3d42ff84 + .long 0x241ff22e,0xd080ff84,0x4e753d68,0x0000ff84 + .long 0x2d680004,0xff882d68,0x0008ff8c,0x61ff0000 + .long 0x19040c80,0x000003ff,0x6c120c80,0xfffffc01 + .long 0x670000fc,0x6d000078,0x6000ff82,0x08ee0003 + .long 0xff660a2e,0x0080ff84,0x6a0608ee,0x0003ff64 + .long 0x122eff62,0x0201000b,0x661a41ee,0xff84222e + .long 0xff5c61ff,0x0000438a,0x812eff64,0xf22ed080 + .long 0xff844e75,0x2d6eff88,0xff942d6e,0xff8cff98 + .long 0x322eff84,0x2f022401,0x02810000,0x7fff0242 + .long 0x80009280,0x06810000,0x60000241,0x7fff8242 + .long 0x3d41ff90,0xf22ed040,0xff90241f,0x60acf23c + .long 0x88000000,0x0000f22e,0x9000ff5c,0xf22e481a + .long 0xff84f23c,0x90000000,0x0000f201,0xa80083ae + .long 0xff6400ae,0x00001048,0xff64122e,0xff620201 + .long 0x0013661c,0x082e0003,0xff6456c1,0x202eff5c + .long 0x61ff0000,0x43fa812e,0xff64f210,0xd0804e75 + .long 0x2f02322e,0xff842401,0x02810000,0x7fff0242 + .long 0x80009280,0x04810000,0x60000241,0x7fff8242 + .long 0x3d41ff84,0xf22ed040,0xff84241f,0x60b6f23c + .long 0x88000000,0x0000f22e,0x9000ff5c,0xf22e481a + .long 0xff84f201,0xa800f23c,0x90000000,0x000083ae + .long 0xff64f200,0x0098f23c,0x58b80002,0xf293ff74 + .long 0x6000fe7e,0x0c010004,0x6700fdb6,0x0c010005 + .long 0x67ff0000,0x18ae0c01,0x000367ff,0x000018b8 + .long 0xf228481a,0x0000f200,0xa800e198,0x1d40ff64 + .long 0x4e75122e,0xff4e6610,0x4a280000,0x6b024e75 + .long 0x1d7c0008,0xff644e75,0x0c010001,0x67400c01 + .long 0x00026724,0x0c010005,0x67ff0000,0x18660c01 + .long 0x000367ff,0x00001870,0x4a280000,0x6b024e75 + .long 0x1d7c0008,0xff644e75,0x4a280000,0x6b081d7c + .long 0x0002ff64,0x4e751d7c,0x000aff64,0x4e754a28 + .long 0x00006b08,0x1d7c0004,0xff644e75,0x1d7c000c + .long 0xff644e75,0x122eff4e,0x66280200,0x0030f200 + .long 0x9000f23c,0x88000000,0x0000f228,0x48010000 + .long 0xf23c9000,0x00000000,0xf200a800,0x81aeff64 + .long 0x4e750c01,0x0001672e,0x0c010002,0x674e0c01 + .long 0x00046710,0x0c010005,0x67ff0000,0x17d660ff + .long 0x000017e4,0x3d680000,0xff841d7c,0x0080ff88 + .long 0x41eeff84,0x60a44a28,0x00006b10,0xf23c4400 + .long 0x00000000,0x1d7c0004,0xff644e75,0xf23c4400 + .long 0x80000000,0x1d7c000c,0xff644e75,0xf228d080 + .long 0x00004a28,0x00006b08,0x1d7c0002,0xff644e75 + .long 0x1d7c000a,0xff644e75,0x122eff4e,0x6618f23c + .long 0x88000000,0x0000f228,0x48030000,0xf200a800 + .long 0x81aeff64,0x4e750c01,0x0001672e,0x0c010002 + .long 0x674e0c01,0x00046710,0x0c010005,0x67ff0000 + .long 0x174260ff,0x00001750,0x3d680000,0xff841d7c + .long 0x0080ff88,0x41eeff84,0x60b44a28,0x00006b10 + .long 0xf23c4400,0x00000000,0x1d7c0004,0xff644e75 + .long 0xf23c4400,0x80000000,0x1d7c000c,0xff644e75 + .long 0xf228d080,0x00004a28,0x00006b08,0x1d7c0002 + .long 0xff644e75,0x1d7c000a,0xff644e75,0x02000030 + .long 0x00000040,0x60080200,0x00300000,0x00802d40 + .long 0xff5c122e,0xff4e6600,0x025c0200,0x00c0667e + .long 0x2d680004,0xff882d68,0x0008ff8c,0x32280000 + .long 0x0881000f,0x3d41ff84,0xf22ed080,0xff844e75 + .long 0x020000c0,0x665808ee,0x0003ff66,0x2d680004 + .long 0xff882d68,0x0008ff8c,0x30280000,0x0880000f + .long 0x3d40ff84,0xf22ed080,0xff84082e,0x0003ff62 + .long 0x66024e75,0x41eeff84,0x61ff0000,0x3e0e4440 + .long 0x06406000,0x322eff84,0x02418000,0x02407fff + .long 0x80413d40,0xff84f22e,0xd040ff84,0x4e750c00 + .long 0x0040667e,0x3d680000,0xff842d68,0x0004ff88 + .long 0x2d680008,0xff8c61ff,0x0000152a,0x0c800000 + .long 0x007f6c00,0x00900c80,0xffffff81,0x67000170 + .long 0x6d0000ec,0xf23c8800,0x00000000,0xf22e9000 + .long 0xff5cf22e,0x4818ff84,0xf201a800,0xf23c9000 + .long 0x00000000,0x83aeff64,0x2f02f22e,0xf080ff84 + .long 0x322eff84,0x24010281,0x00007fff,0x92800242 + .long 0x80008441,0x3d42ff84,0x241ff22e,0xd080ff84 + .long 0x4e753d68,0x0000ff84,0x2d680004,0xff882d68 + .long 0x0008ff8c,0x61ff0000,0x14ac0c80,0x000003ff + .long 0x6c120c80,0xfffffc01,0x670000f4,0x6d000070 + .long 0x6000ff82,0x08ee0003,0xff6608ae,0x0007ff84 + .long 0x122eff62,0x0201000b,0x661a41ee,0xff84222e + .long 0xff5c61ff,0x00003f3a,0x812eff64,0xf22ed080 + .long 0xff844e75,0x2d6eff88,0xff942d6e,0xff8cff98 + .long 0x322eff84,0x2f022401,0x02810000,0x7fff0242 + .long 0x80009280,0x06810000,0x60000241,0x7fff8242 + .long 0x3d41ff90,0xf22ed040,0xff90241f,0x60acf23c + .long 0x88000000,0x0000f22e,0x9000ff5c,0xf22e4818 + .long 0xff84f23c,0x90000000,0x0000f201,0xa80083ae + .long 0xff6400ae,0x00001048,0xff64122e,0xff620201 + .long 0x0013661c,0x082e0003,0xff6456c1,0x202eff5c + .long 0x61ff0000,0x3faa812e,0xff64f210,0xd0804e75 + .long 0x2f02322e,0xff842401,0x02810000,0x7fff0242 + .long 0x80009280,0x04810000,0x60000241,0x7fff8242 + .long 0x3d41ff84,0xf22ed040,0xff84241f,0x60b6f23c + .long 0x88000000,0x0000f22e,0x9000ff5c,0xf22e4818 + .long 0xff84f201,0xa800f23c,0x90000000,0x000083ae + .long 0xff64f200,0x0098f23c,0x58b80002,0xf293ff74 + .long 0x6000fe86,0x0c010004,0x6700fdc6,0x0c010005 + .long 0x67ff0000,0x145e0c01,0x000367ff,0x00001468 + .long 0xf2284818,0x00000c01,0x00026708,0x1d7c0004 + .long 0xff644e75,0x1d7c0002,0xff644e75,0x4241122e + .long 0xff4fe709,0x822eff4e,0x6618f229,0xd0800000 + .long 0xf2284838,0x0000f200,0xa800e198,0x1d40ff64 + .long 0x4e75323b,0x120a4efb,0x10064afc,0x0030ffdc + .long 0xffdcffdc,0x006000f8,0x006e0000,0x0000ffdc + .long 0xffdcffdc,0x0060007c,0x006e0000,0x0000ffdc + .long 0xffdcffdc,0x0060007c,0x006e0000,0x00000060 + .long 0x00600060,0x00600060,0x006e0000,0x00000114 + .long 0x009c009c,0x006000bc,0x006e0000,0x0000006e + .long 0x006e006e,0x006e006e,0x006e0000,0x000061ff + .long 0x00001388,0x022e00f7,0xff644e75,0x61ff0000 + .long 0x137a022e,0x00f7ff64,0x4e753d68,0x0000ff84 + .long 0x20280004,0x08c0001f,0x2d40ff88,0x2d680008 + .long 0xff8c41ee,0xff846000,0xff422d69,0x0000ff84 + .long 0x20290004,0x08c0001f,0x2d40ff88,0x2d690008 + .long 0xff8c43ee,0xff846000,0xff223d69,0x0000ff90 + .long 0x3d680000,0xff842029,0x000408c0,0x001f2d40 + .long 0xff942028,0x000408c0,0x001f2d40,0xff882d69 + .long 0x0008ff98,0x2d680008,0xff8c43ee,0xff9041ee + .long 0xff846000,0xfee61028,0x00001229,0x0000b101 + .long 0x6b00ff78,0x4a006b02,0x4e751d7c,0x0008ff64 + .long 0x4e751028,0x00001229,0x0000b101,0x6b00ff7c + .long 0x4a006a02,0x4e751d7c,0x0008ff64,0x4e752d40 + .long 0xff5c4241,0x122eff4f,0xe709822e,0xff4e6600 + .long 0x02a03d69,0x0000ff90,0x2d690004,0xff942d69 + .long 0x0008ff98,0x3d680000,0xff842d68,0x0004ff88 + .long 0x2d680008,0xff8c61ff,0x0000119a,0x2f0061ff + .long 0x0000123e,0xd09f0c80,0xffffc001,0x670000f8 + .long 0x6d000064,0x0c800000,0x40006700,0x01da6e00 + .long 0x0122f22e,0xd080ff90,0xf22e9000,0xff5cf23c + .long 0x88000000,0x0000f22e,0x4827ff84,0xf201a800 + .long 0xf23c9000,0x00000000,0x83aeff64,0xf22ef080 + .long 0xff842f02,0x322eff84,0x24010281,0x00007fff + .long 0x02428000,0x92808242,0x3d41ff84,0x241ff22e + .long 0xd080ff84,0x4e75f22e,0xd080ff90,0xf22e9000 + .long 0xff5cf23c,0x88000000,0x0000f22e,0x4827ff84 + .long 0xf201a800,0xf23c9000,0x00000000,0x83aeff64 + .long 0x00ae0000,0x1048ff64,0x122eff62,0x02010013 + .long 0x6620082e,0x0003ff64,0x56c1202e,0xff5c0200 + .long 0x003061ff,0x00003c98,0x812eff64,0xf210d080 + .long 0x4e75f22e,0xf080ff84,0x2f02322e,0xff842401 + .long 0x02810000,0x7fff9280,0x04810000,0x60000241 + .long 0x7fff0242,0x80008242,0x3d41ff84,0x241ff22e + .long 0xd040ff84,0x60acf22e,0xd080ff90,0xf22e9000 + .long 0xff5cf23c,0x88000000,0x0000f22e,0x4827ff84 + .long 0xf201a800,0xf23c9000,0x00000000,0x83aeff64 + .long 0xf2000098,0xf23c58b8,0x0002f293,0xff646000 + .long 0xff0c08ee,0x0003ff66,0xf22ed080,0xff90f23c + .long 0x90000000,0x0010f23c,0x88000000,0x0000f22e + .long 0x4827ff84,0xf201a800,0xf23c9000,0x00000000 + .long 0x83aeff64,0x122eff62,0x0201000b,0x6620f22e + .long 0xf080ff84,0x41eeff84,0x222eff5c,0x61ff0000 + .long 0x3b56812e,0xff64f22e,0xd080ff84,0x4e75f22e + .long 0xd040ff90,0xf22e9000,0xff5cf23c,0x88000000 + .long 0x0000f22e,0x48a7ff84,0xf23c9000,0x00000000 + .long 0xf22ef040,0xff842f02,0x322eff84,0x24010281 + .long 0x00007fff,0x02428000,0x92800681,0x00006000 + .long 0x02417fff,0x82423d41,0xff84241f,0xf22ed040 + .long 0xff846000,0xff8af22e,0xd080ff90,0xf22e9000 + .long 0xff5cf23c,0x88000000,0x0000f22e,0x4827ff84 + .long 0xf201a800,0xf23c9000,0x00000000,0x83aeff64 + .long 0xf2000098,0xf23c58b8,0x0002f292,0xfe20f294 + .long 0xff12f22e,0xd040ff90,0x222eff5c,0x020100c0 + .long 0x00010010,0xf2019000,0xf23c8800,0x00000000 + .long 0xf22e48a7,0xff84f23c,0x90000000,0x0000f200 + .long 0x0498f23c,0x58b80002,0xf293fde2,0x6000fed4 + .long 0x323b120a,0x4efb1006,0x4afc0030,0xfd560072 + .long 0x0078006c,0xfd560066,0x00000000,0x00720072 + .long 0x0060006c,0x00720066,0x00000000,0x007e0060 + .long 0x007e006c,0x007e0066,0x00000000,0x006c006c + .long 0x006c006c,0x006c0066,0x00000000,0xfd560072 + .long 0x0078006c,0xfd560066,0x00000000,0x00660066 + .long 0x00660066,0x00660066,0x00000000,0x60ff0000 + .long 0x101e60ff,0x00000f94,0x60ff0000,0x0f8e60ff + .long 0xffffed0e,0x60ffffff,0xed6260ff,0xffffed2e + .long 0x2d40ff5c,0x4241122e,0xff4fe709,0x822eff4e + .long 0x6600027c,0x3d690000,0xff902d69,0x0004ff94 + .long 0x2d690008,0xff983d68,0x0000ff84,0x2d680004 + .long 0xff882d68,0x0008ff8c,0x61ff0000,0x0e582f00 + .long 0x61ff0000,0x0efc4497,0xd197322e,0xff5eec09 + .long 0x201f0c80,0xffffc001,0x6f000064,0x0c800000 + .long 0x3fff6700,0x01b66e00,0x0100f22e,0xd080ff90 + .long 0xf22e9000,0xff5cf23c,0x88000000,0x0000f22e + .long 0x4824ff84,0xf201a800,0xf23c9000,0x00000000 + .long 0x83aeff64,0xf22ef080,0xff842f02,0x322eff84 + .long 0x24010281,0x00007fff,0x02428000,0x92808242 + .long 0x3d41ff84,0x241ff22e,0xd080ff84,0x4e75f22e + .long 0xd080ff90,0xf22e9000,0xff5cf23c,0x88000000 + .long 0x0000f22e,0x4824ff84,0xf201a800,0xf23c9000 + .long 0x00000000,0x83aeff64,0xf227e001,0x3217dffc + .long 0x0000000c,0x02810000,0x7fff9280,0x0c810000 + .long 0x7fff6d90,0x006e1048,0xff66122e,0xff620201 + .long 0x00136620,0x082e0003,0xff6456c1,0x202eff5c + .long 0x02000030,0x61ff0000,0x3936812e,0xff64f210 + .long 0xd0804e75,0xf22ef080,0xff842f02,0x322eff84 + .long 0x24010281,0x00007fff,0x02428000,0x92800481 + .long 0x00006000,0x02417fff,0x82423d41,0xff84241f + .long 0xf22ed040,0xff8460ac,0x08ee0003,0xff66f22e + .long 0xd080ff90,0xf23c9000,0x00000010,0xf23c8800 + .long 0x00000000,0xf22e4824,0xff84f201,0xa800f23c + .long 0x90000000,0x000083ae,0xff64122e,0xff620201 + .long 0x000b6620,0xf22ef080,0xff8441ee,0xff84222e + .long 0xff5c61ff,0x00003830,0x812eff64,0xf22ed080 + .long 0xff844e75,0xf22ed040,0xff90f22e,0x9000ff5c + .long 0xf23c8800,0x00000000,0xf22e48a4,0xff84f23c + .long 0x90000000,0x0000f22e,0xf040ff84,0x2f02322e + .long 0xff842401,0x02810000,0x7fff0242,0x80009280 + .long 0x06810000,0x60000241,0x7fff8242,0x3d41ff84 + .long 0x241ff22e,0xd040ff84,0x608af22e,0xd080ff90 + .long 0xf22e9000,0xff5cf23c,0x88000000,0x0000f22e + .long 0x4824ff84,0xf201a800,0xf23c9000,0x00000000 + .long 0x83aeff64,0xf2000098,0xf23c58b8,0x0001f292 + .long 0xfe44f294,0xff14f22e,0xd040ff90,0x42810001 + .long 0x0010f201,0x9000f23c,0x88000000,0x0000f22e + .long 0x48a4ff84,0xf23c9000,0x00000000,0xf2000498 + .long 0xf23c58b8,0x0001f293,0xfe0c6000,0xfedc323b + .long 0x120a4efb,0x10064afc,0x0030fd7a,0x00720078 + .long 0x0060fd7a,0x00660000,0x00000078,0x006c0078 + .long 0x00600078,0x00660000,0x0000007e,0x007e006c + .long 0x0060007e,0x00660000,0x00000060,0x00600060 + .long 0x00600060,0x00660000,0x0000fd7a,0x00720078 + .long 0x0060fd7a,0x00660000,0x00000066,0x00660066 + .long 0x00660066,0x00660000,0x000060ff,0x00000c7c + .long 0x60ff0000,0x0c7660ff,0x00000cf4,0x60ffffff + .long 0xf0ce60ff,0xfffff09c,0x60ffffff,0xf0f40200 + .long 0x00300000,0x00406008,0x02000030,0x00000080 + .long 0x2d40ff5c,0x4241122e,0xff4fe709,0x822eff4e + .long 0x6600024c,0x61ff0000,0x0a5cf22e,0xd080ff90 + .long 0xf23c8800,0x00000000,0xf22e9000,0xff5cf22e + .long 0x4822ff84,0xf23c9000,0x00000000,0xf201a800 + .long 0x83aeff64,0xf281003c,0x2f02f227,0xe001322e + .long 0xff5eec09,0x34170282,0x00007fff,0x9480b4bb + .long 0x14246c38,0xb4bb142a,0x6d0000b8,0x67000184 + .long 0x32170241,0x80008242,0x3e81f21f,0xd080241f + .long 0x4e754e75,0x00007fff,0x0000407f,0x000043ff + .long 0x00000000,0x00003f81,0x00003c01,0x00ae0000 + .long 0x1048ff64,0x122eff62,0x02010013,0x6624dffc + .long 0x0000000c,0x082e0003,0xff6456c1,0x202eff5c + .long 0x61ff0000,0x366a812e,0xff64f210,0xd080241f + .long 0x4e75122e,0xff5c0201,0x00c0661a,0x32170241 + .long 0x80000482,0x00006000,0x02427fff,0x82423e81 + .long 0xf21fd040,0x60bef22e,0xd080ff90,0x222eff5c + .long 0x02010030,0xf2019000,0xf22e4822,0xff84f23c + .long 0x90000000,0x0000dffc,0x0000000c,0xf227e001 + .long 0x60ba08ee,0x0003ff66,0xdffc0000,0x000cf22e + .long 0xd080ff90,0xf23c9000,0x00000010,0xf23c8800 + .long 0x00000000,0xf22e4822,0xff84f23c,0x90000000 + .long 0x0000f201,0xa80083ae,0xff64122e,0xff620201 + .long 0x000b6622,0xf22ef080,0xff8441ee,0xff84222e + .long 0xff5c61ff,0x000034ba,0x812eff64,0xf22ed080 + .long 0xff84241f,0x4e75f22e,0xd040ff90,0x222eff5c + .long 0x020100c0,0x664ef22e,0x9000ff5c,0xf23c8800 + .long 0x00000000,0xf22e48a2,0xff84f23c,0x90000000 + .long 0x0000f22e,0xf040ff84,0x322eff84,0x24010281 + .long 0x00007fff,0x02428000,0x92800681,0x00006000 + .long 0x02417fff,0x82423d41,0xff84f22e,0xd040ff84 + .long 0x6000ff82,0x222eff5c,0x02010030,0xf2019000 + .long 0x60aa222e,0xff5c0201,0x00c06700,0xfe74222f + .long 0x00040c81,0x80000000,0x6600fe66,0x4aaf0008 + .long 0x6600fe5e,0x082e0001,0xff666700,0xfe54f22e + .long 0xd040ff90,0x222eff5c,0x020100c0,0x00010010 + .long 0xf2019000,0xf23c8800,0x00000000,0xf22e48a2 + .long 0xff84f23c,0x90000000,0x0000f200,0x0018f200 + .long 0x0498f200,0x0438f292,0xfeca6000,0xfe14323b + .long 0x120a4efb,0x10064afc,0x0030fdaa,0x00e4011c + .long 0x0060fdaa,0x00660000,0x000000bc,0x006c011c + .long 0x006000bc,0x00660000,0x00000130,0x0130010c + .long 0x00600130,0x00660000,0x00000060,0x00600060 + .long 0x00600060,0x00660000,0x0000fdaa,0x00e4011c + .long 0x0060fdaa,0x00660000,0x00000066,0x00660066 + .long 0x00660066,0x00660000,0x000060ff,0x0000097c + .long 0x60ff0000,0x09761028,0x00001229,0x0000b101 + .long 0x6b000016,0x4a006b2e,0xf23c4400,0x00000000 + .long 0x1d7c0004,0xff644e75,0x122eff5f,0x02010030 + .long 0x0c010020,0x6710f23c,0x44000000,0x00001d7c + .long 0x0004ff64,0x4e75f23c,0x44008000,0x00001d7c + .long 0x000cff64,0x4e753d68,0x0000ff84,0x2d680004 + .long 0xff882d68,0x0008ff8c,0x61ff0000,0x0828426e + .long 0xff9042ae,0xff9442ae,0xff986000,0xfcce3d69 + .long 0x0000ff90,0x2d690004,0xff942d69,0x0008ff98 + .long 0x61ff0000,0x08ac426e,0xff8442ae,0xff8842ae + .long 0xff8c6000,0xfca61028,0x00001229,0x0000b300 + .long 0x6bff0000,0x094af228,0xd0800000,0x4a280000 + .long 0x6a1c1d7c,0x000aff64,0x4e75f229,0xd0800000 + .long 0x4a290000,0x6a081d7c,0x000aff64,0x4e751d7c + .long 0x0002ff64,0x4e750200,0x00300000,0x00406008 + .long 0x02000030,0x00000080,0x2d40ff5c,0x4241122e + .long 0xff4fe709,0x822eff4e,0x6600024c,0x61ff0000 + .long 0x0694f22e,0xd080ff90,0xf23c8800,0x00000000 + .long 0xf22e9000,0xff5cf22e,0x4828ff84,0xf23c9000 + .long 0x00000000,0xf201a800,0x83aeff64,0xf281003c + .long 0x2f02f227,0xe001322e,0xff5eec09,0x34170282 + .long 0x00007fff,0x9480b4bb,0x14246c38,0xb4bb142a + .long 0x6d0000b8,0x67000184,0x32170241,0x80008242 + .long 0x3e81f21f,0xd080241f,0x4e754e75,0x00007fff + .long 0x0000407f,0x000043ff,0x00000000,0x00003f81 + .long 0x00003c01,0x00ae0000,0x1048ff64,0x122eff62 + .long 0x02010013,0x6624dffc,0x0000000c,0x082e0003 + .long 0xff6456c1,0x202eff5c,0x61ff0000,0x32a2812e + .long 0xff64f210,0xd080241f,0x4e75122e,0xff5c0201 + .long 0x00c0661a,0x32170241,0x80000482,0x00006000 + .long 0x02427fff,0x82423e81,0xf21fd040,0x60bef22e + .long 0xd080ff90,0x222eff5c,0x02010030,0xf2019000 + .long 0xf22e4828,0xff84f23c,0x90000000,0x0000dffc + .long 0x0000000c,0xf227e001,0x60ba08ee,0x0003ff66 + .long 0xdffc0000,0x000cf22e,0xd080ff90,0xf23c9000 + .long 0x00000010,0xf23c8800,0x00000000,0xf22e4828 + .long 0xff84f23c,0x90000000,0x0000f201,0xa80083ae + .long 0xff64122e,0xff620201,0x000b6622,0xf22ef080 + .long 0xff8441ee,0xff84222e,0xff5c61ff,0x000030f2 + .long 0x812eff64,0xf22ed080,0xff84241f,0x4e75f22e + .long 0xd040ff90,0x222eff5c,0x020100c0,0x664ef22e + .long 0x9000ff5c,0xf23c8800,0x00000000,0xf22e48a8 + .long 0xff84f23c,0x90000000,0x0000f22e,0xf040ff84 + .long 0x322eff84,0x24010281,0x00007fff,0x02428000 + .long 0x92800681,0x00006000,0x02417fff,0x82423d41 + .long 0xff84f22e,0xd040ff84,0x6000ff82,0x222eff5c + .long 0x02010030,0xf2019000,0x60aa222e,0xff5c0201 + .long 0x00c06700,0xfe74222f,0x00040c81,0x80000000 + .long 0x6600fe66,0x4aaf0008,0x6600fe5e,0x082e0001 + .long 0xff666700,0xfe54f22e,0xd040ff90,0x222eff5c + .long 0x020100c0,0x00010010,0xf2019000,0xf23c8800 + .long 0x00000000,0xf22e48a8,0xff84f23c,0x90000000 + .long 0x0000f200,0x0018f200,0x0498f200,0x0438f292 + .long 0xfeca6000,0xfe14323b,0x120a4efb,0x10064afc + .long 0x0030fdaa,0x00e2011a,0x0060fdaa,0x00660000 + .long 0x000000ba,0x006c011a,0x006000ba,0x00660000 + .long 0x00000130,0x0130010a,0x00600130,0x00660000 + .long 0x00000060,0x00600060,0x00600060,0x00660000 + .long 0x0000fdaa,0x00e2011a,0x0060fdaa,0x00660000 + .long 0x00000066,0x00660066,0x00660066,0x00660000 + .long 0x000060ff,0x000005b4,0x60ff0000,0x05ae1028 + .long 0x00001229,0x0000b300,0x6a144a00,0x6b2ef23c + .long 0x44000000,0x00001d7c,0x0004ff64,0x4e75122e + .long 0xff5f0201,0x00300c01,0x00206710,0xf23c4400 + .long 0x00000000,0x1d7c0004,0xff644e75,0xf23c4400 + .long 0x80000000,0x1d7c000c,0xff644e75,0x3d680000 + .long 0xff842d68,0x0004ff88,0x2d680008,0xff8c61ff + .long 0x00000462,0x426eff90,0x42aeff94,0x42aeff98 + .long 0x6000fcd0,0x3d690000,0xff902d69,0x0004ff94 + .long 0x2d690008,0xff9861ff,0x000004e6,0x426eff84 + .long 0x42aeff88,0x42aeff8c,0x6000fca8,0x10280000 + .long 0x12290000,0xb3006aff,0x00000584,0xf228d080 + .long 0x0000f200,0x001af293,0x001e1d7c,0x000aff64 + .long 0x4e75f229,0xd0800000,0x4a290000,0x6a081d7c + .long 0x000aff64,0x4e751d7c,0x0002ff64,0x4e750200 + .long 0x00300000,0x00406008,0x02000030,0x00000080 + .long 0x2d40ff5c,0x4241122e,0xff4e6600,0x02744a28 + .long 0x00006bff,0x00000528,0x020000c0,0x6648f22e + .long 0x9000ff5c,0xf23c8800,0x00000000,0xf2104804 + .long 0xf201a800,0x83aeff64,0x4e754a28,0x00006bff + .long 0x000004fc,0x020000c0,0x661c3d68,0x0000ff84 + .long 0x2d680004,0xff882d68,0x0008ff8c,0x61ff0000 + .long 0x03ae6000,0x003e0c00,0x00406600,0x00843d68 + .long 0x0000ff84,0x2d680004,0xff882d68,0x0008ff8c + .long 0x61ff0000,0x038a0c80,0x0000007e,0x67000098 + .long 0x6e00009e,0x0c80ffff,0xff806700,0x01a46d00 + .long 0x0120f23c,0x88000000,0x0000f22e,0x9000ff5c + .long 0xf22e4804,0xff84f201,0xa800f23c,0x90000000 + .long 0x000083ae,0xff642f02,0xf22ef080,0xff84322e + .long 0xff842401,0x02810000,0x7fff9280,0x02428000 + .long 0x84413d42,0xff84241f,0xf22ed080,0xff844e75 + .long 0x3d680000,0xff842d68,0x0004ff88,0x2d680008 + .long 0xff8c61ff,0x00000308,0x0c800000,0x03fe6700 + .long 0x00166e1c,0x0c80ffff,0xfc006700,0x01246d00 + .long 0x00a06000,0xff7e082e,0x0000ff85,0x6600ff74 + .long 0x08ee0003,0xff66f23c,0x90000000,0x0010f23c + .long 0x88000000,0x0000f22e,0x4804ff84,0xf201a800 + .long 0xf23c9000,0x00000000,0x83aeff64,0x122eff62 + .long 0x0201000b,0x6620f22e,0xf080ff84,0x41eeff84 + .long 0x222eff5c,0x61ff0000,0x2d28812e,0xff64f22e + .long 0xd080ff84,0x4e752d6e,0xff88ff94,0x2d6eff8c + .long 0xff98322e,0xff842f02,0x24010281,0x00007fff + .long 0x02428000,0x92800681,0x00006000,0x02417fff + .long 0x82423d41,0xff90f22e,0xd040ff90,0x241f60a6 + .long 0xf23c8800,0x00000000,0xf22e9000,0xff5cf22e + .long 0x4804ff84,0xf23c9000,0x00000000,0xf201a800 + .long 0x83aeff64,0x00ae0000,0x1048ff64,0x122eff62 + .long 0x02010013,0x661c082e,0x0003ff64,0x56c1202e + .long 0xff5c61ff,0x00002d98,0x812eff64,0xf210d080 + .long 0x4e752f02,0x322eff84,0x24010281,0x00007fff + .long 0x02428000,0x92800481,0x00006000,0x02417fff + .long 0x82423d41,0xff84f22e,0xd040ff84,0x241f60b6 + .long 0x082e0000,0xff856600,0xff78f23c,0x88000000 + .long 0x0000f22e,0x9000ff5c,0xf22e4804,0xff84f201 + .long 0xa800f23c,0x90000000,0x000083ae,0xff64f200 + .long 0x0080f23c,0x58b80001,0xf293ff6a,0x6000fe48 + .long 0x0c010004,0x6700fdb4,0x0c010001,0x67160c01 + .long 0x00026736,0x0c010005,0x67ff0000,0x023660ff + .long 0x00000244,0x4a280000,0x6b10f23c,0x44000000 + .long 0x00001d7c,0x0004ff64,0x4e75f23c,0x44008000 + .long 0x00001d7c,0x000cff64,0x4e754a28,0x00006bff + .long 0x0000026c,0xf228d080,0x00001d7c,0x0002ff64 + .long 0x4e752d68,0x0004ff88,0x2d690004,0xff942d68 + .long 0x0008ff8c,0x2d690008,0xff983028,0x00003229 + .long 0x00003d40,0xff843d41,0xff900240,0x7fff0241 + .long 0x7fff3d40,0xff543d41,0xff56b041,0x6cff0000 + .long 0x005c61ff,0x0000015a,0x2f000c2e,0x0004ff4e + .long 0x661041ee,0xff8461ff,0x00002940,0x44403d40 + .long 0xff54302e,0xff560440,0x0042b06e,0xff546c1a + .long 0x302eff54,0xd06f0002,0x322eff84,0x02418000 + .long 0x80413d40,0xff84201f,0x4e75026e,0x8000ff84 + .long 0x08ee0000,0xff85201f,0x4e7561ff,0x00000056 + .long 0x2f000c2e,0x0004ff4f,0x661041ee,0xff9061ff + .long 0x000028e8,0x44403d40,0xff56302e,0xff540440 + .long 0x0042b06e,0xff566c1a,0x302eff56,0xd06f0002 + .long 0x322eff90,0x02418000,0x80413d40,0xff90201f + .long 0x4e75026e,0x8000ff90,0x08ee0000,0xff91201f + .long 0x4e75322e,0xff843001,0x02810000,0x7fff0240 + .long 0x80000040,0x3fff3d40,0xff840c2e,0x0004ff4e + .long 0x670a203c,0x00003fff,0x90814e75,0x41eeff84 + .long 0x61ff0000,0x28764480,0x220060e6,0x0c2e0004 + .long 0xff4e673a,0x322eff84,0x02810000,0x7fff026e + .long 0x8000ff84,0x08010000,0x6712006e,0x3fffff84 + .long 0x203c0000,0x3fff9081,0xe2804e75,0x006e3ffe + .long 0xff84203c,0x00003ffe,0x9081e280,0x4e7541ee + .long 0xff8461ff,0x00002824,0x08000000,0x6710006e + .long 0x3fffff84,0x06800000,0x3fffe280,0x4e75006e + .long 0x3ffeff84,0x06800000,0x3ffee280,0x4e75322e + .long 0xff903001,0x02810000,0x7fff0240,0x80000040 + .long 0x3fff3d40,0xff900c2e,0x0004ff4f,0x670a203c + .long 0x00003fff,0x90814e75,0x41eeff90,0x61ff0000 + .long 0x27ca4480,0x220060e6,0x0c2e0005,0xff4f6732 + .long 0x0c2e0003,0xff4f673e,0x0c2e0003,0xff4e6714 + .long 0x08ee0006,0xff7000ae,0x01004080,0xff6441ee + .long 0xff6c6042,0x00ae0100,0x0000ff64,0x41eeff6c + .long 0x603400ae,0x01004080,0xff6408ee,0x0006ff7c + .long 0x41eeff78,0x602041ee,0xff780c2e,0x0005ff4e + .long 0x66ff0000,0x000c00ae,0x00004080,0xff6400ae + .long 0x01000000,0xff640828,0x00070000,0x670800ae + .long 0x08000000,0xff64f210,0xd0804e75,0x00ae0100 + .long 0x2080ff64,0xf23bd080,0x01700000,0x00084e75 + .long 0x7fff0000,0xffffffff,0xffffffff,0x2d40ff54 + .long 0x302eff42,0x4281122e,0xff64e099,0xf2018800 + .long 0x323b0206,0x4efb1002,0x02340040,0x02f8030c + .long 0x03200334,0x0348035c,0x03660352,0x033e032a + .long 0x03160302,0x004a0238,0x023a0276,0x0054009e + .long 0x0102014c,0x01b201fc,0x021801d8,0x018c0128 + .long 0x00de007a,0x02b6025a,0xf2810006,0x6000032a + .long 0x4e75f28e,0x00066000,0x03204e75,0xf2920022 + .long 0x082e0000,0xff646700,0x031000ae,0x00008080 + .long 0xff64082e,0x0007ff62,0x6600032c,0x600002fa + .long 0x4e75f29d,0x00066000,0x02f0082e,0x0000ff64 + .long 0x671200ae,0x00008080,0xff64082e,0x0007ff62 + .long 0x66000304,0x4e75f293,0x0022082e,0x0000ff64 + .long 0x670002c6,0x00ae0000,0x8080ff64,0x082e0007 + .long 0xff626600,0x02e26000,0x02b0082e,0x0000ff64 + .long 0x671200ae,0x00008080,0xff64082e,0x0007ff62 + .long 0x660002c4,0x4e75f29c,0x00066000,0x028c082e + .long 0x0000ff64,0x671200ae,0x00008080,0xff64082e + .long 0x0007ff62,0x660002a0,0x4e75f294,0x0022082e + .long 0x0000ff64,0x67000262,0x00ae0000,0x8080ff64 + .long 0x082e0007,0xff626600,0x027e6000,0x024c4e75 + .long 0xf29b0006,0x60000242,0x082e0000,0xff646712 + .long 0x00ae0000,0x8080ff64,0x082e0007,0xff626600 + .long 0x02564e75,0xf2950022,0x082e0000,0xff646700 + .long 0x021800ae,0x00008080,0xff64082e,0x0007ff62 + .long 0x66000234,0x60000202,0x082e0000,0xff646712 + .long 0x00ae0000,0x8080ff64,0x082e0007,0xff626600 + .long 0x02164e75,0xf29a0006,0x600001de,0x082e0000 + .long 0xff646700,0x001400ae,0x00008080,0xff64082e + .long 0x0007ff62,0x660001f0,0x4e75f296,0x0022082e + .long 0x0000ff64,0x670001b2,0x00ae0000,0x8080ff64 + .long 0x082e0007,0xff626600,0x01ce6000,0x019c4e75 + .long 0xf2990006,0x60000192,0x082e0000,0xff646712 + .long 0x00ae0000,0x8080ff64,0x082e0007,0xff626600 + .long 0x01a64e75,0xf2970018,0x00ae0000,0x8080ff64 + .long 0x082e0007,0xff626600,0x018e6000,0x015c4e75 + .long 0xf2980006,0x60000152,0x00ae0000,0x8080ff64 + .long 0x082e0007,0xff626600,0x016e4e75,0x6000013a + .long 0x4e75082e,0x0000ff64,0x6700012e,0x00ae0000 + .long 0x8080ff64,0x082e0007,0xff626600,0x014a6000 + .long 0x0118082e,0x0000ff64,0x671200ae,0x00008080 + .long 0xff64082e,0x0007ff62,0x6600012c,0x4e75f291 + .long 0x0022082e,0x0000ff64,0x670000ee,0x00ae0000 + .long 0x8080ff64,0x082e0007,0xff626600,0x010a6000 + .long 0x00d8082e,0x0000ff64,0x671200ae,0x00008080 + .long 0xff64082e,0x0007ff62,0x660000ec,0x4e75f29e + .long 0x0022082e,0x0000ff64,0x670000ae,0x00ae0000 + .long 0x8080ff64,0x082e0007,0xff626600,0x00ca6000 + .long 0x0098082e,0x0000ff64,0x67000014,0x00ae0000 + .long 0x8080ff64,0x082e0007,0xff626600,0x00aa4e75 + .long 0xf2820006,0x60000072,0x4e75f28d,0x00066000 + .long 0x00684e75,0xf2830006,0x6000005e,0x4e75f28c + .long 0x00066000,0x00544e75,0xf2840006,0x6000004a + .long 0x4e75f28b,0x00066000,0x00404e75,0xf2850006 + .long 0x60000036,0x4e75f28a,0x00066000,0x002c4e75 + .long 0xf2860006,0x60000022,0x4e75f289,0x00066000 + .long 0x00184e75,0xf2870006,0x6000000e,0x4e75f288 + .long 0x00066000,0x00044e75,0x122eff41,0x02410007 + .long 0x61ff0000,0x1d665340,0x61ff0000,0x1dd00c40 + .long 0xffff6602,0x4e75202e,0xff54d0ae,0xff685880 + .long 0x2d400006,0x4e751d7c,0x0002ff4a,0x4e75302e + .long 0xff424281,0x122eff64,0xe099f201,0x8800323b + .long 0x02064efb,0x1002021e,0x004002e4,0x02f002fc + .long 0x03080314,0x03200326,0x031a030e,0x030202f6 + .long 0x02ea0046,0x02200224,0x0260004c,0x009200f8 + .long 0x013e01a4,0x01ea0202,0x01c4017e,0x011800d2 + .long 0x006c02a2,0x0240f281,0x02ea4e75,0xf28e02e4 + .long 0x4e75f292,0x02de082e,0x0000ff64,0x671200ae + .long 0x00008080,0xff64082e,0x0007ff62,0x660002cc + .long 0x4e75f29d,0x00044e75,0x082e0000,0xff646700 + .long 0x02b200ae,0x00008080,0xff64082e,0x0007ff62 + .long 0x660002a8,0x6000029c,0xf293001e,0x082e0000 + .long 0xff646712,0x00ae0000,0x8080ff64,0x082e0007 + .long 0xff626600,0x02864e75,0x082e0000,0xff646700 + .long 0x027200ae,0x00008080,0xff64082e,0x0007ff62 + .long 0x66000268,0x6000025c,0xf29c0004,0x4e75082e + .long 0x0000ff64,0x6700024c,0x00ae0000,0x8080ff64 + .long 0x082e0007,0xff626600,0x02426000,0x0236f294 + .long 0x0232082e,0x0000ff64,0x671200ae,0x00008080 + .long 0xff64082e,0x0007ff62,0x66000220,0x4e75f29b + .long 0x00044e75,0x082e0000,0xff646700,0x020600ae + .long 0x00008080,0xff64082e,0x0007ff62,0x660001fc + .long 0x600001f0,0xf295001e,0x082e0000,0xff646712 + .long 0x00ae0000,0x8080ff64,0x082e0007,0xff626600 + .long 0x01da4e75,0x082e0000,0xff646700,0x01c600ae + .long 0x00008080,0xff64082e,0x0007ff62,0x660001bc + .long 0x600001b0,0xf29a0004,0x4e75082e,0x0000ff64 + .long 0x670001a0,0x00ae0000,0x8080ff64,0x082e0007 + .long 0xff626600,0x01966000,0x018af296,0x0186082e + .long 0x0000ff64,0x671200ae,0x00008080,0xff64082e + .long 0x0007ff62,0x66000174,0x4e75f299,0x00044e75 + .long 0x082e0000,0xff646700,0x015a00ae,0x00008080 + .long 0xff64082e,0x0007ff62,0x66000150,0x60000144 + .long 0xf2970140,0x00ae0000,0x8080ff64,0x082e0007 + .long 0xff626600,0x01364e75,0xf2980004,0x4e7500ae + .long 0x00008080,0xff64082e,0x0007ff62,0x6600011c + .long 0x60000110,0x4e756000,0x010a082e,0x0000ff64 + .long 0x671200ae,0x00008080,0xff64082e,0x0007ff62 + .long 0x660000f8,0x4e75082e,0x0000ff64,0x670000e4 + .long 0x00ae0000,0x8080ff64,0x082e0007,0xff626600 + .long 0x00da6000,0x00cef291,0x0020082e,0x0000ff64 + .long 0x67000014,0x00ae0000,0x8080ff64,0x082e0007 + .long 0xff626600,0x00b64e75,0x082e0000,0xff646700 + .long 0x00a200ae,0x00008080,0xff64082e,0x0007ff62 + .long 0x66000098,0x6000008c,0xf29e0020,0x082e0000 + .long 0xff646700,0x001400ae,0x00008080,0xff64082e + .long 0x0007ff62,0x66000074,0x4e75082e,0x0000ff64 + .long 0x67000060,0x00ae0000,0x8080ff64,0x082e0007 + .long 0xff626600,0x00566000,0x004af282,0x00464e75 + .long 0xf28d0040,0x4e75f283,0x003a4e75,0xf28c0034 + .long 0x4e75f284,0x002e4e75,0xf28b0028,0x4e75f285 + .long 0x00224e75,0xf28a001c,0x4e75f286,0x00164e75 + .long 0xf2890010,0x4e75f287,0x000a4e75,0xf2880004 + .long 0x4e751d7c,0x0001ff4a,0x4e751d7c,0x0002ff4a + .long 0x4e75302e,0xff424281,0x122eff64,0xe099f201 + .long 0x8800323b,0x02064efb,0x10020208,0x004002ac + .long 0x02cc02ec,0x030c032c,0x034c035c,0x033c031c + .long 0x02fc02dc,0x02bc0050,0x020e0214,0x02440060 + .long 0x00a400fa,0x013e0194,0x01d801f0,0x01b60172 + .long 0x011c00d8,0x00820278,0x022cf281,0x00084200 + .long 0x6000032e,0x50c06000,0x0328f28e,0x00084200 + .long 0x6000031e,0x50c06000,0x0318f292,0x001a4200 + .long 0x082e0000,0xff646700,0x030800ae,0x00008080 + .long 0xff646000,0x02f250c0,0x600002f6,0xf29d0008 + .long 0x42006000,0x02ec50c0,0x082e0000,0xff646700 + .long 0x02e000ae,0x00008080,0xff646000,0x02caf293 + .long 0x001a4200,0x082e0000,0xff646700,0x02c400ae + .long 0x00008080,0xff646000,0x02ae50c0,0x082e0000 + .long 0xff646700,0x02ac00ae,0x00008080,0xff646000 + .long 0x0296f29c,0x00084200,0x60000296,0x50c0082e + .long 0x0000ff64,0x6700028a,0x00ae0000,0x8080ff64 + .long 0x60000274,0xf294001a,0x4200082e,0x0000ff64 + .long 0x6700026e,0x00ae0000,0x8080ff64,0x60000258 + .long 0x50c06000,0x025cf29b,0x00084200,0x60000252 + .long 0x50c0082e,0x0000ff64,0x67000246,0x00ae0000 + .long 0x8080ff64,0x60000230,0xf295001a,0x4200082e + .long 0x0000ff64,0x6700022a,0x00ae0000,0x8080ff64 + .long 0x60000214,0x50c0082e,0x0000ff64,0x67000212 + .long 0x00ae0000,0x8080ff64,0x600001fc,0xf29a0008 + .long 0x42006000,0x01fc50c0,0x082e0000,0xff646700 + .long 0x01f000ae,0x00008080,0xff646000,0x01daf296 + .long 0x001a4200,0x082e0000,0xff646700,0x01d400ae + .long 0x00008080,0xff646000,0x01be50c0,0x600001c2 + .long 0xf2990008,0x42006000,0x01b850c0,0x082e0000 + .long 0xff646700,0x01ac00ae,0x00008080,0xff646000 + .long 0x0196f297,0x00104200,0x00ae0000,0x8080ff64 + .long 0x60000184,0x50c06000,0x0188f298,0x00084200 + .long 0x6000017e,0x50c000ae,0x00008080,0xff646000 + .long 0x01664200,0x6000016a,0x50c06000,0x01644200 + .long 0x082e0000,0xff646700,0x015800ae,0x00008080 + .long 0xff646000,0x014250c0,0x082e0000,0xff646700 + .long 0x014000ae,0x00008080,0xff646000,0x012af291 + .long 0x001a4200,0x082e0000,0xff646700,0x012400ae + .long 0x00008080,0xff646000,0x010e50c0,0x082e0000 + .long 0xff646700,0x010c00ae,0x00008080,0xff646000 + .long 0x00f6f29e,0x001a4200,0x082e0000,0xff646700 + .long 0x00f000ae,0x00008080,0xff646000,0x00da50c0 + .long 0x082e0000,0xff646700,0x00d800ae,0x00008080 + .long 0xff646000,0x00c2f282,0x00084200,0x600000c2 + .long 0x50c06000,0x00bcf28d,0x00084200,0x600000b2 + .long 0x50c06000,0x00acf283,0x00084200,0x600000a2 + .long 0x50c06000,0x009cf28c,0x00084200,0x60000092 + .long 0x50c06000,0x008cf284,0x00084200,0x60000082 + .long 0x50c06000,0x007cf28b,0x00084200,0x60000072 + .long 0x50c06000,0x006cf285,0x00084200,0x60000062 + .long 0x50c06000,0x005cf28a,0x00084200,0x60000052 + .long 0x50c06000,0x004cf286,0x00084200,0x60000042 + .long 0x50c06000,0x003cf289,0x00084200,0x60000032 + .long 0x50c06000,0x002cf287,0x00084200,0x60000022 + .long 0x50c06000,0x001cf288,0x00084200,0x60000012 + .long 0x50c06000,0x000c082e,0x0007ff62,0x66000088 + .long 0x2040122e,0xff412001,0x02010038,0x66102200 + .long 0x02410007,0x200861ff,0x0000172a,0x4e750c01 + .long 0x0018671a,0x0c010020,0x67382008,0x206e000c + .long 0x61ffffff,0x5a7c4a81,0x66000054,0x4e752008 + .long 0x206e000c,0x61ffffff,0x5a684a81,0x66000040 + .long 0x122eff41,0x02410007,0x700161ff,0x00001722 + .long 0x4e752008,0x206e000c,0x61ffffff,0x5a444a81 + .long 0x6600001c,0x122eff41,0x02410007,0x700161ff + .long 0x0000174e,0x4e751d7c,0x0002ff4a,0x4e753d7c + .long 0x00a1000a,0x60ff0000,0x2b86122e,0xff430241 + .long 0x0070e809,0x61ff0000,0x15b20280,0x000000ff + .long 0x2f00103b,0x09200148,0x2f0061ff,0x00000340 + .long 0x201f221f,0x67000134,0x082e0005,0xff426700 + .long 0x00b8082e,0x0004ff42,0x6600001a,0x123b1120 + .long 0x021e082e,0x00050004,0x670a0c2e,0x0008ff4a + .long 0x66024e75,0x22489fc0,0x41d74a01,0x6a0c20ee + .long 0xffdc20ee,0xffe020ee,0xffe4e309,0x6a0c20ee + .long 0xffe820ee,0xffec20ee,0xfff0e309,0x6a0af210 + .long 0xf020d1fc,0x0000000c,0xe3096a0a,0xf210f010 + .long 0xd1fc0000,0x000ce309,0x6a0af210,0xf008d1fc + .long 0x0000000c,0xe3096a0a,0xf210f004,0xd1fc0000 + .long 0x000ce309,0x6a0af210,0xf002d1fc,0x0000000c + .long 0xe3096a0a,0xf210f001,0xd1fc0000,0x000c2d49 + .long 0xff5441d7,0x2f0061ff,0xffff58b2,0x201fdfc0 + .long 0x4a816600,0x071e4e75,0x2d48ff54,0x9fc043d7 + .long 0x2f012f00,0x61ffffff,0x587e201f,0x4a816600 + .long 0x070e221f,0x41d74a01,0x6a0c2d58,0xffdc2d58 + .long 0xffe02d58,0xffe4e309,0x6a0c2d58,0xffe82d58 + .long 0xffec2d58,0xfff0e309,0x6a04f218,0xd020e309 + .long 0x6a04f218,0xd010e309,0x6a04f218,0xd008e309 + .long 0x6a04f218,0xd004e309,0x6a04f218,0xd002e309 + .long 0x6a04f218,0xd001dfc0,0x4e754e75,0x000c0c18 + .long 0x0c181824,0x0c181824,0x18242430,0x0c181824 + .long 0x18242430,0x18242430,0x2430303c,0x0c181824 + .long 0x18242430,0x18242430,0x2430303c,0x18242430 + .long 0x2430303c,0x2430303c,0x303c3c48,0x0c181824 + .long 0x18242430,0x18242430,0x2430303c,0x18242430 + .long 0x2430303c,0x2430303c,0x303c3c48,0x18242430 + .long 0x2430303c,0x2430303c,0x303c3c48,0x2430303c + .long 0x303c3c48,0x303c3c48,0x3c484854,0x0c181824 + .long 0x18242430,0x18242430,0x2430303c,0x18242430 + .long 0x2430303c,0x2430303c,0x303c3c48,0x18242430 + .long 0x2430303c,0x2430303c,0x303c3c48,0x2430303c + .long 0x303c3c48,0x303c3c48,0x3c484854,0x18242430 + .long 0x2430303c,0x2430303c,0x303c3c48,0x2430303c + .long 0x303c3c48,0x303c3c48,0x3c484854,0x2430303c + .long 0x303c3c48,0x303c3c48,0x3c484854,0x303c3c48 + .long 0x3c484854,0x3c484854,0x48545460,0x008040c0 + .long 0x20a060e0,0x109050d0,0x30b070f0,0x088848c8 + .long 0x28a868e8,0x189858d8,0x38b878f8,0x048444c4 + .long 0x24a464e4,0x149454d4,0x34b474f4,0x0c8c4ccc + .long 0x2cac6cec,0x1c9c5cdc,0x3cbc7cfc,0x028242c2 + .long 0x22a262e2,0x129252d2,0x32b272f2,0x0a8a4aca + .long 0x2aaa6aea,0x1a9a5ada,0x3aba7afa,0x068646c6 + .long 0x26a666e6,0x169656d6,0x36b676f6,0x0e8e4ece + .long 0x2eae6eee,0x1e9e5ede,0x3ebe7efe,0x018141c1 + .long 0x21a161e1,0x119151d1,0x31b171f1,0x098949c9 + .long 0x29a969e9,0x199959d9,0x39b979f9,0x058545c5 + .long 0x25a565e5,0x159555d5,0x35b575f5,0x0d8d4dcd + .long 0x2dad6ded,0x1d9d5ddd,0x3dbd7dfd,0x038343c3 + .long 0x23a363e3,0x139353d3,0x33b373f3,0x0b8b4bcb + .long 0x2bab6beb,0x1b9b5bdb,0x3bbb7bfb,0x078747c7 + .long 0x27a767e7,0x179757d7,0x37b777f7,0x0f8f4fcf + .long 0x2faf6fef,0x1f9f5fdf,0x3fbf7fff,0x2040302e + .long 0xff403200,0x0240003f,0x02810000,0x0007303b + .long 0x020a4efb,0x00064afc,0x00400000,0x00000000 + .long 0x00000000,0x00000000,0x00000000,0x00000000 + .long 0x00000000,0x00000000,0x00000080,0x0086008c + .long 0x00900094,0x0098009c,0x00a000a6,0x00b600c6 + .long 0x00d200de,0x00ea00f6,0x01020118,0x01260134 + .long 0x013e0148,0x0152015c,0x0166017a,0x019801b6 + .long 0x01d201ee,0x020a0226,0x02420260,0x02600260 + .long 0x02600260,0x02600260,0x026002c0,0x02da02f4 + .long 0x03140000,0x00000000,0x0000206e,0xffa44e75 + .long 0x206effa8,0x4e75204a,0x4e75204b,0x4e75204c + .long 0x4e75204d,0x4e752056,0x4e75206e,0xffd84e75 + .long 0x202effa4,0x2200d288,0x2d41ffa4,0x20404e75 + .long 0x202effa8,0x2200d288,0x2d41ffa8,0x20404e75 + .long 0x200a2200,0xd2882441,0x20404e75,0x200b2200 + .long 0xd2882641,0x20404e75,0x200c2200,0xd2882841 + .long 0x20404e75,0x200d2200,0xd2882a41,0x20404e75 + .long 0x20162200,0xd2882c81,0x20404e75,0x1d7c0004 + .long 0xff4a202e,0xffd82200,0xd2882d41,0xffd82040 + .long 0x4e75202e,0xffa49088,0x2d40ffa4,0x20404e75 + .long 0x202effa8,0x90882d40,0xffa82040,0x4e75200a + .long 0x90882440,0x20404e75,0x200b9088,0x26402040 + .long 0x4e75200c,0x90882840,0x20404e75,0x200d9088 + .long 0x2a402040,0x4e752016,0x90882c80,0x20404e75 + .long 0x1d7c0008,0xff4a202e,0xffd89088,0x2d40ffd8 + .long 0x20404e75,0x206eff44,0x54aeff44,0x61ffffff + .long 0x54a24a81,0x66ffffff,0x68203040,0xd1eeffa4 + .long 0x4e75206e,0xff4454ae,0xff4461ff,0xffff5484 + .long 0x4a8166ff,0xffff6802,0x3040d1ee,0xffa84e75 + .long 0x206eff44,0x54aeff44,0x61ffffff,0x54664a81 + .long 0x66ffffff,0x67e43040,0xd1ca4e75,0x206eff44 + .long 0x54aeff44,0x61ffffff,0x544a4a81,0x66ffffff + .long 0x67c83040,0xd1cb4e75,0x206eff44,0x54aeff44 + .long 0x61ffffff,0x542e4a81,0x66ffffff,0x67ac3040 + .long 0xd1cc4e75,0x206eff44,0x54aeff44,0x61ffffff + .long 0x54124a81,0x66ffffff,0x67903040,0xd1cd4e75 + .long 0x206eff44,0x54aeff44,0x61ffffff,0x53f64a81 + .long 0x66ffffff,0x67743040,0xd1d64e75,0x206eff44 + .long 0x54aeff44,0x61ffffff,0x53da4a81,0x66ffffff + .long 0x67583040,0xd1eeffd8,0x4e755081,0x61ff0000 + .long 0x0fda2f00,0x206eff44,0x54aeff44,0x61ffffff + .long 0x53b24a81,0x66ffffff,0x6730205f,0x08000008 + .long 0x660000e6,0x2d40ff54,0x2200e959,0x0241000f + .long 0x61ff0000,0x0fa62f02,0x242eff54,0x0802000b + .long 0x660248c0,0x2202ef59,0x02810000,0x0003e3a8 + .long 0x49c2d082,0xd1c0241f,0x4e75206e,0xff4454ae + .long 0xff4461ff,0xffff535c,0x4a8166ff,0xffff66da + .long 0x30404e75,0x206eff44,0x58aeff44,0x61ffffff + .long 0x53584a81,0x66ffffff,0x66c02040,0x4e75206e + .long 0xff4454ae,0xff4461ff,0xffff5328,0x4a8166ff + .long 0xffff66a6,0x3040d1ee,0xff445588,0x4e75206e + .long 0xff4454ae,0xff4461ff,0xffff5308,0x4a8166ff + .long 0xffff6686,0x206eff44,0x55880800,0x00086600 + .long 0x00382d40,0xff542200,0xe9590241,0x000f61ff + .long 0x00000ef8,0x2f02242e,0xff540802,0x000b6602 + .long 0x48c02202,0xef590281,0x00000003,0xe3a849c2 + .long 0xd082d1c0,0x241f4e75,0x08000006,0x670c48e7 + .long 0x3c002a00,0x26084282,0x60282d40,0xff54e9c0 + .long 0x140461ff,0x00000eb4,0x48e73c00,0x24002a2e + .long 0xff542608,0x0805000b,0x660248c2,0xe9c50542 + .long 0xe1aa0805,0x00076702,0x4283e9c5,0x06820c00 + .long 0x00026d34,0x6718206e,0xff4458ae,0xff4461ff + .long 0xffff5276,0x4a8166ff,0x000000b0,0x6018206e + .long 0xff4454ae,0xff4461ff,0xffff5248,0x4a8166ff + .long 0x00000098,0x48c0d680,0xe9c50782,0x6700006e + .long 0x0c000002,0x6d346718,0x206eff44,0x58aeff44 + .long 0x61ffffff,0x52344a81,0x66ff0000,0x006e601c + .long 0x206eff44,0x54aeff44,0x61ffffff,0x52064a81 + .long 0x66ff0000,0x005648c0,0x60024280,0x28000805 + .long 0x00026714,0x204361ff,0xffff5240,0x4a816600 + .long 0x0028d082,0xd0846018,0xd6822043,0x61ffffff + .long 0x522a4a81,0x66000012,0xd0846004,0xd6822003 + .long 0x20404cdf,0x003c4e75,0x20434cdf,0x003c303c + .long 0x010160ff,0xffff6582,0x4cdf003c,0x60ffffff + .long 0x652861ff,0x000023c6,0x303c00e1,0x600a61ff + .long 0x000023ba,0x303c0161,0x206eff54,0x60ffffff + .long 0x6558102e,0xff420c00,0x009c6700,0x00b20c00 + .long 0x00986700,0x00740c00,0x00946736,0x206eff44 + .long 0x58aeff44,0x61ffffff,0x51704a81,0x66ffffff + .long 0x64d82d40,0xff64206e,0xff4458ae,0xff4461ff + .long 0xffff5156,0x4a8166ff,0xffff64be,0x2d40ff68 + .long 0x4e75206e,0xff4458ae,0xff4461ff,0xffff513a + .long 0x4a8166ff,0xffff64a2,0x2d40ff60,0x206eff44 + .long 0x58aeff44,0x61ffffff,0x51204a81,0x66ffffff + .long 0x64882d40,0xff684e75,0x206eff44,0x58aeff44 + .long 0x61ffffff,0x51044a81,0x66ffffff,0x646c2d40 + .long 0xff60206e,0xff4458ae,0xff4461ff,0xffff50ea + .long 0x4a8166ff,0xffff6452,0x2d40ff64,0x4e75206e + .long 0xff4458ae,0xff4461ff,0xffff50ce,0x4a8166ff + .long 0xffff6436,0x2d40ff60,0x206eff44,0x58aeff44 + .long 0x61ffffff,0x50b44a81,0x66ffffff,0x641c2d40 + .long 0xff64206e,0xff4458ae,0xff4461ff,0xffff509a + .long 0x4a8166ff,0xffff6402,0x2d40ff68,0x4e752040 + .long 0x102eff41,0x22000240,0x00380281,0x00000007 + .long 0x0c000018,0x67240c00,0x0020672c,0x80410c00 + .long 0x003c6706,0x206e000c,0x4e751d7c,0x0080ff4a + .long 0x41f60162,0xff680004,0x4e752008,0x61ff0000 + .long 0x0d70206e,0x000c4e75,0x200861ff,0x00000db2 + .long 0x206e000c,0x0c00000c,0x67024e75,0x51882d48 + .long 0x000c4e75,0x102eff41,0x22000240,0x00380281 + .long 0x00000007,0x0c000018,0x670e0c00,0x00206700 + .long 0x0076206e,0x000c4e75,0x323b120e,0x206e000c + .long 0x4efb1006,0x4afc0008,0x0010001a,0x0024002c + .long 0x0034003c,0x0044004e,0x06ae0000,0x000cffa4 + .long 0x4e7506ae,0x0000000c,0xffa84e75,0xd5fc0000 + .long 0x000c4e75,0xd7fc0000,0x000c4e75,0xd9fc0000 + .long 0x000c4e75,0xdbfc0000,0x000c4e75,0x06ae0000 + .long 0x000cffd4,0x4e751d7c,0x0004ff4a,0x06ae0000 + .long 0x000cffd8,0x4e75323b,0x1214206e,0x000c5188 + .long 0x51ae000c,0x4efb1006,0x4afc0008,0x00100016 + .long 0x001c0020,0x00240028,0x002c0032,0x2d48ffa4 + .long 0x4e752d48,0xffa84e75,0x24484e75,0x26484e75 + .long 0x28484e75,0x2a484e75,0x2d48ffd4,0x4e752d48 + .long 0xffd81d7c,0x0008ff4a,0x4e75082e,0x0006ff42 + .long 0x6664102e,0xff430800,0x0005672c,0x08000004 + .long 0x670a0240,0x007f0c40,0x0038661c,0xe9ee0183 + .long 0xff4261ff,0x00000d6a,0x61ff0000,0x12060c00 + .long 0x00066722,0x1d40ff4f,0xe9ee00c3,0xff4261ff + .long 0x00000cbe,0x61ff0000,0x11ea0c00,0x0006670e + .long 0x1d40ff4e,0x4e7561ff,0x00001148,0x60d661ff + .long 0x00001140,0x60ea302e,0xff420800,0x0005672c + .long 0x08000004,0x670a0240,0x007f0c40,0x0038661c + .long 0xe9ee0183,0xff4261ff,0x00000d06,0x61ff0000 + .long 0x11a20c00,0x00066726,0x1d40ff4f,0xe9ee00c3 + .long 0xff42e9ee,0x1283ff40,0x660000be,0x422eff4e + .long 0xe9ee1343,0xff40303b,0x02124efb,0x000e61ff + .long 0x000010e0,0x60d24afc,0x00080010,0x006a0000 + .long 0x0000002e,0x0000004c,0x000061ff,0x00000a5c + .long 0xf2004000,0xf22ef080,0xff6cf281,0x00044e75 + .long 0x1d7c0001,0xff4e4e75,0x61ff0000,0x0a3ef200 + .long 0x5000f22e,0xf080ff6c,0xf2810004,0x4e751d7c + .long 0x0001ff4e,0x4e7561ff,0x00000a20,0xf2005800 + .long 0xf22ef080,0xff6cf281,0x00044e75,0x1d7c0001 + .long 0xff4e4e75,0x61ff0000,0x0a022d40,0xff5441ee + .long 0xff5461ff,0x000011de,0x1d40ff4e,0x0c000005 + .long 0x670001a4,0x0c000004,0x6700015e,0xf2104400 + .long 0xf22ef080,0xff6c4e75,0x422eff4e,0x303b020a + .long 0x4efb0006,0x4afc0008,0x001000e2,0x027202b0 + .long 0x005601a0,0x009c0000,0x700461ff,0xfffffd22 + .long 0x0c2e0080,0xff4a6726,0x61ffffff,0x4dde4a81 + .long 0x66ff0000,0x1eecf200,0x4000f22e,0xf080ff6c + .long 0xf2810004,0x4e751d7c,0x0001ff4e,0x4e7561ff + .long 0xffff4d76,0x4a8166ff,0xffff6e8a,0x60d87002 + .long 0x61ffffff,0xfcdc0c2e,0x0080ff4a,0x672661ff + .long 0xffff4d82,0x4a8166ff,0x00001e98,0xf2005000 + .long 0xf22ef080,0xff6cf281,0x00044e75,0x1d7c0001 + .long 0xff4e4e75,0x61ffffff,0x4d1a4a81,0x66ffffff + .long 0x6e4460d8,0x700161ff,0xfffffc96,0x0c2e0080 + .long 0xff4a6726,0x61ffffff,0x4d264a81,0x66ff0000 + .long 0x1e42f200,0x5800f22e,0xf080ff6c,0xf2810004 + .long 0x4e751d7c,0x0001ff4e,0x4e7561ff,0xffff4cd4 + .long 0x4a8166ff,0xffff6dfe,0x60d87004,0x61ffffff + .long 0xfc500c2e,0x0080ff4a,0x673e61ff,0xffff4d0c + .long 0x2d40ff54,0x4a8166ff,0x00001e16,0x41eeff54 + .long 0x61ff0000,0x10a01d40,0xff4e0c00,0x00046700 + .long 0x00280c00,0x00056700,0x005ef22e,0x4400ff54 + .long 0xf22ef080,0xff6c4e75,0x61ffffff,0x4c8c4a81 + .long 0x66ffffff,0x6da060c4,0x426eff6c,0xe9d00257 + .long 0xe1882d40,0xff7042ae,0xff74426e,0xff6c0810 + .long 0x00076706,0x08ee0007,0xff6c41ee,0xff6c61ff + .long 0x00000e78,0x323c3f81,0x9240836e,0xff6c1d7c + .long 0x0000ff4e,0x4e753d7c,0x7fffff6c,0xe9d00257 + .long 0xe1882d40,0xff7042ae,0xff740810,0x00076706 + .long 0x08ee0007,0xff6c4e75,0x700861ff,0xfffffb92 + .long 0x0c2e0080,0xff4a6740,0x43eeff54,0x700861ff + .long 0xffff4bc4,0x4a8166ff,0x00001d64,0x41eeff54 + .long 0x61ff0000,0x0f701d40,0xff4e0c00,0x00046700 + .long 0x002e0c00,0x00056700,0x0068f22e,0x5400ff54 + .long 0xf22ef080,0xff6c4e75,0x43eeff54,0x700861ff + .long 0xffff4b6e,0x4a8166ff,0xffff6cda,0x60be426e + .long 0xff6ce9d0,0x031f2d40,0xff70e9e8,0x02d50004 + .long 0x720be3a8,0x2d40ff74,0x08100007,0x670608ee + .long 0x0007ff6c,0x41eeff6c,0x61ff0000,0x0dae323c + .long 0x3c019240,0x836eff6c,0x1d7c0000,0xff4e4e75 + .long 0x3d7c7fff,0xff6ce9d0,0x031f2d40,0xff70e9e8 + .long 0x02d50004,0x720be3a8,0x2d40ff74,0x08100007 + .long 0x670608ee,0x0007ff6c,0x4e75700c,0x61ffffff + .long 0xfac043ee,0xff6c700c,0x61ffffff,0x4afa4a81 + .long 0x66ff0000,0x1ca841ee,0xff6c61ff,0x00000e24 + .long 0x0c000006,0x67061d40,0xff4e4e75,0x61ff0000 + .long 0x0d821d40,0xff4e4e75,0x61ff0000,0x125441ee + .long 0xff6c61ff,0x00000dfc,0x0c000006,0x67061d40 + .long 0xff4e4e75,0x61ff0000,0x0d5a1d40,0xff4e4e75 + .long 0xe9ee10c3,0xff42327b,0x120a4efb,0x98064afc + .long 0x000800e0,0x01e00148,0x06200078,0x041a0010 + .long 0x06204a2e,0xff4e664c,0xf228d080,0x0000f200 + .long 0x9000f200,0x7800f23c,0x90000000,0x0000f201 + .long 0xa800836e,0xff66122e,0xff410201,0x00386714 + .long 0x206e000c,0x61ffffff,0x4ae84a81,0x66ff0000 + .long 0x1c0a4e75,0x122eff41,0x02410007,0x61ff0000 + .long 0x07644e75,0x22280000,0x02818000,0x00000081 + .long 0x00800000,0xf2014400,0x60a44a2e,0xff4e664c + .long 0xf228d080,0x0000f200,0x9000f200,0x7000f23c + .long 0x90000000,0x0000f201,0xa800836e,0xff66122e + .long 0xff410201,0x00386714,0x206e000c,0x61ffffff + .long 0x4a964a81,0x66ff0000,0x1bb04e75,0x122eff41 + .long 0x02410007,0x61ff0000,0x06c04e75,0x22280000 + .long 0x02818000,0x00000081,0x00800000,0xf2014400 + .long 0x60a44a2e,0xff4e664c,0xf228d080,0x0000f200 + .long 0x9000f200,0x6000f23c,0x90000000,0x0000f201 + .long 0xa800836e,0xff66122e,0xff410201,0x00386714 + .long 0x206e000c,0x61ffffff,0x4a444a81,0x66ff0000 + .long 0x1b564e75,0x122eff41,0x02410007,0x61ff0000 + .long 0x061c4e75,0x22280000,0x02818000,0x00000081 + .long 0x00800000,0xf2014400,0x60a43d68,0x0000ff84 + .long 0x426eff86,0x2d680004,0xff882d68,0x0008ff8c + .long 0xf228d080,0x000061ff,0xfffff94c,0x224841ee + .long 0xff84700c,0x0c2e0008,0xff4a6726,0x61ffffff + .long 0x492c4a81,0x66000052,0x4a2eff4e,0x66024e75 + .long 0x08ee0003,0xff66102e,0xff620200,0x000a6616 + .long 0x4e7561ff,0xffff5788,0x4a816600,0x002c4a2e + .long 0xff4e66dc,0x4e7541ee,0xff8461ff,0x00000b3c + .long 0x44400240,0x7fff026e,0x8000ff84,0x816eff84 + .long 0xf22ed040,0xff844e75,0x2caeffd4,0x60ff0000 + .long 0x1ab20200,0x00300000,0x00402d40,0xff5c3028 + .long 0x00000240,0x7fff0c40,0x407e6e00,0x00e66700 + .long 0x01520c40,0x3f816d00,0x0058f228,0xd0800000 + .long 0xf22e9000,0xff5cf23c,0x88000000,0x0000f200 + .long 0x6400f23c,0x90000000,0x0000f201,0xa800836e + .long 0xff66122e,0xff410201,0x00386714,0x206e000c + .long 0x61ffffff,0x49184a81,0x66ff0000,0x1a2a4e75 + .long 0x122eff41,0x02410007,0x61ff0000,0x04f04e75 + .long 0x08ee0003,0xff663d68,0x0000ff84,0x2d680004 + .long 0xff882d68,0x0008ff8c,0x2f084280,0x0c2e0004 + .long 0xff4e660a,0x41eeff84,0x61ff0000,0x0a6e41ee + .long 0xff84222e,0xff5c61ff,0x00000c86,0x41eeff84 + .long 0x61ff0000,0x034c122e,0xff410201,0x00386714 + .long 0x206e000c,0x61ffffff,0x48a44a81,0x66ff0000 + .long 0x19b6600e,0x122eff41,0x02410007,0x61ff0000 + .long 0x047c122e,0xff620201,0x000a6600,0x00b8588f + .long 0x4e754a28,0x0007660e,0x4aa80008,0x6608006e + .long 0x1048ff66,0x6006006e,0x1248ff66,0x2f084a28 + .long 0x00005bc1,0x202eff5c,0x61ff0000,0x0d12f210 + .long 0xd080f200,0x6400122e,0xff410201,0x00386714 + .long 0x206e000c,0x61ffffff,0x48344a81,0x66ff0000 + .long 0x1946600e,0x122eff41,0x02410007,0x61ff0000 + .long 0x040c122e,0xff620201,0x000a6600,0x007c588f + .long 0x4e753228,0x00000241,0x80000041,0x3fff3d41 + .long 0xff842d68,0x0004ff88,0x2d680008,0xff8cf22e + .long 0x9000ff5c,0xf22e4800,0xff84f23c,0x90000000 + .long 0x0000f200,0x0018f23c,0x58380002,0xf294fe7c + .long 0x6000ff50,0x205f3d68,0x0000ff84,0x2d680004 + .long 0xff882d68,0x0008ff8c,0x0c2e0004,0xff4e662c + .long 0x41eeff84,0x61ff0000,0x09424480,0x02407fff + .long 0xefee004f,0xff846014,0x205f3d68,0x0000ff84 + .long 0x2d680004,0xff882d68,0x0008ff8c,0x08ae0007 + .long 0xff8456ee,0xff8641ee,0xff84122e,0xff5fe809 + .long 0x0241000c,0x4841122e,0xff5fe809,0x02410003 + .long 0x428061ff,0x00000782,0x4a2eff86,0x670608ee + .long 0x0007ff84,0xf22ed040,0xff844e75,0x02000030 + .long 0x00000080,0x2d40ff5c,0x30280000,0x02407fff + .long 0x0c4043fe,0x6e0000c8,0x67000120,0x0c403c01 + .long 0x6d000046,0xf228d080,0x0000f22e,0x9000ff5c + .long 0xf23c8800,0x00000000,0xf22e7400,0xff54f23c + .long 0x90000000,0x0000f200,0xa800816e,0xff66226e + .long 0x000c41ee,0xff547008,0x61ffffff,0x46304a81 + .long 0x66ff0000,0x18004e75,0x08ee0003,0xff663d68 + .long 0x0000ff84,0x2d680004,0xff882d68,0x0008ff8c + .long 0x2f084280,0x0c2e0004,0xff4e660a,0x41eeff84 + .long 0x61ff0000,0x084641ee,0xff84222e,0xff5c61ff + .long 0x00000a5e,0x41eeff84,0x61ff0000,0x00d22d40 + .long 0xff542d41,0xff58226e,0x000c41ee,0xff547008 + .long 0x61ffffff,0x45c84a81,0x66ff0000,0x1798122e + .long 0xff620201,0x000a6600,0xfe9c588f,0x4e753028 + .long 0x000a0240,0x07ff6608,0x006e1048,0xff666006 + .long 0x006e1248,0xff662f08,0x4a280000,0x5bc1202e + .long 0xff5c61ff,0x00000af8,0xf210d080,0xf22e7400 + .long 0xff54226e,0x000c41ee,0xff547008,0x61ffffff + .long 0x456c4a81,0x66ff0000,0x173c122e,0xff620201 + .long 0x000a6600,0xfe74588f,0x4e753228,0x00000241 + .long 0x80000041,0x3fff3d41,0xff842d68,0x0004ff88 + .long 0x2d680008,0xff8cf22e,0x9000ff5c,0xf22e4800 + .long 0xff84f23c,0x90000000,0x0000f200,0x0018f23c + .long 0x58380002,0xf294feae,0x6000ff64,0x42803028 + .long 0x00000440,0x3fff0640,0x03ff4a28,0x00046b02 + .long 0x53404840,0xe9884a28,0x00006a04,0x08c0001f + .long 0x22280004,0xe9c11054,0x80812d40,0xff542228 + .long 0x00047015,0xe1a92d41,0xff582228,0x0008e9c1 + .long 0x0015222e,0xff588280,0x202eff54,0x4e754280 + .long 0x30280000,0x04403fff,0x0640007f,0x4a280004 + .long 0x6b025340,0x4840ef88,0x4a280000,0x6a0408c0 + .long 0x001f2228,0x00040281,0x7fffff00,0xe0898081 + .long 0x4e7561ff,0xfffff490,0x2f08102e,0xff4e6600 + .long 0x0082082e,0x0004ff42,0x6712122e,0xff43e809 + .long 0x02410007,0x61ff0000,0x00926004,0x102eff43 + .long 0xebc00647,0x2f0041ee,0xff6c61ff,0x00000ed0 + .long 0x02aecfff,0xf00fff84,0x201f4a2e,0xff876616 + .long 0x4aaeff88,0x66104aae,0xff8c660a,0x4a806606 + .long 0x026ef000,0xff8441ee,0xff84225f,0x700c0c2e + .long 0x0008ff4a,0x670e61ff,0xffff4412,0x4a816600 + .long 0xfb384e75,0x61ffffff,0x52864a81,0x6600fb2a + .long 0x4e750c00,0x00046700,0xff7a41ee,0xff6c426e + .long 0xff6e0c00,0x00056702,0x60c0006e,0x4080ff66 + .long 0x08ee0006,0xff7060b2,0x303b1206,0x4efb0002 + .long 0x00200026,0x002c0030,0x00340038,0x003c0040 + .long 0x0044004a,0x00500054,0x0058005c,0x00600064 + .long 0x202eff9c,0x4e75202e,0xffa04e75,0x20024e75 + .long 0x20034e75,0x20044e75,0x20054e75,0x20064e75 + .long 0x20074e75,0x202effa4,0x4e75202e,0xffa84e75 + .long 0x200a4e75,0x200b4e75,0x200c4e75,0x200d4e75 + .long 0x20164e75,0x202effd8,0x4e75323b,0x12064efb + .long 0x10020010,0x0016001c,0x00200024,0x0028002c + .long 0x00302d40,0xff9c4e75,0x2d40ffa0,0x4e752400 + .long 0x4e752600,0x4e752800,0x4e752a00,0x4e752c00 + .long 0x4e752e00,0x4e75323b,0x12064efb,0x10020010 + .long 0x0016001c,0x00200024,0x0028002c,0x00303d40 + .long 0xff9e4e75,0x3d40ffa2,0x4e753400,0x4e753600 + .long 0x4e753800,0x4e753a00,0x4e753c00,0x4e753e00 + .long 0x4e75323b,0x12064efb,0x10020010,0x0016001c + .long 0x00200024,0x0028002c,0x00301d40,0xff9f4e75 + .long 0x1d40ffa3,0x4e751400,0x4e751600,0x4e751800 + .long 0x4e751a00,0x4e751c00,0x4e751e00,0x4e75323b + .long 0x12064efb,0x10020010,0x0016001c,0x00200024 + .long 0x0028002c,0x0030d1ae,0xffa44e75,0xd1aeffa8 + .long 0x4e75d5c0,0x4e75d7c0,0x4e75d9c0,0x4e75dbc0 + .long 0x4e75d196,0x4e751d7c,0x0004ff4a,0x0c000001 + .long 0x6706d1ae,0xffd84e75,0x54aeffd8,0x4e75323b + .long 0x12064efb,0x10020010,0x0016001c,0x00200024 + .long 0x0028002c,0x003091ae,0xffa44e75,0x91aeffa8 + .long 0x4e7595c0,0x4e7597c0,0x4e7599c0,0x4e759bc0 + .long 0x4e759196,0x4e751d7c,0x0008ff4a,0x0c000001 + .long 0x670691ae,0xffd84e75,0x55aeffd8,0x4e75303b + .long 0x02064efb,0x00020010,0x00280040,0x004c0058 + .long 0x00640070,0x007c2d6e,0xffdcff6c,0x2d6effe0 + .long 0xff702d6e,0xffe4ff74,0x41eeff6c,0x4e752d6e + .long 0xffe8ff6c,0x2d6effec,0xff702d6e,0xfff0ff74 + .long 0x41eeff6c,0x4e75f22e,0xf020ff6c,0x41eeff6c + .long 0x4e75f22e,0xf010ff6c,0x41eeff6c,0x4e75f22e + .long 0xf008ff6c,0x41eeff6c,0x4e75f22e,0xf004ff6c + .long 0x41eeff6c,0x4e75f22e,0xf002ff6c,0x41eeff6c + .long 0x4e75f22e,0xf001ff6c,0x41eeff6c,0x4e75303b + .long 0x02064efb,0x00020010,0x00280040,0x004c0058 + .long 0x00640070,0x007c2d6e,0xffdcff78,0x2d6effe0 + .long 0xff7c2d6e,0xffe4ff80,0x41eeff78,0x4e752d6e + .long 0xffe8ff78,0x2d6effec,0xff7c2d6e,0xfff0ff80 + .long 0x41eeff78,0x4e75f22e,0xf020ff78,0x41eeff78 + .long 0x4e75f22e,0xf010ff78,0x41eeff78,0x4e75f22e + .long 0xf008ff78,0x41eeff78,0x4e75f22e,0xf004ff78 + .long 0x41eeff78,0x4e75f22e,0xf002ff78,0x41eeff78 + .long 0x4e75f22e,0xf001ff78,0x41eeff78,0x4e75303b + .long 0x02064efb,0x00020010,0x00180020,0x002a0034 + .long 0x003e0048,0x0052f22e,0xf080ffdc,0x4e75f22e + .long 0xf080ffe8,0x4e75f227,0xe001f21f,0xd0204e75 + .long 0xf227e001,0xf21fd010,0x4e75f227,0xe001f21f + .long 0xd0084e75,0xf227e001,0xf21fd004,0x4e75f227 + .long 0xe001f21f,0xd0024e75,0xf227e001,0xf21fd001 + .long 0x4e750000,0x3f813c01,0xe408323b,0x02f63001 + .long 0x90680000,0x0c400042,0x6a164280,0x082e0001 + .long 0xff666704,0x08c0001d,0x61ff0000,0x001a4e75 + .long 0x203c2000,0x00003141,0x000042a8,0x000442a8 + .long 0x00084e75,0x2d680008,0xff542d40,0xff582001 + .long 0x92680000,0x6f100c41,0x00206d10,0x0c410040 + .long 0x6d506000,0x009a202e,0xff584e75,0x2f023140 + .long 0x00007020,0x90410c41,0x001d6d08,0x142eff58 + .long 0x852eff57,0xe9e82020,0x0004e9e8,0x18000004 + .long 0xe9ee0800,0xff542142,0x00042141,0x0008e8c0 + .long 0x009e6704,0x08c0001d,0x0280e000,0x0000241f + .long 0x4e752f02,0x31400000,0x04410020,0x70209041 + .long 0x142eff58,0x852eff57,0xe9e82020,0x0004e9e8 + .long 0x18000004,0xe8c1009e,0x660ce8ee,0x081fff54 + .long 0x66042001,0x60062001,0x08c0001d,0x42a80004 + .long 0x21420008,0x0280e000,0x0000241f,0x4e753140 + .long 0x00000c41,0x00416d12,0x672442a8,0x000442a8 + .long 0x0008203c,0x20000000,0x4e752028,0x00042200 + .long 0x0280c000,0x00000281,0x3fffffff,0x60122028 + .long 0x00040280,0x80000000,0xe2880281,0x7fffffff + .long 0x66164aa8,0x00086610,0x4a2eff58,0x660a42a8 + .long 0x000442a8,0x00084e75,0x08c0001d,0x42a80004 + .long 0x42a80008,0x4e7561ff,0x00000110,0x4a806700 + .long 0x00fa006e,0x0208ff66,0x327b1206,0x4efb9802 + .long 0x004000ea,0x00240008,0x4a280002,0x6b0000dc + .long 0x70ff4841,0x0c010004,0x6700003e,0x6e000094 + .long 0x60000064,0x4a280002,0x6a0000c0,0x70ff4841 + .long 0x0c010004,0x67000022,0x6e000078,0x60000048 + .long 0xe3806400,0x00a64841,0x0c010004,0x6700000a + .long 0x6e000060,0x60000030,0x06a80000,0x01000004 + .long 0x640ce4e8,0x0004e4e8,0x00065268,0x00004a80 + .long 0x66060268,0xfe000006,0x02a8ffff,0xff000004 + .long 0x42a80008,0x4e7552a8,0x0008641a,0x52a80004 + .long 0x6414e4e8,0x0004e4e8,0x0006e4e8,0x0008e4e8 + .long 0x000a5268,0x00004a80,0x66060228,0x00fe000b + .long 0x4e7506a8,0x00000800,0x0008641a,0x52a80004 + .long 0x6414e4e8,0x0004e4e8,0x0006e4e8,0x0008e4e8 + .long 0x000a5268,0x00004a80,0x66060268,0xf000000a + .long 0x02a8ffff,0xf8000008,0x4e754841,0x0c010004 + .long 0x6700ff86,0x6eea4e75,0x48414a01,0x66044841 + .long 0x4e7548e7,0x30000c01,0x00046622,0xe9e83602 + .long 0x0004741e,0xe5ab2428,0x00040282,0x0000003f + .long 0x66284aa8,0x00086622,0x4a80661e,0x6020e9e8 + .long 0x35420008,0x741ee5ab,0x24280008,0x02820000 + .long 0x01ff6606,0x4a806602,0x600408c3,0x001d2003 + .long 0x4cdf000c,0x48414e75,0x2f022f03,0x20280004 + .long 0x22280008,0xedc02000,0x671ae5a8,0xe9c13022 + .long 0x8083e5a9,0x21400004,0x21410008,0x2002261f + .long 0x241f4e75,0xedc12000,0xe5a90682,0x00000020 + .long 0x21410004,0x42a80008,0x2002261f,0x241f4e75 + .long 0xede80000,0x0004660e,0xede80000,0x00086700 + .long 0x00740640,0x00204281,0x32280000,0x02417fff + .long 0xb0416e1c,0x92403028,0x00000240,0x80008240 + .long 0x31410000,0x61ffffff,0xff82103c,0x00004e75 + .long 0x0c010020,0x6e20e9e8,0x08400004,0x21400004 + .long 0x20280008,0xe3a82140,0x00080268,0x80000000 + .long 0x103c0004,0x4e750441,0x00202028,0x0008e3a8 + .long 0x21400004,0x42a80008,0x02688000,0x0000103c + .long 0x00044e75,0x02688000,0x0000103c,0x00014e75 + .long 0x30280000,0x02407fff,0x0c407fff,0x67480828 + .long 0x00070004,0x6706103c,0x00004e75,0x4a406618 + .long 0x4aa80004,0x660c4aa8,0x00086606,0x103c0001 + .long 0x4e75103c,0x00044e75,0x4aa80004,0x66124aa8 + .long 0x0008660c,0x02688000,0x0000103c,0x00014e75 + .long 0x103c0006,0x4e754aa8,0x00086612,0x20280004 + .long 0x02807fff,0xffff6606,0x103c0002,0x4e750828 + .long 0x00060004,0x6706103c,0x00034e75,0x103c0005 + .long 0x4e752028,0x00002200,0x02807ff0,0x0000670e + .long 0x0c807ff0,0x00006728,0x103c0000,0x4e750281 + .long 0x000fffff,0x66ff0000,0x00144aa8,0x000466ff + .long 0x0000000a,0x103c0001,0x4e75103c,0x00044e75 + .long 0x0281000f,0xffff66ff,0x00000014,0x4aa80004 + .long 0x66ff0000,0x000a103c,0x00024e75,0x08010013 + .long 0x66ff0000,0x000a103c,0x00054e75,0x103c0003 + .long 0x4e752028,0x00002200,0x02807f80,0x0000670e + .long 0x0c807f80,0x0000671e,0x103c0000,0x4e750281 + .long 0x007fffff,0x66ff0000,0x000a103c,0x00014e75 + .long 0x103c0004,0x4e750281,0x007fffff,0x66ff0000 + .long 0x000a103c,0x00024e75,0x08010016,0x66ff0000 + .long 0x000a103c,0x00054e75,0x103c0003,0x4e752f01 + .long 0x08280007,0x000056e8,0x00023228,0x00000241 + .long 0x7fff9240,0x31410000,0x2f08202f,0x00040240 + .long 0x00c0e848,0x61ffffff,0xfae22057,0x322f0006 + .long 0x024100c0,0xe8494841,0x322f0006,0x02410030 + .long 0xe84961ff,0xfffffc22,0x205f08a8,0x00070000 + .long 0x4a280002,0x670a08e8,0x00070000,0x42280002 + .long 0x42804aa8,0x0004660a,0x4aa80008,0x660408c0 + .long 0x0002082e,0x0001ff66,0x670608ee,0x0005ff67 + .long 0x588f4e75,0x2f010828,0x00070000,0x56e80002 + .long 0x32280000,0x02417fff,0x92403141,0x00002f08 + .long 0x428061ff,0xfffffa64,0x2057323c,0x00044841 + .long 0x322f0006,0x02410030,0xe84961ff,0xfffffbaa + .long 0x205f08a8,0x00070000,0x4a280002,0x670a08e8 + .long 0x00070000,0x42280002,0x42804aa8,0x0004660a + .long 0x4aa80008,0x660408c0,0x0002082e,0x0001ff66 + .long 0x670608ee,0x0005ff67,0x588f4e75,0x02410010 + .long 0xe8088200,0x3001e309,0x600e0241,0x00108200 + .long 0x48408200,0x3001e309,0x103b0008,0x41fb1620 + .long 0x4e750200,0x00020200,0x00020200,0x00020000 + .long 0x00000a08,0x0a080a08,0x0a080a08,0x0a087fff + .long 0x00000000,0x00000000,0x00000000,0x00007ffe + .long 0x0000ffff,0xffffffff,0xffff0000,0x00007ffe + .long 0x0000ffff,0xffffffff,0xffff0000,0x00007fff + .long 0x00000000,0x00000000,0x00000000,0x00007fff + .long 0x00000000,0x00000000,0x00000000,0x0000407e + .long 0x0000ffff,0xff000000,0x00000000,0x0000407e + .long 0x0000ffff,0xff000000,0x00000000,0x00007fff + .long 0x00000000,0x00000000,0x00000000,0x00007fff + .long 0x00000000,0x00000000,0x00000000,0x000043fe + .long 0x0000ffff,0xffffffff,0xf8000000,0x000043fe + .long 0x0000ffff,0xffffffff,0xf8000000,0x00007fff + .long 0x00000000,0x00000000,0x00000000,0x00000000 + .long 0x00000000,0x00000000,0x00000000,0x00000000 + .long 0x00000000,0x00000000,0x00000000,0x00000000 + .long 0x00000000,0x00000000,0x00000000,0x00000000 + .long 0x00000000,0x00000000,0x00000000,0x0000ffff + .long 0x00000000,0x00000000,0x00000000,0x0000fffe + .long 0x0000ffff,0xffffffff,0xffff0000,0x0000ffff + .long 0x00000000,0x00000000,0x00000000,0x0000fffe + .long 0x0000ffff,0xffffffff,0xffff0000,0x0000ffff + .long 0x00000000,0x00000000,0x00000000,0x0000c07e + .long 0x0000ffff,0xff000000,0x00000000,0x0000ffff + .long 0x00000000,0x00000000,0x00000000,0x0000c07e + .long 0x0000ffff,0xff000000,0x00000000,0x0000ffff + .long 0x00000000,0x00000000,0x00000000,0x0000c3fe + .long 0x0000ffff,0xffffffff,0xf8000000,0x0000ffff + .long 0x00000000,0x00000000,0x00000000,0x0000c3fe + .long 0x0000ffff,0xffffffff,0xf8000000,0x0000700c + .long 0x61ffffff,0xe82c43ee,0xff6c700c,0x61ffffff + .long 0x38664a81,0x66ff0000,0x0a14e9ee,0x004fff6c + .long 0x0c407fff,0x66024e75,0x102eff6f,0x0200000f + .long 0x660e4aae,0xff706608,0x4aaeff74,0x66024e75 + .long 0x41eeff6c,0x61ff0000,0x001cf22e,0xf080ff6c + .long 0x4e750000,0x00000203,0x02030203,0x03020302 + .long 0x02032d68,0x0000ff84,0x2d680004,0xff882d68 + .long 0x0008ff8c,0x41eeff84,0x48e73c00,0xf227e001 + .long 0x74027604,0x28104281,0x4c3c1001,0x0000000a + .long 0xe9c408c4,0xd2805803,0x51caffee,0x0804001e + .long 0x67024481,0x04810000,0x00106c0e,0x44810084 + .long 0x40000000,0x00904000,0x00002f01,0x7201f23c + .long 0x44000000,0x0000e9d0,0x0704f200,0x58222830 + .long 0x1c007600,0x7407f23c,0x44234120,0x0000e9c4 + .long 0x08c4f200,0x58225803,0x51caffec,0x52810c81 + .long 0x00000002,0x6fd80810,0x001f6704,0xf200001a + .long 0x22170c81,0x0000001b,0x6f0000e4,0x0810001e + .long 0x66744281,0x2810e9c4,0x07046624,0x52817a01 + .long 0x28305c00,0x66085081,0x52852830,0x5c004283 + .long 0x7407e9c4,0x08c46608,0x58835281,0x51cafff4 + .long 0x20012217,0x92806c10,0x44812810,0x00844000 + .long 0x00000090,0x40000000,0x43fb0170,0x00000666 + .long 0x4283f23c,0x44803f80,0x00007403,0xe2806406 + .long 0xf23148a3,0x38000683,0x0000000c,0x4a8066ec + .long 0xf2000423,0x60684281,0x7a022830,0x5c006608 + .long 0x53855081,0x28305c00,0x761c7407,0xe9c408c4 + .long 0x66085983,0x528151ca,0xfff42001,0x22179280 + .long 0x6e104481,0x28100284,0xbfffffff,0x0290bfff + .long 0xffff43fb,0x01700000,0x05fc4283,0xf23c4480 + .long 0x3f800000,0x7403e280,0x6406f231,0x48a33800 + .long 0x06830000,0x000c4a80,0x66ecf200,0x0420262e + .long 0xff60e9c3,0x26822810,0xe582e9c4,0x0002d480 + .long 0x43fafe50,0x10312800,0x4283efc3,0x0682f203 + .long 0x9000e280,0x640a43fb,0x01700000,0x06446016 + .long 0xe280640a,0x43fb0170,0x000006d2,0x600843fb + .long 0x01700000,0x05902001,0x6a084480,0x00904000 + .long 0x00004283,0xf23c4480,0x3f800000,0xe2806406 + .long 0xf23148a3,0x38000683,0x0000000c,0x4a8066ec + .long 0x0810001e,0x6706f200,0x04206004,0xf2000423 + .long 0xf200a800,0x08800009,0x6706006e,0x0108ff66 + .long 0x588ff21f,0xd0404cdf,0x003cf23c,0x90000000 + .long 0x0000f23c,0x88000000,0x00004e75,0x3ffd0000 + .long 0x9a209a84,0xfbcff798,0x00000000,0x3ffd0000 + .long 0x9a209a84,0xfbcff799,0x00000000,0x3f800000 + .long 0x00000000,0x00000000,0x00000000,0x40000000 + .long 0x00000000,0x00000000,0x00000000,0x41200000 + .long 0x00000000,0x00000000,0x00000000,0x459a2800 + .long 0x00000000,0x00000000,0x00000000,0x00000000 + .long 0x03030202,0x03020203,0x02030302,0x48e73f20 + .long 0xf227e007,0xf23c9000,0x00000020,0x2d50ff58 + .long 0x2e00422e,0xff500c2e,0x0004ff4e,0x66000030 + .long 0x30100240,0x7fff2228,0x00042428,0x00085340 + .long 0xe38ae391,0x4a816cf6,0x4a406e04,0x50eeff50 + .long 0x02407fff,0x30802141,0x00042142,0x00082d50 + .long 0xff902d68,0x0004ff94,0x2d680008,0xff9802ae + .long 0x7fffffff,0xff904a2e,0xff506708,0x2c3cffff + .long 0xecbb6038,0x302eff90,0x3d7c3fff,0xff90f22e + .long 0x4800ff90,0x04403fff,0xf2005022,0xf23a4428 + .long 0xff1cf293,0x000ef23a,0x4823ff02,0xf2066000 + .long 0x600af23a,0x4823fee6,0xf2066000,0xf23c8800 + .long 0x00000000,0x42454a87,0x6f042807,0x60062806 + .long 0x98875284,0x4a846f18,0x0c840000,0x00116f12 + .long 0x78114a87,0x6f0c00ae,0x00002080,0xff646002 + .long 0x78014a87,0x6e06be86,0x6d022c07,0x20065280 + .long 0x90844845,0x42454242,0x4a806c14,0x52450c80 + .long 0xffffecd4,0x6e080680,0x00000018,0x74184480 + .long 0xf23a4480,0xfe98e9ee,0x1682ff60,0xe349d245 + .long 0xe3494aae,0xff586c02,0x528145fa,0xfec01632 + .long 0x1800e98b,0xf2039000,0xe88b4a03,0x660a43fb + .long 0x01700000,0x03706016,0xe20b640a,0x43fb0170 + .long 0x000003fe,0x600843fb,0x01700000,0x04904283 + .long 0xe2886406,0xf23148a3,0x38000683,0x0000000c + .long 0x4a8066ec,0xf23c8800,0x00000000,0xf23c9000 + .long 0x00000010,0xf2104800,0xf2000018,0x4a456608 + .long 0xf2000420,0x6000008e,0x4a2eff50,0x67000072 + .long 0xf227e002,0x36170243,0x7fff0050,0x8000d650 + .long 0x04433fff,0xd6690024,0x04433fff,0xd6690030 + .long 0x04433fff,0x6b000048,0x02578000,0x87570250 + .long 0x7fff2f28,0x00082f28,0x00042f3c,0x3fff0000 + .long 0xf21fd080,0xf21f4823,0x2f29002c,0x2f290028 + .long 0x2f3c3fff,0x00002f29,0x00382f29,0x00342f3c + .long 0x3fff0000,0xf21f4823,0xf21f4823,0x601660fe + .long 0x4a42670c,0xf2294823,0x0024f229,0x48230030 + .long 0xf2000423,0xf200a800,0xf22e6800,0xff9045ee + .long 0xff900800,0x0009670e,0x00aa0000,0x00010008 + .long 0xf22e4800,0xff902d6e,0xff60ff54,0x02ae0000 + .long 0x0030ff60,0x48e7c0c0,0x2f2eff54,0x2f2eff58 + .long 0x41eeff90,0xf2106800,0x4aaeff58,0x6c060090 + .long 0x80000000,0x2f2eff64,0xf22e9000,0xff60f23c + .long 0x88000000,0x0000f22e,0x4801ff90,0xf200a800 + .long 0x816eff66,0x1d57ff64,0x588f2d5f,0xff582d5f + .long 0xff544cdf,0x03032d6e,0xff58ff90,0x2d6eff54 + .long 0xff604845,0x4a4566ff,0x00000086,0xf23a4500 + .long 0xfcec2004,0x53804283,0xe2886406,0xf2314923 + .long 0x38000683,0x0000000c,0x4a8066ec,0x4a2eff50 + .long 0x670af200,0x001860ff,0x00000028,0xf2000018 + .long 0xf2000838,0xf293001a,0x53863a3c,0x0001f23c + .long 0x90000000,0x0020f23a,0x4523fcc2,0x6000fda8 + .long 0xf23a4523,0xfcb8f200,0x0838f294,0x005cf292 + .long 0x000cf23a,0x4420fca6,0x5286604c,0x52863a3c + .long 0x0001f23c,0x90000000,0x00206000,0xfd7af23a + .long 0x4500fc6a,0x20044283,0xe2886406,0xf2314923 + .long 0x38000683,0x0000000c,0x4a8066ec,0xf2000018 + .long 0xf2000838,0xf28e0012,0xf23a4420,0xfc605286 + .long 0x5284f23a,0x4523fc56,0xf23c9000,0x00000010 + .long 0xf2000820,0x41eeff84,0xf2106800,0x24280004 + .long 0x26280008,0x42a80004,0x42a80008,0x20104840 + .long 0x67140480,0x00003ffd,0x4a806e0a,0x4480e28a + .long 0xe29351c8,0xfffa4a82,0x66044a83,0x67104281 + .long 0x06830000,0x0080d581,0x0283ffff,0xff802004 + .long 0x568861ff,0x000002b0,0x4a2eff50,0x6728f200 + .long 0x003af281,0x000cf206,0x4000f200,0x0018602e + .long 0x4a876d08,0xf23a4400,0xfbe46022,0xf2064000 + .long 0xf2000018,0x6018f200,0x003af28e,0x000af23a + .long 0x4400fb9a,0x6008f206,0x4000f200,0x0018f229 + .long 0x48200018,0xf22e6800,0xff90242a,0x0004262a + .long 0x00083012,0x670e0440,0x3ffd4440,0xe28ae293 + .long 0x51c8fffa,0x42810683,0x00000080,0xd5810283 + .long 0xffffff80,0x700441ee,0xff5461ff,0x00000228 + .long 0x202eff54,0x720ce2a8,0xefee010c,0xff84e2a8 + .long 0xefee0404,0xff844a00,0x670800ae,0x00002080 + .long 0xff644280,0x022e000f,0xff844aae,0xff586c02 + .long 0x70024a86,0x6c025280,0xefee0002,0xff84f23c + .long 0x88000000,0x0000f21f,0xd0e04cdf,0x04fc4e75 + .long 0x40020000,0xa0000000,0x00000000,0x40050000 + .long 0xc8000000,0x00000000,0x400c0000,0x9c400000 + .long 0x00000000,0x40190000,0xbebc2000,0x00000000 + .long 0x40340000,0x8e1bc9bf,0x04000000,0x40690000 + .long 0x9dc5ada8,0x2b70b59e,0x40d30000,0xc2781f49 + .long 0xffcfa6d5,0x41a80000,0x93ba47c9,0x80e98ce0 + .long 0x43510000,0xaa7eebfb,0x9df9de8e,0x46a30000 + .long 0xe319a0ae,0xa60e91c7,0x4d480000,0xc9767586 + .long 0x81750c17,0x5a920000,0x9e8b3b5d,0xc53d5de5 + .long 0x75250000,0xc4605202,0x8a20979b,0x40020000 + .long 0xa0000000,0x00000000,0x40050000,0xc8000000 + .long 0x00000000,0x400c0000,0x9c400000,0x00000000 + .long 0x40190000,0xbebc2000,0x00000000,0x40340000 + .long 0x8e1bc9bf,0x04000000,0x40690000,0x9dc5ada8 + .long 0x2b70b59e,0x40d30000,0xc2781f49,0xffcfa6d6 + .long 0x41a80000,0x93ba47c9,0x80e98ce0,0x43510000 + .long 0xaa7eebfb,0x9df9de8e,0x46a30000,0xe319a0ae + .long 0xa60e91c7,0x4d480000,0xc9767586,0x81750c18 + .long 0x5a920000,0x9e8b3b5d,0xc53d5de5,0x75250000 + .long 0xc4605202,0x8a20979b,0x40020000,0xa0000000 + .long 0x00000000,0x40050000,0xc8000000,0x00000000 + .long 0x400c0000,0x9c400000,0x00000000,0x40190000 + .long 0xbebc2000,0x00000000,0x40340000,0x8e1bc9bf + .long 0x04000000,0x40690000,0x9dc5ada8,0x2b70b59d + .long 0x40d30000,0xc2781f49,0xffcfa6d5,0x41a80000 + .long 0x93ba47c9,0x80e98cdf,0x43510000,0xaa7eebfb + .long 0x9df9de8d,0x46a30000,0xe319a0ae,0xa60e91c6 + .long 0x4d480000,0xc9767586,0x81750c17,0x5a920000 + .long 0x9e8b3b5d,0xc53d5de4,0x75250000,0xc4605202 + .long 0x8a20979a,0x48e7ff00,0x7e015380,0x28022a03 + .long 0xe9c21003,0xe782e9c3,0x6003e783,0x8486e385 + .long 0xe3944846,0xd346d685,0x4e71d584,0x4e71d346 + .long 0x48464a47,0x67124847,0xe947de41,0x10c74847 + .long 0x424751c8,0xffc86012,0x48473e01,0x48475247 + .long 0x51c8ffba,0x4847e94f,0x10c74cdf,0x00ff4e75 + .long 0x70016100,0x00d63d7c,0x0121000a,0x6000007e + .long 0x70026100,0x00c63d7c,0x0141000a,0x606e7004 + .long 0x610000b8,0x3d7c0101,0x000a6060,0x70086100 + .long 0x00aa3d7c,0x0161000a,0x6052700c,0x6100009c + .long 0x3d7c0161,0x000a6044,0x70016100,0x008e3d7c + .long 0x00a1000a,0x60367002,0x61000080,0x3d7c00c1 + .long 0x000a6028,0x70046100,0x00723d7c,0x0081000a + .long 0x601a7008,0x61000064,0x3d7c00e1,0x000a600c + .long 0x700c6100,0x00563d7c,0x00e1000a,0x2d6eff68 + .long 0x0006f22e,0xd0c0ffdc,0xf22e9c00,0xff604cee + .long 0x0303ff9c,0x4e5e2f17,0x2f6f0008,0x00042f6f + .long 0x000c0008,0x2f7c0000,0x0001000c,0x3f6f0006 + .long 0x000c3f7c,0x40080006,0x08170005,0x670608ef + .long 0x0002000d,0x60ffffff,0x2d82122e,0xff410201 + .long 0x00380c01,0x00186700,0x000c0c01,0x00206700 + .long 0x00604e75,0x122eff41,0x02410007,0x323b1206 + .long 0x4efb1002,0x00100016,0x001c0020,0x00240028 + .long 0x002c0030,0x91aeffa4,0x4e7591ae,0xffa84e75 + .long 0x95c04e75,0x97c04e75,0x99c04e75,0x9bc04e75 + .long 0x91964e75,0x0c2e0030,0x000a6612,0x082e0005 + .long 0x0004660a,0x4e7a8800,0x91c04e7b,0x88004e75 + .long 0x448060a0,0x00000000,0x00000000,0x00000000 diff --git a/arch/m68k/ifpsp060/fskeleton.S b/arch/m68k/ifpsp060/fskeleton.S new file mode 100644 index 000000000..0a1ae4f44 --- /dev/null +++ b/arch/m68k/ifpsp060/fskeleton.S @@ -0,0 +1,342 @@ +|~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +|MOTOROLA MICROPROCESSOR & MEMORY TECHNOLOGY GROUP +|M68000 Hi-Performance Microprocessor Division +|M68060 Software Package +|Production Release P1.00 -- October 10, 1994 +| +|M68060 Software Package Copyright © 1993, 1994 Motorola Inc. All rights reserved. +| +|THE SOFTWARE is provided on an "AS IS" basis and without warranty. +|To the maximum extent permitted by applicable law, +|MOTOROLA DISCLAIMS ALL WARRANTIES WHETHER EXPRESS OR IMPLIED, +|INCLUDING IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE +|and any warranty against infringement with regard to the SOFTWARE +|(INCLUDING ANY MODIFIED VERSIONS THEREOF) and any accompanying written materials. +| +|To the maximum extent permitted by applicable law, +|IN NO EVENT SHALL MOTOROLA BE LIABLE FOR ANY DAMAGES WHATSOEVER +|(INCLUDING WITHOUT LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, +|BUSINESS INTERRUPTION, LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY LOSS) +|ARISING OF THE USE OR INABILITY TO USE THE SOFTWARE. +|Motorola assumes no responsibility for the maintenance and support of the SOFTWARE. +| +|You are hereby granted a copyright license to use, modify, and distribute the SOFTWARE +|so long as this entire notice is retained without alteration in any modified and/or +|redistributed versions, and that such modified versions are clearly identified as such. +|No licenses are granted by implication, estoppel or otherwise under any patents +|or trademarks of Motorola, Inc. +|~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +| fskeleton.s +| +| This file contains: +| (1) example "Call-out"s +| (2) example package entry code +| (3) example "Call-out" table +| + +#include + +|################################ +| (1) EXAMPLE CALL-OUTS # +| # +| _060_fpsp_done() # +| _060_real_ovfl() # +| _060_real_unfl() # +| _060_real_operr() # +| _060_real_snan() # +| _060_real_dz() # +| _060_real_inex() # +| _060_real_bsun() # +| _060_real_fline() # +| _060_real_fpu_disabled() # +| _060_real_trap() # +|################################ + +| +| _060_fpsp_done(): +| +| This is the main exit point for the 68060 Floating-Point +| Software Package. For a normal exit, all 060FPSP routines call this +| routine. The operating system can do system dependent clean-up or +| simply execute an "rte" as with the sample code below. +| + .global _060_fpsp_done +_060_fpsp_done: + bral _060_isp_done | do the same as isp_done + +| +| _060_real_ovfl(): +| +| This is the exit point for the 060FPSP when an enabled overflow exception +| is present. The routine below should point to the operating system handler +| for enabled overflow conditions. The exception stack frame is an overflow +| stack frame. The FP state frame holds the EXCEPTIONAL OPERAND. +| +| The sample routine below simply clears the exception status bit and +| does an "rte". +| + .global _060_real_ovfl +_060_real_ovfl: + fsave -(%sp) + move.w #0x6000,0x2(%sp) + frestore (%sp)+ + bral trap | jump to trap handler + + +| +| _060_real_unfl(): +| +| This is the exit point for the 060FPSP when an enabled underflow exception +| is present. The routine below should point to the operating system handler +| for enabled underflow conditions. The exception stack frame is an underflow +| stack frame. The FP state frame holds the EXCEPTIONAL OPERAND. +| +| The sample routine below simply clears the exception status bit and +| does an "rte". +| + .global _060_real_unfl +_060_real_unfl: + fsave -(%sp) + move.w #0x6000,0x2(%sp) + frestore (%sp)+ + bral trap | jump to trap handler + +| +| _060_real_operr(): +| +| This is the exit point for the 060FPSP when an enabled operand error exception +| is present. The routine below should point to the operating system handler +| for enabled operand error exceptions. The exception stack frame is an operand error +| stack frame. The FP state frame holds the source operand of the faulting +| instruction. +| +| The sample routine below simply clears the exception status bit and +| does an "rte". +| + .global _060_real_operr +_060_real_operr: + fsave -(%sp) + move.w #0x6000,0x2(%sp) + frestore (%sp)+ + bral trap | jump to trap handler + +| +| _060_real_snan(): +| +| This is the exit point for the 060FPSP when an enabled signalling NaN exception +| is present. The routine below should point to the operating system handler +| for enabled signalling NaN exceptions. The exception stack frame is a signalling NaN +| stack frame. The FP state frame holds the source operand of the faulting +| instruction. +| +| The sample routine below simply clears the exception status bit and +| does an "rte". +| + .global _060_real_snan +_060_real_snan: + fsave -(%sp) + move.w #0x6000,0x2(%sp) + frestore (%sp)+ + bral trap | jump to trap handler + +| +| _060_real_dz(): +| +| This is the exit point for the 060FPSP when an enabled divide-by-zero exception +| is present. The routine below should point to the operating system handler +| for enabled divide-by-zero exceptions. The exception stack frame is a divide-by-zero +| stack frame. The FP state frame holds the source operand of the faulting +| instruction. +| +| The sample routine below simply clears the exception status bit and +| does an "rte". +| + .global _060_real_dz +_060_real_dz: + fsave -(%sp) + move.w #0x6000,0x2(%sp) + frestore (%sp)+ + bral trap | jump to trap handler + +| +| _060_real_inex(): +| +| This is the exit point for the 060FPSP when an enabled inexact exception +| is present. The routine below should point to the operating system handler +| for enabled inexact exceptions. The exception stack frame is an inexact +| stack frame. The FP state frame holds the source operand of the faulting +| instruction. +| +| The sample routine below simply clears the exception status bit and +| does an "rte". +| + .global _060_real_inex +_060_real_inex: + fsave -(%sp) + move.w #0x6000,0x2(%sp) + frestore (%sp)+ + bral trap | jump to trap handler + +| +| _060_real_bsun(): +| +| This is the exit point for the 060FPSP when an enabled bsun exception +| is present. The routine below should point to the operating system handler +| for enabled bsun exceptions. The exception stack frame is a bsun +| stack frame. +| +| The sample routine below clears the exception status bit, clears the NaN +| bit in the FPSR, and does an "rte". The instruction that caused the +| bsun will now be re-executed but with the NaN FPSR bit cleared. +| + .global _060_real_bsun +_060_real_bsun: +| fsave -(%sp) + + fmove.l %fpsr,-(%sp) + andi.b #0xfe,(%sp) + fmove.l (%sp)+,%fpsr + + bral trap | jump to trap handler + +| +| _060_real_fline(): +| +| This is the exit point for the 060FPSP when an F-Line Illegal exception is +| encountered. Three different types of exceptions can enter the F-Line exception +| vector number 11: FP Unimplemented Instructions, FP implemented instructions when +| the FPU is disabled, and F-Line Illegal instructions. The 060FPSP module +| _fpsp_fline() distinguishes between the three and acts appropriately. F-Line +| Illegals branch here. +| + .global _060_real_fline +_060_real_fline: + bral trap | jump to trap handler + +| +| _060_real_fpu_disabled(): +| +| This is the exit point for the 060FPSP when an FPU disabled exception is +| encountered. Three different types of exceptions can enter the F-Line exception +| vector number 11: FP Unimplemented Instructions, FP implemented instructions when +| the FPU is disabled, and F-Line Illegal instructions. The 060FPSP module +| _fpsp_fline() distinguishes between the three and acts appropriately. FPU disabled +| exceptions branch here. +| +| The sample code below enables the FPU, sets the PC field in the exception stack +| frame to the PC of the instruction causing the exception, and does an "rte". +| The execution of the instruction then proceeds with an enabled floating-point +| unit. +| + .global _060_real_fpu_disabled +_060_real_fpu_disabled: + move.l %d0,-(%sp) | enabled the fpu + .long 0x4E7A0808 |movec pcr,%d0 + bclr #0x1,%d0 + .long 0x4E7B0808 |movec %d0,pcr + move.l (%sp)+,%d0 + + move.l 0xc(%sp),0x2(%sp) | set "Current PC" + rte + +| +| _060_real_trap(): +| +| This is the exit point for the 060FPSP when an emulated "ftrapcc" instruction +| discovers that the trap condition is true and it should branch to the operating +| system handler for the trap exception vector number 7. +| +| The sample code below simply executes an "rte". +| + .global _060_real_trap +_060_real_trap: + bral trap | jump to trap handler + +|############################################################################ + +|################################# +| (2) EXAMPLE PACKAGE ENTRY CODE # +|################################# + + .global _060_fpsp_snan +_060_fpsp_snan: + bra.l _FP_CALL_TOP+0x80+0x00 + + .global _060_fpsp_operr +_060_fpsp_operr: + bra.l _FP_CALL_TOP+0x80+0x08 + + .global _060_fpsp_ovfl +_060_fpsp_ovfl: + bra.l _FP_CALL_TOP+0x80+0x10 + + .global _060_fpsp_unfl +_060_fpsp_unfl: + bra.l _FP_CALL_TOP+0x80+0x18 + + .global _060_fpsp_dz +_060_fpsp_dz: + bra.l _FP_CALL_TOP+0x80+0x20 + + .global _060_fpsp_inex +_060_fpsp_inex: + bra.l _FP_CALL_TOP+0x80+0x28 + + .global _060_fpsp_fline +_060_fpsp_fline: + bra.l _FP_CALL_TOP+0x80+0x30 + + .global _060_fpsp_unsupp +_060_fpsp_unsupp: + bra.l _FP_CALL_TOP+0x80+0x38 + + .global _060_fpsp_effadd +_060_fpsp_effadd: + bra.l _FP_CALL_TOP+0x80+0x40 + +|############################################################################ + +|############################### +| (3) EXAMPLE CALL-OUT SECTION # +|############################### + +| The size of this section MUST be 128 bytes!!! + +_FP_CALL_TOP: + .long _060_real_bsun - _FP_CALL_TOP + .long _060_real_snan - _FP_CALL_TOP + .long _060_real_operr - _FP_CALL_TOP + .long _060_real_ovfl - _FP_CALL_TOP + .long _060_real_unfl - _FP_CALL_TOP + .long _060_real_dz - _FP_CALL_TOP + .long _060_real_inex - _FP_CALL_TOP + .long _060_real_fline - _FP_CALL_TOP + .long _060_real_fpu_disabled - _FP_CALL_TOP + .long _060_real_trap - _FP_CALL_TOP + .long _060_real_trace - _FP_CALL_TOP + .long _060_real_access - _FP_CALL_TOP + .long _060_fpsp_done - _FP_CALL_TOP + + .long 0x00000000, 0x00000000, 0x00000000 + + .long _060_imem_read - _FP_CALL_TOP + .long _060_dmem_read - _FP_CALL_TOP + .long _060_dmem_write - _FP_CALL_TOP + .long _060_imem_read_word - _FP_CALL_TOP + .long _060_imem_read_long - _FP_CALL_TOP + .long _060_dmem_read_byte - _FP_CALL_TOP + .long _060_dmem_read_word - _FP_CALL_TOP + .long _060_dmem_read_long - _FP_CALL_TOP + .long _060_dmem_write_byte - _FP_CALL_TOP + .long _060_dmem_write_word - _FP_CALL_TOP + .long _060_dmem_write_long - _FP_CALL_TOP + + .long 0x00000000 + + .long 0x00000000, 0x00000000, 0x00000000, 0x00000000 + +|############################################################################ + +| 060 FPSP KERNEL PACKAGE NEEDS TO GO HERE!!! + +#include "fpsp.sa" diff --git a/arch/m68k/ifpsp060/ftest.sa b/arch/m68k/ifpsp060/ftest.sa new file mode 100644 index 000000000..b365bc2fd --- /dev/null +++ b/arch/m68k/ifpsp060/ftest.sa @@ -0,0 +1,371 @@ + dc.l $60ff0000,$00d40000,$60ff0000,$016c0000 + dc.l $60ff0000,$01a80000,$54657374,$696e6720 + dc.l $36383036,$30204650,$53502073,$74617274 + dc.l $65643a0a,$00546573,$74696e67,$20363830 + dc.l $36302046,$50535020,$756e696d,$706c656d + dc.l $656e7465,$6420696e,$73747275,$6374696f + dc.l $6e207374,$61727465,$643a0a00,$54657374 + dc.l $696e6720,$36383036,$30204650,$53502065 + dc.l $78636570,$74696f6e,$20656e61,$626c6564 + dc.l $20737461,$72746564,$3a0a0070,$61737365 + dc.l $640a0020,$6661696c,$65640a00,$4a80660e + dc.l $487affe9,$61ff0000,$1642588f,$4e752f01 + dc.l $61ff0000,$164c588f,$487affd9,$61ff0000 + dc.l $162a588f,$4e754e56,$fe8048e7,$3f3cf227 + dc.l $e0ff487a,$ff3461ff,$00001610,$588f42ae + dc.l $fea0487b,$01700000,$058061ff,$000015fc + dc.l $588f61ff,$00000588,$61ffffff,$ffa242ae + dc.l $fea0487b,$01700000,$126c61ff,$000015dc + dc.l $588f61ff,$00001280,$61ffffff,$ff8242ae + dc.l $fea0487b,$01700000,$0b6461ff,$000015bc + dc.l $61ff0000,$0b7261ff,$ffffff64,$42aefea0 + dc.l $487b0170,$00000de2,$61ff0000,$159e61ff + dc.l $00000df0,$61ffffff,$ff464cdf,$3cfcf21f + dc.l $d0ff4e5e,$4e754e56,$fe8048e7,$3f3cf227 + dc.l $e0ff487a,$feb161ff,$00001570,$588f42ae + dc.l $fea0487b,$01700000,$00fe61ff,$0000155c + dc.l $588f61ff,$00000110,$61ffffff,$ff024cdf + dc.l $3cfcf21f,$d0ff4e5e,$4e754e56,$fe8048e7 + dc.l $3f3cf227,$e0ff487a,$fea461ff,$0000152c + dc.l $588f42ae,$fea0487b,$01700000,$0f1461ff + dc.l $00001518,$61ff0000,$0f1a61ff,$fffffec0 + dc.l $42aefea0,$487b0170,$00000fd2,$61ff0000 + dc.l $14fa61ff,$00000fd8,$61ffffff,$fea242ae + dc.l $fea0487b,$01700000,$0b6061ff,$000014dc + dc.l $61ff0000,$0b6a61ff,$fffffe84,$42aefea0 + dc.l $487b0170,$00000c22,$61ff0000,$14be61ff + dc.l $00000c2c,$61ffffff,$fe6642ae,$fea0487b + dc.l $01700000,$105661ff,$000014a0,$61ff0000 + dc.l $105a61ff,$fffffe48,$42aefea0,$487b0170 + dc.l $00000da2,$61ff0000,$148261ff,$00000da8 + dc.l $61ffffff,$fe2a4cdf,$3cfcf21f,$d0ff4e5e + dc.l $4e750955,$6e696d70,$6c656d65,$6e746564 + dc.l $20465020,$696e7374,$72756374,$696f6e73 + dc.l $2e2e2e00,$52aefea0,$4cfb3fff,$01700000 + dc.l $1390f23b,$d0ff0170,$000013c6,$f23b9c00 + dc.l $01700000,$141c3d7c,$0000fea6,$48ee7fff + dc.l $ff80f22e,$f0ffff20,$f22ebc00,$feb42d7c + dc.l $40000000,$fe802d7c,$c90fdaa2,$fe842d7c + dc.l $2168c235,$fe8844fc,$0000f22e,$480efe80 + dc.l $42eefea4,$48ee7fff,$ffc0f22e,$f0fffec0 + dc.l $f22ebc00,$fea82d7c,$bfbf0000,$ff202d7c + dc.l $80000000,$ff242d7c,$00000000,$ff282d7c + dc.l $08000208,$feb841fa,$ffc22d48,$febc61ff + dc.l $00001288,$4a0066ff,$000012ae,$61ff0000 + dc.l $12b04a00,$66ff0000,$12a052ae,$fea04cfb + dc.l $3fff0170,$000012da,$f23bd0ff,$01700000 + dc.l $1310f23b,$9c000170,$00001366,$3d7c0000 + dc.l $fea648ee,$7fffff80,$f22ef0ff,$ff20f22e + dc.l $bc00feb4,$2d7c3ffe,$0000fe80,$2d7cc90f + dc.l $daa2fe84,$2d7c2168,$c235fe88,$44fc0000 + dc.l $f22e480f,$fe8042ee,$fea448ee,$7fffffc0 + dc.l $f22ef0ff,$fec0f22e,$bc00fea8,$2d7c3fff + dc.l $0000ff20,$2d7c8000,$0000ff24,$2d7c0000 + dc.l $0000ff28,$2d7c0000,$0208feb8,$41faffc2 + dc.l $2d48febc,$61ff0000,$11d24a00,$66ff0000 + dc.l $11f861ff,$000011fa,$4a0066ff,$000011ea + dc.l $52aefea0,$4cfb3fff,$01700000,$1224f23b + dc.l $d0ff0170,$0000125a,$f23b9c00,$01700000 + dc.l $12b03d7c,$0000fea6,$48ee7fff,$ff80f22e + dc.l $f0ffff20,$f22ebc00,$feb444fc,$0000f200 + dc.l $5c3142ee,$fea448ee,$7fffffc0,$f22ef0ff + dc.l $fec0f22e,$bc00fea8,$2d7c4000,$0000ff20 + dc.l $2d7c935d,$8dddff24,$2d7caaa8,$ac17ff28 + dc.l $2d7c0000,$0208feb8,$41faffc4,$2d48febc + dc.l $61ff0000,$11364a00,$66ff0000,$115c61ff + dc.l $0000115e,$4a0066ff,$0000114e,$52aefea0 + dc.l $4cfb3fff,$01700000,$1188f23b,$d0ff0170 + dc.l $000011be,$f23b9c00,$01700000,$1214f23c + dc.l $88000f00,$00007e00,$3d7c0000,$fea648ee + dc.l $7fffff80,$f22ef0ff,$ff20f22e,$bc00feb4 + dc.l $44fc0000,$f2470012,$42eefea4,$48ee7fff + dc.l $ffc0f22e,$f0fffec0,$f22ebc00,$fea82d7c + dc.l $0f008080,$feb841fa,$ffdc2d48,$febc61ff + dc.l $000010a8,$4a0066ff,$000010ce,$61ff0000 + dc.l $10d04a00,$66ff0000,$10c052ae,$fea04cfb + dc.l $3fff0170,$000010fa,$f23bd0ff,$01700000 + dc.l $1130f23b,$9c000170,$00001186,$f23c8800 + dc.l $0f000000,$7e023d7c,$0000fea6,$48ee7fff + dc.l $ff80f22e,$f0ffff20,$f22ebc00,$feb444fc + dc.l $0000f24f,$0012fffc,$42eefea4,$48ee7fff + dc.l $ffc0f22e,$f0fffec0,$f22ebc00,$fea83d7c + dc.l $ffffff9e,$2d7c0f00,$8080feb8,$41faffd4 + dc.l $2d48febc,$61ff0000,$10124a00,$66ff0000 + dc.l $103861ff,$0000103a,$4a0066ff,$0000102a + dc.l $52aefea0,$4cfb3fff,$01700000,$1064f23b + dc.l $d0ff0170,$0000109a,$f23b9c00,$01700000 + dc.l $10f0f23c,$88000f00,$00003d7c,$0000fea6 + dc.l $48ee7fff,$ff80f22e,$f0ffff20,$f22ebc00 + dc.l $feb444fc,$0000f27b,$0012abcd,$ef0142ee + dc.l $fea448ee,$7fffffc0,$f22ef0ff,$fec0f22e + dc.l $bc00fea8,$2d7c0f00,$8080feb8,$41faffd8 + dc.l $2d48febc,$61ff0000,$0f824a00,$66ff0000 + dc.l $0fa861ff,$00000faa,$4a0066ff,$00000f9a + dc.l $42804e75,$09556e69,$6d706c65,$6d656e74 + dc.l $6564203c,$65613e2e,$2e2e0000,$52aefea0 + dc.l $4cfb3fff,$01700000,$0fb8f23b,$d0ff0170 + dc.l $00000fee,$f23b9c00,$01700000,$10443d7c + dc.l $0000fea6,$48ee7fff,$ff80f22e,$f0ffff20 + dc.l $f22ebc00,$feb4f23c,$58000002,$44fc0000 + dc.l $f23c4823,$c0000000,$80000000,$00000000 + dc.l $42eefea4,$48ee7fff,$ffc0f22e,$f0fffec0 + dc.l $f22ebc00,$fea82d7c,$c0010000,$ff202d7c + dc.l $80000000,$ff242d7c,$00000000,$ff282d7c + dc.l $08000000,$feb841fa,$ffb82d48,$febc61ff + dc.l $00000eb8,$4a0066ff,$00000ede,$61ff0000 + dc.l $0ee04a00,$66ff0000,$0ed052ae,$fea04cfb + dc.l $3fff0170,$00000f0a,$f23bd0ff,$01700000 + dc.l $0f40f23b,$9c000170,$00000f96,$3d7c0000 + dc.l $fea648ee,$7fffff80,$f22ef0ff,$ff20f22e + dc.l $bc00feb4,$44fc0000,$f23c4c18,$c1230001 + dc.l $23456789,$12345678,$42eefea4,$48ee7fff + dc.l $ffc0f22e,$f0fffec0,$f22ebc00,$fea82d7c + dc.l $3e660000,$ff202d7c,$d0ed23e8,$ff242d7c + dc.l $d14035bc,$ff282d7c,$00000108,$feb841fa + dc.l $ffb82d48,$febc61ff,$00000e10,$4a0066ff + dc.l $00000e36,$61ff0000,$0e384a00,$66ff0000 + dc.l $0e2852ae,$fea04cfb,$3fff0170,$00000e62 + dc.l $f23bd0ff,$01700000,$0e98f23b,$9c000170 + dc.l $00000eee,$3d7c0000,$fea644fc,$000048ee + dc.l $7fffff80,$f22ef0ff,$ff20f22e,$bc00feb4 + dc.l $f23c9800,$ffffffff,$ffffffff,$42eefea4 + dc.l $48ee7fff,$ffc0f22e,$f0fffec0,$f22ebc00 + dc.l $fea82d7c,$0000fff0,$feb42d7c,$0ffffff8 + dc.l $feb861ff,$00000d84,$4a0066ff,$00000daa + dc.l $61ff0000,$0dac4a00,$66ff0000,$0d9c52ae + dc.l $fea04cfb,$3fff0170,$00000dd6,$f23bd0ff + dc.l $01700000,$0e0cf23b,$9c000170,$00000e62 + dc.l $3d7c0000,$fea644fc,$000048ee,$7fffff80 + dc.l $f22ef0ff,$ff20f22e,$bc00feb4,$f23c9400 + dc.l $ffffffff,$ffffffff,$42eefea4,$48ee7fff + dc.l $ffc0f22e,$f0fffec0,$f22ebc00,$fea82d7c + dc.l $0000fff0,$feb42d7c,$ffffffff,$febc61ff + dc.l $00000cf8,$4a0066ff,$00000d1e,$61ff0000 + dc.l $0d204a00,$66ff0000,$0d1052ae,$fea04cfb + dc.l $3fff0170,$00000d4a,$f23bd0ff,$01700000 + dc.l $0d80f23b,$9c000170,$00000dd6,$3d7c0000 + dc.l $fea644fc,$000048ee,$7fffff80,$f22ef0ff + dc.l $ff20f22e,$bc00feb4,$f23c8c00,$ffffffff + dc.l $ffffffff,$42eefea4,$48ee7fff,$ffc0f22e + dc.l $f0fffec0,$f22ebc00,$fea82d7c,$0ffffff8 + dc.l $feb82d7c,$ffffffff,$febc61ff,$00000c6c + dc.l $4a0066ff,$00000c92,$61ff0000,$0c944a00 + dc.l $66ff0000,$0c8452ae,$fea04cfb,$3fff0170 + dc.l $00000cbe,$f23bd0ff,$01700000,$0cf4f23b + dc.l $9c000170,$00000d4a,$3d7c0000,$fea644fc + dc.l $000048ee,$7fffff80,$f22ef0ff,$ff20f22e + dc.l $bc00feb4,$f23c9c00,$ffffffff,$ffffffff + dc.l $ffffffff,$42eefea4,$48ee7fff,$ffc0f22e + dc.l $f0fffec0,$f22ebc00,$fea82d7c,$0000fff0 + dc.l $feb42d7c,$0ffffff8,$feb82d7c,$ffffffff + dc.l $febc61ff,$00000bd4,$4a0066ff,$00000bfa + dc.l $61ff0000,$0bfc4a00,$66ff0000,$0bec52ae + dc.l $fea04cfb,$3fff0170,$00000c26,$f23bd0ff + dc.l $01700000,$0c5cf23b,$9c000170,$00000cb2 + dc.l $f23c5800,$0001f23c,$58800002,$f23c5900 + dc.l $0003f23c,$59800004,$f23c5a00,$0005f23c + dc.l $5a800006,$f23c5b00,$0007f23c,$5b800008 + dc.l $f23c8400,$00000000,$70aa3d7c,$0000fea6 + dc.l $48eeffff,$ff80f22e,$bc00feb4,$f22ef0ff + dc.l $ff2044fc,$0000f227,$e80042ee,$fea4f22e + dc.l $bc00fea8,$f23c4480,$7f800000,$f23c4580 + dc.l $7f800000,$f23c4680,$7f800000,$f23c4780 + dc.l $7f800000,$f21f4880,$f21f4980,$f21f4a80 + dc.l $f21f4b80,$48eeffff,$ffc0f22e,$f0fffec0 + dc.l $61ff0000,$0af64a00,$66ff0000,$0b1c61ff + dc.l $00000b1e,$4a0066ff,$00000b0e,$52aefea0 + dc.l $4cfb3fff,$01700000,$0b48f23b,$d0ff0170 + dc.l $00000b7e,$f23b9c00,$01700000,$0bd4f23c + dc.l $58000001,$f23c5880,$0002f23c,$59000003 + dc.l $f23c5980,$0004f23c,$5a000005,$f23c5a80 + dc.l $0006f23c,$5b000007,$f23c5b80,$0008f227 + dc.l $6b00f227,$6a00f227,$6900f227,$6800f22e + dc.l $f0ffff20,$f23c4700,$7f800000,$f23c4600 + dc.l $7f800000,$f23c4500,$7f800000,$f23c4400 + dc.l $7f800000,$f23c8400,$00000000,$f23c8800 + dc.l $00000000,$70aa3d7c,$0000fea6,$48eeffff + dc.l $ff80f22e,$bc00feb4,$44fc0000,$f21fd800 + dc.l $42eefea4,$f22ebc00,$fea848ee,$ffffffc0 + dc.l $f22ef0ff,$fec061ff,$00000a10,$4a0066ff + dc.l $00000a36,$61ff0000,$0a384a00,$66ff0000 + dc.l $0a2852ae,$fea04cfb,$3fff0170,$00000a62 + dc.l $f23bd0ff,$01700000,$0a98f23b,$9c000170 + dc.l $00000aee,$f23c5800,$0001f23c,$58800002 + dc.l $f23c5900,$0003f23c,$59800004,$f23c5a00 + dc.l $0005f23c,$5a800006,$f23c5b00,$0007f23c + dc.l $5b800008,$f23c8400,$00000000,$203cffff + dc.l $ff003d7c,$0000fea6,$48eeffff,$ff80f22e + dc.l $bc00feb4,$f22ef0ff,$ff2044fc,$0000f227 + dc.l $e80042ee,$fea4f22e,$bc00fea8,$48eeffff + dc.l $ffc0f22e,$f0fffec0,$61ff0000,$095e4a00 + dc.l $66ff0000,$098461ff,$00000986,$4a0066ff + dc.l $00000976,$42804e75,$094e6f6e,$2d6d6173 + dc.l $6b61626c,$65206f76,$6572666c,$6f772e2e + dc.l $2e0051fc,$52aefea0,$4cfb3fff,$01700000 + dc.l $0990f23b,$d0ff0170,$000009c6,$f23b9c00 + dc.l $01700000,$0a1c3d7c,$0000fea6,$48ee7fff + dc.l $ff80f22e,$f0ffff20,$f22ebc00,$feb4f23c + dc.l $58000002,$2d7c7ffe,$0000fe80,$2d7c8000 + dc.l $0000fe84,$2d7c0000,$0000fe88,$44fc0000 + dc.l $f22e4823,$fe8042ee,$fea448ee,$7fffffc0 + dc.l $f22ef0ff,$fec0f22e,$bc00fea8,$2d7c7fff + dc.l $0000ff20,$2d7c0000,$0000ff24,$2d7c0000 + dc.l $0000ff28,$2d7c0200,$1048feb8,$41faffc2 + dc.l $2d48febc,$61ff0000,$08824a00,$66ff0000 + dc.l $08a861ff,$000008aa,$4a0066ff,$0000089a + dc.l $42804e75,$09456e61,$626c6564,$206f7665 + dc.l $72666c6f,$772e2e2e,$000051fc,$52aefea0 + dc.l $4cfb3fff,$01700000,$08b8f23b,$d0ff0170 + dc.l $000008ee,$f23b9c00,$01700000,$09443d7c + dc.l $0000fea6,$48ee7fff,$ff80f22e,$f0ffff20 + dc.l $f23c9000,$00001000,$f22ebc00,$feb4f23c + dc.l $58000002,$2d7c7ffe,$0000fe80,$2d7c8000 + dc.l $0000fe84,$2d7c0000,$0000fe88,$44fc0000 + dc.l $f22e4823,$fe8042ee,$fea448ee,$7fffffc0 + dc.l $f22ef0ff,$fec0f22e,$bc00fea8,$2d7c7fff + dc.l $0000ff20,$2d7c0000,$0000ff24,$2d7c0000 + dc.l $0000ff28,$2d7c0200,$1048feb8,$41faffc2 + dc.l $2d48febc,$61ff0000,$07a24a00,$66ff0000 + dc.l $07c861ff,$000007ca,$4a0066ff,$000007ba + dc.l $42804e75,$09456e61,$626c6564,$20756e64 + dc.l $6572666c,$6f772e2e,$2e0051fc,$52aefea0 + dc.l $4cfb3fff,$01700000,$07d8f23b,$d0ff0170 + dc.l $0000080e,$f23b9c00,$01700000,$08643d7c + dc.l $0000fea6,$48ee7fff,$ff80f22e,$f0ffff20 + dc.l $f23c9000,$00000800,$f22ebc00,$feb42d7c + dc.l $00000000,$fe802d7c,$80000000,$fe842d7c + dc.l $00000000,$fe88f22e,$d080fe80,$44fc0000 + dc.l $f23c5820,$000242ee,$fea448ee,$7fffffc0 + dc.l $f22ef0ff,$fec0f22e,$bc00fea8,$2d7c0000 + dc.l $0000ff20,$2d7c4000,$0000ff24,$2d7c0000 + dc.l $0000ff28,$2d7c0000,$0800feb8,$41faffc2 + dc.l $2d48febc,$61ff0000,$06c24a00,$66ff0000 + dc.l $06e861ff,$000006ea,$4a0066ff,$000006da + dc.l $42804e75,$094e6f6e,$2d6d6173,$6b61626c + dc.l $6520756e,$64657266,$6c6f772e,$2e2e0000 + dc.l $52aefea0,$4cfb3fff,$01700000,$06f4f23b + dc.l $d0ff0170,$0000072a,$f23b9c00,$01700000 + dc.l $07803d7c,$0000fea6,$48ee7fff,$ff80f22e + dc.l $f0ffff20,$f22ebc00,$feb42d7c,$00000000 + dc.l $fe802d7c,$80000000,$fe842d7c,$00000000 + dc.l $fe88f22e,$d080fe80,$44fc0000,$f23c5820 + dc.l $000242ee,$fea448ee,$7fffffc0,$f22ef0ff + dc.l $fec0f22e,$bc00fea8,$2d7c0000,$0000ff20 + dc.l $2d7c4000,$0000ff24,$2d7c0000,$0000ff28 + dc.l $2d7c0000,$0800feb8,$41faffc2,$2d48febc + dc.l $61ff0000,$05e64a00,$66ff0000,$060c61ff + dc.l $0000060e,$4a0066ff,$000005fe,$42804e75 + dc.l $09456e61,$626c6564,$20696e65,$78616374 + dc.l $2e2e2e00,$52aefea0,$4cfb3fff,$01700000 + dc.l $0620f23b,$d0ff0170,$00000656,$f23b9c00 + dc.l $01700000,$06ac3d7c,$0000fea6,$48ee7fff + dc.l $ff80f22e,$f0ffff20,$f23c9000,$00000200 + dc.l $f22ebc00,$feb42d7c,$50000000,$fe802d7c + dc.l $80000000,$fe842d7c,$00000000,$fe88f22e + dc.l $d080fe80,$44fc0000,$f23c5822,$000242ee + dc.l $fea448ee,$7fffffc0,$f22ef0ff,$fec0f22e + dc.l $bc00fea8,$2d7c5000,$0000ff20,$2d7c8000 + dc.l $0000ff24,$2d7c0000,$0000ff28,$2d7c0000 + dc.l $0208feb8,$41faffc2,$2d48febc,$61ff0000 + dc.l $050a4a00,$66ff0000,$053061ff,$00000532 + dc.l $4a0066ff,$00000522,$42804e75,$09456e61 + dc.l $626c6564,$20534e41,$4e2e2e2e,$000051fc + dc.l $52aefea0,$4cfb3fff,$01700000,$0544f23b + dc.l $d0ff0170,$0000057a,$f23b9c00,$01700000 + dc.l $05d03d7c,$0000fea6,$48ee7fff,$ff80f22e + dc.l $f0ffff20,$f23c9000,$00004000,$f22ebc00 + dc.l $feb42d7c,$ffff0000,$fe802d7c,$00000000 + dc.l $fe842d7c,$00000001,$fe88f22e,$d080fe80 + dc.l $44fc0000,$f23c5822,$000242ee,$fea448ee + dc.l $7fffffc0,$f22ef0ff,$fec0f22e,$bc00fea8 + dc.l $2d7cffff,$0000ff20,$2d7c0000,$0000ff24 + dc.l $2d7c0000,$0001ff28,$2d7c0900,$4080feb8 + dc.l $41faffc2,$2d48febc,$61ff0000,$042e4a00 + dc.l $66ff0000,$045461ff,$00000456,$4a0066ff + dc.l $00000446,$42804e75,$09456e61,$626c6564 + dc.l $204f5045,$52522e2e,$2e0051fc,$52aefea0 + dc.l $4cfb3fff,$01700000,$0468f23b,$d0ff0170 + dc.l $0000049e,$f23b9c00,$01700000,$04f43d7c + dc.l $0000fea6,$48ee7fff,$ff80f22e,$f0ffff20 + dc.l $f23c9000,$00002000,$f22ebc00,$feb42d7c + dc.l $ffff0000,$fe802d7c,$00000000,$fe842d7c + dc.l $00000000,$fe88f22e,$d080fe80,$44fc0000 + dc.l $f23c4422,$7f800000,$42eefea4,$48ee7fff + dc.l $ffc0f22e,$f0fffec0,$f22ebc00,$fea82d7c + dc.l $ffff0000,$ff202d7c,$00000000,$ff242d7c + dc.l $00000000,$ff282d7c,$01002080,$feb841fa + dc.l $ffc02d48,$febc61ff,$00000350,$4a0066ff + dc.l $00000376,$61ff0000,$03784a00,$66ff0000 + dc.l $03684280,$4e750945,$6e61626c,$65642044 + dc.l $5a2e2e2e,$000051fc,$52aefea0,$4cfb3fff + dc.l $01700000,$038cf23b,$d0ff0170,$000003c2 + dc.l $f23b9c00,$01700000,$04183d7c,$0000fea6 + dc.l $48ee7fff,$ff80f22e,$f0ffff20,$f23c9000 + dc.l $00000400,$f22ebc00,$feb42d7c,$40000000 + dc.l $fe802d7c,$80000000,$fe842d7c,$00000000 + dc.l $fe88f22e,$d080fe80,$44fc0000,$f23c5820 + dc.l $000042ee,$fea448ee,$7fffffc0,$f22ef0ff + dc.l $fec0f22e,$bc00fea8,$2d7c4000,$0000ff20 + dc.l $2d7c8000,$0000ff24,$2d7c0000,$0000ff28 + dc.l $2d7c0200,$0410feb8,$41faffc2,$2d48febc + dc.l $61ff0000,$02764a00,$66ff0000,$029c61ff + dc.l $0000029e,$4a0066ff,$0000028e,$42804e75 + dc.l $09556e69,$6d706c65,$6d656e74,$65642064 + dc.l $61746120,$74797065,$2f666f72,$6d61742e + dc.l $2e2e0000,$52aefea0,$4cfb3fff,$01700000 + dc.l $02a0f23b,$d0ff0170,$000002d6,$f23b9c00 + dc.l $01700000,$032c3d7c,$0000fea6,$48ee7fff + dc.l $ff80f22e,$f0ffff20,$f22ebc00,$feb42d7c + dc.l $c03f0000,$fe802d7c,$00000000,$fe842d7c + dc.l $00000001,$fe88f23c,$58000002,$44fc0000 + dc.l $f22e4823,$fe8042ee,$fea448ee,$7fffffc0 + dc.l $f22ef0ff,$fec0f22e,$bc00fea8,$2d7cc001 + dc.l $0000ff20,$2d7c8000,$0000ff24,$2d7c0000 + dc.l $0000ff28,$2d7c0800,$0000feb8,$41faffc2 + dc.l $2d48febc,$61ff0000,$01924a00,$66ff0000 + dc.l $01b861ff,$000001ba,$4a0066ff,$000001aa + dc.l $52aefea0,$4cfb3fff,$01700000,$01e4f23b + dc.l $d0ff0170,$0000021a,$f23b9c00,$01700000 + dc.l $02703d7c,$0000fea6,$48ee7fff,$ff80f22e + dc.l $f0ffff20,$f22ebc00,$feb42d7c,$80000000 + dc.l $fe802d7c,$01000000,$fe842d7c,$00000000 + dc.l $fe88f23c,$40007fff,$ffff44fc,$0000f22e + dc.l $4823fe80,$42eefea4,$48ee7fff,$ffc0f22e + dc.l $f0fffec0,$f22ebc00,$fea82d7c,$80170000 + dc.l $ff202d7c,$fffffffe,$ff242d7c,$00000000 + dc.l $ff282d7c,$08000000,$feb841fa,$ffc22d48 + dc.l $febc61ff,$000000d4,$4a0066ff,$000000fa + dc.l $61ff0000,$00fc4a00,$66ff0000,$00ec52ae + dc.l $fea04cfb,$3fff0170,$00000126,$f23bd0ff + dc.l $01700000,$015cf23b,$9c000170,$000001b2 + dc.l $3d7c0000,$fea648ee,$7fffff80,$f22ef0ff + dc.l $ff20f22e,$bc00feb4,$2d7cc123,$0001fe80 + dc.l $2d7c2345,$6789fe84,$2d7c1234,$5678fe88 + dc.l $44fc0000,$f22e4c18,$fe8042ee,$fea448ee + dc.l $7fffffc0,$f22ef0ff,$fec0f22e,$bc00fea8 + dc.l $2d7c3e66,$0000ff20,$2d7cd0ed,$23e8ff24 + dc.l $2d7cd140,$35bcff28,$2d7c0000,$0108feb8 + dc.l $41faffc2,$2d48febc,$61ff0000,$001e4a00 + dc.l $66ff0000,$004461ff,$00000046,$4a0066ff + dc.l $00000036,$42804e75,$41eeff80,$43eeffc0 + dc.l $700eb189,$66ff0000,$001c51c8,$fff6302e + dc.l $fea6322e,$fea4b041,$66ff0000,$00084280 + dc.l $4e757001,$4e75222e,$fea07001,$4e7541ee + dc.l $ff2043ee,$fec07017,$b18966ff,$0000002c + dc.l $51c8fff6,$41eefeb4,$43eefea8,$b18966ff + dc.l $00000018,$b18966ff,$00000010,$b18966ff + dc.l $00000008,$42804e75,$70014e75,$acacacac + dc.l $acacacac,$acacacac,$acacacac,$acacacac + dc.l $acacacac,$acacacac,$acacacac,$acacacac + dc.l $acacacac,$acacacac,$acacacac,$acacacac + dc.l $acacacac,$acacacac,$acacacac,$7fff0000 + dc.l $ffffffff,$ffffffff,$7fff0000,$ffffffff + dc.l $ffffffff,$7fff0000,$ffffffff,$ffffffff + dc.l $7fff0000,$ffffffff,$ffffffff,$7fff0000 + dc.l $ffffffff,$ffffffff,$7fff0000,$ffffffff + dc.l $ffffffff,$7fff0000,$ffffffff,$ffffffff + dc.l $7fff0000,$ffffffff,$ffffffff,$00000000 + dc.l $00000000,$00000000,$2f00203a,$e884487b + dc.l $0930ffff,$e880202f,$00044e74,$00042f00 + dc.l $203ae872,$487b0930,$ffffe86a,$202f0004 + dc.l $4e740004,$00000000,$00000000,$00000000 diff --git a/arch/m68k/ifpsp060/ilsp.doc b/arch/m68k/ifpsp060/ilsp.doc new file mode 100644 index 000000000..4e6292f09 --- /dev/null +++ b/arch/m68k/ifpsp060/ilsp.doc @@ -0,0 +1,150 @@ +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +MOTOROLA MICROPROCESSOR & MEMORY TECHNOLOGY GROUP +M68000 Hi-Performance Microprocessor Division +M68060 Software Package +Production Release P1.00 -- October 10, 1994 + +M68060 Software Package Copyright © 1993, 1994 Motorola Inc. All rights reserved. + +THE SOFTWARE is provided on an "AS IS" basis and without warranty. +To the maximum extent permitted by applicable law, +MOTOROLA DISCLAIMS ALL WARRANTIES WHETHER EXPRESS OR IMPLIED, +INCLUDING IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE +and any warranty against infringement with regard to the SOFTWARE +(INCLUDING ANY MODIFIED VERSIONS THEREOF) and any accompanying written materials. + +To the maximum extent permitted by applicable law, +IN NO EVENT SHALL MOTOROLA BE LIABLE FOR ANY DAMAGES WHATSOEVER +(INCLUDING WITHOUT LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, +BUSINESS INTERRUPTION, LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY LOSS) +ARISING OF THE USE OR INABILITY TO USE THE SOFTWARE. +Motorola assumes no responsibility for the maintenance and support of the SOFTWARE. + +You are hereby granted a copyright license to use, modify, and distribute the SOFTWARE +so long as this entire notice is retained without alteration in any modified and/or +redistributed versions, and that such modified versions are clearly identified as such. +No licenses are granted by implication, estoppel or otherwise under any patents +or trademarks of Motorola, Inc. +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +68060 INTEGER SOFTWARE PACKAGE (Library version) +------------------------------------------------- + +The file ilsp.s contains the "Library version" of the +68060 Integer Software Package. Routines included in this +module can be used to emulate 64-bit divide and multiply, +and the "cmp2" instruction. These instructions are not +implemented in hardware on the 68060 and normally take +exception vector #61 "Unimplemented Integer Instruction". + +By re-compiling a program that uses these instructions, and +making subroutine calls in place of the unimplemented +instructions, a program can avoid the overhead associated with +taking the exception. + +Release file format: +-------------------- +The file ilsp.sa is essentially a hexadecimal image of the +release package. This is the ONLY format which will be supported. +The hex image was created by assembling the source code and +then converting the resulting binary output image into an +ASCII text file. The hexadecimal numbers are listed +using the Motorola Assembly Syntax assembler directive "dc.l" +(define constant longword). The file can be converted to other +assembly syntaxes by using any word processor with a global +search and replace function. + +To assist in assembling and linking this module with other modules, +the installer should add a symbolic label to the top of the file. +This will allow calling routines to access the entry points +of this package. + +The source code ilsp.s has also been included but only for +documentation purposes. + +Release file structure: +----------------------- +The file ilsp.sa contains an "Entry-Point" section and a +code section. The ILSP has no "Call-Out" section. The first section +is the "Entry-Point" section. In order to access a function in the +package, a program must "bsr" or "jsr" to the location listed +below in "68060ILSP Entry Points" that corresponds to the desired +function. A branch instruction located at the selected entry point +within the package will then enter the correct emulation code routine. + +The entry point addresses at the beginning of the package will remain +fixed so that a program calling the routines will not have to be +re-compiled with every new 68060ILSP release. + +For example, to use a 64-bit multiply instruction, +do a "bsr" or "jsr" to the entry point defined by +the 060ILSP entry table. A compiler generated code sequence +for unsigned multiply could look like: + +# mulu.l ,Dh:Dl +# mulu.l _multiplier,%d1:%d0 + + subq.l &0x8,%sp # make room for result on stack + pea (%sp) # pass: result addr on stack + mov.l %d0,-(%sp) # pass: multiplicand on stack + mov.l _multiplier,-(%sp) # pass: multiplier on stack + bsr.l _060LISP_TOP+0x18 # branch to multiply routine + add.l &0xc,%sp # clear arguments from stack + mov.l (%sp)+,%d1 # load result[63:32] + mov.l (%sp)+,%d0 # load result[31:0] + +For a divide: + +# divu.l ,Dr:Dq +# divu.l _divisor,%d1:%d0 + + subq.l &0x8,%sp # make room for result on stack + pea (%sp) # pass: result addr on stack + mov.l %d0,-(%sp) # pass: dividend hi on stack + mov.l %d1,-(%sp) # pass: dividend hi on stack + mov.l _divisor,-(%sp) # pass: divisor on stack + bsr.l _060LISP_TOP+0x08 # branch to divide routine + add.l &0xc,%sp # clear arguments from stack + mov.l (%sp)+,%d1 # load remainder + mov.l (%sp)+,%d0 # load quotient + +The library routines also return the correct condition code +register value. If this is important, then the caller of the library +routine must make sure that the value isn't lost while popping +other items off of the stack. + +An example of using the "cmp2" instruction is as follows: + +# cmp2.l ,Rn +# cmp2.l _bounds,%d0 + + pea _bounds # pass ptr to bounds + mov.l %d0,-(%sp) # pass Rn + bsr.l _060LSP_TOP_+0x48 # branch to "cmp2" routine + mov.w %cc,_tmp # save off condition codes + addq.l &0x8,%sp # clear arguments from stack + +Exception reporting: +-------------------- +If the instruction being emulated is a divide and the source +operand is a zero, then the library routine, as its last +instruction, executes an implemented divide using a zero +source operand so that an "Integer Divide-by-Zero" exception +will be taken. Although the exception stack frame will not +point to the correct instruction, the user will at least be able +to record that such an event occurred if desired. + +68060ILSP entry points: +----------------------- +_060ILSP_TOP: +0x000: _060LSP__idivs64_ +0x008: _060LSP__idivu64_ + +0x010: _060LSP__imuls64_ +0x018: _060LSP__imulu64_ + +0x020: _060LSP__cmp2_Ab_ +0x028: _060LSP__cmp2_Aw_ +0x030: _060LSP__cmp2_Al_ +0x038: _060LSP__cmp2_Db_ +0x040: _060LSP__cmp2_Dw_ +0x048: _060LSP__cmp2_Dl_ diff --git a/arch/m68k/ifpsp060/ilsp.sa b/arch/m68k/ifpsp060/ilsp.sa new file mode 100644 index 000000000..2757d502b --- /dev/null +++ b/arch/m68k/ifpsp060/ilsp.sa @@ -0,0 +1,101 @@ + dc.l $60ff0000,$01fe0000,$60ff0000,$02080000 + dc.l $60ff0000,$04900000,$60ff0000,$04080000 + dc.l $60ff0000,$051e0000,$60ff0000,$053c0000 + dc.l $60ff0000,$055a0000,$60ff0000,$05740000 + dc.l $60ff0000,$05940000,$60ff0000,$05b40000 + dc.l $51fc51fc,$51fc51fc,$51fc51fc,$51fc51fc + dc.l $51fc51fc,$51fc51fc,$51fc51fc,$51fc51fc + dc.l $51fc51fc,$51fc51fc,$51fc51fc,$51fc51fc + dc.l $51fc51fc,$51fc51fc,$51fc51fc,$51fc51fc + dc.l $51fc51fc,$51fc51fc,$51fc51fc,$51fc51fc + dc.l $51fc51fc,$51fc51fc,$51fc51fc,$51fc51fc + dc.l $51fc51fc,$51fc51fc,$51fc51fc,$51fc51fc + dc.l $51fc51fc,$51fc51fc,$51fc51fc,$51fc51fc + dc.l $51fc51fc,$51fc51fc,$51fc51fc,$51fc51fc + dc.l $51fc51fc,$51fc51fc,$51fc51fc,$51fc51fc + dc.l $51fc51fc,$51fc51fc,$51fc51fc,$51fc51fc + dc.l $51fc51fc,$51fc51fc,$51fc51fc,$51fc51fc + dc.l $51fc51fc,$51fc51fc,$51fc51fc,$51fc51fc + dc.l $51fc51fc,$51fc51fc,$51fc51fc,$51fc51fc + dc.l $51fc51fc,$51fc51fc,$51fc51fc,$51fc51fc + dc.l $51fc51fc,$51fc51fc,$51fc51fc,$51fc51fc + dc.l $51fc51fc,$51fc51fc,$51fc51fc,$51fc51fc + dc.l $51fc51fc,$51fc51fc,$51fc51fc,$51fc51fc + dc.l $51fc51fc,$51fc51fc,$51fc51fc,$51fc51fc + dc.l $51fc51fc,$51fc51fc,$51fc51fc,$51fc51fc + dc.l $51fc51fc,$51fc51fc,$51fc51fc,$51fc51fc + dc.l $51fc51fc,$51fc51fc,$51fc51fc,$51fc51fc + dc.l $51fc51fc,$51fc51fc,$51fc51fc,$51fc51fc + dc.l $51fc51fc,$51fc51fc,$51fc51fc,$51fc51fc + dc.l $51fc51fc,$51fc51fc,$51fc51fc,$51fc51fc + dc.l $51fc51fc,$51fc51fc,$51fc51fc,$51fc51fc + dc.l $51fc51fc,$51fc51fc,$51fc51fc,$51fc51fc + dc.l $4e56fff0,$48e73f00,$42eefff0,$50eeffff + dc.l $60104e56,$fff048e7,$3f0042ee,$fff051ee + dc.l $ffff2e2e,$00086700,$00ae2a2e,$000c2c2e + dc.l $00104a2e,$ffff671a,$4a875dee,$fffe6a02 + dc.l $44874a85,$5deefffd,$6a0844fc,$00004086 + dc.l $40854a85,$66164a86,$67000046,$be866306 + dc.l $cb466000,$00124c47,$6005600a,$be85634c + dc.l $61ff0000,$00864a2e,$ffff6724,$4a2efffd + dc.l $67024485,$102efffe,$b12efffd,$670c0c86 + dc.l $80000000,$62264486,$60060806,$001f661c + dc.l $026e0010,$fff044ee,$fff04a86,$48f60060 + dc.l $01610014,$4cdf00fc,$4e5e4e75,$2a2e000c + dc.l $2c2e0010,$026e001c,$fff0006e,$0002fff0 + dc.l $44eefff0,$60d62dae,$000c0161,$00142dae + dc.l $00100162,$00140004,$44eefff0,$4cdf00fc + dc.l $4e5e80fc,$00004e75,$0c870000,$ffff621e + dc.l $42814845,$48463a06,$8ac73205,$48463a06 + dc.l $8ac74841,$32054245,$48452c01,$4e7542ae + dc.l $fff8422e,$fffc4281,$0807001f,$660e52ae + dc.l $fff8e38f,$e38ee395,$6000ffee,$26072405 + dc.l $48424843,$b4436606,$323cffff,$600a2205 + dc.l $82c30281,$0000ffff,$2f064246,$48462607 + dc.l $2401c4c7,$4843c6c1,$28059883,$48443004 + dc.l $38064a40,$6600000a,$b4846304,$538160de + dc.l $2f052c01,$48462a07,$61ff0000,$006a2405 + dc.l $26062a1f,$2c1f9c83,$9b8264ff,$0000001a + dc.l $53814282,$26074843,$4243dc83,$db822607 + dc.l $42434843,$da834a2e,$fffc6616,$3d41fff4 + dc.l $42814845,$48463a06,$424650ee,$fffc6000 + dc.l $ff6c3d41,$fff63c05,$48464845,$2e2efff8 + dc.l $670a5387,$e28de296,$51cffffa,$2a062c2e + dc.l $fff44e75,$24062606,$28054843,$4844ccc5 + dc.l $cac3c4c4,$c6c44284,$4846dc45,$d744dc42 + dc.l $d7444846,$42454242,$48454842,$da82da83 + dc.l $4e754e56,$fffc48e7,$380042ee,$fffc202e + dc.l $00086700,$005a222e,$000c6700,$00522400 + dc.l $26002801,$48434844,$c0c1c2c3,$c4c4c6c4 + dc.l $42844840,$d041d784,$d042d784,$48404241 + dc.l $42424841,$4842d282,$d283382e,$fffc0204 + dc.l $00104a81,$6a040004,$000844c4,$c34048f6 + dc.l $00030161,$00104cdf,$001c4e5e,$4e754280 + dc.l $4281382e,$fffc0204,$00100004,$000444c4 + dc.l $60da4e56,$fffc48e7,$3c0042ee,$fffc202e + dc.l $000867da,$222e000c,$67d44205,$4a806c06 + dc.l $44800005,$00014a81,$6c064481,$0a050001 + dc.l $24002600,$28014843,$4844c0c1,$c2c3c4c4 + dc.l $c6c44284,$4840d041,$d784d042,$d7844840 + dc.l $42414242,$48414842,$d282d283,$4a056708 + dc.l $46804681,$5280d384,$382efffc,$02040010 + dc.l $4a816a04,$00040008,$44c4c340,$48f60003 + dc.l $01610010,$4cdf003c,$4e5e4e75,$42804281 + dc.l $382efffc,$02040010,$00040004,$44c460da + dc.l $4e56fffc,$48e73800,$42eefffc,$242e0008 + dc.l $10360161,$000c1236,$0162000c,$000149c0 + dc.l $49c16000,$00b84e56,$fffc48e7,$380042ee + dc.l $fffc242e,$00083036,$0161000c,$32360162 + dc.l $000c0002,$48c048c1,$60000092,$4e56fffc + dc.l $48e73800,$42eefffc,$242e0008,$20360161 + dc.l $000c2236,$0162000c,$00046000,$00704e56 + dc.l $fffc48e7,$380042ee,$fffc242e,$00081036 + dc.l $0161000c,$12360162,$000c0001,$49c049c1 + dc.l $49c26000,$00484e56,$fffc48e7,$380042ee + dc.l $fffc242e,$00083036,$0161000c,$32360162 + dc.l $000c0002,$48c048c1,$48c26000,$00204e56 + dc.l $fffc48e7,$380042ee,$fffc242e,$00082036 + dc.l $0161000c,$22360162,$000c0004,$948042c3 + dc.l $02030004,$9280b282,$42c48604,$02030005 + dc.l $382efffc,$0204001a,$880344c4,$4cdf001c + dc.l $4e5e4e75,$00000000,$00000000,$00000000 diff --git a/arch/m68k/ifpsp060/iskeleton.S b/arch/m68k/ifpsp060/iskeleton.S new file mode 100644 index 000000000..91a9c65fe --- /dev/null +++ b/arch/m68k/ifpsp060/iskeleton.S @@ -0,0 +1,347 @@ +|~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +|MOTOROLA MICROPROCESSOR & MEMORY TECHNOLOGY GROUP +|M68000 Hi-Performance Microprocessor Division +|M68060 Software Package +|Production Release P1.00 -- October 10, 1994 +| +|M68060 Software Package Copyright © 1993, 1994 Motorola Inc. All rights reserved. +| +|THE SOFTWARE is provided on an "AS IS" basis and without warranty. +|To the maximum extent permitted by applicable law, +|MOTOROLA DISCLAIMS ALL WARRANTIES WHETHER EXPRESS OR IMPLIED, +|INCLUDING IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE +|and any warranty against infringement with regard to the SOFTWARE +|(INCLUDING ANY MODIFIED VERSIONS THEREOF) and any accompanying written materials. +| +|To the maximum extent permitted by applicable law, +|IN NO EVENT SHALL MOTOROLA BE LIABLE FOR ANY DAMAGES WHATSOEVER +|(INCLUDING WITHOUT LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, +|BUSINESS INTERRUPTION, LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY LOSS) +|ARISING OF THE USE OR INABILITY TO USE THE SOFTWARE. +|Motorola assumes no responsibility for the maintenance and support of the SOFTWARE. +| +|You are hereby granted a copyright license to use, modify, and distribute the SOFTWARE +|so long as this entire notice is retained without alteration in any modified and/or +|redistributed versions, and that such modified versions are clearly identified as such. +|No licenses are granted by implication, estoppel or otherwise under any patents +|or trademarks of Motorola, Inc. +|~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +| iskeleton.s +| +| This file contains: +| (1) example "Call-out"s +| (2) example package entry code +| (3) example "Call-out" table +| + +#include +#include +#include + + +|################################ +| (1) EXAMPLE CALL-OUTS # +| # +| _060_isp_done() # +| _060_real_chk() # +| _060_real_divbyzero() # +| # +| _060_real_cas() # +| _060_real_cas2() # +| _060_real_lock_page() # +| _060_real_unlock_page() # +|################################ + +| +| _060_isp_done(): +| +| This is and example main exit point for the Unimplemented Integer +| Instruction exception handler. For a normal exit, the +| _isp_unimp() branches to here so that the operating system +| can do any clean-up desired. The stack frame is the +| Unimplemented Integer Instruction stack frame with +| the PC pointing to the instruction following the instruction +| just emulated. +| To simply continue execution at the next instruction, just +| do an "rte". +| +| Linux/68k: If returning to user space, check for needed reselections. + + .global _060_isp_done +_060_isp_done: + btst #0x5,%sp@ | supervisor bit set in saved SR? + beq .Lnotkern + rte +.Lnotkern: + SAVE_ALL_INT + GET_CURRENT(%d0) + | deliver signals, reschedule etc.. + jra ret_from_exception + +| +| _060_real_chk(): +| +| This is an alternate exit point for the Unimplemented Integer +| Instruction exception handler. If the instruction was a "chk2" +| and the operand was out of bounds, then _isp_unimp() creates +| a CHK exception stack frame from the Unimplemented Integer Instrcution +| stack frame and branches to this routine. +| +| Linux/68k: commented out test for tracing + + .global _060_real_chk +_060_real_chk: +| tst.b (%sp) | is tracing enabled? +| bpls real_chk_end | no + +| +| CHK FRAME TRACE FRAME +| ***************** ***************** +| * Current PC * * Current PC * +| ***************** ***************** +| * 0x2 * 0x018 * * 0x2 * 0x024 * +| ***************** ***************** +| * Next * * Next * +| * PC * * PC * +| ***************** ***************** +| * SR * * SR * +| ***************** ***************** +| +| move.b #0x24,0x7(%sp) | set trace vecno +| bral _060_real_trace + +real_chk_end: + bral trap | jump to trap handler + +| +| _060_real_divbyzero: +| +| This is an alternate exit point for the Unimplemented Integer +| Instruction exception handler isp_unimp(). If the instruction is a 64-bit +| integer divide where the source operand is a zero, then the _isp_unimp() +| creates a Divide-by-zero exception stack frame from the Unimplemented +| Integer Instruction stack frame and branches to this routine. +| +| Remember that a trace exception may be pending. The code below performs +| no action associated with the "chk" exception. If tracing is enabled, +| then it create a Trace exception stack frame from the "chk" exception +| stack frame and branches to the _real_trace() entry point. +| +| Linux/68k: commented out test for tracing + + .global _060_real_divbyzero +_060_real_divbyzero: +| tst.b (%sp) | is tracing enabled? +| bpls real_divbyzero_end | no + +| +| DIVBYZERO FRAME TRACE FRAME +| ***************** ***************** +| * Current PC * * Current PC * +| ***************** ***************** +| * 0x2 * 0x014 * * 0x2 * 0x024 * +| ***************** ***************** +| * Next * * Next * +| * PC * * PC * +| ***************** ***************** +| * SR * * SR * +| ***************** ***************** +| +| move.b #0x24,0x7(%sp) | set trace vecno +| bral _060_real_trace + +real_divbyzero_end: + bral trap | jump to trap handler + +|########################## + +| +| _060_real_cas(): +| +| Entry point for the selected cas emulation code implementation. +| If the implementation provided by the 68060ISP is sufficient, +| then this routine simply re-enters the package through _isp_cas. +| + .global _060_real_cas +_060_real_cas: + bral _I_CALL_TOP+0x80+0x08 + +| +| _060_real_cas2(): +| +| Entry point for the selected cas2 emulation code implementation. +| If the implementation provided by the 68060ISP is sufficient, +| then this routine simply re-enters the package through _isp_cas2. +| + .global _060_real_cas2 +_060_real_cas2: + bral _I_CALL_TOP+0x80+0x10 + +| +| _060_lock_page(): +| +| Entry point for the operating system`s routine to "lock" a page +| from being paged out. This routine is needed by the cas/cas2 +| algorithms so that no page faults occur within the "core" code +| region. Note: the routine must lock two pages if the operand +| spans two pages. +| NOTE: THE ROUTINE SHOULD RETURN AN FSLW VALUE IN D0 ON FAILURE +| SO THAT THE 060SP CAN CREATE A PROPER ACCESS ERROR FRAME. +| Arguments: +| a0 = operand address +| d0 = `xxxxxxff -> supervisor; `xxxxxx00 -> user +| d1 = `xxxxxxff -> longword; `xxxxxx00 -> word +| Expected outputs: +| d0 = 0 -> success; non-zero -> failure +| +| Linux/m68k: Make sure the page is properly paged in, so we use +| plpaw and handle any exception here. The kernel must not be +| preempted until _060_unlock_page(), so that the page stays mapped. +| + .global _060_real_lock_page +_060_real_lock_page: + move.l %d2,-(%sp) + | load sfc/dfc + tst.b %d0 + jne 1f + moveq #1,%d0 + jra 2f +1: moveq #5,%d0 +2: movec.l %dfc,%d2 + movec.l %d0,%dfc + movec.l %d0,%sfc + + clr.l %d0 + | prefetch address + .chip 68060 + move.l %a0,%a1 +1: plpaw (%a1) + addq.w #1,%a0 + tst.b %d1 + jeq 2f + addq.w #2,%a0 +2: plpaw (%a0) +3: .chip 68k + + | restore sfc/dfc + movec.l %d2,%dfc + movec.l %d2,%sfc + move.l (%sp)+,%d2 + rts + +.section __ex_table,"a" + .align 4 + .long 1b,11f + .long 2b,21f +.previous +.section .fixup,"ax" + .even +11: move.l #0x020003c0,%d0 + or.l %d2,%d0 + swap %d0 + jra 3b +21: move.l #0x02000bc0,%d0 + or.l %d2,%d0 + swap %d0 + jra 3b +.previous + +| +| _060_unlock_page(): +| +| Entry point for the operating system`s routine to "unlock" a +| page that has been "locked" previously with _real_lock_page. +| Note: the routine must unlock two pages if the operand spans +| two pages. +| Arguments: +| a0 = operand address +| d0 = `xxxxxxff -> supervisor; `xxxxxx00 -> user +| d1 = `xxxxxxff -> longword; `xxxxxx00 -> word +| +| Linux/m68k: perhaps reenable preemption here... + + .global _060_real_unlock_page +_060_real_unlock_page: + clr.l %d0 + rts + +|########################################################################### + +|################################# +| (2) EXAMPLE PACKAGE ENTRY CODE # +|################################# + + .global _060_isp_unimp +_060_isp_unimp: + bral _I_CALL_TOP+0x80+0x00 + + .global _060_isp_cas +_060_isp_cas: + bral _I_CALL_TOP+0x80+0x08 + + .global _060_isp_cas2 +_060_isp_cas2: + bral _I_CALL_TOP+0x80+0x10 + + .global _060_isp_cas_finish +_060_isp_cas_finish: + bra.l _I_CALL_TOP+0x80+0x18 + + .global _060_isp_cas2_finish +_060_isp_cas2_finish: + bral _I_CALL_TOP+0x80+0x20 + + .global _060_isp_cas_inrange +_060_isp_cas_inrange: + bral _I_CALL_TOP+0x80+0x28 + + .global _060_isp_cas_terminate +_060_isp_cas_terminate: + bral _I_CALL_TOP+0x80+0x30 + + .global _060_isp_cas_restart +_060_isp_cas_restart: + bral _I_CALL_TOP+0x80+0x38 + +|########################################################################### + +|############################### +| (3) EXAMPLE CALL-OUT SECTION # +|############################### + +| The size of this section MUST be 128 bytes!!! + +_I_CALL_TOP: + .long _060_real_chk - _I_CALL_TOP + .long _060_real_divbyzero - _I_CALL_TOP + .long _060_real_trace - _I_CALL_TOP + .long _060_real_access - _I_CALL_TOP + .long _060_isp_done - _I_CALL_TOP + + .long _060_real_cas - _I_CALL_TOP + .long _060_real_cas2 - _I_CALL_TOP + .long _060_real_lock_page - _I_CALL_TOP + .long _060_real_unlock_page - _I_CALL_TOP + + .long 0x00000000, 0x00000000, 0x00000000, 0x00000000 + .long 0x00000000, 0x00000000, 0x00000000 + + .long _060_imem_read - _I_CALL_TOP + .long _060_dmem_read - _I_CALL_TOP + .long _060_dmem_write - _I_CALL_TOP + .long _060_imem_read_word - _I_CALL_TOP + .long _060_imem_read_long - _I_CALL_TOP + .long _060_dmem_read_byte - _I_CALL_TOP + .long _060_dmem_read_word - _I_CALL_TOP + .long _060_dmem_read_long - _I_CALL_TOP + .long _060_dmem_write_byte - _I_CALL_TOP + .long _060_dmem_write_word - _I_CALL_TOP + .long _060_dmem_write_long - _I_CALL_TOP + + .long 0x00000000 + .long 0x00000000, 0x00000000, 0x00000000, 0x00000000 + +|########################################################################### + +| 060 INTEGER KERNEL PACKAGE MUST GO HERE!!! +#include "isp.sa" diff --git a/arch/m68k/ifpsp060/isp.doc b/arch/m68k/ifpsp060/isp.doc new file mode 100644 index 000000000..9dadd727f --- /dev/null +++ b/arch/m68k/ifpsp060/isp.doc @@ -0,0 +1,218 @@ +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +MOTOROLA MICROPROCESSOR & MEMORY TECHNOLOGY GROUP +M68000 Hi-Performance Microprocessor Division +M68060 Software Package +Production Release P1.00 -- October 10, 1994 + +M68060 Software Package Copyright © 1993, 1994 Motorola Inc. All rights reserved. + +THE SOFTWARE is provided on an "AS IS" basis and without warranty. +To the maximum extent permitted by applicable law, +MOTOROLA DISCLAIMS ALL WARRANTIES WHETHER EXPRESS OR IMPLIED, +INCLUDING IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE +and any warranty against infringement with regard to the SOFTWARE +(INCLUDING ANY MODIFIED VERSIONS THEREOF) and any accompanying written materials. + +To the maximum extent permitted by applicable law, +IN NO EVENT SHALL MOTOROLA BE LIABLE FOR ANY DAMAGES WHATSOEVER +(INCLUDING WITHOUT LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, +BUSINESS INTERRUPTION, LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY LOSS) +ARISING OF THE USE OR INABILITY TO USE THE SOFTWARE. +Motorola assumes no responsibility for the maintenance and support of the SOFTWARE. + +You are hereby granted a copyright license to use, modify, and distribute the SOFTWARE +so long as this entire notice is retained without alteration in any modified and/or +redistributed versions, and that such modified versions are clearly identified as such. +No licenses are granted by implication, estoppel or otherwise under any patents +or trademarks of Motorola, Inc. +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +68060 INTEGER SOFTWARE PACKAGE (Kernel version) +------------------------------------------------ + +The file isp.sa contains the 68060 Integer Software Package. +This package is essentially an exception handler that can be +integrated into an operating system to handle the "Unimplemented +Integer Instruction" exception vector #61. +This exception is taken when any of the integer instructions +not hardware implemented on the 68060 are encountered. The +isp.sa provides full emulation support for these instructions. + +The unimplemented integer instructions are: + 64-bit divide + 64-bit multiply + movep + cmp2 + chk2 + cas (w/ a misaligned effective address) + cas2 + +Release file format: +-------------------- +The file isp.sa is essentially a hexadecimal image of the +release package. This is the ONLY format which will be supported. +The hex image was created by assembling the source code and +then converting the resulting binary output image into an +ASCII text file. The hexadecimal numbers are listed +using the Motorola Assembly Syntax assembler directive "dc.l" +(define constant longword). The file can be converted to other +assembly syntaxes by using any word processor with a global +search and replace function. + +To assist in assembling and linking this module with other modules, +the installer should add a symbolic label to the top of the file. +This will allow calling routines to access the entry points +of this package. + +The source code isp.s has also been included but only for +documentation purposes. + +Release file structure: +----------------------- + +(top of module) + ----------------- + | | - 128 byte-sized section + (1) | Call-Out | - 4 bytes per entry (user fills these in) + | | - example routines in iskeleton.s + ----------------- + | | - 8 bytes per entry + (2) | Entry Point | - user does a "bra" or "jmp" to this address + | | + ----------------- + | | - code section + (3) ~ ~ + | | + ----------------- +(bottom of module) + +The first section of this module is the "Call-out" section. This section +is NOT INCLUDED in isp.sa (an example "Call-out" section is provided at +the end of the file iskeleton.s). The purpose of this section is to allow +the ISP routines to reference external functions that must be provided +by the host operating system. This section MUST be exactly 128 bytes in +size. There are 32 fields, each 4 bytes in size. Each field corresponds +to a function required by the ISP (these functions and their location are +listed in "68060ISP call-outs" below). Each field entry should contain +the address of the corresponding function RELATIVE to the starting address +of the "call-out" section. The "Call-out" section must sit adjacent to the +isp.sa image in memory. + +The second section, the "Entry-point" section, is used by external routines +to access the functions within the ISP. Since the isp.sa hex file contains +no symbol names, this section contains function entry points that are fixed +with respect to the top of the package. The currently defined entry-points +are listed in section "68060 ISP entry points" below. A calling routine +would simply execute a "bra" or "jmp" that jumped to the selected function +entry-point. + +For example, if the 68060 hardware took a "Unimplemented Integer Instruction" +exception (vector #61), the operating system should execute something +similar to: + + bra _060ISP_TOP+128+0 + +(_060ISP_TOP is the starting address of the "Call-out" section; the "Call-out" +section is 128 bytes long; and the Unimplemented Integer ISP handler entry +point is located 0 bytes from the top of the "Entry-point" section.) + +The third section is the code section. After entering through an "Entry-point", +the entry code jumps to the appropriate emulation code within the code section. + +68060ISP call-outs: (details in iskeleton.s) +-------------------- +0x000: _060_real_chk +0x004: _060_real_divbyzero +0x008: _060_real_trace +0x00c: _060_real_access +0x010: _060_isp_done + +0x014: _060_real_cas +0x018: _060_real_cas2 +0x01c: _060_real_lock_page +0x020: _060_real_unlock_page + +0x024: (Motorola reserved) +0x028: (Motorola reserved) +0x02c: (Motorola reserved) +0x030: (Motorola reserved) +0x034: (Motorola reserved) +0x038: (Motorola reserved) +0x03c: (Motorola reserved) + +0x040: _060_imem_read +0x044: _060_dmem_read +0x048: _060_dmem_write +0x04c: _060_imem_read_word +0x050: _060_imem_read_long +0x054: _060_dmem_read_byte +0x058: _060_dmem_read_word +0x05c: _060_dmem_read_long +0x060: _060_dmem_write_byte +0x064: _060_dmem_write_word +0x068: _060_dmem_write_long + +0x06c: (Motorola reserved) +0x070: (Motorola reserved) +0x074: (Motorola reserved) +0x078: (Motorola reserved) +0x07c: (Motorola reserved) + +68060ISP entry points: +----------------------- +0x000: _060_isp_unimp + +0x008: _060_isp_cas +0x010: _060_isp_cas2 +0x018: _060_isp_cas_finish +0x020: _060_isp_cas2_finish +0x028: _060_isp_cas_inrange +0x030: _060_isp_cas_terminate +0x038: _060_isp_cas_restart + +Integrating cas/cas2: +--------------------- +The instructions "cas2" and "cas" (when used with a misaligned effective +address) take the Unimplemented Integer Instruction exception. When the +060ISP is installed properly, these instructions will enter through the +_060_isp_unimp() entry point of the ISP. + +After the 060ISP decodes the instruction type and fetches the appropriate +data registers, and BEFORE the actual emulated transfers occur, the +package calls either the "Call-out" _060_real_cas() or _060_real_cas2(). +If the emulation code provided by the 060ISP is sufficient for the +host system (see isp.s source code), then these "Call-out"s should be +made, by the system integrator, to point directly back into the package +through the "Entry-point"s _060_isp_cas() or _060_isp_cas2(). + +One other necessary action by the integrator is to supply the routines +_060_real_lock_page() and _060_real_unlock_page(). These functions are +defined further in iskeleton.s and the 68060 Software Package Specification. + +If the "core" emulation routines of either "cas" or "cas2" perform some +actions which are too system-specific, then the system integrator must +supply new emulation code. This new emulation code should reside within +the functions _060_real_cas() or _060_real_cas2(). When this new emulation +code has completed, then it should re-enter the 060ISP package through the +"Entry-point" _060_isp_cas_finish() or _060_isp_cas2_finish(). +To see what the register state is upon entering _060_real_cas() or +_060_real_cas2() and what it should be upon return to the package through +_060_isp_cas_finish() or _060_isp_cas2_finish(), please refer to the +source code in isp.s. + +Miscellaneous: +-------------- + +_060_isp_unimp: +---------------- +- documented in 2.2 in spec. +- Basic flow: + exception taken ---> enter _060_isp_unimp --| + | + | + may exit through _060_real_itrace <----| + or | + may exit through _060_real_chk <----| + or | + may exit through _060_real_divbyzero <----| + or | + may exit through _060_isp_done <----| diff --git a/arch/m68k/ifpsp060/isp.sa b/arch/m68k/ifpsp060/isp.sa new file mode 100644 index 000000000..2f88d2a7d --- /dev/null +++ b/arch/m68k/ifpsp060/isp.sa @@ -0,0 +1,392 @@ + .long 0x60ff0000,0x02360000,0x60ff0000,0x16260000 + .long 0x60ff0000,0x12dc0000,0x60ff0000,0x11ea0000 + .long 0x60ff0000,0x10de0000,0x60ff0000,0x12a40000 + .long 0x60ff0000,0x12560000,0x60ff0000,0x122a0000 + .long 0x51fc51fc,0x51fc51fc,0x51fc51fc,0x51fc51fc + .long 0x51fc51fc,0x51fc51fc,0x51fc51fc,0x51fc51fc + .long 0x51fc51fc,0x51fc51fc,0x51fc51fc,0x51fc51fc + .long 0x51fc51fc,0x51fc51fc,0x51fc51fc,0x51fc51fc + .long 0x2f00203a,0xfefc487b,0x0930ffff,0xfef8202f + .long 0x00044e74,0x00042f00,0x203afeea,0x487b0930 + .long 0xfffffee2,0x202f0004,0x4e740004,0x2f00203a + .long 0xfed8487b,0x0930ffff,0xfecc202f,0x00044e74 + .long 0x00042f00,0x203afec6,0x487b0930,0xfffffeb6 + .long 0x202f0004,0x4e740004,0x2f00203a,0xfeb4487b + .long 0x0930ffff,0xfea0202f,0x00044e74,0x00042f00 + .long 0x203afea2,0x487b0930,0xfffffe8a,0x202f0004 + .long 0x4e740004,0x2f00203a,0xfe90487b,0x0930ffff + .long 0xfe74202f,0x00044e74,0x00042f00,0x203afe7e + .long 0x487b0930,0xfffffe5e,0x202f0004,0x4e740004 + .long 0x2f00203a,0xfe6c487b,0x0930ffff,0xfe48202f + .long 0x00044e74,0x00042f00,0x203afe76,0x487b0930 + .long 0xfffffe32,0x202f0004,0x4e740004,0x2f00203a + .long 0xfe64487b,0x0930ffff,0xfe1c202f,0x00044e74 + .long 0x00042f00,0x203afe52,0x487b0930,0xfffffe06 + .long 0x202f0004,0x4e740004,0x2f00203a,0xfe40487b + .long 0x0930ffff,0xfdf0202f,0x00044e74,0x00042f00 + .long 0x203afe2e,0x487b0930,0xfffffdda,0x202f0004 + .long 0x4e740004,0x2f00203a,0xfe1c487b,0x0930ffff + .long 0xfdc4202f,0x00044e74,0x00042f00,0x203afe0a + .long 0x487b0930,0xfffffdae,0x202f0004,0x4e740004 + .long 0x2f00203a,0xfdf8487b,0x0930ffff,0xfd98202f + .long 0x00044e74,0x00042f00,0x203afde6,0x487b0930 + .long 0xfffffd82,0x202f0004,0x4e740004,0x2f00203a + .long 0xfdd4487b,0x0930ffff,0xfd6c202f,0x00044e74 + .long 0x00042f00,0x203afdc2,0x487b0930,0xfffffd56 + .long 0x202f0004,0x4e740004,0x4e56ffa0,0x48ee3fff + .long 0xffc02d56,0xfff8082e,0x00050004,0x66084e68 + .long 0x2d48fffc,0x600841ee,0x000c2d48,0xfffc422e + .long 0xffaa3d6e,0x0004ffa8,0x2d6e0006,0xffa4206e + .long 0xffa458ae,0xffa461ff,0xffffff26,0x2d40ffa0 + .long 0x0800001e,0x67680800,0x00166628,0x61ff0000 + .long 0x0cb0082e,0x00050004,0x670000ac,0x082e0002 + .long 0xffaa6700,0x00a2082e,0x00070004,0x66000186 + .long 0x600001b0,0x61ff0000,0x0a28082e,0x0002ffaa + .long 0x660e082e,0x0005ffaa,0x6600010a,0x60000078 + .long 0x082e0005,0x000467ea,0x082e0005,0xffaa6600 + .long 0x01264a2e,0x00046b00,0x014c6000,0x01760800 + .long 0x0018670a,0x61ff0000,0x07ae6000,0x004a0800 + .long 0x001b6730,0x48400c00,0x00fc670a,0x61ff0000 + .long 0x0e926000,0x0032206e,0xffa454ae,0xffa461ff + .long 0xfffffe68,0x4a816600,0x019861ff,0x00000d20 + .long 0x60000014,0x61ff0000,0x08c40c2e,0x0010ffaa + .long 0x66000004,0x605c1d6e,0xffa90005,0x082e0005 + .long 0x00046606,0x206efffc,0x4e604cee,0x3fffffc0 + .long 0x082e0007,0x00046612,0x2d6effa4,0x00062cae + .long 0xfff84e5e,0x60ffffff,0xfd622d6e,0xfff8fffc + .long 0x3d6e0004,0x00002d6e,0x00060008,0x2d6effa4 + .long 0x00023d7c,0x20240006,0x598e4e5e,0x60ffffff + .long 0xfd0e1d6e,0xffa90005,0x4cee3fff,0xffc03cae + .long 0x00042d6e,0x00060008,0x2d6effa4,0x00023d7c + .long 0x20180006,0x2c6efff8,0xdffc0000,0x006060ff + .long 0xfffffcb0,0x1d6effa9,0x00054cee,0x3fffffc0 + .long 0x3cae0004,0x2d6e0006,0x00082d6e,0xffa40002 + .long 0x3d7c2014,0x00062c6e,0xfff8dffc,0x00000060 + .long 0x60ffffff,0xfc941d6e,0xffa90005,0x4cee3fff + .long 0xffc02d6e,0x0006000c,0x3d7c2014,0x000a2d6e + .long 0xffa40006,0x2c6efff8,0xdffc0000,0x006460ff + .long 0xfffffc66,0x1d6effa9,0x00054cee,0x3fffffc0 + .long 0x2d6e0006,0x000c3d7c,0x2024000a,0x2d6effa4 + .long 0x00062c6e,0xfff8dffc,0x00000064,0x60ffffff + .long 0xfc4e1d6e,0xffa90005,0x4cee3fff,0xffc03d7c + .long 0x00f4000e,0x2d6effa4,0x000a3d6e,0x00040008 + .long 0x2c6efff8,0xdffc0000,0x006860ff,0xfffffc4c + .long 0x2c882d40,0xfffc4fee,0xffc04cdf,0x7fff2f2f + .long 0x000c2f6f,0x00040010,0x2f6f000c,0x00042f6f + .long 0x0008000c,0x2f5f0004,0x3f7c4008,0x00066028 + .long 0x4cee3fff,0xffc04e5e,0x514f2eaf,0x00083f6f + .long 0x000c0004,0x3f7c4008,0x00062f6f,0x00020008 + .long 0x2f7c0942,0x8001000c,0x08170005,0x670608ef + .long 0x0002000d,0x60ffffff,0xfbcc0c2e,0x0040ffaa + .long 0x660c4280,0x102effab,0x2daeffac,0x0ce04e75 + .long 0x2040302e,0xffa03200,0x0240003f,0x02810000 + .long 0x0007303b,0x020a4efb,0x00064afc,0x00400000 + .long 0x00000000,0x00000000,0x00000000,0x00000000 + .long 0x00000000,0x00000000,0x00000000,0x00000080 + .long 0x0086008c,0x00920098,0x009e00a4,0x00aa00b0 + .long 0x00ce00ec,0x010a0128,0x01460164,0x01820196 + .long 0x01b401d2,0x01f0020e,0x022c024a,0x0268027c + .long 0x029a02b8,0x02d602f4,0x03120330,0x034e036c + .long 0x036c036c,0x036c036c,0x036c036c,0x036c03d6 + .long 0x03f0040a,0x042a03ca,0x00000000,0x0000206e + .long 0xffe04e75,0x206effe4,0x4e75206e,0xffe84e75 + .long 0x206effec,0x4e75206e,0xfff04e75,0x206efff4 + .long 0x4e75206e,0xfff84e75,0x206efffc,0x4e752008 + .long 0x206effe0,0xd0882d40,0xffe02d48,0xffac1d7c + .long 0x0000ffab,0x1d7c0040,0xffaa4e75,0x2008206e + .long 0xffe4d088,0x2d40ffe4,0x2d48ffac,0x1d7c0001 + .long 0xffab1d7c,0x0040ffaa,0x4e752008,0x206effe8 + .long 0xd0882d40,0xffe82d48,0xffac1d7c,0x0002ffab + .long 0x1d7c0040,0xffaa4e75,0x2008206e,0xffecd088 + .long 0x2d40ffec,0x2d48ffac,0x1d7c0003,0xffab1d7c + .long 0x0040ffaa,0x4e752008,0x206efff0,0xd0882d40 + .long 0xfff02d48,0xffac1d7c,0x0004ffab,0x1d7c0040 + .long 0xffaa4e75,0x2008206e,0xfff4d088,0x2d40fff4 + .long 0x2d48ffac,0x1d7c0005,0xffab1d7c,0x0040ffaa + .long 0x4e752008,0x206efff8,0xd0882d40,0xfff82d48 + .long 0xffac1d7c,0x0006ffab,0x1d7c0040,0xffaa4e75 + .long 0x1d7c0004,0xffaa2008,0x206efffc,0xd0882d40 + .long 0xfffc4e75,0x202effe0,0x2d40ffac,0x90882d40 + .long 0xffe02040,0x1d7c0000,0xffab1d7c,0x0040ffaa + .long 0x4e75202e,0xffe42d40,0xffac9088,0x2d40ffe4 + .long 0x20401d7c,0x0001ffab,0x1d7c0040,0xffaa4e75 + .long 0x202effe8,0x2d40ffac,0x90882d40,0xffe82040 + .long 0x1d7c0002,0xffab1d7c,0x0040ffaa,0x4e75202e + .long 0xffec2d40,0xffac9088,0x2d40ffec,0x20401d7c + .long 0x0003ffab,0x1d7c0040,0xffaa4e75,0x202efff0 + .long 0x2d40ffac,0x90882d40,0xfff02040,0x1d7c0004 + .long 0xffab1d7c,0x0040ffaa,0x4e75202e,0xfff42d40 + .long 0xffac9088,0x2d40fff4,0x20401d7c,0x0005ffab + .long 0x1d7c0040,0xffaa4e75,0x202efff8,0x2d40ffac + .long 0x90882d40,0xfff82040,0x1d7c0006,0xffab1d7c + .long 0x0040ffaa,0x4e751d7c,0x0008ffaa,0x202efffc + .long 0x90882d40,0xfffc2040,0x4e75206e,0xffa454ae + .long 0xffa461ff,0xfffff9d4,0x4a8166ff,0xfffffd04 + .long 0x3040d1ee,0xffe04e75,0x206effa4,0x54aeffa4 + .long 0x61ffffff,0xf9b64a81,0x66ffffff,0xfce63040 + .long 0xd1eeffe4,0x4e75206e,0xffa454ae,0xffa461ff + .long 0xfffff998,0x4a8166ff,0xfffffcc8,0x3040d1ee + .long 0xffe84e75,0x206effa4,0x54aeffa4,0x61ffffff + .long 0xf97a4a81,0x66ffffff,0xfcaa3040,0xd1eeffec + .long 0x4e75206e,0xffa454ae,0xffa461ff,0xfffff95c + .long 0x4a8166ff,0xfffffc8c,0x3040d1ee,0xfff04e75 + .long 0x206effa4,0x54aeffa4,0x61ffffff,0xf93e4a81 + .long 0x66ffffff,0xfc6e3040,0xd1eefff4,0x4e75206e + .long 0xffa454ae,0xffa461ff,0xfffff920,0x4a8166ff + .long 0xfffffc50,0x3040d1ee,0xfff84e75,0x206effa4 + .long 0x54aeffa4,0x61ffffff,0xf9024a81,0x66ffffff + .long 0xfc323040,0xd1eefffc,0x4e752f01,0x206effa4 + .long 0x54aeffa4,0x61ffffff,0xf8e24a81,0x66ffffff + .long 0xfc12221f,0x207614e0,0x08000008,0x670e48e7 + .long 0x3c002a00,0x260860ff,0x000000ec,0x2f022200 + .long 0xe9590241,0x000f2236,0x14c00800,0x000b6602 + .long 0x48c12400,0xef5a0282,0x00000003,0xe5a949c0 + .long 0xd081d1c0,0x241f4e75,0x1d7c0080,0xffaa206e + .long 0xffa44e75,0x206effa4,0x54aeffa4,0x61ffffff + .long 0xf87a4a81,0x66ffffff,0xfbaa3040,0x4e75206e + .long 0xffa458ae,0xffa461ff,0xfffff876,0x4a8166ff + .long 0xfffffb90,0x20404e75,0x206effa4,0x54aeffa4 + .long 0x61ffffff,0xf8464a81,0x66ffffff,0xfb763040 + .long 0xd1eeffa4,0x55884e75,0x206effa4,0x54aeffa4 + .long 0x61ffffff,0xf8264a81,0x66ffffff,0xfb56206e + .long 0xffa45588,0x08000008,0x670e48e7,0x3c002a00 + .long 0x260860ff,0x00000030,0x2f022200,0xe9590241 + .long 0x000f2236,0x14c00800,0x000b6602,0x48c12400 + .long 0xef5a0282,0x00000003,0xe5a949c0,0xd081d1c0 + .long 0x241f4e75,0x08050006,0x67044282,0x6016e9c5 + .long 0x24042436,0x24c00805,0x000b6602,0x48c2e9c5 + .long 0x0542e1aa,0x08050007,0x67024283,0xe9c50682 + .long 0x0c000002,0x6d346718,0x206effa4,0x58aeffa4 + .long 0x61ffffff,0xf7ac4a81,0x66ffffff,0xfac66018 + .long 0x206effa4,0x54aeffa4,0x61ffffff,0xf77e4a81 + .long 0x66ffffff,0xfaae48c0,0xd680e9c5,0x07826700 + .long 0x006a0c00,0x00026d34,0x6718206e,0xffa458ae + .long 0xffa461ff,0xfffff76a,0x4a8166ff,0xfffffa84 + .long 0x601c206e,0xffa454ae,0xffa461ff,0xfffff73c + .long 0x4a8166ff,0xfffffa6c,0x48c06002,0x42802800 + .long 0x08050002,0x67122043,0x61ffffff,0xf7764a81 + .long 0x6624d082,0xd0846016,0xd6822043,0x61ffffff + .long 0xf7624a81,0x6610d084,0x6004d682,0x20032040 + .long 0x4cdf003c,0x4e752043,0x203c0101,0x000160ff + .long 0xfffff9f0,0x322effa0,0x10010240,0x00072076 + .long 0x04e0d0ee,0xffa20801,0x00076700,0x008c3001 + .long 0xef580240,0x00072036,0x04c00801,0x00066752 + .long 0x24002448,0xe19a2002,0x61ffffff,0xf71c4a81 + .long 0x660000fc,0x544a204a,0xe19a2002,0x61ffffff + .long 0xf7084a81,0x660000e8,0x544a204a,0xe19a2002 + .long 0x61ffffff,0xf6f44a81,0x660000d4,0x544a204a + .long 0xe19a2002,0x61ffffff,0xf6e04a81,0x660000c0 + .long 0x4e752400,0x2448e048,0x61ffffff,0xf6cc4a81 + .long 0x660000ac,0x544a204a,0x200261ff,0xfffff6ba + .long 0x4a816600,0x009a4e75,0x08010006,0x675c2448 + .long 0x61ffffff,0xf6624a81,0x66000092,0x2400544a + .long 0x204a61ff,0xfffff650,0x4a816600,0x0080e14a + .long 0x1400544a,0x204a61ff,0xfffff63c,0x4a816600 + .long 0x006ce18a,0x1400544a,0x204a61ff,0xfffff628 + .long 0x4a816600,0x0058e18a,0x1400122e,0xffa0e209 + .long 0x02410007,0x2d8214c0,0x4e752448,0x61ffffff + .long 0xf6064a81,0x66000036,0x2400544a,0x204a61ff + .long 0xfffff5f4,0x4a816600,0x0024e14a,0x1400122e + .long 0xffa0e209,0x02410007,0x3d8214c2,0x4e75204a + .long 0x203c00a1,0x000160ff,0xfffff8a8,0x204a203c + .long 0x01210001,0x60ffffff,0xf89a61ff,0xfffff914 + .long 0x102effa2,0xe9180240,0x000f2436,0x04c00c2e + .long 0x0002ffa0,0x6d506728,0x244861ff,0xfffff5c4 + .long 0x4a816600,0x009e2600,0x588a204a,0x61ffffff + .long 0xf5b24a81,0x6600008c,0x22002003,0x60000048 + .long 0x244861ff,0xfffff59c,0x4a816600,0x00763200 + .long 0x484048c0,0x48c1082e,0x0007ffa2,0x66000028 + .long 0x48c26000,0x00222448,0x61ffffff,0xf5604a81 + .long 0x6600005e,0x1200e048,0x49c049c1,0x082e0007 + .long 0xffa26602,0x49c29480,0x42c30203,0x00049280 + .long 0xb28242c4,0x86040203,0x0005382e,0xffa80204 + .long 0x001a8803,0x3d44ffa8,0x082e0003,0xffa26602 + .long 0x4e750804,0x00006602,0x4e751d7c,0x0010ffaa + .long 0x4e75204a,0x203c0101,0x000160ff,0xfffff7c4 + .long 0x204a203c,0x01410001,0x60ffffff,0xf7b6102e + .long 0xffa10200,0x00386600,0x0208102e,0xffa10240 + .long 0x00072e36,0x04c06700,0x00c0102e,0xffa3122e + .long 0xffa20240,0x0007e809,0x02410007,0x3d40ffb2 + .long 0x3d41ffb4,0x2a3604c0,0x2c3614c0,0x082e0003 + .long 0xffa2671a,0x4a875dee,0xffb06a02,0x44874a85 + .long 0x5deeffb1,0x6a0844fc,0x00004086,0x40854a85 + .long 0x66164a86,0x67000048,0xbe866306,0xcb466000 + .long 0x00124c47,0x6005600a,0xbe85634e,0x61ff0000 + .long 0x0068082e,0x0003ffa2,0x67244a2e,0xffb16702 + .long 0x4485102e,0xffb0b12e,0xffb1670c,0x0c868000 + .long 0x00006226,0x44866006,0x0806001f,0x661c44ee + .long 0xffa84a86,0x42eeffa8,0x302effb2,0x322effb4 + .long 0x2d8504c0,0x2d8614c0,0x4e7508ee,0x0001ffa9 + .long 0x08ae0000,0xffa94e75,0x022e001e,0xffa9002e + .long 0x0020ffaa,0x4e750c87,0x0000ffff,0x621e4281 + .long 0x48454846,0x3a068ac7,0x32054846,0x3a068ac7 + .long 0x48413205,0x42454845,0x2c014e75,0x42aeffbc + .long 0x422effb6,0x42810807,0x001f660e,0x52aeffbc + .long 0xe38fe38e,0xe3956000,0xffee2607,0x24054842 + .long 0x4843b443,0x6606323c,0xffff600a,0x220582c3 + .long 0x02810000,0xffff2f06,0x42464846,0x26072401 + .long 0xc4c74843,0xc6c12805,0x98834844,0x30043806 + .long 0x4a406600,0x000ab484,0x63045381,0x60de2f05 + .long 0x2c014846,0x2a0761ff,0x0000006a,0x24052606 + .long 0x2a1f2c1f,0x9c839b82,0x64ff0000,0x001a5381 + .long 0x42822607,0x48434243,0xdc83db82,0x26074243 + .long 0x4843da83,0x4a2effb6,0x66163d41,0xffb84281 + .long 0x48454846,0x3a064246,0x50eeffb6,0x6000ff6c + .long 0x3d41ffba,0x3c054846,0x48452e2e,0xffbc670a + .long 0x5387e28d,0xe29651cf,0xfffa2a06,0x2c2effb8 + .long 0x4e752406,0x26062805,0x48434844,0xccc5cac3 + .long 0xc4c4c6c4,0x42844846,0xdc45d744,0xdc42d744 + .long 0x48464245,0x42424845,0x4842da82,0xda834e75 + .long 0x700461ff,0xfffff61c,0x0c2e0080,0xffaa6712 + .long 0x244861ff,0xfffff2dc,0x4a81661e,0x2e006000 + .long 0xfde658ae,0xffa461ff,0xfffff286,0x4a8166ff + .long 0xfffff5a0,0x2e006000,0xfdce61ff,0xfffff5ce + .long 0x204a203c,0x01010001,0x60ffffff,0xf556102e + .long 0xffa10c00,0x00076e00,0x00b40240,0x00072636 + .long 0x04c0342e,0xffa24241,0x1202e95a,0x02420007 + .long 0x283624c0,0x4a846700,0x00884a83,0x67000082 + .long 0x422effb0,0x082e0003,0xffa26718,0x4a836c08 + .long 0x4483002e,0x0001ffb0,0x4a846c08,0x44840a2e + .long 0x0001ffb0,0x2a032c03,0x2e044846,0x4847c6c4 + .long 0xc8c6cac7,0xccc74287,0x4843d644,0xdd87d645 + .long 0xdd874843,0x42444245,0x48444845,0xd885d886 + .long 0x4a2effb0,0x67084683,0x46845283,0xd9872d83 + .long 0x24c044fc,0x00002d84,0x14c042c7,0x02070008 + .long 0x1c2effa9,0x02060010,0x8c071d46,0xffa94e75 + .long 0x42b624c0,0x42b614c0,0x7e0460e4,0x700461ff + .long 0xfffff510,0x0c2e0080,0xffaa6714,0x244861ff + .long 0xfffff1d0,0x4a816600,0x00202600,0x6000ff34 + .long 0x58aeffa4,0x61ffffff,0xf1784a81,0x66ffffff + .long 0xf4922600,0x6000ff1c,0x61ffffff,0xf4c0204a + .long 0x203c0101,0x000160ff,0xfffff448,0x2d40ffb4 + .long 0x2200e958,0x0240000f,0x227604c0,0x2d49ffb0 + .long 0x2001ec49,0x02410007,0x2a3614c0,0x02400007 + .long 0x263604c0,0x3d40ffba,0x302effa2,0x2200e958 + .long 0x0240000f,0x207604c0,0x2d48ffbc,0x2001ec49 + .long 0x02410007,0x283614c0,0x02400007,0x243604c0 + .long 0x3d40ffb8,0x082e0001,0xffa056c7,0x082e0005 + .long 0x000456c6,0x24482649,0x22072006,0x61ffffff + .long 0xf05c204a,0x4a8066ff,0x000001c8,0x22072006 + .long 0x204b61ff,0xfffff046,0x204b4a80,0x660a204a + .long 0x224b60ff,0xfffff020,0x2f002207,0x2006204a + .long 0x61ffffff,0xf03e201f,0x204b60ff,0x00000194 + .long 0x082e0001,0xffa06648,0x44eeffa8,0xb0426602 + .long 0xb24342ee,0xffa84a04,0x6610362e,0xffba3d81 + .long 0x34c2342e,0xffb83d80,0x24c2082e,0x00050004 + .long 0x56c22002,0x51c1206e,0xffbc61ff,0xffffeff4 + .long 0x200251c1,0x206effb0,0x61ffffff,0xefe64e75 + .long 0x44eeffa8,0xb0826602,0xb28342ee,0xffa84a04 + .long 0x6610362e,0xffba2d81,0x34c0342e,0xffb82d80 + .long 0x24c0082e,0x00050004,0x56c22002,0x50c1206e + .long 0xffbc61ff,0xffffefac,0x200250c1,0x206effb0 + .long 0x61ffffff,0xef9e4e75,0x202effb4,0x6000feae + .long 0x082e0001,0xffa06610,0x700261ff,0xfffff364 + .long 0x2d48ffb4,0x51c7600e,0x700461ff,0xfffff354 + .long 0x2d48ffb4,0x50c7302e,0xffa22200,0xec480240 + .long 0x00072436,0x04c00241,0x00072836,0x14c03d41 + .long 0xffb8082e,0x00050004,0x56c62448,0x22072006 + .long 0x61ffffff,0xef284a80,0x66000096,0x204a60ff + .long 0xffffeeee,0x082e0001,0xffa0662c,0x44eeffa8 + .long 0xb04442ee,0xffa84a01,0x6608362e,0xffb83d80 + .long 0x34c2206e,0xffb451c1,0x082e0005,0x000456c0 + .long 0x61ffffff,0xeefe4e75,0x44eeffa8,0xb08442ee + .long 0xffa84a01,0x6608362e,0xffb82d80,0x34c0206e + .long 0xffb450c1,0x082e0005,0x000456c0,0x61ffffff + .long 0xeed24e75,0x4e7b6000,0x4e7b6001,0x0c2e00fc + .long 0xffa167ff,0xffffff24,0x206effb4,0x082e0001 + .long 0xffa056c7,0x6000ff40,0x4e7b6000,0x4e7b6001 + .long 0x24482f00,0x61ffffff,0xf264201f,0x588f518f + .long 0x518e721a,0x41ef0008,0x43ef0000,0x22d851c9 + .long 0xfffc3d7c,0x4008000a,0x2d4a000c,0x2d400010 + .long 0x4cee3fff,0xffc04e5e,0x60ffffff,0xedf84280 + .long 0x43fb0170,0x000005ae,0xb3c86d0e,0x43fb0170 + .long 0x00000010,0xb1c96d02,0x4e7570ff,0x4e754a06 + .long 0x66047001,0x60027005,0x4a076700,0x01e42448 + .long 0x26492848,0x2a49568c,0x568d220a,0x40c7007c + .long 0x07004e7a,0x60004e7b,0x00004e7b,0x0001f58a + .long 0xf58cf58b,0xf58df46a,0xf46cf46b,0xf46d2441 + .long 0x56812841,0xf5caf5cc,0x247c8000,0x0000267c + .long 0xa0000000,0x287c0000,0x00002008,0x02000003 + .long 0x671c0c00,0x00026700,0x00966000,0x010251fc + .long 0x4e7ba008,0x0e911000,0x0e900000,0x6002600e + .long 0xb082661c,0xb2836618,0x0e915800,0x6002600e + .long 0x4e7bb008,0x0e904800,0x4e7bc008,0x6034600e + .long 0x4e7bb008,0x0e900800,0x4e7bc008,0x6012600e + .long 0x4e714e71,0x4e714e71,0x4e714e71,0x4e7160b0 + .long 0x4e7b6000,0x4e7b6001,0x46c751c4,0x60ffffff + .long 0xfd424e7b,0x60004e7b,0x600146c7,0x50c460ff + .long 0xfffffd30,0x51fc51fc,0x51fc51fc,0x51fc51fc + .long 0x4e7ba008,0x0e911000,0x0e900000,0x6002600e + .long 0xb082662c,0xb2836628,0x0e915800,0x6002600e + .long 0x48440e58,0x48004e7b,0xb0084844,0x6002600e + .long 0x0e504800,0x4e7bc008,0x6000ffa8,0x4e71600e + .long 0x48400e58,0x08004e7b,0xb0084840,0x6002600e + .long 0x0e500800,0x4e7bc008,0x6000ff76,0x4e71600e + .long 0x4e714e71,0x4e714e71,0x4e714e71,0x4e716090 + .long 0x4e7ba008,0x0e911000,0x0e900000,0x6002600e + .long 0xb082663c,0xb2836638,0x0e915800,0x6002600e + .long 0xe19c0e18,0x48004844,0x0e584800,0x6002600e + .long 0xe19c4e7b,0xb0080e10,0x48006004,0x4e71600e + .long 0x4e7bc008,0x6000ff2c,0x4e714e71,0x4e71600e + .long 0xe1980e18,0x08004840,0x0e580800,0x6002600e + .long 0xe1984e7b,0xb0080e10,0x08006004,0x4e71600e + .long 0x4e7bc008,0x6000feea,0x4e714e71,0x4e71600c + .long 0x4e714e71,0x4e714e71,0x4e714e71,0x6000ff72 + .long 0x24482649,0x28482a49,0x528c528d,0x220a40c7 + .long 0x007c0700,0x4e7a6000,0x4e7b0000,0x4e7b0001 + .long 0xf58af58c,0xf58bf58d,0xf46af46c,0xf46bf46d + .long 0x24415681,0x2841f5ca,0xf5cc247c,0x80000000 + .long 0x267ca000,0x0000287c,0x00000000,0x20080800 + .long 0x00006600,0x009a6016,0x51fc51fc,0x51fc51fc + .long 0x4e7ba008,0x0e511000,0x0e500000,0x6002600e + .long 0xb042661c,0xb2436618,0x0e515800,0x6002600e + .long 0x4e7bb008,0x0e504800,0x4e7bc008,0x6034600e + .long 0x4e7bb008,0x0e500800,0x4e7bc008,0x6012600e + .long 0x4e714e71,0x4e714e71,0x4e714e71,0x4e7160b0 + .long 0x4e7b6000,0x4e7b6001,0x46c751c4,0x60ffffff + .long 0xfb624e7b,0x60004e7b,0x600146c7,0x50c460ff + .long 0xfffffb50,0x51fc51fc,0x51fc51fc,0x51fc51fc + .long 0x4e7ba008,0x0e511000,0x0e500000,0x6002600e + .long 0xb042662c,0xb2436628,0x0e515800,0x6002600e + .long 0xe09c0e18,0x48004e7b,0xb008e19c,0x6002600e + .long 0x0e104800,0x4e7bc008,0x6000ffa8,0x4e71600e + .long 0xe0980e18,0x08004e7b,0xb008e198,0x6002600e + .long 0x0e100800,0x4e7bc008,0x6000ff76,0x4e71600e + .long 0x4e714e71,0x4e714e71,0x4e714e71,0x4e716090 + .long 0x4a066604,0x70016002,0x70054a07,0x660000c6 + .long 0x22482448,0x528a2602,0xe04a40c7,0x007c0700 + .long 0x4e7a6000,0x4e7b0000,0x4e7b0001,0xf589f58a + .long 0xf469f46a,0x227c8000,0x0000247c,0xa0000000 + .long 0x267c0000,0x00006016,0x51fc51fc,0x51fc51fc + .long 0x4e7b9008,0x0e500000,0xb0446624,0x6002600e + .long 0x0e182800,0x4e7ba008,0x0e103800,0x6002600e + .long 0x4e7bb008,0x604c4e71,0x4e714e71,0x4e71600e + .long 0xe0980e18,0x08004e7b,0xa008e198,0x6002600e + .long 0x0e100800,0x4e7bb008,0x60164e71,0x4e71600e + .long 0x4e714e71,0x4e714e71,0x4e714e71,0x4e7160a0 + .long 0x4e7b6000,0x4e7b6001,0x46c751c1,0x60ffffff + .long 0xfb164e7b,0x60004e7b,0x600146c7,0x50c160ff + .long 0xfffffb04,0x22482448,0x568a2208,0x08010000 + .long 0x660000c2,0x26024842,0x40c7007c,0x07004e7a + .long 0x60004e7b,0x00004e7b,0x0001f589,0xf58af469 + .long 0xf46a227c,0x80000000,0x247ca000,0x0000267c + .long 0x00000000,0x601851fc,0x51fc51fc,0x51fc51fc + .long 0x4e7b9008,0x0e900000,0xb0846624,0x6002600e + .long 0x0e582800,0x4e7ba008,0x0e503800,0x6002600e + .long 0x4e7bb008,0x604c4e71,0x4e714e71,0x4e71600e + .long 0x48400e58,0x08004840,0x4e7ba008,0x6002600e + .long 0x0e500800,0x4e7bb008,0x60164e71,0x4e71600e + .long 0x4e714e71,0x4e714e71,0x4e714e71,0x4e7160a0 + .long 0x4e7b6000,0x4e7b6001,0x46c751c1,0x60ffffff + .long 0xfa464e7b,0x60004e7b,0x600146c7,0x50c160ff + .long 0xfffffa34,0x2a02e08a,0x26024842,0x40c7007c + .long 0x07004e7a,0x60004e7b,0x00004e7b,0x0001f589 + .long 0xf58af469,0xf46a227c,0x80000000,0x247ca000 + .long 0x0000267c,0x00000000,0x601451fc,0x51fc51fc + .long 0x4e7b9008,0x0e900000,0xb0846624,0x6002600e + .long 0x0e182800,0x0e583800,0x4e7ba008,0x6002600e + .long 0x0e105800,0x4e7bb008,0x6000ff88,0x4e71600e + .long 0xe1980e18,0x08004840,0x0e580800,0x6002600e + .long 0xe1984e7b,0xa0080e10,0x08006004,0x4e71600e + .long 0x4e7bb008,0x6000ff4a,0x4e714e71,0x4e71600e + .long 0x4e714e71,0x4e714e71,0x4e714e71,0x4e716090 diff --git a/arch/m68k/ifpsp060/itest.sa b/arch/m68k/ifpsp060/itest.sa new file mode 100644 index 000000000..7b15eaf63 --- /dev/null +++ b/arch/m68k/ifpsp060/itest.sa @@ -0,0 +1,1281 @@ + dc.l $60ff0000,$005c5465,$7374696e,$67203638 + dc.l $30363020,$49535020,$73746172,$7465643a + dc.l $0a007061,$73736564,$0a002066,$61696c65 + dc.l $640a0000,$4a80660e,$487affe8,$61ff0000 + dc.l $4f9a588f,$4e752f01,$61ff0000,$4fa4588f + dc.l $487affd8,$61ff0000,$4f82588f,$4e754e56 + dc.l $ff6048e7,$3f3c487a,$ff9e61ff,$00004f6c + dc.l $588f42ae,$ff78487b,$01700000,$00ea61ff + dc.l $00004f58,$588f61ff,$000000f0,$61ffffff + dc.l $ffa642ae,$ff78487b,$01700000,$0af661ff + dc.l $00004f38,$588f61ff,$00000af8,$61ffffff + dc.l $ff8642ae,$ff78487b,$01700000,$179c61ff + dc.l $00004f18,$588f61ff,$0000179c,$61ffffff + dc.l $ff6642ae,$ff78487b,$01700000,$038661ff + dc.l $00004ef8,$588f61ff,$00000380,$61ffffff + dc.l $ff4642ae,$ff78487b,$01700000,$202c61ff + dc.l $00004ed8,$588f2d7c,$00000002,$ff7461ff + dc.l $0000202c,$61ffffff,$ff1e42ae,$ff78487b + dc.l $01700000,$0d7c61ff,$00004eb0,$588f61ff + dc.l $00000d74,$61ffffff,$fefe42ae,$ff78487b + dc.l $01700000,$0f8e61ff,$00004e90,$588f61ff + dc.l $00000f88,$61ffffff,$fede4cdf,$3cfc4e5e + dc.l $4e750936,$342d6269,$74206d75,$6c746970 + dc.l $6c792e2e,$2e0051fc,$52aeff78,$4cfb3fff + dc.l $01700000,$4e184281,$243c9999,$9999263c + dc.l $88888888,$3d7c0004,$ff7c44fc,$000048ee + dc.l $7fffff80,$4c013402,$42eeff7e,$48ee7fff + dc.l $ffc042ae,$ff8842ae,$ff8c61ff,$00004da6 + dc.l $4a0066ff,$00004dcc,$52aeff78,$4cfb3fff + dc.l $01700000,$4dc8223c,$77777777,$243c9999 + dc.l $99997600,$3d7c0004,$ff7c44fc,$000048ee + dc.l $7fffff80,$4c013402,$42eeff7e,$48ee7fff + dc.l $ffc042ae,$ff8842ae,$ff8c61ff,$00004d56 + dc.l $4a0066ff,$00004d7c,$52aeff78,$4cfb3fff + dc.l $01700000,$4d787210,$243c6666,$66663d7c + dc.l $0000ff7c,$44fc0000,$48ee7fff,$ff804c01 + dc.l $240242ee,$ff7e48ee,$7fffffc0,$2d7c0000 + dc.l $0006ff88,$61ff0000,$4d0c4a00,$66ff0000 + dc.l $4d3252ae,$ff784cfb,$3fff0170,$00004d2e + dc.l $223c5555,$55557400,$76033d7c,$0000ff7c + dc.l $44fc0000,$48ee7fff,$ff804c01,$340242ee + dc.l $ff7e48ee,$7fffffc0,$2d7c0000,$0000ff88 + dc.l $2d7cffff,$ffffff8c,$61ff0000,$4cb84a00 + dc.l $66ff0000,$4cde52ae,$ff784cfb,$3fff0170 + dc.l $00004cda,$223c4000,$00007400,$76043d7c + dc.l $0000ff7c,$44fc0000,$48ee7fff,$ff804c01 + dc.l $340242ee,$ff7e48ee,$7fffffc0,$2d7c0000 + dc.l $0001ff88,$2d7c0000,$0000ff8c,$61ff0000 + dc.l $4c644a00,$66ff0000,$4c8a52ae,$ff784cfb + dc.l $3fff0170,$00004c86,$72ff7400,$76ff3d7c + dc.l $0008ff7c,$44fc0000,$48ee7fff,$ff804c01 + dc.l $340242ee,$ff7e48ee,$7fffffc0,$2d7cffff + dc.l $fffeff88,$2d7c0000,$0001ff8c,$61ff0000 + dc.l $4c144a00,$66ff0000,$4c3a52ae,$ff784cfb + dc.l $3fff0170,$00004c36,$223c8000,$00007400 + dc.l $76ff3d7c,$0000ff7c,$44fc0000,$48ee7fff + dc.l $ff804c01,$3c0242ee,$ff7e48ee,$7fffffc0 + dc.l $2d7c0000,$0000ff88,$2d7c8000,$0000ff8c + dc.l $61ff0000,$4bc04a00,$66ff0000,$4be652ae + dc.l $ff784cfb,$3fff0170,$00004be2,$223c8000 + dc.l $00007400,$76013d7c,$0008ff7c,$44fc0000 + dc.l $48ee7fff,$ff804c01,$3c0242ee,$ff7e48ee + dc.l $7fffffc0,$2d7cffff,$ffffff88,$2d7c8000 + dc.l $0000ff8c,$61ff0000,$4b6c4a00,$66ff0000 + dc.l $4b9252ae,$ff784cfb,$3fff0170,$00004b8e + dc.l $72017400,$263c8000,$00003d7c,$0008ff7c + dc.l $44fc0000,$48ee7fff,$ff804c01,$3c0242ee + dc.l $ff7e48ee,$7fffffc0,$2d7cffff,$ffffff88 + dc.l $2d7c8000,$0000ff8c,$61ff0000,$4b184a00 + dc.l $66ff0000,$4b3e222e,$ff784280,$4e75096d + dc.l $6f766570,$2e2e2e00,$52aeff78,$4cfb3fff + dc.l $01700000,$4b2841ee,$ff60303c,$aaaa4228 + dc.l $00004228,$00023d7c,$001fff7c,$44fc001f + dc.l $48ee7fff,$ff800188,$000042ee,$ff7e48ee + dc.l $7fffffc0,$12280002,$e1491228,$0000b041 + dc.l $66ff0000,$4ade61ff,$00004aaa,$4a0066ff + dc.l $00004ad0,$52aeff78,$4cfb3fff,$01700000 + dc.l $4acc41ee,$ff64303c,$aaaa42a8,$fffc4290 + dc.l $42a80004,$3d7c001f,$ff7c44fc,$001f48ee + dc.l $7fffff80,$01880000,$42eeff7e,$48ee7fff + dc.l $ffc04aa8,$fffc66ff,$00004a88,$4aa80004 + dc.l $66ff0000,$4a7e0c90,$aa00aa00,$66ff0000 + dc.l $4a7261ff,$00004a3e,$4a0066ff,$00004a64 + dc.l $52aeff78,$4cfb3fff,$01700000,$4a6041ee + dc.l $ff60303c,$aaaa4228,$00004228,$00023d7c + dc.l $0000ff7c,$44fc0000,$48ee7fff,$ff800188 + dc.l $000042ee,$ff7e48ee,$7fffffc0,$12280002 + dc.l $e1491228,$0000b041,$66ff0000,$4a1661ff + dc.l $000049e2,$4a0066ff,$00004a08,$52aeff78 + dc.l $4cfb3fff,$01700000,$4a0441ee,$ff60117c + dc.l $00aa0000,$117c00aa,$00023d7c,$001fff7c + dc.l $44fc001f,$48ee7fff,$ff800108,$000042ee + dc.l $ff7e48ee,$7fffffc0,$3d7caaaa,$ff82323c + dc.l $aaaab041,$66ff0000,$49ba61ff,$00004986 + dc.l $4a0066ff,$000049ac,$52aeff78,$4cfb3fff + dc.l $01700000,$49a841ee,$ff60203c,$aaaaaaaa + dc.l $42280000,$42280002,$42280004,$42280006 + dc.l $3d7c001f,$ff7c44fc,$001f48ee,$7fffff80 + dc.l $01c80000,$42eeff7e,$48ee7fff,$ffc01228 + dc.l $0006e189,$12280004,$e1891228,$0002e189 + dc.l $12280000,$b08166ff,$00004948,$61ff0000 + dc.l $49144a00,$66ff0000,$493a52ae,$ff784cfb + dc.l $3fff0170,$00004936,$41eeff64,$203caaaa + dc.l $aaaa42a8,$fffc4290,$42a80004,$42a80008 + dc.l $3d7c001f,$ff7c44fc,$001f48ee,$7fffff80 + dc.l $01c80000,$42eeff7e,$48ee7fff,$ffc04aa8 + dc.l $fffc66ff,$000048ec,$4aa80008,$66ff0000 + dc.l $48e20c90,$aa00aa00,$66ff0000,$48d60ca8 + dc.l $aa00aa00,$000466ff,$000048c8,$61ff0000 + dc.l $48944a00,$66ff0000,$48ba52ae,$ff784cfb + dc.l $3fff0170,$000048b6,$41eeff60,$117c00aa + dc.l $0000117c,$00aa0002,$117c00aa,$0004117c + dc.l $00aa0006,$3d7c001f,$ff7c44fc,$001f48ee + dc.l $7fffff80,$01480000,$42eeff7e,$48ee7fff + dc.l $ffc02d7c,$aaaaaaaa,$ff80223c,$aaaaaaaa + dc.l $b08166ff,$0000485c,$61ff0000,$48284a00 + dc.l $66ff0000,$484e52ae,$ff784cfb,$3fff0170 + dc.l $0000484a,$41eeff60,$3e3caaaa,$42280000 + dc.l $42280002,$3d7c001f,$ff7c44fc,$001f48ee + dc.l $7fffff80,$0f880000,$42eeff7e,$48ee7fff + dc.l $ffc01228,$0002e149,$12280000,$be4166ff + dc.l $00004800,$61ff0000,$47cc4a00,$66ff0000 + dc.l $47f252ae,$ff784cfb,$3fff0170,$000047ee + dc.l $41eeff60,$117c00aa,$0000117c,$00aa0002 + dc.l $3d7c001f,$ff7c44fc,$001f48ee,$7fffff80 + dc.l $0f080000,$42eeff7e,$48ee7fff,$ffc03d7c + dc.l $aaaaff9e,$323caaaa,$be4166ff,$000047a4 + dc.l $61ff0000,$47704a00,$66ff0000,$479652ae + dc.l $ff784cfb,$3fff0170,$00004792,$41eeff60 + dc.l $303caaaa,$42280000,$42280002,$3d7c001f + dc.l $ff7c44fc,$001f48ee,$7fffff80,$01880000 + dc.l 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$61ff0000,$0d704a00,$66ff0000,$0d9652ae + dc.l $ff784cfb,$3fff0170,$00000d92,$42827602 + dc.l $47eeff54,$49eeff70,$288b99fc,$00000010 + dc.l $78043d7c,$0000ff7c,$44fc0000,$48eeffff + dc.l $ff804c34,$34024526,$00100010,$42eeff7e + dc.l $48eeffff,$ffc02d7c,$00000004,$ff8c61ff + dc.l $00000d12,$4a0066ff,$00000d38,$52aeff78 + dc.l $4cfb3fff,$01700000,$0d344282,$760247ee + dc.l $ff5449ee,$ff70288b,$99fc0000,$00107802 + dc.l $3d7c0000,$ff7c44fc,$000048ee,$ffffff80 + dc.l $4c343402,$47260010,$001042ee,$ff7e48ee + dc.l $ffffffc0,$2d7c0000,$0004ff8c,$61ff0000 + dc.l $0cb44a00,$66ff0000,$0cda52ae,$ff784cfb + dc.l $3fff0170,$00000cd6,$42827602,$47eeff54 + dc.l $49eeff70,$288b99fc,$00000010,$78103d7c + dc.l $0000ff7c,$44fc0000,$48eeffff,$ff804c34 + dc.l $34024926,$00100010,$42eeff7e,$48eeffff + dc.l $ffc02d7c,$00000004,$ff8c61ff,$00000c56 + dc.l $4a0066ff,$00000c7c,$52aeff78,$4cfb3fff + dc.l $01700000,$0c784282,$760247ee,$ff5449ee + dc.l $ff70288b,$99fc0000,$00107808,$3d7c0000 + dc.l $ff7c44fc,$000048ee,$ffffff80,$4c343402 + dc.l $43260010,$001042ee,$ff7e48ee,$ffffffc0 + dc.l $2d7c0000,$0004ff8c,$61ff0000,$0bf84a00 + dc.l $66ff0000,$0c1e52ae,$ff784cfb,$3fff0170 + dc.l $00000c1a,$42827602,$47eeff54,$49eeff70 + dc.l $288b99fc,$00000010,$78043d7c,$0000ff7c + dc.l $44fc0000,$48eeffff,$ff804c34,$34024d26 + dc.l $00100010,$42eeff7e,$48eeffff,$ffc02d7c + dc.l $00000004,$ff8c61ff,$00000b9a,$4a0066ff + dc.l $00000bc0,$52aeff78,$4cfb3fff,$01700000 + dc.l $0bbc4282,$760247ee,$ff5449ee,$ff70288b + dc.l $99fc0000,$00107802,$3d7c0000,$ff7c44fc + dc.l $000048ee,$ffffff80,$4c343402,$4f260010 + dc.l $001042ee,$ff7e48ee,$ffffffc0,$2d7c0000 + dc.l $0004ff8c,$61ff0000,$0b3c4a00,$66ff0000 + dc.l $0b6252ae,$ff784cfb,$3fff0170,$00000b5e + dc.l $42827602,$47eeff54,$49eeff70,$288b99fc + dc.l $00000010,$78023d7c,$0000ff7c,$44fc0000 + dc.l $48eeffff,$ff804c34,$34024f37,$00000010 + dc.l $00000010,$42eeff7e,$48eeffff,$ffc02d7c + dc.l $00000004,$ff8c61ff,$00000ada,$4a0066ff + dc.l $00000b00,$52aeff78,$4cfb3fff,$01700000 + dc.l $0afc4282,$760247ee,$ff5449ee,$ff70288b + dc.l $78023d7c,$0000ff7c,$44fc0000,$48eeffff + dc.l $ff804c34,$34020753,$00000020,$42eeff7e + dc.l $48eeffff,$ffc02d7c,$00000004,$ff8c61ff + dc.l $00000a82,$4a0066ff,$00000aa8,$52aeff78 + dc.l $4cfb3fff,$01700000,$0aa4204f,$42827602 + dc.l $47eeff54,$4feeff70,$2e8b7820,$3d7c0000 + dc.l $ff7c44fc,$000048ee,$ffffff80,$4c373402 + dc.l $491542ee,$ff7e48ee,$ffffffc0,$2d7c0000 + dc.l $0004ff8c,$2e4861ff,$00000a2a,$4a0066ff + dc.l $00000a50,$52aeff78,$52aeff78,$4cfb3fff + dc.l $01700000,$0a48224e,$42827602,$47e9ff74 + dc.l $4de9ff70,$2c8bddfc,$00000010,$2a7cffff + dc.l $fffe337c,$0000ff7c,$44fc0000,$48e9ffff + dc.l $ff804c36,$3402df27,$fff00000,$001042e9 + dc.l $ff7e48e9,$ffffffc0,$237c0000,$0004ff8c + dc.l $2c4961ff,$000009be,$4a0066ff,$000009e4 + dc.l $222eff78,$42804e75,$52aeff78,$4cfb3fff + dc.l $01700000,$09d84282,$760247fa,$ef7449fa + dc.l $ff70288b,$78f03d7c,$0000ff7c,$44fc0000 + dc.l $48eeffff,$ff804c3b,$34024122,$ff801000 + dc.l $42eeff7e,$48eeffff,$ffc02d7c,$00000004 + dc.l $ff8c61ff,$0000095e,$4a0066ff,$00000984 + dc.l $52aeff78,$4cfb3fff,$01700000,$09804282 + dc.l $760247fa,$ef7449fa,$ff70288b,$78f83d7c + dc.l $0000ff7c,$44fc0000,$48eeffff,$ff804c3b + dc.l $34024322,$ff801000,$42eeff7e,$48eeffff + dc.l $ffc02d7c,$00000004,$ff8c61ff,$00000906 + dc.l $4a0066ff,$0000092c,$52aeff78,$4cfb3fff + dc.l $01700000,$09284282,$760247fa,$ef7449fa + dc.l $ff70288b,$78fc3d7c,$0000ff7c,$44fc0000 + dc.l $48eeffff,$ff804c3b,$34024522,$ff801000 + dc.l $42eeff7e,$48eeffff,$ffc02d7c,$00000004 + dc.l $ff8c61ff,$000008ae,$4a0066ff,$000008d4 + dc.l $52aeff78,$4cfb3fff,$01700000,$08d04282 + dc.l $760247fa,$ef7449fa,$ff70288b,$78fe3d7c + dc.l $0000ff7c,$44fc0000,$48eeffff,$ff804c3b + dc.l $34024722,$ff801000,$42eeff7e,$48eeffff + dc.l $ffc02d7c,$00000004,$ff8c61ff,$00000856 + dc.l $4a0066ff,$0000087c,$52aeff78,$4cfb3fff + dc.l $01700000,$08784282,$760247fa,$ef7449fa + dc.l $ff70288b,$78f03d7c,$0000ff7c,$44fc0000 + dc.l $48eeffff,$ff804c3b,$34024922,$ff801000 + dc.l $42eeff7e,$48eeffff,$ffc02d7c,$00000004 + dc.l $ff8c61ff,$000007fe,$4a0066ff,$00000824 + dc.l $52aeff78,$4cfb3fff,$01700000,$08204282 + dc.l $760247fa,$ef7449fa,$ff70288b,$78f83d7c + dc.l $0000ff7c,$44fc0000,$48eeffff,$ff804c3b + dc.l $34024b22,$ff801000,$42eeff7e,$48eeffff + dc.l $ffc02d7c,$00000004,$ff8c61ff,$000007a6 + dc.l $4a0066ff,$000007cc,$52aeff78,$4cfb3fff + dc.l $01700000,$07c84282,$760247fa,$ef7449fa + dc.l $ff70288b,$78fc3d7c,$0000ff7c,$44fc0000 + dc.l $48eeffff,$ff804c3b,$34024d22,$ff801000 + dc.l $42eeff7e,$48eeffff,$ffc02d7c,$00000004 + dc.l $ff8c61ff,$0000074e,$4a0066ff,$00000774 + dc.l $52aeff78,$4cfb3fff,$01700000,$07704282 + dc.l $760247fa,$ef7449fa,$ff70288b,$78fe3d7c + dc.l $0000ff7c,$44fc0000,$48eeffff,$ff804c3b + dc.l $34024f22,$ff801000,$42eeff7e,$48eeffff + dc.l $ffc02d7c,$00000004,$ff8c61ff,$000006f6 + dc.l $4a0066ff,$0000071c,$52aeff78,$4cfb3fff + dc.l $01700000,$07184282,$760247fa,$ef7449fa + dc.l $ff70288b,$78fe3d7c,$0000ff7c,$44fc0000 + dc.l $48eeffff,$ff804c3b,$34024f33,$ffffff80 + dc.l $00001000,$42eeff7e,$48eeffff,$ffc02d7c + dc.l $00000004,$ff8c61ff,$0000069a,$4a0066ff + dc.l $000006c0,$52aeff78,$4cfb3fff,$01700000 + dc.l $06bc4282,$760247fa,$ef7449fa,$ff70288b + dc.l $78fe3d7c,$0000ff7c,$44fc0000,$48eeffff + dc.l $ff804c3b,$34020773,$ffffff70,$00001000 + dc.l $42eeff7e,$48eeffff,$ffc02d7c,$00000004 + dc.l $ff8c61ff,$0000063e,$4a0066ff,$00000664 + dc.l $52aeff78,$4cfb3fff,$01700000,$06604282 + dc.l $760247fa,$ef7449fa,$ff70288b,$280c3d7c + dc.l $0000ff7c,$44fc0000,$48eeffff,$ff804c30 + dc.l $34024993,$00001000,$42eeff7e,$48eeffff + dc.l $ffc02d7c,$00000004,$ff8c61ff,$000005e6 + dc.l $4a0066ff,$0000060c,$52aeff78,$4cfb3fff + dc.l $01700000,$06084282,$760247fa,$ef7449fa + dc.l $ff70288b,$78f0d88c,$3d7c0000,$ff7c44fc + dc.l $000048ee,$ffffff80,$4c303402,$49b30000 + dc.l $00100000,$100042ee,$ff7e48ee,$ffffffc0 + dc.l $2d7c0000,$0004ff8c,$61ff0000,$05884a00 + dc.l $66ff0000,$05ae52ae,$ff784282,$760247fa + dc.l $ff7449fa,$ff70288b,$78f03d7c,$0000ff7c + dc.l $44fc0000,$48eeffff,$ff804c30,$340201f1 + dc.l $ffffff70,$42eeff7e,$48eeffff,$ffc02d7c + dc.l $00000004,$ff8c61ff,$0000053a,$4a0066ff + dc.l $00000560,$52aeff78,$4cfb3fff,$01700000 + dc.l $055c4282,$760247fa,$0f7449fa,$ff70288b + dc.l $2c7c0000,$00023d7c,$0000ff7c,$44fc0000 + dc.l $48eeffff,$ff804c3b,$3402ef22,$ff60f000 + dc.l $42eeff7e,$48eeffff,$ffc02d7c,$00000004 + dc.l $ff8c61ff,$000004de,$4a0066ff,$00000504 + dc.l $52aeff78,$4cfb3fff,$01700000,$0500204f + dc.l $42827602,$47fa0f74,$49faff70,$288b2e7c + dc.l $00000002,$3d7c0000,$ff7c44fc,$000048ee + dc.l $ffffff80,$4c3b3402,$ff22ff60,$f00042ee + dc.l $ff7e48ee,$ffffffc0,$2d7c0000,$0004ff8c + dc.l $2e4861ff,$0000047e,$4a0066ff,$000004a4 + dc.l $52aeff78,$4cfb3fff,$01700000,$04a04282 + dc.l $760247fa,$ff5449fa,$ff70288b,$99fc0000 + dc.l $00107810,$3d7c0000,$ff7c44fc,$000048ee + dc.l $ffffff80,$4c3b3402,$4126ff70,$001042ee + dc.l $ff7e48ee,$ffffffc0,$2d7c0000,$0004ff8c + dc.l $61ff0000,$04204a00,$66ff0000,$044652ae + dc.l $ff784cfb,$3fff0170,$00000442,$42827602 + dc.l $47faff54,$49faff70,$288b99fc,$00000010 + dc.l $78083d7c,$0000ff7c,$44fc0000,$48eeffff + dc.l $ff804c3b,$34024326,$ff700010,$42eeff7e + dc.l $48eeffff,$ffc02d7c,$00000004,$ff8c61ff + dc.l $000003c2,$4a0066ff,$000003e8,$52aeff78 + dc.l $4cfb3fff,$01700000,$03e44282,$760247fa + dc.l $ff5449fa,$ff70288b,$99fc0000,$00107804 + dc.l $3d7c0000,$ff7c44fc,$000048ee,$ffffff80 + dc.l $4c3b3402,$4526ff70,$001042ee,$ff7e48ee + dc.l $ffffffc0,$2d7c0000,$0004ff8c,$61ff0000 + dc.l $03644a00,$66ff0000,$038a52ae,$ff784cfb + dc.l $3fff0170,$00000386,$42827602,$47faff54 + dc.l $49faff70,$288b99fc,$00000010,$78023d7c + dc.l $0000ff7c,$44fc0000,$48eeffff,$ff804c3b + dc.l $34024726,$ff700010,$42eeff7e,$48eeffff + dc.l $ffc02d7c,$00000004,$ff8c61ff,$00000306 + dc.l $4a0066ff,$0000032c,$52aeff78,$4cfb3fff + dc.l $01700000,$03284282,$760247fa,$ff5449fa + dc.l $ff70288b,$99fc0000,$00107810,$3d7c0000 + dc.l $ff7c44fc,$000048ee,$ffffff80,$4c3b3402 + dc.l $4926ff70,$001042ee,$ff7e48ee,$ffffffc0 + dc.l $2d7c0000,$0004ff8c,$61ff0000,$02a84a00 + dc.l $66ff0000,$02ce52ae,$ff784cfb,$3fff0170 + dc.l $000002ca,$42827602,$47faff54,$49faff70 + dc.l $288b99fc,$00000010,$78083d7c,$0000ff7c + dc.l $44fc0000,$48eeffff,$ff804c3b,$34024326 + dc.l $ff700010,$42eeff7e,$48eeffff,$ffc02d7c + dc.l $00000004,$ff8c61ff,$0000024a,$4a0066ff + dc.l $00000270,$52aeff78,$4cfb3fff,$01700000 + dc.l $026c4282,$760247fa,$ff5449fa,$ff70288b + dc.l $99fc0000,$00107804,$3d7c0000,$ff7c44fc + dc.l $000048ee,$ffffff80,$4c3b3402,$4d26ff70 + dc.l $001042ee,$ff7e48ee,$ffffffc0,$2d7c0000 + dc.l $0004ff8c,$61ff0000,$01ec4a00,$66ff0000 + dc.l $021252ae,$ff784cfb,$3fff0170,$0000020e + dc.l $42827602,$47faff54,$49faff70,$288b99fc + dc.l $00000010,$78023d7c,$0000ff7c,$44fc0000 + dc.l $48eeffff,$ff804c3b,$34024f26,$ff700010 + dc.l $42eeff7e,$48eeffff,$ffc02d7c,$00000004 + dc.l $ff8c61ff,$0000018e,$4a0066ff,$000001b4 + dc.l $52aeff78,$4cfb3fff,$01700000,$01b04282 + dc.l $760247fa,$ff5449fa,$ff70288b,$99fc0000 + dc.l $00107802,$3d7c0000,$ff7c44fc,$000048ee + dc.l $ffffff80,$4c3b3402,$4f37ffff,$ff700000 + dc.l $001042ee,$ff7e48ee,$ffffffc0,$2d7c0000 + dc.l $0004ff8c,$61ff0000,$012c4a00,$66ff0000 + dc.l $015252ae,$ff784cfb,$3fff0170,$0000014e + dc.l $42827602,$47faff54,$49faff70,$288b7802 + dc.l $3d7c0000,$ff7c44fc,$000048ee,$ffffff80 + dc.l $4c3b3402,$0773ffff,$ff700000,$002042ee + dc.l $ff7e48ee,$ffffffc0,$2d7c0000,$0004ff8c + dc.l $61ff0000,$00d04a00,$66ff0000,$00f652ae + dc.l $ff784cfb,$3fff0170,$000000f2,$42827602 + dc.l $47faff54,$49faff70,$288b7804,$3d7c0000 + dc.l $ff7c44fc,$000048ee,$ffffff80,$4c303402 + dc.l $4fb5ffff,$ff7042ee,$ff7e48ee,$ffffffc0 + dc.l $2d7c0000,$0004ff8c,$61ff0000,$00784a00 + dc.l $66ff0000,$009e52ae,$ff784cfb,$3fff0170 + dc.l $0000009a,$204f4282,$760247fa,$ff744dfa + dc.l $ff702c8b,$ddfc0000,$00102e7c,$fffffffe + dc.l $3d7c0000,$ff7c44fc,$000048ee,$ffffff80 + dc.l $4c3b3402,$ff27ff70,$00000010,$42eeff7e + dc.l $48eeffff,$ffc02d7c,$00000004,$ff8c2e48 + dc.l $61ff0000,$00104a00,$66ff0000,$00364280 + dc.l $4e7541ee,$ff8043ee,$ffc0700e,$b18966ff + dc.l $0000001c,$51c8fff6,$302eff7c,$322eff7e + dc.l $b04166ff,$00000008,$42804e75,$70014e75 + dc.l $222eff78,$70014e75,$acacacac,$acacacac + dc.l $acacacac,$acacacac,$acacacac,$acacacac + dc.l $acacacac,$acacacac,$acacacac,$acacacac + dc.l $acacacac,$acacacac,$acacacac,$acacacac + dc.l $acacacac,$acacacac,$2f00203a,$afa4487b + dc.l $0930ffff,$afa0202f,$00044e74,$00042f00 + dc.l $203aaf92,$487b0930,$ffffaf8a,$202f0004 + dc.l $4e740004,$00000000,$00000000,$00000000 diff --git a/arch/m68k/ifpsp060/os.S b/arch/m68k/ifpsp060/os.S new file mode 100644 index 000000000..89e2ec224 --- /dev/null +++ b/arch/m68k/ifpsp060/os.S @@ -0,0 +1,396 @@ +|~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +|MOTOROLA MICROPROCESSOR & MEMORY TECHNOLOGY GROUP +|M68000 Hi-Performance Microprocessor Division +|M68060 Software Package +|Production Release P1.00 -- October 10, 1994 +| +|M68060 Software Package Copyright © 1993, 1994 Motorola Inc. All rights reserved. +| +|THE SOFTWARE is provided on an "AS IS" basis and without warranty. +|To the maximum extent permitted by applicable law, +|MOTOROLA DISCLAIMS ALL WARRANTIES WHETHER EXPRESS OR IMPLIED, +|INCLUDING IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE +|and any warranty against infringement with regard to the SOFTWARE +|(INCLUDING ANY MODIFIED VERSIONS THEREOF) and any accompanying written materials. +| +|To the maximum extent permitted by applicable law, +|IN NO EVENT SHALL MOTOROLA BE LIABLE FOR ANY DAMAGES WHATSOEVER +|(INCLUDING WITHOUT LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, +|BUSINESS INTERRUPTION, LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY LOSS) +|ARISING OF THE USE OR INABILITY TO USE THE SOFTWARE. +|Motorola assumes no responsibility for the maintenance and support of the SOFTWARE. +| +|You are hereby granted a copyright license to use, modify, and distribute the SOFTWARE +|so long as this entire notice is retained without alteration in any modified and/or +|redistributed versions, and that such modified versions are clearly identified as such. +|No licenses are granted by implication, estoppel or otherwise under any patents +|or trademarks of Motorola, Inc. +|~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +| os.s +| +| This file contains: +| - example "Call-Out"s required by both the ISP and FPSP. +| + +#include + +|################################ +| EXAMPLE CALL-OUTS # +| # +| _060_dmem_write() # +| _060_dmem_read() # +| _060_imem_read() # +| _060_dmem_read_byte() # +| _060_dmem_read_word() # +| _060_dmem_read_long() # +| _060_imem_read_word() # +| _060_imem_read_long() # +| _060_dmem_write_byte() # +| _060_dmem_write_word() # +| _060_dmem_write_long() # +| # +| _060_real_trace() # +| _060_real_access() # +|################################ + +| +| Each IO routine checks to see if the memory write/read is to/from user +| or supervisor application space. The examples below use simple "move" +| instructions for supervisor mode applications and call _copyin()/_copyout() +| for user mode applications. +| When installing the 060SP, the _copyin()/_copyout() equivalents for a +| given operating system should be substituted. +| +| The addresses within the 060SP are guaranteed to be on the stack. +| The result is that Unix processes are allowed to sleep as a consequence +| of a page fault during a _copyout. +| +| Linux/68k: The _060_[id]mem_{read,write}_{byte,word,long} functions +| (i.e. all the known length <= 4) are implemented by single moves +| statements instead of (more expensive) copy{in,out} calls, if +| working in user space + +| +| _060_dmem_write(): +| +| Writes to data memory while in supervisor mode. +| +| INPUTS: +| a0 - supervisor source address +| a1 - user destination address +| d0 - number of bytes to write +| 0x4(%a6),bit5 - 1 = supervisor mode, 0 = user mode +| OUTPUTS: +| d1 - 0 = success, !0 = failure +| + .global _060_dmem_write +_060_dmem_write: + subq.l #1,%d0 + btst #0x5,0x4(%a6) | check for supervisor state + beqs user_write +super_write: + move.b (%a0)+,(%a1)+ | copy 1 byte + dbra %d0,super_write | quit if --ctr < 0 + clr.l %d1 | return success + rts +user_write: + move.b (%a0)+,%d1 | copy 1 byte +copyoutae: + movs.b %d1,(%a1)+ + dbra %d0,user_write | quit if --ctr < 0 + clr.l %d1 | return success + rts + +| +| _060_imem_read(), _060_dmem_read(): +| +| Reads from data/instruction memory while in supervisor mode. +| +| INPUTS: +| a0 - user source address +| a1 - supervisor destination address +| d0 - number of bytes to read +| 0x4(%a6),bit5 - 1 = supervisor mode, 0 = user mode +| OUTPUTS: +| d1 - 0 = success, !0 = failure +| + .global _060_imem_read + .global _060_dmem_read +_060_imem_read: +_060_dmem_read: + subq.l #1,%d0 + btst #0x5,0x4(%a6) | check for supervisor state + beqs user_read +super_read: + move.b (%a0)+,(%a1)+ | copy 1 byte + dbra %d0,super_read | quit if --ctr < 0 + clr.l %d1 | return success + rts +user_read: +copyinae: + movs.b (%a0)+,%d1 + move.b %d1,(%a1)+ | copy 1 byte + dbra %d0,user_read | quit if --ctr < 0 + clr.l %d1 | return success + rts + +| +| _060_dmem_read_byte(): +| +| Read a data byte from user memory. +| +| INPUTS: +| a0 - user source address +| 0x4(%a6),bit5 - 1 = supervisor mode, 0 = user mode +| OUTPUTS: +| d0 - data byte in d0 +| d1 - 0 = success, !0 = failure +| + .global _060_dmem_read_byte +_060_dmem_read_byte: + clr.l %d0 | clear whole longword + clr.l %d1 | assume success + btst #0x5,0x4(%a6) | check for supervisor state + bnes dmrbs | supervisor +dmrbuae:movs.b (%a0),%d0 | fetch user byte + rts +dmrbs: move.b (%a0),%d0 | fetch super byte + rts + +| +| _060_dmem_read_word(): +| +| Read a data word from user memory. +| +| INPUTS: +| a0 - user source address +| 0x4(%a6),bit5 - 1 = supervisor mode, 0 = user mode +| OUTPUTS: +| d0 - data word in d0 +| d1 - 0 = success, !0 = failure +| +| _060_imem_read_word(): +| +| Read an instruction word from user memory. +| +| INPUTS: +| a0 - user source address +| 0x4(%a6),bit5 - 1 = supervisor mode, 0 = user mode +| OUTPUTS: +| d0 - instruction word in d0 +| d1 - 0 = success, !0 = failure +| + .global _060_dmem_read_word + .global _060_imem_read_word +_060_dmem_read_word: +_060_imem_read_word: + clr.l %d1 | assume success + clr.l %d0 | clear whole longword + btst #0x5,0x4(%a6) | check for supervisor state + bnes dmrws | supervisor +dmrwuae:movs.w (%a0), %d0 | fetch user word + rts +dmrws: move.w (%a0), %d0 | fetch super word + rts + +| +| _060_dmem_read_long(): +| + +| +| INPUTS: +| a0 - user source address +| 0x4(%a6),bit5 - 1 = supervisor mode, 0 = user mode +| OUTPUTS: +| d0 - data longword in d0 +| d1 - 0 = success, !0 = failure +| +| _060_imem_read_long(): +| +| Read an instruction longword from user memory. +| +| INPUTS: +| a0 - user source address +| 0x4(%a6),bit5 - 1 = supervisor mode, 0 = user mode +| OUTPUTS: +| d0 - instruction longword in d0 +| d1 - 0 = success, !0 = failure +| + .global _060_dmem_read_long + .global _060_imem_read_long +_060_dmem_read_long: +_060_imem_read_long: + clr.l %d1 | assume success + btst #0x5,0x4(%a6) | check for supervisor state + bnes dmrls | supervisor +dmrluae:movs.l (%a0),%d0 | fetch user longword + rts +dmrls: move.l (%a0),%d0 | fetch super longword + rts + +| +| _060_dmem_write_byte(): +| +| Write a data byte to user memory. +| +| INPUTS: +| a0 - user destination address +| d0 - data byte in d0 +| 0x4(%a6),bit5 - 1 = supervisor mode, 0 = user mode +| OUTPUTS: +| d1 - 0 = success, !0 = failure +| + .global _060_dmem_write_byte +_060_dmem_write_byte: + clr.l %d1 | assume success + btst #0x5,0x4(%a6) | check for supervisor state + bnes dmwbs | supervisor +dmwbuae:movs.b %d0,(%a0) | store user byte + rts +dmwbs: move.b %d0,(%a0) | store super byte + rts + +| +| _060_dmem_write_word(): +| +| Write a data word to user memory. +| +| INPUTS: +| a0 - user destination address +| d0 - data word in d0 +| 0x4(%a6),bit5 - 1 = supervisor mode, 0 = user mode +| OUTPUTS: +| d1 - 0 = success, !0 = failure +| + .global _060_dmem_write_word +_060_dmem_write_word: + clr.l %d1 | assume success + btst #0x5,0x4(%a6) | check for supervisor state + bnes dmwws | supervisor +dmwwu: +dmwwuae:movs.w %d0,(%a0) | store user word + bras dmwwr +dmwws: move.w %d0,(%a0) | store super word +dmwwr: clr.l %d1 | return success + rts + +| +| _060_dmem_write_long(): +| +| Write a data longword to user memory. +| +| INPUTS: +| a0 - user destination address +| d0 - data longword in d0 +| 0x4(%a6),bit5 - 1 = supervisor mode, 0 = user mode +| OUTPUTS: +| d1 - 0 = success, !0 = failure +| + .global _060_dmem_write_long +_060_dmem_write_long: + clr.l %d1 | assume success + btst #0x5,0x4(%a6) | check for supervisor state + bnes dmwls | supervisor +dmwluae:movs.l %d0,(%a0) | store user longword + rts +dmwls: move.l %d0,(%a0) | store super longword + rts + + +#if 0 +|############################################### + +| +| Use these routines if your kernel doesn't have _copyout/_copyin equivalents. +| Assumes that D0/D1/A0/A1 are scratch registers. The _copyin/_copyout +| below assume that the SFC/DFC have been set previously. +| +| Linux/68k: These are basically non-inlined versions of +| memcpy_{to,from}fs, but without long-transfer optimization +| Note: Assumed that SFC/DFC are pointing correctly to user data +| space... Should be right, or are there any exceptions? + +| +| int _copyout(supervisor_addr, user_addr, nbytes) +| + .global _copyout +_copyout: + move.l 4(%sp),%a0 | source + move.l 8(%sp),%a1 | destination + move.l 12(%sp),%d0 | count + subq.l #1,%d0 +moreout: + move.b (%a0)+,%d1 | fetch supervisor byte +copyoutae: + movs.b %d1,(%a1)+ | store user byte + dbra %d0,moreout | are we through yet? + moveq #0,%d0 | return success + rts + +| +| int _copyin(user_addr, supervisor_addr, nbytes) +| + .global _copyin +_copyin: + move.l 4(%sp),%a0 | source + move.l 8(%sp),%a1 | destination + move.l 12(%sp),%d0 | count + subq.l #1,%d0 +morein: +copyinae: + movs.b (%a0)+,%d1 | fetch user byte + move.b %d1,(%a1)+ | write supervisor byte + dbra %d0,morein | are we through yet? + moveq #0,%d0 | return success + rts +#endif + +|########################################################################### + +| +| _060_real_trace(): +| +| This is the exit point for the 060FPSP when an instruction is being traced +| and there are no other higher priority exceptions pending for this instruction +| or they have already been processed. +| +| The sample code below simply executes an "rte". +| + .global _060_real_trace +_060_real_trace: + bral trap + +| +| _060_real_access(): +| +| This is the exit point for the 060FPSP when an access error exception +| is encountered. The routine below should point to the operating system +| handler for access error exceptions. The exception stack frame is an +| 8-word access error frame. +| +| The sample routine below simply executes an "rte" instruction which +| is most likely the incorrect thing to do and could put the system +| into an infinite loop. +| + .global _060_real_access +_060_real_access: + bral buserr + + + +| Execption handling for movs access to illegal memory + .section .fixup,"ax" + .even +1: moveq #-1,%d1 + rts +.section __ex_table,"a" + .align 4 + .long dmrbuae,1b + .long dmrwuae,1b + .long dmrluae,1b + .long dmwbuae,1b + .long dmwwuae,1b + .long dmwluae,1b + .long copyoutae,1b + .long copyinae,1b + .text diff --git a/arch/m68k/ifpsp060/pfpsp.sa b/arch/m68k/ifpsp060/pfpsp.sa new file mode 100644 index 000000000..d276b27f1 --- /dev/null +++ b/arch/m68k/ifpsp060/pfpsp.sa @@ -0,0 +1,1730 @@ + dc.l $60ff0000,$17400000,$60ff0000,$15f40000 + dc.l $60ff0000,$02b60000,$60ff0000,$04700000 + dc.l $60ff0000,$1b100000,$60ff0000,$19aa0000 + dc.l $60ff0000,$1b5a0000,$60ff0000,$062e0000 + dc.l $60ff0000,$102c0000,$51fc51fc,$51fc51fc + dc.l $51fc51fc,$51fc51fc,$51fc51fc,$51fc51fc + dc.l $51fc51fc,$51fc51fc,$51fc51fc,$51fc51fc + dc.l $51fc51fc,$51fc51fc,$51fc51fc,$51fc51fc + dc.l $2f00203a,$ff2c487b,$0930ffff,$fef8202f + dc.l $00044e74,$00042f00,$203afef2,$487b0930 + dc.l $fffffee2,$202f0004,$4e740004,$2f00203a + dc.l $fee0487b,$0930ffff,$fecc202f,$00044e74 + dc.l $00042f00,$203afed2,$487b0930,$fffffeb6 + dc.l $202f0004,$4e740004,$2f00203a,$fea4487b + dc.l $0930ffff,$fea0202f,$00044e74,$00042f00 + dc.l $203afe96,$487b0930,$fffffe8a,$202f0004 + dc.l $4e740004,$2f00203a,$fe7c487b,$0930ffff + dc.l $fe74202f,$00044e74,$00042f00,$203afe76 + dc.l $487b0930,$fffffe5e,$202f0004,$4e740004 + dc.l $2f00203a,$fe68487b,$0930ffff,$fe48202f + dc.l $00044e74,$00042f00,$203afe56,$487b0930 + dc.l $fffffe32,$202f0004,$4e740004,$2f00203a + dc.l $fe44487b,$0930ffff,$fe1c202f,$00044e74 + dc.l $00042f00,$203afe32,$487b0930,$fffffe06 + dc.l $202f0004,$4e740004,$2f00203a,$fe20487b + dc.l $0930ffff,$fdf0202f,$00044e74,$00042f00 + dc.l $203afe1e,$487b0930,$fffffdda,$202f0004 + dc.l $4e740004,$2f00203a,$fe0c487b,$0930ffff + dc.l $fdc4202f,$00044e74,$00042f00,$203afdfa + dc.l $487b0930,$fffffdae,$202f0004,$4e740004 + dc.l $2f00203a,$fde8487b,$0930ffff,$fd98202f + dc.l $00044e74,$00042f00,$203afdd6,$487b0930 + dc.l $fffffd82,$202f0004,$4e740004,$2f00203a + dc.l $fdc4487b,$0930ffff,$fd6c202f,$00044e74 + dc.l $00042f00,$203afdb2,$487b0930,$fffffd56 + dc.l $202f0004,$4e740004,$2f00203a,$fda0487b + dc.l $0930ffff,$fd40202f,$00044e74,$00042f00 + dc.l $203afd8e,$487b0930,$fffffd2a,$202f0004 + dc.l $4e740004,$2f00203a,$fd7c487b,$0930ffff + dc.l $fd14202f,$00044e74,$00042f00,$203afd6a + dc.l $487b0930,$fffffcfe,$202f0004,$4e740004 + dc.l $40c62d38,$d3d64634,$3d6f90ae,$b1e75cc7 + dc.l $40000000,$c90fdaa2,$2168c235,$00000000 + dc.l $3fff0000,$c90fdaa2,$2168c235,$00000000 + dc.l $3fe45f30,$6dc9c883,$4e56ff40,$f32eff6c + dc.l $48ee0303,$ff9cf22e,$bc00ff60,$f22ef0c0 + dc.l $ffdc2d6e,$ff68ff44,$206eff44,$58aeff44 + dc.l $61ffffff,$ff042d40,$ff40082e,$0005ff42 + dc.l $66000116,$41eeff6c,$61ff0000,$051c41ee + dc.l $ff6c61ff,$00002aec,$1d40ff4e,$082e0005 + dc.l $ff436726,$e9ee0183,$ff4261ff,$00005cac + dc.l $41eeff78,$61ff0000,$2aca0c00,$00066606 + dc.l $61ff0000,$2a2e1d40,$ff4f4280,$102eff63 + dc.l $122eff43,$0241007f,$02ae00ff,$01ffff64 + dc.l $f23c9000,$00000000,$f23c8800,$00000000 + dc.l $41eeff6c,$43eeff78,$223b1530,$00001974 + dc.l $4ebb1930,$0000196c,$e9ee0183,$ff4261ff + dc.l $00005cd8,$082e0004,$ff626622,$082e0001 + dc.l $ff626644,$f22ed0c0,$ffdcf22e,$9c00ff60 + dc.l $4cee0303,$ff9c4e5e,$60ffffff,$fcc6f22e + dc.l $f040ff6c,$3d7ce005,$ff6ef22e,$d0c0ffdc + dc.l $f22e9c00,$ff604cee,$0303ff9c,$f36eff6c + dc.l $4e5e60ff,$fffffcb2,$f22ef040,$ff6c1d7c + dc.l $00c4000b,$3d7ce001,$ff6ef22e,$d0c0ffdc + dc.l $f22e9c00,$ff604cee,$0303ff9c,$f36eff6c + dc.l $4e5e60ff,$fffffcae,$1d7c0000,$ff4e4280 + dc.l $102eff63,$02aeffff,$00ffff64,$f23c9000 + dc.l $00000000,$f23c8800,$00000000,$41eeff6c + dc.l $61ff0000,$2e0c082e,$0004ff62,$6600ff70 + dc.l $082e0001,$ff626600,$ff90f22e,$d0c0ffdc + dc.l $f22e9c00,$ff604cee,$0303ff9c,$4e5e0817 + dc.l $000767ff,$fffffc0c,$f22fa400,$00083f7c + dc.l $20240006,$60ffffff,$fcec4e56,$ff40f32e + dc.l $ff6c48ee,$0303ff9c,$f22ebc00,$ff60f22e + dc.l $f0c0ffdc,$2d6eff68,$ff44206e,$ff4458ae + dc.l $ff4461ff,$fffffd42,$2d40ff40,$082e0005 + dc.l $ff426600,$013241ee,$ff6c61ff,$0000035a + dc.l $41eeff6c,$61ff0000,$292a1d40,$ff4e082e + dc.l $0005ff43,$672e082e,$0004ff43,$6626e9ee + dc.l $0183ff42,$61ff0000,$5ae241ee,$ff7861ff + dc.l $00002900,$0c000006,$660661ff,$00002864 + dc.l $1d40ff4f,$4280102e,$ff63122e,$ff430241 + dc.l $007f02ae,$00ff01ff,$ff64f23c,$90000000 + dc.l $0000f23c,$88000000,$000041ee,$ff6c43ee + dc.l $ff78223b,$15300000,$17aa4ebb,$19300000 + dc.l $17a2e9ee,$0183ff42,$61ff0000,$5b0e082e + dc.l $0003ff62,$6622082e,$0001ff62,$664ef22e + dc.l $d0c0ffdc,$f22e9c00,$ff604cee,$0303ff9c + dc.l $4e5e60ff,$fffffafc,$082e0003,$ff666700 + dc.l $ffd6f22e,$f040ff6c,$3d7ce003,$ff6ef22e + dc.l $d0c0ffdc,$f22e9c00,$ff604cee,$0303ff9c + dc.l $f36eff6c,$4e5e60ff,$fffffaf4,$082e0001 + dc.l $ff666700,$ffaaf22e,$f040ff6c,$1d7c00c4 + dc.l $000b3d7c,$e001ff6e,$f22ed0c0,$ffdcf22e + dc.l $9c00ff60,$4cee0303,$ff9cf36e,$ff6c4e5e + dc.l $60ffffff,$fad01d7c,$0000ff4e,$4280102e + dc.l $ff6302ae,$ffff00ff,$ff64f23c,$90000000 + dc.l $0000f23c,$88000000,$000041ee,$ff6c61ff + dc.l $00002c2e,$082e0003,$ff626600,$ff66082e + dc.l $0001ff62,$6600ff90,$f22ed0c0,$ffdcf22e + dc.l $9c00ff60,$4cee0303,$ff9c4e5e,$08170007 + dc.l $67ffffff,$fa2ef22f,$a4000008,$3f7c2024 + dc.l $000660ff,$fffffb0e,$4e56ff40,$f32eff6c + dc.l $48ee0303,$ff9cf22e,$bc00ff60,$f22ef0c0 + dc.l $ffdc082e,$00050004,$66084e68,$2d48ffd8 + dc.l $600841ee,$00102d48,$ffd82d6e,$ff68ff44 + dc.l $206eff44,$58aeff44,$61ffffff,$fb4c2d40 + dc.l $ff40422e,$ff4a082e,$0005ff42,$66000208 + dc.l $e9ee0006,$ff420c00,$00136700,$049e02ae + dc.l $00ff00ff,$ff64f23c,$90000000,$0000f23c + dc.l $88000000,$000041ee,$ff6c61ff,$0000013a + dc.l $41eeff6c,$61ff0000,$270a0c00,$00066606 + dc.l $61ff0000,$266e1d40,$ff4ee9ee,$0183ff42 + dc.l $082e0005,$ff436728,$0c2e003a,$ff436720 + dc.l $61ff0000,$58b641ee,$ff7861ff,$000026d4 + dc.l $0c000006,$660661ff,$00002638,$1d40ff4f + dc.l $4280102e,$ff63e9ee,$1047ff43,$41eeff6c + dc.l $43eeff78,$223b1d30,$00001598,$4ebb1930 + dc.l $00001590,$102eff62,$6634102e,$ff430200 + dc.l $00380c00,$0038670c,$e9ee0183,$ff4261ff + dc.l $000058e8,$f22ed0c0,$ffdcf22e,$9c00ff60 + dc.l $4cee0303,$ff9c4e5e,$60ffffff,$f8e6c02e + dc.l $ff66edc0,$06086614,$082e0004,$ff6667ba + dc.l $082e0001,$ff6267b2,$60000066,$04800000 + dc.l $00180c00,$00066614,$082e0003,$ff666600 + dc.l $004a082e,$0004ff66,$66000046,$2f0061ff + dc.l $000007e0,$201f3d7b,$0222ff6e,$f22ed0c0 + dc.l $ffdcf22e,$9c00ff60,$4cee0303,$ff9cf36e + dc.l $ff6c4e5e,$60ffffff,$f87ae000,$e006e004 + dc.l $e005e003,$e002e001,$e001303c,$000460bc + dc.l $303c0003,$60b6e9ee,$0006ff42,$0c000011 + dc.l $67080c00,$00156750,$4e753028,$00000240 + dc.l $7fff0c40,$3f806708,$0c40407f,$672c4e75 + dc.l $02a87fff,$ffff0004,$671861ff,$000024cc + dc.l $44400640,$3f810268,$80000000,$81680000 + dc.l $4e750268,$80000000,$4e750228,$007f0004 + dc.l $00687fff,$00004e75,$30280000,$02407fff + dc.l $0c403c00,$67080c40,$43ff67de,$4e7502a8 + dc.l $7fffffff,$00046606,$4aa80008,$67c461ff + dc.l $00002478,$44400640,$3c010268,$80000000 + dc.l $81680000,$4e75e9ee,$00c3ff42,$0c000003 + dc.l $670004a2,$0c000007,$6700049a,$02aeffff + dc.l $00ffff64,$f23c9000,$00000000,$f23c8800 + dc.l $00000000,$302eff6c,$02407fff,$671041ee + dc.l $ff6c61ff,$0000246c,$1d40ff4e,$60061d7c + dc.l $0004ff4e,$4280102e,$ff6341ee,$ff6c2d56 + dc.l $ffd461ff,$0000292a,$102eff62,$66000086 + dc.l $2caeffd4,$082e0005,$00046626,$206effd8 + dc.l $4e60f22e,$d0c0ffdc,$f22e9c00,$ff604cee + dc.l $0303ff9c,$4e5e0817,$0007667a,$60ffffff + dc.l $f7220c2e,$0008ff4a,$66d8f22e,$f080ff6c + dc.l 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$fb9a6008,$f2064000,$f2000018,$f2294820 + dc.l $0018f22e,$6800ff90,$242a0004,$262a0008 + dc.l $3012670e,$04403ffd,$4440e28a,$e29351c8 + dc.l $fffa4281,$06830000,$0080d581,$0283ffff + dc.l $ff807004,$41eeff54,$61ff0000,$0228202e + dc.l $ff54720c,$e2a8efee,$010cff84,$e2a8efee + dc.l $0404ff84,$4a006708,$00ae0000,$2080ff64 + dc.l $4280022e,$000fff84,$4aaeff58,$6c027002 + dc.l $4a866c02,$5280efee,$0002ff84,$f23c8800 + dc.l $00000000,$f21fd0e0,$4cdf04fc,$4e754002 + dc.l $0000a000,$00000000,$00004005,$0000c800 + dc.l $00000000,$0000400c,$00009c40,$00000000 + dc.l $00004019,$0000bebc,$20000000,$00004034 + dc.l $00008e1b,$c9bf0400,$00004069,$00009dc5 + dc.l $ada82b70,$b59e40d3,$0000c278,$1f49ffcf + dc.l $a6d541a8,$000093ba,$47c980e9,$8ce04351 + dc.l $0000aa7e,$ebfb9df9,$de8e46a3,$0000e319 + dc.l $a0aea60e,$91c74d48,$0000c976,$75868175 + dc.l $0c175a92,$00009e8b,$3b5dc53d,$5de57525 + dc.l $0000c460,$52028a20,$979b4002,$0000a000 + dc.l $00000000,$00004005,$0000c800,$00000000 + dc.l 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$4a476712,$4847e947,$de4110c7,$48474247 + dc.l $51c8ffc8,$60124847,$3e014847,$524751c8 + dc.l $ffba4847,$e94f10c7,$4cdf00ff,$4e757001 + dc.l $610000d6,$3d7c0121,$000a6000,$007e7002 + dc.l $610000c6,$3d7c0141,$000a606e,$70046100 + dc.l $00b83d7c,$0101000a,$60607008,$610000aa + dc.l $3d7c0161,$000a6052,$700c6100,$009c3d7c + dc.l $0161000a,$60447001,$6100008e,$3d7c00a1 + dc.l $000a6036,$70026100,$00803d7c,$00c1000a + dc.l $60287004,$61000072,$3d7c0081,$000a601a + dc.l $70086100,$00643d7c,$00e1000a,$600c700c + dc.l $61000056,$3d7c00e1,$000a2d6e,$ff680006 + dc.l $f22ed0c0,$ffdcf22e,$9c00ff60,$4cee0303 + dc.l $ff9c4e5e,$2f172f6f,$00080004,$2f6f000c + dc.l $00082f7c,$00000001,$000c3f6f,$0006000c + dc.l $3f7c4008,$00060817,$00056706,$08ef0002 + dc.l $000d60ff,$ffff95f4,$122eff41,$02010038 + dc.l $0c010018,$6700000c,$0c010020,$67000060 + dc.l $4e75122e,$ff410241,$0007323b,$12064efb + dc.l $10020010,$0016001c,$00200024,$0028002c + dc.l $003091ae,$ffa44e75,$91aeffa8,$4e7595c0 + dc.l $4e7597c0,$4e7599c0,$4e759bc0,$4e759196 + dc.l $4e750c2e,$0030000a,$6612082e,$00050004 + dc.l $660a4e7a,$880091c0,$4e7b8800,$4e754480 + dc.l $60a051fc,$00000000,$00000000,$00000000 diff --git a/arch/m68k/ifpsp060/src/README-SRC b/arch/m68k/ifpsp060/src/README-SRC new file mode 100644 index 000000000..6be5cff2a --- /dev/null +++ b/arch/m68k/ifpsp060/src/README-SRC @@ -0,0 +1,12 @@ +This is the original source code from Motorola for the 68060 processor +support code, providing emulation for rarely used m68k instructions +not implemented in the 68060 silicon. + +The code provided here will not assemble out of the box using the GNU +assembler, however it is being included in order to comply with the +GNU General Public License. + +You don't need to actually assemble these files in order to compile a +workin m68k kernel, the precompiled .sa files in arch/m68k/ifpsp060 +are sufficient and were generated from these source files by +Motorola. diff --git a/arch/m68k/ifpsp060/src/fplsp.S b/arch/m68k/ifpsp060/src/fplsp.S new file mode 100644 index 000000000..3b7ea2dc9 --- /dev/null +++ b/arch/m68k/ifpsp060/src/fplsp.S @@ -0,0 +1,10980 @@ +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +MOTOROLA MICROPROCESSOR & MEMORY TECHNOLOGY GROUP +M68000 Hi-Performance Microprocessor Division +M68060 Software Package +Production Release P1.00 -- October 10, 1994 + +M68060 Software Package Copyright © 1993, 1994 Motorola Inc. All rights reserved. + +THE SOFTWARE is provided on an "AS IS" basis and without warranty. +To the maximum extent permitted by applicable law, +MOTOROLA DISCLAIMS ALL WARRANTIES WHETHER EXPRESS OR IMPLIED, +INCLUDING IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE +and any warranty against infringement with regard to the SOFTWARE +(INCLUDING ANY MODIFIED VERSIONS THEREOF) and any accompanying written materials. + +To the maximum extent permitted by applicable law, +IN NO EVENT SHALL MOTOROLA BE LIABLE FOR ANY DAMAGES WHATSOEVER +(INCLUDING WITHOUT LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, +BUSINESS INTERRUPTION, LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY LOSS) +ARISING OF THE USE OR INABILITY TO USE THE SOFTWARE. +Motorola assumes no responsibility for the maintenance and support of the SOFTWARE. + +You are hereby granted a copyright license to use, modify, and distribute the SOFTWARE +so long as this entire notice is retained without alteration in any modified and/or +redistributed versions, and that such modified versions are clearly identified as such. +No licenses are granted by implication, estoppel or otherwise under any patents +or trademarks of Motorola, Inc. +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +# +# lfptop.s: +# This file is appended to the top of the 060ILSP package +# and contains the entry points into the package. The user, in +# effect, branches to one of the branch table entries located here. +# + + bra.l _facoss_ + short 0x0000 + bra.l _facosd_ + short 0x0000 + bra.l _facosx_ + short 0x0000 + + bra.l _fasins_ + short 0x0000 + bra.l _fasind_ + short 0x0000 + bra.l _fasinx_ + short 0x0000 + + bra.l _fatans_ + short 0x0000 + bra.l _fatand_ + short 0x0000 + bra.l _fatanx_ + short 0x0000 + + bra.l _fatanhs_ + short 0x0000 + bra.l _fatanhd_ + short 0x0000 + bra.l _fatanhx_ + short 0x0000 + + bra.l _fcoss_ + short 0x0000 + bra.l _fcosd_ + short 0x0000 + bra.l _fcosx_ + short 0x0000 + + bra.l _fcoshs_ + short 0x0000 + bra.l _fcoshd_ + short 0x0000 + bra.l _fcoshx_ + short 0x0000 + + bra.l _fetoxs_ + short 0x0000 + bra.l _fetoxd_ + short 0x0000 + bra.l _fetoxx_ + short 0x0000 + + bra.l _fetoxm1s_ + short 0x0000 + bra.l _fetoxm1d_ + short 0x0000 + bra.l _fetoxm1x_ + short 0x0000 + + bra.l _fgetexps_ + short 0x0000 + bra.l _fgetexpd_ + short 0x0000 + bra.l _fgetexpx_ + short 0x0000 + + bra.l _fgetmans_ + short 0x0000 + bra.l _fgetmand_ + short 0x0000 + bra.l _fgetmanx_ + short 0x0000 + + bra.l _flog10s_ + short 0x0000 + bra.l _flog10d_ + short 0x0000 + bra.l _flog10x_ + short 0x0000 + + bra.l _flog2s_ + short 0x0000 + bra.l _flog2d_ + short 0x0000 + bra.l _flog2x_ + short 0x0000 + + bra.l _flogns_ + short 0x0000 + bra.l _flognd_ + short 0x0000 + bra.l _flognx_ + short 0x0000 + + bra.l _flognp1s_ + short 0x0000 + bra.l _flognp1d_ + short 0x0000 + bra.l _flognp1x_ + short 0x0000 + + bra.l _fmods_ + short 0x0000 + bra.l _fmodd_ + short 0x0000 + bra.l _fmodx_ + short 0x0000 + + bra.l _frems_ + short 0x0000 + bra.l _fremd_ + short 0x0000 + bra.l _fremx_ + short 0x0000 + + bra.l _fscales_ + short 0x0000 + bra.l _fscaled_ + short 0x0000 + bra.l _fscalex_ + short 0x0000 + + bra.l _fsins_ + short 0x0000 + bra.l _fsind_ + short 0x0000 + bra.l _fsinx_ + short 0x0000 + + bra.l _fsincoss_ + short 0x0000 + bra.l _fsincosd_ + short 0x0000 + bra.l _fsincosx_ + short 0x0000 + + bra.l _fsinhs_ + short 0x0000 + bra.l _fsinhd_ + short 0x0000 + bra.l _fsinhx_ + short 0x0000 + + bra.l _ftans_ + short 0x0000 + bra.l _ftand_ + short 0x0000 + bra.l _ftanx_ + short 0x0000 + + bra.l _ftanhs_ + short 0x0000 + bra.l _ftanhd_ + short 0x0000 + bra.l _ftanhx_ + short 0x0000 + + bra.l _ftentoxs_ + short 0x0000 + bra.l _ftentoxd_ + short 0x0000 + bra.l _ftentoxx_ + short 0x0000 + + bra.l _ftwotoxs_ + short 0x0000 + bra.l _ftwotoxd_ + short 0x0000 + bra.l _ftwotoxx_ + short 0x0000 + + bra.l _fabss_ + short 0x0000 + bra.l _fabsd_ + short 0x0000 + bra.l _fabsx_ + short 0x0000 + + bra.l _fadds_ + short 0x0000 + bra.l _faddd_ + short 0x0000 + bra.l _faddx_ + short 0x0000 + + bra.l _fdivs_ + short 0x0000 + bra.l _fdivd_ + short 0x0000 + bra.l _fdivx_ + short 0x0000 + + bra.l _fints_ + short 0x0000 + bra.l _fintd_ + short 0x0000 + bra.l _fintx_ + short 0x0000 + + bra.l _fintrzs_ + short 0x0000 + bra.l _fintrzd_ + short 0x0000 + bra.l _fintrzx_ + short 0x0000 + + bra.l _fmuls_ + short 0x0000 + bra.l _fmuld_ + short 0x0000 + bra.l _fmulx_ + short 0x0000 + + bra.l _fnegs_ + short 0x0000 + bra.l _fnegd_ + short 0x0000 + bra.l _fnegx_ + short 0x0000 + + bra.l _fsqrts_ + short 0x0000 + bra.l _fsqrtd_ + short 0x0000 + bra.l _fsqrtx_ + short 0x0000 + + bra.l _fsubs_ + short 0x0000 + bra.l _fsubd_ + short 0x0000 + bra.l _fsubx_ + short 0x0000 + +# leave room for future possible additions + align 0x400 + +# +# This file contains a set of define statements for constants +# in order to promote readability within the corecode itself. +# + +set LOCAL_SIZE, 192 # stack frame size(bytes) +set LV, -LOCAL_SIZE # stack offset + +set EXC_SR, 0x4 # stack status register +set EXC_PC, 0x6 # stack pc +set EXC_VOFF, 0xa # stacked vector offset +set EXC_EA, 0xc # stacked + +set EXC_FP, 0x0 # frame pointer + +set EXC_AREGS, -68 # offset of all address regs +set EXC_DREGS, -100 # offset of all data regs +set EXC_FPREGS, -36 # offset of all fp regs + +set EXC_A7, EXC_AREGS+(7*4) # offset of saved a7 +set OLD_A7, EXC_AREGS+(6*4) # extra copy of saved a7 +set EXC_A6, EXC_AREGS+(6*4) # offset of saved a6 +set EXC_A5, EXC_AREGS+(5*4) +set EXC_A4, EXC_AREGS+(4*4) +set EXC_A3, EXC_AREGS+(3*4) +set EXC_A2, EXC_AREGS+(2*4) +set EXC_A1, EXC_AREGS+(1*4) +set EXC_A0, EXC_AREGS+(0*4) +set EXC_D7, EXC_DREGS+(7*4) +set EXC_D6, EXC_DREGS+(6*4) +set EXC_D5, EXC_DREGS+(5*4) +set EXC_D4, EXC_DREGS+(4*4) +set EXC_D3, EXC_DREGS+(3*4) +set EXC_D2, EXC_DREGS+(2*4) +set EXC_D1, EXC_DREGS+(1*4) +set EXC_D0, EXC_DREGS+(0*4) + +set EXC_FP0, EXC_FPREGS+(0*12) # offset of saved fp0 +set EXC_FP1, EXC_FPREGS+(1*12) # offset of saved fp1 +set EXC_FP2, EXC_FPREGS+(2*12) # offset of saved fp2 (not used) + +set FP_SCR1, LV+80 # fp scratch 1 +set FP_SCR1_EX, FP_SCR1+0 +set FP_SCR1_SGN, FP_SCR1+2 +set FP_SCR1_HI, FP_SCR1+4 +set FP_SCR1_LO, FP_SCR1+8 + +set FP_SCR0, LV+68 # fp scratch 0 +set FP_SCR0_EX, FP_SCR0+0 +set FP_SCR0_SGN, FP_SCR0+2 +set FP_SCR0_HI, FP_SCR0+4 +set FP_SCR0_LO, FP_SCR0+8 + +set FP_DST, LV+56 # fp destination operand +set FP_DST_EX, FP_DST+0 +set FP_DST_SGN, FP_DST+2 +set FP_DST_HI, FP_DST+4 +set FP_DST_LO, FP_DST+8 + +set FP_SRC, LV+44 # fp source operand +set FP_SRC_EX, FP_SRC+0 +set FP_SRC_SGN, FP_SRC+2 +set FP_SRC_HI, FP_SRC+4 +set FP_SRC_LO, FP_SRC+8 + +set USER_FPIAR, LV+40 # FP instr address register + +set USER_FPSR, LV+36 # FP status register +set FPSR_CC, USER_FPSR+0 # FPSR condition codes +set FPSR_QBYTE, USER_FPSR+1 # FPSR qoutient byte +set FPSR_EXCEPT, USER_FPSR+2 # FPSR exception status byte +set FPSR_AEXCEPT, USER_FPSR+3 # FPSR accrued exception byte + +set USER_FPCR, LV+32 # FP control register +set FPCR_ENABLE, USER_FPCR+2 # FPCR exception enable +set FPCR_MODE, USER_FPCR+3 # FPCR rounding mode control + +set L_SCR3, LV+28 # integer scratch 3 +set L_SCR2, LV+24 # integer scratch 2 +set L_SCR1, LV+20 # integer scratch 1 + +set STORE_FLG, LV+19 # flag: operand store (ie. not fcmp/ftst) + +set EXC_TEMP2, LV+24 # temporary space +set EXC_TEMP, LV+16 # temporary space + +set DTAG, LV+15 # destination operand type +set STAG, LV+14 # source operand type + +set SPCOND_FLG, LV+10 # flag: special case (see below) + +set EXC_CC, LV+8 # saved condition codes +set EXC_EXTWPTR, LV+4 # saved current PC (active) +set EXC_EXTWORD, LV+2 # saved extension word +set EXC_CMDREG, LV+2 # saved extension word +set EXC_OPWORD, LV+0 # saved operation word + +################################ + +# Helpful macros + +set FTEMP, 0 # offsets within an +set FTEMP_EX, 0 # extended precision +set FTEMP_SGN, 2 # value saved in memory. +set FTEMP_HI, 4 +set FTEMP_LO, 8 +set FTEMP_GRS, 12 + +set LOCAL, 0 # offsets within an +set LOCAL_EX, 0 # extended precision +set LOCAL_SGN, 2 # value saved in memory. +set LOCAL_HI, 4 +set LOCAL_LO, 8 +set LOCAL_GRS, 12 + +set DST, 0 # offsets within an +set DST_EX, 0 # extended precision +set DST_HI, 4 # value saved in memory. +set DST_LO, 8 + +set SRC, 0 # offsets within an +set SRC_EX, 0 # extended precision +set SRC_HI, 4 # value saved in memory. +set SRC_LO, 8 + +set SGL_LO, 0x3f81 # min sgl prec exponent +set SGL_HI, 0x407e # max sgl prec exponent +set DBL_LO, 0x3c01 # min dbl prec exponent +set DBL_HI, 0x43fe # max dbl prec exponent +set EXT_LO, 0x0 # min ext prec exponent +set EXT_HI, 0x7ffe # max ext prec exponent + +set EXT_BIAS, 0x3fff # extended precision bias +set SGL_BIAS, 0x007f # single precision bias +set DBL_BIAS, 0x03ff # double precision bias + +set NORM, 0x00 # operand type for STAG/DTAG +set ZERO, 0x01 # operand type for STAG/DTAG +set INF, 0x02 # operand type for STAG/DTAG +set QNAN, 0x03 # operand type for STAG/DTAG +set DENORM, 0x04 # operand type for STAG/DTAG +set SNAN, 0x05 # operand type for STAG/DTAG +set UNNORM, 0x06 # operand type for STAG/DTAG + +################## +# FPSR/FPCR bits # +################## +set neg_bit, 0x3 # negative result +set z_bit, 0x2 # zero result +set inf_bit, 0x1 # infinite result +set nan_bit, 0x0 # NAN result + +set q_sn_bit, 0x7 # sign bit of quotient byte + +set bsun_bit, 7 # branch on unordered +set snan_bit, 6 # signalling NAN +set operr_bit, 5 # operand error +set ovfl_bit, 4 # overflow +set unfl_bit, 3 # underflow +set dz_bit, 2 # divide by zero +set inex2_bit, 1 # inexact result 2 +set inex1_bit, 0 # inexact result 1 + +set aiop_bit, 7 # accrued inexact operation bit +set aovfl_bit, 6 # accrued overflow bit +set aunfl_bit, 5 # accrued underflow bit +set adz_bit, 4 # accrued dz bit +set ainex_bit, 3 # accrued inexact bit + +############################# +# FPSR individual bit masks # +############################# +set neg_mask, 0x08000000 # negative bit mask (lw) +set inf_mask, 0x02000000 # infinity bit mask (lw) +set z_mask, 0x04000000 # zero bit mask (lw) +set nan_mask, 0x01000000 # nan bit mask (lw) + +set neg_bmask, 0x08 # negative bit mask (byte) +set inf_bmask, 0x02 # infinity bit mask (byte) +set z_bmask, 0x04 # zero bit mask (byte) +set nan_bmask, 0x01 # nan bit mask (byte) + +set bsun_mask, 0x00008000 # bsun exception mask +set snan_mask, 0x00004000 # snan exception mask +set operr_mask, 0x00002000 # operr exception mask +set ovfl_mask, 0x00001000 # overflow exception mask +set unfl_mask, 0x00000800 # underflow exception mask +set dz_mask, 0x00000400 # dz exception mask +set inex2_mask, 0x00000200 # inex2 exception mask +set inex1_mask, 0x00000100 # inex1 exception mask + +set aiop_mask, 0x00000080 # accrued illegal operation +set aovfl_mask, 0x00000040 # accrued overflow +set aunfl_mask, 0x00000020 # accrued underflow +set adz_mask, 0x00000010 # accrued divide by zero +set ainex_mask, 0x00000008 # accrued inexact + +###################################### +# FPSR combinations used in the FPSP # +###################################### +set dzinf_mask, inf_mask+dz_mask+adz_mask +set opnan_mask, nan_mask+operr_mask+aiop_mask +set nzi_mask, 0x01ffffff #clears N, Z, and I +set unfinx_mask, unfl_mask+inex2_mask+aunfl_mask+ainex_mask +set unf2inx_mask, unfl_mask+inex2_mask+ainex_mask +set ovfinx_mask, ovfl_mask+inex2_mask+aovfl_mask+ainex_mask +set inx1a_mask, inex1_mask+ainex_mask +set inx2a_mask, inex2_mask+ainex_mask +set snaniop_mask, nan_mask+snan_mask+aiop_mask +set snaniop2_mask, snan_mask+aiop_mask +set naniop_mask, nan_mask+aiop_mask +set neginf_mask, neg_mask+inf_mask +set infaiop_mask, inf_mask+aiop_mask +set negz_mask, neg_mask+z_mask +set opaop_mask, operr_mask+aiop_mask +set unfl_inx_mask, unfl_mask+aunfl_mask+ainex_mask +set ovfl_inx_mask, ovfl_mask+aovfl_mask+ainex_mask + +######### +# misc. # +######### +set rnd_stky_bit, 29 # stky bit pos in longword + +set sign_bit, 0x7 # sign bit +set signan_bit, 0x6 # signalling nan bit + +set sgl_thresh, 0x3f81 # minimum sgl exponent +set dbl_thresh, 0x3c01 # minimum dbl exponent + +set x_mode, 0x0 # extended precision +set s_mode, 0x4 # single precision +set d_mode, 0x8 # double precision + +set rn_mode, 0x0 # round-to-nearest +set rz_mode, 0x1 # round-to-zero +set rm_mode, 0x2 # round-tp-minus-infinity +set rp_mode, 0x3 # round-to-plus-infinity + +set mantissalen, 64 # length of mantissa in bits + +set BYTE, 1 # len(byte) == 1 byte +set WORD, 2 # len(word) == 2 bytes +set LONG, 4 # len(longword) == 2 bytes + +set BSUN_VEC, 0xc0 # bsun vector offset +set INEX_VEC, 0xc4 # inexact vector offset +set DZ_VEC, 0xc8 # dz vector offset +set UNFL_VEC, 0xcc # unfl vector offset +set OPERR_VEC, 0xd0 # operr vector offset +set OVFL_VEC, 0xd4 # ovfl vector offset +set SNAN_VEC, 0xd8 # snan vector offset + +########################### +# SPecial CONDition FLaGs # +########################### +set ftrapcc_flg, 0x01 # flag bit: ftrapcc exception +set fbsun_flg, 0x02 # flag bit: bsun exception +set mia7_flg, 0x04 # flag bit: (a7)+ +set mda7_flg, 0x08 # flag bit: -(a7) +set fmovm_flg, 0x40 # flag bit: fmovm instruction +set immed_flg, 0x80 # flag bit: & + +set ftrapcc_bit, 0x0 +set fbsun_bit, 0x1 +set mia7_bit, 0x2 +set mda7_bit, 0x3 +set immed_bit, 0x7 + +################################## +# TRANSCENDENTAL "LAST-OP" FLAGS # +################################## +set FMUL_OP, 0x0 # fmul instr performed last +set FDIV_OP, 0x1 # fdiv performed last +set FADD_OP, 0x2 # fadd performed last +set FMOV_OP, 0x3 # fmov performed last + +############# +# CONSTANTS # +############# +T1: long 0x40C62D38,0xD3D64634 # 16381 LOG2 LEAD +T2: long 0x3D6F90AE,0xB1E75CC7 # 16381 LOG2 TRAIL + +PI: long 0x40000000,0xC90FDAA2,0x2168C235,0x00000000 +PIBY2: long 0x3FFF0000,0xC90FDAA2,0x2168C235,0x00000000 + +TWOBYPI: + long 0x3FE45F30,0x6DC9C883 + +######################################################################### +# MONADIC TEMPLATE # +######################################################################### + global _fsins_ +_fsins_: + link %a6,&-LOCAL_SIZE + + movm.l &0x0303,EXC_DREGS(%a6) # save d0-d1/a0-a1 + fmovm.l %fpcr,%fpsr,USER_FPCR(%a6) # save ctrl regs + fmovm.x &0xc0,EXC_FP0(%a6) # save fp0/fp1 + + fmov.l &0x0,%fpcr # zero FPCR + +# +# copy, convert, and tag input argument +# + fmov.s 0x8(%a6),%fp0 # load sgl input + fmov.x %fp0,FP_SRC(%a6) + lea FP_SRC(%a6),%a0 + bsr.l tag # fetch operand type + mov.b %d0,STAG(%a6) + mov.b %d0,%d1 + + andi.l &0x00ff00ff,USER_FPSR(%a6) + + clr.l %d0 + mov.b FPCR_MODE(%a6),%d0 # pass rnd mode,prec + + tst.b %d1 + bne.b _L0_2s + bsr.l ssin # operand is a NORM + bra.b _L0_6s +_L0_2s: + cmpi.b %d1,&ZERO # is operand a ZERO? + bne.b _L0_3s # no + bsr.l src_zero # yes + bra.b _L0_6s +_L0_3s: + cmpi.b %d1,&INF # is operand an INF? + bne.b _L0_4s # no + bsr.l t_operr # yes + bra.b _L0_6s +_L0_4s: + cmpi.b %d1,&QNAN # is operand a QNAN? + bne.b _L0_5s # no + bsr.l src_qnan # yes + bra.b _L0_6s +_L0_5s: + bsr.l ssind # operand is a DENORM +_L0_6s: + +# +# Result is now in FP0 +# + movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 + fmovm.l USER_FPCR(%a6),%fpcr,%fpsr # restore ctrl regs + fmovm.x EXC_FP1(%a6),&0x40 # restore fp1 + unlk %a6 + rts + + global _fsind_ +_fsind_: + link %a6,&-LOCAL_SIZE + + movm.l &0x0303,EXC_DREGS(%a6) # save d0-d1/a0-a1 + fmovm.l %fpcr,%fpsr,USER_FPCR(%a6) # save ctrl regs + fmovm.x &0xc0,EXC_FP0(%a6) # save fp0/fp1 + + fmov.l &0x0,%fpcr # zero FPCR + +# +# copy, convert, and tag input argument +# + fmov.d 0x8(%a6),%fp0 # load dbl input + fmov.x %fp0,FP_SRC(%a6) + lea FP_SRC(%a6),%a0 + bsr.l tag # fetch operand type + mov.b %d0,STAG(%a6) + mov.b %d0,%d1 + + andi.l &0x00ff00ff,USER_FPSR(%a6) + + clr.l %d0 + mov.b FPCR_MODE(%a6),%d0 # pass rnd mode,prec + + mov.b %d1,STAG(%a6) + tst.b %d1 + bne.b _L0_2d + bsr.l ssin # operand is a NORM + bra.b _L0_6d +_L0_2d: + cmpi.b %d1,&ZERO # is operand a ZERO? + bne.b _L0_3d # no + bsr.l src_zero # yes + bra.b _L0_6d +_L0_3d: + cmpi.b %d1,&INF # is operand an INF? + bne.b _L0_4d # no + bsr.l t_operr # yes + bra.b _L0_6d +_L0_4d: + cmpi.b %d1,&QNAN # is operand a QNAN? + bne.b _L0_5d # no + bsr.l src_qnan # yes + bra.b _L0_6d +_L0_5d: + bsr.l ssind # operand is a DENORM +_L0_6d: + +# +# Result is now in FP0 +# + movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 + fmovm.l USER_FPCR(%a6),%fpcr,%fpsr # restore ctrl regs + fmovm.x EXC_FP1(%a6),&0x40 # restore fp1 + unlk %a6 + rts + + global _fsinx_ +_fsinx_: + link %a6,&-LOCAL_SIZE + + movm.l &0x0303,EXC_DREGS(%a6) # save d0-d1/a0-a1 + fmovm.l %fpcr,%fpsr,USER_FPCR(%a6) # save ctrl regs + fmovm.x &0xc0,EXC_FP0(%a6) # save fp0/fp1 + + fmov.l &0x0,%fpcr # zero FPCR + +# +# copy, convert, and tag input argument +# + lea FP_SRC(%a6),%a0 + mov.l 0x8+0x0(%a6),0x0(%a0) # load ext input + mov.l 0x8+0x4(%a6),0x4(%a0) + mov.l 0x8+0x8(%a6),0x8(%a0) + bsr.l tag # fetch operand type + mov.b %d0,STAG(%a6) + mov.b %d0,%d1 + + andi.l &0x00ff00ff,USER_FPSR(%a6) + + clr.l %d0 + mov.b FPCR_MODE(%a6),%d0 # pass rnd mode,prec + + tst.b %d1 + bne.b _L0_2x + bsr.l ssin # operand is a NORM + bra.b _L0_6x +_L0_2x: + cmpi.b %d1,&ZERO # is operand a ZERO? + bne.b _L0_3x # no + bsr.l src_zero # yes + bra.b _L0_6x +_L0_3x: + cmpi.b %d1,&INF # is operand an INF? + bne.b _L0_4x # no + bsr.l t_operr # yes + bra.b _L0_6x +_L0_4x: + cmpi.b %d1,&QNAN # is operand a QNAN? + bne.b _L0_5x # no + bsr.l src_qnan # yes + bra.b _L0_6x +_L0_5x: + bsr.l ssind # operand is a DENORM +_L0_6x: + +# +# Result is now in FP0 +# + movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 + fmovm.l USER_FPCR(%a6),%fpcr,%fpsr # restore ctrl regs + fmovm.x EXC_FP1(%a6),&0x40 # restore fp1 + unlk %a6 + rts + + +######################################################################### +# MONADIC TEMPLATE # +######################################################################### + global _fcoss_ +_fcoss_: + link %a6,&-LOCAL_SIZE + + movm.l &0x0303,EXC_DREGS(%a6) # save d0-d1/a0-a1 + fmovm.l %fpcr,%fpsr,USER_FPCR(%a6) # save ctrl regs + fmovm.x &0xc0,EXC_FP0(%a6) # save fp0/fp1 + + fmov.l &0x0,%fpcr # zero FPCR + +# +# copy, convert, and tag input argument +# + fmov.s 0x8(%a6),%fp0 # load sgl input + fmov.x %fp0,FP_SRC(%a6) + lea FP_SRC(%a6),%a0 + bsr.l tag # fetch operand type + mov.b %d0,STAG(%a6) + mov.b %d0,%d1 + + andi.l &0x00ff00ff,USER_FPSR(%a6) + + clr.l %d0 + mov.b FPCR_MODE(%a6),%d0 # pass rnd mode,prec + + tst.b %d1 + bne.b _L1_2s + bsr.l scos # operand is a NORM + bra.b _L1_6s +_L1_2s: + cmpi.b %d1,&ZERO # is operand a ZERO? + bne.b _L1_3s # no + bsr.l ld_pone # yes + bra.b _L1_6s +_L1_3s: + cmpi.b %d1,&INF # is operand an INF? + bne.b _L1_4s # no + bsr.l t_operr # yes + bra.b _L1_6s +_L1_4s: + cmpi.b %d1,&QNAN # is operand a QNAN? + bne.b _L1_5s # no + bsr.l src_qnan # yes + bra.b _L1_6s +_L1_5s: + bsr.l scosd # operand is a DENORM +_L1_6s: + +# +# Result is now in FP0 +# + movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 + fmovm.l USER_FPCR(%a6),%fpcr,%fpsr # restore ctrl regs + fmovm.x EXC_FP1(%a6),&0x40 # restore fp1 + unlk %a6 + rts + + global _fcosd_ +_fcosd_: + link %a6,&-LOCAL_SIZE + + movm.l &0x0303,EXC_DREGS(%a6) # save d0-d1/a0-a1 + fmovm.l %fpcr,%fpsr,USER_FPCR(%a6) # save ctrl regs + fmovm.x &0xc0,EXC_FP0(%a6) # save fp0/fp1 + + fmov.l &0x0,%fpcr # zero FPCR + +# +# copy, convert, and tag input argument +# + fmov.d 0x8(%a6),%fp0 # load dbl input + fmov.x %fp0,FP_SRC(%a6) + lea FP_SRC(%a6),%a0 + bsr.l tag # fetch operand type + mov.b %d0,STAG(%a6) + mov.b %d0,%d1 + + andi.l &0x00ff00ff,USER_FPSR(%a6) + + clr.l %d0 + mov.b FPCR_MODE(%a6),%d0 # pass rnd mode,prec + + mov.b %d1,STAG(%a6) + tst.b %d1 + bne.b _L1_2d + bsr.l scos # operand is a NORM + bra.b _L1_6d +_L1_2d: + cmpi.b %d1,&ZERO # is operand a ZERO? + bne.b _L1_3d # no + bsr.l ld_pone # yes + bra.b _L1_6d +_L1_3d: + cmpi.b %d1,&INF # is operand an INF? + bne.b _L1_4d # no + bsr.l t_operr # yes + bra.b _L1_6d +_L1_4d: + cmpi.b %d1,&QNAN # is operand a QNAN? + bne.b _L1_5d # no + bsr.l src_qnan # yes + bra.b _L1_6d +_L1_5d: + bsr.l scosd # operand is a DENORM +_L1_6d: + +# +# Result is now in FP0 +# + movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 + fmovm.l USER_FPCR(%a6),%fpcr,%fpsr # restore ctrl regs + fmovm.x EXC_FP1(%a6),&0x40 # restore fp1 + unlk %a6 + rts + + global _fcosx_ +_fcosx_: + link %a6,&-LOCAL_SIZE + + movm.l &0x0303,EXC_DREGS(%a6) # save d0-d1/a0-a1 + fmovm.l %fpcr,%fpsr,USER_FPCR(%a6) # save ctrl regs + fmovm.x &0xc0,EXC_FP0(%a6) # save fp0/fp1 + + fmov.l &0x0,%fpcr # zero FPCR + +# +# copy, convert, and tag input argument +# + lea FP_SRC(%a6),%a0 + mov.l 0x8+0x0(%a6),0x0(%a0) # load ext input + mov.l 0x8+0x4(%a6),0x4(%a0) + mov.l 0x8+0x8(%a6),0x8(%a0) + bsr.l tag # fetch operand type + mov.b %d0,STAG(%a6) + mov.b %d0,%d1 + + andi.l &0x00ff00ff,USER_FPSR(%a6) + + clr.l %d0 + mov.b FPCR_MODE(%a6),%d0 # pass rnd mode,prec + + tst.b %d1 + bne.b _L1_2x + bsr.l scos # operand is a NORM + bra.b _L1_6x +_L1_2x: + cmpi.b %d1,&ZERO # is operand a ZERO? + bne.b _L1_3x # no + bsr.l ld_pone # yes + bra.b _L1_6x +_L1_3x: + cmpi.b %d1,&INF # is operand an INF? + bne.b _L1_4x # no + bsr.l t_operr # yes + bra.b _L1_6x +_L1_4x: + cmpi.b %d1,&QNAN # is operand a QNAN? + bne.b _L1_5x # no + bsr.l src_qnan # yes + bra.b _L1_6x +_L1_5x: + bsr.l scosd # operand is a DENORM +_L1_6x: + +# +# Result is now in FP0 +# + movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 + fmovm.l USER_FPCR(%a6),%fpcr,%fpsr # restore ctrl regs + fmovm.x EXC_FP1(%a6),&0x40 # restore fp1 + unlk %a6 + rts + + +######################################################################### +# MONADIC TEMPLATE # +######################################################################### + global _fsinhs_ +_fsinhs_: + link %a6,&-LOCAL_SIZE + + movm.l &0x0303,EXC_DREGS(%a6) # save d0-d1/a0-a1 + fmovm.l %fpcr,%fpsr,USER_FPCR(%a6) # save ctrl regs + fmovm.x &0xc0,EXC_FP0(%a6) # save fp0/fp1 + + fmov.l &0x0,%fpcr # zero FPCR + +# +# copy, convert, and tag input argument +# + fmov.s 0x8(%a6),%fp0 # load sgl input + fmov.x %fp0,FP_SRC(%a6) + lea FP_SRC(%a6),%a0 + bsr.l tag # fetch operand type + mov.b %d0,STAG(%a6) + mov.b %d0,%d1 + + andi.l &0x00ff00ff,USER_FPSR(%a6) + + clr.l %d0 + mov.b FPCR_MODE(%a6),%d0 # pass rnd mode,prec + + tst.b %d1 + bne.b _L2_2s + bsr.l ssinh # operand is a NORM + bra.b _L2_6s +_L2_2s: + cmpi.b %d1,&ZERO # is operand a ZERO? + bne.b _L2_3s # no + bsr.l src_zero # yes + bra.b _L2_6s +_L2_3s: + cmpi.b %d1,&INF # is operand an INF? + bne.b _L2_4s # no + bsr.l src_inf # yes + bra.b _L2_6s +_L2_4s: + cmpi.b %d1,&QNAN # is operand a QNAN? + bne.b _L2_5s # no + bsr.l src_qnan # yes + bra.b _L2_6s +_L2_5s: + bsr.l ssinhd # operand is a DENORM +_L2_6s: + +# +# Result is now in FP0 +# + movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 + fmovm.l USER_FPCR(%a6),%fpcr,%fpsr # restore ctrl regs + fmovm.x EXC_FP1(%a6),&0x40 # restore fp1 + unlk %a6 + rts + + global _fsinhd_ +_fsinhd_: + link %a6,&-LOCAL_SIZE + + movm.l &0x0303,EXC_DREGS(%a6) # save d0-d1/a0-a1 + fmovm.l %fpcr,%fpsr,USER_FPCR(%a6) # save ctrl regs + fmovm.x &0xc0,EXC_FP0(%a6) # save fp0/fp1 + + fmov.l &0x0,%fpcr # zero FPCR + +# +# copy, convert, and tag input argument +# + fmov.d 0x8(%a6),%fp0 # load dbl input + fmov.x %fp0,FP_SRC(%a6) + lea FP_SRC(%a6),%a0 + bsr.l tag # fetch operand type + mov.b %d0,STAG(%a6) + mov.b %d0,%d1 + + andi.l &0x00ff00ff,USER_FPSR(%a6) + + clr.l %d0 + mov.b FPCR_MODE(%a6),%d0 # pass rnd mode,prec + + mov.b %d1,STAG(%a6) + tst.b %d1 + bne.b _L2_2d + bsr.l ssinh # operand is a NORM + bra.b _L2_6d +_L2_2d: + cmpi.b %d1,&ZERO # is operand a ZERO? + bne.b _L2_3d # no + bsr.l src_zero # yes + bra.b _L2_6d +_L2_3d: + cmpi.b %d1,&INF # is operand an INF? + bne.b _L2_4d # no + bsr.l src_inf # yes + bra.b _L2_6d +_L2_4d: + cmpi.b %d1,&QNAN # is operand a QNAN? + bne.b _L2_5d # no + bsr.l src_qnan # yes + bra.b _L2_6d +_L2_5d: + bsr.l ssinhd # operand is a DENORM +_L2_6d: + +# +# Result is now in FP0 +# + movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 + fmovm.l USER_FPCR(%a6),%fpcr,%fpsr # restore ctrl regs + fmovm.x EXC_FP1(%a6),&0x40 # restore fp1 + unlk %a6 + rts + + global _fsinhx_ +_fsinhx_: + link %a6,&-LOCAL_SIZE + + movm.l &0x0303,EXC_DREGS(%a6) # save d0-d1/a0-a1 + fmovm.l %fpcr,%fpsr,USER_FPCR(%a6) # save ctrl regs + fmovm.x &0xc0,EXC_FP0(%a6) # save fp0/fp1 + + fmov.l &0x0,%fpcr # zero FPCR + +# +# copy, convert, and tag input argument +# + lea FP_SRC(%a6),%a0 + mov.l 0x8+0x0(%a6),0x0(%a0) # load ext input + mov.l 0x8+0x4(%a6),0x4(%a0) + mov.l 0x8+0x8(%a6),0x8(%a0) + bsr.l tag # fetch operand type + mov.b %d0,STAG(%a6) + mov.b %d0,%d1 + + andi.l &0x00ff00ff,USER_FPSR(%a6) + + clr.l %d0 + mov.b FPCR_MODE(%a6),%d0 # pass rnd mode,prec + + tst.b %d1 + bne.b _L2_2x + bsr.l ssinh # operand is a NORM + bra.b _L2_6x +_L2_2x: + cmpi.b %d1,&ZERO # is operand a ZERO? + bne.b _L2_3x # no + bsr.l src_zero # yes + bra.b _L2_6x +_L2_3x: + cmpi.b %d1,&INF # is operand an INF? + bne.b _L2_4x # no + bsr.l src_inf # yes + bra.b _L2_6x +_L2_4x: + cmpi.b %d1,&QNAN # is operand a QNAN? + bne.b _L2_5x # no + bsr.l src_qnan # yes + bra.b _L2_6x +_L2_5x: + bsr.l ssinhd # operand is a DENORM +_L2_6x: + +# +# Result is now in FP0 +# + movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 + fmovm.l USER_FPCR(%a6),%fpcr,%fpsr # restore ctrl regs + fmovm.x EXC_FP1(%a6),&0x40 # restore fp1 + unlk %a6 + rts + + +######################################################################### +# MONADIC TEMPLATE # +######################################################################### + global _flognp1s_ +_flognp1s_: + link %a6,&-LOCAL_SIZE + + movm.l &0x0303,EXC_DREGS(%a6) # save d0-d1/a0-a1 + fmovm.l %fpcr,%fpsr,USER_FPCR(%a6) # save ctrl regs + fmovm.x &0xc0,EXC_FP0(%a6) # save fp0/fp1 + + fmov.l &0x0,%fpcr # zero FPCR + +# +# copy, convert, and tag input argument +# + fmov.s 0x8(%a6),%fp0 # load sgl input + fmov.x %fp0,FP_SRC(%a6) + lea FP_SRC(%a6),%a0 + bsr.l tag # fetch operand type + mov.b %d0,STAG(%a6) + mov.b %d0,%d1 + + andi.l &0x00ff00ff,USER_FPSR(%a6) + + clr.l %d0 + mov.b FPCR_MODE(%a6),%d0 # pass rnd mode,prec + + tst.b %d1 + bne.b _L3_2s + bsr.l slognp1 # operand is a NORM + bra.b _L3_6s +_L3_2s: + cmpi.b %d1,&ZERO # is operand a ZERO? + bne.b _L3_3s # no + bsr.l src_zero # yes + bra.b _L3_6s +_L3_3s: + cmpi.b %d1,&INF # is operand an INF? + bne.b _L3_4s # no + bsr.l sopr_inf # yes + bra.b _L3_6s +_L3_4s: + cmpi.b %d1,&QNAN # is operand a QNAN? + bne.b _L3_5s # no + bsr.l src_qnan # yes + bra.b _L3_6s +_L3_5s: + bsr.l slognp1d # operand is a DENORM +_L3_6s: + +# +# Result is now in FP0 +# + movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 + fmovm.l USER_FPCR(%a6),%fpcr,%fpsr # restore ctrl regs + fmovm.x EXC_FP1(%a6),&0x40 # restore fp1 + unlk %a6 + rts + + global _flognp1d_ +_flognp1d_: + link %a6,&-LOCAL_SIZE + + movm.l &0x0303,EXC_DREGS(%a6) # save d0-d1/a0-a1 + fmovm.l %fpcr,%fpsr,USER_FPCR(%a6) # save ctrl regs + fmovm.x &0xc0,EXC_FP0(%a6) # save fp0/fp1 + + fmov.l &0x0,%fpcr # zero FPCR + +# +# copy, convert, and tag input argument +# + fmov.d 0x8(%a6),%fp0 # load dbl input + fmov.x %fp0,FP_SRC(%a6) + lea FP_SRC(%a6),%a0 + bsr.l tag # fetch operand type + mov.b %d0,STAG(%a6) + mov.b %d0,%d1 + + andi.l &0x00ff00ff,USER_FPSR(%a6) + + clr.l %d0 + mov.b FPCR_MODE(%a6),%d0 # pass rnd mode,prec + + mov.b %d1,STAG(%a6) + tst.b %d1 + bne.b _L3_2d + bsr.l slognp1 # operand is a NORM + bra.b _L3_6d +_L3_2d: + cmpi.b %d1,&ZERO # is operand a ZERO? + bne.b _L3_3d # no + bsr.l src_zero # yes + bra.b _L3_6d +_L3_3d: + cmpi.b %d1,&INF # is operand an INF? + bne.b _L3_4d # no + bsr.l sopr_inf # yes + bra.b _L3_6d +_L3_4d: + cmpi.b %d1,&QNAN # is operand a QNAN? + bne.b _L3_5d # no + bsr.l src_qnan # yes + bra.b _L3_6d +_L3_5d: + bsr.l slognp1d # operand is a DENORM +_L3_6d: + +# +# Result is now in FP0 +# + movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 + fmovm.l USER_FPCR(%a6),%fpcr,%fpsr # restore ctrl regs + fmovm.x EXC_FP1(%a6),&0x40 # restore fp1 + unlk %a6 + rts + + global _flognp1x_ +_flognp1x_: + link %a6,&-LOCAL_SIZE + + movm.l &0x0303,EXC_DREGS(%a6) # save d0-d1/a0-a1 + fmovm.l %fpcr,%fpsr,USER_FPCR(%a6) # save ctrl regs + fmovm.x &0xc0,EXC_FP0(%a6) # save fp0/fp1 + + fmov.l &0x0,%fpcr # zero FPCR + +# +# copy, convert, and tag input argument +# + lea FP_SRC(%a6),%a0 + mov.l 0x8+0x0(%a6),0x0(%a0) # load ext input + mov.l 0x8+0x4(%a6),0x4(%a0) + mov.l 0x8+0x8(%a6),0x8(%a0) + bsr.l tag # fetch operand type + mov.b %d0,STAG(%a6) + mov.b %d0,%d1 + + andi.l &0x00ff00ff,USER_FPSR(%a6) + + clr.l %d0 + mov.b FPCR_MODE(%a6),%d0 # pass rnd mode,prec + + tst.b %d1 + bne.b _L3_2x + bsr.l slognp1 # operand is a NORM + bra.b _L3_6x +_L3_2x: + cmpi.b %d1,&ZERO # is operand a ZERO? + bne.b _L3_3x # no + bsr.l src_zero # yes + bra.b _L3_6x +_L3_3x: + cmpi.b %d1,&INF # is operand an INF? + bne.b _L3_4x # no + bsr.l sopr_inf # yes + bra.b _L3_6x +_L3_4x: + cmpi.b %d1,&QNAN # is operand a QNAN? + bne.b _L3_5x # no + bsr.l src_qnan # yes + bra.b _L3_6x +_L3_5x: + bsr.l slognp1d # operand is a DENORM +_L3_6x: + +# +# Result is now in FP0 +# + movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 + fmovm.l USER_FPCR(%a6),%fpcr,%fpsr # restore ctrl regs + fmovm.x EXC_FP1(%a6),&0x40 # restore fp1 + unlk %a6 + rts + + +######################################################################### +# MONADIC TEMPLATE # +######################################################################### + global _fetoxm1s_ +_fetoxm1s_: + link %a6,&-LOCAL_SIZE + + movm.l &0x0303,EXC_DREGS(%a6) # save d0-d1/a0-a1 + fmovm.l %fpcr,%fpsr,USER_FPCR(%a6) # save ctrl regs + fmovm.x &0xc0,EXC_FP0(%a6) # save fp0/fp1 + + fmov.l &0x0,%fpcr # zero FPCR + +# +# copy, convert, and tag input argument +# + fmov.s 0x8(%a6),%fp0 # load sgl input + fmov.x %fp0,FP_SRC(%a6) + lea FP_SRC(%a6),%a0 + bsr.l tag # fetch operand type + mov.b %d0,STAG(%a6) + mov.b %d0,%d1 + + andi.l &0x00ff00ff,USER_FPSR(%a6) + + clr.l %d0 + mov.b FPCR_MODE(%a6),%d0 # pass rnd mode,prec + + tst.b %d1 + bne.b _L4_2s + bsr.l setoxm1 # operand is a NORM + bra.b _L4_6s +_L4_2s: + cmpi.b %d1,&ZERO # is operand a ZERO? + bne.b _L4_3s # no + bsr.l src_zero # yes + bra.b _L4_6s +_L4_3s: + cmpi.b %d1,&INF # is operand an INF? + bne.b _L4_4s # no + bsr.l setoxm1i # yes + bra.b _L4_6s +_L4_4s: + cmpi.b %d1,&QNAN # is operand a QNAN? + bne.b _L4_5s # no + bsr.l src_qnan # yes + bra.b _L4_6s +_L4_5s: + bsr.l setoxm1d # operand is a DENORM +_L4_6s: + +# +# Result is now in FP0 +# + movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 + fmovm.l USER_FPCR(%a6),%fpcr,%fpsr # restore ctrl regs + fmovm.x EXC_FP1(%a6),&0x40 # restore fp1 + unlk %a6 + rts + + global _fetoxm1d_ +_fetoxm1d_: + link %a6,&-LOCAL_SIZE + + movm.l &0x0303,EXC_DREGS(%a6) # save d0-d1/a0-a1 + fmovm.l %fpcr,%fpsr,USER_FPCR(%a6) # save ctrl regs + fmovm.x &0xc0,EXC_FP0(%a6) # save fp0/fp1 + + fmov.l &0x0,%fpcr # zero FPCR + +# +# copy, convert, and tag input argument +# + fmov.d 0x8(%a6),%fp0 # load dbl input + fmov.x %fp0,FP_SRC(%a6) + lea FP_SRC(%a6),%a0 + bsr.l tag # fetch operand type + mov.b %d0,STAG(%a6) + mov.b %d0,%d1 + + andi.l &0x00ff00ff,USER_FPSR(%a6) + + clr.l %d0 + mov.b FPCR_MODE(%a6),%d0 # pass rnd mode,prec + + mov.b %d1,STAG(%a6) + tst.b %d1 + bne.b _L4_2d + bsr.l setoxm1 # operand is a NORM + bra.b _L4_6d +_L4_2d: + cmpi.b %d1,&ZERO # is operand a ZERO? + bne.b _L4_3d # no + bsr.l src_zero # yes + bra.b _L4_6d +_L4_3d: + cmpi.b %d1,&INF # is operand an INF? + bne.b _L4_4d # no + bsr.l setoxm1i # yes + bra.b _L4_6d +_L4_4d: + cmpi.b %d1,&QNAN # is operand a QNAN? + bne.b _L4_5d # no + bsr.l src_qnan # yes + bra.b _L4_6d +_L4_5d: + bsr.l setoxm1d # operand is a DENORM +_L4_6d: + +# +# Result is now in FP0 +# + movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 + fmovm.l USER_FPCR(%a6),%fpcr,%fpsr # restore ctrl regs + fmovm.x EXC_FP1(%a6),&0x40 # restore fp1 + unlk %a6 + rts + + global _fetoxm1x_ +_fetoxm1x_: + link %a6,&-LOCAL_SIZE + + movm.l &0x0303,EXC_DREGS(%a6) # save d0-d1/a0-a1 + fmovm.l %fpcr,%fpsr,USER_FPCR(%a6) # save ctrl regs + fmovm.x &0xc0,EXC_FP0(%a6) # save fp0/fp1 + + fmov.l &0x0,%fpcr # zero FPCR + +# +# copy, convert, and tag input argument +# + lea FP_SRC(%a6),%a0 + mov.l 0x8+0x0(%a6),0x0(%a0) # load ext input + mov.l 0x8+0x4(%a6),0x4(%a0) + mov.l 0x8+0x8(%a6),0x8(%a0) + bsr.l tag # fetch operand type + mov.b %d0,STAG(%a6) + mov.b %d0,%d1 + + andi.l &0x00ff00ff,USER_FPSR(%a6) + + clr.l %d0 + mov.b FPCR_MODE(%a6),%d0 # pass rnd mode,prec + + tst.b %d1 + bne.b _L4_2x + bsr.l setoxm1 # operand is a NORM + bra.b _L4_6x +_L4_2x: + cmpi.b %d1,&ZERO # is operand a ZERO? + bne.b _L4_3x # no + bsr.l src_zero # yes + bra.b _L4_6x +_L4_3x: + cmpi.b %d1,&INF # is operand an INF? + bne.b _L4_4x # no + bsr.l setoxm1i # yes + bra.b _L4_6x +_L4_4x: + cmpi.b %d1,&QNAN # is operand a QNAN? + bne.b _L4_5x # no + bsr.l src_qnan # yes + bra.b _L4_6x +_L4_5x: + bsr.l setoxm1d # operand is a DENORM +_L4_6x: + +# +# Result is now in FP0 +# + movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 + fmovm.l USER_FPCR(%a6),%fpcr,%fpsr # restore ctrl regs + fmovm.x EXC_FP1(%a6),&0x40 # restore fp1 + unlk %a6 + rts + + +######################################################################### +# MONADIC TEMPLATE # +######################################################################### + global _ftanhs_ +_ftanhs_: + link %a6,&-LOCAL_SIZE + + movm.l &0x0303,EXC_DREGS(%a6) # save d0-d1/a0-a1 + fmovm.l %fpcr,%fpsr,USER_FPCR(%a6) # save ctrl regs + fmovm.x &0xc0,EXC_FP0(%a6) # save fp0/fp1 + + fmov.l &0x0,%fpcr # zero FPCR + +# +# copy, convert, and tag input argument +# + fmov.s 0x8(%a6),%fp0 # load sgl input + fmov.x %fp0,FP_SRC(%a6) + lea FP_SRC(%a6),%a0 + bsr.l tag # fetch operand type + mov.b %d0,STAG(%a6) + mov.b %d0,%d1 + + andi.l &0x00ff00ff,USER_FPSR(%a6) + + clr.l %d0 + mov.b FPCR_MODE(%a6),%d0 # pass rnd mode,prec + + tst.b %d1 + bne.b _L5_2s + bsr.l stanh # operand is a NORM + bra.b _L5_6s +_L5_2s: + cmpi.b %d1,&ZERO # is operand a ZERO? + bne.b _L5_3s # no + bsr.l src_zero # yes + bra.b _L5_6s +_L5_3s: + cmpi.b %d1,&INF # is operand an INF? + bne.b _L5_4s # no + bsr.l src_one # yes + bra.b _L5_6s +_L5_4s: + cmpi.b %d1,&QNAN # is operand a QNAN? + bne.b _L5_5s # no + bsr.l src_qnan # yes + bra.b _L5_6s +_L5_5s: + bsr.l stanhd # operand is a DENORM +_L5_6s: + +# +# Result is now in FP0 +# + movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 + fmovm.l USER_FPCR(%a6),%fpcr,%fpsr # restore ctrl regs + fmovm.x EXC_FP1(%a6),&0x40 # restore fp1 + unlk %a6 + rts + + global _ftanhd_ +_ftanhd_: + link %a6,&-LOCAL_SIZE + + movm.l &0x0303,EXC_DREGS(%a6) # save d0-d1/a0-a1 + fmovm.l %fpcr,%fpsr,USER_FPCR(%a6) # save ctrl regs + fmovm.x &0xc0,EXC_FP0(%a6) # save fp0/fp1 + + fmov.l &0x0,%fpcr # zero FPCR + +# +# copy, convert, and tag input argument +# + fmov.d 0x8(%a6),%fp0 # load dbl input + fmov.x %fp0,FP_SRC(%a6) + lea FP_SRC(%a6),%a0 + bsr.l tag # fetch operand type + mov.b %d0,STAG(%a6) + mov.b %d0,%d1 + + andi.l &0x00ff00ff,USER_FPSR(%a6) + + clr.l %d0 + mov.b FPCR_MODE(%a6),%d0 # pass rnd mode,prec + + mov.b %d1,STAG(%a6) + tst.b %d1 + bne.b _L5_2d + bsr.l stanh # operand is a NORM + bra.b _L5_6d +_L5_2d: + cmpi.b %d1,&ZERO # is operand a ZERO? + bne.b _L5_3d # no + bsr.l src_zero # yes + bra.b _L5_6d +_L5_3d: + cmpi.b %d1,&INF # is operand an INF? + bne.b _L5_4d # no + bsr.l src_one # yes + bra.b _L5_6d +_L5_4d: + cmpi.b %d1,&QNAN # is operand a QNAN? + bne.b _L5_5d # no + bsr.l src_qnan # yes + bra.b _L5_6d +_L5_5d: + bsr.l stanhd # operand is a DENORM +_L5_6d: + +# +# Result is now in FP0 +# + movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 + fmovm.l USER_FPCR(%a6),%fpcr,%fpsr # restore ctrl regs + fmovm.x EXC_FP1(%a6),&0x40 # restore fp1 + unlk %a6 + rts + + global _ftanhx_ +_ftanhx_: + link %a6,&-LOCAL_SIZE + + movm.l &0x0303,EXC_DREGS(%a6) # save d0-d1/a0-a1 + fmovm.l %fpcr,%fpsr,USER_FPCR(%a6) # save ctrl regs + fmovm.x &0xc0,EXC_FP0(%a6) # save fp0/fp1 + + fmov.l &0x0,%fpcr # zero FPCR + +# +# copy, convert, and tag input argument +# + lea FP_SRC(%a6),%a0 + mov.l 0x8+0x0(%a6),0x0(%a0) # load ext input + mov.l 0x8+0x4(%a6),0x4(%a0) + mov.l 0x8+0x8(%a6),0x8(%a0) + bsr.l tag # fetch operand type + mov.b %d0,STAG(%a6) + mov.b %d0,%d1 + + andi.l &0x00ff00ff,USER_FPSR(%a6) + + clr.l %d0 + mov.b FPCR_MODE(%a6),%d0 # pass rnd mode,prec + + tst.b %d1 + bne.b _L5_2x + bsr.l stanh # operand is a NORM + bra.b _L5_6x +_L5_2x: + cmpi.b %d1,&ZERO # is operand a ZERO? + bne.b _L5_3x # no + bsr.l src_zero # yes + bra.b _L5_6x +_L5_3x: + cmpi.b %d1,&INF # is operand an INF? + bne.b _L5_4x # no + bsr.l src_one # yes + bra.b _L5_6x +_L5_4x: + cmpi.b %d1,&QNAN # is operand a QNAN? + bne.b _L5_5x # no + bsr.l src_qnan # yes + bra.b _L5_6x +_L5_5x: + bsr.l stanhd # operand is a DENORM +_L5_6x: + +# +# Result is now in FP0 +# + movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 + fmovm.l USER_FPCR(%a6),%fpcr,%fpsr # restore ctrl regs + fmovm.x EXC_FP1(%a6),&0x40 # restore fp1 + unlk %a6 + rts + + +######################################################################### +# MONADIC TEMPLATE # +######################################################################### + global _fatans_ +_fatans_: + link %a6,&-LOCAL_SIZE + + movm.l &0x0303,EXC_DREGS(%a6) # save d0-d1/a0-a1 + fmovm.l %fpcr,%fpsr,USER_FPCR(%a6) # save ctrl regs + fmovm.x &0xc0,EXC_FP0(%a6) # save fp0/fp1 + + fmov.l &0x0,%fpcr # zero FPCR + +# +# copy, convert, and tag input argument +# + fmov.s 0x8(%a6),%fp0 # load sgl input + fmov.x %fp0,FP_SRC(%a6) + lea FP_SRC(%a6),%a0 + bsr.l tag # fetch operand type + mov.b %d0,STAG(%a6) + mov.b %d0,%d1 + + andi.l &0x00ff00ff,USER_FPSR(%a6) + + clr.l %d0 + mov.b FPCR_MODE(%a6),%d0 # pass rnd mode,prec + + tst.b %d1 + bne.b _L6_2s + bsr.l satan # operand is a NORM + bra.b _L6_6s +_L6_2s: + cmpi.b %d1,&ZERO # is operand a ZERO? + bne.b _L6_3s # no + bsr.l src_zero # yes + bra.b _L6_6s +_L6_3s: + cmpi.b %d1,&INF # is operand an INF? + bne.b _L6_4s # no + bsr.l spi_2 # yes + bra.b _L6_6s +_L6_4s: + cmpi.b %d1,&QNAN # is operand a QNAN? + bne.b _L6_5s # no + bsr.l src_qnan # yes + bra.b _L6_6s +_L6_5s: + bsr.l satand # operand is a DENORM +_L6_6s: + +# +# Result is now in FP0 +# + movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 + fmovm.l USER_FPCR(%a6),%fpcr,%fpsr # restore ctrl regs + fmovm.x EXC_FP1(%a6),&0x40 # restore fp1 + unlk %a6 + rts + + global _fatand_ +_fatand_: + link %a6,&-LOCAL_SIZE + + movm.l &0x0303,EXC_DREGS(%a6) # save d0-d1/a0-a1 + fmovm.l %fpcr,%fpsr,USER_FPCR(%a6) # save ctrl regs + fmovm.x &0xc0,EXC_FP0(%a6) # save fp0/fp1 + + fmov.l &0x0,%fpcr # zero FPCR + +# +# copy, convert, and tag input argument +# + fmov.d 0x8(%a6),%fp0 # load dbl input + fmov.x %fp0,FP_SRC(%a6) + lea FP_SRC(%a6),%a0 + bsr.l tag # fetch operand type + mov.b %d0,STAG(%a6) + mov.b %d0,%d1 + + andi.l &0x00ff00ff,USER_FPSR(%a6) + + clr.l %d0 + mov.b FPCR_MODE(%a6),%d0 # pass rnd mode,prec + + mov.b %d1,STAG(%a6) + tst.b %d1 + bne.b _L6_2d + bsr.l satan # operand is a NORM + bra.b _L6_6d +_L6_2d: + cmpi.b %d1,&ZERO # is operand a ZERO? + bne.b _L6_3d # no + bsr.l src_zero # yes + bra.b _L6_6d +_L6_3d: + cmpi.b %d1,&INF # is operand an INF? + bne.b _L6_4d # no + bsr.l spi_2 # yes + bra.b _L6_6d +_L6_4d: + cmpi.b %d1,&QNAN # is operand a QNAN? + bne.b _L6_5d # no + bsr.l src_qnan # yes + bra.b _L6_6d +_L6_5d: + bsr.l satand # operand is a DENORM +_L6_6d: + +# +# Result is now in FP0 +# + movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 + fmovm.l USER_FPCR(%a6),%fpcr,%fpsr # restore ctrl regs + fmovm.x EXC_FP1(%a6),&0x40 # restore fp1 + unlk %a6 + rts + + global _fatanx_ +_fatanx_: + link %a6,&-LOCAL_SIZE + + movm.l &0x0303,EXC_DREGS(%a6) # save d0-d1/a0-a1 + fmovm.l %fpcr,%fpsr,USER_FPCR(%a6) # save ctrl regs + fmovm.x &0xc0,EXC_FP0(%a6) # save fp0/fp1 + + fmov.l &0x0,%fpcr # zero FPCR + +# +# copy, convert, and tag input argument +# + lea FP_SRC(%a6),%a0 + mov.l 0x8+0x0(%a6),0x0(%a0) # load ext input + mov.l 0x8+0x4(%a6),0x4(%a0) + mov.l 0x8+0x8(%a6),0x8(%a0) + bsr.l tag # fetch operand type + mov.b %d0,STAG(%a6) + mov.b %d0,%d1 + + andi.l &0x00ff00ff,USER_FPSR(%a6) + + clr.l %d0 + mov.b FPCR_MODE(%a6),%d0 # pass rnd mode,prec + + tst.b %d1 + bne.b _L6_2x + bsr.l satan # operand is a NORM + bra.b _L6_6x +_L6_2x: + cmpi.b %d1,&ZERO # is operand a ZERO? + bne.b _L6_3x # no + bsr.l src_zero # yes + bra.b _L6_6x +_L6_3x: + cmpi.b %d1,&INF # is operand an INF? + bne.b _L6_4x # no + bsr.l spi_2 # yes + bra.b _L6_6x +_L6_4x: + cmpi.b %d1,&QNAN # is operand a QNAN? + bne.b _L6_5x # no + bsr.l src_qnan # yes + bra.b _L6_6x +_L6_5x: + bsr.l satand # operand is a DENORM +_L6_6x: + +# +# Result is now in FP0 +# + movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 + fmovm.l USER_FPCR(%a6),%fpcr,%fpsr # restore ctrl regs + fmovm.x EXC_FP1(%a6),&0x40 # restore fp1 + unlk %a6 + rts + + +######################################################################### +# MONADIC TEMPLATE # +######################################################################### + global _fasins_ +_fasins_: + link %a6,&-LOCAL_SIZE + + movm.l &0x0303,EXC_DREGS(%a6) # save d0-d1/a0-a1 + fmovm.l %fpcr,%fpsr,USER_FPCR(%a6) # save ctrl regs + fmovm.x &0xc0,EXC_FP0(%a6) # save fp0/fp1 + + fmov.l &0x0,%fpcr # zero FPCR + +# +# copy, convert, and tag input argument +# + fmov.s 0x8(%a6),%fp0 # load sgl input + fmov.x %fp0,FP_SRC(%a6) + lea FP_SRC(%a6),%a0 + bsr.l tag # fetch operand type + mov.b %d0,STAG(%a6) + mov.b %d0,%d1 + + andi.l &0x00ff00ff,USER_FPSR(%a6) + + clr.l %d0 + mov.b FPCR_MODE(%a6),%d0 # pass rnd mode,prec + + tst.b %d1 + bne.b _L7_2s + bsr.l sasin # operand is a NORM + bra.b _L7_6s +_L7_2s: + cmpi.b %d1,&ZERO # is operand a ZERO? + bne.b _L7_3s # no + bsr.l src_zero # yes + bra.b _L7_6s +_L7_3s: + cmpi.b %d1,&INF # is operand an INF? + bne.b _L7_4s # no + bsr.l t_operr # yes + bra.b _L7_6s +_L7_4s: + cmpi.b %d1,&QNAN # is operand a QNAN? + bne.b _L7_5s # no + bsr.l src_qnan # yes + bra.b _L7_6s +_L7_5s: + bsr.l sasind # operand is a DENORM +_L7_6s: + +# +# Result is now in FP0 +# + movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 + fmovm.l USER_FPCR(%a6),%fpcr,%fpsr # restore ctrl regs + fmovm.x EXC_FP1(%a6),&0x40 # restore fp1 + unlk %a6 + rts + + global _fasind_ +_fasind_: + link %a6,&-LOCAL_SIZE + + movm.l &0x0303,EXC_DREGS(%a6) # save d0-d1/a0-a1 + fmovm.l %fpcr,%fpsr,USER_FPCR(%a6) # save ctrl regs + fmovm.x &0xc0,EXC_FP0(%a6) # save fp0/fp1 + + fmov.l &0x0,%fpcr # zero FPCR + +# +# copy, convert, and tag input argument +# + fmov.d 0x8(%a6),%fp0 # load dbl input + fmov.x %fp0,FP_SRC(%a6) + lea FP_SRC(%a6),%a0 + bsr.l tag # fetch operand type + mov.b %d0,STAG(%a6) + mov.b %d0,%d1 + + andi.l &0x00ff00ff,USER_FPSR(%a6) + + clr.l %d0 + mov.b FPCR_MODE(%a6),%d0 # pass rnd mode,prec + + mov.b %d1,STAG(%a6) + tst.b %d1 + bne.b _L7_2d + bsr.l sasin # operand is a NORM + bra.b _L7_6d +_L7_2d: + cmpi.b %d1,&ZERO # is operand a ZERO? + bne.b _L7_3d # no + bsr.l src_zero # yes + bra.b _L7_6d +_L7_3d: + cmpi.b %d1,&INF # is operand an INF? + bne.b _L7_4d # no + bsr.l t_operr # yes + bra.b _L7_6d +_L7_4d: + cmpi.b %d1,&QNAN # is operand a QNAN? + bne.b _L7_5d # no + bsr.l src_qnan # yes + bra.b _L7_6d +_L7_5d: + bsr.l sasind # operand is a DENORM +_L7_6d: + +# +# Result is now in FP0 +# + movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 + fmovm.l USER_FPCR(%a6),%fpcr,%fpsr # restore ctrl regs + fmovm.x EXC_FP1(%a6),&0x40 # restore fp1 + unlk %a6 + rts + + global _fasinx_ +_fasinx_: + link %a6,&-LOCAL_SIZE + + movm.l &0x0303,EXC_DREGS(%a6) # save d0-d1/a0-a1 + fmovm.l %fpcr,%fpsr,USER_FPCR(%a6) # save ctrl regs + fmovm.x &0xc0,EXC_FP0(%a6) # save fp0/fp1 + + fmov.l &0x0,%fpcr # zero FPCR + +# +# copy, convert, and tag input argument +# + lea FP_SRC(%a6),%a0 + mov.l 0x8+0x0(%a6),0x0(%a0) # load ext input + mov.l 0x8+0x4(%a6),0x4(%a0) + mov.l 0x8+0x8(%a6),0x8(%a0) + bsr.l tag # fetch operand type + mov.b %d0,STAG(%a6) + mov.b %d0,%d1 + + andi.l &0x00ff00ff,USER_FPSR(%a6) + + clr.l %d0 + mov.b FPCR_MODE(%a6),%d0 # pass rnd mode,prec + + tst.b %d1 + bne.b _L7_2x + bsr.l sasin # operand is a NORM + bra.b _L7_6x +_L7_2x: + cmpi.b %d1,&ZERO # is operand a ZERO? + bne.b _L7_3x # no + bsr.l src_zero # yes + bra.b _L7_6x +_L7_3x: + cmpi.b %d1,&INF # is operand an INF? + bne.b _L7_4x # no + bsr.l t_operr # yes + bra.b _L7_6x +_L7_4x: + cmpi.b %d1,&QNAN # is operand a QNAN? + bne.b _L7_5x # no + bsr.l src_qnan # yes + bra.b _L7_6x +_L7_5x: + bsr.l sasind # operand is a DENORM +_L7_6x: + +# +# Result is now in FP0 +# + movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 + fmovm.l USER_FPCR(%a6),%fpcr,%fpsr # restore ctrl regs + fmovm.x EXC_FP1(%a6),&0x40 # restore fp1 + unlk %a6 + rts + + +######################################################################### +# MONADIC TEMPLATE # +######################################################################### + global _fatanhs_ +_fatanhs_: + link %a6,&-LOCAL_SIZE + + movm.l &0x0303,EXC_DREGS(%a6) # save d0-d1/a0-a1 + fmovm.l %fpcr,%fpsr,USER_FPCR(%a6) # save ctrl regs + fmovm.x &0xc0,EXC_FP0(%a6) # save fp0/fp1 + + fmov.l &0x0,%fpcr # zero FPCR + +# +# copy, convert, and tag input argument +# + fmov.s 0x8(%a6),%fp0 # load sgl input + fmov.x %fp0,FP_SRC(%a6) + lea FP_SRC(%a6),%a0 + bsr.l tag # fetch operand type + mov.b %d0,STAG(%a6) + mov.b %d0,%d1 + + andi.l &0x00ff00ff,USER_FPSR(%a6) + + clr.l %d0 + mov.b FPCR_MODE(%a6),%d0 # pass rnd mode,prec + + tst.b %d1 + bne.b _L8_2s + bsr.l satanh # operand is a NORM + bra.b _L8_6s +_L8_2s: + cmpi.b %d1,&ZERO # is operand a ZERO? + bne.b _L8_3s # no + bsr.l src_zero # yes + bra.b _L8_6s +_L8_3s: + cmpi.b %d1,&INF # is operand an INF? + bne.b _L8_4s # no + bsr.l t_operr # yes + bra.b _L8_6s +_L8_4s: + cmpi.b %d1,&QNAN # is operand a QNAN? + bne.b _L8_5s # no + bsr.l src_qnan # yes + bra.b _L8_6s +_L8_5s: + bsr.l satanhd # operand is a DENORM +_L8_6s: + +# +# Result is now in FP0 +# + movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 + fmovm.l USER_FPCR(%a6),%fpcr,%fpsr # restore ctrl regs + fmovm.x EXC_FP1(%a6),&0x40 # restore fp1 + unlk %a6 + rts + + global _fatanhd_ +_fatanhd_: + link %a6,&-LOCAL_SIZE + + movm.l &0x0303,EXC_DREGS(%a6) # save d0-d1/a0-a1 + fmovm.l %fpcr,%fpsr,USER_FPCR(%a6) # save ctrl regs + fmovm.x &0xc0,EXC_FP0(%a6) # save fp0/fp1 + + fmov.l &0x0,%fpcr # zero FPCR + +# +# copy, convert, and tag input argument +# + fmov.d 0x8(%a6),%fp0 # load dbl input + fmov.x %fp0,FP_SRC(%a6) + lea FP_SRC(%a6),%a0 + bsr.l tag # fetch operand type + mov.b %d0,STAG(%a6) + mov.b %d0,%d1 + + andi.l &0x00ff00ff,USER_FPSR(%a6) + + clr.l %d0 + mov.b FPCR_MODE(%a6),%d0 # pass rnd mode,prec + + mov.b %d1,STAG(%a6) + tst.b %d1 + bne.b _L8_2d + bsr.l satanh # operand is a NORM + bra.b _L8_6d +_L8_2d: + cmpi.b %d1,&ZERO # is operand a ZERO? + bne.b _L8_3d # no + bsr.l src_zero # yes + bra.b _L8_6d +_L8_3d: + cmpi.b %d1,&INF # is operand an INF? + bne.b _L8_4d # no + bsr.l t_operr # yes + bra.b _L8_6d +_L8_4d: + cmpi.b %d1,&QNAN # is operand a QNAN? + bne.b _L8_5d # no + bsr.l src_qnan # yes + bra.b _L8_6d +_L8_5d: + bsr.l satanhd # operand is a DENORM +_L8_6d: + +# +# Result is now in FP0 +# + movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 + fmovm.l USER_FPCR(%a6),%fpcr,%fpsr # restore ctrl regs + fmovm.x EXC_FP1(%a6),&0x40 # restore fp1 + unlk %a6 + rts + + global _fatanhx_ +_fatanhx_: + link %a6,&-LOCAL_SIZE + + movm.l &0x0303,EXC_DREGS(%a6) # save d0-d1/a0-a1 + fmovm.l %fpcr,%fpsr,USER_FPCR(%a6) # save ctrl regs + fmovm.x &0xc0,EXC_FP0(%a6) # save fp0/fp1 + + fmov.l &0x0,%fpcr # zero FPCR + +# +# copy, convert, and tag input argument +# + lea FP_SRC(%a6),%a0 + mov.l 0x8+0x0(%a6),0x0(%a0) # load ext input + mov.l 0x8+0x4(%a6),0x4(%a0) + mov.l 0x8+0x8(%a6),0x8(%a0) + bsr.l tag # fetch operand type + mov.b %d0,STAG(%a6) + mov.b %d0,%d1 + + andi.l &0x00ff00ff,USER_FPSR(%a6) + + clr.l %d0 + mov.b FPCR_MODE(%a6),%d0 # pass rnd mode,prec + + tst.b %d1 + bne.b _L8_2x + bsr.l satanh # operand is a NORM + bra.b _L8_6x +_L8_2x: + cmpi.b %d1,&ZERO # is operand a ZERO? + bne.b _L8_3x # no + bsr.l src_zero # yes + bra.b _L8_6x +_L8_3x: + cmpi.b %d1,&INF # is operand an INF? + bne.b _L8_4x # no + bsr.l t_operr # yes + bra.b _L8_6x +_L8_4x: + cmpi.b %d1,&QNAN # is operand a QNAN? + bne.b _L8_5x # no + bsr.l src_qnan # yes + bra.b _L8_6x +_L8_5x: + bsr.l satanhd # operand is a DENORM +_L8_6x: + +# +# Result is now in FP0 +# + movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 + fmovm.l USER_FPCR(%a6),%fpcr,%fpsr # restore ctrl regs + fmovm.x EXC_FP1(%a6),&0x40 # restore fp1 + unlk %a6 + rts + + +######################################################################### +# MONADIC TEMPLATE # +######################################################################### + global _ftans_ +_ftans_: + link %a6,&-LOCAL_SIZE + + movm.l &0x0303,EXC_DREGS(%a6) # save d0-d1/a0-a1 + fmovm.l %fpcr,%fpsr,USER_FPCR(%a6) # save ctrl regs + fmovm.x &0xc0,EXC_FP0(%a6) # save fp0/fp1 + + fmov.l &0x0,%fpcr # zero FPCR + +# +# copy, convert, and tag input argument +# + fmov.s 0x8(%a6),%fp0 # load sgl input + fmov.x %fp0,FP_SRC(%a6) + lea FP_SRC(%a6),%a0 + bsr.l tag # fetch operand type + mov.b %d0,STAG(%a6) + mov.b %d0,%d1 + + andi.l &0x00ff00ff,USER_FPSR(%a6) + + clr.l %d0 + mov.b FPCR_MODE(%a6),%d0 # pass rnd mode,prec + + tst.b %d1 + bne.b _L9_2s + bsr.l stan # operand is a NORM + bra.b _L9_6s +_L9_2s: + cmpi.b %d1,&ZERO # is operand a ZERO? + bne.b _L9_3s # no + bsr.l src_zero # yes + bra.b _L9_6s +_L9_3s: + cmpi.b %d1,&INF # is operand an INF? + bne.b _L9_4s # no + bsr.l t_operr # yes + bra.b _L9_6s +_L9_4s: + cmpi.b %d1,&QNAN # is operand a QNAN? + bne.b _L9_5s # no + bsr.l src_qnan # yes + bra.b _L9_6s +_L9_5s: + bsr.l stand # operand is a DENORM +_L9_6s: + +# +# Result is now in FP0 +# + movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 + fmovm.l USER_FPCR(%a6),%fpcr,%fpsr # restore ctrl regs + fmovm.x EXC_FP1(%a6),&0x40 # restore fp1 + unlk %a6 + rts + + global _ftand_ +_ftand_: + link %a6,&-LOCAL_SIZE + + movm.l &0x0303,EXC_DREGS(%a6) # save d0-d1/a0-a1 + fmovm.l %fpcr,%fpsr,USER_FPCR(%a6) # save ctrl regs + fmovm.x &0xc0,EXC_FP0(%a6) # save fp0/fp1 + + fmov.l &0x0,%fpcr # zero FPCR + +# +# copy, convert, and tag input argument +# + fmov.d 0x8(%a6),%fp0 # load dbl input + fmov.x %fp0,FP_SRC(%a6) + lea FP_SRC(%a6),%a0 + bsr.l tag # fetch operand type + mov.b %d0,STAG(%a6) + mov.b %d0,%d1 + + andi.l &0x00ff00ff,USER_FPSR(%a6) + + clr.l %d0 + mov.b FPCR_MODE(%a6),%d0 # pass rnd mode,prec + + mov.b %d1,STAG(%a6) + tst.b %d1 + bne.b _L9_2d + bsr.l stan # operand is a NORM + bra.b _L9_6d +_L9_2d: + cmpi.b %d1,&ZERO # is operand a ZERO? + bne.b _L9_3d # no + bsr.l src_zero # yes + bra.b _L9_6d +_L9_3d: + cmpi.b %d1,&INF # is operand an INF? + bne.b _L9_4d # no + bsr.l t_operr # yes + bra.b _L9_6d +_L9_4d: + cmpi.b %d1,&QNAN # is operand a QNAN? + bne.b _L9_5d # no + bsr.l src_qnan # yes + bra.b _L9_6d +_L9_5d: + bsr.l stand # operand is a DENORM +_L9_6d: + +# +# Result is now in FP0 +# + movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 + fmovm.l USER_FPCR(%a6),%fpcr,%fpsr # restore ctrl regs + fmovm.x EXC_FP1(%a6),&0x40 # restore fp1 + unlk %a6 + rts + + global _ftanx_ +_ftanx_: + link %a6,&-LOCAL_SIZE + + movm.l &0x0303,EXC_DREGS(%a6) # save d0-d1/a0-a1 + fmovm.l %fpcr,%fpsr,USER_FPCR(%a6) # save ctrl regs + fmovm.x &0xc0,EXC_FP0(%a6) # save fp0/fp1 + + fmov.l &0x0,%fpcr # zero FPCR + +# +# copy, convert, and tag input argument +# + lea FP_SRC(%a6),%a0 + mov.l 0x8+0x0(%a6),0x0(%a0) # load ext input + mov.l 0x8+0x4(%a6),0x4(%a0) + mov.l 0x8+0x8(%a6),0x8(%a0) + bsr.l tag # fetch operand type + mov.b %d0,STAG(%a6) + mov.b %d0,%d1 + + andi.l &0x00ff00ff,USER_FPSR(%a6) + + clr.l %d0 + mov.b FPCR_MODE(%a6),%d0 # pass rnd mode,prec + + tst.b %d1 + bne.b _L9_2x + bsr.l stan # operand is a NORM + bra.b _L9_6x +_L9_2x: + cmpi.b %d1,&ZERO # is operand a ZERO? + bne.b _L9_3x # no + bsr.l src_zero # yes + bra.b _L9_6x +_L9_3x: + cmpi.b %d1,&INF # is operand an INF? + bne.b _L9_4x # no + bsr.l t_operr # yes + bra.b _L9_6x +_L9_4x: + cmpi.b %d1,&QNAN # is operand a QNAN? + bne.b _L9_5x # no + bsr.l src_qnan # yes + bra.b _L9_6x +_L9_5x: + bsr.l stand # operand is a DENORM +_L9_6x: + +# +# Result is now in FP0 +# + movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 + fmovm.l USER_FPCR(%a6),%fpcr,%fpsr # restore ctrl regs + fmovm.x EXC_FP1(%a6),&0x40 # restore fp1 + unlk %a6 + rts + + +######################################################################### +# MONADIC TEMPLATE # +######################################################################### + global _fetoxs_ +_fetoxs_: + link %a6,&-LOCAL_SIZE + + movm.l &0x0303,EXC_DREGS(%a6) # save d0-d1/a0-a1 + fmovm.l %fpcr,%fpsr,USER_FPCR(%a6) # save ctrl regs + fmovm.x &0xc0,EXC_FP0(%a6) # save fp0/fp1 + + fmov.l &0x0,%fpcr # zero FPCR + +# +# copy, convert, and tag input argument +# + fmov.s 0x8(%a6),%fp0 # load sgl input + fmov.x %fp0,FP_SRC(%a6) + lea FP_SRC(%a6),%a0 + bsr.l tag # fetch operand type + mov.b %d0,STAG(%a6) + mov.b %d0,%d1 + + andi.l &0x00ff00ff,USER_FPSR(%a6) + + clr.l %d0 + mov.b FPCR_MODE(%a6),%d0 # pass rnd mode,prec + + tst.b %d1 + bne.b _L10_2s + bsr.l setox # operand is a NORM + bra.b _L10_6s +_L10_2s: + cmpi.b %d1,&ZERO # is operand a ZERO? + bne.b _L10_3s # no + bsr.l ld_pone # yes + bra.b _L10_6s +_L10_3s: + cmpi.b %d1,&INF # is operand an INF? + bne.b _L10_4s # no + bsr.l szr_inf # yes + bra.b _L10_6s +_L10_4s: + cmpi.b %d1,&QNAN # is operand a QNAN? + bne.b _L10_5s # no + bsr.l src_qnan # yes + bra.b _L10_6s +_L10_5s: + bsr.l setoxd # operand is a DENORM +_L10_6s: + +# +# Result is now in FP0 +# + movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 + fmovm.l USER_FPCR(%a6),%fpcr,%fpsr # restore ctrl regs + fmovm.x EXC_FP1(%a6),&0x40 # restore fp1 + unlk %a6 + rts + + global _fetoxd_ +_fetoxd_: + link %a6,&-LOCAL_SIZE + + movm.l &0x0303,EXC_DREGS(%a6) # save d0-d1/a0-a1 + fmovm.l %fpcr,%fpsr,USER_FPCR(%a6) # save ctrl regs + fmovm.x &0xc0,EXC_FP0(%a6) # save fp0/fp1 + + fmov.l &0x0,%fpcr # zero FPCR + +# +# copy, convert, and tag input argument +# + fmov.d 0x8(%a6),%fp0 # load dbl input + fmov.x %fp0,FP_SRC(%a6) + lea FP_SRC(%a6),%a0 + bsr.l tag # fetch operand type + mov.b %d0,STAG(%a6) + mov.b %d0,%d1 + + andi.l &0x00ff00ff,USER_FPSR(%a6) + + clr.l %d0 + mov.b FPCR_MODE(%a6),%d0 # pass rnd mode,prec + + mov.b %d1,STAG(%a6) + tst.b %d1 + bne.b _L10_2d + bsr.l setox # operand is a NORM + bra.b _L10_6d +_L10_2d: + cmpi.b %d1,&ZERO # is operand a ZERO? + bne.b _L10_3d # no + bsr.l ld_pone # yes + bra.b _L10_6d +_L10_3d: + cmpi.b %d1,&INF # is operand an INF? + bne.b _L10_4d # no + bsr.l szr_inf # yes + bra.b _L10_6d +_L10_4d: + cmpi.b %d1,&QNAN # is operand a QNAN? + bne.b _L10_5d # no + bsr.l src_qnan # yes + bra.b _L10_6d +_L10_5d: + bsr.l setoxd # operand is a DENORM +_L10_6d: + +# +# Result is now in FP0 +# + movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 + fmovm.l USER_FPCR(%a6),%fpcr,%fpsr # restore ctrl regs + fmovm.x EXC_FP1(%a6),&0x40 # restore fp1 + unlk %a6 + rts + + global _fetoxx_ +_fetoxx_: + link %a6,&-LOCAL_SIZE + + movm.l &0x0303,EXC_DREGS(%a6) # save d0-d1/a0-a1 + fmovm.l %fpcr,%fpsr,USER_FPCR(%a6) # save ctrl regs + fmovm.x &0xc0,EXC_FP0(%a6) # save fp0/fp1 + + fmov.l &0x0,%fpcr # zero FPCR + +# +# copy, convert, and tag input argument +# + lea FP_SRC(%a6),%a0 + mov.l 0x8+0x0(%a6),0x0(%a0) # load ext input + mov.l 0x8+0x4(%a6),0x4(%a0) + mov.l 0x8+0x8(%a6),0x8(%a0) + bsr.l tag # fetch operand type + mov.b %d0,STAG(%a6) + mov.b %d0,%d1 + + andi.l &0x00ff00ff,USER_FPSR(%a6) + + clr.l %d0 + mov.b FPCR_MODE(%a6),%d0 # pass rnd mode,prec + + tst.b %d1 + bne.b _L10_2x + bsr.l setox # operand is a NORM + bra.b _L10_6x +_L10_2x: + cmpi.b %d1,&ZERO # is operand a ZERO? + bne.b _L10_3x # no + bsr.l ld_pone # yes + bra.b _L10_6x +_L10_3x: + cmpi.b %d1,&INF # is operand an INF? + bne.b _L10_4x # no + bsr.l szr_inf # yes + bra.b _L10_6x +_L10_4x: + cmpi.b %d1,&QNAN # is operand a QNAN? + bne.b _L10_5x # no + bsr.l src_qnan # yes + bra.b _L10_6x +_L10_5x: + bsr.l setoxd # operand is a DENORM +_L10_6x: + +# +# Result is now in FP0 +# + movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 + fmovm.l USER_FPCR(%a6),%fpcr,%fpsr # restore ctrl regs + fmovm.x EXC_FP1(%a6),&0x40 # restore fp1 + unlk %a6 + rts + + +######################################################################### +# MONADIC TEMPLATE # +######################################################################### + global _ftwotoxs_ +_ftwotoxs_: + link %a6,&-LOCAL_SIZE + + movm.l &0x0303,EXC_DREGS(%a6) # save d0-d1/a0-a1 + fmovm.l %fpcr,%fpsr,USER_FPCR(%a6) # save ctrl regs + fmovm.x &0xc0,EXC_FP0(%a6) # save fp0/fp1 + + fmov.l &0x0,%fpcr # zero FPCR + +# +# copy, convert, and tag input argument +# + fmov.s 0x8(%a6),%fp0 # load sgl input + fmov.x %fp0,FP_SRC(%a6) + lea FP_SRC(%a6),%a0 + bsr.l tag # fetch operand type + mov.b %d0,STAG(%a6) + mov.b %d0,%d1 + + andi.l &0x00ff00ff,USER_FPSR(%a6) + + clr.l %d0 + mov.b FPCR_MODE(%a6),%d0 # pass rnd mode,prec + + tst.b %d1 + bne.b _L11_2s + bsr.l stwotox # operand is a NORM + bra.b _L11_6s +_L11_2s: + cmpi.b %d1,&ZERO # is operand a ZERO? + bne.b _L11_3s # no + bsr.l ld_pone # yes + bra.b _L11_6s +_L11_3s: + cmpi.b %d1,&INF # is operand an INF? + bne.b _L11_4s # no + bsr.l szr_inf # yes + bra.b _L11_6s +_L11_4s: + cmpi.b %d1,&QNAN # is operand a QNAN? + bne.b _L11_5s # no + bsr.l src_qnan # yes + bra.b _L11_6s +_L11_5s: + bsr.l stwotoxd # operand is a DENORM +_L11_6s: + +# +# Result is now in FP0 +# + movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 + fmovm.l USER_FPCR(%a6),%fpcr,%fpsr # restore ctrl regs + fmovm.x EXC_FP1(%a6),&0x40 # restore fp1 + unlk %a6 + rts + + global _ftwotoxd_ +_ftwotoxd_: + link %a6,&-LOCAL_SIZE + + movm.l &0x0303,EXC_DREGS(%a6) # save d0-d1/a0-a1 + fmovm.l %fpcr,%fpsr,USER_FPCR(%a6) # save ctrl regs + fmovm.x &0xc0,EXC_FP0(%a6) # save fp0/fp1 + + fmov.l &0x0,%fpcr # zero FPCR + +# +# copy, convert, and tag input argument +# + fmov.d 0x8(%a6),%fp0 # load dbl input + fmov.x %fp0,FP_SRC(%a6) + lea FP_SRC(%a6),%a0 + bsr.l tag # fetch operand type + mov.b %d0,STAG(%a6) + mov.b %d0,%d1 + + andi.l &0x00ff00ff,USER_FPSR(%a6) + + clr.l %d0 + mov.b FPCR_MODE(%a6),%d0 # pass rnd mode,prec + + mov.b %d1,STAG(%a6) + tst.b %d1 + bne.b _L11_2d + bsr.l stwotox # operand is a NORM + bra.b _L11_6d +_L11_2d: + cmpi.b %d1,&ZERO # is operand a ZERO? + bne.b _L11_3d # no + bsr.l ld_pone # yes + bra.b _L11_6d +_L11_3d: + cmpi.b %d1,&INF # is operand an INF? + bne.b _L11_4d # no + bsr.l szr_inf # yes + bra.b _L11_6d +_L11_4d: + cmpi.b %d1,&QNAN # is operand a QNAN? + bne.b _L11_5d # no + bsr.l src_qnan # yes + bra.b _L11_6d +_L11_5d: + bsr.l stwotoxd # operand is a DENORM +_L11_6d: + +# +# Result is now in FP0 +# + movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 + fmovm.l USER_FPCR(%a6),%fpcr,%fpsr # restore ctrl regs + fmovm.x EXC_FP1(%a6),&0x40 # restore fp1 + unlk %a6 + rts + + global _ftwotoxx_ +_ftwotoxx_: + link %a6,&-LOCAL_SIZE + + movm.l &0x0303,EXC_DREGS(%a6) # save d0-d1/a0-a1 + fmovm.l %fpcr,%fpsr,USER_FPCR(%a6) # save ctrl regs + fmovm.x &0xc0,EXC_FP0(%a6) # save fp0/fp1 + + fmov.l &0x0,%fpcr # zero FPCR + +# +# copy, convert, and tag input argument +# + lea FP_SRC(%a6),%a0 + mov.l 0x8+0x0(%a6),0x0(%a0) # load ext input + mov.l 0x8+0x4(%a6),0x4(%a0) + mov.l 0x8+0x8(%a6),0x8(%a0) + bsr.l tag # fetch operand type + mov.b %d0,STAG(%a6) + mov.b %d0,%d1 + + andi.l &0x00ff00ff,USER_FPSR(%a6) + + clr.l %d0 + mov.b FPCR_MODE(%a6),%d0 # pass rnd mode,prec + + tst.b %d1 + bne.b _L11_2x + bsr.l stwotox # operand is a NORM + bra.b _L11_6x +_L11_2x: + cmpi.b %d1,&ZERO # is operand a ZERO? + bne.b _L11_3x # no + bsr.l ld_pone # yes + bra.b _L11_6x +_L11_3x: + cmpi.b %d1,&INF # is operand an INF? + bne.b _L11_4x # no + bsr.l szr_inf # yes + bra.b _L11_6x +_L11_4x: + cmpi.b %d1,&QNAN # is operand a QNAN? + bne.b _L11_5x # no + bsr.l src_qnan # yes + bra.b _L11_6x +_L11_5x: + bsr.l stwotoxd # operand is a DENORM +_L11_6x: + +# +# Result is now in FP0 +# + movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 + fmovm.l USER_FPCR(%a6),%fpcr,%fpsr # restore ctrl regs + fmovm.x EXC_FP1(%a6),&0x40 # restore fp1 + unlk %a6 + rts + + +######################################################################### +# MONADIC TEMPLATE # +######################################################################### + global _ftentoxs_ +_ftentoxs_: + link %a6,&-LOCAL_SIZE + + movm.l &0x0303,EXC_DREGS(%a6) # save d0-d1/a0-a1 + fmovm.l %fpcr,%fpsr,USER_FPCR(%a6) # save ctrl regs + fmovm.x &0xc0,EXC_FP0(%a6) # save fp0/fp1 + + fmov.l &0x0,%fpcr # zero FPCR + +# +# copy, convert, and tag input argument +# + fmov.s 0x8(%a6),%fp0 # load sgl input + fmov.x %fp0,FP_SRC(%a6) + lea FP_SRC(%a6),%a0 + bsr.l tag # fetch operand type + mov.b %d0,STAG(%a6) + mov.b %d0,%d1 + + andi.l &0x00ff00ff,USER_FPSR(%a6) + + clr.l %d0 + mov.b FPCR_MODE(%a6),%d0 # pass rnd mode,prec + + tst.b %d1 + bne.b _L12_2s + bsr.l stentox # operand is a NORM + bra.b _L12_6s +_L12_2s: + cmpi.b %d1,&ZERO # is operand a ZERO? + bne.b _L12_3s # no + bsr.l ld_pone # yes + bra.b _L12_6s +_L12_3s: + cmpi.b %d1,&INF # is operand an INF? + bne.b _L12_4s # no + bsr.l szr_inf # yes + bra.b _L12_6s +_L12_4s: + cmpi.b %d1,&QNAN # is operand a QNAN? + bne.b _L12_5s # no + bsr.l src_qnan # yes + bra.b _L12_6s +_L12_5s: + bsr.l stentoxd # operand is a DENORM +_L12_6s: + +# +# Result is now in FP0 +# + movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 + fmovm.l USER_FPCR(%a6),%fpcr,%fpsr # restore ctrl regs + fmovm.x EXC_FP1(%a6),&0x40 # restore fp1 + unlk %a6 + rts + + global _ftentoxd_ +_ftentoxd_: + link %a6,&-LOCAL_SIZE + + movm.l &0x0303,EXC_DREGS(%a6) # save d0-d1/a0-a1 + fmovm.l %fpcr,%fpsr,USER_FPCR(%a6) # save ctrl regs + fmovm.x &0xc0,EXC_FP0(%a6) # save fp0/fp1 + + fmov.l &0x0,%fpcr # zero FPCR + +# +# copy, convert, and tag input argument +# + fmov.d 0x8(%a6),%fp0 # load dbl input + fmov.x %fp0,FP_SRC(%a6) + lea FP_SRC(%a6),%a0 + bsr.l tag # fetch operand type + mov.b %d0,STAG(%a6) + mov.b %d0,%d1 + + andi.l &0x00ff00ff,USER_FPSR(%a6) + + clr.l %d0 + mov.b FPCR_MODE(%a6),%d0 # pass rnd mode,prec + + mov.b %d1,STAG(%a6) + tst.b %d1 + bne.b _L12_2d + bsr.l stentox # operand is a NORM + bra.b _L12_6d +_L12_2d: + cmpi.b %d1,&ZERO # is operand a ZERO? + bne.b _L12_3d # no + bsr.l ld_pone # yes + bra.b _L12_6d +_L12_3d: + cmpi.b %d1,&INF # is operand an INF? + bne.b _L12_4d # no + bsr.l szr_inf # yes + bra.b _L12_6d +_L12_4d: + cmpi.b %d1,&QNAN # is operand a QNAN? + bne.b _L12_5d # no + bsr.l src_qnan # yes + bra.b _L12_6d +_L12_5d: + bsr.l stentoxd # operand is a DENORM +_L12_6d: + +# +# Result is now in FP0 +# + movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 + fmovm.l USER_FPCR(%a6),%fpcr,%fpsr # restore ctrl regs + fmovm.x EXC_FP1(%a6),&0x40 # restore fp1 + unlk %a6 + rts + + global _ftentoxx_ +_ftentoxx_: + link %a6,&-LOCAL_SIZE + + movm.l &0x0303,EXC_DREGS(%a6) # save d0-d1/a0-a1 + fmovm.l %fpcr,%fpsr,USER_FPCR(%a6) # save ctrl regs + fmovm.x &0xc0,EXC_FP0(%a6) # save fp0/fp1 + + fmov.l &0x0,%fpcr # zero FPCR + +# +# copy, convert, and tag input argument +# + lea FP_SRC(%a6),%a0 + mov.l 0x8+0x0(%a6),0x0(%a0) # load ext input + mov.l 0x8+0x4(%a6),0x4(%a0) + mov.l 0x8+0x8(%a6),0x8(%a0) + bsr.l tag # fetch operand type + mov.b %d0,STAG(%a6) + mov.b %d0,%d1 + + andi.l &0x00ff00ff,USER_FPSR(%a6) + + clr.l %d0 + mov.b FPCR_MODE(%a6),%d0 # pass rnd mode,prec + + tst.b %d1 + bne.b _L12_2x + bsr.l stentox # operand is a NORM + bra.b _L12_6x +_L12_2x: + cmpi.b %d1,&ZERO # is operand a ZERO? + bne.b _L12_3x # no + bsr.l ld_pone # yes + bra.b _L12_6x +_L12_3x: + cmpi.b %d1,&INF # is operand an INF? + bne.b _L12_4x # no + bsr.l szr_inf # yes + bra.b _L12_6x +_L12_4x: + cmpi.b %d1,&QNAN # is operand a QNAN? + bne.b _L12_5x # no + bsr.l src_qnan # yes + bra.b _L12_6x +_L12_5x: + bsr.l stentoxd # operand is a DENORM +_L12_6x: + +# +# Result is now in FP0 +# + movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 + fmovm.l USER_FPCR(%a6),%fpcr,%fpsr # restore ctrl regs + fmovm.x EXC_FP1(%a6),&0x40 # restore fp1 + unlk %a6 + rts + + +######################################################################### +# MONADIC TEMPLATE # +######################################################################### + global _flogns_ +_flogns_: + link %a6,&-LOCAL_SIZE + + movm.l &0x0303,EXC_DREGS(%a6) # save d0-d1/a0-a1 + fmovm.l %fpcr,%fpsr,USER_FPCR(%a6) # save ctrl regs + fmovm.x &0xc0,EXC_FP0(%a6) # save fp0/fp1 + + fmov.l &0x0,%fpcr # zero FPCR + +# +# copy, convert, and tag input argument +# + fmov.s 0x8(%a6),%fp0 # load sgl input + fmov.x %fp0,FP_SRC(%a6) + lea FP_SRC(%a6),%a0 + bsr.l tag # fetch operand type + mov.b %d0,STAG(%a6) + mov.b %d0,%d1 + + andi.l &0x00ff00ff,USER_FPSR(%a6) + + clr.l %d0 + mov.b FPCR_MODE(%a6),%d0 # pass rnd mode,prec + + tst.b %d1 + bne.b _L13_2s + bsr.l slogn # operand is a NORM + bra.b _L13_6s +_L13_2s: + cmpi.b %d1,&ZERO # is operand a ZERO? + bne.b _L13_3s # no + bsr.l t_dz2 # yes + bra.b _L13_6s +_L13_3s: + cmpi.b %d1,&INF # is operand an INF? + bne.b _L13_4s # no + bsr.l sopr_inf # yes + bra.b _L13_6s +_L13_4s: + cmpi.b %d1,&QNAN # is operand a QNAN? + bne.b _L13_5s # no + bsr.l src_qnan # yes + bra.b _L13_6s +_L13_5s: + bsr.l slognd # operand is a DENORM +_L13_6s: + +# +# Result is now in FP0 +# + movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 + fmovm.l USER_FPCR(%a6),%fpcr,%fpsr # restore ctrl regs + fmovm.x EXC_FP1(%a6),&0x40 # restore fp1 + unlk %a6 + rts + + global _flognd_ +_flognd_: + link %a6,&-LOCAL_SIZE + + movm.l &0x0303,EXC_DREGS(%a6) # save d0-d1/a0-a1 + fmovm.l %fpcr,%fpsr,USER_FPCR(%a6) # save ctrl regs + fmovm.x &0xc0,EXC_FP0(%a6) # save fp0/fp1 + + fmov.l &0x0,%fpcr # zero FPCR + +# +# copy, convert, and tag input argument +# + fmov.d 0x8(%a6),%fp0 # load dbl input + fmov.x %fp0,FP_SRC(%a6) + lea FP_SRC(%a6),%a0 + bsr.l tag # fetch operand type + mov.b %d0,STAG(%a6) + mov.b %d0,%d1 + + andi.l &0x00ff00ff,USER_FPSR(%a6) + + clr.l %d0 + mov.b FPCR_MODE(%a6),%d0 # pass rnd mode,prec + + mov.b %d1,STAG(%a6) + tst.b %d1 + bne.b _L13_2d + bsr.l slogn # operand is a NORM + bra.b _L13_6d +_L13_2d: + cmpi.b %d1,&ZERO # is operand a ZERO? + bne.b _L13_3d # no + bsr.l t_dz2 # yes + bra.b _L13_6d +_L13_3d: + cmpi.b %d1,&INF # is operand an INF? + bne.b _L13_4d # no + bsr.l sopr_inf # yes + bra.b _L13_6d +_L13_4d: + cmpi.b %d1,&QNAN # is operand a QNAN? + bne.b _L13_5d # no + bsr.l src_qnan # yes + bra.b _L13_6d +_L13_5d: + bsr.l slognd # operand is a DENORM +_L13_6d: + +# +# Result is now in FP0 +# + movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 + fmovm.l USER_FPCR(%a6),%fpcr,%fpsr # restore ctrl regs + fmovm.x EXC_FP1(%a6),&0x40 # restore fp1 + unlk %a6 + rts + + global _flognx_ +_flognx_: + link %a6,&-LOCAL_SIZE + + movm.l &0x0303,EXC_DREGS(%a6) # save d0-d1/a0-a1 + fmovm.l %fpcr,%fpsr,USER_FPCR(%a6) # save ctrl regs + fmovm.x &0xc0,EXC_FP0(%a6) # save fp0/fp1 + + fmov.l &0x0,%fpcr # zero FPCR + +# +# copy, convert, and tag input argument +# + lea FP_SRC(%a6),%a0 + mov.l 0x8+0x0(%a6),0x0(%a0) # load ext input + mov.l 0x8+0x4(%a6),0x4(%a0) + mov.l 0x8+0x8(%a6),0x8(%a0) + bsr.l tag # fetch operand type + mov.b %d0,STAG(%a6) + mov.b %d0,%d1 + + andi.l &0x00ff00ff,USER_FPSR(%a6) + + clr.l %d0 + mov.b FPCR_MODE(%a6),%d0 # pass rnd mode,prec + + tst.b %d1 + bne.b _L13_2x + bsr.l slogn # operand is a NORM + bra.b _L13_6x +_L13_2x: + cmpi.b %d1,&ZERO # is operand a ZERO? + bne.b _L13_3x # no + bsr.l t_dz2 # yes + bra.b _L13_6x +_L13_3x: + cmpi.b %d1,&INF # is operand an INF? + bne.b _L13_4x # no + bsr.l sopr_inf # yes + bra.b _L13_6x +_L13_4x: + cmpi.b %d1,&QNAN # is operand a QNAN? + bne.b _L13_5x # no + bsr.l src_qnan # yes + bra.b _L13_6x +_L13_5x: + bsr.l slognd # operand is a DENORM +_L13_6x: + +# +# Result is now in FP0 +# + movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 + fmovm.l USER_FPCR(%a6),%fpcr,%fpsr # restore ctrl regs + fmovm.x EXC_FP1(%a6),&0x40 # restore fp1 + unlk %a6 + rts + + +######################################################################### +# MONADIC TEMPLATE # +######################################################################### + global _flog10s_ +_flog10s_: + link %a6,&-LOCAL_SIZE + + movm.l &0x0303,EXC_DREGS(%a6) # save d0-d1/a0-a1 + fmovm.l %fpcr,%fpsr,USER_FPCR(%a6) # save ctrl regs + fmovm.x &0xc0,EXC_FP0(%a6) # save fp0/fp1 + + fmov.l &0x0,%fpcr # zero FPCR + +# +# copy, convert, and tag input argument +# + fmov.s 0x8(%a6),%fp0 # load sgl input + fmov.x %fp0,FP_SRC(%a6) + lea FP_SRC(%a6),%a0 + bsr.l tag # fetch operand type + mov.b %d0,STAG(%a6) + mov.b %d0,%d1 + + andi.l &0x00ff00ff,USER_FPSR(%a6) + + clr.l %d0 + mov.b FPCR_MODE(%a6),%d0 # pass rnd mode,prec + + tst.b %d1 + bne.b _L14_2s + bsr.l slog10 # operand is a NORM + bra.b _L14_6s +_L14_2s: + cmpi.b %d1,&ZERO # is operand a ZERO? + bne.b _L14_3s # no + bsr.l t_dz2 # yes + bra.b _L14_6s +_L14_3s: + cmpi.b %d1,&INF # is operand an INF? + bne.b _L14_4s # no + bsr.l sopr_inf # yes + bra.b _L14_6s +_L14_4s: + cmpi.b %d1,&QNAN # is operand a QNAN? + bne.b _L14_5s # no + bsr.l src_qnan # yes + bra.b _L14_6s +_L14_5s: + bsr.l slog10d # operand is a DENORM +_L14_6s: + +# +# Result is now in FP0 +# + movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 + fmovm.l USER_FPCR(%a6),%fpcr,%fpsr # restore ctrl regs + fmovm.x EXC_FP1(%a6),&0x40 # restore fp1 + unlk %a6 + rts + + global _flog10d_ +_flog10d_: + link %a6,&-LOCAL_SIZE + + movm.l &0x0303,EXC_DREGS(%a6) # save d0-d1/a0-a1 + fmovm.l %fpcr,%fpsr,USER_FPCR(%a6) # save ctrl regs + fmovm.x &0xc0,EXC_FP0(%a6) # save fp0/fp1 + + fmov.l &0x0,%fpcr # zero FPCR + +# +# copy, convert, and tag input argument +# + fmov.d 0x8(%a6),%fp0 # load dbl input + fmov.x %fp0,FP_SRC(%a6) + lea FP_SRC(%a6),%a0 + bsr.l tag # fetch operand type + mov.b %d0,STAG(%a6) + mov.b %d0,%d1 + + andi.l &0x00ff00ff,USER_FPSR(%a6) + + clr.l %d0 + mov.b FPCR_MODE(%a6),%d0 # pass rnd mode,prec + + mov.b %d1,STAG(%a6) + tst.b %d1 + bne.b _L14_2d + bsr.l slog10 # operand is a NORM + bra.b _L14_6d +_L14_2d: + cmpi.b %d1,&ZERO # is operand a ZERO? + bne.b _L14_3d # no + bsr.l t_dz2 # yes + bra.b _L14_6d +_L14_3d: + cmpi.b %d1,&INF # is operand an INF? + bne.b _L14_4d # no + bsr.l sopr_inf # yes + bra.b _L14_6d +_L14_4d: + cmpi.b %d1,&QNAN # is operand a QNAN? + bne.b _L14_5d # no + bsr.l src_qnan # yes + bra.b _L14_6d +_L14_5d: + bsr.l slog10d # operand is a DENORM +_L14_6d: + +# +# Result is now in FP0 +# + movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 + fmovm.l USER_FPCR(%a6),%fpcr,%fpsr # restore ctrl regs + fmovm.x EXC_FP1(%a6),&0x40 # restore fp1 + unlk %a6 + rts + + global _flog10x_ +_flog10x_: + link %a6,&-LOCAL_SIZE + + movm.l &0x0303,EXC_DREGS(%a6) # save d0-d1/a0-a1 + fmovm.l %fpcr,%fpsr,USER_FPCR(%a6) # save ctrl regs + fmovm.x &0xc0,EXC_FP0(%a6) # save fp0/fp1 + + fmov.l &0x0,%fpcr # zero FPCR + +# +# copy, convert, and tag input argument +# + lea FP_SRC(%a6),%a0 + mov.l 0x8+0x0(%a6),0x0(%a0) # load ext input + mov.l 0x8+0x4(%a6),0x4(%a0) + mov.l 0x8+0x8(%a6),0x8(%a0) + bsr.l tag # fetch operand type + mov.b %d0,STAG(%a6) + mov.b %d0,%d1 + + andi.l &0x00ff00ff,USER_FPSR(%a6) + + clr.l %d0 + mov.b FPCR_MODE(%a6),%d0 # pass rnd mode,prec + + tst.b %d1 + bne.b _L14_2x + bsr.l slog10 # operand is a NORM + bra.b _L14_6x +_L14_2x: + cmpi.b %d1,&ZERO # is operand a ZERO? + bne.b _L14_3x # no + bsr.l t_dz2 # yes + bra.b _L14_6x +_L14_3x: + cmpi.b %d1,&INF # is operand an INF? + bne.b _L14_4x # no + bsr.l sopr_inf # yes + bra.b _L14_6x +_L14_4x: + cmpi.b %d1,&QNAN # is operand a QNAN? + bne.b _L14_5x # no + bsr.l src_qnan # yes + bra.b _L14_6x +_L14_5x: + bsr.l slog10d # operand is a DENORM +_L14_6x: + +# +# Result is now in FP0 +# + movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 + fmovm.l USER_FPCR(%a6),%fpcr,%fpsr # restore ctrl regs + fmovm.x EXC_FP1(%a6),&0x40 # restore fp1 + unlk %a6 + rts + + +######################################################################### +# MONADIC TEMPLATE # +######################################################################### + global _flog2s_ +_flog2s_: + link %a6,&-LOCAL_SIZE + + movm.l &0x0303,EXC_DREGS(%a6) # save d0-d1/a0-a1 + fmovm.l %fpcr,%fpsr,USER_FPCR(%a6) # save ctrl regs + fmovm.x &0xc0,EXC_FP0(%a6) # save fp0/fp1 + + fmov.l &0x0,%fpcr # zero FPCR + +# +# copy, convert, and tag input argument +# + fmov.s 0x8(%a6),%fp0 # load sgl input + fmov.x %fp0,FP_SRC(%a6) + lea FP_SRC(%a6),%a0 + bsr.l tag # fetch operand type + mov.b %d0,STAG(%a6) + mov.b %d0,%d1 + + andi.l &0x00ff00ff,USER_FPSR(%a6) + + clr.l %d0 + mov.b FPCR_MODE(%a6),%d0 # pass rnd mode,prec + + tst.b %d1 + bne.b _L15_2s + bsr.l slog2 # operand is a NORM + bra.b _L15_6s +_L15_2s: + cmpi.b %d1,&ZERO # is operand a ZERO? + bne.b _L15_3s # no + bsr.l t_dz2 # yes + bra.b _L15_6s +_L15_3s: + cmpi.b %d1,&INF # is operand an INF? + bne.b _L15_4s # no + bsr.l sopr_inf # yes + bra.b _L15_6s +_L15_4s: + cmpi.b %d1,&QNAN # is operand a QNAN? + bne.b _L15_5s # no + bsr.l src_qnan # yes + bra.b _L15_6s +_L15_5s: + bsr.l slog2d # operand is a DENORM +_L15_6s: + +# +# Result is now in FP0 +# + movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 + fmovm.l USER_FPCR(%a6),%fpcr,%fpsr # restore ctrl regs + fmovm.x EXC_FP1(%a6),&0x40 # restore fp1 + unlk %a6 + rts + + global _flog2d_ +_flog2d_: + link %a6,&-LOCAL_SIZE + + movm.l &0x0303,EXC_DREGS(%a6) # save d0-d1/a0-a1 + fmovm.l %fpcr,%fpsr,USER_FPCR(%a6) # save ctrl regs + fmovm.x &0xc0,EXC_FP0(%a6) # save fp0/fp1 + + fmov.l &0x0,%fpcr # zero FPCR + +# +# copy, convert, and tag input argument +# + fmov.d 0x8(%a6),%fp0 # load dbl input + fmov.x %fp0,FP_SRC(%a6) + lea FP_SRC(%a6),%a0 + bsr.l tag # fetch operand type + mov.b %d0,STAG(%a6) + mov.b %d0,%d1 + + andi.l &0x00ff00ff,USER_FPSR(%a6) + + clr.l %d0 + mov.b FPCR_MODE(%a6),%d0 # pass rnd mode,prec + + mov.b %d1,STAG(%a6) + tst.b %d1 + bne.b _L15_2d + bsr.l slog2 # operand is a NORM + bra.b _L15_6d +_L15_2d: + cmpi.b %d1,&ZERO # is operand a ZERO? + bne.b _L15_3d # no + bsr.l t_dz2 # yes + bra.b _L15_6d +_L15_3d: + cmpi.b %d1,&INF # is operand an INF? + bne.b _L15_4d # no + bsr.l sopr_inf # yes + bra.b _L15_6d +_L15_4d: + cmpi.b %d1,&QNAN # is operand a QNAN? + bne.b _L15_5d # no + bsr.l src_qnan # yes + bra.b _L15_6d +_L15_5d: + bsr.l slog2d # operand is a DENORM +_L15_6d: + +# +# Result is now in FP0 +# + movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 + fmovm.l USER_FPCR(%a6),%fpcr,%fpsr # restore ctrl regs + fmovm.x EXC_FP1(%a6),&0x40 # restore fp1 + unlk %a6 + rts + + global _flog2x_ +_flog2x_: + link %a6,&-LOCAL_SIZE + + movm.l &0x0303,EXC_DREGS(%a6) # save d0-d1/a0-a1 + fmovm.l %fpcr,%fpsr,USER_FPCR(%a6) # save ctrl regs + fmovm.x &0xc0,EXC_FP0(%a6) # save fp0/fp1 + + fmov.l &0x0,%fpcr # zero FPCR + +# +# copy, convert, and tag input argument +# + lea FP_SRC(%a6),%a0 + mov.l 0x8+0x0(%a6),0x0(%a0) # load ext input + mov.l 0x8+0x4(%a6),0x4(%a0) + mov.l 0x8+0x8(%a6),0x8(%a0) + bsr.l tag # fetch operand type + mov.b %d0,STAG(%a6) + mov.b %d0,%d1 + + andi.l &0x00ff00ff,USER_FPSR(%a6) + + clr.l %d0 + mov.b FPCR_MODE(%a6),%d0 # pass rnd mode,prec + + tst.b %d1 + bne.b _L15_2x + bsr.l slog2 # operand is a NORM + bra.b _L15_6x +_L15_2x: + cmpi.b %d1,&ZERO # is operand a ZERO? + bne.b _L15_3x # no + bsr.l t_dz2 # yes + bra.b _L15_6x +_L15_3x: + cmpi.b %d1,&INF # is operand an INF? + bne.b _L15_4x # no + bsr.l sopr_inf # yes + bra.b _L15_6x +_L15_4x: + cmpi.b %d1,&QNAN # is operand a QNAN? + bne.b _L15_5x # no + bsr.l src_qnan # yes + bra.b _L15_6x +_L15_5x: + bsr.l slog2d # operand is a DENORM +_L15_6x: + +# +# Result is now in FP0 +# + movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 + fmovm.l USER_FPCR(%a6),%fpcr,%fpsr # restore ctrl regs + fmovm.x EXC_FP1(%a6),&0x40 # restore fp1 + unlk %a6 + rts + + +######################################################################### +# MONADIC TEMPLATE # +######################################################################### + global _fcoshs_ +_fcoshs_: + link %a6,&-LOCAL_SIZE + + movm.l &0x0303,EXC_DREGS(%a6) # save d0-d1/a0-a1 + fmovm.l %fpcr,%fpsr,USER_FPCR(%a6) # save ctrl regs + fmovm.x &0xc0,EXC_FP0(%a6) # save fp0/fp1 + + fmov.l &0x0,%fpcr # zero FPCR + +# +# copy, convert, and tag input argument +# + fmov.s 0x8(%a6),%fp0 # load sgl input + fmov.x %fp0,FP_SRC(%a6) + lea FP_SRC(%a6),%a0 + bsr.l tag # fetch operand type + mov.b %d0,STAG(%a6) + mov.b %d0,%d1 + + andi.l &0x00ff00ff,USER_FPSR(%a6) + + clr.l %d0 + mov.b FPCR_MODE(%a6),%d0 # pass rnd mode,prec + + tst.b %d1 + bne.b _L16_2s + bsr.l scosh # operand is a NORM + bra.b _L16_6s +_L16_2s: + cmpi.b %d1,&ZERO # is operand a ZERO? + bne.b _L16_3s # no + bsr.l ld_pone # yes + bra.b _L16_6s +_L16_3s: + cmpi.b %d1,&INF # is operand an INF? + bne.b _L16_4s # no + bsr.l ld_pinf # yes + bra.b _L16_6s +_L16_4s: + cmpi.b %d1,&QNAN # is operand a QNAN? + bne.b _L16_5s # no + bsr.l src_qnan # yes + bra.b _L16_6s +_L16_5s: + bsr.l scoshd # operand is a DENORM +_L16_6s: + +# +# Result is now in FP0 +# + movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 + fmovm.l USER_FPCR(%a6),%fpcr,%fpsr # restore ctrl regs + fmovm.x EXC_FP1(%a6),&0x40 # restore fp1 + unlk %a6 + rts + + global _fcoshd_ +_fcoshd_: + link %a6,&-LOCAL_SIZE + + movm.l &0x0303,EXC_DREGS(%a6) # save d0-d1/a0-a1 + fmovm.l %fpcr,%fpsr,USER_FPCR(%a6) # save ctrl regs + fmovm.x &0xc0,EXC_FP0(%a6) # save fp0/fp1 + + fmov.l &0x0,%fpcr # zero FPCR + +# +# copy, convert, and tag input argument +# + fmov.d 0x8(%a6),%fp0 # load dbl input + fmov.x %fp0,FP_SRC(%a6) + lea FP_SRC(%a6),%a0 + bsr.l tag # fetch operand type + mov.b %d0,STAG(%a6) + mov.b %d0,%d1 + + andi.l &0x00ff00ff,USER_FPSR(%a6) + + clr.l %d0 + mov.b FPCR_MODE(%a6),%d0 # pass rnd mode,prec + + mov.b %d1,STAG(%a6) + tst.b %d1 + bne.b _L16_2d + bsr.l scosh # operand is a NORM + bra.b _L16_6d +_L16_2d: + cmpi.b %d1,&ZERO # is operand a ZERO? + bne.b _L16_3d # no + bsr.l ld_pone # yes + bra.b _L16_6d +_L16_3d: + cmpi.b %d1,&INF # is operand an INF? + bne.b _L16_4d # no + bsr.l ld_pinf # yes + bra.b _L16_6d +_L16_4d: + cmpi.b %d1,&QNAN # is operand a QNAN? + bne.b _L16_5d # no + bsr.l src_qnan # yes + bra.b _L16_6d +_L16_5d: + bsr.l scoshd # operand is a DENORM +_L16_6d: + +# +# Result is now in FP0 +# + movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 + fmovm.l USER_FPCR(%a6),%fpcr,%fpsr # restore ctrl regs + fmovm.x EXC_FP1(%a6),&0x40 # restore fp1 + unlk %a6 + rts + + global _fcoshx_ +_fcoshx_: + link %a6,&-LOCAL_SIZE + + movm.l &0x0303,EXC_DREGS(%a6) # save d0-d1/a0-a1 + fmovm.l %fpcr,%fpsr,USER_FPCR(%a6) # save ctrl regs + fmovm.x &0xc0,EXC_FP0(%a6) # save fp0/fp1 + + fmov.l &0x0,%fpcr # zero FPCR + +# +# copy, convert, and tag input argument +# + lea FP_SRC(%a6),%a0 + mov.l 0x8+0x0(%a6),0x0(%a0) # load ext input + mov.l 0x8+0x4(%a6),0x4(%a0) + mov.l 0x8+0x8(%a6),0x8(%a0) + bsr.l tag # fetch operand type + mov.b %d0,STAG(%a6) + mov.b %d0,%d1 + + andi.l &0x00ff00ff,USER_FPSR(%a6) + + clr.l %d0 + mov.b FPCR_MODE(%a6),%d0 # pass rnd mode,prec + + tst.b %d1 + bne.b _L16_2x + bsr.l scosh # operand is a NORM + bra.b _L16_6x +_L16_2x: + cmpi.b %d1,&ZERO # is operand a ZERO? + bne.b _L16_3x # no + bsr.l ld_pone # yes + bra.b _L16_6x +_L16_3x: + cmpi.b %d1,&INF # is operand an INF? + bne.b _L16_4x # no + bsr.l ld_pinf # yes + bra.b _L16_6x +_L16_4x: + cmpi.b %d1,&QNAN # is operand a QNAN? + bne.b _L16_5x # no + bsr.l src_qnan # yes + bra.b _L16_6x +_L16_5x: + bsr.l scoshd # operand is a DENORM +_L16_6x: + +# +# Result is now in FP0 +# + movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 + fmovm.l USER_FPCR(%a6),%fpcr,%fpsr # restore ctrl regs + fmovm.x EXC_FP1(%a6),&0x40 # restore fp1 + unlk %a6 + rts + + +######################################################################### +# MONADIC TEMPLATE # +######################################################################### + global _facoss_ +_facoss_: + link %a6,&-LOCAL_SIZE + + movm.l &0x0303,EXC_DREGS(%a6) # save d0-d1/a0-a1 + fmovm.l %fpcr,%fpsr,USER_FPCR(%a6) # save ctrl regs + fmovm.x &0xc0,EXC_FP0(%a6) # save fp0/fp1 + + fmov.l &0x0,%fpcr # zero FPCR + +# +# copy, convert, and tag input argument +# + fmov.s 0x8(%a6),%fp0 # load sgl input + fmov.x %fp0,FP_SRC(%a6) + lea FP_SRC(%a6),%a0 + bsr.l tag # fetch operand type + mov.b %d0,STAG(%a6) + mov.b %d0,%d1 + + andi.l &0x00ff00ff,USER_FPSR(%a6) + + clr.l %d0 + mov.b FPCR_MODE(%a6),%d0 # pass rnd mode,prec + + tst.b %d1 + bne.b _L17_2s + bsr.l sacos # operand is a NORM + bra.b _L17_6s +_L17_2s: + cmpi.b %d1,&ZERO # is operand a ZERO? + bne.b _L17_3s # no + bsr.l ld_ppi2 # yes + bra.b _L17_6s +_L17_3s: + cmpi.b %d1,&INF # is operand an INF? + bne.b _L17_4s # no + bsr.l t_operr # yes + bra.b _L17_6s +_L17_4s: + cmpi.b %d1,&QNAN # is operand a QNAN? + bne.b _L17_5s # no + bsr.l src_qnan # yes + bra.b _L17_6s +_L17_5s: + bsr.l sacosd # operand is a DENORM +_L17_6s: + +# +# Result is now in FP0 +# + movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 + fmovm.l USER_FPCR(%a6),%fpcr,%fpsr # restore ctrl regs + fmovm.x EXC_FP1(%a6),&0x40 # restore fp1 + unlk %a6 + rts + + global _facosd_ +_facosd_: + link %a6,&-LOCAL_SIZE + + movm.l &0x0303,EXC_DREGS(%a6) # save d0-d1/a0-a1 + fmovm.l %fpcr,%fpsr,USER_FPCR(%a6) # save ctrl regs + fmovm.x &0xc0,EXC_FP0(%a6) # save fp0/fp1 + + fmov.l &0x0,%fpcr # zero FPCR + +# +# copy, convert, and tag input argument +# + fmov.d 0x8(%a6),%fp0 # load dbl input + fmov.x %fp0,FP_SRC(%a6) + lea FP_SRC(%a6),%a0 + bsr.l tag # fetch operand type + mov.b %d0,STAG(%a6) + mov.b %d0,%d1 + + andi.l &0x00ff00ff,USER_FPSR(%a6) + + clr.l %d0 + mov.b FPCR_MODE(%a6),%d0 # pass rnd mode,prec + + mov.b %d1,STAG(%a6) + tst.b %d1 + bne.b _L17_2d + bsr.l sacos # operand is a NORM + bra.b _L17_6d +_L17_2d: + cmpi.b %d1,&ZERO # is operand a ZERO? + bne.b _L17_3d # no + bsr.l ld_ppi2 # yes + bra.b _L17_6d +_L17_3d: + cmpi.b %d1,&INF # is operand an INF? + bne.b _L17_4d # no + bsr.l t_operr # yes + bra.b _L17_6d +_L17_4d: + cmpi.b %d1,&QNAN # is operand a QNAN? + bne.b _L17_5d # no + bsr.l src_qnan # yes + bra.b _L17_6d +_L17_5d: + bsr.l sacosd # operand is a DENORM +_L17_6d: + +# +# Result is now in FP0 +# + movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 + fmovm.l USER_FPCR(%a6),%fpcr,%fpsr # restore ctrl regs + fmovm.x EXC_FP1(%a6),&0x40 # restore fp1 + unlk %a6 + rts + + global _facosx_ +_facosx_: + link %a6,&-LOCAL_SIZE + + movm.l &0x0303,EXC_DREGS(%a6) # save d0-d1/a0-a1 + fmovm.l %fpcr,%fpsr,USER_FPCR(%a6) # save ctrl regs + fmovm.x &0xc0,EXC_FP0(%a6) # save fp0/fp1 + + fmov.l &0x0,%fpcr # zero FPCR + +# +# copy, convert, and tag input argument +# + lea FP_SRC(%a6),%a0 + mov.l 0x8+0x0(%a6),0x0(%a0) # load ext input + mov.l 0x8+0x4(%a6),0x4(%a0) + mov.l 0x8+0x8(%a6),0x8(%a0) + bsr.l tag # fetch operand type + mov.b %d0,STAG(%a6) + mov.b %d0,%d1 + + andi.l &0x00ff00ff,USER_FPSR(%a6) + + clr.l %d0 + mov.b FPCR_MODE(%a6),%d0 # pass rnd mode,prec + + tst.b %d1 + bne.b _L17_2x + bsr.l sacos # operand is a NORM + bra.b _L17_6x +_L17_2x: + cmpi.b %d1,&ZERO # is operand a ZERO? + bne.b _L17_3x # no + bsr.l ld_ppi2 # yes + bra.b _L17_6x +_L17_3x: + cmpi.b %d1,&INF # is operand an INF? + bne.b _L17_4x # no + bsr.l t_operr # yes + bra.b _L17_6x +_L17_4x: + cmpi.b %d1,&QNAN # is operand a QNAN? + bne.b _L17_5x # no + bsr.l src_qnan # yes + bra.b _L17_6x +_L17_5x: + bsr.l sacosd # operand is a DENORM +_L17_6x: + +# +# Result is now in FP0 +# + movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 + fmovm.l USER_FPCR(%a6),%fpcr,%fpsr # restore ctrl regs + fmovm.x EXC_FP1(%a6),&0x40 # restore fp1 + unlk %a6 + rts + + +######################################################################### +# MONADIC TEMPLATE # +######################################################################### + global _fgetexps_ +_fgetexps_: + link %a6,&-LOCAL_SIZE + + movm.l &0x0303,EXC_DREGS(%a6) # save d0-d1/a0-a1 + fmovm.l %fpcr,%fpsr,USER_FPCR(%a6) # save ctrl regs + fmovm.x &0xc0,EXC_FP0(%a6) # save fp0/fp1 + + fmov.l &0x0,%fpcr # zero FPCR + +# +# copy, convert, and tag input argument +# + fmov.s 0x8(%a6),%fp0 # load sgl input + fmov.x %fp0,FP_SRC(%a6) + lea FP_SRC(%a6),%a0 + bsr.l tag # fetch operand type + mov.b %d0,STAG(%a6) + mov.b %d0,%d1 + + andi.l &0x00ff00ff,USER_FPSR(%a6) + + clr.l %d0 + mov.b FPCR_MODE(%a6),%d0 # pass rnd mode,prec + + tst.b %d1 + bne.b _L18_2s + bsr.l sgetexp # operand is a NORM + bra.b _L18_6s +_L18_2s: + cmpi.b %d1,&ZERO # is operand a ZERO? + bne.b _L18_3s # no + bsr.l src_zero # yes + bra.b _L18_6s +_L18_3s: + cmpi.b %d1,&INF # is operand an INF? + bne.b _L18_4s # no + bsr.l t_operr # yes + bra.b _L18_6s +_L18_4s: + cmpi.b %d1,&QNAN # is operand a QNAN? + bne.b _L18_5s # no + bsr.l src_qnan # yes + bra.b _L18_6s +_L18_5s: + bsr.l sgetexpd # operand is a DENORM +_L18_6s: + +# +# Result is now in FP0 +# + movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 + fmovm.l USER_FPCR(%a6),%fpcr,%fpsr # restore ctrl regs + fmovm.x EXC_FP1(%a6),&0x40 # restore fp1 + unlk %a6 + rts + + global _fgetexpd_ +_fgetexpd_: + link %a6,&-LOCAL_SIZE + + movm.l &0x0303,EXC_DREGS(%a6) # save d0-d1/a0-a1 + fmovm.l %fpcr,%fpsr,USER_FPCR(%a6) # save ctrl regs + fmovm.x &0xc0,EXC_FP0(%a6) # save fp0/fp1 + + fmov.l &0x0,%fpcr # zero FPCR + +# +# copy, convert, and tag input argument +# + fmov.d 0x8(%a6),%fp0 # load dbl input + fmov.x %fp0,FP_SRC(%a6) + lea FP_SRC(%a6),%a0 + bsr.l tag # fetch operand type + mov.b %d0,STAG(%a6) + mov.b %d0,%d1 + + andi.l &0x00ff00ff,USER_FPSR(%a6) + + clr.l %d0 + mov.b FPCR_MODE(%a6),%d0 # pass rnd mode,prec + + mov.b %d1,STAG(%a6) + tst.b %d1 + bne.b _L18_2d + bsr.l sgetexp # operand is a NORM + bra.b _L18_6d +_L18_2d: + cmpi.b %d1,&ZERO # is operand a ZERO? + bne.b _L18_3d # no + bsr.l src_zero # yes + bra.b _L18_6d +_L18_3d: + cmpi.b %d1,&INF # is operand an INF? + bne.b _L18_4d # no + bsr.l t_operr # yes + bra.b _L18_6d +_L18_4d: + cmpi.b %d1,&QNAN # is operand a QNAN? + bne.b _L18_5d # no + bsr.l src_qnan # yes + bra.b _L18_6d +_L18_5d: + bsr.l sgetexpd # operand is a DENORM +_L18_6d: + +# +# Result is now in FP0 +# + movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 + fmovm.l USER_FPCR(%a6),%fpcr,%fpsr # restore ctrl regs + fmovm.x EXC_FP1(%a6),&0x40 # restore fp1 + unlk %a6 + rts + + global _fgetexpx_ +_fgetexpx_: + link %a6,&-LOCAL_SIZE + + movm.l &0x0303,EXC_DREGS(%a6) # save d0-d1/a0-a1 + fmovm.l %fpcr,%fpsr,USER_FPCR(%a6) # save ctrl regs + fmovm.x &0xc0,EXC_FP0(%a6) # save fp0/fp1 + + fmov.l &0x0,%fpcr # zero FPCR + +# +# copy, convert, and tag input argument +# + lea FP_SRC(%a6),%a0 + mov.l 0x8+0x0(%a6),0x0(%a0) # load ext input + mov.l 0x8+0x4(%a6),0x4(%a0) + mov.l 0x8+0x8(%a6),0x8(%a0) + bsr.l tag # fetch operand type + mov.b %d0,STAG(%a6) + mov.b %d0,%d1 + + andi.l &0x00ff00ff,USER_FPSR(%a6) + + clr.l %d0 + mov.b FPCR_MODE(%a6),%d0 # pass rnd mode,prec + + tst.b %d1 + bne.b _L18_2x + bsr.l sgetexp # operand is a NORM + bra.b _L18_6x +_L18_2x: + cmpi.b %d1,&ZERO # is operand a ZERO? + bne.b _L18_3x # no + bsr.l src_zero # yes + bra.b _L18_6x +_L18_3x: + cmpi.b %d1,&INF # is operand an INF? + bne.b _L18_4x # no + bsr.l t_operr # yes + bra.b _L18_6x +_L18_4x: + cmpi.b %d1,&QNAN # is operand a QNAN? + bne.b _L18_5x # no + bsr.l src_qnan # yes + bra.b _L18_6x +_L18_5x: + bsr.l sgetexpd # operand is a DENORM +_L18_6x: + +# +# Result is now in FP0 +# + movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 + fmovm.l USER_FPCR(%a6),%fpcr,%fpsr # restore ctrl regs + fmovm.x EXC_FP1(%a6),&0x40 # restore fp1 + unlk %a6 + rts + + +######################################################################### +# MONADIC TEMPLATE # +######################################################################### + global _fgetmans_ +_fgetmans_: + link %a6,&-LOCAL_SIZE + + movm.l &0x0303,EXC_DREGS(%a6) # save d0-d1/a0-a1 + fmovm.l %fpcr,%fpsr,USER_FPCR(%a6) # save ctrl regs + fmovm.x &0xc0,EXC_FP0(%a6) # save fp0/fp1 + + fmov.l &0x0,%fpcr # zero FPCR + +# +# copy, convert, and tag input argument +# + fmov.s 0x8(%a6),%fp0 # load sgl input + fmov.x %fp0,FP_SRC(%a6) + lea FP_SRC(%a6),%a0 + bsr.l tag # fetch operand type + mov.b %d0,STAG(%a6) + mov.b %d0,%d1 + + andi.l &0x00ff00ff,USER_FPSR(%a6) + + clr.l %d0 + mov.b FPCR_MODE(%a6),%d0 # pass rnd mode,prec + + tst.b %d1 + bne.b _L19_2s + bsr.l sgetman # operand is a NORM + bra.b _L19_6s +_L19_2s: + cmpi.b %d1,&ZERO # is operand a ZERO? + bne.b _L19_3s # no + bsr.l src_zero # yes + bra.b _L19_6s +_L19_3s: + cmpi.b %d1,&INF # is operand an INF? + bne.b _L19_4s # no + bsr.l t_operr # yes + bra.b _L19_6s +_L19_4s: + cmpi.b %d1,&QNAN # is operand a QNAN? + bne.b _L19_5s # no + bsr.l src_qnan # yes + bra.b _L19_6s +_L19_5s: + bsr.l sgetmand # operand is a DENORM +_L19_6s: + +# +# Result is now in FP0 +# + movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 + fmovm.l USER_FPCR(%a6),%fpcr,%fpsr # restore ctrl regs + fmovm.x EXC_FP1(%a6),&0x40 # restore fp1 + unlk %a6 + rts + + global _fgetmand_ +_fgetmand_: + link %a6,&-LOCAL_SIZE + + movm.l &0x0303,EXC_DREGS(%a6) # save d0-d1/a0-a1 + fmovm.l %fpcr,%fpsr,USER_FPCR(%a6) # save ctrl regs + fmovm.x &0xc0,EXC_FP0(%a6) # save fp0/fp1 + + fmov.l &0x0,%fpcr # zero FPCR + +# +# copy, convert, and tag input argument +# + fmov.d 0x8(%a6),%fp0 # load dbl input + fmov.x %fp0,FP_SRC(%a6) + lea FP_SRC(%a6),%a0 + bsr.l tag # fetch operand type + mov.b %d0,STAG(%a6) + mov.b %d0,%d1 + + andi.l &0x00ff00ff,USER_FPSR(%a6) + + clr.l %d0 + mov.b FPCR_MODE(%a6),%d0 # pass rnd mode,prec + + mov.b %d1,STAG(%a6) + tst.b %d1 + bne.b _L19_2d + bsr.l sgetman # operand is a NORM + bra.b _L19_6d +_L19_2d: + cmpi.b %d1,&ZERO # is operand a ZERO? + bne.b _L19_3d # no + bsr.l src_zero # yes + bra.b _L19_6d +_L19_3d: + cmpi.b %d1,&INF # is operand an INF? + bne.b _L19_4d # no + bsr.l t_operr # yes + bra.b _L19_6d +_L19_4d: + cmpi.b %d1,&QNAN # is operand a QNAN? + bne.b _L19_5d # no + bsr.l src_qnan # yes + bra.b _L19_6d +_L19_5d: + bsr.l sgetmand # operand is a DENORM +_L19_6d: + +# +# Result is now in FP0 +# + movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 + fmovm.l USER_FPCR(%a6),%fpcr,%fpsr # restore ctrl regs + fmovm.x EXC_FP1(%a6),&0x40 # restore fp1 + unlk %a6 + rts + + global _fgetmanx_ +_fgetmanx_: + link %a6,&-LOCAL_SIZE + + movm.l &0x0303,EXC_DREGS(%a6) # save d0-d1/a0-a1 + fmovm.l %fpcr,%fpsr,USER_FPCR(%a6) # save ctrl regs + fmovm.x &0xc0,EXC_FP0(%a6) # save fp0/fp1 + + fmov.l &0x0,%fpcr # zero FPCR + +# +# copy, convert, and tag input argument +# + lea FP_SRC(%a6),%a0 + mov.l 0x8+0x0(%a6),0x0(%a0) # load ext input + mov.l 0x8+0x4(%a6),0x4(%a0) + mov.l 0x8+0x8(%a6),0x8(%a0) + bsr.l tag # fetch operand type + mov.b %d0,STAG(%a6) + mov.b %d0,%d1 + + andi.l &0x00ff00ff,USER_FPSR(%a6) + + clr.l %d0 + mov.b FPCR_MODE(%a6),%d0 # pass rnd mode,prec + + tst.b %d1 + bne.b _L19_2x + bsr.l sgetman # operand is a NORM + bra.b _L19_6x +_L19_2x: + cmpi.b %d1,&ZERO # is operand a ZERO? + bne.b _L19_3x # no + bsr.l src_zero # yes + bra.b _L19_6x +_L19_3x: + cmpi.b %d1,&INF # is operand an INF? + bne.b _L19_4x # no + bsr.l t_operr # yes + bra.b _L19_6x +_L19_4x: + cmpi.b %d1,&QNAN # is operand a QNAN? + bne.b _L19_5x # no + bsr.l src_qnan # yes + bra.b _L19_6x +_L19_5x: + bsr.l sgetmand # operand is a DENORM +_L19_6x: + +# +# Result is now in FP0 +# + movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 + fmovm.l USER_FPCR(%a6),%fpcr,%fpsr # restore ctrl regs + fmovm.x EXC_FP1(%a6),&0x40 # restore fp1 + unlk %a6 + rts + + +######################################################################### +# MONADIC TEMPLATE # +######################################################################### + global _fsincoss_ +_fsincoss_: + link %a6,&-LOCAL_SIZE + + movm.l &0x0303,EXC_DREGS(%a6) # save d0-d1/a0-a1 + fmovm.l %fpcr,%fpsr,USER_FPCR(%a6) # save ctrl regs + fmovm.x &0xc0,EXC_FP0(%a6) # save fp0/fp1 + + fmov.l &0x0,%fpcr # zero FPCR + +# +# copy, convert, and tag input argument +# + fmov.s 0x8(%a6),%fp0 # load sgl input + fmov.x %fp0,FP_SRC(%a6) + lea FP_SRC(%a6),%a0 + bsr.l tag # fetch operand type + mov.b %d0,STAG(%a6) + mov.b %d0,%d1 + + andi.l &0x00ff00ff,USER_FPSR(%a6) + + clr.l %d0 + mov.b FPCR_MODE(%a6),%d0 # pass rnd mode,prec + + tst.b %d1 + bne.b _L20_2s + bsr.l ssincos # operand is a NORM + bra.b _L20_6s +_L20_2s: + cmpi.b %d1,&ZERO # is operand a ZERO? + bne.b _L20_3s # no + bsr.l ssincosz # yes + bra.b _L20_6s +_L20_3s: + cmpi.b %d1,&INF # is operand an INF? + bne.b _L20_4s # no + bsr.l ssincosi # yes + bra.b _L20_6s +_L20_4s: + cmpi.b %d1,&QNAN # is operand a QNAN? + bne.b _L20_5s # no + bsr.l ssincosqnan # yes + bra.b _L20_6s +_L20_5s: + bsr.l ssincosd # operand is a DENORM +_L20_6s: + +# +# Result is now in FP0 +# + movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 + fmovm.l USER_FPCR(%a6),%fpcr,%fpsr # restore ctrl regs + fmovm.x &0x03,-(%sp) # store off fp0/fp1 + fmovm.x (%sp)+,&0x40 # fp0 now in fp1 + fmovm.x (%sp)+,&0x80 # fp1 now in fp0 + unlk %a6 + rts + + global _fsincosd_ +_fsincosd_: + link %a6,&-LOCAL_SIZE + + movm.l &0x0303,EXC_DREGS(%a6) # save d0-d1/a0-a1 + fmovm.l %fpcr,%fpsr,USER_FPCR(%a6) # save ctrl regs + fmovm.x &0xc0,EXC_FP0(%a6) # save fp0/fp1 + + fmov.l &0x0,%fpcr # zero FPCR + +# +# copy, convert, and tag input argument +# + fmov.d 0x8(%a6),%fp0 # load dbl input + fmov.x %fp0,FP_SRC(%a6) + lea FP_SRC(%a6),%a0 + bsr.l tag # fetch operand type + mov.b %d0,STAG(%a6) + mov.b %d0,%d1 + + andi.l &0x00ff00ff,USER_FPSR(%a6) + + clr.l %d0 + mov.b FPCR_MODE(%a6),%d0 # pass rnd mode,prec + + mov.b %d1,STAG(%a6) + tst.b %d1 + bne.b _L20_2d + bsr.l ssincos # operand is a NORM + bra.b _L20_6d +_L20_2d: + cmpi.b %d1,&ZERO # is operand a ZERO? + bne.b _L20_3d # no + bsr.l ssincosz # yes + bra.b _L20_6d +_L20_3d: + cmpi.b %d1,&INF # is operand an INF? + bne.b _L20_4d # no + bsr.l ssincosi # yes + bra.b _L20_6d +_L20_4d: + cmpi.b %d1,&QNAN # is operand a QNAN? + bne.b _L20_5d # no + bsr.l ssincosqnan # yes + bra.b _L20_6d +_L20_5d: + bsr.l ssincosd # operand is a DENORM +_L20_6d: + +# +# Result is now in FP0 +# + movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 + fmovm.l USER_FPCR(%a6),%fpcr,%fpsr # restore ctrl regs + fmovm.x &0x03,-(%sp) # store off fp0/fp1 + fmovm.x (%sp)+,&0x40 # fp0 now in fp1 + fmovm.x (%sp)+,&0x80 # fp1 now in fp0 + unlk %a6 + rts + + global _fsincosx_ +_fsincosx_: + link %a6,&-LOCAL_SIZE + + movm.l &0x0303,EXC_DREGS(%a6) # save d0-d1/a0-a1 + fmovm.l %fpcr,%fpsr,USER_FPCR(%a6) # save ctrl regs + fmovm.x &0xc0,EXC_FP0(%a6) # save fp0/fp1 + + fmov.l &0x0,%fpcr # zero FPCR + +# +# copy, convert, and tag input argument +# + lea FP_SRC(%a6),%a0 + mov.l 0x8+0x0(%a6),0x0(%a0) # load ext input + mov.l 0x8+0x4(%a6),0x4(%a0) + mov.l 0x8+0x8(%a6),0x8(%a0) + bsr.l tag # fetch operand type + mov.b %d0,STAG(%a6) + mov.b %d0,%d1 + + andi.l &0x00ff00ff,USER_FPSR(%a6) + + clr.l %d0 + mov.b FPCR_MODE(%a6),%d0 # pass rnd mode,prec + + tst.b %d1 + bne.b _L20_2x + bsr.l ssincos # operand is a NORM + bra.b _L20_6x +_L20_2x: + cmpi.b %d1,&ZERO # is operand a ZERO? + bne.b _L20_3x # no + bsr.l ssincosz # yes + bra.b _L20_6x +_L20_3x: + cmpi.b %d1,&INF # is operand an INF? + bne.b _L20_4x # no + bsr.l ssincosi # yes + bra.b _L20_6x +_L20_4x: + cmpi.b %d1,&QNAN # is operand a QNAN? + bne.b _L20_5x # no + bsr.l ssincosqnan # yes + bra.b _L20_6x +_L20_5x: + bsr.l ssincosd # operand is a DENORM +_L20_6x: + +# +# Result is now in FP0 +# + movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 + fmovm.l USER_FPCR(%a6),%fpcr,%fpsr # restore ctrl regs + fmovm.x &0x03,-(%sp) # store off fp0/fp1 + fmovm.x (%sp)+,&0x40 # fp0 now in fp1 + fmovm.x (%sp)+,&0x80 # fp1 now in fp0 + unlk %a6 + rts + + +######################################################################### +# DYADIC TEMPLATE # +######################################################################### + global _frems_ +_frems_: + link %a6,&-LOCAL_SIZE + + movm.l &0x0303,EXC_DREGS(%a6) # save d0-d1/a0-a1 + fmovm.l %fpcr,%fpsr,USER_FPCR(%a6) # save ctrl regs + fmovm.x &0xc0,EXC_FP0(%a6) # save fp0/fp1 + + fmov.l &0x0,%fpcr # zero FPCR + +# +# copy, convert, and tag input argument +# + fmov.s 0x8(%a6),%fp0 # load sgl dst + fmov.x %fp0,FP_DST(%a6) + lea FP_DST(%a6),%a0 + bsr.l tag # fetch operand type + mov.b %d0,DTAG(%a6) + + fmov.s 0xc(%a6),%fp0 # load sgl src + fmov.x %fp0,FP_SRC(%a6) + lea FP_SRC(%a6),%a0 + bsr.l tag # fetch operand type + mov.b %d0,STAG(%a6) + mov.l %d0,%d1 + + andi.l &0x00ff00ff,USER_FPSR(%a6) + + clr.l %d0 + mov.b FPCR_MODE(%a6),%d0 # pass rnd mode,prec + + lea FP_SRC(%a6),%a0 # pass ptr to src + lea FP_DST(%a6),%a1 # pass ptr to dst + + tst.b %d1 + bne.b _L21_2s + bsr.l srem_snorm # operand is a NORM + bra.b _L21_6s +_L21_2s: + cmpi.b %d1,&ZERO # is operand a ZERO? + bne.b _L21_3s # no + bsr.l srem_szero # yes + bra.b _L21_6s +_L21_3s: + cmpi.b %d1,&INF # is operand an INF? + bne.b _L21_4s # no + bsr.l srem_sinf # yes + bra.b _L21_6s +_L21_4s: + cmpi.b %d1,&QNAN # is operand a QNAN? + bne.b _L21_5s # no + bsr.l sop_sqnan # yes + bra.b _L21_6s +_L21_5s: + bsr.l srem_sdnrm # operand is a DENORM +_L21_6s: + +# +# Result is now in FP0 +# + movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 + fmovm.l USER_FPCR(%a6),%fpcr,%fpsr # restore ctrl regs + fmovm.x EXC_FP1(%a6),&0x40 # restore fp1 + unlk %a6 + rts + + global _fremd_ +_fremd_: + link %a6,&-LOCAL_SIZE + + movm.l &0x0303,EXC_DREGS(%a6) # save d0-d1/a0-a1 + fmovm.l %fpcr,%fpsr,USER_FPCR(%a6) # save ctrl regs + fmovm.x &0xc0,EXC_FP0(%a6) # save fp0/fp1 + + fmov.l &0x0,%fpcr # zero FPCR + +# +# copy, convert, and tag input argument +# + fmov.d 0x8(%a6),%fp0 # load dbl dst + fmov.x %fp0,FP_DST(%a6) + lea FP_DST(%a6),%a0 + bsr.l tag # fetch operand type + mov.b %d0,DTAG(%a6) + + fmov.d 0x10(%a6),%fp0 # load dbl src + fmov.x %fp0,FP_SRC(%a6) + lea FP_SRC(%a6),%a0 + bsr.l tag # fetch operand type + mov.b %d0,STAG(%a6) + mov.l %d0,%d1 + + andi.l &0x00ff00ff,USER_FPSR(%a6) + + clr.l %d0 + mov.b FPCR_MODE(%a6),%d0 # pass rnd mode,prec + + lea FP_SRC(%a6),%a0 # pass ptr to src + lea FP_DST(%a6),%a1 # pass ptr to dst + + tst.b %d1 + bne.b _L21_2d + bsr.l srem_snorm # operand is a NORM + bra.b _L21_6d +_L21_2d: + cmpi.b %d1,&ZERO # is operand a ZERO? + bne.b _L21_3d # no + bsr.l srem_szero # yes + bra.b _L21_6d +_L21_3d: + cmpi.b %d1,&INF # is operand an INF? + bne.b _L21_4d # no + bsr.l srem_sinf # yes + bra.b _L21_6d +_L21_4d: + cmpi.b %d1,&QNAN # is operand a QNAN? + bne.b _L21_5d # no + bsr.l sop_sqnan # yes + bra.b _L21_6d +_L21_5d: + bsr.l srem_sdnrm # operand is a DENORM +_L21_6d: + +# +# Result is now in FP0 +# + movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 + fmovm.l USER_FPCR(%a6),%fpcr,%fpsr # restore ctrl regs + fmovm.x EXC_FP1(%a6),&0x40 # restore fp1 + unlk %a6 + rts + + global _fremx_ +_fremx_: + link %a6,&-LOCAL_SIZE + + movm.l &0x0303,EXC_DREGS(%a6) # save d0-d1/a0-a1 + fmovm.l %fpcr,%fpsr,USER_FPCR(%a6) # save ctrl regs + fmovm.x &0xc0,EXC_FP0(%a6) # save fp0/fp1 + + fmov.l &0x0,%fpcr # zero FPCR + +# +# copy, convert, and tag input argument +# + lea FP_DST(%a6),%a0 + mov.l 0x8+0x0(%a6),0x0(%a0) # load ext dst + mov.l 0x8+0x4(%a6),0x4(%a0) + mov.l 0x8+0x8(%a6),0x8(%a0) + bsr.l tag # fetch operand type + mov.b %d0,DTAG(%a6) + + lea FP_SRC(%a6),%a0 + mov.l 0x14+0x0(%a6),0x0(%a0) # load ext src + mov.l 0x14+0x4(%a6),0x4(%a0) + mov.l 0x14+0x8(%a6),0x8(%a0) + bsr.l tag # fetch operand type + mov.b %d0,STAG(%a6) + mov.l %d0,%d1 + + andi.l &0x00ff00ff,USER_FPSR(%a6) + + clr.l %d0 + mov.b FPCR_MODE(%a6),%d0 # pass rnd mode,prec + + lea FP_SRC(%a6),%a0 # pass ptr to src + lea FP_DST(%a6),%a1 # pass ptr to dst + + tst.b %d1 + bne.b _L21_2x + bsr.l srem_snorm # operand is a NORM + bra.b _L21_6x +_L21_2x: + cmpi.b %d1,&ZERO # is operand a ZERO? + bne.b _L21_3x # no + bsr.l srem_szero # yes + bra.b _L21_6x +_L21_3x: + cmpi.b %d1,&INF # is operand an INF? + bne.b _L21_4x # no + bsr.l srem_sinf # yes + bra.b _L21_6x +_L21_4x: + cmpi.b %d1,&QNAN # is operand a QNAN? + bne.b _L21_5x # no + bsr.l sop_sqnan # yes + bra.b _L21_6x +_L21_5x: + bsr.l srem_sdnrm # operand is a DENORM +_L21_6x: + +# +# Result is now in FP0 +# + movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 + fmovm.l USER_FPCR(%a6),%fpcr,%fpsr # restore ctrl regs + fmovm.x EXC_FP1(%a6),&0x40 # restore fp1 + unlk %a6 + rts + + +######################################################################### +# DYADIC TEMPLATE # +######################################################################### + global _fmods_ +_fmods_: + link %a6,&-LOCAL_SIZE + + movm.l &0x0303,EXC_DREGS(%a6) # save d0-d1/a0-a1 + fmovm.l %fpcr,%fpsr,USER_FPCR(%a6) # save ctrl regs + fmovm.x &0xc0,EXC_FP0(%a6) # save fp0/fp1 + + fmov.l &0x0,%fpcr # zero FPCR + +# +# copy, convert, and tag input argument +# + fmov.s 0x8(%a6),%fp0 # load sgl dst + fmov.x %fp0,FP_DST(%a6) + lea FP_DST(%a6),%a0 + bsr.l tag # fetch operand type + mov.b %d0,DTAG(%a6) + + fmov.s 0xc(%a6),%fp0 # load sgl src + fmov.x %fp0,FP_SRC(%a6) + lea FP_SRC(%a6),%a0 + bsr.l tag # fetch operand type + mov.b %d0,STAG(%a6) + mov.l %d0,%d1 + + andi.l &0x00ff00ff,USER_FPSR(%a6) + + clr.l %d0 + mov.b FPCR_MODE(%a6),%d0 # pass rnd mode,prec + + lea FP_SRC(%a6),%a0 # pass ptr to src + lea FP_DST(%a6),%a1 # pass ptr to dst + + tst.b %d1 + bne.b _L22_2s + bsr.l smod_snorm # operand is a NORM + bra.b _L22_6s +_L22_2s: + cmpi.b %d1,&ZERO # is operand a ZERO? + bne.b _L22_3s # no + bsr.l smod_szero # yes + bra.b _L22_6s +_L22_3s: + cmpi.b %d1,&INF # is operand an INF? + bne.b _L22_4s # no + bsr.l smod_sinf # yes + bra.b _L22_6s +_L22_4s: + cmpi.b %d1,&QNAN # is operand a QNAN? + bne.b _L22_5s # no + bsr.l sop_sqnan # yes + bra.b _L22_6s +_L22_5s: + bsr.l smod_sdnrm # operand is a DENORM +_L22_6s: + +# +# Result is now in FP0 +# + movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 + fmovm.l USER_FPCR(%a6),%fpcr,%fpsr # restore ctrl regs + fmovm.x EXC_FP1(%a6),&0x40 # restore fp1 + unlk %a6 + rts + + global _fmodd_ +_fmodd_: + link %a6,&-LOCAL_SIZE + + movm.l &0x0303,EXC_DREGS(%a6) # save d0-d1/a0-a1 + fmovm.l %fpcr,%fpsr,USER_FPCR(%a6) # save ctrl regs + fmovm.x &0xc0,EXC_FP0(%a6) # save fp0/fp1 + + fmov.l &0x0,%fpcr # zero FPCR + +# +# copy, convert, and tag input argument +# + fmov.d 0x8(%a6),%fp0 # load dbl dst + fmov.x %fp0,FP_DST(%a6) + lea FP_DST(%a6),%a0 + bsr.l tag # fetch operand type + mov.b %d0,DTAG(%a6) + + fmov.d 0x10(%a6),%fp0 # load dbl src + fmov.x %fp0,FP_SRC(%a6) + lea FP_SRC(%a6),%a0 + bsr.l tag # fetch operand type + mov.b %d0,STAG(%a6) + mov.l %d0,%d1 + + andi.l &0x00ff00ff,USER_FPSR(%a6) + + clr.l %d0 + mov.b FPCR_MODE(%a6),%d0 # pass rnd mode,prec + + lea FP_SRC(%a6),%a0 # pass ptr to src + lea FP_DST(%a6),%a1 # pass ptr to dst + + tst.b %d1 + bne.b _L22_2d + bsr.l smod_snorm # operand is a NORM + bra.b _L22_6d +_L22_2d: + cmpi.b %d1,&ZERO # is operand a ZERO? + bne.b _L22_3d # no + bsr.l smod_szero # yes + bra.b _L22_6d +_L22_3d: + cmpi.b %d1,&INF # is operand an INF? + bne.b _L22_4d # no + bsr.l smod_sinf # yes + bra.b _L22_6d +_L22_4d: + cmpi.b %d1,&QNAN # is operand a QNAN? + bne.b _L22_5d # no + bsr.l sop_sqnan # yes + bra.b _L22_6d +_L22_5d: + bsr.l smod_sdnrm # operand is a DENORM +_L22_6d: + +# +# Result is now in FP0 +# + movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 + fmovm.l USER_FPCR(%a6),%fpcr,%fpsr # restore ctrl regs + fmovm.x EXC_FP1(%a6),&0x40 # restore fp1 + unlk %a6 + rts + + global _fmodx_ +_fmodx_: + link %a6,&-LOCAL_SIZE + + movm.l &0x0303,EXC_DREGS(%a6) # save d0-d1/a0-a1 + fmovm.l %fpcr,%fpsr,USER_FPCR(%a6) # save ctrl regs + fmovm.x &0xc0,EXC_FP0(%a6) # save fp0/fp1 + + fmov.l &0x0,%fpcr # zero FPCR + +# +# copy, convert, and tag input argument +# + lea FP_DST(%a6),%a0 + mov.l 0x8+0x0(%a6),0x0(%a0) # load ext dst + mov.l 0x8+0x4(%a6),0x4(%a0) + mov.l 0x8+0x8(%a6),0x8(%a0) + bsr.l tag # fetch operand type + mov.b %d0,DTAG(%a6) + + lea FP_SRC(%a6),%a0 + mov.l 0x14+0x0(%a6),0x0(%a0) # load ext src + mov.l 0x14+0x4(%a6),0x4(%a0) + mov.l 0x14+0x8(%a6),0x8(%a0) + bsr.l tag # fetch operand type + mov.b %d0,STAG(%a6) + mov.l %d0,%d1 + + andi.l &0x00ff00ff,USER_FPSR(%a6) + + clr.l %d0 + mov.b FPCR_MODE(%a6),%d0 # pass rnd mode,prec + + lea FP_SRC(%a6),%a0 # pass ptr to src + lea FP_DST(%a6),%a1 # pass ptr to dst + + tst.b %d1 + bne.b _L22_2x + bsr.l smod_snorm # operand is a NORM + bra.b _L22_6x +_L22_2x: + cmpi.b %d1,&ZERO # is operand a ZERO? + bne.b _L22_3x # no + bsr.l smod_szero # yes + bra.b _L22_6x +_L22_3x: + cmpi.b %d1,&INF # is operand an INF? + bne.b _L22_4x # no + bsr.l smod_sinf # yes + bra.b _L22_6x +_L22_4x: + cmpi.b %d1,&QNAN # is operand a QNAN? + bne.b _L22_5x # no + bsr.l sop_sqnan # yes + bra.b _L22_6x +_L22_5x: + bsr.l smod_sdnrm # operand is a DENORM +_L22_6x: + +# +# Result is now in FP0 +# + movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 + fmovm.l USER_FPCR(%a6),%fpcr,%fpsr # restore ctrl regs + fmovm.x EXC_FP1(%a6),&0x40 # restore fp1 + unlk %a6 + rts + + +######################################################################### +# DYADIC TEMPLATE # +######################################################################### + global _fscales_ +_fscales_: + link %a6,&-LOCAL_SIZE + + movm.l &0x0303,EXC_DREGS(%a6) # save d0-d1/a0-a1 + fmovm.l %fpcr,%fpsr,USER_FPCR(%a6) # save ctrl regs + fmovm.x &0xc0,EXC_FP0(%a6) # save fp0/fp1 + + fmov.l &0x0,%fpcr # zero FPCR + +# +# copy, convert, and tag input argument +# + fmov.s 0x8(%a6),%fp0 # load sgl dst + fmov.x %fp0,FP_DST(%a6) + lea FP_DST(%a6),%a0 + bsr.l tag # fetch operand type + mov.b %d0,DTAG(%a6) + + fmov.s 0xc(%a6),%fp0 # load sgl src + fmov.x %fp0,FP_SRC(%a6) + lea FP_SRC(%a6),%a0 + bsr.l tag # fetch operand type + mov.b %d0,STAG(%a6) + mov.l %d0,%d1 + + andi.l &0x00ff00ff,USER_FPSR(%a6) + + clr.l %d0 + mov.b FPCR_MODE(%a6),%d0 # pass rnd mode,prec + + lea FP_SRC(%a6),%a0 # pass ptr to src + lea FP_DST(%a6),%a1 # pass ptr to dst + + tst.b %d1 + bne.b _L23_2s + bsr.l sscale_snorm # operand is a NORM + bra.b _L23_6s +_L23_2s: + cmpi.b %d1,&ZERO # is operand a ZERO? + bne.b _L23_3s # no + bsr.l sscale_szero # yes + bra.b _L23_6s +_L23_3s: + cmpi.b %d1,&INF # is operand an INF? + bne.b _L23_4s # no + bsr.l sscale_sinf # yes + bra.b _L23_6s +_L23_4s: + cmpi.b %d1,&QNAN # is operand a QNAN? + bne.b _L23_5s # no + bsr.l sop_sqnan # yes + bra.b _L23_6s +_L23_5s: + bsr.l sscale_sdnrm # operand is a DENORM +_L23_6s: + +# +# Result is now in FP0 +# + movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 + fmovm.l USER_FPCR(%a6),%fpcr,%fpsr # restore ctrl regs + fmovm.x EXC_FP1(%a6),&0x40 # restore fp1 + unlk %a6 + rts + + global _fscaled_ +_fscaled_: + link %a6,&-LOCAL_SIZE + + movm.l &0x0303,EXC_DREGS(%a6) # save d0-d1/a0-a1 + fmovm.l %fpcr,%fpsr,USER_FPCR(%a6) # save ctrl regs + fmovm.x &0xc0,EXC_FP0(%a6) # save fp0/fp1 + + fmov.l &0x0,%fpcr # zero FPCR + +# +# copy, convert, and tag input argument +# + fmov.d 0x8(%a6),%fp0 # load dbl dst + fmov.x %fp0,FP_DST(%a6) + lea FP_DST(%a6),%a0 + bsr.l tag # fetch operand type + mov.b %d0,DTAG(%a6) + + fmov.d 0x10(%a6),%fp0 # load dbl src + fmov.x %fp0,FP_SRC(%a6) + lea FP_SRC(%a6),%a0 + bsr.l tag # fetch operand type + mov.b %d0,STAG(%a6) + mov.l %d0,%d1 + + andi.l &0x00ff00ff,USER_FPSR(%a6) + + clr.l %d0 + mov.b FPCR_MODE(%a6),%d0 # pass rnd mode,prec + + lea FP_SRC(%a6),%a0 # pass ptr to src + lea FP_DST(%a6),%a1 # pass ptr to dst + + tst.b %d1 + bne.b _L23_2d + bsr.l sscale_snorm # operand is a NORM + bra.b _L23_6d +_L23_2d: + cmpi.b %d1,&ZERO # is operand a ZERO? + bne.b _L23_3d # no + bsr.l sscale_szero # yes + bra.b _L23_6d +_L23_3d: + cmpi.b %d1,&INF # is operand an INF? + bne.b _L23_4d # no + bsr.l sscale_sinf # yes + bra.b _L23_6d +_L23_4d: + cmpi.b %d1,&QNAN # is operand a QNAN? + bne.b _L23_5d # no + bsr.l sop_sqnan # yes + bra.b _L23_6d +_L23_5d: + bsr.l sscale_sdnrm # operand is a DENORM +_L23_6d: + +# +# Result is now in FP0 +# + movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 + fmovm.l USER_FPCR(%a6),%fpcr,%fpsr # restore ctrl regs + fmovm.x EXC_FP1(%a6),&0x40 # restore fp1 + unlk %a6 + rts + + global _fscalex_ +_fscalex_: + link %a6,&-LOCAL_SIZE + + movm.l &0x0303,EXC_DREGS(%a6) # save d0-d1/a0-a1 + fmovm.l %fpcr,%fpsr,USER_FPCR(%a6) # save ctrl regs + fmovm.x &0xc0,EXC_FP0(%a6) # save fp0/fp1 + + fmov.l &0x0,%fpcr # zero FPCR + +# +# copy, convert, and tag input argument +# + lea FP_DST(%a6),%a0 + mov.l 0x8+0x0(%a6),0x0(%a0) # load ext dst + mov.l 0x8+0x4(%a6),0x4(%a0) + mov.l 0x8+0x8(%a6),0x8(%a0) + bsr.l tag # fetch operand type + mov.b %d0,DTAG(%a6) + + lea FP_SRC(%a6),%a0 + mov.l 0x14+0x0(%a6),0x0(%a0) # load ext src + mov.l 0x14+0x4(%a6),0x4(%a0) + mov.l 0x14+0x8(%a6),0x8(%a0) + bsr.l tag # fetch operand type + mov.b %d0,STAG(%a6) + mov.l %d0,%d1 + + andi.l &0x00ff00ff,USER_FPSR(%a6) + + clr.l %d0 + mov.b FPCR_MODE(%a6),%d0 # pass rnd mode,prec + + lea FP_SRC(%a6),%a0 # pass ptr to src + lea FP_DST(%a6),%a1 # pass ptr to dst + + tst.b %d1 + bne.b _L23_2x + bsr.l sscale_snorm # operand is a NORM + bra.b _L23_6x +_L23_2x: + cmpi.b %d1,&ZERO # is operand a ZERO? + bne.b _L23_3x # no + bsr.l sscale_szero # yes + bra.b _L23_6x +_L23_3x: + cmpi.b %d1,&INF # is operand an INF? + bne.b _L23_4x # no + bsr.l sscale_sinf # yes + bra.b _L23_6x +_L23_4x: + cmpi.b %d1,&QNAN # is operand a QNAN? + bne.b _L23_5x # no + bsr.l sop_sqnan # yes + bra.b _L23_6x +_L23_5x: + bsr.l sscale_sdnrm # operand is a DENORM +_L23_6x: + +# +# Result is now in FP0 +# + movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 + fmovm.l USER_FPCR(%a6),%fpcr,%fpsr # restore ctrl regs + fmovm.x EXC_FP1(%a6),&0x40 # restore fp1 + unlk %a6 + rts + + +######################################################################### +# ssin(): computes the sine of a normalized input # +# ssind(): computes the sine of a denormalized input # +# scos(): computes the cosine of a normalized input # +# scosd(): computes the cosine of a denormalized input # +# ssincos(): computes the sine and cosine of a normalized input # +# ssincosd(): computes the sine and cosine of a denormalized input # +# # +# INPUT *************************************************************** # +# a0 = pointer to extended precision input # +# d0 = round precision,mode # +# # +# OUTPUT ************************************************************** # +# fp0 = sin(X) or cos(X) # +# # +# For ssincos(X): # +# fp0 = sin(X) # +# fp1 = cos(X) # +# # +# ACCURACY and MONOTONICITY ******************************************* # +# The returned result is within 1 ulp in 64 significant bit, i.e. # +# within 0.5001 ulp to 53 bits if the result is subsequently # +# rounded to double precision. The result is provably monotonic # +# in double precision. # +# # +# ALGORITHM *********************************************************** # +# # +# SIN and COS: # +# 1. If SIN is invoked, set AdjN := 0; otherwise, set AdjN := 1. # +# # +# 2. If |X| >= 15Pi or |X| < 2**(-40), go to 7. # +# # +# 3. Decompose X as X = N(Pi/2) + r where |r| <= Pi/4. Let # +# k = N mod 4, so in particular, k = 0,1,2,or 3. # +# Overwrite k by k := k + AdjN. # +# # +# 4. If k is even, go to 6. # +# # +# 5. (k is odd) Set j := (k-1)/2, sgn := (-1)**j. # +# Return sgn*cos(r) where cos(r) is approximated by an # +# even polynomial in r, 1 + r*r*(B1+s*(B2+ ... + s*B8)), # +# s = r*r. # +# Exit. # +# # +# 6. (k is even) Set j := k/2, sgn := (-1)**j. Return sgn*sin(r) # +# where sin(r) is approximated by an odd polynomial in r # +# r + r*s*(A1+s*(A2+ ... + s*A7)), s = r*r. # +# Exit. # +# # +# 7. If |X| > 1, go to 9. # +# # +# 8. (|X|<2**(-40)) If SIN is invoked, return X; # +# otherwise return 1. # +# # +# 9. Overwrite X by X := X rem 2Pi. Now that |X| <= Pi, # +# go back to 3. # +# # +# SINCOS: # +# 1. If |X| >= 15Pi or |X| < 2**(-40), go to 6. # +# # +# 2. Decompose X as X = N(Pi/2) + r where |r| <= Pi/4. Let # +# k = N mod 4, so in particular, k = 0,1,2,or 3. # +# # +# 3. If k is even, go to 5. # +# # +# 4. (k is odd) Set j1 := (k-1)/2, j2 := j1 (EOR) (k mod 2), ie. # +# j1 exclusive or with the l.s.b. of k. # +# sgn1 := (-1)**j1, sgn2 := (-1)**j2. # +# SIN(X) = sgn1 * cos(r) and COS(X) = sgn2*sin(r) where # +# sin(r) and cos(r) are computed as odd and even # +# polynomials in r, respectively. Exit # +# # +# 5. (k is even) Set j1 := k/2, sgn1 := (-1)**j1. # +# SIN(X) = sgn1 * sin(r) and COS(X) = sgn1*cos(r) where # +# sin(r) and cos(r) are computed as odd and even # +# polynomials in r, respectively. Exit # +# # +# 6. If |X| > 1, go to 8. # +# # +# 7. (|X|<2**(-40)) SIN(X) = X and COS(X) = 1. Exit. # +# # +# 8. Overwrite X by X := X rem 2Pi. Now that |X| <= Pi, # +# go back to 2. # +# # +######################################################################### + +SINA7: long 0xBD6AAA77,0xCCC994F5 +SINA6: long 0x3DE61209,0x7AAE8DA1 +SINA5: long 0xBE5AE645,0x2A118AE4 +SINA4: long 0x3EC71DE3,0xA5341531 +SINA3: long 0xBF2A01A0,0x1A018B59,0x00000000,0x00000000 +SINA2: long 0x3FF80000,0x88888888,0x888859AF,0x00000000 +SINA1: long 0xBFFC0000,0xAAAAAAAA,0xAAAAAA99,0x00000000 + +COSB8: long 0x3D2AC4D0,0xD6011EE3 +COSB7: long 0xBDA9396F,0x9F45AC19 +COSB6: long 0x3E21EED9,0x0612C972 +COSB5: long 0xBE927E4F,0xB79D9FCF +COSB4: long 0x3EFA01A0,0x1A01D423,0x00000000,0x00000000 +COSB3: long 0xBFF50000,0xB60B60B6,0x0B61D438,0x00000000 +COSB2: long 0x3FFA0000,0xAAAAAAAA,0xAAAAAB5E +COSB1: long 0xBF000000 + + set INARG,FP_SCR0 + + set X,FP_SCR0 +# set XDCARE,X+2 + set XFRAC,X+4 + + set RPRIME,FP_SCR0 + set SPRIME,FP_SCR1 + + set POSNEG1,L_SCR1 + set TWOTO63,L_SCR1 + + set ENDFLAG,L_SCR2 + set INT,L_SCR2 + + set ADJN,L_SCR3 + +############################################ + global ssin +ssin: + mov.l &0,ADJN(%a6) # yes; SET ADJN TO 0 + bra.b SINBGN + +############################################ + global scos +scos: + mov.l &1,ADJN(%a6) # yes; SET ADJN TO 1 + +############################################ +SINBGN: +#--SAVE FPCR, FP1. CHECK IF |X| IS TOO SMALL OR LARGE + + fmov.x (%a0),%fp0 # LOAD INPUT + fmov.x %fp0,X(%a6) # save input at X + +# "COMPACTIFY" X + mov.l (%a0),%d1 # put exp in hi word + mov.w 4(%a0),%d1 # fetch hi(man) + and.l &0x7FFFFFFF,%d1 # strip sign + + cmpi.l %d1,&0x3FD78000 # is |X| >= 2**(-40)? + bge.b SOK1 # no + bra.w SINSM # yes; input is very small + +SOK1: + cmp.l %d1,&0x4004BC7E # is |X| < 15 PI? + blt.b SINMAIN # no + bra.w SREDUCEX # yes; input is very large + +#--THIS IS THE USUAL CASE, |X| <= 15 PI. +#--THE ARGUMENT REDUCTION IS DONE BY TABLE LOOK UP. +SINMAIN: + fmov.x %fp0,%fp1 + fmul.d TWOBYPI(%pc),%fp1 # X*2/PI + + lea PITBL+0x200(%pc),%a1 # TABLE OF N*PI/2, N = -32,...,32 + + fmov.l %fp1,INT(%a6) # CONVERT TO INTEGER + + mov.l INT(%a6),%d1 # make a copy of N + asl.l &4,%d1 # N *= 16 + add.l %d1,%a1 # tbl_addr = a1 + (N*16) + +# A1 IS THE ADDRESS OF N*PIBY2 +# ...WHICH IS IN TWO PIECES Y1 & Y2 + fsub.x (%a1)+,%fp0 # X-Y1 + fsub.s (%a1),%fp0 # fp0 = R = (X-Y1)-Y2 + +SINCONT: +#--continuation from REDUCEX + +#--GET N+ADJN AND SEE IF SIN(R) OR COS(R) IS NEEDED + mov.l INT(%a6),%d1 + add.l ADJN(%a6),%d1 # SEE IF D0 IS ODD OR EVEN + ror.l &1,%d1 # D0 WAS ODD IFF D0 IS NEGATIVE + cmp.l %d1,&0 + blt.w COSPOLY + +#--LET J BE THE LEAST SIG. BIT OF D0, LET SGN := (-1)**J. +#--THEN WE RETURN SGN*SIN(R). SGN*SIN(R) IS COMPUTED BY +#--R' + R'*S*(A1 + S(A2 + S(A3 + S(A4 + ... + SA7)))), WHERE +#--R' = SGN*R, S=R*R. THIS CAN BE REWRITTEN AS +#--R' + R'*S*( [A1+T(A3+T(A5+TA7))] + [S(A2+T(A4+TA6))]) +#--WHERE T=S*S. +#--NOTE THAT A3 THROUGH A7 ARE STORED IN DOUBLE PRECISION +#--WHILE A1 AND A2 ARE IN DOUBLE-EXTENDED FORMAT. +SINPOLY: + fmovm.x &0x0c,-(%sp) # save fp2/fp3 + + fmov.x %fp0,X(%a6) # X IS R + fmul.x %fp0,%fp0 # FP0 IS S + + fmov.d SINA7(%pc),%fp3 + fmov.d SINA6(%pc),%fp2 + + fmov.x %fp0,%fp1 + fmul.x %fp1,%fp1 # FP1 IS T + + ror.l &1,%d1 + and.l &0x80000000,%d1 +# ...LEAST SIG. BIT OF D0 IN SIGN POSITION + eor.l %d1,X(%a6) # X IS NOW R'= SGN*R + + fmul.x %fp1,%fp3 # TA7 + fmul.x %fp1,%fp2 # TA6 + + fadd.d SINA5(%pc),%fp3 # A5+TA7 + fadd.d SINA4(%pc),%fp2 # A4+TA6 + + fmul.x %fp1,%fp3 # T(A5+TA7) + fmul.x %fp1,%fp2 # T(A4+TA6) + + fadd.d SINA3(%pc),%fp3 # A3+T(A5+TA7) + fadd.x SINA2(%pc),%fp2 # A2+T(A4+TA6) + + fmul.x %fp3,%fp1 # T(A3+T(A5+TA7)) + + fmul.x %fp0,%fp2 # S(A2+T(A4+TA6)) + fadd.x SINA1(%pc),%fp1 # A1+T(A3+T(A5+TA7)) + fmul.x X(%a6),%fp0 # R'*S + + fadd.x %fp2,%fp1 # [A1+T(A3+T(A5+TA7))]+[S(A2+T(A4+TA6))] + + fmul.x %fp1,%fp0 # SIN(R')-R' + + fmovm.x (%sp)+,&0x30 # restore fp2/fp3 + + fmov.l %d0,%fpcr # restore users round mode,prec + fadd.x X(%a6),%fp0 # last inst - possible exception set + bra t_inx2 + +#--LET J BE THE LEAST SIG. BIT OF D0, LET SGN := (-1)**J. +#--THEN WE RETURN SGN*COS(R). SGN*COS(R) IS COMPUTED BY +#--SGN + S'*(B1 + S(B2 + S(B3 + S(B4 + ... + SB8)))), WHERE +#--S=R*R AND S'=SGN*S. THIS CAN BE REWRITTEN AS +#--SGN + S'*([B1+T(B3+T(B5+TB7))] + [S(B2+T(B4+T(B6+TB8)))]) +#--WHERE T=S*S. +#--NOTE THAT B4 THROUGH B8 ARE STORED IN DOUBLE PRECISION +#--WHILE B2 AND B3 ARE IN DOUBLE-EXTENDED FORMAT, B1 IS -1/2 +#--AND IS THEREFORE STORED AS SINGLE PRECISION. +COSPOLY: + fmovm.x &0x0c,-(%sp) # save fp2/fp3 + + fmul.x %fp0,%fp0 # FP0 IS S + + fmov.d COSB8(%pc),%fp2 + fmov.d COSB7(%pc),%fp3 + + fmov.x %fp0,%fp1 + fmul.x %fp1,%fp1 # FP1 IS T + + fmov.x %fp0,X(%a6) # X IS S + ror.l &1,%d1 + and.l &0x80000000,%d1 +# ...LEAST SIG. BIT OF D0 IN SIGN POSITION + + fmul.x %fp1,%fp2 # TB8 + + eor.l %d1,X(%a6) # X IS NOW S'= SGN*S + and.l &0x80000000,%d1 + + fmul.x %fp1,%fp3 # TB7 + + or.l &0x3F800000,%d1 # D0 IS SGN IN SINGLE + mov.l %d1,POSNEG1(%a6) + + fadd.d COSB6(%pc),%fp2 # B6+TB8 + fadd.d COSB5(%pc),%fp3 # B5+TB7 + + fmul.x %fp1,%fp2 # T(B6+TB8) + fmul.x %fp1,%fp3 # T(B5+TB7) + + fadd.d COSB4(%pc),%fp2 # B4+T(B6+TB8) + fadd.x COSB3(%pc),%fp3 # B3+T(B5+TB7) + + fmul.x %fp1,%fp2 # T(B4+T(B6+TB8)) + fmul.x %fp3,%fp1 # T(B3+T(B5+TB7)) + + fadd.x COSB2(%pc),%fp2 # B2+T(B4+T(B6+TB8)) + fadd.s COSB1(%pc),%fp1 # B1+T(B3+T(B5+TB7)) + + fmul.x %fp2,%fp0 # S(B2+T(B4+T(B6+TB8))) + + fadd.x %fp1,%fp0 + + fmul.x X(%a6),%fp0 + + fmovm.x (%sp)+,&0x30 # restore fp2/fp3 + + fmov.l %d0,%fpcr # restore users round mode,prec + fadd.s POSNEG1(%a6),%fp0 # last inst - possible exception set + bra t_inx2 + +############################################## + +# SINe: Big OR Small? +#--IF |X| > 15PI, WE USE THE GENERAL ARGUMENT REDUCTION. +#--IF |X| < 2**(-40), RETURN X OR 1. +SINBORS: + cmp.l %d1,&0x3FFF8000 + bgt.l SREDUCEX + +SINSM: + mov.l ADJN(%a6),%d1 + cmp.l %d1,&0 + bgt.b COSTINY + +# here, the operation may underflow iff the precision is sgl or dbl. +# extended denorms are handled through another entry point. +SINTINY: +# mov.w &0x0000,XDCARE(%a6) # JUST IN CASE + + fmov.l %d0,%fpcr # restore users round mode,prec + mov.b &FMOV_OP,%d1 # last inst is MOVE + fmov.x X(%a6),%fp0 # last inst - possible exception set + bra t_catch + +COSTINY: + fmov.s &0x3F800000,%fp0 # fp0 = 1.0 + fmov.l %d0,%fpcr # restore users round mode,prec + fadd.s &0x80800000,%fp0 # last inst - possible exception set + bra t_pinx2 + +################################################ + global ssind +#--SIN(X) = X FOR DENORMALIZED X +ssind: + bra t_extdnrm + +############################################ + global scosd +#--COS(X) = 1 FOR DENORMALIZED X +scosd: + fmov.s &0x3F800000,%fp0 # fp0 = 1.0 + bra t_pinx2 + +################################################## + + global ssincos +ssincos: +#--SET ADJN TO 4 + mov.l &4,ADJN(%a6) + + fmov.x (%a0),%fp0 # LOAD INPUT + fmov.x %fp0,X(%a6) + + mov.l (%a0),%d1 + mov.w 4(%a0),%d1 + and.l &0x7FFFFFFF,%d1 # COMPACTIFY X + + cmp.l %d1,&0x3FD78000 # |X| >= 2**(-40)? + bge.b SCOK1 + bra.w SCSM + +SCOK1: + cmp.l %d1,&0x4004BC7E # |X| < 15 PI? + blt.b SCMAIN + bra.w SREDUCEX + + +#--THIS IS THE USUAL CASE, |X| <= 15 PI. +#--THE ARGUMENT REDUCTION IS DONE BY TABLE LOOK UP. +SCMAIN: + fmov.x %fp0,%fp1 + + fmul.d TWOBYPI(%pc),%fp1 # X*2/PI + + lea PITBL+0x200(%pc),%a1 # TABLE OF N*PI/2, N = -32,...,32 + + fmov.l %fp1,INT(%a6) # CONVERT TO INTEGER + + mov.l INT(%a6),%d1 + asl.l &4,%d1 + add.l %d1,%a1 # ADDRESS OF N*PIBY2, IN Y1, Y2 + + fsub.x (%a1)+,%fp0 # X-Y1 + fsub.s (%a1),%fp0 # FP0 IS R = (X-Y1)-Y2 + +SCCONT: +#--continuation point from REDUCEX + + mov.l INT(%a6),%d1 + ror.l &1,%d1 + cmp.l %d1,&0 # D0 < 0 IFF N IS ODD + bge.w NEVEN + +SNODD: +#--REGISTERS SAVED SO FAR: D0, A0, FP2. + fmovm.x &0x04,-(%sp) # save fp2 + + fmov.x %fp0,RPRIME(%a6) + fmul.x %fp0,%fp0 # FP0 IS S = R*R + fmov.d SINA7(%pc),%fp1 # A7 + fmov.d COSB8(%pc),%fp2 # B8 + fmul.x %fp0,%fp1 # SA7 + fmul.x %fp0,%fp2 # SB8 + + mov.l %d2,-(%sp) + mov.l %d1,%d2 + ror.l &1,%d2 + and.l &0x80000000,%d2 + eor.l %d1,%d2 + and.l &0x80000000,%d2 + + fadd.d SINA6(%pc),%fp1 # A6+SA7 + fadd.d COSB7(%pc),%fp2 # B7+SB8 + + fmul.x %fp0,%fp1 # S(A6+SA7) + eor.l %d2,RPRIME(%a6) + mov.l (%sp)+,%d2 + fmul.x %fp0,%fp2 # S(B7+SB8) + ror.l &1,%d1 + and.l &0x80000000,%d1 + mov.l &0x3F800000,POSNEG1(%a6) + eor.l %d1,POSNEG1(%a6) + + fadd.d SINA5(%pc),%fp1 # A5+S(A6+SA7) + fadd.d COSB6(%pc),%fp2 # B6+S(B7+SB8) + + fmul.x %fp0,%fp1 # S(A5+S(A6+SA7)) + fmul.x %fp0,%fp2 # S(B6+S(B7+SB8)) + fmov.x %fp0,SPRIME(%a6) + + fadd.d SINA4(%pc),%fp1 # A4+S(A5+S(A6+SA7)) + eor.l %d1,SPRIME(%a6) + fadd.d COSB5(%pc),%fp2 # B5+S(B6+S(B7+SB8)) + + fmul.x %fp0,%fp1 # S(A4+...) + fmul.x %fp0,%fp2 # S(B5+...) + + fadd.d SINA3(%pc),%fp1 # A3+S(A4+...) + fadd.d COSB4(%pc),%fp2 # B4+S(B5+...) + + fmul.x %fp0,%fp1 # S(A3+...) + fmul.x %fp0,%fp2 # S(B4+...) + + fadd.x SINA2(%pc),%fp1 # A2+S(A3+...) + fadd.x COSB3(%pc),%fp2 # B3+S(B4+...) + + fmul.x %fp0,%fp1 # S(A2+...) + fmul.x %fp0,%fp2 # S(B3+...) + + fadd.x SINA1(%pc),%fp1 # A1+S(A2+...) + fadd.x COSB2(%pc),%fp2 # B2+S(B3+...) + + fmul.x %fp0,%fp1 # S(A1+...) + fmul.x %fp2,%fp0 # S(B2+...) + + fmul.x RPRIME(%a6),%fp1 # R'S(A1+...) + fadd.s COSB1(%pc),%fp0 # B1+S(B2...) + fmul.x SPRIME(%a6),%fp0 # S'(B1+S(B2+...)) + + fmovm.x (%sp)+,&0x20 # restore fp2 + + fmov.l %d0,%fpcr + fadd.x RPRIME(%a6),%fp1 # COS(X) + bsr sto_cos # store cosine result + fadd.s POSNEG1(%a6),%fp0 # SIN(X) + bra t_inx2 + +NEVEN: +#--REGISTERS SAVED SO FAR: FP2. + fmovm.x &0x04,-(%sp) # save fp2 + + fmov.x %fp0,RPRIME(%a6) + fmul.x %fp0,%fp0 # FP0 IS S = R*R + + fmov.d COSB8(%pc),%fp1 # B8 + fmov.d SINA7(%pc),%fp2 # A7 + + fmul.x %fp0,%fp1 # SB8 + fmov.x %fp0,SPRIME(%a6) + fmul.x %fp0,%fp2 # SA7 + + ror.l &1,%d1 + and.l &0x80000000,%d1 + + fadd.d COSB7(%pc),%fp1 # B7+SB8 + fadd.d SINA6(%pc),%fp2 # A6+SA7 + + eor.l %d1,RPRIME(%a6) + eor.l %d1,SPRIME(%a6) + + fmul.x %fp0,%fp1 # S(B7+SB8) + + or.l &0x3F800000,%d1 + mov.l %d1,POSNEG1(%a6) + + fmul.x %fp0,%fp2 # S(A6+SA7) + + fadd.d COSB6(%pc),%fp1 # B6+S(B7+SB8) + fadd.d SINA5(%pc),%fp2 # A5+S(A6+SA7) + + fmul.x %fp0,%fp1 # S(B6+S(B7+SB8)) + fmul.x %fp0,%fp2 # S(A5+S(A6+SA7)) + + fadd.d COSB5(%pc),%fp1 # B5+S(B6+S(B7+SB8)) + fadd.d SINA4(%pc),%fp2 # A4+S(A5+S(A6+SA7)) + + fmul.x %fp0,%fp1 # S(B5+...) + fmul.x %fp0,%fp2 # S(A4+...) + + fadd.d COSB4(%pc),%fp1 # B4+S(B5+...) + fadd.d SINA3(%pc),%fp2 # A3+S(A4+...) + + fmul.x %fp0,%fp1 # S(B4+...) + fmul.x %fp0,%fp2 # S(A3+...) + + fadd.x COSB3(%pc),%fp1 # B3+S(B4+...) + fadd.x SINA2(%pc),%fp2 # A2+S(A3+...) + + fmul.x %fp0,%fp1 # S(B3+...) + fmul.x %fp0,%fp2 # S(A2+...) + + fadd.x COSB2(%pc),%fp1 # B2+S(B3+...) + fadd.x SINA1(%pc),%fp2 # A1+S(A2+...) + + fmul.x %fp0,%fp1 # S(B2+...) + fmul.x %fp2,%fp0 # s(a1+...) + + + fadd.s COSB1(%pc),%fp1 # B1+S(B2...) + fmul.x RPRIME(%a6),%fp0 # R'S(A1+...) + fmul.x SPRIME(%a6),%fp1 # S'(B1+S(B2+...)) + + fmovm.x (%sp)+,&0x20 # restore fp2 + + fmov.l %d0,%fpcr + fadd.s POSNEG1(%a6),%fp1 # COS(X) + bsr sto_cos # store cosine result + fadd.x RPRIME(%a6),%fp0 # SIN(X) + bra t_inx2 + +################################################ + +SCBORS: + cmp.l %d1,&0x3FFF8000 + bgt.w SREDUCEX + +################################################ + +SCSM: +# mov.w &0x0000,XDCARE(%a6) + fmov.s &0x3F800000,%fp1 + + fmov.l %d0,%fpcr + fsub.s &0x00800000,%fp1 + bsr sto_cos # store cosine result + fmov.l %fpcr,%d0 # d0 must have fpcr,too + mov.b &FMOV_OP,%d1 # last inst is MOVE + fmov.x X(%a6),%fp0 + bra t_catch + +############################################## + + global ssincosd +#--SIN AND COS OF X FOR DENORMALIZED X +ssincosd: + mov.l %d0,-(%sp) # save d0 + fmov.s &0x3F800000,%fp1 + bsr sto_cos # store cosine result + mov.l (%sp)+,%d0 # restore d0 + bra t_extdnrm + +############################################ + +#--WHEN REDUCEX IS USED, THE CODE WILL INEVITABLY BE SLOW. +#--THIS REDUCTION METHOD, HOWEVER, IS MUCH FASTER THAN USING +#--THE REMAINDER INSTRUCTION WHICH IS NOW IN SOFTWARE. +SREDUCEX: + fmovm.x &0x3c,-(%sp) # save {fp2-fp5} + mov.l %d2,-(%sp) # save d2 + fmov.s &0x00000000,%fp1 # fp1 = 0 + +#--If compact form of abs(arg) in d0=$7ffeffff, argument is so large that +#--there is a danger of unwanted overflow in first LOOP iteration. In this +#--case, reduce argument by one remainder step to make subsequent reduction +#--safe. + cmp.l %d1,&0x7ffeffff # is arg dangerously large? + bne.b SLOOP # no + +# yes; create 2**16383*PI/2 + mov.w &0x7ffe,FP_SCR0_EX(%a6) + mov.l &0xc90fdaa2,FP_SCR0_HI(%a6) + clr.l FP_SCR0_LO(%a6) + +# create low half of 2**16383*PI/2 at FP_SCR1 + mov.w &0x7fdc,FP_SCR1_EX(%a6) + mov.l &0x85a308d3,FP_SCR1_HI(%a6) + clr.l FP_SCR1_LO(%a6) + + ftest.x %fp0 # test sign of argument + fblt.w sred_neg + + or.b &0x80,FP_SCR0_EX(%a6) # positive arg + or.b &0x80,FP_SCR1_EX(%a6) +sred_neg: + fadd.x FP_SCR0(%a6),%fp0 # high part of reduction is exact + fmov.x %fp0,%fp1 # save high result in fp1 + fadd.x FP_SCR1(%a6),%fp0 # low part of reduction + fsub.x %fp0,%fp1 # determine low component of result + fadd.x FP_SCR1(%a6),%fp1 # fp0/fp1 are reduced argument. + +#--ON ENTRY, FP0 IS X, ON RETURN, FP0 IS X REM PI/2, |X| <= PI/4. +#--integer quotient will be stored in N +#--Intermeditate remainder is 66-bit long; (R,r) in (FP0,FP1) +SLOOP: + fmov.x %fp0,INARG(%a6) # +-2**K * F, 1 <= F < 2 + mov.w INARG(%a6),%d1 + mov.l %d1,%a1 # save a copy of D0 + and.l &0x00007FFF,%d1 + sub.l &0x00003FFF,%d1 # d0 = K + cmp.l %d1,&28 + ble.b SLASTLOOP +SCONTLOOP: + sub.l &27,%d1 # d0 = L := K-27 + mov.b &0,ENDFLAG(%a6) + bra.b SWORK +SLASTLOOP: + clr.l %d1 # d0 = L := 0 + mov.b &1,ENDFLAG(%a6) + +SWORK: +#--FIND THE REMAINDER OF (R,r) W.R.T. 2**L * (PI/2). L IS SO CHOSEN +#--THAT INT( X * (2/PI) / 2**(L) ) < 2**29. + +#--CREATE 2**(-L) * (2/PI), SIGN(INARG)*2**(63), +#--2**L * (PIby2_1), 2**L * (PIby2_2) + + mov.l &0x00003FFE,%d2 # BIASED EXP OF 2/PI + sub.l %d1,%d2 # BIASED EXP OF 2**(-L)*(2/PI) + + mov.l &0xA2F9836E,FP_SCR0_HI(%a6) + mov.l &0x4E44152A,FP_SCR0_LO(%a6) + mov.w %d2,FP_SCR0_EX(%a6) # FP_SCR0 = 2**(-L)*(2/PI) + + fmov.x %fp0,%fp2 + fmul.x FP_SCR0(%a6),%fp2 # fp2 = X * 2**(-L)*(2/PI) + +#--WE MUST NOW FIND INT(FP2). SINCE WE NEED THIS VALUE IN +#--FLOATING POINT FORMAT, THE TWO FMOVE'S FMOVE.L FP <--> N +#--WILL BE TOO INEFFICIENT. THE WAY AROUND IT IS THAT +#--(SIGN(INARG)*2**63 + FP2) - SIGN(INARG)*2**63 WILL GIVE +#--US THE DESIRED VALUE IN FLOATING POINT. + mov.l %a1,%d2 + swap %d2 + and.l &0x80000000,%d2 + or.l &0x5F000000,%d2 # d2 = SIGN(INARG)*2**63 IN SGL + mov.l %d2,TWOTO63(%a6) + fadd.s TWOTO63(%a6),%fp2 # THE FRACTIONAL PART OF FP1 IS ROUNDED + fsub.s TWOTO63(%a6),%fp2 # fp2 = N +# fint.x %fp2 + +#--CREATING 2**(L)*Piby2_1 and 2**(L)*Piby2_2 + mov.l %d1,%d2 # d2 = L + + add.l &0x00003FFF,%d2 # BIASED EXP OF 2**L * (PI/2) + mov.w %d2,FP_SCR0_EX(%a6) + mov.l &0xC90FDAA2,FP_SCR0_HI(%a6) + clr.l FP_SCR0_LO(%a6) # FP_SCR0 = 2**(L) * Piby2_1 + + add.l &0x00003FDD,%d1 + mov.w %d1,FP_SCR1_EX(%a6) + mov.l &0x85A308D3,FP_SCR1_HI(%a6) + clr.l FP_SCR1_LO(%a6) # FP_SCR1 = 2**(L) * Piby2_2 + + mov.b ENDFLAG(%a6),%d1 + +#--We are now ready to perform (R+r) - N*P1 - N*P2, P1 = 2**(L) * Piby2_1 and +#--P2 = 2**(L) * Piby2_2 + fmov.x %fp2,%fp4 # fp4 = N + fmul.x FP_SCR0(%a6),%fp4 # fp4 = W = N*P1 + fmov.x %fp2,%fp5 # fp5 = N + fmul.x FP_SCR1(%a6),%fp5 # fp5 = w = N*P2 + fmov.x %fp4,%fp3 # fp3 = W = N*P1 + +#--we want P+p = W+w but |p| <= half ulp of P +#--Then, we need to compute A := R-P and a := r-p + fadd.x %fp5,%fp3 # fp3 = P + fsub.x %fp3,%fp4 # fp4 = W-P + + fsub.x %fp3,%fp0 # fp0 = A := R - P + fadd.x %fp5,%fp4 # fp4 = p = (W-P)+w + + fmov.x %fp0,%fp3 # fp3 = A + fsub.x %fp4,%fp1 # fp1 = a := r - p + +#--Now we need to normalize (A,a) to "new (R,r)" where R+r = A+a but +#--|r| <= half ulp of R. + fadd.x %fp1,%fp0 # fp0 = R := A+a +#--No need to calculate r if this is the last loop + cmp.b %d1,&0 + bgt.w SRESTORE + +#--Need to calculate r + fsub.x %fp0,%fp3 # fp3 = A-R + fadd.x %fp3,%fp1 # fp1 = r := (A-R)+a + bra.w SLOOP + +SRESTORE: + fmov.l %fp2,INT(%a6) + mov.l (%sp)+,%d2 # restore d2 + fmovm.x (%sp)+,&0x3c # restore {fp2-fp5} + + mov.l ADJN(%a6),%d1 + cmp.l %d1,&4 + + blt.w SINCONT + bra.w SCCONT + +######################################################################### +# stan(): computes the tangent of a normalized input # +# stand(): computes the tangent of a denormalized input # +# # +# INPUT *************************************************************** # +# a0 = pointer to extended precision input # +# d0 = round precision,mode # +# # +# OUTPUT ************************************************************** # +# fp0 = tan(X) # +# # +# ACCURACY and MONOTONICITY ******************************************* # +# The returned result is within 3 ulp in 64 significant bit, i.e. # +# within 0.5001 ulp to 53 bits if the result is subsequently # +# rounded to double precision. The result is provably monotonic # +# in double precision. # +# # +# ALGORITHM *********************************************************** # +# # +# 1. If |X| >= 15Pi or |X| < 2**(-40), go to 6. # +# # +# 2. Decompose X as X = N(Pi/2) + r where |r| <= Pi/4. Let # +# k = N mod 2, so in particular, k = 0 or 1. # +# # +# 3. If k is odd, go to 5. # +# # +# 4. (k is even) Tan(X) = tan(r) and tan(r) is approximated by a # +# rational function U/V where # +# U = r + r*s*(P1 + s*(P2 + s*P3)), and # +# V = 1 + s*(Q1 + s*(Q2 + s*(Q3 + s*Q4))), s = r*r. # +# Exit. # +# # +# 4. (k is odd) Tan(X) = -cot(r). Since tan(r) is approximated by # +# a rational function U/V where # +# U = r + r*s*(P1 + s*(P2 + s*P3)), and # +# V = 1 + s*(Q1 + s*(Q2 + s*(Q3 + s*Q4))), s = r*r, # +# -Cot(r) = -V/U. Exit. # +# # +# 6. If |X| > 1, go to 8. # +# # +# 7. (|X|<2**(-40)) Tan(X) = X. Exit. # +# # +# 8. Overwrite X by X := X rem 2Pi. Now that |X| <= Pi, go back # +# to 2. # +# # +######################################################################### + +TANQ4: + long 0x3EA0B759,0xF50F8688 +TANP3: + long 0xBEF2BAA5,0xA8924F04 + +TANQ3: + long 0xBF346F59,0xB39BA65F,0x00000000,0x00000000 + +TANP2: + long 0x3FF60000,0xE073D3FC,0x199C4A00,0x00000000 + +TANQ2: + long 0x3FF90000,0xD23CD684,0x15D95FA1,0x00000000 + +TANP1: + long 0xBFFC0000,0x8895A6C5,0xFB423BCA,0x00000000 + +TANQ1: + long 0xBFFD0000,0xEEF57E0D,0xA84BC8CE,0x00000000 + +INVTWOPI: + long 0x3FFC0000,0xA2F9836E,0x4E44152A,0x00000000 + +TWOPI1: + long 0x40010000,0xC90FDAA2,0x00000000,0x00000000 +TWOPI2: + long 0x3FDF0000,0x85A308D4,0x00000000,0x00000000 + +#--N*PI/2, -32 <= N <= 32, IN A LEADING TERM IN EXT. AND TRAILING +#--TERM IN SGL. NOTE THAT PI IS 64-BIT LONG, THUS N*PI/2 IS AT +#--MOST 69 BITS LONG. +# global PITBL +PITBL: + long 0xC0040000,0xC90FDAA2,0x2168C235,0x21800000 + long 0xC0040000,0xC2C75BCD,0x105D7C23,0xA0D00000 + long 0xC0040000,0xBC7EDCF7,0xFF523611,0xA1E80000 + long 0xC0040000,0xB6365E22,0xEE46F000,0x21480000 + long 0xC0040000,0xAFEDDF4D,0xDD3BA9EE,0xA1200000 + long 0xC0040000,0xA9A56078,0xCC3063DD,0x21FC0000 + long 0xC0040000,0xA35CE1A3,0xBB251DCB,0x21100000 + long 0xC0040000,0x9D1462CE,0xAA19D7B9,0xA1580000 + long 0xC0040000,0x96CBE3F9,0x990E91A8,0x21E00000 + long 0xC0040000,0x90836524,0x88034B96,0x20B00000 + long 0xC0040000,0x8A3AE64F,0x76F80584,0xA1880000 + long 0xC0040000,0x83F2677A,0x65ECBF73,0x21C40000 + long 0xC0030000,0xFB53D14A,0xA9C2F2C2,0x20000000 + long 0xC0030000,0xEEC2D3A0,0x87AC669F,0x21380000 + long 0xC0030000,0xE231D5F6,0x6595DA7B,0xA1300000 + long 0xC0030000,0xD5A0D84C,0x437F4E58,0x9FC00000 + long 0xC0030000,0xC90FDAA2,0x2168C235,0x21000000 + long 0xC0030000,0xBC7EDCF7,0xFF523611,0xA1680000 + long 0xC0030000,0xAFEDDF4D,0xDD3BA9EE,0xA0A00000 + long 0xC0030000,0xA35CE1A3,0xBB251DCB,0x20900000 + long 0xC0030000,0x96CBE3F9,0x990E91A8,0x21600000 + long 0xC0030000,0x8A3AE64F,0x76F80584,0xA1080000 + long 0xC0020000,0xFB53D14A,0xA9C2F2C2,0x1F800000 + long 0xC0020000,0xE231D5F6,0x6595DA7B,0xA0B00000 + long 0xC0020000,0xC90FDAA2,0x2168C235,0x20800000 + long 0xC0020000,0xAFEDDF4D,0xDD3BA9EE,0xA0200000 + long 0xC0020000,0x96CBE3F9,0x990E91A8,0x20E00000 + long 0xC0010000,0xFB53D14A,0xA9C2F2C2,0x1F000000 + long 0xC0010000,0xC90FDAA2,0x2168C235,0x20000000 + long 0xC0010000,0x96CBE3F9,0x990E91A8,0x20600000 + long 0xC0000000,0xC90FDAA2,0x2168C235,0x1F800000 + long 0xBFFF0000,0xC90FDAA2,0x2168C235,0x1F000000 + long 0x00000000,0x00000000,0x00000000,0x00000000 + long 0x3FFF0000,0xC90FDAA2,0x2168C235,0x9F000000 + long 0x40000000,0xC90FDAA2,0x2168C235,0x9F800000 + long 0x40010000,0x96CBE3F9,0x990E91A8,0xA0600000 + long 0x40010000,0xC90FDAA2,0x2168C235,0xA0000000 + long 0x40010000,0xFB53D14A,0xA9C2F2C2,0x9F000000 + long 0x40020000,0x96CBE3F9,0x990E91A8,0xA0E00000 + long 0x40020000,0xAFEDDF4D,0xDD3BA9EE,0x20200000 + long 0x40020000,0xC90FDAA2,0x2168C235,0xA0800000 + long 0x40020000,0xE231D5F6,0x6595DA7B,0x20B00000 + long 0x40020000,0xFB53D14A,0xA9C2F2C2,0x9F800000 + long 0x40030000,0x8A3AE64F,0x76F80584,0x21080000 + long 0x40030000,0x96CBE3F9,0x990E91A8,0xA1600000 + long 0x40030000,0xA35CE1A3,0xBB251DCB,0xA0900000 + long 0x40030000,0xAFEDDF4D,0xDD3BA9EE,0x20A00000 + long 0x40030000,0xBC7EDCF7,0xFF523611,0x21680000 + long 0x40030000,0xC90FDAA2,0x2168C235,0xA1000000 + long 0x40030000,0xD5A0D84C,0x437F4E58,0x1FC00000 + long 0x40030000,0xE231D5F6,0x6595DA7B,0x21300000 + long 0x40030000,0xEEC2D3A0,0x87AC669F,0xA1380000 + long 0x40030000,0xFB53D14A,0xA9C2F2C2,0xA0000000 + long 0x40040000,0x83F2677A,0x65ECBF73,0xA1C40000 + long 0x40040000,0x8A3AE64F,0x76F80584,0x21880000 + long 0x40040000,0x90836524,0x88034B96,0xA0B00000 + long 0x40040000,0x96CBE3F9,0x990E91A8,0xA1E00000 + long 0x40040000,0x9D1462CE,0xAA19D7B9,0x21580000 + long 0x40040000,0xA35CE1A3,0xBB251DCB,0xA1100000 + long 0x40040000,0xA9A56078,0xCC3063DD,0xA1FC0000 + long 0x40040000,0xAFEDDF4D,0xDD3BA9EE,0x21200000 + long 0x40040000,0xB6365E22,0xEE46F000,0xA1480000 + long 0x40040000,0xBC7EDCF7,0xFF523611,0x21E80000 + long 0x40040000,0xC2C75BCD,0x105D7C23,0x20D00000 + long 0x40040000,0xC90FDAA2,0x2168C235,0xA1800000 + + set INARG,FP_SCR0 + + set TWOTO63,L_SCR1 + set INT,L_SCR1 + set ENDFLAG,L_SCR2 + + global stan +stan: + fmov.x (%a0),%fp0 # LOAD INPUT + + mov.l (%a0),%d1 + mov.w 4(%a0),%d1 + and.l &0x7FFFFFFF,%d1 + + cmp.l %d1,&0x3FD78000 # |X| >= 2**(-40)? + bge.b TANOK1 + bra.w TANSM +TANOK1: + cmp.l %d1,&0x4004BC7E # |X| < 15 PI? + blt.b TANMAIN + bra.w REDUCEX + +TANMAIN: +#--THIS IS THE USUAL CASE, |X| <= 15 PI. +#--THE ARGUMENT REDUCTION IS DONE BY TABLE LOOK UP. + fmov.x %fp0,%fp1 + fmul.d TWOBYPI(%pc),%fp1 # X*2/PI + + lea.l PITBL+0x200(%pc),%a1 # TABLE OF N*PI/2, N = -32,...,32 + + fmov.l %fp1,%d1 # CONVERT TO INTEGER + + asl.l &4,%d1 + add.l %d1,%a1 # ADDRESS N*PIBY2 IN Y1, Y2 + + fsub.x (%a1)+,%fp0 # X-Y1 + + fsub.s (%a1),%fp0 # FP0 IS R = (X-Y1)-Y2 + + ror.l &5,%d1 + and.l &0x80000000,%d1 # D0 WAS ODD IFF D0 < 0 + +TANCONT: + fmovm.x &0x0c,-(%sp) # save fp2,fp3 + + cmp.l %d1,&0 + blt.w NODD + + fmov.x %fp0,%fp1 + fmul.x %fp1,%fp1 # S = R*R + + fmov.d TANQ4(%pc),%fp3 + fmov.d TANP3(%pc),%fp2 + + fmul.x %fp1,%fp3 # SQ4 + fmul.x %fp1,%fp2 # SP3 + + fadd.d TANQ3(%pc),%fp3 # Q3+SQ4 + fadd.x TANP2(%pc),%fp2 # P2+SP3 + + fmul.x %fp1,%fp3 # S(Q3+SQ4) + fmul.x %fp1,%fp2 # S(P2+SP3) + + fadd.x TANQ2(%pc),%fp3 # Q2+S(Q3+SQ4) + fadd.x TANP1(%pc),%fp2 # P1+S(P2+SP3) + + fmul.x %fp1,%fp3 # S(Q2+S(Q3+SQ4)) + fmul.x %fp1,%fp2 # S(P1+S(P2+SP3)) + + fadd.x TANQ1(%pc),%fp3 # Q1+S(Q2+S(Q3+SQ4)) + fmul.x %fp0,%fp2 # RS(P1+S(P2+SP3)) + + fmul.x %fp3,%fp1 # S(Q1+S(Q2+S(Q3+SQ4))) + + fadd.x %fp2,%fp0 # R+RS(P1+S(P2+SP3)) + + fadd.s &0x3F800000,%fp1 # 1+S(Q1+...) + + fmovm.x (%sp)+,&0x30 # restore fp2,fp3 + + fmov.l %d0,%fpcr # restore users round mode,prec + fdiv.x %fp1,%fp0 # last inst - possible exception set + bra t_inx2 + +NODD: + fmov.x %fp0,%fp1 + fmul.x %fp0,%fp0 # S = R*R + + fmov.d TANQ4(%pc),%fp3 + fmov.d TANP3(%pc),%fp2 + + fmul.x %fp0,%fp3 # SQ4 + fmul.x %fp0,%fp2 # SP3 + + fadd.d TANQ3(%pc),%fp3 # Q3+SQ4 + fadd.x TANP2(%pc),%fp2 # P2+SP3 + + fmul.x %fp0,%fp3 # S(Q3+SQ4) + fmul.x %fp0,%fp2 # S(P2+SP3) + + fadd.x TANQ2(%pc),%fp3 # Q2+S(Q3+SQ4) + fadd.x TANP1(%pc),%fp2 # P1+S(P2+SP3) + + fmul.x %fp0,%fp3 # S(Q2+S(Q3+SQ4)) + fmul.x %fp0,%fp2 # S(P1+S(P2+SP3)) + + fadd.x TANQ1(%pc),%fp3 # Q1+S(Q2+S(Q3+SQ4)) + fmul.x %fp1,%fp2 # RS(P1+S(P2+SP3)) + + fmul.x %fp3,%fp0 # S(Q1+S(Q2+S(Q3+SQ4))) + + fadd.x %fp2,%fp1 # R+RS(P1+S(P2+SP3)) + fadd.s &0x3F800000,%fp0 # 1+S(Q1+...) + + fmovm.x (%sp)+,&0x30 # restore fp2,fp3 + + fmov.x %fp1,-(%sp) + eor.l &0x80000000,(%sp) + + fmov.l %d0,%fpcr # restore users round mode,prec + fdiv.x (%sp)+,%fp0 # last inst - possible exception set + bra t_inx2 + +TANBORS: +#--IF |X| > 15PI, WE USE THE GENERAL ARGUMENT REDUCTION. +#--IF |X| < 2**(-40), RETURN X OR 1. + cmp.l %d1,&0x3FFF8000 + bgt.b REDUCEX + +TANSM: + fmov.x %fp0,-(%sp) + fmov.l %d0,%fpcr # restore users round mode,prec + mov.b &FMOV_OP,%d1 # last inst is MOVE + fmov.x (%sp)+,%fp0 # last inst - posibble exception set + bra t_catch + + global stand +#--TAN(X) = X FOR DENORMALIZED X +stand: + bra t_extdnrm + +#--WHEN REDUCEX IS USED, THE CODE WILL INEVITABLY BE SLOW. +#--THIS REDUCTION METHOD, HOWEVER, IS MUCH FASTER THAN USING +#--THE REMAINDER INSTRUCTION WHICH IS NOW IN SOFTWARE. +REDUCEX: + fmovm.x &0x3c,-(%sp) # save {fp2-fp5} + mov.l %d2,-(%sp) # save d2 + fmov.s &0x00000000,%fp1 # fp1 = 0 + +#--If compact form of abs(arg) in d0=$7ffeffff, argument is so large that +#--there is a danger of unwanted overflow in first LOOP iteration. In this +#--case, reduce argument by one remainder step to make subsequent reduction +#--safe. + cmp.l %d1,&0x7ffeffff # is arg dangerously large? + bne.b LOOP # no + +# yes; create 2**16383*PI/2 + mov.w &0x7ffe,FP_SCR0_EX(%a6) + mov.l &0xc90fdaa2,FP_SCR0_HI(%a6) + clr.l FP_SCR0_LO(%a6) + +# create low half of 2**16383*PI/2 at FP_SCR1 + mov.w &0x7fdc,FP_SCR1_EX(%a6) + mov.l &0x85a308d3,FP_SCR1_HI(%a6) + clr.l FP_SCR1_LO(%a6) + + ftest.x %fp0 # test sign of argument + fblt.w red_neg + + or.b &0x80,FP_SCR0_EX(%a6) # positive arg + or.b &0x80,FP_SCR1_EX(%a6) +red_neg: + fadd.x FP_SCR0(%a6),%fp0 # high part of reduction is exact + fmov.x %fp0,%fp1 # save high result in fp1 + fadd.x FP_SCR1(%a6),%fp0 # low part of reduction + fsub.x %fp0,%fp1 # determine low component of result + fadd.x FP_SCR1(%a6),%fp1 # fp0/fp1 are reduced argument. + +#--ON ENTRY, FP0 IS X, ON RETURN, FP0 IS X REM PI/2, |X| <= PI/4. +#--integer quotient will be stored in N +#--Intermeditate remainder is 66-bit long; (R,r) in (FP0,FP1) +LOOP: + fmov.x %fp0,INARG(%a6) # +-2**K * F, 1 <= F < 2 + mov.w INARG(%a6),%d1 + mov.l %d1,%a1 # save a copy of D0 + and.l &0x00007FFF,%d1 + sub.l &0x00003FFF,%d1 # d0 = K + cmp.l %d1,&28 + ble.b LASTLOOP +CONTLOOP: + sub.l &27,%d1 # d0 = L := K-27 + mov.b &0,ENDFLAG(%a6) + bra.b WORK +LASTLOOP: + clr.l %d1 # d0 = L := 0 + mov.b &1,ENDFLAG(%a6) + +WORK: +#--FIND THE REMAINDER OF (R,r) W.R.T. 2**L * (PI/2). L IS SO CHOSEN +#--THAT INT( X * (2/PI) / 2**(L) ) < 2**29. + +#--CREATE 2**(-L) * (2/PI), SIGN(INARG)*2**(63), +#--2**L * (PIby2_1), 2**L * (PIby2_2) + + mov.l &0x00003FFE,%d2 # BIASED EXP OF 2/PI + sub.l %d1,%d2 # BIASED EXP OF 2**(-L)*(2/PI) + + mov.l &0xA2F9836E,FP_SCR0_HI(%a6) + mov.l &0x4E44152A,FP_SCR0_LO(%a6) + mov.w %d2,FP_SCR0_EX(%a6) # FP_SCR0 = 2**(-L)*(2/PI) + + fmov.x %fp0,%fp2 + fmul.x FP_SCR0(%a6),%fp2 # fp2 = X * 2**(-L)*(2/PI) + +#--WE MUST NOW FIND INT(FP2). SINCE WE NEED THIS VALUE IN +#--FLOATING POINT FORMAT, THE TWO FMOVE'S FMOVE.L FP <--> N +#--WILL BE TOO INEFFICIENT. THE WAY AROUND IT IS THAT +#--(SIGN(INARG)*2**63 + FP2) - SIGN(INARG)*2**63 WILL GIVE +#--US THE DESIRED VALUE IN FLOATING POINT. + mov.l %a1,%d2 + swap %d2 + and.l &0x80000000,%d2 + or.l &0x5F000000,%d2 # d2 = SIGN(INARG)*2**63 IN SGL + mov.l %d2,TWOTO63(%a6) + fadd.s TWOTO63(%a6),%fp2 # THE FRACTIONAL PART OF FP1 IS ROUNDED + fsub.s TWOTO63(%a6),%fp2 # fp2 = N +# fintrz.x %fp2,%fp2 + +#--CREATING 2**(L)*Piby2_1 and 2**(L)*Piby2_2 + mov.l %d1,%d2 # d2 = L + + add.l &0x00003FFF,%d2 # BIASED EXP OF 2**L * (PI/2) + mov.w %d2,FP_SCR0_EX(%a6) + mov.l &0xC90FDAA2,FP_SCR0_HI(%a6) + clr.l FP_SCR0_LO(%a6) # FP_SCR0 = 2**(L) * Piby2_1 + + add.l &0x00003FDD,%d1 + mov.w %d1,FP_SCR1_EX(%a6) + mov.l &0x85A308D3,FP_SCR1_HI(%a6) + clr.l FP_SCR1_LO(%a6) # FP_SCR1 = 2**(L) * Piby2_2 + + mov.b ENDFLAG(%a6),%d1 + +#--We are now ready to perform (R+r) - N*P1 - N*P2, P1 = 2**(L) * Piby2_1 and +#--P2 = 2**(L) * Piby2_2 + fmov.x %fp2,%fp4 # fp4 = N + fmul.x FP_SCR0(%a6),%fp4 # fp4 = W = N*P1 + fmov.x %fp2,%fp5 # fp5 = N + fmul.x FP_SCR1(%a6),%fp5 # fp5 = w = N*P2 + fmov.x %fp4,%fp3 # fp3 = W = N*P1 + +#--we want P+p = W+w but |p| <= half ulp of P +#--Then, we need to compute A := R-P and a := r-p + fadd.x %fp5,%fp3 # fp3 = P + fsub.x %fp3,%fp4 # fp4 = W-P + + fsub.x %fp3,%fp0 # fp0 = A := R - P + fadd.x %fp5,%fp4 # fp4 = p = (W-P)+w + + fmov.x %fp0,%fp3 # fp3 = A + fsub.x %fp4,%fp1 # fp1 = a := r - p + +#--Now we need to normalize (A,a) to "new (R,r)" where R+r = A+a but +#--|r| <= half ulp of R. + fadd.x %fp1,%fp0 # fp0 = R := A+a +#--No need to calculate r if this is the last loop + cmp.b %d1,&0 + bgt.w RESTORE + +#--Need to calculate r + fsub.x %fp0,%fp3 # fp3 = A-R + fadd.x %fp3,%fp1 # fp1 = r := (A-R)+a + bra.w LOOP + +RESTORE: + fmov.l %fp2,INT(%a6) + mov.l (%sp)+,%d2 # restore d2 + fmovm.x (%sp)+,&0x3c # restore {fp2-fp5} + + mov.l INT(%a6),%d1 + ror.l &1,%d1 + + bra.w TANCONT + +######################################################################### +# satan(): computes the arctangent of a normalized number # +# satand(): computes the arctangent of a denormalized number # +# # +# INPUT *************************************************************** # +# a0 = pointer to extended precision input # +# d0 = round precision,mode # +# # +# OUTPUT ************************************************************** # +# fp0 = arctan(X) # +# # +# ACCURACY and MONOTONICITY ******************************************* # +# The returned result is within 2 ulps in 64 significant bit, # +# i.e. within 0.5001 ulp to 53 bits if the result is subsequently # +# rounded to double precision. The result is provably monotonic # +# in double precision. # +# # +# ALGORITHM *********************************************************** # +# Step 1. If |X| >= 16 or |X| < 1/16, go to Step 5. # +# # +# Step 2. Let X = sgn * 2**k * 1.xxxxxxxx...x. # +# Note that k = -4, -3,..., or 3. # +# Define F = sgn * 2**k * 1.xxxx1, i.e. the first 5 # +# significant bits of X with a bit-1 attached at the 6-th # +# bit position. Define u to be u = (X-F) / (1 + X*F). # +# # +# Step 3. Approximate arctan(u) by a polynomial poly. # +# # +# Step 4. Return arctan(F) + poly, arctan(F) is fetched from a # +# table of values calculated beforehand. Exit. # +# # +# Step 5. If |X| >= 16, go to Step 7. # +# # +# Step 6. Approximate arctan(X) by an odd polynomial in X. Exit. # +# # +# Step 7. Define X' = -1/X. Approximate arctan(X') by an odd # +# polynomial in X'. # +# Arctan(X) = sign(X)*Pi/2 + arctan(X'). Exit. # +# # +######################################################################### + +ATANA3: long 0xBFF6687E,0x314987D8 +ATANA2: long 0x4002AC69,0x34A26DB3 +ATANA1: long 0xBFC2476F,0x4E1DA28E + +ATANB6: long 0x3FB34444,0x7F876989 +ATANB5: long 0xBFB744EE,0x7FAF45DB +ATANB4: long 0x3FBC71C6,0x46940220 +ATANB3: long 0xBFC24924,0x921872F9 +ATANB2: long 0x3FC99999,0x99998FA9 +ATANB1: long 0xBFD55555,0x55555555 + +ATANC5: long 0xBFB70BF3,0x98539E6A +ATANC4: long 0x3FBC7187,0x962D1D7D +ATANC3: long 0xBFC24924,0x827107B8 +ATANC2: long 0x3FC99999,0x9996263E +ATANC1: long 0xBFD55555,0x55555536 + +PPIBY2: long 0x3FFF0000,0xC90FDAA2,0x2168C235,0x00000000 +NPIBY2: long 0xBFFF0000,0xC90FDAA2,0x2168C235,0x00000000 + +PTINY: long 0x00010000,0x80000000,0x00000000,0x00000000 +NTINY: long 0x80010000,0x80000000,0x00000000,0x00000000 + +ATANTBL: + long 0x3FFB0000,0x83D152C5,0x060B7A51,0x00000000 + long 0x3FFB0000,0x8BC85445,0x65498B8B,0x00000000 + long 0x3FFB0000,0x93BE4060,0x17626B0D,0x00000000 + long 0x3FFB0000,0x9BB3078D,0x35AEC202,0x00000000 + long 0x3FFB0000,0xA3A69A52,0x5DDCE7DE,0x00000000 + long 0x3FFB0000,0xAB98E943,0x62765619,0x00000000 + long 0x3FFB0000,0xB389E502,0xF9C59862,0x00000000 + long 0x3FFB0000,0xBB797E43,0x6B09E6FB,0x00000000 + long 0x3FFB0000,0xC367A5C7,0x39E5F446,0x00000000 + long 0x3FFB0000,0xCB544C61,0xCFF7D5C6,0x00000000 + long 0x3FFB0000,0xD33F62F8,0x2488533E,0x00000000 + long 0x3FFB0000,0xDB28DA81,0x62404C77,0x00000000 + long 0x3FFB0000,0xE310A407,0x8AD34F18,0x00000000 + long 0x3FFB0000,0xEAF6B0A8,0x188EE1EB,0x00000000 + long 0x3FFB0000,0xF2DAF194,0x9DBE79D5,0x00000000 + long 0x3FFB0000,0xFABD5813,0x61D47E3E,0x00000000 + long 0x3FFC0000,0x8346AC21,0x0959ECC4,0x00000000 + long 0x3FFC0000,0x8B232A08,0x304282D8,0x00000000 + long 0x3FFC0000,0x92FB70B8,0xD29AE2F9,0x00000000 + long 0x3FFC0000,0x9ACF476F,0x5CCD1CB4,0x00000000 + long 0x3FFC0000,0xA29E7630,0x4954F23F,0x00000000 + long 0x3FFC0000,0xAA68C5D0,0x8AB85230,0x00000000 + long 0x3FFC0000,0xB22DFFFD,0x9D539F83,0x00000000 + long 0x3FFC0000,0xB9EDEF45,0x3E900EA5,0x00000000 + long 0x3FFC0000,0xC1A85F1C,0xC75E3EA5,0x00000000 + long 0x3FFC0000,0xC95D1BE8,0x28138DE6,0x00000000 + long 0x3FFC0000,0xD10BF300,0x840D2DE4,0x00000000 + long 0x3FFC0000,0xD8B4B2BA,0x6BC05E7A,0x00000000 + long 0x3FFC0000,0xE0572A6B,0xB42335F6,0x00000000 + long 0x3FFC0000,0xE7F32A70,0xEA9CAA8F,0x00000000 + long 0x3FFC0000,0xEF888432,0x64ECEFAA,0x00000000 + long 0x3FFC0000,0xF7170A28,0xECC06666,0x00000000 + long 0x3FFD0000,0x812FD288,0x332DAD32,0x00000000 + long 0x3FFD0000,0x88A8D1B1,0x218E4D64,0x00000000 + long 0x3FFD0000,0x9012AB3F,0x23E4AEE8,0x00000000 + long 0x3FFD0000,0x976CC3D4,0x11E7F1B9,0x00000000 + long 0x3FFD0000,0x9EB68949,0x3889A227,0x00000000 + long 0x3FFD0000,0xA5EF72C3,0x4487361B,0x00000000 + long 0x3FFD0000,0xAD1700BA,0xF07A7227,0x00000000 + long 0x3FFD0000,0xB42CBCFA,0xFD37EFB7,0x00000000 + long 0x3FFD0000,0xBB303A94,0x0BA80F89,0x00000000 + long 0x3FFD0000,0xC22115C6,0xFCAEBBAF,0x00000000 + long 0x3FFD0000,0xC8FEF3E6,0x86331221,0x00000000 + long 0x3FFD0000,0xCFC98330,0xB4000C70,0x00000000 + long 0x3FFD0000,0xD6807AA1,0x102C5BF9,0x00000000 + long 0x3FFD0000,0xDD2399BC,0x31252AA3,0x00000000 + long 0x3FFD0000,0xE3B2A855,0x6B8FC517,0x00000000 + long 0x3FFD0000,0xEA2D764F,0x64315989,0x00000000 + long 0x3FFD0000,0xF3BF5BF8,0xBAD1A21D,0x00000000 + long 0x3FFE0000,0x801CE39E,0x0D205C9A,0x00000000 + long 0x3FFE0000,0x8630A2DA,0xDA1ED066,0x00000000 + long 0x3FFE0000,0x8C1AD445,0xF3E09B8C,0x00000000 + long 0x3FFE0000,0x91DB8F16,0x64F350E2,0x00000000 + long 0x3FFE0000,0x97731420,0x365E538C,0x00000000 + long 0x3FFE0000,0x9CE1C8E6,0xA0B8CDBA,0x00000000 + long 0x3FFE0000,0xA22832DB,0xCADAAE09,0x00000000 + long 0x3FFE0000,0xA746F2DD,0xB7602294,0x00000000 + long 0x3FFE0000,0xAC3EC0FB,0x997DD6A2,0x00000000 + long 0x3FFE0000,0xB110688A,0xEBDC6F6A,0x00000000 + long 0x3FFE0000,0xB5BCC490,0x59ECC4B0,0x00000000 + long 0x3FFE0000,0xBA44BC7D,0xD470782F,0x00000000 + long 0x3FFE0000,0xBEA94144,0xFD049AAC,0x00000000 + long 0x3FFE0000,0xC2EB4ABB,0x661628B6,0x00000000 + long 0x3FFE0000,0xC70BD54C,0xE602EE14,0x00000000 + long 0x3FFE0000,0xCD000549,0xADEC7159,0x00000000 + long 0x3FFE0000,0xD48457D2,0xD8EA4EA3,0x00000000 + long 0x3FFE0000,0xDB948DA7,0x12DECE3B,0x00000000 + long 0x3FFE0000,0xE23855F9,0x69E8096A,0x00000000 + long 0x3FFE0000,0xE8771129,0xC4353259,0x00000000 + long 0x3FFE0000,0xEE57C16E,0x0D379C0D,0x00000000 + long 0x3FFE0000,0xF3E10211,0xA87C3779,0x00000000 + long 0x3FFE0000,0xF919039D,0x758B8D41,0x00000000 + long 0x3FFE0000,0xFE058B8F,0x64935FB3,0x00000000 + long 0x3FFF0000,0x8155FB49,0x7B685D04,0x00000000 + long 0x3FFF0000,0x83889E35,0x49D108E1,0x00000000 + long 0x3FFF0000,0x859CFA76,0x511D724B,0x00000000 + long 0x3FFF0000,0x87952ECF,0xFF8131E7,0x00000000 + long 0x3FFF0000,0x89732FD1,0x9557641B,0x00000000 + long 0x3FFF0000,0x8B38CAD1,0x01932A35,0x00000000 + long 0x3FFF0000,0x8CE7A8D8,0x301EE6B5,0x00000000 + long 0x3FFF0000,0x8F46A39E,0x2EAE5281,0x00000000 + long 0x3FFF0000,0x922DA7D7,0x91888487,0x00000000 + long 0x3FFF0000,0x94D19FCB,0xDEDF5241,0x00000000 + long 0x3FFF0000,0x973AB944,0x19D2A08B,0x00000000 + long 0x3FFF0000,0x996FF00E,0x08E10B96,0x00000000 + long 0x3FFF0000,0x9B773F95,0x12321DA7,0x00000000 + long 0x3FFF0000,0x9D55CC32,0x0F935624,0x00000000 + long 0x3FFF0000,0x9F100575,0x006CC571,0x00000000 + long 0x3FFF0000,0xA0A9C290,0xD97CC06C,0x00000000 + long 0x3FFF0000,0xA22659EB,0xEBC0630A,0x00000000 + long 0x3FFF0000,0xA388B4AF,0xF6EF0EC9,0x00000000 + long 0x3FFF0000,0xA4D35F10,0x61D292C4,0x00000000 + long 0x3FFF0000,0xA60895DC,0xFBE3187E,0x00000000 + long 0x3FFF0000,0xA72A51DC,0x7367BEAC,0x00000000 + long 0x3FFF0000,0xA83A5153,0x0956168F,0x00000000 + long 0x3FFF0000,0xA93A2007,0x7539546E,0x00000000 + long 0x3FFF0000,0xAA9E7245,0x023B2605,0x00000000 + long 0x3FFF0000,0xAC4C84BA,0x6FE4D58F,0x00000000 + long 0x3FFF0000,0xADCE4A4A,0x606B9712,0x00000000 + long 0x3FFF0000,0xAF2A2DCD,0x8D263C9C,0x00000000 + long 0x3FFF0000,0xB0656F81,0xF22265C7,0x00000000 + long 0x3FFF0000,0xB1846515,0x0F71496A,0x00000000 + long 0x3FFF0000,0xB28AAA15,0x6F9ADA35,0x00000000 + long 0x3FFF0000,0xB37B44FF,0x3766B895,0x00000000 + long 0x3FFF0000,0xB458C3DC,0xE9630433,0x00000000 + long 0x3FFF0000,0xB525529D,0x562246BD,0x00000000 + long 0x3FFF0000,0xB5E2CCA9,0x5F9D88CC,0x00000000 + long 0x3FFF0000,0xB692CADA,0x7ACA1ADA,0x00000000 + long 0x3FFF0000,0xB736AEA7,0xA6925838,0x00000000 + long 0x3FFF0000,0xB7CFAB28,0x7E9F7B36,0x00000000 + long 0x3FFF0000,0xB85ECC66,0xCB219835,0x00000000 + long 0x3FFF0000,0xB8E4FD5A,0x20A593DA,0x00000000 + long 0x3FFF0000,0xB99F41F6,0x4AFF9BB5,0x00000000 + long 0x3FFF0000,0xBA7F1E17,0x842BBE7B,0x00000000 + long 0x3FFF0000,0xBB471285,0x7637E17D,0x00000000 + long 0x3FFF0000,0xBBFABE8A,0x4788DF6F,0x00000000 + long 0x3FFF0000,0xBC9D0FAD,0x2B689D79,0x00000000 + long 0x3FFF0000,0xBD306A39,0x471ECD86,0x00000000 + long 0x3FFF0000,0xBDB6C731,0x856AF18A,0x00000000 + long 0x3FFF0000,0xBE31CAC5,0x02E80D70,0x00000000 + long 0x3FFF0000,0xBEA2D55C,0xE33194E2,0x00000000 + long 0x3FFF0000,0xBF0B10B7,0xC03128F0,0x00000000 + long 0x3FFF0000,0xBF6B7A18,0xDACB778D,0x00000000 + long 0x3FFF0000,0xBFC4EA46,0x63FA18F6,0x00000000 + long 0x3FFF0000,0xC0181BDE,0x8B89A454,0x00000000 + long 0x3FFF0000,0xC065B066,0xCFBF6439,0x00000000 + long 0x3FFF0000,0xC0AE345F,0x56340AE6,0x00000000 + long 0x3FFF0000,0xC0F22291,0x9CB9E6A7,0x00000000 + + set X,FP_SCR0 + set XDCARE,X+2 + set XFRAC,X+4 + set XFRACLO,X+8 + + set ATANF,FP_SCR1 + set ATANFHI,ATANF+4 + set ATANFLO,ATANF+8 + + global satan +#--ENTRY POINT FOR ATAN(X), HERE X IS FINITE, NON-ZERO, AND NOT NAN'S +satan: + fmov.x (%a0),%fp0 # LOAD INPUT + + mov.l (%a0),%d1 + mov.w 4(%a0),%d1 + fmov.x %fp0,X(%a6) + and.l &0x7FFFFFFF,%d1 + + cmp.l %d1,&0x3FFB8000 # |X| >= 1/16? + bge.b ATANOK1 + bra.w ATANSM + +ATANOK1: + cmp.l %d1,&0x4002FFFF # |X| < 16 ? + ble.b ATANMAIN + bra.w ATANBIG + +#--THE MOST LIKELY CASE, |X| IN [1/16, 16). WE USE TABLE TECHNIQUE +#--THE IDEA IS ATAN(X) = ATAN(F) + ATAN( [X-F] / [1+XF] ). +#--SO IF F IS CHOSEN TO BE CLOSE TO X AND ATAN(F) IS STORED IN +#--A TABLE, ALL WE NEED IS TO APPROXIMATE ATAN(U) WHERE +#--U = (X-F)/(1+XF) IS SMALL (REMEMBER F IS CLOSE TO X). IT IS +#--TRUE THAT A DIVIDE IS NOW NEEDED, BUT THE APPROXIMATION FOR +#--ATAN(U) IS A VERY SHORT POLYNOMIAL AND THE INDEXING TO +#--FETCH F AND SAVING OF REGISTERS CAN BE ALL HIDED UNDER THE +#--DIVIDE. IN THE END THIS METHOD IS MUCH FASTER THAN A TRADITIONAL +#--ONE. NOTE ALSO THAT THE TRADITIONAL SCHEME THAT APPROXIMATE +#--ATAN(X) DIRECTLY WILL NEED TO USE A RATIONAL APPROXIMATION +#--(DIVISION NEEDED) ANYWAY BECAUSE A POLYNOMIAL APPROXIMATION +#--WILL INVOLVE A VERY LONG POLYNOMIAL. + +#--NOW WE SEE X AS +-2^K * 1.BBBBBBB....B <- 1. + 63 BITS +#--WE CHOSE F TO BE +-2^K * 1.BBBB1 +#--THAT IS IT MATCHES THE EXPONENT AND FIRST 5 BITS OF X, THE +#--SIXTH BITS IS SET TO BE 1. SINCE K = -4, -3, ..., 3, THERE +#--ARE ONLY 8 TIMES 16 = 2^7 = 128 |F|'S. SINCE ATAN(-|F|) IS +#-- -ATAN(|F|), WE NEED TO STORE ONLY ATAN(|F|). + +ATANMAIN: + + and.l &0xF8000000,XFRAC(%a6) # FIRST 5 BITS + or.l &0x04000000,XFRAC(%a6) # SET 6-TH BIT TO 1 + mov.l &0x00000000,XFRACLO(%a6) # LOCATION OF X IS NOW F + + fmov.x %fp0,%fp1 # FP1 IS X + fmul.x X(%a6),%fp1 # FP1 IS X*F, NOTE THAT X*F > 0 + fsub.x X(%a6),%fp0 # FP0 IS X-F + fadd.s &0x3F800000,%fp1 # FP1 IS 1 + X*F + fdiv.x %fp1,%fp0 # FP0 IS U = (X-F)/(1+X*F) + +#--WHILE THE DIVISION IS TAKING ITS TIME, WE FETCH ATAN(|F|) +#--CREATE ATAN(F) AND STORE IT IN ATANF, AND +#--SAVE REGISTERS FP2. + + mov.l %d2,-(%sp) # SAVE d2 TEMPORARILY + mov.l %d1,%d2 # THE EXP AND 16 BITS OF X + and.l &0x00007800,%d1 # 4 VARYING BITS OF F'S FRACTION + and.l &0x7FFF0000,%d2 # EXPONENT OF F + sub.l &0x3FFB0000,%d2 # K+4 + asr.l &1,%d2 + add.l %d2,%d1 # THE 7 BITS IDENTIFYING F + asr.l &7,%d1 # INDEX INTO TBL OF ATAN(|F|) + lea ATANTBL(%pc),%a1 + add.l %d1,%a1 # ADDRESS OF ATAN(|F|) + mov.l (%a1)+,ATANF(%a6) + mov.l (%a1)+,ATANFHI(%a6) + mov.l (%a1)+,ATANFLO(%a6) # ATANF IS NOW ATAN(|F|) + mov.l X(%a6),%d1 # LOAD SIGN AND EXPO. AGAIN + and.l &0x80000000,%d1 # SIGN(F) + or.l %d1,ATANF(%a6) # ATANF IS NOW SIGN(F)*ATAN(|F|) + mov.l (%sp)+,%d2 # RESTORE d2 + +#--THAT'S ALL I HAVE TO DO FOR NOW, +#--BUT ALAS, THE DIVIDE IS STILL CRANKING! + +#--U IN FP0, WE ARE NOW READY TO COMPUTE ATAN(U) AS +#--U + A1*U*V*(A2 + V*(A3 + V)), V = U*U +#--THE POLYNOMIAL MAY LOOK STRANGE, BUT IS NEVERTHELESS CORRECT. +#--THE NATURAL FORM IS U + U*V*(A1 + V*(A2 + V*A3)) +#--WHAT WE HAVE HERE IS MERELY A1 = A3, A2 = A1/A3, A3 = A2/A3. +#--THE REASON FOR THIS REARRANGEMENT IS TO MAKE THE INDEPENDENT +#--PARTS A1*U*V AND (A2 + ... STUFF) MORE LOAD-BALANCED + + fmovm.x &0x04,-(%sp) # save fp2 + + fmov.x %fp0,%fp1 + fmul.x %fp1,%fp1 + fmov.d ATANA3(%pc),%fp2 + fadd.x %fp1,%fp2 # A3+V + fmul.x %fp1,%fp2 # V*(A3+V) + fmul.x %fp0,%fp1 # U*V + fadd.d ATANA2(%pc),%fp2 # A2+V*(A3+V) + fmul.d ATANA1(%pc),%fp1 # A1*U*V + fmul.x %fp2,%fp1 # A1*U*V*(A2+V*(A3+V)) + fadd.x %fp1,%fp0 # ATAN(U), FP1 RELEASED + + fmovm.x (%sp)+,&0x20 # restore fp2 + + fmov.l %d0,%fpcr # restore users rnd mode,prec + fadd.x ATANF(%a6),%fp0 # ATAN(X) + bra t_inx2 + +ATANBORS: +#--|X| IS IN d0 IN COMPACT FORM. FP1, d0 SAVED. +#--FP0 IS X AND |X| <= 1/16 OR |X| >= 16. + cmp.l %d1,&0x3FFF8000 + bgt.w ATANBIG # I.E. |X| >= 16 + +ATANSM: +#--|X| <= 1/16 +#--IF |X| < 2^(-40), RETURN X AS ANSWER. OTHERWISE, APPROXIMATE +#--ATAN(X) BY X + X*Y*(B1+Y*(B2+Y*(B3+Y*(B4+Y*(B5+Y*B6))))) +#--WHICH IS X + X*Y*( [B1+Z*(B3+Z*B5)] + [Y*(B2+Z*(B4+Z*B6)] ) +#--WHERE Y = X*X, AND Z = Y*Y. + + cmp.l %d1,&0x3FD78000 + blt.w ATANTINY + +#--COMPUTE POLYNOMIAL + fmovm.x &0x0c,-(%sp) # save fp2/fp3 + + fmul.x %fp0,%fp0 # FPO IS Y = X*X + + fmov.x %fp0,%fp1 + fmul.x %fp1,%fp1 # FP1 IS Z = Y*Y + + fmov.d ATANB6(%pc),%fp2 + fmov.d ATANB5(%pc),%fp3 + + fmul.x %fp1,%fp2 # Z*B6 + fmul.x %fp1,%fp3 # Z*B5 + + fadd.d ATANB4(%pc),%fp2 # B4+Z*B6 + fadd.d ATANB3(%pc),%fp3 # B3+Z*B5 + + fmul.x %fp1,%fp2 # Z*(B4+Z*B6) + fmul.x %fp3,%fp1 # Z*(B3+Z*B5) + + fadd.d ATANB2(%pc),%fp2 # B2+Z*(B4+Z*B6) + fadd.d ATANB1(%pc),%fp1 # B1+Z*(B3+Z*B5) + + fmul.x %fp0,%fp2 # Y*(B2+Z*(B4+Z*B6)) + fmul.x X(%a6),%fp0 # X*Y + + fadd.x %fp2,%fp1 # [B1+Z*(B3+Z*B5)]+[Y*(B2+Z*(B4+Z*B6))] + + fmul.x %fp1,%fp0 # X*Y*([B1+Z*(B3+Z*B5)]+[Y*(B2+Z*(B4+Z*B6))]) + + fmovm.x (%sp)+,&0x30 # restore fp2/fp3 + + fmov.l %d0,%fpcr # restore users rnd mode,prec + fadd.x X(%a6),%fp0 + bra t_inx2 + +ATANTINY: +#--|X| < 2^(-40), ATAN(X) = X + + fmov.l %d0,%fpcr # restore users rnd mode,prec + mov.b &FMOV_OP,%d1 # last inst is MOVE + fmov.x X(%a6),%fp0 # last inst - possible exception set + + bra t_catch + +ATANBIG: +#--IF |X| > 2^(100), RETURN SIGN(X)*(PI/2 - TINY). OTHERWISE, +#--RETURN SIGN(X)*PI/2 + ATAN(-1/X). + cmp.l %d1,&0x40638000 + bgt.w ATANHUGE + +#--APPROXIMATE ATAN(-1/X) BY +#--X'+X'*Y*(C1+Y*(C2+Y*(C3+Y*(C4+Y*C5)))), X' = -1/X, Y = X'*X' +#--THIS CAN BE RE-WRITTEN AS +#--X'+X'*Y*( [C1+Z*(C3+Z*C5)] + [Y*(C2+Z*C4)] ), Z = Y*Y. + + fmovm.x &0x0c,-(%sp) # save fp2/fp3 + + fmov.s &0xBF800000,%fp1 # LOAD -1 + fdiv.x %fp0,%fp1 # FP1 IS -1/X + +#--DIVIDE IS STILL CRANKING + + fmov.x %fp1,%fp0 # FP0 IS X' + fmul.x %fp0,%fp0 # FP0 IS Y = X'*X' + fmov.x %fp1,X(%a6) # X IS REALLY X' + + fmov.x %fp0,%fp1 + fmul.x %fp1,%fp1 # FP1 IS Z = Y*Y + + fmov.d ATANC5(%pc),%fp3 + fmov.d ATANC4(%pc),%fp2 + + fmul.x %fp1,%fp3 # Z*C5 + fmul.x %fp1,%fp2 # Z*B4 + + fadd.d ATANC3(%pc),%fp3 # C3+Z*C5 + fadd.d ATANC2(%pc),%fp2 # C2+Z*C4 + + fmul.x %fp3,%fp1 # Z*(C3+Z*C5), FP3 RELEASED + fmul.x %fp0,%fp2 # Y*(C2+Z*C4) + + fadd.d ATANC1(%pc),%fp1 # C1+Z*(C3+Z*C5) + fmul.x X(%a6),%fp0 # X'*Y + + fadd.x %fp2,%fp1 # [Y*(C2+Z*C4)]+[C1+Z*(C3+Z*C5)] + + fmul.x %fp1,%fp0 # X'*Y*([B1+Z*(B3+Z*B5)] +# ... +[Y*(B2+Z*(B4+Z*B6))]) + fadd.x X(%a6),%fp0 + + fmovm.x (%sp)+,&0x30 # restore fp2/fp3 + + fmov.l %d0,%fpcr # restore users rnd mode,prec + tst.b (%a0) + bpl.b pos_big + +neg_big: + fadd.x NPIBY2(%pc),%fp0 + bra t_minx2 + +pos_big: + fadd.x PPIBY2(%pc),%fp0 + bra t_pinx2 + +ATANHUGE: +#--RETURN SIGN(X)*(PIBY2 - TINY) = SIGN(X)*PIBY2 - SIGN(X)*TINY + tst.b (%a0) + bpl.b pos_huge + +neg_huge: + fmov.x NPIBY2(%pc),%fp0 + fmov.l %d0,%fpcr + fadd.x PTINY(%pc),%fp0 + bra t_minx2 + +pos_huge: + fmov.x PPIBY2(%pc),%fp0 + fmov.l %d0,%fpcr + fadd.x NTINY(%pc),%fp0 + bra t_pinx2 + + global satand +#--ENTRY POINT FOR ATAN(X) FOR DENORMALIZED ARGUMENT +satand: + bra t_extdnrm + +######################################################################### +# sasin(): computes the inverse sine of a normalized input # +# sasind(): computes the inverse sine of a denormalized input # +# # +# INPUT *************************************************************** # +# a0 = pointer to extended precision input # +# d0 = round precision,mode # +# # +# OUTPUT ************************************************************** # +# fp0 = arcsin(X) # +# # +# ACCURACY and MONOTONICITY ******************************************* # +# The returned result is within 3 ulps in 64 significant bit, # +# i.e. within 0.5001 ulp to 53 bits if the result is subsequently # +# rounded to double precision. The result is provably monotonic # +# in double precision. # +# # +# ALGORITHM *********************************************************** # +# # +# ASIN # +# 1. If |X| >= 1, go to 3. # +# # +# 2. (|X| < 1) Calculate asin(X) by # +# z := sqrt( [1-X][1+X] ) # +# asin(X) = atan( x / z ). # +# Exit. # +# # +# 3. If |X| > 1, go to 5. # +# # +# 4. (|X| = 1) sgn := sign(X), return asin(X) := sgn * Pi/2. Exit.# +# # +# 5. (|X| > 1) Generate an invalid operation by 0 * infinity. # +# Exit. # +# # +######################################################################### + + global sasin +sasin: + fmov.x (%a0),%fp0 # LOAD INPUT + + mov.l (%a0),%d1 + mov.w 4(%a0),%d1 + and.l &0x7FFFFFFF,%d1 + cmp.l %d1,&0x3FFF8000 + bge.b ASINBIG + +# This catch is added here for the '060 QSP. Originally, the call to +# satan() would handle this case by causing the exception which would +# not be caught until gen_except(). Now, with the exceptions being +# detected inside of satan(), the exception would have been handled there +# instead of inside sasin() as expected. + cmp.l %d1,&0x3FD78000 + blt.w ASINTINY + +#--THIS IS THE USUAL CASE, |X| < 1 +#--ASIN(X) = ATAN( X / SQRT( (1-X)(1+X) ) ) + +ASINMAIN: + fmov.s &0x3F800000,%fp1 + fsub.x %fp0,%fp1 # 1-X + fmovm.x &0x4,-(%sp) # {fp2} + fmov.s &0x3F800000,%fp2 + fadd.x %fp0,%fp2 # 1+X + fmul.x %fp2,%fp1 # (1+X)(1-X) + fmovm.x (%sp)+,&0x20 # {fp2} + fsqrt.x %fp1 # SQRT([1-X][1+X]) + fdiv.x %fp1,%fp0 # X/SQRT([1-X][1+X]) + fmovm.x &0x01,-(%sp) # save X/SQRT(...) + lea (%sp),%a0 # pass ptr to X/SQRT(...) + bsr satan + add.l &0xc,%sp # clear X/SQRT(...) from stack + bra t_inx2 + +ASINBIG: + fabs.x %fp0 # |X| + fcmp.s %fp0,&0x3F800000 + fbgt t_operr # cause an operr exception + +#--|X| = 1, ASIN(X) = +- PI/2. +ASINONE: + fmov.x PIBY2(%pc),%fp0 + mov.l (%a0),%d1 + and.l &0x80000000,%d1 # SIGN BIT OF X + or.l &0x3F800000,%d1 # +-1 IN SGL FORMAT + mov.l %d1,-(%sp) # push SIGN(X) IN SGL-FMT + fmov.l %d0,%fpcr + fmul.s (%sp)+,%fp0 + bra t_inx2 + +#--|X| < 2^(-40), ATAN(X) = X +ASINTINY: + fmov.l %d0,%fpcr # restore users rnd mode,prec + mov.b &FMOV_OP,%d1 # last inst is MOVE + fmov.x (%a0),%fp0 # last inst - possible exception + bra t_catch + + global sasind +#--ASIN(X) = X FOR DENORMALIZED X +sasind: + bra t_extdnrm + +######################################################################### +# sacos(): computes the inverse cosine of a normalized input # +# sacosd(): computes the inverse cosine of a denormalized input # +# # +# INPUT *************************************************************** # +# a0 = pointer to extended precision input # +# d0 = round precision,mode # +# # +# OUTPUT ************************************************************** # +# fp0 = arccos(X) # +# # +# ACCURACY and MONOTONICITY ******************************************* # +# The returned result is within 3 ulps in 64 significant bit, # +# i.e. within 0.5001 ulp to 53 bits if the result is subsequently # +# rounded to double precision. The result is provably monotonic # +# in double precision. # +# # +# ALGORITHM *********************************************************** # +# # +# ACOS # +# 1. If |X| >= 1, go to 3. # +# # +# 2. (|X| < 1) Calculate acos(X) by # +# z := (1-X) / (1+X) # +# acos(X) = 2 * atan( sqrt(z) ). # +# Exit. # +# # +# 3. If |X| > 1, go to 5. # +# # +# 4. (|X| = 1) If X > 0, return 0. Otherwise, return Pi. Exit. # +# # +# 5. (|X| > 1) Generate an invalid operation by 0 * infinity. # +# Exit. # +# # +######################################################################### + + global sacos +sacos: + fmov.x (%a0),%fp0 # LOAD INPUT + + mov.l (%a0),%d1 # pack exp w/ upper 16 fraction + mov.w 4(%a0),%d1 + and.l &0x7FFFFFFF,%d1 + cmp.l %d1,&0x3FFF8000 + bge.b ACOSBIG + +#--THIS IS THE USUAL CASE, |X| < 1 +#--ACOS(X) = 2 * ATAN( SQRT( (1-X)/(1+X) ) ) + +ACOSMAIN: + fmov.s &0x3F800000,%fp1 + fadd.x %fp0,%fp1 # 1+X + fneg.x %fp0 # -X + fadd.s &0x3F800000,%fp0 # 1-X + fdiv.x %fp1,%fp0 # (1-X)/(1+X) + fsqrt.x %fp0 # SQRT((1-X)/(1+X)) + mov.l %d0,-(%sp) # save original users fpcr + clr.l %d0 + fmovm.x &0x01,-(%sp) # save SQRT(...) to stack + lea (%sp),%a0 # pass ptr to sqrt + bsr satan # ATAN(SQRT([1-X]/[1+X])) + add.l &0xc,%sp # clear SQRT(...) from stack + + fmov.l (%sp)+,%fpcr # restore users round prec,mode + fadd.x %fp0,%fp0 # 2 * ATAN( STUFF ) + bra t_pinx2 + +ACOSBIG: + fabs.x %fp0 + fcmp.s %fp0,&0x3F800000 + fbgt t_operr # cause an operr exception + +#--|X| = 1, ACOS(X) = 0 OR PI + tst.b (%a0) # is X positive or negative? + bpl.b ACOSP1 + +#--X = -1 +#Returns PI and inexact exception +ACOSM1: + fmov.x PI(%pc),%fp0 # load PI + fmov.l %d0,%fpcr # load round mode,prec + fadd.s &0x00800000,%fp0 # add a small value + bra t_pinx2 + +ACOSP1: + bra ld_pzero # answer is positive zero + + global sacosd +#--ACOS(X) = PI/2 FOR DENORMALIZED X +sacosd: + fmov.l %d0,%fpcr # load user's rnd mode/prec + fmov.x PIBY2(%pc),%fp0 + bra t_pinx2 + +######################################################################### +# setox(): computes the exponential for a normalized input # +# setoxd(): computes the exponential for a denormalized input # +# setoxm1(): computes the exponential minus 1 for a normalized input # +# setoxm1d(): computes the exponential minus 1 for a denormalized input # +# # +# INPUT *************************************************************** # +# a0 = pointer to extended precision input # +# d0 = round precision,mode # +# # +# OUTPUT ************************************************************** # +# fp0 = exp(X) or exp(X)-1 # +# # +# ACCURACY and MONOTONICITY ******************************************* # +# The returned result is within 0.85 ulps in 64 significant bit, # +# i.e. within 0.5001 ulp to 53 bits if the result is subsequently # +# rounded to double precision. The result is provably monotonic # +# in double precision. # +# # +# ALGORITHM and IMPLEMENTATION **************************************** # +# # +# setoxd # +# ------ # +# Step 1. Set ans := 1.0 # +# # +# Step 2. Return ans := ans + sign(X)*2^(-126). Exit. # +# Notes: This will always generate one exception -- inexact. # +# # +# # +# setox # +# ----- # +# # +# Step 1. Filter out extreme cases of input argument. # +# 1.1 If |X| >= 2^(-65), go to Step 1.3. # +# 1.2 Go to Step 7. # +# 1.3 If |X| < 16380 log(2), go to Step 2. # +# 1.4 Go to Step 8. # +# Notes: The usual case should take the branches 1.1 -> 1.3 -> 2.# +# To avoid the use of floating-point comparisons, a # +# compact representation of |X| is used. This format is a # +# 32-bit integer, the upper (more significant) 16 bits # +# are the sign and biased exponent field of |X|; the # +# lower 16 bits are the 16 most significant fraction # +# (including the explicit bit) bits of |X|. Consequently, # +# the comparisons in Steps 1.1 and 1.3 can be performed # +# by integer comparison. Note also that the constant # +# 16380 log(2) used in Step 1.3 is also in the compact # +# form. Thus taking the branch to Step 2 guarantees # +# |X| < 16380 log(2). There is no harm to have a small # +# number of cases where |X| is less than, but close to, # +# 16380 log(2) and the branch to Step 9 is taken. # +# # +# Step 2. Calculate N = round-to-nearest-int( X * 64/log2 ). # +# 2.1 Set AdjFlag := 0 (indicates the branch 1.3 -> 2 # +# was taken) # +# 2.2 N := round-to-nearest-integer( X * 64/log2 ). # +# 2.3 Calculate J = N mod 64; so J = 0,1,2,..., # +# or 63. # +# 2.4 Calculate M = (N - J)/64; so N = 64M + J. # +# 2.5 Calculate the address of the stored value of # +# 2^(J/64). # +# 2.6 Create the value Scale = 2^M. # +# Notes: The calculation in 2.2 is really performed by # +# Z := X * constant # +# N := round-to-nearest-integer(Z) # +# where # +# constant := single-precision( 64/log 2 ). # +# # +# Using a single-precision constant avoids memory # +# access. Another effect of using a single-precision # +# "constant" is that the calculated value Z is # +# # +# Z = X*(64/log2)*(1+eps), |eps| <= 2^(-24). # +# # +# This error has to be considered later in Steps 3 and 4. # +# # +# Step 3. Calculate X - N*log2/64. # +# 3.1 R := X + N*L1, # +# where L1 := single-precision(-log2/64). # +# 3.2 R := R + N*L2, # +# L2 := extended-precision(-log2/64 - L1).# +# Notes: a) The way L1 and L2 are chosen ensures L1+L2 # +# approximate the value -log2/64 to 88 bits of accuracy. # +# b) N*L1 is exact because N is no longer than 22 bits # +# and L1 is no longer than 24 bits. # +# c) The calculation X+N*L1 is also exact due to # +# cancellation. Thus, R is practically X+N(L1+L2) to full # +# 64 bits. # +# d) It is important to estimate how large can |R| be # +# after Step 3.2. # +# # +# N = rnd-to-int( X*64/log2 (1+eps) ), |eps|<=2^(-24) # +# X*64/log2 (1+eps) = N + f, |f| <= 0.5 # +# X*64/log2 - N = f - eps*X 64/log2 # +# X - N*log2/64 = f*log2/64 - eps*X # +# # +# # +# Now |X| <= 16446 log2, thus # +# # +# |X - N*log2/64| <= (0.5 + 16446/2^(18))*log2/64 # +# <= 0.57 log2/64. # +# This bound will be used in Step 4. # +# # +# Step 4. Approximate exp(R)-1 by a polynomial # +# p = R + R*R*(A1 + R*(A2 + R*(A3 + R*(A4 + R*A5)))) # +# Notes: a) In order to reduce memory access, the coefficients # +# are made as "short" as possible: A1 (which is 1/2), A4 # +# and A5 are single precision; A2 and A3 are double # +# precision. # +# b) Even with the restrictions above, # +# |p - (exp(R)-1)| < 2^(-68.8) for all |R| <= 0.0062. # +# Note that 0.0062 is slightly bigger than 0.57 log2/64. # +# c) To fully utilize the pipeline, p is separated into # +# two independent pieces of roughly equal complexities # +# p = [ R + R*S*(A2 + S*A4) ] + # +# [ S*(A1 + S*(A3 + S*A5)) ] # +# where S = R*R. # +# # +# Step 5. Compute 2^(J/64)*exp(R) = 2^(J/64)*(1+p) by # +# ans := T + ( T*p + t) # +# where T and t are the stored values for 2^(J/64). # +# Notes: 2^(J/64) is stored as T and t where T+t approximates # +# 2^(J/64) to roughly 85 bits; T is in extended precision # +# and t is in single precision. Note also that T is # +# rounded to 62 bits so that the last two bits of T are # +# zero. The reason for such a special form is that T-1, # +# T-2, and T-8 will all be exact --- a property that will # +# give much more accurate computation of the function # +# EXPM1. # +# # +# Step 6. Reconstruction of exp(X) # +# exp(X) = 2^M * 2^(J/64) * exp(R). # +# 6.1 If AdjFlag = 0, go to 6.3 # +# 6.2 ans := ans * AdjScale # +# 6.3 Restore the user FPCR # +# 6.4 Return ans := ans * Scale. Exit. # +# Notes: If AdjFlag = 0, we have X = Mlog2 + Jlog2/64 + R, # +# |M| <= 16380, and Scale = 2^M. Moreover, exp(X) will # +# neither overflow nor underflow. If AdjFlag = 1, that # +# means that # +# X = (M1+M)log2 + Jlog2/64 + R, |M1+M| >= 16380. # +# Hence, exp(X) may overflow or underflow or neither. # +# When that is the case, AdjScale = 2^(M1) where M1 is # +# approximately M. Thus 6.2 will never cause # +# over/underflow. Possible exception in 6.4 is overflow # +# or underflow. The inexact exception is not generated in # +# 6.4. Although one can argue that the inexact flag # +# should always be raised, to simulate that exception # +# cost to much than the flag is worth in practical uses. # +# # +# Step 7. Return 1 + X. # +# 7.1 ans := X # +# 7.2 Restore user FPCR. # +# 7.3 Return ans := 1 + ans. Exit # +# Notes: For non-zero X, the inexact exception will always be # +# raised by 7.3. That is the only exception raised by 7.3.# +# Note also that we use the FMOVEM instruction to move X # +# in Step 7.1 to avoid unnecessary trapping. (Although # +# the FMOVEM may not seem relevant since X is normalized, # +# the precaution will be useful in the library version of # +# this code where the separate entry for denormalized # +# inputs will be done away with.) # +# # +# Step 8. Handle exp(X) where |X| >= 16380log2. # +# 8.1 If |X| > 16480 log2, go to Step 9. # +# (mimic 2.2 - 2.6) # +# 8.2 N := round-to-integer( X * 64/log2 ) # +# 8.3 Calculate J = N mod 64, J = 0,1,...,63 # +# 8.4 K := (N-J)/64, M1 := truncate(K/2), M = K-M1, # +# AdjFlag := 1. # +# 8.5 Calculate the address of the stored value # +# 2^(J/64). # +# 8.6 Create the values Scale = 2^M, AdjScale = 2^M1. # +# 8.7 Go to Step 3. # +# Notes: Refer to notes for 2.2 - 2.6. # +# # +# Step 9. Handle exp(X), |X| > 16480 log2. # +# 9.1 If X < 0, go to 9.3 # +# 9.2 ans := Huge, go to 9.4 # +# 9.3 ans := Tiny. # +# 9.4 Restore user FPCR. # +# 9.5 Return ans := ans * ans. Exit. # +# Notes: Exp(X) will surely overflow or underflow, depending on # +# X's sign. "Huge" and "Tiny" are respectively large/tiny # +# extended-precision numbers whose square over/underflow # +# with an inexact result. Thus, 9.5 always raises the # +# inexact together with either overflow or underflow. # +# # +# setoxm1d # +# -------- # +# # +# Step 1. Set ans := 0 # +# # +# Step 2. Return ans := X + ans. Exit. # +# Notes: This will return X with the appropriate rounding # +# precision prescribed by the user FPCR. # +# # +# setoxm1 # +# ------- # +# # +# Step 1. Check |X| # +# 1.1 If |X| >= 1/4, go to Step 1.3. # +# 1.2 Go to Step 7. # +# 1.3 If |X| < 70 log(2), go to Step 2. # +# 1.4 Go to Step 10. # +# Notes: The usual case should take the branches 1.1 -> 1.3 -> 2.# +# However, it is conceivable |X| can be small very often # +# because EXPM1 is intended to evaluate exp(X)-1 # +# accurately when |X| is small. For further details on # +# the comparisons, see the notes on Step 1 of setox. # +# # +# Step 2. Calculate N = round-to-nearest-int( X * 64/log2 ). # +# 2.1 N := round-to-nearest-integer( X * 64/log2 ). # +# 2.2 Calculate J = N mod 64; so J = 0,1,2,..., # +# or 63. # +# 2.3 Calculate M = (N - J)/64; so N = 64M + J. # +# 2.4 Calculate the address of the stored value of # +# 2^(J/64). # +# 2.5 Create the values Sc = 2^M and # +# OnebySc := -2^(-M). # +# Notes: See the notes on Step 2 of setox. # +# # +# Step 3. Calculate X - N*log2/64. # +# 3.1 R := X + N*L1, # +# where L1 := single-precision(-log2/64). # +# 3.2 R := R + N*L2, # +# L2 := extended-precision(-log2/64 - L1).# +# Notes: Applying the analysis of Step 3 of setox in this case # +# shows that |R| <= 0.0055 (note that |X| <= 70 log2 in # +# this case). # +# # +# Step 4. Approximate exp(R)-1 by a polynomial # +# p = R+R*R*(A1+R*(A2+R*(A3+R*(A4+R*(A5+R*A6))))) # +# Notes: a) In order to reduce memory access, the coefficients # +# are made as "short" as possible: A1 (which is 1/2), A5 # +# and A6 are single precision; A2, A3 and A4 are double # +# precision. # +# b) Even with the restriction above, # +# |p - (exp(R)-1)| < |R| * 2^(-72.7) # +# for all |R| <= 0.0055. # +# c) To fully utilize the pipeline, p is separated into # +# two independent pieces of roughly equal complexity # +# p = [ R*S*(A2 + S*(A4 + S*A6)) ] + # +# [ R + S*(A1 + S*(A3 + S*A5)) ] # +# where S = R*R. # +# # +# Step 5. Compute 2^(J/64)*p by # +# p := T*p # +# where T and t are the stored values for 2^(J/64). # +# Notes: 2^(J/64) is stored as T and t where T+t approximates # +# 2^(J/64) to roughly 85 bits; T is in extended precision # +# and t is in single precision. Note also that T is # +# rounded to 62 bits so that the last two bits of T are # +# zero. The reason for such a special form is that T-1, # +# T-2, and T-8 will all be exact --- a property that will # +# be exploited in Step 6 below. The total relative error # +# in p is no bigger than 2^(-67.7) compared to the final # +# result. # +# # +# Step 6. Reconstruction of exp(X)-1 # +# exp(X)-1 = 2^M * ( 2^(J/64) + p - 2^(-M) ). # +# 6.1 If M <= 63, go to Step 6.3. # +# 6.2 ans := T + (p + (t + OnebySc)). Go to 6.6 # +# 6.3 If M >= -3, go to 6.5. # +# 6.4 ans := (T + (p + t)) + OnebySc. Go to 6.6 # +# 6.5 ans := (T + OnebySc) + (p + t). # +# 6.6 Restore user FPCR. # +# 6.7 Return ans := Sc * ans. Exit. # +# Notes: The various arrangements of the expressions give # +# accurate evaluations. # +# # +# Step 7. exp(X)-1 for |X| < 1/4. # +# 7.1 If |X| >= 2^(-65), go to Step 9. # +# 7.2 Go to Step 8. # +# # +# Step 8. Calculate exp(X)-1, |X| < 2^(-65). # +# 8.1 If |X| < 2^(-16312), goto 8.3 # +# 8.2 Restore FPCR; return ans := X - 2^(-16382). # +# Exit. # +# 8.3 X := X * 2^(140). # +# 8.4 Restore FPCR; ans := ans - 2^(-16382). # +# Return ans := ans*2^(140). Exit # +# Notes: The idea is to return "X - tiny" under the user # +# precision and rounding modes. To avoid unnecessary # +# inefficiency, we stay away from denormalized numbers # +# the best we can. For |X| >= 2^(-16312), the # +# straightforward 8.2 generates the inexact exception as # +# the case warrants. # +# # +# Step 9. Calculate exp(X)-1, |X| < 1/4, by a polynomial # +# p = X + X*X*(B1 + X*(B2 + ... + X*B12)) # +# Notes: a) In order to reduce memory access, the coefficients # +# are made as "short" as possible: B1 (which is 1/2), B9 # +# to B12 are single precision; B3 to B8 are double # +# precision; and B2 is double extended. # +# b) Even with the restriction above, # +# |p - (exp(X)-1)| < |X| 2^(-70.6) # +# for all |X| <= 0.251. # +# Note that 0.251 is slightly bigger than 1/4. # +# c) To fully preserve accuracy, the polynomial is # +# computed as # +# X + ( S*B1 + Q ) where S = X*X and # +# Q = X*S*(B2 + X*(B3 + ... + X*B12)) # +# d) To fully utilize the pipeline, Q is separated into # +# two independent pieces of roughly equal complexity # +# Q = [ X*S*(B2 + S*(B4 + ... + S*B12)) ] + # +# [ S*S*(B3 + S*(B5 + ... + S*B11)) ] # +# # +# Step 10. Calculate exp(X)-1 for |X| >= 70 log 2. # +# 10.1 If X >= 70log2 , exp(X) - 1 = exp(X) for all # +# practical purposes. Therefore, go to Step 1 of setox. # +# 10.2 If X <= -70log2, exp(X) - 1 = -1 for all practical # +# purposes. # +# ans := -1 # +# Restore user FPCR # +# Return ans := ans + 2^(-126). Exit. # +# Notes: 10.2 will always create an inexact and return -1 + tiny # +# in the user rounding precision and mode. # +# # +######################################################################### + +L2: long 0x3FDC0000,0x82E30865,0x4361C4C6,0x00000000 + +EEXPA3: long 0x3FA55555,0x55554CC1 +EEXPA2: long 0x3FC55555,0x55554A54 + +EM1A4: long 0x3F811111,0x11174385 +EM1A3: long 0x3FA55555,0x55554F5A + +EM1A2: long 0x3FC55555,0x55555555,0x00000000,0x00000000 + +EM1B8: long 0x3EC71DE3,0xA5774682 +EM1B7: long 0x3EFA01A0,0x19D7CB68 + +EM1B6: long 0x3F2A01A0,0x1A019DF3 +EM1B5: long 0x3F56C16C,0x16C170E2 + +EM1B4: long 0x3F811111,0x11111111 +EM1B3: long 0x3FA55555,0x55555555 + +EM1B2: long 0x3FFC0000,0xAAAAAAAA,0xAAAAAAAB + long 0x00000000 + +TWO140: long 0x48B00000,0x00000000 +TWON140: + long 0x37300000,0x00000000 + +EEXPTBL: + long 0x3FFF0000,0x80000000,0x00000000,0x00000000 + long 0x3FFF0000,0x8164D1F3,0xBC030774,0x9F841A9B + long 0x3FFF0000,0x82CD8698,0xAC2BA1D8,0x9FC1D5B9 + long 0x3FFF0000,0x843A28C3,0xACDE4048,0xA0728369 + long 0x3FFF0000,0x85AAC367,0xCC487B14,0x1FC5C95C + long 0x3FFF0000,0x871F6196,0x9E8D1010,0x1EE85C9F + long 0x3FFF0000,0x88980E80,0x92DA8528,0x9FA20729 + long 0x3FFF0000,0x8A14D575,0x496EFD9C,0xA07BF9AF + long 0x3FFF0000,0x8B95C1E3,0xEA8BD6E8,0xA0020DCF + long 0x3FFF0000,0x8D1ADF5B,0x7E5BA9E4,0x205A63DA + long 0x3FFF0000,0x8EA4398B,0x45CD53C0,0x1EB70051 + long 0x3FFF0000,0x9031DC43,0x1466B1DC,0x1F6EB029 + long 0x3FFF0000,0x91C3D373,0xAB11C338,0xA0781494 + long 0x3FFF0000,0x935A2B2F,0x13E6E92C,0x9EB319B0 + long 0x3FFF0000,0x94F4EFA8,0xFEF70960,0x2017457D + long 0x3FFF0000,0x96942D37,0x20185A00,0x1F11D537 + long 0x3FFF0000,0x9837F051,0x8DB8A970,0x9FB952DD + long 0x3FFF0000,0x99E04593,0x20B7FA64,0x1FE43087 + long 0x3FFF0000,0x9B8D39B9,0xD54E5538,0x1FA2A818 + long 0x3FFF0000,0x9D3ED9A7,0x2CFFB750,0x1FDE494D + long 0x3FFF0000,0x9EF53260,0x91A111AC,0x20504890 + long 0x3FFF0000,0xA0B0510F,0xB9714FC4,0xA073691C + long 0x3FFF0000,0xA2704303,0x0C496818,0x1F9B7A05 + long 0x3FFF0000,0xA43515AE,0x09E680A0,0xA0797126 + long 0x3FFF0000,0xA5FED6A9,0xB15138EC,0xA071A140 + long 0x3FFF0000,0xA7CD93B4,0xE9653568,0x204F62DA + long 0x3FFF0000,0xA9A15AB4,0xEA7C0EF8,0x1F283C4A + long 0x3FFF0000,0xAB7A39B5,0xA93ED338,0x9F9A7FDC + long 0x3FFF0000,0xAD583EEA,0x42A14AC8,0xA05B3FAC + long 0x3FFF0000,0xAF3B78AD,0x690A4374,0x1FDF2610 + long 0x3FFF0000,0xB123F581,0xD2AC2590,0x9F705F90 + long 0x3FFF0000,0xB311C412,0xA9112488,0x201F678A + long 0x3FFF0000,0xB504F333,0xF9DE6484,0x1F32FB13 + long 0x3FFF0000,0xB6FD91E3,0x28D17790,0x20038B30 + long 0x3FFF0000,0xB8FBAF47,0x62FB9EE8,0x200DC3CC + long 0x3FFF0000,0xBAFF5AB2,0x133E45FC,0x9F8B2AE6 + long 0x3FFF0000,0xBD08A39F,0x580C36C0,0xA02BBF70 + long 0x3FFF0000,0xBF1799B6,0x7A731084,0xA00BF518 + long 0x3FFF0000,0xC12C4CCA,0x66709458,0xA041DD41 + long 0x3FFF0000,0xC346CCDA,0x24976408,0x9FDF137B + long 0x3FFF0000,0xC5672A11,0x5506DADC,0x201F1568 + long 0x3FFF0000,0xC78D74C8,0xABB9B15C,0x1FC13A2E + long 0x3FFF0000,0xC9B9BD86,0x6E2F27A4,0xA03F8F03 + long 0x3FFF0000,0xCBEC14FE,0xF2727C5C,0x1FF4907D + long 0x3FFF0000,0xCE248C15,0x1F8480E4,0x9E6E53E4 + long 0x3FFF0000,0xD06333DA,0xEF2B2594,0x1FD6D45C + long 0x3FFF0000,0xD2A81D91,0xF12AE45C,0xA076EDB9 + long 0x3FFF0000,0xD4F35AAB,0xCFEDFA20,0x9FA6DE21 + long 0x3FFF0000,0xD744FCCA,0xD69D6AF4,0x1EE69A2F + long 0x3FFF0000,0xD99D15C2,0x78AFD7B4,0x207F439F + long 0x3FFF0000,0xDBFBB797,0xDAF23754,0x201EC207 + long 0x3FFF0000,0xDE60F482,0x5E0E9124,0x9E8BE175 + long 0x3FFF0000,0xE0CCDEEC,0x2A94E110,0x20032C4B + long 0x3FFF0000,0xE33F8972,0xBE8A5A50,0x2004DFF5 + long 0x3FFF0000,0xE5B906E7,0x7C8348A8,0x1E72F47A + long 0x3FFF0000,0xE8396A50,0x3C4BDC68,0x1F722F22 + long 0x3FFF0000,0xEAC0C6E7,0xDD243930,0xA017E945 + long 0x3FFF0000,0xED4F301E,0xD9942B84,0x1F401A5B + long 0x3FFF0000,0xEFE4B99B,0xDCDAF5CC,0x9FB9A9E3 + long 0x3FFF0000,0xF281773C,0x59FFB138,0x20744C05 + long 0x3FFF0000,0xF5257D15,0x2486CC2C,0x1F773A19 + long 0x3FFF0000,0xF7D0DF73,0x0AD13BB8,0x1FFE90D5 + long 0x3FFF0000,0xFA83B2DB,0x722A033C,0xA041ED22 + long 0x3FFF0000,0xFD3E0C0C,0xF486C174,0x1F853F3A + + set ADJFLAG,L_SCR2 + set SCALE,FP_SCR0 + set ADJSCALE,FP_SCR1 + set SC,FP_SCR0 + set ONEBYSC,FP_SCR1 + + global setox +setox: +#--entry point for EXP(X), here X is finite, non-zero, and not NaN's + +#--Step 1. + mov.l (%a0),%d1 # load part of input X + and.l &0x7FFF0000,%d1 # biased expo. of X + cmp.l %d1,&0x3FBE0000 # 2^(-65) + bge.b EXPC1 # normal case + bra EXPSM + +EXPC1: +#--The case |X| >= 2^(-65) + mov.w 4(%a0),%d1 # expo. and partial sig. of |X| + cmp.l %d1,&0x400CB167 # 16380 log2 trunc. 16 bits + blt.b EXPMAIN # normal case + bra EEXPBIG + +EXPMAIN: +#--Step 2. +#--This is the normal branch: 2^(-65) <= |X| < 16380 log2. + fmov.x (%a0),%fp0 # load input from (a0) + + fmov.x %fp0,%fp1 + fmul.s &0x42B8AA3B,%fp0 # 64/log2 * X + fmovm.x &0xc,-(%sp) # save fp2 {%fp2/%fp3} + mov.l &0,ADJFLAG(%a6) + fmov.l %fp0,%d1 # N = int( X * 64/log2 ) + lea EEXPTBL(%pc),%a1 + fmov.l %d1,%fp0 # convert to floating-format + + mov.l %d1,L_SCR1(%a6) # save N temporarily + and.l &0x3F,%d1 # D0 is J = N mod 64 + lsl.l &4,%d1 + add.l %d1,%a1 # address of 2^(J/64) + mov.l L_SCR1(%a6),%d1 + asr.l &6,%d1 # D0 is M + add.w &0x3FFF,%d1 # biased expo. of 2^(M) + mov.w L2(%pc),L_SCR1(%a6) # prefetch L2, no need in CB + +EXPCONT1: +#--Step 3. +#--fp1,fp2 saved on the stack. fp0 is N, fp1 is X, +#--a0 points to 2^(J/64), D0 is biased expo. of 2^(M) + fmov.x %fp0,%fp2 + fmul.s &0xBC317218,%fp0 # N * L1, L1 = lead(-log2/64) + fmul.x L2(%pc),%fp2 # N * L2, L1+L2 = -log2/64 + fadd.x %fp1,%fp0 # X + N*L1 + fadd.x %fp2,%fp0 # fp0 is R, reduced arg. + +#--Step 4. +#--WE NOW COMPUTE EXP(R)-1 BY A POLYNOMIAL +#-- R + R*R*(A1 + R*(A2 + R*(A3 + R*(A4 + R*A5)))) +#--TO FULLY UTILIZE THE PIPELINE, WE COMPUTE S = R*R +#--[R+R*S*(A2+S*A4)] + [S*(A1+S*(A3+S*A5))] + + fmov.x %fp0,%fp1 + fmul.x %fp1,%fp1 # fp1 IS S = R*R + + fmov.s &0x3AB60B70,%fp2 # fp2 IS A5 + + fmul.x %fp1,%fp2 # fp2 IS S*A5 + fmov.x %fp1,%fp3 + fmul.s &0x3C088895,%fp3 # fp3 IS S*A4 + + fadd.d EEXPA3(%pc),%fp2 # fp2 IS A3+S*A5 + fadd.d EEXPA2(%pc),%fp3 # fp3 IS A2+S*A4 + + fmul.x %fp1,%fp2 # fp2 IS S*(A3+S*A5) + mov.w %d1,SCALE(%a6) # SCALE is 2^(M) in extended + mov.l &0x80000000,SCALE+4(%a6) + clr.l SCALE+8(%a6) + + fmul.x %fp1,%fp3 # fp3 IS S*(A2+S*A4) + + fadd.s &0x3F000000,%fp2 # fp2 IS A1+S*(A3+S*A5) + fmul.x %fp0,%fp3 # fp3 IS R*S*(A2+S*A4) + + fmul.x %fp1,%fp2 # fp2 IS S*(A1+S*(A3+S*A5)) + fadd.x %fp3,%fp0 # fp0 IS R+R*S*(A2+S*A4), + + fmov.x (%a1)+,%fp1 # fp1 is lead. pt. of 2^(J/64) + fadd.x %fp2,%fp0 # fp0 is EXP(R) - 1 + +#--Step 5 +#--final reconstruction process +#--EXP(X) = 2^M * ( 2^(J/64) + 2^(J/64)*(EXP(R)-1) ) + + fmul.x %fp1,%fp0 # 2^(J/64)*(Exp(R)-1) + fmovm.x (%sp)+,&0x30 # fp2 restored {%fp2/%fp3} + fadd.s (%a1),%fp0 # accurate 2^(J/64) + + fadd.x %fp1,%fp0 # 2^(J/64) + 2^(J/64)*... + mov.l ADJFLAG(%a6),%d1 + +#--Step 6 + tst.l %d1 + beq.b NORMAL +ADJUST: + fmul.x ADJSCALE(%a6),%fp0 +NORMAL: + fmov.l %d0,%fpcr # restore user FPCR + mov.b &FMUL_OP,%d1 # last inst is MUL + fmul.x SCALE(%a6),%fp0 # multiply 2^(M) + bra t_catch + +EXPSM: +#--Step 7 + fmovm.x (%a0),&0x80 # load X + fmov.l %d0,%fpcr + fadd.s &0x3F800000,%fp0 # 1+X in user mode + bra t_pinx2 + +EEXPBIG: +#--Step 8 + cmp.l %d1,&0x400CB27C # 16480 log2 + bgt.b EXP2BIG +#--Steps 8.2 -- 8.6 + fmov.x (%a0),%fp0 # load input from (a0) + + fmov.x %fp0,%fp1 + fmul.s &0x42B8AA3B,%fp0 # 64/log2 * X + fmovm.x &0xc,-(%sp) # save fp2 {%fp2/%fp3} + mov.l &1,ADJFLAG(%a6) + fmov.l %fp0,%d1 # N = int( X * 64/log2 ) + lea EEXPTBL(%pc),%a1 + fmov.l %d1,%fp0 # convert to floating-format + mov.l %d1,L_SCR1(%a6) # save N temporarily + and.l &0x3F,%d1 # D0 is J = N mod 64 + lsl.l &4,%d1 + add.l %d1,%a1 # address of 2^(J/64) + mov.l L_SCR1(%a6),%d1 + asr.l &6,%d1 # D0 is K + mov.l %d1,L_SCR1(%a6) # save K temporarily + asr.l &1,%d1 # D0 is M1 + sub.l %d1,L_SCR1(%a6) # a1 is M + add.w &0x3FFF,%d1 # biased expo. of 2^(M1) + mov.w %d1,ADJSCALE(%a6) # ADJSCALE := 2^(M1) + mov.l &0x80000000,ADJSCALE+4(%a6) + clr.l ADJSCALE+8(%a6) + mov.l L_SCR1(%a6),%d1 # D0 is M + add.w &0x3FFF,%d1 # biased expo. of 2^(M) + bra.w EXPCONT1 # go back to Step 3 + +EXP2BIG: +#--Step 9 + tst.b (%a0) # is X positive or negative? + bmi t_unfl2 + bra t_ovfl2 + + global setoxd +setoxd: +#--entry point for EXP(X), X is denormalized + mov.l (%a0),-(%sp) + andi.l &0x80000000,(%sp) + ori.l &0x00800000,(%sp) # sign(X)*2^(-126) + + fmov.s &0x3F800000,%fp0 + + fmov.l %d0,%fpcr + fadd.s (%sp)+,%fp0 + bra t_pinx2 + + global setoxm1 +setoxm1: +#--entry point for EXPM1(X), here X is finite, non-zero, non-NaN + +#--Step 1. +#--Step 1.1 + mov.l (%a0),%d1 # load part of input X + and.l &0x7FFF0000,%d1 # biased expo. of X + cmp.l %d1,&0x3FFD0000 # 1/4 + bge.b EM1CON1 # |X| >= 1/4 + bra EM1SM + +EM1CON1: +#--Step 1.3 +#--The case |X| >= 1/4 + mov.w 4(%a0),%d1 # expo. and partial sig. of |X| + cmp.l %d1,&0x4004C215 # 70log2 rounded up to 16 bits + ble.b EM1MAIN # 1/4 <= |X| <= 70log2 + bra EM1BIG + +EM1MAIN: +#--Step 2. +#--This is the case: 1/4 <= |X| <= 70 log2. + fmov.x (%a0),%fp0 # load input from (a0) + + fmov.x %fp0,%fp1 + fmul.s &0x42B8AA3B,%fp0 # 64/log2 * X + fmovm.x &0xc,-(%sp) # save fp2 {%fp2/%fp3} + fmov.l %fp0,%d1 # N = int( X * 64/log2 ) + lea EEXPTBL(%pc),%a1 + fmov.l %d1,%fp0 # convert to floating-format + + mov.l %d1,L_SCR1(%a6) # save N temporarily + and.l &0x3F,%d1 # D0 is J = N mod 64 + lsl.l &4,%d1 + add.l %d1,%a1 # address of 2^(J/64) + mov.l L_SCR1(%a6),%d1 + asr.l &6,%d1 # D0 is M + mov.l %d1,L_SCR1(%a6) # save a copy of M + +#--Step 3. +#--fp1,fp2 saved on the stack. fp0 is N, fp1 is X, +#--a0 points to 2^(J/64), D0 and a1 both contain M + fmov.x %fp0,%fp2 + fmul.s &0xBC317218,%fp0 # N * L1, L1 = lead(-log2/64) + fmul.x L2(%pc),%fp2 # N * L2, L1+L2 = -log2/64 + fadd.x %fp1,%fp0 # X + N*L1 + fadd.x %fp2,%fp0 # fp0 is R, reduced arg. + add.w &0x3FFF,%d1 # D0 is biased expo. of 2^M + +#--Step 4. +#--WE NOW COMPUTE EXP(R)-1 BY A POLYNOMIAL +#-- R + R*R*(A1 + R*(A2 + R*(A3 + R*(A4 + R*(A5 + R*A6))))) +#--TO FULLY UTILIZE THE PIPELINE, WE COMPUTE S = R*R +#--[R*S*(A2+S*(A4+S*A6))] + [R+S*(A1+S*(A3+S*A5))] + + fmov.x %fp0,%fp1 + fmul.x %fp1,%fp1 # fp1 IS S = R*R + + fmov.s &0x3950097B,%fp2 # fp2 IS a6 + + fmul.x %fp1,%fp2 # fp2 IS S*A6 + fmov.x %fp1,%fp3 + fmul.s &0x3AB60B6A,%fp3 # fp3 IS S*A5 + + fadd.d EM1A4(%pc),%fp2 # fp2 IS A4+S*A6 + fadd.d EM1A3(%pc),%fp3 # fp3 IS A3+S*A5 + mov.w %d1,SC(%a6) # SC is 2^(M) in extended + mov.l &0x80000000,SC+4(%a6) + clr.l SC+8(%a6) + + fmul.x %fp1,%fp2 # fp2 IS S*(A4+S*A6) + mov.l L_SCR1(%a6),%d1 # D0 is M + neg.w %d1 # D0 is -M + fmul.x %fp1,%fp3 # fp3 IS S*(A3+S*A5) + add.w &0x3FFF,%d1 # biased expo. of 2^(-M) + fadd.d EM1A2(%pc),%fp2 # fp2 IS A2+S*(A4+S*A6) + fadd.s &0x3F000000,%fp3 # fp3 IS A1+S*(A3+S*A5) + + fmul.x %fp1,%fp2 # fp2 IS S*(A2+S*(A4+S*A6)) + or.w &0x8000,%d1 # signed/expo. of -2^(-M) + mov.w %d1,ONEBYSC(%a6) # OnebySc is -2^(-M) + mov.l &0x80000000,ONEBYSC+4(%a6) + clr.l ONEBYSC+8(%a6) + fmul.x %fp3,%fp1 # fp1 IS S*(A1+S*(A3+S*A5)) + + fmul.x %fp0,%fp2 # fp2 IS R*S*(A2+S*(A4+S*A6)) + fadd.x %fp1,%fp0 # fp0 IS R+S*(A1+S*(A3+S*A5)) + + fadd.x %fp2,%fp0 # fp0 IS EXP(R)-1 + + fmovm.x (%sp)+,&0x30 # fp2 restored {%fp2/%fp3} + +#--Step 5 +#--Compute 2^(J/64)*p + + fmul.x (%a1),%fp0 # 2^(J/64)*(Exp(R)-1) + +#--Step 6 +#--Step 6.1 + mov.l L_SCR1(%a6),%d1 # retrieve M + cmp.l %d1,&63 + ble.b MLE63 +#--Step 6.2 M >= 64 + fmov.s 12(%a1),%fp1 # fp1 is t + fadd.x ONEBYSC(%a6),%fp1 # fp1 is t+OnebySc + fadd.x %fp1,%fp0 # p+(t+OnebySc), fp1 released + fadd.x (%a1),%fp0 # T+(p+(t+OnebySc)) + bra EM1SCALE +MLE63: +#--Step 6.3 M <= 63 + cmp.l %d1,&-3 + bge.b MGEN3 +MLTN3: +#--Step 6.4 M <= -4 + fadd.s 12(%a1),%fp0 # p+t + fadd.x (%a1),%fp0 # T+(p+t) + fadd.x ONEBYSC(%a6),%fp0 # OnebySc + (T+(p+t)) + bra EM1SCALE +MGEN3: +#--Step 6.5 -3 <= M <= 63 + fmov.x (%a1)+,%fp1 # fp1 is T + fadd.s (%a1),%fp0 # fp0 is p+t + fadd.x ONEBYSC(%a6),%fp1 # fp1 is T+OnebySc + fadd.x %fp1,%fp0 # (T+OnebySc)+(p+t) + +EM1SCALE: +#--Step 6.6 + fmov.l %d0,%fpcr + fmul.x SC(%a6),%fp0 + bra t_inx2 + +EM1SM: +#--Step 7 |X| < 1/4. + cmp.l %d1,&0x3FBE0000 # 2^(-65) + bge.b EM1POLY + +EM1TINY: +#--Step 8 |X| < 2^(-65) + cmp.l %d1,&0x00330000 # 2^(-16312) + blt.b EM12TINY +#--Step 8.2 + mov.l &0x80010000,SC(%a6) # SC is -2^(-16382) + mov.l &0x80000000,SC+4(%a6) + clr.l SC+8(%a6) + fmov.x (%a0),%fp0 + fmov.l %d0,%fpcr + mov.b &FADD_OP,%d1 # last inst is ADD + fadd.x SC(%a6),%fp0 + bra t_catch + +EM12TINY: +#--Step 8.3 + fmov.x (%a0),%fp0 + fmul.d TWO140(%pc),%fp0 + mov.l &0x80010000,SC(%a6) + mov.l &0x80000000,SC+4(%a6) + clr.l SC+8(%a6) + fadd.x SC(%a6),%fp0 + fmov.l %d0,%fpcr + mov.b &FMUL_OP,%d1 # last inst is MUL + fmul.d TWON140(%pc),%fp0 + bra t_catch + +EM1POLY: +#--Step 9 exp(X)-1 by a simple polynomial + fmov.x (%a0),%fp0 # fp0 is X + fmul.x %fp0,%fp0 # fp0 is S := X*X + fmovm.x &0xc,-(%sp) # save fp2 {%fp2/%fp3} + fmov.s &0x2F30CAA8,%fp1 # fp1 is B12 + fmul.x %fp0,%fp1 # fp1 is S*B12 + fmov.s &0x310F8290,%fp2 # fp2 is B11 + fadd.s &0x32D73220,%fp1 # fp1 is B10+S*B12 + + fmul.x %fp0,%fp2 # fp2 is S*B11 + fmul.x %fp0,%fp1 # fp1 is S*(B10 + ... + + fadd.s &0x3493F281,%fp2 # fp2 is B9+S*... + fadd.d EM1B8(%pc),%fp1 # fp1 is B8+S*... + + fmul.x %fp0,%fp2 # fp2 is S*(B9+... + fmul.x %fp0,%fp1 # fp1 is S*(B8+... + + fadd.d EM1B7(%pc),%fp2 # fp2 is B7+S*... + fadd.d EM1B6(%pc),%fp1 # fp1 is B6+S*... + + fmul.x %fp0,%fp2 # fp2 is S*(B7+... + fmul.x %fp0,%fp1 # fp1 is S*(B6+... + + fadd.d EM1B5(%pc),%fp2 # fp2 is B5+S*... + fadd.d EM1B4(%pc),%fp1 # fp1 is B4+S*... + + fmul.x %fp0,%fp2 # fp2 is S*(B5+... + fmul.x %fp0,%fp1 # fp1 is S*(B4+... + + fadd.d EM1B3(%pc),%fp2 # fp2 is B3+S*... + fadd.x EM1B2(%pc),%fp1 # fp1 is B2+S*... + + fmul.x %fp0,%fp2 # fp2 is S*(B3+... + fmul.x %fp0,%fp1 # fp1 is S*(B2+... + + fmul.x %fp0,%fp2 # fp2 is S*S*(B3+...) + fmul.x (%a0),%fp1 # fp1 is X*S*(B2... + + fmul.s &0x3F000000,%fp0 # fp0 is S*B1 + fadd.x %fp2,%fp1 # fp1 is Q + + fmovm.x (%sp)+,&0x30 # fp2 restored {%fp2/%fp3} + + fadd.x %fp1,%fp0 # fp0 is S*B1+Q + + fmov.l %d0,%fpcr + fadd.x (%a0),%fp0 + bra t_inx2 + +EM1BIG: +#--Step 10 |X| > 70 log2 + mov.l (%a0),%d1 + cmp.l %d1,&0 + bgt.w EXPC1 +#--Step 10.2 + fmov.s &0xBF800000,%fp0 # fp0 is -1 + fmov.l %d0,%fpcr + fadd.s &0x00800000,%fp0 # -1 + 2^(-126) + bra t_minx2 + + global setoxm1d +setoxm1d: +#--entry point for EXPM1(X), here X is denormalized +#--Step 0. + bra t_extdnrm + +######################################################################### +# sgetexp(): returns the exponent portion of the input argument. # +# The exponent bias is removed and the exponent value is # +# returned as an extended precision number in fp0. # +# sgetexpd(): handles denormalized numbers. # +# # +# sgetman(): extracts the mantissa of the input argument. The # +# mantissa is converted to an extended precision number w/ # +# an exponent of $3fff and is returned in fp0. The range of # +# the result is [1.0 - 2.0). # +# sgetmand(): handles denormalized numbers. # +# # +# INPUT *************************************************************** # +# a0 = pointer to extended precision input # +# # +# OUTPUT ************************************************************** # +# fp0 = exponent(X) or mantissa(X) # +# # +######################################################################### + + global sgetexp +sgetexp: + mov.w SRC_EX(%a0),%d0 # get the exponent + bclr &0xf,%d0 # clear the sign bit + subi.w &0x3fff,%d0 # subtract off the bias + fmov.w %d0,%fp0 # return exp in fp0 + blt.b sgetexpn # it's negative + rts + +sgetexpn: + mov.b &neg_bmask,FPSR_CC(%a6) # set 'N' ccode bit + rts + + global sgetexpd +sgetexpd: + bsr.l norm # normalize + neg.w %d0 # new exp = -(shft amt) + subi.w &0x3fff,%d0 # subtract off the bias + fmov.w %d0,%fp0 # return exp in fp0 + mov.b &neg_bmask,FPSR_CC(%a6) # set 'N' ccode bit + rts + + global sgetman +sgetman: + mov.w SRC_EX(%a0),%d0 # get the exp + ori.w &0x7fff,%d0 # clear old exp + bclr &0xe,%d0 # make it the new exp +-3fff + +# here, we build the result in a tmp location so as not to disturb the input + mov.l SRC_HI(%a0),FP_SCR0_HI(%a6) # copy to tmp loc + mov.l SRC_LO(%a0),FP_SCR0_LO(%a6) # copy to tmp loc + mov.w %d0,FP_SCR0_EX(%a6) # insert new exponent + fmov.x FP_SCR0(%a6),%fp0 # put new value back in fp0 + bmi.b sgetmann # it's negative + rts + +sgetmann: + mov.b &neg_bmask,FPSR_CC(%a6) # set 'N' ccode bit + rts + +# +# For denormalized numbers, shift the mantissa until the j-bit = 1, +# then load the exponent with +/1 $3fff. +# + global sgetmand +sgetmand: + bsr.l norm # normalize exponent + bra.b sgetman + +######################################################################### +# scosh(): computes the hyperbolic cosine of a normalized input # +# scoshd(): computes the hyperbolic cosine of a denormalized input # +# # +# INPUT *************************************************************** # +# a0 = pointer to extended precision input # +# d0 = round precision,mode # +# # +# OUTPUT ************************************************************** # +# fp0 = cosh(X) # +# # +# ACCURACY and MONOTONICITY ******************************************* # +# The returned result is within 3 ulps in 64 significant bit, # +# i.e. within 0.5001 ulp to 53 bits if the result is subsequently # +# rounded to double precision. The result is provably monotonic # +# in double precision. # +# # +# ALGORITHM *********************************************************** # +# # +# COSH # +# 1. If |X| > 16380 log2, go to 3. # +# # +# 2. (|X| <= 16380 log2) Cosh(X) is obtained by the formulae # +# y = |X|, z = exp(Y), and # +# cosh(X) = (1/2)*( z + 1/z ). # +# Exit. # +# # +# 3. (|X| > 16380 log2). If |X| > 16480 log2, go to 5. # +# # +# 4. (16380 log2 < |X| <= 16480 log2) # +# cosh(X) = sign(X) * exp(|X|)/2. # +# However, invoking exp(|X|) may cause premature # +# overflow. Thus, we calculate sinh(X) as follows: # +# Y := |X| # +# Fact := 2**(16380) # +# Y' := Y - 16381 log2 # +# cosh(X) := Fact * exp(Y'). # +# Exit. # +# # +# 5. (|X| > 16480 log2) sinh(X) must overflow. Return # +# Huge*Huge to generate overflow and an infinity with # +# the appropriate sign. Huge is the largest finite number # +# in extended format. Exit. # +# # +######################################################################### + +TWO16380: + long 0x7FFB0000,0x80000000,0x00000000,0x00000000 + + global scosh +scosh: + fmov.x (%a0),%fp0 # LOAD INPUT + + mov.l (%a0),%d1 + mov.w 4(%a0),%d1 + and.l &0x7FFFFFFF,%d1 + cmp.l %d1,&0x400CB167 + bgt.b COSHBIG + +#--THIS IS THE USUAL CASE, |X| < 16380 LOG2 +#--COSH(X) = (1/2) * ( EXP(X) + 1/EXP(X) ) + + fabs.x %fp0 # |X| + + mov.l %d0,-(%sp) + clr.l %d0 + fmovm.x &0x01,-(%sp) # save |X| to stack + lea (%sp),%a0 # pass ptr to |X| + bsr setox # FP0 IS EXP(|X|) + add.l &0xc,%sp # erase |X| from stack + fmul.s &0x3F000000,%fp0 # (1/2)EXP(|X|) + mov.l (%sp)+,%d0 + + fmov.s &0x3E800000,%fp1 # (1/4) + fdiv.x %fp0,%fp1 # 1/(2 EXP(|X|)) + + fmov.l %d0,%fpcr + mov.b &FADD_OP,%d1 # last inst is ADD + fadd.x %fp1,%fp0 + bra t_catch + +COSHBIG: + cmp.l %d1,&0x400CB2B3 + bgt.b COSHHUGE + + fabs.x %fp0 + fsub.d T1(%pc),%fp0 # (|X|-16381LOG2_LEAD) + fsub.d T2(%pc),%fp0 # |X| - 16381 LOG2, ACCURATE + + mov.l %d0,-(%sp) + clr.l %d0 + fmovm.x &0x01,-(%sp) # save fp0 to stack + lea (%sp),%a0 # pass ptr to fp0 + bsr setox + add.l &0xc,%sp # clear fp0 from stack + mov.l (%sp)+,%d0 + + fmov.l %d0,%fpcr + mov.b &FMUL_OP,%d1 # last inst is MUL + fmul.x TWO16380(%pc),%fp0 + bra t_catch + +COSHHUGE: + bra t_ovfl2 + + global scoshd +#--COSH(X) = 1 FOR DENORMALIZED X +scoshd: + fmov.s &0x3F800000,%fp0 + + fmov.l %d0,%fpcr + fadd.s &0x00800000,%fp0 + bra t_pinx2 + +######################################################################### +# ssinh(): computes the hyperbolic sine of a normalized input # +# ssinhd(): computes the hyperbolic sine of a denormalized input # +# # +# INPUT *************************************************************** # +# a0 = pointer to extended precision input # +# d0 = round precision,mode # +# # +# OUTPUT ************************************************************** # +# fp0 = sinh(X) # +# # +# ACCURACY and MONOTONICITY ******************************************* # +# The returned result is within 3 ulps in 64 significant bit, # +# i.e. within 0.5001 ulp to 53 bits if the result is subsequently # +# rounded to double precision. The result is provably monotonic # +# in double precision. # +# # +# ALGORITHM *********************************************************** # +# # +# SINH # +# 1. If |X| > 16380 log2, go to 3. # +# # +# 2. (|X| <= 16380 log2) Sinh(X) is obtained by the formula # +# y = |X|, sgn = sign(X), and z = expm1(Y), # +# sinh(X) = sgn*(1/2)*( z + z/(1+z) ). # +# Exit. # +# # +# 3. If |X| > 16480 log2, go to 5. # +# # +# 4. (16380 log2 < |X| <= 16480 log2) # +# sinh(X) = sign(X) * exp(|X|)/2. # +# However, invoking exp(|X|) may cause premature overflow. # +# Thus, we calculate sinh(X) as follows: # +# Y := |X| # +# sgn := sign(X) # +# sgnFact := sgn * 2**(16380) # +# Y' := Y - 16381 log2 # +# sinh(X) := sgnFact * exp(Y'). # +# Exit. # +# # +# 5. (|X| > 16480 log2) sinh(X) must overflow. Return # +# sign(X)*Huge*Huge to generate overflow and an infinity with # +# the appropriate sign. Huge is the largest finite number in # +# extended format. Exit. # +# # +######################################################################### + + global ssinh +ssinh: + fmov.x (%a0),%fp0 # LOAD INPUT + + mov.l (%a0),%d1 + mov.w 4(%a0),%d1 + mov.l %d1,%a1 # save (compacted) operand + and.l &0x7FFFFFFF,%d1 + cmp.l %d1,&0x400CB167 + bgt.b SINHBIG + +#--THIS IS THE USUAL CASE, |X| < 16380 LOG2 +#--Y = |X|, Z = EXPM1(Y), SINH(X) = SIGN(X)*(1/2)*( Z + Z/(1+Z) ) + + fabs.x %fp0 # Y = |X| + + movm.l &0x8040,-(%sp) # {a1/d0} + fmovm.x &0x01,-(%sp) # save Y on stack + lea (%sp),%a0 # pass ptr to Y + clr.l %d0 + bsr setoxm1 # FP0 IS Z = EXPM1(Y) + add.l &0xc,%sp # clear Y from stack + fmov.l &0,%fpcr + movm.l (%sp)+,&0x0201 # {a1/d0} + + fmov.x %fp0,%fp1 + fadd.s &0x3F800000,%fp1 # 1+Z + fmov.x %fp0,-(%sp) + fdiv.x %fp1,%fp0 # Z/(1+Z) + mov.l %a1,%d1 + and.l &0x80000000,%d1 + or.l &0x3F000000,%d1 + fadd.x (%sp)+,%fp0 + mov.l %d1,-(%sp) + + fmov.l %d0,%fpcr + mov.b &FMUL_OP,%d1 # last inst is MUL + fmul.s (%sp)+,%fp0 # last fp inst - possible exceptions set + bra t_catch + +SINHBIG: + cmp.l %d1,&0x400CB2B3 + bgt t_ovfl + fabs.x %fp0 + fsub.d T1(%pc),%fp0 # (|X|-16381LOG2_LEAD) + mov.l &0,-(%sp) + mov.l &0x80000000,-(%sp) + mov.l %a1,%d1 + and.l &0x80000000,%d1 + or.l &0x7FFB0000,%d1 + mov.l %d1,-(%sp) # EXTENDED FMT + fsub.d T2(%pc),%fp0 # |X| - 16381 LOG2, ACCURATE + + mov.l %d0,-(%sp) + clr.l %d0 + fmovm.x &0x01,-(%sp) # save fp0 on stack + lea (%sp),%a0 # pass ptr to fp0 + bsr setox + add.l &0xc,%sp # clear fp0 from stack + + mov.l (%sp)+,%d0 + fmov.l %d0,%fpcr + mov.b &FMUL_OP,%d1 # last inst is MUL + fmul.x (%sp)+,%fp0 # possible exception + bra t_catch + + global ssinhd +#--SINH(X) = X FOR DENORMALIZED X +ssinhd: + bra t_extdnrm + +######################################################################### +# stanh(): computes the hyperbolic tangent of a normalized input # +# stanhd(): computes the hyperbolic tangent of a denormalized input # +# # +# INPUT *************************************************************** # +# a0 = pointer to extended precision input # +# d0 = round precision,mode # +# # +# OUTPUT ************************************************************** # +# fp0 = tanh(X) # +# # +# ACCURACY and MONOTONICITY ******************************************* # +# The returned result is within 3 ulps in 64 significant bit, # +# i.e. within 0.5001 ulp to 53 bits if the result is subsequently # +# rounded to double precision. The result is provably monotonic # +# in double precision. # +# # +# ALGORITHM *********************************************************** # +# # +# TANH # +# 1. If |X| >= (5/2) log2 or |X| <= 2**(-40), go to 3. # +# # +# 2. (2**(-40) < |X| < (5/2) log2) Calculate tanh(X) by # +# sgn := sign(X), y := 2|X|, z := expm1(Y), and # +# tanh(X) = sgn*( z/(2+z) ). # +# Exit. # +# # +# 3. (|X| <= 2**(-40) or |X| >= (5/2) log2). If |X| < 1, # +# go to 7. # +# # +# 4. (|X| >= (5/2) log2) If |X| >= 50 log2, go to 6. # +# # +# 5. ((5/2) log2 <= |X| < 50 log2) Calculate tanh(X) by # +# sgn := sign(X), y := 2|X|, z := exp(Y), # +# tanh(X) = sgn - [ sgn*2/(1+z) ]. # +# Exit. # +# # +# 6. (|X| >= 50 log2) Tanh(X) = +-1 (round to nearest). Thus, we # +# calculate Tanh(X) by # +# sgn := sign(X), Tiny := 2**(-126), # +# tanh(X) := sgn - sgn*Tiny. # +# Exit. # +# # +# 7. (|X| < 2**(-40)). Tanh(X) = X. Exit. # +# # +######################################################################### + + set X,FP_SCR0 + set XFRAC,X+4 + + set SGN,L_SCR3 + + set V,FP_SCR0 + + global stanh +stanh: + fmov.x (%a0),%fp0 # LOAD INPUT + + fmov.x %fp0,X(%a6) + mov.l (%a0),%d1 + mov.w 4(%a0),%d1 + mov.l %d1,X(%a6) + and.l &0x7FFFFFFF,%d1 + cmp.l %d1, &0x3fd78000 # is |X| < 2^(-40)? + blt.w TANHBORS # yes + cmp.l %d1, &0x3fffddce # is |X| > (5/2)LOG2? + bgt.w TANHBORS # yes + +#--THIS IS THE USUAL CASE +#--Y = 2|X|, Z = EXPM1(Y), TANH(X) = SIGN(X) * Z / (Z+2). + + mov.l X(%a6),%d1 + mov.l %d1,SGN(%a6) + and.l &0x7FFF0000,%d1 + add.l &0x00010000,%d1 # EXPONENT OF 2|X| + mov.l %d1,X(%a6) + and.l &0x80000000,SGN(%a6) + fmov.x X(%a6),%fp0 # FP0 IS Y = 2|X| + + mov.l %d0,-(%sp) + clr.l %d0 + fmovm.x &0x1,-(%sp) # save Y on stack + lea (%sp),%a0 # pass ptr to Y + bsr setoxm1 # FP0 IS Z = EXPM1(Y) + add.l &0xc,%sp # clear Y from stack + mov.l (%sp)+,%d0 + + fmov.x %fp0,%fp1 + fadd.s &0x40000000,%fp1 # Z+2 + mov.l SGN(%a6),%d1 + fmov.x %fp1,V(%a6) + eor.l %d1,V(%a6) + + fmov.l %d0,%fpcr # restore users round prec,mode + fdiv.x V(%a6),%fp0 + bra t_inx2 + +TANHBORS: + cmp.l %d1,&0x3FFF8000 + blt.w TANHSM + + cmp.l %d1,&0x40048AA1 + bgt.w TANHHUGE + +#-- (5/2) LOG2 < |X| < 50 LOG2, +#--TANH(X) = 1 - (2/[EXP(2X)+1]). LET Y = 2|X|, SGN = SIGN(X), +#--TANH(X) = SGN - SGN*2/[EXP(Y)+1]. + + mov.l X(%a6),%d1 + mov.l %d1,SGN(%a6) + and.l &0x7FFF0000,%d1 + add.l &0x00010000,%d1 # EXPO OF 2|X| + mov.l %d1,X(%a6) # Y = 2|X| + and.l &0x80000000,SGN(%a6) + mov.l SGN(%a6),%d1 + fmov.x X(%a6),%fp0 # Y = 2|X| + + mov.l %d0,-(%sp) + clr.l %d0 + fmovm.x &0x01,-(%sp) # save Y on stack + lea (%sp),%a0 # pass ptr to Y + bsr setox # FP0 IS EXP(Y) + add.l &0xc,%sp # clear Y from stack + mov.l (%sp)+,%d0 + mov.l SGN(%a6),%d1 + fadd.s &0x3F800000,%fp0 # EXP(Y)+1 + + eor.l &0xC0000000,%d1 # -SIGN(X)*2 + fmov.s %d1,%fp1 # -SIGN(X)*2 IN SGL FMT + fdiv.x %fp0,%fp1 # -SIGN(X)2 / [EXP(Y)+1 ] + + mov.l SGN(%a6),%d1 + or.l &0x3F800000,%d1 # SGN + fmov.s %d1,%fp0 # SGN IN SGL FMT + + fmov.l %d0,%fpcr # restore users round prec,mode + mov.b &FADD_OP,%d1 # last inst is ADD + fadd.x %fp1,%fp0 + bra t_inx2 + +TANHSM: + fmov.l %d0,%fpcr # restore users round prec,mode + mov.b &FMOV_OP,%d1 # last inst is MOVE + fmov.x X(%a6),%fp0 # last inst - possible exception set + bra t_catch + +#---RETURN SGN(X) - SGN(X)EPS +TANHHUGE: + mov.l X(%a6),%d1 + and.l &0x80000000,%d1 + or.l &0x3F800000,%d1 + fmov.s %d1,%fp0 + and.l &0x80000000,%d1 + eor.l &0x80800000,%d1 # -SIGN(X)*EPS + + fmov.l %d0,%fpcr # restore users round prec,mode + fadd.s %d1,%fp0 + bra t_inx2 + + global stanhd +#--TANH(X) = X FOR DENORMALIZED X +stanhd: + bra t_extdnrm + +######################################################################### +# slogn(): computes the natural logarithm of a normalized input # +# slognd(): computes the natural logarithm of a denormalized input # +# slognp1(): computes the log(1+X) of a normalized input # +# slognp1d(): computes the log(1+X) of a denormalized input # +# # +# INPUT *************************************************************** # +# a0 = pointer to extended precision input # +# d0 = round precision,mode # +# # +# OUTPUT ************************************************************** # +# fp0 = log(X) or log(1+X) # +# # +# ACCURACY and MONOTONICITY ******************************************* # +# The returned result is within 2 ulps in 64 significant bit, # +# i.e. within 0.5001 ulp to 53 bits if the result is subsequently # +# rounded to double precision. The result is provably monotonic # +# in double precision. # +# # +# ALGORITHM *********************************************************** # +# LOGN: # +# Step 1. If |X-1| < 1/16, approximate log(X) by an odd # +# polynomial in u, where u = 2(X-1)/(X+1). Otherwise, # +# move on to Step 2. # +# # +# Step 2. X = 2**k * Y where 1 <= Y < 2. Define F to be the first # +# seven significant bits of Y plus 2**(-7), i.e. # +# F = 1.xxxxxx1 in base 2 where the six "x" match those # +# of Y. Note that |Y-F| <= 2**(-7). # +# # +# Step 3. Define u = (Y-F)/F. Approximate log(1+u) by a # +# polynomial in u, log(1+u) = poly. # +# # +# Step 4. Reconstruct # +# log(X) = log( 2**k * Y ) = k*log(2) + log(F) + log(1+u) # +# by k*log(2) + (log(F) + poly). The values of log(F) are # +# calculated beforehand and stored in the program. # +# # +# lognp1: # +# Step 1: If |X| < 1/16, approximate log(1+X) by an odd # +# polynomial in u where u = 2X/(2+X). Otherwise, move on # +# to Step 2. # +# # +# Step 2: Let 1+X = 2**k * Y, where 1 <= Y < 2. Define F as done # +# in Step 2 of the algorithm for LOGN and compute # +# log(1+X) as k*log(2) + log(F) + poly where poly # +# approximates log(1+u), u = (Y-F)/F. # +# # +# Implementation Notes: # +# Note 1. There are 64 different possible values for F, thus 64 # +# log(F)'s need to be tabulated. Moreover, the values of # +# 1/F are also tabulated so that the division in (Y-F)/F # +# can be performed by a multiplication. # +# # +# Note 2. In Step 2 of lognp1, in order to preserved accuracy, # +# the value Y-F has to be calculated carefully when # +# 1/2 <= X < 3/2. # +# # +# Note 3. To fully exploit the pipeline, polynomials are usually # +# separated into two parts evaluated independently before # +# being added up. # +# # +######################################################################### +LOGOF2: + long 0x3FFE0000,0xB17217F7,0xD1CF79AC,0x00000000 + +one: + long 0x3F800000 +zero: + long 0x00000000 +infty: + long 0x7F800000 +negone: + long 0xBF800000 + +LOGA6: + long 0x3FC2499A,0xB5E4040B +LOGA5: + long 0xBFC555B5,0x848CB7DB + +LOGA4: + long 0x3FC99999,0x987D8730 +LOGA3: + long 0xBFCFFFFF,0xFF6F7E97 + +LOGA2: + long 0x3FD55555,0x555555A4 +LOGA1: + long 0xBFE00000,0x00000008 + +LOGB5: + long 0x3F175496,0xADD7DAD6 +LOGB4: + long 0x3F3C71C2,0xFE80C7E0 + +LOGB3: + long 0x3F624924,0x928BCCFF +LOGB2: + long 0x3F899999,0x999995EC + +LOGB1: + long 0x3FB55555,0x55555555 +TWO: + long 0x40000000,0x00000000 + +LTHOLD: + long 0x3f990000,0x80000000,0x00000000,0x00000000 + +LOGTBL: + long 0x3FFE0000,0xFE03F80F,0xE03F80FE,0x00000000 + long 0x3FF70000,0xFF015358,0x833C47E2,0x00000000 + long 0x3FFE0000,0xFA232CF2,0x52138AC0,0x00000000 + long 0x3FF90000,0xBDC8D83E,0xAD88D549,0x00000000 + long 0x3FFE0000,0xF6603D98,0x0F6603DA,0x00000000 + long 0x3FFA0000,0x9CF43DCF,0xF5EAFD48,0x00000000 + long 0x3FFE0000,0xF2B9D648,0x0F2B9D65,0x00000000 + long 0x3FFA0000,0xDA16EB88,0xCB8DF614,0x00000000 + long 0x3FFE0000,0xEF2EB71F,0xC4345238,0x00000000 + long 0x3FFB0000,0x8B29B775,0x1BD70743,0x00000000 + long 0x3FFE0000,0xEBBDB2A5,0xC1619C8C,0x00000000 + long 0x3FFB0000,0xA8D839F8,0x30C1FB49,0x00000000 + long 0x3FFE0000,0xE865AC7B,0x7603A197,0x00000000 + long 0x3FFB0000,0xC61A2EB1,0x8CD907AD,0x00000000 + long 0x3FFE0000,0xE525982A,0xF70C880E,0x00000000 + long 0x3FFB0000,0xE2F2A47A,0xDE3A18AF,0x00000000 + long 0x3FFE0000,0xE1FC780E,0x1FC780E2,0x00000000 + long 0x3FFB0000,0xFF64898E,0xDF55D551,0x00000000 + long 0x3FFE0000,0xDEE95C4C,0xA037BA57,0x00000000 + long 0x3FFC0000,0x8DB956A9,0x7B3D0148,0x00000000 + long 0x3FFE0000,0xDBEB61EE,0xD19C5958,0x00000000 + long 0x3FFC0000,0x9B8FE100,0xF47BA1DE,0x00000000 + long 0x3FFE0000,0xD901B203,0x6406C80E,0x00000000 + long 0x3FFC0000,0xA9372F1D,0x0DA1BD17,0x00000000 + long 0x3FFE0000,0xD62B80D6,0x2B80D62C,0x00000000 + long 0x3FFC0000,0xB6B07F38,0xCE90E46B,0x00000000 + long 0x3FFE0000,0xD3680D36,0x80D3680D,0x00000000 + long 0x3FFC0000,0xC3FD0329,0x06488481,0x00000000 + long 0x3FFE0000,0xD0B69FCB,0xD2580D0B,0x00000000 + long 0x3FFC0000,0xD11DE0FF,0x15AB18CA,0x00000000 + long 0x3FFE0000,0xCE168A77,0x25080CE1,0x00000000 + long 0x3FFC0000,0xDE1433A1,0x6C66B150,0x00000000 + long 0x3FFE0000,0xCB8727C0,0x65C393E0,0x00000000 + long 0x3FFC0000,0xEAE10B5A,0x7DDC8ADD,0x00000000 + long 0x3FFE0000,0xC907DA4E,0x871146AD,0x00000000 + long 0x3FFC0000,0xF7856E5E,0xE2C9B291,0x00000000 + long 0x3FFE0000,0xC6980C69,0x80C6980C,0x00000000 + long 0x3FFD0000,0x82012CA5,0xA68206D7,0x00000000 + long 0x3FFE0000,0xC4372F85,0x5D824CA6,0x00000000 + long 0x3FFD0000,0x882C5FCD,0x7256A8C5,0x00000000 + long 0x3FFE0000,0xC1E4BBD5,0x95F6E947,0x00000000 + long 0x3FFD0000,0x8E44C60B,0x4CCFD7DE,0x00000000 + long 0x3FFE0000,0xBFA02FE8,0x0BFA02FF,0x00000000 + long 0x3FFD0000,0x944AD09E,0xF4351AF6,0x00000000 + long 0x3FFE0000,0xBD691047,0x07661AA3,0x00000000 + long 0x3FFD0000,0x9A3EECD4,0xC3EAA6B2,0x00000000 + long 0x3FFE0000,0xBB3EE721,0xA54D880C,0x00000000 + long 0x3FFD0000,0xA0218434,0x353F1DE8,0x00000000 + long 0x3FFE0000,0xB92143FA,0x36F5E02E,0x00000000 + long 0x3FFD0000,0xA5F2FCAB,0xBBC506DA,0x00000000 + long 0x3FFE0000,0xB70FBB5A,0x19BE3659,0x00000000 + long 0x3FFD0000,0xABB3B8BA,0x2AD362A5,0x00000000 + long 0x3FFE0000,0xB509E68A,0x9B94821F,0x00000000 + long 0x3FFD0000,0xB1641795,0xCE3CA97B,0x00000000 + long 0x3FFE0000,0xB30F6352,0x8917C80B,0x00000000 + long 0x3FFD0000,0xB7047551,0x5D0F1C61,0x00000000 + long 0x3FFE0000,0xB11FD3B8,0x0B11FD3C,0x00000000 + long 0x3FFD0000,0xBC952AFE,0xEA3D13E1,0x00000000 + long 0x3FFE0000,0xAF3ADDC6,0x80AF3ADE,0x00000000 + long 0x3FFD0000,0xC2168ED0,0xF458BA4A,0x00000000 + long 0x3FFE0000,0xAD602B58,0x0AD602B6,0x00000000 + long 0x3FFD0000,0xC788F439,0xB3163BF1,0x00000000 + long 0x3FFE0000,0xAB8F69E2,0x8359CD11,0x00000000 + long 0x3FFD0000,0xCCECAC08,0xBF04565D,0x00000000 + long 0x3FFE0000,0xA9C84A47,0xA07F5638,0x00000000 + long 0x3FFD0000,0xD2420487,0x2DD85160,0x00000000 + long 0x3FFE0000,0xA80A80A8,0x0A80A80B,0x00000000 + long 0x3FFD0000,0xD7894992,0x3BC3588A,0x00000000 + long 0x3FFE0000,0xA655C439,0x2D7B73A8,0x00000000 + long 0x3FFD0000,0xDCC2C4B4,0x9887DACC,0x00000000 + long 0x3FFE0000,0xA4A9CF1D,0x96833751,0x00000000 + long 0x3FFD0000,0xE1EEBD3E,0x6D6A6B9E,0x00000000 + long 0x3FFE0000,0xA3065E3F,0xAE7CD0E0,0x00000000 + long 0x3FFD0000,0xE70D785C,0x2F9F5BDC,0x00000000 + long 0x3FFE0000,0xA16B312E,0xA8FC377D,0x00000000 + long 0x3FFD0000,0xEC1F392C,0x5179F283,0x00000000 + long 0x3FFE0000,0x9FD809FD,0x809FD80A,0x00000000 + long 0x3FFD0000,0xF12440D3,0xE36130E6,0x00000000 + long 0x3FFE0000,0x9E4CAD23,0xDD5F3A20,0x00000000 + long 0x3FFD0000,0xF61CCE92,0x346600BB,0x00000000 + long 0x3FFE0000,0x9CC8E160,0xC3FB19B9,0x00000000 + long 0x3FFD0000,0xFB091FD3,0x8145630A,0x00000000 + long 0x3FFE0000,0x9B4C6F9E,0xF03A3CAA,0x00000000 + long 0x3FFD0000,0xFFE97042,0xBFA4C2AD,0x00000000 + long 0x3FFE0000,0x99D722DA,0xBDE58F06,0x00000000 + long 0x3FFE0000,0x825EFCED,0x49369330,0x00000000 + long 0x3FFE0000,0x9868C809,0x868C8098,0x00000000 + long 0x3FFE0000,0x84C37A7A,0xB9A905C9,0x00000000 + long 0x3FFE0000,0x97012E02,0x5C04B809,0x00000000 + long 0x3FFE0000,0x87224C2E,0x8E645FB7,0x00000000 + long 0x3FFE0000,0x95A02568,0x095A0257,0x00000000 + long 0x3FFE0000,0x897B8CAC,0x9F7DE298,0x00000000 + long 0x3FFE0000,0x94458094,0x45809446,0x00000000 + long 0x3FFE0000,0x8BCF55DE,0xC4CD05FE,0x00000000 + long 0x3FFE0000,0x92F11384,0x0497889C,0x00000000 + long 0x3FFE0000,0x8E1DC0FB,0x89E125E5,0x00000000 + long 0x3FFE0000,0x91A2B3C4,0xD5E6F809,0x00000000 + long 0x3FFE0000,0x9066E68C,0x955B6C9B,0x00000000 + long 0x3FFE0000,0x905A3863,0x3E06C43B,0x00000000 + long 0x3FFE0000,0x92AADE74,0xC7BE59E0,0x00000000 + long 0x3FFE0000,0x8F1779D9,0xFDC3A219,0x00000000 + long 0x3FFE0000,0x94E9BFF6,0x15845643,0x00000000 + long 0x3FFE0000,0x8DDA5202,0x37694809,0x00000000 + long 0x3FFE0000,0x9723A1B7,0x20134203,0x00000000 + long 0x3FFE0000,0x8CA29C04,0x6514E023,0x00000000 + long 0x3FFE0000,0x995899C8,0x90EB8990,0x00000000 + long 0x3FFE0000,0x8B70344A,0x139BC75A,0x00000000 + long 0x3FFE0000,0x9B88BDAA,0x3A3DAE2F,0x00000000 + long 0x3FFE0000,0x8A42F870,0x5669DB46,0x00000000 + long 0x3FFE0000,0x9DB4224F,0xFFE1157C,0x00000000 + long 0x3FFE0000,0x891AC73A,0xE9819B50,0x00000000 + long 0x3FFE0000,0x9FDADC26,0x8B7A12DA,0x00000000 + long 0x3FFE0000,0x87F78087,0xF78087F8,0x00000000 + long 0x3FFE0000,0xA1FCFF17,0xCE733BD4,0x00000000 + long 0x3FFE0000,0x86D90544,0x7A34ACC6,0x00000000 + long 0x3FFE0000,0xA41A9E8F,0x5446FB9F,0x00000000 + long 0x3FFE0000,0x85BF3761,0x2CEE3C9B,0x00000000 + long 0x3FFE0000,0xA633CD7E,0x6771CD8B,0x00000000 + long 0x3FFE0000,0x84A9F9C8,0x084A9F9D,0x00000000 + long 0x3FFE0000,0xA8489E60,0x0B435A5E,0x00000000 + long 0x3FFE0000,0x83993052,0x3FBE3368,0x00000000 + long 0x3FFE0000,0xAA59233C,0xCCA4BD49,0x00000000 + long 0x3FFE0000,0x828CBFBE,0xB9A020A3,0x00000000 + long 0x3FFE0000,0xAC656DAE,0x6BCC4985,0x00000000 + long 0x3FFE0000,0x81848DA8,0xFAF0D277,0x00000000 + long 0x3FFE0000,0xAE6D8EE3,0x60BB2468,0x00000000 + long 0x3FFE0000,0x80808080,0x80808081,0x00000000 + long 0x3FFE0000,0xB07197A2,0x3C46C654,0x00000000 + + set ADJK,L_SCR1 + + set X,FP_SCR0 + set XDCARE,X+2 + set XFRAC,X+4 + + set F,FP_SCR1 + set FFRAC,F+4 + + set KLOG2,FP_SCR0 + + set SAVEU,FP_SCR0 + + global slogn +#--ENTRY POINT FOR LOG(X) FOR X FINITE, NON-ZERO, NOT NAN'S +slogn: + fmov.x (%a0),%fp0 # LOAD INPUT + mov.l &0x00000000,ADJK(%a6) + +LOGBGN: +#--FPCR SAVED AND CLEARED, INPUT IS 2^(ADJK)*FP0, FP0 CONTAINS +#--A FINITE, NON-ZERO, NORMALIZED NUMBER. + + mov.l (%a0),%d1 + mov.w 4(%a0),%d1 + + mov.l (%a0),X(%a6) + mov.l 4(%a0),X+4(%a6) + mov.l 8(%a0),X+8(%a6) + + cmp.l %d1,&0 # CHECK IF X IS NEGATIVE + blt.w LOGNEG # LOG OF NEGATIVE ARGUMENT IS INVALID +# X IS POSITIVE, CHECK IF X IS NEAR 1 + cmp.l %d1,&0x3ffef07d # IS X < 15/16? + blt.b LOGMAIN # YES + cmp.l %d1,&0x3fff8841 # IS X > 17/16? + ble.w LOGNEAR1 # NO + +LOGMAIN: +#--THIS SHOULD BE THE USUAL CASE, X NOT VERY CLOSE TO 1 + +#--X = 2^(K) * Y, 1 <= Y < 2. THUS, Y = 1.XXXXXXXX....XX IN BINARY. +#--WE DEFINE F = 1.XXXXXX1, I.E. FIRST 7 BITS OF Y AND ATTACH A 1. +#--THE IDEA IS THAT LOG(X) = K*LOG2 + LOG(Y) +#-- = K*LOG2 + LOG(F) + LOG(1 + (Y-F)/F). +#--NOTE THAT U = (Y-F)/F IS VERY SMALL AND THUS APPROXIMATING +#--LOG(1+U) CAN BE VERY EFFICIENT. +#--ALSO NOTE THAT THE VALUE 1/F IS STORED IN A TABLE SO THAT NO +#--DIVISION IS NEEDED TO CALCULATE (Y-F)/F. + +#--GET K, Y, F, AND ADDRESS OF 1/F. + asr.l &8,%d1 + asr.l &8,%d1 # SHIFTED 16 BITS, BIASED EXPO. OF X + sub.l &0x3FFF,%d1 # THIS IS K + add.l ADJK(%a6),%d1 # ADJUST K, ORIGINAL INPUT MAY BE DENORM. + lea LOGTBL(%pc),%a0 # BASE ADDRESS OF 1/F AND LOG(F) + fmov.l %d1,%fp1 # CONVERT K TO FLOATING-POINT FORMAT + +#--WHILE THE CONVERSION IS GOING ON, WE GET F AND ADDRESS OF 1/F + mov.l &0x3FFF0000,X(%a6) # X IS NOW Y, I.E. 2^(-K)*X + mov.l XFRAC(%a6),FFRAC(%a6) + and.l &0xFE000000,FFRAC(%a6) # FIRST 7 BITS OF Y + or.l &0x01000000,FFRAC(%a6) # GET F: ATTACH A 1 AT THE EIGHTH BIT + mov.l FFRAC(%a6),%d1 # READY TO GET ADDRESS OF 1/F + and.l &0x7E000000,%d1 + asr.l &8,%d1 + asr.l &8,%d1 + asr.l &4,%d1 # SHIFTED 20, D0 IS THE DISPLACEMENT + add.l %d1,%a0 # A0 IS THE ADDRESS FOR 1/F + + fmov.x X(%a6),%fp0 + mov.l &0x3fff0000,F(%a6) + clr.l F+8(%a6) + fsub.x F(%a6),%fp0 # Y-F + fmovm.x &0xc,-(%sp) # SAVE FP2-3 WHILE FP0 IS NOT READY +#--SUMMARY: FP0 IS Y-F, A0 IS ADDRESS OF 1/F, FP1 IS K +#--REGISTERS SAVED: FPCR, FP1, FP2 + +LP1CONT1: +#--AN RE-ENTRY POINT FOR LOGNP1 + fmul.x (%a0),%fp0 # FP0 IS U = (Y-F)/F + fmul.x LOGOF2(%pc),%fp1 # GET K*LOG2 WHILE FP0 IS NOT READY + fmov.x %fp0,%fp2 + fmul.x %fp2,%fp2 # FP2 IS V=U*U + fmov.x %fp1,KLOG2(%a6) # PUT K*LOG2 IN MEMEORY, FREE FP1 + +#--LOG(1+U) IS APPROXIMATED BY +#--U + V*(A1+U*(A2+U*(A3+U*(A4+U*(A5+U*A6))))) WHICH IS +#--[U + V*(A1+V*(A3+V*A5))] + [U*V*(A2+V*(A4+V*A6))] + + fmov.x %fp2,%fp3 + fmov.x %fp2,%fp1 + + fmul.d LOGA6(%pc),%fp1 # V*A6 + fmul.d LOGA5(%pc),%fp2 # V*A5 + + fadd.d LOGA4(%pc),%fp1 # A4+V*A6 + fadd.d LOGA3(%pc),%fp2 # A3+V*A5 + + fmul.x %fp3,%fp1 # V*(A4+V*A6) + fmul.x %fp3,%fp2 # V*(A3+V*A5) + + fadd.d LOGA2(%pc),%fp1 # A2+V*(A4+V*A6) + fadd.d LOGA1(%pc),%fp2 # A1+V*(A3+V*A5) + + fmul.x %fp3,%fp1 # V*(A2+V*(A4+V*A6)) + add.l &16,%a0 # ADDRESS OF LOG(F) + fmul.x %fp3,%fp2 # V*(A1+V*(A3+V*A5)) + + fmul.x %fp0,%fp1 # U*V*(A2+V*(A4+V*A6)) + fadd.x %fp2,%fp0 # U+V*(A1+V*(A3+V*A5)) + + fadd.x (%a0),%fp1 # LOG(F)+U*V*(A2+V*(A4+V*A6)) + fmovm.x (%sp)+,&0x30 # RESTORE FP2-3 + fadd.x %fp1,%fp0 # FP0 IS LOG(F) + LOG(1+U) + + fmov.l %d0,%fpcr + fadd.x KLOG2(%a6),%fp0 # FINAL ADD + bra t_inx2 + + +LOGNEAR1: + +# if the input is exactly equal to one, then exit through ld_pzero. +# if these 2 lines weren't here, the correct answer would be returned +# but the INEX2 bit would be set. + fcmp.b %fp0,&0x1 # is it equal to one? + fbeq.l ld_pzero # yes + +#--REGISTERS SAVED: FPCR, FP1. FP0 CONTAINS THE INPUT. + fmov.x %fp0,%fp1 + fsub.s one(%pc),%fp1 # FP1 IS X-1 + fadd.s one(%pc),%fp0 # FP0 IS X+1 + fadd.x %fp1,%fp1 # FP1 IS 2(X-1) +#--LOG(X) = LOG(1+U/2)-LOG(1-U/2) WHICH IS AN ODD POLYNOMIAL +#--IN U, U = 2(X-1)/(X+1) = FP1/FP0 + +LP1CONT2: +#--THIS IS AN RE-ENTRY POINT FOR LOGNP1 + fdiv.x %fp0,%fp1 # FP1 IS U + fmovm.x &0xc,-(%sp) # SAVE FP2-3 +#--REGISTERS SAVED ARE NOW FPCR,FP1,FP2,FP3 +#--LET V=U*U, W=V*V, CALCULATE +#--U + U*V*(B1 + V*(B2 + V*(B3 + V*(B4 + V*B5)))) BY +#--U + U*V*( [B1 + W*(B3 + W*B5)] + [V*(B2 + W*B4)] ) + fmov.x %fp1,%fp0 + fmul.x %fp0,%fp0 # FP0 IS V + fmov.x %fp1,SAVEU(%a6) # STORE U IN MEMORY, FREE FP1 + fmov.x %fp0,%fp1 + fmul.x %fp1,%fp1 # FP1 IS W + + fmov.d LOGB5(%pc),%fp3 + fmov.d LOGB4(%pc),%fp2 + + fmul.x %fp1,%fp3 # W*B5 + fmul.x %fp1,%fp2 # W*B4 + + fadd.d LOGB3(%pc),%fp3 # B3+W*B5 + fadd.d LOGB2(%pc),%fp2 # B2+W*B4 + + fmul.x %fp3,%fp1 # W*(B3+W*B5), FP3 RELEASED + + fmul.x %fp0,%fp2 # V*(B2+W*B4) + + fadd.d LOGB1(%pc),%fp1 # B1+W*(B3+W*B5) + fmul.x SAVEU(%a6),%fp0 # FP0 IS U*V + + fadd.x %fp2,%fp1 # B1+W*(B3+W*B5) + V*(B2+W*B4), FP2 RELEASED + fmovm.x (%sp)+,&0x30 # FP2-3 RESTORED + + fmul.x %fp1,%fp0 # U*V*( [B1+W*(B3+W*B5)] + [V*(B2+W*B4)] ) + + fmov.l %d0,%fpcr + fadd.x SAVEU(%a6),%fp0 + bra t_inx2 + +#--REGISTERS SAVED FPCR. LOG(-VE) IS INVALID +LOGNEG: + bra t_operr + + global slognd +slognd: +#--ENTRY POINT FOR LOG(X) FOR DENORMALIZED INPUT + + mov.l &-100,ADJK(%a6) # INPUT = 2^(ADJK) * FP0 + +#----normalize the input value by left shifting k bits (k to be determined +#----below), adjusting exponent and storing -k to ADJK +#----the value TWOTO100 is no longer needed. +#----Note that this code assumes the denormalized input is NON-ZERO. + + movm.l &0x3f00,-(%sp) # save some registers {d2-d7} + mov.l (%a0),%d3 # D3 is exponent of smallest norm. # + mov.l 4(%a0),%d4 + mov.l 8(%a0),%d5 # (D4,D5) is (Hi_X,Lo_X) + clr.l %d2 # D2 used for holding K + + tst.l %d4 + bne.b Hi_not0 + +Hi_0: + mov.l %d5,%d4 + clr.l %d5 + mov.l &32,%d2 + clr.l %d6 + bfffo %d4{&0:&32},%d6 + lsl.l %d6,%d4 + add.l %d6,%d2 # (D3,D4,D5) is normalized + + mov.l %d3,X(%a6) + mov.l %d4,XFRAC(%a6) + mov.l %d5,XFRAC+4(%a6) + neg.l %d2 + mov.l %d2,ADJK(%a6) + fmov.x X(%a6),%fp0 + movm.l (%sp)+,&0xfc # restore registers {d2-d7} + lea X(%a6),%a0 + bra.w LOGBGN # begin regular log(X) + +Hi_not0: + clr.l %d6 + bfffo %d4{&0:&32},%d6 # find first 1 + mov.l %d6,%d2 # get k + lsl.l %d6,%d4 + mov.l %d5,%d7 # a copy of D5 + lsl.l %d6,%d5 + neg.l %d6 + add.l &32,%d6 + lsr.l %d6,%d7 + or.l %d7,%d4 # (D3,D4,D5) normalized + + mov.l %d3,X(%a6) + mov.l %d4,XFRAC(%a6) + mov.l %d5,XFRAC+4(%a6) + neg.l %d2 + mov.l %d2,ADJK(%a6) + fmov.x X(%a6),%fp0 + movm.l (%sp)+,&0xfc # restore registers {d2-d7} + lea X(%a6),%a0 + bra.w LOGBGN # begin regular log(X) + + global slognp1 +#--ENTRY POINT FOR LOG(1+X) FOR X FINITE, NON-ZERO, NOT NAN'S +slognp1: + fmov.x (%a0),%fp0 # LOAD INPUT + fabs.x %fp0 # test magnitude + fcmp.x %fp0,LTHOLD(%pc) # compare with min threshold + fbgt.w LP1REAL # if greater, continue + fmov.l %d0,%fpcr + mov.b &FMOV_OP,%d1 # last inst is MOVE + fmov.x (%a0),%fp0 # return signed argument + bra t_catch + +LP1REAL: + fmov.x (%a0),%fp0 # LOAD INPUT + mov.l &0x00000000,ADJK(%a6) + fmov.x %fp0,%fp1 # FP1 IS INPUT Z + fadd.s one(%pc),%fp0 # X := ROUND(1+Z) + fmov.x %fp0,X(%a6) + mov.w XFRAC(%a6),XDCARE(%a6) + mov.l X(%a6),%d1 + cmp.l %d1,&0 + ble.w LP1NEG0 # LOG OF ZERO OR -VE + cmp.l %d1,&0x3ffe8000 # IS BOUNDS [1/2,3/2]? + blt.w LOGMAIN + cmp.l %d1,&0x3fffc000 + bgt.w LOGMAIN +#--IF 1+Z > 3/2 OR 1+Z < 1/2, THEN X, WHICH IS ROUNDING 1+Z, +#--CONTAINS AT LEAST 63 BITS OF INFORMATION OF Z. IN THAT CASE, +#--SIMPLY INVOKE LOG(X) FOR LOG(1+Z). + +LP1NEAR1: +#--NEXT SEE IF EXP(-1/16) < X < EXP(1/16) + cmp.l %d1,&0x3ffef07d + blt.w LP1CARE + cmp.l %d1,&0x3fff8841 + bgt.w LP1CARE + +LP1ONE16: +#--EXP(-1/16) < X < EXP(1/16). LOG(1+Z) = LOG(1+U/2) - LOG(1-U/2) +#--WHERE U = 2Z/(2+Z) = 2Z/(1+X). + fadd.x %fp1,%fp1 # FP1 IS 2Z + fadd.s one(%pc),%fp0 # FP0 IS 1+X +#--U = FP1/FP0 + bra.w LP1CONT2 + +LP1CARE: +#--HERE WE USE THE USUAL TABLE DRIVEN APPROACH. CARE HAS TO BE +#--TAKEN BECAUSE 1+Z CAN HAVE 67 BITS OF INFORMATION AND WE MUST +#--PRESERVE ALL THE INFORMATION. BECAUSE 1+Z IS IN [1/2,3/2], +#--THERE ARE ONLY TWO CASES. +#--CASE 1: 1+Z < 1, THEN K = -1 AND Y-F = (2-F) + 2Z +#--CASE 2: 1+Z > 1, THEN K = 0 AND Y-F = (1-F) + Z +#--ON RETURNING TO LP1CONT1, WE MUST HAVE K IN FP1, ADDRESS OF +#--(1/F) IN A0, Y-F IN FP0, AND FP2 SAVED. + + mov.l XFRAC(%a6),FFRAC(%a6) + and.l &0xFE000000,FFRAC(%a6) + or.l &0x01000000,FFRAC(%a6) # F OBTAINED + cmp.l %d1,&0x3FFF8000 # SEE IF 1+Z > 1 + bge.b KISZERO + +KISNEG1: + fmov.s TWO(%pc),%fp0 + mov.l &0x3fff0000,F(%a6) + clr.l F+8(%a6) + fsub.x F(%a6),%fp0 # 2-F + mov.l FFRAC(%a6),%d1 + and.l &0x7E000000,%d1 + asr.l &8,%d1 + asr.l &8,%d1 + asr.l &4,%d1 # D0 CONTAINS DISPLACEMENT FOR 1/F + fadd.x %fp1,%fp1 # GET 2Z + fmovm.x &0xc,-(%sp) # SAVE FP2 {%fp2/%fp3} + fadd.x %fp1,%fp0 # FP0 IS Y-F = (2-F)+2Z + lea LOGTBL(%pc),%a0 # A0 IS ADDRESS OF 1/F + add.l %d1,%a0 + fmov.s negone(%pc),%fp1 # FP1 IS K = -1 + bra.w LP1CONT1 + +KISZERO: + fmov.s one(%pc),%fp0 + mov.l &0x3fff0000,F(%a6) + clr.l F+8(%a6) + fsub.x F(%a6),%fp0 # 1-F + mov.l FFRAC(%a6),%d1 + and.l &0x7E000000,%d1 + asr.l &8,%d1 + asr.l &8,%d1 + asr.l &4,%d1 + fadd.x %fp1,%fp0 # FP0 IS Y-F + fmovm.x &0xc,-(%sp) # FP2 SAVED {%fp2/%fp3} + lea LOGTBL(%pc),%a0 + add.l %d1,%a0 # A0 IS ADDRESS OF 1/F + fmov.s zero(%pc),%fp1 # FP1 IS K = 0 + bra.w LP1CONT1 + +LP1NEG0: +#--FPCR SAVED. D0 IS X IN COMPACT FORM. + cmp.l %d1,&0 + blt.b LP1NEG +LP1ZERO: + fmov.s negone(%pc),%fp0 + + fmov.l %d0,%fpcr + bra t_dz + +LP1NEG: + fmov.s zero(%pc),%fp0 + + fmov.l %d0,%fpcr + bra t_operr + + global slognp1d +#--ENTRY POINT FOR LOG(1+Z) FOR DENORMALIZED INPUT +# Simply return the denorm +slognp1d: + bra t_extdnrm + +######################################################################### +# satanh(): computes the inverse hyperbolic tangent of a norm input # +# satanhd(): computes the inverse hyperbolic tangent of a denorm input # +# # +# INPUT *************************************************************** # +# a0 = pointer to extended precision input # +# d0 = round precision,mode # +# # +# OUTPUT ************************************************************** # +# fp0 = arctanh(X) # +# # +# ACCURACY and MONOTONICITY ******************************************* # +# The returned result is within 3 ulps in 64 significant bit, # +# i.e. within 0.5001 ulp to 53 bits if the result is subsequently # +# rounded to double precision. The result is provably monotonic # +# in double precision. # +# # +# ALGORITHM *********************************************************** # +# # +# ATANH # +# 1. If |X| >= 1, go to 3. # +# # +# 2. (|X| < 1) Calculate atanh(X) by # +# sgn := sign(X) # +# y := |X| # +# z := 2y/(1-y) # +# atanh(X) := sgn * (1/2) * logp1(z) # +# Exit. # +# # +# 3. If |X| > 1, go to 5. # +# # +# 4. (|X| = 1) Generate infinity with an appropriate sign and # +# divide-by-zero by # +# sgn := sign(X) # +# atan(X) := sgn / (+0). # +# Exit. # +# # +# 5. (|X| > 1) Generate an invalid operation by 0 * infinity. # +# Exit. # +# # +######################################################################### + + global satanh +satanh: + mov.l (%a0),%d1 + mov.w 4(%a0),%d1 + and.l &0x7FFFFFFF,%d1 + cmp.l %d1,&0x3FFF8000 + bge.b ATANHBIG + +#--THIS IS THE USUAL CASE, |X| < 1 +#--Y = |X|, Z = 2Y/(1-Y), ATANH(X) = SIGN(X) * (1/2) * LOG1P(Z). + + fabs.x (%a0),%fp0 # Y = |X| + fmov.x %fp0,%fp1 + fneg.x %fp1 # -Y + fadd.x %fp0,%fp0 # 2Y + fadd.s &0x3F800000,%fp1 # 1-Y + fdiv.x %fp1,%fp0 # 2Y/(1-Y) + mov.l (%a0),%d1 + and.l &0x80000000,%d1 + or.l &0x3F000000,%d1 # SIGN(X)*HALF + mov.l %d1,-(%sp) + + mov.l %d0,-(%sp) # save rnd prec,mode + clr.l %d0 # pass ext prec,RN + fmovm.x &0x01,-(%sp) # save Z on stack + lea (%sp),%a0 # pass ptr to Z + bsr slognp1 # LOG1P(Z) + add.l &0xc,%sp # clear Z from stack + + mov.l (%sp)+,%d0 # fetch old prec,mode + fmov.l %d0,%fpcr # load it + mov.b &FMUL_OP,%d1 # last inst is MUL + fmul.s (%sp)+,%fp0 + bra t_catch + +ATANHBIG: + fabs.x (%a0),%fp0 # |X| + fcmp.s %fp0,&0x3F800000 + fbgt t_operr + bra t_dz + + global satanhd +#--ATANH(X) = X FOR DENORMALIZED X +satanhd: + bra t_extdnrm + +######################################################################### +# slog10(): computes the base-10 logarithm of a normalized input # +# slog10d(): computes the base-10 logarithm of a denormalized input # +# slog2(): computes the base-2 logarithm of a normalized input # +# slog2d(): computes the base-2 logarithm of a denormalized input # +# # +# INPUT *************************************************************** # +# a0 = pointer to extended precision input # +# d0 = round precision,mode # +# # +# OUTPUT ************************************************************** # +# fp0 = log_10(X) or log_2(X) # +# # +# ACCURACY and MONOTONICITY ******************************************* # +# The returned result is within 1.7 ulps in 64 significant bit, # +# i.e. within 0.5003 ulp to 53 bits if the result is subsequently # +# rounded to double precision. The result is provably monotonic # +# in double precision. # +# # +# ALGORITHM *********************************************************** # +# # +# slog10d: # +# # +# Step 0. If X < 0, create a NaN and raise the invalid operation # +# flag. Otherwise, save FPCR in D1; set FpCR to default. # +# Notes: Default means round-to-nearest mode, no floating-point # +# traps, and precision control = double extended. # +# # +# Step 1. Call slognd to obtain Y = log(X), the natural log of X. # +# Notes: Even if X is denormalized, log(X) is always normalized. # +# # +# Step 2. Compute log_10(X) = log(X) * (1/log(10)). # +# 2.1 Restore the user FPCR # +# 2.2 Return ans := Y * INV_L10. # +# # +# slog10: # +# # +# Step 0. If X < 0, create a NaN and raise the invalid operation # +# flag. Otherwise, save FPCR in D1; set FpCR to default. # +# Notes: Default means round-to-nearest mode, no floating-point # +# traps, and precision control = double extended. # +# # +# Step 1. Call sLogN to obtain Y = log(X), the natural log of X. # +# # +# Step 2. Compute log_10(X) = log(X) * (1/log(10)). # +# 2.1 Restore the user FPCR # +# 2.2 Return ans := Y * INV_L10. # +# # +# sLog2d: # +# # +# Step 0. If X < 0, create a NaN and raise the invalid operation # +# flag. Otherwise, save FPCR in D1; set FpCR to default. # +# Notes: Default means round-to-nearest mode, no floating-point # +# traps, and precision control = double extended. # +# # +# Step 1. Call slognd to obtain Y = log(X), the natural log of X. # +# Notes: Even if X is denormalized, log(X) is always normalized. # +# # +# Step 2. Compute log_10(X) = log(X) * (1/log(2)). # +# 2.1 Restore the user FPCR # +# 2.2 Return ans := Y * INV_L2. # +# # +# sLog2: # +# # +# Step 0. If X < 0, create a NaN and raise the invalid operation # +# flag. Otherwise, save FPCR in D1; set FpCR to default. # +# Notes: Default means round-to-nearest mode, no floating-point # +# traps, and precision control = double extended. # +# # +# Step 1. If X is not an integer power of two, i.e., X != 2^k, # +# go to Step 3. # +# # +# Step 2. Return k. # +# 2.1 Get integer k, X = 2^k. # +# 2.2 Restore the user FPCR. # +# 2.3 Return ans := convert-to-double-extended(k). # +# # +# Step 3. Call sLogN to obtain Y = log(X), the natural log of X. # +# # +# Step 4. Compute log_2(X) = log(X) * (1/log(2)). # +# 4.1 Restore the user FPCR # +# 4.2 Return ans := Y * INV_L2. # +# # +######################################################################### + +INV_L10: + long 0x3FFD0000,0xDE5BD8A9,0x37287195,0x00000000 + +INV_L2: + long 0x3FFF0000,0xB8AA3B29,0x5C17F0BC,0x00000000 + + global slog10 +#--entry point for Log10(X), X is normalized +slog10: + fmov.b &0x1,%fp0 + fcmp.x %fp0,(%a0) # if operand == 1, + fbeq.l ld_pzero # return an EXACT zero + + mov.l (%a0),%d1 + blt.w invalid + mov.l %d0,-(%sp) + clr.l %d0 + bsr slogn # log(X), X normal. + fmov.l (%sp)+,%fpcr + fmul.x INV_L10(%pc),%fp0 + bra t_inx2 + + global slog10d +#--entry point for Log10(X), X is denormalized +slog10d: + mov.l (%a0),%d1 + blt.w invalid + mov.l %d0,-(%sp) + clr.l %d0 + bsr slognd # log(X), X denorm. + fmov.l (%sp)+,%fpcr + fmul.x INV_L10(%pc),%fp0 + bra t_minx2 + + global slog2 +#--entry point for Log2(X), X is normalized +slog2: + mov.l (%a0),%d1 + blt.w invalid + + mov.l 8(%a0),%d1 + bne.b continue # X is not 2^k + + mov.l 4(%a0),%d1 + and.l &0x7FFFFFFF,%d1 + bne.b continue + +#--X = 2^k. + mov.w (%a0),%d1 + and.l &0x00007FFF,%d1 + sub.l &0x3FFF,%d1 + beq.l ld_pzero + fmov.l %d0,%fpcr + fmov.l %d1,%fp0 + bra t_inx2 + +continue: + mov.l %d0,-(%sp) + clr.l %d0 + bsr slogn # log(X), X normal. + fmov.l (%sp)+,%fpcr + fmul.x INV_L2(%pc),%fp0 + bra t_inx2 + +invalid: + bra t_operr + + global slog2d +#--entry point for Log2(X), X is denormalized +slog2d: + mov.l (%a0),%d1 + blt.w invalid + mov.l %d0,-(%sp) + clr.l %d0 + bsr slognd # log(X), X denorm. + fmov.l (%sp)+,%fpcr + fmul.x INV_L2(%pc),%fp0 + bra t_minx2 + +######################################################################### +# stwotox(): computes 2**X for a normalized input # +# stwotoxd(): computes 2**X for a denormalized input # +# stentox(): computes 10**X for a normalized input # +# stentoxd(): computes 10**X for a denormalized input # +# # +# INPUT *************************************************************** # +# a0 = pointer to extended precision input # +# d0 = round precision,mode # +# # +# OUTPUT ************************************************************** # +# fp0 = 2**X or 10**X # +# # +# ACCURACY and MONOTONICITY ******************************************* # +# The returned result is within 2 ulps in 64 significant bit, # +# i.e. within 0.5001 ulp to 53 bits if the result is subsequently # +# rounded to double precision. The result is provably monotonic # +# in double precision. # +# # +# ALGORITHM *********************************************************** # +# # +# twotox # +# 1. If |X| > 16480, go to ExpBig. # +# # +# 2. If |X| < 2**(-70), go to ExpSm. # +# # +# 3. Decompose X as X = N/64 + r where |r| <= 1/128. Furthermore # +# decompose N as # +# N = 64(M + M') + j, j = 0,1,2,...,63. # +# # +# 4. Overwrite r := r * log2. Then # +# 2**X = 2**(M') * 2**(M) * 2**(j/64) * exp(r). # +# Go to expr to compute that expression. # +# # +# tentox # +# 1. If |X| > 16480*log_10(2) (base 10 log of 2), go to ExpBig. # +# # +# 2. If |X| < 2**(-70), go to ExpSm. # +# # +# 3. Set y := X*log_2(10)*64 (base 2 log of 10). Set # +# N := round-to-int(y). Decompose N as # +# N = 64(M + M') + j, j = 0,1,2,...,63. # +# # +# 4. Define r as # +# r := ((X - N*L1)-N*L2) * L10 # +# where L1, L2 are the leading and trailing parts of # +# log_10(2)/64 and L10 is the natural log of 10. Then # +# 10**X = 2**(M') * 2**(M) * 2**(j/64) * exp(r). # +# Go to expr to compute that expression. # +# # +# expr # +# 1. Fetch 2**(j/64) from table as Fact1 and Fact2. # +# # +# 2. Overwrite Fact1 and Fact2 by # +# Fact1 := 2**(M) * Fact1 # +# Fact2 := 2**(M) * Fact2 # +# Thus Fact1 + Fact2 = 2**(M) * 2**(j/64). # +# # +# 3. Calculate P where 1 + P approximates exp(r): # +# P = r + r*r*(A1+r*(A2+...+r*A5)). # +# # +# 4. Let AdjFact := 2**(M'). Return # +# AdjFact * ( Fact1 + ((Fact1*P) + Fact2) ). # +# Exit. # +# # +# ExpBig # +# 1. Generate overflow by Huge * Huge if X > 0; otherwise, # +# generate underflow by Tiny * Tiny. # +# # +# ExpSm # +# 1. Return 1 + X. # +# # +######################################################################### + +L2TEN64: + long 0x406A934F,0x0979A371 # 64LOG10/LOG2 +L10TWO1: + long 0x3F734413,0x509F8000 # LOG2/64LOG10 + +L10TWO2: + long 0xBFCD0000,0xC0219DC1,0xDA994FD2,0x00000000 + +LOG10: long 0x40000000,0x935D8DDD,0xAAA8AC17,0x00000000 + +LOG2: long 0x3FFE0000,0xB17217F7,0xD1CF79AC,0x00000000 + +EXPA5: long 0x3F56C16D,0x6F7BD0B2 +EXPA4: long 0x3F811112,0x302C712C +EXPA3: long 0x3FA55555,0x55554CC1 +EXPA2: long 0x3FC55555,0x55554A54 +EXPA1: long 0x3FE00000,0x00000000,0x00000000,0x00000000 + +TEXPTBL: + long 0x3FFF0000,0x80000000,0x00000000,0x3F738000 + long 0x3FFF0000,0x8164D1F3,0xBC030773,0x3FBEF7CA + long 0x3FFF0000,0x82CD8698,0xAC2BA1D7,0x3FBDF8A9 + long 0x3FFF0000,0x843A28C3,0xACDE4046,0x3FBCD7C9 + long 0x3FFF0000,0x85AAC367,0xCC487B15,0xBFBDE8DA + long 0x3FFF0000,0x871F6196,0x9E8D1010,0x3FBDE85C + long 0x3FFF0000,0x88980E80,0x92DA8527,0x3FBEBBF1 + long 0x3FFF0000,0x8A14D575,0x496EFD9A,0x3FBB80CA + long 0x3FFF0000,0x8B95C1E3,0xEA8BD6E7,0xBFBA8373 + long 0x3FFF0000,0x8D1ADF5B,0x7E5BA9E6,0xBFBE9670 + long 0x3FFF0000,0x8EA4398B,0x45CD53C0,0x3FBDB700 + long 0x3FFF0000,0x9031DC43,0x1466B1DC,0x3FBEEEB0 + long 0x3FFF0000,0x91C3D373,0xAB11C336,0x3FBBFD6D + long 0x3FFF0000,0x935A2B2F,0x13E6E92C,0xBFBDB319 + long 0x3FFF0000,0x94F4EFA8,0xFEF70961,0x3FBDBA2B + long 0x3FFF0000,0x96942D37,0x20185A00,0x3FBE91D5 + long 0x3FFF0000,0x9837F051,0x8DB8A96F,0x3FBE8D5A + long 0x3FFF0000,0x99E04593,0x20B7FA65,0xBFBCDE7B + long 0x3FFF0000,0x9B8D39B9,0xD54E5539,0xBFBEBAAF + long 0x3FFF0000,0x9D3ED9A7,0x2CFFB751,0xBFBD86DA + long 0x3FFF0000,0x9EF53260,0x91A111AE,0xBFBEBEDD + long 0x3FFF0000,0xA0B0510F,0xB9714FC2,0x3FBCC96E + long 0x3FFF0000,0xA2704303,0x0C496819,0xBFBEC90B + long 0x3FFF0000,0xA43515AE,0x09E6809E,0x3FBBD1DB + long 0x3FFF0000,0xA5FED6A9,0xB15138EA,0x3FBCE5EB + long 0x3FFF0000,0xA7CD93B4,0xE965356A,0xBFBEC274 + long 0x3FFF0000,0xA9A15AB4,0xEA7C0EF8,0x3FBEA83C + long 0x3FFF0000,0xAB7A39B5,0xA93ED337,0x3FBECB00 + long 0x3FFF0000,0xAD583EEA,0x42A14AC6,0x3FBE9301 + long 0x3FFF0000,0xAF3B78AD,0x690A4375,0xBFBD8367 + long 0x3FFF0000,0xB123F581,0xD2AC2590,0xBFBEF05F + long 0x3FFF0000,0xB311C412,0xA9112489,0x3FBDFB3C + long 0x3FFF0000,0xB504F333,0xF9DE6484,0x3FBEB2FB + long 0x3FFF0000,0xB6FD91E3,0x28D17791,0x3FBAE2CB + long 0x3FFF0000,0xB8FBAF47,0x62FB9EE9,0x3FBCDC3C + long 0x3FFF0000,0xBAFF5AB2,0x133E45FB,0x3FBEE9AA + long 0x3FFF0000,0xBD08A39F,0x580C36BF,0xBFBEAEFD + long 0x3FFF0000,0xBF1799B6,0x7A731083,0xBFBCBF51 + long 0x3FFF0000,0xC12C4CCA,0x66709456,0x3FBEF88A + long 0x3FFF0000,0xC346CCDA,0x24976407,0x3FBD83B2 + long 0x3FFF0000,0xC5672A11,0x5506DADD,0x3FBDF8AB + long 0x3FFF0000,0xC78D74C8,0xABB9B15D,0xBFBDFB17 + long 0x3FFF0000,0xC9B9BD86,0x6E2F27A3,0xBFBEFE3C + long 0x3FFF0000,0xCBEC14FE,0xF2727C5D,0xBFBBB6F8 + long 0x3FFF0000,0xCE248C15,0x1F8480E4,0xBFBCEE53 + long 0x3FFF0000,0xD06333DA,0xEF2B2595,0xBFBDA4AE + long 0x3FFF0000,0xD2A81D91,0xF12AE45A,0x3FBC9124 + long 0x3FFF0000,0xD4F35AAB,0xCFEDFA1F,0x3FBEB243 + long 0x3FFF0000,0xD744FCCA,0xD69D6AF4,0x3FBDE69A + long 0x3FFF0000,0xD99D15C2,0x78AFD7B6,0xBFB8BC61 + long 0x3FFF0000,0xDBFBB797,0xDAF23755,0x3FBDF610 + long 0x3FFF0000,0xDE60F482,0x5E0E9124,0xBFBD8BE1 + long 0x3FFF0000,0xE0CCDEEC,0x2A94E111,0x3FBACB12 + long 0x3FFF0000,0xE33F8972,0xBE8A5A51,0x3FBB9BFE + long 0x3FFF0000,0xE5B906E7,0x7C8348A8,0x3FBCF2F4 + long 0x3FFF0000,0xE8396A50,0x3C4BDC68,0x3FBEF22F + long 0x3FFF0000,0xEAC0C6E7,0xDD24392F,0xBFBDBF4A + long 0x3FFF0000,0xED4F301E,0xD9942B84,0x3FBEC01A + long 0x3FFF0000,0xEFE4B99B,0xDCDAF5CB,0x3FBE8CAC + long 0x3FFF0000,0xF281773C,0x59FFB13A,0xBFBCBB3F + long 0x3FFF0000,0xF5257D15,0x2486CC2C,0x3FBEF73A + long 0x3FFF0000,0xF7D0DF73,0x0AD13BB9,0xBFB8B795 + long 0x3FFF0000,0xFA83B2DB,0x722A033A,0x3FBEF84B + long 0x3FFF0000,0xFD3E0C0C,0xF486C175,0xBFBEF581 + + set INT,L_SCR1 + + set X,FP_SCR0 + set XDCARE,X+2 + set XFRAC,X+4 + + set ADJFACT,FP_SCR0 + + set FACT1,FP_SCR0 + set FACT1HI,FACT1+4 + set FACT1LOW,FACT1+8 + + set FACT2,FP_SCR1 + set FACT2HI,FACT2+4 + set FACT2LOW,FACT2+8 + + global stwotox +#--ENTRY POINT FOR 2**(X), HERE X IS FINITE, NON-ZERO, AND NOT NAN'S +stwotox: + fmovm.x (%a0),&0x80 # LOAD INPUT + + mov.l (%a0),%d1 + mov.w 4(%a0),%d1 + fmov.x %fp0,X(%a6) + and.l &0x7FFFFFFF,%d1 + + cmp.l %d1,&0x3FB98000 # |X| >= 2**(-70)? + bge.b TWOOK1 + bra.w EXPBORS + +TWOOK1: + cmp.l %d1,&0x400D80C0 # |X| > 16480? + ble.b TWOMAIN + bra.w EXPBORS + +TWOMAIN: +#--USUAL CASE, 2^(-70) <= |X| <= 16480 + + fmov.x %fp0,%fp1 + fmul.s &0x42800000,%fp1 # 64 * X + fmov.l %fp1,INT(%a6) # N = ROUND-TO-INT(64 X) + mov.l %d2,-(%sp) + lea TEXPTBL(%pc),%a1 # LOAD ADDRESS OF TABLE OF 2^(J/64) + fmov.l INT(%a6),%fp1 # N --> FLOATING FMT + mov.l INT(%a6),%d1 + mov.l %d1,%d2 + and.l &0x3F,%d1 # D0 IS J + asl.l &4,%d1 # DISPLACEMENT FOR 2^(J/64) + add.l %d1,%a1 # ADDRESS FOR 2^(J/64) + asr.l &6,%d2 # d2 IS L, N = 64L + J + mov.l %d2,%d1 + asr.l &1,%d1 # D0 IS M + sub.l %d1,%d2 # d2 IS M', N = 64(M+M') + J + add.l &0x3FFF,%d2 + +#--SUMMARY: a1 IS ADDRESS FOR THE LEADING PORTION OF 2^(J/64), +#--D0 IS M WHERE N = 64(M+M') + J. NOTE THAT |M| <= 16140 BY DESIGN. +#--ADJFACT = 2^(M'). +#--REGISTERS SAVED SO FAR ARE (IN ORDER) FPCR, D0, FP1, a1, AND FP2. + + fmovm.x &0x0c,-(%sp) # save fp2/fp3 + + fmul.s &0x3C800000,%fp1 # (1/64)*N + mov.l (%a1)+,FACT1(%a6) + mov.l (%a1)+,FACT1HI(%a6) + mov.l (%a1)+,FACT1LOW(%a6) + mov.w (%a1)+,FACT2(%a6) + + fsub.x %fp1,%fp0 # X - (1/64)*INT(64 X) + + mov.w (%a1)+,FACT2HI(%a6) + clr.w FACT2HI+2(%a6) + clr.l FACT2LOW(%a6) + add.w %d1,FACT1(%a6) + fmul.x LOG2(%pc),%fp0 # FP0 IS R + add.w %d1,FACT2(%a6) + + bra.w expr + +EXPBORS: +#--FPCR, D0 SAVED + cmp.l %d1,&0x3FFF8000 + bgt.b TEXPBIG + +#--|X| IS SMALL, RETURN 1 + X + + fmov.l %d0,%fpcr # restore users round prec,mode + fadd.s &0x3F800000,%fp0 # RETURN 1 + X + bra t_pinx2 + +TEXPBIG: +#--|X| IS LARGE, GENERATE OVERFLOW IF X > 0; ELSE GENERATE UNDERFLOW +#--REGISTERS SAVE SO FAR ARE FPCR AND D0 + mov.l X(%a6),%d1 + cmp.l %d1,&0 + blt.b EXPNEG + + bra t_ovfl2 # t_ovfl expects positive value + +EXPNEG: + bra t_unfl2 # t_unfl expects positive value + + global stwotoxd +stwotoxd: +#--ENTRY POINT FOR 2**(X) FOR DENORMALIZED ARGUMENT + + fmov.l %d0,%fpcr # set user's rounding mode/precision + fmov.s &0x3F800000,%fp0 # RETURN 1 + X + mov.l (%a0),%d1 + or.l &0x00800001,%d1 + fadd.s %d1,%fp0 + bra t_pinx2 + + global stentox +#--ENTRY POINT FOR 10**(X), HERE X IS FINITE, NON-ZERO, AND NOT NAN'S +stentox: + fmovm.x (%a0),&0x80 # LOAD INPUT + + mov.l (%a0),%d1 + mov.w 4(%a0),%d1 + fmov.x %fp0,X(%a6) + and.l &0x7FFFFFFF,%d1 + + cmp.l %d1,&0x3FB98000 # |X| >= 2**(-70)? + bge.b TENOK1 + bra.w EXPBORS + +TENOK1: + cmp.l %d1,&0x400B9B07 # |X| <= 16480*log2/log10 ? + ble.b TENMAIN + bra.w EXPBORS + +TENMAIN: +#--USUAL CASE, 2^(-70) <= |X| <= 16480 LOG 2 / LOG 10 + + fmov.x %fp0,%fp1 + fmul.d L2TEN64(%pc),%fp1 # X*64*LOG10/LOG2 + fmov.l %fp1,INT(%a6) # N=INT(X*64*LOG10/LOG2) + mov.l %d2,-(%sp) + lea TEXPTBL(%pc),%a1 # LOAD ADDRESS OF TABLE OF 2^(J/64) + fmov.l INT(%a6),%fp1 # N --> FLOATING FMT + mov.l INT(%a6),%d1 + mov.l %d1,%d2 + and.l &0x3F,%d1 # D0 IS J + asl.l &4,%d1 # DISPLACEMENT FOR 2^(J/64) + add.l %d1,%a1 # ADDRESS FOR 2^(J/64) + asr.l &6,%d2 # d2 IS L, N = 64L + J + mov.l %d2,%d1 + asr.l &1,%d1 # D0 IS M + sub.l %d1,%d2 # d2 IS M', N = 64(M+M') + J + add.l &0x3FFF,%d2 + +#--SUMMARY: a1 IS ADDRESS FOR THE LEADING PORTION OF 2^(J/64), +#--D0 IS M WHERE N = 64(M+M') + J. NOTE THAT |M| <= 16140 BY DESIGN. +#--ADJFACT = 2^(M'). +#--REGISTERS SAVED SO FAR ARE (IN ORDER) FPCR, D0, FP1, a1, AND FP2. + fmovm.x &0x0c,-(%sp) # save fp2/fp3 + + fmov.x %fp1,%fp2 + + fmul.d L10TWO1(%pc),%fp1 # N*(LOG2/64LOG10)_LEAD + mov.l (%a1)+,FACT1(%a6) + + fmul.x L10TWO2(%pc),%fp2 # N*(LOG2/64LOG10)_TRAIL + + mov.l (%a1)+,FACT1HI(%a6) + mov.l (%a1)+,FACT1LOW(%a6) + fsub.x %fp1,%fp0 # X - N L_LEAD + mov.w (%a1)+,FACT2(%a6) + + fsub.x %fp2,%fp0 # X - N L_TRAIL + + mov.w (%a1)+,FACT2HI(%a6) + clr.w FACT2HI+2(%a6) + clr.l FACT2LOW(%a6) + + fmul.x LOG10(%pc),%fp0 # FP0 IS R + add.w %d1,FACT1(%a6) + add.w %d1,FACT2(%a6) + +expr: +#--FPCR, FP2, FP3 ARE SAVED IN ORDER AS SHOWN. +#--ADJFACT CONTAINS 2**(M'), FACT1 + FACT2 = 2**(M) * 2**(J/64). +#--FP0 IS R. THE FOLLOWING CODE COMPUTES +#-- 2**(M'+M) * 2**(J/64) * EXP(R) + + fmov.x %fp0,%fp1 + fmul.x %fp1,%fp1 # FP1 IS S = R*R + + fmov.d EXPA5(%pc),%fp2 # FP2 IS A5 + fmov.d EXPA4(%pc),%fp3 # FP3 IS A4 + + fmul.x %fp1,%fp2 # FP2 IS S*A5 + fmul.x %fp1,%fp3 # FP3 IS S*A4 + + fadd.d EXPA3(%pc),%fp2 # FP2 IS A3+S*A5 + fadd.d EXPA2(%pc),%fp3 # FP3 IS A2+S*A4 + + fmul.x %fp1,%fp2 # FP2 IS S*(A3+S*A5) + fmul.x %fp1,%fp3 # FP3 IS S*(A2+S*A4) + + fadd.d EXPA1(%pc),%fp2 # FP2 IS A1+S*(A3+S*A5) + fmul.x %fp0,%fp3 # FP3 IS R*S*(A2+S*A4) + + fmul.x %fp1,%fp2 # FP2 IS S*(A1+S*(A3+S*A5)) + fadd.x %fp3,%fp0 # FP0 IS R+R*S*(A2+S*A4) + fadd.x %fp2,%fp0 # FP0 IS EXP(R) - 1 + + fmovm.x (%sp)+,&0x30 # restore fp2/fp3 + +#--FINAL RECONSTRUCTION PROCESS +#--EXP(X) = 2^M*2^(J/64) + 2^M*2^(J/64)*(EXP(R)-1) - (1 OR 0) + + fmul.x FACT1(%a6),%fp0 + fadd.x FACT2(%a6),%fp0 + fadd.x FACT1(%a6),%fp0 + + fmov.l %d0,%fpcr # restore users round prec,mode + mov.w %d2,ADJFACT(%a6) # INSERT EXPONENT + mov.l (%sp)+,%d2 + mov.l &0x80000000,ADJFACT+4(%a6) + clr.l ADJFACT+8(%a6) + mov.b &FMUL_OP,%d1 # last inst is MUL + fmul.x ADJFACT(%a6),%fp0 # FINAL ADJUSTMENT + bra t_catch + + global stentoxd +stentoxd: +#--ENTRY POINT FOR 10**(X) FOR DENORMALIZED ARGUMENT + + fmov.l %d0,%fpcr # set user's rounding mode/precision + fmov.s &0x3F800000,%fp0 # RETURN 1 + X + mov.l (%a0),%d1 + or.l &0x00800001,%d1 + fadd.s %d1,%fp0 + bra t_pinx2 + +######################################################################### +# sscale(): computes the destination operand scaled by the source # +# operand. If the absoulute value of the source operand is # +# >= 2^14, an overflow or underflow is returned. # +# # +# INPUT *************************************************************** # +# a0 = pointer to double-extended source operand X # +# a1 = pointer to double-extended destination operand Y # +# # +# OUTPUT ************************************************************** # +# fp0 = scale(X,Y) # +# # +######################################################################### + +set SIGN, L_SCR1 + + global sscale +sscale: + mov.l %d0,-(%sp) # store off ctrl bits for now + + mov.w DST_EX(%a1),%d1 # get dst exponent + smi.b SIGN(%a6) # use SIGN to hold dst sign + andi.l &0x00007fff,%d1 # strip sign from dst exp + + mov.w SRC_EX(%a0),%d0 # check src bounds + andi.w &0x7fff,%d0 # clr src sign bit + cmpi.w %d0,&0x3fff # is src ~ ZERO? + blt.w src_small # yes + cmpi.w %d0,&0x400c # no; is src too big? + bgt.w src_out # yes + +# +# Source is within 2^14 range. +# +src_ok: + fintrz.x SRC(%a0),%fp0 # calc int of src + fmov.l %fp0,%d0 # int src to d0 +# don't want any accrued bits from the fintrz showing up later since +# we may need to read the fpsr for the last fp op in t_catch2(). + fmov.l &0x0,%fpsr + + tst.b DST_HI(%a1) # is dst denormalized? + bmi.b sok_norm + +# the dst is a DENORM. normalize the DENORM and add the adjustment to +# the src value. then, jump to the norm part of the routine. +sok_dnrm: + mov.l %d0,-(%sp) # save src for now + + mov.w DST_EX(%a1),FP_SCR0_EX(%a6) # make a copy + mov.l DST_HI(%a1),FP_SCR0_HI(%a6) + mov.l DST_LO(%a1),FP_SCR0_LO(%a6) + + lea FP_SCR0(%a6),%a0 # pass ptr to DENORM + bsr.l norm # normalize the DENORM + neg.l %d0 + add.l (%sp)+,%d0 # add adjustment to src + + fmovm.x FP_SCR0(%a6),&0x80 # load normalized DENORM + + cmpi.w %d0,&-0x3fff # is the shft amt really low? + bge.b sok_norm2 # thank goodness no + +# the multiply factor that we're trying to create should be a denorm +# for the multiply to work. therefore, we're going to actually do a +# multiply with a denorm which will cause an unimplemented data type +# exception to be put into the machine which will be caught and corrected +# later. we don't do this with the DENORMs above because this method +# is slower. but, don't fret, I don't see it being used much either. + fmov.l (%sp)+,%fpcr # restore user fpcr + mov.l &0x80000000,%d1 # load normalized mantissa + subi.l &-0x3fff,%d0 # how many should we shift? + neg.l %d0 # make it positive + cmpi.b %d0,&0x20 # is it > 32? + bge.b sok_dnrm_32 # yes + lsr.l %d0,%d1 # no; bit stays in upper lw + clr.l -(%sp) # insert zero low mantissa + mov.l %d1,-(%sp) # insert new high mantissa + clr.l -(%sp) # make zero exponent + bra.b sok_norm_cont +sok_dnrm_32: + subi.b &0x20,%d0 # get shift count + lsr.l %d0,%d1 # make low mantissa longword + mov.l %d1,-(%sp) # insert new low mantissa + clr.l -(%sp) # insert zero high mantissa + clr.l -(%sp) # make zero exponent + bra.b sok_norm_cont + +# the src will force the dst to a DENORM value or worse. so, let's +# create an fp multiply that will create the result. +sok_norm: + fmovm.x DST(%a1),&0x80 # load fp0 with normalized src +sok_norm2: + fmov.l (%sp)+,%fpcr # restore user fpcr + + addi.w &0x3fff,%d0 # turn src amt into exp value + swap %d0 # put exponent in high word + clr.l -(%sp) # insert new exponent + mov.l &0x80000000,-(%sp) # insert new high mantissa + mov.l %d0,-(%sp) # insert new lo mantissa + +sok_norm_cont: + fmov.l %fpcr,%d0 # d0 needs fpcr for t_catch2 + mov.b &FMUL_OP,%d1 # last inst is MUL + fmul.x (%sp)+,%fp0 # do the multiply + bra t_catch2 # catch any exceptions + +# +# Source is outside of 2^14 range. Test the sign and branch +# to the appropriate exception handler. +# +src_out: + mov.l (%sp)+,%d0 # restore ctrl bits + exg %a0,%a1 # swap src,dst ptrs + tst.b SRC_EX(%a1) # is src negative? + bmi t_unfl # yes; underflow + bra t_ovfl_sc # no; overflow + +# +# The source input is below 1, so we check for denormalized numbers +# and set unfl. +# +src_small: + tst.b DST_HI(%a1) # is dst denormalized? + bpl.b ssmall_done # yes + + mov.l (%sp)+,%d0 + fmov.l %d0,%fpcr # no; load control bits + mov.b &FMOV_OP,%d1 # last inst is MOVE + fmov.x DST(%a1),%fp0 # simply return dest + bra t_catch2 +ssmall_done: + mov.l (%sp)+,%d0 # load control bits into d1 + mov.l %a1,%a0 # pass ptr to dst + bra t_resdnrm + +######################################################################### +# smod(): computes the fp MOD of the input values X,Y. # +# srem(): computes the fp (IEEE) REM of the input values X,Y. # +# # +# INPUT *************************************************************** # +# a0 = pointer to extended precision input X # +# a1 = pointer to extended precision input Y # +# d0 = round precision,mode # +# # +# The input operands X and Y can be either normalized or # +# denormalized. # +# # +# OUTPUT ************************************************************** # +# fp0 = FREM(X,Y) or FMOD(X,Y) # +# # +# ALGORITHM *********************************************************** # +# # +# Step 1. Save and strip signs of X and Y: signX := sign(X), # +# signY := sign(Y), X := |X|, Y := |Y|, # +# signQ := signX EOR signY. Record whether MOD or REM # +# is requested. # +# # +# Step 2. Set L := expo(X)-expo(Y), k := 0, Q := 0. # +# If (L < 0) then # +# R := X, go to Step 4. # +# else # +# R := 2^(-L)X, j := L. # +# endif # +# # +# Step 3. Perform MOD(X,Y) # +# 3.1 If R = Y, go to Step 9. # +# 3.2 If R > Y, then { R := R - Y, Q := Q + 1} # +# 3.3 If j = 0, go to Step 4. # +# 3.4 k := k + 1, j := j - 1, Q := 2Q, R := 2R. Go to # +# Step 3.1. # +# # +# Step 4. At this point, R = X - QY = MOD(X,Y). Set # +# Last_Subtract := false (used in Step 7 below). If # +# MOD is requested, go to Step 6. # +# # +# Step 5. R = MOD(X,Y), but REM(X,Y) is requested. # +# 5.1 If R < Y/2, then R = MOD(X,Y) = REM(X,Y). Go to # +# Step 6. # +# 5.2 If R > Y/2, then { set Last_Subtract := true, # +# Q := Q + 1, Y := signY*Y }. Go to Step 6. # +# 5.3 This is the tricky case of R = Y/2. If Q is odd, # +# then { Q := Q + 1, signX := -signX }. # +# # +# Step 6. R := signX*R. # +# # +# Step 7. If Last_Subtract = true, R := R - Y. # +# # +# Step 8. Return signQ, last 7 bits of Q, and R as required. # +# # +# Step 9. At this point, R = 2^(-j)*X - Q Y = Y. Thus, # +# X = 2^(j)*(Q+1)Y. set Q := 2^(j)*(Q+1), # +# R := 0. Return signQ, last 7 bits of Q, and R. # +# # +######################################################################### + + set Mod_Flag,L_SCR3 + set Sc_Flag,L_SCR3+1 + + set SignY,L_SCR2 + set SignX,L_SCR2+2 + set SignQ,L_SCR3+2 + + set Y,FP_SCR0 + set Y_Hi,Y+4 + set Y_Lo,Y+8 + + set R,FP_SCR1 + set R_Hi,R+4 + set R_Lo,R+8 + +Scale: + long 0x00010000,0x80000000,0x00000000,0x00000000 + + global smod +smod: + clr.b FPSR_QBYTE(%a6) + mov.l %d0,-(%sp) # save ctrl bits + clr.b Mod_Flag(%a6) + bra.b Mod_Rem + + global srem +srem: + clr.b FPSR_QBYTE(%a6) + mov.l %d0,-(%sp) # save ctrl bits + mov.b &0x1,Mod_Flag(%a6) + +Mod_Rem: +#..Save sign of X and Y + movm.l &0x3f00,-(%sp) # save data registers + mov.w SRC_EX(%a0),%d3 + mov.w %d3,SignY(%a6) + and.l &0x00007FFF,%d3 # Y := |Y| + +# + mov.l SRC_HI(%a0),%d4 + mov.l SRC_LO(%a0),%d5 # (D3,D4,D5) is |Y| + + tst.l %d3 + bne.b Y_Normal + + mov.l &0x00003FFE,%d3 # $3FFD + 1 + tst.l %d4 + bne.b HiY_not0 + +HiY_0: + mov.l %d5,%d4 + clr.l %d5 + sub.l &32,%d3 + clr.l %d6 + bfffo %d4{&0:&32},%d6 + lsl.l %d6,%d4 + sub.l %d6,%d3 # (D3,D4,D5) is normalized +# ...with bias $7FFD + bra.b Chk_X + +HiY_not0: + clr.l %d6 + bfffo %d4{&0:&32},%d6 + sub.l %d6,%d3 + lsl.l %d6,%d4 + mov.l %d5,%d7 # a copy of D5 + lsl.l %d6,%d5 + neg.l %d6 + add.l &32,%d6 + lsr.l %d6,%d7 + or.l %d7,%d4 # (D3,D4,D5) normalized +# ...with bias $7FFD + bra.b Chk_X + +Y_Normal: + add.l &0x00003FFE,%d3 # (D3,D4,D5) normalized +# ...with bias $7FFD + +Chk_X: + mov.w DST_EX(%a1),%d0 + mov.w %d0,SignX(%a6) + mov.w SignY(%a6),%d1 + eor.l %d0,%d1 + and.l &0x00008000,%d1 + mov.w %d1,SignQ(%a6) # sign(Q) obtained + and.l &0x00007FFF,%d0 + mov.l DST_HI(%a1),%d1 + mov.l DST_LO(%a1),%d2 # (D0,D1,D2) is |X| + tst.l %d0 + bne.b X_Normal + mov.l &0x00003FFE,%d0 + tst.l %d1 + bne.b HiX_not0 + +HiX_0: + mov.l %d2,%d1 + clr.l %d2 + sub.l &32,%d0 + clr.l %d6 + bfffo %d1{&0:&32},%d6 + lsl.l %d6,%d1 + sub.l %d6,%d0 # (D0,D1,D2) is normalized +# ...with bias $7FFD + bra.b Init + +HiX_not0: + clr.l %d6 + bfffo %d1{&0:&32},%d6 + sub.l %d6,%d0 + lsl.l %d6,%d1 + mov.l %d2,%d7 # a copy of D2 + lsl.l %d6,%d2 + neg.l %d6 + add.l &32,%d6 + lsr.l %d6,%d7 + or.l %d7,%d1 # (D0,D1,D2) normalized +# ...with bias $7FFD + bra.b Init + +X_Normal: + add.l &0x00003FFE,%d0 # (D0,D1,D2) normalized +# ...with bias $7FFD + +Init: +# + mov.l %d3,L_SCR1(%a6) # save biased exp(Y) + mov.l %d0,-(%sp) # save biased exp(X) + sub.l %d3,%d0 # L := expo(X)-expo(Y) + + clr.l %d6 # D6 := carry <- 0 + clr.l %d3 # D3 is Q + mov.l &0,%a1 # A1 is k; j+k=L, Q=0 + +#..(Carry,D1,D2) is R + tst.l %d0 + bge.b Mod_Loop_pre + +#..expo(X) < expo(Y). Thus X = mod(X,Y) +# + mov.l (%sp)+,%d0 # restore d0 + bra.w Get_Mod + +Mod_Loop_pre: + addq.l &0x4,%sp # erase exp(X) +#..At this point R = 2^(-L)X; Q = 0; k = 0; and k+j = L +Mod_Loop: + tst.l %d6 # test carry bit + bgt.b R_GT_Y + +#..At this point carry = 0, R = (D1,D2), Y = (D4,D5) + cmp.l %d1,%d4 # compare hi(R) and hi(Y) + bne.b R_NE_Y + cmp.l %d2,%d5 # compare lo(R) and lo(Y) + bne.b R_NE_Y + +#..At this point, R = Y + bra.w Rem_is_0 + +R_NE_Y: +#..use the borrow of the previous compare + bcs.b R_LT_Y # borrow is set iff R < Y + +R_GT_Y: +#..If Carry is set, then Y < (Carry,D1,D2) < 2Y. Otherwise, Carry = 0 +#..and Y < (D1,D2) < 2Y. Either way, perform R - Y + sub.l %d5,%d2 # lo(R) - lo(Y) + subx.l %d4,%d1 # hi(R) - hi(Y) + clr.l %d6 # clear carry + addq.l &1,%d3 # Q := Q + 1 + +R_LT_Y: +#..At this point, Carry=0, R < Y. R = 2^(k-L)X - QY; k+j = L; j >= 0. + tst.l %d0 # see if j = 0. + beq.b PostLoop + + add.l %d3,%d3 # Q := 2Q + add.l %d2,%d2 # lo(R) = 2lo(R) + roxl.l &1,%d1 # hi(R) = 2hi(R) + carry + scs %d6 # set Carry if 2(R) overflows + addq.l &1,%a1 # k := k+1 + subq.l &1,%d0 # j := j - 1 +#..At this point, R=(Carry,D1,D2) = 2^(k-L)X - QY, j+k=L, j >= 0, R < 2Y. + + bra.b Mod_Loop + +PostLoop: +#..k = L, j = 0, Carry = 0, R = (D1,D2) = X - QY, R < Y. + +#..normalize R. + mov.l L_SCR1(%a6),%d0 # new biased expo of R + tst.l %d1 + bne.b HiR_not0 + +HiR_0: + mov.l %d2,%d1 + clr.l %d2 + sub.l &32,%d0 + clr.l %d6 + bfffo %d1{&0:&32},%d6 + lsl.l %d6,%d1 + sub.l %d6,%d0 # (D0,D1,D2) is normalized +# ...with bias $7FFD + bra.b Get_Mod + +HiR_not0: + clr.l %d6 + bfffo %d1{&0:&32},%d6 + bmi.b Get_Mod # already normalized + sub.l %d6,%d0 + lsl.l %d6,%d1 + mov.l %d2,%d7 # a copy of D2 + lsl.l %d6,%d2 + neg.l %d6 + add.l &32,%d6 + lsr.l %d6,%d7 + or.l %d7,%d1 # (D0,D1,D2) normalized + +# +Get_Mod: + cmp.l %d0,&0x000041FE + bge.b No_Scale +Do_Scale: + mov.w %d0,R(%a6) + mov.l %d1,R_Hi(%a6) + mov.l %d2,R_Lo(%a6) + mov.l L_SCR1(%a6),%d6 + mov.w %d6,Y(%a6) + mov.l %d4,Y_Hi(%a6) + mov.l %d5,Y_Lo(%a6) + fmov.x R(%a6),%fp0 # no exception + mov.b &1,Sc_Flag(%a6) + bra.b ModOrRem +No_Scale: + mov.l %d1,R_Hi(%a6) + mov.l %d2,R_Lo(%a6) + sub.l &0x3FFE,%d0 + mov.w %d0,R(%a6) + mov.l L_SCR1(%a6),%d6 + sub.l &0x3FFE,%d6 + mov.l %d6,L_SCR1(%a6) + fmov.x R(%a6),%fp0 + mov.w %d6,Y(%a6) + mov.l %d4,Y_Hi(%a6) + mov.l %d5,Y_Lo(%a6) + clr.b Sc_Flag(%a6) + +# +ModOrRem: + tst.b Mod_Flag(%a6) + beq.b Fix_Sign + + mov.l L_SCR1(%a6),%d6 # new biased expo(Y) + subq.l &1,%d6 # biased expo(Y/2) + cmp.l %d0,%d6 + blt.b Fix_Sign + bgt.b Last_Sub + + cmp.l %d1,%d4 + bne.b Not_EQ + cmp.l %d2,%d5 + bne.b Not_EQ + bra.w Tie_Case + +Not_EQ: + bcs.b Fix_Sign + +Last_Sub: +# + fsub.x Y(%a6),%fp0 # no exceptions + addq.l &1,%d3 # Q := Q + 1 + +# +Fix_Sign: +#..Get sign of X + mov.w SignX(%a6),%d6 + bge.b Get_Q + fneg.x %fp0 + +#..Get Q +# +Get_Q: + clr.l %d6 + mov.w SignQ(%a6),%d6 # D6 is sign(Q) + mov.l &8,%d7 + lsr.l %d7,%d6 + and.l &0x0000007F,%d3 # 7 bits of Q + or.l %d6,%d3 # sign and bits of Q +# swap %d3 +# fmov.l %fpsr,%d6 +# and.l &0xFF00FFFF,%d6 +# or.l %d3,%d6 +# fmov.l %d6,%fpsr # put Q in fpsr + mov.b %d3,FPSR_QBYTE(%a6) # put Q in fpsr + +# +Restore: + movm.l (%sp)+,&0xfc # {%d2-%d7} + mov.l (%sp)+,%d0 + fmov.l %d0,%fpcr + tst.b Sc_Flag(%a6) + beq.b Finish + mov.b &FMUL_OP,%d1 # last inst is MUL + fmul.x Scale(%pc),%fp0 # may cause underflow + bra t_catch2 +# the '040 package did this apparently to see if the dst operand for the +# preceding fmul was a denorm. but, it better not have been since the +# algorithm just got done playing with fp0 and expected no exceptions +# as a result. trust me... +# bra t_avoid_unsupp # check for denorm as a +# ;result of the scaling + +Finish: + mov.b &FMOV_OP,%d1 # last inst is MOVE + fmov.x %fp0,%fp0 # capture exceptions & round + bra t_catch2 + +Rem_is_0: +#..R = 2^(-j)X - Q Y = Y, thus R = 0 and quotient = 2^j (Q+1) + addq.l &1,%d3 + cmp.l %d0,&8 # D0 is j + bge.b Q_Big + + lsl.l %d0,%d3 + bra.b Set_R_0 + +Q_Big: + clr.l %d3 + +Set_R_0: + fmov.s &0x00000000,%fp0 + clr.b Sc_Flag(%a6) + bra.w Fix_Sign + +Tie_Case: +#..Check parity of Q + mov.l %d3,%d6 + and.l &0x00000001,%d6 + tst.l %d6 + beq.w Fix_Sign # Q is even + +#..Q is odd, Q := Q + 1, signX := -signX + addq.l &1,%d3 + mov.w SignX(%a6),%d6 + eor.l &0x00008000,%d6 + mov.w %d6,SignX(%a6) + bra.w Fix_Sign + +######################################################################### +# XDEF **************************************************************** # +# tag(): return the optype of the input ext fp number # +# # +# This routine is used by the 060FPLSP. # +# # +# XREF **************************************************************** # +# None # +# # +# INPUT *************************************************************** # +# a0 = pointer to extended precision operand # +# # +# OUTPUT ************************************************************** # +# d0 = value of type tag # +# one of: NORM, INF, QNAN, SNAN, DENORM, ZERO # +# # +# ALGORITHM *********************************************************** # +# Simply test the exponent, j-bit, and mantissa values to # +# determine the type of operand. # +# If it's an unnormalized zero, alter the operand and force it # +# to be a normal zero. # +# # +######################################################################### + + global tag +tag: + mov.w FTEMP_EX(%a0), %d0 # extract exponent + andi.w &0x7fff, %d0 # strip off sign + cmpi.w %d0, &0x7fff # is (EXP == MAX)? + beq.b inf_or_nan_x +not_inf_or_nan_x: + btst &0x7,FTEMP_HI(%a0) + beq.b not_norm_x +is_norm_x: + mov.b &NORM, %d0 + rts +not_norm_x: + tst.w %d0 # is exponent = 0? + bne.b is_unnorm_x +not_unnorm_x: + tst.l FTEMP_HI(%a0) + bne.b is_denorm_x + tst.l FTEMP_LO(%a0) + bne.b is_denorm_x +is_zero_x: + mov.b &ZERO, %d0 + rts +is_denorm_x: + mov.b &DENORM, %d0 + rts +is_unnorm_x: + bsr.l unnorm_fix # convert to norm,denorm,or zero + rts +is_unnorm_reg_x: + mov.b &UNNORM, %d0 + rts +inf_or_nan_x: + tst.l FTEMP_LO(%a0) + bne.b is_nan_x + mov.l FTEMP_HI(%a0), %d0 + and.l &0x7fffffff, %d0 # msb is a don't care! + bne.b is_nan_x +is_inf_x: + mov.b &INF, %d0 + rts +is_nan_x: + mov.b &QNAN, %d0 + rts + +############################################################# + +qnan: long 0x7fff0000, 0xffffffff, 0xffffffff + +######################################################################### +# XDEF **************************************************************** # +# t_dz(): Handle 060FPLSP dz exception for "flogn" emulation. # +# t_dz2(): Handle 060FPLSP dz exception for "fatanh" emulation. # +# # +# These rouitnes are used by the 060FPLSP package. # +# # +# XREF **************************************************************** # +# None # +# # +# INPUT *************************************************************** # +# a0 = pointer to extended precision source operand. # +# # +# OUTPUT ************************************************************** # +# fp0 = default DZ result. # +# # +# ALGORITHM *********************************************************** # +# Transcendental emulation for the 060FPLSP has detected that # +# a DZ exception should occur for the instruction. If DZ is disabled, # +# return the default result. # +# If DZ is enabled, the dst operand should be returned unscathed # +# in fp0 while fp1 is used to create a DZ exception so that the # +# operating system can log that such an event occurred. # +# # +######################################################################### + + global t_dz +t_dz: + tst.b SRC_EX(%a0) # check sign for neg or pos + bpl.b dz_pinf # branch if pos sign + + global t_dz2 +t_dz2: + ori.l &dzinf_mask+neg_mask,USER_FPSR(%a6) # set N/I/DZ/ADZ + + btst &dz_bit,FPCR_ENABLE(%a6) + bne.b dz_minf_ena + +# dz is disabled. return a -INF. + fmov.s &0xff800000,%fp0 # return -INF + rts + +# dz is enabled. create a dz exception so the user can record it +# but use fp1 instead. return the dst operand unscathed in fp0. +dz_minf_ena: + fmovm.x EXC_FP0(%a6),&0x80 # return fp0 unscathed + fmov.l USER_FPCR(%a6),%fpcr + fmov.s &0xbf800000,%fp1 # load -1 + fdiv.s &0x00000000,%fp1 # -1 / 0 + rts + +dz_pinf: + ori.l &dzinf_mask,USER_FPSR(%a6) # set I/DZ/ADZ + + btst &dz_bit,FPCR_ENABLE(%a6) + bne.b dz_pinf_ena + +# dz is disabled. return a +INF. + fmov.s &0x7f800000,%fp0 # return +INF + rts + +# dz is enabled. create a dz exception so the user can record it +# but use fp1 instead. return the dst operand unscathed in fp0. +dz_pinf_ena: + fmovm.x EXC_FP0(%a6),&0x80 # return fp0 unscathed + fmov.l USER_FPCR(%a6),%fpcr + fmov.s &0x3f800000,%fp1 # load +1 + fdiv.s &0x00000000,%fp1 # +1 / 0 + rts + +######################################################################### +# XDEF **************************************************************** # +# t_operr(): Handle 060FPLSP OPERR exception during emulation. # +# # +# This routine is used by the 060FPLSP package. # +# # +# XREF **************************************************************** # +# None. # +# # +# INPUT *************************************************************** # +# fp1 = source operand # +# # +# OUTPUT ************************************************************** # +# fp0 = default result # +# fp1 = unchanged # +# # +# ALGORITHM *********************************************************** # +# An operand error should occur as the result of transcendental # +# emulation in the 060FPLSP. If OPERR is disabled, just return a NAN # +# in fp0. If OPERR is enabled, return the dst operand unscathed in fp0 # +# and the source operand in fp1. Use fp2 to create an OPERR exception # +# so that the operating system can log the event. # +# # +######################################################################### + + global t_operr +t_operr: + ori.l &opnan_mask,USER_FPSR(%a6) # set NAN/OPERR/AIOP + + btst &operr_bit,FPCR_ENABLE(%a6) + bne.b operr_ena + +# operr is disabled. return a QNAN in fp0 + fmovm.x qnan(%pc),&0x80 # return QNAN + rts + +# operr is enabled. create an operr exception so the user can record it +# but use fp2 instead. return the dst operand unscathed in fp0. +operr_ena: + fmovm.x EXC_FP0(%a6),&0x80 # return fp0 unscathed + fmov.l USER_FPCR(%a6),%fpcr + fmovm.x &0x04,-(%sp) # save fp2 + fmov.s &0x7f800000,%fp2 # load +INF + fmul.s &0x00000000,%fp2 # +INF x 0 + fmovm.x (%sp)+,&0x20 # restore fp2 + rts + +pls_huge: + long 0x7ffe0000,0xffffffff,0xffffffff +mns_huge: + long 0xfffe0000,0xffffffff,0xffffffff +pls_tiny: + long 0x00000000,0x80000000,0x00000000 +mns_tiny: + long 0x80000000,0x80000000,0x00000000 + +######################################################################### +# XDEF **************************************************************** # +# t_unfl(): Handle 060FPLSP underflow exception during emulation. # +# t_unfl2(): Handle 060FPLSP underflow exception during # +# emulation. result always positive. # +# # +# This routine is used by the 060FPLSP package. # +# # +# XREF **************************************************************** # +# None. # +# # +# INPUT *************************************************************** # +# a0 = pointer to extended precision source operand # +# # +# OUTPUT ************************************************************** # +# fp0 = default underflow result # +# # +# ALGORITHM *********************************************************** # +# An underflow should occur as the result of transcendental # +# emulation in the 060FPLSP. Create an underflow by using "fmul" # +# and two very small numbers of appropriate sign so the operating # +# system can log the event. # +# # +######################################################################### + + global t_unfl +t_unfl: + tst.b SRC_EX(%a0) + bpl.b unf_pos + + global t_unfl2 +t_unfl2: + ori.l &unfinx_mask+neg_mask,USER_FPSR(%a6) # set N/UNFL/INEX2/AUNFL/AINEX + + fmov.l USER_FPCR(%a6),%fpcr + fmovm.x mns_tiny(%pc),&0x80 + fmul.x pls_tiny(%pc),%fp0 + + fmov.l %fpsr,%d0 + rol.l &0x8,%d0 + mov.b %d0,FPSR_CC(%a6) + rts +unf_pos: + ori.w &unfinx_mask,FPSR_EXCEPT(%a6) # set UNFL/INEX2/AUNFL/AINEX + + fmov.l USER_FPCR(%a6),%fpcr + fmovm.x pls_tiny(%pc),&0x80 + fmul.x %fp0,%fp0 + + fmov.l %fpsr,%d0 + rol.l &0x8,%d0 + mov.b %d0,FPSR_CC(%a6) + rts + +######################################################################### +# XDEF **************************************************************** # +# t_ovfl(): Handle 060FPLSP overflow exception during emulation. # +# (monadic) # +# t_ovfl2(): Handle 060FPLSP overflow exception during # +# emulation. result always positive. (dyadic) # +# t_ovfl_sc(): Handle 060FPLSP overflow exception during # +# emulation for "fscale". # +# # +# This routine is used by the 060FPLSP package. # +# # +# XREF **************************************************************** # +# None. # +# # +# INPUT *************************************************************** # +# a0 = pointer to extended precision source operand # +# # +# OUTPUT ************************************************************** # +# fp0 = default underflow result # +# # +# ALGORITHM *********************************************************** # +# An overflow should occur as the result of transcendental # +# emulation in the 060FPLSP. Create an overflow by using "fmul" # +# and two very lareg numbers of appropriate sign so the operating # +# system can log the event. # +# For t_ovfl_sc() we take special care not to lose the INEX2 bit. # +# # +######################################################################### + + global t_ovfl_sc +t_ovfl_sc: + ori.l &ovfl_inx_mask,USER_FPSR(%a6) # set OVFL/AOVFL/AINEX + + mov.b %d0,%d1 # fetch rnd prec,mode + andi.b &0xc0,%d1 # extract prec + beq.w ovfl_work + +# dst op is a DENORM. we have to normalize the mantissa to see if the +# result would be inexact for the given precision. make a copy of the +# dst so we don't screw up the version passed to us. + mov.w LOCAL_EX(%a0),FP_SCR0_EX(%a6) + mov.l LOCAL_HI(%a0),FP_SCR0_HI(%a6) + mov.l LOCAL_LO(%a0),FP_SCR0_LO(%a6) + lea FP_SCR0(%a6),%a0 # pass ptr to FP_SCR0 + movm.l &0xc080,-(%sp) # save d0-d1/a0 + bsr.l norm # normalize mantissa + movm.l (%sp)+,&0x0103 # restore d0-d1/a0 + + cmpi.b %d1,&0x40 # is precision sgl? + bne.b ovfl_sc_dbl # no; dbl +ovfl_sc_sgl: + tst.l LOCAL_LO(%a0) # is lo lw of sgl set? + bne.b ovfl_sc_inx # yes + tst.b 3+LOCAL_HI(%a0) # is lo byte of hi lw set? + bne.b ovfl_sc_inx # yes + bra.w ovfl_work # don't set INEX2 +ovfl_sc_dbl: + mov.l LOCAL_LO(%a0),%d1 # are any of lo 11 bits of + andi.l &0x7ff,%d1 # dbl mantissa set? + beq.w ovfl_work # no; don't set INEX2 +ovfl_sc_inx: + ori.l &inex2_mask,USER_FPSR(%a6) # set INEX2 + bra.b ovfl_work # continue + + global t_ovfl +t_ovfl: + ori.w &ovfinx_mask,FPSR_EXCEPT(%a6) # set OVFL/INEX2/AOVFL/AINEX +ovfl_work: + tst.b SRC_EX(%a0) + bpl.b ovfl_p +ovfl_m: + fmov.l USER_FPCR(%a6),%fpcr + fmovm.x mns_huge(%pc),&0x80 + fmul.x pls_huge(%pc),%fp0 + + fmov.l %fpsr,%d0 + rol.l &0x8,%d0 + ori.b &neg_mask,%d0 + mov.b %d0,FPSR_CC(%a6) + rts +ovfl_p: + fmov.l USER_FPCR(%a6),%fpcr + fmovm.x pls_huge(%pc),&0x80 + fmul.x pls_huge(%pc),%fp0 + + fmov.l %fpsr,%d0 + rol.l &0x8,%d0 + mov.b %d0,FPSR_CC(%a6) + rts + + global t_ovfl2 +t_ovfl2: + ori.w &ovfinx_mask,FPSR_EXCEPT(%a6) # set OVFL/INEX2/AOVFL/AINEX + fmov.l USER_FPCR(%a6),%fpcr + fmovm.x pls_huge(%pc),&0x80 + fmul.x pls_huge(%pc),%fp0 + + fmov.l %fpsr,%d0 + rol.l &0x8,%d0 + mov.b %d0,FPSR_CC(%a6) + rts + +######################################################################### +# XDEF **************************************************************** # +# t_catch(): Handle 060FPLSP OVFL,UNFL,or INEX2 exception during # +# emulation. # +# t_catch2(): Handle 060FPLSP OVFL,UNFL,or INEX2 exception during # +# emulation. # +# # +# These routines are used by the 060FPLSP package. # +# # +# XREF **************************************************************** # +# None. # +# # +# INPUT *************************************************************** # +# fp0 = default underflow or overflow result # +# # +# OUTPUT ************************************************************** # +# fp0 = default result # +# # +# ALGORITHM *********************************************************** # +# If an overflow or underflow occurred during the last # +# instruction of transcendental 060FPLSP emulation, then it has already # +# occurred and has been logged. Now we need to see if an inexact # +# exception should occur. # +# # +######################################################################### + + global t_catch2 +t_catch2: + fmov.l %fpsr,%d0 + or.l %d0,USER_FPSR(%a6) + bra.b inx2_work + + global t_catch +t_catch: + fmov.l %fpsr,%d0 + or.l %d0,USER_FPSR(%a6) + +######################################################################### +# XDEF **************************************************************** # +# t_inx2(): Handle inexact 060FPLSP exception during emulation. # +# t_pinx2(): Handle inexact 060FPLSP exception for "+" results. # +# t_minx2(): Handle inexact 060FPLSP exception for "-" results. # +# # +# XREF **************************************************************** # +# None. # +# # +# INPUT *************************************************************** # +# fp0 = default result # +# # +# OUTPUT ************************************************************** # +# fp0 = default result # +# # +# ALGORITHM *********************************************************** # +# The last instruction of transcendental emulation for the # +# 060FPLSP should be inexact. So, if inexact is enabled, then we create # +# the event here by adding a large and very small number together # +# so that the operating system can log the event. # +# Must check, too, if the result was zero, in which case we just # +# set the FPSR bits and return. # +# # +######################################################################### + + global t_inx2 +t_inx2: + fblt.w t_minx2 + fbeq.w inx2_zero + + global t_pinx2 +t_pinx2: + ori.w &inx2a_mask,FPSR_EXCEPT(%a6) # set INEX2/AINEX + bra.b inx2_work + + global t_minx2 +t_minx2: + ori.l &inx2a_mask+neg_mask,USER_FPSR(%a6) + +inx2_work: + btst &inex2_bit,FPCR_ENABLE(%a6) # is inexact enabled? + bne.b inx2_work_ena # yes + rts +inx2_work_ena: + fmov.l USER_FPCR(%a6),%fpcr # insert user's exceptions + fmov.s &0x3f800000,%fp1 # load +1 + fadd.x pls_tiny(%pc),%fp1 # cause exception + rts + +inx2_zero: + mov.b &z_bmask,FPSR_CC(%a6) + ori.w &inx2a_mask,2+USER_FPSR(%a6) # set INEX/AINEX + rts + +######################################################################### +# XDEF **************************************************************** # +# t_extdnrm(): Handle DENORM inputs in 060FPLSP. # +# t_resdnrm(): Handle DENORM inputs in 060FPLSP for "fscale". # +# # +# This routine is used by the 060FPLSP package. # +# # +# XREF **************************************************************** # +# None. # +# # +# INPUT *************************************************************** # +# a0 = pointer to extended precision input operand # +# # +# OUTPUT ************************************************************** # +# fp0 = default result # +# # +# ALGORITHM *********************************************************** # +# For all functions that have a denormalized input and that # +# f(x)=x, this is the entry point. # +# DENORM value is moved using "fmove" which triggers an exception # +# if enabled so the operating system can log the event. # +# # +######################################################################### + + global t_extdnrm +t_extdnrm: + fmov.l USER_FPCR(%a6),%fpcr + fmov.x SRC_EX(%a0),%fp0 + fmov.l %fpsr,%d0 + ori.l &unfinx_mask,%d0 + or.l %d0,USER_FPSR(%a6) + rts + + global t_resdnrm +t_resdnrm: + fmov.l USER_FPCR(%a6),%fpcr + fmov.x SRC_EX(%a0),%fp0 + fmov.l %fpsr,%d0 + or.l %d0,USER_FPSR(%a6) + rts + +########################################## + +# +# sto_cos: +# This is used by fsincos library emulation. The correct +# values are already in fp0 and fp1 so we do nothing here. +# + global sto_cos +sto_cos: + rts + +########################################## + +# +# dst_qnan --- force result when destination is a NaN +# + global dst_qnan +dst_qnan: + fmov.x DST(%a1),%fp0 + tst.b DST_EX(%a1) + bmi.b dst_qnan_m +dst_qnan_p: + mov.b &nan_bmask,FPSR_CC(%a6) + rts +dst_qnan_m: + mov.b &nan_bmask+neg_bmask,FPSR_CC(%a6) + rts + +# +# src_qnan --- force result when source is a NaN +# + global src_qnan +src_qnan: + fmov.x SRC(%a0),%fp0 + tst.b SRC_EX(%a0) + bmi.b src_qnan_m +src_qnan_p: + mov.b &nan_bmask,FPSR_CC(%a6) + rts +src_qnan_m: + mov.b &nan_bmask+neg_bmask,FPSR_CC(%a6) + rts + +########################################## + +# +# Native instruction support +# +# Some systems may need entry points even for 68060 native +# instructions. These routines are provided for +# convenience. +# + global _fadds_ +_fadds_: + fmov.l %fpcr,-(%sp) # save fpcr + fmov.l &0x00000000,%fpcr # clear fpcr for load + fmov.s 0x8(%sp),%fp0 # load sgl dst + fmov.l (%sp)+,%fpcr # restore fpcr + fadd.s 0x8(%sp),%fp0 # fadd w/ sgl src + rts + + global _faddd_ +_faddd_: + fmov.l %fpcr,-(%sp) # save fpcr + fmov.l &0x00000000,%fpcr # clear fpcr for load + fmov.d 0x8(%sp),%fp0 # load dbl dst + fmov.l (%sp)+,%fpcr # restore fpcr + fadd.d 0xc(%sp),%fp0 # fadd w/ dbl src + rts + + global _faddx_ +_faddx_: + fmovm.x 0x4(%sp),&0x80 # load ext dst + fadd.x 0x10(%sp),%fp0 # fadd w/ ext src + rts + + global _fsubs_ +_fsubs_: + fmov.l %fpcr,-(%sp) # save fpcr + fmov.l &0x00000000,%fpcr # clear fpcr for load + fmov.s 0x8(%sp),%fp0 # load sgl dst + fmov.l (%sp)+,%fpcr # restore fpcr + fsub.s 0x8(%sp),%fp0 # fsub w/ sgl src + rts + + global _fsubd_ +_fsubd_: + fmov.l %fpcr,-(%sp) # save fpcr + fmov.l &0x00000000,%fpcr # clear fpcr for load + fmov.d 0x8(%sp),%fp0 # load dbl dst + fmov.l (%sp)+,%fpcr # restore fpcr + fsub.d 0xc(%sp),%fp0 # fsub w/ dbl src + rts + + global _fsubx_ +_fsubx_: + fmovm.x 0x4(%sp),&0x80 # load ext dst + fsub.x 0x10(%sp),%fp0 # fsub w/ ext src + rts + + global _fmuls_ +_fmuls_: + fmov.l %fpcr,-(%sp) # save fpcr + fmov.l &0x00000000,%fpcr # clear fpcr for load + fmov.s 0x8(%sp),%fp0 # load sgl dst + fmov.l (%sp)+,%fpcr # restore fpcr + fmul.s 0x8(%sp),%fp0 # fmul w/ sgl src + rts + + global _fmuld_ +_fmuld_: + fmov.l %fpcr,-(%sp) # save fpcr + fmov.l &0x00000000,%fpcr # clear fpcr for load + fmov.d 0x8(%sp),%fp0 # load dbl dst + fmov.l (%sp)+,%fpcr # restore fpcr + fmul.d 0xc(%sp),%fp0 # fmul w/ dbl src + rts + + global _fmulx_ +_fmulx_: + fmovm.x 0x4(%sp),&0x80 # load ext dst + fmul.x 0x10(%sp),%fp0 # fmul w/ ext src + rts + + global _fdivs_ +_fdivs_: + fmov.l %fpcr,-(%sp) # save fpcr + fmov.l &0x00000000,%fpcr # clear fpcr for load + fmov.s 0x8(%sp),%fp0 # load sgl dst + fmov.l (%sp)+,%fpcr # restore fpcr + fdiv.s 0x8(%sp),%fp0 # fdiv w/ sgl src + rts + + global _fdivd_ +_fdivd_: + fmov.l %fpcr,-(%sp) # save fpcr + fmov.l &0x00000000,%fpcr # clear fpcr for load + fmov.d 0x8(%sp),%fp0 # load dbl dst + fmov.l (%sp)+,%fpcr # restore fpcr + fdiv.d 0xc(%sp),%fp0 # fdiv w/ dbl src + rts + + global _fdivx_ +_fdivx_: + fmovm.x 0x4(%sp),&0x80 # load ext dst + fdiv.x 0x10(%sp),%fp0 # fdiv w/ ext src + rts + + global _fabss_ +_fabss_: + fabs.s 0x4(%sp),%fp0 # fabs w/ sgl src + rts + + global _fabsd_ +_fabsd_: + fabs.d 0x4(%sp),%fp0 # fabs w/ dbl src + rts + + global _fabsx_ +_fabsx_: + fabs.x 0x4(%sp),%fp0 # fabs w/ ext src + rts + + global _fnegs_ +_fnegs_: + fneg.s 0x4(%sp),%fp0 # fneg w/ sgl src + rts + + global _fnegd_ +_fnegd_: + fneg.d 0x4(%sp),%fp0 # fneg w/ dbl src + rts + + global _fnegx_ +_fnegx_: + fneg.x 0x4(%sp),%fp0 # fneg w/ ext src + rts + + global _fsqrts_ +_fsqrts_: + fsqrt.s 0x4(%sp),%fp0 # fsqrt w/ sgl src + rts + + global _fsqrtd_ +_fsqrtd_: + fsqrt.d 0x4(%sp),%fp0 # fsqrt w/ dbl src + rts + + global _fsqrtx_ +_fsqrtx_: + fsqrt.x 0x4(%sp),%fp0 # fsqrt w/ ext src + rts + + global _fints_ +_fints_: + fint.s 0x4(%sp),%fp0 # fint w/ sgl src + rts + + global _fintd_ +_fintd_: + fint.d 0x4(%sp),%fp0 # fint w/ dbl src + rts + + global _fintx_ +_fintx_: + fint.x 0x4(%sp),%fp0 # fint w/ ext src + rts + + global _fintrzs_ +_fintrzs_: + fintrz.s 0x4(%sp),%fp0 # fintrz w/ sgl src + rts + + global _fintrzd_ +_fintrzd_: + fintrz.d 0x4(%sp),%fp0 # fintrx w/ dbl src + rts + + global _fintrzx_ +_fintrzx_: + fintrz.x 0x4(%sp),%fp0 # fintrz w/ ext src + rts + +######################################################################## + +######################################################################### +# src_zero(): Return signed zero according to sign of src operand. # +######################################################################### + global src_zero +src_zero: + tst.b SRC_EX(%a0) # get sign of src operand + bmi.b ld_mzero # if neg, load neg zero + +# +# ld_pzero(): return a positive zero. +# + global ld_pzero +ld_pzero: + fmov.s &0x00000000,%fp0 # load +0 + mov.b &z_bmask,FPSR_CC(%a6) # set 'Z' ccode bit + rts + +# ld_mzero(): return a negative zero. + global ld_mzero +ld_mzero: + fmov.s &0x80000000,%fp0 # load -0 + mov.b &neg_bmask+z_bmask,FPSR_CC(%a6) # set 'N','Z' ccode bits + rts + +######################################################################### +# dst_zero(): Return signed zero according to sign of dst operand. # +######################################################################### + global dst_zero +dst_zero: + tst.b DST_EX(%a1) # get sign of dst operand + bmi.b ld_mzero # if neg, load neg zero + bra.b ld_pzero # load positive zero + +######################################################################### +# src_inf(): Return signed inf according to sign of src operand. # +######################################################################### + global src_inf +src_inf: + tst.b SRC_EX(%a0) # get sign of src operand + bmi.b ld_minf # if negative branch + +# +# ld_pinf(): return a positive infinity. +# + global ld_pinf +ld_pinf: + fmov.s &0x7f800000,%fp0 # load +INF + mov.b &inf_bmask,FPSR_CC(%a6) # set 'INF' ccode bit + rts + +# +# ld_minf():return a negative infinity. +# + global ld_minf +ld_minf: + fmov.s &0xff800000,%fp0 # load -INF + mov.b &neg_bmask+inf_bmask,FPSR_CC(%a6) # set 'N','I' ccode bits + rts + +######################################################################### +# dst_inf(): Return signed inf according to sign of dst operand. # +######################################################################### + global dst_inf +dst_inf: + tst.b DST_EX(%a1) # get sign of dst operand + bmi.b ld_minf # if negative branch + bra.b ld_pinf + + global szr_inf +################################################################# +# szr_inf(): Return +ZERO for a negative src operand or # +# +INF for a positive src operand. # +# Routine used for fetox, ftwotox, and ftentox. # +################################################################# +szr_inf: + tst.b SRC_EX(%a0) # check sign of source + bmi.b ld_pzero + bra.b ld_pinf + +######################################################################### +# sopr_inf(): Return +INF for a positive src operand or # +# jump to operand error routine for a negative src operand. # +# Routine used for flogn, flognp1, flog10, and flog2. # +######################################################################### + global sopr_inf +sopr_inf: + tst.b SRC_EX(%a0) # check sign of source + bmi.w t_operr + bra.b ld_pinf + +################################################################# +# setoxm1i(): Return minus one for a negative src operand or # +# positive infinity for a positive src operand. # +# Routine used for fetoxm1. # +################################################################# + global setoxm1i +setoxm1i: + tst.b SRC_EX(%a0) # check sign of source + bmi.b ld_mone + bra.b ld_pinf + +######################################################################### +# src_one(): Return signed one according to sign of src operand. # +######################################################################### + global src_one +src_one: + tst.b SRC_EX(%a0) # check sign of source + bmi.b ld_mone + +# +# ld_pone(): return positive one. +# + global ld_pone +ld_pone: + fmov.s &0x3f800000,%fp0 # load +1 + clr.b FPSR_CC(%a6) + rts + +# +# ld_mone(): return negative one. +# + global ld_mone +ld_mone: + fmov.s &0xbf800000,%fp0 # load -1 + mov.b &neg_bmask,FPSR_CC(%a6) # set 'N' ccode bit + rts + +ppiby2: long 0x3fff0000, 0xc90fdaa2, 0x2168c235 +mpiby2: long 0xbfff0000, 0xc90fdaa2, 0x2168c235 + +################################################################# +# spi_2(): Return signed PI/2 according to sign of src operand. # +################################################################# + global spi_2 +spi_2: + tst.b SRC_EX(%a0) # check sign of source + bmi.b ld_mpi2 + +# +# ld_ppi2(): return positive PI/2. +# + global ld_ppi2 +ld_ppi2: + fmov.l %d0,%fpcr + fmov.x ppiby2(%pc),%fp0 # load +pi/2 + bra.w t_pinx2 # set INEX2 + +# +# ld_mpi2(): return negative PI/2. +# + global ld_mpi2 +ld_mpi2: + fmov.l %d0,%fpcr + fmov.x mpiby2(%pc),%fp0 # load -pi/2 + bra.w t_minx2 # set INEX2 + +#################################################### +# The following routines give support for fsincos. # +#################################################### + +# +# ssincosz(): When the src operand is ZERO, store a one in the +# cosine register and return a ZERO in fp0 w/ the same sign +# as the src operand. +# + global ssincosz +ssincosz: + fmov.s &0x3f800000,%fp1 + tst.b SRC_EX(%a0) # test sign + bpl.b sincoszp + fmov.s &0x80000000,%fp0 # return sin result in fp0 + mov.b &z_bmask+neg_bmask,FPSR_CC(%a6) + rts +sincoszp: + fmov.s &0x00000000,%fp0 # return sin result in fp0 + mov.b &z_bmask,FPSR_CC(%a6) + rts + +# +# ssincosi(): When the src operand is INF, store a QNAN in the cosine +# register and jump to the operand error routine for negative +# src operands. +# + global ssincosi +ssincosi: + fmov.x qnan(%pc),%fp1 # load NAN + bra.w t_operr + +# +# ssincosqnan(): When the src operand is a QNAN, store the QNAN in the cosine +# register and branch to the src QNAN routine. +# + global ssincosqnan +ssincosqnan: + fmov.x LOCAL_EX(%a0),%fp1 + bra.w src_qnan + +######################################################################## + + global smod_sdnrm + global smod_snorm +smod_sdnrm: +smod_snorm: + mov.b DTAG(%a6),%d1 + beq.l smod + cmpi.b %d1,&ZERO + beq.w smod_zro + cmpi.b %d1,&INF + beq.l t_operr + cmpi.b %d1,&DENORM + beq.l smod + bra.l dst_qnan + + global smod_szero +smod_szero: + mov.b DTAG(%a6),%d1 + beq.l t_operr + cmpi.b %d1,&ZERO + beq.l t_operr + cmpi.b %d1,&INF + beq.l t_operr + cmpi.b %d1,&DENORM + beq.l t_operr + bra.l dst_qnan + + global smod_sinf +smod_sinf: + mov.b DTAG(%a6),%d1 + beq.l smod_fpn + cmpi.b %d1,&ZERO + beq.l smod_zro + cmpi.b %d1,&INF + beq.l t_operr + cmpi.b %d1,&DENORM + beq.l smod_fpn + bra.l dst_qnan + +smod_zro: +srem_zro: + mov.b SRC_EX(%a0),%d1 # get src sign + mov.b DST_EX(%a1),%d0 # get dst sign + eor.b %d0,%d1 # get qbyte sign + andi.b &0x80,%d1 + mov.b %d1,FPSR_QBYTE(%a6) + tst.b %d0 + bpl.w ld_pzero + bra.w ld_mzero + +smod_fpn: +srem_fpn: + clr.b FPSR_QBYTE(%a6) + mov.l %d0,-(%sp) + mov.b SRC_EX(%a0),%d1 # get src sign + mov.b DST_EX(%a1),%d0 # get dst sign + eor.b %d0,%d1 # get qbyte sign + andi.b &0x80,%d1 + mov.b %d1,FPSR_QBYTE(%a6) + cmpi.b DTAG(%a6),&DENORM + bne.b smod_nrm + lea DST(%a1),%a0 + mov.l (%sp)+,%d0 + bra t_resdnrm +smod_nrm: + fmov.l (%sp)+,%fpcr + fmov.x DST(%a1),%fp0 + tst.b DST_EX(%a1) + bmi.b smod_nrm_neg + rts + +smod_nrm_neg: + mov.b &neg_bmask,FPSR_CC(%a6) # set 'N' code + rts + +######################################################################### + global srem_snorm + global srem_sdnrm +srem_sdnrm: +srem_snorm: + mov.b DTAG(%a6),%d1 + beq.l srem + cmpi.b %d1,&ZERO + beq.w srem_zro + cmpi.b %d1,&INF + beq.l t_operr + cmpi.b %d1,&DENORM + beq.l srem + bra.l dst_qnan + + global srem_szero +srem_szero: + mov.b DTAG(%a6),%d1 + beq.l t_operr + cmpi.b %d1,&ZERO + beq.l t_operr + cmpi.b %d1,&INF + beq.l t_operr + cmpi.b %d1,&DENORM + beq.l t_operr + bra.l dst_qnan + + global srem_sinf +srem_sinf: + mov.b DTAG(%a6),%d1 + beq.w srem_fpn + cmpi.b %d1,&ZERO + beq.w srem_zro + cmpi.b %d1,&INF + beq.l t_operr + cmpi.b %d1,&DENORM + beq.l srem_fpn + bra.l dst_qnan + +######################################################################### + + global sscale_snorm + global sscale_sdnrm +sscale_snorm: +sscale_sdnrm: + mov.b DTAG(%a6),%d1 + beq.l sscale + cmpi.b %d1,&ZERO + beq.l dst_zero + cmpi.b %d1,&INF + beq.l dst_inf + cmpi.b %d1,&DENORM + beq.l sscale + bra.l dst_qnan + + global sscale_szero +sscale_szero: + mov.b DTAG(%a6),%d1 + beq.l sscale + cmpi.b %d1,&ZERO + beq.l dst_zero + cmpi.b %d1,&INF + beq.l dst_inf + cmpi.b %d1,&DENORM + beq.l sscale + bra.l dst_qnan + + global sscale_sinf +sscale_sinf: + mov.b DTAG(%a6),%d1 + beq.l t_operr + cmpi.b %d1,&QNAN + beq.l dst_qnan + bra.l t_operr + +######################################################################## + + global sop_sqnan +sop_sqnan: + mov.b DTAG(%a6),%d1 + cmpi.b %d1,&QNAN + beq.l dst_qnan + bra.l src_qnan + +######################################################################### +# norm(): normalize the mantissa of an extended precision input. the # +# input operand should not be normalized already. # +# # +# XDEF **************************************************************** # +# norm() # +# # +# XREF **************************************************************** # +# none # +# # +# INPUT *************************************************************** # +# a0 = pointer fp extended precision operand to normalize # +# # +# OUTPUT ************************************************************** # +# d0 = number of bit positions the mantissa was shifted # +# a0 = the input operand's mantissa is normalized; the exponent # +# is unchanged. # +# # +######################################################################### + global norm +norm: + mov.l %d2, -(%sp) # create some temp regs + mov.l %d3, -(%sp) + + mov.l FTEMP_HI(%a0), %d0 # load hi(mantissa) + mov.l FTEMP_LO(%a0), %d1 # load lo(mantissa) + + bfffo %d0{&0:&32}, %d2 # how many places to shift? + beq.b norm_lo # hi(man) is all zeroes! + +norm_hi: + lsl.l %d2, %d0 # left shift hi(man) + bfextu %d1{&0:%d2}, %d3 # extract lo bits + + or.l %d3, %d0 # create hi(man) + lsl.l %d2, %d1 # create lo(man) + + mov.l %d0, FTEMP_HI(%a0) # store new hi(man) + mov.l %d1, FTEMP_LO(%a0) # store new lo(man) + + mov.l %d2, %d0 # return shift amount + + mov.l (%sp)+, %d3 # restore temp regs + mov.l (%sp)+, %d2 + + rts + +norm_lo: + bfffo %d1{&0:&32}, %d2 # how many places to shift? + lsl.l %d2, %d1 # shift lo(man) + add.l &32, %d2 # add 32 to shft amount + + mov.l %d1, FTEMP_HI(%a0) # store hi(man) + clr.l FTEMP_LO(%a0) # lo(man) is now zero + + mov.l %d2, %d0 # return shift amount + + mov.l (%sp)+, %d3 # restore temp regs + mov.l (%sp)+, %d2 + + rts + +######################################################################### +# unnorm_fix(): - changes an UNNORM to one of NORM, DENORM, or ZERO # +# - returns corresponding optype tag # +# # +# XDEF **************************************************************** # +# unnorm_fix() # +# # +# XREF **************************************************************** # +# norm() - normalize the mantissa # +# # +# INPUT *************************************************************** # +# a0 = pointer to unnormalized extended precision number # +# # +# OUTPUT ************************************************************** # +# d0 = optype tag - is corrected to one of NORM, DENORM, or ZERO # +# a0 = input operand has been converted to a norm, denorm, or # +# zero; both the exponent and mantissa are changed. # +# # +######################################################################### + + global unnorm_fix +unnorm_fix: + bfffo FTEMP_HI(%a0){&0:&32}, %d0 # how many shifts are needed? + bne.b unnorm_shift # hi(man) is not all zeroes + +# +# hi(man) is all zeroes so see if any bits in lo(man) are set +# +unnorm_chk_lo: + bfffo FTEMP_LO(%a0){&0:&32}, %d0 # is operand really a zero? + beq.w unnorm_zero # yes + + add.w &32, %d0 # no; fix shift distance + +# +# d0 = # shifts needed for complete normalization +# +unnorm_shift: + clr.l %d1 # clear top word + mov.w FTEMP_EX(%a0), %d1 # extract exponent + and.w &0x7fff, %d1 # strip off sgn + + cmp.w %d0, %d1 # will denorm push exp < 0? + bgt.b unnorm_nrm_zero # yes; denorm only until exp = 0 + +# +# exponent would not go < 0. therefore, number stays normalized +# + sub.w %d0, %d1 # shift exponent value + mov.w FTEMP_EX(%a0), %d0 # load old exponent + and.w &0x8000, %d0 # save old sign + or.w %d0, %d1 # {sgn,new exp} + mov.w %d1, FTEMP_EX(%a0) # insert new exponent + + bsr.l norm # normalize UNNORM + + mov.b &NORM, %d0 # return new optype tag + rts + +# +# exponent would go < 0, so only denormalize until exp = 0 +# +unnorm_nrm_zero: + cmp.b %d1, &32 # is exp <= 32? + bgt.b unnorm_nrm_zero_lrg # no; go handle large exponent + + bfextu FTEMP_HI(%a0){%d1:&32}, %d0 # extract new hi(man) + mov.l %d0, FTEMP_HI(%a0) # save new hi(man) + + mov.l FTEMP_LO(%a0), %d0 # fetch old lo(man) + lsl.l %d1, %d0 # extract new lo(man) + mov.l %d0, FTEMP_LO(%a0) # save new lo(man) + + and.w &0x8000, FTEMP_EX(%a0) # set exp = 0 + + mov.b &DENORM, %d0 # return new optype tag + rts + +# +# only mantissa bits set are in lo(man) +# +unnorm_nrm_zero_lrg: + sub.w &32, %d1 # adjust shft amt by 32 + + mov.l FTEMP_LO(%a0), %d0 # fetch old lo(man) + lsl.l %d1, %d0 # left shift lo(man) + + mov.l %d0, FTEMP_HI(%a0) # store new hi(man) + clr.l FTEMP_LO(%a0) # lo(man) = 0 + + and.w &0x8000, FTEMP_EX(%a0) # set exp = 0 + + mov.b &DENORM, %d0 # return new optype tag + rts + +# +# whole mantissa is zero so this UNNORM is actually a zero +# +unnorm_zero: + and.w &0x8000, FTEMP_EX(%a0) # force exponent to zero + + mov.b &ZERO, %d0 # fix optype tag + rts diff --git a/arch/m68k/ifpsp060/src/fpsp.S b/arch/m68k/ifpsp060/src/fpsp.S new file mode 100644 index 000000000..9bbffebe3 --- /dev/null +++ b/arch/m68k/ifpsp060/src/fpsp.S @@ -0,0 +1,24785 @@ +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +MOTOROLA MICROPROCESSOR & MEMORY TECHNOLOGY GROUP +M68000 Hi-Performance Microprocessor Division +M68060 Software Package +Production Release P1.00 -- October 10, 1994 + +M68060 Software Package Copyright © 1993, 1994 Motorola Inc. All rights reserved. + +THE SOFTWARE is provided on an "AS IS" basis and without warranty. +To the maximum extent permitted by applicable law, +MOTOROLA DISCLAIMS ALL WARRANTIES WHETHER EXPRESS OR IMPLIED, +INCLUDING IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE +and any warranty against infringement with regard to the SOFTWARE +(INCLUDING ANY MODIFIED VERSIONS THEREOF) and any accompanying written materials. + +To the maximum extent permitted by applicable law, +IN NO EVENT SHALL MOTOROLA BE LIABLE FOR ANY DAMAGES WHATSOEVER +(INCLUDING WITHOUT LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, +BUSINESS INTERRUPTION, LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY LOSS) +ARISING OF THE USE OR INABILITY TO USE THE SOFTWARE. +Motorola assumes no responsibility for the maintenance and support of the SOFTWARE. + +You are hereby granted a copyright license to use, modify, and distribute the SOFTWARE +so long as this entire notice is retained without alteration in any modified and/or +redistributed versions, and that such modified versions are clearly identified as such. +No licenses are granted by implication, estoppel or otherwise under any patents +or trademarks of Motorola, Inc. +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +# +# freal.s: +# This file is appended to the top of the 060FPSP package +# and contains the entry points into the package. The user, in +# effect, branches to one of the branch table entries located +# after _060FPSP_TABLE. +# Also, subroutine stubs exist in this file (_fpsp_done for +# example) that are referenced by the FPSP package itself in order +# to call a given routine. The stub routine actually performs the +# callout. The FPSP code does a "bsr" to the stub routine. This +# extra layer of hierarchy adds a slight performance penalty but +# it makes the FPSP code easier to read and more mainatinable. +# + +set _off_bsun, 0x00 +set _off_snan, 0x04 +set _off_operr, 0x08 +set _off_ovfl, 0x0c +set _off_unfl, 0x10 +set _off_dz, 0x14 +set _off_inex, 0x18 +set _off_fline, 0x1c +set _off_fpu_dis, 0x20 +set _off_trap, 0x24 +set _off_trace, 0x28 +set _off_access, 0x2c +set _off_done, 0x30 + +set _off_imr, 0x40 +set _off_dmr, 0x44 +set _off_dmw, 0x48 +set _off_irw, 0x4c +set _off_irl, 0x50 +set _off_drb, 0x54 +set _off_drw, 0x58 +set _off_drl, 0x5c +set _off_dwb, 0x60 +set _off_dww, 0x64 +set _off_dwl, 0x68 + +_060FPSP_TABLE: + +############################################################### + +# Here's the table of ENTRY POINTS for those linking the package. + bra.l _fpsp_snan + short 0x0000 + bra.l _fpsp_operr + short 0x0000 + bra.l _fpsp_ovfl + short 0x0000 + bra.l _fpsp_unfl + short 0x0000 + bra.l _fpsp_dz + short 0x0000 + bra.l _fpsp_inex + short 0x0000 + bra.l _fpsp_fline + short 0x0000 + bra.l _fpsp_unsupp + short 0x0000 + bra.l _fpsp_effadd + short 0x0000 + + space 56 + +############################################################### + global _fpsp_done +_fpsp_done: + mov.l %d0,-(%sp) + mov.l (_060FPSP_TABLE-0x80+_off_done,%pc),%d0 + pea.l (_060FPSP_TABLE-0x80,%pc,%d0) + mov.l 0x4(%sp),%d0 + rtd &0x4 + + global _real_ovfl +_real_ovfl: + mov.l %d0,-(%sp) + mov.l (_060FPSP_TABLE-0x80+_off_ovfl,%pc),%d0 + pea.l (_060FPSP_TABLE-0x80,%pc,%d0) + mov.l 0x4(%sp),%d0 + rtd &0x4 + + global _real_unfl +_real_unfl: + mov.l %d0,-(%sp) + mov.l (_060FPSP_TABLE-0x80+_off_unfl,%pc),%d0 + pea.l (_060FPSP_TABLE-0x80,%pc,%d0) + mov.l 0x4(%sp),%d0 + rtd &0x4 + + global _real_inex +_real_inex: + mov.l %d0,-(%sp) + mov.l (_060FPSP_TABLE-0x80+_off_inex,%pc),%d0 + pea.l (_060FPSP_TABLE-0x80,%pc,%d0) + mov.l 0x4(%sp),%d0 + rtd &0x4 + + global _real_bsun +_real_bsun: + mov.l %d0,-(%sp) + mov.l (_060FPSP_TABLE-0x80+_off_bsun,%pc),%d0 + pea.l (_060FPSP_TABLE-0x80,%pc,%d0) + mov.l 0x4(%sp),%d0 + rtd &0x4 + + global _real_operr +_real_operr: + mov.l %d0,-(%sp) + mov.l (_060FPSP_TABLE-0x80+_off_operr,%pc),%d0 + pea.l (_060FPSP_TABLE-0x80,%pc,%d0) + mov.l 0x4(%sp),%d0 + rtd &0x4 + + global _real_snan +_real_snan: + mov.l %d0,-(%sp) + mov.l (_060FPSP_TABLE-0x80+_off_snan,%pc),%d0 + pea.l (_060FPSP_TABLE-0x80,%pc,%d0) + mov.l 0x4(%sp),%d0 + rtd &0x4 + + global _real_dz +_real_dz: + mov.l %d0,-(%sp) + mov.l (_060FPSP_TABLE-0x80+_off_dz,%pc),%d0 + pea.l (_060FPSP_TABLE-0x80,%pc,%d0) + mov.l 0x4(%sp),%d0 + rtd &0x4 + + global _real_fline +_real_fline: + mov.l %d0,-(%sp) + mov.l (_060FPSP_TABLE-0x80+_off_fline,%pc),%d0 + pea.l (_060FPSP_TABLE-0x80,%pc,%d0) + mov.l 0x4(%sp),%d0 + rtd &0x4 + + global _real_fpu_disabled +_real_fpu_disabled: + mov.l %d0,-(%sp) + mov.l (_060FPSP_TABLE-0x80+_off_fpu_dis,%pc),%d0 + pea.l (_060FPSP_TABLE-0x80,%pc,%d0) + mov.l 0x4(%sp),%d0 + rtd &0x4 + + global _real_trap +_real_trap: + mov.l %d0,-(%sp) + mov.l (_060FPSP_TABLE-0x80+_off_trap,%pc),%d0 + pea.l (_060FPSP_TABLE-0x80,%pc,%d0) + mov.l 0x4(%sp),%d0 + rtd &0x4 + + global _real_trace +_real_trace: + mov.l %d0,-(%sp) + mov.l (_060FPSP_TABLE-0x80+_off_trace,%pc),%d0 + pea.l (_060FPSP_TABLE-0x80,%pc,%d0) + mov.l 0x4(%sp),%d0 + rtd &0x4 + + global _real_access +_real_access: + mov.l %d0,-(%sp) + mov.l (_060FPSP_TABLE-0x80+_off_access,%pc),%d0 + pea.l (_060FPSP_TABLE-0x80,%pc,%d0) + mov.l 0x4(%sp),%d0 + rtd &0x4 + +####################################### + + global _imem_read +_imem_read: + mov.l %d0,-(%sp) + mov.l (_060FPSP_TABLE-0x80+_off_imr,%pc),%d0 + pea.l (_060FPSP_TABLE-0x80,%pc,%d0) + mov.l 0x4(%sp),%d0 + rtd &0x4 + + global _dmem_read +_dmem_read: + mov.l %d0,-(%sp) + mov.l (_060FPSP_TABLE-0x80+_off_dmr,%pc),%d0 + pea.l (_060FPSP_TABLE-0x80,%pc,%d0) + mov.l 0x4(%sp),%d0 + rtd &0x4 + + global _dmem_write +_dmem_write: + mov.l %d0,-(%sp) + mov.l (_060FPSP_TABLE-0x80+_off_dmw,%pc),%d0 + pea.l (_060FPSP_TABLE-0x80,%pc,%d0) + mov.l 0x4(%sp),%d0 + rtd &0x4 + + global _imem_read_word +_imem_read_word: + mov.l %d0,-(%sp) + mov.l (_060FPSP_TABLE-0x80+_off_irw,%pc),%d0 + pea.l (_060FPSP_TABLE-0x80,%pc,%d0) + mov.l 0x4(%sp),%d0 + rtd &0x4 + + global _imem_read_long +_imem_read_long: + mov.l %d0,-(%sp) + mov.l (_060FPSP_TABLE-0x80+_off_irl,%pc),%d0 + pea.l (_060FPSP_TABLE-0x80,%pc,%d0) + mov.l 0x4(%sp),%d0 + rtd &0x4 + + global _dmem_read_byte +_dmem_read_byte: + mov.l %d0,-(%sp) + mov.l (_060FPSP_TABLE-0x80+_off_drb,%pc),%d0 + pea.l (_060FPSP_TABLE-0x80,%pc,%d0) + mov.l 0x4(%sp),%d0 + rtd &0x4 + + global _dmem_read_word +_dmem_read_word: + mov.l %d0,-(%sp) + mov.l (_060FPSP_TABLE-0x80+_off_drw,%pc),%d0 + pea.l (_060FPSP_TABLE-0x80,%pc,%d0) + mov.l 0x4(%sp),%d0 + rtd &0x4 + + global _dmem_read_long +_dmem_read_long: + mov.l %d0,-(%sp) + mov.l (_060FPSP_TABLE-0x80+_off_drl,%pc),%d0 + pea.l (_060FPSP_TABLE-0x80,%pc,%d0) + mov.l 0x4(%sp),%d0 + rtd &0x4 + + global _dmem_write_byte +_dmem_write_byte: + mov.l %d0,-(%sp) + mov.l (_060FPSP_TABLE-0x80+_off_dwb,%pc),%d0 + pea.l (_060FPSP_TABLE-0x80,%pc,%d0) + mov.l 0x4(%sp),%d0 + rtd &0x4 + + global _dmem_write_word +_dmem_write_word: + mov.l %d0,-(%sp) + mov.l (_060FPSP_TABLE-0x80+_off_dww,%pc),%d0 + pea.l (_060FPSP_TABLE-0x80,%pc,%d0) + mov.l 0x4(%sp),%d0 + rtd &0x4 + + global _dmem_write_long +_dmem_write_long: + mov.l %d0,-(%sp) + mov.l (_060FPSP_TABLE-0x80+_off_dwl,%pc),%d0 + pea.l (_060FPSP_TABLE-0x80,%pc,%d0) + mov.l 0x4(%sp),%d0 + rtd &0x4 + +# +# This file contains a set of define statements for constants +# in order to promote readability within the corecode itself. +# + +set LOCAL_SIZE, 192 # stack frame size(bytes) +set LV, -LOCAL_SIZE # stack offset + +set EXC_SR, 0x4 # stack status register +set EXC_PC, 0x6 # stack pc +set EXC_VOFF, 0xa # stacked vector offset +set EXC_EA, 0xc # stacked + +set EXC_FP, 0x0 # frame pointer + +set EXC_AREGS, -68 # offset of all address regs +set EXC_DREGS, -100 # offset of all data regs +set EXC_FPREGS, -36 # offset of all fp regs + +set EXC_A7, EXC_AREGS+(7*4) # offset of saved a7 +set OLD_A7, EXC_AREGS+(6*4) # extra copy of saved a7 +set EXC_A6, EXC_AREGS+(6*4) # offset of saved a6 +set EXC_A5, EXC_AREGS+(5*4) +set EXC_A4, EXC_AREGS+(4*4) +set EXC_A3, EXC_AREGS+(3*4) +set EXC_A2, EXC_AREGS+(2*4) +set EXC_A1, EXC_AREGS+(1*4) +set EXC_A0, EXC_AREGS+(0*4) +set EXC_D7, EXC_DREGS+(7*4) +set EXC_D6, EXC_DREGS+(6*4) +set EXC_D5, EXC_DREGS+(5*4) +set EXC_D4, EXC_DREGS+(4*4) +set EXC_D3, EXC_DREGS+(3*4) +set EXC_D2, EXC_DREGS+(2*4) +set EXC_D1, EXC_DREGS+(1*4) +set EXC_D0, EXC_DREGS+(0*4) + +set EXC_FP0, EXC_FPREGS+(0*12) # offset of saved fp0 +set EXC_FP1, EXC_FPREGS+(1*12) # offset of saved fp1 +set EXC_FP2, EXC_FPREGS+(2*12) # offset of saved fp2 (not used) + +set FP_SCR1, LV+80 # fp scratch 1 +set FP_SCR1_EX, FP_SCR1+0 +set FP_SCR1_SGN, FP_SCR1+2 +set FP_SCR1_HI, FP_SCR1+4 +set FP_SCR1_LO, FP_SCR1+8 + +set FP_SCR0, LV+68 # fp scratch 0 +set FP_SCR0_EX, FP_SCR0+0 +set FP_SCR0_SGN, FP_SCR0+2 +set FP_SCR0_HI, FP_SCR0+4 +set FP_SCR0_LO, FP_SCR0+8 + +set FP_DST, LV+56 # fp destination operand +set FP_DST_EX, FP_DST+0 +set FP_DST_SGN, FP_DST+2 +set FP_DST_HI, FP_DST+4 +set FP_DST_LO, FP_DST+8 + +set FP_SRC, LV+44 # fp source operand +set FP_SRC_EX, FP_SRC+0 +set FP_SRC_SGN, FP_SRC+2 +set FP_SRC_HI, FP_SRC+4 +set FP_SRC_LO, FP_SRC+8 + +set USER_FPIAR, LV+40 # FP instr address register + +set USER_FPSR, LV+36 # FP status register +set FPSR_CC, USER_FPSR+0 # FPSR condition codes +set FPSR_QBYTE, USER_FPSR+1 # FPSR qoutient byte +set FPSR_EXCEPT, USER_FPSR+2 # FPSR exception status byte +set FPSR_AEXCEPT, USER_FPSR+3 # FPSR accrued exception byte + +set USER_FPCR, LV+32 # FP control register +set FPCR_ENABLE, USER_FPCR+2 # FPCR exception enable +set FPCR_MODE, USER_FPCR+3 # FPCR rounding mode control + +set L_SCR3, LV+28 # integer scratch 3 +set L_SCR2, LV+24 # integer scratch 2 +set L_SCR1, LV+20 # integer scratch 1 + +set STORE_FLG, LV+19 # flag: operand store (ie. not fcmp/ftst) + +set EXC_TEMP2, LV+24 # temporary space +set EXC_TEMP, LV+16 # temporary space + +set DTAG, LV+15 # destination operand type +set STAG, LV+14 # source operand type + +set SPCOND_FLG, LV+10 # flag: special case (see below) + +set EXC_CC, LV+8 # saved condition codes +set EXC_EXTWPTR, LV+4 # saved current PC (active) +set EXC_EXTWORD, LV+2 # saved extension word +set EXC_CMDREG, LV+2 # saved extension word +set EXC_OPWORD, LV+0 # saved operation word + +################################ + +# Helpful macros + +set FTEMP, 0 # offsets within an +set FTEMP_EX, 0 # extended precision +set FTEMP_SGN, 2 # value saved in memory. +set FTEMP_HI, 4 +set FTEMP_LO, 8 +set FTEMP_GRS, 12 + +set LOCAL, 0 # offsets within an +set LOCAL_EX, 0 # extended precision +set LOCAL_SGN, 2 # value saved in memory. +set LOCAL_HI, 4 +set LOCAL_LO, 8 +set LOCAL_GRS, 12 + +set DST, 0 # offsets within an +set DST_EX, 0 # extended precision +set DST_HI, 4 # value saved in memory. +set DST_LO, 8 + +set SRC, 0 # offsets within an +set SRC_EX, 0 # extended precision +set SRC_HI, 4 # value saved in memory. +set SRC_LO, 8 + +set SGL_LO, 0x3f81 # min sgl prec exponent +set SGL_HI, 0x407e # max sgl prec exponent +set DBL_LO, 0x3c01 # min dbl prec exponent +set DBL_HI, 0x43fe # max dbl prec exponent +set EXT_LO, 0x0 # min ext prec exponent +set EXT_HI, 0x7ffe # max ext prec exponent + +set EXT_BIAS, 0x3fff # extended precision bias +set SGL_BIAS, 0x007f # single precision bias +set DBL_BIAS, 0x03ff # double precision bias + +set NORM, 0x00 # operand type for STAG/DTAG +set ZERO, 0x01 # operand type for STAG/DTAG +set INF, 0x02 # operand type for STAG/DTAG +set QNAN, 0x03 # operand type for STAG/DTAG +set DENORM, 0x04 # operand type for STAG/DTAG +set SNAN, 0x05 # operand type for STAG/DTAG +set UNNORM, 0x06 # operand type for STAG/DTAG + +################## +# FPSR/FPCR bits # +################## +set neg_bit, 0x3 # negative result +set z_bit, 0x2 # zero result +set inf_bit, 0x1 # infinite result +set nan_bit, 0x0 # NAN result + +set q_sn_bit, 0x7 # sign bit of quotient byte + +set bsun_bit, 7 # branch on unordered +set snan_bit, 6 # signalling NAN +set operr_bit, 5 # operand error +set ovfl_bit, 4 # overflow +set unfl_bit, 3 # underflow +set dz_bit, 2 # divide by zero +set inex2_bit, 1 # inexact result 2 +set inex1_bit, 0 # inexact result 1 + +set aiop_bit, 7 # accrued inexact operation bit +set aovfl_bit, 6 # accrued overflow bit +set aunfl_bit, 5 # accrued underflow bit +set adz_bit, 4 # accrued dz bit +set ainex_bit, 3 # accrued inexact bit + +############################# +# FPSR individual bit masks # +############################# +set neg_mask, 0x08000000 # negative bit mask (lw) +set inf_mask, 0x02000000 # infinity bit mask (lw) +set z_mask, 0x04000000 # zero bit mask (lw) +set nan_mask, 0x01000000 # nan bit mask (lw) + +set neg_bmask, 0x08 # negative bit mask (byte) +set inf_bmask, 0x02 # infinity bit mask (byte) +set z_bmask, 0x04 # zero bit mask (byte) +set nan_bmask, 0x01 # nan bit mask (byte) + +set bsun_mask, 0x00008000 # bsun exception mask +set snan_mask, 0x00004000 # snan exception mask +set operr_mask, 0x00002000 # operr exception mask +set ovfl_mask, 0x00001000 # overflow exception mask +set unfl_mask, 0x00000800 # underflow exception mask +set dz_mask, 0x00000400 # dz exception mask +set inex2_mask, 0x00000200 # inex2 exception mask +set inex1_mask, 0x00000100 # inex1 exception mask + +set aiop_mask, 0x00000080 # accrued illegal operation +set aovfl_mask, 0x00000040 # accrued overflow +set aunfl_mask, 0x00000020 # accrued underflow +set adz_mask, 0x00000010 # accrued divide by zero +set ainex_mask, 0x00000008 # accrued inexact + +###################################### +# FPSR combinations used in the FPSP # +###################################### +set dzinf_mask, inf_mask+dz_mask+adz_mask +set opnan_mask, nan_mask+operr_mask+aiop_mask +set nzi_mask, 0x01ffffff #clears N, Z, and I +set unfinx_mask, unfl_mask+inex2_mask+aunfl_mask+ainex_mask +set unf2inx_mask, unfl_mask+inex2_mask+ainex_mask +set ovfinx_mask, ovfl_mask+inex2_mask+aovfl_mask+ainex_mask +set inx1a_mask, inex1_mask+ainex_mask +set inx2a_mask, inex2_mask+ainex_mask +set snaniop_mask, nan_mask+snan_mask+aiop_mask +set snaniop2_mask, snan_mask+aiop_mask +set naniop_mask, nan_mask+aiop_mask +set neginf_mask, neg_mask+inf_mask +set infaiop_mask, inf_mask+aiop_mask +set negz_mask, neg_mask+z_mask +set opaop_mask, operr_mask+aiop_mask +set unfl_inx_mask, unfl_mask+aunfl_mask+ainex_mask +set ovfl_inx_mask, ovfl_mask+aovfl_mask+ainex_mask + +######### +# misc. # +######### +set rnd_stky_bit, 29 # stky bit pos in longword + +set sign_bit, 0x7 # sign bit +set signan_bit, 0x6 # signalling nan bit + +set sgl_thresh, 0x3f81 # minimum sgl exponent +set dbl_thresh, 0x3c01 # minimum dbl exponent + +set x_mode, 0x0 # extended precision +set s_mode, 0x4 # single precision +set d_mode, 0x8 # double precision + +set rn_mode, 0x0 # round-to-nearest +set rz_mode, 0x1 # round-to-zero +set rm_mode, 0x2 # round-tp-minus-infinity +set rp_mode, 0x3 # round-to-plus-infinity + +set mantissalen, 64 # length of mantissa in bits + +set BYTE, 1 # len(byte) == 1 byte +set WORD, 2 # len(word) == 2 bytes +set LONG, 4 # len(longword) == 2 bytes + +set BSUN_VEC, 0xc0 # bsun vector offset +set INEX_VEC, 0xc4 # inexact vector offset +set DZ_VEC, 0xc8 # dz vector offset +set UNFL_VEC, 0xcc # unfl vector offset +set OPERR_VEC, 0xd0 # operr vector offset +set OVFL_VEC, 0xd4 # ovfl vector offset +set SNAN_VEC, 0xd8 # snan vector offset + +########################### +# SPecial CONDition FLaGs # +########################### +set ftrapcc_flg, 0x01 # flag bit: ftrapcc exception +set fbsun_flg, 0x02 # flag bit: bsun exception +set mia7_flg, 0x04 # flag bit: (a7)+ +set mda7_flg, 0x08 # flag bit: -(a7) +set fmovm_flg, 0x40 # flag bit: fmovm instruction +set immed_flg, 0x80 # flag bit: & + +set ftrapcc_bit, 0x0 +set fbsun_bit, 0x1 +set mia7_bit, 0x2 +set mda7_bit, 0x3 +set immed_bit, 0x7 + +################################## +# TRANSCENDENTAL "LAST-OP" FLAGS # +################################## +set FMUL_OP, 0x0 # fmul instr performed last +set FDIV_OP, 0x1 # fdiv performed last +set FADD_OP, 0x2 # fadd performed last +set FMOV_OP, 0x3 # fmov performed last + +############# +# CONSTANTS # +############# +T1: long 0x40C62D38,0xD3D64634 # 16381 LOG2 LEAD +T2: long 0x3D6F90AE,0xB1E75CC7 # 16381 LOG2 TRAIL + +PI: long 0x40000000,0xC90FDAA2,0x2168C235,0x00000000 +PIBY2: long 0x3FFF0000,0xC90FDAA2,0x2168C235,0x00000000 + +TWOBYPI: + long 0x3FE45F30,0x6DC9C883 + +######################################################################### +# XDEF **************************************************************** # +# _fpsp_ovfl(): 060FPSP entry point for FP Overflow exception. # +# # +# This handler should be the first code executed upon taking the # +# FP Overflow exception in an operating system. # +# # +# XREF **************************************************************** # +# _imem_read_long() - read instruction longword # +# fix_skewed_ops() - adjust src operand in fsave frame # +# set_tag_x() - determine optype of src/dst operands # +# store_fpreg() - store opclass 0 or 2 result to FP regfile # +# unnorm_fix() - change UNNORM operands to NORM or ZERO # +# load_fpn2() - load dst operand from FP regfile # +# fout() - emulate an opclass 3 instruction # +# tbl_unsupp - add of table of emulation routines for opclass 0,2 # +# _fpsp_done() - "callout" for 060FPSP exit (all work done!) # +# _real_ovfl() - "callout" for Overflow exception enabled code # +# _real_inex() - "callout" for Inexact exception enabled code # +# _real_trace() - "callout" for Trace exception code # +# # +# INPUT *************************************************************** # +# - The system stack contains the FP Ovfl exception stack frame # +# - The fsave frame contains the source operand # +# # +# OUTPUT ************************************************************** # +# Overflow Exception enabled: # +# - The system stack is unchanged # +# - The fsave frame contains the adjusted src op for opclass 0,2 # +# Overflow Exception disabled: # +# - The system stack is unchanged # +# - The "exception present" flag in the fsave frame is cleared # +# # +# ALGORITHM *********************************************************** # +# On the 060, if an FP overflow is present as the result of any # +# instruction, the 060 will take an overflow exception whether the # +# exception is enabled or disabled in the FPCR. For the disabled case, # +# This handler emulates the instruction to determine what the correct # +# default result should be for the operation. This default result is # +# then stored in either the FP regfile, data regfile, or memory. # +# Finally, the handler exits through the "callout" _fpsp_done() # +# denoting that no exceptional conditions exist within the machine. # +# If the exception is enabled, then this handler must create the # +# exceptional operand and plave it in the fsave state frame, and store # +# the default result (only if the instruction is opclass 3). For # +# exceptions enabled, this handler must exit through the "callout" # +# _real_ovfl() so that the operating system enabled overflow handler # +# can handle this case. # +# Two other conditions exist. First, if overflow was disabled # +# but the inexact exception was enabled, this handler must exit # +# through the "callout" _real_inex() regardless of whether the result # +# was inexact. # +# Also, in the case of an opclass three instruction where # +# overflow was disabled and the trace exception was enabled, this # +# handler must exit through the "callout" _real_trace(). # +# # +######################################################################### + + global _fpsp_ovfl +_fpsp_ovfl: + +#$# sub.l &24,%sp # make room for src/dst + + link.w %a6,&-LOCAL_SIZE # init stack frame + + fsave FP_SRC(%a6) # grab the "busy" frame + + movm.l &0x0303,EXC_DREGS(%a6) # save d0-d1/a0-a1 + fmovm.l %fpcr,%fpsr,%fpiar,USER_FPCR(%a6) # save ctrl regs + fmovm.x &0xc0,EXC_FPREGS(%a6) # save fp0-fp1 on stack + +# the FPIAR holds the "current PC" of the faulting instruction + mov.l USER_FPIAR(%a6),EXC_EXTWPTR(%a6) + mov.l EXC_EXTWPTR(%a6),%a0 # fetch instruction addr + addq.l &0x4,EXC_EXTWPTR(%a6) # incr instruction ptr + bsr.l _imem_read_long # fetch the instruction words + mov.l %d0,EXC_OPWORD(%a6) + +############################################################################## + + btst &0x5,EXC_CMDREG(%a6) # is instr an fmove out? + bne.w fovfl_out + + + lea FP_SRC(%a6),%a0 # pass: ptr to src op + bsr.l fix_skewed_ops # fix src op + +# since, I believe, only NORMs and DENORMs can come through here, +# maybe we can avoid the subroutine call. + lea FP_SRC(%a6),%a0 # pass: ptr to src op + bsr.l set_tag_x # tag the operand type + mov.b %d0,STAG(%a6) # maybe NORM,DENORM + +# bit five of the fp extension word separates the monadic and dyadic operations +# that can pass through fpsp_ovfl(). remember that fcmp, ftst, and fsincos +# will never take this exception. + btst &0x5,1+EXC_CMDREG(%a6) # is operation monadic or dyadic? + beq.b fovfl_extract # monadic + + bfextu EXC_CMDREG(%a6){&6:&3},%d0 # dyadic; load dst reg + bsr.l load_fpn2 # load dst into FP_DST + + lea FP_DST(%a6),%a0 # pass: ptr to dst op + bsr.l set_tag_x # tag the operand type + cmpi.b %d0,&UNNORM # is operand an UNNORM? + bne.b fovfl_op2_done # no + bsr.l unnorm_fix # yes; convert to NORM,DENORM,or ZERO +fovfl_op2_done: + mov.b %d0,DTAG(%a6) # save dst optype tag + +fovfl_extract: + +#$# mov.l FP_SRC_EX(%a6),TRAP_SRCOP_EX(%a6) +#$# mov.l FP_SRC_HI(%a6),TRAP_SRCOP_HI(%a6) +#$# mov.l FP_SRC_LO(%a6),TRAP_SRCOP_LO(%a6) +#$# mov.l FP_DST_EX(%a6),TRAP_DSTOP_EX(%a6) +#$# mov.l FP_DST_HI(%a6),TRAP_DSTOP_HI(%a6) +#$# mov.l FP_DST_LO(%a6),TRAP_DSTOP_LO(%a6) + + clr.l %d0 + mov.b FPCR_MODE(%a6),%d0 # pass rnd prec/mode + + mov.b 1+EXC_CMDREG(%a6),%d1 + andi.w &0x007f,%d1 # extract extension + + andi.l &0x00ff01ff,USER_FPSR(%a6) # zero all but accured field + + fmov.l &0x0,%fpcr # zero current control regs + fmov.l &0x0,%fpsr + + lea FP_SRC(%a6),%a0 + lea FP_DST(%a6),%a1 + +# maybe we can make these entry points ONLY the OVFL entry points of each routine. + mov.l (tbl_unsupp.l,%pc,%d1.w*4),%d1 # fetch routine addr + jsr (tbl_unsupp.l,%pc,%d1.l*1) + +# the operation has been emulated. the result is in fp0. +# the EXOP, if an exception occurred, is in fp1. +# we must save the default result regardless of whether +# traps are enabled or disabled. + bfextu EXC_CMDREG(%a6){&6:&3},%d0 + bsr.l store_fpreg + +# the exceptional possibilities we have left ourselves with are ONLY overflow +# and inexact. and, the inexact is such that overflow occurred and was disabled +# but inexact was enabled. + btst &ovfl_bit,FPCR_ENABLE(%a6) + bne.b fovfl_ovfl_on + + btst &inex2_bit,FPCR_ENABLE(%a6) + bne.b fovfl_inex_on + + fmovm.x EXC_FPREGS(%a6),&0xc0 # restore fp0-fp1 + fmovm.l USER_FPCR(%a6),%fpcr,%fpsr,%fpiar # restore ctrl regs + movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 + + unlk %a6 +#$# add.l &24,%sp + bra.l _fpsp_done + +# overflow is enabled AND overflow, of course, occurred. so, we have the EXOP +# in fp1. now, simply jump to _real_ovfl()! +fovfl_ovfl_on: + fmovm.x &0x40,FP_SRC(%a6) # save EXOP (fp1) to stack + + mov.w &0xe005,2+FP_SRC(%a6) # save exc status + + fmovm.x EXC_FPREGS(%a6),&0xc0 # restore fp0-fp1 + fmovm.l USER_FPCR(%a6),%fpcr,%fpsr,%fpiar # restore ctrl regs + movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 + + frestore FP_SRC(%a6) # do this after fmovm,other fs! + + unlk %a6 + + bra.l _real_ovfl + +# overflow occurred but is disabled. meanwhile, inexact is enabled. Therefore, +# we must jump to real_inex(). +fovfl_inex_on: + + fmovm.x &0x40,FP_SRC(%a6) # save EXOP (fp1) to stack + + mov.b &0xc4,1+EXC_VOFF(%a6) # vector offset = 0xc4 + mov.w &0xe001,2+FP_SRC(%a6) # save exc status + + fmovm.x EXC_FPREGS(%a6),&0xc0 # restore fp0-fp1 + fmovm.l USER_FPCR(%a6),%fpcr,%fpsr,%fpiar # restore ctrl regs + movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 + + frestore FP_SRC(%a6) # do this after fmovm,other fs! + + unlk %a6 + + bra.l _real_inex + +######################################################################## +fovfl_out: + + +#$# mov.l FP_SRC_EX(%a6),TRAP_SRCOP_EX(%a6) +#$# mov.l FP_SRC_HI(%a6),TRAP_SRCOP_HI(%a6) +#$# mov.l FP_SRC_LO(%a6),TRAP_SRCOP_LO(%a6) + +# the src operand is definitely a NORM(!), so tag it as such + mov.b &NORM,STAG(%a6) # set src optype tag + + clr.l %d0 + mov.b FPCR_MODE(%a6),%d0 # pass rnd prec/mode + + and.l &0xffff00ff,USER_FPSR(%a6) # zero all but accured field + + fmov.l &0x0,%fpcr # zero current control regs + fmov.l &0x0,%fpsr + + lea FP_SRC(%a6),%a0 # pass ptr to src operand + + bsr.l fout + + btst &ovfl_bit,FPCR_ENABLE(%a6) + bne.w fovfl_ovfl_on + + btst &inex2_bit,FPCR_ENABLE(%a6) + bne.w fovfl_inex_on + + fmovm.x EXC_FPREGS(%a6),&0xc0 # restore fp0-fp1 + fmovm.l USER_FPCR(%a6),%fpcr,%fpsr,%fpiar # restore ctrl regs + movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 + + unlk %a6 +#$# add.l &24,%sp + + btst &0x7,(%sp) # is trace on? + beq.l _fpsp_done # no + + fmov.l %fpiar,0x8(%sp) # "Current PC" is in FPIAR + mov.w &0x2024,0x6(%sp) # stk fmt = 0x2; voff = 0x024 + bra.l _real_trace + +######################################################################### +# XDEF **************************************************************** # +# _fpsp_unfl(): 060FPSP entry point for FP Underflow exception. # +# # +# This handler should be the first code executed upon taking the # +# FP Underflow exception in an operating system. # +# # +# XREF **************************************************************** # +# _imem_read_long() - read instruction longword # +# fix_skewed_ops() - adjust src operand in fsave frame # +# set_tag_x() - determine optype of src/dst operands # +# store_fpreg() - store opclass 0 or 2 result to FP regfile # +# unnorm_fix() - change UNNORM operands to NORM or ZERO # +# load_fpn2() - load dst operand from FP regfile # +# fout() - emulate an opclass 3 instruction # +# tbl_unsupp - add of table of emulation routines for opclass 0,2 # +# _fpsp_done() - "callout" for 060FPSP exit (all work done!) # +# _real_ovfl() - "callout" for Overflow exception enabled code # +# _real_inex() - "callout" for Inexact exception enabled code # +# _real_trace() - "callout" for Trace exception code # +# # +# INPUT *************************************************************** # +# - The system stack contains the FP Unfl exception stack frame # +# - The fsave frame contains the source operand # +# # +# OUTPUT ************************************************************** # +# Underflow Exception enabled: # +# - The system stack is unchanged # +# - The fsave frame contains the adjusted src op for opclass 0,2 # +# Underflow Exception disabled: # +# - The system stack is unchanged # +# - The "exception present" flag in the fsave frame is cleared # +# # +# ALGORITHM *********************************************************** # +# On the 060, if an FP underflow is present as the result of any # +# instruction, the 060 will take an underflow exception whether the # +# exception is enabled or disabled in the FPCR. For the disabled case, # +# This handler emulates the instruction to determine what the correct # +# default result should be for the operation. This default result is # +# then stored in either the FP regfile, data regfile, or memory. # +# Finally, the handler exits through the "callout" _fpsp_done() # +# denoting that no exceptional conditions exist within the machine. # +# If the exception is enabled, then this handler must create the # +# exceptional operand and plave it in the fsave state frame, and store # +# the default result (only if the instruction is opclass 3). For # +# exceptions enabled, this handler must exit through the "callout" # +# _real_unfl() so that the operating system enabled overflow handler # +# can handle this case. # +# Two other conditions exist. First, if underflow was disabled # +# but the inexact exception was enabled and the result was inexact, # +# this handler must exit through the "callout" _real_inex(). # +# was inexact. # +# Also, in the case of an opclass three instruction where # +# underflow was disabled and the trace exception was enabled, this # +# handler must exit through the "callout" _real_trace(). # +# # +######################################################################### + + global _fpsp_unfl +_fpsp_unfl: + +#$# sub.l &24,%sp # make room for src/dst + + link.w %a6,&-LOCAL_SIZE # init stack frame + + fsave FP_SRC(%a6) # grab the "busy" frame + + movm.l &0x0303,EXC_DREGS(%a6) # save d0-d1/a0-a1 + fmovm.l %fpcr,%fpsr,%fpiar,USER_FPCR(%a6) # save ctrl regs + fmovm.x &0xc0,EXC_FPREGS(%a6) # save fp0-fp1 on stack + +# the FPIAR holds the "current PC" of the faulting instruction + mov.l USER_FPIAR(%a6),EXC_EXTWPTR(%a6) + mov.l EXC_EXTWPTR(%a6),%a0 # fetch instruction addr + addq.l &0x4,EXC_EXTWPTR(%a6) # incr instruction ptr + bsr.l _imem_read_long # fetch the instruction words + mov.l %d0,EXC_OPWORD(%a6) + +############################################################################## + + btst &0x5,EXC_CMDREG(%a6) # is instr an fmove out? + bne.w funfl_out + + + lea FP_SRC(%a6),%a0 # pass: ptr to src op + bsr.l fix_skewed_ops # fix src op + + lea FP_SRC(%a6),%a0 # pass: ptr to src op + bsr.l set_tag_x # tag the operand type + mov.b %d0,STAG(%a6) # maybe NORM,DENORM + +# bit five of the fp ext word separates the monadic and dyadic operations +# that can pass through fpsp_unfl(). remember that fcmp, and ftst +# will never take this exception. + btst &0x5,1+EXC_CMDREG(%a6) # is op monadic or dyadic? + beq.b funfl_extract # monadic + +# now, what's left that's not dyadic is fsincos. we can distinguish it +# from all dyadics by the '0110xxx pattern + btst &0x4,1+EXC_CMDREG(%a6) # is op an fsincos? + bne.b funfl_extract # yes + + bfextu EXC_CMDREG(%a6){&6:&3},%d0 # dyadic; load dst reg + bsr.l load_fpn2 # load dst into FP_DST + + lea FP_DST(%a6),%a0 # pass: ptr to dst op + bsr.l set_tag_x # tag the operand type + cmpi.b %d0,&UNNORM # is operand an UNNORM? + bne.b funfl_op2_done # no + bsr.l unnorm_fix # yes; convert to NORM,DENORM,or ZERO +funfl_op2_done: + mov.b %d0,DTAG(%a6) # save dst optype tag + +funfl_extract: + +#$# mov.l FP_SRC_EX(%a6),TRAP_SRCOP_EX(%a6) +#$# mov.l FP_SRC_HI(%a6),TRAP_SRCOP_HI(%a6) +#$# mov.l FP_SRC_LO(%a6),TRAP_SRCOP_LO(%a6) +#$# mov.l FP_DST_EX(%a6),TRAP_DSTOP_EX(%a6) +#$# mov.l FP_DST_HI(%a6),TRAP_DSTOP_HI(%a6) +#$# mov.l FP_DST_LO(%a6),TRAP_DSTOP_LO(%a6) + + clr.l %d0 + mov.b FPCR_MODE(%a6),%d0 # pass rnd prec/mode + + mov.b 1+EXC_CMDREG(%a6),%d1 + andi.w &0x007f,%d1 # extract extension + + andi.l &0x00ff01ff,USER_FPSR(%a6) + + fmov.l &0x0,%fpcr # zero current control regs + fmov.l &0x0,%fpsr + + lea FP_SRC(%a6),%a0 + lea FP_DST(%a6),%a1 + +# maybe we can make these entry points ONLY the OVFL entry points of each routine. + mov.l (tbl_unsupp.l,%pc,%d1.w*4),%d1 # fetch routine addr + jsr (tbl_unsupp.l,%pc,%d1.l*1) + + bfextu EXC_CMDREG(%a6){&6:&3},%d0 + bsr.l store_fpreg + +# The `060 FPU multiplier hardware is such that if the result of a +# multiply operation is the smallest possible normalized number +# (0x00000000_80000000_00000000), then the machine will take an +# underflow exception. Since this is incorrect, we need to check +# if our emulation, after re-doing the operation, decided that +# no underflow was called for. We do these checks only in +# funfl_{unfl,inex}_on() because w/ both exceptions disabled, this +# special case will simply exit gracefully with the correct result. + +# the exceptional possibilities we have left ourselves with are ONLY overflow +# and inexact. and, the inexact is such that overflow occurred and was disabled +# but inexact was enabled. + btst &unfl_bit,FPCR_ENABLE(%a6) + bne.b funfl_unfl_on + +funfl_chkinex: + btst &inex2_bit,FPCR_ENABLE(%a6) + bne.b funfl_inex_on + +funfl_exit: + fmovm.x EXC_FPREGS(%a6),&0xc0 # restore fp0-fp1 + fmovm.l USER_FPCR(%a6),%fpcr,%fpsr,%fpiar # restore ctrl regs + movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 + + unlk %a6 +#$# add.l &24,%sp + bra.l _fpsp_done + +# overflow is enabled AND overflow, of course, occurred. so, we have the EXOP +# in fp1 (don't forget to save fp0). what to do now? +# well, we simply have to get to go to _real_unfl()! +funfl_unfl_on: + +# The `060 FPU multiplier hardware is such that if the result of a +# multiply operation is the smallest possible normalized number +# (0x00000000_80000000_00000000), then the machine will take an +# underflow exception. Since this is incorrect, we check here to see +# if our emulation, after re-doing the operation, decided that +# no underflow was called for. + btst &unfl_bit,FPSR_EXCEPT(%a6) + beq.w funfl_chkinex + +funfl_unfl_on2: + fmovm.x &0x40,FP_SRC(%a6) # save EXOP (fp1) to stack + + mov.w &0xe003,2+FP_SRC(%a6) # save exc status + + fmovm.x EXC_FPREGS(%a6),&0xc0 # restore fp0-fp1 + fmovm.l USER_FPCR(%a6),%fpcr,%fpsr,%fpiar # restore ctrl regs + movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 + + frestore FP_SRC(%a6) # do this after fmovm,other fs! + + unlk %a6 + + bra.l _real_unfl + +# underflow occurred but is disabled. meanwhile, inexact is enabled. Therefore, +# we must jump to real_inex(). +funfl_inex_on: + +# The `060 FPU multiplier hardware is such that if the result of a +# multiply operation is the smallest possible normalized number +# (0x00000000_80000000_00000000), then the machine will take an +# underflow exception. +# But, whether bogus or not, if inexact is enabled AND it occurred, +# then we have to branch to real_inex. + + btst &inex2_bit,FPSR_EXCEPT(%a6) + beq.w funfl_exit + +funfl_inex_on2: + + fmovm.x &0x40,FP_SRC(%a6) # save EXOP to stack + + mov.b &0xc4,1+EXC_VOFF(%a6) # vector offset = 0xc4 + mov.w &0xe001,2+FP_SRC(%a6) # save exc status + + fmovm.x EXC_FPREGS(%a6),&0xc0 # restore fp0-fp1 + fmovm.l USER_FPCR(%a6),%fpcr,%fpsr,%fpiar # restore ctrl regs + movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 + + frestore FP_SRC(%a6) # do this after fmovm,other fs! + + unlk %a6 + + bra.l _real_inex + +####################################################################### +funfl_out: + + +#$# mov.l FP_SRC_EX(%a6),TRAP_SRCOP_EX(%a6) +#$# mov.l FP_SRC_HI(%a6),TRAP_SRCOP_HI(%a6) +#$# mov.l FP_SRC_LO(%a6),TRAP_SRCOP_LO(%a6) + +# the src operand is definitely a NORM(!), so tag it as such + mov.b &NORM,STAG(%a6) # set src optype tag + + clr.l %d0 + mov.b FPCR_MODE(%a6),%d0 # pass rnd prec/mode + + and.l &0xffff00ff,USER_FPSR(%a6) # zero all but accured field + + fmov.l &0x0,%fpcr # zero current control regs + fmov.l &0x0,%fpsr + + lea FP_SRC(%a6),%a0 # pass ptr to src operand + + bsr.l fout + + btst &unfl_bit,FPCR_ENABLE(%a6) + bne.w funfl_unfl_on2 + + btst &inex2_bit,FPCR_ENABLE(%a6) + bne.w funfl_inex_on2 + + fmovm.x EXC_FPREGS(%a6),&0xc0 # restore fp0-fp1 + fmovm.l USER_FPCR(%a6),%fpcr,%fpsr,%fpiar # restore ctrl regs + movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 + + unlk %a6 +#$# add.l &24,%sp + + btst &0x7,(%sp) # is trace on? + beq.l _fpsp_done # no + + fmov.l %fpiar,0x8(%sp) # "Current PC" is in FPIAR + mov.w &0x2024,0x6(%sp) # stk fmt = 0x2; voff = 0x024 + bra.l _real_trace + +######################################################################### +# XDEF **************************************************************** # +# _fpsp_unsupp(): 060FPSP entry point for FP "Unimplemented # +# Data Type" exception. # +# # +# This handler should be the first code executed upon taking the # +# FP Unimplemented Data Type exception in an operating system. # +# # +# XREF **************************************************************** # +# _imem_read_{word,long}() - read instruction word/longword # +# fix_skewed_ops() - adjust src operand in fsave frame # +# set_tag_x() - determine optype of src/dst operands # +# store_fpreg() - store opclass 0 or 2 result to FP regfile # +# unnorm_fix() - change UNNORM operands to NORM or ZERO # +# load_fpn2() - load dst operand from FP regfile # +# load_fpn1() - load src operand from FP regfile # +# fout() - emulate an opclass 3 instruction # +# tbl_unsupp - add of table of emulation routines for opclass 0,2 # +# _real_inex() - "callout" to operating system inexact handler # +# _fpsp_done() - "callout" for exit; work all done # +# _real_trace() - "callout" for Trace enabled exception # +# funimp_skew() - adjust fsave src ops to "incorrect" value # +# _real_snan() - "callout" for SNAN exception # +# _real_operr() - "callout" for OPERR exception # +# _real_ovfl() - "callout" for OVFL exception # +# _real_unfl() - "callout" for UNFL exception # +# get_packed() - fetch packed operand from memory # +# # +# INPUT *************************************************************** # +# - The system stack contains the "Unimp Data Type" stk frame # +# - The fsave frame contains the ssrc op (for UNNORM/DENORM) # +# # +# OUTPUT ************************************************************** # +# If Inexact exception (opclass 3): # +# - The system stack is changed to an Inexact exception stk frame # +# If SNAN exception (opclass 3): # +# - The system stack is changed to an SNAN exception stk frame # +# If OPERR exception (opclass 3): # +# - The system stack is changed to an OPERR exception stk frame # +# If OVFL exception (opclass 3): # +# - The system stack is changed to an OVFL exception stk frame # +# If UNFL exception (opclass 3): # +# - The system stack is changed to an UNFL exception stack frame # +# If Trace exception enabled: # +# - The system stack is changed to a Trace exception stack frame # +# Else: (normal case) # +# - Correct result has been stored as appropriate # +# # +# ALGORITHM *********************************************************** # +# Two main instruction types can enter here: (1) DENORM or UNNORM # +# unimplemented data types. These can be either opclass 0,2 or 3 # +# instructions, and (2) PACKED unimplemented data format instructions # +# also of opclasses 0,2, or 3. # +# For UNNORM/DENORM opclass 0 and 2, the handler fetches the src # +# operand from the fsave state frame and the dst operand (if dyadic) # +# from the FP register file. The instruction is then emulated by # +# choosing an emulation routine from a table of routines indexed by # +# instruction type. Once the instruction has been emulated and result # +# saved, then we check to see if any enabled exceptions resulted from # +# instruction emulation. If none, then we exit through the "callout" # +# _fpsp_done(). If there is an enabled FP exception, then we insert # +# this exception into the FPU in the fsave state frame and then exit # +# through _fpsp_done(). # +# PACKED opclass 0 and 2 is similar in how the instruction is # +# emulated and exceptions handled. The differences occur in how the # +# handler loads the packed op (by calling get_packed() routine) and # +# by the fact that a Trace exception could be pending for PACKED ops. # +# If a Trace exception is pending, then the current exception stack # +# frame is changed to a Trace exception stack frame and an exit is # +# made through _real_trace(). # +# For UNNORM/DENORM opclass 3, the actual move out to memory is # +# performed by calling the routine fout(). If no exception should occur # +# as the result of emulation, then an exit either occurs through # +# _fpsp_done() or through _real_trace() if a Trace exception is pending # +# (a Trace stack frame must be created here, too). If an FP exception # +# should occur, then we must create an exception stack frame of that # +# type and jump to either _real_snan(), _real_operr(), _real_inex(), # +# _real_unfl(), or _real_ovfl() as appropriate. PACKED opclass 3 # +# emulation is performed in a similar manner. # +# # +######################################################################### + +# +# (1) DENORM and UNNORM (unimplemented) data types: +# +# post-instruction +# ***************** +# * EA * +# pre-instruction * * +# ***************** ***************** +# * 0x0 * 0x0dc * * 0x3 * 0x0dc * +# ***************** ***************** +# * Next * * Next * +# * PC * * PC * +# ***************** ***************** +# * SR * * SR * +# ***************** ***************** +# +# (2) PACKED format (unsupported) opclasses two and three: +# ***************** +# * EA * +# * * +# ***************** +# * 0x2 * 0x0dc * +# ***************** +# * Next * +# * PC * +# ***************** +# * SR * +# ***************** +# + global _fpsp_unsupp +_fpsp_unsupp: + + link.w %a6,&-LOCAL_SIZE # init stack frame + + fsave FP_SRC(%a6) # save fp state + + movm.l &0x0303,EXC_DREGS(%a6) # save d0-d1/a0-a1 + fmovm.l %fpcr,%fpsr,%fpiar,USER_FPCR(%a6) # save ctrl regs + fmovm.x &0xc0,EXC_FPREGS(%a6) # save fp0-fp1 on stack + + btst &0x5,EXC_SR(%a6) # user or supervisor mode? + bne.b fu_s +fu_u: + mov.l %usp,%a0 # fetch user stack pointer + mov.l %a0,EXC_A7(%a6) # save on stack + bra.b fu_cont +# if the exception is an opclass zero or two unimplemented data type +# exception, then the a7' calculated here is wrong since it doesn't +# stack an ea. however, we don't need an a7' for this case anyways. +fu_s: + lea 0x4+EXC_EA(%a6),%a0 # load old a7' + mov.l %a0,EXC_A7(%a6) # save on stack + +fu_cont: + +# the FPIAR holds the "current PC" of the faulting instruction +# the FPIAR should be set correctly for ALL exceptions passing through +# this point. + mov.l USER_FPIAR(%a6),EXC_EXTWPTR(%a6) + mov.l EXC_EXTWPTR(%a6),%a0 # fetch instruction addr + addq.l &0x4,EXC_EXTWPTR(%a6) # incr instruction ptr + bsr.l _imem_read_long # fetch the instruction words + mov.l %d0,EXC_OPWORD(%a6) # store OPWORD and EXTWORD + +############################ + + clr.b SPCOND_FLG(%a6) # clear special condition flag + +# Separate opclass three (fpn-to-mem) ops since they have a different +# stack frame and protocol. + btst &0x5,EXC_CMDREG(%a6) # is it an fmove out? + bne.w fu_out # yes + +# Separate packed opclass two instructions. + bfextu EXC_CMDREG(%a6){&0:&6},%d0 + cmpi.b %d0,&0x13 + beq.w fu_in_pack + + +# I'm not sure at this point what FPSR bits are valid for this instruction. +# so, since the emulation routines re-create them anyways, zero exception field + andi.l &0x00ff00ff,USER_FPSR(%a6) # zero exception field + + fmov.l &0x0,%fpcr # zero current control regs + fmov.l &0x0,%fpsr + +# Opclass two w/ memory-to-fpn operation will have an incorrect extended +# precision format if the src format was single or double and the +# source data type was an INF, NAN, DENORM, or UNNORM + lea FP_SRC(%a6),%a0 # pass ptr to input + bsr.l fix_skewed_ops + +# we don't know whether the src operand or the dst operand (or both) is the +# UNNORM or DENORM. call the function that tags the operand type. if the +# input is an UNNORM, then convert it to a NORM, DENORM, or ZERO. + lea FP_SRC(%a6),%a0 # pass: ptr to src op + bsr.l set_tag_x # tag the operand type + cmpi.b %d0,&UNNORM # is operand an UNNORM? + bne.b fu_op2 # no + bsr.l unnorm_fix # yes; convert to NORM,DENORM,or ZERO + +fu_op2: + mov.b %d0,STAG(%a6) # save src optype tag + + bfextu EXC_CMDREG(%a6){&6:&3},%d0 # dyadic; load dst reg + +# bit five of the fp extension word separates the monadic and dyadic operations +# at this point + btst &0x5,1+EXC_CMDREG(%a6) # is operation monadic or dyadic? + beq.b fu_extract # monadic + cmpi.b 1+EXC_CMDREG(%a6),&0x3a # is operation an ftst? + beq.b fu_extract # yes, so it's monadic, too + + bsr.l load_fpn2 # load dst into FP_DST + + lea FP_DST(%a6),%a0 # pass: ptr to dst op + bsr.l set_tag_x # tag the operand type + cmpi.b %d0,&UNNORM # is operand an UNNORM? + bne.b fu_op2_done # no + bsr.l unnorm_fix # yes; convert to NORM,DENORM,or ZERO +fu_op2_done: + mov.b %d0,DTAG(%a6) # save dst optype tag + +fu_extract: + clr.l %d0 + mov.b FPCR_MODE(%a6),%d0 # fetch rnd mode/prec + + bfextu 1+EXC_CMDREG(%a6){&1:&7},%d1 # extract extension + + lea FP_SRC(%a6),%a0 + lea FP_DST(%a6),%a1 + + mov.l (tbl_unsupp.l,%pc,%d1.l*4),%d1 # fetch routine addr + jsr (tbl_unsupp.l,%pc,%d1.l*1) + +# +# Exceptions in order of precedence: +# BSUN : none +# SNAN : all dyadic ops +# OPERR : fsqrt(-NORM) +# OVFL : all except ftst,fcmp +# UNFL : all except ftst,fcmp +# DZ : fdiv +# INEX2 : all except ftst,fcmp +# INEX1 : none (packed doesn't go through here) +# + +# we determine the highest priority exception(if any) set by the +# emulation routine that has also been enabled by the user. + mov.b FPCR_ENABLE(%a6),%d0 # fetch exceptions set + bne.b fu_in_ena # some are enabled + +fu_in_cont: +# fcmp and ftst do not store any result. + mov.b 1+EXC_CMDREG(%a6),%d0 # fetch extension + andi.b &0x38,%d0 # extract bits 3-5 + cmpi.b %d0,&0x38 # is instr fcmp or ftst? + beq.b fu_in_exit # yes + + bfextu EXC_CMDREG(%a6){&6:&3},%d0 # dyadic; load dst reg + bsr.l store_fpreg # store the result + +fu_in_exit: + + fmovm.x EXC_FPREGS(%a6),&0xc0 # restore fp0/fp1 + fmovm.l USER_FPCR(%a6),%fpcr,%fpsr,%fpiar # restore ctrl regs + movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 + + unlk %a6 + + bra.l _fpsp_done + +fu_in_ena: + and.b FPSR_EXCEPT(%a6),%d0 # keep only ones enabled + bfffo %d0{&24:&8},%d0 # find highest priority exception + bne.b fu_in_exc # there is at least one set + +# +# No exceptions occurred that were also enabled. Now: +# +# if (OVFL && ovfl_disabled && inexact_enabled) { +# branch to _real_inex() (even if the result was exact!); +# } else { +# save the result in the proper fp reg (unless the op is fcmp or ftst); +# return; +# } +# + btst &ovfl_bit,FPSR_EXCEPT(%a6) # was overflow set? + beq.b fu_in_cont # no + +fu_in_ovflchk: + btst &inex2_bit,FPCR_ENABLE(%a6) # was inexact enabled? + beq.b fu_in_cont # no + bra.w fu_in_exc_ovfl # go insert overflow frame + +# +# An exception occurred and that exception was enabled: +# +# shift enabled exception field into lo byte of d0; +# if (((INEX2 || INEX1) && inex_enabled && OVFL && ovfl_disabled) || +# ((INEX2 || INEX1) && inex_enabled && UNFL && unfl_disabled)) { +# /* +# * this is the case where we must call _real_inex() now or else +# * there will be no other way to pass it the exceptional operand +# */ +# call _real_inex(); +# } else { +# restore exc state (SNAN||OPERR||OVFL||UNFL||DZ||INEX) into the FPU; +# } +# +fu_in_exc: + subi.l &24,%d0 # fix offset to be 0-8 + cmpi.b %d0,&0x6 # is exception INEX? (6) + bne.b fu_in_exc_exit # no + +# the enabled exception was inexact + btst &unfl_bit,FPSR_EXCEPT(%a6) # did disabled underflow occur? + bne.w fu_in_exc_unfl # yes + btst &ovfl_bit,FPSR_EXCEPT(%a6) # did disabled overflow occur? + bne.w fu_in_exc_ovfl # yes + +# here, we insert the correct fsave status value into the fsave frame for the +# corresponding exception. the operand in the fsave frame should be the original +# src operand. +fu_in_exc_exit: + mov.l %d0,-(%sp) # save d0 + bsr.l funimp_skew # skew sgl or dbl inputs + mov.l (%sp)+,%d0 # restore d0 + + mov.w (tbl_except.b,%pc,%d0.w*2),2+FP_SRC(%a6) # create exc status + + fmovm.x EXC_FPREGS(%a6),&0xc0 # restore fp0/fp1 + fmovm.l USER_FPCR(%a6),%fpcr,%fpsr,%fpiar # restore ctrl regs + movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 + + frestore FP_SRC(%a6) # restore src op + + unlk %a6 + + bra.l _fpsp_done + +tbl_except: + short 0xe000,0xe006,0xe004,0xe005 + short 0xe003,0xe002,0xe001,0xe001 + +fu_in_exc_unfl: + mov.w &0x4,%d0 + bra.b fu_in_exc_exit +fu_in_exc_ovfl: + mov.w &0x03,%d0 + bra.b fu_in_exc_exit + +# If the input operand to this operation was opclass two and a single +# or double precision denorm, inf, or nan, the operand needs to be +# "corrected" in order to have the proper equivalent extended precision +# number. + global fix_skewed_ops +fix_skewed_ops: + bfextu EXC_CMDREG(%a6){&0:&6},%d0 # extract opclass,src fmt + cmpi.b %d0,&0x11 # is class = 2 & fmt = sgl? + beq.b fso_sgl # yes + cmpi.b %d0,&0x15 # is class = 2 & fmt = dbl? + beq.b fso_dbl # yes + rts # no + +fso_sgl: + mov.w LOCAL_EX(%a0),%d0 # fetch src exponent + andi.w &0x7fff,%d0 # strip sign + cmpi.w %d0,&0x3f80 # is |exp| == $3f80? + beq.b fso_sgl_dnrm_zero # yes + cmpi.w %d0,&0x407f # no; is |exp| == $407f? + beq.b fso_infnan # yes + rts # no + +fso_sgl_dnrm_zero: + andi.l &0x7fffffff,LOCAL_HI(%a0) # clear j-bit + beq.b fso_zero # it's a skewed zero +fso_sgl_dnrm: +# here, we count on norm not to alter a0... + bsr.l norm # normalize mantissa + neg.w %d0 # -shft amt + addi.w &0x3f81,%d0 # adjust new exponent + andi.w &0x8000,LOCAL_EX(%a0) # clear old exponent + or.w %d0,LOCAL_EX(%a0) # insert new exponent + rts + +fso_zero: + andi.w &0x8000,LOCAL_EX(%a0) # clear bogus exponent + rts + +fso_infnan: + andi.b &0x7f,LOCAL_HI(%a0) # clear j-bit + ori.w &0x7fff,LOCAL_EX(%a0) # make exponent = $7fff + rts + +fso_dbl: + mov.w LOCAL_EX(%a0),%d0 # fetch src exponent + andi.w &0x7fff,%d0 # strip sign + cmpi.w %d0,&0x3c00 # is |exp| == $3c00? + beq.b fso_dbl_dnrm_zero # yes + cmpi.w %d0,&0x43ff # no; is |exp| == $43ff? + beq.b fso_infnan # yes + rts # no + +fso_dbl_dnrm_zero: + andi.l &0x7fffffff,LOCAL_HI(%a0) # clear j-bit + bne.b fso_dbl_dnrm # it's a skewed denorm + tst.l LOCAL_LO(%a0) # is it a zero? + beq.b fso_zero # yes +fso_dbl_dnrm: +# here, we count on norm not to alter a0... + bsr.l norm # normalize mantissa + neg.w %d0 # -shft amt + addi.w &0x3c01,%d0 # adjust new exponent + andi.w &0x8000,LOCAL_EX(%a0) # clear old exponent + or.w %d0,LOCAL_EX(%a0) # insert new exponent + rts + +################################################################# + +# fmove out took an unimplemented data type exception. +# the src operand is in FP_SRC. Call _fout() to write out the result and +# to determine which exceptions, if any, to take. +fu_out: + +# Separate packed move outs from the UNNORM and DENORM move outs. + bfextu EXC_CMDREG(%a6){&3:&3},%d0 + cmpi.b %d0,&0x3 + beq.w fu_out_pack + cmpi.b %d0,&0x7 + beq.w fu_out_pack + + +# I'm not sure at this point what FPSR bits are valid for this instruction. +# so, since the emulation routines re-create them anyways, zero exception field. +# fmove out doesn't affect ccodes. + and.l &0xffff00ff,USER_FPSR(%a6) # zero exception field + + fmov.l &0x0,%fpcr # zero current control regs + fmov.l &0x0,%fpsr + +# the src can ONLY be a DENORM or an UNNORM! so, don't make any big subroutine +# call here. just figure out what it is... + mov.w FP_SRC_EX(%a6),%d0 # get exponent + andi.w &0x7fff,%d0 # strip sign + beq.b fu_out_denorm # it's a DENORM + + lea FP_SRC(%a6),%a0 + bsr.l unnorm_fix # yes; fix it + + mov.b %d0,STAG(%a6) + + bra.b fu_out_cont +fu_out_denorm: + mov.b &DENORM,STAG(%a6) +fu_out_cont: + + clr.l %d0 + mov.b FPCR_MODE(%a6),%d0 # fetch rnd mode/prec + + lea FP_SRC(%a6),%a0 # pass ptr to src operand + + mov.l (%a6),EXC_A6(%a6) # in case a6 changes + bsr.l fout # call fmove out routine + +# Exceptions in order of precedence: +# BSUN : none +# SNAN : none +# OPERR : fmove.{b,w,l} out of large UNNORM +# OVFL : fmove.{s,d} +# UNFL : fmove.{s,d,x} +# DZ : none +# INEX2 : all +# INEX1 : none (packed doesn't travel through here) + +# determine the highest priority exception(if any) set by the +# emulation routine that has also been enabled by the user. + mov.b FPCR_ENABLE(%a6),%d0 # fetch exceptions enabled + bne.w fu_out_ena # some are enabled + +fu_out_done: + + mov.l EXC_A6(%a6),(%a6) # in case a6 changed + +# on extended precision opclass three instructions using pre-decrement or +# post-increment addressing mode, the address register is not updated. is the +# address register was the stack pointer used from user mode, then let's update +# it here. if it was used from supervisor mode, then we have to handle this +# as a special case. + btst &0x5,EXC_SR(%a6) + bne.b fu_out_done_s + + mov.l EXC_A7(%a6),%a0 # restore a7 + mov.l %a0,%usp + +fu_out_done_cont: + fmovm.x EXC_FPREGS(%a6),&0xc0 # restore fp0/fp1 + fmovm.l USER_FPCR(%a6),%fpcr,%fpsr,%fpiar # restore ctrl regs + movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 + + unlk %a6 + + btst &0x7,(%sp) # is trace on? + bne.b fu_out_trace # yes + + bra.l _fpsp_done + +# is the ea mode pre-decrement of the stack pointer from supervisor mode? +# ("fmov.x fpm,-(a7)") if so, +fu_out_done_s: + cmpi.b SPCOND_FLG(%a6),&mda7_flg + bne.b fu_out_done_cont + +# the extended precision result is still in fp0. but, we need to save it +# somewhere on the stack until we can copy it to its final resting place. +# here, we're counting on the top of the stack to be the old place-holders +# for fp0/fp1 which have already been restored. that way, we can write +# over those destinations with the shifted stack frame. + fmovm.x &0x80,FP_SRC(%a6) # put answer on stack + + fmovm.x EXC_FPREGS(%a6),&0xc0 # restore fp0/fp1 + fmovm.l USER_FPCR(%a6),%fpcr,%fpsr,%fpiar # restore ctrl regs + movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 + + mov.l (%a6),%a6 # restore frame pointer + + mov.l LOCAL_SIZE+EXC_SR(%sp),LOCAL_SIZE+EXC_SR-0xc(%sp) + mov.l LOCAL_SIZE+2+EXC_PC(%sp),LOCAL_SIZE+2+EXC_PC-0xc(%sp) + +# now, copy the result to the proper place on the stack + mov.l LOCAL_SIZE+FP_SRC_EX(%sp),LOCAL_SIZE+EXC_SR+0x0(%sp) + mov.l LOCAL_SIZE+FP_SRC_HI(%sp),LOCAL_SIZE+EXC_SR+0x4(%sp) + mov.l LOCAL_SIZE+FP_SRC_LO(%sp),LOCAL_SIZE+EXC_SR+0x8(%sp) + + add.l &LOCAL_SIZE-0x8,%sp + + btst &0x7,(%sp) + bne.b fu_out_trace + + bra.l _fpsp_done + +fu_out_ena: + and.b FPSR_EXCEPT(%a6),%d0 # keep only ones enabled + bfffo %d0{&24:&8},%d0 # find highest priority exception + bne.b fu_out_exc # there is at least one set + +# no exceptions were set. +# if a disabled overflow occurred and inexact was enabled but the result +# was exact, then a branch to _real_inex() is made. + btst &ovfl_bit,FPSR_EXCEPT(%a6) # was overflow set? + beq.w fu_out_done # no + +fu_out_ovflchk: + btst &inex2_bit,FPCR_ENABLE(%a6) # was inexact enabled? + beq.w fu_out_done # no + bra.w fu_inex # yes + +# +# The fp move out that took the "Unimplemented Data Type" exception was +# being traced. Since the stack frames are similar, get the "current" PC +# from FPIAR and put it in the trace stack frame then jump to _real_trace(). +# +# UNSUPP FRAME TRACE FRAME +# ***************** ***************** +# * EA * * Current * +# * * * PC * +# ***************** ***************** +# * 0x3 * 0x0dc * * 0x2 * 0x024 * +# ***************** ***************** +# * Next * * Next * +# * PC * * PC * +# ***************** ***************** +# * SR * * SR * +# ***************** ***************** +# +fu_out_trace: + mov.w &0x2024,0x6(%sp) + fmov.l %fpiar,0x8(%sp) + bra.l _real_trace + +# an exception occurred and that exception was enabled. +fu_out_exc: + subi.l &24,%d0 # fix offset to be 0-8 + +# we don't mess with the existing fsave frame. just re-insert it and +# jump to the "_real_{}()" handler... + mov.w (tbl_fu_out.b,%pc,%d0.w*2),%d0 + jmp (tbl_fu_out.b,%pc,%d0.w*1) + + swbeg &0x8 +tbl_fu_out: + short tbl_fu_out - tbl_fu_out # BSUN can't happen + short tbl_fu_out - tbl_fu_out # SNAN can't happen + short fu_operr - tbl_fu_out # OPERR + short fu_ovfl - tbl_fu_out # OVFL + short fu_unfl - tbl_fu_out # UNFL + short tbl_fu_out - tbl_fu_out # DZ can't happen + short fu_inex - tbl_fu_out # INEX2 + short tbl_fu_out - tbl_fu_out # INEX1 won't make it here + +# for snan,operr,ovfl,unfl, src op is still in FP_SRC so just +# frestore it. +fu_snan: + fmovm.x EXC_FPREGS(%a6),&0xc0 # restore fp0/fp1 + fmovm.l USER_FPCR(%a6),%fpcr,%fpsr,%fpiar # restore ctrl regs + movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 + + mov.w &0x30d8,EXC_VOFF(%a6) # vector offset = 0xd8 + mov.w &0xe006,2+FP_SRC(%a6) + + frestore FP_SRC(%a6) + + unlk %a6 + + + bra.l _real_snan + +fu_operr: + fmovm.x EXC_FPREGS(%a6),&0xc0 # restore fp0/fp1 + fmovm.l USER_FPCR(%a6),%fpcr,%fpsr,%fpiar # restore ctrl regs + movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 + + mov.w &0x30d0,EXC_VOFF(%a6) # vector offset = 0xd0 + mov.w &0xe004,2+FP_SRC(%a6) + + frestore FP_SRC(%a6) + + unlk %a6 + + + bra.l _real_operr + +fu_ovfl: + fmovm.x &0x40,FP_SRC(%a6) # save EXOP to the stack + + fmovm.x EXC_FPREGS(%a6),&0xc0 # restore fp0/fp1 + fmovm.l USER_FPCR(%a6),%fpcr,%fpsr,%fpiar # restore ctrl regs + movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 + + mov.w &0x30d4,EXC_VOFF(%a6) # vector offset = 0xd4 + mov.w &0xe005,2+FP_SRC(%a6) + + frestore FP_SRC(%a6) # restore EXOP + + unlk %a6 + + bra.l _real_ovfl + +# underflow can happen for extended precision. extended precision opclass +# three instruction exceptions don't update the stack pointer. so, if the +# exception occurred from user mode, then simply update a7 and exit normally. +# if the exception occurred from supervisor mode, check if +fu_unfl: + mov.l EXC_A6(%a6),(%a6) # restore a6 + + btst &0x5,EXC_SR(%a6) + bne.w fu_unfl_s + + mov.l EXC_A7(%a6),%a0 # restore a7 whether we need + mov.l %a0,%usp # to or not... + +fu_unfl_cont: + fmovm.x &0x40,FP_SRC(%a6) # save EXOP to the stack + + fmovm.x EXC_FPREGS(%a6),&0xc0 # restore fp0/fp1 + fmovm.l USER_FPCR(%a6),%fpcr,%fpsr,%fpiar # restore ctrl regs + movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 + + mov.w &0x30cc,EXC_VOFF(%a6) # vector offset = 0xcc + mov.w &0xe003,2+FP_SRC(%a6) + + frestore FP_SRC(%a6) # restore EXOP + + unlk %a6 + + bra.l _real_unfl + +fu_unfl_s: + cmpi.b SPCOND_FLG(%a6),&mda7_flg # was the mode -(sp)? + bne.b fu_unfl_cont + +# the extended precision result is still in fp0. but, we need to save it +# somewhere on the stack until we can copy it to its final resting place +# (where the exc frame is currently). make sure it's not at the top of the +# frame or it will get overwritten when the exc stack frame is shifted "down". + fmovm.x &0x80,FP_SRC(%a6) # put answer on stack + fmovm.x &0x40,FP_DST(%a6) # put EXOP on stack + + fmovm.x EXC_FPREGS(%a6),&0xc0 # restore fp0/fp1 + fmovm.l USER_FPCR(%a6),%fpcr,%fpsr,%fpiar # restore ctrl regs + movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 + + mov.w &0x30cc,EXC_VOFF(%a6) # vector offset = 0xcc + mov.w &0xe003,2+FP_DST(%a6) + + frestore FP_DST(%a6) # restore EXOP + + mov.l (%a6),%a6 # restore frame pointer + + mov.l LOCAL_SIZE+EXC_SR(%sp),LOCAL_SIZE+EXC_SR-0xc(%sp) + mov.l LOCAL_SIZE+2+EXC_PC(%sp),LOCAL_SIZE+2+EXC_PC-0xc(%sp) + mov.l LOCAL_SIZE+EXC_EA(%sp),LOCAL_SIZE+EXC_EA-0xc(%sp) + +# now, copy the result to the proper place on the stack + mov.l LOCAL_SIZE+FP_SRC_EX(%sp),LOCAL_SIZE+EXC_SR+0x0(%sp) + mov.l LOCAL_SIZE+FP_SRC_HI(%sp),LOCAL_SIZE+EXC_SR+0x4(%sp) + mov.l LOCAL_SIZE+FP_SRC_LO(%sp),LOCAL_SIZE+EXC_SR+0x8(%sp) + + add.l &LOCAL_SIZE-0x8,%sp + + bra.l _real_unfl + +# fmove in and out enter here. +fu_inex: + fmovm.x &0x40,FP_SRC(%a6) # save EXOP to the stack + + fmovm.x EXC_FPREGS(%a6),&0xc0 # restore fp0/fp1 + fmovm.l USER_FPCR(%a6),%fpcr,%fpsr,%fpiar # restore ctrl regs + movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 + + mov.w &0x30c4,EXC_VOFF(%a6) # vector offset = 0xc4 + mov.w &0xe001,2+FP_SRC(%a6) + + frestore FP_SRC(%a6) # restore EXOP + + unlk %a6 + + + bra.l _real_inex + +######################################################################### +######################################################################### +fu_in_pack: + + +# I'm not sure at this point what FPSR bits are valid for this instruction. +# so, since the emulation routines re-create them anyways, zero exception field + andi.l &0x0ff00ff,USER_FPSR(%a6) # zero exception field + + fmov.l &0x0,%fpcr # zero current control regs + fmov.l &0x0,%fpsr + + bsr.l get_packed # fetch packed src operand + + lea FP_SRC(%a6),%a0 # pass ptr to src + bsr.l set_tag_x # set src optype tag + + mov.b %d0,STAG(%a6) # save src optype tag + + bfextu EXC_CMDREG(%a6){&6:&3},%d0 # dyadic; load dst reg + +# bit five of the fp extension word separates the monadic and dyadic operations +# at this point + btst &0x5,1+EXC_CMDREG(%a6) # is operation monadic or dyadic? + beq.b fu_extract_p # monadic + cmpi.b 1+EXC_CMDREG(%a6),&0x3a # is operation an ftst? + beq.b fu_extract_p # yes, so it's monadic, too + + bsr.l load_fpn2 # load dst into FP_DST + + lea FP_DST(%a6),%a0 # pass: ptr to dst op + bsr.l set_tag_x # tag the operand type + cmpi.b %d0,&UNNORM # is operand an UNNORM? + bne.b fu_op2_done_p # no + bsr.l unnorm_fix # yes; convert to NORM,DENORM,or ZERO +fu_op2_done_p: + mov.b %d0,DTAG(%a6) # save dst optype tag + +fu_extract_p: + clr.l %d0 + mov.b FPCR_MODE(%a6),%d0 # fetch rnd mode/prec + + bfextu 1+EXC_CMDREG(%a6){&1:&7},%d1 # extract extension + + lea FP_SRC(%a6),%a0 + lea FP_DST(%a6),%a1 + + mov.l (tbl_unsupp.l,%pc,%d1.l*4),%d1 # fetch routine addr + jsr (tbl_unsupp.l,%pc,%d1.l*1) + +# +# Exceptions in order of precedence: +# BSUN : none +# SNAN : all dyadic ops +# OPERR : fsqrt(-NORM) +# OVFL : all except ftst,fcmp +# UNFL : all except ftst,fcmp +# DZ : fdiv +# INEX2 : all except ftst,fcmp +# INEX1 : all +# + +# we determine the highest priority exception(if any) set by the +# emulation routine that has also been enabled by the user. + mov.b FPCR_ENABLE(%a6),%d0 # fetch exceptions enabled + bne.w fu_in_ena_p # some are enabled + +fu_in_cont_p: +# fcmp and ftst do not store any result. + mov.b 1+EXC_CMDREG(%a6),%d0 # fetch extension + andi.b &0x38,%d0 # extract bits 3-5 + cmpi.b %d0,&0x38 # is instr fcmp or ftst? + beq.b fu_in_exit_p # yes + + bfextu EXC_CMDREG(%a6){&6:&3},%d0 # dyadic; load dst reg + bsr.l store_fpreg # store the result + +fu_in_exit_p: + + btst &0x5,EXC_SR(%a6) # user or supervisor? + bne.w fu_in_exit_s_p # supervisor + + mov.l EXC_A7(%a6),%a0 # update user a7 + mov.l %a0,%usp + +fu_in_exit_cont_p: + fmovm.x EXC_FPREGS(%a6),&0xc0 # restore fp0/fp1 + fmovm.l USER_FPCR(%a6),%fpcr,%fpsr,%fpiar # restore ctrl regs + movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 + + unlk %a6 # unravel stack frame + + btst &0x7,(%sp) # is trace on? + bne.w fu_trace_p # yes + + bra.l _fpsp_done # exit to os + +# the exception occurred in supervisor mode. check to see if the +# addressing mode was (a7)+. if so, we'll need to shift the +# stack frame "up". +fu_in_exit_s_p: + btst &mia7_bit,SPCOND_FLG(%a6) # was ea mode (a7)+ + beq.b fu_in_exit_cont_p # no + + fmovm.x EXC_FPREGS(%a6),&0xc0 # restore fp0/fp1 + fmovm.l USER_FPCR(%a6),%fpcr,%fpsr,%fpiar # restore ctrl regs + movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 + + unlk %a6 # unravel stack frame + +# shift the stack frame "up". we don't really care about the field. + mov.l 0x4(%sp),0x10(%sp) + mov.l 0x0(%sp),0xc(%sp) + add.l &0xc,%sp + + btst &0x7,(%sp) # is trace on? + bne.w fu_trace_p # yes + + bra.l _fpsp_done # exit to os + +fu_in_ena_p: + and.b FPSR_EXCEPT(%a6),%d0 # keep only ones enabled & set + bfffo %d0{&24:&8},%d0 # find highest priority exception + bne.b fu_in_exc_p # at least one was set + +# +# No exceptions occurred that were also enabled. Now: +# +# if (OVFL && ovfl_disabled && inexact_enabled) { +# branch to _real_inex() (even if the result was exact!); +# } else { +# save the result in the proper fp reg (unless the op is fcmp or ftst); +# return; +# } +# + btst &ovfl_bit,FPSR_EXCEPT(%a6) # was overflow set? + beq.w fu_in_cont_p # no + +fu_in_ovflchk_p: + btst &inex2_bit,FPCR_ENABLE(%a6) # was inexact enabled? + beq.w fu_in_cont_p # no + bra.w fu_in_exc_ovfl_p # do _real_inex() now + +# +# An exception occurred and that exception was enabled: +# +# shift enabled exception field into lo byte of d0; +# if (((INEX2 || INEX1) && inex_enabled && OVFL && ovfl_disabled) || +# ((INEX2 || INEX1) && inex_enabled && UNFL && unfl_disabled)) { +# /* +# * this is the case where we must call _real_inex() now or else +# * there will be no other way to pass it the exceptional operand +# */ +# call _real_inex(); +# } else { +# restore exc state (SNAN||OPERR||OVFL||UNFL||DZ||INEX) into the FPU; +# } +# +fu_in_exc_p: + subi.l &24,%d0 # fix offset to be 0-8 + cmpi.b %d0,&0x6 # is exception INEX? (6 or 7) + blt.b fu_in_exc_exit_p # no + +# the enabled exception was inexact + btst &unfl_bit,FPSR_EXCEPT(%a6) # did disabled underflow occur? + bne.w fu_in_exc_unfl_p # yes + btst &ovfl_bit,FPSR_EXCEPT(%a6) # did disabled overflow occur? + bne.w fu_in_exc_ovfl_p # yes + +# here, we insert the correct fsave status value into the fsave frame for the +# corresponding exception. the operand in the fsave frame should be the original +# src operand. +# as a reminder for future predicted pain and agony, we are passing in fsave the +# "non-skewed" operand for cases of sgl and dbl src INFs,NANs, and DENORMs. +# this is INCORRECT for enabled SNAN which would give to the user the skewed SNAN!!! +fu_in_exc_exit_p: + btst &0x5,EXC_SR(%a6) # user or supervisor? + bne.w fu_in_exc_exit_s_p # supervisor + + mov.l EXC_A7(%a6),%a0 # update user a7 + mov.l %a0,%usp + +fu_in_exc_exit_cont_p: + mov.w (tbl_except_p.b,%pc,%d0.w*2),2+FP_SRC(%a6) + + fmovm.x EXC_FPREGS(%a6),&0xc0 # restore fp0/fp1 + fmovm.l USER_FPCR(%a6),%fpcr,%fpsr,%fpiar # restore ctrl regs + movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 + + frestore FP_SRC(%a6) # restore src op + + unlk %a6 + + btst &0x7,(%sp) # is trace enabled? + bne.w fu_trace_p # yes + + bra.l _fpsp_done + +tbl_except_p: + short 0xe000,0xe006,0xe004,0xe005 + short 0xe003,0xe002,0xe001,0xe001 + +fu_in_exc_ovfl_p: + mov.w &0x3,%d0 + bra.w fu_in_exc_exit_p + +fu_in_exc_unfl_p: + mov.w &0x4,%d0 + bra.w fu_in_exc_exit_p + +fu_in_exc_exit_s_p: + btst &mia7_bit,SPCOND_FLG(%a6) + beq.b fu_in_exc_exit_cont_p + + mov.w (tbl_except_p.b,%pc,%d0.w*2),2+FP_SRC(%a6) + + fmovm.x EXC_FPREGS(%a6),&0xc0 # restore fp0/fp1 + fmovm.l USER_FPCR(%a6),%fpcr,%fpsr,%fpiar # restore ctrl regs + movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 + + frestore FP_SRC(%a6) # restore src op + + unlk %a6 # unravel stack frame + +# shift stack frame "up". who cares about field. + mov.l 0x4(%sp),0x10(%sp) + mov.l 0x0(%sp),0xc(%sp) + add.l &0xc,%sp + + btst &0x7,(%sp) # is trace on? + bne.b fu_trace_p # yes + + bra.l _fpsp_done # exit to os + +# +# The opclass two PACKED instruction that took an "Unimplemented Data Type" +# exception was being traced. Make the "current" PC the FPIAR and put it in the +# trace stack frame then jump to _real_trace(). +# +# UNSUPP FRAME TRACE FRAME +# ***************** ***************** +# * EA * * Current * +# * * * PC * +# ***************** ***************** +# * 0x2 * 0x0dc * * 0x2 * 0x024 * +# ***************** ***************** +# * Next * * Next * +# * PC * * PC * +# ***************** ***************** +# * SR * * SR * +# ***************** ***************** +fu_trace_p: + mov.w &0x2024,0x6(%sp) + fmov.l %fpiar,0x8(%sp) + + bra.l _real_trace + +######################################################### +######################################################### +fu_out_pack: + + +# I'm not sure at this point what FPSR bits are valid for this instruction. +# so, since the emulation routines re-create them anyways, zero exception field. +# fmove out doesn't affect ccodes. + and.l &0xffff00ff,USER_FPSR(%a6) # zero exception field + + fmov.l &0x0,%fpcr # zero current control regs + fmov.l &0x0,%fpsr + + bfextu EXC_CMDREG(%a6){&6:&3},%d0 + bsr.l load_fpn1 + +# unlike other opclass 3, unimplemented data type exceptions, packed must be +# able to detect all operand types. + lea FP_SRC(%a6),%a0 + bsr.l set_tag_x # tag the operand type + cmpi.b %d0,&UNNORM # is operand an UNNORM? + bne.b fu_op2_p # no + bsr.l unnorm_fix # yes; convert to NORM,DENORM,or ZERO + +fu_op2_p: + mov.b %d0,STAG(%a6) # save src optype tag + + clr.l %d0 + mov.b FPCR_MODE(%a6),%d0 # fetch rnd mode/prec + + lea FP_SRC(%a6),%a0 # pass ptr to src operand + + mov.l (%a6),EXC_A6(%a6) # in case a6 changes + bsr.l fout # call fmove out routine + +# Exceptions in order of precedence: +# BSUN : no +# SNAN : yes +# OPERR : if ((k_factor > +17) || (dec. exp exceeds 3 digits)) +# OVFL : no +# UNFL : no +# DZ : no +# INEX2 : yes +# INEX1 : no + +# determine the highest priority exception(if any) set by the +# emulation routine that has also been enabled by the user. + mov.b FPCR_ENABLE(%a6),%d0 # fetch exceptions enabled + bne.w fu_out_ena_p # some are enabled + +fu_out_exit_p: + mov.l EXC_A6(%a6),(%a6) # restore a6 + + btst &0x5,EXC_SR(%a6) # user or supervisor? + bne.b fu_out_exit_s_p # supervisor + + mov.l EXC_A7(%a6),%a0 # update user a7 + mov.l %a0,%usp + +fu_out_exit_cont_p: + fmovm.x EXC_FPREGS(%a6),&0xc0 # restore fp0/fp1 + fmovm.l USER_FPCR(%a6),%fpcr,%fpsr,%fpiar # restore ctrl regs + movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 + + unlk %a6 # unravel stack frame + + btst &0x7,(%sp) # is trace on? + bne.w fu_trace_p # yes + + bra.l _fpsp_done # exit to os + +# the exception occurred in supervisor mode. check to see if the +# addressing mode was -(a7). if so, we'll need to shift the +# stack frame "down". +fu_out_exit_s_p: + btst &mda7_bit,SPCOND_FLG(%a6) # was ea mode -(a7) + beq.b fu_out_exit_cont_p # no + + fmovm.x EXC_FPREGS(%a6),&0xc0 # restore fp0/fp1 + fmovm.l USER_FPCR(%a6),%fpcr,%fpsr,%fpiar # restore ctrl regs + movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 + + mov.l (%a6),%a6 # restore frame pointer + + mov.l LOCAL_SIZE+EXC_SR(%sp),LOCAL_SIZE+EXC_SR-0xc(%sp) + mov.l LOCAL_SIZE+2+EXC_PC(%sp),LOCAL_SIZE+2+EXC_PC-0xc(%sp) + +# now, copy the result to the proper place on the stack + mov.l LOCAL_SIZE+FP_DST_EX(%sp),LOCAL_SIZE+EXC_SR+0x0(%sp) + mov.l LOCAL_SIZE+FP_DST_HI(%sp),LOCAL_SIZE+EXC_SR+0x4(%sp) + mov.l LOCAL_SIZE+FP_DST_LO(%sp),LOCAL_SIZE+EXC_SR+0x8(%sp) + + add.l &LOCAL_SIZE-0x8,%sp + + btst &0x7,(%sp) + bne.w fu_trace_p + + bra.l _fpsp_done + +fu_out_ena_p: + and.b FPSR_EXCEPT(%a6),%d0 # keep only ones enabled + bfffo %d0{&24:&8},%d0 # find highest priority exception + beq.w fu_out_exit_p + + mov.l EXC_A6(%a6),(%a6) # restore a6 + +# an exception occurred and that exception was enabled. +# the only exception possible on packed move out are INEX, OPERR, and SNAN. +fu_out_exc_p: + cmpi.b %d0,&0x1a + bgt.w fu_inex_p2 + beq.w fu_operr_p + +fu_snan_p: + btst &0x5,EXC_SR(%a6) + bne.b fu_snan_s_p + + mov.l EXC_A7(%a6),%a0 + mov.l %a0,%usp + bra.w fu_snan + +fu_snan_s_p: + cmpi.b SPCOND_FLG(%a6),&mda7_flg + bne.w fu_snan + +# the instruction was "fmove.p fpn,-(a7)" from supervisor mode. +# the strategy is to move the exception frame "down" 12 bytes. then, we +# can store the default result where the exception frame was. + fmovm.x EXC_FPREGS(%a6),&0xc0 # restore fp0/fp1 + fmovm.l USER_FPCR(%a6),%fpcr,%fpsr,%fpiar # restore ctrl regs + movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 + + mov.w &0x30d8,EXC_VOFF(%a6) # vector offset = 0xd0 + mov.w &0xe006,2+FP_SRC(%a6) # set fsave status + + frestore FP_SRC(%a6) # restore src operand + + mov.l (%a6),%a6 # restore frame pointer + + mov.l LOCAL_SIZE+EXC_SR(%sp),LOCAL_SIZE+EXC_SR-0xc(%sp) + mov.l LOCAL_SIZE+2+EXC_PC(%sp),LOCAL_SIZE+2+EXC_PC-0xc(%sp) + mov.l LOCAL_SIZE+EXC_EA(%sp),LOCAL_SIZE+EXC_EA-0xc(%sp) + +# now, we copy the default result to its proper location + mov.l LOCAL_SIZE+FP_DST_EX(%sp),LOCAL_SIZE+0x4(%sp) + mov.l LOCAL_SIZE+FP_DST_HI(%sp),LOCAL_SIZE+0x8(%sp) + mov.l LOCAL_SIZE+FP_DST_LO(%sp),LOCAL_SIZE+0xc(%sp) + + add.l &LOCAL_SIZE-0x8,%sp + + + bra.l _real_snan + +fu_operr_p: + btst &0x5,EXC_SR(%a6) + bne.w fu_operr_p_s + + mov.l EXC_A7(%a6),%a0 + mov.l %a0,%usp + bra.w fu_operr + +fu_operr_p_s: + cmpi.b SPCOND_FLG(%a6),&mda7_flg + bne.w fu_operr + +# the instruction was "fmove.p fpn,-(a7)" from supervisor mode. +# the strategy is to move the exception frame "down" 12 bytes. then, we +# can store the default result where the exception frame was. + fmovm.x EXC_FPREGS(%a6),&0xc0 # restore fp0/fp1 + fmovm.l USER_FPCR(%a6),%fpcr,%fpsr,%fpiar # restore ctrl regs + movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 + + mov.w &0x30d0,EXC_VOFF(%a6) # vector offset = 0xd0 + mov.w &0xe004,2+FP_SRC(%a6) # set fsave status + + frestore FP_SRC(%a6) # restore src operand + + mov.l (%a6),%a6 # restore frame pointer + + mov.l LOCAL_SIZE+EXC_SR(%sp),LOCAL_SIZE+EXC_SR-0xc(%sp) + mov.l LOCAL_SIZE+2+EXC_PC(%sp),LOCAL_SIZE+2+EXC_PC-0xc(%sp) + mov.l LOCAL_SIZE+EXC_EA(%sp),LOCAL_SIZE+EXC_EA-0xc(%sp) + +# now, we copy the default result to its proper location + mov.l LOCAL_SIZE+FP_DST_EX(%sp),LOCAL_SIZE+0x4(%sp) + mov.l LOCAL_SIZE+FP_DST_HI(%sp),LOCAL_SIZE+0x8(%sp) + mov.l LOCAL_SIZE+FP_DST_LO(%sp),LOCAL_SIZE+0xc(%sp) + + add.l &LOCAL_SIZE-0x8,%sp + + + bra.l _real_operr + +fu_inex_p2: + btst &0x5,EXC_SR(%a6) + bne.w fu_inex_s_p2 + + mov.l EXC_A7(%a6),%a0 + mov.l %a0,%usp + bra.w fu_inex + +fu_inex_s_p2: + cmpi.b SPCOND_FLG(%a6),&mda7_flg + bne.w fu_inex + +# the instruction was "fmove.p fpn,-(a7)" from supervisor mode. +# the strategy is to move the exception frame "down" 12 bytes. then, we +# can store the default result where the exception frame was. + fmovm.x EXC_FPREGS(%a6),&0xc0 # restore fp0/fp1 + fmovm.l USER_FPCR(%a6),%fpcr,%fpsr,%fpiar # restore ctrl regs + movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 + + mov.w &0x30c4,EXC_VOFF(%a6) # vector offset = 0xc4 + mov.w &0xe001,2+FP_SRC(%a6) # set fsave status + + frestore FP_SRC(%a6) # restore src operand + + mov.l (%a6),%a6 # restore frame pointer + + mov.l LOCAL_SIZE+EXC_SR(%sp),LOCAL_SIZE+EXC_SR-0xc(%sp) + mov.l LOCAL_SIZE+2+EXC_PC(%sp),LOCAL_SIZE+2+EXC_PC-0xc(%sp) + mov.l LOCAL_SIZE+EXC_EA(%sp),LOCAL_SIZE+EXC_EA-0xc(%sp) + +# now, we copy the default result to its proper location + mov.l LOCAL_SIZE+FP_DST_EX(%sp),LOCAL_SIZE+0x4(%sp) + mov.l LOCAL_SIZE+FP_DST_HI(%sp),LOCAL_SIZE+0x8(%sp) + mov.l LOCAL_SIZE+FP_DST_LO(%sp),LOCAL_SIZE+0xc(%sp) + + add.l &LOCAL_SIZE-0x8,%sp + + + bra.l _real_inex + +######################################################################### + +# +# if we're stuffing a source operand back into an fsave frame then we +# have to make sure that for single or double source operands that the +# format stuffed is as weird as the hardware usually makes it. +# + global funimp_skew +funimp_skew: + bfextu EXC_EXTWORD(%a6){&3:&3},%d0 # extract src specifier + cmpi.b %d0,&0x1 # was src sgl? + beq.b funimp_skew_sgl # yes + cmpi.b %d0,&0x5 # was src dbl? + beq.b funimp_skew_dbl # yes + rts + +funimp_skew_sgl: + mov.w FP_SRC_EX(%a6),%d0 # fetch DENORM exponent + andi.w &0x7fff,%d0 # strip sign + beq.b funimp_skew_sgl_not + cmpi.w %d0,&0x3f80 + bgt.b funimp_skew_sgl_not + neg.w %d0 # make exponent negative + addi.w &0x3f81,%d0 # find amt to shift + mov.l FP_SRC_HI(%a6),%d1 # fetch DENORM hi(man) + lsr.l %d0,%d1 # shift it + bset &31,%d1 # set j-bit + mov.l %d1,FP_SRC_HI(%a6) # insert new hi(man) + andi.w &0x8000,FP_SRC_EX(%a6) # clear old exponent + ori.w &0x3f80,FP_SRC_EX(%a6) # insert new "skewed" exponent +funimp_skew_sgl_not: + rts + +funimp_skew_dbl: + mov.w FP_SRC_EX(%a6),%d0 # fetch DENORM exponent + andi.w &0x7fff,%d0 # strip sign + beq.b funimp_skew_dbl_not + cmpi.w %d0,&0x3c00 + bgt.b funimp_skew_dbl_not + + tst.b FP_SRC_EX(%a6) # make "internal format" + smi.b 0x2+FP_SRC(%a6) + mov.w %d0,FP_SRC_EX(%a6) # insert exponent with cleared sign + clr.l %d0 # clear g,r,s + lea FP_SRC(%a6),%a0 # pass ptr to src op + mov.w &0x3c01,%d1 # pass denorm threshold + bsr.l dnrm_lp # denorm it + mov.w &0x3c00,%d0 # new exponent + tst.b 0x2+FP_SRC(%a6) # is sign set? + beq.b fss_dbl_denorm_done # no + bset &15,%d0 # set sign +fss_dbl_denorm_done: + bset &0x7,FP_SRC_HI(%a6) # set j-bit + mov.w %d0,FP_SRC_EX(%a6) # insert new exponent +funimp_skew_dbl_not: + rts + +######################################################################### + global _mem_write2 +_mem_write2: + btst &0x5,EXC_SR(%a6) + beq.l _dmem_write + mov.l 0x0(%a0),FP_DST_EX(%a6) + mov.l 0x4(%a0),FP_DST_HI(%a6) + mov.l 0x8(%a0),FP_DST_LO(%a6) + clr.l %d1 + rts + +######################################################################### +# XDEF **************************************************************** # +# _fpsp_effadd(): 060FPSP entry point for FP "Unimplemented # +# effective address" exception. # +# # +# This handler should be the first code executed upon taking the # +# FP Unimplemented Effective Address exception in an operating # +# system. # +# # +# XREF **************************************************************** # +# _imem_read_long() - read instruction longword # +# fix_skewed_ops() - adjust src operand in fsave frame # +# set_tag_x() - determine optype of src/dst operands # +# store_fpreg() - store opclass 0 or 2 result to FP regfile # +# unnorm_fix() - change UNNORM operands to NORM or ZERO # +# load_fpn2() - load dst operand from FP regfile # +# tbl_unsupp - add of table of emulation routines for opclass 0,2 # +# decbin() - convert packed data to FP binary data # +# _real_fpu_disabled() - "callout" for "FPU disabled" exception # +# _real_access() - "callout" for access error exception # +# _mem_read() - read extended immediate operand from memory # +# _fpsp_done() - "callout" for exit; work all done # +# _real_trace() - "callout" for Trace enabled exception # +# fmovm_dynamic() - emulate dynamic fmovm instruction # +# fmovm_ctrl() - emulate fmovm control instruction # +# # +# INPUT *************************************************************** # +# - The system stack contains the "Unimplemented " stk frame # +# # +# OUTPUT ************************************************************** # +# If access error: # +# - The system stack is changed to an access error stack frame # +# If FPU disabled: # +# - The system stack is changed to an FPU disabled stack frame # +# If Trace exception enabled: # +# - The system stack is changed to a Trace exception stack frame # +# Else: (normal case) # +# - None (correct result has been stored as appropriate) # +# # +# ALGORITHM *********************************************************** # +# This exception handles 3 types of operations: # +# (1) FP Instructions using extended precision or packed immediate # +# addressing mode. # +# (2) The "fmovm.x" instruction w/ dynamic register specification. # +# (3) The "fmovm.l" instruction w/ 2 or 3 control registers. # +# # +# For immediate data operations, the data is read in w/ a # +# _mem_read() "callout", converted to FP binary (if packed), and used # +# as the source operand to the instruction specified by the instruction # +# word. If no FP exception should be reported ads a result of the # +# emulation, then the result is stored to the destination register and # +# the handler exits through _fpsp_done(). If an enabled exc has been # +# signalled as a result of emulation, then an fsave state frame # +# corresponding to the FP exception type must be entered into the 060 # +# FPU before exiting. In either the enabled or disabled cases, we # +# must also check if a Trace exception is pending, in which case, we # +# must create a Trace exception stack frame from the current exception # +# stack frame. If no Trace is pending, we simply exit through # +# _fpsp_done(). # +# For "fmovm.x", call the routine fmovm_dynamic() which will # +# decode and emulate the instruction. No FP exceptions can be pending # +# as a result of this operation emulation. A Trace exception can be # +# pending, though, which means the current stack frame must be changed # +# to a Trace stack frame and an exit made through _real_trace(). # +# For the case of "fmovm.x Dn,-(a7)", where the offending instruction # +# was executed from supervisor mode, this handler must store the FP # +# register file values to the system stack by itself since # +# fmovm_dynamic() can't handle this. A normal exit is made through # +# fpsp_done(). # +# For "fmovm.l", fmovm_ctrl() is used to emulate the instruction. # +# Again, a Trace exception may be pending and an exit made through # +# _real_trace(). Else, a normal exit is made through _fpsp_done(). # +# # +# Before any of the above is attempted, it must be checked to # +# see if the FPU is disabled. Since the "Unimp " exception is taken # +# before the "FPU disabled" exception, but the "FPU disabled" exception # +# has higher priority, we check the disabled bit in the PCR. If set, # +# then we must create an 8 word "FPU disabled" exception stack frame # +# from the current 4 word exception stack frame. This includes # +# reproducing the effective address of the instruction to put on the # +# new stack frame. # +# # +# In the process of all emulation work, if a _mem_read() # +# "callout" returns a failing result indicating an access error, then # +# we must create an access error stack frame from the current stack # +# frame. This information includes a faulting address and a fault- # +# status-longword. These are created within this handler. # +# # +######################################################################### + + global _fpsp_effadd +_fpsp_effadd: + +# This exception type takes priority over the "Line F Emulator" +# exception. Therefore, the FPU could be disabled when entering here. +# So, we must check to see if it's disabled and handle that case separately. + mov.l %d0,-(%sp) # save d0 + movc %pcr,%d0 # load proc cr + btst &0x1,%d0 # is FPU disabled? + bne.w iea_disabled # yes + mov.l (%sp)+,%d0 # restore d0 + + link %a6,&-LOCAL_SIZE # init stack frame + + movm.l &0x0303,EXC_DREGS(%a6) # save d0-d1/a0-a1 + fmovm.l %fpcr,%fpsr,%fpiar,USER_FPCR(%a6) # save ctrl regs + fmovm.x &0xc0,EXC_FPREGS(%a6) # save fp0-fp1 on stack + +# PC of instruction that took the exception is the PC in the frame + mov.l EXC_PC(%a6),EXC_EXTWPTR(%a6) + + mov.l EXC_EXTWPTR(%a6),%a0 # fetch instruction addr + addq.l &0x4,EXC_EXTWPTR(%a6) # incr instruction ptr + bsr.l _imem_read_long # fetch the instruction words + mov.l %d0,EXC_OPWORD(%a6) # store OPWORD and EXTWORD + +######################################################################### + + tst.w %d0 # is operation fmovem? + bmi.w iea_fmovm # yes + +# +# here, we will have: +# fabs fdabs fsabs facos fmod +# fadd fdadd fsadd fasin frem +# fcmp fatan fscale +# fdiv fddiv fsdiv fatanh fsin +# fint fcos fsincos +# fintrz fcosh fsinh +# fmove fdmove fsmove fetox ftan +# fmul fdmul fsmul fetoxm1 ftanh +# fneg fdneg fsneg fgetexp ftentox +# fsgldiv fgetman ftwotox +# fsglmul flog10 +# fsqrt flog2 +# fsub fdsub fssub flogn +# ftst flognp1 +# which can all use f.{x,p} +# so, now it's immediate data extended precision AND PACKED FORMAT! +# +iea_op: + andi.l &0x00ff00ff,USER_FPSR(%a6) + + btst &0xa,%d0 # is src fmt x or p? + bne.b iea_op_pack # packed + + + mov.l EXC_EXTWPTR(%a6),%a0 # pass: ptr to # + lea FP_SRC(%a6),%a1 # pass: ptr to super addr + mov.l &0xc,%d0 # pass: 12 bytes + bsr.l _imem_read # read extended immediate + + tst.l %d1 # did ifetch fail? + bne.w iea_iacc # yes + + bra.b iea_op_setsrc + +iea_op_pack: + + mov.l EXC_EXTWPTR(%a6),%a0 # pass: ptr to # + lea FP_SRC(%a6),%a1 # pass: ptr to super dst + mov.l &0xc,%d0 # pass: 12 bytes + bsr.l _imem_read # read packed operand + + tst.l %d1 # did ifetch fail? + bne.w iea_iacc # yes + +# The packed operand is an INF or a NAN if the exponent field is all ones. + bfextu FP_SRC(%a6){&1:&15},%d0 # get exp + cmpi.w %d0,&0x7fff # INF or NAN? + beq.b iea_op_setsrc # operand is an INF or NAN + +# The packed operand is a zero if the mantissa is all zero, else it's +# a normal packed op. + mov.b 3+FP_SRC(%a6),%d0 # get byte 4 + andi.b &0x0f,%d0 # clear all but last nybble + bne.b iea_op_gp_not_spec # not a zero + tst.l FP_SRC_HI(%a6) # is lw 2 zero? + bne.b iea_op_gp_not_spec # not a zero + tst.l FP_SRC_LO(%a6) # is lw 3 zero? + beq.b iea_op_setsrc # operand is a ZERO +iea_op_gp_not_spec: + lea FP_SRC(%a6),%a0 # pass: ptr to packed op + bsr.l decbin # convert to extended + fmovm.x &0x80,FP_SRC(%a6) # make this the srcop + +iea_op_setsrc: + addi.l &0xc,EXC_EXTWPTR(%a6) # update extension word pointer + +# FP_SRC now holds the src operand. + lea FP_SRC(%a6),%a0 # pass: ptr to src op + bsr.l set_tag_x # tag the operand type + mov.b %d0,STAG(%a6) # could be ANYTHING!!! + cmpi.b %d0,&UNNORM # is operand an UNNORM? + bne.b iea_op_getdst # no + bsr.l unnorm_fix # yes; convert to NORM/DENORM/ZERO + mov.b %d0,STAG(%a6) # set new optype tag +iea_op_getdst: + clr.b STORE_FLG(%a6) # clear "store result" boolean + + btst &0x5,1+EXC_CMDREG(%a6) # is operation monadic or dyadic? + beq.b iea_op_extract # monadic + btst &0x4,1+EXC_CMDREG(%a6) # is operation fsincos,ftst,fcmp? + bne.b iea_op_spec # yes + +iea_op_loaddst: + bfextu EXC_CMDREG(%a6){&6:&3},%d0 # fetch dst regno + bsr.l load_fpn2 # load dst operand + + lea FP_DST(%a6),%a0 # pass: ptr to dst op + bsr.l set_tag_x # tag the operand type + mov.b %d0,DTAG(%a6) # could be ANYTHING!!! + cmpi.b %d0,&UNNORM # is operand an UNNORM? + bne.b iea_op_extract # no + bsr.l unnorm_fix # yes; convert to NORM/DENORM/ZERO + mov.b %d0,DTAG(%a6) # set new optype tag + bra.b iea_op_extract + +# the operation is fsincos, ftst, or fcmp. only fcmp is dyadic +iea_op_spec: + btst &0x3,1+EXC_CMDREG(%a6) # is operation fsincos? + beq.b iea_op_extract # yes +# now, we're left with ftst and fcmp. so, first let's tag them so that they don't +# store a result. then, only fcmp will branch back and pick up a dst operand. + st STORE_FLG(%a6) # don't store a final result + btst &0x1,1+EXC_CMDREG(%a6) # is operation fcmp? + beq.b iea_op_loaddst # yes + +iea_op_extract: + clr.l %d0 + mov.b FPCR_MODE(%a6),%d0 # pass: rnd mode,prec + + mov.b 1+EXC_CMDREG(%a6),%d1 + andi.w &0x007f,%d1 # extract extension + + fmov.l &0x0,%fpcr + fmov.l &0x0,%fpsr + + lea FP_SRC(%a6),%a0 + lea FP_DST(%a6),%a1 + + mov.l (tbl_unsupp.l,%pc,%d1.w*4),%d1 # fetch routine addr + jsr (tbl_unsupp.l,%pc,%d1.l*1) + +# +# Exceptions in order of precedence: +# BSUN : none +# SNAN : all operations +# OPERR : all reg-reg or mem-reg operations that can normally operr +# OVFL : same as OPERR +# UNFL : same as OPERR +# DZ : same as OPERR +# INEX2 : same as OPERR +# INEX1 : all packed immediate operations +# + +# we determine the highest priority exception(if any) set by the +# emulation routine that has also been enabled by the user. + mov.b FPCR_ENABLE(%a6),%d0 # fetch exceptions enabled + bne.b iea_op_ena # some are enabled + +# now, we save the result, unless, of course, the operation was ftst or fcmp. +# these don't save results. +iea_op_save: + tst.b STORE_FLG(%a6) # does this op store a result? + bne.b iea_op_exit1 # exit with no frestore + +iea_op_store: + bfextu EXC_CMDREG(%a6){&6:&3},%d0 # fetch dst regno + bsr.l store_fpreg # store the result + +iea_op_exit1: + mov.l EXC_PC(%a6),USER_FPIAR(%a6) # set FPIAR to "Current PC" + mov.l EXC_EXTWPTR(%a6),EXC_PC(%a6) # set "Next PC" in exc frame + + fmovm.x EXC_FPREGS(%a6),&0xc0 # restore fp0-fp1 + fmovm.l USER_FPCR(%a6),%fpcr,%fpsr,%fpiar # restore ctrl regs + movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 + + unlk %a6 # unravel the frame + + btst &0x7,(%sp) # is trace on? + bne.w iea_op_trace # yes + + bra.l _fpsp_done # exit to os + +iea_op_ena: + and.b FPSR_EXCEPT(%a6),%d0 # keep only ones enable and set + bfffo %d0{&24:&8},%d0 # find highest priority exception + bne.b iea_op_exc # at least one was set + +# no exception occurred. now, did a disabled, exact overflow occur with inexact +# enabled? if so, then we have to stuff an overflow frame into the FPU. + btst &ovfl_bit,FPSR_EXCEPT(%a6) # did overflow occur? + beq.b iea_op_save + +iea_op_ovfl: + btst &inex2_bit,FPCR_ENABLE(%a6) # is inexact enabled? + beq.b iea_op_store # no + bra.b iea_op_exc_ovfl # yes + +# an enabled exception occurred. we have to insert the exception type back into +# the machine. +iea_op_exc: + subi.l &24,%d0 # fix offset to be 0-8 + cmpi.b %d0,&0x6 # is exception INEX? + bne.b iea_op_exc_force # no + +# the enabled exception was inexact. so, if it occurs with an overflow +# or underflow that was disabled, then we have to force an overflow or +# underflow frame. + btst &ovfl_bit,FPSR_EXCEPT(%a6) # did overflow occur? + bne.b iea_op_exc_ovfl # yes + btst &unfl_bit,FPSR_EXCEPT(%a6) # did underflow occur? + bne.b iea_op_exc_unfl # yes + +iea_op_exc_force: + mov.w (tbl_iea_except.b,%pc,%d0.w*2),2+FP_SRC(%a6) + bra.b iea_op_exit2 # exit with frestore + +tbl_iea_except: + short 0xe002, 0xe006, 0xe004, 0xe005 + short 0xe003, 0xe002, 0xe001, 0xe001 + +iea_op_exc_ovfl: + mov.w &0xe005,2+FP_SRC(%a6) + bra.b iea_op_exit2 + +iea_op_exc_unfl: + mov.w &0xe003,2+FP_SRC(%a6) + +iea_op_exit2: + mov.l EXC_PC(%a6),USER_FPIAR(%a6) # set FPIAR to "Current PC" + mov.l EXC_EXTWPTR(%a6),EXC_PC(%a6) # set "Next PC" in exc frame + + fmovm.x EXC_FPREGS(%a6),&0xc0 # restore fp0-fp1 + fmovm.l USER_FPCR(%a6),%fpcr,%fpsr,%fpiar # restore ctrl regs + movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 + + frestore FP_SRC(%a6) # restore exceptional state + + unlk %a6 # unravel the frame + + btst &0x7,(%sp) # is trace on? + bne.b iea_op_trace # yes + + bra.l _fpsp_done # exit to os + +# +# The opclass two instruction that took an "Unimplemented Effective Address" +# exception was being traced. Make the "current" PC the FPIAR and put it in +# the trace stack frame then jump to _real_trace(). +# +# UNIMP EA FRAME TRACE FRAME +# ***************** ***************** +# * 0x0 * 0x0f0 * * Current * +# ***************** * PC * +# * Current * ***************** +# * PC * * 0x2 * 0x024 * +# ***************** ***************** +# * SR * * Next * +# ***************** * PC * +# ***************** +# * SR * +# ***************** +iea_op_trace: + mov.l (%sp),-(%sp) # shift stack frame "down" + mov.w 0x8(%sp),0x4(%sp) + mov.w &0x2024,0x6(%sp) # stk fmt = 0x2; voff = 0x024 + fmov.l %fpiar,0x8(%sp) # "Current PC" is in FPIAR + + bra.l _real_trace + +######################################################################### +iea_fmovm: + btst &14,%d0 # ctrl or data reg + beq.w iea_fmovm_ctrl + +iea_fmovm_data: + + btst &0x5,EXC_SR(%a6) # user or supervisor mode + bne.b iea_fmovm_data_s + +iea_fmovm_data_u: + mov.l %usp,%a0 + mov.l %a0,EXC_A7(%a6) # store current a7 + bsr.l fmovm_dynamic # do dynamic fmovm + mov.l EXC_A7(%a6),%a0 # load possibly new a7 + mov.l %a0,%usp # update usp + bra.w iea_fmovm_exit + +iea_fmovm_data_s: + clr.b SPCOND_FLG(%a6) + lea 0x2+EXC_VOFF(%a6),%a0 + mov.l %a0,EXC_A7(%a6) + bsr.l fmovm_dynamic # do dynamic fmovm + + cmpi.b SPCOND_FLG(%a6),&mda7_flg + beq.w iea_fmovm_data_predec + cmpi.b SPCOND_FLG(%a6),&mia7_flg + bne.w iea_fmovm_exit + +# right now, d0 = the size. +# the data has been fetched from the supervisor stack, but we have not +# incremented the stack pointer by the appropriate number of bytes. +# do it here. +iea_fmovm_data_postinc: + btst &0x7,EXC_SR(%a6) + bne.b iea_fmovm_data_pi_trace + + mov.w EXC_SR(%a6),(EXC_SR,%a6,%d0) + mov.l EXC_EXTWPTR(%a6),(EXC_PC,%a6,%d0) + mov.w &0x00f0,(EXC_VOFF,%a6,%d0) + + lea (EXC_SR,%a6,%d0),%a0 + mov.l %a0,EXC_SR(%a6) + + fmovm.x EXC_FP0(%a6),&0xc0 # restore fp0-fp1 + fmovm.l USER_FPCR(%a6),%fpcr,%fpsr,%fpiar # restore ctrl regs + movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 + + unlk %a6 + mov.l (%sp)+,%sp + bra.l _fpsp_done + +iea_fmovm_data_pi_trace: + mov.w EXC_SR(%a6),(EXC_SR-0x4,%a6,%d0) + mov.l EXC_EXTWPTR(%a6),(EXC_PC-0x4,%a6,%d0) + mov.w &0x2024,(EXC_VOFF-0x4,%a6,%d0) + mov.l EXC_PC(%a6),(EXC_VOFF+0x2-0x4,%a6,%d0) + + lea (EXC_SR-0x4,%a6,%d0),%a0 + mov.l %a0,EXC_SR(%a6) + + fmovm.x EXC_FP0(%a6),&0xc0 # restore fp0-fp1 + fmovm.l USER_FPCR(%a6),%fpcr,%fpsr,%fpiar # restore ctrl regs + movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 + + unlk %a6 + mov.l (%sp)+,%sp + bra.l _real_trace + +# right now, d1 = size and d0 = the strg. +iea_fmovm_data_predec: + mov.b %d1,EXC_VOFF(%a6) # store strg + mov.b %d0,0x1+EXC_VOFF(%a6) # store size + + fmovm.x EXC_FP0(%a6),&0xc0 # restore fp0-fp1 + fmovm.l USER_FPCR(%a6),%fpcr,%fpsr,%fpiar # restore ctrl regs + movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 + + mov.l (%a6),-(%sp) # make a copy of a6 + mov.l %d0,-(%sp) # save d0 + mov.l %d1,-(%sp) # save d1 + mov.l EXC_EXTWPTR(%a6),-(%sp) # make a copy of Next PC + + clr.l %d0 + mov.b 0x1+EXC_VOFF(%a6),%d0 # fetch size + neg.l %d0 # get negative of size + + btst &0x7,EXC_SR(%a6) # is trace enabled? + beq.b iea_fmovm_data_p2 + + mov.w EXC_SR(%a6),(EXC_SR-0x4,%a6,%d0) + mov.l EXC_PC(%a6),(EXC_VOFF-0x2,%a6,%d0) + mov.l (%sp)+,(EXC_PC-0x4,%a6,%d0) + mov.w &0x2024,(EXC_VOFF-0x4,%a6,%d0) + + pea (%a6,%d0) # create final sp + bra.b iea_fmovm_data_p3 + +iea_fmovm_data_p2: + mov.w EXC_SR(%a6),(EXC_SR,%a6,%d0) + mov.l (%sp)+,(EXC_PC,%a6,%d0) + mov.w &0x00f0,(EXC_VOFF,%a6,%d0) + + pea (0x4,%a6,%d0) # create final sp + +iea_fmovm_data_p3: + clr.l %d1 + mov.b EXC_VOFF(%a6),%d1 # fetch strg + + tst.b %d1 + bpl.b fm_1 + fmovm.x &0x80,(0x4+0x8,%a6,%d0) + addi.l &0xc,%d0 +fm_1: + lsl.b &0x1,%d1 + bpl.b fm_2 + fmovm.x &0x40,(0x4+0x8,%a6,%d0) + addi.l &0xc,%d0 +fm_2: + lsl.b &0x1,%d1 + bpl.b fm_3 + fmovm.x &0x20,(0x4+0x8,%a6,%d0) + addi.l &0xc,%d0 +fm_3: + lsl.b &0x1,%d1 + bpl.b fm_4 + fmovm.x &0x10,(0x4+0x8,%a6,%d0) + addi.l &0xc,%d0 +fm_4: + lsl.b &0x1,%d1 + bpl.b fm_5 + fmovm.x &0x08,(0x4+0x8,%a6,%d0) + addi.l &0xc,%d0 +fm_5: + lsl.b &0x1,%d1 + bpl.b fm_6 + fmovm.x &0x04,(0x4+0x8,%a6,%d0) + addi.l &0xc,%d0 +fm_6: + lsl.b &0x1,%d1 + bpl.b fm_7 + fmovm.x &0x02,(0x4+0x8,%a6,%d0) + addi.l &0xc,%d0 +fm_7: + lsl.b &0x1,%d1 + bpl.b fm_end + fmovm.x &0x01,(0x4+0x8,%a6,%d0) +fm_end: + mov.l 0x4(%sp),%d1 + mov.l 0x8(%sp),%d0 + mov.l 0xc(%sp),%a6 + mov.l (%sp)+,%sp + + btst &0x7,(%sp) # is trace enabled? + beq.l _fpsp_done + bra.l _real_trace + +######################################################################### +iea_fmovm_ctrl: + + bsr.l fmovm_ctrl # load ctrl regs + +iea_fmovm_exit: + fmovm.x EXC_FPREGS(%a6),&0xc0 # restore fp0-fp1 + fmovm.l USER_FPCR(%a6),%fpcr,%fpsr,%fpiar # restore ctrl regs + movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 + + btst &0x7,EXC_SR(%a6) # is trace on? + bne.b iea_fmovm_trace # yes + + mov.l EXC_EXTWPTR(%a6),EXC_PC(%a6) # set Next PC + + unlk %a6 # unravel the frame + + bra.l _fpsp_done # exit to os + +# +# The control reg instruction that took an "Unimplemented Effective Address" +# exception was being traced. The "Current PC" for the trace frame is the +# PC stacked for Unimp EA. The "Next PC" is in EXC_EXTWPTR. +# After fixing the stack frame, jump to _real_trace(). +# +# UNIMP EA FRAME TRACE FRAME +# ***************** ***************** +# * 0x0 * 0x0f0 * * Current * +# ***************** * PC * +# * Current * ***************** +# * PC * * 0x2 * 0x024 * +# ***************** ***************** +# * SR * * Next * +# ***************** * PC * +# ***************** +# * SR * +# ***************** +# this ain't a pretty solution, but it works: +# -restore a6 (not with unlk) +# -shift stack frame down over where old a6 used to be +# -add LOCAL_SIZE to stack pointer +iea_fmovm_trace: + mov.l (%a6),%a6 # restore frame pointer + mov.w EXC_SR+LOCAL_SIZE(%sp),0x0+LOCAL_SIZE(%sp) + mov.l EXC_PC+LOCAL_SIZE(%sp),0x8+LOCAL_SIZE(%sp) + mov.l EXC_EXTWPTR+LOCAL_SIZE(%sp),0x2+LOCAL_SIZE(%sp) + mov.w &0x2024,0x6+LOCAL_SIZE(%sp) # stk fmt = 0x2; voff = 0x024 + add.l &LOCAL_SIZE,%sp # clear stack frame + + bra.l _real_trace + +######################################################################### +# The FPU is disabled and so we should really have taken the "Line +# F Emulator" exception. So, here we create an 8-word stack frame +# from our 4-word stack frame. This means we must calculate the length +# the faulting instruction to get the "next PC". This is trivial for +# immediate operands but requires some extra work for fmovm dynamic +# which can use most addressing modes. +iea_disabled: + mov.l (%sp)+,%d0 # restore d0 + + link %a6,&-LOCAL_SIZE # init stack frame + + movm.l &0x0303,EXC_DREGS(%a6) # save d0-d1/a0-a1 + +# PC of instruction that took the exception is the PC in the frame + mov.l EXC_PC(%a6),EXC_EXTWPTR(%a6) + mov.l EXC_EXTWPTR(%a6),%a0 # fetch instruction addr + addq.l &0x4,EXC_EXTWPTR(%a6) # incr instruction ptr + bsr.l _imem_read_long # fetch the instruction words + mov.l %d0,EXC_OPWORD(%a6) # store OPWORD and EXTWORD + + tst.w %d0 # is instr fmovm? + bmi.b iea_dis_fmovm # yes +# instruction is using an extended precision immediate operand. Therefore, +# the total instruction length is 16 bytes. +iea_dis_immed: + mov.l &0x10,%d0 # 16 bytes of instruction + bra.b iea_dis_cont +iea_dis_fmovm: + btst &0xe,%d0 # is instr fmovm ctrl + bne.b iea_dis_fmovm_data # no +# the instruction is a fmovm.l with 2 or 3 registers. + bfextu %d0{&19:&3},%d1 + mov.l &0xc,%d0 + cmpi.b %d1,&0x7 # move all regs? + bne.b iea_dis_cont + addq.l &0x4,%d0 + bra.b iea_dis_cont +# the instruction is an fmovm.x dynamic which can use many addressing +# modes and thus can have several different total instruction lengths. +# call fmovm_calc_ea which will go through the ea calc process and, +# as a by-product, will tell us how long the instruction is. +iea_dis_fmovm_data: + clr.l %d0 + bsr.l fmovm_calc_ea + mov.l EXC_EXTWPTR(%a6),%d0 + sub.l EXC_PC(%a6),%d0 +iea_dis_cont: + mov.w %d0,EXC_VOFF(%a6) # store stack shift value + + movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 + + unlk %a6 + +# here, we actually create the 8-word frame from the 4-word frame, +# with the "next PC" as additional info. +# the field is let as undefined. + subq.l &0x8,%sp # make room for new stack + mov.l %d0,-(%sp) # save d0 + mov.w 0xc(%sp),0x4(%sp) # move SR + mov.l 0xe(%sp),0x6(%sp) # move Current PC + clr.l %d0 + mov.w 0x12(%sp),%d0 + mov.l 0x6(%sp),0x10(%sp) # move Current PC + add.l %d0,0x6(%sp) # make Next PC + mov.w &0x402c,0xa(%sp) # insert offset,frame format + mov.l (%sp)+,%d0 # restore d0 + + bra.l _real_fpu_disabled + +########## + +iea_iacc: + movc %pcr,%d0 + btst &0x1,%d0 + bne.b iea_iacc_cont + fmovm.l USER_FPCR(%a6),%fpcr,%fpsr,%fpiar # restore ctrl regs + fmovm.x EXC_FPREGS(%a6),&0xc0 # restore fp0-fp1 on stack +iea_iacc_cont: + movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 + + unlk %a6 + + subq.w &0x8,%sp # make stack frame bigger + mov.l 0x8(%sp),(%sp) # store SR,hi(PC) + mov.w 0xc(%sp),0x4(%sp) # store lo(PC) + mov.w &0x4008,0x6(%sp) # store voff + mov.l 0x2(%sp),0x8(%sp) # store ea + mov.l &0x09428001,0xc(%sp) # store fslw + +iea_acc_done: + btst &0x5,(%sp) # user or supervisor mode? + beq.b iea_acc_done2 # user + bset &0x2,0xd(%sp) # set supervisor TM bit + +iea_acc_done2: + bra.l _real_access + +iea_dacc: + lea -LOCAL_SIZE(%a6),%sp + + movc %pcr,%d1 + btst &0x1,%d1 + bne.b iea_dacc_cont + fmovm.x EXC_FPREGS(%a6),&0xc0 # restore fp0-fp1 on stack + fmovm.l LOCAL_SIZE+USER_FPCR(%sp),%fpcr,%fpsr,%fpiar # restore ctrl regs +iea_dacc_cont: + mov.l (%a6),%a6 + + mov.l 0x4+LOCAL_SIZE(%sp),-0x8+0x4+LOCAL_SIZE(%sp) + mov.w 0x8+LOCAL_SIZE(%sp),-0x8+0x8+LOCAL_SIZE(%sp) + mov.w &0x4008,-0x8+0xa+LOCAL_SIZE(%sp) + mov.l %a0,-0x8+0xc+LOCAL_SIZE(%sp) + mov.w %d0,-0x8+0x10+LOCAL_SIZE(%sp) + mov.w &0x0001,-0x8+0x12+LOCAL_SIZE(%sp) + + movm.l LOCAL_SIZE+EXC_DREGS(%sp),&0x0303 # restore d0-d1/a0-a1 + add.w &LOCAL_SIZE-0x4,%sp + + bra.b iea_acc_done + +######################################################################### +# XDEF **************************************************************** # +# _fpsp_operr(): 060FPSP entry point for FP Operr exception. # +# # +# This handler should be the first code executed upon taking the # +# FP Operand Error exception in an operating system. # +# # +# XREF **************************************************************** # +# _imem_read_long() - read instruction longword # +# fix_skewed_ops() - adjust src operand in fsave frame # +# _real_operr() - "callout" to operating system operr handler # +# _dmem_write_{byte,word,long}() - store data to mem (opclass 3) # +# store_dreg_{b,w,l}() - store data to data regfile (opclass 3) # +# facc_out_{b,w,l}() - store to memory took access error (opcl 3) # +# # +# INPUT *************************************************************** # +# - The system stack contains the FP Operr exception frame # +# - The fsave frame contains the source operand # +# # +# OUTPUT ************************************************************** # +# No access error: # +# - The system stack is unchanged # +# - The fsave frame contains the adjusted src op for opclass 0,2 # +# # +# ALGORITHM *********************************************************** # +# In a system where the FP Operr exception is enabled, the goal # +# is to get to the handler specified at _real_operr(). But, on the 060, # +# for opclass zero and two instruction taking this exception, the # +# input operand in the fsave frame may be incorrect for some cases # +# and needs to be corrected. This handler calls fix_skewed_ops() to # +# do just this and then exits through _real_operr(). # +# For opclass 3 instructions, the 060 doesn't store the default # +# operr result out to memory or data register file as it should. # +# This code must emulate the move out before finally exiting through # +# _real_inex(). The move out, if to memory, is performed using # +# _mem_write() "callout" routines that may return a failing result. # +# In this special case, the handler must exit through facc_out() # +# which creates an access error stack frame from the current operr # +# stack frame. # +# # +######################################################################### + + global _fpsp_operr +_fpsp_operr: + + link.w %a6,&-LOCAL_SIZE # init stack frame + + fsave FP_SRC(%a6) # grab the "busy" frame + + movm.l &0x0303,EXC_DREGS(%a6) # save d0-d1/a0-a1 + fmovm.l %fpcr,%fpsr,%fpiar,USER_FPCR(%a6) # save ctrl regs + fmovm.x &0xc0,EXC_FPREGS(%a6) # save fp0-fp1 on stack + +# the FPIAR holds the "current PC" of the faulting instruction + mov.l USER_FPIAR(%a6),EXC_EXTWPTR(%a6) + + mov.l EXC_EXTWPTR(%a6),%a0 # fetch instruction addr + addq.l &0x4,EXC_EXTWPTR(%a6) # incr instruction ptr + bsr.l _imem_read_long # fetch the instruction words + mov.l %d0,EXC_OPWORD(%a6) + +############################################################################## + + btst &13,%d0 # is instr an fmove out? + bne.b foperr_out # fmove out + + +# here, we simply see if the operand in the fsave frame needs to be "unskewed". +# this would be the case for opclass two operations with a source infinity or +# denorm operand in the sgl or dbl format. NANs also become skewed, but can't +# cause an operr so we don't need to check for them here. + lea FP_SRC(%a6),%a0 # pass: ptr to src op + bsr.l fix_skewed_ops # fix src op + +foperr_exit: + fmovm.x EXC_FPREGS(%a6),&0xc0 # restore fp0-fp1 + fmovm.l USER_FPCR(%a6),%fpcr,%fpsr,%fpiar # restore ctrl regs + movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 + + frestore FP_SRC(%a6) + + unlk %a6 + bra.l _real_operr + +######################################################################## + +# +# the hardware does not save the default result to memory on enabled +# operand error exceptions. we do this here before passing control to +# the user operand error handler. +# +# byte, word, and long destination format operations can pass +# through here. we simply need to test the sign of the src +# operand and save the appropriate minimum or maximum integer value +# to the effective address as pointed to by the stacked effective address. +# +# although packed opclass three operations can take operand error +# exceptions, they won't pass through here since they are caught +# first by the unsupported data format exception handler. that handler +# sends them directly to _real_operr() if necessary. +# +foperr_out: + + mov.w FP_SRC_EX(%a6),%d1 # fetch exponent + andi.w &0x7fff,%d1 + cmpi.w %d1,&0x7fff + bne.b foperr_out_not_qnan +# the operand is either an infinity or a QNAN. + tst.l FP_SRC_LO(%a6) + bne.b foperr_out_qnan + mov.l FP_SRC_HI(%a6),%d1 + andi.l &0x7fffffff,%d1 + beq.b foperr_out_not_qnan +foperr_out_qnan: + mov.l FP_SRC_HI(%a6),L_SCR1(%a6) + bra.b foperr_out_jmp + +foperr_out_not_qnan: + mov.l &0x7fffffff,%d1 + tst.b FP_SRC_EX(%a6) + bpl.b foperr_out_not_qnan2 + addq.l &0x1,%d1 +foperr_out_not_qnan2: + mov.l %d1,L_SCR1(%a6) + +foperr_out_jmp: + bfextu %d0{&19:&3},%d0 # extract dst format field + mov.b 1+EXC_OPWORD(%a6),%d1 # extract mode,reg + mov.w (tbl_operr.b,%pc,%d0.w*2),%a0 + jmp (tbl_operr.b,%pc,%a0) + +tbl_operr: + short foperr_out_l - tbl_operr # long word integer + short tbl_operr - tbl_operr # sgl prec shouldn't happen + short tbl_operr - tbl_operr # ext prec shouldn't happen + short foperr_exit - tbl_operr # packed won't enter here + short foperr_out_w - tbl_operr # word integer + short tbl_operr - tbl_operr # dbl prec shouldn't happen + short foperr_out_b - tbl_operr # byte integer + short tbl_operr - tbl_operr # packed won't enter here + +foperr_out_b: + mov.b L_SCR1(%a6),%d0 # load positive default result + cmpi.b %d1,&0x7 # is mode a data reg? + ble.b foperr_out_b_save_dn # yes + mov.l EXC_EA(%a6),%a0 # pass: of default result + bsr.l _dmem_write_byte # write the default result + + tst.l %d1 # did dstore fail? + bne.l facc_out_b # yes + + bra.w foperr_exit +foperr_out_b_save_dn: + andi.w &0x0007,%d1 + bsr.l store_dreg_b # store result to regfile + bra.w foperr_exit + +foperr_out_w: + mov.w L_SCR1(%a6),%d0 # load positive default result + cmpi.b %d1,&0x7 # is mode a data reg? + ble.b foperr_out_w_save_dn # yes + mov.l EXC_EA(%a6),%a0 # pass: of default result + bsr.l _dmem_write_word # write the default result + + tst.l %d1 # did dstore fail? + bne.l facc_out_w # yes + + bra.w foperr_exit +foperr_out_w_save_dn: + andi.w &0x0007,%d1 + bsr.l store_dreg_w # store result to regfile + bra.w foperr_exit + +foperr_out_l: + mov.l L_SCR1(%a6),%d0 # load positive default result + cmpi.b %d1,&0x7 # is mode a data reg? + ble.b foperr_out_l_save_dn # yes + mov.l EXC_EA(%a6),%a0 # pass: of default result + bsr.l _dmem_write_long # write the default result + + tst.l %d1 # did dstore fail? + bne.l facc_out_l # yes + + bra.w foperr_exit +foperr_out_l_save_dn: + andi.w &0x0007,%d1 + bsr.l store_dreg_l # store result to regfile + bra.w foperr_exit + +######################################################################### +# XDEF **************************************************************** # +# _fpsp_snan(): 060FPSP entry point for FP SNAN exception. # +# # +# This handler should be the first code executed upon taking the # +# FP Signalling NAN exception in an operating system. # +# # +# XREF **************************************************************** # +# _imem_read_long() - read instruction longword # +# fix_skewed_ops() - adjust src operand in fsave frame # +# _real_snan() - "callout" to operating system SNAN handler # +# _dmem_write_{byte,word,long}() - store data to mem (opclass 3) # +# store_dreg_{b,w,l}() - store data to data regfile (opclass 3) # +# facc_out_{b,w,l,d,x}() - store to mem took acc error (opcl 3) # +# _calc_ea_fout() - fix An if is -() or ()+; also get # +# # +# INPUT *************************************************************** # +# - The system stack contains the FP SNAN exception frame # +# - The fsave frame contains the source operand # +# # +# OUTPUT ************************************************************** # +# No access error: # +# - The system stack is unchanged # +# - The fsave frame contains the adjusted src op for opclass 0,2 # +# # +# ALGORITHM *********************************************************** # +# In a system where the FP SNAN exception is enabled, the goal # +# is to get to the handler specified at _real_snan(). But, on the 060, # +# for opclass zero and two instructions taking this exception, the # +# input operand in the fsave frame may be incorrect for some cases # +# and needs to be corrected. This handler calls fix_skewed_ops() to # +# do just this and then exits through _real_snan(). # +# For opclass 3 instructions, the 060 doesn't store the default # +# SNAN result out to memory or data register file as it should. # +# This code must emulate the move out before finally exiting through # +# _real_snan(). The move out, if to memory, is performed using # +# _mem_write() "callout" routines that may return a failing result. # +# In this special case, the handler must exit through facc_out() # +# which creates an access error stack frame from the current SNAN # +# stack frame. # +# For the case of an extended precision opclass 3 instruction, # +# if the effective addressing mode was -() or ()+, then the address # +# register must get updated by calling _calc_ea_fout(). If the # +# was -(a7) from supervisor mode, then the exception frame currently # +# on the system stack must be carefully moved "down" to make room # +# for the operand being moved. # +# # +######################################################################### + + global _fpsp_snan +_fpsp_snan: + + link.w %a6,&-LOCAL_SIZE # init stack frame + + fsave FP_SRC(%a6) # grab the "busy" frame + + movm.l &0x0303,EXC_DREGS(%a6) # save d0-d1/a0-a1 + fmovm.l %fpcr,%fpsr,%fpiar,USER_FPCR(%a6) # save ctrl regs + fmovm.x &0xc0,EXC_FPREGS(%a6) # save fp0-fp1 on stack + +# the FPIAR holds the "current PC" of the faulting instruction + mov.l USER_FPIAR(%a6),EXC_EXTWPTR(%a6) + + mov.l EXC_EXTWPTR(%a6),%a0 # fetch instruction addr + addq.l &0x4,EXC_EXTWPTR(%a6) # incr instruction ptr + bsr.l _imem_read_long # fetch the instruction words + mov.l %d0,EXC_OPWORD(%a6) + +############################################################################## + + btst &13,%d0 # is instr an fmove out? + bne.w fsnan_out # fmove out + + +# here, we simply see if the operand in the fsave frame needs to be "unskewed". +# this would be the case for opclass two operations with a source infinity or +# denorm operand in the sgl or dbl format. NANs also become skewed and must be +# fixed here. + lea FP_SRC(%a6),%a0 # pass: ptr to src op + bsr.l fix_skewed_ops # fix src op + +fsnan_exit: + fmovm.x EXC_FPREGS(%a6),&0xc0 # restore fp0-fp1 + fmovm.l USER_FPCR(%a6),%fpcr,%fpsr,%fpiar # restore ctrl regs + movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 + + frestore FP_SRC(%a6) + + unlk %a6 + bra.l _real_snan + +######################################################################## + +# +# the hardware does not save the default result to memory on enabled +# snan exceptions. we do this here before passing control to +# the user snan handler. +# +# byte, word, long, and packed destination format operations can pass +# through here. since packed format operations already were handled by +# fpsp_unsupp(), then we need to do nothing else for them here. +# for byte, word, and long, we simply need to test the sign of the src +# operand and save the appropriate minimum or maximum integer value +# to the effective address as pointed to by the stacked effective address. +# +fsnan_out: + + bfextu %d0{&19:&3},%d0 # extract dst format field + mov.b 1+EXC_OPWORD(%a6),%d1 # extract mode,reg + mov.w (tbl_snan.b,%pc,%d0.w*2),%a0 + jmp (tbl_snan.b,%pc,%a0) + +tbl_snan: + short fsnan_out_l - tbl_snan # long word integer + short fsnan_out_s - tbl_snan # sgl prec shouldn't happen + short fsnan_out_x - tbl_snan # ext prec shouldn't happen + short tbl_snan - tbl_snan # packed needs no help + short fsnan_out_w - tbl_snan # word integer + short fsnan_out_d - tbl_snan # dbl prec shouldn't happen + short fsnan_out_b - tbl_snan # byte integer + short tbl_snan - tbl_snan # packed needs no help + +fsnan_out_b: + mov.b FP_SRC_HI(%a6),%d0 # load upper byte of SNAN + bset &6,%d0 # set SNAN bit + cmpi.b %d1,&0x7 # is mode a data reg? + ble.b fsnan_out_b_dn # yes + mov.l EXC_EA(%a6),%a0 # pass: of default result + bsr.l _dmem_write_byte # write the default result + + tst.l %d1 # did dstore fail? + bne.l facc_out_b # yes + + bra.w fsnan_exit +fsnan_out_b_dn: + andi.w &0x0007,%d1 + bsr.l store_dreg_b # store result to regfile + bra.w fsnan_exit + +fsnan_out_w: + mov.w FP_SRC_HI(%a6),%d0 # load upper word of SNAN + bset &14,%d0 # set SNAN bit + cmpi.b %d1,&0x7 # is mode a data reg? + ble.b fsnan_out_w_dn # yes + mov.l EXC_EA(%a6),%a0 # pass: of default result + bsr.l _dmem_write_word # write the default result + + tst.l %d1 # did dstore fail? + bne.l facc_out_w # yes + + bra.w fsnan_exit +fsnan_out_w_dn: + andi.w &0x0007,%d1 + bsr.l store_dreg_w # store result to regfile + bra.w fsnan_exit + +fsnan_out_l: + mov.l FP_SRC_HI(%a6),%d0 # load upper longword of SNAN + bset &30,%d0 # set SNAN bit + cmpi.b %d1,&0x7 # is mode a data reg? + ble.b fsnan_out_l_dn # yes + mov.l EXC_EA(%a6),%a0 # pass: of default result + bsr.l _dmem_write_long # write the default result + + tst.l %d1 # did dstore fail? + bne.l facc_out_l # yes + + bra.w fsnan_exit +fsnan_out_l_dn: + andi.w &0x0007,%d1 + bsr.l store_dreg_l # store result to regfile + bra.w fsnan_exit + +fsnan_out_s: + cmpi.b %d1,&0x7 # is mode a data reg? + ble.b fsnan_out_d_dn # yes + mov.l FP_SRC_EX(%a6),%d0 # fetch SNAN sign + andi.l &0x80000000,%d0 # keep sign + ori.l &0x7fc00000,%d0 # insert new exponent,SNAN bit + mov.l FP_SRC_HI(%a6),%d1 # load mantissa + lsr.l &0x8,%d1 # shift mantissa for sgl + or.l %d1,%d0 # create sgl SNAN + mov.l EXC_EA(%a6),%a0 # pass: of default result + bsr.l _dmem_write_long # write the default result + + tst.l %d1 # did dstore fail? + bne.l facc_out_l # yes + + bra.w fsnan_exit +fsnan_out_d_dn: + mov.l FP_SRC_EX(%a6),%d0 # fetch SNAN sign + andi.l &0x80000000,%d0 # keep sign + ori.l &0x7fc00000,%d0 # insert new exponent,SNAN bit + mov.l %d1,-(%sp) + mov.l FP_SRC_HI(%a6),%d1 # load mantissa + lsr.l &0x8,%d1 # shift mantissa for sgl + or.l %d1,%d0 # create sgl SNAN + mov.l (%sp)+,%d1 + andi.w &0x0007,%d1 + bsr.l store_dreg_l # store result to regfile + bra.w fsnan_exit + +fsnan_out_d: + mov.l FP_SRC_EX(%a6),%d0 # fetch SNAN sign + andi.l &0x80000000,%d0 # keep sign + ori.l &0x7ff80000,%d0 # insert new exponent,SNAN bit + mov.l FP_SRC_HI(%a6),%d1 # load hi mantissa + mov.l %d0,FP_SCR0_EX(%a6) # store to temp space + mov.l &11,%d0 # load shift amt + lsr.l %d0,%d1 + or.l %d1,FP_SCR0_EX(%a6) # create dbl hi + mov.l FP_SRC_HI(%a6),%d1 # load hi mantissa + andi.l &0x000007ff,%d1 + ror.l %d0,%d1 + mov.l %d1,FP_SCR0_HI(%a6) # store to temp space + mov.l FP_SRC_LO(%a6),%d1 # load lo mantissa + lsr.l %d0,%d1 + or.l %d1,FP_SCR0_HI(%a6) # create dbl lo + lea FP_SCR0(%a6),%a0 # pass: ptr to operand + mov.l EXC_EA(%a6),%a1 # pass: dst addr + movq.l &0x8,%d0 # pass: size of 8 bytes + bsr.l _dmem_write # write the default result + + tst.l %d1 # did dstore fail? + bne.l facc_out_d # yes + + bra.w fsnan_exit + +# for extended precision, if the addressing mode is pre-decrement or +# post-increment, then the address register did not get updated. +# in addition, for pre-decrement, the stacked is incorrect. +fsnan_out_x: + clr.b SPCOND_FLG(%a6) # clear special case flag + + mov.w FP_SRC_EX(%a6),FP_SCR0_EX(%a6) + clr.w 2+FP_SCR0(%a6) + mov.l FP_SRC_HI(%a6),%d0 + bset &30,%d0 + mov.l %d0,FP_SCR0_HI(%a6) + mov.l FP_SRC_LO(%a6),FP_SCR0_LO(%a6) + + btst &0x5,EXC_SR(%a6) # supervisor mode exception? + bne.b fsnan_out_x_s # yes + + mov.l %usp,%a0 # fetch user stack pointer + mov.l %a0,EXC_A7(%a6) # save on stack for calc_ea() + mov.l (%a6),EXC_A6(%a6) + + bsr.l _calc_ea_fout # find the correct ea,update An + mov.l %a0,%a1 + mov.l %a0,EXC_EA(%a6) # stack correct + + mov.l EXC_A7(%a6),%a0 + mov.l %a0,%usp # restore user stack pointer + mov.l EXC_A6(%a6),(%a6) + +fsnan_out_x_save: + lea FP_SCR0(%a6),%a0 # pass: ptr to operand + movq.l &0xc,%d0 # pass: size of extended + bsr.l _dmem_write # write the default result + + tst.l %d1 # did dstore fail? + bne.l facc_out_x # yes + + bra.w fsnan_exit + +fsnan_out_x_s: + mov.l (%a6),EXC_A6(%a6) + + bsr.l _calc_ea_fout # find the correct ea,update An + mov.l %a0,%a1 + mov.l %a0,EXC_EA(%a6) # stack correct + + mov.l EXC_A6(%a6),(%a6) + + cmpi.b SPCOND_FLG(%a6),&mda7_flg # is mode -(a7)? + bne.b fsnan_out_x_save # no + +# the operation was "fmove.x SNAN,-(a7)" from supervisor mode. + fmovm.x EXC_FPREGS(%a6),&0xc0 # restore fp0-fp1 + fmovm.l USER_FPCR(%a6),%fpcr,%fpsr,%fpiar # restore ctrl regs + movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 + + frestore FP_SRC(%a6) + + mov.l EXC_A6(%a6),%a6 # restore frame pointer + + mov.l LOCAL_SIZE+EXC_SR(%sp),LOCAL_SIZE+EXC_SR-0xc(%sp) + mov.l LOCAL_SIZE+EXC_PC+0x2(%sp),LOCAL_SIZE+EXC_PC+0x2-0xc(%sp) + mov.l LOCAL_SIZE+EXC_EA(%sp),LOCAL_SIZE+EXC_EA-0xc(%sp) + + mov.l LOCAL_SIZE+FP_SCR0_EX(%sp),LOCAL_SIZE+EXC_SR(%sp) + mov.l LOCAL_SIZE+FP_SCR0_HI(%sp),LOCAL_SIZE+EXC_PC+0x2(%sp) + mov.l LOCAL_SIZE+FP_SCR0_LO(%sp),LOCAL_SIZE+EXC_EA(%sp) + + add.l &LOCAL_SIZE-0x8,%sp + + bra.l _real_snan + +######################################################################### +# XDEF **************************************************************** # +# _fpsp_inex(): 060FPSP entry point for FP Inexact exception. # +# # +# This handler should be the first code executed upon taking the # +# FP Inexact exception in an operating system. # +# # +# XREF **************************************************************** # +# _imem_read_long() - read instruction longword # +# fix_skewed_ops() - adjust src operand in fsave frame # +# set_tag_x() - determine optype of src/dst operands # +# store_fpreg() - store opclass 0 or 2 result to FP regfile # +# unnorm_fix() - change UNNORM operands to NORM or ZERO # +# load_fpn2() - load dst operand from FP regfile # +# smovcr() - emulate an "fmovcr" instruction # +# fout() - emulate an opclass 3 instruction # +# tbl_unsupp - add of table of emulation routines for opclass 0,2 # +# _real_inex() - "callout" to operating system inexact handler # +# # +# INPUT *************************************************************** # +# - The system stack contains the FP Inexact exception frame # +# - The fsave frame contains the source operand # +# # +# OUTPUT ************************************************************** # +# - The system stack is unchanged # +# - The fsave frame contains the adjusted src op for opclass 0,2 # +# # +# ALGORITHM *********************************************************** # +# In a system where the FP Inexact exception is enabled, the goal # +# is to get to the handler specified at _real_inex(). But, on the 060, # +# for opclass zero and two instruction taking this exception, the # +# hardware doesn't store the correct result to the destination FP # +# register as did the '040 and '881/2. This handler must emulate the # +# instruction in order to get this value and then store it to the # +# correct register before calling _real_inex(). # +# For opclass 3 instructions, the 060 doesn't store the default # +# inexact result out to memory or data register file as it should. # +# This code must emulate the move out by calling fout() before finally # +# exiting through _real_inex(). # +# # +######################################################################### + + global _fpsp_inex +_fpsp_inex: + + link.w %a6,&-LOCAL_SIZE # init stack frame + + fsave FP_SRC(%a6) # grab the "busy" frame + + movm.l &0x0303,EXC_DREGS(%a6) # save d0-d1/a0-a1 + fmovm.l %fpcr,%fpsr,%fpiar,USER_FPCR(%a6) # save ctrl regs + fmovm.x &0xc0,EXC_FPREGS(%a6) # save fp0-fp1 on stack + +# the FPIAR holds the "current PC" of the faulting instruction + mov.l USER_FPIAR(%a6),EXC_EXTWPTR(%a6) + + mov.l EXC_EXTWPTR(%a6),%a0 # fetch instruction addr + addq.l &0x4,EXC_EXTWPTR(%a6) # incr instruction ptr + bsr.l _imem_read_long # fetch the instruction words + mov.l %d0,EXC_OPWORD(%a6) + +############################################################################## + + btst &13,%d0 # is instr an fmove out? + bne.w finex_out # fmove out + + +# the hardware, for "fabs" and "fneg" w/ a long source format, puts the +# longword integer directly into the upper longword of the mantissa along +# w/ an exponent value of 0x401e. we convert this to extended precision here. + bfextu %d0{&19:&3},%d0 # fetch instr size + bne.b finex_cont # instr size is not long + cmpi.w FP_SRC_EX(%a6),&0x401e # is exponent 0x401e? + bne.b finex_cont # no + fmov.l &0x0,%fpcr + fmov.l FP_SRC_HI(%a6),%fp0 # load integer src + fmov.x %fp0,FP_SRC(%a6) # store integer as extended precision + mov.w &0xe001,0x2+FP_SRC(%a6) + +finex_cont: + lea FP_SRC(%a6),%a0 # pass: ptr to src op + bsr.l fix_skewed_ops # fix src op + +# Here, we zero the ccode and exception byte field since we're going to +# emulate the whole instruction. Notice, though, that we don't kill the +# INEX1 bit. This is because a packed op has long since been converted +# to extended before arriving here. Therefore, we need to retain the +# INEX1 bit from when the operand was first converted. + andi.l &0x00ff01ff,USER_FPSR(%a6) # zero all but accured field + + fmov.l &0x0,%fpcr # zero current control regs + fmov.l &0x0,%fpsr + + bfextu EXC_EXTWORD(%a6){&0:&6},%d1 # extract upper 6 of cmdreg + cmpi.b %d1,&0x17 # is op an fmovecr? + beq.w finex_fmovcr # yes + + lea FP_SRC(%a6),%a0 # pass: ptr to src op + bsr.l set_tag_x # tag the operand type + mov.b %d0,STAG(%a6) # maybe NORM,DENORM + +# bits four and five of the fp extension word separate the monadic and dyadic +# operations that can pass through fpsp_inex(). remember that fcmp and ftst +# will never take this exception, but fsincos will. + btst &0x5,1+EXC_CMDREG(%a6) # is operation monadic or dyadic? + beq.b finex_extract # monadic + + btst &0x4,1+EXC_CMDREG(%a6) # is operation an fsincos? + bne.b finex_extract # yes + + bfextu EXC_CMDREG(%a6){&6:&3},%d0 # dyadic; load dst reg + bsr.l load_fpn2 # load dst into FP_DST + + lea FP_DST(%a6),%a0 # pass: ptr to dst op + bsr.l set_tag_x # tag the operand type + cmpi.b %d0,&UNNORM # is operand an UNNORM? + bne.b finex_op2_done # no + bsr.l unnorm_fix # yes; convert to NORM,DENORM,or ZERO +finex_op2_done: + mov.b %d0,DTAG(%a6) # save dst optype tag + +finex_extract: + clr.l %d0 + mov.b FPCR_MODE(%a6),%d0 # pass rnd prec/mode + + mov.b 1+EXC_CMDREG(%a6),%d1 + andi.w &0x007f,%d1 # extract extension + + lea FP_SRC(%a6),%a0 + lea FP_DST(%a6),%a1 + + mov.l (tbl_unsupp.l,%pc,%d1.w*4),%d1 # fetch routine addr + jsr (tbl_unsupp.l,%pc,%d1.l*1) + +# the operation has been emulated. the result is in fp0. +finex_save: + bfextu EXC_CMDREG(%a6){&6:&3},%d0 + bsr.l store_fpreg + +finex_exit: + fmovm.x EXC_FPREGS(%a6),&0xc0 # restore fp0-fp1 + fmovm.l USER_FPCR(%a6),%fpcr,%fpsr,%fpiar # restore ctrl regs + movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 + + frestore FP_SRC(%a6) + + unlk %a6 + bra.l _real_inex + +finex_fmovcr: + clr.l %d0 + mov.b FPCR_MODE(%a6),%d0 # pass rnd prec,mode + mov.b 1+EXC_CMDREG(%a6),%d1 + andi.l &0x0000007f,%d1 # pass rom offset + bsr.l smovcr + bra.b finex_save + +######################################################################## + +# +# the hardware does not save the default result to memory on enabled +# inexact exceptions. we do this here before passing control to +# the user inexact handler. +# +# byte, word, and long destination format operations can pass +# through here. so can double and single precision. +# although packed opclass three operations can take inexact +# exceptions, they won't pass through here since they are caught +# first by the unsupported data format exception handler. that handler +# sends them directly to _real_inex() if necessary. +# +finex_out: + + mov.b &NORM,STAG(%a6) # src is a NORM + + clr.l %d0 + mov.b FPCR_MODE(%a6),%d0 # pass rnd prec,mode + + andi.l &0xffff00ff,USER_FPSR(%a6) # zero exception field + + lea FP_SRC(%a6),%a0 # pass ptr to src operand + + bsr.l fout # store the default result + + bra.b finex_exit + +######################################################################### +# XDEF **************************************************************** # +# _fpsp_dz(): 060FPSP entry point for FP DZ exception. # +# # +# This handler should be the first code executed upon taking # +# the FP DZ exception in an operating system. # +# # +# XREF **************************************************************** # +# _imem_read_long() - read instruction longword from memory # +# fix_skewed_ops() - adjust fsave operand # +# _real_dz() - "callout" exit point from FP DZ handler # +# # +# INPUT *************************************************************** # +# - The system stack contains the FP DZ exception stack. # +# - The fsave frame contains the source operand. # +# # +# OUTPUT ************************************************************** # +# - The system stack contains the FP DZ exception stack. # +# - The fsave frame contains the adjusted source operand. # +# # +# ALGORITHM *********************************************************** # +# In a system where the DZ exception is enabled, the goal is to # +# get to the handler specified at _real_dz(). But, on the 060, when the # +# exception is taken, the input operand in the fsave state frame may # +# be incorrect for some cases and need to be adjusted. So, this package # +# adjusts the operand using fix_skewed_ops() and then branches to # +# _real_dz(). # +# # +######################################################################### + + global _fpsp_dz +_fpsp_dz: + + link.w %a6,&-LOCAL_SIZE # init stack frame + + fsave FP_SRC(%a6) # grab the "busy" frame + + movm.l &0x0303,EXC_DREGS(%a6) # save d0-d1/a0-a1 + fmovm.l %fpcr,%fpsr,%fpiar,USER_FPCR(%a6) # save ctrl regs + fmovm.x &0xc0,EXC_FPREGS(%a6) # save fp0-fp1 on stack + +# the FPIAR holds the "current PC" of the faulting instruction + mov.l USER_FPIAR(%a6),EXC_EXTWPTR(%a6) + + mov.l EXC_EXTWPTR(%a6),%a0 # fetch instruction addr + addq.l &0x4,EXC_EXTWPTR(%a6) # incr instruction ptr + bsr.l _imem_read_long # fetch the instruction words + mov.l %d0,EXC_OPWORD(%a6) + +############################################################################## + + +# here, we simply see if the operand in the fsave frame needs to be "unskewed". +# this would be the case for opclass two operations with a source zero +# in the sgl or dbl format. + lea FP_SRC(%a6),%a0 # pass: ptr to src op + bsr.l fix_skewed_ops # fix src op + +fdz_exit: + fmovm.x EXC_FPREGS(%a6),&0xc0 # restore fp0-fp1 + fmovm.l USER_FPCR(%a6),%fpcr,%fpsr,%fpiar # restore ctrl regs + movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 + + frestore FP_SRC(%a6) + + unlk %a6 + bra.l _real_dz + +######################################################################### +# XDEF **************************************************************** # +# _fpsp_fline(): 060FPSP entry point for "Line F emulator" exc. # +# # +# This handler should be the first code executed upon taking the # +# "Line F Emulator" exception in an operating system. # +# # +# XREF **************************************************************** # +# _fpsp_unimp() - handle "FP Unimplemented" exceptions # +# _real_fpu_disabled() - handle "FPU disabled" exceptions # +# _real_fline() - handle "FLINE" exceptions # +# _imem_read_long() - read instruction longword # +# # +# INPUT *************************************************************** # +# - The system stack contains a "Line F Emulator" exception # +# stack frame. # +# # +# OUTPUT ************************************************************** # +# - The system stack is unchanged # +# # +# ALGORITHM *********************************************************** # +# When a "Line F Emulator" exception occurs, there are 3 possible # +# exception types, denoted by the exception stack frame format number: # +# (1) FPU unimplemented instruction (6 word stack frame) # +# (2) FPU disabled (8 word stack frame) # +# (3) Line F (4 word stack frame) # +# # +# This module determines which and forks the flow off to the # +# appropriate "callout" (for "disabled" and "Line F") or to the # +# correct emulation code (for "FPU unimplemented"). # +# This code also must check for "fmovecr" instructions w/ a # +# non-zero field. These may get flagged as "Line F" but should # +# really be flagged as "FPU Unimplemented". (This is a "feature" on # +# the '060. # +# # +######################################################################### + + global _fpsp_fline +_fpsp_fline: + +# check to see if this exception is a "FP Unimplemented Instruction" +# exception. if so, branch directly to that handler's entry point. + cmpi.w 0x6(%sp),&0x202c + beq.l _fpsp_unimp + +# check to see if the FPU is disabled. if so, jump to the OS entry +# point for that condition. + cmpi.w 0x6(%sp),&0x402c + beq.l _real_fpu_disabled + +# the exception was an "F-Line Illegal" exception. we check to see +# if the F-Line instruction is an "fmovecr" w/ a non-zero . if +# so, convert the F-Line exception stack frame to an FP Unimplemented +# Instruction exception stack frame else branch to the OS entry +# point for the F-Line exception handler. + link.w %a6,&-LOCAL_SIZE # init stack frame + + movm.l &0x0303,EXC_DREGS(%a6) # save d0-d1/a0-a1 + + mov.l EXC_PC(%a6),EXC_EXTWPTR(%a6) + mov.l EXC_EXTWPTR(%a6),%a0 # fetch instruction addr + addq.l &0x4,EXC_EXTWPTR(%a6) # incr instruction ptr + bsr.l _imem_read_long # fetch instruction words + + bfextu %d0{&0:&10},%d1 # is it an fmovecr? + cmpi.w %d1,&0x03c8 + bne.b fline_fline # no + + bfextu %d0{&16:&6},%d1 # is it an fmovecr? + cmpi.b %d1,&0x17 + bne.b fline_fline # no + +# it's an fmovecr w/ a non-zero that has entered through +# the F-Line Illegal exception. +# so, we need to convert the F-Line exception stack frame into an +# FP Unimplemented Instruction stack frame and jump to that entry +# point. +# +# but, if the FPU is disabled, then we need to jump to the FPU disabled +# entry point. + movc %pcr,%d0 + btst &0x1,%d0 + beq.b fline_fmovcr + + movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 + + unlk %a6 + + sub.l &0x8,%sp # make room for "Next PC", + mov.w 0x8(%sp),(%sp) + mov.l 0xa(%sp),0x2(%sp) # move "Current PC" + mov.w &0x402c,0x6(%sp) + mov.l 0x2(%sp),0xc(%sp) + addq.l &0x4,0x2(%sp) # set "Next PC" + + bra.l _real_fpu_disabled + +fline_fmovcr: + movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 + + unlk %a6 + + fmov.l 0x2(%sp),%fpiar # set current PC + addq.l &0x4,0x2(%sp) # set Next PC + + mov.l (%sp),-(%sp) + mov.l 0x8(%sp),0x4(%sp) + mov.b &0x20,0x6(%sp) + + bra.l _fpsp_unimp + +fline_fline: + movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 + + unlk %a6 + + bra.l _real_fline + +######################################################################### +# XDEF **************************************************************** # +# _fpsp_unimp(): 060FPSP entry point for FP "Unimplemented # +# Instruction" exception. # +# # +# This handler should be the first code executed upon taking the # +# FP Unimplemented Instruction exception in an operating system. # +# # +# XREF **************************************************************** # +# _imem_read_{word,long}() - read instruction word/longword # +# load_fop() - load src/dst ops from memory and/or FP regfile # +# store_fpreg() - store opclass 0 or 2 result to FP regfile # +# tbl_trans - addr of table of emulation routines for trnscndls # +# _real_access() - "callout" for access error exception # +# _fpsp_done() - "callout" for exit; work all done # +# _real_trace() - "callout" for Trace enabled exception # +# smovcr() - emulate "fmovecr" instruction # +# funimp_skew() - adjust fsave src ops to "incorrect" value # +# _ftrapcc() - emulate an "ftrapcc" instruction # +# _fdbcc() - emulate an "fdbcc" instruction # +# _fscc() - emulate an "fscc" instruction # +# _real_trap() - "callout" for Trap exception # +# _real_bsun() - "callout" for enabled Bsun exception # +# # +# INPUT *************************************************************** # +# - The system stack contains the "Unimplemented Instr" stk frame # +# # +# OUTPUT ************************************************************** # +# If access error: # +# - The system stack is changed to an access error stack frame # +# If Trace exception enabled: # +# - The system stack is changed to a Trace exception stack frame # +# Else: (normal case) # +# - Correct result has been stored as appropriate # +# # +# ALGORITHM *********************************************************** # +# There are two main cases of instructions that may enter here to # +# be emulated: (1) the FPgen instructions, most of which were also # +# unimplemented on the 040, and (2) "ftrapcc", "fscc", and "fdbcc". # +# For the first set, this handler calls the routine load_fop() # +# to load the source and destination (for dyadic) operands to be used # +# for instruction emulation. The correct emulation routine is then # +# chosen by decoding the instruction type and indexing into an # +# emulation subroutine index table. After emulation returns, this # +# handler checks to see if an exception should occur as a result of the # +# FP instruction emulation. If so, then an FP exception of the correct # +# type is inserted into the FPU state frame using the "frestore" # +# instruction before exiting through _fpsp_done(). In either the # +# exceptional or non-exceptional cases, we must check to see if the # +# Trace exception is enabled. If so, then we must create a Trace # +# exception frame from the current exception frame and exit through # +# _real_trace(). # +# For "fdbcc", "ftrapcc", and "fscc", the emulation subroutines # +# _fdbcc(), _ftrapcc(), and _fscc() respectively are used. All three # +# may flag that a BSUN exception should be taken. If so, then the # +# current exception stack frame is converted into a BSUN exception # +# stack frame and an exit is made through _real_bsun(). If the # +# instruction was "ftrapcc" and a Trap exception should result, a Trap # +# exception stack frame is created from the current frame and an exit # +# is made through _real_trap(). If a Trace exception is pending, then # +# a Trace exception frame is created from the current frame and a jump # +# is made to _real_trace(). Finally, if none of these conditions exist, # +# then the handler exits though the callout _fpsp_done(). # +# # +# In any of the above scenarios, if a _mem_read() or _mem_write() # +# "callout" returns a failing value, then an access error stack frame # +# is created from the current stack frame and an exit is made through # +# _real_access(). # +# # +######################################################################### + +# +# FP UNIMPLEMENTED INSTRUCTION STACK FRAME: +# +# ***************** +# * * => of fp unimp instr. +# - EA - +# * * +# ***************** +# * 0x2 * 0x02c * => frame format and vector offset(vector #11) +# ***************** +# * * +# - Next PC - => PC of instr to execute after exc handling +# * * +# ***************** +# * SR * => SR at the time the exception was taken +# ***************** +# +# Note: the !NULL bit does not get set in the fsave frame when the +# machine encounters an fp unimp exception. Therefore, it must be set +# before leaving this handler. +# + global _fpsp_unimp +_fpsp_unimp: + + link.w %a6,&-LOCAL_SIZE # init stack frame + + movm.l &0x0303,EXC_DREGS(%a6) # save d0-d1/a0-a1 + fmovm.l %fpcr,%fpsr,%fpiar,USER_FPCR(%a6) # save ctrl regs + fmovm.x &0xc0,EXC_FPREGS(%a6) # save fp0-fp1 + + btst &0x5,EXC_SR(%a6) # user mode exception? + bne.b funimp_s # no; supervisor mode + +# save the value of the user stack pointer onto the stack frame +funimp_u: + mov.l %usp,%a0 # fetch user stack pointer + mov.l %a0,EXC_A7(%a6) # store in stack frame + bra.b funimp_cont + +# store the value of the supervisor stack pointer BEFORE the exc occurred. +# old_sp is address just above stacked effective address. +funimp_s: + lea 4+EXC_EA(%a6),%a0 # load old a7' + mov.l %a0,EXC_A7(%a6) # store a7' + mov.l %a0,OLD_A7(%a6) # make a copy + +funimp_cont: + +# the FPIAR holds the "current PC" of the faulting instruction. + mov.l USER_FPIAR(%a6),EXC_EXTWPTR(%a6) + + mov.l EXC_EXTWPTR(%a6),%a0 # fetch instruction addr + addq.l &0x4,EXC_EXTWPTR(%a6) # incr instruction ptr + bsr.l _imem_read_long # fetch the instruction words + mov.l %d0,EXC_OPWORD(%a6) + +############################################################################ + + fmov.l &0x0,%fpcr # clear FPCR + fmov.l &0x0,%fpsr # clear FPSR + + clr.b SPCOND_FLG(%a6) # clear "special case" flag + +# Divide the fp instructions into 8 types based on the TYPE field in +# bits 6-8 of the opword(classes 6,7 are undefined). +# (for the '060, only two types can take this exception) +# bftst %d0{&7:&3} # test TYPE + btst &22,%d0 # type 0 or 1 ? + bne.w funimp_misc # type 1 + +######################################### +# TYPE == 0: General instructions # +######################################### +funimp_gen: + + clr.b STORE_FLG(%a6) # clear "store result" flag + +# clear the ccode byte and exception status byte + andi.l &0x00ff00ff,USER_FPSR(%a6) + + bfextu %d0{&16:&6},%d1 # extract upper 6 of cmdreg + cmpi.b %d1,&0x17 # is op an fmovecr? + beq.w funimp_fmovcr # yes + +funimp_gen_op: + bsr.l _load_fop # load + + clr.l %d0 + mov.b FPCR_MODE(%a6),%d0 # fetch rnd mode + + mov.b 1+EXC_CMDREG(%a6),%d1 + andi.w &0x003f,%d1 # extract extension bits + lsl.w &0x3,%d1 # shift right 3 bits + or.b STAG(%a6),%d1 # insert src optag bits + + lea FP_DST(%a6),%a1 # pass dst ptr in a1 + lea FP_SRC(%a6),%a0 # pass src ptr in a0 + + mov.w (tbl_trans.w,%pc,%d1.w*2),%d1 + jsr (tbl_trans.w,%pc,%d1.w*1) # emulate + +funimp_fsave: + mov.b FPCR_ENABLE(%a6),%d0 # fetch exceptions enabled + bne.w funimp_ena # some are enabled + +funimp_store: + bfextu EXC_CMDREG(%a6){&6:&3},%d0 # fetch Dn + bsr.l store_fpreg # store result to fp regfile + +funimp_gen_exit: + fmovm.x EXC_FP0(%a6),&0xc0 # restore fp0-fp1 + fmovm.l USER_FPCR(%a6),%fpcr,%fpsr,%fpiar # restore ctrl regs + movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 + +funimp_gen_exit_cmp: + cmpi.b SPCOND_FLG(%a6),&mia7_flg # was the ea mode (sp)+ ? + beq.b funimp_gen_exit_a7 # yes + + cmpi.b SPCOND_FLG(%a6),&mda7_flg # was the ea mode -(sp) ? + beq.b funimp_gen_exit_a7 # yes + +funimp_gen_exit_cont: + unlk %a6 + +funimp_gen_exit_cont2: + btst &0x7,(%sp) # is trace on? + beq.l _fpsp_done # no + +# this catches a problem with the case where an exception will be re-inserted +# into the machine. the frestore has already been executed...so, the fmov.l +# alone of the control register would trigger an unwanted exception. +# until I feel like fixing this, we'll sidestep the exception. + fsave -(%sp) + fmov.l %fpiar,0x14(%sp) # "Current PC" is in FPIAR + frestore (%sp)+ + mov.w &0x2024,0x6(%sp) # stk fmt = 0x2; voff = 0x24 + bra.l _real_trace + +funimp_gen_exit_a7: + btst &0x5,EXC_SR(%a6) # supervisor or user mode? + bne.b funimp_gen_exit_a7_s # supervisor + + mov.l %a0,-(%sp) + mov.l EXC_A7(%a6),%a0 + mov.l %a0,%usp + mov.l (%sp)+,%a0 + bra.b funimp_gen_exit_cont + +# if the instruction was executed from supervisor mode and the addressing +# mode was (a7)+, then the stack frame for the rte must be shifted "up" +# "n" bytes where "n" is the size of the src operand type. +# f.{b,w,l,s,d,x,p} +funimp_gen_exit_a7_s: + mov.l %d0,-(%sp) # save d0 + mov.l EXC_A7(%a6),%d0 # load new a7' + sub.l OLD_A7(%a6),%d0 # subtract old a7' + mov.l 0x2+EXC_PC(%a6),(0x2+EXC_PC,%a6,%d0) # shift stack frame + mov.l EXC_SR(%a6),(EXC_SR,%a6,%d0) # shift stack frame + mov.w %d0,EXC_SR(%a6) # store incr number + mov.l (%sp)+,%d0 # restore d0 + + unlk %a6 + + add.w (%sp),%sp # stack frame shifted + bra.b funimp_gen_exit_cont2 + +###################### +# fmovecr.x #ccc,fpn # +###################### +funimp_fmovcr: + clr.l %d0 + mov.b FPCR_MODE(%a6),%d0 + mov.b 1+EXC_CMDREG(%a6),%d1 + andi.l &0x0000007f,%d1 # pass rom offset in d1 + bsr.l smovcr + bra.w funimp_fsave + +######################################################################### + +# +# the user has enabled some exceptions. we figure not to see this too +# often so that's why it gets lower priority. +# +funimp_ena: + +# was an exception set that was also enabled? + and.b FPSR_EXCEPT(%a6),%d0 # keep only ones enabled and set + bfffo %d0{&24:&8},%d0 # find highest priority exception + bne.b funimp_exc # at least one was set + +# no exception that was enabled was set BUT if we got an exact overflow +# and overflow wasn't enabled but inexact was (yech!) then this is +# an inexact exception; otherwise, return to normal non-exception flow. + btst &ovfl_bit,FPSR_EXCEPT(%a6) # did overflow occur? + beq.w funimp_store # no; return to normal flow + +# the overflow w/ exact result happened but was inexact set in the FPCR? +funimp_ovfl: + btst &inex2_bit,FPCR_ENABLE(%a6) # is inexact enabled? + beq.w funimp_store # no; return to normal flow + bra.b funimp_exc_ovfl # yes + +# some exception happened that was actually enabled. +# we'll insert this new exception into the FPU and then return. +funimp_exc: + subi.l &24,%d0 # fix offset to be 0-8 + cmpi.b %d0,&0x6 # is exception INEX? + bne.b funimp_exc_force # no + +# the enabled exception was inexact. so, if it occurs with an overflow +# or underflow that was disabled, then we have to force an overflow or +# underflow frame. the eventual overflow or underflow handler will see that +# it's actually an inexact and act appropriately. this is the only easy +# way to have the EXOP available for the enabled inexact handler when +# a disabled overflow or underflow has also happened. + btst &ovfl_bit,FPSR_EXCEPT(%a6) # did overflow occur? + bne.b funimp_exc_ovfl # yes + btst &unfl_bit,FPSR_EXCEPT(%a6) # did underflow occur? + bne.b funimp_exc_unfl # yes + +# force the fsave exception status bits to signal an exception of the +# appropriate type. don't forget to "skew" the source operand in case we +# "unskewed" the one the hardware initially gave us. +funimp_exc_force: + mov.l %d0,-(%sp) # save d0 + bsr.l funimp_skew # check for special case + mov.l (%sp)+,%d0 # restore d0 + mov.w (tbl_funimp_except.b,%pc,%d0.w*2),2+FP_SRC(%a6) + bra.b funimp_gen_exit2 # exit with frestore + +tbl_funimp_except: + short 0xe002, 0xe006, 0xe004, 0xe005 + short 0xe003, 0xe002, 0xe001, 0xe001 + +# insert an overflow frame +funimp_exc_ovfl: + bsr.l funimp_skew # check for special case + mov.w &0xe005,2+FP_SRC(%a6) + bra.b funimp_gen_exit2 + +# insert an underflow frame +funimp_exc_unfl: + bsr.l funimp_skew # check for special case + mov.w &0xe003,2+FP_SRC(%a6) + +# this is the general exit point for an enabled exception that will be +# restored into the machine for the instruction just emulated. +funimp_gen_exit2: + fmovm.x EXC_FP0(%a6),&0xc0 # restore fp0-fp1 + fmovm.l USER_FPCR(%a6),%fpcr,%fpsr,%fpiar # restore ctrl regs + movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 + + frestore FP_SRC(%a6) # insert exceptional status + + bra.w funimp_gen_exit_cmp + +############################################################################ + +# +# TYPE == 1: FDB, FS, FTRAP +# +# These instructions were implemented on the '881/2 and '040 in hardware but +# are emulated in software on the '060. +# +funimp_misc: + bfextu %d0{&10:&3},%d1 # extract mode field + cmpi.b %d1,&0x1 # is it an fdb? + beq.w funimp_fdbcc # yes + cmpi.b %d1,&0x7 # is it an fs? + bne.w funimp_fscc # yes + bfextu %d0{&13:&3},%d1 + cmpi.b %d1,&0x2 # is it an fs? + blt.w funimp_fscc # yes + +######################### +# ftrap # +# ftrap.w # # +# ftrap.l # # +######################### +funimp_ftrapcc: + + bsr.l _ftrapcc # FTRAP() + + cmpi.b SPCOND_FLG(%a6),&fbsun_flg # is enabled bsun occurring? + beq.w funimp_bsun # yes + + cmpi.b SPCOND_FLG(%a6),&ftrapcc_flg # should a trap occur? + bne.w funimp_done # no + +# FP UNIMP FRAME TRAP FRAME +# ***************** ***************** +# ** ** ** Current PC ** +# ***************** ***************** +# * 0x2 * 0x02c * * 0x2 * 0x01c * +# ***************** ***************** +# ** Next PC ** ** Next PC ** +# ***************** ***************** +# * SR * * SR * +# ***************** ***************** +# (6 words) (6 words) +# +# the ftrapcc instruction should take a trap. so, here we must create a +# trap stack frame from an unimplemented fp instruction stack frame and +# jump to the user supplied entry point for the trap exception +funimp_ftrapcc_tp: + mov.l USER_FPIAR(%a6),EXC_EA(%a6) # Address = Current PC + mov.w &0x201c,EXC_VOFF(%a6) # Vector Offset = 0x01c + + fmovm.x EXC_FP0(%a6),&0xc0 # restore fp0-fp1 + fmovm.l USER_FPCR(%a6),%fpcr,%fpsr,%fpiar # restore ctrl regs + movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 + + unlk %a6 + bra.l _real_trap + +######################### +# fdb Dn,