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/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (c) 2013, The Linux Foundation. All rights reserved.
*/
#ifndef _DT_BINDINGS_CLK_MSM_MMCC_8960_H
#define _DT_BINDINGS_CLK_MSM_MMCC_8960_H
#define MMSS_AHB_SRC 0
#define FAB_AHB_CLK 1
#define APU_AHB_CLK 2
#define TV_ENC_AHB_CLK 3
#define AMP_AHB_CLK 4
#define DSI2_S_AHB_CLK 5
#define JPEGD_AHB_CLK 6
#define GFX2D0_AHB_CLK 7
#define DSI_S_AHB_CLK 8
#define DSI2_M_AHB_CLK 9
#define VPE_AHB_CLK 10
#define SMMU_AHB_CLK 11
#define HDMI_M_AHB_CLK 12
#define VFE_AHB_CLK 13
#define ROT_AHB_CLK 14
#define VCODEC_AHB_CLK 15
#define MDP_AHB_CLK 16
#define DSI_M_AHB_CLK 17
#define CSI_AHB_CLK 18
#define MMSS_IMEM_AHB_CLK 19
#define IJPEG_AHB_CLK 20
#define HDMI_S_AHB_CLK 21
#define GFX3D_AHB_CLK 22
#define GFX2D1_AHB_CLK 23
#define MMSS_FPB_CLK 24
#define MMSS_AXI_SRC 25
#define MMSS_FAB_CORE 26
#define FAB_MSP_AXI_CLK 27
#define JPEGD_AXI_CLK 28
#define GMEM_AXI_CLK 29
#define MDP_AXI_CLK 30
#define MMSS_IMEM_AXI_CLK 31
#define IJPEG_AXI_CLK 32
#define GFX3D_AXI_CLK 33
#define VCODEC_AXI_CLK 34
#define VFE_AXI_CLK 35
#define VPE_AXI_CLK 36
#define ROT_AXI_CLK 37
#define VCODEC_AXI_A_CLK 38
#define VCODEC_AXI_B_CLK 39
#define MM_AXI_S3_FCLK 40
#define MM_AXI_S2_FCLK 41
#define MM_AXI_S1_FCLK 42
#define MM_AXI_S0_FCLK 43
#define MM_AXI_S2_CLK 44
#define MM_AXI_S1_CLK 45
#define MM_AXI_S0_CLK 46
#define CSI0_SRC 47
#define CSI0_CLK 48
#define CSI0_PHY_CLK 49
#define CSI1_SRC 50
#define CSI1_CLK 51
#define CSI1_PHY_CLK 52
#define CSI2_SRC 53
#define CSI2_CLK 54
#define CSI2_PHY_CLK 55
#define DSI_SRC 56
#define DSI_CLK 57
#define CSI_PIX_CLK 58
#define CSI_RDI_CLK 59
#define MDP_VSYNC_CLK 60
#define HDMI_DIV_CLK 61
#define HDMI_APP_CLK 62
#define CSI_PIX1_CLK 63
#define CSI_RDI2_CLK 64
#define CSI_RDI1_CLK 65
#define GFX2D0_SRC 66
#define GFX2D0_CLK 67
#define GFX2D1_SRC 68
#define GFX2D1_CLK 69
#define GFX3D_SRC 70
#define GFX3D_CLK 71
#define IJPEG_SRC 72
#define IJPEG_CLK 73
#define JPEGD_SRC 74
#define JPEGD_CLK 75
#define MDP_SRC 76
#define MDP_CLK 77
#define MDP_LUT_CLK 78
#define DSI2_PIXEL_SRC 79
#define DSI2_PIXEL_CLK 80
#define DSI2_SRC 81
#define DSI2_CLK 82
#define DSI1_BYTE_SRC 83
#define DSI1_BYTE_CLK 84
#define DSI2_BYTE_SRC 85
#define DSI2_BYTE_CLK 86
#define DSI1_ESC_SRC 87
#define DSI1_ESC_CLK 88
#define DSI2_ESC_SRC 89
#define DSI2_ESC_CLK 90
#define ROT_SRC 91
#define ROT_CLK 92
#define TV_ENC_CLK 93
#define TV_DAC_CLK 94
#define HDMI_TV_CLK 95
#define MDP_TV_CLK 96
#define TV_SRC 97
#define VCODEC_SRC 98
#define VCODEC_CLK 99
#define VFE_SRC 100
#define VFE_CLK 101
#define VFE_CSI_CLK 102
#define VPE_SRC 103
#define VPE_CLK 104
#define DSI_PIXEL_SRC 105
#define DSI_PIXEL_CLK 106
#define CAMCLK0_SRC 107
#define CAMCLK0_CLK 108
#define CAMCLK1_SRC 109
#define CAMCLK1_CLK 110
#define CAMCLK2_SRC 111
#define CAMCLK2_CLK 112
#define CSIPHYTIMER_SRC 113
#define CSIPHY2_TIMER_CLK 114
#define CSIPHY1_TIMER_CLK 115
#define CSIPHY0_TIMER_CLK 116
#define PLL1 117
#define PLL2 118
#define RGB_TV_CLK 119
#define NPL_TV_CLK 120
#define VCAP_AHB_CLK 121
#define VCAP_AXI_CLK 122
#define VCAP_SRC 123
#define VCAP_CLK 124
#define VCAP_NPL_CLK 125
#define PLL15 126
#endif
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