summaryrefslogtreecommitdiffstats
path: root/tools/perf/pmu-events/arch/x86/jaketown/frontend.json
blob: 1b7b1dd36c68ec25614a836aa6a0387bd92ad94f (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
[
    {
        "EventCode": "0x80",
        "Counter": "0,1,2,3",
        "UMask": "0x1",
        "EventName": "ICACHE.HIT",
        "SampleAfterValue": "2000003",
        "BriefDescription": "Number of Instruction Cache, Streaming Buffer and Victim Cache Reads. both cacheable and noncacheable, including UC fetches.",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "PublicDescription": "This event counts the number of instruction cache, streaming buffer and victim cache misses. Counting includes unchacheable accesses.",
        "EventCode": "0x80",
        "Counter": "0,1,2,3",
        "UMask": "0x2",
        "EventName": "ICACHE.MISSES",
        "SampleAfterValue": "200003",
        "BriefDescription": "Instruction cache, streaming buffer and victim cache misses.",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "EventCode": "0x79",
        "Counter": "0,1,2,3",
        "UMask": "0x2",
        "EventName": "IDQ.EMPTY",
        "SampleAfterValue": "2000003",
        "BriefDescription": "Instruction Decode Queue (IDQ) empty cycles.",
        "CounterHTOff": "0,1,2,3"
    },
    {
        "EventCode": "0x79",
        "Counter": "0,1,2,3",
        "UMask": "0x4",
        "EventName": "IDQ.MITE_UOPS",
        "SampleAfterValue": "2000003",
        "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from MITE path.",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "EventCode": "0x79",
        "Counter": "0,1,2,3",
        "UMask": "0x8",
        "EventName": "IDQ.DSB_UOPS",
        "SampleAfterValue": "2000003",
        "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path.",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "EventCode": "0x79",
        "Counter": "0,1,2,3",
        "UMask": "0x10",
        "EventName": "IDQ.MS_DSB_UOPS",
        "SampleAfterValue": "2000003",
        "BriefDescription": "Uops initiated by Decode Stream Buffer (DSB) that are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy.",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "EventCode": "0x79",
        "Counter": "0,1,2,3",
        "UMask": "0x20",
        "EventName": "IDQ.MS_MITE_UOPS",
        "SampleAfterValue": "2000003",
        "BriefDescription": "Uops initiated by MITE and delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy.",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "EventCode": "0x79",
        "Counter": "0,1,2,3",
        "UMask": "0x30",
        "EventName": "IDQ.MS_UOPS",
        "SampleAfterValue": "2000003",
        "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy.",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "PublicDescription": "This event counts cycles during which the microcode sequencer assisted the front-end in delivering uops.  Microcode assists are used for complex instructions or scenarios that can't be handled by the standard decoder.  Using other instructions, if possible, will usually improve performance.  See the Intel? 64 and IA-32 Architectures Optimization Reference Manual for more information.",
        "EventCode": "0x79",
        "Counter": "0,1,2,3",
        "UMask": "0x30",
        "EventName": "IDQ.MS_CYCLES",
        "SampleAfterValue": "2000003",
        "BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy.",
        "CounterMask": "1",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "PublicDescription": "This event counts the number of uops not delivered to the back-end per cycle, per thread, when the back-end was not stalled.  In the ideal case 4 uops can be delivered each cycle.  The event counts the undelivered uops - so if 3 were delivered in one cycle, the counter would be incremented by 1 for that cycle (4 - 3). If the back-end is stalled, the count for this event is not incremented even when uops were not delivered, because the back-end would not have been able to accept them.  This event is used in determining the front-end bound category of the top-down pipeline slots characterization.",
        "EventCode": "0x9C",
        "Counter": "0,1,2,3",
        "UMask": "0x1",
        "EventName": "IDQ_UOPS_NOT_DELIVERED.CORE",
        "SampleAfterValue": "2000003",
        "BriefDescription": "Uops not delivered to Resource Allocation Table (RAT) per thread when backend of the machine is not stalled .",
        "CounterHTOff": "0,1,2,3"
    },
    {
        "EventCode": "0x9C",
        "Counter": "0,1,2,3",
        "UMask": "0x1",
        "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE",
        "SampleAfterValue": "2000003",
        "BriefDescription": "Cycles per thread when 4 or more uops are not delivered to Resource Allocation Table (RAT) when backend of the machine is not stalled.",
        "CounterMask": "4",
        "CounterHTOff": "0,1,2,3"
    },
    {
        "EventCode": "0x9C",
        "Counter": "0,1,2,3",
        "UMask": "0x1",
        "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_1_UOP_DELIV.CORE",
        "SampleAfterValue": "2000003",
        "BriefDescription": "Cycles per thread when 3 or more uops are not delivered to Resource Allocation Table (RAT) when backend of the machine is not stalled.",
        "CounterMask": "3",
        "CounterHTOff": "0,1,2,3"
    },
    {
        "EventCode": "0xAB",
        "Counter": "0,1,2,3",
        "UMask": "0x1",
        "EventName": "DSB2MITE_SWITCHES.COUNT",
        "SampleAfterValue": "2000003",
        "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switches.",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "PublicDescription": "This event counts the cycles attributed to a switch from the Decoded Stream Buffer (DSB), which holds decoded instructions, to the legacy decode pipeline.  It excludes cycles when the back-end cannot  accept new micro-ops.  The penalty for these switches is potentially several cycles of instruction starvation, where no micro-ops are delivered to the back-end.",
        "EventCode": "0xAB",
        "Counter": "0,1,2,3",
        "UMask": "0x2",
        "EventName": "DSB2MITE_SWITCHES.PENALTY_CYCLES",
        "SampleAfterValue": "2000003",
        "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles.",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "EventCode": "0xAC",
        "Counter": "0,1,2,3",
        "UMask": "0x2",
        "EventName": "DSB_FILL.OTHER_CANCEL",
        "SampleAfterValue": "2000003",
        "BriefDescription": "Cases of cancelling valid DSB fill not because of exceeding way limit.",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "EventCode": "0xAC",
        "Counter": "0,1,2,3",
        "UMask": "0x8",
        "EventName": "DSB_FILL.EXCEED_DSB_LINES",
        "SampleAfterValue": "2000003",
        "BriefDescription": "Cycles when Decode Stream Buffer (DSB) fill encounter more than 3 Decode Stream Buffer (DSB) lines.",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "EventCode": "0x79",
        "Counter": "0,1,2,3",
        "UMask": "0x4",
        "EventName": "IDQ.MITE_CYCLES",
        "SampleAfterValue": "2000003",
        "BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from MITE path.",
        "CounterMask": "1",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "EventCode": "0x79",
        "Counter": "0,1,2,3",
        "UMask": "0x8",
        "EventName": "IDQ.DSB_CYCLES",
        "SampleAfterValue": "2000003",
        "BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from Decode Stream Buffer (DSB) path.",
        "CounterMask": "1",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "EventCode": "0x79",
        "Counter": "0,1,2,3",
        "UMask": "0x10",
        "EventName": "IDQ.MS_DSB_CYCLES",
        "SampleAfterValue": "2000003",
        "BriefDescription": "Cycles when uops initiated by Decode Stream Buffer (DSB) are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy.",
        "CounterMask": "1",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "EventCode": "0x79",
        "Counter": "0,1,2,3",
        "UMask": "0x10",
        "EdgeDetect": "1",
        "EventName": "IDQ.MS_DSB_OCCUR",
        "SampleAfterValue": "2000003",
        "BriefDescription": "Deliveries to Instruction Decode Queue (IDQ) initiated by Decode Stream Buffer (DSB) while Microcode Sequenser (MS) is busy.",
        "CounterMask": "1",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "EventCode": "0x9C",
        "Counter": "0,1,2,3",
        "UMask": "0x1",
        "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_2_UOP_DELIV.CORE",
        "SampleAfterValue": "2000003",
        "BriefDescription": "Cycles with less than 2 uops delivered by the front end.",
        "CounterMask": "2",
        "CounterHTOff": "0,1,2,3"
    },
    {
        "EventCode": "0x9C",
        "Counter": "0,1,2,3",
        "UMask": "0x1",
        "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_3_UOP_DELIV.CORE",
        "SampleAfterValue": "2000003",
        "BriefDescription": "Cycles with less than 3 uops delivered by the front end.",
        "CounterMask": "1",
        "CounterHTOff": "0,1,2,3"
    },
    {
        "EventCode": "0x9C",
        "Invert": "1",
        "Counter": "0,1,2,3",
        "UMask": "0x1",
        "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_GE_1_UOP_DELIV.CORE",
        "SampleAfterValue": "2000003",
        "BriefDescription": "Cycles when 1 or more uops were delivered to the by the front end.",
        "CounterMask": "4",
        "CounterHTOff": "0,1,2,3"
    },
    {
        "EventCode": "0x79",
        "Counter": "0,1,2,3",
        "UMask": "0x18",
        "EventName": "IDQ.ALL_DSB_CYCLES_4_UOPS",
        "SampleAfterValue": "2000003",
        "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering 4 Uops.",
        "CounterMask": "4",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "EventCode": "0x79",
        "Counter": "0,1,2,3",
        "UMask": "0x18",
        "EventName": "IDQ.ALL_DSB_CYCLES_ANY_UOPS",
        "SampleAfterValue": "2000003",
        "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering any Uop.",
        "CounterMask": "1",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "EventCode": "0x79",
        "Counter": "0,1,2,3",
        "UMask": "0x24",
        "EventName": "IDQ.ALL_MITE_CYCLES_4_UOPS",
        "SampleAfterValue": "2000003",
        "BriefDescription": "Cycles MITE is delivering 4 Uops.",
        "CounterMask": "4",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "EventCode": "0x79",
        "Counter": "0,1,2,3",
        "UMask": "0x24",
        "EventName": "IDQ.ALL_MITE_CYCLES_ANY_UOPS",
        "SampleAfterValue": "2000003",
        "BriefDescription": "Cycles MITE is delivering any Uop.",
        "CounterMask": "1",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "EventCode": "0xAC",
        "Counter": "0,1,2,3",
        "UMask": "0xa",
        "EventName": "DSB_FILL.ALL_CANCEL",
        "SampleAfterValue": "2000003",
        "BriefDescription": "Cases of cancelling valid Decode Stream Buffer (DSB) fill not because of exceeding way limit.",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "EventCode": "0x9C",
        "Invert": "1",
        "Counter": "0,1,2,3",
        "UMask": "0x1",
        "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_FE_WAS_OK",
        "SampleAfterValue": "2000003",
        "BriefDescription": "Counts cycles FE delivered 4 uops or Resource Allocation Table (RAT) was stalling FE.",
        "CounterMask": "1",
        "CounterHTOff": "0,1,2,3"
    },
    {
        "EventCode": "0x79",
        "Counter": "0,1,2,3",
        "UMask": "0x3c",
        "EventName": "IDQ.MITE_ALL_UOPS",
        "SampleAfterValue": "2000003",
        "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from MITE path.",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "EventCode": "0x79",
        "Counter": "0,1,2,3",
        "UMask": "0x30",
        "EdgeDetect": "1",
        "EventName": "IDQ.MS_SWITCHES",
        "SampleAfterValue": "2000003",
        "BriefDescription": "Number of switches from DSB (Decode Stream Buffer) or MITE (legacy decode pipeline) to the Microcode Sequencer.",
        "CounterMask": "1",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    }
]