summaryrefslogtreecommitdiffstats
path: root/tools/perf/pmu-events/arch/x86/jaketown/virtual-memory.json
blob: a654ab771fce7a5a245bdd62e6b7994b4b8efce0 (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
[
    {
        "EventCode": "0xAE",
        "Counter": "0,1,2,3",
        "UMask": "0x1",
        "EventName": "ITLB.ITLB_FLUSH",
        "SampleAfterValue": "100007",
        "BriefDescription": "Flushing of the Instruction TLB (ITLB) pages, includes 4k/2M/4M pages.",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "EventCode": "0x4F",
        "Counter": "0,1,2,3",
        "UMask": "0x10",
        "EventName": "EPT.WALK_CYCLES",
        "SampleAfterValue": "2000003",
        "BriefDescription": "Cycle count for an Extended Page table walk.  The Extended Page Directory cache is used by Virtual Machine operating systems while the guest operating systems use the standard TLB caches.",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "EventCode": "0x85",
        "Counter": "0,1,2,3",
        "UMask": "0x1",
        "EventName": "ITLB_MISSES.MISS_CAUSES_A_WALK",
        "SampleAfterValue": "100003",
        "BriefDescription": "Misses at all ITLB levels that cause page walks.",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "EventCode": "0x85",
        "Counter": "0,1,2,3",
        "UMask": "0x2",
        "EventName": "ITLB_MISSES.WALK_COMPLETED",
        "SampleAfterValue": "100003",
        "BriefDescription": "Misses in all ITLB levels that cause completed page walks.",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "PublicDescription": "This event count cycles when Page Miss Handler (PMH) is servicing page walks caused by ITLB misses.",
        "EventCode": "0x85",
        "Counter": "0,1,2,3",
        "UMask": "0x4",
        "EventName": "ITLB_MISSES.WALK_DURATION",
        "SampleAfterValue": "2000003",
        "BriefDescription": "Cycles when PMH is busy with page walks.",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "EventCode": "0x85",
        "Counter": "0,1,2,3",
        "UMask": "0x10",
        "EventName": "ITLB_MISSES.STLB_HIT",
        "SampleAfterValue": "100003",
        "BriefDescription": "Operations that miss the first ITLB level but hit the second and do not cause any page walks.",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "EventCode": "0x08",
        "Counter": "0,1,2,3",
        "UMask": "0x1",
        "EventName": "DTLB_LOAD_MISSES.MISS_CAUSES_A_WALK",
        "SampleAfterValue": "100003",
        "BriefDescription": "Load misses in all DTLB levels that cause page walks.",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "EventCode": "0x08",
        "Counter": "0,1,2,3",
        "UMask": "0x2",
        "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED",
        "SampleAfterValue": "100003",
        "BriefDescription": "Load misses at all DTLB levels that cause completed page walks.",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "PublicDescription": "This event counts cycles when the  page miss handler (PMH) is servicing page walks caused by DTLB load misses.",
        "EventCode": "0x08",
        "Counter": "0,1,2,3",
        "UMask": "0x4",
        "EventName": "DTLB_LOAD_MISSES.WALK_DURATION",
        "SampleAfterValue": "2000003",
        "BriefDescription": "Cycles when PMH is busy with page walks.",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "PublicDescription": "This event counts load operations that miss the first DTLB level but hit the second and do not cause any page walks. The penalty in this case is approximately 7 cycles.",
        "EventCode": "0x08",
        "Counter": "0,1,2,3",
        "UMask": "0x10",
        "EventName": "DTLB_LOAD_MISSES.STLB_HIT",
        "SampleAfterValue": "100003",
        "BriefDescription": "Load operations that miss the first DTLB level but hit the second and do not cause page walks.",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "EventCode": "0x49",
        "Counter": "0,1,2,3",
        "UMask": "0x1",
        "EventName": "DTLB_STORE_MISSES.MISS_CAUSES_A_WALK",
        "SampleAfterValue": "100003",
        "BriefDescription": "Store misses in all DTLB levels that cause page walks.",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "EventCode": "0x49",
        "Counter": "0,1,2,3",
        "UMask": "0x2",
        "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED",
        "SampleAfterValue": "100003",
        "BriefDescription": "Store misses in all DTLB levels that cause completed page walks.",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "EventCode": "0x49",
        "Counter": "0,1,2,3",
        "UMask": "0x4",
        "EventName": "DTLB_STORE_MISSES.WALK_DURATION",
        "SampleAfterValue": "2000003",
        "BriefDescription": "Cycles when PMH is busy with page walks.",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "EventCode": "0x49",
        "Counter": "0,1,2,3",
        "UMask": "0x10",
        "EventName": "DTLB_STORE_MISSES.STLB_HIT",
        "SampleAfterValue": "100003",
        "BriefDescription": "Store operations that miss the first TLB level but hit the second and do not cause page walks.",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "EventCode": "0xBD",
        "Counter": "0,1,2,3",
        "UMask": "0x1",
        "EventName": "TLB_FLUSH.DTLB_THREAD",
        "SampleAfterValue": "100007",
        "BriefDescription": "DTLB flush attempts of the thread-specific entries.",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "EventCode": "0xBD",
        "Counter": "0,1,2,3",
        "UMask": "0x20",
        "EventName": "TLB_FLUSH.STLB_ANY",
        "SampleAfterValue": "100007",
        "BriefDescription": "STLB flush attempts.",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    }
]