1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
|
/* $Id: PDMAll.cpp $ */
/** @file
* PDM Critical Sections
*/
/*
* Copyright (C) 2006-2020 Oracle Corporation
*
* This file is part of VirtualBox Open Source Edition (OSE), as
* available from http://www.virtualbox.org. This file is free software;
* you can redistribute it and/or modify it under the terms of the GNU
* General Public License (GPL) as published by the Free Software
* Foundation, in version 2 as it comes in the "COPYING" file of the
* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
*/
/*********************************************************************************************************************************
* Header Files *
*********************************************************************************************************************************/
#define LOG_GROUP LOG_GROUP_PDM
#include "PDMInternal.h"
#include <VBox/vmm/pdm.h>
#include <VBox/vmm/mm.h>
#include <VBox/vmm/vmcc.h>
#include <VBox/err.h>
#include <VBox/vmm/apic.h>
#include <VBox/log.h>
#include <iprt/asm.h>
#include <iprt/assert.h>
#include "PDMInline.h"
#include "dtrace/VBoxVMM.h"
/**
* Gets the pending interrupt.
*
* @returns VBox status code.
* @retval VINF_SUCCESS on success.
* @retval VERR_APIC_INTR_MASKED_BY_TPR when an APIC interrupt is pending but
* can't be delivered due to TPR priority.
* @retval VERR_NO_DATA if there is no interrupt to be delivered (either APIC
* has been software-disabled since it flagged something was pending,
* or other reasons).
*
* @param pVCpu The cross context virtual CPU structure.
* @param pu8Interrupt Where to store the interrupt.
*/
VMMDECL(int) PDMGetInterrupt(PVMCPUCC pVCpu, uint8_t *pu8Interrupt)
{
/*
* The local APIC has a higher priority than the PIC.
*/
int rc = VERR_NO_DATA;
if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INTERRUPT_APIC))
{
VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INTERRUPT_APIC);
uint32_t uTagSrc;
rc = APICGetInterrupt(pVCpu, pu8Interrupt, &uTagSrc);
if (RT_SUCCESS(rc))
{
if (rc == VINF_SUCCESS)
VBOXVMM_PDM_IRQ_GET(pVCpu, RT_LOWORD(uTagSrc), RT_HIWORD(uTagSrc), *pu8Interrupt);
return rc;
}
/* else if it's masked by TPR/PPR/whatever, go ahead checking the PIC. Such masked
interrupts shouldn't prevent ExtINT from being delivered. */
}
PVMCC pVM = pVCpu->CTX_SUFF(pVM);
pdmLock(pVM);
/*
* Check the PIC.
*/
if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INTERRUPT_PIC))
{
VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INTERRUPT_PIC);
Assert(pVM->pdm.s.Pic.CTX_SUFF(pDevIns));
Assert(pVM->pdm.s.Pic.CTX_SUFF(pfnGetInterrupt));
uint32_t uTagSrc;
int i = pVM->pdm.s.Pic.CTX_SUFF(pfnGetInterrupt)(pVM->pdm.s.Pic.CTX_SUFF(pDevIns), &uTagSrc);
AssertMsg(i <= 255 && i >= 0, ("i=%d\n", i));
if (i >= 0)
{
pdmUnlock(pVM);
*pu8Interrupt = (uint8_t)i;
VBOXVMM_PDM_IRQ_GET(pVCpu, RT_LOWORD(uTagSrc), RT_HIWORD(uTagSrc), i);
return VINF_SUCCESS;
}
}
/*
* One scenario where we may possibly get here is if the APIC signaled a pending interrupt,
* got an APIC MMIO/MSR VM-exit which disabled the APIC. We could, in theory, clear the APIC
* force-flag from all the places which disables the APIC but letting PDMGetInterrupt() fail
* without returning a valid interrupt still needs to be handled for the TPR masked case,
* so we shall just handle it here regardless if we choose to update the APIC code in the future.
*/
pdmUnlock(pVM);
return rc;
}
/**
* Sets the pending interrupt coming from ISA source or HPET.
*
* @returns VBox status code.
* @param pVM The cross context VM structure.
* @param u8Irq The IRQ line.
* @param u8Level The new level.
* @param uTagSrc The IRQ tag and source tracer ID.
*/
VMMDECL(int) PDMIsaSetIrq(PVMCC pVM, uint8_t u8Irq, uint8_t u8Level, uint32_t uTagSrc)
{
pdmLock(pVM);
/** @todo put the IRQ13 code elsewhere to avoid this unnecessary bloat. */
if (!uTagSrc && (u8Level & PDM_IRQ_LEVEL_HIGH)) /* FPU IRQ */
{
if (u8Level == PDM_IRQ_LEVEL_HIGH)
VBOXVMM_PDM_IRQ_HIGH(VMMGetCpu(pVM), 0, 0);
else
VBOXVMM_PDM_IRQ_HILO(VMMGetCpu(pVM), 0, 0);
}
int rc = VERR_PDM_NO_PIC_INSTANCE;
/** @todo r=bird: This code is incorrect, as it ASSUMES the PIC and I/O APIC
* are always ring-0 enabled! */
if (pVM->pdm.s.Pic.CTX_SUFF(pDevIns))
{
Assert(pVM->pdm.s.Pic.CTX_SUFF(pfnSetIrq));
pVM->pdm.s.Pic.CTX_SUFF(pfnSetIrq)(pVM->pdm.s.Pic.CTX_SUFF(pDevIns), u8Irq, u8Level, uTagSrc);
rc = VINF_SUCCESS;
}
if (pVM->pdm.s.IoApic.CTX_SUFF(pDevIns))
{
Assert(pVM->pdm.s.IoApic.CTX_SUFF(pfnSetIrq));
/*
* Apply Interrupt Source Override rules.
* See ACPI 4.0 specification 5.2.12.4 and 5.2.12.5 for details on
* interrupt source override.
* Shortly, ISA IRQ0 is electically connected to pin 2 on IO-APIC, and some OSes,
* notably recent OS X rely upon this configuration.
* If changing, also update override rules in MADT and MPS.
*/
/* ISA IRQ0 routed to pin 2, all others ISA sources are identity mapped */
if (u8Irq == 0)
u8Irq = 2;
pVM->pdm.s.IoApic.CTX_SUFF(pfnSetIrq)(pVM->pdm.s.IoApic.CTX_SUFF(pDevIns), u8Irq, u8Level, uTagSrc);
rc = VINF_SUCCESS;
}
if (!uTagSrc && u8Level == PDM_IRQ_LEVEL_LOW)
VBOXVMM_PDM_IRQ_LOW(VMMGetCpu(pVM), 0, 0);
pdmUnlock(pVM);
return rc;
}
/**
* Sets the pending I/O APIC interrupt.
*
* @returns VBox status code.
* @param pVM The cross context VM structure.
* @param u8Irq The IRQ line.
* @param u8Level The new level.
* @param uTagSrc The IRQ tag and source tracer ID.
*/
VMM_INT_DECL(int) PDMIoApicSetIrq(PVM pVM, uint8_t u8Irq, uint8_t u8Level, uint32_t uTagSrc)
{
if (pVM->pdm.s.IoApic.CTX_SUFF(pDevIns))
{
Assert(pVM->pdm.s.IoApic.CTX_SUFF(pfnSetIrq));
pVM->pdm.s.IoApic.CTX_SUFF(pfnSetIrq)(pVM->pdm.s.IoApic.CTX_SUFF(pDevIns), u8Irq, u8Level, uTagSrc);
return VINF_SUCCESS;
}
return VERR_PDM_NO_PIC_INSTANCE;
}
/**
* Broadcasts an EOI to the I/O APICs.
*
* @returns Strict VBox status code - only the following informational status codes:
* @retval VINF_IOM_R3_MMIO_WRITE if the I/O APIC lock is contenteded and we're in R0 or RC.
* @retval VINF_SUCCESS
*
* @param pVM The cross context VM structure.
* @param uVector The interrupt vector corresponding to the EOI.
*/
VMM_INT_DECL(VBOXSTRICTRC) PDMIoApicBroadcastEoi(PVM pVM, uint8_t uVector)
{
/* At present, we support only a maximum of one I/O APIC per-VM. If we ever implement having
multiple I/O APICs per-VM, we'll have to broadcast this EOI to all of the I/O APICs. */
if (pVM->pdm.s.IoApic.CTX_SUFF(pDevIns))
{
Assert(pVM->pdm.s.IoApic.CTX_SUFF(pfnSetEoi));
return pVM->pdm.s.IoApic.CTX_SUFF(pfnSetEoi)(pVM->pdm.s.IoApic.CTX_SUFF(pDevIns), uVector);
}
/* We shouldn't return failure if no I/O APIC is present. */
return VINF_SUCCESS;
}
/**
* Send a MSI to an I/O APIC.
*
* @returns VBox status code.
* @param pVM The cross context VM structure.
* @param GCAddr Request address.
* @param uValue Request value.
* @param uTagSrc The IRQ tag and source tracer ID.
*/
VMM_INT_DECL(int) PDMIoApicSendMsi(PVM pVM, RTGCPHYS GCAddr, uint32_t uValue, uint32_t uTagSrc)
{
if (pVM->pdm.s.IoApic.CTX_SUFF(pDevIns))
{
Assert(pVM->pdm.s.IoApic.CTX_SUFF(pfnSendMsi));
pVM->pdm.s.IoApic.CTX_SUFF(pfnSendMsi)(pVM->pdm.s.IoApic.CTX_SUFF(pDevIns), GCAddr, uValue, uTagSrc);
return VINF_SUCCESS;
}
return VERR_PDM_NO_PIC_INSTANCE;
}
/**
* Returns the presence of an IO-APIC.
*
* @returns true if an IO-APIC is present.
* @param pVM The cross context VM structure.
*/
VMM_INT_DECL(bool) PDMHasIoApic(PVM pVM)
{
return pVM->pdm.s.IoApic.pDevInsR3 != NULL;
}
/**
* Returns the presence of an APIC.
*
* @returns true if an APIC is present.
* @param pVM The cross context VM structure.
*/
VMM_INT_DECL(bool) PDMHasApic(PVM pVM)
{
return pVM->pdm.s.Apic.pDevInsR3 != NIL_RTR3PTR;
}
/**
* Locks PDM.
* This might call back to Ring-3 in order to deal with lock contention in GC and R3.
*
* @param pVM The cross context VM structure.
*/
void pdmLock(PVMCC pVM)
{
#ifdef IN_RING3
int rc = PDMCritSectEnter(&pVM->pdm.s.CritSect, VERR_IGNORED);
#else
int rc = PDMCritSectEnter(&pVM->pdm.s.CritSect, VERR_GENERAL_FAILURE);
if (rc == VERR_GENERAL_FAILURE)
rc = VMMRZCallRing3NoCpu(pVM, VMMCALLRING3_PDM_LOCK, 0);
#endif
AssertRC(rc);
}
/**
* Locks PDM but don't go to ring-3 if it's owned by someone.
*
* @returns VINF_SUCCESS on success.
* @returns rc if we're in GC or R0 and can't get the lock.
* @param pVM The cross context VM structure.
* @param rc The RC to return in GC or R0 when we can't get the lock.
*/
int pdmLockEx(PVMCC pVM, int rc)
{
return PDMCritSectEnter(&pVM->pdm.s.CritSect, rc);
}
/**
* Unlocks PDM.
*
* @param pVM The cross context VM structure.
*/
void pdmUnlock(PVMCC pVM)
{
PDMCritSectLeave(&pVM->pdm.s.CritSect);
}
/**
* Converts ring 3 VMM heap pointer to a guest physical address
*
* @returns VBox status code.
* @param pVM The cross context VM structure.
* @param pv Ring-3 pointer.
* @param pGCPhys GC phys address (out).
*/
VMM_INT_DECL(int) PDMVmmDevHeapR3ToGCPhys(PVM pVM, RTR3PTR pv, RTGCPHYS *pGCPhys)
{
if (RT_LIKELY(pVM->pdm.s.GCPhysVMMDevHeap != NIL_RTGCPHYS))
{
RTR3UINTPTR const offHeap = (RTR3UINTPTR)pv - (RTR3UINTPTR)pVM->pdm.s.pvVMMDevHeap;
if (RT_LIKELY(offHeap < pVM->pdm.s.cbVMMDevHeap))
{
*pGCPhys = pVM->pdm.s.GCPhysVMMDevHeap + offHeap;
return VINF_SUCCESS;
}
/* Don't assert here as this is called before we can catch ring-0 assertions. */
Log(("PDMVmmDevHeapR3ToGCPhys: pv=%p pvVMMDevHeap=%p cbVMMDevHeap=%#x\n",
pv, pVM->pdm.s.pvVMMDevHeap, pVM->pdm.s.cbVMMDevHeap));
}
else
Log(("PDMVmmDevHeapR3ToGCPhys: GCPhysVMMDevHeap=%RGp (pv=%p)\n", pVM->pdm.s.GCPhysVMMDevHeap, pv));
return VERR_PDM_DEV_HEAP_R3_TO_GCPHYS;
}
/**
* Checks if the vmm device heap is enabled (== vmm device's pci region mapped)
*
* @returns dev heap enabled status (true/false)
* @param pVM The cross context VM structure.
*/
VMM_INT_DECL(bool) PDMVmmDevHeapIsEnabled(PVM pVM)
{
return pVM->pdm.s.GCPhysVMMDevHeap != NIL_RTGCPHYS;
}
|
