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| author | Daniel Baumann <daniel.baumann@progress-linux.org> | 2024-04-21 17:43:51 +0000 |
|---|---|---|
| committer | Daniel Baumann <daniel.baumann@progress-linux.org> | 2024-04-21 17:43:51 +0000 |
| commit | be58c81aff4cd4c0ccf43dbd7998da4a6a08c03b (patch) | |
| tree | 779c248fb61c83f65d1f0dc867f2053d76b4e03a /include/lib/cpus/aarch64 | |
| parent | Initial commit. (diff) | |
| download | arm-trusted-firmware-upstream.tar.xz arm-trusted-firmware-upstream.zip | |
Adding upstream version 2.10.0+dfsg.upstream/2.10.0+dfsgupstream
Signed-off-by: Daniel Baumann <daniel.baumann@progress-linux.org>
Diffstat (limited to '')
46 files changed, 2517 insertions, 0 deletions
diff --git a/include/lib/cpus/aarch64/a64fx.h b/include/lib/cpus/aarch64/a64fx.h new file mode 100644 index 0000000..b7342b0 --- /dev/null +++ b/include/lib/cpus/aarch64/a64fx.h @@ -0,0 +1,15 @@ +/* + * Copyright (c) 2022, Fujitsu Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef A64FX_H +#define A64FX_H + +#include <lib/utils_def.h> + +/* A64FX midr for revision 0 */ +#define A64FX_MIDR U(0x461f0010) + +#endif /* A64FX_H */ diff --git a/include/lib/cpus/aarch64/aem_generic.h b/include/lib/cpus/aarch64/aem_generic.h new file mode 100644 index 0000000..acb6adb --- /dev/null +++ b/include/lib/cpus/aarch64/aem_generic.h @@ -0,0 +1,18 @@ +/* + * Copyright (c) 2014-2019, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef AEM_GENERIC_H +#define AEM_GENERIC_H + +#include <lib/utils_def.h> + +/* BASE AEM midr for revision 0 */ +#define BASE_AEM_MIDR U(0x410FD0F0) + +/* Foundation AEM midr for revision 0 */ +#define FOUNDATION_AEM_MIDR U(0x410FD000) + +#endif /* AEM_GENERIC_H */ diff --git a/include/lib/cpus/aarch64/cortex_a35.h b/include/lib/cpus/aarch64/cortex_a35.h new file mode 100644 index 0000000..cef2960 --- /dev/null +++ b/include/lib/cpus/aarch64/cortex_a35.h @@ -0,0 +1,29 @@ +/* + * Copyright (c) 2016-2019, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef CORTEX_A35_H +#define CORTEX_A35_H + +#include <lib/utils_def.h> + +/* Cortex-A35 Main ID register for revision 0 */ +#define CORTEX_A35_MIDR U(0x410FD040) + +/******************************************************************************* + * CPU Extended Control register specific definitions. + * CPUECTLR_EL1 is an implementation-specific register. + ******************************************************************************/ +#define CORTEX_A35_CPUECTLR_EL1 S3_1_C15_C2_1 +#define CORTEX_A35_CPUECTLR_SMPEN_BIT (ULL(1) << 6) + +/******************************************************************************* + * CPU Auxiliary Control register specific definitions. + ******************************************************************************/ +#define CORTEX_A35_CPUACTLR_EL1 S3_1_C15_C2_0 + +#define CORTEX_A35_CPUACTLR_EL1_ENDCCASCI (ULL(1) << 44) + +#endif /* CORTEX_A35_H */ diff --git a/include/lib/cpus/aarch64/cortex_a510.h b/include/lib/cpus/aarch64/cortex_a510.h new file mode 100644 index 0000000..337aac3 --- /dev/null +++ b/include/lib/cpus/aarch64/cortex_a510.h @@ -0,0 +1,55 @@ +/* + * Copyright (c) 2022-2023, Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef CORTEX_A510_H +#define CORTEX_A510_H + +#define CORTEX_A510_MIDR U(0x410FD460) + +/******************************************************************************* + * CPU Extended Control register specific definitions + ******************************************************************************/ +#define CORTEX_A510_CPUECTLR_EL1 S3_0_C15_C1_4 +#define CORTEX_A510_CPUECTLR_EL1_READPREFERUNIQUE_SHIFT U(19) +#define CORTEX_A510_CPUECTLR_EL1_READPREFERUNIQUE_WIDTH U(1) +#define CORTEX_A510_CPUECTLR_EL1_READPREFERUNIQUE_DISABLE U(1) +#define CORTEX_A510_CPUECTLR_EL1_RSCTL_SHIFT U(23) +#define CORTEX_A510_CPUECTLR_EL1_NTCTL_SHIFT U(46) +#define CORTEX_A510_CPUECTLR_EL1_ATOM_EXECALLINSTRNEAR U(2) +#define CORTEX_A510_CPUECTLR_EL1_ATOM_SHIFT U(38) +#define CORTEX_A510_CPUECTLR_EL1_ATOM_WIDTH U(3) + +/******************************************************************************* + * CPU Power Control register specific definitions + ******************************************************************************/ +#define CORTEX_A510_CPUPWRCTLR_EL1 S3_0_C15_C2_7 +#define CORTEX_A510_CPUPWRCTLR_EL1_CORE_PWRDN_BIT U(1) + +/******************************************************************************* + * Complex auxiliary control register specific definitions + ******************************************************************************/ +#define CORTEX_A510_CMPXACTLR_EL1 S3_0_C15_C1_3 +#define CORTEX_A510_CMPXACTLR_EL1_ALIAS_LOADSTORE_DISABLE U(1) +#define CORTEX_A510_CMPXACTLR_EL1_ALIAS_LOADSTORE_SHIFT U(25) +#define CORTEX_A510_CMPXACTLR_EL1_ALIAS_LOADSTORE_WIDTH U(1) +#define CORTEX_A510_CMPXACTLR_EL1_SNPPREFERUNIQUE_DISABLE U(3) +#define CORTEX_A510_CMPXACTLR_EL1_SNPPREFERUNIQUE_SHIFT U(10) +#define CORTEX_A510_CMPXACTLR_EL1_SNPPREFERUNIQUE_WIDTH U(2) + +/******************************************************************************* + * Auxiliary control register specific definitions + ******************************************************************************/ +#define CORTEX_A510_CPUACTLR_EL1 S3_0_C15_C1_0 +#define CORTEX_A510_CPUACTLR_EL1_BIT_17 (ULL(1) << 17) +#define CORTEX_A510_CPUACTLR_EL1_BIT_38 (ULL(1) << 38) +#define CORTEX_A510_CPUACTLR_EL1_ALIAS_LOADSTORE_DISABLE U(1) +#define CORTEX_A510_CPUACTLR_EL1_ALIAS_LOADSTORE_SHIFT U(18) +#define CORTEX_A510_CPUACTLR_EL1_ALIAS_LOADSTORE_WIDTH U(1) +#define CORTEX_A510_CPUACTLR_EL1_DATA_CORRUPT_DISABLE U(1) +#define CORTEX_A510_CPUACTLR_EL1_DATA_CORRUPT_SHIFT U(18) +#define CORTEX_A510_CPUACTLR_EL1_DATA_CORRUPT_WIDTH U(1) + +#endif /* CORTEX_A510_H */ diff --git a/include/lib/cpus/aarch64/cortex_a520.h b/include/lib/cpus/aarch64/cortex_a520.h new file mode 100644 index 0000000..4176981 --- /dev/null +++ b/include/lib/cpus/aarch64/cortex_a520.h @@ -0,0 +1,23 @@ +/* + * Copyright (c) 2021-2023, Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef CORTEX_A520_H +#define CORTEX_A520_H + +#define CORTEX_A520_MIDR U(0x410FD800) + +/******************************************************************************* + * CPU Extended Control register specific definitions + ******************************************************************************/ +#define CORTEX_A520_CPUECTLR_EL1 S3_0_C15_C1_4 + +/******************************************************************************* + * CPU Power Control register specific definitions + ******************************************************************************/ +#define CORTEX_A520_CPUPWRCTLR_EL1 S3_0_C15_C2_7 +#define CORTEX_A520_CPUPWRCTLR_EL1_CORE_PWRDN_BIT U(1) + +#endif /* CORTEX_A520_H */ diff --git a/include/lib/cpus/aarch64/cortex_a53.h b/include/lib/cpus/aarch64/cortex_a53.h new file mode 100644 index 0000000..18796ee --- /dev/null +++ b/include/lib/cpus/aarch64/cortex_a53.h @@ -0,0 +1,85 @@ +/* + * Copyright (c) 2014-2019, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef CORTEX_A53_H +#define CORTEX_A53_H + +#include <lib/utils_def.h> + +/* Cortex-A53 midr for revision 0 */ +#define CORTEX_A53_MIDR U(0x410FD030) + +/* Retention timer tick definitions */ +#define RETENTION_ENTRY_TICKS_2 U(0x1) +#define RETENTION_ENTRY_TICKS_8 U(0x2) +#define RETENTION_ENTRY_TICKS_32 U(0x3) +#define RETENTION_ENTRY_TICKS_64 U(0x4) +#define RETENTION_ENTRY_TICKS_128 U(0x5) +#define RETENTION_ENTRY_TICKS_256 U(0x6) +#define RETENTION_ENTRY_TICKS_512 U(0x7) + +/******************************************************************************* + * CPU Extended Control register specific definitions. + ******************************************************************************/ +#define CORTEX_A53_ECTLR_EL1 S3_1_C15_C2_1 + +#define CORTEX_A53_ECTLR_SMP_BIT (ULL(1) << 6) + +#define CORTEX_A53_ECTLR_CPU_RET_CTRL_SHIFT U(0) +#define CORTEX_A53_ECTLR_CPU_RET_CTRL_MASK (ULL(0x7) << CORTEX_A53_ECTLR_CPU_RET_CTRL_SHIFT) + +#define CORTEX_A53_ECTLR_FPU_RET_CTRL_SHIFT U(3) +#define CORTEX_A53_ECTLR_FPU_RET_CTRL_MASK (ULL(0x7) << CORTEX_A53_ECTLR_FPU_RET_CTRL_SHIFT) + +/******************************************************************************* + * CPU Memory Error Syndrome register specific definitions. + ******************************************************************************/ +#define CORTEX_A53_MERRSR_EL1 S3_1_C15_C2_2 + +/******************************************************************************* + * CPU Auxiliary Control register specific definitions. + ******************************************************************************/ +#define CORTEX_A53_CPUACTLR_EL1 S3_1_C15_C2_0 + +#define CORTEX_A53_CPUACTLR_EL1_ENDCCASCI_SHIFT U(44) +#define CORTEX_A53_CPUACTLR_EL1_ENDCCASCI (ULL(1) << CORTEX_A53_CPUACTLR_EL1_ENDCCASCI_SHIFT) +#define CORTEX_A53_CPUACTLR_EL1_RADIS_SHIFT U(27) +#define CORTEX_A53_CPUACTLR_EL1_RADIS (ULL(3) << CORTEX_A53_CPUACTLR_EL1_RADIS_SHIFT) +#define CORTEX_A53_CPUACTLR_EL1_L1RADIS_SHIFT U(25) +#define CORTEX_A53_CPUACTLR_EL1_L1RADIS (ULL(3) << CORTEX_A53_CPUACTLR_EL1_L1RADIS_SHIFT) +#define CORTEX_A53_CPUACTLR_EL1_DTAH_SHIFT U(24) +#define CORTEX_A53_CPUACTLR_EL1_DTAH (ULL(1) << CORTEX_A53_CPUACTLR_EL1_DTAH_SHIFT) +#define CORTEX_A53_CPUACTLR_EL1_L1PCTL_SHIFT U(13) +#define CORTEX_A53_CPUACTLR_EL1_L1PCTL (ULL(7) << CORTEX_A53_CPUACTLR_EL1_L1PCTL_SHIFT) + +/******************************************************************************* + * L2 Auxiliary Control register specific definitions. + ******************************************************************************/ +#define CORTEX_A53_L2ACTLR_EL1 S3_1_C15_C0_0 + +#define CORTEX_A53_L2ACTLR_ENABLE_UNIQUECLEAN (U(1) << 14) +#define CORTEX_A53_L2ACTLR_DISABLE_CLEAN_PUSH (U(1) << 3) +/******************************************************************************* + * L2 Extended Control register specific definitions. + ******************************************************************************/ +#define CORTEX_A53_L2ECTLR_EL1 S3_1_C11_C0_3 + +#define CORTEX_A53_L2ECTLR_RET_CTRL_SHIFT U(0) +#define CORTEX_A53_L2ECTLR_RET_CTRL_MASK (U(0x7) << L2ECTLR_RET_CTRL_SHIFT) + +/******************************************************************************* + * L2 Memory Error Syndrome register specific definitions. + ******************************************************************************/ +#define CORTEX_A53_L2MERRSR_EL1 S3_1_C15_C2_3 + +/******************************************************************************* + * Helper function to access a53_cpuectlr_el1 register on Cortex-A53 CPUs + ******************************************************************************/ +#ifndef __ASSEMBLER__ +DEFINE_RENAME_SYSREG_RW_FUNCS(a53_cpuectlr_el1, CORTEX_A53_ECTLR_EL1) +#endif /* __ASSEMBLER__ */ + +#endif /* CORTEX_A53_H */ diff --git a/include/lib/cpus/aarch64/cortex_a55.h b/include/lib/cpus/aarch64/cortex_a55.h new file mode 100644 index 0000000..0a1593a --- /dev/null +++ b/include/lib/cpus/aarch64/cortex_a55.h @@ -0,0 +1,48 @@ +/* + * Copyright (c) 2017-2019, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef CORTEX_A55_H +#define CORTEX_A55_H + +#include <lib/utils_def.h> + +/* Cortex-A55 MIDR for revision 0 */ +#define CORTEX_A55_MIDR U(0x410fd050) + +/******************************************************************************* + * CPU Extended Control register specific definitions. + ******************************************************************************/ +#define CORTEX_A55_CPUPWRCTLR_EL1 S3_0_C15_C2_7 +#define CORTEX_A55_CPUECTLR_EL1 S3_0_C15_C1_4 + +#define CORTEX_A55_CPUECTLR_EL1_L1WSCTL (ULL(3) << 25) + +/******************************************************************************* + * CPU Auxiliary Control register specific definitions. + ******************************************************************************/ +#define CORTEX_A55_CPUACTLR_EL1 S3_0_C15_C1_0 + +#define CORTEX_A55_CPUACTLR_EL1_DISABLE_WRITE_STREAMING (ULL(1) << 24) +#define CORTEX_A55_CPUACTLR_EL1_DISABLE_DUAL_ISSUE (ULL(1) << 31) +#define CORTEX_A55_CPUACTLR_EL1_DISABLE_L1_PAGEWALKS (ULL(1) << 49) + +/******************************************************************************* + * CPU Identification register specific definitions. + ******************************************************************************/ +#define CORTEX_A55_CLIDR_EL1 S3_1_C0_C0_1 + +#define CORTEX_A55_CLIDR_EL1_CTYPE3 (ULL(7) << 6) + +/* Definitions of register field mask in CORTEX_A55_CPUPWRCTLR_EL1 */ +#define CORTEX_A55_CORE_PWRDN_EN_MASK U(0x1) + +/* Instruction patching registers */ +#define CPUPSELR_EL3 S3_6_C15_C8_0 +#define CPUPCR_EL3 S3_6_C15_C8_1 +#define CPUPOR_EL3 S3_6_C15_C8_2 +#define CPUPMR_EL3 S3_6_C15_C8_3 + +#endif /* CORTEX_A55_H */ diff --git a/include/lib/cpus/aarch64/cortex_a57.h b/include/lib/cpus/aarch64/cortex_a57.h new file mode 100644 index 0000000..19ac513 --- /dev/null +++ b/include/lib/cpus/aarch64/cortex_a57.h @@ -0,0 +1,88 @@ +/* + * Copyright (c) 2014-2019, Arm Limited and Contributors. All rights reserved. + * Copyright (c) 2020, NVIDIA Corporation. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef CORTEX_A57_H +#define CORTEX_A57_H + +#include <lib/utils_def.h> + +/* Cortex-A57 midr for revision 0 */ +#define CORTEX_A57_MIDR U(0x410FD070) + +/* Retention timer tick definitions */ +#define RETENTION_ENTRY_TICKS_2 U(0x1) +#define RETENTION_ENTRY_TICKS_8 U(0x2) +#define RETENTION_ENTRY_TICKS_32 U(0x3) +#define RETENTION_ENTRY_TICKS_64 U(0x4) +#define RETENTION_ENTRY_TICKS_128 U(0x5) +#define RETENTION_ENTRY_TICKS_256 U(0x6) +#define RETENTION_ENTRY_TICKS_512 U(0x7) + +/******************************************************************************* + * CPU Extended Control register specific definitions. + ******************************************************************************/ +#define CORTEX_A57_ECTLR_EL1 S3_1_C15_C2_1 + +#define CORTEX_A57_ECTLR_SMP_BIT (ULL(1) << 6) +#define CORTEX_A57_ECTLR_DIS_TWD_ACC_PFTCH_BIT (ULL(1) << 38) +#define CORTEX_A57_ECTLR_L2_IPFTCH_DIST_MASK (ULL(0x3) << 35) +#define CORTEX_A57_ECTLR_L2_DPFTCH_DIST_MASK (ULL(0x3) << 32) + +#define CORTEX_A57_ECTLR_CPU_RET_CTRL_SHIFT U(0) +#define CORTEX_A57_ECTLR_CPU_RET_CTRL_MASK (ULL(0x7) << CORTEX_A57_ECTLR_CPU_RET_CTRL_SHIFT) + +/******************************************************************************* + * CPU Memory Error Syndrome register specific definitions. + ******************************************************************************/ +#define CORTEX_A57_MERRSR_EL1 S3_1_C15_C2_2 + +/******************************************************************************* + * CPU Auxiliary Control register specific definitions. + ******************************************************************************/ +#define CORTEX_A57_CPUACTLR_EL1 S3_1_C15_C2_0 + +#define CORTEX_A57_CPUACTLR_EL1_DIS_LOAD_PASS_DMB (ULL(1) << 59) +#define CORTEX_A57_CPUACTLR_EL1_DIS_DMB_NULLIFICATION (ULL(1) << 58) +#define CORTEX_A57_CPUACTLR_EL1_DIS_LOAD_PASS_STORE (ULL(1) << 55) +#define CORTEX_A57_CPUACTLR_EL1_GRE_NGRE_AS_NGNRE (ULL(1) << 54) +#define CORTEX_A57_CPUACTLR_EL1_DIS_OVERREAD (ULL(1) << 52) +#define CORTEX_A57_CPUACTLR_EL1_NO_ALLOC_WBWA (ULL(1) << 49) +#define CORTEX_A57_CPUACTLR_EL1_DCC_AS_DCCI (ULL(1) << 44) +#define CORTEX_A57_CPUACTLR_EL1_FORCE_FPSCR_FLUSH (ULL(1) << 38) +#define CORTEX_A57_CPUACTLR_EL1_DIS_INSTR_PREFETCH (ULL(1) << 32) +#define CORTEX_A57_CPUACTLR_EL1_DIS_STREAMING (ULL(3) << 27) +#define CORTEX_A57_CPUACTLR_EL1_EN_NC_LOAD_FWD (ULL(1) << 24) +#define CORTEX_A57_CPUACTLR_EL1_DIS_L1_STREAMING (ULL(3) << 25) +#define CORTEX_A57_CPUACTLR_EL1_DIS_INDIRECT_PREDICTOR (ULL(1) << 4) + +/******************************************************************************* + * L2 Control register specific definitions. + ******************************************************************************/ +#define CORTEX_A57_L2CTLR_EL1 S3_1_C11_C0_2 + +#define CORTEX_A57_L2CTLR_DATA_RAM_LATENCY_SHIFT U(0) +#define CORTEX_A57_L2CTLR_TAG_RAM_LATENCY_SHIFT U(6) + +#define CORTEX_A57_L2_DATA_RAM_LATENCY_3_CYCLES U(0x2) +#define CORTEX_A57_L2_TAG_RAM_LATENCY_3_CYCLES U(0x2) + +#define CORTEX_A57_L2_ECC_PARITY_PROTECTION_BIT (U(1) << 21) + +/******************************************************************************* + * L2 Extended Control register specific definitions. + ******************************************************************************/ +#define CORTEX_A57_L2ECTLR_EL1 S3_1_C11_C0_3 + +#define CORTEX_A57_L2ECTLR_RET_CTRL_SHIFT U(0) +#define CORTEX_A57_L2ECTLR_RET_CTRL_MASK (U(0x7) << CORTEX_A57_L2ECTLR_RET_CTRL_SHIFT) + +/******************************************************************************* + * L2 Memory Error Syndrome register specific definitions. + ******************************************************************************/ +#define CORTEX_A57_L2MERRSR_EL1 S3_1_C15_C2_3 + +#endif /* CORTEX_A57_H */ diff --git a/include/lib/cpus/aarch64/cortex_a65.h b/include/lib/cpus/aarch64/cortex_a65.h new file mode 100644 index 0000000..0df34c9 --- /dev/null +++ b/include/lib/cpus/aarch64/cortex_a65.h @@ -0,0 +1,31 @@ +/* + * Copyright (c) 2019, Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef CORTEX_A65_H +#define CORTEX_A65_H + +#include <lib/utils_def.h> + +#define CORTEX_A65_MIDR U(0x410FD060) + +/******************************************************************************* + * CPU Extended Control register specific definitions + ******************************************************************************/ +#define CORTEX_A65_ECTLR_EL1 S3_0_C15_C1_4 + +/******************************************************************************* + * CPU Auxiliary Control register specific definitions + ******************************************************************************/ +#define CORTEX_A65_CPUACTLR_EL1 S3_0_C15_C1_0 + +/******************************************************************************* + * CPU Power Control register specific definitions + ******************************************************************************/ + +#define CORTEX_A65_CPUPWRCTLR_EL1 S3_0_C15_C2_7 +#define CORTEX_A65_CPUPWRCTLR_EL1_CORE_PWRDN_BIT (U(1) << 0) + +#endif /* CORTEX_A65_H */ diff --git a/include/lib/cpus/aarch64/cortex_a65ae.h b/include/lib/cpus/aarch64/cortex_a65ae.h new file mode 100644 index 0000000..bd4a881 --- /dev/null +++ b/include/lib/cpus/aarch64/cortex_a65ae.h @@ -0,0 +1,31 @@ +/* + * Copyright (c) 2019, Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef CORTEX_A65AE_H +#define CORTEX_A65AE_H + +#include <lib/utils_def.h> + +#define CORTEX_A65AE_MIDR U(0x410FD430) + +/******************************************************************************* + * CPU Extended Control register specific definitions + ******************************************************************************/ +#define CORTEX_A65AE_ECTLR_EL1 S3_0_C15_C1_4 + +/******************************************************************************* + * CPU Auxiliary Control register specific definitions + ******************************************************************************/ +#define CORTEX_A65AE_CPUACTLR_EL1 S3_0_C15_C1_0 + +/******************************************************************************* + * CPU Power Control register specific definitions + ******************************************************************************/ + +#define CORTEX_A65AE_CPUPWRCTLR_EL1 S3_0_C15_C2_7 +#define CORTEX_A65AE_CPUPWRCTLR_EL1_CORE_PWRDN_BIT (U(1) << 0) + +#endif /* CORTEX_A65AE_H */ diff --git a/include/lib/cpus/aarch64/cortex_a710.h b/include/lib/cpus/aarch64/cortex_a710.h new file mode 100644 index 0000000..432e17a --- /dev/null +++ b/include/lib/cpus/aarch64/cortex_a710.h @@ -0,0 +1,65 @@ +/* + * Copyright (c) 2021-2022, Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef CORTEX_A710_H +#define CORTEX_A710_H + +#define CORTEX_A710_MIDR U(0x410FD470) + +/* Cortex-A710 loop count for CVE-2022-23960 mitigation */ +#define CORTEX_A710_BHB_LOOP_COUNT U(32) + +/******************************************************************************* + * CPU Extended Control register specific definitions + ******************************************************************************/ +#define CORTEX_A710_CPUECTLR_EL1 S3_0_C15_C1_4 +#define CORTEX_A710_CPUECTLR_EL1_PFSTIDIS_BIT (ULL(1) << 8) + +/******************************************************************************* + * CPU Power Control register specific definitions + ******************************************************************************/ +#define CORTEX_A710_CPUPWRCTLR_EL1 S3_0_C15_C2_7 +#define CORTEX_A710_CPUPWRCTLR_EL1_CORE_PWRDN_BIT U(1) + +/******************************************************************************* + * CPU Auxiliary Control register specific definitions. + ******************************************************************************/ +#define CORTEX_A710_CPUACTLR_EL1 S3_0_C15_C1_0 +#define CORTEX_A710_CPUACTLR_EL1_BIT_46 (ULL(1) << 46) +#define CORTEX_A710_CPUACTLR_EL1_BIT_22 (ULL(1) << 22) + +/******************************************************************************* + * CPU Auxiliary Control register 2 specific definitions. + ******************************************************************************/ +#define CORTEX_A710_CPUACTLR2_EL1 S3_0_C15_C1_1 +#define CORTEX_A710_CPUACTLR2_EL1_BIT_40 (ULL(1) << 40) +#define CORTEX_A710_CPUACTLR2_EL1_BIT_36 (ULL(1) << 36) + +/******************************************************************************* + * CPU Auxiliary Control register 5 specific definitions. + ******************************************************************************/ +#define CORTEX_A710_CPUACTLR5_EL1 S3_0_C15_C8_0 +#define CORTEX_A710_CPUACTLR5_EL1_BIT_13 (ULL(1) << 13) +#define CORTEX_A710_CPUACTLR5_EL1_BIT_17 (ULL(1) << 17) +#define CORTEX_A710_CPUACTLR5_EL1_BIT_44 (ULL(1) << 44) + +/******************************************************************************* + * CPU Auxiliary Control register specific definitions. + ******************************************************************************/ +#define CORTEX_A710_CPUECTLR2_EL1 S3_0_C15_C1_5 +#define CORTEX_A710_CPUECTLR2_EL1_PF_MODE_CNSRV ULL(9) +#define CPUECTLR2_EL1_PF_MODE_LSB U(11) +#define CPUECTLR2_EL1_PF_MODE_WIDTH U(4) + +/******************************************************************************* + * CPU Selected Instruction Private register specific definitions. + ******************************************************************************/ +#define CORTEX_A710_CPUPSELR_EL3 S3_6_C15_C8_0 +#define CORTEX_A710_CPUPCR_EL3 S3_6_C15_C8_1 +#define CORTEX_A710_CPUPOR_EL3 S3_6_C15_C8_2 +#define CORTEX_A710_CPUPMR_EL3 S3_6_C15_C8_3 + +#endif /* CORTEX_A710_H */ diff --git a/include/lib/cpus/aarch64/cortex_a715.h b/include/lib/cpus/aarch64/cortex_a715.h new file mode 100644 index 0000000..950d02f --- /dev/null +++ b/include/lib/cpus/aarch64/cortex_a715.h @@ -0,0 +1,26 @@ +/* + * Copyright (c) 2021-2023, Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef CORTEX_A715_H +#define CORTEX_A715_H + +#define CORTEX_A715_MIDR U(0x410FD4D0) + +/* Cortex-A715 loop count for CVE-2022-23960 mitigation */ +#define CORTEX_A715_BHB_LOOP_COUNT U(38) + +/******************************************************************************* + * CPU Extended Control register specific definitions + ******************************************************************************/ +#define CORTEX_A715_CPUECTLR_EL1 S3_0_C15_C1_4 + +/******************************************************************************* + * CPU Power Control register specific definitions + ******************************************************************************/ +#define CORTEX_A715_CPUPWRCTLR_EL1 S3_0_C15_C2_7 +#define CORTEX_A715_CPUPWRCTLR_EL1_CORE_PWRDN_BIT U(1) + +#endif /* CORTEX_A715_H */ diff --git a/include/lib/cpus/aarch64/cortex_a72.h b/include/lib/cpus/aarch64/cortex_a72.h new file mode 100644 index 0000000..a00f6d6 --- /dev/null +++ b/include/lib/cpus/aarch64/cortex_a72.h @@ -0,0 +1,84 @@ +/* + * Copyright (c) 2015-2022, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef CORTEX_A72_H +#define CORTEX_A72_H + +#include <lib/utils_def.h> + +/* Cortex-A72 midr for revision 0 */ +#define CORTEX_A72_MIDR U(0x410FD080) + +/* Cortex-A72 loop count for CVE-2022-23960 mitigation */ +#define CORTEX_A72_BHB_LOOP_COUNT U(8) + +/******************************************************************************* + * CPU Extended Control register specific definitions. + ******************************************************************************/ +#define CORTEX_A72_ECTLR_EL1 S3_1_C15_C2_1 + +#define CORTEX_A72_ECTLR_SMP_BIT (ULL(1) << 6) +#define CORTEX_A72_ECTLR_DIS_TWD_ACC_PFTCH_BIT (ULL(1) << 38) +#define CORTEX_A72_ECTLR_L2_IPFTCH_DIST_MASK (ULL(0x3) << 35) +#define CORTEX_A72_ECTLR_L2_DPFTCH_DIST_MASK (ULL(0x3) << 32) + +/******************************************************************************* + * CPU Memory Error Syndrome register specific definitions. + ******************************************************************************/ +#define CORTEX_A72_MERRSR_EL1 S3_1_C15_C2_2 + +/******************************************************************************* + * CPU Auxiliary Control register specific definitions. + ******************************************************************************/ +#define CORTEX_A72_CPUACTLR_EL1 S3_1_C15_C2_0 + +#define CORTEX_A72_CPUACTLR_EL1_DISABLE_L1_DCACHE_HW_PFTCH (ULL(1) << 56) +#define CORTEX_A72_CPUACTLR_EL1_DIS_LOAD_PASS_STORE (ULL(1) << 55) +#define CORTEX_A72_CPUACTLR_EL1_NO_ALLOC_WBWA (ULL(1) << 49) +#define CORTEX_A72_CPUACTLR_EL1_DCC_AS_DCCI (ULL(1) << 44) +#define CORTEX_A72_CPUACTLR_EL1_DIS_INSTR_PREFETCH (ULL(1) << 32) +#define CORTEX_A72_CPUACTLR_EL1_DELAY_EXCLUSIVE_SNOOP (ULL(1) << 31) + +/******************************************************************************* + * L2 Auxiliary Control register specific definitions. + ******************************************************************************/ +#define CORTEX_A72_L2ACTLR_EL1 S3_1_C15_C0_0 + +#define CORTEX_A72_L2ACTLR_FORCE_TAG_BANK_CLK_ACTIVE (ULL(1) << 28) +#define CORTEX_A72_L2ACTLR_FORCE_L2_LOGIC_CLK_ACTIVE (ULL(1) << 27) +#define CORTEX_A72_L2ACTLR_FORCE_L2_GIC_TIMER_RCG_CLK_ACTIVE (ULL(1) << 26) +#define CORTEX_A72_L2ACTLR_ENABLE_UNIQUE_CLEAN (ULL(1) << 14) +#define CORTEX_A72_L2ACTLR_DISABLE_DSB_WITH_NO_DVM_SYNC (ULL(1) << 11) +#define CORTEX_A72_L2ACTLR_DISABLE_DVM_CMO_BROADCAST (ULL(1) << 8) +#define CORTEX_A72_L2ACTLR_ENABLE_HAZARD_DETECT_TIMEOUT (ULL(1) << 7) +#define CORTEX_A72_L2ACTLR_DISABLE_ACE_SH_OR_CHI (ULL(1) << 6) + +/******************************************************************************* + * L2 Control register specific definitions. + ******************************************************************************/ +#define CORTEX_A72_L2CTLR_EL1 S3_1_C11_C0_2 + +#define CORTEX_A72_L2CTLR_EL1_ECC_AND_PARITY_ENABLE (ULL(1) << 21) +#define CORTEX_A72_L2CTLR_EL1_DATA_INLINE_ECC_ENABLE (ULL(1) << 20) + +#define CORTEX_A72_L2CTLR_DATA_RAM_LATENCY_SHIFT U(0) +#define CORTEX_A72_L2CTLR_DATA_RAM_SETUP_SHIFT U(5) +#define CORTEX_A72_L2CTLR_TAG_RAM_LATENCY_SHIFT U(6) +#define CORTEX_A72_L2CTLR_TAG_RAM_SETUP_SHIFT U(9) + +#define CORTEX_A72_L2_DATA_RAM_LATENCY_MASK U(0x7) +#define CORTEX_A72_L2_TAG_RAM_LATENCY_MASK U(0x7) +#define CORTEX_A72_L2_DATA_RAM_LATENCY_3_CYCLES U(0x2) +#define CORTEX_A72_L2_DATA_RAM_LATENCY_4_CYCLES U(0x3) +#define CORTEX_A72_L2_TAG_RAM_LATENCY_2_CYCLES U(0x1) +#define CORTEX_A72_L2_TAG_RAM_LATENCY_3_CYCLES U(0x2) + +/******************************************************************************* + * L2 Memory Error Syndrome register specific definitions. + ******************************************************************************/ +#define CORTEX_A72_L2MERRSR_EL1 S3_1_C15_C2_3 + +#endif /* CORTEX_A72_H */ diff --git a/include/lib/cpus/aarch64/cortex_a720.h b/include/lib/cpus/aarch64/cortex_a720.h new file mode 100644 index 0000000..47bbbc0 --- /dev/null +++ b/include/lib/cpus/aarch64/cortex_a720.h @@ -0,0 +1,26 @@ +/* + * Copyright (c) 2021-2023, Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef CORTEX_A720_H +#define CORTEX_A720_H + +#define CORTEX_A720_MIDR U(0x410FD810) + +/* Cortex A720 loop count for CVE-2022-23960 mitigation */ +#define CORTEX_A720_BHB_LOOP_COUNT U(132) + +/******************************************************************************* + * CPU Extended Control register specific definitions + ******************************************************************************/ +#define CORTEX_A720_CPUECTLR_EL1 S3_0_C15_C1_4 + +/******************************************************************************* + * CPU Power Control register specific definitions + ******************************************************************************/ +#define CORTEX_A720_CPUPWRCTLR_EL1 S3_0_C15_C2_7 +#define CORTEX_A720_CPUPWRCTLR_EL1_CORE_PWRDN_BIT U(1) + +#endif /* CORTEX_A720_H */ diff --git a/include/lib/cpus/aarch64/cortex_a73.h b/include/lib/cpus/aarch64/cortex_a73.h new file mode 100644 index 0000000..ede76d1 --- /dev/null +++ b/include/lib/cpus/aarch64/cortex_a73.h @@ -0,0 +1,45 @@ +/* + * Copyright (c) 2016-2019, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef CORTEX_A73_H +#define CORTEX_A73_H + +#include <lib/utils_def.h> + +/* Cortex-A73 midr for revision 0 */ +#define CORTEX_A73_MIDR U(0x410FD090) + +/******************************************************************************* + * CPU Extended Control register specific definitions. + ******************************************************************************/ +#define CORTEX_A73_CPUECTLR_EL1 S3_1_C15_C2_1 /* Instruction def. */ + +#define CORTEX_A73_CPUECTLR_SMP_BIT (ULL(1) << 6) + +/******************************************************************************* + * L2 Memory Error Syndrome register specific definitions. + ******************************************************************************/ +#define CORTEX_A73_L2MERRSR_EL1 S3_1_C15_C2_3 /* Instruction def. */ + +/******************************************************************************* + * CPU implementation defined register specific definitions. + ******************************************************************************/ +#define CORTEX_A73_IMP_DEF_REG1 S3_0_C15_C0_0 + +#define CORTEX_A73_IMP_DEF_REG1_DISABLE_LOAD_PASS_STORE (ULL(1) << 3) + +#define CORTEX_A73_DIAGNOSTIC_REGISTER S3_0_C15_C0_1 + +#define CORTEX_A73_IMP_DEF_REG2 S3_0_C15_C0_2 + +/******************************************************************************* + * Helper function to access a73_cpuectlr_el1 register on Cortex-A73 CPUs + ******************************************************************************/ +#ifndef __ASSEMBLER__ +DEFINE_RENAME_SYSREG_RW_FUNCS(a73_cpuectlr_el1, CORTEX_A73_CPUECTLR_EL1) +#endif /* __ASSEMBLER__ */ + +#endif /* CORTEX_A73_H */ diff --git a/include/lib/cpus/aarch64/cortex_a75.h b/include/lib/cpus/aarch64/cortex_a75.h new file mode 100644 index 0000000..ca79991 --- /dev/null +++ b/include/lib/cpus/aarch64/cortex_a75.h @@ -0,0 +1,55 @@ +/* + * Copyright (c) 2017-2019, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef CORTEX_A75_H +#define CORTEX_A75_H + +#include <lib/utils_def.h> + +/* Cortex-A75 MIDR */ +#define CORTEX_A75_MIDR U(0x410fd0a0) + +/******************************************************************************* + * CPU Extended Control register specific definitions. + ******************************************************************************/ +#define CORTEX_A75_CPUPWRCTLR_EL1 S3_0_C15_C2_7 +#define CORTEX_A75_CPUECTLR_EL1 S3_0_C15_C1_4 + +/******************************************************************************* + * CPU Auxiliary Control register specific definitions. + ******************************************************************************/ +#define CORTEX_A75_CPUACTLR_EL1 S3_0_C15_C1_0 + +#define CORTEX_A75_CPUACTLR_EL1_DISABLE_LOAD_PASS_STORE (ULL(1) << 35) + +/* Definitions of register field mask in CORTEX_A75_CPUPWRCTLR_EL1 */ +#define CORTEX_A75_CORE_PWRDN_EN_MASK U(0x1) + +#define CORTEX_A75_ACTLR_AMEN_BIT (ULL(1) << 4) + +/* + * The Cortex-A75 core implements five counters, 0-4. Events 0, 1, 2, are + * fixed and are enabled (Group 0). Events 3 and 4 (Group 1) are + * programmable by programming the appropriate Event count bits in + * CPUAMEVTYPER<n> register and are disabled by default. Platforms may + * enable this with suitable programming. + */ +#define CORTEX_A75_AMU_NR_COUNTERS U(5) +#define CORTEX_A75_AMU_GROUP0_MASK U(0x7) +#define CORTEX_A75_AMU_GROUP1_MASK (U(0) << 3) + +#ifndef __ASSEMBLER__ +#include <stdint.h> + +uint64_t cortex_a75_amu_cnt_read(int idx); +void cortex_a75_amu_cnt_write(int idx, uint64_t val); +unsigned int cortex_a75_amu_read_cpuamcntenset_el0(void); +unsigned int cortex_a75_amu_read_cpuamcntenclr_el0(void); +void cortex_a75_amu_write_cpuamcntenset_el0(unsigned int mask); +void cortex_a75_amu_write_cpuamcntenclr_el0(unsigned int mask); +#endif /* __ASSEMBLER__ */ + +#endif /* CORTEX_A75_H */ diff --git a/include/lib/cpus/aarch64/cortex_a76.h b/include/lib/cpus/aarch64/cortex_a76.h new file mode 100644 index 0000000..b2ec8aa --- /dev/null +++ b/include/lib/cpus/aarch64/cortex_a76.h @@ -0,0 +1,51 @@ +/* + * Copyright (c) 2017-2023, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef CORTEX_A76_H +#define CORTEX_A76_H + +#include <lib/utils_def.h> + +/* Cortex-A76 MIDR for revision 0 */ +#define CORTEX_A76_MIDR U(0x410fd0b0) + +/* Cortex-A76 loop count for CVE-2022-23960 mitigation */ +#define CORTEX_A76_BHB_LOOP_COUNT U(24) + +/******************************************************************************* + * CPU Extended Control register specific definitions. + ******************************************************************************/ +#define CORTEX_A76_CPUPWRCTLR_EL1 S3_0_C15_C2_7 +#define CORTEX_A76_CPUECTLR_EL1 S3_0_C15_C1_4 + +#define CORTEX_A76_CPUECTLR_EL1_WS_THR_L2 (ULL(3) << 24) +#define CORTEX_A76_CPUECTLR_EL1_BIT_51 (ULL(1) << 51) + +/******************************************************************************* + * CPU Auxiliary Control register specific definitions. + ******************************************************************************/ +#define CORTEX_A76_CPUACTLR_EL1 S3_0_C15_C1_0 + +#define CORTEX_A76_CPUACTLR_EL1_DISABLE_STATIC_PREDICTION (ULL(1) << 6) + +#define CORTEX_A76_CPUACTLR_EL1_BIT_13 (ULL(1) << 13) + +#define CORTEX_A76_CPUACTLR2_EL1 S3_0_C15_C1_1 + +#define CORTEX_A76_CPUACTLR2_EL1_BIT_2 (ULL(1) << 2) +#define CORTEX_A76_CPUACTLR2_EL1_BIT_59 (ULL(1) << 59) + +#define CORTEX_A76_CPUACTLR2_EL1_DISABLE_LOAD_PASS_STORE (ULL(1) << 16) + +#define CORTEX_A76_CPUACTLR3_EL1 S3_0_C15_C1_2 + +#define CORTEX_A76_CPUACTLR3_EL1_BIT_10 (ULL(1) << 10) + + +/* Definitions of register field mask in CORTEX_A76_CPUPWRCTLR_EL1 */ +#define CORTEX_A76_CORE_PWRDN_EN_MASK U(0x1) + +#endif /* CORTEX_A76_H */ diff --git a/include/lib/cpus/aarch64/cortex_a76ae.h b/include/lib/cpus/aarch64/cortex_a76ae.h new file mode 100644 index 0000000..0d30f70 --- /dev/null +++ b/include/lib/cpus/aarch64/cortex_a76ae.h @@ -0,0 +1,28 @@ +/* + * Copyright (c) 2019-2022, Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef CORTEX_A76AE_H +#define CORTEX_A76AE_H + +#include <lib/utils_def.h> + +/* Cortex-A76AE MIDR for revision 0 */ +#define CORTEX_A76AE_MIDR U(0x410FD0E0) + +/* Cortex-A76 loop count for CVE-2022-23960 mitigation */ +#define CORTEX_A76AE_BHB_LOOP_COUNT U(24) + +/******************************************************************************* + * CPU Extended Control register specific definitions. + ******************************************************************************/ +#define CORTEX_A76AE_CPUPWRCTLR_EL1 S3_0_C15_C2_7 + +/* Definitions of register field mask in CORTEX_A76AE_CPUPWRCTLR_EL1 */ +#define CORTEX_A76AE_CORE_PWRDN_EN_MASK U(0x1) + +#define CORTEX_A76AE_CPUECTLR_EL1 S3_0_C15_C1_4 + +#endif /* CORTEX_A76AE_H */ diff --git a/include/lib/cpus/aarch64/cortex_a77.h b/include/lib/cpus/aarch64/cortex_a77.h new file mode 100644 index 0000000..39717a3 --- /dev/null +++ b/include/lib/cpus/aarch64/cortex_a77.h @@ -0,0 +1,45 @@ +/* + * Copyright (c) 2018-2022, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef CORTEX_A77_H +#define CORTEX_A77_H + +#include <lib/utils_def.h> + +/* Cortex-A77 MIDR */ +#define CORTEX_A77_MIDR U(0x410FD0D0) + +/* Cortex-A77 loop count for CVE-2022-23960 mitigation */ +#define CORTEX_A77_BHB_LOOP_COUNT U(24) + +/******************************************************************************* + * CPU Extended Control register specific definitions. + ******************************************************************************/ +#define CORTEX_A77_CPUECTLR_EL1 S3_0_C15_C1_4 +#define CORTEX_A77_CPUECTLR_EL1_BIT_8 (ULL(1) << 8) +#define CORTEX_A77_CPUECTLR_EL1_BIT_53 (ULL(1) << 53) + +/******************************************************************************* + * CPU Power Control register specific definitions. + ******************************************************************************/ +#define CORTEX_A77_CPUPWRCTLR_EL1 S3_0_C15_C2_7 +#define CORTEX_A77_CPUPWRCTLR_EL1_CORE_PWRDN_BIT (U(1) << 0) + +/******************************************************************************* + * CPU Auxiliary Control register specific definitions. + ******************************************************************************/ +#define CORTEX_A77_ACTLR2_EL1 S3_0_C15_C1_1 +#define CORTEX_A77_ACTLR2_EL1_BIT_2 (ULL(1) << 2) +#define CORTEX_A77_ACTLR2_EL1_BIT_0 ULL(1) + +#define CORTEX_A77_CPUPSELR_EL3 S3_6_C15_C8_0 +#define CORTEX_A77_CPUPCR_EL3 S3_6_C15_C8_1 +#define CORTEX_A77_CPUPOR_EL3 S3_6_C15_C8_2 +#define CORTEX_A77_CPUPMR_EL3 S3_6_C15_C8_3 +#define CORTEX_A77_CPUPOR2_EL3 S3_6_C15_C8_4 +#define CORTEX_A77_CPUPMR2_EL3 S3_6_C15_C8_5 + +#endif /* CORTEX_A77_H */ diff --git a/include/lib/cpus/aarch64/cortex_a78.h b/include/lib/cpus/aarch64/cortex_a78.h new file mode 100644 index 0000000..2984f82 --- /dev/null +++ b/include/lib/cpus/aarch64/cortex_a78.h @@ -0,0 +1,58 @@ +/* + * Copyright (c) 2019-2023, Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef CORTEX_A78_H +#define CORTEX_A78_H + +#include <lib/utils_def.h> + +#define CORTEX_A78_MIDR U(0x410FD410) + +/* Cortex-A78 loop count for CVE-2022-23960 mitigation */ +#define CORTEX_A78_BHB_LOOP_COUNT U(32) + +/******************************************************************************* + * CPU Extended Control register specific definitions. + ******************************************************************************/ +#define CORTEX_A78_CPUECTLR_EL1 S3_0_C15_C1_4 +#define CORTEX_A78_CPUECTLR_EL1_BIT_8 (ULL(1) << 8) +#define CORTEX_A78_CPUECTLR_EL1_PF_MODE_CNSRV ULL(3) +#define CPUECTLR_EL1_PF_MODE_LSB U(6) +#define CPUECTLR_EL1_PF_MODE_WIDTH U(2) + +/******************************************************************************* + * CPU Power Control register specific definitions + ******************************************************************************/ +#define CORTEX_A78_CPUPWRCTLR_EL1 S3_0_C15_C2_7 +#define CORTEX_A78_CPUPWRCTLR_EL1_CORE_PWRDN_EN_BIT U(1) + +/******************************************************************************* + * CPU Auxiliary Control register specific definitions. + ******************************************************************************/ +#define CORTEX_A78_ACTLR_TAM_BIT (ULL(1) << 30) + +#define CORTEX_A78_ACTLR2_EL1 S3_0_C15_C1_1 +#define CORTEX_A78_ACTLR2_EL1_BIT_0 (ULL(1) << 0) +#define CORTEX_A78_ACTLR2_EL1_BIT_1 (ULL(1) << 1) +#define CORTEX_A78_ACTLR2_EL1_BIT_2 (ULL(1) << 2) +#define CORTEX_A78_ACTLR2_EL1_BIT_40 (ULL(1) << 40) + +#define CORTEX_A78_ACTLR3_EL1 S3_0_C15_C1_2 + +#define CORTEX_A78_ACTLR5_EL1 S3_0_C15_C9_0 + +/******************************************************************************* + * CPU Activity Monitor Unit register specific definitions. + ******************************************************************************/ +#define CPUAMCNTENCLR0_EL0 S3_3_C15_C2_4 +#define CPUAMCNTENSET0_EL0 S3_3_C15_C2_5 +#define CPUAMCNTENCLR1_EL0 S3_3_C15_C3_0 +#define CPUAMCNTENSET1_EL0 S3_3_C15_C3_1 + +#define CORTEX_A78_AMU_GROUP0_MASK U(0xF) +#define CORTEX_A78_AMU_GROUP1_MASK U(0x7) + +#endif /* CORTEX_A78_H */ diff --git a/include/lib/cpus/aarch64/cortex_a78_ae.h b/include/lib/cpus/aarch64/cortex_a78_ae.h new file mode 100644 index 0000000..4ada845 --- /dev/null +++ b/include/lib/cpus/aarch64/cortex_a78_ae.h @@ -0,0 +1,31 @@ +/* + * Copyright (c) 2019-2022, Arm Limited. All rights reserved. + * Copyright (c) 2021-2022, NVIDIA Corporation. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef CORTEX_A78_AE_H +#define CORTEX_A78_AE_H + +#include <cortex_a78.h> + +#define CORTEX_A78_AE_MIDR U(0x410FD420) + +/* Cortex-A78AE loop count for CVE-2022-23960 mitigation */ +#define CORTEX_A78_AE_BHB_LOOP_COUNT U(32) + +/******************************************************************************* + * CPU Extended Control register specific definitions. + ******************************************************************************/ +#define CORTEX_A78_AE_CPUECTLR_EL1 CORTEX_A78_CPUECTLR_EL1 +#define CORTEX_A78_AE_CPUECTLR_EL1_BIT_8 CORTEX_A78_CPUECTLR_EL1_BIT_8 + +/******************************************************************************* + * CPU Auxiliary Control register 2 specific definitions. + ******************************************************************************/ +#define CORTEX_A78_AE_ACTLR2_EL1 CORTEX_A78_ACTLR2_EL1 +#define CORTEX_A78_AE_ACTLR2_EL1_BIT_0 CORTEX_A78_ACTLR2_EL1_BIT_0 +#define CORTEX_A78_AE_ACTLR2_EL1_BIT_40 CORTEX_A78_ACTLR2_EL1_BIT_40 + +#endif /* CORTEX_A78_AE_H */ diff --git a/include/lib/cpus/aarch64/cortex_a78c.h b/include/lib/cpus/aarch64/cortex_a78c.h new file mode 100644 index 0000000..301be69 --- /dev/null +++ b/include/lib/cpus/aarch64/cortex_a78c.h @@ -0,0 +1,50 @@ +/* + * Copyright (c) 2021-2023, Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef CORTEX_A78C_H +#define CORTEX_A78C_H + + +#define CORTEX_A78C_MIDR U(0x410FD4B1) + +/* Cortex-A76 loop count for CVE-2022-23960 mitigation */ +#define CORTEX_A78C_BHB_LOOP_COUNT U(32) + +/******************************************************************************* + * CPU Auxiliary Control register 2 specific definitions. + * ****************************************************************************/ +#define CORTEX_A78C_CPUACTLR2_EL1 S3_0_C15_C1_1 +#define CORTEX_A78C_CPUACTLR2_EL1_BIT_0 (ULL(1) << 0) +#define CORTEX_A78C_CPUACTLR2_EL1_BIT_40 (ULL(1) << 40) + +/******************************************************************************* + * CPU Extended Control register specific definitions. + ******************************************************************************/ +#define CORTEX_A78C_CPUECTLR_EL1 S3_0_C15_C1_4 +#define CORTEX_A78C_CPUECTLR_EL1_BIT_6 (ULL(1) << 6) +#define CORTEX_A78C_CPUECTLR_EL1_BIT_7 (ULL(1) << 7) +#define CORTEX_A78C_CPUECTLR_EL1_MM_ASP_EN (ULL(1) << 53) + +/******************************************************************************* + * CPU Power Control register specific definitions + ******************************************************************************/ +#define CORTEX_A78C_CPUPWRCTLR_EL1 S3_0_C15_C2_7 +#define CORTEX_A78C_CPUPWRCTLR_EL1_CORE_PWRDN_EN_BIT U(1) + +/******************************************************************************* + * CPU Auxiliary Control register 3 specific definitions. + ******************************************************************************/ +#define CORTEX_A78C_ACTLR3_EL1 S3_0_C15_C1_2 + +/******************************************************************************* + * CPU Implementation Specific Selected Instruction registers + ******************************************************************************/ +#define CORTEX_A78C_IMP_CPUPSELR_EL3 S3_6_C15_C8_0 +#define CORTEX_A78C_IMP_CPUPCR_EL3 S3_6_C15_C8_1 +#define CORTEX_A78C_IMP_CPUPOR_EL3 S3_6_C15_C8_2 +#define CORTEX_A78C_IMP_CPUPMR_EL3 S3_6_C15_C8_3 + +#endif /* CORTEX_A78C_H */ diff --git a/include/lib/cpus/aarch64/cortex_blackhawk.h b/include/lib/cpus/aarch64/cortex_blackhawk.h new file mode 100644 index 0000000..bfb3039 --- /dev/null +++ b/include/lib/cpus/aarch64/cortex_blackhawk.h @@ -0,0 +1,23 @@ +/* + * Copyright (c) 2023, Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef CORTEX_BLACKHAWK_H +#define CORTEX_BLACKHAWK_H + +#define CORTEX_BLACKHAWK_MIDR U(0x410FD850) + +/******************************************************************************* + * CPU Extended Control register specific definitions + ******************************************************************************/ +#define CORTEX_BLACKHAWK_CPUECTLR_EL1 S3_0_C15_C1_4 + +/******************************************************************************* + * CPU Power Control register specific definitions + ******************************************************************************/ +#define CORTEX_BLACKHAWK_CPUPWRCTLR_EL1 S3_0_C15_C2_7 +#define CORTEX_BLACKHAWK_CPUPWRCTLR_EL1_CORE_PWRDN_BIT U(1) + +#endif /* CORTEX_BLACKHAWK_H */ diff --git a/include/lib/cpus/aarch64/cortex_chaberton.h b/include/lib/cpus/aarch64/cortex_chaberton.h new file mode 100644 index 0000000..8f10b68 --- /dev/null +++ b/include/lib/cpus/aarch64/cortex_chaberton.h @@ -0,0 +1,23 @@ +/* + * Copyright (c) 2023, Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef CORTEX_CHABERTON_H +#define CORTEX_CHABERTON_H + +#define CORTEX_CHABERTON_MIDR U(0x410FD870) + +/******************************************************************************* + * CPU Extended Control register specific definitions + ******************************************************************************/ +#define CORTEX_CHABERTON_CPUECTLR_EL1 S3_0_C15_C1_4 + +/******************************************************************************* + * CPU Power Control register specific definitions + ******************************************************************************/ +#define CORTEX_CHABERTON_CPUPWRCTLR_EL1 S3_0_C15_C2_7 +#define CORTEX_CHABERTON_CPUPWRCTLR_EL1_CORE_PWRDN_BIT U(1) + +#endif /* CORTEX_CHABERTON_H */ diff --git a/include/lib/cpus/aarch64/cortex_gelas.h b/include/lib/cpus/aarch64/cortex_gelas.h new file mode 100644 index 0000000..90bb78f --- /dev/null +++ b/include/lib/cpus/aarch64/cortex_gelas.h @@ -0,0 +1,31 @@ +/* + * Copyright (c) 2023, Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef CORTEX_GELAS_H +#define CORTEX_GELAS_H + +#include <lib/utils_def.h> + +#define CORTEX_GELAS_MIDR U(0x410FD8B0) + +/******************************************************************************* + * CPU Extended Control register specific definitions + ******************************************************************************/ +#define CORTEX_GELAS_IMP_CPUECTLR_EL1 S3_0_C15_C1_5 + +/******************************************************************************* + * CPU Power Control register specific definitions + ******************************************************************************/ +#define CORTEX_GELAS_CPUPWRCTLR_EL1 S3_0_C15_C2_7 +#define CORTEX_GELAS_CPUPWRCTLR_EL1_CORE_PWRDN_BIT U(1) + +/******************************************************************************* + * SME Control registers + ******************************************************************************/ +#define CORTEX_GELAS_SVCRSM S0_3_C4_C2_3 +#define CORTEX_GELAS_SVCRZA S0_3_C4_C4_3 + +#endif /* CORTEX_GELAS_H */ diff --git a/include/lib/cpus/aarch64/cortex_x1.h b/include/lib/cpus/aarch64/cortex_x1.h new file mode 100644 index 0000000..e3661a8 --- /dev/null +++ b/include/lib/cpus/aarch64/cortex_x1.h @@ -0,0 +1,32 @@ +/* + * Copyright (c) 2022, Google LLC. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef CORTEX_X1_H +#define CORTEX_X1_H + +/* Cortex-X1 MIDR for r1p0 */ +#define CORTEX_X1_MIDR U(0x411fd440) + +/* Cortex-X1 loop count for CVE-2022-23960 mitigation */ +#define CORTEX_X1_BHB_LOOP_COUNT U(32) + +/******************************************************************************* + * CPU Extended Control register specific definitions. + ******************************************************************************/ +#define CORTEX_X1_CPUECTLR_EL1 S3_0_C15_C1_4 + +/******************************************************************************* + * CPU Auxiliary Control register specific definitions. + ******************************************************************************/ +#define CORTEX_X1_ACTLR2_EL1 S3_0_C15_C1_1 + +/******************************************************************************* + * CPU Power Control register specific definitions + ******************************************************************************/ +#define CORTEX_X1_CPUPWRCTLR_EL1 S3_0_C15_C2_7 +#define CORTEX_X1_CORE_PWRDN_EN_MASK U(0x1) + +#endif /* CORTEX_X1_H */ diff --git a/include/lib/cpus/aarch64/cortex_x2.h b/include/lib/cpus/aarch64/cortex_x2.h new file mode 100644 index 0000000..863b8c8 --- /dev/null +++ b/include/lib/cpus/aarch64/cortex_x2.h @@ -0,0 +1,62 @@ +/* + * Copyright (c) 2021-2022, Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef CORTEX_X2_H +#define CORTEX_X2_H + +#define CORTEX_X2_MIDR U(0x410FD480) + +/* Cortex-X2 loop count for CVE-2022-23960 mitigation */ +#define CORTEX_X2_BHB_LOOP_COUNT U(32) + +/******************************************************************************* + * CPU Extended Control register specific definitions + ******************************************************************************/ +#define CORTEX_X2_CPUECTLR_EL1 S3_0_C15_C1_4 +#define CORTEX_X2_CPUECTLR_EL1_PFSTIDIS_BIT (ULL(1) << 8) + +/******************************************************************************* + * CPU Extended Control register 2 specific definitions + ******************************************************************************/ +#define CORTEX_X2_CPUECTLR2_EL1 S3_0_C15_C1_5 + +#define CORTEX_X2_CPUECTLR2_EL1_PF_MODE_SHIFT U(11) +#define CORTEX_X2_CPUECTLR2_EL1_PF_MODE_WIDTH U(4) +#define CORTEX_X2_CPUECTLR2_EL1_PF_MODE_CNSRV ULL(0x9) + +/******************************************************************************* + * CPU Power Control register specific definitions + ******************************************************************************/ +#define CORTEX_X2_CPUPWRCTLR_EL1 S3_0_C15_C2_7 +#define CORTEX_X2_CPUPWRCTLR_EL1_CORE_PWRDN_BIT U(1) + +/******************************************************************************* + * CPU Auxiliary Control Register definitions + ******************************************************************************/ +#define CORTEX_X2_CPUACTLR_EL1 S3_0_C15_C1_0 +#define CORTEX_X2_CPUACTLR_EL1_BIT_22 (ULL(1) << 22) + +/******************************************************************************* + * CPU Auxiliary Control Register 2 definitions + ******************************************************************************/ +#define CORTEX_X2_CPUACTLR2_EL1 S3_0_C15_C1_1 +#define CORTEX_X2_CPUACTLR2_EL1_BIT_40 (ULL(1) << 40) + +/******************************************************************************* + * CPU Auxiliary Control Register 5 definitions + ******************************************************************************/ +#define CORTEX_X2_CPUACTLR5_EL1 S3_0_C15_C8_0 +#define CORTEX_X2_CPUACTLR5_EL1_BIT_17 (ULL(1) << 17) + +/******************************************************************************* + * CPU Implementation Specific Selected Instruction registers + ******************************************************************************/ +#define CORTEX_X2_IMP_CPUPSELR_EL3 S3_6_C15_C8_0 +#define CORTEX_X2_IMP_CPUPCR_EL3 S3_6_C15_C8_1 +#define CORTEX_X2_IMP_CPUPOR_EL3 S3_6_C15_C8_2 +#define CORTEX_X2_IMP_CPUPMR_EL3 S3_6_C15_C8_3 + +#endif /* CORTEX_X2_H */ diff --git a/include/lib/cpus/aarch64/cortex_x3.h b/include/lib/cpus/aarch64/cortex_x3.h new file mode 100644 index 0000000..04548ea --- /dev/null +++ b/include/lib/cpus/aarch64/cortex_x3.h @@ -0,0 +1,50 @@ +/* + * Copyright (c) 2021-2023, Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef CORTEX_X3_H +#define CORTEX_X3_H + +#define CORTEX_X3_MIDR U(0x410FD4E0) + +/* Cortex-X3 loop count for CVE-2022-23960 mitigation */ +#define CORTEX_X3_BHB_LOOP_COUNT U(132) + +/******************************************************************************* + * CPU Extended Control register specific definitions + ******************************************************************************/ +#define CORTEX_X3_CPUECTLR_EL1 S3_0_C15_C1_4 + +/******************************************************************************* + * CPU Power Control register specific definitions + ******************************************************************************/ +#define CORTEX_X3_CPUPWRCTLR_EL1 S3_0_C15_C2_7 +#define CORTEX_X3_CPUPWRCTLR_EL1_CORE_PWRDN_BIT U(1) +#define CORTEX_X3_CPUPWRCTLR_EL1_WFI_RET_CTRL_BITS_SHIFT U(4) +#define CORTEX_X3_CPUPWRCTLR_EL1_WFE_RET_CTRL_BITS_SHIFT U(7) + +/******************************************************************************* + * CPU Auxiliary Control register 2 specific definitions. + ******************************************************************************/ +#define CORTEX_X3_CPUACTLR2_EL1 S3_0_C15_C1_1 +#define CORTEX_X3_CPUACTLR2_EL1_BIT_36 (ULL(1) << 36) + +/******************************************************************************* + * CPU Auxiliary Control register 5 specific definitions. + ******************************************************************************/ +#define CORTEX_X3_CPUACTLR5_EL1 S3_0_C15_C8_0 +#define CORTEX_X3_CPUACTLR5_EL1_BIT_55 (ULL(1) << 55) +#define CORTEX_X3_CPUACTLR5_EL1_BIT_56 (ULL(1) << 56) + +/******************************************************************************* + * CPU Extended Control register 2 specific definitions. + ******************************************************************************/ +#define CORTEX_X3_CPUECTLR2_EL1 S3_0_C15_C1_5 + +#define CORTEX_X3_CPUECTLR2_EL1_PF_MODE_LSB U(11) +#define CORTEX_X3_CPUECTLR2_EL1_PF_MODE_WIDTH U(4) +#define CORTEX_X3_CPUECTLR2_EL1_PF_MODE_CNSRV ULL(0x9) + +#endif /* CORTEX_X3_H */ diff --git a/include/lib/cpus/aarch64/cortex_x4.h b/include/lib/cpus/aarch64/cortex_x4.h new file mode 100644 index 0000000..17d07c8 --- /dev/null +++ b/include/lib/cpus/aarch64/cortex_x4.h @@ -0,0 +1,26 @@ +/* + * Copyright (c) 2022-2023, Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef CORTEX_X4_H +#define CORTEX_X4_H + +#define CORTEX_X4_MIDR U(0x410FD821) + +/* Cortex X4 loop count for CVE-2022-23960 mitigation */ +#define CORTEX_X4_BHB_LOOP_COUNT U(132) + +/******************************************************************************* + * CPU Extended Control register specific definitions + ******************************************************************************/ +#define CORTEX_X4_CPUECTLR_EL1 S3_0_C15_C1_4 + +/******************************************************************************* + * CPU Power Control register specific definitions + ******************************************************************************/ +#define CORTEX_X4_CPUPWRCTLR_EL1 S3_0_C15_C2_7 +#define CORTEX_X4_CPUPWRCTLR_EL1_CORE_PWRDN_BIT U(1) + +#endif /* CORTEX_X4_H */ diff --git a/include/lib/cpus/aarch64/cpu_macros.S b/include/lib/cpus/aarch64/cpu_macros.S new file mode 100644 index 0000000..6faef5d --- /dev/null +++ b/include/lib/cpus/aarch64/cpu_macros.S @@ -0,0 +1,636 @@ +/* + * Copyright (c) 2014-2023, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef CPU_MACROS_S +#define CPU_MACROS_S + +#include <assert_macros.S> +#include <lib/cpus/cpu_ops.h> +#include <lib/cpus/errata.h> + + /* + * Write given expressions as quad words + * + * _count: + * Write at least _count quad words. If the given number of + * expressions is less than _count, repeat the last expression to + * fill _count quad words in total + * _rest: + * Optional list of expressions. _this is for parameter extraction + * only, and has no significance to the caller + * + * Invoked as: + * fill_constants 2, foo, bar, blah, ... + */ + .macro fill_constants _count:req, _this, _rest:vararg + .ifgt \_count + /* Write the current expression */ + .ifb \_this + .error "Nothing to fill" + .endif + .quad \_this + + /* Invoke recursively for remaining expressions */ + .ifnb \_rest + fill_constants \_count-1, \_rest + .else + fill_constants \_count-1, \_this + .endif + .endif + .endm + + /* + * Declare CPU operations + * + * _name: + * Name of the CPU for which operations are being specified + * _midr: + * Numeric value expected to read from CPU's MIDR + * _resetfunc: + * Reset function for the CPU. If there's no CPU reset function, + * specify CPU_NO_RESET_FUNC + * _extra1: + * This is a placeholder for future per CPU operations. Currently, + * some CPUs use this entry to set a test function to determine if + * the workaround for CVE-2017-5715 needs to be applied or not. + * _extra2: + * This is a placeholder for future per CPU operations. Currently + * some CPUs use this entry to set a function to disable the + * workaround for CVE-2018-3639. + * _extra3: + * This is a placeholder for future per CPU operations. Currently, + * some CPUs use this entry to set a test function to determine if + * the workaround for CVE-2022-23960 needs to be applied or not. + * _e_handler: + * This is a placeholder for future per CPU exception handlers. + * _power_down_ops: + * Comma-separated list of functions to perform power-down + * operatios on the CPU. At least one, and up to + * CPU_MAX_PWR_DWN_OPS number of functions may be specified. + * Starting at power level 0, these functions shall handle power + * down at subsequent power levels. If there aren't exactly + * CPU_MAX_PWR_DWN_OPS functions, the last specified one will be + * used to handle power down at subsequent levels + */ + .macro declare_cpu_ops_base _name:req, _midr:req, _resetfunc:req, \ + _extra1:req, _extra2:req, _extra3:req, _e_handler:req, _power_down_ops:vararg + .section .cpu_ops, "a" + .align 3 + .type cpu_ops_\_name, %object + .quad \_midr +#if defined(IMAGE_AT_EL3) + .quad \_resetfunc +#endif + .quad \_extra1 + .quad \_extra2 + .quad \_extra3 + .quad \_e_handler +#ifdef IMAGE_BL31 + /* Insert list of functions */ + fill_constants CPU_MAX_PWR_DWN_OPS, \_power_down_ops +#endif + /* + * It is possible (although unlikely) that a cpu may have no errata in + * code. In that case the start label will not be defined. The list is + * intended to be used in a loop, so define it as zero-length for + * predictable behaviour. Since this macro is always called at the end + * of the cpu file (after all errata have been parsed) we can be sure + * that we are at the end of the list. Some cpus call declare_cpu_ops + * twice, so only do this once. + */ + .pushsection .rodata.errata_entries + .ifndef \_name\()_errata_list_start + \_name\()_errata_list_start: + .endif + .ifndef \_name\()_errata_list_end + \_name\()_errata_list_end: + .endif + .popsection + + /* and now put them in cpu_ops */ + .quad \_name\()_errata_list_start + .quad \_name\()_errata_list_end + +#if REPORT_ERRATA + .ifndef \_name\()_cpu_str + /* + * Place errata reported flag, and the spinlock to arbitrate access to + * it in the data section. + */ + .pushsection .data + define_asm_spinlock \_name\()_errata_lock + \_name\()_errata_reported: + .word 0 + .popsection + + /* Place CPU string in rodata */ + .pushsection .rodata + \_name\()_cpu_str: + .asciz "\_name" + .popsection + .endif + + + /* + * Mandatory errata status printing function for CPUs of + * this class. + */ + .quad \_name\()_errata_report + .quad \_name\()_cpu_str + +#ifdef IMAGE_BL31 + /* Pointers to errata lock and reported flag */ + .quad \_name\()_errata_lock + .quad \_name\()_errata_reported +#endif /* IMAGE_BL31 */ +#endif /* REPORT_ERRATA */ + +#if defined(IMAGE_BL31) && CRASH_REPORTING + .quad \_name\()_cpu_reg_dump +#endif + .endm + + .macro declare_cpu_ops _name:req, _midr:req, _resetfunc:req, \ + _power_down_ops:vararg + declare_cpu_ops_base \_name, \_midr, \_resetfunc, 0, 0, 0, 0, \ + \_power_down_ops + .endm + + .macro declare_cpu_ops_eh _name:req, _midr:req, _resetfunc:req, \ + _e_handler:req, _power_down_ops:vararg + declare_cpu_ops_base \_name, \_midr, \_resetfunc, \ + 0, 0, 0, \_e_handler, \_power_down_ops + .endm + + .macro declare_cpu_ops_wa _name:req, _midr:req, \ + _resetfunc:req, _extra1:req, _extra2:req, \ + _extra3:req, _power_down_ops:vararg + declare_cpu_ops_base \_name, \_midr, \_resetfunc, \ + \_extra1, \_extra2, \_extra3, 0, \_power_down_ops + .endm + +/* TODO can be deleted once all CPUs have been converted */ +#if REPORT_ERRATA + /* + * Print status of a CPU errata + * + * _chosen: + * Identifier indicating whether or not a CPU errata has been + * compiled in. + * _cpu: + * Name of the CPU + * _id: + * Errata identifier + * _rev_var: + * Register containing the combined value CPU revision and variant + * - typically the return value of cpu_get_rev_var + */ + .macro report_errata _chosen, _cpu, _id, _rev_var=x8 + /* Stash a string with errata ID */ + .pushsection .rodata + \_cpu\()_errata_\_id\()_str: + .asciz "\_id" + .popsection + + /* Check whether errata applies */ + mov x0, \_rev_var + /* Shall clobber: x0-x7 */ + bl check_errata_\_id + + .ifeq \_chosen + /* + * Errata workaround has not been compiled in. If the errata would have + * applied had it been compiled in, print its status as missing. + */ + cbz x0, 900f + mov x0, #ERRATA_MISSING + .endif +900: + adr x1, \_cpu\()_cpu_str + adr x2, \_cpu\()_errata_\_id\()_str + bl errata_print_msg + .endm +#endif + + /* + * This macro is used on some CPUs to detect if they are vulnerable + * to CVE-2017-5715. + */ + .macro cpu_check_csv2 _reg _label + mrs \_reg, id_aa64pfr0_el1 + ubfx \_reg, \_reg, #ID_AA64PFR0_CSV2_SHIFT, #ID_AA64PFR0_CSV2_LENGTH + /* + * If the field equals 1, branch targets trained in one context cannot + * affect speculative execution in a different context. + * + * If the field equals 2, it means that the system is also aware of + * SCXTNUM_ELx register contexts. We aren't using them in the TF, so we + * expect users of the registers to do the right thing. + * + * Only apply mitigations if the value of this field is 0. + */ +#if ENABLE_ASSERTIONS + cmp \_reg, #3 /* Only values 0 to 2 are expected */ + ASM_ASSERT(lo) +#endif + + cmp \_reg, #0 + bne \_label + .endm + + /* + * Helper macro that reads the part number of the current + * CPU and jumps to the given label if it matches the CPU + * MIDR provided. + * + * Clobbers x0. + */ + .macro jump_if_cpu_midr _cpu_midr, _label + mrs x0, midr_el1 + ubfx x0, x0, MIDR_PN_SHIFT, #12 + cmp w0, #((\_cpu_midr >> MIDR_PN_SHIFT) & MIDR_PN_MASK) + b.eq \_label + .endm + + +/* + * Workaround wrappers for errata that apply at reset or runtime. Reset errata + * will be applied automatically + * + * _cpu: + * Name of cpu as given to declare_cpu_ops + * + * _cve: + * Whether erratum is a CVE. CVE year if yes, 0 otherwise + * + * _id: + * Erratum or CVE number. Please combine with previous field with ERRATUM + * or CVE macros + * + * _chosen: + * Compile time flag on whether the erratum is included + * + * _apply_at_reset: + * Whether the erratum should be automatically applied at reset + */ +.macro add_erratum_entry _cpu:req, _cve:req, _id:req, _chosen:req, _apply_at_reset:req + .pushsection .rodata.errata_entries + .align 3 + .ifndef \_cpu\()_errata_list_start + \_cpu\()_errata_list_start: + .endif + + /* check if unused and compile out if no references */ + .if \_apply_at_reset && \_chosen + .quad erratum_\_cpu\()_\_id\()_wa + .else + .quad 0 + .endif + /* TODO(errata ABI): this prevents all checker functions from + * being optimised away. Can be done away with unless the ABI + * needs them */ + .quad check_erratum_\_cpu\()_\_id + /* Will fit CVEs with up to 10 character in the ID field */ + .word \_id + .hword \_cve + .byte \_chosen + /* TODO(errata ABI): mitigated field for known but unmitigated + * errata */ + .byte 0x1 + .popsection +.endm + +.macro _workaround_start _cpu:req, _cve:req, _id:req, _chosen:req, _apply_at_reset:req + add_erratum_entry \_cpu, \_cve, \_id, \_chosen, \_apply_at_reset + + func erratum_\_cpu\()_\_id\()_wa + mov x8, x30 + + /* save rev_var for workarounds that might need it but don't + * restore to x0 because few will care */ + mov x7, x0 + bl check_erratum_\_cpu\()_\_id + cbz x0, erratum_\_cpu\()_\_id\()_skip +.endm + +.macro _workaround_end _cpu:req, _id:req + erratum_\_cpu\()_\_id\()_skip: + ret x8 + endfunc erratum_\_cpu\()_\_id\()_wa +.endm + +/******************************************************************************* + * Errata workaround wrappers + ******************************************************************************/ +/* + * Workaround wrappers for errata that apply at reset or runtime. Reset errata + * will be applied automatically + * + * _cpu: + * Name of cpu as given to declare_cpu_ops + * + * _cve: + * Whether erratum is a CVE. CVE year if yes, 0 otherwise + * + * _id: + * Erratum or CVE number. Please combine with previous field with ERRATUM + * or CVE macros + * + * _chosen: + * Compile time flag on whether the erratum is included + * + * in body: + * clobber x0 to x7 (please only use those) + * argument x7 - cpu_rev_var + * + * _wa clobbers: x0-x8 (PCS compliant) + */ +.macro workaround_reset_start _cpu:req, _cve:req, _id:req, _chosen:req + _workaround_start \_cpu, \_cve, \_id, \_chosen, 1 +.endm + +/* + * See `workaround_reset_start` for usage info. Additional arguments: + * + * _midr: + * Check if CPU's MIDR matches the CPU it's meant for. Must be specified + * for errata applied in generic code + */ +.macro workaround_runtime_start _cpu:req, _cve:req, _id:req, _chosen:req, _midr + /* + * Let errata specify if they need MIDR checking. Sadly, storing the + * MIDR in an .equ to retrieve automatically blows up as it stores some + * brackets in the symbol + */ + .ifnb \_midr + jump_if_cpu_midr \_midr, 1f + b erratum_\_cpu\()_\_id\()_skip + + 1: + .endif + _workaround_start \_cpu, \_cve, \_id, \_chosen, 0 +.endm + +/* + * Usage and arguments identical to `workaround_reset_start`. The _cve argument + * is kept here so the same #define can be used as that macro + */ +.macro workaround_reset_end _cpu:req, _cve:req, _id:req + _workaround_end \_cpu, \_id +.endm + +/* + * See `workaround_reset_start` for usage info. The _cve argument is kept here + * so the same #define can be used as that macro. Additional arguments: + * + * _no_isb: + * Optionally do not include the trailing isb. Please disable with the + * NO_ISB macro + */ +.macro workaround_runtime_end _cpu:req, _cve:req, _id:req, _no_isb + /* + * Runtime errata do not have a reset function to call the isb for them + * and missing the isb could be very problematic. It is also likely as + * they tend to be scattered in generic code. + */ + .ifb \_no_isb + isb + .endif + _workaround_end \_cpu, \_id +.endm + +/******************************************************************************* + * Errata workaround helpers + ******************************************************************************/ +/* + * Set a bit in a system register. Can set multiple bits but is limited by the + * way the ORR instruction encodes them. + * + * _reg: + * Register to write to + * + * _bit: + * Bit to set. Please use a descriptive #define + * + * _assert: + * Optionally whether to read back and assert that the bit has been + * written. Please disable with NO_ASSERT macro + * + * clobbers: x1 + */ +.macro sysreg_bit_set _reg:req, _bit:req, _assert=1 + mrs x1, \_reg + orr x1, x1, #\_bit + msr \_reg, x1 +.endm + +/* + * Clear a bit in a system register. Can clear multiple bits but is limited by + * the way the BIC instrucion encodes them. + * + * see sysreg_bit_set for usage + */ +.macro sysreg_bit_clear _reg:req, _bit:req + mrs x1, \_reg + bic x1, x1, #\_bit + msr \_reg, x1 +.endm + +.macro override_vector_table _table:req + adr x1, \_table + msr vbar_el3, x1 +.endm + +/* + * BFI : Inserts bitfield into a system register. + * + * BFI{cond} Rd, Rn, #lsb, #width + */ +.macro sysreg_bitfield_insert _reg:req, _src:req, _lsb:req, _width:req + /* Source value for BFI */ + mov x1, #\_src + mrs x0, \_reg + bfi x0, x1, #\_lsb, #\_width + msr \_reg, x0 +.endm + +/* + * Apply erratum + * + * _cpu: + * Name of cpu as given to declare_cpu_ops + * + * _cve: + * Whether erratum is a CVE. CVE year if yes, 0 otherwise + * + * _id: + * Erratum or CVE number. Please combine with previous field with ERRATUM + * or CVE macros + * + * _chosen: + * Compile time flag on whether the erratum is included + * + * _get_rev: + * Optional parameter that determines whether to insert a call to the CPU revision fetching + * procedure. Stores the result of this in the temporary register x10. + * + * clobbers: x0-x10 (PCS compliant) + */ +.macro apply_erratum _cpu:req, _cve:req, _id:req, _chosen:req, _get_rev=GET_CPU_REV + .if (\_chosen & \_get_rev) + mov x9, x30 + bl cpu_get_rev_var + mov x10, x0 + .elseif (\_chosen) + mov x9, x30 + mov x0, x10 + .endif + + .if \_chosen + bl erratum_\_cpu\()_\_id\()_wa + mov x30, x9 + .endif +.endm + +/* + * Helpers to select which revisions errata apply to. Don't leave a link + * register as the cpu_rev_var_*** will call the ret and we can save on one. + * + * _cpu: + * Name of cpu as given to declare_cpu_ops + * + * _cve: + * Whether erratum is a CVE. CVE year if yes, 0 otherwise + * + * _id: + * Erratum or CVE number. Please combine with previous field with ERRATUM + * or CVE macros + * + * _rev_num: + * Revision to apply to + * + * in body: + * clobber: x0 to x4 + * argument: x0 - cpu_rev_var + */ +.macro check_erratum_ls _cpu:req, _cve:req, _id:req, _rev_num:req + func check_erratum_\_cpu\()_\_id + mov x1, #\_rev_num + b cpu_rev_var_ls + endfunc check_erratum_\_cpu\()_\_id +.endm + +.macro check_erratum_hs _cpu:req, _cve:req, _id:req, _rev_num:req + func check_erratum_\_cpu\()_\_id + mov x1, #\_rev_num + b cpu_rev_var_hs + endfunc check_erratum_\_cpu\()_\_id +.endm + +.macro check_erratum_range _cpu:req, _cve:req, _id:req, _rev_num_lo:req, _rev_num_hi:req + func check_erratum_\_cpu\()_\_id + mov x1, #\_rev_num_lo + mov x2, #\_rev_num_hi + b cpu_rev_var_range + endfunc check_erratum_\_cpu\()_\_id +.endm + +.macro check_erratum_chosen _cpu:req, _cve:req, _id:req, _chosen:req + func check_erratum_\_cpu\()_\_id + .if \_chosen + mov x0, #ERRATA_APPLIES + .else + mov x0, #ERRATA_MISSING + .endif + ret + endfunc check_erratum_\_cpu\()_\_id +.endm + +/* provide a shorthand for the name format for annoying errata */ +.macro check_erratum_custom_start _cpu:req, _cve:req, _id:req + func check_erratum_\_cpu\()_\_id +.endm + +.macro check_erratum_custom_end _cpu:req, _cve:req, _id:req + endfunc check_erratum_\_cpu\()_\_id +.endm + + +/******************************************************************************* + * CPU reset function wrapper + ******************************************************************************/ + +/* + * Wrapper to automatically apply all reset-time errata. Will end with an isb. + * + * _cpu: + * Name of cpu as given to declare_cpu_ops + * + * in body: + * clobber x8 to x14 + * argument x14 - cpu_rev_var + */ +.macro cpu_reset_func_start _cpu:req + func \_cpu\()_reset_func + mov x15, x30 + bl cpu_get_rev_var + mov x14, x0 + + /* short circuit the location to avoid searching the list */ + adrp x12, \_cpu\()_errata_list_start + add x12, x12, :lo12:\_cpu\()_errata_list_start + adrp x13, \_cpu\()_errata_list_end + add x13, x13, :lo12:\_cpu\()_errata_list_end + + errata_begin: + /* if head catches up with end of list, exit */ + cmp x12, x13 + b.eq errata_end + + ldr x10, [x12, #ERRATUM_WA_FUNC] + /* TODO(errata ABI): check mitigated and checker function fields + * for 0 */ + ldrb w11, [x12, #ERRATUM_CHOSEN] + + /* skip if not chosen */ + cbz x11, 1f + /* skip if runtime erratum */ + cbz x10, 1f + + /* put cpu revision in x0 and call workaround */ + mov x0, x14 + blr x10 + 1: + add x12, x12, #ERRATUM_ENTRY_SIZE + b errata_begin + errata_end: +.endm + +.macro cpu_reset_func_end _cpu:req + isb + ret x15 + endfunc \_cpu\()_reset_func +.endm + +/* + * Maintain compatibility with the old scheme of each cpu has its own reporting. + * TODO remove entirely once all cpus have been converted. This includes the + * cpu_ops entry, as print_errata_status can call this directly for all cpus + */ +.macro errata_report_shim _cpu:req + #if REPORT_ERRATA + func \_cpu\()_errata_report + /* normal stack frame for pretty debugging */ + stp x29, x30, [sp, #-16]! + mov x29, sp + + bl generic_errata_report + + ldp x29, x30, [sp], #16 + ret + endfunc \_cpu\()_errata_report + #endif +.endm +#endif /* CPU_MACROS_S */ diff --git a/include/lib/cpus/aarch64/cpuamu.h b/include/lib/cpus/aarch64/cpuamu.h new file mode 100644 index 0000000..cb004bf --- /dev/null +++ b/include/lib/cpus/aarch64/cpuamu.h @@ -0,0 +1,48 @@ +/* + * Copyright (c) 2018, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef CPUAMU_H +#define CPUAMU_H + +/******************************************************************************* + * CPU Activity Monitor Unit register specific definitions. + ******************************************************************************/ +#define CPUAMCNTENCLR_EL0 S3_3_C15_C9_7 +#define CPUAMCNTENSET_EL0 S3_3_C15_C9_6 +#define CPUAMCFGR_EL0 S3_3_C15_C10_6 +#define CPUAMUSERENR_EL0 S3_3_C15_C10_7 + +/* Activity Monitor Event Counter Registers */ +#define CPUAMEVCNTR0_EL0 S3_3_C15_C9_0 +#define CPUAMEVCNTR1_EL0 S3_3_C15_C9_1 +#define CPUAMEVCNTR2_EL0 S3_3_C15_C9_2 +#define CPUAMEVCNTR3_EL0 S3_3_C15_C9_3 +#define CPUAMEVCNTR4_EL0 S3_3_C15_C9_4 + +/* Activity Monitor Event Type Registers */ +#define CPUAMEVTYPER0_EL0 S3_3_C15_C10_0 +#define CPUAMEVTYPER1_EL0 S3_3_C15_C10_1 +#define CPUAMEVTYPER2_EL0 S3_3_C15_C10_2 +#define CPUAMEVTYPER3_EL0 S3_3_C15_C10_3 +#define CPUAMEVTYPER4_EL0 S3_3_C15_C10_4 + +#ifndef __ASSEMBLER__ +#include <stdint.h> + +uint64_t cpuamu_cnt_read(unsigned int idx); +void cpuamu_cnt_write(unsigned int idx, uint64_t val); +unsigned int cpuamu_read_cpuamcntenset_el0(void); +unsigned int cpuamu_read_cpuamcntenclr_el0(void); +void cpuamu_write_cpuamcntenset_el0(unsigned int mask); +void cpuamu_write_cpuamcntenclr_el0(unsigned int mask); + +int midr_match(unsigned int cpu_midr); +void cpuamu_context_save(unsigned int nr_counters); +void cpuamu_context_restore(unsigned int nr_counters); + +#endif /* __ASSEMBLER__ */ + +#endif /* CPUAMU_H */ diff --git a/include/lib/cpus/aarch64/denver.h b/include/lib/cpus/aarch64/denver.h new file mode 100644 index 0000000..84ab6bb --- /dev/null +++ b/include/lib/cpus/aarch64/denver.h @@ -0,0 +1,54 @@ +/* + * Copyright (c) 2015-2018, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef DENVER_H +#define DENVER_H + +/* MIDR values for Denver */ +#define DENVER_MIDR_PN0 U(0x4E0F0000) +#define DENVER_MIDR_PN1 U(0x4E0F0010) +#define DENVER_MIDR_PN2 U(0x4E0F0020) +#define DENVER_MIDR_PN3 U(0x4E0F0030) +#define DENVER_MIDR_PN4 U(0x4E0F0040) +#define DENVER_MIDR_PN5 U(0x4E0F0050) +#define DENVER_MIDR_PN6 U(0x4E0F0060) +#define DENVER_MIDR_PN7 U(0x4E0F0070) +#define DENVER_MIDR_PN8 U(0x4E0F0080) +#define DENVER_MIDR_PN9 U(0x4E0F0090) + +/* Implementer code in the MIDR register */ +#define DENVER_IMPL U(0x4E) + +/* CPU state ids - implementation defined */ +#define DENVER_CPU_STATE_POWER_DOWN U(0x3) + +/* Speculative store buffering */ +#define DENVER_CPU_DIS_SSB_EL3 (U(1) << 11) +#define DENVER_PN4_CPU_DIS_SSB_EL3 (U(1) << 18) + +/* Speculative memory disambiguation */ +#define DENVER_CPU_DIS_MD_EL3 (U(1) << 9) +#define DENVER_PN4_CPU_DIS_MD_EL3 (U(1) << 17) + +/* Core power management states */ +#define DENVER_CPU_PMSTATE_C1 U(0x1) +#define DENVER_CPU_PMSTATE_C6 U(0x6) +#define DENVER_CPU_PMSTATE_C7 U(0x7) +#define DENVER_CPU_PMSTATE_MASK U(0xF) + +/* ACTRL_ELx bits to enable dual execution*/ +#define DENVER_CPU_ENABLE_DUAL_EXEC_EL2 (ULL(1) << 9) +#define DENVER_CPU_ENABLE_DUAL_EXEC_EL3 (ULL(1) << 9) +#define DENVER_CPU_ENABLE_DUAL_EXEC_EL1 (U(1) << 4) + +#ifndef __ASSEMBLER__ + +/* Disable Dynamic Code Optimisation */ +void denver_disable_dco(void); + +#endif /* __ASSEMBLER__ */ + +#endif /* DENVER_H */ diff --git a/include/lib/cpus/aarch64/dsu_def.h b/include/lib/cpus/aarch64/dsu_def.h new file mode 100644 index 0000000..577de61 --- /dev/null +++ b/include/lib/cpus/aarch64/dsu_def.h @@ -0,0 +1,42 @@ +/* + * Copyright (c) 2018-2022, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef DSU_DEF_H +#define DSU_DEF_H + +#include <lib/utils_def.h> + +/******************************************************************** + * DSU Cluster Configuration registers definitions + ********************************************************************/ +#define CLUSTERCFR_EL1 S3_0_C15_C3_0 + +#define CLUSTERCFR_ACP_SHIFT U(11) + +/******************************************************************** + * DSU Cluster Main Revision ID registers definitions + ********************************************************************/ +#define CLUSTERIDR_EL1 S3_0_C15_C3_1 + +#define CLUSTERIDR_REV_SHIFT U(0) +#define CLUSTERIDR_REV_BITS U(4) +#define CLUSTERIDR_VAR_SHIFT U(4) +#define CLUSTERIDR_VAR_BITS U(4) + +/******************************************************************** + * DSU Cluster Auxiliary Control registers definitions + ********************************************************************/ +#define CLUSTERACTLR_EL1 S3_0_C15_C3_3 + +#define CLUSTERACTLR_EL1_DISABLE_CLOCK_GATING (ULL(1) << 15) +#define CLUSTERACTLR_EL1_DISABLE_SCLK_GATING (ULL(3) << 15) + +/******************************************************************** + * Masks applied for DSU errata workarounds + ********************************************************************/ +#define DSU_ERRATA_936184_MASK (U(0x3) << 15) + +#endif /* DSU_DEF_H */ diff --git a/include/lib/cpus/aarch64/generic.h b/include/lib/cpus/aarch64/generic.h new file mode 100644 index 0000000..dd71554 --- /dev/null +++ b/include/lib/cpus/aarch64/generic.h @@ -0,0 +1,18 @@ +/* + * Copyright (c) 2020, Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef AARCH64_GENERIC_H +#define AARCH64_GENERIC_H + +#include <lib/utils_def.h> + +/* + * 0x0 value on the MIDR implementer value is reserved for software use, + * so use an MIDR value of 0 for a default CPU library. + */ +#define AARCH64_GENERIC_MIDR U(0) + +#endif /* AARCH64_GENERIC_H */ diff --git a/include/lib/cpus/aarch64/neoverse_e1.h b/include/lib/cpus/aarch64/neoverse_e1.h new file mode 100644 index 0000000..6e784f6 --- /dev/null +++ b/include/lib/cpus/aarch64/neoverse_e1.h @@ -0,0 +1,31 @@ +/* + * Copyright (c) 2018-2019, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef NEOVERSE_E1_H +#define NEOVERSE_E1_H + +#include <lib/utils_def.h> + +#define NEOVERSE_E1_MIDR U(0x410FD4A0) + +/******************************************************************************* + * CPU Extended Control register specific definitions. + ******************************************************************************/ +#define NEOVERSE_E1_ECTLR_EL1 S3_0_C15_C1_4 + +/******************************************************************************* + * CPU Auxiliary Control register specific definitions. + ******************************************************************************/ +#define NEOVERSE_E1_CPUACTLR_EL1 S3_0_C15_C1_0 + +/******************************************************************************* + * CPU Power Control register specific definitions. + ******************************************************************************/ + +#define NEOVERSE_E1_CPUPWRCTLR_EL1 S3_0_C15_C2_7 +#define NEOVERSE_E1_CPUPWRCTLR_EL1_CORE_PWRDN_BIT (U(1) << 0) + +#endif /* NEOVERSE_E1_H */ diff --git a/include/lib/cpus/aarch64/neoverse_hermes.h b/include/lib/cpus/aarch64/neoverse_hermes.h new file mode 100644 index 0000000..22492c3 --- /dev/null +++ b/include/lib/cpus/aarch64/neoverse_hermes.h @@ -0,0 +1,23 @@ +/* + * Copyright (c) 2023, Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef NEOVERSE_HERMES_H +#define NEOVERSE_HERMES_H + +#define NEOVERSE_HERMES_MIDR U(0x410FD8E0) + +/******************************************************************************* + * CPU Extended Control register specific definitions + ******************************************************************************/ +#define NEOVERSE_HERMES_CPUECTLR_EL1 S3_0_C15_C1_4 + +/******************************************************************************* + * CPU Power Control register specific definitions + ******************************************************************************/ +#define NEOVERSE_HERMES_CPUPWRCTLR_EL1 S3_0_C15_C2_7 +#define NEOVERSE_HERMES_CPUPWRCTLR_EL1_CORE_PWRDN_BIT U(1) + +#endif /* NEOVERSE_HERMES_H */ diff --git a/include/lib/cpus/aarch64/neoverse_n1.h b/include/lib/cpus/aarch64/neoverse_n1.h new file mode 100644 index 0000000..0ba5ad1 --- /dev/null +++ b/include/lib/cpus/aarch64/neoverse_n1.h @@ -0,0 +1,70 @@ +/* + * Copyright (c) 2017-2022, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef NEOVERSE_N1_H +#define NEOVERSE_N1_H + +#include <lib/utils_def.h> + +/* Neoverse N1 MIDR for revision 0 */ +#define NEOVERSE_N1_MIDR U(0x410fd0c0) + +/* Neoverse N1 loop count for CVE-2022-23960 mitigation */ +#define NEOVERSE_N1_BHB_LOOP_COUNT U(24) + +/* Exception Syndrome register EC code for IC Trap */ +#define NEOVERSE_N1_EC_IC_TRAP U(0x1f) + +/******************************************************************************* + * CPU Power Control register specific definitions. + ******************************************************************************/ +#define NEOVERSE_N1_CPUPWRCTLR_EL1 S3_0_C15_C2_7 + +/* Definitions of register field mask in NEOVERSE_N1_CPUPWRCTLR_EL1 */ +#define NEOVERSE_N1_CORE_PWRDN_EN_MASK U(0x1) + +#define NEOVERSE_N1_ACTLR_AMEN_BIT (U(1) << 4) + +#define NEOVERSE_N1_AMU_NR_COUNTERS U(5) +#define NEOVERSE_N1_AMU_GROUP0_MASK U(0x1f) + +/******************************************************************************* + * CPU Extended Control register specific definitions. + ******************************************************************************/ +#define NEOVERSE_N1_CPUECTLR_EL1 S3_0_C15_C1_4 + +#define NEOVERSE_N1_WS_THR_L2_MASK (ULL(3) << 24) +#define NEOVERSE_N1_CPUECTLR_EL1_MM_TLBPF_DIS_BIT (ULL(1) << 51) +#define NEOVERSE_N1_CPUECTLR_EL1_EXTLLC_BIT (ULL(1) << 0) + +/******************************************************************************* + * CPU Auxiliary Control register specific definitions. + ******************************************************************************/ +#define NEOVERSE_N1_CPUACTLR_EL1 S3_0_C15_C1_0 + +#define NEOVERSE_N1_CPUACTLR_EL1_BIT_6 (ULL(1) << 6) +#define NEOVERSE_N1_CPUACTLR_EL1_BIT_13 (ULL(1) << 13) + +#define NEOVERSE_N1_CPUACTLR2_EL1 S3_0_C15_C1_1 + +#define NEOVERSE_N1_CPUACTLR2_EL1_BIT_0 (ULL(1) << 0) +#define NEOVERSE_N1_CPUACTLR2_EL1_BIT_2 (ULL(1) << 2) +#define NEOVERSE_N1_CPUACTLR2_EL1_BIT_11 (ULL(1) << 11) +#define NEOVERSE_N1_CPUACTLR2_EL1_BIT_15 (ULL(1) << 15) +#define NEOVERSE_N1_CPUACTLR2_EL1_BIT_16 (ULL(1) << 16) +#define NEOVERSE_N1_CPUACTLR2_EL1_BIT_59 (ULL(1) << 59) + +#define NEOVERSE_N1_CPUACTLR3_EL1 S3_0_C15_C1_2 + +#define NEOVERSE_N1_CPUACTLR3_EL1_BIT_10 (ULL(1) << 10) + +/* Instruction patching registers */ +#define CPUPSELR_EL3 S3_6_C15_C8_0 +#define CPUPCR_EL3 S3_6_C15_C8_1 +#define CPUPOR_EL3 S3_6_C15_C8_2 +#define CPUPMR_EL3 S3_6_C15_C8_3 + +#endif /* NEOVERSE_N1_H */ diff --git a/include/lib/cpus/aarch64/neoverse_n2.h b/include/lib/cpus/aarch64/neoverse_n2.h new file mode 100644 index 0000000..b379fab --- /dev/null +++ b/include/lib/cpus/aarch64/neoverse_n2.h @@ -0,0 +1,72 @@ +/* + * Copyright (c) 2020-2023, Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef NEOVERSE_N2_H +#define NEOVERSE_N2_H + +/* Neoverse N2 ID register for revision r0p0 */ +#define NEOVERSE_N2_MIDR U(0x410FD490) + +/* Neoverse N2 loop count for CVE-2022-23960 mitigation */ +#define NEOVERSE_N2_BHB_LOOP_COUNT U(32) + +/******************************************************************************* + * CPU Power control register + ******************************************************************************/ +#define NEOVERSE_N2_CPUPWRCTLR_EL1 S3_0_C15_C2_7 +#define NEOVERSE_N2_CORE_PWRDN_EN_BIT (ULL(1) << 0) + +/******************************************************************************* + * CPU Extended Control register specific definitions. + ******************************************************************************/ +#define NEOVERSE_N2_CPUECTLR_EL1 S3_0_C15_C1_4 +#define NEOVERSE_N2_CPUECTLR_EL1_EXTLLC_BIT (ULL(1) << 0) +#define NEOVERSE_N2_CPUECTLR_EL1_PFSTIDIS_BIT (ULL(1) << 8) + +/******************************************************************************* + * CPU Auxiliary Control register specific definitions. + ******************************************************************************/ +#define NEOVERSE_N2_CPUACTLR_EL1 S3_0_C15_C1_0 +#define NEOVERSE_N2_CPUACTLR_EL1_BIT_46 (ULL(1) << 46) +#define NEOVERSE_N2_CPUACTLR_EL1_BIT_22 (ULL(1) << 22) + +/******************************************************************************* + * CPU Auxiliary Control register 2 specific definitions. + ******************************************************************************/ +#define NEOVERSE_N2_CPUACTLR2_EL1 S3_0_C15_C1_1 +#define NEOVERSE_N2_CPUACTLR2_EL1_BIT_0 (ULL(1) << 0) +#define NEOVERSE_N2_CPUACTLR2_EL1_BIT_2 (ULL(1) << 2) +#define NEOVERSE_N2_CPUACTLR2_EL1_BIT_36 (ULL(1) << 36) +#define NEOVERSE_N2_CPUACTLR2_EL1_BIT_40 (ULL(1) << 40) + +/******************************************************************************* + * CPU Auxiliary Control register 3 specific definitions. + ******************************************************************************/ +#define NEOVERSE_N2_CPUACTLR3_EL1 S3_0_C15_C1_2 +#define NEOVERSE_N2_CPUACTLR3_EL1_BIT_47 (ULL(1) << 47) + +/******************************************************************************* + * CPU Auxiliary Control register 5 specific definitions. + ******************************************************************************/ +#define NEOVERSE_N2_CPUACTLR5_EL1 S3_0_C15_C8_0 +#define NEOVERSE_N2_CPUACTLR5_EL1_BIT_56 (ULL(1) << 56) +#define NEOVERSE_N2_CPUACTLR5_EL1_BIT_55 (ULL(1) << 55) +#define NEOVERSE_N2_CPUACTLR5_EL1_BIT_44 (ULL(1) << 44) +#define NEOVERSE_N2_CPUACTLR5_EL1_BIT_13 (ULL(1) << 13) +#define NEOVERSE_N2_CPUACTLR5_EL1_BIT_17 (ULL(1) << 17) + +/******************************************************************************* + * CPU Auxiliary Control register specific definitions. + ******************************************************************************/ +#define NEOVERSE_N2_CPUECTLR2_EL1 S3_0_C15_C1_5 +#define NEOVERSE_N2_CPUECTLR2_EL1_PF_MODE_CNSRV ULL(9) +#define CPUECTLR2_EL1_PF_MODE_LSB U(11) +#define CPUECTLR2_EL1_PF_MODE_WIDTH U(4) +#define CPUECTLR2_EL1_TXREQ_STATIC_FULL ULL(0) +#define CPUECTLR2_EL1_TXREQ_LSB U(0) +#define CPUECTLR2_EL1_TXREQ_WIDTH U(3) + +#endif /* NEOVERSE_N2_H */ diff --git a/include/lib/cpus/aarch64/neoverse_n_common.h b/include/lib/cpus/aarch64/neoverse_n_common.h new file mode 100644 index 0000000..7cb91cd --- /dev/null +++ b/include/lib/cpus/aarch64/neoverse_n_common.h @@ -0,0 +1,18 @@ +/* + * Copyright (c) 2020, Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef NEOVERSE_N_COMMON_H +#define NEOVERSE_N_COMMON_H + +/****************************************************************************** + * Neoverse Nx CPU Configuration register definitions + *****************************************************************************/ +#define CPUCFR_EL1 S3_0_C15_C0_0 + +/* SCU bit of CPU Configuration Register, EL1 */ +#define SCU_SHIFT U(2) + +#endif /* NEOVERSE_N_COMMON_H */ diff --git a/include/lib/cpus/aarch64/neoverse_poseidon.h b/include/lib/cpus/aarch64/neoverse_poseidon.h new file mode 100644 index 0000000..202ef5c --- /dev/null +++ b/include/lib/cpus/aarch64/neoverse_poseidon.h @@ -0,0 +1,27 @@ +/* + * Copyright (c) 2022, Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef NEOVERSE_POSEIDON_H +#define NEOVERSE_POSEIDON_H + + +#define NEOVERSE_POSEIDON_MIDR U(0x410FD830) + +/* Neoverse Poseidon loop count for CVE-2022-23960 mitigation */ +#define NEOVERSE_POSEIDON_BHB_LOOP_COUNT U(132) + +/******************************************************************************* + * CPU Extended Control register specific definitions. + ******************************************************************************/ +#define NEOVERSE_POSEIDON_CPUECTLR_EL1 S3_0_C15_C1_4 + +/******************************************************************************* + * CPU Power Control register specific definitions + ******************************************************************************/ +#define NEOVERSE_POSEIDON_CPUPWRCTLR_EL1 S3_0_C15_C2_7 +#define NEOVERSE_POSEIDON_CPUPWRCTLR_EL1_CORE_PWRDN_BIT U(1) + +#endif /* NEOVERSE_POSEIDON_H */ diff --git a/include/lib/cpus/aarch64/neoverse_v1.h b/include/lib/cpus/aarch64/neoverse_v1.h new file mode 100644 index 0000000..d618994 --- /dev/null +++ b/include/lib/cpus/aarch64/neoverse_v1.h @@ -0,0 +1,51 @@ +/* + * Copyright (c) 2019-2023, Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef NEOVERSE_V1_H +#define NEOVERSE_V1_H + +#define NEOVERSE_V1_MIDR U(0x410FD400) + +/* Neoverse V1 loop count for CVE-2022-23960 mitigation */ +#define NEOVERSE_V1_BHB_LOOP_COUNT U(32) + +/******************************************************************************* + * CPU Extended Control register specific definitions. + ******************************************************************************/ +#define NEOVERSE_V1_CPUECTLR_EL1 S3_0_C15_C1_4 +#define NEOVERSE_V1_CPUPSELR_EL3 S3_6_C15_C8_0 +#define NEOVERSE_V1_CPUPOR_EL3 S3_6_C15_C8_2 +#define NEOVERSE_V1_CPUPMR_EL3 S3_6_C15_C8_3 +#define NEOVERSE_V1_CPUPCR_EL3 S3_6_C15_C8_1 +#define NEOVERSE_V1_CPUECTLR_EL1_BIT_8 (ULL(1) << 8) +#define NEOVERSE_V1_CPUECTLR_EL1_BIT_53 (ULL(1) << 53) +#define NEOVERSE_V1_CPUECTLR_EL1_PF_MODE_CNSRV ULL(3) +#define CPUECTLR_EL1_PF_MODE_LSB U(6) +#define CPUECTLR_EL1_PF_MODE_WIDTH U(2) + +/******************************************************************************* + * CPU Power Control register specific definitions + ******************************************************************************/ +#define NEOVERSE_V1_CPUPWRCTLR_EL1 S3_0_C15_C2_7 +#define NEOVERSE_V1_CPUPWRCTLR_EL1_CORE_PWRDN_BIT U(1) + +/******************************************************************************* + * CPU Auxiliary Control register specific definitions. + ******************************************************************************/ +#define NEOVERSE_V1_ACTLR2_EL1 S3_0_C15_C1_1 +#define NEOVERSE_V1_ACTLR2_EL1_BIT_0 ULL(1) +#define NEOVERSE_V1_ACTLR2_EL1_BIT_2 (ULL(1) << 2) +#define NEOVERSE_V1_ACTLR2_EL1_BIT_28 (ULL(1) << 28) +#define NEOVERSE_V1_ACTLR2_EL1_BIT_40 (ULL(1) << 40) + +#define NEOVERSE_V1_ACTLR3_EL1 S3_0_C15_C1_2 +#define NEOVERSE_V1_ACTLR3_EL1_BIT_47 (ULL(1) << 47) + +#define NEOVERSE_V1_ACTLR5_EL1 S3_0_C15_C9_0 +#define NEOVERSE_V1_ACTLR5_EL1_BIT_55 (ULL(1) << 55) +#define NEOVERSE_V1_ACTLR5_EL1_BIT_56 (ULL(1) << 56) + +#endif /* NEOVERSE_V1_H */ diff --git a/include/lib/cpus/aarch64/neoverse_v2.h b/include/lib/cpus/aarch64/neoverse_v2.h new file mode 100644 index 0000000..68c1558 --- /dev/null +++ b/include/lib/cpus/aarch64/neoverse_v2.h @@ -0,0 +1,53 @@ +/* + * Copyright (c) 2021-2023, Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef NEOVERSE_V2_H +#define NEOVERSE_V2_H + +#define NEOVERSE_V2_MIDR U(0x410FD4F0) + +/* Neoverse V2 loop count for CVE-2022-23960 mitigation */ +#define NEOVERSE_V2_BHB_LOOP_COUNT U(132) + +/******************************************************************************* + * CPU Extended Control register specific definitions + ******************************************************************************/ +#define NEOVERSE_V2_CPUECTLR_EL1 S3_0_C15_C1_4 + +/******************************************************************************* + * CPU Power Control register specific definitions + ******************************************************************************/ +#define NEOVERSE_V2_CPUPWRCTLR_EL1 S3_0_C15_C2_7 +#define NEOVERSE_V2_CPUPWRCTLR_EL1_CORE_PWRDN_BIT U(1) + +/******************************************************************************* + * CPU Extended Control register 2 specific definitions. + ******************************************************************************/ +#define NEOVERSE_V2_CPUECTLR2_EL1 S3_0_C15_C1_5 +#define NEOVERSE_V2_CPUECTLR2_EL1_PF_MODE_CNSRV ULL(9) +#define NEOVERSE_V2_CPUECTLR2_EL1_PF_MODE_LSB U(11) +#define NEOVERSE_V2_CPUECTLR2_EL1_PF_MODE_WIDTH U(4) + +/******************************************************************************* + * CPU Auxiliary Control register 2 specific definitions. + ******************************************************************************/ +#define NEOVERSE_V2_CPUACTLR2_EL1 S3_0_C15_C1_1 +#define NEOVERSE_V2_CPUACTLR2_EL1_BIT_0 (ULL(1) << 0) + +/******************************************************************************* + * CPU Auxiliary Control register 3 specific definitions. + ******************************************************************************/ +#define NEOVERSE_V2_CPUACTLR3_EL1 S3_0_C15_C1_2 +#define NEOVERSE_V2_CPUACTLR3_EL1_BIT_47 (ULL(1) << 47) + +/******************************************************************************* + * CPU Auxiliary Control register 5 specific definitions. + ******************************************************************************/ +#define NEOVERSE_V2_CPUACTLR5_EL1 S3_0_C15_C8_0 +#define NEOVERSE_V2_CPUACTLR5_EL1_BIT_56 (ULL(1) << 56) +#define NEOVERSE_V2_CPUACTLR5_EL1_BIT_55 (ULL(1) << 55) + +#endif /* NEOVERSE_V2_H */ diff --git a/include/lib/cpus/aarch64/nevis.h b/include/lib/cpus/aarch64/nevis.h new file mode 100644 index 0000000..7006a29 --- /dev/null +++ b/include/lib/cpus/aarch64/nevis.h @@ -0,0 +1,23 @@ +/* + * Copyright (c) 2023, Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef NEVIS_H +#define NEVIS_H + +#define NEVIS_MIDR U(0x410FD8A0) + +/******************************************************************************* + * CPU Extended Control register specific definitions + ******************************************************************************/ +#define NEVIS_CPUECTLR_EL1 S3_0_C15_C1_4 + +/******************************************************************************* + * CPU Power Control register specific definitions + ******************************************************************************/ +#define NEVIS_IMP_CPUPWRCTLR_EL1 S3_0_C15_C2_7 +#define NEVIS_IMP_CPUPWRCTLR_EL1_CORE_PWRDN_EN_BIT U(1) + +#endif /* NEVIS_H */ diff --git a/include/lib/cpus/aarch64/qemu_max.h b/include/lib/cpus/aarch64/qemu_max.h new file mode 100644 index 0000000..58923d2 --- /dev/null +++ b/include/lib/cpus/aarch64/qemu_max.h @@ -0,0 +1,22 @@ +/* + * Copyright (c) 2014-2021, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef QEMU_MAX_H +#define QEMU_MAX_H + +#include <lib/utils_def.h> + +/* + * QEMU MAX midr for revision 0 + * 00 - Reserved for software use + * 0 - Variant + * F - Architectural features identified in ID_* registers + * 051 - 'Q', in a 12-bit field. + * 0 - Revision + */ +#define QEMU_MAX_MIDR U(0x000F0510) + +#endif /* QEMU_MAX_H */ diff --git a/include/lib/cpus/aarch64/rainier.h b/include/lib/cpus/aarch64/rainier.h new file mode 100644 index 0000000..978661f --- /dev/null +++ b/include/lib/cpus/aarch64/rainier.h @@ -0,0 +1,66 @@ +/* + * Copyright (c) 2020, Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef RAINIER_H +#define RAINIER_H + +#include <lib/utils_def.h> + +/* RAINIER MIDR for revision 0 */ +#define RAINIER_MIDR U(0x3f0f4120) + +/* Exception Syndrome register EC code for IC Trap */ +#define RAINIER_EC_IC_TRAP U(0x1f) + +/******************************************************************************* + * CPU Power Control register specific definitions. + ******************************************************************************/ +#define RAINIER_CPUPWRCTLR_EL1 S3_0_C15_C2_7 + +/* Definitions of register field mask in RAINIER_CPUPWRCTLR_EL1 */ +#define RAINIER_CORE_PWRDN_EN_MASK U(0x1) + +#define RAINIER_ACTLR_AMEN_BIT (U(1) << 4) + +#define RAINIER_AMU_NR_COUNTERS U(5) +#define RAINIER_AMU_GROUP0_MASK U(0x1f) + +/******************************************************************************* + * CPU Extended Control register specific definitions. + ******************************************************************************/ +#define RAINIER_CPUECTLR_EL1 S3_0_C15_C1_4 + +#define RAINIER_WS_THR_L2_MASK (ULL(3) << 24) +#define RAINIER_CPUECTLR_EL1_MM_TLBPF_DIS_BIT (ULL(1) << 51) + +/******************************************************************************* + * CPU Auxiliary Control register specific definitions. + ******************************************************************************/ +#define RAINIER_CPUACTLR_EL1 S3_0_C15_C1_0 + +#define RAINIER_CPUACTLR_EL1_BIT_6 (ULL(1) << 6) +#define RAINIER_CPUACTLR_EL1_BIT_13 (ULL(1) << 13) + +#define RAINIER_CPUACTLR2_EL1 S3_0_C15_C1_1 + +#define RAINIER_CPUACTLR2_EL1_BIT_0 (ULL(1) << 0) +#define RAINIER_CPUACTLR2_EL1_BIT_2 (ULL(1) << 2) +#define RAINIER_CPUACTLR2_EL1_BIT_11 (ULL(1) << 11) +#define RAINIER_CPUACTLR2_EL1_BIT_15 (ULL(1) << 15) +#define RAINIER_CPUACTLR2_EL1_BIT_16 (ULL(1) << 16) +#define RAINIER_CPUACTLR2_EL1_BIT_59 (ULL(1) << 59) + +#define RAINIER_CPUACTLR3_EL1 S3_0_C15_C1_2 + +#define RAINIER_CPUACTLR3_EL1_BIT_10 (ULL(1) << 10) + +/* Instruction patching registers */ +#define CPUPSELR_EL3 S3_6_C15_C8_0 +#define CPUPCR_EL3 S3_6_C15_C8_1 +#define CPUPOR_EL3 S3_6_C15_C8_2 +#define CPUPMR_EL3 S3_6_C15_C8_3 + +#endif /* RAINIER_H */ diff --git a/include/lib/cpus/aarch64/travis.h b/include/lib/cpus/aarch64/travis.h new file mode 100644 index 0000000..a8a2556 --- /dev/null +++ b/include/lib/cpus/aarch64/travis.h @@ -0,0 +1,29 @@ +/* + * Copyright (c) 2023, Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef TRAVIS_H +#define TRAVIS_H + +#define TRAVIS_MIDR U(0x410FD8C0) + +/******************************************************************************* + * CPU Extended Control register specific definitions + ******************************************************************************/ +#define TRAVIS_IMP_CPUECTLR_EL1 S3_0_C15_C1_4 + +/******************************************************************************* + * CPU Power Control register specific definitions + ******************************************************************************/ +#define TRAVIS_IMP_CPUPWRCTLR_EL1 S3_0_C15_C2_7 +#define TRAVIS_IMP_CPUPWRCTLR_EL1_CORE_PWRDN_EN_BIT U(1) + +/******************************************************************************* + * SME Control registers + ******************************************************************************/ +#define TRAVIS_SVCRSM S0_3_C4_C2_3 +#define TRAVIS_SVCRZA S0_3_C4_C4_3 + +#endif /* TRAVIS_H */ |