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author | Daniel Baumann <daniel.baumann@progress-linux.org> | 2024-04-21 17:43:51 +0000 |
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committer | Daniel Baumann <daniel.baumann@progress-linux.org> | 2024-04-21 17:43:51 +0000 |
commit | be58c81aff4cd4c0ccf43dbd7998da4a6a08c03b (patch) | |
tree | 779c248fb61c83f65d1f0dc867f2053d76b4e03a /plat/imx/imx8m/imx8m_csu.c | |
parent | Initial commit. (diff) | |
download | arm-trusted-firmware-upstream.tar.xz arm-trusted-firmware-upstream.zip |
Adding upstream version 2.10.0+dfsg.upstream/2.10.0+dfsgupstream
Signed-off-by: Daniel Baumann <daniel.baumann@progress-linux.org>
Diffstat (limited to '')
-rw-r--r-- | plat/imx/imx8m/imx8m_csu.c | 56 |
1 files changed, 56 insertions, 0 deletions
diff --git a/plat/imx/imx8m/imx8m_csu.c b/plat/imx/imx8m/imx8m_csu.c new file mode 100644 index 0000000..2b3a7d9 --- /dev/null +++ b/plat/imx/imx8m/imx8m_csu.c @@ -0,0 +1,56 @@ +/* + * Copyright 2020-2022 NXP + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include <lib/mmio.h> + +#include <imx8m_csu.h> + +void imx_csu_init(const struct imx_csu_cfg *csu_cfg) +{ + const struct imx_csu_cfg *csu = csu_cfg; + uint32_t val; + + while (csu->type != CSU_INVALID) { + switch (csu->type) { + case CSU_CSL: + val = mmio_read_32(CSLx_REG(csu->idx)); + if (val & CSLx_LOCK(csu->idx)) { + break; + } + mmio_clrsetbits_32(CSLx_REG(csu->idx), CSLx_CFG(0xff, csu->idx), + CSLx_CFG(csu->csl_level | (csu->lock << 8), csu->idx)); + break; + case CSU_HP: + val = mmio_read_32(CSU_HP_REG(csu->idx)); + if (val & CSU_HP_LOCK(csu->idx)) { + break; + } + mmio_clrsetbits_32(CSU_HP_REG(csu->idx), CSU_HP_CFG(0x1, csu->idx), + CSU_HP_CFG(csu->hp | (csu->lock << 0x1), csu->idx)); + break; + case CSU_SA: + val = mmio_read_32(CSU_SA_REG(csu->idx)); + if (val & CSU_SA_LOCK(csu->idx)) { + break; + } + mmio_clrsetbits_32(CSU_SA_REG(csu->idx), CSU_SA_CFG(0x1, csu->idx), + CSU_SA_CFG(csu->sa | (csu->lock << 0x1), csu->idx)); + break; + case CSU_HPCONTROL: + val = mmio_read_32(CSU_HPCONTROL_REG(csu->idx)); + if (val & CSU_HPCONTROL_LOCK(csu->idx)) { + break; + } + mmio_clrsetbits_32(CSU_HPCONTROL_REG(csu->idx), CSU_HPCONTROL_CFG(0x1, csu->idx), + CSU_HPCONTROL_CFG(csu->hpctrl | (csu->lock << 0x1), csu->idx)); + break; + default: + break; + } + + csu++; + } +} |