Adding upstream version 2.10.0+dfsg.upstream/2.10.0+dfsgupstream

Signed-off-by: Daniel Baumann <daniel.baumann@progress-linux.org>

5 files changed, 688 insertions, 0 deletions

diff --git a/plat/mediatek/drivers/gpio/mt8188/mtgpio.c b/plat/mediatek/drivers/gpio/mt8188/mtgpio.c
new file mode 100644
index 0000000..9e9fc5d
--- /dev/null
+++ b/plat/mediatek/drivers/gpio/mt8188/mtgpio.c
@@ -0,0 +1,38 @@
+/*
+ * Copyright (c) 2022, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <assert.h>
+#include <mtgpio.h>
+#include <platform_def.h>
+
+uintptr_t mt_gpio_find_reg_addr(uint32_t pin)
+{
+	uintptr_t reg_addr = 0U;
+	struct mt_pin_info gpio_info;
+
+	assert(pin < MAX_GPIO_PIN);
+
+	gpio_info = mt_pin_infos[pin];
+
+	switch (gpio_info.base & 0x0f) {
+	case 0:
+		reg_addr = IOCFG_RM_BASE;
+		break;
+	case 1:
+		reg_addr = IOCFG_LT_BASE;
+		break;
+	case 2:
+		reg_addr = IOCFG_LM_BASE;
+		break;
+	case 3:
+		reg_addr = IOCFG_RT_BASE;
+		break;
+	default:
+		break;
+	}
+
+	return reg_addr;
+}
diff --git a/plat/mediatek/drivers/gpio/mt8188/mtgpio.h b/plat/mediatek/drivers/gpio/mt8188/mtgpio.h
new file mode 100644
index 0000000..32a4608
--- /dev/null
+++ b/plat/mediatek/drivers/gpio/mt8188/mtgpio.h
@@ -0,0 +1,221 @@
+/*
+ * Copyright (c) 2022, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef MT_GPIO_H
+#define MT_GPIO_H
+
+#include <mtgpio_common.h>
+
+/* Enumeration for GPIO pin */
+typedef enum GPIO_PIN {
+	GPIO_UNSUPPORTED = -1,
+	GPIO0, GPIO1, GPIO2, GPIO3, GPIO4, GPIO5, GPIO6,
+	GPIO7, GPIO8, GPIO9, GPIO10, GPIO11, GPIO12, GPIO13, GPIO14,
+	GPIO15, GPIO16, GPIO17, GPIO18, GPIO19, GPIO20, GPIO21, GPIO22,
+	GPIO23, GPIO24, GPIO25, GPIO26, GPIO27, GPIO28, GPIO29, GPIO30,
+	GPIO31, GPIO32, GPIO33, GPIO34, GPIO35, GPIO36, GPIO37, GPIO38,
+	GPIO39, GPIO40, GPIO41, GPIO42, GPIO43, GPIO44, GPIO45, GPIO46,
+	GPIO47, GPIO48, GPIO49, GPIO50, GPIO51, GPIO52, GPIO53, GPIO54,
+	GPIO55, GPIO56, GPIO57, GPIO58, GPIO59, GPIO60, GPIO61, GPIO62,
+	GPIO63, GPIO64, GPIO65, GPIO66, GPIO67, GPIO68, GPIO69, GPIO70,
+	GPIO71, GPIO72, GPIO73, GPIO74, GPIO75, GPIO76, GPIO77, GPIO78,
+	GPIO79, GPIO80, GPIO81, GPIO82, GPIO83, GPIO84, GPIO85, GPIO86,
+	GPIO87, GPIO88, GPIO89, GPIO90, GPIO91, GPIO92, GPIO93, GPIO94,
+	GPIO95, GPIO96, GPIO97, GPIO98, GPIO99, GPIO100, GPIO101, GPIO102,
+	GPIO103, GPIO104, GPIO105, GPIO106, GPIO107, GPIO108, GPIO109, GPIO110,
+	GPIO111, GPIO112, GPIO113, GPIO114, GPIO115, GPIO116, GPIO117, GPIO118,
+	GPIO119, GPIO120, GPIO121, GPIO122, GPIO123, GPIO124, GPIO125, GPIO126,
+	GPIO127, GPIO128, GPIO129, GPIO130, GPIO131, GPIO132, GPIO133, GPIO134,
+	GPIO135, GPIO136, GPIO137, GPIO138, GPIO139, GPIO140, GPIO141, GPIO142,
+	GPIO143, GPIO144, GPIO145, GPIO146, GPIO147, GPIO148, GPIO149, GPIO150,
+	GPIO151, GPIO152, GPIO153, GPIO154, GPIO155, GPIO156, GPIO157, GPIO158,
+	GPIO159, GPIO160, GPIO161, GPIO162, GPIO163, GPIO164, GPIO165, GPIO166,
+	GPIO167, GPIO168, GPIO169, GPIO170, GPIO171, GPIO172, GPIO173, GPIO174,
+	GPIO175, GPIO176,
+	MT_GPIO_BASE_MAX
+} GPIO_PIN;
+
+static const struct mt_pin_info mt_pin_infos[] = {
+	PIN(0, 0, 6, 0x30, 0xb0),
+	PIN(1, 0, 7, 0x30, 0xb0),
+	PIN(2, 0, 8, 0x30, 0xb0),
+	PIN(3, 0, 9, 0x30, 0xb0),
+	PIN(4, 0, 10, 0x30, 0xb0),
+	PIN(5, 0, 11, 0x30, 0xb0),
+	PIN(6, 0, 12, 0x30, 0xb0),
+	PIN(7, 0, 13, 0x30, 0xb0),
+	PIN(8, 0, 14, 0x30, 0xb0),
+	PIN(9, 0, 15, 0x30, 0xb0),
+	PIN(10, 0, 16, 0x30, 0xb0),
+	PIN(11, 0, 17, 0x30, 0xb0),
+	PIN(12, 0, 12, 0x31, 0xa0),
+	PIN(13, 0, 13, 0x31, 0xa0),
+	PIN(14, 0, 14, 0x31, 0xa0),
+	PIN(15, 0, 15, 0x31, 0xa0),
+	PIN(16, 0, 1, 0x22, 0x50),
+	PIN(17, 0, 2, 0x22, 0x50),
+	PIN(18, 0, 3, 0x23, 0x60),
+	PIN(19, 0, 4, 0x23, 0x60),
+	PIN(20, 0, 5, 0x23, 0x60),
+	PIN(21, 0, 6, 0x23, 0x60),
+	PIN(22, 0, 0, 0x23, 0x60),
+	PIN(23, 0, 1, 0x23, 0x60),
+	PIN(24, 0, 2, 0x23, 0x60),
+	PIN(25, 0, 3, 0x30, 0xb0),
+	PIN(26, 0, 2, 0x30, 0xb0),
+	PIN(27, 0, 5, 0x30, 0xb0),
+	PIN(28, 0, 4, 0x30, 0xb0),
+	PIN(29, 0, 0, 0x30, 0xb0),
+	PIN(30, 0, 1, 0x30, 0xb0),
+	PIN(31, 0, 11, 0x30, 0xc0),
+	PIN(32, 0, 10, 0x30, 0xc0),
+	PIN(33, 0, 13, 0x30, 0xc0),
+	PIN(34, 0, 12, 0x30, 0xc0),
+	PIN(35, 0, 15, 0x30, 0xc0),
+	PIN(36, 0, 14, 0x30, 0xc0),
+	PIN(37, 0, 21, 0x30, 0xb0),
+	PIN(38, 0, 18, 0x30, 0xb0),
+	PIN(39, 0, 19, 0x30, 0xb0),
+	PIN(40, 0, 20, 0x30, 0xb0),
+	PIN(41, 0, 22, 0x30, 0xb0),
+	PIN(42, 1, 12, 0x31, 0xc0),
+	PIN(43, 1, 13, 0x31, 0xc0),
+	PIN(44, 1, 14, 0x31, 0xc0),
+	PIN(45, 1, 15, 0x31, 0xc0),
+	PIN(46, 0, 0, 0x22, 0x50),
+	PIN(47, 0, 25, 0x30, 0xb0),
+	PIN(48, 0, 24, 0x30, 0xb0),
+	PIN(49, 0, 23, 0x30, 0xb0),
+	PIN(50, 0, 5, 0x22, 0x50),
+	PIN(51, 0, 4, 0x22, 0x50),
+	PIN(52, 0, 3, 0x22, 0x50),
+	PIN(53, 0, 6, 0x22, 0x50),
+	PIN(54, 0, 7, 0x22, 0x50),
+	PIN(55, 0, 26, 0x30, 0xb0),
+	PIN(56, 0, 29, 0x30, 0xb0),
+	PIN(57, 0, 6, 0x31, 0xb0),
+	PIN(58, 0, 9, 0x31, 0xb0),
+	PIN(59, 0, 27, 0x30, 0xb0),
+	PIN(60, 0, 30, 0x30, 0xb0),
+	PIN(61, 0, 28, 0x30, 0xb0),
+	PIN(62, 0, 31, 0x30, 0xb0),
+	PIN(63, 0, 7, 0x31, 0xb0),
+	PIN(64, 0, 10, 0x31, 0xb0),
+	PIN(65, 0, 7, 0x23, 0x60),
+	PIN(66, 0, 9, 0x23, 0x60),
+	PIN(67, 0, 8, 0x23, 0x60),
+	PIN(68, 0, 10, 0x23, 0x60),
+	PIN(69, 0, 1, 0x30, 0xc0),
+	PIN(70, 0, 0, 0x30, 0xc0),
+	PIN(71, 0, 5, 0x30, 0xc0),
+	PIN(72, 0, 4, 0x30, 0xc0),
+	PIN(73, 0, 2, 0x30, 0xc0),
+	PIN(74, 0, 3, 0x30, 0xc0),
+	PIN(75, 0, 7, 0x30, 0xc0),
+	PIN(76, 0, 6, 0x30, 0xc0),
+	PIN(77, 0, 9, 0x30, 0xc0),
+	PIN(78, 0, 8, 0x30, 0xc0),
+	PIN(79, 0, 12, 0x23, 0x60),
+	PIN(80, 0, 11, 0x23, 0x60),
+	PIN(81, 0, 14, 0x23, 0x60),
+	PIN(82, 0, 13, 0x23, 0x60),
+	PIN(83, 0, 16, 0x31, 0xb0),
+	PIN(84, 0, 15, 0x31, 0xb0),
+	PIN(85, 0, 17, 0x31, 0xb0),
+	PIN(86, 0, 19, 0x31, 0xb0),
+	PIN(87, 0, 18, 0x31, 0xb0),
+	PIN(88, 0, 20, 0x31, 0xb0),
+	PIN(89, 0, 22, 0x31, 0xb0),
+	PIN(90, 0, 21, 0x31, 0xb0),
+	PIN(91, 0, 23, 0x31, 0xb0),
+	PIN(92, 0, 3, 0x31, 0xb0),
+	PIN(93, 0, 2, 0x31, 0xb0),
+	PIN(94, 0, 5, 0x31, 0xb0),
+	PIN(95, 0, 4, 0x31, 0xb0),
+	PIN(96, 0, 31, 0x31, 0xa0),
+	PIN(97, 0, 0, 0x31, 0xb0),
+	PIN(98, 0, 8, 0x31, 0xb0),
+	PIN(99, 0, 30, 0x31, 0xa0),
+	PIN(100, 0, 1, 0x31, 0xb0),
+	PIN(101, 0, 0, 0x31, 0xa0),
+	PIN(102, 0, 5, 0x31, 0xa0),
+	PIN(103, 0, 3, 0x31, 0xa0),
+	PIN(104, 0, 4, 0x31, 0xa0),
+	PIN(105, 0, 1, 0x31, 0xa0),
+	PIN(106, 0, 2, 0x31, 0xa0),
+	PIN(107, 0, 21, 0x31, 0xa0),
+	PIN(108, 0, 16, 0x31, 0xa0),
+	PIN(109, 0, 22, 0x31, 0xa0),
+	PIN(110, 0, 17, 0x31, 0xa0),
+	PIN(111, 0, 18, 0x31, 0xa0),
+	PIN(112, 0, 19, 0x31, 0xa0),
+	PIN(113, 0, 20, 0x31, 0xa0),
+	PIN(114, 0, 28, 0x31, 0xa0),
+	PIN(115, 0, 23, 0x31, 0xa0),
+	PIN(116, 0, 29, 0x31, 0xa0),
+	PIN(117, 0, 24, 0x31, 0xa0),
+	PIN(118, 0, 25, 0x31, 0xa0),
+	PIN(119, 0, 26, 0x31, 0xa0),
+	PIN(120, 0, 27, 0x31, 0xa0),
+	PIN(121, 0, 8, 0x22, 0x50),
+	PIN(122, 0, 11, 0x22, 0x50),
+	PIN(123, 0, 10, 0x22, 0x50),
+	PIN(124, 0, 9, 0x22, 0x50),
+	PIN(125, 0, 6, 0x31, 0xa0),
+	PIN(126, 0, 7, 0x31, 0xa0),
+	PIN(127, 0, 8, 0x31, 0xa0),
+	PIN(128, 0, 9, 0x31, 0xa0),
+	PIN(129, 0, 10, 0x31, 0xa0),
+	PIN(130, 0, 11, 0x31, 0xa0),
+	PIN(131, 1, 1, 0x30, 0xd0),
+	PIN(132, 1, 2, 0x30, 0xd0),
+	PIN(133, 1, 9, 0x30, 0xd0),
+	PIN(134, 1, 10, 0x30, 0xd0),
+	PIN(135, 1, 11, 0x30, 0xd0),
+	PIN(136, 1, 12, 0x30, 0xd0),
+	PIN(137, 1, 13, 0x30, 0xd0),
+	PIN(138, 1, 14, 0x30, 0xd0),
+	PIN(139, 1, 15, 0x30, 0xd0),
+	PIN(140, 1, 16, 0x30, 0xd0),
+	PIN(141, 1, 3, 0x30, 0xd0),
+	PIN(142, 1, 4, 0x30, 0xd0),
+	PIN(143, 1, 5, 0x30, 0xd0),
+	PIN(144, 1, 6, 0x30, 0xd0),
+	PIN(145, 1, 7, 0x30, 0xd0),
+	PIN(146, 1, 8, 0x30, 0xd0),
+	PIN(147, 1, 18, 0x30, 0xd0),
+	PIN(148, 1, 19, 0x30, 0xd0),
+	PIN(149, 1, 17, 0x30, 0xd0),
+	PIN(150, 1, 0, 0x30, 0xd0),
+	PIN(151, 1, 9, 0x31, 0xc0),
+	PIN(152, 1, 8, 0x31, 0xc0),
+	PIN(153, 1, 7, 0x31, 0xc0),
+	PIN(154, 1, 6, 0x31, 0xc0),
+	PIN(155, 1, 11, 0x31, 0xc0),
+	PIN(156, 1, 1, 0x31, 0xc0),
+	PIN(157, 1, 0, 0x31, 0xc0),
+	PIN(158, 1, 5, 0x31, 0xc0),
+	PIN(159, 1, 4, 0x31, 0xc0),
+	PIN(160, 1, 3, 0x31, 0xc0),
+	PIN(161, 1, 2, 0x31, 0xc0),
+	PIN(162, 1, 10, 0x31, 0xc0),
+	PIN(163, 1, 1, 0x23, 0x70),
+	PIN(164, 1, 0, 0x23, 0x70),
+	PIN(165, 1, 2, 0x23, 0x70),
+	PIN(166, 1, 3, 0x23, 0x70),
+	PIN(167, 1, 4, 0x23, 0x70),
+	PIN(168, 1, 5, 0x23, 0x70),
+	PIN(169, 1, 1, 0x22, 0x60),
+	PIN(170, 1, 0, 0x22, 0x60),
+	PIN(171, 1, 2, 0x22, 0x60),
+	PIN(172, 1, 3, 0x22, 0x60),
+	PIN(173, 1, 4, 0x22, 0x60),
+	PIN(174, 1, 5, 0x22, 0x60),
+	PIN(175, 0, 11, 0x31, 0xb0),
+	PIN(176, 0, 12, 0x31, 0xb0),
+};
+
+#endif /* MT_GPIO_H */
diff --git a/plat/mediatek/drivers/gpio/mtgpio_common.c b/plat/mediatek/drivers/gpio/mtgpio_common.c
new file mode 100644
index 0000000..bad0190
--- /dev/null
+++ b/plat/mediatek/drivers/gpio/mtgpio_common.c
@@ -0,0 +1,302 @@
+/*
+ * Copyright (c) 2020-2022, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <assert.h>
+#include <common/debug.h>
+#include <drivers/delay_timer.h>
+#include <drivers/gpio.h>
+#include <lib/mmio.h>
+#include <lib/mtk_init/mtk_init.h>
+#include <mtgpio.h>
+#include <platform_def.h>
+
+/******************************************************************************
+ *Macro Definition
+ ******************************************************************************/
+#define GPIO_MODE_BITS		4
+#define MAX_GPIO_MODE_PER_REG	8
+#define MAX_GPIO_REG_BITS	32
+#define DIR_BASE		(GPIO_BASE + 0x000)
+#define DOUT_BASE		(GPIO_BASE + 0x100)
+#define DIN_BASE		(GPIO_BASE + 0x200)
+#define MODE_BASE		(GPIO_BASE + 0x300)
+#define SET			0x4
+#define CLR			0x8
+
+static void mt_set_gpio_dir_chip(uint32_t pin, int dir)
+{
+	uint32_t pos, bit;
+
+	assert(pin < MAX_GPIO_PIN);
+	assert(dir < MT_GPIO_DIR_MAX);
+
+	pos = pin / MAX_GPIO_REG_BITS;
+	bit = pin % MAX_GPIO_REG_BITS;
+
+	if (dir == MT_GPIO_DIR_IN) {
+		mmio_write_32(DIR_BASE + 0x10U * pos + CLR, 1U << bit);
+	} else {
+		mmio_write_32(DIR_BASE + 0x10U * pos + SET, 1U << bit);
+	}
+}
+
+static int mt_get_gpio_dir_chip(uint32_t pin)
+{
+	uint32_t pos, bit;
+	uint32_t reg;
+
+	assert(pin < MAX_GPIO_PIN);
+
+	pos = pin / MAX_GPIO_REG_BITS;
+	bit = pin % MAX_GPIO_REG_BITS;
+
+	reg = mmio_read_32(DIR_BASE + 0x10U * pos);
+	return (((reg & (1U << bit)) != 0U) ? MT_GPIO_DIR_OUT : MT_GPIO_DIR_IN);
+}
+
+static void mt_set_gpio_out_chip(uint32_t pin, int output)
+{
+	uint32_t pos, bit;
+
+	assert(pin < MAX_GPIO_PIN);
+	assert(output < MT_GPIO_OUT_MAX);
+
+	pos = pin / MAX_GPIO_REG_BITS;
+	bit = pin % MAX_GPIO_REG_BITS;
+
+	if (output == MT_GPIO_OUT_ZERO) {
+		mmio_write_32(DOUT_BASE + 0x10U * pos + CLR, 1U << bit);
+	} else {
+		mmio_write_32(DOUT_BASE + 0x10U * pos + SET, 1U << bit);
+	}
+}
+
+static int mt_get_gpio_in_chip(uint32_t pin)
+{
+	uint32_t pos, bit;
+	uint32_t reg;
+
+	assert(pin < MAX_GPIO_PIN);
+
+	pos = pin / MAX_GPIO_REG_BITS;
+	bit = pin % MAX_GPIO_REG_BITS;
+
+	reg = mmio_read_32(DIN_BASE + 0x10U * pos);
+	return (((reg & (1U << bit)) != 0U) ? 1 : 0);
+}
+
+static void mt_gpio_set_spec_pull_pupd(uint32_t pin, int enable,
+			       int select)
+{
+	uintptr_t reg1;
+	uintptr_t reg2;
+	struct mt_pin_info gpio_info;
+
+	gpio_info = mt_pin_infos[pin];
+	uint32_t bit = gpio_info.bit;
+
+	reg1 = mt_gpio_find_reg_addr(pin) + gpio_info.offset;
+	reg2 = reg1 + (gpio_info.base & 0xf0);
+	if (enable == MT_GPIO_PULL_ENABLE) {
+		mmio_write_32(reg2 + SET, (1U << bit));
+		if (select == MT_GPIO_PULL_DOWN) {
+			mmio_write_32(reg1 + SET, (1U << bit));
+		} else {
+			mmio_write_32(reg1 + CLR, (1U << bit));
+		}
+	} else {
+		mmio_write_32(reg2 + CLR, (1U << bit));
+		mmio_write_32((reg2 + 0x010U) + CLR, (1U << bit));
+	}
+}
+
+static void mt_gpio_set_pull_pu_pd(uint32_t pin, int enable,
+				 int select)
+{
+	uintptr_t reg1;
+	uintptr_t reg2;
+	struct mt_pin_info gpio_info;
+
+	gpio_info = mt_pin_infos[pin];
+	uint32_t bit = gpio_info.bit;
+
+	reg1 = mt_gpio_find_reg_addr(pin) + gpio_info.offset;
+	reg2 = reg1 - (gpio_info.base & 0xf0);
+
+	if (enable == MT_GPIO_PULL_ENABLE) {
+		if (select == MT_GPIO_PULL_DOWN) {
+			mmio_write_32(reg1 + CLR, (1U << bit));
+			mmio_write_32(reg2 + SET, (1U << bit));
+		} else {
+			mmio_write_32(reg2 + CLR, (1U << bit));
+			mmio_write_32(reg1 + SET, (1U << bit));
+		}
+	} else {
+		mmio_write_32(reg1 + CLR, (1U << bit));
+		mmio_write_32(reg2 + CLR, (1U << bit));
+	}
+}
+
+static void mt_gpio_set_pull_chip(uint32_t pin, int enable,
+		   int select)
+{
+	struct mt_pin_info gpio_info;
+
+	gpio_info = mt_pin_infos[pin];
+	if (gpio_info.flag) {
+		mt_gpio_set_spec_pull_pupd(pin, enable, select);
+	} else {
+		mt_gpio_set_pull_pu_pd(pin, enable, select);
+	}
+}
+
+static int mt_gpio_get_spec_pull_pupd(uint32_t pin)
+{
+	uintptr_t reg1;
+	uintptr_t reg2;
+	uint32_t r0;
+	uint32_t r1;
+
+	struct mt_pin_info gpio_info;
+
+	gpio_info = mt_pin_infos[pin];
+	uint32_t bit = gpio_info.bit;
+
+	reg1 = mt_gpio_find_reg_addr(pin) + gpio_info.offset;
+	reg2 = reg1 + (gpio_info.base & 0xf0);
+
+	r0 = (mmio_read_32(reg2) >> bit) & 1U;
+	r1 = (mmio_read_32(reg2 + 0x010) >> bit) & 1U;
+	if (r0 == 0U && r1 == 0U) {
+		return MT_GPIO_PULL_NONE;
+	} else {
+		if (mmio_read_32(reg1) & (1U << bit)) {
+			return MT_GPIO_PULL_DOWN;
+		} else {
+			return MT_GPIO_PULL_UP;
+		}
+	}
+}
+
+static int mt_gpio_get_pull_pu_pd(uint32_t pin)
+{
+	uintptr_t reg1;
+	uintptr_t reg2;
+	uint32_t pu;
+	uint32_t pd;
+
+	struct mt_pin_info gpio_info;
+
+	gpio_info = mt_pin_infos[pin];
+	uint32_t bit = gpio_info.bit;
+
+	reg1 = mt_gpio_find_reg_addr(pin) + gpio_info.offset;
+	reg2 = reg1 - (gpio_info.base & 0xf0);
+	pu = (mmio_read_32(reg1) >> bit) & 1U;
+	pd = (mmio_read_32(reg2) >> bit) & 1U;
+	if (pu == 1U) {
+		return MT_GPIO_PULL_UP;
+	} else if (pd == 1U) {
+		return MT_GPIO_PULL_DOWN;
+	} else {
+		return MT_GPIO_PULL_NONE;
+	}
+}
+
+static int mt_gpio_get_pull_chip(uint32_t pin)
+{
+	struct mt_pin_info gpio_info;
+
+	gpio_info = mt_pin_infos[pin];
+	if (gpio_info.flag) {
+		return mt_gpio_get_spec_pull_pupd(pin);
+	} else {
+		return mt_gpio_get_pull_pu_pd(pin);
+	}
+}
+
+static void mt_set_gpio_pull_select_chip(uint32_t pin, int sel)
+{
+	assert(pin < MAX_GPIO_PIN);
+
+	if (sel == MT_GPIO_PULL_NONE) {
+		mt_gpio_set_pull_chip(pin, MT_GPIO_PULL_DISABLE, MT_GPIO_PULL_DOWN);
+	} else if (sel == MT_GPIO_PULL_UP) {
+		mt_gpio_set_pull_chip(pin, MT_GPIO_PULL_ENABLE, MT_GPIO_PULL_UP);
+	} else if (sel == MT_GPIO_PULL_DOWN) {
+		mt_gpio_set_pull_chip(pin, MT_GPIO_PULL_ENABLE, MT_GPIO_PULL_DOWN);
+	}
+}
+
+/* get pull-up or pull-down, regardless of resistor value */
+static int mt_get_gpio_pull_select_chip(uint32_t pin)
+{
+	assert(pin < MAX_GPIO_PIN);
+
+	return mt_gpio_get_pull_chip(pin);
+}
+
+static void mt_set_gpio_dir(int gpio, int direction)
+{
+	mt_set_gpio_dir_chip((uint32_t)gpio, direction);
+}
+
+static int mt_get_gpio_dir(int gpio)
+{
+	uint32_t pin;
+
+	pin = (uint32_t)gpio;
+	return mt_get_gpio_dir_chip(pin);
+}
+
+static void mt_set_gpio_pull(int gpio, int pull)
+{
+	uint32_t pin;
+
+	pin = (uint32_t)gpio;
+	mt_set_gpio_pull_select_chip(pin, pull);
+}
+
+static int mt_get_gpio_pull(int gpio)
+{
+	uint32_t pin;
+
+	pin = (uint32_t)gpio;
+	return mt_get_gpio_pull_select_chip(pin);
+}
+
+static void mt_set_gpio_out(int gpio, int value)
+{
+	uint32_t pin;
+
+	pin = (uint32_t)gpio;
+	mt_set_gpio_out_chip(pin, value);
+}
+
+static int mt_get_gpio_in(int gpio)
+{
+	uint32_t pin;
+
+	pin = (uint32_t)gpio;
+	return mt_get_gpio_in_chip(pin);
+}
+
+const gpio_ops_t mtgpio_ops = {
+	 .get_direction = mt_get_gpio_dir,
+	 .set_direction = mt_set_gpio_dir,
+	 .get_value = mt_get_gpio_in,
+	 .set_value = mt_set_gpio_out,
+	 .set_pull = mt_set_gpio_pull,
+	 .get_pull = mt_get_gpio_pull,
+};
+
+int mt_gpio_init(void)
+{
+	gpio_init(&mtgpio_ops);
+
+	return 0;
+}
+MTK_PLAT_SETUP_0_INIT(mt_gpio_init);
diff --git a/plat/mediatek/drivers/gpio/mtgpio_common.h b/plat/mediatek/drivers/gpio/mtgpio_common.h
new file mode 100644
index 0000000..d6b858c
--- /dev/null
+++ b/plat/mediatek/drivers/gpio/mtgpio_common.h
@@ -0,0 +1,109 @@
+/*
+ * Copyright (c) 2020-2022, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef MT_GPIO_COMMON_H
+#define MT_GPIO_COMMON_H
+
+#include <stdbool.h>
+#include <stdint.h>
+
+#include <plat/common/common_def.h>
+
+/*  Error Code No. */
+#define RSUCCESS        0
+#define ERACCESS        1
+#define ERINVAL         2
+#define ERWRAPPER       3
+#define MAX_GPIO_PIN    MT_GPIO_BASE_MAX
+
+/* GPIO MODE CONTROL VALUE*/
+typedef enum {
+	GPIO_MODE_UNSUPPORTED = -1,
+	GPIO_MODE_GPIO  = 0,
+	GPIO_MODE_00    = 0,
+	GPIO_MODE_01,
+	GPIO_MODE_02,
+	GPIO_MODE_03,
+	GPIO_MODE_04,
+	GPIO_MODE_05,
+	GPIO_MODE_06,
+	GPIO_MODE_07,
+
+	GPIO_MODE_MAX,
+	GPIO_MODE_DEFAULT = GPIO_MODE_00,
+} GPIO_MODE;
+
+/* GPIO DIRECTION */
+typedef enum {
+	MT_GPIO_DIR_UNSUPPORTED = -1,
+	MT_GPIO_DIR_OUT    = 0,
+	MT_GPIO_DIR_IN     = 1,
+	MT_GPIO_DIR_MAX,
+	MT_GPIO_DIR_DEFAULT = MT_GPIO_DIR_IN,
+} GPIO_DIR;
+
+/* GPIO PULL ENABLE*/
+typedef enum {
+	MT_GPIO_PULL_EN_UNSUPPORTED = -1,
+	MT_GPIO_PULL_DISABLE   = 0,
+	MT_GPIO_PULL_ENABLE    = 1,
+	MT_GPIO_PULL_ENABLE_R0 = 2,
+	MT_GPIO_PULL_ENABLE_R1 = 3,
+	MT_GPIO_PULL_ENABLE_R0R1 = 4,
+
+	MT_GPIO_PULL_EN_MAX,
+	MT_GPIO_PULL_EN_DEFAULT = MT_GPIO_PULL_ENABLE,
+} GPIO_PULL_EN;
+
+/* GPIO PULL-UP/PULL-DOWN*/
+typedef enum {
+	MT_GPIO_PULL_UNSUPPORTED = -1,
+	MT_GPIO_PULL_NONE        = 0,
+	MT_GPIO_PULL_UP          = 1,
+	MT_GPIO_PULL_DOWN        = 2,
+	MT_GPIO_PULL_MAX,
+	MT_GPIO_PULL_DEFAULT = MT_GPIO_PULL_DOWN
+} GPIO_PULL;
+
+/* GPIO OUTPUT */
+typedef enum {
+	MT_GPIO_OUT_UNSUPPORTED = -1,
+	MT_GPIO_OUT_ZERO = 0,
+	MT_GPIO_OUT_ONE  = 1,
+
+	MT_GPIO_OUT_MAX,
+	MT_GPIO_OUT_DEFAULT = MT_GPIO_OUT_ZERO,
+	MT_GPIO_DATA_OUT_DEFAULT = MT_GPIO_OUT_ZERO,  /*compatible with DCT*/
+} GPIO_OUT;
+
+/* GPIO INPUT */
+typedef enum {
+	MT_GPIO_IN_UNSUPPORTED = -1,
+	MT_GPIO_IN_ZERO = 0,
+	MT_GPIO_IN_ONE  = 1,
+
+	MT_GPIO_IN_MAX,
+} GPIO_IN;
+
+#define PIN(_id, _flag, _bit, _base, _offset) {		\
+		.id = _id,				\
+		.flag = _flag,				\
+		.bit = _bit,				\
+		.base = _base,				\
+		.offset = _offset,			\
+	}
+
+struct mt_pin_info {
+	uint8_t id;
+	uint8_t flag;
+	uint8_t bit;
+	uint16_t base;
+	uint16_t offset;
+};
+
+int mt_gpio_init(void);
+uintptr_t mt_gpio_find_reg_addr(uint32_t pin);
+#endif /* MT_GPIO_COMMON_H */
diff --git a/plat/mediatek/drivers/gpio/rules.mk b/plat/mediatek/drivers/gpio/rules.mk
new file mode 100644
index 0000000..78061a8
--- /dev/null
+++ b/plat/mediatek/drivers/gpio/rules.mk
@@ -0,0 +1,18 @@
+#
+# Copyright (c) 2022, MediaTek Inc. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+LOCAL_DIR := $(call GET_LOCAL_DIR)
+
+MODULE := gpio
+
+LOCAL_SRCS-y := drivers/gpio/gpio.c
+LOCAL_SRCS-y += ${LOCAL_DIR}/mtgpio_common.c
+LOCAL_SRCS-y += ${LOCAL_DIR}/${MTK_SOC}/mtgpio.c
+
+PLAT_INCLUDES += -I${LOCAL_DIR}
+PLAT_INCLUDES += -I${LOCAL_DIR}/${MTK_SOC}
+
+$(eval $(call MAKE_MODULE,$(MODULE),$(LOCAL_SRCS-y),$(MTK_BL)))