diff options
Diffstat (limited to 'plat/allwinner/common/include')
| -rw-r--r-- | plat/allwinner/common/include/mentor_i2c_plat.h | 28 | ||||
| -rw-r--r-- | plat/allwinner/common/include/plat_macros.S | 27 | ||||
| -rw-r--r-- | plat/allwinner/common/include/platform_def.h | 84 | ||||
| -rw-r--r-- | plat/allwinner/common/include/sunxi_cpucfg_ncat.h | 43 | ||||
| -rw-r--r-- | plat/allwinner/common/include/sunxi_cpucfg_ncat2.h | 36 | ||||
| -rw-r--r-- | plat/allwinner/common/include/sunxi_def.h | 27 | ||||
| -rw-r--r-- | plat/allwinner/common/include/sunxi_private.h | 61 |
7 files changed, 306 insertions, 0 deletions
diff --git a/plat/allwinner/common/include/mentor_i2c_plat.h b/plat/allwinner/common/include/mentor_i2c_plat.h new file mode 100644 index 0000000..d03f2d1 --- /dev/null +++ b/plat/allwinner/common/include/mentor_i2c_plat.h @@ -0,0 +1,28 @@ +/* + * Copyright (C) 2018 Icenowy Zheng <icenowy@aosc.io> + * + * SPDX-License-Identifier: BSD-3-Clause + * https://spdx.org/licenses + */ +/* This driver provides I2C support for Allwinner sunXi SoCs */ + +#ifndef MENTOR_I2C_PLAT_H +#define MENTOR_I2C_PLAT_H + +#define CONFIG_SYS_TCLK 24000000 +#define CONFIG_SYS_I2C_SPEED 100000 +#define CONFIG_SYS_I2C_SLAVE 0 + +#define I2C_INTERRUPT_CLEAR_INVERTED + +struct mentor_i2c_regs { + uint32_t slave_address; + uint32_t xtnd_slave_addr; + uint32_t data; + uint32_t control; + uint32_t status; + uint32_t baudrate; + uint32_t soft_reset; +}; + +#endif /* MENTOR_I2C_PLAT_H */ diff --git a/plat/allwinner/common/include/plat_macros.S b/plat/allwinner/common/include/plat_macros.S new file mode 100644 index 0000000..77f183d --- /dev/null +++ b/plat/allwinner/common/include/plat_macros.S @@ -0,0 +1,27 @@ +/* + * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef PLAT_MACROS_S +#define PLAT_MACROS_S + +#include <arm_macros.S> +#include <sunxi_mmap.h> + + /* --------------------------------------------- + * The below required platform porting macro + * prints out relevant GIC and CCI registers + * whenever an unhandled exception is taken in + * BL31. + * Clobbers: x0 - x10, x16, x17, sp + * --------------------------------------------- + */ + .macro plat_crash_print_regs + mov_imm x17, SUNXI_GICC_BASE + mov_imm x16, SUNXI_GICD_BASE + arm_print_gic_regs + .endm + +#endif /* PLAT_MACROS_S */ diff --git a/plat/allwinner/common/include/platform_def.h b/plat/allwinner/common/include/platform_def.h new file mode 100644 index 0000000..c9d075a --- /dev/null +++ b/plat/allwinner/common/include/platform_def.h @@ -0,0 +1,84 @@ +/* + * Copyright (c) 2017-2020, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef PLATFORM_DEF_H +#define PLATFORM_DEF_H + +#include <common/tbbr/tbbr_img_def.h> +#include <lib/utils_def.h> +#include <plat/common/common_def.h> + +#include <sunxi_mmap.h> + +#ifdef SUNXI_BL31_IN_DRAM + +#define BL31_BASE SUNXI_DRAM_BASE +#define BL31_LIMIT (SUNXI_DRAM_BASE + 0x40000) + +#define MAX_XLAT_TABLES 4 +#define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32) + +#define SUNXI_BL33_VIRT_BASE PRELOADED_BL33_BASE + +#else /* !SUNXI_BL31_IN_DRAM */ + +#define BL31_BASE (SUNXI_SRAM_A2_BASE + \ + SUNXI_SRAM_A2_BL31_OFFSET) +#define BL31_LIMIT (SUNXI_SRAM_A2_BASE + \ + SUNXI_SRAM_A2_SIZE - SUNXI_SCP_SIZE) + +/* Overwrite U-Boot SPL, but reserve the first page for the SPL header. */ +#define BL31_NOBITS_BASE (SUNXI_SRAM_A1_BASE + 0x1000) +#define BL31_NOBITS_LIMIT (SUNXI_SRAM_A1_BASE + SUNXI_SRAM_A1_SIZE) + +#define MAX_XLAT_TABLES 1 +#define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 28) + +#define SUNXI_BL33_VIRT_BASE SUNXI_DRAM_VIRT_BASE + +/* The SCP firmware is allocated the last 16KiB of SRAM A2. */ +#define SUNXI_SCP_BASE BL31_LIMIT +#define SUNXI_SCP_SIZE 0x4000 + +#endif /* SUNXI_BL31_IN_DRAM */ + +/* How much DRAM to map (to map BL33, for fetching the DTB from U-Boot) */ +#define SUNXI_DRAM_MAP_SIZE (64U << 20) + +#define CACHE_WRITEBACK_SHIFT 6 +#define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT) + +#define MAX_STATIC_MMAP_REGIONS 3 +#define MAX_MMAP_REGIONS (5 + MAX_STATIC_MMAP_REGIONS) + +#define PLAT_CSS_SCP_COM_SHARED_MEM_BASE \ + (SUNXI_SRAM_A2_BASE + SUNXI_SRAM_A2_SIZE - 0x200) + +/* These states are used directly for SCPI communication. */ +#define PLAT_MAX_PWR_LVL_STATES U(3) +#define PLAT_MAX_RET_STATE U(1) +#define PLAT_MAX_OFF_STATE U(3) + +#define PLAT_MAX_PWR_LVL U(2) +#define PLAT_NUM_PWR_DOMAINS (U(1) + \ + PLATFORM_CLUSTER_COUNT + \ + PLATFORM_CORE_COUNT) + +#define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32) + +#define PLATFORM_CLUSTER_COUNT U(1) +#define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER_COUNT * \ + PLATFORM_MAX_CPUS_PER_CLUSTER) +#define PLATFORM_MAX_CPUS_PER_CLUSTER U(4) +#define PLATFORM_STACK_SIZE (0x1000 / PLATFORM_CORE_COUNT) + +#ifndef SPD_none +#ifndef BL32_BASE +#define BL32_BASE SUNXI_DRAM_BASE +#endif +#endif + +#endif /* PLATFORM_DEF_H */ diff --git a/plat/allwinner/common/include/sunxi_cpucfg_ncat.h b/plat/allwinner/common/include/sunxi_cpucfg_ncat.h new file mode 100644 index 0000000..22828c2 --- /dev/null +++ b/plat/allwinner/common/include/sunxi_cpucfg_ncat.h @@ -0,0 +1,43 @@ +/* + * Copyright (c) 2017-2021, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef SUNXI_CPUCFG_H +#define SUNXI_CPUCFG_H + +#include <sunxi_mmap.h> + +/* c = cluster, n = core */ +#define SUNXI_CPUCFG_CLS_CTRL_REG0(c) (SUNXI_CPUCFG_BASE + 0x0010 + (c) * 0x10) +#define SUNXI_CPUCFG_CLS_CTRL_REG1(c) (SUNXI_CPUCFG_BASE + 0x0014 + (c) * 0x10) +#define SUNXI_CPUCFG_CACHE_CFG_REG (SUNXI_CPUCFG_BASE + 0x0024) +/* The T507 datasheet does not mention this register. */ +#define SUNXI_CPUCFG_DBG_REG0 (SUNXI_CPUCFG_BASE + 0x00c0) + +#define SUNXI_CPUCFG_RST_CTRL_REG(c) (SUNXI_CPUCFG_BASE + 0x0000 + (c) * 4) +#define SUNXI_CPUCFG_RVBAR_LO_REG(n) (SUNXI_CPUCFG_BASE + 0x0040 + (n) * 8) +#define SUNXI_CPUCFG_RVBAR_HI_REG(n) (SUNXI_CPUCFG_BASE + 0x0044 + (n) * 8) + +#define SUNXI_C0_CPU_CTRL_REG(n) (SUNXI_CPUCFG_BASE + 0x0060 + (n) * 4) + +#define SUNXI_CPU_CTRL_REG(n) (SUNXI_CPUSUBSYS_BASE + 0x20 + (n) * 4) +#define SUNXI_ALT_RVBAR_LO_REG(n) (SUNXI_CPUSUBSYS_BASE + 0x40 + (n) * 8) +#define SUNXI_ALT_RVBAR_HI_REG(n) (SUNXI_CPUSUBSYS_BASE + 0x44 + (n) * 8) + +#define SUNXI_POWERON_RST_REG(c) (SUNXI_R_CPUCFG_BASE + 0x0040 + (c) * 4) +#define SUNXI_POWEROFF_GATING_REG(c) (SUNXI_R_CPUCFG_BASE + 0x0044 + (c) * 4) +#define SUNXI_CPU_POWER_CLAMP_REG(c, n) (SUNXI_R_CPUCFG_BASE + 0x0050 + \ + (c) * 0x10 + (n) * 4) +#define SUNXI_CPU_UNK_REG(n) (SUNXI_R_CPUCFG_BASE + 0x0070 + (n) * 4) + +#define SUNXI_CPUIDLE_EN_REG (SUNXI_R_CPUCFG_BASE + 0x0100) +#define SUNXI_CORE_CLOSE_REG (SUNXI_R_CPUCFG_BASE + 0x0104) +#define SUNXI_PWR_SW_DELAY_REG (SUNXI_R_CPUCFG_BASE + 0x0140) +#define SUNXI_CONFIG_DELAY_REG (SUNXI_R_CPUCFG_BASE + 0x0144) + +#define SUNXI_AA64nAA32_REG SUNXI_CPUCFG_CLS_CTRL_REG0 +#define SUNXI_AA64nAA32_OFFSET 24 + +#endif /* SUNXI_CPUCFG_H */ diff --git a/plat/allwinner/common/include/sunxi_cpucfg_ncat2.h b/plat/allwinner/common/include/sunxi_cpucfg_ncat2.h new file mode 100644 index 0000000..d4aec19 --- /dev/null +++ b/plat/allwinner/common/include/sunxi_cpucfg_ncat2.h @@ -0,0 +1,36 @@ +/* + * Copyright (c) 2021 Sipeed + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef SUNXI_CPUCFG_H +#define SUNXI_CPUCFG_H + +#include <sunxi_mmap.h> + +/* c = cluster, n = core */ +#define SUNXI_CPUCFG_CLS_CTRL_REG0(c) (SUNXI_C0_CPUXCFG_BASE + 0x0010) +#define SUNXI_CPUCFG_CLS_CTRL_REG1(c) (SUNXI_C0_CPUXCFG_BASE + 0x0014) +#define SUNXI_CPUCFG_CACHE_CFG_REG (SUNXI_C0_CPUXCFG_BASE + 0x0024) +#define SUNXI_CPUCFG_DBG_REG0 (SUNXI_C0_CPUXCFG_BASE + 0x00c0) + +#define SUNXI_CPUCFG_RST_CTRL_REG(c) (SUNXI_C0_CPUXCFG_BASE + 0x0000) +#define SUNXI_CPUCFG_GEN_CTRL_REG0(c) (SUNXI_CPUCFG_BASE + 0x0000) +#define SUNXI_CPUCFG_RVBAR_LO_REG(n) (SUNXI_CPUCFG_BASE + 0x0040 + (n) * 8) +#define SUNXI_CPUCFG_RVBAR_HI_REG(n) (SUNXI_CPUCFG_BASE + 0x0044 + (n) * 8) + +#define SUNXI_POWERON_RST_REG(c) (SUNXI_R_CPUCFG_BASE + 0x0040 + (c) * 4) +#define SUNXI_POWEROFF_GATING_REG(c) (SUNXI_R_CPUCFG_BASE + 0x0044 + (c) * 4) +#define SUNXI_CPU_POWER_CLAMP_REG(c, n) (SUNXI_R_CPUCFG_BASE + 0x0050 + \ + (c) * 0x10 + (n) * 4) + +#define SUNXI_AA64nAA32_REG SUNXI_CPUCFG_GEN_CTRL_REG0 +#define SUNXI_AA64nAA32_OFFSET 4 + +static inline bool sunxi_cpucfg_has_per_cluster_regs(void) +{ + return true; +} + +#endif /* SUNXI_CPUCFG_H */ diff --git a/plat/allwinner/common/include/sunxi_def.h b/plat/allwinner/common/include/sunxi_def.h new file mode 100644 index 0000000..20f6c49 --- /dev/null +++ b/plat/allwinner/common/include/sunxi_def.h @@ -0,0 +1,27 @@ +/* + * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef SUNXI_DEF_H +#define SUNXI_DEF_H + +/* Clock configuration */ +#define SUNXI_OSC24M_CLK_IN_HZ 24000000 + +/* UART configuration */ +#define SUNXI_UART0_BAUDRATE 115200 +#define SUNXI_UART0_CLK_IN_HZ SUNXI_OSC24M_CLK_IN_HZ + +#define SUNXI_SOC_A64 0x1689 +#define SUNXI_SOC_H5 0x1718 +#define SUNXI_SOC_H6 0x1728 +#define SUNXI_SOC_H616 0x1823 +#define SUNXI_SOC_R329 0x1851 + +#define SUNXI_VER_BITS_MASK 0xffU +#define JEDEC_ALLWINNER_BKID 9U +#define JEDEC_ALLWINNER_MFID 0x9eU + +#endif /* SUNXI_DEF_H */ diff --git a/plat/allwinner/common/include/sunxi_private.h b/plat/allwinner/common/include/sunxi_private.h new file mode 100644 index 0000000..6a38657 --- /dev/null +++ b/plat/allwinner/common/include/sunxi_private.h @@ -0,0 +1,61 @@ +/* + * Copyright (c) 2017-2021, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef SUNXI_PRIVATE_H +#define SUNXI_PRIVATE_H + +#include <common/fdt_fixup.h> + +#include <lib/psci/psci.h> + +extern const struct psci_cpu_idle_state sunxi_idle_states[]; + +void sunxi_configure_mmu_el3(int flags); + +void sunxi_cpu_on(u_register_t mpidr); +void sunxi_cpu_power_off_others(void); +void sunxi_cpu_power_off_self(void); +void sunxi_power_down(void); + +#if SUNXI_PSCI_USE_NATIVE +void sunxi_set_native_psci_ops(const plat_psci_ops_t **psci_ops); +#else +static inline void sunxi_set_native_psci_ops(const plat_psci_ops_t **psci_ops) +{ +} +#endif +#if SUNXI_PSCI_USE_SCPI +bool sunxi_psci_is_scpi(void); +int sunxi_set_scpi_psci_ops(const plat_psci_ops_t **psci_ops); +#else +static inline bool sunxi_psci_is_scpi(void) +{ + return false; +} +static inline int sunxi_set_scpi_psci_ops(const plat_psci_ops_t **psci_ops) +{ + return -1; +} +#endif +int sunxi_validate_ns_entrypoint(uintptr_t ns_entrypoint); + +int sunxi_pmic_setup(uint16_t socid, const void *fdt); +void sunxi_security_setup(void); + +uint16_t sunxi_read_soc_id(void); +void sunxi_set_gpio_out(char port, int pin, bool level_high); +int sunxi_init_platform_r_twi(uint16_t socid, bool use_rsb); +void sunxi_execute_arisc_code(uint32_t *code, size_t size, uint16_t param); + +#if SUNXI_AMEND_DTB +void sunxi_prepare_dtb(void *fdt); +#else +static inline void sunxi_prepare_dtb(void *fdt) +{ +} +#endif + +#endif /* SUNXI_PRIVATE_H */ |