diff options
Diffstat (limited to 'plat/mediatek/mt8183/include')
| -rw-r--r-- | plat/mediatek/mt8183/include/mcucfg.h | 568 | ||||
| -rw-r--r-- | plat/mediatek/mt8183/include/mt_gic_v3.h | 34 | ||||
| -rw-r--r-- | plat/mediatek/mt8183/include/plat_dcm.h | 53 | ||||
| -rw-r--r-- | plat/mediatek/mt8183/include/plat_debug.h | 34 | ||||
| -rw-r--r-- | plat/mediatek/mt8183/include/plat_macros.S | 78 | ||||
| -rw-r--r-- | plat/mediatek/mt8183/include/plat_private.h | 28 | ||||
| -rw-r--r-- | plat/mediatek/mt8183/include/platform_def.h | 321 | ||||
| -rw-r--r-- | plat/mediatek/mt8183/include/power_tracer.h | 20 | ||||
| -rw-r--r-- | plat/mediatek/mt8183/include/scu.h | 13 | ||||
| -rw-r--r-- | plat/mediatek/mt8183/include/sspm_reg.h | 41 |
10 files changed, 1190 insertions, 0 deletions
diff --git a/plat/mediatek/mt8183/include/mcucfg.h b/plat/mediatek/mt8183/include/mcucfg.h new file mode 100644 index 0000000..6b03818 --- /dev/null +++ b/plat/mediatek/mt8183/include/mcucfg.h @@ -0,0 +1,568 @@ +/* + * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef MT8183_MCUCFG_H +#define MT8183_MCUCFG_H + +#include <platform_def.h> +#include <stdint.h> + +struct mt8183_mcucfg_regs { + uint32_t mp0_ca7l_cache_config; /* 0x0 */ + struct { + uint32_t mem_delsel0; + uint32_t mem_delsel1; + } mp0_cpu[4]; /* 0x4 */ + uint32_t mp0_cache_mem_delsel0; /* 0x24 */ + uint32_t mp0_cache_mem_delsel1; /* 0x28 */ + uint32_t mp0_axi_config; /* 0x2C */ + uint32_t mp0_misc_config[10]; /* 0x30 */ + uint32_t mp0_ca7l_cfg_dis; /* 0x58 */ + uint32_t mp0_ca7l_clken_ctrl; /* 0x5C */ + uint32_t mp0_ca7l_rst_ctrl; /* 0x60 */ + uint32_t mp0_ca7l_misc_config; /* 0x64 */ + uint32_t mp0_ca7l_dbg_pwr_ctrl; /* 0x68 */ + uint32_t mp0_rw_rsvd0; /* 0x6C */ + uint32_t mp0_rw_rsvd1; /* 0x70 */ + uint32_t mp0_ro_rsvd; /* 0x74 */ + uint32_t reserved0_0; /* 0x78 */ + uint32_t mp0_l2_cache_parity1_rdata; /* 0x7C */ + uint32_t mp0_l2_cache_parity2_rdata; /* 0x80 */ + uint32_t reserved0_1; /* 0x84 */ + uint32_t mp0_rgu_dcm_config; /* 0x88 */ + uint32_t mp0_ca53_specific_ctrl; /* 0x8C */ + uint32_t mp0_esr_case; /* 0x90 */ + uint32_t mp0_esr_mask; /* 0x94 */ + uint32_t mp0_esr_trig_en; /* 0x98 */ + uint32_t reserved_0_2; /* 0x9C */ + uint32_t mp0_ses_cg_en; /* 0xA0 */ + uint32_t reserved0_3[216]; /* 0xA4 */ + uint32_t mp_dbg_ctrl; /* 0x404 */ + uint32_t reserved0_4[34]; /* 0x408 */ + uint32_t mp_dfd_ctrl; /* 0x490 */ + uint32_t dfd_cnt_l; /* 0x494 */ + uint32_t dfd_cnt_h; /* 0x498 */ + uint32_t misccfg_ro_rsvd; /* 0x49C */ + uint32_t reserved0_5[24]; /* 0x4A0 */ + uint32_t mp1_rst_status; /* 0x500 */ + uint32_t mp1_dbg_ctrl; /* 0x504 */ + uint32_t mp1_dbg_flag; /* 0x508 */ + uint32_t mp1_ca7l_ir_mon; /* 0x50C */ + uint32_t reserved0_6[32]; /* 0x510 */ + uint32_t mcusys_dbg_mon_sel_a; /* 0x590 */ + uint32_t mcucys_dbg_mon; /* 0x594 */ + uint32_t misccfg_sec_voi_status0; /* 0x598 */ + uint32_t misccfg_sec_vio_status1; /* 0x59C */ + uint32_t reserved0_7[18]; /* 0x5A0 */ + uint32_t gic500_int_mask; /* 0x5E8 */ + uint32_t core_rst_en_latch; /* 0x5EC */ + uint32_t reserved0_8[3]; /* 0x5F0 */ + uint32_t dbg_core_ret; /* 0x5FC */ + uint32_t mcusys_config_a; /* 0x600 */ + uint32_t mcusys_config1_a; /* 0x604 */ + uint32_t mcusys_gic_prebase_a; /* 0x608 */ + uint32_t mcusys_pinmux; /* 0x60C */ + uint32_t sec_range0_start; /* 0x610 */ + uint32_t sec_range0_end; /* 0x614 */ + uint32_t sec_range_enable; /* 0x618 */ + uint32_t l2c_mm_base; /* 0x61C */ + uint32_t reserved0_9[8]; /* 0x620 */ + uint32_t aclken_div; /* 0x640 */ + uint32_t pclken_div; /* 0x644 */ + uint32_t l2c_sram_ctrl; /* 0x648 */ + uint32_t armpll_jit_ctrl; /* 0x64C */ + uint32_t cci_addrmap; /* 0x650 */ + uint32_t cci_config; /* 0x654 */ + uint32_t cci_periphbase; /* 0x658 */ + uint32_t cci_nevntcntovfl; /* 0x65C */ + uint32_t cci_clk_ctrl; /* 0x660 */ + uint32_t cci_acel_s1_ctrl; /* 0x664 */ + uint32_t mcusys_bus_fabric_dcm_ctrl; /* 0x668 */ + uint32_t mcu_misc_dcm_ctrl; /* 0x66C */ + uint32_t xgpt_ctl; /* 0x670 */ + uint32_t xgpt_idx; /* 0x674 */ + uint32_t reserved0_10[3]; /* 0x678 */ + uint32_t mcusys_rw_rsvd0; /* 0x684 */ + uint32_t mcusys_rw_rsvd1; /* 0x688 */ + uint32_t reserved0_11[13]; /* 0x68C */ + uint32_t gic_500_delsel_ctl; /* 0x6C0 */ + uint32_t etb_delsel_ctl; /* 0x6C4 */ + uint32_t etb_rst_ctl; /* 0x6C8 */ + uint32_t reserved0_12[29]; /* 0x6CC */ + uint32_t cci_adb400_dcm_config; /* 0x740 */ + uint32_t sync_dcm_config; /* 0x744 */ + uint32_t reserved0_13; /* 0x748 */ + uint32_t sync_dcm_cluster_config; /* 0x74C */ + uint32_t sw_udi; /* 0x750 */ + uint32_t reserved0_14; /* 0x754 */ + uint32_t gic_sync_dcm; /* 0x758 */ + uint32_t big_dbg_pwr_ctrl; /* 0x75C */ + uint32_t gic_cpu_periphbase; /* 0x760 */ + uint32_t axi_cpu_config; /* 0x764 */ + uint32_t reserved0_15[2]; /* 0x768 */ + uint32_t mcsib_sys_ctrl1; /* 0x770 */ + uint32_t mcsib_sys_ctrl2; /* 0x774 */ + uint32_t mcsib_sys_ctrl3; /* 0x778 */ + uint32_t mcsib_sys_ctrl4; /* 0x77C */ + uint32_t mcsib_dbg_ctrl1; /* 0x780 */ + uint32_t pwrmcu_apb2to1; /* 0x784 */ + uint32_t mp0_spmc; /* 0x788 */ + uint32_t reserved0_16; /* 0x78C */ + uint32_t mp0_spmc_sram_ctl; /* 0x790 */ + uint32_t reserved0_17; /* 0x794 */ + uint32_t mp0_sw_rst_wait_cycle; /* 0x798 */ + uint32_t reserved0_18; /* 0x79C */ + uint32_t mp0_pll_divider_cfg; /* 0x7A0 */ + uint32_t reserved0_19; /* 0x7A4 */ + uint32_t mp2_pll_divider_cfg; /* 0x7A8 */ + uint32_t reserved0_20[5]; /* 0x7AC */ + uint32_t bus_pll_divider_cfg; /* 0x7C0 */ + uint32_t reserved0_21[7]; /* 0x7C4 */ + uint32_t clusterid_aff1; /* 0x7E0 */ + uint32_t clusterid_aff2; /* 0x7E4 */ + uint32_t reserved0_22[2]; /* 0x7E8 */ + uint32_t l2_cfg_mp0; /* 0x7F0 */ + uint32_t l2_cfg_mp1; /* 0x7F4 */ + uint32_t reserved0_23[218]; /* 0x7F8 */ + uint32_t mscib_dcm_en; /* 0xB60 */ + uint32_t reserved0_24[1063]; /* 0xB64 */ + uint32_t cpusys0_sparkvretcntrl; /* 0x1C00 */ + uint32_t cpusys0_sparken; /* 0x1C04 */ + uint32_t cpusys0_amuxsel; /* 0x1C08 */ + uint32_t reserved0_25[9]; /* 0x1C0C */ + uint32_t cpusys0_cpu0_spmc_ctl; /* 0x1C30 */ + uint32_t cpusys0_cpu1_spmc_ctl; /* 0x1C34 */ + uint32_t cpusys0_cpu2_spmc_ctl; /* 0x1C38 */ + uint32_t cpusys0_cpu3_spmc_ctl; /* 0x1C3C */ + uint32_t reserved0_26[8]; /* 0x1C40 */ + uint32_t mp0_sync_dcm_cgavg_ctrl; /* 0x1C60 */ + uint32_t mp0_sync_dcm_cgavg_fact; /* 0x1C64 */ + uint32_t mp0_sync_dcm_cgavg_rfact; /* 0x1C68 */ + uint32_t mp0_sync_dcm_cgavg; /* 0x1C6C */ + uint32_t mp0_l2_parity_clr; /* 0x1C70 */ + uint32_t reserved0_27[357]; /* 0x1C74 */ + uint32_t mp2_cpucfg; /* 0x2208 */ + uint32_t mp2_axi_config; /* 0x220C */ + uint32_t reserved0_28[25]; /* 0x2210 */ + uint32_t mp2_sync_dcm; /* 0x2274 */ + uint32_t reserved0_29[10]; /* 0x2278 */ + uint32_t ptp3_cputop_spmc0; /* 0x22A0 */ + uint32_t ptp3_cputop_spmc1; /* 0x22A4 */ + uint32_t reserved0_30[98]; /* 0x22A8 */ + uint32_t ptp3_cpu0_spmc0; /* 0x2430 */ + uint32_t ptp3_cpu0_spmc1; /* 0x2434 */ + uint32_t ptp3_cpu1_spmc0; /* 0x2438 */ + uint32_t ptp3_cpu1_spmc1; /* 0x243C */ + uint32_t ptp3_cpu2_spmc0; /* 0x2440 */ + uint32_t ptp3_cpu2_spmc1; /* 0x2444 */ + uint32_t ptp3_cpu3_spmc0; /* 0x2448 */ + uint32_t ptp3_cpu3_spmc1; /* 0x244C */ + uint32_t ptp3_cpux_spmc; /* 0x2450 */ + uint32_t reserved0_31[171]; /* 0x2454 */ + uint32_t spark2ld0; /* 0x2700 */ +}; + +static struct mt8183_mcucfg_regs *const mt8183_mcucfg = (void *)MCUCFG_BASE; + +enum { + SW_SPARK_EN = 1 << 0, + SW_NO_WAIT_FOR_Q_CHANNEL = 1 << 1, + SW_FSM_OVERRIDE = 1 << 2, + SW_LOGIC_PRE1_PDB = 1 << 3, + SW_LOGIC_PRE2_PDB = 1 << 4, + SW_LOGIC_PDB = 1 << 5, + SW_ISO = 1 << 6, + SW_SRAM_SLEEPB = 0x3f << 7, + SW_SRAM_ISOINTB = 1 << 13, + SW_CLK_DIS = 1 << 14, + SW_CKISO = 1 << 15, + SW_PD = 0x3f << 16, + SW_HOT_PLUG_RESET = 1 << 22, + SW_PWR_ON_OVERRIDE_EN = 1 << 23, + SW_PWR_ON = 1 << 24, + SW_COQ_DIS = 1 << 25, + LOGIC_PDBO_ALL_OFF_ACK = 1 << 26, + LOGIC_PDBO_ALL_ON_ACK = 1 << 27, + LOGIC_PRE2_PDBO_ALL_ON_ACK = 1 << 28, + LOGIC_PRE1_PDBO_ALL_ON_ACK = 1 << 29 +}; + +enum { + CPU_SW_SPARK_EN = 1 << 0, + CPU_SW_NO_WAIT_FOR_Q_CHANNEL = 1 << 1, + CPU_SW_FSM_OVERRIDE = 1 << 2, + CPU_SW_LOGIC_PRE1_PDB = 1 << 3, + CPU_SW_LOGIC_PRE2_PDB = 1 << 4, + CPU_SW_LOGIC_PDB = 1 << 5, + CPU_SW_ISO = 1 << 6, + CPU_SW_SRAM_SLEEPB = 1 << 7, + CPU_SW_SRAM_ISOINTB = 1 << 8, + CPU_SW_CLK_DIS = 1 << 9, + CPU_SW_CKISO = 1 << 10, + CPU_SW_PD = 0x1f << 11, + CPU_SW_HOT_PLUG_RESET = 1 << 16, + CPU_SW_POWR_ON_OVERRIDE_EN = 1 << 17, + CPU_SW_PWR_ON = 1 << 18, + CPU_SPARK2LDO_ALLSWOFF = 1 << 19, + CPU_PDBO_ALL_ON_ACK = 1 << 20, + CPU_PRE2_PDBO_ALLON_ACK = 1 << 21, + CPU_PRE1_PDBO_ALLON_ACK = 1 << 22 +}; + +enum { + MP2_AXI_CONFIG_ACINACTM = 1 << 0, + MPx_AXI_CONFIG_ACINACTM = 1 << 4, + MPX_CA7_MISC_CONFIG_STANDBYWFIL2 = 1 << 28 +}; + +enum { + MP0_CPU0_STANDBYWFE = 1 << 20, + MP0_CPU1_STANDBYWFE = 1 << 21, + MP0_CPU2_STANDBYWFE = 1 << 22, + MP0_CPU3_STANDBYWFE = 1 << 23 +}; + +enum { + MP1_CPU0_STANDBYWFE = 1 << 20, + MP1_CPU1_STANDBYWFE = 1 << 21, + MP1_CPU2_STANDBYWFE = 1 << 22, + MP1_CPU3_STANDBYWFE = 1 << 23 +}; + +enum { + B_SW_HOT_PLUG_RESET = 1 << 30, + B_SW_PD_OFFSET = 18, + B_SW_PD = 0x3f << B_SW_PD_OFFSET, + B_SW_SRAM_SLEEPB_OFFSET = 12, + B_SW_SRAM_SLEEPB = 0x3f << B_SW_SRAM_SLEEPB_OFFSET +}; + +enum { + B_SW_SRAM_ISOINTB = 1 << 9, + B_SW_ISO = 1 << 8, + B_SW_LOGIC_PDB = 1 << 7, + B_SW_LOGIC_PRE2_PDB = 1 << 6, + B_SW_LOGIC_PRE1_PDB = 1 << 5, + B_SW_FSM_OVERRIDE = 1 << 4, + B_SW_PWR_ON = 1 << 3, + B_SW_PWR_ON_OVERRIDE_EN = 1 << 2 +}; + +enum { + B_FSM_STATE_OUT_OFFSET = 6, + B_FSM_STATE_OUT_MASK = 0x1f << B_FSM_STATE_OUT_OFFSET, + B_SW_LOGIC_PDBO_ALL_OFF_ACK = 1 << 5, + B_SW_LOGIC_PDBO_ALL_ON_ACK = 1 << 4, + B_SW_LOGIC_PRE2_PDBO_ALL_ON_ACK = 1 << 3, + B_SW_LOGIC_PRE1_PDBO_ALL_ON_ACK = 1 << 2, + B_FSM_OFF = 0 << B_FSM_STATE_OUT_OFFSET, + B_FSM_ON = 1 << B_FSM_STATE_OUT_OFFSET, + B_FSM_RET = 2 << B_FSM_STATE_OUT_OFFSET +}; + +/* APB Module infracfg_ao */ +enum { + INFRA_TOPAXI_PROTECTEN_1 = INFRACFG_AO_BASE + 0x250, + INFRA_TOPAXI_PROTECTSTA1_1 = INFRACFG_AO_BASE + 0x258, + INFRA_TOPAXI_PROTECTEN_1_SET = INFRACFG_AO_BASE + 0x2A8, + INFRA_TOPAXI_PROTECTEN_1_CLR = INFRACFG_AO_BASE + 0x2AC +}; + +enum { + IDX_PROTECT_MP0_CACTIVE = 10, + IDX_PROTECT_MP1_CACTIVE = 11, + IDX_PROTECT_ICC0_CACTIVE = 12, + IDX_PROTECT_ICD0_CACTIVE = 13, + IDX_PROTECT_ICC1_CACTIVE = 14, + IDX_PROTECT_ICD1_CACTIVE = 15, + IDX_PROTECT_L2C0_CACTIVE = 26, + IDX_PROTECT_L2C1_CACTIVE = 27 +}; + +/* cpu boot mode */ +enum { + MP0_CPUCFG_64BIT_SHIFT = 12, + MP1_CPUCFG_64BIT_SHIFT = 28, + MP0_CPUCFG_64BIT = 0xf << MP0_CPUCFG_64BIT_SHIFT, + MP1_CPUCFG_64BIT = 0xfu << MP1_CPUCFG_64BIT_SHIFT +}; + +/* scu related */ +enum { + MP0_ACINACTM_SHIFT = 4, + MP1_ACINACTM_SHIFT = 4, + MP2_ACINACTM_SHIFT = 0, + MP0_ACINACTM = 1 << MP0_ACINACTM_SHIFT, + MP1_ACINACTM = 1 << MP1_ACINACTM_SHIFT, + MP2_ACINACTM = 1 << MP2_ACINACTM_SHIFT +}; + +enum { + MP1_DIS_RGU0_WAIT_PD_CPUS_L1_ACK_SHIFT = 0, + MP1_DIS_RGU1_WAIT_PD_CPUS_L1_ACK_SHIFT = 4, + MP1_DIS_RGU2_WAIT_PD_CPUS_L1_ACK_SHIFT = 8, + MP1_DIS_RGU3_WAIT_PD_CPUS_L1_ACK_SHIFT = 12, + MP1_DIS_RGU_NOCPU_WAIT_PD_CPUS_L1_ACK_SHIFT = 16, + + MP1_DIS_RGU0_WAIT_PD_CPUS_L1_ACK = + 0xf << MP1_DIS_RGU0_WAIT_PD_CPUS_L1_ACK_SHIFT, + MP1_DIS_RGU1_WAIT_PD_CPUS_L1_ACK = + 0xf << MP1_DIS_RGU1_WAIT_PD_CPUS_L1_ACK_SHIFT, + MP1_DIS_RGU2_WAIT_PD_CPUS_L1_ACK = + 0xf << MP1_DIS_RGU2_WAIT_PD_CPUS_L1_ACK_SHIFT, + MP1_DIS_RGU3_WAIT_PD_CPUS_L1_ACK = + 0xf << MP1_DIS_RGU3_WAIT_PD_CPUS_L1_ACK_SHIFT, + MP1_DIS_RGU_NOCPU_WAIT_PD_CPUS_L1_ACK = + 0xf << MP1_DIS_RGU_NOCPU_WAIT_PD_CPUS_L1_ACK_SHIFT +}; + +enum { + MP1_AINACTS_SHIFT = 4, + MP1_AINACTS = 1 << MP1_AINACTS_SHIFT +}; + +enum { + MP1_SW_CG_GEN_SHIFT = 12, + MP1_SW_CG_GEN = 1 << MP1_SW_CG_GEN_SHIFT +}; + +enum { + MP1_L2RSTDISABLE_SHIFT = 14, + MP1_L2RSTDISABLE = 1 << MP1_L2RSTDISABLE_SHIFT +}; + +/* bus pll divider dcm related */ +enum { + BUS_PLLDIVIDER_DCM_DBC_CNT_0_SHIFT = 11, + BUS_PLLDIV_ARMWFI_DCM_EN_SHIFT = 24, + BUS_PLLDIV_ARMWFE_DCM_EN_SHIFT = 25, + + BUS_PLLDIV_DCM = (1 << BUS_PLLDIVIDER_DCM_DBC_CNT_0_SHIFT) | + (1 << BUS_PLLDIV_ARMWFI_DCM_EN_SHIFT) | + (1 << BUS_PLLDIV_ARMWFE_DCM_EN_SHIFT) +}; + +/* mp0 pll divider dcm related */ +enum { + MP0_PLLDIV_DCM_DBC_CNT_0_SHIFT = 11, + MP0_PLLDIV_ARMWFI_DCM_EN_SHIFT = 24, + MP0_PLLDIV_ARMWFE_DCM_EN_SHIFT = 25, + MP0_PLLDIV_LASTCORE_IDLE_EN_SHIFT = 31, + MP0_PLLDIV_DCM = (1 << MP0_PLLDIV_DCM_DBC_CNT_0_SHIFT) | + (1 << MP0_PLLDIV_ARMWFI_DCM_EN_SHIFT) | + (1 << MP0_PLLDIV_ARMWFE_DCM_EN_SHIFT) | + (1u << MP0_PLLDIV_LASTCORE_IDLE_EN_SHIFT) +}; + +/* mp2 pll divider dcm related */ +enum { + MP2_PLLDIV_DCM_DBC_CNT_0_SHIFT = 11, + MP2_PLLDIV_ARMWFI_DCM_EN_SHIFT = 24, + MP2_PLLDIV_ARMWFE_DCM_EN_SHIFT = 25, + MP2_PLLDIV_LASTCORE_IDLE_EN_SHIFT = 31, + MP2_PLLDIV_DCM = (1 << MP2_PLLDIV_DCM_DBC_CNT_0_SHIFT) | + (1 << MP2_PLLDIV_ARMWFI_DCM_EN_SHIFT) | + (1 << MP2_PLLDIV_ARMWFE_DCM_EN_SHIFT) | + (1u << MP2_PLLDIV_LASTCORE_IDLE_EN_SHIFT) +}; + +/* mcsib dcm related */ +enum { + MCSIB_CACTIVE_SEL_SHIFT = 0, + MCSIB_DCM_EN_SHIFT = 16, + + MCSIB_CACTIVE_SEL_MASK = 0xffff << MCSIB_CACTIVE_SEL_SHIFT, + MCSIB_CACTIVE_SEL = 0xffff << MCSIB_CACTIVE_SEL_SHIFT, + + MCSIB_DCM_MASK = 0xffffu << MCSIB_DCM_EN_SHIFT, + MCSIB_DCM = 0xffffu << MCSIB_DCM_EN_SHIFT, +}; + +/* cci adb400 dcm related */ +enum { + CCI_M0_ADB400_DCM_EN_SHIFT = 0, + CCI_M1_ADB400_DCM_EN_SHIFT = 1, + CCI_M2_ADB400_DCM_EN_SHIFT = 2, + CCI_S2_ADB400_DCM_EN_SHIFT = 3, + CCI_S3_ADB400_DCM_EN_SHIFT = 4, + CCI_S4_ADB400_DCM_EN_SHIFT = 5, + CCI_S5_ADB400_DCM_EN_SHIFT = 6, + ACP_S3_ADB400_DCM_EN_SHIFT = 11, + + CCI_ADB400_DCM_MASK = (1 << CCI_M0_ADB400_DCM_EN_SHIFT) | + (1 << CCI_M1_ADB400_DCM_EN_SHIFT) | + (1 << CCI_M2_ADB400_DCM_EN_SHIFT) | + (1 << CCI_S2_ADB400_DCM_EN_SHIFT) | + (1 << CCI_S4_ADB400_DCM_EN_SHIFT) | + (1 << CCI_S4_ADB400_DCM_EN_SHIFT) | + (1 << CCI_S5_ADB400_DCM_EN_SHIFT) | + (1 << ACP_S3_ADB400_DCM_EN_SHIFT), + CCI_ADB400_DCM = (1 << CCI_M0_ADB400_DCM_EN_SHIFT) | + (1 << CCI_M1_ADB400_DCM_EN_SHIFT) | + (1 << CCI_M2_ADB400_DCM_EN_SHIFT) | + (0 << CCI_S2_ADB400_DCM_EN_SHIFT) | + (0 << CCI_S4_ADB400_DCM_EN_SHIFT) | + (0 << CCI_S4_ADB400_DCM_EN_SHIFT) | + (0 << CCI_S5_ADB400_DCM_EN_SHIFT) | + (1 << ACP_S3_ADB400_DCM_EN_SHIFT) +}; + +/* sync dcm related */ +enum { + CCI_SYNC_DCM_DIV_EN_SHIFT = 0, + CCI_SYNC_DCM_UPDATE_TOG_SHIFT = 1, + CCI_SYNC_DCM_DIV_SEL_SHIFT = 2, + MP0_SYNC_DCM_DIV_EN_SHIFT = 10, + MP0_SYNC_DCM_UPDATE_TOG_SHIFT = 11, + MP0_SYNC_DCM_DIV_SEL_SHIFT = 12, + + SYNC_DCM_MASK = (1 << CCI_SYNC_DCM_DIV_EN_SHIFT) | + (1 << CCI_SYNC_DCM_UPDATE_TOG_SHIFT) | + (0x7f << CCI_SYNC_DCM_DIV_SEL_SHIFT) | + (1 << MP0_SYNC_DCM_DIV_EN_SHIFT) | + (1 << MP0_SYNC_DCM_UPDATE_TOG_SHIFT) | + (0x7f << MP0_SYNC_DCM_DIV_SEL_SHIFT), + SYNC_DCM = (1 << CCI_SYNC_DCM_DIV_EN_SHIFT) | + (1 << CCI_SYNC_DCM_UPDATE_TOG_SHIFT) | + (0 << CCI_SYNC_DCM_DIV_SEL_SHIFT) | + (1 << MP0_SYNC_DCM_DIV_EN_SHIFT) | + (1 << MP0_SYNC_DCM_UPDATE_TOG_SHIFT) | + (0 << MP0_SYNC_DCM_DIV_SEL_SHIFT) +}; + +/* mcu bus dcm related */ +enum { + MCU_BUS_DCM_EN_SHIFT = 8, + MCU_BUS_DCM = 1 << MCU_BUS_DCM_EN_SHIFT +}; + +/* mcusys bus fabric dcm related */ +enum { + ACLK_INFRA_DYNAMIC_CG_EN_SHIFT = 0, + EMI2_ADB400_S_DCM_CTRL_SHIFT = 1, + ACLK_GPU_DYNAMIC_CG_EN_SHIFT = 2, + ACLK_PSYS_DYNAMIC_CG_EN_SHIFT = 3, + MP0_ADB400_S_DCM_CTRL_SHIFT = 4, + MP0_ADB400_M_DCM_CTRL_SHIFT = 5, + MP1_ADB400_S_DCM_CTRL_SHIFT = 6, + MP1_ADB400_M_DCM_CTRL_SHIFT = 7, + EMICLK_EMI_DYNAMIC_CG_EN_SHIFT = 8, + INFRACLK_INFRA_DYNAMIC_CG_EN_SHIFT = 9, + EMICLK_GPU_DYNAMIC_CG_EN_SHIFT = 10, + INFRACLK_PSYS_DYNAMIC_CG_EN_SHIFT = 11, + EMICLK_EMI1_DYNAMIC_CG_EN_SHIFT = 12, + EMI1_ADB400_S_DCM_CTRL_SHIFT = 16, + MP2_ADB400_M_DCM_CTRL_SHIFT = 17, + MP0_ICC_AXI_STREAM_ARCH_CG_SHIFT = 18, + MP1_ICC_AXI_STREAM_ARCH_CG_SHIFT = 19, + MP2_ICC_AXI_STREAM_ARCH_CG_SHIFT = 20, + L2_SHARE_ADB400_DCM_CTRL_SHIFT = 21, + MP1_AGGRESS_DCM_CTRL_SHIFT = 22, + MP0_AGGRESS_DCM_CTRL_SHIFT = 23, + MP0_ADB400_ACP_S_DCM_CTRL_SHIFT = 24, + MP0_ADB400_ACP_M_DCM_CTRL_SHIFT = 25, + MP1_ADB400_ACP_S_DCM_CTRL_SHIFT = 26, + MP1_ADB400_ACP_M_DCM_CTRL_SHIFT = 27, + MP3_ADB400_M_DCM_CTRL_SHIFT = 28, + MP3_ICC_AXI_STREAM_ARCH_CG_SHIFT = 29, + + MCUSYS_BUS_FABRIC_DCM_MASK = (1 << ACLK_INFRA_DYNAMIC_CG_EN_SHIFT) | + (1 << EMI2_ADB400_S_DCM_CTRL_SHIFT) | + (1 << ACLK_GPU_DYNAMIC_CG_EN_SHIFT) | + (1 << ACLK_PSYS_DYNAMIC_CG_EN_SHIFT) | + (1 << MP0_ADB400_S_DCM_CTRL_SHIFT) | + (1 << MP0_ADB400_M_DCM_CTRL_SHIFT) | + (1 << MP1_ADB400_S_DCM_CTRL_SHIFT) | + (1 << MP1_ADB400_M_DCM_CTRL_SHIFT) | + (1 << EMICLK_EMI_DYNAMIC_CG_EN_SHIFT) | + (1 << INFRACLK_INFRA_DYNAMIC_CG_EN_SHIFT) | + (1 << EMICLK_GPU_DYNAMIC_CG_EN_SHIFT) | + (1 << INFRACLK_PSYS_DYNAMIC_CG_EN_SHIFT) | + (1 << EMICLK_EMI1_DYNAMIC_CG_EN_SHIFT) | + (1 << EMI1_ADB400_S_DCM_CTRL_SHIFT) | + (1 << MP2_ADB400_M_DCM_CTRL_SHIFT) | + (1 << MP0_ICC_AXI_STREAM_ARCH_CG_SHIFT) | + (1 << MP1_ICC_AXI_STREAM_ARCH_CG_SHIFT) | + (1 << MP2_ICC_AXI_STREAM_ARCH_CG_SHIFT) | + (1 << L2_SHARE_ADB400_DCM_CTRL_SHIFT) | + (1 << MP1_AGGRESS_DCM_CTRL_SHIFT) | + (1 << MP0_AGGRESS_DCM_CTRL_SHIFT) | + (1 << MP0_ADB400_ACP_S_DCM_CTRL_SHIFT) | + (1 << MP0_ADB400_ACP_M_DCM_CTRL_SHIFT) | + (1 << MP1_ADB400_ACP_S_DCM_CTRL_SHIFT) | + (1 << MP1_ADB400_ACP_M_DCM_CTRL_SHIFT) | + (1 << MP3_ADB400_M_DCM_CTRL_SHIFT) | + (1 << MP3_ICC_AXI_STREAM_ARCH_CG_SHIFT), + + MCUSYS_BUS_FABRIC_DCM = (1 << ACLK_INFRA_DYNAMIC_CG_EN_SHIFT) | + (1 << EMI2_ADB400_S_DCM_CTRL_SHIFT) | + (1 << ACLK_GPU_DYNAMIC_CG_EN_SHIFT) | + (1 << ACLK_PSYS_DYNAMIC_CG_EN_SHIFT) | + (0 << MP0_ADB400_S_DCM_CTRL_SHIFT) | + (0 << MP0_ADB400_M_DCM_CTRL_SHIFT) | + (1 << MP1_ADB400_S_DCM_CTRL_SHIFT) | + (1 << MP1_ADB400_M_DCM_CTRL_SHIFT) | + (1 << EMICLK_EMI_DYNAMIC_CG_EN_SHIFT) | + (1 << INFRACLK_INFRA_DYNAMIC_CG_EN_SHIFT) | + (1 << EMICLK_GPU_DYNAMIC_CG_EN_SHIFT) | + (1 << INFRACLK_PSYS_DYNAMIC_CG_EN_SHIFT) | + (1 << EMICLK_EMI1_DYNAMIC_CG_EN_SHIFT) | + (1 << EMI1_ADB400_S_DCM_CTRL_SHIFT) | + (0 << MP2_ADB400_M_DCM_CTRL_SHIFT) | + (1 << MP0_ICC_AXI_STREAM_ARCH_CG_SHIFT) | + (1 << MP1_ICC_AXI_STREAM_ARCH_CG_SHIFT) | + (1 << MP2_ICC_AXI_STREAM_ARCH_CG_SHIFT) | + (1 << L2_SHARE_ADB400_DCM_CTRL_SHIFT) | + (1 << MP1_AGGRESS_DCM_CTRL_SHIFT) | + (1 << MP0_AGGRESS_DCM_CTRL_SHIFT) | + (1 << MP0_ADB400_ACP_S_DCM_CTRL_SHIFT) | + (1 << MP0_ADB400_ACP_M_DCM_CTRL_SHIFT) | + (1 << MP1_ADB400_ACP_S_DCM_CTRL_SHIFT) | + (1 << MP1_ADB400_ACP_M_DCM_CTRL_SHIFT) | + (1 << MP3_ADB400_M_DCM_CTRL_SHIFT) | + (1 << MP3_ICC_AXI_STREAM_ARCH_CG_SHIFT) +}; + +/* l2c_sram dcm related */ +enum { + L2C_SRAM_DCM_EN_SHIFT = 0, + L2C_SRAM_DCM = 1 << L2C_SRAM_DCM_EN_SHIFT +}; + +/* mcu misc dcm related */ +enum { + MP0_CNTVALUEB_DCM_EN_SHIFT = 0, + MP_CNTVALUEB_DCM_EN = 8, + + CNTVALUEB_DCM = (1 << MP0_CNTVALUEB_DCM_EN_SHIFT) | + (1 << MP_CNTVALUEB_DCM_EN) +}; + +/* sync dcm cluster config related */ +enum { + MP0_SYNC_DCM_STALL_WR_EN_SHIFT = 7, + MCUSYS_MAX_ACCESS_LATENCY_SHIFT = 24, + + MCU0_SYNC_DCM_STALL_WR_EN = 1 << MP0_SYNC_DCM_STALL_WR_EN_SHIFT, + + MCUSYS_MAX_ACCESS_LATENCY_MASK = 0xf << MCUSYS_MAX_ACCESS_LATENCY_SHIFT, + MCUSYS_MAX_ACCESS_LATENCY = 0x5 << MCUSYS_MAX_ACCESS_LATENCY_SHIFT +}; + +/* cpusys rgu dcm related */ +enum { + CPUSYS_RGU_DCM_CONFIG_SHIFT = 0, + + CPUSYS_RGU_DCM_CINFIG = 1 << CPUSYS_RGU_DCM_CONFIG_SHIFT +}; + +/* mp2 sync dcm related */ +enum { + MP2_DCM_EN_SHIFT = 0, + + MP2_DCM_EN = 1 << MP2_DCM_EN_SHIFT +}; +#endif /* MT8183_MCUCFG_H */ diff --git a/plat/mediatek/mt8183/include/mt_gic_v3.h b/plat/mediatek/mt8183/include/mt_gic_v3.h new file mode 100644 index 0000000..b6fc29b --- /dev/null +++ b/plat/mediatek/mt8183/include/mt_gic_v3.h @@ -0,0 +1,34 @@ +/* + * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef MT_GIC_V3_H +#define MT_GIC_V3_H + +#include <lib/mmio.h> + +#define GIC_INT_MASK (MCUCFG_BASE + 0x5e8) +#define GIC500_ACTIVE_SEL_SHIFT 3 +#define GIC500_ACTIVE_SEL_MASK (0x7 << GIC500_ACTIVE_SEL_SHIFT) +#define GIC500_ACTIVE_CPU_SHIFT 16 +#define GIC500_ACTIVE_CPU_MASK (0xff << GIC500_ACTIVE_CPU_SHIFT) + +#define NR_INT_POL_CTL 20 + +void mt_gic_driver_init(void); +void mt_gic_init(void); +void mt_gic_set_pending(uint32_t irq); +uint32_t mt_gic_get_pending(uint32_t irq); +void mt_gic_cpuif_enable(void); +void mt_gic_cpuif_disable(void); +void mt_gic_rdistif_init(void); +void mt_gic_distif_save(void); +void mt_gic_distif_restore(void); +void mt_gic_rdistif_save(void); +void mt_gic_rdistif_restore(void); +void mt_gic_sync_dcm_enable(void); +void mt_gic_sync_dcm_disable(void); + +#endif /* MT_GIC_V3_H */ diff --git a/plat/mediatek/mt8183/include/plat_dcm.h b/plat/mediatek/mt8183/include/plat_dcm.h new file mode 100644 index 0000000..afa9b63 --- /dev/null +++ b/plat/mediatek/mt8183/include/plat_dcm.h @@ -0,0 +1,53 @@ +/* + * Copyright (c) 2019, MediaTek Inc. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef PLAT_DCM_H +#define PLAT_DCM_H + +#define MP2_SYNC_DCM (MCUCFG_BASE + 0x2274) +#define MP2_SYNC_DCM_MASK (0x1 << 0) +#define MP2_SYNC_DCM_ON (0x1 << 0) +#define MP2_SYNC_DCM_OFF (0x0 << 0) + +extern uint64_t plat_dcm_mcsi_a_addr; +extern uint32_t plat_dcm_mcsi_a_val; +extern int plat_dcm_initiated; + +extern void plat_dcm_mcsi_a_backup(void); +extern void plat_dcm_mcsi_a_restore(void); +extern void plat_dcm_rgu_enable(void); +extern void plat_dcm_restore_cluster_on(unsigned long mpidr); +extern void plat_dcm_msg_handler(uint64_t x1); +extern unsigned long plat_dcm_get_enabled_cnt(uint64_t type); +extern void plat_dcm_init(void); + +#define ALL_DCM_TYPE (ARMCORE_DCM_TYPE | MCUSYS_DCM_TYPE \ + | STALL_DCM_TYPE | BIG_CORE_DCM_TYPE \ + | GIC_SYNC_DCM_TYPE | RGU_DCM_TYPE \ + | INFRA_DCM_TYPE \ + | DDRPHY_DCM_TYPE | EMI_DCM_TYPE | DRAMC_DCM_TYPE \ + | MCSI_DCM_TYPE) + +enum { + ARMCORE_DCM_TYPE = (1U << 0), + MCUSYS_DCM_TYPE = (1U << 1), + INFRA_DCM_TYPE = (1U << 2), + PERI_DCM_TYPE = (1U << 3), + EMI_DCM_TYPE = (1U << 4), + DRAMC_DCM_TYPE = (1U << 5), + DDRPHY_DCM_TYPE = (1U << 6), + STALL_DCM_TYPE = (1U << 7), + BIG_CORE_DCM_TYPE = (1U << 8), + GIC_SYNC_DCM_TYPE = (1U << 9), + LAST_CORE_DCM_TYPE = (1U << 10), + RGU_DCM_TYPE = (1U << 11), + TOPCKG_DCM_TYPE = (1U << 12), + LPDMA_DCM_TYPE = (1U << 13), + MCSI_DCM_TYPE = (1U << 14), + NR_DCM_TYPE = 15, +}; + +#endif /* PLAT_DCM_H */
\ No newline at end of file diff --git a/plat/mediatek/mt8183/include/plat_debug.h b/plat/mediatek/mt8183/include/plat_debug.h new file mode 100644 index 0000000..c9d73cc --- /dev/null +++ b/plat/mediatek/mt8183/include/plat_debug.h @@ -0,0 +1,34 @@ +/* + * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef PLATFORM_DEBUG_H +#define PLATFORM_DEBUG_H + +#define sync_writel(addr, val) \ + do { mmio_write_32((addr), (val)); dsbsy(); } while (0) + +#define MCU_BIU_BASE 0x0c530000 +#define MISC1_CFG_BASE 0xb00 +#define CA15M_CFG_BASE 0x2000 +#define DFD_INTERNAL_CTL (MCU_BIU_BASE + MISC1_CFG_BASE + 0x00) +#define CA15M_DBG_CONTROL (MCU_BIU_BASE + CA15M_CFG_BASE + 0x728) +#define CA15M_PWR_RST_CTL (MCU_BIU_BASE + CA15M_CFG_BASE + 0x08) +#define VPROC_EXT_CTL 0x10006290 + +#define CFG_SF_CTRL 0x0c510014 +#define CFG_SF_INI 0x0c510010 + +#define BIT_CA15M_L2PARITY_EN (1 << 1) +#define BIT_CA15M_LASTPC_DIS (1 << 8) + +#define MCU_ALL_PWR_ON_CTRL 0x0c530b58 +#define PLAT_MTK_CIRCULAR_BUFFER_UNLOCK 0xefab4133 +#define PLAT_MTK_CIRCULAR_BUFFER_LOCK 0xefab4134 + +extern void circular_buffer_setup(void); +extern void l2c_parity_check_setup(void); +extern void clear_all_on_mux(void); +#endif /* PLATFORM_DEBUG_H */ diff --git a/plat/mediatek/mt8183/include/plat_macros.S b/plat/mediatek/mt8183/include/plat_macros.S new file mode 100644 index 0000000..cac7769 --- /dev/null +++ b/plat/mediatek/mt8183/include/plat_macros.S @@ -0,0 +1,78 @@ +/* + * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include <drivers/arm/cci.h> +#include <drivers/arm/gic_common.h> +#include <drivers/arm/gicv2.h> +#include <platform_def.h> + +.section .rodata.gic_reg_name, "aS" +gicc_regs: + .asciz "gicc_hppir", "gicc_ahppir", "gicc_ctlr", "" +gicd_pend_reg: + .asciz "gicd_ispendr regs (Offsets 0x200 - 0x278)\n" \ + " Offset:\t\t\tvalue\n" +newline: + .asciz "\n" +spacer: + .asciz ":\t\t0x" + +.section .rodata.cci_reg_name, "aS" +cci_iface_regs: + .asciz "cci_snoop_ctrl_cluster0", "cci_snoop_ctrl_cluster1" , "" + + /* --------------------------------------------- + * The below macro prints out relevant GIC and + * CCI registers whenever an unhandled exception + * is taken in BL31. + * Clobbers: x0 - x10, x26, x27, sp + * --------------------------------------------- + */ + .macro plat_crash_print_regs + mov_imm x26, BASE_GICD_BASE + mov_imm x27, BASE_GICC_BASE + /* Load the gicc reg list to x6 */ + adr x6, gicc_regs + /* Load the gicc regs to gp regs used by str_in_crash_buf_print */ + ldr w8, [x27, #GICC_HPPIR] + ldr w9, [x27, #GICC_AHPPIR] + ldr w10, [x27, #GICC_CTLR] + /* Store to the crash buf and print to console */ + bl str_in_crash_buf_print + + /* Print the GICD_ISPENDR regs */ + add x7, x26, #GICD_ISPENDR + adr x4, gicd_pend_reg + bl asm_print_str +gicd_ispendr_loop: + sub x4, x7, x26 + cmp x4, #0x280 + b.eq exit_print_gic_regs + bl asm_print_hex + + adr x4, spacer + bl asm_print_str + + ldr x4, [x7], #8 + bl asm_print_hex + + adr x4, newline + bl asm_print_str + b gicd_ispendr_loop +exit_print_gic_regs: + + adr x6, cci_iface_regs + /* Store in x7 the base address of the first interface */ + mov_imm x7, (PLAT_MT_CCI_BASE + SLAVE_IFACE_OFFSET( \ + PLAT_MT_CCI_CLUSTER0_SL_IFACE_IX)) + ldr w8, [x7, #SNOOP_CTRL_REG] + /* Store in x7 the base address of the second interface */ + mov_imm x7, (PLAT_MT_CCI_BASE + SLAVE_IFACE_OFFSET( \ + PLAT_MT_CCI_CLUSTER1_SL_IFACE_IX)) + ldr w9, [x7, #SNOOP_CTRL_REG] + /* Store to the crash buf and print to console */ + bl str_in_crash_buf_print + .endm diff --git a/plat/mediatek/mt8183/include/plat_private.h b/plat/mediatek/mt8183/include/plat_private.h new file mode 100644 index 0000000..0853934 --- /dev/null +++ b/plat/mediatek/mt8183/include/plat_private.h @@ -0,0 +1,28 @@ +/* + * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef PLAT_PRIVATE_H +#define PLAT_PRIVATE_H + +/******************************************************************************* + * Function and variable prototypes + ******************************************************************************/ +void plat_configure_mmu_el3(uintptr_t total_base, + uintptr_t total_size, + uintptr_t ro_start, + uintptr_t ro_limit, + uintptr_t coh_start, + uintptr_t coh_limit); + +void plat_mtk_cci_init(void); +void plat_mtk_cci_enable(void); +void plat_mtk_cci_disable(void); +void plat_mtk_cci_init_sf(void); + +/* Declarations for plat_topology.c */ +int mt_setup_topology(void); + +#endif /* PLAT_PRIVATE_H */ diff --git a/plat/mediatek/mt8183/include/platform_def.h b/plat/mediatek/mt8183/include/platform_def.h new file mode 100644 index 0000000..25ccfbc --- /dev/null +++ b/plat/mediatek/mt8183/include/platform_def.h @@ -0,0 +1,321 @@ +/* + * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef PLATFORM_DEF_H +#define PLATFORM_DEF_H + +#include <arch.h> +#include <drivers/arm/gic_common.h> + +#define PLAT_PRIMARY_CPU 0x0 + +#define IO_PHYS 0x10000000 +#define INFRACFG_AO_BASE (IO_PHYS + 0x1000) +#define PERI_BASE (IO_PHYS + 0x3000) +#define GPIO_BASE (IO_PHYS + 0x5000) +#define SPM_BASE (IO_PHYS + 0x6000) +#define SLEEP_REG_MD_BASE (IO_PHYS + 0xf000) +#define RGU_BASE (IO_PHYS + 0x7000) +#define I2C4_BASE_SE (IO_PHYS + 0x1008000) +#define I2C2_BASE_SE (IO_PHYS + 0x1009000) +#define PMIC_WRAP_BASE (IO_PHYS + 0xd000) +#define MCUCFG_BASE 0x0c530000 +#define CFG_SF_CTRL 0x0c510014 +#define CFG_SF_INI 0x0c510010 +#define EMI_BASE (IO_PHYS + 0x219000) +#define EMI_MPU_BASE (IO_PHYS + 0x226000) +#define TRNG_base (IO_PHYS + 0x20f000) +#define MT_GIC_BASE 0x0c000000 +#define PLAT_MT_CCI_BASE 0x0c500000 +#define CCI_SIZE 0x00010000 +#define EINT_BASE 0x1000b000 +#define DVFSRC_BASE (IO_PHYS + 0x12000) + +#define SSPM_CFGREG_BASE (IO_PHYS + 0x440000) +#define SSPM_MBOX_3_BASE (IO_PHYS + 0x480000) + +#define INFRACFG_AO_BASE (IO_PHYS + 0x1000) + +#define TOPCKGEN_BASE (IO_PHYS + 0x0) +#define CLK_SCP_CFG_0 (TOPCKGEN_BASE + 0x200) +#define CLK_SCP_CFG_1 (TOPCKGEN_BASE + 0x204) + +#define APMIXEDSYS (IO_PHYS + 0xC000) +#define AP_PLL_CON3 (APMIXEDSYS + 0xC) +#define AP_PLL_CON4 (APMIXEDSYS + 0x10) +#define AP_PLL_CON6 (APMIXEDSYS + 0x18) +#define ARMPLL_LL_CON0 (APMIXEDSYS + 0x200) +#define ARMPLL_L_CON0 (APMIXEDSYS + 0x210) +#define ARMPLL_L_PWR_CON0 (APMIXEDSYS + 0x21c) +#define MAINPLL_CON0 (APMIXEDSYS + 0x220) +#define CCIPLL_CON0 (APMIXEDSYS + 0x290) + +#define TOP_CKMUXSEL (INFRACFG_AO_BASE + 0x0) + +#define armpll_mux1_sel_big_mask (0xf << 4) +#define armpll_mux1_sel_big_ARMSPLL (0x1 << 4) +#define armpll_mux1_sel_sml_mask (0xf << 8) +#define armpll_mux1_sel_sml_ARMSPLL (0x1 << 8) + + +/* Aggregate of all devices in the first GB */ +#define MTK_DEV_RNG0_BASE IO_PHYS +#define MTK_DEV_RNG0_SIZE 0x490000 +#define MTK_DEV_RNG1_BASE (IO_PHYS + 0x1000000) +#define MTK_DEV_RNG1_SIZE 0x4000000 +#define MTK_DEV_RNG2_BASE 0x0c000000 +#define MTK_DEV_RNG2_SIZE 0x600000 +#define MT_MCUSYS_SIZE 0x90000 +#define RAM_CONSOLE_BASE 0x11d000 +#define RAM_CONSOLE_SIZE 0x1000 + +/******************************************************************************* + * MSDC + ******************************************************************************/ +#define MSDC0_BASE (IO_PHYS + 0x01230000) + +/******************************************************************************* + * MCUSYS related constants + ******************************************************************************/ +#define MT_L2_WRITE_ACCESS_RATE (MCUCFG_BASE + 0x604) +#define MP0_CA7L_CACHE_CONFIG (MCUCFG_BASE + 0x7f0) +#define MP1_CA7L_CACHE_CONFIG (MCUCFG_BASE + 0x7f4) +#define EMI_WFIFO (MCUCFG_BASE + 0x0b5c) + +/******************************************************************************* + * GIC related constants + ******************************************************************************/ +#define MT_POLARITY_LOW 0 +#define MT_POLARITY_HIGH 1 +#define MT_EDGE_SENSITIVE 1 +#define MT_LEVEL_SENSITIVE 0 + +/******************************************************************************* + * UART related constants + ******************************************************************************/ +#define UART0_BASE (IO_PHYS + 0x01002000) +#define UART1_BASE (IO_PHYS + 0x01003000) + +#define UART_BAUDRATE 115200 +#define UART_CLOCK 26000000 + +/******************************************************************************* + * System counter frequency related constants + ******************************************************************************/ +#define SYS_COUNTER_FREQ_IN_TICKS 13000000 +#define SYS_COUNTER_FREQ_IN_MHZ 13 + +/******************************************************************************* + * GIC-400 & interrupt handling related constants + ******************************************************************************/ + +/* Base MTK_platform compatible GIC memory map */ +#define BASE_GICD_BASE MT_GIC_BASE +#define BASE_GICC_BASE (MT_GIC_BASE + 0x400000) +#define MT_GIC_RDIST_BASE (MT_GIC_BASE + 0x100000) +#define BASE_GICR_BASE (MT_GIC_BASE + 0x100000) +#define BASE_GICH_BASE (MT_GIC_BASE + 0x4000) +#define BASE_GICV_BASE (MT_GIC_BASE + 0x6000) +#define INT_POL_CTL0 (MCUCFG_BASE + 0xa80) +#define SEC_POL_CTL_EN0 (MCUCFG_BASE + 0xa00) +#define GIC_SYNC_DCM (MCUCFG_BASE + 0x758) +#define GIC_SYNC_DCM_MASK 0x3 +#define GIC_SYNC_DCM_ON 0x3 +#define GIC_SYNC_DCM_OFF 0x0 +#define GIC_PRIVATE_SIGNALS 32 + +#define PLAT_ARM_GICD_BASE BASE_GICD_BASE +#define PLAT_ARM_GICC_BASE BASE_GICC_BASE + +#define PLAT_ARM_G1S_IRQ_PROPS(grp) ( \ +INTR_PROP_DESC(MT_IRQ_SEC_SGI_0, GIC_HIGHEST_SEC_PRIORITY, grp, \ + GIC_INTR_CFG_EDGE), \ +INTR_PROP_DESC(MT_IRQ_SEC_SGI_1, GIC_HIGHEST_SEC_PRIORITY, grp, \ + GIC_INTR_CFG_EDGE), \ +INTR_PROP_DESC(MT_IRQ_SEC_SGI_2, GIC_HIGHEST_SEC_PRIORITY, grp, \ + GIC_INTR_CFG_EDGE), \ +INTR_PROP_DESC(MT_IRQ_SEC_SGI_3, GIC_HIGHEST_SEC_PRIORITY, grp, \ + GIC_INTR_CFG_EDGE), \ +INTR_PROP_DESC(MT_IRQ_SEC_SGI_4, GIC_HIGHEST_SEC_PRIORITY, grp, \ + GIC_INTR_CFG_EDGE), \ +INTR_PROP_DESC(MT_IRQ_SEC_SGI_5, GIC_HIGHEST_SEC_PRIORITY, grp, \ + GIC_INTR_CFG_EDGE), \ +INTR_PROP_DESC(MT_IRQ_SEC_SGI_6, GIC_HIGHEST_SEC_PRIORITY, grp, \ + GIC_INTR_CFG_EDGE), \ +INTR_PROP_DESC(MT_IRQ_SEC_SGI_7, GIC_HIGHEST_SEC_PRIORITY, grp, \ + GIC_INTR_CFG_EDGE)) \ + +#define PLAT_ARM_G0_IRQ_PROPS(grp) + +/******************************************************************************* + * CCI-400 related constants + ******************************************************************************/ +#define PLAT_MT_CCI_CLUSTER0_SL_IFACE_IX 4 +#define PLAT_MT_CCI_CLUSTER1_SL_IFACE_IX 3 + +/******************************************************************************* + * WDT Registers + ******************************************************************************/ +#define MTK_WDT_BASE (IO_PHYS + 0x00007000) +#define MTK_WDT_SIZE 0x1000 +#define MTK_WDT_MODE (MTK_WDT_BASE + 0x0000) +#define MTK_WDT_LENGTH (MTK_WDT_BASE + 0x0004) +#define MTK_WDT_RESTART (MTK_WDT_BASE + 0x0008) +#define MTK_WDT_STATUS (MTK_WDT_BASE + 0x000C) +#define MTK_WDT_INTERVAL (MTK_WDT_BASE + 0x0010) +#define MTK_WDT_SWRST (MTK_WDT_BASE + 0x0014) +#define MTK_WDT_SWSYSRST (MTK_WDT_BASE + 0x0018) +#define MTK_WDT_NONRST_REG (MTK_WDT_BASE + 0x0020) +#define MTK_WDT_NONRST_REG2 (MTK_WDT_BASE + 0x0024) +#define MTK_WDT_REQ_MODE (MTK_WDT_BASE + 0x0030) +#define MTK_WDT_REQ_IRQ_EN (MTK_WDT_BASE + 0x0034) +#define MTK_WDT_EXT_REQ_CON (MTK_WDT_BASE + 0x0038) +#define MTK_WDT_DEBUG_CTL (MTK_WDT_BASE + 0x0040) +#define MTK_WDT_LATCH_CTL (MTK_WDT_BASE + 0x0044) +#define MTK_WDT_DEBUG_CTL2 (MTK_WDT_BASE + 0x00A0) +#define MTK_WDT_COUNTER (MTK_WDT_BASE + 0x0514) + +/* WDT_STATUS */ +#define MTK_WDT_STATUS_SPM_THERMAL_RST (1 << 0) +#define MTK_WDT_STATUS_SPM_RST (1 << 1) +#define MTK_WDT_STATUS_EINT_RST (1 << 2) +#define MTK_WDT_STATUS_SYSRST_RST (1 << 3) /* from PMIC */ +#define MTK_WDT_STATUS_DVFSP_RST (1 << 4) +#define MTK_WDT_STATUS_PMCU_RST (1 << 16) +#define MTK_WDT_STATUS_MDDBG_RST (1 << 17) +#define MTK_WDT_STATUS_THERMAL_DIRECT_RST (1 << 18) +#define MTK_WDT_STATUS_DEBUG_RST (1 << 19) +#define MTK_WDT_STATUS_SECURITY_RST (1 << 28) +#define MTK_WDT_STATUS_IRQ_ASSERT (1 << 29) +#define MTK_WDT_STATUS_SW_WDT_RST (1 << 30) +#define MTK_WDT_STATUS_HW_WDT_RST (1U << 31) + +/* RGU other related */ +#define MTK_WDT_MODE_DUAL_MODE 0x0040 +#define MTK_WDT_MODE_IRQ 0x0008 +#define MTK_WDT_MODE_KEY 0x22000000 +#define MTK_WDT_MODE_EXTEN 0x0004 +#define MTK_WDT_SWRST_KEY 0x1209 +#define MTK_WDT_RESTART_KEY 0x1971 + +/******************************************************************************* + * TRNG Registers + ******************************************************************************/ +#define TRNG_BASE_ADDR TRNG_base +#define TRNG_BASE_SIZE 0x1000 +#define TRNG_CTRL (TRNG_base + 0x0000) +#define TRNG_TIME (TRNG_base + 0x0004) +#define TRNG_DATA (TRNG_base + 0x0008) +#define TRNG_PDN_base 0x10001000 +#define TRNG_PDN_BASE_ADDR TRNG_PDN_BASE_ADDR +#define TRNG_PDN_BASE_SIZE 0x1000 +#define TRNG_PDN_SET (TRNG_PDN_base + 0x0088) +#define TRNG_PDN_CLR (TRNG_PDN_base + 0x008c) +#define TRNG_PDN_STATUS (TRNG_PDN_base + 0x0094) +#define TRNG_CTRL_RDY 0x80000000 +#define TRNG_CTRL_START 0x00000001 +#define TRNG_PDN_VALUE 0x200 + +/* FIQ platform related define */ +#define MT_IRQ_SEC_SGI_0 8 +#define MT_IRQ_SEC_SGI_1 9 +#define MT_IRQ_SEC_SGI_2 10 +#define MT_IRQ_SEC_SGI_3 11 +#define MT_IRQ_SEC_SGI_4 12 +#define MT_IRQ_SEC_SGI_5 13 +#define MT_IRQ_SEC_SGI_6 14 +#define MT_IRQ_SEC_SGI_7 15 + +#define FIQ_SMP_CALL_SGI 13 +#define WDT_IRQ_BIT_ID 174 +#define ATF_LOG_IRQ_ID 277 + +#define ATF_AMMS_IRQ_ID 338 +#define PCCIF1_IRQ0_BIT_ID 185 +#define PCCIF1_IRQ1_BIT_ID 186 + +#define DEBUG_XLAT_TABLE 0 + +/******************************************************************************* + * Platform binary types for linking + ******************************************************************************/ +#define PLATFORM_LINKER_FORMAT "elf64-littleaarch64" +#define PLATFORM_LINKER_ARCH aarch64 + +/******************************************************************************* + * Generic platform constants + ******************************************************************************/ + +/* Size of cacheable stacks */ +#if DEBUG_XLAT_TABLE +#define PLATFORM_STACK_SIZE 0x800 +#elif IMAGE_BL1 +#define PLATFORM_STACK_SIZE 0x440 +#elif IMAGE_BL2 +#define PLATFORM_STACK_SIZE 0x400 +#elif IMAGE_BL31 +#define PLATFORM_STACK_SIZE 0x800 +#elif IMAGE_BL32 +#define PLATFORM_STACK_SIZE 0x440 +#endif + +#define FIRMWARE_WELCOME_STR "Booting Trusted Firmware\n" +#define PLAT_MAX_PWR_LVL U(2) +#define PLAT_MAX_RET_STATE U(1) +#define PLAT_MAX_OFF_STATE U(2) + +#define PLATFORM_CACHE_LINE_SIZE 64 +#define PLATFORM_SYSTEM_COUNT U(1) +#define PLATFORM_CLUSTER_COUNT U(2) +#define PLATFORM_CLUSTER0_CORE_COUNT U(4) +#define PLATFORM_CLUSTER1_CORE_COUNT U(4) +#define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER1_CORE_COUNT + \ + PLATFORM_CLUSTER0_CORE_COUNT) +#define PLATFORM_MAX_CPUS_PER_CLUSTER U(4) +#define PLATFORM_NUM_AFFS (PLATFORM_SYSTEM_COUNT + \ + PLATFORM_CLUSTER_COUNT + \ + PLATFORM_CORE_COUNT) + +#define SOC_CHIP_ID U(0x8183) + +/******************************************************************************* + * Platform memory map related constants + ******************************************************************************/ + +#define TZRAM_BASE 0x54600000 +#define TZRAM_SIZE 0x00030000 + +/******************************************************************************* + * BL31 specific defines. + ******************************************************************************/ +/* + * Put BL31 at the top of the Trusted SRAM (just below the shared memory, if + * present). BL31_BASE is calculated using the current BL31 debug size plus a + * little space for growth. + */ +#define BL31_BASE (TZRAM_BASE + 0x1000) +#define BL31_LIMIT (TZRAM_BASE + TZRAM_SIZE) + +/******************************************************************************* + * Platform specific page table and MMU setup constants + ******************************************************************************/ +#define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32) +#define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32) +#define MAX_XLAT_TABLES 16 +#define MAX_MMAP_REGIONS 16 + +/******************************************************************************* + * Declarations and constants to access the mailboxes safely. Each mailbox is + * aligned on the biggest cache line size in the platform. This is known only + * to the platform as it might have a combination of integrated and external + * caches. Such alignment ensures that two maiboxes do not sit on the same cache + * line at any cache level. They could belong to different cpus/clusters & + * get written while being protected by different locks causing corruption of + * a valid mailbox address. + ******************************************************************************/ +#define CACHE_WRITEBACK_SHIFT 6 +#define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT) +#endif /* PLATFORM_DEF_H */ diff --git a/plat/mediatek/mt8183/include/power_tracer.h b/plat/mediatek/mt8183/include/power_tracer.h new file mode 100644 index 0000000..c93be64 --- /dev/null +++ b/plat/mediatek/mt8183/include/power_tracer.h @@ -0,0 +1,20 @@ +/* + * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef POWER_TRACER_H +#define POWER_TRACER_H + +#define CPU_UP 0 +#define CPU_DOWN 1 +#define CPU_SUSPEND 2 +#define CLUSTER_UP 3 +#define CLUSTER_DOWN 4 +#define CLUSTER_SUSPEND 5 + +void trace_power_flow(u_register_t mpidr, unsigned char mode); + +#endif /* POWER_TRACER_H */ + diff --git a/plat/mediatek/mt8183/include/scu.h b/plat/mediatek/mt8183/include/scu.h new file mode 100644 index 0000000..96b80c5 --- /dev/null +++ b/plat/mediatek/mt8183/include/scu.h @@ -0,0 +1,13 @@ +/* + * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef SCU_H +#define SCU_H + +void disable_scu(u_register_t mpidr); +void enable_scu(u_register_t mpidr); + +#endif /* SCU_H */ diff --git a/plat/mediatek/mt8183/include/sspm_reg.h b/plat/mediatek/mt8183/include/sspm_reg.h new file mode 100644 index 0000000..3f1ac86 --- /dev/null +++ b/plat/mediatek/mt8183/include/sspm_reg.h @@ -0,0 +1,41 @@ +/* + * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef __SSPM_REG_H__ +#define __SSPM_REG_H__ + +#include "platform_def.h" + +#define SSPM_CFGREG_RSV_RW_REG0 (SSPM_CFGREG_BASE + 0x0100) +#define SSPM_CFGREG_ACAO_INT_SET (SSPM_CFGREG_BASE + 0x00D8) +#define SSPM_CFGREG_ACAO_INT_CLR (SSPM_CFGREG_BASE + 0x00DC) +#define SSPM_CFGREG_ACAO_WAKEUP_EN (SSPM_CFGREG_BASE + 0x0204) + +#define STANDBYWFI_EN(n) (1 << (n + 8)) +#define GIC_IRQOUT_EN(n) (1 << (n + 0)) + +#define NF_MCDI_MBOX 19 +#define MCDI_MBOX_CLUSTER_0_CAN_POWER_OFF 0 +#define MCDI_MBOX_CLUSTER_1_CAN_POWER_OFF 1 +#define MCDI_MBOX_BUCK_POWER_OFF_MASK 2 +#define MCDI_MBOX_CLUSTER_0_ATF_ACTION_DONE 3 +#define MCDI_MBOX_CLUSTER_1_ATF_ACTION_DONE 4 +#define MCDI_MBOX_BOOTADDR 5 +#define MCDI_MBOX_PAUSE_ACTION 6 +#define MCDI_MBOX_AVAIL_CPU_MASK 7 +#define MCDI_MBOX_CPU_CLUSTER_PWR_STAT 8 +#define MCDI_MBOX_ACTION_STAT 9 +#define MCDI_MBOX_CLUSTER_0_CNT 10 +#define MCDI_MBOX_CLUSTER_1_CNT 11 +#define MCDI_MBOX_CPU_ISOLATION_MASK 12 +#define MCDI_MBOX_PAUSE_ACK 13 +#define MCDI_MBOX_PENDING_ON_EVENT 14 +#define MCDI_MBOX_PROF_CMD 15 +#define MCDI_MBOX_DRCC_CALI_DONE 16 +#define MCDI_MBOX_HP_CMD 17 +#define MCDI_MBOX_HP_ACK 18 + +#endif /* __SSPM_REG_H__ */ |