diff options
Diffstat (limited to 'plat/st/stm32mp2')
| -rw-r--r-- | plat/st/stm32mp2/aarch64/stm32mp2.S | 11 | ||||
| -rw-r--r-- | plat/st/stm32mp2/aarch64/stm32mp2.ld.S | 71 | ||||
| -rw-r--r-- | plat/st/stm32mp2/aarch64/stm32mp2_helper.S | 194 | ||||
| -rw-r--r-- | plat/st/stm32mp2/bl2_plat_setup.c | 26 | ||||
| -rw-r--r-- | plat/st/stm32mp2/include/boot_api.h | 406 | ||||
| -rw-r--r-- | plat/st/stm32mp2/include/plat_macros.S | 13 | ||||
| -rw-r--r-- | plat/st/stm32mp2/include/platform_def.h | 87 | ||||
| -rw-r--r-- | plat/st/stm32mp2/plat_bl2_mem_params_desc.c | 20 | ||||
| -rw-r--r-- | plat/st/stm32mp2/platform.mk | 52 | ||||
| -rw-r--r-- | plat/st/stm32mp2/stm32mp2_def.h | 222 |
10 files changed, 1102 insertions, 0 deletions
diff --git a/plat/st/stm32mp2/aarch64/stm32mp2.S b/plat/st/stm32mp2/aarch64/stm32mp2.S new file mode 100644 index 0000000..1866b8b --- /dev/null +++ b/plat/st/stm32mp2/aarch64/stm32mp2.S @@ -0,0 +1,11 @@ +/* + * Copyright (c) 2023, STMicroelectronics - All Rights Reserved + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +.section .bl2_image +.incbin BL2_BIN_PATH + +.section .dtb_image +.incbin DTB_BIN_PATH diff --git a/plat/st/stm32mp2/aarch64/stm32mp2.ld.S b/plat/st/stm32mp2/aarch64/stm32mp2.ld.S new file mode 100644 index 0000000..48bf424 --- /dev/null +++ b/plat/st/stm32mp2/aarch64/stm32mp2.ld.S @@ -0,0 +1,71 @@ +/* + * Copyright (c) 2023, STMicroelectronics - All Rights Reserved + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef STM32MP2_LD_S +#define STM32MP2_LD_S + +#include <lib/xlat_tables/xlat_tables_defs.h> +#include <platform_def.h> + +OUTPUT_FORMAT(PLATFORM_LINKER_FORMAT) +OUTPUT_ARCH(PLATFORM_LINKER_ARCH) + +ENTRY(__BL2_IMAGE_START__) + +MEMORY { + HEADER (rw) : ORIGIN = 0x00000000, LENGTH = STM32MP_HEADER_RESERVED_SIZE + RAM (rwx) : ORIGIN = STM32MP_BINARY_BASE, LENGTH = STM32MP_BINARY_SIZE +} + +SECTIONS +{ + /* + * TF mapping must conform to ROM code specification. + */ + .header : { + __HEADER_START__ = .; + KEEP(*(.header)) + . = ALIGN(4); + __HEADER_END__ = .; + } >HEADER + + . = STM32MP_BINARY_BASE; + .data . : { + . = ALIGN(PAGE_SIZE); + __DATA_START__ = .; + *(.data*) + + /* + * dtb. + * The strongest and only alignment contraint is MMU 4K page. + * Indeed as images below will be removed, 4K pages will be re-used. + */ + . = ( STM32MP_BL2_DTB_BASE - STM32MP_BINARY_BASE ); + __DTB_IMAGE_START__ = .; + *(.dtb_image*) + __DTB_IMAGE_END__ = .; + + /* + * bl2. + * The strongest and only alignment contraint is MMU 4K page. + * Indeed as images below will be removed, 4K pages will be re-used. + */ +#if SEPARATE_CODE_AND_RODATA + . = ( STM32MP_BL2_RO_BASE - STM32MP_BINARY_BASE ); +#else + . = ( STM32MP_BL2_BASE - STM32MP_BINARY_BASE ); +#endif + __BL2_IMAGE_START__ = .; + *(.bl2_image*) + __BL2_IMAGE_END__ = .; + + __DATA_END__ = .; + } >RAM + + __TF_END__ = .; + +} +#endif /* STM32MP2_LD_S */ diff --git a/plat/st/stm32mp2/aarch64/stm32mp2_helper.S b/plat/st/stm32mp2/aarch64/stm32mp2_helper.S new file mode 100644 index 0000000..66333ad --- /dev/null +++ b/plat/st/stm32mp2/aarch64/stm32mp2_helper.S @@ -0,0 +1,194 @@ +/* + * Copyright (c) 2023, STMicroelectronics - All Rights Reserved + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include <asm_macros.S> +#include <drivers/st/stm32_gpio.h> + +#include <platform_def.h> + +#define GPIO_TX_SHIFT (DEBUG_UART_TX_GPIO_PORT << 1) + + .globl platform_mem_init + .globl plat_secondary_cold_boot_setup + .globl plat_is_my_cpu_primary + .globl plat_crash_console_init + .globl plat_crash_console_flush + .globl plat_crash_console_putc + .globl plat_report_exception + +func platform_mem_init + /* Nothing to do, don't need to init SYSRAM */ + ret +endfunc platform_mem_init + + /* --------------------------------------------- + * void plat_secondary_cold_boot_setup (void); + * + * Set secondary core in WFI waiting for core reset. + * --------------------------------------------- + */ +func plat_secondary_cold_boot_setup + dsb sy + wfi + /* This shouldn't be reached */ + b . +endfunc plat_secondary_cold_boot_setup + + /* ---------------------------------------------- + * unsigned int plat_is_my_cpu_primary(void); + * This function checks if this is the primary CPU + * ---------------------------------------------- + */ +func plat_is_my_cpu_primary + mrs x0, mpidr_el1 + and x0, x0, #(MPIDR_CPU_MASK) + cmp x0, #STM32MP_PRIMARY_CPU + cset x0, eq + ret +endfunc plat_is_my_cpu_primary + + /* --------------------------------------------- + * int plat_crash_console_init(void) + * + * Initialize the crash console without a C Runtime stack. + * --------------------------------------------- + */ +func plat_crash_console_init + /* Reset UART peripheral */ + mov_imm x1, (RCC_BASE + DEBUG_UART_RST_REG) + ldr x2, =DEBUG_UART_RST_BIT + ldr x0, [x1] + orr x0, x0, x2 + str x0, [x1] +1: + ldr x0, [x1] + ands x2, x0, x2 + beq 1b + bic x2, x2, #DEBUG_UART_RST_BIT + str x2, [x1] +2: + ldr x0, [x1] + ands x2, x0, x2 + bne 2b + /* Enable GPIOs for UART TX */ + mov_imm x1, (RCC_BASE + DEBUG_UART_TX_GPIO_BANK_CLK_REG) + ldr w2, [x1] + /* Configure GPIO */ + orr w2, w2, #DEBUG_UART_TX_GPIO_BANK_CLK_EN + str w2, [x1] + mov_imm x1, DEBUG_UART_TX_GPIO_BANK_ADDRESS + /* Set GPIO mode alternate */ + ldr w2, [x1, #GPIO_MODE_OFFSET] + bic w2, w2, #(GPIO_MODE_MASK << GPIO_TX_SHIFT) + orr w2, w2, #(GPIO_MODE_ALTERNATE << GPIO_TX_SHIFT) + str w2, [x1, #GPIO_MODE_OFFSET] + /* Set GPIO speed low */ + ldr w2, [x1, #GPIO_SPEED_OFFSET] + bic w2, w2, #(GPIO_SPEED_MASK << GPIO_TX_SHIFT) + str w2, [x1, #GPIO_SPEED_OFFSET] + /* Set no-pull */ + ldr w2, [x1, #GPIO_PUPD_OFFSET] + bic w2, w2, #(GPIO_PULL_MASK << GPIO_TX_SHIFT) + str w2, [x1, #GPIO_PUPD_OFFSET] + /* Set alternate */ +#if DEBUG_UART_TX_GPIO_PORT >= GPIO_ALT_LOWER_LIMIT + ldr w2, [x1, #GPIO_AFRH_OFFSET] + bic w2, w2, #(GPIO_ALTERNATE_MASK << \ + ((DEBUG_UART_TX_GPIO_PORT - GPIO_ALT_LOWER_LIMIT) << 2)) + orr w2, w2, #(DEBUG_UART_TX_GPIO_ALTERNATE << \ + ((DEBUG_UART_TX_GPIO_PORT - GPIO_ALT_LOWER_LIMIT) << 2)) + str w2, [x1, #GPIO_AFRH_OFFSET] +#else + ldr w2, [x1, #GPIO_AFRL_OFFSET] + bic w2, w2, #(GPIO_ALTERNATE_MASK << (DEBUG_UART_TX_GPIO_PORT << 2)) + orr w2, w2, #(DEBUG_UART_TX_GPIO_ALTERNATE << (DEBUG_UART_TX_GPIO_PORT << 2)) + str w2, [x1, #GPIO_AFRL_OFFSET] +#endif + /* Clear UART clock flexgen divisors, keep enable bit */ + mov_imm x1, (RCC_BASE + DEBUG_UART_PREDIV_CFGR) + mov x2, #0 + str w2, [x1] + mov_imm x1, (RCC_BASE + DEBUG_UART_FINDIV_CFGR) + mov x2, #0x40 + str w2, [x1] + /* Enable UART clock, with its source */ + mov_imm x1, (RCC_BASE + DEBUG_UART_TX_CLKSRC_REG) + mov_imm w2, (DEBUG_UART_TX_CLKSRC | RCC_XBARxCFGR_XBARxEN) + str w2, [x1] + mov_imm x1, (RCC_BASE + DEBUG_UART_TX_EN_REG) + ldr w2, [x1] + orr w2, w2, #DEBUG_UART_TX_EN + str w2, [x1] + + mov_imm x0, STM32MP_DEBUG_USART_BASE + mov_imm x1, STM32MP_DEBUG_USART_CLK_FRQ + mov_imm x2, STM32MP_UART_BAUDRATE + b console_stm32_core_init +endfunc plat_crash_console_init + +func plat_crash_console_flush + mov_imm x0, STM32MP_DEBUG_USART_BASE + b console_stm32_core_flush +endfunc plat_crash_console_flush + +func plat_crash_console_putc + mov_imm x1, STM32MP_DEBUG_USART_BASE + cmp x0, #'\n' + b.ne 1f + mov x15, x30 + mov x0, #'\r' + bl console_stm32_core_putc + mov x30, x15 + mov x0, #'\n' +1: + b console_stm32_core_putc +endfunc plat_crash_console_putc + +#ifdef IMAGE_BL2 + /* --------------------------------------------- + * void plat_report_exception(unsigned int type) + * Function to report an unhandled exception + * with platform-specific means. + * --------------------------------------------- + */ +func plat_report_exception + mov x8, x30 + + adr x4, plat_err_str + bl asm_print_str + + adr x4, esr_el3_str + bl asm_print_str + + mrs x4, esr_el3 + bl asm_print_hex + + adr x4, elr_el3_str + bl asm_print_str + + mrs x4, elr_el3 + bl asm_print_hex + + adr x4, far_el3_str + bl asm_print_str + + mrs x4, far_el3 + bl asm_print_hex + + mov x30, x8 + ret +endfunc plat_report_exception + +.section .rodata.rev_err_str, "aS" +plat_err_str: + .asciz "\nPlatform exception reporting:" +esr_el3_str: + .asciz "\nESR_EL3: " +elr_el3_str: + .asciz "\nELR_EL3: " +far_el3_str: + .asciz "\nFAR_EL3: " +#endif /* IMAGE_BL2 */ diff --git a/plat/st/stm32mp2/bl2_plat_setup.c b/plat/st/stm32mp2/bl2_plat_setup.c new file mode 100644 index 0000000..0805756 --- /dev/null +++ b/plat/st/stm32mp2/bl2_plat_setup.c @@ -0,0 +1,26 @@ +/* + * Copyright (c) 2023, STMicroelectronics - All Rights Reserved + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include <cdefs.h> +#include <stdint.h> + +#include <stm32mp_common.h> + +void bl2_el3_early_platform_setup(u_register_t arg0 __unused, + u_register_t arg1 __unused, + u_register_t arg2 __unused, + u_register_t arg3 __unused) +{ + stm32mp_setup_early_console(); +} + +void bl2_platform_setup(void) +{ +} + +void bl2_el3_plat_arch_setup(void) +{ +} diff --git a/plat/st/stm32mp2/include/boot_api.h b/plat/st/stm32mp2/include/boot_api.h new file mode 100644 index 0000000..d3bed76 --- /dev/null +++ b/plat/st/stm32mp2/include/boot_api.h @@ -0,0 +1,406 @@ +/* + * Copyright (c) 2023, STMicroelectronics - All Rights Reserved + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef BOOT_API_H +#define BOOT_API_H + +#include <stdint.h> +#include <stdio.h> + +/* + * Exported constants + */ + +/* + * Boot Context related definitions + */ + +/* + * Possible value of boot context field 'auth_status' + */ +/* No authentication done */ +#define BOOT_API_CTX_AUTH_NO 0x0U +/* Authentication done and failed */ +#define BOOT_API_CTX_AUTH_FAILED 0x1U +/* Authentication done and succeeded */ +#define BOOT_API_CTX_AUTH_SUCCESS 0x2U + +/* + * Possible value of boot context field 'boot_interface_sel' + */ + +/* Value of field 'boot_interface_sel' when no boot occurred */ +#define BOOT_API_CTX_BOOT_INTERFACE_SEL_NO 0x0U + +/* Boot occurred on SD */ +#define BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_SD 0x1U + +/* Boot occurred on EMMC */ +#define BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_EMMC 0x2U + +/* Boot occurred on FMC */ +#define BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_NAND_FMC 0x3U + +/* Boot occurred on OSPI NOR */ +#define BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_NOR_SPI 0x4U + +/* Boot occurred on UART */ +#define BOOT_API_CTX_BOOT_INTERFACE_SEL_SERIAL_UART 0x5U + +/* Boot occurred on USB */ +#define BOOT_API_CTX_BOOT_INTERFACE_SEL_SERIAL_USB 0x6U + +/* Boot occurred on OSPI NAND */ +#define BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_NAND_SPI 0x7U + +/* Boot occurred on HyperFlash QSPI */ +#define BOOT_API_CTX_BOOT_INTERFACE_SEL_HYPERFLASH_OSPI 0x8U + +/* + * Possible value of boot context field 'emmc_xfer_status' + */ +#define BOOT_API_CTX_EMMC_XFER_STATUS_NOT_STARTED 0x0U +#define BOOT_API_CTX_EMMC_XFER_STATUS_DATAEND_DETECTED 0x1U +#define BOOT_API_CTX_EMMC_XFER_STATUS_XFER_DATA_TIMEOUT 0x2U + +/* + * Possible value of boot context field 'emmc_error_status' + */ +#define BOOT_API_CTX_EMMC_ERROR_STATUS_NONE 0x0U +#define BOOT_API_CTX_EMMC_ERROR_STATUS_CMD_TIMEOUT 0x1U +#define BOOT_API_CTX_EMMC_ERROR_STATUS_ACK_TIMEOUT 0x2U +#define BOOT_API_CTX_EMMC_ERROR_STATUS_DATA_CRC_FAIL 0x3U +#define BOOT_API_CTX_EMMC_ERROR_STATUS_NOT_ENOUGH_BOOT_DATA_RX 0x4U +#define BOOT_API_CTX_EMMC_ERROR_STATUS_HEADER_NOT_FOUND 0x5U +#define BOOT_API_CTX_EMMC_ERROR_STATUS_HEADER_SIZE_ZERO 0x6U +#define BOOT_API_CTX_EMMC_ERROR_STATUS_IMAGE_NOT_COMPLETE 0x7U +#define BOOT_API_CTX_EMMC_ERROR_STATUS_ACK_ERROR 0x8U + +/* Definitions relative to 'p_rom_version_info->platform_type_ver' field */ +#define BOOT_API_CTX_ROM_VERSION_PLAT_VER_IC_EMU_FPGA 0xAA +#define BOOT_API_CTX_ROM_VERSION_PLAT_VER_FPGA_ONLY 0xBB + +/* Image Header related definitions */ + +/* Definition of header version */ +#define BOOT_API_HEADER_VERSION 0x00020000U + +/* + * Magic number used to detect header in memory + * Its value must be 'S' 'T' 'M' 0x32, i.e 0x324D5453 as field + * 'bootapi_image_header_t.magic' + * This identifies the start of a boot image. + */ +#define BOOT_API_IMAGE_HEADER_MAGIC_NB 0x324D5453U + +/* Definitions related to Authentication used in image header structure */ +#define BOOT_API_ECDSA_PUB_KEY_LEN_IN_BYTES 64 +#define BOOT_API_ECDSA_SIGNATURE_LEN_IN_BYTES 64 +#define BOOT_API_SHA256_DIGEST_SIZE_IN_BYTES 32 + +/* Possible values of the field 'boot_api_image_header_t.ecc_algo_type' */ +#define BOOT_API_ECDSA_ALGO_TYPE_P256NIST 1 +#define BOOT_API_ECDSA_ALGO_TYPE_BRAINPOOL256 2 + +/* + * Extension headers related definitions + */ +/* 'bootapi_image_header_t.extension_flag' used for authentication feature */ +#define BOOT_API_AUTHENTICATION_EXTENSION_BIT BIT(0) +/* 'bootapi_image_header_t.extension_flag' used for FSBL decryption feature */ +#define BOOT_API_FSBL_DECRYPTION_EXTENSION_BIT BIT(1) +/* 'bootapi_image_header_t.extension_flag' used for padding header feature */ +#define BOOT_API_PADDING_EXTENSION_BIT BIT(31) +/* + * mask of bits of field 'bootapi_image_header_t.extension_flag' + * used for extension headers + */ +#define BOOT_API_ALL_EXTENSIONS_MASK \ + (BOOT_API_AUTHENTICATION_EXTENSION_BIT | \ + BOOT_API_FSBL_DECRYPTION_EXTENSION_BIT | \ + BOOT_API_PADDING_EXTENSION_BIT) +/* + * Magic number of FSBL decryption extension header + * The value shall gives the four bytes 'S','T',0x00,0x01 in memory + */ +#define BOOT_API_FSBL_DECRYPTION_HEADER_MAGIC_NB 0x01005453U + +/* + * Magic number of PKH revocation extension header + * The value shall gives the four bytes 'S','T',0x00,0x02 in memory + */ +#define BOOT_API_AUTHENTICATION_HEADER_MAGIC_NB 0x02005453U + +/* Max number of ECDSA public key hash in table */ +#define BOOT_API_AUTHENTICATION_NB_PKH_MAX 8U + +/* ECDSA public key hash table size in bytes */ +#define BOOT_API_AUTHENTICATION_TABLE_SIZE_BYTES \ + (BOOT_API_AUTHENTICATION_NB_PKH_MAX * \ + BOOT_API_SHA256_DIGEST_SIZE_IN_BYTES) + +/* + * Magic number of padding extension header + * The value shall gives the four bytes 'S','T',0xFF,0xFF in memory + */ +#define BOOT_API_PADDING_HEADER_MAGIC_NB 0xFFFF5453U + +/* + * Related to binaryType + * 0x00: U-Boot + * 0x10-0x1F: TF-A + * 0x20-0X2F: OPTEE + * 0x30: CM33 image + */ +#define BOOT_API_IMAGE_TYPE_UBOOT 0x0 +#define BOOT_API_IMAGE_TYPE_M33 0x30 + +/* + * Cores secure magic numbers + * Constant to be stored in bakcup register + * BOOT_API_MAGIC_NUMBER_TAMP_BCK_REG_IDX + */ +#define BOOT_API_A35_CORE0_MAGIC_NUMBER 0xCA7FACE0U +#define BOOT_API_A35_CORE1_MAGIC_NUMBER 0xCA7FACE1U + +/* + * TAMP_BCK9R register index + * This register is used to write a Magic Number in order to restart + * Cortex A35 Core 1 and make it execute @ branch address from TAMP_BCK5R + */ +#define BOOT_API_CORE1_MAGIC_NUMBER_TAMP_BCK_REG_IDX 9U + +/* + * TAMP_BCK10R register index + * This register is used to contain the branch address of + * Cortex A35 Core 1 when restarted by a TAMP_BCK4R magic number writing + */ +#define BOOT_API_CORE1_BRANCH_ADDRESS_TAMP_BCK_REG_IDX 10U + +/* + * Possible value of boot context field 'hse_clock_value_in_hz' + */ +#define BOOT_API_CTX_HSE_CLOCK_VALUE_UNDEFINED 0U +#define BOOT_API_CTX_HSE_CLOCK_VALUE_19_2_MHZ 19200000U +#define BOOT_API_CTX_HSE_CLOCK_VALUE_24_MHZ 24000000U +#define BOOT_API_CTX_HSE_CLOCK_VALUE_25_MHZ 25000000U +#define BOOT_API_CTX_HSE_CLOCK_VALUE_26_MHZ 26000000U +#define BOOT_API_CTX_HSE_CLOCK_VALUE_40_MHZ 40000000U +#define BOOT_API_CTX_HSE_CLOCK_VALUE_48_MHZ 48000000U + +/* + * Possible value of boot context field 'boot_partition_used_toboot' + */ +#define BOOT_API_CTX_BOOT_PARTITION_UNDEFINED 0U + +/* Used FSBL1 to boot */ +#define BOOT_API_CTX_BOOT_PARTITION_FSBL1 1U + +/* Used FSBL2 to boot */ +#define BOOT_API_CTX_BOOT_PARTITION_FSBL2 2U + +#define BOOT_API_RETURN_OK 0x66U + +/* + * Possible values of boot context field + * 'ssp_config_ptr_in->ssp_cmd' + */ +/* 'K' 'B' 'U' 'P' -.> 'PUBK' */ +#define BOOT_API_CTX_SSP_CMD_CALC_CHIP_PUBK 0x4B425550 + +/* + * Exported types + */ + +/* + * bootROM version information structure definition + * Total size = 24 bytes = 6 uint32_t + */ +typedef struct { + /* Chip Version */ + uint32_t chip_ver; + + /* Cut version within a fixed chip version */ + uint32_t cut_ver; + + /* Version of ROM Mask within a fixed cut version */ + uint32_t rom_mask_ver; + + /* Internal Version of bootROM code */ + uint32_t bootrom_ver; + + /* Version of bootROM adapted */ + uint32_t for_chip_design_rtl_ver; + + /* Restriction on compiled platform when it applies */ + uint32_t platform_type_ver; +} boot_api_rom_version_info_t; + +/* + * Boot Context related definitions + */ + +/* + * Boot core boot configuration structure + * Specifies all items of the secure boot configuration + * Memory and peripheral part. + */ +typedef struct { + /* Boot partition: ie FSBL partition on which the boot was successful */ + uint32_t boot_partition_used_toboot; + + uint32_t reserved1[3]; + + /* + * Information specific to an SD boot + * Updated each time an SD boot is at least attempted, + * even if not successful + * Note : This is useful to understand why an SD boot failed + * in particular + */ + uint32_t sd_err_internal_timeout_cnt; + uint32_t sd_err_dcrc_fail_cnt; + uint32_t sd_err_dtimeout_cnt; + uint32_t sd_err_ctimeout_cnt; + uint32_t sd_err_ccrc_fail_cnt; + uint32_t sd_overall_retry_cnt; + /* + * Information specific to an eMMC boot + * Updated each time an eMMC boot is at least attempted, + * even if not successful + * Note : This is useful to understand why an eMMC boot failed + * in particular + */ + uint32_t emmc_xfer_status; + uint32_t emmc_error_status; + uint32_t emmc_nbbytes_rxcopied_tosysram_download_area; + + uint32_t reserved[4]; + /* + * Boot interface used to boot : take values from defines + * BOOT_API_CTX_BOOT_INTERFACE_SEL_XXX above + */ + uint16_t boot_interface_selected; + uint16_t boot_interface_instance; + + uint32_t hse_clock_value_in_hz; + + uint32_t nand_fsbl_first_block; + + /* + * Returned authentication status : take values from defines + * BOOT_API_CTX_AUTH_XXX above + */ + uint32_t auth_status; + + /* Pointer on ROM constant containing ROM information */ + const boot_api_rom_version_info_t *p_rom_version_info; +} __packed boot_api_context_t; + +/* + * Image Header related definitions + */ + +/* + * Structure used to define the common Header format used for FSBL, xloader, + * ... and in particular used by bootROM for FSBL header readout. + * FSBL header size is 256 Bytes = 0x100 + */ +typedef struct { + /* BOOT_API_IMAGE_HEADER_MAGIC_NB */ + uint32_t magic; + uint8_t image_signature[BOOT_API_ECDSA_SIGNATURE_LEN_IN_BYTES]; + /* + * Checksum of payload + * 32-bit sum all payload bytes considered as 8 bit unsigned + * numbers, discarding any overflow bits. + * Use to check UART/USB downloaded image integrity when signature + * is not used + */ + uint32_t payload_checksum; + /* Image header version : should have value BOOT_API_HEADER_VERSION */ + uint32_t header_version; + /* Image length in bytes */ + uint32_t image_length; + /* + * Image Entry point address : should be in the SYSRAM area + * and at least within the download area range + */ + uint32_t image_entry_point; + /* Reserved */ + uint32_t reserved1; + /* + * Image load address : not used by bootROM but to be consistent + * with header format for other packages (xloader, ...) + */ + uint32_t load_address; + /* Reserved */ + uint32_t reserved2; + /* Image version to be compared by bootROM with FSBL_A or FSBL_M version + * counter value in OTP prior executing the downloaded image + */ + uint32_t image_version; + /* + * Extension flags : + * + * Bit 0 : Authentication extension header + * value 0 : No signature check request + * Bit 1 : Encryption extension header + * Bit 2 : Padding extension header + */ + uint32_t extension_flags; + /* Length in bytes of all extension headers */ + uint32_t extension_headers_length; + /* Add binary type information */ + uint32_t binary_type; + /* Pad up to 128 byte total size */ + uint8_t pad[16]; + /* Followed by extension header */ + uint8_t ext_header[]; +} __packed boot_api_image_header_t; + +typedef uint8_t boot_api_sha256_t[BOOT_API_SHA256_DIGEST_SIZE_IN_BYTES]; + +typedef struct { + /* Extension header type: + * BOOT_API_FSBL_DECRYPTION_HEADER_MAGIC_NB or + * BOOT_API_AUTHENTICATION_HEADER_MAGIC_NB + * BOOT_API_PADDING_HEADER_MAGIC_NB + */ + uint32_t type; + /* Extension header len in byte */ + uint32_t len; + /* parameters of this extension */ + uint8_t params[]; +} __packed boot_extension_header_t; + +typedef struct { + /* Idx of ECDSA public key to be used in table */ + uint32_t pk_idx; + /* Number of ECDSA public key in table */ + uint32_t nb_pk; + /* + * Type of ECC algorithm to use : + * value 1 : for P-256 NIST algorithm + * value 2 : for Brainpool 256 algorithm + * See definitions 'BOOT_API_ECDSA_ALGO_TYPE_XXX' above. + */ + uint32_t ecc_algo_type; + /* ECDSA public key to be used to check signature. */ + uint8_t ecc_pubk[BOOT_API_ECDSA_PUB_KEY_LEN_IN_BYTES]; + /* table of Hash of Algo+ECDSA public key */ + boot_api_sha256_t pk_hashes[]; +} __packed boot_ext_header_params_authentication_t; + +typedef struct { + /* Size of encryption key (128 or 256) */ + uint32_t key_size; + uint32_t derivation_cont; + /* 128 msb bits of plain payload SHA256 */ + uint32_t hash[4]; +} __packed boot_ext_header_params_encrypted_fsbl_t; + +#endif /* BOOT_API_H */ diff --git a/plat/st/stm32mp2/include/plat_macros.S b/plat/st/stm32mp2/include/plat_macros.S new file mode 100644 index 0000000..e5be2c8 --- /dev/null +++ b/plat/st/stm32mp2/include/plat_macros.S @@ -0,0 +1,13 @@ +/* + * Copyright (c) 2023, STMicroelectronics - All Rights Reserved + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef PLAT_MACROS_S +#define PLAT_MACROS_S + + .macro plat_crash_print_regs + .endm + +#endif /* PLAT_MACROS_S */ diff --git a/plat/st/stm32mp2/include/platform_def.h b/plat/st/stm32mp2/include/platform_def.h new file mode 100644 index 0000000..404c384 --- /dev/null +++ b/plat/st/stm32mp2/include/platform_def.h @@ -0,0 +1,87 @@ +/* + * Copyright (c) 2023, STMicroelectronics - All Rights Reserved + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef PLATFORM_DEF_H +#define PLATFORM_DEF_H + +#include <arch.h> +#include <lib/utils_def.h> +#include <plat/common/common_def.h> + +#include "../stm32mp2_def.h" + +/******************************************************************************* + * Generic platform constants + ******************************************************************************/ + +/* Size of cacheable stacks */ +#define PLATFORM_STACK_SIZE 0xC00 + +#define STM32MP_PRIMARY_CPU U(0x0) +#define STM32MP_SECONDARY_CPU U(0x1) + +#define MAX_IO_DEVICES U(4) +#define MAX_IO_HANDLES U(4) +#define MAX_IO_BLOCK_DEVICES U(1) +#define MAX_IO_MTD_DEVICES U(1) + +#define PLATFORM_CLUSTER_COUNT U(1) +#define PLATFORM_CORE_COUNT U(2) +#define PLATFORM_MAX_CPUS_PER_CLUSTER U(2) + +#define PLAT_MAX_PWR_LVL U(5) +#define PLAT_MAX_CPU_SUSPEND_PWR_LVL U(5) +#define PLAT_NUM_PWR_DOMAINS U(7) + +/* Local power state for power domains in Run state. */ +#define STM32MP_LOCAL_STATE_RUN U(0) +/* Local power state for retention. */ +#define STM32MP_LOCAL_STATE_RET U(1) +#define STM32MP_LOCAL_STATE_LP U(2) +#define PLAT_MAX_RET_STATE STM32MP_LOCAL_STATE_LP +/* Local power state for OFF/power-down. */ +#define STM32MP_LOCAL_STATE_OFF U(3) +#define PLAT_MAX_OFF_STATE STM32MP_LOCAL_STATE_OFF + +/* Macros to parse the state information from State-ID (recommended encoding) */ +#define PLAT_LOCAL_PSTATE_WIDTH U(4) +#define PLAT_LOCAL_PSTATE_MASK GENMASK(PLAT_LOCAL_PSTATE_WIDTH - 1U, 0) + +/******************************************************************************* + * BL2 specific defines. + ******************************************************************************/ +/* + * Put BL2 just below BL3-1. BL2_BASE is calculated using the current BL2 debug + * size plus a little space for growth. + */ +#define BL2_BASE STM32MP_BL2_BASE +#define BL2_LIMIT (STM32MP_BL2_BASE + \ + STM32MP_BL2_SIZE) + +/******************************************************************************* + * BL33 specific defines. + ******************************************************************************/ +#define BL33_BASE STM32MP_BL33_BASE + +/******************************************************************************* + * Platform specific page table and MMU setup constants + ******************************************************************************/ +#define PLAT_PHY_ADDR_SPACE_SIZE (ULL(1) << 33) +#define PLAT_VIRT_ADDR_SPACE_SIZE (ULL(1) << 33) + +/******************************************************************************* + * Declarations and constants to access the mailboxes safely. Each mailbox is + * aligned on the biggest cache line size in the platform. This is known only + * to the platform as it might have a combination of integrated and external + * caches. Such alignment ensures that two maiboxes do not sit on the same cache + * line at any cache level. They could belong to different cpus/clusters & + * get written while being protected by different locks causing corruption of + * a valid mailbox address. + ******************************************************************************/ +#define CACHE_WRITEBACK_SHIFT 6 +#define CACHE_WRITEBACK_GRANULE (U(1) << CACHE_WRITEBACK_SHIFT) + +#endif /* PLATFORM_DEF_H */ diff --git a/plat/st/stm32mp2/plat_bl2_mem_params_desc.c b/plat/st/stm32mp2/plat_bl2_mem_params_desc.c new file mode 100644 index 0000000..630cc84 --- /dev/null +++ b/plat/st/stm32mp2/plat_bl2_mem_params_desc.c @@ -0,0 +1,20 @@ +/* + * Copyright (c) 2023, STMicroelectronics - All Rights Reserved + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include <common/desc_image_load.h> + +/******************************************************************************* + * Following descriptor provides BL image/ep information that gets used + * by BL2 to load the images and also subset of this information is + * passed to next BL image. The image loading sequence is managed by + * populating the images in required loading order. The image execution + * sequence is managed by populating the `next_handoff_image_id` with + * the next executable image id. + ******************************************************************************/ +static bl_mem_params_node_t bl2_mem_params_descs[] = { +}; + +REGISTER_BL_IMAGE_DESCS(bl2_mem_params_descs) diff --git a/plat/st/stm32mp2/platform.mk b/plat/st/stm32mp2/platform.mk new file mode 100644 index 0000000..6ea4638 --- /dev/null +++ b/plat/st/stm32mp2/platform.mk @@ -0,0 +1,52 @@ +# +# Copyright (c) 2023, STMicroelectronics - All Rights Reserved +# +# SPDX-License-Identifier: BSD-3-Clause +# + +include plat/st/common/common.mk + +CRASH_REPORTING := 1 +ENABLE_PIE := 1 +PROGRAMMABLE_RESET_ADDRESS := 1 + +# Default Device tree +DTB_FILE_NAME ?= stm32mp257f-ev1.dtb + +STM32MP25 := 1 + +# STM32 image header version v2.2 +STM32_HEADER_VERSION_MAJOR := 2 +STM32_HEADER_VERSION_MINOR := 2 + +# Number of TF-A copies in the device +STM32_TF_A_COPIES := 2 + +# PLAT_PARTITION_MAX_ENTRIES must take care of STM32_TF-A_COPIES and other partitions +# such as metadata (2) and fsbl-m (2) to find all the FIP partitions (default is 2). +PLAT_PARTITION_MAX_ENTRIES := $(shell echo $$(($(STM32_TF_A_COPIES) + 6))) + +# Device tree +BL2_DTSI := stm32mp25-bl2.dtsi +FDT_SOURCES := $(addprefix ${BUILD_PLAT}/fdts/, $(patsubst %.dtb,%-bl2.dts,$(DTB_FILE_NAME))) + +# Macros and rules to build TF binary +STM32_TF_STM32 := $(addprefix ${BUILD_PLAT}/tf-a-, $(patsubst %.dtb,%.stm32,$(DTB_FILE_NAME))) +STM32_LD_FILE := plat/st/stm32mp2/${ARCH}/stm32mp2.ld.S +STM32_BINARY_MAPPING := plat/st/stm32mp2/${ARCH}/stm32mp2.S + +# STM32MP2x is based on Cortex-A35, which is Armv8.0, and does not support BTI +# Disable mbranch-protection to avoid adding useless code +TF_CFLAGS += -mbranch-protection=none + +# Include paths and source files +PLAT_INCLUDES += -Iplat/st/stm32mp2/include/ + +PLAT_BL_COMMON_SOURCES += lib/cpus/${ARCH}/cortex_a35.S +PLAT_BL_COMMON_SOURCES += drivers/st/uart/${ARCH}/stm32_console.S +PLAT_BL_COMMON_SOURCES += plat/st/stm32mp2/${ARCH}/stm32mp2_helper.S + +BL2_SOURCES += plat/st/stm32mp2/plat_bl2_mem_params_desc.c +BL2_SOURCES += plat/st/stm32mp2/bl2_plat_setup.c + +include plat/st/common/common_rules.mk diff --git a/plat/st/stm32mp2/stm32mp2_def.h b/plat/st/stm32mp2/stm32mp2_def.h new file mode 100644 index 0000000..66514fc --- /dev/null +++ b/plat/st/stm32mp2/stm32mp2_def.h @@ -0,0 +1,222 @@ +/* + * Copyright (c) 2023, STMicroelectronics - All Rights Reserved + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef STM32MP2_DEF_H +#define STM32MP2_DEF_H + +#include <common/tbbr/tbbr_img_def.h> +#ifndef __ASSEMBLER__ +#include <drivers/st/bsec.h> +#endif +#include <drivers/st/stm32mp25_rcc.h> +#include <dt-bindings/clock/stm32mp25-clks.h> +#include <dt-bindings/clock/stm32mp25-clksrc.h> +#include <dt-bindings/reset/stm32mp25-resets.h> + +#ifndef __ASSEMBLER__ +#include <boot_api.h> +#include <stm32mp_common.h> +#include <stm32mp_dt.h> +#include <stm32mp_shared_resources.h> +#endif + +/******************************************************************************* + * STM32MP2 memory map related constants + ******************************************************************************/ +#define STM32MP_SYSRAM_BASE U(0x0E000000) +#define STM32MP_SYSRAM_SIZE U(0x00040000) + +#define STM32MP_SEC_SYSRAM_BASE STM32MP_SYSRAM_BASE +#define STM32MP_SEC_SYSRAM_SIZE STM32MP_SYSRAM_SIZE + +/* DDR configuration */ +#define STM32MP_DDR_BASE U(0x80000000) +#define STM32MP_DDR_MAX_SIZE UL(0x100000000) /* Max 4GB */ + +/* DDR power initializations */ +#ifndef __ASSEMBLER__ +enum ddr_type { + STM32MP_DDR3, + STM32MP_DDR4, + STM32MP_LPDDR4 +}; +#endif + +/* Section used inside TF binaries */ +#define STM32MP_PARAM_LOAD_SIZE U(0x00002400) /* 9 KB for param */ +/* 512 Octets reserved for header */ +#define STM32MP_HEADER_SIZE U(0x00000200) +#define STM32MP_HEADER_BASE (STM32MP_SEC_SYSRAM_BASE + \ + STM32MP_PARAM_LOAD_SIZE) + +/* round_up(STM32MP_PARAM_LOAD_SIZE + STM32MP_HEADER_SIZE, PAGE_SIZE) */ +#define STM32MP_HEADER_RESERVED_SIZE U(0x3000) + +#define STM32MP_BINARY_BASE (STM32MP_SEC_SYSRAM_BASE + \ + STM32MP_PARAM_LOAD_SIZE + \ + STM32MP_HEADER_SIZE) + +#define STM32MP_BINARY_SIZE (STM32MP_SEC_SYSRAM_SIZE - \ + (STM32MP_PARAM_LOAD_SIZE + \ + STM32MP_HEADER_SIZE)) + +#define STM32MP_BL2_SIZE U(0x0002A000) /* 168 KB for BL2 */ + +#define STM32MP_BL2_BASE (STM32MP_SEC_SYSRAM_BASE + \ + STM32MP_SEC_SYSRAM_SIZE - \ + STM32MP_BL2_SIZE) + +/* BL2 and BL32/sp_min require 4 tables */ +#define MAX_XLAT_TABLES U(4) /* 16 KB for mapping */ + +/* + * MAX_MMAP_REGIONS is usually: + * BL stm32mp2_mmap size + mmap regions in *_plat_arch_setup + */ +#define MAX_MMAP_REGIONS 6 + +/* DTB initialization value */ +#define STM32MP_BL2_DTB_SIZE U(0x00005000) /* 20 KB for DTB */ + +#define STM32MP_BL2_DTB_BASE (STM32MP_BL2_BASE - \ + STM32MP_BL2_DTB_SIZE) + +#define STM32MP_BL33_BASE (STM32MP_DDR_BASE + U(0x04000000)) +#define STM32MP_BL33_MAX_SIZE U(0x400000) + +/******************************************************************************* + * STM32MP2 RCC + ******************************************************************************/ +#define RCC_BASE U(0x44200000) + +/******************************************************************************* + * STM32MP2 PWR + ******************************************************************************/ +#define PWR_BASE U(0x44210000) + +/******************************************************************************* + * STM32MP2 GPIO + ******************************************************************************/ +#define GPIOA_BASE U(0x44240000) +#define GPIOB_BASE U(0x44250000) +#define GPIOC_BASE U(0x44260000) +#define GPIOD_BASE U(0x44270000) +#define GPIOE_BASE U(0x44280000) +#define GPIOF_BASE U(0x44290000) +#define GPIOG_BASE U(0x442A0000) +#define GPIOH_BASE U(0x442B0000) +#define GPIOI_BASE U(0x442C0000) +#define GPIOJ_BASE U(0x442D0000) +#define GPIOK_BASE U(0x442E0000) +#define GPIOZ_BASE U(0x46200000) +#define GPIO_BANK_OFFSET U(0x10000) + +#define STM32MP_GPIOS_PIN_MAX_COUNT 16 +#define STM32MP_GPIOZ_PIN_MAX_COUNT 8 + +/******************************************************************************* + * STM32MP2 UART + ******************************************************************************/ +#define USART1_BASE U(0x40330000) +#define USART2_BASE U(0x400E0000) +#define USART3_BASE U(0x400F0000) +#define UART4_BASE U(0x40100000) +#define UART5_BASE U(0x40110000) +#define USART6_BASE U(0x40220000) +#define UART7_BASE U(0x40370000) +#define UART8_BASE U(0x40380000) +#define UART9_BASE U(0x402C0000) +#define STM32MP_NB_OF_UART U(9) + +/* For UART crash console */ +#define STM32MP_DEBUG_USART_CLK_FRQ 64000000 +/* USART2 on HSI@64MHz, TX on GPIOA4 Alternate 6 */ +#define STM32MP_DEBUG_USART_BASE USART2_BASE +#define DEBUG_UART_TX_GPIO_BANK_ADDRESS GPIOA_BASE +#define DEBUG_UART_TX_GPIO_BANK_CLK_REG RCC_GPIOACFGR +#define DEBUG_UART_TX_GPIO_BANK_CLK_EN RCC_GPIOxCFGR_GPIOxEN +#define DEBUG_UART_TX_GPIO_PORT 4 +#define DEBUG_UART_TX_GPIO_ALTERNATE 6 +#define DEBUG_UART_TX_CLKSRC_REG RCC_XBAR8CFGR +#define DEBUG_UART_TX_CLKSRC XBAR_SRC_HSI +#define DEBUG_UART_TX_EN_REG RCC_USART2CFGR +#define DEBUG_UART_TX_EN RCC_UARTxCFGR_UARTxEN +#define DEBUG_UART_RST_REG RCC_USART2CFGR +#define DEBUG_UART_RST_BIT RCC_UARTxCFGR_UARTxRST +#define DEBUG_UART_PREDIV_CFGR RCC_PREDIV8CFGR +#define DEBUG_UART_FINDIV_CFGR RCC_FINDIV8CFGR + +/******************************************************************************* + * STM32MP2 SDMMC + ******************************************************************************/ +#define STM32MP_SDMMC1_BASE U(0x48220000) +#define STM32MP_SDMMC2_BASE U(0x48230000) +#define STM32MP_SDMMC3_BASE U(0x48240000) + +/******************************************************************************* + * STM32MP2 TAMP + ******************************************************************************/ +#define PLAT_MAX_TAMP_INT U(5) +#define PLAT_MAX_TAMP_EXT U(3) +#define TAMP_BASE U(0x46010000) +#define TAMP_SMCR (TAMP_BASE + U(0x20)) +#define TAMP_BKP_REGISTER_BASE (TAMP_BASE + U(0x100)) +#define TAMP_BKP_REG_CLK CK_BUS_RTC +#define TAMP_BKP_SEC_NUMBER U(10) +#define TAMP_COUNTR U(0x40) + +#if !(defined(__LINKER__) || defined(__ASSEMBLER__)) +static inline uintptr_t tamp_bkpr(uint32_t idx) +{ + return TAMP_BKP_REGISTER_BASE + (idx << 2); +} +#endif + +/******************************************************************************* + * STM32MP2 DDRCTRL + ******************************************************************************/ +#define DDRCTRL_BASE U(0x48040000) + +/******************************************************************************* + * STM32MP2 DDRDBG + ******************************************************************************/ +#define DDRDBG_BASE U(0x48050000) + +/******************************************************************************* + * STM32MP2 DDRPHYC + ******************************************************************************/ +#define DDRPHYC_BASE U(0x48C00000) + +/******************************************************************************* + * Miscellaneous STM32MP1 peripherals base address + ******************************************************************************/ +#define BSEC_BASE U(0x44000000) +#define DBGMCU_BASE U(0x4A010000) +#define HASH_BASE U(0x42010000) +#define RTC_BASE U(0x46000000) +#define STGEN_BASE U(0x48080000) +#define SYSCFG_BASE U(0x44230000) + +/******************************************************************************* + * REGULATORS + ******************************************************************************/ +/* 3 PWR + 1 VREFBUF + 14 PMIC regulators + 1 FIXED */ +#define PLAT_NB_RDEVS U(19) +/* 2 FIXED */ +#define PLAT_NB_FIXED_REGUS U(2) +/* No GPIO regu */ +#define PLAT_NB_GPIO_REGUS U(0) + +/******************************************************************************* + * Device Tree defines + ******************************************************************************/ +#define DT_BSEC_COMPAT "st,stm32mp25-bsec" +#define DT_DDR_COMPAT "st,stm32mp2-ddr" +#define DT_PWR_COMPAT "st,stm32mp25-pwr" +#define DT_RCC_CLK_COMPAT "st,stm32mp25-rcc" +#define DT_UART_COMPAT "st,stm32h7-uart" + +#endif /* STM32MP2_DEF_H */ |