diff options
Diffstat (limited to 'plat/xilinx/zynqmp/include')
| -rw-r--r-- | plat/xilinx/zynqmp/include/custom_svc.h | 20 | ||||
| -rw-r--r-- | plat/xilinx/zynqmp/include/plat_ipi.h | 58 | ||||
| -rw-r--r-- | plat/xilinx/zynqmp/include/plat_macros.S | 28 | ||||
| -rw-r--r-- | plat/xilinx/zynqmp/include/plat_pm_common.h | 25 | ||||
| -rw-r--r-- | plat/xilinx/zynqmp/include/plat_private.h | 41 | ||||
| -rw-r--r-- | plat/xilinx/zynqmp/include/platform_def.h | 176 | ||||
| -rw-r--r-- | plat/xilinx/zynqmp/include/zynqmp_def.h | 349 |
7 files changed, 697 insertions, 0 deletions
diff --git a/plat/xilinx/zynqmp/include/custom_svc.h b/plat/xilinx/zynqmp/include/custom_svc.h new file mode 100644 index 0000000..242f3eb --- /dev/null +++ b/plat/xilinx/zynqmp/include/custom_svc.h @@ -0,0 +1,20 @@ +/* + * Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef CUSTOM_SVC_H +#define CUSTOM_SVC_H + +#define ZYNQMP_SIP_SVC_CUSTOM U(0x82002000) +#define ZYNQMP_SIP_SVC64_CUSTOM U(0xC2002000) + +uint64_t custom_smc_handler(uint32_t smc_fid, uint64_t x1, uint64_t x2, + uint64_t x3, uint64_t x4, void *cookie, + void *handle, uint64_t flags); + +void custom_early_setup(void); +void custom_mmap_add(void); +void custom_runtime_setup(void); + +#endif /* CUSTOM_SVC_H */ diff --git a/plat/xilinx/zynqmp/include/plat_ipi.h b/plat/xilinx/zynqmp/include/plat_ipi.h new file mode 100644 index 0000000..4007b91 --- /dev/null +++ b/plat/xilinx/zynqmp/include/plat_ipi.h @@ -0,0 +1,58 @@ +/* + * Copyright (c) 2017-2018, Arm Limited and Contributors. All rights reserved. + * Copyright (c) 2019-2022, Xilinx, Inc. All rights reserved. + * Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* ZynqMP IPI management enums and defines */ + +#ifndef PLAT_IPI_H +#define PLAT_IPI_H + +#include <stdint.h> +#include <ipi.h> + +/********************************************************************* + * IPI agent IDs macros + ********************************************************************/ +#define IPI_ID_APU 0U +#define IPI_ID_RPU0 1U +#define IPI_ID_RPU1 2U +#define IPI_ID_PMU0 3U +#define IPI_ID_PMU1 4U +#define IPI_ID_PMU2 5U +#define IPI_ID_PMU3 6U +#define IPI_ID_PL0 7U +#define IPI_ID_PL1 8U +#define IPI_ID_PL2 9U +#define IPI_ID_PL3 10U + +/********************************************************************* + * IPI message buffers + ********************************************************************/ +#define IPI_BUFFER_BASEADDR 0xFF990000U + +#define IPI_LOCAL_ID IPI_ID_APU +#define IPI_REMOTE_ID IPI_ID_PMU0 + +#define IPI_BUFFER_LOCAL_BASE (IPI_BUFFER_BASEADDR + 0x400U) +#define IPI_BUFFER_REMOTE_BASE (IPI_BUFFER_BASEADDR + 0xE00U) + +#define IPI_BUFFER_TARGET_LOCAL_OFFSET 0x80U +#define IPI_BUFFER_TARGET_REMOTE_OFFSET 0x1C0U + +#define IPI_BUFFER_MAX_WORDS 8U + +#define IPI_BUFFER_REQ_OFFSET 0x0U +#define IPI_BUFFER_RESP_OFFSET 0x20U + +/********************************************************************* + * Platform specific IPI API declarations + ********************************************************************/ + +/* Configure IPI table for zynqmp */ +void zynqmp_ipi_config_table_init(void); + +#endif /* PLAT_IPI_H */ diff --git a/plat/xilinx/zynqmp/include/plat_macros.S b/plat/xilinx/zynqmp/include/plat_macros.S new file mode 100644 index 0000000..c4ab619 --- /dev/null +++ b/plat/xilinx/zynqmp/include/plat_macros.S @@ -0,0 +1,28 @@ +/* + * Copyright (c) 2014-2018, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef PLAT_MACROS_S +#define PLAT_MACROS_S + +#include <arm_macros.S> +#include <cci_macros.S> +#include "zynqmp_def.h" + + /* --------------------------------------------- + * The below required platform porting macro + * prints out relevant GIC and CCI registers + * whenever an unhandled exception is taken in + * BL31. + * Clobbers: x0 - x10, x16, x17, sp + * --------------------------------------------- + */ + .macro plat_crash_print_regs + mov_imm x17, BASE_GICC_BASE + mov_imm x16, BASE_GICD_BASE + arm_print_gic_regs + print_cci_regs + .endm + +#endif /* PLAT_MACROS_S */ diff --git a/plat/xilinx/zynqmp/include/plat_pm_common.h b/plat/xilinx/zynqmp/include/plat_pm_common.h new file mode 100644 index 0000000..8731a20 --- /dev/null +++ b/plat/xilinx/zynqmp/include/plat_pm_common.h @@ -0,0 +1,25 @@ +/* + * Copyright (c) 2013-2020, Arm Limited and Contributors. All rights reserved. + * Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* + * Contains platform specific definitions of commonly used macros data types + * for PU Power Management. This file should be common for all PU's. + */ + +#ifndef PLAT_PM_COMMON_H +#define PLAT_PM_COMMON_H + +#include <stdint.h> +#include <common/debug.h> +#include "zynqmp_pm_defs.h" + + +#define ZYNQMP_TZ_VERSION_MAJOR 1 +#define ZYNQMP_TZ_VERSION_MINOR 0 +#define ZYNQMP_TZ_VERSION ((ZYNQMP_TZ_VERSION_MAJOR << 16) | \ + ZYNQMP_TZ_VERSION_MINOR) +#endif /* _PLAT_PM_COMMON_H_ */ diff --git a/plat/xilinx/zynqmp/include/plat_private.h b/plat/xilinx/zynqmp/include/plat_private.h new file mode 100644 index 0000000..afa102d --- /dev/null +++ b/plat/xilinx/zynqmp/include/plat_private.h @@ -0,0 +1,41 @@ +/* + * Copyright (c) 2014-2020, Arm Limited and Contributors. All rights reserved. + * Copyright (c) 2023, Advanced Micro Devices, Inc. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef PLAT_PRIVATE_H +#define PLAT_PRIVATE_H + +#include <stdint.h> + +#include <bl31/interrupt_mgmt.h> +#include <common/bl_common.h> +#include <drivers/cadence/cdns_uart.h> +#include <lib/xlat_tables/xlat_tables.h> + +void zynqmp_config_setup(void); + +const mmap_region_t *plat_get_mmap(void); + +uint32_t zynqmp_calc_core_pos(u_register_t mpidr); + +/* ZynqMP specific functions */ +uint32_t get_uart_clk(void); +uint32_t zynqmp_get_bootmode(void); + +#if ZYNQMP_WDT_RESTART +typedef struct zynqmp_intr_info_type_el3 { + uint32_t id; + interrupt_type_handler_t handler; +} zynmp_intr_info_type_el3_t; + +/* + * Register handler to specific GIC entrance + * for INTR_TYPE_EL3 type of interrupt + */ +int request_intr_type_el3(uint32_t, interrupt_type_handler_t); +#endif + +#endif /* PLAT_PRIVATE_H */ diff --git a/plat/xilinx/zynqmp/include/platform_def.h b/plat/xilinx/zynqmp/include/platform_def.h new file mode 100644 index 0000000..0c83a56 --- /dev/null +++ b/plat/xilinx/zynqmp/include/platform_def.h @@ -0,0 +1,176 @@ +/* + * Copyright (c) 2014-2022, Arm Limited and Contributors. All rights reserved. + * Copyright (c) 2018-2022, Xilinx, Inc. All rights reserved. + * Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef PLATFORM_DEF_H +#define PLATFORM_DEF_H + +#include <arch.h> +#include <common/interrupt_props.h> +#include <drivers/arm/gic_common.h> +#include <lib/utils_def.h> + +#include "zynqmp_def.h" + +/******************************************************************************* + * Generic platform constants + ******************************************************************************/ + +/* Size of cacheable stacks */ +#ifndef PLATFORM_STACK_SIZE +#define PLATFORM_STACK_SIZE 0x440 +#endif + +#define PLATFORM_CORE_COUNT U(4) +#define PLAT_MAX_PWR_LVL U(1) +#define PLAT_MAX_RET_STATE U(1) +#define PLAT_MAX_OFF_STATE U(2) + +/******************************************************************************* + * BL31 specific defines. + ******************************************************************************/ +/* + * Put BL31 at the top of the Trusted SRAM (just below the shared memory, if + * present). BL31_BASE is calculated using the current BL31 debug size plus a + * little space for growth. + */ +#ifndef ZYNQMP_ATF_MEM_BASE +#if !DEBUG && defined(SPD_none) && !SDEI_SUPPORT +# define BL31_BASE U(0xfffea000) +# define BL31_LIMIT U(0x100000000) +#else +# define BL31_BASE U(0x1000) +# define BL31_LIMIT U(0x80000) +#endif +#else +# define BL31_BASE U(ZYNQMP_ATF_MEM_BASE) +# define BL31_LIMIT (UL(ZYNQMP_ATF_MEM_BASE) + U(ZYNQMP_ATF_MEM_SIZE)) +# ifdef ZYNQMP_ATF_MEM_PROGBITS_SIZE +# define BL31_PROGBITS_LIMIT (UL(ZYNQMP_ATF_MEM_BASE) + U(ZYNQMP_ATF_MEM_PROGBITS_SIZE)) +# endif +#endif + +/******************************************************************************* + * BL32 specific defines. + ******************************************************************************/ +#ifndef ZYNQMP_BL32_MEM_BASE +# define BL32_BASE U(0x60000000) +# define BL32_LIMIT U(0x80000000) +#else +# define BL32_BASE U(ZYNQMP_BL32_MEM_BASE) +# define BL32_LIMIT (UL(ZYNQMP_BL32_MEM_BASE) + U(ZYNQMP_BL32_MEM_SIZE)) +#endif + +/******************************************************************************* + * BL33 specific defines. + ******************************************************************************/ +#ifndef PRELOADED_BL33_BASE +# define PLAT_ARM_NS_IMAGE_BASE U(0x8000000) +#else +# define PLAT_ARM_NS_IMAGE_BASE U(PRELOADED_BL33_BASE) +#endif + +/******************************************************************************* + * TSP specific defines. + ******************************************************************************/ +#define TSP_SEC_MEM_BASE BL32_BASE +#define TSP_SEC_MEM_SIZE (BL32_LIMIT - BL32_BASE) + +/* ID of the secure physical generic timer interrupt used by the TSP */ +#define TSP_IRQ_SEC_PHY_TIMER ARM_IRQ_SEC_PHY_TIMER + +/******************************************************************************* + * Platform specific page table and MMU setup constants + ******************************************************************************/ +#define XILINX_OF_BOARD_DTB_MAX_SIZE U(0x200000) +#define PLAT_DDR_LOWMEM_MAX U(0x80000000) +#define PLAT_OCM_BASE U(0xFFFC0000) +#define PLAT_OCM_LIMIT U(0xFFFFFFFF) + +#define IS_TFA_IN_OCM(x) ((x >= PLAT_OCM_BASE) && (x < PLAT_OCM_LIMIT)) + +#define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32) +#define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32) + +#ifndef MAX_MMAP_REGIONS +#if (defined(XILINX_OF_BOARD_DTB_ADDR) && !IS_TFA_IN_OCM(BL31_BASE)) +#define MAX_MMAP_REGIONS 8 +#else +#define MAX_MMAP_REGIONS 7 +#endif +#endif + +#ifndef MAX_XLAT_TABLES +#if !IS_TFA_IN_OCM(BL31_BASE) +#define MAX_XLAT_TABLES 8 +#else +#define MAX_XLAT_TABLES 5 +#endif +#endif + +#define CACHE_WRITEBACK_SHIFT 6 +#define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT) + +#define ZYNQMP_SDEI_SGI_PRIVATE U(8) + +/* Platform macros to support exception handling framework */ +#define PLAT_PRI_BITS U(3) +#define PLAT_SDEI_CRITICAL_PRI 0x10 +#define PLAT_SDEI_NORMAL_PRI 0x20 + +#define PLAT_ARM_GICD_BASE BASE_GICD_BASE +#define PLAT_ARM_GICC_BASE BASE_GICC_BASE +/* + * Define properties of Group 1 Secure and Group 0 interrupts as per GICv3 + * terminology. On a GICv2 system or mode, the lists will be merged and treated + * as Group 0 interrupts. + */ +#if !ZYNQMP_WDT_RESTART +#define PLAT_ARM_G1S_IRQ_PROPS(grp) \ + INTR_PROP_DESC(ARM_IRQ_SEC_PHY_TIMER, GIC_HIGHEST_SEC_PRIORITY, grp, \ + GIC_INTR_CFG_LEVEL), \ + INTR_PROP_DESC(ARM_IRQ_SEC_SGI_1, GIC_HIGHEST_SEC_PRIORITY, grp, \ + GIC_INTR_CFG_EDGE), \ + INTR_PROP_DESC(ARM_IRQ_SEC_SGI_2, GIC_HIGHEST_SEC_PRIORITY, grp, \ + GIC_INTR_CFG_EDGE), \ + INTR_PROP_DESC(ARM_IRQ_SEC_SGI_3, GIC_HIGHEST_SEC_PRIORITY, grp, \ + GIC_INTR_CFG_EDGE), \ + INTR_PROP_DESC(ARM_IRQ_SEC_SGI_4, GIC_HIGHEST_SEC_PRIORITY, grp, \ + GIC_INTR_CFG_EDGE), \ + INTR_PROP_DESC(ARM_IRQ_SEC_SGI_5, GIC_HIGHEST_SEC_PRIORITY, grp, \ + GIC_INTR_CFG_EDGE), \ + INTR_PROP_DESC(ARM_IRQ_SEC_SGI_6, GIC_HIGHEST_SEC_PRIORITY, grp, \ + GIC_INTR_CFG_EDGE), \ + INTR_PROP_DESC(ARM_IRQ_SEC_SGI_7, GIC_HIGHEST_SEC_PRIORITY, grp, \ + GIC_INTR_CFG_EDGE) +#else +#define PLAT_ARM_G1S_IRQ_PROPS(grp) \ + INTR_PROP_DESC(ARM_IRQ_SEC_PHY_TIMER, GIC_HIGHEST_SEC_PRIORITY, grp, \ + GIC_INTR_CFG_LEVEL), \ + INTR_PROP_DESC(IRQ_TTC3_1, GIC_HIGHEST_SEC_PRIORITY, grp, \ + GIC_INTR_CFG_EDGE), \ + INTR_PROP_DESC(ARM_IRQ_SEC_SGI_1, GIC_HIGHEST_SEC_PRIORITY, grp, \ + GIC_INTR_CFG_EDGE), \ + INTR_PROP_DESC(ARM_IRQ_SEC_SGI_2, GIC_HIGHEST_SEC_PRIORITY, grp, \ + GIC_INTR_CFG_EDGE), \ + INTR_PROP_DESC(ARM_IRQ_SEC_SGI_3, GIC_HIGHEST_SEC_PRIORITY, grp, \ + GIC_INTR_CFG_EDGE), \ + INTR_PROP_DESC(ARM_IRQ_SEC_SGI_4, GIC_HIGHEST_SEC_PRIORITY, grp, \ + GIC_INTR_CFG_EDGE), \ + INTR_PROP_DESC(ARM_IRQ_SEC_SGI_5, GIC_HIGHEST_SEC_PRIORITY, grp, \ + GIC_INTR_CFG_EDGE), \ + INTR_PROP_DESC(ARM_IRQ_SEC_SGI_6, GIC_HIGHEST_SEC_PRIORITY, grp, \ + GIC_INTR_CFG_EDGE), \ + INTR_PROP_DESC(ARM_IRQ_SEC_SGI_7, GIC_HIGHEST_SEC_PRIORITY, grp, \ + GIC_INTR_CFG_EDGE) +#endif + +#define PLAT_ARM_G0_IRQ_PROPS(grp) \ + INTR_PROP_DESC(ARM_IRQ_SEC_SGI_0, PLAT_SDEI_NORMAL_PRI, grp, \ + GIC_INTR_CFG_EDGE) + +#endif /* PLATFORM_DEF_H */ diff --git a/plat/xilinx/zynqmp/include/zynqmp_def.h b/plat/xilinx/zynqmp/include/zynqmp_def.h new file mode 100644 index 0000000..d715ce2 --- /dev/null +++ b/plat/xilinx/zynqmp/include/zynqmp_def.h @@ -0,0 +1,349 @@ +/* + * Copyright (c) 2014-2020, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef ZYNQMP_DEF_H +#define ZYNQMP_DEF_H + +#include <plat/arm/common/smccc_def.h> +#include <plat/common/common_def.h> + +#define ZYNQMP_CONSOLE_ID_cadence 1 +#define ZYNQMP_CONSOLE_ID_cadence0 1 +#define ZYNQMP_CONSOLE_ID_cadence1 2 +#define ZYNQMP_CONSOLE_ID_dcc 3 + +#define CONSOLE_IS(con) (ZYNQMP_CONSOLE_ID_ ## con == ZYNQMP_CONSOLE) + +/* Default counter frequency */ +#define ZYNQMP_DEFAULT_COUNTER_FREQ 0U + +/* Firmware Image Package */ +#define ZYNQMP_PRIMARY_CPU 0 + +/* Memory location options for Shared data and TSP in ZYNQMP */ +#define ZYNQMP_IN_TRUSTED_SRAM 0 +#define ZYNQMP_IN_TRUSTED_DRAM 1 + +/******************************************************************************* + * ZYNQMP memory map related constants + ******************************************************************************/ +/* Aggregate of all devices in the first GB */ +#define DEVICE0_BASE U(0xFF000000) +#define DEVICE0_SIZE U(0x00E00000) +#define DEVICE1_BASE U(0xF9000000) +#define DEVICE1_SIZE U(0x00800000) + +/* For cpu reset APU space here too 0xFE5F1000 CRF_APB*/ +#define CRF_APB_BASE U(0xFD1A0000) +#define CRF_APB_SIZE U(0x00600000) +#define CRF_APB_CLK_BASE U(0xFD1A0020) + +/* CRF registers and bitfields */ +#define CRF_APB_RST_FPD_APU (CRF_APB_BASE + 0X00000104) + +#define CRF_APB_RST_FPD_APU_ACPU_RESET (U(1) << 0) +#define CRF_APB_RST_FPD_APU_ACPU_PWRON_RESET (U(1) << 10) + +/* CRL registers and bitfields */ +#define CRL_APB_BASE U(0xFF5E0000) +#define CRL_APB_BOOT_MODE_USER (CRL_APB_BASE + 0x200) +#define CRL_APB_RESET_CTRL (CRL_APB_BASE + 0x218) +#define CRL_APB_RST_LPD_TOP (CRL_APB_BASE + 0x23C) +#define CRL_APB_BOOT_PIN_CTRL (CRL_APB_BASE + U(0x250)) +#define CRL_APB_CLK_BASE U(0xFF5E0020) + +#define CRL_APB_RPU_AMBA_RESET (U(1) << 2) +#define CRL_APB_RPLL_CTRL_BYPASS (U(1) << 3) + +#define CRL_APB_RESET_CTRL_SOFT_RESET (U(1) << 4) + +#define CRL_APB_BOOT_MODE_MASK (U(0xf) << 0) +#define CRL_APB_BOOT_PIN_MASK (U(0xf0f) << 0) +#define CRL_APB_BOOT_DRIVE_PIN_1_SHIFT U(9) +#define CRL_APB_BOOT_ENABLE_PIN_1_SHIFT U(1) +#define CRL_APB_BOOT_ENABLE_PIN_1 (U(0x1) << \ + CRL_APB_BOOT_ENABLE_PIN_1_SHIFT) +#define CRL_APB_BOOT_DRIVE_PIN_1 (U(0x1) << \ + CRL_APB_BOOT_DRIVE_PIN_1_SHIFT) +#define ZYNQMP_BOOTMODE_JTAG U(0) +#define ZYNQMP_ULPI_RESET_VAL_HIGH (CRL_APB_BOOT_ENABLE_PIN_1 | \ + CRL_APB_BOOT_DRIVE_PIN_1) +#define ZYNQMP_ULPI_RESET_VAL_LOW CRL_APB_BOOT_ENABLE_PIN_1 + +/* system counter registers and bitfields */ +#define IOU_SCNTRS_BASE U(0xFF260000) +#define IOU_SCNTRS_BASEFREQ (IOU_SCNTRS_BASE + 0x20) + +/* APU registers and bitfields */ +#define APU_BASE U(0xFD5C0000) +#define APU_CONFIG_0 (APU_BASE + 0x20) +#define APU_RVBAR_L_0 (APU_BASE + 0x40) +#define APU_RVBAR_H_0 (APU_BASE + 0x44) +#define APU_PWRCTL (APU_BASE + 0x90) + +#define APU_CONFIG_0_VINITHI_SHIFT 8 +#define APU_0_PWRCTL_CPUPWRDWNREQ_MASK 1 +#define APU_1_PWRCTL_CPUPWRDWNREQ_MASK 2 +#define APU_2_PWRCTL_CPUPWRDWNREQ_MASK 4 +#define APU_3_PWRCTL_CPUPWRDWNREQ_MASK 8 + +/* PMU registers and bitfields */ +#define PMU_GLOBAL_BASE U(0xFFD80000) +#define PMU_GLOBAL_CNTRL (PMU_GLOBAL_BASE + 0) +#define PMU_GLOBAL_GEN_STORAGE6 (PMU_GLOBAL_BASE + 0x48) +#define PMU_GLOBAL_REQ_PWRUP_STATUS (PMU_GLOBAL_BASE + 0x110) +#define PMU_GLOBAL_REQ_PWRUP_EN (PMU_GLOBAL_BASE + 0x118) +#define PMU_GLOBAL_REQ_PWRUP_DIS (PMU_GLOBAL_BASE + 0x11c) +#define PMU_GLOBAL_REQ_PWRUP_TRIG (PMU_GLOBAL_BASE + 0x120) + +#define PMU_GLOBAL_CNTRL_FW_IS_PRESENT (1 << 4) + +/******************************************************************************* + * CCI-400 related constants + ******************************************************************************/ +#define PLAT_ARM_CCI_BASE U(0xFD6E0000) +#define PLAT_ARM_CCI_CLUSTER0_SL_IFACE_IX 3 +#define PLAT_ARM_CCI_CLUSTER1_SL_IFACE_IX 4 + +/******************************************************************************* + * GIC-400 & interrupt handling related constants + ******************************************************************************/ +#define BASE_GICD_BASE U(0xF9010000) +#define BASE_GICC_BASE U(0xF9020000) +#define BASE_GICH_BASE U(0xF9040000) +#define BASE_GICV_BASE U(0xF9060000) + +#if ZYNQMP_WDT_RESTART +#define IRQ_SEC_IPI_APU 67 +#define IRQ_TTC3_1 77 +#define TTC3_BASE_ADDR U(0xFF140000) +#define TTC3_INTR_REGISTER_1 (TTC3_BASE_ADDR + 0x54) +#define TTC3_INTR_ENABLE_1 (TTC3_BASE_ADDR + 0x60) +#endif + +#define ARM_IRQ_SEC_PHY_TIMER 29 + +#define ARM_IRQ_SEC_SGI_0 8 +#define ARM_IRQ_SEC_SGI_1 9 +#define ARM_IRQ_SEC_SGI_2 10 +#define ARM_IRQ_SEC_SGI_3 11 +#define ARM_IRQ_SEC_SGI_4 12 +#define ARM_IRQ_SEC_SGI_5 13 +#define ARM_IRQ_SEC_SGI_6 14 +#define ARM_IRQ_SEC_SGI_7 15 + +/* number of interrupt handlers. increase as required */ +#define MAX_INTR_EL3 2 + +/******************************************************************************* + * UART related constants + ******************************************************************************/ +#define ZYNQMP_UART0_BASE U(0xFF000000) +#define ZYNQMP_UART1_BASE U(0xFF010000) + +#if CONSOLE_IS(cadence) || CONSOLE_IS(dcc) +# define UART_BASE ZYNQMP_UART0_BASE +#elif CONSOLE_IS(cadence1) +# define UART_BASE ZYNQMP_UART1_BASE +#else +# error "invalid ZYNQMP_CONSOLE" +#endif + +/* Must be non zero */ +#define UART_BAUDRATE 115200 + +/* Silicon version detection */ +#define ZYNQMP_SILICON_VER_MASK 0xF000 +#define ZYNQMP_SILICON_VER_SHIFT 12 +#define ZYNQMP_CSU_VERSION_SILICON 0 +#define ZYNQMP_CSU_VERSION_QEMU 3 + +#define ZYNQMP_RTL_VER_MASK 0xFF0U +#define ZYNQMP_RTL_VER_SHIFT 4 + +#define ZYNQMP_PS_VER_MASK 0xFU +#define ZYNQMP_PS_VER_SHIFT 0 + +#define ZYNQMP_CSU_BASEADDR U(0xFFCA0000) +#define ZYNQMP_CSU_IDCODE_OFFSET 0x40U + +#define ZYNQMP_CSU_IDCODE_XILINX_ID_SHIFT 0U +#define ZYNQMP_CSU_IDCODE_XILINX_ID_MASK (0xFFFU << \ + ZYNQMP_CSU_IDCODE_XILINX_ID_SHIFT) +#define ZYNQMP_CSU_IDCODE_XILINX_ID 0x093 + +#define ZYNQMP_CSU_IDCODE_SVD_SHIFT 12U +#define ZYNQMP_CSU_IDCODE_SVD_MASK (0x7U << \ + ZYNQMP_CSU_IDCODE_SVD_SHIFT) +#define ZYNQMP_CSU_IDCODE_DEVICE_CODE_SHIFT 15U +#define ZYNQMP_CSU_IDCODE_DEVICE_CODE_MASK (0xFU << \ + ZYNQMP_CSU_IDCODE_DEVICE_CODE_SHIFT) +#define ZYNQMP_CSU_IDCODE_SUB_FAMILY_SHIFT 19U +#define ZYNQMP_CSU_IDCODE_SUB_FAMILY_MASK (0x3U << \ + ZYNQMP_CSU_IDCODE_SUB_FAMILY_SHIFT) +#define ZYNQMP_CSU_IDCODE_FAMILY_SHIFT 21U +#define ZYNQMP_CSU_IDCODE_FAMILY_MASK (0x7FU << \ + ZYNQMP_CSU_IDCODE_FAMILY_SHIFT) +#define ZYNQMP_CSU_IDCODE_FAMILY 0x23 + +#define ZYNQMP_CSU_IDCODE_REVISION_SHIFT 28U +#define ZYNQMP_CSU_IDCODE_REVISION_MASK (0xFU << \ + ZYNQMP_CSU_IDCODE_REVISION_SHIFT) +#define ZYNQMP_CSU_IDCODE_REVISION 0U + +#define ZYNQMP_CSU_VERSION_OFFSET 0x44U + +/* Efuse */ +#define EFUSE_BASEADDR U(0xFFCC0000) +#define EFUSE_IPDISABLE_OFFSET 0x1018 +#define EFUSE_IPDISABLE_VERSION 0x1FFU +#define ZYNQMP_EFUSE_IPDISABLE_SHIFT 20 + +/* Access control register defines */ +#define ACTLR_EL3_L2ACTLR_BIT (1 << 6) +#define ACTLR_EL3_CPUACTLR_BIT (1 << 0) + +#define FPD_SLCR_BASEADDR U(0xFD610000) +#define IOU_SLCR_BASEADDR U(0xFF180000) + +#define ZYNQMP_RPU_GLBL_CNTL U(0xFF9A0000) +#define ZYNQMP_RPU0_CFG U(0xFF9A0100) +#define ZYNQMP_RPU1_CFG U(0xFF9A0200) +#define ZYNQMP_SLSPLIT_MASK U(0x08) +#define ZYNQMP_TCM_COMB_MASK U(0x40) +#define ZYNQMP_SLCLAMP_MASK U(0x10) +#define ZYNQMP_VINITHI_MASK U(0x04) + +/* Tap delay bypass */ +#define IOU_TAPDLY_BYPASS U(0XFF180390) +#define TAP_DELAY_MASK U(0x7) + +/* SD DLL reset */ +#define ZYNQMP_SD_DLL_CTRL U(0xFF180358) +#define ZYNQMP_SD0_DLL_RST_MASK U(0x00000004) +#define ZYNQMP_SD0_DLL_RST U(0x00000004) +#define ZYNQMP_SD1_DLL_RST_MASK U(0x00040000) +#define ZYNQMP_SD1_DLL_RST U(0x00040000) + +/* SD tap delay */ +#define ZYNQMP_SD_DLL_CTRL U(0xFF180358) +#define ZYNQMP_SD_ITAP_DLY U(0xFF180314) +#define ZYNQMP_SD_OTAP_DLY U(0xFF180318) +#define ZYNQMP_SD_TAP_OFFSET U(16) +#define ZYNQMP_SD_ITAPCHGWIN_MASK U(0x200) +#define ZYNQMP_SD_ITAPCHGWIN U(0x200) +#define ZYNQMP_SD_ITAPDLYENA_MASK U(0x100) +#define ZYNQMP_SD_ITAPDLYENA U(0x100) +#define ZYNQMP_SD_ITAPDLYSEL_MASK U(0xFF) +#define ZYNQMP_SD_OTAPDLYSEL_MASK U(0x3F) +#define ZYNQMP_SD_OTAPDLYENA_MASK U(0x40) +#define ZYNQMP_SD_OTAPDLYENA U(0x40) + +/* Clock control registers */ +/* Full power domain clocks */ +#define CRF_APB_APLL_CTRL (CRF_APB_CLK_BASE + 0x00) +#define CRF_APB_DPLL_CTRL (CRF_APB_CLK_BASE + 0x0c) +#define CRF_APB_VPLL_CTRL (CRF_APB_CLK_BASE + 0x18) +#define CRF_APB_PLL_STATUS (CRF_APB_CLK_BASE + 0x24) +#define CRF_APB_APLL_TO_LPD_CTRL (CRF_APB_CLK_BASE + 0x28) +#define CRF_APB_DPLL_TO_LPD_CTRL (CRF_APB_CLK_BASE + 0x2c) +#define CRF_APB_VPLL_TO_LPD_CTRL (CRF_APB_CLK_BASE + 0x30) +/* Peripheral clocks */ +#define CRF_APB_ACPU_CTRL (CRF_APB_CLK_BASE + 0x40) +#define CRF_APB_DBG_TRACE_CTRL (CRF_APB_CLK_BASE + 0x44) +#define CRF_APB_DBG_FPD_CTRL (CRF_APB_CLK_BASE + 0x48) +#define CRF_APB_DP_VIDEO_REF_CTRL (CRF_APB_CLK_BASE + 0x50) +#define CRF_APB_DP_AUDIO_REF_CTRL (CRF_APB_CLK_BASE + 0x54) +#define CRF_APB_DP_STC_REF_CTRL (CRF_APB_CLK_BASE + 0x5c) +#define CRF_APB_DDR_CTRL (CRF_APB_CLK_BASE + 0x60) +#define CRF_APB_GPU_REF_CTRL (CRF_APB_CLK_BASE + 0x64) +#define CRF_APB_SATA_REF_CTRL (CRF_APB_CLK_BASE + 0x80) +#define CRF_APB_PCIE_REF_CTRL (CRF_APB_CLK_BASE + 0x94) +#define CRF_APB_GDMA_REF_CTRL (CRF_APB_CLK_BASE + 0x98) +#define CRF_APB_DPDMA_REF_CTRL (CRF_APB_CLK_BASE + 0x9c) +#define CRF_APB_TOPSW_MAIN_CTRL (CRF_APB_CLK_BASE + 0xa0) +#define CRF_APB_TOPSW_LSBUS_CTRL (CRF_APB_CLK_BASE + 0xa4) +#define CRF_APB_GTGREF0_REF_CTRL (CRF_APB_CLK_BASE + 0xa8) +#define CRF_APB_DBG_TSTMP_CTRL (CRF_APB_CLK_BASE + 0xd8) + +/* Low power domain clocks */ +#define CRL_APB_IOPLL_CTRL (CRL_APB_CLK_BASE + 0x00) +#define CRL_APB_RPLL_CTRL (CRL_APB_CLK_BASE + 0x10) +#define CRL_APB_PLL_STATUS (CRL_APB_CLK_BASE + 0x20) +#define CRL_APB_IOPLL_TO_FPD_CTRL (CRL_APB_CLK_BASE + 0x24) +#define CRL_APB_RPLL_TO_FPD_CTRL (CRL_APB_CLK_BASE + 0x28) +/* Peripheral clocks */ +#define CRL_APB_USB3_DUAL_REF_CTRL (CRL_APB_CLK_BASE + 0x2c) +#define CRL_APB_GEM0_REF_CTRL (CRL_APB_CLK_BASE + 0x30) +#define CRL_APB_GEM1_REF_CTRL (CRL_APB_CLK_BASE + 0x34) +#define CRL_APB_GEM2_REF_CTRL (CRL_APB_CLK_BASE + 0x38) +#define CRL_APB_GEM3_REF_CTRL (CRL_APB_CLK_BASE + 0x3c) +#define CRL_APB_USB0_BUS_REF_CTRL (CRL_APB_CLK_BASE + 0x40) +#define CRL_APB_USB1_BUS_REF_CTRL (CRL_APB_CLK_BASE + 0x44) +#define CRL_APB_QSPI_REF_CTRL (CRL_APB_CLK_BASE + 0x48) +#define CRL_APB_SDIO0_REF_CTRL (CRL_APB_CLK_BASE + 0x4c) +#define CRL_APB_SDIO1_REF_CTRL (CRL_APB_CLK_BASE + 0x50) +#define CRL_APB_UART0_REF_CTRL (CRL_APB_CLK_BASE + 0x54) +#define CRL_APB_UART1_REF_CTRL (CRL_APB_CLK_BASE + 0x58) +#define CRL_APB_SPI0_REF_CTRL (CRL_APB_CLK_BASE + 0x5c) +#define CRL_APB_SPI1_REF_CTRL (CRL_APB_CLK_BASE + 0x60) +#define CRL_APB_CAN0_REF_CTRL (CRL_APB_CLK_BASE + 0x64) +#define CRL_APB_CAN1_REF_CTRL (CRL_APB_CLK_BASE + 0x68) +#define CRL_APB_CPU_R5_CTRL (CRL_APB_CLK_BASE + 0x70) +#define CRL_APB_IOU_SWITCH_CTRL (CRL_APB_CLK_BASE + 0x7c) +#define CRL_APB_CSU_PLL_CTRL (CRL_APB_CLK_BASE + 0x80) +#define CRL_APB_PCAP_CTRL (CRL_APB_CLK_BASE + 0x84) +#define CRL_APB_LPD_SWITCH_CTRL (CRL_APB_CLK_BASE + 0x88) +#define CRL_APB_LPD_LSBUS_CTRL (CRL_APB_CLK_BASE + 0x8c) +#define CRL_APB_DBG_LPD_CTRL (CRL_APB_CLK_BASE + 0x90) +#define CRL_APB_NAND_REF_CTRL (CRL_APB_CLK_BASE + 0x94) +#define CRL_APB_ADMA_REF_CTRL (CRL_APB_CLK_BASE + 0x98) +#define CRL_APB_PL0_REF_CTRL (CRL_APB_CLK_BASE + 0xa0) +#define CRL_APB_PL1_REF_CTRL (CRL_APB_CLK_BASE + 0xa4) +#define CRL_APB_PL2_REF_CTRL (CRL_APB_CLK_BASE + 0xa8) +#define CRL_APB_PL3_REF_CTRL (CRL_APB_CLK_BASE + 0xac) +#define CRL_APB_PL0_THR_CNT (CRL_APB_CLK_BASE + 0xb4) +#define CRL_APB_PL1_THR_CNT (CRL_APB_CLK_BASE + 0xbc) +#define CRL_APB_PL2_THR_CNT (CRL_APB_CLK_BASE + 0xc4) +#define CRL_APB_PL3_THR_CNT (CRL_APB_CLK_BASE + 0xdc) +#define CRL_APB_GEM_TSU_REF_CTRL (CRL_APB_CLK_BASE + 0xe0) +#define CRL_APB_DLL_REF_CTRL (CRL_APB_CLK_BASE + 0xe4) +#define CRL_APB_AMS_REF_CTRL (CRL_APB_CLK_BASE + 0xe8) +#define CRL_APB_I2C0_REF_CTRL (CRL_APB_CLK_BASE + 0x100) +#define CRL_APB_I2C1_REF_CTRL (CRL_APB_CLK_BASE + 0x104) +#define CRL_APB_TIMESTAMP_REF_CTRL (CRL_APB_CLK_BASE + 0x108) +#define IOU_SLCR_GEM_CLK_CTRL (IOU_SLCR_BASEADDR + 0x308) +#define IOU_SLCR_CAN_MIO_CTRL (IOU_SLCR_BASEADDR + 0x304) +#define FPD_SLCR_WDT_CLK_SEL (FPD_SLCR_BASEADDR + 0x100) +#define IOU_SLCR_WDT_CLK_SEL (IOU_SLCR_BASEADDR + 0x300) + +/* Global general storage register base address */ +#define GGS_BASEADDR (0xFFD80030U) +#define GGS_NUM_REGS U(4) + +/* Persistent global general storage register base address */ +#define PGGS_BASEADDR (0xFFD80050U) +#define PGGS_NUM_REGS U(4) + +/* PMU GGS4 register 4 is used for warm restart boot health status */ +#define PMU_GLOBAL_GEN_STORAGE4 (GGS_BASEADDR + 0x10) +/* Warm restart boot health status mask */ +#define PM_BOOT_HEALTH_STATUS_MASK U(0x01) +/* WDT restart scope shift and mask */ +#define RESTART_SCOPE_SHIFT (3) +#define RESTART_SCOPE_MASK (0x3U << RESTART_SCOPE_SHIFT) + +/* AFI registers */ +#define AFIFM6_WRCTRL U(13) +#define FABRIC_WIDTH U(3) + +/* CSUDMA Module Base Address*/ +#define CSUDMA_BASE U(0xFFC80000) + +/* RSA-CORE Module Base Address*/ +#define RSA_CORE_BASE U(0xFFCE0000) + +#endif /* ZYNQMP_DEF_H */ |