/* * Copyright 2022-2023 NXP * * SPDX-License-Identifier: BSD-3-Clause */ #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #define MAP_BL31_TOTAL \ MAP_REGION_FLAT(BL31_BASE, BL31_LIMIT - BL31_BASE, MT_MEMORY | MT_RW | MT_SECURE) #define MAP_BL31_RO \ MAP_REGION_FLAT(BL_CODE_BASE, BL_CODE_END - BL_CODE_BASE, MT_MEMORY | MT_RO | MT_SECURE) static const mmap_region_t imx_mmap[] = { AIPS1_MAP, AIPS2_MAP, AIPS4_MAP, GIC_MAP, TRDC_A_MAP, TRDC_W_MAP, TRDC_M_MAP, TRDC_N_MAP, {0}, }; static entry_point_info_t bl32_image_ep_info; static entry_point_info_t bl33_image_ep_info; /* get SPSR for BL33 entry */ static uint32_t get_spsr_for_bl33_entry(void) { unsigned long el_status; unsigned long mode; uint32_t spsr; /* figure out what mode we enter the non-secure world */ el_status = read_id_aa64pfr0_el1() >> ID_AA64PFR0_EL2_SHIFT; el_status &= ID_AA64PFR0_ELX_MASK; mode = (el_status) ? MODE_EL2 : MODE_EL1; spsr = SPSR_64(mode, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS); return spsr; } void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, u_register_t arg2, u_register_t arg3) { static console_t console; console_lpuart_register(IMX_LPUART_BASE, IMX_BOOT_UART_CLK_IN_HZ, IMX_CONSOLE_BAUDRATE, &console); /* This console is only used for boot stage */ console_set_scope(&console, CONSOLE_FLAG_BOOT); /* * tell BL3-1 where the non-secure software image is located * and the entry state information. */ bl33_image_ep_info.pc = PLAT_NS_IMAGE_OFFSET; bl33_image_ep_info.spsr = get_spsr_for_bl33_entry(); SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE); #if defined(SPD_opteed) /* Populate entry point information for BL32 */ SET_PARAM_HEAD(&bl32_image_ep_info, PARAM_EP, VERSION_1, 0); SET_SECURITY_STATE(bl32_image_ep_info.h.attr, SECURE); bl32_image_ep_info.pc = BL32_BASE; bl32_image_ep_info.spsr = 0; /* Pass TEE base and size to bl33 */ bl33_image_ep_info.args.arg1 = BL32_BASE; bl33_image_ep_info.args.arg2 = BL32_SIZE; /* Make sure memory is clean */ mmio_write_32(BL32_FDT_OVERLAY_ADDR, 0); bl33_image_ep_info.args.arg3 = BL32_FDT_OVERLAY_ADDR; bl32_image_ep_info.args.arg3 = BL32_FDT_OVERLAY_ADDR; #endif } void bl31_plat_arch_setup(void) { /* no coherence memory support on i.MX9 */ const mmap_region_t bl_regions[] = { MAP_BL31_TOTAL, MAP_BL31_RO, }; /* Assign all the GPIO pins to non-secure world by default */ mmio_write_32(GPIO2_BASE + 0x10, 0xffffffff); mmio_write_32(GPIO2_BASE + 0x14, 0x3); mmio_write_32(GPIO2_BASE + 0x18, 0xffffffff); mmio_write_32(GPIO2_BASE + 0x1c, 0x3); mmio_write_32(GPIO3_BASE + 0x10, 0xffffffff); mmio_write_32(GPIO3_BASE + 0x14, 0x3); mmio_write_32(GPIO3_BASE + 0x18, 0xffffffff); mmio_write_32(GPIO3_BASE + 0x1c, 0x3); mmio_write_32(GPIO4_BASE + 0x10, 0xffffffff); mmio_write_32(GPIO4_BASE + 0x14, 0x3); mmio_write_32(GPIO4_BASE + 0x18, 0xffffffff); mmio_write_32(GPIO4_BASE + 0x1c, 0x3); mmio_write_32(GPIO1_BASE + 0x10, 0xffffffff); mmio_write_32(GPIO1_BASE + 0x14, 0x3); mmio_write_32(GPIO1_BASE + 0x18, 0xffffffff); mmio_write_32(GPIO1_BASE + 0x1c, 0x3); setup_page_tables(bl_regions, imx_mmap); enable_mmu_el3(0); /* trdc must be initialized */ trdc_config(); } void bl31_platform_setup(void) { generic_delay_timer_init(); plat_gic_driver_init(); plat_gic_init(); } void bl31_plat_runtime_setup(void) { console_switch_state(CONSOLE_FLAG_RUNTIME); } entry_point_info_t *bl31_plat_get_next_image_ep_info(unsigned int type) { if (type == NON_SECURE) { return &bl33_image_ep_info; } if (type == SECURE) { return &bl32_image_ep_info; } return NULL; } unsigned int plat_get_syscnt_freq2(void) { return COUNTER_FREQUENCY; }