From 0ebf5bdf043a27fd3dfb7f92e0cb63d88954c44d Mon Sep 17 00:00:00 2001 From: Daniel Baumann Date: Fri, 19 Apr 2024 03:47:29 +0200 Subject: Adding upstream version 115.8.0esr. Signed-off-by: Daniel Baumann --- media/libtheora/clang-arm.patch | 277 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 277 insertions(+) create mode 100644 media/libtheora/clang-arm.patch (limited to 'media/libtheora/clang-arm.patch') diff --git a/media/libtheora/clang-arm.patch b/media/libtheora/clang-arm.patch new file mode 100644 index 0000000000..0fd97ebb1b --- /dev/null +++ b/media/libtheora/clang-arm.patch @@ -0,0 +1,277 @@ +diff --git a/lib/arm/arm2gnu.pl b/lib/arm/arm2gnu.pl +index 8cb68e4..d6fe09c 100755 +--- a/lib/arm/arm2gnu.pl ++++ b/lib/arm/arm2gnu.pl +@@ -25,6 +25,8 @@ $n=0; + $thumb = 0; # ARM mode by default, not Thumb. + @proc_stack = (); + ++printf (" .syntax unified\n"); ++ + LINE: + while (<>) { + +diff --git a/lib/arm/armbits.s b/lib/arm/armbits.s +index 9400722..fd6e444 100644 +--- a/lib/arm/armbits.s ++++ b/lib/arm/armbits.s +@@ -67,28 +67,28 @@ oc_pack_read_refill + ; negative. + CMP r10,r11 ; ptr HI + CMPHI r3,#7 ; available<=24 => HI +- LDRHIB r14,[r11],#1 ; r14 = *ptr++ ++ LDRBHI r14,[r11],#1 ; r14 = *ptr++ + SUBHI r3,#8 ; available += 8 + ; (HI) Stall... +- ORRHI r2,r14,LSL r3 ; r2 = window|=r14<<32-available ++ ORRHI r2,r2,r14,LSL r3 ; r2 = window|=r14<<32-available + CMPHI r10,r11 ; ptr HI + CMPHI r3,#7 ; available<=24 => HI +- LDRHIB r14,[r11],#1 ; r14 = *ptr++ ++ LDRBHI r14,[r11],#1 ; r14 = *ptr++ + SUBHI r3,#8 ; available += 8 + ; (HI) Stall... +- ORRHI r2,r14,LSL r3 ; r2 = window|=r14<<32-available ++ ORRHI r2,r2,r14,LSL r3 ; r2 = window|=r14<<32-available + CMPHI r10,r11 ; ptr HI + CMPHI r3,#7 ; available<=24 => HI +- LDRHIB r14,[r11],#1 ; r14 = *ptr++ ++ LDRBHI r14,[r11],#1 ; r14 = *ptr++ + SUBHI r3,#8 ; available += 8 + ; (HI) Stall... +- ORRHI r2,r14,LSL r3 ; r2 = window|=r14<<32-available ++ ORRHI r2,r2,r14,LSL r3 ; r2 = window|=r14<<32-available + CMPHI r10,r11 ; ptr HI + CMPHI r3,#7 ; available<=24 => HI +- LDRHIB r14,[r11],#1 ; r14 = *ptr++ ++ LDRBHI r14,[r11],#1 ; r14 = *ptr++ + SUBHI r3,#8 ; available += 8 + ; (HI) Stall... +- ORRHI r2,r14,LSL r3 ; r2 = window|=r14<<32-available ++ ORRHI r2,r2,r14,LSL r3 ; r2 = window|=r14<<32-available + SUBS r3,r0,r3 ; r3 = available-=_bits, available GT + BLT oc_pack_read_refill_last + MOV r0,r2,LSR r0 ; r0 = window>>32-_bits +@@ -104,14 +104,14 @@ oc_pack_read_refill_last + CMP r11,r10 ; ptr LO + ; If we didn't hit the end of the packet, then pull enough of the next byte to + ; to fill up the window. +- LDRLOB r14,[r11] ; (LO) r14 = *ptr ++ LDRBLO r14,[r11] ; (LO) r14 = *ptr + ; Otherwise, set the EOF flag and pretend we have lots of available bits. + MOVHS r14,#1 ; (HS) r14 = 1 + ADDLO r10,r3,r1 ; (LO) r10 = available + STRHS r14,[r12,#8] ; (HS) eof = 1 + ANDLO r10,r10,#7 ; (LO) r10 = available&7 + MOVHS r3,#1<<30 ; (HS) available = OC_LOTS_OF_BITS +- ORRLO r2,r14,LSL r10 ; (LO) r2 = window|=*ptr>>(available&7) ++ ORRLO r2,r2,r14,LSL r10 ; (LO) r2 = window|=*ptr>>(available&7) + MOV r0,r2,LSR r0 ; r0 = window>>32-_bits + MOV r2,r2,LSL r1 ; r2 = window<<=_bits + STR r11,[r12,#-4] ; ptr = r11 +@@ -183,32 +183,32 @@ oc_huff_token_decode_refill + ; We can't possibly need more than 15 bits, so available must be <= 15. + ; Therefore we can load at least two bytes without checking it. + CMP r2,r3 ; ptr HI +- LDRHIB r14,[r3],#1 ; r14 = *ptr++ ++ LDRBHI r14,[r3],#1 ; r14 = *ptr++ + RSBHI r5,r5,#24 ; (HI) available = 32-(available+=8) + RSBLS r5,r5,#32 ; (LS) r5 = 32-available +- ORRHI r4,r14,LSL r5 ; r4 = window|=r14<<32-available ++ ORRHI r4,r4,r14,LSL r5 ; r4 = window|=r14<<32-available + CMPHI r2,r3 ; ptr HI +- LDRHIB r14,[r3],#1 ; r14 = *ptr++ ++ LDRBHI r14,[r3],#1 ; r14 = *ptr++ + SUBHI r5,#8 ; available += 8 + ; (HI) Stall... +- ORRHI r4,r14,LSL r5 ; r4 = window|=r14<<32-available ++ ORRHI r4,r4,r14,LSL r5 ; r4 = window|=r14<<32-available + ; We can use unsigned compares for both the pointers and for available + ; (allowing us to chain condition codes) because available will never be + ; larger than 32 (or we wouldn't be here), and thus 32-available will never be + ; negative. + CMPHI r2,r3 ; ptr HI + CMPHI r5,#7 ; available<=24 => HI +- LDRHIB r14,[r3],#1 ; r14 = *ptr++ ++ LDRBHI r14,[r3],#1 ; r14 = *ptr++ + SUBHI r5,#8 ; available += 8 + ; (HI) Stall... +- ORRHI r4,r14,LSL r5 ; r4 = window|=r14<<32-available ++ ORRHI r4,r4,r14,LSL r5 ; r4 = window|=r14<<32-available + CMP r2,r3 ; ptr HI + MOVLS r5,#-1<<30 ; (LS) available = OC_LOTS_OF_BITS+32 + CMPHI r5,#7 ; (HI) available<=24 => HI +- LDRHIB r14,[r3],#1 ; (HI) r14 = *ptr++ ++ LDRBHI r14,[r3],#1 ; (HI) r14 = *ptr++ + SUBHI r5,#8 ; (HI) available += 8 + ; (HI) Stall... +- ORRHI r4,r14,LSL r5 ; (HI) r4 = window|=r14<<32-available ++ ORRHI r4,r4,r14,LSL r5 ; (HI) r4 = window|=r14<<32-available + RSB r14,r10,#32 ; r14 = 32-n + MOV r14,r4,LSR r14 ; r14 = bits=window>>32-n + ADD r12,r12,r14 ; +diff --git a/lib/arm/armfrag.s b/lib/arm/armfrag.s +index 38627ed..38ee775 100644 +--- a/lib/arm/armfrag.s ++++ b/lib/arm/armfrag.s +@@ -357,7 +357,7 @@ ofrintra_v6_lp + ORR r5, r5, r5, LSR #8 ; r5 = __777766 + PKHBT r2, r2, r3, LSL #16 ; r2 = 33221100 + PKHBT r3, r4, r5, LSL #16 ; r3 = 77665544 +- STRD r2, [r0], r1 ++ STRD r2, r3, [r0], r1 + BGT ofrintra_v6_lp + LDMFD r13!,{r4-r6,PC} + ENDP +@@ -397,7 +397,7 @@ ofrinter_v6_lp + USAT16 r12,#8, r12 ; r12= __66__44 + USAT16 r5, #8, r5 ; r4 = __77__55 + ORR r5, r12,r5, LSL #8 ; r5 = 33221100 +- STRD r4, [r0], r2 ++ STRD r4, r5, [r0], r2 + BGT ofrinter_v6_lp + LDMFD r13!,{r4-r7,PC} + ENDP +@@ -439,7 +439,7 @@ ofrinter2_v6_lp + USAT16 r8, #8, r8 ; r8 = __22__00 + USAT16 r7, #8, r7 ; r7 = __33__11 + ORR r8, r8, r7, LSL #8 ; r8 = 33221100 +- STRD r8, [r0], r3 ++ STRD r8, r9, [r0], r3 + BGT ofrinter2_v6_lp + LDMFD r13!,{r4-r9,PC} + ENDP +diff --git a/lib/arm/armidct.s b/lib/arm/armidct.s +index 68530c7..269f74b 100644 +--- a/lib/arm/armidct.s ++++ b/lib/arm/armidct.s +@@ -875,7 +875,7 @@ idct2_1core_v6 PROC + LDR r3, OC_C4S4 + LDRSH r6, [r1], #16 ; r6 = x[1,0] + SMULWB r12,r3, r2 ; r12= t[0,0]=OC_C4S4*x[0,0]>>16 +- LDRD r4, OC_C7S1 ; r4 = OC_C7S1; r5 = OC_C1S7 ++ LDRD r4, r5, OC_C7S1 ; r4 = OC_C7S1; r5 = OC_C1S7 + SMULWB r6, r3, r6 ; r6 = t[1,0]=OC_C4S4*x[1,0]>>16 + SMULWT r4, r4, r2 ; r4 = t[0,4]=OC_C7S1*x[0,1]>>16 + SMULWT r7, r5, r2 ; r7 = t[0,7]=OC_C1S7*x[0,1]>>16 +@@ -937,7 +937,7 @@ idct2_2core_down_v6 PROC + MOV r7 ,#8 ; r7 = 8 + LDR r6, [r1], #16 ; r6 = + SMLAWB r12,r3, r2, r7 ; r12= (t[0,0]=OC_C4S4*x[0,0]>>16)+8 +- LDRD r4, OC_C7S1 ; r4 = OC_C7S1; r5 = OC_C1S7 ++ LDRD r4, r5, OC_C7S1 ; r4 = OC_C7S1; r5 = OC_C1S7 + SMLAWB r7, r3, r6, r7 ; r7 = (t[1,0]=OC_C4S4*x[1,0]>>16)+8 + SMULWT r5, r5, r2 ; r2 = t[0,7]=OC_C1S7*x[0,1]>>16 + PKHBT r12,r12,r7, LSL #16 ; r12= +@@ -1053,7 +1053,7 @@ idct3_2core_v6 PROC + ; r1 = const ogg_int16_t *_x (source) + ; Stage 1: + LDRD r4, [r1], #16 ; r4 = ; r5 = <*|x[0,2]> +- LDRD r10,OC_C6S2_3_v6 ; r10= OC_C6S2; r11= OC_C2S6 ++ LDRD r10, r11, OC_C6S2_3_v6 ; r10= OC_C6S2; r11= OC_C2S6 + ; Stall + SMULWB r3, r11,r5 ; r3 = t[0,3]=OC_C2S6*x[0,2]>>16 + LDR r11,OC_C4S4 +@@ -1132,12 +1132,12 @@ idct4_3core_v6 PROC + ; r1 = const ogg_int16_t *_x (source) + ; Stage 1: + LDRD r10,[r1], #16 ; r10= ; r11= +- LDRD r2, OC_C5S3_4_v6 ; r2 = OC_C5S3; r3 = OC_C3S5 ++ LDRD r2, r3, OC_C5S3_4_v6 ; r2 = OC_C5S3; r3 = OC_C3S5 + LDRD r4, [r1], #16 ; r4 = ; r5 = + SMULWT r9, r3, r11 ; r9 = t[0,6]=OC_C3S5*x[0,3]>>16 + SMULWT r8, r2, r11 ; r8 = -t[0,5]=OC_C5S3*x[0,3]>>16 + PKHBT r9, r9, r2 ; r9 = <0|t[0,6]> +- LDRD r6, OC_C6S2_4_v6 ; r6 = OC_C6S2; r7 = OC_C2S6 ++ LDRD r6, r7, OC_C6S2_4_v6 ; r6 = OC_C6S2; r7 = OC_C2S6 + PKHBT r8, r8, r2 ; r9 = <0|-t[0,5]> + SMULWB r3, r7, r11 ; r3 = t[0,3]=OC_C2S6*x[0,2]>>16 + SMULWB r2, r6, r11 ; r2 = t[0,2]=OC_C6S2*x[0,2]>>16 +@@ -1148,7 +1148,7 @@ idct4_3core_v6 PROC + SMULWB r12,r11,r10 ; r12= t[0,0]=OC_C4S4*x[0,0]>>16 + PKHBT r2, r2, r5, LSL #16 ; r2 = + SMULWB r5, r11,r4 ; r5 = t[1,0]=OC_C4S4*x[1,0]>>16 +- LDRD r6, OC_C7S1_4_v6 ; r6 = OC_C7S1; r7 = OC_C1S7 ++ LDRD r6, r7, OC_C7S1_4_v6 ; r6 = OC_C7S1; r7 = OC_C1S7 + PKHBT r12,r12,r5, LSL #16 ; r12= + SMULWT r5, r7, r4 ; r5 = t[1,7]=OC_C1S7*x[1,1]>>16 + SMULWT r7, r7, r10 ; r7 = t[0,7]=OC_C1S7*x[0,1]>>16 +@@ -1216,10 +1216,10 @@ idct4_4core_down_v6 PROC + ; r1 = const ogg_int16_t *_x (source) + ; Stage 1: + LDRD r10,[r1], #16 ; r10= ; r11= +- LDRD r2, OC_C5S3_4_v6 ; r2 = OC_C5S3; r3 = OC_C3S5 ++ LDRD r2, r3, OC_C5S3_4_v6 ; r2 = OC_C5S3; r3 = OC_C3S5 + LDRD r4, [r1], #16 ; r4 = ; r5 = + SMULWT r9, r3, r11 ; r9 = t[0,6]=OC_C3S5*x[0,3]>>16 +- LDRD r6, OC_C6S2_4_v6 ; r6 = OC_C6S2; r7 = OC_C2S6 ++ LDRD r6, r7, OC_C6S2_4_v6 ; r6 = OC_C6S2; r7 = OC_C2S6 + SMULWT r8, r2, r11 ; r8 = -t[0,5]=OC_C5S3*x[0,3]>>16 + ; Here we cheat: row 3 had just a DC, so x[0,3]==x[1,3] by definition. + PKHBT r9, r9, r9, LSL #16 ; r9 = +@@ -1234,7 +1234,7 @@ idct4_4core_down_v6 PROC + SMLAWB r12,r11,r10,r7 ; r12= t[0,0]+8=(OC_C4S4*x[0,0]>>16)+8 + PKHBT r2, r2, r5, LSL #16 ; r2 = + SMLAWB r5, r11,r4 ,r7 ; r5 = t[1,0]+8=(OC_C4S4*x[1,0]>>16)+8 +- LDRD r6, OC_C7S1_4_v6 ; r6 = OC_C7S1; r7 = OC_C1S7 ++ LDRD r6, r7, OC_C7S1_4_v6 ; r6 = OC_C7S1; r7 = OC_C1S7 + PKHBT r12,r12,r5, LSL #16 ; r12= + SMULWT r5, r7, r4 ; r5 = t[1,7]=OC_C1S7*x[1,1]>>16 + SMULWT r7, r7, r10 ; r7 = t[0,7]=OC_C1S7*x[0,1]>>16 +@@ -1264,7 +1264,7 @@ idct8_8core_v6 PROC + STMFD r13!,{r0,r14} + ; Stage 1: + ;5-6 rotation by 3pi/16 +- LDRD r10,OC_C5S3_4_v6 ; r10= OC_C5S3, r11= OC_C3S5 ++ LDRD r10, r11, OC_C5S3_4_v6 ; r10= OC_C5S3, r11= OC_C3S5 + LDR r4, [r1,#8] ; r4 = + LDR r7, [r1,#24] ; r7 = + SMULWT r5, r11,r4 ; r5 = OC_C3S5*x[0,5]>>16 +@@ -1281,7 +1281,7 @@ idct8_8core_v6 PROC + PKHBT r6, r6, r11,LSL #16 ; r6 = + SMULWT r8, r10,r12 ; r8 = OC_C5S3*x[1,3]>>16 + ;2-3 rotation by 6pi/16 +- LDRD r10,OC_C6S2_4_v6 ; r10= OC_C6S2, r11= OC_C2S6 ++ LDRD r10, r11, OC_C6S2_4_v6 ; r10= OC_C6S2, r11= OC_C2S6 + PKHBT r3, r3, r8, LSL #16 ; r3 = + LDR r8, [r1,#12] ; r8 = + SMULWB r2, r10,r0 ; r2 = OC_C6S2*x[0,2]>>16 +@@ -1297,7 +1297,7 @@ idct8_8core_v6 PROC + PKHBT r3, r3, r10,LSL #16 ; r3 = + SMULWB r12,r11,r7 ; r12= OC_C2S6*x[1,6]>>16 + ;4-7 rotation by 7pi/16 +- LDRD r10,OC_C7S1_8_v6 ; r10= OC_C7S1, r11= OC_C1S7 ++ LDRD r10, r11, OC_C7S1_8_v6 ; r10= OC_C7S1, r11= OC_C1S7 + PKHBT r9, r9, r12,LSL #16 ; r9 = + LDR r0, [r1],#16 ; r0 = + PKHTB r7, r7, r8, ASR #16 ; r7 = +@@ -1363,7 +1363,7 @@ idct8_8core_down_v6 PROC + STMFD r13!,{r0,r14} + ; Stage 1: + ;5-6 rotation by 3pi/16 +- LDRD r10,OC_C5S3_8_v6 ; r10= OC_C5S3, r11= OC_C3S5 ++ LDRD r10, r11, OC_C5S3_8_v6 ; r10= OC_C5S3, r11= OC_C3S5 + LDR r4, [r1,#8] ; r4 = + LDR r7, [r1,#24] ; r7 = + SMULWT r5, r11,r4 ; r5 = OC_C3S5*x[0,5]>>16 +@@ -1380,7 +1380,7 @@ idct8_8core_down_v6 PROC + PKHBT r6, r6, r11,LSL #16 ; r6 = + SMULWT r8, r10,r12 ; r8 = OC_C5S3*x[1,3]>>16 + ;2-3 rotation by 6pi/16 +- LDRD r10,OC_C6S2_8_v6 ; r10= OC_C6S2, r11= OC_C2S6 ++ LDRD r10, r11, OC_C6S2_8_v6 ; r10= OC_C6S2, r11= OC_C2S6 + PKHBT r3, r3, r8, LSL #16 ; r3 = + LDR r8, [r1,#12] ; r8 = + SMULWB r2, r10,r0 ; r2 = OC_C6S2*x[0,2]>>16 +@@ -1396,7 +1396,7 @@ idct8_8core_down_v6 PROC + PKHBT r3, r3, r10,LSL #16 ; r3 = + SMULWB r12,r11,r7 ; r12= OC_C2S6*x[1,6]>>16 + ;4-7 rotation by 7pi/16 +- LDRD r10,OC_C7S1_8_v6 ; r10= OC_C7S1, r11= OC_C1S7 ++ LDRD r10, r11, OC_C7S1_8_v6 ; r10= OC_C7S1, r11= OC_C1S7 + PKHBT r9, r9, r12,LSL #16 ; r9 = + LDR r0, [r1],#16 ; r0 = + PKHTB r7, r7, r8, ASR #16 ; r7 = +-- +2.39.1 + -- cgit v1.2.3