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| author | Daniel Baumann <daniel.baumann@progress-linux.org> | 2024-04-19 01:13:27 +0000 |
|---|---|---|
| committer | Daniel Baumann <daniel.baumann@progress-linux.org> | 2024-04-19 01:13:27 +0000 |
| commit | 40a355a42d4a9444dc753c04c6608dade2f06a23 (patch) | |
| tree | 871fc667d2de662f171103ce5ec067014ef85e61 /js/src/jit/loong64/Assembler-loong64.h | |
| parent | Adding upstream version 124.0.1. (diff) | |
| download | firefox-adbda400be353e676059e335c3c0aaf99e719475.tar.xz firefox-adbda400be353e676059e335c3c0aaf99e719475.zip | |
Adding upstream version 125.0.1.upstream/125.0.1
Signed-off-by: Daniel Baumann <daniel.baumann@progress-linux.org>
Diffstat (limited to 'js/src/jit/loong64/Assembler-loong64.h')
| -rw-r--r-- | js/src/jit/loong64/Assembler-loong64.h | 11 |
1 files changed, 8 insertions, 3 deletions
diff --git a/js/src/jit/loong64/Assembler-loong64.h b/js/src/jit/loong64/Assembler-loong64.h index 4e0b8d6b66..a385d71f5f 100644 --- a/js/src/jit/loong64/Assembler-loong64.h +++ b/js/src/jit/loong64/Assembler-loong64.h @@ -309,6 +309,7 @@ static const uint32_t Imm26Shift = 0; static const uint32_t Imm26Bits = 26; static const uint32_t CODEShift = 0; static const uint32_t CODEBits = 15; +static const uint32_t HINTBits = 5; // LoongArch instruction field bit masks. static const uint32_t RJMask = (1 << RJBits) - 1; @@ -316,7 +317,9 @@ static const uint32_t RKMask = (1 << RKBits) - 1; static const uint32_t RDMask = (1 << RDBits) - 1; static const uint32_t SA2Mask = (1 << SA2Bits) - 1; static const uint32_t SA3Mask = (1 << SA3Bits) - 1; +static const uint32_t CDMask = (1 << CDBits) - 1; static const uint32_t CONDMask = (1 << CONDBits) - 1; +static const uint32_t HINTMask = (1 << HINTBits) - 1; static const uint32_t LSBWMask = (1 << LSBWBits) - 1; static const uint32_t LSBDMask = (1 << LSBDBits) - 1; static const uint32_t MSBWMask = (1 << MSBWBits) - 1; @@ -1611,7 +1614,7 @@ class InstReg : public Instruction { InstReg(OpcodeField op, int32_t cond, FloatRegister fk, FloatRegister fj, AssemblerLOONG64::FPConditionBit cd) : Instruction(op | (cond & CONDMask) << CONDShift | FK(fk) | FJ(fj) | - (cd & RDMask)) { + (cd & CDMask)) { MOZ_ASSERT(is_uintN(cond, 5)); } @@ -1700,7 +1703,7 @@ class InstImm : public Instruction { } InstImm(OpcodeField op, int32_t si12, Register rj, int32_t hint) : Instruction(op | (si12 & Imm12Mask) << Imm12Shift | RJ(rj) | - (hint & RDMask)) { + (hint & HINTMask)) { MOZ_ASSERT(op == op_preld); } InstImm(OpcodeField op, int32_t msb, int32_t lsb, Register rj, Register rd, @@ -1738,7 +1741,9 @@ class InstImm : public Instruction { uint32_t extractRJ() { return extractBitField(RJShift + RJBits - 1, RJShift); } - void setRJ(uint32_t rj) { data = (data & ~RJMask) | (rj << RJShift); } + void setRJ(uint32_t rj) { + data = (data & ~(RJMask << RJShift)) | (rj << RJShift); + } uint32_t extractRD() { return extractBitField(RDShift + RDBits - 1, RDShift); } |