diff options
Diffstat (limited to 'third_party/rust/cpufeatures')
| -rw-r--r-- | third_party/rust/cpufeatures/.cargo-checksum.json | 1 | ||||
| -rw-r--r-- | third_party/rust/cpufeatures/CHANGELOG.md | 113 | ||||
| -rw-r--r-- | third_party/rust/cpufeatures/Cargo.toml | 41 | ||||
| -rw-r--r-- | third_party/rust/cpufeatures/LICENSE-APACHE | 201 | ||||
| -rw-r--r-- | third_party/rust/cpufeatures/LICENSE-MIT | 25 | ||||
| -rw-r--r-- | third_party/rust/cpufeatures/README.md | 106 | ||||
| -rw-r--r-- | third_party/rust/cpufeatures/src/aarch64.rs | 154 | ||||
| -rw-r--r-- | third_party/rust/cpufeatures/src/lib.rs | 183 | ||||
| -rw-r--r-- | third_party/rust/cpufeatures/src/miri.rs | 20 | ||||
| -rw-r--r-- | third_party/rust/cpufeatures/src/x86.rs | 145 | ||||
| -rw-r--r-- | third_party/rust/cpufeatures/tests/aarch64.rs | 17 | ||||
| -rw-r--r-- | third_party/rust/cpufeatures/tests/x86.rs | 17 |
12 files changed, 1023 insertions, 0 deletions
diff --git a/third_party/rust/cpufeatures/.cargo-checksum.json b/third_party/rust/cpufeatures/.cargo-checksum.json new file mode 100644 index 0000000000..bcc82d15c2 --- /dev/null +++ b/third_party/rust/cpufeatures/.cargo-checksum.json @@ -0,0 +1 @@ +{"files":{"CHANGELOG.md":"688a7222c5a7a23c1095f3d38983c7b529230858e3f5600c1115baf1d81b9809","Cargo.toml":"e23fc3baf256869f019907444cce751c17c5b36d681d5e866cdccc7b1d0a12d9","LICENSE-APACHE":"a9040321c3712d8fd0b09cf52b17445de04a23a10165049ae187cd39e5c86be5","LICENSE-MIT":"904801faf3f1850328af8e1aa1047b9190cc22ed40df5c87f2d93d17f847ef67","README.md":"3a7469c8306dce5e6c1b4eb3f9d7290174e57e9118911e016a06192bc89ae67f","src/aarch64.rs":"03780cca3518699dd0f57345c9fda1cae7d73a3a77c7f1802f7f172204417694","src/lib.rs":"6e5c3f23006241c3135e8df7d25fb68ca8ee768d065a08db7910a4fcaa786a28","src/miri.rs":"acf1a7e7ae31a1de07941084c6b589a2d4c6ea5f87012c811592c865d04c02cb","src/x86.rs":"f4a17990a3a8c1e8286bdda35d19fa1372e0548341ca205f1e7e417fa3f3e966","tests/aarch64.rs":"bdabbe67316c128b57003ba5faa07707b5f339b1f3e984da4bc383cc93c2bedd","tests/x86.rs":"fcf476ca6ebd0845ab547cea4fe40c2ba2a2324c024264d9a86f666586f3a480"},"package":"03e69e28e9f7f77debdedbaafa2866e1de9ba56df55a8bd7cfc724c25a09987c"}
\ No newline at end of file diff --git a/third_party/rust/cpufeatures/CHANGELOG.md b/third_party/rust/cpufeatures/CHANGELOG.md new file mode 100644 index 0000000000..a0533ef40e --- /dev/null +++ b/third_party/rust/cpufeatures/CHANGELOG.md @@ -0,0 +1,113 @@ +# Changelog + +All notable changes to this project will be documented in this file. + +The format is based on [Keep a Changelog](https://keepachangelog.com/en/1.0.0/), +and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0.html). + +## 0.2.8 (2023-06-15) +### Fixed +- Check OS register support on x86 targets ([#919]) + +[#919]: https://github.com/RustCrypto/utils/issues/919 + +## 0.2.7 (2023-04-20) +### Added +- Support freestanding/UEFI `x86` targets ([#821]) + +[#821]: https://github.com/RustCrypto/utils/issues/821 + +## 0.2.6 (2023-03-24) +### Added +- Support dynamic feature detection on iOS and derivative platforms ([#848]) +- Support for detecting AVX-512 target features ([#862]) + +[#848]: https://github.com/RustCrypto/utils/issues/848 +[#862]: https://github.com/RustCrypto/utils/pull/862 + +## 0.2.5 (2022-09-04) +### Fixed +- Add workaround for [CPUID bug] in `std` ([#800]) + +[CPUID bug]: https://github.com/rust-lang/rust/issues/101346 +[#800]: https://github.com/RustCrypto/utils/pull/800 + +## 0.2.4 (2022-08-22) [YANKED] +- Re-release v0.2.3 without any changes to fix [#795] ([#796]) + +[#795]: https://github.com/RustCrypto/utils/issues/795 +[#796]: https://github.com/RustCrypto/utils/pull/796 + +## 0.2.3 (2022-08-18) [YANKED] +### Changed +- Update `libc` version to v0.2.95 ([#789]) +- Disable all target features under MIRI ([#779]) +- Check AVX availability when detecting AVX2 and FMA ([#792]) + +[#779]: https://github.com/RustCrypto/utils/pull/779 +[#789]: https://github.com/RustCrypto/utils/pull/789 +[#792]: https://github.com/RustCrypto/utils/pull/792 + +## 0.2.2 (2022-03-18) [YANKED] +### Added +- Support for Android on `aarch64` ([#752]) + +### Removed +- Vestigial code around `crypto` target feature ([#600]) + +[#600]: https://github.com/RustCrypto/utils/pull/600 +[#752]: https://github.com/RustCrypto/utils/pull/752 + +## 0.2.1 (2021-08-26) [YANKED] +### Changed +- Revert [#583] "Use from_bytes_with_nul for string check" ([#597]) + +[#583]: https://github.com/RustCrypto/utils/pull/583 +[#597]: https://github.com/RustCrypto/utils/pull/597 + +## 0.2.0 (2021-08-26) [YANKED] +### Removed +- AArch64 `crypto` target feature ([#594]) + +[#594]: https://github.com/RustCrypto/utils/pull/594 + +## 0.1.5 (2021-06-21) +### Added +- iOS support ([#435], [#501]) + +### Changed +- Map `aarch64` HWCAPs to target features; add `crypto` ([#456]) + +[#435]: https://github.com/RustCrypto/utils/pull/435 +[#456]: https://github.com/RustCrypto/utils/pull/456 +[#501]: https://github.com/RustCrypto/utils/pull/501 + +## 0.1.4 (2021-05-14) +### Added +- Support compiling on non-Linux/macOS aarch64 targets ([#408]) + +[#408]: https://github.com/RustCrypto/utils/pull/408 + +## 0.1.3 (2021-05-13) +### Removed +- `neon` on `aarch64` targets: already enabled by default ([#406]) + +[#406]: https://github.com/RustCrypto/utils/pull/406 + +## 0.1.2 (2021-05-13) [YANKED] +### Added +- `neon` feature detection on `aarch64` targets ([#403]) + +### Fixed +- Support for `musl`-based targets ([#403]) + +[#403]: https://github.com/RustCrypto/utils/pull/403 + +## 0.1.1 (2021-05-06) +### Added +- `aarch64` support for Linux and macOS/M4 targets ([#393]) + +[#393]: https://github.com/RustCrypto/utils/pull/393 + +## 0.1.0 (2021-04-29) +- Initial release diff --git a/third_party/rust/cpufeatures/Cargo.toml b/third_party/rust/cpufeatures/Cargo.toml new file mode 100644 index 0000000000..2f8eee1ad9 --- /dev/null +++ b/third_party/rust/cpufeatures/Cargo.toml @@ -0,0 +1,41 @@ +# THIS FILE IS AUTOMATICALLY GENERATED BY CARGO +# +# When uploading crates to the registry Cargo will automatically +# "normalize" Cargo.toml files for maximal compatibility +# with all versions of Cargo and also rewrite `path` dependencies +# to registry (e.g., crates.io) dependencies. +# +# If you are reading this file be aware that the original Cargo.toml +# will likely look very different (and much more reasonable). +# See Cargo.toml.orig for the original contents. + +[package] +edition = "2018" +name = "cpufeatures" +version = "0.2.8" +authors = ["RustCrypto Developers"] +description = """ +Lightweight runtime CPU feature detection for x86/x86_64 and aarch64 with +no_std support and support for mobile targets including Android and iOS +""" +documentation = "https://docs.rs/cpufeatures" +readme = "README.md" +keywords = [ + "cpuid", + "target-feature", +] +categories = [ + "hardware-support", + "no-std", +] +license = "MIT OR Apache-2.0" +repository = "https://github.com/RustCrypto/utils" + +[target.aarch64-linux-android.dependencies.libc] +version = "0.2.95" + +[target."cfg(all(target_arch = \"aarch64\", target_os = \"linux\"))".dependencies.libc] +version = "0.2.95" + +[target."cfg(all(target_arch = \"aarch64\", target_vendor = \"apple\"))".dependencies.libc] +version = "0.2.95" diff --git a/third_party/rust/cpufeatures/LICENSE-APACHE b/third_party/rust/cpufeatures/LICENSE-APACHE new file mode 100644 index 0000000000..78173fa2e7 --- /dev/null +++ b/third_party/rust/cpufeatures/LICENSE-APACHE @@ -0,0 +1,201 @@ + Apache License + Version 2.0, January 2004 + http://www.apache.org/licenses/ + +TERMS AND CONDITIONS FOR USE, REPRODUCTION, AND DISTRIBUTION + +1. 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IN NO EVENT +SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY +CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION +OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR +IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER +DEALINGS IN THE SOFTWARE. diff --git a/third_party/rust/cpufeatures/README.md b/third_party/rust/cpufeatures/README.md new file mode 100644 index 0000000000..273789d74f --- /dev/null +++ b/third_party/rust/cpufeatures/README.md @@ -0,0 +1,106 @@ +# [RustCrypto]: CPU Feature Detection + +[![crate][crate-image]][crate-link] +[![Docs][docs-image]][docs-link] +![Apache2/MIT licensed][license-image] +![Rust Version][rustc-image] +[![Project Chat][chat-image]][chat-link] +[![Build Status][build-image]][build-link] + +Lightweight and efficient runtime CPU feature detection for `aarch64` and +`x86`/`x86_64` targets. + +Supports `no_std` as well as mobile targets including iOS and Android, +providing an alternative to the `std`-dependent `is_x86_feature_detected!` +macro. + +[Documentation][docs-link] + +## Supported architectures + +# Supported target architectures + +*NOTE: target features with an asterisk are unstable (nightly-only) and subject +to change to match upstream name changes in the Rust standard library. + +## `aarch64` + +Linux, iOS, and macOS/ARM only (ARM64 does not support OS-independent feature detection) + +Target features: + +- `aes`* +- `sha2`* +- `sha3`* + +## `x86`/`x86_64` + +OS independent and `no_std`-friendly + +Target features: + +- `adx` +- `aes` +- `avx` +- `avx2` +- `avx512bw`* +- `avx512cd`* +- `avx512dq`* +- `avx512er`* +- `avx512f`* +- `avx512ifma`* +- `avx512pf`* +- `avx512vl`* +- `bmi1` +- `bmi2` +- `fma`, +- `mmx` +- `pclmulqdq` +- `popcnt` +- `rdrand` +- `rdseed` +- `sgx` +- `sha` +- `sse` +- `sse2` +- `sse3` +- `sse4.1` +- `sse4.2` +- `ssse3` + +If you would like detection support for a target feature which is not on +this list, please [open a GitHub issue]. + +## License + +Licensed under either of: + + * [Apache License, Version 2.0](http://www.apache.org/licenses/LICENSE-2.0) + * [MIT license](http://opensource.org/licenses/MIT) + +at your option. + +### Contribution + +Unless you explicitly state otherwise, any contribution intentionally submitted +for inclusion in the work by you, as defined in the Apache-2.0 license, shall be +dual licensed as above, without any additional terms or conditions. + +[//]: # (badges) + +[crate-image]: https://img.shields.io/crates/v/cpufeatures.svg +[crate-link]: https://crates.io/crates/cpufeatures +[docs-image]: https://docs.rs/cpufeatures/badge.svg +[docs-link]: https://docs.rs/cpufeatures/ +[license-image]: https://img.shields.io/badge/license-Apache2.0/MIT-blue.svg +[rustc-image]: https://img.shields.io/badge/rustc-1.40+-blue.svg +[chat-image]: https://img.shields.io/badge/zulip-join_chat-blue.svg +[chat-link]: https://rustcrypto.zulipchat.com/#narrow/stream/260052-utils +[build-image]: https://github.com/RustCrypto/utils/workflows/cpufeatures/badge.svg?branch=master&event=push +[build-link]: https://github.com/RustCrypto/utils/actions/workflows/cpufeatures.yml + +[//]: # (general links) + +[RustCrypto]: https://github.com/rustcrypto +[RustCrypto/utils#378]: https://github.com/RustCrypto/utils/issues/378 +[open a GitHub issue]: https://github.com/RustCrypto/utils/issues/new?title=cpufeatures:%20requesting%20support%20for%20CHANGEME%20target%20feature diff --git a/third_party/rust/cpufeatures/src/aarch64.rs b/third_party/rust/cpufeatures/src/aarch64.rs new file mode 100644 index 0000000000..2c9a044b07 --- /dev/null +++ b/third_party/rust/cpufeatures/src/aarch64.rs @@ -0,0 +1,154 @@ +//! ARM64 CPU feature detection support. +//! +//! Unfortunately ARM instructions to detect CPU features cannot be called from +//! unprivileged userspace code, so this implementation relies on OS-specific +//! APIs for feature detection. + +// Evaluate the given `$body` expression any of the supplied target features +// are not enabled. Otherwise returns true. +#[macro_export] +#[doc(hidden)] +macro_rules! __unless_target_features { + ($($tf:tt),+ => $body:expr ) => { + { + #[cfg(not(all($(target_feature=$tf,)*)))] + $body + + #[cfg(all($(target_feature=$tf,)*))] + true + } + }; +} + +// Linux runtime detection of target CPU features using `getauxval`. +#[cfg(any(target_os = "linux", target_os = "android"))] +#[macro_export] +#[doc(hidden)] +macro_rules! __detect_target_features { + ($($tf:tt),+) => {{ + let hwcaps = $crate::aarch64::getauxval_hwcap(); + $($crate::check!(hwcaps, $tf) & )+ true + }}; +} + +/// Linux helper function for calling `getauxval` to get `AT_HWCAP`. +#[cfg(any(target_os = "linux", target_os = "android"))] +pub fn getauxval_hwcap() -> u64 { + unsafe { libc::getauxval(libc::AT_HWCAP) } +} + +// Apple platform's runtime detection of target CPU features using `sysctlbyname`. +#[cfg(target_vendor = "apple")] +#[macro_export] +#[doc(hidden)] +macro_rules! __detect_target_features { + ($($tf:tt),+) => {{ + $($crate::check!($tf) & )+ true + }}; +} + +// Linux `expand_check_macro` +#[cfg(any(target_os = "linux", target_os = "android"))] +macro_rules! __expand_check_macro { + ($(($name:tt, $hwcap:ident)),* $(,)?) => { + #[macro_export] + #[doc(hidden)] + macro_rules! check { + $( + ($hwcaps:expr, $name) => { + (($hwcaps & $crate::aarch64::hwcaps::$hwcap) != 0) + }; + )* + } + }; +} + +// Linux `expand_check_macro` +#[cfg(any(target_os = "linux", target_os = "android"))] +__expand_check_macro! { + ("aes", AES), // Enable AES support. + ("sha2", SHA2), // Enable SHA1 and SHA256 support. + ("sha3", SHA3), // Enable SHA512 and SHA3 support. +} + +/// Linux hardware capabilities mapped to target features. +/// +/// Note that LLVM target features are coarser grained than what Linux supports +/// and imply more capabilities under each feature. This module attempts to +/// provide that mapping accordingly. +/// +/// See this issue for more info: <https://github.com/RustCrypto/utils/issues/395> +#[cfg(any(target_os = "linux", target_os = "android"))] +pub mod hwcaps { + use libc::c_ulong; + + pub const AES: c_ulong = libc::HWCAP_AES | libc::HWCAP_PMULL; + pub const SHA2: c_ulong = libc::HWCAP_SHA2; + pub const SHA3: c_ulong = libc::HWCAP_SHA3 | libc::HWCAP_SHA512; +} + +// Apple OS (macOS, iOS, watchOS, and tvOS) `check!` macro. +// +// NOTE: several of these instructions (e.g. `aes`, `sha2`) can be assumed to +// be present on all Apple ARM64 hardware. +// +// Newer CPU instructions now have nodes within sysctl's `hw.optional` +// namespace, however the ones that do not can safely be assumed to be +// present on all Apple ARM64 devices, now and for the foreseeable future. +// +// See discussion on this issue for more information: +// <https://github.com/RustCrypto/utils/issues/378> +#[cfg(target_vendor = "apple")] +#[macro_export] +#[doc(hidden)] +macro_rules! check { + ("aes") => { + true + }; + ("sha2") => { + true + }; + ("sha3") => { + unsafe { + // `sha3` target feature implies SHA-512 as well + $crate::aarch64::sysctlbyname(b"hw.optional.armv8_2_sha512\0") + && $crate::aarch64::sysctlbyname(b"hw.optional.armv8_2_sha3\0") + } + }; +} + +/// Apple helper function for calling `sysctlbyname`. +#[cfg(target_vendor = "apple")] +pub unsafe fn sysctlbyname(name: &[u8]) -> bool { + assert_eq!( + name.last().cloned(), + Some(0), + "name is not NUL terminated: {:?}", + name + ); + + let mut value: u32 = 0; + let mut size = core::mem::size_of::<u32>(); + + let rc = libc::sysctlbyname( + name.as_ptr() as *const i8, + &mut value as *mut _ as *mut libc::c_void, + &mut size, + core::ptr::null_mut(), + 0, + ); + + assert_eq!(size, 4, "unexpected sysctlbyname(3) result size"); + assert_eq!(rc, 0, "sysctlbyname returned error code: {}", rc); + value != 0 +} + +// On other targets, runtime CPU feature detection is unavailable +#[cfg(not(any(target_vendor = "apple", target_os = "linux", target_os = "android",)))] +#[macro_export] +#[doc(hidden)] +macro_rules! __detect_target_features { + ($($tf:tt),+) => { + false + }; +} diff --git a/third_party/rust/cpufeatures/src/lib.rs b/third_party/rust/cpufeatures/src/lib.rs new file mode 100644 index 0000000000..dfd1feab72 --- /dev/null +++ b/third_party/rust/cpufeatures/src/lib.rs @@ -0,0 +1,183 @@ +//! This crate provides macros for runtime CPU feature detection. It's intended +//! as a stopgap until Rust [RFC 2725] adding first-class target feature detection +//! macros to `libcore` is implemented. +//! +//! # Supported target architectures +//! +//! *NOTE: target features with an asterisk are unstable (nightly-only) and +//! subject to change to match upstream name changes in the Rust standard +//! library. +//! +//! ## `aarch64` +//! +//! Linux, iOS, and macOS/ARM only (ARM64 does not support OS-independent feature detection) +//! +//! Target features: +//! +//! - `aes`* +//! - `sha2`* +//! - `sha3`* +//! +//! ## `x86`/`x86_64` +//! +//! OS independent and `no_std`-friendly +//! +//! Target features: +//! +//! - `adx` +//! - `aes` +//! - `avx` +//! - `avx2` +//! - `avx512bw`* +//! - `avx512cd`* +//! - `avx512dq`* +//! - `avx512er`* +//! - `avx512f`* +//! - `avx512ifma`* +//! - `avx512pf`* +//! - `avx512vl`* +//! - `bmi1` +//! - `bmi2` +//! - `fma`, +//! - `mmx` +//! - `pclmulqdq` +//! - `popcnt` +//! - `rdrand` +//! - `rdseed` +//! - `sgx` +//! - `sha` +//! - `sse` +//! - `sse2` +//! - `sse3` +//! - `sse4.1` +//! - `sse4.2` +//! - `ssse3` +//! +//! If you would like detection support for a target feature which is not on +//! this list, please [open a GitHub issue][gh]. +//! +//! # Example +//! ``` +//! # #[cfg(any(target_arch = "x86", target_arch = "x86_64"))] +//! # { +//! // This macro creates `cpuid_aes_sha` module +//! cpufeatures::new!(cpuid_aes_sha, "aes", "sha"); +//! +//! // `token` is a Zero Sized Type (ZST) value, which guarantees +//! // that underlying static storage got properly initialized, +//! // which allows to omit initialization branch +//! let token: cpuid_aes_sha::InitToken = cpuid_aes_sha::init(); +//! +//! if token.get() { +//! println!("CPU supports both SHA and AES extensions"); +//! } else { +//! println!("SHA and AES extensions are not supported"); +//! } +//! +//! // If stored value needed only once you can get stored value +//! // omitting the token +//! let val = cpuid_aes_sha::get(); +//! assert_eq!(val, token.get()); +//! +//! // Additionally you can get both token and value +//! let (token, val) = cpuid_aes_sha::init_get(); +//! assert_eq!(val, token.get()); +//! # } +//! ``` +//! +//! Note that if all tested target features are enabled via compiler options +//! (e.g. by using `RUSTFLAGS`), the `get` method will always return `true` +//! and `init` will not use CPUID instruction. Such behavior allows +//! compiler to completely eliminate fallback code. +//! +//! After first call macro caches result and returns it in subsequent +//! calls, thus runtime overhead for them is minimal. +//! +//! [RFC 2725]: https://github.com/rust-lang/rfcs/pull/2725 +//! [gh]: https://github.com/RustCrypto/utils/issues/new?title=cpufeatures:%20requesting%20support%20for%20CHANGEME%20target%20feature + +#![no_std] +#![doc( + html_logo_url = "https://raw.githubusercontent.com/RustCrypto/media/6ee8e381/logo.svg", + html_favicon_url = "https://raw.githubusercontent.com/RustCrypto/media/6ee8e381/logo.svg" +)] + +#[cfg(not(miri))] +#[cfg(all(target_arch = "aarch64"))] +#[doc(hidden)] +pub mod aarch64; + +#[cfg(not(miri))] +#[cfg(any(target_arch = "x86", target_arch = "x86_64"))] +mod x86; + +#[cfg(miri)] +mod miri; + +#[cfg(not(any(target_arch = "aarch64", target_arch = "x86", target_arch = "x86_64")))] +compile_error!("This crate works only on `aarch64`, `x86`, and `x86-64` targets."); + +/// Create module with CPU feature detection code. +#[macro_export] +macro_rules! new { + ($mod_name:ident, $($tf:tt),+ $(,)?) => { + mod $mod_name { + use core::sync::atomic::{AtomicU8, Ordering::Relaxed}; + + const UNINIT: u8 = u8::max_value(); + static STORAGE: AtomicU8 = AtomicU8::new(UNINIT); + + /// Initialization token + #[derive(Copy, Clone, Debug)] + pub struct InitToken(()); + + impl InitToken { + /// Get initialized value + #[inline(always)] + pub fn get(&self) -> bool { + $crate::__unless_target_features! { + $($tf),+ => { + STORAGE.load(Relaxed) == 1 + } + } + } + } + + /// Initialize underlying storage if needed and get + /// stored value and initialization token. + #[inline] + pub fn init_get() -> (InitToken, bool) { + let res = $crate::__unless_target_features! { + $($tf),+ => { + // Relaxed ordering is fine, as we only have a single atomic variable. + let val = STORAGE.load(Relaxed); + + if val == UNINIT { + let res = $crate::__detect_target_features!($($tf),+); + STORAGE.store(res as u8, Relaxed); + res + } else { + val == 1 + } + } + }; + + (InitToken(()), res) + } + + /// Initialize underlying storage if needed and get + /// initialization token. + #[inline] + pub fn init() -> InitToken { + init_get().0 + } + + /// Initialize underlying storage if needed and get + /// stored value. + #[inline] + pub fn get() -> bool { + init_get().1 + } + } + }; +} diff --git a/third_party/rust/cpufeatures/src/miri.rs b/third_party/rust/cpufeatures/src/miri.rs new file mode 100644 index 0000000000..8dff21c13e --- /dev/null +++ b/third_party/rust/cpufeatures/src/miri.rs @@ -0,0 +1,20 @@ +//! Minimal miri support. +//! +//! Miri is an interpreter, and though it tries to emulate the target CPU +//! it does not support any target features. + +#[macro_export] +#[doc(hidden)] +macro_rules! __unless_target_features { + ($($tf:tt),+ => $body:expr ) => { + false + }; +} + +#[macro_export] +#[doc(hidden)] +macro_rules! __detect_target_features { + ($($tf:tt),+) => { + false + }; +} diff --git a/third_party/rust/cpufeatures/src/x86.rs b/third_party/rust/cpufeatures/src/x86.rs new file mode 100644 index 0000000000..2199f2779d --- /dev/null +++ b/third_party/rust/cpufeatures/src/x86.rs @@ -0,0 +1,145 @@ +//! x86/x86-64 CPU feature detection support. +//! +//! Portable, `no_std`-friendly implementation that relies on the x86 `CPUID` +//! instruction for feature detection. + +/// Evaluate the given `$body` expression any of the supplied target features +/// are not enabled. Otherwise returns true. +/// +/// The `$body` expression is not evaluated on SGX targets, and returns false +/// on these targets unless *all* supplied target features are enabled. +#[macro_export] +#[doc(hidden)] +macro_rules! __unless_target_features { + ($($tf:tt),+ => $body:expr ) => {{ + #[cfg(not(all($(target_feature=$tf,)*)))] + { + #[cfg(not(any(target_env = "sgx", target_os = "", target_os = "uefi")))] + $body + + // CPUID is not available on SGX. Freestanding and UEFI targets + // do not support SIMD features with default compilation flags. + #[cfg(any(target_env = "sgx", target_os = "", target_os = "uefi"))] + false + } + + #[cfg(all($(target_feature=$tf,)*))] + true + }}; +} + +/// Use CPUID to detect the presence of all supplied target features. +#[macro_export] +#[doc(hidden)] +macro_rules! __detect_target_features { + ($($tf:tt),+) => {{ + #[cfg(target_arch = "x86")] + use core::arch::x86::{__cpuid, __cpuid_count, CpuidResult}; + #[cfg(target_arch = "x86_64")] + use core::arch::x86_64::{__cpuid, __cpuid_count, CpuidResult}; + + // These wrappers are workarounds around + // https://github.com/rust-lang/rust/issues/101346 + // + // DO NOT remove it until MSRV is bumped to a version + // with the issue fix (at least 1.64). + #[inline(never)] + unsafe fn cpuid(leaf: u32) -> CpuidResult { + __cpuid(leaf) + } + + #[inline(never)] + unsafe fn cpuid_count(leaf: u32, sub_leaf: u32) -> CpuidResult { + __cpuid_count(leaf, sub_leaf) + } + + let cr = unsafe { + [cpuid(1), cpuid_count(7, 0)] + }; + + $($crate::check!(cr, $tf) & )+ true + }}; +} + +/// Check that OS supports required SIMD registers +#[macro_export] +#[doc(hidden)] +macro_rules! __xgetbv { + ($cr:expr, $mask:expr) => {{ + #[cfg(target_arch = "x86")] + use core::arch::x86 as arch; + #[cfg(target_arch = "x86_64")] + use core::arch::x86_64 as arch; + + // Check bits 26 and 27 + let xmask = 0b11 << 26; + let xsave = $cr[0].ecx & xmask == xmask; + if xsave { + let xcr0 = unsafe { arch::_xgetbv(arch::_XCR_XFEATURE_ENABLED_MASK) }; + (xcr0 & $mask) == $mask + } else { + false + } + }}; +} + +macro_rules! __expand_check_macro { + ($(($name:tt, $reg_cap:tt $(, $i:expr, $reg:ident, $offset:expr)*)),* $(,)?) => { + #[macro_export] + #[doc(hidden)] + macro_rules! check { + $( + ($cr:expr, $name) => {{ + // Register bits are listed here: + // https://wiki.osdev.org/CPU_Registers_x86#Extended_Control_Registers + let reg_cap = match $reg_cap { + // Bit 1 + "xmm" => $crate::__xgetbv!($cr, 0b10), + // Bits 1 and 2 + "ymm" => $crate::__xgetbv!($cr, 0b110), + // Bits 1, 2, 5, 6, and 7 + "zmm" => $crate::__xgetbv!($cr, 0b1110_0110), + _ => true, + }; + reg_cap + $( + & ($cr[$i].$reg & (1 << $offset) != 0) + )* + }}; + )* + } + }; +} + +__expand_check_macro! { + ("sse3", "xmm", 0, ecx, 0), + ("pclmulqdq", "xmm", 0, ecx, 1), + ("ssse3", "xmm", 0, ecx, 9), + ("fma", "xmm", 0, ecx, 12, 0, ecx, 28), + ("sse4.1", "xmm", 0, ecx, 19), + ("sse4.2", "xmm", 0, ecx, 20), + ("popcnt", "", 0, ecx, 23), + ("aes", "xmm", 0, ecx, 25), + ("avx", "xmm", 0, ecx, 28), + ("rdrand", "", 0, ecx, 30), + + ("mmx", "", 0, edx, 23), + ("sse", "xmm", 0, edx, 25), + ("sse2", "xmm", 0, edx, 26), + + ("sgx", "", 1, ebx, 2), + ("bmi1", "", 1, ebx, 3), + ("bmi2", "", 1, ebx, 8), + ("avx2", "ymm", 1, ebx, 5, 0, ecx, 28), + ("avx512f", "zmm", 1, ebx, 16), + ("avx512dq", "zmm", 1, ebx, 17), + ("rdseed", "", 1, ebx, 18), + ("adx", "", 1, ebx, 19), + ("avx512ifma", "zmm", 1, ebx, 21), + ("avx512pf", "zmm", 1, ebx, 26), + ("avx512er", "zmm", 1, ebx, 27), + ("avx512cd", "zmm", 1, ebx, 28), + ("sha", "xmm", 1, ebx, 29), + ("avx512bw", "zmm", 1, ebx, 30), + ("avx512vl", "zmm", 1, ebx, 31), +} diff --git a/third_party/rust/cpufeatures/tests/aarch64.rs b/third_party/rust/cpufeatures/tests/aarch64.rs new file mode 100644 index 0000000000..949669bed0 --- /dev/null +++ b/third_party/rust/cpufeatures/tests/aarch64.rs @@ -0,0 +1,17 @@ +//! ARM64 tests + +#![cfg(target_arch = "aarch64")] + +cpufeatures::new!(armcaps, "aes", "sha2", "sha3"); + +#[test] +fn init() { + let token: armcaps::InitToken = armcaps::init(); + assert_eq!(token.get(), armcaps::get()); +} + +#[test] +fn init_get() { + let (token, val) = armcaps::init_get(); + assert_eq!(val, token.get()); +} diff --git a/third_party/rust/cpufeatures/tests/x86.rs b/third_party/rust/cpufeatures/tests/x86.rs new file mode 100644 index 0000000000..0d81242389 --- /dev/null +++ b/third_party/rust/cpufeatures/tests/x86.rs @@ -0,0 +1,17 @@ +//! x86/x86_64 tests + +#![cfg(any(target_arch = "x86", target_arch = "x86_64"))] + +cpufeatures::new!(cpuid, "aes", "sha"); + +#[test] +fn init() { + let token: cpuid::InitToken = cpuid::init(); + assert_eq!(token.get(), cpuid::get()); +} + +#[test] +fn init_get() { + let (token, val) = cpuid::init_get(); + assert_eq!(val, token.get()); +} |