// Copyright 2022 the V8 project authors. All rights reserved. // Use of this source code is governed by a BSD-style license that can be // found in the LICENSE file. #include "jit/riscv64/extension/extension-riscv-m.h" #include "jit/riscv64/Assembler-riscv64.h" #include "jit/riscv64/constant/Constant-riscv64.h" #include "jit/riscv64/Architecture-riscv64.h" namespace js { namespace jit { // RV32M Standard Extension void AssemblerRISCVM::mul(Register rd, Register rs1, Register rs2) { GenInstrALU_rr(0b0000001, 0b000, rd, rs1, rs2); } void AssemblerRISCVM::mulh(Register rd, Register rs1, Register rs2) { GenInstrALU_rr(0b0000001, 0b001, rd, rs1, rs2); } void AssemblerRISCVM::mulhsu(Register rd, Register rs1, Register rs2) { GenInstrALU_rr(0b0000001, 0b010, rd, rs1, rs2); } void AssemblerRISCVM::mulhu(Register rd, Register rs1, Register rs2) { GenInstrALU_rr(0b0000001, 0b011, rd, rs1, rs2); } void AssemblerRISCVM::div(Register rd, Register rs1, Register rs2) { GenInstrALU_rr(0b0000001, 0b100, rd, rs1, rs2); } void AssemblerRISCVM::divu(Register rd, Register rs1, Register rs2) { GenInstrALU_rr(0b0000001, 0b101, rd, rs1, rs2); } void AssemblerRISCVM::rem(Register rd, Register rs1, Register rs2) { GenInstrALU_rr(0b0000001, 0b110, rd, rs1, rs2); } void AssemblerRISCVM::remu(Register rd, Register rs1, Register rs2) { GenInstrALU_rr(0b0000001, 0b111, rd, rs1, rs2); } #ifdef JS_CODEGEN_RISCV64 // RV64M Standard Extension (in addition to RV32M) void AssemblerRISCVM::mulw(Register rd, Register rs1, Register rs2) { GenInstrALUW_rr(0b0000001, 0b000, rd, rs1, rs2); } void AssemblerRISCVM::divw(Register rd, Register rs1, Register rs2) { GenInstrALUW_rr(0b0000001, 0b100, rd, rs1, rs2); } void AssemblerRISCVM::divuw(Register rd, Register rs1, Register rs2) { GenInstrALUW_rr(0b0000001, 0b101, rd, rs1, rs2); } void AssemblerRISCVM::remw(Register rd, Register rs1, Register rs2) { GenInstrALUW_rr(0b0000001, 0b110, rd, rs1, rs2); } void AssemblerRISCVM::remuw(Register rd, Register rs1, Register rs2) { GenInstrALUW_rr(0b0000001, 0b111, rd, rs1, rs2); } #endif } // namespace jit } // namespace js