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| author | Daniel Baumann <daniel.baumann@progress-linux.org> | 2024-04-08 19:26:18 +0000 |
|---|---|---|
| committer | Daniel Baumann <daniel.baumann@progress-linux.org> | 2024-04-08 19:26:18 +0000 |
| commit | 09e70a0de2ea691518756b99c4d975e7e6814bea (patch) | |
| tree | 22fa82d0aed0f422007088031c31bfa6f5265e63 /linux-kernel-patches/06-91df9fdf51492aec9fed6b4cbd33160886740f47.patch | |
| parent | Initial commit. (diff) | |
| download | intel-microcode-09e70a0de2ea691518756b99c4d975e7e6814bea.tar.xz intel-microcode-09e70a0de2ea691518756b99c4d975e7e6814bea.zip | |
Adding upstream version 3.20240312.1.upstream/3.20240312.1
Signed-off-by: Daniel Baumann <daniel.baumann@progress-linux.org>
Diffstat (limited to 'linux-kernel-patches/06-91df9fdf51492aec9fed6b4cbd33160886740f47.patch')
| -rw-r--r-- | linux-kernel-patches/06-91df9fdf51492aec9fed6b4cbd33160886740f47.patch | 58 |
1 files changed, 58 insertions, 0 deletions
diff --git a/linux-kernel-patches/06-91df9fdf51492aec9fed6b4cbd33160886740f47.patch b/linux-kernel-patches/06-91df9fdf51492aec9fed6b4cbd33160886740f47.patch new file mode 100644 index 0000000..ab9c49e --- /dev/null +++ b/linux-kernel-patches/06-91df9fdf51492aec9fed6b4cbd33160886740f47.patch @@ -0,0 +1,58 @@ +From 91df9fdf51492aec9fed6b4cbd33160886740f47 Mon Sep 17 00:00:00 2001
+From: Ashok Raj <ashok.raj@intel.com>
+Date: Wed, 28 Feb 2018 11:28:42 +0100
+Subject: x86/microcode/intel: Writeback and invalidate caches before updating
+ microcode
+
+Updating microcode is less error prone when caches have been flushed and
+depending on what exactly the microcode is updating. For example, some
+of the issues around certain Broadwell parts can be addressed by doing a
+full cache flush.
+
+[ Borislav: Massage it and use native_wbinvd() in both cases. ]
+
+Signed-off-by: Ashok Raj <ashok.raj@intel.com>
+Signed-off-by: Borislav Petkov <bp@suse.de>
+Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
+Tested-by: Tom Lendacky <thomas.lendacky@amd.com>
+Tested-by: Ashok Raj <ashok.raj@intel.com>
+Cc: Arjan Van De Ven <arjan.van.de.ven@intel.com>
+Link: http://lkml.kernel.org/r/1519352533-15992-3-git-send-email-ashok.raj@intel.com
+Link: https://lkml.kernel.org/r/20180228102846.13447-4-bp@alien8.de
+---
+ arch/x86/kernel/cpu/microcode/intel.c | 12 ++++++++++++
+ 1 file changed, 12 insertions(+)
+
+diff --git a/arch/x86/kernel/cpu/microcode/intel.c b/arch/x86/kernel/cpu/microcode/intel.c
+index 87bd6dc..e2864bc 100644
+--- a/arch/x86/kernel/cpu/microcode/intel.c
++++ b/arch/x86/kernel/cpu/microcode/intel.c
+@@ -600,6 +600,12 @@ static int apply_microcode_early(struct ucode_cpu_info *uci, bool early)
+ return UCODE_OK;
+ }
+
++ /*
++ * Writeback and invalidate caches before updating microcode to avoid
++ * internal issues depending on what the microcode is updating.
++ */
++ native_wbinvd();
++
+ /* write microcode via MSR 0x79 */
+ native_wrmsrl(MSR_IA32_UCODE_WRITE, (unsigned long)mc->bits);
+
+@@ -816,6 +822,12 @@ static enum ucode_state apply_microcode_intel(int cpu)
+ return UCODE_OK;
+ }
+
++ /*
++ * Writeback and invalidate caches before updating microcode to avoid
++ * internal issues depending on what the microcode is updating.
++ */
++ native_wbinvd();
++
+ /* write microcode via MSR 0x79 */
+ wrmsrl(MSR_IA32_UCODE_WRITE, (unsigned long)mc->bits);
+
+--
+cgit v1.1
+
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