Merging upstream version 22.

Signed-off-by: Daniel Baumann <daniel.baumann@progress-linux.org>

1 files changed, 13 insertions, 10 deletions

diff --git a/isa-list b/isa-list
index 07222de..14e9905 100644
--- a/isa-list
+++ b/isa-list
@@ -21,7 +21,7 @@ Test: return !(
 qemu-good: "qemu-$DEB_HOST_MULTIARCH_CPU""$QEMU_EXTRA" -cpu pentium',+cmov,+cx8'
 qemu-bad: "qemu-$DEB_HOST_MULTIARCH_CPU""$QEMU_EXTRA" -cpu pentium',-cmov,-cx8'
 Description:
- This is the Micro-Architecture Levels baseline for debian under i386 architecture, corresponding
+ This is the Micro-Architecture Levels baseline for Debian under i386 architecture, corresponding
  to i686 CPU.
  .
  This includes:
@@ -44,8 +44,8 @@ Description:
  Quark, or older processors.
 
 Name: amd64-baseline
-Architecture: any-i386 any-amd64
-Package: no
+Architecture: any-i386
+Package: yes
 Priority: -1
 Test: return !(
  __builtin_cpu_supports("cmov") && __builtin_cpu_supports("mmx") && __builtin_cpu_supports("sse") &&
@@ -55,8 +55,8 @@ Test: return !(
 qemu-good: "qemu-$DEB_HOST_MULTIARCH_CPU""$QEMU_EXTRA" -cpu qemu"$DEB_HOST_ARCH_BITS"',+cmov,+mmx,+sse,+sse2,+cx8,+fxsr'
 qemu-bad: "qemu-$DEB_HOST_MULTIARCH_CPU""$QEMU_EXTRA" -cpu qemu"$DEB_HOST_ARCH_BITS"',-sse,-sse2'
 Description:
- This is the Micro-Architecture Levels baseline for debian under x86-64 architecture, corresponding
- to x86-65 psABI v1.
+ This is the Micro-Architecture Levels baseline for Debian under
+ x86-64 architecture, corresponding to x86-65 psABI v1.
  .
  This includes:
  - cmov instruction (CMOV instruction set),
@@ -81,7 +81,8 @@ Test: return !(
 qemu-good: "qemu-$DEB_HOST_MULTIARCH_CPU""$QEMU_EXTRA" -cpu qemu"$DEB_HOST_ARCH_BITS"',+cmov,+mmx,+sse,+sse2,+cx8,+fxsr'
 qemu-bad: "qemu-$DEB_HOST_MULTIARCH_CPU""$QEMU_EXTRA" -cpu qemu"$DEB_HOST_ARCH_BITS"',-cmov,-mmx,-sse,-sse2,-cx8,-fxsr'
 Description:
- This is the Micro-Architecture Levels baseline as defined by the amd64 ABI document.
+ This is the Micro-Architecture Levels baseline as defined by the
+ amd64 ABI document.
  This includes:
  - cmov instruction (CMOV instruction set),
  - cmpxchg8b ant other 64 bits atomics instruction (CX8 instruction set),
@@ -95,7 +96,7 @@ Description:
 
 Name: x86-64-v2
 Architecture: any-i386 any-amd64
-Package: no
+Package: yes
 qemu-good: "qemu-$DEB_HOST_MULTIARCH_CPU""$QEMU_EXTRA" -cpu qemu"$DEB_HOST_ARCH_BITS"'-v1,+cmov,+mmx,+sse,+sse2,+cx8,+fxsr,+cx16,+lahf-lm,+popcnt,+sse3,+sse4.1,+sse4.2,+ssse3'
 qemu-bad: "qemu-$DEB_HOST_MULTIARCH_CPU""$QEMU_EXTRA" -cpu qemu"$DEB_HOST_ARCH_BITS"'-v1,+cmov,+mmx,+sse,+sse2,+cx8,+fxsr,-cx16,-lahf-lm,-popcnt,-sse3,-sse4.1,-sse4.2,-ssse3'
 Priority: 2000
@@ -108,7 +109,8 @@ Test: return !(
  __builtin_cpu_supports("sse4.1") && __builtin_cpu_supports("sse4.2") && __builtin_cpu_supports("ssse3")
  );
 Description:
- This is the Micro-Architecture Levels version 2 as defined by the amd64 ABI document.
+ This is the Micro-Architecture Levels version 2 as defined by the
+ amd64 ABI document.
  This includes:
  - cmov instruction (CMOV instruction set),
  - cmpxchg8b ant other 64 bits atomics instruction (CX8 instruction set),
@@ -175,7 +177,7 @@ Description:
 Name: x86-64-v3
 Architecture: any-i386 any-amd64
 Priority: 3000
-Package: no
+Package: yes
 #qemu-good: "qemu-$DEB_HOST_MULTIARCH_CPU""$QEMU_EXTRA" -cpu qemu"$DEB_HOST_ARCH_BITS"-v1',+cmov,+mmx,+sse,+sse2,+cx8,+fxsr,+cx16,+lahf-lm,+popcnt,+sse3,+sse4.1,+sse4.2,+ssse3,+avx,+avx2,+bmi1,+bmi2,+f16c,+fma,+abm'
 #qemu-bad: "qemu-$DEB_HOST_MULTIARCH_CPU""$QEMU_EXTRA" -cpu qemu"$DEB_HOST_ARCH_BITS"-v1',+cmov,+mmx,+sse,+sse2,+cx8,+fxsr,+cx16,+lahf-lm,+popcnt,+sse3,+sse4.1,+sse4.2,+ssse3,-avx,-avx2,-bmi1,-bmi2,-f16c,-fma,-abm'
 Test: return !(
@@ -192,7 +194,8 @@ Test: return !(
  CPU_FEATURE_ACTIVE(LZCNT) && CPU_FEATURE_ACTIVE(OSXSAVE)
  );
 Description:
- This is the Micro-Architecture Levels version 3 as defined by the amd64 ABI document.
+ This is the Micro-Architecture Levels version 3 as defined by
+ the amd64 ABI document.
  This includes:
  - cmov instruction (CMOV instruction set),
  - cmpxchg8b ant other 64 bits atomics instruction (CX8 instruction set),