Adding upstream version 2.4.121.upstream/2.4.121upstream

Signed-off-by: Daniel Baumann <daniel.baumann@progress-linux.org>

5 files changed, 64 insertions, 35 deletions

diff --git a/tests/amdgpu/shader_code.h b/tests/amdgpu/shader_code.h
index 74d32bb..164c619 100644
--- a/tests/amdgpu/shader_code.h
+++ b/tests/amdgpu/shader_code.h
@@ -75,13 +75,13 @@ struct shader_test_cs_shader {
 struct shader_test_ps_shader {
 	const uint32_t *shader;
 	unsigned shader_size;
-	const uint32_t patchinfo_code_size;
+	uint32_t patchinfo_code_size;
 	const uint32_t *patchinfo_code;
 	const uint32_t *patchinfo_code_offset;
 	const struct reg_info *sh_reg;
-	const uint32_t num_sh_reg;
+	uint32_t num_sh_reg;
 	const struct reg_info *context_reg;
-	const uint32_t num_context_reg;
+	uint32_t num_context_reg;
 };
 
 struct shader_test_vs_shader {
@@ -111,7 +111,7 @@ static const struct shader_test_cs_shader shader_test_cs[AMDGPU_TEST_GFX_MAX][2]
 #define SHADER_PS_INFO(_ps, _n) \
 	{ps_##_ps##_shader_gfx##_n, sizeof(ps_##_ps##_shader_gfx##_n), \
 	ps_##_ps##_shader_patchinfo_code_size_gfx##_n, \
-	ps_##_ps##_shader_patchinfo_code_gfx##_n, \
+	&(ps_##_ps##_shader_patchinfo_code_gfx##_n)[0][0][0], \
 	ps_##_ps##_shader_patchinfo_offset_gfx##_n, \
 	ps_##_ps##_sh_registers_gfx##_n, ps_##_ps##_num_sh_registers_gfx##_n, \
 	ps_##_ps##_context_registers_gfx##_n, ps_##_ps##_num_context_registers_gfx##_n}
diff --git a/tests/amdgpu/shader_code_gfx10.h b/tests/amdgpu/shader_code_gfx10.h
index 4849bbc..1e7c8f9 100644
--- a/tests/amdgpu/shader_code_gfx10.h
+++ b/tests/amdgpu/shader_code_gfx10.h
@@ -41,7 +41,7 @@ static const uint32_t ps_const_shader_gfx10[] = {
     0xF8001C0F, 0x00000100, 0xBF810000
 };
 
-static const uint32_t ps_const_shader_patchinfo_code_size_gfx10 = 6;
+#define ps_const_shader_patchinfo_code_size_gfx10 6
 
 static const uint32_t ps_const_shader_patchinfo_code_gfx10[][10][6] = {
     {{ 0xBF800000, 0xBF800000, 0xBF800000, 0xBF800000, 0xF8001890, 0x00000000 },
@@ -61,7 +61,7 @@ static const uint32_t ps_const_shader_patchinfo_offset_gfx10[] = {
     0x00000004
 };
 
-static const uint32_t ps_const_num_sh_registers_gfx10 = 2;
+#define ps_const_num_sh_registers_gfx10 2
 
 static const struct reg_info ps_const_sh_registers_gfx10[] = {
 	{0x2C0A, 0x000C0000},//{ mmSPI_SHADER_PGM_RSRC1_PS, 0x000C0000 },
@@ -79,7 +79,7 @@ static const struct reg_info ps_const_context_registers_gfx10[] =
     {0xA1C5, 0x00000004}, //{ mmSPI_SHADER_COL_FORMAT,   0x00000004 /* SI_EXPORT_FMT_FP16_ABGR */ }
 };
 
-static const uint32_t ps_const_num_context_registers_gfx10 = 7;
+#define ps_const_num_context_registers_gfx10 7
 
 static const uint32_t ps_tex_shader_gfx10[] = {
     0xBEFC030C, 0xBE8E047E, 0xBEFE0A7E, 0xC8080000,
@@ -93,7 +93,7 @@ static const uint32_t ps_tex_shader_patchinfo_offset_gfx10[] = {
     0x0000000C
 };
 
-static const uint32_t ps_tex_shader_patchinfo_code_size_gfx10 = 6;
+#define ps_tex_shader_patchinfo_code_size_gfx10 6
 
 static const uint32_t ps_tex_shader_patchinfo_code_gfx10[][10][6] = {
     {{ 0xBF800000, 0xBF800000, 0xBF800000, 0xBF800000, 0xF8001890, 0x00000000 },
@@ -115,7 +115,7 @@ static const struct reg_info ps_tex_sh_registers_gfx10[] =
      {0x2C0B, 0x00000018 }, //{ mmSPI_SHADER_PGM_RSRC2_PS, 0x00000018 }
 };
 
-static const uint32_t ps_tex_num_sh_registers_gfx10 = 2;
+#define ps_tex_num_sh_registers_gfx10 2
 
 // Holds Context Register Information
 static const struct reg_info ps_tex_context_registers_gfx10[] =
@@ -129,7 +129,7 @@ static const struct reg_info ps_tex_context_registers_gfx10[] =
     {0xA1C5, 0x00000004}, //{ mmSPI_SHADER_COL_FORMAT,   0x00000004 /* SI_EXPORT_FMT_FP16_ABGR */ }
 };
 
-static const uint32_t ps_tex_num_context_registers_gfx10 = 7;
+#define ps_tex_num_context_registers_gfx10 7
 
 static const uint32_t vs_RectPosTexFast_shader_gfx10[] = {
     0x7E000B00, 0x060000F3, 0x7E020202, 0x7E040206,
@@ -148,7 +148,7 @@ static const struct reg_info vs_RectPosTexFast_sh_registers_gfx10[] =
     {0x2C4B, 0x00000018 }, //{ mmSPI_SHADER_PGM_RSRC2_VS, 0x00000018 }
 };
 
-static const uint32_t vs_RectPosTexFast_num_sh_registers_gfx10 = 2;
+#define vs_RectPosTexFast_num_sh_registers_gfx10 2
 
 // Holds Context Register Information
 static const struct reg_info vs_RectPosTexFast_context_registers_gfx10[] =
@@ -157,7 +157,7 @@ static const struct reg_info vs_RectPosTexFast_context_registers_gfx10[] =
     {0xA1C3, 0x00000000}, //{ mmSPI_SHADER_POS_FORMAT, 0x00000000 /* Always 0 for now */}
 };
 
-static const uint32_t vs_RectPosTexFast_num_context_registers_gfx10 = 2;
+#define vs_RectPosTexFast_num_context_registers_gfx10 2
 
 static const uint32_t preamblecache_gfx10[] = {
 	0xc0026900, 0x81, 0x80000000, 0x40004000, 0xc0026900, 0x8c, 0xaa99aaaa, 0x0,
@@ -196,7 +196,7 @@ static const uint32_t cached_cmd_gfx10[] = {
 	0xc0026900, 0x2b0, 0x0, 0x0, 0xc0016900, 0x2f8, 0x0
 };
 
-static const uint32_t sh_reg_base_gfx10 = 0x2C00;
-static const uint32_t context_reg_base_gfx10 = 0xA000;
+#define sh_reg_base_gfx10 0x2C00
+#define context_reg_base_gfx10 0xA000
 
 #endif
diff --git a/tests/amdgpu/shader_code_gfx11.h b/tests/amdgpu/shader_code_gfx11.h
index d9ee0a7..8a998ae 100644
--- a/tests/amdgpu/shader_code_gfx11.h
+++ b/tests/amdgpu/shader_code_gfx11.h
@@ -101,7 +101,7 @@ static const uint32_t ps_const_shader_gfx11[] = {
     0xBF9F0000
 };
 
-static const uint32_t ps_const_shader_patchinfo_code_size_gfx11 = 6;
+#define ps_const_shader_patchinfo_code_size_gfx11 6
 
 static const uint32_t ps_const_shader_patchinfo_code_gfx11[][10][6] = {
 	{{ 0xBF800000, 0xBF800000, 0xBF800000, 0xBF800000, 0xF8000890, 0x00000000 },  // SI_EXPORT_FMT_ZERO
@@ -121,7 +121,7 @@ static const uint32_t ps_const_shader_patchinfo_offset_gfx11[] = {
 	0x00000006
 };
 
-static const uint32_t ps_const_num_sh_registers_gfx11 = 2;
+#define ps_const_num_sh_registers_gfx11 2
 
 static const struct reg_info ps_const_sh_registers_gfx11[] = {
 	{0x2C0A, 0x020C0000}, //{ mmSPI_SHADER_PGM_RSRC1_PS, 0x020C0000 },
@@ -138,7 +138,7 @@ static const struct reg_info ps_const_context_registers_gfx11[] = {
 	{0xA1C5, 0x00000004 }, //{ mmSPI_SHADER_COL_FORMAT,   0x00000004 /* SI_EXPORT_FMT_FP16_ABGR */ }
 };
 
-static const uint32_t ps_const_num_context_registers_gfx11 = 7;
+#define ps_const_num_context_registers_gfx11 7
 
 static const uint32_t ps_tex_shader_gfx11[] =
 {
@@ -174,7 +174,7 @@ static const uint32_t ps_tex_shader_patchinfo_offset_gfx11[] =
 };
 
 // Denotes the Patch Info Code Length
-static const uint32_t ps_tex_shader_patchinfo_code_size_gfx11 = 6;
+#define ps_tex_shader_patchinfo_code_size_gfx11 6
 
 static const uint32_t ps_tex_shader_patchinfo_code_gfx11[][10][6] =
 {
@@ -197,7 +197,7 @@ static const struct reg_info ps_tex_sh_registers_gfx11[] =
     {0x2C0B, 0x00000018 } //{ mmSPI_SHADER_PGM_RSRC2_PS, 0x00000018 }
 };
 
-static const uint32_t ps_tex_num_sh_registers_gfx11 = 2;
+#define ps_tex_num_sh_registers_gfx11 2
 
 // Holds Context Register Information
 static const struct reg_info ps_tex_context_registers_gfx11[] =
@@ -211,8 +211,7 @@ static const struct reg_info ps_tex_context_registers_gfx11[] =
     {0xA1C5, 0x00000004 } //{ mmSPI_SHADER_COL_FORMAT,   0x00000004 /* SI_EXPORT_FMT_FP16_ABGR */ }
 };
 
-static const uint32_t ps_tex_num_context_registers_gfx11 = 7;
-
+#define ps_tex_num_context_registers_gfx11 7
 
 static const uint32_t vs_RectPosTexFast_shader_gfx11[] =
 {
@@ -261,7 +260,7 @@ static const struct reg_info vs_RectPosTexFast_sh_registers_gfx11[] =
 	{0x2C8B, 0x0008001C}, //{ mmSPI_SHADER_PGM_RSRC2_GS, 0x0008001C }
 };
 
-static const uint32_t vs_RectPosTexFast_num_sh_registers_gfx11 = 2;
+#define vs_RectPosTexFast_num_sh_registers_gfx11 2
 
 // Holds Context Register Information
 static const struct reg_info vs_RectPosTexFast_context_registers_gfx11[] =
@@ -274,7 +273,7 @@ static const struct reg_info vs_RectPosTexFast_context_registers_gfx11[] =
 	{0xA2CE, 0x00000001}, //{ mmVGT_GS_MAX_VERT_OUT, 0x00000001 }
 };
 
-static const uint32_t vs_RectPosTexFast_num_context_registers_gfx11 = 6;
+#define vs_RectPosTexFast_num_context_registers_gfx11 6
 
 static const uint32_t preamblecache_gfx11[] = {
 	0xc0026900, 0x81, 0x80000000, 0x40004000, 0xc0026900, 0x8c, 0xaa99aaaa, 0x0,
@@ -314,7 +313,8 @@ static const uint32_t cached_cmd_gfx11[] = {
 	0xc0046900, 0x1d5, 0x0, 0x0, 0x0, 0x0, 0xc0016900, 0x104, 0x4a00005,
 	0xc0016900, 0x1f, 0xf2a0055, 0xc0017900, 0x266, 0x4
 };
-static const uint32_t sh_reg_base_gfx11 = 0x2C00;
-static const uint32_t context_reg_base_gfx11 = 0xA000;
+
+#define sh_reg_base_gfx11 0x2C00
+#define context_reg_base_gfx11 0xA000
 
 #endif
diff --git a/tests/amdgpu/shader_code_gfx9.h b/tests/amdgpu/shader_code_gfx9.h
index 3ad1ca8..1cb6582 100644
--- a/tests/amdgpu/shader_code_gfx9.h
+++ b/tests/amdgpu/shader_code_gfx9.h
@@ -51,7 +51,7 @@ static const uint32_t ps_const_shader_gfx9[] = {
 	0xC4001C0F, 0x00000100, 0xBF810000
 };
 
-static const uint32_t ps_const_shader_patchinfo_code_size_gfx9 = 6;
+#define ps_const_shader_patchinfo_code_size_gfx9 6
 
 static const uint32_t ps_const_shader_patchinfo_code_gfx9[][10][6] = {
     {{ 0xBF800000, 0xBF800000, 0xBF800000, 0xBF800000, 0xC4001890, 0x00000000 },
@@ -71,14 +71,14 @@ static const uint32_t ps_const_shader_patchinfo_offset_gfx9[] = {
 	0x00000004
 };
 
-static const uint32_t ps_const_num_sh_registers_gfx9 = 2;
+#define ps_const_num_sh_registers_gfx9 2
 
 static const struct reg_info ps_const_sh_registers_gfx9[] = {
 	{0x2C0A, 0x000C0040},//{ mmSPI_SHADER_PGM_RSRC1_PS, 0x000C0040 },
 	{0x2C0B, 0x00000008}, //{ mmSPI_SHADER_PGM_RSRC2_PS, 0x00000008 }
 };
 
-static const uint32_t ps_const_num_context_registers_gfx9 = 7;
+#define ps_const_num_context_registers_gfx9 7
 
 static const struct reg_info ps_const_context_registers_gfx9[] = {
     {0xA1B4, 0x00000002}, //{ mmSPI_PS_INPUT_ADDR,       0x00000002 },
@@ -102,7 +102,7 @@ static const uint32_t ps_tex_shader_patchinfo_offset_gfx9[] = {
     0x0000000B
 };
 
-static const uint32_t ps_tex_shader_patchinfo_code_size_gfx9 = 6;
+#define ps_tex_shader_patchinfo_code_size_gfx9 6
 
 static const uint32_t ps_tex_shader_patchinfo_code_gfx9[][10][6] = {
     {{ 0xBF800000, 0xBF800000, 0xBF800000, 0xBF800000, 0xC4001890, 0x00000000 },
@@ -118,13 +118,14 @@ static const uint32_t ps_tex_shader_patchinfo_code_gfx9[][10][6] = {
     }
 };
 
-static const uint32_t ps_tex_num_sh_registers_gfx9 = 2;
+#define ps_tex_num_sh_registers_gfx9 2
+
 static const struct reg_info ps_tex_sh_registers_gfx9[] = {
     {0x2C0A, 0x000C0081},//{ mmSPI_SHADER_PGM_RSRC1_PS, 0x000C0081 },
     {0x2C0B, 0x00000018}, //{ mmSPI_SHADER_PGM_RSRC2_PS, 0x00000018 }
 };
 
-static const uint32_t ps_tex_num_context_registers_gfx9 = 7;
+#define ps_tex_num_context_registers_gfx9 7
 
 static const struct reg_info ps_tex_context_registers_gfx9[] = {
     {0xA1B4, 0x00000002}, //{ mmSPI_PS_INPUT_ADDR,       0x00000002 },
@@ -153,7 +154,7 @@ static const struct reg_info vs_RectPosTexFast_sh_registers_gfx9[] =
     {0x2C4B, 0x00000018}, //{ mmSPI_SHADER_PGM_RSRC2_VS, 0x00000018 }
 };
 
-static const uint32_t vs_RectPosTexFast_num_sh_registers_gfx9 = 2;
+#define vs_RectPosTexFast_num_sh_registers_gfx9 2
 
 // Holds Context Register Information
 static const struct reg_info vs_RectPosTexFast_context_registers_gfx9[] =
@@ -162,7 +163,7 @@ static const struct reg_info vs_RectPosTexFast_context_registers_gfx9[] =
     {0xA1C3, 0x00000000}, //{ mmSPI_SHADER_POS_FORMAT, 0x00000000 /* Always 0 for now */}
 };
 
-static const uint32_t vs_RectPosTexFast_num_context_registers_gfx9 = 2;
+#define vs_RectPosTexFast_num_context_registers_gfx9 2
 
 static const uint32_t preamblecache_gfx9[] = {
 	0xc0026900, 0x81, 0x80000000, 0x40004000, 0xc0026900, 0x8c, 0xaa99aaaa, 0x0,
@@ -198,7 +199,7 @@ static const uint32_t cached_cmd_gfx9[] = {
 	0xc0026900, 0x2b0, 0x0, 0x0, 0xc0016900, 0x2f8, 0x0
 };
 
-static const uint32_t sh_reg_base_gfx9 = 0x2C00;
-static const uint32_t context_reg_base_gfx9 = 0xA000;
+#define sh_reg_base_gfx9 0x2C00
+#define context_reg_base_gfx9 0xA000
 
 #endif
diff --git a/tests/amdgpu/shader_test_util.c b/tests/amdgpu/shader_test_util.c
index 60148fb..8a19f59 100644
--- a/tests/amdgpu/shader_test_util.c
+++ b/tests/amdgpu/shader_test_util.c
@@ -4,6 +4,7 @@
 #include <sys/types.h>
 #include <sys/stat.h>
 #include <string.h>
+#include <assert.h>
 
 #include "CUnit/Basic.h"
 #include "amdgpu_test.h"
@@ -303,6 +304,9 @@ static void amdgpu_dispatch_init(struct shader_test_priv *test_priv)
 	case AMDGPU_TEST_GFX_V11:
 		amdgpu_dispatch_init_gfx11(test_priv);
 		break;
+	case AMDGPU_TEST_GFX_MAX:
+		assert(1 && "Not Support gfx, never go here");
+		break;
 	}
 }
 
@@ -338,6 +342,9 @@ static void amdgpu_dispatch_write_cumask(struct shader_test_priv *test_priv)
 		ptr[i++] = 0xffffffff;
 		ptr[i++] = 0xffffffff;
 		break;
+	case AMDGPU_TEST_GFX_MAX:
+		assert(1 && "Not Support gfx, never go here");
+		break;
 	}
 
 	test_priv->cmd_curr = i;
@@ -541,6 +548,9 @@ static void amdgpu_dispatch_write2hw(struct shader_test_priv *test_priv)
 	case AMDGPU_TEST_GFX_V11:
 		amdgpu_dispatch_write2hw_gfx11(test_priv);
 		break;
+	case AMDGPU_TEST_GFX_MAX:
+		assert(1 && "Not Support gfx, never go here");
+		break;
 	}
 }
 
@@ -1168,6 +1178,9 @@ static void amdgpu_draw_setup_and_write_drawblt_surf_info(struct shader_test_pri
 	case AMDGPU_TEST_GFX_V11:
 		amdgpu_draw_setup_and_write_drawblt_surf_info_gfx11(test_priv);
 		break;
+	case AMDGPU_TEST_GFX_MAX:
+		assert(1 && "Not Support gfx, never go here");
+		break;
 	}
 }
 
@@ -1298,6 +1311,9 @@ static void amdgpu_draw_setup_and_write_drawblt_state(struct shader_test_priv *t
 	case AMDGPU_TEST_GFX_V11:
 		amdgpu_draw_setup_and_write_drawblt_state_gfx11(test_priv);
 		break;
+	case AMDGPU_TEST_GFX_MAX:
+		assert(1 && "Not Support gfx, never go here");
+		break;
 	}
 }
 
@@ -1546,6 +1562,9 @@ static void amdgpu_draw_vs_RectPosTexFast_write2hw(struct shader_test_priv *test
 	case AMDGPU_TEST_GFX_V11:
 		amdgpu_draw_vs_RectPosTexFast_write2hw_gfx11(test_priv);
 		break;
+	case AMDGPU_TEST_GFX_MAX:
+		assert(1 && "Not Support gfx, never go here");
+		break;
 	}
 }
 
@@ -1679,6 +1698,9 @@ static void amdgpu_draw_ps_write2hw(struct shader_test_priv *test_priv)
 	case AMDGPU_TEST_GFX_V11:
 		amdgpu_draw_ps_write2hw_gfx11(test_priv);
 		break;
+	case AMDGPU_TEST_GFX_MAX:
+		assert(1 && "Not Support gfx, never go here");
+		break;
 	}
 }
 
@@ -1718,6 +1740,9 @@ static void amdgpu_draw_draw(struct shader_test_priv *test_priv)
 		ptr[i++] = 0x242;
 		ptr[i++] = 0x11;
 		break;
+	case AMDGPU_TEST_GFX_MAX:
+		assert(1 && "Not Support gfx, never go here");
+		break;
 	}
 
 	ptr[i++] = PACKET3(PACKET3_DRAW_INDEX_AUTO, 1);
@@ -2010,6 +2035,9 @@ static void amdgpu_memcpy_draw_test(struct shader_test_info *test_info)
 		ptr_cmd[i++] = 0x400;
 		i++;
 		break;
+	case AMDGPU_TEST_GFX_MAX:
+		assert(1 && "Not Support gfx, never go here");
+		break;
 	}
 
 	ptr_cmd[i++] = PACKET3(PACKET3_SET_SH_REG, 4);