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-rw-r--r--.gitlab-ci.yml6
-rw-r--r--amdgpu/amdgpu-symbols.txt5
-rw-r--r--amdgpu/amdgpu.h51
-rw-r--r--amdgpu/amdgpu_cs.c15
-rw-r--r--amdgpu/amdgpu_device.c103
-rw-r--r--amdgpu/amdgpu_internal.h21
-rw-r--r--amdgpu/amdgpu_vamgr.c71
-rw-r--r--data/amdgpu.ids67
-rw-r--r--etnaviv/meson.build2
-rw-r--r--exynos/meson.build2
-rw-r--r--freedreno/meson.build2
-rw-r--r--include/drm/amdgpu_drm.h26
-rw-r--r--intel/meson.build2
-rw-r--r--libsync.h2
-rw-r--r--meson.build4
-rw-r--r--omap/meson.build2
-rw-r--r--symbols-check.py4
-rw-r--r--tegra/job.c2
-rw-r--r--tegra/meson.build2
-rw-r--r--tests/amdgpu/shader_code.h8
-rw-r--r--tests/amdgpu/shader_code_gfx10.h20
-rw-r--r--tests/amdgpu/shader_code_gfx11.h22
-rw-r--r--tests/amdgpu/shader_code_gfx9.h21
-rw-r--r--tests/amdgpu/shader_test_util.c28
-rw-r--r--tests/util/kms.c1
-rw-r--r--xf86drm.c20
-rw-r--r--xf86drm.h5
27 files changed, 398 insertions, 116 deletions
diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml
index 6e8655f..4c07ae9 100644
--- a/.gitlab-ci.yml
+++ b/.gitlab-ci.yml
@@ -190,8 +190,8 @@ x86_64-freebsd-container_prep:
variables:
GIT_DEPTH: 10
script:
- - meson build
- --auto-features=enabled
+ - meson setup build
+ --fatal-meson-warnings --auto-features=enabled
-D udev=true
- ninja -C build
- ninja -C build test
@@ -213,7 +213,7 @@ x86_64-freebsd-container_prep:
# the workspace to see details about the failed tests.
- |
set +e
- /app/vmctl exec "pkg info; cd $CI_PROJECT_NAME ; meson build --auto-features=enabled -D etnaviv=disabled -D nouveau=disabled -D valgrind=disabled && ninja -C build"
+ /app/vmctl exec "pkg info; cd $CI_PROJECT_NAME ; meson setup build --fatal-meson-warnings --auto-features=enabled -D etnaviv=disabled -D nouveau=disabled -D valgrind=disabled && ninja -C build"
set -ex
scp -r vm:$CI_PROJECT_NAME/build/meson-logs .
/app/vmctl exec "ninja -C $CI_PROJECT_NAME/build install"
diff --git a/amdgpu/amdgpu-symbols.txt b/amdgpu/amdgpu-symbols.txt
index 530b343..594480e 100644
--- a/amdgpu/amdgpu-symbols.txt
+++ b/amdgpu/amdgpu-symbols.txt
@@ -56,6 +56,7 @@ amdgpu_cs_wait_semaphore
amdgpu_device_deinitialize
amdgpu_device_get_fd
amdgpu_device_initialize
+amdgpu_device_initialize2
amdgpu_find_bo_by_cpu_mapping
amdgpu_get_marketing_name
amdgpu_query_buffer_size_alignment
@@ -71,7 +72,11 @@ amdgpu_query_info
amdgpu_query_sensor_info
amdgpu_query_video_caps_info
amdgpu_read_mm_registers
+amdgpu_va_manager_alloc
+amdgpu_va_manager_init
+amdgpu_va_manager_deinit
amdgpu_va_range_alloc
+amdgpu_va_range_alloc2
amdgpu_va_range_free
amdgpu_va_get_start_addr
amdgpu_va_range_query
diff --git a/amdgpu/amdgpu.h b/amdgpu/amdgpu.h
index 9bdbf36..c9c1f12 100644
--- a/amdgpu/amdgpu.h
+++ b/amdgpu/amdgpu.h
@@ -139,6 +139,12 @@ typedef struct amdgpu_bo_list *amdgpu_bo_list_handle;
typedef struct amdgpu_va *amdgpu_va_handle;
/**
+ * Define handle dealing with VA allocation. An amdgpu_device
+ * owns one of these, but they can also be used without a device.
+ */
+typedef struct amdgpu_va_manager *amdgpu_va_manager_handle;
+
+/**
* Define handle for semaphore
*/
typedef struct amdgpu_semaphore *amdgpu_semaphore_handle;
@@ -528,6 +534,20 @@ int amdgpu_device_initialize(int fd,
amdgpu_device_handle *device_handle);
/**
+ * Same as amdgpu_device_initialize() except when deduplicate_device
+ * is false *and* fd points to a device that was already initialized.
+ * In this case, amdgpu_device_initialize would return the same
+ * amdgpu_device_handle while here amdgpu_device_initialize2 would
+ * return a new handle.
+ * amdgpu_device_initialize() should be preferred in most situations;
+ * the only use-case where not-deduplicating devices make sense is
+ * when one wants to have isolated device handles in the same process.
+ */
+int amdgpu_device_initialize2(int fd, bool deduplicate_device,
+ uint32_t *major_version,
+ uint32_t *minor_version,
+ amdgpu_device_handle *device_handle);
+/**
*
* When access to such library does not needed any more the special
* function must be call giving opportunity to clean up any
@@ -1411,6 +1431,37 @@ int amdgpu_va_range_query(amdgpu_device_handle dev,
uint64_t *end);
/**
+ * Allocate a amdgpu_va_manager object.
+ * The returned object has be initialized with the amdgpu_va_manager_init
+ * before use.
+ * On release, amdgpu_va_manager_deinit needs to be called, then the memory
+ * can be released using free().
+ */
+amdgpu_va_manager_handle amdgpu_va_manager_alloc(void);
+
+void amdgpu_va_manager_init(amdgpu_va_manager_handle va_mgr,
+ uint64_t low_va_offset, uint64_t low_va_max,
+ uint64_t high_va_offset, uint64_t high_va_max,
+ uint32_t virtual_address_alignment);
+
+void amdgpu_va_manager_deinit(amdgpu_va_manager_handle va_mgr);
+
+/**
+ * Similar to #amdgpu_va_range_alloc() but allocates VA
+ * directly from an amdgpu_va_manager_handle instead of using
+ * the manager from an amdgpu_device.
+ */
+
+int amdgpu_va_range_alloc2(amdgpu_va_manager_handle va_mgr,
+ enum amdgpu_gpu_va_range va_range_type,
+ uint64_t size,
+ uint64_t va_base_alignment,
+ uint64_t va_base_required,
+ uint64_t *va_base_allocated,
+ amdgpu_va_handle *va_range_handle,
+ uint64_t flags);
+
+/**
* VA mapping/unmapping for the buffer object
*
* \param bo - \c [in] BO handle
diff --git a/amdgpu/amdgpu_cs.c b/amdgpu/amdgpu_cs.c
index 49fc16c..2db4967 100644
--- a/amdgpu/amdgpu_cs.c
+++ b/amdgpu/amdgpu_cs.c
@@ -598,24 +598,31 @@ drm_public int amdgpu_cs_signal_semaphore(amdgpu_context_handle ctx,
uint32_t ring,
amdgpu_semaphore_handle sem)
{
+ int ret;
+
if (!ctx || !sem)
return -EINVAL;
if (ip_type >= AMDGPU_HW_IP_NUM)
return -EINVAL;
if (ring >= AMDGPU_CS_MAX_RINGS)
return -EINVAL;
- /* sem has been signaled */
- if (sem->signal_fence.context)
- return -EINVAL;
+
pthread_mutex_lock(&ctx->sequence_mutex);
+ /* sem has been signaled */
+ if (sem->signal_fence.context) {
+ ret = -EINVAL;
+ goto unlock;
+ }
sem->signal_fence.context = ctx;
sem->signal_fence.ip_type = ip_type;
sem->signal_fence.ip_instance = ip_instance;
sem->signal_fence.ring = ring;
sem->signal_fence.fence = ctx->last_seq[ip_type][ip_instance][ring];
update_references(NULL, &sem->refcount);
+ ret = 0;
+unlock:
pthread_mutex_unlock(&ctx->sequence_mutex);
- return 0;
+ return ret;
}
drm_public int amdgpu_cs_wait_semaphore(amdgpu_context_handle ctx,
diff --git a/amdgpu/amdgpu_device.c b/amdgpu/amdgpu_device.c
index aeb5e3c..34463b5 100644
--- a/amdgpu/amdgpu_device.c
+++ b/amdgpu/amdgpu_device.c
@@ -95,22 +95,26 @@ static int amdgpu_get_auth(int fd, int *auth)
static void amdgpu_device_free_internal(amdgpu_device_handle dev)
{
- amdgpu_device_handle *node = &dev_list;
-
- pthread_mutex_lock(&dev_mutex);
- while (*node != dev && (*node)->next)
- node = &(*node)->next;
- *node = (*node)->next;
- pthread_mutex_unlock(&dev_mutex);
+ /* Remove dev from dev_list, if it was added there. */
+ if (dev == dev_list) {
+ dev_list = dev->next;
+ } else {
+ for (amdgpu_device_handle node = dev_list; node; node = node->next) {
+ if (node->next == dev) {
+ node->next = dev->next;
+ break;
+ }
+ }
+ }
close(dev->fd);
if ((dev->flink_fd >= 0) && (dev->fd != dev->flink_fd))
close(dev->flink_fd);
- amdgpu_vamgr_deinit(&dev->vamgr_32);
- amdgpu_vamgr_deinit(&dev->vamgr);
- amdgpu_vamgr_deinit(&dev->vamgr_high_32);
- amdgpu_vamgr_deinit(&dev->vamgr_high);
+ amdgpu_vamgr_deinit(&dev->va_mgr.vamgr_32);
+ amdgpu_vamgr_deinit(&dev->va_mgr.vamgr_low);
+ amdgpu_vamgr_deinit(&dev->va_mgr.vamgr_high_32);
+ amdgpu_vamgr_deinit(&dev->va_mgr.vamgr_high);
handle_table_fini(&dev->bo_handles);
handle_table_fini(&dev->bo_flink_names);
pthread_mutex_destroy(&dev->bo_table_mutex);
@@ -140,22 +144,23 @@ static void amdgpu_device_reference(struct amdgpu_device **dst,
*dst = src;
}
-drm_public int amdgpu_device_initialize(int fd,
- uint32_t *major_version,
- uint32_t *minor_version,
- amdgpu_device_handle *device_handle)
+static int _amdgpu_device_initialize(int fd,
+ uint32_t *major_version,
+ uint32_t *minor_version,
+ amdgpu_device_handle *device_handle,
+ bool deduplicate_device)
{
- struct amdgpu_device *dev;
+ struct amdgpu_device *dev = NULL;
drmVersionPtr version;
int r;
int flag_auth = 0;
int flag_authexist=0;
uint32_t accel_working = 0;
- uint64_t start, max;
*device_handle = NULL;
pthread_mutex_lock(&dev_mutex);
+
r = amdgpu_get_auth(fd, &flag_auth);
if (r) {
fprintf(stderr, "%s: amdgpu_get_auth (1) failed (%i)\n",
@@ -164,9 +169,10 @@ drm_public int amdgpu_device_initialize(int fd,
return r;
}
- for (dev = dev_list; dev; dev = dev->next)
- if (fd_compare(dev->fd, fd) == 0)
- break;
+ if (deduplicate_device)
+ for (dev = dev_list; dev; dev = dev->next)
+ if (fd_compare(dev->fd, fd) == 0)
+ break;
if (dev) {
r = amdgpu_get_auth(dev->fd, &flag_authexist);
@@ -238,35 +244,22 @@ drm_public int amdgpu_device_initialize(int fd,
goto cleanup;
}
- start = dev->dev_info.virtual_address_offset;
- max = MIN2(dev->dev_info.virtual_address_max, 0x100000000ULL);
- amdgpu_vamgr_init(&dev->vamgr_32, start, max,
- dev->dev_info.virtual_address_alignment);
-
- start = max;
- max = MAX2(dev->dev_info.virtual_address_max, 0x100000000ULL);
- amdgpu_vamgr_init(&dev->vamgr, start, max,
- dev->dev_info.virtual_address_alignment);
-
- start = dev->dev_info.high_va_offset;
- max = MIN2(dev->dev_info.high_va_max, (start & ~0xffffffffULL) +
- 0x100000000ULL);
- amdgpu_vamgr_init(&dev->vamgr_high_32, start, max,
- dev->dev_info.virtual_address_alignment);
-
- start = max;
- max = MAX2(dev->dev_info.high_va_max, (start & ~0xffffffffULL) +
- 0x100000000ULL);
- amdgpu_vamgr_init(&dev->vamgr_high, start, max,
- dev->dev_info.virtual_address_alignment);
+ amdgpu_va_manager_init(&dev->va_mgr,
+ dev->dev_info.virtual_address_offset,
+ dev->dev_info.virtual_address_max,
+ dev->dev_info.high_va_offset,
+ dev->dev_info.high_va_max,
+ dev->dev_info.virtual_address_alignment);
amdgpu_parse_asic_ids(dev);
*major_version = dev->major_version;
*minor_version = dev->minor_version;
*device_handle = dev;
- dev->next = dev_list;
- dev_list = dev;
+ if (deduplicate_device) {
+ dev->next = dev_list;
+ dev_list = dev;
+ }
pthread_mutex_unlock(&dev_mutex);
return 0;
@@ -279,9 +272,27 @@ cleanup:
return r;
}
+drm_public int amdgpu_device_initialize(int fd,
+ uint32_t *major_version,
+ uint32_t *minor_version,
+ amdgpu_device_handle *device_handle)
+{
+ return _amdgpu_device_initialize(fd, major_version, minor_version, device_handle, true);
+}
+
+drm_public int amdgpu_device_initialize2(int fd, bool deduplicate_device,
+ uint32_t *major_version,
+ uint32_t *minor_version,
+ amdgpu_device_handle *device_handle)
+{
+ return _amdgpu_device_initialize(fd, major_version, minor_version, device_handle, deduplicate_device);
+}
+
drm_public int amdgpu_device_deinitialize(amdgpu_device_handle dev)
{
+ pthread_mutex_lock(&dev_mutex);
amdgpu_device_reference(&dev, NULL);
+ pthread_mutex_unlock(&dev_mutex);
return 0;
}
@@ -306,10 +317,10 @@ drm_public int amdgpu_query_sw_info(amdgpu_device_handle dev,
switch (info) {
case amdgpu_sw_info_address32_hi:
- if (dev->vamgr_high_32.va_max)
- *val32 = (dev->vamgr_high_32.va_max - 1) >> 32;
+ if (dev->va_mgr.vamgr_high_32.va_max)
+ *val32 = (dev->va_mgr.vamgr_high_32.va_max - 1) >> 32;
else
- *val32 = (dev->vamgr_32.va_max - 1) >> 32;
+ *val32 = (dev->va_mgr.vamgr_32.va_max - 1) >> 32;
return 0;
}
return -EINVAL;
diff --git a/amdgpu/amdgpu_internal.h b/amdgpu/amdgpu_internal.h
index 2834c9c..af85b84 100644
--- a/amdgpu/amdgpu_internal.h
+++ b/amdgpu/amdgpu_internal.h
@@ -63,6 +63,17 @@ struct amdgpu_va {
struct amdgpu_bo_va_mgr *vamgr;
};
+struct amdgpu_va_manager {
+ /** The VA manager for the lower virtual address space */
+ struct amdgpu_bo_va_mgr vamgr_low;
+ /** The VA manager for the 32bit address space */
+ struct amdgpu_bo_va_mgr vamgr_32;
+ /** The VA manager for the high virtual address space */
+ struct amdgpu_bo_va_mgr vamgr_high;
+ /** The VA manager for the 32bit high address space */
+ struct amdgpu_bo_va_mgr vamgr_high_32;
+};
+
struct amdgpu_device {
atomic_t refcount;
struct amdgpu_device *next;
@@ -80,14 +91,8 @@ struct amdgpu_device {
pthread_mutex_t bo_table_mutex;
struct drm_amdgpu_info_device dev_info;
struct amdgpu_gpu_info info;
- /** The VA manager for the lower virtual address space */
- struct amdgpu_bo_va_mgr vamgr;
- /** The VA manager for the 32bit address space */
- struct amdgpu_bo_va_mgr vamgr_32;
- /** The VA manager for the high virtual address space */
- struct amdgpu_bo_va_mgr vamgr_high;
- /** The VA manager for the 32bit high address space */
- struct amdgpu_bo_va_mgr vamgr_high_32;
+
+ struct amdgpu_va_manager va_mgr;
};
struct amdgpu_bo {
diff --git a/amdgpu/amdgpu_vamgr.c b/amdgpu/amdgpu_vamgr.c
index 2c4c9db..29944ec 100644
--- a/amdgpu/amdgpu_vamgr.c
+++ b/amdgpu/amdgpu_vamgr.c
@@ -229,24 +229,39 @@ drm_public int amdgpu_va_range_alloc(amdgpu_device_handle dev,
amdgpu_va_handle *va_range_handle,
uint64_t flags)
{
+ return amdgpu_va_range_alloc2(&dev->va_mgr, va_range_type, size,
+ va_base_alignment, va_base_required,
+ va_base_allocated, va_range_handle,
+ flags);
+}
+
+drm_public int amdgpu_va_range_alloc2(amdgpu_va_manager_handle va_mgr,
+ enum amdgpu_gpu_va_range va_range_type,
+ uint64_t size,
+ uint64_t va_base_alignment,
+ uint64_t va_base_required,
+ uint64_t *va_base_allocated,
+ amdgpu_va_handle *va_range_handle,
+ uint64_t flags)
+{
struct amdgpu_bo_va_mgr *vamgr;
bool search_from_top = !!(flags & AMDGPU_VA_RANGE_REPLAYABLE);
int ret;
/* Clear the flag when the high VA manager is not initialized */
- if (flags & AMDGPU_VA_RANGE_HIGH && !dev->vamgr_high_32.va_max)
+ if (flags & AMDGPU_VA_RANGE_HIGH && !va_mgr->vamgr_high_32.va_max)
flags &= ~AMDGPU_VA_RANGE_HIGH;
if (flags & AMDGPU_VA_RANGE_HIGH) {
if (flags & AMDGPU_VA_RANGE_32_BIT)
- vamgr = &dev->vamgr_high_32;
+ vamgr = &va_mgr->vamgr_high_32;
else
- vamgr = &dev->vamgr_high;
+ vamgr = &va_mgr->vamgr_high;
} else {
if (flags & AMDGPU_VA_RANGE_32_BIT)
- vamgr = &dev->vamgr_32;
+ vamgr = &va_mgr->vamgr_32;
else
- vamgr = &dev->vamgr;
+ vamgr = &va_mgr->vamgr_low;
}
va_base_alignment = MAX2(va_base_alignment, vamgr->va_alignment);
@@ -259,9 +274,9 @@ drm_public int amdgpu_va_range_alloc(amdgpu_device_handle dev,
if (!(flags & AMDGPU_VA_RANGE_32_BIT) && ret) {
/* fallback to 32bit address */
if (flags & AMDGPU_VA_RANGE_HIGH)
- vamgr = &dev->vamgr_high_32;
+ vamgr = &va_mgr->vamgr_high_32;
else
- vamgr = &dev->vamgr_32;
+ vamgr = &va_mgr->vamgr_32;
ret = amdgpu_vamgr_find_va(vamgr, size,
va_base_alignment, va_base_required,
search_from_top, va_base_allocated);
@@ -300,3 +315,45 @@ drm_public uint64_t amdgpu_va_get_start_addr(amdgpu_va_handle va_handle)
{
return va_handle->address;
}
+
+drm_public amdgpu_va_manager_handle amdgpu_va_manager_alloc(void)
+{
+ amdgpu_va_manager_handle r = calloc(1, sizeof(struct amdgpu_va_manager));
+ return r;
+}
+
+drm_public void amdgpu_va_manager_init(struct amdgpu_va_manager *va_mgr,
+ uint64_t low_va_offset, uint64_t low_va_max,
+ uint64_t high_va_offset, uint64_t high_va_max,
+ uint32_t virtual_address_alignment)
+{
+ uint64_t start, max;
+
+ start = low_va_offset;
+ max = MIN2(low_va_max, 0x100000000ULL);
+ amdgpu_vamgr_init(&va_mgr->vamgr_32, start, max,
+ virtual_address_alignment);
+
+ start = max;
+ max = MAX2(low_va_max, 0x100000000ULL);
+ amdgpu_vamgr_init(&va_mgr->vamgr_low, start, max,
+ virtual_address_alignment);
+
+ start = high_va_offset;
+ max = MIN2(high_va_max, (start & ~0xffffffffULL) + 0x100000000ULL);
+ amdgpu_vamgr_init(&va_mgr->vamgr_high_32, start, max,
+ virtual_address_alignment);
+
+ start = max;
+ max = MAX2(high_va_max, (start & ~0xffffffffULL) + 0x100000000ULL);
+ amdgpu_vamgr_init(&va_mgr->vamgr_high, start, max,
+ virtual_address_alignment);
+}
+
+drm_public void amdgpu_va_manager_deinit(struct amdgpu_va_manager *va_mgr)
+{
+ amdgpu_vamgr_deinit(&va_mgr->vamgr_32);
+ amdgpu_vamgr_deinit(&va_mgr->vamgr_low);
+ amdgpu_vamgr_deinit(&va_mgr->vamgr_high_32);
+ amdgpu_vamgr_deinit(&va_mgr->vamgr_high);
+}
diff --git a/data/amdgpu.ids b/data/amdgpu.ids
index 0e79a58..f2a4fc1 100644
--- a/data/amdgpu.ids
+++ b/data/amdgpu.ids
@@ -29,6 +29,46 @@
131B, 00, AMD Radeon R4 Graphics
131C, 00, AMD Radeon R7 Graphics
131D, 00, AMD Radeon R6 Graphics
+1435, AE, AMD Custom GPU 0932
+1506, C1, AMD Radeon 610M
+1506, C2, AMD Radeon 610M
+1506, C3, AMD Radeon 610M
+1506, C4, AMD Radeon 610M
+15BF, 00, AMD Radeon 780M
+15BF, 01, AMD Radeon 760M
+15BF, 02, AMD Radeon 780M
+15BF, 03, AMD Radeon 760M
+15BF, C1, AMD Radeon 780M
+15BF, C2, AMD Radeon 780M
+15BF, C3, AMD Radeon 760M
+15BF, C4, AMD Radeon 780M
+15BF, C5, AMD Radeon 740M
+15BF, C6, AMD Radeon 780M
+15BF, C7, AMD Radeon 780M
+15BF, C8, AMD Radeon 760M
+15BF, C9, AMD Radeon 780M
+15BF, CA, AMD Radeon 740M
+15BF, CB, AMD Radeon 760M
+15BF, CD, AMD Radeon 760M
+15BF, CF, AMD Radeon 780M
+15BF, D3, AMD Radeon 780M
+15BF, D4, AMD Radeon 780M
+15BF, D5, AMD Radeon 760M
+15BF, D6, AMD Radeon 760M
+15BF, D7, AMD Radeon 780M
+15BF, D8, AMD Radeon 740M
+15BF, D9, AMD Radeon 780M
+15BF, DA, AMD Radeon 780M
+15BF, DB, AMD Radeon 760M
+15BF, DD, AMD Radeon 780M
+15BF, DE, AMD Radeon 740M
+15BF, F0, AMD Radeon 760M
+15C8, C1, AMD Radeon 740M
+15C8, C2, AMD Radeon 740M
+15C8, C3, AMD Radeon 740M
+15C8, C4, AMD Radeon 740M
+15C8, D1, AMD Radeon 740M
+15C8, D3, AMD Radeon 740M
15D8, 00, AMD Radeon RX Vega 8 Graphics WS
15D8, 91, AMD Radeon Vega 3 Graphics
15D8, 91, AMD Ryzen Embedded R1606G with Radeon Vega Gfx
@@ -101,6 +141,19 @@
15DD, E1, AMD Radeon Vega 3 Graphics
15DD, E2, AMD Radeon Vega 3 Graphics
163F, AE, AMD Custom GPU 0405
+163F, E1, AMD Custom GPU 0405
+164E, D8, AMD Radeon 610M
+164E, D9, AMD Radeon 610M
+164E, DA, AMD Radeon 610M
+164E, DB, AMD Radeon 610M
+164E, DC, AMD Radeon 610M
+1681, 06, AMD Radeon 680M
+1681, 07, AMD Radeon 660M
+1681, 0A, AMD Radeon 680M
+1681, 0B, AMD Radeon 660M
+1681, C7, AMD Radeon 680M
+1681, C8, AMD Radeon 680M
+1681, C9, AMD Radeon 660M
6600, 00, AMD Radeon HD 8600 / 8700M
6600, 81, AMD Radeon R7 M370
6601, 00, AMD Radeon HD 8500M / 8700M
@@ -368,7 +421,12 @@
73DF, C3, AMD Radeon RX 6800M
73DF, C5, AMD Radeon RX 6700 XT
73DF, CF, AMD Radeon RX 6700M
+73DF, D5, AMD Radeon RX 6750 GRE 12GB
73DF, D7, AMD TDC-235
+73DF, DF, AMD Radeon RX 6700
+73DF, E5, AMD Radeon RX 6750 GRE 12GB
+73DF, FF, AMD Radeon RX 6700
+73E0, 00, AMD Radeon RX 6600M
73E1, 00, AMD Radeon Pro W6600M
73E3, 00, AMD Radeon Pro W6600
73EF, C0, AMD Radeon RX 6800S
@@ -380,6 +438,8 @@
73FF, C3, AMD Radeon RX 6600M
73FF, C7, AMD Radeon RX 6600
73FF, CB, AMD Radeon RX 6600S
+73FF, CF, AMD Radeon RX 6600 LE
+73FF, DF, AMD Radeon RX 6750 GRE 10GB
7408, 00, AMD Instinct MI250X
740C, 01, AMD Instinct MI250X / MI250
740F, 02, AMD Instinct MI210
@@ -394,22 +454,29 @@
743F, C7, AMD Radeon RX 6400
743F, C8, AMD Radeon RX 6500M
743F, CC, AMD Radeon 6550S
+743F, CE, AMD Radeon RX 6450M
743F, CF, AMD Radeon RX 6300M
+743F, D3, AMD Radeon RX 6550M
743F, D7, AMD Radeon RX 6400
7448, 00, AMD Radeon Pro W7900
744C, C8, AMD Radeon RX 7900 XTX
744C, CC, AMD Radeon RX 7900 XT
744C, CE, AMD Radeon RX 7900 GRE
+744C, CF, AMD Radeon RX 7900M
745E, CC, AMD Radeon Pro W7800
+7470, 00, AMD Radeon Pro W7700
747E, C8, AMD Radeon RX 7800 XT
747E, FF, AMD Radeon RX 7700 XT
7480, 00, AMD Radeon Pro W7600
+7480, C0, AMD Radeon RX 7600 XT
7480, C1, AMD Radeon RX 7700S
7480, C3, AMD Radeon RX 7600S
7480, C7, AMD Radeon RX 7600M XT
7480, CF, AMD Radeon RX 7600
7483, CF, AMD Radeon RX 7600M
7489, 00, AMD Radeon Pro W7500
+74A0, 00, AMD Instinct MI300A
+74A1, 00, AMD Instinct MI300X
9830, 00, AMD Radeon HD 8400 / R3 Series
9831, 00, AMD Radeon HD 8400E
9832, 00, AMD Radeon HD 8330
diff --git a/etnaviv/meson.build b/etnaviv/meson.build
index 9ccf869..b965096 100644
--- a/etnaviv/meson.build
+++ b/etnaviv/meson.build
@@ -61,6 +61,6 @@ test(
args : [
'--lib', libdrm_etnaviv,
'--symbols-file', files('etnaviv-symbols.txt'),
- '--nm', prog_nm.path(),
+ '--nm', prog_nm.full_path(),
],
)
diff --git a/exynos/meson.build b/exynos/meson.build
index 6b4fe1e..c87be6b 100644
--- a/exynos/meson.build
+++ b/exynos/meson.build
@@ -56,6 +56,6 @@ test(
args : [
'--lib', libdrm_exynos,
'--symbols-file', files('exynos-symbols.txt'),
- '--nm', prog_nm.path(),
+ '--nm', prog_nm.full_path(),
],
)
diff --git a/freedreno/meson.build b/freedreno/meson.build
index 5ba1a3f..1d1bd82 100644
--- a/freedreno/meson.build
+++ b/freedreno/meson.build
@@ -77,6 +77,6 @@ test(
args : [
'--lib', libdrm_freedreno,
'--symbols-file', files('freedreno-symbols.txt'),
- '--nm', prog_nm.path(),
+ '--nm', prog_nm.full_path(),
],
)
diff --git a/include/drm/amdgpu_drm.h b/include/drm/amdgpu_drm.h
index ad21c61..ae3f4e2 100644
--- a/include/drm/amdgpu_drm.h
+++ b/include/drm/amdgpu_drm.h
@@ -392,7 +392,7 @@ struct drm_amdgpu_gem_userptr {
#define AMDGPU_TILING_NUM_BANKS_SHIFT 21
#define AMDGPU_TILING_NUM_BANKS_MASK 0x3
-/* GFX9 and later: */
+/* GFX9 - GFX11: */
#define AMDGPU_TILING_SWIZZLE_MODE_SHIFT 0
#define AMDGPU_TILING_SWIZZLE_MODE_MASK 0x1f
#define AMDGPU_TILING_DCC_OFFSET_256B_SHIFT 5
@@ -406,6 +406,17 @@ struct drm_amdgpu_gem_userptr {
#define AMDGPU_TILING_SCANOUT_SHIFT 63
#define AMDGPU_TILING_SCANOUT_MASK 0x1
+/* GFX12 and later: */
+#define AMDGPU_TILING_GFX12_SWIZZLE_MODE_SHIFT 0
+#define AMDGPU_TILING_GFX12_SWIZZLE_MODE_MASK 0x7
+/* These are DCC recompression setting for memory management: */
+#define AMDGPU_TILING_GFX12_DCC_MAX_COMPRESSED_BLOCK_SHIFT 3
+#define AMDGPU_TILING_GFX12_DCC_MAX_COMPRESSED_BLOCK_MASK 0x3 /* 0:64B, 1:128B, 2:256B */
+#define AMDGPU_TILING_GFX12_DCC_NUMBER_TYPE_SHIFT 5
+#define AMDGPU_TILING_GFX12_DCC_NUMBER_TYPE_MASK 0x7 /* CB_COLOR0_INFO.NUMBER_TYPE */
+#define AMDGPU_TILING_GFX12_DCC_DATA_FORMAT_SHIFT 8
+#define AMDGPU_TILING_GFX12_DCC_DATA_FORMAT_MASK 0x3f /* [0:4]:CB_COLOR0_INFO.FORMAT, [5]:MM */
+
/* Set/Get helpers for tiling flags. */
#define AMDGPU_TILING_SET(field, value) \
(((__u64)(value) & AMDGPU_TILING_##field##_MASK) << AMDGPU_TILING_##field##_SHIFT)
@@ -743,6 +754,16 @@ struct drm_amdgpu_cs_chunk_cp_gfx_shadow {
#define AMDGPU_IDS_FLAGS_TMZ 0x4
#define AMDGPU_IDS_FLAGS_CONFORMANT_TRUNC_COORD 0x8
+/*
+ * Query h/w info: Flag identifying VF/PF/PT mode
+ *
+ */
+#define AMDGPU_IDS_FLAGS_MODE_MASK 0x300
+#define AMDGPU_IDS_FLAGS_MODE_SHIFT 0x8
+#define AMDGPU_IDS_FLAGS_MODE_PF 0x0
+#define AMDGPU_IDS_FLAGS_MODE_VF 0x1
+#define AMDGPU_IDS_FLAGS_MODE_PT 0x2
+
/* indicate if acceleration can be working */
#define AMDGPU_INFO_ACCEL_WORKING 0x00
/* get the crtc_id from the mode object id? */
@@ -865,6 +886,8 @@ struct drm_amdgpu_cs_chunk_cp_gfx_shadow {
#define AMDGPU_INFO_SENSOR_PEAK_PSTATE_GFX_SCLK 0xa
/* Subquery id: Query GPU peak pstate memory clock */
#define AMDGPU_INFO_SENSOR_PEAK_PSTATE_GFX_MCLK 0xb
+ /* Subquery id: Query input GPU power */
+ #define AMDGPU_INFO_SENSOR_GPU_INPUT_POWER 0xc
/* Number of VRAM page faults on CPU access. */
#define AMDGPU_INFO_NUM_VRAM_CPU_PAGE_FAULTS 0x1E
#define AMDGPU_INFO_VRAM_LOST_COUNTER 0x1F
@@ -1266,6 +1289,7 @@ struct drm_amdgpu_info_gpuvm_fault {
#define AMDGPU_FAMILY_GC_10_3_6 149 /* GC 10.3.6 */
#define AMDGPU_FAMILY_GC_10_3_7 151 /* GC 10.3.7 */
#define AMDGPU_FAMILY_GC_11_5_0 150 /* GC 11.5.0 */
+#define AMDGPU_FAMILY_GC_12_0_0 152 /* GC 12.0.0 */
#if defined(__cplusplus)
}
diff --git a/intel/meson.build b/intel/meson.build
index 4af2a35..e609449 100644
--- a/intel/meson.build
+++ b/intel/meson.build
@@ -104,6 +104,6 @@ test(
args : [
'--lib', libdrm_intel,
'--symbols-file', files('intel-symbols.txt'),
- '--nm', prog_nm.path(),
+ '--nm', prog_nm.full_path(),
],
)
diff --git a/libsync.h b/libsync.h
index f1a2f96..c6b64ed 100644
--- a/libsync.h
+++ b/libsync.h
@@ -33,7 +33,7 @@
#include <stdint.h>
#include <string.h>
#include <sys/ioctl.h>
-#include <sys/poll.h>
+#include <poll.h>
#include <unistd.h>
#if defined(__cplusplus)
diff --git a/meson.build b/meson.build
index 1a7dbbe..f083957 100644
--- a/meson.build
+++ b/meson.build
@@ -21,7 +21,7 @@
project(
'libdrm',
['c'],
- version : '2.4.120',
+ version : '2.4.121',
license : 'MIT',
meson_version : '>= 0.59',
default_options : ['buildtype=debugoptimized', 'c_std=c11'],
@@ -235,7 +235,7 @@ config_file = configure_file(
configuration : config,
output : 'config.h',
)
-add_project_arguments('-include', '@0@'.format(config_file), language : 'c')
+add_project_arguments('-include', meson.current_build_dir() / 'config.h', language : 'c')
inc_root = include_directories('.')
inc_drm = include_directories('include/drm')
diff --git a/omap/meson.build b/omap/meson.build
index eebd142..8856d4a 100644
--- a/omap/meson.build
+++ b/omap/meson.build
@@ -56,6 +56,6 @@ test(
args : [
'--lib', libdrm_omap,
'--symbols-file', files('omap-symbols.txt'),
- '--nm', prog_nm.path(),
+ '--nm', prog_nm.full_path(),
],
)
diff --git a/symbols-check.py b/symbols-check.py
index 2e7ba68..c63c0d1 100644
--- a/symbols-check.py
+++ b/symbols-check.py
@@ -7,6 +7,7 @@ import subprocess
# This list contains symbols that _might_ be exported for some platforms
PLATFORM_SYMBOLS = [
+ '_GLOBAL_OFFSET_TABLE_',
'__bss_end__',
'__bss_start__',
'__bss_start',
@@ -16,6 +17,9 @@ PLATFORM_SYMBOLS = [
'_end',
'_fini',
'_init',
+ '_fbss',
+ '_fdata',
+ '_ftext',
]
diff --git a/tegra/job.c b/tegra/job.c
index 75a344f..b9af498 100644
--- a/tegra/job.c
+++ b/tegra/job.c
@@ -33,7 +33,7 @@
#include <unistd.h>
#include <sys/ioctl.h>
-#include <sys/poll.h>
+#include <poll.h>
#include "private.h"
diff --git a/tegra/meson.build b/tegra/meson.build
index 5325ed7..11ce217 100644
--- a/tegra/meson.build
+++ b/tegra/meson.build
@@ -59,6 +59,6 @@ test(
args : [
'--lib', libdrm_tegra,
'--symbols-file', files('tegra-symbols.txt'),
- '--nm', prog_nm.path(),
+ '--nm', prog_nm.full_path(),
],
)
diff --git a/tests/amdgpu/shader_code.h b/tests/amdgpu/shader_code.h
index 74d32bb..164c619 100644
--- a/tests/amdgpu/shader_code.h
+++ b/tests/amdgpu/shader_code.h
@@ -75,13 +75,13 @@ struct shader_test_cs_shader {
struct shader_test_ps_shader {
const uint32_t *shader;
unsigned shader_size;
- const uint32_t patchinfo_code_size;
+ uint32_t patchinfo_code_size;
const uint32_t *patchinfo_code;
const uint32_t *patchinfo_code_offset;
const struct reg_info *sh_reg;
- const uint32_t num_sh_reg;
+ uint32_t num_sh_reg;
const struct reg_info *context_reg;
- const uint32_t num_context_reg;
+ uint32_t num_context_reg;
};
struct shader_test_vs_shader {
@@ -111,7 +111,7 @@ static const struct shader_test_cs_shader shader_test_cs[AMDGPU_TEST_GFX_MAX][2]
#define SHADER_PS_INFO(_ps, _n) \
{ps_##_ps##_shader_gfx##_n, sizeof(ps_##_ps##_shader_gfx##_n), \
ps_##_ps##_shader_patchinfo_code_size_gfx##_n, \
- ps_##_ps##_shader_patchinfo_code_gfx##_n, \
+ &(ps_##_ps##_shader_patchinfo_code_gfx##_n)[0][0][0], \
ps_##_ps##_shader_patchinfo_offset_gfx##_n, \
ps_##_ps##_sh_registers_gfx##_n, ps_##_ps##_num_sh_registers_gfx##_n, \
ps_##_ps##_context_registers_gfx##_n, ps_##_ps##_num_context_registers_gfx##_n}
diff --git a/tests/amdgpu/shader_code_gfx10.h b/tests/amdgpu/shader_code_gfx10.h
index 4849bbc..1e7c8f9 100644
--- a/tests/amdgpu/shader_code_gfx10.h
+++ b/tests/amdgpu/shader_code_gfx10.h
@@ -41,7 +41,7 @@ static const uint32_t ps_const_shader_gfx10[] = {
0xF8001C0F, 0x00000100, 0xBF810000
};
-static const uint32_t ps_const_shader_patchinfo_code_size_gfx10 = 6;
+#define ps_const_shader_patchinfo_code_size_gfx10 6
static const uint32_t ps_const_shader_patchinfo_code_gfx10[][10][6] = {
{{ 0xBF800000, 0xBF800000, 0xBF800000, 0xBF800000, 0xF8001890, 0x00000000 },
@@ -61,7 +61,7 @@ static const uint32_t ps_const_shader_patchinfo_offset_gfx10[] = {
0x00000004
};
-static const uint32_t ps_const_num_sh_registers_gfx10 = 2;
+#define ps_const_num_sh_registers_gfx10 2
static const struct reg_info ps_const_sh_registers_gfx10[] = {
{0x2C0A, 0x000C0000},//{ mmSPI_SHADER_PGM_RSRC1_PS, 0x000C0000 },
@@ -79,7 +79,7 @@ static const struct reg_info ps_const_context_registers_gfx10[] =
{0xA1C5, 0x00000004}, //{ mmSPI_SHADER_COL_FORMAT, 0x00000004 /* SI_EXPORT_FMT_FP16_ABGR */ }
};
-static const uint32_t ps_const_num_context_registers_gfx10 = 7;
+#define ps_const_num_context_registers_gfx10 7
static const uint32_t ps_tex_shader_gfx10[] = {
0xBEFC030C, 0xBE8E047E, 0xBEFE0A7E, 0xC8080000,
@@ -93,7 +93,7 @@ static const uint32_t ps_tex_shader_patchinfo_offset_gfx10[] = {
0x0000000C
};
-static const uint32_t ps_tex_shader_patchinfo_code_size_gfx10 = 6;
+#define ps_tex_shader_patchinfo_code_size_gfx10 6
static const uint32_t ps_tex_shader_patchinfo_code_gfx10[][10][6] = {
{{ 0xBF800000, 0xBF800000, 0xBF800000, 0xBF800000, 0xF8001890, 0x00000000 },
@@ -115,7 +115,7 @@ static const struct reg_info ps_tex_sh_registers_gfx10[] =
{0x2C0B, 0x00000018 }, //{ mmSPI_SHADER_PGM_RSRC2_PS, 0x00000018 }
};
-static const uint32_t ps_tex_num_sh_registers_gfx10 = 2;
+#define ps_tex_num_sh_registers_gfx10 2
// Holds Context Register Information
static const struct reg_info ps_tex_context_registers_gfx10[] =
@@ -129,7 +129,7 @@ static const struct reg_info ps_tex_context_registers_gfx10[] =
{0xA1C5, 0x00000004}, //{ mmSPI_SHADER_COL_FORMAT, 0x00000004 /* SI_EXPORT_FMT_FP16_ABGR */ }
};
-static const uint32_t ps_tex_num_context_registers_gfx10 = 7;
+#define ps_tex_num_context_registers_gfx10 7
static const uint32_t vs_RectPosTexFast_shader_gfx10[] = {
0x7E000B00, 0x060000F3, 0x7E020202, 0x7E040206,
@@ -148,7 +148,7 @@ static const struct reg_info vs_RectPosTexFast_sh_registers_gfx10[] =
{0x2C4B, 0x00000018 }, //{ mmSPI_SHADER_PGM_RSRC2_VS, 0x00000018 }
};
-static const uint32_t vs_RectPosTexFast_num_sh_registers_gfx10 = 2;
+#define vs_RectPosTexFast_num_sh_registers_gfx10 2
// Holds Context Register Information
static const struct reg_info vs_RectPosTexFast_context_registers_gfx10[] =
@@ -157,7 +157,7 @@ static const struct reg_info vs_RectPosTexFast_context_registers_gfx10[] =
{0xA1C3, 0x00000000}, //{ mmSPI_SHADER_POS_FORMAT, 0x00000000 /* Always 0 for now */}
};
-static const uint32_t vs_RectPosTexFast_num_context_registers_gfx10 = 2;
+#define vs_RectPosTexFast_num_context_registers_gfx10 2
static const uint32_t preamblecache_gfx10[] = {
0xc0026900, 0x81, 0x80000000, 0x40004000, 0xc0026900, 0x8c, 0xaa99aaaa, 0x0,
@@ -196,7 +196,7 @@ static const uint32_t cached_cmd_gfx10[] = {
0xc0026900, 0x2b0, 0x0, 0x0, 0xc0016900, 0x2f8, 0x0
};
-static const uint32_t sh_reg_base_gfx10 = 0x2C00;
-static const uint32_t context_reg_base_gfx10 = 0xA000;
+#define sh_reg_base_gfx10 0x2C00
+#define context_reg_base_gfx10 0xA000
#endif
diff --git a/tests/amdgpu/shader_code_gfx11.h b/tests/amdgpu/shader_code_gfx11.h
index d9ee0a7..8a998ae 100644
--- a/tests/amdgpu/shader_code_gfx11.h
+++ b/tests/amdgpu/shader_code_gfx11.h
@@ -101,7 +101,7 @@ static const uint32_t ps_const_shader_gfx11[] = {
0xBF9F0000
};
-static const uint32_t ps_const_shader_patchinfo_code_size_gfx11 = 6;
+#define ps_const_shader_patchinfo_code_size_gfx11 6
static const uint32_t ps_const_shader_patchinfo_code_gfx11[][10][6] = {
{{ 0xBF800000, 0xBF800000, 0xBF800000, 0xBF800000, 0xF8000890, 0x00000000 }, // SI_EXPORT_FMT_ZERO
@@ -121,7 +121,7 @@ static const uint32_t ps_const_shader_patchinfo_offset_gfx11[] = {
0x00000006
};
-static const uint32_t ps_const_num_sh_registers_gfx11 = 2;
+#define ps_const_num_sh_registers_gfx11 2
static const struct reg_info ps_const_sh_registers_gfx11[] = {
{0x2C0A, 0x020C0000}, //{ mmSPI_SHADER_PGM_RSRC1_PS, 0x020C0000 },
@@ -138,7 +138,7 @@ static const struct reg_info ps_const_context_registers_gfx11[] = {
{0xA1C5, 0x00000004 }, //{ mmSPI_SHADER_COL_FORMAT, 0x00000004 /* SI_EXPORT_FMT_FP16_ABGR */ }
};
-static const uint32_t ps_const_num_context_registers_gfx11 = 7;
+#define ps_const_num_context_registers_gfx11 7
static const uint32_t ps_tex_shader_gfx11[] =
{
@@ -174,7 +174,7 @@ static const uint32_t ps_tex_shader_patchinfo_offset_gfx11[] =
};
// Denotes the Patch Info Code Length
-static const uint32_t ps_tex_shader_patchinfo_code_size_gfx11 = 6;
+#define ps_tex_shader_patchinfo_code_size_gfx11 6
static const uint32_t ps_tex_shader_patchinfo_code_gfx11[][10][6] =
{
@@ -197,7 +197,7 @@ static const struct reg_info ps_tex_sh_registers_gfx11[] =
{0x2C0B, 0x00000018 } //{ mmSPI_SHADER_PGM_RSRC2_PS, 0x00000018 }
};
-static const uint32_t ps_tex_num_sh_registers_gfx11 = 2;
+#define ps_tex_num_sh_registers_gfx11 2
// Holds Context Register Information
static const struct reg_info ps_tex_context_registers_gfx11[] =
@@ -211,8 +211,7 @@ static const struct reg_info ps_tex_context_registers_gfx11[] =
{0xA1C5, 0x00000004 } //{ mmSPI_SHADER_COL_FORMAT, 0x00000004 /* SI_EXPORT_FMT_FP16_ABGR */ }
};
-static const uint32_t ps_tex_num_context_registers_gfx11 = 7;
-
+#define ps_tex_num_context_registers_gfx11 7
static const uint32_t vs_RectPosTexFast_shader_gfx11[] =
{
@@ -261,7 +260,7 @@ static const struct reg_info vs_RectPosTexFast_sh_registers_gfx11[] =
{0x2C8B, 0x0008001C}, //{ mmSPI_SHADER_PGM_RSRC2_GS, 0x0008001C }
};
-static const uint32_t vs_RectPosTexFast_num_sh_registers_gfx11 = 2;
+#define vs_RectPosTexFast_num_sh_registers_gfx11 2
// Holds Context Register Information
static const struct reg_info vs_RectPosTexFast_context_registers_gfx11[] =
@@ -274,7 +273,7 @@ static const struct reg_info vs_RectPosTexFast_context_registers_gfx11[] =
{0xA2CE, 0x00000001}, //{ mmVGT_GS_MAX_VERT_OUT, 0x00000001 }
};
-static const uint32_t vs_RectPosTexFast_num_context_registers_gfx11 = 6;
+#define vs_RectPosTexFast_num_context_registers_gfx11 6
static const uint32_t preamblecache_gfx11[] = {
0xc0026900, 0x81, 0x80000000, 0x40004000, 0xc0026900, 0x8c, 0xaa99aaaa, 0x0,
@@ -314,7 +313,8 @@ static const uint32_t cached_cmd_gfx11[] = {
0xc0046900, 0x1d5, 0x0, 0x0, 0x0, 0x0, 0xc0016900, 0x104, 0x4a00005,
0xc0016900, 0x1f, 0xf2a0055, 0xc0017900, 0x266, 0x4
};
-static const uint32_t sh_reg_base_gfx11 = 0x2C00;
-static const uint32_t context_reg_base_gfx11 = 0xA000;
+
+#define sh_reg_base_gfx11 0x2C00
+#define context_reg_base_gfx11 0xA000
#endif
diff --git a/tests/amdgpu/shader_code_gfx9.h b/tests/amdgpu/shader_code_gfx9.h
index 3ad1ca8..1cb6582 100644
--- a/tests/amdgpu/shader_code_gfx9.h
+++ b/tests/amdgpu/shader_code_gfx9.h
@@ -51,7 +51,7 @@ static const uint32_t ps_const_shader_gfx9[] = {
0xC4001C0F, 0x00000100, 0xBF810000
};
-static const uint32_t ps_const_shader_patchinfo_code_size_gfx9 = 6;
+#define ps_const_shader_patchinfo_code_size_gfx9 6
static const uint32_t ps_const_shader_patchinfo_code_gfx9[][10][6] = {
{{ 0xBF800000, 0xBF800000, 0xBF800000, 0xBF800000, 0xC4001890, 0x00000000 },
@@ -71,14 +71,14 @@ static const uint32_t ps_const_shader_patchinfo_offset_gfx9[] = {
0x00000004
};
-static const uint32_t ps_const_num_sh_registers_gfx9 = 2;
+#define ps_const_num_sh_registers_gfx9 2
static const struct reg_info ps_const_sh_registers_gfx9[] = {
{0x2C0A, 0x000C0040},//{ mmSPI_SHADER_PGM_RSRC1_PS, 0x000C0040 },
{0x2C0B, 0x00000008}, //{ mmSPI_SHADER_PGM_RSRC2_PS, 0x00000008 }
};
-static const uint32_t ps_const_num_context_registers_gfx9 = 7;
+#define ps_const_num_context_registers_gfx9 7
static const struct reg_info ps_const_context_registers_gfx9[] = {
{0xA1B4, 0x00000002}, //{ mmSPI_PS_INPUT_ADDR, 0x00000002 },
@@ -102,7 +102,7 @@ static const uint32_t ps_tex_shader_patchinfo_offset_gfx9[] = {
0x0000000B
};
-static const uint32_t ps_tex_shader_patchinfo_code_size_gfx9 = 6;
+#define ps_tex_shader_patchinfo_code_size_gfx9 6
static const uint32_t ps_tex_shader_patchinfo_code_gfx9[][10][6] = {
{{ 0xBF800000, 0xBF800000, 0xBF800000, 0xBF800000, 0xC4001890, 0x00000000 },
@@ -118,13 +118,14 @@ static const uint32_t ps_tex_shader_patchinfo_code_gfx9[][10][6] = {
}
};
-static const uint32_t ps_tex_num_sh_registers_gfx9 = 2;
+#define ps_tex_num_sh_registers_gfx9 2
+
static const struct reg_info ps_tex_sh_registers_gfx9[] = {
{0x2C0A, 0x000C0081},//{ mmSPI_SHADER_PGM_RSRC1_PS, 0x000C0081 },
{0x2C0B, 0x00000018}, //{ mmSPI_SHADER_PGM_RSRC2_PS, 0x00000018 }
};
-static const uint32_t ps_tex_num_context_registers_gfx9 = 7;
+#define ps_tex_num_context_registers_gfx9 7
static const struct reg_info ps_tex_context_registers_gfx9[] = {
{0xA1B4, 0x00000002}, //{ mmSPI_PS_INPUT_ADDR, 0x00000002 },
@@ -153,7 +154,7 @@ static const struct reg_info vs_RectPosTexFast_sh_registers_gfx9[] =
{0x2C4B, 0x00000018}, //{ mmSPI_SHADER_PGM_RSRC2_VS, 0x00000018 }
};
-static const uint32_t vs_RectPosTexFast_num_sh_registers_gfx9 = 2;
+#define vs_RectPosTexFast_num_sh_registers_gfx9 2
// Holds Context Register Information
static const struct reg_info vs_RectPosTexFast_context_registers_gfx9[] =
@@ -162,7 +163,7 @@ static const struct reg_info vs_RectPosTexFast_context_registers_gfx9[] =
{0xA1C3, 0x00000000}, //{ mmSPI_SHADER_POS_FORMAT, 0x00000000 /* Always 0 for now */}
};
-static const uint32_t vs_RectPosTexFast_num_context_registers_gfx9 = 2;
+#define vs_RectPosTexFast_num_context_registers_gfx9 2
static const uint32_t preamblecache_gfx9[] = {
0xc0026900, 0x81, 0x80000000, 0x40004000, 0xc0026900, 0x8c, 0xaa99aaaa, 0x0,
@@ -198,7 +199,7 @@ static const uint32_t cached_cmd_gfx9[] = {
0xc0026900, 0x2b0, 0x0, 0x0, 0xc0016900, 0x2f8, 0x0
};
-static const uint32_t sh_reg_base_gfx9 = 0x2C00;
-static const uint32_t context_reg_base_gfx9 = 0xA000;
+#define sh_reg_base_gfx9 0x2C00
+#define context_reg_base_gfx9 0xA000
#endif
diff --git a/tests/amdgpu/shader_test_util.c b/tests/amdgpu/shader_test_util.c
index 60148fb..8a19f59 100644
--- a/tests/amdgpu/shader_test_util.c
+++ b/tests/amdgpu/shader_test_util.c
@@ -4,6 +4,7 @@
#include <sys/types.h>
#include <sys/stat.h>
#include <string.h>
+#include <assert.h>
#include "CUnit/Basic.h"
#include "amdgpu_test.h"
@@ -303,6 +304,9 @@ static void amdgpu_dispatch_init(struct shader_test_priv *test_priv)
case AMDGPU_TEST_GFX_V11:
amdgpu_dispatch_init_gfx11(test_priv);
break;
+ case AMDGPU_TEST_GFX_MAX:
+ assert(1 && "Not Support gfx, never go here");
+ break;
}
}
@@ -338,6 +342,9 @@ static void amdgpu_dispatch_write_cumask(struct shader_test_priv *test_priv)
ptr[i++] = 0xffffffff;
ptr[i++] = 0xffffffff;
break;
+ case AMDGPU_TEST_GFX_MAX:
+ assert(1 && "Not Support gfx, never go here");
+ break;
}
test_priv->cmd_curr = i;
@@ -541,6 +548,9 @@ static void amdgpu_dispatch_write2hw(struct shader_test_priv *test_priv)
case AMDGPU_TEST_GFX_V11:
amdgpu_dispatch_write2hw_gfx11(test_priv);
break;
+ case AMDGPU_TEST_GFX_MAX:
+ assert(1 && "Not Support gfx, never go here");
+ break;
}
}
@@ -1168,6 +1178,9 @@ static void amdgpu_draw_setup_and_write_drawblt_surf_info(struct shader_test_pri
case AMDGPU_TEST_GFX_V11:
amdgpu_draw_setup_and_write_drawblt_surf_info_gfx11(test_priv);
break;
+ case AMDGPU_TEST_GFX_MAX:
+ assert(1 && "Not Support gfx, never go here");
+ break;
}
}
@@ -1298,6 +1311,9 @@ static void amdgpu_draw_setup_and_write_drawblt_state(struct shader_test_priv *t
case AMDGPU_TEST_GFX_V11:
amdgpu_draw_setup_and_write_drawblt_state_gfx11(test_priv);
break;
+ case AMDGPU_TEST_GFX_MAX:
+ assert(1 && "Not Support gfx, never go here");
+ break;
}
}
@@ -1546,6 +1562,9 @@ static void amdgpu_draw_vs_RectPosTexFast_write2hw(struct shader_test_priv *test
case AMDGPU_TEST_GFX_V11:
amdgpu_draw_vs_RectPosTexFast_write2hw_gfx11(test_priv);
break;
+ case AMDGPU_TEST_GFX_MAX:
+ assert(1 && "Not Support gfx, never go here");
+ break;
}
}
@@ -1679,6 +1698,9 @@ static void amdgpu_draw_ps_write2hw(struct shader_test_priv *test_priv)
case AMDGPU_TEST_GFX_V11:
amdgpu_draw_ps_write2hw_gfx11(test_priv);
break;
+ case AMDGPU_TEST_GFX_MAX:
+ assert(1 && "Not Support gfx, never go here");
+ break;
}
}
@@ -1718,6 +1740,9 @@ static void amdgpu_draw_draw(struct shader_test_priv *test_priv)
ptr[i++] = 0x242;
ptr[i++] = 0x11;
break;
+ case AMDGPU_TEST_GFX_MAX:
+ assert(1 && "Not Support gfx, never go here");
+ break;
}
ptr[i++] = PACKET3(PACKET3_DRAW_INDEX_AUTO, 1);
@@ -2010,6 +2035,9 @@ static void amdgpu_memcpy_draw_test(struct shader_test_info *test_info)
ptr_cmd[i++] = 0x400;
i++;
break;
+ case AMDGPU_TEST_GFX_MAX:
+ assert(1 && "Not Support gfx, never go here");
+ break;
}
ptr_cmd[i++] = PACKET3(PACKET3_SET_SH_REG, 4);
diff --git a/tests/util/kms.c b/tests/util/kms.c
index 34a8418..8bbc227 100644
--- a/tests/util/kms.c
+++ b/tests/util/kms.c
@@ -126,6 +126,7 @@ static const char * const modules[] = {
"simpledrm",
"imx-lcdif",
"vkms",
+ "tidss",
};
int util_open(const char *device, const char *module)
diff --git a/xf86drm.c b/xf86drm.c
index 2e76f0e..1c87110 100644
--- a/xf86drm.c
+++ b/xf86drm.c
@@ -4471,14 +4471,24 @@ process_device(drmDevicePtr *device, const char *d_name,
{
struct stat sbuf;
char node[PATH_MAX + 1];
- int node_type, subsystem_type;
+ int node_type, subsystem_type, written;
unsigned int maj, min;
+ const int max_node_length = ALIGN(drmGetMaxNodeName(), sizeof(void *));
node_type = drmGetNodeType(d_name);
if (node_type < 0)
return -1;
- snprintf(node, PATH_MAX, "%s/%s", DRM_DIR_NAME, d_name);
+ written = snprintf(node, PATH_MAX, "%s/%s", DRM_DIR_NAME, d_name);
+ if (written < 0)
+ return -1;
+
+ /* anything longer than this will be truncated in drmDeviceAlloc.
+ * Account for NULL byte
+ */
+ if (written + 1 > max_node_length)
+ return -1;
+
if (stat(node, &sbuf))
return -1;
@@ -4585,6 +4595,7 @@ drm_public int drmGetDeviceFromDevId(dev_t find_rdev, uint32_t flags, drmDeviceP
const char *dev_name;
int node_type, subsystem_type;
int maj, min, n, ret;
+ const int max_node_length = ALIGN(drmGetMaxNodeName(), sizeof(void *));
if (device == NULL)
return -EINVAL;
@@ -4603,9 +4614,14 @@ drm_public int drmGetDeviceFromDevId(dev_t find_rdev, uint32_t flags, drmDeviceP
if (!dev_name)
return -EINVAL;
+ /* anything longer than this will be truncated in drmDeviceAlloc.
+ * Account for NULL byte
+ */
n = snprintf(node, PATH_MAX, dev_name, DRM_DIR_NAME, min);
if (n == -1 || n >= PATH_MAX)
return -errno;
+ if (written + 1 > max_node_length)
+ return -EINVAL
if (stat(node, &sbuf))
return -EINVAL;
diff --git a/xf86drm.h b/xf86drm.h
index 2cb1415..6d91dfb 100644
--- a/xf86drm.h
+++ b/xf86drm.h
@@ -926,6 +926,11 @@ extern int drmGetDeviceFromDevId(dev_t dev_id, uint32_t flags, drmDevicePtr *dev
*/
extern int drmGetNodeTypeFromDevId(dev_t devid);
+/**
+ * Check if two drmDevice pointers represent the same DRM device.
+ *
+ * Returns 1 if the devices are equal, 0 otherwise.
+ */
extern int drmDevicesEqual(drmDevicePtr a, drmDevicePtr b);
extern int drmSyncobjCreate(int fd, uint32_t flags, uint32_t *handle);
generated by cgit v1.2.3 (git 2.39.1) at 2024-11-29 09:32:37 +0000