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authorDaniel Baumann <daniel.baumann@progress-linux.org>2024-05-05 11:06:50 +0000
committerDaniel Baumann <daniel.baumann@progress-linux.org>2024-05-05 11:06:50 +0000
commitc662bc3e81d6cc7c9265ea9c58b8d1dbf66245ea (patch)
tree6a0ebdb4cb3c7b76c824f021d9f3624d16037457 /doc/man/nvme_cmbloc.2
parentAdding upstream version 1.8. (diff)
downloadlibnvme-upstream/1.9.tar.xz
libnvme-upstream/1.9.zip
Adding upstream version 1.9.upstream/1.9upstream
Signed-off-by: Daniel Baumann <daniel.baumann@progress-linux.org>
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+.TH "libnvme" 9 "enum nvme_cmbloc" "May 2024" "API Manual" LINUX
+.SH NAME
+enum nvme_cmbloc \- This field indicates the controller memory buffer location
+.SH SYNOPSIS
+enum nvme_cmbloc {
+.br
+.BI " NVME_CMBLOC_BIR_SHIFT"
+,
+.br
+.br
+.BI " NVME_CMBLOC_CQMMS_SHIFT"
+,
+.br
+.br
+.BI " NVME_CMBLOC_CQPDS_SHIFT"
+,
+.br
+.br
+.BI " NVME_CMBLOC_CDPLMS_SHIFT"
+,
+.br
+.br
+.BI " NVME_CMBLOC_CDPCILS_SHIFT"
+,
+.br
+.br
+.BI " NVME_CMBLOC_CDMMMS_SHIFT"
+,
+.br
+.br
+.BI " NVME_CMBLOC_CQDA_SHIFT"
+,
+.br
+.br
+.BI " NVME_CMBLOC_OFST_SHIFT"
+,
+.br
+.br
+.BI " NVME_CMBLOC_BIR_MASK"
+,
+.br
+.br
+.BI " NVME_CMBLOC_CQMMS_MASK"
+,
+.br
+.br
+.BI " NVME_CMBLOC_CQPDS_MASK"
+,
+.br
+.br
+.BI " NVME_CMBLOC_CDPLMS_MASK"
+,
+.br
+.br
+.BI " NVME_CMBLOC_CDPCILS_MASK"
+,
+.br
+.br
+.BI " NVME_CMBLOC_CDMMMS_MASK"
+,
+.br
+.br
+.BI " NVME_CMBLOC_CQDA_MASK"
+,
+.br
+.br
+.BI " NVME_CMBLOC_OFST_MASK"
+
+};
+.SH Constants
+.IP "NVME_CMBLOC_BIR_SHIFT" 12
+Shift amount to get the base indicator register
+.IP "NVME_CMBLOC_CQMMS_SHIFT" 12
+Shift amount to get the CMB queue mixed memory support
+.IP "NVME_CMBLOC_CQPDS_SHIFT" 12
+Shift amount to get the CMB queue physically discontiguous support
+.IP "NVME_CMBLOC_CDPLMS_SHIFT" 12
+Shift amount to get the CMB data pointer mixed locations support
+.IP "NVME_CMBLOC_CDPCILS_SHIFT" 12
+Shift amount to get the CMB data pointer and command independent locations support
+.IP "NVME_CMBLOC_CDMMMS_SHIFT" 12
+Shift amount to get the CMB data metadata mixed memory support
+.IP "NVME_CMBLOC_CQDA_SHIFT" 12
+Shift amount to get the CMB queue dword alignment
+.IP "NVME_CMBLOC_OFST_SHIFT" 12
+Shift amount to get the offset
+.IP "NVME_CMBLOC_BIR_MASK" 12
+Mask to get the base indicator register
+.IP "NVME_CMBLOC_CQMMS_MASK" 12
+Mask to get the CMB queue mixed memory support
+.IP "NVME_CMBLOC_CQPDS_MASK" 12
+Mask to get the CMB queue physically discontiguous support
+.IP "NVME_CMBLOC_CDPLMS_MASK" 12
+Mask to get the CMB data pointer mixed locations support
+.IP "NVME_CMBLOC_CDPCILS_MASK" 12
+Mask to get the CMB data pointer and command independent locations support
+.IP "NVME_CMBLOC_CDMMMS_MASK" 12
+Mask to get the CMB data metadata mixed memory support
+.IP "NVME_CMBLOC_CQDA_MASK" 12
+Mask to get the CMB queue dword alignment
+.IP "NVME_CMBLOC_OFST_MASK" 12
+Mask to get the offset