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| author | Daniel Baumann <daniel.baumann@progress-linux.org> | 2024-05-18 18:50:03 +0000 |
|---|---|---|
| committer | Daniel Baumann <daniel.baumann@progress-linux.org> | 2024-05-18 18:50:03 +0000 |
| commit | 01a69402cf9d38ff180345d55c2ee51c7e89fbc7 (patch) | |
| tree | b406c5242a088c4f59c6e4b719b783f43aca6ae9 /Documentation/devicetree/bindings/riscv/cpus.yaml | |
| parent | Adding upstream version 6.7.12. (diff) | |
| download | linux-01a69402cf9d38ff180345d55c2ee51c7e89fbc7.tar.xz linux-01a69402cf9d38ff180345d55c2ee51c7e89fbc7.zip | |
Adding upstream version 6.8.9.upstream/6.8.9
Signed-off-by: Daniel Baumann <daniel.baumann@progress-linux.org>
Diffstat (limited to 'Documentation/devicetree/bindings/riscv/cpus.yaml')
| -rw-r--r-- | Documentation/devicetree/bindings/riscv/cpus.yaml | 10 |
1 files changed, 8 insertions, 2 deletions
diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml index f392e367d6..9d8670c00e 100644 --- a/Documentation/devicetree/bindings/riscv/cpus.yaml +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml @@ -32,6 +32,7 @@ properties: oneOf: - items: - enum: + - amd,mbv32 - andestech,ax45mp - canaan,k210 - sifive,bullet0 @@ -62,8 +63,8 @@ properties: mmu-type: description: - Identifies the MMU address translation mode used on this - hart. These values originate from the RISC-V Privileged + Identifies the largest MMU address translation mode supported by + this hart. These values originate from the RISC-V Privileged Specification document, available from https://riscv.org/specifications/ $ref: /schemas/types.yaml#/definitions/string @@ -79,6 +80,11 @@ properties: description: The blocksize in bytes for the Zicbom cache operations. + riscv,cbop-block-size: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + The blocksize in bytes for the Zicbop cache operations. + riscv,cboz-block-size: $ref: /schemas/types.yaml#/definitions/uint32 description: |