diff options
author | Daniel Baumann <daniel.baumann@progress-linux.org> | 2024-04-11 08:27:49 +0000 |
---|---|---|
committer | Daniel Baumann <daniel.baumann@progress-linux.org> | 2024-04-11 08:27:49 +0000 |
commit | ace9429bb58fd418f0c81d4c2835699bddf6bde6 (patch) | |
tree | b2d64bc10158fdd5497876388cd68142ca374ed3 /Documentation/devicetree/bindings/soc/amlogic | |
parent | Initial commit. (diff) | |
download | linux-ace9429bb58fd418f0c81d4c2835699bddf6bde6.tar.xz linux-ace9429bb58fd418f0c81d4c2835699bddf6bde6.zip |
Adding upstream version 6.6.15.upstream/6.6.15
Signed-off-by: Daniel Baumann <daniel.baumann@progress-linux.org>
Diffstat (limited to 'Documentation/devicetree/bindings/soc/amlogic')
3 files changed, 250 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/soc/amlogic/amlogic,canvas.yaml b/Documentation/devicetree/bindings/soc/amlogic/amlogic,canvas.yaml new file mode 100644 index 0000000000..cd06865e1f --- /dev/null +++ b/Documentation/devicetree/bindings/soc/amlogic/amlogic,canvas.yaml @@ -0,0 +1,50 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +# Copyright 2019 BayLibre, SAS +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/soc/amlogic/amlogic,canvas.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Amlogic Canvas Video Lookup Table + +maintainers: + - Neil Armstrong <neil.armstrong@linaro.org> + - Maxime Jourdan <mjourdan@baylibre.com> + +description: | + A canvas is a collection of metadata that describes a pixel buffer. + Those metadata include: width, height, phyaddr, wrapping and block mode. + Starting with GXBB the endianness can also be described. + + Many IPs within Amlogic SoCs rely on canvas indexes to read/write pixel data + rather than use the phy addresses directly. For instance, this is the case for + the video decoders and the display. + + Amlogic SoCs have 256 canvas. + +properties: + compatible: + oneOf: + - items: + - enum: + - amlogic,meson8-canvas + - amlogic,meson8b-canvas + - amlogic,meson8m2-canvas + - const: amlogic,canvas + - const: amlogic,canvas # GXBB and newer SoCs + + reg: + maxItems: 1 + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + canvas: video-lut@48 { + compatible = "amlogic,canvas"; + reg = <0x48 0x14>; + }; diff --git a/Documentation/devicetree/bindings/soc/amlogic/amlogic,meson-gx-clk-measure.yaml b/Documentation/devicetree/bindings/soc/amlogic/amlogic,meson-gx-clk-measure.yaml new file mode 100644 index 0000000000..77c2811530 --- /dev/null +++ b/Documentation/devicetree/bindings/soc/amlogic/amlogic,meson-gx-clk-measure.yaml @@ -0,0 +1,40 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/soc/amlogic/amlogic,meson-gx-clk-measure.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Amlogic Internal Clock Measurer + +description: + The Amlogic SoCs contains an IP to measure the internal clocks. + The precision is multiple of MHz, useful to debug the clock states. + +maintainers: + - Neil Armstrong <neil.armstrong@linaro.org> + +properties: + compatible: + enum: + - amlogic,meson-gx-clk-measure + - amlogic,meson8-clk-measure + - amlogic,meson8b-clk-measure + - amlogic,meson-axg-clk-measure + - amlogic,meson-g12a-clk-measure + - amlogic,meson-sm1-clk-measure + + reg: + maxItems: 1 + +required: + - compatible + - reg + +unevaluatedProperties: false + +examples: + - | + clock-measure@8758 { + compatible = "amlogic,meson-gx-clk-measure"; + reg = <0x8758 0x10>; + }; diff --git a/Documentation/devicetree/bindings/soc/amlogic/amlogic,meson-gx-hhi-sysctrl.yaml b/Documentation/devicetree/bindings/soc/amlogic/amlogic,meson-gx-hhi-sysctrl.yaml new file mode 100644 index 0000000000..16977e4e43 --- /dev/null +++ b/Documentation/devicetree/bindings/soc/amlogic/amlogic,meson-gx-hhi-sysctrl.yaml @@ -0,0 +1,160 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/soc/amlogic/amlogic,meson-gx-hhi-sysctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Amlogic Meson System Control registers + +maintainers: + - Neil Armstrong <neil.armstrong@linaro.org> + +properties: + compatible: + items: + - enum: + - amlogic,meson-gx-hhi-sysctrl + - amlogic,meson-gx-ao-sysctrl + - amlogic,meson-axg-hhi-sysctrl + - amlogic,meson-axg-ao-sysctrl + - const: simple-mfd + - const: syscon + + reg: + maxItems: 1 + + clock-controller: + type: object + + power-controller: + $ref: /schemas/power/amlogic,meson-ee-pwrc.yaml + + pinctrl: + type: object + + phy: + type: object + +allOf: + - if: + properties: + compatible: + enum: + - amlogic,meson-gx-hhi-sysctrl + - amlogic,meson-axg-hhi-sysctrl + then: + properties: + clock-controller: + $ref: /schemas/clock/amlogic,gxbb-clkc.yaml# + + required: + - power-controller + + - if: + properties: + compatible: + enum: + - amlogic,meson-gx-ao-sysctrl + - amlogic,meson-axg-ao-sysctrl + then: + properties: + clock-controller: + $ref: /schemas/clock/amlogic,gxbb-aoclkc.yaml# + + power-controller: false + phy: false + + - if: + properties: + compatible: + enum: + - amlogic,meson-gx-hhi-sysctrl + then: + properties: + phy: false + + - if: + properties: + compatible: + enum: + - amlogic,meson-axg-hhi-sysctrl + then: + properties: + phy: + oneOf: + - $ref: /schemas/phy/amlogic,g12a-mipi-dphy-analog.yaml + - $ref: /schemas/phy/amlogic,meson-axg-mipi-pcie-analog.yaml + +required: + - compatible + - reg + - clock-controller + +additionalProperties: false + +examples: + - | + bus@c883c000 { + compatible = "simple-bus"; + reg = <0xc883c000 0x2000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xc883c000 0x2000>; + + sysctrl: system-controller@0 { + compatible = "amlogic,meson-gx-hhi-sysctrl", "simple-mfd", "syscon"; + reg = <0 0x400>; + + clock-controller { + compatible = "amlogic,gxbb-clkc"; + #clock-cells = <1>; + clocks = <&xtal>; + clock-names = "xtal"; + }; + + power-controller { + compatible = "amlogic,meson-gxbb-pwrc"; + #power-domain-cells = <1>; + amlogic,ao-sysctrl = <&sysctrl_AO>; + + resets = <&reset_viu>, + <&reset_venc>, + <&reset_vcbus>, + <&reset_bt656>, + <&reset_dvin>, + <&reset_rdma>, + <&reset_venci>, + <&reset_vencp>, + <&reset_vdac>, + <&reset_vdi6>, + <&reset_vencl>, + <&reset_vid_lock>; + reset-names = "viu", "venc", "vcbus", "bt656", "dvin", + "rdma", "venci", "vencp", "vdac", "vdi6", + "vencl", "vid_lock"; + clocks = <&clk_vpu>, <&clk_vapb>; + clock-names = "vpu", "vapb"; + }; + }; + }; + + bus@c8100000 { + compatible = "simple-bus"; + reg = <0xc8100000 0x100000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xc8100000 0x100000>; + + sysctrl_AO: system-controller@0 { + compatible = "amlogic,meson-gx-ao-sysctrl", "simple-mfd", "syscon"; + reg = <0 0x100>; + + clock-controller { + compatible = "amlogic,meson-gxbb-aoclkc", "amlogic,meson-gx-aoclkc"; + #clock-cells = <1>; + #reset-cells = <1>; + clocks = <&xtal>, <&clk81>; + clock-names = "xtal", "mpeg-clk"; + }; + }; + }; |