diff options
author | Daniel Baumann <daniel.baumann@progress-linux.org> | 2024-05-18 17:39:57 +0000 |
---|---|---|
committer | Daniel Baumann <daniel.baumann@progress-linux.org> | 2024-05-18 17:39:57 +0000 |
commit | dc50eab76b709d68175a358d6e23a5a3890764d3 (patch) | |
tree | c754d0390db060af0213ff994f0ac310e4cfd6e9 /arch/arm64/boot/dts/renesas | |
parent | Adding debian version 6.6.15-2. (diff) | |
download | linux-dc50eab76b709d68175a358d6e23a5a3890764d3.tar.xz linux-dc50eab76b709d68175a358d6e23a5a3890764d3.zip |
Merging upstream version 6.7.7.
Signed-off-by: Daniel Baumann <daniel.baumann@progress-linux.org>
Diffstat (limited to 'arch/arm64/boot/dts/renesas')
42 files changed, 1177 insertions, 268 deletions
diff --git a/arch/arm64/boot/dts/renesas/Makefile b/arch/arm64/boot/dts/renesas/Makefile index 7114cbbd87..8ea68d5827 100644 --- a/arch/arm64/boot/dts/renesas/Makefile +++ b/arch/arm64/boot/dts/renesas/Makefile @@ -29,21 +29,35 @@ dtb-$(CONFIG_ARCH_R8A774E1) += r8a774e1-hihope-rzg2h-ex-idk-1110wr.dtb dtb-$(CONFIG_ARCH_R8A774E1) += r8a774e1-hihope-rzg2h-ex-mipi-2.1.dtb dtb-$(CONFIG_ARCH_R8A77951) += r8a77951-salvator-x.dtb +r8a77951-salvator-x-panel-aa104xd12-dtbs := r8a77951-salvator-x.dtb salvator-panel-aa104xd12.dtbo +dtb-$(CONFIG_ARCH_R8A77951) += r8a77951-salvator-x-panel-aa104xd12.dtb dtb-$(CONFIG_ARCH_R8A77951) += r8a77951-salvator-xs.dtb +r8a77951-salvator-xs-panel-aa104xd12-dtbs := r8a77951-salvator-xs.dtb salvator-panel-aa104xd12.dtbo +dtb-$(CONFIG_ARCH_R8A77951) += r8a77951-salvator-xs-panel-aa104xd12.dtb dtb-$(CONFIG_ARCH_R8A77951) += r8a77951-ulcb.dtb dtb-$(CONFIG_ARCH_R8A77951) += r8a77951-ulcb-kf.dtb dtb-$(CONFIG_ARCH_R8A77960) += r8a77960-salvator-x.dtb +r8a77960-salvator-x-panel-aa104xd12-dtbs := r8a77960-salvator-x.dtb salvator-panel-aa104xd12.dtbo +dtb-$(CONFIG_ARCH_R8A77960) += r8a77960-salvator-x-panel-aa104xd12.dtb dtb-$(CONFIG_ARCH_R8A77960) += r8a77960-salvator-xs.dtb +r8a77960-salvator-xs-panel-aa104xd12-dtbs := r8a77960-salvator-xs.dtb salvator-panel-aa104xd12.dtbo +dtb-$(CONFIG_ARCH_R8A77960) += r8a77960-salvator-xs-panel-aa104xd12.dtb dtb-$(CONFIG_ARCH_R8A77960) += r8a77960-ulcb.dtb dtb-$(CONFIG_ARCH_R8A77960) += r8a77960-ulcb-kf.dtb dtb-$(CONFIG_ARCH_R8A77961) += r8a77961-salvator-xs.dtb +r8a77961-salvator-xs-panel-aa104xd12-dtbs := r8a77961-salvator-xs.dtb salvator-panel-aa104xd12.dtbo +dtb-$(CONFIG_ARCH_R8A77961) += r8a77961-salvator-xs-panel-aa104xd12.dtb dtb-$(CONFIG_ARCH_R8A77961) += r8a77961-ulcb.dtb dtb-$(CONFIG_ARCH_R8A77961) += r8a77961-ulcb-kf.dtb dtb-$(CONFIG_ARCH_R8A77965) += r8a77965-salvator-x.dtb +r8a77965-salvator-x-panel-aa104xd12-dtbs := r8a77965-salvator-x.dtb salvator-panel-aa104xd12.dtbo +dtb-$(CONFIG_ARCH_R8A77965) += r8a77965-salvator-x-panel-aa104xd12.dtb dtb-$(CONFIG_ARCH_R8A77965) += r8a77965-salvator-xs.dtb +r8a77965-salvator-xs-panel-aa104xd12-dtbs := r8a77965-salvator-xs.dtb salvator-panel-aa104xd12.dtbo +dtb-$(CONFIG_ARCH_R8A77965) += r8a77965-salvator-xs-panel-aa104xd12.dtb dtb-$(CONFIG_ARCH_R8A77965) += r8a77965-ulcb.dtb dtb-$(CONFIG_ARCH_R8A77965) += r8a77965-ulcb-kf.dtb @@ -55,36 +69,60 @@ dtb-$(CONFIG_ARCH_R8A77980) += r8a77980-v3hsk.dtb dtb-$(CONFIG_ARCH_R8A77980) += r8a77980a-condor-i.dtb dtb-$(CONFIG_ARCH_R8A77990) += r8a77990-ebisu.dtb +r8a77990-ebisu-panel-aa104xd12-dtbs := r8a77990-ebisu.dtb draak-ebisu-panel-aa104xd12.dtbo +dtb-$(CONFIG_ARCH_R8A77990) += r8a77990-ebisu-panel-aa104xd12.dtb dtb-$(CONFIG_ARCH_R8A77995) += r8a77995-draak.dtb +r8a77995-draak-panel-aa104xd12-dtbs := r8a77995-draak.dtb draak-ebisu-panel-aa104xd12.dtbo +dtb-$(CONFIG_ARCH_R8A77995) += r8a77995-draak-panel-aa104xd12.dtb dtb-$(CONFIG_ARCH_R8A779A0) += r8a779a0-falcon.dtb dtb-$(CONFIG_ARCH_R8A779F0) += r8a779f0-spider.dtb +dtb-$(CONFIG_ARCH_R8A779F0) += r8a779f4-s4sk.dtb dtb-$(CONFIG_ARCH_R8A779G0) += r8a779g0-white-hawk.dtb dtb-$(CONFIG_ARCH_R8A779G0) += r8a779g0-white-hawk-ard-audio-da7212.dtbo +r8a779g0-white-hawk-ard-audio-da7212-dtbs := r8a779g0-white-hawk.dtb r8a779g0-white-hawk-ard-audio-da7212.dtbo +dtb-$(CONFIG_ARCH_R8A779G0) += r8a779g0-white-hawk-ard-audio-da7212.dtb dtb-$(CONFIG_ARCH_R8A77951) += r8a779m1-salvator-xs.dtb +r8a779m1-salvator-xs-panel-aa104xd12-dtbs := r8a779m1-salvator-xs.dtb salvator-panel-aa104xd12.dtbo +dtb-$(CONFIG_ARCH_R8A77951) += r8a779m1-salvator-xs-panel-aa104xd12.dtb dtb-$(CONFIG_ARCH_R8A77951) += r8a779m1-ulcb.dtb dtb-$(CONFIG_ARCH_R8A77951) += r8a779m1-ulcb-kf.dtb dtb-$(CONFIG_ARCH_R8A77961) += r8a779m3-salvator-xs.dtb +r8a779m3-salvator-xs-panel-aa104xd12-dtbs := r8a779m3-salvator-xs.dtb salvator-panel-aa104xd12.dtbo +dtb-$(CONFIG_ARCH_R8A77961) += r8a779m3-salvator-xs-panel-aa104xd12.dtb dtb-$(CONFIG_ARCH_R8A77961) += r8a779m3-ulcb.dtb dtb-$(CONFIG_ARCH_R8A77961) += r8a779m3-ulcb-kf.dtb dtb-$(CONFIG_ARCH_R8A77965) += r8a779m5-salvator-xs.dtb +r8a779m5-salvator-xs-panel-aa104xd12-dtbs := r8a779m5-salvator-xs.dtb salvator-panel-aa104xd12.dtbo +dtb-$(CONFIG_ARCH_R8A77965) += r8a779m5-salvator-xs-panel-aa104xd12.dtb dtb-$(CONFIG_ARCH_R9A07G043) += r9a07g043u11-smarc.dtb dtb-$(CONFIG_ARCH_R9A07G043) += r9a07g043-smarc-pmod.dtbo +r9a07g043u11-smarc-pmod-dtbs := r9a07g043u11-smarc.dtb r9a07g043-smarc-pmod.dtbo +dtb-$(CONFIG_ARCH_R9A07G043) += r9a07g043u11-smarc-pmod.dtb dtb-$(CONFIG_ARCH_R9A07G044) += r9a07g044c2-smarc.dtb dtb-$(CONFIG_ARCH_R9A07G044) += r9a07g044c2-smarc-cru-csi-ov5645.dtbo +r9a07g044c2-smarc-cru-csi-ov5645-dtbs := r9a07g044c2-smarc.dtb r9a07g044c2-smarc-cru-csi-ov5645.dtbo +dtb-$(CONFIG_ARCH_R9A07G044) += r9a07g044c2-smarc-cru-csi-ov5645.dtb + dtb-$(CONFIG_ARCH_R9A07G044) += r9a07g044l2-smarc.dtb dtb-$(CONFIG_ARCH_R9A07G044) += r9a07g044l2-smarc-cru-csi-ov5645.dtbo +r9a07g044l2-smarc-cru-csi-ov5645-dtbs := r9a07g044l2-smarc.dtb r9a07g044l2-smarc-cru-csi-ov5645.dtbo +dtb-$(CONFIG_ARCH_R9A07G044) += r9a07g044l2-smarc-cru-csi-ov5645.dtb dtb-$(CONFIG_ARCH_R9A07G054) += r9a07g054l2-smarc.dtb dtb-$(CONFIG_ARCH_R9A07G054) += r9a07g054l2-smarc-cru-csi-ov5645.dtbo +r9a07g054l2-smarc-cru-csi-ov5645-dtbs := r9a07g054l2-smarc.dtb r9a07g054l2-smarc-cru-csi-ov5645.dtbo +dtb-$(CONFIG_ARCH_R9A07G054) += r9a07g054l2-smarc-cru-csi-ov5645.dtb + +dtb-$(CONFIG_ARCH_R9A08G045) += r9a08g045s33-smarc.dtb dtb-$(CONFIG_ARCH_R9A09G011) += r9a09g011-v2mevk2.dtb diff --git a/arch/arm64/boot/dts/renesas/beacon-renesom-baseboard.dtsi b/arch/arm64/boot/dts/renesas/beacon-renesom-baseboard.dtsi index 2e9927b977..5a14f116f7 100644 --- a/arch/arm64/boot/dts/renesas/beacon-renesom-baseboard.dtsi +++ b/arch/arm64/boot/dts/renesas/beacon-renesom-baseboard.dtsi @@ -651,7 +651,7 @@ <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>, <&versaclock6_bb 4>, <&audio_clk_b>, <&audio_clk_c>, - <&cpg CPG_CORE CPG_AUDIO_CLK_I>; + <&cpg CPG_MOD 922>; status = "okay"; diff --git a/arch/arm64/boot/dts/renesas/ebisu.dtsi b/arch/arm64/boot/dts/renesas/ebisu.dtsi index bbc29452d1..f1a5778ef1 100644 --- a/arch/arm64/boot/dts/renesas/ebisu.dtsi +++ b/arch/arm64/boot/dts/renesas/ebisu.dtsi @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0 /* - * Device Tree Source for the Ebisu board + * Device Tree Source for the Ebisu/Ebisu-4D board * * Copyright (C) 2018 Renesas Electronics Corp. */ diff --git a/arch/arm64/boot/dts/renesas/hihope-rev4.dtsi b/arch/arm64/boot/dts/renesas/hihope-rev4.dtsi index 7fc0339a3a..66f3affe04 100644 --- a/arch/arm64/boot/dts/renesas/hihope-rev4.dtsi +++ b/arch/arm64/boot/dts/renesas/hihope-rev4.dtsi @@ -112,7 +112,7 @@ <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>, <&audio_clk_a>, <&cs2000>, <&audio_clk_c>, - <&cpg CPG_CORE CPG_AUDIO_CLK_I>; + <&cpg CPG_MOD 922>; rsnd_port: port { rsnd_endpoint: endpoint { diff --git a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi index 9065dc2434..95b0a1f6de 100644 --- a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi @@ -10,8 +10,6 @@ #include <dt-bindings/clock/r8a774a1-cpg-mssr.h> #include <dt-bindings/power/r8a774a1-sysc.h> -#define CPG_AUDIO_CLK_I R8A774A1_CLK_S0D4 - / { compatible = "renesas,r8a774a1"; #address-cells = <2>; @@ -1713,7 +1711,7 @@ <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>, <&audio_clk_a>, <&audio_clk_b>, <&audio_clk_c>, - <&cpg CPG_CORE R8A774A1_CLK_S0D4>; + <&cpg CPG_MOD 922>; clock-names = "ssi-all", "ssi.9", "ssi.8", "ssi.7", "ssi.6", "ssi.5", "ssi.4", "ssi.3", "ssi.2", diff --git a/arch/arm64/boot/dts/renesas/r8a774b1.dtsi b/arch/arm64/boot/dts/renesas/r8a774b1.dtsi index 75776decd2..786660fcde 100644 --- a/arch/arm64/boot/dts/renesas/r8a774b1.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a774b1.dtsi @@ -10,8 +10,6 @@ #include <dt-bindings/clock/r8a774b1-cpg-mssr.h> #include <dt-bindings/power/r8a774b1-sysc.h> -#define CPG_AUDIO_CLK_I R8A774B1_CLK_S0D4 - / { compatible = "renesas,r8a774b1"; #address-cells = <2>; @@ -1597,7 +1595,7 @@ <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>, <&audio_clk_a>, <&audio_clk_b>, <&audio_clk_c>, - <&cpg CPG_CORE R8A774B1_CLK_S0D4>; + <&cpg CPG_MOD 922>; clock-names = "ssi-all", "ssi.9", "ssi.8", "ssi.7", "ssi.6", "ssi.5", "ssi.4", "ssi.3", "ssi.2", diff --git a/arch/arm64/boot/dts/renesas/r8a774c0.dtsi b/arch/arm64/boot/dts/renesas/r8a774c0.dtsi index ad2e87b039..eed94ffed7 100644 --- a/arch/arm64/boot/dts/renesas/r8a774c0.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a774c0.dtsi @@ -1350,7 +1350,7 @@ <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>, <&audio_clk_a>, <&audio_clk_b>, <&audio_clk_c>, - <&cpg CPG_CORE R8A774C0_CLK_ZA2>; + <&cpg CPG_MOD 922>; clock-names = "ssi-all", "ssi.9", "ssi.8", "ssi.7", "ssi.6", "ssi.5", "ssi.4", "ssi.3", "ssi.2", diff --git a/arch/arm64/boot/dts/renesas/r8a774e1.dtsi b/arch/arm64/boot/dts/renesas/r8a774e1.dtsi index 2acf4067ab..175e5d296d 100644 --- a/arch/arm64/boot/dts/renesas/r8a774e1.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a774e1.dtsi @@ -10,8 +10,6 @@ #include <dt-bindings/clock/r8a774e1-cpg-mssr.h> #include <dt-bindings/power/r8a774e1-sysc.h> -#define CPG_AUDIO_CLK_I R8A774E1_CLK_S0D4 - / { compatible = "renesas,r8a774e1"; #address-cells = <2>; @@ -1809,7 +1807,7 @@ <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>, <&audio_clk_a>, <&audio_clk_b>, <&audio_clk_c>, - <&cpg CPG_CORE R8A774E1_CLK_S0D4>; + <&cpg CPG_MOD 922>; clock-names = "ssi-all", "ssi.9", "ssi.8", "ssi.7", "ssi.6", "ssi.5", "ssi.4", "ssi.3", "ssi.2", diff --git a/arch/arm64/boot/dts/renesas/r8a77951.dtsi b/arch/arm64/boot/dts/renesas/r8a77951.dtsi index 6d15229d25..a4260d9291 100644 --- a/arch/arm64/boot/dts/renesas/r8a77951.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77951.dtsi @@ -9,8 +9,6 @@ #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/power/r8a7795-sysc.h> -#define CPG_AUDIO_CLK_I R8A7795_CLK_S0D4 - #define SOC_HAS_HDMI1 #define SOC_HAS_SATA #define SOC_HAS_USB2_CH2 @@ -2032,7 +2030,7 @@ <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>, <&audio_clk_a>, <&audio_clk_b>, <&audio_clk_c>, - <&cpg CPG_CORE R8A7795_CLK_S0D4>; + <&cpg CPG_MOD 922>; clock-names = "ssi-all", "ssi.9", "ssi.8", "ssi.7", "ssi.6", "ssi.5", "ssi.4", "ssi.3", "ssi.2", diff --git a/arch/arm64/boot/dts/renesas/r8a77960.dtsi b/arch/arm64/boot/dts/renesas/r8a77960.dtsi index 17062ec506..a631ead171 100644 --- a/arch/arm64/boot/dts/renesas/r8a77960.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77960.dtsi @@ -9,8 +9,6 @@ #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/power/r8a7796-sysc.h> -#define CPG_AUDIO_CLK_I R8A7796_CLK_S0D4 - / { compatible = "renesas,r8a7796"; #address-cells = <2>; @@ -1903,7 +1901,7 @@ <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>, <&audio_clk_a>, <&audio_clk_b>, <&audio_clk_c>, - <&cpg CPG_CORE R8A7796_CLK_S0D4>; + <&cpg CPG_MOD 922>; clock-names = "ssi-all", "ssi.9", "ssi.8", "ssi.7", "ssi.6", "ssi.5", "ssi.4", "ssi.3", "ssi.2", diff --git a/arch/arm64/boot/dts/renesas/r8a77961.dtsi b/arch/arm64/boot/dts/renesas/r8a77961.dtsi index d3f47da1b6..7254912a24 100644 --- a/arch/arm64/boot/dts/renesas/r8a77961.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77961.dtsi @@ -9,8 +9,6 @@ #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/power/r8a77961-sysc.h> -#define CPG_AUDIO_CLK_I R8A77961_CLK_S0D4 - / { compatible = "renesas,r8a77961"; #address-cells = <2>; @@ -1783,7 +1781,7 @@ <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>, <&audio_clk_a>, <&audio_clk_b>, <&audio_clk_c>, - <&cpg CPG_CORE R8A77961_CLK_S0D4>; + <&cpg CPG_MOD 922>; clock-names = "ssi-all", "ssi.9", "ssi.8", "ssi.7", "ssi.6", "ssi.5", "ssi.4", "ssi.3", "ssi.2", diff --git a/arch/arm64/boot/dts/renesas/r8a77965.dtsi b/arch/arm64/boot/dts/renesas/r8a77965.dtsi index c758200384..e57b902706 100644 --- a/arch/arm64/boot/dts/renesas/r8a77965.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77965.dtsi @@ -12,8 +12,6 @@ #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/power/r8a77965-sysc.h> -#define CPG_AUDIO_CLK_I R8A77965_CLK_S0D4 - #define SOC_HAS_SATA / { @@ -1766,7 +1764,7 @@ <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>, <&audio_clk_a>, <&audio_clk_b>, <&audio_clk_c>, - <&cpg CPG_CORE R8A77965_CLK_S0D4>; + <&cpg CPG_MOD 922>; clock-names = "ssi-all", "ssi.9", "ssi.8", "ssi.7", "ssi.6", "ssi.5", "ssi.4", "ssi.3", "ssi.2", diff --git a/arch/arm64/boot/dts/renesas/r8a77990-ebisu.dts b/arch/arm64/boot/dts/renesas/r8a77990-ebisu.dts index 9da0fd08f8..d5ac34a966 100644 --- a/arch/arm64/boot/dts/renesas/r8a77990-ebisu.dts +++ b/arch/arm64/boot/dts/renesas/r8a77990-ebisu.dts @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0 /* - * Device Tree Source for the Ebisu board with R-Car E3 + * Device Tree Source for the Ebisu/Ebisu-4D board with R-Car E3 * * Copyright (C) 2018 Renesas Electronics Corp. */ diff --git a/arch/arm64/boot/dts/renesas/r8a77990.dtsi b/arch/arm64/boot/dts/renesas/r8a77990.dtsi index 4c545eff9b..8c2b283423 100644 --- a/arch/arm64/boot/dts/renesas/r8a77990.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77990.dtsi @@ -1501,7 +1501,7 @@ <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>, <&audio_clk_a>, <&audio_clk_b>, <&audio_clk_c>, - <&cpg CPG_CORE R8A77990_CLK_ZA2>; + <&cpg CPG_MOD 922>; clock-names = "ssi-all", "ssi.9", "ssi.8", "ssi.7", "ssi.6", "ssi.5", "ssi.4", "ssi.3", "ssi.2", diff --git a/arch/arm64/boot/dts/renesas/r8a77995.dtsi b/arch/arm64/boot/dts/renesas/r8a77995.dtsi index e25024a7b6..8cf6473c63 100644 --- a/arch/arm64/boot/dts/renesas/r8a77995.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77995.dtsi @@ -1063,7 +1063,7 @@ <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>, <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>, <&audio_clk_a>, <&audio_clk_b>, - <&cpg CPG_CORE R8A77995_CLK_ZA2>; + <&cpg CPG_MOD 922>; clock-names = "ssi-all", "ssi.4", "ssi.3", "src.6", "src.5", diff --git a/arch/arm64/boot/dts/renesas/r8a779f0-spider-cpu.dtsi b/arch/arm64/boot/dts/renesas/r8a779f0-spider-cpu.dtsi index 5cbde8e8fc..477f3114d2 100644 --- a/arch/arm64/boot/dts/renesas/r8a779f0-spider-cpu.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a779f0-spider-cpu.dtsi @@ -53,6 +53,12 @@ reg = <0x4 0x80000000 0x0 0x80000000>; }; + rc21012_pci: clk-rc21012-pci { + compatible = "fixed-clock"; + clock-frequency = <100000000>; + #clock-cells = <0>; + }; + rc21012_ufs: clk-rc21012-ufs { compatible = "fixed-clock"; clock-frequency = <38400000>; @@ -106,6 +112,12 @@ reg = <0x20>; gpio-controller; #gpio-cells = <2>; + + rc21012-gpio2-hog { + gpio-hog; + gpios = <5 GPIO_ACTIVE_LOW>; + output-high; + }; }; }; @@ -145,6 +157,18 @@ status = "okay"; }; +&pcie0_clkref { + compatible = "gpio-gate-clock"; + clocks = <&rc21012_pci>; + enable-gpios = <&gpio2 15 GPIO_ACTIVE_LOW>; + /delete-property/ clock-frequency; +}; + +&pciec0 { + reset-gpio = <&gpio_exp_20 0 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + &pfc { pinctrl-0 = <&scif_clk_pins>; pinctrl-names = "default"; diff --git a/arch/arm64/boot/dts/renesas/r8a779f0.dtsi b/arch/arm64/boot/dts/renesas/r8a779f0.dtsi index ecdd5a523f..7fb4989cce 100644 --- a/arch/arm64/boot/dts/renesas/r8a779f0.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a779f0.dtsi @@ -262,6 +262,20 @@ clock-frequency = <0>; }; + pcie0_clkref: pcie0-clkref { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by the board */ + clock-frequency = <0>; + }; + + pcie1_clkref: pcie1-clkref { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by the board */ + clock-frequency = <0>; + }; + pmu_a55 { compatible = "arm,cortex-a55-pmu"; interrupts-extended = <&gic GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; @@ -726,6 +740,126 @@ status = "disabled"; }; + pciec0: pcie@e65d0000 { + compatible = "renesas,r8a779f0-pcie", + "renesas,rcar-gen4-pcie"; + reg = <0 0xe65d0000 0 0x1000>, <0 0xe65d2000 0 0x0800>, + <0 0xe65d3000 0 0x2000>, <0 0xe65d5000 0 0x1200>, + <0 0xe65d6200 0 0x0e00>, <0 0xe65d7000 0 0x0400>, + <0 0xfe000000 0 0x400000>; + reg-names = "dbi", "dbi2", "atu", "dma", "app", "phy", "config"; + interrupts = <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "msi", "dma", "sft_ce", "app"; + clocks = <&cpg CPG_MOD 624>, <&pcie0_clkref>; + clock-names = "core", "ref"; + power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; + resets = <&cpg 624>; + reset-names = "pwr"; + max-link-speed = <4>; + num-lanes = <2>; + #address-cells = <3>; + #size-cells = <2>; + bus-range = <0x00 0xff>; + device_type = "pci"; + ranges = <0x01000000 0 0x00000000 0 0xfe000000 0 0x00400000>, + <0x02000000 0 0x30000000 0 0x30000000 0 0x10000000>; + dma-ranges = <0x42000000 0 0x00000000 0 0x00000000 1 0x00000000>; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &gic GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 2 &gic GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 3 &gic GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 4 &gic GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>; + snps,enable-cdm-check; + status = "disabled"; + }; + + pciec1: pcie@e65d8000 { + compatible = "renesas,r8a779f0-pcie", + "renesas,rcar-gen4-pcie"; + reg = <0 0xe65d8000 0 0x1000>, <0 0xe65da000 0 0x0800>, + <0 0xe65db000 0 0x2000>, <0 0xe65dd000 0 0x1200>, + <0 0xe65de200 0 0x0e00>, <0 0xe65df000 0 0x0400>, + <0 0xee900000 0 0x400000>; + reg-names = "dbi", "dbi2", "atu", "dma", "app", "phy", "config"; + interrupts = <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "msi", "dma", "sft_ce", "app"; + clocks = <&cpg CPG_MOD 625>, <&pcie1_clkref>; + clock-names = "core", "ref"; + power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; + resets = <&cpg 625>; + reset-names = "pwr"; + max-link-speed = <4>; + num-lanes = <2>; + #address-cells = <3>; + #size-cells = <2>; + bus-range = <0x00 0xff>; + device_type = "pci"; + ranges = <0x01000000 0 0x00000000 0 0xee900000 0 0x00400000>, + <0x02000000 0 0xc0000000 0 0xc0000000 0 0x10000000>; + dma-ranges = <0x42000000 0 0x00000000 0 0x00000000 1 0x00000000>; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &gic GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 2 &gic GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 3 &gic GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 4 &gic GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>; + snps,enable-cdm-check; + status = "disabled"; + }; + + pciec0_ep: pcie-ep@e65d0000 { + compatible = "renesas,r8a779f0-pcie-ep", + "renesas,rcar-gen4-pcie-ep"; + reg = <0 0xe65d0000 0 0x2000>, <0 0xe65d2000 0 0x1000>, + <0 0xe65d3000 0 0x2000>, <0 0xe65d5000 0 0x1200>, + <0 0xe65d6200 0 0x0e00>, <0 0xe65d7000 0 0x0400>, + <0 0xfe000000 0 0x400000>; + reg-names = "dbi", "dbi2", "atu", "dma", "app", "phy", "addr_space"; + interrupts = <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "dma", "sft_ce", "app"; + clocks = <&cpg CPG_MOD 624>, <&pcie0_clkref>; + clock-names = "core", "ref"; + power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; + resets = <&cpg 624>; + reset-names = "pwr"; + max-link-speed = <4>; + num-lanes = <2>; + max-functions = /bits/ 8 <2>; + status = "disabled"; + }; + + pciec1_ep: pcie-ep@e65d8000 { + compatible = "renesas,r8a779f0-pcie-ep", + "renesas,rcar-gen4-pcie-ep"; + reg = <0 0xe65d8000 0 0x2000>, <0 0xe65da000 0 0x1000>, + <0 0xe65db000 0 0x2000>, <0 0xe65dd000 0 0x1200>, + <0 0xe65de200 0 0x0e00>, <0 0xe65df000 0 0x0400>, + <0 0xee900000 0 0x400000>; + reg-names = "dbi", "dbi2", "atu", "dma", "app", "phy", "addr_space"; + interrupts = <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "dma", "sft_ce", "app"; + clocks = <&cpg CPG_MOD 625>, <&pcie1_clkref>; + clock-names = "core", "ref"; + power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; + resets = <&cpg 625>; + reset-names = "pwr"; + max-link-speed = <4>; + num-lanes = <2>; + max-functions = /bits/ 8 <2>; + status = "disabled"; + }; + ufs: ufs@e6860000 { compatible = "renesas,r8a779f0-ufs"; reg = <0 0xe6860000 0 0x100>; diff --git a/arch/arm64/boot/dts/renesas/r8a779f4-s4sk.dts b/arch/arm64/boot/dts/renesas/r8a779f4-s4sk.dts new file mode 100644 index 0000000000..abfda5c6ca --- /dev/null +++ b/arch/arm64/boot/dts/renesas/r8a779f4-s4sk.dts @@ -0,0 +1,240 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Device Tree Source for the R-Car S4 Starter Kit board + * + * Copyright (C) 2023 Renesas Electronics Corp. + */ + +/dts-v1/; +#include <dt-bindings/gpio/gpio.h> +#include "r8a779f4.dtsi" + +/ { + model = "R-Car S4 Starter Kit board"; + compatible = "renesas,s4sk", "renesas,r8a779f4", "renesas,r8a779f0"; + + aliases { + serial0 = &hscif0; + serial1 = &hscif1; + eth0 = &rswitch; + }; + + chosen { + bootargs = "ignore_loglevel rw root=/dev/nfs ip=on"; + stdout-path = "serial0:921600n8"; + }; + + memory@48000000 { + device_type = "memory"; + /* first 128MB is reserved for secure area. */ + /* The last 512MB is reserved for CR. */ + reg = <0x0 0x48000000 0x0 0x58000000>; + }; + + memory@480000000 { + device_type = "memory"; + reg = <0x4 0x80000000 0x0 0x80000000>; + }; + + vcc_sdhi: regulator-vcc-sdhi { + compatible = "regulator-fixed"; + regulator-name = "SDHI Vcc"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio1 24 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; +}; + +ð_serdes { + status = "okay"; +}; + +&extal_clk { + clock-frequency = <20000000>; +}; + +&extalr_clk { + clock-frequency = <32768>; +}; + +&hscif0 { + pinctrl-0 = <&hscif0_pins>; + pinctrl-names = "default"; + + uart-has-rtscts; + status = "okay"; +}; + +&hscif1 { + pinctrl-0 = <&hscif1_pins>; + pinctrl-names = "default"; + + uart-has-rtscts; + status = "okay"; +}; + +&i2c2 { + pinctrl-0 = <&i2c2_pins>; + pinctrl-names = "default"; + + status = "okay"; + clock-frequency = <400000>; +}; + +&i2c4 { + pinctrl-0 = <&i2c4_pins>; + pinctrl-names = "default"; + + status = "okay"; + clock-frequency = <400000>; +}; + +&i2c5 { + pinctrl-0 = <&i2c5_pins>; + pinctrl-names = "default"; + + status = "okay"; + clock-frequency = <400000>; + + eeprom@50 { + compatible = "st,24c16", "atmel,24c16"; + reg = <0x50>; + pagesize = <16>; + }; +}; + +&mmc0 { + pinctrl-0 = <&sd_pins>; + pinctrl-names = "default"; + + vmmc-supply = <&vcc_sdhi>; + cd-gpios = <&gpio1 23 GPIO_ACTIVE_LOW>; + bus-width = <4>; + status = "okay"; +}; + +&pfc { + pinctrl-0 = <&scif_clk_pins>; + pinctrl-names = "default"; + + hscif0_pins: hscif0 { + groups = "hscif0_data", "hscif0_ctrl"; + function = "hscif0"; + }; + + hscif1_pins: hscif1 { + groups = "hscif1_data", "hscif1_ctrl"; + function = "hscif1"; + }; + + i2c2_pins: i2c2 { + groups = "i2c2"; + function = "i2c2"; + }; + + i2c4_pins: i2c4 { + groups = "i2c4"; + function = "i2c4"; + }; + + i2c5_pins: i2c5 { + groups = "i2c5"; + function = "i2c5"; + }; + + scif_clk_pins: scif_clk { + groups = "scif_clk"; + function = "scif_clk"; + }; + + sd_pins: sd { + groups = "mmc_data4", "mmc_ctrl"; + function = "mmc"; + power-source = <3300>; + }; + + tsn0_pins: tsn0 { + groups = "tsn0_mdio_b", "tsn0_link_b"; + function = "tsn0"; + drive-strength = <18>; + power-source = <3300>; + }; + + tsn1_pins: tsn1 { + groups = "tsn1_mdio_b", "tsn1_link_b"; + function = "tsn1"; + drive-strength = <18>; + power-source = <3300>; + }; +}; + +&rswitch { + pinctrl-0 = <&tsn0_pins>, <&tsn1_pins>; + pinctrl-names = "default"; + status = "okay"; + + ethernet-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + phy-handle = <&ic99>; + phy-mode = "sgmii"; + phys = <ð_serdes 0>; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ic99: ethernet-phy@1 { + reg = <1>; + compatible = "ethernet-phy-ieee802.3-c45"; + interrupt-parent = <&gpio3>; + interrupts = <10 IRQ_TYPE_LEVEL_LOW>; + }; + }; + }; + + port@1 { + reg = <1>; + phy-handle = <&ic102>; + phy-mode = "sgmii"; + phys = <ð_serdes 1>; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ic102: ethernet-phy@2 { + reg = <2>; + compatible = "ethernet-phy-ieee802.3-c45"; + interrupt-parent = <&gpio3>; + interrupts = <11 IRQ_TYPE_LEVEL_LOW>; + }; + }; + }; + + port@2 { + status = "disabled"; + }; + }; +}; + +&rwdt { + timeout-sec = <60>; + status = "okay"; +}; + +&scif_clk { + clock-frequency = <24000000>; +}; + +&ufs { + status = "okay"; +}; + +&ufs30_clk { + clock-frequency = <38400000>; +}; diff --git a/arch/arm64/boot/dts/renesas/r8a779f4.dtsi b/arch/arm64/boot/dts/renesas/r8a779f4.dtsi new file mode 100644 index 0000000000..ebed41892d --- /dev/null +++ b/arch/arm64/boot/dts/renesas/r8a779f4.dtsi @@ -0,0 +1,12 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Device Tree Source for the R-Car S4-8 (R8A779F4) SoC + * + * Copyright (C) 2023 Renesas Electronics Corp. + */ + +#include "r8a779f0.dtsi" + +/ { + compatible = "renesas,r8a779f4", "renesas,r8a779f0"; +}; diff --git a/arch/arm64/boot/dts/renesas/r9a08g045.dtsi b/arch/arm64/boot/dts/renesas/r9a08g045.dtsi new file mode 100644 index 0000000000..6c7b29b69d --- /dev/null +++ b/arch/arm64/boot/dts/renesas/r9a08g045.dtsi @@ -0,0 +1,170 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* + * Device Tree Source for the RZ/G3S SoC + * + * Copyright (C) 2023 Renesas Electronics Corp. + */ + +#include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/clock/r9a08g045-cpg.h> + +/ { + compatible = "renesas,r9a08g045"; + #address-cells = <2>; + #size-cells = <2>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + compatible = "arm,cortex-a55"; + reg = <0>; + device_type = "cpu"; + #cooling-cells = <2>; + next-level-cache = <&L3_CA55>; + enable-method = "psci"; + clocks = <&cpg CPG_CORE R9A08G045_CLK_I>; + }; + + L3_CA55: cache-controller-0 { + compatible = "cache"; + cache-level = <3>; + cache-unified; + cache-size = <0x40000>; + }; + }; + + extal_clk: extal-clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by the board. */ + clock-frequency = <0>; + }; + + soc: soc { + compatible = "simple-bus"; + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + scif0: serial@1004b800 { + compatible = "renesas,scif-r9a08g045", "renesas,scif-r9a07g044"; + reg = <0 0x1004b800 0 0x400>; + interrupts = <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "eri", "rxi", "txi", + "bri", "dri", "tei"; + clocks = <&cpg CPG_MOD R9A08G045_SCIF0_CLK_PCK>; + clock-names = "fck"; + power-domains = <&cpg>; + resets = <&cpg R9A08G045_SCIF0_RST_SYSTEM_N>; + status = "disabled"; + }; + + cpg: clock-controller@11010000 { + compatible = "renesas,r9a08g045-cpg"; + reg = <0 0x11010000 0 0x10000>; + clocks = <&extal_clk>; + clock-names = "extal"; + #clock-cells = <2>; + #reset-cells = <1>; + #power-domain-cells = <0>; + }; + + sysc: system-controller@11020000 { + compatible = "renesas,r9a08g045-sysc"; + reg = <0 0x11020000 0 0x10000>; + interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "lpm_int", "ca55stbydone_int", + "cm33stbyr_int", "ca55_deny"; + status = "disabled"; + }; + + pinctrl: pinctrl@11030000 { + compatible = "renesas,r9a08g045-pinctrl"; + reg = <0 0x11030000 0 0x10000>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + gpio-ranges = <&pinctrl 0 0 152>; + clocks = <&cpg CPG_MOD R9A08G045_GPIO_HCLK>; + power-domains = <&cpg>; + resets = <&cpg R9A08G045_GPIO_RSTN>, + <&cpg R9A08G045_GPIO_PORT_RESETN>, + <&cpg R9A08G045_GPIO_SPARE_RESETN>; + }; + + sdhi0: mmc@11c00000 { + compatible = "renesas,sdhi-r9a08g045", "renesas,rcar-gen3-sdhi"; + reg = <0x0 0x11c00000 0 0x10000>; + interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD R9A08G045_SDHI0_IMCLK>, + <&cpg CPG_MOD R9A08G045_SDHI0_CLK_HS>, + <&cpg CPG_MOD R9A08G045_SDHI0_IMCLK2>, + <&cpg CPG_MOD R9A08G045_SDHI0_ACLK>; + clock-names = "core", "clkh", "cd", "aclk"; + resets = <&cpg R9A08G045_SDHI0_IXRST>; + power-domains = <&cpg>; + status = "disabled"; + }; + + sdhi1: mmc@11c10000 { + compatible = "renesas,sdhi-r9a08g045", "renesas,rcar-gen3-sdhi"; + reg = <0x0 0x11c10000 0 0x10000>; + interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD R9A08G045_SDHI1_IMCLK>, + <&cpg CPG_MOD R9A08G045_SDHI1_CLK_HS>, + <&cpg CPG_MOD R9A08G045_SDHI1_IMCLK2>, + <&cpg CPG_MOD R9A08G045_SDHI1_ACLK>; + clock-names = "core", "clkh", "cd", "aclk"; + resets = <&cpg R9A08G045_SDHI1_IXRST>; + power-domains = <&cpg>; + status = "disabled"; + }; + + sdhi2: mmc@11c20000 { + compatible = "renesas,sdhi-r9a08g045", "renesas,rcar-gen3-sdhi"; + reg = <0x0 0x11c20000 0 0x10000>; + interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD R9A08G045_SDHI2_IMCLK>, + <&cpg CPG_MOD R9A08G045_SDHI2_CLK_HS>, + <&cpg CPG_MOD R9A08G045_SDHI2_IMCLK2>, + <&cpg CPG_MOD R9A08G045_SDHI2_ACLK>; + clock-names = "core", "clkh", "cd", "aclk"; + resets = <&cpg R9A08G045_SDHI2_IXRST>; + power-domains = <&cpg>; + status = "disabled"; + }; + + gic: interrupt-controller@12400000 { + compatible = "arm,gic-v3"; + #interrupt-cells = <3>; + #address-cells = <0>; + interrupt-controller; + reg = <0x0 0x12400000 0 0x40000>, + <0x0 0x12440000 0 0x60000>; + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>; + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts-extended = <&gic GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, + <&gic GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, + <&gic GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, + <&gic GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; + }; +}; diff --git a/arch/arm64/boot/dts/renesas/r9a08g045s33-smarc.dts b/arch/arm64/boot/dts/renesas/r9a08g045s33-smarc.dts new file mode 100644 index 0000000000..6b57e0e02d --- /dev/null +++ b/arch/arm64/boot/dts/renesas/r9a08g045s33-smarc.dts @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* + * Device Tree Source for the RZ/G3S SMARC EVK board + * + * Copyright (C) 2023 Renesas Electronics Corp. + */ + +/dts-v1/; + +#include "r9a08g045s33.dtsi" +#include "rzg3s-smarc-som.dtsi" +#include "rzg3s-smarc.dtsi" + +/ { + model = "Renesas SMARC EVK version 2 based on r9a08g045s33"; + compatible = "renesas,smarc2-evk", "renesas,rzg3s-smarcm", + "renesas,r9a08g045s33", "renesas,r9a08g045"; +}; diff --git a/arch/arm64/boot/dts/renesas/r9a08g045s33.dtsi b/arch/arm64/boot/dts/renesas/r9a08g045s33.dtsi new file mode 100644 index 0000000000..3351f26c7a --- /dev/null +++ b/arch/arm64/boot/dts/renesas/r9a08g045s33.dtsi @@ -0,0 +1,14 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* + * Device Tree Source for the RZ/G3S R9A08G045S33 SoC specific part + * + * Copyright (C) 2023 Renesas Electronics Corp. + */ + +/dts-v1/; + +#include "r9a08g045.dtsi" + +/ { + compatible = "renesas,r9a08g045s33", "renesas,r9a08g045"; +}; diff --git a/arch/arm64/boot/dts/renesas/rz-smarc-common.dtsi b/arch/arm64/boot/dts/renesas/rz-smarc-common.dtsi index a7594ba3a9..b7a3e6caa3 100644 --- a/arch/arm64/boot/dts/renesas/rz-smarc-common.dtsi +++ b/arch/arm64/boot/dts/renesas/rz-smarc-common.dtsi @@ -32,12 +32,6 @@ stdout-path = "serial0:115200n8"; }; - audio_mclock: audio_mclock { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <11289600>; - }; - snd_rzg2l: sound { compatible = "simple-audio-card"; simple-audio-card,format = "i2s"; @@ -55,7 +49,7 @@ }; codec_dai: simple-audio-card,codec { - clocks = <&audio_mclock>; + clocks = <&versa3 2>; sound-dai = <&wm8978>; }; }; @@ -76,6 +70,12 @@ gpios-states = <1>; states = <3300000 1>, <1800000 0>; }; + + x1: x1-clock { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + }; }; &audio_clk1 { diff --git a/arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi b/arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi index 68eab8e26b..37807f1bda 100644 --- a/arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi @@ -110,6 +110,26 @@ #sound-dai-cells = <0>; reg = <0x1a>; }; + + versa3: clock-generator@68 { + compatible = "renesas,5p35023"; + reg = <0x68>; + #clock-cells = <1>; + clocks = <&x1>; + + renesas,settings = [ + 80 00 11 19 4c 02 23 7f 83 19 08 a9 5f 25 24 bf + 00 14 7a e1 00 00 00 00 01 55 59 bb 3f 30 90 b6 + 80 b0 45 c4 95 + ]; + + assigned-clocks = <&versa3 0>, <&versa3 1>, + <&versa3 2>, <&versa3 3>, + <&versa3 4>, <&versa3 5>; + assigned-clock-rates = <24000000>, <11289600>, + <11289600>, <12000000>, + <25000000>, <12288000>; + }; }; #if PMOD_MTU3 diff --git a/arch/arm64/boot/dts/renesas/rzg2lc-smarc.dtsi b/arch/arm64/boot/dts/renesas/rzg2lc-smarc.dtsi index 83fce96a25..859bc8745e 100644 --- a/arch/arm64/boot/dts/renesas/rzg2lc-smarc.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg2lc-smarc.dtsi @@ -126,6 +126,26 @@ #sound-dai-cells = <0>; reg = <0x1a>; }; + + versa3: clock-generator@68 { + compatible = "renesas,5p35023"; + reg = <0x68>; + #clock-cells = <1>; + clocks = <&x1>; + + renesas,settings = [ + 80 00 11 19 4c 02 23 7f 83 19 08 a9 5f 25 24 bf + 00 14 7a e1 00 00 00 00 01 55 59 bb 3f 30 90 b6 + 80 b0 45 c4 95 + ]; + + assigned-clocks = <&versa3 0>, <&versa3 1>, + <&versa3 2>, <&versa3 3>, + <&versa3 4>, <&versa3 5>; + assigned-clock-rates = <24000000>, <11289600>, + <11289600>, <12000000>, + <25000000>, <12288000>; + }; }; #if PMOD_MTU3 diff --git a/arch/arm64/boot/dts/renesas/rzg2ul-smarc.dtsi b/arch/arm64/boot/dts/renesas/rzg2ul-smarc.dtsi index 8eb411aac8..de590996e1 100644 --- a/arch/arm64/boot/dts/renesas/rzg2ul-smarc.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg2ul-smarc.dtsi @@ -20,6 +20,30 @@ sound-dai = <&ssi1>; }; +&i2c0 { + clock-frequency = <400000>; + + versa3: clock-generator@68 { + compatible = "renesas,5p35023"; + reg = <0x68>; + #clock-cells = <1>; + clocks = <&x1>; + + renesas,settings = [ + 80 00 11 19 4c 02 23 7f 83 19 08 a9 5f 25 24 bf + 00 14 7a e1 00 00 00 00 01 55 59 bb 3f 30 90 b6 + 80 b0 45 c4 95 + ]; + + assigned-clocks = <&versa3 0>, <&versa3 1>, + <&versa3 2>, <&versa3 3>, + <&versa3 4>, <&versa3 5>; + assigned-clock-rates = <24000000>, <11289600>, + <11289600>, <12000000>, + <25000000>, <12288000>; + }; +}; + &i2c1 { wm8978: codec@1a { compatible = "wlf,wm8978"; diff --git a/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi b/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi new file mode 100644 index 0000000000..a199de8f8b --- /dev/null +++ b/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi @@ -0,0 +1,142 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* + * Device Tree Source for the R9A08G045S33 SMARC Carrier-II's SoM board. + * + * Copyright (C) 2023 Renesas Electronics Corp. + */ + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/pinctrl/rzg2l-pinctrl.h> + +/* + * Signals of SW_CONFIG switches: + * @SW_SD0_DEV_SEL: + * 0 - SD0 is connected to eMMC + * 1 - SD0 is connected to uSD0 card + */ +#define SW_SD0_DEV_SEL 1 + +/ { + compatible = "renesas,rzg3s-smarcm", "renesas,r9a08g045s33", "renesas,r9a08g045"; + + aliases { + mmc0 = &sdhi0; + }; + + chosen { + bootargs = "ignore_loglevel"; + stdout-path = "serial0:115200n8"; + }; + + memory@48000000 { + device_type = "memory"; + /* First 128MB is reserved for secure area. */ + reg = <0x0 0x48000000 0x0 0x38000000>; + }; + + vcc_sdhi0: regulator0 { + compatible = "regulator-fixed"; + regulator-name = "SDHI0 Vcc"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpios = <&pinctrl RZG2L_GPIO(2, 1) GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + +#if SW_SD0_DEV_SEL + vccq_sdhi0: regulator1 { + compatible = "regulator-gpio"; + regulator-name = "SDHI0 VccQ"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + gpios = <&pinctrl RZG2L_GPIO(2, 2) GPIO_ACTIVE_HIGH>; + gpios-states = <1>; + states = <3300000 1>, <1800000 0>; + }; +#else + reg_1p8v: regulator1 { + compatible = "regulator-fixed"; + regulator-name = "fixed-1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; +#endif +}; + +&extal_clk { + clock-frequency = <24000000>; +}; + +#if SW_SD0_DEV_SEL +/* SD0 slot */ +&sdhi0 { + pinctrl-0 = <&sdhi0_pins>; + pinctrl-1 = <&sdhi0_uhs_pins>; + pinctrl-names = "default", "state_uhs"; + vmmc-supply = <&vcc_sdhi0>; + vqmmc-supply = <&vccq_sdhi0>; + bus-width = <4>; + sd-uhs-sdr50; + sd-uhs-sdr104; + max-frequency = <125000000>; + status = "okay"; +}; +#else +/* eMMC */ +&sdhi0 { + pinctrl-0 = <&sdhi0_emmc_pins>; + pinctrl-1 = <&sdhi0_emmc_pins>; + pinctrl-names = "default", "state_uhs"; + vmmc-supply = <&vcc_sdhi0>; + vqmmc-supply = <®_1p8v>; + bus-width = <8>; + mmc-hs200-1_8v; + non-removable; + fixed-emmc-driver-type = <1>; + max-frequency = <125000000>; + status = "okay"; +}; +#endif + +&pinctrl { + sdhi0_pins: sd0 { + data { + pins = "SD0_DATA0", "SD0_DATA1", "SD0_DATA2", "SD0_DATA3"; + power-source = <3300>; + }; + + ctrl { + pins = "SD0_CLK", "SD0_CMD"; + power-source = <3300>; + }; + + cd { + pinmux = <RZG2L_PORT_PINMUX(0, 0, 1)>; /* SD0_CD */ + }; + }; + + sdhi0_uhs_pins: sd0-uhs { + data { + pins = "SD0_DATA0", "SD0_DATA1", "SD0_DATA2", "SD0_DATA3"; + power-source = <1800>; + }; + + ctrl { + pins = "SD0_CLK", "SD0_CMD"; + power-source = <1800>; + }; + + cd { + pinmux = <RZG2L_PORT_PINMUX(0, 0, 1)>; /* SD0_CD */ + }; + }; + + sdhi0_emmc_pins: sd0-emmc { + pins = "SD0_DATA0", "SD0_DATA1", "SD0_DATA2", "SD0_DATA3", + "SD0_DATA4", "SD0_DATA5", "SD0_DATA6", "SD0_DATA7", + "SD0_CLK", "SD0_CMD", "SD0_RST#"; + power-source = <1800>; + }; +}; diff --git a/arch/arm64/boot/dts/renesas/rzg3s-smarc.dtsi b/arch/arm64/boot/dts/renesas/rzg3s-smarc.dtsi new file mode 100644 index 0000000000..e7073a09ed --- /dev/null +++ b/arch/arm64/boot/dts/renesas/rzg3s-smarc.dtsi @@ -0,0 +1,28 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* + * Device Tree Source for the RZ SMARC Carrier-II Board. + * + * Copyright (C) 2023 Renesas Electronics Corp. + */ + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/pinctrl/rzg2l-pinctrl.h> + +/ { + aliases { + serial0 = &scif0; + }; +}; + +&pinctrl { + scif0_pins: scif0 { + pinmux = <RZG2L_PORT_PINMUX(6, 3, 1)>, /* RXD */ + <RZG2L_PORT_PINMUX(6, 4, 1)>; /* TXD */ + }; +}; + +&scif0 { + pinctrl-names = "default"; + pinctrl-0 = <&scif0_pins>; + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/renesas/salvator-common.dtsi b/arch/arm64/boot/dts/renesas/salvator-common.dtsi index 4a3d503782..1eb4883b32 100644 --- a/arch/arm64/boot/dts/renesas/salvator-common.dtsi +++ b/arch/arm64/boot/dts/renesas/salvator-common.dtsi @@ -822,7 +822,7 @@ <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>, <&audio_clk_a>, <&cs2000>, <&audio_clk_c>, - <&cpg CPG_CORE CPG_AUDIO_CLK_I>; + <&cpg CPG_MOD 922>; ports { #address-cells = <1>; diff --git a/arch/arm64/boot/dts/renesas/ulcb-audio-graph-card-mix+split.dtsi b/arch/arm64/boot/dts/renesas/ulcb-audio-graph-card-mix+split.dtsi index 672b0a224e..be6d7a0357 100644 --- a/arch/arm64/boot/dts/renesas/ulcb-audio-graph-card-mix+split.dtsi +++ b/arch/arm64/boot/dts/renesas/ulcb-audio-graph-card-mix+split.dtsi @@ -21,14 +21,14 @@ / { sound_card: sound { compatible = "audio-graph-scu-card"; - label = "rcar-sound"; + label = "snd-ulcb-mix"; routing = "ak4613 Playback", "DAI0 Playback", "ak4613 Playback", "DAI1 Playback", "DAI0 Capture", "ak4613 Capture"; - dais = <&rsnd_port0 /* (A) CPU0 */ - &rsnd_port1 /* (B) CPU1 */ + dais = <&snd_ulcb1 /* (A) CPU0 */ + &snd_ulcb2 /* (B) CPU1 */ >; }; }; @@ -58,14 +58,18 @@ }; &rcar_sound { - ports { + #address-cells = <1>; + #size-cells = <0>; + + ports@0 { #address-cells = <1>; #size-cells = <0>; + reg = <0>; /* * (A) CPU0 */ - rsnd_port0: port@0 { + snd_ulcb1: port@0 { reg = <0>; rsnd_for_ak4613_1: endpoint { remote-endpoint = <&ak4613_ep1>; @@ -78,7 +82,7 @@ /* * (B) CPU1 */ - rsnd_port1: port@1 { + snd_ulcb2: port@1 { reg = <1>; rsnd_for_ak4613_2: endpoint { remote-endpoint = <&ak4613_ep2>; diff --git a/arch/arm64/boot/dts/renesas/ulcb-audio-graph-card.dtsi b/arch/arm64/boot/dts/renesas/ulcb-audio-graph-card.dtsi index 3be54df645..3f1df6ee17 100644 --- a/arch/arm64/boot/dts/renesas/ulcb-audio-graph-card.dtsi +++ b/arch/arm64/boot/dts/renesas/ulcb-audio-graph-card.dtsi @@ -18,10 +18,10 @@ / { sound_card: sound { compatible = "audio-graph-card"; - label = "rcar-sound"; + label = "snd-ulcb"; - dais = <&rsnd_port0 /* (A) CPU0 <-> ak4613 */ - &rsnd_port1 /* (B) CPU1 -> HDMI */ + dais = <&snd_ulcb1 /* (A) CPU0 <-> ak4613 */ + &snd_ulcb2 /* (B) CPU1 -> HDMI */ >; }; }; @@ -53,10 +53,15 @@ }; &rcar_sound { - ports { + #address-cells = <1>; + #size-cells = <0>; + + ports@0 { #address-cells = <1>; #size-cells = <0>; - rsnd_port0: port@0 { + reg = <0>; + + snd_ulcb1: port@0 { /* * (A) CPU0 <-> ak4613 */ @@ -69,7 +74,7 @@ capture = <&ssi1>, <&src1>, <&dvc1>; }; }; - rsnd_port1: port@1 { + snd_ulcb2: port@1 { /* * (B) CPU1 -> HDMI */ diff --git a/arch/arm64/boot/dts/renesas/ulcb-audio-graph-card2-mix+split.dtsi b/arch/arm64/boot/dts/renesas/ulcb-audio-graph-card2-mix+split.dtsi index 75b024e3fe..8966e6a7d2 100644 --- a/arch/arm64/boot/dts/renesas/ulcb-audio-graph-card2-mix+split.dtsi +++ b/arch/arm64/boot/dts/renesas/ulcb-audio-graph-card2-mix+split.dtsi @@ -20,13 +20,12 @@ / { sound_card: sound { compatible = "audio-graph-card2"; - label = "rcar-sound"; + label = "snd-ulcb-mix"; routing = "ak4613 Playback", "DAI0 Playback", "ak4613 Playback", "DAI1 Playback", "DAI0 Capture", "ak4613 Capture"; - /delete-property/ dais; links = <&fe_a /* (A) CPU0 */ &fe_b /* (B) CPU1 */ &be_x /* (X) ak4613 */ @@ -50,14 +49,12 @@ }; ports@1 { - #address-cells = <1>; - #size-cells = <0>; reg = <1>; /* * BE * (X) ak4613 */ - be_x: port@0 { reg = <0>; be_x_ep: endpoint { remote-endpoint = <&ak4613_x_ep>; }; }; + be_x: port { be_x_ep: endpoint { remote-endpoint = <&ak4613_x_ep>; }; }; }; }; }; @@ -78,9 +75,13 @@ }; &rcar_sound { - ports { + #address-cells = <1>; + #size-cells = <0>; + + ports@0 { #address-cells = <1>; #size-cells = <0>; + reg = <0>; /* * (A) CPU0 diff --git a/arch/arm64/boot/dts/renesas/ulcb-audio-graph-card2.dtsi b/arch/arm64/boot/dts/renesas/ulcb-audio-graph-card2.dtsi index 5ebec12358..19fa6e1029 100644 --- a/arch/arm64/boot/dts/renesas/ulcb-audio-graph-card2.dtsi +++ b/arch/arm64/boot/dts/renesas/ulcb-audio-graph-card2.dtsi @@ -20,7 +20,7 @@ compatible = "audio-graph-card2"; /delete-property/ dais; - links = <&rsnd_port0 /* (A) CPU0 <-> ak4613 */ - &rsnd_port1 /* (B) CPU1 -> HDMI */ + links = <&snd_ulcb1 /* (A) CPU0 <-> ak4613 */ + &snd_ulcb2 /* (B) CPU1 -> HDMI */ >; }; diff --git a/arch/arm64/boot/dts/renesas/ulcb-kf-audio-graph-card-mix+split.dtsi b/arch/arm64/boot/dts/renesas/ulcb-kf-audio-graph-card-mix+split.dtsi index 9b01354940..8ae6af1af0 100644 --- a/arch/arm64/boot/dts/renesas/ulcb-kf-audio-graph-card-mix+split.dtsi +++ b/arch/arm64/boot/dts/renesas/ulcb-kf-audio-graph-card-mix+split.dtsi @@ -19,32 +19,31 @@ * * (A) aplay -D plughw:0,0 xxx.wav (MIX-0) * (B) aplay -D plughw:0,1 xxx.wav (MIX-1) - * (C) aplay -D plughw:0,2 xxx.wav (TDM-0) - * (D) aplay -D plughw:0,3 xxx.wav (TDM-1) - * (E) aplay -D plughw:0,4 xxx.wav (TDM-2) - * (F) aplay -D plughw:0,5 xxx.wav (TDM-3) + * (C) aplay -D plughw:1,0 xxx.wav (TDM-0) + * (D) aplay -D plughw:1,1 xxx.wav (TDM-1) + * (E) aplay -D plughw:1,2 xxx.wav (TDM-2) + * (F) aplay -D plughw:1,3 xxx.wav (TDM-3) * * (A) arecord -D plughw:0,0 xxx.wav - * (G) arecord -D plughw:0,6 xxx.wav + * (G) arecord -D plughw:1,4 xxx.wav */ +/ { + sound_card_kf: expand-sound { + compatible = "audio-graph-scu-card"; + label = "snd-kf-split"; -&sound_card { - routing = "ak4613 Playback", "DAI0 Playback", - "ak4613 Playback", "DAI1 Playback", - "DAI0 Capture", "ak4613 Capture", - "pcm3168a Playback", "DAI2 Playback", - "pcm3168a Playback", "DAI3 Playback", - "pcm3168a Playback", "DAI4 Playback", - "pcm3168a Playback", "DAI5 Playback"; + routing = "pcm3168a Playback", "DAI2 Playback", + "pcm3168a Playback", "DAI3 Playback", + "pcm3168a Playback", "DAI4 Playback", + "pcm3168a Playback", "DAI5 Playback"; - dais = <&rsnd_port0 /* (A) CPU0 */ - &rsnd_port1 /* (B) CPU1 */ - &rsnd_port2 /* (C) CPU2 */ - &rsnd_port3 /* (D) CPU3 */ - &rsnd_port4 /* (E) CPU4 */ - &rsnd_port5 /* (F) CPU5 */ - &rsnd_port6 /* (G) GPU6 */ - >; + dais = <&snd_kf1 /* (C) CPU2 */ + &snd_kf2 /* (D) CPU3 */ + &snd_kf3 /* (E) CPU4 */ + &snd_kf4 /* (F) CPU5 */ + &snd_kf5 /* (G) GPU6 */ + >; + }; }; &pcm3168a { @@ -103,13 +102,15 @@ }; &rcar_sound { - ports { - /* rsnd_port0-1 are defined in ulcb.dtsi */ + ports@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; /* * (C) CPU2 */ - rsnd_port2: port@2 { + snd_kf1: port@2 { reg = <2>; rsnd_for_pcm3168a_play1: endpoint { remote-endpoint = <&pcm3168a_endpoint_p1>; @@ -121,7 +122,7 @@ /* * (D) CPU3 */ - rsnd_port3: port@3 { + snd_kf2: port@3 { reg = <3>; rsnd_for_pcm3168a_play2: endpoint { remote-endpoint = <&pcm3168a_endpoint_p2>; @@ -133,7 +134,7 @@ /* * (E) CPU4 */ - rsnd_port4: port@4 { + snd_kf3: port@4 { reg = <4>; rsnd_for_pcm3168a_play3: endpoint { remote-endpoint = <&pcm3168a_endpoint_p3>; @@ -145,7 +146,7 @@ /* * (F) CPU5 */ - rsnd_port5: port@5 { + snd_kf4: port@5 { reg = <5>; rsnd_for_pcm3168a_play4: endpoint { remote-endpoint = <&pcm3168a_endpoint_p4>; @@ -157,7 +158,7 @@ /* * (G) CPU6 */ - rsnd_port6: port@6 { + snd_kf5: port@6 { reg = <6>; rsnd_for_pcm3168a_capture: endpoint { remote-endpoint = <&pcm3168a_endpoint_c>; diff --git a/arch/arm64/boot/dts/renesas/ulcb-kf-audio-graph-card.dtsi b/arch/arm64/boot/dts/renesas/ulcb-kf-audio-graph-card.dtsi index 1db99b7608..5fbd4ca83e 100644 --- a/arch/arm64/boot/dts/renesas/ulcb-kf-audio-graph-card.dtsi +++ b/arch/arm64/boot/dts/renesas/ulcb-kf-audio-graph-card.dtsi @@ -13,18 +13,20 @@ * * (A) aplay -D plughw:0,0 xxx.wav * (B) aplay -D plughw:0,1 xxx.wav - * (C) aplay -D plughw:0,2 xxx.wav + * (C) aplay -D plughw:1,0 xxx.wav * * (A) arecord -D plughw:0,0 xxx.wav - * (D) arecord -D plughw:0,3 xxx.wav + * (D) arecord -D plughw:1,1 xxx.wav */ +/ { + sound_card_kf: expand-sound { + compatible = "audio-graph-card"; + label = "snd-kf"; -&sound_card { - dais = <&rsnd_port0 /* (A) CPU0 <-> ak4613 */ - &rsnd_port1 /* (B) CPU1 -> HDMI */ - &rsnd_port2 /* (C) CPU2 -> PCM3168A-p */ - &rsnd_port3 /* (D) CPU3 <- PCM3168A-c */ + dais = <&snd_kf1 /* (C) CPU2 -> PCM3168A-p */ + &snd_kf2 /* (D) CPU3 <- PCM3168A-c */ >; + }; }; &pcm3168a { @@ -56,12 +58,15 @@ }; &rcar_sound { - ports { - /* rsnd_port0/1 are defined in ulcb.dtsi */ + ports@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + /* * (C) CPU2 -> PCM3168A-p */ - rsnd_port2: port@2 { + snd_kf1: port@2 { reg = <2>; rsnd_for_pcm3168a_play: endpoint { remote-endpoint = <&pcm3168a_endpoint_p>; @@ -74,7 +79,7 @@ /* * (D) CPU3 <- PCM3168A-c */ - rsnd_port3: port@3 { + snd_kf2: port@3 { reg = <3>; rsnd_for_pcm3168a_capture: endpoint { remote-endpoint = <&pcm3168a_endpoint_c>; diff --git a/arch/arm64/boot/dts/renesas/ulcb-kf-audio-graph-card2-mix+split.dtsi b/arch/arm64/boot/dts/renesas/ulcb-kf-audio-graph-card2-mix+split.dtsi index da644128a9..4cf632bc46 100644 --- a/arch/arm64/boot/dts/renesas/ulcb-kf-audio-graph-card2-mix+split.dtsi +++ b/arch/arm64/boot/dts/renesas/ulcb-kf-audio-graph-card2-mix+split.dtsi @@ -19,61 +19,65 @@ * * (A) aplay -D plughw:0,0 xxx.wav (MIX-0) * (B) aplay -D plughw:0,1 xxx.wav (MIX-1) - * (C) aplay -D plughw:0,2 xxx.wav (TDM-0) - * (D) aplay -D plughw:0,3 xxx.wav (TDM-1) - * (E) aplay -D plughw:0,4 xxx.wav (TDM-2) - * (F) aplay -D plughw:0,5 xxx.wav (TDM-3) + * (C) aplay -D plughw:1,0 xxx.wav (TDM-0) + * (D) aplay -D plughw:1,1 xxx.wav (TDM-1) + * (E) aplay -D plughw:1,2 xxx.wav (TDM-2) + * (F) aplay -D plughw:1,3 xxx.wav (TDM-3) * * (A) arecord -D plughw:0,0 xxx.wav - * (G) arecord -D plughw:0,6 xxx.wav + * (G) arecord -D plughw:1,4 xxx.wav */ -&sound_card { - routing = "ak4613 Playback", "DAI0 Playback", - "ak4613 Playback", "DAI1 Playback", - "DAI0 Capture", "ak4613 Capture", - "pcm3168a Playback", "DAI2 Playback", - "pcm3168a Playback", "DAI3 Playback", - "pcm3168a Playback", "DAI4 Playback", - "pcm3168a Playback", "DAI5 Playback", - "DAI6 Capture", "pcm3168a Capture"; +/ { + sound_card_kf: expand-sound { + compatible = "audio-graph-card2"; + label = "snd-kf-split"; - /delete-property/ dais; - links = <&fe_a /* (A) CPU0 */ - &fe_b /* (B) CPU1 */ - &fe_c /* (C) CPU2 */ - &fe_d /* (D) CPU3 */ - &fe_e /* (E) CPU4 */ - &fe_f /* (F) CPU5 */ - &rsnd_g /* (G) CPU6 */ - &be_x /* (X) ak4613 */ - &be_y /* (Y) PCM3168A-p */ - >; + routing = "pcm3168a Playback", "DAI2 Playback", + "pcm3168a Playback", "DAI3 Playback", + "pcm3168a Playback", "DAI4 Playback", + "pcm3168a Playback", "DAI5 Playback", + "DAI6 Capture", "pcm3168a Capture"; - dpcm { - ports@0 { - /* - * FE - * - * (A)/(B) are defined on ulcb - * (C) CPU2 - * (D) CPU3 - * (E) CPU4 - * (F) CPU5 - */ - fe_c: port@2 { reg = <2>; fe_c_ep: endpoint { remote-endpoint = <&rsnd_c_ep>; }; }; - fe_d: port@3 { reg = <3>; fe_d_ep: endpoint { remote-endpoint = <&rsnd_d_ep>; }; }; - fe_e: port@4 { reg = <4>; fe_e_ep: endpoint { remote-endpoint = <&rsnd_e_ep>; }; }; - fe_f: port@5 { reg = <5>; fe_f_ep: endpoint { remote-endpoint = <&rsnd_f_ep>; }; }; - }; + links = <&fe_c /* (C) CPU2 */ + &fe_d /* (D) CPU3 */ + &fe_e /* (E) CPU4 */ + &fe_f /* (F) CPU5 */ + &rsnd_g /* (G) CPU6 */ + &be_y /* (Y) PCM3168A-p */ + >; - ports@1 { - /* - * BE - * - * (X) is defined on ulcb - * (Y) PCM3168A-p - */ - be_y: port@1 { reg = <1>; be_y_ep: endpoint { remote-endpoint = <&pcm3168a_y_ep>; }; }; + dpcm { + #address-cells = <1>; + #size-cells = <0>; + + ports@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + /* + * FE + * + * (C) CPU2 + * (D) CPU3 + * (E) CPU4 + * (F) CPU5 + */ + fe_c: port@2 { reg = <2>; fe_c_ep: endpoint { remote-endpoint = <&rsnd_c_ep>; }; }; + fe_d: port@3 { reg = <3>; fe_d_ep: endpoint { remote-endpoint = <&rsnd_d_ep>; }; }; + fe_e: port@4 { reg = <4>; fe_e_ep: endpoint { remote-endpoint = <&rsnd_e_ep>; }; }; + fe_f: port@5 { reg = <5>; fe_f_ep: endpoint { remote-endpoint = <&rsnd_f_ep>; }; }; + }; + + ports@1 { + reg = <1>; + /* + * BE + * + * (Y) PCM3168A-p + */ + be_y: port { be_y_ep: endpoint { remote-endpoint = <&pcm3168a_y_ep>; }; }; + }; }; }; }; @@ -111,8 +115,10 @@ }; &rcar_sound { - ports { - /* (A)/(B) are defined in ulcb.dtsi */ + ports@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; /* * (C) CPU2 diff --git a/arch/arm64/boot/dts/renesas/ulcb-kf-audio-graph-card2.dtsi b/arch/arm64/boot/dts/renesas/ulcb-kf-audio-graph-card2.dtsi index c30e056538..4fc229418d 100644 --- a/arch/arm64/boot/dts/renesas/ulcb-kf-audio-graph-card2.dtsi +++ b/arch/arm64/boot/dts/renesas/ulcb-kf-audio-graph-card2.dtsi @@ -13,18 +13,18 @@ * * (A) aplay -D plughw:0,0 xxx.wav * (B) aplay -D plughw:0,1 xxx.wav - * (C) aplay -D plughw:0,2 xxx.wav + * (C) aplay -D plughw:1,0 xxx.wav * * (A) arecord -D plughw:0,0 xxx.wav - * (D) arecord -D plughw:0,3 xxx.wav + * (D) arecord -D plughw:1,1 xxx.wav */ #include "ulcb-kf-audio-graph-card.dtsi" -&sound_card { +&sound_card_kf { + compatible = "audio-graph-card2"; + /delete-property/ dais; - links = <&rsnd_port0 /* (A) CPU0 <-> ak4613 */ - &rsnd_port1 /* (B) CPU1 -> HDMI */ - &rsnd_port2 /* (C) CPU2 -> PCM3168A-p */ - &rsnd_port3 /* (D) CPU3 <- PCM3168A-c */ + links = <&snd_kf1 /* (C) CPU2 -> PCM3168A-p */ + &snd_kf2 /* (D) CPU3 <- PCM3168A-c */ >; }; diff --git a/arch/arm64/boot/dts/renesas/ulcb-kf-simple-audio-card-mix+split.dtsi b/arch/arm64/boot/dts/renesas/ulcb-kf-simple-audio-card-mix+split.dtsi index bc221f9944..f01d91aaad 100644 --- a/arch/arm64/boot/dts/renesas/ulcb-kf-simple-audio-card-mix+split.dtsi +++ b/arch/arm64/boot/dts/renesas/ulcb-kf-simple-audio-card-mix+split.dtsi @@ -19,89 +19,92 @@ * * (A) aplay -D plughw:0,0 xxx.wav (MIX-0) * (B) aplay -D plughw:0,1 xxx.wav (MIX-1) - * (C) aplay -D plughw:0,2 xxx.wav (TDM-0) - * (D) aplay -D plughw:0,3 xxx.wav (TDM-1) - * (E) aplay -D plughw:0,4 xxx.wav (TDM-2) - * (F) aplay -D plughw:0,5 xxx.wav (TDM-3) + * (C) aplay -D plughw:1,0 xxx.wav (TDM-0) + * (D) aplay -D plughw:1,1 xxx.wav (TDM-1) + * (E) aplay -D plughw:1,2 xxx.wav (TDM-2) + * (F) aplay -D plughw:1,3 xxx.wav (TDM-3) * * (A) arecord -D plughw:0,0 xxx.wav - * (G) arecord -D plughw:0,6 xxx.wav + * (G) arecord -D plughw:1,4 xxx.wav */ -&sound_card { - - simple-audio-card,routing = "ak4613 Playback", "DAI0 Playback", - "ak4613 Playback", "DAI1 Playback", - "DAI0 Capture", "ak4613 Capture", - "pcm3168a Playback", "DAI2 Playback", - "pcm3168a Playback", "DAI3 Playback", - "pcm3168a Playback", "DAI4 Playback", - "pcm3168a Playback", "DAI5 Playback"; - - /* dai-link@0 is defined in ulcb.dtsi */ - - simple-audio-card,dai-link@1 { +/ { + sound_card_kf: expand-sound { #address-cells = <1>; #size-cells = <0>; - reg = <1>; - convert-channels = <8>; /* to 8ch TDM */ - /* - * (C) CPU2 - */ - cpu@0 { + compatible = "simple-scu-audio-card"; + label = "snd-kf-split"; + + simple-audio-card,routing = "pcm3168a Playback", "DAI2 Playback", + "pcm3168a Playback", "DAI3 Playback", + "pcm3168a Playback", "DAI4 Playback", + "pcm3168a Playback", "DAI5 Playback"; + + simple-audio-card,dai-link@0 { + #address-cells = <1>; + #size-cells = <0>; reg = <0>; - bitclock-master; - frame-master; - sound-dai = <&rcar_sound 2>; + convert-channels = <8>; /* to 8ch TDM */ + + /* + * (C) CPU2 + */ + cpu@0 { + reg = <0>; + bitclock-master; + frame-master; + sound-dai = <&rcar_sound 2>; + }; + /* + * (D) CPU3 + */ + cpu@1 { + reg = <1>; + sound-dai = <&rcar_sound 3>; + }; + /* + * (E) CPU4 + */ + cpu@2 { + reg = <2>; + sound-dai = <&rcar_sound 4>; + }; + /* + * (F) CPU5 + */ + cpu@3 { + reg = <3>; + sound-dai = <&rcar_sound 5>; + }; + /* + * (Y) PCM3168A-p + */ + codec { + prefix = "pcm3168a"; + mclk-fs = <512>; + sound-dai = <&pcm3168a 0>; + }; }; - /* - * (D) CPU3 - */ - cpu@1 { + + simple-audio-card,dai-link@1 { reg = <1>; - sound-dai = <&rcar_sound 3>; - }; - /* - * (E) CPU4 - */ - cpu@2 { - reg = <2>; - sound-dai = <&rcar_sound 4>; - }; - /* - * (F) CPU5 - */ - cpu@3 { - reg = <3>; - sound-dai = <&rcar_sound 5>; - }; - /* - * (Y) PCM3168A-p - */ - codec { - prefix = "pcm3168a"; - mclk-fs = <512>; - sound-dai = <&pcm3168a 0>; - }; - }; - simple-audio-card,dai-link@2 { - reg = <2>; - /* - * (G) CPU6 - */ - cpu { - bitclock-master; - frame-master; - sound-dai = <&rcar_sound 6>; - }; - /* - * (Z) PCM3168A-c - */ - codec { - prefix = "pcm3168a"; - mclk-fs = <512>; - sound-dai = <&pcm3168a 1>; + /* + * (G) CPU6 + */ + cpu { + bitclock-master; + frame-master; + sound-dai = <&rcar_sound 6>; + }; + /* + * (Z) PCM3168A-c + */ + codec { + prefix = "pcm3168a"; + mclk-fs = <512>; + sound-dai = <&pcm3168a 1>; + }; }; }; }; @@ -115,7 +118,8 @@ }; &rcar_sound { - rcar_sound,dai { + rcar_sound,dai@1 { + reg = <1>; /* dai0-1 are defined in ulcb.dtsi */ diff --git a/arch/arm64/boot/dts/renesas/ulcb-kf-simple-audio-card.dtsi b/arch/arm64/boot/dts/renesas/ulcb-kf-simple-audio-card.dtsi index 2010e8ac7f..28d29ecfb3 100644 --- a/arch/arm64/boot/dts/renesas/ulcb-kf-simple-audio-card.dtsi +++ b/arch/arm64/boot/dts/renesas/ulcb-kf-simple-audio-card.dtsi @@ -13,45 +13,51 @@ * * (A) aplay -D plughw:0,0 xxx.wav * (B) aplay -D plughw:0,1 xxx.wav - * (C) aplay -D plughw:0,2 xxx.wav + * (C) aplay -D plughw:1,0 xxx.wav * * (A) arecord -D plughw:0,0 xxx.wav - * (D) arecord -D plughw:0,3 xxx.wav + * (D) arecord -D plughw:1,1 xxx.wav */ -&sound_card { - /* dai-link@0/1 are defined in ulcb.dtsi */ +/ { + sound_card_kf: expand-sound { + compatible = "simple-audio-card"; + label = "snd-kf"; - /* - * (C) CPU2 -> PCM3168A-p - */ - simple-audio-card,dai-link@2 { - reg = <2>; - cpu { - bitclock-master; - frame-master; - dai-tdm-slot-num = <8>; - sound-dai = <&rcar_sound 2>; - }; - codec { - mclk-fs = <512>; - sound-dai = <&pcm3168a 0>; - }; - }; - /* - * (D) CPU3 <- PCM3168A-c - */ - simple-audio-card,dai-link@3 { - reg = <3>; - cpu { - bitclock-master; - frame-master; - dai-tdm-slot-num = <6>; - sound-dai = <&rcar_sound 3>; + #address-cells = <1>; + #size-cells = <0>; + + /* + * (C) CPU2 -> PCM3168A-p + */ + simple-audio-card,dai-link@0 { + reg = <0>; + cpu { + bitclock-master; + frame-master; + dai-tdm-slot-num = <8>; + sound-dai = <&rcar_sound 2>; + }; + codec { + mclk-fs = <512>; + sound-dai = <&pcm3168a 0>; + }; }; - codec { - mclk-fs = <512>; - sound-dai = <&pcm3168a 1>; + /* + * (D) CPU3 <- PCM3168A-c + */ + simple-audio-card,dai-link@1 { + reg = <1>; + cpu { + bitclock-master; + frame-master; + dai-tdm-slot-num = <6>; + sound-dai = <&rcar_sound 3>; + }; + codec { + mclk-fs = <512>; + sound-dai = <&pcm3168a 1>; + }; }; }; }; @@ -65,9 +71,8 @@ }; &rcar_sound { - - rcar_sound,dai { - /* dai0-1 are defined in ulcb.dtsi */ + rcar_sound,dai@1 { + reg = <1>; /* * (C) CPU2 -> PCM3168A-p diff --git a/arch/arm64/boot/dts/renesas/ulcb-simple-audio-card-mix+split.dtsi b/arch/arm64/boot/dts/renesas/ulcb-simple-audio-card-mix+split.dtsi index 217d890198..9b955510e3 100644 --- a/arch/arm64/boot/dts/renesas/ulcb-simple-audio-card-mix+split.dtsi +++ b/arch/arm64/boot/dts/renesas/ulcb-simple-audio-card-mix+split.dtsi @@ -24,7 +24,7 @@ #size-cells = <0>; compatible = "simple-scu-audio-card"; - label = "rcar-sound"; + label = "snd-ulcb-mix"; simple-audio-card,prefix = "ak4613"; simple-audio-card,routing = "ak4613 Playback", "DAI0 Playback", @@ -72,9 +72,13 @@ }; &rcar_sound { + #address-cells = <1>; + #size-cells = <0>; #sound-dai-cells = <1>; - rcar_sound,dai { + rcar_sound,dai@0 { + reg = <0>; + /* * (A) CPU0 */ diff --git a/arch/arm64/boot/dts/renesas/ulcb-simple-audio-card.dtsi b/arch/arm64/boot/dts/renesas/ulcb-simple-audio-card.dtsi index 751cfd8c52..ba0e188e7b 100644 --- a/arch/arm64/boot/dts/renesas/ulcb-simple-audio-card.dtsi +++ b/arch/arm64/boot/dts/renesas/ulcb-simple-audio-card.dtsi @@ -18,7 +18,7 @@ / { sound_card: sound { compatible = "simple-audio-card"; - label = "rcar-sound"; + label = "snd-ulcb"; #address-cells = <1>; #size-cells = <0>; @@ -69,9 +69,13 @@ }; &rcar_sound { + #address-cells = <1>; + #size-cells = <0>; #sound-dai-cells = <1>; - rcar_sound,dai { + rcar_sound,dai@0 { + reg = <0>; + /* * (A) CPU0 <-> ak4613 */ diff --git a/arch/arm64/boot/dts/renesas/ulcb.dtsi b/arch/arm64/boot/dts/renesas/ulcb.dtsi index 0be2716659..a2f66f9160 100644 --- a/arch/arm64/boot/dts/renesas/ulcb.dtsi +++ b/arch/arm64/boot/dts/renesas/ulcb.dtsi @@ -383,7 +383,7 @@ <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>, <&audio_clk_a>, <&cs2000>, <&audio_clk_c>, - <&cpg CPG_CORE CPG_AUDIO_CLK_I>; + <&cpg CPG_MOD 922>; }; &rpc { |