diff options
author | Daniel Baumann <daniel.baumann@progress-linux.org> | 2024-07-01 17:13:54 +0000 |
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committer | Daniel Baumann <daniel.baumann@progress-linux.org> | 2024-07-01 17:13:54 +0000 |
commit | 2957e9a7ea070524508a846205689431cb5c101f (patch) | |
tree | 42f079ff82e701ebcb76829974b4caca3e5b6798 /arch/mips/pci | |
parent | Adding upstream version 6.9.2. (diff) | |
download | linux-2957e9a7ea070524508a846205689431cb5c101f.tar.xz linux-2957e9a7ea070524508a846205689431cb5c101f.zip |
Adding upstream version 6.9.7.upstream/6.9.7upstream
Signed-off-by: Daniel Baumann <daniel.baumann@progress-linux.org>
Diffstat (limited to 'arch/mips/pci')
-rw-r--r-- | arch/mips/pci/ops-rc32434.c | 4 | ||||
-rwxr-xr-x[-rw-r--r--] | arch/mips/pci/pcie-octeon.c | 6 |
2 files changed, 8 insertions, 2 deletions
diff --git a/arch/mips/pci/ops-rc32434.c b/arch/mips/pci/ops-rc32434.c index 874ed6df9..34b9323bd 100644 --- a/arch/mips/pci/ops-rc32434.c +++ b/arch/mips/pci/ops-rc32434.c @@ -112,8 +112,8 @@ retry: * gives them time to settle */ if (where == PCI_VENDOR_ID) { - if (ret == 0xffffffff || ret == 0x00000000 || - ret == 0x0000ffff || ret == 0xffff0000) { + if (*val == 0xffffffff || *val == 0x00000000 || + *val == 0x0000ffff || *val == 0xffff0000) { if (delay > 4) return 0; delay *= 2; diff --git a/arch/mips/pci/pcie-octeon.c b/arch/mips/pci/pcie-octeon.c index 2583e318e..b080c7c6c 100644..100755 --- a/arch/mips/pci/pcie-octeon.c +++ b/arch/mips/pci/pcie-octeon.c @@ -230,12 +230,18 @@ static inline uint64_t __cvmx_pcie_build_config_addr(int pcie_port, int bus, { union cvmx_pcie_address pcie_addr; union cvmx_pciercx_cfg006 pciercx_cfg006; + union cvmx_pciercx_cfg032 pciercx_cfg032; pciercx_cfg006.u32 = cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG006(pcie_port)); if ((bus <= pciercx_cfg006.s.pbnum) && (dev != 0)) return 0; + pciercx_cfg032.u32 = + cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG032(pcie_port)); + if ((pciercx_cfg032.s.dlla == 0) || (pciercx_cfg032.s.lt == 1)) + return 0; + pcie_addr.u64 = 0; pcie_addr.config.upper = 2; pcie_addr.config.io = 1; |