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authorDaniel Baumann <daniel.baumann@progress-linux.org>2024-04-11 08:27:49 +0000
committerDaniel Baumann <daniel.baumann@progress-linux.org>2024-04-11 08:27:49 +0000
commitace9429bb58fd418f0c81d4c2835699bddf6bde6 (patch)
treeb2d64bc10158fdd5497876388cd68142ca374ed3 /drivers/accel/habanalabs/include/gaudi
parentInitial commit. (diff)
downloadlinux-ace9429bb58fd418f0c81d4c2835699bddf6bde6.tar.xz
linux-ace9429bb58fd418f0c81d4c2835699bddf6bde6.zip
Adding upstream version 6.6.15.upstream/6.6.15
Signed-off-by: Daniel Baumann <daniel.baumann@progress-linux.org>
Diffstat (limited to 'drivers/accel/habanalabs/include/gaudi')
-rw-r--r--drivers/accel/habanalabs/include/gaudi/asic_reg/cpu_if_regs.h174
-rw-r--r--drivers/accel/habanalabs/include/gaudi/asic_reg/dma0_core_masks.h348
-rw-r--r--drivers/accel/habanalabs/include/gaudi/asic_reg/dma0_core_regs.h156
-rw-r--r--drivers/accel/habanalabs/include/gaudi/asic_reg/dma0_qm_masks.h800
-rw-r--r--drivers/accel/habanalabs/include/gaudi/asic_reg/dma0_qm_regs.h834
-rw-r--r--drivers/accel/habanalabs/include/gaudi/asic_reg/dma1_core_regs.h156
-rw-r--r--drivers/accel/habanalabs/include/gaudi/asic_reg/dma1_qm_regs.h834
-rw-r--r--drivers/accel/habanalabs/include/gaudi/asic_reg/dma2_core_regs.h156
-rw-r--r--drivers/accel/habanalabs/include/gaudi/asic_reg/dma2_qm_regs.h834
-rw-r--r--drivers/accel/habanalabs/include/gaudi/asic_reg/dma3_core_regs.h156
-rw-r--r--drivers/accel/habanalabs/include/gaudi/asic_reg/dma3_qm_regs.h834
-rw-r--r--drivers/accel/habanalabs/include/gaudi/asic_reg/dma4_core_regs.h156
-rw-r--r--drivers/accel/habanalabs/include/gaudi/asic_reg/dma4_qm_regs.h834
-rw-r--r--drivers/accel/habanalabs/include/gaudi/asic_reg/dma5_core_regs.h156
-rw-r--r--drivers/accel/habanalabs/include/gaudi/asic_reg/dma5_qm_regs.h834
-rw-r--r--drivers/accel/habanalabs/include/gaudi/asic_reg/dma6_core_regs.h156
-rw-r--r--drivers/accel/habanalabs/include/gaudi/asic_reg/dma6_qm_regs.h834
-rw-r--r--drivers/accel/habanalabs/include/gaudi/asic_reg/dma7_core_regs.h156
-rw-r--r--drivers/accel/habanalabs/include/gaudi/asic_reg/dma7_qm_regs.h834
-rw-r--r--drivers/accel/habanalabs/include/gaudi/asic_reg/dma_if_e_n_down_ch0_regs.h896
-rw-r--r--drivers/accel/habanalabs/include/gaudi/asic_reg/dma_if_e_n_down_ch1_regs.h896
-rw-r--r--drivers/accel/habanalabs/include/gaudi/asic_reg/dma_if_e_n_regs.h860
-rw-r--r--drivers/accel/habanalabs/include/gaudi/asic_reg/dma_if_e_s_down_ch0_regs.h896
-rw-r--r--drivers/accel/habanalabs/include/gaudi/asic_reg/dma_if_e_s_down_ch1_regs.h896
-rw-r--r--drivers/accel/habanalabs/include/gaudi/asic_reg/dma_if_e_s_regs.h860
-rw-r--r--drivers/accel/habanalabs/include/gaudi/asic_reg/dma_if_w_n_down_ch0_regs.h896
-rw-r--r--drivers/accel/habanalabs/include/gaudi/asic_reg/dma_if_w_n_down_ch1_regs.h896
-rw-r--r--drivers/accel/habanalabs/include/gaudi/asic_reg/dma_if_w_n_regs.h860
-rw-r--r--drivers/accel/habanalabs/include/gaudi/asic_reg/dma_if_w_s_down_ch0_regs.h896
-rw-r--r--drivers/accel/habanalabs/include/gaudi/asic_reg/dma_if_w_s_down_ch1_regs.h896
-rw-r--r--drivers/accel/habanalabs/include/gaudi/asic_reg/dma_if_w_s_regs.h860
-rw-r--r--drivers/accel/habanalabs/include/gaudi/asic_reg/gaudi_blocks.h4974
-rw-r--r--drivers/accel/habanalabs/include/gaudi/asic_reg/gaudi_regs.h325
-rw-r--r--drivers/accel/habanalabs/include/gaudi/asic_reg/mme0_ctrl_regs.h1456
-rw-r--r--drivers/accel/habanalabs/include/gaudi/asic_reg/mme0_qm_masks.h800
-rw-r--r--drivers/accel/habanalabs/include/gaudi/asic_reg/mme0_qm_regs.h834
-rw-r--r--drivers/accel/habanalabs/include/gaudi/asic_reg/mme1_ctrl_regs.h1456
-rw-r--r--drivers/accel/habanalabs/include/gaudi/asic_reg/mme2_ctrl_regs.h1456
-rw-r--r--drivers/accel/habanalabs/include/gaudi/asic_reg/mme2_qm_regs.h834
-rw-r--r--drivers/accel/habanalabs/include/gaudi/asic_reg/mme3_ctrl_regs.h1456
-rw-r--r--drivers/accel/habanalabs/include/gaudi/asic_reg/mmu_up_regs.h72
-rw-r--r--drivers/accel/habanalabs/include/gaudi/asic_reg/nic0_qm0_masks.h800
-rw-r--r--drivers/accel/habanalabs/include/gaudi/asic_reg/nic0_qm0_regs.h834
-rw-r--r--drivers/accel/habanalabs/include/gaudi/asic_reg/nic0_qm1_regs.h834
-rw-r--r--drivers/accel/habanalabs/include/gaudi/asic_reg/nic1_qm0_regs.h834
-rw-r--r--drivers/accel/habanalabs/include/gaudi/asic_reg/nic1_qm1_regs.h834
-rw-r--r--drivers/accel/habanalabs/include/gaudi/asic_reg/nic2_qm0_regs.h834
-rw-r--r--drivers/accel/habanalabs/include/gaudi/asic_reg/nic2_qm1_regs.h834
-rw-r--r--drivers/accel/habanalabs/include/gaudi/asic_reg/nic3_qm0_regs.h834
-rw-r--r--drivers/accel/habanalabs/include/gaudi/asic_reg/nic3_qm1_regs.h834
-rw-r--r--drivers/accel/habanalabs/include/gaudi/asic_reg/nic4_qm0_regs.h834
-rw-r--r--drivers/accel/habanalabs/include/gaudi/asic_reg/nic4_qm1_regs.h834
-rw-r--r--drivers/accel/habanalabs/include/gaudi/asic_reg/nif_rtr_ctrl_0_regs.h896
-rw-r--r--drivers/accel/habanalabs/include/gaudi/asic_reg/nif_rtr_ctrl_1_regs.h896
-rw-r--r--drivers/accel/habanalabs/include/gaudi/asic_reg/nif_rtr_ctrl_2_regs.h896
-rw-r--r--drivers/accel/habanalabs/include/gaudi/asic_reg/nif_rtr_ctrl_3_regs.h896
-rw-r--r--drivers/accel/habanalabs/include/gaudi/asic_reg/nif_rtr_ctrl_4_regs.h896
-rw-r--r--drivers/accel/habanalabs/include/gaudi/asic_reg/nif_rtr_ctrl_5_regs.h896
-rw-r--r--drivers/accel/habanalabs/include/gaudi/asic_reg/nif_rtr_ctrl_6_regs.h896
-rw-r--r--drivers/accel/habanalabs/include/gaudi/asic_reg/nif_rtr_ctrl_7_regs.h896
-rw-r--r--drivers/accel/habanalabs/include/gaudi/asic_reg/psoc_cpu_pll_regs.h114
-rw-r--r--drivers/accel/habanalabs/include/gaudi/asic_reg/psoc_etr_regs.h114
-rw-r--r--drivers/accel/habanalabs/include/gaudi/asic_reg/psoc_global_conf_masks.h502
-rw-r--r--drivers/accel/habanalabs/include/gaudi/asic_reg/psoc_global_conf_regs.h1062
-rw-r--r--drivers/accel/habanalabs/include/gaudi/asic_reg/psoc_timestamp_regs.h56
-rw-r--r--drivers/accel/habanalabs/include/gaudi/asic_reg/sif_rtr_ctrl_0_regs.h896
-rw-r--r--drivers/accel/habanalabs/include/gaudi/asic_reg/sif_rtr_ctrl_1_regs.h896
-rw-r--r--drivers/accel/habanalabs/include/gaudi/asic_reg/sif_rtr_ctrl_2_regs.h896
-rw-r--r--drivers/accel/habanalabs/include/gaudi/asic_reg/sif_rtr_ctrl_3_regs.h896
-rw-r--r--drivers/accel/habanalabs/include/gaudi/asic_reg/sif_rtr_ctrl_4_regs.h896
-rw-r--r--drivers/accel/habanalabs/include/gaudi/asic_reg/sif_rtr_ctrl_5_regs.h896
-rw-r--r--drivers/accel/habanalabs/include/gaudi/asic_reg/sif_rtr_ctrl_6_regs.h896
-rw-r--r--drivers/accel/habanalabs/include/gaudi/asic_reg/sif_rtr_ctrl_7_regs.h896
-rw-r--r--drivers/accel/habanalabs/include/gaudi/asic_reg/stlb_regs.h82
-rw-r--r--drivers/accel/habanalabs/include/gaudi/asic_reg/tpc0_cfg_masks.h2578
-rw-r--r--drivers/accel/habanalabs/include/gaudi/asic_reg/tpc0_cfg_regs.h1226
-rw-r--r--drivers/accel/habanalabs/include/gaudi/asic_reg/tpc0_qm_masks.h800
-rw-r--r--drivers/accel/habanalabs/include/gaudi/asic_reg/tpc0_qm_regs.h834
-rw-r--r--drivers/accel/habanalabs/include/gaudi/asic_reg/tpc1_cfg_regs.h1226
-rw-r--r--drivers/accel/habanalabs/include/gaudi/asic_reg/tpc1_qm_regs.h834
-rw-r--r--drivers/accel/habanalabs/include/gaudi/asic_reg/tpc2_cfg_regs.h1226
-rw-r--r--drivers/accel/habanalabs/include/gaudi/asic_reg/tpc2_qm_regs.h834
-rw-r--r--drivers/accel/habanalabs/include/gaudi/asic_reg/tpc3_cfg_regs.h1226
-rw-r--r--drivers/accel/habanalabs/include/gaudi/asic_reg/tpc3_qm_regs.h834
-rw-r--r--drivers/accel/habanalabs/include/gaudi/asic_reg/tpc4_cfg_regs.h1226
-rw-r--r--drivers/accel/habanalabs/include/gaudi/asic_reg/tpc4_qm_regs.h834
-rw-r--r--drivers/accel/habanalabs/include/gaudi/asic_reg/tpc5_cfg_regs.h1226
-rw-r--r--drivers/accel/habanalabs/include/gaudi/asic_reg/tpc5_qm_regs.h834
-rw-r--r--drivers/accel/habanalabs/include/gaudi/asic_reg/tpc6_cfg_regs.h1226
-rw-r--r--drivers/accel/habanalabs/include/gaudi/asic_reg/tpc6_qm_regs.h834
-rw-r--r--drivers/accel/habanalabs/include/gaudi/asic_reg/tpc7_cfg_regs.h1226
-rw-r--r--drivers/accel/habanalabs/include/gaudi/asic_reg/tpc7_qm_regs.h834
-rw-r--r--drivers/accel/habanalabs/include/gaudi/gaudi.h61
-rw-r--r--drivers/accel/habanalabs/include/gaudi/gaudi_async_events.h332
-rw-r--r--drivers/accel/habanalabs/include/gaudi/gaudi_async_ids_map_extended.h710
-rw-r--r--drivers/accel/habanalabs/include/gaudi/gaudi_coresight.h367
-rw-r--r--drivers/accel/habanalabs/include/gaudi/gaudi_fw_if.h91
-rw-r--r--drivers/accel/habanalabs/include/gaudi/gaudi_masks.h470
-rw-r--r--drivers/accel/habanalabs/include/gaudi/gaudi_packets.h194
-rw-r--r--drivers/accel/habanalabs/include/gaudi/gaudi_reg_map.h39
100 files changed, 81041 insertions, 0 deletions
diff --git a/drivers/accel/habanalabs/include/gaudi/asic_reg/cpu_if_regs.h b/drivers/accel/habanalabs/include/gaudi/asic_reg/cpu_if_regs.h
new file mode 100644
index 0000000000..cf80e31317
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi/asic_reg/cpu_if_regs.h
@@ -0,0 +1,174 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2016-2018 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ ** DO NOT EDIT BELOW **
+ ************************************/
+
+#ifndef ASIC_REG_CPU_IF_REGS_H_
+#define ASIC_REG_CPU_IF_REGS_H_
+
+/*
+ *****************************************
+ * CPU_IF (Prototype: CPU_IF)
+ *****************************************
+ */
+
+#define mmCPU_IF_ARUSER_OVR 0x442104
+
+#define mmCPU_IF_ARUSER_OVR_EN 0x442108
+
+#define mmCPU_IF_AWUSER_OVR 0x44210C
+
+#define mmCPU_IF_AWUSER_OVR_EN 0x442110
+
+#define mmCPU_IF_AXCACHE_OVR 0x442114
+
+#define mmCPU_IF_LOCK_OVR 0x442118
+
+#define mmCPU_IF_PROT_OVR 0x44211C
+
+#define mmCPU_IF_MAX_OUTSTANDING 0x442120
+
+#define mmCPU_IF_EARLY_BRESP_EN 0x442124
+
+#define mmCPU_IF_FORCE_RSP_OK 0x442128
+
+#define mmCPU_IF_CPU_MSB_ADDR 0x44212C
+
+#define mmCPU_IF_AXI_SPLIT_INTR 0x442130
+
+#define mmCPU_IF_TOTAL_WR_CNT 0x442140
+
+#define mmCPU_IF_INFLIGHT_WR_CNT 0x442144
+
+#define mmCPU_IF_TOTAL_RD_CNT 0x442150
+
+#define mmCPU_IF_INFLIGHT_RD_CNT 0x442154
+
+#define mmCPU_IF_PF_PQ_PI 0x442200
+
+#define mmCPU_IF_PQ_BASE_ADDR_LOW 0x442204
+
+#define mmCPU_IF_PQ_BASE_ADDR_HIGH 0x442208
+
+#define mmCPU_IF_PQ_LENGTH 0x44220C
+
+#define mmCPU_IF_CQ_BASE_ADDR_LOW 0x442210
+
+#define mmCPU_IF_CQ_BASE_ADDR_HIGH 0x442214
+
+#define mmCPU_IF_CQ_LENGTH 0x442218
+
+#define mmCPU_IF_EQ_BASE_ADDR_LOW 0x442220
+
+#define mmCPU_IF_EQ_BASE_ADDR_HIGH 0x442224
+
+#define mmCPU_IF_EQ_LENGTH 0x442228
+
+#define mmCPU_IF_EQ_RD_OFFS 0x44222C
+
+#define mmCPU_IF_QUEUE_INIT 0x442230
+
+#define mmCPU_IF_TPC_SERR_INTR_STS 0x442300
+
+#define mmCPU_IF_TPC_SERR_INTR_CLR 0x442304
+
+#define mmCPU_IF_TPC_SERR_INTR_MASK 0x442308
+
+#define mmCPU_IF_TPC_DERR_INTR_STS 0x442310
+
+#define mmCPU_IF_TPC_DERR_INTR_CLR 0x442314
+
+#define mmCPU_IF_TPC_DERR_INTR_MASK 0x442318
+
+#define mmCPU_IF_DMA_SERR_INTR_STS 0x442320
+
+#define mmCPU_IF_DMA_SERR_INTR_CLR 0x442324
+
+#define mmCPU_IF_DMA_SERR_INTR_MASK 0x442328
+
+#define mmCPU_IF_DMA_DERR_INTR_STS 0x442330
+
+#define mmCPU_IF_DMA_DERR_INTR_CLR 0x442334
+
+#define mmCPU_IF_DMA_DERR_INTR_MASK 0x442338
+
+#define mmCPU_IF_SRAM_SERR_INTR_STS 0x442340
+
+#define mmCPU_IF_SRAM_SERR_INTR_CLR 0x442344
+
+#define mmCPU_IF_SRAM_SERR_INTR_MASK 0x442348
+
+#define mmCPU_IF_SRAM_DERR_INTR_STS 0x442350
+
+#define mmCPU_IF_SRAM_DERR_INTR_CLR 0x442354
+
+#define mmCPU_IF_SRAM_DERR_INTR_MASK 0x442358
+
+#define mmCPU_IF_NIC_SERR_INTR_STS 0x442360
+
+#define mmCPU_IF_NIC_SERR_INTR_CLR 0x442364
+
+#define mmCPU_IF_NIC_SERR_INTR_MASK 0x442368
+
+#define mmCPU_IF_NIC_DERR_INTR_STS 0x442370
+
+#define mmCPU_IF_NIC_DERR_INTR_CLR 0x442374
+
+#define mmCPU_IF_NIC_DERR_INTR_MASK 0x442378
+
+#define mmCPU_IF_DMA_IF_SERR_INTR_STS 0x442380
+
+#define mmCPU_IF_DMA_IF_SERR_INTR_CLR 0x442384
+
+#define mmCPU_IF_DMA_IF_SERR_INTR_MASK 0x442388
+
+#define mmCPU_IF_DMA_IF_DERR_INTR_STS 0x442390
+
+#define mmCPU_IF_DMA_IF_DERR_INTR_CLR 0x442394
+
+#define mmCPU_IF_DMA_IF_DERR_INTR_MASK 0x442398
+
+#define mmCPU_IF_HBM_SERR_INTR_STS 0x4423A0
+
+#define mmCPU_IF_HBM_SERR_INTR_CLR 0x4423A4
+
+#define mmCPU_IF_HBM_SERR_INTR_MASK 0x4423A8
+
+#define mmCPU_IF_HBM_DERR_INTR_STS 0x4423B0
+
+#define mmCPU_IF_HBM_DERR_INTR_CLR 0x4423B4
+
+#define mmCPU_IF_HBM_DERR_INTR_MASK 0x4423B8
+
+#define mmCPU_IF_PLL_SEI_INTR_STS 0x442400
+
+#define mmCPU_IF_PLL_SEI_INTR_CLR 0x442404
+
+#define mmCPU_IF_PLL_SEI_INTR_MASK 0x442408
+
+#define mmCPU_IF_NIC_SEI_INTR_STS 0x442410
+
+#define mmCPU_IF_NIC_SEI_INTR_CLR 0x442414
+
+#define mmCPU_IF_NIC_SEI_INTR_MASK 0x442418
+
+#define mmCPU_IF_DMA_SEI_INTR_STS 0x442420
+
+#define mmCPU_IF_DMA_SEI_INTR_CLR 0x442424
+
+#define mmCPU_IF_DMA_SEI_INTR_MASK 0x442428
+
+#define mmCPU_IF_DMA_IF_SEI_INTR_STS 0x442430
+
+#define mmCPU_IF_DMA_IF_SEI_INTR_CLR 0x442434
+
+#define mmCPU_IF_DMA_IF_SEI_INTR_MASK 0x442438
+
+#endif /* ASIC_REG_CPU_IF_REGS_H_ */
diff --git a/drivers/accel/habanalabs/include/gaudi/asic_reg/dma0_core_masks.h b/drivers/accel/habanalabs/include/gaudi/asic_reg/dma0_core_masks.h
new file mode 100644
index 0000000000..d079a37aca
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi/asic_reg/dma0_core_masks.h
@@ -0,0 +1,348 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2016-2018 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ ** DO NOT EDIT BELOW **
+ ************************************/
+
+#ifndef ASIC_REG_DMA0_CORE_MASKS_H_
+#define ASIC_REG_DMA0_CORE_MASKS_H_
+
+/*
+ *****************************************
+ * DMA0_CORE (Prototype: DMA_CORE)
+ *****************************************
+ */
+
+/* DMA0_CORE_CFG_0 */
+#define DMA0_CORE_CFG_0_EN_SHIFT 0
+#define DMA0_CORE_CFG_0_EN_MASK 0x1
+
+/* DMA0_CORE_CFG_1 */
+#define DMA0_CORE_CFG_1_HALT_SHIFT 0
+#define DMA0_CORE_CFG_1_HALT_MASK 0x1
+#define DMA0_CORE_CFG_1_FLUSH_SHIFT 1
+#define DMA0_CORE_CFG_1_FLUSH_MASK 0x2
+#define DMA0_CORE_CFG_1_SB_FORCE_MISS_SHIFT 2
+#define DMA0_CORE_CFG_1_SB_FORCE_MISS_MASK 0x4
+
+/* DMA0_CORE_LBW_MAX_OUTSTAND */
+#define DMA0_CORE_LBW_MAX_OUTSTAND_VAL_SHIFT 0
+#define DMA0_CORE_LBW_MAX_OUTSTAND_VAL_MASK 0x1F
+
+/* DMA0_CORE_SRC_BASE_LO */
+#define DMA0_CORE_SRC_BASE_LO_VAL_SHIFT 0
+#define DMA0_CORE_SRC_BASE_LO_VAL_MASK 0xFFFFFFFF
+
+/* DMA0_CORE_SRC_BASE_HI */
+#define DMA0_CORE_SRC_BASE_HI_VAL_SHIFT 0
+#define DMA0_CORE_SRC_BASE_HI_VAL_MASK 0xFFFFFFFF
+
+/* DMA0_CORE_DST_BASE_LO */
+#define DMA0_CORE_DST_BASE_LO_VAL_SHIFT 0
+#define DMA0_CORE_DST_BASE_LO_VAL_MASK 0xFFFFFFFF
+
+/* DMA0_CORE_DST_BASE_HI */
+#define DMA0_CORE_DST_BASE_HI_VAL_SHIFT 0
+#define DMA0_CORE_DST_BASE_HI_VAL_MASK 0xFFFFFF
+#define DMA0_CORE_DST_BASE_HI_CTX_ID_HI_SHIFT 24
+#define DMA0_CORE_DST_BASE_HI_CTX_ID_HI_MASK 0xFF000000
+
+/* DMA0_CORE_SRC_TSIZE_1 */
+#define DMA0_CORE_SRC_TSIZE_1_VAL_SHIFT 0
+#define DMA0_CORE_SRC_TSIZE_1_VAL_MASK 0xFFFFFFFF
+
+/* DMA0_CORE_SRC_STRIDE_1 */
+#define DMA0_CORE_SRC_STRIDE_1_VAL_SHIFT 0
+#define DMA0_CORE_SRC_STRIDE_1_VAL_MASK 0xFFFFFFFF
+
+/* DMA0_CORE_SRC_TSIZE_2 */
+#define DMA0_CORE_SRC_TSIZE_2_VAL_SHIFT 0
+#define DMA0_CORE_SRC_TSIZE_2_VAL_MASK 0xFFFFFFFF
+
+/* DMA0_CORE_SRC_STRIDE_2 */
+#define DMA0_CORE_SRC_STRIDE_2_VAL_SHIFT 0
+#define DMA0_CORE_SRC_STRIDE_2_VAL_MASK 0xFFFFFFFF
+
+/* DMA0_CORE_SRC_TSIZE_3 */
+#define DMA0_CORE_SRC_TSIZE_3_VAL_SHIFT 0
+#define DMA0_CORE_SRC_TSIZE_3_VAL_MASK 0xFFFFFFFF
+
+/* DMA0_CORE_SRC_STRIDE_3 */
+#define DMA0_CORE_SRC_STRIDE_3_VAL_SHIFT 0
+#define DMA0_CORE_SRC_STRIDE_3_VAL_MASK 0xFFFFFFFF
+
+/* DMA0_CORE_SRC_TSIZE_4 */
+#define DMA0_CORE_SRC_TSIZE_4_VAL_SHIFT 0
+#define DMA0_CORE_SRC_TSIZE_4_VAL_MASK 0xFFFFFFFF
+
+/* DMA0_CORE_SRC_STRIDE_4 */
+#define DMA0_CORE_SRC_STRIDE_4_VAL_SHIFT 0
+#define DMA0_CORE_SRC_STRIDE_4_VAL_MASK 0xFFFFFFFF
+
+/* DMA0_CORE_SRC_TSIZE_0 */
+#define DMA0_CORE_SRC_TSIZE_0_VAL_SHIFT 0
+#define DMA0_CORE_SRC_TSIZE_0_VAL_MASK 0xFFFFFFFF
+
+/* DMA0_CORE_DST_TSIZE_1 */
+#define DMA0_CORE_DST_TSIZE_1_VAL_SHIFT 0
+#define DMA0_CORE_DST_TSIZE_1_VAL_MASK 0xFFFFFFFF
+
+/* DMA0_CORE_DST_STRIDE_1 */
+#define DMA0_CORE_DST_STRIDE_1_VAL_SHIFT 0
+#define DMA0_CORE_DST_STRIDE_1_VAL_MASK 0xFFFFFFFF
+
+/* DMA0_CORE_DST_TSIZE_2 */
+#define DMA0_CORE_DST_TSIZE_2_VAL_SHIFT 0
+#define DMA0_CORE_DST_TSIZE_2_VAL_MASK 0xFFFFFFFF
+
+/* DMA0_CORE_DST_STRIDE_2 */
+#define DMA0_CORE_DST_STRIDE_2_VAL_SHIFT 0
+#define DMA0_CORE_DST_STRIDE_2_VAL_MASK 0xFFFFFFFF
+
+/* DMA0_CORE_DST_TSIZE_3 */
+#define DMA0_CORE_DST_TSIZE_3_VAL_SHIFT 0
+#define DMA0_CORE_DST_TSIZE_3_VAL_MASK 0xFFFFFFFF
+
+/* DMA0_CORE_DST_STRIDE_3 */
+#define DMA0_CORE_DST_STRIDE_3_VAL_SHIFT 0
+#define DMA0_CORE_DST_STRIDE_3_VAL_MASK 0xFFFFFFFF
+
+/* DMA0_CORE_DST_TSIZE_4 */
+#define DMA0_CORE_DST_TSIZE_4_VAL_SHIFT 0
+#define DMA0_CORE_DST_TSIZE_4_VAL_MASK 0xFFFFFFFF
+
+/* DMA0_CORE_DST_STRIDE_4 */
+#define DMA0_CORE_DST_STRIDE_4_VAL_SHIFT 0
+#define DMA0_CORE_DST_STRIDE_4_VAL_MASK 0xFFFFFFFF
+
+/* DMA0_CORE_DST_TSIZE_0 */
+#define DMA0_CORE_DST_TSIZE_0_VAL_SHIFT 0
+#define DMA0_CORE_DST_TSIZE_0_VAL_MASK 0xFFFFFFFF
+
+/* DMA0_CORE_COMMIT */
+#define DMA0_CORE_COMMIT_WR_COMP_EN_SHIFT 0
+#define DMA0_CORE_COMMIT_WR_COMP_EN_MASK 0x1
+#define DMA0_CORE_COMMIT_TRANSPOSE_SHIFT 1
+#define DMA0_CORE_COMMIT_TRANSPOSE_MASK 0x2
+#define DMA0_CORE_COMMIT_DTYPE_SHIFT 2
+#define DMA0_CORE_COMMIT_DTYPE_MASK 0x4
+#define DMA0_CORE_COMMIT_LIN_SHIFT 3
+#define DMA0_CORE_COMMIT_LIN_MASK 0x8
+#define DMA0_CORE_COMMIT_MEM_SET_SHIFT 4
+#define DMA0_CORE_COMMIT_MEM_SET_MASK 0x10
+#define DMA0_CORE_COMMIT_COMPRESS_SHIFT 5
+#define DMA0_CORE_COMMIT_COMPRESS_MASK 0x20
+#define DMA0_CORE_COMMIT_DECOMPRESS_SHIFT 6
+#define DMA0_CORE_COMMIT_DECOMPRESS_MASK 0x40
+#define DMA0_CORE_COMMIT_CTX_ID_SHIFT 16
+#define DMA0_CORE_COMMIT_CTX_ID_MASK 0xFF0000
+
+/* DMA0_CORE_WR_COMP_WDATA */
+#define DMA0_CORE_WR_COMP_WDATA_VAL_SHIFT 0
+#define DMA0_CORE_WR_COMP_WDATA_VAL_MASK 0xFFFFFFFF
+
+/* DMA0_CORE_WR_COMP_ADDR_LO */
+#define DMA0_CORE_WR_COMP_ADDR_LO_VAL_SHIFT 0
+#define DMA0_CORE_WR_COMP_ADDR_LO_VAL_MASK 0xFFFFFFFF
+
+/* DMA0_CORE_WR_COMP_ADDR_HI */
+#define DMA0_CORE_WR_COMP_ADDR_HI_VAL_SHIFT 0
+#define DMA0_CORE_WR_COMP_ADDR_HI_VAL_MASK 0xFFFFFFFF
+
+/* DMA0_CORE_WR_COMP_AWUSER_31_11 */
+#define DMA0_CORE_WR_COMP_AWUSER_31_11_VAL_SHIFT 0
+#define DMA0_CORE_WR_COMP_AWUSER_31_11_VAL_MASK 0x1FFFFF
+
+/* DMA0_CORE_TE_NUMROWS */
+#define DMA0_CORE_TE_NUMROWS_VAL_SHIFT 0
+#define DMA0_CORE_TE_NUMROWS_VAL_MASK 0xFFFFFFFF
+
+/* DMA0_CORE_PROT */
+#define DMA0_CORE_PROT_VAL_SHIFT 0
+#define DMA0_CORE_PROT_VAL_MASK 0x1
+#define DMA0_CORE_PROT_ERR_VAL_SHIFT 1
+#define DMA0_CORE_PROT_ERR_VAL_MASK 0x2
+
+/* DMA0_CORE_SECURE_PROPS */
+#define DMA0_CORE_SECURE_PROPS_ASID_SHIFT 0
+#define DMA0_CORE_SECURE_PROPS_ASID_MASK 0x3FF
+#define DMA0_CORE_SECURE_PROPS_MMBP_SHIFT 10
+#define DMA0_CORE_SECURE_PROPS_MMBP_MASK 0x400
+
+/* DMA0_CORE_NON_SECURE_PROPS */
+#define DMA0_CORE_NON_SECURE_PROPS_ASID_SHIFT 0
+#define DMA0_CORE_NON_SECURE_PROPS_ASID_MASK 0x3FF
+#define DMA0_CORE_NON_SECURE_PROPS_MMBP_SHIFT 10
+#define DMA0_CORE_NON_SECURE_PROPS_MMBP_MASK 0x400
+
+/* DMA0_CORE_RD_MAX_OUTSTAND */
+#define DMA0_CORE_RD_MAX_OUTSTAND_VAL_SHIFT 0
+#define DMA0_CORE_RD_MAX_OUTSTAND_VAL_MASK 0xFFF
+
+/* DMA0_CORE_RD_MAX_SIZE */
+#define DMA0_CORE_RD_MAX_SIZE_DATA_SHIFT 0
+#define DMA0_CORE_RD_MAX_SIZE_DATA_MASK 0x7FF
+#define DMA0_CORE_RD_MAX_SIZE_MD_SHIFT 16
+#define DMA0_CORE_RD_MAX_SIZE_MD_MASK 0x7FF0000
+
+/* DMA0_CORE_RD_ARCACHE */
+#define DMA0_CORE_RD_ARCACHE_VAL_SHIFT 0
+#define DMA0_CORE_RD_ARCACHE_VAL_MASK 0xF
+
+/* DMA0_CORE_RD_ARUSER_31_11 */
+#define DMA0_CORE_RD_ARUSER_31_11_VAL_SHIFT 0
+#define DMA0_CORE_RD_ARUSER_31_11_VAL_MASK 0x1FFFFF
+
+/* DMA0_CORE_RD_INFLIGHTS */
+#define DMA0_CORE_RD_INFLIGHTS_VAL_SHIFT 0
+#define DMA0_CORE_RD_INFLIGHTS_VAL_MASK 0xFFFFFFFF
+
+/* DMA0_CORE_WR_MAX_OUTSTAND */
+#define DMA0_CORE_WR_MAX_OUTSTAND_VAL_SHIFT 0
+#define DMA0_CORE_WR_MAX_OUTSTAND_VAL_MASK 0xFFF
+
+/* DMA0_CORE_WR_MAX_AWID */
+#define DMA0_CORE_WR_MAX_AWID_VAL_SHIFT 0
+#define DMA0_CORE_WR_MAX_AWID_VAL_MASK 0xFFFF
+
+/* DMA0_CORE_WR_AWCACHE */
+#define DMA0_CORE_WR_AWCACHE_VAL_SHIFT 0
+#define DMA0_CORE_WR_AWCACHE_VAL_MASK 0xF
+
+/* DMA0_CORE_WR_AWUSER_31_11 */
+#define DMA0_CORE_WR_AWUSER_31_11_VAL_SHIFT 0
+#define DMA0_CORE_WR_AWUSER_31_11_VAL_MASK 0x1FFFFF
+
+/* DMA0_CORE_WR_INFLIGHTS */
+#define DMA0_CORE_WR_INFLIGHTS_VAL_SHIFT 0
+#define DMA0_CORE_WR_INFLIGHTS_VAL_MASK 0xFFFF
+
+/* DMA0_CORE_RD_RATE_LIM_CFG_0 */
+#define DMA0_CORE_RD_RATE_LIM_CFG_0_RST_TOKEN_SHIFT 0
+#define DMA0_CORE_RD_RATE_LIM_CFG_0_RST_TOKEN_MASK 0xFF
+#define DMA0_CORE_RD_RATE_LIM_CFG_0_SAT_SHIFT 16
+#define DMA0_CORE_RD_RATE_LIM_CFG_0_SAT_MASK 0xFF0000
+
+/* DMA0_CORE_RD_RATE_LIM_CFG_1 */
+#define DMA0_CORE_RD_RATE_LIM_CFG_1_TOUT_SHIFT 0
+#define DMA0_CORE_RD_RATE_LIM_CFG_1_TOUT_MASK 0xFF
+#define DMA0_CORE_RD_RATE_LIM_CFG_1_EN_SHIFT 31
+#define DMA0_CORE_RD_RATE_LIM_CFG_1_EN_MASK 0x80000000
+
+/* DMA0_CORE_WR_RATE_LIM_CFG_0 */
+#define DMA0_CORE_WR_RATE_LIM_CFG_0_RST_TOKEN_SHIFT 0
+#define DMA0_CORE_WR_RATE_LIM_CFG_0_RST_TOKEN_MASK 0xFF
+#define DMA0_CORE_WR_RATE_LIM_CFG_0_SAT_SHIFT 16
+#define DMA0_CORE_WR_RATE_LIM_CFG_0_SAT_MASK 0xFF0000
+
+/* DMA0_CORE_WR_RATE_LIM_CFG_1 */
+#define DMA0_CORE_WR_RATE_LIM_CFG_1_TOUT_SHIFT 0
+#define DMA0_CORE_WR_RATE_LIM_CFG_1_TOUT_MASK 0xFF
+#define DMA0_CORE_WR_RATE_LIM_CFG_1_EN_SHIFT 31
+#define DMA0_CORE_WR_RATE_LIM_CFG_1_EN_MASK 0x80000000
+
+/* DMA0_CORE_ERR_CFG */
+#define DMA0_CORE_ERR_CFG_ERR_MSG_EN_SHIFT 0
+#define DMA0_CORE_ERR_CFG_ERR_MSG_EN_MASK 0x1
+#define DMA0_CORE_ERR_CFG_STOP_ON_ERR_SHIFT 1
+#define DMA0_CORE_ERR_CFG_STOP_ON_ERR_MASK 0x2
+
+/* DMA0_CORE_ERR_CAUSE */
+#define DMA0_CORE_ERR_CAUSE_HBW_RD_ERR_SHIFT 0
+#define DMA0_CORE_ERR_CAUSE_HBW_RD_ERR_MASK 0x1
+#define DMA0_CORE_ERR_CAUSE_HBW_WR_ERR_SHIFT 1
+#define DMA0_CORE_ERR_CAUSE_HBW_WR_ERR_MASK 0x2
+#define DMA0_CORE_ERR_CAUSE_LBW_WR_ERR_SHIFT 2
+#define DMA0_CORE_ERR_CAUSE_LBW_WR_ERR_MASK 0x4
+#define DMA0_CORE_ERR_CAUSE_DESC_OVF_SHIFT 3
+#define DMA0_CORE_ERR_CAUSE_DESC_OVF_MASK 0x8
+
+/* DMA0_CORE_ERRMSG_ADDR_LO */
+#define DMA0_CORE_ERRMSG_ADDR_LO_VAL_SHIFT 0
+#define DMA0_CORE_ERRMSG_ADDR_LO_VAL_MASK 0xFFFFFFFF
+
+/* DMA0_CORE_ERRMSG_ADDR_HI */
+#define DMA0_CORE_ERRMSG_ADDR_HI_VAL_SHIFT 0
+#define DMA0_CORE_ERRMSG_ADDR_HI_VAL_MASK 0xFFFFFFFF
+
+/* DMA0_CORE_ERRMSG_WDATA */
+#define DMA0_CORE_ERRMSG_WDATA_VAL_SHIFT 0
+#define DMA0_CORE_ERRMSG_WDATA_VAL_MASK 0xFFFFFFFF
+
+/* DMA0_CORE_STS0 */
+#define DMA0_CORE_STS0_RD_REQ_CNT_SHIFT 0
+#define DMA0_CORE_STS0_RD_REQ_CNT_MASK 0x7FFF
+#define DMA0_CORE_STS0_WR_REQ_CNT_SHIFT 16
+#define DMA0_CORE_STS0_WR_REQ_CNT_MASK 0x7FFF0000
+#define DMA0_CORE_STS0_BUSY_SHIFT 31
+#define DMA0_CORE_STS0_BUSY_MASK 0x80000000
+
+/* DMA0_CORE_STS1 */
+#define DMA0_CORE_STS1_IS_HALT_SHIFT 0
+#define DMA0_CORE_STS1_IS_HALT_MASK 0x1
+
+/* DMA0_CORE_RD_DBGMEM_ADD */
+#define DMA0_CORE_RD_DBGMEM_ADD_VAL_SHIFT 0
+#define DMA0_CORE_RD_DBGMEM_ADD_VAL_MASK 0xFFFFFFFF
+
+/* DMA0_CORE_RD_DBGMEM_DATA_WR */
+#define DMA0_CORE_RD_DBGMEM_DATA_WR_VAL_SHIFT 0
+#define DMA0_CORE_RD_DBGMEM_DATA_WR_VAL_MASK 0xFFFFFFFF
+
+/* DMA0_CORE_RD_DBGMEM_DATA_RD */
+#define DMA0_CORE_RD_DBGMEM_DATA_RD_VAL_SHIFT 0
+#define DMA0_CORE_RD_DBGMEM_DATA_RD_VAL_MASK 0xFFFFFFFF
+
+/* DMA0_CORE_RD_DBGMEM_CTRL */
+#define DMA0_CORE_RD_DBGMEM_CTRL_WR_NRD_SHIFT 0
+#define DMA0_CORE_RD_DBGMEM_CTRL_WR_NRD_MASK 0x1
+
+/* DMA0_CORE_RD_DBGMEM_RC */
+#define DMA0_CORE_RD_DBGMEM_RC_VALID_SHIFT 0
+#define DMA0_CORE_RD_DBGMEM_RC_VALID_MASK 0x1
+
+/* DMA0_CORE_DBG_HBW_AXI_AR_CNT */
+
+/* DMA0_CORE_DBG_HBW_AXI_AW_CNT */
+
+/* DMA0_CORE_DBG_LBW_AXI_AW_CNT */
+
+/* DMA0_CORE_DBG_DESC_CNT */
+#define DMA0_CORE_DBG_DESC_CNT_RD_STS_CTX_CNT_SHIFT 0
+#define DMA0_CORE_DBG_DESC_CNT_RD_STS_CTX_CNT_MASK 0xFFFFFFFF
+
+/* DMA0_CORE_DBG_STS */
+#define DMA0_CORE_DBG_STS_RD_CTX_FULL_SHIFT 0
+#define DMA0_CORE_DBG_STS_RD_CTX_FULL_MASK 0x1
+#define DMA0_CORE_DBG_STS_WR_CTX_FULL_SHIFT 1
+#define DMA0_CORE_DBG_STS_WR_CTX_FULL_MASK 0x2
+#define DMA0_CORE_DBG_STS_WR_COMP_FULL_SHIFT 2
+#define DMA0_CORE_DBG_STS_WR_COMP_FULL_MASK 0x4
+#define DMA0_CORE_DBG_STS_RD_CTX_EMPTY_SHIFT 3
+#define DMA0_CORE_DBG_STS_RD_CTX_EMPTY_MASK 0x8
+#define DMA0_CORE_DBG_STS_WR_CTX_EMPTY_SHIFT 4
+#define DMA0_CORE_DBG_STS_WR_CTX_EMPTY_MASK 0x10
+#define DMA0_CORE_DBG_STS_WR_COMP_EMPTY_SHIFT 5
+#define DMA0_CORE_DBG_STS_WR_COMP_EMPTY_MASK 0x20
+#define DMA0_CORE_DBG_STS_TE_EMPTY_SHIFT 6
+#define DMA0_CORE_DBG_STS_TE_EMPTY_MASK 0x40
+#define DMA0_CORE_DBG_STS_TE_BUSY_SHIFT 7
+#define DMA0_CORE_DBG_STS_TE_BUSY_MASK 0x80
+#define DMA0_CORE_DBG_STS_GSKT_EMPTY_SHIFT 8
+#define DMA0_CORE_DBG_STS_GSKT_EMPTY_MASK 0x100
+#define DMA0_CORE_DBG_STS_GSKT_FULL_SHIFT 9
+#define DMA0_CORE_DBG_STS_GSKT_FULL_MASK 0x200
+#define DMA0_CORE_DBG_STS_RDBUF_FULLNESS_SHIFT 20
+#define DMA0_CORE_DBG_STS_RDBUF_FULLNESS_MASK 0x7FF00000
+
+/* DMA0_CORE_DBG_RD_DESC_ID */
+
+/* DMA0_CORE_DBG_WR_DESC_ID */
+
+#endif /* ASIC_REG_DMA0_CORE_MASKS_H_ */
diff --git a/drivers/accel/habanalabs/include/gaudi/asic_reg/dma0_core_regs.h b/drivers/accel/habanalabs/include/gaudi/asic_reg/dma0_core_regs.h
new file mode 100644
index 0000000000..1fdd5d5fc6
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi/asic_reg/dma0_core_regs.h
@@ -0,0 +1,156 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2016-2018 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ ** DO NOT EDIT BELOW **
+ ************************************/
+
+#ifndef ASIC_REG_DMA0_CORE_REGS_H_
+#define ASIC_REG_DMA0_CORE_REGS_H_
+
+/*
+ *****************************************
+ * DMA0_CORE (Prototype: DMA_CORE)
+ *****************************************
+ */
+
+#define mmDMA0_CORE_CFG_0 0x500000
+
+#define mmDMA0_CORE_CFG_1 0x500004
+
+#define mmDMA0_CORE_LBW_MAX_OUTSTAND 0x500008
+
+#define mmDMA0_CORE_SRC_BASE_LO 0x500014
+
+#define mmDMA0_CORE_SRC_BASE_HI 0x500018
+
+#define mmDMA0_CORE_DST_BASE_LO 0x50001C
+
+#define mmDMA0_CORE_DST_BASE_HI 0x500020
+
+#define mmDMA0_CORE_SRC_TSIZE_1 0x50002C
+
+#define mmDMA0_CORE_SRC_STRIDE_1 0x500030
+
+#define mmDMA0_CORE_SRC_TSIZE_2 0x500034
+
+#define mmDMA0_CORE_SRC_STRIDE_2 0x500038
+
+#define mmDMA0_CORE_SRC_TSIZE_3 0x50003C
+
+#define mmDMA0_CORE_SRC_STRIDE_3 0x500040
+
+#define mmDMA0_CORE_SRC_TSIZE_4 0x500044
+
+#define mmDMA0_CORE_SRC_STRIDE_4 0x500048
+
+#define mmDMA0_CORE_SRC_TSIZE_0 0x50004C
+
+#define mmDMA0_CORE_DST_TSIZE_1 0x500054
+
+#define mmDMA0_CORE_DST_STRIDE_1 0x500058
+
+#define mmDMA0_CORE_DST_TSIZE_2 0x50005C
+
+#define mmDMA0_CORE_DST_STRIDE_2 0x500060
+
+#define mmDMA0_CORE_DST_TSIZE_3 0x500064
+
+#define mmDMA0_CORE_DST_STRIDE_3 0x500068
+
+#define mmDMA0_CORE_DST_TSIZE_4 0x50006C
+
+#define mmDMA0_CORE_DST_STRIDE_4 0x500070
+
+#define mmDMA0_CORE_DST_TSIZE_0 0x500074
+
+#define mmDMA0_CORE_COMMIT 0x500078
+
+#define mmDMA0_CORE_WR_COMP_WDATA 0x50007C
+
+#define mmDMA0_CORE_WR_COMP_ADDR_LO 0x500080
+
+#define mmDMA0_CORE_WR_COMP_ADDR_HI 0x500084
+
+#define mmDMA0_CORE_WR_COMP_AWUSER_31_11 0x500088
+
+#define mmDMA0_CORE_TE_NUMROWS 0x500094
+
+#define mmDMA0_CORE_PROT 0x5000B8
+
+#define mmDMA0_CORE_SECURE_PROPS 0x5000F0
+
+#define mmDMA0_CORE_NON_SECURE_PROPS 0x5000F4
+
+#define mmDMA0_CORE_RD_MAX_OUTSTAND 0x500100
+
+#define mmDMA0_CORE_RD_MAX_SIZE 0x500104
+
+#define mmDMA0_CORE_RD_ARCACHE 0x500108
+
+#define mmDMA0_CORE_RD_ARUSER_31_11 0x500110
+
+#define mmDMA0_CORE_RD_INFLIGHTS 0x500114
+
+#define mmDMA0_CORE_WR_MAX_OUTSTAND 0x500120
+
+#define mmDMA0_CORE_WR_MAX_AWID 0x500124
+
+#define mmDMA0_CORE_WR_AWCACHE 0x500128
+
+#define mmDMA0_CORE_WR_AWUSER_31_11 0x500130
+
+#define mmDMA0_CORE_WR_INFLIGHTS 0x500134
+
+#define mmDMA0_CORE_RD_RATE_LIM_CFG_0 0x500150
+
+#define mmDMA0_CORE_RD_RATE_LIM_CFG_1 0x500154
+
+#define mmDMA0_CORE_WR_RATE_LIM_CFG_0 0x500158
+
+#define mmDMA0_CORE_WR_RATE_LIM_CFG_1 0x50015C
+
+#define mmDMA0_CORE_ERR_CFG 0x500160
+
+#define mmDMA0_CORE_ERR_CAUSE 0x500164
+
+#define mmDMA0_CORE_ERRMSG_ADDR_LO 0x500170
+
+#define mmDMA0_CORE_ERRMSG_ADDR_HI 0x500174
+
+#define mmDMA0_CORE_ERRMSG_WDATA 0x500178
+
+#define mmDMA0_CORE_STS0 0x500190
+
+#define mmDMA0_CORE_STS1 0x500194
+
+#define mmDMA0_CORE_RD_DBGMEM_ADD 0x500200
+
+#define mmDMA0_CORE_RD_DBGMEM_DATA_WR 0x500204
+
+#define mmDMA0_CORE_RD_DBGMEM_DATA_RD 0x500208
+
+#define mmDMA0_CORE_RD_DBGMEM_CTRL 0x50020C
+
+#define mmDMA0_CORE_RD_DBGMEM_RC 0x500210
+
+#define mmDMA0_CORE_DBG_HBW_AXI_AR_CNT 0x500220
+
+#define mmDMA0_CORE_DBG_HBW_AXI_AW_CNT 0x500224
+
+#define mmDMA0_CORE_DBG_LBW_AXI_AW_CNT 0x500228
+
+#define mmDMA0_CORE_DBG_DESC_CNT 0x50022C
+
+#define mmDMA0_CORE_DBG_STS 0x500230
+
+#define mmDMA0_CORE_DBG_RD_DESC_ID 0x500234
+
+#define mmDMA0_CORE_DBG_WR_DESC_ID 0x500238
+
+#endif /* ASIC_REG_DMA0_CORE_REGS_H_ */
diff --git a/drivers/accel/habanalabs/include/gaudi/asic_reg/dma0_qm_masks.h b/drivers/accel/habanalabs/include/gaudi/asic_reg/dma0_qm_masks.h
new file mode 100644
index 0000000000..48376aabc3
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi/asic_reg/dma0_qm_masks.h
@@ -0,0 +1,800 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2016-2018 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ ** DO NOT EDIT BELOW **
+ ************************************/
+
+#ifndef ASIC_REG_DMA0_QM_MASKS_H_
+#define ASIC_REG_DMA0_QM_MASKS_H_
+
+/*
+ *****************************************
+ * DMA0_QM (Prototype: QMAN)
+ *****************************************
+ */
+
+/* DMA0_QM_GLBL_CFG0 */
+#define DMA0_QM_GLBL_CFG0_PQF_EN_SHIFT 0
+#define DMA0_QM_GLBL_CFG0_PQF_EN_MASK 0xF
+#define DMA0_QM_GLBL_CFG0_CQF_EN_SHIFT 4
+#define DMA0_QM_GLBL_CFG0_CQF_EN_MASK 0x1F0
+#define DMA0_QM_GLBL_CFG0_CP_EN_SHIFT 9
+#define DMA0_QM_GLBL_CFG0_CP_EN_MASK 0x3E00
+
+/* DMA0_QM_GLBL_CFG1 */
+#define DMA0_QM_GLBL_CFG1_PQF_STOP_SHIFT 0
+#define DMA0_QM_GLBL_CFG1_PQF_STOP_MASK 0xF
+#define DMA0_QM_GLBL_CFG1_CQF_STOP_SHIFT 4
+#define DMA0_QM_GLBL_CFG1_CQF_STOP_MASK 0x1F0
+#define DMA0_QM_GLBL_CFG1_CP_STOP_SHIFT 9
+#define DMA0_QM_GLBL_CFG1_CP_STOP_MASK 0x3E00
+#define DMA0_QM_GLBL_CFG1_PQF_FLUSH_SHIFT 16
+#define DMA0_QM_GLBL_CFG1_PQF_FLUSH_MASK 0xF0000
+#define DMA0_QM_GLBL_CFG1_CQF_FLUSH_SHIFT 20
+#define DMA0_QM_GLBL_CFG1_CQF_FLUSH_MASK 0x1F00000
+#define DMA0_QM_GLBL_CFG1_CP_FLUSH_SHIFT 25
+#define DMA0_QM_GLBL_CFG1_CP_FLUSH_MASK 0x3E000000
+
+/* DMA0_QM_GLBL_PROT */
+#define DMA0_QM_GLBL_PROT_PQF_SHIFT 0
+#define DMA0_QM_GLBL_PROT_PQF_MASK 0xF
+#define DMA0_QM_GLBL_PROT_CQF_SHIFT 4
+#define DMA0_QM_GLBL_PROT_CQF_MASK 0x1F0
+#define DMA0_QM_GLBL_PROT_CP_SHIFT 9
+#define DMA0_QM_GLBL_PROT_CP_MASK 0x3E00
+#define DMA0_QM_GLBL_PROT_ERR_SHIFT 14
+#define DMA0_QM_GLBL_PROT_ERR_MASK 0x4000
+#define DMA0_QM_GLBL_PROT_ARB_SHIFT 15
+#define DMA0_QM_GLBL_PROT_ARB_MASK 0x8000
+
+/* DMA0_QM_GLBL_ERR_CFG */
+#define DMA0_QM_GLBL_ERR_CFG_PQF_ERR_MSG_EN_SHIFT 0
+#define DMA0_QM_GLBL_ERR_CFG_PQF_ERR_MSG_EN_MASK 0xF
+#define DMA0_QM_GLBL_ERR_CFG_CQF_ERR_MSG_EN_SHIFT 4
+#define DMA0_QM_GLBL_ERR_CFG_CQF_ERR_MSG_EN_MASK 0x1F0
+#define DMA0_QM_GLBL_ERR_CFG_CP_ERR_MSG_EN_SHIFT 9
+#define DMA0_QM_GLBL_ERR_CFG_CP_ERR_MSG_EN_MASK 0x3E00
+#define DMA0_QM_GLBL_ERR_CFG_PQF_STOP_ON_ERR_SHIFT 16
+#define DMA0_QM_GLBL_ERR_CFG_PQF_STOP_ON_ERR_MASK 0xF0000
+#define DMA0_QM_GLBL_ERR_CFG_CQF_STOP_ON_ERR_SHIFT 20
+#define DMA0_QM_GLBL_ERR_CFG_CQF_STOP_ON_ERR_MASK 0x1F00000
+#define DMA0_QM_GLBL_ERR_CFG_CP_STOP_ON_ERR_SHIFT 25
+#define DMA0_QM_GLBL_ERR_CFG_CP_STOP_ON_ERR_MASK 0x3E000000
+#define DMA0_QM_GLBL_ERR_CFG_ARB_STOP_ON_ERR_SHIFT 31
+#define DMA0_QM_GLBL_ERR_CFG_ARB_STOP_ON_ERR_MASK 0x80000000
+
+/* DMA0_QM_GLBL_SECURE_PROPS */
+#define DMA0_QM_GLBL_SECURE_PROPS_0_ASID_SHIFT 0
+#define DMA0_QM_GLBL_SECURE_PROPS_0_ASID_MASK 0x3FF
+#define DMA0_QM_GLBL_SECURE_PROPS_1_ASID_SHIFT 0
+#define DMA0_QM_GLBL_SECURE_PROPS_1_ASID_MASK 0x3FF
+#define DMA0_QM_GLBL_SECURE_PROPS_2_ASID_SHIFT 0
+#define DMA0_QM_GLBL_SECURE_PROPS_2_ASID_MASK 0x3FF
+#define DMA0_QM_GLBL_SECURE_PROPS_3_ASID_SHIFT 0
+#define DMA0_QM_GLBL_SECURE_PROPS_3_ASID_MASK 0x3FF
+#define DMA0_QM_GLBL_SECURE_PROPS_4_ASID_SHIFT 0
+#define DMA0_QM_GLBL_SECURE_PROPS_4_ASID_MASK 0x3FF
+#define DMA0_QM_GLBL_SECURE_PROPS_0_MMBP_SHIFT 10
+#define DMA0_QM_GLBL_SECURE_PROPS_0_MMBP_MASK 0x400
+#define DMA0_QM_GLBL_SECURE_PROPS_1_MMBP_SHIFT 10
+#define DMA0_QM_GLBL_SECURE_PROPS_1_MMBP_MASK 0x400
+#define DMA0_QM_GLBL_SECURE_PROPS_2_MMBP_SHIFT 10
+#define DMA0_QM_GLBL_SECURE_PROPS_2_MMBP_MASK 0x400
+#define DMA0_QM_GLBL_SECURE_PROPS_3_MMBP_SHIFT 10
+#define DMA0_QM_GLBL_SECURE_PROPS_3_MMBP_MASK 0x400
+#define DMA0_QM_GLBL_SECURE_PROPS_4_MMBP_SHIFT 10
+#define DMA0_QM_GLBL_SECURE_PROPS_4_MMBP_MASK 0x400
+
+/* DMA0_QM_GLBL_NON_SECURE_PROPS */
+#define DMA0_QM_GLBL_NON_SECURE_PROPS_0_ASID_SHIFT 0
+#define DMA0_QM_GLBL_NON_SECURE_PROPS_0_ASID_MASK 0x3FF
+#define DMA0_QM_GLBL_NON_SECURE_PROPS_1_ASID_SHIFT 0
+#define DMA0_QM_GLBL_NON_SECURE_PROPS_1_ASID_MASK 0x3FF
+#define DMA0_QM_GLBL_NON_SECURE_PROPS_2_ASID_SHIFT 0
+#define DMA0_QM_GLBL_NON_SECURE_PROPS_2_ASID_MASK 0x3FF
+#define DMA0_QM_GLBL_NON_SECURE_PROPS_3_ASID_SHIFT 0
+#define DMA0_QM_GLBL_NON_SECURE_PROPS_3_ASID_MASK 0x3FF
+#define DMA0_QM_GLBL_NON_SECURE_PROPS_4_ASID_SHIFT 0
+#define DMA0_QM_GLBL_NON_SECURE_PROPS_4_ASID_MASK 0x3FF
+#define DMA0_QM_GLBL_NON_SECURE_PROPS_0_MMBP_SHIFT 10
+#define DMA0_QM_GLBL_NON_SECURE_PROPS_0_MMBP_MASK 0x400
+#define DMA0_QM_GLBL_NON_SECURE_PROPS_1_MMBP_SHIFT 10
+#define DMA0_QM_GLBL_NON_SECURE_PROPS_1_MMBP_MASK 0x400
+#define DMA0_QM_GLBL_NON_SECURE_PROPS_2_MMBP_SHIFT 10
+#define DMA0_QM_GLBL_NON_SECURE_PROPS_2_MMBP_MASK 0x400
+#define DMA0_QM_GLBL_NON_SECURE_PROPS_3_MMBP_SHIFT 10
+#define DMA0_QM_GLBL_NON_SECURE_PROPS_3_MMBP_MASK 0x400
+#define DMA0_QM_GLBL_NON_SECURE_PROPS_4_MMBP_SHIFT 10
+#define DMA0_QM_GLBL_NON_SECURE_PROPS_4_MMBP_MASK 0x400
+
+/* DMA0_QM_GLBL_STS0 */
+#define DMA0_QM_GLBL_STS0_PQF_IDLE_SHIFT 0
+#define DMA0_QM_GLBL_STS0_PQF_IDLE_MASK 0xF
+#define DMA0_QM_GLBL_STS0_CQF_IDLE_SHIFT 4
+#define DMA0_QM_GLBL_STS0_CQF_IDLE_MASK 0x1F0
+#define DMA0_QM_GLBL_STS0_CP_IDLE_SHIFT 9
+#define DMA0_QM_GLBL_STS0_CP_IDLE_MASK 0x3E00
+#define DMA0_QM_GLBL_STS0_PQF_IS_STOP_SHIFT 16
+#define DMA0_QM_GLBL_STS0_PQF_IS_STOP_MASK 0xF0000
+#define DMA0_QM_GLBL_STS0_CQF_IS_STOP_SHIFT 20
+#define DMA0_QM_GLBL_STS0_CQF_IS_STOP_MASK 0x1F00000
+#define DMA0_QM_GLBL_STS0_CP_IS_STOP_SHIFT 25
+#define DMA0_QM_GLBL_STS0_CP_IS_STOP_MASK 0x3E000000
+#define DMA0_QM_GLBL_STS0_ARB_IS_STOP_SHIFT 31
+#define DMA0_QM_GLBL_STS0_ARB_IS_STOP_MASK 0x80000000
+
+/* DMA0_QM_GLBL_STS1 */
+#define DMA0_QM_GLBL_STS1_PQF_RD_ERR_SHIFT 0
+#define DMA0_QM_GLBL_STS1_PQF_RD_ERR_MASK 0x1
+#define DMA0_QM_GLBL_STS1_CQF_RD_ERR_SHIFT 1
+#define DMA0_QM_GLBL_STS1_CQF_RD_ERR_MASK 0x2
+#define DMA0_QM_GLBL_STS1_CP_RD_ERR_SHIFT 2
+#define DMA0_QM_GLBL_STS1_CP_RD_ERR_MASK 0x4
+#define DMA0_QM_GLBL_STS1_CP_UNDEF_CMD_ERR_SHIFT 3
+#define DMA0_QM_GLBL_STS1_CP_UNDEF_CMD_ERR_MASK 0x8
+#define DMA0_QM_GLBL_STS1_CP_STOP_OP_SHIFT 4
+#define DMA0_QM_GLBL_STS1_CP_STOP_OP_MASK 0x10
+#define DMA0_QM_GLBL_STS1_CP_MSG_WR_ERR_SHIFT 5
+#define DMA0_QM_GLBL_STS1_CP_MSG_WR_ERR_MASK 0x20
+#define DMA0_QM_GLBL_STS1_CP_WREG_ERR_SHIFT 6
+#define DMA0_QM_GLBL_STS1_CP_WREG_ERR_MASK 0x40
+#define DMA0_QM_GLBL_STS1_CP_FENCE0_OVF_ERR_SHIFT 8
+#define DMA0_QM_GLBL_STS1_CP_FENCE0_OVF_ERR_MASK 0x100
+#define DMA0_QM_GLBL_STS1_CP_FENCE1_OVF_ERR_SHIFT 9
+#define DMA0_QM_GLBL_STS1_CP_FENCE1_OVF_ERR_MASK 0x200
+#define DMA0_QM_GLBL_STS1_CP_FENCE2_OVF_ERR_SHIFT 10
+#define DMA0_QM_GLBL_STS1_CP_FENCE2_OVF_ERR_MASK 0x400
+#define DMA0_QM_GLBL_STS1_CP_FENCE3_OVF_ERR_SHIFT 11
+#define DMA0_QM_GLBL_STS1_CP_FENCE3_OVF_ERR_MASK 0x800
+#define DMA0_QM_GLBL_STS1_CP_FENCE0_UDF_ERR_SHIFT 12
+#define DMA0_QM_GLBL_STS1_CP_FENCE0_UDF_ERR_MASK 0x1000
+#define DMA0_QM_GLBL_STS1_CP_FENCE1_UDF_ERR_SHIFT 13
+#define DMA0_QM_GLBL_STS1_CP_FENCE1_UDF_ERR_MASK 0x2000
+#define DMA0_QM_GLBL_STS1_CP_FENCE2_UDF_ERR_SHIFT 14
+#define DMA0_QM_GLBL_STS1_CP_FENCE2_UDF_ERR_MASK 0x4000
+#define DMA0_QM_GLBL_STS1_CP_FENCE3_UDF_ERR_SHIFT 15
+#define DMA0_QM_GLBL_STS1_CP_FENCE3_UDF_ERR_MASK 0x8000
+
+/* DMA0_QM_GLBL_STS1_4 */
+#define DMA0_QM_GLBL_STS1_4_CQF_RD_ERR_SHIFT 1
+#define DMA0_QM_GLBL_STS1_4_CQF_RD_ERR_MASK 0x2
+#define DMA0_QM_GLBL_STS1_4_CP_RD_ERR_SHIFT 2
+#define DMA0_QM_GLBL_STS1_4_CP_RD_ERR_MASK 0x4
+#define DMA0_QM_GLBL_STS1_4_CP_UNDEF_CMD_ERR_SHIFT 3
+#define DMA0_QM_GLBL_STS1_4_CP_UNDEF_CMD_ERR_MASK 0x8
+#define DMA0_QM_GLBL_STS1_4_CP_STOP_OP_SHIFT 4
+#define DMA0_QM_GLBL_STS1_4_CP_STOP_OP_MASK 0x10
+#define DMA0_QM_GLBL_STS1_4_CP_MSG_WR_ERR_SHIFT 5
+#define DMA0_QM_GLBL_STS1_4_CP_MSG_WR_ERR_MASK 0x20
+#define DMA0_QM_GLBL_STS1_4_CP_WREG_ERR_SHIFT 6
+#define DMA0_QM_GLBL_STS1_4_CP_WREG_ERR_MASK 0x40
+#define DMA0_QM_GLBL_STS1_4_CP_FENCE0_OVF_ERR_SHIFT 8
+#define DMA0_QM_GLBL_STS1_4_CP_FENCE0_OVF_ERR_MASK 0x100
+#define DMA0_QM_GLBL_STS1_4_CP_FENCE1_OVF_ERR_SHIFT 9
+#define DMA0_QM_GLBL_STS1_4_CP_FENCE1_OVF_ERR_MASK 0x200
+#define DMA0_QM_GLBL_STS1_4_CP_FENCE2_OVF_ERR_SHIFT 10
+#define DMA0_QM_GLBL_STS1_4_CP_FENCE2_OVF_ERR_MASK 0x400
+#define DMA0_QM_GLBL_STS1_4_CP_FENCE3_OVF_ERR_SHIFT 11
+#define DMA0_QM_GLBL_STS1_4_CP_FENCE3_OVF_ERR_MASK 0x800
+#define DMA0_QM_GLBL_STS1_4_CP_FENCE0_UDF_ERR_SHIFT 12
+#define DMA0_QM_GLBL_STS1_4_CP_FENCE0_UDF_ERR_MASK 0x1000
+#define DMA0_QM_GLBL_STS1_4_CP_FENCE1_UDF_ERR_SHIFT 13
+#define DMA0_QM_GLBL_STS1_4_CP_FENCE1_UDF_ERR_MASK 0x2000
+#define DMA0_QM_GLBL_STS1_4_CP_FENCE2_UDF_ERR_SHIFT 14
+#define DMA0_QM_GLBL_STS1_4_CP_FENCE2_UDF_ERR_MASK 0x4000
+#define DMA0_QM_GLBL_STS1_4_CP_FENCE3_UDF_ERR_SHIFT 15
+#define DMA0_QM_GLBL_STS1_4_CP_FENCE3_UDF_ERR_MASK 0x8000
+
+/* DMA0_QM_GLBL_MSG_EN */
+#define DMA0_QM_GLBL_MSG_EN_PQF_RD_ERR_SHIFT 0
+#define DMA0_QM_GLBL_MSG_EN_PQF_RD_ERR_MASK 0x1
+#define DMA0_QM_GLBL_MSG_EN_CQF_RD_ERR_SHIFT 1
+#define DMA0_QM_GLBL_MSG_EN_CQF_RD_ERR_MASK 0x2
+#define DMA0_QM_GLBL_MSG_EN_CP_RD_ERR_SHIFT 2
+#define DMA0_QM_GLBL_MSG_EN_CP_RD_ERR_MASK 0x4
+#define DMA0_QM_GLBL_MSG_EN_CP_UNDEF_CMD_ERR_SHIFT 3
+#define DMA0_QM_GLBL_MSG_EN_CP_UNDEF_CMD_ERR_MASK 0x8
+#define DMA0_QM_GLBL_MSG_EN_CP_STOP_OP_SHIFT 4
+#define DMA0_QM_GLBL_MSG_EN_CP_STOP_OP_MASK 0x10
+#define DMA0_QM_GLBL_MSG_EN_CP_MSG_WR_ERR_SHIFT 5
+#define DMA0_QM_GLBL_MSG_EN_CP_MSG_WR_ERR_MASK 0x20
+#define DMA0_QM_GLBL_MSG_EN_CP_WREG_ERR_SHIFT 6
+#define DMA0_QM_GLBL_MSG_EN_CP_WREG_ERR_MASK 0x40
+#define DMA0_QM_GLBL_MSG_EN_CP_FENCE0_OVF_ERR_SHIFT 8
+#define DMA0_QM_GLBL_MSG_EN_CP_FENCE0_OVF_ERR_MASK 0x100
+#define DMA0_QM_GLBL_MSG_EN_CP_FENCE1_OVF_ERR_SHIFT 9
+#define DMA0_QM_GLBL_MSG_EN_CP_FENCE1_OVF_ERR_MASK 0x200
+#define DMA0_QM_GLBL_MSG_EN_CP_FENCE2_OVF_ERR_SHIFT 10
+#define DMA0_QM_GLBL_MSG_EN_CP_FENCE2_OVF_ERR_MASK 0x400
+#define DMA0_QM_GLBL_MSG_EN_CP_FENCE3_OVF_ERR_SHIFT 11
+#define DMA0_QM_GLBL_MSG_EN_CP_FENCE3_OVF_ERR_MASK 0x800
+#define DMA0_QM_GLBL_MSG_EN_CP_FENCE0_UDF_ERR_SHIFT 12
+#define DMA0_QM_GLBL_MSG_EN_CP_FENCE0_UDF_ERR_MASK 0x1000
+#define DMA0_QM_GLBL_MSG_EN_CP_FENCE1_UDF_ERR_SHIFT 13
+#define DMA0_QM_GLBL_MSG_EN_CP_FENCE1_UDF_ERR_MASK 0x2000
+#define DMA0_QM_GLBL_MSG_EN_CP_FENCE2_UDF_ERR_SHIFT 14
+#define DMA0_QM_GLBL_MSG_EN_CP_FENCE2_UDF_ERR_MASK 0x4000
+#define DMA0_QM_GLBL_MSG_EN_CP_FENCE3_UDF_ERR_SHIFT 15
+#define DMA0_QM_GLBL_MSG_EN_CP_FENCE3_UDF_ERR_MASK 0x8000
+
+/* DMA0_QM_GLBL_MSG_EN_4 */
+#define DMA0_QM_GLBL_MSG_EN_4_CQF_RD_ERR_SHIFT 1
+#define DMA0_QM_GLBL_MSG_EN_4_CQF_RD_ERR_MASK 0x2
+#define DMA0_QM_GLBL_MSG_EN_4_CP_RD_ERR_SHIFT 2
+#define DMA0_QM_GLBL_MSG_EN_4_CP_RD_ERR_MASK 0x4
+#define DMA0_QM_GLBL_MSG_EN_4_CP_UNDEF_CMD_ERR_SHIFT 3
+#define DMA0_QM_GLBL_MSG_EN_4_CP_UNDEF_CMD_ERR_MASK 0x8
+#define DMA0_QM_GLBL_MSG_EN_4_CP_STOP_OP_SHIFT 4
+#define DMA0_QM_GLBL_MSG_EN_4_CP_STOP_OP_MASK 0x10
+#define DMA0_QM_GLBL_MSG_EN_4_CP_MSG_WR_ERR_SHIFT 5
+#define DMA0_QM_GLBL_MSG_EN_4_CP_MSG_WR_ERR_MASK 0x20
+#define DMA0_QM_GLBL_MSG_EN_4_CP_WREG_ERR_SHIFT 6
+#define DMA0_QM_GLBL_MSG_EN_4_CP_WREG_ERR_MASK 0x40
+#define DMA0_QM_GLBL_MSG_EN_4_CP_FENCE0_OVF_ERR_SHIFT 8
+#define DMA0_QM_GLBL_MSG_EN_4_CP_FENCE0_OVF_ERR_MASK 0x100
+#define DMA0_QM_GLBL_MSG_EN_4_CP_FENCE1_OVF_ERR_SHIFT 9
+#define DMA0_QM_GLBL_MSG_EN_4_CP_FENCE1_OVF_ERR_MASK 0x200
+#define DMA0_QM_GLBL_MSG_EN_4_CP_FENCE2_OVF_ERR_SHIFT 10
+#define DMA0_QM_GLBL_MSG_EN_4_CP_FENCE2_OVF_ERR_MASK 0x400
+#define DMA0_QM_GLBL_MSG_EN_4_CP_FENCE3_OVF_ERR_SHIFT 11
+#define DMA0_QM_GLBL_MSG_EN_4_CP_FENCE3_OVF_ERR_MASK 0x800
+#define DMA0_QM_GLBL_MSG_EN_4_CP_FENCE0_UDF_ERR_SHIFT 12
+#define DMA0_QM_GLBL_MSG_EN_4_CP_FENCE0_UDF_ERR_MASK 0x1000
+#define DMA0_QM_GLBL_MSG_EN_4_CP_FENCE1_UDF_ERR_SHIFT 13
+#define DMA0_QM_GLBL_MSG_EN_4_CP_FENCE1_UDF_ERR_MASK 0x2000
+#define DMA0_QM_GLBL_MSG_EN_4_CP_FENCE2_UDF_ERR_SHIFT 14
+#define DMA0_QM_GLBL_MSG_EN_4_CP_FENCE2_UDF_ERR_MASK 0x4000
+#define DMA0_QM_GLBL_MSG_EN_4_CP_FENCE3_UDF_ERR_SHIFT 15
+#define DMA0_QM_GLBL_MSG_EN_4_CP_FENCE3_UDF_ERR_MASK 0x8000
+
+/* DMA0_QM_PQ_BASE_LO */
+#define DMA0_QM_PQ_BASE_LO_VAL_SHIFT 0
+#define DMA0_QM_PQ_BASE_LO_VAL_MASK 0xFFFFFFFF
+
+/* DMA0_QM_PQ_BASE_HI */
+#define DMA0_QM_PQ_BASE_HI_VAL_SHIFT 0
+#define DMA0_QM_PQ_BASE_HI_VAL_MASK 0xFFFFFFFF
+
+/* DMA0_QM_PQ_SIZE */
+#define DMA0_QM_PQ_SIZE_VAL_SHIFT 0
+#define DMA0_QM_PQ_SIZE_VAL_MASK 0xFFFFFFFF
+
+/* DMA0_QM_PQ_PI */
+#define DMA0_QM_PQ_PI_VAL_SHIFT 0
+#define DMA0_QM_PQ_PI_VAL_MASK 0xFFFFFFFF
+
+/* DMA0_QM_PQ_CI */
+#define DMA0_QM_PQ_CI_VAL_SHIFT 0
+#define DMA0_QM_PQ_CI_VAL_MASK 0xFFFFFFFF
+
+/* DMA0_QM_PQ_CFG0 */
+#define DMA0_QM_PQ_CFG0_RESERVED_SHIFT 0
+#define DMA0_QM_PQ_CFG0_RESERVED_MASK 0x1
+
+/* DMA0_QM_PQ_CFG1 */
+#define DMA0_QM_PQ_CFG1_CREDIT_LIM_SHIFT 0
+#define DMA0_QM_PQ_CFG1_CREDIT_LIM_MASK 0xFFFF
+#define DMA0_QM_PQ_CFG1_MAX_INFLIGHT_SHIFT 16
+#define DMA0_QM_PQ_CFG1_MAX_INFLIGHT_MASK 0xFFFF0000
+
+/* DMA0_QM_PQ_ARUSER_31_11 */
+#define DMA0_QM_PQ_ARUSER_31_11_VAL_SHIFT 0
+#define DMA0_QM_PQ_ARUSER_31_11_VAL_MASK 0x1FFFFF
+
+/* DMA0_QM_PQ_STS0 */
+#define DMA0_QM_PQ_STS0_PQ_CREDIT_CNT_SHIFT 0
+#define DMA0_QM_PQ_STS0_PQ_CREDIT_CNT_MASK 0xFFFF
+#define DMA0_QM_PQ_STS0_PQ_FREE_CNT_SHIFT 16
+#define DMA0_QM_PQ_STS0_PQ_FREE_CNT_MASK 0xFFFF0000
+
+/* DMA0_QM_PQ_STS1 */
+#define DMA0_QM_PQ_STS1_PQ_INFLIGHT_CNT_SHIFT 0
+#define DMA0_QM_PQ_STS1_PQ_INFLIGHT_CNT_MASK 0xFFFF
+#define DMA0_QM_PQ_STS1_PQ_BUF_EMPTY_SHIFT 30
+#define DMA0_QM_PQ_STS1_PQ_BUF_EMPTY_MASK 0x40000000
+#define DMA0_QM_PQ_STS1_PQ_BUSY_SHIFT 31
+#define DMA0_QM_PQ_STS1_PQ_BUSY_MASK 0x80000000
+
+/* DMA0_QM_CQ_CFG0 */
+#define DMA0_QM_CQ_CFG0_RESERVED_SHIFT 0
+#define DMA0_QM_CQ_CFG0_RESERVED_MASK 0x1
+
+/* DMA0_QM_CQ_CFG1 */
+#define DMA0_QM_CQ_CFG1_CREDIT_LIM_SHIFT 0
+#define DMA0_QM_CQ_CFG1_CREDIT_LIM_MASK 0xFFFF
+#define DMA0_QM_CQ_CFG1_MAX_INFLIGHT_SHIFT 16
+#define DMA0_QM_CQ_CFG1_MAX_INFLIGHT_MASK 0xFFFF0000
+
+/* DMA0_QM_CQ_ARUSER_31_11 */
+#define DMA0_QM_CQ_ARUSER_31_11_VAL_SHIFT 0
+#define DMA0_QM_CQ_ARUSER_31_11_VAL_MASK 0x1FFFFF
+
+/* DMA0_QM_CQ_STS0 */
+#define DMA0_QM_CQ_STS0_CQ_CREDIT_CNT_SHIFT 0
+#define DMA0_QM_CQ_STS0_CQ_CREDIT_CNT_MASK 0xFFFF
+#define DMA0_QM_CQ_STS0_CQ_FREE_CNT_SHIFT 16
+#define DMA0_QM_CQ_STS0_CQ_FREE_CNT_MASK 0xFFFF0000
+
+/* DMA0_QM_CQ_STS1 */
+#define DMA0_QM_CQ_STS1_CQ_INFLIGHT_CNT_SHIFT 0
+#define DMA0_QM_CQ_STS1_CQ_INFLIGHT_CNT_MASK 0xFFFF
+#define DMA0_QM_CQ_STS1_CQ_BUF_EMPTY_SHIFT 30
+#define DMA0_QM_CQ_STS1_CQ_BUF_EMPTY_MASK 0x40000000
+#define DMA0_QM_CQ_STS1_CQ_BUSY_SHIFT 31
+#define DMA0_QM_CQ_STS1_CQ_BUSY_MASK 0x80000000
+
+/* DMA0_QM_CQ_PTR_LO_0 */
+#define DMA0_QM_CQ_PTR_LO_0_VAL_SHIFT 0
+#define DMA0_QM_CQ_PTR_LO_0_VAL_MASK 0xFFFFFFFF
+
+/* DMA0_QM_CQ_PTR_HI_0 */
+#define DMA0_QM_CQ_PTR_HI_0_VAL_SHIFT 0
+#define DMA0_QM_CQ_PTR_HI_0_VAL_MASK 0xFFFFFFFF
+
+/* DMA0_QM_CQ_TSIZE_0 */
+#define DMA0_QM_CQ_TSIZE_0_VAL_SHIFT 0
+#define DMA0_QM_CQ_TSIZE_0_VAL_MASK 0xFFFFFFFF
+
+/* DMA0_QM_CQ_CTL_0 */
+#define DMA0_QM_CQ_CTL_0_RPT_SHIFT 0
+#define DMA0_QM_CQ_CTL_0_RPT_MASK 0xFFFF
+#define DMA0_QM_CQ_CTL_0_CTL_SHIFT 16
+#define DMA0_QM_CQ_CTL_0_CTL_MASK 0xFFFF0000
+
+/* DMA0_QM_CQ_PTR_LO_1 */
+#define DMA0_QM_CQ_PTR_LO_1_VAL_SHIFT 0
+#define DMA0_QM_CQ_PTR_LO_1_VAL_MASK 0xFFFFFFFF
+
+/* DMA0_QM_CQ_PTR_HI_1 */
+#define DMA0_QM_CQ_PTR_HI_1_VAL_SHIFT 0
+#define DMA0_QM_CQ_PTR_HI_1_VAL_MASK 0xFFFFFFFF
+
+/* DMA0_QM_CQ_TSIZE_1 */
+#define DMA0_QM_CQ_TSIZE_1_VAL_SHIFT 0
+#define DMA0_QM_CQ_TSIZE_1_VAL_MASK 0xFFFFFFFF
+
+/* DMA0_QM_CQ_CTL_1 */
+#define DMA0_QM_CQ_CTL_1_RPT_SHIFT 0
+#define DMA0_QM_CQ_CTL_1_RPT_MASK 0xFFFF
+#define DMA0_QM_CQ_CTL_1_CTL_SHIFT 16
+#define DMA0_QM_CQ_CTL_1_CTL_MASK 0xFFFF0000
+
+/* DMA0_QM_CQ_PTR_LO_2 */
+#define DMA0_QM_CQ_PTR_LO_2_VAL_SHIFT 0
+#define DMA0_QM_CQ_PTR_LO_2_VAL_MASK 0xFFFFFFFF
+
+/* DMA0_QM_CQ_PTR_HI_2 */
+#define DMA0_QM_CQ_PTR_HI_2_VAL_SHIFT 0
+#define DMA0_QM_CQ_PTR_HI_2_VAL_MASK 0xFFFFFFFF
+
+/* DMA0_QM_CQ_TSIZE_2 */
+#define DMA0_QM_CQ_TSIZE_2_VAL_SHIFT 0
+#define DMA0_QM_CQ_TSIZE_2_VAL_MASK 0xFFFFFFFF
+
+/* DMA0_QM_CQ_CTL_2 */
+#define DMA0_QM_CQ_CTL_2_RPT_SHIFT 0
+#define DMA0_QM_CQ_CTL_2_RPT_MASK 0xFFFF
+#define DMA0_QM_CQ_CTL_2_CTL_SHIFT 16
+#define DMA0_QM_CQ_CTL_2_CTL_MASK 0xFFFF0000
+
+/* DMA0_QM_CQ_PTR_LO_3 */
+#define DMA0_QM_CQ_PTR_LO_3_VAL_SHIFT 0
+#define DMA0_QM_CQ_PTR_LO_3_VAL_MASK 0xFFFFFFFF
+
+/* DMA0_QM_CQ_PTR_HI_3 */
+#define DMA0_QM_CQ_PTR_HI_3_VAL_SHIFT 0
+#define DMA0_QM_CQ_PTR_HI_3_VAL_MASK 0xFFFFFFFF
+
+/* DMA0_QM_CQ_TSIZE_3 */
+#define DMA0_QM_CQ_TSIZE_3_VAL_SHIFT 0
+#define DMA0_QM_CQ_TSIZE_3_VAL_MASK 0xFFFFFFFF
+
+/* DMA0_QM_CQ_CTL_3 */
+#define DMA0_QM_CQ_CTL_3_RPT_SHIFT 0
+#define DMA0_QM_CQ_CTL_3_RPT_MASK 0xFFFF
+#define DMA0_QM_CQ_CTL_3_CTL_SHIFT 16
+#define DMA0_QM_CQ_CTL_3_CTL_MASK 0xFFFF0000
+
+/* DMA0_QM_CQ_PTR_LO_4 */
+#define DMA0_QM_CQ_PTR_LO_4_VAL_SHIFT 0
+#define DMA0_QM_CQ_PTR_LO_4_VAL_MASK 0xFFFFFFFF
+
+/* DMA0_QM_CQ_PTR_HI_4 */
+#define DMA0_QM_CQ_PTR_HI_4_VAL_SHIFT 0
+#define DMA0_QM_CQ_PTR_HI_4_VAL_MASK 0xFFFFFFFF
+
+/* DMA0_QM_CQ_TSIZE_4 */
+#define DMA0_QM_CQ_TSIZE_4_VAL_SHIFT 0
+#define DMA0_QM_CQ_TSIZE_4_VAL_MASK 0xFFFFFFFF
+
+/* DMA0_QM_CQ_CTL_4 */
+#define DMA0_QM_CQ_CTL_4_RPT_SHIFT 0
+#define DMA0_QM_CQ_CTL_4_RPT_MASK 0xFFFF
+#define DMA0_QM_CQ_CTL_4_CTL_SHIFT 16
+#define DMA0_QM_CQ_CTL_4_CTL_MASK 0xFFFF0000
+
+/* DMA0_QM_CQ_PTR_LO_STS */
+#define DMA0_QM_CQ_PTR_LO_STS_VAL_SHIFT 0
+#define DMA0_QM_CQ_PTR_LO_STS_VAL_MASK 0xFFFFFFFF
+
+/* DMA0_QM_CQ_PTR_HI_STS */
+#define DMA0_QM_CQ_PTR_HI_STS_VAL_SHIFT 0
+#define DMA0_QM_CQ_PTR_HI_STS_VAL_MASK 0xFFFFFFFF
+
+/* DMA0_QM_CQ_TSIZE_STS */
+#define DMA0_QM_CQ_TSIZE_STS_VAL_SHIFT 0
+#define DMA0_QM_CQ_TSIZE_STS_VAL_MASK 0xFFFFFFFF
+
+/* DMA0_QM_CQ_CTL_STS */
+#define DMA0_QM_CQ_CTL_STS_RPT_SHIFT 0
+#define DMA0_QM_CQ_CTL_STS_RPT_MASK 0xFFFF
+#define DMA0_QM_CQ_CTL_STS_CTL_SHIFT 16
+#define DMA0_QM_CQ_CTL_STS_CTL_MASK 0xFFFF0000
+
+/* DMA0_QM_CQ_IFIFO_CNT */
+#define DMA0_QM_CQ_IFIFO_CNT_VAL_SHIFT 0
+#define DMA0_QM_CQ_IFIFO_CNT_VAL_MASK 0x3
+
+/* DMA0_QM_CP_MSG_BASE0_ADDR_LO */
+#define DMA0_QM_CP_MSG_BASE0_ADDR_LO_VAL_SHIFT 0
+#define DMA0_QM_CP_MSG_BASE0_ADDR_LO_VAL_MASK 0xFFFFFFFF
+
+/* DMA0_QM_CP_MSG_BASE0_ADDR_HI */
+#define DMA0_QM_CP_MSG_BASE0_ADDR_HI_VAL_SHIFT 0
+#define DMA0_QM_CP_MSG_BASE0_ADDR_HI_VAL_MASK 0xFFFFFFFF
+
+/* DMA0_QM_CP_MSG_BASE1_ADDR_LO */
+#define DMA0_QM_CP_MSG_BASE1_ADDR_LO_VAL_SHIFT 0
+#define DMA0_QM_CP_MSG_BASE1_ADDR_LO_VAL_MASK 0xFFFFFFFF
+
+/* DMA0_QM_CP_MSG_BASE1_ADDR_HI */
+#define DMA0_QM_CP_MSG_BASE1_ADDR_HI_VAL_SHIFT 0
+#define DMA0_QM_CP_MSG_BASE1_ADDR_HI_VAL_MASK 0xFFFFFFFF
+
+/* DMA0_QM_CP_MSG_BASE2_ADDR_LO */
+#define DMA0_QM_CP_MSG_BASE2_ADDR_LO_VAL_SHIFT 0
+#define DMA0_QM_CP_MSG_BASE2_ADDR_LO_VAL_MASK 0xFFFFFFFF
+
+/* DMA0_QM_CP_MSG_BASE2_ADDR_HI */
+#define DMA0_QM_CP_MSG_BASE2_ADDR_HI_VAL_SHIFT 0
+#define DMA0_QM_CP_MSG_BASE2_ADDR_HI_VAL_MASK 0xFFFFFFFF
+
+/* DMA0_QM_CP_MSG_BASE3_ADDR_LO */
+#define DMA0_QM_CP_MSG_BASE3_ADDR_LO_VAL_SHIFT 0
+#define DMA0_QM_CP_MSG_BASE3_ADDR_LO_VAL_MASK 0xFFFFFFFF
+
+/* DMA0_QM_CP_MSG_BASE3_ADDR_HI */
+#define DMA0_QM_CP_MSG_BASE3_ADDR_HI_VAL_SHIFT 0
+#define DMA0_QM_CP_MSG_BASE3_ADDR_HI_VAL_MASK 0xFFFFFFFF
+
+/* DMA0_QM_CP_LDMA_TSIZE_OFFSET */
+#define DMA0_QM_CP_LDMA_TSIZE_OFFSET_VAL_SHIFT 0
+#define DMA0_QM_CP_LDMA_TSIZE_OFFSET_VAL_MASK 0xFFFFFFFF
+
+/* DMA0_QM_CP_LDMA_SRC_BASE_LO_OFFSET */
+#define DMA0_QM_CP_LDMA_SRC_BASE_LO_OFFSET_VAL_SHIFT 0
+#define DMA0_QM_CP_LDMA_SRC_BASE_LO_OFFSET_VAL_MASK 0xFFFFFFFF
+
+/* DMA0_QM_CP_LDMA_DST_BASE_LO_OFFSET */
+#define DMA0_QM_CP_LDMA_DST_BASE_LO_OFFSET_VAL_SHIFT 0
+#define DMA0_QM_CP_LDMA_DST_BASE_LO_OFFSET_VAL_MASK 0xFFFFFFFF
+
+/* DMA0_QM_CP_FENCE0_RDATA */
+#define DMA0_QM_CP_FENCE0_RDATA_INC_VAL_SHIFT 0
+#define DMA0_QM_CP_FENCE0_RDATA_INC_VAL_MASK 0xF
+
+/* DMA0_QM_CP_FENCE1_RDATA */
+#define DMA0_QM_CP_FENCE1_RDATA_INC_VAL_SHIFT 0
+#define DMA0_QM_CP_FENCE1_RDATA_INC_VAL_MASK 0xF
+
+/* DMA0_QM_CP_FENCE2_RDATA */
+#define DMA0_QM_CP_FENCE2_RDATA_INC_VAL_SHIFT 0
+#define DMA0_QM_CP_FENCE2_RDATA_INC_VAL_MASK 0xF
+
+/* DMA0_QM_CP_FENCE3_RDATA */
+#define DMA0_QM_CP_FENCE3_RDATA_INC_VAL_SHIFT 0
+#define DMA0_QM_CP_FENCE3_RDATA_INC_VAL_MASK 0xF
+
+/* DMA0_QM_CP_FENCE0_CNT */
+#define DMA0_QM_CP_FENCE0_CNT_VAL_SHIFT 0
+#define DMA0_QM_CP_FENCE0_CNT_VAL_MASK 0x3FFF
+
+/* DMA0_QM_CP_FENCE1_CNT */
+#define DMA0_QM_CP_FENCE1_CNT_VAL_SHIFT 0
+#define DMA0_QM_CP_FENCE1_CNT_VAL_MASK 0x3FFF
+
+/* DMA0_QM_CP_FENCE2_CNT */
+#define DMA0_QM_CP_FENCE2_CNT_VAL_SHIFT 0
+#define DMA0_QM_CP_FENCE2_CNT_VAL_MASK 0x3FFF
+
+/* DMA0_QM_CP_FENCE3_CNT */
+#define DMA0_QM_CP_FENCE3_CNT_VAL_SHIFT 0
+#define DMA0_QM_CP_FENCE3_CNT_VAL_MASK 0x3FFF
+
+/* DMA0_QM_CP_STS */
+#define DMA0_QM_CP_STS_MSG_INFLIGHT_CNT_SHIFT 0
+#define DMA0_QM_CP_STS_MSG_INFLIGHT_CNT_MASK 0xFFFF
+#define DMA0_QM_CP_STS_ERDY_SHIFT 16
+#define DMA0_QM_CP_STS_ERDY_MASK 0x10000
+#define DMA0_QM_CP_STS_RRDY_SHIFT 17
+#define DMA0_QM_CP_STS_RRDY_MASK 0x20000
+#define DMA0_QM_CP_STS_MRDY_SHIFT 18
+#define DMA0_QM_CP_STS_MRDY_MASK 0x40000
+#define DMA0_QM_CP_STS_SW_STOP_SHIFT 19
+#define DMA0_QM_CP_STS_SW_STOP_MASK 0x80000
+#define DMA0_QM_CP_STS_FENCE_ID_SHIFT 20
+#define DMA0_QM_CP_STS_FENCE_ID_MASK 0x300000
+#define DMA0_QM_CP_STS_FENCE_IN_PROGRESS_SHIFT 22
+#define DMA0_QM_CP_STS_FENCE_IN_PROGRESS_MASK 0x400000
+
+/* DMA0_QM_CP_CURRENT_INST_LO */
+#define DMA0_QM_CP_CURRENT_INST_LO_VAL_SHIFT 0
+#define DMA0_QM_CP_CURRENT_INST_LO_VAL_MASK 0xFFFFFFFF
+
+/* DMA0_QM_CP_CURRENT_INST_HI */
+#define DMA0_QM_CP_CURRENT_INST_HI_VAL_SHIFT 0
+#define DMA0_QM_CP_CURRENT_INST_HI_VAL_MASK 0xFFFFFFFF
+
+/* DMA0_QM_CP_BARRIER_CFG */
+#define DMA0_QM_CP_BARRIER_CFG_EBGUARD_SHIFT 0
+#define DMA0_QM_CP_BARRIER_CFG_EBGUARD_MASK 0xFFF
+#define DMA0_QM_CP_BARRIER_CFG_RBGUARD_SHIFT 16
+#define DMA0_QM_CP_BARRIER_CFG_RBGUARD_MASK 0xF0000
+
+/* DMA0_QM_CP_DBG_0 */
+#define DMA0_QM_CP_DBG_0_CS_SHIFT 0
+#define DMA0_QM_CP_DBG_0_CS_MASK 0xF
+#define DMA0_QM_CP_DBG_0_EB_CNT_NOT_ZERO_SHIFT 4
+#define DMA0_QM_CP_DBG_0_EB_CNT_NOT_ZERO_MASK 0x10
+#define DMA0_QM_CP_DBG_0_BULK_CNT_NOT_ZERO_SHIFT 5
+#define DMA0_QM_CP_DBG_0_BULK_CNT_NOT_ZERO_MASK 0x20
+#define DMA0_QM_CP_DBG_0_MREB_STALL_SHIFT 6
+#define DMA0_QM_CP_DBG_0_MREB_STALL_MASK 0x40
+#define DMA0_QM_CP_DBG_0_STALL_SHIFT 7
+#define DMA0_QM_CP_DBG_0_STALL_MASK 0x80
+
+/* DMA0_QM_CP_ARUSER_31_11 */
+#define DMA0_QM_CP_ARUSER_31_11_VAL_SHIFT 0
+#define DMA0_QM_CP_ARUSER_31_11_VAL_MASK 0x1FFFFF
+
+/* DMA0_QM_CP_AWUSER_31_11 */
+#define DMA0_QM_CP_AWUSER_31_11_VAL_SHIFT 0
+#define DMA0_QM_CP_AWUSER_31_11_VAL_MASK 0x1FFFFF
+
+/* DMA0_QM_ARB_CFG_0 */
+#define DMA0_QM_ARB_CFG_0_TYPE_SHIFT 0
+#define DMA0_QM_ARB_CFG_0_TYPE_MASK 0x1
+#define DMA0_QM_ARB_CFG_0_IS_MASTER_SHIFT 4
+#define DMA0_QM_ARB_CFG_0_IS_MASTER_MASK 0x10
+#define DMA0_QM_ARB_CFG_0_EN_SHIFT 8
+#define DMA0_QM_ARB_CFG_0_EN_MASK 0x100
+#define DMA0_QM_ARB_CFG_0_MASK_SHIFT 12
+#define DMA0_QM_ARB_CFG_0_MASK_MASK 0xF000
+#define DMA0_QM_ARB_CFG_0_MST_MSG_NOSTALL_SHIFT 16
+#define DMA0_QM_ARB_CFG_0_MST_MSG_NOSTALL_MASK 0x10000
+
+/* DMA0_QM_ARB_CHOISE_Q_PUSH */
+#define DMA0_QM_ARB_CHOISE_Q_PUSH_VAL_SHIFT 0
+#define DMA0_QM_ARB_CHOISE_Q_PUSH_VAL_MASK 0x3
+
+/* DMA0_QM_ARB_WRR_WEIGHT */
+#define DMA0_QM_ARB_WRR_WEIGHT_VAL_SHIFT 0
+#define DMA0_QM_ARB_WRR_WEIGHT_VAL_MASK 0xFFFFFFFF
+
+/* DMA0_QM_ARB_CFG_1 */
+#define DMA0_QM_ARB_CFG_1_CLR_SHIFT 0
+#define DMA0_QM_ARB_CFG_1_CLR_MASK 0x1
+
+/* DMA0_QM_ARB_MST_AVAIL_CRED */
+#define DMA0_QM_ARB_MST_AVAIL_CRED_VAL_SHIFT 0
+#define DMA0_QM_ARB_MST_AVAIL_CRED_VAL_MASK 0x7F
+
+/* DMA0_QM_ARB_MST_CRED_INC */
+#define DMA0_QM_ARB_MST_CRED_INC_VAL_SHIFT 0
+#define DMA0_QM_ARB_MST_CRED_INC_VAL_MASK 0xFFFFFFFF
+
+/* DMA0_QM_ARB_MST_CHOISE_PUSH_OFST */
+#define DMA0_QM_ARB_MST_CHOISE_PUSH_OFST_VAL_SHIFT 0
+#define DMA0_QM_ARB_MST_CHOISE_PUSH_OFST_VAL_MASK 0xFFFFFFFF
+
+/* DMA0_QM_ARB_SLV_MASTER_INC_CRED_OFST */
+#define DMA0_QM_ARB_SLV_MASTER_INC_CRED_OFST_VAL_SHIFT 0
+#define DMA0_QM_ARB_SLV_MASTER_INC_CRED_OFST_VAL_MASK 0xFFFFFFFF
+
+/* DMA0_QM_ARB_MST_SLAVE_EN */
+#define DMA0_QM_ARB_MST_SLAVE_EN_VAL_SHIFT 0
+#define DMA0_QM_ARB_MST_SLAVE_EN_VAL_MASK 0xFFFFFFFF
+
+/* DMA0_QM_ARB_MST_QUIET_PER */
+#define DMA0_QM_ARB_MST_QUIET_PER_VAL_SHIFT 0
+#define DMA0_QM_ARB_MST_QUIET_PER_VAL_MASK 0xFFFFFFFF
+
+/* DMA0_QM_ARB_SLV_CHOISE_WDT */
+#define DMA0_QM_ARB_SLV_CHOISE_WDT_VAL_SHIFT 0
+#define DMA0_QM_ARB_SLV_CHOISE_WDT_VAL_MASK 0xFFFFFFFF
+
+/* DMA0_QM_ARB_SLV_ID */
+#define DMA0_QM_ARB_SLV_ID_VAL_SHIFT 0
+#define DMA0_QM_ARB_SLV_ID_VAL_MASK 0x1F
+
+/* DMA0_QM_ARB_MSG_MAX_INFLIGHT */
+#define DMA0_QM_ARB_MSG_MAX_INFLIGHT_VAL_SHIFT 0
+#define DMA0_QM_ARB_MSG_MAX_INFLIGHT_VAL_MASK 0x3F
+
+/* DMA0_QM_ARB_MSG_AWUSER_31_11 */
+#define DMA0_QM_ARB_MSG_AWUSER_31_11_VAL_SHIFT 0
+#define DMA0_QM_ARB_MSG_AWUSER_31_11_VAL_MASK 0x1FFFFF
+
+/* DMA0_QM_ARB_MSG_AWUSER_SEC_PROP */
+#define DMA0_QM_ARB_MSG_AWUSER_SEC_PROP_ASID_SHIFT 0
+#define DMA0_QM_ARB_MSG_AWUSER_SEC_PROP_ASID_MASK 0x3FF
+#define DMA0_QM_ARB_MSG_AWUSER_SEC_PROP_MMBP_SHIFT 10
+#define DMA0_QM_ARB_MSG_AWUSER_SEC_PROP_MMBP_MASK 0x400
+
+/* DMA0_QM_ARB_MSG_AWUSER_NON_SEC_PROP */
+#define DMA0_QM_ARB_MSG_AWUSER_NON_SEC_PROP_ASID_SHIFT 0
+#define DMA0_QM_ARB_MSG_AWUSER_NON_SEC_PROP_ASID_MASK 0x3FF
+#define DMA0_QM_ARB_MSG_AWUSER_NON_SEC_PROP_MMBP_SHIFT 10
+#define DMA0_QM_ARB_MSG_AWUSER_NON_SEC_PROP_MMBP_MASK 0x400
+
+/* DMA0_QM_ARB_BASE_LO */
+#define DMA0_QM_ARB_BASE_LO_VAL_SHIFT 0
+#define DMA0_QM_ARB_BASE_LO_VAL_MASK 0xFFFFFFFF
+
+/* DMA0_QM_ARB_BASE_HI */
+#define DMA0_QM_ARB_BASE_HI_VAL_SHIFT 0
+#define DMA0_QM_ARB_BASE_HI_VAL_MASK 0xFFFFFFFF
+
+/* DMA0_QM_ARB_STATE_STS */
+#define DMA0_QM_ARB_STATE_STS_VAL_SHIFT 0
+#define DMA0_QM_ARB_STATE_STS_VAL_MASK 0xFFFFFFFF
+
+/* DMA0_QM_ARB_CHOISE_FULLNESS_STS */
+#define DMA0_QM_ARB_CHOISE_FULLNESS_STS_VAL_SHIFT 0
+#define DMA0_QM_ARB_CHOISE_FULLNESS_STS_VAL_MASK 0x7F
+
+/* DMA0_QM_ARB_MSG_STS */
+#define DMA0_QM_ARB_MSG_STS_FULL_SHIFT 0
+#define DMA0_QM_ARB_MSG_STS_FULL_MASK 0x1
+#define DMA0_QM_ARB_MSG_STS_NO_INFLIGHT_SHIFT 1
+#define DMA0_QM_ARB_MSG_STS_NO_INFLIGHT_MASK 0x2
+
+/* DMA0_QM_ARB_SLV_CHOISE_Q_HEAD */
+#define DMA0_QM_ARB_SLV_CHOISE_Q_HEAD_VAL_SHIFT 0
+#define DMA0_QM_ARB_SLV_CHOISE_Q_HEAD_VAL_MASK 0x3
+
+/* DMA0_QM_ARB_ERR_CAUSE */
+#define DMA0_QM_ARB_ERR_CAUSE_CHOISE_OVF_SHIFT 0
+#define DMA0_QM_ARB_ERR_CAUSE_CHOISE_OVF_MASK 0x1
+#define DMA0_QM_ARB_ERR_CAUSE_CHOISE_WDT_SHIFT 1
+#define DMA0_QM_ARB_ERR_CAUSE_CHOISE_WDT_MASK 0x2
+#define DMA0_QM_ARB_ERR_CAUSE_AXI_LBW_ERR_SHIFT 2
+#define DMA0_QM_ARB_ERR_CAUSE_AXI_LBW_ERR_MASK 0x4
+
+/* DMA0_QM_ARB_ERR_MSG_EN */
+#define DMA0_QM_ARB_ERR_MSG_EN_CHOISE_OVF_SHIFT 0
+#define DMA0_QM_ARB_ERR_MSG_EN_CHOISE_OVF_MASK 0x1
+#define DMA0_QM_ARB_ERR_MSG_EN_CHOISE_WDT_SHIFT 1
+#define DMA0_QM_ARB_ERR_MSG_EN_CHOISE_WDT_MASK 0x2
+#define DMA0_QM_ARB_ERR_MSG_EN_AXI_LBW_ERR_SHIFT 2
+#define DMA0_QM_ARB_ERR_MSG_EN_AXI_LBW_ERR_MASK 0x4
+
+/* DMA0_QM_ARB_ERR_STS_DRP */
+#define DMA0_QM_ARB_ERR_STS_DRP_VAL_SHIFT 0
+#define DMA0_QM_ARB_ERR_STS_DRP_VAL_MASK 0x3
+
+/* DMA0_QM_ARB_MST_CRED_STS */
+#define DMA0_QM_ARB_MST_CRED_STS_VAL_SHIFT 0
+#define DMA0_QM_ARB_MST_CRED_STS_VAL_MASK 0x7F
+
+/* DMA0_QM_CGM_CFG */
+#define DMA0_QM_CGM_CFG_IDLE_TH_SHIFT 0
+#define DMA0_QM_CGM_CFG_IDLE_TH_MASK 0xFFF
+#define DMA0_QM_CGM_CFG_G2F_TH_SHIFT 16
+#define DMA0_QM_CGM_CFG_G2F_TH_MASK 0xFF0000
+#define DMA0_QM_CGM_CFG_CP_IDLE_MASK_SHIFT 24
+#define DMA0_QM_CGM_CFG_CP_IDLE_MASK_MASK 0x1F000000
+#define DMA0_QM_CGM_CFG_EN_SHIFT 31
+#define DMA0_QM_CGM_CFG_EN_MASK 0x80000000
+
+/* DMA0_QM_CGM_STS */
+#define DMA0_QM_CGM_STS_ST_SHIFT 0
+#define DMA0_QM_CGM_STS_ST_MASK 0x3
+#define DMA0_QM_CGM_STS_CG_SHIFT 4
+#define DMA0_QM_CGM_STS_CG_MASK 0x10
+#define DMA0_QM_CGM_STS_AGENT_IDLE_SHIFT 8
+#define DMA0_QM_CGM_STS_AGENT_IDLE_MASK 0x100
+#define DMA0_QM_CGM_STS_AXI_IDLE_SHIFT 9
+#define DMA0_QM_CGM_STS_AXI_IDLE_MASK 0x200
+#define DMA0_QM_CGM_STS_CP_IDLE_SHIFT 10
+#define DMA0_QM_CGM_STS_CP_IDLE_MASK 0x400
+
+/* DMA0_QM_CGM_CFG1 */
+#define DMA0_QM_CGM_CFG1_MASK_TH_SHIFT 0
+#define DMA0_QM_CGM_CFG1_MASK_TH_MASK 0xFF
+
+/* DMA0_QM_LOCAL_RANGE_BASE */
+#define DMA0_QM_LOCAL_RANGE_BASE_VAL_SHIFT 0
+#define DMA0_QM_LOCAL_RANGE_BASE_VAL_MASK 0xFFFF
+
+/* DMA0_QM_LOCAL_RANGE_SIZE */
+#define DMA0_QM_LOCAL_RANGE_SIZE_VAL_SHIFT 0
+#define DMA0_QM_LOCAL_RANGE_SIZE_VAL_MASK 0xFFFF
+
+/* DMA0_QM_CSMR_STRICT_PRIO_CFG */
+#define DMA0_QM_CSMR_STRICT_PRIO_CFG_TYPE_SHIFT 0
+#define DMA0_QM_CSMR_STRICT_PRIO_CFG_TYPE_MASK 0x1
+
+/* DMA0_QM_HBW_RD_RATE_LIM_CFG_1 */
+#define DMA0_QM_HBW_RD_RATE_LIM_CFG_1_TOUT_SHIFT 0
+#define DMA0_QM_HBW_RD_RATE_LIM_CFG_1_TOUT_MASK 0xFF
+#define DMA0_QM_HBW_RD_RATE_LIM_CFG_1_EN_SHIFT 31
+#define DMA0_QM_HBW_RD_RATE_LIM_CFG_1_EN_MASK 0x80000000
+
+/* DMA0_QM_LBW_WR_RATE_LIM_CFG_0 */
+#define DMA0_QM_LBW_WR_RATE_LIM_CFG_0_RST_TOKEN_SHIFT 0
+#define DMA0_QM_LBW_WR_RATE_LIM_CFG_0_RST_TOKEN_MASK 0xFF
+#define DMA0_QM_LBW_WR_RATE_LIM_CFG_0_SAT_SHIFT 16
+#define DMA0_QM_LBW_WR_RATE_LIM_CFG_0_SAT_MASK 0xFF0000
+
+/* DMA0_QM_LBW_WR_RATE_LIM_CFG_1 */
+#define DMA0_QM_LBW_WR_RATE_LIM_CFG_1_TOUT_SHIFT 0
+#define DMA0_QM_LBW_WR_RATE_LIM_CFG_1_TOUT_MASK 0xFF
+#define DMA0_QM_LBW_WR_RATE_LIM_CFG_1_EN_SHIFT 31
+#define DMA0_QM_LBW_WR_RATE_LIM_CFG_1_EN_MASK 0x80000000
+
+/* DMA0_QM_HBW_RD_RATE_LIM_CFG_0 */
+#define DMA0_QM_HBW_RD_RATE_LIM_CFG_0_RST_TOKEN_SHIFT 0
+#define DMA0_QM_HBW_RD_RATE_LIM_CFG_0_RST_TOKEN_MASK 0xFF
+#define DMA0_QM_HBW_RD_RATE_LIM_CFG_0_SAT_SHIFT 16
+#define DMA0_QM_HBW_RD_RATE_LIM_CFG_0_SAT_MASK 0xFF0000
+
+/* DMA0_QM_GLBL_AXCACHE */
+#define DMA0_QM_GLBL_AXCACHE_AR_SHIFT 0
+#define DMA0_QM_GLBL_AXCACHE_AR_MASK 0xF
+#define DMA0_QM_GLBL_AXCACHE_AW_SHIFT 16
+#define DMA0_QM_GLBL_AXCACHE_AW_MASK 0xF0000
+
+/* DMA0_QM_IND_GW_APB_CFG */
+#define DMA0_QM_IND_GW_APB_CFG_ADDR_SHIFT 0
+#define DMA0_QM_IND_GW_APB_CFG_ADDR_MASK 0x7FFFFFFF
+#define DMA0_QM_IND_GW_APB_CFG_CMD_SHIFT 31
+#define DMA0_QM_IND_GW_APB_CFG_CMD_MASK 0x80000000
+
+/* DMA0_QM_IND_GW_APB_WDATA */
+#define DMA0_QM_IND_GW_APB_WDATA_VAL_SHIFT 0
+#define DMA0_QM_IND_GW_APB_WDATA_VAL_MASK 0xFFFFFFFF
+
+/* DMA0_QM_IND_GW_APB_RDATA */
+#define DMA0_QM_IND_GW_APB_RDATA_VAL_SHIFT 0
+#define DMA0_QM_IND_GW_APB_RDATA_VAL_MASK 0xFFFFFFFF
+
+/* DMA0_QM_IND_GW_APB_STATUS */
+#define DMA0_QM_IND_GW_APB_STATUS_RDY_SHIFT 0
+#define DMA0_QM_IND_GW_APB_STATUS_RDY_MASK 0x1
+#define DMA0_QM_IND_GW_APB_STATUS_ERR_SHIFT 1
+#define DMA0_QM_IND_GW_APB_STATUS_ERR_MASK 0x2
+
+/* DMA0_QM_GLBL_ERR_ADDR_LO */
+#define DMA0_QM_GLBL_ERR_ADDR_LO_VAL_SHIFT 0
+#define DMA0_QM_GLBL_ERR_ADDR_LO_VAL_MASK 0xFFFFFFFF
+
+/* DMA0_QM_GLBL_ERR_ADDR_HI */
+#define DMA0_QM_GLBL_ERR_ADDR_HI_VAL_SHIFT 0
+#define DMA0_QM_GLBL_ERR_ADDR_HI_VAL_MASK 0xFFFFFFFF
+
+/* DMA0_QM_GLBL_ERR_WDATA */
+#define DMA0_QM_GLBL_ERR_WDATA_VAL_SHIFT 0
+#define DMA0_QM_GLBL_ERR_WDATA_VAL_MASK 0xFFFFFFFF
+
+/* DMA0_QM_GLBL_MEM_INIT_BUSY */
+#define DMA0_QM_GLBL_MEM_INIT_BUSY_RBUF_SHIFT 0
+#define DMA0_QM_GLBL_MEM_INIT_BUSY_RBUF_MASK 0xF
+
+#endif /* ASIC_REG_DMA0_QM_MASKS_H_ */
diff --git a/drivers/accel/habanalabs/include/gaudi/asic_reg/dma0_qm_regs.h b/drivers/accel/habanalabs/include/gaudi/asic_reg/dma0_qm_regs.h
new file mode 100644
index 0000000000..8e56a93d88
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi/asic_reg/dma0_qm_regs.h
@@ -0,0 +1,834 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2016-2018 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ ** DO NOT EDIT BELOW **
+ ************************************/
+
+#ifndef ASIC_REG_DMA0_QM_REGS_H_
+#define ASIC_REG_DMA0_QM_REGS_H_
+
+/*
+ *****************************************
+ * DMA0_QM (Prototype: QMAN)
+ *****************************************
+ */
+
+#define mmDMA0_QM_GLBL_CFG0 0x508000
+
+#define mmDMA0_QM_GLBL_CFG1 0x508004
+
+#define mmDMA0_QM_GLBL_PROT 0x508008
+
+#define mmDMA0_QM_GLBL_ERR_CFG 0x50800C
+
+#define mmDMA0_QM_GLBL_SECURE_PROPS_0 0x508010
+
+#define mmDMA0_QM_GLBL_SECURE_PROPS_1 0x508014
+
+#define mmDMA0_QM_GLBL_SECURE_PROPS_2 0x508018
+
+#define mmDMA0_QM_GLBL_SECURE_PROPS_3 0x50801C
+
+#define mmDMA0_QM_GLBL_SECURE_PROPS_4 0x508020
+
+#define mmDMA0_QM_GLBL_NON_SECURE_PROPS_0 0x508024
+
+#define mmDMA0_QM_GLBL_NON_SECURE_PROPS_1 0x508028
+
+#define mmDMA0_QM_GLBL_NON_SECURE_PROPS_2 0x50802C
+
+#define mmDMA0_QM_GLBL_NON_SECURE_PROPS_3 0x508030
+
+#define mmDMA0_QM_GLBL_NON_SECURE_PROPS_4 0x508034
+
+#define mmDMA0_QM_GLBL_STS0 0x508038
+
+#define mmDMA0_QM_GLBL_STS1_0 0x508040
+
+#define mmDMA0_QM_GLBL_STS1_1 0x508044
+
+#define mmDMA0_QM_GLBL_STS1_2 0x508048
+
+#define mmDMA0_QM_GLBL_STS1_3 0x50804C
+
+#define mmDMA0_QM_GLBL_STS1_4 0x508050
+
+#define mmDMA0_QM_GLBL_MSG_EN_0 0x508054
+
+#define mmDMA0_QM_GLBL_MSG_EN_1 0x508058
+
+#define mmDMA0_QM_GLBL_MSG_EN_2 0x50805C
+
+#define mmDMA0_QM_GLBL_MSG_EN_3 0x508060
+
+#define mmDMA0_QM_GLBL_MSG_EN_4 0x508068
+
+#define mmDMA0_QM_PQ_BASE_LO_0 0x508070
+
+#define mmDMA0_QM_PQ_BASE_LO_1 0x508074
+
+#define mmDMA0_QM_PQ_BASE_LO_2 0x508078
+
+#define mmDMA0_QM_PQ_BASE_LO_3 0x50807C
+
+#define mmDMA0_QM_PQ_BASE_HI_0 0x508080
+
+#define mmDMA0_QM_PQ_BASE_HI_1 0x508084
+
+#define mmDMA0_QM_PQ_BASE_HI_2 0x508088
+
+#define mmDMA0_QM_PQ_BASE_HI_3 0x50808C
+
+#define mmDMA0_QM_PQ_SIZE_0 0x508090
+
+#define mmDMA0_QM_PQ_SIZE_1 0x508094
+
+#define mmDMA0_QM_PQ_SIZE_2 0x508098
+
+#define mmDMA0_QM_PQ_SIZE_3 0x50809C
+
+#define mmDMA0_QM_PQ_PI_0 0x5080A0
+
+#define mmDMA0_QM_PQ_PI_1 0x5080A4
+
+#define mmDMA0_QM_PQ_PI_2 0x5080A8
+
+#define mmDMA0_QM_PQ_PI_3 0x5080AC
+
+#define mmDMA0_QM_PQ_CI_0 0x5080B0
+
+#define mmDMA0_QM_PQ_CI_1 0x5080B4
+
+#define mmDMA0_QM_PQ_CI_2 0x5080B8
+
+#define mmDMA0_QM_PQ_CI_3 0x5080BC
+
+#define mmDMA0_QM_PQ_CFG0_0 0x5080C0
+
+#define mmDMA0_QM_PQ_CFG0_1 0x5080C4
+
+#define mmDMA0_QM_PQ_CFG0_2 0x5080C8
+
+#define mmDMA0_QM_PQ_CFG0_3 0x5080CC
+
+#define mmDMA0_QM_PQ_CFG1_0 0x5080D0
+
+#define mmDMA0_QM_PQ_CFG1_1 0x5080D4
+
+#define mmDMA0_QM_PQ_CFG1_2 0x5080D8
+
+#define mmDMA0_QM_PQ_CFG1_3 0x5080DC
+
+#define mmDMA0_QM_PQ_ARUSER_31_11_0 0x5080E0
+
+#define mmDMA0_QM_PQ_ARUSER_31_11_1 0x5080E4
+
+#define mmDMA0_QM_PQ_ARUSER_31_11_2 0x5080E8
+
+#define mmDMA0_QM_PQ_ARUSER_31_11_3 0x5080EC
+
+#define mmDMA0_QM_PQ_STS0_0 0x5080F0
+
+#define mmDMA0_QM_PQ_STS0_1 0x5080F4
+
+#define mmDMA0_QM_PQ_STS0_2 0x5080F8
+
+#define mmDMA0_QM_PQ_STS0_3 0x5080FC
+
+#define mmDMA0_QM_PQ_STS1_0 0x508100
+
+#define mmDMA0_QM_PQ_STS1_1 0x508104
+
+#define mmDMA0_QM_PQ_STS1_2 0x508108
+
+#define mmDMA0_QM_PQ_STS1_3 0x50810C
+
+#define mmDMA0_QM_CQ_CFG0_0 0x508110
+
+#define mmDMA0_QM_CQ_CFG0_1 0x508114
+
+#define mmDMA0_QM_CQ_CFG0_2 0x508118
+
+#define mmDMA0_QM_CQ_CFG0_3 0x50811C
+
+#define mmDMA0_QM_CQ_CFG0_4 0x508120
+
+#define mmDMA0_QM_CQ_CFG1_0 0x508124
+
+#define mmDMA0_QM_CQ_CFG1_1 0x508128
+
+#define mmDMA0_QM_CQ_CFG1_2 0x50812C
+
+#define mmDMA0_QM_CQ_CFG1_3 0x508130
+
+#define mmDMA0_QM_CQ_CFG1_4 0x508134
+
+#define mmDMA0_QM_CQ_ARUSER_31_11_0 0x508138
+
+#define mmDMA0_QM_CQ_ARUSER_31_11_1 0x50813C
+
+#define mmDMA0_QM_CQ_ARUSER_31_11_2 0x508140
+
+#define mmDMA0_QM_CQ_ARUSER_31_11_3 0x508144
+
+#define mmDMA0_QM_CQ_ARUSER_31_11_4 0x508148
+
+#define mmDMA0_QM_CQ_STS0_0 0x50814C
+
+#define mmDMA0_QM_CQ_STS0_1 0x508150
+
+#define mmDMA0_QM_CQ_STS0_2 0x508154
+
+#define mmDMA0_QM_CQ_STS0_3 0x508158
+
+#define mmDMA0_QM_CQ_STS0_4 0x50815C
+
+#define mmDMA0_QM_CQ_STS1_0 0x508160
+
+#define mmDMA0_QM_CQ_STS1_1 0x508164
+
+#define mmDMA0_QM_CQ_STS1_2 0x508168
+
+#define mmDMA0_QM_CQ_STS1_3 0x50816C
+
+#define mmDMA0_QM_CQ_STS1_4 0x508170
+
+#define mmDMA0_QM_CQ_PTR_LO_0 0x508174
+
+#define mmDMA0_QM_CQ_PTR_HI_0 0x508178
+
+#define mmDMA0_QM_CQ_TSIZE_0 0x50817C
+
+#define mmDMA0_QM_CQ_CTL_0 0x508180
+
+#define mmDMA0_QM_CQ_PTR_LO_1 0x508184
+
+#define mmDMA0_QM_CQ_PTR_HI_1 0x508188
+
+#define mmDMA0_QM_CQ_TSIZE_1 0x50818C
+
+#define mmDMA0_QM_CQ_CTL_1 0x508190
+
+#define mmDMA0_QM_CQ_PTR_LO_2 0x508194
+
+#define mmDMA0_QM_CQ_PTR_HI_2 0x508198
+
+#define mmDMA0_QM_CQ_TSIZE_2 0x50819C
+
+#define mmDMA0_QM_CQ_CTL_2 0x5081A0
+
+#define mmDMA0_QM_CQ_PTR_LO_3 0x5081A4
+
+#define mmDMA0_QM_CQ_PTR_HI_3 0x5081A8
+
+#define mmDMA0_QM_CQ_TSIZE_3 0x5081AC
+
+#define mmDMA0_QM_CQ_CTL_3 0x5081B0
+
+#define mmDMA0_QM_CQ_PTR_LO_4 0x5081B4
+
+#define mmDMA0_QM_CQ_PTR_HI_4 0x5081B8
+
+#define mmDMA0_QM_CQ_TSIZE_4 0x5081BC
+
+#define mmDMA0_QM_CQ_CTL_4 0x5081C0
+
+#define mmDMA0_QM_CQ_PTR_LO_STS_0 0x5081C4
+
+#define mmDMA0_QM_CQ_PTR_LO_STS_1 0x5081C8
+
+#define mmDMA0_QM_CQ_PTR_LO_STS_2 0x5081CC
+
+#define mmDMA0_QM_CQ_PTR_LO_STS_3 0x5081D0
+
+#define mmDMA0_QM_CQ_PTR_LO_STS_4 0x5081D4
+
+#define mmDMA0_QM_CQ_PTR_HI_STS_0 0x5081D8
+
+#define mmDMA0_QM_CQ_PTR_HI_STS_1 0x5081DC
+
+#define mmDMA0_QM_CQ_PTR_HI_STS_2 0x5081E0
+
+#define mmDMA0_QM_CQ_PTR_HI_STS_3 0x5081E4
+
+#define mmDMA0_QM_CQ_PTR_HI_STS_4 0x5081E8
+
+#define mmDMA0_QM_CQ_TSIZE_STS_0 0x5081EC
+
+#define mmDMA0_QM_CQ_TSIZE_STS_1 0x5081F0
+
+#define mmDMA0_QM_CQ_TSIZE_STS_2 0x5081F4
+
+#define mmDMA0_QM_CQ_TSIZE_STS_3 0x5081F8
+
+#define mmDMA0_QM_CQ_TSIZE_STS_4 0x5081FC
+
+#define mmDMA0_QM_CQ_CTL_STS_0 0x508200
+
+#define mmDMA0_QM_CQ_CTL_STS_1 0x508204
+
+#define mmDMA0_QM_CQ_CTL_STS_2 0x508208
+
+#define mmDMA0_QM_CQ_CTL_STS_3 0x50820C
+
+#define mmDMA0_QM_CQ_CTL_STS_4 0x508210
+
+#define mmDMA0_QM_CQ_IFIFO_CNT_0 0x508214
+
+#define mmDMA0_QM_CQ_IFIFO_CNT_1 0x508218
+
+#define mmDMA0_QM_CQ_IFIFO_CNT_2 0x50821C
+
+#define mmDMA0_QM_CQ_IFIFO_CNT_3 0x508220
+
+#define mmDMA0_QM_CQ_IFIFO_CNT_4 0x508224
+
+#define mmDMA0_QM_CP_MSG_BASE0_ADDR_LO_0 0x508228
+
+#define mmDMA0_QM_CP_MSG_BASE0_ADDR_LO_1 0x50822C
+
+#define mmDMA0_QM_CP_MSG_BASE0_ADDR_LO_2 0x508230
+
+#define mmDMA0_QM_CP_MSG_BASE0_ADDR_LO_3 0x508234
+
+#define mmDMA0_QM_CP_MSG_BASE0_ADDR_LO_4 0x508238
+
+#define mmDMA0_QM_CP_MSG_BASE0_ADDR_HI_0 0x50823C
+
+#define mmDMA0_QM_CP_MSG_BASE0_ADDR_HI_1 0x508240
+
+#define mmDMA0_QM_CP_MSG_BASE0_ADDR_HI_2 0x508244
+
+#define mmDMA0_QM_CP_MSG_BASE0_ADDR_HI_3 0x508248
+
+#define mmDMA0_QM_CP_MSG_BASE0_ADDR_HI_4 0x50824C
+
+#define mmDMA0_QM_CP_MSG_BASE1_ADDR_LO_0 0x508250
+
+#define mmDMA0_QM_CP_MSG_BASE1_ADDR_LO_1 0x508254
+
+#define mmDMA0_QM_CP_MSG_BASE1_ADDR_LO_2 0x508258
+
+#define mmDMA0_QM_CP_MSG_BASE1_ADDR_LO_3 0x50825C
+
+#define mmDMA0_QM_CP_MSG_BASE1_ADDR_LO_4 0x508260
+
+#define mmDMA0_QM_CP_MSG_BASE1_ADDR_HI_0 0x508264
+
+#define mmDMA0_QM_CP_MSG_BASE1_ADDR_HI_1 0x508268
+
+#define mmDMA0_QM_CP_MSG_BASE1_ADDR_HI_2 0x50826C
+
+#define mmDMA0_QM_CP_MSG_BASE1_ADDR_HI_3 0x508270
+
+#define mmDMA0_QM_CP_MSG_BASE1_ADDR_HI_4 0x508274
+
+#define mmDMA0_QM_CP_MSG_BASE2_ADDR_LO_0 0x508278
+
+#define mmDMA0_QM_CP_MSG_BASE2_ADDR_LO_1 0x50827C
+
+#define mmDMA0_QM_CP_MSG_BASE2_ADDR_LO_2 0x508280
+
+#define mmDMA0_QM_CP_MSG_BASE2_ADDR_LO_3 0x508284
+
+#define mmDMA0_QM_CP_MSG_BASE2_ADDR_LO_4 0x508288
+
+#define mmDMA0_QM_CP_MSG_BASE2_ADDR_HI_0 0x50828C
+
+#define mmDMA0_QM_CP_MSG_BASE2_ADDR_HI_1 0x508290
+
+#define mmDMA0_QM_CP_MSG_BASE2_ADDR_HI_2 0x508294
+
+#define mmDMA0_QM_CP_MSG_BASE2_ADDR_HI_3 0x508298
+
+#define mmDMA0_QM_CP_MSG_BASE2_ADDR_HI_4 0x50829C
+
+#define mmDMA0_QM_CP_MSG_BASE3_ADDR_LO_0 0x5082A0
+
+#define mmDMA0_QM_CP_MSG_BASE3_ADDR_LO_1 0x5082A4
+
+#define mmDMA0_QM_CP_MSG_BASE3_ADDR_LO_2 0x5082A8
+
+#define mmDMA0_QM_CP_MSG_BASE3_ADDR_LO_3 0x5082AC
+
+#define mmDMA0_QM_CP_MSG_BASE3_ADDR_LO_4 0x5082B0
+
+#define mmDMA0_QM_CP_MSG_BASE3_ADDR_HI_0 0x5082B4
+
+#define mmDMA0_QM_CP_MSG_BASE3_ADDR_HI_1 0x5082B8
+
+#define mmDMA0_QM_CP_MSG_BASE3_ADDR_HI_2 0x5082BC
+
+#define mmDMA0_QM_CP_MSG_BASE3_ADDR_HI_3 0x5082C0
+
+#define mmDMA0_QM_CP_MSG_BASE3_ADDR_HI_4 0x5082C4
+
+#define mmDMA0_QM_CP_LDMA_TSIZE_OFFSET_0 0x5082C8
+
+#define mmDMA0_QM_CP_LDMA_TSIZE_OFFSET_1 0x5082CC
+
+#define mmDMA0_QM_CP_LDMA_TSIZE_OFFSET_2 0x5082D0
+
+#define mmDMA0_QM_CP_LDMA_TSIZE_OFFSET_3 0x5082D4
+
+#define mmDMA0_QM_CP_LDMA_TSIZE_OFFSET_4 0x5082D8
+
+#define mmDMA0_QM_CP_LDMA_SRC_BASE_LO_OFFSET_0 0x5082E0
+
+#define mmDMA0_QM_CP_LDMA_SRC_BASE_LO_OFFSET_1 0x5082E4
+
+#define mmDMA0_QM_CP_LDMA_SRC_BASE_LO_OFFSET_2 0x5082E8
+
+#define mmDMA0_QM_CP_LDMA_SRC_BASE_LO_OFFSET_3 0x5082EC
+
+#define mmDMA0_QM_CP_LDMA_SRC_BASE_LO_OFFSET_4 0x5082F0
+
+#define mmDMA0_QM_CP_LDMA_DST_BASE_LO_OFFSET_0 0x5082F4
+
+#define mmDMA0_QM_CP_LDMA_DST_BASE_LO_OFFSET_1 0x5082F8
+
+#define mmDMA0_QM_CP_LDMA_DST_BASE_LO_OFFSET_2 0x5082FC
+
+#define mmDMA0_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 0x508300
+
+#define mmDMA0_QM_CP_LDMA_DST_BASE_LO_OFFSET_4 0x508304
+
+#define mmDMA0_QM_CP_FENCE0_RDATA_0 0x508308
+
+#define mmDMA0_QM_CP_FENCE0_RDATA_1 0x50830C
+
+#define mmDMA0_QM_CP_FENCE0_RDATA_2 0x508310
+
+#define mmDMA0_QM_CP_FENCE0_RDATA_3 0x508314
+
+#define mmDMA0_QM_CP_FENCE0_RDATA_4 0x508318
+
+#define mmDMA0_QM_CP_FENCE1_RDATA_0 0x50831C
+
+#define mmDMA0_QM_CP_FENCE1_RDATA_1 0x508320
+
+#define mmDMA0_QM_CP_FENCE1_RDATA_2 0x508324
+
+#define mmDMA0_QM_CP_FENCE1_RDATA_3 0x508328
+
+#define mmDMA0_QM_CP_FENCE1_RDATA_4 0x50832C
+
+#define mmDMA0_QM_CP_FENCE2_RDATA_0 0x508330
+
+#define mmDMA0_QM_CP_FENCE2_RDATA_1 0x508334
+
+#define mmDMA0_QM_CP_FENCE2_RDATA_2 0x508338
+
+#define mmDMA0_QM_CP_FENCE2_RDATA_3 0x50833C
+
+#define mmDMA0_QM_CP_FENCE2_RDATA_4 0x508340
+
+#define mmDMA0_QM_CP_FENCE3_RDATA_0 0x508344
+
+#define mmDMA0_QM_CP_FENCE3_RDATA_1 0x508348
+
+#define mmDMA0_QM_CP_FENCE3_RDATA_2 0x50834C
+
+#define mmDMA0_QM_CP_FENCE3_RDATA_3 0x508350
+
+#define mmDMA0_QM_CP_FENCE3_RDATA_4 0x508354
+
+#define mmDMA0_QM_CP_FENCE0_CNT_0 0x508358
+
+#define mmDMA0_QM_CP_FENCE0_CNT_1 0x50835C
+
+#define mmDMA0_QM_CP_FENCE0_CNT_2 0x508360
+
+#define mmDMA0_QM_CP_FENCE0_CNT_3 0x508364
+
+#define mmDMA0_QM_CP_FENCE0_CNT_4 0x508368
+
+#define mmDMA0_QM_CP_FENCE1_CNT_0 0x50836C
+
+#define mmDMA0_QM_CP_FENCE1_CNT_1 0x508370
+
+#define mmDMA0_QM_CP_FENCE1_CNT_2 0x508374
+
+#define mmDMA0_QM_CP_FENCE1_CNT_3 0x508378
+
+#define mmDMA0_QM_CP_FENCE1_CNT_4 0x50837C
+
+#define mmDMA0_QM_CP_FENCE2_CNT_0 0x508380
+
+#define mmDMA0_QM_CP_FENCE2_CNT_1 0x508384
+
+#define mmDMA0_QM_CP_FENCE2_CNT_2 0x508388
+
+#define mmDMA0_QM_CP_FENCE2_CNT_3 0x50838C
+
+#define mmDMA0_QM_CP_FENCE2_CNT_4 0x508390
+
+#define mmDMA0_QM_CP_FENCE3_CNT_0 0x508394
+
+#define mmDMA0_QM_CP_FENCE3_CNT_1 0x508398
+
+#define mmDMA0_QM_CP_FENCE3_CNT_2 0x50839C
+
+#define mmDMA0_QM_CP_FENCE3_CNT_3 0x5083A0
+
+#define mmDMA0_QM_CP_FENCE3_CNT_4 0x5083A4
+
+#define mmDMA0_QM_CP_STS_0 0x5083A8
+
+#define mmDMA0_QM_CP_STS_1 0x5083AC
+
+#define mmDMA0_QM_CP_STS_2 0x5083B0
+
+#define mmDMA0_QM_CP_STS_3 0x5083B4
+
+#define mmDMA0_QM_CP_STS_4 0x5083B8
+
+#define mmDMA0_QM_CP_CURRENT_INST_LO_0 0x5083BC
+
+#define mmDMA0_QM_CP_CURRENT_INST_LO_1 0x5083C0
+
+#define mmDMA0_QM_CP_CURRENT_INST_LO_2 0x5083C4
+
+#define mmDMA0_QM_CP_CURRENT_INST_LO_3 0x5083C8
+
+#define mmDMA0_QM_CP_CURRENT_INST_LO_4 0x5083CC
+
+#define mmDMA0_QM_CP_CURRENT_INST_HI_0 0x5083D0
+
+#define mmDMA0_QM_CP_CURRENT_INST_HI_1 0x5083D4
+
+#define mmDMA0_QM_CP_CURRENT_INST_HI_2 0x5083D8
+
+#define mmDMA0_QM_CP_CURRENT_INST_HI_3 0x5083DC
+
+#define mmDMA0_QM_CP_CURRENT_INST_HI_4 0x5083E0
+
+#define mmDMA0_QM_CP_BARRIER_CFG_0 0x5083F4
+
+#define mmDMA0_QM_CP_BARRIER_CFG_1 0x5083F8
+
+#define mmDMA0_QM_CP_BARRIER_CFG_2 0x5083FC
+
+#define mmDMA0_QM_CP_BARRIER_CFG_3 0x508400
+
+#define mmDMA0_QM_CP_BARRIER_CFG_4 0x508404
+
+#define mmDMA0_QM_CP_DBG_0_0 0x508408
+
+#define mmDMA0_QM_CP_DBG_0_1 0x50840C
+
+#define mmDMA0_QM_CP_DBG_0_2 0x508410
+
+#define mmDMA0_QM_CP_DBG_0_3 0x508414
+
+#define mmDMA0_QM_CP_DBG_0_4 0x508418
+
+#define mmDMA0_QM_CP_ARUSER_31_11_0 0x50841C
+
+#define mmDMA0_QM_CP_ARUSER_31_11_1 0x508420
+
+#define mmDMA0_QM_CP_ARUSER_31_11_2 0x508424
+
+#define mmDMA0_QM_CP_ARUSER_31_11_3 0x508428
+
+#define mmDMA0_QM_CP_ARUSER_31_11_4 0x50842C
+
+#define mmDMA0_QM_CP_AWUSER_31_11_0 0x508430
+
+#define mmDMA0_QM_CP_AWUSER_31_11_1 0x508434
+
+#define mmDMA0_QM_CP_AWUSER_31_11_2 0x508438
+
+#define mmDMA0_QM_CP_AWUSER_31_11_3 0x50843C
+
+#define mmDMA0_QM_CP_AWUSER_31_11_4 0x508440
+
+#define mmDMA0_QM_ARB_CFG_0 0x508A00
+
+#define mmDMA0_QM_ARB_CHOISE_Q_PUSH 0x508A04
+
+#define mmDMA0_QM_ARB_WRR_WEIGHT_0 0x508A08
+
+#define mmDMA0_QM_ARB_WRR_WEIGHT_1 0x508A0C
+
+#define mmDMA0_QM_ARB_WRR_WEIGHT_2 0x508A10
+
+#define mmDMA0_QM_ARB_WRR_WEIGHT_3 0x508A14
+
+#define mmDMA0_QM_ARB_CFG_1 0x508A18
+
+#define mmDMA0_QM_ARB_MST_AVAIL_CRED_0 0x508A20
+
+#define mmDMA0_QM_ARB_MST_AVAIL_CRED_1 0x508A24
+
+#define mmDMA0_QM_ARB_MST_AVAIL_CRED_2 0x508A28
+
+#define mmDMA0_QM_ARB_MST_AVAIL_CRED_3 0x508A2C
+
+#define mmDMA0_QM_ARB_MST_AVAIL_CRED_4 0x508A30
+
+#define mmDMA0_QM_ARB_MST_AVAIL_CRED_5 0x508A34
+
+#define mmDMA0_QM_ARB_MST_AVAIL_CRED_6 0x508A38
+
+#define mmDMA0_QM_ARB_MST_AVAIL_CRED_7 0x508A3C
+
+#define mmDMA0_QM_ARB_MST_AVAIL_CRED_8 0x508A40
+
+#define mmDMA0_QM_ARB_MST_AVAIL_CRED_9 0x508A44
+
+#define mmDMA0_QM_ARB_MST_AVAIL_CRED_10 0x508A48
+
+#define mmDMA0_QM_ARB_MST_AVAIL_CRED_11 0x508A4C
+
+#define mmDMA0_QM_ARB_MST_AVAIL_CRED_12 0x508A50
+
+#define mmDMA0_QM_ARB_MST_AVAIL_CRED_13 0x508A54
+
+#define mmDMA0_QM_ARB_MST_AVAIL_CRED_14 0x508A58
+
+#define mmDMA0_QM_ARB_MST_AVAIL_CRED_15 0x508A5C
+
+#define mmDMA0_QM_ARB_MST_AVAIL_CRED_16 0x508A60
+
+#define mmDMA0_QM_ARB_MST_AVAIL_CRED_17 0x508A64
+
+#define mmDMA0_QM_ARB_MST_AVAIL_CRED_18 0x508A68
+
+#define mmDMA0_QM_ARB_MST_AVAIL_CRED_19 0x508A6C
+
+#define mmDMA0_QM_ARB_MST_AVAIL_CRED_20 0x508A70
+
+#define mmDMA0_QM_ARB_MST_AVAIL_CRED_21 0x508A74
+
+#define mmDMA0_QM_ARB_MST_AVAIL_CRED_22 0x508A78
+
+#define mmDMA0_QM_ARB_MST_AVAIL_CRED_23 0x508A7C
+
+#define mmDMA0_QM_ARB_MST_AVAIL_CRED_24 0x508A80
+
+#define mmDMA0_QM_ARB_MST_AVAIL_CRED_25 0x508A84
+
+#define mmDMA0_QM_ARB_MST_AVAIL_CRED_26 0x508A88
+
+#define mmDMA0_QM_ARB_MST_AVAIL_CRED_27 0x508A8C
+
+#define mmDMA0_QM_ARB_MST_AVAIL_CRED_28 0x508A90
+
+#define mmDMA0_QM_ARB_MST_AVAIL_CRED_29 0x508A94
+
+#define mmDMA0_QM_ARB_MST_AVAIL_CRED_30 0x508A98
+
+#define mmDMA0_QM_ARB_MST_AVAIL_CRED_31 0x508A9C
+
+#define mmDMA0_QM_ARB_MST_CRED_INC 0x508AA0
+
+#define mmDMA0_QM_ARB_MST_CHOISE_PUSH_OFST_0 0x508AA4
+
+#define mmDMA0_QM_ARB_MST_CHOISE_PUSH_OFST_1 0x508AA8
+
+#define mmDMA0_QM_ARB_MST_CHOISE_PUSH_OFST_2 0x508AAC
+
+#define mmDMA0_QM_ARB_MST_CHOISE_PUSH_OFST_3 0x508AB0
+
+#define mmDMA0_QM_ARB_MST_CHOISE_PUSH_OFST_4 0x508AB4
+
+#define mmDMA0_QM_ARB_MST_CHOISE_PUSH_OFST_5 0x508AB8
+
+#define mmDMA0_QM_ARB_MST_CHOISE_PUSH_OFST_6 0x508ABC
+
+#define mmDMA0_QM_ARB_MST_CHOISE_PUSH_OFST_7 0x508AC0
+
+#define mmDMA0_QM_ARB_MST_CHOISE_PUSH_OFST_8 0x508AC4
+
+#define mmDMA0_QM_ARB_MST_CHOISE_PUSH_OFST_9 0x508AC8
+
+#define mmDMA0_QM_ARB_MST_CHOISE_PUSH_OFST_10 0x508ACC
+
+#define mmDMA0_QM_ARB_MST_CHOISE_PUSH_OFST_11 0x508AD0
+
+#define mmDMA0_QM_ARB_MST_CHOISE_PUSH_OFST_12 0x508AD4
+
+#define mmDMA0_QM_ARB_MST_CHOISE_PUSH_OFST_13 0x508AD8
+
+#define mmDMA0_QM_ARB_MST_CHOISE_PUSH_OFST_14 0x508ADC
+
+#define mmDMA0_QM_ARB_MST_CHOISE_PUSH_OFST_15 0x508AE0
+
+#define mmDMA0_QM_ARB_MST_CHOISE_PUSH_OFST_16 0x508AE4
+
+#define mmDMA0_QM_ARB_MST_CHOISE_PUSH_OFST_17 0x508AE8
+
+#define mmDMA0_QM_ARB_MST_CHOISE_PUSH_OFST_18 0x508AEC
+
+#define mmDMA0_QM_ARB_MST_CHOISE_PUSH_OFST_19 0x508AF0
+
+#define mmDMA0_QM_ARB_MST_CHOISE_PUSH_OFST_20 0x508AF4
+
+#define mmDMA0_QM_ARB_MST_CHOISE_PUSH_OFST_21 0x508AF8
+
+#define mmDMA0_QM_ARB_MST_CHOISE_PUSH_OFST_22 0x508AFC
+
+#define mmDMA0_QM_ARB_MST_CHOISE_PUSH_OFST_23 0x508B00
+
+#define mmDMA0_QM_ARB_MST_CHOISE_PUSH_OFST_24 0x508B04
+
+#define mmDMA0_QM_ARB_MST_CHOISE_PUSH_OFST_25 0x508B08
+
+#define mmDMA0_QM_ARB_MST_CHOISE_PUSH_OFST_26 0x508B0C
+
+#define mmDMA0_QM_ARB_MST_CHOISE_PUSH_OFST_27 0x508B10
+
+#define mmDMA0_QM_ARB_MST_CHOISE_PUSH_OFST_28 0x508B14
+
+#define mmDMA0_QM_ARB_MST_CHOISE_PUSH_OFST_29 0x508B18
+
+#define mmDMA0_QM_ARB_MST_CHOISE_PUSH_OFST_30 0x508B1C
+
+#define mmDMA0_QM_ARB_MST_CHOISE_PUSH_OFST_31 0x508B20
+
+#define mmDMA0_QM_ARB_SLV_MASTER_INC_CRED_OFST 0x508B28
+
+#define mmDMA0_QM_ARB_MST_SLAVE_EN 0x508B2C
+
+#define mmDMA0_QM_ARB_MST_QUIET_PER 0x508B34
+
+#define mmDMA0_QM_ARB_SLV_CHOISE_WDT 0x508B38
+
+#define mmDMA0_QM_ARB_SLV_ID 0x508B3C
+
+#define mmDMA0_QM_ARB_MSG_MAX_INFLIGHT 0x508B44
+
+#define mmDMA0_QM_ARB_MSG_AWUSER_31_11 0x508B48
+
+#define mmDMA0_QM_ARB_MSG_AWUSER_SEC_PROP 0x508B4C
+
+#define mmDMA0_QM_ARB_MSG_AWUSER_NON_SEC_PROP 0x508B50
+
+#define mmDMA0_QM_ARB_BASE_LO 0x508B54
+
+#define mmDMA0_QM_ARB_BASE_HI 0x508B58
+
+#define mmDMA0_QM_ARB_STATE_STS 0x508B80
+
+#define mmDMA0_QM_ARB_CHOISE_FULLNESS_STS 0x508B84
+
+#define mmDMA0_QM_ARB_MSG_STS 0x508B88
+
+#define mmDMA0_QM_ARB_SLV_CHOISE_Q_HEAD 0x508B8C
+
+#define mmDMA0_QM_ARB_ERR_CAUSE 0x508B9C
+
+#define mmDMA0_QM_ARB_ERR_MSG_EN 0x508BA0
+
+#define mmDMA0_QM_ARB_ERR_STS_DRP 0x508BA8
+
+#define mmDMA0_QM_ARB_MST_CRED_STS_0 0x508BB0
+
+#define mmDMA0_QM_ARB_MST_CRED_STS_1 0x508BB4
+
+#define mmDMA0_QM_ARB_MST_CRED_STS_2 0x508BB8
+
+#define mmDMA0_QM_ARB_MST_CRED_STS_3 0x508BBC
+
+#define mmDMA0_QM_ARB_MST_CRED_STS_4 0x508BC0
+
+#define mmDMA0_QM_ARB_MST_CRED_STS_5 0x508BC4
+
+#define mmDMA0_QM_ARB_MST_CRED_STS_6 0x508BC8
+
+#define mmDMA0_QM_ARB_MST_CRED_STS_7 0x508BCC
+
+#define mmDMA0_QM_ARB_MST_CRED_STS_8 0x508BD0
+
+#define mmDMA0_QM_ARB_MST_CRED_STS_9 0x508BD4
+
+#define mmDMA0_QM_ARB_MST_CRED_STS_10 0x508BD8
+
+#define mmDMA0_QM_ARB_MST_CRED_STS_11 0x508BDC
+
+#define mmDMA0_QM_ARB_MST_CRED_STS_12 0x508BE0
+
+#define mmDMA0_QM_ARB_MST_CRED_STS_13 0x508BE4
+
+#define mmDMA0_QM_ARB_MST_CRED_STS_14 0x508BE8
+
+#define mmDMA0_QM_ARB_MST_CRED_STS_15 0x508BEC
+
+#define mmDMA0_QM_ARB_MST_CRED_STS_16 0x508BF0
+
+#define mmDMA0_QM_ARB_MST_CRED_STS_17 0x508BF4
+
+#define mmDMA0_QM_ARB_MST_CRED_STS_18 0x508BF8
+
+#define mmDMA0_QM_ARB_MST_CRED_STS_19 0x508BFC
+
+#define mmDMA0_QM_ARB_MST_CRED_STS_20 0x508C00
+
+#define mmDMA0_QM_ARB_MST_CRED_STS_21 0x508C04
+
+#define mmDMA0_QM_ARB_MST_CRED_STS_22 0x508C08
+
+#define mmDMA0_QM_ARB_MST_CRED_STS_23 0x508C0C
+
+#define mmDMA0_QM_ARB_MST_CRED_STS_24 0x508C10
+
+#define mmDMA0_QM_ARB_MST_CRED_STS_25 0x508C14
+
+#define mmDMA0_QM_ARB_MST_CRED_STS_26 0x508C18
+
+#define mmDMA0_QM_ARB_MST_CRED_STS_27 0x508C1C
+
+#define mmDMA0_QM_ARB_MST_CRED_STS_28 0x508C20
+
+#define mmDMA0_QM_ARB_MST_CRED_STS_29 0x508C24
+
+#define mmDMA0_QM_ARB_MST_CRED_STS_30 0x508C28
+
+#define mmDMA0_QM_ARB_MST_CRED_STS_31 0x508C2C
+
+#define mmDMA0_QM_CGM_CFG 0x508C70
+
+#define mmDMA0_QM_CGM_STS 0x508C74
+
+#define mmDMA0_QM_CGM_CFG1 0x508C78
+
+#define mmDMA0_QM_LOCAL_RANGE_BASE 0x508C80
+
+#define mmDMA0_QM_LOCAL_RANGE_SIZE 0x508C84
+
+#define mmDMA0_QM_CSMR_STRICT_PRIO_CFG 0x508C90
+
+#define mmDMA0_QM_HBW_RD_RATE_LIM_CFG_1 0x508C94
+
+#define mmDMA0_QM_LBW_WR_RATE_LIM_CFG_0 0x508C98
+
+#define mmDMA0_QM_LBW_WR_RATE_LIM_CFG_1 0x508C9C
+
+#define mmDMA0_QM_HBW_RD_RATE_LIM_CFG_0 0x508CA0
+
+#define mmDMA0_QM_GLBL_AXCACHE 0x508CA4
+
+#define mmDMA0_QM_IND_GW_APB_CFG 0x508CB0
+
+#define mmDMA0_QM_IND_GW_APB_WDATA 0x508CB4
+
+#define mmDMA0_QM_IND_GW_APB_RDATA 0x508CB8
+
+#define mmDMA0_QM_IND_GW_APB_STATUS 0x508CBC
+
+#define mmDMA0_QM_GLBL_ERR_ADDR_LO 0x508CD0
+
+#define mmDMA0_QM_GLBL_ERR_ADDR_HI 0x508CD4
+
+#define mmDMA0_QM_GLBL_ERR_WDATA 0x508CD8
+
+#define mmDMA0_QM_GLBL_MEM_INIT_BUSY 0x508D00
+
+#endif /* ASIC_REG_DMA0_QM_REGS_H_ */
diff --git a/drivers/accel/habanalabs/include/gaudi/asic_reg/dma1_core_regs.h b/drivers/accel/habanalabs/include/gaudi/asic_reg/dma1_core_regs.h
new file mode 100644
index 0000000000..4d8d8f26c5
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi/asic_reg/dma1_core_regs.h
@@ -0,0 +1,156 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2016-2018 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ ** DO NOT EDIT BELOW **
+ ************************************/
+
+#ifndef ASIC_REG_DMA1_CORE_REGS_H_
+#define ASIC_REG_DMA1_CORE_REGS_H_
+
+/*
+ *****************************************
+ * DMA1_CORE (Prototype: DMA_CORE)
+ *****************************************
+ */
+
+#define mmDMA1_CORE_CFG_0 0x520000
+
+#define mmDMA1_CORE_CFG_1 0x520004
+
+#define mmDMA1_CORE_LBW_MAX_OUTSTAND 0x520008
+
+#define mmDMA1_CORE_SRC_BASE_LO 0x520014
+
+#define mmDMA1_CORE_SRC_BASE_HI 0x520018
+
+#define mmDMA1_CORE_DST_BASE_LO 0x52001C
+
+#define mmDMA1_CORE_DST_BASE_HI 0x520020
+
+#define mmDMA1_CORE_SRC_TSIZE_1 0x52002C
+
+#define mmDMA1_CORE_SRC_STRIDE_1 0x520030
+
+#define mmDMA1_CORE_SRC_TSIZE_2 0x520034
+
+#define mmDMA1_CORE_SRC_STRIDE_2 0x520038
+
+#define mmDMA1_CORE_SRC_TSIZE_3 0x52003C
+
+#define mmDMA1_CORE_SRC_STRIDE_3 0x520040
+
+#define mmDMA1_CORE_SRC_TSIZE_4 0x520044
+
+#define mmDMA1_CORE_SRC_STRIDE_4 0x520048
+
+#define mmDMA1_CORE_SRC_TSIZE_0 0x52004C
+
+#define mmDMA1_CORE_DST_TSIZE_1 0x520054
+
+#define mmDMA1_CORE_DST_STRIDE_1 0x520058
+
+#define mmDMA1_CORE_DST_TSIZE_2 0x52005C
+
+#define mmDMA1_CORE_DST_STRIDE_2 0x520060
+
+#define mmDMA1_CORE_DST_TSIZE_3 0x520064
+
+#define mmDMA1_CORE_DST_STRIDE_3 0x520068
+
+#define mmDMA1_CORE_DST_TSIZE_4 0x52006C
+
+#define mmDMA1_CORE_DST_STRIDE_4 0x520070
+
+#define mmDMA1_CORE_DST_TSIZE_0 0x520074
+
+#define mmDMA1_CORE_COMMIT 0x520078
+
+#define mmDMA1_CORE_WR_COMP_WDATA 0x52007C
+
+#define mmDMA1_CORE_WR_COMP_ADDR_LO 0x520080
+
+#define mmDMA1_CORE_WR_COMP_ADDR_HI 0x520084
+
+#define mmDMA1_CORE_WR_COMP_AWUSER_31_11 0x520088
+
+#define mmDMA1_CORE_TE_NUMROWS 0x520094
+
+#define mmDMA1_CORE_PROT 0x5200B8
+
+#define mmDMA1_CORE_SECURE_PROPS 0x5200F0
+
+#define mmDMA1_CORE_NON_SECURE_PROPS 0x5200F4
+
+#define mmDMA1_CORE_RD_MAX_OUTSTAND 0x520100
+
+#define mmDMA1_CORE_RD_MAX_SIZE 0x520104
+
+#define mmDMA1_CORE_RD_ARCACHE 0x520108
+
+#define mmDMA1_CORE_RD_ARUSER_31_11 0x520110
+
+#define mmDMA1_CORE_RD_INFLIGHTS 0x520114
+
+#define mmDMA1_CORE_WR_MAX_OUTSTAND 0x520120
+
+#define mmDMA1_CORE_WR_MAX_AWID 0x520124
+
+#define mmDMA1_CORE_WR_AWCACHE 0x520128
+
+#define mmDMA1_CORE_WR_AWUSER_31_11 0x520130
+
+#define mmDMA1_CORE_WR_INFLIGHTS 0x520134
+
+#define mmDMA1_CORE_RD_RATE_LIM_CFG_0 0x520150
+
+#define mmDMA1_CORE_RD_RATE_LIM_CFG_1 0x520154
+
+#define mmDMA1_CORE_WR_RATE_LIM_CFG_0 0x520158
+
+#define mmDMA1_CORE_WR_RATE_LIM_CFG_1 0x52015C
+
+#define mmDMA1_CORE_ERR_CFG 0x520160
+
+#define mmDMA1_CORE_ERR_CAUSE 0x520164
+
+#define mmDMA1_CORE_ERRMSG_ADDR_LO 0x520170
+
+#define mmDMA1_CORE_ERRMSG_ADDR_HI 0x520174
+
+#define mmDMA1_CORE_ERRMSG_WDATA 0x520178
+
+#define mmDMA1_CORE_STS0 0x520190
+
+#define mmDMA1_CORE_STS1 0x520194
+
+#define mmDMA1_CORE_RD_DBGMEM_ADD 0x520200
+
+#define mmDMA1_CORE_RD_DBGMEM_DATA_WR 0x520204
+
+#define mmDMA1_CORE_RD_DBGMEM_DATA_RD 0x520208
+
+#define mmDMA1_CORE_RD_DBGMEM_CTRL 0x52020C
+
+#define mmDMA1_CORE_RD_DBGMEM_RC 0x520210
+
+#define mmDMA1_CORE_DBG_HBW_AXI_AR_CNT 0x520220
+
+#define mmDMA1_CORE_DBG_HBW_AXI_AW_CNT 0x520224
+
+#define mmDMA1_CORE_DBG_LBW_AXI_AW_CNT 0x520228
+
+#define mmDMA1_CORE_DBG_DESC_CNT 0x52022C
+
+#define mmDMA1_CORE_DBG_STS 0x520230
+
+#define mmDMA1_CORE_DBG_RD_DESC_ID 0x520234
+
+#define mmDMA1_CORE_DBG_WR_DESC_ID 0x520238
+
+#endif /* ASIC_REG_DMA1_CORE_REGS_H_ */
diff --git a/drivers/accel/habanalabs/include/gaudi/asic_reg/dma1_qm_regs.h b/drivers/accel/habanalabs/include/gaudi/asic_reg/dma1_qm_regs.h
new file mode 100644
index 0000000000..c3ef300849
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi/asic_reg/dma1_qm_regs.h
@@ -0,0 +1,834 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2016-2018 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ ** DO NOT EDIT BELOW **
+ ************************************/
+
+#ifndef ASIC_REG_DMA1_QM_REGS_H_
+#define ASIC_REG_DMA1_QM_REGS_H_
+
+/*
+ *****************************************
+ * DMA1_QM (Prototype: QMAN)
+ *****************************************
+ */
+
+#define mmDMA1_QM_GLBL_CFG0 0x528000
+
+#define mmDMA1_QM_GLBL_CFG1 0x528004
+
+#define mmDMA1_QM_GLBL_PROT 0x528008
+
+#define mmDMA1_QM_GLBL_ERR_CFG 0x52800C
+
+#define mmDMA1_QM_GLBL_SECURE_PROPS_0 0x528010
+
+#define mmDMA1_QM_GLBL_SECURE_PROPS_1 0x528014
+
+#define mmDMA1_QM_GLBL_SECURE_PROPS_2 0x528018
+
+#define mmDMA1_QM_GLBL_SECURE_PROPS_3 0x52801C
+
+#define mmDMA1_QM_GLBL_SECURE_PROPS_4 0x528020
+
+#define mmDMA1_QM_GLBL_NON_SECURE_PROPS_0 0x528024
+
+#define mmDMA1_QM_GLBL_NON_SECURE_PROPS_1 0x528028
+
+#define mmDMA1_QM_GLBL_NON_SECURE_PROPS_2 0x52802C
+
+#define mmDMA1_QM_GLBL_NON_SECURE_PROPS_3 0x528030
+
+#define mmDMA1_QM_GLBL_NON_SECURE_PROPS_4 0x528034
+
+#define mmDMA1_QM_GLBL_STS0 0x528038
+
+#define mmDMA1_QM_GLBL_STS1_0 0x528040
+
+#define mmDMA1_QM_GLBL_STS1_1 0x528044
+
+#define mmDMA1_QM_GLBL_STS1_2 0x528048
+
+#define mmDMA1_QM_GLBL_STS1_3 0x52804C
+
+#define mmDMA1_QM_GLBL_STS1_4 0x528050
+
+#define mmDMA1_QM_GLBL_MSG_EN_0 0x528054
+
+#define mmDMA1_QM_GLBL_MSG_EN_1 0x528058
+
+#define mmDMA1_QM_GLBL_MSG_EN_2 0x52805C
+
+#define mmDMA1_QM_GLBL_MSG_EN_3 0x528060
+
+#define mmDMA1_QM_GLBL_MSG_EN_4 0x528068
+
+#define mmDMA1_QM_PQ_BASE_LO_0 0x528070
+
+#define mmDMA1_QM_PQ_BASE_LO_1 0x528074
+
+#define mmDMA1_QM_PQ_BASE_LO_2 0x528078
+
+#define mmDMA1_QM_PQ_BASE_LO_3 0x52807C
+
+#define mmDMA1_QM_PQ_BASE_HI_0 0x528080
+
+#define mmDMA1_QM_PQ_BASE_HI_1 0x528084
+
+#define mmDMA1_QM_PQ_BASE_HI_2 0x528088
+
+#define mmDMA1_QM_PQ_BASE_HI_3 0x52808C
+
+#define mmDMA1_QM_PQ_SIZE_0 0x528090
+
+#define mmDMA1_QM_PQ_SIZE_1 0x528094
+
+#define mmDMA1_QM_PQ_SIZE_2 0x528098
+
+#define mmDMA1_QM_PQ_SIZE_3 0x52809C
+
+#define mmDMA1_QM_PQ_PI_0 0x5280A0
+
+#define mmDMA1_QM_PQ_PI_1 0x5280A4
+
+#define mmDMA1_QM_PQ_PI_2 0x5280A8
+
+#define mmDMA1_QM_PQ_PI_3 0x5280AC
+
+#define mmDMA1_QM_PQ_CI_0 0x5280B0
+
+#define mmDMA1_QM_PQ_CI_1 0x5280B4
+
+#define mmDMA1_QM_PQ_CI_2 0x5280B8
+
+#define mmDMA1_QM_PQ_CI_3 0x5280BC
+
+#define mmDMA1_QM_PQ_CFG0_0 0x5280C0
+
+#define mmDMA1_QM_PQ_CFG0_1 0x5280C4
+
+#define mmDMA1_QM_PQ_CFG0_2 0x5280C8
+
+#define mmDMA1_QM_PQ_CFG0_3 0x5280CC
+
+#define mmDMA1_QM_PQ_CFG1_0 0x5280D0
+
+#define mmDMA1_QM_PQ_CFG1_1 0x5280D4
+
+#define mmDMA1_QM_PQ_CFG1_2 0x5280D8
+
+#define mmDMA1_QM_PQ_CFG1_3 0x5280DC
+
+#define mmDMA1_QM_PQ_ARUSER_31_11_0 0x5280E0
+
+#define mmDMA1_QM_PQ_ARUSER_31_11_1 0x5280E4
+
+#define mmDMA1_QM_PQ_ARUSER_31_11_2 0x5280E8
+
+#define mmDMA1_QM_PQ_ARUSER_31_11_3 0x5280EC
+
+#define mmDMA1_QM_PQ_STS0_0 0x5280F0
+
+#define mmDMA1_QM_PQ_STS0_1 0x5280F4
+
+#define mmDMA1_QM_PQ_STS0_2 0x5280F8
+
+#define mmDMA1_QM_PQ_STS0_3 0x5280FC
+
+#define mmDMA1_QM_PQ_STS1_0 0x528100
+
+#define mmDMA1_QM_PQ_STS1_1 0x528104
+
+#define mmDMA1_QM_PQ_STS1_2 0x528108
+
+#define mmDMA1_QM_PQ_STS1_3 0x52810C
+
+#define mmDMA1_QM_CQ_CFG0_0 0x528110
+
+#define mmDMA1_QM_CQ_CFG0_1 0x528114
+
+#define mmDMA1_QM_CQ_CFG0_2 0x528118
+
+#define mmDMA1_QM_CQ_CFG0_3 0x52811C
+
+#define mmDMA1_QM_CQ_CFG0_4 0x528120
+
+#define mmDMA1_QM_CQ_CFG1_0 0x528124
+
+#define mmDMA1_QM_CQ_CFG1_1 0x528128
+
+#define mmDMA1_QM_CQ_CFG1_2 0x52812C
+
+#define mmDMA1_QM_CQ_CFG1_3 0x528130
+
+#define mmDMA1_QM_CQ_CFG1_4 0x528134
+
+#define mmDMA1_QM_CQ_ARUSER_31_11_0 0x528138
+
+#define mmDMA1_QM_CQ_ARUSER_31_11_1 0x52813C
+
+#define mmDMA1_QM_CQ_ARUSER_31_11_2 0x528140
+
+#define mmDMA1_QM_CQ_ARUSER_31_11_3 0x528144
+
+#define mmDMA1_QM_CQ_ARUSER_31_11_4 0x528148
+
+#define mmDMA1_QM_CQ_STS0_0 0x52814C
+
+#define mmDMA1_QM_CQ_STS0_1 0x528150
+
+#define mmDMA1_QM_CQ_STS0_2 0x528154
+
+#define mmDMA1_QM_CQ_STS0_3 0x528158
+
+#define mmDMA1_QM_CQ_STS0_4 0x52815C
+
+#define mmDMA1_QM_CQ_STS1_0 0x528160
+
+#define mmDMA1_QM_CQ_STS1_1 0x528164
+
+#define mmDMA1_QM_CQ_STS1_2 0x528168
+
+#define mmDMA1_QM_CQ_STS1_3 0x52816C
+
+#define mmDMA1_QM_CQ_STS1_4 0x528170
+
+#define mmDMA1_QM_CQ_PTR_LO_0 0x528174
+
+#define mmDMA1_QM_CQ_PTR_HI_0 0x528178
+
+#define mmDMA1_QM_CQ_TSIZE_0 0x52817C
+
+#define mmDMA1_QM_CQ_CTL_0 0x528180
+
+#define mmDMA1_QM_CQ_PTR_LO_1 0x528184
+
+#define mmDMA1_QM_CQ_PTR_HI_1 0x528188
+
+#define mmDMA1_QM_CQ_TSIZE_1 0x52818C
+
+#define mmDMA1_QM_CQ_CTL_1 0x528190
+
+#define mmDMA1_QM_CQ_PTR_LO_2 0x528194
+
+#define mmDMA1_QM_CQ_PTR_HI_2 0x528198
+
+#define mmDMA1_QM_CQ_TSIZE_2 0x52819C
+
+#define mmDMA1_QM_CQ_CTL_2 0x5281A0
+
+#define mmDMA1_QM_CQ_PTR_LO_3 0x5281A4
+
+#define mmDMA1_QM_CQ_PTR_HI_3 0x5281A8
+
+#define mmDMA1_QM_CQ_TSIZE_3 0x5281AC
+
+#define mmDMA1_QM_CQ_CTL_3 0x5281B0
+
+#define mmDMA1_QM_CQ_PTR_LO_4 0x5281B4
+
+#define mmDMA1_QM_CQ_PTR_HI_4 0x5281B8
+
+#define mmDMA1_QM_CQ_TSIZE_4 0x5281BC
+
+#define mmDMA1_QM_CQ_CTL_4 0x5281C0
+
+#define mmDMA1_QM_CQ_PTR_LO_STS_0 0x5281C4
+
+#define mmDMA1_QM_CQ_PTR_LO_STS_1 0x5281C8
+
+#define mmDMA1_QM_CQ_PTR_LO_STS_2 0x5281CC
+
+#define mmDMA1_QM_CQ_PTR_LO_STS_3 0x5281D0
+
+#define mmDMA1_QM_CQ_PTR_LO_STS_4 0x5281D4
+
+#define mmDMA1_QM_CQ_PTR_HI_STS_0 0x5281D8
+
+#define mmDMA1_QM_CQ_PTR_HI_STS_1 0x5281DC
+
+#define mmDMA1_QM_CQ_PTR_HI_STS_2 0x5281E0
+
+#define mmDMA1_QM_CQ_PTR_HI_STS_3 0x5281E4
+
+#define mmDMA1_QM_CQ_PTR_HI_STS_4 0x5281E8
+
+#define mmDMA1_QM_CQ_TSIZE_STS_0 0x5281EC
+
+#define mmDMA1_QM_CQ_TSIZE_STS_1 0x5281F0
+
+#define mmDMA1_QM_CQ_TSIZE_STS_2 0x5281F4
+
+#define mmDMA1_QM_CQ_TSIZE_STS_3 0x5281F8
+
+#define mmDMA1_QM_CQ_TSIZE_STS_4 0x5281FC
+
+#define mmDMA1_QM_CQ_CTL_STS_0 0x528200
+
+#define mmDMA1_QM_CQ_CTL_STS_1 0x528204
+
+#define mmDMA1_QM_CQ_CTL_STS_2 0x528208
+
+#define mmDMA1_QM_CQ_CTL_STS_3 0x52820C
+
+#define mmDMA1_QM_CQ_CTL_STS_4 0x528210
+
+#define mmDMA1_QM_CQ_IFIFO_CNT_0 0x528214
+
+#define mmDMA1_QM_CQ_IFIFO_CNT_1 0x528218
+
+#define mmDMA1_QM_CQ_IFIFO_CNT_2 0x52821C
+
+#define mmDMA1_QM_CQ_IFIFO_CNT_3 0x528220
+
+#define mmDMA1_QM_CQ_IFIFO_CNT_4 0x528224
+
+#define mmDMA1_QM_CP_MSG_BASE0_ADDR_LO_0 0x528228
+
+#define mmDMA1_QM_CP_MSG_BASE0_ADDR_LO_1 0x52822C
+
+#define mmDMA1_QM_CP_MSG_BASE0_ADDR_LO_2 0x528230
+
+#define mmDMA1_QM_CP_MSG_BASE0_ADDR_LO_3 0x528234
+
+#define mmDMA1_QM_CP_MSG_BASE0_ADDR_LO_4 0x528238
+
+#define mmDMA1_QM_CP_MSG_BASE0_ADDR_HI_0 0x52823C
+
+#define mmDMA1_QM_CP_MSG_BASE0_ADDR_HI_1 0x528240
+
+#define mmDMA1_QM_CP_MSG_BASE0_ADDR_HI_2 0x528244
+
+#define mmDMA1_QM_CP_MSG_BASE0_ADDR_HI_3 0x528248
+
+#define mmDMA1_QM_CP_MSG_BASE0_ADDR_HI_4 0x52824C
+
+#define mmDMA1_QM_CP_MSG_BASE1_ADDR_LO_0 0x528250
+
+#define mmDMA1_QM_CP_MSG_BASE1_ADDR_LO_1 0x528254
+
+#define mmDMA1_QM_CP_MSG_BASE1_ADDR_LO_2 0x528258
+
+#define mmDMA1_QM_CP_MSG_BASE1_ADDR_LO_3 0x52825C
+
+#define mmDMA1_QM_CP_MSG_BASE1_ADDR_LO_4 0x528260
+
+#define mmDMA1_QM_CP_MSG_BASE1_ADDR_HI_0 0x528264
+
+#define mmDMA1_QM_CP_MSG_BASE1_ADDR_HI_1 0x528268
+
+#define mmDMA1_QM_CP_MSG_BASE1_ADDR_HI_2 0x52826C
+
+#define mmDMA1_QM_CP_MSG_BASE1_ADDR_HI_3 0x528270
+
+#define mmDMA1_QM_CP_MSG_BASE1_ADDR_HI_4 0x528274
+
+#define mmDMA1_QM_CP_MSG_BASE2_ADDR_LO_0 0x528278
+
+#define mmDMA1_QM_CP_MSG_BASE2_ADDR_LO_1 0x52827C
+
+#define mmDMA1_QM_CP_MSG_BASE2_ADDR_LO_2 0x528280
+
+#define mmDMA1_QM_CP_MSG_BASE2_ADDR_LO_3 0x528284
+
+#define mmDMA1_QM_CP_MSG_BASE2_ADDR_LO_4 0x528288
+
+#define mmDMA1_QM_CP_MSG_BASE2_ADDR_HI_0 0x52828C
+
+#define mmDMA1_QM_CP_MSG_BASE2_ADDR_HI_1 0x528290
+
+#define mmDMA1_QM_CP_MSG_BASE2_ADDR_HI_2 0x528294
+
+#define mmDMA1_QM_CP_MSG_BASE2_ADDR_HI_3 0x528298
+
+#define mmDMA1_QM_CP_MSG_BASE2_ADDR_HI_4 0x52829C
+
+#define mmDMA1_QM_CP_MSG_BASE3_ADDR_LO_0 0x5282A0
+
+#define mmDMA1_QM_CP_MSG_BASE3_ADDR_LO_1 0x5282A4
+
+#define mmDMA1_QM_CP_MSG_BASE3_ADDR_LO_2 0x5282A8
+
+#define mmDMA1_QM_CP_MSG_BASE3_ADDR_LO_3 0x5282AC
+
+#define mmDMA1_QM_CP_MSG_BASE3_ADDR_LO_4 0x5282B0
+
+#define mmDMA1_QM_CP_MSG_BASE3_ADDR_HI_0 0x5282B4
+
+#define mmDMA1_QM_CP_MSG_BASE3_ADDR_HI_1 0x5282B8
+
+#define mmDMA1_QM_CP_MSG_BASE3_ADDR_HI_2 0x5282BC
+
+#define mmDMA1_QM_CP_MSG_BASE3_ADDR_HI_3 0x5282C0
+
+#define mmDMA1_QM_CP_MSG_BASE3_ADDR_HI_4 0x5282C4
+
+#define mmDMA1_QM_CP_LDMA_TSIZE_OFFSET_0 0x5282C8
+
+#define mmDMA1_QM_CP_LDMA_TSIZE_OFFSET_1 0x5282CC
+
+#define mmDMA1_QM_CP_LDMA_TSIZE_OFFSET_2 0x5282D0
+
+#define mmDMA1_QM_CP_LDMA_TSIZE_OFFSET_3 0x5282D4
+
+#define mmDMA1_QM_CP_LDMA_TSIZE_OFFSET_4 0x5282D8
+
+#define mmDMA1_QM_CP_LDMA_SRC_BASE_LO_OFFSET_0 0x5282E0
+
+#define mmDMA1_QM_CP_LDMA_SRC_BASE_LO_OFFSET_1 0x5282E4
+
+#define mmDMA1_QM_CP_LDMA_SRC_BASE_LO_OFFSET_2 0x5282E8
+
+#define mmDMA1_QM_CP_LDMA_SRC_BASE_LO_OFFSET_3 0x5282EC
+
+#define mmDMA1_QM_CP_LDMA_SRC_BASE_LO_OFFSET_4 0x5282F0
+
+#define mmDMA1_QM_CP_LDMA_DST_BASE_LO_OFFSET_0 0x5282F4
+
+#define mmDMA1_QM_CP_LDMA_DST_BASE_LO_OFFSET_1 0x5282F8
+
+#define mmDMA1_QM_CP_LDMA_DST_BASE_LO_OFFSET_2 0x5282FC
+
+#define mmDMA1_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 0x528300
+
+#define mmDMA1_QM_CP_LDMA_DST_BASE_LO_OFFSET_4 0x528304
+
+#define mmDMA1_QM_CP_FENCE0_RDATA_0 0x528308
+
+#define mmDMA1_QM_CP_FENCE0_RDATA_1 0x52830C
+
+#define mmDMA1_QM_CP_FENCE0_RDATA_2 0x528310
+
+#define mmDMA1_QM_CP_FENCE0_RDATA_3 0x528314
+
+#define mmDMA1_QM_CP_FENCE0_RDATA_4 0x528318
+
+#define mmDMA1_QM_CP_FENCE1_RDATA_0 0x52831C
+
+#define mmDMA1_QM_CP_FENCE1_RDATA_1 0x528320
+
+#define mmDMA1_QM_CP_FENCE1_RDATA_2 0x528324
+
+#define mmDMA1_QM_CP_FENCE1_RDATA_3 0x528328
+
+#define mmDMA1_QM_CP_FENCE1_RDATA_4 0x52832C
+
+#define mmDMA1_QM_CP_FENCE2_RDATA_0 0x528330
+
+#define mmDMA1_QM_CP_FENCE2_RDATA_1 0x528334
+
+#define mmDMA1_QM_CP_FENCE2_RDATA_2 0x528338
+
+#define mmDMA1_QM_CP_FENCE2_RDATA_3 0x52833C
+
+#define mmDMA1_QM_CP_FENCE2_RDATA_4 0x528340
+
+#define mmDMA1_QM_CP_FENCE3_RDATA_0 0x528344
+
+#define mmDMA1_QM_CP_FENCE3_RDATA_1 0x528348
+
+#define mmDMA1_QM_CP_FENCE3_RDATA_2 0x52834C
+
+#define mmDMA1_QM_CP_FENCE3_RDATA_3 0x528350
+
+#define mmDMA1_QM_CP_FENCE3_RDATA_4 0x528354
+
+#define mmDMA1_QM_CP_FENCE0_CNT_0 0x528358
+
+#define mmDMA1_QM_CP_FENCE0_CNT_1 0x52835C
+
+#define mmDMA1_QM_CP_FENCE0_CNT_2 0x528360
+
+#define mmDMA1_QM_CP_FENCE0_CNT_3 0x528364
+
+#define mmDMA1_QM_CP_FENCE0_CNT_4 0x528368
+
+#define mmDMA1_QM_CP_FENCE1_CNT_0 0x52836C
+
+#define mmDMA1_QM_CP_FENCE1_CNT_1 0x528370
+
+#define mmDMA1_QM_CP_FENCE1_CNT_2 0x528374
+
+#define mmDMA1_QM_CP_FENCE1_CNT_3 0x528378
+
+#define mmDMA1_QM_CP_FENCE1_CNT_4 0x52837C
+
+#define mmDMA1_QM_CP_FENCE2_CNT_0 0x528380
+
+#define mmDMA1_QM_CP_FENCE2_CNT_1 0x528384
+
+#define mmDMA1_QM_CP_FENCE2_CNT_2 0x528388
+
+#define mmDMA1_QM_CP_FENCE2_CNT_3 0x52838C
+
+#define mmDMA1_QM_CP_FENCE2_CNT_4 0x528390
+
+#define mmDMA1_QM_CP_FENCE3_CNT_0 0x528394
+
+#define mmDMA1_QM_CP_FENCE3_CNT_1 0x528398
+
+#define mmDMA1_QM_CP_FENCE3_CNT_2 0x52839C
+
+#define mmDMA1_QM_CP_FENCE3_CNT_3 0x5283A0
+
+#define mmDMA1_QM_CP_FENCE3_CNT_4 0x5283A4
+
+#define mmDMA1_QM_CP_STS_0 0x5283A8
+
+#define mmDMA1_QM_CP_STS_1 0x5283AC
+
+#define mmDMA1_QM_CP_STS_2 0x5283B0
+
+#define mmDMA1_QM_CP_STS_3 0x5283B4
+
+#define mmDMA1_QM_CP_STS_4 0x5283B8
+
+#define mmDMA1_QM_CP_CURRENT_INST_LO_0 0x5283BC
+
+#define mmDMA1_QM_CP_CURRENT_INST_LO_1 0x5283C0
+
+#define mmDMA1_QM_CP_CURRENT_INST_LO_2 0x5283C4
+
+#define mmDMA1_QM_CP_CURRENT_INST_LO_3 0x5283C8
+
+#define mmDMA1_QM_CP_CURRENT_INST_LO_4 0x5283CC
+
+#define mmDMA1_QM_CP_CURRENT_INST_HI_0 0x5283D0
+
+#define mmDMA1_QM_CP_CURRENT_INST_HI_1 0x5283D4
+
+#define mmDMA1_QM_CP_CURRENT_INST_HI_2 0x5283D8
+
+#define mmDMA1_QM_CP_CURRENT_INST_HI_3 0x5283DC
+
+#define mmDMA1_QM_CP_CURRENT_INST_HI_4 0x5283E0
+
+#define mmDMA1_QM_CP_BARRIER_CFG_0 0x5283F4
+
+#define mmDMA1_QM_CP_BARRIER_CFG_1 0x5283F8
+
+#define mmDMA1_QM_CP_BARRIER_CFG_2 0x5283FC
+
+#define mmDMA1_QM_CP_BARRIER_CFG_3 0x528400
+
+#define mmDMA1_QM_CP_BARRIER_CFG_4 0x528404
+
+#define mmDMA1_QM_CP_DBG_0_0 0x528408
+
+#define mmDMA1_QM_CP_DBG_0_1 0x52840C
+
+#define mmDMA1_QM_CP_DBG_0_2 0x528410
+
+#define mmDMA1_QM_CP_DBG_0_3 0x528414
+
+#define mmDMA1_QM_CP_DBG_0_4 0x528418
+
+#define mmDMA1_QM_CP_ARUSER_31_11_0 0x52841C
+
+#define mmDMA1_QM_CP_ARUSER_31_11_1 0x528420
+
+#define mmDMA1_QM_CP_ARUSER_31_11_2 0x528424
+
+#define mmDMA1_QM_CP_ARUSER_31_11_3 0x528428
+
+#define mmDMA1_QM_CP_ARUSER_31_11_4 0x52842C
+
+#define mmDMA1_QM_CP_AWUSER_31_11_0 0x528430
+
+#define mmDMA1_QM_CP_AWUSER_31_11_1 0x528434
+
+#define mmDMA1_QM_CP_AWUSER_31_11_2 0x528438
+
+#define mmDMA1_QM_CP_AWUSER_31_11_3 0x52843C
+
+#define mmDMA1_QM_CP_AWUSER_31_11_4 0x528440
+
+#define mmDMA1_QM_ARB_CFG_0 0x528A00
+
+#define mmDMA1_QM_ARB_CHOISE_Q_PUSH 0x528A04
+
+#define mmDMA1_QM_ARB_WRR_WEIGHT_0 0x528A08
+
+#define mmDMA1_QM_ARB_WRR_WEIGHT_1 0x528A0C
+
+#define mmDMA1_QM_ARB_WRR_WEIGHT_2 0x528A10
+
+#define mmDMA1_QM_ARB_WRR_WEIGHT_3 0x528A14
+
+#define mmDMA1_QM_ARB_CFG_1 0x528A18
+
+#define mmDMA1_QM_ARB_MST_AVAIL_CRED_0 0x528A20
+
+#define mmDMA1_QM_ARB_MST_AVAIL_CRED_1 0x528A24
+
+#define mmDMA1_QM_ARB_MST_AVAIL_CRED_2 0x528A28
+
+#define mmDMA1_QM_ARB_MST_AVAIL_CRED_3 0x528A2C
+
+#define mmDMA1_QM_ARB_MST_AVAIL_CRED_4 0x528A30
+
+#define mmDMA1_QM_ARB_MST_AVAIL_CRED_5 0x528A34
+
+#define mmDMA1_QM_ARB_MST_AVAIL_CRED_6 0x528A38
+
+#define mmDMA1_QM_ARB_MST_AVAIL_CRED_7 0x528A3C
+
+#define mmDMA1_QM_ARB_MST_AVAIL_CRED_8 0x528A40
+
+#define mmDMA1_QM_ARB_MST_AVAIL_CRED_9 0x528A44
+
+#define mmDMA1_QM_ARB_MST_AVAIL_CRED_10 0x528A48
+
+#define mmDMA1_QM_ARB_MST_AVAIL_CRED_11 0x528A4C
+
+#define mmDMA1_QM_ARB_MST_AVAIL_CRED_12 0x528A50
+
+#define mmDMA1_QM_ARB_MST_AVAIL_CRED_13 0x528A54
+
+#define mmDMA1_QM_ARB_MST_AVAIL_CRED_14 0x528A58
+
+#define mmDMA1_QM_ARB_MST_AVAIL_CRED_15 0x528A5C
+
+#define mmDMA1_QM_ARB_MST_AVAIL_CRED_16 0x528A60
+
+#define mmDMA1_QM_ARB_MST_AVAIL_CRED_17 0x528A64
+
+#define mmDMA1_QM_ARB_MST_AVAIL_CRED_18 0x528A68
+
+#define mmDMA1_QM_ARB_MST_AVAIL_CRED_19 0x528A6C
+
+#define mmDMA1_QM_ARB_MST_AVAIL_CRED_20 0x528A70
+
+#define mmDMA1_QM_ARB_MST_AVAIL_CRED_21 0x528A74
+
+#define mmDMA1_QM_ARB_MST_AVAIL_CRED_22 0x528A78
+
+#define mmDMA1_QM_ARB_MST_AVAIL_CRED_23 0x528A7C
+
+#define mmDMA1_QM_ARB_MST_AVAIL_CRED_24 0x528A80
+
+#define mmDMA1_QM_ARB_MST_AVAIL_CRED_25 0x528A84
+
+#define mmDMA1_QM_ARB_MST_AVAIL_CRED_26 0x528A88
+
+#define mmDMA1_QM_ARB_MST_AVAIL_CRED_27 0x528A8C
+
+#define mmDMA1_QM_ARB_MST_AVAIL_CRED_28 0x528A90
+
+#define mmDMA1_QM_ARB_MST_AVAIL_CRED_29 0x528A94
+
+#define mmDMA1_QM_ARB_MST_AVAIL_CRED_30 0x528A98
+
+#define mmDMA1_QM_ARB_MST_AVAIL_CRED_31 0x528A9C
+
+#define mmDMA1_QM_ARB_MST_CRED_INC 0x528AA0
+
+#define mmDMA1_QM_ARB_MST_CHOISE_PUSH_OFST_0 0x528AA4
+
+#define mmDMA1_QM_ARB_MST_CHOISE_PUSH_OFST_1 0x528AA8
+
+#define mmDMA1_QM_ARB_MST_CHOISE_PUSH_OFST_2 0x528AAC
+
+#define mmDMA1_QM_ARB_MST_CHOISE_PUSH_OFST_3 0x528AB0
+
+#define mmDMA1_QM_ARB_MST_CHOISE_PUSH_OFST_4 0x528AB4
+
+#define mmDMA1_QM_ARB_MST_CHOISE_PUSH_OFST_5 0x528AB8
+
+#define mmDMA1_QM_ARB_MST_CHOISE_PUSH_OFST_6 0x528ABC
+
+#define mmDMA1_QM_ARB_MST_CHOISE_PUSH_OFST_7 0x528AC0
+
+#define mmDMA1_QM_ARB_MST_CHOISE_PUSH_OFST_8 0x528AC4
+
+#define mmDMA1_QM_ARB_MST_CHOISE_PUSH_OFST_9 0x528AC8
+
+#define mmDMA1_QM_ARB_MST_CHOISE_PUSH_OFST_10 0x528ACC
+
+#define mmDMA1_QM_ARB_MST_CHOISE_PUSH_OFST_11 0x528AD0
+
+#define mmDMA1_QM_ARB_MST_CHOISE_PUSH_OFST_12 0x528AD4
+
+#define mmDMA1_QM_ARB_MST_CHOISE_PUSH_OFST_13 0x528AD8
+
+#define mmDMA1_QM_ARB_MST_CHOISE_PUSH_OFST_14 0x528ADC
+
+#define mmDMA1_QM_ARB_MST_CHOISE_PUSH_OFST_15 0x528AE0
+
+#define mmDMA1_QM_ARB_MST_CHOISE_PUSH_OFST_16 0x528AE4
+
+#define mmDMA1_QM_ARB_MST_CHOISE_PUSH_OFST_17 0x528AE8
+
+#define mmDMA1_QM_ARB_MST_CHOISE_PUSH_OFST_18 0x528AEC
+
+#define mmDMA1_QM_ARB_MST_CHOISE_PUSH_OFST_19 0x528AF0
+
+#define mmDMA1_QM_ARB_MST_CHOISE_PUSH_OFST_20 0x528AF4
+
+#define mmDMA1_QM_ARB_MST_CHOISE_PUSH_OFST_21 0x528AF8
+
+#define mmDMA1_QM_ARB_MST_CHOISE_PUSH_OFST_22 0x528AFC
+
+#define mmDMA1_QM_ARB_MST_CHOISE_PUSH_OFST_23 0x528B00
+
+#define mmDMA1_QM_ARB_MST_CHOISE_PUSH_OFST_24 0x528B04
+
+#define mmDMA1_QM_ARB_MST_CHOISE_PUSH_OFST_25 0x528B08
+
+#define mmDMA1_QM_ARB_MST_CHOISE_PUSH_OFST_26 0x528B0C
+
+#define mmDMA1_QM_ARB_MST_CHOISE_PUSH_OFST_27 0x528B10
+
+#define mmDMA1_QM_ARB_MST_CHOISE_PUSH_OFST_28 0x528B14
+
+#define mmDMA1_QM_ARB_MST_CHOISE_PUSH_OFST_29 0x528B18
+
+#define mmDMA1_QM_ARB_MST_CHOISE_PUSH_OFST_30 0x528B1C
+
+#define mmDMA1_QM_ARB_MST_CHOISE_PUSH_OFST_31 0x528B20
+
+#define mmDMA1_QM_ARB_SLV_MASTER_INC_CRED_OFST 0x528B28
+
+#define mmDMA1_QM_ARB_MST_SLAVE_EN 0x528B2C
+
+#define mmDMA1_QM_ARB_MST_QUIET_PER 0x528B34
+
+#define mmDMA1_QM_ARB_SLV_CHOISE_WDT 0x528B38
+
+#define mmDMA1_QM_ARB_SLV_ID 0x528B3C
+
+#define mmDMA1_QM_ARB_MSG_MAX_INFLIGHT 0x528B44
+
+#define mmDMA1_QM_ARB_MSG_AWUSER_31_11 0x528B48
+
+#define mmDMA1_QM_ARB_MSG_AWUSER_SEC_PROP 0x528B4C
+
+#define mmDMA1_QM_ARB_MSG_AWUSER_NON_SEC_PROP 0x528B50
+
+#define mmDMA1_QM_ARB_BASE_LO 0x528B54
+
+#define mmDMA1_QM_ARB_BASE_HI 0x528B58
+
+#define mmDMA1_QM_ARB_STATE_STS 0x528B80
+
+#define mmDMA1_QM_ARB_CHOISE_FULLNESS_STS 0x528B84
+
+#define mmDMA1_QM_ARB_MSG_STS 0x528B88
+
+#define mmDMA1_QM_ARB_SLV_CHOISE_Q_HEAD 0x528B8C
+
+#define mmDMA1_QM_ARB_ERR_CAUSE 0x528B9C
+
+#define mmDMA1_QM_ARB_ERR_MSG_EN 0x528BA0
+
+#define mmDMA1_QM_ARB_ERR_STS_DRP 0x528BA8
+
+#define mmDMA1_QM_ARB_MST_CRED_STS_0 0x528BB0
+
+#define mmDMA1_QM_ARB_MST_CRED_STS_1 0x528BB4
+
+#define mmDMA1_QM_ARB_MST_CRED_STS_2 0x528BB8
+
+#define mmDMA1_QM_ARB_MST_CRED_STS_3 0x528BBC
+
+#define mmDMA1_QM_ARB_MST_CRED_STS_4 0x528BC0
+
+#define mmDMA1_QM_ARB_MST_CRED_STS_5 0x528BC4
+
+#define mmDMA1_QM_ARB_MST_CRED_STS_6 0x528BC8
+
+#define mmDMA1_QM_ARB_MST_CRED_STS_7 0x528BCC
+
+#define mmDMA1_QM_ARB_MST_CRED_STS_8 0x528BD0
+
+#define mmDMA1_QM_ARB_MST_CRED_STS_9 0x528BD4
+
+#define mmDMA1_QM_ARB_MST_CRED_STS_10 0x528BD8
+
+#define mmDMA1_QM_ARB_MST_CRED_STS_11 0x528BDC
+
+#define mmDMA1_QM_ARB_MST_CRED_STS_12 0x528BE0
+
+#define mmDMA1_QM_ARB_MST_CRED_STS_13 0x528BE4
+
+#define mmDMA1_QM_ARB_MST_CRED_STS_14 0x528BE8
+
+#define mmDMA1_QM_ARB_MST_CRED_STS_15 0x528BEC
+
+#define mmDMA1_QM_ARB_MST_CRED_STS_16 0x528BF0
+
+#define mmDMA1_QM_ARB_MST_CRED_STS_17 0x528BF4
+
+#define mmDMA1_QM_ARB_MST_CRED_STS_18 0x528BF8
+
+#define mmDMA1_QM_ARB_MST_CRED_STS_19 0x528BFC
+
+#define mmDMA1_QM_ARB_MST_CRED_STS_20 0x528C00
+
+#define mmDMA1_QM_ARB_MST_CRED_STS_21 0x528C04
+
+#define mmDMA1_QM_ARB_MST_CRED_STS_22 0x528C08
+
+#define mmDMA1_QM_ARB_MST_CRED_STS_23 0x528C0C
+
+#define mmDMA1_QM_ARB_MST_CRED_STS_24 0x528C10
+
+#define mmDMA1_QM_ARB_MST_CRED_STS_25 0x528C14
+
+#define mmDMA1_QM_ARB_MST_CRED_STS_26 0x528C18
+
+#define mmDMA1_QM_ARB_MST_CRED_STS_27 0x528C1C
+
+#define mmDMA1_QM_ARB_MST_CRED_STS_28 0x528C20
+
+#define mmDMA1_QM_ARB_MST_CRED_STS_29 0x528C24
+
+#define mmDMA1_QM_ARB_MST_CRED_STS_30 0x528C28
+
+#define mmDMA1_QM_ARB_MST_CRED_STS_31 0x528C2C
+
+#define mmDMA1_QM_CGM_CFG 0x528C70
+
+#define mmDMA1_QM_CGM_STS 0x528C74
+
+#define mmDMA1_QM_CGM_CFG1 0x528C78
+
+#define mmDMA1_QM_LOCAL_RANGE_BASE 0x528C80
+
+#define mmDMA1_QM_LOCAL_RANGE_SIZE 0x528C84
+
+#define mmDMA1_QM_CSMR_STRICT_PRIO_CFG 0x528C90
+
+#define mmDMA1_QM_HBW_RD_RATE_LIM_CFG_1 0x528C94
+
+#define mmDMA1_QM_LBW_WR_RATE_LIM_CFG_0 0x528C98
+
+#define mmDMA1_QM_LBW_WR_RATE_LIM_CFG_1 0x528C9C
+
+#define mmDMA1_QM_HBW_RD_RATE_LIM_CFG_0 0x528CA0
+
+#define mmDMA1_QM_GLBL_AXCACHE 0x528CA4
+
+#define mmDMA1_QM_IND_GW_APB_CFG 0x528CB0
+
+#define mmDMA1_QM_IND_GW_APB_WDATA 0x528CB4
+
+#define mmDMA1_QM_IND_GW_APB_RDATA 0x528CB8
+
+#define mmDMA1_QM_IND_GW_APB_STATUS 0x528CBC
+
+#define mmDMA1_QM_GLBL_ERR_ADDR_LO 0x528CD0
+
+#define mmDMA1_QM_GLBL_ERR_ADDR_HI 0x528CD4
+
+#define mmDMA1_QM_GLBL_ERR_WDATA 0x528CD8
+
+#define mmDMA1_QM_GLBL_MEM_INIT_BUSY 0x528D00
+
+#endif /* ASIC_REG_DMA1_QM_REGS_H_ */
diff --git a/drivers/accel/habanalabs/include/gaudi/asic_reg/dma2_core_regs.h b/drivers/accel/habanalabs/include/gaudi/asic_reg/dma2_core_regs.h
new file mode 100644
index 0000000000..a42862cd5a
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi/asic_reg/dma2_core_regs.h
@@ -0,0 +1,156 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2016-2018 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ ** DO NOT EDIT BELOW **
+ ************************************/
+
+#ifndef ASIC_REG_DMA2_CORE_REGS_H_
+#define ASIC_REG_DMA2_CORE_REGS_H_
+
+/*
+ *****************************************
+ * DMA2_CORE (Prototype: DMA_CORE)
+ *****************************************
+ */
+
+#define mmDMA2_CORE_CFG_0 0x540000
+
+#define mmDMA2_CORE_CFG_1 0x540004
+
+#define mmDMA2_CORE_LBW_MAX_OUTSTAND 0x540008
+
+#define mmDMA2_CORE_SRC_BASE_LO 0x540014
+
+#define mmDMA2_CORE_SRC_BASE_HI 0x540018
+
+#define mmDMA2_CORE_DST_BASE_LO 0x54001C
+
+#define mmDMA2_CORE_DST_BASE_HI 0x540020
+
+#define mmDMA2_CORE_SRC_TSIZE_1 0x54002C
+
+#define mmDMA2_CORE_SRC_STRIDE_1 0x540030
+
+#define mmDMA2_CORE_SRC_TSIZE_2 0x540034
+
+#define mmDMA2_CORE_SRC_STRIDE_2 0x540038
+
+#define mmDMA2_CORE_SRC_TSIZE_3 0x54003C
+
+#define mmDMA2_CORE_SRC_STRIDE_3 0x540040
+
+#define mmDMA2_CORE_SRC_TSIZE_4 0x540044
+
+#define mmDMA2_CORE_SRC_STRIDE_4 0x540048
+
+#define mmDMA2_CORE_SRC_TSIZE_0 0x54004C
+
+#define mmDMA2_CORE_DST_TSIZE_1 0x540054
+
+#define mmDMA2_CORE_DST_STRIDE_1 0x540058
+
+#define mmDMA2_CORE_DST_TSIZE_2 0x54005C
+
+#define mmDMA2_CORE_DST_STRIDE_2 0x540060
+
+#define mmDMA2_CORE_DST_TSIZE_3 0x540064
+
+#define mmDMA2_CORE_DST_STRIDE_3 0x540068
+
+#define mmDMA2_CORE_DST_TSIZE_4 0x54006C
+
+#define mmDMA2_CORE_DST_STRIDE_4 0x540070
+
+#define mmDMA2_CORE_DST_TSIZE_0 0x540074
+
+#define mmDMA2_CORE_COMMIT 0x540078
+
+#define mmDMA2_CORE_WR_COMP_WDATA 0x54007C
+
+#define mmDMA2_CORE_WR_COMP_ADDR_LO 0x540080
+
+#define mmDMA2_CORE_WR_COMP_ADDR_HI 0x540084
+
+#define mmDMA2_CORE_WR_COMP_AWUSER_31_11 0x540088
+
+#define mmDMA2_CORE_TE_NUMROWS 0x540094
+
+#define mmDMA2_CORE_PROT 0x5400B8
+
+#define mmDMA2_CORE_SECURE_PROPS 0x5400F0
+
+#define mmDMA2_CORE_NON_SECURE_PROPS 0x5400F4
+
+#define mmDMA2_CORE_RD_MAX_OUTSTAND 0x540100
+
+#define mmDMA2_CORE_RD_MAX_SIZE 0x540104
+
+#define mmDMA2_CORE_RD_ARCACHE 0x540108
+
+#define mmDMA2_CORE_RD_ARUSER_31_11 0x540110
+
+#define mmDMA2_CORE_RD_INFLIGHTS 0x540114
+
+#define mmDMA2_CORE_WR_MAX_OUTSTAND 0x540120
+
+#define mmDMA2_CORE_WR_MAX_AWID 0x540124
+
+#define mmDMA2_CORE_WR_AWCACHE 0x540128
+
+#define mmDMA2_CORE_WR_AWUSER_31_11 0x540130
+
+#define mmDMA2_CORE_WR_INFLIGHTS 0x540134
+
+#define mmDMA2_CORE_RD_RATE_LIM_CFG_0 0x540150
+
+#define mmDMA2_CORE_RD_RATE_LIM_CFG_1 0x540154
+
+#define mmDMA2_CORE_WR_RATE_LIM_CFG_0 0x540158
+
+#define mmDMA2_CORE_WR_RATE_LIM_CFG_1 0x54015C
+
+#define mmDMA2_CORE_ERR_CFG 0x540160
+
+#define mmDMA2_CORE_ERR_CAUSE 0x540164
+
+#define mmDMA2_CORE_ERRMSG_ADDR_LO 0x540170
+
+#define mmDMA2_CORE_ERRMSG_ADDR_HI 0x540174
+
+#define mmDMA2_CORE_ERRMSG_WDATA 0x540178
+
+#define mmDMA2_CORE_STS0 0x540190
+
+#define mmDMA2_CORE_STS1 0x540194
+
+#define mmDMA2_CORE_RD_DBGMEM_ADD 0x540200
+
+#define mmDMA2_CORE_RD_DBGMEM_DATA_WR 0x540204
+
+#define mmDMA2_CORE_RD_DBGMEM_DATA_RD 0x540208
+
+#define mmDMA2_CORE_RD_DBGMEM_CTRL 0x54020C
+
+#define mmDMA2_CORE_RD_DBGMEM_RC 0x540210
+
+#define mmDMA2_CORE_DBG_HBW_AXI_AR_CNT 0x540220
+
+#define mmDMA2_CORE_DBG_HBW_AXI_AW_CNT 0x540224
+
+#define mmDMA2_CORE_DBG_LBW_AXI_AW_CNT 0x540228
+
+#define mmDMA2_CORE_DBG_DESC_CNT 0x54022C
+
+#define mmDMA2_CORE_DBG_STS 0x540230
+
+#define mmDMA2_CORE_DBG_RD_DESC_ID 0x540234
+
+#define mmDMA2_CORE_DBG_WR_DESC_ID 0x540238
+
+#endif /* ASIC_REG_DMA2_CORE_REGS_H_ */
diff --git a/drivers/accel/habanalabs/include/gaudi/asic_reg/dma2_qm_regs.h b/drivers/accel/habanalabs/include/gaudi/asic_reg/dma2_qm_regs.h
new file mode 100644
index 0000000000..8c4d4e0168
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi/asic_reg/dma2_qm_regs.h
@@ -0,0 +1,834 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2016-2018 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ ** DO NOT EDIT BELOW **
+ ************************************/
+
+#ifndef ASIC_REG_DMA2_QM_REGS_H_
+#define ASIC_REG_DMA2_QM_REGS_H_
+
+/*
+ *****************************************
+ * DMA2_QM (Prototype: QMAN)
+ *****************************************
+ */
+
+#define mmDMA2_QM_GLBL_CFG0 0x548000
+
+#define mmDMA2_QM_GLBL_CFG1 0x548004
+
+#define mmDMA2_QM_GLBL_PROT 0x548008
+
+#define mmDMA2_QM_GLBL_ERR_CFG 0x54800C
+
+#define mmDMA2_QM_GLBL_SECURE_PROPS_0 0x548010
+
+#define mmDMA2_QM_GLBL_SECURE_PROPS_1 0x548014
+
+#define mmDMA2_QM_GLBL_SECURE_PROPS_2 0x548018
+
+#define mmDMA2_QM_GLBL_SECURE_PROPS_3 0x54801C
+
+#define mmDMA2_QM_GLBL_SECURE_PROPS_4 0x548020
+
+#define mmDMA2_QM_GLBL_NON_SECURE_PROPS_0 0x548024
+
+#define mmDMA2_QM_GLBL_NON_SECURE_PROPS_1 0x548028
+
+#define mmDMA2_QM_GLBL_NON_SECURE_PROPS_2 0x54802C
+
+#define mmDMA2_QM_GLBL_NON_SECURE_PROPS_3 0x548030
+
+#define mmDMA2_QM_GLBL_NON_SECURE_PROPS_4 0x548034
+
+#define mmDMA2_QM_GLBL_STS0 0x548038
+
+#define mmDMA2_QM_GLBL_STS1_0 0x548040
+
+#define mmDMA2_QM_GLBL_STS1_1 0x548044
+
+#define mmDMA2_QM_GLBL_STS1_2 0x548048
+
+#define mmDMA2_QM_GLBL_STS1_3 0x54804C
+
+#define mmDMA2_QM_GLBL_STS1_4 0x548050
+
+#define mmDMA2_QM_GLBL_MSG_EN_0 0x548054
+
+#define mmDMA2_QM_GLBL_MSG_EN_1 0x548058
+
+#define mmDMA2_QM_GLBL_MSG_EN_2 0x54805C
+
+#define mmDMA2_QM_GLBL_MSG_EN_3 0x548060
+
+#define mmDMA2_QM_GLBL_MSG_EN_4 0x548068
+
+#define mmDMA2_QM_PQ_BASE_LO_0 0x548070
+
+#define mmDMA2_QM_PQ_BASE_LO_1 0x548074
+
+#define mmDMA2_QM_PQ_BASE_LO_2 0x548078
+
+#define mmDMA2_QM_PQ_BASE_LO_3 0x54807C
+
+#define mmDMA2_QM_PQ_BASE_HI_0 0x548080
+
+#define mmDMA2_QM_PQ_BASE_HI_1 0x548084
+
+#define mmDMA2_QM_PQ_BASE_HI_2 0x548088
+
+#define mmDMA2_QM_PQ_BASE_HI_3 0x54808C
+
+#define mmDMA2_QM_PQ_SIZE_0 0x548090
+
+#define mmDMA2_QM_PQ_SIZE_1 0x548094
+
+#define mmDMA2_QM_PQ_SIZE_2 0x548098
+
+#define mmDMA2_QM_PQ_SIZE_3 0x54809C
+
+#define mmDMA2_QM_PQ_PI_0 0x5480A0
+
+#define mmDMA2_QM_PQ_PI_1 0x5480A4
+
+#define mmDMA2_QM_PQ_PI_2 0x5480A8
+
+#define mmDMA2_QM_PQ_PI_3 0x5480AC
+
+#define mmDMA2_QM_PQ_CI_0 0x5480B0
+
+#define mmDMA2_QM_PQ_CI_1 0x5480B4
+
+#define mmDMA2_QM_PQ_CI_2 0x5480B8
+
+#define mmDMA2_QM_PQ_CI_3 0x5480BC
+
+#define mmDMA2_QM_PQ_CFG0_0 0x5480C0
+
+#define mmDMA2_QM_PQ_CFG0_1 0x5480C4
+
+#define mmDMA2_QM_PQ_CFG0_2 0x5480C8
+
+#define mmDMA2_QM_PQ_CFG0_3 0x5480CC
+
+#define mmDMA2_QM_PQ_CFG1_0 0x5480D0
+
+#define mmDMA2_QM_PQ_CFG1_1 0x5480D4
+
+#define mmDMA2_QM_PQ_CFG1_2 0x5480D8
+
+#define mmDMA2_QM_PQ_CFG1_3 0x5480DC
+
+#define mmDMA2_QM_PQ_ARUSER_31_11_0 0x5480E0
+
+#define mmDMA2_QM_PQ_ARUSER_31_11_1 0x5480E4
+
+#define mmDMA2_QM_PQ_ARUSER_31_11_2 0x5480E8
+
+#define mmDMA2_QM_PQ_ARUSER_31_11_3 0x5480EC
+
+#define mmDMA2_QM_PQ_STS0_0 0x5480F0
+
+#define mmDMA2_QM_PQ_STS0_1 0x5480F4
+
+#define mmDMA2_QM_PQ_STS0_2 0x5480F8
+
+#define mmDMA2_QM_PQ_STS0_3 0x5480FC
+
+#define mmDMA2_QM_PQ_STS1_0 0x548100
+
+#define mmDMA2_QM_PQ_STS1_1 0x548104
+
+#define mmDMA2_QM_PQ_STS1_2 0x548108
+
+#define mmDMA2_QM_PQ_STS1_3 0x54810C
+
+#define mmDMA2_QM_CQ_CFG0_0 0x548110
+
+#define mmDMA2_QM_CQ_CFG0_1 0x548114
+
+#define mmDMA2_QM_CQ_CFG0_2 0x548118
+
+#define mmDMA2_QM_CQ_CFG0_3 0x54811C
+
+#define mmDMA2_QM_CQ_CFG0_4 0x548120
+
+#define mmDMA2_QM_CQ_CFG1_0 0x548124
+
+#define mmDMA2_QM_CQ_CFG1_1 0x548128
+
+#define mmDMA2_QM_CQ_CFG1_2 0x54812C
+
+#define mmDMA2_QM_CQ_CFG1_3 0x548130
+
+#define mmDMA2_QM_CQ_CFG1_4 0x548134
+
+#define mmDMA2_QM_CQ_ARUSER_31_11_0 0x548138
+
+#define mmDMA2_QM_CQ_ARUSER_31_11_1 0x54813C
+
+#define mmDMA2_QM_CQ_ARUSER_31_11_2 0x548140
+
+#define mmDMA2_QM_CQ_ARUSER_31_11_3 0x548144
+
+#define mmDMA2_QM_CQ_ARUSER_31_11_4 0x548148
+
+#define mmDMA2_QM_CQ_STS0_0 0x54814C
+
+#define mmDMA2_QM_CQ_STS0_1 0x548150
+
+#define mmDMA2_QM_CQ_STS0_2 0x548154
+
+#define mmDMA2_QM_CQ_STS0_3 0x548158
+
+#define mmDMA2_QM_CQ_STS0_4 0x54815C
+
+#define mmDMA2_QM_CQ_STS1_0 0x548160
+
+#define mmDMA2_QM_CQ_STS1_1 0x548164
+
+#define mmDMA2_QM_CQ_STS1_2 0x548168
+
+#define mmDMA2_QM_CQ_STS1_3 0x54816C
+
+#define mmDMA2_QM_CQ_STS1_4 0x548170
+
+#define mmDMA2_QM_CQ_PTR_LO_0 0x548174
+
+#define mmDMA2_QM_CQ_PTR_HI_0 0x548178
+
+#define mmDMA2_QM_CQ_TSIZE_0 0x54817C
+
+#define mmDMA2_QM_CQ_CTL_0 0x548180
+
+#define mmDMA2_QM_CQ_PTR_LO_1 0x548184
+
+#define mmDMA2_QM_CQ_PTR_HI_1 0x548188
+
+#define mmDMA2_QM_CQ_TSIZE_1 0x54818C
+
+#define mmDMA2_QM_CQ_CTL_1 0x548190
+
+#define mmDMA2_QM_CQ_PTR_LO_2 0x548194
+
+#define mmDMA2_QM_CQ_PTR_HI_2 0x548198
+
+#define mmDMA2_QM_CQ_TSIZE_2 0x54819C
+
+#define mmDMA2_QM_CQ_CTL_2 0x5481A0
+
+#define mmDMA2_QM_CQ_PTR_LO_3 0x5481A4
+
+#define mmDMA2_QM_CQ_PTR_HI_3 0x5481A8
+
+#define mmDMA2_QM_CQ_TSIZE_3 0x5481AC
+
+#define mmDMA2_QM_CQ_CTL_3 0x5481B0
+
+#define mmDMA2_QM_CQ_PTR_LO_4 0x5481B4
+
+#define mmDMA2_QM_CQ_PTR_HI_4 0x5481B8
+
+#define mmDMA2_QM_CQ_TSIZE_4 0x5481BC
+
+#define mmDMA2_QM_CQ_CTL_4 0x5481C0
+
+#define mmDMA2_QM_CQ_PTR_LO_STS_0 0x5481C4
+
+#define mmDMA2_QM_CQ_PTR_LO_STS_1 0x5481C8
+
+#define mmDMA2_QM_CQ_PTR_LO_STS_2 0x5481CC
+
+#define mmDMA2_QM_CQ_PTR_LO_STS_3 0x5481D0
+
+#define mmDMA2_QM_CQ_PTR_LO_STS_4 0x5481D4
+
+#define mmDMA2_QM_CQ_PTR_HI_STS_0 0x5481D8
+
+#define mmDMA2_QM_CQ_PTR_HI_STS_1 0x5481DC
+
+#define mmDMA2_QM_CQ_PTR_HI_STS_2 0x5481E0
+
+#define mmDMA2_QM_CQ_PTR_HI_STS_3 0x5481E4
+
+#define mmDMA2_QM_CQ_PTR_HI_STS_4 0x5481E8
+
+#define mmDMA2_QM_CQ_TSIZE_STS_0 0x5481EC
+
+#define mmDMA2_QM_CQ_TSIZE_STS_1 0x5481F0
+
+#define mmDMA2_QM_CQ_TSIZE_STS_2 0x5481F4
+
+#define mmDMA2_QM_CQ_TSIZE_STS_3 0x5481F8
+
+#define mmDMA2_QM_CQ_TSIZE_STS_4 0x5481FC
+
+#define mmDMA2_QM_CQ_CTL_STS_0 0x548200
+
+#define mmDMA2_QM_CQ_CTL_STS_1 0x548204
+
+#define mmDMA2_QM_CQ_CTL_STS_2 0x548208
+
+#define mmDMA2_QM_CQ_CTL_STS_3 0x54820C
+
+#define mmDMA2_QM_CQ_CTL_STS_4 0x548210
+
+#define mmDMA2_QM_CQ_IFIFO_CNT_0 0x548214
+
+#define mmDMA2_QM_CQ_IFIFO_CNT_1 0x548218
+
+#define mmDMA2_QM_CQ_IFIFO_CNT_2 0x54821C
+
+#define mmDMA2_QM_CQ_IFIFO_CNT_3 0x548220
+
+#define mmDMA2_QM_CQ_IFIFO_CNT_4 0x548224
+
+#define mmDMA2_QM_CP_MSG_BASE0_ADDR_LO_0 0x548228
+
+#define mmDMA2_QM_CP_MSG_BASE0_ADDR_LO_1 0x54822C
+
+#define mmDMA2_QM_CP_MSG_BASE0_ADDR_LO_2 0x548230
+
+#define mmDMA2_QM_CP_MSG_BASE0_ADDR_LO_3 0x548234
+
+#define mmDMA2_QM_CP_MSG_BASE0_ADDR_LO_4 0x548238
+
+#define mmDMA2_QM_CP_MSG_BASE0_ADDR_HI_0 0x54823C
+
+#define mmDMA2_QM_CP_MSG_BASE0_ADDR_HI_1 0x548240
+
+#define mmDMA2_QM_CP_MSG_BASE0_ADDR_HI_2 0x548244
+
+#define mmDMA2_QM_CP_MSG_BASE0_ADDR_HI_3 0x548248
+
+#define mmDMA2_QM_CP_MSG_BASE0_ADDR_HI_4 0x54824C
+
+#define mmDMA2_QM_CP_MSG_BASE1_ADDR_LO_0 0x548250
+
+#define mmDMA2_QM_CP_MSG_BASE1_ADDR_LO_1 0x548254
+
+#define mmDMA2_QM_CP_MSG_BASE1_ADDR_LO_2 0x548258
+
+#define mmDMA2_QM_CP_MSG_BASE1_ADDR_LO_3 0x54825C
+
+#define mmDMA2_QM_CP_MSG_BASE1_ADDR_LO_4 0x548260
+
+#define mmDMA2_QM_CP_MSG_BASE1_ADDR_HI_0 0x548264
+
+#define mmDMA2_QM_CP_MSG_BASE1_ADDR_HI_1 0x548268
+
+#define mmDMA2_QM_CP_MSG_BASE1_ADDR_HI_2 0x54826C
+
+#define mmDMA2_QM_CP_MSG_BASE1_ADDR_HI_3 0x548270
+
+#define mmDMA2_QM_CP_MSG_BASE1_ADDR_HI_4 0x548274
+
+#define mmDMA2_QM_CP_MSG_BASE2_ADDR_LO_0 0x548278
+
+#define mmDMA2_QM_CP_MSG_BASE2_ADDR_LO_1 0x54827C
+
+#define mmDMA2_QM_CP_MSG_BASE2_ADDR_LO_2 0x548280
+
+#define mmDMA2_QM_CP_MSG_BASE2_ADDR_LO_3 0x548284
+
+#define mmDMA2_QM_CP_MSG_BASE2_ADDR_LO_4 0x548288
+
+#define mmDMA2_QM_CP_MSG_BASE2_ADDR_HI_0 0x54828C
+
+#define mmDMA2_QM_CP_MSG_BASE2_ADDR_HI_1 0x548290
+
+#define mmDMA2_QM_CP_MSG_BASE2_ADDR_HI_2 0x548294
+
+#define mmDMA2_QM_CP_MSG_BASE2_ADDR_HI_3 0x548298
+
+#define mmDMA2_QM_CP_MSG_BASE2_ADDR_HI_4 0x54829C
+
+#define mmDMA2_QM_CP_MSG_BASE3_ADDR_LO_0 0x5482A0
+
+#define mmDMA2_QM_CP_MSG_BASE3_ADDR_LO_1 0x5482A4
+
+#define mmDMA2_QM_CP_MSG_BASE3_ADDR_LO_2 0x5482A8
+
+#define mmDMA2_QM_CP_MSG_BASE3_ADDR_LO_3 0x5482AC
+
+#define mmDMA2_QM_CP_MSG_BASE3_ADDR_LO_4 0x5482B0
+
+#define mmDMA2_QM_CP_MSG_BASE3_ADDR_HI_0 0x5482B4
+
+#define mmDMA2_QM_CP_MSG_BASE3_ADDR_HI_1 0x5482B8
+
+#define mmDMA2_QM_CP_MSG_BASE3_ADDR_HI_2 0x5482BC
+
+#define mmDMA2_QM_CP_MSG_BASE3_ADDR_HI_3 0x5482C0
+
+#define mmDMA2_QM_CP_MSG_BASE3_ADDR_HI_4 0x5482C4
+
+#define mmDMA2_QM_CP_LDMA_TSIZE_OFFSET_0 0x5482C8
+
+#define mmDMA2_QM_CP_LDMA_TSIZE_OFFSET_1 0x5482CC
+
+#define mmDMA2_QM_CP_LDMA_TSIZE_OFFSET_2 0x5482D0
+
+#define mmDMA2_QM_CP_LDMA_TSIZE_OFFSET_3 0x5482D4
+
+#define mmDMA2_QM_CP_LDMA_TSIZE_OFFSET_4 0x5482D8
+
+#define mmDMA2_QM_CP_LDMA_SRC_BASE_LO_OFFSET_0 0x5482E0
+
+#define mmDMA2_QM_CP_LDMA_SRC_BASE_LO_OFFSET_1 0x5482E4
+
+#define mmDMA2_QM_CP_LDMA_SRC_BASE_LO_OFFSET_2 0x5482E8
+
+#define mmDMA2_QM_CP_LDMA_SRC_BASE_LO_OFFSET_3 0x5482EC
+
+#define mmDMA2_QM_CP_LDMA_SRC_BASE_LO_OFFSET_4 0x5482F0
+
+#define mmDMA2_QM_CP_LDMA_DST_BASE_LO_OFFSET_0 0x5482F4
+
+#define mmDMA2_QM_CP_LDMA_DST_BASE_LO_OFFSET_1 0x5482F8
+
+#define mmDMA2_QM_CP_LDMA_DST_BASE_LO_OFFSET_2 0x5482FC
+
+#define mmDMA2_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 0x548300
+
+#define mmDMA2_QM_CP_LDMA_DST_BASE_LO_OFFSET_4 0x548304
+
+#define mmDMA2_QM_CP_FENCE0_RDATA_0 0x548308
+
+#define mmDMA2_QM_CP_FENCE0_RDATA_1 0x54830C
+
+#define mmDMA2_QM_CP_FENCE0_RDATA_2 0x548310
+
+#define mmDMA2_QM_CP_FENCE0_RDATA_3 0x548314
+
+#define mmDMA2_QM_CP_FENCE0_RDATA_4 0x548318
+
+#define mmDMA2_QM_CP_FENCE1_RDATA_0 0x54831C
+
+#define mmDMA2_QM_CP_FENCE1_RDATA_1 0x548320
+
+#define mmDMA2_QM_CP_FENCE1_RDATA_2 0x548324
+
+#define mmDMA2_QM_CP_FENCE1_RDATA_3 0x548328
+
+#define mmDMA2_QM_CP_FENCE1_RDATA_4 0x54832C
+
+#define mmDMA2_QM_CP_FENCE2_RDATA_0 0x548330
+
+#define mmDMA2_QM_CP_FENCE2_RDATA_1 0x548334
+
+#define mmDMA2_QM_CP_FENCE2_RDATA_2 0x548338
+
+#define mmDMA2_QM_CP_FENCE2_RDATA_3 0x54833C
+
+#define mmDMA2_QM_CP_FENCE2_RDATA_4 0x548340
+
+#define mmDMA2_QM_CP_FENCE3_RDATA_0 0x548344
+
+#define mmDMA2_QM_CP_FENCE3_RDATA_1 0x548348
+
+#define mmDMA2_QM_CP_FENCE3_RDATA_2 0x54834C
+
+#define mmDMA2_QM_CP_FENCE3_RDATA_3 0x548350
+
+#define mmDMA2_QM_CP_FENCE3_RDATA_4 0x548354
+
+#define mmDMA2_QM_CP_FENCE0_CNT_0 0x548358
+
+#define mmDMA2_QM_CP_FENCE0_CNT_1 0x54835C
+
+#define mmDMA2_QM_CP_FENCE0_CNT_2 0x548360
+
+#define mmDMA2_QM_CP_FENCE0_CNT_3 0x548364
+
+#define mmDMA2_QM_CP_FENCE0_CNT_4 0x548368
+
+#define mmDMA2_QM_CP_FENCE1_CNT_0 0x54836C
+
+#define mmDMA2_QM_CP_FENCE1_CNT_1 0x548370
+
+#define mmDMA2_QM_CP_FENCE1_CNT_2 0x548374
+
+#define mmDMA2_QM_CP_FENCE1_CNT_3 0x548378
+
+#define mmDMA2_QM_CP_FENCE1_CNT_4 0x54837C
+
+#define mmDMA2_QM_CP_FENCE2_CNT_0 0x548380
+
+#define mmDMA2_QM_CP_FENCE2_CNT_1 0x548384
+
+#define mmDMA2_QM_CP_FENCE2_CNT_2 0x548388
+
+#define mmDMA2_QM_CP_FENCE2_CNT_3 0x54838C
+
+#define mmDMA2_QM_CP_FENCE2_CNT_4 0x548390
+
+#define mmDMA2_QM_CP_FENCE3_CNT_0 0x548394
+
+#define mmDMA2_QM_CP_FENCE3_CNT_1 0x548398
+
+#define mmDMA2_QM_CP_FENCE3_CNT_2 0x54839C
+
+#define mmDMA2_QM_CP_FENCE3_CNT_3 0x5483A0
+
+#define mmDMA2_QM_CP_FENCE3_CNT_4 0x5483A4
+
+#define mmDMA2_QM_CP_STS_0 0x5483A8
+
+#define mmDMA2_QM_CP_STS_1 0x5483AC
+
+#define mmDMA2_QM_CP_STS_2 0x5483B0
+
+#define mmDMA2_QM_CP_STS_3 0x5483B4
+
+#define mmDMA2_QM_CP_STS_4 0x5483B8
+
+#define mmDMA2_QM_CP_CURRENT_INST_LO_0 0x5483BC
+
+#define mmDMA2_QM_CP_CURRENT_INST_LO_1 0x5483C0
+
+#define mmDMA2_QM_CP_CURRENT_INST_LO_2 0x5483C4
+
+#define mmDMA2_QM_CP_CURRENT_INST_LO_3 0x5483C8
+
+#define mmDMA2_QM_CP_CURRENT_INST_LO_4 0x5483CC
+
+#define mmDMA2_QM_CP_CURRENT_INST_HI_0 0x5483D0
+
+#define mmDMA2_QM_CP_CURRENT_INST_HI_1 0x5483D4
+
+#define mmDMA2_QM_CP_CURRENT_INST_HI_2 0x5483D8
+
+#define mmDMA2_QM_CP_CURRENT_INST_HI_3 0x5483DC
+
+#define mmDMA2_QM_CP_CURRENT_INST_HI_4 0x5483E0
+
+#define mmDMA2_QM_CP_BARRIER_CFG_0 0x5483F4
+
+#define mmDMA2_QM_CP_BARRIER_CFG_1 0x5483F8
+
+#define mmDMA2_QM_CP_BARRIER_CFG_2 0x5483FC
+
+#define mmDMA2_QM_CP_BARRIER_CFG_3 0x548400
+
+#define mmDMA2_QM_CP_BARRIER_CFG_4 0x548404
+
+#define mmDMA2_QM_CP_DBG_0_0 0x548408
+
+#define mmDMA2_QM_CP_DBG_0_1 0x54840C
+
+#define mmDMA2_QM_CP_DBG_0_2 0x548410
+
+#define mmDMA2_QM_CP_DBG_0_3 0x548414
+
+#define mmDMA2_QM_CP_DBG_0_4 0x548418
+
+#define mmDMA2_QM_CP_ARUSER_31_11_0 0x54841C
+
+#define mmDMA2_QM_CP_ARUSER_31_11_1 0x548420
+
+#define mmDMA2_QM_CP_ARUSER_31_11_2 0x548424
+
+#define mmDMA2_QM_CP_ARUSER_31_11_3 0x548428
+
+#define mmDMA2_QM_CP_ARUSER_31_11_4 0x54842C
+
+#define mmDMA2_QM_CP_AWUSER_31_11_0 0x548430
+
+#define mmDMA2_QM_CP_AWUSER_31_11_1 0x548434
+
+#define mmDMA2_QM_CP_AWUSER_31_11_2 0x548438
+
+#define mmDMA2_QM_CP_AWUSER_31_11_3 0x54843C
+
+#define mmDMA2_QM_CP_AWUSER_31_11_4 0x548440
+
+#define mmDMA2_QM_ARB_CFG_0 0x548A00
+
+#define mmDMA2_QM_ARB_CHOISE_Q_PUSH 0x548A04
+
+#define mmDMA2_QM_ARB_WRR_WEIGHT_0 0x548A08
+
+#define mmDMA2_QM_ARB_WRR_WEIGHT_1 0x548A0C
+
+#define mmDMA2_QM_ARB_WRR_WEIGHT_2 0x548A10
+
+#define mmDMA2_QM_ARB_WRR_WEIGHT_3 0x548A14
+
+#define mmDMA2_QM_ARB_CFG_1 0x548A18
+
+#define mmDMA2_QM_ARB_MST_AVAIL_CRED_0 0x548A20
+
+#define mmDMA2_QM_ARB_MST_AVAIL_CRED_1 0x548A24
+
+#define mmDMA2_QM_ARB_MST_AVAIL_CRED_2 0x548A28
+
+#define mmDMA2_QM_ARB_MST_AVAIL_CRED_3 0x548A2C
+
+#define mmDMA2_QM_ARB_MST_AVAIL_CRED_4 0x548A30
+
+#define mmDMA2_QM_ARB_MST_AVAIL_CRED_5 0x548A34
+
+#define mmDMA2_QM_ARB_MST_AVAIL_CRED_6 0x548A38
+
+#define mmDMA2_QM_ARB_MST_AVAIL_CRED_7 0x548A3C
+
+#define mmDMA2_QM_ARB_MST_AVAIL_CRED_8 0x548A40
+
+#define mmDMA2_QM_ARB_MST_AVAIL_CRED_9 0x548A44
+
+#define mmDMA2_QM_ARB_MST_AVAIL_CRED_10 0x548A48
+
+#define mmDMA2_QM_ARB_MST_AVAIL_CRED_11 0x548A4C
+
+#define mmDMA2_QM_ARB_MST_AVAIL_CRED_12 0x548A50
+
+#define mmDMA2_QM_ARB_MST_AVAIL_CRED_13 0x548A54
+
+#define mmDMA2_QM_ARB_MST_AVAIL_CRED_14 0x548A58
+
+#define mmDMA2_QM_ARB_MST_AVAIL_CRED_15 0x548A5C
+
+#define mmDMA2_QM_ARB_MST_AVAIL_CRED_16 0x548A60
+
+#define mmDMA2_QM_ARB_MST_AVAIL_CRED_17 0x548A64
+
+#define mmDMA2_QM_ARB_MST_AVAIL_CRED_18 0x548A68
+
+#define mmDMA2_QM_ARB_MST_AVAIL_CRED_19 0x548A6C
+
+#define mmDMA2_QM_ARB_MST_AVAIL_CRED_20 0x548A70
+
+#define mmDMA2_QM_ARB_MST_AVAIL_CRED_21 0x548A74
+
+#define mmDMA2_QM_ARB_MST_AVAIL_CRED_22 0x548A78
+
+#define mmDMA2_QM_ARB_MST_AVAIL_CRED_23 0x548A7C
+
+#define mmDMA2_QM_ARB_MST_AVAIL_CRED_24 0x548A80
+
+#define mmDMA2_QM_ARB_MST_AVAIL_CRED_25 0x548A84
+
+#define mmDMA2_QM_ARB_MST_AVAIL_CRED_26 0x548A88
+
+#define mmDMA2_QM_ARB_MST_AVAIL_CRED_27 0x548A8C
+
+#define mmDMA2_QM_ARB_MST_AVAIL_CRED_28 0x548A90
+
+#define mmDMA2_QM_ARB_MST_AVAIL_CRED_29 0x548A94
+
+#define mmDMA2_QM_ARB_MST_AVAIL_CRED_30 0x548A98
+
+#define mmDMA2_QM_ARB_MST_AVAIL_CRED_31 0x548A9C
+
+#define mmDMA2_QM_ARB_MST_CRED_INC 0x548AA0
+
+#define mmDMA2_QM_ARB_MST_CHOISE_PUSH_OFST_0 0x548AA4
+
+#define mmDMA2_QM_ARB_MST_CHOISE_PUSH_OFST_1 0x548AA8
+
+#define mmDMA2_QM_ARB_MST_CHOISE_PUSH_OFST_2 0x548AAC
+
+#define mmDMA2_QM_ARB_MST_CHOISE_PUSH_OFST_3 0x548AB0
+
+#define mmDMA2_QM_ARB_MST_CHOISE_PUSH_OFST_4 0x548AB4
+
+#define mmDMA2_QM_ARB_MST_CHOISE_PUSH_OFST_5 0x548AB8
+
+#define mmDMA2_QM_ARB_MST_CHOISE_PUSH_OFST_6 0x548ABC
+
+#define mmDMA2_QM_ARB_MST_CHOISE_PUSH_OFST_7 0x548AC0
+
+#define mmDMA2_QM_ARB_MST_CHOISE_PUSH_OFST_8 0x548AC4
+
+#define mmDMA2_QM_ARB_MST_CHOISE_PUSH_OFST_9 0x548AC8
+
+#define mmDMA2_QM_ARB_MST_CHOISE_PUSH_OFST_10 0x548ACC
+
+#define mmDMA2_QM_ARB_MST_CHOISE_PUSH_OFST_11 0x548AD0
+
+#define mmDMA2_QM_ARB_MST_CHOISE_PUSH_OFST_12 0x548AD4
+
+#define mmDMA2_QM_ARB_MST_CHOISE_PUSH_OFST_13 0x548AD8
+
+#define mmDMA2_QM_ARB_MST_CHOISE_PUSH_OFST_14 0x548ADC
+
+#define mmDMA2_QM_ARB_MST_CHOISE_PUSH_OFST_15 0x548AE0
+
+#define mmDMA2_QM_ARB_MST_CHOISE_PUSH_OFST_16 0x548AE4
+
+#define mmDMA2_QM_ARB_MST_CHOISE_PUSH_OFST_17 0x548AE8
+
+#define mmDMA2_QM_ARB_MST_CHOISE_PUSH_OFST_18 0x548AEC
+
+#define mmDMA2_QM_ARB_MST_CHOISE_PUSH_OFST_19 0x548AF0
+
+#define mmDMA2_QM_ARB_MST_CHOISE_PUSH_OFST_20 0x548AF4
+
+#define mmDMA2_QM_ARB_MST_CHOISE_PUSH_OFST_21 0x548AF8
+
+#define mmDMA2_QM_ARB_MST_CHOISE_PUSH_OFST_22 0x548AFC
+
+#define mmDMA2_QM_ARB_MST_CHOISE_PUSH_OFST_23 0x548B00
+
+#define mmDMA2_QM_ARB_MST_CHOISE_PUSH_OFST_24 0x548B04
+
+#define mmDMA2_QM_ARB_MST_CHOISE_PUSH_OFST_25 0x548B08
+
+#define mmDMA2_QM_ARB_MST_CHOISE_PUSH_OFST_26 0x548B0C
+
+#define mmDMA2_QM_ARB_MST_CHOISE_PUSH_OFST_27 0x548B10
+
+#define mmDMA2_QM_ARB_MST_CHOISE_PUSH_OFST_28 0x548B14
+
+#define mmDMA2_QM_ARB_MST_CHOISE_PUSH_OFST_29 0x548B18
+
+#define mmDMA2_QM_ARB_MST_CHOISE_PUSH_OFST_30 0x548B1C
+
+#define mmDMA2_QM_ARB_MST_CHOISE_PUSH_OFST_31 0x548B20
+
+#define mmDMA2_QM_ARB_SLV_MASTER_INC_CRED_OFST 0x548B28
+
+#define mmDMA2_QM_ARB_MST_SLAVE_EN 0x548B2C
+
+#define mmDMA2_QM_ARB_MST_QUIET_PER 0x548B34
+
+#define mmDMA2_QM_ARB_SLV_CHOISE_WDT 0x548B38
+
+#define mmDMA2_QM_ARB_SLV_ID 0x548B3C
+
+#define mmDMA2_QM_ARB_MSG_MAX_INFLIGHT 0x548B44
+
+#define mmDMA2_QM_ARB_MSG_AWUSER_31_11 0x548B48
+
+#define mmDMA2_QM_ARB_MSG_AWUSER_SEC_PROP 0x548B4C
+
+#define mmDMA2_QM_ARB_MSG_AWUSER_NON_SEC_PROP 0x548B50
+
+#define mmDMA2_QM_ARB_BASE_LO 0x548B54
+
+#define mmDMA2_QM_ARB_BASE_HI 0x548B58
+
+#define mmDMA2_QM_ARB_STATE_STS 0x548B80
+
+#define mmDMA2_QM_ARB_CHOISE_FULLNESS_STS 0x548B84
+
+#define mmDMA2_QM_ARB_MSG_STS 0x548B88
+
+#define mmDMA2_QM_ARB_SLV_CHOISE_Q_HEAD 0x548B8C
+
+#define mmDMA2_QM_ARB_ERR_CAUSE 0x548B9C
+
+#define mmDMA2_QM_ARB_ERR_MSG_EN 0x548BA0
+
+#define mmDMA2_QM_ARB_ERR_STS_DRP 0x548BA8
+
+#define mmDMA2_QM_ARB_MST_CRED_STS_0 0x548BB0
+
+#define mmDMA2_QM_ARB_MST_CRED_STS_1 0x548BB4
+
+#define mmDMA2_QM_ARB_MST_CRED_STS_2 0x548BB8
+
+#define mmDMA2_QM_ARB_MST_CRED_STS_3 0x548BBC
+
+#define mmDMA2_QM_ARB_MST_CRED_STS_4 0x548BC0
+
+#define mmDMA2_QM_ARB_MST_CRED_STS_5 0x548BC4
+
+#define mmDMA2_QM_ARB_MST_CRED_STS_6 0x548BC8
+
+#define mmDMA2_QM_ARB_MST_CRED_STS_7 0x548BCC
+
+#define mmDMA2_QM_ARB_MST_CRED_STS_8 0x548BD0
+
+#define mmDMA2_QM_ARB_MST_CRED_STS_9 0x548BD4
+
+#define mmDMA2_QM_ARB_MST_CRED_STS_10 0x548BD8
+
+#define mmDMA2_QM_ARB_MST_CRED_STS_11 0x548BDC
+
+#define mmDMA2_QM_ARB_MST_CRED_STS_12 0x548BE0
+
+#define mmDMA2_QM_ARB_MST_CRED_STS_13 0x548BE4
+
+#define mmDMA2_QM_ARB_MST_CRED_STS_14 0x548BE8
+
+#define mmDMA2_QM_ARB_MST_CRED_STS_15 0x548BEC
+
+#define mmDMA2_QM_ARB_MST_CRED_STS_16 0x548BF0
+
+#define mmDMA2_QM_ARB_MST_CRED_STS_17 0x548BF4
+
+#define mmDMA2_QM_ARB_MST_CRED_STS_18 0x548BF8
+
+#define mmDMA2_QM_ARB_MST_CRED_STS_19 0x548BFC
+
+#define mmDMA2_QM_ARB_MST_CRED_STS_20 0x548C00
+
+#define mmDMA2_QM_ARB_MST_CRED_STS_21 0x548C04
+
+#define mmDMA2_QM_ARB_MST_CRED_STS_22 0x548C08
+
+#define mmDMA2_QM_ARB_MST_CRED_STS_23 0x548C0C
+
+#define mmDMA2_QM_ARB_MST_CRED_STS_24 0x548C10
+
+#define mmDMA2_QM_ARB_MST_CRED_STS_25 0x548C14
+
+#define mmDMA2_QM_ARB_MST_CRED_STS_26 0x548C18
+
+#define mmDMA2_QM_ARB_MST_CRED_STS_27 0x548C1C
+
+#define mmDMA2_QM_ARB_MST_CRED_STS_28 0x548C20
+
+#define mmDMA2_QM_ARB_MST_CRED_STS_29 0x548C24
+
+#define mmDMA2_QM_ARB_MST_CRED_STS_30 0x548C28
+
+#define mmDMA2_QM_ARB_MST_CRED_STS_31 0x548C2C
+
+#define mmDMA2_QM_CGM_CFG 0x548C70
+
+#define mmDMA2_QM_CGM_STS 0x548C74
+
+#define mmDMA2_QM_CGM_CFG1 0x548C78
+
+#define mmDMA2_QM_LOCAL_RANGE_BASE 0x548C80
+
+#define mmDMA2_QM_LOCAL_RANGE_SIZE 0x548C84
+
+#define mmDMA2_QM_CSMR_STRICT_PRIO_CFG 0x548C90
+
+#define mmDMA2_QM_HBW_RD_RATE_LIM_CFG_1 0x548C94
+
+#define mmDMA2_QM_LBW_WR_RATE_LIM_CFG_0 0x548C98
+
+#define mmDMA2_QM_LBW_WR_RATE_LIM_CFG_1 0x548C9C
+
+#define mmDMA2_QM_HBW_RD_RATE_LIM_CFG_0 0x548CA0
+
+#define mmDMA2_QM_GLBL_AXCACHE 0x548CA4
+
+#define mmDMA2_QM_IND_GW_APB_CFG 0x548CB0
+
+#define mmDMA2_QM_IND_GW_APB_WDATA 0x548CB4
+
+#define mmDMA2_QM_IND_GW_APB_RDATA 0x548CB8
+
+#define mmDMA2_QM_IND_GW_APB_STATUS 0x548CBC
+
+#define mmDMA2_QM_GLBL_ERR_ADDR_LO 0x548CD0
+
+#define mmDMA2_QM_GLBL_ERR_ADDR_HI 0x548CD4
+
+#define mmDMA2_QM_GLBL_ERR_WDATA 0x548CD8
+
+#define mmDMA2_QM_GLBL_MEM_INIT_BUSY 0x548D00
+
+#endif /* ASIC_REG_DMA2_QM_REGS_H_ */
diff --git a/drivers/accel/habanalabs/include/gaudi/asic_reg/dma3_core_regs.h b/drivers/accel/habanalabs/include/gaudi/asic_reg/dma3_core_regs.h
new file mode 100644
index 0000000000..fb145f416f
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi/asic_reg/dma3_core_regs.h
@@ -0,0 +1,156 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2016-2018 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ ** DO NOT EDIT BELOW **
+ ************************************/
+
+#ifndef ASIC_REG_DMA3_CORE_REGS_H_
+#define ASIC_REG_DMA3_CORE_REGS_H_
+
+/*
+ *****************************************
+ * DMA3_CORE (Prototype: DMA_CORE)
+ *****************************************
+ */
+
+#define mmDMA3_CORE_CFG_0 0x560000
+
+#define mmDMA3_CORE_CFG_1 0x560004
+
+#define mmDMA3_CORE_LBW_MAX_OUTSTAND 0x560008
+
+#define mmDMA3_CORE_SRC_BASE_LO 0x560014
+
+#define mmDMA3_CORE_SRC_BASE_HI 0x560018
+
+#define mmDMA3_CORE_DST_BASE_LO 0x56001C
+
+#define mmDMA3_CORE_DST_BASE_HI 0x560020
+
+#define mmDMA3_CORE_SRC_TSIZE_1 0x56002C
+
+#define mmDMA3_CORE_SRC_STRIDE_1 0x560030
+
+#define mmDMA3_CORE_SRC_TSIZE_2 0x560034
+
+#define mmDMA3_CORE_SRC_STRIDE_2 0x560038
+
+#define mmDMA3_CORE_SRC_TSIZE_3 0x56003C
+
+#define mmDMA3_CORE_SRC_STRIDE_3 0x560040
+
+#define mmDMA3_CORE_SRC_TSIZE_4 0x560044
+
+#define mmDMA3_CORE_SRC_STRIDE_4 0x560048
+
+#define mmDMA3_CORE_SRC_TSIZE_0 0x56004C
+
+#define mmDMA3_CORE_DST_TSIZE_1 0x560054
+
+#define mmDMA3_CORE_DST_STRIDE_1 0x560058
+
+#define mmDMA3_CORE_DST_TSIZE_2 0x56005C
+
+#define mmDMA3_CORE_DST_STRIDE_2 0x560060
+
+#define mmDMA3_CORE_DST_TSIZE_3 0x560064
+
+#define mmDMA3_CORE_DST_STRIDE_3 0x560068
+
+#define mmDMA3_CORE_DST_TSIZE_4 0x56006C
+
+#define mmDMA3_CORE_DST_STRIDE_4 0x560070
+
+#define mmDMA3_CORE_DST_TSIZE_0 0x560074
+
+#define mmDMA3_CORE_COMMIT 0x560078
+
+#define mmDMA3_CORE_WR_COMP_WDATA 0x56007C
+
+#define mmDMA3_CORE_WR_COMP_ADDR_LO 0x560080
+
+#define mmDMA3_CORE_WR_COMP_ADDR_HI 0x560084
+
+#define mmDMA3_CORE_WR_COMP_AWUSER_31_11 0x560088
+
+#define mmDMA3_CORE_TE_NUMROWS 0x560094
+
+#define mmDMA3_CORE_PROT 0x5600B8
+
+#define mmDMA3_CORE_SECURE_PROPS 0x5600F0
+
+#define mmDMA3_CORE_NON_SECURE_PROPS 0x5600F4
+
+#define mmDMA3_CORE_RD_MAX_OUTSTAND 0x560100
+
+#define mmDMA3_CORE_RD_MAX_SIZE 0x560104
+
+#define mmDMA3_CORE_RD_ARCACHE 0x560108
+
+#define mmDMA3_CORE_RD_ARUSER_31_11 0x560110
+
+#define mmDMA3_CORE_RD_INFLIGHTS 0x560114
+
+#define mmDMA3_CORE_WR_MAX_OUTSTAND 0x560120
+
+#define mmDMA3_CORE_WR_MAX_AWID 0x560124
+
+#define mmDMA3_CORE_WR_AWCACHE 0x560128
+
+#define mmDMA3_CORE_WR_AWUSER_31_11 0x560130
+
+#define mmDMA3_CORE_WR_INFLIGHTS 0x560134
+
+#define mmDMA3_CORE_RD_RATE_LIM_CFG_0 0x560150
+
+#define mmDMA3_CORE_RD_RATE_LIM_CFG_1 0x560154
+
+#define mmDMA3_CORE_WR_RATE_LIM_CFG_0 0x560158
+
+#define mmDMA3_CORE_WR_RATE_LIM_CFG_1 0x56015C
+
+#define mmDMA3_CORE_ERR_CFG 0x560160
+
+#define mmDMA3_CORE_ERR_CAUSE 0x560164
+
+#define mmDMA3_CORE_ERRMSG_ADDR_LO 0x560170
+
+#define mmDMA3_CORE_ERRMSG_ADDR_HI 0x560174
+
+#define mmDMA3_CORE_ERRMSG_WDATA 0x560178
+
+#define mmDMA3_CORE_STS0 0x560190
+
+#define mmDMA3_CORE_STS1 0x560194
+
+#define mmDMA3_CORE_RD_DBGMEM_ADD 0x560200
+
+#define mmDMA3_CORE_RD_DBGMEM_DATA_WR 0x560204
+
+#define mmDMA3_CORE_RD_DBGMEM_DATA_RD 0x560208
+
+#define mmDMA3_CORE_RD_DBGMEM_CTRL 0x56020C
+
+#define mmDMA3_CORE_RD_DBGMEM_RC 0x560210
+
+#define mmDMA3_CORE_DBG_HBW_AXI_AR_CNT 0x560220
+
+#define mmDMA3_CORE_DBG_HBW_AXI_AW_CNT 0x560224
+
+#define mmDMA3_CORE_DBG_LBW_AXI_AW_CNT 0x560228
+
+#define mmDMA3_CORE_DBG_DESC_CNT 0x56022C
+
+#define mmDMA3_CORE_DBG_STS 0x560230
+
+#define mmDMA3_CORE_DBG_RD_DESC_ID 0x560234
+
+#define mmDMA3_CORE_DBG_WR_DESC_ID 0x560238
+
+#endif /* ASIC_REG_DMA3_CORE_REGS_H_ */
diff --git a/drivers/accel/habanalabs/include/gaudi/asic_reg/dma3_qm_regs.h b/drivers/accel/habanalabs/include/gaudi/asic_reg/dma3_qm_regs.h
new file mode 100644
index 0000000000..a4b461ca3d
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi/asic_reg/dma3_qm_regs.h
@@ -0,0 +1,834 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2016-2018 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ ** DO NOT EDIT BELOW **
+ ************************************/
+
+#ifndef ASIC_REG_DMA3_QM_REGS_H_
+#define ASIC_REG_DMA3_QM_REGS_H_
+
+/*
+ *****************************************
+ * DMA3_QM (Prototype: QMAN)
+ *****************************************
+ */
+
+#define mmDMA3_QM_GLBL_CFG0 0x568000
+
+#define mmDMA3_QM_GLBL_CFG1 0x568004
+
+#define mmDMA3_QM_GLBL_PROT 0x568008
+
+#define mmDMA3_QM_GLBL_ERR_CFG 0x56800C
+
+#define mmDMA3_QM_GLBL_SECURE_PROPS_0 0x568010
+
+#define mmDMA3_QM_GLBL_SECURE_PROPS_1 0x568014
+
+#define mmDMA3_QM_GLBL_SECURE_PROPS_2 0x568018
+
+#define mmDMA3_QM_GLBL_SECURE_PROPS_3 0x56801C
+
+#define mmDMA3_QM_GLBL_SECURE_PROPS_4 0x568020
+
+#define mmDMA3_QM_GLBL_NON_SECURE_PROPS_0 0x568024
+
+#define mmDMA3_QM_GLBL_NON_SECURE_PROPS_1 0x568028
+
+#define mmDMA3_QM_GLBL_NON_SECURE_PROPS_2 0x56802C
+
+#define mmDMA3_QM_GLBL_NON_SECURE_PROPS_3 0x568030
+
+#define mmDMA3_QM_GLBL_NON_SECURE_PROPS_4 0x568034
+
+#define mmDMA3_QM_GLBL_STS0 0x568038
+
+#define mmDMA3_QM_GLBL_STS1_0 0x568040
+
+#define mmDMA3_QM_GLBL_STS1_1 0x568044
+
+#define mmDMA3_QM_GLBL_STS1_2 0x568048
+
+#define mmDMA3_QM_GLBL_STS1_3 0x56804C
+
+#define mmDMA3_QM_GLBL_STS1_4 0x568050
+
+#define mmDMA3_QM_GLBL_MSG_EN_0 0x568054
+
+#define mmDMA3_QM_GLBL_MSG_EN_1 0x568058
+
+#define mmDMA3_QM_GLBL_MSG_EN_2 0x56805C
+
+#define mmDMA3_QM_GLBL_MSG_EN_3 0x568060
+
+#define mmDMA3_QM_GLBL_MSG_EN_4 0x568068
+
+#define mmDMA3_QM_PQ_BASE_LO_0 0x568070
+
+#define mmDMA3_QM_PQ_BASE_LO_1 0x568074
+
+#define mmDMA3_QM_PQ_BASE_LO_2 0x568078
+
+#define mmDMA3_QM_PQ_BASE_LO_3 0x56807C
+
+#define mmDMA3_QM_PQ_BASE_HI_0 0x568080
+
+#define mmDMA3_QM_PQ_BASE_HI_1 0x568084
+
+#define mmDMA3_QM_PQ_BASE_HI_2 0x568088
+
+#define mmDMA3_QM_PQ_BASE_HI_3 0x56808C
+
+#define mmDMA3_QM_PQ_SIZE_0 0x568090
+
+#define mmDMA3_QM_PQ_SIZE_1 0x568094
+
+#define mmDMA3_QM_PQ_SIZE_2 0x568098
+
+#define mmDMA3_QM_PQ_SIZE_3 0x56809C
+
+#define mmDMA3_QM_PQ_PI_0 0x5680A0
+
+#define mmDMA3_QM_PQ_PI_1 0x5680A4
+
+#define mmDMA3_QM_PQ_PI_2 0x5680A8
+
+#define mmDMA3_QM_PQ_PI_3 0x5680AC
+
+#define mmDMA3_QM_PQ_CI_0 0x5680B0
+
+#define mmDMA3_QM_PQ_CI_1 0x5680B4
+
+#define mmDMA3_QM_PQ_CI_2 0x5680B8
+
+#define mmDMA3_QM_PQ_CI_3 0x5680BC
+
+#define mmDMA3_QM_PQ_CFG0_0 0x5680C0
+
+#define mmDMA3_QM_PQ_CFG0_1 0x5680C4
+
+#define mmDMA3_QM_PQ_CFG0_2 0x5680C8
+
+#define mmDMA3_QM_PQ_CFG0_3 0x5680CC
+
+#define mmDMA3_QM_PQ_CFG1_0 0x5680D0
+
+#define mmDMA3_QM_PQ_CFG1_1 0x5680D4
+
+#define mmDMA3_QM_PQ_CFG1_2 0x5680D8
+
+#define mmDMA3_QM_PQ_CFG1_3 0x5680DC
+
+#define mmDMA3_QM_PQ_ARUSER_31_11_0 0x5680E0
+
+#define mmDMA3_QM_PQ_ARUSER_31_11_1 0x5680E4
+
+#define mmDMA3_QM_PQ_ARUSER_31_11_2 0x5680E8
+
+#define mmDMA3_QM_PQ_ARUSER_31_11_3 0x5680EC
+
+#define mmDMA3_QM_PQ_STS0_0 0x5680F0
+
+#define mmDMA3_QM_PQ_STS0_1 0x5680F4
+
+#define mmDMA3_QM_PQ_STS0_2 0x5680F8
+
+#define mmDMA3_QM_PQ_STS0_3 0x5680FC
+
+#define mmDMA3_QM_PQ_STS1_0 0x568100
+
+#define mmDMA3_QM_PQ_STS1_1 0x568104
+
+#define mmDMA3_QM_PQ_STS1_2 0x568108
+
+#define mmDMA3_QM_PQ_STS1_3 0x56810C
+
+#define mmDMA3_QM_CQ_CFG0_0 0x568110
+
+#define mmDMA3_QM_CQ_CFG0_1 0x568114
+
+#define mmDMA3_QM_CQ_CFG0_2 0x568118
+
+#define mmDMA3_QM_CQ_CFG0_3 0x56811C
+
+#define mmDMA3_QM_CQ_CFG0_4 0x568120
+
+#define mmDMA3_QM_CQ_CFG1_0 0x568124
+
+#define mmDMA3_QM_CQ_CFG1_1 0x568128
+
+#define mmDMA3_QM_CQ_CFG1_2 0x56812C
+
+#define mmDMA3_QM_CQ_CFG1_3 0x568130
+
+#define mmDMA3_QM_CQ_CFG1_4 0x568134
+
+#define mmDMA3_QM_CQ_ARUSER_31_11_0 0x568138
+
+#define mmDMA3_QM_CQ_ARUSER_31_11_1 0x56813C
+
+#define mmDMA3_QM_CQ_ARUSER_31_11_2 0x568140
+
+#define mmDMA3_QM_CQ_ARUSER_31_11_3 0x568144
+
+#define mmDMA3_QM_CQ_ARUSER_31_11_4 0x568148
+
+#define mmDMA3_QM_CQ_STS0_0 0x56814C
+
+#define mmDMA3_QM_CQ_STS0_1 0x568150
+
+#define mmDMA3_QM_CQ_STS0_2 0x568154
+
+#define mmDMA3_QM_CQ_STS0_3 0x568158
+
+#define mmDMA3_QM_CQ_STS0_4 0x56815C
+
+#define mmDMA3_QM_CQ_STS1_0 0x568160
+
+#define mmDMA3_QM_CQ_STS1_1 0x568164
+
+#define mmDMA3_QM_CQ_STS1_2 0x568168
+
+#define mmDMA3_QM_CQ_STS1_3 0x56816C
+
+#define mmDMA3_QM_CQ_STS1_4 0x568170
+
+#define mmDMA3_QM_CQ_PTR_LO_0 0x568174
+
+#define mmDMA3_QM_CQ_PTR_HI_0 0x568178
+
+#define mmDMA3_QM_CQ_TSIZE_0 0x56817C
+
+#define mmDMA3_QM_CQ_CTL_0 0x568180
+
+#define mmDMA3_QM_CQ_PTR_LO_1 0x568184
+
+#define mmDMA3_QM_CQ_PTR_HI_1 0x568188
+
+#define mmDMA3_QM_CQ_TSIZE_1 0x56818C
+
+#define mmDMA3_QM_CQ_CTL_1 0x568190
+
+#define mmDMA3_QM_CQ_PTR_LO_2 0x568194
+
+#define mmDMA3_QM_CQ_PTR_HI_2 0x568198
+
+#define mmDMA3_QM_CQ_TSIZE_2 0x56819C
+
+#define mmDMA3_QM_CQ_CTL_2 0x5681A0
+
+#define mmDMA3_QM_CQ_PTR_LO_3 0x5681A4
+
+#define mmDMA3_QM_CQ_PTR_HI_3 0x5681A8
+
+#define mmDMA3_QM_CQ_TSIZE_3 0x5681AC
+
+#define mmDMA3_QM_CQ_CTL_3 0x5681B0
+
+#define mmDMA3_QM_CQ_PTR_LO_4 0x5681B4
+
+#define mmDMA3_QM_CQ_PTR_HI_4 0x5681B8
+
+#define mmDMA3_QM_CQ_TSIZE_4 0x5681BC
+
+#define mmDMA3_QM_CQ_CTL_4 0x5681C0
+
+#define mmDMA3_QM_CQ_PTR_LO_STS_0 0x5681C4
+
+#define mmDMA3_QM_CQ_PTR_LO_STS_1 0x5681C8
+
+#define mmDMA3_QM_CQ_PTR_LO_STS_2 0x5681CC
+
+#define mmDMA3_QM_CQ_PTR_LO_STS_3 0x5681D0
+
+#define mmDMA3_QM_CQ_PTR_LO_STS_4 0x5681D4
+
+#define mmDMA3_QM_CQ_PTR_HI_STS_0 0x5681D8
+
+#define mmDMA3_QM_CQ_PTR_HI_STS_1 0x5681DC
+
+#define mmDMA3_QM_CQ_PTR_HI_STS_2 0x5681E0
+
+#define mmDMA3_QM_CQ_PTR_HI_STS_3 0x5681E4
+
+#define mmDMA3_QM_CQ_PTR_HI_STS_4 0x5681E8
+
+#define mmDMA3_QM_CQ_TSIZE_STS_0 0x5681EC
+
+#define mmDMA3_QM_CQ_TSIZE_STS_1 0x5681F0
+
+#define mmDMA3_QM_CQ_TSIZE_STS_2 0x5681F4
+
+#define mmDMA3_QM_CQ_TSIZE_STS_3 0x5681F8
+
+#define mmDMA3_QM_CQ_TSIZE_STS_4 0x5681FC
+
+#define mmDMA3_QM_CQ_CTL_STS_0 0x568200
+
+#define mmDMA3_QM_CQ_CTL_STS_1 0x568204
+
+#define mmDMA3_QM_CQ_CTL_STS_2 0x568208
+
+#define mmDMA3_QM_CQ_CTL_STS_3 0x56820C
+
+#define mmDMA3_QM_CQ_CTL_STS_4 0x568210
+
+#define mmDMA3_QM_CQ_IFIFO_CNT_0 0x568214
+
+#define mmDMA3_QM_CQ_IFIFO_CNT_1 0x568218
+
+#define mmDMA3_QM_CQ_IFIFO_CNT_2 0x56821C
+
+#define mmDMA3_QM_CQ_IFIFO_CNT_3 0x568220
+
+#define mmDMA3_QM_CQ_IFIFO_CNT_4 0x568224
+
+#define mmDMA3_QM_CP_MSG_BASE0_ADDR_LO_0 0x568228
+
+#define mmDMA3_QM_CP_MSG_BASE0_ADDR_LO_1 0x56822C
+
+#define mmDMA3_QM_CP_MSG_BASE0_ADDR_LO_2 0x568230
+
+#define mmDMA3_QM_CP_MSG_BASE0_ADDR_LO_3 0x568234
+
+#define mmDMA3_QM_CP_MSG_BASE0_ADDR_LO_4 0x568238
+
+#define mmDMA3_QM_CP_MSG_BASE0_ADDR_HI_0 0x56823C
+
+#define mmDMA3_QM_CP_MSG_BASE0_ADDR_HI_1 0x568240
+
+#define mmDMA3_QM_CP_MSG_BASE0_ADDR_HI_2 0x568244
+
+#define mmDMA3_QM_CP_MSG_BASE0_ADDR_HI_3 0x568248
+
+#define mmDMA3_QM_CP_MSG_BASE0_ADDR_HI_4 0x56824C
+
+#define mmDMA3_QM_CP_MSG_BASE1_ADDR_LO_0 0x568250
+
+#define mmDMA3_QM_CP_MSG_BASE1_ADDR_LO_1 0x568254
+
+#define mmDMA3_QM_CP_MSG_BASE1_ADDR_LO_2 0x568258
+
+#define mmDMA3_QM_CP_MSG_BASE1_ADDR_LO_3 0x56825C
+
+#define mmDMA3_QM_CP_MSG_BASE1_ADDR_LO_4 0x568260
+
+#define mmDMA3_QM_CP_MSG_BASE1_ADDR_HI_0 0x568264
+
+#define mmDMA3_QM_CP_MSG_BASE1_ADDR_HI_1 0x568268
+
+#define mmDMA3_QM_CP_MSG_BASE1_ADDR_HI_2 0x56826C
+
+#define mmDMA3_QM_CP_MSG_BASE1_ADDR_HI_3 0x568270
+
+#define mmDMA3_QM_CP_MSG_BASE1_ADDR_HI_4 0x568274
+
+#define mmDMA3_QM_CP_MSG_BASE2_ADDR_LO_0 0x568278
+
+#define mmDMA3_QM_CP_MSG_BASE2_ADDR_LO_1 0x56827C
+
+#define mmDMA3_QM_CP_MSG_BASE2_ADDR_LO_2 0x568280
+
+#define mmDMA3_QM_CP_MSG_BASE2_ADDR_LO_3 0x568284
+
+#define mmDMA3_QM_CP_MSG_BASE2_ADDR_LO_4 0x568288
+
+#define mmDMA3_QM_CP_MSG_BASE2_ADDR_HI_0 0x56828C
+
+#define mmDMA3_QM_CP_MSG_BASE2_ADDR_HI_1 0x568290
+
+#define mmDMA3_QM_CP_MSG_BASE2_ADDR_HI_2 0x568294
+
+#define mmDMA3_QM_CP_MSG_BASE2_ADDR_HI_3 0x568298
+
+#define mmDMA3_QM_CP_MSG_BASE2_ADDR_HI_4 0x56829C
+
+#define mmDMA3_QM_CP_MSG_BASE3_ADDR_LO_0 0x5682A0
+
+#define mmDMA3_QM_CP_MSG_BASE3_ADDR_LO_1 0x5682A4
+
+#define mmDMA3_QM_CP_MSG_BASE3_ADDR_LO_2 0x5682A8
+
+#define mmDMA3_QM_CP_MSG_BASE3_ADDR_LO_3 0x5682AC
+
+#define mmDMA3_QM_CP_MSG_BASE3_ADDR_LO_4 0x5682B0
+
+#define mmDMA3_QM_CP_MSG_BASE3_ADDR_HI_0 0x5682B4
+
+#define mmDMA3_QM_CP_MSG_BASE3_ADDR_HI_1 0x5682B8
+
+#define mmDMA3_QM_CP_MSG_BASE3_ADDR_HI_2 0x5682BC
+
+#define mmDMA3_QM_CP_MSG_BASE3_ADDR_HI_3 0x5682C0
+
+#define mmDMA3_QM_CP_MSG_BASE3_ADDR_HI_4 0x5682C4
+
+#define mmDMA3_QM_CP_LDMA_TSIZE_OFFSET_0 0x5682C8
+
+#define mmDMA3_QM_CP_LDMA_TSIZE_OFFSET_1 0x5682CC
+
+#define mmDMA3_QM_CP_LDMA_TSIZE_OFFSET_2 0x5682D0
+
+#define mmDMA3_QM_CP_LDMA_TSIZE_OFFSET_3 0x5682D4
+
+#define mmDMA3_QM_CP_LDMA_TSIZE_OFFSET_4 0x5682D8
+
+#define mmDMA3_QM_CP_LDMA_SRC_BASE_LO_OFFSET_0 0x5682E0
+
+#define mmDMA3_QM_CP_LDMA_SRC_BASE_LO_OFFSET_1 0x5682E4
+
+#define mmDMA3_QM_CP_LDMA_SRC_BASE_LO_OFFSET_2 0x5682E8
+
+#define mmDMA3_QM_CP_LDMA_SRC_BASE_LO_OFFSET_3 0x5682EC
+
+#define mmDMA3_QM_CP_LDMA_SRC_BASE_LO_OFFSET_4 0x5682F0
+
+#define mmDMA3_QM_CP_LDMA_DST_BASE_LO_OFFSET_0 0x5682F4
+
+#define mmDMA3_QM_CP_LDMA_DST_BASE_LO_OFFSET_1 0x5682F8
+
+#define mmDMA3_QM_CP_LDMA_DST_BASE_LO_OFFSET_2 0x5682FC
+
+#define mmDMA3_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 0x568300
+
+#define mmDMA3_QM_CP_LDMA_DST_BASE_LO_OFFSET_4 0x568304
+
+#define mmDMA3_QM_CP_FENCE0_RDATA_0 0x568308
+
+#define mmDMA3_QM_CP_FENCE0_RDATA_1 0x56830C
+
+#define mmDMA3_QM_CP_FENCE0_RDATA_2 0x568310
+
+#define mmDMA3_QM_CP_FENCE0_RDATA_3 0x568314
+
+#define mmDMA3_QM_CP_FENCE0_RDATA_4 0x568318
+
+#define mmDMA3_QM_CP_FENCE1_RDATA_0 0x56831C
+
+#define mmDMA3_QM_CP_FENCE1_RDATA_1 0x568320
+
+#define mmDMA3_QM_CP_FENCE1_RDATA_2 0x568324
+
+#define mmDMA3_QM_CP_FENCE1_RDATA_3 0x568328
+
+#define mmDMA3_QM_CP_FENCE1_RDATA_4 0x56832C
+
+#define mmDMA3_QM_CP_FENCE2_RDATA_0 0x568330
+
+#define mmDMA3_QM_CP_FENCE2_RDATA_1 0x568334
+
+#define mmDMA3_QM_CP_FENCE2_RDATA_2 0x568338
+
+#define mmDMA3_QM_CP_FENCE2_RDATA_3 0x56833C
+
+#define mmDMA3_QM_CP_FENCE2_RDATA_4 0x568340
+
+#define mmDMA3_QM_CP_FENCE3_RDATA_0 0x568344
+
+#define mmDMA3_QM_CP_FENCE3_RDATA_1 0x568348
+
+#define mmDMA3_QM_CP_FENCE3_RDATA_2 0x56834C
+
+#define mmDMA3_QM_CP_FENCE3_RDATA_3 0x568350
+
+#define mmDMA3_QM_CP_FENCE3_RDATA_4 0x568354
+
+#define mmDMA3_QM_CP_FENCE0_CNT_0 0x568358
+
+#define mmDMA3_QM_CP_FENCE0_CNT_1 0x56835C
+
+#define mmDMA3_QM_CP_FENCE0_CNT_2 0x568360
+
+#define mmDMA3_QM_CP_FENCE0_CNT_3 0x568364
+
+#define mmDMA3_QM_CP_FENCE0_CNT_4 0x568368
+
+#define mmDMA3_QM_CP_FENCE1_CNT_0 0x56836C
+
+#define mmDMA3_QM_CP_FENCE1_CNT_1 0x568370
+
+#define mmDMA3_QM_CP_FENCE1_CNT_2 0x568374
+
+#define mmDMA3_QM_CP_FENCE1_CNT_3 0x568378
+
+#define mmDMA3_QM_CP_FENCE1_CNT_4 0x56837C
+
+#define mmDMA3_QM_CP_FENCE2_CNT_0 0x568380
+
+#define mmDMA3_QM_CP_FENCE2_CNT_1 0x568384
+
+#define mmDMA3_QM_CP_FENCE2_CNT_2 0x568388
+
+#define mmDMA3_QM_CP_FENCE2_CNT_3 0x56838C
+
+#define mmDMA3_QM_CP_FENCE2_CNT_4 0x568390
+
+#define mmDMA3_QM_CP_FENCE3_CNT_0 0x568394
+
+#define mmDMA3_QM_CP_FENCE3_CNT_1 0x568398
+
+#define mmDMA3_QM_CP_FENCE3_CNT_2 0x56839C
+
+#define mmDMA3_QM_CP_FENCE3_CNT_3 0x5683A0
+
+#define mmDMA3_QM_CP_FENCE3_CNT_4 0x5683A4
+
+#define mmDMA3_QM_CP_STS_0 0x5683A8
+
+#define mmDMA3_QM_CP_STS_1 0x5683AC
+
+#define mmDMA3_QM_CP_STS_2 0x5683B0
+
+#define mmDMA3_QM_CP_STS_3 0x5683B4
+
+#define mmDMA3_QM_CP_STS_4 0x5683B8
+
+#define mmDMA3_QM_CP_CURRENT_INST_LO_0 0x5683BC
+
+#define mmDMA3_QM_CP_CURRENT_INST_LO_1 0x5683C0
+
+#define mmDMA3_QM_CP_CURRENT_INST_LO_2 0x5683C4
+
+#define mmDMA3_QM_CP_CURRENT_INST_LO_3 0x5683C8
+
+#define mmDMA3_QM_CP_CURRENT_INST_LO_4 0x5683CC
+
+#define mmDMA3_QM_CP_CURRENT_INST_HI_0 0x5683D0
+
+#define mmDMA3_QM_CP_CURRENT_INST_HI_1 0x5683D4
+
+#define mmDMA3_QM_CP_CURRENT_INST_HI_2 0x5683D8
+
+#define mmDMA3_QM_CP_CURRENT_INST_HI_3 0x5683DC
+
+#define mmDMA3_QM_CP_CURRENT_INST_HI_4 0x5683E0
+
+#define mmDMA3_QM_CP_BARRIER_CFG_0 0x5683F4
+
+#define mmDMA3_QM_CP_BARRIER_CFG_1 0x5683F8
+
+#define mmDMA3_QM_CP_BARRIER_CFG_2 0x5683FC
+
+#define mmDMA3_QM_CP_BARRIER_CFG_3 0x568400
+
+#define mmDMA3_QM_CP_BARRIER_CFG_4 0x568404
+
+#define mmDMA3_QM_CP_DBG_0_0 0x568408
+
+#define mmDMA3_QM_CP_DBG_0_1 0x56840C
+
+#define mmDMA3_QM_CP_DBG_0_2 0x568410
+
+#define mmDMA3_QM_CP_DBG_0_3 0x568414
+
+#define mmDMA3_QM_CP_DBG_0_4 0x568418
+
+#define mmDMA3_QM_CP_ARUSER_31_11_0 0x56841C
+
+#define mmDMA3_QM_CP_ARUSER_31_11_1 0x568420
+
+#define mmDMA3_QM_CP_ARUSER_31_11_2 0x568424
+
+#define mmDMA3_QM_CP_ARUSER_31_11_3 0x568428
+
+#define mmDMA3_QM_CP_ARUSER_31_11_4 0x56842C
+
+#define mmDMA3_QM_CP_AWUSER_31_11_0 0x568430
+
+#define mmDMA3_QM_CP_AWUSER_31_11_1 0x568434
+
+#define mmDMA3_QM_CP_AWUSER_31_11_2 0x568438
+
+#define mmDMA3_QM_CP_AWUSER_31_11_3 0x56843C
+
+#define mmDMA3_QM_CP_AWUSER_31_11_4 0x568440
+
+#define mmDMA3_QM_ARB_CFG_0 0x568A00
+
+#define mmDMA3_QM_ARB_CHOISE_Q_PUSH 0x568A04
+
+#define mmDMA3_QM_ARB_WRR_WEIGHT_0 0x568A08
+
+#define mmDMA3_QM_ARB_WRR_WEIGHT_1 0x568A0C
+
+#define mmDMA3_QM_ARB_WRR_WEIGHT_2 0x568A10
+
+#define mmDMA3_QM_ARB_WRR_WEIGHT_3 0x568A14
+
+#define mmDMA3_QM_ARB_CFG_1 0x568A18
+
+#define mmDMA3_QM_ARB_MST_AVAIL_CRED_0 0x568A20
+
+#define mmDMA3_QM_ARB_MST_AVAIL_CRED_1 0x568A24
+
+#define mmDMA3_QM_ARB_MST_AVAIL_CRED_2 0x568A28
+
+#define mmDMA3_QM_ARB_MST_AVAIL_CRED_3 0x568A2C
+
+#define mmDMA3_QM_ARB_MST_AVAIL_CRED_4 0x568A30
+
+#define mmDMA3_QM_ARB_MST_AVAIL_CRED_5 0x568A34
+
+#define mmDMA3_QM_ARB_MST_AVAIL_CRED_6 0x568A38
+
+#define mmDMA3_QM_ARB_MST_AVAIL_CRED_7 0x568A3C
+
+#define mmDMA3_QM_ARB_MST_AVAIL_CRED_8 0x568A40
+
+#define mmDMA3_QM_ARB_MST_AVAIL_CRED_9 0x568A44
+
+#define mmDMA3_QM_ARB_MST_AVAIL_CRED_10 0x568A48
+
+#define mmDMA3_QM_ARB_MST_AVAIL_CRED_11 0x568A4C
+
+#define mmDMA3_QM_ARB_MST_AVAIL_CRED_12 0x568A50
+
+#define mmDMA3_QM_ARB_MST_AVAIL_CRED_13 0x568A54
+
+#define mmDMA3_QM_ARB_MST_AVAIL_CRED_14 0x568A58
+
+#define mmDMA3_QM_ARB_MST_AVAIL_CRED_15 0x568A5C
+
+#define mmDMA3_QM_ARB_MST_AVAIL_CRED_16 0x568A60
+
+#define mmDMA3_QM_ARB_MST_AVAIL_CRED_17 0x568A64
+
+#define mmDMA3_QM_ARB_MST_AVAIL_CRED_18 0x568A68
+
+#define mmDMA3_QM_ARB_MST_AVAIL_CRED_19 0x568A6C
+
+#define mmDMA3_QM_ARB_MST_AVAIL_CRED_20 0x568A70
+
+#define mmDMA3_QM_ARB_MST_AVAIL_CRED_21 0x568A74
+
+#define mmDMA3_QM_ARB_MST_AVAIL_CRED_22 0x568A78
+
+#define mmDMA3_QM_ARB_MST_AVAIL_CRED_23 0x568A7C
+
+#define mmDMA3_QM_ARB_MST_AVAIL_CRED_24 0x568A80
+
+#define mmDMA3_QM_ARB_MST_AVAIL_CRED_25 0x568A84
+
+#define mmDMA3_QM_ARB_MST_AVAIL_CRED_26 0x568A88
+
+#define mmDMA3_QM_ARB_MST_AVAIL_CRED_27 0x568A8C
+
+#define mmDMA3_QM_ARB_MST_AVAIL_CRED_28 0x568A90
+
+#define mmDMA3_QM_ARB_MST_AVAIL_CRED_29 0x568A94
+
+#define mmDMA3_QM_ARB_MST_AVAIL_CRED_30 0x568A98
+
+#define mmDMA3_QM_ARB_MST_AVAIL_CRED_31 0x568A9C
+
+#define mmDMA3_QM_ARB_MST_CRED_INC 0x568AA0
+
+#define mmDMA3_QM_ARB_MST_CHOISE_PUSH_OFST_0 0x568AA4
+
+#define mmDMA3_QM_ARB_MST_CHOISE_PUSH_OFST_1 0x568AA8
+
+#define mmDMA3_QM_ARB_MST_CHOISE_PUSH_OFST_2 0x568AAC
+
+#define mmDMA3_QM_ARB_MST_CHOISE_PUSH_OFST_3 0x568AB0
+
+#define mmDMA3_QM_ARB_MST_CHOISE_PUSH_OFST_4 0x568AB4
+
+#define mmDMA3_QM_ARB_MST_CHOISE_PUSH_OFST_5 0x568AB8
+
+#define mmDMA3_QM_ARB_MST_CHOISE_PUSH_OFST_6 0x568ABC
+
+#define mmDMA3_QM_ARB_MST_CHOISE_PUSH_OFST_7 0x568AC0
+
+#define mmDMA3_QM_ARB_MST_CHOISE_PUSH_OFST_8 0x568AC4
+
+#define mmDMA3_QM_ARB_MST_CHOISE_PUSH_OFST_9 0x568AC8
+
+#define mmDMA3_QM_ARB_MST_CHOISE_PUSH_OFST_10 0x568ACC
+
+#define mmDMA3_QM_ARB_MST_CHOISE_PUSH_OFST_11 0x568AD0
+
+#define mmDMA3_QM_ARB_MST_CHOISE_PUSH_OFST_12 0x568AD4
+
+#define mmDMA3_QM_ARB_MST_CHOISE_PUSH_OFST_13 0x568AD8
+
+#define mmDMA3_QM_ARB_MST_CHOISE_PUSH_OFST_14 0x568ADC
+
+#define mmDMA3_QM_ARB_MST_CHOISE_PUSH_OFST_15 0x568AE0
+
+#define mmDMA3_QM_ARB_MST_CHOISE_PUSH_OFST_16 0x568AE4
+
+#define mmDMA3_QM_ARB_MST_CHOISE_PUSH_OFST_17 0x568AE8
+
+#define mmDMA3_QM_ARB_MST_CHOISE_PUSH_OFST_18 0x568AEC
+
+#define mmDMA3_QM_ARB_MST_CHOISE_PUSH_OFST_19 0x568AF0
+
+#define mmDMA3_QM_ARB_MST_CHOISE_PUSH_OFST_20 0x568AF4
+
+#define mmDMA3_QM_ARB_MST_CHOISE_PUSH_OFST_21 0x568AF8
+
+#define mmDMA3_QM_ARB_MST_CHOISE_PUSH_OFST_22 0x568AFC
+
+#define mmDMA3_QM_ARB_MST_CHOISE_PUSH_OFST_23 0x568B00
+
+#define mmDMA3_QM_ARB_MST_CHOISE_PUSH_OFST_24 0x568B04
+
+#define mmDMA3_QM_ARB_MST_CHOISE_PUSH_OFST_25 0x568B08
+
+#define mmDMA3_QM_ARB_MST_CHOISE_PUSH_OFST_26 0x568B0C
+
+#define mmDMA3_QM_ARB_MST_CHOISE_PUSH_OFST_27 0x568B10
+
+#define mmDMA3_QM_ARB_MST_CHOISE_PUSH_OFST_28 0x568B14
+
+#define mmDMA3_QM_ARB_MST_CHOISE_PUSH_OFST_29 0x568B18
+
+#define mmDMA3_QM_ARB_MST_CHOISE_PUSH_OFST_30 0x568B1C
+
+#define mmDMA3_QM_ARB_MST_CHOISE_PUSH_OFST_31 0x568B20
+
+#define mmDMA3_QM_ARB_SLV_MASTER_INC_CRED_OFST 0x568B28
+
+#define mmDMA3_QM_ARB_MST_SLAVE_EN 0x568B2C
+
+#define mmDMA3_QM_ARB_MST_QUIET_PER 0x568B34
+
+#define mmDMA3_QM_ARB_SLV_CHOISE_WDT 0x568B38
+
+#define mmDMA3_QM_ARB_SLV_ID 0x568B3C
+
+#define mmDMA3_QM_ARB_MSG_MAX_INFLIGHT 0x568B44
+
+#define mmDMA3_QM_ARB_MSG_AWUSER_31_11 0x568B48
+
+#define mmDMA3_QM_ARB_MSG_AWUSER_SEC_PROP 0x568B4C
+
+#define mmDMA3_QM_ARB_MSG_AWUSER_NON_SEC_PROP 0x568B50
+
+#define mmDMA3_QM_ARB_BASE_LO 0x568B54
+
+#define mmDMA3_QM_ARB_BASE_HI 0x568B58
+
+#define mmDMA3_QM_ARB_STATE_STS 0x568B80
+
+#define mmDMA3_QM_ARB_CHOISE_FULLNESS_STS 0x568B84
+
+#define mmDMA3_QM_ARB_MSG_STS 0x568B88
+
+#define mmDMA3_QM_ARB_SLV_CHOISE_Q_HEAD 0x568B8C
+
+#define mmDMA3_QM_ARB_ERR_CAUSE 0x568B9C
+
+#define mmDMA3_QM_ARB_ERR_MSG_EN 0x568BA0
+
+#define mmDMA3_QM_ARB_ERR_STS_DRP 0x568BA8
+
+#define mmDMA3_QM_ARB_MST_CRED_STS_0 0x568BB0
+
+#define mmDMA3_QM_ARB_MST_CRED_STS_1 0x568BB4
+
+#define mmDMA3_QM_ARB_MST_CRED_STS_2 0x568BB8
+
+#define mmDMA3_QM_ARB_MST_CRED_STS_3 0x568BBC
+
+#define mmDMA3_QM_ARB_MST_CRED_STS_4 0x568BC0
+
+#define mmDMA3_QM_ARB_MST_CRED_STS_5 0x568BC4
+
+#define mmDMA3_QM_ARB_MST_CRED_STS_6 0x568BC8
+
+#define mmDMA3_QM_ARB_MST_CRED_STS_7 0x568BCC
+
+#define mmDMA3_QM_ARB_MST_CRED_STS_8 0x568BD0
+
+#define mmDMA3_QM_ARB_MST_CRED_STS_9 0x568BD4
+
+#define mmDMA3_QM_ARB_MST_CRED_STS_10 0x568BD8
+
+#define mmDMA3_QM_ARB_MST_CRED_STS_11 0x568BDC
+
+#define mmDMA3_QM_ARB_MST_CRED_STS_12 0x568BE0
+
+#define mmDMA3_QM_ARB_MST_CRED_STS_13 0x568BE4
+
+#define mmDMA3_QM_ARB_MST_CRED_STS_14 0x568BE8
+
+#define mmDMA3_QM_ARB_MST_CRED_STS_15 0x568BEC
+
+#define mmDMA3_QM_ARB_MST_CRED_STS_16 0x568BF0
+
+#define mmDMA3_QM_ARB_MST_CRED_STS_17 0x568BF4
+
+#define mmDMA3_QM_ARB_MST_CRED_STS_18 0x568BF8
+
+#define mmDMA3_QM_ARB_MST_CRED_STS_19 0x568BFC
+
+#define mmDMA3_QM_ARB_MST_CRED_STS_20 0x568C00
+
+#define mmDMA3_QM_ARB_MST_CRED_STS_21 0x568C04
+
+#define mmDMA3_QM_ARB_MST_CRED_STS_22 0x568C08
+
+#define mmDMA3_QM_ARB_MST_CRED_STS_23 0x568C0C
+
+#define mmDMA3_QM_ARB_MST_CRED_STS_24 0x568C10
+
+#define mmDMA3_QM_ARB_MST_CRED_STS_25 0x568C14
+
+#define mmDMA3_QM_ARB_MST_CRED_STS_26 0x568C18
+
+#define mmDMA3_QM_ARB_MST_CRED_STS_27 0x568C1C
+
+#define mmDMA3_QM_ARB_MST_CRED_STS_28 0x568C20
+
+#define mmDMA3_QM_ARB_MST_CRED_STS_29 0x568C24
+
+#define mmDMA3_QM_ARB_MST_CRED_STS_30 0x568C28
+
+#define mmDMA3_QM_ARB_MST_CRED_STS_31 0x568C2C
+
+#define mmDMA3_QM_CGM_CFG 0x568C70
+
+#define mmDMA3_QM_CGM_STS 0x568C74
+
+#define mmDMA3_QM_CGM_CFG1 0x568C78
+
+#define mmDMA3_QM_LOCAL_RANGE_BASE 0x568C80
+
+#define mmDMA3_QM_LOCAL_RANGE_SIZE 0x568C84
+
+#define mmDMA3_QM_CSMR_STRICT_PRIO_CFG 0x568C90
+
+#define mmDMA3_QM_HBW_RD_RATE_LIM_CFG_1 0x568C94
+
+#define mmDMA3_QM_LBW_WR_RATE_LIM_CFG_0 0x568C98
+
+#define mmDMA3_QM_LBW_WR_RATE_LIM_CFG_1 0x568C9C
+
+#define mmDMA3_QM_HBW_RD_RATE_LIM_CFG_0 0x568CA0
+
+#define mmDMA3_QM_GLBL_AXCACHE 0x568CA4
+
+#define mmDMA3_QM_IND_GW_APB_CFG 0x568CB0
+
+#define mmDMA3_QM_IND_GW_APB_WDATA 0x568CB4
+
+#define mmDMA3_QM_IND_GW_APB_RDATA 0x568CB8
+
+#define mmDMA3_QM_IND_GW_APB_STATUS 0x568CBC
+
+#define mmDMA3_QM_GLBL_ERR_ADDR_LO 0x568CD0
+
+#define mmDMA3_QM_GLBL_ERR_ADDR_HI 0x568CD4
+
+#define mmDMA3_QM_GLBL_ERR_WDATA 0x568CD8
+
+#define mmDMA3_QM_GLBL_MEM_INIT_BUSY 0x568D00
+
+#endif /* ASIC_REG_DMA3_QM_REGS_H_ */
diff --git a/drivers/accel/habanalabs/include/gaudi/asic_reg/dma4_core_regs.h b/drivers/accel/habanalabs/include/gaudi/asic_reg/dma4_core_regs.h
new file mode 100644
index 0000000000..192d11404b
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi/asic_reg/dma4_core_regs.h
@@ -0,0 +1,156 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2016-2018 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ ** DO NOT EDIT BELOW **
+ ************************************/
+
+#ifndef ASIC_REG_DMA4_CORE_REGS_H_
+#define ASIC_REG_DMA4_CORE_REGS_H_
+
+/*
+ *****************************************
+ * DMA4_CORE (Prototype: DMA_CORE)
+ *****************************************
+ */
+
+#define mmDMA4_CORE_CFG_0 0x580000
+
+#define mmDMA4_CORE_CFG_1 0x580004
+
+#define mmDMA4_CORE_LBW_MAX_OUTSTAND 0x580008
+
+#define mmDMA4_CORE_SRC_BASE_LO 0x580014
+
+#define mmDMA4_CORE_SRC_BASE_HI 0x580018
+
+#define mmDMA4_CORE_DST_BASE_LO 0x58001C
+
+#define mmDMA4_CORE_DST_BASE_HI 0x580020
+
+#define mmDMA4_CORE_SRC_TSIZE_1 0x58002C
+
+#define mmDMA4_CORE_SRC_STRIDE_1 0x580030
+
+#define mmDMA4_CORE_SRC_TSIZE_2 0x580034
+
+#define mmDMA4_CORE_SRC_STRIDE_2 0x580038
+
+#define mmDMA4_CORE_SRC_TSIZE_3 0x58003C
+
+#define mmDMA4_CORE_SRC_STRIDE_3 0x580040
+
+#define mmDMA4_CORE_SRC_TSIZE_4 0x580044
+
+#define mmDMA4_CORE_SRC_STRIDE_4 0x580048
+
+#define mmDMA4_CORE_SRC_TSIZE_0 0x58004C
+
+#define mmDMA4_CORE_DST_TSIZE_1 0x580054
+
+#define mmDMA4_CORE_DST_STRIDE_1 0x580058
+
+#define mmDMA4_CORE_DST_TSIZE_2 0x58005C
+
+#define mmDMA4_CORE_DST_STRIDE_2 0x580060
+
+#define mmDMA4_CORE_DST_TSIZE_3 0x580064
+
+#define mmDMA4_CORE_DST_STRIDE_3 0x580068
+
+#define mmDMA4_CORE_DST_TSIZE_4 0x58006C
+
+#define mmDMA4_CORE_DST_STRIDE_4 0x580070
+
+#define mmDMA4_CORE_DST_TSIZE_0 0x580074
+
+#define mmDMA4_CORE_COMMIT 0x580078
+
+#define mmDMA4_CORE_WR_COMP_WDATA 0x58007C
+
+#define mmDMA4_CORE_WR_COMP_ADDR_LO 0x580080
+
+#define mmDMA4_CORE_WR_COMP_ADDR_HI 0x580084
+
+#define mmDMA4_CORE_WR_COMP_AWUSER_31_11 0x580088
+
+#define mmDMA4_CORE_TE_NUMROWS 0x580094
+
+#define mmDMA4_CORE_PROT 0x5800B8
+
+#define mmDMA4_CORE_SECURE_PROPS 0x5800F0
+
+#define mmDMA4_CORE_NON_SECURE_PROPS 0x5800F4
+
+#define mmDMA4_CORE_RD_MAX_OUTSTAND 0x580100
+
+#define mmDMA4_CORE_RD_MAX_SIZE 0x580104
+
+#define mmDMA4_CORE_RD_ARCACHE 0x580108
+
+#define mmDMA4_CORE_RD_ARUSER_31_11 0x580110
+
+#define mmDMA4_CORE_RD_INFLIGHTS 0x580114
+
+#define mmDMA4_CORE_WR_MAX_OUTSTAND 0x580120
+
+#define mmDMA4_CORE_WR_MAX_AWID 0x580124
+
+#define mmDMA4_CORE_WR_AWCACHE 0x580128
+
+#define mmDMA4_CORE_WR_AWUSER_31_11 0x580130
+
+#define mmDMA4_CORE_WR_INFLIGHTS 0x580134
+
+#define mmDMA4_CORE_RD_RATE_LIM_CFG_0 0x580150
+
+#define mmDMA4_CORE_RD_RATE_LIM_CFG_1 0x580154
+
+#define mmDMA4_CORE_WR_RATE_LIM_CFG_0 0x580158
+
+#define mmDMA4_CORE_WR_RATE_LIM_CFG_1 0x58015C
+
+#define mmDMA4_CORE_ERR_CFG 0x580160
+
+#define mmDMA4_CORE_ERR_CAUSE 0x580164
+
+#define mmDMA4_CORE_ERRMSG_ADDR_LO 0x580170
+
+#define mmDMA4_CORE_ERRMSG_ADDR_HI 0x580174
+
+#define mmDMA4_CORE_ERRMSG_WDATA 0x580178
+
+#define mmDMA4_CORE_STS0 0x580190
+
+#define mmDMA4_CORE_STS1 0x580194
+
+#define mmDMA4_CORE_RD_DBGMEM_ADD 0x580200
+
+#define mmDMA4_CORE_RD_DBGMEM_DATA_WR 0x580204
+
+#define mmDMA4_CORE_RD_DBGMEM_DATA_RD 0x580208
+
+#define mmDMA4_CORE_RD_DBGMEM_CTRL 0x58020C
+
+#define mmDMA4_CORE_RD_DBGMEM_RC 0x580210
+
+#define mmDMA4_CORE_DBG_HBW_AXI_AR_CNT 0x580220
+
+#define mmDMA4_CORE_DBG_HBW_AXI_AW_CNT 0x580224
+
+#define mmDMA4_CORE_DBG_LBW_AXI_AW_CNT 0x580228
+
+#define mmDMA4_CORE_DBG_DESC_CNT 0x58022C
+
+#define mmDMA4_CORE_DBG_STS 0x580230
+
+#define mmDMA4_CORE_DBG_RD_DESC_ID 0x580234
+
+#define mmDMA4_CORE_DBG_WR_DESC_ID 0x580238
+
+#endif /* ASIC_REG_DMA4_CORE_REGS_H_ */
diff --git a/drivers/accel/habanalabs/include/gaudi/asic_reg/dma4_qm_regs.h b/drivers/accel/habanalabs/include/gaudi/asic_reg/dma4_qm_regs.h
new file mode 100644
index 0000000000..f0cbda0d1e
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi/asic_reg/dma4_qm_regs.h
@@ -0,0 +1,834 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2016-2018 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ ** DO NOT EDIT BELOW **
+ ************************************/
+
+#ifndef ASIC_REG_DMA4_QM_REGS_H_
+#define ASIC_REG_DMA4_QM_REGS_H_
+
+/*
+ *****************************************
+ * DMA4_QM (Prototype: QMAN)
+ *****************************************
+ */
+
+#define mmDMA4_QM_GLBL_CFG0 0x588000
+
+#define mmDMA4_QM_GLBL_CFG1 0x588004
+
+#define mmDMA4_QM_GLBL_PROT 0x588008
+
+#define mmDMA4_QM_GLBL_ERR_CFG 0x58800C
+
+#define mmDMA4_QM_GLBL_SECURE_PROPS_0 0x588010
+
+#define mmDMA4_QM_GLBL_SECURE_PROPS_1 0x588014
+
+#define mmDMA4_QM_GLBL_SECURE_PROPS_2 0x588018
+
+#define mmDMA4_QM_GLBL_SECURE_PROPS_3 0x58801C
+
+#define mmDMA4_QM_GLBL_SECURE_PROPS_4 0x588020
+
+#define mmDMA4_QM_GLBL_NON_SECURE_PROPS_0 0x588024
+
+#define mmDMA4_QM_GLBL_NON_SECURE_PROPS_1 0x588028
+
+#define mmDMA4_QM_GLBL_NON_SECURE_PROPS_2 0x58802C
+
+#define mmDMA4_QM_GLBL_NON_SECURE_PROPS_3 0x588030
+
+#define mmDMA4_QM_GLBL_NON_SECURE_PROPS_4 0x588034
+
+#define mmDMA4_QM_GLBL_STS0 0x588038
+
+#define mmDMA4_QM_GLBL_STS1_0 0x588040
+
+#define mmDMA4_QM_GLBL_STS1_1 0x588044
+
+#define mmDMA4_QM_GLBL_STS1_2 0x588048
+
+#define mmDMA4_QM_GLBL_STS1_3 0x58804C
+
+#define mmDMA4_QM_GLBL_STS1_4 0x588050
+
+#define mmDMA4_QM_GLBL_MSG_EN_0 0x588054
+
+#define mmDMA4_QM_GLBL_MSG_EN_1 0x588058
+
+#define mmDMA4_QM_GLBL_MSG_EN_2 0x58805C
+
+#define mmDMA4_QM_GLBL_MSG_EN_3 0x588060
+
+#define mmDMA4_QM_GLBL_MSG_EN_4 0x588068
+
+#define mmDMA4_QM_PQ_BASE_LO_0 0x588070
+
+#define mmDMA4_QM_PQ_BASE_LO_1 0x588074
+
+#define mmDMA4_QM_PQ_BASE_LO_2 0x588078
+
+#define mmDMA4_QM_PQ_BASE_LO_3 0x58807C
+
+#define mmDMA4_QM_PQ_BASE_HI_0 0x588080
+
+#define mmDMA4_QM_PQ_BASE_HI_1 0x588084
+
+#define mmDMA4_QM_PQ_BASE_HI_2 0x588088
+
+#define mmDMA4_QM_PQ_BASE_HI_3 0x58808C
+
+#define mmDMA4_QM_PQ_SIZE_0 0x588090
+
+#define mmDMA4_QM_PQ_SIZE_1 0x588094
+
+#define mmDMA4_QM_PQ_SIZE_2 0x588098
+
+#define mmDMA4_QM_PQ_SIZE_3 0x58809C
+
+#define mmDMA4_QM_PQ_PI_0 0x5880A0
+
+#define mmDMA4_QM_PQ_PI_1 0x5880A4
+
+#define mmDMA4_QM_PQ_PI_2 0x5880A8
+
+#define mmDMA4_QM_PQ_PI_3 0x5880AC
+
+#define mmDMA4_QM_PQ_CI_0 0x5880B0
+
+#define mmDMA4_QM_PQ_CI_1 0x5880B4
+
+#define mmDMA4_QM_PQ_CI_2 0x5880B8
+
+#define mmDMA4_QM_PQ_CI_3 0x5880BC
+
+#define mmDMA4_QM_PQ_CFG0_0 0x5880C0
+
+#define mmDMA4_QM_PQ_CFG0_1 0x5880C4
+
+#define mmDMA4_QM_PQ_CFG0_2 0x5880C8
+
+#define mmDMA4_QM_PQ_CFG0_3 0x5880CC
+
+#define mmDMA4_QM_PQ_CFG1_0 0x5880D0
+
+#define mmDMA4_QM_PQ_CFG1_1 0x5880D4
+
+#define mmDMA4_QM_PQ_CFG1_2 0x5880D8
+
+#define mmDMA4_QM_PQ_CFG1_3 0x5880DC
+
+#define mmDMA4_QM_PQ_ARUSER_31_11_0 0x5880E0
+
+#define mmDMA4_QM_PQ_ARUSER_31_11_1 0x5880E4
+
+#define mmDMA4_QM_PQ_ARUSER_31_11_2 0x5880E8
+
+#define mmDMA4_QM_PQ_ARUSER_31_11_3 0x5880EC
+
+#define mmDMA4_QM_PQ_STS0_0 0x5880F0
+
+#define mmDMA4_QM_PQ_STS0_1 0x5880F4
+
+#define mmDMA4_QM_PQ_STS0_2 0x5880F8
+
+#define mmDMA4_QM_PQ_STS0_3 0x5880FC
+
+#define mmDMA4_QM_PQ_STS1_0 0x588100
+
+#define mmDMA4_QM_PQ_STS1_1 0x588104
+
+#define mmDMA4_QM_PQ_STS1_2 0x588108
+
+#define mmDMA4_QM_PQ_STS1_3 0x58810C
+
+#define mmDMA4_QM_CQ_CFG0_0 0x588110
+
+#define mmDMA4_QM_CQ_CFG0_1 0x588114
+
+#define mmDMA4_QM_CQ_CFG0_2 0x588118
+
+#define mmDMA4_QM_CQ_CFG0_3 0x58811C
+
+#define mmDMA4_QM_CQ_CFG0_4 0x588120
+
+#define mmDMA4_QM_CQ_CFG1_0 0x588124
+
+#define mmDMA4_QM_CQ_CFG1_1 0x588128
+
+#define mmDMA4_QM_CQ_CFG1_2 0x58812C
+
+#define mmDMA4_QM_CQ_CFG1_3 0x588130
+
+#define mmDMA4_QM_CQ_CFG1_4 0x588134
+
+#define mmDMA4_QM_CQ_ARUSER_31_11_0 0x588138
+
+#define mmDMA4_QM_CQ_ARUSER_31_11_1 0x58813C
+
+#define mmDMA4_QM_CQ_ARUSER_31_11_2 0x588140
+
+#define mmDMA4_QM_CQ_ARUSER_31_11_3 0x588144
+
+#define mmDMA4_QM_CQ_ARUSER_31_11_4 0x588148
+
+#define mmDMA4_QM_CQ_STS0_0 0x58814C
+
+#define mmDMA4_QM_CQ_STS0_1 0x588150
+
+#define mmDMA4_QM_CQ_STS0_2 0x588154
+
+#define mmDMA4_QM_CQ_STS0_3 0x588158
+
+#define mmDMA4_QM_CQ_STS0_4 0x58815C
+
+#define mmDMA4_QM_CQ_STS1_0 0x588160
+
+#define mmDMA4_QM_CQ_STS1_1 0x588164
+
+#define mmDMA4_QM_CQ_STS1_2 0x588168
+
+#define mmDMA4_QM_CQ_STS1_3 0x58816C
+
+#define mmDMA4_QM_CQ_STS1_4 0x588170
+
+#define mmDMA4_QM_CQ_PTR_LO_0 0x588174
+
+#define mmDMA4_QM_CQ_PTR_HI_0 0x588178
+
+#define mmDMA4_QM_CQ_TSIZE_0 0x58817C
+
+#define mmDMA4_QM_CQ_CTL_0 0x588180
+
+#define mmDMA4_QM_CQ_PTR_LO_1 0x588184
+
+#define mmDMA4_QM_CQ_PTR_HI_1 0x588188
+
+#define mmDMA4_QM_CQ_TSIZE_1 0x58818C
+
+#define mmDMA4_QM_CQ_CTL_1 0x588190
+
+#define mmDMA4_QM_CQ_PTR_LO_2 0x588194
+
+#define mmDMA4_QM_CQ_PTR_HI_2 0x588198
+
+#define mmDMA4_QM_CQ_TSIZE_2 0x58819C
+
+#define mmDMA4_QM_CQ_CTL_2 0x5881A0
+
+#define mmDMA4_QM_CQ_PTR_LO_3 0x5881A4
+
+#define mmDMA4_QM_CQ_PTR_HI_3 0x5881A8
+
+#define mmDMA4_QM_CQ_TSIZE_3 0x5881AC
+
+#define mmDMA4_QM_CQ_CTL_3 0x5881B0
+
+#define mmDMA4_QM_CQ_PTR_LO_4 0x5881B4
+
+#define mmDMA4_QM_CQ_PTR_HI_4 0x5881B8
+
+#define mmDMA4_QM_CQ_TSIZE_4 0x5881BC
+
+#define mmDMA4_QM_CQ_CTL_4 0x5881C0
+
+#define mmDMA4_QM_CQ_PTR_LO_STS_0 0x5881C4
+
+#define mmDMA4_QM_CQ_PTR_LO_STS_1 0x5881C8
+
+#define mmDMA4_QM_CQ_PTR_LO_STS_2 0x5881CC
+
+#define mmDMA4_QM_CQ_PTR_LO_STS_3 0x5881D0
+
+#define mmDMA4_QM_CQ_PTR_LO_STS_4 0x5881D4
+
+#define mmDMA4_QM_CQ_PTR_HI_STS_0 0x5881D8
+
+#define mmDMA4_QM_CQ_PTR_HI_STS_1 0x5881DC
+
+#define mmDMA4_QM_CQ_PTR_HI_STS_2 0x5881E0
+
+#define mmDMA4_QM_CQ_PTR_HI_STS_3 0x5881E4
+
+#define mmDMA4_QM_CQ_PTR_HI_STS_4 0x5881E8
+
+#define mmDMA4_QM_CQ_TSIZE_STS_0 0x5881EC
+
+#define mmDMA4_QM_CQ_TSIZE_STS_1 0x5881F0
+
+#define mmDMA4_QM_CQ_TSIZE_STS_2 0x5881F4
+
+#define mmDMA4_QM_CQ_TSIZE_STS_3 0x5881F8
+
+#define mmDMA4_QM_CQ_TSIZE_STS_4 0x5881FC
+
+#define mmDMA4_QM_CQ_CTL_STS_0 0x588200
+
+#define mmDMA4_QM_CQ_CTL_STS_1 0x588204
+
+#define mmDMA4_QM_CQ_CTL_STS_2 0x588208
+
+#define mmDMA4_QM_CQ_CTL_STS_3 0x58820C
+
+#define mmDMA4_QM_CQ_CTL_STS_4 0x588210
+
+#define mmDMA4_QM_CQ_IFIFO_CNT_0 0x588214
+
+#define mmDMA4_QM_CQ_IFIFO_CNT_1 0x588218
+
+#define mmDMA4_QM_CQ_IFIFO_CNT_2 0x58821C
+
+#define mmDMA4_QM_CQ_IFIFO_CNT_3 0x588220
+
+#define mmDMA4_QM_CQ_IFIFO_CNT_4 0x588224
+
+#define mmDMA4_QM_CP_MSG_BASE0_ADDR_LO_0 0x588228
+
+#define mmDMA4_QM_CP_MSG_BASE0_ADDR_LO_1 0x58822C
+
+#define mmDMA4_QM_CP_MSG_BASE0_ADDR_LO_2 0x588230
+
+#define mmDMA4_QM_CP_MSG_BASE0_ADDR_LO_3 0x588234
+
+#define mmDMA4_QM_CP_MSG_BASE0_ADDR_LO_4 0x588238
+
+#define mmDMA4_QM_CP_MSG_BASE0_ADDR_HI_0 0x58823C
+
+#define mmDMA4_QM_CP_MSG_BASE0_ADDR_HI_1 0x588240
+
+#define mmDMA4_QM_CP_MSG_BASE0_ADDR_HI_2 0x588244
+
+#define mmDMA4_QM_CP_MSG_BASE0_ADDR_HI_3 0x588248
+
+#define mmDMA4_QM_CP_MSG_BASE0_ADDR_HI_4 0x58824C
+
+#define mmDMA4_QM_CP_MSG_BASE1_ADDR_LO_0 0x588250
+
+#define mmDMA4_QM_CP_MSG_BASE1_ADDR_LO_1 0x588254
+
+#define mmDMA4_QM_CP_MSG_BASE1_ADDR_LO_2 0x588258
+
+#define mmDMA4_QM_CP_MSG_BASE1_ADDR_LO_3 0x58825C
+
+#define mmDMA4_QM_CP_MSG_BASE1_ADDR_LO_4 0x588260
+
+#define mmDMA4_QM_CP_MSG_BASE1_ADDR_HI_0 0x588264
+
+#define mmDMA4_QM_CP_MSG_BASE1_ADDR_HI_1 0x588268
+
+#define mmDMA4_QM_CP_MSG_BASE1_ADDR_HI_2 0x58826C
+
+#define mmDMA4_QM_CP_MSG_BASE1_ADDR_HI_3 0x588270
+
+#define mmDMA4_QM_CP_MSG_BASE1_ADDR_HI_4 0x588274
+
+#define mmDMA4_QM_CP_MSG_BASE2_ADDR_LO_0 0x588278
+
+#define mmDMA4_QM_CP_MSG_BASE2_ADDR_LO_1 0x58827C
+
+#define mmDMA4_QM_CP_MSG_BASE2_ADDR_LO_2 0x588280
+
+#define mmDMA4_QM_CP_MSG_BASE2_ADDR_LO_3 0x588284
+
+#define mmDMA4_QM_CP_MSG_BASE2_ADDR_LO_4 0x588288
+
+#define mmDMA4_QM_CP_MSG_BASE2_ADDR_HI_0 0x58828C
+
+#define mmDMA4_QM_CP_MSG_BASE2_ADDR_HI_1 0x588290
+
+#define mmDMA4_QM_CP_MSG_BASE2_ADDR_HI_2 0x588294
+
+#define mmDMA4_QM_CP_MSG_BASE2_ADDR_HI_3 0x588298
+
+#define mmDMA4_QM_CP_MSG_BASE2_ADDR_HI_4 0x58829C
+
+#define mmDMA4_QM_CP_MSG_BASE3_ADDR_LO_0 0x5882A0
+
+#define mmDMA4_QM_CP_MSG_BASE3_ADDR_LO_1 0x5882A4
+
+#define mmDMA4_QM_CP_MSG_BASE3_ADDR_LO_2 0x5882A8
+
+#define mmDMA4_QM_CP_MSG_BASE3_ADDR_LO_3 0x5882AC
+
+#define mmDMA4_QM_CP_MSG_BASE3_ADDR_LO_4 0x5882B0
+
+#define mmDMA4_QM_CP_MSG_BASE3_ADDR_HI_0 0x5882B4
+
+#define mmDMA4_QM_CP_MSG_BASE3_ADDR_HI_1 0x5882B8
+
+#define mmDMA4_QM_CP_MSG_BASE3_ADDR_HI_2 0x5882BC
+
+#define mmDMA4_QM_CP_MSG_BASE3_ADDR_HI_3 0x5882C0
+
+#define mmDMA4_QM_CP_MSG_BASE3_ADDR_HI_4 0x5882C4
+
+#define mmDMA4_QM_CP_LDMA_TSIZE_OFFSET_0 0x5882C8
+
+#define mmDMA4_QM_CP_LDMA_TSIZE_OFFSET_1 0x5882CC
+
+#define mmDMA4_QM_CP_LDMA_TSIZE_OFFSET_2 0x5882D0
+
+#define mmDMA4_QM_CP_LDMA_TSIZE_OFFSET_3 0x5882D4
+
+#define mmDMA4_QM_CP_LDMA_TSIZE_OFFSET_4 0x5882D8
+
+#define mmDMA4_QM_CP_LDMA_SRC_BASE_LO_OFFSET_0 0x5882E0
+
+#define mmDMA4_QM_CP_LDMA_SRC_BASE_LO_OFFSET_1 0x5882E4
+
+#define mmDMA4_QM_CP_LDMA_SRC_BASE_LO_OFFSET_2 0x5882E8
+
+#define mmDMA4_QM_CP_LDMA_SRC_BASE_LO_OFFSET_3 0x5882EC
+
+#define mmDMA4_QM_CP_LDMA_SRC_BASE_LO_OFFSET_4 0x5882F0
+
+#define mmDMA4_QM_CP_LDMA_DST_BASE_LO_OFFSET_0 0x5882F4
+
+#define mmDMA4_QM_CP_LDMA_DST_BASE_LO_OFFSET_1 0x5882F8
+
+#define mmDMA4_QM_CP_LDMA_DST_BASE_LO_OFFSET_2 0x5882FC
+
+#define mmDMA4_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 0x588300
+
+#define mmDMA4_QM_CP_LDMA_DST_BASE_LO_OFFSET_4 0x588304
+
+#define mmDMA4_QM_CP_FENCE0_RDATA_0 0x588308
+
+#define mmDMA4_QM_CP_FENCE0_RDATA_1 0x58830C
+
+#define mmDMA4_QM_CP_FENCE0_RDATA_2 0x588310
+
+#define mmDMA4_QM_CP_FENCE0_RDATA_3 0x588314
+
+#define mmDMA4_QM_CP_FENCE0_RDATA_4 0x588318
+
+#define mmDMA4_QM_CP_FENCE1_RDATA_0 0x58831C
+
+#define mmDMA4_QM_CP_FENCE1_RDATA_1 0x588320
+
+#define mmDMA4_QM_CP_FENCE1_RDATA_2 0x588324
+
+#define mmDMA4_QM_CP_FENCE1_RDATA_3 0x588328
+
+#define mmDMA4_QM_CP_FENCE1_RDATA_4 0x58832C
+
+#define mmDMA4_QM_CP_FENCE2_RDATA_0 0x588330
+
+#define mmDMA4_QM_CP_FENCE2_RDATA_1 0x588334
+
+#define mmDMA4_QM_CP_FENCE2_RDATA_2 0x588338
+
+#define mmDMA4_QM_CP_FENCE2_RDATA_3 0x58833C
+
+#define mmDMA4_QM_CP_FENCE2_RDATA_4 0x588340
+
+#define mmDMA4_QM_CP_FENCE3_RDATA_0 0x588344
+
+#define mmDMA4_QM_CP_FENCE3_RDATA_1 0x588348
+
+#define mmDMA4_QM_CP_FENCE3_RDATA_2 0x58834C
+
+#define mmDMA4_QM_CP_FENCE3_RDATA_3 0x588350
+
+#define mmDMA4_QM_CP_FENCE3_RDATA_4 0x588354
+
+#define mmDMA4_QM_CP_FENCE0_CNT_0 0x588358
+
+#define mmDMA4_QM_CP_FENCE0_CNT_1 0x58835C
+
+#define mmDMA4_QM_CP_FENCE0_CNT_2 0x588360
+
+#define mmDMA4_QM_CP_FENCE0_CNT_3 0x588364
+
+#define mmDMA4_QM_CP_FENCE0_CNT_4 0x588368
+
+#define mmDMA4_QM_CP_FENCE1_CNT_0 0x58836C
+
+#define mmDMA4_QM_CP_FENCE1_CNT_1 0x588370
+
+#define mmDMA4_QM_CP_FENCE1_CNT_2 0x588374
+
+#define mmDMA4_QM_CP_FENCE1_CNT_3 0x588378
+
+#define mmDMA4_QM_CP_FENCE1_CNT_4 0x58837C
+
+#define mmDMA4_QM_CP_FENCE2_CNT_0 0x588380
+
+#define mmDMA4_QM_CP_FENCE2_CNT_1 0x588384
+
+#define mmDMA4_QM_CP_FENCE2_CNT_2 0x588388
+
+#define mmDMA4_QM_CP_FENCE2_CNT_3 0x58838C
+
+#define mmDMA4_QM_CP_FENCE2_CNT_4 0x588390
+
+#define mmDMA4_QM_CP_FENCE3_CNT_0 0x588394
+
+#define mmDMA4_QM_CP_FENCE3_CNT_1 0x588398
+
+#define mmDMA4_QM_CP_FENCE3_CNT_2 0x58839C
+
+#define mmDMA4_QM_CP_FENCE3_CNT_3 0x5883A0
+
+#define mmDMA4_QM_CP_FENCE3_CNT_4 0x5883A4
+
+#define mmDMA4_QM_CP_STS_0 0x5883A8
+
+#define mmDMA4_QM_CP_STS_1 0x5883AC
+
+#define mmDMA4_QM_CP_STS_2 0x5883B0
+
+#define mmDMA4_QM_CP_STS_3 0x5883B4
+
+#define mmDMA4_QM_CP_STS_4 0x5883B8
+
+#define mmDMA4_QM_CP_CURRENT_INST_LO_0 0x5883BC
+
+#define mmDMA4_QM_CP_CURRENT_INST_LO_1 0x5883C0
+
+#define mmDMA4_QM_CP_CURRENT_INST_LO_2 0x5883C4
+
+#define mmDMA4_QM_CP_CURRENT_INST_LO_3 0x5883C8
+
+#define mmDMA4_QM_CP_CURRENT_INST_LO_4 0x5883CC
+
+#define mmDMA4_QM_CP_CURRENT_INST_HI_0 0x5883D0
+
+#define mmDMA4_QM_CP_CURRENT_INST_HI_1 0x5883D4
+
+#define mmDMA4_QM_CP_CURRENT_INST_HI_2 0x5883D8
+
+#define mmDMA4_QM_CP_CURRENT_INST_HI_3 0x5883DC
+
+#define mmDMA4_QM_CP_CURRENT_INST_HI_4 0x5883E0
+
+#define mmDMA4_QM_CP_BARRIER_CFG_0 0x5883F4
+
+#define mmDMA4_QM_CP_BARRIER_CFG_1 0x5883F8
+
+#define mmDMA4_QM_CP_BARRIER_CFG_2 0x5883FC
+
+#define mmDMA4_QM_CP_BARRIER_CFG_3 0x588400
+
+#define mmDMA4_QM_CP_BARRIER_CFG_4 0x588404
+
+#define mmDMA4_QM_CP_DBG_0_0 0x588408
+
+#define mmDMA4_QM_CP_DBG_0_1 0x58840C
+
+#define mmDMA4_QM_CP_DBG_0_2 0x588410
+
+#define mmDMA4_QM_CP_DBG_0_3 0x588414
+
+#define mmDMA4_QM_CP_DBG_0_4 0x588418
+
+#define mmDMA4_QM_CP_ARUSER_31_11_0 0x58841C
+
+#define mmDMA4_QM_CP_ARUSER_31_11_1 0x588420
+
+#define mmDMA4_QM_CP_ARUSER_31_11_2 0x588424
+
+#define mmDMA4_QM_CP_ARUSER_31_11_3 0x588428
+
+#define mmDMA4_QM_CP_ARUSER_31_11_4 0x58842C
+
+#define mmDMA4_QM_CP_AWUSER_31_11_0 0x588430
+
+#define mmDMA4_QM_CP_AWUSER_31_11_1 0x588434
+
+#define mmDMA4_QM_CP_AWUSER_31_11_2 0x588438
+
+#define mmDMA4_QM_CP_AWUSER_31_11_3 0x58843C
+
+#define mmDMA4_QM_CP_AWUSER_31_11_4 0x588440
+
+#define mmDMA4_QM_ARB_CFG_0 0x588A00
+
+#define mmDMA4_QM_ARB_CHOISE_Q_PUSH 0x588A04
+
+#define mmDMA4_QM_ARB_WRR_WEIGHT_0 0x588A08
+
+#define mmDMA4_QM_ARB_WRR_WEIGHT_1 0x588A0C
+
+#define mmDMA4_QM_ARB_WRR_WEIGHT_2 0x588A10
+
+#define mmDMA4_QM_ARB_WRR_WEIGHT_3 0x588A14
+
+#define mmDMA4_QM_ARB_CFG_1 0x588A18
+
+#define mmDMA4_QM_ARB_MST_AVAIL_CRED_0 0x588A20
+
+#define mmDMA4_QM_ARB_MST_AVAIL_CRED_1 0x588A24
+
+#define mmDMA4_QM_ARB_MST_AVAIL_CRED_2 0x588A28
+
+#define mmDMA4_QM_ARB_MST_AVAIL_CRED_3 0x588A2C
+
+#define mmDMA4_QM_ARB_MST_AVAIL_CRED_4 0x588A30
+
+#define mmDMA4_QM_ARB_MST_AVAIL_CRED_5 0x588A34
+
+#define mmDMA4_QM_ARB_MST_AVAIL_CRED_6 0x588A38
+
+#define mmDMA4_QM_ARB_MST_AVAIL_CRED_7 0x588A3C
+
+#define mmDMA4_QM_ARB_MST_AVAIL_CRED_8 0x588A40
+
+#define mmDMA4_QM_ARB_MST_AVAIL_CRED_9 0x588A44
+
+#define mmDMA4_QM_ARB_MST_AVAIL_CRED_10 0x588A48
+
+#define mmDMA4_QM_ARB_MST_AVAIL_CRED_11 0x588A4C
+
+#define mmDMA4_QM_ARB_MST_AVAIL_CRED_12 0x588A50
+
+#define mmDMA4_QM_ARB_MST_AVAIL_CRED_13 0x588A54
+
+#define mmDMA4_QM_ARB_MST_AVAIL_CRED_14 0x588A58
+
+#define mmDMA4_QM_ARB_MST_AVAIL_CRED_15 0x588A5C
+
+#define mmDMA4_QM_ARB_MST_AVAIL_CRED_16 0x588A60
+
+#define mmDMA4_QM_ARB_MST_AVAIL_CRED_17 0x588A64
+
+#define mmDMA4_QM_ARB_MST_AVAIL_CRED_18 0x588A68
+
+#define mmDMA4_QM_ARB_MST_AVAIL_CRED_19 0x588A6C
+
+#define mmDMA4_QM_ARB_MST_AVAIL_CRED_20 0x588A70
+
+#define mmDMA4_QM_ARB_MST_AVAIL_CRED_21 0x588A74
+
+#define mmDMA4_QM_ARB_MST_AVAIL_CRED_22 0x588A78
+
+#define mmDMA4_QM_ARB_MST_AVAIL_CRED_23 0x588A7C
+
+#define mmDMA4_QM_ARB_MST_AVAIL_CRED_24 0x588A80
+
+#define mmDMA4_QM_ARB_MST_AVAIL_CRED_25 0x588A84
+
+#define mmDMA4_QM_ARB_MST_AVAIL_CRED_26 0x588A88
+
+#define mmDMA4_QM_ARB_MST_AVAIL_CRED_27 0x588A8C
+
+#define mmDMA4_QM_ARB_MST_AVAIL_CRED_28 0x588A90
+
+#define mmDMA4_QM_ARB_MST_AVAIL_CRED_29 0x588A94
+
+#define mmDMA4_QM_ARB_MST_AVAIL_CRED_30 0x588A98
+
+#define mmDMA4_QM_ARB_MST_AVAIL_CRED_31 0x588A9C
+
+#define mmDMA4_QM_ARB_MST_CRED_INC 0x588AA0
+
+#define mmDMA4_QM_ARB_MST_CHOISE_PUSH_OFST_0 0x588AA4
+
+#define mmDMA4_QM_ARB_MST_CHOISE_PUSH_OFST_1 0x588AA8
+
+#define mmDMA4_QM_ARB_MST_CHOISE_PUSH_OFST_2 0x588AAC
+
+#define mmDMA4_QM_ARB_MST_CHOISE_PUSH_OFST_3 0x588AB0
+
+#define mmDMA4_QM_ARB_MST_CHOISE_PUSH_OFST_4 0x588AB4
+
+#define mmDMA4_QM_ARB_MST_CHOISE_PUSH_OFST_5 0x588AB8
+
+#define mmDMA4_QM_ARB_MST_CHOISE_PUSH_OFST_6 0x588ABC
+
+#define mmDMA4_QM_ARB_MST_CHOISE_PUSH_OFST_7 0x588AC0
+
+#define mmDMA4_QM_ARB_MST_CHOISE_PUSH_OFST_8 0x588AC4
+
+#define mmDMA4_QM_ARB_MST_CHOISE_PUSH_OFST_9 0x588AC8
+
+#define mmDMA4_QM_ARB_MST_CHOISE_PUSH_OFST_10 0x588ACC
+
+#define mmDMA4_QM_ARB_MST_CHOISE_PUSH_OFST_11 0x588AD0
+
+#define mmDMA4_QM_ARB_MST_CHOISE_PUSH_OFST_12 0x588AD4
+
+#define mmDMA4_QM_ARB_MST_CHOISE_PUSH_OFST_13 0x588AD8
+
+#define mmDMA4_QM_ARB_MST_CHOISE_PUSH_OFST_14 0x588ADC
+
+#define mmDMA4_QM_ARB_MST_CHOISE_PUSH_OFST_15 0x588AE0
+
+#define mmDMA4_QM_ARB_MST_CHOISE_PUSH_OFST_16 0x588AE4
+
+#define mmDMA4_QM_ARB_MST_CHOISE_PUSH_OFST_17 0x588AE8
+
+#define mmDMA4_QM_ARB_MST_CHOISE_PUSH_OFST_18 0x588AEC
+
+#define mmDMA4_QM_ARB_MST_CHOISE_PUSH_OFST_19 0x588AF0
+
+#define mmDMA4_QM_ARB_MST_CHOISE_PUSH_OFST_20 0x588AF4
+
+#define mmDMA4_QM_ARB_MST_CHOISE_PUSH_OFST_21 0x588AF8
+
+#define mmDMA4_QM_ARB_MST_CHOISE_PUSH_OFST_22 0x588AFC
+
+#define mmDMA4_QM_ARB_MST_CHOISE_PUSH_OFST_23 0x588B00
+
+#define mmDMA4_QM_ARB_MST_CHOISE_PUSH_OFST_24 0x588B04
+
+#define mmDMA4_QM_ARB_MST_CHOISE_PUSH_OFST_25 0x588B08
+
+#define mmDMA4_QM_ARB_MST_CHOISE_PUSH_OFST_26 0x588B0C
+
+#define mmDMA4_QM_ARB_MST_CHOISE_PUSH_OFST_27 0x588B10
+
+#define mmDMA4_QM_ARB_MST_CHOISE_PUSH_OFST_28 0x588B14
+
+#define mmDMA4_QM_ARB_MST_CHOISE_PUSH_OFST_29 0x588B18
+
+#define mmDMA4_QM_ARB_MST_CHOISE_PUSH_OFST_30 0x588B1C
+
+#define mmDMA4_QM_ARB_MST_CHOISE_PUSH_OFST_31 0x588B20
+
+#define mmDMA4_QM_ARB_SLV_MASTER_INC_CRED_OFST 0x588B28
+
+#define mmDMA4_QM_ARB_MST_SLAVE_EN 0x588B2C
+
+#define mmDMA4_QM_ARB_MST_QUIET_PER 0x588B34
+
+#define mmDMA4_QM_ARB_SLV_CHOISE_WDT 0x588B38
+
+#define mmDMA4_QM_ARB_SLV_ID 0x588B3C
+
+#define mmDMA4_QM_ARB_MSG_MAX_INFLIGHT 0x588B44
+
+#define mmDMA4_QM_ARB_MSG_AWUSER_31_11 0x588B48
+
+#define mmDMA4_QM_ARB_MSG_AWUSER_SEC_PROP 0x588B4C
+
+#define mmDMA4_QM_ARB_MSG_AWUSER_NON_SEC_PROP 0x588B50
+
+#define mmDMA4_QM_ARB_BASE_LO 0x588B54
+
+#define mmDMA4_QM_ARB_BASE_HI 0x588B58
+
+#define mmDMA4_QM_ARB_STATE_STS 0x588B80
+
+#define mmDMA4_QM_ARB_CHOISE_FULLNESS_STS 0x588B84
+
+#define mmDMA4_QM_ARB_MSG_STS 0x588B88
+
+#define mmDMA4_QM_ARB_SLV_CHOISE_Q_HEAD 0x588B8C
+
+#define mmDMA4_QM_ARB_ERR_CAUSE 0x588B9C
+
+#define mmDMA4_QM_ARB_ERR_MSG_EN 0x588BA0
+
+#define mmDMA4_QM_ARB_ERR_STS_DRP 0x588BA8
+
+#define mmDMA4_QM_ARB_MST_CRED_STS_0 0x588BB0
+
+#define mmDMA4_QM_ARB_MST_CRED_STS_1 0x588BB4
+
+#define mmDMA4_QM_ARB_MST_CRED_STS_2 0x588BB8
+
+#define mmDMA4_QM_ARB_MST_CRED_STS_3 0x588BBC
+
+#define mmDMA4_QM_ARB_MST_CRED_STS_4 0x588BC0
+
+#define mmDMA4_QM_ARB_MST_CRED_STS_5 0x588BC4
+
+#define mmDMA4_QM_ARB_MST_CRED_STS_6 0x588BC8
+
+#define mmDMA4_QM_ARB_MST_CRED_STS_7 0x588BCC
+
+#define mmDMA4_QM_ARB_MST_CRED_STS_8 0x588BD0
+
+#define mmDMA4_QM_ARB_MST_CRED_STS_9 0x588BD4
+
+#define mmDMA4_QM_ARB_MST_CRED_STS_10 0x588BD8
+
+#define mmDMA4_QM_ARB_MST_CRED_STS_11 0x588BDC
+
+#define mmDMA4_QM_ARB_MST_CRED_STS_12 0x588BE0
+
+#define mmDMA4_QM_ARB_MST_CRED_STS_13 0x588BE4
+
+#define mmDMA4_QM_ARB_MST_CRED_STS_14 0x588BE8
+
+#define mmDMA4_QM_ARB_MST_CRED_STS_15 0x588BEC
+
+#define mmDMA4_QM_ARB_MST_CRED_STS_16 0x588BF0
+
+#define mmDMA4_QM_ARB_MST_CRED_STS_17 0x588BF4
+
+#define mmDMA4_QM_ARB_MST_CRED_STS_18 0x588BF8
+
+#define mmDMA4_QM_ARB_MST_CRED_STS_19 0x588BFC
+
+#define mmDMA4_QM_ARB_MST_CRED_STS_20 0x588C00
+
+#define mmDMA4_QM_ARB_MST_CRED_STS_21 0x588C04
+
+#define mmDMA4_QM_ARB_MST_CRED_STS_22 0x588C08
+
+#define mmDMA4_QM_ARB_MST_CRED_STS_23 0x588C0C
+
+#define mmDMA4_QM_ARB_MST_CRED_STS_24 0x588C10
+
+#define mmDMA4_QM_ARB_MST_CRED_STS_25 0x588C14
+
+#define mmDMA4_QM_ARB_MST_CRED_STS_26 0x588C18
+
+#define mmDMA4_QM_ARB_MST_CRED_STS_27 0x588C1C
+
+#define mmDMA4_QM_ARB_MST_CRED_STS_28 0x588C20
+
+#define mmDMA4_QM_ARB_MST_CRED_STS_29 0x588C24
+
+#define mmDMA4_QM_ARB_MST_CRED_STS_30 0x588C28
+
+#define mmDMA4_QM_ARB_MST_CRED_STS_31 0x588C2C
+
+#define mmDMA4_QM_CGM_CFG 0x588C70
+
+#define mmDMA4_QM_CGM_STS 0x588C74
+
+#define mmDMA4_QM_CGM_CFG1 0x588C78
+
+#define mmDMA4_QM_LOCAL_RANGE_BASE 0x588C80
+
+#define mmDMA4_QM_LOCAL_RANGE_SIZE 0x588C84
+
+#define mmDMA4_QM_CSMR_STRICT_PRIO_CFG 0x588C90
+
+#define mmDMA4_QM_HBW_RD_RATE_LIM_CFG_1 0x588C94
+
+#define mmDMA4_QM_LBW_WR_RATE_LIM_CFG_0 0x588C98
+
+#define mmDMA4_QM_LBW_WR_RATE_LIM_CFG_1 0x588C9C
+
+#define mmDMA4_QM_HBW_RD_RATE_LIM_CFG_0 0x588CA0
+
+#define mmDMA4_QM_GLBL_AXCACHE 0x588CA4
+
+#define mmDMA4_QM_IND_GW_APB_CFG 0x588CB0
+
+#define mmDMA4_QM_IND_GW_APB_WDATA 0x588CB4
+
+#define mmDMA4_QM_IND_GW_APB_RDATA 0x588CB8
+
+#define mmDMA4_QM_IND_GW_APB_STATUS 0x588CBC
+
+#define mmDMA4_QM_GLBL_ERR_ADDR_LO 0x588CD0
+
+#define mmDMA4_QM_GLBL_ERR_ADDR_HI 0x588CD4
+
+#define mmDMA4_QM_GLBL_ERR_WDATA 0x588CD8
+
+#define mmDMA4_QM_GLBL_MEM_INIT_BUSY 0x588D00
+
+#endif /* ASIC_REG_DMA4_QM_REGS_H_ */
diff --git a/drivers/accel/habanalabs/include/gaudi/asic_reg/dma5_core_regs.h b/drivers/accel/habanalabs/include/gaudi/asic_reg/dma5_core_regs.h
new file mode 100644
index 0000000000..6e07c6fb6f
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi/asic_reg/dma5_core_regs.h
@@ -0,0 +1,156 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2016-2018 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ ** DO NOT EDIT BELOW **
+ ************************************/
+
+#ifndef ASIC_REG_DMA5_CORE_REGS_H_
+#define ASIC_REG_DMA5_CORE_REGS_H_
+
+/*
+ *****************************************
+ * DMA5_CORE (Prototype: DMA_CORE)
+ *****************************************
+ */
+
+#define mmDMA5_CORE_CFG_0 0x5A0000
+
+#define mmDMA5_CORE_CFG_1 0x5A0004
+
+#define mmDMA5_CORE_LBW_MAX_OUTSTAND 0x5A0008
+
+#define mmDMA5_CORE_SRC_BASE_LO 0x5A0014
+
+#define mmDMA5_CORE_SRC_BASE_HI 0x5A0018
+
+#define mmDMA5_CORE_DST_BASE_LO 0x5A001C
+
+#define mmDMA5_CORE_DST_BASE_HI 0x5A0020
+
+#define mmDMA5_CORE_SRC_TSIZE_1 0x5A002C
+
+#define mmDMA5_CORE_SRC_STRIDE_1 0x5A0030
+
+#define mmDMA5_CORE_SRC_TSIZE_2 0x5A0034
+
+#define mmDMA5_CORE_SRC_STRIDE_2 0x5A0038
+
+#define mmDMA5_CORE_SRC_TSIZE_3 0x5A003C
+
+#define mmDMA5_CORE_SRC_STRIDE_3 0x5A0040
+
+#define mmDMA5_CORE_SRC_TSIZE_4 0x5A0044
+
+#define mmDMA5_CORE_SRC_STRIDE_4 0x5A0048
+
+#define mmDMA5_CORE_SRC_TSIZE_0 0x5A004C
+
+#define mmDMA5_CORE_DST_TSIZE_1 0x5A0054
+
+#define mmDMA5_CORE_DST_STRIDE_1 0x5A0058
+
+#define mmDMA5_CORE_DST_TSIZE_2 0x5A005C
+
+#define mmDMA5_CORE_DST_STRIDE_2 0x5A0060
+
+#define mmDMA5_CORE_DST_TSIZE_3 0x5A0064
+
+#define mmDMA5_CORE_DST_STRIDE_3 0x5A0068
+
+#define mmDMA5_CORE_DST_TSIZE_4 0x5A006C
+
+#define mmDMA5_CORE_DST_STRIDE_4 0x5A0070
+
+#define mmDMA5_CORE_DST_TSIZE_0 0x5A0074
+
+#define mmDMA5_CORE_COMMIT 0x5A0078
+
+#define mmDMA5_CORE_WR_COMP_WDATA 0x5A007C
+
+#define mmDMA5_CORE_WR_COMP_ADDR_LO 0x5A0080
+
+#define mmDMA5_CORE_WR_COMP_ADDR_HI 0x5A0084
+
+#define mmDMA5_CORE_WR_COMP_AWUSER_31_11 0x5A0088
+
+#define mmDMA5_CORE_TE_NUMROWS 0x5A0094
+
+#define mmDMA5_CORE_PROT 0x5A00B8
+
+#define mmDMA5_CORE_SECURE_PROPS 0x5A00F0
+
+#define mmDMA5_CORE_NON_SECURE_PROPS 0x5A00F4
+
+#define mmDMA5_CORE_RD_MAX_OUTSTAND 0x5A0100
+
+#define mmDMA5_CORE_RD_MAX_SIZE 0x5A0104
+
+#define mmDMA5_CORE_RD_ARCACHE 0x5A0108
+
+#define mmDMA5_CORE_RD_ARUSER_31_11 0x5A0110
+
+#define mmDMA5_CORE_RD_INFLIGHTS 0x5A0114
+
+#define mmDMA5_CORE_WR_MAX_OUTSTAND 0x5A0120
+
+#define mmDMA5_CORE_WR_MAX_AWID 0x5A0124
+
+#define mmDMA5_CORE_WR_AWCACHE 0x5A0128
+
+#define mmDMA5_CORE_WR_AWUSER_31_11 0x5A0130
+
+#define mmDMA5_CORE_WR_INFLIGHTS 0x5A0134
+
+#define mmDMA5_CORE_RD_RATE_LIM_CFG_0 0x5A0150
+
+#define mmDMA5_CORE_RD_RATE_LIM_CFG_1 0x5A0154
+
+#define mmDMA5_CORE_WR_RATE_LIM_CFG_0 0x5A0158
+
+#define mmDMA5_CORE_WR_RATE_LIM_CFG_1 0x5A015C
+
+#define mmDMA5_CORE_ERR_CFG 0x5A0160
+
+#define mmDMA5_CORE_ERR_CAUSE 0x5A0164
+
+#define mmDMA5_CORE_ERRMSG_ADDR_LO 0x5A0170
+
+#define mmDMA5_CORE_ERRMSG_ADDR_HI 0x5A0174
+
+#define mmDMA5_CORE_ERRMSG_WDATA 0x5A0178
+
+#define mmDMA5_CORE_STS0 0x5A0190
+
+#define mmDMA5_CORE_STS1 0x5A0194
+
+#define mmDMA5_CORE_RD_DBGMEM_ADD 0x5A0200
+
+#define mmDMA5_CORE_RD_DBGMEM_DATA_WR 0x5A0204
+
+#define mmDMA5_CORE_RD_DBGMEM_DATA_RD 0x5A0208
+
+#define mmDMA5_CORE_RD_DBGMEM_CTRL 0x5A020C
+
+#define mmDMA5_CORE_RD_DBGMEM_RC 0x5A0210
+
+#define mmDMA5_CORE_DBG_HBW_AXI_AR_CNT 0x5A0220
+
+#define mmDMA5_CORE_DBG_HBW_AXI_AW_CNT 0x5A0224
+
+#define mmDMA5_CORE_DBG_LBW_AXI_AW_CNT 0x5A0228
+
+#define mmDMA5_CORE_DBG_DESC_CNT 0x5A022C
+
+#define mmDMA5_CORE_DBG_STS 0x5A0230
+
+#define mmDMA5_CORE_DBG_RD_DESC_ID 0x5A0234
+
+#define mmDMA5_CORE_DBG_WR_DESC_ID 0x5A0238
+
+#endif /* ASIC_REG_DMA5_CORE_REGS_H_ */
diff --git a/drivers/accel/habanalabs/include/gaudi/asic_reg/dma5_qm_regs.h b/drivers/accel/habanalabs/include/gaudi/asic_reg/dma5_qm_regs.h
new file mode 100644
index 0000000000..0faea21756
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi/asic_reg/dma5_qm_regs.h
@@ -0,0 +1,834 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2016-2018 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ ** DO NOT EDIT BELOW **
+ ************************************/
+
+#ifndef ASIC_REG_DMA5_QM_REGS_H_
+#define ASIC_REG_DMA5_QM_REGS_H_
+
+/*
+ *****************************************
+ * DMA5_QM (Prototype: QMAN)
+ *****************************************
+ */
+
+#define mmDMA5_QM_GLBL_CFG0 0x5A8000
+
+#define mmDMA5_QM_GLBL_CFG1 0x5A8004
+
+#define mmDMA5_QM_GLBL_PROT 0x5A8008
+
+#define mmDMA5_QM_GLBL_ERR_CFG 0x5A800C
+
+#define mmDMA5_QM_GLBL_SECURE_PROPS_0 0x5A8010
+
+#define mmDMA5_QM_GLBL_SECURE_PROPS_1 0x5A8014
+
+#define mmDMA5_QM_GLBL_SECURE_PROPS_2 0x5A8018
+
+#define mmDMA5_QM_GLBL_SECURE_PROPS_3 0x5A801C
+
+#define mmDMA5_QM_GLBL_SECURE_PROPS_4 0x5A8020
+
+#define mmDMA5_QM_GLBL_NON_SECURE_PROPS_0 0x5A8024
+
+#define mmDMA5_QM_GLBL_NON_SECURE_PROPS_1 0x5A8028
+
+#define mmDMA5_QM_GLBL_NON_SECURE_PROPS_2 0x5A802C
+
+#define mmDMA5_QM_GLBL_NON_SECURE_PROPS_3 0x5A8030
+
+#define mmDMA5_QM_GLBL_NON_SECURE_PROPS_4 0x5A8034
+
+#define mmDMA5_QM_GLBL_STS0 0x5A8038
+
+#define mmDMA5_QM_GLBL_STS1_0 0x5A8040
+
+#define mmDMA5_QM_GLBL_STS1_1 0x5A8044
+
+#define mmDMA5_QM_GLBL_STS1_2 0x5A8048
+
+#define mmDMA5_QM_GLBL_STS1_3 0x5A804C
+
+#define mmDMA5_QM_GLBL_STS1_4 0x5A8050
+
+#define mmDMA5_QM_GLBL_MSG_EN_0 0x5A8054
+
+#define mmDMA5_QM_GLBL_MSG_EN_1 0x5A8058
+
+#define mmDMA5_QM_GLBL_MSG_EN_2 0x5A805C
+
+#define mmDMA5_QM_GLBL_MSG_EN_3 0x5A8060
+
+#define mmDMA5_QM_GLBL_MSG_EN_4 0x5A8068
+
+#define mmDMA5_QM_PQ_BASE_LO_0 0x5A8070
+
+#define mmDMA5_QM_PQ_BASE_LO_1 0x5A8074
+
+#define mmDMA5_QM_PQ_BASE_LO_2 0x5A8078
+
+#define mmDMA5_QM_PQ_BASE_LO_3 0x5A807C
+
+#define mmDMA5_QM_PQ_BASE_HI_0 0x5A8080
+
+#define mmDMA5_QM_PQ_BASE_HI_1 0x5A8084
+
+#define mmDMA5_QM_PQ_BASE_HI_2 0x5A8088
+
+#define mmDMA5_QM_PQ_BASE_HI_3 0x5A808C
+
+#define mmDMA5_QM_PQ_SIZE_0 0x5A8090
+
+#define mmDMA5_QM_PQ_SIZE_1 0x5A8094
+
+#define mmDMA5_QM_PQ_SIZE_2 0x5A8098
+
+#define mmDMA5_QM_PQ_SIZE_3 0x5A809C
+
+#define mmDMA5_QM_PQ_PI_0 0x5A80A0
+
+#define mmDMA5_QM_PQ_PI_1 0x5A80A4
+
+#define mmDMA5_QM_PQ_PI_2 0x5A80A8
+
+#define mmDMA5_QM_PQ_PI_3 0x5A80AC
+
+#define mmDMA5_QM_PQ_CI_0 0x5A80B0
+
+#define mmDMA5_QM_PQ_CI_1 0x5A80B4
+
+#define mmDMA5_QM_PQ_CI_2 0x5A80B8
+
+#define mmDMA5_QM_PQ_CI_3 0x5A80BC
+
+#define mmDMA5_QM_PQ_CFG0_0 0x5A80C0
+
+#define mmDMA5_QM_PQ_CFG0_1 0x5A80C4
+
+#define mmDMA5_QM_PQ_CFG0_2 0x5A80C8
+
+#define mmDMA5_QM_PQ_CFG0_3 0x5A80CC
+
+#define mmDMA5_QM_PQ_CFG1_0 0x5A80D0
+
+#define mmDMA5_QM_PQ_CFG1_1 0x5A80D4
+
+#define mmDMA5_QM_PQ_CFG1_2 0x5A80D8
+
+#define mmDMA5_QM_PQ_CFG1_3 0x5A80DC
+
+#define mmDMA5_QM_PQ_ARUSER_31_11_0 0x5A80E0
+
+#define mmDMA5_QM_PQ_ARUSER_31_11_1 0x5A80E4
+
+#define mmDMA5_QM_PQ_ARUSER_31_11_2 0x5A80E8
+
+#define mmDMA5_QM_PQ_ARUSER_31_11_3 0x5A80EC
+
+#define mmDMA5_QM_PQ_STS0_0 0x5A80F0
+
+#define mmDMA5_QM_PQ_STS0_1 0x5A80F4
+
+#define mmDMA5_QM_PQ_STS0_2 0x5A80F8
+
+#define mmDMA5_QM_PQ_STS0_3 0x5A80FC
+
+#define mmDMA5_QM_PQ_STS1_0 0x5A8100
+
+#define mmDMA5_QM_PQ_STS1_1 0x5A8104
+
+#define mmDMA5_QM_PQ_STS1_2 0x5A8108
+
+#define mmDMA5_QM_PQ_STS1_3 0x5A810C
+
+#define mmDMA5_QM_CQ_CFG0_0 0x5A8110
+
+#define mmDMA5_QM_CQ_CFG0_1 0x5A8114
+
+#define mmDMA5_QM_CQ_CFG0_2 0x5A8118
+
+#define mmDMA5_QM_CQ_CFG0_3 0x5A811C
+
+#define mmDMA5_QM_CQ_CFG0_4 0x5A8120
+
+#define mmDMA5_QM_CQ_CFG1_0 0x5A8124
+
+#define mmDMA5_QM_CQ_CFG1_1 0x5A8128
+
+#define mmDMA5_QM_CQ_CFG1_2 0x5A812C
+
+#define mmDMA5_QM_CQ_CFG1_3 0x5A8130
+
+#define mmDMA5_QM_CQ_CFG1_4 0x5A8134
+
+#define mmDMA5_QM_CQ_ARUSER_31_11_0 0x5A8138
+
+#define mmDMA5_QM_CQ_ARUSER_31_11_1 0x5A813C
+
+#define mmDMA5_QM_CQ_ARUSER_31_11_2 0x5A8140
+
+#define mmDMA5_QM_CQ_ARUSER_31_11_3 0x5A8144
+
+#define mmDMA5_QM_CQ_ARUSER_31_11_4 0x5A8148
+
+#define mmDMA5_QM_CQ_STS0_0 0x5A814C
+
+#define mmDMA5_QM_CQ_STS0_1 0x5A8150
+
+#define mmDMA5_QM_CQ_STS0_2 0x5A8154
+
+#define mmDMA5_QM_CQ_STS0_3 0x5A8158
+
+#define mmDMA5_QM_CQ_STS0_4 0x5A815C
+
+#define mmDMA5_QM_CQ_STS1_0 0x5A8160
+
+#define mmDMA5_QM_CQ_STS1_1 0x5A8164
+
+#define mmDMA5_QM_CQ_STS1_2 0x5A8168
+
+#define mmDMA5_QM_CQ_STS1_3 0x5A816C
+
+#define mmDMA5_QM_CQ_STS1_4 0x5A8170
+
+#define mmDMA5_QM_CQ_PTR_LO_0 0x5A8174
+
+#define mmDMA5_QM_CQ_PTR_HI_0 0x5A8178
+
+#define mmDMA5_QM_CQ_TSIZE_0 0x5A817C
+
+#define mmDMA5_QM_CQ_CTL_0 0x5A8180
+
+#define mmDMA5_QM_CQ_PTR_LO_1 0x5A8184
+
+#define mmDMA5_QM_CQ_PTR_HI_1 0x5A8188
+
+#define mmDMA5_QM_CQ_TSIZE_1 0x5A818C
+
+#define mmDMA5_QM_CQ_CTL_1 0x5A8190
+
+#define mmDMA5_QM_CQ_PTR_LO_2 0x5A8194
+
+#define mmDMA5_QM_CQ_PTR_HI_2 0x5A8198
+
+#define mmDMA5_QM_CQ_TSIZE_2 0x5A819C
+
+#define mmDMA5_QM_CQ_CTL_2 0x5A81A0
+
+#define mmDMA5_QM_CQ_PTR_LO_3 0x5A81A4
+
+#define mmDMA5_QM_CQ_PTR_HI_3 0x5A81A8
+
+#define mmDMA5_QM_CQ_TSIZE_3 0x5A81AC
+
+#define mmDMA5_QM_CQ_CTL_3 0x5A81B0
+
+#define mmDMA5_QM_CQ_PTR_LO_4 0x5A81B4
+
+#define mmDMA5_QM_CQ_PTR_HI_4 0x5A81B8
+
+#define mmDMA5_QM_CQ_TSIZE_4 0x5A81BC
+
+#define mmDMA5_QM_CQ_CTL_4 0x5A81C0
+
+#define mmDMA5_QM_CQ_PTR_LO_STS_0 0x5A81C4
+
+#define mmDMA5_QM_CQ_PTR_LO_STS_1 0x5A81C8
+
+#define mmDMA5_QM_CQ_PTR_LO_STS_2 0x5A81CC
+
+#define mmDMA5_QM_CQ_PTR_LO_STS_3 0x5A81D0
+
+#define mmDMA5_QM_CQ_PTR_LO_STS_4 0x5A81D4
+
+#define mmDMA5_QM_CQ_PTR_HI_STS_0 0x5A81D8
+
+#define mmDMA5_QM_CQ_PTR_HI_STS_1 0x5A81DC
+
+#define mmDMA5_QM_CQ_PTR_HI_STS_2 0x5A81E0
+
+#define mmDMA5_QM_CQ_PTR_HI_STS_3 0x5A81E4
+
+#define mmDMA5_QM_CQ_PTR_HI_STS_4 0x5A81E8
+
+#define mmDMA5_QM_CQ_TSIZE_STS_0 0x5A81EC
+
+#define mmDMA5_QM_CQ_TSIZE_STS_1 0x5A81F0
+
+#define mmDMA5_QM_CQ_TSIZE_STS_2 0x5A81F4
+
+#define mmDMA5_QM_CQ_TSIZE_STS_3 0x5A81F8
+
+#define mmDMA5_QM_CQ_TSIZE_STS_4 0x5A81FC
+
+#define mmDMA5_QM_CQ_CTL_STS_0 0x5A8200
+
+#define mmDMA5_QM_CQ_CTL_STS_1 0x5A8204
+
+#define mmDMA5_QM_CQ_CTL_STS_2 0x5A8208
+
+#define mmDMA5_QM_CQ_CTL_STS_3 0x5A820C
+
+#define mmDMA5_QM_CQ_CTL_STS_4 0x5A8210
+
+#define mmDMA5_QM_CQ_IFIFO_CNT_0 0x5A8214
+
+#define mmDMA5_QM_CQ_IFIFO_CNT_1 0x5A8218
+
+#define mmDMA5_QM_CQ_IFIFO_CNT_2 0x5A821C
+
+#define mmDMA5_QM_CQ_IFIFO_CNT_3 0x5A8220
+
+#define mmDMA5_QM_CQ_IFIFO_CNT_4 0x5A8224
+
+#define mmDMA5_QM_CP_MSG_BASE0_ADDR_LO_0 0x5A8228
+
+#define mmDMA5_QM_CP_MSG_BASE0_ADDR_LO_1 0x5A822C
+
+#define mmDMA5_QM_CP_MSG_BASE0_ADDR_LO_2 0x5A8230
+
+#define mmDMA5_QM_CP_MSG_BASE0_ADDR_LO_3 0x5A8234
+
+#define mmDMA5_QM_CP_MSG_BASE0_ADDR_LO_4 0x5A8238
+
+#define mmDMA5_QM_CP_MSG_BASE0_ADDR_HI_0 0x5A823C
+
+#define mmDMA5_QM_CP_MSG_BASE0_ADDR_HI_1 0x5A8240
+
+#define mmDMA5_QM_CP_MSG_BASE0_ADDR_HI_2 0x5A8244
+
+#define mmDMA5_QM_CP_MSG_BASE0_ADDR_HI_3 0x5A8248
+
+#define mmDMA5_QM_CP_MSG_BASE0_ADDR_HI_4 0x5A824C
+
+#define mmDMA5_QM_CP_MSG_BASE1_ADDR_LO_0 0x5A8250
+
+#define mmDMA5_QM_CP_MSG_BASE1_ADDR_LO_1 0x5A8254
+
+#define mmDMA5_QM_CP_MSG_BASE1_ADDR_LO_2 0x5A8258
+
+#define mmDMA5_QM_CP_MSG_BASE1_ADDR_LO_3 0x5A825C
+
+#define mmDMA5_QM_CP_MSG_BASE1_ADDR_LO_4 0x5A8260
+
+#define mmDMA5_QM_CP_MSG_BASE1_ADDR_HI_0 0x5A8264
+
+#define mmDMA5_QM_CP_MSG_BASE1_ADDR_HI_1 0x5A8268
+
+#define mmDMA5_QM_CP_MSG_BASE1_ADDR_HI_2 0x5A826C
+
+#define mmDMA5_QM_CP_MSG_BASE1_ADDR_HI_3 0x5A8270
+
+#define mmDMA5_QM_CP_MSG_BASE1_ADDR_HI_4 0x5A8274
+
+#define mmDMA5_QM_CP_MSG_BASE2_ADDR_LO_0 0x5A8278
+
+#define mmDMA5_QM_CP_MSG_BASE2_ADDR_LO_1 0x5A827C
+
+#define mmDMA5_QM_CP_MSG_BASE2_ADDR_LO_2 0x5A8280
+
+#define mmDMA5_QM_CP_MSG_BASE2_ADDR_LO_3 0x5A8284
+
+#define mmDMA5_QM_CP_MSG_BASE2_ADDR_LO_4 0x5A8288
+
+#define mmDMA5_QM_CP_MSG_BASE2_ADDR_HI_0 0x5A828C
+
+#define mmDMA5_QM_CP_MSG_BASE2_ADDR_HI_1 0x5A8290
+
+#define mmDMA5_QM_CP_MSG_BASE2_ADDR_HI_2 0x5A8294
+
+#define mmDMA5_QM_CP_MSG_BASE2_ADDR_HI_3 0x5A8298
+
+#define mmDMA5_QM_CP_MSG_BASE2_ADDR_HI_4 0x5A829C
+
+#define mmDMA5_QM_CP_MSG_BASE3_ADDR_LO_0 0x5A82A0
+
+#define mmDMA5_QM_CP_MSG_BASE3_ADDR_LO_1 0x5A82A4
+
+#define mmDMA5_QM_CP_MSG_BASE3_ADDR_LO_2 0x5A82A8
+
+#define mmDMA5_QM_CP_MSG_BASE3_ADDR_LO_3 0x5A82AC
+
+#define mmDMA5_QM_CP_MSG_BASE3_ADDR_LO_4 0x5A82B0
+
+#define mmDMA5_QM_CP_MSG_BASE3_ADDR_HI_0 0x5A82B4
+
+#define mmDMA5_QM_CP_MSG_BASE3_ADDR_HI_1 0x5A82B8
+
+#define mmDMA5_QM_CP_MSG_BASE3_ADDR_HI_2 0x5A82BC
+
+#define mmDMA5_QM_CP_MSG_BASE3_ADDR_HI_3 0x5A82C0
+
+#define mmDMA5_QM_CP_MSG_BASE3_ADDR_HI_4 0x5A82C4
+
+#define mmDMA5_QM_CP_LDMA_TSIZE_OFFSET_0 0x5A82C8
+
+#define mmDMA5_QM_CP_LDMA_TSIZE_OFFSET_1 0x5A82CC
+
+#define mmDMA5_QM_CP_LDMA_TSIZE_OFFSET_2 0x5A82D0
+
+#define mmDMA5_QM_CP_LDMA_TSIZE_OFFSET_3 0x5A82D4
+
+#define mmDMA5_QM_CP_LDMA_TSIZE_OFFSET_4 0x5A82D8
+
+#define mmDMA5_QM_CP_LDMA_SRC_BASE_LO_OFFSET_0 0x5A82E0
+
+#define mmDMA5_QM_CP_LDMA_SRC_BASE_LO_OFFSET_1 0x5A82E4
+
+#define mmDMA5_QM_CP_LDMA_SRC_BASE_LO_OFFSET_2 0x5A82E8
+
+#define mmDMA5_QM_CP_LDMA_SRC_BASE_LO_OFFSET_3 0x5A82EC
+
+#define mmDMA5_QM_CP_LDMA_SRC_BASE_LO_OFFSET_4 0x5A82F0
+
+#define mmDMA5_QM_CP_LDMA_DST_BASE_LO_OFFSET_0 0x5A82F4
+
+#define mmDMA5_QM_CP_LDMA_DST_BASE_LO_OFFSET_1 0x5A82F8
+
+#define mmDMA5_QM_CP_LDMA_DST_BASE_LO_OFFSET_2 0x5A82FC
+
+#define mmDMA5_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 0x5A8300
+
+#define mmDMA5_QM_CP_LDMA_DST_BASE_LO_OFFSET_4 0x5A8304
+
+#define mmDMA5_QM_CP_FENCE0_RDATA_0 0x5A8308
+
+#define mmDMA5_QM_CP_FENCE0_RDATA_1 0x5A830C
+
+#define mmDMA5_QM_CP_FENCE0_RDATA_2 0x5A8310
+
+#define mmDMA5_QM_CP_FENCE0_RDATA_3 0x5A8314
+
+#define mmDMA5_QM_CP_FENCE0_RDATA_4 0x5A8318
+
+#define mmDMA5_QM_CP_FENCE1_RDATA_0 0x5A831C
+
+#define mmDMA5_QM_CP_FENCE1_RDATA_1 0x5A8320
+
+#define mmDMA5_QM_CP_FENCE1_RDATA_2 0x5A8324
+
+#define mmDMA5_QM_CP_FENCE1_RDATA_3 0x5A8328
+
+#define mmDMA5_QM_CP_FENCE1_RDATA_4 0x5A832C
+
+#define mmDMA5_QM_CP_FENCE2_RDATA_0 0x5A8330
+
+#define mmDMA5_QM_CP_FENCE2_RDATA_1 0x5A8334
+
+#define mmDMA5_QM_CP_FENCE2_RDATA_2 0x5A8338
+
+#define mmDMA5_QM_CP_FENCE2_RDATA_3 0x5A833C
+
+#define mmDMA5_QM_CP_FENCE2_RDATA_4 0x5A8340
+
+#define mmDMA5_QM_CP_FENCE3_RDATA_0 0x5A8344
+
+#define mmDMA5_QM_CP_FENCE3_RDATA_1 0x5A8348
+
+#define mmDMA5_QM_CP_FENCE3_RDATA_2 0x5A834C
+
+#define mmDMA5_QM_CP_FENCE3_RDATA_3 0x5A8350
+
+#define mmDMA5_QM_CP_FENCE3_RDATA_4 0x5A8354
+
+#define mmDMA5_QM_CP_FENCE0_CNT_0 0x5A8358
+
+#define mmDMA5_QM_CP_FENCE0_CNT_1 0x5A835C
+
+#define mmDMA5_QM_CP_FENCE0_CNT_2 0x5A8360
+
+#define mmDMA5_QM_CP_FENCE0_CNT_3 0x5A8364
+
+#define mmDMA5_QM_CP_FENCE0_CNT_4 0x5A8368
+
+#define mmDMA5_QM_CP_FENCE1_CNT_0 0x5A836C
+
+#define mmDMA5_QM_CP_FENCE1_CNT_1 0x5A8370
+
+#define mmDMA5_QM_CP_FENCE1_CNT_2 0x5A8374
+
+#define mmDMA5_QM_CP_FENCE1_CNT_3 0x5A8378
+
+#define mmDMA5_QM_CP_FENCE1_CNT_4 0x5A837C
+
+#define mmDMA5_QM_CP_FENCE2_CNT_0 0x5A8380
+
+#define mmDMA5_QM_CP_FENCE2_CNT_1 0x5A8384
+
+#define mmDMA5_QM_CP_FENCE2_CNT_2 0x5A8388
+
+#define mmDMA5_QM_CP_FENCE2_CNT_3 0x5A838C
+
+#define mmDMA5_QM_CP_FENCE2_CNT_4 0x5A8390
+
+#define mmDMA5_QM_CP_FENCE3_CNT_0 0x5A8394
+
+#define mmDMA5_QM_CP_FENCE3_CNT_1 0x5A8398
+
+#define mmDMA5_QM_CP_FENCE3_CNT_2 0x5A839C
+
+#define mmDMA5_QM_CP_FENCE3_CNT_3 0x5A83A0
+
+#define mmDMA5_QM_CP_FENCE3_CNT_4 0x5A83A4
+
+#define mmDMA5_QM_CP_STS_0 0x5A83A8
+
+#define mmDMA5_QM_CP_STS_1 0x5A83AC
+
+#define mmDMA5_QM_CP_STS_2 0x5A83B0
+
+#define mmDMA5_QM_CP_STS_3 0x5A83B4
+
+#define mmDMA5_QM_CP_STS_4 0x5A83B8
+
+#define mmDMA5_QM_CP_CURRENT_INST_LO_0 0x5A83BC
+
+#define mmDMA5_QM_CP_CURRENT_INST_LO_1 0x5A83C0
+
+#define mmDMA5_QM_CP_CURRENT_INST_LO_2 0x5A83C4
+
+#define mmDMA5_QM_CP_CURRENT_INST_LO_3 0x5A83C8
+
+#define mmDMA5_QM_CP_CURRENT_INST_LO_4 0x5A83CC
+
+#define mmDMA5_QM_CP_CURRENT_INST_HI_0 0x5A83D0
+
+#define mmDMA5_QM_CP_CURRENT_INST_HI_1 0x5A83D4
+
+#define mmDMA5_QM_CP_CURRENT_INST_HI_2 0x5A83D8
+
+#define mmDMA5_QM_CP_CURRENT_INST_HI_3 0x5A83DC
+
+#define mmDMA5_QM_CP_CURRENT_INST_HI_4 0x5A83E0
+
+#define mmDMA5_QM_CP_BARRIER_CFG_0 0x5A83F4
+
+#define mmDMA5_QM_CP_BARRIER_CFG_1 0x5A83F8
+
+#define mmDMA5_QM_CP_BARRIER_CFG_2 0x5A83FC
+
+#define mmDMA5_QM_CP_BARRIER_CFG_3 0x5A8400
+
+#define mmDMA5_QM_CP_BARRIER_CFG_4 0x5A8404
+
+#define mmDMA5_QM_CP_DBG_0_0 0x5A8408
+
+#define mmDMA5_QM_CP_DBG_0_1 0x5A840C
+
+#define mmDMA5_QM_CP_DBG_0_2 0x5A8410
+
+#define mmDMA5_QM_CP_DBG_0_3 0x5A8414
+
+#define mmDMA5_QM_CP_DBG_0_4 0x5A8418
+
+#define mmDMA5_QM_CP_ARUSER_31_11_0 0x5A841C
+
+#define mmDMA5_QM_CP_ARUSER_31_11_1 0x5A8420
+
+#define mmDMA5_QM_CP_ARUSER_31_11_2 0x5A8424
+
+#define mmDMA5_QM_CP_ARUSER_31_11_3 0x5A8428
+
+#define mmDMA5_QM_CP_ARUSER_31_11_4 0x5A842C
+
+#define mmDMA5_QM_CP_AWUSER_31_11_0 0x5A8430
+
+#define mmDMA5_QM_CP_AWUSER_31_11_1 0x5A8434
+
+#define mmDMA5_QM_CP_AWUSER_31_11_2 0x5A8438
+
+#define mmDMA5_QM_CP_AWUSER_31_11_3 0x5A843C
+
+#define mmDMA5_QM_CP_AWUSER_31_11_4 0x5A8440
+
+#define mmDMA5_QM_ARB_CFG_0 0x5A8A00
+
+#define mmDMA5_QM_ARB_CHOISE_Q_PUSH 0x5A8A04
+
+#define mmDMA5_QM_ARB_WRR_WEIGHT_0 0x5A8A08
+
+#define mmDMA5_QM_ARB_WRR_WEIGHT_1 0x5A8A0C
+
+#define mmDMA5_QM_ARB_WRR_WEIGHT_2 0x5A8A10
+
+#define mmDMA5_QM_ARB_WRR_WEIGHT_3 0x5A8A14
+
+#define mmDMA5_QM_ARB_CFG_1 0x5A8A18
+
+#define mmDMA5_QM_ARB_MST_AVAIL_CRED_0 0x5A8A20
+
+#define mmDMA5_QM_ARB_MST_AVAIL_CRED_1 0x5A8A24
+
+#define mmDMA5_QM_ARB_MST_AVAIL_CRED_2 0x5A8A28
+
+#define mmDMA5_QM_ARB_MST_AVAIL_CRED_3 0x5A8A2C
+
+#define mmDMA5_QM_ARB_MST_AVAIL_CRED_4 0x5A8A30
+
+#define mmDMA5_QM_ARB_MST_AVAIL_CRED_5 0x5A8A34
+
+#define mmDMA5_QM_ARB_MST_AVAIL_CRED_6 0x5A8A38
+
+#define mmDMA5_QM_ARB_MST_AVAIL_CRED_7 0x5A8A3C
+
+#define mmDMA5_QM_ARB_MST_AVAIL_CRED_8 0x5A8A40
+
+#define mmDMA5_QM_ARB_MST_AVAIL_CRED_9 0x5A8A44
+
+#define mmDMA5_QM_ARB_MST_AVAIL_CRED_10 0x5A8A48
+
+#define mmDMA5_QM_ARB_MST_AVAIL_CRED_11 0x5A8A4C
+
+#define mmDMA5_QM_ARB_MST_AVAIL_CRED_12 0x5A8A50
+
+#define mmDMA5_QM_ARB_MST_AVAIL_CRED_13 0x5A8A54
+
+#define mmDMA5_QM_ARB_MST_AVAIL_CRED_14 0x5A8A58
+
+#define mmDMA5_QM_ARB_MST_AVAIL_CRED_15 0x5A8A5C
+
+#define mmDMA5_QM_ARB_MST_AVAIL_CRED_16 0x5A8A60
+
+#define mmDMA5_QM_ARB_MST_AVAIL_CRED_17 0x5A8A64
+
+#define mmDMA5_QM_ARB_MST_AVAIL_CRED_18 0x5A8A68
+
+#define mmDMA5_QM_ARB_MST_AVAIL_CRED_19 0x5A8A6C
+
+#define mmDMA5_QM_ARB_MST_AVAIL_CRED_20 0x5A8A70
+
+#define mmDMA5_QM_ARB_MST_AVAIL_CRED_21 0x5A8A74
+
+#define mmDMA5_QM_ARB_MST_AVAIL_CRED_22 0x5A8A78
+
+#define mmDMA5_QM_ARB_MST_AVAIL_CRED_23 0x5A8A7C
+
+#define mmDMA5_QM_ARB_MST_AVAIL_CRED_24 0x5A8A80
+
+#define mmDMA5_QM_ARB_MST_AVAIL_CRED_25 0x5A8A84
+
+#define mmDMA5_QM_ARB_MST_AVAIL_CRED_26 0x5A8A88
+
+#define mmDMA5_QM_ARB_MST_AVAIL_CRED_27 0x5A8A8C
+
+#define mmDMA5_QM_ARB_MST_AVAIL_CRED_28 0x5A8A90
+
+#define mmDMA5_QM_ARB_MST_AVAIL_CRED_29 0x5A8A94
+
+#define mmDMA5_QM_ARB_MST_AVAIL_CRED_30 0x5A8A98
+
+#define mmDMA5_QM_ARB_MST_AVAIL_CRED_31 0x5A8A9C
+
+#define mmDMA5_QM_ARB_MST_CRED_INC 0x5A8AA0
+
+#define mmDMA5_QM_ARB_MST_CHOISE_PUSH_OFST_0 0x5A8AA4
+
+#define mmDMA5_QM_ARB_MST_CHOISE_PUSH_OFST_1 0x5A8AA8
+
+#define mmDMA5_QM_ARB_MST_CHOISE_PUSH_OFST_2 0x5A8AAC
+
+#define mmDMA5_QM_ARB_MST_CHOISE_PUSH_OFST_3 0x5A8AB0
+
+#define mmDMA5_QM_ARB_MST_CHOISE_PUSH_OFST_4 0x5A8AB4
+
+#define mmDMA5_QM_ARB_MST_CHOISE_PUSH_OFST_5 0x5A8AB8
+
+#define mmDMA5_QM_ARB_MST_CHOISE_PUSH_OFST_6 0x5A8ABC
+
+#define mmDMA5_QM_ARB_MST_CHOISE_PUSH_OFST_7 0x5A8AC0
+
+#define mmDMA5_QM_ARB_MST_CHOISE_PUSH_OFST_8 0x5A8AC4
+
+#define mmDMA5_QM_ARB_MST_CHOISE_PUSH_OFST_9 0x5A8AC8
+
+#define mmDMA5_QM_ARB_MST_CHOISE_PUSH_OFST_10 0x5A8ACC
+
+#define mmDMA5_QM_ARB_MST_CHOISE_PUSH_OFST_11 0x5A8AD0
+
+#define mmDMA5_QM_ARB_MST_CHOISE_PUSH_OFST_12 0x5A8AD4
+
+#define mmDMA5_QM_ARB_MST_CHOISE_PUSH_OFST_13 0x5A8AD8
+
+#define mmDMA5_QM_ARB_MST_CHOISE_PUSH_OFST_14 0x5A8ADC
+
+#define mmDMA5_QM_ARB_MST_CHOISE_PUSH_OFST_15 0x5A8AE0
+
+#define mmDMA5_QM_ARB_MST_CHOISE_PUSH_OFST_16 0x5A8AE4
+
+#define mmDMA5_QM_ARB_MST_CHOISE_PUSH_OFST_17 0x5A8AE8
+
+#define mmDMA5_QM_ARB_MST_CHOISE_PUSH_OFST_18 0x5A8AEC
+
+#define mmDMA5_QM_ARB_MST_CHOISE_PUSH_OFST_19 0x5A8AF0
+
+#define mmDMA5_QM_ARB_MST_CHOISE_PUSH_OFST_20 0x5A8AF4
+
+#define mmDMA5_QM_ARB_MST_CHOISE_PUSH_OFST_21 0x5A8AF8
+
+#define mmDMA5_QM_ARB_MST_CHOISE_PUSH_OFST_22 0x5A8AFC
+
+#define mmDMA5_QM_ARB_MST_CHOISE_PUSH_OFST_23 0x5A8B00
+
+#define mmDMA5_QM_ARB_MST_CHOISE_PUSH_OFST_24 0x5A8B04
+
+#define mmDMA5_QM_ARB_MST_CHOISE_PUSH_OFST_25 0x5A8B08
+
+#define mmDMA5_QM_ARB_MST_CHOISE_PUSH_OFST_26 0x5A8B0C
+
+#define mmDMA5_QM_ARB_MST_CHOISE_PUSH_OFST_27 0x5A8B10
+
+#define mmDMA5_QM_ARB_MST_CHOISE_PUSH_OFST_28 0x5A8B14
+
+#define mmDMA5_QM_ARB_MST_CHOISE_PUSH_OFST_29 0x5A8B18
+
+#define mmDMA5_QM_ARB_MST_CHOISE_PUSH_OFST_30 0x5A8B1C
+
+#define mmDMA5_QM_ARB_MST_CHOISE_PUSH_OFST_31 0x5A8B20
+
+#define mmDMA5_QM_ARB_SLV_MASTER_INC_CRED_OFST 0x5A8B28
+
+#define mmDMA5_QM_ARB_MST_SLAVE_EN 0x5A8B2C
+
+#define mmDMA5_QM_ARB_MST_QUIET_PER 0x5A8B34
+
+#define mmDMA5_QM_ARB_SLV_CHOISE_WDT 0x5A8B38
+
+#define mmDMA5_QM_ARB_SLV_ID 0x5A8B3C
+
+#define mmDMA5_QM_ARB_MSG_MAX_INFLIGHT 0x5A8B44
+
+#define mmDMA5_QM_ARB_MSG_AWUSER_31_11 0x5A8B48
+
+#define mmDMA5_QM_ARB_MSG_AWUSER_SEC_PROP 0x5A8B4C
+
+#define mmDMA5_QM_ARB_MSG_AWUSER_NON_SEC_PROP 0x5A8B50
+
+#define mmDMA5_QM_ARB_BASE_LO 0x5A8B54
+
+#define mmDMA5_QM_ARB_BASE_HI 0x5A8B58
+
+#define mmDMA5_QM_ARB_STATE_STS 0x5A8B80
+
+#define mmDMA5_QM_ARB_CHOISE_FULLNESS_STS 0x5A8B84
+
+#define mmDMA5_QM_ARB_MSG_STS 0x5A8B88
+
+#define mmDMA5_QM_ARB_SLV_CHOISE_Q_HEAD 0x5A8B8C
+
+#define mmDMA5_QM_ARB_ERR_CAUSE 0x5A8B9C
+
+#define mmDMA5_QM_ARB_ERR_MSG_EN 0x5A8BA0
+
+#define mmDMA5_QM_ARB_ERR_STS_DRP 0x5A8BA8
+
+#define mmDMA5_QM_ARB_MST_CRED_STS_0 0x5A8BB0
+
+#define mmDMA5_QM_ARB_MST_CRED_STS_1 0x5A8BB4
+
+#define mmDMA5_QM_ARB_MST_CRED_STS_2 0x5A8BB8
+
+#define mmDMA5_QM_ARB_MST_CRED_STS_3 0x5A8BBC
+
+#define mmDMA5_QM_ARB_MST_CRED_STS_4 0x5A8BC0
+
+#define mmDMA5_QM_ARB_MST_CRED_STS_5 0x5A8BC4
+
+#define mmDMA5_QM_ARB_MST_CRED_STS_6 0x5A8BC8
+
+#define mmDMA5_QM_ARB_MST_CRED_STS_7 0x5A8BCC
+
+#define mmDMA5_QM_ARB_MST_CRED_STS_8 0x5A8BD0
+
+#define mmDMA5_QM_ARB_MST_CRED_STS_9 0x5A8BD4
+
+#define mmDMA5_QM_ARB_MST_CRED_STS_10 0x5A8BD8
+
+#define mmDMA5_QM_ARB_MST_CRED_STS_11 0x5A8BDC
+
+#define mmDMA5_QM_ARB_MST_CRED_STS_12 0x5A8BE0
+
+#define mmDMA5_QM_ARB_MST_CRED_STS_13 0x5A8BE4
+
+#define mmDMA5_QM_ARB_MST_CRED_STS_14 0x5A8BE8
+
+#define mmDMA5_QM_ARB_MST_CRED_STS_15 0x5A8BEC
+
+#define mmDMA5_QM_ARB_MST_CRED_STS_16 0x5A8BF0
+
+#define mmDMA5_QM_ARB_MST_CRED_STS_17 0x5A8BF4
+
+#define mmDMA5_QM_ARB_MST_CRED_STS_18 0x5A8BF8
+
+#define mmDMA5_QM_ARB_MST_CRED_STS_19 0x5A8BFC
+
+#define mmDMA5_QM_ARB_MST_CRED_STS_20 0x5A8C00
+
+#define mmDMA5_QM_ARB_MST_CRED_STS_21 0x5A8C04
+
+#define mmDMA5_QM_ARB_MST_CRED_STS_22 0x5A8C08
+
+#define mmDMA5_QM_ARB_MST_CRED_STS_23 0x5A8C0C
+
+#define mmDMA5_QM_ARB_MST_CRED_STS_24 0x5A8C10
+
+#define mmDMA5_QM_ARB_MST_CRED_STS_25 0x5A8C14
+
+#define mmDMA5_QM_ARB_MST_CRED_STS_26 0x5A8C18
+
+#define mmDMA5_QM_ARB_MST_CRED_STS_27 0x5A8C1C
+
+#define mmDMA5_QM_ARB_MST_CRED_STS_28 0x5A8C20
+
+#define mmDMA5_QM_ARB_MST_CRED_STS_29 0x5A8C24
+
+#define mmDMA5_QM_ARB_MST_CRED_STS_30 0x5A8C28
+
+#define mmDMA5_QM_ARB_MST_CRED_STS_31 0x5A8C2C
+
+#define mmDMA5_QM_CGM_CFG 0x5A8C70
+
+#define mmDMA5_QM_CGM_STS 0x5A8C74
+
+#define mmDMA5_QM_CGM_CFG1 0x5A8C78
+
+#define mmDMA5_QM_LOCAL_RANGE_BASE 0x5A8C80
+
+#define mmDMA5_QM_LOCAL_RANGE_SIZE 0x5A8C84
+
+#define mmDMA5_QM_CSMR_STRICT_PRIO_CFG 0x5A8C90
+
+#define mmDMA5_QM_HBW_RD_RATE_LIM_CFG_1 0x5A8C94
+
+#define mmDMA5_QM_LBW_WR_RATE_LIM_CFG_0 0x5A8C98
+
+#define mmDMA5_QM_LBW_WR_RATE_LIM_CFG_1 0x5A8C9C
+
+#define mmDMA5_QM_HBW_RD_RATE_LIM_CFG_0 0x5A8CA0
+
+#define mmDMA5_QM_GLBL_AXCACHE 0x5A8CA4
+
+#define mmDMA5_QM_IND_GW_APB_CFG 0x5A8CB0
+
+#define mmDMA5_QM_IND_GW_APB_WDATA 0x5A8CB4
+
+#define mmDMA5_QM_IND_GW_APB_RDATA 0x5A8CB8
+
+#define mmDMA5_QM_IND_GW_APB_STATUS 0x5A8CBC
+
+#define mmDMA5_QM_GLBL_ERR_ADDR_LO 0x5A8CD0
+
+#define mmDMA5_QM_GLBL_ERR_ADDR_HI 0x5A8CD4
+
+#define mmDMA5_QM_GLBL_ERR_WDATA 0x5A8CD8
+
+#define mmDMA5_QM_GLBL_MEM_INIT_BUSY 0x5A8D00
+
+#endif /* ASIC_REG_DMA5_QM_REGS_H_ */
diff --git a/drivers/accel/habanalabs/include/gaudi/asic_reg/dma6_core_regs.h b/drivers/accel/habanalabs/include/gaudi/asic_reg/dma6_core_regs.h
new file mode 100644
index 0000000000..4962c13e2e
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi/asic_reg/dma6_core_regs.h
@@ -0,0 +1,156 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2016-2018 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ ** DO NOT EDIT BELOW **
+ ************************************/
+
+#ifndef ASIC_REG_DMA6_CORE_REGS_H_
+#define ASIC_REG_DMA6_CORE_REGS_H_
+
+/*
+ *****************************************
+ * DMA6_CORE (Prototype: DMA_CORE)
+ *****************************************
+ */
+
+#define mmDMA6_CORE_CFG_0 0x5C0000
+
+#define mmDMA6_CORE_CFG_1 0x5C0004
+
+#define mmDMA6_CORE_LBW_MAX_OUTSTAND 0x5C0008
+
+#define mmDMA6_CORE_SRC_BASE_LO 0x5C0014
+
+#define mmDMA6_CORE_SRC_BASE_HI 0x5C0018
+
+#define mmDMA6_CORE_DST_BASE_LO 0x5C001C
+
+#define mmDMA6_CORE_DST_BASE_HI 0x5C0020
+
+#define mmDMA6_CORE_SRC_TSIZE_1 0x5C002C
+
+#define mmDMA6_CORE_SRC_STRIDE_1 0x5C0030
+
+#define mmDMA6_CORE_SRC_TSIZE_2 0x5C0034
+
+#define mmDMA6_CORE_SRC_STRIDE_2 0x5C0038
+
+#define mmDMA6_CORE_SRC_TSIZE_3 0x5C003C
+
+#define mmDMA6_CORE_SRC_STRIDE_3 0x5C0040
+
+#define mmDMA6_CORE_SRC_TSIZE_4 0x5C0044
+
+#define mmDMA6_CORE_SRC_STRIDE_4 0x5C0048
+
+#define mmDMA6_CORE_SRC_TSIZE_0 0x5C004C
+
+#define mmDMA6_CORE_DST_TSIZE_1 0x5C0054
+
+#define mmDMA6_CORE_DST_STRIDE_1 0x5C0058
+
+#define mmDMA6_CORE_DST_TSIZE_2 0x5C005C
+
+#define mmDMA6_CORE_DST_STRIDE_2 0x5C0060
+
+#define mmDMA6_CORE_DST_TSIZE_3 0x5C0064
+
+#define mmDMA6_CORE_DST_STRIDE_3 0x5C0068
+
+#define mmDMA6_CORE_DST_TSIZE_4 0x5C006C
+
+#define mmDMA6_CORE_DST_STRIDE_4 0x5C0070
+
+#define mmDMA6_CORE_DST_TSIZE_0 0x5C0074
+
+#define mmDMA6_CORE_COMMIT 0x5C0078
+
+#define mmDMA6_CORE_WR_COMP_WDATA 0x5C007C
+
+#define mmDMA6_CORE_WR_COMP_ADDR_LO 0x5C0080
+
+#define mmDMA6_CORE_WR_COMP_ADDR_HI 0x5C0084
+
+#define mmDMA6_CORE_WR_COMP_AWUSER_31_11 0x5C0088
+
+#define mmDMA6_CORE_TE_NUMROWS 0x5C0094
+
+#define mmDMA6_CORE_PROT 0x5C00B8
+
+#define mmDMA6_CORE_SECURE_PROPS 0x5C00F0
+
+#define mmDMA6_CORE_NON_SECURE_PROPS 0x5C00F4
+
+#define mmDMA6_CORE_RD_MAX_OUTSTAND 0x5C0100
+
+#define mmDMA6_CORE_RD_MAX_SIZE 0x5C0104
+
+#define mmDMA6_CORE_RD_ARCACHE 0x5C0108
+
+#define mmDMA6_CORE_RD_ARUSER_31_11 0x5C0110
+
+#define mmDMA6_CORE_RD_INFLIGHTS 0x5C0114
+
+#define mmDMA6_CORE_WR_MAX_OUTSTAND 0x5C0120
+
+#define mmDMA6_CORE_WR_MAX_AWID 0x5C0124
+
+#define mmDMA6_CORE_WR_AWCACHE 0x5C0128
+
+#define mmDMA6_CORE_WR_AWUSER_31_11 0x5C0130
+
+#define mmDMA6_CORE_WR_INFLIGHTS 0x5C0134
+
+#define mmDMA6_CORE_RD_RATE_LIM_CFG_0 0x5C0150
+
+#define mmDMA6_CORE_RD_RATE_LIM_CFG_1 0x5C0154
+
+#define mmDMA6_CORE_WR_RATE_LIM_CFG_0 0x5C0158
+
+#define mmDMA6_CORE_WR_RATE_LIM_CFG_1 0x5C015C
+
+#define mmDMA6_CORE_ERR_CFG 0x5C0160
+
+#define mmDMA6_CORE_ERR_CAUSE 0x5C0164
+
+#define mmDMA6_CORE_ERRMSG_ADDR_LO 0x5C0170
+
+#define mmDMA6_CORE_ERRMSG_ADDR_HI 0x5C0174
+
+#define mmDMA6_CORE_ERRMSG_WDATA 0x5C0178
+
+#define mmDMA6_CORE_STS0 0x5C0190
+
+#define mmDMA6_CORE_STS1 0x5C0194
+
+#define mmDMA6_CORE_RD_DBGMEM_ADD 0x5C0200
+
+#define mmDMA6_CORE_RD_DBGMEM_DATA_WR 0x5C0204
+
+#define mmDMA6_CORE_RD_DBGMEM_DATA_RD 0x5C0208
+
+#define mmDMA6_CORE_RD_DBGMEM_CTRL 0x5C020C
+
+#define mmDMA6_CORE_RD_DBGMEM_RC 0x5C0210
+
+#define mmDMA6_CORE_DBG_HBW_AXI_AR_CNT 0x5C0220
+
+#define mmDMA6_CORE_DBG_HBW_AXI_AW_CNT 0x5C0224
+
+#define mmDMA6_CORE_DBG_LBW_AXI_AW_CNT 0x5C0228
+
+#define mmDMA6_CORE_DBG_DESC_CNT 0x5C022C
+
+#define mmDMA6_CORE_DBG_STS 0x5C0230
+
+#define mmDMA6_CORE_DBG_RD_DESC_ID 0x5C0234
+
+#define mmDMA6_CORE_DBG_WR_DESC_ID 0x5C0238
+
+#endif /* ASIC_REG_DMA6_CORE_REGS_H_ */
diff --git a/drivers/accel/habanalabs/include/gaudi/asic_reg/dma6_qm_regs.h b/drivers/accel/habanalabs/include/gaudi/asic_reg/dma6_qm_regs.h
new file mode 100644
index 0000000000..af87adb94c
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi/asic_reg/dma6_qm_regs.h
@@ -0,0 +1,834 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2016-2018 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ ** DO NOT EDIT BELOW **
+ ************************************/
+
+#ifndef ASIC_REG_DMA6_QM_REGS_H_
+#define ASIC_REG_DMA6_QM_REGS_H_
+
+/*
+ *****************************************
+ * DMA6_QM (Prototype: QMAN)
+ *****************************************
+ */
+
+#define mmDMA6_QM_GLBL_CFG0 0x5C8000
+
+#define mmDMA6_QM_GLBL_CFG1 0x5C8004
+
+#define mmDMA6_QM_GLBL_PROT 0x5C8008
+
+#define mmDMA6_QM_GLBL_ERR_CFG 0x5C800C
+
+#define mmDMA6_QM_GLBL_SECURE_PROPS_0 0x5C8010
+
+#define mmDMA6_QM_GLBL_SECURE_PROPS_1 0x5C8014
+
+#define mmDMA6_QM_GLBL_SECURE_PROPS_2 0x5C8018
+
+#define mmDMA6_QM_GLBL_SECURE_PROPS_3 0x5C801C
+
+#define mmDMA6_QM_GLBL_SECURE_PROPS_4 0x5C8020
+
+#define mmDMA6_QM_GLBL_NON_SECURE_PROPS_0 0x5C8024
+
+#define mmDMA6_QM_GLBL_NON_SECURE_PROPS_1 0x5C8028
+
+#define mmDMA6_QM_GLBL_NON_SECURE_PROPS_2 0x5C802C
+
+#define mmDMA6_QM_GLBL_NON_SECURE_PROPS_3 0x5C8030
+
+#define mmDMA6_QM_GLBL_NON_SECURE_PROPS_4 0x5C8034
+
+#define mmDMA6_QM_GLBL_STS0 0x5C8038
+
+#define mmDMA6_QM_GLBL_STS1_0 0x5C8040
+
+#define mmDMA6_QM_GLBL_STS1_1 0x5C8044
+
+#define mmDMA6_QM_GLBL_STS1_2 0x5C8048
+
+#define mmDMA6_QM_GLBL_STS1_3 0x5C804C
+
+#define mmDMA6_QM_GLBL_STS1_4 0x5C8050
+
+#define mmDMA6_QM_GLBL_MSG_EN_0 0x5C8054
+
+#define mmDMA6_QM_GLBL_MSG_EN_1 0x5C8058
+
+#define mmDMA6_QM_GLBL_MSG_EN_2 0x5C805C
+
+#define mmDMA6_QM_GLBL_MSG_EN_3 0x5C8060
+
+#define mmDMA6_QM_GLBL_MSG_EN_4 0x5C8068
+
+#define mmDMA6_QM_PQ_BASE_LO_0 0x5C8070
+
+#define mmDMA6_QM_PQ_BASE_LO_1 0x5C8074
+
+#define mmDMA6_QM_PQ_BASE_LO_2 0x5C8078
+
+#define mmDMA6_QM_PQ_BASE_LO_3 0x5C807C
+
+#define mmDMA6_QM_PQ_BASE_HI_0 0x5C8080
+
+#define mmDMA6_QM_PQ_BASE_HI_1 0x5C8084
+
+#define mmDMA6_QM_PQ_BASE_HI_2 0x5C8088
+
+#define mmDMA6_QM_PQ_BASE_HI_3 0x5C808C
+
+#define mmDMA6_QM_PQ_SIZE_0 0x5C8090
+
+#define mmDMA6_QM_PQ_SIZE_1 0x5C8094
+
+#define mmDMA6_QM_PQ_SIZE_2 0x5C8098
+
+#define mmDMA6_QM_PQ_SIZE_3 0x5C809C
+
+#define mmDMA6_QM_PQ_PI_0 0x5C80A0
+
+#define mmDMA6_QM_PQ_PI_1 0x5C80A4
+
+#define mmDMA6_QM_PQ_PI_2 0x5C80A8
+
+#define mmDMA6_QM_PQ_PI_3 0x5C80AC
+
+#define mmDMA6_QM_PQ_CI_0 0x5C80B0
+
+#define mmDMA6_QM_PQ_CI_1 0x5C80B4
+
+#define mmDMA6_QM_PQ_CI_2 0x5C80B8
+
+#define mmDMA6_QM_PQ_CI_3 0x5C80BC
+
+#define mmDMA6_QM_PQ_CFG0_0 0x5C80C0
+
+#define mmDMA6_QM_PQ_CFG0_1 0x5C80C4
+
+#define mmDMA6_QM_PQ_CFG0_2 0x5C80C8
+
+#define mmDMA6_QM_PQ_CFG0_3 0x5C80CC
+
+#define mmDMA6_QM_PQ_CFG1_0 0x5C80D0
+
+#define mmDMA6_QM_PQ_CFG1_1 0x5C80D4
+
+#define mmDMA6_QM_PQ_CFG1_2 0x5C80D8
+
+#define mmDMA6_QM_PQ_CFG1_3 0x5C80DC
+
+#define mmDMA6_QM_PQ_ARUSER_31_11_0 0x5C80E0
+
+#define mmDMA6_QM_PQ_ARUSER_31_11_1 0x5C80E4
+
+#define mmDMA6_QM_PQ_ARUSER_31_11_2 0x5C80E8
+
+#define mmDMA6_QM_PQ_ARUSER_31_11_3 0x5C80EC
+
+#define mmDMA6_QM_PQ_STS0_0 0x5C80F0
+
+#define mmDMA6_QM_PQ_STS0_1 0x5C80F4
+
+#define mmDMA6_QM_PQ_STS0_2 0x5C80F8
+
+#define mmDMA6_QM_PQ_STS0_3 0x5C80FC
+
+#define mmDMA6_QM_PQ_STS1_0 0x5C8100
+
+#define mmDMA6_QM_PQ_STS1_1 0x5C8104
+
+#define mmDMA6_QM_PQ_STS1_2 0x5C8108
+
+#define mmDMA6_QM_PQ_STS1_3 0x5C810C
+
+#define mmDMA6_QM_CQ_CFG0_0 0x5C8110
+
+#define mmDMA6_QM_CQ_CFG0_1 0x5C8114
+
+#define mmDMA6_QM_CQ_CFG0_2 0x5C8118
+
+#define mmDMA6_QM_CQ_CFG0_3 0x5C811C
+
+#define mmDMA6_QM_CQ_CFG0_4 0x5C8120
+
+#define mmDMA6_QM_CQ_CFG1_0 0x5C8124
+
+#define mmDMA6_QM_CQ_CFG1_1 0x5C8128
+
+#define mmDMA6_QM_CQ_CFG1_2 0x5C812C
+
+#define mmDMA6_QM_CQ_CFG1_3 0x5C8130
+
+#define mmDMA6_QM_CQ_CFG1_4 0x5C8134
+
+#define mmDMA6_QM_CQ_ARUSER_31_11_0 0x5C8138
+
+#define mmDMA6_QM_CQ_ARUSER_31_11_1 0x5C813C
+
+#define mmDMA6_QM_CQ_ARUSER_31_11_2 0x5C8140
+
+#define mmDMA6_QM_CQ_ARUSER_31_11_3 0x5C8144
+
+#define mmDMA6_QM_CQ_ARUSER_31_11_4 0x5C8148
+
+#define mmDMA6_QM_CQ_STS0_0 0x5C814C
+
+#define mmDMA6_QM_CQ_STS0_1 0x5C8150
+
+#define mmDMA6_QM_CQ_STS0_2 0x5C8154
+
+#define mmDMA6_QM_CQ_STS0_3 0x5C8158
+
+#define mmDMA6_QM_CQ_STS0_4 0x5C815C
+
+#define mmDMA6_QM_CQ_STS1_0 0x5C8160
+
+#define mmDMA6_QM_CQ_STS1_1 0x5C8164
+
+#define mmDMA6_QM_CQ_STS1_2 0x5C8168
+
+#define mmDMA6_QM_CQ_STS1_3 0x5C816C
+
+#define mmDMA6_QM_CQ_STS1_4 0x5C8170
+
+#define mmDMA6_QM_CQ_PTR_LO_0 0x5C8174
+
+#define mmDMA6_QM_CQ_PTR_HI_0 0x5C8178
+
+#define mmDMA6_QM_CQ_TSIZE_0 0x5C817C
+
+#define mmDMA6_QM_CQ_CTL_0 0x5C8180
+
+#define mmDMA6_QM_CQ_PTR_LO_1 0x5C8184
+
+#define mmDMA6_QM_CQ_PTR_HI_1 0x5C8188
+
+#define mmDMA6_QM_CQ_TSIZE_1 0x5C818C
+
+#define mmDMA6_QM_CQ_CTL_1 0x5C8190
+
+#define mmDMA6_QM_CQ_PTR_LO_2 0x5C8194
+
+#define mmDMA6_QM_CQ_PTR_HI_2 0x5C8198
+
+#define mmDMA6_QM_CQ_TSIZE_2 0x5C819C
+
+#define mmDMA6_QM_CQ_CTL_2 0x5C81A0
+
+#define mmDMA6_QM_CQ_PTR_LO_3 0x5C81A4
+
+#define mmDMA6_QM_CQ_PTR_HI_3 0x5C81A8
+
+#define mmDMA6_QM_CQ_TSIZE_3 0x5C81AC
+
+#define mmDMA6_QM_CQ_CTL_3 0x5C81B0
+
+#define mmDMA6_QM_CQ_PTR_LO_4 0x5C81B4
+
+#define mmDMA6_QM_CQ_PTR_HI_4 0x5C81B8
+
+#define mmDMA6_QM_CQ_TSIZE_4 0x5C81BC
+
+#define mmDMA6_QM_CQ_CTL_4 0x5C81C0
+
+#define mmDMA6_QM_CQ_PTR_LO_STS_0 0x5C81C4
+
+#define mmDMA6_QM_CQ_PTR_LO_STS_1 0x5C81C8
+
+#define mmDMA6_QM_CQ_PTR_LO_STS_2 0x5C81CC
+
+#define mmDMA6_QM_CQ_PTR_LO_STS_3 0x5C81D0
+
+#define mmDMA6_QM_CQ_PTR_LO_STS_4 0x5C81D4
+
+#define mmDMA6_QM_CQ_PTR_HI_STS_0 0x5C81D8
+
+#define mmDMA6_QM_CQ_PTR_HI_STS_1 0x5C81DC
+
+#define mmDMA6_QM_CQ_PTR_HI_STS_2 0x5C81E0
+
+#define mmDMA6_QM_CQ_PTR_HI_STS_3 0x5C81E4
+
+#define mmDMA6_QM_CQ_PTR_HI_STS_4 0x5C81E8
+
+#define mmDMA6_QM_CQ_TSIZE_STS_0 0x5C81EC
+
+#define mmDMA6_QM_CQ_TSIZE_STS_1 0x5C81F0
+
+#define mmDMA6_QM_CQ_TSIZE_STS_2 0x5C81F4
+
+#define mmDMA6_QM_CQ_TSIZE_STS_3 0x5C81F8
+
+#define mmDMA6_QM_CQ_TSIZE_STS_4 0x5C81FC
+
+#define mmDMA6_QM_CQ_CTL_STS_0 0x5C8200
+
+#define mmDMA6_QM_CQ_CTL_STS_1 0x5C8204
+
+#define mmDMA6_QM_CQ_CTL_STS_2 0x5C8208
+
+#define mmDMA6_QM_CQ_CTL_STS_3 0x5C820C
+
+#define mmDMA6_QM_CQ_CTL_STS_4 0x5C8210
+
+#define mmDMA6_QM_CQ_IFIFO_CNT_0 0x5C8214
+
+#define mmDMA6_QM_CQ_IFIFO_CNT_1 0x5C8218
+
+#define mmDMA6_QM_CQ_IFIFO_CNT_2 0x5C821C
+
+#define mmDMA6_QM_CQ_IFIFO_CNT_3 0x5C8220
+
+#define mmDMA6_QM_CQ_IFIFO_CNT_4 0x5C8224
+
+#define mmDMA6_QM_CP_MSG_BASE0_ADDR_LO_0 0x5C8228
+
+#define mmDMA6_QM_CP_MSG_BASE0_ADDR_LO_1 0x5C822C
+
+#define mmDMA6_QM_CP_MSG_BASE0_ADDR_LO_2 0x5C8230
+
+#define mmDMA6_QM_CP_MSG_BASE0_ADDR_LO_3 0x5C8234
+
+#define mmDMA6_QM_CP_MSG_BASE0_ADDR_LO_4 0x5C8238
+
+#define mmDMA6_QM_CP_MSG_BASE0_ADDR_HI_0 0x5C823C
+
+#define mmDMA6_QM_CP_MSG_BASE0_ADDR_HI_1 0x5C8240
+
+#define mmDMA6_QM_CP_MSG_BASE0_ADDR_HI_2 0x5C8244
+
+#define mmDMA6_QM_CP_MSG_BASE0_ADDR_HI_3 0x5C8248
+
+#define mmDMA6_QM_CP_MSG_BASE0_ADDR_HI_4 0x5C824C
+
+#define mmDMA6_QM_CP_MSG_BASE1_ADDR_LO_0 0x5C8250
+
+#define mmDMA6_QM_CP_MSG_BASE1_ADDR_LO_1 0x5C8254
+
+#define mmDMA6_QM_CP_MSG_BASE1_ADDR_LO_2 0x5C8258
+
+#define mmDMA6_QM_CP_MSG_BASE1_ADDR_LO_3 0x5C825C
+
+#define mmDMA6_QM_CP_MSG_BASE1_ADDR_LO_4 0x5C8260
+
+#define mmDMA6_QM_CP_MSG_BASE1_ADDR_HI_0 0x5C8264
+
+#define mmDMA6_QM_CP_MSG_BASE1_ADDR_HI_1 0x5C8268
+
+#define mmDMA6_QM_CP_MSG_BASE1_ADDR_HI_2 0x5C826C
+
+#define mmDMA6_QM_CP_MSG_BASE1_ADDR_HI_3 0x5C8270
+
+#define mmDMA6_QM_CP_MSG_BASE1_ADDR_HI_4 0x5C8274
+
+#define mmDMA6_QM_CP_MSG_BASE2_ADDR_LO_0 0x5C8278
+
+#define mmDMA6_QM_CP_MSG_BASE2_ADDR_LO_1 0x5C827C
+
+#define mmDMA6_QM_CP_MSG_BASE2_ADDR_LO_2 0x5C8280
+
+#define mmDMA6_QM_CP_MSG_BASE2_ADDR_LO_3 0x5C8284
+
+#define mmDMA6_QM_CP_MSG_BASE2_ADDR_LO_4 0x5C8288
+
+#define mmDMA6_QM_CP_MSG_BASE2_ADDR_HI_0 0x5C828C
+
+#define mmDMA6_QM_CP_MSG_BASE2_ADDR_HI_1 0x5C8290
+
+#define mmDMA6_QM_CP_MSG_BASE2_ADDR_HI_2 0x5C8294
+
+#define mmDMA6_QM_CP_MSG_BASE2_ADDR_HI_3 0x5C8298
+
+#define mmDMA6_QM_CP_MSG_BASE2_ADDR_HI_4 0x5C829C
+
+#define mmDMA6_QM_CP_MSG_BASE3_ADDR_LO_0 0x5C82A0
+
+#define mmDMA6_QM_CP_MSG_BASE3_ADDR_LO_1 0x5C82A4
+
+#define mmDMA6_QM_CP_MSG_BASE3_ADDR_LO_2 0x5C82A8
+
+#define mmDMA6_QM_CP_MSG_BASE3_ADDR_LO_3 0x5C82AC
+
+#define mmDMA6_QM_CP_MSG_BASE3_ADDR_LO_4 0x5C82B0
+
+#define mmDMA6_QM_CP_MSG_BASE3_ADDR_HI_0 0x5C82B4
+
+#define mmDMA6_QM_CP_MSG_BASE3_ADDR_HI_1 0x5C82B8
+
+#define mmDMA6_QM_CP_MSG_BASE3_ADDR_HI_2 0x5C82BC
+
+#define mmDMA6_QM_CP_MSG_BASE3_ADDR_HI_3 0x5C82C0
+
+#define mmDMA6_QM_CP_MSG_BASE3_ADDR_HI_4 0x5C82C4
+
+#define mmDMA6_QM_CP_LDMA_TSIZE_OFFSET_0 0x5C82C8
+
+#define mmDMA6_QM_CP_LDMA_TSIZE_OFFSET_1 0x5C82CC
+
+#define mmDMA6_QM_CP_LDMA_TSIZE_OFFSET_2 0x5C82D0
+
+#define mmDMA6_QM_CP_LDMA_TSIZE_OFFSET_3 0x5C82D4
+
+#define mmDMA6_QM_CP_LDMA_TSIZE_OFFSET_4 0x5C82D8
+
+#define mmDMA6_QM_CP_LDMA_SRC_BASE_LO_OFFSET_0 0x5C82E0
+
+#define mmDMA6_QM_CP_LDMA_SRC_BASE_LO_OFFSET_1 0x5C82E4
+
+#define mmDMA6_QM_CP_LDMA_SRC_BASE_LO_OFFSET_2 0x5C82E8
+
+#define mmDMA6_QM_CP_LDMA_SRC_BASE_LO_OFFSET_3 0x5C82EC
+
+#define mmDMA6_QM_CP_LDMA_SRC_BASE_LO_OFFSET_4 0x5C82F0
+
+#define mmDMA6_QM_CP_LDMA_DST_BASE_LO_OFFSET_0 0x5C82F4
+
+#define mmDMA6_QM_CP_LDMA_DST_BASE_LO_OFFSET_1 0x5C82F8
+
+#define mmDMA6_QM_CP_LDMA_DST_BASE_LO_OFFSET_2 0x5C82FC
+
+#define mmDMA6_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 0x5C8300
+
+#define mmDMA6_QM_CP_LDMA_DST_BASE_LO_OFFSET_4 0x5C8304
+
+#define mmDMA6_QM_CP_FENCE0_RDATA_0 0x5C8308
+
+#define mmDMA6_QM_CP_FENCE0_RDATA_1 0x5C830C
+
+#define mmDMA6_QM_CP_FENCE0_RDATA_2 0x5C8310
+
+#define mmDMA6_QM_CP_FENCE0_RDATA_3 0x5C8314
+
+#define mmDMA6_QM_CP_FENCE0_RDATA_4 0x5C8318
+
+#define mmDMA6_QM_CP_FENCE1_RDATA_0 0x5C831C
+
+#define mmDMA6_QM_CP_FENCE1_RDATA_1 0x5C8320
+
+#define mmDMA6_QM_CP_FENCE1_RDATA_2 0x5C8324
+
+#define mmDMA6_QM_CP_FENCE1_RDATA_3 0x5C8328
+
+#define mmDMA6_QM_CP_FENCE1_RDATA_4 0x5C832C
+
+#define mmDMA6_QM_CP_FENCE2_RDATA_0 0x5C8330
+
+#define mmDMA6_QM_CP_FENCE2_RDATA_1 0x5C8334
+
+#define mmDMA6_QM_CP_FENCE2_RDATA_2 0x5C8338
+
+#define mmDMA6_QM_CP_FENCE2_RDATA_3 0x5C833C
+
+#define mmDMA6_QM_CP_FENCE2_RDATA_4 0x5C8340
+
+#define mmDMA6_QM_CP_FENCE3_RDATA_0 0x5C8344
+
+#define mmDMA6_QM_CP_FENCE3_RDATA_1 0x5C8348
+
+#define mmDMA6_QM_CP_FENCE3_RDATA_2 0x5C834C
+
+#define mmDMA6_QM_CP_FENCE3_RDATA_3 0x5C8350
+
+#define mmDMA6_QM_CP_FENCE3_RDATA_4 0x5C8354
+
+#define mmDMA6_QM_CP_FENCE0_CNT_0 0x5C8358
+
+#define mmDMA6_QM_CP_FENCE0_CNT_1 0x5C835C
+
+#define mmDMA6_QM_CP_FENCE0_CNT_2 0x5C8360
+
+#define mmDMA6_QM_CP_FENCE0_CNT_3 0x5C8364
+
+#define mmDMA6_QM_CP_FENCE0_CNT_4 0x5C8368
+
+#define mmDMA6_QM_CP_FENCE1_CNT_0 0x5C836C
+
+#define mmDMA6_QM_CP_FENCE1_CNT_1 0x5C8370
+
+#define mmDMA6_QM_CP_FENCE1_CNT_2 0x5C8374
+
+#define mmDMA6_QM_CP_FENCE1_CNT_3 0x5C8378
+
+#define mmDMA6_QM_CP_FENCE1_CNT_4 0x5C837C
+
+#define mmDMA6_QM_CP_FENCE2_CNT_0 0x5C8380
+
+#define mmDMA6_QM_CP_FENCE2_CNT_1 0x5C8384
+
+#define mmDMA6_QM_CP_FENCE2_CNT_2 0x5C8388
+
+#define mmDMA6_QM_CP_FENCE2_CNT_3 0x5C838C
+
+#define mmDMA6_QM_CP_FENCE2_CNT_4 0x5C8390
+
+#define mmDMA6_QM_CP_FENCE3_CNT_0 0x5C8394
+
+#define mmDMA6_QM_CP_FENCE3_CNT_1 0x5C8398
+
+#define mmDMA6_QM_CP_FENCE3_CNT_2 0x5C839C
+
+#define mmDMA6_QM_CP_FENCE3_CNT_3 0x5C83A0
+
+#define mmDMA6_QM_CP_FENCE3_CNT_4 0x5C83A4
+
+#define mmDMA6_QM_CP_STS_0 0x5C83A8
+
+#define mmDMA6_QM_CP_STS_1 0x5C83AC
+
+#define mmDMA6_QM_CP_STS_2 0x5C83B0
+
+#define mmDMA6_QM_CP_STS_3 0x5C83B4
+
+#define mmDMA6_QM_CP_STS_4 0x5C83B8
+
+#define mmDMA6_QM_CP_CURRENT_INST_LO_0 0x5C83BC
+
+#define mmDMA6_QM_CP_CURRENT_INST_LO_1 0x5C83C0
+
+#define mmDMA6_QM_CP_CURRENT_INST_LO_2 0x5C83C4
+
+#define mmDMA6_QM_CP_CURRENT_INST_LO_3 0x5C83C8
+
+#define mmDMA6_QM_CP_CURRENT_INST_LO_4 0x5C83CC
+
+#define mmDMA6_QM_CP_CURRENT_INST_HI_0 0x5C83D0
+
+#define mmDMA6_QM_CP_CURRENT_INST_HI_1 0x5C83D4
+
+#define mmDMA6_QM_CP_CURRENT_INST_HI_2 0x5C83D8
+
+#define mmDMA6_QM_CP_CURRENT_INST_HI_3 0x5C83DC
+
+#define mmDMA6_QM_CP_CURRENT_INST_HI_4 0x5C83E0
+
+#define mmDMA6_QM_CP_BARRIER_CFG_0 0x5C83F4
+
+#define mmDMA6_QM_CP_BARRIER_CFG_1 0x5C83F8
+
+#define mmDMA6_QM_CP_BARRIER_CFG_2 0x5C83FC
+
+#define mmDMA6_QM_CP_BARRIER_CFG_3 0x5C8400
+
+#define mmDMA6_QM_CP_BARRIER_CFG_4 0x5C8404
+
+#define mmDMA6_QM_CP_DBG_0_0 0x5C8408
+
+#define mmDMA6_QM_CP_DBG_0_1 0x5C840C
+
+#define mmDMA6_QM_CP_DBG_0_2 0x5C8410
+
+#define mmDMA6_QM_CP_DBG_0_3 0x5C8414
+
+#define mmDMA6_QM_CP_DBG_0_4 0x5C8418
+
+#define mmDMA6_QM_CP_ARUSER_31_11_0 0x5C841C
+
+#define mmDMA6_QM_CP_ARUSER_31_11_1 0x5C8420
+
+#define mmDMA6_QM_CP_ARUSER_31_11_2 0x5C8424
+
+#define mmDMA6_QM_CP_ARUSER_31_11_3 0x5C8428
+
+#define mmDMA6_QM_CP_ARUSER_31_11_4 0x5C842C
+
+#define mmDMA6_QM_CP_AWUSER_31_11_0 0x5C8430
+
+#define mmDMA6_QM_CP_AWUSER_31_11_1 0x5C8434
+
+#define mmDMA6_QM_CP_AWUSER_31_11_2 0x5C8438
+
+#define mmDMA6_QM_CP_AWUSER_31_11_3 0x5C843C
+
+#define mmDMA6_QM_CP_AWUSER_31_11_4 0x5C8440
+
+#define mmDMA6_QM_ARB_CFG_0 0x5C8A00
+
+#define mmDMA6_QM_ARB_CHOISE_Q_PUSH 0x5C8A04
+
+#define mmDMA6_QM_ARB_WRR_WEIGHT_0 0x5C8A08
+
+#define mmDMA6_QM_ARB_WRR_WEIGHT_1 0x5C8A0C
+
+#define mmDMA6_QM_ARB_WRR_WEIGHT_2 0x5C8A10
+
+#define mmDMA6_QM_ARB_WRR_WEIGHT_3 0x5C8A14
+
+#define mmDMA6_QM_ARB_CFG_1 0x5C8A18
+
+#define mmDMA6_QM_ARB_MST_AVAIL_CRED_0 0x5C8A20
+
+#define mmDMA6_QM_ARB_MST_AVAIL_CRED_1 0x5C8A24
+
+#define mmDMA6_QM_ARB_MST_AVAIL_CRED_2 0x5C8A28
+
+#define mmDMA6_QM_ARB_MST_AVAIL_CRED_3 0x5C8A2C
+
+#define mmDMA6_QM_ARB_MST_AVAIL_CRED_4 0x5C8A30
+
+#define mmDMA6_QM_ARB_MST_AVAIL_CRED_5 0x5C8A34
+
+#define mmDMA6_QM_ARB_MST_AVAIL_CRED_6 0x5C8A38
+
+#define mmDMA6_QM_ARB_MST_AVAIL_CRED_7 0x5C8A3C
+
+#define mmDMA6_QM_ARB_MST_AVAIL_CRED_8 0x5C8A40
+
+#define mmDMA6_QM_ARB_MST_AVAIL_CRED_9 0x5C8A44
+
+#define mmDMA6_QM_ARB_MST_AVAIL_CRED_10 0x5C8A48
+
+#define mmDMA6_QM_ARB_MST_AVAIL_CRED_11 0x5C8A4C
+
+#define mmDMA6_QM_ARB_MST_AVAIL_CRED_12 0x5C8A50
+
+#define mmDMA6_QM_ARB_MST_AVAIL_CRED_13 0x5C8A54
+
+#define mmDMA6_QM_ARB_MST_AVAIL_CRED_14 0x5C8A58
+
+#define mmDMA6_QM_ARB_MST_AVAIL_CRED_15 0x5C8A5C
+
+#define mmDMA6_QM_ARB_MST_AVAIL_CRED_16 0x5C8A60
+
+#define mmDMA6_QM_ARB_MST_AVAIL_CRED_17 0x5C8A64
+
+#define mmDMA6_QM_ARB_MST_AVAIL_CRED_18 0x5C8A68
+
+#define mmDMA6_QM_ARB_MST_AVAIL_CRED_19 0x5C8A6C
+
+#define mmDMA6_QM_ARB_MST_AVAIL_CRED_20 0x5C8A70
+
+#define mmDMA6_QM_ARB_MST_AVAIL_CRED_21 0x5C8A74
+
+#define mmDMA6_QM_ARB_MST_AVAIL_CRED_22 0x5C8A78
+
+#define mmDMA6_QM_ARB_MST_AVAIL_CRED_23 0x5C8A7C
+
+#define mmDMA6_QM_ARB_MST_AVAIL_CRED_24 0x5C8A80
+
+#define mmDMA6_QM_ARB_MST_AVAIL_CRED_25 0x5C8A84
+
+#define mmDMA6_QM_ARB_MST_AVAIL_CRED_26 0x5C8A88
+
+#define mmDMA6_QM_ARB_MST_AVAIL_CRED_27 0x5C8A8C
+
+#define mmDMA6_QM_ARB_MST_AVAIL_CRED_28 0x5C8A90
+
+#define mmDMA6_QM_ARB_MST_AVAIL_CRED_29 0x5C8A94
+
+#define mmDMA6_QM_ARB_MST_AVAIL_CRED_30 0x5C8A98
+
+#define mmDMA6_QM_ARB_MST_AVAIL_CRED_31 0x5C8A9C
+
+#define mmDMA6_QM_ARB_MST_CRED_INC 0x5C8AA0
+
+#define mmDMA6_QM_ARB_MST_CHOISE_PUSH_OFST_0 0x5C8AA4
+
+#define mmDMA6_QM_ARB_MST_CHOISE_PUSH_OFST_1 0x5C8AA8
+
+#define mmDMA6_QM_ARB_MST_CHOISE_PUSH_OFST_2 0x5C8AAC
+
+#define mmDMA6_QM_ARB_MST_CHOISE_PUSH_OFST_3 0x5C8AB0
+
+#define mmDMA6_QM_ARB_MST_CHOISE_PUSH_OFST_4 0x5C8AB4
+
+#define mmDMA6_QM_ARB_MST_CHOISE_PUSH_OFST_5 0x5C8AB8
+
+#define mmDMA6_QM_ARB_MST_CHOISE_PUSH_OFST_6 0x5C8ABC
+
+#define mmDMA6_QM_ARB_MST_CHOISE_PUSH_OFST_7 0x5C8AC0
+
+#define mmDMA6_QM_ARB_MST_CHOISE_PUSH_OFST_8 0x5C8AC4
+
+#define mmDMA6_QM_ARB_MST_CHOISE_PUSH_OFST_9 0x5C8AC8
+
+#define mmDMA6_QM_ARB_MST_CHOISE_PUSH_OFST_10 0x5C8ACC
+
+#define mmDMA6_QM_ARB_MST_CHOISE_PUSH_OFST_11 0x5C8AD0
+
+#define mmDMA6_QM_ARB_MST_CHOISE_PUSH_OFST_12 0x5C8AD4
+
+#define mmDMA6_QM_ARB_MST_CHOISE_PUSH_OFST_13 0x5C8AD8
+
+#define mmDMA6_QM_ARB_MST_CHOISE_PUSH_OFST_14 0x5C8ADC
+
+#define mmDMA6_QM_ARB_MST_CHOISE_PUSH_OFST_15 0x5C8AE0
+
+#define mmDMA6_QM_ARB_MST_CHOISE_PUSH_OFST_16 0x5C8AE4
+
+#define mmDMA6_QM_ARB_MST_CHOISE_PUSH_OFST_17 0x5C8AE8
+
+#define mmDMA6_QM_ARB_MST_CHOISE_PUSH_OFST_18 0x5C8AEC
+
+#define mmDMA6_QM_ARB_MST_CHOISE_PUSH_OFST_19 0x5C8AF0
+
+#define mmDMA6_QM_ARB_MST_CHOISE_PUSH_OFST_20 0x5C8AF4
+
+#define mmDMA6_QM_ARB_MST_CHOISE_PUSH_OFST_21 0x5C8AF8
+
+#define mmDMA6_QM_ARB_MST_CHOISE_PUSH_OFST_22 0x5C8AFC
+
+#define mmDMA6_QM_ARB_MST_CHOISE_PUSH_OFST_23 0x5C8B00
+
+#define mmDMA6_QM_ARB_MST_CHOISE_PUSH_OFST_24 0x5C8B04
+
+#define mmDMA6_QM_ARB_MST_CHOISE_PUSH_OFST_25 0x5C8B08
+
+#define mmDMA6_QM_ARB_MST_CHOISE_PUSH_OFST_26 0x5C8B0C
+
+#define mmDMA6_QM_ARB_MST_CHOISE_PUSH_OFST_27 0x5C8B10
+
+#define mmDMA6_QM_ARB_MST_CHOISE_PUSH_OFST_28 0x5C8B14
+
+#define mmDMA6_QM_ARB_MST_CHOISE_PUSH_OFST_29 0x5C8B18
+
+#define mmDMA6_QM_ARB_MST_CHOISE_PUSH_OFST_30 0x5C8B1C
+
+#define mmDMA6_QM_ARB_MST_CHOISE_PUSH_OFST_31 0x5C8B20
+
+#define mmDMA6_QM_ARB_SLV_MASTER_INC_CRED_OFST 0x5C8B28
+
+#define mmDMA6_QM_ARB_MST_SLAVE_EN 0x5C8B2C
+
+#define mmDMA6_QM_ARB_MST_QUIET_PER 0x5C8B34
+
+#define mmDMA6_QM_ARB_SLV_CHOISE_WDT 0x5C8B38
+
+#define mmDMA6_QM_ARB_SLV_ID 0x5C8B3C
+
+#define mmDMA6_QM_ARB_MSG_MAX_INFLIGHT 0x5C8B44
+
+#define mmDMA6_QM_ARB_MSG_AWUSER_31_11 0x5C8B48
+
+#define mmDMA6_QM_ARB_MSG_AWUSER_SEC_PROP 0x5C8B4C
+
+#define mmDMA6_QM_ARB_MSG_AWUSER_NON_SEC_PROP 0x5C8B50
+
+#define mmDMA6_QM_ARB_BASE_LO 0x5C8B54
+
+#define mmDMA6_QM_ARB_BASE_HI 0x5C8B58
+
+#define mmDMA6_QM_ARB_STATE_STS 0x5C8B80
+
+#define mmDMA6_QM_ARB_CHOISE_FULLNESS_STS 0x5C8B84
+
+#define mmDMA6_QM_ARB_MSG_STS 0x5C8B88
+
+#define mmDMA6_QM_ARB_SLV_CHOISE_Q_HEAD 0x5C8B8C
+
+#define mmDMA6_QM_ARB_ERR_CAUSE 0x5C8B9C
+
+#define mmDMA6_QM_ARB_ERR_MSG_EN 0x5C8BA0
+
+#define mmDMA6_QM_ARB_ERR_STS_DRP 0x5C8BA8
+
+#define mmDMA6_QM_ARB_MST_CRED_STS_0 0x5C8BB0
+
+#define mmDMA6_QM_ARB_MST_CRED_STS_1 0x5C8BB4
+
+#define mmDMA6_QM_ARB_MST_CRED_STS_2 0x5C8BB8
+
+#define mmDMA6_QM_ARB_MST_CRED_STS_3 0x5C8BBC
+
+#define mmDMA6_QM_ARB_MST_CRED_STS_4 0x5C8BC0
+
+#define mmDMA6_QM_ARB_MST_CRED_STS_5 0x5C8BC4
+
+#define mmDMA6_QM_ARB_MST_CRED_STS_6 0x5C8BC8
+
+#define mmDMA6_QM_ARB_MST_CRED_STS_7 0x5C8BCC
+
+#define mmDMA6_QM_ARB_MST_CRED_STS_8 0x5C8BD0
+
+#define mmDMA6_QM_ARB_MST_CRED_STS_9 0x5C8BD4
+
+#define mmDMA6_QM_ARB_MST_CRED_STS_10 0x5C8BD8
+
+#define mmDMA6_QM_ARB_MST_CRED_STS_11 0x5C8BDC
+
+#define mmDMA6_QM_ARB_MST_CRED_STS_12 0x5C8BE0
+
+#define mmDMA6_QM_ARB_MST_CRED_STS_13 0x5C8BE4
+
+#define mmDMA6_QM_ARB_MST_CRED_STS_14 0x5C8BE8
+
+#define mmDMA6_QM_ARB_MST_CRED_STS_15 0x5C8BEC
+
+#define mmDMA6_QM_ARB_MST_CRED_STS_16 0x5C8BF0
+
+#define mmDMA6_QM_ARB_MST_CRED_STS_17 0x5C8BF4
+
+#define mmDMA6_QM_ARB_MST_CRED_STS_18 0x5C8BF8
+
+#define mmDMA6_QM_ARB_MST_CRED_STS_19 0x5C8BFC
+
+#define mmDMA6_QM_ARB_MST_CRED_STS_20 0x5C8C00
+
+#define mmDMA6_QM_ARB_MST_CRED_STS_21 0x5C8C04
+
+#define mmDMA6_QM_ARB_MST_CRED_STS_22 0x5C8C08
+
+#define mmDMA6_QM_ARB_MST_CRED_STS_23 0x5C8C0C
+
+#define mmDMA6_QM_ARB_MST_CRED_STS_24 0x5C8C10
+
+#define mmDMA6_QM_ARB_MST_CRED_STS_25 0x5C8C14
+
+#define mmDMA6_QM_ARB_MST_CRED_STS_26 0x5C8C18
+
+#define mmDMA6_QM_ARB_MST_CRED_STS_27 0x5C8C1C
+
+#define mmDMA6_QM_ARB_MST_CRED_STS_28 0x5C8C20
+
+#define mmDMA6_QM_ARB_MST_CRED_STS_29 0x5C8C24
+
+#define mmDMA6_QM_ARB_MST_CRED_STS_30 0x5C8C28
+
+#define mmDMA6_QM_ARB_MST_CRED_STS_31 0x5C8C2C
+
+#define mmDMA6_QM_CGM_CFG 0x5C8C70
+
+#define mmDMA6_QM_CGM_STS 0x5C8C74
+
+#define mmDMA6_QM_CGM_CFG1 0x5C8C78
+
+#define mmDMA6_QM_LOCAL_RANGE_BASE 0x5C8C80
+
+#define mmDMA6_QM_LOCAL_RANGE_SIZE 0x5C8C84
+
+#define mmDMA6_QM_CSMR_STRICT_PRIO_CFG 0x5C8C90
+
+#define mmDMA6_QM_HBW_RD_RATE_LIM_CFG_1 0x5C8C94
+
+#define mmDMA6_QM_LBW_WR_RATE_LIM_CFG_0 0x5C8C98
+
+#define mmDMA6_QM_LBW_WR_RATE_LIM_CFG_1 0x5C8C9C
+
+#define mmDMA6_QM_HBW_RD_RATE_LIM_CFG_0 0x5C8CA0
+
+#define mmDMA6_QM_GLBL_AXCACHE 0x5C8CA4
+
+#define mmDMA6_QM_IND_GW_APB_CFG 0x5C8CB0
+
+#define mmDMA6_QM_IND_GW_APB_WDATA 0x5C8CB4
+
+#define mmDMA6_QM_IND_GW_APB_RDATA 0x5C8CB8
+
+#define mmDMA6_QM_IND_GW_APB_STATUS 0x5C8CBC
+
+#define mmDMA6_QM_GLBL_ERR_ADDR_LO 0x5C8CD0
+
+#define mmDMA6_QM_GLBL_ERR_ADDR_HI 0x5C8CD4
+
+#define mmDMA6_QM_GLBL_ERR_WDATA 0x5C8CD8
+
+#define mmDMA6_QM_GLBL_MEM_INIT_BUSY 0x5C8D00
+
+#endif /* ASIC_REG_DMA6_QM_REGS_H_ */
diff --git a/drivers/accel/habanalabs/include/gaudi/asic_reg/dma7_core_regs.h b/drivers/accel/habanalabs/include/gaudi/asic_reg/dma7_core_regs.h
new file mode 100644
index 0000000000..8dd705d201
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi/asic_reg/dma7_core_regs.h
@@ -0,0 +1,156 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2016-2018 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ ** DO NOT EDIT BELOW **
+ ************************************/
+
+#ifndef ASIC_REG_DMA7_CORE_REGS_H_
+#define ASIC_REG_DMA7_CORE_REGS_H_
+
+/*
+ *****************************************
+ * DMA7_CORE (Prototype: DMA_CORE)
+ *****************************************
+ */
+
+#define mmDMA7_CORE_CFG_0 0x5E0000
+
+#define mmDMA7_CORE_CFG_1 0x5E0004
+
+#define mmDMA7_CORE_LBW_MAX_OUTSTAND 0x5E0008
+
+#define mmDMA7_CORE_SRC_BASE_LO 0x5E0014
+
+#define mmDMA7_CORE_SRC_BASE_HI 0x5E0018
+
+#define mmDMA7_CORE_DST_BASE_LO 0x5E001C
+
+#define mmDMA7_CORE_DST_BASE_HI 0x5E0020
+
+#define mmDMA7_CORE_SRC_TSIZE_1 0x5E002C
+
+#define mmDMA7_CORE_SRC_STRIDE_1 0x5E0030
+
+#define mmDMA7_CORE_SRC_TSIZE_2 0x5E0034
+
+#define mmDMA7_CORE_SRC_STRIDE_2 0x5E0038
+
+#define mmDMA7_CORE_SRC_TSIZE_3 0x5E003C
+
+#define mmDMA7_CORE_SRC_STRIDE_3 0x5E0040
+
+#define mmDMA7_CORE_SRC_TSIZE_4 0x5E0044
+
+#define mmDMA7_CORE_SRC_STRIDE_4 0x5E0048
+
+#define mmDMA7_CORE_SRC_TSIZE_0 0x5E004C
+
+#define mmDMA7_CORE_DST_TSIZE_1 0x5E0054
+
+#define mmDMA7_CORE_DST_STRIDE_1 0x5E0058
+
+#define mmDMA7_CORE_DST_TSIZE_2 0x5E005C
+
+#define mmDMA7_CORE_DST_STRIDE_2 0x5E0060
+
+#define mmDMA7_CORE_DST_TSIZE_3 0x5E0064
+
+#define mmDMA7_CORE_DST_STRIDE_3 0x5E0068
+
+#define mmDMA7_CORE_DST_TSIZE_4 0x5E006C
+
+#define mmDMA7_CORE_DST_STRIDE_4 0x5E0070
+
+#define mmDMA7_CORE_DST_TSIZE_0 0x5E0074
+
+#define mmDMA7_CORE_COMMIT 0x5E0078
+
+#define mmDMA7_CORE_WR_COMP_WDATA 0x5E007C
+
+#define mmDMA7_CORE_WR_COMP_ADDR_LO 0x5E0080
+
+#define mmDMA7_CORE_WR_COMP_ADDR_HI 0x5E0084
+
+#define mmDMA7_CORE_WR_COMP_AWUSER_31_11 0x5E0088
+
+#define mmDMA7_CORE_TE_NUMROWS 0x5E0094
+
+#define mmDMA7_CORE_PROT 0x5E00B8
+
+#define mmDMA7_CORE_SECURE_PROPS 0x5E00F0
+
+#define mmDMA7_CORE_NON_SECURE_PROPS 0x5E00F4
+
+#define mmDMA7_CORE_RD_MAX_OUTSTAND 0x5E0100
+
+#define mmDMA7_CORE_RD_MAX_SIZE 0x5E0104
+
+#define mmDMA7_CORE_RD_ARCACHE 0x5E0108
+
+#define mmDMA7_CORE_RD_ARUSER_31_11 0x5E0110
+
+#define mmDMA7_CORE_RD_INFLIGHTS 0x5E0114
+
+#define mmDMA7_CORE_WR_MAX_OUTSTAND 0x5E0120
+
+#define mmDMA7_CORE_WR_MAX_AWID 0x5E0124
+
+#define mmDMA7_CORE_WR_AWCACHE 0x5E0128
+
+#define mmDMA7_CORE_WR_AWUSER_31_11 0x5E0130
+
+#define mmDMA7_CORE_WR_INFLIGHTS 0x5E0134
+
+#define mmDMA7_CORE_RD_RATE_LIM_CFG_0 0x5E0150
+
+#define mmDMA7_CORE_RD_RATE_LIM_CFG_1 0x5E0154
+
+#define mmDMA7_CORE_WR_RATE_LIM_CFG_0 0x5E0158
+
+#define mmDMA7_CORE_WR_RATE_LIM_CFG_1 0x5E015C
+
+#define mmDMA7_CORE_ERR_CFG 0x5E0160
+
+#define mmDMA7_CORE_ERR_CAUSE 0x5E0164
+
+#define mmDMA7_CORE_ERRMSG_ADDR_LO 0x5E0170
+
+#define mmDMA7_CORE_ERRMSG_ADDR_HI 0x5E0174
+
+#define mmDMA7_CORE_ERRMSG_WDATA 0x5E0178
+
+#define mmDMA7_CORE_STS0 0x5E0190
+
+#define mmDMA7_CORE_STS1 0x5E0194
+
+#define mmDMA7_CORE_RD_DBGMEM_ADD 0x5E0200
+
+#define mmDMA7_CORE_RD_DBGMEM_DATA_WR 0x5E0204
+
+#define mmDMA7_CORE_RD_DBGMEM_DATA_RD 0x5E0208
+
+#define mmDMA7_CORE_RD_DBGMEM_CTRL 0x5E020C
+
+#define mmDMA7_CORE_RD_DBGMEM_RC 0x5E0210
+
+#define mmDMA7_CORE_DBG_HBW_AXI_AR_CNT 0x5E0220
+
+#define mmDMA7_CORE_DBG_HBW_AXI_AW_CNT 0x5E0224
+
+#define mmDMA7_CORE_DBG_LBW_AXI_AW_CNT 0x5E0228
+
+#define mmDMA7_CORE_DBG_DESC_CNT 0x5E022C
+
+#define mmDMA7_CORE_DBG_STS 0x5E0230
+
+#define mmDMA7_CORE_DBG_RD_DESC_ID 0x5E0234
+
+#define mmDMA7_CORE_DBG_WR_DESC_ID 0x5E0238
+
+#endif /* ASIC_REG_DMA7_CORE_REGS_H_ */
diff --git a/drivers/accel/habanalabs/include/gaudi/asic_reg/dma7_qm_regs.h b/drivers/accel/habanalabs/include/gaudi/asic_reg/dma7_qm_regs.h
new file mode 100644
index 0000000000..d6c631f63e
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi/asic_reg/dma7_qm_regs.h
@@ -0,0 +1,834 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2016-2018 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ ** DO NOT EDIT BELOW **
+ ************************************/
+
+#ifndef ASIC_REG_DMA7_QM_REGS_H_
+#define ASIC_REG_DMA7_QM_REGS_H_
+
+/*
+ *****************************************
+ * DMA7_QM (Prototype: QMAN)
+ *****************************************
+ */
+
+#define mmDMA7_QM_GLBL_CFG0 0x5E8000
+
+#define mmDMA7_QM_GLBL_CFG1 0x5E8004
+
+#define mmDMA7_QM_GLBL_PROT 0x5E8008
+
+#define mmDMA7_QM_GLBL_ERR_CFG 0x5E800C
+
+#define mmDMA7_QM_GLBL_SECURE_PROPS_0 0x5E8010
+
+#define mmDMA7_QM_GLBL_SECURE_PROPS_1 0x5E8014
+
+#define mmDMA7_QM_GLBL_SECURE_PROPS_2 0x5E8018
+
+#define mmDMA7_QM_GLBL_SECURE_PROPS_3 0x5E801C
+
+#define mmDMA7_QM_GLBL_SECURE_PROPS_4 0x5E8020
+
+#define mmDMA7_QM_GLBL_NON_SECURE_PROPS_0 0x5E8024
+
+#define mmDMA7_QM_GLBL_NON_SECURE_PROPS_1 0x5E8028
+
+#define mmDMA7_QM_GLBL_NON_SECURE_PROPS_2 0x5E802C
+
+#define mmDMA7_QM_GLBL_NON_SECURE_PROPS_3 0x5E8030
+
+#define mmDMA7_QM_GLBL_NON_SECURE_PROPS_4 0x5E8034
+
+#define mmDMA7_QM_GLBL_STS0 0x5E8038
+
+#define mmDMA7_QM_GLBL_STS1_0 0x5E8040
+
+#define mmDMA7_QM_GLBL_STS1_1 0x5E8044
+
+#define mmDMA7_QM_GLBL_STS1_2 0x5E8048
+
+#define mmDMA7_QM_GLBL_STS1_3 0x5E804C
+
+#define mmDMA7_QM_GLBL_STS1_4 0x5E8050
+
+#define mmDMA7_QM_GLBL_MSG_EN_0 0x5E8054
+
+#define mmDMA7_QM_GLBL_MSG_EN_1 0x5E8058
+
+#define mmDMA7_QM_GLBL_MSG_EN_2 0x5E805C
+
+#define mmDMA7_QM_GLBL_MSG_EN_3 0x5E8060
+
+#define mmDMA7_QM_GLBL_MSG_EN_4 0x5E8068
+
+#define mmDMA7_QM_PQ_BASE_LO_0 0x5E8070
+
+#define mmDMA7_QM_PQ_BASE_LO_1 0x5E8074
+
+#define mmDMA7_QM_PQ_BASE_LO_2 0x5E8078
+
+#define mmDMA7_QM_PQ_BASE_LO_3 0x5E807C
+
+#define mmDMA7_QM_PQ_BASE_HI_0 0x5E8080
+
+#define mmDMA7_QM_PQ_BASE_HI_1 0x5E8084
+
+#define mmDMA7_QM_PQ_BASE_HI_2 0x5E8088
+
+#define mmDMA7_QM_PQ_BASE_HI_3 0x5E808C
+
+#define mmDMA7_QM_PQ_SIZE_0 0x5E8090
+
+#define mmDMA7_QM_PQ_SIZE_1 0x5E8094
+
+#define mmDMA7_QM_PQ_SIZE_2 0x5E8098
+
+#define mmDMA7_QM_PQ_SIZE_3 0x5E809C
+
+#define mmDMA7_QM_PQ_PI_0 0x5E80A0
+
+#define mmDMA7_QM_PQ_PI_1 0x5E80A4
+
+#define mmDMA7_QM_PQ_PI_2 0x5E80A8
+
+#define mmDMA7_QM_PQ_PI_3 0x5E80AC
+
+#define mmDMA7_QM_PQ_CI_0 0x5E80B0
+
+#define mmDMA7_QM_PQ_CI_1 0x5E80B4
+
+#define mmDMA7_QM_PQ_CI_2 0x5E80B8
+
+#define mmDMA7_QM_PQ_CI_3 0x5E80BC
+
+#define mmDMA7_QM_PQ_CFG0_0 0x5E80C0
+
+#define mmDMA7_QM_PQ_CFG0_1 0x5E80C4
+
+#define mmDMA7_QM_PQ_CFG0_2 0x5E80C8
+
+#define mmDMA7_QM_PQ_CFG0_3 0x5E80CC
+
+#define mmDMA7_QM_PQ_CFG1_0 0x5E80D0
+
+#define mmDMA7_QM_PQ_CFG1_1 0x5E80D4
+
+#define mmDMA7_QM_PQ_CFG1_2 0x5E80D8
+
+#define mmDMA7_QM_PQ_CFG1_3 0x5E80DC
+
+#define mmDMA7_QM_PQ_ARUSER_31_11_0 0x5E80E0
+
+#define mmDMA7_QM_PQ_ARUSER_31_11_1 0x5E80E4
+
+#define mmDMA7_QM_PQ_ARUSER_31_11_2 0x5E80E8
+
+#define mmDMA7_QM_PQ_ARUSER_31_11_3 0x5E80EC
+
+#define mmDMA7_QM_PQ_STS0_0 0x5E80F0
+
+#define mmDMA7_QM_PQ_STS0_1 0x5E80F4
+
+#define mmDMA7_QM_PQ_STS0_2 0x5E80F8
+
+#define mmDMA7_QM_PQ_STS0_3 0x5E80FC
+
+#define mmDMA7_QM_PQ_STS1_0 0x5E8100
+
+#define mmDMA7_QM_PQ_STS1_1 0x5E8104
+
+#define mmDMA7_QM_PQ_STS1_2 0x5E8108
+
+#define mmDMA7_QM_PQ_STS1_3 0x5E810C
+
+#define mmDMA7_QM_CQ_CFG0_0 0x5E8110
+
+#define mmDMA7_QM_CQ_CFG0_1 0x5E8114
+
+#define mmDMA7_QM_CQ_CFG0_2 0x5E8118
+
+#define mmDMA7_QM_CQ_CFG0_3 0x5E811C
+
+#define mmDMA7_QM_CQ_CFG0_4 0x5E8120
+
+#define mmDMA7_QM_CQ_CFG1_0 0x5E8124
+
+#define mmDMA7_QM_CQ_CFG1_1 0x5E8128
+
+#define mmDMA7_QM_CQ_CFG1_2 0x5E812C
+
+#define mmDMA7_QM_CQ_CFG1_3 0x5E8130
+
+#define mmDMA7_QM_CQ_CFG1_4 0x5E8134
+
+#define mmDMA7_QM_CQ_ARUSER_31_11_0 0x5E8138
+
+#define mmDMA7_QM_CQ_ARUSER_31_11_1 0x5E813C
+
+#define mmDMA7_QM_CQ_ARUSER_31_11_2 0x5E8140
+
+#define mmDMA7_QM_CQ_ARUSER_31_11_3 0x5E8144
+
+#define mmDMA7_QM_CQ_ARUSER_31_11_4 0x5E8148
+
+#define mmDMA7_QM_CQ_STS0_0 0x5E814C
+
+#define mmDMA7_QM_CQ_STS0_1 0x5E8150
+
+#define mmDMA7_QM_CQ_STS0_2 0x5E8154
+
+#define mmDMA7_QM_CQ_STS0_3 0x5E8158
+
+#define mmDMA7_QM_CQ_STS0_4 0x5E815C
+
+#define mmDMA7_QM_CQ_STS1_0 0x5E8160
+
+#define mmDMA7_QM_CQ_STS1_1 0x5E8164
+
+#define mmDMA7_QM_CQ_STS1_2 0x5E8168
+
+#define mmDMA7_QM_CQ_STS1_3 0x5E816C
+
+#define mmDMA7_QM_CQ_STS1_4 0x5E8170
+
+#define mmDMA7_QM_CQ_PTR_LO_0 0x5E8174
+
+#define mmDMA7_QM_CQ_PTR_HI_0 0x5E8178
+
+#define mmDMA7_QM_CQ_TSIZE_0 0x5E817C
+
+#define mmDMA7_QM_CQ_CTL_0 0x5E8180
+
+#define mmDMA7_QM_CQ_PTR_LO_1 0x5E8184
+
+#define mmDMA7_QM_CQ_PTR_HI_1 0x5E8188
+
+#define mmDMA7_QM_CQ_TSIZE_1 0x5E818C
+
+#define mmDMA7_QM_CQ_CTL_1 0x5E8190
+
+#define mmDMA7_QM_CQ_PTR_LO_2 0x5E8194
+
+#define mmDMA7_QM_CQ_PTR_HI_2 0x5E8198
+
+#define mmDMA7_QM_CQ_TSIZE_2 0x5E819C
+
+#define mmDMA7_QM_CQ_CTL_2 0x5E81A0
+
+#define mmDMA7_QM_CQ_PTR_LO_3 0x5E81A4
+
+#define mmDMA7_QM_CQ_PTR_HI_3 0x5E81A8
+
+#define mmDMA7_QM_CQ_TSIZE_3 0x5E81AC
+
+#define mmDMA7_QM_CQ_CTL_3 0x5E81B0
+
+#define mmDMA7_QM_CQ_PTR_LO_4 0x5E81B4
+
+#define mmDMA7_QM_CQ_PTR_HI_4 0x5E81B8
+
+#define mmDMA7_QM_CQ_TSIZE_4 0x5E81BC
+
+#define mmDMA7_QM_CQ_CTL_4 0x5E81C0
+
+#define mmDMA7_QM_CQ_PTR_LO_STS_0 0x5E81C4
+
+#define mmDMA7_QM_CQ_PTR_LO_STS_1 0x5E81C8
+
+#define mmDMA7_QM_CQ_PTR_LO_STS_2 0x5E81CC
+
+#define mmDMA7_QM_CQ_PTR_LO_STS_3 0x5E81D0
+
+#define mmDMA7_QM_CQ_PTR_LO_STS_4 0x5E81D4
+
+#define mmDMA7_QM_CQ_PTR_HI_STS_0 0x5E81D8
+
+#define mmDMA7_QM_CQ_PTR_HI_STS_1 0x5E81DC
+
+#define mmDMA7_QM_CQ_PTR_HI_STS_2 0x5E81E0
+
+#define mmDMA7_QM_CQ_PTR_HI_STS_3 0x5E81E4
+
+#define mmDMA7_QM_CQ_PTR_HI_STS_4 0x5E81E8
+
+#define mmDMA7_QM_CQ_TSIZE_STS_0 0x5E81EC
+
+#define mmDMA7_QM_CQ_TSIZE_STS_1 0x5E81F0
+
+#define mmDMA7_QM_CQ_TSIZE_STS_2 0x5E81F4
+
+#define mmDMA7_QM_CQ_TSIZE_STS_3 0x5E81F8
+
+#define mmDMA7_QM_CQ_TSIZE_STS_4 0x5E81FC
+
+#define mmDMA7_QM_CQ_CTL_STS_0 0x5E8200
+
+#define mmDMA7_QM_CQ_CTL_STS_1 0x5E8204
+
+#define mmDMA7_QM_CQ_CTL_STS_2 0x5E8208
+
+#define mmDMA7_QM_CQ_CTL_STS_3 0x5E820C
+
+#define mmDMA7_QM_CQ_CTL_STS_4 0x5E8210
+
+#define mmDMA7_QM_CQ_IFIFO_CNT_0 0x5E8214
+
+#define mmDMA7_QM_CQ_IFIFO_CNT_1 0x5E8218
+
+#define mmDMA7_QM_CQ_IFIFO_CNT_2 0x5E821C
+
+#define mmDMA7_QM_CQ_IFIFO_CNT_3 0x5E8220
+
+#define mmDMA7_QM_CQ_IFIFO_CNT_4 0x5E8224
+
+#define mmDMA7_QM_CP_MSG_BASE0_ADDR_LO_0 0x5E8228
+
+#define mmDMA7_QM_CP_MSG_BASE0_ADDR_LO_1 0x5E822C
+
+#define mmDMA7_QM_CP_MSG_BASE0_ADDR_LO_2 0x5E8230
+
+#define mmDMA7_QM_CP_MSG_BASE0_ADDR_LO_3 0x5E8234
+
+#define mmDMA7_QM_CP_MSG_BASE0_ADDR_LO_4 0x5E8238
+
+#define mmDMA7_QM_CP_MSG_BASE0_ADDR_HI_0 0x5E823C
+
+#define mmDMA7_QM_CP_MSG_BASE0_ADDR_HI_1 0x5E8240
+
+#define mmDMA7_QM_CP_MSG_BASE0_ADDR_HI_2 0x5E8244
+
+#define mmDMA7_QM_CP_MSG_BASE0_ADDR_HI_3 0x5E8248
+
+#define mmDMA7_QM_CP_MSG_BASE0_ADDR_HI_4 0x5E824C
+
+#define mmDMA7_QM_CP_MSG_BASE1_ADDR_LO_0 0x5E8250
+
+#define mmDMA7_QM_CP_MSG_BASE1_ADDR_LO_1 0x5E8254
+
+#define mmDMA7_QM_CP_MSG_BASE1_ADDR_LO_2 0x5E8258
+
+#define mmDMA7_QM_CP_MSG_BASE1_ADDR_LO_3 0x5E825C
+
+#define mmDMA7_QM_CP_MSG_BASE1_ADDR_LO_4 0x5E8260
+
+#define mmDMA7_QM_CP_MSG_BASE1_ADDR_HI_0 0x5E8264
+
+#define mmDMA7_QM_CP_MSG_BASE1_ADDR_HI_1 0x5E8268
+
+#define mmDMA7_QM_CP_MSG_BASE1_ADDR_HI_2 0x5E826C
+
+#define mmDMA7_QM_CP_MSG_BASE1_ADDR_HI_3 0x5E8270
+
+#define mmDMA7_QM_CP_MSG_BASE1_ADDR_HI_4 0x5E8274
+
+#define mmDMA7_QM_CP_MSG_BASE2_ADDR_LO_0 0x5E8278
+
+#define mmDMA7_QM_CP_MSG_BASE2_ADDR_LO_1 0x5E827C
+
+#define mmDMA7_QM_CP_MSG_BASE2_ADDR_LO_2 0x5E8280
+
+#define mmDMA7_QM_CP_MSG_BASE2_ADDR_LO_3 0x5E8284
+
+#define mmDMA7_QM_CP_MSG_BASE2_ADDR_LO_4 0x5E8288
+
+#define mmDMA7_QM_CP_MSG_BASE2_ADDR_HI_0 0x5E828C
+
+#define mmDMA7_QM_CP_MSG_BASE2_ADDR_HI_1 0x5E8290
+
+#define mmDMA7_QM_CP_MSG_BASE2_ADDR_HI_2 0x5E8294
+
+#define mmDMA7_QM_CP_MSG_BASE2_ADDR_HI_3 0x5E8298
+
+#define mmDMA7_QM_CP_MSG_BASE2_ADDR_HI_4 0x5E829C
+
+#define mmDMA7_QM_CP_MSG_BASE3_ADDR_LO_0 0x5E82A0
+
+#define mmDMA7_QM_CP_MSG_BASE3_ADDR_LO_1 0x5E82A4
+
+#define mmDMA7_QM_CP_MSG_BASE3_ADDR_LO_2 0x5E82A8
+
+#define mmDMA7_QM_CP_MSG_BASE3_ADDR_LO_3 0x5E82AC
+
+#define mmDMA7_QM_CP_MSG_BASE3_ADDR_LO_4 0x5E82B0
+
+#define mmDMA7_QM_CP_MSG_BASE3_ADDR_HI_0 0x5E82B4
+
+#define mmDMA7_QM_CP_MSG_BASE3_ADDR_HI_1 0x5E82B8
+
+#define mmDMA7_QM_CP_MSG_BASE3_ADDR_HI_2 0x5E82BC
+
+#define mmDMA7_QM_CP_MSG_BASE3_ADDR_HI_3 0x5E82C0
+
+#define mmDMA7_QM_CP_MSG_BASE3_ADDR_HI_4 0x5E82C4
+
+#define mmDMA7_QM_CP_LDMA_TSIZE_OFFSET_0 0x5E82C8
+
+#define mmDMA7_QM_CP_LDMA_TSIZE_OFFSET_1 0x5E82CC
+
+#define mmDMA7_QM_CP_LDMA_TSIZE_OFFSET_2 0x5E82D0
+
+#define mmDMA7_QM_CP_LDMA_TSIZE_OFFSET_3 0x5E82D4
+
+#define mmDMA7_QM_CP_LDMA_TSIZE_OFFSET_4 0x5E82D8
+
+#define mmDMA7_QM_CP_LDMA_SRC_BASE_LO_OFFSET_0 0x5E82E0
+
+#define mmDMA7_QM_CP_LDMA_SRC_BASE_LO_OFFSET_1 0x5E82E4
+
+#define mmDMA7_QM_CP_LDMA_SRC_BASE_LO_OFFSET_2 0x5E82E8
+
+#define mmDMA7_QM_CP_LDMA_SRC_BASE_LO_OFFSET_3 0x5E82EC
+
+#define mmDMA7_QM_CP_LDMA_SRC_BASE_LO_OFFSET_4 0x5E82F0
+
+#define mmDMA7_QM_CP_LDMA_DST_BASE_LO_OFFSET_0 0x5E82F4
+
+#define mmDMA7_QM_CP_LDMA_DST_BASE_LO_OFFSET_1 0x5E82F8
+
+#define mmDMA7_QM_CP_LDMA_DST_BASE_LO_OFFSET_2 0x5E82FC
+
+#define mmDMA7_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 0x5E8300
+
+#define mmDMA7_QM_CP_LDMA_DST_BASE_LO_OFFSET_4 0x5E8304
+
+#define mmDMA7_QM_CP_FENCE0_RDATA_0 0x5E8308
+
+#define mmDMA7_QM_CP_FENCE0_RDATA_1 0x5E830C
+
+#define mmDMA7_QM_CP_FENCE0_RDATA_2 0x5E8310
+
+#define mmDMA7_QM_CP_FENCE0_RDATA_3 0x5E8314
+
+#define mmDMA7_QM_CP_FENCE0_RDATA_4 0x5E8318
+
+#define mmDMA7_QM_CP_FENCE1_RDATA_0 0x5E831C
+
+#define mmDMA7_QM_CP_FENCE1_RDATA_1 0x5E8320
+
+#define mmDMA7_QM_CP_FENCE1_RDATA_2 0x5E8324
+
+#define mmDMA7_QM_CP_FENCE1_RDATA_3 0x5E8328
+
+#define mmDMA7_QM_CP_FENCE1_RDATA_4 0x5E832C
+
+#define mmDMA7_QM_CP_FENCE2_RDATA_0 0x5E8330
+
+#define mmDMA7_QM_CP_FENCE2_RDATA_1 0x5E8334
+
+#define mmDMA7_QM_CP_FENCE2_RDATA_2 0x5E8338
+
+#define mmDMA7_QM_CP_FENCE2_RDATA_3 0x5E833C
+
+#define mmDMA7_QM_CP_FENCE2_RDATA_4 0x5E8340
+
+#define mmDMA7_QM_CP_FENCE3_RDATA_0 0x5E8344
+
+#define mmDMA7_QM_CP_FENCE3_RDATA_1 0x5E8348
+
+#define mmDMA7_QM_CP_FENCE3_RDATA_2 0x5E834C
+
+#define mmDMA7_QM_CP_FENCE3_RDATA_3 0x5E8350
+
+#define mmDMA7_QM_CP_FENCE3_RDATA_4 0x5E8354
+
+#define mmDMA7_QM_CP_FENCE0_CNT_0 0x5E8358
+
+#define mmDMA7_QM_CP_FENCE0_CNT_1 0x5E835C
+
+#define mmDMA7_QM_CP_FENCE0_CNT_2 0x5E8360
+
+#define mmDMA7_QM_CP_FENCE0_CNT_3 0x5E8364
+
+#define mmDMA7_QM_CP_FENCE0_CNT_4 0x5E8368
+
+#define mmDMA7_QM_CP_FENCE1_CNT_0 0x5E836C
+
+#define mmDMA7_QM_CP_FENCE1_CNT_1 0x5E8370
+
+#define mmDMA7_QM_CP_FENCE1_CNT_2 0x5E8374
+
+#define mmDMA7_QM_CP_FENCE1_CNT_3 0x5E8378
+
+#define mmDMA7_QM_CP_FENCE1_CNT_4 0x5E837C
+
+#define mmDMA7_QM_CP_FENCE2_CNT_0 0x5E8380
+
+#define mmDMA7_QM_CP_FENCE2_CNT_1 0x5E8384
+
+#define mmDMA7_QM_CP_FENCE2_CNT_2 0x5E8388
+
+#define mmDMA7_QM_CP_FENCE2_CNT_3 0x5E838C
+
+#define mmDMA7_QM_CP_FENCE2_CNT_4 0x5E8390
+
+#define mmDMA7_QM_CP_FENCE3_CNT_0 0x5E8394
+
+#define mmDMA7_QM_CP_FENCE3_CNT_1 0x5E8398
+
+#define mmDMA7_QM_CP_FENCE3_CNT_2 0x5E839C
+
+#define mmDMA7_QM_CP_FENCE3_CNT_3 0x5E83A0
+
+#define mmDMA7_QM_CP_FENCE3_CNT_4 0x5E83A4
+
+#define mmDMA7_QM_CP_STS_0 0x5E83A8
+
+#define mmDMA7_QM_CP_STS_1 0x5E83AC
+
+#define mmDMA7_QM_CP_STS_2 0x5E83B0
+
+#define mmDMA7_QM_CP_STS_3 0x5E83B4
+
+#define mmDMA7_QM_CP_STS_4 0x5E83B8
+
+#define mmDMA7_QM_CP_CURRENT_INST_LO_0 0x5E83BC
+
+#define mmDMA7_QM_CP_CURRENT_INST_LO_1 0x5E83C0
+
+#define mmDMA7_QM_CP_CURRENT_INST_LO_2 0x5E83C4
+
+#define mmDMA7_QM_CP_CURRENT_INST_LO_3 0x5E83C8
+
+#define mmDMA7_QM_CP_CURRENT_INST_LO_4 0x5E83CC
+
+#define mmDMA7_QM_CP_CURRENT_INST_HI_0 0x5E83D0
+
+#define mmDMA7_QM_CP_CURRENT_INST_HI_1 0x5E83D4
+
+#define mmDMA7_QM_CP_CURRENT_INST_HI_2 0x5E83D8
+
+#define mmDMA7_QM_CP_CURRENT_INST_HI_3 0x5E83DC
+
+#define mmDMA7_QM_CP_CURRENT_INST_HI_4 0x5E83E0
+
+#define mmDMA7_QM_CP_BARRIER_CFG_0 0x5E83F4
+
+#define mmDMA7_QM_CP_BARRIER_CFG_1 0x5E83F8
+
+#define mmDMA7_QM_CP_BARRIER_CFG_2 0x5E83FC
+
+#define mmDMA7_QM_CP_BARRIER_CFG_3 0x5E8400
+
+#define mmDMA7_QM_CP_BARRIER_CFG_4 0x5E8404
+
+#define mmDMA7_QM_CP_DBG_0_0 0x5E8408
+
+#define mmDMA7_QM_CP_DBG_0_1 0x5E840C
+
+#define mmDMA7_QM_CP_DBG_0_2 0x5E8410
+
+#define mmDMA7_QM_CP_DBG_0_3 0x5E8414
+
+#define mmDMA7_QM_CP_DBG_0_4 0x5E8418
+
+#define mmDMA7_QM_CP_ARUSER_31_11_0 0x5E841C
+
+#define mmDMA7_QM_CP_ARUSER_31_11_1 0x5E8420
+
+#define mmDMA7_QM_CP_ARUSER_31_11_2 0x5E8424
+
+#define mmDMA7_QM_CP_ARUSER_31_11_3 0x5E8428
+
+#define mmDMA7_QM_CP_ARUSER_31_11_4 0x5E842C
+
+#define mmDMA7_QM_CP_AWUSER_31_11_0 0x5E8430
+
+#define mmDMA7_QM_CP_AWUSER_31_11_1 0x5E8434
+
+#define mmDMA7_QM_CP_AWUSER_31_11_2 0x5E8438
+
+#define mmDMA7_QM_CP_AWUSER_31_11_3 0x5E843C
+
+#define mmDMA7_QM_CP_AWUSER_31_11_4 0x5E8440
+
+#define mmDMA7_QM_ARB_CFG_0 0x5E8A00
+
+#define mmDMA7_QM_ARB_CHOISE_Q_PUSH 0x5E8A04
+
+#define mmDMA7_QM_ARB_WRR_WEIGHT_0 0x5E8A08
+
+#define mmDMA7_QM_ARB_WRR_WEIGHT_1 0x5E8A0C
+
+#define mmDMA7_QM_ARB_WRR_WEIGHT_2 0x5E8A10
+
+#define mmDMA7_QM_ARB_WRR_WEIGHT_3 0x5E8A14
+
+#define mmDMA7_QM_ARB_CFG_1 0x5E8A18
+
+#define mmDMA7_QM_ARB_MST_AVAIL_CRED_0 0x5E8A20
+
+#define mmDMA7_QM_ARB_MST_AVAIL_CRED_1 0x5E8A24
+
+#define mmDMA7_QM_ARB_MST_AVAIL_CRED_2 0x5E8A28
+
+#define mmDMA7_QM_ARB_MST_AVAIL_CRED_3 0x5E8A2C
+
+#define mmDMA7_QM_ARB_MST_AVAIL_CRED_4 0x5E8A30
+
+#define mmDMA7_QM_ARB_MST_AVAIL_CRED_5 0x5E8A34
+
+#define mmDMA7_QM_ARB_MST_AVAIL_CRED_6 0x5E8A38
+
+#define mmDMA7_QM_ARB_MST_AVAIL_CRED_7 0x5E8A3C
+
+#define mmDMA7_QM_ARB_MST_AVAIL_CRED_8 0x5E8A40
+
+#define mmDMA7_QM_ARB_MST_AVAIL_CRED_9 0x5E8A44
+
+#define mmDMA7_QM_ARB_MST_AVAIL_CRED_10 0x5E8A48
+
+#define mmDMA7_QM_ARB_MST_AVAIL_CRED_11 0x5E8A4C
+
+#define mmDMA7_QM_ARB_MST_AVAIL_CRED_12 0x5E8A50
+
+#define mmDMA7_QM_ARB_MST_AVAIL_CRED_13 0x5E8A54
+
+#define mmDMA7_QM_ARB_MST_AVAIL_CRED_14 0x5E8A58
+
+#define mmDMA7_QM_ARB_MST_AVAIL_CRED_15 0x5E8A5C
+
+#define mmDMA7_QM_ARB_MST_AVAIL_CRED_16 0x5E8A60
+
+#define mmDMA7_QM_ARB_MST_AVAIL_CRED_17 0x5E8A64
+
+#define mmDMA7_QM_ARB_MST_AVAIL_CRED_18 0x5E8A68
+
+#define mmDMA7_QM_ARB_MST_AVAIL_CRED_19 0x5E8A6C
+
+#define mmDMA7_QM_ARB_MST_AVAIL_CRED_20 0x5E8A70
+
+#define mmDMA7_QM_ARB_MST_AVAIL_CRED_21 0x5E8A74
+
+#define mmDMA7_QM_ARB_MST_AVAIL_CRED_22 0x5E8A78
+
+#define mmDMA7_QM_ARB_MST_AVAIL_CRED_23 0x5E8A7C
+
+#define mmDMA7_QM_ARB_MST_AVAIL_CRED_24 0x5E8A80
+
+#define mmDMA7_QM_ARB_MST_AVAIL_CRED_25 0x5E8A84
+
+#define mmDMA7_QM_ARB_MST_AVAIL_CRED_26 0x5E8A88
+
+#define mmDMA7_QM_ARB_MST_AVAIL_CRED_27 0x5E8A8C
+
+#define mmDMA7_QM_ARB_MST_AVAIL_CRED_28 0x5E8A90
+
+#define mmDMA7_QM_ARB_MST_AVAIL_CRED_29 0x5E8A94
+
+#define mmDMA7_QM_ARB_MST_AVAIL_CRED_30 0x5E8A98
+
+#define mmDMA7_QM_ARB_MST_AVAIL_CRED_31 0x5E8A9C
+
+#define mmDMA7_QM_ARB_MST_CRED_INC 0x5E8AA0
+
+#define mmDMA7_QM_ARB_MST_CHOISE_PUSH_OFST_0 0x5E8AA4
+
+#define mmDMA7_QM_ARB_MST_CHOISE_PUSH_OFST_1 0x5E8AA8
+
+#define mmDMA7_QM_ARB_MST_CHOISE_PUSH_OFST_2 0x5E8AAC
+
+#define mmDMA7_QM_ARB_MST_CHOISE_PUSH_OFST_3 0x5E8AB0
+
+#define mmDMA7_QM_ARB_MST_CHOISE_PUSH_OFST_4 0x5E8AB4
+
+#define mmDMA7_QM_ARB_MST_CHOISE_PUSH_OFST_5 0x5E8AB8
+
+#define mmDMA7_QM_ARB_MST_CHOISE_PUSH_OFST_6 0x5E8ABC
+
+#define mmDMA7_QM_ARB_MST_CHOISE_PUSH_OFST_7 0x5E8AC0
+
+#define mmDMA7_QM_ARB_MST_CHOISE_PUSH_OFST_8 0x5E8AC4
+
+#define mmDMA7_QM_ARB_MST_CHOISE_PUSH_OFST_9 0x5E8AC8
+
+#define mmDMA7_QM_ARB_MST_CHOISE_PUSH_OFST_10 0x5E8ACC
+
+#define mmDMA7_QM_ARB_MST_CHOISE_PUSH_OFST_11 0x5E8AD0
+
+#define mmDMA7_QM_ARB_MST_CHOISE_PUSH_OFST_12 0x5E8AD4
+
+#define mmDMA7_QM_ARB_MST_CHOISE_PUSH_OFST_13 0x5E8AD8
+
+#define mmDMA7_QM_ARB_MST_CHOISE_PUSH_OFST_14 0x5E8ADC
+
+#define mmDMA7_QM_ARB_MST_CHOISE_PUSH_OFST_15 0x5E8AE0
+
+#define mmDMA7_QM_ARB_MST_CHOISE_PUSH_OFST_16 0x5E8AE4
+
+#define mmDMA7_QM_ARB_MST_CHOISE_PUSH_OFST_17 0x5E8AE8
+
+#define mmDMA7_QM_ARB_MST_CHOISE_PUSH_OFST_18 0x5E8AEC
+
+#define mmDMA7_QM_ARB_MST_CHOISE_PUSH_OFST_19 0x5E8AF0
+
+#define mmDMA7_QM_ARB_MST_CHOISE_PUSH_OFST_20 0x5E8AF4
+
+#define mmDMA7_QM_ARB_MST_CHOISE_PUSH_OFST_21 0x5E8AF8
+
+#define mmDMA7_QM_ARB_MST_CHOISE_PUSH_OFST_22 0x5E8AFC
+
+#define mmDMA7_QM_ARB_MST_CHOISE_PUSH_OFST_23 0x5E8B00
+
+#define mmDMA7_QM_ARB_MST_CHOISE_PUSH_OFST_24 0x5E8B04
+
+#define mmDMA7_QM_ARB_MST_CHOISE_PUSH_OFST_25 0x5E8B08
+
+#define mmDMA7_QM_ARB_MST_CHOISE_PUSH_OFST_26 0x5E8B0C
+
+#define mmDMA7_QM_ARB_MST_CHOISE_PUSH_OFST_27 0x5E8B10
+
+#define mmDMA7_QM_ARB_MST_CHOISE_PUSH_OFST_28 0x5E8B14
+
+#define mmDMA7_QM_ARB_MST_CHOISE_PUSH_OFST_29 0x5E8B18
+
+#define mmDMA7_QM_ARB_MST_CHOISE_PUSH_OFST_30 0x5E8B1C
+
+#define mmDMA7_QM_ARB_MST_CHOISE_PUSH_OFST_31 0x5E8B20
+
+#define mmDMA7_QM_ARB_SLV_MASTER_INC_CRED_OFST 0x5E8B28
+
+#define mmDMA7_QM_ARB_MST_SLAVE_EN 0x5E8B2C
+
+#define mmDMA7_QM_ARB_MST_QUIET_PER 0x5E8B34
+
+#define mmDMA7_QM_ARB_SLV_CHOISE_WDT 0x5E8B38
+
+#define mmDMA7_QM_ARB_SLV_ID 0x5E8B3C
+
+#define mmDMA7_QM_ARB_MSG_MAX_INFLIGHT 0x5E8B44
+
+#define mmDMA7_QM_ARB_MSG_AWUSER_31_11 0x5E8B48
+
+#define mmDMA7_QM_ARB_MSG_AWUSER_SEC_PROP 0x5E8B4C
+
+#define mmDMA7_QM_ARB_MSG_AWUSER_NON_SEC_PROP 0x5E8B50
+
+#define mmDMA7_QM_ARB_BASE_LO 0x5E8B54
+
+#define mmDMA7_QM_ARB_BASE_HI 0x5E8B58
+
+#define mmDMA7_QM_ARB_STATE_STS 0x5E8B80
+
+#define mmDMA7_QM_ARB_CHOISE_FULLNESS_STS 0x5E8B84
+
+#define mmDMA7_QM_ARB_MSG_STS 0x5E8B88
+
+#define mmDMA7_QM_ARB_SLV_CHOISE_Q_HEAD 0x5E8B8C
+
+#define mmDMA7_QM_ARB_ERR_CAUSE 0x5E8B9C
+
+#define mmDMA7_QM_ARB_ERR_MSG_EN 0x5E8BA0
+
+#define mmDMA7_QM_ARB_ERR_STS_DRP 0x5E8BA8
+
+#define mmDMA7_QM_ARB_MST_CRED_STS_0 0x5E8BB0
+
+#define mmDMA7_QM_ARB_MST_CRED_STS_1 0x5E8BB4
+
+#define mmDMA7_QM_ARB_MST_CRED_STS_2 0x5E8BB8
+
+#define mmDMA7_QM_ARB_MST_CRED_STS_3 0x5E8BBC
+
+#define mmDMA7_QM_ARB_MST_CRED_STS_4 0x5E8BC0
+
+#define mmDMA7_QM_ARB_MST_CRED_STS_5 0x5E8BC4
+
+#define mmDMA7_QM_ARB_MST_CRED_STS_6 0x5E8BC8
+
+#define mmDMA7_QM_ARB_MST_CRED_STS_7 0x5E8BCC
+
+#define mmDMA7_QM_ARB_MST_CRED_STS_8 0x5E8BD0
+
+#define mmDMA7_QM_ARB_MST_CRED_STS_9 0x5E8BD4
+
+#define mmDMA7_QM_ARB_MST_CRED_STS_10 0x5E8BD8
+
+#define mmDMA7_QM_ARB_MST_CRED_STS_11 0x5E8BDC
+
+#define mmDMA7_QM_ARB_MST_CRED_STS_12 0x5E8BE0
+
+#define mmDMA7_QM_ARB_MST_CRED_STS_13 0x5E8BE4
+
+#define mmDMA7_QM_ARB_MST_CRED_STS_14 0x5E8BE8
+
+#define mmDMA7_QM_ARB_MST_CRED_STS_15 0x5E8BEC
+
+#define mmDMA7_QM_ARB_MST_CRED_STS_16 0x5E8BF0
+
+#define mmDMA7_QM_ARB_MST_CRED_STS_17 0x5E8BF4
+
+#define mmDMA7_QM_ARB_MST_CRED_STS_18 0x5E8BF8
+
+#define mmDMA7_QM_ARB_MST_CRED_STS_19 0x5E8BFC
+
+#define mmDMA7_QM_ARB_MST_CRED_STS_20 0x5E8C00
+
+#define mmDMA7_QM_ARB_MST_CRED_STS_21 0x5E8C04
+
+#define mmDMA7_QM_ARB_MST_CRED_STS_22 0x5E8C08
+
+#define mmDMA7_QM_ARB_MST_CRED_STS_23 0x5E8C0C
+
+#define mmDMA7_QM_ARB_MST_CRED_STS_24 0x5E8C10
+
+#define mmDMA7_QM_ARB_MST_CRED_STS_25 0x5E8C14
+
+#define mmDMA7_QM_ARB_MST_CRED_STS_26 0x5E8C18
+
+#define mmDMA7_QM_ARB_MST_CRED_STS_27 0x5E8C1C
+
+#define mmDMA7_QM_ARB_MST_CRED_STS_28 0x5E8C20
+
+#define mmDMA7_QM_ARB_MST_CRED_STS_29 0x5E8C24
+
+#define mmDMA7_QM_ARB_MST_CRED_STS_30 0x5E8C28
+
+#define mmDMA7_QM_ARB_MST_CRED_STS_31 0x5E8C2C
+
+#define mmDMA7_QM_CGM_CFG 0x5E8C70
+
+#define mmDMA7_QM_CGM_STS 0x5E8C74
+
+#define mmDMA7_QM_CGM_CFG1 0x5E8C78
+
+#define mmDMA7_QM_LOCAL_RANGE_BASE 0x5E8C80
+
+#define mmDMA7_QM_LOCAL_RANGE_SIZE 0x5E8C84
+
+#define mmDMA7_QM_CSMR_STRICT_PRIO_CFG 0x5E8C90
+
+#define mmDMA7_QM_HBW_RD_RATE_LIM_CFG_1 0x5E8C94
+
+#define mmDMA7_QM_LBW_WR_RATE_LIM_CFG_0 0x5E8C98
+
+#define mmDMA7_QM_LBW_WR_RATE_LIM_CFG_1 0x5E8C9C
+
+#define mmDMA7_QM_HBW_RD_RATE_LIM_CFG_0 0x5E8CA0
+
+#define mmDMA7_QM_GLBL_AXCACHE 0x5E8CA4
+
+#define mmDMA7_QM_IND_GW_APB_CFG 0x5E8CB0
+
+#define mmDMA7_QM_IND_GW_APB_WDATA 0x5E8CB4
+
+#define mmDMA7_QM_IND_GW_APB_RDATA 0x5E8CB8
+
+#define mmDMA7_QM_IND_GW_APB_STATUS 0x5E8CBC
+
+#define mmDMA7_QM_GLBL_ERR_ADDR_LO 0x5E8CD0
+
+#define mmDMA7_QM_GLBL_ERR_ADDR_HI 0x5E8CD4
+
+#define mmDMA7_QM_GLBL_ERR_WDATA 0x5E8CD8
+
+#define mmDMA7_QM_GLBL_MEM_INIT_BUSY 0x5E8D00
+
+#endif /* ASIC_REG_DMA7_QM_REGS_H_ */
diff --git a/drivers/accel/habanalabs/include/gaudi/asic_reg/dma_if_e_n_down_ch0_regs.h b/drivers/accel/habanalabs/include/gaudi/asic_reg/dma_if_e_n_down_ch0_regs.h
new file mode 100644
index 0000000000..8c1c72df44
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi/asic_reg/dma_if_e_n_down_ch0_regs.h
@@ -0,0 +1,896 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2016-2018 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ ** DO NOT EDIT BELOW **
+ ************************************/
+
+#ifndef ASIC_REG_DMA_IF_E_N_DOWN_CH0_REGS_H_
+#define ASIC_REG_DMA_IF_E_N_DOWN_CH0_REGS_H_
+
+/*
+ *****************************************
+ * DMA_IF_E_N_DOWN_CH0 (Prototype: RTR_CTRL)
+ *****************************************
+ */
+
+#define mmDMA_IF_E_N_DOWN_CH0_PERM_SEL 0x4E1108
+
+#define mmDMA_IF_E_N_DOWN_CH0_HBM_POLY_H3_0 0x4E1114
+
+#define mmDMA_IF_E_N_DOWN_CH0_HBM_POLY_H3_1 0x4E1118
+
+#define mmDMA_IF_E_N_DOWN_CH0_HBM_POLY_H3_2 0x4E111C
+
+#define mmDMA_IF_E_N_DOWN_CH0_HBM_POLY_H3_3 0x4E1120
+
+#define mmDMA_IF_E_N_DOWN_CH0_HBM_POLY_H3_4 0x4E1124
+
+#define mmDMA_IF_E_N_DOWN_CH0_HBM_POLY_H3_5 0x4E1128
+
+#define mmDMA_IF_E_N_DOWN_CH0_HBM_POLY_H3_6 0x4E112C
+
+#define mmDMA_IF_E_N_DOWN_CH0_HBM_POLY_H3_7 0x4E1130
+
+#define mmDMA_IF_E_N_DOWN_CH0_HBM_POLY_H3_8 0x4E1134
+
+#define mmDMA_IF_E_N_DOWN_CH0_HBM_POLY_H3_9 0x4E1138
+
+#define mmDMA_IF_E_N_DOWN_CH0_HBM_POLY_H3_10 0x4E113C
+
+#define mmDMA_IF_E_N_DOWN_CH0_HBM_POLY_H3_11 0x4E1140
+
+#define mmDMA_IF_E_N_DOWN_CH0_HBM_POLY_H3_12 0x4E1144
+
+#define mmDMA_IF_E_N_DOWN_CH0_HBM_POLY_H3_13 0x4E1148
+
+#define mmDMA_IF_E_N_DOWN_CH0_HBM_POLY_H3_14 0x4E114C
+
+#define mmDMA_IF_E_N_DOWN_CH0_HBM_POLY_H3_15 0x4E1150
+
+#define mmDMA_IF_E_N_DOWN_CH0_HBM_POLY_H3_16 0x4E1154
+
+#define mmDMA_IF_E_N_DOWN_CH0_HBM_POLY_H3_17 0x4E1158
+
+#define mmDMA_IF_E_N_DOWN_CH0_HBM_POLY_H3_18 0x4E115C
+
+#define mmDMA_IF_E_N_DOWN_CH0_HBM_POLY_H3_19 0x4E1160
+
+#define mmDMA_IF_E_N_DOWN_CH0_HBM_POLY_H3_20 0x4E1164
+
+#define mmDMA_IF_E_N_DOWN_CH0_HBM_POLY_H3_21 0x4E1168
+
+#define mmDMA_IF_E_N_DOWN_CH0_HBM_POLY_H3_22 0x4E116C
+
+#define mmDMA_IF_E_N_DOWN_CH0_HBM_POLY_H3_23 0x4E1170
+
+#define mmDMA_IF_E_N_DOWN_CH0_HBM_POLY_H3_24 0x4E1174
+
+#define mmDMA_IF_E_N_DOWN_CH0_HBM_POLY_H3_25 0x4E1178
+
+#define mmDMA_IF_E_N_DOWN_CH0_HBM_POLY_H3_26 0x4E117C
+
+#define mmDMA_IF_E_N_DOWN_CH0_HBM_POLY_H3_27 0x4E1180
+
+#define mmDMA_IF_E_N_DOWN_CH0_SRAM_POLY_H3_0 0x4E1184
+
+#define mmDMA_IF_E_N_DOWN_CH0_SRAM_POLY_H3_1 0x4E1188
+
+#define mmDMA_IF_E_N_DOWN_CH0_SRAM_POLY_H3_2 0x4E118C
+
+#define mmDMA_IF_E_N_DOWN_CH0_SRAM_POLY_H3_3 0x4E1190
+
+#define mmDMA_IF_E_N_DOWN_CH0_SRAM_POLY_H3_4 0x4E1194
+
+#define mmDMA_IF_E_N_DOWN_CH0_SRAM_POLY_H3_5 0x4E1198
+
+#define mmDMA_IF_E_N_DOWN_CH0_SRAM_POLY_H3_6 0x4E119C
+
+#define mmDMA_IF_E_N_DOWN_CH0_SRAM_POLY_H3_7 0x4E11A0
+
+#define mmDMA_IF_E_N_DOWN_CH0_SRAM_POLY_H3_8 0x4E11A4
+
+#define mmDMA_IF_E_N_DOWN_CH0_SRAM_POLY_H3_9 0x4E11A8
+
+#define mmDMA_IF_E_N_DOWN_CH0_SRAM_POLY_H3_10 0x4E11AC
+
+#define mmDMA_IF_E_N_DOWN_CH0_SRAM_POLY_H3_11 0x4E11B0
+
+#define mmDMA_IF_E_N_DOWN_CH0_SRAM_POLY_H3_12 0x4E11B4
+
+#define mmDMA_IF_E_N_DOWN_CH0_SRAM_POLY_H3_13 0x4E11B8
+
+#define mmDMA_IF_E_N_DOWN_CH0_SRAM_POLY_H3_14 0x4E11BC
+
+#define mmDMA_IF_E_N_DOWN_CH0_SCRAM_SRAM_EN 0x4E126C
+
+#define mmDMA_IF_E_N_DOWN_CH0_RL_HBM_EN 0x4E1274
+
+#define mmDMA_IF_E_N_DOWN_CH0_RL_HBM_SAT 0x4E1278
+
+#define mmDMA_IF_E_N_DOWN_CH0_RL_HBM_RST 0x4E127C
+
+#define mmDMA_IF_E_N_DOWN_CH0_RL_HBM_TIMEOUT 0x4E1280
+
+#define mmDMA_IF_E_N_DOWN_CH0_SCRAM_HBM_EN 0x4E1284
+
+#define mmDMA_IF_E_N_DOWN_CH0_RL_PCI_EN 0x4E1288
+
+#define mmDMA_IF_E_N_DOWN_CH0_RL_PCI_SAT 0x4E128C
+
+#define mmDMA_IF_E_N_DOWN_CH0_RL_PCI_RST 0x4E1290
+
+#define mmDMA_IF_E_N_DOWN_CH0_RL_PCI_TIMEOUT 0x4E1294
+
+#define mmDMA_IF_E_N_DOWN_CH0_RL_SRAM_EN 0x4E129C
+
+#define mmDMA_IF_E_N_DOWN_CH0_RL_SRAM_SAT 0x4E12A0
+
+#define mmDMA_IF_E_N_DOWN_CH0_RL_SRAM_RST 0x4E12A4
+
+#define mmDMA_IF_E_N_DOWN_CH0_RL_SRAM_TIMEOUT 0x4E12AC
+
+#define mmDMA_IF_E_N_DOWN_CH0_RL_SRAM_RED 0x4E12B4
+
+#define mmDMA_IF_E_N_DOWN_CH0_E2E_HBM_EN 0x4E12EC
+
+#define mmDMA_IF_E_N_DOWN_CH0_E2E_PCI_EN 0x4E12F0
+
+#define mmDMA_IF_E_N_DOWN_CH0_E2E_HBM_WR_SIZE 0x4E12F4
+
+#define mmDMA_IF_E_N_DOWN_CH0_E2E_PCI_WR_SIZE 0x4E12F8
+
+#define mmDMA_IF_E_N_DOWN_CH0_E2E_AW_PCI_CTR_SET_EN 0x4E1404
+
+#define mmDMA_IF_E_N_DOWN_CH0_E2E_AW_PCI_CTR_SET 0x4E1408
+
+#define mmDMA_IF_E_N_DOWN_CH0_E2E_AW_PCI_CTR_WRAP 0x4E140C
+
+#define mmDMA_IF_E_N_DOWN_CH0_E2E_AW_PCI_CTR_CNT 0x4E1410
+
+#define mmDMA_IF_E_N_DOWN_CH0_E2E_AW_HBM_CTR_SET_EN 0x4E1414
+
+#define mmDMA_IF_E_N_DOWN_CH0_E2E_AW_HBM_CTR_SET 0x4E1418
+
+#define mmDMA_IF_E_N_DOWN_CH0_E2E_HBM_RD_SIZE 0x4E141C
+
+#define mmDMA_IF_E_N_DOWN_CH0_E2E_PCI_RD_SIZE 0x4E1420
+
+#define mmDMA_IF_E_N_DOWN_CH0_E2E_AR_PCI_CTR_SET_EN 0x4E1424
+
+#define mmDMA_IF_E_N_DOWN_CH0_E2E_AR_PCI_CTR_SET 0x4E1428
+
+#define mmDMA_IF_E_N_DOWN_CH0_E2E_AR_PCI_CTR_WRAP 0x4E142C
+
+#define mmDMA_IF_E_N_DOWN_CH0_E2E_AR_PCI_CTR_CNT 0x4E1430
+
+#define mmDMA_IF_E_N_DOWN_CH0_E2E_AR_HBM_CTR_SET_EN 0x4E1434
+
+#define mmDMA_IF_E_N_DOWN_CH0_E2E_AR_HBM_CTR_SET 0x4E1438
+
+#define mmDMA_IF_E_N_DOWN_CH0_NL_HBM_SEL_0 0x4E1450
+
+#define mmDMA_IF_E_N_DOWN_CH0_NL_HBM_SEL_1 0x4E1454
+
+#define mmDMA_IF_E_N_DOWN_CH0_NON_LIN_EN 0x4E1480
+
+#define mmDMA_IF_E_N_DOWN_CH0_NL_SRAM_BANK_0 0x4E1500
+
+#define mmDMA_IF_E_N_DOWN_CH0_NL_SRAM_BANK_1 0x4E1504
+
+#define mmDMA_IF_E_N_DOWN_CH0_NL_SRAM_BANK_2 0x4E1508
+
+#define mmDMA_IF_E_N_DOWN_CH0_NL_SRAM_BANK_3 0x4E150C
+
+#define mmDMA_IF_E_N_DOWN_CH0_NL_SRAM_BANK_4 0x4E1510
+
+#define mmDMA_IF_E_N_DOWN_CH0_NL_SRAM_OFFSET_0 0x4E1514
+
+#define mmDMA_IF_E_N_DOWN_CH0_NL_SRAM_OFFSET_1 0x4E1520
+
+#define mmDMA_IF_E_N_DOWN_CH0_NL_SRAM_OFFSET_2 0x4E1524
+
+#define mmDMA_IF_E_N_DOWN_CH0_NL_SRAM_OFFSET_3 0x4E1528
+
+#define mmDMA_IF_E_N_DOWN_CH0_NL_SRAM_OFFSET_4 0x4E152C
+
+#define mmDMA_IF_E_N_DOWN_CH0_NL_SRAM_OFFSET_5 0x4E1530
+
+#define mmDMA_IF_E_N_DOWN_CH0_NL_SRAM_OFFSET_6 0x4E1534
+
+#define mmDMA_IF_E_N_DOWN_CH0_NL_SRAM_OFFSET_7 0x4E1538
+
+#define mmDMA_IF_E_N_DOWN_CH0_NL_SRAM_OFFSET_8 0x4E153C
+
+#define mmDMA_IF_E_N_DOWN_CH0_NL_SRAM_OFFSET_9 0x4E1540
+
+#define mmDMA_IF_E_N_DOWN_CH0_NL_HBM_OFFSET_0 0x4E1550
+
+#define mmDMA_IF_E_N_DOWN_CH0_NL_HBM_OFFSET_1 0x4E1554
+
+#define mmDMA_IF_E_N_DOWN_CH0_NL_HBM_OFFSET_2 0x4E1558
+
+#define mmDMA_IF_E_N_DOWN_CH0_NL_HBM_OFFSET_3 0x4E155C
+
+#define mmDMA_IF_E_N_DOWN_CH0_NL_HBM_OFFSET_4 0x4E1560
+
+#define mmDMA_IF_E_N_DOWN_CH0_NL_HBM_OFFSET_5 0x4E1564
+
+#define mmDMA_IF_E_N_DOWN_CH0_NL_HBM_OFFSET_6 0x4E1568
+
+#define mmDMA_IF_E_N_DOWN_CH0_NL_HBM_OFFSET_7 0x4E156C
+
+#define mmDMA_IF_E_N_DOWN_CH0_NL_HBM_OFFSET_8 0x4E1570
+
+#define mmDMA_IF_E_N_DOWN_CH0_NL_HBM_OFFSET_9 0x4E1574
+
+#define mmDMA_IF_E_N_DOWN_CH0_NL_HBM_OFFSET_10 0x4E1578
+
+#define mmDMA_IF_E_N_DOWN_CH0_NL_HBM_OFFSET_11 0x4E157C
+
+#define mmDMA_IF_E_N_DOWN_CH0_NL_HBM_OFFSET_12 0x4E1580
+
+#define mmDMA_IF_E_N_DOWN_CH0_NL_HBM_OFFSET_13 0x4E1584
+
+#define mmDMA_IF_E_N_DOWN_CH0_NL_HBM_OFFSET_14 0x4E1588
+
+#define mmDMA_IF_E_N_DOWN_CH0_NL_HBM_OFFSET_15 0x4E158C
+
+#define mmDMA_IF_E_N_DOWN_CH0_NL_HBM_OFFSET_16 0x4E1590
+
+#define mmDMA_IF_E_N_DOWN_CH0_NL_HBM_OFFSET_17 0x4E1594
+
+#define mmDMA_IF_E_N_DOWN_CH0_NL_HBM_OFFSET_18 0x4E1598
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_0 0x4E15E4
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_1 0x4E15E8
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_2 0x4E15EC
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_3 0x4E15F0
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_4 0x4E15F4
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_5 0x4E15F8
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_6 0x4E15FC
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_7 0x4E1600
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_8 0x4E1604
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_9 0x4E1608
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_10 0x4E160C
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_11 0x4E1610
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_12 0x4E1614
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_13 0x4E1618
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_14 0x4E161C
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_15 0x4E1620
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_0 0x4E1624
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_1 0x4E1628
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_2 0x4E162C
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_3 0x4E1630
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_4 0x4E1634
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_5 0x4E1638
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_6 0x4E163C
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_7 0x4E1640
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_8 0x4E1644
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_9 0x4E1648
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_10 0x4E164C
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_11 0x4E1650
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_12 0x4E1654
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_13 0x4E1658
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_14 0x4E165C
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_15 0x4E1660
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_0 0x4E1664
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_1 0x4E1668
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_2 0x4E166C
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_3 0x4E1670
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_4 0x4E1674
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_5 0x4E1678
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_6 0x4E167C
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_7 0x4E1680
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_8 0x4E1684
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_9 0x4E1688
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_10 0x4E168C
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_11 0x4E1690
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_12 0x4E1694
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_13 0x4E1698
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_14 0x4E169C
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_15 0x4E16A0
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_0 0x4E16A4
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_1 0x4E16A8
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_2 0x4E16AC
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_3 0x4E16B0
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_4 0x4E16B4
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_5 0x4E16B8
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_6 0x4E16BC
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_7 0x4E16C0
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_8 0x4E16C4
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_9 0x4E16C8
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_10 0x4E16CC
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_11 0x4E16D0
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_12 0x4E16D4
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_13 0x4E16D8
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_14 0x4E16DC
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_15 0x4E16E0
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_0 0x4E16E4
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_1 0x4E16E8
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_2 0x4E16EC
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_3 0x4E16F0
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_4 0x4E16F4
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_5 0x4E16F8
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_6 0x4E16FC
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_7 0x4E1700
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_8 0x4E1704
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_9 0x4E1708
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_10 0x4E170C
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_11 0x4E1710
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_12 0x4E1714
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_13 0x4E1718
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_14 0x4E171C
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_15 0x4E1720
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_0 0x4E1724
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_1 0x4E1728
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_2 0x4E172C
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_3 0x4E1730
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_4 0x4E1734
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_5 0x4E1738
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_6 0x4E173C
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_7 0x4E1740
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_8 0x4E1744
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_9 0x4E1748
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_10 0x4E174C
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_11 0x4E1750
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_12 0x4E1754
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_13 0x4E1758
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_14 0x4E175C
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_15 0x4E1760
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_0 0x4E1764
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_1 0x4E1768
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_2 0x4E176C
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_3 0x4E1770
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_4 0x4E1774
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_5 0x4E1778
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_6 0x4E177C
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_7 0x4E1780
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_8 0x4E1784
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_9 0x4E1788
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_10 0x4E178C
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_11 0x4E1790
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_12 0x4E1794
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_13 0x4E1798
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_14 0x4E179C
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_15 0x4E17A0
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_0 0x4E17A4
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_1 0x4E17A8
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_2 0x4E17AC
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_3 0x4E17B0
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_4 0x4E17B4
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_5 0x4E17B8
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_6 0x4E17BC
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_7 0x4E17C0
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_8 0x4E17C4
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_9 0x4E17C8
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_10 0x4E17CC
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_11 0x4E17D0
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_12 0x4E17D4
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_13 0x4E17D8
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_14 0x4E17DC
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_15 0x4E17E0
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_0 0x4E1824
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_1 0x4E1828
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_2 0x4E182C
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_3 0x4E1830
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_4 0x4E1834
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_5 0x4E1838
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_6 0x4E183C
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_7 0x4E1840
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_8 0x4E1844
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_9 0x4E1848
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_10 0x4E184C
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_11 0x4E1850
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_12 0x4E1854
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_13 0x4E1858
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_14 0x4E185C
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_15 0x4E1860
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_0 0x4E1864
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_1 0x4E1868
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_2 0x4E186C
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_3 0x4E1870
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_4 0x4E1874
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_5 0x4E1878
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_6 0x4E187C
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_7 0x4E1880
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_8 0x4E1884
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_9 0x4E1888
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_10 0x4E188C
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_11 0x4E1890
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_12 0x4E1894
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_13 0x4E1898
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_14 0x4E189C
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_15 0x4E18A0
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_0 0x4E18A4
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_1 0x4E18A8
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_2 0x4E18AC
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_3 0x4E18B0
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_4 0x4E18B4
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_5 0x4E18B8
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_6 0x4E18BC
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_7 0x4E18C0
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_8 0x4E18C4
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_9 0x4E18C8
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_10 0x4E18CC
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_11 0x4E18D0
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_12 0x4E18D4
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_13 0x4E18D8
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_14 0x4E18DC
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_15 0x4E18E0
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_0 0x4E18E4
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_1 0x4E18E8
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_2 0x4E18EC
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_3 0x4E18F0
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_4 0x4E18F4
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_5 0x4E18F8
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_6 0x4E18FC
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_7 0x4E1900
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_8 0x4E1904
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_9 0x4E1908
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_10 0x4E190C
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_11 0x4E1910
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_12 0x4E1914
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_13 0x4E1918
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_14 0x4E191C
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_15 0x4E1920
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_0 0x4E1924
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_1 0x4E1928
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_2 0x4E192C
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_3 0x4E1930
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_4 0x4E1934
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_5 0x4E1938
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_6 0x4E193C
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_7 0x4E1940
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_8 0x4E1944
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_9 0x4E1948
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_10 0x4E194C
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_11 0x4E1950
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_12 0x4E1954
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_13 0x4E1958
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_14 0x4E195C
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_15 0x4E1960
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_0 0x4E1964
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_1 0x4E1968
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_2 0x4E196C
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_3 0x4E1970
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_4 0x4E1974
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_5 0x4E1978
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_6 0x4E197C
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_7 0x4E1980
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_8 0x4E1984
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_9 0x4E1988
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_10 0x4E198C
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_11 0x4E1990
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_12 0x4E1994
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_13 0x4E1998
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_14 0x4E199C
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_15 0x4E19A0
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_0 0x4E19A4
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_1 0x4E19A8
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_2 0x4E19AC
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_3 0x4E19B0
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_4 0x4E19B4
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_5 0x4E19B8
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_6 0x4E19BC
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_7 0x4E19C0
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_8 0x4E19C4
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_9 0x4E19C8
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_10 0x4E19CC
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_11 0x4E19D0
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_12 0x4E19D4
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_13 0x4E19D8
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_14 0x4E19DC
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_15 0x4E19E0
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_0 0x4E19E4
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_1 0x4E19E8
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_2 0x4E19EC
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_3 0x4E19F0
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_4 0x4E19F4
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_5 0x4E19F8
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_6 0x4E19FC
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_7 0x4E1A00
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_8 0x4E1A04
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_9 0x4E1A08
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_10 0x4E1A0C
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_11 0x4E1A10
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_12 0x4E1A14
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_13 0x4E1A18
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_14 0x4E1A1C
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_15 0x4E1A20
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_HIT_AW 0x4E1A64
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_HIT_AR 0x4E1A68
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_HIT_AW 0x4E1A6C
+
+#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_HIT_AR 0x4E1A70
+
+#define mmDMA_IF_E_N_DOWN_CH0_RGL_CFG 0x4E1B64
+
+#define mmDMA_IF_E_N_DOWN_CH0_RGL_SHIFT 0x4E1B68
+
+#define mmDMA_IF_E_N_DOWN_CH0_RGL_EXPECTED_LAT_0 0x4E1B6C
+
+#define mmDMA_IF_E_N_DOWN_CH0_RGL_EXPECTED_LAT_1 0x4E1B70
+
+#define mmDMA_IF_E_N_DOWN_CH0_RGL_EXPECTED_LAT_2 0x4E1B74
+
+#define mmDMA_IF_E_N_DOWN_CH0_RGL_EXPECTED_LAT_3 0x4E1B78
+
+#define mmDMA_IF_E_N_DOWN_CH0_RGL_EXPECTED_LAT_4 0x4E1B7C
+
+#define mmDMA_IF_E_N_DOWN_CH0_RGL_EXPECTED_LAT_5 0x4E1B80
+
+#define mmDMA_IF_E_N_DOWN_CH0_RGL_EXPECTED_LAT_6 0x4E1B84
+
+#define mmDMA_IF_E_N_DOWN_CH0_RGL_EXPECTED_LAT_7 0x4E1B88
+
+#define mmDMA_IF_E_N_DOWN_CH0_RGL_TOKEN_0 0x4E1BAC
+
+#define mmDMA_IF_E_N_DOWN_CH0_RGL_TOKEN_1 0x4E1BB0
+
+#define mmDMA_IF_E_N_DOWN_CH0_RGL_TOKEN_2 0x4E1BB4
+
+#define mmDMA_IF_E_N_DOWN_CH0_RGL_TOKEN_3 0x4E1BB8
+
+#define mmDMA_IF_E_N_DOWN_CH0_RGL_TOKEN_4 0x4E1BBC
+
+#define mmDMA_IF_E_N_DOWN_CH0_RGL_TOKEN_5 0x4E1BC0
+
+#define mmDMA_IF_E_N_DOWN_CH0_RGL_TOKEN_6 0x4E1BC4
+
+#define mmDMA_IF_E_N_DOWN_CH0_RGL_TOKEN_7 0x4E1BC8
+
+#define mmDMA_IF_E_N_DOWN_CH0_RGL_BANK_ID_0 0x4E1BEC
+
+#define mmDMA_IF_E_N_DOWN_CH0_RGL_BANK_ID_1 0x4E1BF0
+
+#define mmDMA_IF_E_N_DOWN_CH0_RGL_BANK_ID_2 0x4E1BF4
+
+#define mmDMA_IF_E_N_DOWN_CH0_RGL_BANK_ID_3 0x4E1BF8
+
+#define mmDMA_IF_E_N_DOWN_CH0_RGL_BANK_ID_4 0x4E1BFC
+
+#define mmDMA_IF_E_N_DOWN_CH0_RGL_BANK_ID_5 0x4E1C00
+
+#define mmDMA_IF_E_N_DOWN_CH0_RGL_BANK_ID_6 0x4E1C04
+
+#define mmDMA_IF_E_N_DOWN_CH0_RGL_BANK_ID_7 0x4E1C08
+
+#define mmDMA_IF_E_N_DOWN_CH0_RGL_WDT 0x4E1C2C
+
+#define mmDMA_IF_E_N_DOWN_CH0_E2E_AR_HBM0_CH0_CTR_WRAP 0x4E1C30
+
+#define mmDMA_IF_E_N_DOWN_CH0_E2E_AR_HBM0_CH1_CTR_WRAP 0x4E1C34
+
+#define mmDMA_IF_E_N_DOWN_CH0_E2E_AR_HBM1_CH0_CTR_WRAP 0x4E1C38
+
+#define mmDMA_IF_E_N_DOWN_CH0_E2E_AR_HBM1_CH1_CTR_WRAP 0x4E1C3C
+
+#define mmDMA_IF_E_N_DOWN_CH0_E2E_AR_HBM2_CH0_CTR_WRAP 0x4E1C40
+
+#define mmDMA_IF_E_N_DOWN_CH0_E2E_AR_HBM2_CH1_CTR_WRAP 0x4E1C44
+
+#define mmDMA_IF_E_N_DOWN_CH0_E2E_AR_HBM3_CH0_CTR_WRAP 0x4E1C48
+
+#define mmDMA_IF_E_N_DOWN_CH0_E2E_AR_HBM3_CH1_CTR_WRAP 0x4E1C4C
+
+#define mmDMA_IF_E_N_DOWN_CH0_E2E_AR_HBM0_CH0_CTR_CNT 0x4E1C50
+
+#define mmDMA_IF_E_N_DOWN_CH0_E2E_AR_HBM0_CH1_CTR_CNT 0x4E1C54
+
+#define mmDMA_IF_E_N_DOWN_CH0_E2E_AR_HBM1_CH0_CTR_CNT 0x4E1C58
+
+#define mmDMA_IF_E_N_DOWN_CH0_E2E_AR_HBM1_CH1_CTR_CNT 0x4E1C5C
+
+#define mmDMA_IF_E_N_DOWN_CH0_E2E_AR_HBM2_CH0_CTR_CNT 0x4E1C60
+
+#define mmDMA_IF_E_N_DOWN_CH0_E2E_AR_HBM2_CH1_CTR_CNT 0x4E1C64
+
+#define mmDMA_IF_E_N_DOWN_CH0_E2E_AR_HBM3_CH0_CTR_CNT 0x4E1C68
+
+#define mmDMA_IF_E_N_DOWN_CH0_E2E_AR_HBM3_CH1_CTR_CNT 0x4E1C6C
+
+#define mmDMA_IF_E_N_DOWN_CH0_E2E_AW_HBM0_CH0_CTR_WRAP 0x4E1C70
+
+#define mmDMA_IF_E_N_DOWN_CH0_E2E_AW_HBM0_CH1_CTR_WRAP 0x4E1C74
+
+#define mmDMA_IF_E_N_DOWN_CH0_E2E_AW_HBM1_CH0_CTR_WRAP 0x4E1C78
+
+#define mmDMA_IF_E_N_DOWN_CH0_E2E_AW_HBM1_CH1_CTR_WRAP 0x4E1C7C
+
+#define mmDMA_IF_E_N_DOWN_CH0_E2E_AW_HBM2_CH0_CTR_WRAP 0x4E1C80
+
+#define mmDMA_IF_E_N_DOWN_CH0_E2E_AW_HBM2_CH1_CTR_WRAP 0x4E1C84
+
+#define mmDMA_IF_E_N_DOWN_CH0_E2E_AW_HBM3_CH0_CTR_WRAP 0x4E1C88
+
+#define mmDMA_IF_E_N_DOWN_CH0_E2E_AW_HBM3_CH1_CTR_WRAP 0x4E1C8C
+
+#define mmDMA_IF_E_N_DOWN_CH0_E2E_AW_HBM0_CH0_CTR_CNT 0x4E1C90
+
+#define mmDMA_IF_E_N_DOWN_CH0_E2E_AW_HBM0_CH1_CTR_CNT 0x4E1C94
+
+#define mmDMA_IF_E_N_DOWN_CH0_E2E_AW_HBM1_CH0_CTR_CNT 0x4E1C98
+
+#define mmDMA_IF_E_N_DOWN_CH0_E2E_AW_HBM1_CH1_CTR_CNT 0x4E1C9C
+
+#define mmDMA_IF_E_N_DOWN_CH0_E2E_AW_HBM2_CH0_CTR_CNT 0x4E1CA0
+
+#define mmDMA_IF_E_N_DOWN_CH0_E2E_AW_HBM2_CH1_CTR_CNT 0x4E1CA4
+
+#define mmDMA_IF_E_N_DOWN_CH0_E2E_AW_HBM3_CH0_CTR_CNT 0x4E1CA8
+
+#define mmDMA_IF_E_N_DOWN_CH0_E2E_AW_HBM3_CH1_CTR_CNT 0x4E1CAC
+
+#define mmDMA_IF_E_N_DOWN_CH0_NL_HBM_PC_SEL_0 0x4E1CB0
+
+#define mmDMA_IF_E_N_DOWN_CH0_NL_HBM_PC_SEL_1 0x4E1CB4
+
+#define mmDMA_IF_E_N_DOWN_CH0_NL_HBM_PC_SEL_2 0x4E1CB8
+
+#define mmDMA_IF_E_N_DOWN_CH0_NL_HBM_PC_SEL_3 0x4E1CBC
+
+#endif /* ASIC_REG_DMA_IF_E_N_DOWN_CH0_REGS_H_ */
diff --git a/drivers/accel/habanalabs/include/gaudi/asic_reg/dma_if_e_n_down_ch1_regs.h b/drivers/accel/habanalabs/include/gaudi/asic_reg/dma_if_e_n_down_ch1_regs.h
new file mode 100644
index 0000000000..b2b593fcec
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi/asic_reg/dma_if_e_n_down_ch1_regs.h
@@ -0,0 +1,896 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2016-2018 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ ** DO NOT EDIT BELOW **
+ ************************************/
+
+#ifndef ASIC_REG_DMA_IF_E_N_DOWN_CH1_REGS_H_
+#define ASIC_REG_DMA_IF_E_N_DOWN_CH1_REGS_H_
+
+/*
+ *****************************************
+ * DMA_IF_E_N_DOWN_CH1 (Prototype: RTR_CTRL)
+ *****************************************
+ */
+
+#define mmDMA_IF_E_N_DOWN_CH1_PERM_SEL 0x4E2108
+
+#define mmDMA_IF_E_N_DOWN_CH1_HBM_POLY_H3_0 0x4E2114
+
+#define mmDMA_IF_E_N_DOWN_CH1_HBM_POLY_H3_1 0x4E2118
+
+#define mmDMA_IF_E_N_DOWN_CH1_HBM_POLY_H3_2 0x4E211C
+
+#define mmDMA_IF_E_N_DOWN_CH1_HBM_POLY_H3_3 0x4E2120
+
+#define mmDMA_IF_E_N_DOWN_CH1_HBM_POLY_H3_4 0x4E2124
+
+#define mmDMA_IF_E_N_DOWN_CH1_HBM_POLY_H3_5 0x4E2128
+
+#define mmDMA_IF_E_N_DOWN_CH1_HBM_POLY_H3_6 0x4E212C
+
+#define mmDMA_IF_E_N_DOWN_CH1_HBM_POLY_H3_7 0x4E2130
+
+#define mmDMA_IF_E_N_DOWN_CH1_HBM_POLY_H3_8 0x4E2134
+
+#define mmDMA_IF_E_N_DOWN_CH1_HBM_POLY_H3_9 0x4E2138
+
+#define mmDMA_IF_E_N_DOWN_CH1_HBM_POLY_H3_10 0x4E213C
+
+#define mmDMA_IF_E_N_DOWN_CH1_HBM_POLY_H3_11 0x4E2140
+
+#define mmDMA_IF_E_N_DOWN_CH1_HBM_POLY_H3_12 0x4E2144
+
+#define mmDMA_IF_E_N_DOWN_CH1_HBM_POLY_H3_13 0x4E2148
+
+#define mmDMA_IF_E_N_DOWN_CH1_HBM_POLY_H3_14 0x4E214C
+
+#define mmDMA_IF_E_N_DOWN_CH1_HBM_POLY_H3_15 0x4E2150
+
+#define mmDMA_IF_E_N_DOWN_CH1_HBM_POLY_H3_16 0x4E2154
+
+#define mmDMA_IF_E_N_DOWN_CH1_HBM_POLY_H3_17 0x4E2158
+
+#define mmDMA_IF_E_N_DOWN_CH1_HBM_POLY_H3_18 0x4E215C
+
+#define mmDMA_IF_E_N_DOWN_CH1_HBM_POLY_H3_19 0x4E2160
+
+#define mmDMA_IF_E_N_DOWN_CH1_HBM_POLY_H3_20 0x4E2164
+
+#define mmDMA_IF_E_N_DOWN_CH1_HBM_POLY_H3_21 0x4E2168
+
+#define mmDMA_IF_E_N_DOWN_CH1_HBM_POLY_H3_22 0x4E216C
+
+#define mmDMA_IF_E_N_DOWN_CH1_HBM_POLY_H3_23 0x4E2170
+
+#define mmDMA_IF_E_N_DOWN_CH1_HBM_POLY_H3_24 0x4E2174
+
+#define mmDMA_IF_E_N_DOWN_CH1_HBM_POLY_H3_25 0x4E2178
+
+#define mmDMA_IF_E_N_DOWN_CH1_HBM_POLY_H3_26 0x4E217C
+
+#define mmDMA_IF_E_N_DOWN_CH1_HBM_POLY_H3_27 0x4E2180
+
+#define mmDMA_IF_E_N_DOWN_CH1_SRAM_POLY_H3_0 0x4E2184
+
+#define mmDMA_IF_E_N_DOWN_CH1_SRAM_POLY_H3_1 0x4E2188
+
+#define mmDMA_IF_E_N_DOWN_CH1_SRAM_POLY_H3_2 0x4E218C
+
+#define mmDMA_IF_E_N_DOWN_CH1_SRAM_POLY_H3_3 0x4E2190
+
+#define mmDMA_IF_E_N_DOWN_CH1_SRAM_POLY_H3_4 0x4E2194
+
+#define mmDMA_IF_E_N_DOWN_CH1_SRAM_POLY_H3_5 0x4E2198
+
+#define mmDMA_IF_E_N_DOWN_CH1_SRAM_POLY_H3_6 0x4E219C
+
+#define mmDMA_IF_E_N_DOWN_CH1_SRAM_POLY_H3_7 0x4E21A0
+
+#define mmDMA_IF_E_N_DOWN_CH1_SRAM_POLY_H3_8 0x4E21A4
+
+#define mmDMA_IF_E_N_DOWN_CH1_SRAM_POLY_H3_9 0x4E21A8
+
+#define mmDMA_IF_E_N_DOWN_CH1_SRAM_POLY_H3_10 0x4E21AC
+
+#define mmDMA_IF_E_N_DOWN_CH1_SRAM_POLY_H3_11 0x4E21B0
+
+#define mmDMA_IF_E_N_DOWN_CH1_SRAM_POLY_H3_12 0x4E21B4
+
+#define mmDMA_IF_E_N_DOWN_CH1_SRAM_POLY_H3_13 0x4E21B8
+
+#define mmDMA_IF_E_N_DOWN_CH1_SRAM_POLY_H3_14 0x4E21BC
+
+#define mmDMA_IF_E_N_DOWN_CH1_SCRAM_SRAM_EN 0x4E226C
+
+#define mmDMA_IF_E_N_DOWN_CH1_RL_HBM_EN 0x4E2274
+
+#define mmDMA_IF_E_N_DOWN_CH1_RL_HBM_SAT 0x4E2278
+
+#define mmDMA_IF_E_N_DOWN_CH1_RL_HBM_RST 0x4E227C
+
+#define mmDMA_IF_E_N_DOWN_CH1_RL_HBM_TIMEOUT 0x4E2280
+
+#define mmDMA_IF_E_N_DOWN_CH1_SCRAM_HBM_EN 0x4E2284
+
+#define mmDMA_IF_E_N_DOWN_CH1_RL_PCI_EN 0x4E2288
+
+#define mmDMA_IF_E_N_DOWN_CH1_RL_PCI_SAT 0x4E228C
+
+#define mmDMA_IF_E_N_DOWN_CH1_RL_PCI_RST 0x4E2290
+
+#define mmDMA_IF_E_N_DOWN_CH1_RL_PCI_TIMEOUT 0x4E2294
+
+#define mmDMA_IF_E_N_DOWN_CH1_RL_SRAM_EN 0x4E229C
+
+#define mmDMA_IF_E_N_DOWN_CH1_RL_SRAM_SAT 0x4E22A0
+
+#define mmDMA_IF_E_N_DOWN_CH1_RL_SRAM_RST 0x4E22A4
+
+#define mmDMA_IF_E_N_DOWN_CH1_RL_SRAM_TIMEOUT 0x4E22AC
+
+#define mmDMA_IF_E_N_DOWN_CH1_RL_SRAM_RED 0x4E22B4
+
+#define mmDMA_IF_E_N_DOWN_CH1_E2E_HBM_EN 0x4E22EC
+
+#define mmDMA_IF_E_N_DOWN_CH1_E2E_PCI_EN 0x4E22F0
+
+#define mmDMA_IF_E_N_DOWN_CH1_E2E_HBM_WR_SIZE 0x4E22F4
+
+#define mmDMA_IF_E_N_DOWN_CH1_E2E_PCI_WR_SIZE 0x4E22F8
+
+#define mmDMA_IF_E_N_DOWN_CH1_E2E_AW_PCI_CTR_SET_EN 0x4E2404
+
+#define mmDMA_IF_E_N_DOWN_CH1_E2E_AW_PCI_CTR_SET 0x4E2408
+
+#define mmDMA_IF_E_N_DOWN_CH1_E2E_AW_PCI_CTR_WRAP 0x4E240C
+
+#define mmDMA_IF_E_N_DOWN_CH1_E2E_AW_PCI_CTR_CNT 0x4E2410
+
+#define mmDMA_IF_E_N_DOWN_CH1_E2E_AW_HBM_CTR_SET_EN 0x4E2414
+
+#define mmDMA_IF_E_N_DOWN_CH1_E2E_AW_HBM_CTR_SET 0x4E2418
+
+#define mmDMA_IF_E_N_DOWN_CH1_E2E_HBM_RD_SIZE 0x4E241C
+
+#define mmDMA_IF_E_N_DOWN_CH1_E2E_PCI_RD_SIZE 0x4E2420
+
+#define mmDMA_IF_E_N_DOWN_CH1_E2E_AR_PCI_CTR_SET_EN 0x4E2424
+
+#define mmDMA_IF_E_N_DOWN_CH1_E2E_AR_PCI_CTR_SET 0x4E2428
+
+#define mmDMA_IF_E_N_DOWN_CH1_E2E_AR_PCI_CTR_WRAP 0x4E242C
+
+#define mmDMA_IF_E_N_DOWN_CH1_E2E_AR_PCI_CTR_CNT 0x4E2430
+
+#define mmDMA_IF_E_N_DOWN_CH1_E2E_AR_HBM_CTR_SET_EN 0x4E2434
+
+#define mmDMA_IF_E_N_DOWN_CH1_E2E_AR_HBM_CTR_SET 0x4E2438
+
+#define mmDMA_IF_E_N_DOWN_CH1_NL_HBM_SEL_0 0x4E2450
+
+#define mmDMA_IF_E_N_DOWN_CH1_NL_HBM_SEL_1 0x4E2454
+
+#define mmDMA_IF_E_N_DOWN_CH1_NON_LIN_EN 0x4E2480
+
+#define mmDMA_IF_E_N_DOWN_CH1_NL_SRAM_BANK_0 0x4E2500
+
+#define mmDMA_IF_E_N_DOWN_CH1_NL_SRAM_BANK_1 0x4E2504
+
+#define mmDMA_IF_E_N_DOWN_CH1_NL_SRAM_BANK_2 0x4E2508
+
+#define mmDMA_IF_E_N_DOWN_CH1_NL_SRAM_BANK_3 0x4E250C
+
+#define mmDMA_IF_E_N_DOWN_CH1_NL_SRAM_BANK_4 0x4E2510
+
+#define mmDMA_IF_E_N_DOWN_CH1_NL_SRAM_OFFSET_0 0x4E2514
+
+#define mmDMA_IF_E_N_DOWN_CH1_NL_SRAM_OFFSET_1 0x4E2520
+
+#define mmDMA_IF_E_N_DOWN_CH1_NL_SRAM_OFFSET_2 0x4E2524
+
+#define mmDMA_IF_E_N_DOWN_CH1_NL_SRAM_OFFSET_3 0x4E2528
+
+#define mmDMA_IF_E_N_DOWN_CH1_NL_SRAM_OFFSET_4 0x4E252C
+
+#define mmDMA_IF_E_N_DOWN_CH1_NL_SRAM_OFFSET_5 0x4E2530
+
+#define mmDMA_IF_E_N_DOWN_CH1_NL_SRAM_OFFSET_6 0x4E2534
+
+#define mmDMA_IF_E_N_DOWN_CH1_NL_SRAM_OFFSET_7 0x4E2538
+
+#define mmDMA_IF_E_N_DOWN_CH1_NL_SRAM_OFFSET_8 0x4E253C
+
+#define mmDMA_IF_E_N_DOWN_CH1_NL_SRAM_OFFSET_9 0x4E2540
+
+#define mmDMA_IF_E_N_DOWN_CH1_NL_HBM_OFFSET_0 0x4E2550
+
+#define mmDMA_IF_E_N_DOWN_CH1_NL_HBM_OFFSET_1 0x4E2554
+
+#define mmDMA_IF_E_N_DOWN_CH1_NL_HBM_OFFSET_2 0x4E2558
+
+#define mmDMA_IF_E_N_DOWN_CH1_NL_HBM_OFFSET_3 0x4E255C
+
+#define mmDMA_IF_E_N_DOWN_CH1_NL_HBM_OFFSET_4 0x4E2560
+
+#define mmDMA_IF_E_N_DOWN_CH1_NL_HBM_OFFSET_5 0x4E2564
+
+#define mmDMA_IF_E_N_DOWN_CH1_NL_HBM_OFFSET_6 0x4E2568
+
+#define mmDMA_IF_E_N_DOWN_CH1_NL_HBM_OFFSET_7 0x4E256C
+
+#define mmDMA_IF_E_N_DOWN_CH1_NL_HBM_OFFSET_8 0x4E2570
+
+#define mmDMA_IF_E_N_DOWN_CH1_NL_HBM_OFFSET_9 0x4E2574
+
+#define mmDMA_IF_E_N_DOWN_CH1_NL_HBM_OFFSET_10 0x4E2578
+
+#define mmDMA_IF_E_N_DOWN_CH1_NL_HBM_OFFSET_11 0x4E257C
+
+#define mmDMA_IF_E_N_DOWN_CH1_NL_HBM_OFFSET_12 0x4E2580
+
+#define mmDMA_IF_E_N_DOWN_CH1_NL_HBM_OFFSET_13 0x4E2584
+
+#define mmDMA_IF_E_N_DOWN_CH1_NL_HBM_OFFSET_14 0x4E2588
+
+#define mmDMA_IF_E_N_DOWN_CH1_NL_HBM_OFFSET_15 0x4E258C
+
+#define mmDMA_IF_E_N_DOWN_CH1_NL_HBM_OFFSET_16 0x4E2590
+
+#define mmDMA_IF_E_N_DOWN_CH1_NL_HBM_OFFSET_17 0x4E2594
+
+#define mmDMA_IF_E_N_DOWN_CH1_NL_HBM_OFFSET_18 0x4E2598
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_0 0x4E25E4
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_1 0x4E25E8
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_2 0x4E25EC
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_3 0x4E25F0
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_4 0x4E25F4
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_5 0x4E25F8
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_6 0x4E25FC
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_7 0x4E2600
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_8 0x4E2604
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_9 0x4E2608
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_10 0x4E260C
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_11 0x4E2610
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_12 0x4E2614
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_13 0x4E2618
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_14 0x4E261C
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_15 0x4E2620
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_0 0x4E2624
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_1 0x4E2628
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_2 0x4E262C
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_3 0x4E2630
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_4 0x4E2634
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_5 0x4E2638
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_6 0x4E263C
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_7 0x4E2640
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_8 0x4E2644
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_9 0x4E2648
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_10 0x4E264C
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_11 0x4E2650
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_12 0x4E2654
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_13 0x4E2658
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_14 0x4E265C
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_15 0x4E2660
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_0 0x4E2664
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_1 0x4E2668
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_2 0x4E266C
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_3 0x4E2670
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_4 0x4E2674
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_5 0x4E2678
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_6 0x4E267C
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_7 0x4E2680
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_8 0x4E2684
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_9 0x4E2688
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_10 0x4E268C
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_11 0x4E2690
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_12 0x4E2694
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_13 0x4E2698
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_14 0x4E269C
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_15 0x4E26A0
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_0 0x4E26A4
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_1 0x4E26A8
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_2 0x4E26AC
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_3 0x4E26B0
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_4 0x4E26B4
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_5 0x4E26B8
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_6 0x4E26BC
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_7 0x4E26C0
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_8 0x4E26C4
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_9 0x4E26C8
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_10 0x4E26CC
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_11 0x4E26D0
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_12 0x4E26D4
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_13 0x4E26D8
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_14 0x4E26DC
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_15 0x4E26E0
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_0 0x4E26E4
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_1 0x4E26E8
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_2 0x4E26EC
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_3 0x4E26F0
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_4 0x4E26F4
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_5 0x4E26F8
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_6 0x4E26FC
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_7 0x4E2700
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_8 0x4E2704
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_9 0x4E2708
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_10 0x4E270C
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_11 0x4E2710
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_12 0x4E2714
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_13 0x4E2718
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_14 0x4E271C
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_15 0x4E2720
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_0 0x4E2724
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_1 0x4E2728
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_2 0x4E272C
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_3 0x4E2730
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_4 0x4E2734
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_5 0x4E2738
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_6 0x4E273C
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_7 0x4E2740
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_8 0x4E2744
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_9 0x4E2748
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_10 0x4E274C
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_11 0x4E2750
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_12 0x4E2754
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_13 0x4E2758
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_14 0x4E275C
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_15 0x4E2760
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_0 0x4E2764
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_1 0x4E2768
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_2 0x4E276C
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_3 0x4E2770
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_4 0x4E2774
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_5 0x4E2778
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_6 0x4E277C
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_7 0x4E2780
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_8 0x4E2784
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_9 0x4E2788
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_10 0x4E278C
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_11 0x4E2790
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_12 0x4E2794
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_13 0x4E2798
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_14 0x4E279C
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_15 0x4E27A0
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_0 0x4E27A4
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_1 0x4E27A8
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_2 0x4E27AC
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_3 0x4E27B0
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_4 0x4E27B4
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_5 0x4E27B8
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_6 0x4E27BC
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_7 0x4E27C0
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_8 0x4E27C4
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_9 0x4E27C8
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_10 0x4E27CC
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_11 0x4E27D0
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_12 0x4E27D4
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_13 0x4E27D8
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_14 0x4E27DC
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_15 0x4E27E0
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_0 0x4E2824
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_1 0x4E2828
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_2 0x4E282C
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_3 0x4E2830
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_4 0x4E2834
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_5 0x4E2838
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_6 0x4E283C
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_7 0x4E2840
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_8 0x4E2844
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_9 0x4E2848
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_10 0x4E284C
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_11 0x4E2850
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_12 0x4E2854
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_13 0x4E2858
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_14 0x4E285C
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_15 0x4E2860
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_0 0x4E2864
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_1 0x4E2868
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_2 0x4E286C
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_3 0x4E2870
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_4 0x4E2874
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_5 0x4E2878
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_6 0x4E287C
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_7 0x4E2880
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_8 0x4E2884
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_9 0x4E2888
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_10 0x4E288C
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_11 0x4E2890
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_12 0x4E2894
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_13 0x4E2898
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_14 0x4E289C
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_15 0x4E28A0
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_0 0x4E28A4
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_1 0x4E28A8
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_2 0x4E28AC
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_3 0x4E28B0
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_4 0x4E28B4
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_5 0x4E28B8
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_6 0x4E28BC
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_7 0x4E28C0
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_8 0x4E28C4
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_9 0x4E28C8
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_10 0x4E28CC
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_11 0x4E28D0
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_12 0x4E28D4
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_13 0x4E28D8
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_14 0x4E28DC
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_15 0x4E28E0
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_0 0x4E28E4
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_1 0x4E28E8
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_2 0x4E28EC
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_3 0x4E28F0
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_4 0x4E28F4
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_5 0x4E28F8
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_6 0x4E28FC
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_7 0x4E2900
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_8 0x4E2904
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_9 0x4E2908
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_10 0x4E290C
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_11 0x4E2910
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_12 0x4E2914
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_13 0x4E2918
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_14 0x4E291C
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_15 0x4E2920
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_0 0x4E2924
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_1 0x4E2928
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_2 0x4E292C
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_3 0x4E2930
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_4 0x4E2934
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_5 0x4E2938
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_6 0x4E293C
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_7 0x4E2940
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_8 0x4E2944
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_9 0x4E2948
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_10 0x4E294C
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_11 0x4E2950
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_12 0x4E2954
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_13 0x4E2958
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_14 0x4E295C
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_15 0x4E2960
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_0 0x4E2964
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_1 0x4E2968
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_2 0x4E296C
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_3 0x4E2970
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_4 0x4E2974
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_5 0x4E2978
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_6 0x4E297C
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_7 0x4E2980
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_8 0x4E2984
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_9 0x4E2988
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_10 0x4E298C
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_11 0x4E2990
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_12 0x4E2994
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_13 0x4E2998
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_14 0x4E299C
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_15 0x4E29A0
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_0 0x4E29A4
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_1 0x4E29A8
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_2 0x4E29AC
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_3 0x4E29B0
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_4 0x4E29B4
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_5 0x4E29B8
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_6 0x4E29BC
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_7 0x4E29C0
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_8 0x4E29C4
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_9 0x4E29C8
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_10 0x4E29CC
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_11 0x4E29D0
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_12 0x4E29D4
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_13 0x4E29D8
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_14 0x4E29DC
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_15 0x4E29E0
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_0 0x4E29E4
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_1 0x4E29E8
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_2 0x4E29EC
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_3 0x4E29F0
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_4 0x4E29F4
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_5 0x4E29F8
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_6 0x4E29FC
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_7 0x4E2A00
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_8 0x4E2A04
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_9 0x4E2A08
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_10 0x4E2A0C
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_11 0x4E2A10
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_12 0x4E2A14
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_13 0x4E2A18
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_14 0x4E2A1C
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_15 0x4E2A20
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_HIT_AW 0x4E2A64
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_HIT_AR 0x4E2A68
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_HIT_AW 0x4E2A6C
+
+#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_HIT_AR 0x4E2A70
+
+#define mmDMA_IF_E_N_DOWN_CH1_RGL_CFG 0x4E2B64
+
+#define mmDMA_IF_E_N_DOWN_CH1_RGL_SHIFT 0x4E2B68
+
+#define mmDMA_IF_E_N_DOWN_CH1_RGL_EXPECTED_LAT_0 0x4E2B6C
+
+#define mmDMA_IF_E_N_DOWN_CH1_RGL_EXPECTED_LAT_1 0x4E2B70
+
+#define mmDMA_IF_E_N_DOWN_CH1_RGL_EXPECTED_LAT_2 0x4E2B74
+
+#define mmDMA_IF_E_N_DOWN_CH1_RGL_EXPECTED_LAT_3 0x4E2B78
+
+#define mmDMA_IF_E_N_DOWN_CH1_RGL_EXPECTED_LAT_4 0x4E2B7C
+
+#define mmDMA_IF_E_N_DOWN_CH1_RGL_EXPECTED_LAT_5 0x4E2B80
+
+#define mmDMA_IF_E_N_DOWN_CH1_RGL_EXPECTED_LAT_6 0x4E2B84
+
+#define mmDMA_IF_E_N_DOWN_CH1_RGL_EXPECTED_LAT_7 0x4E2B88
+
+#define mmDMA_IF_E_N_DOWN_CH1_RGL_TOKEN_0 0x4E2BAC
+
+#define mmDMA_IF_E_N_DOWN_CH1_RGL_TOKEN_1 0x4E2BB0
+
+#define mmDMA_IF_E_N_DOWN_CH1_RGL_TOKEN_2 0x4E2BB4
+
+#define mmDMA_IF_E_N_DOWN_CH1_RGL_TOKEN_3 0x4E2BB8
+
+#define mmDMA_IF_E_N_DOWN_CH1_RGL_TOKEN_4 0x4E2BBC
+
+#define mmDMA_IF_E_N_DOWN_CH1_RGL_TOKEN_5 0x4E2BC0
+
+#define mmDMA_IF_E_N_DOWN_CH1_RGL_TOKEN_6 0x4E2BC4
+
+#define mmDMA_IF_E_N_DOWN_CH1_RGL_TOKEN_7 0x4E2BC8
+
+#define mmDMA_IF_E_N_DOWN_CH1_RGL_BANK_ID_0 0x4E2BEC
+
+#define mmDMA_IF_E_N_DOWN_CH1_RGL_BANK_ID_1 0x4E2BF0
+
+#define mmDMA_IF_E_N_DOWN_CH1_RGL_BANK_ID_2 0x4E2BF4
+
+#define mmDMA_IF_E_N_DOWN_CH1_RGL_BANK_ID_3 0x4E2BF8
+
+#define mmDMA_IF_E_N_DOWN_CH1_RGL_BANK_ID_4 0x4E2BFC
+
+#define mmDMA_IF_E_N_DOWN_CH1_RGL_BANK_ID_5 0x4E2C00
+
+#define mmDMA_IF_E_N_DOWN_CH1_RGL_BANK_ID_6 0x4E2C04
+
+#define mmDMA_IF_E_N_DOWN_CH1_RGL_BANK_ID_7 0x4E2C08
+
+#define mmDMA_IF_E_N_DOWN_CH1_RGL_WDT 0x4E2C2C
+
+#define mmDMA_IF_E_N_DOWN_CH1_E2E_AR_HBM0_CH0_CTR_WRAP 0x4E2C30
+
+#define mmDMA_IF_E_N_DOWN_CH1_E2E_AR_HBM0_CH1_CTR_WRAP 0x4E2C34
+
+#define mmDMA_IF_E_N_DOWN_CH1_E2E_AR_HBM1_CH0_CTR_WRAP 0x4E2C38
+
+#define mmDMA_IF_E_N_DOWN_CH1_E2E_AR_HBM1_CH1_CTR_WRAP 0x4E2C3C
+
+#define mmDMA_IF_E_N_DOWN_CH1_E2E_AR_HBM2_CH0_CTR_WRAP 0x4E2C40
+
+#define mmDMA_IF_E_N_DOWN_CH1_E2E_AR_HBM2_CH1_CTR_WRAP 0x4E2C44
+
+#define mmDMA_IF_E_N_DOWN_CH1_E2E_AR_HBM3_CH0_CTR_WRAP 0x4E2C48
+
+#define mmDMA_IF_E_N_DOWN_CH1_E2E_AR_HBM3_CH1_CTR_WRAP 0x4E2C4C
+
+#define mmDMA_IF_E_N_DOWN_CH1_E2E_AR_HBM0_CH0_CTR_CNT 0x4E2C50
+
+#define mmDMA_IF_E_N_DOWN_CH1_E2E_AR_HBM0_CH1_CTR_CNT 0x4E2C54
+
+#define mmDMA_IF_E_N_DOWN_CH1_E2E_AR_HBM1_CH0_CTR_CNT 0x4E2C58
+
+#define mmDMA_IF_E_N_DOWN_CH1_E2E_AR_HBM1_CH1_CTR_CNT 0x4E2C5C
+
+#define mmDMA_IF_E_N_DOWN_CH1_E2E_AR_HBM2_CH0_CTR_CNT 0x4E2C60
+
+#define mmDMA_IF_E_N_DOWN_CH1_E2E_AR_HBM2_CH1_CTR_CNT 0x4E2C64
+
+#define mmDMA_IF_E_N_DOWN_CH1_E2E_AR_HBM3_CH0_CTR_CNT 0x4E2C68
+
+#define mmDMA_IF_E_N_DOWN_CH1_E2E_AR_HBM3_CH1_CTR_CNT 0x4E2C6C
+
+#define mmDMA_IF_E_N_DOWN_CH1_E2E_AW_HBM0_CH0_CTR_WRAP 0x4E2C70
+
+#define mmDMA_IF_E_N_DOWN_CH1_E2E_AW_HBM0_CH1_CTR_WRAP 0x4E2C74
+
+#define mmDMA_IF_E_N_DOWN_CH1_E2E_AW_HBM1_CH0_CTR_WRAP 0x4E2C78
+
+#define mmDMA_IF_E_N_DOWN_CH1_E2E_AW_HBM1_CH1_CTR_WRAP 0x4E2C7C
+
+#define mmDMA_IF_E_N_DOWN_CH1_E2E_AW_HBM2_CH0_CTR_WRAP 0x4E2C80
+
+#define mmDMA_IF_E_N_DOWN_CH1_E2E_AW_HBM2_CH1_CTR_WRAP 0x4E2C84
+
+#define mmDMA_IF_E_N_DOWN_CH1_E2E_AW_HBM3_CH0_CTR_WRAP 0x4E2C88
+
+#define mmDMA_IF_E_N_DOWN_CH1_E2E_AW_HBM3_CH1_CTR_WRAP 0x4E2C8C
+
+#define mmDMA_IF_E_N_DOWN_CH1_E2E_AW_HBM0_CH0_CTR_CNT 0x4E2C90
+
+#define mmDMA_IF_E_N_DOWN_CH1_E2E_AW_HBM0_CH1_CTR_CNT 0x4E2C94
+
+#define mmDMA_IF_E_N_DOWN_CH1_E2E_AW_HBM1_CH0_CTR_CNT 0x4E2C98
+
+#define mmDMA_IF_E_N_DOWN_CH1_E2E_AW_HBM1_CH1_CTR_CNT 0x4E2C9C
+
+#define mmDMA_IF_E_N_DOWN_CH1_E2E_AW_HBM2_CH0_CTR_CNT 0x4E2CA0
+
+#define mmDMA_IF_E_N_DOWN_CH1_E2E_AW_HBM2_CH1_CTR_CNT 0x4E2CA4
+
+#define mmDMA_IF_E_N_DOWN_CH1_E2E_AW_HBM3_CH0_CTR_CNT 0x4E2CA8
+
+#define mmDMA_IF_E_N_DOWN_CH1_E2E_AW_HBM3_CH1_CTR_CNT 0x4E2CAC
+
+#define mmDMA_IF_E_N_DOWN_CH1_NL_HBM_PC_SEL_0 0x4E2CB0
+
+#define mmDMA_IF_E_N_DOWN_CH1_NL_HBM_PC_SEL_1 0x4E2CB4
+
+#define mmDMA_IF_E_N_DOWN_CH1_NL_HBM_PC_SEL_2 0x4E2CB8
+
+#define mmDMA_IF_E_N_DOWN_CH1_NL_HBM_PC_SEL_3 0x4E2CBC
+
+#endif /* ASIC_REG_DMA_IF_E_N_DOWN_CH1_REGS_H_ */
diff --git a/drivers/accel/habanalabs/include/gaudi/asic_reg/dma_if_e_n_regs.h b/drivers/accel/habanalabs/include/gaudi/asic_reg/dma_if_e_n_regs.h
new file mode 100644
index 0000000000..8a10c6a761
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi/asic_reg/dma_if_e_n_regs.h
@@ -0,0 +1,860 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2016-2018 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ ** DO NOT EDIT BELOW **
+ ************************************/
+
+#ifndef ASIC_REG_DMA_IF_E_N_REGS_H_
+#define ASIC_REG_DMA_IF_E_N_REGS_H_
+
+/*
+ *****************************************
+ * DMA_IF_E_N (Prototype: DMA_IF)
+ *****************************************
+ */
+
+#define mmDMA_IF_E_N_HBM0_WR_CRED_CNT 0x4E0000
+
+#define mmDMA_IF_E_N_HBM1_WR_CRED_CNT 0x4E0004
+
+#define mmDMA_IF_E_N_HBM0_RD_CRED_CNT 0x4E0008
+
+#define mmDMA_IF_E_N_HBM1_RD_CRED_CNT 0x4E000C
+
+#define mmDMA_IF_E_N_HBM_LIMITER_0 0x4E0030
+
+#define mmDMA_IF_E_N_HBM_LIMITER_1 0x4E0034
+
+#define mmDMA_IF_E_N_HBM_LIMITER_2 0x4E0038
+
+#define mmDMA_IF_E_N_HBM_LIMITER_3 0x4E003C
+
+#define mmDMA_IF_E_N_HBM_ALMOST_EN_0 0x4E0040
+
+#define mmDMA_IF_E_N_HBM_ALMOST_EN_1 0x4E0044
+
+#define mmDMA_IF_E_N_HBM_CRED_EN_0 0x4E0050
+
+#define mmDMA_IF_E_N_HBM_CRED_EN_1 0x4E0054
+
+#define mmDMA_IF_E_N_SOB_MIN_RPROT_0 0x4E0100
+
+#define mmDMA_IF_E_N_SOB_MIN_RPROT_1 0x4E0104
+
+#define mmDMA_IF_E_N_SOB_MIN_RPROT_2 0x4E0108
+
+#define mmDMA_IF_E_N_SOB_MIN_RPROT_3 0x4E010C
+
+#define mmDMA_IF_E_N_SOB_MIN_RPROT_4 0x4E0110
+
+#define mmDMA_IF_E_N_SOB_MIN_RPROT_5 0x4E0114
+
+#define mmDMA_IF_E_N_SOB_MIN_RPROT_6 0x4E0118
+
+#define mmDMA_IF_E_N_SOB_MIN_RPROT_7 0x4E011C
+
+#define mmDMA_IF_E_N_SOB_MIN_RPROT_8 0x4E0120
+
+#define mmDMA_IF_E_N_SOB_MIN_RPROT_9 0x4E0124
+
+#define mmDMA_IF_E_N_SOB_MIN_RPROT_10 0x4E0128
+
+#define mmDMA_IF_E_N_SOB_MIN_RPROT_11 0x4E012C
+
+#define mmDMA_IF_E_N_SOB_MIN_RPROT_12 0x4E0130
+
+#define mmDMA_IF_E_N_SOB_MIN_RPROT_13 0x4E0134
+
+#define mmDMA_IF_E_N_SOB_MIN_RPROT_14 0x4E0138
+
+#define mmDMA_IF_E_N_SOB_MIN_RPROT_15 0x4E013C
+
+#define mmDMA_IF_E_N_SOB_MAX_RPROT_0 0x4E0140
+
+#define mmDMA_IF_E_N_SOB_MAX_RPROT_1 0x4E0144
+
+#define mmDMA_IF_E_N_SOB_MAX_RPROT_2 0x4E0148
+
+#define mmDMA_IF_E_N_SOB_MAX_RPROT_3 0x4E014C
+
+#define mmDMA_IF_E_N_SOB_MAX_RPROT_4 0x4E0150
+
+#define mmDMA_IF_E_N_SOB_MAX_RPROT_5 0x4E0154
+
+#define mmDMA_IF_E_N_SOB_MAX_RPROT_6 0x4E0158
+
+#define mmDMA_IF_E_N_SOB_MAX_RPROT_7 0x4E015C
+
+#define mmDMA_IF_E_N_SOB_MAX_RPROT_8 0x4E0160
+
+#define mmDMA_IF_E_N_SOB_MAX_RPROT_9 0x4E0164
+
+#define mmDMA_IF_E_N_SOB_MAX_RPROT_10 0x4E0168
+
+#define mmDMA_IF_E_N_SOB_MAX_RPROT_11 0x4E016C
+
+#define mmDMA_IF_E_N_SOB_MAX_RPROT_12 0x4E0170
+
+#define mmDMA_IF_E_N_SOB_MAX_RPROT_13 0x4E0174
+
+#define mmDMA_IF_E_N_SOB_MAX_RPROT_14 0x4E0178
+
+#define mmDMA_IF_E_N_SOB_MAX_RPROT_15 0x4E017C
+
+#define mmDMA_IF_E_N_SOB_MIN_WPROT_0 0x4E0180
+
+#define mmDMA_IF_E_N_SOB_MIN_WPROT_1 0x4E0184
+
+#define mmDMA_IF_E_N_SOB_MIN_WPROT_2 0x4E0188
+
+#define mmDMA_IF_E_N_SOB_MIN_WPROT_3 0x4E018C
+
+#define mmDMA_IF_E_N_SOB_MIN_WPROT_4 0x4E0190
+
+#define mmDMA_IF_E_N_SOB_MIN_WPROT_5 0x4E0194
+
+#define mmDMA_IF_E_N_SOB_MIN_WPROT_6 0x4E0198
+
+#define mmDMA_IF_E_N_SOB_MIN_WPROT_7 0x4E019C
+
+#define mmDMA_IF_E_N_SOB_MIN_WPROT_8 0x4E01A0
+
+#define mmDMA_IF_E_N_SOB_MIN_WPROT_9 0x4E01A4
+
+#define mmDMA_IF_E_N_SOB_MIN_WPROT_10 0x4E01A8
+
+#define mmDMA_IF_E_N_SOB_MIN_WPROT_11 0x4E01AC
+
+#define mmDMA_IF_E_N_SOB_MIN_WPROT_12 0x4E01B0
+
+#define mmDMA_IF_E_N_SOB_MIN_WPROT_13 0x4E01B4
+
+#define mmDMA_IF_E_N_SOB_MIN_WPROT_14 0x4E01B8
+
+#define mmDMA_IF_E_N_SOB_MIN_WPROT_15 0x4E01BC
+
+#define mmDMA_IF_E_N_SOB_MAX_WPROT_0 0x4E01C0
+
+#define mmDMA_IF_E_N_SOB_MAX_WPROT_1 0x4E01C4
+
+#define mmDMA_IF_E_N_SOB_MAX_WPROT_2 0x4E01C8
+
+#define mmDMA_IF_E_N_SOB_MAX_WPROT_3 0x4E01CC
+
+#define mmDMA_IF_E_N_SOB_MAX_WPROT_4 0x4E01D0
+
+#define mmDMA_IF_E_N_SOB_MAX_WPROT_5 0x4E01D4
+
+#define mmDMA_IF_E_N_SOB_MAX_WPROT_6 0x4E01D8
+
+#define mmDMA_IF_E_N_SOB_MAX_WPROT_7 0x4E01DC
+
+#define mmDMA_IF_E_N_SOB_MAX_WPROT_8 0x4E01E0
+
+#define mmDMA_IF_E_N_SOB_MAX_WPROT_9 0x4E01E4
+
+#define mmDMA_IF_E_N_SOB_MAX_WPROT_10 0x4E01E8
+
+#define mmDMA_IF_E_N_SOB_MAX_WPROT_11 0x4E01EC
+
+#define mmDMA_IF_E_N_SOB_MAX_WPROT_12 0x4E01F0
+
+#define mmDMA_IF_E_N_SOB_MAX_WPROT_13 0x4E01F4
+
+#define mmDMA_IF_E_N_SOB_MAX_WPROT_14 0x4E01F8
+
+#define mmDMA_IF_E_N_SOB_MAX_WPROT_15 0x4E01FC
+
+#define mmDMA_IF_E_N_SOB_MIN_RPRIV_0 0x4E0200
+
+#define mmDMA_IF_E_N_SOB_MIN_RPRIV_1 0x4E0204
+
+#define mmDMA_IF_E_N_SOB_MIN_RPRIV_2 0x4E0208
+
+#define mmDMA_IF_E_N_SOB_MIN_RPRIV_3 0x4E020C
+
+#define mmDMA_IF_E_N_SOB_MIN_RPRIV_4 0x4E0210
+
+#define mmDMA_IF_E_N_SOB_MIN_RPRIV_5 0x4E0214
+
+#define mmDMA_IF_E_N_SOB_MIN_RPRIV_6 0x4E0218
+
+#define mmDMA_IF_E_N_SOB_MIN_RPRIV_7 0x4E021C
+
+#define mmDMA_IF_E_N_SOB_MIN_RPRIV_8 0x4E0220
+
+#define mmDMA_IF_E_N_SOB_MIN_RPRIV_9 0x4E0224
+
+#define mmDMA_IF_E_N_SOB_MIN_RPRIV_10 0x4E0228
+
+#define mmDMA_IF_E_N_SOB_MIN_RPRIV_11 0x4E022C
+
+#define mmDMA_IF_E_N_SOB_MIN_RPRIV_12 0x4E0230
+
+#define mmDMA_IF_E_N_SOB_MIN_RPRIV_13 0x4E0234
+
+#define mmDMA_IF_E_N_SOB_MIN_RPRIV_14 0x4E0238
+
+#define mmDMA_IF_E_N_SOB_MIN_RPRIV_15 0x4E023C
+
+#define mmDMA_IF_E_N_SOB_MAX_RPRIV_0 0x4E0240
+
+#define mmDMA_IF_E_N_SOB_MAX_RPRIV_1 0x4E0244
+
+#define mmDMA_IF_E_N_SOB_MAX_RPRIV_2 0x4E0248
+
+#define mmDMA_IF_E_N_SOB_MAX_RPRIV_3 0x4E024C
+
+#define mmDMA_IF_E_N_SOB_MAX_RPRIV_4 0x4E0250
+
+#define mmDMA_IF_E_N_SOB_MAX_RPRIV_5 0x4E0254
+
+#define mmDMA_IF_E_N_SOB_MAX_RPRIV_6 0x4E0258
+
+#define mmDMA_IF_E_N_SOB_MAX_RPRIV_7 0x4E025C
+
+#define mmDMA_IF_E_N_SOB_MAX_RPRIV_8 0x4E0260
+
+#define mmDMA_IF_E_N_SOB_MAX_RPRIV_9 0x4E0264
+
+#define mmDMA_IF_E_N_SOB_MAX_RPRIV_10 0x4E0268
+
+#define mmDMA_IF_E_N_SOB_MAX_RPRIV_11 0x4E026C
+
+#define mmDMA_IF_E_N_SOB_MAX_RPRIV_12 0x4E0270
+
+#define mmDMA_IF_E_N_SOB_MAX_RPRIV_13 0x4E0274
+
+#define mmDMA_IF_E_N_SOB_MAX_RPRIV_14 0x4E0278
+
+#define mmDMA_IF_E_N_SOB_MAX_RPRIV_15 0x4E027C
+
+#define mmDMA_IF_E_N_SOB_MIN_WPRIV_0 0x4E0280
+
+#define mmDMA_IF_E_N_SOB_MIN_WPRIV_1 0x4E0284
+
+#define mmDMA_IF_E_N_SOB_MIN_WPRIV_2 0x4E0288
+
+#define mmDMA_IF_E_N_SOB_MIN_WPRIV_3 0x4E028C
+
+#define mmDMA_IF_E_N_SOB_MIN_WPRIV_4 0x4E0290
+
+#define mmDMA_IF_E_N_SOB_MIN_WPRIV_5 0x4E0294
+
+#define mmDMA_IF_E_N_SOB_MIN_WPRIV_6 0x4E0298
+
+#define mmDMA_IF_E_N_SOB_MIN_WPRIV_7 0x4E029C
+
+#define mmDMA_IF_E_N_SOB_MIN_WPRIV_8 0x4E02A0
+
+#define mmDMA_IF_E_N_SOB_MIN_WPRIV_9 0x4E02A4
+
+#define mmDMA_IF_E_N_SOB_MIN_WPRIV_10 0x4E02A8
+
+#define mmDMA_IF_E_N_SOB_MIN_WPRIV_11 0x4E02AC
+
+#define mmDMA_IF_E_N_SOB_MIN_WPRIV_12 0x4E02B0
+
+#define mmDMA_IF_E_N_SOB_MIN_WPRIV_13 0x4E02B4
+
+#define mmDMA_IF_E_N_SOB_MIN_WPRIV_14 0x4E02B8
+
+#define mmDMA_IF_E_N_SOB_MIN_WPRIV_15 0x4E02BC
+
+#define mmDMA_IF_E_N_SOB_MAX_WPRIV_0 0x4E02C0
+
+#define mmDMA_IF_E_N_SOB_MAX_WPRIV_1 0x4E02C4
+
+#define mmDMA_IF_E_N_SOB_MAX_WPRIV_2 0x4E02C8
+
+#define mmDMA_IF_E_N_SOB_MAX_WPRIV_3 0x4E02CC
+
+#define mmDMA_IF_E_N_SOB_MAX_WPRIV_4 0x4E02D0
+
+#define mmDMA_IF_E_N_SOB_MAX_WPRIV_5 0x4E02D4
+
+#define mmDMA_IF_E_N_SOB_MAX_WPRIV_6 0x4E02D8
+
+#define mmDMA_IF_E_N_SOB_MAX_WPRIV_7 0x4E02DC
+
+#define mmDMA_IF_E_N_SOB_MAX_WPRIV_8 0x4E02E0
+
+#define mmDMA_IF_E_N_SOB_MAX_WPRIV_9 0x4E02E4
+
+#define mmDMA_IF_E_N_SOB_MAX_WPRIV_10 0x4E02E8
+
+#define mmDMA_IF_E_N_SOB_MAX_WPRIV_11 0x4E02EC
+
+#define mmDMA_IF_E_N_SOB_MAX_WPRIV_12 0x4E02F0
+
+#define mmDMA_IF_E_N_SOB_MAX_WPRIV_13 0x4E02F4
+
+#define mmDMA_IF_E_N_SOB_MAX_WPRIV_14 0x4E02F8
+
+#define mmDMA_IF_E_N_SOB_MAX_WPRIV_15 0x4E02FC
+
+#define mmDMA_IF_E_N_DMA0_MIN_RPROT_0 0x4E0300
+
+#define mmDMA_IF_E_N_DMA0_MIN_RPROT_1 0x4E0304
+
+#define mmDMA_IF_E_N_DMA0_MIN_RPROT_2 0x4E0308
+
+#define mmDMA_IF_E_N_DMA0_MIN_RPROT_3 0x4E030C
+
+#define mmDMA_IF_E_N_DMA0_MIN_RPROT_4 0x4E0310
+
+#define mmDMA_IF_E_N_DMA0_MIN_RPROT_5 0x4E0314
+
+#define mmDMA_IF_E_N_DMA0_MIN_RPROT_6 0x4E0318
+
+#define mmDMA_IF_E_N_DMA0_MIN_RPROT_7 0x4E031C
+
+#define mmDMA_IF_E_N_DMA0_MIN_RPROT_8 0x4E0320
+
+#define mmDMA_IF_E_N_DMA0_MIN_RPROT_9 0x4E0324
+
+#define mmDMA_IF_E_N_DMA0_MIN_RPROT_10 0x4E0328
+
+#define mmDMA_IF_E_N_DMA0_MIN_RPROT_11 0x4E032C
+
+#define mmDMA_IF_E_N_DMA0_MIN_RPROT_12 0x4E0330
+
+#define mmDMA_IF_E_N_DMA0_MIN_RPROT_13 0x4E0334
+
+#define mmDMA_IF_E_N_DMA0_MIN_RPROT_14 0x4E0338
+
+#define mmDMA_IF_E_N_DMA0_MIN_RPROT_15 0x4E033C
+
+#define mmDMA_IF_E_N_DMA0_MAX_RPROT_0 0x4E0340
+
+#define mmDMA_IF_E_N_DMA0_MAX_RPROT_1 0x4E0344
+
+#define mmDMA_IF_E_N_DMA0_MAX_RPROT_2 0x4E0348
+
+#define mmDMA_IF_E_N_DMA0_MAX_RPROT_3 0x4E034C
+
+#define mmDMA_IF_E_N_DMA0_MAX_RPROT_4 0x4E0350
+
+#define mmDMA_IF_E_N_DMA0_MAX_RPROT_5 0x4E0354
+
+#define mmDMA_IF_E_N_DMA0_MAX_RPROT_6 0x4E0358
+
+#define mmDMA_IF_E_N_DMA0_MAX_RPROT_7 0x4E035C
+
+#define mmDMA_IF_E_N_DMA0_MAX_RPROT_8 0x4E0360
+
+#define mmDMA_IF_E_N_DMA0_MAX_RPROT_9 0x4E0364
+
+#define mmDMA_IF_E_N_DMA0_MAX_RPROT_10 0x4E0368
+
+#define mmDMA_IF_E_N_DMA0_MAX_RPROT_11 0x4E036C
+
+#define mmDMA_IF_E_N_DMA0_MAX_RPROT_12 0x4E0370
+
+#define mmDMA_IF_E_N_DMA0_MAX_RPROT_13 0x4E0374
+
+#define mmDMA_IF_E_N_DMA0_MAX_RPROT_14 0x4E0378
+
+#define mmDMA_IF_E_N_DMA0_MAX_RPROT_15 0x4E037C
+
+#define mmDMA_IF_E_N_DMA0_MIN_WPROT_0 0x4E0380
+
+#define mmDMA_IF_E_N_DMA0_MIN_WPROT_1 0x4E0384
+
+#define mmDMA_IF_E_N_DMA0_MIN_WPROT_2 0x4E0388
+
+#define mmDMA_IF_E_N_DMA0_MIN_WPROT_3 0x4E038C
+
+#define mmDMA_IF_E_N_DMA0_MIN_WPROT_4 0x4E0390
+
+#define mmDMA_IF_E_N_DMA0_MIN_WPROT_5 0x4E0394
+
+#define mmDMA_IF_E_N_DMA0_MIN_WPROT_6 0x4E0398
+
+#define mmDMA_IF_E_N_DMA0_MIN_WPROT_7 0x4E039C
+
+#define mmDMA_IF_E_N_DMA0_MIN_WPROT_8 0x4E03A0
+
+#define mmDMA_IF_E_N_DMA0_MIN_WPROT_9 0x4E03A4
+
+#define mmDMA_IF_E_N_DMA0_MIN_WPROT_10 0x4E03A8
+
+#define mmDMA_IF_E_N_DMA0_MIN_WPROT_11 0x4E03AC
+
+#define mmDMA_IF_E_N_DMA0_MIN_WPROT_12 0x4E03B0
+
+#define mmDMA_IF_E_N_DMA0_MIN_WPROT_13 0x4E03B4
+
+#define mmDMA_IF_E_N_DMA0_MIN_WPROT_14 0x4E03B8
+
+#define mmDMA_IF_E_N_DMA0_MIN_WPROT_15 0x4E03BC
+
+#define mmDMA_IF_E_N_DMA0_MAX_WPROT_0 0x4E03C0
+
+#define mmDMA_IF_E_N_DMA0_MAX_WPROT_1 0x4E03C4
+
+#define mmDMA_IF_E_N_DMA0_MAX_WPROT_2 0x4E03C8
+
+#define mmDMA_IF_E_N_DMA0_MAX_WPROT_3 0x4E03CC
+
+#define mmDMA_IF_E_N_DMA0_MAX_WPROT_4 0x4E03D0
+
+#define mmDMA_IF_E_N_DMA0_MAX_WPROT_5 0x4E03D4
+
+#define mmDMA_IF_E_N_DMA0_MAX_WPROT_6 0x4E03D8
+
+#define mmDMA_IF_E_N_DMA0_MAX_WPROT_7 0x4E03DC
+
+#define mmDMA_IF_E_N_DMA0_MAX_WPROT_8 0x4E03E0
+
+#define mmDMA_IF_E_N_DMA0_MAX_WPROT_9 0x4E03E4
+
+#define mmDMA_IF_E_N_DMA0_MAX_WPROT_10 0x4E03E8
+
+#define mmDMA_IF_E_N_DMA0_MAX_WPROT_11 0x4E03EC
+
+#define mmDMA_IF_E_N_DMA0_MAX_WPROT_12 0x4E03F0
+
+#define mmDMA_IF_E_N_DMA0_MAX_WPROT_13 0x4E03F4
+
+#define mmDMA_IF_E_N_DMA0_MAX_WPROT_14 0x4E03F8
+
+#define mmDMA_IF_E_N_DMA0_MAX_WPROT_15 0x4E03FC
+
+#define mmDMA_IF_E_N_DMA0_MIN_RPRIV_0 0x4E0400
+
+#define mmDMA_IF_E_N_DMA0_MIN_RPRIV_1 0x4E0404
+
+#define mmDMA_IF_E_N_DMA0_MIN_RPRIV_2 0x4E0408
+
+#define mmDMA_IF_E_N_DMA0_MIN_RPRIV_3 0x4E040C
+
+#define mmDMA_IF_E_N_DMA0_MIN_RPRIV_4 0x4E0410
+
+#define mmDMA_IF_E_N_DMA0_MIN_RPRIV_5 0x4E0414
+
+#define mmDMA_IF_E_N_DMA0_MIN_RPRIV_6 0x4E0418
+
+#define mmDMA_IF_E_N_DMA0_MIN_RPRIV_7 0x4E041C
+
+#define mmDMA_IF_E_N_DMA0_MIN_RPRIV_8 0x4E0420
+
+#define mmDMA_IF_E_N_DMA0_MIN_RPRIV_9 0x4E0424
+
+#define mmDMA_IF_E_N_DMA0_MIN_RPRIV_10 0x4E0428
+
+#define mmDMA_IF_E_N_DMA0_MIN_RPRIV_11 0x4E042C
+
+#define mmDMA_IF_E_N_DMA0_MIN_RPRIV_12 0x4E0430
+
+#define mmDMA_IF_E_N_DMA0_MIN_RPRIV_13 0x4E0434
+
+#define mmDMA_IF_E_N_DMA0_MIN_RPRIV_14 0x4E0438
+
+#define mmDMA_IF_E_N_DMA0_MIN_RPRIV_15 0x4E043C
+
+#define mmDMA_IF_E_N_DMA0_MAX_RPRIV_0 0x4E0440
+
+#define mmDMA_IF_E_N_DMA0_MAX_RPRIV_1 0x4E0444
+
+#define mmDMA_IF_E_N_DMA0_MAX_RPRIV_2 0x4E0448
+
+#define mmDMA_IF_E_N_DMA0_MAX_RPRIV_3 0x4E044C
+
+#define mmDMA_IF_E_N_DMA0_MAX_RPRIV_4 0x4E0450
+
+#define mmDMA_IF_E_N_DMA0_MAX_RPRIV_5 0x4E0454
+
+#define mmDMA_IF_E_N_DMA0_MAX_RPRIV_6 0x4E0458
+
+#define mmDMA_IF_E_N_DMA0_MAX_RPRIV_7 0x4E045C
+
+#define mmDMA_IF_E_N_DMA0_MAX_RPRIV_8 0x4E0460
+
+#define mmDMA_IF_E_N_DMA0_MAX_RPRIV_9 0x4E0464
+
+#define mmDMA_IF_E_N_DMA0_MAX_RPRIV_10 0x4E0468
+
+#define mmDMA_IF_E_N_DMA0_MAX_RPRIV_11 0x4E046C
+
+#define mmDMA_IF_E_N_DMA0_MAX_RPRIV_12 0x4E0470
+
+#define mmDMA_IF_E_N_DMA0_MAX_RPRIV_13 0x4E0474
+
+#define mmDMA_IF_E_N_DMA0_MAX_RPRIV_14 0x4E0478
+
+#define mmDMA_IF_E_N_DMA0_MAX_RPRIV_15 0x4E047C
+
+#define mmDMA_IF_E_N_DMA0_MIN_WPRIV_0 0x4E0480
+
+#define mmDMA_IF_E_N_DMA0_MIN_WPRIV_1 0x4E0484
+
+#define mmDMA_IF_E_N_DMA0_MIN_WPRIV_2 0x4E0488
+
+#define mmDMA_IF_E_N_DMA0_MIN_WPRIV_3 0x4E048C
+
+#define mmDMA_IF_E_N_DMA0_MIN_WPRIV_4 0x4E0490
+
+#define mmDMA_IF_E_N_DMA0_MIN_WPRIV_5 0x4E0494
+
+#define mmDMA_IF_E_N_DMA0_MIN_WPRIV_6 0x4E0498
+
+#define mmDMA_IF_E_N_DMA0_MIN_WPRIV_7 0x4E049C
+
+#define mmDMA_IF_E_N_DMA0_MIN_WPRIV_8 0x4E04A0
+
+#define mmDMA_IF_E_N_DMA0_MIN_WPRIV_9 0x4E04A4
+
+#define mmDMA_IF_E_N_DMA0_MIN_WPRIV_10 0x4E04A8
+
+#define mmDMA_IF_E_N_DMA0_MIN_WPRIV_11 0x4E04AC
+
+#define mmDMA_IF_E_N_DMA0_MIN_WPRIV_12 0x4E04B0
+
+#define mmDMA_IF_E_N_DMA0_MIN_WPRIV_13 0x4E04B4
+
+#define mmDMA_IF_E_N_DMA0_MIN_WPRIV_14 0x4E04B8
+
+#define mmDMA_IF_E_N_DMA0_MIN_WPRIV_15 0x4E04BC
+
+#define mmDMA_IF_E_N_DMA0_MAX_WPRIV_0 0x4E04C0
+
+#define mmDMA_IF_E_N_DMA0_MAX_WPRIV_1 0x4E04C4
+
+#define mmDMA_IF_E_N_DMA0_MAX_WPRIV_2 0x4E04C8
+
+#define mmDMA_IF_E_N_DMA0_MAX_WPRIV_3 0x4E04CC
+
+#define mmDMA_IF_E_N_DMA0_MAX_WPRIV_4 0x4E04D0
+
+#define mmDMA_IF_E_N_DMA0_MAX_WPRIV_5 0x4E04D4
+
+#define mmDMA_IF_E_N_DMA0_MAX_WPRIV_6 0x4E04D8
+
+#define mmDMA_IF_E_N_DMA0_MAX_WPRIV_7 0x4E04DC
+
+#define mmDMA_IF_E_N_DMA0_MAX_WPRIV_8 0x4E04E0
+
+#define mmDMA_IF_E_N_DMA0_MAX_WPRIV_9 0x4E04E4
+
+#define mmDMA_IF_E_N_DMA0_MAX_WPRIV_10 0x4E04E8
+
+#define mmDMA_IF_E_N_DMA0_MAX_WPRIV_11 0x4E04EC
+
+#define mmDMA_IF_E_N_DMA0_MAX_WPRIV_12 0x4E04F0
+
+#define mmDMA_IF_E_N_DMA0_MAX_WPRIV_13 0x4E04F4
+
+#define mmDMA_IF_E_N_DMA0_MAX_WPRIV_14 0x4E04F8
+
+#define mmDMA_IF_E_N_DMA0_MAX_WPRIV_15 0x4E04FC
+
+#define mmDMA_IF_E_N_DMA1_MIN_RPROT_0 0x4E0500
+
+#define mmDMA_IF_E_N_DMA1_MIN_RPROT_1 0x4E0504
+
+#define mmDMA_IF_E_N_DMA1_MIN_RPROT_2 0x4E0508
+
+#define mmDMA_IF_E_N_DMA1_MIN_RPROT_3 0x4E050C
+
+#define mmDMA_IF_E_N_DMA1_MIN_RPROT_4 0x4E0510
+
+#define mmDMA_IF_E_N_DMA1_MIN_RPROT_5 0x4E0514
+
+#define mmDMA_IF_E_N_DMA1_MIN_RPROT_6 0x4E0518
+
+#define mmDMA_IF_E_N_DMA1_MIN_RPROT_7 0x4E051C
+
+#define mmDMA_IF_E_N_DMA1_MIN_RPROT_8 0x4E0520
+
+#define mmDMA_IF_E_N_DMA1_MIN_RPROT_9 0x4E0524
+
+#define mmDMA_IF_E_N_DMA1_MIN_RPROT_10 0x4E0528
+
+#define mmDMA_IF_E_N_DMA1_MIN_RPROT_11 0x4E052C
+
+#define mmDMA_IF_E_N_DMA1_MIN_RPROT_12 0x4E0530
+
+#define mmDMA_IF_E_N_DMA1_MIN_RPROT_13 0x4E0534
+
+#define mmDMA_IF_E_N_DMA1_MIN_RPROT_14 0x4E0538
+
+#define mmDMA_IF_E_N_DMA1_MIN_RPROT_15 0x4E053C
+
+#define mmDMA_IF_E_N_DMA1_MAX_RPROT_0 0x4E0540
+
+#define mmDMA_IF_E_N_DMA1_MAX_RPROT_1 0x4E0544
+
+#define mmDMA_IF_E_N_DMA1_MAX_RPROT_2 0x4E0548
+
+#define mmDMA_IF_E_N_DMA1_MAX_RPROT_3 0x4E054C
+
+#define mmDMA_IF_E_N_DMA1_MAX_RPROT_4 0x4E0550
+
+#define mmDMA_IF_E_N_DMA1_MAX_RPROT_5 0x4E0554
+
+#define mmDMA_IF_E_N_DMA1_MAX_RPROT_6 0x4E0558
+
+#define mmDMA_IF_E_N_DMA1_MAX_RPROT_7 0x4E055C
+
+#define mmDMA_IF_E_N_DMA1_MAX_RPROT_8 0x4E0560
+
+#define mmDMA_IF_E_N_DMA1_MAX_RPROT_9 0x4E0564
+
+#define mmDMA_IF_E_N_DMA1_MAX_RPROT_10 0x4E0568
+
+#define mmDMA_IF_E_N_DMA1_MAX_RPROT_11 0x4E056C
+
+#define mmDMA_IF_E_N_DMA1_MAX_RPROT_12 0x4E0570
+
+#define mmDMA_IF_E_N_DMA1_MAX_RPROT_13 0x4E0574
+
+#define mmDMA_IF_E_N_DMA1_MAX_RPROT_14 0x4E0578
+
+#define mmDMA_IF_E_N_DMA1_MAX_RPROT_15 0x4E057C
+
+#define mmDMA_IF_E_N_DMA1_MIN_WPROT_0 0x4E0580
+
+#define mmDMA_IF_E_N_DMA1_MIN_WPROT_1 0x4E0584
+
+#define mmDMA_IF_E_N_DMA1_MIN_WPROT_2 0x4E0588
+
+#define mmDMA_IF_E_N_DMA1_MIN_WPROT_3 0x4E058C
+
+#define mmDMA_IF_E_N_DMA1_MIN_WPROT_4 0x4E0590
+
+#define mmDMA_IF_E_N_DMA1_MIN_WPROT_5 0x4E0594
+
+#define mmDMA_IF_E_N_DMA1_MIN_WPROT_6 0x4E0598
+
+#define mmDMA_IF_E_N_DMA1_MIN_WPROT_7 0x4E059C
+
+#define mmDMA_IF_E_N_DMA1_MIN_WPROT_8 0x4E05A0
+
+#define mmDMA_IF_E_N_DMA1_MIN_WPROT_9 0x4E05A4
+
+#define mmDMA_IF_E_N_DMA1_MIN_WPROT_10 0x4E05A8
+
+#define mmDMA_IF_E_N_DMA1_MIN_WPROT_11 0x4E05AC
+
+#define mmDMA_IF_E_N_DMA1_MIN_WPROT_12 0x4E05B0
+
+#define mmDMA_IF_E_N_DMA1_MIN_WPROT_13 0x4E05B4
+
+#define mmDMA_IF_E_N_DMA1_MIN_WPROT_14 0x4E05B8
+
+#define mmDMA_IF_E_N_DMA1_MIN_WPROT_15 0x4E05BC
+
+#define mmDMA_IF_E_N_DMA1_MAX_WPROT_0 0x4E05C0
+
+#define mmDMA_IF_E_N_DMA1_MAX_WPROT_1 0x4E05C4
+
+#define mmDMA_IF_E_N_DMA1_MAX_WPROT_2 0x4E05C8
+
+#define mmDMA_IF_E_N_DMA1_MAX_WPROT_3 0x4E05CC
+
+#define mmDMA_IF_E_N_DMA1_MAX_WPROT_4 0x4E05D0
+
+#define mmDMA_IF_E_N_DMA1_MAX_WPROT_5 0x4E05D4
+
+#define mmDMA_IF_E_N_DMA1_MAX_WPROT_6 0x4E05D8
+
+#define mmDMA_IF_E_N_DMA1_MAX_WPROT_7 0x4E05DC
+
+#define mmDMA_IF_E_N_DMA1_MAX_WPROT_8 0x4E05E0
+
+#define mmDMA_IF_E_N_DMA1_MAX_WPROT_9 0x4E05E4
+
+#define mmDMA_IF_E_N_DMA1_MAX_WPROT_10 0x4E05E8
+
+#define mmDMA_IF_E_N_DMA1_MAX_WPROT_11 0x4E05EC
+
+#define mmDMA_IF_E_N_DMA1_MAX_WPROT_12 0x4E05F0
+
+#define mmDMA_IF_E_N_DMA1_MAX_WPROT_13 0x4E05F4
+
+#define mmDMA_IF_E_N_DMA1_MAX_WPROT_14 0x4E05F8
+
+#define mmDMA_IF_E_N_DMA1_MAX_WPROT_15 0x4E05FC
+
+#define mmDMA_IF_E_N_DMA1_MIN_RPRIV_0 0x4E0600
+
+#define mmDMA_IF_E_N_DMA1_MIN_RPRIV_1 0x4E0604
+
+#define mmDMA_IF_E_N_DMA1_MIN_RPRIV_2 0x4E0608
+
+#define mmDMA_IF_E_N_DMA1_MIN_RPRIV_3 0x4E060C
+
+#define mmDMA_IF_E_N_DMA1_MIN_RPRIV_4 0x4E0610
+
+#define mmDMA_IF_E_N_DMA1_MIN_RPRIV_5 0x4E0614
+
+#define mmDMA_IF_E_N_DMA1_MIN_RPRIV_6 0x4E0618
+
+#define mmDMA_IF_E_N_DMA1_MIN_RPRIV_7 0x4E061C
+
+#define mmDMA_IF_E_N_DMA1_MIN_RPRIV_8 0x4E0620
+
+#define mmDMA_IF_E_N_DMA1_MIN_RPRIV_9 0x4E0624
+
+#define mmDMA_IF_E_N_DMA1_MIN_RPRIV_10 0x4E0628
+
+#define mmDMA_IF_E_N_DMA1_MIN_RPRIV_11 0x4E062C
+
+#define mmDMA_IF_E_N_DMA1_MIN_RPRIV_12 0x4E0630
+
+#define mmDMA_IF_E_N_DMA1_MIN_RPRIV_13 0x4E0634
+
+#define mmDMA_IF_E_N_DMA1_MIN_RPRIV_14 0x4E0638
+
+#define mmDMA_IF_E_N_DMA1_MIN_RPRIV_15 0x4E063C
+
+#define mmDMA_IF_E_N_DMA1_MAX_RPRIV_0 0x4E0640
+
+#define mmDMA_IF_E_N_DMA1_MAX_RPRIV_1 0x4E0644
+
+#define mmDMA_IF_E_N_DMA1_MAX_RPRIV_2 0x4E0648
+
+#define mmDMA_IF_E_N_DMA1_MAX_RPRIV_3 0x4E064C
+
+#define mmDMA_IF_E_N_DMA1_MAX_RPRIV_4 0x4E0650
+
+#define mmDMA_IF_E_N_DMA1_MAX_RPRIV_5 0x4E0654
+
+#define mmDMA_IF_E_N_DMA1_MAX_RPRIV_6 0x4E0658
+
+#define mmDMA_IF_E_N_DMA1_MAX_RPRIV_7 0x4E065C
+
+#define mmDMA_IF_E_N_DMA1_MAX_RPRIV_8 0x4E0660
+
+#define mmDMA_IF_E_N_DMA1_MAX_RPRIV_9 0x4E0664
+
+#define mmDMA_IF_E_N_DMA1_MAX_RPRIV_10 0x4E0668
+
+#define mmDMA_IF_E_N_DMA1_MAX_RPRIV_11 0x4E066C
+
+#define mmDMA_IF_E_N_DMA1_MAX_RPRIV_12 0x4E0670
+
+#define mmDMA_IF_E_N_DMA1_MAX_RPRIV_13 0x4E0674
+
+#define mmDMA_IF_E_N_DMA1_MAX_RPRIV_14 0x4E0678
+
+#define mmDMA_IF_E_N_DMA1_MAX_RPRIV_15 0x4E067C
+
+#define mmDMA_IF_E_N_DMA1_MIN_WPRIV_0 0x4E0680
+
+#define mmDMA_IF_E_N_DMA1_MIN_WPRIV_1 0x4E0684
+
+#define mmDMA_IF_E_N_DMA1_MIN_WPRIV_2 0x4E0688
+
+#define mmDMA_IF_E_N_DMA1_MIN_WPRIV_3 0x4E068C
+
+#define mmDMA_IF_E_N_DMA1_MIN_WPRIV_4 0x4E0690
+
+#define mmDMA_IF_E_N_DMA1_MIN_WPRIV_5 0x4E0694
+
+#define mmDMA_IF_E_N_DMA1_MIN_WPRIV_6 0x4E0698
+
+#define mmDMA_IF_E_N_DMA1_MIN_WPRIV_7 0x4E069C
+
+#define mmDMA_IF_E_N_DMA1_MIN_WPRIV_8 0x4E06A0
+
+#define mmDMA_IF_E_N_DMA1_MIN_WPRIV_9 0x4E06A4
+
+#define mmDMA_IF_E_N_DMA1_MIN_WPRIV_10 0x4E06A8
+
+#define mmDMA_IF_E_N_DMA1_MIN_WPRIV_11 0x4E06AC
+
+#define mmDMA_IF_E_N_DMA1_MIN_WPRIV_12 0x4E06B0
+
+#define mmDMA_IF_E_N_DMA1_MIN_WPRIV_13 0x4E06B4
+
+#define mmDMA_IF_E_N_DMA1_MIN_WPRIV_14 0x4E06B8
+
+#define mmDMA_IF_E_N_DMA1_MIN_WPRIV_15 0x4E06BC
+
+#define mmDMA_IF_E_N_DMA1_MAX_WPRIV_0 0x4E06C0
+
+#define mmDMA_IF_E_N_DMA1_MAX_WPRIV_1 0x4E06C4
+
+#define mmDMA_IF_E_N_DMA1_MAX_WPRIV_2 0x4E06C8
+
+#define mmDMA_IF_E_N_DMA1_MAX_WPRIV_3 0x4E06CC
+
+#define mmDMA_IF_E_N_DMA1_MAX_WPRIV_4 0x4E06D0
+
+#define mmDMA_IF_E_N_DMA1_MAX_WPRIV_5 0x4E06D4
+
+#define mmDMA_IF_E_N_DMA1_MAX_WPRIV_6 0x4E06D8
+
+#define mmDMA_IF_E_N_DMA1_MAX_WPRIV_7 0x4E06DC
+
+#define mmDMA_IF_E_N_DMA1_MAX_WPRIV_8 0x4E06E0
+
+#define mmDMA_IF_E_N_DMA1_MAX_WPRIV_9 0x4E06E4
+
+#define mmDMA_IF_E_N_DMA1_MAX_WPRIV_10 0x4E06E8
+
+#define mmDMA_IF_E_N_DMA1_MAX_WPRIV_11 0x4E06EC
+
+#define mmDMA_IF_E_N_DMA1_MAX_WPRIV_12 0x4E06F0
+
+#define mmDMA_IF_E_N_DMA1_MAX_WPRIV_13 0x4E06F4
+
+#define mmDMA_IF_E_N_DMA1_MAX_WPRIV_14 0x4E06F8
+
+#define mmDMA_IF_E_N_DMA1_MAX_WPRIV_15 0x4E06FC
+
+#define mmDMA_IF_E_N_SOB_HIT_RPROT 0x4E0700
+
+#define mmDMA_IF_E_N_SOB_HIT_WPROT 0x4E0704
+
+#define mmDMA_IF_E_N_SOB_HIT_RPRIV 0x4E070C
+
+#define mmDMA_IF_E_N_SOB_HIT_WPRIV 0x4E0710
+
+#define mmDMA_IF_E_N_DMA0_HIT_RPROT 0x4E071C
+
+#define mmDMA_IF_E_N_DMA0_HIT_WPROT 0x4E0720
+
+#define mmDMA_IF_E_N_DMA0_HIT_RPRIV 0x4E0724
+
+#define mmDMA_IF_E_N_DMA0_HIT_WPRIV 0x4E0728
+
+#define mmDMA_IF_E_N_DMA1_HIT_RPROT 0x4E0730
+
+#define mmDMA_IF_E_N_DMA1_HIT_WPROT 0x4E0734
+
+#define mmDMA_IF_E_N_DMA1_HIT_RPRIV 0x4E0738
+
+#define mmDMA_IF_E_N_DMA1_HIT_WPRIV 0x4E073C
+
+#define mmDMA_IF_E_N_HBM_BIN 0x4E0800
+
+#define mmDMA_IF_E_N_MME_BIN 0x4E0804
+
+#define mmDMA_IF_E_N_TPC_BIN 0x4E0808
+
+#define mmDMA_IF_E_N_DMA_BIN 0x4E080C
+
+#define mmDMA_IF_E_N_SOB_CG_EN 0x4E0810
+
+#define mmDMA_IF_E_N_HBM_I2C_ADDR_0 0x4E0820
+
+#define mmDMA_IF_E_N_HBM_I2C_ADDR_1 0x4E0824
+
+#define mmDMA_IF_E_N_HBM_I2C_ADDR_2 0x4E0828
+
+#define mmDMA_IF_E_N_HBM_I2C_ADDR_3 0x4E082C
+
+#define mmDMA_IF_E_N_HBM_I2C_ADDR_4 0x4E0830
+
+#define mmDMA_IF_E_N_HBM_MISC 0x4E0834
+
+#endif /* ASIC_REG_DMA_IF_E_N_REGS_H_ */
diff --git a/drivers/accel/habanalabs/include/gaudi/asic_reg/dma_if_e_s_down_ch0_regs.h b/drivers/accel/habanalabs/include/gaudi/asic_reg/dma_if_e_s_down_ch0_regs.h
new file mode 100644
index 0000000000..cd61289a1e
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi/asic_reg/dma_if_e_s_down_ch0_regs.h
@@ -0,0 +1,896 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2016-2018 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ ** DO NOT EDIT BELOW **
+ ************************************/
+
+#ifndef ASIC_REG_DMA_IF_E_S_DOWN_CH0_REGS_H_
+#define ASIC_REG_DMA_IF_E_S_DOWN_CH0_REGS_H_
+
+/*
+ *****************************************
+ * DMA_IF_E_S_DOWN_CH0 (Prototype: RTR_CTRL)
+ *****************************************
+ */
+
+#define mmDMA_IF_E_S_DOWN_CH0_PERM_SEL 0x4A1108
+
+#define mmDMA_IF_E_S_DOWN_CH0_HBM_POLY_H3_0 0x4A1114
+
+#define mmDMA_IF_E_S_DOWN_CH0_HBM_POLY_H3_1 0x4A1118
+
+#define mmDMA_IF_E_S_DOWN_CH0_HBM_POLY_H3_2 0x4A111C
+
+#define mmDMA_IF_E_S_DOWN_CH0_HBM_POLY_H3_3 0x4A1120
+
+#define mmDMA_IF_E_S_DOWN_CH0_HBM_POLY_H3_4 0x4A1124
+
+#define mmDMA_IF_E_S_DOWN_CH0_HBM_POLY_H3_5 0x4A1128
+
+#define mmDMA_IF_E_S_DOWN_CH0_HBM_POLY_H3_6 0x4A112C
+
+#define mmDMA_IF_E_S_DOWN_CH0_HBM_POLY_H3_7 0x4A1130
+
+#define mmDMA_IF_E_S_DOWN_CH0_HBM_POLY_H3_8 0x4A1134
+
+#define mmDMA_IF_E_S_DOWN_CH0_HBM_POLY_H3_9 0x4A1138
+
+#define mmDMA_IF_E_S_DOWN_CH0_HBM_POLY_H3_10 0x4A113C
+
+#define mmDMA_IF_E_S_DOWN_CH0_HBM_POLY_H3_11 0x4A1140
+
+#define mmDMA_IF_E_S_DOWN_CH0_HBM_POLY_H3_12 0x4A1144
+
+#define mmDMA_IF_E_S_DOWN_CH0_HBM_POLY_H3_13 0x4A1148
+
+#define mmDMA_IF_E_S_DOWN_CH0_HBM_POLY_H3_14 0x4A114C
+
+#define mmDMA_IF_E_S_DOWN_CH0_HBM_POLY_H3_15 0x4A1150
+
+#define mmDMA_IF_E_S_DOWN_CH0_HBM_POLY_H3_16 0x4A1154
+
+#define mmDMA_IF_E_S_DOWN_CH0_HBM_POLY_H3_17 0x4A1158
+
+#define mmDMA_IF_E_S_DOWN_CH0_HBM_POLY_H3_18 0x4A115C
+
+#define mmDMA_IF_E_S_DOWN_CH0_HBM_POLY_H3_19 0x4A1160
+
+#define mmDMA_IF_E_S_DOWN_CH0_HBM_POLY_H3_20 0x4A1164
+
+#define mmDMA_IF_E_S_DOWN_CH0_HBM_POLY_H3_21 0x4A1168
+
+#define mmDMA_IF_E_S_DOWN_CH0_HBM_POLY_H3_22 0x4A116C
+
+#define mmDMA_IF_E_S_DOWN_CH0_HBM_POLY_H3_23 0x4A1170
+
+#define mmDMA_IF_E_S_DOWN_CH0_HBM_POLY_H3_24 0x4A1174
+
+#define mmDMA_IF_E_S_DOWN_CH0_HBM_POLY_H3_25 0x4A1178
+
+#define mmDMA_IF_E_S_DOWN_CH0_HBM_POLY_H3_26 0x4A117C
+
+#define mmDMA_IF_E_S_DOWN_CH0_HBM_POLY_H3_27 0x4A1180
+
+#define mmDMA_IF_E_S_DOWN_CH0_SRAM_POLY_H3_0 0x4A1184
+
+#define mmDMA_IF_E_S_DOWN_CH0_SRAM_POLY_H3_1 0x4A1188
+
+#define mmDMA_IF_E_S_DOWN_CH0_SRAM_POLY_H3_2 0x4A118C
+
+#define mmDMA_IF_E_S_DOWN_CH0_SRAM_POLY_H3_3 0x4A1190
+
+#define mmDMA_IF_E_S_DOWN_CH0_SRAM_POLY_H3_4 0x4A1194
+
+#define mmDMA_IF_E_S_DOWN_CH0_SRAM_POLY_H3_5 0x4A1198
+
+#define mmDMA_IF_E_S_DOWN_CH0_SRAM_POLY_H3_6 0x4A119C
+
+#define mmDMA_IF_E_S_DOWN_CH0_SRAM_POLY_H3_7 0x4A11A0
+
+#define mmDMA_IF_E_S_DOWN_CH0_SRAM_POLY_H3_8 0x4A11A4
+
+#define mmDMA_IF_E_S_DOWN_CH0_SRAM_POLY_H3_9 0x4A11A8
+
+#define mmDMA_IF_E_S_DOWN_CH0_SRAM_POLY_H3_10 0x4A11AC
+
+#define mmDMA_IF_E_S_DOWN_CH0_SRAM_POLY_H3_11 0x4A11B0
+
+#define mmDMA_IF_E_S_DOWN_CH0_SRAM_POLY_H3_12 0x4A11B4
+
+#define mmDMA_IF_E_S_DOWN_CH0_SRAM_POLY_H3_13 0x4A11B8
+
+#define mmDMA_IF_E_S_DOWN_CH0_SRAM_POLY_H3_14 0x4A11BC
+
+#define mmDMA_IF_E_S_DOWN_CH0_SCRAM_SRAM_EN 0x4A126C
+
+#define mmDMA_IF_E_S_DOWN_CH0_RL_HBM_EN 0x4A1274
+
+#define mmDMA_IF_E_S_DOWN_CH0_RL_HBM_SAT 0x4A1278
+
+#define mmDMA_IF_E_S_DOWN_CH0_RL_HBM_RST 0x4A127C
+
+#define mmDMA_IF_E_S_DOWN_CH0_RL_HBM_TIMEOUT 0x4A1280
+
+#define mmDMA_IF_E_S_DOWN_CH0_SCRAM_HBM_EN 0x4A1284
+
+#define mmDMA_IF_E_S_DOWN_CH0_RL_PCI_EN 0x4A1288
+
+#define mmDMA_IF_E_S_DOWN_CH0_RL_PCI_SAT 0x4A128C
+
+#define mmDMA_IF_E_S_DOWN_CH0_RL_PCI_RST 0x4A1290
+
+#define mmDMA_IF_E_S_DOWN_CH0_RL_PCI_TIMEOUT 0x4A1294
+
+#define mmDMA_IF_E_S_DOWN_CH0_RL_SRAM_EN 0x4A129C
+
+#define mmDMA_IF_E_S_DOWN_CH0_RL_SRAM_SAT 0x4A12A0
+
+#define mmDMA_IF_E_S_DOWN_CH0_RL_SRAM_RST 0x4A12A4
+
+#define mmDMA_IF_E_S_DOWN_CH0_RL_SRAM_TIMEOUT 0x4A12AC
+
+#define mmDMA_IF_E_S_DOWN_CH0_RL_SRAM_RED 0x4A12B4
+
+#define mmDMA_IF_E_S_DOWN_CH0_E2E_HBM_EN 0x4A12EC
+
+#define mmDMA_IF_E_S_DOWN_CH0_E2E_PCI_EN 0x4A12F0
+
+#define mmDMA_IF_E_S_DOWN_CH0_E2E_HBM_WR_SIZE 0x4A12F4
+
+#define mmDMA_IF_E_S_DOWN_CH0_E2E_PCI_WR_SIZE 0x4A12F8
+
+#define mmDMA_IF_E_S_DOWN_CH0_E2E_AW_PCI_CTR_SET_EN 0x4A1404
+
+#define mmDMA_IF_E_S_DOWN_CH0_E2E_AW_PCI_CTR_SET 0x4A1408
+
+#define mmDMA_IF_E_S_DOWN_CH0_E2E_AW_PCI_CTR_WRAP 0x4A140C
+
+#define mmDMA_IF_E_S_DOWN_CH0_E2E_AW_PCI_CTR_CNT 0x4A1410
+
+#define mmDMA_IF_E_S_DOWN_CH0_E2E_AW_HBM_CTR_SET_EN 0x4A1414
+
+#define mmDMA_IF_E_S_DOWN_CH0_E2E_AW_HBM_CTR_SET 0x4A1418
+
+#define mmDMA_IF_E_S_DOWN_CH0_E2E_HBM_RD_SIZE 0x4A141C
+
+#define mmDMA_IF_E_S_DOWN_CH0_E2E_PCI_RD_SIZE 0x4A1420
+
+#define mmDMA_IF_E_S_DOWN_CH0_E2E_AR_PCI_CTR_SET_EN 0x4A1424
+
+#define mmDMA_IF_E_S_DOWN_CH0_E2E_AR_PCI_CTR_SET 0x4A1428
+
+#define mmDMA_IF_E_S_DOWN_CH0_E2E_AR_PCI_CTR_WRAP 0x4A142C
+
+#define mmDMA_IF_E_S_DOWN_CH0_E2E_AR_PCI_CTR_CNT 0x4A1430
+
+#define mmDMA_IF_E_S_DOWN_CH0_E2E_AR_HBM_CTR_SET_EN 0x4A1434
+
+#define mmDMA_IF_E_S_DOWN_CH0_E2E_AR_HBM_CTR_SET 0x4A1438
+
+#define mmDMA_IF_E_S_DOWN_CH0_NL_HBM_SEL_0 0x4A1450
+
+#define mmDMA_IF_E_S_DOWN_CH0_NL_HBM_SEL_1 0x4A1454
+
+#define mmDMA_IF_E_S_DOWN_CH0_NON_LIN_EN 0x4A1480
+
+#define mmDMA_IF_E_S_DOWN_CH0_NL_SRAM_BANK_0 0x4A1500
+
+#define mmDMA_IF_E_S_DOWN_CH0_NL_SRAM_BANK_1 0x4A1504
+
+#define mmDMA_IF_E_S_DOWN_CH0_NL_SRAM_BANK_2 0x4A1508
+
+#define mmDMA_IF_E_S_DOWN_CH0_NL_SRAM_BANK_3 0x4A150C
+
+#define mmDMA_IF_E_S_DOWN_CH0_NL_SRAM_BANK_4 0x4A1510
+
+#define mmDMA_IF_E_S_DOWN_CH0_NL_SRAM_OFFSET_0 0x4A1514
+
+#define mmDMA_IF_E_S_DOWN_CH0_NL_SRAM_OFFSET_1 0x4A1520
+
+#define mmDMA_IF_E_S_DOWN_CH0_NL_SRAM_OFFSET_2 0x4A1524
+
+#define mmDMA_IF_E_S_DOWN_CH0_NL_SRAM_OFFSET_3 0x4A1528
+
+#define mmDMA_IF_E_S_DOWN_CH0_NL_SRAM_OFFSET_4 0x4A152C
+
+#define mmDMA_IF_E_S_DOWN_CH0_NL_SRAM_OFFSET_5 0x4A1530
+
+#define mmDMA_IF_E_S_DOWN_CH0_NL_SRAM_OFFSET_6 0x4A1534
+
+#define mmDMA_IF_E_S_DOWN_CH0_NL_SRAM_OFFSET_7 0x4A1538
+
+#define mmDMA_IF_E_S_DOWN_CH0_NL_SRAM_OFFSET_8 0x4A153C
+
+#define mmDMA_IF_E_S_DOWN_CH0_NL_SRAM_OFFSET_9 0x4A1540
+
+#define mmDMA_IF_E_S_DOWN_CH0_NL_HBM_OFFSET_0 0x4A1550
+
+#define mmDMA_IF_E_S_DOWN_CH0_NL_HBM_OFFSET_1 0x4A1554
+
+#define mmDMA_IF_E_S_DOWN_CH0_NL_HBM_OFFSET_2 0x4A1558
+
+#define mmDMA_IF_E_S_DOWN_CH0_NL_HBM_OFFSET_3 0x4A155C
+
+#define mmDMA_IF_E_S_DOWN_CH0_NL_HBM_OFFSET_4 0x4A1560
+
+#define mmDMA_IF_E_S_DOWN_CH0_NL_HBM_OFFSET_5 0x4A1564
+
+#define mmDMA_IF_E_S_DOWN_CH0_NL_HBM_OFFSET_6 0x4A1568
+
+#define mmDMA_IF_E_S_DOWN_CH0_NL_HBM_OFFSET_7 0x4A156C
+
+#define mmDMA_IF_E_S_DOWN_CH0_NL_HBM_OFFSET_8 0x4A1570
+
+#define mmDMA_IF_E_S_DOWN_CH0_NL_HBM_OFFSET_9 0x4A1574
+
+#define mmDMA_IF_E_S_DOWN_CH0_NL_HBM_OFFSET_10 0x4A1578
+
+#define mmDMA_IF_E_S_DOWN_CH0_NL_HBM_OFFSET_11 0x4A157C
+
+#define mmDMA_IF_E_S_DOWN_CH0_NL_HBM_OFFSET_12 0x4A1580
+
+#define mmDMA_IF_E_S_DOWN_CH0_NL_HBM_OFFSET_13 0x4A1584
+
+#define mmDMA_IF_E_S_DOWN_CH0_NL_HBM_OFFSET_14 0x4A1588
+
+#define mmDMA_IF_E_S_DOWN_CH0_NL_HBM_OFFSET_15 0x4A158C
+
+#define mmDMA_IF_E_S_DOWN_CH0_NL_HBM_OFFSET_16 0x4A1590
+
+#define mmDMA_IF_E_S_DOWN_CH0_NL_HBM_OFFSET_17 0x4A1594
+
+#define mmDMA_IF_E_S_DOWN_CH0_NL_HBM_OFFSET_18 0x4A1598
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_0 0x4A15E4
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_1 0x4A15E8
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_2 0x4A15EC
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_3 0x4A15F0
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_4 0x4A15F4
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_5 0x4A15F8
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_6 0x4A15FC
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_7 0x4A1600
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_8 0x4A1604
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_9 0x4A1608
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_10 0x4A160C
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_11 0x4A1610
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_12 0x4A1614
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_13 0x4A1618
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_14 0x4A161C
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_15 0x4A1620
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_0 0x4A1624
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_1 0x4A1628
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_2 0x4A162C
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_3 0x4A1630
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_4 0x4A1634
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_5 0x4A1638
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_6 0x4A163C
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_7 0x4A1640
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_8 0x4A1644
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_9 0x4A1648
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_10 0x4A164C
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_11 0x4A1650
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_12 0x4A1654
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_13 0x4A1658
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_14 0x4A165C
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_15 0x4A1660
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_0 0x4A1664
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_1 0x4A1668
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_2 0x4A166C
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_3 0x4A1670
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_4 0x4A1674
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_5 0x4A1678
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_6 0x4A167C
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_7 0x4A1680
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_8 0x4A1684
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_9 0x4A1688
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_10 0x4A168C
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_11 0x4A1690
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_12 0x4A1694
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_13 0x4A1698
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_14 0x4A169C
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_15 0x4A16A0
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_0 0x4A16A4
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_1 0x4A16A8
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_2 0x4A16AC
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_3 0x4A16B0
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_4 0x4A16B4
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_5 0x4A16B8
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_6 0x4A16BC
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_7 0x4A16C0
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_8 0x4A16C4
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_9 0x4A16C8
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_10 0x4A16CC
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_11 0x4A16D0
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_12 0x4A16D4
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_13 0x4A16D8
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_14 0x4A16DC
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_15 0x4A16E0
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_0 0x4A16E4
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_1 0x4A16E8
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_2 0x4A16EC
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_3 0x4A16F0
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_4 0x4A16F4
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_5 0x4A16F8
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_6 0x4A16FC
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_7 0x4A1700
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_8 0x4A1704
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_9 0x4A1708
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_10 0x4A170C
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_11 0x4A1710
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_12 0x4A1714
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_13 0x4A1718
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_14 0x4A171C
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_15 0x4A1720
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_0 0x4A1724
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_1 0x4A1728
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_2 0x4A172C
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_3 0x4A1730
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_4 0x4A1734
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_5 0x4A1738
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_6 0x4A173C
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_7 0x4A1740
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_8 0x4A1744
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_9 0x4A1748
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_10 0x4A174C
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_11 0x4A1750
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_12 0x4A1754
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_13 0x4A1758
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_14 0x4A175C
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_15 0x4A1760
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_0 0x4A1764
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_1 0x4A1768
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_2 0x4A176C
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_3 0x4A1770
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_4 0x4A1774
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_5 0x4A1778
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_6 0x4A177C
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_7 0x4A1780
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_8 0x4A1784
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_9 0x4A1788
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_10 0x4A178C
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_11 0x4A1790
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_12 0x4A1794
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_13 0x4A1798
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_14 0x4A179C
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_15 0x4A17A0
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_0 0x4A17A4
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_1 0x4A17A8
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_2 0x4A17AC
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_3 0x4A17B0
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_4 0x4A17B4
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_5 0x4A17B8
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_6 0x4A17BC
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_7 0x4A17C0
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_8 0x4A17C4
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_9 0x4A17C8
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_10 0x4A17CC
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_11 0x4A17D0
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_12 0x4A17D4
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_13 0x4A17D8
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_14 0x4A17DC
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_15 0x4A17E0
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_0 0x4A1824
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_1 0x4A1828
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_2 0x4A182C
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_3 0x4A1830
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_4 0x4A1834
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_5 0x4A1838
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_6 0x4A183C
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_7 0x4A1840
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_8 0x4A1844
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_9 0x4A1848
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_10 0x4A184C
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_11 0x4A1850
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_12 0x4A1854
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_13 0x4A1858
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_14 0x4A185C
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_15 0x4A1860
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_0 0x4A1864
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_1 0x4A1868
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_2 0x4A186C
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_3 0x4A1870
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_4 0x4A1874
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_5 0x4A1878
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_6 0x4A187C
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_7 0x4A1880
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_8 0x4A1884
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_9 0x4A1888
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_10 0x4A188C
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_11 0x4A1890
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_12 0x4A1894
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_13 0x4A1898
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_14 0x4A189C
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_15 0x4A18A0
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_0 0x4A18A4
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_1 0x4A18A8
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_2 0x4A18AC
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_3 0x4A18B0
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_4 0x4A18B4
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_5 0x4A18B8
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_6 0x4A18BC
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_7 0x4A18C0
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_8 0x4A18C4
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_9 0x4A18C8
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_10 0x4A18CC
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_11 0x4A18D0
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_12 0x4A18D4
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_13 0x4A18D8
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_14 0x4A18DC
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_15 0x4A18E0
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_0 0x4A18E4
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_1 0x4A18E8
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_2 0x4A18EC
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_3 0x4A18F0
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_4 0x4A18F4
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_5 0x4A18F8
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_6 0x4A18FC
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_7 0x4A1900
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_8 0x4A1904
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_9 0x4A1908
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_10 0x4A190C
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_11 0x4A1910
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_12 0x4A1914
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_13 0x4A1918
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_14 0x4A191C
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_15 0x4A1920
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_0 0x4A1924
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_1 0x4A1928
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_2 0x4A192C
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_3 0x4A1930
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_4 0x4A1934
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_5 0x4A1938
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_6 0x4A193C
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_7 0x4A1940
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_8 0x4A1944
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_9 0x4A1948
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_10 0x4A194C
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_11 0x4A1950
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_12 0x4A1954
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_13 0x4A1958
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_14 0x4A195C
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_15 0x4A1960
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_0 0x4A1964
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_1 0x4A1968
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_2 0x4A196C
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_3 0x4A1970
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_4 0x4A1974
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_5 0x4A1978
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_6 0x4A197C
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_7 0x4A1980
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_8 0x4A1984
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_9 0x4A1988
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_10 0x4A198C
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_11 0x4A1990
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_12 0x4A1994
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_13 0x4A1998
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_14 0x4A199C
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_15 0x4A19A0
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_0 0x4A19A4
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_1 0x4A19A8
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_2 0x4A19AC
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_3 0x4A19B0
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_4 0x4A19B4
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_5 0x4A19B8
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_6 0x4A19BC
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_7 0x4A19C0
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_8 0x4A19C4
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_9 0x4A19C8
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_10 0x4A19CC
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_11 0x4A19D0
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_12 0x4A19D4
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_13 0x4A19D8
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_14 0x4A19DC
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_15 0x4A19E0
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_0 0x4A19E4
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_1 0x4A19E8
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_2 0x4A19EC
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_3 0x4A19F0
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_4 0x4A19F4
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_5 0x4A19F8
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_6 0x4A19FC
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_7 0x4A1A00
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_8 0x4A1A04
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_9 0x4A1A08
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_10 0x4A1A0C
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_11 0x4A1A10
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_12 0x4A1A14
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_13 0x4A1A18
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_14 0x4A1A1C
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_15 0x4A1A20
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_HIT_AW 0x4A1A64
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_HIT_AR 0x4A1A68
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_HIT_AW 0x4A1A6C
+
+#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_HIT_AR 0x4A1A70
+
+#define mmDMA_IF_E_S_DOWN_CH0_RGL_CFG 0x4A1B64
+
+#define mmDMA_IF_E_S_DOWN_CH0_RGL_SHIFT 0x4A1B68
+
+#define mmDMA_IF_E_S_DOWN_CH0_RGL_EXPECTED_LAT_0 0x4A1B6C
+
+#define mmDMA_IF_E_S_DOWN_CH0_RGL_EXPECTED_LAT_1 0x4A1B70
+
+#define mmDMA_IF_E_S_DOWN_CH0_RGL_EXPECTED_LAT_2 0x4A1B74
+
+#define mmDMA_IF_E_S_DOWN_CH0_RGL_EXPECTED_LAT_3 0x4A1B78
+
+#define mmDMA_IF_E_S_DOWN_CH0_RGL_EXPECTED_LAT_4 0x4A1B7C
+
+#define mmDMA_IF_E_S_DOWN_CH0_RGL_EXPECTED_LAT_5 0x4A1B80
+
+#define mmDMA_IF_E_S_DOWN_CH0_RGL_EXPECTED_LAT_6 0x4A1B84
+
+#define mmDMA_IF_E_S_DOWN_CH0_RGL_EXPECTED_LAT_7 0x4A1B88
+
+#define mmDMA_IF_E_S_DOWN_CH0_RGL_TOKEN_0 0x4A1BAC
+
+#define mmDMA_IF_E_S_DOWN_CH0_RGL_TOKEN_1 0x4A1BB0
+
+#define mmDMA_IF_E_S_DOWN_CH0_RGL_TOKEN_2 0x4A1BB4
+
+#define mmDMA_IF_E_S_DOWN_CH0_RGL_TOKEN_3 0x4A1BB8
+
+#define mmDMA_IF_E_S_DOWN_CH0_RGL_TOKEN_4 0x4A1BBC
+
+#define mmDMA_IF_E_S_DOWN_CH0_RGL_TOKEN_5 0x4A1BC0
+
+#define mmDMA_IF_E_S_DOWN_CH0_RGL_TOKEN_6 0x4A1BC4
+
+#define mmDMA_IF_E_S_DOWN_CH0_RGL_TOKEN_7 0x4A1BC8
+
+#define mmDMA_IF_E_S_DOWN_CH0_RGL_BANK_ID_0 0x4A1BEC
+
+#define mmDMA_IF_E_S_DOWN_CH0_RGL_BANK_ID_1 0x4A1BF0
+
+#define mmDMA_IF_E_S_DOWN_CH0_RGL_BANK_ID_2 0x4A1BF4
+
+#define mmDMA_IF_E_S_DOWN_CH0_RGL_BANK_ID_3 0x4A1BF8
+
+#define mmDMA_IF_E_S_DOWN_CH0_RGL_BANK_ID_4 0x4A1BFC
+
+#define mmDMA_IF_E_S_DOWN_CH0_RGL_BANK_ID_5 0x4A1C00
+
+#define mmDMA_IF_E_S_DOWN_CH0_RGL_BANK_ID_6 0x4A1C04
+
+#define mmDMA_IF_E_S_DOWN_CH0_RGL_BANK_ID_7 0x4A1C08
+
+#define mmDMA_IF_E_S_DOWN_CH0_RGL_WDT 0x4A1C2C
+
+#define mmDMA_IF_E_S_DOWN_CH0_E2E_AR_HBM0_CH0_CTR_WRAP 0x4A1C30
+
+#define mmDMA_IF_E_S_DOWN_CH0_E2E_AR_HBM0_CH1_CTR_WRAP 0x4A1C34
+
+#define mmDMA_IF_E_S_DOWN_CH0_E2E_AR_HBM1_CH0_CTR_WRAP 0x4A1C38
+
+#define mmDMA_IF_E_S_DOWN_CH0_E2E_AR_HBM1_CH1_CTR_WRAP 0x4A1C3C
+
+#define mmDMA_IF_E_S_DOWN_CH0_E2E_AR_HBM2_CH0_CTR_WRAP 0x4A1C40
+
+#define mmDMA_IF_E_S_DOWN_CH0_E2E_AR_HBM2_CH1_CTR_WRAP 0x4A1C44
+
+#define mmDMA_IF_E_S_DOWN_CH0_E2E_AR_HBM3_CH0_CTR_WRAP 0x4A1C48
+
+#define mmDMA_IF_E_S_DOWN_CH0_E2E_AR_HBM3_CH1_CTR_WRAP 0x4A1C4C
+
+#define mmDMA_IF_E_S_DOWN_CH0_E2E_AR_HBM0_CH0_CTR_CNT 0x4A1C50
+
+#define mmDMA_IF_E_S_DOWN_CH0_E2E_AR_HBM0_CH1_CTR_CNT 0x4A1C54
+
+#define mmDMA_IF_E_S_DOWN_CH0_E2E_AR_HBM1_CH0_CTR_CNT 0x4A1C58
+
+#define mmDMA_IF_E_S_DOWN_CH0_E2E_AR_HBM1_CH1_CTR_CNT 0x4A1C5C
+
+#define mmDMA_IF_E_S_DOWN_CH0_E2E_AR_HBM2_CH0_CTR_CNT 0x4A1C60
+
+#define mmDMA_IF_E_S_DOWN_CH0_E2E_AR_HBM2_CH1_CTR_CNT 0x4A1C64
+
+#define mmDMA_IF_E_S_DOWN_CH0_E2E_AR_HBM3_CH0_CTR_CNT 0x4A1C68
+
+#define mmDMA_IF_E_S_DOWN_CH0_E2E_AR_HBM3_CH1_CTR_CNT 0x4A1C6C
+
+#define mmDMA_IF_E_S_DOWN_CH0_E2E_AW_HBM0_CH0_CTR_WRAP 0x4A1C70
+
+#define mmDMA_IF_E_S_DOWN_CH0_E2E_AW_HBM0_CH1_CTR_WRAP 0x4A1C74
+
+#define mmDMA_IF_E_S_DOWN_CH0_E2E_AW_HBM1_CH0_CTR_WRAP 0x4A1C78
+
+#define mmDMA_IF_E_S_DOWN_CH0_E2E_AW_HBM1_CH1_CTR_WRAP 0x4A1C7C
+
+#define mmDMA_IF_E_S_DOWN_CH0_E2E_AW_HBM2_CH0_CTR_WRAP 0x4A1C80
+
+#define mmDMA_IF_E_S_DOWN_CH0_E2E_AW_HBM2_CH1_CTR_WRAP 0x4A1C84
+
+#define mmDMA_IF_E_S_DOWN_CH0_E2E_AW_HBM3_CH0_CTR_WRAP 0x4A1C88
+
+#define mmDMA_IF_E_S_DOWN_CH0_E2E_AW_HBM3_CH1_CTR_WRAP 0x4A1C8C
+
+#define mmDMA_IF_E_S_DOWN_CH0_E2E_AW_HBM0_CH0_CTR_CNT 0x4A1C90
+
+#define mmDMA_IF_E_S_DOWN_CH0_E2E_AW_HBM0_CH1_CTR_CNT 0x4A1C94
+
+#define mmDMA_IF_E_S_DOWN_CH0_E2E_AW_HBM1_CH0_CTR_CNT 0x4A1C98
+
+#define mmDMA_IF_E_S_DOWN_CH0_E2E_AW_HBM1_CH1_CTR_CNT 0x4A1C9C
+
+#define mmDMA_IF_E_S_DOWN_CH0_E2E_AW_HBM2_CH0_CTR_CNT 0x4A1CA0
+
+#define mmDMA_IF_E_S_DOWN_CH0_E2E_AW_HBM2_CH1_CTR_CNT 0x4A1CA4
+
+#define mmDMA_IF_E_S_DOWN_CH0_E2E_AW_HBM3_CH0_CTR_CNT 0x4A1CA8
+
+#define mmDMA_IF_E_S_DOWN_CH0_E2E_AW_HBM3_CH1_CTR_CNT 0x4A1CAC
+
+#define mmDMA_IF_E_S_DOWN_CH0_NL_HBM_PC_SEL_0 0x4A1CB0
+
+#define mmDMA_IF_E_S_DOWN_CH0_NL_HBM_PC_SEL_1 0x4A1CB4
+
+#define mmDMA_IF_E_S_DOWN_CH0_NL_HBM_PC_SEL_2 0x4A1CB8
+
+#define mmDMA_IF_E_S_DOWN_CH0_NL_HBM_PC_SEL_3 0x4A1CBC
+
+#endif /* ASIC_REG_DMA_IF_E_S_DOWN_CH0_REGS_H_ */
diff --git a/drivers/accel/habanalabs/include/gaudi/asic_reg/dma_if_e_s_down_ch1_regs.h b/drivers/accel/habanalabs/include/gaudi/asic_reg/dma_if_e_s_down_ch1_regs.h
new file mode 100644
index 0000000000..3f32370a14
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi/asic_reg/dma_if_e_s_down_ch1_regs.h
@@ -0,0 +1,896 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2016-2018 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ ** DO NOT EDIT BELOW **
+ ************************************/
+
+#ifndef ASIC_REG_DMA_IF_E_S_DOWN_CH1_REGS_H_
+#define ASIC_REG_DMA_IF_E_S_DOWN_CH1_REGS_H_
+
+/*
+ *****************************************
+ * DMA_IF_E_S_DOWN_CH1 (Prototype: RTR_CTRL)
+ *****************************************
+ */
+
+#define mmDMA_IF_E_S_DOWN_CH1_PERM_SEL 0x4A2108
+
+#define mmDMA_IF_E_S_DOWN_CH1_HBM_POLY_H3_0 0x4A2114
+
+#define mmDMA_IF_E_S_DOWN_CH1_HBM_POLY_H3_1 0x4A2118
+
+#define mmDMA_IF_E_S_DOWN_CH1_HBM_POLY_H3_2 0x4A211C
+
+#define mmDMA_IF_E_S_DOWN_CH1_HBM_POLY_H3_3 0x4A2120
+
+#define mmDMA_IF_E_S_DOWN_CH1_HBM_POLY_H3_4 0x4A2124
+
+#define mmDMA_IF_E_S_DOWN_CH1_HBM_POLY_H3_5 0x4A2128
+
+#define mmDMA_IF_E_S_DOWN_CH1_HBM_POLY_H3_6 0x4A212C
+
+#define mmDMA_IF_E_S_DOWN_CH1_HBM_POLY_H3_7 0x4A2130
+
+#define mmDMA_IF_E_S_DOWN_CH1_HBM_POLY_H3_8 0x4A2134
+
+#define mmDMA_IF_E_S_DOWN_CH1_HBM_POLY_H3_9 0x4A2138
+
+#define mmDMA_IF_E_S_DOWN_CH1_HBM_POLY_H3_10 0x4A213C
+
+#define mmDMA_IF_E_S_DOWN_CH1_HBM_POLY_H3_11 0x4A2140
+
+#define mmDMA_IF_E_S_DOWN_CH1_HBM_POLY_H3_12 0x4A2144
+
+#define mmDMA_IF_E_S_DOWN_CH1_HBM_POLY_H3_13 0x4A2148
+
+#define mmDMA_IF_E_S_DOWN_CH1_HBM_POLY_H3_14 0x4A214C
+
+#define mmDMA_IF_E_S_DOWN_CH1_HBM_POLY_H3_15 0x4A2150
+
+#define mmDMA_IF_E_S_DOWN_CH1_HBM_POLY_H3_16 0x4A2154
+
+#define mmDMA_IF_E_S_DOWN_CH1_HBM_POLY_H3_17 0x4A2158
+
+#define mmDMA_IF_E_S_DOWN_CH1_HBM_POLY_H3_18 0x4A215C
+
+#define mmDMA_IF_E_S_DOWN_CH1_HBM_POLY_H3_19 0x4A2160
+
+#define mmDMA_IF_E_S_DOWN_CH1_HBM_POLY_H3_20 0x4A2164
+
+#define mmDMA_IF_E_S_DOWN_CH1_HBM_POLY_H3_21 0x4A2168
+
+#define mmDMA_IF_E_S_DOWN_CH1_HBM_POLY_H3_22 0x4A216C
+
+#define mmDMA_IF_E_S_DOWN_CH1_HBM_POLY_H3_23 0x4A2170
+
+#define mmDMA_IF_E_S_DOWN_CH1_HBM_POLY_H3_24 0x4A2174
+
+#define mmDMA_IF_E_S_DOWN_CH1_HBM_POLY_H3_25 0x4A2178
+
+#define mmDMA_IF_E_S_DOWN_CH1_HBM_POLY_H3_26 0x4A217C
+
+#define mmDMA_IF_E_S_DOWN_CH1_HBM_POLY_H3_27 0x4A2180
+
+#define mmDMA_IF_E_S_DOWN_CH1_SRAM_POLY_H3_0 0x4A2184
+
+#define mmDMA_IF_E_S_DOWN_CH1_SRAM_POLY_H3_1 0x4A2188
+
+#define mmDMA_IF_E_S_DOWN_CH1_SRAM_POLY_H3_2 0x4A218C
+
+#define mmDMA_IF_E_S_DOWN_CH1_SRAM_POLY_H3_3 0x4A2190
+
+#define mmDMA_IF_E_S_DOWN_CH1_SRAM_POLY_H3_4 0x4A2194
+
+#define mmDMA_IF_E_S_DOWN_CH1_SRAM_POLY_H3_5 0x4A2198
+
+#define mmDMA_IF_E_S_DOWN_CH1_SRAM_POLY_H3_6 0x4A219C
+
+#define mmDMA_IF_E_S_DOWN_CH1_SRAM_POLY_H3_7 0x4A21A0
+
+#define mmDMA_IF_E_S_DOWN_CH1_SRAM_POLY_H3_8 0x4A21A4
+
+#define mmDMA_IF_E_S_DOWN_CH1_SRAM_POLY_H3_9 0x4A21A8
+
+#define mmDMA_IF_E_S_DOWN_CH1_SRAM_POLY_H3_10 0x4A21AC
+
+#define mmDMA_IF_E_S_DOWN_CH1_SRAM_POLY_H3_11 0x4A21B0
+
+#define mmDMA_IF_E_S_DOWN_CH1_SRAM_POLY_H3_12 0x4A21B4
+
+#define mmDMA_IF_E_S_DOWN_CH1_SRAM_POLY_H3_13 0x4A21B8
+
+#define mmDMA_IF_E_S_DOWN_CH1_SRAM_POLY_H3_14 0x4A21BC
+
+#define mmDMA_IF_E_S_DOWN_CH1_SCRAM_SRAM_EN 0x4A226C
+
+#define mmDMA_IF_E_S_DOWN_CH1_RL_HBM_EN 0x4A2274
+
+#define mmDMA_IF_E_S_DOWN_CH1_RL_HBM_SAT 0x4A2278
+
+#define mmDMA_IF_E_S_DOWN_CH1_RL_HBM_RST 0x4A227C
+
+#define mmDMA_IF_E_S_DOWN_CH1_RL_HBM_TIMEOUT 0x4A2280
+
+#define mmDMA_IF_E_S_DOWN_CH1_SCRAM_HBM_EN 0x4A2284
+
+#define mmDMA_IF_E_S_DOWN_CH1_RL_PCI_EN 0x4A2288
+
+#define mmDMA_IF_E_S_DOWN_CH1_RL_PCI_SAT 0x4A228C
+
+#define mmDMA_IF_E_S_DOWN_CH1_RL_PCI_RST 0x4A2290
+
+#define mmDMA_IF_E_S_DOWN_CH1_RL_PCI_TIMEOUT 0x4A2294
+
+#define mmDMA_IF_E_S_DOWN_CH1_RL_SRAM_EN 0x4A229C
+
+#define mmDMA_IF_E_S_DOWN_CH1_RL_SRAM_SAT 0x4A22A0
+
+#define mmDMA_IF_E_S_DOWN_CH1_RL_SRAM_RST 0x4A22A4
+
+#define mmDMA_IF_E_S_DOWN_CH1_RL_SRAM_TIMEOUT 0x4A22AC
+
+#define mmDMA_IF_E_S_DOWN_CH1_RL_SRAM_RED 0x4A22B4
+
+#define mmDMA_IF_E_S_DOWN_CH1_E2E_HBM_EN 0x4A22EC
+
+#define mmDMA_IF_E_S_DOWN_CH1_E2E_PCI_EN 0x4A22F0
+
+#define mmDMA_IF_E_S_DOWN_CH1_E2E_HBM_WR_SIZE 0x4A22F4
+
+#define mmDMA_IF_E_S_DOWN_CH1_E2E_PCI_WR_SIZE 0x4A22F8
+
+#define mmDMA_IF_E_S_DOWN_CH1_E2E_AW_PCI_CTR_SET_EN 0x4A2404
+
+#define mmDMA_IF_E_S_DOWN_CH1_E2E_AW_PCI_CTR_SET 0x4A2408
+
+#define mmDMA_IF_E_S_DOWN_CH1_E2E_AW_PCI_CTR_WRAP 0x4A240C
+
+#define mmDMA_IF_E_S_DOWN_CH1_E2E_AW_PCI_CTR_CNT 0x4A2410
+
+#define mmDMA_IF_E_S_DOWN_CH1_E2E_AW_HBM_CTR_SET_EN 0x4A2414
+
+#define mmDMA_IF_E_S_DOWN_CH1_E2E_AW_HBM_CTR_SET 0x4A2418
+
+#define mmDMA_IF_E_S_DOWN_CH1_E2E_HBM_RD_SIZE 0x4A241C
+
+#define mmDMA_IF_E_S_DOWN_CH1_E2E_PCI_RD_SIZE 0x4A2420
+
+#define mmDMA_IF_E_S_DOWN_CH1_E2E_AR_PCI_CTR_SET_EN 0x4A2424
+
+#define mmDMA_IF_E_S_DOWN_CH1_E2E_AR_PCI_CTR_SET 0x4A2428
+
+#define mmDMA_IF_E_S_DOWN_CH1_E2E_AR_PCI_CTR_WRAP 0x4A242C
+
+#define mmDMA_IF_E_S_DOWN_CH1_E2E_AR_PCI_CTR_CNT 0x4A2430
+
+#define mmDMA_IF_E_S_DOWN_CH1_E2E_AR_HBM_CTR_SET_EN 0x4A2434
+
+#define mmDMA_IF_E_S_DOWN_CH1_E2E_AR_HBM_CTR_SET 0x4A2438
+
+#define mmDMA_IF_E_S_DOWN_CH1_NL_HBM_SEL_0 0x4A2450
+
+#define mmDMA_IF_E_S_DOWN_CH1_NL_HBM_SEL_1 0x4A2454
+
+#define mmDMA_IF_E_S_DOWN_CH1_NON_LIN_EN 0x4A2480
+
+#define mmDMA_IF_E_S_DOWN_CH1_NL_SRAM_BANK_0 0x4A2500
+
+#define mmDMA_IF_E_S_DOWN_CH1_NL_SRAM_BANK_1 0x4A2504
+
+#define mmDMA_IF_E_S_DOWN_CH1_NL_SRAM_BANK_2 0x4A2508
+
+#define mmDMA_IF_E_S_DOWN_CH1_NL_SRAM_BANK_3 0x4A250C
+
+#define mmDMA_IF_E_S_DOWN_CH1_NL_SRAM_BANK_4 0x4A2510
+
+#define mmDMA_IF_E_S_DOWN_CH1_NL_SRAM_OFFSET_0 0x4A2514
+
+#define mmDMA_IF_E_S_DOWN_CH1_NL_SRAM_OFFSET_1 0x4A2520
+
+#define mmDMA_IF_E_S_DOWN_CH1_NL_SRAM_OFFSET_2 0x4A2524
+
+#define mmDMA_IF_E_S_DOWN_CH1_NL_SRAM_OFFSET_3 0x4A2528
+
+#define mmDMA_IF_E_S_DOWN_CH1_NL_SRAM_OFFSET_4 0x4A252C
+
+#define mmDMA_IF_E_S_DOWN_CH1_NL_SRAM_OFFSET_5 0x4A2530
+
+#define mmDMA_IF_E_S_DOWN_CH1_NL_SRAM_OFFSET_6 0x4A2534
+
+#define mmDMA_IF_E_S_DOWN_CH1_NL_SRAM_OFFSET_7 0x4A2538
+
+#define mmDMA_IF_E_S_DOWN_CH1_NL_SRAM_OFFSET_8 0x4A253C
+
+#define mmDMA_IF_E_S_DOWN_CH1_NL_SRAM_OFFSET_9 0x4A2540
+
+#define mmDMA_IF_E_S_DOWN_CH1_NL_HBM_OFFSET_0 0x4A2550
+
+#define mmDMA_IF_E_S_DOWN_CH1_NL_HBM_OFFSET_1 0x4A2554
+
+#define mmDMA_IF_E_S_DOWN_CH1_NL_HBM_OFFSET_2 0x4A2558
+
+#define mmDMA_IF_E_S_DOWN_CH1_NL_HBM_OFFSET_3 0x4A255C
+
+#define mmDMA_IF_E_S_DOWN_CH1_NL_HBM_OFFSET_4 0x4A2560
+
+#define mmDMA_IF_E_S_DOWN_CH1_NL_HBM_OFFSET_5 0x4A2564
+
+#define mmDMA_IF_E_S_DOWN_CH1_NL_HBM_OFFSET_6 0x4A2568
+
+#define mmDMA_IF_E_S_DOWN_CH1_NL_HBM_OFFSET_7 0x4A256C
+
+#define mmDMA_IF_E_S_DOWN_CH1_NL_HBM_OFFSET_8 0x4A2570
+
+#define mmDMA_IF_E_S_DOWN_CH1_NL_HBM_OFFSET_9 0x4A2574
+
+#define mmDMA_IF_E_S_DOWN_CH1_NL_HBM_OFFSET_10 0x4A2578
+
+#define mmDMA_IF_E_S_DOWN_CH1_NL_HBM_OFFSET_11 0x4A257C
+
+#define mmDMA_IF_E_S_DOWN_CH1_NL_HBM_OFFSET_12 0x4A2580
+
+#define mmDMA_IF_E_S_DOWN_CH1_NL_HBM_OFFSET_13 0x4A2584
+
+#define mmDMA_IF_E_S_DOWN_CH1_NL_HBM_OFFSET_14 0x4A2588
+
+#define mmDMA_IF_E_S_DOWN_CH1_NL_HBM_OFFSET_15 0x4A258C
+
+#define mmDMA_IF_E_S_DOWN_CH1_NL_HBM_OFFSET_16 0x4A2590
+
+#define mmDMA_IF_E_S_DOWN_CH1_NL_HBM_OFFSET_17 0x4A2594
+
+#define mmDMA_IF_E_S_DOWN_CH1_NL_HBM_OFFSET_18 0x4A2598
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_0 0x4A25E4
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_1 0x4A25E8
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_2 0x4A25EC
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_3 0x4A25F0
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_4 0x4A25F4
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_5 0x4A25F8
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_6 0x4A25FC
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_7 0x4A2600
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_8 0x4A2604
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_9 0x4A2608
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_10 0x4A260C
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_11 0x4A2610
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_12 0x4A2614
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_13 0x4A2618
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_14 0x4A261C
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_15 0x4A2620
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_0 0x4A2624
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_1 0x4A2628
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_2 0x4A262C
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_3 0x4A2630
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_4 0x4A2634
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_5 0x4A2638
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_6 0x4A263C
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_7 0x4A2640
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_8 0x4A2644
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_9 0x4A2648
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_10 0x4A264C
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_11 0x4A2650
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_12 0x4A2654
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_13 0x4A2658
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_14 0x4A265C
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_15 0x4A2660
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_0 0x4A2664
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_1 0x4A2668
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_2 0x4A266C
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_3 0x4A2670
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_4 0x4A2674
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_5 0x4A2678
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_6 0x4A267C
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_7 0x4A2680
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_8 0x4A2684
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_9 0x4A2688
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_10 0x4A268C
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_11 0x4A2690
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_12 0x4A2694
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_13 0x4A2698
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_14 0x4A269C
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_15 0x4A26A0
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_0 0x4A26A4
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_1 0x4A26A8
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_2 0x4A26AC
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_3 0x4A26B0
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_4 0x4A26B4
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_5 0x4A26B8
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_6 0x4A26BC
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_7 0x4A26C0
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_8 0x4A26C4
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_9 0x4A26C8
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_10 0x4A26CC
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_11 0x4A26D0
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_12 0x4A26D4
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_13 0x4A26D8
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_14 0x4A26DC
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_15 0x4A26E0
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_0 0x4A26E4
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_1 0x4A26E8
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_2 0x4A26EC
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_3 0x4A26F0
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_4 0x4A26F4
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_5 0x4A26F8
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_6 0x4A26FC
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_7 0x4A2700
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_8 0x4A2704
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_9 0x4A2708
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_10 0x4A270C
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_11 0x4A2710
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_12 0x4A2714
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_13 0x4A2718
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_14 0x4A271C
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_15 0x4A2720
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_0 0x4A2724
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_1 0x4A2728
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_2 0x4A272C
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_3 0x4A2730
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_4 0x4A2734
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_5 0x4A2738
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_6 0x4A273C
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_7 0x4A2740
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_8 0x4A2744
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_9 0x4A2748
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_10 0x4A274C
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_11 0x4A2750
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_12 0x4A2754
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_13 0x4A2758
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_14 0x4A275C
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_15 0x4A2760
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_0 0x4A2764
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_1 0x4A2768
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_2 0x4A276C
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_3 0x4A2770
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_4 0x4A2774
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_5 0x4A2778
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_6 0x4A277C
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_7 0x4A2780
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_8 0x4A2784
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_9 0x4A2788
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_10 0x4A278C
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_11 0x4A2790
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_12 0x4A2794
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_13 0x4A2798
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_14 0x4A279C
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_15 0x4A27A0
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_0 0x4A27A4
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_1 0x4A27A8
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_2 0x4A27AC
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_3 0x4A27B0
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_4 0x4A27B4
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_5 0x4A27B8
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_6 0x4A27BC
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_7 0x4A27C0
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_8 0x4A27C4
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_9 0x4A27C8
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_10 0x4A27CC
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_11 0x4A27D0
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_12 0x4A27D4
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_13 0x4A27D8
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_14 0x4A27DC
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_15 0x4A27E0
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_0 0x4A2824
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_1 0x4A2828
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_2 0x4A282C
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_3 0x4A2830
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_4 0x4A2834
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_5 0x4A2838
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_6 0x4A283C
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_7 0x4A2840
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_8 0x4A2844
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_9 0x4A2848
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_10 0x4A284C
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_11 0x4A2850
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_12 0x4A2854
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_13 0x4A2858
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_14 0x4A285C
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_15 0x4A2860
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_0 0x4A2864
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_1 0x4A2868
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_2 0x4A286C
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_3 0x4A2870
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_4 0x4A2874
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_5 0x4A2878
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_6 0x4A287C
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_7 0x4A2880
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_8 0x4A2884
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_9 0x4A2888
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_10 0x4A288C
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_11 0x4A2890
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_12 0x4A2894
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_13 0x4A2898
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_14 0x4A289C
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_15 0x4A28A0
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_0 0x4A28A4
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_1 0x4A28A8
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_2 0x4A28AC
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_3 0x4A28B0
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_4 0x4A28B4
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_5 0x4A28B8
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_6 0x4A28BC
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_7 0x4A28C0
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_8 0x4A28C4
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_9 0x4A28C8
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_10 0x4A28CC
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_11 0x4A28D0
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_12 0x4A28D4
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_13 0x4A28D8
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_14 0x4A28DC
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_15 0x4A28E0
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_0 0x4A28E4
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_1 0x4A28E8
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_2 0x4A28EC
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_3 0x4A28F0
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_4 0x4A28F4
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_5 0x4A28F8
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_6 0x4A28FC
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_7 0x4A2900
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_8 0x4A2904
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_9 0x4A2908
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_10 0x4A290C
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_11 0x4A2910
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_12 0x4A2914
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_13 0x4A2918
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_14 0x4A291C
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_15 0x4A2920
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_0 0x4A2924
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_1 0x4A2928
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_2 0x4A292C
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_3 0x4A2930
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_4 0x4A2934
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_5 0x4A2938
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_6 0x4A293C
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_7 0x4A2940
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_8 0x4A2944
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_9 0x4A2948
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_10 0x4A294C
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_11 0x4A2950
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_12 0x4A2954
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_13 0x4A2958
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_14 0x4A295C
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_15 0x4A2960
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_0 0x4A2964
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_1 0x4A2968
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_2 0x4A296C
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_3 0x4A2970
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_4 0x4A2974
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_5 0x4A2978
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_6 0x4A297C
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_7 0x4A2980
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_8 0x4A2984
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_9 0x4A2988
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_10 0x4A298C
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_11 0x4A2990
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_12 0x4A2994
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_13 0x4A2998
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_14 0x4A299C
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_15 0x4A29A0
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_0 0x4A29A4
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_1 0x4A29A8
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_2 0x4A29AC
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_3 0x4A29B0
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_4 0x4A29B4
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_5 0x4A29B8
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_6 0x4A29BC
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_7 0x4A29C0
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_8 0x4A29C4
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_9 0x4A29C8
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_10 0x4A29CC
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_11 0x4A29D0
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_12 0x4A29D4
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_13 0x4A29D8
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_14 0x4A29DC
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_15 0x4A29E0
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_0 0x4A29E4
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_1 0x4A29E8
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_2 0x4A29EC
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_3 0x4A29F0
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_4 0x4A29F4
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_5 0x4A29F8
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_6 0x4A29FC
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_7 0x4A2A00
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_8 0x4A2A04
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_9 0x4A2A08
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_10 0x4A2A0C
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_11 0x4A2A10
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_12 0x4A2A14
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_13 0x4A2A18
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_14 0x4A2A1C
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_15 0x4A2A20
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_HIT_AW 0x4A2A64
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_HIT_AR 0x4A2A68
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_HIT_AW 0x4A2A6C
+
+#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_HIT_AR 0x4A2A70
+
+#define mmDMA_IF_E_S_DOWN_CH1_RGL_CFG 0x4A2B64
+
+#define mmDMA_IF_E_S_DOWN_CH1_RGL_SHIFT 0x4A2B68
+
+#define mmDMA_IF_E_S_DOWN_CH1_RGL_EXPECTED_LAT_0 0x4A2B6C
+
+#define mmDMA_IF_E_S_DOWN_CH1_RGL_EXPECTED_LAT_1 0x4A2B70
+
+#define mmDMA_IF_E_S_DOWN_CH1_RGL_EXPECTED_LAT_2 0x4A2B74
+
+#define mmDMA_IF_E_S_DOWN_CH1_RGL_EXPECTED_LAT_3 0x4A2B78
+
+#define mmDMA_IF_E_S_DOWN_CH1_RGL_EXPECTED_LAT_4 0x4A2B7C
+
+#define mmDMA_IF_E_S_DOWN_CH1_RGL_EXPECTED_LAT_5 0x4A2B80
+
+#define mmDMA_IF_E_S_DOWN_CH1_RGL_EXPECTED_LAT_6 0x4A2B84
+
+#define mmDMA_IF_E_S_DOWN_CH1_RGL_EXPECTED_LAT_7 0x4A2B88
+
+#define mmDMA_IF_E_S_DOWN_CH1_RGL_TOKEN_0 0x4A2BAC
+
+#define mmDMA_IF_E_S_DOWN_CH1_RGL_TOKEN_1 0x4A2BB0
+
+#define mmDMA_IF_E_S_DOWN_CH1_RGL_TOKEN_2 0x4A2BB4
+
+#define mmDMA_IF_E_S_DOWN_CH1_RGL_TOKEN_3 0x4A2BB8
+
+#define mmDMA_IF_E_S_DOWN_CH1_RGL_TOKEN_4 0x4A2BBC
+
+#define mmDMA_IF_E_S_DOWN_CH1_RGL_TOKEN_5 0x4A2BC0
+
+#define mmDMA_IF_E_S_DOWN_CH1_RGL_TOKEN_6 0x4A2BC4
+
+#define mmDMA_IF_E_S_DOWN_CH1_RGL_TOKEN_7 0x4A2BC8
+
+#define mmDMA_IF_E_S_DOWN_CH1_RGL_BANK_ID_0 0x4A2BEC
+
+#define mmDMA_IF_E_S_DOWN_CH1_RGL_BANK_ID_1 0x4A2BF0
+
+#define mmDMA_IF_E_S_DOWN_CH1_RGL_BANK_ID_2 0x4A2BF4
+
+#define mmDMA_IF_E_S_DOWN_CH1_RGL_BANK_ID_3 0x4A2BF8
+
+#define mmDMA_IF_E_S_DOWN_CH1_RGL_BANK_ID_4 0x4A2BFC
+
+#define mmDMA_IF_E_S_DOWN_CH1_RGL_BANK_ID_5 0x4A2C00
+
+#define mmDMA_IF_E_S_DOWN_CH1_RGL_BANK_ID_6 0x4A2C04
+
+#define mmDMA_IF_E_S_DOWN_CH1_RGL_BANK_ID_7 0x4A2C08
+
+#define mmDMA_IF_E_S_DOWN_CH1_RGL_WDT 0x4A2C2C
+
+#define mmDMA_IF_E_S_DOWN_CH1_E2E_AR_HBM0_CH0_CTR_WRAP 0x4A2C30
+
+#define mmDMA_IF_E_S_DOWN_CH1_E2E_AR_HBM0_CH1_CTR_WRAP 0x4A2C34
+
+#define mmDMA_IF_E_S_DOWN_CH1_E2E_AR_HBM1_CH0_CTR_WRAP 0x4A2C38
+
+#define mmDMA_IF_E_S_DOWN_CH1_E2E_AR_HBM1_CH1_CTR_WRAP 0x4A2C3C
+
+#define mmDMA_IF_E_S_DOWN_CH1_E2E_AR_HBM2_CH0_CTR_WRAP 0x4A2C40
+
+#define mmDMA_IF_E_S_DOWN_CH1_E2E_AR_HBM2_CH1_CTR_WRAP 0x4A2C44
+
+#define mmDMA_IF_E_S_DOWN_CH1_E2E_AR_HBM3_CH0_CTR_WRAP 0x4A2C48
+
+#define mmDMA_IF_E_S_DOWN_CH1_E2E_AR_HBM3_CH1_CTR_WRAP 0x4A2C4C
+
+#define mmDMA_IF_E_S_DOWN_CH1_E2E_AR_HBM0_CH0_CTR_CNT 0x4A2C50
+
+#define mmDMA_IF_E_S_DOWN_CH1_E2E_AR_HBM0_CH1_CTR_CNT 0x4A2C54
+
+#define mmDMA_IF_E_S_DOWN_CH1_E2E_AR_HBM1_CH0_CTR_CNT 0x4A2C58
+
+#define mmDMA_IF_E_S_DOWN_CH1_E2E_AR_HBM1_CH1_CTR_CNT 0x4A2C5C
+
+#define mmDMA_IF_E_S_DOWN_CH1_E2E_AR_HBM2_CH0_CTR_CNT 0x4A2C60
+
+#define mmDMA_IF_E_S_DOWN_CH1_E2E_AR_HBM2_CH1_CTR_CNT 0x4A2C64
+
+#define mmDMA_IF_E_S_DOWN_CH1_E2E_AR_HBM3_CH0_CTR_CNT 0x4A2C68
+
+#define mmDMA_IF_E_S_DOWN_CH1_E2E_AR_HBM3_CH1_CTR_CNT 0x4A2C6C
+
+#define mmDMA_IF_E_S_DOWN_CH1_E2E_AW_HBM0_CH0_CTR_WRAP 0x4A2C70
+
+#define mmDMA_IF_E_S_DOWN_CH1_E2E_AW_HBM0_CH1_CTR_WRAP 0x4A2C74
+
+#define mmDMA_IF_E_S_DOWN_CH1_E2E_AW_HBM1_CH0_CTR_WRAP 0x4A2C78
+
+#define mmDMA_IF_E_S_DOWN_CH1_E2E_AW_HBM1_CH1_CTR_WRAP 0x4A2C7C
+
+#define mmDMA_IF_E_S_DOWN_CH1_E2E_AW_HBM2_CH0_CTR_WRAP 0x4A2C80
+
+#define mmDMA_IF_E_S_DOWN_CH1_E2E_AW_HBM2_CH1_CTR_WRAP 0x4A2C84
+
+#define mmDMA_IF_E_S_DOWN_CH1_E2E_AW_HBM3_CH0_CTR_WRAP 0x4A2C88
+
+#define mmDMA_IF_E_S_DOWN_CH1_E2E_AW_HBM3_CH1_CTR_WRAP 0x4A2C8C
+
+#define mmDMA_IF_E_S_DOWN_CH1_E2E_AW_HBM0_CH0_CTR_CNT 0x4A2C90
+
+#define mmDMA_IF_E_S_DOWN_CH1_E2E_AW_HBM0_CH1_CTR_CNT 0x4A2C94
+
+#define mmDMA_IF_E_S_DOWN_CH1_E2E_AW_HBM1_CH0_CTR_CNT 0x4A2C98
+
+#define mmDMA_IF_E_S_DOWN_CH1_E2E_AW_HBM1_CH1_CTR_CNT 0x4A2C9C
+
+#define mmDMA_IF_E_S_DOWN_CH1_E2E_AW_HBM2_CH0_CTR_CNT 0x4A2CA0
+
+#define mmDMA_IF_E_S_DOWN_CH1_E2E_AW_HBM2_CH1_CTR_CNT 0x4A2CA4
+
+#define mmDMA_IF_E_S_DOWN_CH1_E2E_AW_HBM3_CH0_CTR_CNT 0x4A2CA8
+
+#define mmDMA_IF_E_S_DOWN_CH1_E2E_AW_HBM3_CH1_CTR_CNT 0x4A2CAC
+
+#define mmDMA_IF_E_S_DOWN_CH1_NL_HBM_PC_SEL_0 0x4A2CB0
+
+#define mmDMA_IF_E_S_DOWN_CH1_NL_HBM_PC_SEL_1 0x4A2CB4
+
+#define mmDMA_IF_E_S_DOWN_CH1_NL_HBM_PC_SEL_2 0x4A2CB8
+
+#define mmDMA_IF_E_S_DOWN_CH1_NL_HBM_PC_SEL_3 0x4A2CBC
+
+#endif /* ASIC_REG_DMA_IF_E_S_DOWN_CH1_REGS_H_ */
diff --git a/drivers/accel/habanalabs/include/gaudi/asic_reg/dma_if_e_s_regs.h b/drivers/accel/habanalabs/include/gaudi/asic_reg/dma_if_e_s_regs.h
new file mode 100644
index 0000000000..78c18da715
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi/asic_reg/dma_if_e_s_regs.h
@@ -0,0 +1,860 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2016-2018 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ ** DO NOT EDIT BELOW **
+ ************************************/
+
+#ifndef ASIC_REG_DMA_IF_E_S_REGS_H_
+#define ASIC_REG_DMA_IF_E_S_REGS_H_
+
+/*
+ *****************************************
+ * DMA_IF_E_S (Prototype: DMA_IF)
+ *****************************************
+ */
+
+#define mmDMA_IF_E_S_HBM0_WR_CRED_CNT 0x4A0000
+
+#define mmDMA_IF_E_S_HBM1_WR_CRED_CNT 0x4A0004
+
+#define mmDMA_IF_E_S_HBM0_RD_CRED_CNT 0x4A0008
+
+#define mmDMA_IF_E_S_HBM1_RD_CRED_CNT 0x4A000C
+
+#define mmDMA_IF_E_S_HBM_LIMITER_0 0x4A0030
+
+#define mmDMA_IF_E_S_HBM_LIMITER_1 0x4A0034
+
+#define mmDMA_IF_E_S_HBM_LIMITER_2 0x4A0038
+
+#define mmDMA_IF_E_S_HBM_LIMITER_3 0x4A003C
+
+#define mmDMA_IF_E_S_HBM_ALMOST_EN_0 0x4A0040
+
+#define mmDMA_IF_E_S_HBM_ALMOST_EN_1 0x4A0044
+
+#define mmDMA_IF_E_S_HBM_CRED_EN_0 0x4A0050
+
+#define mmDMA_IF_E_S_HBM_CRED_EN_1 0x4A0054
+
+#define mmDMA_IF_E_S_SOB_MIN_RPROT_0 0x4A0100
+
+#define mmDMA_IF_E_S_SOB_MIN_RPROT_1 0x4A0104
+
+#define mmDMA_IF_E_S_SOB_MIN_RPROT_2 0x4A0108
+
+#define mmDMA_IF_E_S_SOB_MIN_RPROT_3 0x4A010C
+
+#define mmDMA_IF_E_S_SOB_MIN_RPROT_4 0x4A0110
+
+#define mmDMA_IF_E_S_SOB_MIN_RPROT_5 0x4A0114
+
+#define mmDMA_IF_E_S_SOB_MIN_RPROT_6 0x4A0118
+
+#define mmDMA_IF_E_S_SOB_MIN_RPROT_7 0x4A011C
+
+#define mmDMA_IF_E_S_SOB_MIN_RPROT_8 0x4A0120
+
+#define mmDMA_IF_E_S_SOB_MIN_RPROT_9 0x4A0124
+
+#define mmDMA_IF_E_S_SOB_MIN_RPROT_10 0x4A0128
+
+#define mmDMA_IF_E_S_SOB_MIN_RPROT_11 0x4A012C
+
+#define mmDMA_IF_E_S_SOB_MIN_RPROT_12 0x4A0130
+
+#define mmDMA_IF_E_S_SOB_MIN_RPROT_13 0x4A0134
+
+#define mmDMA_IF_E_S_SOB_MIN_RPROT_14 0x4A0138
+
+#define mmDMA_IF_E_S_SOB_MIN_RPROT_15 0x4A013C
+
+#define mmDMA_IF_E_S_SOB_MAX_RPROT_0 0x4A0140
+
+#define mmDMA_IF_E_S_SOB_MAX_RPROT_1 0x4A0144
+
+#define mmDMA_IF_E_S_SOB_MAX_RPROT_2 0x4A0148
+
+#define mmDMA_IF_E_S_SOB_MAX_RPROT_3 0x4A014C
+
+#define mmDMA_IF_E_S_SOB_MAX_RPROT_4 0x4A0150
+
+#define mmDMA_IF_E_S_SOB_MAX_RPROT_5 0x4A0154
+
+#define mmDMA_IF_E_S_SOB_MAX_RPROT_6 0x4A0158
+
+#define mmDMA_IF_E_S_SOB_MAX_RPROT_7 0x4A015C
+
+#define mmDMA_IF_E_S_SOB_MAX_RPROT_8 0x4A0160
+
+#define mmDMA_IF_E_S_SOB_MAX_RPROT_9 0x4A0164
+
+#define mmDMA_IF_E_S_SOB_MAX_RPROT_10 0x4A0168
+
+#define mmDMA_IF_E_S_SOB_MAX_RPROT_11 0x4A016C
+
+#define mmDMA_IF_E_S_SOB_MAX_RPROT_12 0x4A0170
+
+#define mmDMA_IF_E_S_SOB_MAX_RPROT_13 0x4A0174
+
+#define mmDMA_IF_E_S_SOB_MAX_RPROT_14 0x4A0178
+
+#define mmDMA_IF_E_S_SOB_MAX_RPROT_15 0x4A017C
+
+#define mmDMA_IF_E_S_SOB_MIN_WPROT_0 0x4A0180
+
+#define mmDMA_IF_E_S_SOB_MIN_WPROT_1 0x4A0184
+
+#define mmDMA_IF_E_S_SOB_MIN_WPROT_2 0x4A0188
+
+#define mmDMA_IF_E_S_SOB_MIN_WPROT_3 0x4A018C
+
+#define mmDMA_IF_E_S_SOB_MIN_WPROT_4 0x4A0190
+
+#define mmDMA_IF_E_S_SOB_MIN_WPROT_5 0x4A0194
+
+#define mmDMA_IF_E_S_SOB_MIN_WPROT_6 0x4A0198
+
+#define mmDMA_IF_E_S_SOB_MIN_WPROT_7 0x4A019C
+
+#define mmDMA_IF_E_S_SOB_MIN_WPROT_8 0x4A01A0
+
+#define mmDMA_IF_E_S_SOB_MIN_WPROT_9 0x4A01A4
+
+#define mmDMA_IF_E_S_SOB_MIN_WPROT_10 0x4A01A8
+
+#define mmDMA_IF_E_S_SOB_MIN_WPROT_11 0x4A01AC
+
+#define mmDMA_IF_E_S_SOB_MIN_WPROT_12 0x4A01B0
+
+#define mmDMA_IF_E_S_SOB_MIN_WPROT_13 0x4A01B4
+
+#define mmDMA_IF_E_S_SOB_MIN_WPROT_14 0x4A01B8
+
+#define mmDMA_IF_E_S_SOB_MIN_WPROT_15 0x4A01BC
+
+#define mmDMA_IF_E_S_SOB_MAX_WPROT_0 0x4A01C0
+
+#define mmDMA_IF_E_S_SOB_MAX_WPROT_1 0x4A01C4
+
+#define mmDMA_IF_E_S_SOB_MAX_WPROT_2 0x4A01C8
+
+#define mmDMA_IF_E_S_SOB_MAX_WPROT_3 0x4A01CC
+
+#define mmDMA_IF_E_S_SOB_MAX_WPROT_4 0x4A01D0
+
+#define mmDMA_IF_E_S_SOB_MAX_WPROT_5 0x4A01D4
+
+#define mmDMA_IF_E_S_SOB_MAX_WPROT_6 0x4A01D8
+
+#define mmDMA_IF_E_S_SOB_MAX_WPROT_7 0x4A01DC
+
+#define mmDMA_IF_E_S_SOB_MAX_WPROT_8 0x4A01E0
+
+#define mmDMA_IF_E_S_SOB_MAX_WPROT_9 0x4A01E4
+
+#define mmDMA_IF_E_S_SOB_MAX_WPROT_10 0x4A01E8
+
+#define mmDMA_IF_E_S_SOB_MAX_WPROT_11 0x4A01EC
+
+#define mmDMA_IF_E_S_SOB_MAX_WPROT_12 0x4A01F0
+
+#define mmDMA_IF_E_S_SOB_MAX_WPROT_13 0x4A01F4
+
+#define mmDMA_IF_E_S_SOB_MAX_WPROT_14 0x4A01F8
+
+#define mmDMA_IF_E_S_SOB_MAX_WPROT_15 0x4A01FC
+
+#define mmDMA_IF_E_S_SOB_MIN_RPRIV_0 0x4A0200
+
+#define mmDMA_IF_E_S_SOB_MIN_RPRIV_1 0x4A0204
+
+#define mmDMA_IF_E_S_SOB_MIN_RPRIV_2 0x4A0208
+
+#define mmDMA_IF_E_S_SOB_MIN_RPRIV_3 0x4A020C
+
+#define mmDMA_IF_E_S_SOB_MIN_RPRIV_4 0x4A0210
+
+#define mmDMA_IF_E_S_SOB_MIN_RPRIV_5 0x4A0214
+
+#define mmDMA_IF_E_S_SOB_MIN_RPRIV_6 0x4A0218
+
+#define mmDMA_IF_E_S_SOB_MIN_RPRIV_7 0x4A021C
+
+#define mmDMA_IF_E_S_SOB_MIN_RPRIV_8 0x4A0220
+
+#define mmDMA_IF_E_S_SOB_MIN_RPRIV_9 0x4A0224
+
+#define mmDMA_IF_E_S_SOB_MIN_RPRIV_10 0x4A0228
+
+#define mmDMA_IF_E_S_SOB_MIN_RPRIV_11 0x4A022C
+
+#define mmDMA_IF_E_S_SOB_MIN_RPRIV_12 0x4A0230
+
+#define mmDMA_IF_E_S_SOB_MIN_RPRIV_13 0x4A0234
+
+#define mmDMA_IF_E_S_SOB_MIN_RPRIV_14 0x4A0238
+
+#define mmDMA_IF_E_S_SOB_MIN_RPRIV_15 0x4A023C
+
+#define mmDMA_IF_E_S_SOB_MAX_RPRIV_0 0x4A0240
+
+#define mmDMA_IF_E_S_SOB_MAX_RPRIV_1 0x4A0244
+
+#define mmDMA_IF_E_S_SOB_MAX_RPRIV_2 0x4A0248
+
+#define mmDMA_IF_E_S_SOB_MAX_RPRIV_3 0x4A024C
+
+#define mmDMA_IF_E_S_SOB_MAX_RPRIV_4 0x4A0250
+
+#define mmDMA_IF_E_S_SOB_MAX_RPRIV_5 0x4A0254
+
+#define mmDMA_IF_E_S_SOB_MAX_RPRIV_6 0x4A0258
+
+#define mmDMA_IF_E_S_SOB_MAX_RPRIV_7 0x4A025C
+
+#define mmDMA_IF_E_S_SOB_MAX_RPRIV_8 0x4A0260
+
+#define mmDMA_IF_E_S_SOB_MAX_RPRIV_9 0x4A0264
+
+#define mmDMA_IF_E_S_SOB_MAX_RPRIV_10 0x4A0268
+
+#define mmDMA_IF_E_S_SOB_MAX_RPRIV_11 0x4A026C
+
+#define mmDMA_IF_E_S_SOB_MAX_RPRIV_12 0x4A0270
+
+#define mmDMA_IF_E_S_SOB_MAX_RPRIV_13 0x4A0274
+
+#define mmDMA_IF_E_S_SOB_MAX_RPRIV_14 0x4A0278
+
+#define mmDMA_IF_E_S_SOB_MAX_RPRIV_15 0x4A027C
+
+#define mmDMA_IF_E_S_SOB_MIN_WPRIV_0 0x4A0280
+
+#define mmDMA_IF_E_S_SOB_MIN_WPRIV_1 0x4A0284
+
+#define mmDMA_IF_E_S_SOB_MIN_WPRIV_2 0x4A0288
+
+#define mmDMA_IF_E_S_SOB_MIN_WPRIV_3 0x4A028C
+
+#define mmDMA_IF_E_S_SOB_MIN_WPRIV_4 0x4A0290
+
+#define mmDMA_IF_E_S_SOB_MIN_WPRIV_5 0x4A0294
+
+#define mmDMA_IF_E_S_SOB_MIN_WPRIV_6 0x4A0298
+
+#define mmDMA_IF_E_S_SOB_MIN_WPRIV_7 0x4A029C
+
+#define mmDMA_IF_E_S_SOB_MIN_WPRIV_8 0x4A02A0
+
+#define mmDMA_IF_E_S_SOB_MIN_WPRIV_9 0x4A02A4
+
+#define mmDMA_IF_E_S_SOB_MIN_WPRIV_10 0x4A02A8
+
+#define mmDMA_IF_E_S_SOB_MIN_WPRIV_11 0x4A02AC
+
+#define mmDMA_IF_E_S_SOB_MIN_WPRIV_12 0x4A02B0
+
+#define mmDMA_IF_E_S_SOB_MIN_WPRIV_13 0x4A02B4
+
+#define mmDMA_IF_E_S_SOB_MIN_WPRIV_14 0x4A02B8
+
+#define mmDMA_IF_E_S_SOB_MIN_WPRIV_15 0x4A02BC
+
+#define mmDMA_IF_E_S_SOB_MAX_WPRIV_0 0x4A02C0
+
+#define mmDMA_IF_E_S_SOB_MAX_WPRIV_1 0x4A02C4
+
+#define mmDMA_IF_E_S_SOB_MAX_WPRIV_2 0x4A02C8
+
+#define mmDMA_IF_E_S_SOB_MAX_WPRIV_3 0x4A02CC
+
+#define mmDMA_IF_E_S_SOB_MAX_WPRIV_4 0x4A02D0
+
+#define mmDMA_IF_E_S_SOB_MAX_WPRIV_5 0x4A02D4
+
+#define mmDMA_IF_E_S_SOB_MAX_WPRIV_6 0x4A02D8
+
+#define mmDMA_IF_E_S_SOB_MAX_WPRIV_7 0x4A02DC
+
+#define mmDMA_IF_E_S_SOB_MAX_WPRIV_8 0x4A02E0
+
+#define mmDMA_IF_E_S_SOB_MAX_WPRIV_9 0x4A02E4
+
+#define mmDMA_IF_E_S_SOB_MAX_WPRIV_10 0x4A02E8
+
+#define mmDMA_IF_E_S_SOB_MAX_WPRIV_11 0x4A02EC
+
+#define mmDMA_IF_E_S_SOB_MAX_WPRIV_12 0x4A02F0
+
+#define mmDMA_IF_E_S_SOB_MAX_WPRIV_13 0x4A02F4
+
+#define mmDMA_IF_E_S_SOB_MAX_WPRIV_14 0x4A02F8
+
+#define mmDMA_IF_E_S_SOB_MAX_WPRIV_15 0x4A02FC
+
+#define mmDMA_IF_E_S_DMA0_MIN_RPROT_0 0x4A0300
+
+#define mmDMA_IF_E_S_DMA0_MIN_RPROT_1 0x4A0304
+
+#define mmDMA_IF_E_S_DMA0_MIN_RPROT_2 0x4A0308
+
+#define mmDMA_IF_E_S_DMA0_MIN_RPROT_3 0x4A030C
+
+#define mmDMA_IF_E_S_DMA0_MIN_RPROT_4 0x4A0310
+
+#define mmDMA_IF_E_S_DMA0_MIN_RPROT_5 0x4A0314
+
+#define mmDMA_IF_E_S_DMA0_MIN_RPROT_6 0x4A0318
+
+#define mmDMA_IF_E_S_DMA0_MIN_RPROT_7 0x4A031C
+
+#define mmDMA_IF_E_S_DMA0_MIN_RPROT_8 0x4A0320
+
+#define mmDMA_IF_E_S_DMA0_MIN_RPROT_9 0x4A0324
+
+#define mmDMA_IF_E_S_DMA0_MIN_RPROT_10 0x4A0328
+
+#define mmDMA_IF_E_S_DMA0_MIN_RPROT_11 0x4A032C
+
+#define mmDMA_IF_E_S_DMA0_MIN_RPROT_12 0x4A0330
+
+#define mmDMA_IF_E_S_DMA0_MIN_RPROT_13 0x4A0334
+
+#define mmDMA_IF_E_S_DMA0_MIN_RPROT_14 0x4A0338
+
+#define mmDMA_IF_E_S_DMA0_MIN_RPROT_15 0x4A033C
+
+#define mmDMA_IF_E_S_DMA0_MAX_RPROT_0 0x4A0340
+
+#define mmDMA_IF_E_S_DMA0_MAX_RPROT_1 0x4A0344
+
+#define mmDMA_IF_E_S_DMA0_MAX_RPROT_2 0x4A0348
+
+#define mmDMA_IF_E_S_DMA0_MAX_RPROT_3 0x4A034C
+
+#define mmDMA_IF_E_S_DMA0_MAX_RPROT_4 0x4A0350
+
+#define mmDMA_IF_E_S_DMA0_MAX_RPROT_5 0x4A0354
+
+#define mmDMA_IF_E_S_DMA0_MAX_RPROT_6 0x4A0358
+
+#define mmDMA_IF_E_S_DMA0_MAX_RPROT_7 0x4A035C
+
+#define mmDMA_IF_E_S_DMA0_MAX_RPROT_8 0x4A0360
+
+#define mmDMA_IF_E_S_DMA0_MAX_RPROT_9 0x4A0364
+
+#define mmDMA_IF_E_S_DMA0_MAX_RPROT_10 0x4A0368
+
+#define mmDMA_IF_E_S_DMA0_MAX_RPROT_11 0x4A036C
+
+#define mmDMA_IF_E_S_DMA0_MAX_RPROT_12 0x4A0370
+
+#define mmDMA_IF_E_S_DMA0_MAX_RPROT_13 0x4A0374
+
+#define mmDMA_IF_E_S_DMA0_MAX_RPROT_14 0x4A0378
+
+#define mmDMA_IF_E_S_DMA0_MAX_RPROT_15 0x4A037C
+
+#define mmDMA_IF_E_S_DMA0_MIN_WPROT_0 0x4A0380
+
+#define mmDMA_IF_E_S_DMA0_MIN_WPROT_1 0x4A0384
+
+#define mmDMA_IF_E_S_DMA0_MIN_WPROT_2 0x4A0388
+
+#define mmDMA_IF_E_S_DMA0_MIN_WPROT_3 0x4A038C
+
+#define mmDMA_IF_E_S_DMA0_MIN_WPROT_4 0x4A0390
+
+#define mmDMA_IF_E_S_DMA0_MIN_WPROT_5 0x4A0394
+
+#define mmDMA_IF_E_S_DMA0_MIN_WPROT_6 0x4A0398
+
+#define mmDMA_IF_E_S_DMA0_MIN_WPROT_7 0x4A039C
+
+#define mmDMA_IF_E_S_DMA0_MIN_WPROT_8 0x4A03A0
+
+#define mmDMA_IF_E_S_DMA0_MIN_WPROT_9 0x4A03A4
+
+#define mmDMA_IF_E_S_DMA0_MIN_WPROT_10 0x4A03A8
+
+#define mmDMA_IF_E_S_DMA0_MIN_WPROT_11 0x4A03AC
+
+#define mmDMA_IF_E_S_DMA0_MIN_WPROT_12 0x4A03B0
+
+#define mmDMA_IF_E_S_DMA0_MIN_WPROT_13 0x4A03B4
+
+#define mmDMA_IF_E_S_DMA0_MIN_WPROT_14 0x4A03B8
+
+#define mmDMA_IF_E_S_DMA0_MIN_WPROT_15 0x4A03BC
+
+#define mmDMA_IF_E_S_DMA0_MAX_WPROT_0 0x4A03C0
+
+#define mmDMA_IF_E_S_DMA0_MAX_WPROT_1 0x4A03C4
+
+#define mmDMA_IF_E_S_DMA0_MAX_WPROT_2 0x4A03C8
+
+#define mmDMA_IF_E_S_DMA0_MAX_WPROT_3 0x4A03CC
+
+#define mmDMA_IF_E_S_DMA0_MAX_WPROT_4 0x4A03D0
+
+#define mmDMA_IF_E_S_DMA0_MAX_WPROT_5 0x4A03D4
+
+#define mmDMA_IF_E_S_DMA0_MAX_WPROT_6 0x4A03D8
+
+#define mmDMA_IF_E_S_DMA0_MAX_WPROT_7 0x4A03DC
+
+#define mmDMA_IF_E_S_DMA0_MAX_WPROT_8 0x4A03E0
+
+#define mmDMA_IF_E_S_DMA0_MAX_WPROT_9 0x4A03E4
+
+#define mmDMA_IF_E_S_DMA0_MAX_WPROT_10 0x4A03E8
+
+#define mmDMA_IF_E_S_DMA0_MAX_WPROT_11 0x4A03EC
+
+#define mmDMA_IF_E_S_DMA0_MAX_WPROT_12 0x4A03F0
+
+#define mmDMA_IF_E_S_DMA0_MAX_WPROT_13 0x4A03F4
+
+#define mmDMA_IF_E_S_DMA0_MAX_WPROT_14 0x4A03F8
+
+#define mmDMA_IF_E_S_DMA0_MAX_WPROT_15 0x4A03FC
+
+#define mmDMA_IF_E_S_DMA0_MIN_RPRIV_0 0x4A0400
+
+#define mmDMA_IF_E_S_DMA0_MIN_RPRIV_1 0x4A0404
+
+#define mmDMA_IF_E_S_DMA0_MIN_RPRIV_2 0x4A0408
+
+#define mmDMA_IF_E_S_DMA0_MIN_RPRIV_3 0x4A040C
+
+#define mmDMA_IF_E_S_DMA0_MIN_RPRIV_4 0x4A0410
+
+#define mmDMA_IF_E_S_DMA0_MIN_RPRIV_5 0x4A0414
+
+#define mmDMA_IF_E_S_DMA0_MIN_RPRIV_6 0x4A0418
+
+#define mmDMA_IF_E_S_DMA0_MIN_RPRIV_7 0x4A041C
+
+#define mmDMA_IF_E_S_DMA0_MIN_RPRIV_8 0x4A0420
+
+#define mmDMA_IF_E_S_DMA0_MIN_RPRIV_9 0x4A0424
+
+#define mmDMA_IF_E_S_DMA0_MIN_RPRIV_10 0x4A0428
+
+#define mmDMA_IF_E_S_DMA0_MIN_RPRIV_11 0x4A042C
+
+#define mmDMA_IF_E_S_DMA0_MIN_RPRIV_12 0x4A0430
+
+#define mmDMA_IF_E_S_DMA0_MIN_RPRIV_13 0x4A0434
+
+#define mmDMA_IF_E_S_DMA0_MIN_RPRIV_14 0x4A0438
+
+#define mmDMA_IF_E_S_DMA0_MIN_RPRIV_15 0x4A043C
+
+#define mmDMA_IF_E_S_DMA0_MAX_RPRIV_0 0x4A0440
+
+#define mmDMA_IF_E_S_DMA0_MAX_RPRIV_1 0x4A0444
+
+#define mmDMA_IF_E_S_DMA0_MAX_RPRIV_2 0x4A0448
+
+#define mmDMA_IF_E_S_DMA0_MAX_RPRIV_3 0x4A044C
+
+#define mmDMA_IF_E_S_DMA0_MAX_RPRIV_4 0x4A0450
+
+#define mmDMA_IF_E_S_DMA0_MAX_RPRIV_5 0x4A0454
+
+#define mmDMA_IF_E_S_DMA0_MAX_RPRIV_6 0x4A0458
+
+#define mmDMA_IF_E_S_DMA0_MAX_RPRIV_7 0x4A045C
+
+#define mmDMA_IF_E_S_DMA0_MAX_RPRIV_8 0x4A0460
+
+#define mmDMA_IF_E_S_DMA0_MAX_RPRIV_9 0x4A0464
+
+#define mmDMA_IF_E_S_DMA0_MAX_RPRIV_10 0x4A0468
+
+#define mmDMA_IF_E_S_DMA0_MAX_RPRIV_11 0x4A046C
+
+#define mmDMA_IF_E_S_DMA0_MAX_RPRIV_12 0x4A0470
+
+#define mmDMA_IF_E_S_DMA0_MAX_RPRIV_13 0x4A0474
+
+#define mmDMA_IF_E_S_DMA0_MAX_RPRIV_14 0x4A0478
+
+#define mmDMA_IF_E_S_DMA0_MAX_RPRIV_15 0x4A047C
+
+#define mmDMA_IF_E_S_DMA0_MIN_WPRIV_0 0x4A0480
+
+#define mmDMA_IF_E_S_DMA0_MIN_WPRIV_1 0x4A0484
+
+#define mmDMA_IF_E_S_DMA0_MIN_WPRIV_2 0x4A0488
+
+#define mmDMA_IF_E_S_DMA0_MIN_WPRIV_3 0x4A048C
+
+#define mmDMA_IF_E_S_DMA0_MIN_WPRIV_4 0x4A0490
+
+#define mmDMA_IF_E_S_DMA0_MIN_WPRIV_5 0x4A0494
+
+#define mmDMA_IF_E_S_DMA0_MIN_WPRIV_6 0x4A0498
+
+#define mmDMA_IF_E_S_DMA0_MIN_WPRIV_7 0x4A049C
+
+#define mmDMA_IF_E_S_DMA0_MIN_WPRIV_8 0x4A04A0
+
+#define mmDMA_IF_E_S_DMA0_MIN_WPRIV_9 0x4A04A4
+
+#define mmDMA_IF_E_S_DMA0_MIN_WPRIV_10 0x4A04A8
+
+#define mmDMA_IF_E_S_DMA0_MIN_WPRIV_11 0x4A04AC
+
+#define mmDMA_IF_E_S_DMA0_MIN_WPRIV_12 0x4A04B0
+
+#define mmDMA_IF_E_S_DMA0_MIN_WPRIV_13 0x4A04B4
+
+#define mmDMA_IF_E_S_DMA0_MIN_WPRIV_14 0x4A04B8
+
+#define mmDMA_IF_E_S_DMA0_MIN_WPRIV_15 0x4A04BC
+
+#define mmDMA_IF_E_S_DMA0_MAX_WPRIV_0 0x4A04C0
+
+#define mmDMA_IF_E_S_DMA0_MAX_WPRIV_1 0x4A04C4
+
+#define mmDMA_IF_E_S_DMA0_MAX_WPRIV_2 0x4A04C8
+
+#define mmDMA_IF_E_S_DMA0_MAX_WPRIV_3 0x4A04CC
+
+#define mmDMA_IF_E_S_DMA0_MAX_WPRIV_4 0x4A04D0
+
+#define mmDMA_IF_E_S_DMA0_MAX_WPRIV_5 0x4A04D4
+
+#define mmDMA_IF_E_S_DMA0_MAX_WPRIV_6 0x4A04D8
+
+#define mmDMA_IF_E_S_DMA0_MAX_WPRIV_7 0x4A04DC
+
+#define mmDMA_IF_E_S_DMA0_MAX_WPRIV_8 0x4A04E0
+
+#define mmDMA_IF_E_S_DMA0_MAX_WPRIV_9 0x4A04E4
+
+#define mmDMA_IF_E_S_DMA0_MAX_WPRIV_10 0x4A04E8
+
+#define mmDMA_IF_E_S_DMA0_MAX_WPRIV_11 0x4A04EC
+
+#define mmDMA_IF_E_S_DMA0_MAX_WPRIV_12 0x4A04F0
+
+#define mmDMA_IF_E_S_DMA0_MAX_WPRIV_13 0x4A04F4
+
+#define mmDMA_IF_E_S_DMA0_MAX_WPRIV_14 0x4A04F8
+
+#define mmDMA_IF_E_S_DMA0_MAX_WPRIV_15 0x4A04FC
+
+#define mmDMA_IF_E_S_DMA1_MIN_RPROT_0 0x4A0500
+
+#define mmDMA_IF_E_S_DMA1_MIN_RPROT_1 0x4A0504
+
+#define mmDMA_IF_E_S_DMA1_MIN_RPROT_2 0x4A0508
+
+#define mmDMA_IF_E_S_DMA1_MIN_RPROT_3 0x4A050C
+
+#define mmDMA_IF_E_S_DMA1_MIN_RPROT_4 0x4A0510
+
+#define mmDMA_IF_E_S_DMA1_MIN_RPROT_5 0x4A0514
+
+#define mmDMA_IF_E_S_DMA1_MIN_RPROT_6 0x4A0518
+
+#define mmDMA_IF_E_S_DMA1_MIN_RPROT_7 0x4A051C
+
+#define mmDMA_IF_E_S_DMA1_MIN_RPROT_8 0x4A0520
+
+#define mmDMA_IF_E_S_DMA1_MIN_RPROT_9 0x4A0524
+
+#define mmDMA_IF_E_S_DMA1_MIN_RPROT_10 0x4A0528
+
+#define mmDMA_IF_E_S_DMA1_MIN_RPROT_11 0x4A052C
+
+#define mmDMA_IF_E_S_DMA1_MIN_RPROT_12 0x4A0530
+
+#define mmDMA_IF_E_S_DMA1_MIN_RPROT_13 0x4A0534
+
+#define mmDMA_IF_E_S_DMA1_MIN_RPROT_14 0x4A0538
+
+#define mmDMA_IF_E_S_DMA1_MIN_RPROT_15 0x4A053C
+
+#define mmDMA_IF_E_S_DMA1_MAX_RPROT_0 0x4A0540
+
+#define mmDMA_IF_E_S_DMA1_MAX_RPROT_1 0x4A0544
+
+#define mmDMA_IF_E_S_DMA1_MAX_RPROT_2 0x4A0548
+
+#define mmDMA_IF_E_S_DMA1_MAX_RPROT_3 0x4A054C
+
+#define mmDMA_IF_E_S_DMA1_MAX_RPROT_4 0x4A0550
+
+#define mmDMA_IF_E_S_DMA1_MAX_RPROT_5 0x4A0554
+
+#define mmDMA_IF_E_S_DMA1_MAX_RPROT_6 0x4A0558
+
+#define mmDMA_IF_E_S_DMA1_MAX_RPROT_7 0x4A055C
+
+#define mmDMA_IF_E_S_DMA1_MAX_RPROT_8 0x4A0560
+
+#define mmDMA_IF_E_S_DMA1_MAX_RPROT_9 0x4A0564
+
+#define mmDMA_IF_E_S_DMA1_MAX_RPROT_10 0x4A0568
+
+#define mmDMA_IF_E_S_DMA1_MAX_RPROT_11 0x4A056C
+
+#define mmDMA_IF_E_S_DMA1_MAX_RPROT_12 0x4A0570
+
+#define mmDMA_IF_E_S_DMA1_MAX_RPROT_13 0x4A0574
+
+#define mmDMA_IF_E_S_DMA1_MAX_RPROT_14 0x4A0578
+
+#define mmDMA_IF_E_S_DMA1_MAX_RPROT_15 0x4A057C
+
+#define mmDMA_IF_E_S_DMA1_MIN_WPROT_0 0x4A0580
+
+#define mmDMA_IF_E_S_DMA1_MIN_WPROT_1 0x4A0584
+
+#define mmDMA_IF_E_S_DMA1_MIN_WPROT_2 0x4A0588
+
+#define mmDMA_IF_E_S_DMA1_MIN_WPROT_3 0x4A058C
+
+#define mmDMA_IF_E_S_DMA1_MIN_WPROT_4 0x4A0590
+
+#define mmDMA_IF_E_S_DMA1_MIN_WPROT_5 0x4A0594
+
+#define mmDMA_IF_E_S_DMA1_MIN_WPROT_6 0x4A0598
+
+#define mmDMA_IF_E_S_DMA1_MIN_WPROT_7 0x4A059C
+
+#define mmDMA_IF_E_S_DMA1_MIN_WPROT_8 0x4A05A0
+
+#define mmDMA_IF_E_S_DMA1_MIN_WPROT_9 0x4A05A4
+
+#define mmDMA_IF_E_S_DMA1_MIN_WPROT_10 0x4A05A8
+
+#define mmDMA_IF_E_S_DMA1_MIN_WPROT_11 0x4A05AC
+
+#define mmDMA_IF_E_S_DMA1_MIN_WPROT_12 0x4A05B0
+
+#define mmDMA_IF_E_S_DMA1_MIN_WPROT_13 0x4A05B4
+
+#define mmDMA_IF_E_S_DMA1_MIN_WPROT_14 0x4A05B8
+
+#define mmDMA_IF_E_S_DMA1_MIN_WPROT_15 0x4A05BC
+
+#define mmDMA_IF_E_S_DMA1_MAX_WPROT_0 0x4A05C0
+
+#define mmDMA_IF_E_S_DMA1_MAX_WPROT_1 0x4A05C4
+
+#define mmDMA_IF_E_S_DMA1_MAX_WPROT_2 0x4A05C8
+
+#define mmDMA_IF_E_S_DMA1_MAX_WPROT_3 0x4A05CC
+
+#define mmDMA_IF_E_S_DMA1_MAX_WPROT_4 0x4A05D0
+
+#define mmDMA_IF_E_S_DMA1_MAX_WPROT_5 0x4A05D4
+
+#define mmDMA_IF_E_S_DMA1_MAX_WPROT_6 0x4A05D8
+
+#define mmDMA_IF_E_S_DMA1_MAX_WPROT_7 0x4A05DC
+
+#define mmDMA_IF_E_S_DMA1_MAX_WPROT_8 0x4A05E0
+
+#define mmDMA_IF_E_S_DMA1_MAX_WPROT_9 0x4A05E4
+
+#define mmDMA_IF_E_S_DMA1_MAX_WPROT_10 0x4A05E8
+
+#define mmDMA_IF_E_S_DMA1_MAX_WPROT_11 0x4A05EC
+
+#define mmDMA_IF_E_S_DMA1_MAX_WPROT_12 0x4A05F0
+
+#define mmDMA_IF_E_S_DMA1_MAX_WPROT_13 0x4A05F4
+
+#define mmDMA_IF_E_S_DMA1_MAX_WPROT_14 0x4A05F8
+
+#define mmDMA_IF_E_S_DMA1_MAX_WPROT_15 0x4A05FC
+
+#define mmDMA_IF_E_S_DMA1_MIN_RPRIV_0 0x4A0600
+
+#define mmDMA_IF_E_S_DMA1_MIN_RPRIV_1 0x4A0604
+
+#define mmDMA_IF_E_S_DMA1_MIN_RPRIV_2 0x4A0608
+
+#define mmDMA_IF_E_S_DMA1_MIN_RPRIV_3 0x4A060C
+
+#define mmDMA_IF_E_S_DMA1_MIN_RPRIV_4 0x4A0610
+
+#define mmDMA_IF_E_S_DMA1_MIN_RPRIV_5 0x4A0614
+
+#define mmDMA_IF_E_S_DMA1_MIN_RPRIV_6 0x4A0618
+
+#define mmDMA_IF_E_S_DMA1_MIN_RPRIV_7 0x4A061C
+
+#define mmDMA_IF_E_S_DMA1_MIN_RPRIV_8 0x4A0620
+
+#define mmDMA_IF_E_S_DMA1_MIN_RPRIV_9 0x4A0624
+
+#define mmDMA_IF_E_S_DMA1_MIN_RPRIV_10 0x4A0628
+
+#define mmDMA_IF_E_S_DMA1_MIN_RPRIV_11 0x4A062C
+
+#define mmDMA_IF_E_S_DMA1_MIN_RPRIV_12 0x4A0630
+
+#define mmDMA_IF_E_S_DMA1_MIN_RPRIV_13 0x4A0634
+
+#define mmDMA_IF_E_S_DMA1_MIN_RPRIV_14 0x4A0638
+
+#define mmDMA_IF_E_S_DMA1_MIN_RPRIV_15 0x4A063C
+
+#define mmDMA_IF_E_S_DMA1_MAX_RPRIV_0 0x4A0640
+
+#define mmDMA_IF_E_S_DMA1_MAX_RPRIV_1 0x4A0644
+
+#define mmDMA_IF_E_S_DMA1_MAX_RPRIV_2 0x4A0648
+
+#define mmDMA_IF_E_S_DMA1_MAX_RPRIV_3 0x4A064C
+
+#define mmDMA_IF_E_S_DMA1_MAX_RPRIV_4 0x4A0650
+
+#define mmDMA_IF_E_S_DMA1_MAX_RPRIV_5 0x4A0654
+
+#define mmDMA_IF_E_S_DMA1_MAX_RPRIV_6 0x4A0658
+
+#define mmDMA_IF_E_S_DMA1_MAX_RPRIV_7 0x4A065C
+
+#define mmDMA_IF_E_S_DMA1_MAX_RPRIV_8 0x4A0660
+
+#define mmDMA_IF_E_S_DMA1_MAX_RPRIV_9 0x4A0664
+
+#define mmDMA_IF_E_S_DMA1_MAX_RPRIV_10 0x4A0668
+
+#define mmDMA_IF_E_S_DMA1_MAX_RPRIV_11 0x4A066C
+
+#define mmDMA_IF_E_S_DMA1_MAX_RPRIV_12 0x4A0670
+
+#define mmDMA_IF_E_S_DMA1_MAX_RPRIV_13 0x4A0674
+
+#define mmDMA_IF_E_S_DMA1_MAX_RPRIV_14 0x4A0678
+
+#define mmDMA_IF_E_S_DMA1_MAX_RPRIV_15 0x4A067C
+
+#define mmDMA_IF_E_S_DMA1_MIN_WPRIV_0 0x4A0680
+
+#define mmDMA_IF_E_S_DMA1_MIN_WPRIV_1 0x4A0684
+
+#define mmDMA_IF_E_S_DMA1_MIN_WPRIV_2 0x4A0688
+
+#define mmDMA_IF_E_S_DMA1_MIN_WPRIV_3 0x4A068C
+
+#define mmDMA_IF_E_S_DMA1_MIN_WPRIV_4 0x4A0690
+
+#define mmDMA_IF_E_S_DMA1_MIN_WPRIV_5 0x4A0694
+
+#define mmDMA_IF_E_S_DMA1_MIN_WPRIV_6 0x4A0698
+
+#define mmDMA_IF_E_S_DMA1_MIN_WPRIV_7 0x4A069C
+
+#define mmDMA_IF_E_S_DMA1_MIN_WPRIV_8 0x4A06A0
+
+#define mmDMA_IF_E_S_DMA1_MIN_WPRIV_9 0x4A06A4
+
+#define mmDMA_IF_E_S_DMA1_MIN_WPRIV_10 0x4A06A8
+
+#define mmDMA_IF_E_S_DMA1_MIN_WPRIV_11 0x4A06AC
+
+#define mmDMA_IF_E_S_DMA1_MIN_WPRIV_12 0x4A06B0
+
+#define mmDMA_IF_E_S_DMA1_MIN_WPRIV_13 0x4A06B4
+
+#define mmDMA_IF_E_S_DMA1_MIN_WPRIV_14 0x4A06B8
+
+#define mmDMA_IF_E_S_DMA1_MIN_WPRIV_15 0x4A06BC
+
+#define mmDMA_IF_E_S_DMA1_MAX_WPRIV_0 0x4A06C0
+
+#define mmDMA_IF_E_S_DMA1_MAX_WPRIV_1 0x4A06C4
+
+#define mmDMA_IF_E_S_DMA1_MAX_WPRIV_2 0x4A06C8
+
+#define mmDMA_IF_E_S_DMA1_MAX_WPRIV_3 0x4A06CC
+
+#define mmDMA_IF_E_S_DMA1_MAX_WPRIV_4 0x4A06D0
+
+#define mmDMA_IF_E_S_DMA1_MAX_WPRIV_5 0x4A06D4
+
+#define mmDMA_IF_E_S_DMA1_MAX_WPRIV_6 0x4A06D8
+
+#define mmDMA_IF_E_S_DMA1_MAX_WPRIV_7 0x4A06DC
+
+#define mmDMA_IF_E_S_DMA1_MAX_WPRIV_8 0x4A06E0
+
+#define mmDMA_IF_E_S_DMA1_MAX_WPRIV_9 0x4A06E4
+
+#define mmDMA_IF_E_S_DMA1_MAX_WPRIV_10 0x4A06E8
+
+#define mmDMA_IF_E_S_DMA1_MAX_WPRIV_11 0x4A06EC
+
+#define mmDMA_IF_E_S_DMA1_MAX_WPRIV_12 0x4A06F0
+
+#define mmDMA_IF_E_S_DMA1_MAX_WPRIV_13 0x4A06F4
+
+#define mmDMA_IF_E_S_DMA1_MAX_WPRIV_14 0x4A06F8
+
+#define mmDMA_IF_E_S_DMA1_MAX_WPRIV_15 0x4A06FC
+
+#define mmDMA_IF_E_S_SOB_HIT_RPROT 0x4A0700
+
+#define mmDMA_IF_E_S_SOB_HIT_WPROT 0x4A0704
+
+#define mmDMA_IF_E_S_SOB_HIT_RPRIV 0x4A070C
+
+#define mmDMA_IF_E_S_SOB_HIT_WPRIV 0x4A0710
+
+#define mmDMA_IF_E_S_DMA0_HIT_RPROT 0x4A071C
+
+#define mmDMA_IF_E_S_DMA0_HIT_WPROT 0x4A0720
+
+#define mmDMA_IF_E_S_DMA0_HIT_RPRIV 0x4A0724
+
+#define mmDMA_IF_E_S_DMA0_HIT_WPRIV 0x4A0728
+
+#define mmDMA_IF_E_S_DMA1_HIT_RPROT 0x4A0730
+
+#define mmDMA_IF_E_S_DMA1_HIT_WPROT 0x4A0734
+
+#define mmDMA_IF_E_S_DMA1_HIT_RPRIV 0x4A0738
+
+#define mmDMA_IF_E_S_DMA1_HIT_WPRIV 0x4A073C
+
+#define mmDMA_IF_E_S_HBM_BIN 0x4A0800
+
+#define mmDMA_IF_E_S_MME_BIN 0x4A0804
+
+#define mmDMA_IF_E_S_TPC_BIN 0x4A0808
+
+#define mmDMA_IF_E_S_DMA_BIN 0x4A080C
+
+#define mmDMA_IF_E_S_SOB_CG_EN 0x4A0810
+
+#define mmDMA_IF_E_S_HBM_I2C_ADDR_0 0x4A0820
+
+#define mmDMA_IF_E_S_HBM_I2C_ADDR_1 0x4A0824
+
+#define mmDMA_IF_E_S_HBM_I2C_ADDR_2 0x4A0828
+
+#define mmDMA_IF_E_S_HBM_I2C_ADDR_3 0x4A082C
+
+#define mmDMA_IF_E_S_HBM_I2C_ADDR_4 0x4A0830
+
+#define mmDMA_IF_E_S_HBM_MISC 0x4A0834
+
+#endif /* ASIC_REG_DMA_IF_E_S_REGS_H_ */
diff --git a/drivers/accel/habanalabs/include/gaudi/asic_reg/dma_if_w_n_down_ch0_regs.h b/drivers/accel/habanalabs/include/gaudi/asic_reg/dma_if_w_n_down_ch0_regs.h
new file mode 100644
index 0000000000..4ccaf87129
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi/asic_reg/dma_if_w_n_down_ch0_regs.h
@@ -0,0 +1,896 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2016-2018 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ ** DO NOT EDIT BELOW **
+ ************************************/
+
+#ifndef ASIC_REG_DMA_IF_W_N_DOWN_CH0_REGS_H_
+#define ASIC_REG_DMA_IF_W_N_DOWN_CH0_REGS_H_
+
+/*
+ *****************************************
+ * DMA_IF_W_N_DOWN_CH0 (Prototype: RTR_CTRL)
+ *****************************************
+ */
+
+#define mmDMA_IF_W_N_DOWN_CH0_PERM_SEL 0x4C1108
+
+#define mmDMA_IF_W_N_DOWN_CH0_HBM_POLY_H3_0 0x4C1114
+
+#define mmDMA_IF_W_N_DOWN_CH0_HBM_POLY_H3_1 0x4C1118
+
+#define mmDMA_IF_W_N_DOWN_CH0_HBM_POLY_H3_2 0x4C111C
+
+#define mmDMA_IF_W_N_DOWN_CH0_HBM_POLY_H3_3 0x4C1120
+
+#define mmDMA_IF_W_N_DOWN_CH0_HBM_POLY_H3_4 0x4C1124
+
+#define mmDMA_IF_W_N_DOWN_CH0_HBM_POLY_H3_5 0x4C1128
+
+#define mmDMA_IF_W_N_DOWN_CH0_HBM_POLY_H3_6 0x4C112C
+
+#define mmDMA_IF_W_N_DOWN_CH0_HBM_POLY_H3_7 0x4C1130
+
+#define mmDMA_IF_W_N_DOWN_CH0_HBM_POLY_H3_8 0x4C1134
+
+#define mmDMA_IF_W_N_DOWN_CH0_HBM_POLY_H3_9 0x4C1138
+
+#define mmDMA_IF_W_N_DOWN_CH0_HBM_POLY_H3_10 0x4C113C
+
+#define mmDMA_IF_W_N_DOWN_CH0_HBM_POLY_H3_11 0x4C1140
+
+#define mmDMA_IF_W_N_DOWN_CH0_HBM_POLY_H3_12 0x4C1144
+
+#define mmDMA_IF_W_N_DOWN_CH0_HBM_POLY_H3_13 0x4C1148
+
+#define mmDMA_IF_W_N_DOWN_CH0_HBM_POLY_H3_14 0x4C114C
+
+#define mmDMA_IF_W_N_DOWN_CH0_HBM_POLY_H3_15 0x4C1150
+
+#define mmDMA_IF_W_N_DOWN_CH0_HBM_POLY_H3_16 0x4C1154
+
+#define mmDMA_IF_W_N_DOWN_CH0_HBM_POLY_H3_17 0x4C1158
+
+#define mmDMA_IF_W_N_DOWN_CH0_HBM_POLY_H3_18 0x4C115C
+
+#define mmDMA_IF_W_N_DOWN_CH0_HBM_POLY_H3_19 0x4C1160
+
+#define mmDMA_IF_W_N_DOWN_CH0_HBM_POLY_H3_20 0x4C1164
+
+#define mmDMA_IF_W_N_DOWN_CH0_HBM_POLY_H3_21 0x4C1168
+
+#define mmDMA_IF_W_N_DOWN_CH0_HBM_POLY_H3_22 0x4C116C
+
+#define mmDMA_IF_W_N_DOWN_CH0_HBM_POLY_H3_23 0x4C1170
+
+#define mmDMA_IF_W_N_DOWN_CH0_HBM_POLY_H3_24 0x4C1174
+
+#define mmDMA_IF_W_N_DOWN_CH0_HBM_POLY_H3_25 0x4C1178
+
+#define mmDMA_IF_W_N_DOWN_CH0_HBM_POLY_H3_26 0x4C117C
+
+#define mmDMA_IF_W_N_DOWN_CH0_HBM_POLY_H3_27 0x4C1180
+
+#define mmDMA_IF_W_N_DOWN_CH0_SRAM_POLY_H3_0 0x4C1184
+
+#define mmDMA_IF_W_N_DOWN_CH0_SRAM_POLY_H3_1 0x4C1188
+
+#define mmDMA_IF_W_N_DOWN_CH0_SRAM_POLY_H3_2 0x4C118C
+
+#define mmDMA_IF_W_N_DOWN_CH0_SRAM_POLY_H3_3 0x4C1190
+
+#define mmDMA_IF_W_N_DOWN_CH0_SRAM_POLY_H3_4 0x4C1194
+
+#define mmDMA_IF_W_N_DOWN_CH0_SRAM_POLY_H3_5 0x4C1198
+
+#define mmDMA_IF_W_N_DOWN_CH0_SRAM_POLY_H3_6 0x4C119C
+
+#define mmDMA_IF_W_N_DOWN_CH0_SRAM_POLY_H3_7 0x4C11A0
+
+#define mmDMA_IF_W_N_DOWN_CH0_SRAM_POLY_H3_8 0x4C11A4
+
+#define mmDMA_IF_W_N_DOWN_CH0_SRAM_POLY_H3_9 0x4C11A8
+
+#define mmDMA_IF_W_N_DOWN_CH0_SRAM_POLY_H3_10 0x4C11AC
+
+#define mmDMA_IF_W_N_DOWN_CH0_SRAM_POLY_H3_11 0x4C11B0
+
+#define mmDMA_IF_W_N_DOWN_CH0_SRAM_POLY_H3_12 0x4C11B4
+
+#define mmDMA_IF_W_N_DOWN_CH0_SRAM_POLY_H3_13 0x4C11B8
+
+#define mmDMA_IF_W_N_DOWN_CH0_SRAM_POLY_H3_14 0x4C11BC
+
+#define mmDMA_IF_W_N_DOWN_CH0_SCRAM_SRAM_EN 0x4C126C
+
+#define mmDMA_IF_W_N_DOWN_CH0_RL_HBM_EN 0x4C1274
+
+#define mmDMA_IF_W_N_DOWN_CH0_RL_HBM_SAT 0x4C1278
+
+#define mmDMA_IF_W_N_DOWN_CH0_RL_HBM_RST 0x4C127C
+
+#define mmDMA_IF_W_N_DOWN_CH0_RL_HBM_TIMEOUT 0x4C1280
+
+#define mmDMA_IF_W_N_DOWN_CH0_SCRAM_HBM_EN 0x4C1284
+
+#define mmDMA_IF_W_N_DOWN_CH0_RL_PCI_EN 0x4C1288
+
+#define mmDMA_IF_W_N_DOWN_CH0_RL_PCI_SAT 0x4C128C
+
+#define mmDMA_IF_W_N_DOWN_CH0_RL_PCI_RST 0x4C1290
+
+#define mmDMA_IF_W_N_DOWN_CH0_RL_PCI_TIMEOUT 0x4C1294
+
+#define mmDMA_IF_W_N_DOWN_CH0_RL_SRAM_EN 0x4C129C
+
+#define mmDMA_IF_W_N_DOWN_CH0_RL_SRAM_SAT 0x4C12A0
+
+#define mmDMA_IF_W_N_DOWN_CH0_RL_SRAM_RST 0x4C12A4
+
+#define mmDMA_IF_W_N_DOWN_CH0_RL_SRAM_TIMEOUT 0x4C12AC
+
+#define mmDMA_IF_W_N_DOWN_CH0_RL_SRAM_RED 0x4C12B4
+
+#define mmDMA_IF_W_N_DOWN_CH0_E2E_HBM_EN 0x4C12EC
+
+#define mmDMA_IF_W_N_DOWN_CH0_E2E_PCI_EN 0x4C12F0
+
+#define mmDMA_IF_W_N_DOWN_CH0_E2E_HBM_WR_SIZE 0x4C12F4
+
+#define mmDMA_IF_W_N_DOWN_CH0_E2E_PCI_WR_SIZE 0x4C12F8
+
+#define mmDMA_IF_W_N_DOWN_CH0_E2E_AW_PCI_CTR_SET_EN 0x4C1404
+
+#define mmDMA_IF_W_N_DOWN_CH0_E2E_AW_PCI_CTR_SET 0x4C1408
+
+#define mmDMA_IF_W_N_DOWN_CH0_E2E_AW_PCI_CTR_WRAP 0x4C140C
+
+#define mmDMA_IF_W_N_DOWN_CH0_E2E_AW_PCI_CTR_CNT 0x4C1410
+
+#define mmDMA_IF_W_N_DOWN_CH0_E2E_AW_HBM_CTR_SET_EN 0x4C1414
+
+#define mmDMA_IF_W_N_DOWN_CH0_E2E_AW_HBM_CTR_SET 0x4C1418
+
+#define mmDMA_IF_W_N_DOWN_CH0_E2E_HBM_RD_SIZE 0x4C141C
+
+#define mmDMA_IF_W_N_DOWN_CH0_E2E_PCI_RD_SIZE 0x4C1420
+
+#define mmDMA_IF_W_N_DOWN_CH0_E2E_AR_PCI_CTR_SET_EN 0x4C1424
+
+#define mmDMA_IF_W_N_DOWN_CH0_E2E_AR_PCI_CTR_SET 0x4C1428
+
+#define mmDMA_IF_W_N_DOWN_CH0_E2E_AR_PCI_CTR_WRAP 0x4C142C
+
+#define mmDMA_IF_W_N_DOWN_CH0_E2E_AR_PCI_CTR_CNT 0x4C1430
+
+#define mmDMA_IF_W_N_DOWN_CH0_E2E_AR_HBM_CTR_SET_EN 0x4C1434
+
+#define mmDMA_IF_W_N_DOWN_CH0_E2E_AR_HBM_CTR_SET 0x4C1438
+
+#define mmDMA_IF_W_N_DOWN_CH0_NL_HBM_SEL_0 0x4C1450
+
+#define mmDMA_IF_W_N_DOWN_CH0_NL_HBM_SEL_1 0x4C1454
+
+#define mmDMA_IF_W_N_DOWN_CH0_NON_LIN_EN 0x4C1480
+
+#define mmDMA_IF_W_N_DOWN_CH0_NL_SRAM_BANK_0 0x4C1500
+
+#define mmDMA_IF_W_N_DOWN_CH0_NL_SRAM_BANK_1 0x4C1504
+
+#define mmDMA_IF_W_N_DOWN_CH0_NL_SRAM_BANK_2 0x4C1508
+
+#define mmDMA_IF_W_N_DOWN_CH0_NL_SRAM_BANK_3 0x4C150C
+
+#define mmDMA_IF_W_N_DOWN_CH0_NL_SRAM_BANK_4 0x4C1510
+
+#define mmDMA_IF_W_N_DOWN_CH0_NL_SRAM_OFFSET_0 0x4C1514
+
+#define mmDMA_IF_W_N_DOWN_CH0_NL_SRAM_OFFSET_1 0x4C1520
+
+#define mmDMA_IF_W_N_DOWN_CH0_NL_SRAM_OFFSET_2 0x4C1524
+
+#define mmDMA_IF_W_N_DOWN_CH0_NL_SRAM_OFFSET_3 0x4C1528
+
+#define mmDMA_IF_W_N_DOWN_CH0_NL_SRAM_OFFSET_4 0x4C152C
+
+#define mmDMA_IF_W_N_DOWN_CH0_NL_SRAM_OFFSET_5 0x4C1530
+
+#define mmDMA_IF_W_N_DOWN_CH0_NL_SRAM_OFFSET_6 0x4C1534
+
+#define mmDMA_IF_W_N_DOWN_CH0_NL_SRAM_OFFSET_7 0x4C1538
+
+#define mmDMA_IF_W_N_DOWN_CH0_NL_SRAM_OFFSET_8 0x4C153C
+
+#define mmDMA_IF_W_N_DOWN_CH0_NL_SRAM_OFFSET_9 0x4C1540
+
+#define mmDMA_IF_W_N_DOWN_CH0_NL_HBM_OFFSET_0 0x4C1550
+
+#define mmDMA_IF_W_N_DOWN_CH0_NL_HBM_OFFSET_1 0x4C1554
+
+#define mmDMA_IF_W_N_DOWN_CH0_NL_HBM_OFFSET_2 0x4C1558
+
+#define mmDMA_IF_W_N_DOWN_CH0_NL_HBM_OFFSET_3 0x4C155C
+
+#define mmDMA_IF_W_N_DOWN_CH0_NL_HBM_OFFSET_4 0x4C1560
+
+#define mmDMA_IF_W_N_DOWN_CH0_NL_HBM_OFFSET_5 0x4C1564
+
+#define mmDMA_IF_W_N_DOWN_CH0_NL_HBM_OFFSET_6 0x4C1568
+
+#define mmDMA_IF_W_N_DOWN_CH0_NL_HBM_OFFSET_7 0x4C156C
+
+#define mmDMA_IF_W_N_DOWN_CH0_NL_HBM_OFFSET_8 0x4C1570
+
+#define mmDMA_IF_W_N_DOWN_CH0_NL_HBM_OFFSET_9 0x4C1574
+
+#define mmDMA_IF_W_N_DOWN_CH0_NL_HBM_OFFSET_10 0x4C1578
+
+#define mmDMA_IF_W_N_DOWN_CH0_NL_HBM_OFFSET_11 0x4C157C
+
+#define mmDMA_IF_W_N_DOWN_CH0_NL_HBM_OFFSET_12 0x4C1580
+
+#define mmDMA_IF_W_N_DOWN_CH0_NL_HBM_OFFSET_13 0x4C1584
+
+#define mmDMA_IF_W_N_DOWN_CH0_NL_HBM_OFFSET_14 0x4C1588
+
+#define mmDMA_IF_W_N_DOWN_CH0_NL_HBM_OFFSET_15 0x4C158C
+
+#define mmDMA_IF_W_N_DOWN_CH0_NL_HBM_OFFSET_16 0x4C1590
+
+#define mmDMA_IF_W_N_DOWN_CH0_NL_HBM_OFFSET_17 0x4C1594
+
+#define mmDMA_IF_W_N_DOWN_CH0_NL_HBM_OFFSET_18 0x4C1598
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_0 0x4C15E4
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_1 0x4C15E8
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_2 0x4C15EC
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_3 0x4C15F0
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_4 0x4C15F4
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_5 0x4C15F8
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_6 0x4C15FC
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_7 0x4C1600
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_8 0x4C1604
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_9 0x4C1608
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_10 0x4C160C
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_11 0x4C1610
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_12 0x4C1614
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_13 0x4C1618
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_14 0x4C161C
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_15 0x4C1620
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_0 0x4C1624
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_1 0x4C1628
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_2 0x4C162C
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_3 0x4C1630
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_4 0x4C1634
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_5 0x4C1638
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_6 0x4C163C
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_7 0x4C1640
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_8 0x4C1644
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_9 0x4C1648
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_10 0x4C164C
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_11 0x4C1650
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_12 0x4C1654
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_13 0x4C1658
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_14 0x4C165C
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_15 0x4C1660
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_0 0x4C1664
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_1 0x4C1668
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_2 0x4C166C
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_3 0x4C1670
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_4 0x4C1674
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_5 0x4C1678
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_6 0x4C167C
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_7 0x4C1680
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_8 0x4C1684
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_9 0x4C1688
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_10 0x4C168C
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_11 0x4C1690
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_12 0x4C1694
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_13 0x4C1698
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_14 0x4C169C
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_15 0x4C16A0
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_0 0x4C16A4
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_1 0x4C16A8
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_2 0x4C16AC
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_3 0x4C16B0
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_4 0x4C16B4
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_5 0x4C16B8
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_6 0x4C16BC
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_7 0x4C16C0
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_8 0x4C16C4
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_9 0x4C16C8
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_10 0x4C16CC
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_11 0x4C16D0
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_12 0x4C16D4
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_13 0x4C16D8
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_14 0x4C16DC
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_15 0x4C16E0
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_0 0x4C16E4
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_1 0x4C16E8
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_2 0x4C16EC
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_3 0x4C16F0
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_4 0x4C16F4
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_5 0x4C16F8
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_6 0x4C16FC
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_7 0x4C1700
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_8 0x4C1704
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_9 0x4C1708
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_10 0x4C170C
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_11 0x4C1710
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_12 0x4C1714
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_13 0x4C1718
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_14 0x4C171C
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_15 0x4C1720
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_0 0x4C1724
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_1 0x4C1728
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_2 0x4C172C
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_3 0x4C1730
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_4 0x4C1734
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_5 0x4C1738
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_6 0x4C173C
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_7 0x4C1740
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_8 0x4C1744
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_9 0x4C1748
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_10 0x4C174C
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_11 0x4C1750
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_12 0x4C1754
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_13 0x4C1758
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_14 0x4C175C
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_15 0x4C1760
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_0 0x4C1764
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_1 0x4C1768
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_2 0x4C176C
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_3 0x4C1770
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_4 0x4C1774
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_5 0x4C1778
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_6 0x4C177C
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_7 0x4C1780
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_8 0x4C1784
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_9 0x4C1788
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_10 0x4C178C
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_11 0x4C1790
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_12 0x4C1794
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_13 0x4C1798
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_14 0x4C179C
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_15 0x4C17A0
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_0 0x4C17A4
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_1 0x4C17A8
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_2 0x4C17AC
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_3 0x4C17B0
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_4 0x4C17B4
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_5 0x4C17B8
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_6 0x4C17BC
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_7 0x4C17C0
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_8 0x4C17C4
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_9 0x4C17C8
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_10 0x4C17CC
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_11 0x4C17D0
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_12 0x4C17D4
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_13 0x4C17D8
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_14 0x4C17DC
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_15 0x4C17E0
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_0 0x4C1824
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_1 0x4C1828
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_2 0x4C182C
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_3 0x4C1830
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_4 0x4C1834
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_5 0x4C1838
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_6 0x4C183C
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_7 0x4C1840
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_8 0x4C1844
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_9 0x4C1848
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_10 0x4C184C
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_11 0x4C1850
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_12 0x4C1854
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_13 0x4C1858
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_14 0x4C185C
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_15 0x4C1860
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_0 0x4C1864
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_1 0x4C1868
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_2 0x4C186C
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_3 0x4C1870
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_4 0x4C1874
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_5 0x4C1878
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_6 0x4C187C
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_7 0x4C1880
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_8 0x4C1884
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_9 0x4C1888
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_10 0x4C188C
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_11 0x4C1890
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_12 0x4C1894
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_13 0x4C1898
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_14 0x4C189C
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_15 0x4C18A0
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_0 0x4C18A4
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_1 0x4C18A8
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_2 0x4C18AC
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_3 0x4C18B0
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_4 0x4C18B4
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_5 0x4C18B8
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_6 0x4C18BC
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_7 0x4C18C0
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_8 0x4C18C4
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_9 0x4C18C8
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_10 0x4C18CC
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_11 0x4C18D0
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_12 0x4C18D4
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_13 0x4C18D8
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_14 0x4C18DC
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_15 0x4C18E0
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_0 0x4C18E4
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_1 0x4C18E8
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_2 0x4C18EC
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_3 0x4C18F0
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_4 0x4C18F4
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_5 0x4C18F8
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_6 0x4C18FC
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_7 0x4C1900
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_8 0x4C1904
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_9 0x4C1908
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_10 0x4C190C
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_11 0x4C1910
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_12 0x4C1914
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_13 0x4C1918
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_14 0x4C191C
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_15 0x4C1920
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_0 0x4C1924
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_1 0x4C1928
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_2 0x4C192C
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_3 0x4C1930
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_4 0x4C1934
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_5 0x4C1938
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_6 0x4C193C
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_7 0x4C1940
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_8 0x4C1944
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_9 0x4C1948
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_10 0x4C194C
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_11 0x4C1950
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_12 0x4C1954
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_13 0x4C1958
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_14 0x4C195C
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_15 0x4C1960
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_0 0x4C1964
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_1 0x4C1968
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_2 0x4C196C
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_3 0x4C1970
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_4 0x4C1974
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_5 0x4C1978
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_6 0x4C197C
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_7 0x4C1980
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_8 0x4C1984
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_9 0x4C1988
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_10 0x4C198C
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_11 0x4C1990
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_12 0x4C1994
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_13 0x4C1998
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_14 0x4C199C
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_15 0x4C19A0
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_0 0x4C19A4
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_1 0x4C19A8
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_2 0x4C19AC
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_3 0x4C19B0
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_4 0x4C19B4
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_5 0x4C19B8
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_6 0x4C19BC
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_7 0x4C19C0
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_8 0x4C19C4
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_9 0x4C19C8
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_10 0x4C19CC
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_11 0x4C19D0
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_12 0x4C19D4
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_13 0x4C19D8
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_14 0x4C19DC
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_15 0x4C19E0
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_0 0x4C19E4
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_1 0x4C19E8
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_2 0x4C19EC
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_3 0x4C19F0
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_4 0x4C19F4
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_5 0x4C19F8
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_6 0x4C19FC
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_7 0x4C1A00
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_8 0x4C1A04
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_9 0x4C1A08
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_10 0x4C1A0C
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_11 0x4C1A10
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_12 0x4C1A14
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_13 0x4C1A18
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_14 0x4C1A1C
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_15 0x4C1A20
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_HIT_AW 0x4C1A64
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_HIT_AR 0x4C1A68
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_HIT_AW 0x4C1A6C
+
+#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_HIT_AR 0x4C1A70
+
+#define mmDMA_IF_W_N_DOWN_CH0_RGL_CFG 0x4C1B64
+
+#define mmDMA_IF_W_N_DOWN_CH0_RGL_SHIFT 0x4C1B68
+
+#define mmDMA_IF_W_N_DOWN_CH0_RGL_EXPECTED_LAT_0 0x4C1B6C
+
+#define mmDMA_IF_W_N_DOWN_CH0_RGL_EXPECTED_LAT_1 0x4C1B70
+
+#define mmDMA_IF_W_N_DOWN_CH0_RGL_EXPECTED_LAT_2 0x4C1B74
+
+#define mmDMA_IF_W_N_DOWN_CH0_RGL_EXPECTED_LAT_3 0x4C1B78
+
+#define mmDMA_IF_W_N_DOWN_CH0_RGL_EXPECTED_LAT_4 0x4C1B7C
+
+#define mmDMA_IF_W_N_DOWN_CH0_RGL_EXPECTED_LAT_5 0x4C1B80
+
+#define mmDMA_IF_W_N_DOWN_CH0_RGL_EXPECTED_LAT_6 0x4C1B84
+
+#define mmDMA_IF_W_N_DOWN_CH0_RGL_EXPECTED_LAT_7 0x4C1B88
+
+#define mmDMA_IF_W_N_DOWN_CH0_RGL_TOKEN_0 0x4C1BAC
+
+#define mmDMA_IF_W_N_DOWN_CH0_RGL_TOKEN_1 0x4C1BB0
+
+#define mmDMA_IF_W_N_DOWN_CH0_RGL_TOKEN_2 0x4C1BB4
+
+#define mmDMA_IF_W_N_DOWN_CH0_RGL_TOKEN_3 0x4C1BB8
+
+#define mmDMA_IF_W_N_DOWN_CH0_RGL_TOKEN_4 0x4C1BBC
+
+#define mmDMA_IF_W_N_DOWN_CH0_RGL_TOKEN_5 0x4C1BC0
+
+#define mmDMA_IF_W_N_DOWN_CH0_RGL_TOKEN_6 0x4C1BC4
+
+#define mmDMA_IF_W_N_DOWN_CH0_RGL_TOKEN_7 0x4C1BC8
+
+#define mmDMA_IF_W_N_DOWN_CH0_RGL_BANK_ID_0 0x4C1BEC
+
+#define mmDMA_IF_W_N_DOWN_CH0_RGL_BANK_ID_1 0x4C1BF0
+
+#define mmDMA_IF_W_N_DOWN_CH0_RGL_BANK_ID_2 0x4C1BF4
+
+#define mmDMA_IF_W_N_DOWN_CH0_RGL_BANK_ID_3 0x4C1BF8
+
+#define mmDMA_IF_W_N_DOWN_CH0_RGL_BANK_ID_4 0x4C1BFC
+
+#define mmDMA_IF_W_N_DOWN_CH0_RGL_BANK_ID_5 0x4C1C00
+
+#define mmDMA_IF_W_N_DOWN_CH0_RGL_BANK_ID_6 0x4C1C04
+
+#define mmDMA_IF_W_N_DOWN_CH0_RGL_BANK_ID_7 0x4C1C08
+
+#define mmDMA_IF_W_N_DOWN_CH0_RGL_WDT 0x4C1C2C
+
+#define mmDMA_IF_W_N_DOWN_CH0_E2E_AR_HBM0_CH0_CTR_WRAP 0x4C1C30
+
+#define mmDMA_IF_W_N_DOWN_CH0_E2E_AR_HBM0_CH1_CTR_WRAP 0x4C1C34
+
+#define mmDMA_IF_W_N_DOWN_CH0_E2E_AR_HBM1_CH0_CTR_WRAP 0x4C1C38
+
+#define mmDMA_IF_W_N_DOWN_CH0_E2E_AR_HBM1_CH1_CTR_WRAP 0x4C1C3C
+
+#define mmDMA_IF_W_N_DOWN_CH0_E2E_AR_HBM2_CH0_CTR_WRAP 0x4C1C40
+
+#define mmDMA_IF_W_N_DOWN_CH0_E2E_AR_HBM2_CH1_CTR_WRAP 0x4C1C44
+
+#define mmDMA_IF_W_N_DOWN_CH0_E2E_AR_HBM3_CH0_CTR_WRAP 0x4C1C48
+
+#define mmDMA_IF_W_N_DOWN_CH0_E2E_AR_HBM3_CH1_CTR_WRAP 0x4C1C4C
+
+#define mmDMA_IF_W_N_DOWN_CH0_E2E_AR_HBM0_CH0_CTR_CNT 0x4C1C50
+
+#define mmDMA_IF_W_N_DOWN_CH0_E2E_AR_HBM0_CH1_CTR_CNT 0x4C1C54
+
+#define mmDMA_IF_W_N_DOWN_CH0_E2E_AR_HBM1_CH0_CTR_CNT 0x4C1C58
+
+#define mmDMA_IF_W_N_DOWN_CH0_E2E_AR_HBM1_CH1_CTR_CNT 0x4C1C5C
+
+#define mmDMA_IF_W_N_DOWN_CH0_E2E_AR_HBM2_CH0_CTR_CNT 0x4C1C60
+
+#define mmDMA_IF_W_N_DOWN_CH0_E2E_AR_HBM2_CH1_CTR_CNT 0x4C1C64
+
+#define mmDMA_IF_W_N_DOWN_CH0_E2E_AR_HBM3_CH0_CTR_CNT 0x4C1C68
+
+#define mmDMA_IF_W_N_DOWN_CH0_E2E_AR_HBM3_CH1_CTR_CNT 0x4C1C6C
+
+#define mmDMA_IF_W_N_DOWN_CH0_E2E_AW_HBM0_CH0_CTR_WRAP 0x4C1C70
+
+#define mmDMA_IF_W_N_DOWN_CH0_E2E_AW_HBM0_CH1_CTR_WRAP 0x4C1C74
+
+#define mmDMA_IF_W_N_DOWN_CH0_E2E_AW_HBM1_CH0_CTR_WRAP 0x4C1C78
+
+#define mmDMA_IF_W_N_DOWN_CH0_E2E_AW_HBM1_CH1_CTR_WRAP 0x4C1C7C
+
+#define mmDMA_IF_W_N_DOWN_CH0_E2E_AW_HBM2_CH0_CTR_WRAP 0x4C1C80
+
+#define mmDMA_IF_W_N_DOWN_CH0_E2E_AW_HBM2_CH1_CTR_WRAP 0x4C1C84
+
+#define mmDMA_IF_W_N_DOWN_CH0_E2E_AW_HBM3_CH0_CTR_WRAP 0x4C1C88
+
+#define mmDMA_IF_W_N_DOWN_CH0_E2E_AW_HBM3_CH1_CTR_WRAP 0x4C1C8C
+
+#define mmDMA_IF_W_N_DOWN_CH0_E2E_AW_HBM0_CH0_CTR_CNT 0x4C1C90
+
+#define mmDMA_IF_W_N_DOWN_CH0_E2E_AW_HBM0_CH1_CTR_CNT 0x4C1C94
+
+#define mmDMA_IF_W_N_DOWN_CH0_E2E_AW_HBM1_CH0_CTR_CNT 0x4C1C98
+
+#define mmDMA_IF_W_N_DOWN_CH0_E2E_AW_HBM1_CH1_CTR_CNT 0x4C1C9C
+
+#define mmDMA_IF_W_N_DOWN_CH0_E2E_AW_HBM2_CH0_CTR_CNT 0x4C1CA0
+
+#define mmDMA_IF_W_N_DOWN_CH0_E2E_AW_HBM2_CH1_CTR_CNT 0x4C1CA4
+
+#define mmDMA_IF_W_N_DOWN_CH0_E2E_AW_HBM3_CH0_CTR_CNT 0x4C1CA8
+
+#define mmDMA_IF_W_N_DOWN_CH0_E2E_AW_HBM3_CH1_CTR_CNT 0x4C1CAC
+
+#define mmDMA_IF_W_N_DOWN_CH0_NL_HBM_PC_SEL_0 0x4C1CB0
+
+#define mmDMA_IF_W_N_DOWN_CH0_NL_HBM_PC_SEL_1 0x4C1CB4
+
+#define mmDMA_IF_W_N_DOWN_CH0_NL_HBM_PC_SEL_2 0x4C1CB8
+
+#define mmDMA_IF_W_N_DOWN_CH0_NL_HBM_PC_SEL_3 0x4C1CBC
+
+#endif /* ASIC_REG_DMA_IF_W_N_DOWN_CH0_REGS_H_ */
diff --git a/drivers/accel/habanalabs/include/gaudi/asic_reg/dma_if_w_n_down_ch1_regs.h b/drivers/accel/habanalabs/include/gaudi/asic_reg/dma_if_w_n_down_ch1_regs.h
new file mode 100644
index 0000000000..9236f41830
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi/asic_reg/dma_if_w_n_down_ch1_regs.h
@@ -0,0 +1,896 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2016-2018 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ ** DO NOT EDIT BELOW **
+ ************************************/
+
+#ifndef ASIC_REG_DMA_IF_W_N_DOWN_CH1_REGS_H_
+#define ASIC_REG_DMA_IF_W_N_DOWN_CH1_REGS_H_
+
+/*
+ *****************************************
+ * DMA_IF_W_N_DOWN_CH1 (Prototype: RTR_CTRL)
+ *****************************************
+ */
+
+#define mmDMA_IF_W_N_DOWN_CH1_PERM_SEL 0x4C2108
+
+#define mmDMA_IF_W_N_DOWN_CH1_HBM_POLY_H3_0 0x4C2114
+
+#define mmDMA_IF_W_N_DOWN_CH1_HBM_POLY_H3_1 0x4C2118
+
+#define mmDMA_IF_W_N_DOWN_CH1_HBM_POLY_H3_2 0x4C211C
+
+#define mmDMA_IF_W_N_DOWN_CH1_HBM_POLY_H3_3 0x4C2120
+
+#define mmDMA_IF_W_N_DOWN_CH1_HBM_POLY_H3_4 0x4C2124
+
+#define mmDMA_IF_W_N_DOWN_CH1_HBM_POLY_H3_5 0x4C2128
+
+#define mmDMA_IF_W_N_DOWN_CH1_HBM_POLY_H3_6 0x4C212C
+
+#define mmDMA_IF_W_N_DOWN_CH1_HBM_POLY_H3_7 0x4C2130
+
+#define mmDMA_IF_W_N_DOWN_CH1_HBM_POLY_H3_8 0x4C2134
+
+#define mmDMA_IF_W_N_DOWN_CH1_HBM_POLY_H3_9 0x4C2138
+
+#define mmDMA_IF_W_N_DOWN_CH1_HBM_POLY_H3_10 0x4C213C
+
+#define mmDMA_IF_W_N_DOWN_CH1_HBM_POLY_H3_11 0x4C2140
+
+#define mmDMA_IF_W_N_DOWN_CH1_HBM_POLY_H3_12 0x4C2144
+
+#define mmDMA_IF_W_N_DOWN_CH1_HBM_POLY_H3_13 0x4C2148
+
+#define mmDMA_IF_W_N_DOWN_CH1_HBM_POLY_H3_14 0x4C214C
+
+#define mmDMA_IF_W_N_DOWN_CH1_HBM_POLY_H3_15 0x4C2150
+
+#define mmDMA_IF_W_N_DOWN_CH1_HBM_POLY_H3_16 0x4C2154
+
+#define mmDMA_IF_W_N_DOWN_CH1_HBM_POLY_H3_17 0x4C2158
+
+#define mmDMA_IF_W_N_DOWN_CH1_HBM_POLY_H3_18 0x4C215C
+
+#define mmDMA_IF_W_N_DOWN_CH1_HBM_POLY_H3_19 0x4C2160
+
+#define mmDMA_IF_W_N_DOWN_CH1_HBM_POLY_H3_20 0x4C2164
+
+#define mmDMA_IF_W_N_DOWN_CH1_HBM_POLY_H3_21 0x4C2168
+
+#define mmDMA_IF_W_N_DOWN_CH1_HBM_POLY_H3_22 0x4C216C
+
+#define mmDMA_IF_W_N_DOWN_CH1_HBM_POLY_H3_23 0x4C2170
+
+#define mmDMA_IF_W_N_DOWN_CH1_HBM_POLY_H3_24 0x4C2174
+
+#define mmDMA_IF_W_N_DOWN_CH1_HBM_POLY_H3_25 0x4C2178
+
+#define mmDMA_IF_W_N_DOWN_CH1_HBM_POLY_H3_26 0x4C217C
+
+#define mmDMA_IF_W_N_DOWN_CH1_HBM_POLY_H3_27 0x4C2180
+
+#define mmDMA_IF_W_N_DOWN_CH1_SRAM_POLY_H3_0 0x4C2184
+
+#define mmDMA_IF_W_N_DOWN_CH1_SRAM_POLY_H3_1 0x4C2188
+
+#define mmDMA_IF_W_N_DOWN_CH1_SRAM_POLY_H3_2 0x4C218C
+
+#define mmDMA_IF_W_N_DOWN_CH1_SRAM_POLY_H3_3 0x4C2190
+
+#define mmDMA_IF_W_N_DOWN_CH1_SRAM_POLY_H3_4 0x4C2194
+
+#define mmDMA_IF_W_N_DOWN_CH1_SRAM_POLY_H3_5 0x4C2198
+
+#define mmDMA_IF_W_N_DOWN_CH1_SRAM_POLY_H3_6 0x4C219C
+
+#define mmDMA_IF_W_N_DOWN_CH1_SRAM_POLY_H3_7 0x4C21A0
+
+#define mmDMA_IF_W_N_DOWN_CH1_SRAM_POLY_H3_8 0x4C21A4
+
+#define mmDMA_IF_W_N_DOWN_CH1_SRAM_POLY_H3_9 0x4C21A8
+
+#define mmDMA_IF_W_N_DOWN_CH1_SRAM_POLY_H3_10 0x4C21AC
+
+#define mmDMA_IF_W_N_DOWN_CH1_SRAM_POLY_H3_11 0x4C21B0
+
+#define mmDMA_IF_W_N_DOWN_CH1_SRAM_POLY_H3_12 0x4C21B4
+
+#define mmDMA_IF_W_N_DOWN_CH1_SRAM_POLY_H3_13 0x4C21B8
+
+#define mmDMA_IF_W_N_DOWN_CH1_SRAM_POLY_H3_14 0x4C21BC
+
+#define mmDMA_IF_W_N_DOWN_CH1_SCRAM_SRAM_EN 0x4C226C
+
+#define mmDMA_IF_W_N_DOWN_CH1_RL_HBM_EN 0x4C2274
+
+#define mmDMA_IF_W_N_DOWN_CH1_RL_HBM_SAT 0x4C2278
+
+#define mmDMA_IF_W_N_DOWN_CH1_RL_HBM_RST 0x4C227C
+
+#define mmDMA_IF_W_N_DOWN_CH1_RL_HBM_TIMEOUT 0x4C2280
+
+#define mmDMA_IF_W_N_DOWN_CH1_SCRAM_HBM_EN 0x4C2284
+
+#define mmDMA_IF_W_N_DOWN_CH1_RL_PCI_EN 0x4C2288
+
+#define mmDMA_IF_W_N_DOWN_CH1_RL_PCI_SAT 0x4C228C
+
+#define mmDMA_IF_W_N_DOWN_CH1_RL_PCI_RST 0x4C2290
+
+#define mmDMA_IF_W_N_DOWN_CH1_RL_PCI_TIMEOUT 0x4C2294
+
+#define mmDMA_IF_W_N_DOWN_CH1_RL_SRAM_EN 0x4C229C
+
+#define mmDMA_IF_W_N_DOWN_CH1_RL_SRAM_SAT 0x4C22A0
+
+#define mmDMA_IF_W_N_DOWN_CH1_RL_SRAM_RST 0x4C22A4
+
+#define mmDMA_IF_W_N_DOWN_CH1_RL_SRAM_TIMEOUT 0x4C22AC
+
+#define mmDMA_IF_W_N_DOWN_CH1_RL_SRAM_RED 0x4C22B4
+
+#define mmDMA_IF_W_N_DOWN_CH1_E2E_HBM_EN 0x4C22EC
+
+#define mmDMA_IF_W_N_DOWN_CH1_E2E_PCI_EN 0x4C22F0
+
+#define mmDMA_IF_W_N_DOWN_CH1_E2E_HBM_WR_SIZE 0x4C22F4
+
+#define mmDMA_IF_W_N_DOWN_CH1_E2E_PCI_WR_SIZE 0x4C22F8
+
+#define mmDMA_IF_W_N_DOWN_CH1_E2E_AW_PCI_CTR_SET_EN 0x4C2404
+
+#define mmDMA_IF_W_N_DOWN_CH1_E2E_AW_PCI_CTR_SET 0x4C2408
+
+#define mmDMA_IF_W_N_DOWN_CH1_E2E_AW_PCI_CTR_WRAP 0x4C240C
+
+#define mmDMA_IF_W_N_DOWN_CH1_E2E_AW_PCI_CTR_CNT 0x4C2410
+
+#define mmDMA_IF_W_N_DOWN_CH1_E2E_AW_HBM_CTR_SET_EN 0x4C2414
+
+#define mmDMA_IF_W_N_DOWN_CH1_E2E_AW_HBM_CTR_SET 0x4C2418
+
+#define mmDMA_IF_W_N_DOWN_CH1_E2E_HBM_RD_SIZE 0x4C241C
+
+#define mmDMA_IF_W_N_DOWN_CH1_E2E_PCI_RD_SIZE 0x4C2420
+
+#define mmDMA_IF_W_N_DOWN_CH1_E2E_AR_PCI_CTR_SET_EN 0x4C2424
+
+#define mmDMA_IF_W_N_DOWN_CH1_E2E_AR_PCI_CTR_SET 0x4C2428
+
+#define mmDMA_IF_W_N_DOWN_CH1_E2E_AR_PCI_CTR_WRAP 0x4C242C
+
+#define mmDMA_IF_W_N_DOWN_CH1_E2E_AR_PCI_CTR_CNT 0x4C2430
+
+#define mmDMA_IF_W_N_DOWN_CH1_E2E_AR_HBM_CTR_SET_EN 0x4C2434
+
+#define mmDMA_IF_W_N_DOWN_CH1_E2E_AR_HBM_CTR_SET 0x4C2438
+
+#define mmDMA_IF_W_N_DOWN_CH1_NL_HBM_SEL_0 0x4C2450
+
+#define mmDMA_IF_W_N_DOWN_CH1_NL_HBM_SEL_1 0x4C2454
+
+#define mmDMA_IF_W_N_DOWN_CH1_NON_LIN_EN 0x4C2480
+
+#define mmDMA_IF_W_N_DOWN_CH1_NL_SRAM_BANK_0 0x4C2500
+
+#define mmDMA_IF_W_N_DOWN_CH1_NL_SRAM_BANK_1 0x4C2504
+
+#define mmDMA_IF_W_N_DOWN_CH1_NL_SRAM_BANK_2 0x4C2508
+
+#define mmDMA_IF_W_N_DOWN_CH1_NL_SRAM_BANK_3 0x4C250C
+
+#define mmDMA_IF_W_N_DOWN_CH1_NL_SRAM_BANK_4 0x4C2510
+
+#define mmDMA_IF_W_N_DOWN_CH1_NL_SRAM_OFFSET_0 0x4C2514
+
+#define mmDMA_IF_W_N_DOWN_CH1_NL_SRAM_OFFSET_1 0x4C2520
+
+#define mmDMA_IF_W_N_DOWN_CH1_NL_SRAM_OFFSET_2 0x4C2524
+
+#define mmDMA_IF_W_N_DOWN_CH1_NL_SRAM_OFFSET_3 0x4C2528
+
+#define mmDMA_IF_W_N_DOWN_CH1_NL_SRAM_OFFSET_4 0x4C252C
+
+#define mmDMA_IF_W_N_DOWN_CH1_NL_SRAM_OFFSET_5 0x4C2530
+
+#define mmDMA_IF_W_N_DOWN_CH1_NL_SRAM_OFFSET_6 0x4C2534
+
+#define mmDMA_IF_W_N_DOWN_CH1_NL_SRAM_OFFSET_7 0x4C2538
+
+#define mmDMA_IF_W_N_DOWN_CH1_NL_SRAM_OFFSET_8 0x4C253C
+
+#define mmDMA_IF_W_N_DOWN_CH1_NL_SRAM_OFFSET_9 0x4C2540
+
+#define mmDMA_IF_W_N_DOWN_CH1_NL_HBM_OFFSET_0 0x4C2550
+
+#define mmDMA_IF_W_N_DOWN_CH1_NL_HBM_OFFSET_1 0x4C2554
+
+#define mmDMA_IF_W_N_DOWN_CH1_NL_HBM_OFFSET_2 0x4C2558
+
+#define mmDMA_IF_W_N_DOWN_CH1_NL_HBM_OFFSET_3 0x4C255C
+
+#define mmDMA_IF_W_N_DOWN_CH1_NL_HBM_OFFSET_4 0x4C2560
+
+#define mmDMA_IF_W_N_DOWN_CH1_NL_HBM_OFFSET_5 0x4C2564
+
+#define mmDMA_IF_W_N_DOWN_CH1_NL_HBM_OFFSET_6 0x4C2568
+
+#define mmDMA_IF_W_N_DOWN_CH1_NL_HBM_OFFSET_7 0x4C256C
+
+#define mmDMA_IF_W_N_DOWN_CH1_NL_HBM_OFFSET_8 0x4C2570
+
+#define mmDMA_IF_W_N_DOWN_CH1_NL_HBM_OFFSET_9 0x4C2574
+
+#define mmDMA_IF_W_N_DOWN_CH1_NL_HBM_OFFSET_10 0x4C2578
+
+#define mmDMA_IF_W_N_DOWN_CH1_NL_HBM_OFFSET_11 0x4C257C
+
+#define mmDMA_IF_W_N_DOWN_CH1_NL_HBM_OFFSET_12 0x4C2580
+
+#define mmDMA_IF_W_N_DOWN_CH1_NL_HBM_OFFSET_13 0x4C2584
+
+#define mmDMA_IF_W_N_DOWN_CH1_NL_HBM_OFFSET_14 0x4C2588
+
+#define mmDMA_IF_W_N_DOWN_CH1_NL_HBM_OFFSET_15 0x4C258C
+
+#define mmDMA_IF_W_N_DOWN_CH1_NL_HBM_OFFSET_16 0x4C2590
+
+#define mmDMA_IF_W_N_DOWN_CH1_NL_HBM_OFFSET_17 0x4C2594
+
+#define mmDMA_IF_W_N_DOWN_CH1_NL_HBM_OFFSET_18 0x4C2598
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_0 0x4C25E4
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_1 0x4C25E8
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_2 0x4C25EC
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_3 0x4C25F0
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_4 0x4C25F4
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_5 0x4C25F8
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_6 0x4C25FC
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_7 0x4C2600
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_8 0x4C2604
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_9 0x4C2608
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_10 0x4C260C
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_11 0x4C2610
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_12 0x4C2614
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_13 0x4C2618
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_14 0x4C261C
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_15 0x4C2620
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_0 0x4C2624
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_1 0x4C2628
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_2 0x4C262C
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_3 0x4C2630
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_4 0x4C2634
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_5 0x4C2638
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_6 0x4C263C
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_7 0x4C2640
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_8 0x4C2644
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_9 0x4C2648
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_10 0x4C264C
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_11 0x4C2650
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_12 0x4C2654
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_13 0x4C2658
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_14 0x4C265C
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_15 0x4C2660
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_0 0x4C2664
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_1 0x4C2668
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_2 0x4C266C
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_3 0x4C2670
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_4 0x4C2674
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_5 0x4C2678
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_6 0x4C267C
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_7 0x4C2680
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_8 0x4C2684
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_9 0x4C2688
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_10 0x4C268C
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_11 0x4C2690
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_12 0x4C2694
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_13 0x4C2698
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_14 0x4C269C
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_15 0x4C26A0
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_0 0x4C26A4
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_1 0x4C26A8
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_2 0x4C26AC
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_3 0x4C26B0
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_4 0x4C26B4
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_5 0x4C26B8
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_6 0x4C26BC
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_7 0x4C26C0
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_8 0x4C26C4
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_9 0x4C26C8
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_10 0x4C26CC
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_11 0x4C26D0
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_12 0x4C26D4
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_13 0x4C26D8
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_14 0x4C26DC
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_15 0x4C26E0
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_0 0x4C26E4
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_1 0x4C26E8
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_2 0x4C26EC
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_3 0x4C26F0
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_4 0x4C26F4
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_5 0x4C26F8
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_6 0x4C26FC
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_7 0x4C2700
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_8 0x4C2704
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_9 0x4C2708
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_10 0x4C270C
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_11 0x4C2710
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_12 0x4C2714
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_13 0x4C2718
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_14 0x4C271C
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_15 0x4C2720
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_0 0x4C2724
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_1 0x4C2728
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_2 0x4C272C
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_3 0x4C2730
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_4 0x4C2734
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_5 0x4C2738
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_6 0x4C273C
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_7 0x4C2740
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_8 0x4C2744
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_9 0x4C2748
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_10 0x4C274C
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_11 0x4C2750
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_12 0x4C2754
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_13 0x4C2758
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_14 0x4C275C
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_15 0x4C2760
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_0 0x4C2764
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_1 0x4C2768
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_2 0x4C276C
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_3 0x4C2770
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_4 0x4C2774
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_5 0x4C2778
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_6 0x4C277C
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_7 0x4C2780
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_8 0x4C2784
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_9 0x4C2788
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_10 0x4C278C
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_11 0x4C2790
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_12 0x4C2794
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_13 0x4C2798
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_14 0x4C279C
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_15 0x4C27A0
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_0 0x4C27A4
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_1 0x4C27A8
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_2 0x4C27AC
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_3 0x4C27B0
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_4 0x4C27B4
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_5 0x4C27B8
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_6 0x4C27BC
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_7 0x4C27C0
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_8 0x4C27C4
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_9 0x4C27C8
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_10 0x4C27CC
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_11 0x4C27D0
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_12 0x4C27D4
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_13 0x4C27D8
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_14 0x4C27DC
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_15 0x4C27E0
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_0 0x4C2824
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_1 0x4C2828
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_2 0x4C282C
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_3 0x4C2830
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_4 0x4C2834
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_5 0x4C2838
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_6 0x4C283C
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_7 0x4C2840
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_8 0x4C2844
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_9 0x4C2848
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_10 0x4C284C
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_11 0x4C2850
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_12 0x4C2854
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_13 0x4C2858
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_14 0x4C285C
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_15 0x4C2860
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_0 0x4C2864
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_1 0x4C2868
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_2 0x4C286C
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_3 0x4C2870
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_4 0x4C2874
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_5 0x4C2878
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_6 0x4C287C
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_7 0x4C2880
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_8 0x4C2884
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_9 0x4C2888
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_10 0x4C288C
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_11 0x4C2890
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_12 0x4C2894
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_13 0x4C2898
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_14 0x4C289C
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_15 0x4C28A0
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_0 0x4C28A4
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_1 0x4C28A8
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_2 0x4C28AC
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_3 0x4C28B0
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_4 0x4C28B4
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_5 0x4C28B8
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_6 0x4C28BC
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_7 0x4C28C0
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_8 0x4C28C4
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_9 0x4C28C8
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_10 0x4C28CC
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_11 0x4C28D0
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_12 0x4C28D4
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_13 0x4C28D8
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_14 0x4C28DC
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_15 0x4C28E0
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_0 0x4C28E4
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_1 0x4C28E8
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_2 0x4C28EC
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_3 0x4C28F0
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_4 0x4C28F4
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_5 0x4C28F8
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_6 0x4C28FC
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_7 0x4C2900
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_8 0x4C2904
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_9 0x4C2908
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_10 0x4C290C
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_11 0x4C2910
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_12 0x4C2914
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_13 0x4C2918
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_14 0x4C291C
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_15 0x4C2920
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_0 0x4C2924
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_1 0x4C2928
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_2 0x4C292C
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_3 0x4C2930
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_4 0x4C2934
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_5 0x4C2938
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_6 0x4C293C
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_7 0x4C2940
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_8 0x4C2944
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_9 0x4C2948
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_10 0x4C294C
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_11 0x4C2950
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_12 0x4C2954
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_13 0x4C2958
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_14 0x4C295C
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_15 0x4C2960
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_0 0x4C2964
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_1 0x4C2968
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_2 0x4C296C
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_3 0x4C2970
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_4 0x4C2974
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_5 0x4C2978
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_6 0x4C297C
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_7 0x4C2980
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_8 0x4C2984
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_9 0x4C2988
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_10 0x4C298C
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_11 0x4C2990
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_12 0x4C2994
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_13 0x4C2998
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_14 0x4C299C
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_15 0x4C29A0
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_0 0x4C29A4
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_1 0x4C29A8
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_2 0x4C29AC
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_3 0x4C29B0
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_4 0x4C29B4
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_5 0x4C29B8
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_6 0x4C29BC
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_7 0x4C29C0
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_8 0x4C29C4
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_9 0x4C29C8
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_10 0x4C29CC
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_11 0x4C29D0
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_12 0x4C29D4
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_13 0x4C29D8
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_14 0x4C29DC
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_15 0x4C29E0
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_0 0x4C29E4
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_1 0x4C29E8
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_2 0x4C29EC
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_3 0x4C29F0
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_4 0x4C29F4
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_5 0x4C29F8
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_6 0x4C29FC
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_7 0x4C2A00
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_8 0x4C2A04
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_9 0x4C2A08
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_10 0x4C2A0C
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_11 0x4C2A10
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_12 0x4C2A14
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_13 0x4C2A18
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_14 0x4C2A1C
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_15 0x4C2A20
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_HIT_AW 0x4C2A64
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_HIT_AR 0x4C2A68
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_HIT_AW 0x4C2A6C
+
+#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_HIT_AR 0x4C2A70
+
+#define mmDMA_IF_W_N_DOWN_CH1_RGL_CFG 0x4C2B64
+
+#define mmDMA_IF_W_N_DOWN_CH1_RGL_SHIFT 0x4C2B68
+
+#define mmDMA_IF_W_N_DOWN_CH1_RGL_EXPECTED_LAT_0 0x4C2B6C
+
+#define mmDMA_IF_W_N_DOWN_CH1_RGL_EXPECTED_LAT_1 0x4C2B70
+
+#define mmDMA_IF_W_N_DOWN_CH1_RGL_EXPECTED_LAT_2 0x4C2B74
+
+#define mmDMA_IF_W_N_DOWN_CH1_RGL_EXPECTED_LAT_3 0x4C2B78
+
+#define mmDMA_IF_W_N_DOWN_CH1_RGL_EXPECTED_LAT_4 0x4C2B7C
+
+#define mmDMA_IF_W_N_DOWN_CH1_RGL_EXPECTED_LAT_5 0x4C2B80
+
+#define mmDMA_IF_W_N_DOWN_CH1_RGL_EXPECTED_LAT_6 0x4C2B84
+
+#define mmDMA_IF_W_N_DOWN_CH1_RGL_EXPECTED_LAT_7 0x4C2B88
+
+#define mmDMA_IF_W_N_DOWN_CH1_RGL_TOKEN_0 0x4C2BAC
+
+#define mmDMA_IF_W_N_DOWN_CH1_RGL_TOKEN_1 0x4C2BB0
+
+#define mmDMA_IF_W_N_DOWN_CH1_RGL_TOKEN_2 0x4C2BB4
+
+#define mmDMA_IF_W_N_DOWN_CH1_RGL_TOKEN_3 0x4C2BB8
+
+#define mmDMA_IF_W_N_DOWN_CH1_RGL_TOKEN_4 0x4C2BBC
+
+#define mmDMA_IF_W_N_DOWN_CH1_RGL_TOKEN_5 0x4C2BC0
+
+#define mmDMA_IF_W_N_DOWN_CH1_RGL_TOKEN_6 0x4C2BC4
+
+#define mmDMA_IF_W_N_DOWN_CH1_RGL_TOKEN_7 0x4C2BC8
+
+#define mmDMA_IF_W_N_DOWN_CH1_RGL_BANK_ID_0 0x4C2BEC
+
+#define mmDMA_IF_W_N_DOWN_CH1_RGL_BANK_ID_1 0x4C2BF0
+
+#define mmDMA_IF_W_N_DOWN_CH1_RGL_BANK_ID_2 0x4C2BF4
+
+#define mmDMA_IF_W_N_DOWN_CH1_RGL_BANK_ID_3 0x4C2BF8
+
+#define mmDMA_IF_W_N_DOWN_CH1_RGL_BANK_ID_4 0x4C2BFC
+
+#define mmDMA_IF_W_N_DOWN_CH1_RGL_BANK_ID_5 0x4C2C00
+
+#define mmDMA_IF_W_N_DOWN_CH1_RGL_BANK_ID_6 0x4C2C04
+
+#define mmDMA_IF_W_N_DOWN_CH1_RGL_BANK_ID_7 0x4C2C08
+
+#define mmDMA_IF_W_N_DOWN_CH1_RGL_WDT 0x4C2C2C
+
+#define mmDMA_IF_W_N_DOWN_CH1_E2E_AR_HBM0_CH0_CTR_WRAP 0x4C2C30
+
+#define mmDMA_IF_W_N_DOWN_CH1_E2E_AR_HBM0_CH1_CTR_WRAP 0x4C2C34
+
+#define mmDMA_IF_W_N_DOWN_CH1_E2E_AR_HBM1_CH0_CTR_WRAP 0x4C2C38
+
+#define mmDMA_IF_W_N_DOWN_CH1_E2E_AR_HBM1_CH1_CTR_WRAP 0x4C2C3C
+
+#define mmDMA_IF_W_N_DOWN_CH1_E2E_AR_HBM2_CH0_CTR_WRAP 0x4C2C40
+
+#define mmDMA_IF_W_N_DOWN_CH1_E2E_AR_HBM2_CH1_CTR_WRAP 0x4C2C44
+
+#define mmDMA_IF_W_N_DOWN_CH1_E2E_AR_HBM3_CH0_CTR_WRAP 0x4C2C48
+
+#define mmDMA_IF_W_N_DOWN_CH1_E2E_AR_HBM3_CH1_CTR_WRAP 0x4C2C4C
+
+#define mmDMA_IF_W_N_DOWN_CH1_E2E_AR_HBM0_CH0_CTR_CNT 0x4C2C50
+
+#define mmDMA_IF_W_N_DOWN_CH1_E2E_AR_HBM0_CH1_CTR_CNT 0x4C2C54
+
+#define mmDMA_IF_W_N_DOWN_CH1_E2E_AR_HBM1_CH0_CTR_CNT 0x4C2C58
+
+#define mmDMA_IF_W_N_DOWN_CH1_E2E_AR_HBM1_CH1_CTR_CNT 0x4C2C5C
+
+#define mmDMA_IF_W_N_DOWN_CH1_E2E_AR_HBM2_CH0_CTR_CNT 0x4C2C60
+
+#define mmDMA_IF_W_N_DOWN_CH1_E2E_AR_HBM2_CH1_CTR_CNT 0x4C2C64
+
+#define mmDMA_IF_W_N_DOWN_CH1_E2E_AR_HBM3_CH0_CTR_CNT 0x4C2C68
+
+#define mmDMA_IF_W_N_DOWN_CH1_E2E_AR_HBM3_CH1_CTR_CNT 0x4C2C6C
+
+#define mmDMA_IF_W_N_DOWN_CH1_E2E_AW_HBM0_CH0_CTR_WRAP 0x4C2C70
+
+#define mmDMA_IF_W_N_DOWN_CH1_E2E_AW_HBM0_CH1_CTR_WRAP 0x4C2C74
+
+#define mmDMA_IF_W_N_DOWN_CH1_E2E_AW_HBM1_CH0_CTR_WRAP 0x4C2C78
+
+#define mmDMA_IF_W_N_DOWN_CH1_E2E_AW_HBM1_CH1_CTR_WRAP 0x4C2C7C
+
+#define mmDMA_IF_W_N_DOWN_CH1_E2E_AW_HBM2_CH0_CTR_WRAP 0x4C2C80
+
+#define mmDMA_IF_W_N_DOWN_CH1_E2E_AW_HBM2_CH1_CTR_WRAP 0x4C2C84
+
+#define mmDMA_IF_W_N_DOWN_CH1_E2E_AW_HBM3_CH0_CTR_WRAP 0x4C2C88
+
+#define mmDMA_IF_W_N_DOWN_CH1_E2E_AW_HBM3_CH1_CTR_WRAP 0x4C2C8C
+
+#define mmDMA_IF_W_N_DOWN_CH1_E2E_AW_HBM0_CH0_CTR_CNT 0x4C2C90
+
+#define mmDMA_IF_W_N_DOWN_CH1_E2E_AW_HBM0_CH1_CTR_CNT 0x4C2C94
+
+#define mmDMA_IF_W_N_DOWN_CH1_E2E_AW_HBM1_CH0_CTR_CNT 0x4C2C98
+
+#define mmDMA_IF_W_N_DOWN_CH1_E2E_AW_HBM1_CH1_CTR_CNT 0x4C2C9C
+
+#define mmDMA_IF_W_N_DOWN_CH1_E2E_AW_HBM2_CH0_CTR_CNT 0x4C2CA0
+
+#define mmDMA_IF_W_N_DOWN_CH1_E2E_AW_HBM2_CH1_CTR_CNT 0x4C2CA4
+
+#define mmDMA_IF_W_N_DOWN_CH1_E2E_AW_HBM3_CH0_CTR_CNT 0x4C2CA8
+
+#define mmDMA_IF_W_N_DOWN_CH1_E2E_AW_HBM3_CH1_CTR_CNT 0x4C2CAC
+
+#define mmDMA_IF_W_N_DOWN_CH1_NL_HBM_PC_SEL_0 0x4C2CB0
+
+#define mmDMA_IF_W_N_DOWN_CH1_NL_HBM_PC_SEL_1 0x4C2CB4
+
+#define mmDMA_IF_W_N_DOWN_CH1_NL_HBM_PC_SEL_2 0x4C2CB8
+
+#define mmDMA_IF_W_N_DOWN_CH1_NL_HBM_PC_SEL_3 0x4C2CBC
+
+#endif /* ASIC_REG_DMA_IF_W_N_DOWN_CH1_REGS_H_ */
diff --git a/drivers/accel/habanalabs/include/gaudi/asic_reg/dma_if_w_n_regs.h b/drivers/accel/habanalabs/include/gaudi/asic_reg/dma_if_w_n_regs.h
new file mode 100644
index 0000000000..da60893a5f
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi/asic_reg/dma_if_w_n_regs.h
@@ -0,0 +1,860 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2016-2018 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ ** DO NOT EDIT BELOW **
+ ************************************/
+
+#ifndef ASIC_REG_DMA_IF_W_N_REGS_H_
+#define ASIC_REG_DMA_IF_W_N_REGS_H_
+
+/*
+ *****************************************
+ * DMA_IF_W_N (Prototype: DMA_IF)
+ *****************************************
+ */
+
+#define mmDMA_IF_W_N_HBM0_WR_CRED_CNT 0x4C0000
+
+#define mmDMA_IF_W_N_HBM1_WR_CRED_CNT 0x4C0004
+
+#define mmDMA_IF_W_N_HBM0_RD_CRED_CNT 0x4C0008
+
+#define mmDMA_IF_W_N_HBM1_RD_CRED_CNT 0x4C000C
+
+#define mmDMA_IF_W_N_HBM_LIMITER_0 0x4C0030
+
+#define mmDMA_IF_W_N_HBM_LIMITER_1 0x4C0034
+
+#define mmDMA_IF_W_N_HBM_LIMITER_2 0x4C0038
+
+#define mmDMA_IF_W_N_HBM_LIMITER_3 0x4C003C
+
+#define mmDMA_IF_W_N_HBM_ALMOST_EN_0 0x4C0040
+
+#define mmDMA_IF_W_N_HBM_ALMOST_EN_1 0x4C0044
+
+#define mmDMA_IF_W_N_HBM_CRED_EN_0 0x4C0050
+
+#define mmDMA_IF_W_N_HBM_CRED_EN_1 0x4C0054
+
+#define mmDMA_IF_W_N_SOB_MIN_RPROT_0 0x4C0100
+
+#define mmDMA_IF_W_N_SOB_MIN_RPROT_1 0x4C0104
+
+#define mmDMA_IF_W_N_SOB_MIN_RPROT_2 0x4C0108
+
+#define mmDMA_IF_W_N_SOB_MIN_RPROT_3 0x4C010C
+
+#define mmDMA_IF_W_N_SOB_MIN_RPROT_4 0x4C0110
+
+#define mmDMA_IF_W_N_SOB_MIN_RPROT_5 0x4C0114
+
+#define mmDMA_IF_W_N_SOB_MIN_RPROT_6 0x4C0118
+
+#define mmDMA_IF_W_N_SOB_MIN_RPROT_7 0x4C011C
+
+#define mmDMA_IF_W_N_SOB_MIN_RPROT_8 0x4C0120
+
+#define mmDMA_IF_W_N_SOB_MIN_RPROT_9 0x4C0124
+
+#define mmDMA_IF_W_N_SOB_MIN_RPROT_10 0x4C0128
+
+#define mmDMA_IF_W_N_SOB_MIN_RPROT_11 0x4C012C
+
+#define mmDMA_IF_W_N_SOB_MIN_RPROT_12 0x4C0130
+
+#define mmDMA_IF_W_N_SOB_MIN_RPROT_13 0x4C0134
+
+#define mmDMA_IF_W_N_SOB_MIN_RPROT_14 0x4C0138
+
+#define mmDMA_IF_W_N_SOB_MIN_RPROT_15 0x4C013C
+
+#define mmDMA_IF_W_N_SOB_MAX_RPROT_0 0x4C0140
+
+#define mmDMA_IF_W_N_SOB_MAX_RPROT_1 0x4C0144
+
+#define mmDMA_IF_W_N_SOB_MAX_RPROT_2 0x4C0148
+
+#define mmDMA_IF_W_N_SOB_MAX_RPROT_3 0x4C014C
+
+#define mmDMA_IF_W_N_SOB_MAX_RPROT_4 0x4C0150
+
+#define mmDMA_IF_W_N_SOB_MAX_RPROT_5 0x4C0154
+
+#define mmDMA_IF_W_N_SOB_MAX_RPROT_6 0x4C0158
+
+#define mmDMA_IF_W_N_SOB_MAX_RPROT_7 0x4C015C
+
+#define mmDMA_IF_W_N_SOB_MAX_RPROT_8 0x4C0160
+
+#define mmDMA_IF_W_N_SOB_MAX_RPROT_9 0x4C0164
+
+#define mmDMA_IF_W_N_SOB_MAX_RPROT_10 0x4C0168
+
+#define mmDMA_IF_W_N_SOB_MAX_RPROT_11 0x4C016C
+
+#define mmDMA_IF_W_N_SOB_MAX_RPROT_12 0x4C0170
+
+#define mmDMA_IF_W_N_SOB_MAX_RPROT_13 0x4C0174
+
+#define mmDMA_IF_W_N_SOB_MAX_RPROT_14 0x4C0178
+
+#define mmDMA_IF_W_N_SOB_MAX_RPROT_15 0x4C017C
+
+#define mmDMA_IF_W_N_SOB_MIN_WPROT_0 0x4C0180
+
+#define mmDMA_IF_W_N_SOB_MIN_WPROT_1 0x4C0184
+
+#define mmDMA_IF_W_N_SOB_MIN_WPROT_2 0x4C0188
+
+#define mmDMA_IF_W_N_SOB_MIN_WPROT_3 0x4C018C
+
+#define mmDMA_IF_W_N_SOB_MIN_WPROT_4 0x4C0190
+
+#define mmDMA_IF_W_N_SOB_MIN_WPROT_5 0x4C0194
+
+#define mmDMA_IF_W_N_SOB_MIN_WPROT_6 0x4C0198
+
+#define mmDMA_IF_W_N_SOB_MIN_WPROT_7 0x4C019C
+
+#define mmDMA_IF_W_N_SOB_MIN_WPROT_8 0x4C01A0
+
+#define mmDMA_IF_W_N_SOB_MIN_WPROT_9 0x4C01A4
+
+#define mmDMA_IF_W_N_SOB_MIN_WPROT_10 0x4C01A8
+
+#define mmDMA_IF_W_N_SOB_MIN_WPROT_11 0x4C01AC
+
+#define mmDMA_IF_W_N_SOB_MIN_WPROT_12 0x4C01B0
+
+#define mmDMA_IF_W_N_SOB_MIN_WPROT_13 0x4C01B4
+
+#define mmDMA_IF_W_N_SOB_MIN_WPROT_14 0x4C01B8
+
+#define mmDMA_IF_W_N_SOB_MIN_WPROT_15 0x4C01BC
+
+#define mmDMA_IF_W_N_SOB_MAX_WPROT_0 0x4C01C0
+
+#define mmDMA_IF_W_N_SOB_MAX_WPROT_1 0x4C01C4
+
+#define mmDMA_IF_W_N_SOB_MAX_WPROT_2 0x4C01C8
+
+#define mmDMA_IF_W_N_SOB_MAX_WPROT_3 0x4C01CC
+
+#define mmDMA_IF_W_N_SOB_MAX_WPROT_4 0x4C01D0
+
+#define mmDMA_IF_W_N_SOB_MAX_WPROT_5 0x4C01D4
+
+#define mmDMA_IF_W_N_SOB_MAX_WPROT_6 0x4C01D8
+
+#define mmDMA_IF_W_N_SOB_MAX_WPROT_7 0x4C01DC
+
+#define mmDMA_IF_W_N_SOB_MAX_WPROT_8 0x4C01E0
+
+#define mmDMA_IF_W_N_SOB_MAX_WPROT_9 0x4C01E4
+
+#define mmDMA_IF_W_N_SOB_MAX_WPROT_10 0x4C01E8
+
+#define mmDMA_IF_W_N_SOB_MAX_WPROT_11 0x4C01EC
+
+#define mmDMA_IF_W_N_SOB_MAX_WPROT_12 0x4C01F0
+
+#define mmDMA_IF_W_N_SOB_MAX_WPROT_13 0x4C01F4
+
+#define mmDMA_IF_W_N_SOB_MAX_WPROT_14 0x4C01F8
+
+#define mmDMA_IF_W_N_SOB_MAX_WPROT_15 0x4C01FC
+
+#define mmDMA_IF_W_N_SOB_MIN_RPRIV_0 0x4C0200
+
+#define mmDMA_IF_W_N_SOB_MIN_RPRIV_1 0x4C0204
+
+#define mmDMA_IF_W_N_SOB_MIN_RPRIV_2 0x4C0208
+
+#define mmDMA_IF_W_N_SOB_MIN_RPRIV_3 0x4C020C
+
+#define mmDMA_IF_W_N_SOB_MIN_RPRIV_4 0x4C0210
+
+#define mmDMA_IF_W_N_SOB_MIN_RPRIV_5 0x4C0214
+
+#define mmDMA_IF_W_N_SOB_MIN_RPRIV_6 0x4C0218
+
+#define mmDMA_IF_W_N_SOB_MIN_RPRIV_7 0x4C021C
+
+#define mmDMA_IF_W_N_SOB_MIN_RPRIV_8 0x4C0220
+
+#define mmDMA_IF_W_N_SOB_MIN_RPRIV_9 0x4C0224
+
+#define mmDMA_IF_W_N_SOB_MIN_RPRIV_10 0x4C0228
+
+#define mmDMA_IF_W_N_SOB_MIN_RPRIV_11 0x4C022C
+
+#define mmDMA_IF_W_N_SOB_MIN_RPRIV_12 0x4C0230
+
+#define mmDMA_IF_W_N_SOB_MIN_RPRIV_13 0x4C0234
+
+#define mmDMA_IF_W_N_SOB_MIN_RPRIV_14 0x4C0238
+
+#define mmDMA_IF_W_N_SOB_MIN_RPRIV_15 0x4C023C
+
+#define mmDMA_IF_W_N_SOB_MAX_RPRIV_0 0x4C0240
+
+#define mmDMA_IF_W_N_SOB_MAX_RPRIV_1 0x4C0244
+
+#define mmDMA_IF_W_N_SOB_MAX_RPRIV_2 0x4C0248
+
+#define mmDMA_IF_W_N_SOB_MAX_RPRIV_3 0x4C024C
+
+#define mmDMA_IF_W_N_SOB_MAX_RPRIV_4 0x4C0250
+
+#define mmDMA_IF_W_N_SOB_MAX_RPRIV_5 0x4C0254
+
+#define mmDMA_IF_W_N_SOB_MAX_RPRIV_6 0x4C0258
+
+#define mmDMA_IF_W_N_SOB_MAX_RPRIV_7 0x4C025C
+
+#define mmDMA_IF_W_N_SOB_MAX_RPRIV_8 0x4C0260
+
+#define mmDMA_IF_W_N_SOB_MAX_RPRIV_9 0x4C0264
+
+#define mmDMA_IF_W_N_SOB_MAX_RPRIV_10 0x4C0268
+
+#define mmDMA_IF_W_N_SOB_MAX_RPRIV_11 0x4C026C
+
+#define mmDMA_IF_W_N_SOB_MAX_RPRIV_12 0x4C0270
+
+#define mmDMA_IF_W_N_SOB_MAX_RPRIV_13 0x4C0274
+
+#define mmDMA_IF_W_N_SOB_MAX_RPRIV_14 0x4C0278
+
+#define mmDMA_IF_W_N_SOB_MAX_RPRIV_15 0x4C027C
+
+#define mmDMA_IF_W_N_SOB_MIN_WPRIV_0 0x4C0280
+
+#define mmDMA_IF_W_N_SOB_MIN_WPRIV_1 0x4C0284
+
+#define mmDMA_IF_W_N_SOB_MIN_WPRIV_2 0x4C0288
+
+#define mmDMA_IF_W_N_SOB_MIN_WPRIV_3 0x4C028C
+
+#define mmDMA_IF_W_N_SOB_MIN_WPRIV_4 0x4C0290
+
+#define mmDMA_IF_W_N_SOB_MIN_WPRIV_5 0x4C0294
+
+#define mmDMA_IF_W_N_SOB_MIN_WPRIV_6 0x4C0298
+
+#define mmDMA_IF_W_N_SOB_MIN_WPRIV_7 0x4C029C
+
+#define mmDMA_IF_W_N_SOB_MIN_WPRIV_8 0x4C02A0
+
+#define mmDMA_IF_W_N_SOB_MIN_WPRIV_9 0x4C02A4
+
+#define mmDMA_IF_W_N_SOB_MIN_WPRIV_10 0x4C02A8
+
+#define mmDMA_IF_W_N_SOB_MIN_WPRIV_11 0x4C02AC
+
+#define mmDMA_IF_W_N_SOB_MIN_WPRIV_12 0x4C02B0
+
+#define mmDMA_IF_W_N_SOB_MIN_WPRIV_13 0x4C02B4
+
+#define mmDMA_IF_W_N_SOB_MIN_WPRIV_14 0x4C02B8
+
+#define mmDMA_IF_W_N_SOB_MIN_WPRIV_15 0x4C02BC
+
+#define mmDMA_IF_W_N_SOB_MAX_WPRIV_0 0x4C02C0
+
+#define mmDMA_IF_W_N_SOB_MAX_WPRIV_1 0x4C02C4
+
+#define mmDMA_IF_W_N_SOB_MAX_WPRIV_2 0x4C02C8
+
+#define mmDMA_IF_W_N_SOB_MAX_WPRIV_3 0x4C02CC
+
+#define mmDMA_IF_W_N_SOB_MAX_WPRIV_4 0x4C02D0
+
+#define mmDMA_IF_W_N_SOB_MAX_WPRIV_5 0x4C02D4
+
+#define mmDMA_IF_W_N_SOB_MAX_WPRIV_6 0x4C02D8
+
+#define mmDMA_IF_W_N_SOB_MAX_WPRIV_7 0x4C02DC
+
+#define mmDMA_IF_W_N_SOB_MAX_WPRIV_8 0x4C02E0
+
+#define mmDMA_IF_W_N_SOB_MAX_WPRIV_9 0x4C02E4
+
+#define mmDMA_IF_W_N_SOB_MAX_WPRIV_10 0x4C02E8
+
+#define mmDMA_IF_W_N_SOB_MAX_WPRIV_11 0x4C02EC
+
+#define mmDMA_IF_W_N_SOB_MAX_WPRIV_12 0x4C02F0
+
+#define mmDMA_IF_W_N_SOB_MAX_WPRIV_13 0x4C02F4
+
+#define mmDMA_IF_W_N_SOB_MAX_WPRIV_14 0x4C02F8
+
+#define mmDMA_IF_W_N_SOB_MAX_WPRIV_15 0x4C02FC
+
+#define mmDMA_IF_W_N_DMA0_MIN_RPROT_0 0x4C0300
+
+#define mmDMA_IF_W_N_DMA0_MIN_RPROT_1 0x4C0304
+
+#define mmDMA_IF_W_N_DMA0_MIN_RPROT_2 0x4C0308
+
+#define mmDMA_IF_W_N_DMA0_MIN_RPROT_3 0x4C030C
+
+#define mmDMA_IF_W_N_DMA0_MIN_RPROT_4 0x4C0310
+
+#define mmDMA_IF_W_N_DMA0_MIN_RPROT_5 0x4C0314
+
+#define mmDMA_IF_W_N_DMA0_MIN_RPROT_6 0x4C0318
+
+#define mmDMA_IF_W_N_DMA0_MIN_RPROT_7 0x4C031C
+
+#define mmDMA_IF_W_N_DMA0_MIN_RPROT_8 0x4C0320
+
+#define mmDMA_IF_W_N_DMA0_MIN_RPROT_9 0x4C0324
+
+#define mmDMA_IF_W_N_DMA0_MIN_RPROT_10 0x4C0328
+
+#define mmDMA_IF_W_N_DMA0_MIN_RPROT_11 0x4C032C
+
+#define mmDMA_IF_W_N_DMA0_MIN_RPROT_12 0x4C0330
+
+#define mmDMA_IF_W_N_DMA0_MIN_RPROT_13 0x4C0334
+
+#define mmDMA_IF_W_N_DMA0_MIN_RPROT_14 0x4C0338
+
+#define mmDMA_IF_W_N_DMA0_MIN_RPROT_15 0x4C033C
+
+#define mmDMA_IF_W_N_DMA0_MAX_RPROT_0 0x4C0340
+
+#define mmDMA_IF_W_N_DMA0_MAX_RPROT_1 0x4C0344
+
+#define mmDMA_IF_W_N_DMA0_MAX_RPROT_2 0x4C0348
+
+#define mmDMA_IF_W_N_DMA0_MAX_RPROT_3 0x4C034C
+
+#define mmDMA_IF_W_N_DMA0_MAX_RPROT_4 0x4C0350
+
+#define mmDMA_IF_W_N_DMA0_MAX_RPROT_5 0x4C0354
+
+#define mmDMA_IF_W_N_DMA0_MAX_RPROT_6 0x4C0358
+
+#define mmDMA_IF_W_N_DMA0_MAX_RPROT_7 0x4C035C
+
+#define mmDMA_IF_W_N_DMA0_MAX_RPROT_8 0x4C0360
+
+#define mmDMA_IF_W_N_DMA0_MAX_RPROT_9 0x4C0364
+
+#define mmDMA_IF_W_N_DMA0_MAX_RPROT_10 0x4C0368
+
+#define mmDMA_IF_W_N_DMA0_MAX_RPROT_11 0x4C036C
+
+#define mmDMA_IF_W_N_DMA0_MAX_RPROT_12 0x4C0370
+
+#define mmDMA_IF_W_N_DMA0_MAX_RPROT_13 0x4C0374
+
+#define mmDMA_IF_W_N_DMA0_MAX_RPROT_14 0x4C0378
+
+#define mmDMA_IF_W_N_DMA0_MAX_RPROT_15 0x4C037C
+
+#define mmDMA_IF_W_N_DMA0_MIN_WPROT_0 0x4C0380
+
+#define mmDMA_IF_W_N_DMA0_MIN_WPROT_1 0x4C0384
+
+#define mmDMA_IF_W_N_DMA0_MIN_WPROT_2 0x4C0388
+
+#define mmDMA_IF_W_N_DMA0_MIN_WPROT_3 0x4C038C
+
+#define mmDMA_IF_W_N_DMA0_MIN_WPROT_4 0x4C0390
+
+#define mmDMA_IF_W_N_DMA0_MIN_WPROT_5 0x4C0394
+
+#define mmDMA_IF_W_N_DMA0_MIN_WPROT_6 0x4C0398
+
+#define mmDMA_IF_W_N_DMA0_MIN_WPROT_7 0x4C039C
+
+#define mmDMA_IF_W_N_DMA0_MIN_WPROT_8 0x4C03A0
+
+#define mmDMA_IF_W_N_DMA0_MIN_WPROT_9 0x4C03A4
+
+#define mmDMA_IF_W_N_DMA0_MIN_WPROT_10 0x4C03A8
+
+#define mmDMA_IF_W_N_DMA0_MIN_WPROT_11 0x4C03AC
+
+#define mmDMA_IF_W_N_DMA0_MIN_WPROT_12 0x4C03B0
+
+#define mmDMA_IF_W_N_DMA0_MIN_WPROT_13 0x4C03B4
+
+#define mmDMA_IF_W_N_DMA0_MIN_WPROT_14 0x4C03B8
+
+#define mmDMA_IF_W_N_DMA0_MIN_WPROT_15 0x4C03BC
+
+#define mmDMA_IF_W_N_DMA0_MAX_WPROT_0 0x4C03C0
+
+#define mmDMA_IF_W_N_DMA0_MAX_WPROT_1 0x4C03C4
+
+#define mmDMA_IF_W_N_DMA0_MAX_WPROT_2 0x4C03C8
+
+#define mmDMA_IF_W_N_DMA0_MAX_WPROT_3 0x4C03CC
+
+#define mmDMA_IF_W_N_DMA0_MAX_WPROT_4 0x4C03D0
+
+#define mmDMA_IF_W_N_DMA0_MAX_WPROT_5 0x4C03D4
+
+#define mmDMA_IF_W_N_DMA0_MAX_WPROT_6 0x4C03D8
+
+#define mmDMA_IF_W_N_DMA0_MAX_WPROT_7 0x4C03DC
+
+#define mmDMA_IF_W_N_DMA0_MAX_WPROT_8 0x4C03E0
+
+#define mmDMA_IF_W_N_DMA0_MAX_WPROT_9 0x4C03E4
+
+#define mmDMA_IF_W_N_DMA0_MAX_WPROT_10 0x4C03E8
+
+#define mmDMA_IF_W_N_DMA0_MAX_WPROT_11 0x4C03EC
+
+#define mmDMA_IF_W_N_DMA0_MAX_WPROT_12 0x4C03F0
+
+#define mmDMA_IF_W_N_DMA0_MAX_WPROT_13 0x4C03F4
+
+#define mmDMA_IF_W_N_DMA0_MAX_WPROT_14 0x4C03F8
+
+#define mmDMA_IF_W_N_DMA0_MAX_WPROT_15 0x4C03FC
+
+#define mmDMA_IF_W_N_DMA0_MIN_RPRIV_0 0x4C0400
+
+#define mmDMA_IF_W_N_DMA0_MIN_RPRIV_1 0x4C0404
+
+#define mmDMA_IF_W_N_DMA0_MIN_RPRIV_2 0x4C0408
+
+#define mmDMA_IF_W_N_DMA0_MIN_RPRIV_3 0x4C040C
+
+#define mmDMA_IF_W_N_DMA0_MIN_RPRIV_4 0x4C0410
+
+#define mmDMA_IF_W_N_DMA0_MIN_RPRIV_5 0x4C0414
+
+#define mmDMA_IF_W_N_DMA0_MIN_RPRIV_6 0x4C0418
+
+#define mmDMA_IF_W_N_DMA0_MIN_RPRIV_7 0x4C041C
+
+#define mmDMA_IF_W_N_DMA0_MIN_RPRIV_8 0x4C0420
+
+#define mmDMA_IF_W_N_DMA0_MIN_RPRIV_9 0x4C0424
+
+#define mmDMA_IF_W_N_DMA0_MIN_RPRIV_10 0x4C0428
+
+#define mmDMA_IF_W_N_DMA0_MIN_RPRIV_11 0x4C042C
+
+#define mmDMA_IF_W_N_DMA0_MIN_RPRIV_12 0x4C0430
+
+#define mmDMA_IF_W_N_DMA0_MIN_RPRIV_13 0x4C0434
+
+#define mmDMA_IF_W_N_DMA0_MIN_RPRIV_14 0x4C0438
+
+#define mmDMA_IF_W_N_DMA0_MIN_RPRIV_15 0x4C043C
+
+#define mmDMA_IF_W_N_DMA0_MAX_RPRIV_0 0x4C0440
+
+#define mmDMA_IF_W_N_DMA0_MAX_RPRIV_1 0x4C0444
+
+#define mmDMA_IF_W_N_DMA0_MAX_RPRIV_2 0x4C0448
+
+#define mmDMA_IF_W_N_DMA0_MAX_RPRIV_3 0x4C044C
+
+#define mmDMA_IF_W_N_DMA0_MAX_RPRIV_4 0x4C0450
+
+#define mmDMA_IF_W_N_DMA0_MAX_RPRIV_5 0x4C0454
+
+#define mmDMA_IF_W_N_DMA0_MAX_RPRIV_6 0x4C0458
+
+#define mmDMA_IF_W_N_DMA0_MAX_RPRIV_7 0x4C045C
+
+#define mmDMA_IF_W_N_DMA0_MAX_RPRIV_8 0x4C0460
+
+#define mmDMA_IF_W_N_DMA0_MAX_RPRIV_9 0x4C0464
+
+#define mmDMA_IF_W_N_DMA0_MAX_RPRIV_10 0x4C0468
+
+#define mmDMA_IF_W_N_DMA0_MAX_RPRIV_11 0x4C046C
+
+#define mmDMA_IF_W_N_DMA0_MAX_RPRIV_12 0x4C0470
+
+#define mmDMA_IF_W_N_DMA0_MAX_RPRIV_13 0x4C0474
+
+#define mmDMA_IF_W_N_DMA0_MAX_RPRIV_14 0x4C0478
+
+#define mmDMA_IF_W_N_DMA0_MAX_RPRIV_15 0x4C047C
+
+#define mmDMA_IF_W_N_DMA0_MIN_WPRIV_0 0x4C0480
+
+#define mmDMA_IF_W_N_DMA0_MIN_WPRIV_1 0x4C0484
+
+#define mmDMA_IF_W_N_DMA0_MIN_WPRIV_2 0x4C0488
+
+#define mmDMA_IF_W_N_DMA0_MIN_WPRIV_3 0x4C048C
+
+#define mmDMA_IF_W_N_DMA0_MIN_WPRIV_4 0x4C0490
+
+#define mmDMA_IF_W_N_DMA0_MIN_WPRIV_5 0x4C0494
+
+#define mmDMA_IF_W_N_DMA0_MIN_WPRIV_6 0x4C0498
+
+#define mmDMA_IF_W_N_DMA0_MIN_WPRIV_7 0x4C049C
+
+#define mmDMA_IF_W_N_DMA0_MIN_WPRIV_8 0x4C04A0
+
+#define mmDMA_IF_W_N_DMA0_MIN_WPRIV_9 0x4C04A4
+
+#define mmDMA_IF_W_N_DMA0_MIN_WPRIV_10 0x4C04A8
+
+#define mmDMA_IF_W_N_DMA0_MIN_WPRIV_11 0x4C04AC
+
+#define mmDMA_IF_W_N_DMA0_MIN_WPRIV_12 0x4C04B0
+
+#define mmDMA_IF_W_N_DMA0_MIN_WPRIV_13 0x4C04B4
+
+#define mmDMA_IF_W_N_DMA0_MIN_WPRIV_14 0x4C04B8
+
+#define mmDMA_IF_W_N_DMA0_MIN_WPRIV_15 0x4C04BC
+
+#define mmDMA_IF_W_N_DMA0_MAX_WPRIV_0 0x4C04C0
+
+#define mmDMA_IF_W_N_DMA0_MAX_WPRIV_1 0x4C04C4
+
+#define mmDMA_IF_W_N_DMA0_MAX_WPRIV_2 0x4C04C8
+
+#define mmDMA_IF_W_N_DMA0_MAX_WPRIV_3 0x4C04CC
+
+#define mmDMA_IF_W_N_DMA0_MAX_WPRIV_4 0x4C04D0
+
+#define mmDMA_IF_W_N_DMA0_MAX_WPRIV_5 0x4C04D4
+
+#define mmDMA_IF_W_N_DMA0_MAX_WPRIV_6 0x4C04D8
+
+#define mmDMA_IF_W_N_DMA0_MAX_WPRIV_7 0x4C04DC
+
+#define mmDMA_IF_W_N_DMA0_MAX_WPRIV_8 0x4C04E0
+
+#define mmDMA_IF_W_N_DMA0_MAX_WPRIV_9 0x4C04E4
+
+#define mmDMA_IF_W_N_DMA0_MAX_WPRIV_10 0x4C04E8
+
+#define mmDMA_IF_W_N_DMA0_MAX_WPRIV_11 0x4C04EC
+
+#define mmDMA_IF_W_N_DMA0_MAX_WPRIV_12 0x4C04F0
+
+#define mmDMA_IF_W_N_DMA0_MAX_WPRIV_13 0x4C04F4
+
+#define mmDMA_IF_W_N_DMA0_MAX_WPRIV_14 0x4C04F8
+
+#define mmDMA_IF_W_N_DMA0_MAX_WPRIV_15 0x4C04FC
+
+#define mmDMA_IF_W_N_DMA1_MIN_RPROT_0 0x4C0500
+
+#define mmDMA_IF_W_N_DMA1_MIN_RPROT_1 0x4C0504
+
+#define mmDMA_IF_W_N_DMA1_MIN_RPROT_2 0x4C0508
+
+#define mmDMA_IF_W_N_DMA1_MIN_RPROT_3 0x4C050C
+
+#define mmDMA_IF_W_N_DMA1_MIN_RPROT_4 0x4C0510
+
+#define mmDMA_IF_W_N_DMA1_MIN_RPROT_5 0x4C0514
+
+#define mmDMA_IF_W_N_DMA1_MIN_RPROT_6 0x4C0518
+
+#define mmDMA_IF_W_N_DMA1_MIN_RPROT_7 0x4C051C
+
+#define mmDMA_IF_W_N_DMA1_MIN_RPROT_8 0x4C0520
+
+#define mmDMA_IF_W_N_DMA1_MIN_RPROT_9 0x4C0524
+
+#define mmDMA_IF_W_N_DMA1_MIN_RPROT_10 0x4C0528
+
+#define mmDMA_IF_W_N_DMA1_MIN_RPROT_11 0x4C052C
+
+#define mmDMA_IF_W_N_DMA1_MIN_RPROT_12 0x4C0530
+
+#define mmDMA_IF_W_N_DMA1_MIN_RPROT_13 0x4C0534
+
+#define mmDMA_IF_W_N_DMA1_MIN_RPROT_14 0x4C0538
+
+#define mmDMA_IF_W_N_DMA1_MIN_RPROT_15 0x4C053C
+
+#define mmDMA_IF_W_N_DMA1_MAX_RPROT_0 0x4C0540
+
+#define mmDMA_IF_W_N_DMA1_MAX_RPROT_1 0x4C0544
+
+#define mmDMA_IF_W_N_DMA1_MAX_RPROT_2 0x4C0548
+
+#define mmDMA_IF_W_N_DMA1_MAX_RPROT_3 0x4C054C
+
+#define mmDMA_IF_W_N_DMA1_MAX_RPROT_4 0x4C0550
+
+#define mmDMA_IF_W_N_DMA1_MAX_RPROT_5 0x4C0554
+
+#define mmDMA_IF_W_N_DMA1_MAX_RPROT_6 0x4C0558
+
+#define mmDMA_IF_W_N_DMA1_MAX_RPROT_7 0x4C055C
+
+#define mmDMA_IF_W_N_DMA1_MAX_RPROT_8 0x4C0560
+
+#define mmDMA_IF_W_N_DMA1_MAX_RPROT_9 0x4C0564
+
+#define mmDMA_IF_W_N_DMA1_MAX_RPROT_10 0x4C0568
+
+#define mmDMA_IF_W_N_DMA1_MAX_RPROT_11 0x4C056C
+
+#define mmDMA_IF_W_N_DMA1_MAX_RPROT_12 0x4C0570
+
+#define mmDMA_IF_W_N_DMA1_MAX_RPROT_13 0x4C0574
+
+#define mmDMA_IF_W_N_DMA1_MAX_RPROT_14 0x4C0578
+
+#define mmDMA_IF_W_N_DMA1_MAX_RPROT_15 0x4C057C
+
+#define mmDMA_IF_W_N_DMA1_MIN_WPROT_0 0x4C0580
+
+#define mmDMA_IF_W_N_DMA1_MIN_WPROT_1 0x4C0584
+
+#define mmDMA_IF_W_N_DMA1_MIN_WPROT_2 0x4C0588
+
+#define mmDMA_IF_W_N_DMA1_MIN_WPROT_3 0x4C058C
+
+#define mmDMA_IF_W_N_DMA1_MIN_WPROT_4 0x4C0590
+
+#define mmDMA_IF_W_N_DMA1_MIN_WPROT_5 0x4C0594
+
+#define mmDMA_IF_W_N_DMA1_MIN_WPROT_6 0x4C0598
+
+#define mmDMA_IF_W_N_DMA1_MIN_WPROT_7 0x4C059C
+
+#define mmDMA_IF_W_N_DMA1_MIN_WPROT_8 0x4C05A0
+
+#define mmDMA_IF_W_N_DMA1_MIN_WPROT_9 0x4C05A4
+
+#define mmDMA_IF_W_N_DMA1_MIN_WPROT_10 0x4C05A8
+
+#define mmDMA_IF_W_N_DMA1_MIN_WPROT_11 0x4C05AC
+
+#define mmDMA_IF_W_N_DMA1_MIN_WPROT_12 0x4C05B0
+
+#define mmDMA_IF_W_N_DMA1_MIN_WPROT_13 0x4C05B4
+
+#define mmDMA_IF_W_N_DMA1_MIN_WPROT_14 0x4C05B8
+
+#define mmDMA_IF_W_N_DMA1_MIN_WPROT_15 0x4C05BC
+
+#define mmDMA_IF_W_N_DMA1_MAX_WPROT_0 0x4C05C0
+
+#define mmDMA_IF_W_N_DMA1_MAX_WPROT_1 0x4C05C4
+
+#define mmDMA_IF_W_N_DMA1_MAX_WPROT_2 0x4C05C8
+
+#define mmDMA_IF_W_N_DMA1_MAX_WPROT_3 0x4C05CC
+
+#define mmDMA_IF_W_N_DMA1_MAX_WPROT_4 0x4C05D0
+
+#define mmDMA_IF_W_N_DMA1_MAX_WPROT_5 0x4C05D4
+
+#define mmDMA_IF_W_N_DMA1_MAX_WPROT_6 0x4C05D8
+
+#define mmDMA_IF_W_N_DMA1_MAX_WPROT_7 0x4C05DC
+
+#define mmDMA_IF_W_N_DMA1_MAX_WPROT_8 0x4C05E0
+
+#define mmDMA_IF_W_N_DMA1_MAX_WPROT_9 0x4C05E4
+
+#define mmDMA_IF_W_N_DMA1_MAX_WPROT_10 0x4C05E8
+
+#define mmDMA_IF_W_N_DMA1_MAX_WPROT_11 0x4C05EC
+
+#define mmDMA_IF_W_N_DMA1_MAX_WPROT_12 0x4C05F0
+
+#define mmDMA_IF_W_N_DMA1_MAX_WPROT_13 0x4C05F4
+
+#define mmDMA_IF_W_N_DMA1_MAX_WPROT_14 0x4C05F8
+
+#define mmDMA_IF_W_N_DMA1_MAX_WPROT_15 0x4C05FC
+
+#define mmDMA_IF_W_N_DMA1_MIN_RPRIV_0 0x4C0600
+
+#define mmDMA_IF_W_N_DMA1_MIN_RPRIV_1 0x4C0604
+
+#define mmDMA_IF_W_N_DMA1_MIN_RPRIV_2 0x4C0608
+
+#define mmDMA_IF_W_N_DMA1_MIN_RPRIV_3 0x4C060C
+
+#define mmDMA_IF_W_N_DMA1_MIN_RPRIV_4 0x4C0610
+
+#define mmDMA_IF_W_N_DMA1_MIN_RPRIV_5 0x4C0614
+
+#define mmDMA_IF_W_N_DMA1_MIN_RPRIV_6 0x4C0618
+
+#define mmDMA_IF_W_N_DMA1_MIN_RPRIV_7 0x4C061C
+
+#define mmDMA_IF_W_N_DMA1_MIN_RPRIV_8 0x4C0620
+
+#define mmDMA_IF_W_N_DMA1_MIN_RPRIV_9 0x4C0624
+
+#define mmDMA_IF_W_N_DMA1_MIN_RPRIV_10 0x4C0628
+
+#define mmDMA_IF_W_N_DMA1_MIN_RPRIV_11 0x4C062C
+
+#define mmDMA_IF_W_N_DMA1_MIN_RPRIV_12 0x4C0630
+
+#define mmDMA_IF_W_N_DMA1_MIN_RPRIV_13 0x4C0634
+
+#define mmDMA_IF_W_N_DMA1_MIN_RPRIV_14 0x4C0638
+
+#define mmDMA_IF_W_N_DMA1_MIN_RPRIV_15 0x4C063C
+
+#define mmDMA_IF_W_N_DMA1_MAX_RPRIV_0 0x4C0640
+
+#define mmDMA_IF_W_N_DMA1_MAX_RPRIV_1 0x4C0644
+
+#define mmDMA_IF_W_N_DMA1_MAX_RPRIV_2 0x4C0648
+
+#define mmDMA_IF_W_N_DMA1_MAX_RPRIV_3 0x4C064C
+
+#define mmDMA_IF_W_N_DMA1_MAX_RPRIV_4 0x4C0650
+
+#define mmDMA_IF_W_N_DMA1_MAX_RPRIV_5 0x4C0654
+
+#define mmDMA_IF_W_N_DMA1_MAX_RPRIV_6 0x4C0658
+
+#define mmDMA_IF_W_N_DMA1_MAX_RPRIV_7 0x4C065C
+
+#define mmDMA_IF_W_N_DMA1_MAX_RPRIV_8 0x4C0660
+
+#define mmDMA_IF_W_N_DMA1_MAX_RPRIV_9 0x4C0664
+
+#define mmDMA_IF_W_N_DMA1_MAX_RPRIV_10 0x4C0668
+
+#define mmDMA_IF_W_N_DMA1_MAX_RPRIV_11 0x4C066C
+
+#define mmDMA_IF_W_N_DMA1_MAX_RPRIV_12 0x4C0670
+
+#define mmDMA_IF_W_N_DMA1_MAX_RPRIV_13 0x4C0674
+
+#define mmDMA_IF_W_N_DMA1_MAX_RPRIV_14 0x4C0678
+
+#define mmDMA_IF_W_N_DMA1_MAX_RPRIV_15 0x4C067C
+
+#define mmDMA_IF_W_N_DMA1_MIN_WPRIV_0 0x4C0680
+
+#define mmDMA_IF_W_N_DMA1_MIN_WPRIV_1 0x4C0684
+
+#define mmDMA_IF_W_N_DMA1_MIN_WPRIV_2 0x4C0688
+
+#define mmDMA_IF_W_N_DMA1_MIN_WPRIV_3 0x4C068C
+
+#define mmDMA_IF_W_N_DMA1_MIN_WPRIV_4 0x4C0690
+
+#define mmDMA_IF_W_N_DMA1_MIN_WPRIV_5 0x4C0694
+
+#define mmDMA_IF_W_N_DMA1_MIN_WPRIV_6 0x4C0698
+
+#define mmDMA_IF_W_N_DMA1_MIN_WPRIV_7 0x4C069C
+
+#define mmDMA_IF_W_N_DMA1_MIN_WPRIV_8 0x4C06A0
+
+#define mmDMA_IF_W_N_DMA1_MIN_WPRIV_9 0x4C06A4
+
+#define mmDMA_IF_W_N_DMA1_MIN_WPRIV_10 0x4C06A8
+
+#define mmDMA_IF_W_N_DMA1_MIN_WPRIV_11 0x4C06AC
+
+#define mmDMA_IF_W_N_DMA1_MIN_WPRIV_12 0x4C06B0
+
+#define mmDMA_IF_W_N_DMA1_MIN_WPRIV_13 0x4C06B4
+
+#define mmDMA_IF_W_N_DMA1_MIN_WPRIV_14 0x4C06B8
+
+#define mmDMA_IF_W_N_DMA1_MIN_WPRIV_15 0x4C06BC
+
+#define mmDMA_IF_W_N_DMA1_MAX_WPRIV_0 0x4C06C0
+
+#define mmDMA_IF_W_N_DMA1_MAX_WPRIV_1 0x4C06C4
+
+#define mmDMA_IF_W_N_DMA1_MAX_WPRIV_2 0x4C06C8
+
+#define mmDMA_IF_W_N_DMA1_MAX_WPRIV_3 0x4C06CC
+
+#define mmDMA_IF_W_N_DMA1_MAX_WPRIV_4 0x4C06D0
+
+#define mmDMA_IF_W_N_DMA1_MAX_WPRIV_5 0x4C06D4
+
+#define mmDMA_IF_W_N_DMA1_MAX_WPRIV_6 0x4C06D8
+
+#define mmDMA_IF_W_N_DMA1_MAX_WPRIV_7 0x4C06DC
+
+#define mmDMA_IF_W_N_DMA1_MAX_WPRIV_8 0x4C06E0
+
+#define mmDMA_IF_W_N_DMA1_MAX_WPRIV_9 0x4C06E4
+
+#define mmDMA_IF_W_N_DMA1_MAX_WPRIV_10 0x4C06E8
+
+#define mmDMA_IF_W_N_DMA1_MAX_WPRIV_11 0x4C06EC
+
+#define mmDMA_IF_W_N_DMA1_MAX_WPRIV_12 0x4C06F0
+
+#define mmDMA_IF_W_N_DMA1_MAX_WPRIV_13 0x4C06F4
+
+#define mmDMA_IF_W_N_DMA1_MAX_WPRIV_14 0x4C06F8
+
+#define mmDMA_IF_W_N_DMA1_MAX_WPRIV_15 0x4C06FC
+
+#define mmDMA_IF_W_N_SOB_HIT_RPROT 0x4C0700
+
+#define mmDMA_IF_W_N_SOB_HIT_WPROT 0x4C0704
+
+#define mmDMA_IF_W_N_SOB_HIT_RPRIV 0x4C070C
+
+#define mmDMA_IF_W_N_SOB_HIT_WPRIV 0x4C0710
+
+#define mmDMA_IF_W_N_DMA0_HIT_RPROT 0x4C071C
+
+#define mmDMA_IF_W_N_DMA0_HIT_WPROT 0x4C0720
+
+#define mmDMA_IF_W_N_DMA0_HIT_RPRIV 0x4C0724
+
+#define mmDMA_IF_W_N_DMA0_HIT_WPRIV 0x4C0728
+
+#define mmDMA_IF_W_N_DMA1_HIT_RPROT 0x4C0730
+
+#define mmDMA_IF_W_N_DMA1_HIT_WPROT 0x4C0734
+
+#define mmDMA_IF_W_N_DMA1_HIT_RPRIV 0x4C0738
+
+#define mmDMA_IF_W_N_DMA1_HIT_WPRIV 0x4C073C
+
+#define mmDMA_IF_W_N_HBM_BIN 0x4C0800
+
+#define mmDMA_IF_W_N_MME_BIN 0x4C0804
+
+#define mmDMA_IF_W_N_TPC_BIN 0x4C0808
+
+#define mmDMA_IF_W_N_DMA_BIN 0x4C080C
+
+#define mmDMA_IF_W_N_SOB_CG_EN 0x4C0810
+
+#define mmDMA_IF_W_N_HBM_I2C_ADDR_0 0x4C0820
+
+#define mmDMA_IF_W_N_HBM_I2C_ADDR_1 0x4C0824
+
+#define mmDMA_IF_W_N_HBM_I2C_ADDR_2 0x4C0828
+
+#define mmDMA_IF_W_N_HBM_I2C_ADDR_3 0x4C082C
+
+#define mmDMA_IF_W_N_HBM_I2C_ADDR_4 0x4C0830
+
+#define mmDMA_IF_W_N_HBM_MISC 0x4C0834
+
+#endif /* ASIC_REG_DMA_IF_W_N_REGS_H_ */
diff --git a/drivers/accel/habanalabs/include/gaudi/asic_reg/dma_if_w_s_down_ch0_regs.h b/drivers/accel/habanalabs/include/gaudi/asic_reg/dma_if_w_s_down_ch0_regs.h
new file mode 100644
index 0000000000..56ffc920d5
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi/asic_reg/dma_if_w_s_down_ch0_regs.h
@@ -0,0 +1,896 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2016-2018 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ ** DO NOT EDIT BELOW **
+ ************************************/
+
+#ifndef ASIC_REG_DMA_IF_W_S_DOWN_CH0_REGS_H_
+#define ASIC_REG_DMA_IF_W_S_DOWN_CH0_REGS_H_
+
+/*
+ *****************************************
+ * DMA_IF_W_S_DOWN_CH0 (Prototype: RTR_CTRL)
+ *****************************************
+ */
+
+#define mmDMA_IF_W_S_DOWN_CH0_PERM_SEL 0x481108
+
+#define mmDMA_IF_W_S_DOWN_CH0_HBM_POLY_H3_0 0x481114
+
+#define mmDMA_IF_W_S_DOWN_CH0_HBM_POLY_H3_1 0x481118
+
+#define mmDMA_IF_W_S_DOWN_CH0_HBM_POLY_H3_2 0x48111C
+
+#define mmDMA_IF_W_S_DOWN_CH0_HBM_POLY_H3_3 0x481120
+
+#define mmDMA_IF_W_S_DOWN_CH0_HBM_POLY_H3_4 0x481124
+
+#define mmDMA_IF_W_S_DOWN_CH0_HBM_POLY_H3_5 0x481128
+
+#define mmDMA_IF_W_S_DOWN_CH0_HBM_POLY_H3_6 0x48112C
+
+#define mmDMA_IF_W_S_DOWN_CH0_HBM_POLY_H3_7 0x481130
+
+#define mmDMA_IF_W_S_DOWN_CH0_HBM_POLY_H3_8 0x481134
+
+#define mmDMA_IF_W_S_DOWN_CH0_HBM_POLY_H3_9 0x481138
+
+#define mmDMA_IF_W_S_DOWN_CH0_HBM_POLY_H3_10 0x48113C
+
+#define mmDMA_IF_W_S_DOWN_CH0_HBM_POLY_H3_11 0x481140
+
+#define mmDMA_IF_W_S_DOWN_CH0_HBM_POLY_H3_12 0x481144
+
+#define mmDMA_IF_W_S_DOWN_CH0_HBM_POLY_H3_13 0x481148
+
+#define mmDMA_IF_W_S_DOWN_CH0_HBM_POLY_H3_14 0x48114C
+
+#define mmDMA_IF_W_S_DOWN_CH0_HBM_POLY_H3_15 0x481150
+
+#define mmDMA_IF_W_S_DOWN_CH0_HBM_POLY_H3_16 0x481154
+
+#define mmDMA_IF_W_S_DOWN_CH0_HBM_POLY_H3_17 0x481158
+
+#define mmDMA_IF_W_S_DOWN_CH0_HBM_POLY_H3_18 0x48115C
+
+#define mmDMA_IF_W_S_DOWN_CH0_HBM_POLY_H3_19 0x481160
+
+#define mmDMA_IF_W_S_DOWN_CH0_HBM_POLY_H3_20 0x481164
+
+#define mmDMA_IF_W_S_DOWN_CH0_HBM_POLY_H3_21 0x481168
+
+#define mmDMA_IF_W_S_DOWN_CH0_HBM_POLY_H3_22 0x48116C
+
+#define mmDMA_IF_W_S_DOWN_CH0_HBM_POLY_H3_23 0x481170
+
+#define mmDMA_IF_W_S_DOWN_CH0_HBM_POLY_H3_24 0x481174
+
+#define mmDMA_IF_W_S_DOWN_CH0_HBM_POLY_H3_25 0x481178
+
+#define mmDMA_IF_W_S_DOWN_CH0_HBM_POLY_H3_26 0x48117C
+
+#define mmDMA_IF_W_S_DOWN_CH0_HBM_POLY_H3_27 0x481180
+
+#define mmDMA_IF_W_S_DOWN_CH0_SRAM_POLY_H3_0 0x481184
+
+#define mmDMA_IF_W_S_DOWN_CH0_SRAM_POLY_H3_1 0x481188
+
+#define mmDMA_IF_W_S_DOWN_CH0_SRAM_POLY_H3_2 0x48118C
+
+#define mmDMA_IF_W_S_DOWN_CH0_SRAM_POLY_H3_3 0x481190
+
+#define mmDMA_IF_W_S_DOWN_CH0_SRAM_POLY_H3_4 0x481194
+
+#define mmDMA_IF_W_S_DOWN_CH0_SRAM_POLY_H3_5 0x481198
+
+#define mmDMA_IF_W_S_DOWN_CH0_SRAM_POLY_H3_6 0x48119C
+
+#define mmDMA_IF_W_S_DOWN_CH0_SRAM_POLY_H3_7 0x4811A0
+
+#define mmDMA_IF_W_S_DOWN_CH0_SRAM_POLY_H3_8 0x4811A4
+
+#define mmDMA_IF_W_S_DOWN_CH0_SRAM_POLY_H3_9 0x4811A8
+
+#define mmDMA_IF_W_S_DOWN_CH0_SRAM_POLY_H3_10 0x4811AC
+
+#define mmDMA_IF_W_S_DOWN_CH0_SRAM_POLY_H3_11 0x4811B0
+
+#define mmDMA_IF_W_S_DOWN_CH0_SRAM_POLY_H3_12 0x4811B4
+
+#define mmDMA_IF_W_S_DOWN_CH0_SRAM_POLY_H3_13 0x4811B8
+
+#define mmDMA_IF_W_S_DOWN_CH0_SRAM_POLY_H3_14 0x4811BC
+
+#define mmDMA_IF_W_S_DOWN_CH0_SCRAM_SRAM_EN 0x48126C
+
+#define mmDMA_IF_W_S_DOWN_CH0_RL_HBM_EN 0x481274
+
+#define mmDMA_IF_W_S_DOWN_CH0_RL_HBM_SAT 0x481278
+
+#define mmDMA_IF_W_S_DOWN_CH0_RL_HBM_RST 0x48127C
+
+#define mmDMA_IF_W_S_DOWN_CH0_RL_HBM_TIMEOUT 0x481280
+
+#define mmDMA_IF_W_S_DOWN_CH0_SCRAM_HBM_EN 0x481284
+
+#define mmDMA_IF_W_S_DOWN_CH0_RL_PCI_EN 0x481288
+
+#define mmDMA_IF_W_S_DOWN_CH0_RL_PCI_SAT 0x48128C
+
+#define mmDMA_IF_W_S_DOWN_CH0_RL_PCI_RST 0x481290
+
+#define mmDMA_IF_W_S_DOWN_CH0_RL_PCI_TIMEOUT 0x481294
+
+#define mmDMA_IF_W_S_DOWN_CH0_RL_SRAM_EN 0x48129C
+
+#define mmDMA_IF_W_S_DOWN_CH0_RL_SRAM_SAT 0x4812A0
+
+#define mmDMA_IF_W_S_DOWN_CH0_RL_SRAM_RST 0x4812A4
+
+#define mmDMA_IF_W_S_DOWN_CH0_RL_SRAM_TIMEOUT 0x4812AC
+
+#define mmDMA_IF_W_S_DOWN_CH0_RL_SRAM_RED 0x4812B4
+
+#define mmDMA_IF_W_S_DOWN_CH0_E2E_HBM_EN 0x4812EC
+
+#define mmDMA_IF_W_S_DOWN_CH0_E2E_PCI_EN 0x4812F0
+
+#define mmDMA_IF_W_S_DOWN_CH0_E2E_HBM_WR_SIZE 0x4812F4
+
+#define mmDMA_IF_W_S_DOWN_CH0_E2E_PCI_WR_SIZE 0x4812F8
+
+#define mmDMA_IF_W_S_DOWN_CH0_E2E_AW_PCI_CTR_SET_EN 0x481404
+
+#define mmDMA_IF_W_S_DOWN_CH0_E2E_AW_PCI_CTR_SET 0x481408
+
+#define mmDMA_IF_W_S_DOWN_CH0_E2E_AW_PCI_CTR_WRAP 0x48140C
+
+#define mmDMA_IF_W_S_DOWN_CH0_E2E_AW_PCI_CTR_CNT 0x481410
+
+#define mmDMA_IF_W_S_DOWN_CH0_E2E_AW_HBM_CTR_SET_EN 0x481414
+
+#define mmDMA_IF_W_S_DOWN_CH0_E2E_AW_HBM_CTR_SET 0x481418
+
+#define mmDMA_IF_W_S_DOWN_CH0_E2E_HBM_RD_SIZE 0x48141C
+
+#define mmDMA_IF_W_S_DOWN_CH0_E2E_PCI_RD_SIZE 0x481420
+
+#define mmDMA_IF_W_S_DOWN_CH0_E2E_AR_PCI_CTR_SET_EN 0x481424
+
+#define mmDMA_IF_W_S_DOWN_CH0_E2E_AR_PCI_CTR_SET 0x481428
+
+#define mmDMA_IF_W_S_DOWN_CH0_E2E_AR_PCI_CTR_WRAP 0x48142C
+
+#define mmDMA_IF_W_S_DOWN_CH0_E2E_AR_PCI_CTR_CNT 0x481430
+
+#define mmDMA_IF_W_S_DOWN_CH0_E2E_AR_HBM_CTR_SET_EN 0x481434
+
+#define mmDMA_IF_W_S_DOWN_CH0_E2E_AR_HBM_CTR_SET 0x481438
+
+#define mmDMA_IF_W_S_DOWN_CH0_NL_HBM_SEL_0 0x481450
+
+#define mmDMA_IF_W_S_DOWN_CH0_NL_HBM_SEL_1 0x481454
+
+#define mmDMA_IF_W_S_DOWN_CH0_NON_LIN_EN 0x481480
+
+#define mmDMA_IF_W_S_DOWN_CH0_NL_SRAM_BANK_0 0x481500
+
+#define mmDMA_IF_W_S_DOWN_CH0_NL_SRAM_BANK_1 0x481504
+
+#define mmDMA_IF_W_S_DOWN_CH0_NL_SRAM_BANK_2 0x481508
+
+#define mmDMA_IF_W_S_DOWN_CH0_NL_SRAM_BANK_3 0x48150C
+
+#define mmDMA_IF_W_S_DOWN_CH0_NL_SRAM_BANK_4 0x481510
+
+#define mmDMA_IF_W_S_DOWN_CH0_NL_SRAM_OFFSET_0 0x481514
+
+#define mmDMA_IF_W_S_DOWN_CH0_NL_SRAM_OFFSET_1 0x481520
+
+#define mmDMA_IF_W_S_DOWN_CH0_NL_SRAM_OFFSET_2 0x481524
+
+#define mmDMA_IF_W_S_DOWN_CH0_NL_SRAM_OFFSET_3 0x481528
+
+#define mmDMA_IF_W_S_DOWN_CH0_NL_SRAM_OFFSET_4 0x48152C
+
+#define mmDMA_IF_W_S_DOWN_CH0_NL_SRAM_OFFSET_5 0x481530
+
+#define mmDMA_IF_W_S_DOWN_CH0_NL_SRAM_OFFSET_6 0x481534
+
+#define mmDMA_IF_W_S_DOWN_CH0_NL_SRAM_OFFSET_7 0x481538
+
+#define mmDMA_IF_W_S_DOWN_CH0_NL_SRAM_OFFSET_8 0x48153C
+
+#define mmDMA_IF_W_S_DOWN_CH0_NL_SRAM_OFFSET_9 0x481540
+
+#define mmDMA_IF_W_S_DOWN_CH0_NL_HBM_OFFSET_0 0x481550
+
+#define mmDMA_IF_W_S_DOWN_CH0_NL_HBM_OFFSET_1 0x481554
+
+#define mmDMA_IF_W_S_DOWN_CH0_NL_HBM_OFFSET_2 0x481558
+
+#define mmDMA_IF_W_S_DOWN_CH0_NL_HBM_OFFSET_3 0x48155C
+
+#define mmDMA_IF_W_S_DOWN_CH0_NL_HBM_OFFSET_4 0x481560
+
+#define mmDMA_IF_W_S_DOWN_CH0_NL_HBM_OFFSET_5 0x481564
+
+#define mmDMA_IF_W_S_DOWN_CH0_NL_HBM_OFFSET_6 0x481568
+
+#define mmDMA_IF_W_S_DOWN_CH0_NL_HBM_OFFSET_7 0x48156C
+
+#define mmDMA_IF_W_S_DOWN_CH0_NL_HBM_OFFSET_8 0x481570
+
+#define mmDMA_IF_W_S_DOWN_CH0_NL_HBM_OFFSET_9 0x481574
+
+#define mmDMA_IF_W_S_DOWN_CH0_NL_HBM_OFFSET_10 0x481578
+
+#define mmDMA_IF_W_S_DOWN_CH0_NL_HBM_OFFSET_11 0x48157C
+
+#define mmDMA_IF_W_S_DOWN_CH0_NL_HBM_OFFSET_12 0x481580
+
+#define mmDMA_IF_W_S_DOWN_CH0_NL_HBM_OFFSET_13 0x481584
+
+#define mmDMA_IF_W_S_DOWN_CH0_NL_HBM_OFFSET_14 0x481588
+
+#define mmDMA_IF_W_S_DOWN_CH0_NL_HBM_OFFSET_15 0x48158C
+
+#define mmDMA_IF_W_S_DOWN_CH0_NL_HBM_OFFSET_16 0x481590
+
+#define mmDMA_IF_W_S_DOWN_CH0_NL_HBM_OFFSET_17 0x481594
+
+#define mmDMA_IF_W_S_DOWN_CH0_NL_HBM_OFFSET_18 0x481598
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_0 0x4815E4
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_1 0x4815E8
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_2 0x4815EC
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_3 0x4815F0
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_4 0x4815F4
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_5 0x4815F8
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_6 0x4815FC
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_7 0x481600
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_8 0x481604
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_9 0x481608
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_10 0x48160C
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_11 0x481610
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_12 0x481614
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_13 0x481618
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_14 0x48161C
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_15 0x481620
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_0 0x481624
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_1 0x481628
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_2 0x48162C
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_3 0x481630
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_4 0x481634
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_5 0x481638
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_6 0x48163C
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_7 0x481640
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_8 0x481644
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_9 0x481648
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_10 0x48164C
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_11 0x481650
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_12 0x481654
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_13 0x481658
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_14 0x48165C
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_15 0x481660
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_0 0x481664
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_1 0x481668
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_2 0x48166C
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_3 0x481670
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_4 0x481674
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_5 0x481678
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_6 0x48167C
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_7 0x481680
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_8 0x481684
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_9 0x481688
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_10 0x48168C
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_11 0x481690
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_12 0x481694
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_13 0x481698
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_14 0x48169C
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_15 0x4816A0
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_0 0x4816A4
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_1 0x4816A8
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_2 0x4816AC
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_3 0x4816B0
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_4 0x4816B4
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_5 0x4816B8
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_6 0x4816BC
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_7 0x4816C0
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_8 0x4816C4
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_9 0x4816C8
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_10 0x4816CC
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_11 0x4816D0
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_12 0x4816D4
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_13 0x4816D8
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_14 0x4816DC
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_15 0x4816E0
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_0 0x4816E4
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_1 0x4816E8
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_2 0x4816EC
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_3 0x4816F0
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_4 0x4816F4
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_5 0x4816F8
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_6 0x4816FC
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_7 0x481700
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_8 0x481704
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_9 0x481708
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_10 0x48170C
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_11 0x481710
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_12 0x481714
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_13 0x481718
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_14 0x48171C
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_15 0x481720
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_0 0x481724
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_1 0x481728
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_2 0x48172C
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_3 0x481730
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_4 0x481734
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_5 0x481738
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_6 0x48173C
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_7 0x481740
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_8 0x481744
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_9 0x481748
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_10 0x48174C
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_11 0x481750
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_12 0x481754
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_13 0x481758
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_14 0x48175C
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_15 0x481760
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_0 0x481764
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_1 0x481768
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_2 0x48176C
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_3 0x481770
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_4 0x481774
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_5 0x481778
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_6 0x48177C
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_7 0x481780
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_8 0x481784
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_9 0x481788
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_10 0x48178C
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_11 0x481790
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_12 0x481794
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_13 0x481798
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_14 0x48179C
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_15 0x4817A0
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_0 0x4817A4
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_1 0x4817A8
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_2 0x4817AC
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_3 0x4817B0
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_4 0x4817B4
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_5 0x4817B8
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_6 0x4817BC
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_7 0x4817C0
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_8 0x4817C4
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_9 0x4817C8
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_10 0x4817CC
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_11 0x4817D0
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_12 0x4817D4
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_13 0x4817D8
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_14 0x4817DC
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_15 0x4817E0
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_0 0x481824
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_1 0x481828
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_2 0x48182C
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_3 0x481830
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_4 0x481834
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_5 0x481838
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_6 0x48183C
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_7 0x481840
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_8 0x481844
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_9 0x481848
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_10 0x48184C
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_11 0x481850
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_12 0x481854
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_13 0x481858
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_14 0x48185C
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_15 0x481860
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_0 0x481864
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_1 0x481868
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_2 0x48186C
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_3 0x481870
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_4 0x481874
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_5 0x481878
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_6 0x48187C
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_7 0x481880
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_8 0x481884
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_9 0x481888
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_10 0x48188C
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_11 0x481890
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_12 0x481894
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_13 0x481898
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_14 0x48189C
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_15 0x4818A0
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_0 0x4818A4
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_1 0x4818A8
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_2 0x4818AC
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_3 0x4818B0
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_4 0x4818B4
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_5 0x4818B8
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_6 0x4818BC
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_7 0x4818C0
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_8 0x4818C4
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_9 0x4818C8
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_10 0x4818CC
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_11 0x4818D0
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_12 0x4818D4
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_13 0x4818D8
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_14 0x4818DC
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_15 0x4818E0
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_0 0x4818E4
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_1 0x4818E8
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_2 0x4818EC
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_3 0x4818F0
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_4 0x4818F4
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_5 0x4818F8
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_6 0x4818FC
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_7 0x481900
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_8 0x481904
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_9 0x481908
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_10 0x48190C
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_11 0x481910
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_12 0x481914
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_13 0x481918
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_14 0x48191C
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_15 0x481920
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_0 0x481924
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_1 0x481928
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_2 0x48192C
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_3 0x481930
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_4 0x481934
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_5 0x481938
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_6 0x48193C
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_7 0x481940
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_8 0x481944
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_9 0x481948
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_10 0x48194C
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_11 0x481950
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_12 0x481954
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_13 0x481958
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_14 0x48195C
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_15 0x481960
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_0 0x481964
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_1 0x481968
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_2 0x48196C
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_3 0x481970
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_4 0x481974
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_5 0x481978
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_6 0x48197C
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_7 0x481980
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_8 0x481984
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_9 0x481988
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_10 0x48198C
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_11 0x481990
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_12 0x481994
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_13 0x481998
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_14 0x48199C
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_15 0x4819A0
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_0 0x4819A4
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_1 0x4819A8
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_2 0x4819AC
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_3 0x4819B0
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_4 0x4819B4
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_5 0x4819B8
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_6 0x4819BC
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_7 0x4819C0
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_8 0x4819C4
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_9 0x4819C8
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_10 0x4819CC
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_11 0x4819D0
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_12 0x4819D4
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_13 0x4819D8
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_14 0x4819DC
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_15 0x4819E0
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_0 0x4819E4
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_1 0x4819E8
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_2 0x4819EC
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_3 0x4819F0
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_4 0x4819F4
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_5 0x4819F8
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_6 0x4819FC
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_7 0x481A00
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_8 0x481A04
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_9 0x481A08
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_10 0x481A0C
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_11 0x481A10
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_12 0x481A14
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_13 0x481A18
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_14 0x481A1C
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_15 0x481A20
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_HIT_AW 0x481A64
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_HIT_AR 0x481A68
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_HIT_AW 0x481A6C
+
+#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_HIT_AR 0x481A70
+
+#define mmDMA_IF_W_S_DOWN_CH0_RGL_CFG 0x481B64
+
+#define mmDMA_IF_W_S_DOWN_CH0_RGL_SHIFT 0x481B68
+
+#define mmDMA_IF_W_S_DOWN_CH0_RGL_EXPECTED_LAT_0 0x481B6C
+
+#define mmDMA_IF_W_S_DOWN_CH0_RGL_EXPECTED_LAT_1 0x481B70
+
+#define mmDMA_IF_W_S_DOWN_CH0_RGL_EXPECTED_LAT_2 0x481B74
+
+#define mmDMA_IF_W_S_DOWN_CH0_RGL_EXPECTED_LAT_3 0x481B78
+
+#define mmDMA_IF_W_S_DOWN_CH0_RGL_EXPECTED_LAT_4 0x481B7C
+
+#define mmDMA_IF_W_S_DOWN_CH0_RGL_EXPECTED_LAT_5 0x481B80
+
+#define mmDMA_IF_W_S_DOWN_CH0_RGL_EXPECTED_LAT_6 0x481B84
+
+#define mmDMA_IF_W_S_DOWN_CH0_RGL_EXPECTED_LAT_7 0x481B88
+
+#define mmDMA_IF_W_S_DOWN_CH0_RGL_TOKEN_0 0x481BAC
+
+#define mmDMA_IF_W_S_DOWN_CH0_RGL_TOKEN_1 0x481BB0
+
+#define mmDMA_IF_W_S_DOWN_CH0_RGL_TOKEN_2 0x481BB4
+
+#define mmDMA_IF_W_S_DOWN_CH0_RGL_TOKEN_3 0x481BB8
+
+#define mmDMA_IF_W_S_DOWN_CH0_RGL_TOKEN_4 0x481BBC
+
+#define mmDMA_IF_W_S_DOWN_CH0_RGL_TOKEN_5 0x481BC0
+
+#define mmDMA_IF_W_S_DOWN_CH0_RGL_TOKEN_6 0x481BC4
+
+#define mmDMA_IF_W_S_DOWN_CH0_RGL_TOKEN_7 0x481BC8
+
+#define mmDMA_IF_W_S_DOWN_CH0_RGL_BANK_ID_0 0x481BEC
+
+#define mmDMA_IF_W_S_DOWN_CH0_RGL_BANK_ID_1 0x481BF0
+
+#define mmDMA_IF_W_S_DOWN_CH0_RGL_BANK_ID_2 0x481BF4
+
+#define mmDMA_IF_W_S_DOWN_CH0_RGL_BANK_ID_3 0x481BF8
+
+#define mmDMA_IF_W_S_DOWN_CH0_RGL_BANK_ID_4 0x481BFC
+
+#define mmDMA_IF_W_S_DOWN_CH0_RGL_BANK_ID_5 0x481C00
+
+#define mmDMA_IF_W_S_DOWN_CH0_RGL_BANK_ID_6 0x481C04
+
+#define mmDMA_IF_W_S_DOWN_CH0_RGL_BANK_ID_7 0x481C08
+
+#define mmDMA_IF_W_S_DOWN_CH0_RGL_WDT 0x481C2C
+
+#define mmDMA_IF_W_S_DOWN_CH0_E2E_AR_HBM0_CH0_CTR_WRAP 0x481C30
+
+#define mmDMA_IF_W_S_DOWN_CH0_E2E_AR_HBM0_CH1_CTR_WRAP 0x481C34
+
+#define mmDMA_IF_W_S_DOWN_CH0_E2E_AR_HBM1_CH0_CTR_WRAP 0x481C38
+
+#define mmDMA_IF_W_S_DOWN_CH0_E2E_AR_HBM1_CH1_CTR_WRAP 0x481C3C
+
+#define mmDMA_IF_W_S_DOWN_CH0_E2E_AR_HBM2_CH0_CTR_WRAP 0x481C40
+
+#define mmDMA_IF_W_S_DOWN_CH0_E2E_AR_HBM2_CH1_CTR_WRAP 0x481C44
+
+#define mmDMA_IF_W_S_DOWN_CH0_E2E_AR_HBM3_CH0_CTR_WRAP 0x481C48
+
+#define mmDMA_IF_W_S_DOWN_CH0_E2E_AR_HBM3_CH1_CTR_WRAP 0x481C4C
+
+#define mmDMA_IF_W_S_DOWN_CH0_E2E_AR_HBM0_CH0_CTR_CNT 0x481C50
+
+#define mmDMA_IF_W_S_DOWN_CH0_E2E_AR_HBM0_CH1_CTR_CNT 0x481C54
+
+#define mmDMA_IF_W_S_DOWN_CH0_E2E_AR_HBM1_CH0_CTR_CNT 0x481C58
+
+#define mmDMA_IF_W_S_DOWN_CH0_E2E_AR_HBM1_CH1_CTR_CNT 0x481C5C
+
+#define mmDMA_IF_W_S_DOWN_CH0_E2E_AR_HBM2_CH0_CTR_CNT 0x481C60
+
+#define mmDMA_IF_W_S_DOWN_CH0_E2E_AR_HBM2_CH1_CTR_CNT 0x481C64
+
+#define mmDMA_IF_W_S_DOWN_CH0_E2E_AR_HBM3_CH0_CTR_CNT 0x481C68
+
+#define mmDMA_IF_W_S_DOWN_CH0_E2E_AR_HBM3_CH1_CTR_CNT 0x481C6C
+
+#define mmDMA_IF_W_S_DOWN_CH0_E2E_AW_HBM0_CH0_CTR_WRAP 0x481C70
+
+#define mmDMA_IF_W_S_DOWN_CH0_E2E_AW_HBM0_CH1_CTR_WRAP 0x481C74
+
+#define mmDMA_IF_W_S_DOWN_CH0_E2E_AW_HBM1_CH0_CTR_WRAP 0x481C78
+
+#define mmDMA_IF_W_S_DOWN_CH0_E2E_AW_HBM1_CH1_CTR_WRAP 0x481C7C
+
+#define mmDMA_IF_W_S_DOWN_CH0_E2E_AW_HBM2_CH0_CTR_WRAP 0x481C80
+
+#define mmDMA_IF_W_S_DOWN_CH0_E2E_AW_HBM2_CH1_CTR_WRAP 0x481C84
+
+#define mmDMA_IF_W_S_DOWN_CH0_E2E_AW_HBM3_CH0_CTR_WRAP 0x481C88
+
+#define mmDMA_IF_W_S_DOWN_CH0_E2E_AW_HBM3_CH1_CTR_WRAP 0x481C8C
+
+#define mmDMA_IF_W_S_DOWN_CH0_E2E_AW_HBM0_CH0_CTR_CNT 0x481C90
+
+#define mmDMA_IF_W_S_DOWN_CH0_E2E_AW_HBM0_CH1_CTR_CNT 0x481C94
+
+#define mmDMA_IF_W_S_DOWN_CH0_E2E_AW_HBM1_CH0_CTR_CNT 0x481C98
+
+#define mmDMA_IF_W_S_DOWN_CH0_E2E_AW_HBM1_CH1_CTR_CNT 0x481C9C
+
+#define mmDMA_IF_W_S_DOWN_CH0_E2E_AW_HBM2_CH0_CTR_CNT 0x481CA0
+
+#define mmDMA_IF_W_S_DOWN_CH0_E2E_AW_HBM2_CH1_CTR_CNT 0x481CA4
+
+#define mmDMA_IF_W_S_DOWN_CH0_E2E_AW_HBM3_CH0_CTR_CNT 0x481CA8
+
+#define mmDMA_IF_W_S_DOWN_CH0_E2E_AW_HBM3_CH1_CTR_CNT 0x481CAC
+
+#define mmDMA_IF_W_S_DOWN_CH0_NL_HBM_PC_SEL_0 0x481CB0
+
+#define mmDMA_IF_W_S_DOWN_CH0_NL_HBM_PC_SEL_1 0x481CB4
+
+#define mmDMA_IF_W_S_DOWN_CH0_NL_HBM_PC_SEL_2 0x481CB8
+
+#define mmDMA_IF_W_S_DOWN_CH0_NL_HBM_PC_SEL_3 0x481CBC
+
+#endif /* ASIC_REG_DMA_IF_W_S_DOWN_CH0_REGS_H_ */
diff --git a/drivers/accel/habanalabs/include/gaudi/asic_reg/dma_if_w_s_down_ch1_regs.h b/drivers/accel/habanalabs/include/gaudi/asic_reg/dma_if_w_s_down_ch1_regs.h
new file mode 100644
index 0000000000..cbc642918d
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi/asic_reg/dma_if_w_s_down_ch1_regs.h
@@ -0,0 +1,896 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2016-2018 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ ** DO NOT EDIT BELOW **
+ ************************************/
+
+#ifndef ASIC_REG_DMA_IF_W_S_DOWN_CH1_REGS_H_
+#define ASIC_REG_DMA_IF_W_S_DOWN_CH1_REGS_H_
+
+/*
+ *****************************************
+ * DMA_IF_W_S_DOWN_CH1 (Prototype: RTR_CTRL)
+ *****************************************
+ */
+
+#define mmDMA_IF_W_S_DOWN_CH1_PERM_SEL 0x482108
+
+#define mmDMA_IF_W_S_DOWN_CH1_HBM_POLY_H3_0 0x482114
+
+#define mmDMA_IF_W_S_DOWN_CH1_HBM_POLY_H3_1 0x482118
+
+#define mmDMA_IF_W_S_DOWN_CH1_HBM_POLY_H3_2 0x48211C
+
+#define mmDMA_IF_W_S_DOWN_CH1_HBM_POLY_H3_3 0x482120
+
+#define mmDMA_IF_W_S_DOWN_CH1_HBM_POLY_H3_4 0x482124
+
+#define mmDMA_IF_W_S_DOWN_CH1_HBM_POLY_H3_5 0x482128
+
+#define mmDMA_IF_W_S_DOWN_CH1_HBM_POLY_H3_6 0x48212C
+
+#define mmDMA_IF_W_S_DOWN_CH1_HBM_POLY_H3_7 0x482130
+
+#define mmDMA_IF_W_S_DOWN_CH1_HBM_POLY_H3_8 0x482134
+
+#define mmDMA_IF_W_S_DOWN_CH1_HBM_POLY_H3_9 0x482138
+
+#define mmDMA_IF_W_S_DOWN_CH1_HBM_POLY_H3_10 0x48213C
+
+#define mmDMA_IF_W_S_DOWN_CH1_HBM_POLY_H3_11 0x482140
+
+#define mmDMA_IF_W_S_DOWN_CH1_HBM_POLY_H3_12 0x482144
+
+#define mmDMA_IF_W_S_DOWN_CH1_HBM_POLY_H3_13 0x482148
+
+#define mmDMA_IF_W_S_DOWN_CH1_HBM_POLY_H3_14 0x48214C
+
+#define mmDMA_IF_W_S_DOWN_CH1_HBM_POLY_H3_15 0x482150
+
+#define mmDMA_IF_W_S_DOWN_CH1_HBM_POLY_H3_16 0x482154
+
+#define mmDMA_IF_W_S_DOWN_CH1_HBM_POLY_H3_17 0x482158
+
+#define mmDMA_IF_W_S_DOWN_CH1_HBM_POLY_H3_18 0x48215C
+
+#define mmDMA_IF_W_S_DOWN_CH1_HBM_POLY_H3_19 0x482160
+
+#define mmDMA_IF_W_S_DOWN_CH1_HBM_POLY_H3_20 0x482164
+
+#define mmDMA_IF_W_S_DOWN_CH1_HBM_POLY_H3_21 0x482168
+
+#define mmDMA_IF_W_S_DOWN_CH1_HBM_POLY_H3_22 0x48216C
+
+#define mmDMA_IF_W_S_DOWN_CH1_HBM_POLY_H3_23 0x482170
+
+#define mmDMA_IF_W_S_DOWN_CH1_HBM_POLY_H3_24 0x482174
+
+#define mmDMA_IF_W_S_DOWN_CH1_HBM_POLY_H3_25 0x482178
+
+#define mmDMA_IF_W_S_DOWN_CH1_HBM_POLY_H3_26 0x48217C
+
+#define mmDMA_IF_W_S_DOWN_CH1_HBM_POLY_H3_27 0x482180
+
+#define mmDMA_IF_W_S_DOWN_CH1_SRAM_POLY_H3_0 0x482184
+
+#define mmDMA_IF_W_S_DOWN_CH1_SRAM_POLY_H3_1 0x482188
+
+#define mmDMA_IF_W_S_DOWN_CH1_SRAM_POLY_H3_2 0x48218C
+
+#define mmDMA_IF_W_S_DOWN_CH1_SRAM_POLY_H3_3 0x482190
+
+#define mmDMA_IF_W_S_DOWN_CH1_SRAM_POLY_H3_4 0x482194
+
+#define mmDMA_IF_W_S_DOWN_CH1_SRAM_POLY_H3_5 0x482198
+
+#define mmDMA_IF_W_S_DOWN_CH1_SRAM_POLY_H3_6 0x48219C
+
+#define mmDMA_IF_W_S_DOWN_CH1_SRAM_POLY_H3_7 0x4821A0
+
+#define mmDMA_IF_W_S_DOWN_CH1_SRAM_POLY_H3_8 0x4821A4
+
+#define mmDMA_IF_W_S_DOWN_CH1_SRAM_POLY_H3_9 0x4821A8
+
+#define mmDMA_IF_W_S_DOWN_CH1_SRAM_POLY_H3_10 0x4821AC
+
+#define mmDMA_IF_W_S_DOWN_CH1_SRAM_POLY_H3_11 0x4821B0
+
+#define mmDMA_IF_W_S_DOWN_CH1_SRAM_POLY_H3_12 0x4821B4
+
+#define mmDMA_IF_W_S_DOWN_CH1_SRAM_POLY_H3_13 0x4821B8
+
+#define mmDMA_IF_W_S_DOWN_CH1_SRAM_POLY_H3_14 0x4821BC
+
+#define mmDMA_IF_W_S_DOWN_CH1_SCRAM_SRAM_EN 0x48226C
+
+#define mmDMA_IF_W_S_DOWN_CH1_RL_HBM_EN 0x482274
+
+#define mmDMA_IF_W_S_DOWN_CH1_RL_HBM_SAT 0x482278
+
+#define mmDMA_IF_W_S_DOWN_CH1_RL_HBM_RST 0x48227C
+
+#define mmDMA_IF_W_S_DOWN_CH1_RL_HBM_TIMEOUT 0x482280
+
+#define mmDMA_IF_W_S_DOWN_CH1_SCRAM_HBM_EN 0x482284
+
+#define mmDMA_IF_W_S_DOWN_CH1_RL_PCI_EN 0x482288
+
+#define mmDMA_IF_W_S_DOWN_CH1_RL_PCI_SAT 0x48228C
+
+#define mmDMA_IF_W_S_DOWN_CH1_RL_PCI_RST 0x482290
+
+#define mmDMA_IF_W_S_DOWN_CH1_RL_PCI_TIMEOUT 0x482294
+
+#define mmDMA_IF_W_S_DOWN_CH1_RL_SRAM_EN 0x48229C
+
+#define mmDMA_IF_W_S_DOWN_CH1_RL_SRAM_SAT 0x4822A0
+
+#define mmDMA_IF_W_S_DOWN_CH1_RL_SRAM_RST 0x4822A4
+
+#define mmDMA_IF_W_S_DOWN_CH1_RL_SRAM_TIMEOUT 0x4822AC
+
+#define mmDMA_IF_W_S_DOWN_CH1_RL_SRAM_RED 0x4822B4
+
+#define mmDMA_IF_W_S_DOWN_CH1_E2E_HBM_EN 0x4822EC
+
+#define mmDMA_IF_W_S_DOWN_CH1_E2E_PCI_EN 0x4822F0
+
+#define mmDMA_IF_W_S_DOWN_CH1_E2E_HBM_WR_SIZE 0x4822F4
+
+#define mmDMA_IF_W_S_DOWN_CH1_E2E_PCI_WR_SIZE 0x4822F8
+
+#define mmDMA_IF_W_S_DOWN_CH1_E2E_AW_PCI_CTR_SET_EN 0x482404
+
+#define mmDMA_IF_W_S_DOWN_CH1_E2E_AW_PCI_CTR_SET 0x482408
+
+#define mmDMA_IF_W_S_DOWN_CH1_E2E_AW_PCI_CTR_WRAP 0x48240C
+
+#define mmDMA_IF_W_S_DOWN_CH1_E2E_AW_PCI_CTR_CNT 0x482410
+
+#define mmDMA_IF_W_S_DOWN_CH1_E2E_AW_HBM_CTR_SET_EN 0x482414
+
+#define mmDMA_IF_W_S_DOWN_CH1_E2E_AW_HBM_CTR_SET 0x482418
+
+#define mmDMA_IF_W_S_DOWN_CH1_E2E_HBM_RD_SIZE 0x48241C
+
+#define mmDMA_IF_W_S_DOWN_CH1_E2E_PCI_RD_SIZE 0x482420
+
+#define mmDMA_IF_W_S_DOWN_CH1_E2E_AR_PCI_CTR_SET_EN 0x482424
+
+#define mmDMA_IF_W_S_DOWN_CH1_E2E_AR_PCI_CTR_SET 0x482428
+
+#define mmDMA_IF_W_S_DOWN_CH1_E2E_AR_PCI_CTR_WRAP 0x48242C
+
+#define mmDMA_IF_W_S_DOWN_CH1_E2E_AR_PCI_CTR_CNT 0x482430
+
+#define mmDMA_IF_W_S_DOWN_CH1_E2E_AR_HBM_CTR_SET_EN 0x482434
+
+#define mmDMA_IF_W_S_DOWN_CH1_E2E_AR_HBM_CTR_SET 0x482438
+
+#define mmDMA_IF_W_S_DOWN_CH1_NL_HBM_SEL_0 0x482450
+
+#define mmDMA_IF_W_S_DOWN_CH1_NL_HBM_SEL_1 0x482454
+
+#define mmDMA_IF_W_S_DOWN_CH1_NON_LIN_EN 0x482480
+
+#define mmDMA_IF_W_S_DOWN_CH1_NL_SRAM_BANK_0 0x482500
+
+#define mmDMA_IF_W_S_DOWN_CH1_NL_SRAM_BANK_1 0x482504
+
+#define mmDMA_IF_W_S_DOWN_CH1_NL_SRAM_BANK_2 0x482508
+
+#define mmDMA_IF_W_S_DOWN_CH1_NL_SRAM_BANK_3 0x48250C
+
+#define mmDMA_IF_W_S_DOWN_CH1_NL_SRAM_BANK_4 0x482510
+
+#define mmDMA_IF_W_S_DOWN_CH1_NL_SRAM_OFFSET_0 0x482514
+
+#define mmDMA_IF_W_S_DOWN_CH1_NL_SRAM_OFFSET_1 0x482520
+
+#define mmDMA_IF_W_S_DOWN_CH1_NL_SRAM_OFFSET_2 0x482524
+
+#define mmDMA_IF_W_S_DOWN_CH1_NL_SRAM_OFFSET_3 0x482528
+
+#define mmDMA_IF_W_S_DOWN_CH1_NL_SRAM_OFFSET_4 0x48252C
+
+#define mmDMA_IF_W_S_DOWN_CH1_NL_SRAM_OFFSET_5 0x482530
+
+#define mmDMA_IF_W_S_DOWN_CH1_NL_SRAM_OFFSET_6 0x482534
+
+#define mmDMA_IF_W_S_DOWN_CH1_NL_SRAM_OFFSET_7 0x482538
+
+#define mmDMA_IF_W_S_DOWN_CH1_NL_SRAM_OFFSET_8 0x48253C
+
+#define mmDMA_IF_W_S_DOWN_CH1_NL_SRAM_OFFSET_9 0x482540
+
+#define mmDMA_IF_W_S_DOWN_CH1_NL_HBM_OFFSET_0 0x482550
+
+#define mmDMA_IF_W_S_DOWN_CH1_NL_HBM_OFFSET_1 0x482554
+
+#define mmDMA_IF_W_S_DOWN_CH1_NL_HBM_OFFSET_2 0x482558
+
+#define mmDMA_IF_W_S_DOWN_CH1_NL_HBM_OFFSET_3 0x48255C
+
+#define mmDMA_IF_W_S_DOWN_CH1_NL_HBM_OFFSET_4 0x482560
+
+#define mmDMA_IF_W_S_DOWN_CH1_NL_HBM_OFFSET_5 0x482564
+
+#define mmDMA_IF_W_S_DOWN_CH1_NL_HBM_OFFSET_6 0x482568
+
+#define mmDMA_IF_W_S_DOWN_CH1_NL_HBM_OFFSET_7 0x48256C
+
+#define mmDMA_IF_W_S_DOWN_CH1_NL_HBM_OFFSET_8 0x482570
+
+#define mmDMA_IF_W_S_DOWN_CH1_NL_HBM_OFFSET_9 0x482574
+
+#define mmDMA_IF_W_S_DOWN_CH1_NL_HBM_OFFSET_10 0x482578
+
+#define mmDMA_IF_W_S_DOWN_CH1_NL_HBM_OFFSET_11 0x48257C
+
+#define mmDMA_IF_W_S_DOWN_CH1_NL_HBM_OFFSET_12 0x482580
+
+#define mmDMA_IF_W_S_DOWN_CH1_NL_HBM_OFFSET_13 0x482584
+
+#define mmDMA_IF_W_S_DOWN_CH1_NL_HBM_OFFSET_14 0x482588
+
+#define mmDMA_IF_W_S_DOWN_CH1_NL_HBM_OFFSET_15 0x48258C
+
+#define mmDMA_IF_W_S_DOWN_CH1_NL_HBM_OFFSET_16 0x482590
+
+#define mmDMA_IF_W_S_DOWN_CH1_NL_HBM_OFFSET_17 0x482594
+
+#define mmDMA_IF_W_S_DOWN_CH1_NL_HBM_OFFSET_18 0x482598
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_0 0x4825E4
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_1 0x4825E8
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_2 0x4825EC
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_3 0x4825F0
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_4 0x4825F4
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_5 0x4825F8
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_6 0x4825FC
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_7 0x482600
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_8 0x482604
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_9 0x482608
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_10 0x48260C
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_11 0x482610
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_12 0x482614
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_13 0x482618
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_14 0x48261C
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_15 0x482620
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_0 0x482624
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_1 0x482628
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_2 0x48262C
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_3 0x482630
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_4 0x482634
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_5 0x482638
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_6 0x48263C
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_7 0x482640
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_8 0x482644
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_9 0x482648
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_10 0x48264C
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_11 0x482650
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_12 0x482654
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_13 0x482658
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_14 0x48265C
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_15 0x482660
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_0 0x482664
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_1 0x482668
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_2 0x48266C
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_3 0x482670
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_4 0x482674
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_5 0x482678
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_6 0x48267C
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_7 0x482680
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_8 0x482684
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_9 0x482688
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_10 0x48268C
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_11 0x482690
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_12 0x482694
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_13 0x482698
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_14 0x48269C
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_15 0x4826A0
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_0 0x4826A4
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_1 0x4826A8
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_2 0x4826AC
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_3 0x4826B0
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_4 0x4826B4
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_5 0x4826B8
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_6 0x4826BC
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_7 0x4826C0
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_8 0x4826C4
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_9 0x4826C8
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_10 0x4826CC
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_11 0x4826D0
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_12 0x4826D4
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_13 0x4826D8
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_14 0x4826DC
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_15 0x4826E0
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_0 0x4826E4
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_1 0x4826E8
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_2 0x4826EC
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_3 0x4826F0
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_4 0x4826F4
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_5 0x4826F8
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_6 0x4826FC
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_7 0x482700
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_8 0x482704
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_9 0x482708
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_10 0x48270C
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_11 0x482710
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_12 0x482714
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_13 0x482718
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_14 0x48271C
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_15 0x482720
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_0 0x482724
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_1 0x482728
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_2 0x48272C
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_3 0x482730
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_4 0x482734
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_5 0x482738
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_6 0x48273C
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_7 0x482740
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_8 0x482744
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_9 0x482748
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_10 0x48274C
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_11 0x482750
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_12 0x482754
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_13 0x482758
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_14 0x48275C
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_15 0x482760
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_0 0x482764
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_1 0x482768
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_2 0x48276C
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_3 0x482770
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_4 0x482774
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_5 0x482778
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_6 0x48277C
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_7 0x482780
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_8 0x482784
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_9 0x482788
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_10 0x48278C
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_11 0x482790
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_12 0x482794
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_13 0x482798
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_14 0x48279C
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_15 0x4827A0
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_0 0x4827A4
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_1 0x4827A8
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_2 0x4827AC
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_3 0x4827B0
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_4 0x4827B4
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_5 0x4827B8
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_6 0x4827BC
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_7 0x4827C0
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_8 0x4827C4
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_9 0x4827C8
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_10 0x4827CC
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_11 0x4827D0
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_12 0x4827D4
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_13 0x4827D8
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_14 0x4827DC
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_15 0x4827E0
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_0 0x482824
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_1 0x482828
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_2 0x48282C
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_3 0x482830
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_4 0x482834
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_5 0x482838
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_6 0x48283C
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_7 0x482840
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_8 0x482844
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_9 0x482848
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_10 0x48284C
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_11 0x482850
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_12 0x482854
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_13 0x482858
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_14 0x48285C
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_15 0x482860
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_0 0x482864
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_1 0x482868
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_2 0x48286C
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_3 0x482870
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_4 0x482874
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_5 0x482878
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_6 0x48287C
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_7 0x482880
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_8 0x482884
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_9 0x482888
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_10 0x48288C
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_11 0x482890
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_12 0x482894
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_13 0x482898
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_14 0x48289C
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_15 0x4828A0
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_0 0x4828A4
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_1 0x4828A8
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_2 0x4828AC
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_3 0x4828B0
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_4 0x4828B4
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_5 0x4828B8
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_6 0x4828BC
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_7 0x4828C0
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_8 0x4828C4
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_9 0x4828C8
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_10 0x4828CC
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_11 0x4828D0
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_12 0x4828D4
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_13 0x4828D8
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_14 0x4828DC
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_15 0x4828E0
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_0 0x4828E4
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_1 0x4828E8
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_2 0x4828EC
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_3 0x4828F0
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_4 0x4828F4
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_5 0x4828F8
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_6 0x4828FC
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_7 0x482900
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_8 0x482904
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_9 0x482908
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_10 0x48290C
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_11 0x482910
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_12 0x482914
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_13 0x482918
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_14 0x48291C
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_15 0x482920
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_0 0x482924
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_1 0x482928
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_2 0x48292C
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_3 0x482930
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_4 0x482934
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_5 0x482938
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_6 0x48293C
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_7 0x482940
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_8 0x482944
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_9 0x482948
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_10 0x48294C
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_11 0x482950
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_12 0x482954
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_13 0x482958
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_14 0x48295C
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_15 0x482960
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_0 0x482964
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_1 0x482968
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_2 0x48296C
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_3 0x482970
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_4 0x482974
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_5 0x482978
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_6 0x48297C
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_7 0x482980
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_8 0x482984
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_9 0x482988
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_10 0x48298C
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_11 0x482990
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_12 0x482994
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_13 0x482998
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_14 0x48299C
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_15 0x4829A0
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_0 0x4829A4
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_1 0x4829A8
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_2 0x4829AC
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_3 0x4829B0
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_4 0x4829B4
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_5 0x4829B8
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_6 0x4829BC
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_7 0x4829C0
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_8 0x4829C4
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_9 0x4829C8
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_10 0x4829CC
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_11 0x4829D0
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_12 0x4829D4
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_13 0x4829D8
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_14 0x4829DC
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_15 0x4829E0
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_0 0x4829E4
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_1 0x4829E8
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_2 0x4829EC
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_3 0x4829F0
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_4 0x4829F4
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_5 0x4829F8
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_6 0x4829FC
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_7 0x482A00
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_8 0x482A04
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_9 0x482A08
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_10 0x482A0C
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_11 0x482A10
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_12 0x482A14
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_13 0x482A18
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_14 0x482A1C
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_15 0x482A20
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_HIT_AW 0x482A64
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_HIT_AR 0x482A68
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_HIT_AW 0x482A6C
+
+#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_HIT_AR 0x482A70
+
+#define mmDMA_IF_W_S_DOWN_CH1_RGL_CFG 0x482B64
+
+#define mmDMA_IF_W_S_DOWN_CH1_RGL_SHIFT 0x482B68
+
+#define mmDMA_IF_W_S_DOWN_CH1_RGL_EXPECTED_LAT_0 0x482B6C
+
+#define mmDMA_IF_W_S_DOWN_CH1_RGL_EXPECTED_LAT_1 0x482B70
+
+#define mmDMA_IF_W_S_DOWN_CH1_RGL_EXPECTED_LAT_2 0x482B74
+
+#define mmDMA_IF_W_S_DOWN_CH1_RGL_EXPECTED_LAT_3 0x482B78
+
+#define mmDMA_IF_W_S_DOWN_CH1_RGL_EXPECTED_LAT_4 0x482B7C
+
+#define mmDMA_IF_W_S_DOWN_CH1_RGL_EXPECTED_LAT_5 0x482B80
+
+#define mmDMA_IF_W_S_DOWN_CH1_RGL_EXPECTED_LAT_6 0x482B84
+
+#define mmDMA_IF_W_S_DOWN_CH1_RGL_EXPECTED_LAT_7 0x482B88
+
+#define mmDMA_IF_W_S_DOWN_CH1_RGL_TOKEN_0 0x482BAC
+
+#define mmDMA_IF_W_S_DOWN_CH1_RGL_TOKEN_1 0x482BB0
+
+#define mmDMA_IF_W_S_DOWN_CH1_RGL_TOKEN_2 0x482BB4
+
+#define mmDMA_IF_W_S_DOWN_CH1_RGL_TOKEN_3 0x482BB8
+
+#define mmDMA_IF_W_S_DOWN_CH1_RGL_TOKEN_4 0x482BBC
+
+#define mmDMA_IF_W_S_DOWN_CH1_RGL_TOKEN_5 0x482BC0
+
+#define mmDMA_IF_W_S_DOWN_CH1_RGL_TOKEN_6 0x482BC4
+
+#define mmDMA_IF_W_S_DOWN_CH1_RGL_TOKEN_7 0x482BC8
+
+#define mmDMA_IF_W_S_DOWN_CH1_RGL_BANK_ID_0 0x482BEC
+
+#define mmDMA_IF_W_S_DOWN_CH1_RGL_BANK_ID_1 0x482BF0
+
+#define mmDMA_IF_W_S_DOWN_CH1_RGL_BANK_ID_2 0x482BF4
+
+#define mmDMA_IF_W_S_DOWN_CH1_RGL_BANK_ID_3 0x482BF8
+
+#define mmDMA_IF_W_S_DOWN_CH1_RGL_BANK_ID_4 0x482BFC
+
+#define mmDMA_IF_W_S_DOWN_CH1_RGL_BANK_ID_5 0x482C00
+
+#define mmDMA_IF_W_S_DOWN_CH1_RGL_BANK_ID_6 0x482C04
+
+#define mmDMA_IF_W_S_DOWN_CH1_RGL_BANK_ID_7 0x482C08
+
+#define mmDMA_IF_W_S_DOWN_CH1_RGL_WDT 0x482C2C
+
+#define mmDMA_IF_W_S_DOWN_CH1_E2E_AR_HBM0_CH0_CTR_WRAP 0x482C30
+
+#define mmDMA_IF_W_S_DOWN_CH1_E2E_AR_HBM0_CH1_CTR_WRAP 0x482C34
+
+#define mmDMA_IF_W_S_DOWN_CH1_E2E_AR_HBM1_CH0_CTR_WRAP 0x482C38
+
+#define mmDMA_IF_W_S_DOWN_CH1_E2E_AR_HBM1_CH1_CTR_WRAP 0x482C3C
+
+#define mmDMA_IF_W_S_DOWN_CH1_E2E_AR_HBM2_CH0_CTR_WRAP 0x482C40
+
+#define mmDMA_IF_W_S_DOWN_CH1_E2E_AR_HBM2_CH1_CTR_WRAP 0x482C44
+
+#define mmDMA_IF_W_S_DOWN_CH1_E2E_AR_HBM3_CH0_CTR_WRAP 0x482C48
+
+#define mmDMA_IF_W_S_DOWN_CH1_E2E_AR_HBM3_CH1_CTR_WRAP 0x482C4C
+
+#define mmDMA_IF_W_S_DOWN_CH1_E2E_AR_HBM0_CH0_CTR_CNT 0x482C50
+
+#define mmDMA_IF_W_S_DOWN_CH1_E2E_AR_HBM0_CH1_CTR_CNT 0x482C54
+
+#define mmDMA_IF_W_S_DOWN_CH1_E2E_AR_HBM1_CH0_CTR_CNT 0x482C58
+
+#define mmDMA_IF_W_S_DOWN_CH1_E2E_AR_HBM1_CH1_CTR_CNT 0x482C5C
+
+#define mmDMA_IF_W_S_DOWN_CH1_E2E_AR_HBM2_CH0_CTR_CNT 0x482C60
+
+#define mmDMA_IF_W_S_DOWN_CH1_E2E_AR_HBM2_CH1_CTR_CNT 0x482C64
+
+#define mmDMA_IF_W_S_DOWN_CH1_E2E_AR_HBM3_CH0_CTR_CNT 0x482C68
+
+#define mmDMA_IF_W_S_DOWN_CH1_E2E_AR_HBM3_CH1_CTR_CNT 0x482C6C
+
+#define mmDMA_IF_W_S_DOWN_CH1_E2E_AW_HBM0_CH0_CTR_WRAP 0x482C70
+
+#define mmDMA_IF_W_S_DOWN_CH1_E2E_AW_HBM0_CH1_CTR_WRAP 0x482C74
+
+#define mmDMA_IF_W_S_DOWN_CH1_E2E_AW_HBM1_CH0_CTR_WRAP 0x482C78
+
+#define mmDMA_IF_W_S_DOWN_CH1_E2E_AW_HBM1_CH1_CTR_WRAP 0x482C7C
+
+#define mmDMA_IF_W_S_DOWN_CH1_E2E_AW_HBM2_CH0_CTR_WRAP 0x482C80
+
+#define mmDMA_IF_W_S_DOWN_CH1_E2E_AW_HBM2_CH1_CTR_WRAP 0x482C84
+
+#define mmDMA_IF_W_S_DOWN_CH1_E2E_AW_HBM3_CH0_CTR_WRAP 0x482C88
+
+#define mmDMA_IF_W_S_DOWN_CH1_E2E_AW_HBM3_CH1_CTR_WRAP 0x482C8C
+
+#define mmDMA_IF_W_S_DOWN_CH1_E2E_AW_HBM0_CH0_CTR_CNT 0x482C90
+
+#define mmDMA_IF_W_S_DOWN_CH1_E2E_AW_HBM0_CH1_CTR_CNT 0x482C94
+
+#define mmDMA_IF_W_S_DOWN_CH1_E2E_AW_HBM1_CH0_CTR_CNT 0x482C98
+
+#define mmDMA_IF_W_S_DOWN_CH1_E2E_AW_HBM1_CH1_CTR_CNT 0x482C9C
+
+#define mmDMA_IF_W_S_DOWN_CH1_E2E_AW_HBM2_CH0_CTR_CNT 0x482CA0
+
+#define mmDMA_IF_W_S_DOWN_CH1_E2E_AW_HBM2_CH1_CTR_CNT 0x482CA4
+
+#define mmDMA_IF_W_S_DOWN_CH1_E2E_AW_HBM3_CH0_CTR_CNT 0x482CA8
+
+#define mmDMA_IF_W_S_DOWN_CH1_E2E_AW_HBM3_CH1_CTR_CNT 0x482CAC
+
+#define mmDMA_IF_W_S_DOWN_CH1_NL_HBM_PC_SEL_0 0x482CB0
+
+#define mmDMA_IF_W_S_DOWN_CH1_NL_HBM_PC_SEL_1 0x482CB4
+
+#define mmDMA_IF_W_S_DOWN_CH1_NL_HBM_PC_SEL_2 0x482CB8
+
+#define mmDMA_IF_W_S_DOWN_CH1_NL_HBM_PC_SEL_3 0x482CBC
+
+#endif /* ASIC_REG_DMA_IF_W_S_DOWN_CH1_REGS_H_ */
diff --git a/drivers/accel/habanalabs/include/gaudi/asic_reg/dma_if_w_s_regs.h b/drivers/accel/habanalabs/include/gaudi/asic_reg/dma_if_w_s_regs.h
new file mode 100644
index 0000000000..2382bc41be
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi/asic_reg/dma_if_w_s_regs.h
@@ -0,0 +1,860 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2016-2018 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ ** DO NOT EDIT BELOW **
+ ************************************/
+
+#ifndef ASIC_REG_DMA_IF_W_S_REGS_H_
+#define ASIC_REG_DMA_IF_W_S_REGS_H_
+
+/*
+ *****************************************
+ * DMA_IF_W_S (Prototype: DMA_IF)
+ *****************************************
+ */
+
+#define mmDMA_IF_W_S_HBM0_WR_CRED_CNT 0x480000
+
+#define mmDMA_IF_W_S_HBM1_WR_CRED_CNT 0x480004
+
+#define mmDMA_IF_W_S_HBM0_RD_CRED_CNT 0x480008
+
+#define mmDMA_IF_W_S_HBM1_RD_CRED_CNT 0x48000C
+
+#define mmDMA_IF_W_S_HBM_LIMITER_0 0x480030
+
+#define mmDMA_IF_W_S_HBM_LIMITER_1 0x480034
+
+#define mmDMA_IF_W_S_HBM_LIMITER_2 0x480038
+
+#define mmDMA_IF_W_S_HBM_LIMITER_3 0x48003C
+
+#define mmDMA_IF_W_S_HBM_ALMOST_EN_0 0x480040
+
+#define mmDMA_IF_W_S_HBM_ALMOST_EN_1 0x480044
+
+#define mmDMA_IF_W_S_HBM_CRED_EN_0 0x480050
+
+#define mmDMA_IF_W_S_HBM_CRED_EN_1 0x480054
+
+#define mmDMA_IF_W_S_SOB_MIN_RPROT_0 0x480100
+
+#define mmDMA_IF_W_S_SOB_MIN_RPROT_1 0x480104
+
+#define mmDMA_IF_W_S_SOB_MIN_RPROT_2 0x480108
+
+#define mmDMA_IF_W_S_SOB_MIN_RPROT_3 0x48010C
+
+#define mmDMA_IF_W_S_SOB_MIN_RPROT_4 0x480110
+
+#define mmDMA_IF_W_S_SOB_MIN_RPROT_5 0x480114
+
+#define mmDMA_IF_W_S_SOB_MIN_RPROT_6 0x480118
+
+#define mmDMA_IF_W_S_SOB_MIN_RPROT_7 0x48011C
+
+#define mmDMA_IF_W_S_SOB_MIN_RPROT_8 0x480120
+
+#define mmDMA_IF_W_S_SOB_MIN_RPROT_9 0x480124
+
+#define mmDMA_IF_W_S_SOB_MIN_RPROT_10 0x480128
+
+#define mmDMA_IF_W_S_SOB_MIN_RPROT_11 0x48012C
+
+#define mmDMA_IF_W_S_SOB_MIN_RPROT_12 0x480130
+
+#define mmDMA_IF_W_S_SOB_MIN_RPROT_13 0x480134
+
+#define mmDMA_IF_W_S_SOB_MIN_RPROT_14 0x480138
+
+#define mmDMA_IF_W_S_SOB_MIN_RPROT_15 0x48013C
+
+#define mmDMA_IF_W_S_SOB_MAX_RPROT_0 0x480140
+
+#define mmDMA_IF_W_S_SOB_MAX_RPROT_1 0x480144
+
+#define mmDMA_IF_W_S_SOB_MAX_RPROT_2 0x480148
+
+#define mmDMA_IF_W_S_SOB_MAX_RPROT_3 0x48014C
+
+#define mmDMA_IF_W_S_SOB_MAX_RPROT_4 0x480150
+
+#define mmDMA_IF_W_S_SOB_MAX_RPROT_5 0x480154
+
+#define mmDMA_IF_W_S_SOB_MAX_RPROT_6 0x480158
+
+#define mmDMA_IF_W_S_SOB_MAX_RPROT_7 0x48015C
+
+#define mmDMA_IF_W_S_SOB_MAX_RPROT_8 0x480160
+
+#define mmDMA_IF_W_S_SOB_MAX_RPROT_9 0x480164
+
+#define mmDMA_IF_W_S_SOB_MAX_RPROT_10 0x480168
+
+#define mmDMA_IF_W_S_SOB_MAX_RPROT_11 0x48016C
+
+#define mmDMA_IF_W_S_SOB_MAX_RPROT_12 0x480170
+
+#define mmDMA_IF_W_S_SOB_MAX_RPROT_13 0x480174
+
+#define mmDMA_IF_W_S_SOB_MAX_RPROT_14 0x480178
+
+#define mmDMA_IF_W_S_SOB_MAX_RPROT_15 0x48017C
+
+#define mmDMA_IF_W_S_SOB_MIN_WPROT_0 0x480180
+
+#define mmDMA_IF_W_S_SOB_MIN_WPROT_1 0x480184
+
+#define mmDMA_IF_W_S_SOB_MIN_WPROT_2 0x480188
+
+#define mmDMA_IF_W_S_SOB_MIN_WPROT_3 0x48018C
+
+#define mmDMA_IF_W_S_SOB_MIN_WPROT_4 0x480190
+
+#define mmDMA_IF_W_S_SOB_MIN_WPROT_5 0x480194
+
+#define mmDMA_IF_W_S_SOB_MIN_WPROT_6 0x480198
+
+#define mmDMA_IF_W_S_SOB_MIN_WPROT_7 0x48019C
+
+#define mmDMA_IF_W_S_SOB_MIN_WPROT_8 0x4801A0
+
+#define mmDMA_IF_W_S_SOB_MIN_WPROT_9 0x4801A4
+
+#define mmDMA_IF_W_S_SOB_MIN_WPROT_10 0x4801A8
+
+#define mmDMA_IF_W_S_SOB_MIN_WPROT_11 0x4801AC
+
+#define mmDMA_IF_W_S_SOB_MIN_WPROT_12 0x4801B0
+
+#define mmDMA_IF_W_S_SOB_MIN_WPROT_13 0x4801B4
+
+#define mmDMA_IF_W_S_SOB_MIN_WPROT_14 0x4801B8
+
+#define mmDMA_IF_W_S_SOB_MIN_WPROT_15 0x4801BC
+
+#define mmDMA_IF_W_S_SOB_MAX_WPROT_0 0x4801C0
+
+#define mmDMA_IF_W_S_SOB_MAX_WPROT_1 0x4801C4
+
+#define mmDMA_IF_W_S_SOB_MAX_WPROT_2 0x4801C8
+
+#define mmDMA_IF_W_S_SOB_MAX_WPROT_3 0x4801CC
+
+#define mmDMA_IF_W_S_SOB_MAX_WPROT_4 0x4801D0
+
+#define mmDMA_IF_W_S_SOB_MAX_WPROT_5 0x4801D4
+
+#define mmDMA_IF_W_S_SOB_MAX_WPROT_6 0x4801D8
+
+#define mmDMA_IF_W_S_SOB_MAX_WPROT_7 0x4801DC
+
+#define mmDMA_IF_W_S_SOB_MAX_WPROT_8 0x4801E0
+
+#define mmDMA_IF_W_S_SOB_MAX_WPROT_9 0x4801E4
+
+#define mmDMA_IF_W_S_SOB_MAX_WPROT_10 0x4801E8
+
+#define mmDMA_IF_W_S_SOB_MAX_WPROT_11 0x4801EC
+
+#define mmDMA_IF_W_S_SOB_MAX_WPROT_12 0x4801F0
+
+#define mmDMA_IF_W_S_SOB_MAX_WPROT_13 0x4801F4
+
+#define mmDMA_IF_W_S_SOB_MAX_WPROT_14 0x4801F8
+
+#define mmDMA_IF_W_S_SOB_MAX_WPROT_15 0x4801FC
+
+#define mmDMA_IF_W_S_SOB_MIN_RPRIV_0 0x480200
+
+#define mmDMA_IF_W_S_SOB_MIN_RPRIV_1 0x480204
+
+#define mmDMA_IF_W_S_SOB_MIN_RPRIV_2 0x480208
+
+#define mmDMA_IF_W_S_SOB_MIN_RPRIV_3 0x48020C
+
+#define mmDMA_IF_W_S_SOB_MIN_RPRIV_4 0x480210
+
+#define mmDMA_IF_W_S_SOB_MIN_RPRIV_5 0x480214
+
+#define mmDMA_IF_W_S_SOB_MIN_RPRIV_6 0x480218
+
+#define mmDMA_IF_W_S_SOB_MIN_RPRIV_7 0x48021C
+
+#define mmDMA_IF_W_S_SOB_MIN_RPRIV_8 0x480220
+
+#define mmDMA_IF_W_S_SOB_MIN_RPRIV_9 0x480224
+
+#define mmDMA_IF_W_S_SOB_MIN_RPRIV_10 0x480228
+
+#define mmDMA_IF_W_S_SOB_MIN_RPRIV_11 0x48022C
+
+#define mmDMA_IF_W_S_SOB_MIN_RPRIV_12 0x480230
+
+#define mmDMA_IF_W_S_SOB_MIN_RPRIV_13 0x480234
+
+#define mmDMA_IF_W_S_SOB_MIN_RPRIV_14 0x480238
+
+#define mmDMA_IF_W_S_SOB_MIN_RPRIV_15 0x48023C
+
+#define mmDMA_IF_W_S_SOB_MAX_RPRIV_0 0x480240
+
+#define mmDMA_IF_W_S_SOB_MAX_RPRIV_1 0x480244
+
+#define mmDMA_IF_W_S_SOB_MAX_RPRIV_2 0x480248
+
+#define mmDMA_IF_W_S_SOB_MAX_RPRIV_3 0x48024C
+
+#define mmDMA_IF_W_S_SOB_MAX_RPRIV_4 0x480250
+
+#define mmDMA_IF_W_S_SOB_MAX_RPRIV_5 0x480254
+
+#define mmDMA_IF_W_S_SOB_MAX_RPRIV_6 0x480258
+
+#define mmDMA_IF_W_S_SOB_MAX_RPRIV_7 0x48025C
+
+#define mmDMA_IF_W_S_SOB_MAX_RPRIV_8 0x480260
+
+#define mmDMA_IF_W_S_SOB_MAX_RPRIV_9 0x480264
+
+#define mmDMA_IF_W_S_SOB_MAX_RPRIV_10 0x480268
+
+#define mmDMA_IF_W_S_SOB_MAX_RPRIV_11 0x48026C
+
+#define mmDMA_IF_W_S_SOB_MAX_RPRIV_12 0x480270
+
+#define mmDMA_IF_W_S_SOB_MAX_RPRIV_13 0x480274
+
+#define mmDMA_IF_W_S_SOB_MAX_RPRIV_14 0x480278
+
+#define mmDMA_IF_W_S_SOB_MAX_RPRIV_15 0x48027C
+
+#define mmDMA_IF_W_S_SOB_MIN_WPRIV_0 0x480280
+
+#define mmDMA_IF_W_S_SOB_MIN_WPRIV_1 0x480284
+
+#define mmDMA_IF_W_S_SOB_MIN_WPRIV_2 0x480288
+
+#define mmDMA_IF_W_S_SOB_MIN_WPRIV_3 0x48028C
+
+#define mmDMA_IF_W_S_SOB_MIN_WPRIV_4 0x480290
+
+#define mmDMA_IF_W_S_SOB_MIN_WPRIV_5 0x480294
+
+#define mmDMA_IF_W_S_SOB_MIN_WPRIV_6 0x480298
+
+#define mmDMA_IF_W_S_SOB_MIN_WPRIV_7 0x48029C
+
+#define mmDMA_IF_W_S_SOB_MIN_WPRIV_8 0x4802A0
+
+#define mmDMA_IF_W_S_SOB_MIN_WPRIV_9 0x4802A4
+
+#define mmDMA_IF_W_S_SOB_MIN_WPRIV_10 0x4802A8
+
+#define mmDMA_IF_W_S_SOB_MIN_WPRIV_11 0x4802AC
+
+#define mmDMA_IF_W_S_SOB_MIN_WPRIV_12 0x4802B0
+
+#define mmDMA_IF_W_S_SOB_MIN_WPRIV_13 0x4802B4
+
+#define mmDMA_IF_W_S_SOB_MIN_WPRIV_14 0x4802B8
+
+#define mmDMA_IF_W_S_SOB_MIN_WPRIV_15 0x4802BC
+
+#define mmDMA_IF_W_S_SOB_MAX_WPRIV_0 0x4802C0
+
+#define mmDMA_IF_W_S_SOB_MAX_WPRIV_1 0x4802C4
+
+#define mmDMA_IF_W_S_SOB_MAX_WPRIV_2 0x4802C8
+
+#define mmDMA_IF_W_S_SOB_MAX_WPRIV_3 0x4802CC
+
+#define mmDMA_IF_W_S_SOB_MAX_WPRIV_4 0x4802D0
+
+#define mmDMA_IF_W_S_SOB_MAX_WPRIV_5 0x4802D4
+
+#define mmDMA_IF_W_S_SOB_MAX_WPRIV_6 0x4802D8
+
+#define mmDMA_IF_W_S_SOB_MAX_WPRIV_7 0x4802DC
+
+#define mmDMA_IF_W_S_SOB_MAX_WPRIV_8 0x4802E0
+
+#define mmDMA_IF_W_S_SOB_MAX_WPRIV_9 0x4802E4
+
+#define mmDMA_IF_W_S_SOB_MAX_WPRIV_10 0x4802E8
+
+#define mmDMA_IF_W_S_SOB_MAX_WPRIV_11 0x4802EC
+
+#define mmDMA_IF_W_S_SOB_MAX_WPRIV_12 0x4802F0
+
+#define mmDMA_IF_W_S_SOB_MAX_WPRIV_13 0x4802F4
+
+#define mmDMA_IF_W_S_SOB_MAX_WPRIV_14 0x4802F8
+
+#define mmDMA_IF_W_S_SOB_MAX_WPRIV_15 0x4802FC
+
+#define mmDMA_IF_W_S_DMA0_MIN_RPROT_0 0x480300
+
+#define mmDMA_IF_W_S_DMA0_MIN_RPROT_1 0x480304
+
+#define mmDMA_IF_W_S_DMA0_MIN_RPROT_2 0x480308
+
+#define mmDMA_IF_W_S_DMA0_MIN_RPROT_3 0x48030C
+
+#define mmDMA_IF_W_S_DMA0_MIN_RPROT_4 0x480310
+
+#define mmDMA_IF_W_S_DMA0_MIN_RPROT_5 0x480314
+
+#define mmDMA_IF_W_S_DMA0_MIN_RPROT_6 0x480318
+
+#define mmDMA_IF_W_S_DMA0_MIN_RPROT_7 0x48031C
+
+#define mmDMA_IF_W_S_DMA0_MIN_RPROT_8 0x480320
+
+#define mmDMA_IF_W_S_DMA0_MIN_RPROT_9 0x480324
+
+#define mmDMA_IF_W_S_DMA0_MIN_RPROT_10 0x480328
+
+#define mmDMA_IF_W_S_DMA0_MIN_RPROT_11 0x48032C
+
+#define mmDMA_IF_W_S_DMA0_MIN_RPROT_12 0x480330
+
+#define mmDMA_IF_W_S_DMA0_MIN_RPROT_13 0x480334
+
+#define mmDMA_IF_W_S_DMA0_MIN_RPROT_14 0x480338
+
+#define mmDMA_IF_W_S_DMA0_MIN_RPROT_15 0x48033C
+
+#define mmDMA_IF_W_S_DMA0_MAX_RPROT_0 0x480340
+
+#define mmDMA_IF_W_S_DMA0_MAX_RPROT_1 0x480344
+
+#define mmDMA_IF_W_S_DMA0_MAX_RPROT_2 0x480348
+
+#define mmDMA_IF_W_S_DMA0_MAX_RPROT_3 0x48034C
+
+#define mmDMA_IF_W_S_DMA0_MAX_RPROT_4 0x480350
+
+#define mmDMA_IF_W_S_DMA0_MAX_RPROT_5 0x480354
+
+#define mmDMA_IF_W_S_DMA0_MAX_RPROT_6 0x480358
+
+#define mmDMA_IF_W_S_DMA0_MAX_RPROT_7 0x48035C
+
+#define mmDMA_IF_W_S_DMA0_MAX_RPROT_8 0x480360
+
+#define mmDMA_IF_W_S_DMA0_MAX_RPROT_9 0x480364
+
+#define mmDMA_IF_W_S_DMA0_MAX_RPROT_10 0x480368
+
+#define mmDMA_IF_W_S_DMA0_MAX_RPROT_11 0x48036C
+
+#define mmDMA_IF_W_S_DMA0_MAX_RPROT_12 0x480370
+
+#define mmDMA_IF_W_S_DMA0_MAX_RPROT_13 0x480374
+
+#define mmDMA_IF_W_S_DMA0_MAX_RPROT_14 0x480378
+
+#define mmDMA_IF_W_S_DMA0_MAX_RPROT_15 0x48037C
+
+#define mmDMA_IF_W_S_DMA0_MIN_WPROT_0 0x480380
+
+#define mmDMA_IF_W_S_DMA0_MIN_WPROT_1 0x480384
+
+#define mmDMA_IF_W_S_DMA0_MIN_WPROT_2 0x480388
+
+#define mmDMA_IF_W_S_DMA0_MIN_WPROT_3 0x48038C
+
+#define mmDMA_IF_W_S_DMA0_MIN_WPROT_4 0x480390
+
+#define mmDMA_IF_W_S_DMA0_MIN_WPROT_5 0x480394
+
+#define mmDMA_IF_W_S_DMA0_MIN_WPROT_6 0x480398
+
+#define mmDMA_IF_W_S_DMA0_MIN_WPROT_7 0x48039C
+
+#define mmDMA_IF_W_S_DMA0_MIN_WPROT_8 0x4803A0
+
+#define mmDMA_IF_W_S_DMA0_MIN_WPROT_9 0x4803A4
+
+#define mmDMA_IF_W_S_DMA0_MIN_WPROT_10 0x4803A8
+
+#define mmDMA_IF_W_S_DMA0_MIN_WPROT_11 0x4803AC
+
+#define mmDMA_IF_W_S_DMA0_MIN_WPROT_12 0x4803B0
+
+#define mmDMA_IF_W_S_DMA0_MIN_WPROT_13 0x4803B4
+
+#define mmDMA_IF_W_S_DMA0_MIN_WPROT_14 0x4803B8
+
+#define mmDMA_IF_W_S_DMA0_MIN_WPROT_15 0x4803BC
+
+#define mmDMA_IF_W_S_DMA0_MAX_WPROT_0 0x4803C0
+
+#define mmDMA_IF_W_S_DMA0_MAX_WPROT_1 0x4803C4
+
+#define mmDMA_IF_W_S_DMA0_MAX_WPROT_2 0x4803C8
+
+#define mmDMA_IF_W_S_DMA0_MAX_WPROT_3 0x4803CC
+
+#define mmDMA_IF_W_S_DMA0_MAX_WPROT_4 0x4803D0
+
+#define mmDMA_IF_W_S_DMA0_MAX_WPROT_5 0x4803D4
+
+#define mmDMA_IF_W_S_DMA0_MAX_WPROT_6 0x4803D8
+
+#define mmDMA_IF_W_S_DMA0_MAX_WPROT_7 0x4803DC
+
+#define mmDMA_IF_W_S_DMA0_MAX_WPROT_8 0x4803E0
+
+#define mmDMA_IF_W_S_DMA0_MAX_WPROT_9 0x4803E4
+
+#define mmDMA_IF_W_S_DMA0_MAX_WPROT_10 0x4803E8
+
+#define mmDMA_IF_W_S_DMA0_MAX_WPROT_11 0x4803EC
+
+#define mmDMA_IF_W_S_DMA0_MAX_WPROT_12 0x4803F0
+
+#define mmDMA_IF_W_S_DMA0_MAX_WPROT_13 0x4803F4
+
+#define mmDMA_IF_W_S_DMA0_MAX_WPROT_14 0x4803F8
+
+#define mmDMA_IF_W_S_DMA0_MAX_WPROT_15 0x4803FC
+
+#define mmDMA_IF_W_S_DMA0_MIN_RPRIV_0 0x480400
+
+#define mmDMA_IF_W_S_DMA0_MIN_RPRIV_1 0x480404
+
+#define mmDMA_IF_W_S_DMA0_MIN_RPRIV_2 0x480408
+
+#define mmDMA_IF_W_S_DMA0_MIN_RPRIV_3 0x48040C
+
+#define mmDMA_IF_W_S_DMA0_MIN_RPRIV_4 0x480410
+
+#define mmDMA_IF_W_S_DMA0_MIN_RPRIV_5 0x480414
+
+#define mmDMA_IF_W_S_DMA0_MIN_RPRIV_6 0x480418
+
+#define mmDMA_IF_W_S_DMA0_MIN_RPRIV_7 0x48041C
+
+#define mmDMA_IF_W_S_DMA0_MIN_RPRIV_8 0x480420
+
+#define mmDMA_IF_W_S_DMA0_MIN_RPRIV_9 0x480424
+
+#define mmDMA_IF_W_S_DMA0_MIN_RPRIV_10 0x480428
+
+#define mmDMA_IF_W_S_DMA0_MIN_RPRIV_11 0x48042C
+
+#define mmDMA_IF_W_S_DMA0_MIN_RPRIV_12 0x480430
+
+#define mmDMA_IF_W_S_DMA0_MIN_RPRIV_13 0x480434
+
+#define mmDMA_IF_W_S_DMA0_MIN_RPRIV_14 0x480438
+
+#define mmDMA_IF_W_S_DMA0_MIN_RPRIV_15 0x48043C
+
+#define mmDMA_IF_W_S_DMA0_MAX_RPRIV_0 0x480440
+
+#define mmDMA_IF_W_S_DMA0_MAX_RPRIV_1 0x480444
+
+#define mmDMA_IF_W_S_DMA0_MAX_RPRIV_2 0x480448
+
+#define mmDMA_IF_W_S_DMA0_MAX_RPRIV_3 0x48044C
+
+#define mmDMA_IF_W_S_DMA0_MAX_RPRIV_4 0x480450
+
+#define mmDMA_IF_W_S_DMA0_MAX_RPRIV_5 0x480454
+
+#define mmDMA_IF_W_S_DMA0_MAX_RPRIV_6 0x480458
+
+#define mmDMA_IF_W_S_DMA0_MAX_RPRIV_7 0x48045C
+
+#define mmDMA_IF_W_S_DMA0_MAX_RPRIV_8 0x480460
+
+#define mmDMA_IF_W_S_DMA0_MAX_RPRIV_9 0x480464
+
+#define mmDMA_IF_W_S_DMA0_MAX_RPRIV_10 0x480468
+
+#define mmDMA_IF_W_S_DMA0_MAX_RPRIV_11 0x48046C
+
+#define mmDMA_IF_W_S_DMA0_MAX_RPRIV_12 0x480470
+
+#define mmDMA_IF_W_S_DMA0_MAX_RPRIV_13 0x480474
+
+#define mmDMA_IF_W_S_DMA0_MAX_RPRIV_14 0x480478
+
+#define mmDMA_IF_W_S_DMA0_MAX_RPRIV_15 0x48047C
+
+#define mmDMA_IF_W_S_DMA0_MIN_WPRIV_0 0x480480
+
+#define mmDMA_IF_W_S_DMA0_MIN_WPRIV_1 0x480484
+
+#define mmDMA_IF_W_S_DMA0_MIN_WPRIV_2 0x480488
+
+#define mmDMA_IF_W_S_DMA0_MIN_WPRIV_3 0x48048C
+
+#define mmDMA_IF_W_S_DMA0_MIN_WPRIV_4 0x480490
+
+#define mmDMA_IF_W_S_DMA0_MIN_WPRIV_5 0x480494
+
+#define mmDMA_IF_W_S_DMA0_MIN_WPRIV_6 0x480498
+
+#define mmDMA_IF_W_S_DMA0_MIN_WPRIV_7 0x48049C
+
+#define mmDMA_IF_W_S_DMA0_MIN_WPRIV_8 0x4804A0
+
+#define mmDMA_IF_W_S_DMA0_MIN_WPRIV_9 0x4804A4
+
+#define mmDMA_IF_W_S_DMA0_MIN_WPRIV_10 0x4804A8
+
+#define mmDMA_IF_W_S_DMA0_MIN_WPRIV_11 0x4804AC
+
+#define mmDMA_IF_W_S_DMA0_MIN_WPRIV_12 0x4804B0
+
+#define mmDMA_IF_W_S_DMA0_MIN_WPRIV_13 0x4804B4
+
+#define mmDMA_IF_W_S_DMA0_MIN_WPRIV_14 0x4804B8
+
+#define mmDMA_IF_W_S_DMA0_MIN_WPRIV_15 0x4804BC
+
+#define mmDMA_IF_W_S_DMA0_MAX_WPRIV_0 0x4804C0
+
+#define mmDMA_IF_W_S_DMA0_MAX_WPRIV_1 0x4804C4
+
+#define mmDMA_IF_W_S_DMA0_MAX_WPRIV_2 0x4804C8
+
+#define mmDMA_IF_W_S_DMA0_MAX_WPRIV_3 0x4804CC
+
+#define mmDMA_IF_W_S_DMA0_MAX_WPRIV_4 0x4804D0
+
+#define mmDMA_IF_W_S_DMA0_MAX_WPRIV_5 0x4804D4
+
+#define mmDMA_IF_W_S_DMA0_MAX_WPRIV_6 0x4804D8
+
+#define mmDMA_IF_W_S_DMA0_MAX_WPRIV_7 0x4804DC
+
+#define mmDMA_IF_W_S_DMA0_MAX_WPRIV_8 0x4804E0
+
+#define mmDMA_IF_W_S_DMA0_MAX_WPRIV_9 0x4804E4
+
+#define mmDMA_IF_W_S_DMA0_MAX_WPRIV_10 0x4804E8
+
+#define mmDMA_IF_W_S_DMA0_MAX_WPRIV_11 0x4804EC
+
+#define mmDMA_IF_W_S_DMA0_MAX_WPRIV_12 0x4804F0
+
+#define mmDMA_IF_W_S_DMA0_MAX_WPRIV_13 0x4804F4
+
+#define mmDMA_IF_W_S_DMA0_MAX_WPRIV_14 0x4804F8
+
+#define mmDMA_IF_W_S_DMA0_MAX_WPRIV_15 0x4804FC
+
+#define mmDMA_IF_W_S_DMA1_MIN_RPROT_0 0x480500
+
+#define mmDMA_IF_W_S_DMA1_MIN_RPROT_1 0x480504
+
+#define mmDMA_IF_W_S_DMA1_MIN_RPROT_2 0x480508
+
+#define mmDMA_IF_W_S_DMA1_MIN_RPROT_3 0x48050C
+
+#define mmDMA_IF_W_S_DMA1_MIN_RPROT_4 0x480510
+
+#define mmDMA_IF_W_S_DMA1_MIN_RPROT_5 0x480514
+
+#define mmDMA_IF_W_S_DMA1_MIN_RPROT_6 0x480518
+
+#define mmDMA_IF_W_S_DMA1_MIN_RPROT_7 0x48051C
+
+#define mmDMA_IF_W_S_DMA1_MIN_RPROT_8 0x480520
+
+#define mmDMA_IF_W_S_DMA1_MIN_RPROT_9 0x480524
+
+#define mmDMA_IF_W_S_DMA1_MIN_RPROT_10 0x480528
+
+#define mmDMA_IF_W_S_DMA1_MIN_RPROT_11 0x48052C
+
+#define mmDMA_IF_W_S_DMA1_MIN_RPROT_12 0x480530
+
+#define mmDMA_IF_W_S_DMA1_MIN_RPROT_13 0x480534
+
+#define mmDMA_IF_W_S_DMA1_MIN_RPROT_14 0x480538
+
+#define mmDMA_IF_W_S_DMA1_MIN_RPROT_15 0x48053C
+
+#define mmDMA_IF_W_S_DMA1_MAX_RPROT_0 0x480540
+
+#define mmDMA_IF_W_S_DMA1_MAX_RPROT_1 0x480544
+
+#define mmDMA_IF_W_S_DMA1_MAX_RPROT_2 0x480548
+
+#define mmDMA_IF_W_S_DMA1_MAX_RPROT_3 0x48054C
+
+#define mmDMA_IF_W_S_DMA1_MAX_RPROT_4 0x480550
+
+#define mmDMA_IF_W_S_DMA1_MAX_RPROT_5 0x480554
+
+#define mmDMA_IF_W_S_DMA1_MAX_RPROT_6 0x480558
+
+#define mmDMA_IF_W_S_DMA1_MAX_RPROT_7 0x48055C
+
+#define mmDMA_IF_W_S_DMA1_MAX_RPROT_8 0x480560
+
+#define mmDMA_IF_W_S_DMA1_MAX_RPROT_9 0x480564
+
+#define mmDMA_IF_W_S_DMA1_MAX_RPROT_10 0x480568
+
+#define mmDMA_IF_W_S_DMA1_MAX_RPROT_11 0x48056C
+
+#define mmDMA_IF_W_S_DMA1_MAX_RPROT_12 0x480570
+
+#define mmDMA_IF_W_S_DMA1_MAX_RPROT_13 0x480574
+
+#define mmDMA_IF_W_S_DMA1_MAX_RPROT_14 0x480578
+
+#define mmDMA_IF_W_S_DMA1_MAX_RPROT_15 0x48057C
+
+#define mmDMA_IF_W_S_DMA1_MIN_WPROT_0 0x480580
+
+#define mmDMA_IF_W_S_DMA1_MIN_WPROT_1 0x480584
+
+#define mmDMA_IF_W_S_DMA1_MIN_WPROT_2 0x480588
+
+#define mmDMA_IF_W_S_DMA1_MIN_WPROT_3 0x48058C
+
+#define mmDMA_IF_W_S_DMA1_MIN_WPROT_4 0x480590
+
+#define mmDMA_IF_W_S_DMA1_MIN_WPROT_5 0x480594
+
+#define mmDMA_IF_W_S_DMA1_MIN_WPROT_6 0x480598
+
+#define mmDMA_IF_W_S_DMA1_MIN_WPROT_7 0x48059C
+
+#define mmDMA_IF_W_S_DMA1_MIN_WPROT_8 0x4805A0
+
+#define mmDMA_IF_W_S_DMA1_MIN_WPROT_9 0x4805A4
+
+#define mmDMA_IF_W_S_DMA1_MIN_WPROT_10 0x4805A8
+
+#define mmDMA_IF_W_S_DMA1_MIN_WPROT_11 0x4805AC
+
+#define mmDMA_IF_W_S_DMA1_MIN_WPROT_12 0x4805B0
+
+#define mmDMA_IF_W_S_DMA1_MIN_WPROT_13 0x4805B4
+
+#define mmDMA_IF_W_S_DMA1_MIN_WPROT_14 0x4805B8
+
+#define mmDMA_IF_W_S_DMA1_MIN_WPROT_15 0x4805BC
+
+#define mmDMA_IF_W_S_DMA1_MAX_WPROT_0 0x4805C0
+
+#define mmDMA_IF_W_S_DMA1_MAX_WPROT_1 0x4805C4
+
+#define mmDMA_IF_W_S_DMA1_MAX_WPROT_2 0x4805C8
+
+#define mmDMA_IF_W_S_DMA1_MAX_WPROT_3 0x4805CC
+
+#define mmDMA_IF_W_S_DMA1_MAX_WPROT_4 0x4805D0
+
+#define mmDMA_IF_W_S_DMA1_MAX_WPROT_5 0x4805D4
+
+#define mmDMA_IF_W_S_DMA1_MAX_WPROT_6 0x4805D8
+
+#define mmDMA_IF_W_S_DMA1_MAX_WPROT_7 0x4805DC
+
+#define mmDMA_IF_W_S_DMA1_MAX_WPROT_8 0x4805E0
+
+#define mmDMA_IF_W_S_DMA1_MAX_WPROT_9 0x4805E4
+
+#define mmDMA_IF_W_S_DMA1_MAX_WPROT_10 0x4805E8
+
+#define mmDMA_IF_W_S_DMA1_MAX_WPROT_11 0x4805EC
+
+#define mmDMA_IF_W_S_DMA1_MAX_WPROT_12 0x4805F0
+
+#define mmDMA_IF_W_S_DMA1_MAX_WPROT_13 0x4805F4
+
+#define mmDMA_IF_W_S_DMA1_MAX_WPROT_14 0x4805F8
+
+#define mmDMA_IF_W_S_DMA1_MAX_WPROT_15 0x4805FC
+
+#define mmDMA_IF_W_S_DMA1_MIN_RPRIV_0 0x480600
+
+#define mmDMA_IF_W_S_DMA1_MIN_RPRIV_1 0x480604
+
+#define mmDMA_IF_W_S_DMA1_MIN_RPRIV_2 0x480608
+
+#define mmDMA_IF_W_S_DMA1_MIN_RPRIV_3 0x48060C
+
+#define mmDMA_IF_W_S_DMA1_MIN_RPRIV_4 0x480610
+
+#define mmDMA_IF_W_S_DMA1_MIN_RPRIV_5 0x480614
+
+#define mmDMA_IF_W_S_DMA1_MIN_RPRIV_6 0x480618
+
+#define mmDMA_IF_W_S_DMA1_MIN_RPRIV_7 0x48061C
+
+#define mmDMA_IF_W_S_DMA1_MIN_RPRIV_8 0x480620
+
+#define mmDMA_IF_W_S_DMA1_MIN_RPRIV_9 0x480624
+
+#define mmDMA_IF_W_S_DMA1_MIN_RPRIV_10 0x480628
+
+#define mmDMA_IF_W_S_DMA1_MIN_RPRIV_11 0x48062C
+
+#define mmDMA_IF_W_S_DMA1_MIN_RPRIV_12 0x480630
+
+#define mmDMA_IF_W_S_DMA1_MIN_RPRIV_13 0x480634
+
+#define mmDMA_IF_W_S_DMA1_MIN_RPRIV_14 0x480638
+
+#define mmDMA_IF_W_S_DMA1_MIN_RPRIV_15 0x48063C
+
+#define mmDMA_IF_W_S_DMA1_MAX_RPRIV_0 0x480640
+
+#define mmDMA_IF_W_S_DMA1_MAX_RPRIV_1 0x480644
+
+#define mmDMA_IF_W_S_DMA1_MAX_RPRIV_2 0x480648
+
+#define mmDMA_IF_W_S_DMA1_MAX_RPRIV_3 0x48064C
+
+#define mmDMA_IF_W_S_DMA1_MAX_RPRIV_4 0x480650
+
+#define mmDMA_IF_W_S_DMA1_MAX_RPRIV_5 0x480654
+
+#define mmDMA_IF_W_S_DMA1_MAX_RPRIV_6 0x480658
+
+#define mmDMA_IF_W_S_DMA1_MAX_RPRIV_7 0x48065C
+
+#define mmDMA_IF_W_S_DMA1_MAX_RPRIV_8 0x480660
+
+#define mmDMA_IF_W_S_DMA1_MAX_RPRIV_9 0x480664
+
+#define mmDMA_IF_W_S_DMA1_MAX_RPRIV_10 0x480668
+
+#define mmDMA_IF_W_S_DMA1_MAX_RPRIV_11 0x48066C
+
+#define mmDMA_IF_W_S_DMA1_MAX_RPRIV_12 0x480670
+
+#define mmDMA_IF_W_S_DMA1_MAX_RPRIV_13 0x480674
+
+#define mmDMA_IF_W_S_DMA1_MAX_RPRIV_14 0x480678
+
+#define mmDMA_IF_W_S_DMA1_MAX_RPRIV_15 0x48067C
+
+#define mmDMA_IF_W_S_DMA1_MIN_WPRIV_0 0x480680
+
+#define mmDMA_IF_W_S_DMA1_MIN_WPRIV_1 0x480684
+
+#define mmDMA_IF_W_S_DMA1_MIN_WPRIV_2 0x480688
+
+#define mmDMA_IF_W_S_DMA1_MIN_WPRIV_3 0x48068C
+
+#define mmDMA_IF_W_S_DMA1_MIN_WPRIV_4 0x480690
+
+#define mmDMA_IF_W_S_DMA1_MIN_WPRIV_5 0x480694
+
+#define mmDMA_IF_W_S_DMA1_MIN_WPRIV_6 0x480698
+
+#define mmDMA_IF_W_S_DMA1_MIN_WPRIV_7 0x48069C
+
+#define mmDMA_IF_W_S_DMA1_MIN_WPRIV_8 0x4806A0
+
+#define mmDMA_IF_W_S_DMA1_MIN_WPRIV_9 0x4806A4
+
+#define mmDMA_IF_W_S_DMA1_MIN_WPRIV_10 0x4806A8
+
+#define mmDMA_IF_W_S_DMA1_MIN_WPRIV_11 0x4806AC
+
+#define mmDMA_IF_W_S_DMA1_MIN_WPRIV_12 0x4806B0
+
+#define mmDMA_IF_W_S_DMA1_MIN_WPRIV_13 0x4806B4
+
+#define mmDMA_IF_W_S_DMA1_MIN_WPRIV_14 0x4806B8
+
+#define mmDMA_IF_W_S_DMA1_MIN_WPRIV_15 0x4806BC
+
+#define mmDMA_IF_W_S_DMA1_MAX_WPRIV_0 0x4806C0
+
+#define mmDMA_IF_W_S_DMA1_MAX_WPRIV_1 0x4806C4
+
+#define mmDMA_IF_W_S_DMA1_MAX_WPRIV_2 0x4806C8
+
+#define mmDMA_IF_W_S_DMA1_MAX_WPRIV_3 0x4806CC
+
+#define mmDMA_IF_W_S_DMA1_MAX_WPRIV_4 0x4806D0
+
+#define mmDMA_IF_W_S_DMA1_MAX_WPRIV_5 0x4806D4
+
+#define mmDMA_IF_W_S_DMA1_MAX_WPRIV_6 0x4806D8
+
+#define mmDMA_IF_W_S_DMA1_MAX_WPRIV_7 0x4806DC
+
+#define mmDMA_IF_W_S_DMA1_MAX_WPRIV_8 0x4806E0
+
+#define mmDMA_IF_W_S_DMA1_MAX_WPRIV_9 0x4806E4
+
+#define mmDMA_IF_W_S_DMA1_MAX_WPRIV_10 0x4806E8
+
+#define mmDMA_IF_W_S_DMA1_MAX_WPRIV_11 0x4806EC
+
+#define mmDMA_IF_W_S_DMA1_MAX_WPRIV_12 0x4806F0
+
+#define mmDMA_IF_W_S_DMA1_MAX_WPRIV_13 0x4806F4
+
+#define mmDMA_IF_W_S_DMA1_MAX_WPRIV_14 0x4806F8
+
+#define mmDMA_IF_W_S_DMA1_MAX_WPRIV_15 0x4806FC
+
+#define mmDMA_IF_W_S_SOB_HIT_RPROT 0x480700
+
+#define mmDMA_IF_W_S_SOB_HIT_WPROT 0x480704
+
+#define mmDMA_IF_W_S_SOB_HIT_RPRIV 0x48070C
+
+#define mmDMA_IF_W_S_SOB_HIT_WPRIV 0x480710
+
+#define mmDMA_IF_W_S_DMA0_HIT_RPROT 0x48071C
+
+#define mmDMA_IF_W_S_DMA0_HIT_WPROT 0x480720
+
+#define mmDMA_IF_W_S_DMA0_HIT_RPRIV 0x480724
+
+#define mmDMA_IF_W_S_DMA0_HIT_WPRIV 0x480728
+
+#define mmDMA_IF_W_S_DMA1_HIT_RPROT 0x480730
+
+#define mmDMA_IF_W_S_DMA1_HIT_WPROT 0x480734
+
+#define mmDMA_IF_W_S_DMA1_HIT_RPRIV 0x480738
+
+#define mmDMA_IF_W_S_DMA1_HIT_WPRIV 0x48073C
+
+#define mmDMA_IF_W_S_HBM_BIN 0x480800
+
+#define mmDMA_IF_W_S_MME_BIN 0x480804
+
+#define mmDMA_IF_W_S_TPC_BIN 0x480808
+
+#define mmDMA_IF_W_S_DMA_BIN 0x48080C
+
+#define mmDMA_IF_W_S_SOB_CG_EN 0x480810
+
+#define mmDMA_IF_W_S_HBM_I2C_ADDR_0 0x480820
+
+#define mmDMA_IF_W_S_HBM_I2C_ADDR_1 0x480824
+
+#define mmDMA_IF_W_S_HBM_I2C_ADDR_2 0x480828
+
+#define mmDMA_IF_W_S_HBM_I2C_ADDR_3 0x48082C
+
+#define mmDMA_IF_W_S_HBM_I2C_ADDR_4 0x480830
+
+#define mmDMA_IF_W_S_HBM_MISC 0x480834
+
+#endif /* ASIC_REG_DMA_IF_W_S_REGS_H_ */
diff --git a/drivers/accel/habanalabs/include/gaudi/asic_reg/gaudi_blocks.h b/drivers/accel/habanalabs/include/gaudi/asic_reg/gaudi_blocks.h
new file mode 100644
index 0000000000..c7596aac7a
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi/asic_reg/gaudi_blocks.h
@@ -0,0 +1,4974 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2016-2018 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ ** DO NOT EDIT BELOW **
+ ************************************/
+
+#ifndef GAUDI_BLOCKS_H_
+#define GAUDI_BLOCKS_H_
+
+#define mmNIC0_PHY0_BASE 0x0ull
+#define NIC0_PHY0_MAX_OFFSET 0x9F13
+#define mmMME0_ACC_BASE 0x7FFC020000ull
+#define MME0_ACC_MAX_OFFSET 0x5C00
+#define MME0_ACC_SECTION 0x20000
+#define mmMME0_SBAB_BASE 0x7FFC040000ull
+#define MME0_SBAB_MAX_OFFSET 0x5800
+#define MME0_SBAB_SECTION 0x1000
+#define mmMME0_PRTN_BASE 0x7FFC041000ull
+#define MME0_PRTN_MAX_OFFSET 0x5000
+#define MME0_PRTN_SECTION 0x1F000
+#define mmMME0_CTRL_BASE 0x7FFC060000ull
+#define MME0_CTRL_MAX_OFFSET 0xDA80
+#define MME0_CTRL_SECTION 0x8000
+#define mmARCH_MME0_CTRL_BASE 0x7FFC060008ull
+#define ARCH_MME0_CTRL_MAX_OFFSET 0x3400
+#define ARCH_MME0_CTRL_SECTION 0x3400
+#define mmARCH_TENSOR_S_MME0_CTRL_BASE 0x7FFC06003Cull
+#define ARCH_TENSOR_S_MME0_CTRL_MAX_OFFSET 0x4C00
+#define ARCH_TENSOR_S_MME0_CTRL_SECTION 0x4C00
+#define mmARCH_AGU_S_MME0_CTRL_BASE 0x7FFC060088ull
+#define ARCH_AGU_S_MME0_CTRL_MAX_OFFSET 0x2400
+#define ARCH_AGU_S_MME0_CTRL_SECTION 0x2400
+#define mmARCH_TENSOR_L_MME0_CTRL_BASE 0x7FFC0600ACull
+#define ARCH_TENSOR_L_MME0_CTRL_MAX_OFFSET 0x4C00
+#define ARCH_TENSOR_L_MME0_CTRL_SECTION 0x4C00
+#define mmARCH_AGU_L_LOCAL_MME0_CTRL_BASE 0x7FFC0600F8ull
+#define ARCH_AGU_L_LOCAL_MME0_CTRL_MAX_OFFSET 0x2400
+#define ARCH_AGU_L_LOCAL_MME0_CTRL_SECTION 0x2400
+#define mmARCH_AGU_L_REMOTE_MME0_CTRL_BASE 0x7FFC06011Cull
+#define ARCH_AGU_L_REMOTE_MME0_CTRL_MAX_OFFSET 0x2400
+#define ARCH_AGU_L_REMOTE_MME0_CTRL_SECTION 0x2400
+#define mmARCH_TENSOR_O_MME0_CTRL_BASE 0x7FFC060140ull
+#define ARCH_TENSOR_O_MME0_CTRL_MAX_OFFSET 0x4C00
+#define ARCH_TENSOR_O_MME0_CTRL_SECTION 0x4C00
+#define mmARCH_AGU_O_LOCAL_MME0_CTRL_BASE 0x7FFC06018Cull
+#define ARCH_AGU_O_LOCAL_MME0_CTRL_MAX_OFFSET 0x2400
+#define ARCH_AGU_O_LOCAL_MME0_CTRL_SECTION 0x2400
+#define mmARCH_AGU_O_REMOTE_MME0_CTRL_BASE 0x7FFC0601B0ull
+#define ARCH_AGU_O_REMOTE_MME0_CTRL_MAX_OFFSET 0x2400
+#define ARCH_AGU_O_REMOTE_MME0_CTRL_SECTION 0x2400
+#define mmARCH_DESC_MME0_CTRL_BASE 0x7FFC0601D4ull
+#define ARCH_DESC_MME0_CTRL_MAX_OFFSET 0x5400
+#define ARCH_DESC_MME0_CTRL_SECTION 0x2340
+#define mmSHADOW_0_MME0_CTRL_BASE 0x7FFC060408ull
+#define SHADOW_0_MME0_CTRL_MAX_OFFSET 0x3400
+#define SHADOW_0_MME0_CTRL_SECTION 0x3400
+#define mmSHADOW_0_TENSOR_S_MME0_CTRL_BASE 0x7FFC06043Cull
+#define SHADOW_0_TENSOR_S_MME0_CTRL_MAX_OFFSET 0x4C00
+#define SHADOW_0_TENSOR_S_MME0_CTRL_SECTION 0x4C00
+#define mmSHADOW_0_AGU_S_MME0_CTRL_BASE 0x7FFC060488ull
+#define SHADOW_0_AGU_S_MME0_CTRL_MAX_OFFSET 0x2400
+#define SHADOW_0_AGU_S_MME0_CTRL_SECTION 0x2400
+#define mmSHADOW_0_TENSOR_L_MME0_CTRL_BASE 0x7FFC0604ACull
+#define SHADOW_0_TENSOR_L_MME0_CTRL_MAX_OFFSET 0x4C00
+#define SHADOW_0_TENSOR_L_MME0_CTRL_SECTION 0x4C00
+#define mmSHADOW_0_AGU_L_LOCAL_MME0_CTRL_BASE 0x7FFC0604F8ull
+#define SHADOW_0_AGU_L_LOCAL_MME0_CTRL_MAX_OFFSET 0x2400
+#define SHADOW_0_AGU_L_LOCAL_MME0_CTRL_SECTION 0x2400
+#define mmSHADOW_0_AGU_L_REMOTE_MME0_CTRL_BASE 0x7FFC06051Cull
+#define SHADOW_0_AGU_L_REMOTE_MME0_CTRL_MAX_OFFSET 0x2400
+#define SHADOW_0_AGU_L_REMOTE_MME0_CTRL_SECTION 0x2400
+#define mmSHADOW_0_TENSOR_O_MME0_CTRL_BASE 0x7FFC060540ull
+#define SHADOW_0_TENSOR_O_MME0_CTRL_MAX_OFFSET 0x4C00
+#define SHADOW_0_TENSOR_O_MME0_CTRL_SECTION 0x4C00
+#define mmSHADOW_0_AGU_O_LOCAL_MME0_CTRL_BASE 0x7FFC06058Cull
+#define SHADOW_0_AGU_O_LOCAL_MME0_CTRL_MAX_OFFSET 0x2400
+#define SHADOW_0_AGU_O_LOCAL_MME0_CTRL_SECTION 0x2400
+#define mmSHADOW_0_AGU_O_REMOTE_MME0_CTRL_BASE 0x7FFC0605B0ull
+#define SHADOW_0_AGU_O_REMOTE_MME0_CTRL_MAX_OFFSET 0x2400
+#define SHADOW_0_AGU_O_REMOTE_MME0_CTRL_SECTION 0x2400
+#define mmSHADOW_0_DESC_MME0_CTRL_BASE 0x7FFC0605D4ull
+#define SHADOW_0_DESC_MME0_CTRL_MAX_OFFSET 0x5400
+#define SHADOW_0_DESC_MME0_CTRL_SECTION 0xB400
+#define mmSHADOW_1_MME0_CTRL_BASE 0x7FFC060688ull
+#define SHADOW_1_MME0_CTRL_MAX_OFFSET 0x3400
+#define SHADOW_1_MME0_CTRL_SECTION 0x3400
+#define mmSHADOW_1_TENSOR_S_MME0_CTRL_BASE 0x7FFC0606BCull
+#define SHADOW_1_TENSOR_S_MME0_CTRL_MAX_OFFSET 0x4C00
+#define SHADOW_1_TENSOR_S_MME0_CTRL_SECTION 0x4C00
+#define mmSHADOW_1_AGU_S_MME0_CTRL_BASE 0x7FFC060708ull
+#define SHADOW_1_AGU_S_MME0_CTRL_MAX_OFFSET 0x2400
+#define SHADOW_1_AGU_S_MME0_CTRL_SECTION 0x2400
+#define mmSHADOW_1_TENSOR_L_MME0_CTRL_BASE 0x7FFC06072Cull
+#define SHADOW_1_TENSOR_L_MME0_CTRL_MAX_OFFSET 0x4C00
+#define SHADOW_1_TENSOR_L_MME0_CTRL_SECTION 0x4C00
+#define mmSHADOW_1_AGU_L_LOCAL_MME0_CTRL_BASE 0x7FFC060778ull
+#define SHADOW_1_AGU_L_LOCAL_MME0_CTRL_MAX_OFFSET 0x2400
+#define SHADOW_1_AGU_L_LOCAL_MME0_CTRL_SECTION 0x2400
+#define mmSHADOW_1_AGU_L_REMOTE_MME0_CTRL_BASE 0x7FFC06079Cull
+#define SHADOW_1_AGU_L_REMOTE_MME0_CTRL_MAX_OFFSET 0x2400
+#define SHADOW_1_AGU_L_REMOTE_MME0_CTRL_SECTION 0x2400
+#define mmSHADOW_1_TENSOR_O_MME0_CTRL_BASE 0x7FFC0607C0ull
+#define SHADOW_1_TENSOR_O_MME0_CTRL_MAX_OFFSET 0x4C00
+#define SHADOW_1_TENSOR_O_MME0_CTRL_SECTION 0x4C00
+#define mmSHADOW_1_AGU_O_LOCAL_MME0_CTRL_BASE 0x7FFC06080Cull
+#define SHADOW_1_AGU_O_LOCAL_MME0_CTRL_MAX_OFFSET 0x2400
+#define SHADOW_1_AGU_O_LOCAL_MME0_CTRL_SECTION 0x2400
+#define mmSHADOW_1_AGU_O_REMOTE_MME0_CTRL_BASE 0x7FFC060830ull
+#define SHADOW_1_AGU_O_REMOTE_MME0_CTRL_MAX_OFFSET 0x2400
+#define SHADOW_1_AGU_O_REMOTE_MME0_CTRL_SECTION 0x2400
+#define mmSHADOW_1_DESC_MME0_CTRL_BASE 0x7FFC060854ull
+#define SHADOW_1_DESC_MME0_CTRL_MAX_OFFSET 0x5400
+#define SHADOW_1_DESC_MME0_CTRL_SECTION 0xB400
+#define mmSHADOW_2_MME0_CTRL_BASE 0x7FFC060908ull
+#define SHADOW_2_MME0_CTRL_MAX_OFFSET 0x3400
+#define SHADOW_2_MME0_CTRL_SECTION 0x3400
+#define mmSHADOW_2_TENSOR_S_MME0_CTRL_BASE 0x7FFC06093Cull
+#define SHADOW_2_TENSOR_S_MME0_CTRL_MAX_OFFSET 0x4C00
+#define SHADOW_2_TENSOR_S_MME0_CTRL_SECTION 0x4C00
+#define mmSHADOW_2_AGU_S_MME0_CTRL_BASE 0x7FFC060988ull
+#define SHADOW_2_AGU_S_MME0_CTRL_MAX_OFFSET 0x2400
+#define SHADOW_2_AGU_S_MME0_CTRL_SECTION 0x2400
+#define mmSHADOW_2_TENSOR_L_MME0_CTRL_BASE 0x7FFC0609ACull
+#define SHADOW_2_TENSOR_L_MME0_CTRL_MAX_OFFSET 0x4C00
+#define SHADOW_2_TENSOR_L_MME0_CTRL_SECTION 0x4C00
+#define mmSHADOW_2_AGU_L_LOCAL_MME0_CTRL_BASE 0x7FFC0609F8ull
+#define SHADOW_2_AGU_L_LOCAL_MME0_CTRL_MAX_OFFSET 0x2400
+#define SHADOW_2_AGU_L_LOCAL_MME0_CTRL_SECTION 0x2400
+#define mmSHADOW_2_AGU_L_REMOTE_MME0_CTRL_BASE 0x7FFC060A1Cull
+#define SHADOW_2_AGU_L_REMOTE_MME0_CTRL_MAX_OFFSET 0x2400
+#define SHADOW_2_AGU_L_REMOTE_MME0_CTRL_SECTION 0x2400
+#define mmSHADOW_2_TENSOR_O_MME0_CTRL_BASE 0x7FFC060A40ull
+#define SHADOW_2_TENSOR_O_MME0_CTRL_MAX_OFFSET 0x4C00
+#define SHADOW_2_TENSOR_O_MME0_CTRL_SECTION 0x4C00
+#define mmSHADOW_2_AGU_O_LOCAL_MME0_CTRL_BASE 0x7FFC060A8Cull
+#define SHADOW_2_AGU_O_LOCAL_MME0_CTRL_MAX_OFFSET 0x2400
+#define SHADOW_2_AGU_O_LOCAL_MME0_CTRL_SECTION 0x2400
+#define mmSHADOW_2_AGU_O_REMOTE_MME0_CTRL_BASE 0x7FFC060AB0ull
+#define SHADOW_2_AGU_O_REMOTE_MME0_CTRL_MAX_OFFSET 0x2400
+#define SHADOW_2_AGU_O_REMOTE_MME0_CTRL_SECTION 0x2400
+#define mmSHADOW_2_DESC_MME0_CTRL_BASE 0x7FFC060AD4ull
+#define SHADOW_2_DESC_MME0_CTRL_MAX_OFFSET 0x5400
+#define SHADOW_2_DESC_MME0_CTRL_SECTION 0xB400
+#define mmSHADOW_3_MME0_CTRL_BASE 0x7FFC060B88ull
+#define SHADOW_3_MME0_CTRL_MAX_OFFSET 0x3400
+#define SHADOW_3_MME0_CTRL_SECTION 0x3400
+#define mmSHADOW_3_TENSOR_S_MME0_CTRL_BASE 0x7FFC060BBCull
+#define SHADOW_3_TENSOR_S_MME0_CTRL_MAX_OFFSET 0x4C00
+#define SHADOW_3_TENSOR_S_MME0_CTRL_SECTION 0x4C00
+#define mmSHADOW_3_AGU_S_MME0_CTRL_BASE 0x7FFC060C08ull
+#define SHADOW_3_AGU_S_MME0_CTRL_MAX_OFFSET 0x2400
+#define SHADOW_3_AGU_S_MME0_CTRL_SECTION 0x2400
+#define mmSHADOW_3_TENSOR_L_MME0_CTRL_BASE 0x7FFC060C2Cull
+#define SHADOW_3_TENSOR_L_MME0_CTRL_MAX_OFFSET 0x4C00
+#define SHADOW_3_TENSOR_L_MME0_CTRL_SECTION 0x4C00
+#define mmSHADOW_3_AGU_L_LOCAL_MME0_CTRL_BASE 0x7FFC060C78ull
+#define SHADOW_3_AGU_L_LOCAL_MME0_CTRL_MAX_OFFSET 0x2400
+#define SHADOW_3_AGU_L_LOCAL_MME0_CTRL_SECTION 0x2400
+#define mmSHADOW_3_AGU_L_REMOTE_MME0_CTRL_BASE 0x7FFC060C9Cull
+#define SHADOW_3_AGU_L_REMOTE_MME0_CTRL_MAX_OFFSET 0x2400
+#define SHADOW_3_AGU_L_REMOTE_MME0_CTRL_SECTION 0x2400
+#define mmSHADOW_3_TENSOR_O_MME0_CTRL_BASE 0x7FFC060CC0ull
+#define SHADOW_3_TENSOR_O_MME0_CTRL_MAX_OFFSET 0x4C00
+#define SHADOW_3_TENSOR_O_MME0_CTRL_SECTION 0x4C00
+#define mmSHADOW_3_AGU_O_LOCAL_MME0_CTRL_BASE 0x7FFC060D0Cull
+#define SHADOW_3_AGU_O_LOCAL_MME0_CTRL_MAX_OFFSET 0x2400
+#define SHADOW_3_AGU_O_LOCAL_MME0_CTRL_SECTION 0x2400
+#define mmSHADOW_3_AGU_O_REMOTE_MME0_CTRL_BASE 0x7FFC060D30ull
+#define SHADOW_3_AGU_O_REMOTE_MME0_CTRL_MAX_OFFSET 0x2400
+#define SHADOW_3_AGU_O_REMOTE_MME0_CTRL_SECTION 0x2400
+#define mmSHADOW_3_DESC_MME0_CTRL_BASE 0x7FFC060D54ull
+#define SHADOW_3_DESC_MME0_CTRL_MAX_OFFSET 0x5400
+#define SHADOW_3_DESC_MME0_CTRL_SECTION 0x72AC
+#define mmMME0_QM_BASE 0x7FFC068000ull
+#define MME0_QM_MAX_OFFSET 0xD040
+#define MME0_QM_SECTION 0x38000
+#define mmMME1_ACC_BASE 0x7FFC0A0000ull
+#define MME1_ACC_MAX_OFFSET 0x5C00
+#define MME1_ACC_SECTION 0x20000
+#define mmMME1_SBAB_BASE 0x7FFC0C0000ull
+#define MME1_SBAB_MAX_OFFSET 0x5800
+#define MME1_SBAB_SECTION 0x1000
+#define mmMME1_PRTN_BASE 0x7FFC0C1000ull
+#define MME1_PRTN_MAX_OFFSET 0x5000
+#define MME1_PRTN_SECTION 0x1F000
+#define mmMME1_CTRL_BASE 0x7FFC0E0000ull
+#define MME1_CTRL_MAX_OFFSET 0xDA80
+#define MME1_CTRL_SECTION 0x8000
+#define mmARCH_MME1_CTRL_BASE 0x7FFC0E0008ull
+#define ARCH_MME1_CTRL_MAX_OFFSET 0x3400
+#define ARCH_MME1_CTRL_SECTION 0x3400
+#define mmARCH_TENSOR_S_MME1_CTRL_BASE 0x7FFC0E003Cull
+#define ARCH_TENSOR_S_MME1_CTRL_MAX_OFFSET 0x4C00
+#define ARCH_TENSOR_S_MME1_CTRL_SECTION 0x4C00
+#define mmARCH_AGU_S_MME1_CTRL_BASE 0x7FFC0E0088ull
+#define ARCH_AGU_S_MME1_CTRL_MAX_OFFSET 0x2400
+#define ARCH_AGU_S_MME1_CTRL_SECTION 0x2400
+#define mmARCH_TENSOR_L_MME1_CTRL_BASE 0x7FFC0E00ACull
+#define ARCH_TENSOR_L_MME1_CTRL_MAX_OFFSET 0x4C00
+#define ARCH_TENSOR_L_MME1_CTRL_SECTION 0x4C00
+#define mmARCH_AGU_L_LOCAL_MME1_CTRL_BASE 0x7FFC0E00F8ull
+#define ARCH_AGU_L_LOCAL_MME1_CTRL_MAX_OFFSET 0x2400
+#define ARCH_AGU_L_LOCAL_MME1_CTRL_SECTION 0x2400
+#define mmARCH_AGU_L_REMOTE_MME1_CTRL_BASE 0x7FFC0E011Cull
+#define ARCH_AGU_L_REMOTE_MME1_CTRL_MAX_OFFSET 0x2400
+#define ARCH_AGU_L_REMOTE_MME1_CTRL_SECTION 0x2400
+#define mmARCH_TENSOR_O_MME1_CTRL_BASE 0x7FFC0E0140ull
+#define ARCH_TENSOR_O_MME1_CTRL_MAX_OFFSET 0x4C00
+#define ARCH_TENSOR_O_MME1_CTRL_SECTION 0x4C00
+#define mmARCH_AGU_O_LOCAL_MME1_CTRL_BASE 0x7FFC0E018Cull
+#define ARCH_AGU_O_LOCAL_MME1_CTRL_MAX_OFFSET 0x2400
+#define ARCH_AGU_O_LOCAL_MME1_CTRL_SECTION 0x2400
+#define mmARCH_AGU_O_REMOTE_MME1_CTRL_BASE 0x7FFC0E01B0ull
+#define ARCH_AGU_O_REMOTE_MME1_CTRL_MAX_OFFSET 0x2400
+#define ARCH_AGU_O_REMOTE_MME1_CTRL_SECTION 0x2400
+#define mmARCH_DESC_MME1_CTRL_BASE 0x7FFC0E01D4ull
+#define ARCH_DESC_MME1_CTRL_MAX_OFFSET 0x5400
+#define ARCH_DESC_MME1_CTRL_SECTION 0x2340
+#define mmSHADOW_0_MME1_CTRL_BASE 0x7FFC0E0408ull
+#define SHADOW_0_MME1_CTRL_MAX_OFFSET 0x3400
+#define SHADOW_0_MME1_CTRL_SECTION 0x3400
+#define mmSHADOW_0_TENSOR_S_MME1_CTRL_BASE 0x7FFC0E043Cull
+#define SHADOW_0_TENSOR_S_MME1_CTRL_MAX_OFFSET 0x4C00
+#define SHADOW_0_TENSOR_S_MME1_CTRL_SECTION 0x4C00
+#define mmSHADOW_0_AGU_S_MME1_CTRL_BASE 0x7FFC0E0488ull
+#define SHADOW_0_AGU_S_MME1_CTRL_MAX_OFFSET 0x2400
+#define SHADOW_0_AGU_S_MME1_CTRL_SECTION 0x2400
+#define mmSHADOW_0_TENSOR_L_MME1_CTRL_BASE 0x7FFC0E04ACull
+#define SHADOW_0_TENSOR_L_MME1_CTRL_MAX_OFFSET 0x4C00
+#define SHADOW_0_TENSOR_L_MME1_CTRL_SECTION 0x4C00
+#define mmSHADOW_0_AGU_L_LOCAL_MME1_CTRL_BASE 0x7FFC0E04F8ull
+#define SHADOW_0_AGU_L_LOCAL_MME1_CTRL_MAX_OFFSET 0x2400
+#define SHADOW_0_AGU_L_LOCAL_MME1_CTRL_SECTION 0x2400
+#define mmSHADOW_0_AGU_L_REMOTE_MME1_CTRL_BASE 0x7FFC0E051Cull
+#define SHADOW_0_AGU_L_REMOTE_MME1_CTRL_MAX_OFFSET 0x2400
+#define SHADOW_0_AGU_L_REMOTE_MME1_CTRL_SECTION 0x2400
+#define mmSHADOW_0_TENSOR_O_MME1_CTRL_BASE 0x7FFC0E0540ull
+#define SHADOW_0_TENSOR_O_MME1_CTRL_MAX_OFFSET 0x4C00
+#define SHADOW_0_TENSOR_O_MME1_CTRL_SECTION 0x4C00
+#define mmSHADOW_0_AGU_O_LOCAL_MME1_CTRL_BASE 0x7FFC0E058Cull
+#define SHADOW_0_AGU_O_LOCAL_MME1_CTRL_MAX_OFFSET 0x2400
+#define SHADOW_0_AGU_O_LOCAL_MME1_CTRL_SECTION 0x2400
+#define mmSHADOW_0_AGU_O_REMOTE_MME1_CTRL_BASE 0x7FFC0E05B0ull
+#define SHADOW_0_AGU_O_REMOTE_MME1_CTRL_MAX_OFFSET 0x2400
+#define SHADOW_0_AGU_O_REMOTE_MME1_CTRL_SECTION 0x2400
+#define mmSHADOW_0_DESC_MME1_CTRL_BASE 0x7FFC0E05D4ull
+#define SHADOW_0_DESC_MME1_CTRL_MAX_OFFSET 0x5400
+#define SHADOW_0_DESC_MME1_CTRL_SECTION 0xB400
+#define mmSHADOW_1_MME1_CTRL_BASE 0x7FFC0E0688ull
+#define SHADOW_1_MME1_CTRL_MAX_OFFSET 0x3400
+#define SHADOW_1_MME1_CTRL_SECTION 0x3400
+#define mmSHADOW_1_TENSOR_S_MME1_CTRL_BASE 0x7FFC0E06BCull
+#define SHADOW_1_TENSOR_S_MME1_CTRL_MAX_OFFSET 0x4C00
+#define SHADOW_1_TENSOR_S_MME1_CTRL_SECTION 0x4C00
+#define mmSHADOW_1_AGU_S_MME1_CTRL_BASE 0x7FFC0E0708ull
+#define SHADOW_1_AGU_S_MME1_CTRL_MAX_OFFSET 0x2400
+#define SHADOW_1_AGU_S_MME1_CTRL_SECTION 0x2400
+#define mmSHADOW_1_TENSOR_L_MME1_CTRL_BASE 0x7FFC0E072Cull
+#define SHADOW_1_TENSOR_L_MME1_CTRL_MAX_OFFSET 0x4C00
+#define SHADOW_1_TENSOR_L_MME1_CTRL_SECTION 0x4C00
+#define mmSHADOW_1_AGU_L_LOCAL_MME1_CTRL_BASE 0x7FFC0E0778ull
+#define SHADOW_1_AGU_L_LOCAL_MME1_CTRL_MAX_OFFSET 0x2400
+#define SHADOW_1_AGU_L_LOCAL_MME1_CTRL_SECTION 0x2400
+#define mmSHADOW_1_AGU_L_REMOTE_MME1_CTRL_BASE 0x7FFC0E079Cull
+#define SHADOW_1_AGU_L_REMOTE_MME1_CTRL_MAX_OFFSET 0x2400
+#define SHADOW_1_AGU_L_REMOTE_MME1_CTRL_SECTION 0x2400
+#define mmSHADOW_1_TENSOR_O_MME1_CTRL_BASE 0x7FFC0E07C0ull
+#define SHADOW_1_TENSOR_O_MME1_CTRL_MAX_OFFSET 0x4C00
+#define SHADOW_1_TENSOR_O_MME1_CTRL_SECTION 0x4C00
+#define mmSHADOW_1_AGU_O_LOCAL_MME1_CTRL_BASE 0x7FFC0E080Cull
+#define SHADOW_1_AGU_O_LOCAL_MME1_CTRL_MAX_OFFSET 0x2400
+#define SHADOW_1_AGU_O_LOCAL_MME1_CTRL_SECTION 0x2400
+#define mmSHADOW_1_AGU_O_REMOTE_MME1_CTRL_BASE 0x7FFC0E0830ull
+#define SHADOW_1_AGU_O_REMOTE_MME1_CTRL_MAX_OFFSET 0x2400
+#define SHADOW_1_AGU_O_REMOTE_MME1_CTRL_SECTION 0x2400
+#define mmSHADOW_1_DESC_MME1_CTRL_BASE 0x7FFC0E0854ull
+#define SHADOW_1_DESC_MME1_CTRL_MAX_OFFSET 0x5400
+#define SHADOW_1_DESC_MME1_CTRL_SECTION 0xB400
+#define mmSHADOW_2_MME1_CTRL_BASE 0x7FFC0E0908ull
+#define SHADOW_2_MME1_CTRL_MAX_OFFSET 0x3400
+#define SHADOW_2_MME1_CTRL_SECTION 0x3400
+#define mmSHADOW_2_TENSOR_S_MME1_CTRL_BASE 0x7FFC0E093Cull
+#define SHADOW_2_TENSOR_S_MME1_CTRL_MAX_OFFSET 0x4C00
+#define SHADOW_2_TENSOR_S_MME1_CTRL_SECTION 0x4C00
+#define mmSHADOW_2_AGU_S_MME1_CTRL_BASE 0x7FFC0E0988ull
+#define SHADOW_2_AGU_S_MME1_CTRL_MAX_OFFSET 0x2400
+#define SHADOW_2_AGU_S_MME1_CTRL_SECTION 0x2400
+#define mmSHADOW_2_TENSOR_L_MME1_CTRL_BASE 0x7FFC0E09ACull
+#define SHADOW_2_TENSOR_L_MME1_CTRL_MAX_OFFSET 0x4C00
+#define SHADOW_2_TENSOR_L_MME1_CTRL_SECTION 0x4C00
+#define mmSHADOW_2_AGU_L_LOCAL_MME1_CTRL_BASE 0x7FFC0E09F8ull
+#define SHADOW_2_AGU_L_LOCAL_MME1_CTRL_MAX_OFFSET 0x2400
+#define SHADOW_2_AGU_L_LOCAL_MME1_CTRL_SECTION 0x2400
+#define mmSHADOW_2_AGU_L_REMOTE_MME1_CTRL_BASE 0x7FFC0E0A1Cull
+#define SHADOW_2_AGU_L_REMOTE_MME1_CTRL_MAX_OFFSET 0x2400
+#define SHADOW_2_AGU_L_REMOTE_MME1_CTRL_SECTION 0x2400
+#define mmSHADOW_2_TENSOR_O_MME1_CTRL_BASE 0x7FFC0E0A40ull
+#define SHADOW_2_TENSOR_O_MME1_CTRL_MAX_OFFSET 0x4C00
+#define SHADOW_2_TENSOR_O_MME1_CTRL_SECTION 0x4C00
+#define mmSHADOW_2_AGU_O_LOCAL_MME1_CTRL_BASE 0x7FFC0E0A8Cull
+#define SHADOW_2_AGU_O_LOCAL_MME1_CTRL_MAX_OFFSET 0x2400
+#define SHADOW_2_AGU_O_LOCAL_MME1_CTRL_SECTION 0x2400
+#define mmSHADOW_2_AGU_O_REMOTE_MME1_CTRL_BASE 0x7FFC0E0AB0ull
+#define SHADOW_2_AGU_O_REMOTE_MME1_CTRL_MAX_OFFSET 0x2400
+#define SHADOW_2_AGU_O_REMOTE_MME1_CTRL_SECTION 0x2400
+#define mmSHADOW_2_DESC_MME1_CTRL_BASE 0x7FFC0E0AD4ull
+#define SHADOW_2_DESC_MME1_CTRL_MAX_OFFSET 0x5400
+#define SHADOW_2_DESC_MME1_CTRL_SECTION 0xB400
+#define mmSHADOW_3_MME1_CTRL_BASE 0x7FFC0E0B88ull
+#define SHADOW_3_MME1_CTRL_MAX_OFFSET 0x3400
+#define SHADOW_3_MME1_CTRL_SECTION 0x3400
+#define mmSHADOW_3_TENSOR_S_MME1_CTRL_BASE 0x7FFC0E0BBCull
+#define SHADOW_3_TENSOR_S_MME1_CTRL_MAX_OFFSET 0x4C00
+#define SHADOW_3_TENSOR_S_MME1_CTRL_SECTION 0x4C00
+#define mmSHADOW_3_AGU_S_MME1_CTRL_BASE 0x7FFC0E0C08ull
+#define SHADOW_3_AGU_S_MME1_CTRL_MAX_OFFSET 0x2400
+#define SHADOW_3_AGU_S_MME1_CTRL_SECTION 0x2400
+#define mmSHADOW_3_TENSOR_L_MME1_CTRL_BASE 0x7FFC0E0C2Cull
+#define SHADOW_3_TENSOR_L_MME1_CTRL_MAX_OFFSET 0x4C00
+#define SHADOW_3_TENSOR_L_MME1_CTRL_SECTION 0x4C00
+#define mmSHADOW_3_AGU_L_LOCAL_MME1_CTRL_BASE 0x7FFC0E0C78ull
+#define SHADOW_3_AGU_L_LOCAL_MME1_CTRL_MAX_OFFSET 0x2400
+#define SHADOW_3_AGU_L_LOCAL_MME1_CTRL_SECTION 0x2400
+#define mmSHADOW_3_AGU_L_REMOTE_MME1_CTRL_BASE 0x7FFC0E0C9Cull
+#define SHADOW_3_AGU_L_REMOTE_MME1_CTRL_MAX_OFFSET 0x2400
+#define SHADOW_3_AGU_L_REMOTE_MME1_CTRL_SECTION 0x2400
+#define mmSHADOW_3_TENSOR_O_MME1_CTRL_BASE 0x7FFC0E0CC0ull
+#define SHADOW_3_TENSOR_O_MME1_CTRL_MAX_OFFSET 0x4C00
+#define SHADOW_3_TENSOR_O_MME1_CTRL_SECTION 0x4C00
+#define mmSHADOW_3_AGU_O_LOCAL_MME1_CTRL_BASE 0x7FFC0E0D0Cull
+#define SHADOW_3_AGU_O_LOCAL_MME1_CTRL_MAX_OFFSET 0x2400
+#define SHADOW_3_AGU_O_LOCAL_MME1_CTRL_SECTION 0x2400
+#define mmSHADOW_3_AGU_O_REMOTE_MME1_CTRL_BASE 0x7FFC0E0D30ull
+#define SHADOW_3_AGU_O_REMOTE_MME1_CTRL_MAX_OFFSET 0x2400
+#define SHADOW_3_AGU_O_REMOTE_MME1_CTRL_SECTION 0x2400
+#define mmSHADOW_3_DESC_MME1_CTRL_BASE 0x7FFC0E0D54ull
+#define SHADOW_3_DESC_MME1_CTRL_MAX_OFFSET 0x5400
+#define SHADOW_3_DESC_MME1_CTRL_SECTION 0x72AC
+#define mmMME1_QM_BASE 0x7FFC0E8000ull
+#define MME1_QM_MAX_OFFSET 0xD040
+#define MME1_QM_SECTION 0x38000
+#define mmMME2_ACC_BASE 0x7FFC120000ull
+#define MME2_ACC_MAX_OFFSET 0x5C00
+#define MME2_ACC_SECTION 0x20000
+#define mmMME2_SBAB_BASE 0x7FFC140000ull
+#define MME2_SBAB_MAX_OFFSET 0x5800
+#define MME2_SBAB_SECTION 0x1000
+#define mmMME2_PRTN_BASE 0x7FFC141000ull
+#define MME2_PRTN_MAX_OFFSET 0x5000
+#define MME2_PRTN_SECTION 0x1F000
+#define mmMME2_CTRL_BASE 0x7FFC160000ull
+#define MME2_CTRL_MAX_OFFSET 0xDA80
+#define MME2_CTRL_SECTION 0x8000
+#define mmARCH_MME2_CTRL_BASE 0x7FFC160008ull
+#define ARCH_MME2_CTRL_MAX_OFFSET 0x3400
+#define ARCH_MME2_CTRL_SECTION 0x3400
+#define mmARCH_TENSOR_S_MME2_CTRL_BASE 0x7FFC16003Cull
+#define ARCH_TENSOR_S_MME2_CTRL_MAX_OFFSET 0x4C00
+#define ARCH_TENSOR_S_MME2_CTRL_SECTION 0x4C00
+#define mmARCH_AGU_S_MME2_CTRL_BASE 0x7FFC160088ull
+#define ARCH_AGU_S_MME2_CTRL_MAX_OFFSET 0x2400
+#define ARCH_AGU_S_MME2_CTRL_SECTION 0x2400
+#define mmARCH_TENSOR_L_MME2_CTRL_BASE 0x7FFC1600ACull
+#define ARCH_TENSOR_L_MME2_CTRL_MAX_OFFSET 0x4C00
+#define ARCH_TENSOR_L_MME2_CTRL_SECTION 0x4C00
+#define mmARCH_AGU_L_LOCAL_MME2_CTRL_BASE 0x7FFC1600F8ull
+#define ARCH_AGU_L_LOCAL_MME2_CTRL_MAX_OFFSET 0x2400
+#define ARCH_AGU_L_LOCAL_MME2_CTRL_SECTION 0x2400
+#define mmARCH_AGU_L_REMOTE_MME2_CTRL_BASE 0x7FFC16011Cull
+#define ARCH_AGU_L_REMOTE_MME2_CTRL_MAX_OFFSET 0x2400
+#define ARCH_AGU_L_REMOTE_MME2_CTRL_SECTION 0x2400
+#define mmARCH_TENSOR_O_MME2_CTRL_BASE 0x7FFC160140ull
+#define ARCH_TENSOR_O_MME2_CTRL_MAX_OFFSET 0x4C00
+#define ARCH_TENSOR_O_MME2_CTRL_SECTION 0x4C00
+#define mmARCH_AGU_O_LOCAL_MME2_CTRL_BASE 0x7FFC16018Cull
+#define ARCH_AGU_O_LOCAL_MME2_CTRL_MAX_OFFSET 0x2400
+#define ARCH_AGU_O_LOCAL_MME2_CTRL_SECTION 0x2400
+#define mmARCH_AGU_O_REMOTE_MME2_CTRL_BASE 0x7FFC1601B0ull
+#define ARCH_AGU_O_REMOTE_MME2_CTRL_MAX_OFFSET 0x2400
+#define ARCH_AGU_O_REMOTE_MME2_CTRL_SECTION 0x2400
+#define mmARCH_DESC_MME2_CTRL_BASE 0x7FFC1601D4ull
+#define ARCH_DESC_MME2_CTRL_MAX_OFFSET 0x5400
+#define ARCH_DESC_MME2_CTRL_SECTION 0x2340
+#define mmSHADOW_0_MME2_CTRL_BASE 0x7FFC160408ull
+#define SHADOW_0_MME2_CTRL_MAX_OFFSET 0x3400
+#define SHADOW_0_MME2_CTRL_SECTION 0x3400
+#define mmSHADOW_0_TENSOR_S_MME2_CTRL_BASE 0x7FFC16043Cull
+#define SHADOW_0_TENSOR_S_MME2_CTRL_MAX_OFFSET 0x4C00
+#define SHADOW_0_TENSOR_S_MME2_CTRL_SECTION 0x4C00
+#define mmSHADOW_0_AGU_S_MME2_CTRL_BASE 0x7FFC160488ull
+#define SHADOW_0_AGU_S_MME2_CTRL_MAX_OFFSET 0x2400
+#define SHADOW_0_AGU_S_MME2_CTRL_SECTION 0x2400
+#define mmSHADOW_0_TENSOR_L_MME2_CTRL_BASE 0x7FFC1604ACull
+#define SHADOW_0_TENSOR_L_MME2_CTRL_MAX_OFFSET 0x4C00
+#define SHADOW_0_TENSOR_L_MME2_CTRL_SECTION 0x4C00
+#define mmSHADOW_0_AGU_L_LOCAL_MME2_CTRL_BASE 0x7FFC1604F8ull
+#define SHADOW_0_AGU_L_LOCAL_MME2_CTRL_MAX_OFFSET 0x2400
+#define SHADOW_0_AGU_L_LOCAL_MME2_CTRL_SECTION 0x2400
+#define mmSHADOW_0_AGU_L_REMOTE_MME2_CTRL_BASE 0x7FFC16051Cull
+#define SHADOW_0_AGU_L_REMOTE_MME2_CTRL_MAX_OFFSET 0x2400
+#define SHADOW_0_AGU_L_REMOTE_MME2_CTRL_SECTION 0x2400
+#define mmSHADOW_0_TENSOR_O_MME2_CTRL_BASE 0x7FFC160540ull
+#define SHADOW_0_TENSOR_O_MME2_CTRL_MAX_OFFSET 0x4C00
+#define SHADOW_0_TENSOR_O_MME2_CTRL_SECTION 0x4C00
+#define mmSHADOW_0_AGU_O_LOCAL_MME2_CTRL_BASE 0x7FFC16058Cull
+#define SHADOW_0_AGU_O_LOCAL_MME2_CTRL_MAX_OFFSET 0x2400
+#define SHADOW_0_AGU_O_LOCAL_MME2_CTRL_SECTION 0x2400
+#define mmSHADOW_0_AGU_O_REMOTE_MME2_CTRL_BASE 0x7FFC1605B0ull
+#define SHADOW_0_AGU_O_REMOTE_MME2_CTRL_MAX_OFFSET 0x2400
+#define SHADOW_0_AGU_O_REMOTE_MME2_CTRL_SECTION 0x2400
+#define mmSHADOW_0_DESC_MME2_CTRL_BASE 0x7FFC1605D4ull
+#define SHADOW_0_DESC_MME2_CTRL_MAX_OFFSET 0x5400
+#define SHADOW_0_DESC_MME2_CTRL_SECTION 0xB400
+#define mmSHADOW_1_MME2_CTRL_BASE 0x7FFC160688ull
+#define SHADOW_1_MME2_CTRL_MAX_OFFSET 0x3400
+#define SHADOW_1_MME2_CTRL_SECTION 0x3400
+#define mmSHADOW_1_TENSOR_S_MME2_CTRL_BASE 0x7FFC1606BCull
+#define SHADOW_1_TENSOR_S_MME2_CTRL_MAX_OFFSET 0x4C00
+#define SHADOW_1_TENSOR_S_MME2_CTRL_SECTION 0x4C00
+#define mmSHADOW_1_AGU_S_MME2_CTRL_BASE 0x7FFC160708ull
+#define SHADOW_1_AGU_S_MME2_CTRL_MAX_OFFSET 0x2400
+#define SHADOW_1_AGU_S_MME2_CTRL_SECTION 0x2400
+#define mmSHADOW_1_TENSOR_L_MME2_CTRL_BASE 0x7FFC16072Cull
+#define SHADOW_1_TENSOR_L_MME2_CTRL_MAX_OFFSET 0x4C00
+#define SHADOW_1_TENSOR_L_MME2_CTRL_SECTION 0x4C00
+#define mmSHADOW_1_AGU_L_LOCAL_MME2_CTRL_BASE 0x7FFC160778ull
+#define SHADOW_1_AGU_L_LOCAL_MME2_CTRL_MAX_OFFSET 0x2400
+#define SHADOW_1_AGU_L_LOCAL_MME2_CTRL_SECTION 0x2400
+#define mmSHADOW_1_AGU_L_REMOTE_MME2_CTRL_BASE 0x7FFC16079Cull
+#define SHADOW_1_AGU_L_REMOTE_MME2_CTRL_MAX_OFFSET 0x2400
+#define SHADOW_1_AGU_L_REMOTE_MME2_CTRL_SECTION 0x2400
+#define mmSHADOW_1_TENSOR_O_MME2_CTRL_BASE 0x7FFC1607C0ull
+#define SHADOW_1_TENSOR_O_MME2_CTRL_MAX_OFFSET 0x4C00
+#define SHADOW_1_TENSOR_O_MME2_CTRL_SECTION 0x4C00
+#define mmSHADOW_1_AGU_O_LOCAL_MME2_CTRL_BASE 0x7FFC16080Cull
+#define SHADOW_1_AGU_O_LOCAL_MME2_CTRL_MAX_OFFSET 0x2400
+#define SHADOW_1_AGU_O_LOCAL_MME2_CTRL_SECTION 0x2400
+#define mmSHADOW_1_AGU_O_REMOTE_MME2_CTRL_BASE 0x7FFC160830ull
+#define SHADOW_1_AGU_O_REMOTE_MME2_CTRL_MAX_OFFSET 0x2400
+#define SHADOW_1_AGU_O_REMOTE_MME2_CTRL_SECTION 0x2400
+#define mmSHADOW_1_DESC_MME2_CTRL_BASE 0x7FFC160854ull
+#define SHADOW_1_DESC_MME2_CTRL_MAX_OFFSET 0x5400
+#define SHADOW_1_DESC_MME2_CTRL_SECTION 0xB400
+#define mmSHADOW_2_MME2_CTRL_BASE 0x7FFC160908ull
+#define SHADOW_2_MME2_CTRL_MAX_OFFSET 0x3400
+#define SHADOW_2_MME2_CTRL_SECTION 0x3400
+#define mmSHADOW_2_TENSOR_S_MME2_CTRL_BASE 0x7FFC16093Cull
+#define SHADOW_2_TENSOR_S_MME2_CTRL_MAX_OFFSET 0x4C00
+#define SHADOW_2_TENSOR_S_MME2_CTRL_SECTION 0x4C00
+#define mmSHADOW_2_AGU_S_MME2_CTRL_BASE 0x7FFC160988ull
+#define SHADOW_2_AGU_S_MME2_CTRL_MAX_OFFSET 0x2400
+#define SHADOW_2_AGU_S_MME2_CTRL_SECTION 0x2400
+#define mmSHADOW_2_TENSOR_L_MME2_CTRL_BASE 0x7FFC1609ACull
+#define SHADOW_2_TENSOR_L_MME2_CTRL_MAX_OFFSET 0x4C00
+#define SHADOW_2_TENSOR_L_MME2_CTRL_SECTION 0x4C00
+#define mmSHADOW_2_AGU_L_LOCAL_MME2_CTRL_BASE 0x7FFC1609F8ull
+#define SHADOW_2_AGU_L_LOCAL_MME2_CTRL_MAX_OFFSET 0x2400
+#define SHADOW_2_AGU_L_LOCAL_MME2_CTRL_SECTION 0x2400
+#define mmSHADOW_2_AGU_L_REMOTE_MME2_CTRL_BASE 0x7FFC160A1Cull
+#define SHADOW_2_AGU_L_REMOTE_MME2_CTRL_MAX_OFFSET 0x2400
+#define SHADOW_2_AGU_L_REMOTE_MME2_CTRL_SECTION 0x2400
+#define mmSHADOW_2_TENSOR_O_MME2_CTRL_BASE 0x7FFC160A40ull
+#define SHADOW_2_TENSOR_O_MME2_CTRL_MAX_OFFSET 0x4C00
+#define SHADOW_2_TENSOR_O_MME2_CTRL_SECTION 0x4C00
+#define mmSHADOW_2_AGU_O_LOCAL_MME2_CTRL_BASE 0x7FFC160A8Cull
+#define SHADOW_2_AGU_O_LOCAL_MME2_CTRL_MAX_OFFSET 0x2400
+#define SHADOW_2_AGU_O_LOCAL_MME2_CTRL_SECTION 0x2400
+#define mmSHADOW_2_AGU_O_REMOTE_MME2_CTRL_BASE 0x7FFC160AB0ull
+#define SHADOW_2_AGU_O_REMOTE_MME2_CTRL_MAX_OFFSET 0x2400
+#define SHADOW_2_AGU_O_REMOTE_MME2_CTRL_SECTION 0x2400
+#define mmSHADOW_2_DESC_MME2_CTRL_BASE 0x7FFC160AD4ull
+#define SHADOW_2_DESC_MME2_CTRL_MAX_OFFSET 0x5400
+#define SHADOW_2_DESC_MME2_CTRL_SECTION 0xB400
+#define mmSHADOW_3_MME2_CTRL_BASE 0x7FFC160B88ull
+#define SHADOW_3_MME2_CTRL_MAX_OFFSET 0x3400
+#define SHADOW_3_MME2_CTRL_SECTION 0x3400
+#define mmSHADOW_3_TENSOR_S_MME2_CTRL_BASE 0x7FFC160BBCull
+#define SHADOW_3_TENSOR_S_MME2_CTRL_MAX_OFFSET 0x4C00
+#define SHADOW_3_TENSOR_S_MME2_CTRL_SECTION 0x4C00
+#define mmSHADOW_3_AGU_S_MME2_CTRL_BASE 0x7FFC160C08ull
+#define SHADOW_3_AGU_S_MME2_CTRL_MAX_OFFSET 0x2400
+#define SHADOW_3_AGU_S_MME2_CTRL_SECTION 0x2400
+#define mmSHADOW_3_TENSOR_L_MME2_CTRL_BASE 0x7FFC160C2Cull
+#define SHADOW_3_TENSOR_L_MME2_CTRL_MAX_OFFSET 0x4C00
+#define SHADOW_3_TENSOR_L_MME2_CTRL_SECTION 0x4C00
+#define mmSHADOW_3_AGU_L_LOCAL_MME2_CTRL_BASE 0x7FFC160C78ull
+#define SHADOW_3_AGU_L_LOCAL_MME2_CTRL_MAX_OFFSET 0x2400
+#define SHADOW_3_AGU_L_LOCAL_MME2_CTRL_SECTION 0x2400
+#define mmSHADOW_3_AGU_L_REMOTE_MME2_CTRL_BASE 0x7FFC160C9Cull
+#define SHADOW_3_AGU_L_REMOTE_MME2_CTRL_MAX_OFFSET 0x2400
+#define SHADOW_3_AGU_L_REMOTE_MME2_CTRL_SECTION 0x2400
+#define mmSHADOW_3_TENSOR_O_MME2_CTRL_BASE 0x7FFC160CC0ull
+#define SHADOW_3_TENSOR_O_MME2_CTRL_MAX_OFFSET 0x4C00
+#define SHADOW_3_TENSOR_O_MME2_CTRL_SECTION 0x4C00
+#define mmSHADOW_3_AGU_O_LOCAL_MME2_CTRL_BASE 0x7FFC160D0Cull
+#define SHADOW_3_AGU_O_LOCAL_MME2_CTRL_MAX_OFFSET 0x2400
+#define SHADOW_3_AGU_O_LOCAL_MME2_CTRL_SECTION 0x2400
+#define mmSHADOW_3_AGU_O_REMOTE_MME2_CTRL_BASE 0x7FFC160D30ull
+#define SHADOW_3_AGU_O_REMOTE_MME2_CTRL_MAX_OFFSET 0x2400
+#define SHADOW_3_AGU_O_REMOTE_MME2_CTRL_SECTION 0x2400
+#define mmSHADOW_3_DESC_MME2_CTRL_BASE 0x7FFC160D54ull
+#define SHADOW_3_DESC_MME2_CTRL_MAX_OFFSET 0x5400
+#define SHADOW_3_DESC_MME2_CTRL_SECTION 0x72AC
+#define mmMME2_QM_BASE 0x7FFC168000ull
+#define MME2_QM_MAX_OFFSET 0xD040
+#define MME2_QM_SECTION 0x38000
+#define mmMME3_ACC_BASE 0x7FFC1A0000ull
+#define MME3_ACC_MAX_OFFSET 0x5C00
+#define MME3_ACC_SECTION 0x20000
+#define mmMME3_SBAB_BASE 0x7FFC1C0000ull
+#define MME3_SBAB_MAX_OFFSET 0x5800
+#define MME3_SBAB_SECTION 0x1000
+#define mmMME3_PRTN_BASE 0x7FFC1C1000ull
+#define MME3_PRTN_MAX_OFFSET 0x5000
+#define MME3_PRTN_SECTION 0x1F000
+#define mmMME3_CTRL_BASE 0x7FFC1E0000ull
+#define MME3_CTRL_MAX_OFFSET 0xDA80
+#define MME3_CTRL_SECTION 0x8000
+#define mmARCH_MME3_CTRL_BASE 0x7FFC1E0008ull
+#define ARCH_MME3_CTRL_MAX_OFFSET 0x3400
+#define ARCH_MME3_CTRL_SECTION 0x3400
+#define mmARCH_TENSOR_S_MME3_CTRL_BASE 0x7FFC1E003Cull
+#define ARCH_TENSOR_S_MME3_CTRL_MAX_OFFSET 0x4C00
+#define ARCH_TENSOR_S_MME3_CTRL_SECTION 0x4C00
+#define mmARCH_AGU_S_MME3_CTRL_BASE 0x7FFC1E0088ull
+#define ARCH_AGU_S_MME3_CTRL_MAX_OFFSET 0x2400
+#define ARCH_AGU_S_MME3_CTRL_SECTION 0x2400
+#define mmARCH_TENSOR_L_MME3_CTRL_BASE 0x7FFC1E00ACull
+#define ARCH_TENSOR_L_MME3_CTRL_MAX_OFFSET 0x4C00
+#define ARCH_TENSOR_L_MME3_CTRL_SECTION 0x4C00
+#define mmARCH_AGU_L_LOCAL_MME3_CTRL_BASE 0x7FFC1E00F8ull
+#define ARCH_AGU_L_LOCAL_MME3_CTRL_MAX_OFFSET 0x2400
+#define ARCH_AGU_L_LOCAL_MME3_CTRL_SECTION 0x2400
+#define mmARCH_AGU_L_REMOTE_MME3_CTRL_BASE 0x7FFC1E011Cull
+#define ARCH_AGU_L_REMOTE_MME3_CTRL_MAX_OFFSET 0x2400
+#define ARCH_AGU_L_REMOTE_MME3_CTRL_SECTION 0x2400
+#define mmARCH_TENSOR_O_MME3_CTRL_BASE 0x7FFC1E0140ull
+#define ARCH_TENSOR_O_MME3_CTRL_MAX_OFFSET 0x4C00
+#define ARCH_TENSOR_O_MME3_CTRL_SECTION 0x4C00
+#define mmARCH_AGU_O_LOCAL_MME3_CTRL_BASE 0x7FFC1E018Cull
+#define ARCH_AGU_O_LOCAL_MME3_CTRL_MAX_OFFSET 0x2400
+#define ARCH_AGU_O_LOCAL_MME3_CTRL_SECTION 0x2400
+#define mmARCH_AGU_O_REMOTE_MME3_CTRL_BASE 0x7FFC1E01B0ull
+#define ARCH_AGU_O_REMOTE_MME3_CTRL_MAX_OFFSET 0x2400
+#define ARCH_AGU_O_REMOTE_MME3_CTRL_SECTION 0x2400
+#define mmARCH_DESC_MME3_CTRL_BASE 0x7FFC1E01D4ull
+#define ARCH_DESC_MME3_CTRL_MAX_OFFSET 0x5400
+#define ARCH_DESC_MME3_CTRL_SECTION 0x2340
+#define mmSHADOW_0_MME3_CTRL_BASE 0x7FFC1E0408ull
+#define SHADOW_0_MME3_CTRL_MAX_OFFSET 0x3400
+#define SHADOW_0_MME3_CTRL_SECTION 0x3400
+#define mmSHADOW_0_TENSOR_S_MME3_CTRL_BASE 0x7FFC1E043Cull
+#define SHADOW_0_TENSOR_S_MME3_CTRL_MAX_OFFSET 0x4C00
+#define SHADOW_0_TENSOR_S_MME3_CTRL_SECTION 0x4C00
+#define mmSHADOW_0_AGU_S_MME3_CTRL_BASE 0x7FFC1E0488ull
+#define SHADOW_0_AGU_S_MME3_CTRL_MAX_OFFSET 0x2400
+#define SHADOW_0_AGU_S_MME3_CTRL_SECTION 0x2400
+#define mmSHADOW_0_TENSOR_L_MME3_CTRL_BASE 0x7FFC1E04ACull
+#define SHADOW_0_TENSOR_L_MME3_CTRL_MAX_OFFSET 0x4C00
+#define SHADOW_0_TENSOR_L_MME3_CTRL_SECTION 0x4C00
+#define mmSHADOW_0_AGU_L_LOCAL_MME3_CTRL_BASE 0x7FFC1E04F8ull
+#define SHADOW_0_AGU_L_LOCAL_MME3_CTRL_MAX_OFFSET 0x2400
+#define SHADOW_0_AGU_L_LOCAL_MME3_CTRL_SECTION 0x2400
+#define mmSHADOW_0_AGU_L_REMOTE_MME3_CTRL_BASE 0x7FFC1E051Cull
+#define SHADOW_0_AGU_L_REMOTE_MME3_CTRL_MAX_OFFSET 0x2400
+#define SHADOW_0_AGU_L_REMOTE_MME3_CTRL_SECTION 0x2400
+#define mmSHADOW_0_TENSOR_O_MME3_CTRL_BASE 0x7FFC1E0540ull
+#define SHADOW_0_TENSOR_O_MME3_CTRL_MAX_OFFSET 0x4C00
+#define SHADOW_0_TENSOR_O_MME3_CTRL_SECTION 0x4C00
+#define mmSHADOW_0_AGU_O_LOCAL_MME3_CTRL_BASE 0x7FFC1E058Cull
+#define SHADOW_0_AGU_O_LOCAL_MME3_CTRL_MAX_OFFSET 0x2400
+#define SHADOW_0_AGU_O_LOCAL_MME3_CTRL_SECTION 0x2400
+#define mmSHADOW_0_AGU_O_REMOTE_MME3_CTRL_BASE 0x7FFC1E05B0ull
+#define SHADOW_0_AGU_O_REMOTE_MME3_CTRL_MAX_OFFSET 0x2400
+#define SHADOW_0_AGU_O_REMOTE_MME3_CTRL_SECTION 0x2400
+#define mmSHADOW_0_DESC_MME3_CTRL_BASE 0x7FFC1E05D4ull
+#define SHADOW_0_DESC_MME3_CTRL_MAX_OFFSET 0x5400
+#define SHADOW_0_DESC_MME3_CTRL_SECTION 0xB400
+#define mmSHADOW_1_MME3_CTRL_BASE 0x7FFC1E0688ull
+#define SHADOW_1_MME3_CTRL_MAX_OFFSET 0x3400
+#define SHADOW_1_MME3_CTRL_SECTION 0x3400
+#define mmSHADOW_1_TENSOR_S_MME3_CTRL_BASE 0x7FFC1E06BCull
+#define SHADOW_1_TENSOR_S_MME3_CTRL_MAX_OFFSET 0x4C00
+#define SHADOW_1_TENSOR_S_MME3_CTRL_SECTION 0x4C00
+#define mmSHADOW_1_AGU_S_MME3_CTRL_BASE 0x7FFC1E0708ull
+#define SHADOW_1_AGU_S_MME3_CTRL_MAX_OFFSET 0x2400
+#define SHADOW_1_AGU_S_MME3_CTRL_SECTION 0x2400
+#define mmSHADOW_1_TENSOR_L_MME3_CTRL_BASE 0x7FFC1E072Cull
+#define SHADOW_1_TENSOR_L_MME3_CTRL_MAX_OFFSET 0x4C00
+#define SHADOW_1_TENSOR_L_MME3_CTRL_SECTION 0x4C00
+#define mmSHADOW_1_AGU_L_LOCAL_MME3_CTRL_BASE 0x7FFC1E0778ull
+#define SHADOW_1_AGU_L_LOCAL_MME3_CTRL_MAX_OFFSET 0x2400
+#define SHADOW_1_AGU_L_LOCAL_MME3_CTRL_SECTION 0x2400
+#define mmSHADOW_1_AGU_L_REMOTE_MME3_CTRL_BASE 0x7FFC1E079Cull
+#define SHADOW_1_AGU_L_REMOTE_MME3_CTRL_MAX_OFFSET 0x2400
+#define SHADOW_1_AGU_L_REMOTE_MME3_CTRL_SECTION 0x2400
+#define mmSHADOW_1_TENSOR_O_MME3_CTRL_BASE 0x7FFC1E07C0ull
+#define SHADOW_1_TENSOR_O_MME3_CTRL_MAX_OFFSET 0x4C00
+#define SHADOW_1_TENSOR_O_MME3_CTRL_SECTION 0x4C00
+#define mmSHADOW_1_AGU_O_LOCAL_MME3_CTRL_BASE 0x7FFC1E080Cull
+#define SHADOW_1_AGU_O_LOCAL_MME3_CTRL_MAX_OFFSET 0x2400
+#define SHADOW_1_AGU_O_LOCAL_MME3_CTRL_SECTION 0x2400
+#define mmSHADOW_1_AGU_O_REMOTE_MME3_CTRL_BASE 0x7FFC1E0830ull
+#define SHADOW_1_AGU_O_REMOTE_MME3_CTRL_MAX_OFFSET 0x2400
+#define SHADOW_1_AGU_O_REMOTE_MME3_CTRL_SECTION 0x2400
+#define mmSHADOW_1_DESC_MME3_CTRL_BASE 0x7FFC1E0854ull
+#define SHADOW_1_DESC_MME3_CTRL_MAX_OFFSET 0x5400
+#define SHADOW_1_DESC_MME3_CTRL_SECTION 0xB400
+#define mmSHADOW_2_MME3_CTRL_BASE 0x7FFC1E0908ull
+#define SHADOW_2_MME3_CTRL_MAX_OFFSET 0x3400
+#define SHADOW_2_MME3_CTRL_SECTION 0x3400
+#define mmSHADOW_2_TENSOR_S_MME3_CTRL_BASE 0x7FFC1E093Cull
+#define SHADOW_2_TENSOR_S_MME3_CTRL_MAX_OFFSET 0x4C00
+#define SHADOW_2_TENSOR_S_MME3_CTRL_SECTION 0x4C00
+#define mmSHADOW_2_AGU_S_MME3_CTRL_BASE 0x7FFC1E0988ull
+#define SHADOW_2_AGU_S_MME3_CTRL_MAX_OFFSET 0x2400
+#define SHADOW_2_AGU_S_MME3_CTRL_SECTION 0x2400
+#define mmSHADOW_2_TENSOR_L_MME3_CTRL_BASE 0x7FFC1E09ACull
+#define SHADOW_2_TENSOR_L_MME3_CTRL_MAX_OFFSET 0x4C00
+#define SHADOW_2_TENSOR_L_MME3_CTRL_SECTION 0x4C00
+#define mmSHADOW_2_AGU_L_LOCAL_MME3_CTRL_BASE 0x7FFC1E09F8ull
+#define SHADOW_2_AGU_L_LOCAL_MME3_CTRL_MAX_OFFSET 0x2400
+#define SHADOW_2_AGU_L_LOCAL_MME3_CTRL_SECTION 0x2400
+#define mmSHADOW_2_AGU_L_REMOTE_MME3_CTRL_BASE 0x7FFC1E0A1Cull
+#define SHADOW_2_AGU_L_REMOTE_MME3_CTRL_MAX_OFFSET 0x2400
+#define SHADOW_2_AGU_L_REMOTE_MME3_CTRL_SECTION 0x2400
+#define mmSHADOW_2_TENSOR_O_MME3_CTRL_BASE 0x7FFC1E0A40ull
+#define SHADOW_2_TENSOR_O_MME3_CTRL_MAX_OFFSET 0x4C00
+#define SHADOW_2_TENSOR_O_MME3_CTRL_SECTION 0x4C00
+#define mmSHADOW_2_AGU_O_LOCAL_MME3_CTRL_BASE 0x7FFC1E0A8Cull
+#define SHADOW_2_AGU_O_LOCAL_MME3_CTRL_MAX_OFFSET 0x2400
+#define SHADOW_2_AGU_O_LOCAL_MME3_CTRL_SECTION 0x2400
+#define mmSHADOW_2_AGU_O_REMOTE_MME3_CTRL_BASE 0x7FFC1E0AB0ull
+#define SHADOW_2_AGU_O_REMOTE_MME3_CTRL_MAX_OFFSET 0x2400
+#define SHADOW_2_AGU_O_REMOTE_MME3_CTRL_SECTION 0x2400
+#define mmSHADOW_2_DESC_MME3_CTRL_BASE 0x7FFC1E0AD4ull
+#define SHADOW_2_DESC_MME3_CTRL_MAX_OFFSET 0x5400
+#define SHADOW_2_DESC_MME3_CTRL_SECTION 0xB400
+#define mmSHADOW_3_MME3_CTRL_BASE 0x7FFC1E0B88ull
+#define SHADOW_3_MME3_CTRL_MAX_OFFSET 0x3400
+#define SHADOW_3_MME3_CTRL_SECTION 0x3400
+#define mmSHADOW_3_TENSOR_S_MME3_CTRL_BASE 0x7FFC1E0BBCull
+#define SHADOW_3_TENSOR_S_MME3_CTRL_MAX_OFFSET 0x4C00
+#define SHADOW_3_TENSOR_S_MME3_CTRL_SECTION 0x4C00
+#define mmSHADOW_3_AGU_S_MME3_CTRL_BASE 0x7FFC1E0C08ull
+#define SHADOW_3_AGU_S_MME3_CTRL_MAX_OFFSET 0x2400
+#define SHADOW_3_AGU_S_MME3_CTRL_SECTION 0x2400
+#define mmSHADOW_3_TENSOR_L_MME3_CTRL_BASE 0x7FFC1E0C2Cull
+#define SHADOW_3_TENSOR_L_MME3_CTRL_MAX_OFFSET 0x4C00
+#define SHADOW_3_TENSOR_L_MME3_CTRL_SECTION 0x4C00
+#define mmSHADOW_3_AGU_L_LOCAL_MME3_CTRL_BASE 0x7FFC1E0C78ull
+#define SHADOW_3_AGU_L_LOCAL_MME3_CTRL_MAX_OFFSET 0x2400
+#define SHADOW_3_AGU_L_LOCAL_MME3_CTRL_SECTION 0x2400
+#define mmSHADOW_3_AGU_L_REMOTE_MME3_CTRL_BASE 0x7FFC1E0C9Cull
+#define SHADOW_3_AGU_L_REMOTE_MME3_CTRL_MAX_OFFSET 0x2400
+#define SHADOW_3_AGU_L_REMOTE_MME3_CTRL_SECTION 0x2400
+#define mmSHADOW_3_TENSOR_O_MME3_CTRL_BASE 0x7FFC1E0CC0ull
+#define SHADOW_3_TENSOR_O_MME3_CTRL_MAX_OFFSET 0x4C00
+#define SHADOW_3_TENSOR_O_MME3_CTRL_SECTION 0x4C00
+#define mmSHADOW_3_AGU_O_LOCAL_MME3_CTRL_BASE 0x7FFC1E0D0Cull
+#define SHADOW_3_AGU_O_LOCAL_MME3_CTRL_MAX_OFFSET 0x2400
+#define SHADOW_3_AGU_O_LOCAL_MME3_CTRL_SECTION 0x2400
+#define mmSHADOW_3_AGU_O_REMOTE_MME3_CTRL_BASE 0x7FFC1E0D30ull
+#define SHADOW_3_AGU_O_REMOTE_MME3_CTRL_MAX_OFFSET 0x2400
+#define SHADOW_3_AGU_O_REMOTE_MME3_CTRL_SECTION 0x2400
+#define mmSHADOW_3_DESC_MME3_CTRL_BASE 0x7FFC1E0D54ull
+#define SHADOW_3_DESC_MME3_CTRL_MAX_OFFSET 0x5400
+#define SHADOW_3_DESC_MME3_CTRL_SECTION 0x72AC
+#define mmMME3_QM_BASE 0x7FFC1E8000ull
+#define MME3_QM_MAX_OFFSET 0xD040
+#define MME3_QM_SECTION 0x18000
+#define mmSRAM_Y0_X0_BANK_BASE 0x7FFC200000ull
+#define SRAM_Y0_X0_BANK_MAX_OFFSET 0x4000
+#define SRAM_Y0_X0_BANK_SECTION 0x1000
+#define mmSRAM_Y0_X0_RTR_BASE 0x7FFC201000ull
+#define SRAM_Y0_X0_RTR_MAX_OFFSET 0x3340
+#define SRAM_Y0_X0_RTR_SECTION 0x7000
+#define mmSRAM_Y0_X1_BANK_BASE 0x7FFC208000ull
+#define SRAM_Y0_X1_BANK_MAX_OFFSET 0x4000
+#define SRAM_Y0_X1_BANK_SECTION 0x1000
+#define mmSRAM_Y0_X1_RTR_BASE 0x7FFC209000ull
+#define SRAM_Y0_X1_RTR_MAX_OFFSET 0x3340
+#define SRAM_Y0_X1_RTR_SECTION 0x7000
+#define mmSRAM_Y0_X2_BANK_BASE 0x7FFC210000ull
+#define SRAM_Y0_X2_BANK_MAX_OFFSET 0x4000
+#define SRAM_Y0_X2_BANK_SECTION 0x1000
+#define mmSRAM_Y0_X2_RTR_BASE 0x7FFC211000ull
+#define SRAM_Y0_X2_RTR_MAX_OFFSET 0x3340
+#define SRAM_Y0_X2_RTR_SECTION 0x7000
+#define mmSRAM_Y0_X3_BANK_BASE 0x7FFC218000ull
+#define SRAM_Y0_X3_BANK_MAX_OFFSET 0x4000
+#define SRAM_Y0_X3_BANK_SECTION 0x1000
+#define mmSRAM_Y0_X3_RTR_BASE 0x7FFC219000ull
+#define SRAM_Y0_X3_RTR_MAX_OFFSET 0x3340
+#define SRAM_Y0_X3_RTR_SECTION 0x7000
+#define mmSRAM_Y0_X4_BANK_BASE 0x7FFC220000ull
+#define SRAM_Y0_X4_BANK_MAX_OFFSET 0x4000
+#define SRAM_Y0_X4_BANK_SECTION 0x1000
+#define mmSRAM_Y0_X4_RTR_BASE 0x7FFC221000ull
+#define SRAM_Y0_X4_RTR_MAX_OFFSET 0x3340
+#define SRAM_Y0_X4_RTR_SECTION 0x7000
+#define mmSRAM_Y0_X5_BANK_BASE 0x7FFC228000ull
+#define SRAM_Y0_X5_BANK_MAX_OFFSET 0x4000
+#define SRAM_Y0_X5_BANK_SECTION 0x1000
+#define mmSRAM_Y0_X5_RTR_BASE 0x7FFC229000ull
+#define SRAM_Y0_X5_RTR_MAX_OFFSET 0x3340
+#define SRAM_Y0_X5_RTR_SECTION 0x7000
+#define mmSRAM_Y0_X6_BANK_BASE 0x7FFC230000ull
+#define SRAM_Y0_X6_BANK_MAX_OFFSET 0x4000
+#define SRAM_Y0_X6_BANK_SECTION 0x1000
+#define mmSRAM_Y0_X6_RTR_BASE 0x7FFC231000ull
+#define SRAM_Y0_X6_RTR_MAX_OFFSET 0x3340
+#define SRAM_Y0_X6_RTR_SECTION 0x7000
+#define mmSRAM_Y0_X7_BANK_BASE 0x7FFC238000ull
+#define SRAM_Y0_X7_BANK_MAX_OFFSET 0x4000
+#define SRAM_Y0_X7_BANK_SECTION 0x1000
+#define mmSRAM_Y0_X7_RTR_BASE 0x7FFC239000ull
+#define SRAM_Y0_X7_RTR_MAX_OFFSET 0x3340
+#define SRAM_Y0_X7_RTR_SECTION 0x7000
+#define mmSRAM_Y1_X0_BANK_BASE 0x7FFC240000ull
+#define SRAM_Y1_X0_BANK_MAX_OFFSET 0x4000
+#define SRAM_Y1_X0_BANK_SECTION 0x1000
+#define mmSRAM_Y1_X0_RTR_BASE 0x7FFC241000ull
+#define SRAM_Y1_X0_RTR_MAX_OFFSET 0x3340
+#define SRAM_Y1_X0_RTR_SECTION 0x7000
+#define mmSRAM_Y1_X1_BANK_BASE 0x7FFC248000ull
+#define SRAM_Y1_X1_BANK_MAX_OFFSET 0x4000
+#define SRAM_Y1_X1_BANK_SECTION 0x1000
+#define mmSRAM_Y1_X1_RTR_BASE 0x7FFC249000ull
+#define SRAM_Y1_X1_RTR_MAX_OFFSET 0x3340
+#define SRAM_Y1_X1_RTR_SECTION 0x7000
+#define mmSRAM_Y1_X2_BANK_BASE 0x7FFC250000ull
+#define SRAM_Y1_X2_BANK_MAX_OFFSET 0x4000
+#define SRAM_Y1_X2_BANK_SECTION 0x1000
+#define mmSRAM_Y1_X2_RTR_BASE 0x7FFC251000ull
+#define SRAM_Y1_X2_RTR_MAX_OFFSET 0x3340
+#define SRAM_Y1_X2_RTR_SECTION 0x7000
+#define mmSRAM_Y1_X3_BANK_BASE 0x7FFC258000ull
+#define SRAM_Y1_X3_BANK_MAX_OFFSET 0x4000
+#define SRAM_Y1_X3_BANK_SECTION 0x1000
+#define mmSRAM_Y1_X3_RTR_BASE 0x7FFC259000ull
+#define SRAM_Y1_X3_RTR_MAX_OFFSET 0x3340
+#define SRAM_Y1_X3_RTR_SECTION 0x7000
+#define mmSRAM_Y1_X4_BANK_BASE 0x7FFC260000ull
+#define SRAM_Y1_X4_BANK_MAX_OFFSET 0x4000
+#define SRAM_Y1_X4_BANK_SECTION 0x1000
+#define mmSRAM_Y1_X4_RTR_BASE 0x7FFC261000ull
+#define SRAM_Y1_X4_RTR_MAX_OFFSET 0x3340
+#define SRAM_Y1_X4_RTR_SECTION 0x7000
+#define mmSRAM_Y1_X5_BANK_BASE 0x7FFC268000ull
+#define SRAM_Y1_X5_BANK_MAX_OFFSET 0x4000
+#define SRAM_Y1_X5_BANK_SECTION 0x1000
+#define mmSRAM_Y1_X5_RTR_BASE 0x7FFC269000ull
+#define SRAM_Y1_X5_RTR_MAX_OFFSET 0x3340
+#define SRAM_Y1_X5_RTR_SECTION 0x7000
+#define mmSRAM_Y1_X6_BANK_BASE 0x7FFC270000ull
+#define SRAM_Y1_X6_BANK_MAX_OFFSET 0x4000
+#define SRAM_Y1_X6_BANK_SECTION 0x1000
+#define mmSRAM_Y1_X6_RTR_BASE 0x7FFC271000ull
+#define SRAM_Y1_X6_RTR_MAX_OFFSET 0x3340
+#define SRAM_Y1_X6_RTR_SECTION 0x7000
+#define mmSRAM_Y1_X7_BANK_BASE 0x7FFC278000ull
+#define SRAM_Y1_X7_BANK_MAX_OFFSET 0x4000
+#define SRAM_Y1_X7_BANK_SECTION 0x1000
+#define mmSRAM_Y1_X7_RTR_BASE 0x7FFC279000ull
+#define SRAM_Y1_X7_RTR_MAX_OFFSET 0x3340
+#define SRAM_Y1_X7_RTR_SECTION 0x7000
+#define mmSRAM_Y2_X0_BANK_BASE 0x7FFC280000ull
+#define SRAM_Y2_X0_BANK_MAX_OFFSET 0x4000
+#define SRAM_Y2_X0_BANK_SECTION 0x1000
+#define mmSRAM_Y2_X0_RTR_BASE 0x7FFC281000ull
+#define SRAM_Y2_X0_RTR_MAX_OFFSET 0x3340
+#define SRAM_Y2_X0_RTR_SECTION 0x7000
+#define mmSRAM_Y2_X1_BANK_BASE 0x7FFC288000ull
+#define SRAM_Y2_X1_BANK_MAX_OFFSET 0x4000
+#define SRAM_Y2_X1_BANK_SECTION 0x1000
+#define mmSRAM_Y2_X1_RTR_BASE 0x7FFC289000ull
+#define SRAM_Y2_X1_RTR_MAX_OFFSET 0x3340
+#define SRAM_Y2_X1_RTR_SECTION 0x7000
+#define mmSRAM_Y2_X2_BANK_BASE 0x7FFC290000ull
+#define SRAM_Y2_X2_BANK_MAX_OFFSET 0x4000
+#define SRAM_Y2_X2_BANK_SECTION 0x1000
+#define mmSRAM_Y2_X2_RTR_BASE 0x7FFC291000ull
+#define SRAM_Y2_X2_RTR_MAX_OFFSET 0x3340
+#define SRAM_Y2_X2_RTR_SECTION 0x7000
+#define mmSRAM_Y2_X3_BANK_BASE 0x7FFC298000ull
+#define SRAM_Y2_X3_BANK_MAX_OFFSET 0x4000
+#define SRAM_Y2_X3_BANK_SECTION 0x1000
+#define mmSRAM_Y2_X3_RTR_BASE 0x7FFC299000ull
+#define SRAM_Y2_X3_RTR_MAX_OFFSET 0x3340
+#define SRAM_Y2_X3_RTR_SECTION 0x7000
+#define mmSRAM_Y2_X4_BANK_BASE 0x7FFC2A0000ull
+#define SRAM_Y2_X4_BANK_MAX_OFFSET 0x4000
+#define SRAM_Y2_X4_BANK_SECTION 0x1000
+#define mmSRAM_Y2_X4_RTR_BASE 0x7FFC2A1000ull
+#define SRAM_Y2_X4_RTR_MAX_OFFSET 0x3340
+#define SRAM_Y2_X4_RTR_SECTION 0x7000
+#define mmSRAM_Y2_X5_BANK_BASE 0x7FFC2A8000ull
+#define SRAM_Y2_X5_BANK_MAX_OFFSET 0x4000
+#define SRAM_Y2_X5_BANK_SECTION 0x1000
+#define mmSRAM_Y2_X5_RTR_BASE 0x7FFC2A9000ull
+#define SRAM_Y2_X5_RTR_MAX_OFFSET 0x3340
+#define SRAM_Y2_X5_RTR_SECTION 0x7000
+#define mmSRAM_Y2_X6_BANK_BASE 0x7FFC2B0000ull
+#define SRAM_Y2_X6_BANK_MAX_OFFSET 0x4000
+#define SRAM_Y2_X6_BANK_SECTION 0x1000
+#define mmSRAM_Y2_X6_RTR_BASE 0x7FFC2B1000ull
+#define SRAM_Y2_X6_RTR_MAX_OFFSET 0x3340
+#define SRAM_Y2_X6_RTR_SECTION 0x7000
+#define mmSRAM_Y2_X7_BANK_BASE 0x7FFC2B8000ull
+#define SRAM_Y2_X7_BANK_MAX_OFFSET 0x4000
+#define SRAM_Y2_X7_BANK_SECTION 0x1000
+#define mmSRAM_Y2_X7_RTR_BASE 0x7FFC2B9000ull
+#define SRAM_Y2_X7_RTR_MAX_OFFSET 0x3340
+#define SRAM_Y2_X7_RTR_SECTION 0x7000
+#define mmSRAM_Y3_X0_BANK_BASE 0x7FFC2C0000ull
+#define SRAM_Y3_X0_BANK_MAX_OFFSET 0x4000
+#define SRAM_Y3_X0_BANK_SECTION 0x1000
+#define mmSRAM_Y3_X0_RTR_BASE 0x7FFC2C1000ull
+#define SRAM_Y3_X0_RTR_MAX_OFFSET 0x3340
+#define SRAM_Y3_X0_RTR_SECTION 0x7000
+#define mmSRAM_Y3_X1_BANK_BASE 0x7FFC2C8000ull
+#define SRAM_Y3_X1_BANK_MAX_OFFSET 0x4000
+#define SRAM_Y3_X1_BANK_SECTION 0x1000
+#define mmSRAM_Y3_X1_RTR_BASE 0x7FFC2C9000ull
+#define SRAM_Y3_X1_RTR_MAX_OFFSET 0x3340
+#define SRAM_Y3_X1_RTR_SECTION 0x7000
+#define mmSRAM_Y3_X2_BANK_BASE 0x7FFC2D0000ull
+#define SRAM_Y3_X2_BANK_MAX_OFFSET 0x4000
+#define SRAM_Y3_X2_BANK_SECTION 0x1000
+#define mmSRAM_Y3_X2_RTR_BASE 0x7FFC2D1000ull
+#define SRAM_Y3_X2_RTR_MAX_OFFSET 0x3340
+#define SRAM_Y3_X2_RTR_SECTION 0x7000
+#define mmSRAM_Y3_X3_BANK_BASE 0x7FFC2D8000ull
+#define SRAM_Y3_X3_BANK_MAX_OFFSET 0x4000
+#define SRAM_Y3_X3_BANK_SECTION 0x1000
+#define mmSRAM_Y3_X3_RTR_BASE 0x7FFC2D9000ull
+#define SRAM_Y3_X3_RTR_MAX_OFFSET 0x3340
+#define SRAM_Y3_X3_RTR_SECTION 0x7000
+#define mmSRAM_Y3_X4_BANK_BASE 0x7FFC2E0000ull
+#define SRAM_Y3_X4_BANK_MAX_OFFSET 0x4000
+#define SRAM_Y3_X4_BANK_SECTION 0x1000
+#define mmSRAM_Y3_X4_RTR_BASE 0x7FFC2E1000ull
+#define SRAM_Y3_X4_RTR_MAX_OFFSET 0x3340
+#define SRAM_Y3_X4_RTR_SECTION 0x7000
+#define mmSRAM_Y3_X5_BANK_BASE 0x7FFC2E8000ull
+#define SRAM_Y3_X5_BANK_MAX_OFFSET 0x4000
+#define SRAM_Y3_X5_BANK_SECTION 0x1000
+#define mmSRAM_Y3_X5_RTR_BASE 0x7FFC2E9000ull
+#define SRAM_Y3_X5_RTR_MAX_OFFSET 0x3340
+#define SRAM_Y3_X5_RTR_SECTION 0x7000
+#define mmSRAM_Y3_X6_BANK_BASE 0x7FFC2F0000ull
+#define SRAM_Y3_X6_BANK_MAX_OFFSET 0x4000
+#define SRAM_Y3_X6_BANK_SECTION 0x1000
+#define mmSRAM_Y3_X6_RTR_BASE 0x7FFC2F1000ull
+#define SRAM_Y3_X6_RTR_MAX_OFFSET 0x3340
+#define SRAM_Y3_X6_RTR_SECTION 0x7000
+#define mmSRAM_Y3_X7_BANK_BASE 0x7FFC2F8000ull
+#define SRAM_Y3_X7_BANK_MAX_OFFSET 0x4000
+#define SRAM_Y3_X7_BANK_SECTION 0x1000
+#define mmSRAM_Y3_X7_RTR_BASE 0x7FFC2F9000ull
+#define SRAM_Y3_X7_RTR_MAX_OFFSET 0x3340
+#define SRAM_Y3_X7_RTR_SECTION 0x7000
+#define mmSIF_RTR_0_BASE 0x7FFC300000ull
+#define SIF_RTR_0_MAX_OFFSET 0x6500
+#define SIF_RTR_0_SECTION 0x6000
+#define mmSIF_RTR_CTRL_0_BASE 0x7FFC306000ull
+#define SIF_RTR_CTRL_0_MAX_OFFSET 0xCC00
+#define SIF_RTR_CTRL_0_SECTION 0xA000
+#define mmSIF_RTR_1_BASE 0x7FFC310000ull
+#define SIF_RTR_1_MAX_OFFSET 0x6500
+#define SIF_RTR_1_SECTION 0x6000
+#define mmSIF_RTR_CTRL_1_BASE 0x7FFC316000ull
+#define SIF_RTR_CTRL_1_MAX_OFFSET 0xCC00
+#define SIF_RTR_CTRL_1_SECTION 0xA000
+#define mmSIF_RTR_2_BASE 0x7FFC320000ull
+#define SIF_RTR_2_MAX_OFFSET 0x6500
+#define SIF_RTR_2_SECTION 0x6000
+#define mmSIF_RTR_CTRL_2_BASE 0x7FFC326000ull
+#define SIF_RTR_CTRL_2_MAX_OFFSET 0xCC00
+#define SIF_RTR_CTRL_2_SECTION 0xA000
+#define mmSIF_RTR_3_BASE 0x7FFC330000ull
+#define SIF_RTR_3_MAX_OFFSET 0x6500
+#define SIF_RTR_3_SECTION 0x6000
+#define mmSIF_RTR_CTRL_3_BASE 0x7FFC336000ull
+#define SIF_RTR_CTRL_3_MAX_OFFSET 0xCC00
+#define SIF_RTR_CTRL_3_SECTION 0xA000
+#define mmSIF_RTR_4_BASE 0x7FFC340000ull
+#define SIF_RTR_4_MAX_OFFSET 0x6500
+#define SIF_RTR_4_SECTION 0x6000
+#define mmSIF_RTR_CTRL_4_BASE 0x7FFC346000ull
+#define SIF_RTR_CTRL_4_MAX_OFFSET 0xCC00
+#define SIF_RTR_CTRL_4_SECTION 0xA000
+#define mmSIF_RTR_5_BASE 0x7FFC350000ull
+#define SIF_RTR_5_MAX_OFFSET 0x6500
+#define SIF_RTR_5_SECTION 0x6000
+#define mmSIF_RTR_CTRL_5_BASE 0x7FFC356000ull
+#define SIF_RTR_CTRL_5_MAX_OFFSET 0xCC00
+#define SIF_RTR_CTRL_5_SECTION 0xA000
+#define mmSIF_RTR_6_BASE 0x7FFC360000ull
+#define SIF_RTR_6_MAX_OFFSET 0x6500
+#define SIF_RTR_6_SECTION 0x6000
+#define mmSIF_RTR_CTRL_6_BASE 0x7FFC366000ull
+#define SIF_RTR_CTRL_6_MAX_OFFSET 0xCC00
+#define SIF_RTR_CTRL_6_SECTION 0xA000
+#define mmSIF_RTR_7_BASE 0x7FFC370000ull
+#define SIF_RTR_7_MAX_OFFSET 0x6500
+#define SIF_RTR_7_SECTION 0x6000
+#define mmSIF_RTR_CTRL_7_BASE 0x7FFC376000ull
+#define SIF_RTR_CTRL_7_MAX_OFFSET 0xCC00
+#define SIF_RTR_CTRL_7_SECTION 0xA000
+#define mmNIF_RTR_0_BASE 0x7FFC380000ull
+#define NIF_RTR_0_MAX_OFFSET 0x6500
+#define NIF_RTR_0_SECTION 0x6000
+#define mmNIF_RTR_CTRL_0_BASE 0x7FFC386000ull
+#define NIF_RTR_CTRL_0_MAX_OFFSET 0xCC00
+#define NIF_RTR_CTRL_0_SECTION 0xA000
+#define mmNIF_RTR_1_BASE 0x7FFC390000ull
+#define NIF_RTR_1_MAX_OFFSET 0x6500
+#define NIF_RTR_1_SECTION 0x6000
+#define mmNIF_RTR_CTRL_1_BASE 0x7FFC396000ull
+#define NIF_RTR_CTRL_1_MAX_OFFSET 0xCC00
+#define NIF_RTR_CTRL_1_SECTION 0xA000
+#define mmNIF_RTR_2_BASE 0x7FFC3A0000ull
+#define NIF_RTR_2_MAX_OFFSET 0x6500
+#define NIF_RTR_2_SECTION 0x6000
+#define mmNIF_RTR_CTRL_2_BASE 0x7FFC3A6000ull
+#define NIF_RTR_CTRL_2_MAX_OFFSET 0xCC00
+#define NIF_RTR_CTRL_2_SECTION 0xA000
+#define mmNIF_RTR_3_BASE 0x7FFC3B0000ull
+#define NIF_RTR_3_MAX_OFFSET 0x6500
+#define NIF_RTR_3_SECTION 0x6000
+#define mmNIF_RTR_CTRL_3_BASE 0x7FFC3B6000ull
+#define NIF_RTR_CTRL_3_MAX_OFFSET 0xCC00
+#define NIF_RTR_CTRL_3_SECTION 0xA000
+#define mmNIF_RTR_4_BASE 0x7FFC3C0000ull
+#define NIF_RTR_4_MAX_OFFSET 0x6500
+#define NIF_RTR_4_SECTION 0x6000
+#define mmNIF_RTR_CTRL_4_BASE 0x7FFC3C6000ull
+#define NIF_RTR_CTRL_4_MAX_OFFSET 0xCC00
+#define NIF_RTR_CTRL_4_SECTION 0xA000
+#define mmNIF_RTR_5_BASE 0x7FFC3D0000ull
+#define NIF_RTR_5_MAX_OFFSET 0x6500
+#define NIF_RTR_5_SECTION 0x6000
+#define mmNIF_RTR_CTRL_5_BASE 0x7FFC3D6000ull
+#define NIF_RTR_CTRL_5_MAX_OFFSET 0xCC00
+#define NIF_RTR_CTRL_5_SECTION 0xA000
+#define mmNIF_RTR_6_BASE 0x7FFC3E0000ull
+#define NIF_RTR_6_MAX_OFFSET 0x6500
+#define NIF_RTR_6_SECTION 0x6000
+#define mmNIF_RTR_CTRL_6_BASE 0x7FFC3E6000ull
+#define NIF_RTR_CTRL_6_MAX_OFFSET 0xCC00
+#define NIF_RTR_CTRL_6_SECTION 0xA000
+#define mmNIF_RTR_7_BASE 0x7FFC3F0000ull
+#define NIF_RTR_7_MAX_OFFSET 0x6500
+#define NIF_RTR_7_SECTION 0x6000
+#define mmNIF_RTR_CTRL_7_BASE 0x7FFC3F6000ull
+#define NIF_RTR_CTRL_7_MAX_OFFSET 0xCC00
+#define NIF_RTR_CTRL_7_SECTION 0x4B000
+#define mmCPU_CA53_CFG_BASE 0x7FFC441000ull
+#define CPU_CA53_CFG_MAX_OFFSET 0x2180
+#define CPU_CA53_CFG_SECTION 0x1000
+#define mmCPU_IF_BASE 0x7FFC442000ull
+#define CPU_IF_MAX_OFFSET 0x43C0
+#define CPU_IF_SECTION 0x2000
+#define mmCPU_TIMESTAMP_BASE 0x7FFC444000ull
+#define CPU_TIMESTAMP_MAX_OFFSET 0x1000
+#define CPU_TIMESTAMP_SECTION 0x3C000
+#define mmDMA_IF_W_S_BASE 0x7FFC480000ull
+#define DMA_IF_W_S_MAX_OFFSET 0x8380
+#define DMA_IF_W_S_SECTION 0x1000
+#define mmDMA_IF_W_S_DOWN_CH0_BASE 0x7FFC481000ull
+#define DMA_IF_W_S_DOWN_CH0_MAX_OFFSET 0xCC00
+#define DMA_IF_W_S_DOWN_CH0_SECTION 0x1000
+#define mmDMA_IF_W_S_DOWN_CH1_BASE 0x7FFC482000ull
+#define DMA_IF_W_S_DOWN_CH1_MAX_OFFSET 0xCC00
+#define DMA_IF_W_S_DOWN_CH1_SECTION 0x5000
+#define mmDMA_W_PLL_BASE 0x7FFC487000ull
+#define DMA_W_PLL_MAX_OFFSET 0x5200
+#define DMA_W_PLL_SECTION 0x1000
+#define mmIF_W_PLL_BASE 0x7FFC488000ull
+#define IF_W_PLL_MAX_OFFSET 0x5200
+#define IF_W_PLL_SECTION 0x1000
+#define mmDMA_IF_W_S_DOWN_BASE 0x7FFC489000ull
+#define DMA_IF_W_S_DOWN_MAX_OFFSET 0x1500
+#define DMA_IF_W_S_DOWN_SECTION 0x7000
+#define mmSYNC_MNGR_GLBL_W_S_BASE 0x7FFC490000ull
+#define SYNC_MNGR_GLBL_W_S_MAX_OFFSET 0x6C00
+#define SYNC_MNGR_GLBL_W_S_SECTION 0x1000
+#define mmSYNC_MNGR_OBJS_W_S_BASE 0x7FFC491000ull
+#define SYNC_MNGR_OBJS_W_S_MAX_OFFSET 0x5C00
+#define SYNC_MNGR_OBJS_W_S_SECTION 0xF000
+#define mmDMA_IF_E_S_BASE 0x7FFC4A0000ull
+#define DMA_IF_E_S_MAX_OFFSET 0x8380
+#define DMA_IF_E_S_SECTION 0x1000
+#define mmDMA_IF_E_S_DOWN_CH0_BASE 0x7FFC4A1000ull
+#define DMA_IF_E_S_DOWN_CH0_MAX_OFFSET 0xCC00
+#define DMA_IF_E_S_DOWN_CH0_SECTION 0x1000
+#define mmDMA_IF_E_S_DOWN_CH1_BASE 0x7FFC4A2000ull
+#define DMA_IF_E_S_DOWN_CH1_MAX_OFFSET 0xCC00
+#define DMA_IF_E_S_DOWN_CH1_SECTION 0x5000
+#define mmIF_E_PLL_BASE 0x7FFC4A7000ull
+#define IF_E_PLL_MAX_OFFSET 0x5200
+#define IF_E_PLL_SECTION 0x1000
+#define mmDMA_E_PLL_BASE 0x7FFC4A8000ull
+#define DMA_E_PLL_MAX_OFFSET 0x5200
+#define DMA_E_PLL_SECTION 0x1000
+#define mmDMA_IF_E_S_DOWN_BASE 0x7FFC4A9000ull
+#define DMA_IF_E_S_DOWN_MAX_OFFSET 0x1500
+#define DMA_IF_E_S_DOWN_SECTION 0x7000
+#define mmSYNC_MNGR_GLBL_E_S_BASE 0x7FFC4B0000ull
+#define SYNC_MNGR_GLBL_E_S_MAX_OFFSET 0x6C00
+#define SYNC_MNGR_GLBL_E_S_SECTION 0x1000
+#define mmSYNC_MNGR_OBJS_E_S_BASE 0x7FFC4B1000ull
+#define SYNC_MNGR_OBJS_E_S_MAX_OFFSET 0x5C00
+#define SYNC_MNGR_OBJS_E_S_SECTION 0xF000
+#define mmDMA_IF_W_N_BASE 0x7FFC4C0000ull
+#define DMA_IF_W_N_MAX_OFFSET 0x8380
+#define DMA_IF_W_N_SECTION 0x1000
+#define mmDMA_IF_W_N_DOWN_CH0_BASE 0x7FFC4C1000ull
+#define DMA_IF_W_N_DOWN_CH0_MAX_OFFSET 0xCC00
+#define DMA_IF_W_N_DOWN_CH0_SECTION 0x1000
+#define mmDMA_IF_W_N_DOWN_CH1_BASE 0x7FFC4C2000ull
+#define DMA_IF_W_N_DOWN_CH1_MAX_OFFSET 0xCC00
+#define DMA_IF_W_N_DOWN_CH1_SECTION 0x5000
+#define mmMESH_W_PLL_BASE 0x7FFC4C7000ull
+#define MESH_W_PLL_MAX_OFFSET 0x5200
+#define MESH_W_PLL_SECTION 0x1000
+#define mmSRAM_W_PLL_BASE 0x7FFC4C8000ull
+#define SRAM_W_PLL_MAX_OFFSET 0x5200
+#define SRAM_W_PLL_SECTION 0x1000
+#define mmDMA_IF_W_N_DOWN_BASE 0x7FFC4C9000ull
+#define DMA_IF_W_N_DOWN_MAX_OFFSET 0x1500
+#define DMA_IF_W_N_DOWN_SECTION 0x7000
+#define mmSYNC_MNGR_GLBL_W_N_BASE 0x7FFC4D0000ull
+#define SYNC_MNGR_GLBL_W_N_MAX_OFFSET 0x6C00
+#define SYNC_MNGR_GLBL_W_N_SECTION 0x1000
+#define mmSYNC_MNGR_OBJS_W_N_BASE 0x7FFC4D1000ull
+#define SYNC_MNGR_OBJS_W_N_MAX_OFFSET 0x5C00
+#define SYNC_MNGR_OBJS_W_N_SECTION 0xF000
+#define mmDMA_IF_E_N_BASE 0x7FFC4E0000ull
+#define DMA_IF_E_N_MAX_OFFSET 0x8380
+#define DMA_IF_E_N_SECTION 0x1000
+#define mmDMA_IF_E_N_DOWN_CH0_BASE 0x7FFC4E1000ull
+#define DMA_IF_E_N_DOWN_CH0_MAX_OFFSET 0xCC00
+#define DMA_IF_E_N_DOWN_CH0_SECTION 0x1000
+#define mmDMA_IF_E_N_DOWN_CH1_BASE 0x7FFC4E2000ull
+#define DMA_IF_E_N_DOWN_CH1_MAX_OFFSET 0xCC00
+#define DMA_IF_E_N_DOWN_CH1_SECTION 0x5000
+#define mmMESH_E_PLL_BASE 0x7FFC4E7000ull
+#define MESH_E_PLL_MAX_OFFSET 0x5200
+#define MESH_E_PLL_SECTION 0x1000
+#define mmSRAM_E_PLL_BASE 0x7FFC4E8000ull
+#define SRAM_E_PLL_MAX_OFFSET 0x5200
+#define SRAM_E_PLL_SECTION 0x1000
+#define mmDMA_IF_E_N_DOWN_BASE 0x7FFC4E9000ull
+#define DMA_IF_E_N_DOWN_MAX_OFFSET 0x1500
+#define DMA_IF_E_N_DOWN_SECTION 0x7000
+#define mmSYNC_MNGR_GLBL_E_N_BASE 0x7FFC4F0000ull
+#define SYNC_MNGR_GLBL_E_N_MAX_OFFSET 0x6C00
+#define SYNC_MNGR_GLBL_E_N_SECTION 0x1000
+#define mmSYNC_MNGR_OBJS_E_N_BASE 0x7FFC4F1000ull
+#define SYNC_MNGR_OBJS_E_N_MAX_OFFSET 0x5C00
+#define SYNC_MNGR_OBJS_E_N_SECTION 0xF000
+#define mmDMA0_CORE_BASE 0x7FFC500000ull
+#define DMA0_CORE_MAX_OFFSET 0x23C0
+#define DMA0_CORE_SECTION 0x8000
+#define mmDMA0_QM_BASE 0x7FFC508000ull
+#define DMA0_QM_MAX_OFFSET 0xD040
+#define DMA0_QM_SECTION 0x18000
+#define mmDMA1_CORE_BASE 0x7FFC520000ull
+#define DMA1_CORE_MAX_OFFSET 0x23C0
+#define DMA1_CORE_SECTION 0x8000
+#define mmDMA1_QM_BASE 0x7FFC528000ull
+#define DMA1_QM_MAX_OFFSET 0xD040
+#define DMA1_QM_SECTION 0x18000
+#define mmDMA2_CORE_BASE 0x7FFC540000ull
+#define DMA2_CORE_MAX_OFFSET 0x23C0
+#define DMA2_CORE_SECTION 0x8000
+#define mmDMA2_QM_BASE 0x7FFC548000ull
+#define DMA2_QM_MAX_OFFSET 0xD040
+#define DMA2_QM_SECTION 0x18000
+#define mmDMA3_CORE_BASE 0x7FFC560000ull
+#define DMA3_CORE_MAX_OFFSET 0x23C0
+#define DMA3_CORE_SECTION 0x8000
+#define mmDMA3_QM_BASE 0x7FFC568000ull
+#define DMA3_QM_MAX_OFFSET 0xD040
+#define DMA3_QM_SECTION 0x18000
+#define mmDMA4_CORE_BASE 0x7FFC580000ull
+#define DMA4_CORE_MAX_OFFSET 0x23C0
+#define DMA4_CORE_SECTION 0x8000
+#define mmDMA4_QM_BASE 0x7FFC588000ull
+#define DMA4_QM_MAX_OFFSET 0xD040
+#define DMA4_QM_SECTION 0x18000
+#define mmDMA5_CORE_BASE 0x7FFC5A0000ull
+#define DMA5_CORE_MAX_OFFSET 0x23C0
+#define DMA5_CORE_SECTION 0x8000
+#define mmDMA5_QM_BASE 0x7FFC5A8000ull
+#define DMA5_QM_MAX_OFFSET 0xD040
+#define DMA5_QM_SECTION 0x18000
+#define mmDMA6_CORE_BASE 0x7FFC5C0000ull
+#define DMA6_CORE_MAX_OFFSET 0x23C0
+#define DMA6_CORE_SECTION 0x8000
+#define mmDMA6_QM_BASE 0x7FFC5C8000ull
+#define DMA6_QM_MAX_OFFSET 0xD040
+#define DMA6_QM_SECTION 0x18000
+#define mmDMA7_CORE_BASE 0x7FFC5E0000ull
+#define DMA7_CORE_MAX_OFFSET 0x23C0
+#define DMA7_CORE_SECTION 0x8000
+#define mmDMA7_QM_BASE 0x7FFC5E8000ull
+#define DMA7_QM_MAX_OFFSET 0xD040
+#define DMA7_QM_SECTION 0x18000
+#define mmHBM0_BASE 0x7FFC600000ull
+#define HBM0_MAX_OFFSET 0x8F58
+#define HBM0_SECTION 0x80000
+#define mmHBM1_BASE 0x7FFC680000ull
+#define HBM1_MAX_OFFSET 0x8F58
+#define HBM1_SECTION 0x80000
+#define mmHBM2_BASE 0x7FFC700000ull
+#define HBM2_MAX_OFFSET 0x8F58
+#define HBM2_SECTION 0x80000
+#define mmHBM3_BASE 0x7FFC780000ull
+#define HBM3_MAX_OFFSET 0x8F58
+#define HBM3_SECTION 0x80000
+#define mmGIC_BASE 0x7FFC800000ull
+#define GIC_MAX_OFFSET 0x10000
+#define GIC_SECTION 0x401000
+#define mmPCIE_WRAP_BASE 0x7FFCC01000ull
+#define PCIE_WRAP_MAX_OFFSET 0xDF00
+#define PCIE_WRAP_SECTION 0x1000
+#define mmPCIE_DBI_BASE 0x7FFCC02000ull
+#define PCIE_DBI_MAX_OFFSET 0xC040
+#define PCIE_DBI_SECTION 0x2000
+#define mmPCIE_CORE_BASE 0x7FFCC04000ull
+#define PCIE_CORE_MAX_OFFSET 0x9BC0
+#define PCIE_CORE_SECTION 0x3000
+#define mmPCIE_AUX_BASE 0x7FFCC07000ull
+#define PCIE_AUX_MAX_OFFSET 0x9C40
+#define PCIE_AUX_SECTION 0x9000
+#define mmPCIE_PHY_BASE 0x7FFCC10000ull
+#define PCIE_PHY_MAX_OFFSET 0x9640
+#define PCIE_PHY_SECTION 0x1000
+#define mmMMU_UP_BASE 0x7FFCC11000ull
+#define MMU_UP_MAX_OFFSET 0x7000
+#define MMU_UP_SECTION 0x1000
+#define mmSTLB_BASE 0x7FFCC12000ull
+#define STLB_MAX_OFFSET 0x8800
+#define STLB_SECTION 0x1000
+#define mmPCIE_MSI_BASE 0x7FFCC13000ull
+#define PCIE_MSI_MAX_OFFSET 0x8000
+#define PCIE_MSI_SECTION 0x2D000
+#define mmPSOC_I2C_M0_BASE 0x7FFCC40000ull
+#define PSOC_I2C_M0_MAX_OFFSET 0x1000
+#define PSOC_I2C_M0_SECTION 0x1000
+#define mmPSOC_I2C_M1_BASE 0x7FFCC41000ull
+#define PSOC_I2C_M1_MAX_OFFSET 0x1000
+#define PSOC_I2C_M1_SECTION 0x1000
+#define mmPSOC_I2C_S_BASE 0x7FFCC42000ull
+#define PSOC_I2C_S_MAX_OFFSET 0x1000
+#define PSOC_I2C_S_SECTION 0x1000
+#define mmPSOC_SPI_BASE 0x7FFCC43000ull
+#define PSOC_SPI_MAX_OFFSET 0x1000
+#define PSOC_SPI_SECTION 0x2000
+#define mmPSOC_UART_0_BASE 0x7FFCC45000ull
+#define PSOC_UART_0_MAX_OFFSET 0x1000
+#define PSOC_UART_0_SECTION 0x1000
+#define mmPSOC_UART_1_BASE 0x7FFCC46000ull
+#define PSOC_UART_1_MAX_OFFSET 0x1000
+#define PSOC_UART_1_SECTION 0x1000
+#define mmPSOC_TIMER_BASE 0x7FFCC47000ull
+#define PSOC_TIMER_MAX_OFFSET 0x1000
+#define PSOC_TIMER_SECTION 0x1000
+#define mmPSOC_WDOG_BASE 0x7FFCC48000ull
+#define PSOC_WDOG_MAX_OFFSET 0x1000
+#define PSOC_WDOG_SECTION 0x1000
+#define mmPSOC_TIMESTAMP_BASE 0x7FFCC49000ull
+#define PSOC_TIMESTAMP_MAX_OFFSET 0x1000
+#define PSOC_TIMESTAMP_SECTION 0x1000
+#define mmPSOC_EFUSE_BASE 0x7FFCC4A000ull
+#define PSOC_EFUSE_MAX_OFFSET 0x3040
+#define PSOC_EFUSE_SECTION 0x1000
+#define mmPSOC_GLOBAL_CONF_BASE 0x7FFCC4B000ull
+#define PSOC_GLOBAL_CONF_MAX_OFFSET 0xCD80
+#define PSOC_GLOBAL_CONF_SECTION 0x1000
+#define mmPSOC_GPIO0_BASE 0x7FFCC4C000ull
+#define PSOC_GPIO0_MAX_OFFSET 0x1000
+#define PSOC_GPIO0_SECTION 0x1000
+#define mmPSOC_GPIO1_BASE 0x7FFCC4D000ull
+#define PSOC_GPIO1_MAX_OFFSET 0x1000
+#define PSOC_GPIO1_SECTION 0x1000
+#define mmPSOC_BTL_BASE 0x7FFCC4E000ull
+#define PSOC_BTL_MAX_OFFSET 0x1480
+#define PSOC_BTL_SECTION 0x1000
+#define mmPSOC_CS_TRACE_BASE 0x7FFCC4F000ull
+#define PSOC_CS_TRACE_MAX_OFFSET 0x1680
+#define PSOC_CS_TRACE_SECTION 0x1000
+#define mmPSOC_GPIO2_BASE 0x7FFCC50000ull
+#define PSOC_GPIO2_MAX_OFFSET 0x1000
+#define PSOC_GPIO2_SECTION 0x1000
+#define mmPSOC_GPIO3_BASE 0x7FFCC51000ull
+#define PSOC_GPIO3_MAX_OFFSET 0x1000
+#define PSOC_GPIO3_SECTION 0x1000
+#define mmPSOC_GPIO4_BASE 0x7FFCC52000ull
+#define PSOC_GPIO4_MAX_OFFSET 0x1000
+#define PSOC_GPIO4_SECTION 0x1000
+#define mmPSOC_DFT_EFUSE_BASE 0x7FFCC53000ull
+#define PSOC_DFT_EFUSE_MAX_OFFSET 0x3040
+#define PSOC_DFT_EFUSE_SECTION 0x1000
+#define mmPSOC_RPM_0_BASE 0x7FFCC54000ull
+#define PSOC_RPM_0_MAX_OFFSET 0x8800
+#define PSOC_RPM_0_SECTION 0x1000
+#define mmPSOC_RPM_1_BASE 0x7FFCC55000ull
+#define PSOC_RPM_1_MAX_OFFSET 0x8800
+#define PSOC_RPM_1_SECTION 0x1000
+#define mmPSOC_RPM_2_BASE 0x7FFCC56000ull
+#define PSOC_RPM_2_MAX_OFFSET 0x8800
+#define PSOC_RPM_2_SECTION 0x1000
+#define mmPSOC_RPM_3_BASE 0x7FFCC57000ull
+#define PSOC_RPM_3_MAX_OFFSET 0x8800
+#define PSOC_RPM_3_SECTION 0x19000
+#define mmPSOC_CPU_PLL_BASE 0x7FFCC70000ull
+#define PSOC_CPU_PLL_MAX_OFFSET 0x5200
+#define PSOC_CPU_PLL_SECTION 0x1000
+#define mmPSOC_MME_PLL_BASE 0x7FFCC71000ull
+#define PSOC_MME_PLL_MAX_OFFSET 0x5200
+#define PSOC_MME_PLL_SECTION 0x1000
+#define mmPSOC_PCI_PLL_BASE 0x7FFCC72000ull
+#define PSOC_PCI_PLL_MAX_OFFSET 0x5200
+#define PSOC_PCI_PLL_SECTION 0x1000
+#define mmPSOC_TPC_PLL_BASE 0x7FFCC73000ull
+#define PSOC_TPC_PLL_MAX_OFFSET 0x5200
+#define PSOC_TPC_PLL_SECTION 0x1000
+#define mmPSOC_HBM_PLL_BASE 0x7FFCC74000ull
+#define PSOC_HBM_PLL_MAX_OFFSET 0x5200
+#define PSOC_HBM_PLL_SECTION 0x1000
+#define mmPSOC_PM_BASE 0x7FFCC75000ull
+#define PSOC_PM_MAX_OFFSET 0x1F00
+#define PSOC_PM_SECTION 0x1000
+#define mmPSOC_TS_BASE 0x7FFCC76000ull
+#define PSOC_TS_MAX_OFFSET 0xE640
+#define PSOC_TS_SECTION 0x2000
+#define mmPSOC_PWM0_BASE 0x7FFCC78000ull
+#define PSOC_PWM0_MAX_OFFSET 0x5800
+#define PSOC_PWM0_SECTION 0x1000
+#define mmPSOC_PWM1_BASE 0x7FFCC79000ull
+#define PSOC_PWM1_MAX_OFFSET 0x5800
+#define PSOC_PWM1_SECTION 0x1000
+#define mmPSOC_PWM2_BASE 0x7FFCC7A000ull
+#define PSOC_PWM2_MAX_OFFSET 0x5800
+#define PSOC_PWM2_SECTION 0x1000
+#define mmPSOC_PWM3_BASE 0x7FFCC7B000ull
+#define PSOC_PWM3_MAX_OFFSET 0x5800
+#define PSOC_PWM3_SECTION 0x1000
+#define mmPSOC_GPIO5_BASE 0x7FFCC7C000ull
+#define PSOC_GPIO5_MAX_OFFSET 0x1000
+#define PSOC_GPIO5_SECTION 0x1000
+#define mmPSOC_GPIO6_BASE 0x7FFCC7D000ull
+#define PSOC_GPIO6_MAX_OFFSET 0x1000
+#define PSOC_GPIO6_SECTION 0x3000
+#define mmPCIE_PMA_0_BASE 0x7FFCC80000ull
+#define PCIE_PMA_0_MAX_OFFSET 0x10003
+#define PCIE_PMA_0_SECTION 0x10000
+#define mmPCIE_PMA_1_BASE 0x7FFCC90000ull
+#define PCIE_PMA_1_MAX_OFFSET 0x10003
+#define PCIE_PMA_1_SECTION 0x10000
+#define mmPCIE_PMA_2_BASE 0x7FFCCA0000ull
+#define PCIE_PMA_2_MAX_OFFSET 0x10003
+#define PCIE_PMA_2_SECTION 0x10000
+#define mmPCIE_PMA_3_BASE 0x7FFCCB0000ull
+#define PCIE_PMA_3_MAX_OFFSET 0x10003
+#define PCIE_PMA_3_SECTION 0x10000
+#define mmNIC0_MAC_CH0_BASE 0x7FFCCC0000ull
+#define NIC0_MAC_CH0_MAX_OFFSET 0x8400
+#define NIC0_MAC_CH0_SECTION 0x1000
+#define mmNIC0_MAC_CH1_BASE 0x7FFCCC1000ull
+#define NIC0_MAC_CH1_MAX_OFFSET 0x8400
+#define NIC0_MAC_CH1_SECTION 0x1000
+#define mmNIC0_MAC_CH2_BASE 0x7FFCCC2000ull
+#define NIC0_MAC_CH2_MAX_OFFSET 0x8400
+#define NIC0_MAC_CH2_SECTION 0x1000
+#define mmNIC0_MAC_CH3_BASE 0x7FFCCC3000ull
+#define NIC0_MAC_CH3_MAX_OFFSET 0x8400
+#define NIC0_MAC_CH3_SECTION 0x1000
+#define mmNIC0_STAT_BASE 0x7FFCCC4000ull
+#define NIC0_STAT_MAX_OFFSET 0x4D00
+#define NIC0_STAT_SECTION 0x1000
+#define mmNIC0_MAC_XPCS91_BASE 0x7FFCCC5000ull
+#define NIC0_MAC_XPCS91_MAX_OFFSET 0x2380
+#define NIC0_MAC_XPCS91_SECTION 0x3000
+#define mmNIC0_MAC_CORE_BASE 0x7FFCCC8000ull
+#define NIC0_MAC_CORE_MAX_OFFSET 0x5400
+#define NIC0_MAC_CORE_SECTION 0x1000
+#define mmNIC0_MAC_AUX_BASE 0x7FFCCC9000ull
+#define NIC0_MAC_AUX_MAX_OFFSET 0x3000
+#define NIC0_MAC_AUX_SECTION 0xF000
+#define mmNIC0_PHY_BASE 0x7FFCCD8000ull
+#define NIC0_PHY_MAX_OFFSET 0x3400
+#define NIC0_PHY_SECTION 0x8000
+#define mmNIC0_QM0_BASE 0x7FFCCE0000ull
+#define NIC0_QM0_MAX_OFFSET 0xD040
+#define NIC0_QM0_SECTION 0x2000
+#define mmNIC0_QM1_BASE 0x7FFCCE2000ull
+#define NIC0_QM1_MAX_OFFSET 0xD040
+#define NIC0_QM1_SECTION 0x2000
+#define mmNIC0_QPC0_BASE 0x7FFCCE4000ull
+#define NIC0_QPC0_MAX_OFFSET 0x7140
+#define NIC0_QPC0_SECTION 0x1000
+#define mmNIC0_QPC1_BASE 0x7FFCCE5000ull
+#define NIC0_QPC1_MAX_OFFSET 0x7140
+#define NIC0_QPC1_SECTION 0x3000
+#define mmNIC0_RXB_BASE 0x7FFCCE8000ull
+#define NIC0_RXB_MAX_OFFSET 0x6040
+#define NIC0_RXB_SECTION 0x1000
+#define mmNIC0_RXE0_BASE 0x7FFCCE9000ull
+#define NIC0_RXE0_MAX_OFFSET 0x2FC0
+#define NIC0_RXE0_SECTION 0x1000
+#define mmNIC0_RXE1_BASE 0x7FFCCEA000ull
+#define NIC0_RXE1_MAX_OFFSET 0x2FC0
+#define NIC0_RXE1_SECTION 0x1000
+#define mmNIC0_RX_GW_BASE 0x7FFCCEB000ull
+#define NIC0_RX_GW_MAX_OFFSET 0x4540
+#define NIC0_RX_GW_SECTION 0x5000
+#define mmNIC0_TXS0_BASE 0x7FFCCF0000ull
+#define NIC0_TXS0_MAX_OFFSET 0x19C0
+#define NIC0_TXS0_SECTION 0x1000
+#define mmNIC0_TXS1_BASE 0x7FFCCF1000ull
+#define NIC0_TXS1_MAX_OFFSET 0x19C0
+#define NIC0_TXS1_SECTION 0x1000
+#define mmNIC0_TXE0_BASE 0x7FFCCF2000ull
+#define NIC0_TXE0_MAX_OFFSET 0x2040
+#define NIC0_TXE0_SECTION 0x1000
+#define mmNIC0_TXE1_BASE 0x7FFCCF3000ull
+#define NIC0_TXE1_MAX_OFFSET 0x2040
+#define NIC0_TXE1_SECTION 0x1000
+#define mmNIC0_TXB_BASE 0x7FFCCF4000ull
+#define NIC0_TXB_MAX_OFFSET 0xD400
+#define NIC0_TXB_SECTION 0x1000
+#define mmNIC0_TMR_BASE 0x7FFCCF5000ull
+#define NIC0_TMR_MAX_OFFSET 0x1600
+#define NIC0_TMR_SECTION 0x1000
+#define mmNIC0_TX_GW_BASE 0x7FFCCF6000ull
+#define NIC0_TX_GW_MAX_OFFSET 0x1400
+#define NIC0_TX_GW_SECTION 0x2000
+#define mmNIC0_TS_BASE 0x7FFCCF8000ull
+#define NIC0_TS_MAX_OFFSET 0xE640
+#define NIC0_TS_SECTION 0x1000
+#define mmNIC0_PLL_BASE 0x7FFCCF9000ull
+#define NIC0_PLL_MAX_OFFSET 0x5200
+#define NIC0_PLL_SECTION 0x1000
+#define mmNIC0_PM_BASE 0x7FFCCFA000ull
+#define NIC0_PM_MAX_OFFSET 0x1F00
+#define NIC0_PM_SECTION 0x6000
+#define mmNIC1_MAC_CH0_BASE 0x7FFCD00000ull
+#define NIC1_MAC_CH0_MAX_OFFSET 0x8400
+#define NIC1_MAC_CH0_SECTION 0x1000
+#define mmNIC1_MAC_CH1_BASE 0x7FFCD01000ull
+#define NIC1_MAC_CH1_MAX_OFFSET 0x8400
+#define NIC1_MAC_CH1_SECTION 0x1000
+#define mmNIC1_MAC_CH2_BASE 0x7FFCD02000ull
+#define NIC1_MAC_CH2_MAX_OFFSET 0x8400
+#define NIC1_MAC_CH2_SECTION 0x1000
+#define mmNIC1_MAC_CH3_BASE 0x7FFCD03000ull
+#define NIC1_MAC_CH3_MAX_OFFSET 0x8400
+#define NIC1_MAC_CH3_SECTION 0x1000
+#define mmNIC1_STAT_BASE 0x7FFCD04000ull
+#define NIC1_STAT_MAX_OFFSET 0x4D00
+#define NIC1_STAT_SECTION 0x1000
+#define mmNIC1_MAC_XPCS91_BASE 0x7FFCD05000ull
+#define NIC1_MAC_XPCS91_MAX_OFFSET 0x2380
+#define NIC1_MAC_XPCS91_SECTION 0x3000
+#define mmNIC1_MAC_CORE_BASE 0x7FFCD08000ull
+#define NIC1_MAC_CORE_MAX_OFFSET 0x5400
+#define NIC1_MAC_CORE_SECTION 0x1000
+#define mmNIC1_MAC_AUX_BASE 0x7FFCD09000ull
+#define NIC1_MAC_AUX_MAX_OFFSET 0x3000
+#define NIC1_MAC_AUX_SECTION 0xF000
+#define mmNIC1_PHY_BASE 0x7FFCD18000ull
+#define NIC1_PHY_MAX_OFFSET 0x3400
+#define NIC1_PHY_SECTION 0x8000
+#define mmNIC1_QM0_BASE 0x7FFCD20000ull
+#define NIC1_QM0_MAX_OFFSET 0xD040
+#define NIC1_QM0_SECTION 0x2000
+#define mmNIC1_QM1_BASE 0x7FFCD22000ull
+#define NIC1_QM1_MAX_OFFSET 0xD040
+#define NIC1_QM1_SECTION 0x2000
+#define mmNIC1_QPC0_BASE 0x7FFCD24000ull
+#define NIC1_QPC0_MAX_OFFSET 0x7140
+#define NIC1_QPC0_SECTION 0x1000
+#define mmNIC1_QPC1_BASE 0x7FFCD25000ull
+#define NIC1_QPC1_MAX_OFFSET 0x7140
+#define NIC1_QPC1_SECTION 0x3000
+#define mmNIC1_RXB_BASE 0x7FFCD28000ull
+#define NIC1_RXB_MAX_OFFSET 0x6040
+#define NIC1_RXB_SECTION 0x1000
+#define mmNIC1_RXE0_BASE 0x7FFCD29000ull
+#define NIC1_RXE0_MAX_OFFSET 0x2FC0
+#define NIC1_RXE0_SECTION 0x1000
+#define mmNIC1_RXE1_BASE 0x7FFCD2A000ull
+#define NIC1_RXE1_MAX_OFFSET 0x2FC0
+#define NIC1_RXE1_SECTION 0x1000
+#define mmNIC1_RX_GW_BASE 0x7FFCD2B000ull
+#define NIC1_RX_GW_MAX_OFFSET 0x4540
+#define NIC1_RX_GW_SECTION 0x5000
+#define mmNIC1_TXS0_BASE 0x7FFCD30000ull
+#define NIC1_TXS0_MAX_OFFSET 0x19C0
+#define NIC1_TXS0_SECTION 0x1000
+#define mmNIC1_TXS1_BASE 0x7FFCD31000ull
+#define NIC1_TXS1_MAX_OFFSET 0x19C0
+#define NIC1_TXS1_SECTION 0x1000
+#define mmNIC1_TXE0_BASE 0x7FFCD32000ull
+#define NIC1_TXE0_MAX_OFFSET 0x2040
+#define NIC1_TXE0_SECTION 0x1000
+#define mmNIC1_TXE1_BASE 0x7FFCD33000ull
+#define NIC1_TXE1_MAX_OFFSET 0x2040
+#define NIC1_TXE1_SECTION 0x1000
+#define mmNIC1_TXB_BASE 0x7FFCD34000ull
+#define NIC1_TXB_MAX_OFFSET 0xD400
+#define NIC1_TXB_SECTION 0x1000
+#define mmNIC1_TMR_BASE 0x7FFCD35000ull
+#define NIC1_TMR_MAX_OFFSET 0x1600
+#define NIC1_TMR_SECTION 0x1000
+#define mmNIC1_TX_GW_BASE 0x7FFCD36000ull
+#define NIC1_TX_GW_MAX_OFFSET 0x1400
+#define NIC1_TX_GW_SECTION 0x2000
+#define mmNIC1_TS_BASE 0x7FFCD38000ull
+#define NIC1_TS_MAX_OFFSET 0xE640
+#define NIC1_TS_SECTION 0x1000
+#define mmNIC1_PLL_BASE 0x7FFCD39000ull
+#define NIC1_PLL_MAX_OFFSET 0x5200
+#define NIC1_PLL_SECTION 0x1000
+#define mmNIC1_PM_BASE 0x7FFCD3A000ull
+#define NIC1_PM_MAX_OFFSET 0x1F00
+#define NIC1_PM_SECTION 0x6000
+#define mmNIC2_MAC_CH0_BASE 0x7FFCD40000ull
+#define NIC2_MAC_CH0_MAX_OFFSET 0x8400
+#define NIC2_MAC_CH0_SECTION 0x1000
+#define mmNIC2_MAC_CH1_BASE 0x7FFCD41000ull
+#define NIC2_MAC_CH1_MAX_OFFSET 0x8400
+#define NIC2_MAC_CH1_SECTION 0x1000
+#define mmNIC2_MAC_CH2_BASE 0x7FFCD42000ull
+#define NIC2_MAC_CH2_MAX_OFFSET 0x8400
+#define NIC2_MAC_CH2_SECTION 0x1000
+#define mmNIC2_MAC_CH3_BASE 0x7FFCD43000ull
+#define NIC2_MAC_CH3_MAX_OFFSET 0x8400
+#define NIC2_MAC_CH3_SECTION 0x1000
+#define mmNIC2_STAT_BASE 0x7FFCD44000ull
+#define NIC2_STAT_MAX_OFFSET 0x4D00
+#define NIC2_STAT_SECTION 0x1000
+#define mmNIC2_MAC_XPCS91_BASE 0x7FFCD45000ull
+#define NIC2_MAC_XPCS91_MAX_OFFSET 0x2380
+#define NIC2_MAC_XPCS91_SECTION 0x3000
+#define mmNIC2_MAC_CORE_BASE 0x7FFCD48000ull
+#define NIC2_MAC_CORE_MAX_OFFSET 0x5400
+#define NIC2_MAC_CORE_SECTION 0x1000
+#define mmNIC2_MAC_AUX_BASE 0x7FFCD49000ull
+#define NIC2_MAC_AUX_MAX_OFFSET 0x3000
+#define NIC2_MAC_AUX_SECTION 0xF000
+#define mmNIC2_PHY_BASE 0x7FFCD58000ull
+#define NIC2_PHY_MAX_OFFSET 0x3400
+#define NIC2_PHY_SECTION 0x8000
+#define mmNIC2_QM0_BASE 0x7FFCD60000ull
+#define NIC2_QM0_MAX_OFFSET 0xD040
+#define NIC2_QM0_SECTION 0x2000
+#define mmNIC2_QM1_BASE 0x7FFCD62000ull
+#define NIC2_QM1_MAX_OFFSET 0xD040
+#define NIC2_QM1_SECTION 0x2000
+#define mmNIC2_QPC0_BASE 0x7FFCD64000ull
+#define NIC2_QPC0_MAX_OFFSET 0x7140
+#define NIC2_QPC0_SECTION 0x1000
+#define mmNIC2_QPC1_BASE 0x7FFCD65000ull
+#define NIC2_QPC1_MAX_OFFSET 0x7140
+#define NIC2_QPC1_SECTION 0x3000
+#define mmNIC2_RXB_BASE 0x7FFCD68000ull
+#define NIC2_RXB_MAX_OFFSET 0x6040
+#define NIC2_RXB_SECTION 0x1000
+#define mmNIC2_RXE0_BASE 0x7FFCD69000ull
+#define NIC2_RXE0_MAX_OFFSET 0x2FC0
+#define NIC2_RXE0_SECTION 0x1000
+#define mmNIC2_RXE1_BASE 0x7FFCD6A000ull
+#define NIC2_RXE1_MAX_OFFSET 0x2FC0
+#define NIC2_RXE1_SECTION 0x1000
+#define mmNIC2_RX_GW_BASE 0x7FFCD6B000ull
+#define NIC2_RX_GW_MAX_OFFSET 0x4540
+#define NIC2_RX_GW_SECTION 0x5000
+#define mmNIC2_TXS0_BASE 0x7FFCD70000ull
+#define NIC2_TXS0_MAX_OFFSET 0x19C0
+#define NIC2_TXS0_SECTION 0x1000
+#define mmNIC2_TXS1_BASE 0x7FFCD71000ull
+#define NIC2_TXS1_MAX_OFFSET 0x19C0
+#define NIC2_TXS1_SECTION 0x1000
+#define mmNIC2_TXE0_BASE 0x7FFCD72000ull
+#define NIC2_TXE0_MAX_OFFSET 0x2040
+#define NIC2_TXE0_SECTION 0x1000
+#define mmNIC2_TXE1_BASE 0x7FFCD73000ull
+#define NIC2_TXE1_MAX_OFFSET 0x2040
+#define NIC2_TXE1_SECTION 0x1000
+#define mmNIC2_TXB_BASE 0x7FFCD74000ull
+#define NIC2_TXB_MAX_OFFSET 0xD400
+#define NIC2_TXB_SECTION 0x1000
+#define mmNIC2_TMR_BASE 0x7FFCD75000ull
+#define NIC2_TMR_MAX_OFFSET 0x1600
+#define NIC2_TMR_SECTION 0x1000
+#define mmNIC2_TX_GW_BASE 0x7FFCD76000ull
+#define NIC2_TX_GW_MAX_OFFSET 0x1400
+#define NIC2_TX_GW_SECTION 0x2000
+#define mmNIC2_HBM_PLL_BASE 0x7FFCD78000ull
+#define NIC2_HBM_PLL_MAX_OFFSET 0x5200
+#define NIC2_HBM_PLL_SECTION 0x1000
+#define mmNIC2_MME_PLL_BASE 0x7FFCD79000ull
+#define NIC2_MME_PLL_MAX_OFFSET 0x5200
+#define NIC2_MME_PLL_SECTION 0x1000
+#define mmNIC2_TPC_PLL_BASE 0x7FFCD7A000ull
+#define NIC2_TPC_PLL_MAX_OFFSET 0x5200
+#define NIC2_TPC_PLL_SECTION 0x6000
+#define mmNIC3_MAC_CH0_BASE 0x7FFCD80000ull
+#define NIC3_MAC_CH0_MAX_OFFSET 0x8400
+#define NIC3_MAC_CH0_SECTION 0x1000
+#define mmNIC3_MAC_CH1_BASE 0x7FFCD81000ull
+#define NIC3_MAC_CH1_MAX_OFFSET 0x8400
+#define NIC3_MAC_CH1_SECTION 0x1000
+#define mmNIC3_MAC_CH2_BASE 0x7FFCD82000ull
+#define NIC3_MAC_CH2_MAX_OFFSET 0x8400
+#define NIC3_MAC_CH2_SECTION 0x1000
+#define mmNIC3_MAC_CH3_BASE 0x7FFCD83000ull
+#define NIC3_MAC_CH3_MAX_OFFSET 0x8400
+#define NIC3_MAC_CH3_SECTION 0x1000
+#define mmNIC3_STAT_BASE 0x7FFCD84000ull
+#define NIC3_STAT_MAX_OFFSET 0x4D00
+#define NIC3_STAT_SECTION 0x1000
+#define mmNIC3_MAC_XPCS91_BASE 0x7FFCD85000ull
+#define NIC3_MAC_XPCS91_MAX_OFFSET 0x2380
+#define NIC3_MAC_XPCS91_SECTION 0x3000
+#define mmNIC3_MAC_CORE_BASE 0x7FFCD88000ull
+#define NIC3_MAC_CORE_MAX_OFFSET 0x5400
+#define NIC3_MAC_CORE_SECTION 0x1000
+#define mmNIC3_MAC_AUX_BASE 0x7FFCD89000ull
+#define NIC3_MAC_AUX_MAX_OFFSET 0x3000
+#define NIC3_MAC_AUX_SECTION 0xF000
+#define mmNIC3_PHY_BASE 0x7FFCD98000ull
+#define NIC3_PHY_MAX_OFFSET 0x3400
+#define NIC3_PHY_SECTION 0x8000
+#define mmNIC3_QM0_BASE 0x7FFCDA0000ull
+#define NIC3_QM0_MAX_OFFSET 0xD040
+#define NIC3_QM0_SECTION 0x2000
+#define mmNIC3_QM1_BASE 0x7FFCDA2000ull
+#define NIC3_QM1_MAX_OFFSET 0xD040
+#define NIC3_QM1_SECTION 0x2000
+#define mmNIC3_QPC0_BASE 0x7FFCDA4000ull
+#define NIC3_QPC0_MAX_OFFSET 0x7140
+#define NIC3_QPC0_SECTION 0x1000
+#define mmNIC3_QPC1_BASE 0x7FFCDA5000ull
+#define NIC3_QPC1_MAX_OFFSET 0x7140
+#define NIC3_QPC1_SECTION 0x3000
+#define mmNIC3_RXB_BASE 0x7FFCDA8000ull
+#define NIC3_RXB_MAX_OFFSET 0x6040
+#define NIC3_RXB_SECTION 0x1000
+#define mmNIC3_RXE0_BASE 0x7FFCDA9000ull
+#define NIC3_RXE0_MAX_OFFSET 0x2FC0
+#define NIC3_RXE0_SECTION 0x1000
+#define mmNIC3_RXE1_BASE 0x7FFCDAA000ull
+#define NIC3_RXE1_MAX_OFFSET 0x2FC0
+#define NIC3_RXE1_SECTION 0x1000
+#define mmNIC3_RX_GW_BASE 0x7FFCDAB000ull
+#define NIC3_RX_GW_MAX_OFFSET 0x4540
+#define NIC3_RX_GW_SECTION 0x5000
+#define mmNIC3_TXS0_BASE 0x7FFCDB0000ull
+#define NIC3_TXS0_MAX_OFFSET 0x19C0
+#define NIC3_TXS0_SECTION 0x1000
+#define mmNIC3_TXS1_BASE 0x7FFCDB1000ull
+#define NIC3_TXS1_MAX_OFFSET 0x19C0
+#define NIC3_TXS1_SECTION 0x1000
+#define mmNIC3_TXE0_BASE 0x7FFCDB2000ull
+#define NIC3_TXE0_MAX_OFFSET 0x2040
+#define NIC3_TXE0_SECTION 0x1000
+#define mmNIC3_TXE1_BASE 0x7FFCDB3000ull
+#define NIC3_TXE1_MAX_OFFSET 0x2040
+#define NIC3_TXE1_SECTION 0x1000
+#define mmNIC3_TXB_BASE 0x7FFCDB4000ull
+#define NIC3_TXB_MAX_OFFSET 0xD400
+#define NIC3_TXB_SECTION 0x1000
+#define mmNIC3_TMR_BASE 0x7FFCDB5000ull
+#define NIC3_TMR_MAX_OFFSET 0x1600
+#define NIC3_TMR_SECTION 0x1000
+#define mmNIC3_TX_GW_BASE 0x7FFCDB6000ull
+#define NIC3_TX_GW_MAX_OFFSET 0x1400
+#define NIC3_TX_GW_SECTION 0x2000
+#define mmNIC3_TS_BASE 0x7FFCDB8000ull
+#define NIC3_TS_MAX_OFFSET 0xE640
+#define NIC3_TS_SECTION 0x2000
+#define mmNIC3_PM_BASE 0x7FFCDBA000ull
+#define NIC3_PM_MAX_OFFSET 0x1F00
+#define NIC3_PM_SECTION 0x6000
+#define mmNIC4_MAC_CH0_BASE 0x7FFCDC0000ull
+#define NIC4_MAC_CH0_MAX_OFFSET 0x8400
+#define NIC4_MAC_CH0_SECTION 0x1000
+#define mmNIC4_MAC_CH1_BASE 0x7FFCDC1000ull
+#define NIC4_MAC_CH1_MAX_OFFSET 0x8400
+#define NIC4_MAC_CH1_SECTION 0x1000
+#define mmNIC4_MAC_CH2_BASE 0x7FFCDC2000ull
+#define NIC4_MAC_CH2_MAX_OFFSET 0x8400
+#define NIC4_MAC_CH2_SECTION 0x1000
+#define mmNIC4_MAC_CH3_BASE 0x7FFCDC3000ull
+#define NIC4_MAC_CH3_MAX_OFFSET 0x8400
+#define NIC4_MAC_CH3_SECTION 0x1000
+#define mmNIC4_STAT_BASE 0x7FFCDC4000ull
+#define NIC4_STAT_MAX_OFFSET 0x4D00
+#define NIC4_STAT_SECTION 0x1000
+#define mmNIC4_MAC_XPCS91_BASE 0x7FFCDC5000ull
+#define NIC4_MAC_XPCS91_MAX_OFFSET 0x2380
+#define NIC4_MAC_XPCS91_SECTION 0x3000
+#define mmNIC4_MAC_CORE_BASE 0x7FFCDC8000ull
+#define NIC4_MAC_CORE_MAX_OFFSET 0x5400
+#define NIC4_MAC_CORE_SECTION 0x1000
+#define mmNIC4_MAC_AUX_BASE 0x7FFCDC9000ull
+#define NIC4_MAC_AUX_MAX_OFFSET 0x3000
+#define NIC4_MAC_AUX_SECTION 0xF000
+#define mmNIC4_PHY_BASE 0x7FFCDD8000ull
+#define NIC4_PHY_MAX_OFFSET 0x3400
+#define NIC4_PHY_SECTION 0x8000
+#define mmNIC4_QM0_BASE 0x7FFCDE0000ull
+#define NIC4_QM0_MAX_OFFSET 0xD040
+#define NIC4_QM0_SECTION 0x2000
+#define mmNIC4_QM1_BASE 0x7FFCDE2000ull
+#define NIC4_QM1_MAX_OFFSET 0xD040
+#define NIC4_QM1_SECTION 0x2000
+#define mmNIC4_QPC0_BASE 0x7FFCDE4000ull
+#define NIC4_QPC0_MAX_OFFSET 0x7140
+#define NIC4_QPC0_SECTION 0x1000
+#define mmNIC4_QPC1_BASE 0x7FFCDE5000ull
+#define NIC4_QPC1_MAX_OFFSET 0x7140
+#define NIC4_QPC1_SECTION 0x3000
+#define mmNIC4_RXB_BASE 0x7FFCDE8000ull
+#define NIC4_RXB_MAX_OFFSET 0x6040
+#define NIC4_RXB_SECTION 0x1000
+#define mmNIC4_RXE0_BASE 0x7FFCDE9000ull
+#define NIC4_RXE0_MAX_OFFSET 0x2FC0
+#define NIC4_RXE0_SECTION 0x1000
+#define mmNIC4_RXE1_BASE 0x7FFCDEA000ull
+#define NIC4_RXE1_MAX_OFFSET 0x2FC0
+#define NIC4_RXE1_SECTION 0x1000
+#define mmNIC4_RX_GW_BASE 0x7FFCDEB000ull
+#define NIC4_RX_GW_MAX_OFFSET 0x4540
+#define NIC4_RX_GW_SECTION 0x5000
+#define mmNIC4_TXS0_BASE 0x7FFCDF0000ull
+#define NIC4_TXS0_MAX_OFFSET 0x19C0
+#define NIC4_TXS0_SECTION 0x1000
+#define mmNIC4_TXS1_BASE 0x7FFCDF1000ull
+#define NIC4_TXS1_MAX_OFFSET 0x19C0
+#define NIC4_TXS1_SECTION 0x1000
+#define mmNIC4_TXE0_BASE 0x7FFCDF2000ull
+#define NIC4_TXE0_MAX_OFFSET 0x2040
+#define NIC4_TXE0_SECTION 0x1000
+#define mmNIC4_TXE1_BASE 0x7FFCDF3000ull
+#define NIC4_TXE1_MAX_OFFSET 0x2040
+#define NIC4_TXE1_SECTION 0x1000
+#define mmNIC4_TXB_BASE 0x7FFCDF4000ull
+#define NIC4_TXB_MAX_OFFSET 0xD400
+#define NIC4_TXB_SECTION 0x1000
+#define mmNIC4_TMR_BASE 0x7FFCDF5000ull
+#define NIC4_TMR_MAX_OFFSET 0x1600
+#define NIC4_TMR_SECTION 0x1000
+#define mmNIC4_TX_GW_BASE 0x7FFCDF6000ull
+#define NIC4_TX_GW_MAX_OFFSET 0x1400
+#define NIC4_TX_GW_SECTION 0x10000
+#define mmTPC0_CFG_BASE 0x7FFCE06000ull
+#define TPC0_CFG_MAX_OFFSET 0xE400
+#define TPC0_CFG_SECTION 0x4000
+#define mmKERNEL_TENSOR_0_TPC0_CFG_BASE 0x7FFCE06400ull
+#define KERNEL_TENSOR_0_TPC0_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_0_TPC0_CFG_SECTION 0x3800
+#define mmKERNEL_TENSOR_1_TPC0_CFG_BASE 0x7FFCE06438ull
+#define KERNEL_TENSOR_1_TPC0_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_1_TPC0_CFG_SECTION 0x3800
+#define mmKERNEL_TENSOR_2_TPC0_CFG_BASE 0x7FFCE06470ull
+#define KERNEL_TENSOR_2_TPC0_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_2_TPC0_CFG_SECTION 0x3800
+#define mmKERNEL_TENSOR_3_TPC0_CFG_BASE 0x7FFCE064A8ull
+#define KERNEL_TENSOR_3_TPC0_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_3_TPC0_CFG_SECTION 0x3800
+#define mmKERNEL_TENSOR_4_TPC0_CFG_BASE 0x7FFCE064E0ull
+#define KERNEL_TENSOR_4_TPC0_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_4_TPC0_CFG_SECTION 0x3800
+#define mmKERNEL_TENSOR_5_TPC0_CFG_BASE 0x7FFCE06518ull
+#define KERNEL_TENSOR_5_TPC0_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_5_TPC0_CFG_SECTION 0x3800
+#define mmKERNEL_TENSOR_6_TPC0_CFG_BASE 0x7FFCE06550ull
+#define KERNEL_TENSOR_6_TPC0_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_6_TPC0_CFG_SECTION 0x3800
+#define mmKERNEL_TENSOR_7_TPC0_CFG_BASE 0x7FFCE06588ull
+#define KERNEL_TENSOR_7_TPC0_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_7_TPC0_CFG_SECTION 0x3800
+#define mmKERNEL_TENSOR_8_TPC0_CFG_BASE 0x7FFCE065C0ull
+#define KERNEL_TENSOR_8_TPC0_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_8_TPC0_CFG_SECTION 0x3800
+#define mmKERNEL_TENSOR_9_TPC0_CFG_BASE 0x7FFCE065F8ull
+#define KERNEL_TENSOR_9_TPC0_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_9_TPC0_CFG_SECTION 0x3800
+#define mmKERNEL_TENSOR_10_TPC0_CFG_BASE 0x7FFCE06630ull
+#define KERNEL_TENSOR_10_TPC0_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_10_TPC0_CFG_SECTION 0x3800
+#define mmKERNEL_TENSOR_11_TPC0_CFG_BASE 0x7FFCE06668ull
+#define KERNEL_TENSOR_11_TPC0_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_11_TPC0_CFG_SECTION 0x3800
+#define mmKERNEL_TENSOR_12_TPC0_CFG_BASE 0x7FFCE066A0ull
+#define KERNEL_TENSOR_12_TPC0_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_12_TPC0_CFG_SECTION 0x3800
+#define mmKERNEL_TENSOR_13_TPC0_CFG_BASE 0x7FFCE066D8ull
+#define KERNEL_TENSOR_13_TPC0_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_13_TPC0_CFG_SECTION 0x3800
+#define mmKERNEL_TENSOR_14_TPC0_CFG_BASE 0x7FFCE06710ull
+#define KERNEL_TENSOR_14_TPC0_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_14_TPC0_CFG_SECTION 0x3800
+#define mmKERNEL_TENSOR_15_TPC0_CFG_BASE 0x7FFCE06748ull
+#define KERNEL_TENSOR_15_TPC0_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_15_TPC0_CFG_SECTION 0x3800
+#define mmKERNEL_SYNC_OBJECT_TPC0_CFG_BASE 0x7FFCE06780ull
+#define KERNEL_SYNC_OBJECT_TPC0_CFG_MAX_OFFSET 0x8000
+#define KERNEL_SYNC_OBJECT_TPC0_CFG_SECTION 0x8000
+#define mmKERNEL_TPC0_CFG_BASE 0x7FFCE06788ull
+#define KERNEL_TPC0_CFG_MAX_OFFSET 0xB800
+#define KERNEL_TPC0_CFG_SECTION 0x2780
+#define mmQM_TENSOR_0_TPC0_CFG_BASE 0x7FFCE06A00ull
+#define QM_TENSOR_0_TPC0_CFG_MAX_OFFSET 0x3800
+#define QM_TENSOR_0_TPC0_CFG_SECTION 0x3800
+#define mmQM_TENSOR_1_TPC0_CFG_BASE 0x7FFCE06A38ull
+#define QM_TENSOR_1_TPC0_CFG_MAX_OFFSET 0x3800
+#define QM_TENSOR_1_TPC0_CFG_SECTION 0x3800
+#define mmQM_TENSOR_2_TPC0_CFG_BASE 0x7FFCE06A70ull
+#define QM_TENSOR_2_TPC0_CFG_MAX_OFFSET 0x3800
+#define QM_TENSOR_2_TPC0_CFG_SECTION 0x3800
+#define mmQM_TENSOR_3_TPC0_CFG_BASE 0x7FFCE06AA8ull
+#define QM_TENSOR_3_TPC0_CFG_MAX_OFFSET 0x3800
+#define QM_TENSOR_3_TPC0_CFG_SECTION 0x3800
+#define mmQM_TENSOR_4_TPC0_CFG_BASE 0x7FFCE06AE0ull
+#define QM_TENSOR_4_TPC0_CFG_MAX_OFFSET 0x3800
+#define QM_TENSOR_4_TPC0_CFG_SECTION 0x3800
+#define mmQM_TENSOR_5_TPC0_CFG_BASE 0x7FFCE06B18ull
+#define QM_TENSOR_5_TPC0_CFG_MAX_OFFSET 0x3800
+#define QM_TENSOR_5_TPC0_CFG_SECTION 0x3800
+#define mmQM_TENSOR_6_TPC0_CFG_BASE 0x7FFCE06B50ull
+#define QM_TENSOR_6_TPC0_CFG_MAX_OFFSET 0x3800
+#define QM_TENSOR_6_TPC0_CFG_SECTION 0x3800
+#define mmQM_TENSOR_7_TPC0_CFG_BASE 0x7FFCE06B88ull
+#define QM_TENSOR_7_TPC0_CFG_MAX_OFFSET 0x3800
+#define QM_TENSOR_7_TPC0_CFG_SECTION 0x3800
+#define mmQM_TENSOR_8_TPC0_CFG_BASE 0x7FFCE06BC0ull
+#define QM_TENSOR_8_TPC0_CFG_MAX_OFFSET 0x3800
+#define QM_TENSOR_8_TPC0_CFG_SECTION 0x3800
+#define mmQM_TENSOR_9_TPC0_CFG_BASE 0x7FFCE06BF8ull
+#define QM_TENSOR_9_TPC0_CFG_MAX_OFFSET 0x3800
+#define QM_TENSOR_9_TPC0_CFG_SECTION 0x3800
+#define mmQM_TENSOR_10_TPC0_CFG_BASE 0x7FFCE06C30ull
+#define QM_TENSOR_10_TPC0_CFG_MAX_OFFSET 0x3800
+#define QM_TENSOR_10_TPC0_CFG_SECTION 0x3800
+#define mmQM_TENSOR_11_TPC0_CFG_BASE 0x7FFCE06C68ull
+#define QM_TENSOR_11_TPC0_CFG_MAX_OFFSET 0x3800
+#define QM_TENSOR_11_TPC0_CFG_SECTION 0x3800
+#define mmQM_TENSOR_12_TPC0_CFG_BASE 0x7FFCE06CA0ull
+#define QM_TENSOR_12_TPC0_CFG_MAX_OFFSET 0x3800
+#define QM_TENSOR_12_TPC0_CFG_SECTION 0x3800
+#define mmQM_TENSOR_13_TPC0_CFG_BASE 0x7FFCE06CD8ull
+#define QM_TENSOR_13_TPC0_CFG_MAX_OFFSET 0x3800
+#define QM_TENSOR_13_TPC0_CFG_SECTION 0x3800
+#define mmQM_TENSOR_14_TPC0_CFG_BASE 0x7FFCE06D10ull
+#define QM_TENSOR_14_TPC0_CFG_MAX_OFFSET 0x3800
+#define QM_TENSOR_14_TPC0_CFG_SECTION 0x3800
+#define mmQM_TENSOR_15_TPC0_CFG_BASE 0x7FFCE06D48ull
+#define QM_TENSOR_15_TPC0_CFG_MAX_OFFSET 0x3800
+#define QM_TENSOR_15_TPC0_CFG_SECTION 0x3800
+#define mmQM_SYNC_OBJECT_TPC0_CFG_BASE 0x7FFCE06D80ull
+#define QM_SYNC_OBJECT_TPC0_CFG_MAX_OFFSET 0x8000
+#define QM_SYNC_OBJECT_TPC0_CFG_SECTION 0x8000
+#define mmQM_TPC0_CFG_BASE 0x7FFCE06D88ull
+#define QM_TPC0_CFG_MAX_OFFSET 0xB800
+#define QM_TPC0_CFG_SECTION 0x2780
+#define mmTPC0_E2E_CRED_BASE 0x7FFCE07000ull
+#define TPC0_E2E_CRED_MAX_OFFSET 0x1680
+#define TPC0_E2E_CRED_SECTION 0x1000
+#define mmTPC0_QM_BASE 0x7FFCE08000ull
+#define TPC0_QM_MAX_OFFSET 0xD040
+#define TPC0_QM_SECTION 0x3E000
+#define mmTPC1_CFG_BASE 0x7FFCE46000ull
+#define TPC1_CFG_MAX_OFFSET 0xE400
+#define TPC1_CFG_SECTION 0x4000
+#define mmKERNEL_TENSOR_0_TPC1_CFG_BASE 0x7FFCE46400ull
+#define KERNEL_TENSOR_0_TPC1_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_0_TPC1_CFG_SECTION 0x3800
+#define mmKERNEL_TENSOR_1_TPC1_CFG_BASE 0x7FFCE46438ull
+#define KERNEL_TENSOR_1_TPC1_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_1_TPC1_CFG_SECTION 0x3800
+#define mmKERNEL_TENSOR_2_TPC1_CFG_BASE 0x7FFCE46470ull
+#define KERNEL_TENSOR_2_TPC1_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_2_TPC1_CFG_SECTION 0x3800
+#define mmKERNEL_TENSOR_3_TPC1_CFG_BASE 0x7FFCE464A8ull
+#define KERNEL_TENSOR_3_TPC1_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_3_TPC1_CFG_SECTION 0x3800
+#define mmKERNEL_TENSOR_4_TPC1_CFG_BASE 0x7FFCE464E0ull
+#define KERNEL_TENSOR_4_TPC1_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_4_TPC1_CFG_SECTION 0x3800
+#define mmKERNEL_TENSOR_5_TPC1_CFG_BASE 0x7FFCE46518ull
+#define KERNEL_TENSOR_5_TPC1_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_5_TPC1_CFG_SECTION 0x3800
+#define mmKERNEL_TENSOR_6_TPC1_CFG_BASE 0x7FFCE46550ull
+#define KERNEL_TENSOR_6_TPC1_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_6_TPC1_CFG_SECTION 0x3800
+#define mmKERNEL_TENSOR_7_TPC1_CFG_BASE 0x7FFCE46588ull
+#define KERNEL_TENSOR_7_TPC1_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_7_TPC1_CFG_SECTION 0x3800
+#define mmKERNEL_TENSOR_8_TPC1_CFG_BASE 0x7FFCE465C0ull
+#define KERNEL_TENSOR_8_TPC1_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_8_TPC1_CFG_SECTION 0x3800
+#define mmKERNEL_TENSOR_9_TPC1_CFG_BASE 0x7FFCE465F8ull
+#define KERNEL_TENSOR_9_TPC1_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_9_TPC1_CFG_SECTION 0x3800
+#define mmKERNEL_TENSOR_10_TPC1_CFG_BASE 0x7FFCE46630ull
+#define KERNEL_TENSOR_10_TPC1_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_10_TPC1_CFG_SECTION 0x3800
+#define mmKERNEL_TENSOR_11_TPC1_CFG_BASE 0x7FFCE46668ull
+#define KERNEL_TENSOR_11_TPC1_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_11_TPC1_CFG_SECTION 0x3800
+#define mmKERNEL_TENSOR_12_TPC1_CFG_BASE 0x7FFCE466A0ull
+#define KERNEL_TENSOR_12_TPC1_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_12_TPC1_CFG_SECTION 0x3800
+#define mmKERNEL_TENSOR_13_TPC1_CFG_BASE 0x7FFCE466D8ull
+#define KERNEL_TENSOR_13_TPC1_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_13_TPC1_CFG_SECTION 0x3800
+#define mmKERNEL_TENSOR_14_TPC1_CFG_BASE 0x7FFCE46710ull
+#define KERNEL_TENSOR_14_TPC1_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_14_TPC1_CFG_SECTION 0x3800
+#define mmKERNEL_TENSOR_15_TPC1_CFG_BASE 0x7FFCE46748ull
+#define KERNEL_TENSOR_15_TPC1_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_15_TPC1_CFG_SECTION 0x3800
+#define mmKERNEL_SYNC_OBJECT_TPC1_CFG_BASE 0x7FFCE46780ull
+#define KERNEL_SYNC_OBJECT_TPC1_CFG_MAX_OFFSET 0x8000
+#define KERNEL_SYNC_OBJECT_TPC1_CFG_SECTION 0x8000
+#define mmKERNEL_TPC1_CFG_BASE 0x7FFCE46788ull
+#define KERNEL_TPC1_CFG_MAX_OFFSET 0xB800
+#define KERNEL_TPC1_CFG_SECTION 0x2780
+#define mmQM_TENSOR_0_TPC1_CFG_BASE 0x7FFCE46A00ull
+#define QM_TENSOR_0_TPC1_CFG_MAX_OFFSET 0x3800
+#define QM_TENSOR_0_TPC1_CFG_SECTION 0x3800
+#define mmQM_TENSOR_1_TPC1_CFG_BASE 0x7FFCE46A38ull
+#define QM_TENSOR_1_TPC1_CFG_MAX_OFFSET 0x3800
+#define QM_TENSOR_1_TPC1_CFG_SECTION 0x3800
+#define mmQM_TENSOR_2_TPC1_CFG_BASE 0x7FFCE46A70ull
+#define QM_TENSOR_2_TPC1_CFG_MAX_OFFSET 0x3800
+#define QM_TENSOR_2_TPC1_CFG_SECTION 0x3800
+#define mmQM_TENSOR_3_TPC1_CFG_BASE 0x7FFCE46AA8ull
+#define QM_TENSOR_3_TPC1_CFG_MAX_OFFSET 0x3800
+#define QM_TENSOR_3_TPC1_CFG_SECTION 0x3800
+#define mmQM_TENSOR_4_TPC1_CFG_BASE 0x7FFCE46AE0ull
+#define QM_TENSOR_4_TPC1_CFG_MAX_OFFSET 0x3800
+#define QM_TENSOR_4_TPC1_CFG_SECTION 0x3800
+#define mmQM_TENSOR_5_TPC1_CFG_BASE 0x7FFCE46B18ull
+#define QM_TENSOR_5_TPC1_CFG_MAX_OFFSET 0x3800
+#define QM_TENSOR_5_TPC1_CFG_SECTION 0x3800
+#define mmQM_TENSOR_6_TPC1_CFG_BASE 0x7FFCE46B50ull
+#define QM_TENSOR_6_TPC1_CFG_MAX_OFFSET 0x3800
+#define QM_TENSOR_6_TPC1_CFG_SECTION 0x3800
+#define mmQM_TENSOR_7_TPC1_CFG_BASE 0x7FFCE46B88ull
+#define QM_TENSOR_7_TPC1_CFG_MAX_OFFSET 0x3800
+#define QM_TENSOR_7_TPC1_CFG_SECTION 0x3800
+#define mmQM_TENSOR_8_TPC1_CFG_BASE 0x7FFCE46BC0ull
+#define QM_TENSOR_8_TPC1_CFG_MAX_OFFSET 0x3800
+#define QM_TENSOR_8_TPC1_CFG_SECTION 0x3800
+#define mmQM_TENSOR_9_TPC1_CFG_BASE 0x7FFCE46BF8ull
+#define QM_TENSOR_9_TPC1_CFG_MAX_OFFSET 0x3800
+#define QM_TENSOR_9_TPC1_CFG_SECTION 0x3800
+#define mmQM_TENSOR_10_TPC1_CFG_BASE 0x7FFCE46C30ull
+#define QM_TENSOR_10_TPC1_CFG_MAX_OFFSET 0x3800
+#define QM_TENSOR_10_TPC1_CFG_SECTION 0x3800
+#define mmQM_TENSOR_11_TPC1_CFG_BASE 0x7FFCE46C68ull
+#define QM_TENSOR_11_TPC1_CFG_MAX_OFFSET 0x3800
+#define QM_TENSOR_11_TPC1_CFG_SECTION 0x3800
+#define mmQM_TENSOR_12_TPC1_CFG_BASE 0x7FFCE46CA0ull
+#define QM_TENSOR_12_TPC1_CFG_MAX_OFFSET 0x3800
+#define QM_TENSOR_12_TPC1_CFG_SECTION 0x3800
+#define mmQM_TENSOR_13_TPC1_CFG_BASE 0x7FFCE46CD8ull
+#define QM_TENSOR_13_TPC1_CFG_MAX_OFFSET 0x3800
+#define QM_TENSOR_13_TPC1_CFG_SECTION 0x3800
+#define mmQM_TENSOR_14_TPC1_CFG_BASE 0x7FFCE46D10ull
+#define QM_TENSOR_14_TPC1_CFG_MAX_OFFSET 0x3800
+#define QM_TENSOR_14_TPC1_CFG_SECTION 0x3800
+#define mmQM_TENSOR_15_TPC1_CFG_BASE 0x7FFCE46D48ull
+#define QM_TENSOR_15_TPC1_CFG_MAX_OFFSET 0x3800
+#define QM_TENSOR_15_TPC1_CFG_SECTION 0x3800
+#define mmQM_SYNC_OBJECT_TPC1_CFG_BASE 0x7FFCE46D80ull
+#define QM_SYNC_OBJECT_TPC1_CFG_MAX_OFFSET 0x8000
+#define QM_SYNC_OBJECT_TPC1_CFG_SECTION 0x8000
+#define mmQM_TPC1_CFG_BASE 0x7FFCE46D88ull
+#define QM_TPC1_CFG_MAX_OFFSET 0xB800
+#define QM_TPC1_CFG_SECTION 0x2780
+#define mmTPC1_E2E_CRED_BASE 0x7FFCE47000ull
+#define TPC1_E2E_CRED_MAX_OFFSET 0x1680
+#define TPC1_E2E_CRED_SECTION 0x1000
+#define mmTPC1_QM_BASE 0x7FFCE48000ull
+#define TPC1_QM_MAX_OFFSET 0xD040
+#define TPC1_QM_SECTION 0x3E000
+#define mmTPC2_CFG_BASE 0x7FFCE86000ull
+#define TPC2_CFG_MAX_OFFSET 0xE400
+#define TPC2_CFG_SECTION 0x4000
+#define mmKERNEL_TENSOR_0_TPC2_CFG_BASE 0x7FFCE86400ull
+#define KERNEL_TENSOR_0_TPC2_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_0_TPC2_CFG_SECTION 0x3800
+#define mmKERNEL_TENSOR_1_TPC2_CFG_BASE 0x7FFCE86438ull
+#define KERNEL_TENSOR_1_TPC2_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_1_TPC2_CFG_SECTION 0x3800
+#define mmKERNEL_TENSOR_2_TPC2_CFG_BASE 0x7FFCE86470ull
+#define KERNEL_TENSOR_2_TPC2_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_2_TPC2_CFG_SECTION 0x3800
+#define mmKERNEL_TENSOR_3_TPC2_CFG_BASE 0x7FFCE864A8ull
+#define KERNEL_TENSOR_3_TPC2_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_3_TPC2_CFG_SECTION 0x3800
+#define mmKERNEL_TENSOR_4_TPC2_CFG_BASE 0x7FFCE864E0ull
+#define KERNEL_TENSOR_4_TPC2_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_4_TPC2_CFG_SECTION 0x3800
+#define mmKERNEL_TENSOR_5_TPC2_CFG_BASE 0x7FFCE86518ull
+#define KERNEL_TENSOR_5_TPC2_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_5_TPC2_CFG_SECTION 0x3800
+#define mmKERNEL_TENSOR_6_TPC2_CFG_BASE 0x7FFCE86550ull
+#define KERNEL_TENSOR_6_TPC2_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_6_TPC2_CFG_SECTION 0x3800
+#define mmKERNEL_TENSOR_7_TPC2_CFG_BASE 0x7FFCE86588ull
+#define KERNEL_TENSOR_7_TPC2_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_7_TPC2_CFG_SECTION 0x3800
+#define mmKERNEL_TENSOR_8_TPC2_CFG_BASE 0x7FFCE865C0ull
+#define KERNEL_TENSOR_8_TPC2_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_8_TPC2_CFG_SECTION 0x3800
+#define mmKERNEL_TENSOR_9_TPC2_CFG_BASE 0x7FFCE865F8ull
+#define KERNEL_TENSOR_9_TPC2_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_9_TPC2_CFG_SECTION 0x3800
+#define mmKERNEL_TENSOR_10_TPC2_CFG_BASE 0x7FFCE86630ull
+#define KERNEL_TENSOR_10_TPC2_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_10_TPC2_CFG_SECTION 0x3800
+#define mmKERNEL_TENSOR_11_TPC2_CFG_BASE 0x7FFCE86668ull
+#define KERNEL_TENSOR_11_TPC2_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_11_TPC2_CFG_SECTION 0x3800
+#define mmKERNEL_TENSOR_12_TPC2_CFG_BASE 0x7FFCE866A0ull
+#define KERNEL_TENSOR_12_TPC2_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_12_TPC2_CFG_SECTION 0x3800
+#define mmKERNEL_TENSOR_13_TPC2_CFG_BASE 0x7FFCE866D8ull
+#define KERNEL_TENSOR_13_TPC2_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_13_TPC2_CFG_SECTION 0x3800
+#define mmKERNEL_TENSOR_14_TPC2_CFG_BASE 0x7FFCE86710ull
+#define KERNEL_TENSOR_14_TPC2_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_14_TPC2_CFG_SECTION 0x3800
+#define mmKERNEL_TENSOR_15_TPC2_CFG_BASE 0x7FFCE86748ull
+#define KERNEL_TENSOR_15_TPC2_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_15_TPC2_CFG_SECTION 0x3800
+#define mmKERNEL_SYNC_OBJECT_TPC2_CFG_BASE 0x7FFCE86780ull
+#define KERNEL_SYNC_OBJECT_TPC2_CFG_MAX_OFFSET 0x8000
+#define KERNEL_SYNC_OBJECT_TPC2_CFG_SECTION 0x8000
+#define mmKERNEL_TPC2_CFG_BASE 0x7FFCE86788ull
+#define KERNEL_TPC2_CFG_MAX_OFFSET 0xB800
+#define KERNEL_TPC2_CFG_SECTION 0x2780
+#define mmQM_TENSOR_0_TPC2_CFG_BASE 0x7FFCE86A00ull
+#define QM_TENSOR_0_TPC2_CFG_MAX_OFFSET 0x3800
+#define QM_TENSOR_0_TPC2_CFG_SECTION 0x3800
+#define mmQM_TENSOR_1_TPC2_CFG_BASE 0x7FFCE86A38ull
+#define QM_TENSOR_1_TPC2_CFG_MAX_OFFSET 0x3800
+#define QM_TENSOR_1_TPC2_CFG_SECTION 0x3800
+#define mmQM_TENSOR_2_TPC2_CFG_BASE 0x7FFCE86A70ull
+#define QM_TENSOR_2_TPC2_CFG_MAX_OFFSET 0x3800
+#define QM_TENSOR_2_TPC2_CFG_SECTION 0x3800
+#define mmQM_TENSOR_3_TPC2_CFG_BASE 0x7FFCE86AA8ull
+#define QM_TENSOR_3_TPC2_CFG_MAX_OFFSET 0x3800
+#define QM_TENSOR_3_TPC2_CFG_SECTION 0x3800
+#define mmQM_TENSOR_4_TPC2_CFG_BASE 0x7FFCE86AE0ull
+#define QM_TENSOR_4_TPC2_CFG_MAX_OFFSET 0x3800
+#define QM_TENSOR_4_TPC2_CFG_SECTION 0x3800
+#define mmQM_TENSOR_5_TPC2_CFG_BASE 0x7FFCE86B18ull
+#define QM_TENSOR_5_TPC2_CFG_MAX_OFFSET 0x3800
+#define QM_TENSOR_5_TPC2_CFG_SECTION 0x3800
+#define mmQM_TENSOR_6_TPC2_CFG_BASE 0x7FFCE86B50ull
+#define QM_TENSOR_6_TPC2_CFG_MAX_OFFSET 0x3800
+#define QM_TENSOR_6_TPC2_CFG_SECTION 0x3800
+#define mmQM_TENSOR_7_TPC2_CFG_BASE 0x7FFCE86B88ull
+#define QM_TENSOR_7_TPC2_CFG_MAX_OFFSET 0x3800
+#define QM_TENSOR_7_TPC2_CFG_SECTION 0x3800
+#define mmQM_TENSOR_8_TPC2_CFG_BASE 0x7FFCE86BC0ull
+#define QM_TENSOR_8_TPC2_CFG_MAX_OFFSET 0x3800
+#define QM_TENSOR_8_TPC2_CFG_SECTION 0x3800
+#define mmQM_TENSOR_9_TPC2_CFG_BASE 0x7FFCE86BF8ull
+#define QM_TENSOR_9_TPC2_CFG_MAX_OFFSET 0x3800
+#define QM_TENSOR_9_TPC2_CFG_SECTION 0x3800
+#define mmQM_TENSOR_10_TPC2_CFG_BASE 0x7FFCE86C30ull
+#define QM_TENSOR_10_TPC2_CFG_MAX_OFFSET 0x3800
+#define QM_TENSOR_10_TPC2_CFG_SECTION 0x3800
+#define mmQM_TENSOR_11_TPC2_CFG_BASE 0x7FFCE86C68ull
+#define QM_TENSOR_11_TPC2_CFG_MAX_OFFSET 0x3800
+#define QM_TENSOR_11_TPC2_CFG_SECTION 0x3800
+#define mmQM_TENSOR_12_TPC2_CFG_BASE 0x7FFCE86CA0ull
+#define QM_TENSOR_12_TPC2_CFG_MAX_OFFSET 0x3800
+#define QM_TENSOR_12_TPC2_CFG_SECTION 0x3800
+#define mmQM_TENSOR_13_TPC2_CFG_BASE 0x7FFCE86CD8ull
+#define QM_TENSOR_13_TPC2_CFG_MAX_OFFSET 0x3800
+#define QM_TENSOR_13_TPC2_CFG_SECTION 0x3800
+#define mmQM_TENSOR_14_TPC2_CFG_BASE 0x7FFCE86D10ull
+#define QM_TENSOR_14_TPC2_CFG_MAX_OFFSET 0x3800
+#define QM_TENSOR_14_TPC2_CFG_SECTION 0x3800
+#define mmQM_TENSOR_15_TPC2_CFG_BASE 0x7FFCE86D48ull
+#define QM_TENSOR_15_TPC2_CFG_MAX_OFFSET 0x3800
+#define QM_TENSOR_15_TPC2_CFG_SECTION 0x3800
+#define mmQM_SYNC_OBJECT_TPC2_CFG_BASE 0x7FFCE86D80ull
+#define QM_SYNC_OBJECT_TPC2_CFG_MAX_OFFSET 0x8000
+#define QM_SYNC_OBJECT_TPC2_CFG_SECTION 0x8000
+#define mmQM_TPC2_CFG_BASE 0x7FFCE86D88ull
+#define QM_TPC2_CFG_MAX_OFFSET 0xB800
+#define QM_TPC2_CFG_SECTION 0x2780
+#define mmTPC2_E2E_CRED_BASE 0x7FFCE87000ull
+#define TPC2_E2E_CRED_MAX_OFFSET 0x1680
+#define TPC2_E2E_CRED_SECTION 0x1000
+#define mmTPC2_QM_BASE 0x7FFCE88000ull
+#define TPC2_QM_MAX_OFFSET 0xD040
+#define TPC2_QM_SECTION 0x3E000
+#define mmTPC3_CFG_BASE 0x7FFCEC6000ull
+#define TPC3_CFG_MAX_OFFSET 0xE400
+#define TPC3_CFG_SECTION 0x4000
+#define mmKERNEL_TENSOR_0_TPC3_CFG_BASE 0x7FFCEC6400ull
+#define KERNEL_TENSOR_0_TPC3_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_0_TPC3_CFG_SECTION 0x3800
+#define mmKERNEL_TENSOR_1_TPC3_CFG_BASE 0x7FFCEC6438ull
+#define KERNEL_TENSOR_1_TPC3_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_1_TPC3_CFG_SECTION 0x3800
+#define mmKERNEL_TENSOR_2_TPC3_CFG_BASE 0x7FFCEC6470ull
+#define KERNEL_TENSOR_2_TPC3_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_2_TPC3_CFG_SECTION 0x3800
+#define mmKERNEL_TENSOR_3_TPC3_CFG_BASE 0x7FFCEC64A8ull
+#define KERNEL_TENSOR_3_TPC3_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_3_TPC3_CFG_SECTION 0x3800
+#define mmKERNEL_TENSOR_4_TPC3_CFG_BASE 0x7FFCEC64E0ull
+#define KERNEL_TENSOR_4_TPC3_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_4_TPC3_CFG_SECTION 0x3800
+#define mmKERNEL_TENSOR_5_TPC3_CFG_BASE 0x7FFCEC6518ull
+#define KERNEL_TENSOR_5_TPC3_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_5_TPC3_CFG_SECTION 0x3800
+#define mmKERNEL_TENSOR_6_TPC3_CFG_BASE 0x7FFCEC6550ull
+#define KERNEL_TENSOR_6_TPC3_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_6_TPC3_CFG_SECTION 0x3800
+#define mmKERNEL_TENSOR_7_TPC3_CFG_BASE 0x7FFCEC6588ull
+#define KERNEL_TENSOR_7_TPC3_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_7_TPC3_CFG_SECTION 0x3800
+#define mmKERNEL_TENSOR_8_TPC3_CFG_BASE 0x7FFCEC65C0ull
+#define KERNEL_TENSOR_8_TPC3_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_8_TPC3_CFG_SECTION 0x3800
+#define mmKERNEL_TENSOR_9_TPC3_CFG_BASE 0x7FFCEC65F8ull
+#define KERNEL_TENSOR_9_TPC3_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_9_TPC3_CFG_SECTION 0x3800
+#define mmKERNEL_TENSOR_10_TPC3_CFG_BASE 0x7FFCEC6630ull
+#define KERNEL_TENSOR_10_TPC3_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_10_TPC3_CFG_SECTION 0x3800
+#define mmKERNEL_TENSOR_11_TPC3_CFG_BASE 0x7FFCEC6668ull
+#define KERNEL_TENSOR_11_TPC3_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_11_TPC3_CFG_SECTION 0x3800
+#define mmKERNEL_TENSOR_12_TPC3_CFG_BASE 0x7FFCEC66A0ull
+#define KERNEL_TENSOR_12_TPC3_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_12_TPC3_CFG_SECTION 0x3800
+#define mmKERNEL_TENSOR_13_TPC3_CFG_BASE 0x7FFCEC66D8ull
+#define KERNEL_TENSOR_13_TPC3_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_13_TPC3_CFG_SECTION 0x3800
+#define mmKERNEL_TENSOR_14_TPC3_CFG_BASE 0x7FFCEC6710ull
+#define KERNEL_TENSOR_14_TPC3_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_14_TPC3_CFG_SECTION 0x3800
+#define mmKERNEL_TENSOR_15_TPC3_CFG_BASE 0x7FFCEC6748ull
+#define KERNEL_TENSOR_15_TPC3_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_15_TPC3_CFG_SECTION 0x3800
+#define mmKERNEL_SYNC_OBJECT_TPC3_CFG_BASE 0x7FFCEC6780ull
+#define KERNEL_SYNC_OBJECT_TPC3_CFG_MAX_OFFSET 0x8000
+#define KERNEL_SYNC_OBJECT_TPC3_CFG_SECTION 0x8000
+#define mmKERNEL_TPC3_CFG_BASE 0x7FFCEC6788ull
+#define KERNEL_TPC3_CFG_MAX_OFFSET 0xB800
+#define KERNEL_TPC3_CFG_SECTION 0x2780
+#define mmQM_TENSOR_0_TPC3_CFG_BASE 0x7FFCEC6A00ull
+#define QM_TENSOR_0_TPC3_CFG_MAX_OFFSET 0x3800
+#define QM_TENSOR_0_TPC3_CFG_SECTION 0x3800
+#define mmQM_TENSOR_1_TPC3_CFG_BASE 0x7FFCEC6A38ull
+#define QM_TENSOR_1_TPC3_CFG_MAX_OFFSET 0x3800
+#define QM_TENSOR_1_TPC3_CFG_SECTION 0x3800
+#define mmQM_TENSOR_2_TPC3_CFG_BASE 0x7FFCEC6A70ull
+#define QM_TENSOR_2_TPC3_CFG_MAX_OFFSET 0x3800
+#define QM_TENSOR_2_TPC3_CFG_SECTION 0x3800
+#define mmQM_TENSOR_3_TPC3_CFG_BASE 0x7FFCEC6AA8ull
+#define QM_TENSOR_3_TPC3_CFG_MAX_OFFSET 0x3800
+#define QM_TENSOR_3_TPC3_CFG_SECTION 0x3800
+#define mmQM_TENSOR_4_TPC3_CFG_BASE 0x7FFCEC6AE0ull
+#define QM_TENSOR_4_TPC3_CFG_MAX_OFFSET 0x3800
+#define QM_TENSOR_4_TPC3_CFG_SECTION 0x3800
+#define mmQM_TENSOR_5_TPC3_CFG_BASE 0x7FFCEC6B18ull
+#define QM_TENSOR_5_TPC3_CFG_MAX_OFFSET 0x3800
+#define QM_TENSOR_5_TPC3_CFG_SECTION 0x3800
+#define mmQM_TENSOR_6_TPC3_CFG_BASE 0x7FFCEC6B50ull
+#define QM_TENSOR_6_TPC3_CFG_MAX_OFFSET 0x3800
+#define QM_TENSOR_6_TPC3_CFG_SECTION 0x3800
+#define mmQM_TENSOR_7_TPC3_CFG_BASE 0x7FFCEC6B88ull
+#define QM_TENSOR_7_TPC3_CFG_MAX_OFFSET 0x3800
+#define QM_TENSOR_7_TPC3_CFG_SECTION 0x3800
+#define mmQM_TENSOR_8_TPC3_CFG_BASE 0x7FFCEC6BC0ull
+#define QM_TENSOR_8_TPC3_CFG_MAX_OFFSET 0x3800
+#define QM_TENSOR_8_TPC3_CFG_SECTION 0x3800
+#define mmQM_TENSOR_9_TPC3_CFG_BASE 0x7FFCEC6BF8ull
+#define QM_TENSOR_9_TPC3_CFG_MAX_OFFSET 0x3800
+#define QM_TENSOR_9_TPC3_CFG_SECTION 0x3800
+#define mmQM_TENSOR_10_TPC3_CFG_BASE 0x7FFCEC6C30ull
+#define QM_TENSOR_10_TPC3_CFG_MAX_OFFSET 0x3800
+#define QM_TENSOR_10_TPC3_CFG_SECTION 0x3800
+#define mmQM_TENSOR_11_TPC3_CFG_BASE 0x7FFCEC6C68ull
+#define QM_TENSOR_11_TPC3_CFG_MAX_OFFSET 0x3800
+#define QM_TENSOR_11_TPC3_CFG_SECTION 0x3800
+#define mmQM_TENSOR_12_TPC3_CFG_BASE 0x7FFCEC6CA0ull
+#define QM_TENSOR_12_TPC3_CFG_MAX_OFFSET 0x3800
+#define QM_TENSOR_12_TPC3_CFG_SECTION 0x3800
+#define mmQM_TENSOR_13_TPC3_CFG_BASE 0x7FFCEC6CD8ull
+#define QM_TENSOR_13_TPC3_CFG_MAX_OFFSET 0x3800
+#define QM_TENSOR_13_TPC3_CFG_SECTION 0x3800
+#define mmQM_TENSOR_14_TPC3_CFG_BASE 0x7FFCEC6D10ull
+#define QM_TENSOR_14_TPC3_CFG_MAX_OFFSET 0x3800
+#define QM_TENSOR_14_TPC3_CFG_SECTION 0x3800
+#define mmQM_TENSOR_15_TPC3_CFG_BASE 0x7FFCEC6D48ull
+#define QM_TENSOR_15_TPC3_CFG_MAX_OFFSET 0x3800
+#define QM_TENSOR_15_TPC3_CFG_SECTION 0x3800
+#define mmQM_SYNC_OBJECT_TPC3_CFG_BASE 0x7FFCEC6D80ull
+#define QM_SYNC_OBJECT_TPC3_CFG_MAX_OFFSET 0x8000
+#define QM_SYNC_OBJECT_TPC3_CFG_SECTION 0x8000
+#define mmQM_TPC3_CFG_BASE 0x7FFCEC6D88ull
+#define QM_TPC3_CFG_MAX_OFFSET 0xB800
+#define QM_TPC3_CFG_SECTION 0x2780
+#define mmTPC3_E2E_CRED_BASE 0x7FFCEC7000ull
+#define TPC3_E2E_CRED_MAX_OFFSET 0x1680
+#define TPC3_E2E_CRED_SECTION 0x1000
+#define mmTPC3_QM_BASE 0x7FFCEC8000ull
+#define TPC3_QM_MAX_OFFSET 0xD040
+#define TPC3_QM_SECTION 0x3E000
+#define mmTPC4_CFG_BASE 0x7FFCF06000ull
+#define TPC4_CFG_MAX_OFFSET 0xE400
+#define TPC4_CFG_SECTION 0x4000
+#define mmKERNEL_TENSOR_0_TPC4_CFG_BASE 0x7FFCF06400ull
+#define KERNEL_TENSOR_0_TPC4_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_0_TPC4_CFG_SECTION 0x3800
+#define mmKERNEL_TENSOR_1_TPC4_CFG_BASE 0x7FFCF06438ull
+#define KERNEL_TENSOR_1_TPC4_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_1_TPC4_CFG_SECTION 0x3800
+#define mmKERNEL_TENSOR_2_TPC4_CFG_BASE 0x7FFCF06470ull
+#define KERNEL_TENSOR_2_TPC4_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_2_TPC4_CFG_SECTION 0x3800
+#define mmKERNEL_TENSOR_3_TPC4_CFG_BASE 0x7FFCF064A8ull
+#define KERNEL_TENSOR_3_TPC4_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_3_TPC4_CFG_SECTION 0x3800
+#define mmKERNEL_TENSOR_4_TPC4_CFG_BASE 0x7FFCF064E0ull
+#define KERNEL_TENSOR_4_TPC4_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_4_TPC4_CFG_SECTION 0x3800
+#define mmKERNEL_TENSOR_5_TPC4_CFG_BASE 0x7FFCF06518ull
+#define KERNEL_TENSOR_5_TPC4_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_5_TPC4_CFG_SECTION 0x3800
+#define mmKERNEL_TENSOR_6_TPC4_CFG_BASE 0x7FFCF06550ull
+#define KERNEL_TENSOR_6_TPC4_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_6_TPC4_CFG_SECTION 0x3800
+#define mmKERNEL_TENSOR_7_TPC4_CFG_BASE 0x7FFCF06588ull
+#define KERNEL_TENSOR_7_TPC4_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_7_TPC4_CFG_SECTION 0x3800
+#define mmKERNEL_TENSOR_8_TPC4_CFG_BASE 0x7FFCF065C0ull
+#define KERNEL_TENSOR_8_TPC4_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_8_TPC4_CFG_SECTION 0x3800
+#define mmKERNEL_TENSOR_9_TPC4_CFG_BASE 0x7FFCF065F8ull
+#define KERNEL_TENSOR_9_TPC4_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_9_TPC4_CFG_SECTION 0x3800
+#define mmKERNEL_TENSOR_10_TPC4_CFG_BASE 0x7FFCF06630ull
+#define KERNEL_TENSOR_10_TPC4_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_10_TPC4_CFG_SECTION 0x3800
+#define mmKERNEL_TENSOR_11_TPC4_CFG_BASE 0x7FFCF06668ull
+#define KERNEL_TENSOR_11_TPC4_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_11_TPC4_CFG_SECTION 0x3800
+#define mmKERNEL_TENSOR_12_TPC4_CFG_BASE 0x7FFCF066A0ull
+#define KERNEL_TENSOR_12_TPC4_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_12_TPC4_CFG_SECTION 0x3800
+#define mmKERNEL_TENSOR_13_TPC4_CFG_BASE 0x7FFCF066D8ull
+#define KERNEL_TENSOR_13_TPC4_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_13_TPC4_CFG_SECTION 0x3800
+#define mmKERNEL_TENSOR_14_TPC4_CFG_BASE 0x7FFCF06710ull
+#define KERNEL_TENSOR_14_TPC4_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_14_TPC4_CFG_SECTION 0x3800
+#define mmKERNEL_TENSOR_15_TPC4_CFG_BASE 0x7FFCF06748ull
+#define KERNEL_TENSOR_15_TPC4_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_15_TPC4_CFG_SECTION 0x3800
+#define mmKERNEL_SYNC_OBJECT_TPC4_CFG_BASE 0x7FFCF06780ull
+#define KERNEL_SYNC_OBJECT_TPC4_CFG_MAX_OFFSET 0x8000
+#define KERNEL_SYNC_OBJECT_TPC4_CFG_SECTION 0x8000
+#define mmKERNEL_TPC4_CFG_BASE 0x7FFCF06788ull
+#define KERNEL_TPC4_CFG_MAX_OFFSET 0xB800
+#define KERNEL_TPC4_CFG_SECTION 0x2780
+#define mmQM_TENSOR_0_TPC4_CFG_BASE 0x7FFCF06A00ull
+#define QM_TENSOR_0_TPC4_CFG_MAX_OFFSET 0x3800
+#define QM_TENSOR_0_TPC4_CFG_SECTION 0x3800
+#define mmQM_TENSOR_1_TPC4_CFG_BASE 0x7FFCF06A38ull
+#define QM_TENSOR_1_TPC4_CFG_MAX_OFFSET 0x3800
+#define QM_TENSOR_1_TPC4_CFG_SECTION 0x3800
+#define mmQM_TENSOR_2_TPC4_CFG_BASE 0x7FFCF06A70ull
+#define QM_TENSOR_2_TPC4_CFG_MAX_OFFSET 0x3800
+#define QM_TENSOR_2_TPC4_CFG_SECTION 0x3800
+#define mmQM_TENSOR_3_TPC4_CFG_BASE 0x7FFCF06AA8ull
+#define QM_TENSOR_3_TPC4_CFG_MAX_OFFSET 0x3800
+#define QM_TENSOR_3_TPC4_CFG_SECTION 0x3800
+#define mmQM_TENSOR_4_TPC4_CFG_BASE 0x7FFCF06AE0ull
+#define QM_TENSOR_4_TPC4_CFG_MAX_OFFSET 0x3800
+#define QM_TENSOR_4_TPC4_CFG_SECTION 0x3800
+#define mmQM_TENSOR_5_TPC4_CFG_BASE 0x7FFCF06B18ull
+#define QM_TENSOR_5_TPC4_CFG_MAX_OFFSET 0x3800
+#define QM_TENSOR_5_TPC4_CFG_SECTION 0x3800
+#define mmQM_TENSOR_6_TPC4_CFG_BASE 0x7FFCF06B50ull
+#define QM_TENSOR_6_TPC4_CFG_MAX_OFFSET 0x3800
+#define QM_TENSOR_6_TPC4_CFG_SECTION 0x3800
+#define mmQM_TENSOR_7_TPC4_CFG_BASE 0x7FFCF06B88ull
+#define QM_TENSOR_7_TPC4_CFG_MAX_OFFSET 0x3800
+#define QM_TENSOR_7_TPC4_CFG_SECTION 0x3800
+#define mmQM_TENSOR_8_TPC4_CFG_BASE 0x7FFCF06BC0ull
+#define QM_TENSOR_8_TPC4_CFG_MAX_OFFSET 0x3800
+#define QM_TENSOR_8_TPC4_CFG_SECTION 0x3800
+#define mmQM_TENSOR_9_TPC4_CFG_BASE 0x7FFCF06BF8ull
+#define QM_TENSOR_9_TPC4_CFG_MAX_OFFSET 0x3800
+#define QM_TENSOR_9_TPC4_CFG_SECTION 0x3800
+#define mmQM_TENSOR_10_TPC4_CFG_BASE 0x7FFCF06C30ull
+#define QM_TENSOR_10_TPC4_CFG_MAX_OFFSET 0x3800
+#define QM_TENSOR_10_TPC4_CFG_SECTION 0x3800
+#define mmQM_TENSOR_11_TPC4_CFG_BASE 0x7FFCF06C68ull
+#define QM_TENSOR_11_TPC4_CFG_MAX_OFFSET 0x3800
+#define QM_TENSOR_11_TPC4_CFG_SECTION 0x3800
+#define mmQM_TENSOR_12_TPC4_CFG_BASE 0x7FFCF06CA0ull
+#define QM_TENSOR_12_TPC4_CFG_MAX_OFFSET 0x3800
+#define QM_TENSOR_12_TPC4_CFG_SECTION 0x3800
+#define mmQM_TENSOR_13_TPC4_CFG_BASE 0x7FFCF06CD8ull
+#define QM_TENSOR_13_TPC4_CFG_MAX_OFFSET 0x3800
+#define QM_TENSOR_13_TPC4_CFG_SECTION 0x3800
+#define mmQM_TENSOR_14_TPC4_CFG_BASE 0x7FFCF06D10ull
+#define QM_TENSOR_14_TPC4_CFG_MAX_OFFSET 0x3800
+#define QM_TENSOR_14_TPC4_CFG_SECTION 0x3800
+#define mmQM_TENSOR_15_TPC4_CFG_BASE 0x7FFCF06D48ull
+#define QM_TENSOR_15_TPC4_CFG_MAX_OFFSET 0x3800
+#define QM_TENSOR_15_TPC4_CFG_SECTION 0x3800
+#define mmQM_SYNC_OBJECT_TPC4_CFG_BASE 0x7FFCF06D80ull
+#define QM_SYNC_OBJECT_TPC4_CFG_MAX_OFFSET 0x8000
+#define QM_SYNC_OBJECT_TPC4_CFG_SECTION 0x8000
+#define mmQM_TPC4_CFG_BASE 0x7FFCF06D88ull
+#define QM_TPC4_CFG_MAX_OFFSET 0xB800
+#define QM_TPC4_CFG_SECTION 0x2780
+#define mmTPC4_E2E_CRED_BASE 0x7FFCF07000ull
+#define TPC4_E2E_CRED_MAX_OFFSET 0x1680
+#define TPC4_E2E_CRED_SECTION 0x1000
+#define mmTPC4_QM_BASE 0x7FFCF08000ull
+#define TPC4_QM_MAX_OFFSET 0xD040
+#define TPC4_QM_SECTION 0x3E000
+#define mmTPC5_CFG_BASE 0x7FFCF46000ull
+#define TPC5_CFG_MAX_OFFSET 0xE400
+#define TPC5_CFG_SECTION 0x4000
+#define mmKERNEL_TENSOR_0_TPC5_CFG_BASE 0x7FFCF46400ull
+#define KERNEL_TENSOR_0_TPC5_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_0_TPC5_CFG_SECTION 0x3800
+#define mmKERNEL_TENSOR_1_TPC5_CFG_BASE 0x7FFCF46438ull
+#define KERNEL_TENSOR_1_TPC5_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_1_TPC5_CFG_SECTION 0x3800
+#define mmKERNEL_TENSOR_2_TPC5_CFG_BASE 0x7FFCF46470ull
+#define KERNEL_TENSOR_2_TPC5_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_2_TPC5_CFG_SECTION 0x3800
+#define mmKERNEL_TENSOR_3_TPC5_CFG_BASE 0x7FFCF464A8ull
+#define KERNEL_TENSOR_3_TPC5_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_3_TPC5_CFG_SECTION 0x3800
+#define mmKERNEL_TENSOR_4_TPC5_CFG_BASE 0x7FFCF464E0ull
+#define KERNEL_TENSOR_4_TPC5_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_4_TPC5_CFG_SECTION 0x3800
+#define mmKERNEL_TENSOR_5_TPC5_CFG_BASE 0x7FFCF46518ull
+#define KERNEL_TENSOR_5_TPC5_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_5_TPC5_CFG_SECTION 0x3800
+#define mmKERNEL_TENSOR_6_TPC5_CFG_BASE 0x7FFCF46550ull
+#define KERNEL_TENSOR_6_TPC5_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_6_TPC5_CFG_SECTION 0x3800
+#define mmKERNEL_TENSOR_7_TPC5_CFG_BASE 0x7FFCF46588ull
+#define KERNEL_TENSOR_7_TPC5_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_7_TPC5_CFG_SECTION 0x3800
+#define mmKERNEL_TENSOR_8_TPC5_CFG_BASE 0x7FFCF465C0ull
+#define KERNEL_TENSOR_8_TPC5_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_8_TPC5_CFG_SECTION 0x3800
+#define mmKERNEL_TENSOR_9_TPC5_CFG_BASE 0x7FFCF465F8ull
+#define KERNEL_TENSOR_9_TPC5_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_9_TPC5_CFG_SECTION 0x3800
+#define mmKERNEL_TENSOR_10_TPC5_CFG_BASE 0x7FFCF46630ull
+#define KERNEL_TENSOR_10_TPC5_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_10_TPC5_CFG_SECTION 0x3800
+#define mmKERNEL_TENSOR_11_TPC5_CFG_BASE 0x7FFCF46668ull
+#define KERNEL_TENSOR_11_TPC5_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_11_TPC5_CFG_SECTION 0x3800
+#define mmKERNEL_TENSOR_12_TPC5_CFG_BASE 0x7FFCF466A0ull
+#define KERNEL_TENSOR_12_TPC5_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_12_TPC5_CFG_SECTION 0x3800
+#define mmKERNEL_TENSOR_13_TPC5_CFG_BASE 0x7FFCF466D8ull
+#define KERNEL_TENSOR_13_TPC5_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_13_TPC5_CFG_SECTION 0x3800
+#define mmKERNEL_TENSOR_14_TPC5_CFG_BASE 0x7FFCF46710ull
+#define KERNEL_TENSOR_14_TPC5_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_14_TPC5_CFG_SECTION 0x3800
+#define mmKERNEL_TENSOR_15_TPC5_CFG_BASE 0x7FFCF46748ull
+#define KERNEL_TENSOR_15_TPC5_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_15_TPC5_CFG_SECTION 0x3800
+#define mmKERNEL_SYNC_OBJECT_TPC5_CFG_BASE 0x7FFCF46780ull
+#define KERNEL_SYNC_OBJECT_TPC5_CFG_MAX_OFFSET 0x8000
+#define KERNEL_SYNC_OBJECT_TPC5_CFG_SECTION 0x8000
+#define mmKERNEL_TPC5_CFG_BASE 0x7FFCF46788ull
+#define KERNEL_TPC5_CFG_MAX_OFFSET 0xB800
+#define KERNEL_TPC5_CFG_SECTION 0x2780
+#define mmQM_TENSOR_0_TPC5_CFG_BASE 0x7FFCF46A00ull
+#define QM_TENSOR_0_TPC5_CFG_MAX_OFFSET 0x3800
+#define QM_TENSOR_0_TPC5_CFG_SECTION 0x3800
+#define mmQM_TENSOR_1_TPC5_CFG_BASE 0x7FFCF46A38ull
+#define QM_TENSOR_1_TPC5_CFG_MAX_OFFSET 0x3800
+#define QM_TENSOR_1_TPC5_CFG_SECTION 0x3800
+#define mmQM_TENSOR_2_TPC5_CFG_BASE 0x7FFCF46A70ull
+#define QM_TENSOR_2_TPC5_CFG_MAX_OFFSET 0x3800
+#define QM_TENSOR_2_TPC5_CFG_SECTION 0x3800
+#define mmQM_TENSOR_3_TPC5_CFG_BASE 0x7FFCF46AA8ull
+#define QM_TENSOR_3_TPC5_CFG_MAX_OFFSET 0x3800
+#define QM_TENSOR_3_TPC5_CFG_SECTION 0x3800
+#define mmQM_TENSOR_4_TPC5_CFG_BASE 0x7FFCF46AE0ull
+#define QM_TENSOR_4_TPC5_CFG_MAX_OFFSET 0x3800
+#define QM_TENSOR_4_TPC5_CFG_SECTION 0x3800
+#define mmQM_TENSOR_5_TPC5_CFG_BASE 0x7FFCF46B18ull
+#define QM_TENSOR_5_TPC5_CFG_MAX_OFFSET 0x3800
+#define QM_TENSOR_5_TPC5_CFG_SECTION 0x3800
+#define mmQM_TENSOR_6_TPC5_CFG_BASE 0x7FFCF46B50ull
+#define QM_TENSOR_6_TPC5_CFG_MAX_OFFSET 0x3800
+#define QM_TENSOR_6_TPC5_CFG_SECTION 0x3800
+#define mmQM_TENSOR_7_TPC5_CFG_BASE 0x7FFCF46B88ull
+#define QM_TENSOR_7_TPC5_CFG_MAX_OFFSET 0x3800
+#define QM_TENSOR_7_TPC5_CFG_SECTION 0x3800
+#define mmQM_TENSOR_8_TPC5_CFG_BASE 0x7FFCF46BC0ull
+#define QM_TENSOR_8_TPC5_CFG_MAX_OFFSET 0x3800
+#define QM_TENSOR_8_TPC5_CFG_SECTION 0x3800
+#define mmQM_TENSOR_9_TPC5_CFG_BASE 0x7FFCF46BF8ull
+#define QM_TENSOR_9_TPC5_CFG_MAX_OFFSET 0x3800
+#define QM_TENSOR_9_TPC5_CFG_SECTION 0x3800
+#define mmQM_TENSOR_10_TPC5_CFG_BASE 0x7FFCF46C30ull
+#define QM_TENSOR_10_TPC5_CFG_MAX_OFFSET 0x3800
+#define QM_TENSOR_10_TPC5_CFG_SECTION 0x3800
+#define mmQM_TENSOR_11_TPC5_CFG_BASE 0x7FFCF46C68ull
+#define QM_TENSOR_11_TPC5_CFG_MAX_OFFSET 0x3800
+#define QM_TENSOR_11_TPC5_CFG_SECTION 0x3800
+#define mmQM_TENSOR_12_TPC5_CFG_BASE 0x7FFCF46CA0ull
+#define QM_TENSOR_12_TPC5_CFG_MAX_OFFSET 0x3800
+#define QM_TENSOR_12_TPC5_CFG_SECTION 0x3800
+#define mmQM_TENSOR_13_TPC5_CFG_BASE 0x7FFCF46CD8ull
+#define QM_TENSOR_13_TPC5_CFG_MAX_OFFSET 0x3800
+#define QM_TENSOR_13_TPC5_CFG_SECTION 0x3800
+#define mmQM_TENSOR_14_TPC5_CFG_BASE 0x7FFCF46D10ull
+#define QM_TENSOR_14_TPC5_CFG_MAX_OFFSET 0x3800
+#define QM_TENSOR_14_TPC5_CFG_SECTION 0x3800
+#define mmQM_TENSOR_15_TPC5_CFG_BASE 0x7FFCF46D48ull
+#define QM_TENSOR_15_TPC5_CFG_MAX_OFFSET 0x3800
+#define QM_TENSOR_15_TPC5_CFG_SECTION 0x3800
+#define mmQM_SYNC_OBJECT_TPC5_CFG_BASE 0x7FFCF46D80ull
+#define QM_SYNC_OBJECT_TPC5_CFG_MAX_OFFSET 0x8000
+#define QM_SYNC_OBJECT_TPC5_CFG_SECTION 0x8000
+#define mmQM_TPC5_CFG_BASE 0x7FFCF46D88ull
+#define QM_TPC5_CFG_MAX_OFFSET 0xB800
+#define QM_TPC5_CFG_SECTION 0x2780
+#define mmTPC5_E2E_CRED_BASE 0x7FFCF47000ull
+#define TPC5_E2E_CRED_MAX_OFFSET 0x1680
+#define TPC5_E2E_CRED_SECTION 0x1000
+#define mmTPC5_QM_BASE 0x7FFCF48000ull
+#define TPC5_QM_MAX_OFFSET 0xD040
+#define TPC5_QM_SECTION 0x3E000
+#define mmTPC6_CFG_BASE 0x7FFCF86000ull
+#define TPC6_CFG_MAX_OFFSET 0xE400
+#define TPC6_CFG_SECTION 0x4000
+#define mmKERNEL_TENSOR_0_TPC6_CFG_BASE 0x7FFCF86400ull
+#define KERNEL_TENSOR_0_TPC6_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_0_TPC6_CFG_SECTION 0x3800
+#define mmKERNEL_TENSOR_1_TPC6_CFG_BASE 0x7FFCF86438ull
+#define KERNEL_TENSOR_1_TPC6_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_1_TPC6_CFG_SECTION 0x3800
+#define mmKERNEL_TENSOR_2_TPC6_CFG_BASE 0x7FFCF86470ull
+#define KERNEL_TENSOR_2_TPC6_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_2_TPC6_CFG_SECTION 0x3800
+#define mmKERNEL_TENSOR_3_TPC6_CFG_BASE 0x7FFCF864A8ull
+#define KERNEL_TENSOR_3_TPC6_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_3_TPC6_CFG_SECTION 0x3800
+#define mmKERNEL_TENSOR_4_TPC6_CFG_BASE 0x7FFCF864E0ull
+#define KERNEL_TENSOR_4_TPC6_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_4_TPC6_CFG_SECTION 0x3800
+#define mmKERNEL_TENSOR_5_TPC6_CFG_BASE 0x7FFCF86518ull
+#define KERNEL_TENSOR_5_TPC6_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_5_TPC6_CFG_SECTION 0x3800
+#define mmKERNEL_TENSOR_6_TPC6_CFG_BASE 0x7FFCF86550ull
+#define KERNEL_TENSOR_6_TPC6_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_6_TPC6_CFG_SECTION 0x3800
+#define mmKERNEL_TENSOR_7_TPC6_CFG_BASE 0x7FFCF86588ull
+#define KERNEL_TENSOR_7_TPC6_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_7_TPC6_CFG_SECTION 0x3800
+#define mmKERNEL_TENSOR_8_TPC6_CFG_BASE 0x7FFCF865C0ull
+#define KERNEL_TENSOR_8_TPC6_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_8_TPC6_CFG_SECTION 0x3800
+#define mmKERNEL_TENSOR_9_TPC6_CFG_BASE 0x7FFCF865F8ull
+#define KERNEL_TENSOR_9_TPC6_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_9_TPC6_CFG_SECTION 0x3800
+#define mmKERNEL_TENSOR_10_TPC6_CFG_BASE 0x7FFCF86630ull
+#define KERNEL_TENSOR_10_TPC6_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_10_TPC6_CFG_SECTION 0x3800
+#define mmKERNEL_TENSOR_11_TPC6_CFG_BASE 0x7FFCF86668ull
+#define KERNEL_TENSOR_11_TPC6_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_11_TPC6_CFG_SECTION 0x3800
+#define mmKERNEL_TENSOR_12_TPC6_CFG_BASE 0x7FFCF866A0ull
+#define KERNEL_TENSOR_12_TPC6_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_12_TPC6_CFG_SECTION 0x3800
+#define mmKERNEL_TENSOR_13_TPC6_CFG_BASE 0x7FFCF866D8ull
+#define KERNEL_TENSOR_13_TPC6_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_13_TPC6_CFG_SECTION 0x3800
+#define mmKERNEL_TENSOR_14_TPC6_CFG_BASE 0x7FFCF86710ull
+#define KERNEL_TENSOR_14_TPC6_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_14_TPC6_CFG_SECTION 0x3800
+#define mmKERNEL_TENSOR_15_TPC6_CFG_BASE 0x7FFCF86748ull
+#define KERNEL_TENSOR_15_TPC6_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_15_TPC6_CFG_SECTION 0x3800
+#define mmKERNEL_SYNC_OBJECT_TPC6_CFG_BASE 0x7FFCF86780ull
+#define KERNEL_SYNC_OBJECT_TPC6_CFG_MAX_OFFSET 0x8000
+#define KERNEL_SYNC_OBJECT_TPC6_CFG_SECTION 0x8000
+#define mmKERNEL_TPC6_CFG_BASE 0x7FFCF86788ull
+#define KERNEL_TPC6_CFG_MAX_OFFSET 0xB800
+#define KERNEL_TPC6_CFG_SECTION 0x2780
+#define mmQM_TENSOR_0_TPC6_CFG_BASE 0x7FFCF86A00ull
+#define QM_TENSOR_0_TPC6_CFG_MAX_OFFSET 0x3800
+#define QM_TENSOR_0_TPC6_CFG_SECTION 0x3800
+#define mmQM_TENSOR_1_TPC6_CFG_BASE 0x7FFCF86A38ull
+#define QM_TENSOR_1_TPC6_CFG_MAX_OFFSET 0x3800
+#define QM_TENSOR_1_TPC6_CFG_SECTION 0x3800
+#define mmQM_TENSOR_2_TPC6_CFG_BASE 0x7FFCF86A70ull
+#define QM_TENSOR_2_TPC6_CFG_MAX_OFFSET 0x3800
+#define QM_TENSOR_2_TPC6_CFG_SECTION 0x3800
+#define mmQM_TENSOR_3_TPC6_CFG_BASE 0x7FFCF86AA8ull
+#define QM_TENSOR_3_TPC6_CFG_MAX_OFFSET 0x3800
+#define QM_TENSOR_3_TPC6_CFG_SECTION 0x3800
+#define mmQM_TENSOR_4_TPC6_CFG_BASE 0x7FFCF86AE0ull
+#define QM_TENSOR_4_TPC6_CFG_MAX_OFFSET 0x3800
+#define QM_TENSOR_4_TPC6_CFG_SECTION 0x3800
+#define mmQM_TENSOR_5_TPC6_CFG_BASE 0x7FFCF86B18ull
+#define QM_TENSOR_5_TPC6_CFG_MAX_OFFSET 0x3800
+#define QM_TENSOR_5_TPC6_CFG_SECTION 0x3800
+#define mmQM_TENSOR_6_TPC6_CFG_BASE 0x7FFCF86B50ull
+#define QM_TENSOR_6_TPC6_CFG_MAX_OFFSET 0x3800
+#define QM_TENSOR_6_TPC6_CFG_SECTION 0x3800
+#define mmQM_TENSOR_7_TPC6_CFG_BASE 0x7FFCF86B88ull
+#define QM_TENSOR_7_TPC6_CFG_MAX_OFFSET 0x3800
+#define QM_TENSOR_7_TPC6_CFG_SECTION 0x3800
+#define mmQM_TENSOR_8_TPC6_CFG_BASE 0x7FFCF86BC0ull
+#define QM_TENSOR_8_TPC6_CFG_MAX_OFFSET 0x3800
+#define QM_TENSOR_8_TPC6_CFG_SECTION 0x3800
+#define mmQM_TENSOR_9_TPC6_CFG_BASE 0x7FFCF86BF8ull
+#define QM_TENSOR_9_TPC6_CFG_MAX_OFFSET 0x3800
+#define QM_TENSOR_9_TPC6_CFG_SECTION 0x3800
+#define mmQM_TENSOR_10_TPC6_CFG_BASE 0x7FFCF86C30ull
+#define QM_TENSOR_10_TPC6_CFG_MAX_OFFSET 0x3800
+#define QM_TENSOR_10_TPC6_CFG_SECTION 0x3800
+#define mmQM_TENSOR_11_TPC6_CFG_BASE 0x7FFCF86C68ull
+#define QM_TENSOR_11_TPC6_CFG_MAX_OFFSET 0x3800
+#define QM_TENSOR_11_TPC6_CFG_SECTION 0x3800
+#define mmQM_TENSOR_12_TPC6_CFG_BASE 0x7FFCF86CA0ull
+#define QM_TENSOR_12_TPC6_CFG_MAX_OFFSET 0x3800
+#define QM_TENSOR_12_TPC6_CFG_SECTION 0x3800
+#define mmQM_TENSOR_13_TPC6_CFG_BASE 0x7FFCF86CD8ull
+#define QM_TENSOR_13_TPC6_CFG_MAX_OFFSET 0x3800
+#define QM_TENSOR_13_TPC6_CFG_SECTION 0x3800
+#define mmQM_TENSOR_14_TPC6_CFG_BASE 0x7FFCF86D10ull
+#define QM_TENSOR_14_TPC6_CFG_MAX_OFFSET 0x3800
+#define QM_TENSOR_14_TPC6_CFG_SECTION 0x3800
+#define mmQM_TENSOR_15_TPC6_CFG_BASE 0x7FFCF86D48ull
+#define QM_TENSOR_15_TPC6_CFG_MAX_OFFSET 0x3800
+#define QM_TENSOR_15_TPC6_CFG_SECTION 0x3800
+#define mmQM_SYNC_OBJECT_TPC6_CFG_BASE 0x7FFCF86D80ull
+#define QM_SYNC_OBJECT_TPC6_CFG_MAX_OFFSET 0x8000
+#define QM_SYNC_OBJECT_TPC6_CFG_SECTION 0x8000
+#define mmQM_TPC6_CFG_BASE 0x7FFCF86D88ull
+#define QM_TPC6_CFG_MAX_OFFSET 0xB800
+#define QM_TPC6_CFG_SECTION 0x2780
+#define mmTPC6_E2E_CRED_BASE 0x7FFCF87000ull
+#define TPC6_E2E_CRED_MAX_OFFSET 0x1680
+#define TPC6_E2E_CRED_SECTION 0x1000
+#define mmTPC6_QM_BASE 0x7FFCF88000ull
+#define TPC6_QM_MAX_OFFSET 0xD040
+#define TPC6_QM_SECTION 0x3E000
+#define mmTPC7_CFG_BASE 0x7FFCFC6000ull
+#define TPC7_CFG_MAX_OFFSET 0xE400
+#define TPC7_CFG_SECTION 0x4000
+#define mmKERNEL_TENSOR_0_TPC7_CFG_BASE 0x7FFCFC6400ull
+#define KERNEL_TENSOR_0_TPC7_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_0_TPC7_CFG_SECTION 0x3800
+#define mmKERNEL_TENSOR_1_TPC7_CFG_BASE 0x7FFCFC6438ull
+#define KERNEL_TENSOR_1_TPC7_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_1_TPC7_CFG_SECTION 0x3800
+#define mmKERNEL_TENSOR_2_TPC7_CFG_BASE 0x7FFCFC6470ull
+#define KERNEL_TENSOR_2_TPC7_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_2_TPC7_CFG_SECTION 0x3800
+#define mmKERNEL_TENSOR_3_TPC7_CFG_BASE 0x7FFCFC64A8ull
+#define KERNEL_TENSOR_3_TPC7_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_3_TPC7_CFG_SECTION 0x3800
+#define mmKERNEL_TENSOR_4_TPC7_CFG_BASE 0x7FFCFC64E0ull
+#define KERNEL_TENSOR_4_TPC7_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_4_TPC7_CFG_SECTION 0x3800
+#define mmKERNEL_TENSOR_5_TPC7_CFG_BASE 0x7FFCFC6518ull
+#define KERNEL_TENSOR_5_TPC7_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_5_TPC7_CFG_SECTION 0x3800
+#define mmKERNEL_TENSOR_6_TPC7_CFG_BASE 0x7FFCFC6550ull
+#define KERNEL_TENSOR_6_TPC7_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_6_TPC7_CFG_SECTION 0x3800
+#define mmKERNEL_TENSOR_7_TPC7_CFG_BASE 0x7FFCFC6588ull
+#define KERNEL_TENSOR_7_TPC7_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_7_TPC7_CFG_SECTION 0x3800
+#define mmKERNEL_TENSOR_8_TPC7_CFG_BASE 0x7FFCFC65C0ull
+#define KERNEL_TENSOR_8_TPC7_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_8_TPC7_CFG_SECTION 0x3800
+#define mmKERNEL_TENSOR_9_TPC7_CFG_BASE 0x7FFCFC65F8ull
+#define KERNEL_TENSOR_9_TPC7_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_9_TPC7_CFG_SECTION 0x3800
+#define mmKERNEL_TENSOR_10_TPC7_CFG_BASE 0x7FFCFC6630ull
+#define KERNEL_TENSOR_10_TPC7_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_10_TPC7_CFG_SECTION 0x3800
+#define mmKERNEL_TENSOR_11_TPC7_CFG_BASE 0x7FFCFC6668ull
+#define KERNEL_TENSOR_11_TPC7_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_11_TPC7_CFG_SECTION 0x3800
+#define mmKERNEL_TENSOR_12_TPC7_CFG_BASE 0x7FFCFC66A0ull
+#define KERNEL_TENSOR_12_TPC7_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_12_TPC7_CFG_SECTION 0x3800
+#define mmKERNEL_TENSOR_13_TPC7_CFG_BASE 0x7FFCFC66D8ull
+#define KERNEL_TENSOR_13_TPC7_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_13_TPC7_CFG_SECTION 0x3800
+#define mmKERNEL_TENSOR_14_TPC7_CFG_BASE 0x7FFCFC6710ull
+#define KERNEL_TENSOR_14_TPC7_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_14_TPC7_CFG_SECTION 0x3800
+#define mmKERNEL_TENSOR_15_TPC7_CFG_BASE 0x7FFCFC6748ull
+#define KERNEL_TENSOR_15_TPC7_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_15_TPC7_CFG_SECTION 0x3800
+#define mmKERNEL_SYNC_OBJECT_TPC7_CFG_BASE 0x7FFCFC6780ull
+#define KERNEL_SYNC_OBJECT_TPC7_CFG_MAX_OFFSET 0x8000
+#define KERNEL_SYNC_OBJECT_TPC7_CFG_SECTION 0x8000
+#define mmKERNEL_TPC7_CFG_BASE 0x7FFCFC6788ull
+#define KERNEL_TPC7_CFG_MAX_OFFSET 0xB800
+#define KERNEL_TPC7_CFG_SECTION 0x2780
+#define mmQM_TENSOR_0_TPC7_CFG_BASE 0x7FFCFC6A00ull
+#define QM_TENSOR_0_TPC7_CFG_MAX_OFFSET 0x3800
+#define QM_TENSOR_0_TPC7_CFG_SECTION 0x3800
+#define mmQM_TENSOR_1_TPC7_CFG_BASE 0x7FFCFC6A38ull
+#define QM_TENSOR_1_TPC7_CFG_MAX_OFFSET 0x3800
+#define QM_TENSOR_1_TPC7_CFG_SECTION 0x3800
+#define mmQM_TENSOR_2_TPC7_CFG_BASE 0x7FFCFC6A70ull
+#define QM_TENSOR_2_TPC7_CFG_MAX_OFFSET 0x3800
+#define QM_TENSOR_2_TPC7_CFG_SECTION 0x3800
+#define mmQM_TENSOR_3_TPC7_CFG_BASE 0x7FFCFC6AA8ull
+#define QM_TENSOR_3_TPC7_CFG_MAX_OFFSET 0x3800
+#define QM_TENSOR_3_TPC7_CFG_SECTION 0x3800
+#define mmQM_TENSOR_4_TPC7_CFG_BASE 0x7FFCFC6AE0ull
+#define QM_TENSOR_4_TPC7_CFG_MAX_OFFSET 0x3800
+#define QM_TENSOR_4_TPC7_CFG_SECTION 0x3800
+#define mmQM_TENSOR_5_TPC7_CFG_BASE 0x7FFCFC6B18ull
+#define QM_TENSOR_5_TPC7_CFG_MAX_OFFSET 0x3800
+#define QM_TENSOR_5_TPC7_CFG_SECTION 0x3800
+#define mmQM_TENSOR_6_TPC7_CFG_BASE 0x7FFCFC6B50ull
+#define QM_TENSOR_6_TPC7_CFG_MAX_OFFSET 0x3800
+#define QM_TENSOR_6_TPC7_CFG_SECTION 0x3800
+#define mmQM_TENSOR_7_TPC7_CFG_BASE 0x7FFCFC6B88ull
+#define QM_TENSOR_7_TPC7_CFG_MAX_OFFSET 0x3800
+#define QM_TENSOR_7_TPC7_CFG_SECTION 0x3800
+#define mmQM_TENSOR_8_TPC7_CFG_BASE 0x7FFCFC6BC0ull
+#define QM_TENSOR_8_TPC7_CFG_MAX_OFFSET 0x3800
+#define QM_TENSOR_8_TPC7_CFG_SECTION 0x3800
+#define mmQM_TENSOR_9_TPC7_CFG_BASE 0x7FFCFC6BF8ull
+#define QM_TENSOR_9_TPC7_CFG_MAX_OFFSET 0x3800
+#define QM_TENSOR_9_TPC7_CFG_SECTION 0x3800
+#define mmQM_TENSOR_10_TPC7_CFG_BASE 0x7FFCFC6C30ull
+#define QM_TENSOR_10_TPC7_CFG_MAX_OFFSET 0x3800
+#define QM_TENSOR_10_TPC7_CFG_SECTION 0x3800
+#define mmQM_TENSOR_11_TPC7_CFG_BASE 0x7FFCFC6C68ull
+#define QM_TENSOR_11_TPC7_CFG_MAX_OFFSET 0x3800
+#define QM_TENSOR_11_TPC7_CFG_SECTION 0x3800
+#define mmQM_TENSOR_12_TPC7_CFG_BASE 0x7FFCFC6CA0ull
+#define QM_TENSOR_12_TPC7_CFG_MAX_OFFSET 0x3800
+#define QM_TENSOR_12_TPC7_CFG_SECTION 0x3800
+#define mmQM_TENSOR_13_TPC7_CFG_BASE 0x7FFCFC6CD8ull
+#define QM_TENSOR_13_TPC7_CFG_MAX_OFFSET 0x3800
+#define QM_TENSOR_13_TPC7_CFG_SECTION 0x3800
+#define mmQM_TENSOR_14_TPC7_CFG_BASE 0x7FFCFC6D10ull
+#define QM_TENSOR_14_TPC7_CFG_MAX_OFFSET 0x3800
+#define QM_TENSOR_14_TPC7_CFG_SECTION 0x3800
+#define mmQM_TENSOR_15_TPC7_CFG_BASE 0x7FFCFC6D48ull
+#define QM_TENSOR_15_TPC7_CFG_MAX_OFFSET 0x3800
+#define QM_TENSOR_15_TPC7_CFG_SECTION 0x3800
+#define mmQM_SYNC_OBJECT_TPC7_CFG_BASE 0x7FFCFC6D80ull
+#define QM_SYNC_OBJECT_TPC7_CFG_MAX_OFFSET 0x8000
+#define QM_SYNC_OBJECT_TPC7_CFG_SECTION 0x8000
+#define mmQM_TPC7_CFG_BASE 0x7FFCFC6D88ull
+#define QM_TPC7_CFG_MAX_OFFSET 0xB800
+#define QM_TPC7_CFG_SECTION 0x2780
+#define mmTPC7_E2E_CRED_BASE 0x7FFCFC7000ull
+#define TPC7_E2E_CRED_MAX_OFFSET 0x1680
+#define TPC7_E2E_CRED_SECTION 0x1000
+#define mmTPC7_QM_BASE 0x7FFCFC8000ull
+#define TPC7_QM_MAX_OFFSET 0xD040
+#define TPC7_QM_SECTION 0x1038000
+#define mmMME_S_ROM_TABLE_BASE 0x7FFE000000ull
+#define MME_S_ROM_TABLE_MAX_OFFSET 0x1000
+#define MME_S_ROM_TABLE_SECTION 0x21000
+#define mmMME0_ACC_STM_BASE 0x7FFE021000ull
+#define MME0_ACC_STM_MAX_OFFSET 0x1000
+#define MME0_ACC_STM_SECTION 0x1000
+#define mmMME0_ACC_CTI_BASE 0x7FFE022000ull
+#define MME0_ACC_CTI_MAX_OFFSET 0x1000
+#define MME0_ACC_CTI_SECTION 0x1000
+#define mmMME0_ACC_ETF_BASE 0x7FFE023000ull
+#define MME0_ACC_ETF_MAX_OFFSET 0x1000
+#define MME0_ACC_ETF_SECTION 0x1000
+#define mmMME0_ACC_SPMU_BASE 0x7FFE024000ull
+#define MME0_ACC_SPMU_MAX_OFFSET 0x1000
+#define MME0_ACC_SPMU_SECTION 0x1000
+#define mmMME0_ACC_CTI0_BASE 0x7FFE025000ull
+#define MME0_ACC_CTI0_MAX_OFFSET 0x1000
+#define MME0_ACC_CTI0_SECTION 0x1000
+#define mmMME0_ACC_CTI1_BASE 0x7FFE026000ull
+#define MME0_ACC_CTI1_MAX_OFFSET 0x1000
+#define MME0_ACC_CTI1_SECTION 0x1000
+#define mmMME0_ACC_BMON0_BASE 0x7FFE027000ull
+#define MME0_ACC_BMON0_MAX_OFFSET 0x1000
+#define MME0_ACC_BMON0_SECTION 0x9000
+#define mmMME0_ACC_FUNNEL_BASE 0x7FFE030000ull
+#define MME0_ACC_FUNNEL_MAX_OFFSET 0x1000
+#define MME0_ACC_FUNNEL_SECTION 0x11000
+#define mmMME0_SBAB_STM_BASE 0x7FFE041000ull
+#define MME0_SBAB_STM_MAX_OFFSET 0x1000
+#define MME0_SBAB_STM_SECTION 0x1000
+#define mmMME0_SBAB_CTI_BASE 0x7FFE042000ull
+#define MME0_SBAB_CTI_MAX_OFFSET 0x1000
+#define MME0_SBAB_CTI_SECTION 0x1000
+#define mmMME0_SBAB_ETF_BASE 0x7FFE043000ull
+#define MME0_SBAB_ETF_MAX_OFFSET 0x1000
+#define MME0_SBAB_ETF_SECTION 0x1000
+#define mmMME0_SBAB_SPMU_BASE 0x7FFE044000ull
+#define MME0_SBAB_SPMU_MAX_OFFSET 0x1000
+#define MME0_SBAB_SPMU_SECTION 0x1000
+#define mmMME0_SBAB_CTI0_BASE 0x7FFE045000ull
+#define MME0_SBAB_CTI0_MAX_OFFSET 0x1000
+#define MME0_SBAB_CTI0_SECTION 0x1000
+#define mmMME0_SBAB_CTI1_BASE 0x7FFE046000ull
+#define MME0_SBAB_CTI1_MAX_OFFSET 0x1000
+#define MME0_SBAB_CTI1_SECTION 0x1000
+#define mmMME0_SBAB_BMON0_BASE 0x7FFE047000ull
+#define MME0_SBAB_BMON0_MAX_OFFSET 0x1000
+#define MME0_SBAB_BMON0_SECTION 0x1000
+#define mmMME0_SBAB_BMON1_BASE 0x7FFE048000ull
+#define MME0_SBAB_BMON1_MAX_OFFSET 0x1000
+#define MME0_SBAB_BMON1_SECTION 0x19000
+#define mmMME0_CTRL_STM_BASE 0x7FFE061000ull
+#define MME0_CTRL_STM_MAX_OFFSET 0x1000
+#define MME0_CTRL_STM_SECTION 0x1000
+#define mmMME0_CTRL_CTI_BASE 0x7FFE062000ull
+#define MME0_CTRL_CTI_MAX_OFFSET 0x1000
+#define MME0_CTRL_CTI_SECTION 0x1000
+#define mmMME0_CTRL_ETF_BASE 0x7FFE063000ull
+#define MME0_CTRL_ETF_MAX_OFFSET 0x1000
+#define MME0_CTRL_ETF_SECTION 0x1000
+#define mmMME0_CTRL_SPMU_BASE 0x7FFE064000ull
+#define MME0_CTRL_SPMU_MAX_OFFSET 0x1000
+#define MME0_CTRL_SPMU_SECTION 0x1000
+#define mmMME0_CTRL_CTI0_BASE 0x7FFE065000ull
+#define MME0_CTRL_CTI0_MAX_OFFSET 0x1000
+#define MME0_CTRL_CTI0_SECTION 0x1000
+#define mmMME0_CTRL_CTI1_BASE 0x7FFE066000ull
+#define MME0_CTRL_CTI1_MAX_OFFSET 0x1000
+#define MME0_CTRL_CTI1_SECTION 0x1000
+#define mmMME0_CTRL_BMON0_BASE 0x7FFE067000ull
+#define MME0_CTRL_BMON0_MAX_OFFSET 0x1000
+#define MME0_CTRL_BMON0_SECTION 0x1000
+#define mmMME0_CTRL_BMON1_BASE 0x7FFE068000ull
+#define MME0_CTRL_BMON1_MAX_OFFSET 0x1000
+#define MME0_CTRL_BMON1_SECTION 0x39000
+#define mmMME1_ACC_STM_BASE 0x7FFE0A1000ull
+#define MME1_ACC_STM_MAX_OFFSET 0x1000
+#define MME1_ACC_STM_SECTION 0x1000
+#define mmMME1_ACC_CTI_BASE 0x7FFE0A2000ull
+#define MME1_ACC_CTI_MAX_OFFSET 0x1000
+#define MME1_ACC_CTI_SECTION 0x1000
+#define mmMME1_ACC_ETF_BASE 0x7FFE0A3000ull
+#define MME1_ACC_ETF_MAX_OFFSET 0x1000
+#define MME1_ACC_ETF_SECTION 0x1000
+#define mmMME1_ACC_SPMU_BASE 0x7FFE0A4000ull
+#define MME1_ACC_SPMU_MAX_OFFSET 0x1000
+#define MME1_ACC_SPMU_SECTION 0x1000
+#define mmMME1_ACC_CTI0_BASE 0x7FFE0A5000ull
+#define MME1_ACC_CTI0_MAX_OFFSET 0x1000
+#define MME1_ACC_CTI0_SECTION 0x1000
+#define mmMME1_ACC_CTI1_BASE 0x7FFE0A6000ull
+#define MME1_ACC_CTI1_MAX_OFFSET 0x1000
+#define MME1_ACC_CTI1_SECTION 0x1000
+#define mmMME1_ACC_BMON0_BASE 0x7FFE0A7000ull
+#define MME1_ACC_BMON0_MAX_OFFSET 0x1000
+#define MME1_ACC_BMON0_SECTION 0x9000
+#define mmMME1_ACC_FUNNEL_BASE 0x7FFE0B0000ull
+#define MME1_ACC_FUNNEL_MAX_OFFSET 0x1000
+#define MME1_ACC_FUNNEL_SECTION 0x11000
+#define mmMME1_SBAB_STM_BASE 0x7FFE0C1000ull
+#define MME1_SBAB_STM_MAX_OFFSET 0x1000
+#define MME1_SBAB_STM_SECTION 0x1000
+#define mmMME1_SBAB_CTI_BASE 0x7FFE0C2000ull
+#define MME1_SBAB_CTI_MAX_OFFSET 0x1000
+#define MME1_SBAB_CTI_SECTION 0x1000
+#define mmMME1_SBAB_ETF_BASE 0x7FFE0C3000ull
+#define MME1_SBAB_ETF_MAX_OFFSET 0x1000
+#define MME1_SBAB_ETF_SECTION 0x1000
+#define mmMME1_SBAB_SPMU_BASE 0x7FFE0C4000ull
+#define MME1_SBAB_SPMU_MAX_OFFSET 0x1000
+#define MME1_SBAB_SPMU_SECTION 0x1000
+#define mmMME1_SBAB_CTI0_BASE 0x7FFE0C5000ull
+#define MME1_SBAB_CTI0_MAX_OFFSET 0x1000
+#define MME1_SBAB_CTI0_SECTION 0x1000
+#define mmMME1_SBAB_CTI1_BASE 0x7FFE0C6000ull
+#define MME1_SBAB_CTI1_MAX_OFFSET 0x1000
+#define MME1_SBAB_CTI1_SECTION 0x1000
+#define mmMME1_SBAB_BMON0_BASE 0x7FFE0C7000ull
+#define MME1_SBAB_BMON0_MAX_OFFSET 0x1000
+#define MME1_SBAB_BMON0_SECTION 0x1000
+#define mmMME1_SBAB_BMON1_BASE 0x7FFE0C8000ull
+#define MME1_SBAB_BMON1_MAX_OFFSET 0x1000
+#define MME1_SBAB_BMON1_SECTION 0x19000
+#define mmMME1_CTRL_STM_BASE 0x7FFE0E1000ull
+#define MME1_CTRL_STM_MAX_OFFSET 0x1000
+#define MME1_CTRL_STM_SECTION 0x1000
+#define mmMME1_CTRL_CTI_BASE 0x7FFE0E2000ull
+#define MME1_CTRL_CTI_MAX_OFFSET 0x1000
+#define MME1_CTRL_CTI_SECTION 0x1000
+#define mmMME1_CTRL_ETF_BASE 0x7FFE0E3000ull
+#define MME1_CTRL_ETF_MAX_OFFSET 0x1000
+#define MME1_CTRL_ETF_SECTION 0x1000
+#define mmMME1_CTRL_SPMU_BASE 0x7FFE0E4000ull
+#define MME1_CTRL_SPMU_MAX_OFFSET 0x1000
+#define MME1_CTRL_SPMU_SECTION 0x1000
+#define mmMME1_CTRL_CTI0_BASE 0x7FFE0E5000ull
+#define MME1_CTRL_CTI0_MAX_OFFSET 0x1000
+#define MME1_CTRL_CTI0_SECTION 0x1000
+#define mmMME1_CTRL_CTI1_BASE 0x7FFE0E6000ull
+#define MME1_CTRL_CTI1_MAX_OFFSET 0x1000
+#define MME1_CTRL_CTI1_SECTION 0x1000
+#define mmMME1_CTRL_BMON0_BASE 0x7FFE0E7000ull
+#define MME1_CTRL_BMON0_MAX_OFFSET 0x1000
+#define MME1_CTRL_BMON0_SECTION 0x1000
+#define mmMME1_CTRL_BMON1_BASE 0x7FFE0E8000ull
+#define MME1_CTRL_BMON1_MAX_OFFSET 0x1000
+#define MME1_CTRL_BMON1_SECTION 0x18000
+#define mmMME_N_ROM_TABLE_BASE 0x7FFE100000ull
+#define MME_N_ROM_TABLE_MAX_OFFSET 0x1000
+#define MME_N_ROM_TABLE_SECTION 0x21000
+#define mmMME2_ACC_STM_BASE 0x7FFE121000ull
+#define MME2_ACC_STM_MAX_OFFSET 0x1000
+#define MME2_ACC_STM_SECTION 0x1000
+#define mmMME2_ACC_CTI_BASE 0x7FFE122000ull
+#define MME2_ACC_CTI_MAX_OFFSET 0x1000
+#define MME2_ACC_CTI_SECTION 0x1000
+#define mmMME2_MME2_ACC_ETF_BASE 0x7FFE123000ull
+#define MME2_MME2_ACC_ETF_MAX_OFFSET 0x1000
+#define MME2_MME2_ACC_ETF_SECTION 0x1000
+#define mmMME2_ACC_SPMU_BASE 0x7FFE124000ull
+#define MME2_ACC_SPMU_MAX_OFFSET 0x1000
+#define MME2_ACC_SPMU_SECTION 0x1000
+#define mmMME2_ACC_CTI0_BASE 0x7FFE125000ull
+#define MME2_ACC_CTI0_MAX_OFFSET 0x1000
+#define MME2_ACC_CTI0_SECTION 0x1000
+#define mmMME2_ACC_CTI1_BASE 0x7FFE126000ull
+#define MME2_ACC_CTI1_MAX_OFFSET 0x1000
+#define MME2_ACC_CTI1_SECTION 0x1000
+#define mmMME2_ACC_BMON0_BASE 0x7FFE127000ull
+#define MME2_ACC_BMON0_MAX_OFFSET 0x1000
+#define MME2_ACC_BMON0_SECTION 0x9000
+#define mmMME2_ACC_FUNNEL_BASE 0x7FFE130000ull
+#define MME2_ACC_FUNNEL_MAX_OFFSET 0x1000
+#define MME2_ACC_FUNNEL_SECTION 0x11000
+#define mmMME2_SBAB_STM_BASE 0x7FFE141000ull
+#define MME2_SBAB_STM_MAX_OFFSET 0x1000
+#define MME2_SBAB_STM_SECTION 0x1000
+#define mmMME2_SBAB_CTI_BASE 0x7FFE142000ull
+#define MME2_SBAB_CTI_MAX_OFFSET 0x1000
+#define MME2_SBAB_CTI_SECTION 0x1000
+#define mmMME2_SBAB_ETF_BASE 0x7FFE143000ull
+#define MME2_SBAB_ETF_MAX_OFFSET 0x1000
+#define MME2_SBAB_ETF_SECTION 0x1000
+#define mmMME2_SBAB_SPMU_BASE 0x7FFE144000ull
+#define MME2_SBAB_SPMU_MAX_OFFSET 0x1000
+#define MME2_SBAB_SPMU_SECTION 0x1000
+#define mmMME2_SBAB_CTI0_BASE 0x7FFE145000ull
+#define MME2_SBAB_CTI0_MAX_OFFSET 0x1000
+#define MME2_SBAB_CTI0_SECTION 0x1000
+#define mmMME2_SBAB_CTI1_BASE 0x7FFE146000ull
+#define MME2_SBAB_CTI1_MAX_OFFSET 0x1000
+#define MME2_SBAB_CTI1_SECTION 0x1000
+#define mmMME2_SBAB_BMON0_BASE 0x7FFE147000ull
+#define MME2_SBAB_BMON0_MAX_OFFSET 0x1000
+#define MME2_SBAB_BMON0_SECTION 0x1000
+#define mmMME2_SBAB_BMON1_BASE 0x7FFE148000ull
+#define MME2_SBAB_BMON1_MAX_OFFSET 0x1000
+#define MME2_SBAB_BMON1_SECTION 0x19000
+#define mmMME2_CTRL_STM_BASE 0x7FFE161000ull
+#define MME2_CTRL_STM_MAX_OFFSET 0x1000
+#define MME2_CTRL_STM_SECTION 0x1000
+#define mmMME2_CTRL_CTI_BASE 0x7FFE162000ull
+#define MME2_CTRL_CTI_MAX_OFFSET 0x1000
+#define MME2_CTRL_CTI_SECTION 0x1000
+#define mmMME2_CTRL_ETF_BASE 0x7FFE163000ull
+#define MME2_CTRL_ETF_MAX_OFFSET 0x1000
+#define MME2_CTRL_ETF_SECTION 0x1000
+#define mmMME2_CTRL_SPMU_BASE 0x7FFE164000ull
+#define MME2_CTRL_SPMU_MAX_OFFSET 0x1000
+#define MME2_CTRL_SPMU_SECTION 0x1000
+#define mmMME2_CTRL_CTI0_BASE 0x7FFE165000ull
+#define MME2_CTRL_CTI0_MAX_OFFSET 0x1000
+#define MME2_CTRL_CTI0_SECTION 0x1000
+#define mmMME2_CTRL_CTI1_BASE 0x7FFE166000ull
+#define MME2_CTRL_CTI1_MAX_OFFSET 0x1000
+#define MME2_CTRL_CTI1_SECTION 0x1000
+#define mmMME2_CTRL_BMON0_BASE 0x7FFE167000ull
+#define MME2_CTRL_BMON0_MAX_OFFSET 0x1000
+#define MME2_CTRL_BMON0_SECTION 0x1000
+#define mmMME2_CTRL_BMON1_BASE 0x7FFE168000ull
+#define MME2_CTRL_BMON1_MAX_OFFSET 0x1000
+#define MME2_CTRL_BMON1_SECTION 0x39000
+#define mmMME3_ACC_STM_BASE 0x7FFE1A1000ull
+#define MME3_ACC_STM_MAX_OFFSET 0x1000
+#define MME3_ACC_STM_SECTION 0x1000
+#define mmMME3_ACC_CTI_BASE 0x7FFE1A2000ull
+#define MME3_ACC_CTI_MAX_OFFSET 0x1000
+#define MME3_ACC_CTI_SECTION 0x1000
+#define mmMME3_ACC_ETF_BASE 0x7FFE1A3000ull
+#define MME3_ACC_ETF_MAX_OFFSET 0x1000
+#define MME3_ACC_ETF_SECTION 0x1000
+#define mmMME3_ACC_SPMU_BASE 0x7FFE1A4000ull
+#define MME3_ACC_SPMU_MAX_OFFSET 0x1000
+#define MME3_ACC_SPMU_SECTION 0x1000
+#define mmMME3_ACC_CTI0_BASE 0x7FFE1A5000ull
+#define MME3_ACC_CTI0_MAX_OFFSET 0x1000
+#define MME3_ACC_CTI0_SECTION 0x1000
+#define mmMME3_ACC_CTI1_BASE 0x7FFE1A6000ull
+#define MME3_ACC_CTI1_MAX_OFFSET 0x1000
+#define MME3_ACC_CTI1_SECTION 0x1000
+#define mmMME3_ACC_BMON0_BASE 0x7FFE1A7000ull
+#define MME3_ACC_BMON0_MAX_OFFSET 0x1000
+#define MME3_ACC_BMON0_SECTION 0x9000
+#define mmMME3_ACC_FUNNEL_BASE 0x7FFE1B0000ull
+#define MME3_ACC_FUNNEL_MAX_OFFSET 0x1000
+#define MME3_ACC_FUNNEL_SECTION 0x11000
+#define mmMME3_SBAB_STM_BASE 0x7FFE1C1000ull
+#define MME3_SBAB_STM_MAX_OFFSET 0x1000
+#define MME3_SBAB_STM_SECTION 0x1000
+#define mmMME3_SBAB_CTI_BASE 0x7FFE1C2000ull
+#define MME3_SBAB_CTI_MAX_OFFSET 0x1000
+#define MME3_SBAB_CTI_SECTION 0x1000
+#define mmMME3_SBAB_ETF_BASE 0x7FFE1C3000ull
+#define MME3_SBAB_ETF_MAX_OFFSET 0x1000
+#define MME3_SBAB_ETF_SECTION 0x1000
+#define mmMME3_SBAB_SPMU_BASE 0x7FFE1C4000ull
+#define MME3_SBAB_SPMU_MAX_OFFSET 0x1000
+#define MME3_SBAB_SPMU_SECTION 0x1000
+#define mmMME3_SBAB_CTI0_BASE 0x7FFE1C5000ull
+#define MME3_SBAB_CTI0_MAX_OFFSET 0x1000
+#define MME3_SBAB_CTI0_SECTION 0x1000
+#define mmMME3_SBAB_CTI1_BASE 0x7FFE1C6000ull
+#define MME3_SBAB_CTI1_MAX_OFFSET 0x1000
+#define MME3_SBAB_CTI1_SECTION 0x1000
+#define mmMME3_SBAB_BMON0_BASE 0x7FFE1C7000ull
+#define MME3_SBAB_BMON0_MAX_OFFSET 0x1000
+#define MME3_SBAB_BMON0_SECTION 0x1000
+#define mmMME3_SBAB_BMON1_BASE 0x7FFE1C8000ull
+#define MME3_SBAB_BMON1_MAX_OFFSET 0x1000
+#define MME3_SBAB_BMON1_SECTION 0x19000
+#define mmMME3_CTRL_STM_BASE 0x7FFE1E1000ull
+#define MME3_CTRL_STM_MAX_OFFSET 0x1000
+#define MME3_CTRL_STM_SECTION 0x1000
+#define mmMME3_CTRL_CTI_BASE 0x7FFE1E2000ull
+#define MME3_CTRL_CTI_MAX_OFFSET 0x1000
+#define MME3_CTRL_CTI_SECTION 0x1000
+#define mmMME3_CTRL_ETF_BASE 0x7FFE1E3000ull
+#define MME3_CTRL_ETF_MAX_OFFSET 0x1000
+#define MME3_CTRL_ETF_SECTION 0x1000
+#define mmMME3_CTRL_SPMU_BASE 0x7FFE1E4000ull
+#define MME3_CTRL_SPMU_MAX_OFFSET 0x1000
+#define MME3_CTRL_SPMU_SECTION 0x1000
+#define mmMME3_CTRL_CTI0_BASE 0x7FFE1E5000ull
+#define MME3_CTRL_CTI0_MAX_OFFSET 0x1000
+#define MME3_CTRL_CTI0_SECTION 0x1000
+#define mmMME3_CTRL_CTI1_BASE 0x7FFE1E6000ull
+#define MME3_CTRL_CTI1_MAX_OFFSET 0x1000
+#define MME3_CTRL_CTI1_SECTION 0x1000
+#define mmMME3_CTRL_BMON0_BASE 0x7FFE1E7000ull
+#define MME3_CTRL_BMON0_MAX_OFFSET 0x1000
+#define MME3_CTRL_BMON0_SECTION 0x1000
+#define mmMME3_CTRL_BMON1_BASE 0x7FFE1E8000ull
+#define MME3_CTRL_BMON1_MAX_OFFSET 0x1000
+#define MME3_CTRL_BMON1_SECTION 0x18000
+#define mmIC_ROM_TABLE_BASE 0x7FFE200000ull
+#define IC_ROM_TABLE_MAX_OFFSET 0x1000
+#define IC_ROM_TABLE_SECTION 0x1000
+#define mmSRAM_Y0_X0_FUNNEL_BASE 0x7FFE201000ull
+#define SRAM_Y0_X0_FUNNEL_MAX_OFFSET 0x1000
+#define SRAM_Y0_X0_FUNNEL_SECTION 0x8000
+#define mmSRAM_Y0_X1_FUNNEL_BASE 0x7FFE209000ull
+#define SRAM_Y0_X1_FUNNEL_MAX_OFFSET 0x1000
+#define SRAM_Y0_X1_FUNNEL_SECTION 0x8000
+#define mmSRAM_Y0_X2_FUNNEL_BASE 0x7FFE211000ull
+#define SRAM_Y0_X2_FUNNEL_MAX_OFFSET 0x1000
+#define SRAM_Y0_X2_FUNNEL_SECTION 0x8000
+#define mmSRAM_Y0_X3_FUNNEL_BASE 0x7FFE219000ull
+#define SRAM_Y0_X3_FUNNEL_MAX_OFFSET 0x1000
+#define SRAM_Y0_X3_FUNNEL_SECTION 0x8000
+#define mmSRAM_Y0_X4_FUNNEL_BASE 0x7FFE221000ull
+#define SRAM_Y0_X4_FUNNEL_MAX_OFFSET 0x1000
+#define SRAM_Y0_X4_FUNNEL_SECTION 0x8000
+#define mmSRAM_Y0_X5_FUNNEL_BASE 0x7FFE229000ull
+#define SRAM_Y0_X5_FUNNEL_MAX_OFFSET 0x1000
+#define SRAM_Y0_X5_FUNNEL_SECTION 0x8000
+#define mmSRAM_Y0_X6_FUNNEL_BASE 0x7FFE231000ull
+#define SRAM_Y0_X6_FUNNEL_MAX_OFFSET 0x1000
+#define SRAM_Y0_X6_FUNNEL_SECTION 0x8000
+#define mmSRAM_Y0_X7_FUNNEL_BASE 0x7FFE239000ull
+#define SRAM_Y0_X7_FUNNEL_MAX_OFFSET 0x1000
+#define SRAM_Y0_X7_FUNNEL_SECTION 0x8000
+#define mmSRAM_Y1_X0_FUNNEL_BASE 0x7FFE241000ull
+#define SRAM_Y1_X0_FUNNEL_MAX_OFFSET 0x1000
+#define SRAM_Y1_X0_FUNNEL_SECTION 0x8000
+#define mmSRAM_Y1_X1_FUNNEL_BASE 0x7FFE249000ull
+#define SRAM_Y1_X1_FUNNEL_MAX_OFFSET 0x1000
+#define SRAM_Y1_X1_FUNNEL_SECTION 0x8000
+#define mmSRAM_Y1_X2_FUNNEL_BASE 0x7FFE251000ull
+#define SRAM_Y1_X2_FUNNEL_MAX_OFFSET 0x1000
+#define SRAM_Y1_X2_FUNNEL_SECTION 0x8000
+#define mmSRAM_Y1_X3_FUNNEL_BASE 0x7FFE259000ull
+#define SRAM_Y1_X3_FUNNEL_MAX_OFFSET 0x1000
+#define SRAM_Y1_X3_FUNNEL_SECTION 0x8000
+#define mmSRAM_Y1_X4_FUNNEL_BASE 0x7FFE261000ull
+#define SRAM_Y1_X4_FUNNEL_MAX_OFFSET 0x1000
+#define SRAM_Y1_X4_FUNNEL_SECTION 0x8000
+#define mmSRAM_Y1_X5_FUNNEL_BASE 0x7FFE269000ull
+#define SRAM_Y1_X5_FUNNEL_MAX_OFFSET 0x1000
+#define SRAM_Y1_X5_FUNNEL_SECTION 0x8000
+#define mmSRAM_Y1_X6_FUNNEL_BASE 0x7FFE271000ull
+#define SRAM_Y1_X6_FUNNEL_MAX_OFFSET 0x1000
+#define SRAM_Y1_X6_FUNNEL_SECTION 0x8000
+#define mmSRAM_Y1_X7_FUNNEL_BASE 0x7FFE279000ull
+#define SRAM_Y1_X7_FUNNEL_MAX_OFFSET 0x1000
+#define SRAM_Y1_X7_FUNNEL_SECTION 0x8000
+#define mmSRAM_Y2_X0_FUNNEL_BASE 0x7FFE281000ull
+#define SRAM_Y2_X0_FUNNEL_MAX_OFFSET 0x1000
+#define SRAM_Y2_X0_FUNNEL_SECTION 0x8000
+#define mmSRAM_Y2_X1_FUNNEL_BASE 0x7FFE289000ull
+#define SRAM_Y2_X1_FUNNEL_MAX_OFFSET 0x1000
+#define SRAM_Y2_X1_FUNNEL_SECTION 0x8000
+#define mmSRAM_Y2_X2_FUNNEL_BASE 0x7FFE291000ull
+#define SRAM_Y2_X2_FUNNEL_MAX_OFFSET 0x1000
+#define SRAM_Y2_X2_FUNNEL_SECTION 0x8000
+#define mmSRAM_Y2_X3_FUNNEL_BASE 0x7FFE299000ull
+#define SRAM_Y2_X3_FUNNEL_MAX_OFFSET 0x1000
+#define SRAM_Y2_X3_FUNNEL_SECTION 0x8000
+#define mmSRAM_Y2_X4_FUNNEL_BASE 0x7FFE2A1000ull
+#define SRAM_Y2_X4_FUNNEL_MAX_OFFSET 0x1000
+#define SRAM_Y2_X4_FUNNEL_SECTION 0x8000
+#define mmSRAM_Y2_X5_FUNNEL_BASE 0x7FFE2A9000ull
+#define SRAM_Y2_X5_FUNNEL_MAX_OFFSET 0x1000
+#define SRAM_Y2_X5_FUNNEL_SECTION 0x8000
+#define mmSRAM_Y2_X6_FUNNEL_BASE 0x7FFE2B1000ull
+#define SRAM_Y2_X6_FUNNEL_MAX_OFFSET 0x1000
+#define SRAM_Y2_X6_FUNNEL_SECTION 0x8000
+#define mmSRAM_Y2_X7_FUNNEL_BASE 0x7FFE2B9000ull
+#define SRAM_Y2_X7_FUNNEL_MAX_OFFSET 0x1000
+#define SRAM_Y2_X7_FUNNEL_SECTION 0x8000
+#define mmSRAM_Y3_X0_FUNNEL_BASE 0x7FFE2C1000ull
+#define SRAM_Y3_X0_FUNNEL_MAX_OFFSET 0x1000
+#define SRAM_Y3_X0_FUNNEL_SECTION 0x8000
+#define mmSRAM_Y3_X1_FUNNEL_BASE 0x7FFE2C9000ull
+#define SRAM_Y3_X1_FUNNEL_MAX_OFFSET 0x1000
+#define SRAM_Y3_X1_FUNNEL_SECTION 0x8000
+#define mmSRAM_Y3_X2_FUNNEL_BASE 0x7FFE2D1000ull
+#define SRAM_Y3_X2_FUNNEL_MAX_OFFSET 0x1000
+#define SRAM_Y3_X2_FUNNEL_SECTION 0x8000
+#define mmSRAM_Y3_X4_FUNNEL_BASE 0x7FFE2D9000ull
+#define SRAM_Y3_X4_FUNNEL_MAX_OFFSET 0x1000
+#define SRAM_Y3_X4_FUNNEL_SECTION 0x8000
+#define mmSRAM_Y3_X3_FUNNEL_BASE 0x7FFE2E1000ull
+#define SRAM_Y3_X3_FUNNEL_MAX_OFFSET 0x1000
+#define SRAM_Y3_X3_FUNNEL_SECTION 0x8000
+#define mmSRAM_Y3_X5_FUNNEL_BASE 0x7FFE2E9000ull
+#define SRAM_Y3_X5_FUNNEL_MAX_OFFSET 0x1000
+#define SRAM_Y3_X5_FUNNEL_SECTION 0x8000
+#define mmSRAM_Y3_X6_FUNNEL_BASE 0x7FFE2F1000ull
+#define SRAM_Y3_X6_FUNNEL_MAX_OFFSET 0x1000
+#define SRAM_Y3_X6_FUNNEL_SECTION 0x8000
+#define mmSRAM_Y3_X7_FUNNEL_BASE 0x7FFE2F9000ull
+#define SRAM_Y3_X7_FUNNEL_MAX_OFFSET 0x1000
+#define SRAM_Y3_X7_FUNNEL_SECTION 0x7000
+#define mmIF_ROM_TABLE_BASE 0x7FFE300000ull
+#define IF_ROM_TABLE_MAX_OFFSET 0x1000
+#define IF_ROM_TABLE_SECTION 0x1000
+#define mmSIF_FUNNEL_0_BASE 0x7FFE301000ull
+#define SIF_FUNNEL_0_MAX_OFFSET 0x1000
+#define SIF_FUNNEL_0_SECTION 0x10000
+#define mmSIF_FUNNEL_1_BASE 0x7FFE311000ull
+#define SIF_FUNNEL_1_MAX_OFFSET 0x1000
+#define SIF_FUNNEL_1_SECTION 0x10000
+#define mmSIF_FUNNEL_2_BASE 0x7FFE321000ull
+#define SIF_FUNNEL_2_MAX_OFFSET 0x1000
+#define SIF_FUNNEL_2_SECTION 0x10000
+#define mmSIF_FUNNEL_3_BASE 0x7FFE331000ull
+#define SIF_FUNNEL_3_MAX_OFFSET 0x1000
+#define SIF_FUNNEL_3_SECTION 0x10000
+#define mmSIF_FUNNEL_4_BASE 0x7FFE341000ull
+#define SIF_FUNNEL_4_MAX_OFFSET 0x1000
+#define SIF_FUNNEL_4_SECTION 0x10000
+#define mmSIF_FUNNEL_5_BASE 0x7FFE351000ull
+#define SIF_FUNNEL_5_MAX_OFFSET 0x1000
+#define SIF_FUNNEL_5_SECTION 0x10000
+#define mmSIF_FUNNEL_6_BASE 0x7FFE361000ull
+#define SIF_FUNNEL_6_MAX_OFFSET 0x1000
+#define SIF_FUNNEL_6_SECTION 0x10000
+#define mmSIF_FUNNEL_7_BASE 0x7FFE371000ull
+#define SIF_FUNNEL_7_MAX_OFFSET 0x1000
+#define SIF_FUNNEL_7_SECTION 0x10000
+#define mmNIF_FUNNEL_0_BASE 0x7FFE381000ull
+#define NIF_FUNNEL_0_MAX_OFFSET 0x1000
+#define NIF_FUNNEL_0_SECTION 0x10000
+#define mmNIF_FUNNEL_1_BASE 0x7FFE391000ull
+#define NIF_FUNNEL_1_MAX_OFFSET 0x1000
+#define NIF_FUNNEL_1_SECTION 0x10000
+#define mmNIF_FUNNEL_2_BASE 0x7FFE3A1000ull
+#define NIF_FUNNEL_2_MAX_OFFSET 0x1000
+#define NIF_FUNNEL_2_SECTION 0x10000
+#define mmNIF_FUNNEL_3_BASE 0x7FFE3B1000ull
+#define NIF_FUNNEL_3_MAX_OFFSET 0x1000
+#define NIF_FUNNEL_3_SECTION 0x10000
+#define mmNIF_FUNNEL_4_BASE 0x7FFE3C1000ull
+#define NIF_FUNNEL_4_MAX_OFFSET 0x1000
+#define NIF_FUNNEL_4_SECTION 0x10000
+#define mmNIF_FUNNEL_5_BASE 0x7FFE3D1000ull
+#define NIF_FUNNEL_5_MAX_OFFSET 0x1000
+#define NIF_FUNNEL_5_SECTION 0x10000
+#define mmNIF_FUNNEL_6_BASE 0x7FFE3E1000ull
+#define NIF_FUNNEL_6_MAX_OFFSET 0x1000
+#define NIF_FUNNEL_6_SECTION 0x10000
+#define mmNIF_FUNNEL_7_BASE 0x7FFE3F1000ull
+#define NIF_FUNNEL_7_MAX_OFFSET 0x1000
+#define NIF_FUNNEL_7_SECTION 0xF000
+#define mmDMA_IF_ROM_TABLE_BASE 0x7FFE400000ull
+#define DMA_IF_ROM_TABLE_MAX_OFFSET 0x1000
+#define DMA_IF_ROM_TABLE_SECTION 0x1000
+#define mmDMA_IF_W_S_STM_BASE 0x7FFE401000ull
+#define DMA_IF_W_S_STM_MAX_OFFSET 0x1000
+#define DMA_IF_W_S_STM_SECTION 0x1000
+#define mmDMA_IF_W_S_CTI_BASE 0x7FFE402000ull
+#define DMA_IF_W_S_CTI_MAX_OFFSET 0x1000
+#define DMA_IF_W_S_CTI_SECTION 0x1000
+#define mmDMA_IF_W_S_ETF_BASE 0x7FFE403000ull
+#define DMA_IF_W_S_ETF_MAX_OFFSET 0x1000
+#define DMA_IF_W_S_ETF_SECTION 0x2000
+#define mmDMA_IF_W_S_BMON0_CTI_BASE 0x7FFE405000ull
+#define DMA_IF_W_S_BMON0_CTI_MAX_OFFSET 0x1000
+#define DMA_IF_W_S_BMON0_CTI_SECTION 0x1000
+#define mmDMA_IF_W_S_BMON1_CTI_BASE 0x7FFE406000ull
+#define DMA_IF_W_S_BMON1_CTI_MAX_OFFSET 0x1000
+#define DMA_IF_W_S_BMON1_CTI_SECTION 0x1000
+#define mmDMA_IF_W_S_HBM0_WR_BMON_BASE 0x7FFE407000ull
+#define DMA_IF_W_S_HBM0_WR_BMON_MAX_OFFSET 0x1000
+#define DMA_IF_W_S_HBM0_WR_BMON_SECTION 0x1000
+#define mmDMA_IF_W_S_HBM0_RD_BMON_BASE 0x7FFE408000ull
+#define DMA_IF_W_S_HBM0_RD_BMON_MAX_OFFSET 0x1000
+#define DMA_IF_W_S_HBM0_RD_BMON_SECTION 0x1000
+#define mmDMA_IF_W_S_HBM1_WR_BMON_BASE 0x7FFE409000ull
+#define DMA_IF_W_S_HBM1_WR_BMON_MAX_OFFSET 0x1000
+#define DMA_IF_W_S_HBM1_WR_BMON_SECTION 0x1000
+#define mmDMA_IF_W_S_HBM1_RD_BMON_BASE 0x7FFE40A000ull
+#define DMA_IF_W_S_HBM1_RD_BMON_MAX_OFFSET 0x1000
+#define DMA_IF_W_S_HBM1_RD_BMON_SECTION 0x1000
+#define mmDMA_IF_W_S_SOB_WR_BMON_BASE 0x7FFE40B000ull
+#define DMA_IF_W_S_SOB_WR_BMON_MAX_OFFSET 0x1000
+#define DMA_IF_W_S_SOB_WR_BMON_SECTION 0x4000
+#define mmDMA_IF_W_S_FUNNEL_BASE 0x7FFE40F000ull
+#define DMA_IF_W_S_FUNNEL_MAX_OFFSET 0x1000
+#define DMA_IF_W_S_FUNNEL_SECTION 0x12000
+#define mmDMA_IF_E_S_STM_BASE 0x7FFE421000ull
+#define DMA_IF_E_S_STM_MAX_OFFSET 0x1000
+#define DMA_IF_E_S_STM_SECTION 0x1000
+#define mmDMA_IF_E_S_CTI_BASE 0x7FFE422000ull
+#define DMA_IF_E_S_CTI_MAX_OFFSET 0x1000
+#define DMA_IF_E_S_CTI_SECTION 0x1000
+#define mmDMA_IF_E_S_ETF_BASE 0x7FFE423000ull
+#define DMA_IF_E_S_ETF_MAX_OFFSET 0x1000
+#define DMA_IF_E_S_ETF_SECTION 0x2000
+#define mmDMA_IF_E_S_BMON0_CTI_BASE 0x7FFE425000ull
+#define DMA_IF_E_S_BMON0_CTI_MAX_OFFSET 0x1000
+#define DMA_IF_E_S_BMON0_CTI_SECTION 0x1000
+#define mmDMA_IF_E_S_BMON1_CTI_BASE 0x7FFE426000ull
+#define DMA_IF_E_S_BMON1_CTI_MAX_OFFSET 0x1000
+#define DMA_IF_E_S_BMON1_CTI_SECTION 0x1000
+#define mmDMA_IF_E_S_HBM0_WR_BMON_BASE 0x7FFE427000ull
+#define DMA_IF_E_S_HBM0_WR_BMON_MAX_OFFSET 0x1000
+#define DMA_IF_E_S_HBM0_WR_BMON_SECTION 0x1000
+#define mmDMA_IF_E_S_HBM0_RD_BMON_BASE 0x7FFE428000ull
+#define DMA_IF_E_S_HBM0_RD_BMON_MAX_OFFSET 0x1000
+#define DMA_IF_E_S_HBM0_RD_BMON_SECTION 0x1000
+#define mmDMA_IF_E_S_HBM1_WR_BMON_BASE 0x7FFE429000ull
+#define DMA_IF_E_S_HBM1_WR_BMON_MAX_OFFSET 0x1000
+#define DMA_IF_E_S_HBM1_WR_BMON_SECTION 0x1000
+#define mmDMA_IF_E_S_HBM1_RD_BMON_BASE 0x7FFE42A000ull
+#define DMA_IF_E_S_HBM1_RD_BMON_MAX_OFFSET 0x1000
+#define DMA_IF_E_S_HBM1_RD_BMON_SECTION 0x1000
+#define mmDMA_IF_E_S_SOB_WR_BMON_BASE 0x7FFE42B000ull
+#define DMA_IF_E_S_SOB_WR_BMON_MAX_OFFSET 0x1000
+#define DMA_IF_E_S_SOB_WR_BMON_SECTION 0x4000
+#define mmDMA_IF_E_S_FUNNEL_BASE 0x7FFE42F000ull
+#define DMA_IF_E_S_FUNNEL_MAX_OFFSET 0x1000
+#define DMA_IF_E_S_FUNNEL_SECTION 0x12000
+#define mmDMA_IF_W_N_STM_BASE 0x7FFE441000ull
+#define DMA_IF_W_N_STM_MAX_OFFSET 0x1000
+#define DMA_IF_W_N_STM_SECTION 0x1000
+#define mmDMA_IF_W_N_CTI_BASE 0x7FFE442000ull
+#define DMA_IF_W_N_CTI_MAX_OFFSET 0x1000
+#define DMA_IF_W_N_CTI_SECTION 0x1000
+#define mmDMA_IF_W_N_ETF_BASE 0x7FFE443000ull
+#define DMA_IF_W_N_ETF_MAX_OFFSET 0x1000
+#define DMA_IF_W_N_ETF_SECTION 0x2000
+#define mmDMA_IF_W_N_BMON0_CTI_BASE 0x7FFE445000ull
+#define DMA_IF_W_N_BMON0_CTI_MAX_OFFSET 0x1000
+#define DMA_IF_W_N_BMON0_CTI_SECTION 0x1000
+#define mmDMA_IF_W_N_BMON1_CTI_BASE 0x7FFE446000ull
+#define DMA_IF_W_N_BMON1_CTI_MAX_OFFSET 0x1000
+#define DMA_IF_W_N_BMON1_CTI_SECTION 0x1000
+#define mmDMA_IF_W_N_HBM0_WR_BMON_BASE 0x7FFE447000ull
+#define DMA_IF_W_N_HBM0_WR_BMON_MAX_OFFSET 0x1000
+#define DMA_IF_W_N_HBM0_WR_BMON_SECTION 0x1000
+#define mmDMA_IF_W_N_HBM0_RD_BMON_BASE 0x7FFE448000ull
+#define DMA_IF_W_N_HBM0_RD_BMON_MAX_OFFSET 0x1000
+#define DMA_IF_W_N_HBM0_RD_BMON_SECTION 0x1000
+#define mmDMA_IF_W_N_HBM1_WR_BMON_BASE 0x7FFE449000ull
+#define DMA_IF_W_N_HBM1_WR_BMON_MAX_OFFSET 0x1000
+#define DMA_IF_W_N_HBM1_WR_BMON_SECTION 0x1000
+#define mmDMA_IF_W_N_HBM1_RD_BMON_BASE 0x7FFE44A000ull
+#define DMA_IF_W_N_HBM1_RD_BMON_MAX_OFFSET 0x1000
+#define DMA_IF_W_N_HBM1_RD_BMON_SECTION 0x1000
+#define mmDMA_IF_W_N_SOB_WR_BMON_BASE 0x7FFE44B000ull
+#define DMA_IF_W_N_SOB_WR_BMON_MAX_OFFSET 0x1000
+#define DMA_IF_W_N_SOB_WR_BMON_SECTION 0x4000
+#define mmDMA_IF_W_N_FUNNEL_BASE 0x7FFE44F000ull
+#define DMA_IF_W_N_FUNNEL_MAX_OFFSET 0x1000
+#define DMA_IF_W_N_FUNNEL_SECTION 0x12000
+#define mmDMA_IF_E_N_STM_BASE 0x7FFE461000ull
+#define DMA_IF_E_N_STM_MAX_OFFSET 0x1000
+#define DMA_IF_E_N_STM_SECTION 0x1000
+#define mmDMA_IF_E_N_CTI_BASE 0x7FFE462000ull
+#define DMA_IF_E_N_CTI_MAX_OFFSET 0x1000
+#define DMA_IF_E_N_CTI_SECTION 0x1000
+#define mmDMA_IF_E_N_ETF_BASE 0x7FFE463000ull
+#define DMA_IF_E_N_ETF_MAX_OFFSET 0x1000
+#define DMA_IF_E_N_ETF_SECTION 0x2000
+#define mmDMA_IF_E_N_BMON0_CTI_BASE 0x7FFE465000ull
+#define DMA_IF_E_N_BMON0_CTI_MAX_OFFSET 0x1000
+#define DMA_IF_E_N_BMON0_CTI_SECTION 0x1000
+#define mmDMA_IF_E_N_BMON1_CTI_BASE 0x7FFE466000ull
+#define DMA_IF_E_N_BMON1_CTI_MAX_OFFSET 0x1000
+#define DMA_IF_E_N_BMON1_CTI_SECTION 0x1000
+#define mmDMA_IF_E_N_HBM0_WR_BMON_BASE 0x7FFE467000ull
+#define DMA_IF_E_N_HBM0_WR_BMON_MAX_OFFSET 0x1000
+#define DMA_IF_E_N_HBM0_WR_BMON_SECTION 0x1000
+#define mmDMA_IF_E_N_HBM0_RD_BMON_BASE 0x7FFE468000ull
+#define DMA_IF_E_N_HBM0_RD_BMON_MAX_OFFSET 0x1000
+#define DMA_IF_E_N_HBM0_RD_BMON_SECTION 0x1000
+#define mmDMA_IF_E_N_HBM1_WR_BMON_BASE 0x7FFE469000ull
+#define DMA_IF_E_N_HBM1_WR_BMON_MAX_OFFSET 0x1000
+#define DMA_IF_E_N_HBM1_WR_BMON_SECTION 0x1000
+#define mmDMA_IF_E_N_HBM1_RD_BMON_BASE 0x7FFE46A000ull
+#define DMA_IF_E_N_HBM1_RD_BMON_MAX_OFFSET 0x1000
+#define DMA_IF_E_N_HBM1_RD_BMON_SECTION 0x1000
+#define mmDMA_IF_E_N_SOB_WR_BMON_BASE 0x7FFE46B000ull
+#define DMA_IF_E_N_SOB_WR_BMON_MAX_OFFSET 0x1000
+#define DMA_IF_E_N_SOB_WR_BMON_SECTION 0x4000
+#define mmDMA_IF_E_N_FUNNEL_BASE 0x7FFE46F000ull
+#define DMA_IF_E_N_FUNNEL_MAX_OFFSET 0x1000
+#define DMA_IF_E_N_FUNNEL_SECTION 0x11000
+#define mmCPU_ROM_TABLE_BASE 0x7FFE480000ull
+#define CPU_ROM_TABLE_MAX_OFFSET 0x1000
+#define CPU_ROM_TABLE_SECTION 0x1000
+#define mmCPU_ETF_0_BASE 0x7FFE481000ull
+#define CPU_ETF_0_MAX_OFFSET 0x1000
+#define CPU_ETF_0_SECTION 0x1000
+#define mmCPU_ETF_1_BASE 0x7FFE482000ull
+#define CPU_ETF_1_MAX_OFFSET 0x1000
+#define CPU_ETF_1_SECTION 0x2000
+#define mmCPU_CTI_BASE 0x7FFE484000ull
+#define CPU_CTI_MAX_OFFSET 0x1000
+#define CPU_CTI_SECTION 0x1000
+#define mmCPU_FUNNEL_BASE 0x7FFE485000ull
+#define CPU_FUNNEL_MAX_OFFSET 0x1000
+#define CPU_FUNNEL_SECTION 0x1000
+#define mmCPU_STM_BASE 0x7FFE486000ull
+#define CPU_STM_MAX_OFFSET 0x1000
+#define CPU_STM_SECTION 0x1000
+#define mmCPU_CTI_TRACE_BASE 0x7FFE487000ull
+#define CPU_CTI_TRACE_MAX_OFFSET 0x1000
+#define CPU_CTI_TRACE_SECTION 0x1000
+#define mmCPU_ETF_TRACE_BASE 0x7FFE488000ull
+#define CPU_ETF_TRACE_MAX_OFFSET 0x1000
+#define CPU_ETF_TRACE_SECTION 0x1000
+#define mmCPU_WR_BMON_BASE 0x7FFE489000ull
+#define CPU_WR_BMON_MAX_OFFSET 0x1000
+#define CPU_WR_BMON_SECTION 0x1000
+#define mmCPU_RD_BMON_BASE 0x7FFE48A000ull
+#define CPU_RD_BMON_MAX_OFFSET 0x1000
+#define CPU_RD_BMON_SECTION 0x76000
+#define mmDMA_ROM_TABLE_BASE 0x7FFE500000ull
+#define DMA_ROM_TABLE_MAX_OFFSET 0x1000
+#define DMA_ROM_TABLE_SECTION 0x1000
+#define mmDMA_CH_0_CS_STM_BASE 0x7FFE501000ull
+#define DMA_CH_0_CS_STM_MAX_OFFSET 0x1000
+#define DMA_CH_0_CS_STM_SECTION 0x1000
+#define mmDMA_CH_0_CS_CTI_BASE 0x7FFE502000ull
+#define DMA_CH_0_CS_CTI_MAX_OFFSET 0x1000
+#define DMA_CH_0_CS_CTI_SECTION 0x1000
+#define mmDMA_CH_0_CS_ETF_BASE 0x7FFE503000ull
+#define DMA_CH_0_CS_ETF_MAX_OFFSET 0x1000
+#define DMA_CH_0_CS_ETF_SECTION 0x1000
+#define mmDMA_CH_0_CS_SPMU_BASE 0x7FFE504000ull
+#define DMA_CH_0_CS_SPMU_MAX_OFFSET 0x1000
+#define DMA_CH_0_CS_SPMU_SECTION 0x1000
+#define mmDMA_CH_0_BMON_CTI_BASE 0x7FFE505000ull
+#define DMA_CH_0_BMON_CTI_MAX_OFFSET 0x1000
+#define DMA_CH_0_BMON_CTI_SECTION 0x1000
+#define mmDMA_CH_0_USER_CTI_BASE 0x7FFE506000ull
+#define DMA_CH_0_USER_CTI_MAX_OFFSET 0x1000
+#define DMA_CH_0_USER_CTI_SECTION 0x1000
+#define mmDMA_CH_0_BMON_0_BASE 0x7FFE507000ull
+#define DMA_CH_0_BMON_0_MAX_OFFSET 0x1000
+#define DMA_CH_0_BMON_0_SECTION 0x1000
+#define mmDMA_CH_0_BMON_1_BASE 0x7FFE508000ull
+#define DMA_CH_0_BMON_1_MAX_OFFSET 0x1000
+#define DMA_CH_0_BMON_1_SECTION 0x19000
+#define mmDMA_CH_1_CS_STM_BASE 0x7FFE521000ull
+#define DMA_CH_1_CS_STM_MAX_OFFSET 0x1000
+#define DMA_CH_1_CS_STM_SECTION 0x1000
+#define mmDMA_CH_1_CS_CTI_BASE 0x7FFE522000ull
+#define DMA_CH_1_CS_CTI_MAX_OFFSET 0x1000
+#define DMA_CH_1_CS_CTI_SECTION 0x1000
+#define mmDMA_CH_1_CS_ETF_BASE 0x7FFE523000ull
+#define DMA_CH_1_CS_ETF_MAX_OFFSET 0x1000
+#define DMA_CH_1_CS_ETF_SECTION 0x1000
+#define mmDMA_CH_1_CS_SPMU_BASE 0x7FFE524000ull
+#define DMA_CH_1_CS_SPMU_MAX_OFFSET 0x1000
+#define DMA_CH_1_CS_SPMU_SECTION 0x1000
+#define mmDMA_CH_1_BMON_CTI_BASE 0x7FFE525000ull
+#define DMA_CH_1_BMON_CTI_MAX_OFFSET 0x1000
+#define DMA_CH_1_BMON_CTI_SECTION 0x1000
+#define mmDMA_CH_1_USER_CTI_BASE 0x7FFE526000ull
+#define DMA_CH_1_USER_CTI_MAX_OFFSET 0x1000
+#define DMA_CH_1_USER_CTI_SECTION 0x1000
+#define mmDMA_CH_1_BMON_0_BASE 0x7FFE527000ull
+#define DMA_CH_1_BMON_0_MAX_OFFSET 0x1000
+#define DMA_CH_1_BMON_0_SECTION 0x1000
+#define mmDMA_CH_1_BMON_1_BASE 0x7FFE528000ull
+#define DMA_CH_1_BMON_1_MAX_OFFSET 0x1000
+#define DMA_CH_1_BMON_1_SECTION 0x19000
+#define mmDMA_CH_2_CS_STM_BASE 0x7FFE541000ull
+#define DMA_CH_2_CS_STM_MAX_OFFSET 0x1000
+#define DMA_CH_2_CS_STM_SECTION 0x1000
+#define mmDMA_CH_2_CS_CTI_BASE 0x7FFE542000ull
+#define DMA_CH_2_CS_CTI_MAX_OFFSET 0x1000
+#define DMA_CH_2_CS_CTI_SECTION 0x1000
+#define mmDMA_CH_2_CS_ETF_BASE 0x7FFE543000ull
+#define DMA_CH_2_CS_ETF_MAX_OFFSET 0x1000
+#define DMA_CH_2_CS_ETF_SECTION 0x1000
+#define mmDMA_CH_2_CS_SPMU_BASE 0x7FFE544000ull
+#define DMA_CH_2_CS_SPMU_MAX_OFFSET 0x1000
+#define DMA_CH_2_CS_SPMU_SECTION 0x1000
+#define mmDMA_CH_2_BMON_CTI_BASE 0x7FFE545000ull
+#define DMA_CH_2_BMON_CTI_MAX_OFFSET 0x1000
+#define DMA_CH_2_BMON_CTI_SECTION 0x1000
+#define mmDMA_CH_2_USER_CTI_BASE 0x7FFE546000ull
+#define DMA_CH_2_USER_CTI_MAX_OFFSET 0x1000
+#define DMA_CH_2_USER_CTI_SECTION 0x1000
+#define mmDMA_CH_2_BMON_0_BASE 0x7FFE547000ull
+#define DMA_CH_2_BMON_0_MAX_OFFSET 0x1000
+#define DMA_CH_2_BMON_0_SECTION 0x1000
+#define mmDMA_CH_2_BMON_1_BASE 0x7FFE548000ull
+#define DMA_CH_2_BMON_1_MAX_OFFSET 0x1000
+#define DMA_CH_2_BMON_1_SECTION 0x19000
+#define mmDMA_CH_3_CS_STM_BASE 0x7FFE561000ull
+#define DMA_CH_3_CS_STM_MAX_OFFSET 0x1000
+#define DMA_CH_3_CS_STM_SECTION 0x1000
+#define mmDMA_CH_3_CS_CTI_BASE 0x7FFE562000ull
+#define DMA_CH_3_CS_CTI_MAX_OFFSET 0x1000
+#define DMA_CH_3_CS_CTI_SECTION 0x1000
+#define mmDMA_CH_3_CS_ETF_BASE 0x7FFE563000ull
+#define DMA_CH_3_CS_ETF_MAX_OFFSET 0x1000
+#define DMA_CH_3_CS_ETF_SECTION 0x1000
+#define mmDMA_CH_3_CS_SPMU_BASE 0x7FFE564000ull
+#define DMA_CH_3_CS_SPMU_MAX_OFFSET 0x1000
+#define DMA_CH_3_CS_SPMU_SECTION 0x1000
+#define mmDMA_CH_3_BMON_CTI_BASE 0x7FFE565000ull
+#define DMA_CH_3_BMON_CTI_MAX_OFFSET 0x1000
+#define DMA_CH_3_BMON_CTI_SECTION 0x1000
+#define mmDMA_CH_3_USER_CTI_BASE 0x7FFE566000ull
+#define DMA_CH_3_USER_CTI_MAX_OFFSET 0x1000
+#define DMA_CH_3_USER_CTI_SECTION 0x1000
+#define mmDMA_CH_3_BMON_0_BASE 0x7FFE567000ull
+#define DMA_CH_3_BMON_0_MAX_OFFSET 0x1000
+#define DMA_CH_3_BMON_0_SECTION 0x1000
+#define mmDMA_CH_3_BMON_1_BASE 0x7FFE568000ull
+#define DMA_CH_3_BMON_1_MAX_OFFSET 0x1000
+#define DMA_CH_3_BMON_1_SECTION 0x19000
+#define mmDMA_CH_4_CS_STM_BASE 0x7FFE581000ull
+#define DMA_CH_4_CS_STM_MAX_OFFSET 0x1000
+#define DMA_CH_4_CS_STM_SECTION 0x1000
+#define mmDMA_CH_4_CS_CTI_BASE 0x7FFE582000ull
+#define DMA_CH_4_CS_CTI_MAX_OFFSET 0x1000
+#define DMA_CH_4_CS_CTI_SECTION 0x1000
+#define mmDMA_CH_4_CS_ETF_BASE 0x7FFE583000ull
+#define DMA_CH_4_CS_ETF_MAX_OFFSET 0x1000
+#define DMA_CH_4_CS_ETF_SECTION 0x1000
+#define mmDMA_CH_4_CS_SPMU_BASE 0x7FFE584000ull
+#define DMA_CH_4_CS_SPMU_MAX_OFFSET 0x1000
+#define DMA_CH_4_CS_SPMU_SECTION 0x1000
+#define mmDMA_CH_4_BMON_CTI_BASE 0x7FFE585000ull
+#define DMA_CH_4_BMON_CTI_MAX_OFFSET 0x1000
+#define DMA_CH_4_BMON_CTI_SECTION 0x1000
+#define mmDMA_CH_4_USER_CTI_BASE 0x7FFE586000ull
+#define DMA_CH_4_USER_CTI_MAX_OFFSET 0x1000
+#define DMA_CH_4_USER_CTI_SECTION 0x1000
+#define mmDMA_CH_4_BMON_0_BASE 0x7FFE587000ull
+#define DMA_CH_4_BMON_0_MAX_OFFSET 0x1000
+#define DMA_CH_4_BMON_0_SECTION 0x1000
+#define mmDMA_CH_4_BMON_1_BASE 0x7FFE588000ull
+#define DMA_CH_4_BMON_1_MAX_OFFSET 0x1000
+#define DMA_CH_4_BMON_1_SECTION 0x19000
+#define mmDMA_CH_5_CS_STM_BASE 0x7FFE5A1000ull
+#define DMA_CH_5_CS_STM_MAX_OFFSET 0x1000
+#define DMA_CH_5_CS_STM_SECTION 0x1000
+#define mmDMA_CH_5_CS_CTI_BASE 0x7FFE5A2000ull
+#define DMA_CH_5_CS_CTI_MAX_OFFSET 0x1000
+#define DMA_CH_5_CS_CTI_SECTION 0x1000
+#define mmDMA_CH_5_CS_ETF_BASE 0x7FFE5A3000ull
+#define DMA_CH_5_CS_ETF_MAX_OFFSET 0x1000
+#define DMA_CH_5_CS_ETF_SECTION 0x1000
+#define mmDMA_CH_5_CS_SPMU_BASE 0x7FFE5A4000ull
+#define DMA_CH_5_CS_SPMU_MAX_OFFSET 0x1000
+#define DMA_CH_5_CS_SPMU_SECTION 0x1000
+#define mmDMA_CH_5_BMON_CTI_BASE 0x7FFE5A5000ull
+#define DMA_CH_5_BMON_CTI_MAX_OFFSET 0x1000
+#define DMA_CH_5_BMON_CTI_SECTION 0x1000
+#define mmDMA_CH_5_USER_CTI_BASE 0x7FFE5A6000ull
+#define DMA_CH_5_USER_CTI_MAX_OFFSET 0x1000
+#define DMA_CH_5_USER_CTI_SECTION 0x1000
+#define mmDMA_CH_5_BMON_0_BASE 0x7FFE5A7000ull
+#define DMA_CH_5_BMON_0_MAX_OFFSET 0x1000
+#define DMA_CH_5_BMON_0_SECTION 0x1000
+#define mmDMA_CH_5_BMON_1_BASE 0x7FFE5A8000ull
+#define DMA_CH_5_BMON_1_MAX_OFFSET 0x1000
+#define DMA_CH_5_BMON_1_SECTION 0x19000
+#define mmDMA_CH_6_CS_STM_BASE 0x7FFE5C1000ull
+#define DMA_CH_6_CS_STM_MAX_OFFSET 0x1000
+#define DMA_CH_6_CS_STM_SECTION 0x1000
+#define mmDMA_CH_6_CS_CTI_BASE 0x7FFE5C2000ull
+#define DMA_CH_6_CS_CTI_MAX_OFFSET 0x1000
+#define DMA_CH_6_CS_CTI_SECTION 0x1000
+#define mmDMA_CH_6_CS_ETF_BASE 0x7FFE5C3000ull
+#define DMA_CH_6_CS_ETF_MAX_OFFSET 0x1000
+#define DMA_CH_6_CS_ETF_SECTION 0x1000
+#define mmDMA_CH_6_CS_SPMU_BASE 0x7FFE5C4000ull
+#define DMA_CH_6_CS_SPMU_MAX_OFFSET 0x1000
+#define DMA_CH_6_CS_SPMU_SECTION 0x1000
+#define mmDMA_CH_6_BMON_CTI_BASE 0x7FFE5C5000ull
+#define DMA_CH_6_BMON_CTI_MAX_OFFSET 0x1000
+#define DMA_CH_6_BMON_CTI_SECTION 0x1000
+#define mmDMA_CH_6_USER_CTI_BASE 0x7FFE5C6000ull
+#define DMA_CH_6_USER_CTI_MAX_OFFSET 0x1000
+#define DMA_CH_6_USER_CTI_SECTION 0x1000
+#define mmDMA_CH_6_BMON_0_BASE 0x7FFE5C7000ull
+#define DMA_CH_6_BMON_0_MAX_OFFSET 0x1000
+#define DMA_CH_6_BMON_0_SECTION 0x1000
+#define mmDMA_CH_6_BMON_1_BASE 0x7FFE5C8000ull
+#define DMA_CH_6_BMON_1_MAX_OFFSET 0x1000
+#define DMA_CH_6_BMON_1_SECTION 0x19000
+#define mmDMA_CH_7_CS_STM_BASE 0x7FFE5E1000ull
+#define DMA_CH_7_CS_STM_MAX_OFFSET 0x1000
+#define DMA_CH_7_CS_STM_SECTION 0x1000
+#define mmDMA_CH_7_CS_CTI_BASE 0x7FFE5E2000ull
+#define DMA_CH_7_CS_CTI_MAX_OFFSET 0x1000
+#define DMA_CH_7_CS_CTI_SECTION 0x1000
+#define mmDMA_CH_7_CS_ETF_BASE 0x7FFE5E3000ull
+#define DMA_CH_7_CS_ETF_MAX_OFFSET 0x1000
+#define DMA_CH_7_CS_ETF_SECTION 0x1000
+#define mmDMA_CH_7_CS_SPMU_BASE 0x7FFE5E4000ull
+#define DMA_CH_7_CS_SPMU_MAX_OFFSET 0x1000
+#define DMA_CH_7_CS_SPMU_SECTION 0x1000
+#define mmDMA_CH_7_BMON_CTI_BASE 0x7FFE5E5000ull
+#define DMA_CH_7_BMON_CTI_MAX_OFFSET 0x1000
+#define DMA_CH_7_BMON_CTI_SECTION 0x1000
+#define mmDMA_CH_7_USER_CTI_BASE 0x7FFE5E6000ull
+#define DMA_CH_7_USER_CTI_MAX_OFFSET 0x1000
+#define DMA_CH_7_USER_CTI_SECTION 0x1000
+#define mmDMA_CH_7_BMON_0_BASE 0x7FFE5E7000ull
+#define DMA_CH_7_BMON_0_MAX_OFFSET 0x1000
+#define DMA_CH_7_BMON_0_SECTION 0x1000
+#define mmDMA_CH_7_BMON_1_BASE 0x7FFE5E8000ull
+#define DMA_CH_7_BMON_1_MAX_OFFSET 0x1000
+#define DMA_CH_7_BMON_1_SECTION 0x18000
+#define mmNIC_TPC_FUNNEL_W_S_BASE 0x7FFE600000ull
+#define NIC_TPC_FUNNEL_W_S_MAX_OFFSET 0x1000
+#define NIC_TPC_FUNNEL_W_S_SECTION 0x80000
+#define mmNIC_TPC_FUNNEL_E_S_BASE 0x7FFE680000ull
+#define NIC_TPC_FUNNEL_E_S_MAX_OFFSET 0x1000
+#define NIC_TPC_FUNNEL_E_S_SECTION 0x80000
+#define mmNIC_TPC_FUNNEL_W_N_BASE 0x7FFE700000ull
+#define NIC_TPC_FUNNEL_W_N_MAX_OFFSET 0x1000
+#define NIC_TPC_FUNNEL_W_N_SECTION 0x80000
+#define mmNIC_TPC_FUNNEL_E_N_BASE 0x7FFE780000ull
+#define NIC_TPC_FUNNEL_E_N_MAX_OFFSET 0x1000
+#define NIC_TPC_FUNNEL_E_N_SECTION 0x80000
+#define mmCA53_BASE 0x7FFE800000ull
+#define CA53_MAX_OFFSET 0x141000
+#define CA53_SECTION 0x400000
+#define mmPCI_ROM_TABLE_BASE 0x7FFEC00000ull
+#define PCI_ROM_TABLE_MAX_OFFSET 0x1000
+#define PCI_ROM_TABLE_SECTION 0x1000
+#define mmPCIE_STM_BASE 0x7FFEC01000ull
+#define PCIE_STM_MAX_OFFSET 0x1000
+#define PCIE_STM_SECTION 0x1000
+#define mmPCIE_ETF_BASE 0x7FFEC02000ull
+#define PCIE_ETF_MAX_OFFSET 0x1000
+#define PCIE_ETF_SECTION 0x1000
+#define mmPCIE_CTI_0_BASE 0x7FFEC03000ull
+#define PCIE_CTI_0_MAX_OFFSET 0x1000
+#define PCIE_CTI_0_SECTION 0x1000
+#define mmPCIE_SPMU_BASE 0x7FFEC04000ull
+#define PCIE_SPMU_MAX_OFFSET 0x1000
+#define PCIE_SPMU_SECTION 0x1000
+#define mmPCIE_CTI_1_BASE 0x7FFEC05000ull
+#define PCIE_CTI_1_MAX_OFFSET 0x1000
+#define PCIE_CTI_1_SECTION 0x1000
+#define mmPCIE_FUNNEL_BASE 0x7FFEC06000ull
+#define PCIE_FUNNEL_MAX_OFFSET 0x1000
+#define PCIE_FUNNEL_SECTION 0x1000
+#define mmPCIE_BMON_MSTR_WR_BASE 0x7FFEC07000ull
+#define PCIE_BMON_MSTR_WR_MAX_OFFSET 0x1000
+#define PCIE_BMON_MSTR_WR_SECTION 0x1000
+#define mmPCIE_BMON_MSTR_RD_BASE 0x7FFEC08000ull
+#define PCIE_BMON_MSTR_RD_MAX_OFFSET 0x1000
+#define PCIE_BMON_MSTR_RD_SECTION 0x1000
+#define mmPCIE_BMON_SLV_WR_BASE 0x7FFEC09000ull
+#define PCIE_BMON_SLV_WR_MAX_OFFSET 0x1000
+#define PCIE_BMON_SLV_WR_SECTION 0x1000
+#define mmPCIE_BMON_SLV_RD_BASE 0x7FFEC0A000ull
+#define PCIE_BMON_SLV_RD_MAX_OFFSET 0x1000
+#define PCIE_BMON_SLV_RD_SECTION 0x7000
+#define mmMMU_CS_STM_BASE 0x7FFEC11000ull
+#define MMU_CS_STM_MAX_OFFSET 0x1000
+#define MMU_CS_STM_SECTION 0x1000
+#define mmMMU_CS_CTI_BASE 0x7FFEC12000ull
+#define MMU_CS_CTI_MAX_OFFSET 0x1000
+#define MMU_CS_CTI_SECTION 0x1000
+#define mmMMU_CS_ETF_BASE 0x7FFEC13000ull
+#define MMU_CS_ETF_MAX_OFFSET 0x1000
+#define MMU_CS_ETF_SECTION 0x1000
+#define mmMMU_CS_SPMU_BASE 0x7FFEC14000ull
+#define MMU_CS_SPMU_MAX_OFFSET 0x1000
+#define MMU_CS_SPMU_SECTION 0x1000
+#define mmMMU_BMON_CTI_BASE 0x7FFEC15000ull
+#define MMU_BMON_CTI_MAX_OFFSET 0x1000
+#define MMU_BMON_CTI_SECTION 0x1000
+#define mmMMU_USER_CTI_BASE 0x7FFEC16000ull
+#define MMU_USER_CTI_MAX_OFFSET 0x1000
+#define MMU_USER_CTI_SECTION 0x1000
+#define mmMMU_BMON_0_BASE 0x7FFEC17000ull
+#define MMU_BMON_0_MAX_OFFSET 0x1000
+#define MMU_BMON_0_SECTION 0x1000
+#define mmMMU_BMON_1_BASE 0x7FFEC18000ull
+#define MMU_BMON_1_MAX_OFFSET 0x1000
+#define MMU_BMON_1_SECTION 0x28000
+#define mmPSOC_CTI_BASE 0x7FFEC40000ull
+#define PSOC_CTI_MAX_OFFSET 0x1000
+#define PSOC_CTI_SECTION 0x1000
+#define mmPSOC_STM_BASE 0x7FFEC41000ull
+#define PSOC_STM_MAX_OFFSET 0x1000
+#define PSOC_STM_SECTION 0x1000
+#define mmPSOC_FUNNEL_BASE 0x7FFEC42000ull
+#define PSOC_FUNNEL_MAX_OFFSET 0x1000
+#define PSOC_FUNNEL_SECTION 0x1000
+#define mmPSOC_ETR_BASE 0x7FFEC43000ull
+#define PSOC_ETR_MAX_OFFSET 0x1000
+#define PSOC_ETR_SECTION 0x1000
+#define mmPSOC_ETF_BASE 0x7FFEC44000ull
+#define PSOC_ETF_MAX_OFFSET 0x1000
+#define PSOC_ETF_SECTION 0x1000
+#define mmPSOC_TS_CTI_BASE 0x7FFEC45000ull
+#define PSOC_TS_CTI_MAX_OFFSET 0x1000
+#define PSOC_TS_CTI_SECTION 0xB000
+#define mmTOP_ROM_TABLE_BASE 0x7FFEC50000ull
+#define TOP_ROM_TABLE_MAX_OFFSET 0x1000
+#define TOP_ROM_TABLE_SECTION 0x70000
+#define mmNIC0_ROM_TABLE_BASE 0x7FFECC0000ull
+#define NIC0_ROM_TABLE_MAX_OFFSET 0x1000
+#define NIC0_ROM_TABLE_SECTION 0x1000
+#define mmSTM_0_NIC0_DBG_BASE 0x7FFECC1000ull
+#define STM_0_NIC0_DBG_MAX_OFFSET 0x21000
+#define STM_0_NIC0_DBG_SECTION 0x1000
+#define mmCTI_0_NIC0_DBG_BASE 0x7FFECC2000ull
+#define CTI_0_NIC0_DBG_MAX_OFFSET 0x1000
+#define CTI_0_NIC0_DBG_SECTION 0x1000
+#define mmETF_0_NIC0_DBG_BASE 0x7FFECC3000ull
+#define ETF_0_NIC0_DBG_MAX_OFFSET 0x1000
+#define ETF_0_NIC0_DBG_SECTION 0x1000
+#define mmSPMU_0_NIC0_DBG_BASE 0x7FFECC4000ull
+#define SPMU_0_NIC0_DBG_MAX_OFFSET 0x1000
+#define SPMU_0_NIC0_DBG_SECTION 0x2000
+#define mmUSER_CTI_0_NIC0_DBG_BASE 0x7FFECC6000ull
+#define USER_CTI_0_NIC0_DBG_MAX_OFFSET 0x1000
+#define USER_CTI_0_NIC0_DBG_SECTION 0xB000
+#define mmSTM_1_NIC0_DBG_BASE 0x7FFECD1000ull
+#define STM_1_NIC0_DBG_MAX_OFFSET 0x1000
+#define STM_1_NIC0_DBG_SECTION 0x1000
+#define mmCTI_1_NIC0_DBG_BASE 0x7FFECD2000ull
+#define CTI_1_NIC0_DBG_MAX_OFFSET 0x1000
+#define CTI_1_NIC0_DBG_SECTION 0x1000
+#define mmETF_1_NIC0_DBG_BASE 0x7FFECD3000ull
+#define ETF_1_NIC0_DBG_MAX_OFFSET 0x1000
+#define ETF_1_NIC0_DBG_SECTION 0x1000
+#define mmSPMU_1_NIC0_DBG_BASE 0x7FFECD4000ull
+#define SPMU_1_NIC0_DBG_MAX_OFFSET 0x1000
+#define SPMU_1_NIC0_DBG_SECTION 0x1000
+#define mmBMON_CTI_NIC0_DBG_BASE 0x7FFECD5000ull
+#define BMON_CTI_NIC0_DBG_MAX_OFFSET 0x1000
+#define BMON_CTI_NIC0_DBG_SECTION 0x1000
+#define mmUSER_CTI_1_NIC0_DBG_BASE 0x7FFECD6000ull
+#define USER_CTI_1_NIC0_DBG_MAX_OFFSET 0x1000
+#define USER_CTI_1_NIC0_DBG_SECTION 0x1000
+#define mmBMON0_NIC0_DBG_BASE 0x7FFECD7000ull
+#define BMON0_NIC0_DBG_MAX_OFFSET 0x1000
+#define BMON0_NIC0_DBG_SECTION 0x1000
+#define mmBMON1_NIC0_DBG_BASE 0x7FFECD8000ull
+#define BMON1_NIC0_DBG_MAX_OFFSET 0x1000
+#define BMON1_NIC0_DBG_SECTION 0x1000
+#define mmBMON2_NIC0_DBG_BASE 0x7FFECD9000ull
+#define BMON2_NIC0_DBG_MAX_OFFSET 0x1000
+#define BMON2_NIC0_DBG_SECTION 0x1000
+#define mmBMON3_NIC0_DBG_BASE 0x7FFECDA000ull
+#define BMON3_NIC0_DBG_MAX_OFFSET 0x1000
+#define BMON3_NIC0_DBG_SECTION 0x1000
+#define mmBMON4_NIC0_DBG_BASE 0x7FFECDB000ull
+#define BMON4_NIC0_DBG_MAX_OFFSET 0x1000
+#define BMON4_NIC0_DBG_SECTION 0x6000
+#define mmFUNNEL_NIC0_DBG_BASE 0x7FFECE1000ull
+#define FUNNEL_NIC0_DBG_MAX_OFFSET 0x1000
+#define FUNNEL_NIC0_DBG_SECTION 0x1F000
+#define mmNIC1_ROM_TABLE_BASE 0x7FFED00000ull
+#define NIC1_ROM_TABLE_MAX_OFFSET 0x1000
+#define NIC1_ROM_TABLE_SECTION 0x1000
+#define mmSTM_0_NIC1_DBG_BASE 0x7FFED01000ull
+#define STM_0_NIC1_DBG_MAX_OFFSET 0x21000
+#define STM_0_NIC1_DBG_SECTION 0x1000
+#define mmCTI_0_NIC1_DBG_BASE 0x7FFED02000ull
+#define CTI_0_NIC1_DBG_MAX_OFFSET 0x1000
+#define CTI_0_NIC1_DBG_SECTION 0x1000
+#define mmETF_0_NIC1_DBG_BASE 0x7FFED03000ull
+#define ETF_0_NIC1_DBG_MAX_OFFSET 0x1000
+#define ETF_0_NIC1_DBG_SECTION 0x1000
+#define mmSPMU_0_NIC1_DBG_BASE 0x7FFED04000ull
+#define SPMU_0_NIC1_DBG_MAX_OFFSET 0x1000
+#define SPMU_0_NIC1_DBG_SECTION 0x2000
+#define mmUSER_CTI_0_NIC1_DBG_BASE 0x7FFED06000ull
+#define USER_CTI_0_NIC1_DBG_MAX_OFFSET 0x1000
+#define USER_CTI_0_NIC1_DBG_SECTION 0xB000
+#define mmSTM_1_NIC1_DBG_BASE 0x7FFED11000ull
+#define STM_1_NIC1_DBG_MAX_OFFSET 0x1000
+#define STM_1_NIC1_DBG_SECTION 0x1000
+#define mmCTI_1_NIC1_DBG_BASE 0x7FFED12000ull
+#define CTI_1_NIC1_DBG_MAX_OFFSET 0x1000
+#define CTI_1_NIC1_DBG_SECTION 0x1000
+#define mmETF_1_NIC1_DBG_BASE 0x7FFED13000ull
+#define ETF_1_NIC1_DBG_MAX_OFFSET 0x1000
+#define ETF_1_NIC1_DBG_SECTION 0x1000
+#define mmSPMU_1_NIC1_DBG_BASE 0x7FFED14000ull
+#define SPMU_1_NIC1_DBG_MAX_OFFSET 0x1000
+#define SPMU_1_NIC1_DBG_SECTION 0x1000
+#define mmBMON_CTI_NIC1_DBG_BASE 0x7FFED15000ull
+#define BMON_CTI_NIC1_DBG_MAX_OFFSET 0x1000
+#define BMON_CTI_NIC1_DBG_SECTION 0x1000
+#define mmUSER_CTI_1_NIC1_DBG_BASE 0x7FFED16000ull
+#define USER_CTI_1_NIC1_DBG_MAX_OFFSET 0x1000
+#define USER_CTI_1_NIC1_DBG_SECTION 0x1000
+#define mmBMON0_NIC1_DBG_BASE 0x7FFED17000ull
+#define BMON0_NIC1_DBG_MAX_OFFSET 0x1000
+#define BMON0_NIC1_DBG_SECTION 0x1000
+#define mmBMON1_NIC1_DBG_BASE 0x7FFED18000ull
+#define BMON1_NIC1_DBG_MAX_OFFSET 0x1000
+#define BMON1_NIC1_DBG_SECTION 0x1000
+#define mmBMON2_NIC1_DBG_BASE 0x7FFED19000ull
+#define BMON2_NIC1_DBG_MAX_OFFSET 0x1000
+#define BMON2_NIC1_DBG_SECTION 0x1000
+#define mmBMON3_NIC1_DBG_BASE 0x7FFED1A000ull
+#define BMON3_NIC1_DBG_MAX_OFFSET 0x1000
+#define BMON3_NIC1_DBG_SECTION 0x1000
+#define mmBMON4_NIC1_DBG_BASE 0x7FFED1B000ull
+#define BMON4_NIC1_DBG_MAX_OFFSET 0x1000
+#define BMON4_NIC1_DBG_SECTION 0x6000
+#define mmFUNNEL_NIC1_DBG_BASE 0x7FFED21000ull
+#define FUNNEL_NIC1_DBG_MAX_OFFSET 0x1000
+#define FUNNEL_NIC1_DBG_SECTION 0x1F000
+#define mmNIC2_ROM_TABLE_BASE 0x7FFED40000ull
+#define NIC2_ROM_TABLE_MAX_OFFSET 0x1000
+#define NIC2_ROM_TABLE_SECTION 0x1000
+#define mmSTM_0_NIC2_DBG_BASE 0x7FFED41000ull
+#define STM_0_NIC2_DBG_MAX_OFFSET 0x21000
+#define STM_0_NIC2_DBG_SECTION 0x1000
+#define mmCTI_0_NIC2_DBG_BASE 0x7FFED42000ull
+#define CTI_0_NIC2_DBG_MAX_OFFSET 0x1000
+#define CTI_0_NIC2_DBG_SECTION 0x1000
+#define mmETF_0_NIC2_DBG_BASE 0x7FFED43000ull
+#define ETF_0_NIC2_DBG_MAX_OFFSET 0x1000
+#define ETF_0_NIC2_DBG_SECTION 0x1000
+#define mmSPMU_0_NIC2_DBG_BASE 0x7FFED44000ull
+#define SPMU_0_NIC2_DBG_MAX_OFFSET 0x1000
+#define SPMU_0_NIC2_DBG_SECTION 0x2000
+#define mmUSER_CTI_0_NIC2_DBG_BASE 0x7FFED46000ull
+#define USER_CTI_0_NIC2_DBG_MAX_OFFSET 0x1000
+#define USER_CTI_0_NIC2_DBG_SECTION 0xB000
+#define mmSTM_1_NIC2_DBG_BASE 0x7FFED51000ull
+#define STM_1_NIC2_DBG_MAX_OFFSET 0x1000
+#define STM_1_NIC2_DBG_SECTION 0x1000
+#define mmCTI_1_NIC2_DBG_BASE 0x7FFED52000ull
+#define CTI_1_NIC2_DBG_MAX_OFFSET 0x1000
+#define CTI_1_NIC2_DBG_SECTION 0x1000
+#define mmETF_1_NIC2_DBG_BASE 0x7FFED53000ull
+#define ETF_1_NIC2_DBG_MAX_OFFSET 0x1000
+#define ETF_1_NIC2_DBG_SECTION 0x1000
+#define mmSPMU_1_NIC2_DBG_BASE 0x7FFED54000ull
+#define SPMU_1_NIC2_DBG_MAX_OFFSET 0x1000
+#define SPMU_1_NIC2_DBG_SECTION 0x1000
+#define mmBMON_CTI_NIC2_DBG_BASE 0x7FFED55000ull
+#define BMON_CTI_NIC2_DBG_MAX_OFFSET 0x1000
+#define BMON_CTI_NIC2_DBG_SECTION 0x1000
+#define mmUSER_CTI_1_NIC2_DBG_BASE 0x7FFED56000ull
+#define USER_CTI_1_NIC2_DBG_MAX_OFFSET 0x1000
+#define USER_CTI_1_NIC2_DBG_SECTION 0x1000
+#define mmBMON0_NIC2_DBG_BASE 0x7FFED57000ull
+#define BMON0_NIC2_DBG_MAX_OFFSET 0x1000
+#define BMON0_NIC2_DBG_SECTION 0x1000
+#define mmBMON1_NIC2_DBG_BASE 0x7FFED58000ull
+#define BMON1_NIC2_DBG_MAX_OFFSET 0x1000
+#define BMON1_NIC2_DBG_SECTION 0x1000
+#define mmBMON2_NIC2_DBG_BASE 0x7FFED59000ull
+#define BMON2_NIC2_DBG_MAX_OFFSET 0x1000
+#define BMON2_NIC2_DBG_SECTION 0x1000
+#define mmBMON3_NIC2_DBG_BASE 0x7FFED5A000ull
+#define BMON3_NIC2_DBG_MAX_OFFSET 0x1000
+#define BMON3_NIC2_DBG_SECTION 0x1000
+#define mmBMON4_NIC2_DBG_BASE 0x7FFED5B000ull
+#define BMON4_NIC2_DBG_MAX_OFFSET 0x1000
+#define BMON4_NIC2_DBG_SECTION 0x6000
+#define mmFUNNEL_NIC2_DBG_BASE 0x7FFED61000ull
+#define FUNNEL_NIC2_DBG_MAX_OFFSET 0x1000
+#define FUNNEL_NIC2_DBG_SECTION 0x1F000
+#define mmNIC3_ROM_TABLE_BASE 0x7FFED80000ull
+#define NIC3_ROM_TABLE_MAX_OFFSET 0x1000
+#define NIC3_ROM_TABLE_SECTION 0x1000
+#define mmSTM_0_NIC3_DBG_BASE 0x7FFED81000ull
+#define STM_0_NIC3_DBG_MAX_OFFSET 0x21000
+#define STM_0_NIC3_DBG_SECTION 0x1000
+#define mmCTI_0_NIC3_DBG_BASE 0x7FFED82000ull
+#define CTI_0_NIC3_DBG_MAX_OFFSET 0x1000
+#define CTI_0_NIC3_DBG_SECTION 0x1000
+#define mmETF_0_NIC3_DBG_BASE 0x7FFED83000ull
+#define ETF_0_NIC3_DBG_MAX_OFFSET 0x1000
+#define ETF_0_NIC3_DBG_SECTION 0x1000
+#define mmSPMU_0_NIC3_DBG_BASE 0x7FFED84000ull
+#define SPMU_0_NIC3_DBG_MAX_OFFSET 0x1000
+#define SPMU_0_NIC3_DBG_SECTION 0x2000
+#define mmUSER_CTI_0_NIC3_DBG_BASE 0x7FFED86000ull
+#define USER_CTI_0_NIC3_DBG_MAX_OFFSET 0x1000
+#define USER_CTI_0_NIC3_DBG_SECTION 0xB000
+#define mmSTM_1_NIC3_DBG_BASE 0x7FFED91000ull
+#define STM_1_NIC3_DBG_MAX_OFFSET 0x1000
+#define STM_1_NIC3_DBG_SECTION 0x1000
+#define mmCTI_1_NIC3_DBG_BASE 0x7FFED92000ull
+#define CTI_1_NIC3_DBG_MAX_OFFSET 0x1000
+#define CTI_1_NIC3_DBG_SECTION 0x1000
+#define mmETF_1_NIC3_DBG_BASE 0x7FFED93000ull
+#define ETF_1_NIC3_DBG_MAX_OFFSET 0x1000
+#define ETF_1_NIC3_DBG_SECTION 0x1000
+#define mmSPMU_1_NIC3_DBG_BASE 0x7FFED94000ull
+#define SPMU_1_NIC3_DBG_MAX_OFFSET 0x1000
+#define SPMU_1_NIC3_DBG_SECTION 0x1000
+#define mmBMON_CTI_NIC3_DBG_BASE 0x7FFED95000ull
+#define BMON_CTI_NIC3_DBG_MAX_OFFSET 0x1000
+#define BMON_CTI_NIC3_DBG_SECTION 0x1000
+#define mmUSER_CTI_1_NIC3_DBG_BASE 0x7FFED96000ull
+#define USER_CTI_1_NIC3_DBG_MAX_OFFSET 0x1000
+#define USER_CTI_1_NIC3_DBG_SECTION 0x1000
+#define mmBMON0_NIC3_DBG_BASE 0x7FFED97000ull
+#define BMON0_NIC3_DBG_MAX_OFFSET 0x1000
+#define BMON0_NIC3_DBG_SECTION 0x1000
+#define mmBMON1_NIC3_DBG_BASE 0x7FFED98000ull
+#define BMON1_NIC3_DBG_MAX_OFFSET 0x1000
+#define BMON1_NIC3_DBG_SECTION 0x1000
+#define mmBMON2_NIC3_DBG_BASE 0x7FFED99000ull
+#define BMON2_NIC3_DBG_MAX_OFFSET 0x1000
+#define BMON2_NIC3_DBG_SECTION 0x1000
+#define mmBMON3_NIC3_DBG_BASE 0x7FFED9A000ull
+#define BMON3_NIC3_DBG_MAX_OFFSET 0x1000
+#define BMON3_NIC3_DBG_SECTION 0x1000
+#define mmBMON4_NIC3_DBG_BASE 0x7FFED9B000ull
+#define BMON4_NIC3_DBG_MAX_OFFSET 0x1000
+#define BMON4_NIC3_DBG_SECTION 0x6000
+#define mmFUNNEL_NIC3_DBG_BASE 0x7FFEDA1000ull
+#define FUNNEL_NIC3_DBG_MAX_OFFSET 0x1000
+#define FUNNEL_NIC3_DBG_SECTION 0x1F000
+#define mmNIC4_ROM_TABLE_BASE 0x7FFEDC0000ull
+#define NIC4_ROM_TABLE_MAX_OFFSET 0x1000
+#define NIC4_ROM_TABLE_SECTION 0x1000
+#define mmSTM_0_NIC4_DBG_BASE 0x7FFEDC1000ull
+#define STM_0_NIC4_DBG_MAX_OFFSET 0x21000
+#define STM_0_NIC4_DBG_SECTION 0x1000
+#define mmCTI_0_NIC4_DBG_BASE 0x7FFEDC2000ull
+#define CTI_0_NIC4_DBG_MAX_OFFSET 0x1000
+#define CTI_0_NIC4_DBG_SECTION 0x1000
+#define mmETF_0_NIC4_DBG_BASE 0x7FFEDC3000ull
+#define ETF_0_NIC4_DBG_MAX_OFFSET 0x1000
+#define ETF_0_NIC4_DBG_SECTION 0x1000
+#define mmSPMU_0_NIC4_DBG_BASE 0x7FFEDC4000ull
+#define SPMU_0_NIC4_DBG_MAX_OFFSET 0x1000
+#define SPMU_0_NIC4_DBG_SECTION 0x2000
+#define mmUSER_CTI_0_NIC4_DBG_BASE 0x7FFEDC6000ull
+#define USER_CTI_0_NIC4_DBG_MAX_OFFSET 0x1000
+#define USER_CTI_0_NIC4_DBG_SECTION 0xB000
+#define mmSTM_1_NIC4_DBG_BASE 0x7FFEDD1000ull
+#define STM_1_NIC4_DBG_MAX_OFFSET 0x1000
+#define STM_1_NIC4_DBG_SECTION 0x1000
+#define mmCTI_1_NIC4_DBG_BASE 0x7FFEDD2000ull
+#define CTI_1_NIC4_DBG_MAX_OFFSET 0x1000
+#define CTI_1_NIC4_DBG_SECTION 0x1000
+#define mmETF_1_NIC4_DBG_BASE 0x7FFEDD3000ull
+#define ETF_1_NIC4_DBG_MAX_OFFSET 0x1000
+#define ETF_1_NIC4_DBG_SECTION 0x1000
+#define mmSPMU_1_NIC4_DBG_BASE 0x7FFEDD4000ull
+#define SPMU_1_NIC4_DBG_MAX_OFFSET 0x1000
+#define SPMU_1_NIC4_DBG_SECTION 0x1000
+#define mmBMON_CTI_NIC4_DBG_BASE 0x7FFEDD5000ull
+#define BMON_CTI_NIC4_DBG_MAX_OFFSET 0x1000
+#define BMON_CTI_NIC4_DBG_SECTION 0x1000
+#define mmUSER_CTI_1_NIC4_DBG_BASE 0x7FFEDD6000ull
+#define USER_CTI_1_NIC4_DBG_MAX_OFFSET 0x1000
+#define USER_CTI_1_NIC4_DBG_SECTION 0x1000
+#define mmBMON0_NIC4_DBG_BASE 0x7FFEDD7000ull
+#define BMON0_NIC4_DBG_MAX_OFFSET 0x1000
+#define BMON0_NIC4_DBG_SECTION 0x1000
+#define mmBMON1_NIC4_DBG_BASE 0x7FFEDD8000ull
+#define BMON1_NIC4_DBG_MAX_OFFSET 0x1000
+#define BMON1_NIC4_DBG_SECTION 0x1000
+#define mmBMON2_NIC4_DBG_BASE 0x7FFEDD9000ull
+#define BMON2_NIC4_DBG_MAX_OFFSET 0x1000
+#define BMON2_NIC4_DBG_SECTION 0x1000
+#define mmBMON3_NIC4_DBG_BASE 0x7FFEDDA000ull
+#define BMON3_NIC4_DBG_MAX_OFFSET 0x1000
+#define BMON3_NIC4_DBG_SECTION 0x1000
+#define mmBMON4_NIC4_DBG_BASE 0x7FFEDDB000ull
+#define BMON4_NIC4_DBG_MAX_OFFSET 0x1000
+#define BMON4_NIC4_DBG_SECTION 0x6000
+#define mmFUNNEL_NIC4_DBG_BASE 0x7FFEDE1000ull
+#define FUNNEL_NIC4_DBG_MAX_OFFSET 0x1000
+#define FUNNEL_NIC4_DBG_SECTION 0x21F000
+#define mmTPC0_ROM_TABLE_BASE 0x7FFF000000ull
+#define TPC0_ROM_TABLE_MAX_OFFSET 0x1000
+#define TPC0_ROM_TABLE_SECTION 0x1000
+#define mmTPC0_EML_SPMU_BASE 0x7FFF001000ull
+#define TPC0_EML_SPMU_MAX_OFFSET 0x1000
+#define TPC0_EML_SPMU_SECTION 0x1000
+#define mmTPC0_EML_ETF_BASE 0x7FFF002000ull
+#define TPC0_EML_ETF_MAX_OFFSET 0x1000
+#define TPC0_EML_ETF_SECTION 0x1000
+#define mmTPC0_EML_STM_BASE 0x7FFF003000ull
+#define TPC0_EML_STM_MAX_OFFSET 0x1000
+#define TPC0_EML_STM_SECTION 0x2000
+#define mmTPC0_EML_CTI_BASE 0x7FFF005000ull
+#define TPC0_EML_CTI_MAX_OFFSET 0x1000
+#define TPC0_EML_CTI_SECTION 0x1000
+#define mmTPC0_EML_FUNNEL_BASE 0x7FFF006000ull
+#define TPC0_EML_FUNNEL_MAX_OFFSET 0x1000
+#define TPC0_EML_FUNNEL_SECTION 0x1000
+#define mmTPC0_EML_BUSMON_0_BASE 0x7FFF007000ull
+#define TPC0_EML_BUSMON_0_MAX_OFFSET 0x1000
+#define TPC0_EML_BUSMON_0_SECTION 0x1000
+#define mmTPC0_EML_BUSMON_1_BASE 0x7FFF008000ull
+#define TPC0_EML_BUSMON_1_MAX_OFFSET 0x1000
+#define TPC0_EML_BUSMON_1_SECTION 0x1000
+#define mmTPC0_EML_BUSMON_2_BASE 0x7FFF009000ull
+#define TPC0_EML_BUSMON_2_MAX_OFFSET 0x1000
+#define TPC0_EML_BUSMON_2_SECTION 0x1000
+#define mmTPC0_EML_BUSMON_3_BASE 0x7FFF00A000ull
+#define TPC0_EML_BUSMON_3_MAX_OFFSET 0x1000
+#define TPC0_EML_BUSMON_3_SECTION 0x36000
+#define mmTPC0_EML_CFG_BASE 0x7FFF040000ull
+#define TPC0_EML_CFG_MAX_OFFSET 0x3380
+#define TPC0_EML_CFG_SECTION 0x1000
+#define mmTPC0_EML_TPC_CFG_BASE 0x7FFF041000ull
+#define TPC0_EML_TPC_CFG_MAX_OFFSET 0xE400
+#define TPC0_EML_TPC_CFG_SECTION 0x4000
+#define mmKERNEL_TENSOR_0_TPC0_EML_TPC_CFG_BASE 0x7FFF041400ull
+#define KERNEL_TENSOR_0_TPC0_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_0_TPC0_EML_TPC_CFG_SECTION 0x3800
+#define mmKERNEL_TENSOR_1_TPC0_EML_TPC_CFG_BASE 0x7FFF041438ull
+#define KERNEL_TENSOR_1_TPC0_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_1_TPC0_EML_TPC_CFG_SECTION 0x3800
+#define mmKERNEL_TENSOR_2_TPC0_EML_TPC_CFG_BASE 0x7FFF041470ull
+#define KERNEL_TENSOR_2_TPC0_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_2_TPC0_EML_TPC_CFG_SECTION 0x3800
+#define mmKERNEL_TENSOR_3_TPC0_EML_TPC_CFG_BASE 0x7FFF0414A8ull
+#define KERNEL_TENSOR_3_TPC0_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_3_TPC0_EML_TPC_CFG_SECTION 0x3800
+#define mmKERNEL_TENSOR_4_TPC0_EML_TPC_CFG_BASE 0x7FFF0414E0ull
+#define KERNEL_TENSOR_4_TPC0_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_4_TPC0_EML_TPC_CFG_SECTION 0x3800
+#define mmKERNEL_TENSOR_5_TPC0_EML_TPC_CFG_BASE 0x7FFF041518ull
+#define KERNEL_TENSOR_5_TPC0_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_5_TPC0_EML_TPC_CFG_SECTION 0x3800
+#define mmKERNEL_TENSOR_6_TPC0_EML_TPC_CFG_BASE 0x7FFF041550ull
+#define KERNEL_TENSOR_6_TPC0_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_6_TPC0_EML_TPC_CFG_SECTION 0x3800
+#define mmKERNEL_TENSOR_7_TPC0_EML_TPC_CFG_BASE 0x7FFF041588ull
+#define KERNEL_TENSOR_7_TPC0_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_7_TPC0_EML_TPC_CFG_SECTION 0x3800
+#define mmKERNEL_TENSOR_8_TPC0_EML_TPC_CFG_BASE 0x7FFF0415C0ull
+#define KERNEL_TENSOR_8_TPC0_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_8_TPC0_EML_TPC_CFG_SECTION 0x3800
+#define mmKERNEL_TENSOR_9_TPC0_EML_TPC_CFG_BASE 0x7FFF0415F8ull
+#define KERNEL_TENSOR_9_TPC0_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_9_TPC0_EML_TPC_CFG_SECTION 0x3800
+#define mmKERNEL_TENSOR_10_TPC0_EML_TPC_CFG_BASE 0x7FFF041630ull
+#define KERNEL_TENSOR_10_TPC0_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_10_TPC0_EML_TPC_CFG_SECTION 0x3800
+#define mmKERNEL_TENSOR_11_TPC0_EML_TPC_CFG_BASE 0x7FFF041668ull
+#define KERNEL_TENSOR_11_TPC0_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_11_TPC0_EML_TPC_CFG_SECTION 0x3800
+#define mmKERNEL_TENSOR_12_TPC0_EML_TPC_CFG_BASE 0x7FFF0416A0ull
+#define KERNEL_TENSOR_12_TPC0_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_12_TPC0_EML_TPC_CFG_SECTION 0x3800
+#define mmKERNEL_TENSOR_13_TPC0_EML_TPC_CFG_BASE 0x7FFF0416D8ull
+#define KERNEL_TENSOR_13_TPC0_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_13_TPC0_EML_TPC_CFG_SECTION 0x3800
+#define mmKERNEL_TENSOR_14_TPC0_EML_TPC_CFG_BASE 0x7FFF041710ull
+#define KERNEL_TENSOR_14_TPC0_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_14_TPC0_EML_TPC_CFG_SECTION 0x3800
+#define mmKERNEL_TENSOR_15_TPC0_EML_TPC_CFG_BASE 0x7FFF041748ull
+#define KERNEL_TENSOR_15_TPC0_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_15_TPC0_EML_TPC_CFG_SECTION 0x3800
+#define mmKERNEL_SYNC_OBJECT_TPC0_EML_TPC_CFG_BASE 0x7FFF041780ull
+#define KERNEL_SYNC_OBJECT_TPC0_EML_TPC_CFG_MAX_OFFSET 0x8000
+#define KERNEL_SYNC_OBJECT_TPC0_EML_TPC_CFG_SECTION 0x8000
+#define mmKERNEL_TPC0_EML_TPC_CFG_BASE 0x7FFF041788ull
+#define KERNEL_TPC0_EML_TPC_CFG_MAX_OFFSET 0xB800
+#define KERNEL_TPC0_EML_TPC_CFG_SECTION 0x2780
+#define mmQM_TENSOR_0_TPC0_EML_TPC_CFG_BASE 0x7FFF041A00ull
+#define QM_TENSOR_0_TPC0_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define QM_TENSOR_0_TPC0_EML_TPC_CFG_SECTION 0x3800
+#define mmQM_TENSOR_1_TPC0_EML_TPC_CFG_BASE 0x7FFF041A38ull
+#define QM_TENSOR_1_TPC0_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define QM_TENSOR_1_TPC0_EML_TPC_CFG_SECTION 0x3800
+#define mmQM_TENSOR_2_TPC0_EML_TPC_CFG_BASE 0x7FFF041A70ull
+#define QM_TENSOR_2_TPC0_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define QM_TENSOR_2_TPC0_EML_TPC_CFG_SECTION 0x3800
+#define mmQM_TENSOR_3_TPC0_EML_TPC_CFG_BASE 0x7FFF041AA8ull
+#define QM_TENSOR_3_TPC0_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define QM_TENSOR_3_TPC0_EML_TPC_CFG_SECTION 0x3800
+#define mmQM_TENSOR_4_TPC0_EML_TPC_CFG_BASE 0x7FFF041AE0ull
+#define QM_TENSOR_4_TPC0_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define QM_TENSOR_4_TPC0_EML_TPC_CFG_SECTION 0x3800
+#define mmQM_TENSOR_5_TPC0_EML_TPC_CFG_BASE 0x7FFF041B18ull
+#define QM_TENSOR_5_TPC0_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define QM_TENSOR_5_TPC0_EML_TPC_CFG_SECTION 0x3800
+#define mmQM_TENSOR_6_TPC0_EML_TPC_CFG_BASE 0x7FFF041B50ull
+#define QM_TENSOR_6_TPC0_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define QM_TENSOR_6_TPC0_EML_TPC_CFG_SECTION 0x3800
+#define mmQM_TENSOR_7_TPC0_EML_TPC_CFG_BASE 0x7FFF041B88ull
+#define QM_TENSOR_7_TPC0_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define QM_TENSOR_7_TPC0_EML_TPC_CFG_SECTION 0x3800
+#define mmQM_TENSOR_8_TPC0_EML_TPC_CFG_BASE 0x7FFF041BC0ull
+#define QM_TENSOR_8_TPC0_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define QM_TENSOR_8_TPC0_EML_TPC_CFG_SECTION 0x3800
+#define mmQM_TENSOR_9_TPC0_EML_TPC_CFG_BASE 0x7FFF041BF8ull
+#define QM_TENSOR_9_TPC0_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define QM_TENSOR_9_TPC0_EML_TPC_CFG_SECTION 0x3800
+#define mmQM_TENSOR_10_TPC0_EML_TPC_CFG_BASE 0x7FFF041C30ull
+#define QM_TENSOR_10_TPC0_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define QM_TENSOR_10_TPC0_EML_TPC_CFG_SECTION 0x3800
+#define mmQM_TENSOR_11_TPC0_EML_TPC_CFG_BASE 0x7FFF041C68ull
+#define QM_TENSOR_11_TPC0_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define QM_TENSOR_11_TPC0_EML_TPC_CFG_SECTION 0x3800
+#define mmQM_TENSOR_12_TPC0_EML_TPC_CFG_BASE 0x7FFF041CA0ull
+#define QM_TENSOR_12_TPC0_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define QM_TENSOR_12_TPC0_EML_TPC_CFG_SECTION 0x3800
+#define mmQM_TENSOR_13_TPC0_EML_TPC_CFG_BASE 0x7FFF041CD8ull
+#define QM_TENSOR_13_TPC0_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define QM_TENSOR_13_TPC0_EML_TPC_CFG_SECTION 0x3800
+#define mmQM_TENSOR_14_TPC0_EML_TPC_CFG_BASE 0x7FFF041D10ull
+#define QM_TENSOR_14_TPC0_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define QM_TENSOR_14_TPC0_EML_TPC_CFG_SECTION 0x3800
+#define mmQM_TENSOR_15_TPC0_EML_TPC_CFG_BASE 0x7FFF041D48ull
+#define QM_TENSOR_15_TPC0_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define QM_TENSOR_15_TPC0_EML_TPC_CFG_SECTION 0x3800
+#define mmQM_SYNC_OBJECT_TPC0_EML_TPC_CFG_BASE 0x7FFF041D80ull
+#define QM_SYNC_OBJECT_TPC0_EML_TPC_CFG_MAX_OFFSET 0x8000
+#define QM_SYNC_OBJECT_TPC0_EML_TPC_CFG_SECTION 0x8000
+#define mmQM_TPC0_EML_TPC_CFG_BASE 0x7FFF041D88ull
+#define QM_TPC0_EML_TPC_CFG_MAX_OFFSET 0xB800
+#define QM_TPC0_EML_TPC_CFG_SECTION 0x2780
+#define mmTPC0_EML_TPC_QM_BASE 0x7FFF042000ull
+#define TPC0_EML_TPC_QM_MAX_OFFSET 0xD040
+#define TPC0_EML_TPC_QM_SECTION 0x1BD000
+#define mmTPC0_EML_CS_BASE 0x7FFF1FF000ull
+#define TPC0_EML_CS_MAX_OFFSET 0x1000
+#define TPC0_EML_CS_SECTION 0x1000
+#define mmTPC1_ROM_TABLE_BASE 0x7FFF200000ull
+#define TPC1_ROM_TABLE_MAX_OFFSET 0x1000
+#define TPC1_ROM_TABLE_SECTION 0x1000
+#define mmTPC1_EML_SPMU_BASE 0x7FFF201000ull
+#define TPC1_EML_SPMU_MAX_OFFSET 0x1000
+#define TPC1_EML_SPMU_SECTION 0x1000
+#define mmTPC1_EML_ETF_BASE 0x7FFF202000ull
+#define TPC1_EML_ETF_MAX_OFFSET 0x1000
+#define TPC1_EML_ETF_SECTION 0x1000
+#define mmTPC1_EML_STM_BASE 0x7FFF203000ull
+#define TPC1_EML_STM_MAX_OFFSET 0x1000
+#define TPC1_EML_STM_SECTION 0x2000
+#define mmTPC1_EML_CTI_BASE 0x7FFF205000ull
+#define TPC1_EML_CTI_MAX_OFFSET 0x1000
+#define TPC1_EML_CTI_SECTION 0x1000
+#define mmTPC1_EML_FUNNEL_BASE 0x7FFF206000ull
+#define TPC1_EML_FUNNEL_MAX_OFFSET 0x1000
+#define TPC1_EML_FUNNEL_SECTION 0x1000
+#define mmTPC1_EML_BUSMON_0_BASE 0x7FFF207000ull
+#define TPC1_EML_BUSMON_0_MAX_OFFSET 0x1000
+#define TPC1_EML_BUSMON_0_SECTION 0x1000
+#define mmTPC1_EML_BUSMON_1_BASE 0x7FFF208000ull
+#define TPC1_EML_BUSMON_1_MAX_OFFSET 0x1000
+#define TPC1_EML_BUSMON_1_SECTION 0x1000
+#define mmTPC1_EML_BUSMON_2_BASE 0x7FFF209000ull
+#define TPC1_EML_BUSMON_2_MAX_OFFSET 0x1000
+#define TPC1_EML_BUSMON_2_SECTION 0x1000
+#define mmTPC1_EML_BUSMON_3_BASE 0x7FFF20A000ull
+#define TPC1_EML_BUSMON_3_MAX_OFFSET 0x1000
+#define TPC1_EML_BUSMON_3_SECTION 0x36000
+#define mmTPC1_EML_CFG_BASE 0x7FFF240000ull
+#define TPC1_EML_CFG_MAX_OFFSET 0x3380
+#define TPC1_EML_CFG_SECTION 0x1000
+#define mmTPC1_EML_TPC_CFG_BASE 0x7FFF241000ull
+#define TPC1_EML_TPC_CFG_MAX_OFFSET 0xE400
+#define TPC1_EML_TPC_CFG_SECTION 0x4000
+#define mmKERNEL_TENSOR_0_TPC1_EML_TPC_CFG_BASE 0x7FFF241400ull
+#define KERNEL_TENSOR_0_TPC1_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_0_TPC1_EML_TPC_CFG_SECTION 0x3800
+#define mmKERNEL_TENSOR_1_TPC1_EML_TPC_CFG_BASE 0x7FFF241438ull
+#define KERNEL_TENSOR_1_TPC1_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_1_TPC1_EML_TPC_CFG_SECTION 0x3800
+#define mmKERNEL_TENSOR_2_TPC1_EML_TPC_CFG_BASE 0x7FFF241470ull
+#define KERNEL_TENSOR_2_TPC1_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_2_TPC1_EML_TPC_CFG_SECTION 0x3800
+#define mmKERNEL_TENSOR_3_TPC1_EML_TPC_CFG_BASE 0x7FFF2414A8ull
+#define KERNEL_TENSOR_3_TPC1_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_3_TPC1_EML_TPC_CFG_SECTION 0x3800
+#define mmKERNEL_TENSOR_4_TPC1_EML_TPC_CFG_BASE 0x7FFF2414E0ull
+#define KERNEL_TENSOR_4_TPC1_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_4_TPC1_EML_TPC_CFG_SECTION 0x3800
+#define mmKERNEL_TENSOR_5_TPC1_EML_TPC_CFG_BASE 0x7FFF241518ull
+#define KERNEL_TENSOR_5_TPC1_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_5_TPC1_EML_TPC_CFG_SECTION 0x3800
+#define mmKERNEL_TENSOR_6_TPC1_EML_TPC_CFG_BASE 0x7FFF241550ull
+#define KERNEL_TENSOR_6_TPC1_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_6_TPC1_EML_TPC_CFG_SECTION 0x3800
+#define mmKERNEL_TENSOR_7_TPC1_EML_TPC_CFG_BASE 0x7FFF241588ull
+#define KERNEL_TENSOR_7_TPC1_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_7_TPC1_EML_TPC_CFG_SECTION 0x3800
+#define mmKERNEL_TENSOR_8_TPC1_EML_TPC_CFG_BASE 0x7FFF2415C0ull
+#define KERNEL_TENSOR_8_TPC1_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_8_TPC1_EML_TPC_CFG_SECTION 0x3800
+#define mmKERNEL_TENSOR_9_TPC1_EML_TPC_CFG_BASE 0x7FFF2415F8ull
+#define KERNEL_TENSOR_9_TPC1_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_9_TPC1_EML_TPC_CFG_SECTION 0x3800
+#define mmKERNEL_TENSOR_10_TPC1_EML_TPC_CFG_BASE 0x7FFF241630ull
+#define KERNEL_TENSOR_10_TPC1_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_10_TPC1_EML_TPC_CFG_SECTION 0x3800
+#define mmKERNEL_TENSOR_11_TPC1_EML_TPC_CFG_BASE 0x7FFF241668ull
+#define KERNEL_TENSOR_11_TPC1_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_11_TPC1_EML_TPC_CFG_SECTION 0x3800
+#define mmKERNEL_TENSOR_12_TPC1_EML_TPC_CFG_BASE 0x7FFF2416A0ull
+#define KERNEL_TENSOR_12_TPC1_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_12_TPC1_EML_TPC_CFG_SECTION 0x3800
+#define mmKERNEL_TENSOR_13_TPC1_EML_TPC_CFG_BASE 0x7FFF2416D8ull
+#define KERNEL_TENSOR_13_TPC1_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_13_TPC1_EML_TPC_CFG_SECTION 0x3800
+#define mmKERNEL_TENSOR_14_TPC1_EML_TPC_CFG_BASE 0x7FFF241710ull
+#define KERNEL_TENSOR_14_TPC1_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_14_TPC1_EML_TPC_CFG_SECTION 0x3800
+#define mmKERNEL_TENSOR_15_TPC1_EML_TPC_CFG_BASE 0x7FFF241748ull
+#define KERNEL_TENSOR_15_TPC1_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_15_TPC1_EML_TPC_CFG_SECTION 0x3800
+#define mmKERNEL_SYNC_OBJECT_TPC1_EML_TPC_CFG_BASE 0x7FFF241780ull
+#define KERNEL_SYNC_OBJECT_TPC1_EML_TPC_CFG_MAX_OFFSET 0x8000
+#define KERNEL_SYNC_OBJECT_TPC1_EML_TPC_CFG_SECTION 0x8000
+#define mmKERNEL_TPC1_EML_TPC_CFG_BASE 0x7FFF241788ull
+#define KERNEL_TPC1_EML_TPC_CFG_MAX_OFFSET 0xB800
+#define KERNEL_TPC1_EML_TPC_CFG_SECTION 0x2780
+#define mmQM_TENSOR_0_TPC1_EML_TPC_CFG_BASE 0x7FFF241A00ull
+#define QM_TENSOR_0_TPC1_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define QM_TENSOR_0_TPC1_EML_TPC_CFG_SECTION 0x3800
+#define mmQM_TENSOR_1_TPC1_EML_TPC_CFG_BASE 0x7FFF241A38ull
+#define QM_TENSOR_1_TPC1_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define QM_TENSOR_1_TPC1_EML_TPC_CFG_SECTION 0x3800
+#define mmQM_TENSOR_2_TPC1_EML_TPC_CFG_BASE 0x7FFF241A70ull
+#define QM_TENSOR_2_TPC1_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define QM_TENSOR_2_TPC1_EML_TPC_CFG_SECTION 0x3800
+#define mmQM_TENSOR_3_TPC1_EML_TPC_CFG_BASE 0x7FFF241AA8ull
+#define QM_TENSOR_3_TPC1_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define QM_TENSOR_3_TPC1_EML_TPC_CFG_SECTION 0x3800
+#define mmQM_TENSOR_4_TPC1_EML_TPC_CFG_BASE 0x7FFF241AE0ull
+#define QM_TENSOR_4_TPC1_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define QM_TENSOR_4_TPC1_EML_TPC_CFG_SECTION 0x3800
+#define mmQM_TENSOR_5_TPC1_EML_TPC_CFG_BASE 0x7FFF241B18ull
+#define QM_TENSOR_5_TPC1_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define QM_TENSOR_5_TPC1_EML_TPC_CFG_SECTION 0x3800
+#define mmQM_TENSOR_6_TPC1_EML_TPC_CFG_BASE 0x7FFF241B50ull
+#define QM_TENSOR_6_TPC1_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define QM_TENSOR_6_TPC1_EML_TPC_CFG_SECTION 0x3800
+#define mmQM_TENSOR_7_TPC1_EML_TPC_CFG_BASE 0x7FFF241B88ull
+#define QM_TENSOR_7_TPC1_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define QM_TENSOR_7_TPC1_EML_TPC_CFG_SECTION 0x3800
+#define mmQM_TENSOR_8_TPC1_EML_TPC_CFG_BASE 0x7FFF241BC0ull
+#define QM_TENSOR_8_TPC1_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define QM_TENSOR_8_TPC1_EML_TPC_CFG_SECTION 0x3800
+#define mmQM_TENSOR_9_TPC1_EML_TPC_CFG_BASE 0x7FFF241BF8ull
+#define QM_TENSOR_9_TPC1_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define QM_TENSOR_9_TPC1_EML_TPC_CFG_SECTION 0x3800
+#define mmQM_TENSOR_10_TPC1_EML_TPC_CFG_BASE 0x7FFF241C30ull
+#define QM_TENSOR_10_TPC1_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define QM_TENSOR_10_TPC1_EML_TPC_CFG_SECTION 0x3800
+#define mmQM_TENSOR_11_TPC1_EML_TPC_CFG_BASE 0x7FFF241C68ull
+#define QM_TENSOR_11_TPC1_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define QM_TENSOR_11_TPC1_EML_TPC_CFG_SECTION 0x3800
+#define mmQM_TENSOR_12_TPC1_EML_TPC_CFG_BASE 0x7FFF241CA0ull
+#define QM_TENSOR_12_TPC1_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define QM_TENSOR_12_TPC1_EML_TPC_CFG_SECTION 0x3800
+#define mmQM_TENSOR_13_TPC1_EML_TPC_CFG_BASE 0x7FFF241CD8ull
+#define QM_TENSOR_13_TPC1_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define QM_TENSOR_13_TPC1_EML_TPC_CFG_SECTION 0x3800
+#define mmQM_TENSOR_14_TPC1_EML_TPC_CFG_BASE 0x7FFF241D10ull
+#define QM_TENSOR_14_TPC1_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define QM_TENSOR_14_TPC1_EML_TPC_CFG_SECTION 0x3800
+#define mmQM_TENSOR_15_TPC1_EML_TPC_CFG_BASE 0x7FFF241D48ull
+#define QM_TENSOR_15_TPC1_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define QM_TENSOR_15_TPC1_EML_TPC_CFG_SECTION 0x3800
+#define mmQM_SYNC_OBJECT_TPC1_EML_TPC_CFG_BASE 0x7FFF241D80ull
+#define QM_SYNC_OBJECT_TPC1_EML_TPC_CFG_MAX_OFFSET 0x8000
+#define QM_SYNC_OBJECT_TPC1_EML_TPC_CFG_SECTION 0x8000
+#define mmQM_TPC1_EML_TPC_CFG_BASE 0x7FFF241D88ull
+#define QM_TPC1_EML_TPC_CFG_MAX_OFFSET 0xB800
+#define QM_TPC1_EML_TPC_CFG_SECTION 0x2780
+#define mmTPC1_EML_TPC_QM_BASE 0x7FFF242000ull
+#define TPC1_EML_TPC_QM_MAX_OFFSET 0xD040
+#define TPC1_EML_TPC_QM_SECTION 0x1BD000
+#define mmTPC1_EML_CS_BASE 0x7FFF3FF000ull
+#define TPC1_EML_CS_MAX_OFFSET 0x1000
+#define TPC1_EML_CS_SECTION 0x1000
+#define mmTPC2_ROM_TABLE_BASE 0x7FFF400000ull
+#define TPC2_ROM_TABLE_MAX_OFFSET 0x1000
+#define TPC2_ROM_TABLE_SECTION 0x1000
+#define mmTPC2_EML_SPMU_BASE 0x7FFF401000ull
+#define TPC2_EML_SPMU_MAX_OFFSET 0x1000
+#define TPC2_EML_SPMU_SECTION 0x1000
+#define mmTPC2_EML_ETF_BASE 0x7FFF402000ull
+#define TPC2_EML_ETF_MAX_OFFSET 0x1000
+#define TPC2_EML_ETF_SECTION 0x1000
+#define mmTPC2_EML_STM_BASE 0x7FFF403000ull
+#define TPC2_EML_STM_MAX_OFFSET 0x1000
+#define TPC2_EML_STM_SECTION 0x2000
+#define mmTPC2_EML_CTI_BASE 0x7FFF405000ull
+#define TPC2_EML_CTI_MAX_OFFSET 0x1000
+#define TPC2_EML_CTI_SECTION 0x1000
+#define mmTPC2_EML_FUNNEL_BASE 0x7FFF406000ull
+#define TPC2_EML_FUNNEL_MAX_OFFSET 0x1000
+#define TPC2_EML_FUNNEL_SECTION 0x1000
+#define mmTPC2_EML_BUSMON_0_BASE 0x7FFF407000ull
+#define TPC2_EML_BUSMON_0_MAX_OFFSET 0x1000
+#define TPC2_EML_BUSMON_0_SECTION 0x1000
+#define mmTPC2_EML_BUSMON_1_BASE 0x7FFF408000ull
+#define TPC2_EML_BUSMON_1_MAX_OFFSET 0x1000
+#define TPC2_EML_BUSMON_1_SECTION 0x1000
+#define mmTPC2_EML_BUSMON_2_BASE 0x7FFF409000ull
+#define TPC2_EML_BUSMON_2_MAX_OFFSET 0x1000
+#define TPC2_EML_BUSMON_2_SECTION 0x1000
+#define mmTPC2_EML_BUSMON_3_BASE 0x7FFF40A000ull
+#define TPC2_EML_BUSMON_3_MAX_OFFSET 0x1000
+#define TPC2_EML_BUSMON_3_SECTION 0x36000
+#define mmTPC2_EML_CFG_BASE 0x7FFF440000ull
+#define TPC2_EML_CFG_MAX_OFFSET 0x3380
+#define TPC2_EML_CFG_SECTION 0x1000
+#define mmTPC2_EML_TPC_CFG_BASE 0x7FFF441000ull
+#define TPC2_EML_TPC_CFG_MAX_OFFSET 0xE400
+#define TPC2_EML_TPC_CFG_SECTION 0x4000
+#define mmKERNEL_TENSOR_0_TPC2_EML_TPC_CFG_BASE 0x7FFF441400ull
+#define KERNEL_TENSOR_0_TPC2_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_0_TPC2_EML_TPC_CFG_SECTION 0x3800
+#define mmKERNEL_TENSOR_1_TPC2_EML_TPC_CFG_BASE 0x7FFF441438ull
+#define KERNEL_TENSOR_1_TPC2_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_1_TPC2_EML_TPC_CFG_SECTION 0x3800
+#define mmKERNEL_TENSOR_2_TPC2_EML_TPC_CFG_BASE 0x7FFF441470ull
+#define KERNEL_TENSOR_2_TPC2_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_2_TPC2_EML_TPC_CFG_SECTION 0x3800
+#define mmKERNEL_TENSOR_3_TPC2_EML_TPC_CFG_BASE 0x7FFF4414A8ull
+#define KERNEL_TENSOR_3_TPC2_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_3_TPC2_EML_TPC_CFG_SECTION 0x3800
+#define mmKERNEL_TENSOR_4_TPC2_EML_TPC_CFG_BASE 0x7FFF4414E0ull
+#define KERNEL_TENSOR_4_TPC2_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_4_TPC2_EML_TPC_CFG_SECTION 0x3800
+#define mmKERNEL_TENSOR_5_TPC2_EML_TPC_CFG_BASE 0x7FFF441518ull
+#define KERNEL_TENSOR_5_TPC2_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_5_TPC2_EML_TPC_CFG_SECTION 0x3800
+#define mmKERNEL_TENSOR_6_TPC2_EML_TPC_CFG_BASE 0x7FFF441550ull
+#define KERNEL_TENSOR_6_TPC2_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_6_TPC2_EML_TPC_CFG_SECTION 0x3800
+#define mmKERNEL_TENSOR_7_TPC2_EML_TPC_CFG_BASE 0x7FFF441588ull
+#define KERNEL_TENSOR_7_TPC2_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_7_TPC2_EML_TPC_CFG_SECTION 0x3800
+#define mmKERNEL_TENSOR_8_TPC2_EML_TPC_CFG_BASE 0x7FFF4415C0ull
+#define KERNEL_TENSOR_8_TPC2_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_8_TPC2_EML_TPC_CFG_SECTION 0x3800
+#define mmKERNEL_TENSOR_9_TPC2_EML_TPC_CFG_BASE 0x7FFF4415F8ull
+#define KERNEL_TENSOR_9_TPC2_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_9_TPC2_EML_TPC_CFG_SECTION 0x3800
+#define mmKERNEL_TENSOR_10_TPC2_EML_TPC_CFG_BASE 0x7FFF441630ull
+#define KERNEL_TENSOR_10_TPC2_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_10_TPC2_EML_TPC_CFG_SECTION 0x3800
+#define mmKERNEL_TENSOR_11_TPC2_EML_TPC_CFG_BASE 0x7FFF441668ull
+#define KERNEL_TENSOR_11_TPC2_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_11_TPC2_EML_TPC_CFG_SECTION 0x3800
+#define mmKERNEL_TENSOR_12_TPC2_EML_TPC_CFG_BASE 0x7FFF4416A0ull
+#define KERNEL_TENSOR_12_TPC2_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_12_TPC2_EML_TPC_CFG_SECTION 0x3800
+#define mmKERNEL_TENSOR_13_TPC2_EML_TPC_CFG_BASE 0x7FFF4416D8ull
+#define KERNEL_TENSOR_13_TPC2_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_13_TPC2_EML_TPC_CFG_SECTION 0x3800
+#define mmKERNEL_TENSOR_14_TPC2_EML_TPC_CFG_BASE 0x7FFF441710ull
+#define KERNEL_TENSOR_14_TPC2_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_14_TPC2_EML_TPC_CFG_SECTION 0x3800
+#define mmKERNEL_TENSOR_15_TPC2_EML_TPC_CFG_BASE 0x7FFF441748ull
+#define KERNEL_TENSOR_15_TPC2_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_15_TPC2_EML_TPC_CFG_SECTION 0x3800
+#define mmKERNEL_SYNC_OBJECT_TPC2_EML_TPC_CFG_BASE 0x7FFF441780ull
+#define KERNEL_SYNC_OBJECT_TPC2_EML_TPC_CFG_MAX_OFFSET 0x8000
+#define KERNEL_SYNC_OBJECT_TPC2_EML_TPC_CFG_SECTION 0x8000
+#define mmKERNEL_TPC2_EML_TPC_CFG_BASE 0x7FFF441788ull
+#define KERNEL_TPC2_EML_TPC_CFG_MAX_OFFSET 0xB800
+#define KERNEL_TPC2_EML_TPC_CFG_SECTION 0x2780
+#define mmQM_TENSOR_0_TPC2_EML_TPC_CFG_BASE 0x7FFF441A00ull
+#define QM_TENSOR_0_TPC2_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define QM_TENSOR_0_TPC2_EML_TPC_CFG_SECTION 0x3800
+#define mmQM_TENSOR_1_TPC2_EML_TPC_CFG_BASE 0x7FFF441A38ull
+#define QM_TENSOR_1_TPC2_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define QM_TENSOR_1_TPC2_EML_TPC_CFG_SECTION 0x3800
+#define mmQM_TENSOR_2_TPC2_EML_TPC_CFG_BASE 0x7FFF441A70ull
+#define QM_TENSOR_2_TPC2_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define QM_TENSOR_2_TPC2_EML_TPC_CFG_SECTION 0x3800
+#define mmQM_TENSOR_3_TPC2_EML_TPC_CFG_BASE 0x7FFF441AA8ull
+#define QM_TENSOR_3_TPC2_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define QM_TENSOR_3_TPC2_EML_TPC_CFG_SECTION 0x3800
+#define mmQM_TENSOR_4_TPC2_EML_TPC_CFG_BASE 0x7FFF441AE0ull
+#define QM_TENSOR_4_TPC2_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define QM_TENSOR_4_TPC2_EML_TPC_CFG_SECTION 0x3800
+#define mmQM_TENSOR_5_TPC2_EML_TPC_CFG_BASE 0x7FFF441B18ull
+#define QM_TENSOR_5_TPC2_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define QM_TENSOR_5_TPC2_EML_TPC_CFG_SECTION 0x3800
+#define mmQM_TENSOR_6_TPC2_EML_TPC_CFG_BASE 0x7FFF441B50ull
+#define QM_TENSOR_6_TPC2_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define QM_TENSOR_6_TPC2_EML_TPC_CFG_SECTION 0x3800
+#define mmQM_TENSOR_7_TPC2_EML_TPC_CFG_BASE 0x7FFF441B88ull
+#define QM_TENSOR_7_TPC2_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define QM_TENSOR_7_TPC2_EML_TPC_CFG_SECTION 0x3800
+#define mmQM_TENSOR_8_TPC2_EML_TPC_CFG_BASE 0x7FFF441BC0ull
+#define QM_TENSOR_8_TPC2_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define QM_TENSOR_8_TPC2_EML_TPC_CFG_SECTION 0x3800
+#define mmQM_TENSOR_9_TPC2_EML_TPC_CFG_BASE 0x7FFF441BF8ull
+#define QM_TENSOR_9_TPC2_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define QM_TENSOR_9_TPC2_EML_TPC_CFG_SECTION 0x3800
+#define mmQM_TENSOR_10_TPC2_EML_TPC_CFG_BASE 0x7FFF441C30ull
+#define QM_TENSOR_10_TPC2_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define QM_TENSOR_10_TPC2_EML_TPC_CFG_SECTION 0x3800
+#define mmQM_TENSOR_11_TPC2_EML_TPC_CFG_BASE 0x7FFF441C68ull
+#define QM_TENSOR_11_TPC2_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define QM_TENSOR_11_TPC2_EML_TPC_CFG_SECTION 0x3800
+#define mmQM_TENSOR_12_TPC2_EML_TPC_CFG_BASE 0x7FFF441CA0ull
+#define QM_TENSOR_12_TPC2_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define QM_TENSOR_12_TPC2_EML_TPC_CFG_SECTION 0x3800
+#define mmQM_TENSOR_13_TPC2_EML_TPC_CFG_BASE 0x7FFF441CD8ull
+#define QM_TENSOR_13_TPC2_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define QM_TENSOR_13_TPC2_EML_TPC_CFG_SECTION 0x3800
+#define mmQM_TENSOR_14_TPC2_EML_TPC_CFG_BASE 0x7FFF441D10ull
+#define QM_TENSOR_14_TPC2_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define QM_TENSOR_14_TPC2_EML_TPC_CFG_SECTION 0x3800
+#define mmQM_TENSOR_15_TPC2_EML_TPC_CFG_BASE 0x7FFF441D48ull
+#define QM_TENSOR_15_TPC2_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define QM_TENSOR_15_TPC2_EML_TPC_CFG_SECTION 0x3800
+#define mmQM_SYNC_OBJECT_TPC2_EML_TPC_CFG_BASE 0x7FFF441D80ull
+#define QM_SYNC_OBJECT_TPC2_EML_TPC_CFG_MAX_OFFSET 0x8000
+#define QM_SYNC_OBJECT_TPC2_EML_TPC_CFG_SECTION 0x8000
+#define mmQM_TPC2_EML_TPC_CFG_BASE 0x7FFF441D88ull
+#define QM_TPC2_EML_TPC_CFG_MAX_OFFSET 0xB800
+#define QM_TPC2_EML_TPC_CFG_SECTION 0x2780
+#define mmTPC2_EML_TPC_QM_BASE 0x7FFF442000ull
+#define TPC2_EML_TPC_QM_MAX_OFFSET 0xD040
+#define TPC2_EML_TPC_QM_SECTION 0x1BD000
+#define mmTPC2_EML_CS_BASE 0x7FFF5FF000ull
+#define TPC2_EML_CS_MAX_OFFSET 0x1000
+#define TPC2_EML_CS_SECTION 0x1000
+#define mmTPC3_ROM_TABLE_BASE 0x7FFF600000ull
+#define TPC3_ROM_TABLE_MAX_OFFSET 0x1000
+#define TPC3_ROM_TABLE_SECTION 0x1000
+#define mmTPC3_EML_SPMU_BASE 0x7FFF601000ull
+#define TPC3_EML_SPMU_MAX_OFFSET 0x1000
+#define TPC3_EML_SPMU_SECTION 0x1000
+#define mmTPC3_EML_ETF_BASE 0x7FFF602000ull
+#define TPC3_EML_ETF_MAX_OFFSET 0x1000
+#define TPC3_EML_ETF_SECTION 0x1000
+#define mmTPC3_EML_STM_BASE 0x7FFF603000ull
+#define TPC3_EML_STM_MAX_OFFSET 0x1000
+#define TPC3_EML_STM_SECTION 0x2000
+#define mmTPC3_EML_CTI_BASE 0x7FFF605000ull
+#define TPC3_EML_CTI_MAX_OFFSET 0x1000
+#define TPC3_EML_CTI_SECTION 0x1000
+#define mmTPC3_EML_FUNNEL_BASE 0x7FFF606000ull
+#define TPC3_EML_FUNNEL_MAX_OFFSET 0x1000
+#define TPC3_EML_FUNNEL_SECTION 0x1000
+#define mmTPC3_EML_BUSMON_0_BASE 0x7FFF607000ull
+#define TPC3_EML_BUSMON_0_MAX_OFFSET 0x1000
+#define TPC3_EML_BUSMON_0_SECTION 0x1000
+#define mmTPC3_EML_BUSMON_1_BASE 0x7FFF608000ull
+#define TPC3_EML_BUSMON_1_MAX_OFFSET 0x1000
+#define TPC3_EML_BUSMON_1_SECTION 0x1000
+#define mmTPC3_EML_BUSMON_2_BASE 0x7FFF609000ull
+#define TPC3_EML_BUSMON_2_MAX_OFFSET 0x1000
+#define TPC3_EML_BUSMON_2_SECTION 0x1000
+#define mmTPC3_EML_BUSMON_3_BASE 0x7FFF60A000ull
+#define TPC3_EML_BUSMON_3_MAX_OFFSET 0x1000
+#define TPC3_EML_BUSMON_3_SECTION 0x36000
+#define mmTPC3_EML_CFG_BASE 0x7FFF640000ull
+#define TPC3_EML_CFG_MAX_OFFSET 0x3380
+#define TPC3_EML_CFG_SECTION 0x1000
+#define mmTPC3_EML_TPC_CFG_BASE 0x7FFF641000ull
+#define TPC3_EML_TPC_CFG_MAX_OFFSET 0xE400
+#define TPC3_EML_TPC_CFG_SECTION 0x4000
+#define mmKERNEL_TENSOR_0_TPC3_EML_TPC_CFG_BASE 0x7FFF641400ull
+#define KERNEL_TENSOR_0_TPC3_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_0_TPC3_EML_TPC_CFG_SECTION 0x3800
+#define mmKERNEL_TENSOR_1_TPC3_EML_TPC_CFG_BASE 0x7FFF641438ull
+#define KERNEL_TENSOR_1_TPC3_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_1_TPC3_EML_TPC_CFG_SECTION 0x3800
+#define mmKERNEL_TENSOR_2_TPC3_EML_TPC_CFG_BASE 0x7FFF641470ull
+#define KERNEL_TENSOR_2_TPC3_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_2_TPC3_EML_TPC_CFG_SECTION 0x3800
+#define mmKERNEL_TENSOR_3_TPC3_EML_TPC_CFG_BASE 0x7FFF6414A8ull
+#define KERNEL_TENSOR_3_TPC3_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_3_TPC3_EML_TPC_CFG_SECTION 0x3800
+#define mmKERNEL_TENSOR_4_TPC3_EML_TPC_CFG_BASE 0x7FFF6414E0ull
+#define KERNEL_TENSOR_4_TPC3_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_4_TPC3_EML_TPC_CFG_SECTION 0x3800
+#define mmKERNEL_TENSOR_5_TPC3_EML_TPC_CFG_BASE 0x7FFF641518ull
+#define KERNEL_TENSOR_5_TPC3_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_5_TPC3_EML_TPC_CFG_SECTION 0x3800
+#define mmKERNEL_TENSOR_6_TPC3_EML_TPC_CFG_BASE 0x7FFF641550ull
+#define KERNEL_TENSOR_6_TPC3_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_6_TPC3_EML_TPC_CFG_SECTION 0x3800
+#define mmKERNEL_TENSOR_7_TPC3_EML_TPC_CFG_BASE 0x7FFF641588ull
+#define KERNEL_TENSOR_7_TPC3_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_7_TPC3_EML_TPC_CFG_SECTION 0x3800
+#define mmKERNEL_TENSOR_8_TPC3_EML_TPC_CFG_BASE 0x7FFF6415C0ull
+#define KERNEL_TENSOR_8_TPC3_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_8_TPC3_EML_TPC_CFG_SECTION 0x3800
+#define mmKERNEL_TENSOR_9_TPC3_EML_TPC_CFG_BASE 0x7FFF6415F8ull
+#define KERNEL_TENSOR_9_TPC3_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_9_TPC3_EML_TPC_CFG_SECTION 0x3800
+#define mmKERNEL_TENSOR_10_TPC3_EML_TPC_CFG_BASE 0x7FFF641630ull
+#define KERNEL_TENSOR_10_TPC3_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_10_TPC3_EML_TPC_CFG_SECTION 0x3800
+#define mmKERNEL_TENSOR_11_TPC3_EML_TPC_CFG_BASE 0x7FFF641668ull
+#define KERNEL_TENSOR_11_TPC3_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_11_TPC3_EML_TPC_CFG_SECTION 0x3800
+#define mmKERNEL_TENSOR_12_TPC3_EML_TPC_CFG_BASE 0x7FFF6416A0ull
+#define KERNEL_TENSOR_12_TPC3_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_12_TPC3_EML_TPC_CFG_SECTION 0x3800
+#define mmKERNEL_TENSOR_13_TPC3_EML_TPC_CFG_BASE 0x7FFF6416D8ull
+#define KERNEL_TENSOR_13_TPC3_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_13_TPC3_EML_TPC_CFG_SECTION 0x3800
+#define mmKERNEL_TENSOR_14_TPC3_EML_TPC_CFG_BASE 0x7FFF641710ull
+#define KERNEL_TENSOR_14_TPC3_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_14_TPC3_EML_TPC_CFG_SECTION 0x3800
+#define mmKERNEL_TENSOR_15_TPC3_EML_TPC_CFG_BASE 0x7FFF641748ull
+#define KERNEL_TENSOR_15_TPC3_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_15_TPC3_EML_TPC_CFG_SECTION 0x3800
+#define mmKERNEL_SYNC_OBJECT_TPC3_EML_TPC_CFG_BASE 0x7FFF641780ull
+#define KERNEL_SYNC_OBJECT_TPC3_EML_TPC_CFG_MAX_OFFSET 0x8000
+#define KERNEL_SYNC_OBJECT_TPC3_EML_TPC_CFG_SECTION 0x8000
+#define mmKERNEL_TPC3_EML_TPC_CFG_BASE 0x7FFF641788ull
+#define KERNEL_TPC3_EML_TPC_CFG_MAX_OFFSET 0xB800
+#define KERNEL_TPC3_EML_TPC_CFG_SECTION 0x2780
+#define mmQM_TENSOR_0_TPC3_EML_TPC_CFG_BASE 0x7FFF641A00ull
+#define QM_TENSOR_0_TPC3_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define QM_TENSOR_0_TPC3_EML_TPC_CFG_SECTION 0x3800
+#define mmQM_TENSOR_1_TPC3_EML_TPC_CFG_BASE 0x7FFF641A38ull
+#define QM_TENSOR_1_TPC3_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define QM_TENSOR_1_TPC3_EML_TPC_CFG_SECTION 0x3800
+#define mmQM_TENSOR_2_TPC3_EML_TPC_CFG_BASE 0x7FFF641A70ull
+#define QM_TENSOR_2_TPC3_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define QM_TENSOR_2_TPC3_EML_TPC_CFG_SECTION 0x3800
+#define mmQM_TENSOR_3_TPC3_EML_TPC_CFG_BASE 0x7FFF641AA8ull
+#define QM_TENSOR_3_TPC3_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define QM_TENSOR_3_TPC3_EML_TPC_CFG_SECTION 0x3800
+#define mmQM_TENSOR_4_TPC3_EML_TPC_CFG_BASE 0x7FFF641AE0ull
+#define QM_TENSOR_4_TPC3_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define QM_TENSOR_4_TPC3_EML_TPC_CFG_SECTION 0x3800
+#define mmQM_TENSOR_5_TPC3_EML_TPC_CFG_BASE 0x7FFF641B18ull
+#define QM_TENSOR_5_TPC3_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define QM_TENSOR_5_TPC3_EML_TPC_CFG_SECTION 0x3800
+#define mmQM_TENSOR_6_TPC3_EML_TPC_CFG_BASE 0x7FFF641B50ull
+#define QM_TENSOR_6_TPC3_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define QM_TENSOR_6_TPC3_EML_TPC_CFG_SECTION 0x3800
+#define mmQM_TENSOR_7_TPC3_EML_TPC_CFG_BASE 0x7FFF641B88ull
+#define QM_TENSOR_7_TPC3_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define QM_TENSOR_7_TPC3_EML_TPC_CFG_SECTION 0x3800
+#define mmQM_TENSOR_8_TPC3_EML_TPC_CFG_BASE 0x7FFF641BC0ull
+#define QM_TENSOR_8_TPC3_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define QM_TENSOR_8_TPC3_EML_TPC_CFG_SECTION 0x3800
+#define mmQM_TENSOR_9_TPC3_EML_TPC_CFG_BASE 0x7FFF641BF8ull
+#define QM_TENSOR_9_TPC3_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define QM_TENSOR_9_TPC3_EML_TPC_CFG_SECTION 0x3800
+#define mmQM_TENSOR_10_TPC3_EML_TPC_CFG_BASE 0x7FFF641C30ull
+#define QM_TENSOR_10_TPC3_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define QM_TENSOR_10_TPC3_EML_TPC_CFG_SECTION 0x3800
+#define mmQM_TENSOR_11_TPC3_EML_TPC_CFG_BASE 0x7FFF641C68ull
+#define QM_TENSOR_11_TPC3_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define QM_TENSOR_11_TPC3_EML_TPC_CFG_SECTION 0x3800
+#define mmQM_TENSOR_12_TPC3_EML_TPC_CFG_BASE 0x7FFF641CA0ull
+#define QM_TENSOR_12_TPC3_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define QM_TENSOR_12_TPC3_EML_TPC_CFG_SECTION 0x3800
+#define mmQM_TENSOR_13_TPC3_EML_TPC_CFG_BASE 0x7FFF641CD8ull
+#define QM_TENSOR_13_TPC3_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define QM_TENSOR_13_TPC3_EML_TPC_CFG_SECTION 0x3800
+#define mmQM_TENSOR_14_TPC3_EML_TPC_CFG_BASE 0x7FFF641D10ull
+#define QM_TENSOR_14_TPC3_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define QM_TENSOR_14_TPC3_EML_TPC_CFG_SECTION 0x3800
+#define mmQM_TENSOR_15_TPC3_EML_TPC_CFG_BASE 0x7FFF641D48ull
+#define QM_TENSOR_15_TPC3_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define QM_TENSOR_15_TPC3_EML_TPC_CFG_SECTION 0x3800
+#define mmQM_SYNC_OBJECT_TPC3_EML_TPC_CFG_BASE 0x7FFF641D80ull
+#define QM_SYNC_OBJECT_TPC3_EML_TPC_CFG_MAX_OFFSET 0x8000
+#define QM_SYNC_OBJECT_TPC3_EML_TPC_CFG_SECTION 0x8000
+#define mmQM_TPC3_EML_TPC_CFG_BASE 0x7FFF641D88ull
+#define QM_TPC3_EML_TPC_CFG_MAX_OFFSET 0xB800
+#define QM_TPC3_EML_TPC_CFG_SECTION 0x2780
+#define mmTPC3_EML_TPC_QM_BASE 0x7FFF642000ull
+#define TPC3_EML_TPC_QM_MAX_OFFSET 0xD040
+#define TPC3_EML_TPC_QM_SECTION 0x1BD000
+#define mmTPC3_EML_CS_BASE 0x7FFF7FF000ull
+#define TPC3_EML_CS_MAX_OFFSET 0x1000
+#define TPC3_EML_CS_SECTION 0x1000
+#define mmTPC4_ROM_TABLE_BASE 0x7FFF800000ull
+#define TPC4_ROM_TABLE_MAX_OFFSET 0x1000
+#define TPC4_ROM_TABLE_SECTION 0x1000
+#define mmTPC4_EML_SPMU_BASE 0x7FFF801000ull
+#define TPC4_EML_SPMU_MAX_OFFSET 0x1000
+#define TPC4_EML_SPMU_SECTION 0x1000
+#define mmTPC4_EML_ETF_BASE 0x7FFF802000ull
+#define TPC4_EML_ETF_MAX_OFFSET 0x1000
+#define TPC4_EML_ETF_SECTION 0x1000
+#define mmTPC4_EML_STM_BASE 0x7FFF803000ull
+#define TPC4_EML_STM_MAX_OFFSET 0x1000
+#define TPC4_EML_STM_SECTION 0x2000
+#define mmTPC4_EML_CTI_BASE 0x7FFF805000ull
+#define TPC4_EML_CTI_MAX_OFFSET 0x1000
+#define TPC4_EML_CTI_SECTION 0x1000
+#define mmTPC4_EML_FUNNEL_BASE 0x7FFF806000ull
+#define TPC4_EML_FUNNEL_MAX_OFFSET 0x1000
+#define TPC4_EML_FUNNEL_SECTION 0x1000
+#define mmTPC4_EML_BUSMON_0_BASE 0x7FFF807000ull
+#define TPC4_EML_BUSMON_0_MAX_OFFSET 0x1000
+#define TPC4_EML_BUSMON_0_SECTION 0x1000
+#define mmTPC4_EML_BUSMON_1_BASE 0x7FFF808000ull
+#define TPC4_EML_BUSMON_1_MAX_OFFSET 0x1000
+#define TPC4_EML_BUSMON_1_SECTION 0x1000
+#define mmTPC4_EML_BUSMON_2_BASE 0x7FFF809000ull
+#define TPC4_EML_BUSMON_2_MAX_OFFSET 0x1000
+#define TPC4_EML_BUSMON_2_SECTION 0x1000
+#define mmTPC4_EML_BUSMON_3_BASE 0x7FFF80A000ull
+#define TPC4_EML_BUSMON_3_MAX_OFFSET 0x1000
+#define TPC4_EML_BUSMON_3_SECTION 0x36000
+#define mmTPC4_EML_CFG_BASE 0x7FFF840000ull
+#define TPC4_EML_CFG_MAX_OFFSET 0x3380
+#define TPC4_EML_CFG_SECTION 0x1000
+#define mmTPC4_EML_TPC_CFG_BASE 0x7FFF841000ull
+#define TPC4_EML_TPC_CFG_MAX_OFFSET 0xE400
+#define TPC4_EML_TPC_CFG_SECTION 0x4000
+#define mmKERNEL_TENSOR_0_TPC4_EML_TPC_CFG_BASE 0x7FFF841400ull
+#define KERNEL_TENSOR_0_TPC4_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_0_TPC4_EML_TPC_CFG_SECTION 0x3800
+#define mmKERNEL_TENSOR_1_TPC4_EML_TPC_CFG_BASE 0x7FFF841438ull
+#define KERNEL_TENSOR_1_TPC4_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_1_TPC4_EML_TPC_CFG_SECTION 0x3800
+#define mmKERNEL_TENSOR_2_TPC4_EML_TPC_CFG_BASE 0x7FFF841470ull
+#define KERNEL_TENSOR_2_TPC4_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_2_TPC4_EML_TPC_CFG_SECTION 0x3800
+#define mmKERNEL_TENSOR_3_TPC4_EML_TPC_CFG_BASE 0x7FFF8414A8ull
+#define KERNEL_TENSOR_3_TPC4_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_3_TPC4_EML_TPC_CFG_SECTION 0x3800
+#define mmKERNEL_TENSOR_4_TPC4_EML_TPC_CFG_BASE 0x7FFF8414E0ull
+#define KERNEL_TENSOR_4_TPC4_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_4_TPC4_EML_TPC_CFG_SECTION 0x3800
+#define mmKERNEL_TENSOR_5_TPC4_EML_TPC_CFG_BASE 0x7FFF841518ull
+#define KERNEL_TENSOR_5_TPC4_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_5_TPC4_EML_TPC_CFG_SECTION 0x3800
+#define mmKERNEL_TENSOR_6_TPC4_EML_TPC_CFG_BASE 0x7FFF841550ull
+#define KERNEL_TENSOR_6_TPC4_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_6_TPC4_EML_TPC_CFG_SECTION 0x3800
+#define mmKERNEL_TENSOR_7_TPC4_EML_TPC_CFG_BASE 0x7FFF841588ull
+#define KERNEL_TENSOR_7_TPC4_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_7_TPC4_EML_TPC_CFG_SECTION 0x3800
+#define mmKERNEL_TENSOR_8_TPC4_EML_TPC_CFG_BASE 0x7FFF8415C0ull
+#define KERNEL_TENSOR_8_TPC4_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_8_TPC4_EML_TPC_CFG_SECTION 0x3800
+#define mmKERNEL_TENSOR_9_TPC4_EML_TPC_CFG_BASE 0x7FFF8415F8ull
+#define KERNEL_TENSOR_9_TPC4_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_9_TPC4_EML_TPC_CFG_SECTION 0x3800
+#define mmKERNEL_TENSOR_10_TPC4_EML_TPC_CFG_BASE 0x7FFF841630ull
+#define KERNEL_TENSOR_10_TPC4_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_10_TPC4_EML_TPC_CFG_SECTION 0x3800
+#define mmKERNEL_TENSOR_11_TPC4_EML_TPC_CFG_BASE 0x7FFF841668ull
+#define KERNEL_TENSOR_11_TPC4_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_11_TPC4_EML_TPC_CFG_SECTION 0x3800
+#define mmKERNEL_TENSOR_12_TPC4_EML_TPC_CFG_BASE 0x7FFF8416A0ull
+#define KERNEL_TENSOR_12_TPC4_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_12_TPC4_EML_TPC_CFG_SECTION 0x3800
+#define mmKERNEL_TENSOR_13_TPC4_EML_TPC_CFG_BASE 0x7FFF8416D8ull
+#define KERNEL_TENSOR_13_TPC4_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_13_TPC4_EML_TPC_CFG_SECTION 0x3800
+#define mmKERNEL_TENSOR_14_TPC4_EML_TPC_CFG_BASE 0x7FFF841710ull
+#define KERNEL_TENSOR_14_TPC4_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_14_TPC4_EML_TPC_CFG_SECTION 0x3800
+#define mmKERNEL_TENSOR_15_TPC4_EML_TPC_CFG_BASE 0x7FFF841748ull
+#define KERNEL_TENSOR_15_TPC4_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_15_TPC4_EML_TPC_CFG_SECTION 0x3800
+#define mmKERNEL_SYNC_OBJECT_TPC4_EML_TPC_CFG_BASE 0x7FFF841780ull
+#define KERNEL_SYNC_OBJECT_TPC4_EML_TPC_CFG_MAX_OFFSET 0x8000
+#define KERNEL_SYNC_OBJECT_TPC4_EML_TPC_CFG_SECTION 0x8000
+#define mmKERNEL_TPC4_EML_TPC_CFG_BASE 0x7FFF841788ull
+#define KERNEL_TPC4_EML_TPC_CFG_MAX_OFFSET 0xB800
+#define KERNEL_TPC4_EML_TPC_CFG_SECTION 0x2780
+#define mmQM_TENSOR_0_TPC4_EML_TPC_CFG_BASE 0x7FFF841A00ull
+#define QM_TENSOR_0_TPC4_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define QM_TENSOR_0_TPC4_EML_TPC_CFG_SECTION 0x3800
+#define mmQM_TENSOR_1_TPC4_EML_TPC_CFG_BASE 0x7FFF841A38ull
+#define QM_TENSOR_1_TPC4_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define QM_TENSOR_1_TPC4_EML_TPC_CFG_SECTION 0x3800
+#define mmQM_TENSOR_2_TPC4_EML_TPC_CFG_BASE 0x7FFF841A70ull
+#define QM_TENSOR_2_TPC4_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define QM_TENSOR_2_TPC4_EML_TPC_CFG_SECTION 0x3800
+#define mmQM_TENSOR_3_TPC4_EML_TPC_CFG_BASE 0x7FFF841AA8ull
+#define QM_TENSOR_3_TPC4_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define QM_TENSOR_3_TPC4_EML_TPC_CFG_SECTION 0x3800
+#define mmQM_TENSOR_4_TPC4_EML_TPC_CFG_BASE 0x7FFF841AE0ull
+#define QM_TENSOR_4_TPC4_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define QM_TENSOR_4_TPC4_EML_TPC_CFG_SECTION 0x3800
+#define mmQM_TENSOR_5_TPC4_EML_TPC_CFG_BASE 0x7FFF841B18ull
+#define QM_TENSOR_5_TPC4_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define QM_TENSOR_5_TPC4_EML_TPC_CFG_SECTION 0x3800
+#define mmQM_TENSOR_6_TPC4_EML_TPC_CFG_BASE 0x7FFF841B50ull
+#define QM_TENSOR_6_TPC4_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define QM_TENSOR_6_TPC4_EML_TPC_CFG_SECTION 0x3800
+#define mmQM_TENSOR_7_TPC4_EML_TPC_CFG_BASE 0x7FFF841B88ull
+#define QM_TENSOR_7_TPC4_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define QM_TENSOR_7_TPC4_EML_TPC_CFG_SECTION 0x3800
+#define mmQM_TENSOR_8_TPC4_EML_TPC_CFG_BASE 0x7FFF841BC0ull
+#define QM_TENSOR_8_TPC4_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define QM_TENSOR_8_TPC4_EML_TPC_CFG_SECTION 0x3800
+#define mmQM_TENSOR_9_TPC4_EML_TPC_CFG_BASE 0x7FFF841BF8ull
+#define QM_TENSOR_9_TPC4_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define QM_TENSOR_9_TPC4_EML_TPC_CFG_SECTION 0x3800
+#define mmQM_TENSOR_10_TPC4_EML_TPC_CFG_BASE 0x7FFF841C30ull
+#define QM_TENSOR_10_TPC4_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define QM_TENSOR_10_TPC4_EML_TPC_CFG_SECTION 0x3800
+#define mmQM_TENSOR_11_TPC4_EML_TPC_CFG_BASE 0x7FFF841C68ull
+#define QM_TENSOR_11_TPC4_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define QM_TENSOR_11_TPC4_EML_TPC_CFG_SECTION 0x3800
+#define mmQM_TENSOR_12_TPC4_EML_TPC_CFG_BASE 0x7FFF841CA0ull
+#define QM_TENSOR_12_TPC4_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define QM_TENSOR_12_TPC4_EML_TPC_CFG_SECTION 0x3800
+#define mmQM_TENSOR_13_TPC4_EML_TPC_CFG_BASE 0x7FFF841CD8ull
+#define QM_TENSOR_13_TPC4_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define QM_TENSOR_13_TPC4_EML_TPC_CFG_SECTION 0x3800
+#define mmQM_TENSOR_14_TPC4_EML_TPC_CFG_BASE 0x7FFF841D10ull
+#define QM_TENSOR_14_TPC4_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define QM_TENSOR_14_TPC4_EML_TPC_CFG_SECTION 0x3800
+#define mmQM_TENSOR_15_TPC4_EML_TPC_CFG_BASE 0x7FFF841D48ull
+#define QM_TENSOR_15_TPC4_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define QM_TENSOR_15_TPC4_EML_TPC_CFG_SECTION 0x3800
+#define mmQM_SYNC_OBJECT_TPC4_EML_TPC_CFG_BASE 0x7FFF841D80ull
+#define QM_SYNC_OBJECT_TPC4_EML_TPC_CFG_MAX_OFFSET 0x8000
+#define QM_SYNC_OBJECT_TPC4_EML_TPC_CFG_SECTION 0x8000
+#define mmQM_TPC4_EML_TPC_CFG_BASE 0x7FFF841D88ull
+#define QM_TPC4_EML_TPC_CFG_MAX_OFFSET 0xB800
+#define QM_TPC4_EML_TPC_CFG_SECTION 0x2780
+#define mmTPC4_EML_TPC_QM_BASE 0x7FFF842000ull
+#define TPC4_EML_TPC_QM_MAX_OFFSET 0xD040
+#define TPC4_EML_TPC_QM_SECTION 0x1BD000
+#define mmTPC4_EML_CS_BASE 0x7FFF9FF000ull
+#define TPC4_EML_CS_MAX_OFFSET 0x1000
+#define TPC4_EML_CS_SECTION 0x1000
+#define mmTPC5_ROM_TABLE_BASE 0x7FFFA00000ull
+#define TPC5_ROM_TABLE_MAX_OFFSET 0x1000
+#define TPC5_ROM_TABLE_SECTION 0x1000
+#define mmTPC5_EML_SPMU_BASE 0x7FFFA01000ull
+#define TPC5_EML_SPMU_MAX_OFFSET 0x1000
+#define TPC5_EML_SPMU_SECTION 0x1000
+#define mmTPC5_EML_ETF_BASE 0x7FFFA02000ull
+#define TPC5_EML_ETF_MAX_OFFSET 0x1000
+#define TPC5_EML_ETF_SECTION 0x1000
+#define mmTPC5_EML_STM_BASE 0x7FFFA03000ull
+#define TPC5_EML_STM_MAX_OFFSET 0x1000
+#define TPC5_EML_STM_SECTION 0x2000
+#define mmTPC5_EML_CTI_BASE 0x7FFFA05000ull
+#define TPC5_EML_CTI_MAX_OFFSET 0x1000
+#define TPC5_EML_CTI_SECTION 0x1000
+#define mmTPC5_EML_FUNNEL_BASE 0x7FFFA06000ull
+#define TPC5_EML_FUNNEL_MAX_OFFSET 0x1000
+#define TPC5_EML_FUNNEL_SECTION 0x1000
+#define mmTPC5_EML_BUSMON_0_BASE 0x7FFFA07000ull
+#define TPC5_EML_BUSMON_0_MAX_OFFSET 0x1000
+#define TPC5_EML_BUSMON_0_SECTION 0x1000
+#define mmTPC5_EML_BUSMON_1_BASE 0x7FFFA08000ull
+#define TPC5_EML_BUSMON_1_MAX_OFFSET 0x1000
+#define TPC5_EML_BUSMON_1_SECTION 0x1000
+#define mmTPC5_EML_BUSMON_2_BASE 0x7FFFA09000ull
+#define TPC5_EML_BUSMON_2_MAX_OFFSET 0x1000
+#define TPC5_EML_BUSMON_2_SECTION 0x1000
+#define mmTPC5_EML_BUSMON_3_BASE 0x7FFFA0A000ull
+#define TPC5_EML_BUSMON_3_MAX_OFFSET 0x1000
+#define TPC5_EML_BUSMON_3_SECTION 0x36000
+#define mmTPC5_EML_CFG_BASE 0x7FFFA40000ull
+#define TPC5_EML_CFG_MAX_OFFSET 0x3380
+#define TPC5_EML_CFG_SECTION 0x1000
+#define mmTPC5_EML_TPC_CFG_BASE 0x7FFFA41000ull
+#define TPC5_EML_TPC_CFG_MAX_OFFSET 0xE400
+#define TPC5_EML_TPC_CFG_SECTION 0x4000
+#define mmKERNEL_TENSOR_0_TPC5_EML_TPC_CFG_BASE 0x7FFFA41400ull
+#define KERNEL_TENSOR_0_TPC5_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_0_TPC5_EML_TPC_CFG_SECTION 0x3800
+#define mmKERNEL_TENSOR_1_TPC5_EML_TPC_CFG_BASE 0x7FFFA41438ull
+#define KERNEL_TENSOR_1_TPC5_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_1_TPC5_EML_TPC_CFG_SECTION 0x3800
+#define mmKERNEL_TENSOR_2_TPC5_EML_TPC_CFG_BASE 0x7FFFA41470ull
+#define KERNEL_TENSOR_2_TPC5_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_2_TPC5_EML_TPC_CFG_SECTION 0x3800
+#define mmKERNEL_TENSOR_3_TPC5_EML_TPC_CFG_BASE 0x7FFFA414A8ull
+#define KERNEL_TENSOR_3_TPC5_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_3_TPC5_EML_TPC_CFG_SECTION 0x3800
+#define mmKERNEL_TENSOR_4_TPC5_EML_TPC_CFG_BASE 0x7FFFA414E0ull
+#define KERNEL_TENSOR_4_TPC5_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_4_TPC5_EML_TPC_CFG_SECTION 0x3800
+#define mmKERNEL_TENSOR_5_TPC5_EML_TPC_CFG_BASE 0x7FFFA41518ull
+#define KERNEL_TENSOR_5_TPC5_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_5_TPC5_EML_TPC_CFG_SECTION 0x3800
+#define mmKERNEL_TENSOR_6_TPC5_EML_TPC_CFG_BASE 0x7FFFA41550ull
+#define KERNEL_TENSOR_6_TPC5_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_6_TPC5_EML_TPC_CFG_SECTION 0x3800
+#define mmKERNEL_TENSOR_7_TPC5_EML_TPC_CFG_BASE 0x7FFFA41588ull
+#define KERNEL_TENSOR_7_TPC5_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_7_TPC5_EML_TPC_CFG_SECTION 0x3800
+#define mmKERNEL_TENSOR_8_TPC5_EML_TPC_CFG_BASE 0x7FFFA415C0ull
+#define KERNEL_TENSOR_8_TPC5_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_8_TPC5_EML_TPC_CFG_SECTION 0x3800
+#define mmKERNEL_TENSOR_9_TPC5_EML_TPC_CFG_BASE 0x7FFFA415F8ull
+#define KERNEL_TENSOR_9_TPC5_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_9_TPC5_EML_TPC_CFG_SECTION 0x3800
+#define mmKERNEL_TENSOR_10_TPC5_EML_TPC_CFG_BASE 0x7FFFA41630ull
+#define KERNEL_TENSOR_10_TPC5_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_10_TPC5_EML_TPC_CFG_SECTION 0x3800
+#define mmKERNEL_TENSOR_11_TPC5_EML_TPC_CFG_BASE 0x7FFFA41668ull
+#define KERNEL_TENSOR_11_TPC5_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_11_TPC5_EML_TPC_CFG_SECTION 0x3800
+#define mmKERNEL_TENSOR_12_TPC5_EML_TPC_CFG_BASE 0x7FFFA416A0ull
+#define KERNEL_TENSOR_12_TPC5_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_12_TPC5_EML_TPC_CFG_SECTION 0x3800
+#define mmKERNEL_TENSOR_13_TPC5_EML_TPC_CFG_BASE 0x7FFFA416D8ull
+#define KERNEL_TENSOR_13_TPC5_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_13_TPC5_EML_TPC_CFG_SECTION 0x3800
+#define mmKERNEL_TENSOR_14_TPC5_EML_TPC_CFG_BASE 0x7FFFA41710ull
+#define KERNEL_TENSOR_14_TPC5_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_14_TPC5_EML_TPC_CFG_SECTION 0x3800
+#define mmKERNEL_TENSOR_15_TPC5_EML_TPC_CFG_BASE 0x7FFFA41748ull
+#define KERNEL_TENSOR_15_TPC5_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_15_TPC5_EML_TPC_CFG_SECTION 0x3800
+#define mmKERNEL_SYNC_OBJECT_TPC5_EML_TPC_CFG_BASE 0x7FFFA41780ull
+#define KERNEL_SYNC_OBJECT_TPC5_EML_TPC_CFG_MAX_OFFSET 0x8000
+#define KERNEL_SYNC_OBJECT_TPC5_EML_TPC_CFG_SECTION 0x8000
+#define mmKERNEL_TPC5_EML_TPC_CFG_BASE 0x7FFFA41788ull
+#define KERNEL_TPC5_EML_TPC_CFG_MAX_OFFSET 0xB800
+#define KERNEL_TPC5_EML_TPC_CFG_SECTION 0x2780
+#define mmQM_TENSOR_0_TPC5_EML_TPC_CFG_BASE 0x7FFFA41A00ull
+#define QM_TENSOR_0_TPC5_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define QM_TENSOR_0_TPC5_EML_TPC_CFG_SECTION 0x3800
+#define mmQM_TENSOR_1_TPC5_EML_TPC_CFG_BASE 0x7FFFA41A38ull
+#define QM_TENSOR_1_TPC5_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define QM_TENSOR_1_TPC5_EML_TPC_CFG_SECTION 0x3800
+#define mmQM_TENSOR_2_TPC5_EML_TPC_CFG_BASE 0x7FFFA41A70ull
+#define QM_TENSOR_2_TPC5_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define QM_TENSOR_2_TPC5_EML_TPC_CFG_SECTION 0x3800
+#define mmQM_TENSOR_3_TPC5_EML_TPC_CFG_BASE 0x7FFFA41AA8ull
+#define QM_TENSOR_3_TPC5_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define QM_TENSOR_3_TPC5_EML_TPC_CFG_SECTION 0x3800
+#define mmQM_TENSOR_4_TPC5_EML_TPC_CFG_BASE 0x7FFFA41AE0ull
+#define QM_TENSOR_4_TPC5_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define QM_TENSOR_4_TPC5_EML_TPC_CFG_SECTION 0x3800
+#define mmQM_TENSOR_5_TPC5_EML_TPC_CFG_BASE 0x7FFFA41B18ull
+#define QM_TENSOR_5_TPC5_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define QM_TENSOR_5_TPC5_EML_TPC_CFG_SECTION 0x3800
+#define mmQM_TENSOR_6_TPC5_EML_TPC_CFG_BASE 0x7FFFA41B50ull
+#define QM_TENSOR_6_TPC5_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define QM_TENSOR_6_TPC5_EML_TPC_CFG_SECTION 0x3800
+#define mmQM_TENSOR_7_TPC5_EML_TPC_CFG_BASE 0x7FFFA41B88ull
+#define QM_TENSOR_7_TPC5_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define QM_TENSOR_7_TPC5_EML_TPC_CFG_SECTION 0x3800
+#define mmQM_TENSOR_8_TPC5_EML_TPC_CFG_BASE 0x7FFFA41BC0ull
+#define QM_TENSOR_8_TPC5_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define QM_TENSOR_8_TPC5_EML_TPC_CFG_SECTION 0x3800
+#define mmQM_TENSOR_9_TPC5_EML_TPC_CFG_BASE 0x7FFFA41BF8ull
+#define QM_TENSOR_9_TPC5_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define QM_TENSOR_9_TPC5_EML_TPC_CFG_SECTION 0x3800
+#define mmQM_TENSOR_10_TPC5_EML_TPC_CFG_BASE 0x7FFFA41C30ull
+#define QM_TENSOR_10_TPC5_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define QM_TENSOR_10_TPC5_EML_TPC_CFG_SECTION 0x3800
+#define mmQM_TENSOR_11_TPC5_EML_TPC_CFG_BASE 0x7FFFA41C68ull
+#define QM_TENSOR_11_TPC5_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define QM_TENSOR_11_TPC5_EML_TPC_CFG_SECTION 0x3800
+#define mmQM_TENSOR_12_TPC5_EML_TPC_CFG_BASE 0x7FFFA41CA0ull
+#define QM_TENSOR_12_TPC5_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define QM_TENSOR_12_TPC5_EML_TPC_CFG_SECTION 0x3800
+#define mmQM_TENSOR_13_TPC5_EML_TPC_CFG_BASE 0x7FFFA41CD8ull
+#define QM_TENSOR_13_TPC5_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define QM_TENSOR_13_TPC5_EML_TPC_CFG_SECTION 0x3800
+#define mmQM_TENSOR_14_TPC5_EML_TPC_CFG_BASE 0x7FFFA41D10ull
+#define QM_TENSOR_14_TPC5_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define QM_TENSOR_14_TPC5_EML_TPC_CFG_SECTION 0x3800
+#define mmQM_TENSOR_15_TPC5_EML_TPC_CFG_BASE 0x7FFFA41D48ull
+#define QM_TENSOR_15_TPC5_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define QM_TENSOR_15_TPC5_EML_TPC_CFG_SECTION 0x3800
+#define mmQM_SYNC_OBJECT_TPC5_EML_TPC_CFG_BASE 0x7FFFA41D80ull
+#define QM_SYNC_OBJECT_TPC5_EML_TPC_CFG_MAX_OFFSET 0x8000
+#define QM_SYNC_OBJECT_TPC5_EML_TPC_CFG_SECTION 0x8000
+#define mmQM_TPC5_EML_TPC_CFG_BASE 0x7FFFA41D88ull
+#define QM_TPC5_EML_TPC_CFG_MAX_OFFSET 0xB800
+#define QM_TPC5_EML_TPC_CFG_SECTION 0x2780
+#define mmTPC5_EML_TPC_QM_BASE 0x7FFFA42000ull
+#define TPC5_EML_TPC_QM_MAX_OFFSET 0xD040
+#define TPC5_EML_TPC_QM_SECTION 0x1BD000
+#define mmTPC5_EML_CS_BASE 0x7FFFBFF000ull
+#define TPC5_EML_CS_MAX_OFFSET 0x1000
+#define TPC5_EML_CS_SECTION 0x1000
+#define mmTPC6_ROM_TABLE_BASE 0x7FFFC00000ull
+#define TPC6_ROM_TABLE_MAX_OFFSET 0x1000
+#define TPC6_ROM_TABLE_SECTION 0x1000
+#define mmTPC6_EML_SPMU_BASE 0x7FFFC01000ull
+#define TPC6_EML_SPMU_MAX_OFFSET 0x1000
+#define TPC6_EML_SPMU_SECTION 0x1000
+#define mmTPC6_EML_ETF_BASE 0x7FFFC02000ull
+#define TPC6_EML_ETF_MAX_OFFSET 0x1000
+#define TPC6_EML_ETF_SECTION 0x1000
+#define mmTPC6_EML_STM_BASE 0x7FFFC03000ull
+#define TPC6_EML_STM_MAX_OFFSET 0x1000
+#define TPC6_EML_STM_SECTION 0x2000
+#define mmTPC6_EML_CTI_BASE 0x7FFFC05000ull
+#define TPC6_EML_CTI_MAX_OFFSET 0x1000
+#define TPC6_EML_CTI_SECTION 0x1000
+#define mmTPC6_EML_FUNNEL_BASE 0x7FFFC06000ull
+#define TPC6_EML_FUNNEL_MAX_OFFSET 0x1000
+#define TPC6_EML_FUNNEL_SECTION 0x1000
+#define mmTPC6_EML_BUSMON_0_BASE 0x7FFFC07000ull
+#define TPC6_EML_BUSMON_0_MAX_OFFSET 0x1000
+#define TPC6_EML_BUSMON_0_SECTION 0x1000
+#define mmTPC6_EML_BUSMON_1_BASE 0x7FFFC08000ull
+#define TPC6_EML_BUSMON_1_MAX_OFFSET 0x1000
+#define TPC6_EML_BUSMON_1_SECTION 0x1000
+#define mmTPC6_EML_BUSMON_2_BASE 0x7FFFC09000ull
+#define TPC6_EML_BUSMON_2_MAX_OFFSET 0x1000
+#define TPC6_EML_BUSMON_2_SECTION 0x1000
+#define mmTPC6_EML_BUSMON_3_BASE 0x7FFFC0A000ull
+#define TPC6_EML_BUSMON_3_MAX_OFFSET 0x1000
+#define TPC6_EML_BUSMON_3_SECTION 0x36000
+#define mmTPC6_EML_CFG_BASE 0x7FFFC40000ull
+#define TPC6_EML_CFG_MAX_OFFSET 0x3380
+#define TPC6_EML_CFG_SECTION 0x1000
+#define mmTPC6_EML_TPC_CFG_BASE 0x7FFFC41000ull
+#define TPC6_EML_TPC_CFG_MAX_OFFSET 0xE400
+#define TPC6_EML_TPC_CFG_SECTION 0x4000
+#define mmKERNEL_TENSOR_0_TPC6_EML_TPC_CFG_BASE 0x7FFFC41400ull
+#define KERNEL_TENSOR_0_TPC6_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_0_TPC6_EML_TPC_CFG_SECTION 0x3800
+#define mmKERNEL_TENSOR_1_TPC6_EML_TPC_CFG_BASE 0x7FFFC41438ull
+#define KERNEL_TENSOR_1_TPC6_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_1_TPC6_EML_TPC_CFG_SECTION 0x3800
+#define mmKERNEL_TENSOR_2_TPC6_EML_TPC_CFG_BASE 0x7FFFC41470ull
+#define KERNEL_TENSOR_2_TPC6_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_2_TPC6_EML_TPC_CFG_SECTION 0x3800
+#define mmKERNEL_TENSOR_3_TPC6_EML_TPC_CFG_BASE 0x7FFFC414A8ull
+#define KERNEL_TENSOR_3_TPC6_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_3_TPC6_EML_TPC_CFG_SECTION 0x3800
+#define mmKERNEL_TENSOR_4_TPC6_EML_TPC_CFG_BASE 0x7FFFC414E0ull
+#define KERNEL_TENSOR_4_TPC6_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_4_TPC6_EML_TPC_CFG_SECTION 0x3800
+#define mmKERNEL_TENSOR_5_TPC6_EML_TPC_CFG_BASE 0x7FFFC41518ull
+#define KERNEL_TENSOR_5_TPC6_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_5_TPC6_EML_TPC_CFG_SECTION 0x3800
+#define mmKERNEL_TENSOR_6_TPC6_EML_TPC_CFG_BASE 0x7FFFC41550ull
+#define KERNEL_TENSOR_6_TPC6_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_6_TPC6_EML_TPC_CFG_SECTION 0x3800
+#define mmKERNEL_TENSOR_7_TPC6_EML_TPC_CFG_BASE 0x7FFFC41588ull
+#define KERNEL_TENSOR_7_TPC6_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_7_TPC6_EML_TPC_CFG_SECTION 0x3800
+#define mmKERNEL_TENSOR_8_TPC6_EML_TPC_CFG_BASE 0x7FFFC415C0ull
+#define KERNEL_TENSOR_8_TPC6_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_8_TPC6_EML_TPC_CFG_SECTION 0x3800
+#define mmKERNEL_TENSOR_9_TPC6_EML_TPC_CFG_BASE 0x7FFFC415F8ull
+#define KERNEL_TENSOR_9_TPC6_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_9_TPC6_EML_TPC_CFG_SECTION 0x3800
+#define mmKERNEL_TENSOR_10_TPC6_EML_TPC_CFG_BASE 0x7FFFC41630ull
+#define KERNEL_TENSOR_10_TPC6_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_10_TPC6_EML_TPC_CFG_SECTION 0x3800
+#define mmKERNEL_TENSOR_11_TPC6_EML_TPC_CFG_BASE 0x7FFFC41668ull
+#define KERNEL_TENSOR_11_TPC6_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_11_TPC6_EML_TPC_CFG_SECTION 0x3800
+#define mmKERNEL_TENSOR_12_TPC6_EML_TPC_CFG_BASE 0x7FFFC416A0ull
+#define KERNEL_TENSOR_12_TPC6_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_12_TPC6_EML_TPC_CFG_SECTION 0x3800
+#define mmKERNEL_TENSOR_13_TPC6_EML_TPC_CFG_BASE 0x7FFFC416D8ull
+#define KERNEL_TENSOR_13_TPC6_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_13_TPC6_EML_TPC_CFG_SECTION 0x3800
+#define mmKERNEL_TENSOR_14_TPC6_EML_TPC_CFG_BASE 0x7FFFC41710ull
+#define KERNEL_TENSOR_14_TPC6_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_14_TPC6_EML_TPC_CFG_SECTION 0x3800
+#define mmKERNEL_TENSOR_15_TPC6_EML_TPC_CFG_BASE 0x7FFFC41748ull
+#define KERNEL_TENSOR_15_TPC6_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_15_TPC6_EML_TPC_CFG_SECTION 0x3800
+#define mmKERNEL_SYNC_OBJECT_TPC6_EML_TPC_CFG_BASE 0x7FFFC41780ull
+#define KERNEL_SYNC_OBJECT_TPC6_EML_TPC_CFG_MAX_OFFSET 0x8000
+#define KERNEL_SYNC_OBJECT_TPC6_EML_TPC_CFG_SECTION 0x8000
+#define mmKERNEL_TPC6_EML_TPC_CFG_BASE 0x7FFFC41788ull
+#define KERNEL_TPC6_EML_TPC_CFG_MAX_OFFSET 0xB800
+#define KERNEL_TPC6_EML_TPC_CFG_SECTION 0x2780
+#define mmQM_TENSOR_0_TPC6_EML_TPC_CFG_BASE 0x7FFFC41A00ull
+#define QM_TENSOR_0_TPC6_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define QM_TENSOR_0_TPC6_EML_TPC_CFG_SECTION 0x3800
+#define mmQM_TENSOR_1_TPC6_EML_TPC_CFG_BASE 0x7FFFC41A38ull
+#define QM_TENSOR_1_TPC6_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define QM_TENSOR_1_TPC6_EML_TPC_CFG_SECTION 0x3800
+#define mmQM_TENSOR_2_TPC6_EML_TPC_CFG_BASE 0x7FFFC41A70ull
+#define QM_TENSOR_2_TPC6_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define QM_TENSOR_2_TPC6_EML_TPC_CFG_SECTION 0x3800
+#define mmQM_TENSOR_3_TPC6_EML_TPC_CFG_BASE 0x7FFFC41AA8ull
+#define QM_TENSOR_3_TPC6_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define QM_TENSOR_3_TPC6_EML_TPC_CFG_SECTION 0x3800
+#define mmQM_TENSOR_4_TPC6_EML_TPC_CFG_BASE 0x7FFFC41AE0ull
+#define QM_TENSOR_4_TPC6_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define QM_TENSOR_4_TPC6_EML_TPC_CFG_SECTION 0x3800
+#define mmQM_TENSOR_5_TPC6_EML_TPC_CFG_BASE 0x7FFFC41B18ull
+#define QM_TENSOR_5_TPC6_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define QM_TENSOR_5_TPC6_EML_TPC_CFG_SECTION 0x3800
+#define mmQM_TENSOR_6_TPC6_EML_TPC_CFG_BASE 0x7FFFC41B50ull
+#define QM_TENSOR_6_TPC6_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define QM_TENSOR_6_TPC6_EML_TPC_CFG_SECTION 0x3800
+#define mmQM_TENSOR_7_TPC6_EML_TPC_CFG_BASE 0x7FFFC41B88ull
+#define QM_TENSOR_7_TPC6_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define QM_TENSOR_7_TPC6_EML_TPC_CFG_SECTION 0x3800
+#define mmQM_TENSOR_8_TPC6_EML_TPC_CFG_BASE 0x7FFFC41BC0ull
+#define QM_TENSOR_8_TPC6_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define QM_TENSOR_8_TPC6_EML_TPC_CFG_SECTION 0x3800
+#define mmQM_TENSOR_9_TPC6_EML_TPC_CFG_BASE 0x7FFFC41BF8ull
+#define QM_TENSOR_9_TPC6_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define QM_TENSOR_9_TPC6_EML_TPC_CFG_SECTION 0x3800
+#define mmQM_TENSOR_10_TPC6_EML_TPC_CFG_BASE 0x7FFFC41C30ull
+#define QM_TENSOR_10_TPC6_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define QM_TENSOR_10_TPC6_EML_TPC_CFG_SECTION 0x3800
+#define mmQM_TENSOR_11_TPC6_EML_TPC_CFG_BASE 0x7FFFC41C68ull
+#define QM_TENSOR_11_TPC6_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define QM_TENSOR_11_TPC6_EML_TPC_CFG_SECTION 0x3800
+#define mmQM_TENSOR_12_TPC6_EML_TPC_CFG_BASE 0x7FFFC41CA0ull
+#define QM_TENSOR_12_TPC6_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define QM_TENSOR_12_TPC6_EML_TPC_CFG_SECTION 0x3800
+#define mmQM_TENSOR_13_TPC6_EML_TPC_CFG_BASE 0x7FFFC41CD8ull
+#define QM_TENSOR_13_TPC6_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define QM_TENSOR_13_TPC6_EML_TPC_CFG_SECTION 0x3800
+#define mmQM_TENSOR_14_TPC6_EML_TPC_CFG_BASE 0x7FFFC41D10ull
+#define QM_TENSOR_14_TPC6_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define QM_TENSOR_14_TPC6_EML_TPC_CFG_SECTION 0x3800
+#define mmQM_TENSOR_15_TPC6_EML_TPC_CFG_BASE 0x7FFFC41D48ull
+#define QM_TENSOR_15_TPC6_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define QM_TENSOR_15_TPC6_EML_TPC_CFG_SECTION 0x3800
+#define mmQM_SYNC_OBJECT_TPC6_EML_TPC_CFG_BASE 0x7FFFC41D80ull
+#define QM_SYNC_OBJECT_TPC6_EML_TPC_CFG_MAX_OFFSET 0x8000
+#define QM_SYNC_OBJECT_TPC6_EML_TPC_CFG_SECTION 0x8000
+#define mmQM_TPC6_EML_TPC_CFG_BASE 0x7FFFC41D88ull
+#define QM_TPC6_EML_TPC_CFG_MAX_OFFSET 0xB800
+#define QM_TPC6_EML_TPC_CFG_SECTION 0x2780
+#define mmTPC6_EML_TPC_QM_BASE 0x7FFFC42000ull
+#define TPC6_EML_TPC_QM_MAX_OFFSET 0xD040
+#define TPC6_EML_TPC_QM_SECTION 0x1BD000
+#define mmTPC6_EML_CS_BASE 0x7FFFDFF000ull
+#define TPC6_EML_CS_MAX_OFFSET 0x1000
+#define TPC6_EML_CS_SECTION 0x1000
+#define mmTPC7_ROM_TABLE_BASE 0x7FFFE00000ull
+#define TPC7_ROM_TABLE_MAX_OFFSET 0x1000
+#define TPC7_ROM_TABLE_SECTION 0x1000
+#define mmTPC7_EML_SPMU_BASE 0x7FFFE01000ull
+#define TPC7_EML_SPMU_MAX_OFFSET 0x1000
+#define TPC7_EML_SPMU_SECTION 0x1000
+#define mmTPC7_EML_ETF_BASE 0x7FFFE02000ull
+#define TPC7_EML_ETF_MAX_OFFSET 0x1000
+#define TPC7_EML_ETF_SECTION 0x1000
+#define mmTPC7_EML_STM_BASE 0x7FFFE03000ull
+#define TPC7_EML_STM_MAX_OFFSET 0x1000
+#define TPC7_EML_STM_SECTION 0x2000
+#define mmTPC7_EML_CTI_BASE 0x7FFFE05000ull
+#define TPC7_EML_CTI_MAX_OFFSET 0x1000
+#define TPC7_EML_CTI_SECTION 0x1000
+#define mmTPC7_EML_FUNNEL_BASE 0x7FFFE06000ull
+#define TPC7_EML_FUNNEL_MAX_OFFSET 0x1000
+#define TPC7_EML_FUNNEL_SECTION 0x1000
+#define mmTPC7_EML_BUSMON_0_BASE 0x7FFFE07000ull
+#define TPC7_EML_BUSMON_0_MAX_OFFSET 0x1000
+#define TPC7_EML_BUSMON_0_SECTION 0x1000
+#define mmTPC7_EML_BUSMON_1_BASE 0x7FFFE08000ull
+#define TPC7_EML_BUSMON_1_MAX_OFFSET 0x1000
+#define TPC7_EML_BUSMON_1_SECTION 0x1000
+#define mmTPC7_EML_BUSMON_2_BASE 0x7FFFE09000ull
+#define TPC7_EML_BUSMON_2_MAX_OFFSET 0x1000
+#define TPC7_EML_BUSMON_2_SECTION 0x1000
+#define mmTPC7_EML_BUSMON_3_BASE 0x7FFFE0A000ull
+#define TPC7_EML_BUSMON_3_MAX_OFFSET 0x1000
+#define TPC7_EML_BUSMON_3_SECTION 0x36000
+#define mmTPC7_EML_CFG_BASE 0x7FFFE40000ull
+#define TPC7_EML_CFG_MAX_OFFSET 0x3380
+#define TPC7_EML_CFG_SECTION 0x1000
+#define mmTPC7_EML_TPC_CFG_BASE 0x7FFFE41000ull
+#define TPC7_EML_TPC_CFG_MAX_OFFSET 0xE400
+#define TPC7_EML_TPC_CFG_SECTION 0x4000
+#define mmKERNEL_TENSOR_0_TPC7_EML_TPC_CFG_BASE 0x7FFFE41400ull
+#define KERNEL_TENSOR_0_TPC7_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_0_TPC7_EML_TPC_CFG_SECTION 0x3800
+#define mmKERNEL_TENSOR_1_TPC7_EML_TPC_CFG_BASE 0x7FFFE41438ull
+#define KERNEL_TENSOR_1_TPC7_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_1_TPC7_EML_TPC_CFG_SECTION 0x3800
+#define mmKERNEL_TENSOR_2_TPC7_EML_TPC_CFG_BASE 0x7FFFE41470ull
+#define KERNEL_TENSOR_2_TPC7_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_2_TPC7_EML_TPC_CFG_SECTION 0x3800
+#define mmKERNEL_TENSOR_3_TPC7_EML_TPC_CFG_BASE 0x7FFFE414A8ull
+#define KERNEL_TENSOR_3_TPC7_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_3_TPC7_EML_TPC_CFG_SECTION 0x3800
+#define mmKERNEL_TENSOR_4_TPC7_EML_TPC_CFG_BASE 0x7FFFE414E0ull
+#define KERNEL_TENSOR_4_TPC7_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_4_TPC7_EML_TPC_CFG_SECTION 0x3800
+#define mmKERNEL_TENSOR_5_TPC7_EML_TPC_CFG_BASE 0x7FFFE41518ull
+#define KERNEL_TENSOR_5_TPC7_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_5_TPC7_EML_TPC_CFG_SECTION 0x3800
+#define mmKERNEL_TENSOR_6_TPC7_EML_TPC_CFG_BASE 0x7FFFE41550ull
+#define KERNEL_TENSOR_6_TPC7_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_6_TPC7_EML_TPC_CFG_SECTION 0x3800
+#define mmKERNEL_TENSOR_7_TPC7_EML_TPC_CFG_BASE 0x7FFFE41588ull
+#define KERNEL_TENSOR_7_TPC7_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_7_TPC7_EML_TPC_CFG_SECTION 0x3800
+#define mmKERNEL_TENSOR_8_TPC7_EML_TPC_CFG_BASE 0x7FFFE415C0ull
+#define KERNEL_TENSOR_8_TPC7_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_8_TPC7_EML_TPC_CFG_SECTION 0x3800
+#define mmKERNEL_TENSOR_9_TPC7_EML_TPC_CFG_BASE 0x7FFFE415F8ull
+#define KERNEL_TENSOR_9_TPC7_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_9_TPC7_EML_TPC_CFG_SECTION 0x3800
+#define mmKERNEL_TENSOR_10_TPC7_EML_TPC_CFG_BASE 0x7FFFE41630ull
+#define KERNEL_TENSOR_10_TPC7_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_10_TPC7_EML_TPC_CFG_SECTION 0x3800
+#define mmKERNEL_TENSOR_11_TPC7_EML_TPC_CFG_BASE 0x7FFFE41668ull
+#define KERNEL_TENSOR_11_TPC7_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_11_TPC7_EML_TPC_CFG_SECTION 0x3800
+#define mmKERNEL_TENSOR_12_TPC7_EML_TPC_CFG_BASE 0x7FFFE416A0ull
+#define KERNEL_TENSOR_12_TPC7_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_12_TPC7_EML_TPC_CFG_SECTION 0x3800
+#define mmKERNEL_TENSOR_13_TPC7_EML_TPC_CFG_BASE 0x7FFFE416D8ull
+#define KERNEL_TENSOR_13_TPC7_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_13_TPC7_EML_TPC_CFG_SECTION 0x3800
+#define mmKERNEL_TENSOR_14_TPC7_EML_TPC_CFG_BASE 0x7FFFE41710ull
+#define KERNEL_TENSOR_14_TPC7_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_14_TPC7_EML_TPC_CFG_SECTION 0x3800
+#define mmKERNEL_TENSOR_15_TPC7_EML_TPC_CFG_BASE 0x7FFFE41748ull
+#define KERNEL_TENSOR_15_TPC7_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define KERNEL_TENSOR_15_TPC7_EML_TPC_CFG_SECTION 0x3800
+#define mmKERNEL_SYNC_OBJECT_TPC7_EML_TPC_CFG_BASE 0x7FFFE41780ull
+#define KERNEL_SYNC_OBJECT_TPC7_EML_TPC_CFG_MAX_OFFSET 0x8000
+#define KERNEL_SYNC_OBJECT_TPC7_EML_TPC_CFG_SECTION 0x8000
+#define mmKERNEL_TPC7_EML_TPC_CFG_BASE 0x7FFFE41788ull
+#define KERNEL_TPC7_EML_TPC_CFG_MAX_OFFSET 0xB800
+#define KERNEL_TPC7_EML_TPC_CFG_SECTION 0x2780
+#define mmQM_TENSOR_0_TPC7_EML_TPC_CFG_BASE 0x7FFFE41A00ull
+#define QM_TENSOR_0_TPC7_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define QM_TENSOR_0_TPC7_EML_TPC_CFG_SECTION 0x3800
+#define mmQM_TENSOR_1_TPC7_EML_TPC_CFG_BASE 0x7FFFE41A38ull
+#define QM_TENSOR_1_TPC7_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define QM_TENSOR_1_TPC7_EML_TPC_CFG_SECTION 0x3800
+#define mmQM_TENSOR_2_TPC7_EML_TPC_CFG_BASE 0x7FFFE41A70ull
+#define QM_TENSOR_2_TPC7_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define QM_TENSOR_2_TPC7_EML_TPC_CFG_SECTION 0x3800
+#define mmQM_TENSOR_3_TPC7_EML_TPC_CFG_BASE 0x7FFFE41AA8ull
+#define QM_TENSOR_3_TPC7_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define QM_TENSOR_3_TPC7_EML_TPC_CFG_SECTION 0x3800
+#define mmQM_TENSOR_4_TPC7_EML_TPC_CFG_BASE 0x7FFFE41AE0ull
+#define QM_TENSOR_4_TPC7_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define QM_TENSOR_4_TPC7_EML_TPC_CFG_SECTION 0x3800
+#define mmQM_TENSOR_5_TPC7_EML_TPC_CFG_BASE 0x7FFFE41B18ull
+#define QM_TENSOR_5_TPC7_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define QM_TENSOR_5_TPC7_EML_TPC_CFG_SECTION 0x3800
+#define mmQM_TENSOR_6_TPC7_EML_TPC_CFG_BASE 0x7FFFE41B50ull
+#define QM_TENSOR_6_TPC7_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define QM_TENSOR_6_TPC7_EML_TPC_CFG_SECTION 0x3800
+#define mmQM_TENSOR_7_TPC7_EML_TPC_CFG_BASE 0x7FFFE41B88ull
+#define QM_TENSOR_7_TPC7_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define QM_TENSOR_7_TPC7_EML_TPC_CFG_SECTION 0x3800
+#define mmQM_TENSOR_8_TPC7_EML_TPC_CFG_BASE 0x7FFFE41BC0ull
+#define QM_TENSOR_8_TPC7_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define QM_TENSOR_8_TPC7_EML_TPC_CFG_SECTION 0x3800
+#define mmQM_TENSOR_9_TPC7_EML_TPC_CFG_BASE 0x7FFFE41BF8ull
+#define QM_TENSOR_9_TPC7_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define QM_TENSOR_9_TPC7_EML_TPC_CFG_SECTION 0x3800
+#define mmQM_TENSOR_10_TPC7_EML_TPC_CFG_BASE 0x7FFFE41C30ull
+#define QM_TENSOR_10_TPC7_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define QM_TENSOR_10_TPC7_EML_TPC_CFG_SECTION 0x3800
+#define mmQM_TENSOR_11_TPC7_EML_TPC_CFG_BASE 0x7FFFE41C68ull
+#define QM_TENSOR_11_TPC7_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define QM_TENSOR_11_TPC7_EML_TPC_CFG_SECTION 0x3800
+#define mmQM_TENSOR_12_TPC7_EML_TPC_CFG_BASE 0x7FFFE41CA0ull
+#define QM_TENSOR_12_TPC7_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define QM_TENSOR_12_TPC7_EML_TPC_CFG_SECTION 0x3800
+#define mmQM_TENSOR_13_TPC7_EML_TPC_CFG_BASE 0x7FFFE41CD8ull
+#define QM_TENSOR_13_TPC7_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define QM_TENSOR_13_TPC7_EML_TPC_CFG_SECTION 0x3800
+#define mmQM_TENSOR_14_TPC7_EML_TPC_CFG_BASE 0x7FFFE41D10ull
+#define QM_TENSOR_14_TPC7_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define QM_TENSOR_14_TPC7_EML_TPC_CFG_SECTION 0x3800
+#define mmQM_TENSOR_15_TPC7_EML_TPC_CFG_BASE 0x7FFFE41D48ull
+#define QM_TENSOR_15_TPC7_EML_TPC_CFG_MAX_OFFSET 0x3800
+#define QM_TENSOR_15_TPC7_EML_TPC_CFG_SECTION 0x3800
+#define mmQM_SYNC_OBJECT_TPC7_EML_TPC_CFG_BASE 0x7FFFE41D80ull
+#define QM_SYNC_OBJECT_TPC7_EML_TPC_CFG_MAX_OFFSET 0x8000
+#define QM_SYNC_OBJECT_TPC7_EML_TPC_CFG_SECTION 0x8000
+#define mmQM_TPC7_EML_TPC_CFG_BASE 0x7FFFE41D88ull
+#define QM_TPC7_EML_TPC_CFG_MAX_OFFSET 0xB800
+#define QM_TPC7_EML_TPC_CFG_SECTION 0x2780
+#define mmTPC7_EML_TPC_QM_BASE 0x7FFFE42000ull
+#define TPC7_EML_TPC_QM_MAX_OFFSET 0xD040
+#define TPC7_EML_TPC_QM_SECTION 0x1BD000
+#define mmTPC7_EML_CS_BASE 0x7FFFFFF000ull
+#define TPC7_EML_CS_MAX_OFFSET 0x1000
+
+#endif /* GAUDI_BLOCKS_H_ */
diff --git a/drivers/accel/habanalabs/include/gaudi/asic_reg/gaudi_regs.h b/drivers/accel/habanalabs/include/gaudi/asic_reg/gaudi_regs.h
new file mode 100644
index 0000000000..23ee8691db
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi/asic_reg/gaudi_regs.h
@@ -0,0 +1,325 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2016-2020 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+#ifndef ASIC_REG_GAUDI_REGS_H_
+#define ASIC_REG_GAUDI_REGS_H_
+
+#include "gaudi_blocks.h"
+#include "psoc_global_conf_regs.h"
+#include "psoc_timestamp_regs.h"
+#include "cpu_if_regs.h"
+#include "mmu_up_regs.h"
+#include "stlb_regs.h"
+#include "dma0_qm_regs.h"
+#include "dma1_qm_regs.h"
+#include "dma2_qm_regs.h"
+#include "dma3_qm_regs.h"
+#include "dma4_qm_regs.h"
+#include "dma5_qm_regs.h"
+#include "dma6_qm_regs.h"
+#include "dma7_qm_regs.h"
+#include "dma0_core_regs.h"
+#include "dma1_core_regs.h"
+#include "dma2_core_regs.h"
+#include "dma3_core_regs.h"
+#include "dma4_core_regs.h"
+#include "dma5_core_regs.h"
+#include "dma6_core_regs.h"
+#include "dma7_core_regs.h"
+#include "mme0_ctrl_regs.h"
+#include "mme1_ctrl_regs.h"
+#include "mme2_ctrl_regs.h"
+#include "mme3_ctrl_regs.h"
+#include "mme0_qm_regs.h"
+#include "mme2_qm_regs.h"
+#include "tpc0_cfg_regs.h"
+#include "tpc1_cfg_regs.h"
+#include "tpc2_cfg_regs.h"
+#include "tpc3_cfg_regs.h"
+#include "tpc4_cfg_regs.h"
+#include "tpc5_cfg_regs.h"
+#include "tpc6_cfg_regs.h"
+#include "tpc7_cfg_regs.h"
+#include "tpc0_qm_regs.h"
+#include "tpc1_qm_regs.h"
+#include "tpc2_qm_regs.h"
+#include "tpc3_qm_regs.h"
+#include "tpc4_qm_regs.h"
+#include "tpc5_qm_regs.h"
+#include "tpc6_qm_regs.h"
+#include "tpc7_qm_regs.h"
+#include "dma_if_e_n_down_ch0_regs.h"
+#include "dma_if_e_n_down_ch1_regs.h"
+#include "dma_if_e_s_down_ch0_regs.h"
+#include "dma_if_e_s_down_ch1_regs.h"
+#include "dma_if_w_n_down_ch0_regs.h"
+#include "dma_if_w_n_down_ch1_regs.h"
+#include "dma_if_w_s_down_ch0_regs.h"
+#include "dma_if_w_s_down_ch1_regs.h"
+#include "dma_if_e_n_regs.h"
+#include "dma_if_e_s_regs.h"
+#include "dma_if_w_n_regs.h"
+#include "dma_if_w_s_regs.h"
+#include "nif_rtr_ctrl_0_regs.h"
+#include "nif_rtr_ctrl_1_regs.h"
+#include "nif_rtr_ctrl_2_regs.h"
+#include "nif_rtr_ctrl_3_regs.h"
+#include "nif_rtr_ctrl_4_regs.h"
+#include "nif_rtr_ctrl_5_regs.h"
+#include "nif_rtr_ctrl_6_regs.h"
+#include "nif_rtr_ctrl_7_regs.h"
+#include "sif_rtr_ctrl_0_regs.h"
+#include "sif_rtr_ctrl_1_regs.h"
+#include "sif_rtr_ctrl_2_regs.h"
+#include "sif_rtr_ctrl_3_regs.h"
+#include "sif_rtr_ctrl_4_regs.h"
+#include "sif_rtr_ctrl_5_regs.h"
+#include "sif_rtr_ctrl_6_regs.h"
+#include "sif_rtr_ctrl_7_regs.h"
+#include "psoc_etr_regs.h"
+#include "psoc_cpu_pll_regs.h"
+
+#include "dma0_qm_masks.h"
+#include "mme0_qm_masks.h"
+#include "tpc0_qm_masks.h"
+#include "dma0_core_masks.h"
+#include "tpc0_cfg_masks.h"
+#include "psoc_global_conf_masks.h"
+
+#include "nic0_qm0_regs.h"
+#include "nic1_qm0_regs.h"
+#include "nic2_qm0_regs.h"
+#include "nic3_qm0_regs.h"
+#include "nic4_qm0_regs.h"
+#include "nic0_qm1_regs.h"
+#include "nic1_qm1_regs.h"
+#include "nic2_qm1_regs.h"
+#include "nic3_qm1_regs.h"
+#include "nic4_qm1_regs.h"
+
+#include "nic0_qm0_masks.h"
+
+#define GAUDI_ECC_MEM_SEL_OFFSET 0xF18
+#define GAUDI_ECC_ADDRESS_OFFSET 0xF1C
+#define GAUDI_ECC_SYNDROME_OFFSET 0xF20
+#define GAUDI_ECC_MEM_INFO_CLR_OFFSET 0xF28
+#define GAUDI_ECC_MEM_INFO_CLR_SERR_MASK BIT(8)
+#define GAUDI_ECC_MEM_INFO_CLR_DERR_MASK BIT(9)
+#define GAUDI_ECC_SERR0_OFFSET 0xF30
+#define GAUDI_ECC_DERR0_OFFSET 0xF40
+
+#define mmSYNC_MNGR_W_S_SYNC_MNGR_OBJS_SOB_OBJ_0 0x492000
+#define mmSYNC_MNGR_W_S_SYNC_MNGR_OBJS_MON_PAY_ADDRL_0 0x494000
+#define mmSYNC_MNGR_W_S_SYNC_MNGR_OBJS_MON_PAY_ADDRH_0 0x494800
+#define mmSYNC_MNGR_W_S_SYNC_MNGR_OBJS_MON_PAY_DATA_0 0x495000
+#define mmSYNC_MNGR_W_S_SYNC_MNGR_OBJS_MON_ARM_0 0x495800
+#define mmSYNC_MNGR_W_S_SYNC_MNGR_OBJS_MON_STATUS_0 0x496000
+#define mmSYNC_MNGR_E_S_SYNC_MNGR_OBJS_SOB_OBJ_0 0x4B2000
+#define mmSYNC_MNGR_E_S_SYNC_MNGR_OBJS_MON_STATUS_0 0x4B6000
+#define mmSYNC_MNGR_W_N_SYNC_MNGR_OBJS_SOB_OBJ_0 0x4D2000
+#define mmSYNC_MNGR_W_N_SYNC_MNGR_OBJS_MON_STATUS_0 0x4D6000
+#define mmSYNC_MNGR_E_N_SYNC_MNGR_OBJS_SOB_OBJ_0 0x4F2000
+#define mmSYNC_MNGR_E_N_SYNC_MNGR_OBJS_SOB_OBJ_1 0x4F2004
+#define mmSYNC_MNGR_E_N_SYNC_MNGR_OBJS_SOB_OBJ_2047 0x4F3FFC
+#define mmSYNC_MNGR_E_N_SYNC_MNGR_OBJS_MON_PAY_ADDRL_0 0x4F4000
+#define mmSYNC_MNGR_E_N_SYNC_MNGR_OBJS_MON_PAY_ADDRH_0 0x4F4800
+#define mmSYNC_MNGR_E_N_SYNC_MNGR_OBJS_MON_PAY_DATA_0 0x4F5000
+#define mmSYNC_MNGR_E_N_SYNC_MNGR_OBJS_MON_ARM_0 0x4F5800
+#define mmSYNC_MNGR_E_N_SYNC_MNGR_OBJS_MON_STATUS_0 0x4F6000
+#define mmSYNC_MNGR_E_N_SYNC_MNGR_OBJS_MON_STATUS_511 0x4F67FC
+
+#define mmSIF_RTR_0_LBW_RANGE_PROT_HIT_AW 0x300400
+#define mmSIF_RTR_1_LBW_RANGE_PROT_HIT_AW 0x310400
+#define mmSIF_RTR_2_LBW_RANGE_PROT_HIT_AW 0x320400
+#define mmSIF_RTR_3_LBW_RANGE_PROT_HIT_AW 0x330400
+#define mmSIF_RTR_4_LBW_RANGE_PROT_HIT_AW 0x340400
+#define mmSIF_RTR_5_LBW_RANGE_PROT_HIT_AW 0x350400
+#define mmSIF_RTR_6_LBW_RANGE_PROT_HIT_AW 0x360400
+#define mmSIF_RTR_7_LBW_RANGE_PROT_HIT_AW 0x370400
+
+#define mmSIF_RTR_0_LBW_RANGE_PROT_HIT_AR 0x300490
+#define mmSIF_RTR_1_LBW_RANGE_PROT_HIT_AR 0x310490
+#define mmSIF_RTR_2_LBW_RANGE_PROT_HIT_AR 0x320490
+#define mmSIF_RTR_3_LBW_RANGE_PROT_HIT_AR 0x330490
+#define mmSIF_RTR_4_LBW_RANGE_PROT_HIT_AR 0x340490
+#define mmSIF_RTR_5_LBW_RANGE_PROT_HIT_AR 0x350490
+#define mmSIF_RTR_6_LBW_RANGE_PROT_HIT_AR 0x360490
+#define mmSIF_RTR_7_LBW_RANGE_PROT_HIT_AR 0x370490
+
+#define mmSIF_RTR_0_LBW_RANGE_PROT_MIN_AW_0 0x300410
+#define mmSIF_RTR_1_LBW_RANGE_PROT_MIN_AW_0 0x310410
+#define mmSIF_RTR_2_LBW_RANGE_PROT_MIN_AW_0 0x320410
+#define mmSIF_RTR_3_LBW_RANGE_PROT_MIN_AW_0 0x330410
+#define mmSIF_RTR_4_LBW_RANGE_PROT_MIN_AW_0 0x340410
+#define mmSIF_RTR_5_LBW_RANGE_PROT_MIN_AW_0 0x350410
+#define mmSIF_RTR_6_LBW_RANGE_PROT_MIN_AW_0 0x360410
+#define mmSIF_RTR_7_LBW_RANGE_PROT_MIN_AW_0 0x370410
+
+#define mmSIF_RTR_0_LBW_RANGE_PROT_MAX_AW_0 0x300450
+#define mmSIF_RTR_1_LBW_RANGE_PROT_MAX_AW_0 0x310450
+#define mmSIF_RTR_2_LBW_RANGE_PROT_MAX_AW_0 0x320450
+#define mmSIF_RTR_3_LBW_RANGE_PROT_MAX_AW_0 0x330450
+#define mmSIF_RTR_4_LBW_RANGE_PROT_MAX_AW_0 0x340450
+#define mmSIF_RTR_5_LBW_RANGE_PROT_MAX_AW_0 0x350450
+#define mmSIF_RTR_6_LBW_RANGE_PROT_MAX_AW_0 0x360450
+#define mmSIF_RTR_7_LBW_RANGE_PROT_MAX_AW_0 0x370450
+
+#define mmSIF_RTR_0_LBW_RANGE_PROT_MIN_AR_0 0x3004A0
+#define mmSIF_RTR_1_LBW_RANGE_PROT_MIN_AR_0 0x3104A0
+#define mmSIF_RTR_2_LBW_RANGE_PROT_MIN_AR_0 0x3204A0
+#define mmSIF_RTR_3_LBW_RANGE_PROT_MIN_AR_0 0x3304A0
+#define mmSIF_RTR_4_LBW_RANGE_PROT_MIN_AR_0 0x3404A0
+#define mmSIF_RTR_5_LBW_RANGE_PROT_MIN_AR_0 0x3504A0
+#define mmSIF_RTR_6_LBW_RANGE_PROT_MIN_AR_0 0x3604A0
+#define mmSIF_RTR_7_LBW_RANGE_PROT_MIN_AR_0 0x3704A0
+
+#define mmSIF_RTR_0_LBW_RANGE_PROT_MAX_AR_0 0x3004E0
+#define mmSIF_RTR_1_LBW_RANGE_PROT_MAX_AR_0 0x3104E0
+#define mmSIF_RTR_2_LBW_RANGE_PROT_MAX_AR_0 0x3204E0
+#define mmSIF_RTR_3_LBW_RANGE_PROT_MAX_AR_0 0x3304E0
+#define mmSIF_RTR_4_LBW_RANGE_PROT_MAX_AR_0 0x3404E0
+#define mmSIF_RTR_5_LBW_RANGE_PROT_MAX_AR_0 0x3504E0
+#define mmSIF_RTR_6_LBW_RANGE_PROT_MAX_AR_0 0x3604E0
+#define mmSIF_RTR_7_LBW_RANGE_PROT_MAX_AR_0 0x3704E0
+
+#define mmNIF_RTR_0_LBW_RANGE_PROT_HIT_AW 0x380400
+#define mmNIF_RTR_1_LBW_RANGE_PROT_HIT_AW 0x390400
+#define mmNIF_RTR_2_LBW_RANGE_PROT_HIT_AW 0x3A0400
+#define mmNIF_RTR_3_LBW_RANGE_PROT_HIT_AW 0x3B0400
+#define mmNIF_RTR_4_LBW_RANGE_PROT_HIT_AW 0x3C0400
+#define mmNIF_RTR_5_LBW_RANGE_PROT_HIT_AW 0x3D0400
+#define mmNIF_RTR_6_LBW_RANGE_PROT_HIT_AW 0x3E0400
+#define mmNIF_RTR_7_LBW_RANGE_PROT_HIT_AW 0x3F0400
+
+#define mmNIF_RTR_0_LBW_RANGE_PROT_HIT_AR 0x380490
+#define mmNIF_RTR_1_LBW_RANGE_PROT_HIT_AR 0x390490
+#define mmNIF_RTR_2_LBW_RANGE_PROT_HIT_AR 0x3A0490
+#define mmNIF_RTR_3_LBW_RANGE_PROT_HIT_AR 0x3B0490
+#define mmNIF_RTR_4_LBW_RANGE_PROT_HIT_AR 0x3C0490
+#define mmNIF_RTR_5_LBW_RANGE_PROT_HIT_AR 0x3D0490
+#define mmNIF_RTR_6_LBW_RANGE_PROT_HIT_AR 0x3E0490
+#define mmNIF_RTR_7_LBW_RANGE_PROT_HIT_AR 0x3F0490
+
+#define mmNIF_RTR_0_LBW_RANGE_PROT_MIN_AW_0 0x380410
+#define mmNIF_RTR_1_LBW_RANGE_PROT_MIN_AW_0 0x390410
+#define mmNIF_RTR_2_LBW_RANGE_PROT_MIN_AW_0 0x3A0410
+#define mmNIF_RTR_3_LBW_RANGE_PROT_MIN_AW_0 0x3B0410
+#define mmNIF_RTR_4_LBW_RANGE_PROT_MIN_AW_0 0x3C0410
+#define mmNIF_RTR_5_LBW_RANGE_PROT_MIN_AW_0 0x3D0410
+#define mmNIF_RTR_6_LBW_RANGE_PROT_MIN_AW_0 0x3E0410
+#define mmNIF_RTR_7_LBW_RANGE_PROT_MIN_AW_0 0x3F0410
+
+#define mmNIF_RTR_0_LBW_RANGE_PROT_MAX_AW_0 0x380450
+#define mmNIF_RTR_1_LBW_RANGE_PROT_MAX_AW_0 0x390450
+#define mmNIF_RTR_2_LBW_RANGE_PROT_MAX_AW_0 0x3A0450
+#define mmNIF_RTR_3_LBW_RANGE_PROT_MAX_AW_0 0x3B0450
+#define mmNIF_RTR_4_LBW_RANGE_PROT_MAX_AW_0 0x3C0450
+#define mmNIF_RTR_5_LBW_RANGE_PROT_MAX_AW_0 0x3D0450
+#define mmNIF_RTR_6_LBW_RANGE_PROT_MAX_AW_0 0x3E0450
+#define mmNIF_RTR_7_LBW_RANGE_PROT_MAX_AW_0 0x3F0450
+
+#define mmNIF_RTR_0_LBW_RANGE_PROT_MIN_AR_0 0x3804A0
+#define mmNIF_RTR_1_LBW_RANGE_PROT_MIN_AR_0 0x3904A0
+#define mmNIF_RTR_2_LBW_RANGE_PROT_MIN_AR_0 0x3A04A0
+#define mmNIF_RTR_3_LBW_RANGE_PROT_MIN_AR_0 0x3B04A0
+#define mmNIF_RTR_4_LBW_RANGE_PROT_MIN_AR_0 0x3C04A0
+#define mmNIF_RTR_5_LBW_RANGE_PROT_MIN_AR_0 0x3D04A0
+#define mmNIF_RTR_6_LBW_RANGE_PROT_MIN_AR_0 0x3E04A0
+#define mmNIF_RTR_7_LBW_RANGE_PROT_MIN_AR_0 0x3F04A0
+
+#define mmNIF_RTR_0_LBW_RANGE_PROT_MAX_AR_0 0x3804E0
+#define mmNIF_RTR_1_LBW_RANGE_PROT_MAX_AR_0 0x3904E0
+#define mmNIF_RTR_2_LBW_RANGE_PROT_MAX_AR_0 0x3A04E0
+#define mmNIF_RTR_3_LBW_RANGE_PROT_MAX_AR_0 0x3B04E0
+#define mmNIF_RTR_4_LBW_RANGE_PROT_MAX_AR_0 0x3C04E0
+#define mmNIF_RTR_5_LBW_RANGE_PROT_MAX_AR_0 0x3D04E0
+#define mmNIF_RTR_6_LBW_RANGE_PROT_MAX_AR_0 0x3E04E0
+#define mmNIF_RTR_7_LBW_RANGE_PROT_MAX_AR_0 0x3F04E0
+
+#define mmDMA_IF_W_S_DOWN_RSP_MID_WGHT_0 0x489030
+#define mmDMA_IF_W_S_DOWN_RSP_MID_WGHT_1 0x489034
+
+#define mmDMA_IF_E_S_DOWN_RSP_MID_WGHT_0 0x4A9030
+#define mmDMA_IF_E_S_DOWN_RSP_MID_WGHT_1 0x4A9034
+
+#define mmDMA_IF_W_N_DOWN_RSP_MID_WGHT_0 0x4C9030
+#define mmDMA_IF_W_N_DOWN_RSP_MID_WGHT_1 0x4C9034
+
+#define mmDMA_IF_E_N_DOWN_RSP_MID_WGHT_0 0x4E9030
+#define mmDMA_IF_E_N_DOWN_RSP_MID_WGHT_1 0x4E9034
+
+#define mmMME1_QM_GLBL_CFG0 0xE8000
+#define mmMME1_QM_GLBL_STS0 0xE8038
+
+#define mmMME0_SBAB_SB_STALL 0x4002C
+#define mmMME0_SBAB_ARUSER0 0x40034
+#define mmMME0_SBAB_ARUSER1 0x40038
+#define mmMME0_SBAB_PROT 0x40050
+
+#define mmMME1_SBAB_SB_STALL 0xC002C
+#define mmMME1_SBAB_ARUSER0 0xC0034
+#define mmMME1_SBAB_ARUSER1 0xC0038
+#define mmMME1_SBAB_PROT 0xC0050
+
+#define mmMME2_SBAB_SB_STALL 0x14002C
+#define mmMME2_SBAB_ARUSER0 0x140034
+#define mmMME2_SBAB_ARUSER1 0x140038
+#define mmMME2_SBAB_PROT 0x140050
+
+#define mmMME3_SBAB_SB_STALL 0x1C002C
+#define mmMME3_SBAB_ARUSER0 0x1C0034
+#define mmMME3_SBAB_ARUSER1 0x1C0038
+#define mmMME3_SBAB_PROT 0x1C0050
+
+#define mmMME0_ACC_ACC_STALL 0x20028
+#define mmMME0_ACC_WBC 0x20038
+#define mmMME0_ACC_PROT 0x20050
+
+#define mmMME1_ACC_ACC_STALL 0xA0028
+#define mmMME1_ACC_WBC 0xA0038
+#define mmMME1_ACC_PROT 0xA0050
+
+#define mmMME2_ACC_ACC_STALL 0x120028
+#define mmMME2_ACC_WBC 0x120038
+#define mmMME2_ACC_PROT 0x120050
+
+#define mmMME3_ACC_ACC_STALL 0x1A0028
+#define mmMME3_ACC_WBC 0x1A0038
+#define mmMME3_ACC_PROT 0x1A0050
+
+#define mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR 0x800040
+
+#define mmPSOC_EFUSE_READ 0xC4A000
+#define mmPSOC_EFUSE_DATA_0 0xC4A080
+
+#define mmPCIE_WRAP_MAX_OUTSTAND 0xC01B20
+#define mmPCIE_WRAP_LBW_PROT_OVR 0xC01B48
+#define mmPCIE_WRAP_HBW_DRAIN_CFG 0xC01D54
+#define mmPCIE_WRAP_LBW_DRAIN_CFG 0xC01D5C
+
+#define mmPCIE_MSI_INTR_0 0xC13000
+
+#define mmPCIE_DBI_DEVICE_ID_VENDOR_ID_REG 0xC02000
+
+#define mmPCIE_AUX_FLR_CTRL 0xC07394
+#define mmPCIE_AUX_DBI 0xC07490
+
+#define mmPCIE_CORE_MSI_REQ 0xC04100
+
+#define mmPSOC_PCI_PLL_NR 0xC72100
+#define mmSRAM_W_PLL_NR 0x4C8100
+#define mmPSOC_HBM_PLL_NR 0xC74100
+#define mmNIC0_PLL_NR 0xCF9100
+#define mmDMA_W_PLL_NR 0x487100
+#define mmMESH_W_PLL_NR 0x4C7100
+#define mmPSOC_MME_PLL_NR 0xC71100
+#define mmPSOC_TPC_PLL_NR 0xC73100
+#define mmIF_W_PLL_NR 0x488100
+
+#define mmPCIE_WRAP_RR_ELBI_RD_SEC_REG_CTRL 0xC01208
+
+#endif /* ASIC_REG_GAUDI_REGS_H_ */
diff --git a/drivers/accel/habanalabs/include/gaudi/asic_reg/mme0_ctrl_regs.h b/drivers/accel/habanalabs/include/gaudi/asic_reg/mme0_ctrl_regs.h
new file mode 100644
index 0000000000..083d073a01
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi/asic_reg/mme0_ctrl_regs.h
@@ -0,0 +1,1456 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2016-2018 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ ** DO NOT EDIT BELOW **
+ ************************************/
+
+#ifndef ASIC_REG_MME0_CTRL_REGS_H_
+#define ASIC_REG_MME0_CTRL_REGS_H_
+
+/*
+ *****************************************
+ * MME0_CTRL (Prototype: MME)
+ *****************************************
+ */
+
+#define mmMME0_CTRL_ARCH_STATUS 0x60000
+
+#define mmMME0_CTRL_ARCH_BASE_ADDR_HIGH_S 0x60008
+
+#define mmMME0_CTRL_ARCH_BASE_ADDR_HIGH_L 0x6000C
+
+#define mmMME0_CTRL_ARCH_BASE_ADDR_HIGH_O 0x60010
+
+#define mmMME0_CTRL_ARCH_BASE_ADDR_LOW_S 0x60014
+
+#define mmMME0_CTRL_ARCH_BASE_ADDR_LOW_L 0x60018
+
+#define mmMME0_CTRL_ARCH_BASE_ADDR_LOW_O 0x6001C
+
+#define mmMME0_CTRL_ARCH_HEADER_LOW 0x60020
+
+#define mmMME0_CTRL_ARCH_HEADER_HIGH 0x60024
+
+#define mmMME0_CTRL_ARCH_CONV_KERNEL_SIZE_MINUS_1 0x60028
+
+#define mmMME0_CTRL_ARCH_CONV_ASSOCIATED_DIMS_LOW 0x6002C
+
+#define mmMME0_CTRL_ARCH_CONV_ASSOCIATED_DIMS_HIGH 0x60030
+
+#define mmMME0_CTRL_ARCH_NUM_ITERATIONS_MINUS_1 0x60034
+
+#define mmMME0_CTRL_ARCH_OUTER_LOOP 0x60038
+
+#define mmMME0_CTRL_ARCH_TENSOR_S_VALID_ELEMENTS_0 0x6003C
+
+#define mmMME0_CTRL_ARCH_TENSOR_S_VALID_ELEMENTS_1 0x60040
+
+#define mmMME0_CTRL_ARCH_TENSOR_S_VALID_ELEMENTS_2 0x60044
+
+#define mmMME0_CTRL_ARCH_TENSOR_S_VALID_ELEMENTS_3 0x60048
+
+#define mmMME0_CTRL_ARCH_TENSOR_S_VALID_ELEMENTS_4 0x6004C
+
+#define mmMME0_CTRL_ARCH_TENSOR_S_LOOP_STRIDE_0 0x60050
+
+#define mmMME0_CTRL_ARCH_TENSOR_S_LOOP_STRIDE_1 0x60054
+
+#define mmMME0_CTRL_ARCH_TENSOR_S_LOOP_STRIDE_2 0x60058
+
+#define mmMME0_CTRL_ARCH_TENSOR_S_LOOP_STRIDE_3 0x6005C
+
+#define mmMME0_CTRL_ARCH_TENSOR_S_LOOP_STRIDE_4 0x60060
+
+#define mmMME0_CTRL_ARCH_TENSOR_S_ROI_SIZE_0 0x60064
+
+#define mmMME0_CTRL_ARCH_TENSOR_S_ROI_SIZE_1 0x60068
+
+#define mmMME0_CTRL_ARCH_TENSOR_S_ROI_SIZE_2 0x6006C
+
+#define mmMME0_CTRL_ARCH_TENSOR_S_ROI_SIZE_3 0x60070
+
+#define mmMME0_CTRL_ARCH_TENSOR_S_SPATIAL_STRIDES_0 0x60074
+
+#define mmMME0_CTRL_ARCH_TENSOR_S_SPATIAL_STRIDES_1 0x60078
+
+#define mmMME0_CTRL_ARCH_TENSOR_S_SPATIAL_STRIDES_2 0x6007C
+
+#define mmMME0_CTRL_ARCH_TENSOR_S_SPATIAL_STRIDES_3 0x60080
+
+#define mmMME0_CTRL_ARCH_TENSOR_S_SPATIAL_SIZE_MINUS_1 0x60084
+
+#define mmMME0_CTRL_ARCH_AGU_S_ROI_BASE_OFFSET_0 0x60088
+
+#define mmMME0_CTRL_ARCH_AGU_S_ROI_BASE_OFFSET_1 0x6008C
+
+#define mmMME0_CTRL_ARCH_AGU_S_ROI_BASE_OFFSET_2 0x60090
+
+#define mmMME0_CTRL_ARCH_AGU_S_ROI_BASE_OFFSET_3 0x60094
+
+#define mmMME0_CTRL_ARCH_AGU_S_ROI_BASE_OFFSET_4 0x60098
+
+#define mmMME0_CTRL_ARCH_AGU_S_START_OFFSET_0 0x6009C
+
+#define mmMME0_CTRL_ARCH_AGU_S_START_OFFSET_1 0x600A0
+
+#define mmMME0_CTRL_ARCH_AGU_S_START_OFFSET_2 0x600A4
+
+#define mmMME0_CTRL_ARCH_AGU_S_START_OFFSET_3 0x600A8
+
+#define mmMME0_CTRL_ARCH_TENSOR_L_VALID_ELEMENTS_0 0x600AC
+
+#define mmMME0_CTRL_ARCH_TENSOR_L_VALID_ELEMENTS_1 0x600B0
+
+#define mmMME0_CTRL_ARCH_TENSOR_L_VALID_ELEMENTS_2 0x600B4
+
+#define mmMME0_CTRL_ARCH_TENSOR_L_VALID_ELEMENTS_3 0x600B8
+
+#define mmMME0_CTRL_ARCH_TENSOR_L_VALID_ELEMENTS_4 0x600BC
+
+#define mmMME0_CTRL_ARCH_TENSOR_L_LOOP_STRIDE_0 0x600C0
+
+#define mmMME0_CTRL_ARCH_TENSOR_L_LOOP_STRIDE_1 0x600C4
+
+#define mmMME0_CTRL_ARCH_TENSOR_L_LOOP_STRIDE_2 0x600C8
+
+#define mmMME0_CTRL_ARCH_TENSOR_L_LOOP_STRIDE_3 0x600CC
+
+#define mmMME0_CTRL_ARCH_TENSOR_L_LOOP_STRIDE_4 0x600D0
+
+#define mmMME0_CTRL_ARCH_TENSOR_L_ROI_SIZE_0 0x600D4
+
+#define mmMME0_CTRL_ARCH_TENSOR_L_ROI_SIZE_1 0x600D8
+
+#define mmMME0_CTRL_ARCH_TENSOR_L_ROI_SIZE_2 0x600DC
+
+#define mmMME0_CTRL_ARCH_TENSOR_L_ROI_SIZE_3 0x600E0
+
+#define mmMME0_CTRL_ARCH_TENSOR_L_SPATIAL_STRIDES_0 0x600E4
+
+#define mmMME0_CTRL_ARCH_TENSOR_L_SPATIAL_STRIDES_1 0x600E8
+
+#define mmMME0_CTRL_ARCH_TENSOR_L_SPATIAL_STRIDES_2 0x600EC
+
+#define mmMME0_CTRL_ARCH_TENSOR_L_SPATIAL_STRIDES_3 0x600F0
+
+#define mmMME0_CTRL_ARCH_TENSOR_L_SPATIAL_SIZE_MINUS_1 0x600F4
+
+#define mmMME0_CTRL_ARCH_AGU_L_LOCAL_ROI_BASE_OFFSET_0 0x600F8
+
+#define mmMME0_CTRL_ARCH_AGU_L_LOCAL_ROI_BASE_OFFSET_1 0x600FC
+
+#define mmMME0_CTRL_ARCH_AGU_L_LOCAL_ROI_BASE_OFFSET_2 0x60100
+
+#define mmMME0_CTRL_ARCH_AGU_L_LOCAL_ROI_BASE_OFFSET_3 0x60104
+
+#define mmMME0_CTRL_ARCH_AGU_L_LOCAL_ROI_BASE_OFFSET_4 0x60108
+
+#define mmMME0_CTRL_ARCH_AGU_L_LOCAL_START_OFFSET_0 0x6010C
+
+#define mmMME0_CTRL_ARCH_AGU_L_LOCAL_START_OFFSET_1 0x60110
+
+#define mmMME0_CTRL_ARCH_AGU_L_LOCAL_START_OFFSET_2 0x60114
+
+#define mmMME0_CTRL_ARCH_AGU_L_LOCAL_START_OFFSET_3 0x60118
+
+#define mmMME0_CTRL_ARCH_AGU_L_REMOTE_ROI_BASE_OFFSET_0 0x6011C
+
+#define mmMME0_CTRL_ARCH_AGU_L_REMOTE_ROI_BASE_OFFSET_1 0x60120
+
+#define mmMME0_CTRL_ARCH_AGU_L_REMOTE_ROI_BASE_OFFSET_2 0x60124
+
+#define mmMME0_CTRL_ARCH_AGU_L_REMOTE_ROI_BASE_OFFSET_3 0x60128
+
+#define mmMME0_CTRL_ARCH_AGU_L_REMOTE_ROI_BASE_OFFSET_4 0x6012C
+
+#define mmMME0_CTRL_ARCH_AGU_L_REMOTE_START_OFFSET_0 0x60130
+
+#define mmMME0_CTRL_ARCH_AGU_L_REMOTE_START_OFFSET_1 0x60134
+
+#define mmMME0_CTRL_ARCH_AGU_L_REMOTE_START_OFFSET_2 0x60138
+
+#define mmMME0_CTRL_ARCH_AGU_L_REMOTE_START_OFFSET_3 0x6013C
+
+#define mmMME0_CTRL_ARCH_TENSOR_O_VALID_ELEMENTS_0 0x60140
+
+#define mmMME0_CTRL_ARCH_TENSOR_O_VALID_ELEMENTS_1 0x60144
+
+#define mmMME0_CTRL_ARCH_TENSOR_O_VALID_ELEMENTS_2 0x60148
+
+#define mmMME0_CTRL_ARCH_TENSOR_O_VALID_ELEMENTS_3 0x6014C
+
+#define mmMME0_CTRL_ARCH_TENSOR_O_VALID_ELEMENTS_4 0x60150
+
+#define mmMME0_CTRL_ARCH_TENSOR_O_LOOP_STRIDE_0 0x60154
+
+#define mmMME0_CTRL_ARCH_TENSOR_O_LOOP_STRIDE_1 0x60158
+
+#define mmMME0_CTRL_ARCH_TENSOR_O_LOOP_STRIDE_2 0x6015C
+
+#define mmMME0_CTRL_ARCH_TENSOR_O_LOOP_STRIDE_3 0x60160
+
+#define mmMME0_CTRL_ARCH_TENSOR_O_LOOP_STRIDE_4 0x60164
+
+#define mmMME0_CTRL_ARCH_TENSOR_O_ROI_SIZE_0 0x60168
+
+#define mmMME0_CTRL_ARCH_TENSOR_O_ROI_SIZE_1 0x6016C
+
+#define mmMME0_CTRL_ARCH_TENSOR_O_ROI_SIZE_2 0x60170
+
+#define mmMME0_CTRL_ARCH_TENSOR_O_ROI_SIZE_3 0x60174
+
+#define mmMME0_CTRL_ARCH_TENSOR_O_SPATIAL_STRIDES_0 0x60178
+
+#define mmMME0_CTRL_ARCH_TENSOR_O_SPATIAL_STRIDES_1 0x6017C
+
+#define mmMME0_CTRL_ARCH_TENSOR_O_SPATIAL_STRIDES_2 0x60180
+
+#define mmMME0_CTRL_ARCH_TENSOR_O_SPATIAL_STRIDES_3 0x60184
+
+#define mmMME0_CTRL_ARCH_TENSOR_O_SPATIAL_SIZE_MINUS_1 0x60188
+
+#define mmMME0_CTRL_ARCH_AGU_O_LOCAL_ROI_BASE_OFFSET_0 0x6018C
+
+#define mmMME0_CTRL_ARCH_AGU_O_LOCAL_ROI_BASE_OFFSET_1 0x60190
+
+#define mmMME0_CTRL_ARCH_AGU_O_LOCAL_ROI_BASE_OFFSET_2 0x60194
+
+#define mmMME0_CTRL_ARCH_AGU_O_LOCAL_ROI_BASE_OFFSET_3 0x60198
+
+#define mmMME0_CTRL_ARCH_AGU_O_LOCAL_ROI_BASE_OFFSET_4 0x6019C
+
+#define mmMME0_CTRL_ARCH_AGU_O_LOCAL_START_OFFSET_0 0x601A0
+
+#define mmMME0_CTRL_ARCH_AGU_O_LOCAL_START_OFFSET_1 0x601A4
+
+#define mmMME0_CTRL_ARCH_AGU_O_LOCAL_START_OFFSET_2 0x601A8
+
+#define mmMME0_CTRL_ARCH_AGU_O_LOCAL_START_OFFSET_3 0x601AC
+
+#define mmMME0_CTRL_ARCH_AGU_O_REMOTE_ROI_BASE_OFFSET_0 0x601B0
+
+#define mmMME0_CTRL_ARCH_AGU_O_REMOTE_ROI_BASE_OFFSET_1 0x601B4
+
+#define mmMME0_CTRL_ARCH_AGU_O_REMOTE_ROI_BASE_OFFSET_2 0x601B8
+
+#define mmMME0_CTRL_ARCH_AGU_O_REMOTE_ROI_BASE_OFFSET_3 0x601BC
+
+#define mmMME0_CTRL_ARCH_AGU_O_REMOTE_ROI_BASE_OFFSET_4 0x601C0
+
+#define mmMME0_CTRL_ARCH_AGU_O_REMOTE_START_OFFSET_0 0x601C4
+
+#define mmMME0_CTRL_ARCH_AGU_O_REMOTE_START_OFFSET_1 0x601C8
+
+#define mmMME0_CTRL_ARCH_AGU_O_REMOTE_START_OFFSET_2 0x601CC
+
+#define mmMME0_CTRL_ARCH_AGU_O_REMOTE_START_OFFSET_3 0x601D0
+
+#define mmMME0_CTRL_ARCH_DESC_SB_REPEAT 0x601D4
+
+#define mmMME0_CTRL_ARCH_DESC_RATE_LIMITER 0x601D8
+
+#define mmMME0_CTRL_ARCH_DESC_SYNC_OBJECT_ADDR_LOW_LOCAL 0x601DC
+
+#define mmMME0_CTRL_ARCH_DESC_SYNC_OBJECT_ADDR_LOW_REMOTE 0x601E0
+
+#define mmMME0_CTRL_ARCH_DESC_SYNC_OBJECT_ADDR_HIGH 0x601E4
+
+#define mmMME0_CTRL_ARCH_DESC_SYNC_OBJECT_DATA 0x601E8
+
+#define mmMME0_CTRL_ARCH_DESC_AXI_USER_DATA 0x601EC
+
+#define mmMME0_CTRL_ARCH_DESC_PERF_EVT_S 0x601F0
+
+#define mmMME0_CTRL_ARCH_DESC_PERF_EVT_L_LOCAL 0x601F4
+
+#define mmMME0_CTRL_ARCH_DESC_PERF_EVT_L_REMOTE 0x601F8
+
+#define mmMME0_CTRL_ARCH_DESC_PERF_EVT_O_LOCAL 0x601FC
+
+#define mmMME0_CTRL_ARCH_DESC_PERF_EVT_O_REMOTE 0x60200
+
+#define mmMME0_CTRL_ARCH_DESC_PADDING_VALUE_S 0x60204
+
+#define mmMME0_CTRL_ARCH_DESC_PADDING_VALUE_L 0x60208
+
+#define mmMME0_CTRL_ARCH_DESC_META_DATA_AGU_S 0x6020C
+
+#define mmMME0_CTRL_ARCH_DESC_META_DATA_AGU_L_LOCAL 0x60210
+
+#define mmMME0_CTRL_ARCH_DESC_META_DATA_AGU_L_REMOTE 0x60214
+
+#define mmMME0_CTRL_ARCH_DESC_META_DATA_AGU_O_LOCAL 0x60218
+
+#define mmMME0_CTRL_ARCH_DESC_META_DATA_AGU_O_REMOTE 0x6021C
+
+#define mmMME0_CTRL_ARCH_DESC_PCU_RL_SATURATION 0x60220
+
+#define mmMME0_CTRL_ARCH_DESC_DUMMY 0x60224
+
+#define mmMME0_CTRL_CMD 0x60280
+
+#define mmMME0_CTRL_STATUS1 0x60284
+
+#define mmMME0_CTRL_RESET 0x60288
+
+#define mmMME0_CTRL_QM_STALL 0x6028C
+
+#define mmMME0_CTRL_SYNC_OBJECT_FIFO_TH 0x60290
+
+#define mmMME0_CTRL_EUS_ROLLUP_CNT_ADD 0x60294
+
+#define mmMME0_CTRL_INTR_CAUSE 0x60298
+
+#define mmMME0_CTRL_INTR_MASK 0x6029C
+
+#define mmMME0_CTRL_LOG_SHADOW 0x602A0
+
+#define mmMME0_CTRL_PCU_RL_DESC0 0x602A4
+
+#define mmMME0_CTRL_PCU_RL_TOKEN_UPDATE 0x602A8
+
+#define mmMME0_CTRL_PCU_RL_TH 0x602AC
+
+#define mmMME0_CTRL_PCU_RL_MIN 0x602B0
+
+#define mmMME0_CTRL_PCU_RL_CTRL_EN 0x602B4
+
+#define mmMME0_CTRL_PCU_RL_HISTORY_LOG_SIZE 0x602B8
+
+#define mmMME0_CTRL_PCU_DUMMY_A_BF16 0x602BC
+
+#define mmMME0_CTRL_PCU_DUMMY_B_BF16 0x602C0
+
+#define mmMME0_CTRL_PCU_DUMMY_A_FP32_ODD 0x602C4
+
+#define mmMME0_CTRL_PCU_DUMMY_A_FP32_EVEN 0x602C8
+
+#define mmMME0_CTRL_PCU_DUMMY_B_FP32_ODD 0x602CC
+
+#define mmMME0_CTRL_PCU_DUMMY_B_FP32_EVEN 0x602D0
+
+#define mmMME0_CTRL_PROT 0x602D4
+
+#define mmMME0_CTRL_EU_POWER_SAVE_DISABLE 0x602D8
+
+#define mmMME0_CTRL_CS_DBG_BLOCK_ID 0x602DC
+
+#define mmMME0_CTRL_CS_DBG_STATUS_DROP_CNT 0x602E0
+
+#define mmMME0_CTRL_TE_CLOSE_CGATE 0x602E4
+
+#define mmMME0_CTRL_AGU_SM_INFLIGHT_CNTR 0x602E8
+
+#define mmMME0_CTRL_AGU_SM_TOTAL_CNTR 0x602EC
+
+#define mmMME0_CTRL_EZSYNC_OUT_CREDIT 0x602F0
+
+#define mmMME0_CTRL_PCU_RL_SAT_SEC 0x602F4
+
+#define mmMME0_CTRL_AGU_SYNC_MSG_AXI_USER 0x602F8
+
+#define mmMME0_CTRL_QM_SLV_LBW_CLK_EN 0x602FC
+
+#define mmMME0_CTRL_SHADOW_0_STATUS 0x60400
+
+#define mmMME0_CTRL_SHADOW_0_BASE_ADDR_HIGH_S 0x60408
+
+#define mmMME0_CTRL_SHADOW_0_BASE_ADDR_HIGH_L 0x6040C
+
+#define mmMME0_CTRL_SHADOW_0_BASE_ADDR_HIGH_O 0x60410
+
+#define mmMME0_CTRL_SHADOW_0_BASE_ADDR_LOW_S 0x60414
+
+#define mmMME0_CTRL_SHADOW_0_BASE_ADDR_LOW_L 0x60418
+
+#define mmMME0_CTRL_SHADOW_0_BASE_ADDR_LOW_O 0x6041C
+
+#define mmMME0_CTRL_SHADOW_0_HEADER_LOW 0x60420
+
+#define mmMME0_CTRL_SHADOW_0_HEADER_HIGH 0x60424
+
+#define mmMME0_CTRL_SHADOW_0_CONV_KERNEL_SIZE_MINUS_1 0x60428
+
+#define mmMME0_CTRL_SHADOW_0_CONV_ASSOCIATED_DIMS_LOW 0x6042C
+
+#define mmMME0_CTRL_SHADOW_0_CONV_ASSOCIATED_DIMS_HIGH 0x60430
+
+#define mmMME0_CTRL_SHADOW_0_NUM_ITERATIONS_MINUS_1 0x60434
+
+#define mmMME0_CTRL_SHADOW_0_OUTER_LOOP 0x60438
+
+#define mmMME0_CTRL_SHADOW_0_TENSOR_S_VALID_ELEMENTS_0 0x6043C
+
+#define mmMME0_CTRL_SHADOW_0_TENSOR_S_VALID_ELEMENTS_1 0x60440
+
+#define mmMME0_CTRL_SHADOW_0_TENSOR_S_VALID_ELEMENTS_2 0x60444
+
+#define mmMME0_CTRL_SHADOW_0_TENSOR_S_VALID_ELEMENTS_3 0x60448
+
+#define mmMME0_CTRL_SHADOW_0_TENSOR_S_VALID_ELEMENTS_4 0x6044C
+
+#define mmMME0_CTRL_SHADOW_0_TENSOR_S_LOOP_STRIDE_0 0x60450
+
+#define mmMME0_CTRL_SHADOW_0_TENSOR_S_LOOP_STRIDE_1 0x60454
+
+#define mmMME0_CTRL_SHADOW_0_TENSOR_S_LOOP_STRIDE_2 0x60458
+
+#define mmMME0_CTRL_SHADOW_0_TENSOR_S_LOOP_STRIDE_3 0x6045C
+
+#define mmMME0_CTRL_SHADOW_0_TENSOR_S_LOOP_STRIDE_4 0x60460
+
+#define mmMME0_CTRL_SHADOW_0_TENSOR_S_ROI_SIZE_0 0x60464
+
+#define mmMME0_CTRL_SHADOW_0_TENSOR_S_ROI_SIZE_1 0x60468
+
+#define mmMME0_CTRL_SHADOW_0_TENSOR_S_ROI_SIZE_2 0x6046C
+
+#define mmMME0_CTRL_SHADOW_0_TENSOR_S_ROI_SIZE_3 0x60470
+
+#define mmMME0_CTRL_SHADOW_0_TENSOR_S_SPATIAL_STRIDES_0 0x60474
+
+#define mmMME0_CTRL_SHADOW_0_TENSOR_S_SPATIAL_STRIDES_1 0x60478
+
+#define mmMME0_CTRL_SHADOW_0_TENSOR_S_SPATIAL_STRIDES_2 0x6047C
+
+#define mmMME0_CTRL_SHADOW_0_TENSOR_S_SPATIAL_STRIDES_3 0x60480
+
+#define mmMME0_CTRL_SHADOW_0_TENSOR_S_SPATIAL_SIZE_MINUS_1 0x60484
+
+#define mmMME0_CTRL_SHADOW_0_AGU_S_ROI_BASE_OFFSET_0 0x60488
+
+#define mmMME0_CTRL_SHADOW_0_AGU_S_ROI_BASE_OFFSET_1 0x6048C
+
+#define mmMME0_CTRL_SHADOW_0_AGU_S_ROI_BASE_OFFSET_2 0x60490
+
+#define mmMME0_CTRL_SHADOW_0_AGU_S_ROI_BASE_OFFSET_3 0x60494
+
+#define mmMME0_CTRL_SHADOW_0_AGU_S_ROI_BASE_OFFSET_4 0x60498
+
+#define mmMME0_CTRL_SHADOW_0_AGU_S_START_OFFSET_0 0x6049C
+
+#define mmMME0_CTRL_SHADOW_0_AGU_S_START_OFFSET_1 0x604A0
+
+#define mmMME0_CTRL_SHADOW_0_AGU_S_START_OFFSET_2 0x604A4
+
+#define mmMME0_CTRL_SHADOW_0_AGU_S_START_OFFSET_3 0x604A8
+
+#define mmMME0_CTRL_SHADOW_0_TENSOR_L_VALID_ELEMENTS_0 0x604AC
+
+#define mmMME0_CTRL_SHADOW_0_TENSOR_L_VALID_ELEMENTS_1 0x604B0
+
+#define mmMME0_CTRL_SHADOW_0_TENSOR_L_VALID_ELEMENTS_2 0x604B4
+
+#define mmMME0_CTRL_SHADOW_0_TENSOR_L_VALID_ELEMENTS_3 0x604B8
+
+#define mmMME0_CTRL_SHADOW_0_TENSOR_L_VALID_ELEMENTS_4 0x604BC
+
+#define mmMME0_CTRL_SHADOW_0_TENSOR_L_LOOP_STRIDE_0 0x604C0
+
+#define mmMME0_CTRL_SHADOW_0_TENSOR_L_LOOP_STRIDE_1 0x604C4
+
+#define mmMME0_CTRL_SHADOW_0_TENSOR_L_LOOP_STRIDE_2 0x604C8
+
+#define mmMME0_CTRL_SHADOW_0_TENSOR_L_LOOP_STRIDE_3 0x604CC
+
+#define mmMME0_CTRL_SHADOW_0_TENSOR_L_LOOP_STRIDE_4 0x604D0
+
+#define mmMME0_CTRL_SHADOW_0_TENSOR_L_ROI_SIZE_0 0x604D4
+
+#define mmMME0_CTRL_SHADOW_0_TENSOR_L_ROI_SIZE_1 0x604D8
+
+#define mmMME0_CTRL_SHADOW_0_TENSOR_L_ROI_SIZE_2 0x604DC
+
+#define mmMME0_CTRL_SHADOW_0_TENSOR_L_ROI_SIZE_3 0x604E0
+
+#define mmMME0_CTRL_SHADOW_0_TENSOR_L_SPATIAL_STRIDES_0 0x604E4
+
+#define mmMME0_CTRL_SHADOW_0_TENSOR_L_SPATIAL_STRIDES_1 0x604E8
+
+#define mmMME0_CTRL_SHADOW_0_TENSOR_L_SPATIAL_STRIDES_2 0x604EC
+
+#define mmMME0_CTRL_SHADOW_0_TENSOR_L_SPATIAL_STRIDES_3 0x604F0
+
+#define mmMME0_CTRL_SHADOW_0_TENSOR_L_SPATIAL_SIZE_MINUS_1 0x604F4
+
+#define mmMME0_CTRL_SHADOW_0_AGU_L_LOCAL_ROI_BASE_OFFSET_0 0x604F8
+
+#define mmMME0_CTRL_SHADOW_0_AGU_L_LOCAL_ROI_BASE_OFFSET_1 0x604FC
+
+#define mmMME0_CTRL_SHADOW_0_AGU_L_LOCAL_ROI_BASE_OFFSET_2 0x60500
+
+#define mmMME0_CTRL_SHADOW_0_AGU_L_LOCAL_ROI_BASE_OFFSET_3 0x60504
+
+#define mmMME0_CTRL_SHADOW_0_AGU_L_LOCAL_ROI_BASE_OFFSET_4 0x60508
+
+#define mmMME0_CTRL_SHADOW_0_AGU_L_LOCAL_START_OFFSET_0 0x6050C
+
+#define mmMME0_CTRL_SHADOW_0_AGU_L_LOCAL_START_OFFSET_1 0x60510
+
+#define mmMME0_CTRL_SHADOW_0_AGU_L_LOCAL_START_OFFSET_2 0x60514
+
+#define mmMME0_CTRL_SHADOW_0_AGU_L_LOCAL_START_OFFSET_3 0x60518
+
+#define mmMME0_CTRL_SHADOW_0_AGU_L_REMOTE_ROI_BASE_OFFSET_0 0x6051C
+
+#define mmMME0_CTRL_SHADOW_0_AGU_L_REMOTE_ROI_BASE_OFFSET_1 0x60520
+
+#define mmMME0_CTRL_SHADOW_0_AGU_L_REMOTE_ROI_BASE_OFFSET_2 0x60524
+
+#define mmMME0_CTRL_SHADOW_0_AGU_L_REMOTE_ROI_BASE_OFFSET_3 0x60528
+
+#define mmMME0_CTRL_SHADOW_0_AGU_L_REMOTE_ROI_BASE_OFFSET_4 0x6052C
+
+#define mmMME0_CTRL_SHADOW_0_AGU_L_REMOTE_START_OFFSET_0 0x60530
+
+#define mmMME0_CTRL_SHADOW_0_AGU_L_REMOTE_START_OFFSET_1 0x60534
+
+#define mmMME0_CTRL_SHADOW_0_AGU_L_REMOTE_START_OFFSET_2 0x60538
+
+#define mmMME0_CTRL_SHADOW_0_AGU_L_REMOTE_START_OFFSET_3 0x6053C
+
+#define mmMME0_CTRL_SHADOW_0_TENSOR_O_VALID_ELEMENTS_0 0x60540
+
+#define mmMME0_CTRL_SHADOW_0_TENSOR_O_VALID_ELEMENTS_1 0x60544
+
+#define mmMME0_CTRL_SHADOW_0_TENSOR_O_VALID_ELEMENTS_2 0x60548
+
+#define mmMME0_CTRL_SHADOW_0_TENSOR_O_VALID_ELEMENTS_3 0x6054C
+
+#define mmMME0_CTRL_SHADOW_0_TENSOR_O_VALID_ELEMENTS_4 0x60550
+
+#define mmMME0_CTRL_SHADOW_0_TENSOR_O_LOOP_STRIDE_0 0x60554
+
+#define mmMME0_CTRL_SHADOW_0_TENSOR_O_LOOP_STRIDE_1 0x60558
+
+#define mmMME0_CTRL_SHADOW_0_TENSOR_O_LOOP_STRIDE_2 0x6055C
+
+#define mmMME0_CTRL_SHADOW_0_TENSOR_O_LOOP_STRIDE_3 0x60560
+
+#define mmMME0_CTRL_SHADOW_0_TENSOR_O_LOOP_STRIDE_4 0x60564
+
+#define mmMME0_CTRL_SHADOW_0_TENSOR_O_ROI_SIZE_0 0x60568
+
+#define mmMME0_CTRL_SHADOW_0_TENSOR_O_ROI_SIZE_1 0x6056C
+
+#define mmMME0_CTRL_SHADOW_0_TENSOR_O_ROI_SIZE_2 0x60570
+
+#define mmMME0_CTRL_SHADOW_0_TENSOR_O_ROI_SIZE_3 0x60574
+
+#define mmMME0_CTRL_SHADOW_0_TENSOR_O_SPATIAL_STRIDES_0 0x60578
+
+#define mmMME0_CTRL_SHADOW_0_TENSOR_O_SPATIAL_STRIDES_1 0x6057C
+
+#define mmMME0_CTRL_SHADOW_0_TENSOR_O_SPATIAL_STRIDES_2 0x60580
+
+#define mmMME0_CTRL_SHADOW_0_TENSOR_O_SPATIAL_STRIDES_3 0x60584
+
+#define mmMME0_CTRL_SHADOW_0_TENSOR_O_SPATIAL_SIZE_MINUS_1 0x60588
+
+#define mmMME0_CTRL_SHADOW_0_AGU_O_LOCAL_ROI_BASE_OFFSET_0 0x6058C
+
+#define mmMME0_CTRL_SHADOW_0_AGU_O_LOCAL_ROI_BASE_OFFSET_1 0x60590
+
+#define mmMME0_CTRL_SHADOW_0_AGU_O_LOCAL_ROI_BASE_OFFSET_2 0x60594
+
+#define mmMME0_CTRL_SHADOW_0_AGU_O_LOCAL_ROI_BASE_OFFSET_3 0x60598
+
+#define mmMME0_CTRL_SHADOW_0_AGU_O_LOCAL_ROI_BASE_OFFSET_4 0x6059C
+
+#define mmMME0_CTRL_SHADOW_0_AGU_O_LOCAL_START_OFFSET_0 0x605A0
+
+#define mmMME0_CTRL_SHADOW_0_AGU_O_LOCAL_START_OFFSET_1 0x605A4
+
+#define mmMME0_CTRL_SHADOW_0_AGU_O_LOCAL_START_OFFSET_2 0x605A8
+
+#define mmMME0_CTRL_SHADOW_0_AGU_O_LOCAL_START_OFFSET_3 0x605AC
+
+#define mmMME0_CTRL_SHADOW_0_AGU_O_REMOTE_ROI_BASE_OFFSET_0 0x605B0
+
+#define mmMME0_CTRL_SHADOW_0_AGU_O_REMOTE_ROI_BASE_OFFSET_1 0x605B4
+
+#define mmMME0_CTRL_SHADOW_0_AGU_O_REMOTE_ROI_BASE_OFFSET_2 0x605B8
+
+#define mmMME0_CTRL_SHADOW_0_AGU_O_REMOTE_ROI_BASE_OFFSET_3 0x605BC
+
+#define mmMME0_CTRL_SHADOW_0_AGU_O_REMOTE_ROI_BASE_OFFSET_4 0x605C0
+
+#define mmMME0_CTRL_SHADOW_0_AGU_O_REMOTE_START_OFFSET_0 0x605C4
+
+#define mmMME0_CTRL_SHADOW_0_AGU_O_REMOTE_START_OFFSET_1 0x605C8
+
+#define mmMME0_CTRL_SHADOW_0_AGU_O_REMOTE_START_OFFSET_2 0x605CC
+
+#define mmMME0_CTRL_SHADOW_0_AGU_O_REMOTE_START_OFFSET_3 0x605D0
+
+#define mmMME0_CTRL_SHADOW_0_DESC_SB_REPEAT 0x605D4
+
+#define mmMME0_CTRL_SHADOW_0_DESC_RATE_LIMITER 0x605D8
+
+#define mmMME0_CTRL_SHADOW_0_DESC_SYNC_OBJECT_ADDR_LOW_LOCAL 0x605DC
+
+#define mmMME0_CTRL_SHADOW_0_DESC_SYNC_OBJECT_ADDR_LOW_REMOTE 0x605E0
+
+#define mmMME0_CTRL_SHADOW_0_DESC_SYNC_OBJECT_ADDR_HIGH 0x605E4
+
+#define mmMME0_CTRL_SHADOW_0_DESC_SYNC_OBJECT_DATA 0x605E8
+
+#define mmMME0_CTRL_SHADOW_0_DESC_AXI_USER_DATA 0x605EC
+
+#define mmMME0_CTRL_SHADOW_0_DESC_PERF_EVT_S 0x605F0
+
+#define mmMME0_CTRL_SHADOW_0_DESC_PERF_EVT_L_LOCAL 0x605F4
+
+#define mmMME0_CTRL_SHADOW_0_DESC_PERF_EVT_L_REMOTE 0x605F8
+
+#define mmMME0_CTRL_SHADOW_0_DESC_PERF_EVT_O_LOCAL 0x605FC
+
+#define mmMME0_CTRL_SHADOW_0_DESC_PERF_EVT_O_REMOTE 0x60600
+
+#define mmMME0_CTRL_SHADOW_0_DESC_PADDING_VALUE_S 0x60604
+
+#define mmMME0_CTRL_SHADOW_0_DESC_PADDING_VALUE_L 0x60608
+
+#define mmMME0_CTRL_SHADOW_0_DESC_META_DATA_AGU_S 0x6060C
+
+#define mmMME0_CTRL_SHADOW_0_DESC_META_DATA_AGU_L_LOCAL 0x60610
+
+#define mmMME0_CTRL_SHADOW_0_DESC_META_DATA_AGU_L_REMOTE 0x60614
+
+#define mmMME0_CTRL_SHADOW_0_DESC_META_DATA_AGU_O_LOCAL 0x60618
+
+#define mmMME0_CTRL_SHADOW_0_DESC_META_DATA_AGU_O_REMOTE 0x6061C
+
+#define mmMME0_CTRL_SHADOW_0_DESC_PCU_RL_SATURATION 0x60620
+
+#define mmMME0_CTRL_SHADOW_0_DESC_DUMMY 0x60624
+
+#define mmMME0_CTRL_SHADOW_1_STATUS 0x60680
+
+#define mmMME0_CTRL_SHADOW_1_BASE_ADDR_HIGH_S 0x60688
+
+#define mmMME0_CTRL_SHADOW_1_BASE_ADDR_HIGH_L 0x6068C
+
+#define mmMME0_CTRL_SHADOW_1_BASE_ADDR_HIGH_O 0x60690
+
+#define mmMME0_CTRL_SHADOW_1_BASE_ADDR_LOW_S 0x60694
+
+#define mmMME0_CTRL_SHADOW_1_BASE_ADDR_LOW_L 0x60698
+
+#define mmMME0_CTRL_SHADOW_1_BASE_ADDR_LOW_O 0x6069C
+
+#define mmMME0_CTRL_SHADOW_1_HEADER_LOW 0x606A0
+
+#define mmMME0_CTRL_SHADOW_1_HEADER_HIGH 0x606A4
+
+#define mmMME0_CTRL_SHADOW_1_CONV_KERNEL_SIZE_MINUS_1 0x606A8
+
+#define mmMME0_CTRL_SHADOW_1_CONV_ASSOCIATED_DIMS_LOW 0x606AC
+
+#define mmMME0_CTRL_SHADOW_1_CONV_ASSOCIATED_DIMS_HIGH 0x606B0
+
+#define mmMME0_CTRL_SHADOW_1_NUM_ITERATIONS_MINUS_1 0x606B4
+
+#define mmMME0_CTRL_SHADOW_1_OUTER_LOOP 0x606B8
+
+#define mmMME0_CTRL_SHADOW_1_TENSOR_S_VALID_ELEMENTS_0 0x606BC
+
+#define mmMME0_CTRL_SHADOW_1_TENSOR_S_VALID_ELEMENTS_1 0x606C0
+
+#define mmMME0_CTRL_SHADOW_1_TENSOR_S_VALID_ELEMENTS_2 0x606C4
+
+#define mmMME0_CTRL_SHADOW_1_TENSOR_S_VALID_ELEMENTS_3 0x606C8
+
+#define mmMME0_CTRL_SHADOW_1_TENSOR_S_VALID_ELEMENTS_4 0x606CC
+
+#define mmMME0_CTRL_SHADOW_1_TENSOR_S_LOOP_STRIDE_0 0x606D0
+
+#define mmMME0_CTRL_SHADOW_1_TENSOR_S_LOOP_STRIDE_1 0x606D4
+
+#define mmMME0_CTRL_SHADOW_1_TENSOR_S_LOOP_STRIDE_2 0x606D8
+
+#define mmMME0_CTRL_SHADOW_1_TENSOR_S_LOOP_STRIDE_3 0x606DC
+
+#define mmMME0_CTRL_SHADOW_1_TENSOR_S_LOOP_STRIDE_4 0x606E0
+
+#define mmMME0_CTRL_SHADOW_1_TENSOR_S_ROI_SIZE_0 0x606E4
+
+#define mmMME0_CTRL_SHADOW_1_TENSOR_S_ROI_SIZE_1 0x606E8
+
+#define mmMME0_CTRL_SHADOW_1_TENSOR_S_ROI_SIZE_2 0x606EC
+
+#define mmMME0_CTRL_SHADOW_1_TENSOR_S_ROI_SIZE_3 0x606F0
+
+#define mmMME0_CTRL_SHADOW_1_TENSOR_S_SPATIAL_STRIDES_0 0x606F4
+
+#define mmMME0_CTRL_SHADOW_1_TENSOR_S_SPATIAL_STRIDES_1 0x606F8
+
+#define mmMME0_CTRL_SHADOW_1_TENSOR_S_SPATIAL_STRIDES_2 0x606FC
+
+#define mmMME0_CTRL_SHADOW_1_TENSOR_S_SPATIAL_STRIDES_3 0x60700
+
+#define mmMME0_CTRL_SHADOW_1_TENSOR_S_SPATIAL_SIZE_MINUS_1 0x60704
+
+#define mmMME0_CTRL_SHADOW_1_AGU_S_ROI_BASE_OFFSET_0 0x60708
+
+#define mmMME0_CTRL_SHADOW_1_AGU_S_ROI_BASE_OFFSET_1 0x6070C
+
+#define mmMME0_CTRL_SHADOW_1_AGU_S_ROI_BASE_OFFSET_2 0x60710
+
+#define mmMME0_CTRL_SHADOW_1_AGU_S_ROI_BASE_OFFSET_3 0x60714
+
+#define mmMME0_CTRL_SHADOW_1_AGU_S_ROI_BASE_OFFSET_4 0x60718
+
+#define mmMME0_CTRL_SHADOW_1_AGU_S_START_OFFSET_0 0x6071C
+
+#define mmMME0_CTRL_SHADOW_1_AGU_S_START_OFFSET_1 0x60720
+
+#define mmMME0_CTRL_SHADOW_1_AGU_S_START_OFFSET_2 0x60724
+
+#define mmMME0_CTRL_SHADOW_1_AGU_S_START_OFFSET_3 0x60728
+
+#define mmMME0_CTRL_SHADOW_1_TENSOR_L_VALID_ELEMENTS_0 0x6072C
+
+#define mmMME0_CTRL_SHADOW_1_TENSOR_L_VALID_ELEMENTS_1 0x60730
+
+#define mmMME0_CTRL_SHADOW_1_TENSOR_L_VALID_ELEMENTS_2 0x60734
+
+#define mmMME0_CTRL_SHADOW_1_TENSOR_L_VALID_ELEMENTS_3 0x60738
+
+#define mmMME0_CTRL_SHADOW_1_TENSOR_L_VALID_ELEMENTS_4 0x6073C
+
+#define mmMME0_CTRL_SHADOW_1_TENSOR_L_LOOP_STRIDE_0 0x60740
+
+#define mmMME0_CTRL_SHADOW_1_TENSOR_L_LOOP_STRIDE_1 0x60744
+
+#define mmMME0_CTRL_SHADOW_1_TENSOR_L_LOOP_STRIDE_2 0x60748
+
+#define mmMME0_CTRL_SHADOW_1_TENSOR_L_LOOP_STRIDE_3 0x6074C
+
+#define mmMME0_CTRL_SHADOW_1_TENSOR_L_LOOP_STRIDE_4 0x60750
+
+#define mmMME0_CTRL_SHADOW_1_TENSOR_L_ROI_SIZE_0 0x60754
+
+#define mmMME0_CTRL_SHADOW_1_TENSOR_L_ROI_SIZE_1 0x60758
+
+#define mmMME0_CTRL_SHADOW_1_TENSOR_L_ROI_SIZE_2 0x6075C
+
+#define mmMME0_CTRL_SHADOW_1_TENSOR_L_ROI_SIZE_3 0x60760
+
+#define mmMME0_CTRL_SHADOW_1_TENSOR_L_SPATIAL_STRIDES_0 0x60764
+
+#define mmMME0_CTRL_SHADOW_1_TENSOR_L_SPATIAL_STRIDES_1 0x60768
+
+#define mmMME0_CTRL_SHADOW_1_TENSOR_L_SPATIAL_STRIDES_2 0x6076C
+
+#define mmMME0_CTRL_SHADOW_1_TENSOR_L_SPATIAL_STRIDES_3 0x60770
+
+#define mmMME0_CTRL_SHADOW_1_TENSOR_L_SPATIAL_SIZE_MINUS_1 0x60774
+
+#define mmMME0_CTRL_SHADOW_1_AGU_L_LOCAL_ROI_BASE_OFFSET_0 0x60778
+
+#define mmMME0_CTRL_SHADOW_1_AGU_L_LOCAL_ROI_BASE_OFFSET_1 0x6077C
+
+#define mmMME0_CTRL_SHADOW_1_AGU_L_LOCAL_ROI_BASE_OFFSET_2 0x60780
+
+#define mmMME0_CTRL_SHADOW_1_AGU_L_LOCAL_ROI_BASE_OFFSET_3 0x60784
+
+#define mmMME0_CTRL_SHADOW_1_AGU_L_LOCAL_ROI_BASE_OFFSET_4 0x60788
+
+#define mmMME0_CTRL_SHADOW_1_AGU_L_LOCAL_START_OFFSET_0 0x6078C
+
+#define mmMME0_CTRL_SHADOW_1_AGU_L_LOCAL_START_OFFSET_1 0x60790
+
+#define mmMME0_CTRL_SHADOW_1_AGU_L_LOCAL_START_OFFSET_2 0x60794
+
+#define mmMME0_CTRL_SHADOW_1_AGU_L_LOCAL_START_OFFSET_3 0x60798
+
+#define mmMME0_CTRL_SHADOW_1_AGU_L_REMOTE_ROI_BASE_OFFSET_0 0x6079C
+
+#define mmMME0_CTRL_SHADOW_1_AGU_L_REMOTE_ROI_BASE_OFFSET_1 0x607A0
+
+#define mmMME0_CTRL_SHADOW_1_AGU_L_REMOTE_ROI_BASE_OFFSET_2 0x607A4
+
+#define mmMME0_CTRL_SHADOW_1_AGU_L_REMOTE_ROI_BASE_OFFSET_3 0x607A8
+
+#define mmMME0_CTRL_SHADOW_1_AGU_L_REMOTE_ROI_BASE_OFFSET_4 0x607AC
+
+#define mmMME0_CTRL_SHADOW_1_AGU_L_REMOTE_START_OFFSET_0 0x607B0
+
+#define mmMME0_CTRL_SHADOW_1_AGU_L_REMOTE_START_OFFSET_1 0x607B4
+
+#define mmMME0_CTRL_SHADOW_1_AGU_L_REMOTE_START_OFFSET_2 0x607B8
+
+#define mmMME0_CTRL_SHADOW_1_AGU_L_REMOTE_START_OFFSET_3 0x607BC
+
+#define mmMME0_CTRL_SHADOW_1_TENSOR_O_VALID_ELEMENTS_0 0x607C0
+
+#define mmMME0_CTRL_SHADOW_1_TENSOR_O_VALID_ELEMENTS_1 0x607C4
+
+#define mmMME0_CTRL_SHADOW_1_TENSOR_O_VALID_ELEMENTS_2 0x607C8
+
+#define mmMME0_CTRL_SHADOW_1_TENSOR_O_VALID_ELEMENTS_3 0x607CC
+
+#define mmMME0_CTRL_SHADOW_1_TENSOR_O_VALID_ELEMENTS_4 0x607D0
+
+#define mmMME0_CTRL_SHADOW_1_TENSOR_O_LOOP_STRIDE_0 0x607D4
+
+#define mmMME0_CTRL_SHADOW_1_TENSOR_O_LOOP_STRIDE_1 0x607D8
+
+#define mmMME0_CTRL_SHADOW_1_TENSOR_O_LOOP_STRIDE_2 0x607DC
+
+#define mmMME0_CTRL_SHADOW_1_TENSOR_O_LOOP_STRIDE_3 0x607E0
+
+#define mmMME0_CTRL_SHADOW_1_TENSOR_O_LOOP_STRIDE_4 0x607E4
+
+#define mmMME0_CTRL_SHADOW_1_TENSOR_O_ROI_SIZE_0 0x607E8
+
+#define mmMME0_CTRL_SHADOW_1_TENSOR_O_ROI_SIZE_1 0x607EC
+
+#define mmMME0_CTRL_SHADOW_1_TENSOR_O_ROI_SIZE_2 0x607F0
+
+#define mmMME0_CTRL_SHADOW_1_TENSOR_O_ROI_SIZE_3 0x607F4
+
+#define mmMME0_CTRL_SHADOW_1_TENSOR_O_SPATIAL_STRIDES_0 0x607F8
+
+#define mmMME0_CTRL_SHADOW_1_TENSOR_O_SPATIAL_STRIDES_1 0x607FC
+
+#define mmMME0_CTRL_SHADOW_1_TENSOR_O_SPATIAL_STRIDES_2 0x60800
+
+#define mmMME0_CTRL_SHADOW_1_TENSOR_O_SPATIAL_STRIDES_3 0x60804
+
+#define mmMME0_CTRL_SHADOW_1_TENSOR_O_SPATIAL_SIZE_MINUS_1 0x60808
+
+#define mmMME0_CTRL_SHADOW_1_AGU_O_LOCAL_ROI_BASE_OFFSET_0 0x6080C
+
+#define mmMME0_CTRL_SHADOW_1_AGU_O_LOCAL_ROI_BASE_OFFSET_1 0x60810
+
+#define mmMME0_CTRL_SHADOW_1_AGU_O_LOCAL_ROI_BASE_OFFSET_2 0x60814
+
+#define mmMME0_CTRL_SHADOW_1_AGU_O_LOCAL_ROI_BASE_OFFSET_3 0x60818
+
+#define mmMME0_CTRL_SHADOW_1_AGU_O_LOCAL_ROI_BASE_OFFSET_4 0x6081C
+
+#define mmMME0_CTRL_SHADOW_1_AGU_O_LOCAL_START_OFFSET_0 0x60820
+
+#define mmMME0_CTRL_SHADOW_1_AGU_O_LOCAL_START_OFFSET_1 0x60824
+
+#define mmMME0_CTRL_SHADOW_1_AGU_O_LOCAL_START_OFFSET_2 0x60828
+
+#define mmMME0_CTRL_SHADOW_1_AGU_O_LOCAL_START_OFFSET_3 0x6082C
+
+#define mmMME0_CTRL_SHADOW_1_AGU_O_REMOTE_ROI_BASE_OFFSET_0 0x60830
+
+#define mmMME0_CTRL_SHADOW_1_AGU_O_REMOTE_ROI_BASE_OFFSET_1 0x60834
+
+#define mmMME0_CTRL_SHADOW_1_AGU_O_REMOTE_ROI_BASE_OFFSET_2 0x60838
+
+#define mmMME0_CTRL_SHADOW_1_AGU_O_REMOTE_ROI_BASE_OFFSET_3 0x6083C
+
+#define mmMME0_CTRL_SHADOW_1_AGU_O_REMOTE_ROI_BASE_OFFSET_4 0x60840
+
+#define mmMME0_CTRL_SHADOW_1_AGU_O_REMOTE_START_OFFSET_0 0x60844
+
+#define mmMME0_CTRL_SHADOW_1_AGU_O_REMOTE_START_OFFSET_1 0x60848
+
+#define mmMME0_CTRL_SHADOW_1_AGU_O_REMOTE_START_OFFSET_2 0x6084C
+
+#define mmMME0_CTRL_SHADOW_1_AGU_O_REMOTE_START_OFFSET_3 0x60850
+
+#define mmMME0_CTRL_SHADOW_1_DESC_SB_REPEAT 0x60854
+
+#define mmMME0_CTRL_SHADOW_1_DESC_RATE_LIMITER 0x60858
+
+#define mmMME0_CTRL_SHADOW_1_DESC_SYNC_OBJECT_ADDR_LOW_LOCAL 0x6085C
+
+#define mmMME0_CTRL_SHADOW_1_DESC_SYNC_OBJECT_ADDR_LOW_REMOTE 0x60860
+
+#define mmMME0_CTRL_SHADOW_1_DESC_SYNC_OBJECT_ADDR_HIGH 0x60864
+
+#define mmMME0_CTRL_SHADOW_1_DESC_SYNC_OBJECT_DATA 0x60868
+
+#define mmMME0_CTRL_SHADOW_1_DESC_AXI_USER_DATA 0x6086C
+
+#define mmMME0_CTRL_SHADOW_1_DESC_PERF_EVT_S 0x60870
+
+#define mmMME0_CTRL_SHADOW_1_DESC_PERF_EVT_L_LOCAL 0x60874
+
+#define mmMME0_CTRL_SHADOW_1_DESC_PERF_EVT_L_REMOTE 0x60878
+
+#define mmMME0_CTRL_SHADOW_1_DESC_PERF_EVT_O_LOCAL 0x6087C
+
+#define mmMME0_CTRL_SHADOW_1_DESC_PERF_EVT_O_REMOTE 0x60880
+
+#define mmMME0_CTRL_SHADOW_1_DESC_PADDING_VALUE_S 0x60884
+
+#define mmMME0_CTRL_SHADOW_1_DESC_PADDING_VALUE_L 0x60888
+
+#define mmMME0_CTRL_SHADOW_1_DESC_META_DATA_AGU_S 0x6088C
+
+#define mmMME0_CTRL_SHADOW_1_DESC_META_DATA_AGU_L_LOCAL 0x60890
+
+#define mmMME0_CTRL_SHADOW_1_DESC_META_DATA_AGU_L_REMOTE 0x60894
+
+#define mmMME0_CTRL_SHADOW_1_DESC_META_DATA_AGU_O_LOCAL 0x60898
+
+#define mmMME0_CTRL_SHADOW_1_DESC_META_DATA_AGU_O_REMOTE 0x6089C
+
+#define mmMME0_CTRL_SHADOW_1_DESC_PCU_RL_SATURATION 0x608A0
+
+#define mmMME0_CTRL_SHADOW_1_DESC_DUMMY 0x608A4
+
+#define mmMME0_CTRL_SHADOW_2_STATUS 0x60900
+
+#define mmMME0_CTRL_SHADOW_2_BASE_ADDR_HIGH_S 0x60908
+
+#define mmMME0_CTRL_SHADOW_2_BASE_ADDR_HIGH_L 0x6090C
+
+#define mmMME0_CTRL_SHADOW_2_BASE_ADDR_HIGH_O 0x60910
+
+#define mmMME0_CTRL_SHADOW_2_BASE_ADDR_LOW_S 0x60914
+
+#define mmMME0_CTRL_SHADOW_2_BASE_ADDR_LOW_L 0x60918
+
+#define mmMME0_CTRL_SHADOW_2_BASE_ADDR_LOW_O 0x6091C
+
+#define mmMME0_CTRL_SHADOW_2_HEADER_LOW 0x60920
+
+#define mmMME0_CTRL_SHADOW_2_HEADER_HIGH 0x60924
+
+#define mmMME0_CTRL_SHADOW_2_CONV_KERNEL_SIZE_MINUS_1 0x60928
+
+#define mmMME0_CTRL_SHADOW_2_CONV_ASSOCIATED_DIMS_LOW 0x6092C
+
+#define mmMME0_CTRL_SHADOW_2_CONV_ASSOCIATED_DIMS_HIGH 0x60930
+
+#define mmMME0_CTRL_SHADOW_2_NUM_ITERATIONS_MINUS_1 0x60934
+
+#define mmMME0_CTRL_SHADOW_2_OUTER_LOOP 0x60938
+
+#define mmMME0_CTRL_SHADOW_2_TENSOR_S_VALID_ELEMENTS_0 0x6093C
+
+#define mmMME0_CTRL_SHADOW_2_TENSOR_S_VALID_ELEMENTS_1 0x60940
+
+#define mmMME0_CTRL_SHADOW_2_TENSOR_S_VALID_ELEMENTS_2 0x60944
+
+#define mmMME0_CTRL_SHADOW_2_TENSOR_S_VALID_ELEMENTS_3 0x60948
+
+#define mmMME0_CTRL_SHADOW_2_TENSOR_S_VALID_ELEMENTS_4 0x6094C
+
+#define mmMME0_CTRL_SHADOW_2_TENSOR_S_LOOP_STRIDE_0 0x60950
+
+#define mmMME0_CTRL_SHADOW_2_TENSOR_S_LOOP_STRIDE_1 0x60954
+
+#define mmMME0_CTRL_SHADOW_2_TENSOR_S_LOOP_STRIDE_2 0x60958
+
+#define mmMME0_CTRL_SHADOW_2_TENSOR_S_LOOP_STRIDE_3 0x6095C
+
+#define mmMME0_CTRL_SHADOW_2_TENSOR_S_LOOP_STRIDE_4 0x60960
+
+#define mmMME0_CTRL_SHADOW_2_TENSOR_S_ROI_SIZE_0 0x60964
+
+#define mmMME0_CTRL_SHADOW_2_TENSOR_S_ROI_SIZE_1 0x60968
+
+#define mmMME0_CTRL_SHADOW_2_TENSOR_S_ROI_SIZE_2 0x6096C
+
+#define mmMME0_CTRL_SHADOW_2_TENSOR_S_ROI_SIZE_3 0x60970
+
+#define mmMME0_CTRL_SHADOW_2_TENSOR_S_SPATIAL_STRIDES_0 0x60974
+
+#define mmMME0_CTRL_SHADOW_2_TENSOR_S_SPATIAL_STRIDES_1 0x60978
+
+#define mmMME0_CTRL_SHADOW_2_TENSOR_S_SPATIAL_STRIDES_2 0x6097C
+
+#define mmMME0_CTRL_SHADOW_2_TENSOR_S_SPATIAL_STRIDES_3 0x60980
+
+#define mmMME0_CTRL_SHADOW_2_TENSOR_S_SPATIAL_SIZE_MINUS_1 0x60984
+
+#define mmMME0_CTRL_SHADOW_2_AGU_S_ROI_BASE_OFFSET_0 0x60988
+
+#define mmMME0_CTRL_SHADOW_2_AGU_S_ROI_BASE_OFFSET_1 0x6098C
+
+#define mmMME0_CTRL_SHADOW_2_AGU_S_ROI_BASE_OFFSET_2 0x60990
+
+#define mmMME0_CTRL_SHADOW_2_AGU_S_ROI_BASE_OFFSET_3 0x60994
+
+#define mmMME0_CTRL_SHADOW_2_AGU_S_ROI_BASE_OFFSET_4 0x60998
+
+#define mmMME0_CTRL_SHADOW_2_AGU_S_START_OFFSET_0 0x6099C
+
+#define mmMME0_CTRL_SHADOW_2_AGU_S_START_OFFSET_1 0x609A0
+
+#define mmMME0_CTRL_SHADOW_2_AGU_S_START_OFFSET_2 0x609A4
+
+#define mmMME0_CTRL_SHADOW_2_AGU_S_START_OFFSET_3 0x609A8
+
+#define mmMME0_CTRL_SHADOW_2_TENSOR_L_VALID_ELEMENTS_0 0x609AC
+
+#define mmMME0_CTRL_SHADOW_2_TENSOR_L_VALID_ELEMENTS_1 0x609B0
+
+#define mmMME0_CTRL_SHADOW_2_TENSOR_L_VALID_ELEMENTS_2 0x609B4
+
+#define mmMME0_CTRL_SHADOW_2_TENSOR_L_VALID_ELEMENTS_3 0x609B8
+
+#define mmMME0_CTRL_SHADOW_2_TENSOR_L_VALID_ELEMENTS_4 0x609BC
+
+#define mmMME0_CTRL_SHADOW_2_TENSOR_L_LOOP_STRIDE_0 0x609C0
+
+#define mmMME0_CTRL_SHADOW_2_TENSOR_L_LOOP_STRIDE_1 0x609C4
+
+#define mmMME0_CTRL_SHADOW_2_TENSOR_L_LOOP_STRIDE_2 0x609C8
+
+#define mmMME0_CTRL_SHADOW_2_TENSOR_L_LOOP_STRIDE_3 0x609CC
+
+#define mmMME0_CTRL_SHADOW_2_TENSOR_L_LOOP_STRIDE_4 0x609D0
+
+#define mmMME0_CTRL_SHADOW_2_TENSOR_L_ROI_SIZE_0 0x609D4
+
+#define mmMME0_CTRL_SHADOW_2_TENSOR_L_ROI_SIZE_1 0x609D8
+
+#define mmMME0_CTRL_SHADOW_2_TENSOR_L_ROI_SIZE_2 0x609DC
+
+#define mmMME0_CTRL_SHADOW_2_TENSOR_L_ROI_SIZE_3 0x609E0
+
+#define mmMME0_CTRL_SHADOW_2_TENSOR_L_SPATIAL_STRIDES_0 0x609E4
+
+#define mmMME0_CTRL_SHADOW_2_TENSOR_L_SPATIAL_STRIDES_1 0x609E8
+
+#define mmMME0_CTRL_SHADOW_2_TENSOR_L_SPATIAL_STRIDES_2 0x609EC
+
+#define mmMME0_CTRL_SHADOW_2_TENSOR_L_SPATIAL_STRIDES_3 0x609F0
+
+#define mmMME0_CTRL_SHADOW_2_TENSOR_L_SPATIAL_SIZE_MINUS_1 0x609F4
+
+#define mmMME0_CTRL_SHADOW_2_AGU_L_LOCAL_ROI_BASE_OFFSET_0 0x609F8
+
+#define mmMME0_CTRL_SHADOW_2_AGU_L_LOCAL_ROI_BASE_OFFSET_1 0x609FC
+
+#define mmMME0_CTRL_SHADOW_2_AGU_L_LOCAL_ROI_BASE_OFFSET_2 0x60A00
+
+#define mmMME0_CTRL_SHADOW_2_AGU_L_LOCAL_ROI_BASE_OFFSET_3 0x60A04
+
+#define mmMME0_CTRL_SHADOW_2_AGU_L_LOCAL_ROI_BASE_OFFSET_4 0x60A08
+
+#define mmMME0_CTRL_SHADOW_2_AGU_L_LOCAL_START_OFFSET_0 0x60A0C
+
+#define mmMME0_CTRL_SHADOW_2_AGU_L_LOCAL_START_OFFSET_1 0x60A10
+
+#define mmMME0_CTRL_SHADOW_2_AGU_L_LOCAL_START_OFFSET_2 0x60A14
+
+#define mmMME0_CTRL_SHADOW_2_AGU_L_LOCAL_START_OFFSET_3 0x60A18
+
+#define mmMME0_CTRL_SHADOW_2_AGU_L_REMOTE_ROI_BASE_OFFSET_0 0x60A1C
+
+#define mmMME0_CTRL_SHADOW_2_AGU_L_REMOTE_ROI_BASE_OFFSET_1 0x60A20
+
+#define mmMME0_CTRL_SHADOW_2_AGU_L_REMOTE_ROI_BASE_OFFSET_2 0x60A24
+
+#define mmMME0_CTRL_SHADOW_2_AGU_L_REMOTE_ROI_BASE_OFFSET_3 0x60A28
+
+#define mmMME0_CTRL_SHADOW_2_AGU_L_REMOTE_ROI_BASE_OFFSET_4 0x60A2C
+
+#define mmMME0_CTRL_SHADOW_2_AGU_L_REMOTE_START_OFFSET_0 0x60A30
+
+#define mmMME0_CTRL_SHADOW_2_AGU_L_REMOTE_START_OFFSET_1 0x60A34
+
+#define mmMME0_CTRL_SHADOW_2_AGU_L_REMOTE_START_OFFSET_2 0x60A38
+
+#define mmMME0_CTRL_SHADOW_2_AGU_L_REMOTE_START_OFFSET_3 0x60A3C
+
+#define mmMME0_CTRL_SHADOW_2_TENSOR_O_VALID_ELEMENTS_0 0x60A40
+
+#define mmMME0_CTRL_SHADOW_2_TENSOR_O_VALID_ELEMENTS_1 0x60A44
+
+#define mmMME0_CTRL_SHADOW_2_TENSOR_O_VALID_ELEMENTS_2 0x60A48
+
+#define mmMME0_CTRL_SHADOW_2_TENSOR_O_VALID_ELEMENTS_3 0x60A4C
+
+#define mmMME0_CTRL_SHADOW_2_TENSOR_O_VALID_ELEMENTS_4 0x60A50
+
+#define mmMME0_CTRL_SHADOW_2_TENSOR_O_LOOP_STRIDE_0 0x60A54
+
+#define mmMME0_CTRL_SHADOW_2_TENSOR_O_LOOP_STRIDE_1 0x60A58
+
+#define mmMME0_CTRL_SHADOW_2_TENSOR_O_LOOP_STRIDE_2 0x60A5C
+
+#define mmMME0_CTRL_SHADOW_2_TENSOR_O_LOOP_STRIDE_3 0x60A60
+
+#define mmMME0_CTRL_SHADOW_2_TENSOR_O_LOOP_STRIDE_4 0x60A64
+
+#define mmMME0_CTRL_SHADOW_2_TENSOR_O_ROI_SIZE_0 0x60A68
+
+#define mmMME0_CTRL_SHADOW_2_TENSOR_O_ROI_SIZE_1 0x60A6C
+
+#define mmMME0_CTRL_SHADOW_2_TENSOR_O_ROI_SIZE_2 0x60A70
+
+#define mmMME0_CTRL_SHADOW_2_TENSOR_O_ROI_SIZE_3 0x60A74
+
+#define mmMME0_CTRL_SHADOW_2_TENSOR_O_SPATIAL_STRIDES_0 0x60A78
+
+#define mmMME0_CTRL_SHADOW_2_TENSOR_O_SPATIAL_STRIDES_1 0x60A7C
+
+#define mmMME0_CTRL_SHADOW_2_TENSOR_O_SPATIAL_STRIDES_2 0x60A80
+
+#define mmMME0_CTRL_SHADOW_2_TENSOR_O_SPATIAL_STRIDES_3 0x60A84
+
+#define mmMME0_CTRL_SHADOW_2_TENSOR_O_SPATIAL_SIZE_MINUS_1 0x60A88
+
+#define mmMME0_CTRL_SHADOW_2_AGU_O_LOCAL_ROI_BASE_OFFSET_0 0x60A8C
+
+#define mmMME0_CTRL_SHADOW_2_AGU_O_LOCAL_ROI_BASE_OFFSET_1 0x60A90
+
+#define mmMME0_CTRL_SHADOW_2_AGU_O_LOCAL_ROI_BASE_OFFSET_2 0x60A94
+
+#define mmMME0_CTRL_SHADOW_2_AGU_O_LOCAL_ROI_BASE_OFFSET_3 0x60A98
+
+#define mmMME0_CTRL_SHADOW_2_AGU_O_LOCAL_ROI_BASE_OFFSET_4 0x60A9C
+
+#define mmMME0_CTRL_SHADOW_2_AGU_O_LOCAL_START_OFFSET_0 0x60AA0
+
+#define mmMME0_CTRL_SHADOW_2_AGU_O_LOCAL_START_OFFSET_1 0x60AA4
+
+#define mmMME0_CTRL_SHADOW_2_AGU_O_LOCAL_START_OFFSET_2 0x60AA8
+
+#define mmMME0_CTRL_SHADOW_2_AGU_O_LOCAL_START_OFFSET_3 0x60AAC
+
+#define mmMME0_CTRL_SHADOW_2_AGU_O_REMOTE_ROI_BASE_OFFSET_0 0x60AB0
+
+#define mmMME0_CTRL_SHADOW_2_AGU_O_REMOTE_ROI_BASE_OFFSET_1 0x60AB4
+
+#define mmMME0_CTRL_SHADOW_2_AGU_O_REMOTE_ROI_BASE_OFFSET_2 0x60AB8
+
+#define mmMME0_CTRL_SHADOW_2_AGU_O_REMOTE_ROI_BASE_OFFSET_3 0x60ABC
+
+#define mmMME0_CTRL_SHADOW_2_AGU_O_REMOTE_ROI_BASE_OFFSET_4 0x60AC0
+
+#define mmMME0_CTRL_SHADOW_2_AGU_O_REMOTE_START_OFFSET_0 0x60AC4
+
+#define mmMME0_CTRL_SHADOW_2_AGU_O_REMOTE_START_OFFSET_1 0x60AC8
+
+#define mmMME0_CTRL_SHADOW_2_AGU_O_REMOTE_START_OFFSET_2 0x60ACC
+
+#define mmMME0_CTRL_SHADOW_2_AGU_O_REMOTE_START_OFFSET_3 0x60AD0
+
+#define mmMME0_CTRL_SHADOW_2_DESC_SB_REPEAT 0x60AD4
+
+#define mmMME0_CTRL_SHADOW_2_DESC_RATE_LIMITER 0x60AD8
+
+#define mmMME0_CTRL_SHADOW_2_DESC_SYNC_OBJECT_ADDR_LOW_LOCAL 0x60ADC
+
+#define mmMME0_CTRL_SHADOW_2_DESC_SYNC_OBJECT_ADDR_LOW_REMOTE 0x60AE0
+
+#define mmMME0_CTRL_SHADOW_2_DESC_SYNC_OBJECT_ADDR_HIGH 0x60AE4
+
+#define mmMME0_CTRL_SHADOW_2_DESC_SYNC_OBJECT_DATA 0x60AE8
+
+#define mmMME0_CTRL_SHADOW_2_DESC_AXI_USER_DATA 0x60AEC
+
+#define mmMME0_CTRL_SHADOW_2_DESC_PERF_EVT_S 0x60AF0
+
+#define mmMME0_CTRL_SHADOW_2_DESC_PERF_EVT_L_LOCAL 0x60AF4
+
+#define mmMME0_CTRL_SHADOW_2_DESC_PERF_EVT_L_REMOTE 0x60AF8
+
+#define mmMME0_CTRL_SHADOW_2_DESC_PERF_EVT_O_LOCAL 0x60AFC
+
+#define mmMME0_CTRL_SHADOW_2_DESC_PERF_EVT_O_REMOTE 0x60B00
+
+#define mmMME0_CTRL_SHADOW_2_DESC_PADDING_VALUE_S 0x60B04
+
+#define mmMME0_CTRL_SHADOW_2_DESC_PADDING_VALUE_L 0x60B08
+
+#define mmMME0_CTRL_SHADOW_2_DESC_META_DATA_AGU_S 0x60B0C
+
+#define mmMME0_CTRL_SHADOW_2_DESC_META_DATA_AGU_L_LOCAL 0x60B10
+
+#define mmMME0_CTRL_SHADOW_2_DESC_META_DATA_AGU_L_REMOTE 0x60B14
+
+#define mmMME0_CTRL_SHADOW_2_DESC_META_DATA_AGU_O_LOCAL 0x60B18
+
+#define mmMME0_CTRL_SHADOW_2_DESC_META_DATA_AGU_O_REMOTE 0x60B1C
+
+#define mmMME0_CTRL_SHADOW_2_DESC_PCU_RL_SATURATION 0x60B20
+
+#define mmMME0_CTRL_SHADOW_2_DESC_DUMMY 0x60B24
+
+#define mmMME0_CTRL_SHADOW_3_STATUS 0x60B80
+
+#define mmMME0_CTRL_SHADOW_3_BASE_ADDR_HIGH_S 0x60B88
+
+#define mmMME0_CTRL_SHADOW_3_BASE_ADDR_HIGH_L 0x60B8C
+
+#define mmMME0_CTRL_SHADOW_3_BASE_ADDR_HIGH_O 0x60B90
+
+#define mmMME0_CTRL_SHADOW_3_BASE_ADDR_LOW_S 0x60B94
+
+#define mmMME0_CTRL_SHADOW_3_BASE_ADDR_LOW_L 0x60B98
+
+#define mmMME0_CTRL_SHADOW_3_BASE_ADDR_LOW_O 0x60B9C
+
+#define mmMME0_CTRL_SHADOW_3_HEADER_LOW 0x60BA0
+
+#define mmMME0_CTRL_SHADOW_3_HEADER_HIGH 0x60BA4
+
+#define mmMME0_CTRL_SHADOW_3_CONV_KERNEL_SIZE_MINUS_1 0x60BA8
+
+#define mmMME0_CTRL_SHADOW_3_CONV_ASSOCIATED_DIMS_LOW 0x60BAC
+
+#define mmMME0_CTRL_SHADOW_3_CONV_ASSOCIATED_DIMS_HIGH 0x60BB0
+
+#define mmMME0_CTRL_SHADOW_3_NUM_ITERATIONS_MINUS_1 0x60BB4
+
+#define mmMME0_CTRL_SHADOW_3_OUTER_LOOP 0x60BB8
+
+#define mmMME0_CTRL_SHADOW_3_TENSOR_S_VALID_ELEMENTS_0 0x60BBC
+
+#define mmMME0_CTRL_SHADOW_3_TENSOR_S_VALID_ELEMENTS_1 0x60BC0
+
+#define mmMME0_CTRL_SHADOW_3_TENSOR_S_VALID_ELEMENTS_2 0x60BC4
+
+#define mmMME0_CTRL_SHADOW_3_TENSOR_S_VALID_ELEMENTS_3 0x60BC8
+
+#define mmMME0_CTRL_SHADOW_3_TENSOR_S_VALID_ELEMENTS_4 0x60BCC
+
+#define mmMME0_CTRL_SHADOW_3_TENSOR_S_LOOP_STRIDE_0 0x60BD0
+
+#define mmMME0_CTRL_SHADOW_3_TENSOR_S_LOOP_STRIDE_1 0x60BD4
+
+#define mmMME0_CTRL_SHADOW_3_TENSOR_S_LOOP_STRIDE_2 0x60BD8
+
+#define mmMME0_CTRL_SHADOW_3_TENSOR_S_LOOP_STRIDE_3 0x60BDC
+
+#define mmMME0_CTRL_SHADOW_3_TENSOR_S_LOOP_STRIDE_4 0x60BE0
+
+#define mmMME0_CTRL_SHADOW_3_TENSOR_S_ROI_SIZE_0 0x60BE4
+
+#define mmMME0_CTRL_SHADOW_3_TENSOR_S_ROI_SIZE_1 0x60BE8
+
+#define mmMME0_CTRL_SHADOW_3_TENSOR_S_ROI_SIZE_2 0x60BEC
+
+#define mmMME0_CTRL_SHADOW_3_TENSOR_S_ROI_SIZE_3 0x60BF0
+
+#define mmMME0_CTRL_SHADOW_3_TENSOR_S_SPATIAL_STRIDES_0 0x60BF4
+
+#define mmMME0_CTRL_SHADOW_3_TENSOR_S_SPATIAL_STRIDES_1 0x60BF8
+
+#define mmMME0_CTRL_SHADOW_3_TENSOR_S_SPATIAL_STRIDES_2 0x60BFC
+
+#define mmMME0_CTRL_SHADOW_3_TENSOR_S_SPATIAL_STRIDES_3 0x60C00
+
+#define mmMME0_CTRL_SHADOW_3_TENSOR_S_SPATIAL_SIZE_MINUS_1 0x60C04
+
+#define mmMME0_CTRL_SHADOW_3_AGU_S_ROI_BASE_OFFSET_0 0x60C08
+
+#define mmMME0_CTRL_SHADOW_3_AGU_S_ROI_BASE_OFFSET_1 0x60C0C
+
+#define mmMME0_CTRL_SHADOW_3_AGU_S_ROI_BASE_OFFSET_2 0x60C10
+
+#define mmMME0_CTRL_SHADOW_3_AGU_S_ROI_BASE_OFFSET_3 0x60C14
+
+#define mmMME0_CTRL_SHADOW_3_AGU_S_ROI_BASE_OFFSET_4 0x60C18
+
+#define mmMME0_CTRL_SHADOW_3_AGU_S_START_OFFSET_0 0x60C1C
+
+#define mmMME0_CTRL_SHADOW_3_AGU_S_START_OFFSET_1 0x60C20
+
+#define mmMME0_CTRL_SHADOW_3_AGU_S_START_OFFSET_2 0x60C24
+
+#define mmMME0_CTRL_SHADOW_3_AGU_S_START_OFFSET_3 0x60C28
+
+#define mmMME0_CTRL_SHADOW_3_TENSOR_L_VALID_ELEMENTS_0 0x60C2C
+
+#define mmMME0_CTRL_SHADOW_3_TENSOR_L_VALID_ELEMENTS_1 0x60C30
+
+#define mmMME0_CTRL_SHADOW_3_TENSOR_L_VALID_ELEMENTS_2 0x60C34
+
+#define mmMME0_CTRL_SHADOW_3_TENSOR_L_VALID_ELEMENTS_3 0x60C38
+
+#define mmMME0_CTRL_SHADOW_3_TENSOR_L_VALID_ELEMENTS_4 0x60C3C
+
+#define mmMME0_CTRL_SHADOW_3_TENSOR_L_LOOP_STRIDE_0 0x60C40
+
+#define mmMME0_CTRL_SHADOW_3_TENSOR_L_LOOP_STRIDE_1 0x60C44
+
+#define mmMME0_CTRL_SHADOW_3_TENSOR_L_LOOP_STRIDE_2 0x60C48
+
+#define mmMME0_CTRL_SHADOW_3_TENSOR_L_LOOP_STRIDE_3 0x60C4C
+
+#define mmMME0_CTRL_SHADOW_3_TENSOR_L_LOOP_STRIDE_4 0x60C50
+
+#define mmMME0_CTRL_SHADOW_3_TENSOR_L_ROI_SIZE_0 0x60C54
+
+#define mmMME0_CTRL_SHADOW_3_TENSOR_L_ROI_SIZE_1 0x60C58
+
+#define mmMME0_CTRL_SHADOW_3_TENSOR_L_ROI_SIZE_2 0x60C5C
+
+#define mmMME0_CTRL_SHADOW_3_TENSOR_L_ROI_SIZE_3 0x60C60
+
+#define mmMME0_CTRL_SHADOW_3_TENSOR_L_SPATIAL_STRIDES_0 0x60C64
+
+#define mmMME0_CTRL_SHADOW_3_TENSOR_L_SPATIAL_STRIDES_1 0x60C68
+
+#define mmMME0_CTRL_SHADOW_3_TENSOR_L_SPATIAL_STRIDES_2 0x60C6C
+
+#define mmMME0_CTRL_SHADOW_3_TENSOR_L_SPATIAL_STRIDES_3 0x60C70
+
+#define mmMME0_CTRL_SHADOW_3_TENSOR_L_SPATIAL_SIZE_MINUS_1 0x60C74
+
+#define mmMME0_CTRL_SHADOW_3_AGU_L_LOCAL_ROI_BASE_OFFSET_0 0x60C78
+
+#define mmMME0_CTRL_SHADOW_3_AGU_L_LOCAL_ROI_BASE_OFFSET_1 0x60C7C
+
+#define mmMME0_CTRL_SHADOW_3_AGU_L_LOCAL_ROI_BASE_OFFSET_2 0x60C80
+
+#define mmMME0_CTRL_SHADOW_3_AGU_L_LOCAL_ROI_BASE_OFFSET_3 0x60C84
+
+#define mmMME0_CTRL_SHADOW_3_AGU_L_LOCAL_ROI_BASE_OFFSET_4 0x60C88
+
+#define mmMME0_CTRL_SHADOW_3_AGU_L_LOCAL_START_OFFSET_0 0x60C8C
+
+#define mmMME0_CTRL_SHADOW_3_AGU_L_LOCAL_START_OFFSET_1 0x60C90
+
+#define mmMME0_CTRL_SHADOW_3_AGU_L_LOCAL_START_OFFSET_2 0x60C94
+
+#define mmMME0_CTRL_SHADOW_3_AGU_L_LOCAL_START_OFFSET_3 0x60C98
+
+#define mmMME0_CTRL_SHADOW_3_AGU_L_REMOTE_ROI_BASE_OFFSET_0 0x60C9C
+
+#define mmMME0_CTRL_SHADOW_3_AGU_L_REMOTE_ROI_BASE_OFFSET_1 0x60CA0
+
+#define mmMME0_CTRL_SHADOW_3_AGU_L_REMOTE_ROI_BASE_OFFSET_2 0x60CA4
+
+#define mmMME0_CTRL_SHADOW_3_AGU_L_REMOTE_ROI_BASE_OFFSET_3 0x60CA8
+
+#define mmMME0_CTRL_SHADOW_3_AGU_L_REMOTE_ROI_BASE_OFFSET_4 0x60CAC
+
+#define mmMME0_CTRL_SHADOW_3_AGU_L_REMOTE_START_OFFSET_0 0x60CB0
+
+#define mmMME0_CTRL_SHADOW_3_AGU_L_REMOTE_START_OFFSET_1 0x60CB4
+
+#define mmMME0_CTRL_SHADOW_3_AGU_L_REMOTE_START_OFFSET_2 0x60CB8
+
+#define mmMME0_CTRL_SHADOW_3_AGU_L_REMOTE_START_OFFSET_3 0x60CBC
+
+#define mmMME0_CTRL_SHADOW_3_TENSOR_O_VALID_ELEMENTS_0 0x60CC0
+
+#define mmMME0_CTRL_SHADOW_3_TENSOR_O_VALID_ELEMENTS_1 0x60CC4
+
+#define mmMME0_CTRL_SHADOW_3_TENSOR_O_VALID_ELEMENTS_2 0x60CC8
+
+#define mmMME0_CTRL_SHADOW_3_TENSOR_O_VALID_ELEMENTS_3 0x60CCC
+
+#define mmMME0_CTRL_SHADOW_3_TENSOR_O_VALID_ELEMENTS_4 0x60CD0
+
+#define mmMME0_CTRL_SHADOW_3_TENSOR_O_LOOP_STRIDE_0 0x60CD4
+
+#define mmMME0_CTRL_SHADOW_3_TENSOR_O_LOOP_STRIDE_1 0x60CD8
+
+#define mmMME0_CTRL_SHADOW_3_TENSOR_O_LOOP_STRIDE_2 0x60CDC
+
+#define mmMME0_CTRL_SHADOW_3_TENSOR_O_LOOP_STRIDE_3 0x60CE0
+
+#define mmMME0_CTRL_SHADOW_3_TENSOR_O_LOOP_STRIDE_4 0x60CE4
+
+#define mmMME0_CTRL_SHADOW_3_TENSOR_O_ROI_SIZE_0 0x60CE8
+
+#define mmMME0_CTRL_SHADOW_3_TENSOR_O_ROI_SIZE_1 0x60CEC
+
+#define mmMME0_CTRL_SHADOW_3_TENSOR_O_ROI_SIZE_2 0x60CF0
+
+#define mmMME0_CTRL_SHADOW_3_TENSOR_O_ROI_SIZE_3 0x60CF4
+
+#define mmMME0_CTRL_SHADOW_3_TENSOR_O_SPATIAL_STRIDES_0 0x60CF8
+
+#define mmMME0_CTRL_SHADOW_3_TENSOR_O_SPATIAL_STRIDES_1 0x60CFC
+
+#define mmMME0_CTRL_SHADOW_3_TENSOR_O_SPATIAL_STRIDES_2 0x60D00
+
+#define mmMME0_CTRL_SHADOW_3_TENSOR_O_SPATIAL_STRIDES_3 0x60D04
+
+#define mmMME0_CTRL_SHADOW_3_TENSOR_O_SPATIAL_SIZE_MINUS_1 0x60D08
+
+#define mmMME0_CTRL_SHADOW_3_AGU_O_LOCAL_ROI_BASE_OFFSET_0 0x60D0C
+
+#define mmMME0_CTRL_SHADOW_3_AGU_O_LOCAL_ROI_BASE_OFFSET_1 0x60D10
+
+#define mmMME0_CTRL_SHADOW_3_AGU_O_LOCAL_ROI_BASE_OFFSET_2 0x60D14
+
+#define mmMME0_CTRL_SHADOW_3_AGU_O_LOCAL_ROI_BASE_OFFSET_3 0x60D18
+
+#define mmMME0_CTRL_SHADOW_3_AGU_O_LOCAL_ROI_BASE_OFFSET_4 0x60D1C
+
+#define mmMME0_CTRL_SHADOW_3_AGU_O_LOCAL_START_OFFSET_0 0x60D20
+
+#define mmMME0_CTRL_SHADOW_3_AGU_O_LOCAL_START_OFFSET_1 0x60D24
+
+#define mmMME0_CTRL_SHADOW_3_AGU_O_LOCAL_START_OFFSET_2 0x60D28
+
+#define mmMME0_CTRL_SHADOW_3_AGU_O_LOCAL_START_OFFSET_3 0x60D2C
+
+#define mmMME0_CTRL_SHADOW_3_AGU_O_REMOTE_ROI_BASE_OFFSET_0 0x60D30
+
+#define mmMME0_CTRL_SHADOW_3_AGU_O_REMOTE_ROI_BASE_OFFSET_1 0x60D34
+
+#define mmMME0_CTRL_SHADOW_3_AGU_O_REMOTE_ROI_BASE_OFFSET_2 0x60D38
+
+#define mmMME0_CTRL_SHADOW_3_AGU_O_REMOTE_ROI_BASE_OFFSET_3 0x60D3C
+
+#define mmMME0_CTRL_SHADOW_3_AGU_O_REMOTE_ROI_BASE_OFFSET_4 0x60D40
+
+#define mmMME0_CTRL_SHADOW_3_AGU_O_REMOTE_START_OFFSET_0 0x60D44
+
+#define mmMME0_CTRL_SHADOW_3_AGU_O_REMOTE_START_OFFSET_1 0x60D48
+
+#define mmMME0_CTRL_SHADOW_3_AGU_O_REMOTE_START_OFFSET_2 0x60D4C
+
+#define mmMME0_CTRL_SHADOW_3_AGU_O_REMOTE_START_OFFSET_3 0x60D50
+
+#define mmMME0_CTRL_SHADOW_3_DESC_SB_REPEAT 0x60D54
+
+#define mmMME0_CTRL_SHADOW_3_DESC_RATE_LIMITER 0x60D58
+
+#define mmMME0_CTRL_SHADOW_3_DESC_SYNC_OBJECT_ADDR_LOW_LOCAL 0x60D5C
+
+#define mmMME0_CTRL_SHADOW_3_DESC_SYNC_OBJECT_ADDR_LOW_REMOTE 0x60D60
+
+#define mmMME0_CTRL_SHADOW_3_DESC_SYNC_OBJECT_ADDR_HIGH 0x60D64
+
+#define mmMME0_CTRL_SHADOW_3_DESC_SYNC_OBJECT_DATA 0x60D68
+
+#define mmMME0_CTRL_SHADOW_3_DESC_AXI_USER_DATA 0x60D6C
+
+#define mmMME0_CTRL_SHADOW_3_DESC_PERF_EVT_S 0x60D70
+
+#define mmMME0_CTRL_SHADOW_3_DESC_PERF_EVT_L_LOCAL 0x60D74
+
+#define mmMME0_CTRL_SHADOW_3_DESC_PERF_EVT_L_REMOTE 0x60D78
+
+#define mmMME0_CTRL_SHADOW_3_DESC_PERF_EVT_O_LOCAL 0x60D7C
+
+#define mmMME0_CTRL_SHADOW_3_DESC_PERF_EVT_O_REMOTE 0x60D80
+
+#define mmMME0_CTRL_SHADOW_3_DESC_PADDING_VALUE_S 0x60D84
+
+#define mmMME0_CTRL_SHADOW_3_DESC_PADDING_VALUE_L 0x60D88
+
+#define mmMME0_CTRL_SHADOW_3_DESC_META_DATA_AGU_S 0x60D8C
+
+#define mmMME0_CTRL_SHADOW_3_DESC_META_DATA_AGU_L_LOCAL 0x60D90
+
+#define mmMME0_CTRL_SHADOW_3_DESC_META_DATA_AGU_L_REMOTE 0x60D94
+
+#define mmMME0_CTRL_SHADOW_3_DESC_META_DATA_AGU_O_LOCAL 0x60D98
+
+#define mmMME0_CTRL_SHADOW_3_DESC_META_DATA_AGU_O_REMOTE 0x60D9C
+
+#define mmMME0_CTRL_SHADOW_3_DESC_PCU_RL_SATURATION 0x60DA0
+
+#define mmMME0_CTRL_SHADOW_3_DESC_DUMMY 0x60DA4
+
+#endif /* ASIC_REG_MME0_CTRL_REGS_H_ */
diff --git a/drivers/accel/habanalabs/include/gaudi/asic_reg/mme0_qm_masks.h b/drivers/accel/habanalabs/include/gaudi/asic_reg/mme0_qm_masks.h
new file mode 100644
index 0000000000..e6dd30ce0c
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi/asic_reg/mme0_qm_masks.h
@@ -0,0 +1,800 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2016-2018 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ ** DO NOT EDIT BELOW **
+ ************************************/
+
+#ifndef ASIC_REG_MME0_QM_MASKS_H_
+#define ASIC_REG_MME0_QM_MASKS_H_
+
+/*
+ *****************************************
+ * MME0_QM (Prototype: QMAN)
+ *****************************************
+ */
+
+/* MME0_QM_GLBL_CFG0 */
+#define MME0_QM_GLBL_CFG0_PQF_EN_SHIFT 0
+#define MME0_QM_GLBL_CFG0_PQF_EN_MASK 0xF
+#define MME0_QM_GLBL_CFG0_CQF_EN_SHIFT 4
+#define MME0_QM_GLBL_CFG0_CQF_EN_MASK 0x1F0
+#define MME0_QM_GLBL_CFG0_CP_EN_SHIFT 9
+#define MME0_QM_GLBL_CFG0_CP_EN_MASK 0x3E00
+
+/* MME0_QM_GLBL_CFG1 */
+#define MME0_QM_GLBL_CFG1_PQF_STOP_SHIFT 0
+#define MME0_QM_GLBL_CFG1_PQF_STOP_MASK 0xF
+#define MME0_QM_GLBL_CFG1_CQF_STOP_SHIFT 4
+#define MME0_QM_GLBL_CFG1_CQF_STOP_MASK 0x1F0
+#define MME0_QM_GLBL_CFG1_CP_STOP_SHIFT 9
+#define MME0_QM_GLBL_CFG1_CP_STOP_MASK 0x3E00
+#define MME0_QM_GLBL_CFG1_PQF_FLUSH_SHIFT 16
+#define MME0_QM_GLBL_CFG1_PQF_FLUSH_MASK 0xF0000
+#define MME0_QM_GLBL_CFG1_CQF_FLUSH_SHIFT 20
+#define MME0_QM_GLBL_CFG1_CQF_FLUSH_MASK 0x1F00000
+#define MME0_QM_GLBL_CFG1_CP_FLUSH_SHIFT 25
+#define MME0_QM_GLBL_CFG1_CP_FLUSH_MASK 0x3E000000
+
+/* MME0_QM_GLBL_PROT */
+#define MME0_QM_GLBL_PROT_PQF_SHIFT 0
+#define MME0_QM_GLBL_PROT_PQF_MASK 0xF
+#define MME0_QM_GLBL_PROT_CQF_SHIFT 4
+#define MME0_QM_GLBL_PROT_CQF_MASK 0x1F0
+#define MME0_QM_GLBL_PROT_CP_SHIFT 9
+#define MME0_QM_GLBL_PROT_CP_MASK 0x3E00
+#define MME0_QM_GLBL_PROT_ERR_SHIFT 14
+#define MME0_QM_GLBL_PROT_ERR_MASK 0x4000
+#define MME0_QM_GLBL_PROT_ARB_SHIFT 15
+#define MME0_QM_GLBL_PROT_ARB_MASK 0x8000
+
+/* MME0_QM_GLBL_ERR_CFG */
+#define MME0_QM_GLBL_ERR_CFG_PQF_ERR_MSG_EN_SHIFT 0
+#define MME0_QM_GLBL_ERR_CFG_PQF_ERR_MSG_EN_MASK 0xF
+#define MME0_QM_GLBL_ERR_CFG_CQF_ERR_MSG_EN_SHIFT 4
+#define MME0_QM_GLBL_ERR_CFG_CQF_ERR_MSG_EN_MASK 0x1F0
+#define MME0_QM_GLBL_ERR_CFG_CP_ERR_MSG_EN_SHIFT 9
+#define MME0_QM_GLBL_ERR_CFG_CP_ERR_MSG_EN_MASK 0x3E00
+#define MME0_QM_GLBL_ERR_CFG_PQF_STOP_ON_ERR_SHIFT 16
+#define MME0_QM_GLBL_ERR_CFG_PQF_STOP_ON_ERR_MASK 0xF0000
+#define MME0_QM_GLBL_ERR_CFG_CQF_STOP_ON_ERR_SHIFT 20
+#define MME0_QM_GLBL_ERR_CFG_CQF_STOP_ON_ERR_MASK 0x1F00000
+#define MME0_QM_GLBL_ERR_CFG_CP_STOP_ON_ERR_SHIFT 25
+#define MME0_QM_GLBL_ERR_CFG_CP_STOP_ON_ERR_MASK 0x3E000000
+#define MME0_QM_GLBL_ERR_CFG_ARB_STOP_ON_ERR_SHIFT 31
+#define MME0_QM_GLBL_ERR_CFG_ARB_STOP_ON_ERR_MASK 0x80000000
+
+/* MME0_QM_GLBL_SECURE_PROPS */
+#define MME0_QM_GLBL_SECURE_PROPS_0_ASID_SHIFT 0
+#define MME0_QM_GLBL_SECURE_PROPS_0_ASID_MASK 0x3FF
+#define MME0_QM_GLBL_SECURE_PROPS_1_ASID_SHIFT 0
+#define MME0_QM_GLBL_SECURE_PROPS_1_ASID_MASK 0x3FF
+#define MME0_QM_GLBL_SECURE_PROPS_2_ASID_SHIFT 0
+#define MME0_QM_GLBL_SECURE_PROPS_2_ASID_MASK 0x3FF
+#define MME0_QM_GLBL_SECURE_PROPS_3_ASID_SHIFT 0
+#define MME0_QM_GLBL_SECURE_PROPS_3_ASID_MASK 0x3FF
+#define MME0_QM_GLBL_SECURE_PROPS_4_ASID_SHIFT 0
+#define MME0_QM_GLBL_SECURE_PROPS_4_ASID_MASK 0x3FF
+#define MME0_QM_GLBL_SECURE_PROPS_0_MMBP_SHIFT 10
+#define MME0_QM_GLBL_SECURE_PROPS_0_MMBP_MASK 0x400
+#define MME0_QM_GLBL_SECURE_PROPS_1_MMBP_SHIFT 10
+#define MME0_QM_GLBL_SECURE_PROPS_1_MMBP_MASK 0x400
+#define MME0_QM_GLBL_SECURE_PROPS_2_MMBP_SHIFT 10
+#define MME0_QM_GLBL_SECURE_PROPS_2_MMBP_MASK 0x400
+#define MME0_QM_GLBL_SECURE_PROPS_3_MMBP_SHIFT 10
+#define MME0_QM_GLBL_SECURE_PROPS_3_MMBP_MASK 0x400
+#define MME0_QM_GLBL_SECURE_PROPS_4_MMBP_SHIFT 10
+#define MME0_QM_GLBL_SECURE_PROPS_4_MMBP_MASK 0x400
+
+/* MME0_QM_GLBL_NON_SECURE_PROPS */
+#define MME0_QM_GLBL_NON_SECURE_PROPS_0_ASID_SHIFT 0
+#define MME0_QM_GLBL_NON_SECURE_PROPS_0_ASID_MASK 0x3FF
+#define MME0_QM_GLBL_NON_SECURE_PROPS_1_ASID_SHIFT 0
+#define MME0_QM_GLBL_NON_SECURE_PROPS_1_ASID_MASK 0x3FF
+#define MME0_QM_GLBL_NON_SECURE_PROPS_2_ASID_SHIFT 0
+#define MME0_QM_GLBL_NON_SECURE_PROPS_2_ASID_MASK 0x3FF
+#define MME0_QM_GLBL_NON_SECURE_PROPS_3_ASID_SHIFT 0
+#define MME0_QM_GLBL_NON_SECURE_PROPS_3_ASID_MASK 0x3FF
+#define MME0_QM_GLBL_NON_SECURE_PROPS_4_ASID_SHIFT 0
+#define MME0_QM_GLBL_NON_SECURE_PROPS_4_ASID_MASK 0x3FF
+#define MME0_QM_GLBL_NON_SECURE_PROPS_0_MMBP_SHIFT 10
+#define MME0_QM_GLBL_NON_SECURE_PROPS_0_MMBP_MASK 0x400
+#define MME0_QM_GLBL_NON_SECURE_PROPS_1_MMBP_SHIFT 10
+#define MME0_QM_GLBL_NON_SECURE_PROPS_1_MMBP_MASK 0x400
+#define MME0_QM_GLBL_NON_SECURE_PROPS_2_MMBP_SHIFT 10
+#define MME0_QM_GLBL_NON_SECURE_PROPS_2_MMBP_MASK 0x400
+#define MME0_QM_GLBL_NON_SECURE_PROPS_3_MMBP_SHIFT 10
+#define MME0_QM_GLBL_NON_SECURE_PROPS_3_MMBP_MASK 0x400
+#define MME0_QM_GLBL_NON_SECURE_PROPS_4_MMBP_SHIFT 10
+#define MME0_QM_GLBL_NON_SECURE_PROPS_4_MMBP_MASK 0x400
+
+/* MME0_QM_GLBL_STS0 */
+#define MME0_QM_GLBL_STS0_PQF_IDLE_SHIFT 0
+#define MME0_QM_GLBL_STS0_PQF_IDLE_MASK 0xF
+#define MME0_QM_GLBL_STS0_CQF_IDLE_SHIFT 4
+#define MME0_QM_GLBL_STS0_CQF_IDLE_MASK 0x1F0
+#define MME0_QM_GLBL_STS0_CP_IDLE_SHIFT 9
+#define MME0_QM_GLBL_STS0_CP_IDLE_MASK 0x3E00
+#define MME0_QM_GLBL_STS0_PQF_IS_STOP_SHIFT 16
+#define MME0_QM_GLBL_STS0_PQF_IS_STOP_MASK 0xF0000
+#define MME0_QM_GLBL_STS0_CQF_IS_STOP_SHIFT 20
+#define MME0_QM_GLBL_STS0_CQF_IS_STOP_MASK 0x1F00000
+#define MME0_QM_GLBL_STS0_CP_IS_STOP_SHIFT 25
+#define MME0_QM_GLBL_STS0_CP_IS_STOP_MASK 0x3E000000
+#define MME0_QM_GLBL_STS0_ARB_IS_STOP_SHIFT 31
+#define MME0_QM_GLBL_STS0_ARB_IS_STOP_MASK 0x80000000
+
+/* MME0_QM_GLBL_STS1 */
+#define MME0_QM_GLBL_STS1_PQF_RD_ERR_SHIFT 0
+#define MME0_QM_GLBL_STS1_PQF_RD_ERR_MASK 0x1
+#define MME0_QM_GLBL_STS1_CQF_RD_ERR_SHIFT 1
+#define MME0_QM_GLBL_STS1_CQF_RD_ERR_MASK 0x2
+#define MME0_QM_GLBL_STS1_CP_RD_ERR_SHIFT 2
+#define MME0_QM_GLBL_STS1_CP_RD_ERR_MASK 0x4
+#define MME0_QM_GLBL_STS1_CP_UNDEF_CMD_ERR_SHIFT 3
+#define MME0_QM_GLBL_STS1_CP_UNDEF_CMD_ERR_MASK 0x8
+#define MME0_QM_GLBL_STS1_CP_STOP_OP_SHIFT 4
+#define MME0_QM_GLBL_STS1_CP_STOP_OP_MASK 0x10
+#define MME0_QM_GLBL_STS1_CP_MSG_WR_ERR_SHIFT 5
+#define MME0_QM_GLBL_STS1_CP_MSG_WR_ERR_MASK 0x20
+#define MME0_QM_GLBL_STS1_CP_WREG_ERR_SHIFT 6
+#define MME0_QM_GLBL_STS1_CP_WREG_ERR_MASK 0x40
+#define MME0_QM_GLBL_STS1_CP_FENCE0_OVF_ERR_SHIFT 8
+#define MME0_QM_GLBL_STS1_CP_FENCE0_OVF_ERR_MASK 0x100
+#define MME0_QM_GLBL_STS1_CP_FENCE1_OVF_ERR_SHIFT 9
+#define MME0_QM_GLBL_STS1_CP_FENCE1_OVF_ERR_MASK 0x200
+#define MME0_QM_GLBL_STS1_CP_FENCE2_OVF_ERR_SHIFT 10
+#define MME0_QM_GLBL_STS1_CP_FENCE2_OVF_ERR_MASK 0x400
+#define MME0_QM_GLBL_STS1_CP_FENCE3_OVF_ERR_SHIFT 11
+#define MME0_QM_GLBL_STS1_CP_FENCE3_OVF_ERR_MASK 0x800
+#define MME0_QM_GLBL_STS1_CP_FENCE0_UDF_ERR_SHIFT 12
+#define MME0_QM_GLBL_STS1_CP_FENCE0_UDF_ERR_MASK 0x1000
+#define MME0_QM_GLBL_STS1_CP_FENCE1_UDF_ERR_SHIFT 13
+#define MME0_QM_GLBL_STS1_CP_FENCE1_UDF_ERR_MASK 0x2000
+#define MME0_QM_GLBL_STS1_CP_FENCE2_UDF_ERR_SHIFT 14
+#define MME0_QM_GLBL_STS1_CP_FENCE2_UDF_ERR_MASK 0x4000
+#define MME0_QM_GLBL_STS1_CP_FENCE3_UDF_ERR_SHIFT 15
+#define MME0_QM_GLBL_STS1_CP_FENCE3_UDF_ERR_MASK 0x8000
+
+/* MME0_QM_GLBL_STS1_4 */
+#define MME0_QM_GLBL_STS1_4_CQF_RD_ERR_SHIFT 1
+#define MME0_QM_GLBL_STS1_4_CQF_RD_ERR_MASK 0x2
+#define MME0_QM_GLBL_STS1_4_CP_RD_ERR_SHIFT 2
+#define MME0_QM_GLBL_STS1_4_CP_RD_ERR_MASK 0x4
+#define MME0_QM_GLBL_STS1_4_CP_UNDEF_CMD_ERR_SHIFT 3
+#define MME0_QM_GLBL_STS1_4_CP_UNDEF_CMD_ERR_MASK 0x8
+#define MME0_QM_GLBL_STS1_4_CP_STOP_OP_SHIFT 4
+#define MME0_QM_GLBL_STS1_4_CP_STOP_OP_MASK 0x10
+#define MME0_QM_GLBL_STS1_4_CP_MSG_WR_ERR_SHIFT 5
+#define MME0_QM_GLBL_STS1_4_CP_MSG_WR_ERR_MASK 0x20
+#define MME0_QM_GLBL_STS1_4_CP_WREG_ERR_SHIFT 6
+#define MME0_QM_GLBL_STS1_4_CP_WREG_ERR_MASK 0x40
+#define MME0_QM_GLBL_STS1_4_CP_FENCE0_OVF_ERR_SHIFT 8
+#define MME0_QM_GLBL_STS1_4_CP_FENCE0_OVF_ERR_MASK 0x100
+#define MME0_QM_GLBL_STS1_4_CP_FENCE1_OVF_ERR_SHIFT 9
+#define MME0_QM_GLBL_STS1_4_CP_FENCE1_OVF_ERR_MASK 0x200
+#define MME0_QM_GLBL_STS1_4_CP_FENCE2_OVF_ERR_SHIFT 10
+#define MME0_QM_GLBL_STS1_4_CP_FENCE2_OVF_ERR_MASK 0x400
+#define MME0_QM_GLBL_STS1_4_CP_FENCE3_OVF_ERR_SHIFT 11
+#define MME0_QM_GLBL_STS1_4_CP_FENCE3_OVF_ERR_MASK 0x800
+#define MME0_QM_GLBL_STS1_4_CP_FENCE0_UDF_ERR_SHIFT 12
+#define MME0_QM_GLBL_STS1_4_CP_FENCE0_UDF_ERR_MASK 0x1000
+#define MME0_QM_GLBL_STS1_4_CP_FENCE1_UDF_ERR_SHIFT 13
+#define MME0_QM_GLBL_STS1_4_CP_FENCE1_UDF_ERR_MASK 0x2000
+#define MME0_QM_GLBL_STS1_4_CP_FENCE2_UDF_ERR_SHIFT 14
+#define MME0_QM_GLBL_STS1_4_CP_FENCE2_UDF_ERR_MASK 0x4000
+#define MME0_QM_GLBL_STS1_4_CP_FENCE3_UDF_ERR_SHIFT 15
+#define MME0_QM_GLBL_STS1_4_CP_FENCE3_UDF_ERR_MASK 0x8000
+
+/* MME0_QM_GLBL_MSG_EN */
+#define MME0_QM_GLBL_MSG_EN_PQF_RD_ERR_SHIFT 0
+#define MME0_QM_GLBL_MSG_EN_PQF_RD_ERR_MASK 0x1
+#define MME0_QM_GLBL_MSG_EN_CQF_RD_ERR_SHIFT 1
+#define MME0_QM_GLBL_MSG_EN_CQF_RD_ERR_MASK 0x2
+#define MME0_QM_GLBL_MSG_EN_CP_RD_ERR_SHIFT 2
+#define MME0_QM_GLBL_MSG_EN_CP_RD_ERR_MASK 0x4
+#define MME0_QM_GLBL_MSG_EN_CP_UNDEF_CMD_ERR_SHIFT 3
+#define MME0_QM_GLBL_MSG_EN_CP_UNDEF_CMD_ERR_MASK 0x8
+#define MME0_QM_GLBL_MSG_EN_CP_STOP_OP_SHIFT 4
+#define MME0_QM_GLBL_MSG_EN_CP_STOP_OP_MASK 0x10
+#define MME0_QM_GLBL_MSG_EN_CP_MSG_WR_ERR_SHIFT 5
+#define MME0_QM_GLBL_MSG_EN_CP_MSG_WR_ERR_MASK 0x20
+#define MME0_QM_GLBL_MSG_EN_CP_WREG_ERR_SHIFT 6
+#define MME0_QM_GLBL_MSG_EN_CP_WREG_ERR_MASK 0x40
+#define MME0_QM_GLBL_MSG_EN_CP_FENCE0_OVF_ERR_SHIFT 8
+#define MME0_QM_GLBL_MSG_EN_CP_FENCE0_OVF_ERR_MASK 0x100
+#define MME0_QM_GLBL_MSG_EN_CP_FENCE1_OVF_ERR_SHIFT 9
+#define MME0_QM_GLBL_MSG_EN_CP_FENCE1_OVF_ERR_MASK 0x200
+#define MME0_QM_GLBL_MSG_EN_CP_FENCE2_OVF_ERR_SHIFT 10
+#define MME0_QM_GLBL_MSG_EN_CP_FENCE2_OVF_ERR_MASK 0x400
+#define MME0_QM_GLBL_MSG_EN_CP_FENCE3_OVF_ERR_SHIFT 11
+#define MME0_QM_GLBL_MSG_EN_CP_FENCE3_OVF_ERR_MASK 0x800
+#define MME0_QM_GLBL_MSG_EN_CP_FENCE0_UDF_ERR_SHIFT 12
+#define MME0_QM_GLBL_MSG_EN_CP_FENCE0_UDF_ERR_MASK 0x1000
+#define MME0_QM_GLBL_MSG_EN_CP_FENCE1_UDF_ERR_SHIFT 13
+#define MME0_QM_GLBL_MSG_EN_CP_FENCE1_UDF_ERR_MASK 0x2000
+#define MME0_QM_GLBL_MSG_EN_CP_FENCE2_UDF_ERR_SHIFT 14
+#define MME0_QM_GLBL_MSG_EN_CP_FENCE2_UDF_ERR_MASK 0x4000
+#define MME0_QM_GLBL_MSG_EN_CP_FENCE3_UDF_ERR_SHIFT 15
+#define MME0_QM_GLBL_MSG_EN_CP_FENCE3_UDF_ERR_MASK 0x8000
+
+/* MME0_QM_GLBL_MSG_EN_4 */
+#define MME0_QM_GLBL_MSG_EN_4_CQF_RD_ERR_SHIFT 1
+#define MME0_QM_GLBL_MSG_EN_4_CQF_RD_ERR_MASK 0x2
+#define MME0_QM_GLBL_MSG_EN_4_CP_RD_ERR_SHIFT 2
+#define MME0_QM_GLBL_MSG_EN_4_CP_RD_ERR_MASK 0x4
+#define MME0_QM_GLBL_MSG_EN_4_CP_UNDEF_CMD_ERR_SHIFT 3
+#define MME0_QM_GLBL_MSG_EN_4_CP_UNDEF_CMD_ERR_MASK 0x8
+#define MME0_QM_GLBL_MSG_EN_4_CP_STOP_OP_SHIFT 4
+#define MME0_QM_GLBL_MSG_EN_4_CP_STOP_OP_MASK 0x10
+#define MME0_QM_GLBL_MSG_EN_4_CP_MSG_WR_ERR_SHIFT 5
+#define MME0_QM_GLBL_MSG_EN_4_CP_MSG_WR_ERR_MASK 0x20
+#define MME0_QM_GLBL_MSG_EN_4_CP_WREG_ERR_SHIFT 6
+#define MME0_QM_GLBL_MSG_EN_4_CP_WREG_ERR_MASK 0x40
+#define MME0_QM_GLBL_MSG_EN_4_CP_FENCE0_OVF_ERR_SHIFT 8
+#define MME0_QM_GLBL_MSG_EN_4_CP_FENCE0_OVF_ERR_MASK 0x100
+#define MME0_QM_GLBL_MSG_EN_4_CP_FENCE1_OVF_ERR_SHIFT 9
+#define MME0_QM_GLBL_MSG_EN_4_CP_FENCE1_OVF_ERR_MASK 0x200
+#define MME0_QM_GLBL_MSG_EN_4_CP_FENCE2_OVF_ERR_SHIFT 10
+#define MME0_QM_GLBL_MSG_EN_4_CP_FENCE2_OVF_ERR_MASK 0x400
+#define MME0_QM_GLBL_MSG_EN_4_CP_FENCE3_OVF_ERR_SHIFT 11
+#define MME0_QM_GLBL_MSG_EN_4_CP_FENCE3_OVF_ERR_MASK 0x800
+#define MME0_QM_GLBL_MSG_EN_4_CP_FENCE0_UDF_ERR_SHIFT 12
+#define MME0_QM_GLBL_MSG_EN_4_CP_FENCE0_UDF_ERR_MASK 0x1000
+#define MME0_QM_GLBL_MSG_EN_4_CP_FENCE1_UDF_ERR_SHIFT 13
+#define MME0_QM_GLBL_MSG_EN_4_CP_FENCE1_UDF_ERR_MASK 0x2000
+#define MME0_QM_GLBL_MSG_EN_4_CP_FENCE2_UDF_ERR_SHIFT 14
+#define MME0_QM_GLBL_MSG_EN_4_CP_FENCE2_UDF_ERR_MASK 0x4000
+#define MME0_QM_GLBL_MSG_EN_4_CP_FENCE3_UDF_ERR_SHIFT 15
+#define MME0_QM_GLBL_MSG_EN_4_CP_FENCE3_UDF_ERR_MASK 0x8000
+
+/* MME0_QM_PQ_BASE_LO */
+#define MME0_QM_PQ_BASE_LO_VAL_SHIFT 0
+#define MME0_QM_PQ_BASE_LO_VAL_MASK 0xFFFFFFFF
+
+/* MME0_QM_PQ_BASE_HI */
+#define MME0_QM_PQ_BASE_HI_VAL_SHIFT 0
+#define MME0_QM_PQ_BASE_HI_VAL_MASK 0xFFFFFFFF
+
+/* MME0_QM_PQ_SIZE */
+#define MME0_QM_PQ_SIZE_VAL_SHIFT 0
+#define MME0_QM_PQ_SIZE_VAL_MASK 0xFFFFFFFF
+
+/* MME0_QM_PQ_PI */
+#define MME0_QM_PQ_PI_VAL_SHIFT 0
+#define MME0_QM_PQ_PI_VAL_MASK 0xFFFFFFFF
+
+/* MME0_QM_PQ_CI */
+#define MME0_QM_PQ_CI_VAL_SHIFT 0
+#define MME0_QM_PQ_CI_VAL_MASK 0xFFFFFFFF
+
+/* MME0_QM_PQ_CFG0 */
+#define MME0_QM_PQ_CFG0_RESERVED_SHIFT 0
+#define MME0_QM_PQ_CFG0_RESERVED_MASK 0x1
+
+/* MME0_QM_PQ_CFG1 */
+#define MME0_QM_PQ_CFG1_CREDIT_LIM_SHIFT 0
+#define MME0_QM_PQ_CFG1_CREDIT_LIM_MASK 0xFFFF
+#define MME0_QM_PQ_CFG1_MAX_INFLIGHT_SHIFT 16
+#define MME0_QM_PQ_CFG1_MAX_INFLIGHT_MASK 0xFFFF0000
+
+/* MME0_QM_PQ_ARUSER_31_11 */
+#define MME0_QM_PQ_ARUSER_31_11_VAL_SHIFT 0
+#define MME0_QM_PQ_ARUSER_31_11_VAL_MASK 0x1FFFFF
+
+/* MME0_QM_PQ_STS0 */
+#define MME0_QM_PQ_STS0_PQ_CREDIT_CNT_SHIFT 0
+#define MME0_QM_PQ_STS0_PQ_CREDIT_CNT_MASK 0xFFFF
+#define MME0_QM_PQ_STS0_PQ_FREE_CNT_SHIFT 16
+#define MME0_QM_PQ_STS0_PQ_FREE_CNT_MASK 0xFFFF0000
+
+/* MME0_QM_PQ_STS1 */
+#define MME0_QM_PQ_STS1_PQ_INFLIGHT_CNT_SHIFT 0
+#define MME0_QM_PQ_STS1_PQ_INFLIGHT_CNT_MASK 0xFFFF
+#define MME0_QM_PQ_STS1_PQ_BUF_EMPTY_SHIFT 30
+#define MME0_QM_PQ_STS1_PQ_BUF_EMPTY_MASK 0x40000000
+#define MME0_QM_PQ_STS1_PQ_BUSY_SHIFT 31
+#define MME0_QM_PQ_STS1_PQ_BUSY_MASK 0x80000000
+
+/* MME0_QM_CQ_CFG0 */
+#define MME0_QM_CQ_CFG0_RESERVED_SHIFT 0
+#define MME0_QM_CQ_CFG0_RESERVED_MASK 0x1
+
+/* MME0_QM_CQ_CFG1 */
+#define MME0_QM_CQ_CFG1_CREDIT_LIM_SHIFT 0
+#define MME0_QM_CQ_CFG1_CREDIT_LIM_MASK 0xFFFF
+#define MME0_QM_CQ_CFG1_MAX_INFLIGHT_SHIFT 16
+#define MME0_QM_CQ_CFG1_MAX_INFLIGHT_MASK 0xFFFF0000
+
+/* MME0_QM_CQ_ARUSER_31_11 */
+#define MME0_QM_CQ_ARUSER_31_11_VAL_SHIFT 0
+#define MME0_QM_CQ_ARUSER_31_11_VAL_MASK 0x1FFFFF
+
+/* MME0_QM_CQ_STS0 */
+#define MME0_QM_CQ_STS0_CQ_CREDIT_CNT_SHIFT 0
+#define MME0_QM_CQ_STS0_CQ_CREDIT_CNT_MASK 0xFFFF
+#define MME0_QM_CQ_STS0_CQ_FREE_CNT_SHIFT 16
+#define MME0_QM_CQ_STS0_CQ_FREE_CNT_MASK 0xFFFF0000
+
+/* MME0_QM_CQ_STS1 */
+#define MME0_QM_CQ_STS1_CQ_INFLIGHT_CNT_SHIFT 0
+#define MME0_QM_CQ_STS1_CQ_INFLIGHT_CNT_MASK 0xFFFF
+#define MME0_QM_CQ_STS1_CQ_BUF_EMPTY_SHIFT 30
+#define MME0_QM_CQ_STS1_CQ_BUF_EMPTY_MASK 0x40000000
+#define MME0_QM_CQ_STS1_CQ_BUSY_SHIFT 31
+#define MME0_QM_CQ_STS1_CQ_BUSY_MASK 0x80000000
+
+/* MME0_QM_CQ_PTR_LO_0 */
+#define MME0_QM_CQ_PTR_LO_0_VAL_SHIFT 0
+#define MME0_QM_CQ_PTR_LO_0_VAL_MASK 0xFFFFFFFF
+
+/* MME0_QM_CQ_PTR_HI_0 */
+#define MME0_QM_CQ_PTR_HI_0_VAL_SHIFT 0
+#define MME0_QM_CQ_PTR_HI_0_VAL_MASK 0xFFFFFFFF
+
+/* MME0_QM_CQ_TSIZE_0 */
+#define MME0_QM_CQ_TSIZE_0_VAL_SHIFT 0
+#define MME0_QM_CQ_TSIZE_0_VAL_MASK 0xFFFFFFFF
+
+/* MME0_QM_CQ_CTL_0 */
+#define MME0_QM_CQ_CTL_0_RPT_SHIFT 0
+#define MME0_QM_CQ_CTL_0_RPT_MASK 0xFFFF
+#define MME0_QM_CQ_CTL_0_CTL_SHIFT 16
+#define MME0_QM_CQ_CTL_0_CTL_MASK 0xFFFF0000
+
+/* MME0_QM_CQ_PTR_LO_1 */
+#define MME0_QM_CQ_PTR_LO_1_VAL_SHIFT 0
+#define MME0_QM_CQ_PTR_LO_1_VAL_MASK 0xFFFFFFFF
+
+/* MME0_QM_CQ_PTR_HI_1 */
+#define MME0_QM_CQ_PTR_HI_1_VAL_SHIFT 0
+#define MME0_QM_CQ_PTR_HI_1_VAL_MASK 0xFFFFFFFF
+
+/* MME0_QM_CQ_TSIZE_1 */
+#define MME0_QM_CQ_TSIZE_1_VAL_SHIFT 0
+#define MME0_QM_CQ_TSIZE_1_VAL_MASK 0xFFFFFFFF
+
+/* MME0_QM_CQ_CTL_1 */
+#define MME0_QM_CQ_CTL_1_RPT_SHIFT 0
+#define MME0_QM_CQ_CTL_1_RPT_MASK 0xFFFF
+#define MME0_QM_CQ_CTL_1_CTL_SHIFT 16
+#define MME0_QM_CQ_CTL_1_CTL_MASK 0xFFFF0000
+
+/* MME0_QM_CQ_PTR_LO_2 */
+#define MME0_QM_CQ_PTR_LO_2_VAL_SHIFT 0
+#define MME0_QM_CQ_PTR_LO_2_VAL_MASK 0xFFFFFFFF
+
+/* MME0_QM_CQ_PTR_HI_2 */
+#define MME0_QM_CQ_PTR_HI_2_VAL_SHIFT 0
+#define MME0_QM_CQ_PTR_HI_2_VAL_MASK 0xFFFFFFFF
+
+/* MME0_QM_CQ_TSIZE_2 */
+#define MME0_QM_CQ_TSIZE_2_VAL_SHIFT 0
+#define MME0_QM_CQ_TSIZE_2_VAL_MASK 0xFFFFFFFF
+
+/* MME0_QM_CQ_CTL_2 */
+#define MME0_QM_CQ_CTL_2_RPT_SHIFT 0
+#define MME0_QM_CQ_CTL_2_RPT_MASK 0xFFFF
+#define MME0_QM_CQ_CTL_2_CTL_SHIFT 16
+#define MME0_QM_CQ_CTL_2_CTL_MASK 0xFFFF0000
+
+/* MME0_QM_CQ_PTR_LO_3 */
+#define MME0_QM_CQ_PTR_LO_3_VAL_SHIFT 0
+#define MME0_QM_CQ_PTR_LO_3_VAL_MASK 0xFFFFFFFF
+
+/* MME0_QM_CQ_PTR_HI_3 */
+#define MME0_QM_CQ_PTR_HI_3_VAL_SHIFT 0
+#define MME0_QM_CQ_PTR_HI_3_VAL_MASK 0xFFFFFFFF
+
+/* MME0_QM_CQ_TSIZE_3 */
+#define MME0_QM_CQ_TSIZE_3_VAL_SHIFT 0
+#define MME0_QM_CQ_TSIZE_3_VAL_MASK 0xFFFFFFFF
+
+/* MME0_QM_CQ_CTL_3 */
+#define MME0_QM_CQ_CTL_3_RPT_SHIFT 0
+#define MME0_QM_CQ_CTL_3_RPT_MASK 0xFFFF
+#define MME0_QM_CQ_CTL_3_CTL_SHIFT 16
+#define MME0_QM_CQ_CTL_3_CTL_MASK 0xFFFF0000
+
+/* MME0_QM_CQ_PTR_LO_4 */
+#define MME0_QM_CQ_PTR_LO_4_VAL_SHIFT 0
+#define MME0_QM_CQ_PTR_LO_4_VAL_MASK 0xFFFFFFFF
+
+/* MME0_QM_CQ_PTR_HI_4 */
+#define MME0_QM_CQ_PTR_HI_4_VAL_SHIFT 0
+#define MME0_QM_CQ_PTR_HI_4_VAL_MASK 0xFFFFFFFF
+
+/* MME0_QM_CQ_TSIZE_4 */
+#define MME0_QM_CQ_TSIZE_4_VAL_SHIFT 0
+#define MME0_QM_CQ_TSIZE_4_VAL_MASK 0xFFFFFFFF
+
+/* MME0_QM_CQ_CTL_4 */
+#define MME0_QM_CQ_CTL_4_RPT_SHIFT 0
+#define MME0_QM_CQ_CTL_4_RPT_MASK 0xFFFF
+#define MME0_QM_CQ_CTL_4_CTL_SHIFT 16
+#define MME0_QM_CQ_CTL_4_CTL_MASK 0xFFFF0000
+
+/* MME0_QM_CQ_PTR_LO_STS */
+#define MME0_QM_CQ_PTR_LO_STS_VAL_SHIFT 0
+#define MME0_QM_CQ_PTR_LO_STS_VAL_MASK 0xFFFFFFFF
+
+/* MME0_QM_CQ_PTR_HI_STS */
+#define MME0_QM_CQ_PTR_HI_STS_VAL_SHIFT 0
+#define MME0_QM_CQ_PTR_HI_STS_VAL_MASK 0xFFFFFFFF
+
+/* MME0_QM_CQ_TSIZE_STS */
+#define MME0_QM_CQ_TSIZE_STS_VAL_SHIFT 0
+#define MME0_QM_CQ_TSIZE_STS_VAL_MASK 0xFFFFFFFF
+
+/* MME0_QM_CQ_CTL_STS */
+#define MME0_QM_CQ_CTL_STS_RPT_SHIFT 0
+#define MME0_QM_CQ_CTL_STS_RPT_MASK 0xFFFF
+#define MME0_QM_CQ_CTL_STS_CTL_SHIFT 16
+#define MME0_QM_CQ_CTL_STS_CTL_MASK 0xFFFF0000
+
+/* MME0_QM_CQ_IFIFO_CNT */
+#define MME0_QM_CQ_IFIFO_CNT_VAL_SHIFT 0
+#define MME0_QM_CQ_IFIFO_CNT_VAL_MASK 0x3
+
+/* MME0_QM_CP_MSG_BASE0_ADDR_LO */
+#define MME0_QM_CP_MSG_BASE0_ADDR_LO_VAL_SHIFT 0
+#define MME0_QM_CP_MSG_BASE0_ADDR_LO_VAL_MASK 0xFFFFFFFF
+
+/* MME0_QM_CP_MSG_BASE0_ADDR_HI */
+#define MME0_QM_CP_MSG_BASE0_ADDR_HI_VAL_SHIFT 0
+#define MME0_QM_CP_MSG_BASE0_ADDR_HI_VAL_MASK 0xFFFFFFFF
+
+/* MME0_QM_CP_MSG_BASE1_ADDR_LO */
+#define MME0_QM_CP_MSG_BASE1_ADDR_LO_VAL_SHIFT 0
+#define MME0_QM_CP_MSG_BASE1_ADDR_LO_VAL_MASK 0xFFFFFFFF
+
+/* MME0_QM_CP_MSG_BASE1_ADDR_HI */
+#define MME0_QM_CP_MSG_BASE1_ADDR_HI_VAL_SHIFT 0
+#define MME0_QM_CP_MSG_BASE1_ADDR_HI_VAL_MASK 0xFFFFFFFF
+
+/* MME0_QM_CP_MSG_BASE2_ADDR_LO */
+#define MME0_QM_CP_MSG_BASE2_ADDR_LO_VAL_SHIFT 0
+#define MME0_QM_CP_MSG_BASE2_ADDR_LO_VAL_MASK 0xFFFFFFFF
+
+/* MME0_QM_CP_MSG_BASE2_ADDR_HI */
+#define MME0_QM_CP_MSG_BASE2_ADDR_HI_VAL_SHIFT 0
+#define MME0_QM_CP_MSG_BASE2_ADDR_HI_VAL_MASK 0xFFFFFFFF
+
+/* MME0_QM_CP_MSG_BASE3_ADDR_LO */
+#define MME0_QM_CP_MSG_BASE3_ADDR_LO_VAL_SHIFT 0
+#define MME0_QM_CP_MSG_BASE3_ADDR_LO_VAL_MASK 0xFFFFFFFF
+
+/* MME0_QM_CP_MSG_BASE3_ADDR_HI */
+#define MME0_QM_CP_MSG_BASE3_ADDR_HI_VAL_SHIFT 0
+#define MME0_QM_CP_MSG_BASE3_ADDR_HI_VAL_MASK 0xFFFFFFFF
+
+/* MME0_QM_CP_LDMA_TSIZE_OFFSET */
+#define MME0_QM_CP_LDMA_TSIZE_OFFSET_VAL_SHIFT 0
+#define MME0_QM_CP_LDMA_TSIZE_OFFSET_VAL_MASK 0xFFFFFFFF
+
+/* MME0_QM_CP_LDMA_SRC_BASE_LO_OFFSET */
+#define MME0_QM_CP_LDMA_SRC_BASE_LO_OFFSET_VAL_SHIFT 0
+#define MME0_QM_CP_LDMA_SRC_BASE_LO_OFFSET_VAL_MASK 0xFFFFFFFF
+
+/* MME0_QM_CP_LDMA_DST_BASE_LO_OFFSET */
+#define MME0_QM_CP_LDMA_DST_BASE_LO_OFFSET_VAL_SHIFT 0
+#define MME0_QM_CP_LDMA_DST_BASE_LO_OFFSET_VAL_MASK 0xFFFFFFFF
+
+/* MME0_QM_CP_FENCE0_RDATA */
+#define MME0_QM_CP_FENCE0_RDATA_INC_VAL_SHIFT 0
+#define MME0_QM_CP_FENCE0_RDATA_INC_VAL_MASK 0xF
+
+/* MME0_QM_CP_FENCE1_RDATA */
+#define MME0_QM_CP_FENCE1_RDATA_INC_VAL_SHIFT 0
+#define MME0_QM_CP_FENCE1_RDATA_INC_VAL_MASK 0xF
+
+/* MME0_QM_CP_FENCE2_RDATA */
+#define MME0_QM_CP_FENCE2_RDATA_INC_VAL_SHIFT 0
+#define MME0_QM_CP_FENCE2_RDATA_INC_VAL_MASK 0xF
+
+/* MME0_QM_CP_FENCE3_RDATA */
+#define MME0_QM_CP_FENCE3_RDATA_INC_VAL_SHIFT 0
+#define MME0_QM_CP_FENCE3_RDATA_INC_VAL_MASK 0xF
+
+/* MME0_QM_CP_FENCE0_CNT */
+#define MME0_QM_CP_FENCE0_CNT_VAL_SHIFT 0
+#define MME0_QM_CP_FENCE0_CNT_VAL_MASK 0x3FFF
+
+/* MME0_QM_CP_FENCE1_CNT */
+#define MME0_QM_CP_FENCE1_CNT_VAL_SHIFT 0
+#define MME0_QM_CP_FENCE1_CNT_VAL_MASK 0x3FFF
+
+/* MME0_QM_CP_FENCE2_CNT */
+#define MME0_QM_CP_FENCE2_CNT_VAL_SHIFT 0
+#define MME0_QM_CP_FENCE2_CNT_VAL_MASK 0x3FFF
+
+/* MME0_QM_CP_FENCE3_CNT */
+#define MME0_QM_CP_FENCE3_CNT_VAL_SHIFT 0
+#define MME0_QM_CP_FENCE3_CNT_VAL_MASK 0x3FFF
+
+/* MME0_QM_CP_STS */
+#define MME0_QM_CP_STS_MSG_INFLIGHT_CNT_SHIFT 0
+#define MME0_QM_CP_STS_MSG_INFLIGHT_CNT_MASK 0xFFFF
+#define MME0_QM_CP_STS_ERDY_SHIFT 16
+#define MME0_QM_CP_STS_ERDY_MASK 0x10000
+#define MME0_QM_CP_STS_RRDY_SHIFT 17
+#define MME0_QM_CP_STS_RRDY_MASK 0x20000
+#define MME0_QM_CP_STS_MRDY_SHIFT 18
+#define MME0_QM_CP_STS_MRDY_MASK 0x40000
+#define MME0_QM_CP_STS_SW_STOP_SHIFT 19
+#define MME0_QM_CP_STS_SW_STOP_MASK 0x80000
+#define MME0_QM_CP_STS_FENCE_ID_SHIFT 20
+#define MME0_QM_CP_STS_FENCE_ID_MASK 0x300000
+#define MME0_QM_CP_STS_FENCE_IN_PROGRESS_SHIFT 22
+#define MME0_QM_CP_STS_FENCE_IN_PROGRESS_MASK 0x400000
+
+/* MME0_QM_CP_CURRENT_INST_LO */
+#define MME0_QM_CP_CURRENT_INST_LO_VAL_SHIFT 0
+#define MME0_QM_CP_CURRENT_INST_LO_VAL_MASK 0xFFFFFFFF
+
+/* MME0_QM_CP_CURRENT_INST_HI */
+#define MME0_QM_CP_CURRENT_INST_HI_VAL_SHIFT 0
+#define MME0_QM_CP_CURRENT_INST_HI_VAL_MASK 0xFFFFFFFF
+
+/* MME0_QM_CP_BARRIER_CFG */
+#define MME0_QM_CP_BARRIER_CFG_EBGUARD_SHIFT 0
+#define MME0_QM_CP_BARRIER_CFG_EBGUARD_MASK 0xFFF
+#define MME0_QM_CP_BARRIER_CFG_RBGUARD_SHIFT 16
+#define MME0_QM_CP_BARRIER_CFG_RBGUARD_MASK 0xF0000
+
+/* MME0_QM_CP_DBG_0 */
+#define MME0_QM_CP_DBG_0_CS_SHIFT 0
+#define MME0_QM_CP_DBG_0_CS_MASK 0xF
+#define MME0_QM_CP_DBG_0_EB_CNT_NOT_ZERO_SHIFT 4
+#define MME0_QM_CP_DBG_0_EB_CNT_NOT_ZERO_MASK 0x10
+#define MME0_QM_CP_DBG_0_BULK_CNT_NOT_ZERO_SHIFT 5
+#define MME0_QM_CP_DBG_0_BULK_CNT_NOT_ZERO_MASK 0x20
+#define MME0_QM_CP_DBG_0_MREB_STALL_SHIFT 6
+#define MME0_QM_CP_DBG_0_MREB_STALL_MASK 0x40
+#define MME0_QM_CP_DBG_0_STALL_SHIFT 7
+#define MME0_QM_CP_DBG_0_STALL_MASK 0x80
+
+/* MME0_QM_CP_ARUSER_31_11 */
+#define MME0_QM_CP_ARUSER_31_11_VAL_SHIFT 0
+#define MME0_QM_CP_ARUSER_31_11_VAL_MASK 0x1FFFFF
+
+/* MME0_QM_CP_AWUSER_31_11 */
+#define MME0_QM_CP_AWUSER_31_11_VAL_SHIFT 0
+#define MME0_QM_CP_AWUSER_31_11_VAL_MASK 0x1FFFFF
+
+/* MME0_QM_ARB_CFG_0 */
+#define MME0_QM_ARB_CFG_0_TYPE_SHIFT 0
+#define MME0_QM_ARB_CFG_0_TYPE_MASK 0x1
+#define MME0_QM_ARB_CFG_0_IS_MASTER_SHIFT 4
+#define MME0_QM_ARB_CFG_0_IS_MASTER_MASK 0x10
+#define MME0_QM_ARB_CFG_0_EN_SHIFT 8
+#define MME0_QM_ARB_CFG_0_EN_MASK 0x100
+#define MME0_QM_ARB_CFG_0_MASK_SHIFT 12
+#define MME0_QM_ARB_CFG_0_MASK_MASK 0xF000
+#define MME0_QM_ARB_CFG_0_MST_MSG_NOSTALL_SHIFT 16
+#define MME0_QM_ARB_CFG_0_MST_MSG_NOSTALL_MASK 0x10000
+
+/* MME0_QM_ARB_CHOISE_Q_PUSH */
+#define MME0_QM_ARB_CHOISE_Q_PUSH_VAL_SHIFT 0
+#define MME0_QM_ARB_CHOISE_Q_PUSH_VAL_MASK 0x3
+
+/* MME0_QM_ARB_WRR_WEIGHT */
+#define MME0_QM_ARB_WRR_WEIGHT_VAL_SHIFT 0
+#define MME0_QM_ARB_WRR_WEIGHT_VAL_MASK 0xFFFFFFFF
+
+/* MME0_QM_ARB_CFG_1 */
+#define MME0_QM_ARB_CFG_1_CLR_SHIFT 0
+#define MME0_QM_ARB_CFG_1_CLR_MASK 0x1
+
+/* MME0_QM_ARB_MST_AVAIL_CRED */
+#define MME0_QM_ARB_MST_AVAIL_CRED_VAL_SHIFT 0
+#define MME0_QM_ARB_MST_AVAIL_CRED_VAL_MASK 0x7F
+
+/* MME0_QM_ARB_MST_CRED_INC */
+#define MME0_QM_ARB_MST_CRED_INC_VAL_SHIFT 0
+#define MME0_QM_ARB_MST_CRED_INC_VAL_MASK 0xFFFFFFFF
+
+/* MME0_QM_ARB_MST_CHOISE_PUSH_OFST */
+#define MME0_QM_ARB_MST_CHOISE_PUSH_OFST_VAL_SHIFT 0
+#define MME0_QM_ARB_MST_CHOISE_PUSH_OFST_VAL_MASK 0xFFFFFFFF
+
+/* MME0_QM_ARB_SLV_MASTER_INC_CRED_OFST */
+#define MME0_QM_ARB_SLV_MASTER_INC_CRED_OFST_VAL_SHIFT 0
+#define MME0_QM_ARB_SLV_MASTER_INC_CRED_OFST_VAL_MASK 0xFFFFFFFF
+
+/* MME0_QM_ARB_MST_SLAVE_EN */
+#define MME0_QM_ARB_MST_SLAVE_EN_VAL_SHIFT 0
+#define MME0_QM_ARB_MST_SLAVE_EN_VAL_MASK 0xFFFFFFFF
+
+/* MME0_QM_ARB_MST_QUIET_PER */
+#define MME0_QM_ARB_MST_QUIET_PER_VAL_SHIFT 0
+#define MME0_QM_ARB_MST_QUIET_PER_VAL_MASK 0xFFFFFFFF
+
+/* MME0_QM_ARB_SLV_CHOISE_WDT */
+#define MME0_QM_ARB_SLV_CHOISE_WDT_VAL_SHIFT 0
+#define MME0_QM_ARB_SLV_CHOISE_WDT_VAL_MASK 0xFFFFFFFF
+
+/* MME0_QM_ARB_SLV_ID */
+#define MME0_QM_ARB_SLV_ID_VAL_SHIFT 0
+#define MME0_QM_ARB_SLV_ID_VAL_MASK 0x1F
+
+/* MME0_QM_ARB_MSG_MAX_INFLIGHT */
+#define MME0_QM_ARB_MSG_MAX_INFLIGHT_VAL_SHIFT 0
+#define MME0_QM_ARB_MSG_MAX_INFLIGHT_VAL_MASK 0x3F
+
+/* MME0_QM_ARB_MSG_AWUSER_31_11 */
+#define MME0_QM_ARB_MSG_AWUSER_31_11_VAL_SHIFT 0
+#define MME0_QM_ARB_MSG_AWUSER_31_11_VAL_MASK 0x1FFFFF
+
+/* MME0_QM_ARB_MSG_AWUSER_SEC_PROP */
+#define MME0_QM_ARB_MSG_AWUSER_SEC_PROP_ASID_SHIFT 0
+#define MME0_QM_ARB_MSG_AWUSER_SEC_PROP_ASID_MASK 0x3FF
+#define MME0_QM_ARB_MSG_AWUSER_SEC_PROP_MMBP_SHIFT 10
+#define MME0_QM_ARB_MSG_AWUSER_SEC_PROP_MMBP_MASK 0x400
+
+/* MME0_QM_ARB_MSG_AWUSER_NON_SEC_PROP */
+#define MME0_QM_ARB_MSG_AWUSER_NON_SEC_PROP_ASID_SHIFT 0
+#define MME0_QM_ARB_MSG_AWUSER_NON_SEC_PROP_ASID_MASK 0x3FF
+#define MME0_QM_ARB_MSG_AWUSER_NON_SEC_PROP_MMBP_SHIFT 10
+#define MME0_QM_ARB_MSG_AWUSER_NON_SEC_PROP_MMBP_MASK 0x400
+
+/* MME0_QM_ARB_BASE_LO */
+#define MME0_QM_ARB_BASE_LO_VAL_SHIFT 0
+#define MME0_QM_ARB_BASE_LO_VAL_MASK 0xFFFFFFFF
+
+/* MME0_QM_ARB_BASE_HI */
+#define MME0_QM_ARB_BASE_HI_VAL_SHIFT 0
+#define MME0_QM_ARB_BASE_HI_VAL_MASK 0xFFFFFFFF
+
+/* MME0_QM_ARB_STATE_STS */
+#define MME0_QM_ARB_STATE_STS_VAL_SHIFT 0
+#define MME0_QM_ARB_STATE_STS_VAL_MASK 0xFFFFFFFF
+
+/* MME0_QM_ARB_CHOISE_FULLNESS_STS */
+#define MME0_QM_ARB_CHOISE_FULLNESS_STS_VAL_SHIFT 0
+#define MME0_QM_ARB_CHOISE_FULLNESS_STS_VAL_MASK 0x7F
+
+/* MME0_QM_ARB_MSG_STS */
+#define MME0_QM_ARB_MSG_STS_FULL_SHIFT 0
+#define MME0_QM_ARB_MSG_STS_FULL_MASK 0x1
+#define MME0_QM_ARB_MSG_STS_NO_INFLIGHT_SHIFT 1
+#define MME0_QM_ARB_MSG_STS_NO_INFLIGHT_MASK 0x2
+
+/* MME0_QM_ARB_SLV_CHOISE_Q_HEAD */
+#define MME0_QM_ARB_SLV_CHOISE_Q_HEAD_VAL_SHIFT 0
+#define MME0_QM_ARB_SLV_CHOISE_Q_HEAD_VAL_MASK 0x3
+
+/* MME0_QM_ARB_ERR_CAUSE */
+#define MME0_QM_ARB_ERR_CAUSE_CHOISE_OVF_SHIFT 0
+#define MME0_QM_ARB_ERR_CAUSE_CHOISE_OVF_MASK 0x1
+#define MME0_QM_ARB_ERR_CAUSE_CHOISE_WDT_SHIFT 1
+#define MME0_QM_ARB_ERR_CAUSE_CHOISE_WDT_MASK 0x2
+#define MME0_QM_ARB_ERR_CAUSE_AXI_LBW_ERR_SHIFT 2
+#define MME0_QM_ARB_ERR_CAUSE_AXI_LBW_ERR_MASK 0x4
+
+/* MME0_QM_ARB_ERR_MSG_EN */
+#define MME0_QM_ARB_ERR_MSG_EN_CHOISE_OVF_SHIFT 0
+#define MME0_QM_ARB_ERR_MSG_EN_CHOISE_OVF_MASK 0x1
+#define MME0_QM_ARB_ERR_MSG_EN_CHOISE_WDT_SHIFT 1
+#define MME0_QM_ARB_ERR_MSG_EN_CHOISE_WDT_MASK 0x2
+#define MME0_QM_ARB_ERR_MSG_EN_AXI_LBW_ERR_SHIFT 2
+#define MME0_QM_ARB_ERR_MSG_EN_AXI_LBW_ERR_MASK 0x4
+
+/* MME0_QM_ARB_ERR_STS_DRP */
+#define MME0_QM_ARB_ERR_STS_DRP_VAL_SHIFT 0
+#define MME0_QM_ARB_ERR_STS_DRP_VAL_MASK 0x3
+
+/* MME0_QM_ARB_MST_CRED_STS */
+#define MME0_QM_ARB_MST_CRED_STS_VAL_SHIFT 0
+#define MME0_QM_ARB_MST_CRED_STS_VAL_MASK 0x7F
+
+/* MME0_QM_CGM_CFG */
+#define MME0_QM_CGM_CFG_IDLE_TH_SHIFT 0
+#define MME0_QM_CGM_CFG_IDLE_TH_MASK 0xFFF
+#define MME0_QM_CGM_CFG_G2F_TH_SHIFT 16
+#define MME0_QM_CGM_CFG_G2F_TH_MASK 0xFF0000
+#define MME0_QM_CGM_CFG_CP_IDLE_MASK_SHIFT 24
+#define MME0_QM_CGM_CFG_CP_IDLE_MASK_MASK 0x1F000000
+#define MME0_QM_CGM_CFG_EN_SHIFT 31
+#define MME0_QM_CGM_CFG_EN_MASK 0x80000000
+
+/* MME0_QM_CGM_STS */
+#define MME0_QM_CGM_STS_ST_SHIFT 0
+#define MME0_QM_CGM_STS_ST_MASK 0x3
+#define MME0_QM_CGM_STS_CG_SHIFT 4
+#define MME0_QM_CGM_STS_CG_MASK 0x10
+#define MME0_QM_CGM_STS_AGENT_IDLE_SHIFT 8
+#define MME0_QM_CGM_STS_AGENT_IDLE_MASK 0x100
+#define MME0_QM_CGM_STS_AXI_IDLE_SHIFT 9
+#define MME0_QM_CGM_STS_AXI_IDLE_MASK 0x200
+#define MME0_QM_CGM_STS_CP_IDLE_SHIFT 10
+#define MME0_QM_CGM_STS_CP_IDLE_MASK 0x400
+
+/* MME0_QM_CGM_CFG1 */
+#define MME0_QM_CGM_CFG1_MASK_TH_SHIFT 0
+#define MME0_QM_CGM_CFG1_MASK_TH_MASK 0xFF
+
+/* MME0_QM_LOCAL_RANGE_BASE */
+#define MME0_QM_LOCAL_RANGE_BASE_VAL_SHIFT 0
+#define MME0_QM_LOCAL_RANGE_BASE_VAL_MASK 0xFFFF
+
+/* MME0_QM_LOCAL_RANGE_SIZE */
+#define MME0_QM_LOCAL_RANGE_SIZE_VAL_SHIFT 0
+#define MME0_QM_LOCAL_RANGE_SIZE_VAL_MASK 0xFFFF
+
+/* MME0_QM_CSMR_STRICT_PRIO_CFG */
+#define MME0_QM_CSMR_STRICT_PRIO_CFG_TYPE_SHIFT 0
+#define MME0_QM_CSMR_STRICT_PRIO_CFG_TYPE_MASK 0x1
+
+/* MME0_QM_HBW_RD_RATE_LIM_CFG_1 */
+#define MME0_QM_HBW_RD_RATE_LIM_CFG_1_TOUT_SHIFT 0
+#define MME0_QM_HBW_RD_RATE_LIM_CFG_1_TOUT_MASK 0xFF
+#define MME0_QM_HBW_RD_RATE_LIM_CFG_1_EN_SHIFT 31
+#define MME0_QM_HBW_RD_RATE_LIM_CFG_1_EN_MASK 0x80000000
+
+/* MME0_QM_LBW_WR_RATE_LIM_CFG_0 */
+#define MME0_QM_LBW_WR_RATE_LIM_CFG_0_RST_TOKEN_SHIFT 0
+#define MME0_QM_LBW_WR_RATE_LIM_CFG_0_RST_TOKEN_MASK 0xFF
+#define MME0_QM_LBW_WR_RATE_LIM_CFG_0_SAT_SHIFT 16
+#define MME0_QM_LBW_WR_RATE_LIM_CFG_0_SAT_MASK 0xFF0000
+
+/* MME0_QM_LBW_WR_RATE_LIM_CFG_1 */
+#define MME0_QM_LBW_WR_RATE_LIM_CFG_1_TOUT_SHIFT 0
+#define MME0_QM_LBW_WR_RATE_LIM_CFG_1_TOUT_MASK 0xFF
+#define MME0_QM_LBW_WR_RATE_LIM_CFG_1_EN_SHIFT 31
+#define MME0_QM_LBW_WR_RATE_LIM_CFG_1_EN_MASK 0x80000000
+
+/* MME0_QM_HBW_RD_RATE_LIM_CFG_0 */
+#define MME0_QM_HBW_RD_RATE_LIM_CFG_0_RST_TOKEN_SHIFT 0
+#define MME0_QM_HBW_RD_RATE_LIM_CFG_0_RST_TOKEN_MASK 0xFF
+#define MME0_QM_HBW_RD_RATE_LIM_CFG_0_SAT_SHIFT 16
+#define MME0_QM_HBW_RD_RATE_LIM_CFG_0_SAT_MASK 0xFF0000
+
+/* MME0_QM_GLBL_AXCACHE */
+#define MME0_QM_GLBL_AXCACHE_AR_SHIFT 0
+#define MME0_QM_GLBL_AXCACHE_AR_MASK 0xF
+#define MME0_QM_GLBL_AXCACHE_AW_SHIFT 16
+#define MME0_QM_GLBL_AXCACHE_AW_MASK 0xF0000
+
+/* MME0_QM_IND_GW_APB_CFG */
+#define MME0_QM_IND_GW_APB_CFG_ADDR_SHIFT 0
+#define MME0_QM_IND_GW_APB_CFG_ADDR_MASK 0x7FFFFFFF
+#define MME0_QM_IND_GW_APB_CFG_CMD_SHIFT 31
+#define MME0_QM_IND_GW_APB_CFG_CMD_MASK 0x80000000
+
+/* MME0_QM_IND_GW_APB_WDATA */
+#define MME0_QM_IND_GW_APB_WDATA_VAL_SHIFT 0
+#define MME0_QM_IND_GW_APB_WDATA_VAL_MASK 0xFFFFFFFF
+
+/* MME0_QM_IND_GW_APB_RDATA */
+#define MME0_QM_IND_GW_APB_RDATA_VAL_SHIFT 0
+#define MME0_QM_IND_GW_APB_RDATA_VAL_MASK 0xFFFFFFFF
+
+/* MME0_QM_IND_GW_APB_STATUS */
+#define MME0_QM_IND_GW_APB_STATUS_RDY_SHIFT 0
+#define MME0_QM_IND_GW_APB_STATUS_RDY_MASK 0x1
+#define MME0_QM_IND_GW_APB_STATUS_ERR_SHIFT 1
+#define MME0_QM_IND_GW_APB_STATUS_ERR_MASK 0x2
+
+/* MME0_QM_GLBL_ERR_ADDR_LO */
+#define MME0_QM_GLBL_ERR_ADDR_LO_VAL_SHIFT 0
+#define MME0_QM_GLBL_ERR_ADDR_LO_VAL_MASK 0xFFFFFFFF
+
+/* MME0_QM_GLBL_ERR_ADDR_HI */
+#define MME0_QM_GLBL_ERR_ADDR_HI_VAL_SHIFT 0
+#define MME0_QM_GLBL_ERR_ADDR_HI_VAL_MASK 0xFFFFFFFF
+
+/* MME0_QM_GLBL_ERR_WDATA */
+#define MME0_QM_GLBL_ERR_WDATA_VAL_SHIFT 0
+#define MME0_QM_GLBL_ERR_WDATA_VAL_MASK 0xFFFFFFFF
+
+/* MME0_QM_GLBL_MEM_INIT_BUSY */
+#define MME0_QM_GLBL_MEM_INIT_BUSY_RBUF_SHIFT 0
+#define MME0_QM_GLBL_MEM_INIT_BUSY_RBUF_MASK 0xF
+
+#endif /* ASIC_REG_MME0_QM_MASKS_H_ */
diff --git a/drivers/accel/habanalabs/include/gaudi/asic_reg/mme0_qm_regs.h b/drivers/accel/habanalabs/include/gaudi/asic_reg/mme0_qm_regs.h
new file mode 100644
index 0000000000..4f078b328b
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi/asic_reg/mme0_qm_regs.h
@@ -0,0 +1,834 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2016-2018 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ ** DO NOT EDIT BELOW **
+ ************************************/
+
+#ifndef ASIC_REG_MME0_QM_REGS_H_
+#define ASIC_REG_MME0_QM_REGS_H_
+
+/*
+ *****************************************
+ * MME0_QM (Prototype: QMAN)
+ *****************************************
+ */
+
+#define mmMME0_QM_GLBL_CFG0 0x68000
+
+#define mmMME0_QM_GLBL_CFG1 0x68004
+
+#define mmMME0_QM_GLBL_PROT 0x68008
+
+#define mmMME0_QM_GLBL_ERR_CFG 0x6800C
+
+#define mmMME0_QM_GLBL_SECURE_PROPS_0 0x68010
+
+#define mmMME0_QM_GLBL_SECURE_PROPS_1 0x68014
+
+#define mmMME0_QM_GLBL_SECURE_PROPS_2 0x68018
+
+#define mmMME0_QM_GLBL_SECURE_PROPS_3 0x6801C
+
+#define mmMME0_QM_GLBL_SECURE_PROPS_4 0x68020
+
+#define mmMME0_QM_GLBL_NON_SECURE_PROPS_0 0x68024
+
+#define mmMME0_QM_GLBL_NON_SECURE_PROPS_1 0x68028
+
+#define mmMME0_QM_GLBL_NON_SECURE_PROPS_2 0x6802C
+
+#define mmMME0_QM_GLBL_NON_SECURE_PROPS_3 0x68030
+
+#define mmMME0_QM_GLBL_NON_SECURE_PROPS_4 0x68034
+
+#define mmMME0_QM_GLBL_STS0 0x68038
+
+#define mmMME0_QM_GLBL_STS1_0 0x68040
+
+#define mmMME0_QM_GLBL_STS1_1 0x68044
+
+#define mmMME0_QM_GLBL_STS1_2 0x68048
+
+#define mmMME0_QM_GLBL_STS1_3 0x6804C
+
+#define mmMME0_QM_GLBL_STS1_4 0x68050
+
+#define mmMME0_QM_GLBL_MSG_EN_0 0x68054
+
+#define mmMME0_QM_GLBL_MSG_EN_1 0x68058
+
+#define mmMME0_QM_GLBL_MSG_EN_2 0x6805C
+
+#define mmMME0_QM_GLBL_MSG_EN_3 0x68060
+
+#define mmMME0_QM_GLBL_MSG_EN_4 0x68068
+
+#define mmMME0_QM_PQ_BASE_LO_0 0x68070
+
+#define mmMME0_QM_PQ_BASE_LO_1 0x68074
+
+#define mmMME0_QM_PQ_BASE_LO_2 0x68078
+
+#define mmMME0_QM_PQ_BASE_LO_3 0x6807C
+
+#define mmMME0_QM_PQ_BASE_HI_0 0x68080
+
+#define mmMME0_QM_PQ_BASE_HI_1 0x68084
+
+#define mmMME0_QM_PQ_BASE_HI_2 0x68088
+
+#define mmMME0_QM_PQ_BASE_HI_3 0x6808C
+
+#define mmMME0_QM_PQ_SIZE_0 0x68090
+
+#define mmMME0_QM_PQ_SIZE_1 0x68094
+
+#define mmMME0_QM_PQ_SIZE_2 0x68098
+
+#define mmMME0_QM_PQ_SIZE_3 0x6809C
+
+#define mmMME0_QM_PQ_PI_0 0x680A0
+
+#define mmMME0_QM_PQ_PI_1 0x680A4
+
+#define mmMME0_QM_PQ_PI_2 0x680A8
+
+#define mmMME0_QM_PQ_PI_3 0x680AC
+
+#define mmMME0_QM_PQ_CI_0 0x680B0
+
+#define mmMME0_QM_PQ_CI_1 0x680B4
+
+#define mmMME0_QM_PQ_CI_2 0x680B8
+
+#define mmMME0_QM_PQ_CI_3 0x680BC
+
+#define mmMME0_QM_PQ_CFG0_0 0x680C0
+
+#define mmMME0_QM_PQ_CFG0_1 0x680C4
+
+#define mmMME0_QM_PQ_CFG0_2 0x680C8
+
+#define mmMME0_QM_PQ_CFG0_3 0x680CC
+
+#define mmMME0_QM_PQ_CFG1_0 0x680D0
+
+#define mmMME0_QM_PQ_CFG1_1 0x680D4
+
+#define mmMME0_QM_PQ_CFG1_2 0x680D8
+
+#define mmMME0_QM_PQ_CFG1_3 0x680DC
+
+#define mmMME0_QM_PQ_ARUSER_31_11_0 0x680E0
+
+#define mmMME0_QM_PQ_ARUSER_31_11_1 0x680E4
+
+#define mmMME0_QM_PQ_ARUSER_31_11_2 0x680E8
+
+#define mmMME0_QM_PQ_ARUSER_31_11_3 0x680EC
+
+#define mmMME0_QM_PQ_STS0_0 0x680F0
+
+#define mmMME0_QM_PQ_STS0_1 0x680F4
+
+#define mmMME0_QM_PQ_STS0_2 0x680F8
+
+#define mmMME0_QM_PQ_STS0_3 0x680FC
+
+#define mmMME0_QM_PQ_STS1_0 0x68100
+
+#define mmMME0_QM_PQ_STS1_1 0x68104
+
+#define mmMME0_QM_PQ_STS1_2 0x68108
+
+#define mmMME0_QM_PQ_STS1_3 0x6810C
+
+#define mmMME0_QM_CQ_CFG0_0 0x68110
+
+#define mmMME0_QM_CQ_CFG0_1 0x68114
+
+#define mmMME0_QM_CQ_CFG0_2 0x68118
+
+#define mmMME0_QM_CQ_CFG0_3 0x6811C
+
+#define mmMME0_QM_CQ_CFG0_4 0x68120
+
+#define mmMME0_QM_CQ_CFG1_0 0x68124
+
+#define mmMME0_QM_CQ_CFG1_1 0x68128
+
+#define mmMME0_QM_CQ_CFG1_2 0x6812C
+
+#define mmMME0_QM_CQ_CFG1_3 0x68130
+
+#define mmMME0_QM_CQ_CFG1_4 0x68134
+
+#define mmMME0_QM_CQ_ARUSER_31_11_0 0x68138
+
+#define mmMME0_QM_CQ_ARUSER_31_11_1 0x6813C
+
+#define mmMME0_QM_CQ_ARUSER_31_11_2 0x68140
+
+#define mmMME0_QM_CQ_ARUSER_31_11_3 0x68144
+
+#define mmMME0_QM_CQ_ARUSER_31_11_4 0x68148
+
+#define mmMME0_QM_CQ_STS0_0 0x6814C
+
+#define mmMME0_QM_CQ_STS0_1 0x68150
+
+#define mmMME0_QM_CQ_STS0_2 0x68154
+
+#define mmMME0_QM_CQ_STS0_3 0x68158
+
+#define mmMME0_QM_CQ_STS0_4 0x6815C
+
+#define mmMME0_QM_CQ_STS1_0 0x68160
+
+#define mmMME0_QM_CQ_STS1_1 0x68164
+
+#define mmMME0_QM_CQ_STS1_2 0x68168
+
+#define mmMME0_QM_CQ_STS1_3 0x6816C
+
+#define mmMME0_QM_CQ_STS1_4 0x68170
+
+#define mmMME0_QM_CQ_PTR_LO_0 0x68174
+
+#define mmMME0_QM_CQ_PTR_HI_0 0x68178
+
+#define mmMME0_QM_CQ_TSIZE_0 0x6817C
+
+#define mmMME0_QM_CQ_CTL_0 0x68180
+
+#define mmMME0_QM_CQ_PTR_LO_1 0x68184
+
+#define mmMME0_QM_CQ_PTR_HI_1 0x68188
+
+#define mmMME0_QM_CQ_TSIZE_1 0x6818C
+
+#define mmMME0_QM_CQ_CTL_1 0x68190
+
+#define mmMME0_QM_CQ_PTR_LO_2 0x68194
+
+#define mmMME0_QM_CQ_PTR_HI_2 0x68198
+
+#define mmMME0_QM_CQ_TSIZE_2 0x6819C
+
+#define mmMME0_QM_CQ_CTL_2 0x681A0
+
+#define mmMME0_QM_CQ_PTR_LO_3 0x681A4
+
+#define mmMME0_QM_CQ_PTR_HI_3 0x681A8
+
+#define mmMME0_QM_CQ_TSIZE_3 0x681AC
+
+#define mmMME0_QM_CQ_CTL_3 0x681B0
+
+#define mmMME0_QM_CQ_PTR_LO_4 0x681B4
+
+#define mmMME0_QM_CQ_PTR_HI_4 0x681B8
+
+#define mmMME0_QM_CQ_TSIZE_4 0x681BC
+
+#define mmMME0_QM_CQ_CTL_4 0x681C0
+
+#define mmMME0_QM_CQ_PTR_LO_STS_0 0x681C4
+
+#define mmMME0_QM_CQ_PTR_LO_STS_1 0x681C8
+
+#define mmMME0_QM_CQ_PTR_LO_STS_2 0x681CC
+
+#define mmMME0_QM_CQ_PTR_LO_STS_3 0x681D0
+
+#define mmMME0_QM_CQ_PTR_LO_STS_4 0x681D4
+
+#define mmMME0_QM_CQ_PTR_HI_STS_0 0x681D8
+
+#define mmMME0_QM_CQ_PTR_HI_STS_1 0x681DC
+
+#define mmMME0_QM_CQ_PTR_HI_STS_2 0x681E0
+
+#define mmMME0_QM_CQ_PTR_HI_STS_3 0x681E4
+
+#define mmMME0_QM_CQ_PTR_HI_STS_4 0x681E8
+
+#define mmMME0_QM_CQ_TSIZE_STS_0 0x681EC
+
+#define mmMME0_QM_CQ_TSIZE_STS_1 0x681F0
+
+#define mmMME0_QM_CQ_TSIZE_STS_2 0x681F4
+
+#define mmMME0_QM_CQ_TSIZE_STS_3 0x681F8
+
+#define mmMME0_QM_CQ_TSIZE_STS_4 0x681FC
+
+#define mmMME0_QM_CQ_CTL_STS_0 0x68200
+
+#define mmMME0_QM_CQ_CTL_STS_1 0x68204
+
+#define mmMME0_QM_CQ_CTL_STS_2 0x68208
+
+#define mmMME0_QM_CQ_CTL_STS_3 0x6820C
+
+#define mmMME0_QM_CQ_CTL_STS_4 0x68210
+
+#define mmMME0_QM_CQ_IFIFO_CNT_0 0x68214
+
+#define mmMME0_QM_CQ_IFIFO_CNT_1 0x68218
+
+#define mmMME0_QM_CQ_IFIFO_CNT_2 0x6821C
+
+#define mmMME0_QM_CQ_IFIFO_CNT_3 0x68220
+
+#define mmMME0_QM_CQ_IFIFO_CNT_4 0x68224
+
+#define mmMME0_QM_CP_MSG_BASE0_ADDR_LO_0 0x68228
+
+#define mmMME0_QM_CP_MSG_BASE0_ADDR_LO_1 0x6822C
+
+#define mmMME0_QM_CP_MSG_BASE0_ADDR_LO_2 0x68230
+
+#define mmMME0_QM_CP_MSG_BASE0_ADDR_LO_3 0x68234
+
+#define mmMME0_QM_CP_MSG_BASE0_ADDR_LO_4 0x68238
+
+#define mmMME0_QM_CP_MSG_BASE0_ADDR_HI_0 0x6823C
+
+#define mmMME0_QM_CP_MSG_BASE0_ADDR_HI_1 0x68240
+
+#define mmMME0_QM_CP_MSG_BASE0_ADDR_HI_2 0x68244
+
+#define mmMME0_QM_CP_MSG_BASE0_ADDR_HI_3 0x68248
+
+#define mmMME0_QM_CP_MSG_BASE0_ADDR_HI_4 0x6824C
+
+#define mmMME0_QM_CP_MSG_BASE1_ADDR_LO_0 0x68250
+
+#define mmMME0_QM_CP_MSG_BASE1_ADDR_LO_1 0x68254
+
+#define mmMME0_QM_CP_MSG_BASE1_ADDR_LO_2 0x68258
+
+#define mmMME0_QM_CP_MSG_BASE1_ADDR_LO_3 0x6825C
+
+#define mmMME0_QM_CP_MSG_BASE1_ADDR_LO_4 0x68260
+
+#define mmMME0_QM_CP_MSG_BASE1_ADDR_HI_0 0x68264
+
+#define mmMME0_QM_CP_MSG_BASE1_ADDR_HI_1 0x68268
+
+#define mmMME0_QM_CP_MSG_BASE1_ADDR_HI_2 0x6826C
+
+#define mmMME0_QM_CP_MSG_BASE1_ADDR_HI_3 0x68270
+
+#define mmMME0_QM_CP_MSG_BASE1_ADDR_HI_4 0x68274
+
+#define mmMME0_QM_CP_MSG_BASE2_ADDR_LO_0 0x68278
+
+#define mmMME0_QM_CP_MSG_BASE2_ADDR_LO_1 0x6827C
+
+#define mmMME0_QM_CP_MSG_BASE2_ADDR_LO_2 0x68280
+
+#define mmMME0_QM_CP_MSG_BASE2_ADDR_LO_3 0x68284
+
+#define mmMME0_QM_CP_MSG_BASE2_ADDR_LO_4 0x68288
+
+#define mmMME0_QM_CP_MSG_BASE2_ADDR_HI_0 0x6828C
+
+#define mmMME0_QM_CP_MSG_BASE2_ADDR_HI_1 0x68290
+
+#define mmMME0_QM_CP_MSG_BASE2_ADDR_HI_2 0x68294
+
+#define mmMME0_QM_CP_MSG_BASE2_ADDR_HI_3 0x68298
+
+#define mmMME0_QM_CP_MSG_BASE2_ADDR_HI_4 0x6829C
+
+#define mmMME0_QM_CP_MSG_BASE3_ADDR_LO_0 0x682A0
+
+#define mmMME0_QM_CP_MSG_BASE3_ADDR_LO_1 0x682A4
+
+#define mmMME0_QM_CP_MSG_BASE3_ADDR_LO_2 0x682A8
+
+#define mmMME0_QM_CP_MSG_BASE3_ADDR_LO_3 0x682AC
+
+#define mmMME0_QM_CP_MSG_BASE3_ADDR_LO_4 0x682B0
+
+#define mmMME0_QM_CP_MSG_BASE3_ADDR_HI_0 0x682B4
+
+#define mmMME0_QM_CP_MSG_BASE3_ADDR_HI_1 0x682B8
+
+#define mmMME0_QM_CP_MSG_BASE3_ADDR_HI_2 0x682BC
+
+#define mmMME0_QM_CP_MSG_BASE3_ADDR_HI_3 0x682C0
+
+#define mmMME0_QM_CP_MSG_BASE3_ADDR_HI_4 0x682C4
+
+#define mmMME0_QM_CP_LDMA_TSIZE_OFFSET_0 0x682C8
+
+#define mmMME0_QM_CP_LDMA_TSIZE_OFFSET_1 0x682CC
+
+#define mmMME0_QM_CP_LDMA_TSIZE_OFFSET_2 0x682D0
+
+#define mmMME0_QM_CP_LDMA_TSIZE_OFFSET_3 0x682D4
+
+#define mmMME0_QM_CP_LDMA_TSIZE_OFFSET_4 0x682D8
+
+#define mmMME0_QM_CP_LDMA_SRC_BASE_LO_OFFSET_0 0x682E0
+
+#define mmMME0_QM_CP_LDMA_SRC_BASE_LO_OFFSET_1 0x682E4
+
+#define mmMME0_QM_CP_LDMA_SRC_BASE_LO_OFFSET_2 0x682E8
+
+#define mmMME0_QM_CP_LDMA_SRC_BASE_LO_OFFSET_3 0x682EC
+
+#define mmMME0_QM_CP_LDMA_SRC_BASE_LO_OFFSET_4 0x682F0
+
+#define mmMME0_QM_CP_LDMA_DST_BASE_LO_OFFSET_0 0x682F4
+
+#define mmMME0_QM_CP_LDMA_DST_BASE_LO_OFFSET_1 0x682F8
+
+#define mmMME0_QM_CP_LDMA_DST_BASE_LO_OFFSET_2 0x682FC
+
+#define mmMME0_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 0x68300
+
+#define mmMME0_QM_CP_LDMA_DST_BASE_LO_OFFSET_4 0x68304
+
+#define mmMME0_QM_CP_FENCE0_RDATA_0 0x68308
+
+#define mmMME0_QM_CP_FENCE0_RDATA_1 0x6830C
+
+#define mmMME0_QM_CP_FENCE0_RDATA_2 0x68310
+
+#define mmMME0_QM_CP_FENCE0_RDATA_3 0x68314
+
+#define mmMME0_QM_CP_FENCE0_RDATA_4 0x68318
+
+#define mmMME0_QM_CP_FENCE1_RDATA_0 0x6831C
+
+#define mmMME0_QM_CP_FENCE1_RDATA_1 0x68320
+
+#define mmMME0_QM_CP_FENCE1_RDATA_2 0x68324
+
+#define mmMME0_QM_CP_FENCE1_RDATA_3 0x68328
+
+#define mmMME0_QM_CP_FENCE1_RDATA_4 0x6832C
+
+#define mmMME0_QM_CP_FENCE2_RDATA_0 0x68330
+
+#define mmMME0_QM_CP_FENCE2_RDATA_1 0x68334
+
+#define mmMME0_QM_CP_FENCE2_RDATA_2 0x68338
+
+#define mmMME0_QM_CP_FENCE2_RDATA_3 0x6833C
+
+#define mmMME0_QM_CP_FENCE2_RDATA_4 0x68340
+
+#define mmMME0_QM_CP_FENCE3_RDATA_0 0x68344
+
+#define mmMME0_QM_CP_FENCE3_RDATA_1 0x68348
+
+#define mmMME0_QM_CP_FENCE3_RDATA_2 0x6834C
+
+#define mmMME0_QM_CP_FENCE3_RDATA_3 0x68350
+
+#define mmMME0_QM_CP_FENCE3_RDATA_4 0x68354
+
+#define mmMME0_QM_CP_FENCE0_CNT_0 0x68358
+
+#define mmMME0_QM_CP_FENCE0_CNT_1 0x6835C
+
+#define mmMME0_QM_CP_FENCE0_CNT_2 0x68360
+
+#define mmMME0_QM_CP_FENCE0_CNT_3 0x68364
+
+#define mmMME0_QM_CP_FENCE0_CNT_4 0x68368
+
+#define mmMME0_QM_CP_FENCE1_CNT_0 0x6836C
+
+#define mmMME0_QM_CP_FENCE1_CNT_1 0x68370
+
+#define mmMME0_QM_CP_FENCE1_CNT_2 0x68374
+
+#define mmMME0_QM_CP_FENCE1_CNT_3 0x68378
+
+#define mmMME0_QM_CP_FENCE1_CNT_4 0x6837C
+
+#define mmMME0_QM_CP_FENCE2_CNT_0 0x68380
+
+#define mmMME0_QM_CP_FENCE2_CNT_1 0x68384
+
+#define mmMME0_QM_CP_FENCE2_CNT_2 0x68388
+
+#define mmMME0_QM_CP_FENCE2_CNT_3 0x6838C
+
+#define mmMME0_QM_CP_FENCE2_CNT_4 0x68390
+
+#define mmMME0_QM_CP_FENCE3_CNT_0 0x68394
+
+#define mmMME0_QM_CP_FENCE3_CNT_1 0x68398
+
+#define mmMME0_QM_CP_FENCE3_CNT_2 0x6839C
+
+#define mmMME0_QM_CP_FENCE3_CNT_3 0x683A0
+
+#define mmMME0_QM_CP_FENCE3_CNT_4 0x683A4
+
+#define mmMME0_QM_CP_STS_0 0x683A8
+
+#define mmMME0_QM_CP_STS_1 0x683AC
+
+#define mmMME0_QM_CP_STS_2 0x683B0
+
+#define mmMME0_QM_CP_STS_3 0x683B4
+
+#define mmMME0_QM_CP_STS_4 0x683B8
+
+#define mmMME0_QM_CP_CURRENT_INST_LO_0 0x683BC
+
+#define mmMME0_QM_CP_CURRENT_INST_LO_1 0x683C0
+
+#define mmMME0_QM_CP_CURRENT_INST_LO_2 0x683C4
+
+#define mmMME0_QM_CP_CURRENT_INST_LO_3 0x683C8
+
+#define mmMME0_QM_CP_CURRENT_INST_LO_4 0x683CC
+
+#define mmMME0_QM_CP_CURRENT_INST_HI_0 0x683D0
+
+#define mmMME0_QM_CP_CURRENT_INST_HI_1 0x683D4
+
+#define mmMME0_QM_CP_CURRENT_INST_HI_2 0x683D8
+
+#define mmMME0_QM_CP_CURRENT_INST_HI_3 0x683DC
+
+#define mmMME0_QM_CP_CURRENT_INST_HI_4 0x683E0
+
+#define mmMME0_QM_CP_BARRIER_CFG_0 0x683F4
+
+#define mmMME0_QM_CP_BARRIER_CFG_1 0x683F8
+
+#define mmMME0_QM_CP_BARRIER_CFG_2 0x683FC
+
+#define mmMME0_QM_CP_BARRIER_CFG_3 0x68400
+
+#define mmMME0_QM_CP_BARRIER_CFG_4 0x68404
+
+#define mmMME0_QM_CP_DBG_0_0 0x68408
+
+#define mmMME0_QM_CP_DBG_0_1 0x6840C
+
+#define mmMME0_QM_CP_DBG_0_2 0x68410
+
+#define mmMME0_QM_CP_DBG_0_3 0x68414
+
+#define mmMME0_QM_CP_DBG_0_4 0x68418
+
+#define mmMME0_QM_CP_ARUSER_31_11_0 0x6841C
+
+#define mmMME0_QM_CP_ARUSER_31_11_1 0x68420
+
+#define mmMME0_QM_CP_ARUSER_31_11_2 0x68424
+
+#define mmMME0_QM_CP_ARUSER_31_11_3 0x68428
+
+#define mmMME0_QM_CP_ARUSER_31_11_4 0x6842C
+
+#define mmMME0_QM_CP_AWUSER_31_11_0 0x68430
+
+#define mmMME0_QM_CP_AWUSER_31_11_1 0x68434
+
+#define mmMME0_QM_CP_AWUSER_31_11_2 0x68438
+
+#define mmMME0_QM_CP_AWUSER_31_11_3 0x6843C
+
+#define mmMME0_QM_CP_AWUSER_31_11_4 0x68440
+
+#define mmMME0_QM_ARB_CFG_0 0x68A00
+
+#define mmMME0_QM_ARB_CHOISE_Q_PUSH 0x68A04
+
+#define mmMME0_QM_ARB_WRR_WEIGHT_0 0x68A08
+
+#define mmMME0_QM_ARB_WRR_WEIGHT_1 0x68A0C
+
+#define mmMME0_QM_ARB_WRR_WEIGHT_2 0x68A10
+
+#define mmMME0_QM_ARB_WRR_WEIGHT_3 0x68A14
+
+#define mmMME0_QM_ARB_CFG_1 0x68A18
+
+#define mmMME0_QM_ARB_MST_AVAIL_CRED_0 0x68A20
+
+#define mmMME0_QM_ARB_MST_AVAIL_CRED_1 0x68A24
+
+#define mmMME0_QM_ARB_MST_AVAIL_CRED_2 0x68A28
+
+#define mmMME0_QM_ARB_MST_AVAIL_CRED_3 0x68A2C
+
+#define mmMME0_QM_ARB_MST_AVAIL_CRED_4 0x68A30
+
+#define mmMME0_QM_ARB_MST_AVAIL_CRED_5 0x68A34
+
+#define mmMME0_QM_ARB_MST_AVAIL_CRED_6 0x68A38
+
+#define mmMME0_QM_ARB_MST_AVAIL_CRED_7 0x68A3C
+
+#define mmMME0_QM_ARB_MST_AVAIL_CRED_8 0x68A40
+
+#define mmMME0_QM_ARB_MST_AVAIL_CRED_9 0x68A44
+
+#define mmMME0_QM_ARB_MST_AVAIL_CRED_10 0x68A48
+
+#define mmMME0_QM_ARB_MST_AVAIL_CRED_11 0x68A4C
+
+#define mmMME0_QM_ARB_MST_AVAIL_CRED_12 0x68A50
+
+#define mmMME0_QM_ARB_MST_AVAIL_CRED_13 0x68A54
+
+#define mmMME0_QM_ARB_MST_AVAIL_CRED_14 0x68A58
+
+#define mmMME0_QM_ARB_MST_AVAIL_CRED_15 0x68A5C
+
+#define mmMME0_QM_ARB_MST_AVAIL_CRED_16 0x68A60
+
+#define mmMME0_QM_ARB_MST_AVAIL_CRED_17 0x68A64
+
+#define mmMME0_QM_ARB_MST_AVAIL_CRED_18 0x68A68
+
+#define mmMME0_QM_ARB_MST_AVAIL_CRED_19 0x68A6C
+
+#define mmMME0_QM_ARB_MST_AVAIL_CRED_20 0x68A70
+
+#define mmMME0_QM_ARB_MST_AVAIL_CRED_21 0x68A74
+
+#define mmMME0_QM_ARB_MST_AVAIL_CRED_22 0x68A78
+
+#define mmMME0_QM_ARB_MST_AVAIL_CRED_23 0x68A7C
+
+#define mmMME0_QM_ARB_MST_AVAIL_CRED_24 0x68A80
+
+#define mmMME0_QM_ARB_MST_AVAIL_CRED_25 0x68A84
+
+#define mmMME0_QM_ARB_MST_AVAIL_CRED_26 0x68A88
+
+#define mmMME0_QM_ARB_MST_AVAIL_CRED_27 0x68A8C
+
+#define mmMME0_QM_ARB_MST_AVAIL_CRED_28 0x68A90
+
+#define mmMME0_QM_ARB_MST_AVAIL_CRED_29 0x68A94
+
+#define mmMME0_QM_ARB_MST_AVAIL_CRED_30 0x68A98
+
+#define mmMME0_QM_ARB_MST_AVAIL_CRED_31 0x68A9C
+
+#define mmMME0_QM_ARB_MST_CRED_INC 0x68AA0
+
+#define mmMME0_QM_ARB_MST_CHOISE_PUSH_OFST_0 0x68AA4
+
+#define mmMME0_QM_ARB_MST_CHOISE_PUSH_OFST_1 0x68AA8
+
+#define mmMME0_QM_ARB_MST_CHOISE_PUSH_OFST_2 0x68AAC
+
+#define mmMME0_QM_ARB_MST_CHOISE_PUSH_OFST_3 0x68AB0
+
+#define mmMME0_QM_ARB_MST_CHOISE_PUSH_OFST_4 0x68AB4
+
+#define mmMME0_QM_ARB_MST_CHOISE_PUSH_OFST_5 0x68AB8
+
+#define mmMME0_QM_ARB_MST_CHOISE_PUSH_OFST_6 0x68ABC
+
+#define mmMME0_QM_ARB_MST_CHOISE_PUSH_OFST_7 0x68AC0
+
+#define mmMME0_QM_ARB_MST_CHOISE_PUSH_OFST_8 0x68AC4
+
+#define mmMME0_QM_ARB_MST_CHOISE_PUSH_OFST_9 0x68AC8
+
+#define mmMME0_QM_ARB_MST_CHOISE_PUSH_OFST_10 0x68ACC
+
+#define mmMME0_QM_ARB_MST_CHOISE_PUSH_OFST_11 0x68AD0
+
+#define mmMME0_QM_ARB_MST_CHOISE_PUSH_OFST_12 0x68AD4
+
+#define mmMME0_QM_ARB_MST_CHOISE_PUSH_OFST_13 0x68AD8
+
+#define mmMME0_QM_ARB_MST_CHOISE_PUSH_OFST_14 0x68ADC
+
+#define mmMME0_QM_ARB_MST_CHOISE_PUSH_OFST_15 0x68AE0
+
+#define mmMME0_QM_ARB_MST_CHOISE_PUSH_OFST_16 0x68AE4
+
+#define mmMME0_QM_ARB_MST_CHOISE_PUSH_OFST_17 0x68AE8
+
+#define mmMME0_QM_ARB_MST_CHOISE_PUSH_OFST_18 0x68AEC
+
+#define mmMME0_QM_ARB_MST_CHOISE_PUSH_OFST_19 0x68AF0
+
+#define mmMME0_QM_ARB_MST_CHOISE_PUSH_OFST_20 0x68AF4
+
+#define mmMME0_QM_ARB_MST_CHOISE_PUSH_OFST_21 0x68AF8
+
+#define mmMME0_QM_ARB_MST_CHOISE_PUSH_OFST_22 0x68AFC
+
+#define mmMME0_QM_ARB_MST_CHOISE_PUSH_OFST_23 0x68B00
+
+#define mmMME0_QM_ARB_MST_CHOISE_PUSH_OFST_24 0x68B04
+
+#define mmMME0_QM_ARB_MST_CHOISE_PUSH_OFST_25 0x68B08
+
+#define mmMME0_QM_ARB_MST_CHOISE_PUSH_OFST_26 0x68B0C
+
+#define mmMME0_QM_ARB_MST_CHOISE_PUSH_OFST_27 0x68B10
+
+#define mmMME0_QM_ARB_MST_CHOISE_PUSH_OFST_28 0x68B14
+
+#define mmMME0_QM_ARB_MST_CHOISE_PUSH_OFST_29 0x68B18
+
+#define mmMME0_QM_ARB_MST_CHOISE_PUSH_OFST_30 0x68B1C
+
+#define mmMME0_QM_ARB_MST_CHOISE_PUSH_OFST_31 0x68B20
+
+#define mmMME0_QM_ARB_SLV_MASTER_INC_CRED_OFST 0x68B28
+
+#define mmMME0_QM_ARB_MST_SLAVE_EN 0x68B2C
+
+#define mmMME0_QM_ARB_MST_QUIET_PER 0x68B34
+
+#define mmMME0_QM_ARB_SLV_CHOISE_WDT 0x68B38
+
+#define mmMME0_QM_ARB_SLV_ID 0x68B3C
+
+#define mmMME0_QM_ARB_MSG_MAX_INFLIGHT 0x68B44
+
+#define mmMME0_QM_ARB_MSG_AWUSER_31_11 0x68B48
+
+#define mmMME0_QM_ARB_MSG_AWUSER_SEC_PROP 0x68B4C
+
+#define mmMME0_QM_ARB_MSG_AWUSER_NON_SEC_PROP 0x68B50
+
+#define mmMME0_QM_ARB_BASE_LO 0x68B54
+
+#define mmMME0_QM_ARB_BASE_HI 0x68B58
+
+#define mmMME0_QM_ARB_STATE_STS 0x68B80
+
+#define mmMME0_QM_ARB_CHOISE_FULLNESS_STS 0x68B84
+
+#define mmMME0_QM_ARB_MSG_STS 0x68B88
+
+#define mmMME0_QM_ARB_SLV_CHOISE_Q_HEAD 0x68B8C
+
+#define mmMME0_QM_ARB_ERR_CAUSE 0x68B9C
+
+#define mmMME0_QM_ARB_ERR_MSG_EN 0x68BA0
+
+#define mmMME0_QM_ARB_ERR_STS_DRP 0x68BA8
+
+#define mmMME0_QM_ARB_MST_CRED_STS_0 0x68BB0
+
+#define mmMME0_QM_ARB_MST_CRED_STS_1 0x68BB4
+
+#define mmMME0_QM_ARB_MST_CRED_STS_2 0x68BB8
+
+#define mmMME0_QM_ARB_MST_CRED_STS_3 0x68BBC
+
+#define mmMME0_QM_ARB_MST_CRED_STS_4 0x68BC0
+
+#define mmMME0_QM_ARB_MST_CRED_STS_5 0x68BC4
+
+#define mmMME0_QM_ARB_MST_CRED_STS_6 0x68BC8
+
+#define mmMME0_QM_ARB_MST_CRED_STS_7 0x68BCC
+
+#define mmMME0_QM_ARB_MST_CRED_STS_8 0x68BD0
+
+#define mmMME0_QM_ARB_MST_CRED_STS_9 0x68BD4
+
+#define mmMME0_QM_ARB_MST_CRED_STS_10 0x68BD8
+
+#define mmMME0_QM_ARB_MST_CRED_STS_11 0x68BDC
+
+#define mmMME0_QM_ARB_MST_CRED_STS_12 0x68BE0
+
+#define mmMME0_QM_ARB_MST_CRED_STS_13 0x68BE4
+
+#define mmMME0_QM_ARB_MST_CRED_STS_14 0x68BE8
+
+#define mmMME0_QM_ARB_MST_CRED_STS_15 0x68BEC
+
+#define mmMME0_QM_ARB_MST_CRED_STS_16 0x68BF0
+
+#define mmMME0_QM_ARB_MST_CRED_STS_17 0x68BF4
+
+#define mmMME0_QM_ARB_MST_CRED_STS_18 0x68BF8
+
+#define mmMME0_QM_ARB_MST_CRED_STS_19 0x68BFC
+
+#define mmMME0_QM_ARB_MST_CRED_STS_20 0x68C00
+
+#define mmMME0_QM_ARB_MST_CRED_STS_21 0x68C04
+
+#define mmMME0_QM_ARB_MST_CRED_STS_22 0x68C08
+
+#define mmMME0_QM_ARB_MST_CRED_STS_23 0x68C0C
+
+#define mmMME0_QM_ARB_MST_CRED_STS_24 0x68C10
+
+#define mmMME0_QM_ARB_MST_CRED_STS_25 0x68C14
+
+#define mmMME0_QM_ARB_MST_CRED_STS_26 0x68C18
+
+#define mmMME0_QM_ARB_MST_CRED_STS_27 0x68C1C
+
+#define mmMME0_QM_ARB_MST_CRED_STS_28 0x68C20
+
+#define mmMME0_QM_ARB_MST_CRED_STS_29 0x68C24
+
+#define mmMME0_QM_ARB_MST_CRED_STS_30 0x68C28
+
+#define mmMME0_QM_ARB_MST_CRED_STS_31 0x68C2C
+
+#define mmMME0_QM_CGM_CFG 0x68C70
+
+#define mmMME0_QM_CGM_STS 0x68C74
+
+#define mmMME0_QM_CGM_CFG1 0x68C78
+
+#define mmMME0_QM_LOCAL_RANGE_BASE 0x68C80
+
+#define mmMME0_QM_LOCAL_RANGE_SIZE 0x68C84
+
+#define mmMME0_QM_CSMR_STRICT_PRIO_CFG 0x68C90
+
+#define mmMME0_QM_HBW_RD_RATE_LIM_CFG_1 0x68C94
+
+#define mmMME0_QM_LBW_WR_RATE_LIM_CFG_0 0x68C98
+
+#define mmMME0_QM_LBW_WR_RATE_LIM_CFG_1 0x68C9C
+
+#define mmMME0_QM_HBW_RD_RATE_LIM_CFG_0 0x68CA0
+
+#define mmMME0_QM_GLBL_AXCACHE 0x68CA4
+
+#define mmMME0_QM_IND_GW_APB_CFG 0x68CB0
+
+#define mmMME0_QM_IND_GW_APB_WDATA 0x68CB4
+
+#define mmMME0_QM_IND_GW_APB_RDATA 0x68CB8
+
+#define mmMME0_QM_IND_GW_APB_STATUS 0x68CBC
+
+#define mmMME0_QM_GLBL_ERR_ADDR_LO 0x68CD0
+
+#define mmMME0_QM_GLBL_ERR_ADDR_HI 0x68CD4
+
+#define mmMME0_QM_GLBL_ERR_WDATA 0x68CD8
+
+#define mmMME0_QM_GLBL_MEM_INIT_BUSY 0x68D00
+
+#endif /* ASIC_REG_MME0_QM_REGS_H_ */
diff --git a/drivers/accel/habanalabs/include/gaudi/asic_reg/mme1_ctrl_regs.h b/drivers/accel/habanalabs/include/gaudi/asic_reg/mme1_ctrl_regs.h
new file mode 100644
index 0000000000..6c07f7d454
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi/asic_reg/mme1_ctrl_regs.h
@@ -0,0 +1,1456 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2016-2018 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ ** DO NOT EDIT BELOW **
+ ************************************/
+
+#ifndef ASIC_REG_MME1_CTRL_REGS_H_
+#define ASIC_REG_MME1_CTRL_REGS_H_
+
+/*
+ *****************************************
+ * MME1_CTRL (Prototype: MME)
+ *****************************************
+ */
+
+#define mmMME1_CTRL_ARCH_STATUS 0xE0000
+
+#define mmMME1_CTRL_ARCH_BASE_ADDR_HIGH_S 0xE0008
+
+#define mmMME1_CTRL_ARCH_BASE_ADDR_HIGH_L 0xE000C
+
+#define mmMME1_CTRL_ARCH_BASE_ADDR_HIGH_O 0xE0010
+
+#define mmMME1_CTRL_ARCH_BASE_ADDR_LOW_S 0xE0014
+
+#define mmMME1_CTRL_ARCH_BASE_ADDR_LOW_L 0xE0018
+
+#define mmMME1_CTRL_ARCH_BASE_ADDR_LOW_O 0xE001C
+
+#define mmMME1_CTRL_ARCH_HEADER_LOW 0xE0020
+
+#define mmMME1_CTRL_ARCH_HEADER_HIGH 0xE0024
+
+#define mmMME1_CTRL_ARCH_CONV_KERNEL_SIZE_MINUS_1 0xE0028
+
+#define mmMME1_CTRL_ARCH_CONV_ASSOCIATED_DIMS_LOW 0xE002C
+
+#define mmMME1_CTRL_ARCH_CONV_ASSOCIATED_DIMS_HIGH 0xE0030
+
+#define mmMME1_CTRL_ARCH_NUM_ITERATIONS_MINUS_1 0xE0034
+
+#define mmMME1_CTRL_ARCH_OUTER_LOOP 0xE0038
+
+#define mmMME1_CTRL_ARCH_TENSOR_S_VALID_ELEMENTS_0 0xE003C
+
+#define mmMME1_CTRL_ARCH_TENSOR_S_VALID_ELEMENTS_1 0xE0040
+
+#define mmMME1_CTRL_ARCH_TENSOR_S_VALID_ELEMENTS_2 0xE0044
+
+#define mmMME1_CTRL_ARCH_TENSOR_S_VALID_ELEMENTS_3 0xE0048
+
+#define mmMME1_CTRL_ARCH_TENSOR_S_VALID_ELEMENTS_4 0xE004C
+
+#define mmMME1_CTRL_ARCH_TENSOR_S_LOOP_STRIDE_0 0xE0050
+
+#define mmMME1_CTRL_ARCH_TENSOR_S_LOOP_STRIDE_1 0xE0054
+
+#define mmMME1_CTRL_ARCH_TENSOR_S_LOOP_STRIDE_2 0xE0058
+
+#define mmMME1_CTRL_ARCH_TENSOR_S_LOOP_STRIDE_3 0xE005C
+
+#define mmMME1_CTRL_ARCH_TENSOR_S_LOOP_STRIDE_4 0xE0060
+
+#define mmMME1_CTRL_ARCH_TENSOR_S_ROI_SIZE_0 0xE0064
+
+#define mmMME1_CTRL_ARCH_TENSOR_S_ROI_SIZE_1 0xE0068
+
+#define mmMME1_CTRL_ARCH_TENSOR_S_ROI_SIZE_2 0xE006C
+
+#define mmMME1_CTRL_ARCH_TENSOR_S_ROI_SIZE_3 0xE0070
+
+#define mmMME1_CTRL_ARCH_TENSOR_S_SPATIAL_STRIDES_0 0xE0074
+
+#define mmMME1_CTRL_ARCH_TENSOR_S_SPATIAL_STRIDES_1 0xE0078
+
+#define mmMME1_CTRL_ARCH_TENSOR_S_SPATIAL_STRIDES_2 0xE007C
+
+#define mmMME1_CTRL_ARCH_TENSOR_S_SPATIAL_STRIDES_3 0xE0080
+
+#define mmMME1_CTRL_ARCH_TENSOR_S_SPATIAL_SIZE_MINUS_1 0xE0084
+
+#define mmMME1_CTRL_ARCH_AGU_S_ROI_BASE_OFFSET_0 0xE0088
+
+#define mmMME1_CTRL_ARCH_AGU_S_ROI_BASE_OFFSET_1 0xE008C
+
+#define mmMME1_CTRL_ARCH_AGU_S_ROI_BASE_OFFSET_2 0xE0090
+
+#define mmMME1_CTRL_ARCH_AGU_S_ROI_BASE_OFFSET_3 0xE0094
+
+#define mmMME1_CTRL_ARCH_AGU_S_ROI_BASE_OFFSET_4 0xE0098
+
+#define mmMME1_CTRL_ARCH_AGU_S_START_OFFSET_0 0xE009C
+
+#define mmMME1_CTRL_ARCH_AGU_S_START_OFFSET_1 0xE00A0
+
+#define mmMME1_CTRL_ARCH_AGU_S_START_OFFSET_2 0xE00A4
+
+#define mmMME1_CTRL_ARCH_AGU_S_START_OFFSET_3 0xE00A8
+
+#define mmMME1_CTRL_ARCH_TENSOR_L_VALID_ELEMENTS_0 0xE00AC
+
+#define mmMME1_CTRL_ARCH_TENSOR_L_VALID_ELEMENTS_1 0xE00B0
+
+#define mmMME1_CTRL_ARCH_TENSOR_L_VALID_ELEMENTS_2 0xE00B4
+
+#define mmMME1_CTRL_ARCH_TENSOR_L_VALID_ELEMENTS_3 0xE00B8
+
+#define mmMME1_CTRL_ARCH_TENSOR_L_VALID_ELEMENTS_4 0xE00BC
+
+#define mmMME1_CTRL_ARCH_TENSOR_L_LOOP_STRIDE_0 0xE00C0
+
+#define mmMME1_CTRL_ARCH_TENSOR_L_LOOP_STRIDE_1 0xE00C4
+
+#define mmMME1_CTRL_ARCH_TENSOR_L_LOOP_STRIDE_2 0xE00C8
+
+#define mmMME1_CTRL_ARCH_TENSOR_L_LOOP_STRIDE_3 0xE00CC
+
+#define mmMME1_CTRL_ARCH_TENSOR_L_LOOP_STRIDE_4 0xE00D0
+
+#define mmMME1_CTRL_ARCH_TENSOR_L_ROI_SIZE_0 0xE00D4
+
+#define mmMME1_CTRL_ARCH_TENSOR_L_ROI_SIZE_1 0xE00D8
+
+#define mmMME1_CTRL_ARCH_TENSOR_L_ROI_SIZE_2 0xE00DC
+
+#define mmMME1_CTRL_ARCH_TENSOR_L_ROI_SIZE_3 0xE00E0
+
+#define mmMME1_CTRL_ARCH_TENSOR_L_SPATIAL_STRIDES_0 0xE00E4
+
+#define mmMME1_CTRL_ARCH_TENSOR_L_SPATIAL_STRIDES_1 0xE00E8
+
+#define mmMME1_CTRL_ARCH_TENSOR_L_SPATIAL_STRIDES_2 0xE00EC
+
+#define mmMME1_CTRL_ARCH_TENSOR_L_SPATIAL_STRIDES_3 0xE00F0
+
+#define mmMME1_CTRL_ARCH_TENSOR_L_SPATIAL_SIZE_MINUS_1 0xE00F4
+
+#define mmMME1_CTRL_ARCH_AGU_L_LOCAL_ROI_BASE_OFFSET_0 0xE00F8
+
+#define mmMME1_CTRL_ARCH_AGU_L_LOCAL_ROI_BASE_OFFSET_1 0xE00FC
+
+#define mmMME1_CTRL_ARCH_AGU_L_LOCAL_ROI_BASE_OFFSET_2 0xE0100
+
+#define mmMME1_CTRL_ARCH_AGU_L_LOCAL_ROI_BASE_OFFSET_3 0xE0104
+
+#define mmMME1_CTRL_ARCH_AGU_L_LOCAL_ROI_BASE_OFFSET_4 0xE0108
+
+#define mmMME1_CTRL_ARCH_AGU_L_LOCAL_START_OFFSET_0 0xE010C
+
+#define mmMME1_CTRL_ARCH_AGU_L_LOCAL_START_OFFSET_1 0xE0110
+
+#define mmMME1_CTRL_ARCH_AGU_L_LOCAL_START_OFFSET_2 0xE0114
+
+#define mmMME1_CTRL_ARCH_AGU_L_LOCAL_START_OFFSET_3 0xE0118
+
+#define mmMME1_CTRL_ARCH_AGU_L_REMOTE_ROI_BASE_OFFSET_0 0xE011C
+
+#define mmMME1_CTRL_ARCH_AGU_L_REMOTE_ROI_BASE_OFFSET_1 0xE0120
+
+#define mmMME1_CTRL_ARCH_AGU_L_REMOTE_ROI_BASE_OFFSET_2 0xE0124
+
+#define mmMME1_CTRL_ARCH_AGU_L_REMOTE_ROI_BASE_OFFSET_3 0xE0128
+
+#define mmMME1_CTRL_ARCH_AGU_L_REMOTE_ROI_BASE_OFFSET_4 0xE012C
+
+#define mmMME1_CTRL_ARCH_AGU_L_REMOTE_START_OFFSET_0 0xE0130
+
+#define mmMME1_CTRL_ARCH_AGU_L_REMOTE_START_OFFSET_1 0xE0134
+
+#define mmMME1_CTRL_ARCH_AGU_L_REMOTE_START_OFFSET_2 0xE0138
+
+#define mmMME1_CTRL_ARCH_AGU_L_REMOTE_START_OFFSET_3 0xE013C
+
+#define mmMME1_CTRL_ARCH_TENSOR_O_VALID_ELEMENTS_0 0xE0140
+
+#define mmMME1_CTRL_ARCH_TENSOR_O_VALID_ELEMENTS_1 0xE0144
+
+#define mmMME1_CTRL_ARCH_TENSOR_O_VALID_ELEMENTS_2 0xE0148
+
+#define mmMME1_CTRL_ARCH_TENSOR_O_VALID_ELEMENTS_3 0xE014C
+
+#define mmMME1_CTRL_ARCH_TENSOR_O_VALID_ELEMENTS_4 0xE0150
+
+#define mmMME1_CTRL_ARCH_TENSOR_O_LOOP_STRIDE_0 0xE0154
+
+#define mmMME1_CTRL_ARCH_TENSOR_O_LOOP_STRIDE_1 0xE0158
+
+#define mmMME1_CTRL_ARCH_TENSOR_O_LOOP_STRIDE_2 0xE015C
+
+#define mmMME1_CTRL_ARCH_TENSOR_O_LOOP_STRIDE_3 0xE0160
+
+#define mmMME1_CTRL_ARCH_TENSOR_O_LOOP_STRIDE_4 0xE0164
+
+#define mmMME1_CTRL_ARCH_TENSOR_O_ROI_SIZE_0 0xE0168
+
+#define mmMME1_CTRL_ARCH_TENSOR_O_ROI_SIZE_1 0xE016C
+
+#define mmMME1_CTRL_ARCH_TENSOR_O_ROI_SIZE_2 0xE0170
+
+#define mmMME1_CTRL_ARCH_TENSOR_O_ROI_SIZE_3 0xE0174
+
+#define mmMME1_CTRL_ARCH_TENSOR_O_SPATIAL_STRIDES_0 0xE0178
+
+#define mmMME1_CTRL_ARCH_TENSOR_O_SPATIAL_STRIDES_1 0xE017C
+
+#define mmMME1_CTRL_ARCH_TENSOR_O_SPATIAL_STRIDES_2 0xE0180
+
+#define mmMME1_CTRL_ARCH_TENSOR_O_SPATIAL_STRIDES_3 0xE0184
+
+#define mmMME1_CTRL_ARCH_TENSOR_O_SPATIAL_SIZE_MINUS_1 0xE0188
+
+#define mmMME1_CTRL_ARCH_AGU_O_LOCAL_ROI_BASE_OFFSET_0 0xE018C
+
+#define mmMME1_CTRL_ARCH_AGU_O_LOCAL_ROI_BASE_OFFSET_1 0xE0190
+
+#define mmMME1_CTRL_ARCH_AGU_O_LOCAL_ROI_BASE_OFFSET_2 0xE0194
+
+#define mmMME1_CTRL_ARCH_AGU_O_LOCAL_ROI_BASE_OFFSET_3 0xE0198
+
+#define mmMME1_CTRL_ARCH_AGU_O_LOCAL_ROI_BASE_OFFSET_4 0xE019C
+
+#define mmMME1_CTRL_ARCH_AGU_O_LOCAL_START_OFFSET_0 0xE01A0
+
+#define mmMME1_CTRL_ARCH_AGU_O_LOCAL_START_OFFSET_1 0xE01A4
+
+#define mmMME1_CTRL_ARCH_AGU_O_LOCAL_START_OFFSET_2 0xE01A8
+
+#define mmMME1_CTRL_ARCH_AGU_O_LOCAL_START_OFFSET_3 0xE01AC
+
+#define mmMME1_CTRL_ARCH_AGU_O_REMOTE_ROI_BASE_OFFSET_0 0xE01B0
+
+#define mmMME1_CTRL_ARCH_AGU_O_REMOTE_ROI_BASE_OFFSET_1 0xE01B4
+
+#define mmMME1_CTRL_ARCH_AGU_O_REMOTE_ROI_BASE_OFFSET_2 0xE01B8
+
+#define mmMME1_CTRL_ARCH_AGU_O_REMOTE_ROI_BASE_OFFSET_3 0xE01BC
+
+#define mmMME1_CTRL_ARCH_AGU_O_REMOTE_ROI_BASE_OFFSET_4 0xE01C0
+
+#define mmMME1_CTRL_ARCH_AGU_O_REMOTE_START_OFFSET_0 0xE01C4
+
+#define mmMME1_CTRL_ARCH_AGU_O_REMOTE_START_OFFSET_1 0xE01C8
+
+#define mmMME1_CTRL_ARCH_AGU_O_REMOTE_START_OFFSET_2 0xE01CC
+
+#define mmMME1_CTRL_ARCH_AGU_O_REMOTE_START_OFFSET_3 0xE01D0
+
+#define mmMME1_CTRL_ARCH_DESC_SB_REPEAT 0xE01D4
+
+#define mmMME1_CTRL_ARCH_DESC_RATE_LIMITER 0xE01D8
+
+#define mmMME1_CTRL_ARCH_DESC_SYNC_OBJECT_ADDR_LOW_LOCAL 0xE01DC
+
+#define mmMME1_CTRL_ARCH_DESC_SYNC_OBJECT_ADDR_LOW_REMOTE 0xE01E0
+
+#define mmMME1_CTRL_ARCH_DESC_SYNC_OBJECT_ADDR_HIGH 0xE01E4
+
+#define mmMME1_CTRL_ARCH_DESC_SYNC_OBJECT_DATA 0xE01E8
+
+#define mmMME1_CTRL_ARCH_DESC_AXI_USER_DATA 0xE01EC
+
+#define mmMME1_CTRL_ARCH_DESC_PERF_EVT_S 0xE01F0
+
+#define mmMME1_CTRL_ARCH_DESC_PERF_EVT_L_LOCAL 0xE01F4
+
+#define mmMME1_CTRL_ARCH_DESC_PERF_EVT_L_REMOTE 0xE01F8
+
+#define mmMME1_CTRL_ARCH_DESC_PERF_EVT_O_LOCAL 0xE01FC
+
+#define mmMME1_CTRL_ARCH_DESC_PERF_EVT_O_REMOTE 0xE0200
+
+#define mmMME1_CTRL_ARCH_DESC_PADDING_VALUE_S 0xE0204
+
+#define mmMME1_CTRL_ARCH_DESC_PADDING_VALUE_L 0xE0208
+
+#define mmMME1_CTRL_ARCH_DESC_META_DATA_AGU_S 0xE020C
+
+#define mmMME1_CTRL_ARCH_DESC_META_DATA_AGU_L_LOCAL 0xE0210
+
+#define mmMME1_CTRL_ARCH_DESC_META_DATA_AGU_L_REMOTE 0xE0214
+
+#define mmMME1_CTRL_ARCH_DESC_META_DATA_AGU_O_LOCAL 0xE0218
+
+#define mmMME1_CTRL_ARCH_DESC_META_DATA_AGU_O_REMOTE 0xE021C
+
+#define mmMME1_CTRL_ARCH_DESC_PCU_RL_SATURATION 0xE0220
+
+#define mmMME1_CTRL_ARCH_DESC_DUMMY 0xE0224
+
+#define mmMME1_CTRL_CMD 0xE0280
+
+#define mmMME1_CTRL_STATUS1 0xE0284
+
+#define mmMME1_CTRL_RESET 0xE0288
+
+#define mmMME1_CTRL_QM_STALL 0xE028C
+
+#define mmMME1_CTRL_SYNC_OBJECT_FIFO_TH 0xE0290
+
+#define mmMME1_CTRL_EUS_ROLLUP_CNT_ADD 0xE0294
+
+#define mmMME1_CTRL_INTR_CAUSE 0xE0298
+
+#define mmMME1_CTRL_INTR_MASK 0xE029C
+
+#define mmMME1_CTRL_LOG_SHADOW 0xE02A0
+
+#define mmMME1_CTRL_PCU_RL_DESC0 0xE02A4
+
+#define mmMME1_CTRL_PCU_RL_TOKEN_UPDATE 0xE02A8
+
+#define mmMME1_CTRL_PCU_RL_TH 0xE02AC
+
+#define mmMME1_CTRL_PCU_RL_MIN 0xE02B0
+
+#define mmMME1_CTRL_PCU_RL_CTRL_EN 0xE02B4
+
+#define mmMME1_CTRL_PCU_RL_HISTORY_LOG_SIZE 0xE02B8
+
+#define mmMME1_CTRL_PCU_DUMMY_A_BF16 0xE02BC
+
+#define mmMME1_CTRL_PCU_DUMMY_B_BF16 0xE02C0
+
+#define mmMME1_CTRL_PCU_DUMMY_A_FP32_ODD 0xE02C4
+
+#define mmMME1_CTRL_PCU_DUMMY_A_FP32_EVEN 0xE02C8
+
+#define mmMME1_CTRL_PCU_DUMMY_B_FP32_ODD 0xE02CC
+
+#define mmMME1_CTRL_PCU_DUMMY_B_FP32_EVEN 0xE02D0
+
+#define mmMME1_CTRL_PROT 0xE02D4
+
+#define mmMME1_CTRL_EU_POWER_SAVE_DISABLE 0xE02D8
+
+#define mmMME1_CTRL_CS_DBG_BLOCK_ID 0xE02DC
+
+#define mmMME1_CTRL_CS_DBG_STATUS_DROP_CNT 0xE02E0
+
+#define mmMME1_CTRL_TE_CLOSE_CGATE 0xE02E4
+
+#define mmMME1_CTRL_AGU_SM_INFLIGHT_CNTR 0xE02E8
+
+#define mmMME1_CTRL_AGU_SM_TOTAL_CNTR 0xE02EC
+
+#define mmMME1_CTRL_EZSYNC_OUT_CREDIT 0xE02F0
+
+#define mmMME1_CTRL_PCU_RL_SAT_SEC 0xE02F4
+
+#define mmMME1_CTRL_AGU_SYNC_MSG_AXI_USER 0xE02F8
+
+#define mmMME1_CTRL_QM_SLV_LBW_CLK_EN 0xE02FC
+
+#define mmMME1_CTRL_SHADOW_0_STATUS 0xE0400
+
+#define mmMME1_CTRL_SHADOW_0_BASE_ADDR_HIGH_S 0xE0408
+
+#define mmMME1_CTRL_SHADOW_0_BASE_ADDR_HIGH_L 0xE040C
+
+#define mmMME1_CTRL_SHADOW_0_BASE_ADDR_HIGH_O 0xE0410
+
+#define mmMME1_CTRL_SHADOW_0_BASE_ADDR_LOW_S 0xE0414
+
+#define mmMME1_CTRL_SHADOW_0_BASE_ADDR_LOW_L 0xE0418
+
+#define mmMME1_CTRL_SHADOW_0_BASE_ADDR_LOW_O 0xE041C
+
+#define mmMME1_CTRL_SHADOW_0_HEADER_LOW 0xE0420
+
+#define mmMME1_CTRL_SHADOW_0_HEADER_HIGH 0xE0424
+
+#define mmMME1_CTRL_SHADOW_0_CONV_KERNEL_SIZE_MINUS_1 0xE0428
+
+#define mmMME1_CTRL_SHADOW_0_CONV_ASSOCIATED_DIMS_LOW 0xE042C
+
+#define mmMME1_CTRL_SHADOW_0_CONV_ASSOCIATED_DIMS_HIGH 0xE0430
+
+#define mmMME1_CTRL_SHADOW_0_NUM_ITERATIONS_MINUS_1 0xE0434
+
+#define mmMME1_CTRL_SHADOW_0_OUTER_LOOP 0xE0438
+
+#define mmMME1_CTRL_SHADOW_0_TENSOR_S_VALID_ELEMENTS_0 0xE043C
+
+#define mmMME1_CTRL_SHADOW_0_TENSOR_S_VALID_ELEMENTS_1 0xE0440
+
+#define mmMME1_CTRL_SHADOW_0_TENSOR_S_VALID_ELEMENTS_2 0xE0444
+
+#define mmMME1_CTRL_SHADOW_0_TENSOR_S_VALID_ELEMENTS_3 0xE0448
+
+#define mmMME1_CTRL_SHADOW_0_TENSOR_S_VALID_ELEMENTS_4 0xE044C
+
+#define mmMME1_CTRL_SHADOW_0_TENSOR_S_LOOP_STRIDE_0 0xE0450
+
+#define mmMME1_CTRL_SHADOW_0_TENSOR_S_LOOP_STRIDE_1 0xE0454
+
+#define mmMME1_CTRL_SHADOW_0_TENSOR_S_LOOP_STRIDE_2 0xE0458
+
+#define mmMME1_CTRL_SHADOW_0_TENSOR_S_LOOP_STRIDE_3 0xE045C
+
+#define mmMME1_CTRL_SHADOW_0_TENSOR_S_LOOP_STRIDE_4 0xE0460
+
+#define mmMME1_CTRL_SHADOW_0_TENSOR_S_ROI_SIZE_0 0xE0464
+
+#define mmMME1_CTRL_SHADOW_0_TENSOR_S_ROI_SIZE_1 0xE0468
+
+#define mmMME1_CTRL_SHADOW_0_TENSOR_S_ROI_SIZE_2 0xE046C
+
+#define mmMME1_CTRL_SHADOW_0_TENSOR_S_ROI_SIZE_3 0xE0470
+
+#define mmMME1_CTRL_SHADOW_0_TENSOR_S_SPATIAL_STRIDES_0 0xE0474
+
+#define mmMME1_CTRL_SHADOW_0_TENSOR_S_SPATIAL_STRIDES_1 0xE0478
+
+#define mmMME1_CTRL_SHADOW_0_TENSOR_S_SPATIAL_STRIDES_2 0xE047C
+
+#define mmMME1_CTRL_SHADOW_0_TENSOR_S_SPATIAL_STRIDES_3 0xE0480
+
+#define mmMME1_CTRL_SHADOW_0_TENSOR_S_SPATIAL_SIZE_MINUS_1 0xE0484
+
+#define mmMME1_CTRL_SHADOW_0_AGU_S_ROI_BASE_OFFSET_0 0xE0488
+
+#define mmMME1_CTRL_SHADOW_0_AGU_S_ROI_BASE_OFFSET_1 0xE048C
+
+#define mmMME1_CTRL_SHADOW_0_AGU_S_ROI_BASE_OFFSET_2 0xE0490
+
+#define mmMME1_CTRL_SHADOW_0_AGU_S_ROI_BASE_OFFSET_3 0xE0494
+
+#define mmMME1_CTRL_SHADOW_0_AGU_S_ROI_BASE_OFFSET_4 0xE0498
+
+#define mmMME1_CTRL_SHADOW_0_AGU_S_START_OFFSET_0 0xE049C
+
+#define mmMME1_CTRL_SHADOW_0_AGU_S_START_OFFSET_1 0xE04A0
+
+#define mmMME1_CTRL_SHADOW_0_AGU_S_START_OFFSET_2 0xE04A4
+
+#define mmMME1_CTRL_SHADOW_0_AGU_S_START_OFFSET_3 0xE04A8
+
+#define mmMME1_CTRL_SHADOW_0_TENSOR_L_VALID_ELEMENTS_0 0xE04AC
+
+#define mmMME1_CTRL_SHADOW_0_TENSOR_L_VALID_ELEMENTS_1 0xE04B0
+
+#define mmMME1_CTRL_SHADOW_0_TENSOR_L_VALID_ELEMENTS_2 0xE04B4
+
+#define mmMME1_CTRL_SHADOW_0_TENSOR_L_VALID_ELEMENTS_3 0xE04B8
+
+#define mmMME1_CTRL_SHADOW_0_TENSOR_L_VALID_ELEMENTS_4 0xE04BC
+
+#define mmMME1_CTRL_SHADOW_0_TENSOR_L_LOOP_STRIDE_0 0xE04C0
+
+#define mmMME1_CTRL_SHADOW_0_TENSOR_L_LOOP_STRIDE_1 0xE04C4
+
+#define mmMME1_CTRL_SHADOW_0_TENSOR_L_LOOP_STRIDE_2 0xE04C8
+
+#define mmMME1_CTRL_SHADOW_0_TENSOR_L_LOOP_STRIDE_3 0xE04CC
+
+#define mmMME1_CTRL_SHADOW_0_TENSOR_L_LOOP_STRIDE_4 0xE04D0
+
+#define mmMME1_CTRL_SHADOW_0_TENSOR_L_ROI_SIZE_0 0xE04D4
+
+#define mmMME1_CTRL_SHADOW_0_TENSOR_L_ROI_SIZE_1 0xE04D8
+
+#define mmMME1_CTRL_SHADOW_0_TENSOR_L_ROI_SIZE_2 0xE04DC
+
+#define mmMME1_CTRL_SHADOW_0_TENSOR_L_ROI_SIZE_3 0xE04E0
+
+#define mmMME1_CTRL_SHADOW_0_TENSOR_L_SPATIAL_STRIDES_0 0xE04E4
+
+#define mmMME1_CTRL_SHADOW_0_TENSOR_L_SPATIAL_STRIDES_1 0xE04E8
+
+#define mmMME1_CTRL_SHADOW_0_TENSOR_L_SPATIAL_STRIDES_2 0xE04EC
+
+#define mmMME1_CTRL_SHADOW_0_TENSOR_L_SPATIAL_STRIDES_3 0xE04F0
+
+#define mmMME1_CTRL_SHADOW_0_TENSOR_L_SPATIAL_SIZE_MINUS_1 0xE04F4
+
+#define mmMME1_CTRL_SHADOW_0_AGU_L_LOCAL_ROI_BASE_OFFSET_0 0xE04F8
+
+#define mmMME1_CTRL_SHADOW_0_AGU_L_LOCAL_ROI_BASE_OFFSET_1 0xE04FC
+
+#define mmMME1_CTRL_SHADOW_0_AGU_L_LOCAL_ROI_BASE_OFFSET_2 0xE0500
+
+#define mmMME1_CTRL_SHADOW_0_AGU_L_LOCAL_ROI_BASE_OFFSET_3 0xE0504
+
+#define mmMME1_CTRL_SHADOW_0_AGU_L_LOCAL_ROI_BASE_OFFSET_4 0xE0508
+
+#define mmMME1_CTRL_SHADOW_0_AGU_L_LOCAL_START_OFFSET_0 0xE050C
+
+#define mmMME1_CTRL_SHADOW_0_AGU_L_LOCAL_START_OFFSET_1 0xE0510
+
+#define mmMME1_CTRL_SHADOW_0_AGU_L_LOCAL_START_OFFSET_2 0xE0514
+
+#define mmMME1_CTRL_SHADOW_0_AGU_L_LOCAL_START_OFFSET_3 0xE0518
+
+#define mmMME1_CTRL_SHADOW_0_AGU_L_REMOTE_ROI_BASE_OFFSET_0 0xE051C
+
+#define mmMME1_CTRL_SHADOW_0_AGU_L_REMOTE_ROI_BASE_OFFSET_1 0xE0520
+
+#define mmMME1_CTRL_SHADOW_0_AGU_L_REMOTE_ROI_BASE_OFFSET_2 0xE0524
+
+#define mmMME1_CTRL_SHADOW_0_AGU_L_REMOTE_ROI_BASE_OFFSET_3 0xE0528
+
+#define mmMME1_CTRL_SHADOW_0_AGU_L_REMOTE_ROI_BASE_OFFSET_4 0xE052C
+
+#define mmMME1_CTRL_SHADOW_0_AGU_L_REMOTE_START_OFFSET_0 0xE0530
+
+#define mmMME1_CTRL_SHADOW_0_AGU_L_REMOTE_START_OFFSET_1 0xE0534
+
+#define mmMME1_CTRL_SHADOW_0_AGU_L_REMOTE_START_OFFSET_2 0xE0538
+
+#define mmMME1_CTRL_SHADOW_0_AGU_L_REMOTE_START_OFFSET_3 0xE053C
+
+#define mmMME1_CTRL_SHADOW_0_TENSOR_O_VALID_ELEMENTS_0 0xE0540
+
+#define mmMME1_CTRL_SHADOW_0_TENSOR_O_VALID_ELEMENTS_1 0xE0544
+
+#define mmMME1_CTRL_SHADOW_0_TENSOR_O_VALID_ELEMENTS_2 0xE0548
+
+#define mmMME1_CTRL_SHADOW_0_TENSOR_O_VALID_ELEMENTS_3 0xE054C
+
+#define mmMME1_CTRL_SHADOW_0_TENSOR_O_VALID_ELEMENTS_4 0xE0550
+
+#define mmMME1_CTRL_SHADOW_0_TENSOR_O_LOOP_STRIDE_0 0xE0554
+
+#define mmMME1_CTRL_SHADOW_0_TENSOR_O_LOOP_STRIDE_1 0xE0558
+
+#define mmMME1_CTRL_SHADOW_0_TENSOR_O_LOOP_STRIDE_2 0xE055C
+
+#define mmMME1_CTRL_SHADOW_0_TENSOR_O_LOOP_STRIDE_3 0xE0560
+
+#define mmMME1_CTRL_SHADOW_0_TENSOR_O_LOOP_STRIDE_4 0xE0564
+
+#define mmMME1_CTRL_SHADOW_0_TENSOR_O_ROI_SIZE_0 0xE0568
+
+#define mmMME1_CTRL_SHADOW_0_TENSOR_O_ROI_SIZE_1 0xE056C
+
+#define mmMME1_CTRL_SHADOW_0_TENSOR_O_ROI_SIZE_2 0xE0570
+
+#define mmMME1_CTRL_SHADOW_0_TENSOR_O_ROI_SIZE_3 0xE0574
+
+#define mmMME1_CTRL_SHADOW_0_TENSOR_O_SPATIAL_STRIDES_0 0xE0578
+
+#define mmMME1_CTRL_SHADOW_0_TENSOR_O_SPATIAL_STRIDES_1 0xE057C
+
+#define mmMME1_CTRL_SHADOW_0_TENSOR_O_SPATIAL_STRIDES_2 0xE0580
+
+#define mmMME1_CTRL_SHADOW_0_TENSOR_O_SPATIAL_STRIDES_3 0xE0584
+
+#define mmMME1_CTRL_SHADOW_0_TENSOR_O_SPATIAL_SIZE_MINUS_1 0xE0588
+
+#define mmMME1_CTRL_SHADOW_0_AGU_O_LOCAL_ROI_BASE_OFFSET_0 0xE058C
+
+#define mmMME1_CTRL_SHADOW_0_AGU_O_LOCAL_ROI_BASE_OFFSET_1 0xE0590
+
+#define mmMME1_CTRL_SHADOW_0_AGU_O_LOCAL_ROI_BASE_OFFSET_2 0xE0594
+
+#define mmMME1_CTRL_SHADOW_0_AGU_O_LOCAL_ROI_BASE_OFFSET_3 0xE0598
+
+#define mmMME1_CTRL_SHADOW_0_AGU_O_LOCAL_ROI_BASE_OFFSET_4 0xE059C
+
+#define mmMME1_CTRL_SHADOW_0_AGU_O_LOCAL_START_OFFSET_0 0xE05A0
+
+#define mmMME1_CTRL_SHADOW_0_AGU_O_LOCAL_START_OFFSET_1 0xE05A4
+
+#define mmMME1_CTRL_SHADOW_0_AGU_O_LOCAL_START_OFFSET_2 0xE05A8
+
+#define mmMME1_CTRL_SHADOW_0_AGU_O_LOCAL_START_OFFSET_3 0xE05AC
+
+#define mmMME1_CTRL_SHADOW_0_AGU_O_REMOTE_ROI_BASE_OFFSET_0 0xE05B0
+
+#define mmMME1_CTRL_SHADOW_0_AGU_O_REMOTE_ROI_BASE_OFFSET_1 0xE05B4
+
+#define mmMME1_CTRL_SHADOW_0_AGU_O_REMOTE_ROI_BASE_OFFSET_2 0xE05B8
+
+#define mmMME1_CTRL_SHADOW_0_AGU_O_REMOTE_ROI_BASE_OFFSET_3 0xE05BC
+
+#define mmMME1_CTRL_SHADOW_0_AGU_O_REMOTE_ROI_BASE_OFFSET_4 0xE05C0
+
+#define mmMME1_CTRL_SHADOW_0_AGU_O_REMOTE_START_OFFSET_0 0xE05C4
+
+#define mmMME1_CTRL_SHADOW_0_AGU_O_REMOTE_START_OFFSET_1 0xE05C8
+
+#define mmMME1_CTRL_SHADOW_0_AGU_O_REMOTE_START_OFFSET_2 0xE05CC
+
+#define mmMME1_CTRL_SHADOW_0_AGU_O_REMOTE_START_OFFSET_3 0xE05D0
+
+#define mmMME1_CTRL_SHADOW_0_DESC_SB_REPEAT 0xE05D4
+
+#define mmMME1_CTRL_SHADOW_0_DESC_RATE_LIMITER 0xE05D8
+
+#define mmMME1_CTRL_SHADOW_0_DESC_SYNC_OBJECT_ADDR_LOW_LOCAL 0xE05DC
+
+#define mmMME1_CTRL_SHADOW_0_DESC_SYNC_OBJECT_ADDR_LOW_REMOTE 0xE05E0
+
+#define mmMME1_CTRL_SHADOW_0_DESC_SYNC_OBJECT_ADDR_HIGH 0xE05E4
+
+#define mmMME1_CTRL_SHADOW_0_DESC_SYNC_OBJECT_DATA 0xE05E8
+
+#define mmMME1_CTRL_SHADOW_0_DESC_AXI_USER_DATA 0xE05EC
+
+#define mmMME1_CTRL_SHADOW_0_DESC_PERF_EVT_S 0xE05F0
+
+#define mmMME1_CTRL_SHADOW_0_DESC_PERF_EVT_L_LOCAL 0xE05F4
+
+#define mmMME1_CTRL_SHADOW_0_DESC_PERF_EVT_L_REMOTE 0xE05F8
+
+#define mmMME1_CTRL_SHADOW_0_DESC_PERF_EVT_O_LOCAL 0xE05FC
+
+#define mmMME1_CTRL_SHADOW_0_DESC_PERF_EVT_O_REMOTE 0xE0600
+
+#define mmMME1_CTRL_SHADOW_0_DESC_PADDING_VALUE_S 0xE0604
+
+#define mmMME1_CTRL_SHADOW_0_DESC_PADDING_VALUE_L 0xE0608
+
+#define mmMME1_CTRL_SHADOW_0_DESC_META_DATA_AGU_S 0xE060C
+
+#define mmMME1_CTRL_SHADOW_0_DESC_META_DATA_AGU_L_LOCAL 0xE0610
+
+#define mmMME1_CTRL_SHADOW_0_DESC_META_DATA_AGU_L_REMOTE 0xE0614
+
+#define mmMME1_CTRL_SHADOW_0_DESC_META_DATA_AGU_O_LOCAL 0xE0618
+
+#define mmMME1_CTRL_SHADOW_0_DESC_META_DATA_AGU_O_REMOTE 0xE061C
+
+#define mmMME1_CTRL_SHADOW_0_DESC_PCU_RL_SATURATION 0xE0620
+
+#define mmMME1_CTRL_SHADOW_0_DESC_DUMMY 0xE0624
+
+#define mmMME1_CTRL_SHADOW_1_STATUS 0xE0680
+
+#define mmMME1_CTRL_SHADOW_1_BASE_ADDR_HIGH_S 0xE0688
+
+#define mmMME1_CTRL_SHADOW_1_BASE_ADDR_HIGH_L 0xE068C
+
+#define mmMME1_CTRL_SHADOW_1_BASE_ADDR_HIGH_O 0xE0690
+
+#define mmMME1_CTRL_SHADOW_1_BASE_ADDR_LOW_S 0xE0694
+
+#define mmMME1_CTRL_SHADOW_1_BASE_ADDR_LOW_L 0xE0698
+
+#define mmMME1_CTRL_SHADOW_1_BASE_ADDR_LOW_O 0xE069C
+
+#define mmMME1_CTRL_SHADOW_1_HEADER_LOW 0xE06A0
+
+#define mmMME1_CTRL_SHADOW_1_HEADER_HIGH 0xE06A4
+
+#define mmMME1_CTRL_SHADOW_1_CONV_KERNEL_SIZE_MINUS_1 0xE06A8
+
+#define mmMME1_CTRL_SHADOW_1_CONV_ASSOCIATED_DIMS_LOW 0xE06AC
+
+#define mmMME1_CTRL_SHADOW_1_CONV_ASSOCIATED_DIMS_HIGH 0xE06B0
+
+#define mmMME1_CTRL_SHADOW_1_NUM_ITERATIONS_MINUS_1 0xE06B4
+
+#define mmMME1_CTRL_SHADOW_1_OUTER_LOOP 0xE06B8
+
+#define mmMME1_CTRL_SHADOW_1_TENSOR_S_VALID_ELEMENTS_0 0xE06BC
+
+#define mmMME1_CTRL_SHADOW_1_TENSOR_S_VALID_ELEMENTS_1 0xE06C0
+
+#define mmMME1_CTRL_SHADOW_1_TENSOR_S_VALID_ELEMENTS_2 0xE06C4
+
+#define mmMME1_CTRL_SHADOW_1_TENSOR_S_VALID_ELEMENTS_3 0xE06C8
+
+#define mmMME1_CTRL_SHADOW_1_TENSOR_S_VALID_ELEMENTS_4 0xE06CC
+
+#define mmMME1_CTRL_SHADOW_1_TENSOR_S_LOOP_STRIDE_0 0xE06D0
+
+#define mmMME1_CTRL_SHADOW_1_TENSOR_S_LOOP_STRIDE_1 0xE06D4
+
+#define mmMME1_CTRL_SHADOW_1_TENSOR_S_LOOP_STRIDE_2 0xE06D8
+
+#define mmMME1_CTRL_SHADOW_1_TENSOR_S_LOOP_STRIDE_3 0xE06DC
+
+#define mmMME1_CTRL_SHADOW_1_TENSOR_S_LOOP_STRIDE_4 0xE06E0
+
+#define mmMME1_CTRL_SHADOW_1_TENSOR_S_ROI_SIZE_0 0xE06E4
+
+#define mmMME1_CTRL_SHADOW_1_TENSOR_S_ROI_SIZE_1 0xE06E8
+
+#define mmMME1_CTRL_SHADOW_1_TENSOR_S_ROI_SIZE_2 0xE06EC
+
+#define mmMME1_CTRL_SHADOW_1_TENSOR_S_ROI_SIZE_3 0xE06F0
+
+#define mmMME1_CTRL_SHADOW_1_TENSOR_S_SPATIAL_STRIDES_0 0xE06F4
+
+#define mmMME1_CTRL_SHADOW_1_TENSOR_S_SPATIAL_STRIDES_1 0xE06F8
+
+#define mmMME1_CTRL_SHADOW_1_TENSOR_S_SPATIAL_STRIDES_2 0xE06FC
+
+#define mmMME1_CTRL_SHADOW_1_TENSOR_S_SPATIAL_STRIDES_3 0xE0700
+
+#define mmMME1_CTRL_SHADOW_1_TENSOR_S_SPATIAL_SIZE_MINUS_1 0xE0704
+
+#define mmMME1_CTRL_SHADOW_1_AGU_S_ROI_BASE_OFFSET_0 0xE0708
+
+#define mmMME1_CTRL_SHADOW_1_AGU_S_ROI_BASE_OFFSET_1 0xE070C
+
+#define mmMME1_CTRL_SHADOW_1_AGU_S_ROI_BASE_OFFSET_2 0xE0710
+
+#define mmMME1_CTRL_SHADOW_1_AGU_S_ROI_BASE_OFFSET_3 0xE0714
+
+#define mmMME1_CTRL_SHADOW_1_AGU_S_ROI_BASE_OFFSET_4 0xE0718
+
+#define mmMME1_CTRL_SHADOW_1_AGU_S_START_OFFSET_0 0xE071C
+
+#define mmMME1_CTRL_SHADOW_1_AGU_S_START_OFFSET_1 0xE0720
+
+#define mmMME1_CTRL_SHADOW_1_AGU_S_START_OFFSET_2 0xE0724
+
+#define mmMME1_CTRL_SHADOW_1_AGU_S_START_OFFSET_3 0xE0728
+
+#define mmMME1_CTRL_SHADOW_1_TENSOR_L_VALID_ELEMENTS_0 0xE072C
+
+#define mmMME1_CTRL_SHADOW_1_TENSOR_L_VALID_ELEMENTS_1 0xE0730
+
+#define mmMME1_CTRL_SHADOW_1_TENSOR_L_VALID_ELEMENTS_2 0xE0734
+
+#define mmMME1_CTRL_SHADOW_1_TENSOR_L_VALID_ELEMENTS_3 0xE0738
+
+#define mmMME1_CTRL_SHADOW_1_TENSOR_L_VALID_ELEMENTS_4 0xE073C
+
+#define mmMME1_CTRL_SHADOW_1_TENSOR_L_LOOP_STRIDE_0 0xE0740
+
+#define mmMME1_CTRL_SHADOW_1_TENSOR_L_LOOP_STRIDE_1 0xE0744
+
+#define mmMME1_CTRL_SHADOW_1_TENSOR_L_LOOP_STRIDE_2 0xE0748
+
+#define mmMME1_CTRL_SHADOW_1_TENSOR_L_LOOP_STRIDE_3 0xE074C
+
+#define mmMME1_CTRL_SHADOW_1_TENSOR_L_LOOP_STRIDE_4 0xE0750
+
+#define mmMME1_CTRL_SHADOW_1_TENSOR_L_ROI_SIZE_0 0xE0754
+
+#define mmMME1_CTRL_SHADOW_1_TENSOR_L_ROI_SIZE_1 0xE0758
+
+#define mmMME1_CTRL_SHADOW_1_TENSOR_L_ROI_SIZE_2 0xE075C
+
+#define mmMME1_CTRL_SHADOW_1_TENSOR_L_ROI_SIZE_3 0xE0760
+
+#define mmMME1_CTRL_SHADOW_1_TENSOR_L_SPATIAL_STRIDES_0 0xE0764
+
+#define mmMME1_CTRL_SHADOW_1_TENSOR_L_SPATIAL_STRIDES_1 0xE0768
+
+#define mmMME1_CTRL_SHADOW_1_TENSOR_L_SPATIAL_STRIDES_2 0xE076C
+
+#define mmMME1_CTRL_SHADOW_1_TENSOR_L_SPATIAL_STRIDES_3 0xE0770
+
+#define mmMME1_CTRL_SHADOW_1_TENSOR_L_SPATIAL_SIZE_MINUS_1 0xE0774
+
+#define mmMME1_CTRL_SHADOW_1_AGU_L_LOCAL_ROI_BASE_OFFSET_0 0xE0778
+
+#define mmMME1_CTRL_SHADOW_1_AGU_L_LOCAL_ROI_BASE_OFFSET_1 0xE077C
+
+#define mmMME1_CTRL_SHADOW_1_AGU_L_LOCAL_ROI_BASE_OFFSET_2 0xE0780
+
+#define mmMME1_CTRL_SHADOW_1_AGU_L_LOCAL_ROI_BASE_OFFSET_3 0xE0784
+
+#define mmMME1_CTRL_SHADOW_1_AGU_L_LOCAL_ROI_BASE_OFFSET_4 0xE0788
+
+#define mmMME1_CTRL_SHADOW_1_AGU_L_LOCAL_START_OFFSET_0 0xE078C
+
+#define mmMME1_CTRL_SHADOW_1_AGU_L_LOCAL_START_OFFSET_1 0xE0790
+
+#define mmMME1_CTRL_SHADOW_1_AGU_L_LOCAL_START_OFFSET_2 0xE0794
+
+#define mmMME1_CTRL_SHADOW_1_AGU_L_LOCAL_START_OFFSET_3 0xE0798
+
+#define mmMME1_CTRL_SHADOW_1_AGU_L_REMOTE_ROI_BASE_OFFSET_0 0xE079C
+
+#define mmMME1_CTRL_SHADOW_1_AGU_L_REMOTE_ROI_BASE_OFFSET_1 0xE07A0
+
+#define mmMME1_CTRL_SHADOW_1_AGU_L_REMOTE_ROI_BASE_OFFSET_2 0xE07A4
+
+#define mmMME1_CTRL_SHADOW_1_AGU_L_REMOTE_ROI_BASE_OFFSET_3 0xE07A8
+
+#define mmMME1_CTRL_SHADOW_1_AGU_L_REMOTE_ROI_BASE_OFFSET_4 0xE07AC
+
+#define mmMME1_CTRL_SHADOW_1_AGU_L_REMOTE_START_OFFSET_0 0xE07B0
+
+#define mmMME1_CTRL_SHADOW_1_AGU_L_REMOTE_START_OFFSET_1 0xE07B4
+
+#define mmMME1_CTRL_SHADOW_1_AGU_L_REMOTE_START_OFFSET_2 0xE07B8
+
+#define mmMME1_CTRL_SHADOW_1_AGU_L_REMOTE_START_OFFSET_3 0xE07BC
+
+#define mmMME1_CTRL_SHADOW_1_TENSOR_O_VALID_ELEMENTS_0 0xE07C0
+
+#define mmMME1_CTRL_SHADOW_1_TENSOR_O_VALID_ELEMENTS_1 0xE07C4
+
+#define mmMME1_CTRL_SHADOW_1_TENSOR_O_VALID_ELEMENTS_2 0xE07C8
+
+#define mmMME1_CTRL_SHADOW_1_TENSOR_O_VALID_ELEMENTS_3 0xE07CC
+
+#define mmMME1_CTRL_SHADOW_1_TENSOR_O_VALID_ELEMENTS_4 0xE07D0
+
+#define mmMME1_CTRL_SHADOW_1_TENSOR_O_LOOP_STRIDE_0 0xE07D4
+
+#define mmMME1_CTRL_SHADOW_1_TENSOR_O_LOOP_STRIDE_1 0xE07D8
+
+#define mmMME1_CTRL_SHADOW_1_TENSOR_O_LOOP_STRIDE_2 0xE07DC
+
+#define mmMME1_CTRL_SHADOW_1_TENSOR_O_LOOP_STRIDE_3 0xE07E0
+
+#define mmMME1_CTRL_SHADOW_1_TENSOR_O_LOOP_STRIDE_4 0xE07E4
+
+#define mmMME1_CTRL_SHADOW_1_TENSOR_O_ROI_SIZE_0 0xE07E8
+
+#define mmMME1_CTRL_SHADOW_1_TENSOR_O_ROI_SIZE_1 0xE07EC
+
+#define mmMME1_CTRL_SHADOW_1_TENSOR_O_ROI_SIZE_2 0xE07F0
+
+#define mmMME1_CTRL_SHADOW_1_TENSOR_O_ROI_SIZE_3 0xE07F4
+
+#define mmMME1_CTRL_SHADOW_1_TENSOR_O_SPATIAL_STRIDES_0 0xE07F8
+
+#define mmMME1_CTRL_SHADOW_1_TENSOR_O_SPATIAL_STRIDES_1 0xE07FC
+
+#define mmMME1_CTRL_SHADOW_1_TENSOR_O_SPATIAL_STRIDES_2 0xE0800
+
+#define mmMME1_CTRL_SHADOW_1_TENSOR_O_SPATIAL_STRIDES_3 0xE0804
+
+#define mmMME1_CTRL_SHADOW_1_TENSOR_O_SPATIAL_SIZE_MINUS_1 0xE0808
+
+#define mmMME1_CTRL_SHADOW_1_AGU_O_LOCAL_ROI_BASE_OFFSET_0 0xE080C
+
+#define mmMME1_CTRL_SHADOW_1_AGU_O_LOCAL_ROI_BASE_OFFSET_1 0xE0810
+
+#define mmMME1_CTRL_SHADOW_1_AGU_O_LOCAL_ROI_BASE_OFFSET_2 0xE0814
+
+#define mmMME1_CTRL_SHADOW_1_AGU_O_LOCAL_ROI_BASE_OFFSET_3 0xE0818
+
+#define mmMME1_CTRL_SHADOW_1_AGU_O_LOCAL_ROI_BASE_OFFSET_4 0xE081C
+
+#define mmMME1_CTRL_SHADOW_1_AGU_O_LOCAL_START_OFFSET_0 0xE0820
+
+#define mmMME1_CTRL_SHADOW_1_AGU_O_LOCAL_START_OFFSET_1 0xE0824
+
+#define mmMME1_CTRL_SHADOW_1_AGU_O_LOCAL_START_OFFSET_2 0xE0828
+
+#define mmMME1_CTRL_SHADOW_1_AGU_O_LOCAL_START_OFFSET_3 0xE082C
+
+#define mmMME1_CTRL_SHADOW_1_AGU_O_REMOTE_ROI_BASE_OFFSET_0 0xE0830
+
+#define mmMME1_CTRL_SHADOW_1_AGU_O_REMOTE_ROI_BASE_OFFSET_1 0xE0834
+
+#define mmMME1_CTRL_SHADOW_1_AGU_O_REMOTE_ROI_BASE_OFFSET_2 0xE0838
+
+#define mmMME1_CTRL_SHADOW_1_AGU_O_REMOTE_ROI_BASE_OFFSET_3 0xE083C
+
+#define mmMME1_CTRL_SHADOW_1_AGU_O_REMOTE_ROI_BASE_OFFSET_4 0xE0840
+
+#define mmMME1_CTRL_SHADOW_1_AGU_O_REMOTE_START_OFFSET_0 0xE0844
+
+#define mmMME1_CTRL_SHADOW_1_AGU_O_REMOTE_START_OFFSET_1 0xE0848
+
+#define mmMME1_CTRL_SHADOW_1_AGU_O_REMOTE_START_OFFSET_2 0xE084C
+
+#define mmMME1_CTRL_SHADOW_1_AGU_O_REMOTE_START_OFFSET_3 0xE0850
+
+#define mmMME1_CTRL_SHADOW_1_DESC_SB_REPEAT 0xE0854
+
+#define mmMME1_CTRL_SHADOW_1_DESC_RATE_LIMITER 0xE0858
+
+#define mmMME1_CTRL_SHADOW_1_DESC_SYNC_OBJECT_ADDR_LOW_LOCAL 0xE085C
+
+#define mmMME1_CTRL_SHADOW_1_DESC_SYNC_OBJECT_ADDR_LOW_REMOTE 0xE0860
+
+#define mmMME1_CTRL_SHADOW_1_DESC_SYNC_OBJECT_ADDR_HIGH 0xE0864
+
+#define mmMME1_CTRL_SHADOW_1_DESC_SYNC_OBJECT_DATA 0xE0868
+
+#define mmMME1_CTRL_SHADOW_1_DESC_AXI_USER_DATA 0xE086C
+
+#define mmMME1_CTRL_SHADOW_1_DESC_PERF_EVT_S 0xE0870
+
+#define mmMME1_CTRL_SHADOW_1_DESC_PERF_EVT_L_LOCAL 0xE0874
+
+#define mmMME1_CTRL_SHADOW_1_DESC_PERF_EVT_L_REMOTE 0xE0878
+
+#define mmMME1_CTRL_SHADOW_1_DESC_PERF_EVT_O_LOCAL 0xE087C
+
+#define mmMME1_CTRL_SHADOW_1_DESC_PERF_EVT_O_REMOTE 0xE0880
+
+#define mmMME1_CTRL_SHADOW_1_DESC_PADDING_VALUE_S 0xE0884
+
+#define mmMME1_CTRL_SHADOW_1_DESC_PADDING_VALUE_L 0xE0888
+
+#define mmMME1_CTRL_SHADOW_1_DESC_META_DATA_AGU_S 0xE088C
+
+#define mmMME1_CTRL_SHADOW_1_DESC_META_DATA_AGU_L_LOCAL 0xE0890
+
+#define mmMME1_CTRL_SHADOW_1_DESC_META_DATA_AGU_L_REMOTE 0xE0894
+
+#define mmMME1_CTRL_SHADOW_1_DESC_META_DATA_AGU_O_LOCAL 0xE0898
+
+#define mmMME1_CTRL_SHADOW_1_DESC_META_DATA_AGU_O_REMOTE 0xE089C
+
+#define mmMME1_CTRL_SHADOW_1_DESC_PCU_RL_SATURATION 0xE08A0
+
+#define mmMME1_CTRL_SHADOW_1_DESC_DUMMY 0xE08A4
+
+#define mmMME1_CTRL_SHADOW_2_STATUS 0xE0900
+
+#define mmMME1_CTRL_SHADOW_2_BASE_ADDR_HIGH_S 0xE0908
+
+#define mmMME1_CTRL_SHADOW_2_BASE_ADDR_HIGH_L 0xE090C
+
+#define mmMME1_CTRL_SHADOW_2_BASE_ADDR_HIGH_O 0xE0910
+
+#define mmMME1_CTRL_SHADOW_2_BASE_ADDR_LOW_S 0xE0914
+
+#define mmMME1_CTRL_SHADOW_2_BASE_ADDR_LOW_L 0xE0918
+
+#define mmMME1_CTRL_SHADOW_2_BASE_ADDR_LOW_O 0xE091C
+
+#define mmMME1_CTRL_SHADOW_2_HEADER_LOW 0xE0920
+
+#define mmMME1_CTRL_SHADOW_2_HEADER_HIGH 0xE0924
+
+#define mmMME1_CTRL_SHADOW_2_CONV_KERNEL_SIZE_MINUS_1 0xE0928
+
+#define mmMME1_CTRL_SHADOW_2_CONV_ASSOCIATED_DIMS_LOW 0xE092C
+
+#define mmMME1_CTRL_SHADOW_2_CONV_ASSOCIATED_DIMS_HIGH 0xE0930
+
+#define mmMME1_CTRL_SHADOW_2_NUM_ITERATIONS_MINUS_1 0xE0934
+
+#define mmMME1_CTRL_SHADOW_2_OUTER_LOOP 0xE0938
+
+#define mmMME1_CTRL_SHADOW_2_TENSOR_S_VALID_ELEMENTS_0 0xE093C
+
+#define mmMME1_CTRL_SHADOW_2_TENSOR_S_VALID_ELEMENTS_1 0xE0940
+
+#define mmMME1_CTRL_SHADOW_2_TENSOR_S_VALID_ELEMENTS_2 0xE0944
+
+#define mmMME1_CTRL_SHADOW_2_TENSOR_S_VALID_ELEMENTS_3 0xE0948
+
+#define mmMME1_CTRL_SHADOW_2_TENSOR_S_VALID_ELEMENTS_4 0xE094C
+
+#define mmMME1_CTRL_SHADOW_2_TENSOR_S_LOOP_STRIDE_0 0xE0950
+
+#define mmMME1_CTRL_SHADOW_2_TENSOR_S_LOOP_STRIDE_1 0xE0954
+
+#define mmMME1_CTRL_SHADOW_2_TENSOR_S_LOOP_STRIDE_2 0xE0958
+
+#define mmMME1_CTRL_SHADOW_2_TENSOR_S_LOOP_STRIDE_3 0xE095C
+
+#define mmMME1_CTRL_SHADOW_2_TENSOR_S_LOOP_STRIDE_4 0xE0960
+
+#define mmMME1_CTRL_SHADOW_2_TENSOR_S_ROI_SIZE_0 0xE0964
+
+#define mmMME1_CTRL_SHADOW_2_TENSOR_S_ROI_SIZE_1 0xE0968
+
+#define mmMME1_CTRL_SHADOW_2_TENSOR_S_ROI_SIZE_2 0xE096C
+
+#define mmMME1_CTRL_SHADOW_2_TENSOR_S_ROI_SIZE_3 0xE0970
+
+#define mmMME1_CTRL_SHADOW_2_TENSOR_S_SPATIAL_STRIDES_0 0xE0974
+
+#define mmMME1_CTRL_SHADOW_2_TENSOR_S_SPATIAL_STRIDES_1 0xE0978
+
+#define mmMME1_CTRL_SHADOW_2_TENSOR_S_SPATIAL_STRIDES_2 0xE097C
+
+#define mmMME1_CTRL_SHADOW_2_TENSOR_S_SPATIAL_STRIDES_3 0xE0980
+
+#define mmMME1_CTRL_SHADOW_2_TENSOR_S_SPATIAL_SIZE_MINUS_1 0xE0984
+
+#define mmMME1_CTRL_SHADOW_2_AGU_S_ROI_BASE_OFFSET_0 0xE0988
+
+#define mmMME1_CTRL_SHADOW_2_AGU_S_ROI_BASE_OFFSET_1 0xE098C
+
+#define mmMME1_CTRL_SHADOW_2_AGU_S_ROI_BASE_OFFSET_2 0xE0990
+
+#define mmMME1_CTRL_SHADOW_2_AGU_S_ROI_BASE_OFFSET_3 0xE0994
+
+#define mmMME1_CTRL_SHADOW_2_AGU_S_ROI_BASE_OFFSET_4 0xE0998
+
+#define mmMME1_CTRL_SHADOW_2_AGU_S_START_OFFSET_0 0xE099C
+
+#define mmMME1_CTRL_SHADOW_2_AGU_S_START_OFFSET_1 0xE09A0
+
+#define mmMME1_CTRL_SHADOW_2_AGU_S_START_OFFSET_2 0xE09A4
+
+#define mmMME1_CTRL_SHADOW_2_AGU_S_START_OFFSET_3 0xE09A8
+
+#define mmMME1_CTRL_SHADOW_2_TENSOR_L_VALID_ELEMENTS_0 0xE09AC
+
+#define mmMME1_CTRL_SHADOW_2_TENSOR_L_VALID_ELEMENTS_1 0xE09B0
+
+#define mmMME1_CTRL_SHADOW_2_TENSOR_L_VALID_ELEMENTS_2 0xE09B4
+
+#define mmMME1_CTRL_SHADOW_2_TENSOR_L_VALID_ELEMENTS_3 0xE09B8
+
+#define mmMME1_CTRL_SHADOW_2_TENSOR_L_VALID_ELEMENTS_4 0xE09BC
+
+#define mmMME1_CTRL_SHADOW_2_TENSOR_L_LOOP_STRIDE_0 0xE09C0
+
+#define mmMME1_CTRL_SHADOW_2_TENSOR_L_LOOP_STRIDE_1 0xE09C4
+
+#define mmMME1_CTRL_SHADOW_2_TENSOR_L_LOOP_STRIDE_2 0xE09C8
+
+#define mmMME1_CTRL_SHADOW_2_TENSOR_L_LOOP_STRIDE_3 0xE09CC
+
+#define mmMME1_CTRL_SHADOW_2_TENSOR_L_LOOP_STRIDE_4 0xE09D0
+
+#define mmMME1_CTRL_SHADOW_2_TENSOR_L_ROI_SIZE_0 0xE09D4
+
+#define mmMME1_CTRL_SHADOW_2_TENSOR_L_ROI_SIZE_1 0xE09D8
+
+#define mmMME1_CTRL_SHADOW_2_TENSOR_L_ROI_SIZE_2 0xE09DC
+
+#define mmMME1_CTRL_SHADOW_2_TENSOR_L_ROI_SIZE_3 0xE09E0
+
+#define mmMME1_CTRL_SHADOW_2_TENSOR_L_SPATIAL_STRIDES_0 0xE09E4
+
+#define mmMME1_CTRL_SHADOW_2_TENSOR_L_SPATIAL_STRIDES_1 0xE09E8
+
+#define mmMME1_CTRL_SHADOW_2_TENSOR_L_SPATIAL_STRIDES_2 0xE09EC
+
+#define mmMME1_CTRL_SHADOW_2_TENSOR_L_SPATIAL_STRIDES_3 0xE09F0
+
+#define mmMME1_CTRL_SHADOW_2_TENSOR_L_SPATIAL_SIZE_MINUS_1 0xE09F4
+
+#define mmMME1_CTRL_SHADOW_2_AGU_L_LOCAL_ROI_BASE_OFFSET_0 0xE09F8
+
+#define mmMME1_CTRL_SHADOW_2_AGU_L_LOCAL_ROI_BASE_OFFSET_1 0xE09FC
+
+#define mmMME1_CTRL_SHADOW_2_AGU_L_LOCAL_ROI_BASE_OFFSET_2 0xE0A00
+
+#define mmMME1_CTRL_SHADOW_2_AGU_L_LOCAL_ROI_BASE_OFFSET_3 0xE0A04
+
+#define mmMME1_CTRL_SHADOW_2_AGU_L_LOCAL_ROI_BASE_OFFSET_4 0xE0A08
+
+#define mmMME1_CTRL_SHADOW_2_AGU_L_LOCAL_START_OFFSET_0 0xE0A0C
+
+#define mmMME1_CTRL_SHADOW_2_AGU_L_LOCAL_START_OFFSET_1 0xE0A10
+
+#define mmMME1_CTRL_SHADOW_2_AGU_L_LOCAL_START_OFFSET_2 0xE0A14
+
+#define mmMME1_CTRL_SHADOW_2_AGU_L_LOCAL_START_OFFSET_3 0xE0A18
+
+#define mmMME1_CTRL_SHADOW_2_AGU_L_REMOTE_ROI_BASE_OFFSET_0 0xE0A1C
+
+#define mmMME1_CTRL_SHADOW_2_AGU_L_REMOTE_ROI_BASE_OFFSET_1 0xE0A20
+
+#define mmMME1_CTRL_SHADOW_2_AGU_L_REMOTE_ROI_BASE_OFFSET_2 0xE0A24
+
+#define mmMME1_CTRL_SHADOW_2_AGU_L_REMOTE_ROI_BASE_OFFSET_3 0xE0A28
+
+#define mmMME1_CTRL_SHADOW_2_AGU_L_REMOTE_ROI_BASE_OFFSET_4 0xE0A2C
+
+#define mmMME1_CTRL_SHADOW_2_AGU_L_REMOTE_START_OFFSET_0 0xE0A30
+
+#define mmMME1_CTRL_SHADOW_2_AGU_L_REMOTE_START_OFFSET_1 0xE0A34
+
+#define mmMME1_CTRL_SHADOW_2_AGU_L_REMOTE_START_OFFSET_2 0xE0A38
+
+#define mmMME1_CTRL_SHADOW_2_AGU_L_REMOTE_START_OFFSET_3 0xE0A3C
+
+#define mmMME1_CTRL_SHADOW_2_TENSOR_O_VALID_ELEMENTS_0 0xE0A40
+
+#define mmMME1_CTRL_SHADOW_2_TENSOR_O_VALID_ELEMENTS_1 0xE0A44
+
+#define mmMME1_CTRL_SHADOW_2_TENSOR_O_VALID_ELEMENTS_2 0xE0A48
+
+#define mmMME1_CTRL_SHADOW_2_TENSOR_O_VALID_ELEMENTS_3 0xE0A4C
+
+#define mmMME1_CTRL_SHADOW_2_TENSOR_O_VALID_ELEMENTS_4 0xE0A50
+
+#define mmMME1_CTRL_SHADOW_2_TENSOR_O_LOOP_STRIDE_0 0xE0A54
+
+#define mmMME1_CTRL_SHADOW_2_TENSOR_O_LOOP_STRIDE_1 0xE0A58
+
+#define mmMME1_CTRL_SHADOW_2_TENSOR_O_LOOP_STRIDE_2 0xE0A5C
+
+#define mmMME1_CTRL_SHADOW_2_TENSOR_O_LOOP_STRIDE_3 0xE0A60
+
+#define mmMME1_CTRL_SHADOW_2_TENSOR_O_LOOP_STRIDE_4 0xE0A64
+
+#define mmMME1_CTRL_SHADOW_2_TENSOR_O_ROI_SIZE_0 0xE0A68
+
+#define mmMME1_CTRL_SHADOW_2_TENSOR_O_ROI_SIZE_1 0xE0A6C
+
+#define mmMME1_CTRL_SHADOW_2_TENSOR_O_ROI_SIZE_2 0xE0A70
+
+#define mmMME1_CTRL_SHADOW_2_TENSOR_O_ROI_SIZE_3 0xE0A74
+
+#define mmMME1_CTRL_SHADOW_2_TENSOR_O_SPATIAL_STRIDES_0 0xE0A78
+
+#define mmMME1_CTRL_SHADOW_2_TENSOR_O_SPATIAL_STRIDES_1 0xE0A7C
+
+#define mmMME1_CTRL_SHADOW_2_TENSOR_O_SPATIAL_STRIDES_2 0xE0A80
+
+#define mmMME1_CTRL_SHADOW_2_TENSOR_O_SPATIAL_STRIDES_3 0xE0A84
+
+#define mmMME1_CTRL_SHADOW_2_TENSOR_O_SPATIAL_SIZE_MINUS_1 0xE0A88
+
+#define mmMME1_CTRL_SHADOW_2_AGU_O_LOCAL_ROI_BASE_OFFSET_0 0xE0A8C
+
+#define mmMME1_CTRL_SHADOW_2_AGU_O_LOCAL_ROI_BASE_OFFSET_1 0xE0A90
+
+#define mmMME1_CTRL_SHADOW_2_AGU_O_LOCAL_ROI_BASE_OFFSET_2 0xE0A94
+
+#define mmMME1_CTRL_SHADOW_2_AGU_O_LOCAL_ROI_BASE_OFFSET_3 0xE0A98
+
+#define mmMME1_CTRL_SHADOW_2_AGU_O_LOCAL_ROI_BASE_OFFSET_4 0xE0A9C
+
+#define mmMME1_CTRL_SHADOW_2_AGU_O_LOCAL_START_OFFSET_0 0xE0AA0
+
+#define mmMME1_CTRL_SHADOW_2_AGU_O_LOCAL_START_OFFSET_1 0xE0AA4
+
+#define mmMME1_CTRL_SHADOW_2_AGU_O_LOCAL_START_OFFSET_2 0xE0AA8
+
+#define mmMME1_CTRL_SHADOW_2_AGU_O_LOCAL_START_OFFSET_3 0xE0AAC
+
+#define mmMME1_CTRL_SHADOW_2_AGU_O_REMOTE_ROI_BASE_OFFSET_0 0xE0AB0
+
+#define mmMME1_CTRL_SHADOW_2_AGU_O_REMOTE_ROI_BASE_OFFSET_1 0xE0AB4
+
+#define mmMME1_CTRL_SHADOW_2_AGU_O_REMOTE_ROI_BASE_OFFSET_2 0xE0AB8
+
+#define mmMME1_CTRL_SHADOW_2_AGU_O_REMOTE_ROI_BASE_OFFSET_3 0xE0ABC
+
+#define mmMME1_CTRL_SHADOW_2_AGU_O_REMOTE_ROI_BASE_OFFSET_4 0xE0AC0
+
+#define mmMME1_CTRL_SHADOW_2_AGU_O_REMOTE_START_OFFSET_0 0xE0AC4
+
+#define mmMME1_CTRL_SHADOW_2_AGU_O_REMOTE_START_OFFSET_1 0xE0AC8
+
+#define mmMME1_CTRL_SHADOW_2_AGU_O_REMOTE_START_OFFSET_2 0xE0ACC
+
+#define mmMME1_CTRL_SHADOW_2_AGU_O_REMOTE_START_OFFSET_3 0xE0AD0
+
+#define mmMME1_CTRL_SHADOW_2_DESC_SB_REPEAT 0xE0AD4
+
+#define mmMME1_CTRL_SHADOW_2_DESC_RATE_LIMITER 0xE0AD8
+
+#define mmMME1_CTRL_SHADOW_2_DESC_SYNC_OBJECT_ADDR_LOW_LOCAL 0xE0ADC
+
+#define mmMME1_CTRL_SHADOW_2_DESC_SYNC_OBJECT_ADDR_LOW_REMOTE 0xE0AE0
+
+#define mmMME1_CTRL_SHADOW_2_DESC_SYNC_OBJECT_ADDR_HIGH 0xE0AE4
+
+#define mmMME1_CTRL_SHADOW_2_DESC_SYNC_OBJECT_DATA 0xE0AE8
+
+#define mmMME1_CTRL_SHADOW_2_DESC_AXI_USER_DATA 0xE0AEC
+
+#define mmMME1_CTRL_SHADOW_2_DESC_PERF_EVT_S 0xE0AF0
+
+#define mmMME1_CTRL_SHADOW_2_DESC_PERF_EVT_L_LOCAL 0xE0AF4
+
+#define mmMME1_CTRL_SHADOW_2_DESC_PERF_EVT_L_REMOTE 0xE0AF8
+
+#define mmMME1_CTRL_SHADOW_2_DESC_PERF_EVT_O_LOCAL 0xE0AFC
+
+#define mmMME1_CTRL_SHADOW_2_DESC_PERF_EVT_O_REMOTE 0xE0B00
+
+#define mmMME1_CTRL_SHADOW_2_DESC_PADDING_VALUE_S 0xE0B04
+
+#define mmMME1_CTRL_SHADOW_2_DESC_PADDING_VALUE_L 0xE0B08
+
+#define mmMME1_CTRL_SHADOW_2_DESC_META_DATA_AGU_S 0xE0B0C
+
+#define mmMME1_CTRL_SHADOW_2_DESC_META_DATA_AGU_L_LOCAL 0xE0B10
+
+#define mmMME1_CTRL_SHADOW_2_DESC_META_DATA_AGU_L_REMOTE 0xE0B14
+
+#define mmMME1_CTRL_SHADOW_2_DESC_META_DATA_AGU_O_LOCAL 0xE0B18
+
+#define mmMME1_CTRL_SHADOW_2_DESC_META_DATA_AGU_O_REMOTE 0xE0B1C
+
+#define mmMME1_CTRL_SHADOW_2_DESC_PCU_RL_SATURATION 0xE0B20
+
+#define mmMME1_CTRL_SHADOW_2_DESC_DUMMY 0xE0B24
+
+#define mmMME1_CTRL_SHADOW_3_STATUS 0xE0B80
+
+#define mmMME1_CTRL_SHADOW_3_BASE_ADDR_HIGH_S 0xE0B88
+
+#define mmMME1_CTRL_SHADOW_3_BASE_ADDR_HIGH_L 0xE0B8C
+
+#define mmMME1_CTRL_SHADOW_3_BASE_ADDR_HIGH_O 0xE0B90
+
+#define mmMME1_CTRL_SHADOW_3_BASE_ADDR_LOW_S 0xE0B94
+
+#define mmMME1_CTRL_SHADOW_3_BASE_ADDR_LOW_L 0xE0B98
+
+#define mmMME1_CTRL_SHADOW_3_BASE_ADDR_LOW_O 0xE0B9C
+
+#define mmMME1_CTRL_SHADOW_3_HEADER_LOW 0xE0BA0
+
+#define mmMME1_CTRL_SHADOW_3_HEADER_HIGH 0xE0BA4
+
+#define mmMME1_CTRL_SHADOW_3_CONV_KERNEL_SIZE_MINUS_1 0xE0BA8
+
+#define mmMME1_CTRL_SHADOW_3_CONV_ASSOCIATED_DIMS_LOW 0xE0BAC
+
+#define mmMME1_CTRL_SHADOW_3_CONV_ASSOCIATED_DIMS_HIGH 0xE0BB0
+
+#define mmMME1_CTRL_SHADOW_3_NUM_ITERATIONS_MINUS_1 0xE0BB4
+
+#define mmMME1_CTRL_SHADOW_3_OUTER_LOOP 0xE0BB8
+
+#define mmMME1_CTRL_SHADOW_3_TENSOR_S_VALID_ELEMENTS_0 0xE0BBC
+
+#define mmMME1_CTRL_SHADOW_3_TENSOR_S_VALID_ELEMENTS_1 0xE0BC0
+
+#define mmMME1_CTRL_SHADOW_3_TENSOR_S_VALID_ELEMENTS_2 0xE0BC4
+
+#define mmMME1_CTRL_SHADOW_3_TENSOR_S_VALID_ELEMENTS_3 0xE0BC8
+
+#define mmMME1_CTRL_SHADOW_3_TENSOR_S_VALID_ELEMENTS_4 0xE0BCC
+
+#define mmMME1_CTRL_SHADOW_3_TENSOR_S_LOOP_STRIDE_0 0xE0BD0
+
+#define mmMME1_CTRL_SHADOW_3_TENSOR_S_LOOP_STRIDE_1 0xE0BD4
+
+#define mmMME1_CTRL_SHADOW_3_TENSOR_S_LOOP_STRIDE_2 0xE0BD8
+
+#define mmMME1_CTRL_SHADOW_3_TENSOR_S_LOOP_STRIDE_3 0xE0BDC
+
+#define mmMME1_CTRL_SHADOW_3_TENSOR_S_LOOP_STRIDE_4 0xE0BE0
+
+#define mmMME1_CTRL_SHADOW_3_TENSOR_S_ROI_SIZE_0 0xE0BE4
+
+#define mmMME1_CTRL_SHADOW_3_TENSOR_S_ROI_SIZE_1 0xE0BE8
+
+#define mmMME1_CTRL_SHADOW_3_TENSOR_S_ROI_SIZE_2 0xE0BEC
+
+#define mmMME1_CTRL_SHADOW_3_TENSOR_S_ROI_SIZE_3 0xE0BF0
+
+#define mmMME1_CTRL_SHADOW_3_TENSOR_S_SPATIAL_STRIDES_0 0xE0BF4
+
+#define mmMME1_CTRL_SHADOW_3_TENSOR_S_SPATIAL_STRIDES_1 0xE0BF8
+
+#define mmMME1_CTRL_SHADOW_3_TENSOR_S_SPATIAL_STRIDES_2 0xE0BFC
+
+#define mmMME1_CTRL_SHADOW_3_TENSOR_S_SPATIAL_STRIDES_3 0xE0C00
+
+#define mmMME1_CTRL_SHADOW_3_TENSOR_S_SPATIAL_SIZE_MINUS_1 0xE0C04
+
+#define mmMME1_CTRL_SHADOW_3_AGU_S_ROI_BASE_OFFSET_0 0xE0C08
+
+#define mmMME1_CTRL_SHADOW_3_AGU_S_ROI_BASE_OFFSET_1 0xE0C0C
+
+#define mmMME1_CTRL_SHADOW_3_AGU_S_ROI_BASE_OFFSET_2 0xE0C10
+
+#define mmMME1_CTRL_SHADOW_3_AGU_S_ROI_BASE_OFFSET_3 0xE0C14
+
+#define mmMME1_CTRL_SHADOW_3_AGU_S_ROI_BASE_OFFSET_4 0xE0C18
+
+#define mmMME1_CTRL_SHADOW_3_AGU_S_START_OFFSET_0 0xE0C1C
+
+#define mmMME1_CTRL_SHADOW_3_AGU_S_START_OFFSET_1 0xE0C20
+
+#define mmMME1_CTRL_SHADOW_3_AGU_S_START_OFFSET_2 0xE0C24
+
+#define mmMME1_CTRL_SHADOW_3_AGU_S_START_OFFSET_3 0xE0C28
+
+#define mmMME1_CTRL_SHADOW_3_TENSOR_L_VALID_ELEMENTS_0 0xE0C2C
+
+#define mmMME1_CTRL_SHADOW_3_TENSOR_L_VALID_ELEMENTS_1 0xE0C30
+
+#define mmMME1_CTRL_SHADOW_3_TENSOR_L_VALID_ELEMENTS_2 0xE0C34
+
+#define mmMME1_CTRL_SHADOW_3_TENSOR_L_VALID_ELEMENTS_3 0xE0C38
+
+#define mmMME1_CTRL_SHADOW_3_TENSOR_L_VALID_ELEMENTS_4 0xE0C3C
+
+#define mmMME1_CTRL_SHADOW_3_TENSOR_L_LOOP_STRIDE_0 0xE0C40
+
+#define mmMME1_CTRL_SHADOW_3_TENSOR_L_LOOP_STRIDE_1 0xE0C44
+
+#define mmMME1_CTRL_SHADOW_3_TENSOR_L_LOOP_STRIDE_2 0xE0C48
+
+#define mmMME1_CTRL_SHADOW_3_TENSOR_L_LOOP_STRIDE_3 0xE0C4C
+
+#define mmMME1_CTRL_SHADOW_3_TENSOR_L_LOOP_STRIDE_4 0xE0C50
+
+#define mmMME1_CTRL_SHADOW_3_TENSOR_L_ROI_SIZE_0 0xE0C54
+
+#define mmMME1_CTRL_SHADOW_3_TENSOR_L_ROI_SIZE_1 0xE0C58
+
+#define mmMME1_CTRL_SHADOW_3_TENSOR_L_ROI_SIZE_2 0xE0C5C
+
+#define mmMME1_CTRL_SHADOW_3_TENSOR_L_ROI_SIZE_3 0xE0C60
+
+#define mmMME1_CTRL_SHADOW_3_TENSOR_L_SPATIAL_STRIDES_0 0xE0C64
+
+#define mmMME1_CTRL_SHADOW_3_TENSOR_L_SPATIAL_STRIDES_1 0xE0C68
+
+#define mmMME1_CTRL_SHADOW_3_TENSOR_L_SPATIAL_STRIDES_2 0xE0C6C
+
+#define mmMME1_CTRL_SHADOW_3_TENSOR_L_SPATIAL_STRIDES_3 0xE0C70
+
+#define mmMME1_CTRL_SHADOW_3_TENSOR_L_SPATIAL_SIZE_MINUS_1 0xE0C74
+
+#define mmMME1_CTRL_SHADOW_3_AGU_L_LOCAL_ROI_BASE_OFFSET_0 0xE0C78
+
+#define mmMME1_CTRL_SHADOW_3_AGU_L_LOCAL_ROI_BASE_OFFSET_1 0xE0C7C
+
+#define mmMME1_CTRL_SHADOW_3_AGU_L_LOCAL_ROI_BASE_OFFSET_2 0xE0C80
+
+#define mmMME1_CTRL_SHADOW_3_AGU_L_LOCAL_ROI_BASE_OFFSET_3 0xE0C84
+
+#define mmMME1_CTRL_SHADOW_3_AGU_L_LOCAL_ROI_BASE_OFFSET_4 0xE0C88
+
+#define mmMME1_CTRL_SHADOW_3_AGU_L_LOCAL_START_OFFSET_0 0xE0C8C
+
+#define mmMME1_CTRL_SHADOW_3_AGU_L_LOCAL_START_OFFSET_1 0xE0C90
+
+#define mmMME1_CTRL_SHADOW_3_AGU_L_LOCAL_START_OFFSET_2 0xE0C94
+
+#define mmMME1_CTRL_SHADOW_3_AGU_L_LOCAL_START_OFFSET_3 0xE0C98
+
+#define mmMME1_CTRL_SHADOW_3_AGU_L_REMOTE_ROI_BASE_OFFSET_0 0xE0C9C
+
+#define mmMME1_CTRL_SHADOW_3_AGU_L_REMOTE_ROI_BASE_OFFSET_1 0xE0CA0
+
+#define mmMME1_CTRL_SHADOW_3_AGU_L_REMOTE_ROI_BASE_OFFSET_2 0xE0CA4
+
+#define mmMME1_CTRL_SHADOW_3_AGU_L_REMOTE_ROI_BASE_OFFSET_3 0xE0CA8
+
+#define mmMME1_CTRL_SHADOW_3_AGU_L_REMOTE_ROI_BASE_OFFSET_4 0xE0CAC
+
+#define mmMME1_CTRL_SHADOW_3_AGU_L_REMOTE_START_OFFSET_0 0xE0CB0
+
+#define mmMME1_CTRL_SHADOW_3_AGU_L_REMOTE_START_OFFSET_1 0xE0CB4
+
+#define mmMME1_CTRL_SHADOW_3_AGU_L_REMOTE_START_OFFSET_2 0xE0CB8
+
+#define mmMME1_CTRL_SHADOW_3_AGU_L_REMOTE_START_OFFSET_3 0xE0CBC
+
+#define mmMME1_CTRL_SHADOW_3_TENSOR_O_VALID_ELEMENTS_0 0xE0CC0
+
+#define mmMME1_CTRL_SHADOW_3_TENSOR_O_VALID_ELEMENTS_1 0xE0CC4
+
+#define mmMME1_CTRL_SHADOW_3_TENSOR_O_VALID_ELEMENTS_2 0xE0CC8
+
+#define mmMME1_CTRL_SHADOW_3_TENSOR_O_VALID_ELEMENTS_3 0xE0CCC
+
+#define mmMME1_CTRL_SHADOW_3_TENSOR_O_VALID_ELEMENTS_4 0xE0CD0
+
+#define mmMME1_CTRL_SHADOW_3_TENSOR_O_LOOP_STRIDE_0 0xE0CD4
+
+#define mmMME1_CTRL_SHADOW_3_TENSOR_O_LOOP_STRIDE_1 0xE0CD8
+
+#define mmMME1_CTRL_SHADOW_3_TENSOR_O_LOOP_STRIDE_2 0xE0CDC
+
+#define mmMME1_CTRL_SHADOW_3_TENSOR_O_LOOP_STRIDE_3 0xE0CE0
+
+#define mmMME1_CTRL_SHADOW_3_TENSOR_O_LOOP_STRIDE_4 0xE0CE4
+
+#define mmMME1_CTRL_SHADOW_3_TENSOR_O_ROI_SIZE_0 0xE0CE8
+
+#define mmMME1_CTRL_SHADOW_3_TENSOR_O_ROI_SIZE_1 0xE0CEC
+
+#define mmMME1_CTRL_SHADOW_3_TENSOR_O_ROI_SIZE_2 0xE0CF0
+
+#define mmMME1_CTRL_SHADOW_3_TENSOR_O_ROI_SIZE_3 0xE0CF4
+
+#define mmMME1_CTRL_SHADOW_3_TENSOR_O_SPATIAL_STRIDES_0 0xE0CF8
+
+#define mmMME1_CTRL_SHADOW_3_TENSOR_O_SPATIAL_STRIDES_1 0xE0CFC
+
+#define mmMME1_CTRL_SHADOW_3_TENSOR_O_SPATIAL_STRIDES_2 0xE0D00
+
+#define mmMME1_CTRL_SHADOW_3_TENSOR_O_SPATIAL_STRIDES_3 0xE0D04
+
+#define mmMME1_CTRL_SHADOW_3_TENSOR_O_SPATIAL_SIZE_MINUS_1 0xE0D08
+
+#define mmMME1_CTRL_SHADOW_3_AGU_O_LOCAL_ROI_BASE_OFFSET_0 0xE0D0C
+
+#define mmMME1_CTRL_SHADOW_3_AGU_O_LOCAL_ROI_BASE_OFFSET_1 0xE0D10
+
+#define mmMME1_CTRL_SHADOW_3_AGU_O_LOCAL_ROI_BASE_OFFSET_2 0xE0D14
+
+#define mmMME1_CTRL_SHADOW_3_AGU_O_LOCAL_ROI_BASE_OFFSET_3 0xE0D18
+
+#define mmMME1_CTRL_SHADOW_3_AGU_O_LOCAL_ROI_BASE_OFFSET_4 0xE0D1C
+
+#define mmMME1_CTRL_SHADOW_3_AGU_O_LOCAL_START_OFFSET_0 0xE0D20
+
+#define mmMME1_CTRL_SHADOW_3_AGU_O_LOCAL_START_OFFSET_1 0xE0D24
+
+#define mmMME1_CTRL_SHADOW_3_AGU_O_LOCAL_START_OFFSET_2 0xE0D28
+
+#define mmMME1_CTRL_SHADOW_3_AGU_O_LOCAL_START_OFFSET_3 0xE0D2C
+
+#define mmMME1_CTRL_SHADOW_3_AGU_O_REMOTE_ROI_BASE_OFFSET_0 0xE0D30
+
+#define mmMME1_CTRL_SHADOW_3_AGU_O_REMOTE_ROI_BASE_OFFSET_1 0xE0D34
+
+#define mmMME1_CTRL_SHADOW_3_AGU_O_REMOTE_ROI_BASE_OFFSET_2 0xE0D38
+
+#define mmMME1_CTRL_SHADOW_3_AGU_O_REMOTE_ROI_BASE_OFFSET_3 0xE0D3C
+
+#define mmMME1_CTRL_SHADOW_3_AGU_O_REMOTE_ROI_BASE_OFFSET_4 0xE0D40
+
+#define mmMME1_CTRL_SHADOW_3_AGU_O_REMOTE_START_OFFSET_0 0xE0D44
+
+#define mmMME1_CTRL_SHADOW_3_AGU_O_REMOTE_START_OFFSET_1 0xE0D48
+
+#define mmMME1_CTRL_SHADOW_3_AGU_O_REMOTE_START_OFFSET_2 0xE0D4C
+
+#define mmMME1_CTRL_SHADOW_3_AGU_O_REMOTE_START_OFFSET_3 0xE0D50
+
+#define mmMME1_CTRL_SHADOW_3_DESC_SB_REPEAT 0xE0D54
+
+#define mmMME1_CTRL_SHADOW_3_DESC_RATE_LIMITER 0xE0D58
+
+#define mmMME1_CTRL_SHADOW_3_DESC_SYNC_OBJECT_ADDR_LOW_LOCAL 0xE0D5C
+
+#define mmMME1_CTRL_SHADOW_3_DESC_SYNC_OBJECT_ADDR_LOW_REMOTE 0xE0D60
+
+#define mmMME1_CTRL_SHADOW_3_DESC_SYNC_OBJECT_ADDR_HIGH 0xE0D64
+
+#define mmMME1_CTRL_SHADOW_3_DESC_SYNC_OBJECT_DATA 0xE0D68
+
+#define mmMME1_CTRL_SHADOW_3_DESC_AXI_USER_DATA 0xE0D6C
+
+#define mmMME1_CTRL_SHADOW_3_DESC_PERF_EVT_S 0xE0D70
+
+#define mmMME1_CTRL_SHADOW_3_DESC_PERF_EVT_L_LOCAL 0xE0D74
+
+#define mmMME1_CTRL_SHADOW_3_DESC_PERF_EVT_L_REMOTE 0xE0D78
+
+#define mmMME1_CTRL_SHADOW_3_DESC_PERF_EVT_O_LOCAL 0xE0D7C
+
+#define mmMME1_CTRL_SHADOW_3_DESC_PERF_EVT_O_REMOTE 0xE0D80
+
+#define mmMME1_CTRL_SHADOW_3_DESC_PADDING_VALUE_S 0xE0D84
+
+#define mmMME1_CTRL_SHADOW_3_DESC_PADDING_VALUE_L 0xE0D88
+
+#define mmMME1_CTRL_SHADOW_3_DESC_META_DATA_AGU_S 0xE0D8C
+
+#define mmMME1_CTRL_SHADOW_3_DESC_META_DATA_AGU_L_LOCAL 0xE0D90
+
+#define mmMME1_CTRL_SHADOW_3_DESC_META_DATA_AGU_L_REMOTE 0xE0D94
+
+#define mmMME1_CTRL_SHADOW_3_DESC_META_DATA_AGU_O_LOCAL 0xE0D98
+
+#define mmMME1_CTRL_SHADOW_3_DESC_META_DATA_AGU_O_REMOTE 0xE0D9C
+
+#define mmMME1_CTRL_SHADOW_3_DESC_PCU_RL_SATURATION 0xE0DA0
+
+#define mmMME1_CTRL_SHADOW_3_DESC_DUMMY 0xE0DA4
+
+#endif /* ASIC_REG_MME1_CTRL_REGS_H_ */
diff --git a/drivers/accel/habanalabs/include/gaudi/asic_reg/mme2_ctrl_regs.h b/drivers/accel/habanalabs/include/gaudi/asic_reg/mme2_ctrl_regs.h
new file mode 100644
index 0000000000..a1f2eb8b91
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi/asic_reg/mme2_ctrl_regs.h
@@ -0,0 +1,1456 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2016-2018 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ ** DO NOT EDIT BELOW **
+ ************************************/
+
+#ifndef ASIC_REG_MME2_CTRL_REGS_H_
+#define ASIC_REG_MME2_CTRL_REGS_H_
+
+/*
+ *****************************************
+ * MME2_CTRL (Prototype: MME)
+ *****************************************
+ */
+
+#define mmMME2_CTRL_ARCH_STATUS 0x160000
+
+#define mmMME2_CTRL_ARCH_BASE_ADDR_HIGH_S 0x160008
+
+#define mmMME2_CTRL_ARCH_BASE_ADDR_HIGH_L 0x16000C
+
+#define mmMME2_CTRL_ARCH_BASE_ADDR_HIGH_O 0x160010
+
+#define mmMME2_CTRL_ARCH_BASE_ADDR_LOW_S 0x160014
+
+#define mmMME2_CTRL_ARCH_BASE_ADDR_LOW_L 0x160018
+
+#define mmMME2_CTRL_ARCH_BASE_ADDR_LOW_O 0x16001C
+
+#define mmMME2_CTRL_ARCH_HEADER_LOW 0x160020
+
+#define mmMME2_CTRL_ARCH_HEADER_HIGH 0x160024
+
+#define mmMME2_CTRL_ARCH_CONV_KERNEL_SIZE_MINUS_1 0x160028
+
+#define mmMME2_CTRL_ARCH_CONV_ASSOCIATED_DIMS_LOW 0x16002C
+
+#define mmMME2_CTRL_ARCH_CONV_ASSOCIATED_DIMS_HIGH 0x160030
+
+#define mmMME2_CTRL_ARCH_NUM_ITERATIONS_MINUS_1 0x160034
+
+#define mmMME2_CTRL_ARCH_OUTER_LOOP 0x160038
+
+#define mmMME2_CTRL_ARCH_TENSOR_S_VALID_ELEMENTS_0 0x16003C
+
+#define mmMME2_CTRL_ARCH_TENSOR_S_VALID_ELEMENTS_1 0x160040
+
+#define mmMME2_CTRL_ARCH_TENSOR_S_VALID_ELEMENTS_2 0x160044
+
+#define mmMME2_CTRL_ARCH_TENSOR_S_VALID_ELEMENTS_3 0x160048
+
+#define mmMME2_CTRL_ARCH_TENSOR_S_VALID_ELEMENTS_4 0x16004C
+
+#define mmMME2_CTRL_ARCH_TENSOR_S_LOOP_STRIDE_0 0x160050
+
+#define mmMME2_CTRL_ARCH_TENSOR_S_LOOP_STRIDE_1 0x160054
+
+#define mmMME2_CTRL_ARCH_TENSOR_S_LOOP_STRIDE_2 0x160058
+
+#define mmMME2_CTRL_ARCH_TENSOR_S_LOOP_STRIDE_3 0x16005C
+
+#define mmMME2_CTRL_ARCH_TENSOR_S_LOOP_STRIDE_4 0x160060
+
+#define mmMME2_CTRL_ARCH_TENSOR_S_ROI_SIZE_0 0x160064
+
+#define mmMME2_CTRL_ARCH_TENSOR_S_ROI_SIZE_1 0x160068
+
+#define mmMME2_CTRL_ARCH_TENSOR_S_ROI_SIZE_2 0x16006C
+
+#define mmMME2_CTRL_ARCH_TENSOR_S_ROI_SIZE_3 0x160070
+
+#define mmMME2_CTRL_ARCH_TENSOR_S_SPATIAL_STRIDES_0 0x160074
+
+#define mmMME2_CTRL_ARCH_TENSOR_S_SPATIAL_STRIDES_1 0x160078
+
+#define mmMME2_CTRL_ARCH_TENSOR_S_SPATIAL_STRIDES_2 0x16007C
+
+#define mmMME2_CTRL_ARCH_TENSOR_S_SPATIAL_STRIDES_3 0x160080
+
+#define mmMME2_CTRL_ARCH_TENSOR_S_SPATIAL_SIZE_MINUS_1 0x160084
+
+#define mmMME2_CTRL_ARCH_AGU_S_ROI_BASE_OFFSET_0 0x160088
+
+#define mmMME2_CTRL_ARCH_AGU_S_ROI_BASE_OFFSET_1 0x16008C
+
+#define mmMME2_CTRL_ARCH_AGU_S_ROI_BASE_OFFSET_2 0x160090
+
+#define mmMME2_CTRL_ARCH_AGU_S_ROI_BASE_OFFSET_3 0x160094
+
+#define mmMME2_CTRL_ARCH_AGU_S_ROI_BASE_OFFSET_4 0x160098
+
+#define mmMME2_CTRL_ARCH_AGU_S_START_OFFSET_0 0x16009C
+
+#define mmMME2_CTRL_ARCH_AGU_S_START_OFFSET_1 0x1600A0
+
+#define mmMME2_CTRL_ARCH_AGU_S_START_OFFSET_2 0x1600A4
+
+#define mmMME2_CTRL_ARCH_AGU_S_START_OFFSET_3 0x1600A8
+
+#define mmMME2_CTRL_ARCH_TENSOR_L_VALID_ELEMENTS_0 0x1600AC
+
+#define mmMME2_CTRL_ARCH_TENSOR_L_VALID_ELEMENTS_1 0x1600B0
+
+#define mmMME2_CTRL_ARCH_TENSOR_L_VALID_ELEMENTS_2 0x1600B4
+
+#define mmMME2_CTRL_ARCH_TENSOR_L_VALID_ELEMENTS_3 0x1600B8
+
+#define mmMME2_CTRL_ARCH_TENSOR_L_VALID_ELEMENTS_4 0x1600BC
+
+#define mmMME2_CTRL_ARCH_TENSOR_L_LOOP_STRIDE_0 0x1600C0
+
+#define mmMME2_CTRL_ARCH_TENSOR_L_LOOP_STRIDE_1 0x1600C4
+
+#define mmMME2_CTRL_ARCH_TENSOR_L_LOOP_STRIDE_2 0x1600C8
+
+#define mmMME2_CTRL_ARCH_TENSOR_L_LOOP_STRIDE_3 0x1600CC
+
+#define mmMME2_CTRL_ARCH_TENSOR_L_LOOP_STRIDE_4 0x1600D0
+
+#define mmMME2_CTRL_ARCH_TENSOR_L_ROI_SIZE_0 0x1600D4
+
+#define mmMME2_CTRL_ARCH_TENSOR_L_ROI_SIZE_1 0x1600D8
+
+#define mmMME2_CTRL_ARCH_TENSOR_L_ROI_SIZE_2 0x1600DC
+
+#define mmMME2_CTRL_ARCH_TENSOR_L_ROI_SIZE_3 0x1600E0
+
+#define mmMME2_CTRL_ARCH_TENSOR_L_SPATIAL_STRIDES_0 0x1600E4
+
+#define mmMME2_CTRL_ARCH_TENSOR_L_SPATIAL_STRIDES_1 0x1600E8
+
+#define mmMME2_CTRL_ARCH_TENSOR_L_SPATIAL_STRIDES_2 0x1600EC
+
+#define mmMME2_CTRL_ARCH_TENSOR_L_SPATIAL_STRIDES_3 0x1600F0
+
+#define mmMME2_CTRL_ARCH_TENSOR_L_SPATIAL_SIZE_MINUS_1 0x1600F4
+
+#define mmMME2_CTRL_ARCH_AGU_L_LOCAL_ROI_BASE_OFFSET_0 0x1600F8
+
+#define mmMME2_CTRL_ARCH_AGU_L_LOCAL_ROI_BASE_OFFSET_1 0x1600FC
+
+#define mmMME2_CTRL_ARCH_AGU_L_LOCAL_ROI_BASE_OFFSET_2 0x160100
+
+#define mmMME2_CTRL_ARCH_AGU_L_LOCAL_ROI_BASE_OFFSET_3 0x160104
+
+#define mmMME2_CTRL_ARCH_AGU_L_LOCAL_ROI_BASE_OFFSET_4 0x160108
+
+#define mmMME2_CTRL_ARCH_AGU_L_LOCAL_START_OFFSET_0 0x16010C
+
+#define mmMME2_CTRL_ARCH_AGU_L_LOCAL_START_OFFSET_1 0x160110
+
+#define mmMME2_CTRL_ARCH_AGU_L_LOCAL_START_OFFSET_2 0x160114
+
+#define mmMME2_CTRL_ARCH_AGU_L_LOCAL_START_OFFSET_3 0x160118
+
+#define mmMME2_CTRL_ARCH_AGU_L_REMOTE_ROI_BASE_OFFSET_0 0x16011C
+
+#define mmMME2_CTRL_ARCH_AGU_L_REMOTE_ROI_BASE_OFFSET_1 0x160120
+
+#define mmMME2_CTRL_ARCH_AGU_L_REMOTE_ROI_BASE_OFFSET_2 0x160124
+
+#define mmMME2_CTRL_ARCH_AGU_L_REMOTE_ROI_BASE_OFFSET_3 0x160128
+
+#define mmMME2_CTRL_ARCH_AGU_L_REMOTE_ROI_BASE_OFFSET_4 0x16012C
+
+#define mmMME2_CTRL_ARCH_AGU_L_REMOTE_START_OFFSET_0 0x160130
+
+#define mmMME2_CTRL_ARCH_AGU_L_REMOTE_START_OFFSET_1 0x160134
+
+#define mmMME2_CTRL_ARCH_AGU_L_REMOTE_START_OFFSET_2 0x160138
+
+#define mmMME2_CTRL_ARCH_AGU_L_REMOTE_START_OFFSET_3 0x16013C
+
+#define mmMME2_CTRL_ARCH_TENSOR_O_VALID_ELEMENTS_0 0x160140
+
+#define mmMME2_CTRL_ARCH_TENSOR_O_VALID_ELEMENTS_1 0x160144
+
+#define mmMME2_CTRL_ARCH_TENSOR_O_VALID_ELEMENTS_2 0x160148
+
+#define mmMME2_CTRL_ARCH_TENSOR_O_VALID_ELEMENTS_3 0x16014C
+
+#define mmMME2_CTRL_ARCH_TENSOR_O_VALID_ELEMENTS_4 0x160150
+
+#define mmMME2_CTRL_ARCH_TENSOR_O_LOOP_STRIDE_0 0x160154
+
+#define mmMME2_CTRL_ARCH_TENSOR_O_LOOP_STRIDE_1 0x160158
+
+#define mmMME2_CTRL_ARCH_TENSOR_O_LOOP_STRIDE_2 0x16015C
+
+#define mmMME2_CTRL_ARCH_TENSOR_O_LOOP_STRIDE_3 0x160160
+
+#define mmMME2_CTRL_ARCH_TENSOR_O_LOOP_STRIDE_4 0x160164
+
+#define mmMME2_CTRL_ARCH_TENSOR_O_ROI_SIZE_0 0x160168
+
+#define mmMME2_CTRL_ARCH_TENSOR_O_ROI_SIZE_1 0x16016C
+
+#define mmMME2_CTRL_ARCH_TENSOR_O_ROI_SIZE_2 0x160170
+
+#define mmMME2_CTRL_ARCH_TENSOR_O_ROI_SIZE_3 0x160174
+
+#define mmMME2_CTRL_ARCH_TENSOR_O_SPATIAL_STRIDES_0 0x160178
+
+#define mmMME2_CTRL_ARCH_TENSOR_O_SPATIAL_STRIDES_1 0x16017C
+
+#define mmMME2_CTRL_ARCH_TENSOR_O_SPATIAL_STRIDES_2 0x160180
+
+#define mmMME2_CTRL_ARCH_TENSOR_O_SPATIAL_STRIDES_3 0x160184
+
+#define mmMME2_CTRL_ARCH_TENSOR_O_SPATIAL_SIZE_MINUS_1 0x160188
+
+#define mmMME2_CTRL_ARCH_AGU_O_LOCAL_ROI_BASE_OFFSET_0 0x16018C
+
+#define mmMME2_CTRL_ARCH_AGU_O_LOCAL_ROI_BASE_OFFSET_1 0x160190
+
+#define mmMME2_CTRL_ARCH_AGU_O_LOCAL_ROI_BASE_OFFSET_2 0x160194
+
+#define mmMME2_CTRL_ARCH_AGU_O_LOCAL_ROI_BASE_OFFSET_3 0x160198
+
+#define mmMME2_CTRL_ARCH_AGU_O_LOCAL_ROI_BASE_OFFSET_4 0x16019C
+
+#define mmMME2_CTRL_ARCH_AGU_O_LOCAL_START_OFFSET_0 0x1601A0
+
+#define mmMME2_CTRL_ARCH_AGU_O_LOCAL_START_OFFSET_1 0x1601A4
+
+#define mmMME2_CTRL_ARCH_AGU_O_LOCAL_START_OFFSET_2 0x1601A8
+
+#define mmMME2_CTRL_ARCH_AGU_O_LOCAL_START_OFFSET_3 0x1601AC
+
+#define mmMME2_CTRL_ARCH_AGU_O_REMOTE_ROI_BASE_OFFSET_0 0x1601B0
+
+#define mmMME2_CTRL_ARCH_AGU_O_REMOTE_ROI_BASE_OFFSET_1 0x1601B4
+
+#define mmMME2_CTRL_ARCH_AGU_O_REMOTE_ROI_BASE_OFFSET_2 0x1601B8
+
+#define mmMME2_CTRL_ARCH_AGU_O_REMOTE_ROI_BASE_OFFSET_3 0x1601BC
+
+#define mmMME2_CTRL_ARCH_AGU_O_REMOTE_ROI_BASE_OFFSET_4 0x1601C0
+
+#define mmMME2_CTRL_ARCH_AGU_O_REMOTE_START_OFFSET_0 0x1601C4
+
+#define mmMME2_CTRL_ARCH_AGU_O_REMOTE_START_OFFSET_1 0x1601C8
+
+#define mmMME2_CTRL_ARCH_AGU_O_REMOTE_START_OFFSET_2 0x1601CC
+
+#define mmMME2_CTRL_ARCH_AGU_O_REMOTE_START_OFFSET_3 0x1601D0
+
+#define mmMME2_CTRL_ARCH_DESC_SB_REPEAT 0x1601D4
+
+#define mmMME2_CTRL_ARCH_DESC_RATE_LIMITER 0x1601D8
+
+#define mmMME2_CTRL_ARCH_DESC_SYNC_OBJECT_ADDR_LOW_LOCAL 0x1601DC
+
+#define mmMME2_CTRL_ARCH_DESC_SYNC_OBJECT_ADDR_LOW_REMOTE 0x1601E0
+
+#define mmMME2_CTRL_ARCH_DESC_SYNC_OBJECT_ADDR_HIGH 0x1601E4
+
+#define mmMME2_CTRL_ARCH_DESC_SYNC_OBJECT_DATA 0x1601E8
+
+#define mmMME2_CTRL_ARCH_DESC_AXI_USER_DATA 0x1601EC
+
+#define mmMME2_CTRL_ARCH_DESC_PERF_EVT_S 0x1601F0
+
+#define mmMME2_CTRL_ARCH_DESC_PERF_EVT_L_LOCAL 0x1601F4
+
+#define mmMME2_CTRL_ARCH_DESC_PERF_EVT_L_REMOTE 0x1601F8
+
+#define mmMME2_CTRL_ARCH_DESC_PERF_EVT_O_LOCAL 0x1601FC
+
+#define mmMME2_CTRL_ARCH_DESC_PERF_EVT_O_REMOTE 0x160200
+
+#define mmMME2_CTRL_ARCH_DESC_PADDING_VALUE_S 0x160204
+
+#define mmMME2_CTRL_ARCH_DESC_PADDING_VALUE_L 0x160208
+
+#define mmMME2_CTRL_ARCH_DESC_META_DATA_AGU_S 0x16020C
+
+#define mmMME2_CTRL_ARCH_DESC_META_DATA_AGU_L_LOCAL 0x160210
+
+#define mmMME2_CTRL_ARCH_DESC_META_DATA_AGU_L_REMOTE 0x160214
+
+#define mmMME2_CTRL_ARCH_DESC_META_DATA_AGU_O_LOCAL 0x160218
+
+#define mmMME2_CTRL_ARCH_DESC_META_DATA_AGU_O_REMOTE 0x16021C
+
+#define mmMME2_CTRL_ARCH_DESC_PCU_RL_SATURATION 0x160220
+
+#define mmMME2_CTRL_ARCH_DESC_DUMMY 0x160224
+
+#define mmMME2_CTRL_CMD 0x160280
+
+#define mmMME2_CTRL_STATUS1 0x160284
+
+#define mmMME2_CTRL_RESET 0x160288
+
+#define mmMME2_CTRL_QM_STALL 0x16028C
+
+#define mmMME2_CTRL_SYNC_OBJECT_FIFO_TH 0x160290
+
+#define mmMME2_CTRL_EUS_ROLLUP_CNT_ADD 0x160294
+
+#define mmMME2_CTRL_INTR_CAUSE 0x160298
+
+#define mmMME2_CTRL_INTR_MASK 0x16029C
+
+#define mmMME2_CTRL_LOG_SHADOW 0x1602A0
+
+#define mmMME2_CTRL_PCU_RL_DESC0 0x1602A4
+
+#define mmMME2_CTRL_PCU_RL_TOKEN_UPDATE 0x1602A8
+
+#define mmMME2_CTRL_PCU_RL_TH 0x1602AC
+
+#define mmMME2_CTRL_PCU_RL_MIN 0x1602B0
+
+#define mmMME2_CTRL_PCU_RL_CTRL_EN 0x1602B4
+
+#define mmMME2_CTRL_PCU_RL_HISTORY_LOG_SIZE 0x1602B8
+
+#define mmMME2_CTRL_PCU_DUMMY_A_BF16 0x1602BC
+
+#define mmMME2_CTRL_PCU_DUMMY_B_BF16 0x1602C0
+
+#define mmMME2_CTRL_PCU_DUMMY_A_FP32_ODD 0x1602C4
+
+#define mmMME2_CTRL_PCU_DUMMY_A_FP32_EVEN 0x1602C8
+
+#define mmMME2_CTRL_PCU_DUMMY_B_FP32_ODD 0x1602CC
+
+#define mmMME2_CTRL_PCU_DUMMY_B_FP32_EVEN 0x1602D0
+
+#define mmMME2_CTRL_PROT 0x1602D4
+
+#define mmMME2_CTRL_EU_POWER_SAVE_DISABLE 0x1602D8
+
+#define mmMME2_CTRL_CS_DBG_BLOCK_ID 0x1602DC
+
+#define mmMME2_CTRL_CS_DBG_STATUS_DROP_CNT 0x1602E0
+
+#define mmMME2_CTRL_TE_CLOSE_CGATE 0x1602E4
+
+#define mmMME2_CTRL_AGU_SM_INFLIGHT_CNTR 0x1602E8
+
+#define mmMME2_CTRL_AGU_SM_TOTAL_CNTR 0x1602EC
+
+#define mmMME2_CTRL_EZSYNC_OUT_CREDIT 0x1602F0
+
+#define mmMME2_CTRL_PCU_RL_SAT_SEC 0x1602F4
+
+#define mmMME2_CTRL_AGU_SYNC_MSG_AXI_USER 0x1602F8
+
+#define mmMME2_CTRL_QM_SLV_LBW_CLK_EN 0x1602FC
+
+#define mmMME2_CTRL_SHADOW_0_STATUS 0x160400
+
+#define mmMME2_CTRL_SHADOW_0_BASE_ADDR_HIGH_S 0x160408
+
+#define mmMME2_CTRL_SHADOW_0_BASE_ADDR_HIGH_L 0x16040C
+
+#define mmMME2_CTRL_SHADOW_0_BASE_ADDR_HIGH_O 0x160410
+
+#define mmMME2_CTRL_SHADOW_0_BASE_ADDR_LOW_S 0x160414
+
+#define mmMME2_CTRL_SHADOW_0_BASE_ADDR_LOW_L 0x160418
+
+#define mmMME2_CTRL_SHADOW_0_BASE_ADDR_LOW_O 0x16041C
+
+#define mmMME2_CTRL_SHADOW_0_HEADER_LOW 0x160420
+
+#define mmMME2_CTRL_SHADOW_0_HEADER_HIGH 0x160424
+
+#define mmMME2_CTRL_SHADOW_0_CONV_KERNEL_SIZE_MINUS_1 0x160428
+
+#define mmMME2_CTRL_SHADOW_0_CONV_ASSOCIATED_DIMS_LOW 0x16042C
+
+#define mmMME2_CTRL_SHADOW_0_CONV_ASSOCIATED_DIMS_HIGH 0x160430
+
+#define mmMME2_CTRL_SHADOW_0_NUM_ITERATIONS_MINUS_1 0x160434
+
+#define mmMME2_CTRL_SHADOW_0_OUTER_LOOP 0x160438
+
+#define mmMME2_CTRL_SHADOW_0_TENSOR_S_VALID_ELEMENTS_0 0x16043C
+
+#define mmMME2_CTRL_SHADOW_0_TENSOR_S_VALID_ELEMENTS_1 0x160440
+
+#define mmMME2_CTRL_SHADOW_0_TENSOR_S_VALID_ELEMENTS_2 0x160444
+
+#define mmMME2_CTRL_SHADOW_0_TENSOR_S_VALID_ELEMENTS_3 0x160448
+
+#define mmMME2_CTRL_SHADOW_0_TENSOR_S_VALID_ELEMENTS_4 0x16044C
+
+#define mmMME2_CTRL_SHADOW_0_TENSOR_S_LOOP_STRIDE_0 0x160450
+
+#define mmMME2_CTRL_SHADOW_0_TENSOR_S_LOOP_STRIDE_1 0x160454
+
+#define mmMME2_CTRL_SHADOW_0_TENSOR_S_LOOP_STRIDE_2 0x160458
+
+#define mmMME2_CTRL_SHADOW_0_TENSOR_S_LOOP_STRIDE_3 0x16045C
+
+#define mmMME2_CTRL_SHADOW_0_TENSOR_S_LOOP_STRIDE_4 0x160460
+
+#define mmMME2_CTRL_SHADOW_0_TENSOR_S_ROI_SIZE_0 0x160464
+
+#define mmMME2_CTRL_SHADOW_0_TENSOR_S_ROI_SIZE_1 0x160468
+
+#define mmMME2_CTRL_SHADOW_0_TENSOR_S_ROI_SIZE_2 0x16046C
+
+#define mmMME2_CTRL_SHADOW_0_TENSOR_S_ROI_SIZE_3 0x160470
+
+#define mmMME2_CTRL_SHADOW_0_TENSOR_S_SPATIAL_STRIDES_0 0x160474
+
+#define mmMME2_CTRL_SHADOW_0_TENSOR_S_SPATIAL_STRIDES_1 0x160478
+
+#define mmMME2_CTRL_SHADOW_0_TENSOR_S_SPATIAL_STRIDES_2 0x16047C
+
+#define mmMME2_CTRL_SHADOW_0_TENSOR_S_SPATIAL_STRIDES_3 0x160480
+
+#define mmMME2_CTRL_SHADOW_0_TENSOR_S_SPATIAL_SIZE_MINUS_1 0x160484
+
+#define mmMME2_CTRL_SHADOW_0_AGU_S_ROI_BASE_OFFSET_0 0x160488
+
+#define mmMME2_CTRL_SHADOW_0_AGU_S_ROI_BASE_OFFSET_1 0x16048C
+
+#define mmMME2_CTRL_SHADOW_0_AGU_S_ROI_BASE_OFFSET_2 0x160490
+
+#define mmMME2_CTRL_SHADOW_0_AGU_S_ROI_BASE_OFFSET_3 0x160494
+
+#define mmMME2_CTRL_SHADOW_0_AGU_S_ROI_BASE_OFFSET_4 0x160498
+
+#define mmMME2_CTRL_SHADOW_0_AGU_S_START_OFFSET_0 0x16049C
+
+#define mmMME2_CTRL_SHADOW_0_AGU_S_START_OFFSET_1 0x1604A0
+
+#define mmMME2_CTRL_SHADOW_0_AGU_S_START_OFFSET_2 0x1604A4
+
+#define mmMME2_CTRL_SHADOW_0_AGU_S_START_OFFSET_3 0x1604A8
+
+#define mmMME2_CTRL_SHADOW_0_TENSOR_L_VALID_ELEMENTS_0 0x1604AC
+
+#define mmMME2_CTRL_SHADOW_0_TENSOR_L_VALID_ELEMENTS_1 0x1604B0
+
+#define mmMME2_CTRL_SHADOW_0_TENSOR_L_VALID_ELEMENTS_2 0x1604B4
+
+#define mmMME2_CTRL_SHADOW_0_TENSOR_L_VALID_ELEMENTS_3 0x1604B8
+
+#define mmMME2_CTRL_SHADOW_0_TENSOR_L_VALID_ELEMENTS_4 0x1604BC
+
+#define mmMME2_CTRL_SHADOW_0_TENSOR_L_LOOP_STRIDE_0 0x1604C0
+
+#define mmMME2_CTRL_SHADOW_0_TENSOR_L_LOOP_STRIDE_1 0x1604C4
+
+#define mmMME2_CTRL_SHADOW_0_TENSOR_L_LOOP_STRIDE_2 0x1604C8
+
+#define mmMME2_CTRL_SHADOW_0_TENSOR_L_LOOP_STRIDE_3 0x1604CC
+
+#define mmMME2_CTRL_SHADOW_0_TENSOR_L_LOOP_STRIDE_4 0x1604D0
+
+#define mmMME2_CTRL_SHADOW_0_TENSOR_L_ROI_SIZE_0 0x1604D4
+
+#define mmMME2_CTRL_SHADOW_0_TENSOR_L_ROI_SIZE_1 0x1604D8
+
+#define mmMME2_CTRL_SHADOW_0_TENSOR_L_ROI_SIZE_2 0x1604DC
+
+#define mmMME2_CTRL_SHADOW_0_TENSOR_L_ROI_SIZE_3 0x1604E0
+
+#define mmMME2_CTRL_SHADOW_0_TENSOR_L_SPATIAL_STRIDES_0 0x1604E4
+
+#define mmMME2_CTRL_SHADOW_0_TENSOR_L_SPATIAL_STRIDES_1 0x1604E8
+
+#define mmMME2_CTRL_SHADOW_0_TENSOR_L_SPATIAL_STRIDES_2 0x1604EC
+
+#define mmMME2_CTRL_SHADOW_0_TENSOR_L_SPATIAL_STRIDES_3 0x1604F0
+
+#define mmMME2_CTRL_SHADOW_0_TENSOR_L_SPATIAL_SIZE_MINUS_1 0x1604F4
+
+#define mmMME2_CTRL_SHADOW_0_AGU_L_LOCAL_ROI_BASE_OFFSET_0 0x1604F8
+
+#define mmMME2_CTRL_SHADOW_0_AGU_L_LOCAL_ROI_BASE_OFFSET_1 0x1604FC
+
+#define mmMME2_CTRL_SHADOW_0_AGU_L_LOCAL_ROI_BASE_OFFSET_2 0x160500
+
+#define mmMME2_CTRL_SHADOW_0_AGU_L_LOCAL_ROI_BASE_OFFSET_3 0x160504
+
+#define mmMME2_CTRL_SHADOW_0_AGU_L_LOCAL_ROI_BASE_OFFSET_4 0x160508
+
+#define mmMME2_CTRL_SHADOW_0_AGU_L_LOCAL_START_OFFSET_0 0x16050C
+
+#define mmMME2_CTRL_SHADOW_0_AGU_L_LOCAL_START_OFFSET_1 0x160510
+
+#define mmMME2_CTRL_SHADOW_0_AGU_L_LOCAL_START_OFFSET_2 0x160514
+
+#define mmMME2_CTRL_SHADOW_0_AGU_L_LOCAL_START_OFFSET_3 0x160518
+
+#define mmMME2_CTRL_SHADOW_0_AGU_L_REMOTE_ROI_BASE_OFFSET_0 0x16051C
+
+#define mmMME2_CTRL_SHADOW_0_AGU_L_REMOTE_ROI_BASE_OFFSET_1 0x160520
+
+#define mmMME2_CTRL_SHADOW_0_AGU_L_REMOTE_ROI_BASE_OFFSET_2 0x160524
+
+#define mmMME2_CTRL_SHADOW_0_AGU_L_REMOTE_ROI_BASE_OFFSET_3 0x160528
+
+#define mmMME2_CTRL_SHADOW_0_AGU_L_REMOTE_ROI_BASE_OFFSET_4 0x16052C
+
+#define mmMME2_CTRL_SHADOW_0_AGU_L_REMOTE_START_OFFSET_0 0x160530
+
+#define mmMME2_CTRL_SHADOW_0_AGU_L_REMOTE_START_OFFSET_1 0x160534
+
+#define mmMME2_CTRL_SHADOW_0_AGU_L_REMOTE_START_OFFSET_2 0x160538
+
+#define mmMME2_CTRL_SHADOW_0_AGU_L_REMOTE_START_OFFSET_3 0x16053C
+
+#define mmMME2_CTRL_SHADOW_0_TENSOR_O_VALID_ELEMENTS_0 0x160540
+
+#define mmMME2_CTRL_SHADOW_0_TENSOR_O_VALID_ELEMENTS_1 0x160544
+
+#define mmMME2_CTRL_SHADOW_0_TENSOR_O_VALID_ELEMENTS_2 0x160548
+
+#define mmMME2_CTRL_SHADOW_0_TENSOR_O_VALID_ELEMENTS_3 0x16054C
+
+#define mmMME2_CTRL_SHADOW_0_TENSOR_O_VALID_ELEMENTS_4 0x160550
+
+#define mmMME2_CTRL_SHADOW_0_TENSOR_O_LOOP_STRIDE_0 0x160554
+
+#define mmMME2_CTRL_SHADOW_0_TENSOR_O_LOOP_STRIDE_1 0x160558
+
+#define mmMME2_CTRL_SHADOW_0_TENSOR_O_LOOP_STRIDE_2 0x16055C
+
+#define mmMME2_CTRL_SHADOW_0_TENSOR_O_LOOP_STRIDE_3 0x160560
+
+#define mmMME2_CTRL_SHADOW_0_TENSOR_O_LOOP_STRIDE_4 0x160564
+
+#define mmMME2_CTRL_SHADOW_0_TENSOR_O_ROI_SIZE_0 0x160568
+
+#define mmMME2_CTRL_SHADOW_0_TENSOR_O_ROI_SIZE_1 0x16056C
+
+#define mmMME2_CTRL_SHADOW_0_TENSOR_O_ROI_SIZE_2 0x160570
+
+#define mmMME2_CTRL_SHADOW_0_TENSOR_O_ROI_SIZE_3 0x160574
+
+#define mmMME2_CTRL_SHADOW_0_TENSOR_O_SPATIAL_STRIDES_0 0x160578
+
+#define mmMME2_CTRL_SHADOW_0_TENSOR_O_SPATIAL_STRIDES_1 0x16057C
+
+#define mmMME2_CTRL_SHADOW_0_TENSOR_O_SPATIAL_STRIDES_2 0x160580
+
+#define mmMME2_CTRL_SHADOW_0_TENSOR_O_SPATIAL_STRIDES_3 0x160584
+
+#define mmMME2_CTRL_SHADOW_0_TENSOR_O_SPATIAL_SIZE_MINUS_1 0x160588
+
+#define mmMME2_CTRL_SHADOW_0_AGU_O_LOCAL_ROI_BASE_OFFSET_0 0x16058C
+
+#define mmMME2_CTRL_SHADOW_0_AGU_O_LOCAL_ROI_BASE_OFFSET_1 0x160590
+
+#define mmMME2_CTRL_SHADOW_0_AGU_O_LOCAL_ROI_BASE_OFFSET_2 0x160594
+
+#define mmMME2_CTRL_SHADOW_0_AGU_O_LOCAL_ROI_BASE_OFFSET_3 0x160598
+
+#define mmMME2_CTRL_SHADOW_0_AGU_O_LOCAL_ROI_BASE_OFFSET_4 0x16059C
+
+#define mmMME2_CTRL_SHADOW_0_AGU_O_LOCAL_START_OFFSET_0 0x1605A0
+
+#define mmMME2_CTRL_SHADOW_0_AGU_O_LOCAL_START_OFFSET_1 0x1605A4
+
+#define mmMME2_CTRL_SHADOW_0_AGU_O_LOCAL_START_OFFSET_2 0x1605A8
+
+#define mmMME2_CTRL_SHADOW_0_AGU_O_LOCAL_START_OFFSET_3 0x1605AC
+
+#define mmMME2_CTRL_SHADOW_0_AGU_O_REMOTE_ROI_BASE_OFFSET_0 0x1605B0
+
+#define mmMME2_CTRL_SHADOW_0_AGU_O_REMOTE_ROI_BASE_OFFSET_1 0x1605B4
+
+#define mmMME2_CTRL_SHADOW_0_AGU_O_REMOTE_ROI_BASE_OFFSET_2 0x1605B8
+
+#define mmMME2_CTRL_SHADOW_0_AGU_O_REMOTE_ROI_BASE_OFFSET_3 0x1605BC
+
+#define mmMME2_CTRL_SHADOW_0_AGU_O_REMOTE_ROI_BASE_OFFSET_4 0x1605C0
+
+#define mmMME2_CTRL_SHADOW_0_AGU_O_REMOTE_START_OFFSET_0 0x1605C4
+
+#define mmMME2_CTRL_SHADOW_0_AGU_O_REMOTE_START_OFFSET_1 0x1605C8
+
+#define mmMME2_CTRL_SHADOW_0_AGU_O_REMOTE_START_OFFSET_2 0x1605CC
+
+#define mmMME2_CTRL_SHADOW_0_AGU_O_REMOTE_START_OFFSET_3 0x1605D0
+
+#define mmMME2_CTRL_SHADOW_0_DESC_SB_REPEAT 0x1605D4
+
+#define mmMME2_CTRL_SHADOW_0_DESC_RATE_LIMITER 0x1605D8
+
+#define mmMME2_CTRL_SHADOW_0_DESC_SYNC_OBJECT_ADDR_LOW_LOCAL 0x1605DC
+
+#define mmMME2_CTRL_SHADOW_0_DESC_SYNC_OBJECT_ADDR_LOW_REMOTE 0x1605E0
+
+#define mmMME2_CTRL_SHADOW_0_DESC_SYNC_OBJECT_ADDR_HIGH 0x1605E4
+
+#define mmMME2_CTRL_SHADOW_0_DESC_SYNC_OBJECT_DATA 0x1605E8
+
+#define mmMME2_CTRL_SHADOW_0_DESC_AXI_USER_DATA 0x1605EC
+
+#define mmMME2_CTRL_SHADOW_0_DESC_PERF_EVT_S 0x1605F0
+
+#define mmMME2_CTRL_SHADOW_0_DESC_PERF_EVT_L_LOCAL 0x1605F4
+
+#define mmMME2_CTRL_SHADOW_0_DESC_PERF_EVT_L_REMOTE 0x1605F8
+
+#define mmMME2_CTRL_SHADOW_0_DESC_PERF_EVT_O_LOCAL 0x1605FC
+
+#define mmMME2_CTRL_SHADOW_0_DESC_PERF_EVT_O_REMOTE 0x160600
+
+#define mmMME2_CTRL_SHADOW_0_DESC_PADDING_VALUE_S 0x160604
+
+#define mmMME2_CTRL_SHADOW_0_DESC_PADDING_VALUE_L 0x160608
+
+#define mmMME2_CTRL_SHADOW_0_DESC_META_DATA_AGU_S 0x16060C
+
+#define mmMME2_CTRL_SHADOW_0_DESC_META_DATA_AGU_L_LOCAL 0x160610
+
+#define mmMME2_CTRL_SHADOW_0_DESC_META_DATA_AGU_L_REMOTE 0x160614
+
+#define mmMME2_CTRL_SHADOW_0_DESC_META_DATA_AGU_O_LOCAL 0x160618
+
+#define mmMME2_CTRL_SHADOW_0_DESC_META_DATA_AGU_O_REMOTE 0x16061C
+
+#define mmMME2_CTRL_SHADOW_0_DESC_PCU_RL_SATURATION 0x160620
+
+#define mmMME2_CTRL_SHADOW_0_DESC_DUMMY 0x160624
+
+#define mmMME2_CTRL_SHADOW_1_STATUS 0x160680
+
+#define mmMME2_CTRL_SHADOW_1_BASE_ADDR_HIGH_S 0x160688
+
+#define mmMME2_CTRL_SHADOW_1_BASE_ADDR_HIGH_L 0x16068C
+
+#define mmMME2_CTRL_SHADOW_1_BASE_ADDR_HIGH_O 0x160690
+
+#define mmMME2_CTRL_SHADOW_1_BASE_ADDR_LOW_S 0x160694
+
+#define mmMME2_CTRL_SHADOW_1_BASE_ADDR_LOW_L 0x160698
+
+#define mmMME2_CTRL_SHADOW_1_BASE_ADDR_LOW_O 0x16069C
+
+#define mmMME2_CTRL_SHADOW_1_HEADER_LOW 0x1606A0
+
+#define mmMME2_CTRL_SHADOW_1_HEADER_HIGH 0x1606A4
+
+#define mmMME2_CTRL_SHADOW_1_CONV_KERNEL_SIZE_MINUS_1 0x1606A8
+
+#define mmMME2_CTRL_SHADOW_1_CONV_ASSOCIATED_DIMS_LOW 0x1606AC
+
+#define mmMME2_CTRL_SHADOW_1_CONV_ASSOCIATED_DIMS_HIGH 0x1606B0
+
+#define mmMME2_CTRL_SHADOW_1_NUM_ITERATIONS_MINUS_1 0x1606B4
+
+#define mmMME2_CTRL_SHADOW_1_OUTER_LOOP 0x1606B8
+
+#define mmMME2_CTRL_SHADOW_1_TENSOR_S_VALID_ELEMENTS_0 0x1606BC
+
+#define mmMME2_CTRL_SHADOW_1_TENSOR_S_VALID_ELEMENTS_1 0x1606C0
+
+#define mmMME2_CTRL_SHADOW_1_TENSOR_S_VALID_ELEMENTS_2 0x1606C4
+
+#define mmMME2_CTRL_SHADOW_1_TENSOR_S_VALID_ELEMENTS_3 0x1606C8
+
+#define mmMME2_CTRL_SHADOW_1_TENSOR_S_VALID_ELEMENTS_4 0x1606CC
+
+#define mmMME2_CTRL_SHADOW_1_TENSOR_S_LOOP_STRIDE_0 0x1606D0
+
+#define mmMME2_CTRL_SHADOW_1_TENSOR_S_LOOP_STRIDE_1 0x1606D4
+
+#define mmMME2_CTRL_SHADOW_1_TENSOR_S_LOOP_STRIDE_2 0x1606D8
+
+#define mmMME2_CTRL_SHADOW_1_TENSOR_S_LOOP_STRIDE_3 0x1606DC
+
+#define mmMME2_CTRL_SHADOW_1_TENSOR_S_LOOP_STRIDE_4 0x1606E0
+
+#define mmMME2_CTRL_SHADOW_1_TENSOR_S_ROI_SIZE_0 0x1606E4
+
+#define mmMME2_CTRL_SHADOW_1_TENSOR_S_ROI_SIZE_1 0x1606E8
+
+#define mmMME2_CTRL_SHADOW_1_TENSOR_S_ROI_SIZE_2 0x1606EC
+
+#define mmMME2_CTRL_SHADOW_1_TENSOR_S_ROI_SIZE_3 0x1606F0
+
+#define mmMME2_CTRL_SHADOW_1_TENSOR_S_SPATIAL_STRIDES_0 0x1606F4
+
+#define mmMME2_CTRL_SHADOW_1_TENSOR_S_SPATIAL_STRIDES_1 0x1606F8
+
+#define mmMME2_CTRL_SHADOW_1_TENSOR_S_SPATIAL_STRIDES_2 0x1606FC
+
+#define mmMME2_CTRL_SHADOW_1_TENSOR_S_SPATIAL_STRIDES_3 0x160700
+
+#define mmMME2_CTRL_SHADOW_1_TENSOR_S_SPATIAL_SIZE_MINUS_1 0x160704
+
+#define mmMME2_CTRL_SHADOW_1_AGU_S_ROI_BASE_OFFSET_0 0x160708
+
+#define mmMME2_CTRL_SHADOW_1_AGU_S_ROI_BASE_OFFSET_1 0x16070C
+
+#define mmMME2_CTRL_SHADOW_1_AGU_S_ROI_BASE_OFFSET_2 0x160710
+
+#define mmMME2_CTRL_SHADOW_1_AGU_S_ROI_BASE_OFFSET_3 0x160714
+
+#define mmMME2_CTRL_SHADOW_1_AGU_S_ROI_BASE_OFFSET_4 0x160718
+
+#define mmMME2_CTRL_SHADOW_1_AGU_S_START_OFFSET_0 0x16071C
+
+#define mmMME2_CTRL_SHADOW_1_AGU_S_START_OFFSET_1 0x160720
+
+#define mmMME2_CTRL_SHADOW_1_AGU_S_START_OFFSET_2 0x160724
+
+#define mmMME2_CTRL_SHADOW_1_AGU_S_START_OFFSET_3 0x160728
+
+#define mmMME2_CTRL_SHADOW_1_TENSOR_L_VALID_ELEMENTS_0 0x16072C
+
+#define mmMME2_CTRL_SHADOW_1_TENSOR_L_VALID_ELEMENTS_1 0x160730
+
+#define mmMME2_CTRL_SHADOW_1_TENSOR_L_VALID_ELEMENTS_2 0x160734
+
+#define mmMME2_CTRL_SHADOW_1_TENSOR_L_VALID_ELEMENTS_3 0x160738
+
+#define mmMME2_CTRL_SHADOW_1_TENSOR_L_VALID_ELEMENTS_4 0x16073C
+
+#define mmMME2_CTRL_SHADOW_1_TENSOR_L_LOOP_STRIDE_0 0x160740
+
+#define mmMME2_CTRL_SHADOW_1_TENSOR_L_LOOP_STRIDE_1 0x160744
+
+#define mmMME2_CTRL_SHADOW_1_TENSOR_L_LOOP_STRIDE_2 0x160748
+
+#define mmMME2_CTRL_SHADOW_1_TENSOR_L_LOOP_STRIDE_3 0x16074C
+
+#define mmMME2_CTRL_SHADOW_1_TENSOR_L_LOOP_STRIDE_4 0x160750
+
+#define mmMME2_CTRL_SHADOW_1_TENSOR_L_ROI_SIZE_0 0x160754
+
+#define mmMME2_CTRL_SHADOW_1_TENSOR_L_ROI_SIZE_1 0x160758
+
+#define mmMME2_CTRL_SHADOW_1_TENSOR_L_ROI_SIZE_2 0x16075C
+
+#define mmMME2_CTRL_SHADOW_1_TENSOR_L_ROI_SIZE_3 0x160760
+
+#define mmMME2_CTRL_SHADOW_1_TENSOR_L_SPATIAL_STRIDES_0 0x160764
+
+#define mmMME2_CTRL_SHADOW_1_TENSOR_L_SPATIAL_STRIDES_1 0x160768
+
+#define mmMME2_CTRL_SHADOW_1_TENSOR_L_SPATIAL_STRIDES_2 0x16076C
+
+#define mmMME2_CTRL_SHADOW_1_TENSOR_L_SPATIAL_STRIDES_3 0x160770
+
+#define mmMME2_CTRL_SHADOW_1_TENSOR_L_SPATIAL_SIZE_MINUS_1 0x160774
+
+#define mmMME2_CTRL_SHADOW_1_AGU_L_LOCAL_ROI_BASE_OFFSET_0 0x160778
+
+#define mmMME2_CTRL_SHADOW_1_AGU_L_LOCAL_ROI_BASE_OFFSET_1 0x16077C
+
+#define mmMME2_CTRL_SHADOW_1_AGU_L_LOCAL_ROI_BASE_OFFSET_2 0x160780
+
+#define mmMME2_CTRL_SHADOW_1_AGU_L_LOCAL_ROI_BASE_OFFSET_3 0x160784
+
+#define mmMME2_CTRL_SHADOW_1_AGU_L_LOCAL_ROI_BASE_OFFSET_4 0x160788
+
+#define mmMME2_CTRL_SHADOW_1_AGU_L_LOCAL_START_OFFSET_0 0x16078C
+
+#define mmMME2_CTRL_SHADOW_1_AGU_L_LOCAL_START_OFFSET_1 0x160790
+
+#define mmMME2_CTRL_SHADOW_1_AGU_L_LOCAL_START_OFFSET_2 0x160794
+
+#define mmMME2_CTRL_SHADOW_1_AGU_L_LOCAL_START_OFFSET_3 0x160798
+
+#define mmMME2_CTRL_SHADOW_1_AGU_L_REMOTE_ROI_BASE_OFFSET_0 0x16079C
+
+#define mmMME2_CTRL_SHADOW_1_AGU_L_REMOTE_ROI_BASE_OFFSET_1 0x1607A0
+
+#define mmMME2_CTRL_SHADOW_1_AGU_L_REMOTE_ROI_BASE_OFFSET_2 0x1607A4
+
+#define mmMME2_CTRL_SHADOW_1_AGU_L_REMOTE_ROI_BASE_OFFSET_3 0x1607A8
+
+#define mmMME2_CTRL_SHADOW_1_AGU_L_REMOTE_ROI_BASE_OFFSET_4 0x1607AC
+
+#define mmMME2_CTRL_SHADOW_1_AGU_L_REMOTE_START_OFFSET_0 0x1607B0
+
+#define mmMME2_CTRL_SHADOW_1_AGU_L_REMOTE_START_OFFSET_1 0x1607B4
+
+#define mmMME2_CTRL_SHADOW_1_AGU_L_REMOTE_START_OFFSET_2 0x1607B8
+
+#define mmMME2_CTRL_SHADOW_1_AGU_L_REMOTE_START_OFFSET_3 0x1607BC
+
+#define mmMME2_CTRL_SHADOW_1_TENSOR_O_VALID_ELEMENTS_0 0x1607C0
+
+#define mmMME2_CTRL_SHADOW_1_TENSOR_O_VALID_ELEMENTS_1 0x1607C4
+
+#define mmMME2_CTRL_SHADOW_1_TENSOR_O_VALID_ELEMENTS_2 0x1607C8
+
+#define mmMME2_CTRL_SHADOW_1_TENSOR_O_VALID_ELEMENTS_3 0x1607CC
+
+#define mmMME2_CTRL_SHADOW_1_TENSOR_O_VALID_ELEMENTS_4 0x1607D0
+
+#define mmMME2_CTRL_SHADOW_1_TENSOR_O_LOOP_STRIDE_0 0x1607D4
+
+#define mmMME2_CTRL_SHADOW_1_TENSOR_O_LOOP_STRIDE_1 0x1607D8
+
+#define mmMME2_CTRL_SHADOW_1_TENSOR_O_LOOP_STRIDE_2 0x1607DC
+
+#define mmMME2_CTRL_SHADOW_1_TENSOR_O_LOOP_STRIDE_3 0x1607E0
+
+#define mmMME2_CTRL_SHADOW_1_TENSOR_O_LOOP_STRIDE_4 0x1607E4
+
+#define mmMME2_CTRL_SHADOW_1_TENSOR_O_ROI_SIZE_0 0x1607E8
+
+#define mmMME2_CTRL_SHADOW_1_TENSOR_O_ROI_SIZE_1 0x1607EC
+
+#define mmMME2_CTRL_SHADOW_1_TENSOR_O_ROI_SIZE_2 0x1607F0
+
+#define mmMME2_CTRL_SHADOW_1_TENSOR_O_ROI_SIZE_3 0x1607F4
+
+#define mmMME2_CTRL_SHADOW_1_TENSOR_O_SPATIAL_STRIDES_0 0x1607F8
+
+#define mmMME2_CTRL_SHADOW_1_TENSOR_O_SPATIAL_STRIDES_1 0x1607FC
+
+#define mmMME2_CTRL_SHADOW_1_TENSOR_O_SPATIAL_STRIDES_2 0x160800
+
+#define mmMME2_CTRL_SHADOW_1_TENSOR_O_SPATIAL_STRIDES_3 0x160804
+
+#define mmMME2_CTRL_SHADOW_1_TENSOR_O_SPATIAL_SIZE_MINUS_1 0x160808
+
+#define mmMME2_CTRL_SHADOW_1_AGU_O_LOCAL_ROI_BASE_OFFSET_0 0x16080C
+
+#define mmMME2_CTRL_SHADOW_1_AGU_O_LOCAL_ROI_BASE_OFFSET_1 0x160810
+
+#define mmMME2_CTRL_SHADOW_1_AGU_O_LOCAL_ROI_BASE_OFFSET_2 0x160814
+
+#define mmMME2_CTRL_SHADOW_1_AGU_O_LOCAL_ROI_BASE_OFFSET_3 0x160818
+
+#define mmMME2_CTRL_SHADOW_1_AGU_O_LOCAL_ROI_BASE_OFFSET_4 0x16081C
+
+#define mmMME2_CTRL_SHADOW_1_AGU_O_LOCAL_START_OFFSET_0 0x160820
+
+#define mmMME2_CTRL_SHADOW_1_AGU_O_LOCAL_START_OFFSET_1 0x160824
+
+#define mmMME2_CTRL_SHADOW_1_AGU_O_LOCAL_START_OFFSET_2 0x160828
+
+#define mmMME2_CTRL_SHADOW_1_AGU_O_LOCAL_START_OFFSET_3 0x16082C
+
+#define mmMME2_CTRL_SHADOW_1_AGU_O_REMOTE_ROI_BASE_OFFSET_0 0x160830
+
+#define mmMME2_CTRL_SHADOW_1_AGU_O_REMOTE_ROI_BASE_OFFSET_1 0x160834
+
+#define mmMME2_CTRL_SHADOW_1_AGU_O_REMOTE_ROI_BASE_OFFSET_2 0x160838
+
+#define mmMME2_CTRL_SHADOW_1_AGU_O_REMOTE_ROI_BASE_OFFSET_3 0x16083C
+
+#define mmMME2_CTRL_SHADOW_1_AGU_O_REMOTE_ROI_BASE_OFFSET_4 0x160840
+
+#define mmMME2_CTRL_SHADOW_1_AGU_O_REMOTE_START_OFFSET_0 0x160844
+
+#define mmMME2_CTRL_SHADOW_1_AGU_O_REMOTE_START_OFFSET_1 0x160848
+
+#define mmMME2_CTRL_SHADOW_1_AGU_O_REMOTE_START_OFFSET_2 0x16084C
+
+#define mmMME2_CTRL_SHADOW_1_AGU_O_REMOTE_START_OFFSET_3 0x160850
+
+#define mmMME2_CTRL_SHADOW_1_DESC_SB_REPEAT 0x160854
+
+#define mmMME2_CTRL_SHADOW_1_DESC_RATE_LIMITER 0x160858
+
+#define mmMME2_CTRL_SHADOW_1_DESC_SYNC_OBJECT_ADDR_LOW_LOCAL 0x16085C
+
+#define mmMME2_CTRL_SHADOW_1_DESC_SYNC_OBJECT_ADDR_LOW_REMOTE 0x160860
+
+#define mmMME2_CTRL_SHADOW_1_DESC_SYNC_OBJECT_ADDR_HIGH 0x160864
+
+#define mmMME2_CTRL_SHADOW_1_DESC_SYNC_OBJECT_DATA 0x160868
+
+#define mmMME2_CTRL_SHADOW_1_DESC_AXI_USER_DATA 0x16086C
+
+#define mmMME2_CTRL_SHADOW_1_DESC_PERF_EVT_S 0x160870
+
+#define mmMME2_CTRL_SHADOW_1_DESC_PERF_EVT_L_LOCAL 0x160874
+
+#define mmMME2_CTRL_SHADOW_1_DESC_PERF_EVT_L_REMOTE 0x160878
+
+#define mmMME2_CTRL_SHADOW_1_DESC_PERF_EVT_O_LOCAL 0x16087C
+
+#define mmMME2_CTRL_SHADOW_1_DESC_PERF_EVT_O_REMOTE 0x160880
+
+#define mmMME2_CTRL_SHADOW_1_DESC_PADDING_VALUE_S 0x160884
+
+#define mmMME2_CTRL_SHADOW_1_DESC_PADDING_VALUE_L 0x160888
+
+#define mmMME2_CTRL_SHADOW_1_DESC_META_DATA_AGU_S 0x16088C
+
+#define mmMME2_CTRL_SHADOW_1_DESC_META_DATA_AGU_L_LOCAL 0x160890
+
+#define mmMME2_CTRL_SHADOW_1_DESC_META_DATA_AGU_L_REMOTE 0x160894
+
+#define mmMME2_CTRL_SHADOW_1_DESC_META_DATA_AGU_O_LOCAL 0x160898
+
+#define mmMME2_CTRL_SHADOW_1_DESC_META_DATA_AGU_O_REMOTE 0x16089C
+
+#define mmMME2_CTRL_SHADOW_1_DESC_PCU_RL_SATURATION 0x1608A0
+
+#define mmMME2_CTRL_SHADOW_1_DESC_DUMMY 0x1608A4
+
+#define mmMME2_CTRL_SHADOW_2_STATUS 0x160900
+
+#define mmMME2_CTRL_SHADOW_2_BASE_ADDR_HIGH_S 0x160908
+
+#define mmMME2_CTRL_SHADOW_2_BASE_ADDR_HIGH_L 0x16090C
+
+#define mmMME2_CTRL_SHADOW_2_BASE_ADDR_HIGH_O 0x160910
+
+#define mmMME2_CTRL_SHADOW_2_BASE_ADDR_LOW_S 0x160914
+
+#define mmMME2_CTRL_SHADOW_2_BASE_ADDR_LOW_L 0x160918
+
+#define mmMME2_CTRL_SHADOW_2_BASE_ADDR_LOW_O 0x16091C
+
+#define mmMME2_CTRL_SHADOW_2_HEADER_LOW 0x160920
+
+#define mmMME2_CTRL_SHADOW_2_HEADER_HIGH 0x160924
+
+#define mmMME2_CTRL_SHADOW_2_CONV_KERNEL_SIZE_MINUS_1 0x160928
+
+#define mmMME2_CTRL_SHADOW_2_CONV_ASSOCIATED_DIMS_LOW 0x16092C
+
+#define mmMME2_CTRL_SHADOW_2_CONV_ASSOCIATED_DIMS_HIGH 0x160930
+
+#define mmMME2_CTRL_SHADOW_2_NUM_ITERATIONS_MINUS_1 0x160934
+
+#define mmMME2_CTRL_SHADOW_2_OUTER_LOOP 0x160938
+
+#define mmMME2_CTRL_SHADOW_2_TENSOR_S_VALID_ELEMENTS_0 0x16093C
+
+#define mmMME2_CTRL_SHADOW_2_TENSOR_S_VALID_ELEMENTS_1 0x160940
+
+#define mmMME2_CTRL_SHADOW_2_TENSOR_S_VALID_ELEMENTS_2 0x160944
+
+#define mmMME2_CTRL_SHADOW_2_TENSOR_S_VALID_ELEMENTS_3 0x160948
+
+#define mmMME2_CTRL_SHADOW_2_TENSOR_S_VALID_ELEMENTS_4 0x16094C
+
+#define mmMME2_CTRL_SHADOW_2_TENSOR_S_LOOP_STRIDE_0 0x160950
+
+#define mmMME2_CTRL_SHADOW_2_TENSOR_S_LOOP_STRIDE_1 0x160954
+
+#define mmMME2_CTRL_SHADOW_2_TENSOR_S_LOOP_STRIDE_2 0x160958
+
+#define mmMME2_CTRL_SHADOW_2_TENSOR_S_LOOP_STRIDE_3 0x16095C
+
+#define mmMME2_CTRL_SHADOW_2_TENSOR_S_LOOP_STRIDE_4 0x160960
+
+#define mmMME2_CTRL_SHADOW_2_TENSOR_S_ROI_SIZE_0 0x160964
+
+#define mmMME2_CTRL_SHADOW_2_TENSOR_S_ROI_SIZE_1 0x160968
+
+#define mmMME2_CTRL_SHADOW_2_TENSOR_S_ROI_SIZE_2 0x16096C
+
+#define mmMME2_CTRL_SHADOW_2_TENSOR_S_ROI_SIZE_3 0x160970
+
+#define mmMME2_CTRL_SHADOW_2_TENSOR_S_SPATIAL_STRIDES_0 0x160974
+
+#define mmMME2_CTRL_SHADOW_2_TENSOR_S_SPATIAL_STRIDES_1 0x160978
+
+#define mmMME2_CTRL_SHADOW_2_TENSOR_S_SPATIAL_STRIDES_2 0x16097C
+
+#define mmMME2_CTRL_SHADOW_2_TENSOR_S_SPATIAL_STRIDES_3 0x160980
+
+#define mmMME2_CTRL_SHADOW_2_TENSOR_S_SPATIAL_SIZE_MINUS_1 0x160984
+
+#define mmMME2_CTRL_SHADOW_2_AGU_S_ROI_BASE_OFFSET_0 0x160988
+
+#define mmMME2_CTRL_SHADOW_2_AGU_S_ROI_BASE_OFFSET_1 0x16098C
+
+#define mmMME2_CTRL_SHADOW_2_AGU_S_ROI_BASE_OFFSET_2 0x160990
+
+#define mmMME2_CTRL_SHADOW_2_AGU_S_ROI_BASE_OFFSET_3 0x160994
+
+#define mmMME2_CTRL_SHADOW_2_AGU_S_ROI_BASE_OFFSET_4 0x160998
+
+#define mmMME2_CTRL_SHADOW_2_AGU_S_START_OFFSET_0 0x16099C
+
+#define mmMME2_CTRL_SHADOW_2_AGU_S_START_OFFSET_1 0x1609A0
+
+#define mmMME2_CTRL_SHADOW_2_AGU_S_START_OFFSET_2 0x1609A4
+
+#define mmMME2_CTRL_SHADOW_2_AGU_S_START_OFFSET_3 0x1609A8
+
+#define mmMME2_CTRL_SHADOW_2_TENSOR_L_VALID_ELEMENTS_0 0x1609AC
+
+#define mmMME2_CTRL_SHADOW_2_TENSOR_L_VALID_ELEMENTS_1 0x1609B0
+
+#define mmMME2_CTRL_SHADOW_2_TENSOR_L_VALID_ELEMENTS_2 0x1609B4
+
+#define mmMME2_CTRL_SHADOW_2_TENSOR_L_VALID_ELEMENTS_3 0x1609B8
+
+#define mmMME2_CTRL_SHADOW_2_TENSOR_L_VALID_ELEMENTS_4 0x1609BC
+
+#define mmMME2_CTRL_SHADOW_2_TENSOR_L_LOOP_STRIDE_0 0x1609C0
+
+#define mmMME2_CTRL_SHADOW_2_TENSOR_L_LOOP_STRIDE_1 0x1609C4
+
+#define mmMME2_CTRL_SHADOW_2_TENSOR_L_LOOP_STRIDE_2 0x1609C8
+
+#define mmMME2_CTRL_SHADOW_2_TENSOR_L_LOOP_STRIDE_3 0x1609CC
+
+#define mmMME2_CTRL_SHADOW_2_TENSOR_L_LOOP_STRIDE_4 0x1609D0
+
+#define mmMME2_CTRL_SHADOW_2_TENSOR_L_ROI_SIZE_0 0x1609D4
+
+#define mmMME2_CTRL_SHADOW_2_TENSOR_L_ROI_SIZE_1 0x1609D8
+
+#define mmMME2_CTRL_SHADOW_2_TENSOR_L_ROI_SIZE_2 0x1609DC
+
+#define mmMME2_CTRL_SHADOW_2_TENSOR_L_ROI_SIZE_3 0x1609E0
+
+#define mmMME2_CTRL_SHADOW_2_TENSOR_L_SPATIAL_STRIDES_0 0x1609E4
+
+#define mmMME2_CTRL_SHADOW_2_TENSOR_L_SPATIAL_STRIDES_1 0x1609E8
+
+#define mmMME2_CTRL_SHADOW_2_TENSOR_L_SPATIAL_STRIDES_2 0x1609EC
+
+#define mmMME2_CTRL_SHADOW_2_TENSOR_L_SPATIAL_STRIDES_3 0x1609F0
+
+#define mmMME2_CTRL_SHADOW_2_TENSOR_L_SPATIAL_SIZE_MINUS_1 0x1609F4
+
+#define mmMME2_CTRL_SHADOW_2_AGU_L_LOCAL_ROI_BASE_OFFSET_0 0x1609F8
+
+#define mmMME2_CTRL_SHADOW_2_AGU_L_LOCAL_ROI_BASE_OFFSET_1 0x1609FC
+
+#define mmMME2_CTRL_SHADOW_2_AGU_L_LOCAL_ROI_BASE_OFFSET_2 0x160A00
+
+#define mmMME2_CTRL_SHADOW_2_AGU_L_LOCAL_ROI_BASE_OFFSET_3 0x160A04
+
+#define mmMME2_CTRL_SHADOW_2_AGU_L_LOCAL_ROI_BASE_OFFSET_4 0x160A08
+
+#define mmMME2_CTRL_SHADOW_2_AGU_L_LOCAL_START_OFFSET_0 0x160A0C
+
+#define mmMME2_CTRL_SHADOW_2_AGU_L_LOCAL_START_OFFSET_1 0x160A10
+
+#define mmMME2_CTRL_SHADOW_2_AGU_L_LOCAL_START_OFFSET_2 0x160A14
+
+#define mmMME2_CTRL_SHADOW_2_AGU_L_LOCAL_START_OFFSET_3 0x160A18
+
+#define mmMME2_CTRL_SHADOW_2_AGU_L_REMOTE_ROI_BASE_OFFSET_0 0x160A1C
+
+#define mmMME2_CTRL_SHADOW_2_AGU_L_REMOTE_ROI_BASE_OFFSET_1 0x160A20
+
+#define mmMME2_CTRL_SHADOW_2_AGU_L_REMOTE_ROI_BASE_OFFSET_2 0x160A24
+
+#define mmMME2_CTRL_SHADOW_2_AGU_L_REMOTE_ROI_BASE_OFFSET_3 0x160A28
+
+#define mmMME2_CTRL_SHADOW_2_AGU_L_REMOTE_ROI_BASE_OFFSET_4 0x160A2C
+
+#define mmMME2_CTRL_SHADOW_2_AGU_L_REMOTE_START_OFFSET_0 0x160A30
+
+#define mmMME2_CTRL_SHADOW_2_AGU_L_REMOTE_START_OFFSET_1 0x160A34
+
+#define mmMME2_CTRL_SHADOW_2_AGU_L_REMOTE_START_OFFSET_2 0x160A38
+
+#define mmMME2_CTRL_SHADOW_2_AGU_L_REMOTE_START_OFFSET_3 0x160A3C
+
+#define mmMME2_CTRL_SHADOW_2_TENSOR_O_VALID_ELEMENTS_0 0x160A40
+
+#define mmMME2_CTRL_SHADOW_2_TENSOR_O_VALID_ELEMENTS_1 0x160A44
+
+#define mmMME2_CTRL_SHADOW_2_TENSOR_O_VALID_ELEMENTS_2 0x160A48
+
+#define mmMME2_CTRL_SHADOW_2_TENSOR_O_VALID_ELEMENTS_3 0x160A4C
+
+#define mmMME2_CTRL_SHADOW_2_TENSOR_O_VALID_ELEMENTS_4 0x160A50
+
+#define mmMME2_CTRL_SHADOW_2_TENSOR_O_LOOP_STRIDE_0 0x160A54
+
+#define mmMME2_CTRL_SHADOW_2_TENSOR_O_LOOP_STRIDE_1 0x160A58
+
+#define mmMME2_CTRL_SHADOW_2_TENSOR_O_LOOP_STRIDE_2 0x160A5C
+
+#define mmMME2_CTRL_SHADOW_2_TENSOR_O_LOOP_STRIDE_3 0x160A60
+
+#define mmMME2_CTRL_SHADOW_2_TENSOR_O_LOOP_STRIDE_4 0x160A64
+
+#define mmMME2_CTRL_SHADOW_2_TENSOR_O_ROI_SIZE_0 0x160A68
+
+#define mmMME2_CTRL_SHADOW_2_TENSOR_O_ROI_SIZE_1 0x160A6C
+
+#define mmMME2_CTRL_SHADOW_2_TENSOR_O_ROI_SIZE_2 0x160A70
+
+#define mmMME2_CTRL_SHADOW_2_TENSOR_O_ROI_SIZE_3 0x160A74
+
+#define mmMME2_CTRL_SHADOW_2_TENSOR_O_SPATIAL_STRIDES_0 0x160A78
+
+#define mmMME2_CTRL_SHADOW_2_TENSOR_O_SPATIAL_STRIDES_1 0x160A7C
+
+#define mmMME2_CTRL_SHADOW_2_TENSOR_O_SPATIAL_STRIDES_2 0x160A80
+
+#define mmMME2_CTRL_SHADOW_2_TENSOR_O_SPATIAL_STRIDES_3 0x160A84
+
+#define mmMME2_CTRL_SHADOW_2_TENSOR_O_SPATIAL_SIZE_MINUS_1 0x160A88
+
+#define mmMME2_CTRL_SHADOW_2_AGU_O_LOCAL_ROI_BASE_OFFSET_0 0x160A8C
+
+#define mmMME2_CTRL_SHADOW_2_AGU_O_LOCAL_ROI_BASE_OFFSET_1 0x160A90
+
+#define mmMME2_CTRL_SHADOW_2_AGU_O_LOCAL_ROI_BASE_OFFSET_2 0x160A94
+
+#define mmMME2_CTRL_SHADOW_2_AGU_O_LOCAL_ROI_BASE_OFFSET_3 0x160A98
+
+#define mmMME2_CTRL_SHADOW_2_AGU_O_LOCAL_ROI_BASE_OFFSET_4 0x160A9C
+
+#define mmMME2_CTRL_SHADOW_2_AGU_O_LOCAL_START_OFFSET_0 0x160AA0
+
+#define mmMME2_CTRL_SHADOW_2_AGU_O_LOCAL_START_OFFSET_1 0x160AA4
+
+#define mmMME2_CTRL_SHADOW_2_AGU_O_LOCAL_START_OFFSET_2 0x160AA8
+
+#define mmMME2_CTRL_SHADOW_2_AGU_O_LOCAL_START_OFFSET_3 0x160AAC
+
+#define mmMME2_CTRL_SHADOW_2_AGU_O_REMOTE_ROI_BASE_OFFSET_0 0x160AB0
+
+#define mmMME2_CTRL_SHADOW_2_AGU_O_REMOTE_ROI_BASE_OFFSET_1 0x160AB4
+
+#define mmMME2_CTRL_SHADOW_2_AGU_O_REMOTE_ROI_BASE_OFFSET_2 0x160AB8
+
+#define mmMME2_CTRL_SHADOW_2_AGU_O_REMOTE_ROI_BASE_OFFSET_3 0x160ABC
+
+#define mmMME2_CTRL_SHADOW_2_AGU_O_REMOTE_ROI_BASE_OFFSET_4 0x160AC0
+
+#define mmMME2_CTRL_SHADOW_2_AGU_O_REMOTE_START_OFFSET_0 0x160AC4
+
+#define mmMME2_CTRL_SHADOW_2_AGU_O_REMOTE_START_OFFSET_1 0x160AC8
+
+#define mmMME2_CTRL_SHADOW_2_AGU_O_REMOTE_START_OFFSET_2 0x160ACC
+
+#define mmMME2_CTRL_SHADOW_2_AGU_O_REMOTE_START_OFFSET_3 0x160AD0
+
+#define mmMME2_CTRL_SHADOW_2_DESC_SB_REPEAT 0x160AD4
+
+#define mmMME2_CTRL_SHADOW_2_DESC_RATE_LIMITER 0x160AD8
+
+#define mmMME2_CTRL_SHADOW_2_DESC_SYNC_OBJECT_ADDR_LOW_LOCAL 0x160ADC
+
+#define mmMME2_CTRL_SHADOW_2_DESC_SYNC_OBJECT_ADDR_LOW_REMOTE 0x160AE0
+
+#define mmMME2_CTRL_SHADOW_2_DESC_SYNC_OBJECT_ADDR_HIGH 0x160AE4
+
+#define mmMME2_CTRL_SHADOW_2_DESC_SYNC_OBJECT_DATA 0x160AE8
+
+#define mmMME2_CTRL_SHADOW_2_DESC_AXI_USER_DATA 0x160AEC
+
+#define mmMME2_CTRL_SHADOW_2_DESC_PERF_EVT_S 0x160AF0
+
+#define mmMME2_CTRL_SHADOW_2_DESC_PERF_EVT_L_LOCAL 0x160AF4
+
+#define mmMME2_CTRL_SHADOW_2_DESC_PERF_EVT_L_REMOTE 0x160AF8
+
+#define mmMME2_CTRL_SHADOW_2_DESC_PERF_EVT_O_LOCAL 0x160AFC
+
+#define mmMME2_CTRL_SHADOW_2_DESC_PERF_EVT_O_REMOTE 0x160B00
+
+#define mmMME2_CTRL_SHADOW_2_DESC_PADDING_VALUE_S 0x160B04
+
+#define mmMME2_CTRL_SHADOW_2_DESC_PADDING_VALUE_L 0x160B08
+
+#define mmMME2_CTRL_SHADOW_2_DESC_META_DATA_AGU_S 0x160B0C
+
+#define mmMME2_CTRL_SHADOW_2_DESC_META_DATA_AGU_L_LOCAL 0x160B10
+
+#define mmMME2_CTRL_SHADOW_2_DESC_META_DATA_AGU_L_REMOTE 0x160B14
+
+#define mmMME2_CTRL_SHADOW_2_DESC_META_DATA_AGU_O_LOCAL 0x160B18
+
+#define mmMME2_CTRL_SHADOW_2_DESC_META_DATA_AGU_O_REMOTE 0x160B1C
+
+#define mmMME2_CTRL_SHADOW_2_DESC_PCU_RL_SATURATION 0x160B20
+
+#define mmMME2_CTRL_SHADOW_2_DESC_DUMMY 0x160B24
+
+#define mmMME2_CTRL_SHADOW_3_STATUS 0x160B80
+
+#define mmMME2_CTRL_SHADOW_3_BASE_ADDR_HIGH_S 0x160B88
+
+#define mmMME2_CTRL_SHADOW_3_BASE_ADDR_HIGH_L 0x160B8C
+
+#define mmMME2_CTRL_SHADOW_3_BASE_ADDR_HIGH_O 0x160B90
+
+#define mmMME2_CTRL_SHADOW_3_BASE_ADDR_LOW_S 0x160B94
+
+#define mmMME2_CTRL_SHADOW_3_BASE_ADDR_LOW_L 0x160B98
+
+#define mmMME2_CTRL_SHADOW_3_BASE_ADDR_LOW_O 0x160B9C
+
+#define mmMME2_CTRL_SHADOW_3_HEADER_LOW 0x160BA0
+
+#define mmMME2_CTRL_SHADOW_3_HEADER_HIGH 0x160BA4
+
+#define mmMME2_CTRL_SHADOW_3_CONV_KERNEL_SIZE_MINUS_1 0x160BA8
+
+#define mmMME2_CTRL_SHADOW_3_CONV_ASSOCIATED_DIMS_LOW 0x160BAC
+
+#define mmMME2_CTRL_SHADOW_3_CONV_ASSOCIATED_DIMS_HIGH 0x160BB0
+
+#define mmMME2_CTRL_SHADOW_3_NUM_ITERATIONS_MINUS_1 0x160BB4
+
+#define mmMME2_CTRL_SHADOW_3_OUTER_LOOP 0x160BB8
+
+#define mmMME2_CTRL_SHADOW_3_TENSOR_S_VALID_ELEMENTS_0 0x160BBC
+
+#define mmMME2_CTRL_SHADOW_3_TENSOR_S_VALID_ELEMENTS_1 0x160BC0
+
+#define mmMME2_CTRL_SHADOW_3_TENSOR_S_VALID_ELEMENTS_2 0x160BC4
+
+#define mmMME2_CTRL_SHADOW_3_TENSOR_S_VALID_ELEMENTS_3 0x160BC8
+
+#define mmMME2_CTRL_SHADOW_3_TENSOR_S_VALID_ELEMENTS_4 0x160BCC
+
+#define mmMME2_CTRL_SHADOW_3_TENSOR_S_LOOP_STRIDE_0 0x160BD0
+
+#define mmMME2_CTRL_SHADOW_3_TENSOR_S_LOOP_STRIDE_1 0x160BD4
+
+#define mmMME2_CTRL_SHADOW_3_TENSOR_S_LOOP_STRIDE_2 0x160BD8
+
+#define mmMME2_CTRL_SHADOW_3_TENSOR_S_LOOP_STRIDE_3 0x160BDC
+
+#define mmMME2_CTRL_SHADOW_3_TENSOR_S_LOOP_STRIDE_4 0x160BE0
+
+#define mmMME2_CTRL_SHADOW_3_TENSOR_S_ROI_SIZE_0 0x160BE4
+
+#define mmMME2_CTRL_SHADOW_3_TENSOR_S_ROI_SIZE_1 0x160BE8
+
+#define mmMME2_CTRL_SHADOW_3_TENSOR_S_ROI_SIZE_2 0x160BEC
+
+#define mmMME2_CTRL_SHADOW_3_TENSOR_S_ROI_SIZE_3 0x160BF0
+
+#define mmMME2_CTRL_SHADOW_3_TENSOR_S_SPATIAL_STRIDES_0 0x160BF4
+
+#define mmMME2_CTRL_SHADOW_3_TENSOR_S_SPATIAL_STRIDES_1 0x160BF8
+
+#define mmMME2_CTRL_SHADOW_3_TENSOR_S_SPATIAL_STRIDES_2 0x160BFC
+
+#define mmMME2_CTRL_SHADOW_3_TENSOR_S_SPATIAL_STRIDES_3 0x160C00
+
+#define mmMME2_CTRL_SHADOW_3_TENSOR_S_SPATIAL_SIZE_MINUS_1 0x160C04
+
+#define mmMME2_CTRL_SHADOW_3_AGU_S_ROI_BASE_OFFSET_0 0x160C08
+
+#define mmMME2_CTRL_SHADOW_3_AGU_S_ROI_BASE_OFFSET_1 0x160C0C
+
+#define mmMME2_CTRL_SHADOW_3_AGU_S_ROI_BASE_OFFSET_2 0x160C10
+
+#define mmMME2_CTRL_SHADOW_3_AGU_S_ROI_BASE_OFFSET_3 0x160C14
+
+#define mmMME2_CTRL_SHADOW_3_AGU_S_ROI_BASE_OFFSET_4 0x160C18
+
+#define mmMME2_CTRL_SHADOW_3_AGU_S_START_OFFSET_0 0x160C1C
+
+#define mmMME2_CTRL_SHADOW_3_AGU_S_START_OFFSET_1 0x160C20
+
+#define mmMME2_CTRL_SHADOW_3_AGU_S_START_OFFSET_2 0x160C24
+
+#define mmMME2_CTRL_SHADOW_3_AGU_S_START_OFFSET_3 0x160C28
+
+#define mmMME2_CTRL_SHADOW_3_TENSOR_L_VALID_ELEMENTS_0 0x160C2C
+
+#define mmMME2_CTRL_SHADOW_3_TENSOR_L_VALID_ELEMENTS_1 0x160C30
+
+#define mmMME2_CTRL_SHADOW_3_TENSOR_L_VALID_ELEMENTS_2 0x160C34
+
+#define mmMME2_CTRL_SHADOW_3_TENSOR_L_VALID_ELEMENTS_3 0x160C38
+
+#define mmMME2_CTRL_SHADOW_3_TENSOR_L_VALID_ELEMENTS_4 0x160C3C
+
+#define mmMME2_CTRL_SHADOW_3_TENSOR_L_LOOP_STRIDE_0 0x160C40
+
+#define mmMME2_CTRL_SHADOW_3_TENSOR_L_LOOP_STRIDE_1 0x160C44
+
+#define mmMME2_CTRL_SHADOW_3_TENSOR_L_LOOP_STRIDE_2 0x160C48
+
+#define mmMME2_CTRL_SHADOW_3_TENSOR_L_LOOP_STRIDE_3 0x160C4C
+
+#define mmMME2_CTRL_SHADOW_3_TENSOR_L_LOOP_STRIDE_4 0x160C50
+
+#define mmMME2_CTRL_SHADOW_3_TENSOR_L_ROI_SIZE_0 0x160C54
+
+#define mmMME2_CTRL_SHADOW_3_TENSOR_L_ROI_SIZE_1 0x160C58
+
+#define mmMME2_CTRL_SHADOW_3_TENSOR_L_ROI_SIZE_2 0x160C5C
+
+#define mmMME2_CTRL_SHADOW_3_TENSOR_L_ROI_SIZE_3 0x160C60
+
+#define mmMME2_CTRL_SHADOW_3_TENSOR_L_SPATIAL_STRIDES_0 0x160C64
+
+#define mmMME2_CTRL_SHADOW_3_TENSOR_L_SPATIAL_STRIDES_1 0x160C68
+
+#define mmMME2_CTRL_SHADOW_3_TENSOR_L_SPATIAL_STRIDES_2 0x160C6C
+
+#define mmMME2_CTRL_SHADOW_3_TENSOR_L_SPATIAL_STRIDES_3 0x160C70
+
+#define mmMME2_CTRL_SHADOW_3_TENSOR_L_SPATIAL_SIZE_MINUS_1 0x160C74
+
+#define mmMME2_CTRL_SHADOW_3_AGU_L_LOCAL_ROI_BASE_OFFSET_0 0x160C78
+
+#define mmMME2_CTRL_SHADOW_3_AGU_L_LOCAL_ROI_BASE_OFFSET_1 0x160C7C
+
+#define mmMME2_CTRL_SHADOW_3_AGU_L_LOCAL_ROI_BASE_OFFSET_2 0x160C80
+
+#define mmMME2_CTRL_SHADOW_3_AGU_L_LOCAL_ROI_BASE_OFFSET_3 0x160C84
+
+#define mmMME2_CTRL_SHADOW_3_AGU_L_LOCAL_ROI_BASE_OFFSET_4 0x160C88
+
+#define mmMME2_CTRL_SHADOW_3_AGU_L_LOCAL_START_OFFSET_0 0x160C8C
+
+#define mmMME2_CTRL_SHADOW_3_AGU_L_LOCAL_START_OFFSET_1 0x160C90
+
+#define mmMME2_CTRL_SHADOW_3_AGU_L_LOCAL_START_OFFSET_2 0x160C94
+
+#define mmMME2_CTRL_SHADOW_3_AGU_L_LOCAL_START_OFFSET_3 0x160C98
+
+#define mmMME2_CTRL_SHADOW_3_AGU_L_REMOTE_ROI_BASE_OFFSET_0 0x160C9C
+
+#define mmMME2_CTRL_SHADOW_3_AGU_L_REMOTE_ROI_BASE_OFFSET_1 0x160CA0
+
+#define mmMME2_CTRL_SHADOW_3_AGU_L_REMOTE_ROI_BASE_OFFSET_2 0x160CA4
+
+#define mmMME2_CTRL_SHADOW_3_AGU_L_REMOTE_ROI_BASE_OFFSET_3 0x160CA8
+
+#define mmMME2_CTRL_SHADOW_3_AGU_L_REMOTE_ROI_BASE_OFFSET_4 0x160CAC
+
+#define mmMME2_CTRL_SHADOW_3_AGU_L_REMOTE_START_OFFSET_0 0x160CB0
+
+#define mmMME2_CTRL_SHADOW_3_AGU_L_REMOTE_START_OFFSET_1 0x160CB4
+
+#define mmMME2_CTRL_SHADOW_3_AGU_L_REMOTE_START_OFFSET_2 0x160CB8
+
+#define mmMME2_CTRL_SHADOW_3_AGU_L_REMOTE_START_OFFSET_3 0x160CBC
+
+#define mmMME2_CTRL_SHADOW_3_TENSOR_O_VALID_ELEMENTS_0 0x160CC0
+
+#define mmMME2_CTRL_SHADOW_3_TENSOR_O_VALID_ELEMENTS_1 0x160CC4
+
+#define mmMME2_CTRL_SHADOW_3_TENSOR_O_VALID_ELEMENTS_2 0x160CC8
+
+#define mmMME2_CTRL_SHADOW_3_TENSOR_O_VALID_ELEMENTS_3 0x160CCC
+
+#define mmMME2_CTRL_SHADOW_3_TENSOR_O_VALID_ELEMENTS_4 0x160CD0
+
+#define mmMME2_CTRL_SHADOW_3_TENSOR_O_LOOP_STRIDE_0 0x160CD4
+
+#define mmMME2_CTRL_SHADOW_3_TENSOR_O_LOOP_STRIDE_1 0x160CD8
+
+#define mmMME2_CTRL_SHADOW_3_TENSOR_O_LOOP_STRIDE_2 0x160CDC
+
+#define mmMME2_CTRL_SHADOW_3_TENSOR_O_LOOP_STRIDE_3 0x160CE0
+
+#define mmMME2_CTRL_SHADOW_3_TENSOR_O_LOOP_STRIDE_4 0x160CE4
+
+#define mmMME2_CTRL_SHADOW_3_TENSOR_O_ROI_SIZE_0 0x160CE8
+
+#define mmMME2_CTRL_SHADOW_3_TENSOR_O_ROI_SIZE_1 0x160CEC
+
+#define mmMME2_CTRL_SHADOW_3_TENSOR_O_ROI_SIZE_2 0x160CF0
+
+#define mmMME2_CTRL_SHADOW_3_TENSOR_O_ROI_SIZE_3 0x160CF4
+
+#define mmMME2_CTRL_SHADOW_3_TENSOR_O_SPATIAL_STRIDES_0 0x160CF8
+
+#define mmMME2_CTRL_SHADOW_3_TENSOR_O_SPATIAL_STRIDES_1 0x160CFC
+
+#define mmMME2_CTRL_SHADOW_3_TENSOR_O_SPATIAL_STRIDES_2 0x160D00
+
+#define mmMME2_CTRL_SHADOW_3_TENSOR_O_SPATIAL_STRIDES_3 0x160D04
+
+#define mmMME2_CTRL_SHADOW_3_TENSOR_O_SPATIAL_SIZE_MINUS_1 0x160D08
+
+#define mmMME2_CTRL_SHADOW_3_AGU_O_LOCAL_ROI_BASE_OFFSET_0 0x160D0C
+
+#define mmMME2_CTRL_SHADOW_3_AGU_O_LOCAL_ROI_BASE_OFFSET_1 0x160D10
+
+#define mmMME2_CTRL_SHADOW_3_AGU_O_LOCAL_ROI_BASE_OFFSET_2 0x160D14
+
+#define mmMME2_CTRL_SHADOW_3_AGU_O_LOCAL_ROI_BASE_OFFSET_3 0x160D18
+
+#define mmMME2_CTRL_SHADOW_3_AGU_O_LOCAL_ROI_BASE_OFFSET_4 0x160D1C
+
+#define mmMME2_CTRL_SHADOW_3_AGU_O_LOCAL_START_OFFSET_0 0x160D20
+
+#define mmMME2_CTRL_SHADOW_3_AGU_O_LOCAL_START_OFFSET_1 0x160D24
+
+#define mmMME2_CTRL_SHADOW_3_AGU_O_LOCAL_START_OFFSET_2 0x160D28
+
+#define mmMME2_CTRL_SHADOW_3_AGU_O_LOCAL_START_OFFSET_3 0x160D2C
+
+#define mmMME2_CTRL_SHADOW_3_AGU_O_REMOTE_ROI_BASE_OFFSET_0 0x160D30
+
+#define mmMME2_CTRL_SHADOW_3_AGU_O_REMOTE_ROI_BASE_OFFSET_1 0x160D34
+
+#define mmMME2_CTRL_SHADOW_3_AGU_O_REMOTE_ROI_BASE_OFFSET_2 0x160D38
+
+#define mmMME2_CTRL_SHADOW_3_AGU_O_REMOTE_ROI_BASE_OFFSET_3 0x160D3C
+
+#define mmMME2_CTRL_SHADOW_3_AGU_O_REMOTE_ROI_BASE_OFFSET_4 0x160D40
+
+#define mmMME2_CTRL_SHADOW_3_AGU_O_REMOTE_START_OFFSET_0 0x160D44
+
+#define mmMME2_CTRL_SHADOW_3_AGU_O_REMOTE_START_OFFSET_1 0x160D48
+
+#define mmMME2_CTRL_SHADOW_3_AGU_O_REMOTE_START_OFFSET_2 0x160D4C
+
+#define mmMME2_CTRL_SHADOW_3_AGU_O_REMOTE_START_OFFSET_3 0x160D50
+
+#define mmMME2_CTRL_SHADOW_3_DESC_SB_REPEAT 0x160D54
+
+#define mmMME2_CTRL_SHADOW_3_DESC_RATE_LIMITER 0x160D58
+
+#define mmMME2_CTRL_SHADOW_3_DESC_SYNC_OBJECT_ADDR_LOW_LOCAL 0x160D5C
+
+#define mmMME2_CTRL_SHADOW_3_DESC_SYNC_OBJECT_ADDR_LOW_REMOTE 0x160D60
+
+#define mmMME2_CTRL_SHADOW_3_DESC_SYNC_OBJECT_ADDR_HIGH 0x160D64
+
+#define mmMME2_CTRL_SHADOW_3_DESC_SYNC_OBJECT_DATA 0x160D68
+
+#define mmMME2_CTRL_SHADOW_3_DESC_AXI_USER_DATA 0x160D6C
+
+#define mmMME2_CTRL_SHADOW_3_DESC_PERF_EVT_S 0x160D70
+
+#define mmMME2_CTRL_SHADOW_3_DESC_PERF_EVT_L_LOCAL 0x160D74
+
+#define mmMME2_CTRL_SHADOW_3_DESC_PERF_EVT_L_REMOTE 0x160D78
+
+#define mmMME2_CTRL_SHADOW_3_DESC_PERF_EVT_O_LOCAL 0x160D7C
+
+#define mmMME2_CTRL_SHADOW_3_DESC_PERF_EVT_O_REMOTE 0x160D80
+
+#define mmMME2_CTRL_SHADOW_3_DESC_PADDING_VALUE_S 0x160D84
+
+#define mmMME2_CTRL_SHADOW_3_DESC_PADDING_VALUE_L 0x160D88
+
+#define mmMME2_CTRL_SHADOW_3_DESC_META_DATA_AGU_S 0x160D8C
+
+#define mmMME2_CTRL_SHADOW_3_DESC_META_DATA_AGU_L_LOCAL 0x160D90
+
+#define mmMME2_CTRL_SHADOW_3_DESC_META_DATA_AGU_L_REMOTE 0x160D94
+
+#define mmMME2_CTRL_SHADOW_3_DESC_META_DATA_AGU_O_LOCAL 0x160D98
+
+#define mmMME2_CTRL_SHADOW_3_DESC_META_DATA_AGU_O_REMOTE 0x160D9C
+
+#define mmMME2_CTRL_SHADOW_3_DESC_PCU_RL_SATURATION 0x160DA0
+
+#define mmMME2_CTRL_SHADOW_3_DESC_DUMMY 0x160DA4
+
+#endif /* ASIC_REG_MME2_CTRL_REGS_H_ */
diff --git a/drivers/accel/habanalabs/include/gaudi/asic_reg/mme2_qm_regs.h b/drivers/accel/habanalabs/include/gaudi/asic_reg/mme2_qm_regs.h
new file mode 100644
index 0000000000..c1ea6a4220
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi/asic_reg/mme2_qm_regs.h
@@ -0,0 +1,834 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2016-2018 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ ** DO NOT EDIT BELOW **
+ ************************************/
+
+#ifndef ASIC_REG_MME2_QM_REGS_H_
+#define ASIC_REG_MME2_QM_REGS_H_
+
+/*
+ *****************************************
+ * MME2_QM (Prototype: QMAN)
+ *****************************************
+ */
+
+#define mmMME2_QM_GLBL_CFG0 0x168000
+
+#define mmMME2_QM_GLBL_CFG1 0x168004
+
+#define mmMME2_QM_GLBL_PROT 0x168008
+
+#define mmMME2_QM_GLBL_ERR_CFG 0x16800C
+
+#define mmMME2_QM_GLBL_SECURE_PROPS_0 0x168010
+
+#define mmMME2_QM_GLBL_SECURE_PROPS_1 0x168014
+
+#define mmMME2_QM_GLBL_SECURE_PROPS_2 0x168018
+
+#define mmMME2_QM_GLBL_SECURE_PROPS_3 0x16801C
+
+#define mmMME2_QM_GLBL_SECURE_PROPS_4 0x168020
+
+#define mmMME2_QM_GLBL_NON_SECURE_PROPS_0 0x168024
+
+#define mmMME2_QM_GLBL_NON_SECURE_PROPS_1 0x168028
+
+#define mmMME2_QM_GLBL_NON_SECURE_PROPS_2 0x16802C
+
+#define mmMME2_QM_GLBL_NON_SECURE_PROPS_3 0x168030
+
+#define mmMME2_QM_GLBL_NON_SECURE_PROPS_4 0x168034
+
+#define mmMME2_QM_GLBL_STS0 0x168038
+
+#define mmMME2_QM_GLBL_STS1_0 0x168040
+
+#define mmMME2_QM_GLBL_STS1_1 0x168044
+
+#define mmMME2_QM_GLBL_STS1_2 0x168048
+
+#define mmMME2_QM_GLBL_STS1_3 0x16804C
+
+#define mmMME2_QM_GLBL_STS1_4 0x168050
+
+#define mmMME2_QM_GLBL_MSG_EN_0 0x168054
+
+#define mmMME2_QM_GLBL_MSG_EN_1 0x168058
+
+#define mmMME2_QM_GLBL_MSG_EN_2 0x16805C
+
+#define mmMME2_QM_GLBL_MSG_EN_3 0x168060
+
+#define mmMME2_QM_GLBL_MSG_EN_4 0x168068
+
+#define mmMME2_QM_PQ_BASE_LO_0 0x168070
+
+#define mmMME2_QM_PQ_BASE_LO_1 0x168074
+
+#define mmMME2_QM_PQ_BASE_LO_2 0x168078
+
+#define mmMME2_QM_PQ_BASE_LO_3 0x16807C
+
+#define mmMME2_QM_PQ_BASE_HI_0 0x168080
+
+#define mmMME2_QM_PQ_BASE_HI_1 0x168084
+
+#define mmMME2_QM_PQ_BASE_HI_2 0x168088
+
+#define mmMME2_QM_PQ_BASE_HI_3 0x16808C
+
+#define mmMME2_QM_PQ_SIZE_0 0x168090
+
+#define mmMME2_QM_PQ_SIZE_1 0x168094
+
+#define mmMME2_QM_PQ_SIZE_2 0x168098
+
+#define mmMME2_QM_PQ_SIZE_3 0x16809C
+
+#define mmMME2_QM_PQ_PI_0 0x1680A0
+
+#define mmMME2_QM_PQ_PI_1 0x1680A4
+
+#define mmMME2_QM_PQ_PI_2 0x1680A8
+
+#define mmMME2_QM_PQ_PI_3 0x1680AC
+
+#define mmMME2_QM_PQ_CI_0 0x1680B0
+
+#define mmMME2_QM_PQ_CI_1 0x1680B4
+
+#define mmMME2_QM_PQ_CI_2 0x1680B8
+
+#define mmMME2_QM_PQ_CI_3 0x1680BC
+
+#define mmMME2_QM_PQ_CFG0_0 0x1680C0
+
+#define mmMME2_QM_PQ_CFG0_1 0x1680C4
+
+#define mmMME2_QM_PQ_CFG0_2 0x1680C8
+
+#define mmMME2_QM_PQ_CFG0_3 0x1680CC
+
+#define mmMME2_QM_PQ_CFG1_0 0x1680D0
+
+#define mmMME2_QM_PQ_CFG1_1 0x1680D4
+
+#define mmMME2_QM_PQ_CFG1_2 0x1680D8
+
+#define mmMME2_QM_PQ_CFG1_3 0x1680DC
+
+#define mmMME2_QM_PQ_ARUSER_31_11_0 0x1680E0
+
+#define mmMME2_QM_PQ_ARUSER_31_11_1 0x1680E4
+
+#define mmMME2_QM_PQ_ARUSER_31_11_2 0x1680E8
+
+#define mmMME2_QM_PQ_ARUSER_31_11_3 0x1680EC
+
+#define mmMME2_QM_PQ_STS0_0 0x1680F0
+
+#define mmMME2_QM_PQ_STS0_1 0x1680F4
+
+#define mmMME2_QM_PQ_STS0_2 0x1680F8
+
+#define mmMME2_QM_PQ_STS0_3 0x1680FC
+
+#define mmMME2_QM_PQ_STS1_0 0x168100
+
+#define mmMME2_QM_PQ_STS1_1 0x168104
+
+#define mmMME2_QM_PQ_STS1_2 0x168108
+
+#define mmMME2_QM_PQ_STS1_3 0x16810C
+
+#define mmMME2_QM_CQ_CFG0_0 0x168110
+
+#define mmMME2_QM_CQ_CFG0_1 0x168114
+
+#define mmMME2_QM_CQ_CFG0_2 0x168118
+
+#define mmMME2_QM_CQ_CFG0_3 0x16811C
+
+#define mmMME2_QM_CQ_CFG0_4 0x168120
+
+#define mmMME2_QM_CQ_CFG1_0 0x168124
+
+#define mmMME2_QM_CQ_CFG1_1 0x168128
+
+#define mmMME2_QM_CQ_CFG1_2 0x16812C
+
+#define mmMME2_QM_CQ_CFG1_3 0x168130
+
+#define mmMME2_QM_CQ_CFG1_4 0x168134
+
+#define mmMME2_QM_CQ_ARUSER_31_11_0 0x168138
+
+#define mmMME2_QM_CQ_ARUSER_31_11_1 0x16813C
+
+#define mmMME2_QM_CQ_ARUSER_31_11_2 0x168140
+
+#define mmMME2_QM_CQ_ARUSER_31_11_3 0x168144
+
+#define mmMME2_QM_CQ_ARUSER_31_11_4 0x168148
+
+#define mmMME2_QM_CQ_STS0_0 0x16814C
+
+#define mmMME2_QM_CQ_STS0_1 0x168150
+
+#define mmMME2_QM_CQ_STS0_2 0x168154
+
+#define mmMME2_QM_CQ_STS0_3 0x168158
+
+#define mmMME2_QM_CQ_STS0_4 0x16815C
+
+#define mmMME2_QM_CQ_STS1_0 0x168160
+
+#define mmMME2_QM_CQ_STS1_1 0x168164
+
+#define mmMME2_QM_CQ_STS1_2 0x168168
+
+#define mmMME2_QM_CQ_STS1_3 0x16816C
+
+#define mmMME2_QM_CQ_STS1_4 0x168170
+
+#define mmMME2_QM_CQ_PTR_LO_0 0x168174
+
+#define mmMME2_QM_CQ_PTR_HI_0 0x168178
+
+#define mmMME2_QM_CQ_TSIZE_0 0x16817C
+
+#define mmMME2_QM_CQ_CTL_0 0x168180
+
+#define mmMME2_QM_CQ_PTR_LO_1 0x168184
+
+#define mmMME2_QM_CQ_PTR_HI_1 0x168188
+
+#define mmMME2_QM_CQ_TSIZE_1 0x16818C
+
+#define mmMME2_QM_CQ_CTL_1 0x168190
+
+#define mmMME2_QM_CQ_PTR_LO_2 0x168194
+
+#define mmMME2_QM_CQ_PTR_HI_2 0x168198
+
+#define mmMME2_QM_CQ_TSIZE_2 0x16819C
+
+#define mmMME2_QM_CQ_CTL_2 0x1681A0
+
+#define mmMME2_QM_CQ_PTR_LO_3 0x1681A4
+
+#define mmMME2_QM_CQ_PTR_HI_3 0x1681A8
+
+#define mmMME2_QM_CQ_TSIZE_3 0x1681AC
+
+#define mmMME2_QM_CQ_CTL_3 0x1681B0
+
+#define mmMME2_QM_CQ_PTR_LO_4 0x1681B4
+
+#define mmMME2_QM_CQ_PTR_HI_4 0x1681B8
+
+#define mmMME2_QM_CQ_TSIZE_4 0x1681BC
+
+#define mmMME2_QM_CQ_CTL_4 0x1681C0
+
+#define mmMME2_QM_CQ_PTR_LO_STS_0 0x1681C4
+
+#define mmMME2_QM_CQ_PTR_LO_STS_1 0x1681C8
+
+#define mmMME2_QM_CQ_PTR_LO_STS_2 0x1681CC
+
+#define mmMME2_QM_CQ_PTR_LO_STS_3 0x1681D0
+
+#define mmMME2_QM_CQ_PTR_LO_STS_4 0x1681D4
+
+#define mmMME2_QM_CQ_PTR_HI_STS_0 0x1681D8
+
+#define mmMME2_QM_CQ_PTR_HI_STS_1 0x1681DC
+
+#define mmMME2_QM_CQ_PTR_HI_STS_2 0x1681E0
+
+#define mmMME2_QM_CQ_PTR_HI_STS_3 0x1681E4
+
+#define mmMME2_QM_CQ_PTR_HI_STS_4 0x1681E8
+
+#define mmMME2_QM_CQ_TSIZE_STS_0 0x1681EC
+
+#define mmMME2_QM_CQ_TSIZE_STS_1 0x1681F0
+
+#define mmMME2_QM_CQ_TSIZE_STS_2 0x1681F4
+
+#define mmMME2_QM_CQ_TSIZE_STS_3 0x1681F8
+
+#define mmMME2_QM_CQ_TSIZE_STS_4 0x1681FC
+
+#define mmMME2_QM_CQ_CTL_STS_0 0x168200
+
+#define mmMME2_QM_CQ_CTL_STS_1 0x168204
+
+#define mmMME2_QM_CQ_CTL_STS_2 0x168208
+
+#define mmMME2_QM_CQ_CTL_STS_3 0x16820C
+
+#define mmMME2_QM_CQ_CTL_STS_4 0x168210
+
+#define mmMME2_QM_CQ_IFIFO_CNT_0 0x168214
+
+#define mmMME2_QM_CQ_IFIFO_CNT_1 0x168218
+
+#define mmMME2_QM_CQ_IFIFO_CNT_2 0x16821C
+
+#define mmMME2_QM_CQ_IFIFO_CNT_3 0x168220
+
+#define mmMME2_QM_CQ_IFIFO_CNT_4 0x168224
+
+#define mmMME2_QM_CP_MSG_BASE0_ADDR_LO_0 0x168228
+
+#define mmMME2_QM_CP_MSG_BASE0_ADDR_LO_1 0x16822C
+
+#define mmMME2_QM_CP_MSG_BASE0_ADDR_LO_2 0x168230
+
+#define mmMME2_QM_CP_MSG_BASE0_ADDR_LO_3 0x168234
+
+#define mmMME2_QM_CP_MSG_BASE0_ADDR_LO_4 0x168238
+
+#define mmMME2_QM_CP_MSG_BASE0_ADDR_HI_0 0x16823C
+
+#define mmMME2_QM_CP_MSG_BASE0_ADDR_HI_1 0x168240
+
+#define mmMME2_QM_CP_MSG_BASE0_ADDR_HI_2 0x168244
+
+#define mmMME2_QM_CP_MSG_BASE0_ADDR_HI_3 0x168248
+
+#define mmMME2_QM_CP_MSG_BASE0_ADDR_HI_4 0x16824C
+
+#define mmMME2_QM_CP_MSG_BASE1_ADDR_LO_0 0x168250
+
+#define mmMME2_QM_CP_MSG_BASE1_ADDR_LO_1 0x168254
+
+#define mmMME2_QM_CP_MSG_BASE1_ADDR_LO_2 0x168258
+
+#define mmMME2_QM_CP_MSG_BASE1_ADDR_LO_3 0x16825C
+
+#define mmMME2_QM_CP_MSG_BASE1_ADDR_LO_4 0x168260
+
+#define mmMME2_QM_CP_MSG_BASE1_ADDR_HI_0 0x168264
+
+#define mmMME2_QM_CP_MSG_BASE1_ADDR_HI_1 0x168268
+
+#define mmMME2_QM_CP_MSG_BASE1_ADDR_HI_2 0x16826C
+
+#define mmMME2_QM_CP_MSG_BASE1_ADDR_HI_3 0x168270
+
+#define mmMME2_QM_CP_MSG_BASE1_ADDR_HI_4 0x168274
+
+#define mmMME2_QM_CP_MSG_BASE2_ADDR_LO_0 0x168278
+
+#define mmMME2_QM_CP_MSG_BASE2_ADDR_LO_1 0x16827C
+
+#define mmMME2_QM_CP_MSG_BASE2_ADDR_LO_2 0x168280
+
+#define mmMME2_QM_CP_MSG_BASE2_ADDR_LO_3 0x168284
+
+#define mmMME2_QM_CP_MSG_BASE2_ADDR_LO_4 0x168288
+
+#define mmMME2_QM_CP_MSG_BASE2_ADDR_HI_0 0x16828C
+
+#define mmMME2_QM_CP_MSG_BASE2_ADDR_HI_1 0x168290
+
+#define mmMME2_QM_CP_MSG_BASE2_ADDR_HI_2 0x168294
+
+#define mmMME2_QM_CP_MSG_BASE2_ADDR_HI_3 0x168298
+
+#define mmMME2_QM_CP_MSG_BASE2_ADDR_HI_4 0x16829C
+
+#define mmMME2_QM_CP_MSG_BASE3_ADDR_LO_0 0x1682A0
+
+#define mmMME2_QM_CP_MSG_BASE3_ADDR_LO_1 0x1682A4
+
+#define mmMME2_QM_CP_MSG_BASE3_ADDR_LO_2 0x1682A8
+
+#define mmMME2_QM_CP_MSG_BASE3_ADDR_LO_3 0x1682AC
+
+#define mmMME2_QM_CP_MSG_BASE3_ADDR_LO_4 0x1682B0
+
+#define mmMME2_QM_CP_MSG_BASE3_ADDR_HI_0 0x1682B4
+
+#define mmMME2_QM_CP_MSG_BASE3_ADDR_HI_1 0x1682B8
+
+#define mmMME2_QM_CP_MSG_BASE3_ADDR_HI_2 0x1682BC
+
+#define mmMME2_QM_CP_MSG_BASE3_ADDR_HI_3 0x1682C0
+
+#define mmMME2_QM_CP_MSG_BASE3_ADDR_HI_4 0x1682C4
+
+#define mmMME2_QM_CP_LDMA_TSIZE_OFFSET_0 0x1682C8
+
+#define mmMME2_QM_CP_LDMA_TSIZE_OFFSET_1 0x1682CC
+
+#define mmMME2_QM_CP_LDMA_TSIZE_OFFSET_2 0x1682D0
+
+#define mmMME2_QM_CP_LDMA_TSIZE_OFFSET_3 0x1682D4
+
+#define mmMME2_QM_CP_LDMA_TSIZE_OFFSET_4 0x1682D8
+
+#define mmMME2_QM_CP_LDMA_SRC_BASE_LO_OFFSET_0 0x1682E0
+
+#define mmMME2_QM_CP_LDMA_SRC_BASE_LO_OFFSET_1 0x1682E4
+
+#define mmMME2_QM_CP_LDMA_SRC_BASE_LO_OFFSET_2 0x1682E8
+
+#define mmMME2_QM_CP_LDMA_SRC_BASE_LO_OFFSET_3 0x1682EC
+
+#define mmMME2_QM_CP_LDMA_SRC_BASE_LO_OFFSET_4 0x1682F0
+
+#define mmMME2_QM_CP_LDMA_DST_BASE_LO_OFFSET_0 0x1682F4
+
+#define mmMME2_QM_CP_LDMA_DST_BASE_LO_OFFSET_1 0x1682F8
+
+#define mmMME2_QM_CP_LDMA_DST_BASE_LO_OFFSET_2 0x1682FC
+
+#define mmMME2_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 0x168300
+
+#define mmMME2_QM_CP_LDMA_DST_BASE_LO_OFFSET_4 0x168304
+
+#define mmMME2_QM_CP_FENCE0_RDATA_0 0x168308
+
+#define mmMME2_QM_CP_FENCE0_RDATA_1 0x16830C
+
+#define mmMME2_QM_CP_FENCE0_RDATA_2 0x168310
+
+#define mmMME2_QM_CP_FENCE0_RDATA_3 0x168314
+
+#define mmMME2_QM_CP_FENCE0_RDATA_4 0x168318
+
+#define mmMME2_QM_CP_FENCE1_RDATA_0 0x16831C
+
+#define mmMME2_QM_CP_FENCE1_RDATA_1 0x168320
+
+#define mmMME2_QM_CP_FENCE1_RDATA_2 0x168324
+
+#define mmMME2_QM_CP_FENCE1_RDATA_3 0x168328
+
+#define mmMME2_QM_CP_FENCE1_RDATA_4 0x16832C
+
+#define mmMME2_QM_CP_FENCE2_RDATA_0 0x168330
+
+#define mmMME2_QM_CP_FENCE2_RDATA_1 0x168334
+
+#define mmMME2_QM_CP_FENCE2_RDATA_2 0x168338
+
+#define mmMME2_QM_CP_FENCE2_RDATA_3 0x16833C
+
+#define mmMME2_QM_CP_FENCE2_RDATA_4 0x168340
+
+#define mmMME2_QM_CP_FENCE3_RDATA_0 0x168344
+
+#define mmMME2_QM_CP_FENCE3_RDATA_1 0x168348
+
+#define mmMME2_QM_CP_FENCE3_RDATA_2 0x16834C
+
+#define mmMME2_QM_CP_FENCE3_RDATA_3 0x168350
+
+#define mmMME2_QM_CP_FENCE3_RDATA_4 0x168354
+
+#define mmMME2_QM_CP_FENCE0_CNT_0 0x168358
+
+#define mmMME2_QM_CP_FENCE0_CNT_1 0x16835C
+
+#define mmMME2_QM_CP_FENCE0_CNT_2 0x168360
+
+#define mmMME2_QM_CP_FENCE0_CNT_3 0x168364
+
+#define mmMME2_QM_CP_FENCE0_CNT_4 0x168368
+
+#define mmMME2_QM_CP_FENCE1_CNT_0 0x16836C
+
+#define mmMME2_QM_CP_FENCE1_CNT_1 0x168370
+
+#define mmMME2_QM_CP_FENCE1_CNT_2 0x168374
+
+#define mmMME2_QM_CP_FENCE1_CNT_3 0x168378
+
+#define mmMME2_QM_CP_FENCE1_CNT_4 0x16837C
+
+#define mmMME2_QM_CP_FENCE2_CNT_0 0x168380
+
+#define mmMME2_QM_CP_FENCE2_CNT_1 0x168384
+
+#define mmMME2_QM_CP_FENCE2_CNT_2 0x168388
+
+#define mmMME2_QM_CP_FENCE2_CNT_3 0x16838C
+
+#define mmMME2_QM_CP_FENCE2_CNT_4 0x168390
+
+#define mmMME2_QM_CP_FENCE3_CNT_0 0x168394
+
+#define mmMME2_QM_CP_FENCE3_CNT_1 0x168398
+
+#define mmMME2_QM_CP_FENCE3_CNT_2 0x16839C
+
+#define mmMME2_QM_CP_FENCE3_CNT_3 0x1683A0
+
+#define mmMME2_QM_CP_FENCE3_CNT_4 0x1683A4
+
+#define mmMME2_QM_CP_STS_0 0x1683A8
+
+#define mmMME2_QM_CP_STS_1 0x1683AC
+
+#define mmMME2_QM_CP_STS_2 0x1683B0
+
+#define mmMME2_QM_CP_STS_3 0x1683B4
+
+#define mmMME2_QM_CP_STS_4 0x1683B8
+
+#define mmMME2_QM_CP_CURRENT_INST_LO_0 0x1683BC
+
+#define mmMME2_QM_CP_CURRENT_INST_LO_1 0x1683C0
+
+#define mmMME2_QM_CP_CURRENT_INST_LO_2 0x1683C4
+
+#define mmMME2_QM_CP_CURRENT_INST_LO_3 0x1683C8
+
+#define mmMME2_QM_CP_CURRENT_INST_LO_4 0x1683CC
+
+#define mmMME2_QM_CP_CURRENT_INST_HI_0 0x1683D0
+
+#define mmMME2_QM_CP_CURRENT_INST_HI_1 0x1683D4
+
+#define mmMME2_QM_CP_CURRENT_INST_HI_2 0x1683D8
+
+#define mmMME2_QM_CP_CURRENT_INST_HI_3 0x1683DC
+
+#define mmMME2_QM_CP_CURRENT_INST_HI_4 0x1683E0
+
+#define mmMME2_QM_CP_BARRIER_CFG_0 0x1683F4
+
+#define mmMME2_QM_CP_BARRIER_CFG_1 0x1683F8
+
+#define mmMME2_QM_CP_BARRIER_CFG_2 0x1683FC
+
+#define mmMME2_QM_CP_BARRIER_CFG_3 0x168400
+
+#define mmMME2_QM_CP_BARRIER_CFG_4 0x168404
+
+#define mmMME2_QM_CP_DBG_0_0 0x168408
+
+#define mmMME2_QM_CP_DBG_0_1 0x16840C
+
+#define mmMME2_QM_CP_DBG_0_2 0x168410
+
+#define mmMME2_QM_CP_DBG_0_3 0x168414
+
+#define mmMME2_QM_CP_DBG_0_4 0x168418
+
+#define mmMME2_QM_CP_ARUSER_31_11_0 0x16841C
+
+#define mmMME2_QM_CP_ARUSER_31_11_1 0x168420
+
+#define mmMME2_QM_CP_ARUSER_31_11_2 0x168424
+
+#define mmMME2_QM_CP_ARUSER_31_11_3 0x168428
+
+#define mmMME2_QM_CP_ARUSER_31_11_4 0x16842C
+
+#define mmMME2_QM_CP_AWUSER_31_11_0 0x168430
+
+#define mmMME2_QM_CP_AWUSER_31_11_1 0x168434
+
+#define mmMME2_QM_CP_AWUSER_31_11_2 0x168438
+
+#define mmMME2_QM_CP_AWUSER_31_11_3 0x16843C
+
+#define mmMME2_QM_CP_AWUSER_31_11_4 0x168440
+
+#define mmMME2_QM_ARB_CFG_0 0x168A00
+
+#define mmMME2_QM_ARB_CHOISE_Q_PUSH 0x168A04
+
+#define mmMME2_QM_ARB_WRR_WEIGHT_0 0x168A08
+
+#define mmMME2_QM_ARB_WRR_WEIGHT_1 0x168A0C
+
+#define mmMME2_QM_ARB_WRR_WEIGHT_2 0x168A10
+
+#define mmMME2_QM_ARB_WRR_WEIGHT_3 0x168A14
+
+#define mmMME2_QM_ARB_CFG_1 0x168A18
+
+#define mmMME2_QM_ARB_MST_AVAIL_CRED_0 0x168A20
+
+#define mmMME2_QM_ARB_MST_AVAIL_CRED_1 0x168A24
+
+#define mmMME2_QM_ARB_MST_AVAIL_CRED_2 0x168A28
+
+#define mmMME2_QM_ARB_MST_AVAIL_CRED_3 0x168A2C
+
+#define mmMME2_QM_ARB_MST_AVAIL_CRED_4 0x168A30
+
+#define mmMME2_QM_ARB_MST_AVAIL_CRED_5 0x168A34
+
+#define mmMME2_QM_ARB_MST_AVAIL_CRED_6 0x168A38
+
+#define mmMME2_QM_ARB_MST_AVAIL_CRED_7 0x168A3C
+
+#define mmMME2_QM_ARB_MST_AVAIL_CRED_8 0x168A40
+
+#define mmMME2_QM_ARB_MST_AVAIL_CRED_9 0x168A44
+
+#define mmMME2_QM_ARB_MST_AVAIL_CRED_10 0x168A48
+
+#define mmMME2_QM_ARB_MST_AVAIL_CRED_11 0x168A4C
+
+#define mmMME2_QM_ARB_MST_AVAIL_CRED_12 0x168A50
+
+#define mmMME2_QM_ARB_MST_AVAIL_CRED_13 0x168A54
+
+#define mmMME2_QM_ARB_MST_AVAIL_CRED_14 0x168A58
+
+#define mmMME2_QM_ARB_MST_AVAIL_CRED_15 0x168A5C
+
+#define mmMME2_QM_ARB_MST_AVAIL_CRED_16 0x168A60
+
+#define mmMME2_QM_ARB_MST_AVAIL_CRED_17 0x168A64
+
+#define mmMME2_QM_ARB_MST_AVAIL_CRED_18 0x168A68
+
+#define mmMME2_QM_ARB_MST_AVAIL_CRED_19 0x168A6C
+
+#define mmMME2_QM_ARB_MST_AVAIL_CRED_20 0x168A70
+
+#define mmMME2_QM_ARB_MST_AVAIL_CRED_21 0x168A74
+
+#define mmMME2_QM_ARB_MST_AVAIL_CRED_22 0x168A78
+
+#define mmMME2_QM_ARB_MST_AVAIL_CRED_23 0x168A7C
+
+#define mmMME2_QM_ARB_MST_AVAIL_CRED_24 0x168A80
+
+#define mmMME2_QM_ARB_MST_AVAIL_CRED_25 0x168A84
+
+#define mmMME2_QM_ARB_MST_AVAIL_CRED_26 0x168A88
+
+#define mmMME2_QM_ARB_MST_AVAIL_CRED_27 0x168A8C
+
+#define mmMME2_QM_ARB_MST_AVAIL_CRED_28 0x168A90
+
+#define mmMME2_QM_ARB_MST_AVAIL_CRED_29 0x168A94
+
+#define mmMME2_QM_ARB_MST_AVAIL_CRED_30 0x168A98
+
+#define mmMME2_QM_ARB_MST_AVAIL_CRED_31 0x168A9C
+
+#define mmMME2_QM_ARB_MST_CRED_INC 0x168AA0
+
+#define mmMME2_QM_ARB_MST_CHOISE_PUSH_OFST_0 0x168AA4
+
+#define mmMME2_QM_ARB_MST_CHOISE_PUSH_OFST_1 0x168AA8
+
+#define mmMME2_QM_ARB_MST_CHOISE_PUSH_OFST_2 0x168AAC
+
+#define mmMME2_QM_ARB_MST_CHOISE_PUSH_OFST_3 0x168AB0
+
+#define mmMME2_QM_ARB_MST_CHOISE_PUSH_OFST_4 0x168AB4
+
+#define mmMME2_QM_ARB_MST_CHOISE_PUSH_OFST_5 0x168AB8
+
+#define mmMME2_QM_ARB_MST_CHOISE_PUSH_OFST_6 0x168ABC
+
+#define mmMME2_QM_ARB_MST_CHOISE_PUSH_OFST_7 0x168AC0
+
+#define mmMME2_QM_ARB_MST_CHOISE_PUSH_OFST_8 0x168AC4
+
+#define mmMME2_QM_ARB_MST_CHOISE_PUSH_OFST_9 0x168AC8
+
+#define mmMME2_QM_ARB_MST_CHOISE_PUSH_OFST_10 0x168ACC
+
+#define mmMME2_QM_ARB_MST_CHOISE_PUSH_OFST_11 0x168AD0
+
+#define mmMME2_QM_ARB_MST_CHOISE_PUSH_OFST_12 0x168AD4
+
+#define mmMME2_QM_ARB_MST_CHOISE_PUSH_OFST_13 0x168AD8
+
+#define mmMME2_QM_ARB_MST_CHOISE_PUSH_OFST_14 0x168ADC
+
+#define mmMME2_QM_ARB_MST_CHOISE_PUSH_OFST_15 0x168AE0
+
+#define mmMME2_QM_ARB_MST_CHOISE_PUSH_OFST_16 0x168AE4
+
+#define mmMME2_QM_ARB_MST_CHOISE_PUSH_OFST_17 0x168AE8
+
+#define mmMME2_QM_ARB_MST_CHOISE_PUSH_OFST_18 0x168AEC
+
+#define mmMME2_QM_ARB_MST_CHOISE_PUSH_OFST_19 0x168AF0
+
+#define mmMME2_QM_ARB_MST_CHOISE_PUSH_OFST_20 0x168AF4
+
+#define mmMME2_QM_ARB_MST_CHOISE_PUSH_OFST_21 0x168AF8
+
+#define mmMME2_QM_ARB_MST_CHOISE_PUSH_OFST_22 0x168AFC
+
+#define mmMME2_QM_ARB_MST_CHOISE_PUSH_OFST_23 0x168B00
+
+#define mmMME2_QM_ARB_MST_CHOISE_PUSH_OFST_24 0x168B04
+
+#define mmMME2_QM_ARB_MST_CHOISE_PUSH_OFST_25 0x168B08
+
+#define mmMME2_QM_ARB_MST_CHOISE_PUSH_OFST_26 0x168B0C
+
+#define mmMME2_QM_ARB_MST_CHOISE_PUSH_OFST_27 0x168B10
+
+#define mmMME2_QM_ARB_MST_CHOISE_PUSH_OFST_28 0x168B14
+
+#define mmMME2_QM_ARB_MST_CHOISE_PUSH_OFST_29 0x168B18
+
+#define mmMME2_QM_ARB_MST_CHOISE_PUSH_OFST_30 0x168B1C
+
+#define mmMME2_QM_ARB_MST_CHOISE_PUSH_OFST_31 0x168B20
+
+#define mmMME2_QM_ARB_SLV_MASTER_INC_CRED_OFST 0x168B28
+
+#define mmMME2_QM_ARB_MST_SLAVE_EN 0x168B2C
+
+#define mmMME2_QM_ARB_MST_QUIET_PER 0x168B34
+
+#define mmMME2_QM_ARB_SLV_CHOISE_WDT 0x168B38
+
+#define mmMME2_QM_ARB_SLV_ID 0x168B3C
+
+#define mmMME2_QM_ARB_MSG_MAX_INFLIGHT 0x168B44
+
+#define mmMME2_QM_ARB_MSG_AWUSER_31_11 0x168B48
+
+#define mmMME2_QM_ARB_MSG_AWUSER_SEC_PROP 0x168B4C
+
+#define mmMME2_QM_ARB_MSG_AWUSER_NON_SEC_PROP 0x168B50
+
+#define mmMME2_QM_ARB_BASE_LO 0x168B54
+
+#define mmMME2_QM_ARB_BASE_HI 0x168B58
+
+#define mmMME2_QM_ARB_STATE_STS 0x168B80
+
+#define mmMME2_QM_ARB_CHOISE_FULLNESS_STS 0x168B84
+
+#define mmMME2_QM_ARB_MSG_STS 0x168B88
+
+#define mmMME2_QM_ARB_SLV_CHOISE_Q_HEAD 0x168B8C
+
+#define mmMME2_QM_ARB_ERR_CAUSE 0x168B9C
+
+#define mmMME2_QM_ARB_ERR_MSG_EN 0x168BA0
+
+#define mmMME2_QM_ARB_ERR_STS_DRP 0x168BA8
+
+#define mmMME2_QM_ARB_MST_CRED_STS_0 0x168BB0
+
+#define mmMME2_QM_ARB_MST_CRED_STS_1 0x168BB4
+
+#define mmMME2_QM_ARB_MST_CRED_STS_2 0x168BB8
+
+#define mmMME2_QM_ARB_MST_CRED_STS_3 0x168BBC
+
+#define mmMME2_QM_ARB_MST_CRED_STS_4 0x168BC0
+
+#define mmMME2_QM_ARB_MST_CRED_STS_5 0x168BC4
+
+#define mmMME2_QM_ARB_MST_CRED_STS_6 0x168BC8
+
+#define mmMME2_QM_ARB_MST_CRED_STS_7 0x168BCC
+
+#define mmMME2_QM_ARB_MST_CRED_STS_8 0x168BD0
+
+#define mmMME2_QM_ARB_MST_CRED_STS_9 0x168BD4
+
+#define mmMME2_QM_ARB_MST_CRED_STS_10 0x168BD8
+
+#define mmMME2_QM_ARB_MST_CRED_STS_11 0x168BDC
+
+#define mmMME2_QM_ARB_MST_CRED_STS_12 0x168BE0
+
+#define mmMME2_QM_ARB_MST_CRED_STS_13 0x168BE4
+
+#define mmMME2_QM_ARB_MST_CRED_STS_14 0x168BE8
+
+#define mmMME2_QM_ARB_MST_CRED_STS_15 0x168BEC
+
+#define mmMME2_QM_ARB_MST_CRED_STS_16 0x168BF0
+
+#define mmMME2_QM_ARB_MST_CRED_STS_17 0x168BF4
+
+#define mmMME2_QM_ARB_MST_CRED_STS_18 0x168BF8
+
+#define mmMME2_QM_ARB_MST_CRED_STS_19 0x168BFC
+
+#define mmMME2_QM_ARB_MST_CRED_STS_20 0x168C00
+
+#define mmMME2_QM_ARB_MST_CRED_STS_21 0x168C04
+
+#define mmMME2_QM_ARB_MST_CRED_STS_22 0x168C08
+
+#define mmMME2_QM_ARB_MST_CRED_STS_23 0x168C0C
+
+#define mmMME2_QM_ARB_MST_CRED_STS_24 0x168C10
+
+#define mmMME2_QM_ARB_MST_CRED_STS_25 0x168C14
+
+#define mmMME2_QM_ARB_MST_CRED_STS_26 0x168C18
+
+#define mmMME2_QM_ARB_MST_CRED_STS_27 0x168C1C
+
+#define mmMME2_QM_ARB_MST_CRED_STS_28 0x168C20
+
+#define mmMME2_QM_ARB_MST_CRED_STS_29 0x168C24
+
+#define mmMME2_QM_ARB_MST_CRED_STS_30 0x168C28
+
+#define mmMME2_QM_ARB_MST_CRED_STS_31 0x168C2C
+
+#define mmMME2_QM_CGM_CFG 0x168C70
+
+#define mmMME2_QM_CGM_STS 0x168C74
+
+#define mmMME2_QM_CGM_CFG1 0x168C78
+
+#define mmMME2_QM_LOCAL_RANGE_BASE 0x168C80
+
+#define mmMME2_QM_LOCAL_RANGE_SIZE 0x168C84
+
+#define mmMME2_QM_CSMR_STRICT_PRIO_CFG 0x168C90
+
+#define mmMME2_QM_HBW_RD_RATE_LIM_CFG_1 0x168C94
+
+#define mmMME2_QM_LBW_WR_RATE_LIM_CFG_0 0x168C98
+
+#define mmMME2_QM_LBW_WR_RATE_LIM_CFG_1 0x168C9C
+
+#define mmMME2_QM_HBW_RD_RATE_LIM_CFG_0 0x168CA0
+
+#define mmMME2_QM_GLBL_AXCACHE 0x168CA4
+
+#define mmMME2_QM_IND_GW_APB_CFG 0x168CB0
+
+#define mmMME2_QM_IND_GW_APB_WDATA 0x168CB4
+
+#define mmMME2_QM_IND_GW_APB_RDATA 0x168CB8
+
+#define mmMME2_QM_IND_GW_APB_STATUS 0x168CBC
+
+#define mmMME2_QM_GLBL_ERR_ADDR_LO 0x168CD0
+
+#define mmMME2_QM_GLBL_ERR_ADDR_HI 0x168CD4
+
+#define mmMME2_QM_GLBL_ERR_WDATA 0x168CD8
+
+#define mmMME2_QM_GLBL_MEM_INIT_BUSY 0x168D00
+
+#endif /* ASIC_REG_MME2_QM_REGS_H_ */
diff --git a/drivers/accel/habanalabs/include/gaudi/asic_reg/mme3_ctrl_regs.h b/drivers/accel/habanalabs/include/gaudi/asic_reg/mme3_ctrl_regs.h
new file mode 100644
index 0000000000..36f6edc72e
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi/asic_reg/mme3_ctrl_regs.h
@@ -0,0 +1,1456 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2016-2018 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ ** DO NOT EDIT BELOW **
+ ************************************/
+
+#ifndef ASIC_REG_MME3_CTRL_REGS_H_
+#define ASIC_REG_MME3_CTRL_REGS_H_
+
+/*
+ *****************************************
+ * MME3_CTRL (Prototype: MME)
+ *****************************************
+ */
+
+#define mmMME3_CTRL_ARCH_STATUS 0x1E0000
+
+#define mmMME3_CTRL_ARCH_BASE_ADDR_HIGH_S 0x1E0008
+
+#define mmMME3_CTRL_ARCH_BASE_ADDR_HIGH_L 0x1E000C
+
+#define mmMME3_CTRL_ARCH_BASE_ADDR_HIGH_O 0x1E0010
+
+#define mmMME3_CTRL_ARCH_BASE_ADDR_LOW_S 0x1E0014
+
+#define mmMME3_CTRL_ARCH_BASE_ADDR_LOW_L 0x1E0018
+
+#define mmMME3_CTRL_ARCH_BASE_ADDR_LOW_O 0x1E001C
+
+#define mmMME3_CTRL_ARCH_HEADER_LOW 0x1E0020
+
+#define mmMME3_CTRL_ARCH_HEADER_HIGH 0x1E0024
+
+#define mmMME3_CTRL_ARCH_CONV_KERNEL_SIZE_MINUS_1 0x1E0028
+
+#define mmMME3_CTRL_ARCH_CONV_ASSOCIATED_DIMS_LOW 0x1E002C
+
+#define mmMME3_CTRL_ARCH_CONV_ASSOCIATED_DIMS_HIGH 0x1E0030
+
+#define mmMME3_CTRL_ARCH_NUM_ITERATIONS_MINUS_1 0x1E0034
+
+#define mmMME3_CTRL_ARCH_OUTER_LOOP 0x1E0038
+
+#define mmMME3_CTRL_ARCH_TENSOR_S_VALID_ELEMENTS_0 0x1E003C
+
+#define mmMME3_CTRL_ARCH_TENSOR_S_VALID_ELEMENTS_1 0x1E0040
+
+#define mmMME3_CTRL_ARCH_TENSOR_S_VALID_ELEMENTS_2 0x1E0044
+
+#define mmMME3_CTRL_ARCH_TENSOR_S_VALID_ELEMENTS_3 0x1E0048
+
+#define mmMME3_CTRL_ARCH_TENSOR_S_VALID_ELEMENTS_4 0x1E004C
+
+#define mmMME3_CTRL_ARCH_TENSOR_S_LOOP_STRIDE_0 0x1E0050
+
+#define mmMME3_CTRL_ARCH_TENSOR_S_LOOP_STRIDE_1 0x1E0054
+
+#define mmMME3_CTRL_ARCH_TENSOR_S_LOOP_STRIDE_2 0x1E0058
+
+#define mmMME3_CTRL_ARCH_TENSOR_S_LOOP_STRIDE_3 0x1E005C
+
+#define mmMME3_CTRL_ARCH_TENSOR_S_LOOP_STRIDE_4 0x1E0060
+
+#define mmMME3_CTRL_ARCH_TENSOR_S_ROI_SIZE_0 0x1E0064
+
+#define mmMME3_CTRL_ARCH_TENSOR_S_ROI_SIZE_1 0x1E0068
+
+#define mmMME3_CTRL_ARCH_TENSOR_S_ROI_SIZE_2 0x1E006C
+
+#define mmMME3_CTRL_ARCH_TENSOR_S_ROI_SIZE_3 0x1E0070
+
+#define mmMME3_CTRL_ARCH_TENSOR_S_SPATIAL_STRIDES_0 0x1E0074
+
+#define mmMME3_CTRL_ARCH_TENSOR_S_SPATIAL_STRIDES_1 0x1E0078
+
+#define mmMME3_CTRL_ARCH_TENSOR_S_SPATIAL_STRIDES_2 0x1E007C
+
+#define mmMME3_CTRL_ARCH_TENSOR_S_SPATIAL_STRIDES_3 0x1E0080
+
+#define mmMME3_CTRL_ARCH_TENSOR_S_SPATIAL_SIZE_MINUS_1 0x1E0084
+
+#define mmMME3_CTRL_ARCH_AGU_S_ROI_BASE_OFFSET_0 0x1E0088
+
+#define mmMME3_CTRL_ARCH_AGU_S_ROI_BASE_OFFSET_1 0x1E008C
+
+#define mmMME3_CTRL_ARCH_AGU_S_ROI_BASE_OFFSET_2 0x1E0090
+
+#define mmMME3_CTRL_ARCH_AGU_S_ROI_BASE_OFFSET_3 0x1E0094
+
+#define mmMME3_CTRL_ARCH_AGU_S_ROI_BASE_OFFSET_4 0x1E0098
+
+#define mmMME3_CTRL_ARCH_AGU_S_START_OFFSET_0 0x1E009C
+
+#define mmMME3_CTRL_ARCH_AGU_S_START_OFFSET_1 0x1E00A0
+
+#define mmMME3_CTRL_ARCH_AGU_S_START_OFFSET_2 0x1E00A4
+
+#define mmMME3_CTRL_ARCH_AGU_S_START_OFFSET_3 0x1E00A8
+
+#define mmMME3_CTRL_ARCH_TENSOR_L_VALID_ELEMENTS_0 0x1E00AC
+
+#define mmMME3_CTRL_ARCH_TENSOR_L_VALID_ELEMENTS_1 0x1E00B0
+
+#define mmMME3_CTRL_ARCH_TENSOR_L_VALID_ELEMENTS_2 0x1E00B4
+
+#define mmMME3_CTRL_ARCH_TENSOR_L_VALID_ELEMENTS_3 0x1E00B8
+
+#define mmMME3_CTRL_ARCH_TENSOR_L_VALID_ELEMENTS_4 0x1E00BC
+
+#define mmMME3_CTRL_ARCH_TENSOR_L_LOOP_STRIDE_0 0x1E00C0
+
+#define mmMME3_CTRL_ARCH_TENSOR_L_LOOP_STRIDE_1 0x1E00C4
+
+#define mmMME3_CTRL_ARCH_TENSOR_L_LOOP_STRIDE_2 0x1E00C8
+
+#define mmMME3_CTRL_ARCH_TENSOR_L_LOOP_STRIDE_3 0x1E00CC
+
+#define mmMME3_CTRL_ARCH_TENSOR_L_LOOP_STRIDE_4 0x1E00D0
+
+#define mmMME3_CTRL_ARCH_TENSOR_L_ROI_SIZE_0 0x1E00D4
+
+#define mmMME3_CTRL_ARCH_TENSOR_L_ROI_SIZE_1 0x1E00D8
+
+#define mmMME3_CTRL_ARCH_TENSOR_L_ROI_SIZE_2 0x1E00DC
+
+#define mmMME3_CTRL_ARCH_TENSOR_L_ROI_SIZE_3 0x1E00E0
+
+#define mmMME3_CTRL_ARCH_TENSOR_L_SPATIAL_STRIDES_0 0x1E00E4
+
+#define mmMME3_CTRL_ARCH_TENSOR_L_SPATIAL_STRIDES_1 0x1E00E8
+
+#define mmMME3_CTRL_ARCH_TENSOR_L_SPATIAL_STRIDES_2 0x1E00EC
+
+#define mmMME3_CTRL_ARCH_TENSOR_L_SPATIAL_STRIDES_3 0x1E00F0
+
+#define mmMME3_CTRL_ARCH_TENSOR_L_SPATIAL_SIZE_MINUS_1 0x1E00F4
+
+#define mmMME3_CTRL_ARCH_AGU_L_LOCAL_ROI_BASE_OFFSET_0 0x1E00F8
+
+#define mmMME3_CTRL_ARCH_AGU_L_LOCAL_ROI_BASE_OFFSET_1 0x1E00FC
+
+#define mmMME3_CTRL_ARCH_AGU_L_LOCAL_ROI_BASE_OFFSET_2 0x1E0100
+
+#define mmMME3_CTRL_ARCH_AGU_L_LOCAL_ROI_BASE_OFFSET_3 0x1E0104
+
+#define mmMME3_CTRL_ARCH_AGU_L_LOCAL_ROI_BASE_OFFSET_4 0x1E0108
+
+#define mmMME3_CTRL_ARCH_AGU_L_LOCAL_START_OFFSET_0 0x1E010C
+
+#define mmMME3_CTRL_ARCH_AGU_L_LOCAL_START_OFFSET_1 0x1E0110
+
+#define mmMME3_CTRL_ARCH_AGU_L_LOCAL_START_OFFSET_2 0x1E0114
+
+#define mmMME3_CTRL_ARCH_AGU_L_LOCAL_START_OFFSET_3 0x1E0118
+
+#define mmMME3_CTRL_ARCH_AGU_L_REMOTE_ROI_BASE_OFFSET_0 0x1E011C
+
+#define mmMME3_CTRL_ARCH_AGU_L_REMOTE_ROI_BASE_OFFSET_1 0x1E0120
+
+#define mmMME3_CTRL_ARCH_AGU_L_REMOTE_ROI_BASE_OFFSET_2 0x1E0124
+
+#define mmMME3_CTRL_ARCH_AGU_L_REMOTE_ROI_BASE_OFFSET_3 0x1E0128
+
+#define mmMME3_CTRL_ARCH_AGU_L_REMOTE_ROI_BASE_OFFSET_4 0x1E012C
+
+#define mmMME3_CTRL_ARCH_AGU_L_REMOTE_START_OFFSET_0 0x1E0130
+
+#define mmMME3_CTRL_ARCH_AGU_L_REMOTE_START_OFFSET_1 0x1E0134
+
+#define mmMME3_CTRL_ARCH_AGU_L_REMOTE_START_OFFSET_2 0x1E0138
+
+#define mmMME3_CTRL_ARCH_AGU_L_REMOTE_START_OFFSET_3 0x1E013C
+
+#define mmMME3_CTRL_ARCH_TENSOR_O_VALID_ELEMENTS_0 0x1E0140
+
+#define mmMME3_CTRL_ARCH_TENSOR_O_VALID_ELEMENTS_1 0x1E0144
+
+#define mmMME3_CTRL_ARCH_TENSOR_O_VALID_ELEMENTS_2 0x1E0148
+
+#define mmMME3_CTRL_ARCH_TENSOR_O_VALID_ELEMENTS_3 0x1E014C
+
+#define mmMME3_CTRL_ARCH_TENSOR_O_VALID_ELEMENTS_4 0x1E0150
+
+#define mmMME3_CTRL_ARCH_TENSOR_O_LOOP_STRIDE_0 0x1E0154
+
+#define mmMME3_CTRL_ARCH_TENSOR_O_LOOP_STRIDE_1 0x1E0158
+
+#define mmMME3_CTRL_ARCH_TENSOR_O_LOOP_STRIDE_2 0x1E015C
+
+#define mmMME3_CTRL_ARCH_TENSOR_O_LOOP_STRIDE_3 0x1E0160
+
+#define mmMME3_CTRL_ARCH_TENSOR_O_LOOP_STRIDE_4 0x1E0164
+
+#define mmMME3_CTRL_ARCH_TENSOR_O_ROI_SIZE_0 0x1E0168
+
+#define mmMME3_CTRL_ARCH_TENSOR_O_ROI_SIZE_1 0x1E016C
+
+#define mmMME3_CTRL_ARCH_TENSOR_O_ROI_SIZE_2 0x1E0170
+
+#define mmMME3_CTRL_ARCH_TENSOR_O_ROI_SIZE_3 0x1E0174
+
+#define mmMME3_CTRL_ARCH_TENSOR_O_SPATIAL_STRIDES_0 0x1E0178
+
+#define mmMME3_CTRL_ARCH_TENSOR_O_SPATIAL_STRIDES_1 0x1E017C
+
+#define mmMME3_CTRL_ARCH_TENSOR_O_SPATIAL_STRIDES_2 0x1E0180
+
+#define mmMME3_CTRL_ARCH_TENSOR_O_SPATIAL_STRIDES_3 0x1E0184
+
+#define mmMME3_CTRL_ARCH_TENSOR_O_SPATIAL_SIZE_MINUS_1 0x1E0188
+
+#define mmMME3_CTRL_ARCH_AGU_O_LOCAL_ROI_BASE_OFFSET_0 0x1E018C
+
+#define mmMME3_CTRL_ARCH_AGU_O_LOCAL_ROI_BASE_OFFSET_1 0x1E0190
+
+#define mmMME3_CTRL_ARCH_AGU_O_LOCAL_ROI_BASE_OFFSET_2 0x1E0194
+
+#define mmMME3_CTRL_ARCH_AGU_O_LOCAL_ROI_BASE_OFFSET_3 0x1E0198
+
+#define mmMME3_CTRL_ARCH_AGU_O_LOCAL_ROI_BASE_OFFSET_4 0x1E019C
+
+#define mmMME3_CTRL_ARCH_AGU_O_LOCAL_START_OFFSET_0 0x1E01A0
+
+#define mmMME3_CTRL_ARCH_AGU_O_LOCAL_START_OFFSET_1 0x1E01A4
+
+#define mmMME3_CTRL_ARCH_AGU_O_LOCAL_START_OFFSET_2 0x1E01A8
+
+#define mmMME3_CTRL_ARCH_AGU_O_LOCAL_START_OFFSET_3 0x1E01AC
+
+#define mmMME3_CTRL_ARCH_AGU_O_REMOTE_ROI_BASE_OFFSET_0 0x1E01B0
+
+#define mmMME3_CTRL_ARCH_AGU_O_REMOTE_ROI_BASE_OFFSET_1 0x1E01B4
+
+#define mmMME3_CTRL_ARCH_AGU_O_REMOTE_ROI_BASE_OFFSET_2 0x1E01B8
+
+#define mmMME3_CTRL_ARCH_AGU_O_REMOTE_ROI_BASE_OFFSET_3 0x1E01BC
+
+#define mmMME3_CTRL_ARCH_AGU_O_REMOTE_ROI_BASE_OFFSET_4 0x1E01C0
+
+#define mmMME3_CTRL_ARCH_AGU_O_REMOTE_START_OFFSET_0 0x1E01C4
+
+#define mmMME3_CTRL_ARCH_AGU_O_REMOTE_START_OFFSET_1 0x1E01C8
+
+#define mmMME3_CTRL_ARCH_AGU_O_REMOTE_START_OFFSET_2 0x1E01CC
+
+#define mmMME3_CTRL_ARCH_AGU_O_REMOTE_START_OFFSET_3 0x1E01D0
+
+#define mmMME3_CTRL_ARCH_DESC_SB_REPEAT 0x1E01D4
+
+#define mmMME3_CTRL_ARCH_DESC_RATE_LIMITER 0x1E01D8
+
+#define mmMME3_CTRL_ARCH_DESC_SYNC_OBJECT_ADDR_LOW_LOCAL 0x1E01DC
+
+#define mmMME3_CTRL_ARCH_DESC_SYNC_OBJECT_ADDR_LOW_REMOTE 0x1E01E0
+
+#define mmMME3_CTRL_ARCH_DESC_SYNC_OBJECT_ADDR_HIGH 0x1E01E4
+
+#define mmMME3_CTRL_ARCH_DESC_SYNC_OBJECT_DATA 0x1E01E8
+
+#define mmMME3_CTRL_ARCH_DESC_AXI_USER_DATA 0x1E01EC
+
+#define mmMME3_CTRL_ARCH_DESC_PERF_EVT_S 0x1E01F0
+
+#define mmMME3_CTRL_ARCH_DESC_PERF_EVT_L_LOCAL 0x1E01F4
+
+#define mmMME3_CTRL_ARCH_DESC_PERF_EVT_L_REMOTE 0x1E01F8
+
+#define mmMME3_CTRL_ARCH_DESC_PERF_EVT_O_LOCAL 0x1E01FC
+
+#define mmMME3_CTRL_ARCH_DESC_PERF_EVT_O_REMOTE 0x1E0200
+
+#define mmMME3_CTRL_ARCH_DESC_PADDING_VALUE_S 0x1E0204
+
+#define mmMME3_CTRL_ARCH_DESC_PADDING_VALUE_L 0x1E0208
+
+#define mmMME3_CTRL_ARCH_DESC_META_DATA_AGU_S 0x1E020C
+
+#define mmMME3_CTRL_ARCH_DESC_META_DATA_AGU_L_LOCAL 0x1E0210
+
+#define mmMME3_CTRL_ARCH_DESC_META_DATA_AGU_L_REMOTE 0x1E0214
+
+#define mmMME3_CTRL_ARCH_DESC_META_DATA_AGU_O_LOCAL 0x1E0218
+
+#define mmMME3_CTRL_ARCH_DESC_META_DATA_AGU_O_REMOTE 0x1E021C
+
+#define mmMME3_CTRL_ARCH_DESC_PCU_RL_SATURATION 0x1E0220
+
+#define mmMME3_CTRL_ARCH_DESC_DUMMY 0x1E0224
+
+#define mmMME3_CTRL_CMD 0x1E0280
+
+#define mmMME3_CTRL_STATUS1 0x1E0284
+
+#define mmMME3_CTRL_RESET 0x1E0288
+
+#define mmMME3_CTRL_QM_STALL 0x1E028C
+
+#define mmMME3_CTRL_SYNC_OBJECT_FIFO_TH 0x1E0290
+
+#define mmMME3_CTRL_EUS_ROLLUP_CNT_ADD 0x1E0294
+
+#define mmMME3_CTRL_INTR_CAUSE 0x1E0298
+
+#define mmMME3_CTRL_INTR_MASK 0x1E029C
+
+#define mmMME3_CTRL_LOG_SHADOW 0x1E02A0
+
+#define mmMME3_CTRL_PCU_RL_DESC0 0x1E02A4
+
+#define mmMME3_CTRL_PCU_RL_TOKEN_UPDATE 0x1E02A8
+
+#define mmMME3_CTRL_PCU_RL_TH 0x1E02AC
+
+#define mmMME3_CTRL_PCU_RL_MIN 0x1E02B0
+
+#define mmMME3_CTRL_PCU_RL_CTRL_EN 0x1E02B4
+
+#define mmMME3_CTRL_PCU_RL_HISTORY_LOG_SIZE 0x1E02B8
+
+#define mmMME3_CTRL_PCU_DUMMY_A_BF16 0x1E02BC
+
+#define mmMME3_CTRL_PCU_DUMMY_B_BF16 0x1E02C0
+
+#define mmMME3_CTRL_PCU_DUMMY_A_FP32_ODD 0x1E02C4
+
+#define mmMME3_CTRL_PCU_DUMMY_A_FP32_EVEN 0x1E02C8
+
+#define mmMME3_CTRL_PCU_DUMMY_B_FP32_ODD 0x1E02CC
+
+#define mmMME3_CTRL_PCU_DUMMY_B_FP32_EVEN 0x1E02D0
+
+#define mmMME3_CTRL_PROT 0x1E02D4
+
+#define mmMME3_CTRL_EU_POWER_SAVE_DISABLE 0x1E02D8
+
+#define mmMME3_CTRL_CS_DBG_BLOCK_ID 0x1E02DC
+
+#define mmMME3_CTRL_CS_DBG_STATUS_DROP_CNT 0x1E02E0
+
+#define mmMME3_CTRL_TE_CLOSE_CGATE 0x1E02E4
+
+#define mmMME3_CTRL_AGU_SM_INFLIGHT_CNTR 0x1E02E8
+
+#define mmMME3_CTRL_AGU_SM_TOTAL_CNTR 0x1E02EC
+
+#define mmMME3_CTRL_EZSYNC_OUT_CREDIT 0x1E02F0
+
+#define mmMME3_CTRL_PCU_RL_SAT_SEC 0x1E02F4
+
+#define mmMME3_CTRL_AGU_SYNC_MSG_AXI_USER 0x1E02F8
+
+#define mmMME3_CTRL_QM_SLV_LBW_CLK_EN 0x1E02FC
+
+#define mmMME3_CTRL_SHADOW_0_STATUS 0x1E0400
+
+#define mmMME3_CTRL_SHADOW_0_BASE_ADDR_HIGH_S 0x1E0408
+
+#define mmMME3_CTRL_SHADOW_0_BASE_ADDR_HIGH_L 0x1E040C
+
+#define mmMME3_CTRL_SHADOW_0_BASE_ADDR_HIGH_O 0x1E0410
+
+#define mmMME3_CTRL_SHADOW_0_BASE_ADDR_LOW_S 0x1E0414
+
+#define mmMME3_CTRL_SHADOW_0_BASE_ADDR_LOW_L 0x1E0418
+
+#define mmMME3_CTRL_SHADOW_0_BASE_ADDR_LOW_O 0x1E041C
+
+#define mmMME3_CTRL_SHADOW_0_HEADER_LOW 0x1E0420
+
+#define mmMME3_CTRL_SHADOW_0_HEADER_HIGH 0x1E0424
+
+#define mmMME3_CTRL_SHADOW_0_CONV_KERNEL_SIZE_MINUS_1 0x1E0428
+
+#define mmMME3_CTRL_SHADOW_0_CONV_ASSOCIATED_DIMS_LOW 0x1E042C
+
+#define mmMME3_CTRL_SHADOW_0_CONV_ASSOCIATED_DIMS_HIGH 0x1E0430
+
+#define mmMME3_CTRL_SHADOW_0_NUM_ITERATIONS_MINUS_1 0x1E0434
+
+#define mmMME3_CTRL_SHADOW_0_OUTER_LOOP 0x1E0438
+
+#define mmMME3_CTRL_SHADOW_0_TENSOR_S_VALID_ELEMENTS_0 0x1E043C
+
+#define mmMME3_CTRL_SHADOW_0_TENSOR_S_VALID_ELEMENTS_1 0x1E0440
+
+#define mmMME3_CTRL_SHADOW_0_TENSOR_S_VALID_ELEMENTS_2 0x1E0444
+
+#define mmMME3_CTRL_SHADOW_0_TENSOR_S_VALID_ELEMENTS_3 0x1E0448
+
+#define mmMME3_CTRL_SHADOW_0_TENSOR_S_VALID_ELEMENTS_4 0x1E044C
+
+#define mmMME3_CTRL_SHADOW_0_TENSOR_S_LOOP_STRIDE_0 0x1E0450
+
+#define mmMME3_CTRL_SHADOW_0_TENSOR_S_LOOP_STRIDE_1 0x1E0454
+
+#define mmMME3_CTRL_SHADOW_0_TENSOR_S_LOOP_STRIDE_2 0x1E0458
+
+#define mmMME3_CTRL_SHADOW_0_TENSOR_S_LOOP_STRIDE_3 0x1E045C
+
+#define mmMME3_CTRL_SHADOW_0_TENSOR_S_LOOP_STRIDE_4 0x1E0460
+
+#define mmMME3_CTRL_SHADOW_0_TENSOR_S_ROI_SIZE_0 0x1E0464
+
+#define mmMME3_CTRL_SHADOW_0_TENSOR_S_ROI_SIZE_1 0x1E0468
+
+#define mmMME3_CTRL_SHADOW_0_TENSOR_S_ROI_SIZE_2 0x1E046C
+
+#define mmMME3_CTRL_SHADOW_0_TENSOR_S_ROI_SIZE_3 0x1E0470
+
+#define mmMME3_CTRL_SHADOW_0_TENSOR_S_SPATIAL_STRIDES_0 0x1E0474
+
+#define mmMME3_CTRL_SHADOW_0_TENSOR_S_SPATIAL_STRIDES_1 0x1E0478
+
+#define mmMME3_CTRL_SHADOW_0_TENSOR_S_SPATIAL_STRIDES_2 0x1E047C
+
+#define mmMME3_CTRL_SHADOW_0_TENSOR_S_SPATIAL_STRIDES_3 0x1E0480
+
+#define mmMME3_CTRL_SHADOW_0_TENSOR_S_SPATIAL_SIZE_MINUS_1 0x1E0484
+
+#define mmMME3_CTRL_SHADOW_0_AGU_S_ROI_BASE_OFFSET_0 0x1E0488
+
+#define mmMME3_CTRL_SHADOW_0_AGU_S_ROI_BASE_OFFSET_1 0x1E048C
+
+#define mmMME3_CTRL_SHADOW_0_AGU_S_ROI_BASE_OFFSET_2 0x1E0490
+
+#define mmMME3_CTRL_SHADOW_0_AGU_S_ROI_BASE_OFFSET_3 0x1E0494
+
+#define mmMME3_CTRL_SHADOW_0_AGU_S_ROI_BASE_OFFSET_4 0x1E0498
+
+#define mmMME3_CTRL_SHADOW_0_AGU_S_START_OFFSET_0 0x1E049C
+
+#define mmMME3_CTRL_SHADOW_0_AGU_S_START_OFFSET_1 0x1E04A0
+
+#define mmMME3_CTRL_SHADOW_0_AGU_S_START_OFFSET_2 0x1E04A4
+
+#define mmMME3_CTRL_SHADOW_0_AGU_S_START_OFFSET_3 0x1E04A8
+
+#define mmMME3_CTRL_SHADOW_0_TENSOR_L_VALID_ELEMENTS_0 0x1E04AC
+
+#define mmMME3_CTRL_SHADOW_0_TENSOR_L_VALID_ELEMENTS_1 0x1E04B0
+
+#define mmMME3_CTRL_SHADOW_0_TENSOR_L_VALID_ELEMENTS_2 0x1E04B4
+
+#define mmMME3_CTRL_SHADOW_0_TENSOR_L_VALID_ELEMENTS_3 0x1E04B8
+
+#define mmMME3_CTRL_SHADOW_0_TENSOR_L_VALID_ELEMENTS_4 0x1E04BC
+
+#define mmMME3_CTRL_SHADOW_0_TENSOR_L_LOOP_STRIDE_0 0x1E04C0
+
+#define mmMME3_CTRL_SHADOW_0_TENSOR_L_LOOP_STRIDE_1 0x1E04C4
+
+#define mmMME3_CTRL_SHADOW_0_TENSOR_L_LOOP_STRIDE_2 0x1E04C8
+
+#define mmMME3_CTRL_SHADOW_0_TENSOR_L_LOOP_STRIDE_3 0x1E04CC
+
+#define mmMME3_CTRL_SHADOW_0_TENSOR_L_LOOP_STRIDE_4 0x1E04D0
+
+#define mmMME3_CTRL_SHADOW_0_TENSOR_L_ROI_SIZE_0 0x1E04D4
+
+#define mmMME3_CTRL_SHADOW_0_TENSOR_L_ROI_SIZE_1 0x1E04D8
+
+#define mmMME3_CTRL_SHADOW_0_TENSOR_L_ROI_SIZE_2 0x1E04DC
+
+#define mmMME3_CTRL_SHADOW_0_TENSOR_L_ROI_SIZE_3 0x1E04E0
+
+#define mmMME3_CTRL_SHADOW_0_TENSOR_L_SPATIAL_STRIDES_0 0x1E04E4
+
+#define mmMME3_CTRL_SHADOW_0_TENSOR_L_SPATIAL_STRIDES_1 0x1E04E8
+
+#define mmMME3_CTRL_SHADOW_0_TENSOR_L_SPATIAL_STRIDES_2 0x1E04EC
+
+#define mmMME3_CTRL_SHADOW_0_TENSOR_L_SPATIAL_STRIDES_3 0x1E04F0
+
+#define mmMME3_CTRL_SHADOW_0_TENSOR_L_SPATIAL_SIZE_MINUS_1 0x1E04F4
+
+#define mmMME3_CTRL_SHADOW_0_AGU_L_LOCAL_ROI_BASE_OFFSET_0 0x1E04F8
+
+#define mmMME3_CTRL_SHADOW_0_AGU_L_LOCAL_ROI_BASE_OFFSET_1 0x1E04FC
+
+#define mmMME3_CTRL_SHADOW_0_AGU_L_LOCAL_ROI_BASE_OFFSET_2 0x1E0500
+
+#define mmMME3_CTRL_SHADOW_0_AGU_L_LOCAL_ROI_BASE_OFFSET_3 0x1E0504
+
+#define mmMME3_CTRL_SHADOW_0_AGU_L_LOCAL_ROI_BASE_OFFSET_4 0x1E0508
+
+#define mmMME3_CTRL_SHADOW_0_AGU_L_LOCAL_START_OFFSET_0 0x1E050C
+
+#define mmMME3_CTRL_SHADOW_0_AGU_L_LOCAL_START_OFFSET_1 0x1E0510
+
+#define mmMME3_CTRL_SHADOW_0_AGU_L_LOCAL_START_OFFSET_2 0x1E0514
+
+#define mmMME3_CTRL_SHADOW_0_AGU_L_LOCAL_START_OFFSET_3 0x1E0518
+
+#define mmMME3_CTRL_SHADOW_0_AGU_L_REMOTE_ROI_BASE_OFFSET_0 0x1E051C
+
+#define mmMME3_CTRL_SHADOW_0_AGU_L_REMOTE_ROI_BASE_OFFSET_1 0x1E0520
+
+#define mmMME3_CTRL_SHADOW_0_AGU_L_REMOTE_ROI_BASE_OFFSET_2 0x1E0524
+
+#define mmMME3_CTRL_SHADOW_0_AGU_L_REMOTE_ROI_BASE_OFFSET_3 0x1E0528
+
+#define mmMME3_CTRL_SHADOW_0_AGU_L_REMOTE_ROI_BASE_OFFSET_4 0x1E052C
+
+#define mmMME3_CTRL_SHADOW_0_AGU_L_REMOTE_START_OFFSET_0 0x1E0530
+
+#define mmMME3_CTRL_SHADOW_0_AGU_L_REMOTE_START_OFFSET_1 0x1E0534
+
+#define mmMME3_CTRL_SHADOW_0_AGU_L_REMOTE_START_OFFSET_2 0x1E0538
+
+#define mmMME3_CTRL_SHADOW_0_AGU_L_REMOTE_START_OFFSET_3 0x1E053C
+
+#define mmMME3_CTRL_SHADOW_0_TENSOR_O_VALID_ELEMENTS_0 0x1E0540
+
+#define mmMME3_CTRL_SHADOW_0_TENSOR_O_VALID_ELEMENTS_1 0x1E0544
+
+#define mmMME3_CTRL_SHADOW_0_TENSOR_O_VALID_ELEMENTS_2 0x1E0548
+
+#define mmMME3_CTRL_SHADOW_0_TENSOR_O_VALID_ELEMENTS_3 0x1E054C
+
+#define mmMME3_CTRL_SHADOW_0_TENSOR_O_VALID_ELEMENTS_4 0x1E0550
+
+#define mmMME3_CTRL_SHADOW_0_TENSOR_O_LOOP_STRIDE_0 0x1E0554
+
+#define mmMME3_CTRL_SHADOW_0_TENSOR_O_LOOP_STRIDE_1 0x1E0558
+
+#define mmMME3_CTRL_SHADOW_0_TENSOR_O_LOOP_STRIDE_2 0x1E055C
+
+#define mmMME3_CTRL_SHADOW_0_TENSOR_O_LOOP_STRIDE_3 0x1E0560
+
+#define mmMME3_CTRL_SHADOW_0_TENSOR_O_LOOP_STRIDE_4 0x1E0564
+
+#define mmMME3_CTRL_SHADOW_0_TENSOR_O_ROI_SIZE_0 0x1E0568
+
+#define mmMME3_CTRL_SHADOW_0_TENSOR_O_ROI_SIZE_1 0x1E056C
+
+#define mmMME3_CTRL_SHADOW_0_TENSOR_O_ROI_SIZE_2 0x1E0570
+
+#define mmMME3_CTRL_SHADOW_0_TENSOR_O_ROI_SIZE_3 0x1E0574
+
+#define mmMME3_CTRL_SHADOW_0_TENSOR_O_SPATIAL_STRIDES_0 0x1E0578
+
+#define mmMME3_CTRL_SHADOW_0_TENSOR_O_SPATIAL_STRIDES_1 0x1E057C
+
+#define mmMME3_CTRL_SHADOW_0_TENSOR_O_SPATIAL_STRIDES_2 0x1E0580
+
+#define mmMME3_CTRL_SHADOW_0_TENSOR_O_SPATIAL_STRIDES_3 0x1E0584
+
+#define mmMME3_CTRL_SHADOW_0_TENSOR_O_SPATIAL_SIZE_MINUS_1 0x1E0588
+
+#define mmMME3_CTRL_SHADOW_0_AGU_O_LOCAL_ROI_BASE_OFFSET_0 0x1E058C
+
+#define mmMME3_CTRL_SHADOW_0_AGU_O_LOCAL_ROI_BASE_OFFSET_1 0x1E0590
+
+#define mmMME3_CTRL_SHADOW_0_AGU_O_LOCAL_ROI_BASE_OFFSET_2 0x1E0594
+
+#define mmMME3_CTRL_SHADOW_0_AGU_O_LOCAL_ROI_BASE_OFFSET_3 0x1E0598
+
+#define mmMME3_CTRL_SHADOW_0_AGU_O_LOCAL_ROI_BASE_OFFSET_4 0x1E059C
+
+#define mmMME3_CTRL_SHADOW_0_AGU_O_LOCAL_START_OFFSET_0 0x1E05A0
+
+#define mmMME3_CTRL_SHADOW_0_AGU_O_LOCAL_START_OFFSET_1 0x1E05A4
+
+#define mmMME3_CTRL_SHADOW_0_AGU_O_LOCAL_START_OFFSET_2 0x1E05A8
+
+#define mmMME3_CTRL_SHADOW_0_AGU_O_LOCAL_START_OFFSET_3 0x1E05AC
+
+#define mmMME3_CTRL_SHADOW_0_AGU_O_REMOTE_ROI_BASE_OFFSET_0 0x1E05B0
+
+#define mmMME3_CTRL_SHADOW_0_AGU_O_REMOTE_ROI_BASE_OFFSET_1 0x1E05B4
+
+#define mmMME3_CTRL_SHADOW_0_AGU_O_REMOTE_ROI_BASE_OFFSET_2 0x1E05B8
+
+#define mmMME3_CTRL_SHADOW_0_AGU_O_REMOTE_ROI_BASE_OFFSET_3 0x1E05BC
+
+#define mmMME3_CTRL_SHADOW_0_AGU_O_REMOTE_ROI_BASE_OFFSET_4 0x1E05C0
+
+#define mmMME3_CTRL_SHADOW_0_AGU_O_REMOTE_START_OFFSET_0 0x1E05C4
+
+#define mmMME3_CTRL_SHADOW_0_AGU_O_REMOTE_START_OFFSET_1 0x1E05C8
+
+#define mmMME3_CTRL_SHADOW_0_AGU_O_REMOTE_START_OFFSET_2 0x1E05CC
+
+#define mmMME3_CTRL_SHADOW_0_AGU_O_REMOTE_START_OFFSET_3 0x1E05D0
+
+#define mmMME3_CTRL_SHADOW_0_DESC_SB_REPEAT 0x1E05D4
+
+#define mmMME3_CTRL_SHADOW_0_DESC_RATE_LIMITER 0x1E05D8
+
+#define mmMME3_CTRL_SHADOW_0_DESC_SYNC_OBJECT_ADDR_LOW_LOCAL 0x1E05DC
+
+#define mmMME3_CTRL_SHADOW_0_DESC_SYNC_OBJECT_ADDR_LOW_REMOTE 0x1E05E0
+
+#define mmMME3_CTRL_SHADOW_0_DESC_SYNC_OBJECT_ADDR_HIGH 0x1E05E4
+
+#define mmMME3_CTRL_SHADOW_0_DESC_SYNC_OBJECT_DATA 0x1E05E8
+
+#define mmMME3_CTRL_SHADOW_0_DESC_AXI_USER_DATA 0x1E05EC
+
+#define mmMME3_CTRL_SHADOW_0_DESC_PERF_EVT_S 0x1E05F0
+
+#define mmMME3_CTRL_SHADOW_0_DESC_PERF_EVT_L_LOCAL 0x1E05F4
+
+#define mmMME3_CTRL_SHADOW_0_DESC_PERF_EVT_L_REMOTE 0x1E05F8
+
+#define mmMME3_CTRL_SHADOW_0_DESC_PERF_EVT_O_LOCAL 0x1E05FC
+
+#define mmMME3_CTRL_SHADOW_0_DESC_PERF_EVT_O_REMOTE 0x1E0600
+
+#define mmMME3_CTRL_SHADOW_0_DESC_PADDING_VALUE_S 0x1E0604
+
+#define mmMME3_CTRL_SHADOW_0_DESC_PADDING_VALUE_L 0x1E0608
+
+#define mmMME3_CTRL_SHADOW_0_DESC_META_DATA_AGU_S 0x1E060C
+
+#define mmMME3_CTRL_SHADOW_0_DESC_META_DATA_AGU_L_LOCAL 0x1E0610
+
+#define mmMME3_CTRL_SHADOW_0_DESC_META_DATA_AGU_L_REMOTE 0x1E0614
+
+#define mmMME3_CTRL_SHADOW_0_DESC_META_DATA_AGU_O_LOCAL 0x1E0618
+
+#define mmMME3_CTRL_SHADOW_0_DESC_META_DATA_AGU_O_REMOTE 0x1E061C
+
+#define mmMME3_CTRL_SHADOW_0_DESC_PCU_RL_SATURATION 0x1E0620
+
+#define mmMME3_CTRL_SHADOW_0_DESC_DUMMY 0x1E0624
+
+#define mmMME3_CTRL_SHADOW_1_STATUS 0x1E0680
+
+#define mmMME3_CTRL_SHADOW_1_BASE_ADDR_HIGH_S 0x1E0688
+
+#define mmMME3_CTRL_SHADOW_1_BASE_ADDR_HIGH_L 0x1E068C
+
+#define mmMME3_CTRL_SHADOW_1_BASE_ADDR_HIGH_O 0x1E0690
+
+#define mmMME3_CTRL_SHADOW_1_BASE_ADDR_LOW_S 0x1E0694
+
+#define mmMME3_CTRL_SHADOW_1_BASE_ADDR_LOW_L 0x1E0698
+
+#define mmMME3_CTRL_SHADOW_1_BASE_ADDR_LOW_O 0x1E069C
+
+#define mmMME3_CTRL_SHADOW_1_HEADER_LOW 0x1E06A0
+
+#define mmMME3_CTRL_SHADOW_1_HEADER_HIGH 0x1E06A4
+
+#define mmMME3_CTRL_SHADOW_1_CONV_KERNEL_SIZE_MINUS_1 0x1E06A8
+
+#define mmMME3_CTRL_SHADOW_1_CONV_ASSOCIATED_DIMS_LOW 0x1E06AC
+
+#define mmMME3_CTRL_SHADOW_1_CONV_ASSOCIATED_DIMS_HIGH 0x1E06B0
+
+#define mmMME3_CTRL_SHADOW_1_NUM_ITERATIONS_MINUS_1 0x1E06B4
+
+#define mmMME3_CTRL_SHADOW_1_OUTER_LOOP 0x1E06B8
+
+#define mmMME3_CTRL_SHADOW_1_TENSOR_S_VALID_ELEMENTS_0 0x1E06BC
+
+#define mmMME3_CTRL_SHADOW_1_TENSOR_S_VALID_ELEMENTS_1 0x1E06C0
+
+#define mmMME3_CTRL_SHADOW_1_TENSOR_S_VALID_ELEMENTS_2 0x1E06C4
+
+#define mmMME3_CTRL_SHADOW_1_TENSOR_S_VALID_ELEMENTS_3 0x1E06C8
+
+#define mmMME3_CTRL_SHADOW_1_TENSOR_S_VALID_ELEMENTS_4 0x1E06CC
+
+#define mmMME3_CTRL_SHADOW_1_TENSOR_S_LOOP_STRIDE_0 0x1E06D0
+
+#define mmMME3_CTRL_SHADOW_1_TENSOR_S_LOOP_STRIDE_1 0x1E06D4
+
+#define mmMME3_CTRL_SHADOW_1_TENSOR_S_LOOP_STRIDE_2 0x1E06D8
+
+#define mmMME3_CTRL_SHADOW_1_TENSOR_S_LOOP_STRIDE_3 0x1E06DC
+
+#define mmMME3_CTRL_SHADOW_1_TENSOR_S_LOOP_STRIDE_4 0x1E06E0
+
+#define mmMME3_CTRL_SHADOW_1_TENSOR_S_ROI_SIZE_0 0x1E06E4
+
+#define mmMME3_CTRL_SHADOW_1_TENSOR_S_ROI_SIZE_1 0x1E06E8
+
+#define mmMME3_CTRL_SHADOW_1_TENSOR_S_ROI_SIZE_2 0x1E06EC
+
+#define mmMME3_CTRL_SHADOW_1_TENSOR_S_ROI_SIZE_3 0x1E06F0
+
+#define mmMME3_CTRL_SHADOW_1_TENSOR_S_SPATIAL_STRIDES_0 0x1E06F4
+
+#define mmMME3_CTRL_SHADOW_1_TENSOR_S_SPATIAL_STRIDES_1 0x1E06F8
+
+#define mmMME3_CTRL_SHADOW_1_TENSOR_S_SPATIAL_STRIDES_2 0x1E06FC
+
+#define mmMME3_CTRL_SHADOW_1_TENSOR_S_SPATIAL_STRIDES_3 0x1E0700
+
+#define mmMME3_CTRL_SHADOW_1_TENSOR_S_SPATIAL_SIZE_MINUS_1 0x1E0704
+
+#define mmMME3_CTRL_SHADOW_1_AGU_S_ROI_BASE_OFFSET_0 0x1E0708
+
+#define mmMME3_CTRL_SHADOW_1_AGU_S_ROI_BASE_OFFSET_1 0x1E070C
+
+#define mmMME3_CTRL_SHADOW_1_AGU_S_ROI_BASE_OFFSET_2 0x1E0710
+
+#define mmMME3_CTRL_SHADOW_1_AGU_S_ROI_BASE_OFFSET_3 0x1E0714
+
+#define mmMME3_CTRL_SHADOW_1_AGU_S_ROI_BASE_OFFSET_4 0x1E0718
+
+#define mmMME3_CTRL_SHADOW_1_AGU_S_START_OFFSET_0 0x1E071C
+
+#define mmMME3_CTRL_SHADOW_1_AGU_S_START_OFFSET_1 0x1E0720
+
+#define mmMME3_CTRL_SHADOW_1_AGU_S_START_OFFSET_2 0x1E0724
+
+#define mmMME3_CTRL_SHADOW_1_AGU_S_START_OFFSET_3 0x1E0728
+
+#define mmMME3_CTRL_SHADOW_1_TENSOR_L_VALID_ELEMENTS_0 0x1E072C
+
+#define mmMME3_CTRL_SHADOW_1_TENSOR_L_VALID_ELEMENTS_1 0x1E0730
+
+#define mmMME3_CTRL_SHADOW_1_TENSOR_L_VALID_ELEMENTS_2 0x1E0734
+
+#define mmMME3_CTRL_SHADOW_1_TENSOR_L_VALID_ELEMENTS_3 0x1E0738
+
+#define mmMME3_CTRL_SHADOW_1_TENSOR_L_VALID_ELEMENTS_4 0x1E073C
+
+#define mmMME3_CTRL_SHADOW_1_TENSOR_L_LOOP_STRIDE_0 0x1E0740
+
+#define mmMME3_CTRL_SHADOW_1_TENSOR_L_LOOP_STRIDE_1 0x1E0744
+
+#define mmMME3_CTRL_SHADOW_1_TENSOR_L_LOOP_STRIDE_2 0x1E0748
+
+#define mmMME3_CTRL_SHADOW_1_TENSOR_L_LOOP_STRIDE_3 0x1E074C
+
+#define mmMME3_CTRL_SHADOW_1_TENSOR_L_LOOP_STRIDE_4 0x1E0750
+
+#define mmMME3_CTRL_SHADOW_1_TENSOR_L_ROI_SIZE_0 0x1E0754
+
+#define mmMME3_CTRL_SHADOW_1_TENSOR_L_ROI_SIZE_1 0x1E0758
+
+#define mmMME3_CTRL_SHADOW_1_TENSOR_L_ROI_SIZE_2 0x1E075C
+
+#define mmMME3_CTRL_SHADOW_1_TENSOR_L_ROI_SIZE_3 0x1E0760
+
+#define mmMME3_CTRL_SHADOW_1_TENSOR_L_SPATIAL_STRIDES_0 0x1E0764
+
+#define mmMME3_CTRL_SHADOW_1_TENSOR_L_SPATIAL_STRIDES_1 0x1E0768
+
+#define mmMME3_CTRL_SHADOW_1_TENSOR_L_SPATIAL_STRIDES_2 0x1E076C
+
+#define mmMME3_CTRL_SHADOW_1_TENSOR_L_SPATIAL_STRIDES_3 0x1E0770
+
+#define mmMME3_CTRL_SHADOW_1_TENSOR_L_SPATIAL_SIZE_MINUS_1 0x1E0774
+
+#define mmMME3_CTRL_SHADOW_1_AGU_L_LOCAL_ROI_BASE_OFFSET_0 0x1E0778
+
+#define mmMME3_CTRL_SHADOW_1_AGU_L_LOCAL_ROI_BASE_OFFSET_1 0x1E077C
+
+#define mmMME3_CTRL_SHADOW_1_AGU_L_LOCAL_ROI_BASE_OFFSET_2 0x1E0780
+
+#define mmMME3_CTRL_SHADOW_1_AGU_L_LOCAL_ROI_BASE_OFFSET_3 0x1E0784
+
+#define mmMME3_CTRL_SHADOW_1_AGU_L_LOCAL_ROI_BASE_OFFSET_4 0x1E0788
+
+#define mmMME3_CTRL_SHADOW_1_AGU_L_LOCAL_START_OFFSET_0 0x1E078C
+
+#define mmMME3_CTRL_SHADOW_1_AGU_L_LOCAL_START_OFFSET_1 0x1E0790
+
+#define mmMME3_CTRL_SHADOW_1_AGU_L_LOCAL_START_OFFSET_2 0x1E0794
+
+#define mmMME3_CTRL_SHADOW_1_AGU_L_LOCAL_START_OFFSET_3 0x1E0798
+
+#define mmMME3_CTRL_SHADOW_1_AGU_L_REMOTE_ROI_BASE_OFFSET_0 0x1E079C
+
+#define mmMME3_CTRL_SHADOW_1_AGU_L_REMOTE_ROI_BASE_OFFSET_1 0x1E07A0
+
+#define mmMME3_CTRL_SHADOW_1_AGU_L_REMOTE_ROI_BASE_OFFSET_2 0x1E07A4
+
+#define mmMME3_CTRL_SHADOW_1_AGU_L_REMOTE_ROI_BASE_OFFSET_3 0x1E07A8
+
+#define mmMME3_CTRL_SHADOW_1_AGU_L_REMOTE_ROI_BASE_OFFSET_4 0x1E07AC
+
+#define mmMME3_CTRL_SHADOW_1_AGU_L_REMOTE_START_OFFSET_0 0x1E07B0
+
+#define mmMME3_CTRL_SHADOW_1_AGU_L_REMOTE_START_OFFSET_1 0x1E07B4
+
+#define mmMME3_CTRL_SHADOW_1_AGU_L_REMOTE_START_OFFSET_2 0x1E07B8
+
+#define mmMME3_CTRL_SHADOW_1_AGU_L_REMOTE_START_OFFSET_3 0x1E07BC
+
+#define mmMME3_CTRL_SHADOW_1_TENSOR_O_VALID_ELEMENTS_0 0x1E07C0
+
+#define mmMME3_CTRL_SHADOW_1_TENSOR_O_VALID_ELEMENTS_1 0x1E07C4
+
+#define mmMME3_CTRL_SHADOW_1_TENSOR_O_VALID_ELEMENTS_2 0x1E07C8
+
+#define mmMME3_CTRL_SHADOW_1_TENSOR_O_VALID_ELEMENTS_3 0x1E07CC
+
+#define mmMME3_CTRL_SHADOW_1_TENSOR_O_VALID_ELEMENTS_4 0x1E07D0
+
+#define mmMME3_CTRL_SHADOW_1_TENSOR_O_LOOP_STRIDE_0 0x1E07D4
+
+#define mmMME3_CTRL_SHADOW_1_TENSOR_O_LOOP_STRIDE_1 0x1E07D8
+
+#define mmMME3_CTRL_SHADOW_1_TENSOR_O_LOOP_STRIDE_2 0x1E07DC
+
+#define mmMME3_CTRL_SHADOW_1_TENSOR_O_LOOP_STRIDE_3 0x1E07E0
+
+#define mmMME3_CTRL_SHADOW_1_TENSOR_O_LOOP_STRIDE_4 0x1E07E4
+
+#define mmMME3_CTRL_SHADOW_1_TENSOR_O_ROI_SIZE_0 0x1E07E8
+
+#define mmMME3_CTRL_SHADOW_1_TENSOR_O_ROI_SIZE_1 0x1E07EC
+
+#define mmMME3_CTRL_SHADOW_1_TENSOR_O_ROI_SIZE_2 0x1E07F0
+
+#define mmMME3_CTRL_SHADOW_1_TENSOR_O_ROI_SIZE_3 0x1E07F4
+
+#define mmMME3_CTRL_SHADOW_1_TENSOR_O_SPATIAL_STRIDES_0 0x1E07F8
+
+#define mmMME3_CTRL_SHADOW_1_TENSOR_O_SPATIAL_STRIDES_1 0x1E07FC
+
+#define mmMME3_CTRL_SHADOW_1_TENSOR_O_SPATIAL_STRIDES_2 0x1E0800
+
+#define mmMME3_CTRL_SHADOW_1_TENSOR_O_SPATIAL_STRIDES_3 0x1E0804
+
+#define mmMME3_CTRL_SHADOW_1_TENSOR_O_SPATIAL_SIZE_MINUS_1 0x1E0808
+
+#define mmMME3_CTRL_SHADOW_1_AGU_O_LOCAL_ROI_BASE_OFFSET_0 0x1E080C
+
+#define mmMME3_CTRL_SHADOW_1_AGU_O_LOCAL_ROI_BASE_OFFSET_1 0x1E0810
+
+#define mmMME3_CTRL_SHADOW_1_AGU_O_LOCAL_ROI_BASE_OFFSET_2 0x1E0814
+
+#define mmMME3_CTRL_SHADOW_1_AGU_O_LOCAL_ROI_BASE_OFFSET_3 0x1E0818
+
+#define mmMME3_CTRL_SHADOW_1_AGU_O_LOCAL_ROI_BASE_OFFSET_4 0x1E081C
+
+#define mmMME3_CTRL_SHADOW_1_AGU_O_LOCAL_START_OFFSET_0 0x1E0820
+
+#define mmMME3_CTRL_SHADOW_1_AGU_O_LOCAL_START_OFFSET_1 0x1E0824
+
+#define mmMME3_CTRL_SHADOW_1_AGU_O_LOCAL_START_OFFSET_2 0x1E0828
+
+#define mmMME3_CTRL_SHADOW_1_AGU_O_LOCAL_START_OFFSET_3 0x1E082C
+
+#define mmMME3_CTRL_SHADOW_1_AGU_O_REMOTE_ROI_BASE_OFFSET_0 0x1E0830
+
+#define mmMME3_CTRL_SHADOW_1_AGU_O_REMOTE_ROI_BASE_OFFSET_1 0x1E0834
+
+#define mmMME3_CTRL_SHADOW_1_AGU_O_REMOTE_ROI_BASE_OFFSET_2 0x1E0838
+
+#define mmMME3_CTRL_SHADOW_1_AGU_O_REMOTE_ROI_BASE_OFFSET_3 0x1E083C
+
+#define mmMME3_CTRL_SHADOW_1_AGU_O_REMOTE_ROI_BASE_OFFSET_4 0x1E0840
+
+#define mmMME3_CTRL_SHADOW_1_AGU_O_REMOTE_START_OFFSET_0 0x1E0844
+
+#define mmMME3_CTRL_SHADOW_1_AGU_O_REMOTE_START_OFFSET_1 0x1E0848
+
+#define mmMME3_CTRL_SHADOW_1_AGU_O_REMOTE_START_OFFSET_2 0x1E084C
+
+#define mmMME3_CTRL_SHADOW_1_AGU_O_REMOTE_START_OFFSET_3 0x1E0850
+
+#define mmMME3_CTRL_SHADOW_1_DESC_SB_REPEAT 0x1E0854
+
+#define mmMME3_CTRL_SHADOW_1_DESC_RATE_LIMITER 0x1E0858
+
+#define mmMME3_CTRL_SHADOW_1_DESC_SYNC_OBJECT_ADDR_LOW_LOCAL 0x1E085C
+
+#define mmMME3_CTRL_SHADOW_1_DESC_SYNC_OBJECT_ADDR_LOW_REMOTE 0x1E0860
+
+#define mmMME3_CTRL_SHADOW_1_DESC_SYNC_OBJECT_ADDR_HIGH 0x1E0864
+
+#define mmMME3_CTRL_SHADOW_1_DESC_SYNC_OBJECT_DATA 0x1E0868
+
+#define mmMME3_CTRL_SHADOW_1_DESC_AXI_USER_DATA 0x1E086C
+
+#define mmMME3_CTRL_SHADOW_1_DESC_PERF_EVT_S 0x1E0870
+
+#define mmMME3_CTRL_SHADOW_1_DESC_PERF_EVT_L_LOCAL 0x1E0874
+
+#define mmMME3_CTRL_SHADOW_1_DESC_PERF_EVT_L_REMOTE 0x1E0878
+
+#define mmMME3_CTRL_SHADOW_1_DESC_PERF_EVT_O_LOCAL 0x1E087C
+
+#define mmMME3_CTRL_SHADOW_1_DESC_PERF_EVT_O_REMOTE 0x1E0880
+
+#define mmMME3_CTRL_SHADOW_1_DESC_PADDING_VALUE_S 0x1E0884
+
+#define mmMME3_CTRL_SHADOW_1_DESC_PADDING_VALUE_L 0x1E0888
+
+#define mmMME3_CTRL_SHADOW_1_DESC_META_DATA_AGU_S 0x1E088C
+
+#define mmMME3_CTRL_SHADOW_1_DESC_META_DATA_AGU_L_LOCAL 0x1E0890
+
+#define mmMME3_CTRL_SHADOW_1_DESC_META_DATA_AGU_L_REMOTE 0x1E0894
+
+#define mmMME3_CTRL_SHADOW_1_DESC_META_DATA_AGU_O_LOCAL 0x1E0898
+
+#define mmMME3_CTRL_SHADOW_1_DESC_META_DATA_AGU_O_REMOTE 0x1E089C
+
+#define mmMME3_CTRL_SHADOW_1_DESC_PCU_RL_SATURATION 0x1E08A0
+
+#define mmMME3_CTRL_SHADOW_1_DESC_DUMMY 0x1E08A4
+
+#define mmMME3_CTRL_SHADOW_2_STATUS 0x1E0900
+
+#define mmMME3_CTRL_SHADOW_2_BASE_ADDR_HIGH_S 0x1E0908
+
+#define mmMME3_CTRL_SHADOW_2_BASE_ADDR_HIGH_L 0x1E090C
+
+#define mmMME3_CTRL_SHADOW_2_BASE_ADDR_HIGH_O 0x1E0910
+
+#define mmMME3_CTRL_SHADOW_2_BASE_ADDR_LOW_S 0x1E0914
+
+#define mmMME3_CTRL_SHADOW_2_BASE_ADDR_LOW_L 0x1E0918
+
+#define mmMME3_CTRL_SHADOW_2_BASE_ADDR_LOW_O 0x1E091C
+
+#define mmMME3_CTRL_SHADOW_2_HEADER_LOW 0x1E0920
+
+#define mmMME3_CTRL_SHADOW_2_HEADER_HIGH 0x1E0924
+
+#define mmMME3_CTRL_SHADOW_2_CONV_KERNEL_SIZE_MINUS_1 0x1E0928
+
+#define mmMME3_CTRL_SHADOW_2_CONV_ASSOCIATED_DIMS_LOW 0x1E092C
+
+#define mmMME3_CTRL_SHADOW_2_CONV_ASSOCIATED_DIMS_HIGH 0x1E0930
+
+#define mmMME3_CTRL_SHADOW_2_NUM_ITERATIONS_MINUS_1 0x1E0934
+
+#define mmMME3_CTRL_SHADOW_2_OUTER_LOOP 0x1E0938
+
+#define mmMME3_CTRL_SHADOW_2_TENSOR_S_VALID_ELEMENTS_0 0x1E093C
+
+#define mmMME3_CTRL_SHADOW_2_TENSOR_S_VALID_ELEMENTS_1 0x1E0940
+
+#define mmMME3_CTRL_SHADOW_2_TENSOR_S_VALID_ELEMENTS_2 0x1E0944
+
+#define mmMME3_CTRL_SHADOW_2_TENSOR_S_VALID_ELEMENTS_3 0x1E0948
+
+#define mmMME3_CTRL_SHADOW_2_TENSOR_S_VALID_ELEMENTS_4 0x1E094C
+
+#define mmMME3_CTRL_SHADOW_2_TENSOR_S_LOOP_STRIDE_0 0x1E0950
+
+#define mmMME3_CTRL_SHADOW_2_TENSOR_S_LOOP_STRIDE_1 0x1E0954
+
+#define mmMME3_CTRL_SHADOW_2_TENSOR_S_LOOP_STRIDE_2 0x1E0958
+
+#define mmMME3_CTRL_SHADOW_2_TENSOR_S_LOOP_STRIDE_3 0x1E095C
+
+#define mmMME3_CTRL_SHADOW_2_TENSOR_S_LOOP_STRIDE_4 0x1E0960
+
+#define mmMME3_CTRL_SHADOW_2_TENSOR_S_ROI_SIZE_0 0x1E0964
+
+#define mmMME3_CTRL_SHADOW_2_TENSOR_S_ROI_SIZE_1 0x1E0968
+
+#define mmMME3_CTRL_SHADOW_2_TENSOR_S_ROI_SIZE_2 0x1E096C
+
+#define mmMME3_CTRL_SHADOW_2_TENSOR_S_ROI_SIZE_3 0x1E0970
+
+#define mmMME3_CTRL_SHADOW_2_TENSOR_S_SPATIAL_STRIDES_0 0x1E0974
+
+#define mmMME3_CTRL_SHADOW_2_TENSOR_S_SPATIAL_STRIDES_1 0x1E0978
+
+#define mmMME3_CTRL_SHADOW_2_TENSOR_S_SPATIAL_STRIDES_2 0x1E097C
+
+#define mmMME3_CTRL_SHADOW_2_TENSOR_S_SPATIAL_STRIDES_3 0x1E0980
+
+#define mmMME3_CTRL_SHADOW_2_TENSOR_S_SPATIAL_SIZE_MINUS_1 0x1E0984
+
+#define mmMME3_CTRL_SHADOW_2_AGU_S_ROI_BASE_OFFSET_0 0x1E0988
+
+#define mmMME3_CTRL_SHADOW_2_AGU_S_ROI_BASE_OFFSET_1 0x1E098C
+
+#define mmMME3_CTRL_SHADOW_2_AGU_S_ROI_BASE_OFFSET_2 0x1E0990
+
+#define mmMME3_CTRL_SHADOW_2_AGU_S_ROI_BASE_OFFSET_3 0x1E0994
+
+#define mmMME3_CTRL_SHADOW_2_AGU_S_ROI_BASE_OFFSET_4 0x1E0998
+
+#define mmMME3_CTRL_SHADOW_2_AGU_S_START_OFFSET_0 0x1E099C
+
+#define mmMME3_CTRL_SHADOW_2_AGU_S_START_OFFSET_1 0x1E09A0
+
+#define mmMME3_CTRL_SHADOW_2_AGU_S_START_OFFSET_2 0x1E09A4
+
+#define mmMME3_CTRL_SHADOW_2_AGU_S_START_OFFSET_3 0x1E09A8
+
+#define mmMME3_CTRL_SHADOW_2_TENSOR_L_VALID_ELEMENTS_0 0x1E09AC
+
+#define mmMME3_CTRL_SHADOW_2_TENSOR_L_VALID_ELEMENTS_1 0x1E09B0
+
+#define mmMME3_CTRL_SHADOW_2_TENSOR_L_VALID_ELEMENTS_2 0x1E09B4
+
+#define mmMME3_CTRL_SHADOW_2_TENSOR_L_VALID_ELEMENTS_3 0x1E09B8
+
+#define mmMME3_CTRL_SHADOW_2_TENSOR_L_VALID_ELEMENTS_4 0x1E09BC
+
+#define mmMME3_CTRL_SHADOW_2_TENSOR_L_LOOP_STRIDE_0 0x1E09C0
+
+#define mmMME3_CTRL_SHADOW_2_TENSOR_L_LOOP_STRIDE_1 0x1E09C4
+
+#define mmMME3_CTRL_SHADOW_2_TENSOR_L_LOOP_STRIDE_2 0x1E09C8
+
+#define mmMME3_CTRL_SHADOW_2_TENSOR_L_LOOP_STRIDE_3 0x1E09CC
+
+#define mmMME3_CTRL_SHADOW_2_TENSOR_L_LOOP_STRIDE_4 0x1E09D0
+
+#define mmMME3_CTRL_SHADOW_2_TENSOR_L_ROI_SIZE_0 0x1E09D4
+
+#define mmMME3_CTRL_SHADOW_2_TENSOR_L_ROI_SIZE_1 0x1E09D8
+
+#define mmMME3_CTRL_SHADOW_2_TENSOR_L_ROI_SIZE_2 0x1E09DC
+
+#define mmMME3_CTRL_SHADOW_2_TENSOR_L_ROI_SIZE_3 0x1E09E0
+
+#define mmMME3_CTRL_SHADOW_2_TENSOR_L_SPATIAL_STRIDES_0 0x1E09E4
+
+#define mmMME3_CTRL_SHADOW_2_TENSOR_L_SPATIAL_STRIDES_1 0x1E09E8
+
+#define mmMME3_CTRL_SHADOW_2_TENSOR_L_SPATIAL_STRIDES_2 0x1E09EC
+
+#define mmMME3_CTRL_SHADOW_2_TENSOR_L_SPATIAL_STRIDES_3 0x1E09F0
+
+#define mmMME3_CTRL_SHADOW_2_TENSOR_L_SPATIAL_SIZE_MINUS_1 0x1E09F4
+
+#define mmMME3_CTRL_SHADOW_2_AGU_L_LOCAL_ROI_BASE_OFFSET_0 0x1E09F8
+
+#define mmMME3_CTRL_SHADOW_2_AGU_L_LOCAL_ROI_BASE_OFFSET_1 0x1E09FC
+
+#define mmMME3_CTRL_SHADOW_2_AGU_L_LOCAL_ROI_BASE_OFFSET_2 0x1E0A00
+
+#define mmMME3_CTRL_SHADOW_2_AGU_L_LOCAL_ROI_BASE_OFFSET_3 0x1E0A04
+
+#define mmMME3_CTRL_SHADOW_2_AGU_L_LOCAL_ROI_BASE_OFFSET_4 0x1E0A08
+
+#define mmMME3_CTRL_SHADOW_2_AGU_L_LOCAL_START_OFFSET_0 0x1E0A0C
+
+#define mmMME3_CTRL_SHADOW_2_AGU_L_LOCAL_START_OFFSET_1 0x1E0A10
+
+#define mmMME3_CTRL_SHADOW_2_AGU_L_LOCAL_START_OFFSET_2 0x1E0A14
+
+#define mmMME3_CTRL_SHADOW_2_AGU_L_LOCAL_START_OFFSET_3 0x1E0A18
+
+#define mmMME3_CTRL_SHADOW_2_AGU_L_REMOTE_ROI_BASE_OFFSET_0 0x1E0A1C
+
+#define mmMME3_CTRL_SHADOW_2_AGU_L_REMOTE_ROI_BASE_OFFSET_1 0x1E0A20
+
+#define mmMME3_CTRL_SHADOW_2_AGU_L_REMOTE_ROI_BASE_OFFSET_2 0x1E0A24
+
+#define mmMME3_CTRL_SHADOW_2_AGU_L_REMOTE_ROI_BASE_OFFSET_3 0x1E0A28
+
+#define mmMME3_CTRL_SHADOW_2_AGU_L_REMOTE_ROI_BASE_OFFSET_4 0x1E0A2C
+
+#define mmMME3_CTRL_SHADOW_2_AGU_L_REMOTE_START_OFFSET_0 0x1E0A30
+
+#define mmMME3_CTRL_SHADOW_2_AGU_L_REMOTE_START_OFFSET_1 0x1E0A34
+
+#define mmMME3_CTRL_SHADOW_2_AGU_L_REMOTE_START_OFFSET_2 0x1E0A38
+
+#define mmMME3_CTRL_SHADOW_2_AGU_L_REMOTE_START_OFFSET_3 0x1E0A3C
+
+#define mmMME3_CTRL_SHADOW_2_TENSOR_O_VALID_ELEMENTS_0 0x1E0A40
+
+#define mmMME3_CTRL_SHADOW_2_TENSOR_O_VALID_ELEMENTS_1 0x1E0A44
+
+#define mmMME3_CTRL_SHADOW_2_TENSOR_O_VALID_ELEMENTS_2 0x1E0A48
+
+#define mmMME3_CTRL_SHADOW_2_TENSOR_O_VALID_ELEMENTS_3 0x1E0A4C
+
+#define mmMME3_CTRL_SHADOW_2_TENSOR_O_VALID_ELEMENTS_4 0x1E0A50
+
+#define mmMME3_CTRL_SHADOW_2_TENSOR_O_LOOP_STRIDE_0 0x1E0A54
+
+#define mmMME3_CTRL_SHADOW_2_TENSOR_O_LOOP_STRIDE_1 0x1E0A58
+
+#define mmMME3_CTRL_SHADOW_2_TENSOR_O_LOOP_STRIDE_2 0x1E0A5C
+
+#define mmMME3_CTRL_SHADOW_2_TENSOR_O_LOOP_STRIDE_3 0x1E0A60
+
+#define mmMME3_CTRL_SHADOW_2_TENSOR_O_LOOP_STRIDE_4 0x1E0A64
+
+#define mmMME3_CTRL_SHADOW_2_TENSOR_O_ROI_SIZE_0 0x1E0A68
+
+#define mmMME3_CTRL_SHADOW_2_TENSOR_O_ROI_SIZE_1 0x1E0A6C
+
+#define mmMME3_CTRL_SHADOW_2_TENSOR_O_ROI_SIZE_2 0x1E0A70
+
+#define mmMME3_CTRL_SHADOW_2_TENSOR_O_ROI_SIZE_3 0x1E0A74
+
+#define mmMME3_CTRL_SHADOW_2_TENSOR_O_SPATIAL_STRIDES_0 0x1E0A78
+
+#define mmMME3_CTRL_SHADOW_2_TENSOR_O_SPATIAL_STRIDES_1 0x1E0A7C
+
+#define mmMME3_CTRL_SHADOW_2_TENSOR_O_SPATIAL_STRIDES_2 0x1E0A80
+
+#define mmMME3_CTRL_SHADOW_2_TENSOR_O_SPATIAL_STRIDES_3 0x1E0A84
+
+#define mmMME3_CTRL_SHADOW_2_TENSOR_O_SPATIAL_SIZE_MINUS_1 0x1E0A88
+
+#define mmMME3_CTRL_SHADOW_2_AGU_O_LOCAL_ROI_BASE_OFFSET_0 0x1E0A8C
+
+#define mmMME3_CTRL_SHADOW_2_AGU_O_LOCAL_ROI_BASE_OFFSET_1 0x1E0A90
+
+#define mmMME3_CTRL_SHADOW_2_AGU_O_LOCAL_ROI_BASE_OFFSET_2 0x1E0A94
+
+#define mmMME3_CTRL_SHADOW_2_AGU_O_LOCAL_ROI_BASE_OFFSET_3 0x1E0A98
+
+#define mmMME3_CTRL_SHADOW_2_AGU_O_LOCAL_ROI_BASE_OFFSET_4 0x1E0A9C
+
+#define mmMME3_CTRL_SHADOW_2_AGU_O_LOCAL_START_OFFSET_0 0x1E0AA0
+
+#define mmMME3_CTRL_SHADOW_2_AGU_O_LOCAL_START_OFFSET_1 0x1E0AA4
+
+#define mmMME3_CTRL_SHADOW_2_AGU_O_LOCAL_START_OFFSET_2 0x1E0AA8
+
+#define mmMME3_CTRL_SHADOW_2_AGU_O_LOCAL_START_OFFSET_3 0x1E0AAC
+
+#define mmMME3_CTRL_SHADOW_2_AGU_O_REMOTE_ROI_BASE_OFFSET_0 0x1E0AB0
+
+#define mmMME3_CTRL_SHADOW_2_AGU_O_REMOTE_ROI_BASE_OFFSET_1 0x1E0AB4
+
+#define mmMME3_CTRL_SHADOW_2_AGU_O_REMOTE_ROI_BASE_OFFSET_2 0x1E0AB8
+
+#define mmMME3_CTRL_SHADOW_2_AGU_O_REMOTE_ROI_BASE_OFFSET_3 0x1E0ABC
+
+#define mmMME3_CTRL_SHADOW_2_AGU_O_REMOTE_ROI_BASE_OFFSET_4 0x1E0AC0
+
+#define mmMME3_CTRL_SHADOW_2_AGU_O_REMOTE_START_OFFSET_0 0x1E0AC4
+
+#define mmMME3_CTRL_SHADOW_2_AGU_O_REMOTE_START_OFFSET_1 0x1E0AC8
+
+#define mmMME3_CTRL_SHADOW_2_AGU_O_REMOTE_START_OFFSET_2 0x1E0ACC
+
+#define mmMME3_CTRL_SHADOW_2_AGU_O_REMOTE_START_OFFSET_3 0x1E0AD0
+
+#define mmMME3_CTRL_SHADOW_2_DESC_SB_REPEAT 0x1E0AD4
+
+#define mmMME3_CTRL_SHADOW_2_DESC_RATE_LIMITER 0x1E0AD8
+
+#define mmMME3_CTRL_SHADOW_2_DESC_SYNC_OBJECT_ADDR_LOW_LOCAL 0x1E0ADC
+
+#define mmMME3_CTRL_SHADOW_2_DESC_SYNC_OBJECT_ADDR_LOW_REMOTE 0x1E0AE0
+
+#define mmMME3_CTRL_SHADOW_2_DESC_SYNC_OBJECT_ADDR_HIGH 0x1E0AE4
+
+#define mmMME3_CTRL_SHADOW_2_DESC_SYNC_OBJECT_DATA 0x1E0AE8
+
+#define mmMME3_CTRL_SHADOW_2_DESC_AXI_USER_DATA 0x1E0AEC
+
+#define mmMME3_CTRL_SHADOW_2_DESC_PERF_EVT_S 0x1E0AF0
+
+#define mmMME3_CTRL_SHADOW_2_DESC_PERF_EVT_L_LOCAL 0x1E0AF4
+
+#define mmMME3_CTRL_SHADOW_2_DESC_PERF_EVT_L_REMOTE 0x1E0AF8
+
+#define mmMME3_CTRL_SHADOW_2_DESC_PERF_EVT_O_LOCAL 0x1E0AFC
+
+#define mmMME3_CTRL_SHADOW_2_DESC_PERF_EVT_O_REMOTE 0x1E0B00
+
+#define mmMME3_CTRL_SHADOW_2_DESC_PADDING_VALUE_S 0x1E0B04
+
+#define mmMME3_CTRL_SHADOW_2_DESC_PADDING_VALUE_L 0x1E0B08
+
+#define mmMME3_CTRL_SHADOW_2_DESC_META_DATA_AGU_S 0x1E0B0C
+
+#define mmMME3_CTRL_SHADOW_2_DESC_META_DATA_AGU_L_LOCAL 0x1E0B10
+
+#define mmMME3_CTRL_SHADOW_2_DESC_META_DATA_AGU_L_REMOTE 0x1E0B14
+
+#define mmMME3_CTRL_SHADOW_2_DESC_META_DATA_AGU_O_LOCAL 0x1E0B18
+
+#define mmMME3_CTRL_SHADOW_2_DESC_META_DATA_AGU_O_REMOTE 0x1E0B1C
+
+#define mmMME3_CTRL_SHADOW_2_DESC_PCU_RL_SATURATION 0x1E0B20
+
+#define mmMME3_CTRL_SHADOW_2_DESC_DUMMY 0x1E0B24
+
+#define mmMME3_CTRL_SHADOW_3_STATUS 0x1E0B80
+
+#define mmMME3_CTRL_SHADOW_3_BASE_ADDR_HIGH_S 0x1E0B88
+
+#define mmMME3_CTRL_SHADOW_3_BASE_ADDR_HIGH_L 0x1E0B8C
+
+#define mmMME3_CTRL_SHADOW_3_BASE_ADDR_HIGH_O 0x1E0B90
+
+#define mmMME3_CTRL_SHADOW_3_BASE_ADDR_LOW_S 0x1E0B94
+
+#define mmMME3_CTRL_SHADOW_3_BASE_ADDR_LOW_L 0x1E0B98
+
+#define mmMME3_CTRL_SHADOW_3_BASE_ADDR_LOW_O 0x1E0B9C
+
+#define mmMME3_CTRL_SHADOW_3_HEADER_LOW 0x1E0BA0
+
+#define mmMME3_CTRL_SHADOW_3_HEADER_HIGH 0x1E0BA4
+
+#define mmMME3_CTRL_SHADOW_3_CONV_KERNEL_SIZE_MINUS_1 0x1E0BA8
+
+#define mmMME3_CTRL_SHADOW_3_CONV_ASSOCIATED_DIMS_LOW 0x1E0BAC
+
+#define mmMME3_CTRL_SHADOW_3_CONV_ASSOCIATED_DIMS_HIGH 0x1E0BB0
+
+#define mmMME3_CTRL_SHADOW_3_NUM_ITERATIONS_MINUS_1 0x1E0BB4
+
+#define mmMME3_CTRL_SHADOW_3_OUTER_LOOP 0x1E0BB8
+
+#define mmMME3_CTRL_SHADOW_3_TENSOR_S_VALID_ELEMENTS_0 0x1E0BBC
+
+#define mmMME3_CTRL_SHADOW_3_TENSOR_S_VALID_ELEMENTS_1 0x1E0BC0
+
+#define mmMME3_CTRL_SHADOW_3_TENSOR_S_VALID_ELEMENTS_2 0x1E0BC4
+
+#define mmMME3_CTRL_SHADOW_3_TENSOR_S_VALID_ELEMENTS_3 0x1E0BC8
+
+#define mmMME3_CTRL_SHADOW_3_TENSOR_S_VALID_ELEMENTS_4 0x1E0BCC
+
+#define mmMME3_CTRL_SHADOW_3_TENSOR_S_LOOP_STRIDE_0 0x1E0BD0
+
+#define mmMME3_CTRL_SHADOW_3_TENSOR_S_LOOP_STRIDE_1 0x1E0BD4
+
+#define mmMME3_CTRL_SHADOW_3_TENSOR_S_LOOP_STRIDE_2 0x1E0BD8
+
+#define mmMME3_CTRL_SHADOW_3_TENSOR_S_LOOP_STRIDE_3 0x1E0BDC
+
+#define mmMME3_CTRL_SHADOW_3_TENSOR_S_LOOP_STRIDE_4 0x1E0BE0
+
+#define mmMME3_CTRL_SHADOW_3_TENSOR_S_ROI_SIZE_0 0x1E0BE4
+
+#define mmMME3_CTRL_SHADOW_3_TENSOR_S_ROI_SIZE_1 0x1E0BE8
+
+#define mmMME3_CTRL_SHADOW_3_TENSOR_S_ROI_SIZE_2 0x1E0BEC
+
+#define mmMME3_CTRL_SHADOW_3_TENSOR_S_ROI_SIZE_3 0x1E0BF0
+
+#define mmMME3_CTRL_SHADOW_3_TENSOR_S_SPATIAL_STRIDES_0 0x1E0BF4
+
+#define mmMME3_CTRL_SHADOW_3_TENSOR_S_SPATIAL_STRIDES_1 0x1E0BF8
+
+#define mmMME3_CTRL_SHADOW_3_TENSOR_S_SPATIAL_STRIDES_2 0x1E0BFC
+
+#define mmMME3_CTRL_SHADOW_3_TENSOR_S_SPATIAL_STRIDES_3 0x1E0C00
+
+#define mmMME3_CTRL_SHADOW_3_TENSOR_S_SPATIAL_SIZE_MINUS_1 0x1E0C04
+
+#define mmMME3_CTRL_SHADOW_3_AGU_S_ROI_BASE_OFFSET_0 0x1E0C08
+
+#define mmMME3_CTRL_SHADOW_3_AGU_S_ROI_BASE_OFFSET_1 0x1E0C0C
+
+#define mmMME3_CTRL_SHADOW_3_AGU_S_ROI_BASE_OFFSET_2 0x1E0C10
+
+#define mmMME3_CTRL_SHADOW_3_AGU_S_ROI_BASE_OFFSET_3 0x1E0C14
+
+#define mmMME3_CTRL_SHADOW_3_AGU_S_ROI_BASE_OFFSET_4 0x1E0C18
+
+#define mmMME3_CTRL_SHADOW_3_AGU_S_START_OFFSET_0 0x1E0C1C
+
+#define mmMME3_CTRL_SHADOW_3_AGU_S_START_OFFSET_1 0x1E0C20
+
+#define mmMME3_CTRL_SHADOW_3_AGU_S_START_OFFSET_2 0x1E0C24
+
+#define mmMME3_CTRL_SHADOW_3_AGU_S_START_OFFSET_3 0x1E0C28
+
+#define mmMME3_CTRL_SHADOW_3_TENSOR_L_VALID_ELEMENTS_0 0x1E0C2C
+
+#define mmMME3_CTRL_SHADOW_3_TENSOR_L_VALID_ELEMENTS_1 0x1E0C30
+
+#define mmMME3_CTRL_SHADOW_3_TENSOR_L_VALID_ELEMENTS_2 0x1E0C34
+
+#define mmMME3_CTRL_SHADOW_3_TENSOR_L_VALID_ELEMENTS_3 0x1E0C38
+
+#define mmMME3_CTRL_SHADOW_3_TENSOR_L_VALID_ELEMENTS_4 0x1E0C3C
+
+#define mmMME3_CTRL_SHADOW_3_TENSOR_L_LOOP_STRIDE_0 0x1E0C40
+
+#define mmMME3_CTRL_SHADOW_3_TENSOR_L_LOOP_STRIDE_1 0x1E0C44
+
+#define mmMME3_CTRL_SHADOW_3_TENSOR_L_LOOP_STRIDE_2 0x1E0C48
+
+#define mmMME3_CTRL_SHADOW_3_TENSOR_L_LOOP_STRIDE_3 0x1E0C4C
+
+#define mmMME3_CTRL_SHADOW_3_TENSOR_L_LOOP_STRIDE_4 0x1E0C50
+
+#define mmMME3_CTRL_SHADOW_3_TENSOR_L_ROI_SIZE_0 0x1E0C54
+
+#define mmMME3_CTRL_SHADOW_3_TENSOR_L_ROI_SIZE_1 0x1E0C58
+
+#define mmMME3_CTRL_SHADOW_3_TENSOR_L_ROI_SIZE_2 0x1E0C5C
+
+#define mmMME3_CTRL_SHADOW_3_TENSOR_L_ROI_SIZE_3 0x1E0C60
+
+#define mmMME3_CTRL_SHADOW_3_TENSOR_L_SPATIAL_STRIDES_0 0x1E0C64
+
+#define mmMME3_CTRL_SHADOW_3_TENSOR_L_SPATIAL_STRIDES_1 0x1E0C68
+
+#define mmMME3_CTRL_SHADOW_3_TENSOR_L_SPATIAL_STRIDES_2 0x1E0C6C
+
+#define mmMME3_CTRL_SHADOW_3_TENSOR_L_SPATIAL_STRIDES_3 0x1E0C70
+
+#define mmMME3_CTRL_SHADOW_3_TENSOR_L_SPATIAL_SIZE_MINUS_1 0x1E0C74
+
+#define mmMME3_CTRL_SHADOW_3_AGU_L_LOCAL_ROI_BASE_OFFSET_0 0x1E0C78
+
+#define mmMME3_CTRL_SHADOW_3_AGU_L_LOCAL_ROI_BASE_OFFSET_1 0x1E0C7C
+
+#define mmMME3_CTRL_SHADOW_3_AGU_L_LOCAL_ROI_BASE_OFFSET_2 0x1E0C80
+
+#define mmMME3_CTRL_SHADOW_3_AGU_L_LOCAL_ROI_BASE_OFFSET_3 0x1E0C84
+
+#define mmMME3_CTRL_SHADOW_3_AGU_L_LOCAL_ROI_BASE_OFFSET_4 0x1E0C88
+
+#define mmMME3_CTRL_SHADOW_3_AGU_L_LOCAL_START_OFFSET_0 0x1E0C8C
+
+#define mmMME3_CTRL_SHADOW_3_AGU_L_LOCAL_START_OFFSET_1 0x1E0C90
+
+#define mmMME3_CTRL_SHADOW_3_AGU_L_LOCAL_START_OFFSET_2 0x1E0C94
+
+#define mmMME3_CTRL_SHADOW_3_AGU_L_LOCAL_START_OFFSET_3 0x1E0C98
+
+#define mmMME3_CTRL_SHADOW_3_AGU_L_REMOTE_ROI_BASE_OFFSET_0 0x1E0C9C
+
+#define mmMME3_CTRL_SHADOW_3_AGU_L_REMOTE_ROI_BASE_OFFSET_1 0x1E0CA0
+
+#define mmMME3_CTRL_SHADOW_3_AGU_L_REMOTE_ROI_BASE_OFFSET_2 0x1E0CA4
+
+#define mmMME3_CTRL_SHADOW_3_AGU_L_REMOTE_ROI_BASE_OFFSET_3 0x1E0CA8
+
+#define mmMME3_CTRL_SHADOW_3_AGU_L_REMOTE_ROI_BASE_OFFSET_4 0x1E0CAC
+
+#define mmMME3_CTRL_SHADOW_3_AGU_L_REMOTE_START_OFFSET_0 0x1E0CB0
+
+#define mmMME3_CTRL_SHADOW_3_AGU_L_REMOTE_START_OFFSET_1 0x1E0CB4
+
+#define mmMME3_CTRL_SHADOW_3_AGU_L_REMOTE_START_OFFSET_2 0x1E0CB8
+
+#define mmMME3_CTRL_SHADOW_3_AGU_L_REMOTE_START_OFFSET_3 0x1E0CBC
+
+#define mmMME3_CTRL_SHADOW_3_TENSOR_O_VALID_ELEMENTS_0 0x1E0CC0
+
+#define mmMME3_CTRL_SHADOW_3_TENSOR_O_VALID_ELEMENTS_1 0x1E0CC4
+
+#define mmMME3_CTRL_SHADOW_3_TENSOR_O_VALID_ELEMENTS_2 0x1E0CC8
+
+#define mmMME3_CTRL_SHADOW_3_TENSOR_O_VALID_ELEMENTS_3 0x1E0CCC
+
+#define mmMME3_CTRL_SHADOW_3_TENSOR_O_VALID_ELEMENTS_4 0x1E0CD0
+
+#define mmMME3_CTRL_SHADOW_3_TENSOR_O_LOOP_STRIDE_0 0x1E0CD4
+
+#define mmMME3_CTRL_SHADOW_3_TENSOR_O_LOOP_STRIDE_1 0x1E0CD8
+
+#define mmMME3_CTRL_SHADOW_3_TENSOR_O_LOOP_STRIDE_2 0x1E0CDC
+
+#define mmMME3_CTRL_SHADOW_3_TENSOR_O_LOOP_STRIDE_3 0x1E0CE0
+
+#define mmMME3_CTRL_SHADOW_3_TENSOR_O_LOOP_STRIDE_4 0x1E0CE4
+
+#define mmMME3_CTRL_SHADOW_3_TENSOR_O_ROI_SIZE_0 0x1E0CE8
+
+#define mmMME3_CTRL_SHADOW_3_TENSOR_O_ROI_SIZE_1 0x1E0CEC
+
+#define mmMME3_CTRL_SHADOW_3_TENSOR_O_ROI_SIZE_2 0x1E0CF0
+
+#define mmMME3_CTRL_SHADOW_3_TENSOR_O_ROI_SIZE_3 0x1E0CF4
+
+#define mmMME3_CTRL_SHADOW_3_TENSOR_O_SPATIAL_STRIDES_0 0x1E0CF8
+
+#define mmMME3_CTRL_SHADOW_3_TENSOR_O_SPATIAL_STRIDES_1 0x1E0CFC
+
+#define mmMME3_CTRL_SHADOW_3_TENSOR_O_SPATIAL_STRIDES_2 0x1E0D00
+
+#define mmMME3_CTRL_SHADOW_3_TENSOR_O_SPATIAL_STRIDES_3 0x1E0D04
+
+#define mmMME3_CTRL_SHADOW_3_TENSOR_O_SPATIAL_SIZE_MINUS_1 0x1E0D08
+
+#define mmMME3_CTRL_SHADOW_3_AGU_O_LOCAL_ROI_BASE_OFFSET_0 0x1E0D0C
+
+#define mmMME3_CTRL_SHADOW_3_AGU_O_LOCAL_ROI_BASE_OFFSET_1 0x1E0D10
+
+#define mmMME3_CTRL_SHADOW_3_AGU_O_LOCAL_ROI_BASE_OFFSET_2 0x1E0D14
+
+#define mmMME3_CTRL_SHADOW_3_AGU_O_LOCAL_ROI_BASE_OFFSET_3 0x1E0D18
+
+#define mmMME3_CTRL_SHADOW_3_AGU_O_LOCAL_ROI_BASE_OFFSET_4 0x1E0D1C
+
+#define mmMME3_CTRL_SHADOW_3_AGU_O_LOCAL_START_OFFSET_0 0x1E0D20
+
+#define mmMME3_CTRL_SHADOW_3_AGU_O_LOCAL_START_OFFSET_1 0x1E0D24
+
+#define mmMME3_CTRL_SHADOW_3_AGU_O_LOCAL_START_OFFSET_2 0x1E0D28
+
+#define mmMME3_CTRL_SHADOW_3_AGU_O_LOCAL_START_OFFSET_3 0x1E0D2C
+
+#define mmMME3_CTRL_SHADOW_3_AGU_O_REMOTE_ROI_BASE_OFFSET_0 0x1E0D30
+
+#define mmMME3_CTRL_SHADOW_3_AGU_O_REMOTE_ROI_BASE_OFFSET_1 0x1E0D34
+
+#define mmMME3_CTRL_SHADOW_3_AGU_O_REMOTE_ROI_BASE_OFFSET_2 0x1E0D38
+
+#define mmMME3_CTRL_SHADOW_3_AGU_O_REMOTE_ROI_BASE_OFFSET_3 0x1E0D3C
+
+#define mmMME3_CTRL_SHADOW_3_AGU_O_REMOTE_ROI_BASE_OFFSET_4 0x1E0D40
+
+#define mmMME3_CTRL_SHADOW_3_AGU_O_REMOTE_START_OFFSET_0 0x1E0D44
+
+#define mmMME3_CTRL_SHADOW_3_AGU_O_REMOTE_START_OFFSET_1 0x1E0D48
+
+#define mmMME3_CTRL_SHADOW_3_AGU_O_REMOTE_START_OFFSET_2 0x1E0D4C
+
+#define mmMME3_CTRL_SHADOW_3_AGU_O_REMOTE_START_OFFSET_3 0x1E0D50
+
+#define mmMME3_CTRL_SHADOW_3_DESC_SB_REPEAT 0x1E0D54
+
+#define mmMME3_CTRL_SHADOW_3_DESC_RATE_LIMITER 0x1E0D58
+
+#define mmMME3_CTRL_SHADOW_3_DESC_SYNC_OBJECT_ADDR_LOW_LOCAL 0x1E0D5C
+
+#define mmMME3_CTRL_SHADOW_3_DESC_SYNC_OBJECT_ADDR_LOW_REMOTE 0x1E0D60
+
+#define mmMME3_CTRL_SHADOW_3_DESC_SYNC_OBJECT_ADDR_HIGH 0x1E0D64
+
+#define mmMME3_CTRL_SHADOW_3_DESC_SYNC_OBJECT_DATA 0x1E0D68
+
+#define mmMME3_CTRL_SHADOW_3_DESC_AXI_USER_DATA 0x1E0D6C
+
+#define mmMME3_CTRL_SHADOW_3_DESC_PERF_EVT_S 0x1E0D70
+
+#define mmMME3_CTRL_SHADOW_3_DESC_PERF_EVT_L_LOCAL 0x1E0D74
+
+#define mmMME3_CTRL_SHADOW_3_DESC_PERF_EVT_L_REMOTE 0x1E0D78
+
+#define mmMME3_CTRL_SHADOW_3_DESC_PERF_EVT_O_LOCAL 0x1E0D7C
+
+#define mmMME3_CTRL_SHADOW_3_DESC_PERF_EVT_O_REMOTE 0x1E0D80
+
+#define mmMME3_CTRL_SHADOW_3_DESC_PADDING_VALUE_S 0x1E0D84
+
+#define mmMME3_CTRL_SHADOW_3_DESC_PADDING_VALUE_L 0x1E0D88
+
+#define mmMME3_CTRL_SHADOW_3_DESC_META_DATA_AGU_S 0x1E0D8C
+
+#define mmMME3_CTRL_SHADOW_3_DESC_META_DATA_AGU_L_LOCAL 0x1E0D90
+
+#define mmMME3_CTRL_SHADOW_3_DESC_META_DATA_AGU_L_REMOTE 0x1E0D94
+
+#define mmMME3_CTRL_SHADOW_3_DESC_META_DATA_AGU_O_LOCAL 0x1E0D98
+
+#define mmMME3_CTRL_SHADOW_3_DESC_META_DATA_AGU_O_REMOTE 0x1E0D9C
+
+#define mmMME3_CTRL_SHADOW_3_DESC_PCU_RL_SATURATION 0x1E0DA0
+
+#define mmMME3_CTRL_SHADOW_3_DESC_DUMMY 0x1E0DA4
+
+#endif /* ASIC_REG_MME3_CTRL_REGS_H_ */
diff --git a/drivers/accel/habanalabs/include/gaudi/asic_reg/mmu_up_regs.h b/drivers/accel/habanalabs/include/gaudi/asic_reg/mmu_up_regs.h
new file mode 100644
index 0000000000..61465b5998
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi/asic_reg/mmu_up_regs.h
@@ -0,0 +1,72 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2016-2018 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ ** DO NOT EDIT BELOW **
+ ************************************/
+
+#ifndef ASIC_REG_MMU_UP_REGS_H_
+#define ASIC_REG_MMU_UP_REGS_H_
+
+/*
+ *****************************************
+ * MMU_UP (Prototype: MMU)
+ *****************************************
+ */
+
+#define mmMMU_UP_MMU_ENABLE 0xC1100C
+
+#define mmMMU_UP_FORCE_ORDERING 0xC11010
+
+#define mmMMU_UP_FEATURE_ENABLE 0xC11014
+
+#define mmMMU_UP_VA_ORDERING_MASK_31_7 0xC11018
+
+#define mmMMU_UP_VA_ORDERING_MASK_49_32 0xC1101C
+
+#define mmMMU_UP_LOG2_DDR_SIZE 0xC11020
+
+#define mmMMU_UP_SCRAMBLER 0xC11024
+
+#define mmMMU_UP_MEM_INIT_BUSY 0xC11028
+
+#define mmMMU_UP_SPI_MASK 0xC1102C
+
+#define mmMMU_UP_SPI_CAUSE 0xC11030
+
+#define mmMMU_UP_PAGE_ERROR_CAPTURE 0xC11034
+
+#define mmMMU_UP_PAGE_ERROR_CAPTURE_VA 0xC11038
+
+#define mmMMU_UP_ACCESS_ERROR_CAPTURE 0xC1103C
+
+#define mmMMU_UP_ACCESS_ERROR_CAPTURE_VA 0xC11040
+
+#define mmMMU_UP_SPI_INTERRUPT_CLR 0xC11044
+
+#define mmMMU_UP_SPI_INTERRUPT_MASK 0xC11048
+
+#define mmMMU_UP_DBG_MEM_WRAP_RM 0xC1104C
+
+#define mmMMU_UP_SPI_CAUSE_CLR 0xC11050
+
+#define mmMMU_UP_SLICE_CREDIT 0xC11054
+
+#define mmMMU_UP_PIPE_CREDIT 0xC11058
+
+#define mmMMU_UP_RAZWI_WRITE_VLD 0xC1105C
+
+#define mmMMU_UP_RAZWI_WRITE_ID 0xC11060
+
+#define mmMMU_UP_RAZWI_READ_VLD 0xC11064
+
+#define mmMMU_UP_RAZWI_READ_ID 0xC11068
+
+#define mmMMU_UP_MMU_BYPASS 0xC1106C
+
+#endif /* ASIC_REG_MMU_UP_REGS_H_ */
diff --git a/drivers/accel/habanalabs/include/gaudi/asic_reg/nic0_qm0_masks.h b/drivers/accel/habanalabs/include/gaudi/asic_reg/nic0_qm0_masks.h
new file mode 100644
index 0000000000..bd37b64521
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi/asic_reg/nic0_qm0_masks.h
@@ -0,0 +1,800 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2016-2018 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ ** DO NOT EDIT BELOW **
+ ************************************/
+
+#ifndef ASIC_REG_NIC0_QM0_MASKS_H_
+#define ASIC_REG_NIC0_QM0_MASKS_H_
+
+/*
+ *****************************************
+ * NIC0_QM0 (Prototype: QMAN)
+ *****************************************
+ */
+
+/* NIC0_QM0_GLBL_CFG0 */
+#define NIC0_QM0_GLBL_CFG0_PQF_EN_SHIFT 0
+#define NIC0_QM0_GLBL_CFG0_PQF_EN_MASK 0xF
+#define NIC0_QM0_GLBL_CFG0_CQF_EN_SHIFT 4
+#define NIC0_QM0_GLBL_CFG0_CQF_EN_MASK 0x1F0
+#define NIC0_QM0_GLBL_CFG0_CP_EN_SHIFT 9
+#define NIC0_QM0_GLBL_CFG0_CP_EN_MASK 0x3E00
+
+/* NIC0_QM0_GLBL_CFG1 */
+#define NIC0_QM0_GLBL_CFG1_PQF_STOP_SHIFT 0
+#define NIC0_QM0_GLBL_CFG1_PQF_STOP_MASK 0xF
+#define NIC0_QM0_GLBL_CFG1_CQF_STOP_SHIFT 4
+#define NIC0_QM0_GLBL_CFG1_CQF_STOP_MASK 0x1F0
+#define NIC0_QM0_GLBL_CFG1_CP_STOP_SHIFT 9
+#define NIC0_QM0_GLBL_CFG1_CP_STOP_MASK 0x3E00
+#define NIC0_QM0_GLBL_CFG1_PQF_FLUSH_SHIFT 16
+#define NIC0_QM0_GLBL_CFG1_PQF_FLUSH_MASK 0xF0000
+#define NIC0_QM0_GLBL_CFG1_CQF_FLUSH_SHIFT 20
+#define NIC0_QM0_GLBL_CFG1_CQF_FLUSH_MASK 0x1F00000
+#define NIC0_QM0_GLBL_CFG1_CP_FLUSH_SHIFT 25
+#define NIC0_QM0_GLBL_CFG1_CP_FLUSH_MASK 0x3E000000
+
+/* NIC0_QM0_GLBL_PROT */
+#define NIC0_QM0_GLBL_PROT_PQF_SHIFT 0
+#define NIC0_QM0_GLBL_PROT_PQF_MASK 0xF
+#define NIC0_QM0_GLBL_PROT_CQF_SHIFT 4
+#define NIC0_QM0_GLBL_PROT_CQF_MASK 0x1F0
+#define NIC0_QM0_GLBL_PROT_CP_SHIFT 9
+#define NIC0_QM0_GLBL_PROT_CP_MASK 0x3E00
+#define NIC0_QM0_GLBL_PROT_ERR_SHIFT 14
+#define NIC0_QM0_GLBL_PROT_ERR_MASK 0x4000
+#define NIC0_QM0_GLBL_PROT_ARB_SHIFT 15
+#define NIC0_QM0_GLBL_PROT_ARB_MASK 0x8000
+
+/* NIC0_QM0_GLBL_ERR_CFG */
+#define NIC0_QM0_GLBL_ERR_CFG_PQF_ERR_MSG_EN_SHIFT 0
+#define NIC0_QM0_GLBL_ERR_CFG_PQF_ERR_MSG_EN_MASK 0xF
+#define NIC0_QM0_GLBL_ERR_CFG_CQF_ERR_MSG_EN_SHIFT 4
+#define NIC0_QM0_GLBL_ERR_CFG_CQF_ERR_MSG_EN_MASK 0x1F0
+#define NIC0_QM0_GLBL_ERR_CFG_CP_ERR_MSG_EN_SHIFT 9
+#define NIC0_QM0_GLBL_ERR_CFG_CP_ERR_MSG_EN_MASK 0x3E00
+#define NIC0_QM0_GLBL_ERR_CFG_PQF_STOP_ON_ERR_SHIFT 16
+#define NIC0_QM0_GLBL_ERR_CFG_PQF_STOP_ON_ERR_MASK 0xF0000
+#define NIC0_QM0_GLBL_ERR_CFG_CQF_STOP_ON_ERR_SHIFT 20
+#define NIC0_QM0_GLBL_ERR_CFG_CQF_STOP_ON_ERR_MASK 0x1F00000
+#define NIC0_QM0_GLBL_ERR_CFG_CP_STOP_ON_ERR_SHIFT 25
+#define NIC0_QM0_GLBL_ERR_CFG_CP_STOP_ON_ERR_MASK 0x3E000000
+#define NIC0_QM0_GLBL_ERR_CFG_ARB_STOP_ON_ERR_SHIFT 31
+#define NIC0_QM0_GLBL_ERR_CFG_ARB_STOP_ON_ERR_MASK 0x80000000
+
+/* NIC0_QM0_GLBL_SECURE_PROPS */
+#define NIC0_QM0_GLBL_SECURE_PROPS_0_ASID_SHIFT 0
+#define NIC0_QM0_GLBL_SECURE_PROPS_0_ASID_MASK 0x3FF
+#define NIC0_QM0_GLBL_SECURE_PROPS_1_ASID_SHIFT 0
+#define NIC0_QM0_GLBL_SECURE_PROPS_1_ASID_MASK 0x3FF
+#define NIC0_QM0_GLBL_SECURE_PROPS_2_ASID_SHIFT 0
+#define NIC0_QM0_GLBL_SECURE_PROPS_2_ASID_MASK 0x3FF
+#define NIC0_QM0_GLBL_SECURE_PROPS_3_ASID_SHIFT 0
+#define NIC0_QM0_GLBL_SECURE_PROPS_3_ASID_MASK 0x3FF
+#define NIC0_QM0_GLBL_SECURE_PROPS_4_ASID_SHIFT 0
+#define NIC0_QM0_GLBL_SECURE_PROPS_4_ASID_MASK 0x3FF
+#define NIC0_QM0_GLBL_SECURE_PROPS_0_MMBP_SHIFT 10
+#define NIC0_QM0_GLBL_SECURE_PROPS_0_MMBP_MASK 0x400
+#define NIC0_QM0_GLBL_SECURE_PROPS_1_MMBP_SHIFT 10
+#define NIC0_QM0_GLBL_SECURE_PROPS_1_MMBP_MASK 0x400
+#define NIC0_QM0_GLBL_SECURE_PROPS_2_MMBP_SHIFT 10
+#define NIC0_QM0_GLBL_SECURE_PROPS_2_MMBP_MASK 0x400
+#define NIC0_QM0_GLBL_SECURE_PROPS_3_MMBP_SHIFT 10
+#define NIC0_QM0_GLBL_SECURE_PROPS_3_MMBP_MASK 0x400
+#define NIC0_QM0_GLBL_SECURE_PROPS_4_MMBP_SHIFT 10
+#define NIC0_QM0_GLBL_SECURE_PROPS_4_MMBP_MASK 0x400
+
+/* NIC0_QM0_GLBL_NON_SECURE_PROPS */
+#define NIC0_QM0_GLBL_NON_SECURE_PROPS_0_ASID_SHIFT 0
+#define NIC0_QM0_GLBL_NON_SECURE_PROPS_0_ASID_MASK 0x3FF
+#define NIC0_QM0_GLBL_NON_SECURE_PROPS_1_ASID_SHIFT 0
+#define NIC0_QM0_GLBL_NON_SECURE_PROPS_1_ASID_MASK 0x3FF
+#define NIC0_QM0_GLBL_NON_SECURE_PROPS_2_ASID_SHIFT 0
+#define NIC0_QM0_GLBL_NON_SECURE_PROPS_2_ASID_MASK 0x3FF
+#define NIC0_QM0_GLBL_NON_SECURE_PROPS_3_ASID_SHIFT 0
+#define NIC0_QM0_GLBL_NON_SECURE_PROPS_3_ASID_MASK 0x3FF
+#define NIC0_QM0_GLBL_NON_SECURE_PROPS_4_ASID_SHIFT 0
+#define NIC0_QM0_GLBL_NON_SECURE_PROPS_4_ASID_MASK 0x3FF
+#define NIC0_QM0_GLBL_NON_SECURE_PROPS_0_MMBP_SHIFT 10
+#define NIC0_QM0_GLBL_NON_SECURE_PROPS_0_MMBP_MASK 0x400
+#define NIC0_QM0_GLBL_NON_SECURE_PROPS_1_MMBP_SHIFT 10
+#define NIC0_QM0_GLBL_NON_SECURE_PROPS_1_MMBP_MASK 0x400
+#define NIC0_QM0_GLBL_NON_SECURE_PROPS_2_MMBP_SHIFT 10
+#define NIC0_QM0_GLBL_NON_SECURE_PROPS_2_MMBP_MASK 0x400
+#define NIC0_QM0_GLBL_NON_SECURE_PROPS_3_MMBP_SHIFT 10
+#define NIC0_QM0_GLBL_NON_SECURE_PROPS_3_MMBP_MASK 0x400
+#define NIC0_QM0_GLBL_NON_SECURE_PROPS_4_MMBP_SHIFT 10
+#define NIC0_QM0_GLBL_NON_SECURE_PROPS_4_MMBP_MASK 0x400
+
+/* NIC0_QM0_GLBL_STS0 */
+#define NIC0_QM0_GLBL_STS0_PQF_IDLE_SHIFT 0
+#define NIC0_QM0_GLBL_STS0_PQF_IDLE_MASK 0xF
+#define NIC0_QM0_GLBL_STS0_CQF_IDLE_SHIFT 4
+#define NIC0_QM0_GLBL_STS0_CQF_IDLE_MASK 0x1F0
+#define NIC0_QM0_GLBL_STS0_CP_IDLE_SHIFT 9
+#define NIC0_QM0_GLBL_STS0_CP_IDLE_MASK 0x3E00
+#define NIC0_QM0_GLBL_STS0_PQF_IS_STOP_SHIFT 16
+#define NIC0_QM0_GLBL_STS0_PQF_IS_STOP_MASK 0xF0000
+#define NIC0_QM0_GLBL_STS0_CQF_IS_STOP_SHIFT 20
+#define NIC0_QM0_GLBL_STS0_CQF_IS_STOP_MASK 0x1F00000
+#define NIC0_QM0_GLBL_STS0_CP_IS_STOP_SHIFT 25
+#define NIC0_QM0_GLBL_STS0_CP_IS_STOP_MASK 0x3E000000
+#define NIC0_QM0_GLBL_STS0_ARB_IS_STOP_SHIFT 31
+#define NIC0_QM0_GLBL_STS0_ARB_IS_STOP_MASK 0x80000000
+
+/* NIC0_QM0_GLBL_STS1 */
+#define NIC0_QM0_GLBL_STS1_PQF_RD_ERR_SHIFT 0
+#define NIC0_QM0_GLBL_STS1_PQF_RD_ERR_MASK 0x1
+#define NIC0_QM0_GLBL_STS1_CQF_RD_ERR_SHIFT 1
+#define NIC0_QM0_GLBL_STS1_CQF_RD_ERR_MASK 0x2
+#define NIC0_QM0_GLBL_STS1_CP_RD_ERR_SHIFT 2
+#define NIC0_QM0_GLBL_STS1_CP_RD_ERR_MASK 0x4
+#define NIC0_QM0_GLBL_STS1_CP_UNDEF_CMD_ERR_SHIFT 3
+#define NIC0_QM0_GLBL_STS1_CP_UNDEF_CMD_ERR_MASK 0x8
+#define NIC0_QM0_GLBL_STS1_CP_STOP_OP_SHIFT 4
+#define NIC0_QM0_GLBL_STS1_CP_STOP_OP_MASK 0x10
+#define NIC0_QM0_GLBL_STS1_CP_MSG_WR_ERR_SHIFT 5
+#define NIC0_QM0_GLBL_STS1_CP_MSG_WR_ERR_MASK 0x20
+#define NIC0_QM0_GLBL_STS1_CP_WREG_ERR_SHIFT 6
+#define NIC0_QM0_GLBL_STS1_CP_WREG_ERR_MASK 0x40
+#define NIC0_QM0_GLBL_STS1_CP_FENCE0_OVF_ERR_SHIFT 8
+#define NIC0_QM0_GLBL_STS1_CP_FENCE0_OVF_ERR_MASK 0x100
+#define NIC0_QM0_GLBL_STS1_CP_FENCE1_OVF_ERR_SHIFT 9
+#define NIC0_QM0_GLBL_STS1_CP_FENCE1_OVF_ERR_MASK 0x200
+#define NIC0_QM0_GLBL_STS1_CP_FENCE2_OVF_ERR_SHIFT 10
+#define NIC0_QM0_GLBL_STS1_CP_FENCE2_OVF_ERR_MASK 0x400
+#define NIC0_QM0_GLBL_STS1_CP_FENCE3_OVF_ERR_SHIFT 11
+#define NIC0_QM0_GLBL_STS1_CP_FENCE3_OVF_ERR_MASK 0x800
+#define NIC0_QM0_GLBL_STS1_CP_FENCE0_UDF_ERR_SHIFT 12
+#define NIC0_QM0_GLBL_STS1_CP_FENCE0_UDF_ERR_MASK 0x1000
+#define NIC0_QM0_GLBL_STS1_CP_FENCE1_UDF_ERR_SHIFT 13
+#define NIC0_QM0_GLBL_STS1_CP_FENCE1_UDF_ERR_MASK 0x2000
+#define NIC0_QM0_GLBL_STS1_CP_FENCE2_UDF_ERR_SHIFT 14
+#define NIC0_QM0_GLBL_STS1_CP_FENCE2_UDF_ERR_MASK 0x4000
+#define NIC0_QM0_GLBL_STS1_CP_FENCE3_UDF_ERR_SHIFT 15
+#define NIC0_QM0_GLBL_STS1_CP_FENCE3_UDF_ERR_MASK 0x8000
+
+/* NIC0_QM0_GLBL_STS1_4 */
+#define NIC0_QM0_GLBL_STS1_4_CQF_RD_ERR_SHIFT 1
+#define NIC0_QM0_GLBL_STS1_4_CQF_RD_ERR_MASK 0x2
+#define NIC0_QM0_GLBL_STS1_4_CP_RD_ERR_SHIFT 2
+#define NIC0_QM0_GLBL_STS1_4_CP_RD_ERR_MASK 0x4
+#define NIC0_QM0_GLBL_STS1_4_CP_UNDEF_CMD_ERR_SHIFT 3
+#define NIC0_QM0_GLBL_STS1_4_CP_UNDEF_CMD_ERR_MASK 0x8
+#define NIC0_QM0_GLBL_STS1_4_CP_STOP_OP_SHIFT 4
+#define NIC0_QM0_GLBL_STS1_4_CP_STOP_OP_MASK 0x10
+#define NIC0_QM0_GLBL_STS1_4_CP_MSG_WR_ERR_SHIFT 5
+#define NIC0_QM0_GLBL_STS1_4_CP_MSG_WR_ERR_MASK 0x20
+#define NIC0_QM0_GLBL_STS1_4_CP_WREG_ERR_SHIFT 6
+#define NIC0_QM0_GLBL_STS1_4_CP_WREG_ERR_MASK 0x40
+#define NIC0_QM0_GLBL_STS1_4_CP_FENCE0_OVF_ERR_SHIFT 8
+#define NIC0_QM0_GLBL_STS1_4_CP_FENCE0_OVF_ERR_MASK 0x100
+#define NIC0_QM0_GLBL_STS1_4_CP_FENCE1_OVF_ERR_SHIFT 9
+#define NIC0_QM0_GLBL_STS1_4_CP_FENCE1_OVF_ERR_MASK 0x200
+#define NIC0_QM0_GLBL_STS1_4_CP_FENCE2_OVF_ERR_SHIFT 10
+#define NIC0_QM0_GLBL_STS1_4_CP_FENCE2_OVF_ERR_MASK 0x400
+#define NIC0_QM0_GLBL_STS1_4_CP_FENCE3_OVF_ERR_SHIFT 11
+#define NIC0_QM0_GLBL_STS1_4_CP_FENCE3_OVF_ERR_MASK 0x800
+#define NIC0_QM0_GLBL_STS1_4_CP_FENCE0_UDF_ERR_SHIFT 12
+#define NIC0_QM0_GLBL_STS1_4_CP_FENCE0_UDF_ERR_MASK 0x1000
+#define NIC0_QM0_GLBL_STS1_4_CP_FENCE1_UDF_ERR_SHIFT 13
+#define NIC0_QM0_GLBL_STS1_4_CP_FENCE1_UDF_ERR_MASK 0x2000
+#define NIC0_QM0_GLBL_STS1_4_CP_FENCE2_UDF_ERR_SHIFT 14
+#define NIC0_QM0_GLBL_STS1_4_CP_FENCE2_UDF_ERR_MASK 0x4000
+#define NIC0_QM0_GLBL_STS1_4_CP_FENCE3_UDF_ERR_SHIFT 15
+#define NIC0_QM0_GLBL_STS1_4_CP_FENCE3_UDF_ERR_MASK 0x8000
+
+/* NIC0_QM0_GLBL_MSG_EN */
+#define NIC0_QM0_GLBL_MSG_EN_PQF_RD_ERR_SHIFT 0
+#define NIC0_QM0_GLBL_MSG_EN_PQF_RD_ERR_MASK 0x1
+#define NIC0_QM0_GLBL_MSG_EN_CQF_RD_ERR_SHIFT 1
+#define NIC0_QM0_GLBL_MSG_EN_CQF_RD_ERR_MASK 0x2
+#define NIC0_QM0_GLBL_MSG_EN_CP_RD_ERR_SHIFT 2
+#define NIC0_QM0_GLBL_MSG_EN_CP_RD_ERR_MASK 0x4
+#define NIC0_QM0_GLBL_MSG_EN_CP_UNDEF_CMD_ERR_SHIFT 3
+#define NIC0_QM0_GLBL_MSG_EN_CP_UNDEF_CMD_ERR_MASK 0x8
+#define NIC0_QM0_GLBL_MSG_EN_CP_STOP_OP_SHIFT 4
+#define NIC0_QM0_GLBL_MSG_EN_CP_STOP_OP_MASK 0x10
+#define NIC0_QM0_GLBL_MSG_EN_CP_MSG_WR_ERR_SHIFT 5
+#define NIC0_QM0_GLBL_MSG_EN_CP_MSG_WR_ERR_MASK 0x20
+#define NIC0_QM0_GLBL_MSG_EN_CP_WREG_ERR_SHIFT 6
+#define NIC0_QM0_GLBL_MSG_EN_CP_WREG_ERR_MASK 0x40
+#define NIC0_QM0_GLBL_MSG_EN_CP_FENCE0_OVF_ERR_SHIFT 8
+#define NIC0_QM0_GLBL_MSG_EN_CP_FENCE0_OVF_ERR_MASK 0x100
+#define NIC0_QM0_GLBL_MSG_EN_CP_FENCE1_OVF_ERR_SHIFT 9
+#define NIC0_QM0_GLBL_MSG_EN_CP_FENCE1_OVF_ERR_MASK 0x200
+#define NIC0_QM0_GLBL_MSG_EN_CP_FENCE2_OVF_ERR_SHIFT 10
+#define NIC0_QM0_GLBL_MSG_EN_CP_FENCE2_OVF_ERR_MASK 0x400
+#define NIC0_QM0_GLBL_MSG_EN_CP_FENCE3_OVF_ERR_SHIFT 11
+#define NIC0_QM0_GLBL_MSG_EN_CP_FENCE3_OVF_ERR_MASK 0x800
+#define NIC0_QM0_GLBL_MSG_EN_CP_FENCE0_UDF_ERR_SHIFT 12
+#define NIC0_QM0_GLBL_MSG_EN_CP_FENCE0_UDF_ERR_MASK 0x1000
+#define NIC0_QM0_GLBL_MSG_EN_CP_FENCE1_UDF_ERR_SHIFT 13
+#define NIC0_QM0_GLBL_MSG_EN_CP_FENCE1_UDF_ERR_MASK 0x2000
+#define NIC0_QM0_GLBL_MSG_EN_CP_FENCE2_UDF_ERR_SHIFT 14
+#define NIC0_QM0_GLBL_MSG_EN_CP_FENCE2_UDF_ERR_MASK 0x4000
+#define NIC0_QM0_GLBL_MSG_EN_CP_FENCE3_UDF_ERR_SHIFT 15
+#define NIC0_QM0_GLBL_MSG_EN_CP_FENCE3_UDF_ERR_MASK 0x8000
+
+/* NIC0_QM0_GLBL_MSG_EN_4 */
+#define NIC0_QM0_GLBL_MSG_EN_4_CQF_RD_ERR_SHIFT 1
+#define NIC0_QM0_GLBL_MSG_EN_4_CQF_RD_ERR_MASK 0x2
+#define NIC0_QM0_GLBL_MSG_EN_4_CP_RD_ERR_SHIFT 2
+#define NIC0_QM0_GLBL_MSG_EN_4_CP_RD_ERR_MASK 0x4
+#define NIC0_QM0_GLBL_MSG_EN_4_CP_UNDEF_CMD_ERR_SHIFT 3
+#define NIC0_QM0_GLBL_MSG_EN_4_CP_UNDEF_CMD_ERR_MASK 0x8
+#define NIC0_QM0_GLBL_MSG_EN_4_CP_STOP_OP_SHIFT 4
+#define NIC0_QM0_GLBL_MSG_EN_4_CP_STOP_OP_MASK 0x10
+#define NIC0_QM0_GLBL_MSG_EN_4_CP_MSG_WR_ERR_SHIFT 5
+#define NIC0_QM0_GLBL_MSG_EN_4_CP_MSG_WR_ERR_MASK 0x20
+#define NIC0_QM0_GLBL_MSG_EN_4_CP_WREG_ERR_SHIFT 6
+#define NIC0_QM0_GLBL_MSG_EN_4_CP_WREG_ERR_MASK 0x40
+#define NIC0_QM0_GLBL_MSG_EN_4_CP_FENCE0_OVF_ERR_SHIFT 8
+#define NIC0_QM0_GLBL_MSG_EN_4_CP_FENCE0_OVF_ERR_MASK 0x100
+#define NIC0_QM0_GLBL_MSG_EN_4_CP_FENCE1_OVF_ERR_SHIFT 9
+#define NIC0_QM0_GLBL_MSG_EN_4_CP_FENCE1_OVF_ERR_MASK 0x200
+#define NIC0_QM0_GLBL_MSG_EN_4_CP_FENCE2_OVF_ERR_SHIFT 10
+#define NIC0_QM0_GLBL_MSG_EN_4_CP_FENCE2_OVF_ERR_MASK 0x400
+#define NIC0_QM0_GLBL_MSG_EN_4_CP_FENCE3_OVF_ERR_SHIFT 11
+#define NIC0_QM0_GLBL_MSG_EN_4_CP_FENCE3_OVF_ERR_MASK 0x800
+#define NIC0_QM0_GLBL_MSG_EN_4_CP_FENCE0_UDF_ERR_SHIFT 12
+#define NIC0_QM0_GLBL_MSG_EN_4_CP_FENCE0_UDF_ERR_MASK 0x1000
+#define NIC0_QM0_GLBL_MSG_EN_4_CP_FENCE1_UDF_ERR_SHIFT 13
+#define NIC0_QM0_GLBL_MSG_EN_4_CP_FENCE1_UDF_ERR_MASK 0x2000
+#define NIC0_QM0_GLBL_MSG_EN_4_CP_FENCE2_UDF_ERR_SHIFT 14
+#define NIC0_QM0_GLBL_MSG_EN_4_CP_FENCE2_UDF_ERR_MASK 0x4000
+#define NIC0_QM0_GLBL_MSG_EN_4_CP_FENCE3_UDF_ERR_SHIFT 15
+#define NIC0_QM0_GLBL_MSG_EN_4_CP_FENCE3_UDF_ERR_MASK 0x8000
+
+/* NIC0_QM0_PQ_BASE_LO */
+#define NIC0_QM0_PQ_BASE_LO_VAL_SHIFT 0
+#define NIC0_QM0_PQ_BASE_LO_VAL_MASK 0xFFFFFFFF
+
+/* NIC0_QM0_PQ_BASE_HI */
+#define NIC0_QM0_PQ_BASE_HI_VAL_SHIFT 0
+#define NIC0_QM0_PQ_BASE_HI_VAL_MASK 0xFFFFFFFF
+
+/* NIC0_QM0_PQ_SIZE */
+#define NIC0_QM0_PQ_SIZE_VAL_SHIFT 0
+#define NIC0_QM0_PQ_SIZE_VAL_MASK 0xFFFFFFFF
+
+/* NIC0_QM0_PQ_PI */
+#define NIC0_QM0_PQ_PI_VAL_SHIFT 0
+#define NIC0_QM0_PQ_PI_VAL_MASK 0xFFFFFFFF
+
+/* NIC0_QM0_PQ_CI */
+#define NIC0_QM0_PQ_CI_VAL_SHIFT 0
+#define NIC0_QM0_PQ_CI_VAL_MASK 0xFFFFFFFF
+
+/* NIC0_QM0_PQ_CFG0 */
+#define NIC0_QM0_PQ_CFG0_RESERVED_SHIFT 0
+#define NIC0_QM0_PQ_CFG0_RESERVED_MASK 0x1
+
+/* NIC0_QM0_PQ_CFG1 */
+#define NIC0_QM0_PQ_CFG1_CREDIT_LIM_SHIFT 0
+#define NIC0_QM0_PQ_CFG1_CREDIT_LIM_MASK 0xFFFF
+#define NIC0_QM0_PQ_CFG1_MAX_INFLIGHT_SHIFT 16
+#define NIC0_QM0_PQ_CFG1_MAX_INFLIGHT_MASK 0xFFFF0000
+
+/* NIC0_QM0_PQ_ARUSER_31_11 */
+#define NIC0_QM0_PQ_ARUSER_31_11_VAL_SHIFT 0
+#define NIC0_QM0_PQ_ARUSER_31_11_VAL_MASK 0x1FFFFF
+
+/* NIC0_QM0_PQ_STS0 */
+#define NIC0_QM0_PQ_STS0_PQ_CREDIT_CNT_SHIFT 0
+#define NIC0_QM0_PQ_STS0_PQ_CREDIT_CNT_MASK 0xFFFF
+#define NIC0_QM0_PQ_STS0_PQ_FREE_CNT_SHIFT 16
+#define NIC0_QM0_PQ_STS0_PQ_FREE_CNT_MASK 0xFFFF0000
+
+/* NIC0_QM0_PQ_STS1 */
+#define NIC0_QM0_PQ_STS1_PQ_INFLIGHT_CNT_SHIFT 0
+#define NIC0_QM0_PQ_STS1_PQ_INFLIGHT_CNT_MASK 0xFFFF
+#define NIC0_QM0_PQ_STS1_PQ_BUF_EMPTY_SHIFT 30
+#define NIC0_QM0_PQ_STS1_PQ_BUF_EMPTY_MASK 0x40000000
+#define NIC0_QM0_PQ_STS1_PQ_BUSY_SHIFT 31
+#define NIC0_QM0_PQ_STS1_PQ_BUSY_MASK 0x80000000
+
+/* NIC0_QM0_CQ_CFG0 */
+#define NIC0_QM0_CQ_CFG0_RESERVED_SHIFT 0
+#define NIC0_QM0_CQ_CFG0_RESERVED_MASK 0x1
+
+/* NIC0_QM0_CQ_CFG1 */
+#define NIC0_QM0_CQ_CFG1_CREDIT_LIM_SHIFT 0
+#define NIC0_QM0_CQ_CFG1_CREDIT_LIM_MASK 0xFFFF
+#define NIC0_QM0_CQ_CFG1_MAX_INFLIGHT_SHIFT 16
+#define NIC0_QM0_CQ_CFG1_MAX_INFLIGHT_MASK 0xFFFF0000
+
+/* NIC0_QM0_CQ_ARUSER_31_11 */
+#define NIC0_QM0_CQ_ARUSER_31_11_VAL_SHIFT 0
+#define NIC0_QM0_CQ_ARUSER_31_11_VAL_MASK 0x1FFFFF
+
+/* NIC0_QM0_CQ_STS0 */
+#define NIC0_QM0_CQ_STS0_CQ_CREDIT_CNT_SHIFT 0
+#define NIC0_QM0_CQ_STS0_CQ_CREDIT_CNT_MASK 0xFFFF
+#define NIC0_QM0_CQ_STS0_CQ_FREE_CNT_SHIFT 16
+#define NIC0_QM0_CQ_STS0_CQ_FREE_CNT_MASK 0xFFFF0000
+
+/* NIC0_QM0_CQ_STS1 */
+#define NIC0_QM0_CQ_STS1_CQ_INFLIGHT_CNT_SHIFT 0
+#define NIC0_QM0_CQ_STS1_CQ_INFLIGHT_CNT_MASK 0xFFFF
+#define NIC0_QM0_CQ_STS1_CQ_BUF_EMPTY_SHIFT 30
+#define NIC0_QM0_CQ_STS1_CQ_BUF_EMPTY_MASK 0x40000000
+#define NIC0_QM0_CQ_STS1_CQ_BUSY_SHIFT 31
+#define NIC0_QM0_CQ_STS1_CQ_BUSY_MASK 0x80000000
+
+/* NIC0_QM0_CQ_PTR_LO_0 */
+#define NIC0_QM0_CQ_PTR_LO_0_VAL_SHIFT 0
+#define NIC0_QM0_CQ_PTR_LO_0_VAL_MASK 0xFFFFFFFF
+
+/* NIC0_QM0_CQ_PTR_HI_0 */
+#define NIC0_QM0_CQ_PTR_HI_0_VAL_SHIFT 0
+#define NIC0_QM0_CQ_PTR_HI_0_VAL_MASK 0xFFFFFFFF
+
+/* NIC0_QM0_CQ_TSIZE_0 */
+#define NIC0_QM0_CQ_TSIZE_0_VAL_SHIFT 0
+#define NIC0_QM0_CQ_TSIZE_0_VAL_MASK 0xFFFFFFFF
+
+/* NIC0_QM0_CQ_CTL_0 */
+#define NIC0_QM0_CQ_CTL_0_RPT_SHIFT 0
+#define NIC0_QM0_CQ_CTL_0_RPT_MASK 0xFFFF
+#define NIC0_QM0_CQ_CTL_0_CTL_SHIFT 16
+#define NIC0_QM0_CQ_CTL_0_CTL_MASK 0xFFFF0000
+
+/* NIC0_QM0_CQ_PTR_LO_1 */
+#define NIC0_QM0_CQ_PTR_LO_1_VAL_SHIFT 0
+#define NIC0_QM0_CQ_PTR_LO_1_VAL_MASK 0xFFFFFFFF
+
+/* NIC0_QM0_CQ_PTR_HI_1 */
+#define NIC0_QM0_CQ_PTR_HI_1_VAL_SHIFT 0
+#define NIC0_QM0_CQ_PTR_HI_1_VAL_MASK 0xFFFFFFFF
+
+/* NIC0_QM0_CQ_TSIZE_1 */
+#define NIC0_QM0_CQ_TSIZE_1_VAL_SHIFT 0
+#define NIC0_QM0_CQ_TSIZE_1_VAL_MASK 0xFFFFFFFF
+
+/* NIC0_QM0_CQ_CTL_1 */
+#define NIC0_QM0_CQ_CTL_1_RPT_SHIFT 0
+#define NIC0_QM0_CQ_CTL_1_RPT_MASK 0xFFFF
+#define NIC0_QM0_CQ_CTL_1_CTL_SHIFT 16
+#define NIC0_QM0_CQ_CTL_1_CTL_MASK 0xFFFF0000
+
+/* NIC0_QM0_CQ_PTR_LO_2 */
+#define NIC0_QM0_CQ_PTR_LO_2_VAL_SHIFT 0
+#define NIC0_QM0_CQ_PTR_LO_2_VAL_MASK 0xFFFFFFFF
+
+/* NIC0_QM0_CQ_PTR_HI_2 */
+#define NIC0_QM0_CQ_PTR_HI_2_VAL_SHIFT 0
+#define NIC0_QM0_CQ_PTR_HI_2_VAL_MASK 0xFFFFFFFF
+
+/* NIC0_QM0_CQ_TSIZE_2 */
+#define NIC0_QM0_CQ_TSIZE_2_VAL_SHIFT 0
+#define NIC0_QM0_CQ_TSIZE_2_VAL_MASK 0xFFFFFFFF
+
+/* NIC0_QM0_CQ_CTL_2 */
+#define NIC0_QM0_CQ_CTL_2_RPT_SHIFT 0
+#define NIC0_QM0_CQ_CTL_2_RPT_MASK 0xFFFF
+#define NIC0_QM0_CQ_CTL_2_CTL_SHIFT 16
+#define NIC0_QM0_CQ_CTL_2_CTL_MASK 0xFFFF0000
+
+/* NIC0_QM0_CQ_PTR_LO_3 */
+#define NIC0_QM0_CQ_PTR_LO_3_VAL_SHIFT 0
+#define NIC0_QM0_CQ_PTR_LO_3_VAL_MASK 0xFFFFFFFF
+
+/* NIC0_QM0_CQ_PTR_HI_3 */
+#define NIC0_QM0_CQ_PTR_HI_3_VAL_SHIFT 0
+#define NIC0_QM0_CQ_PTR_HI_3_VAL_MASK 0xFFFFFFFF
+
+/* NIC0_QM0_CQ_TSIZE_3 */
+#define NIC0_QM0_CQ_TSIZE_3_VAL_SHIFT 0
+#define NIC0_QM0_CQ_TSIZE_3_VAL_MASK 0xFFFFFFFF
+
+/* NIC0_QM0_CQ_CTL_3 */
+#define NIC0_QM0_CQ_CTL_3_RPT_SHIFT 0
+#define NIC0_QM0_CQ_CTL_3_RPT_MASK 0xFFFF
+#define NIC0_QM0_CQ_CTL_3_CTL_SHIFT 16
+#define NIC0_QM0_CQ_CTL_3_CTL_MASK 0xFFFF0000
+
+/* NIC0_QM0_CQ_PTR_LO_4 */
+#define NIC0_QM0_CQ_PTR_LO_4_VAL_SHIFT 0
+#define NIC0_QM0_CQ_PTR_LO_4_VAL_MASK 0xFFFFFFFF
+
+/* NIC0_QM0_CQ_PTR_HI_4 */
+#define NIC0_QM0_CQ_PTR_HI_4_VAL_SHIFT 0
+#define NIC0_QM0_CQ_PTR_HI_4_VAL_MASK 0xFFFFFFFF
+
+/* NIC0_QM0_CQ_TSIZE_4 */
+#define NIC0_QM0_CQ_TSIZE_4_VAL_SHIFT 0
+#define NIC0_QM0_CQ_TSIZE_4_VAL_MASK 0xFFFFFFFF
+
+/* NIC0_QM0_CQ_CTL_4 */
+#define NIC0_QM0_CQ_CTL_4_RPT_SHIFT 0
+#define NIC0_QM0_CQ_CTL_4_RPT_MASK 0xFFFF
+#define NIC0_QM0_CQ_CTL_4_CTL_SHIFT 16
+#define NIC0_QM0_CQ_CTL_4_CTL_MASK 0xFFFF0000
+
+/* NIC0_QM0_CQ_PTR_LO_STS */
+#define NIC0_QM0_CQ_PTR_LO_STS_VAL_SHIFT 0
+#define NIC0_QM0_CQ_PTR_LO_STS_VAL_MASK 0xFFFFFFFF
+
+/* NIC0_QM0_CQ_PTR_HI_STS */
+#define NIC0_QM0_CQ_PTR_HI_STS_VAL_SHIFT 0
+#define NIC0_QM0_CQ_PTR_HI_STS_VAL_MASK 0xFFFFFFFF
+
+/* NIC0_QM0_CQ_TSIZE_STS */
+#define NIC0_QM0_CQ_TSIZE_STS_VAL_SHIFT 0
+#define NIC0_QM0_CQ_TSIZE_STS_VAL_MASK 0xFFFFFFFF
+
+/* NIC0_QM0_CQ_CTL_STS */
+#define NIC0_QM0_CQ_CTL_STS_RPT_SHIFT 0
+#define NIC0_QM0_CQ_CTL_STS_RPT_MASK 0xFFFF
+#define NIC0_QM0_CQ_CTL_STS_CTL_SHIFT 16
+#define NIC0_QM0_CQ_CTL_STS_CTL_MASK 0xFFFF0000
+
+/* NIC0_QM0_CQ_IFIFO_CNT */
+#define NIC0_QM0_CQ_IFIFO_CNT_VAL_SHIFT 0
+#define NIC0_QM0_CQ_IFIFO_CNT_VAL_MASK 0x3
+
+/* NIC0_QM0_CP_MSG_BASE0_ADDR_LO */
+#define NIC0_QM0_CP_MSG_BASE0_ADDR_LO_VAL_SHIFT 0
+#define NIC0_QM0_CP_MSG_BASE0_ADDR_LO_VAL_MASK 0xFFFFFFFF
+
+/* NIC0_QM0_CP_MSG_BASE0_ADDR_HI */
+#define NIC0_QM0_CP_MSG_BASE0_ADDR_HI_VAL_SHIFT 0
+#define NIC0_QM0_CP_MSG_BASE0_ADDR_HI_VAL_MASK 0xFFFFFFFF
+
+/* NIC0_QM0_CP_MSG_BASE1_ADDR_LO */
+#define NIC0_QM0_CP_MSG_BASE1_ADDR_LO_VAL_SHIFT 0
+#define NIC0_QM0_CP_MSG_BASE1_ADDR_LO_VAL_MASK 0xFFFFFFFF
+
+/* NIC0_QM0_CP_MSG_BASE1_ADDR_HI */
+#define NIC0_QM0_CP_MSG_BASE1_ADDR_HI_VAL_SHIFT 0
+#define NIC0_QM0_CP_MSG_BASE1_ADDR_HI_VAL_MASK 0xFFFFFFFF
+
+/* NIC0_QM0_CP_MSG_BASE2_ADDR_LO */
+#define NIC0_QM0_CP_MSG_BASE2_ADDR_LO_VAL_SHIFT 0
+#define NIC0_QM0_CP_MSG_BASE2_ADDR_LO_VAL_MASK 0xFFFFFFFF
+
+/* NIC0_QM0_CP_MSG_BASE2_ADDR_HI */
+#define NIC0_QM0_CP_MSG_BASE2_ADDR_HI_VAL_SHIFT 0
+#define NIC0_QM0_CP_MSG_BASE2_ADDR_HI_VAL_MASK 0xFFFFFFFF
+
+/* NIC0_QM0_CP_MSG_BASE3_ADDR_LO */
+#define NIC0_QM0_CP_MSG_BASE3_ADDR_LO_VAL_SHIFT 0
+#define NIC0_QM0_CP_MSG_BASE3_ADDR_LO_VAL_MASK 0xFFFFFFFF
+
+/* NIC0_QM0_CP_MSG_BASE3_ADDR_HI */
+#define NIC0_QM0_CP_MSG_BASE3_ADDR_HI_VAL_SHIFT 0
+#define NIC0_QM0_CP_MSG_BASE3_ADDR_HI_VAL_MASK 0xFFFFFFFF
+
+/* NIC0_QM0_CP_LDMA_TSIZE_OFFSET */
+#define NIC0_QM0_CP_LDMA_TSIZE_OFFSET_VAL_SHIFT 0
+#define NIC0_QM0_CP_LDMA_TSIZE_OFFSET_VAL_MASK 0xFFFFFFFF
+
+/* NIC0_QM0_CP_LDMA_SRC_BASE_LO_OFFSET */
+#define NIC0_QM0_CP_LDMA_SRC_BASE_LO_OFFSET_VAL_SHIFT 0
+#define NIC0_QM0_CP_LDMA_SRC_BASE_LO_OFFSET_VAL_MASK 0xFFFFFFFF
+
+/* NIC0_QM0_CP_LDMA_DST_BASE_LO_OFFSET */
+#define NIC0_QM0_CP_LDMA_DST_BASE_LO_OFFSET_VAL_SHIFT 0
+#define NIC0_QM0_CP_LDMA_DST_BASE_LO_OFFSET_VAL_MASK 0xFFFFFFFF
+
+/* NIC0_QM0_CP_FENCE0_RDATA */
+#define NIC0_QM0_CP_FENCE0_RDATA_INC_VAL_SHIFT 0
+#define NIC0_QM0_CP_FENCE0_RDATA_INC_VAL_MASK 0xF
+
+/* NIC0_QM0_CP_FENCE1_RDATA */
+#define NIC0_QM0_CP_FENCE1_RDATA_INC_VAL_SHIFT 0
+#define NIC0_QM0_CP_FENCE1_RDATA_INC_VAL_MASK 0xF
+
+/* NIC0_QM0_CP_FENCE2_RDATA */
+#define NIC0_QM0_CP_FENCE2_RDATA_INC_VAL_SHIFT 0
+#define NIC0_QM0_CP_FENCE2_RDATA_INC_VAL_MASK 0xF
+
+/* NIC0_QM0_CP_FENCE3_RDATA */
+#define NIC0_QM0_CP_FENCE3_RDATA_INC_VAL_SHIFT 0
+#define NIC0_QM0_CP_FENCE3_RDATA_INC_VAL_MASK 0xF
+
+/* NIC0_QM0_CP_FENCE0_CNT */
+#define NIC0_QM0_CP_FENCE0_CNT_VAL_SHIFT 0
+#define NIC0_QM0_CP_FENCE0_CNT_VAL_MASK 0x3FFF
+
+/* NIC0_QM0_CP_FENCE1_CNT */
+#define NIC0_QM0_CP_FENCE1_CNT_VAL_SHIFT 0
+#define NIC0_QM0_CP_FENCE1_CNT_VAL_MASK 0x3FFF
+
+/* NIC0_QM0_CP_FENCE2_CNT */
+#define NIC0_QM0_CP_FENCE2_CNT_VAL_SHIFT 0
+#define NIC0_QM0_CP_FENCE2_CNT_VAL_MASK 0x3FFF
+
+/* NIC0_QM0_CP_FENCE3_CNT */
+#define NIC0_QM0_CP_FENCE3_CNT_VAL_SHIFT 0
+#define NIC0_QM0_CP_FENCE3_CNT_VAL_MASK 0x3FFF
+
+/* NIC0_QM0_CP_STS */
+#define NIC0_QM0_CP_STS_MSG_INFLIGHT_CNT_SHIFT 0
+#define NIC0_QM0_CP_STS_MSG_INFLIGHT_CNT_MASK 0xFFFF
+#define NIC0_QM0_CP_STS_ERDY_SHIFT 16
+#define NIC0_QM0_CP_STS_ERDY_MASK 0x10000
+#define NIC0_QM0_CP_STS_RRDY_SHIFT 17
+#define NIC0_QM0_CP_STS_RRDY_MASK 0x20000
+#define NIC0_QM0_CP_STS_MRDY_SHIFT 18
+#define NIC0_QM0_CP_STS_MRDY_MASK 0x40000
+#define NIC0_QM0_CP_STS_SW_STOP_SHIFT 19
+#define NIC0_QM0_CP_STS_SW_STOP_MASK 0x80000
+#define NIC0_QM0_CP_STS_FENCE_ID_SHIFT 20
+#define NIC0_QM0_CP_STS_FENCE_ID_MASK 0x300000
+#define NIC0_QM0_CP_STS_FENCE_IN_PROGRESS_SHIFT 22
+#define NIC0_QM0_CP_STS_FENCE_IN_PROGRESS_MASK 0x400000
+
+/* NIC0_QM0_CP_CURRENT_INST_LO */
+#define NIC0_QM0_CP_CURRENT_INST_LO_VAL_SHIFT 0
+#define NIC0_QM0_CP_CURRENT_INST_LO_VAL_MASK 0xFFFFFFFF
+
+/* NIC0_QM0_CP_CURRENT_INST_HI */
+#define NIC0_QM0_CP_CURRENT_INST_HI_VAL_SHIFT 0
+#define NIC0_QM0_CP_CURRENT_INST_HI_VAL_MASK 0xFFFFFFFF
+
+/* NIC0_QM0_CP_BARRIER_CFG */
+#define NIC0_QM0_CP_BARRIER_CFG_EBGUARD_SHIFT 0
+#define NIC0_QM0_CP_BARRIER_CFG_EBGUARD_MASK 0xFFF
+#define NIC0_QM0_CP_BARRIER_CFG_RBGUARD_SHIFT 16
+#define NIC0_QM0_CP_BARRIER_CFG_RBGUARD_MASK 0xF0000
+
+/* NIC0_QM0_CP_DBG_0 */
+#define NIC0_QM0_CP_DBG_0_CS_SHIFT 0
+#define NIC0_QM0_CP_DBG_0_CS_MASK 0xF
+#define NIC0_QM0_CP_DBG_0_EB_CNT_NOT_ZERO_SHIFT 4
+#define NIC0_QM0_CP_DBG_0_EB_CNT_NOT_ZERO_MASK 0x10
+#define NIC0_QM0_CP_DBG_0_BULK_CNT_NOT_ZERO_SHIFT 5
+#define NIC0_QM0_CP_DBG_0_BULK_CNT_NOT_ZERO_MASK 0x20
+#define NIC0_QM0_CP_DBG_0_MREB_STALL_SHIFT 6
+#define NIC0_QM0_CP_DBG_0_MREB_STALL_MASK 0x40
+#define NIC0_QM0_CP_DBG_0_STALL_SHIFT 7
+#define NIC0_QM0_CP_DBG_0_STALL_MASK 0x80
+
+/* NIC0_QM0_CP_ARUSER_31_11 */
+#define NIC0_QM0_CP_ARUSER_31_11_VAL_SHIFT 0
+#define NIC0_QM0_CP_ARUSER_31_11_VAL_MASK 0x1FFFFF
+
+/* NIC0_QM0_CP_AWUSER_31_11 */
+#define NIC0_QM0_CP_AWUSER_31_11_VAL_SHIFT 0
+#define NIC0_QM0_CP_AWUSER_31_11_VAL_MASK 0x1FFFFF
+
+/* NIC0_QM0_ARB_CFG_0 */
+#define NIC0_QM0_ARB_CFG_0_TYPE_SHIFT 0
+#define NIC0_QM0_ARB_CFG_0_TYPE_MASK 0x1
+#define NIC0_QM0_ARB_CFG_0_IS_MASTER_SHIFT 4
+#define NIC0_QM0_ARB_CFG_0_IS_MASTER_MASK 0x10
+#define NIC0_QM0_ARB_CFG_0_EN_SHIFT 8
+#define NIC0_QM0_ARB_CFG_0_EN_MASK 0x100
+#define NIC0_QM0_ARB_CFG_0_MASK_SHIFT 12
+#define NIC0_QM0_ARB_CFG_0_MASK_MASK 0xF000
+#define NIC0_QM0_ARB_CFG_0_MST_MSG_NOSTALL_SHIFT 16
+#define NIC0_QM0_ARB_CFG_0_MST_MSG_NOSTALL_MASK 0x10000
+
+/* NIC0_QM0_ARB_CHOISE_Q_PUSH */
+#define NIC0_QM0_ARB_CHOISE_Q_PUSH_VAL_SHIFT 0
+#define NIC0_QM0_ARB_CHOISE_Q_PUSH_VAL_MASK 0x3
+
+/* NIC0_QM0_ARB_WRR_WEIGHT */
+#define NIC0_QM0_ARB_WRR_WEIGHT_VAL_SHIFT 0
+#define NIC0_QM0_ARB_WRR_WEIGHT_VAL_MASK 0xFFFFFFFF
+
+/* NIC0_QM0_ARB_CFG_1 */
+#define NIC0_QM0_ARB_CFG_1_CLR_SHIFT 0
+#define NIC0_QM0_ARB_CFG_1_CLR_MASK 0x1
+
+/* NIC0_QM0_ARB_MST_AVAIL_CRED */
+#define NIC0_QM0_ARB_MST_AVAIL_CRED_VAL_SHIFT 0
+#define NIC0_QM0_ARB_MST_AVAIL_CRED_VAL_MASK 0x7F
+
+/* NIC0_QM0_ARB_MST_CRED_INC */
+#define NIC0_QM0_ARB_MST_CRED_INC_VAL_SHIFT 0
+#define NIC0_QM0_ARB_MST_CRED_INC_VAL_MASK 0xFFFFFFFF
+
+/* NIC0_QM0_ARB_MST_CHOISE_PUSH_OFST */
+#define NIC0_QM0_ARB_MST_CHOISE_PUSH_OFST_VAL_SHIFT 0
+#define NIC0_QM0_ARB_MST_CHOISE_PUSH_OFST_VAL_MASK 0xFFFFFFFF
+
+/* NIC0_QM0_ARB_SLV_MASTER_INC_CRED_OFST */
+#define NIC0_QM0_ARB_SLV_MASTER_INC_CRED_OFST_VAL_SHIFT 0
+#define NIC0_QM0_ARB_SLV_MASTER_INC_CRED_OFST_VAL_MASK 0xFFFFFFFF
+
+/* NIC0_QM0_ARB_MST_SLAVE_EN */
+#define NIC0_QM0_ARB_MST_SLAVE_EN_VAL_SHIFT 0
+#define NIC0_QM0_ARB_MST_SLAVE_EN_VAL_MASK 0xFFFFFFFF
+
+/* NIC0_QM0_ARB_MST_QUIET_PER */
+#define NIC0_QM0_ARB_MST_QUIET_PER_VAL_SHIFT 0
+#define NIC0_QM0_ARB_MST_QUIET_PER_VAL_MASK 0xFFFFFFFF
+
+/* NIC0_QM0_ARB_SLV_CHOISE_WDT */
+#define NIC0_QM0_ARB_SLV_CHOISE_WDT_VAL_SHIFT 0
+#define NIC0_QM0_ARB_SLV_CHOISE_WDT_VAL_MASK 0xFFFFFFFF
+
+/* NIC0_QM0_ARB_SLV_ID */
+#define NIC0_QM0_ARB_SLV_ID_VAL_SHIFT 0
+#define NIC0_QM0_ARB_SLV_ID_VAL_MASK 0x1F
+
+/* NIC0_QM0_ARB_MSG_MAX_INFLIGHT */
+#define NIC0_QM0_ARB_MSG_MAX_INFLIGHT_VAL_SHIFT 0
+#define NIC0_QM0_ARB_MSG_MAX_INFLIGHT_VAL_MASK 0x3F
+
+/* NIC0_QM0_ARB_MSG_AWUSER_31_11 */
+#define NIC0_QM0_ARB_MSG_AWUSER_31_11_VAL_SHIFT 0
+#define NIC0_QM0_ARB_MSG_AWUSER_31_11_VAL_MASK 0x1FFFFF
+
+/* NIC0_QM0_ARB_MSG_AWUSER_SEC_PROP */
+#define NIC0_QM0_ARB_MSG_AWUSER_SEC_PROP_ASID_SHIFT 0
+#define NIC0_QM0_ARB_MSG_AWUSER_SEC_PROP_ASID_MASK 0x3FF
+#define NIC0_QM0_ARB_MSG_AWUSER_SEC_PROP_MMBP_SHIFT 10
+#define NIC0_QM0_ARB_MSG_AWUSER_SEC_PROP_MMBP_MASK 0x400
+
+/* NIC0_QM0_ARB_MSG_AWUSER_NON_SEC_PROP */
+#define NIC0_QM0_ARB_MSG_AWUSER_NON_SEC_PROP_ASID_SHIFT 0
+#define NIC0_QM0_ARB_MSG_AWUSER_NON_SEC_PROP_ASID_MASK 0x3FF
+#define NIC0_QM0_ARB_MSG_AWUSER_NON_SEC_PROP_MMBP_SHIFT 10
+#define NIC0_QM0_ARB_MSG_AWUSER_NON_SEC_PROP_MMBP_MASK 0x400
+
+/* NIC0_QM0_ARB_BASE_LO */
+#define NIC0_QM0_ARB_BASE_LO_VAL_SHIFT 0
+#define NIC0_QM0_ARB_BASE_LO_VAL_MASK 0xFFFFFFFF
+
+/* NIC0_QM0_ARB_BASE_HI */
+#define NIC0_QM0_ARB_BASE_HI_VAL_SHIFT 0
+#define NIC0_QM0_ARB_BASE_HI_VAL_MASK 0xFFFFFFFF
+
+/* NIC0_QM0_ARB_STATE_STS */
+#define NIC0_QM0_ARB_STATE_STS_VAL_SHIFT 0
+#define NIC0_QM0_ARB_STATE_STS_VAL_MASK 0xFFFFFFFF
+
+/* NIC0_QM0_ARB_CHOISE_FULLNESS_STS */
+#define NIC0_QM0_ARB_CHOISE_FULLNESS_STS_VAL_SHIFT 0
+#define NIC0_QM0_ARB_CHOISE_FULLNESS_STS_VAL_MASK 0x7F
+
+/* NIC0_QM0_ARB_MSG_STS */
+#define NIC0_QM0_ARB_MSG_STS_FULL_SHIFT 0
+#define NIC0_QM0_ARB_MSG_STS_FULL_MASK 0x1
+#define NIC0_QM0_ARB_MSG_STS_NO_INFLIGHT_SHIFT 1
+#define NIC0_QM0_ARB_MSG_STS_NO_INFLIGHT_MASK 0x2
+
+/* NIC0_QM0_ARB_SLV_CHOISE_Q_HEAD */
+#define NIC0_QM0_ARB_SLV_CHOISE_Q_HEAD_VAL_SHIFT 0
+#define NIC0_QM0_ARB_SLV_CHOISE_Q_HEAD_VAL_MASK 0x3
+
+/* NIC0_QM0_ARB_ERR_CAUSE */
+#define NIC0_QM0_ARB_ERR_CAUSE_CHOISE_OVF_SHIFT 0
+#define NIC0_QM0_ARB_ERR_CAUSE_CHOISE_OVF_MASK 0x1
+#define NIC0_QM0_ARB_ERR_CAUSE_CHOISE_WDT_SHIFT 1
+#define NIC0_QM0_ARB_ERR_CAUSE_CHOISE_WDT_MASK 0x2
+#define NIC0_QM0_ARB_ERR_CAUSE_AXI_LBW_ERR_SHIFT 2
+#define NIC0_QM0_ARB_ERR_CAUSE_AXI_LBW_ERR_MASK 0x4
+
+/* NIC0_QM0_ARB_ERR_MSG_EN */
+#define NIC0_QM0_ARB_ERR_MSG_EN_CHOISE_OVF_SHIFT 0
+#define NIC0_QM0_ARB_ERR_MSG_EN_CHOISE_OVF_MASK 0x1
+#define NIC0_QM0_ARB_ERR_MSG_EN_CHOISE_WDT_SHIFT 1
+#define NIC0_QM0_ARB_ERR_MSG_EN_CHOISE_WDT_MASK 0x2
+#define NIC0_QM0_ARB_ERR_MSG_EN_AXI_LBW_ERR_SHIFT 2
+#define NIC0_QM0_ARB_ERR_MSG_EN_AXI_LBW_ERR_MASK 0x4
+
+/* NIC0_QM0_ARB_ERR_STS_DRP */
+#define NIC0_QM0_ARB_ERR_STS_DRP_VAL_SHIFT 0
+#define NIC0_QM0_ARB_ERR_STS_DRP_VAL_MASK 0x3
+
+/* NIC0_QM0_ARB_MST_CRED_STS */
+#define NIC0_QM0_ARB_MST_CRED_STS_VAL_SHIFT 0
+#define NIC0_QM0_ARB_MST_CRED_STS_VAL_MASK 0x7F
+
+/* NIC0_QM0_CGM_CFG */
+#define NIC0_QM0_CGM_CFG_IDLE_TH_SHIFT 0
+#define NIC0_QM0_CGM_CFG_IDLE_TH_MASK 0xFFF
+#define NIC0_QM0_CGM_CFG_G2F_TH_SHIFT 16
+#define NIC0_QM0_CGM_CFG_G2F_TH_MASK 0xFF0000
+#define NIC0_QM0_CGM_CFG_CP_IDLE_MASK_SHIFT 24
+#define NIC0_QM0_CGM_CFG_CP_IDLE_MASK_MASK 0x1F000000
+#define NIC0_QM0_CGM_CFG_EN_SHIFT 31
+#define NIC0_QM0_CGM_CFG_EN_MASK 0x80000000
+
+/* NIC0_QM0_CGM_STS */
+#define NIC0_QM0_CGM_STS_ST_SHIFT 0
+#define NIC0_QM0_CGM_STS_ST_MASK 0x3
+#define NIC0_QM0_CGM_STS_CG_SHIFT 4
+#define NIC0_QM0_CGM_STS_CG_MASK 0x10
+#define NIC0_QM0_CGM_STS_AGENT_IDLE_SHIFT 8
+#define NIC0_QM0_CGM_STS_AGENT_IDLE_MASK 0x100
+#define NIC0_QM0_CGM_STS_AXI_IDLE_SHIFT 9
+#define NIC0_QM0_CGM_STS_AXI_IDLE_MASK 0x200
+#define NIC0_QM0_CGM_STS_CP_IDLE_SHIFT 10
+#define NIC0_QM0_CGM_STS_CP_IDLE_MASK 0x400
+
+/* NIC0_QM0_CGM_CFG1 */
+#define NIC0_QM0_CGM_CFG1_MASK_TH_SHIFT 0
+#define NIC0_QM0_CGM_CFG1_MASK_TH_MASK 0xFF
+
+/* NIC0_QM0_LOCAL_RANGE_BASE */
+#define NIC0_QM0_LOCAL_RANGE_BASE_VAL_SHIFT 0
+#define NIC0_QM0_LOCAL_RANGE_BASE_VAL_MASK 0xFFFF
+
+/* NIC0_QM0_LOCAL_RANGE_SIZE */
+#define NIC0_QM0_LOCAL_RANGE_SIZE_VAL_SHIFT 0
+#define NIC0_QM0_LOCAL_RANGE_SIZE_VAL_MASK 0xFFFF
+
+/* NIC0_QM0_CSMR_STRICT_PRIO_CFG */
+#define NIC0_QM0_CSMR_STRICT_PRIO_CFG_TYPE_SHIFT 0
+#define NIC0_QM0_CSMR_STRICT_PRIO_CFG_TYPE_MASK 0x1
+
+/* NIC0_QM0_HBW_RD_RATE_LIM_CFG_1 */
+#define NIC0_QM0_HBW_RD_RATE_LIM_CFG_1_TOUT_SHIFT 0
+#define NIC0_QM0_HBW_RD_RATE_LIM_CFG_1_TOUT_MASK 0xFF
+#define NIC0_QM0_HBW_RD_RATE_LIM_CFG_1_EN_SHIFT 31
+#define NIC0_QM0_HBW_RD_RATE_LIM_CFG_1_EN_MASK 0x80000000
+
+/* NIC0_QM0_LBW_WR_RATE_LIM_CFG_0 */
+#define NIC0_QM0_LBW_WR_RATE_LIM_CFG_0_RST_TOKEN_SHIFT 0
+#define NIC0_QM0_LBW_WR_RATE_LIM_CFG_0_RST_TOKEN_MASK 0xFF
+#define NIC0_QM0_LBW_WR_RATE_LIM_CFG_0_SAT_SHIFT 16
+#define NIC0_QM0_LBW_WR_RATE_LIM_CFG_0_SAT_MASK 0xFF0000
+
+/* NIC0_QM0_LBW_WR_RATE_LIM_CFG_1 */
+#define NIC0_QM0_LBW_WR_RATE_LIM_CFG_1_TOUT_SHIFT 0
+#define NIC0_QM0_LBW_WR_RATE_LIM_CFG_1_TOUT_MASK 0xFF
+#define NIC0_QM0_LBW_WR_RATE_LIM_CFG_1_EN_SHIFT 31
+#define NIC0_QM0_LBW_WR_RATE_LIM_CFG_1_EN_MASK 0x80000000
+
+/* NIC0_QM0_HBW_RD_RATE_LIM_CFG_0 */
+#define NIC0_QM0_HBW_RD_RATE_LIM_CFG_0_RST_TOKEN_SHIFT 0
+#define NIC0_QM0_HBW_RD_RATE_LIM_CFG_0_RST_TOKEN_MASK 0xFF
+#define NIC0_QM0_HBW_RD_RATE_LIM_CFG_0_SAT_SHIFT 16
+#define NIC0_QM0_HBW_RD_RATE_LIM_CFG_0_SAT_MASK 0xFF0000
+
+/* NIC0_QM0_GLBL_AXCACHE */
+#define NIC0_QM0_GLBL_AXCACHE_AR_SHIFT 0
+#define NIC0_QM0_GLBL_AXCACHE_AR_MASK 0xF
+#define NIC0_QM0_GLBL_AXCACHE_AW_SHIFT 16
+#define NIC0_QM0_GLBL_AXCACHE_AW_MASK 0xF0000
+
+/* NIC0_QM0_IND_GW_APB_CFG */
+#define NIC0_QM0_IND_GW_APB_CFG_ADDR_SHIFT 0
+#define NIC0_QM0_IND_GW_APB_CFG_ADDR_MASK 0x7FFFFFFF
+#define NIC0_QM0_IND_GW_APB_CFG_CMD_SHIFT 31
+#define NIC0_QM0_IND_GW_APB_CFG_CMD_MASK 0x80000000
+
+/* NIC0_QM0_IND_GW_APB_WDATA */
+#define NIC0_QM0_IND_GW_APB_WDATA_VAL_SHIFT 0
+#define NIC0_QM0_IND_GW_APB_WDATA_VAL_MASK 0xFFFFFFFF
+
+/* NIC0_QM0_IND_GW_APB_RDATA */
+#define NIC0_QM0_IND_GW_APB_RDATA_VAL_SHIFT 0
+#define NIC0_QM0_IND_GW_APB_RDATA_VAL_MASK 0xFFFFFFFF
+
+/* NIC0_QM0_IND_GW_APB_STATUS */
+#define NIC0_QM0_IND_GW_APB_STATUS_RDY_SHIFT 0
+#define NIC0_QM0_IND_GW_APB_STATUS_RDY_MASK 0x1
+#define NIC0_QM0_IND_GW_APB_STATUS_ERR_SHIFT 1
+#define NIC0_QM0_IND_GW_APB_STATUS_ERR_MASK 0x2
+
+/* NIC0_QM0_GLBL_ERR_ADDR_LO */
+#define NIC0_QM0_GLBL_ERR_ADDR_LO_VAL_SHIFT 0
+#define NIC0_QM0_GLBL_ERR_ADDR_LO_VAL_MASK 0xFFFFFFFF
+
+/* NIC0_QM0_GLBL_ERR_ADDR_HI */
+#define NIC0_QM0_GLBL_ERR_ADDR_HI_VAL_SHIFT 0
+#define NIC0_QM0_GLBL_ERR_ADDR_HI_VAL_MASK 0xFFFFFFFF
+
+/* NIC0_QM0_GLBL_ERR_WDATA */
+#define NIC0_QM0_GLBL_ERR_WDATA_VAL_SHIFT 0
+#define NIC0_QM0_GLBL_ERR_WDATA_VAL_MASK 0xFFFFFFFF
+
+/* NIC0_QM0_GLBL_MEM_INIT_BUSY */
+#define NIC0_QM0_GLBL_MEM_INIT_BUSY_RBUF_SHIFT 0
+#define NIC0_QM0_GLBL_MEM_INIT_BUSY_RBUF_MASK 0xF
+
+#endif /* ASIC_REG_NIC0_QM0_MASKS_H_ */
diff --git a/drivers/accel/habanalabs/include/gaudi/asic_reg/nic0_qm0_regs.h b/drivers/accel/habanalabs/include/gaudi/asic_reg/nic0_qm0_regs.h
new file mode 100644
index 0000000000..7c97f4041b
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi/asic_reg/nic0_qm0_regs.h
@@ -0,0 +1,834 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2016-2018 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ ** DO NOT EDIT BELOW **
+ ************************************/
+
+#ifndef ASIC_REG_NIC0_QM0_REGS_H_
+#define ASIC_REG_NIC0_QM0_REGS_H_
+
+/*
+ *****************************************
+ * NIC0_QM0 (Prototype: QMAN)
+ *****************************************
+ */
+
+#define mmNIC0_QM0_GLBL_CFG0 0xCE0000
+
+#define mmNIC0_QM0_GLBL_CFG1 0xCE0004
+
+#define mmNIC0_QM0_GLBL_PROT 0xCE0008
+
+#define mmNIC0_QM0_GLBL_ERR_CFG 0xCE000C
+
+#define mmNIC0_QM0_GLBL_SECURE_PROPS_0 0xCE0010
+
+#define mmNIC0_QM0_GLBL_SECURE_PROPS_1 0xCE0014
+
+#define mmNIC0_QM0_GLBL_SECURE_PROPS_2 0xCE0018
+
+#define mmNIC0_QM0_GLBL_SECURE_PROPS_3 0xCE001C
+
+#define mmNIC0_QM0_GLBL_SECURE_PROPS_4 0xCE0020
+
+#define mmNIC0_QM0_GLBL_NON_SECURE_PROPS_0 0xCE0024
+
+#define mmNIC0_QM0_GLBL_NON_SECURE_PROPS_1 0xCE0028
+
+#define mmNIC0_QM0_GLBL_NON_SECURE_PROPS_2 0xCE002C
+
+#define mmNIC0_QM0_GLBL_NON_SECURE_PROPS_3 0xCE0030
+
+#define mmNIC0_QM0_GLBL_NON_SECURE_PROPS_4 0xCE0034
+
+#define mmNIC0_QM0_GLBL_STS0 0xCE0038
+
+#define mmNIC0_QM0_GLBL_STS1_0 0xCE0040
+
+#define mmNIC0_QM0_GLBL_STS1_1 0xCE0044
+
+#define mmNIC0_QM0_GLBL_STS1_2 0xCE0048
+
+#define mmNIC0_QM0_GLBL_STS1_3 0xCE004C
+
+#define mmNIC0_QM0_GLBL_STS1_4 0xCE0050
+
+#define mmNIC0_QM0_GLBL_MSG_EN_0 0xCE0054
+
+#define mmNIC0_QM0_GLBL_MSG_EN_1 0xCE0058
+
+#define mmNIC0_QM0_GLBL_MSG_EN_2 0xCE005C
+
+#define mmNIC0_QM0_GLBL_MSG_EN_3 0xCE0060
+
+#define mmNIC0_QM0_GLBL_MSG_EN_4 0xCE0068
+
+#define mmNIC0_QM0_PQ_BASE_LO_0 0xCE0070
+
+#define mmNIC0_QM0_PQ_BASE_LO_1 0xCE0074
+
+#define mmNIC0_QM0_PQ_BASE_LO_2 0xCE0078
+
+#define mmNIC0_QM0_PQ_BASE_LO_3 0xCE007C
+
+#define mmNIC0_QM0_PQ_BASE_HI_0 0xCE0080
+
+#define mmNIC0_QM0_PQ_BASE_HI_1 0xCE0084
+
+#define mmNIC0_QM0_PQ_BASE_HI_2 0xCE0088
+
+#define mmNIC0_QM0_PQ_BASE_HI_3 0xCE008C
+
+#define mmNIC0_QM0_PQ_SIZE_0 0xCE0090
+
+#define mmNIC0_QM0_PQ_SIZE_1 0xCE0094
+
+#define mmNIC0_QM0_PQ_SIZE_2 0xCE0098
+
+#define mmNIC0_QM0_PQ_SIZE_3 0xCE009C
+
+#define mmNIC0_QM0_PQ_PI_0 0xCE00A0
+
+#define mmNIC0_QM0_PQ_PI_1 0xCE00A4
+
+#define mmNIC0_QM0_PQ_PI_2 0xCE00A8
+
+#define mmNIC0_QM0_PQ_PI_3 0xCE00AC
+
+#define mmNIC0_QM0_PQ_CI_0 0xCE00B0
+
+#define mmNIC0_QM0_PQ_CI_1 0xCE00B4
+
+#define mmNIC0_QM0_PQ_CI_2 0xCE00B8
+
+#define mmNIC0_QM0_PQ_CI_3 0xCE00BC
+
+#define mmNIC0_QM0_PQ_CFG0_0 0xCE00C0
+
+#define mmNIC0_QM0_PQ_CFG0_1 0xCE00C4
+
+#define mmNIC0_QM0_PQ_CFG0_2 0xCE00C8
+
+#define mmNIC0_QM0_PQ_CFG0_3 0xCE00CC
+
+#define mmNIC0_QM0_PQ_CFG1_0 0xCE00D0
+
+#define mmNIC0_QM0_PQ_CFG1_1 0xCE00D4
+
+#define mmNIC0_QM0_PQ_CFG1_2 0xCE00D8
+
+#define mmNIC0_QM0_PQ_CFG1_3 0xCE00DC
+
+#define mmNIC0_QM0_PQ_ARUSER_31_11_0 0xCE00E0
+
+#define mmNIC0_QM0_PQ_ARUSER_31_11_1 0xCE00E4
+
+#define mmNIC0_QM0_PQ_ARUSER_31_11_2 0xCE00E8
+
+#define mmNIC0_QM0_PQ_ARUSER_31_11_3 0xCE00EC
+
+#define mmNIC0_QM0_PQ_STS0_0 0xCE00F0
+
+#define mmNIC0_QM0_PQ_STS0_1 0xCE00F4
+
+#define mmNIC0_QM0_PQ_STS0_2 0xCE00F8
+
+#define mmNIC0_QM0_PQ_STS0_3 0xCE00FC
+
+#define mmNIC0_QM0_PQ_STS1_0 0xCE0100
+
+#define mmNIC0_QM0_PQ_STS1_1 0xCE0104
+
+#define mmNIC0_QM0_PQ_STS1_2 0xCE0108
+
+#define mmNIC0_QM0_PQ_STS1_3 0xCE010C
+
+#define mmNIC0_QM0_CQ_CFG0_0 0xCE0110
+
+#define mmNIC0_QM0_CQ_CFG0_1 0xCE0114
+
+#define mmNIC0_QM0_CQ_CFG0_2 0xCE0118
+
+#define mmNIC0_QM0_CQ_CFG0_3 0xCE011C
+
+#define mmNIC0_QM0_CQ_CFG0_4 0xCE0120
+
+#define mmNIC0_QM0_CQ_CFG1_0 0xCE0124
+
+#define mmNIC0_QM0_CQ_CFG1_1 0xCE0128
+
+#define mmNIC0_QM0_CQ_CFG1_2 0xCE012C
+
+#define mmNIC0_QM0_CQ_CFG1_3 0xCE0130
+
+#define mmNIC0_QM0_CQ_CFG1_4 0xCE0134
+
+#define mmNIC0_QM0_CQ_ARUSER_31_11_0 0xCE0138
+
+#define mmNIC0_QM0_CQ_ARUSER_31_11_1 0xCE013C
+
+#define mmNIC0_QM0_CQ_ARUSER_31_11_2 0xCE0140
+
+#define mmNIC0_QM0_CQ_ARUSER_31_11_3 0xCE0144
+
+#define mmNIC0_QM0_CQ_ARUSER_31_11_4 0xCE0148
+
+#define mmNIC0_QM0_CQ_STS0_0 0xCE014C
+
+#define mmNIC0_QM0_CQ_STS0_1 0xCE0150
+
+#define mmNIC0_QM0_CQ_STS0_2 0xCE0154
+
+#define mmNIC0_QM0_CQ_STS0_3 0xCE0158
+
+#define mmNIC0_QM0_CQ_STS0_4 0xCE015C
+
+#define mmNIC0_QM0_CQ_STS1_0 0xCE0160
+
+#define mmNIC0_QM0_CQ_STS1_1 0xCE0164
+
+#define mmNIC0_QM0_CQ_STS1_2 0xCE0168
+
+#define mmNIC0_QM0_CQ_STS1_3 0xCE016C
+
+#define mmNIC0_QM0_CQ_STS1_4 0xCE0170
+
+#define mmNIC0_QM0_CQ_PTR_LO_0 0xCE0174
+
+#define mmNIC0_QM0_CQ_PTR_HI_0 0xCE0178
+
+#define mmNIC0_QM0_CQ_TSIZE_0 0xCE017C
+
+#define mmNIC0_QM0_CQ_CTL_0 0xCE0180
+
+#define mmNIC0_QM0_CQ_PTR_LO_1 0xCE0184
+
+#define mmNIC0_QM0_CQ_PTR_HI_1 0xCE0188
+
+#define mmNIC0_QM0_CQ_TSIZE_1 0xCE018C
+
+#define mmNIC0_QM0_CQ_CTL_1 0xCE0190
+
+#define mmNIC0_QM0_CQ_PTR_LO_2 0xCE0194
+
+#define mmNIC0_QM0_CQ_PTR_HI_2 0xCE0198
+
+#define mmNIC0_QM0_CQ_TSIZE_2 0xCE019C
+
+#define mmNIC0_QM0_CQ_CTL_2 0xCE01A0
+
+#define mmNIC0_QM0_CQ_PTR_LO_3 0xCE01A4
+
+#define mmNIC0_QM0_CQ_PTR_HI_3 0xCE01A8
+
+#define mmNIC0_QM0_CQ_TSIZE_3 0xCE01AC
+
+#define mmNIC0_QM0_CQ_CTL_3 0xCE01B0
+
+#define mmNIC0_QM0_CQ_PTR_LO_4 0xCE01B4
+
+#define mmNIC0_QM0_CQ_PTR_HI_4 0xCE01B8
+
+#define mmNIC0_QM0_CQ_TSIZE_4 0xCE01BC
+
+#define mmNIC0_QM0_CQ_CTL_4 0xCE01C0
+
+#define mmNIC0_QM0_CQ_PTR_LO_STS_0 0xCE01C4
+
+#define mmNIC0_QM0_CQ_PTR_LO_STS_1 0xCE01C8
+
+#define mmNIC0_QM0_CQ_PTR_LO_STS_2 0xCE01CC
+
+#define mmNIC0_QM0_CQ_PTR_LO_STS_3 0xCE01D0
+
+#define mmNIC0_QM0_CQ_PTR_LO_STS_4 0xCE01D4
+
+#define mmNIC0_QM0_CQ_PTR_HI_STS_0 0xCE01D8
+
+#define mmNIC0_QM0_CQ_PTR_HI_STS_1 0xCE01DC
+
+#define mmNIC0_QM0_CQ_PTR_HI_STS_2 0xCE01E0
+
+#define mmNIC0_QM0_CQ_PTR_HI_STS_3 0xCE01E4
+
+#define mmNIC0_QM0_CQ_PTR_HI_STS_4 0xCE01E8
+
+#define mmNIC0_QM0_CQ_TSIZE_STS_0 0xCE01EC
+
+#define mmNIC0_QM0_CQ_TSIZE_STS_1 0xCE01F0
+
+#define mmNIC0_QM0_CQ_TSIZE_STS_2 0xCE01F4
+
+#define mmNIC0_QM0_CQ_TSIZE_STS_3 0xCE01F8
+
+#define mmNIC0_QM0_CQ_TSIZE_STS_4 0xCE01FC
+
+#define mmNIC0_QM0_CQ_CTL_STS_0 0xCE0200
+
+#define mmNIC0_QM0_CQ_CTL_STS_1 0xCE0204
+
+#define mmNIC0_QM0_CQ_CTL_STS_2 0xCE0208
+
+#define mmNIC0_QM0_CQ_CTL_STS_3 0xCE020C
+
+#define mmNIC0_QM0_CQ_CTL_STS_4 0xCE0210
+
+#define mmNIC0_QM0_CQ_IFIFO_CNT_0 0xCE0214
+
+#define mmNIC0_QM0_CQ_IFIFO_CNT_1 0xCE0218
+
+#define mmNIC0_QM0_CQ_IFIFO_CNT_2 0xCE021C
+
+#define mmNIC0_QM0_CQ_IFIFO_CNT_3 0xCE0220
+
+#define mmNIC0_QM0_CQ_IFIFO_CNT_4 0xCE0224
+
+#define mmNIC0_QM0_CP_MSG_BASE0_ADDR_LO_0 0xCE0228
+
+#define mmNIC0_QM0_CP_MSG_BASE0_ADDR_LO_1 0xCE022C
+
+#define mmNIC0_QM0_CP_MSG_BASE0_ADDR_LO_2 0xCE0230
+
+#define mmNIC0_QM0_CP_MSG_BASE0_ADDR_LO_3 0xCE0234
+
+#define mmNIC0_QM0_CP_MSG_BASE0_ADDR_LO_4 0xCE0238
+
+#define mmNIC0_QM0_CP_MSG_BASE0_ADDR_HI_0 0xCE023C
+
+#define mmNIC0_QM0_CP_MSG_BASE0_ADDR_HI_1 0xCE0240
+
+#define mmNIC0_QM0_CP_MSG_BASE0_ADDR_HI_2 0xCE0244
+
+#define mmNIC0_QM0_CP_MSG_BASE0_ADDR_HI_3 0xCE0248
+
+#define mmNIC0_QM0_CP_MSG_BASE0_ADDR_HI_4 0xCE024C
+
+#define mmNIC0_QM0_CP_MSG_BASE1_ADDR_LO_0 0xCE0250
+
+#define mmNIC0_QM0_CP_MSG_BASE1_ADDR_LO_1 0xCE0254
+
+#define mmNIC0_QM0_CP_MSG_BASE1_ADDR_LO_2 0xCE0258
+
+#define mmNIC0_QM0_CP_MSG_BASE1_ADDR_LO_3 0xCE025C
+
+#define mmNIC0_QM0_CP_MSG_BASE1_ADDR_LO_4 0xCE0260
+
+#define mmNIC0_QM0_CP_MSG_BASE1_ADDR_HI_0 0xCE0264
+
+#define mmNIC0_QM0_CP_MSG_BASE1_ADDR_HI_1 0xCE0268
+
+#define mmNIC0_QM0_CP_MSG_BASE1_ADDR_HI_2 0xCE026C
+
+#define mmNIC0_QM0_CP_MSG_BASE1_ADDR_HI_3 0xCE0270
+
+#define mmNIC0_QM0_CP_MSG_BASE1_ADDR_HI_4 0xCE0274
+
+#define mmNIC0_QM0_CP_MSG_BASE2_ADDR_LO_0 0xCE0278
+
+#define mmNIC0_QM0_CP_MSG_BASE2_ADDR_LO_1 0xCE027C
+
+#define mmNIC0_QM0_CP_MSG_BASE2_ADDR_LO_2 0xCE0280
+
+#define mmNIC0_QM0_CP_MSG_BASE2_ADDR_LO_3 0xCE0284
+
+#define mmNIC0_QM0_CP_MSG_BASE2_ADDR_LO_4 0xCE0288
+
+#define mmNIC0_QM0_CP_MSG_BASE2_ADDR_HI_0 0xCE028C
+
+#define mmNIC0_QM0_CP_MSG_BASE2_ADDR_HI_1 0xCE0290
+
+#define mmNIC0_QM0_CP_MSG_BASE2_ADDR_HI_2 0xCE0294
+
+#define mmNIC0_QM0_CP_MSG_BASE2_ADDR_HI_3 0xCE0298
+
+#define mmNIC0_QM0_CP_MSG_BASE2_ADDR_HI_4 0xCE029C
+
+#define mmNIC0_QM0_CP_MSG_BASE3_ADDR_LO_0 0xCE02A0
+
+#define mmNIC0_QM0_CP_MSG_BASE3_ADDR_LO_1 0xCE02A4
+
+#define mmNIC0_QM0_CP_MSG_BASE3_ADDR_LO_2 0xCE02A8
+
+#define mmNIC0_QM0_CP_MSG_BASE3_ADDR_LO_3 0xCE02AC
+
+#define mmNIC0_QM0_CP_MSG_BASE3_ADDR_LO_4 0xCE02B0
+
+#define mmNIC0_QM0_CP_MSG_BASE3_ADDR_HI_0 0xCE02B4
+
+#define mmNIC0_QM0_CP_MSG_BASE3_ADDR_HI_1 0xCE02B8
+
+#define mmNIC0_QM0_CP_MSG_BASE3_ADDR_HI_2 0xCE02BC
+
+#define mmNIC0_QM0_CP_MSG_BASE3_ADDR_HI_3 0xCE02C0
+
+#define mmNIC0_QM0_CP_MSG_BASE3_ADDR_HI_4 0xCE02C4
+
+#define mmNIC0_QM0_CP_LDMA_TSIZE_OFFSET_0 0xCE02C8
+
+#define mmNIC0_QM0_CP_LDMA_TSIZE_OFFSET_1 0xCE02CC
+
+#define mmNIC0_QM0_CP_LDMA_TSIZE_OFFSET_2 0xCE02D0
+
+#define mmNIC0_QM0_CP_LDMA_TSIZE_OFFSET_3 0xCE02D4
+
+#define mmNIC0_QM0_CP_LDMA_TSIZE_OFFSET_4 0xCE02D8
+
+#define mmNIC0_QM0_CP_LDMA_SRC_BASE_LO_OFFSET_0 0xCE02E0
+
+#define mmNIC0_QM0_CP_LDMA_SRC_BASE_LO_OFFSET_1 0xCE02E4
+
+#define mmNIC0_QM0_CP_LDMA_SRC_BASE_LO_OFFSET_2 0xCE02E8
+
+#define mmNIC0_QM0_CP_LDMA_SRC_BASE_LO_OFFSET_3 0xCE02EC
+
+#define mmNIC0_QM0_CP_LDMA_SRC_BASE_LO_OFFSET_4 0xCE02F0
+
+#define mmNIC0_QM0_CP_LDMA_DST_BASE_LO_OFFSET_0 0xCE02F4
+
+#define mmNIC0_QM0_CP_LDMA_DST_BASE_LO_OFFSET_1 0xCE02F8
+
+#define mmNIC0_QM0_CP_LDMA_DST_BASE_LO_OFFSET_2 0xCE02FC
+
+#define mmNIC0_QM0_CP_LDMA_DST_BASE_LO_OFFSET_3 0xCE0300
+
+#define mmNIC0_QM0_CP_LDMA_DST_BASE_LO_OFFSET_4 0xCE0304
+
+#define mmNIC0_QM0_CP_FENCE0_RDATA_0 0xCE0308
+
+#define mmNIC0_QM0_CP_FENCE0_RDATA_1 0xCE030C
+
+#define mmNIC0_QM0_CP_FENCE0_RDATA_2 0xCE0310
+
+#define mmNIC0_QM0_CP_FENCE0_RDATA_3 0xCE0314
+
+#define mmNIC0_QM0_CP_FENCE0_RDATA_4 0xCE0318
+
+#define mmNIC0_QM0_CP_FENCE1_RDATA_0 0xCE031C
+
+#define mmNIC0_QM0_CP_FENCE1_RDATA_1 0xCE0320
+
+#define mmNIC0_QM0_CP_FENCE1_RDATA_2 0xCE0324
+
+#define mmNIC0_QM0_CP_FENCE1_RDATA_3 0xCE0328
+
+#define mmNIC0_QM0_CP_FENCE1_RDATA_4 0xCE032C
+
+#define mmNIC0_QM0_CP_FENCE2_RDATA_0 0xCE0330
+
+#define mmNIC0_QM0_CP_FENCE2_RDATA_1 0xCE0334
+
+#define mmNIC0_QM0_CP_FENCE2_RDATA_2 0xCE0338
+
+#define mmNIC0_QM0_CP_FENCE2_RDATA_3 0xCE033C
+
+#define mmNIC0_QM0_CP_FENCE2_RDATA_4 0xCE0340
+
+#define mmNIC0_QM0_CP_FENCE3_RDATA_0 0xCE0344
+
+#define mmNIC0_QM0_CP_FENCE3_RDATA_1 0xCE0348
+
+#define mmNIC0_QM0_CP_FENCE3_RDATA_2 0xCE034C
+
+#define mmNIC0_QM0_CP_FENCE3_RDATA_3 0xCE0350
+
+#define mmNIC0_QM0_CP_FENCE3_RDATA_4 0xCE0354
+
+#define mmNIC0_QM0_CP_FENCE0_CNT_0 0xCE0358
+
+#define mmNIC0_QM0_CP_FENCE0_CNT_1 0xCE035C
+
+#define mmNIC0_QM0_CP_FENCE0_CNT_2 0xCE0360
+
+#define mmNIC0_QM0_CP_FENCE0_CNT_3 0xCE0364
+
+#define mmNIC0_QM0_CP_FENCE0_CNT_4 0xCE0368
+
+#define mmNIC0_QM0_CP_FENCE1_CNT_0 0xCE036C
+
+#define mmNIC0_QM0_CP_FENCE1_CNT_1 0xCE0370
+
+#define mmNIC0_QM0_CP_FENCE1_CNT_2 0xCE0374
+
+#define mmNIC0_QM0_CP_FENCE1_CNT_3 0xCE0378
+
+#define mmNIC0_QM0_CP_FENCE1_CNT_4 0xCE037C
+
+#define mmNIC0_QM0_CP_FENCE2_CNT_0 0xCE0380
+
+#define mmNIC0_QM0_CP_FENCE2_CNT_1 0xCE0384
+
+#define mmNIC0_QM0_CP_FENCE2_CNT_2 0xCE0388
+
+#define mmNIC0_QM0_CP_FENCE2_CNT_3 0xCE038C
+
+#define mmNIC0_QM0_CP_FENCE2_CNT_4 0xCE0390
+
+#define mmNIC0_QM0_CP_FENCE3_CNT_0 0xCE0394
+
+#define mmNIC0_QM0_CP_FENCE3_CNT_1 0xCE0398
+
+#define mmNIC0_QM0_CP_FENCE3_CNT_2 0xCE039C
+
+#define mmNIC0_QM0_CP_FENCE3_CNT_3 0xCE03A0
+
+#define mmNIC0_QM0_CP_FENCE3_CNT_4 0xCE03A4
+
+#define mmNIC0_QM0_CP_STS_0 0xCE03A8
+
+#define mmNIC0_QM0_CP_STS_1 0xCE03AC
+
+#define mmNIC0_QM0_CP_STS_2 0xCE03B0
+
+#define mmNIC0_QM0_CP_STS_3 0xCE03B4
+
+#define mmNIC0_QM0_CP_STS_4 0xCE03B8
+
+#define mmNIC0_QM0_CP_CURRENT_INST_LO_0 0xCE03BC
+
+#define mmNIC0_QM0_CP_CURRENT_INST_LO_1 0xCE03C0
+
+#define mmNIC0_QM0_CP_CURRENT_INST_LO_2 0xCE03C4
+
+#define mmNIC0_QM0_CP_CURRENT_INST_LO_3 0xCE03C8
+
+#define mmNIC0_QM0_CP_CURRENT_INST_LO_4 0xCE03CC
+
+#define mmNIC0_QM0_CP_CURRENT_INST_HI_0 0xCE03D0
+
+#define mmNIC0_QM0_CP_CURRENT_INST_HI_1 0xCE03D4
+
+#define mmNIC0_QM0_CP_CURRENT_INST_HI_2 0xCE03D8
+
+#define mmNIC0_QM0_CP_CURRENT_INST_HI_3 0xCE03DC
+
+#define mmNIC0_QM0_CP_CURRENT_INST_HI_4 0xCE03E0
+
+#define mmNIC0_QM0_CP_BARRIER_CFG_0 0xCE03F4
+
+#define mmNIC0_QM0_CP_BARRIER_CFG_1 0xCE03F8
+
+#define mmNIC0_QM0_CP_BARRIER_CFG_2 0xCE03FC
+
+#define mmNIC0_QM0_CP_BARRIER_CFG_3 0xCE0400
+
+#define mmNIC0_QM0_CP_BARRIER_CFG_4 0xCE0404
+
+#define mmNIC0_QM0_CP_DBG_0_0 0xCE0408
+
+#define mmNIC0_QM0_CP_DBG_0_1 0xCE040C
+
+#define mmNIC0_QM0_CP_DBG_0_2 0xCE0410
+
+#define mmNIC0_QM0_CP_DBG_0_3 0xCE0414
+
+#define mmNIC0_QM0_CP_DBG_0_4 0xCE0418
+
+#define mmNIC0_QM0_CP_ARUSER_31_11_0 0xCE041C
+
+#define mmNIC0_QM0_CP_ARUSER_31_11_1 0xCE0420
+
+#define mmNIC0_QM0_CP_ARUSER_31_11_2 0xCE0424
+
+#define mmNIC0_QM0_CP_ARUSER_31_11_3 0xCE0428
+
+#define mmNIC0_QM0_CP_ARUSER_31_11_4 0xCE042C
+
+#define mmNIC0_QM0_CP_AWUSER_31_11_0 0xCE0430
+
+#define mmNIC0_QM0_CP_AWUSER_31_11_1 0xCE0434
+
+#define mmNIC0_QM0_CP_AWUSER_31_11_2 0xCE0438
+
+#define mmNIC0_QM0_CP_AWUSER_31_11_3 0xCE043C
+
+#define mmNIC0_QM0_CP_AWUSER_31_11_4 0xCE0440
+
+#define mmNIC0_QM0_ARB_CFG_0 0xCE0A00
+
+#define mmNIC0_QM0_ARB_CHOISE_Q_PUSH 0xCE0A04
+
+#define mmNIC0_QM0_ARB_WRR_WEIGHT_0 0xCE0A08
+
+#define mmNIC0_QM0_ARB_WRR_WEIGHT_1 0xCE0A0C
+
+#define mmNIC0_QM0_ARB_WRR_WEIGHT_2 0xCE0A10
+
+#define mmNIC0_QM0_ARB_WRR_WEIGHT_3 0xCE0A14
+
+#define mmNIC0_QM0_ARB_CFG_1 0xCE0A18
+
+#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_0 0xCE0A20
+
+#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_1 0xCE0A24
+
+#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_2 0xCE0A28
+
+#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_3 0xCE0A2C
+
+#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_4 0xCE0A30
+
+#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_5 0xCE0A34
+
+#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_6 0xCE0A38
+
+#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_7 0xCE0A3C
+
+#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_8 0xCE0A40
+
+#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_9 0xCE0A44
+
+#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_10 0xCE0A48
+
+#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_11 0xCE0A4C
+
+#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_12 0xCE0A50
+
+#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_13 0xCE0A54
+
+#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_14 0xCE0A58
+
+#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_15 0xCE0A5C
+
+#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_16 0xCE0A60
+
+#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_17 0xCE0A64
+
+#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_18 0xCE0A68
+
+#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_19 0xCE0A6C
+
+#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_20 0xCE0A70
+
+#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_21 0xCE0A74
+
+#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_22 0xCE0A78
+
+#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_23 0xCE0A7C
+
+#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_24 0xCE0A80
+
+#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_25 0xCE0A84
+
+#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_26 0xCE0A88
+
+#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_27 0xCE0A8C
+
+#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_28 0xCE0A90
+
+#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_29 0xCE0A94
+
+#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_30 0xCE0A98
+
+#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_31 0xCE0A9C
+
+#define mmNIC0_QM0_ARB_MST_CRED_INC 0xCE0AA0
+
+#define mmNIC0_QM0_ARB_MST_CHOISE_PUSH_OFST_0 0xCE0AA4
+
+#define mmNIC0_QM0_ARB_MST_CHOISE_PUSH_OFST_1 0xCE0AA8
+
+#define mmNIC0_QM0_ARB_MST_CHOISE_PUSH_OFST_2 0xCE0AAC
+
+#define mmNIC0_QM0_ARB_MST_CHOISE_PUSH_OFST_3 0xCE0AB0
+
+#define mmNIC0_QM0_ARB_MST_CHOISE_PUSH_OFST_4 0xCE0AB4
+
+#define mmNIC0_QM0_ARB_MST_CHOISE_PUSH_OFST_5 0xCE0AB8
+
+#define mmNIC0_QM0_ARB_MST_CHOISE_PUSH_OFST_6 0xCE0ABC
+
+#define mmNIC0_QM0_ARB_MST_CHOISE_PUSH_OFST_7 0xCE0AC0
+
+#define mmNIC0_QM0_ARB_MST_CHOISE_PUSH_OFST_8 0xCE0AC4
+
+#define mmNIC0_QM0_ARB_MST_CHOISE_PUSH_OFST_9 0xCE0AC8
+
+#define mmNIC0_QM0_ARB_MST_CHOISE_PUSH_OFST_10 0xCE0ACC
+
+#define mmNIC0_QM0_ARB_MST_CHOISE_PUSH_OFST_11 0xCE0AD0
+
+#define mmNIC0_QM0_ARB_MST_CHOISE_PUSH_OFST_12 0xCE0AD4
+
+#define mmNIC0_QM0_ARB_MST_CHOISE_PUSH_OFST_13 0xCE0AD8
+
+#define mmNIC0_QM0_ARB_MST_CHOISE_PUSH_OFST_14 0xCE0ADC
+
+#define mmNIC0_QM0_ARB_MST_CHOISE_PUSH_OFST_15 0xCE0AE0
+
+#define mmNIC0_QM0_ARB_MST_CHOISE_PUSH_OFST_16 0xCE0AE4
+
+#define mmNIC0_QM0_ARB_MST_CHOISE_PUSH_OFST_17 0xCE0AE8
+
+#define mmNIC0_QM0_ARB_MST_CHOISE_PUSH_OFST_18 0xCE0AEC
+
+#define mmNIC0_QM0_ARB_MST_CHOISE_PUSH_OFST_19 0xCE0AF0
+
+#define mmNIC0_QM0_ARB_MST_CHOISE_PUSH_OFST_20 0xCE0AF4
+
+#define mmNIC0_QM0_ARB_MST_CHOISE_PUSH_OFST_21 0xCE0AF8
+
+#define mmNIC0_QM0_ARB_MST_CHOISE_PUSH_OFST_22 0xCE0AFC
+
+#define mmNIC0_QM0_ARB_MST_CHOISE_PUSH_OFST_23 0xCE0B00
+
+#define mmNIC0_QM0_ARB_MST_CHOISE_PUSH_OFST_24 0xCE0B04
+
+#define mmNIC0_QM0_ARB_MST_CHOISE_PUSH_OFST_25 0xCE0B08
+
+#define mmNIC0_QM0_ARB_MST_CHOISE_PUSH_OFST_26 0xCE0B0C
+
+#define mmNIC0_QM0_ARB_MST_CHOISE_PUSH_OFST_27 0xCE0B10
+
+#define mmNIC0_QM0_ARB_MST_CHOISE_PUSH_OFST_28 0xCE0B14
+
+#define mmNIC0_QM0_ARB_MST_CHOISE_PUSH_OFST_29 0xCE0B18
+
+#define mmNIC0_QM0_ARB_MST_CHOISE_PUSH_OFST_30 0xCE0B1C
+
+#define mmNIC0_QM0_ARB_MST_CHOISE_PUSH_OFST_31 0xCE0B20
+
+#define mmNIC0_QM0_ARB_SLV_MASTER_INC_CRED_OFST 0xCE0B28
+
+#define mmNIC0_QM0_ARB_MST_SLAVE_EN 0xCE0B2C
+
+#define mmNIC0_QM0_ARB_MST_QUIET_PER 0xCE0B34
+
+#define mmNIC0_QM0_ARB_SLV_CHOISE_WDT 0xCE0B38
+
+#define mmNIC0_QM0_ARB_SLV_ID 0xCE0B3C
+
+#define mmNIC0_QM0_ARB_MSG_MAX_INFLIGHT 0xCE0B44
+
+#define mmNIC0_QM0_ARB_MSG_AWUSER_31_11 0xCE0B48
+
+#define mmNIC0_QM0_ARB_MSG_AWUSER_SEC_PROP 0xCE0B4C
+
+#define mmNIC0_QM0_ARB_MSG_AWUSER_NON_SEC_PROP 0xCE0B50
+
+#define mmNIC0_QM0_ARB_BASE_LO 0xCE0B54
+
+#define mmNIC0_QM0_ARB_BASE_HI 0xCE0B58
+
+#define mmNIC0_QM0_ARB_STATE_STS 0xCE0B80
+
+#define mmNIC0_QM0_ARB_CHOISE_FULLNESS_STS 0xCE0B84
+
+#define mmNIC0_QM0_ARB_MSG_STS 0xCE0B88
+
+#define mmNIC0_QM0_ARB_SLV_CHOISE_Q_HEAD 0xCE0B8C
+
+#define mmNIC0_QM0_ARB_ERR_CAUSE 0xCE0B9C
+
+#define mmNIC0_QM0_ARB_ERR_MSG_EN 0xCE0BA0
+
+#define mmNIC0_QM0_ARB_ERR_STS_DRP 0xCE0BA8
+
+#define mmNIC0_QM0_ARB_MST_CRED_STS_0 0xCE0BB0
+
+#define mmNIC0_QM0_ARB_MST_CRED_STS_1 0xCE0BB4
+
+#define mmNIC0_QM0_ARB_MST_CRED_STS_2 0xCE0BB8
+
+#define mmNIC0_QM0_ARB_MST_CRED_STS_3 0xCE0BBC
+
+#define mmNIC0_QM0_ARB_MST_CRED_STS_4 0xCE0BC0
+
+#define mmNIC0_QM0_ARB_MST_CRED_STS_5 0xCE0BC4
+
+#define mmNIC0_QM0_ARB_MST_CRED_STS_6 0xCE0BC8
+
+#define mmNIC0_QM0_ARB_MST_CRED_STS_7 0xCE0BCC
+
+#define mmNIC0_QM0_ARB_MST_CRED_STS_8 0xCE0BD0
+
+#define mmNIC0_QM0_ARB_MST_CRED_STS_9 0xCE0BD4
+
+#define mmNIC0_QM0_ARB_MST_CRED_STS_10 0xCE0BD8
+
+#define mmNIC0_QM0_ARB_MST_CRED_STS_11 0xCE0BDC
+
+#define mmNIC0_QM0_ARB_MST_CRED_STS_12 0xCE0BE0
+
+#define mmNIC0_QM0_ARB_MST_CRED_STS_13 0xCE0BE4
+
+#define mmNIC0_QM0_ARB_MST_CRED_STS_14 0xCE0BE8
+
+#define mmNIC0_QM0_ARB_MST_CRED_STS_15 0xCE0BEC
+
+#define mmNIC0_QM0_ARB_MST_CRED_STS_16 0xCE0BF0
+
+#define mmNIC0_QM0_ARB_MST_CRED_STS_17 0xCE0BF4
+
+#define mmNIC0_QM0_ARB_MST_CRED_STS_18 0xCE0BF8
+
+#define mmNIC0_QM0_ARB_MST_CRED_STS_19 0xCE0BFC
+
+#define mmNIC0_QM0_ARB_MST_CRED_STS_20 0xCE0C00
+
+#define mmNIC0_QM0_ARB_MST_CRED_STS_21 0xCE0C04
+
+#define mmNIC0_QM0_ARB_MST_CRED_STS_22 0xCE0C08
+
+#define mmNIC0_QM0_ARB_MST_CRED_STS_23 0xCE0C0C
+
+#define mmNIC0_QM0_ARB_MST_CRED_STS_24 0xCE0C10
+
+#define mmNIC0_QM0_ARB_MST_CRED_STS_25 0xCE0C14
+
+#define mmNIC0_QM0_ARB_MST_CRED_STS_26 0xCE0C18
+
+#define mmNIC0_QM0_ARB_MST_CRED_STS_27 0xCE0C1C
+
+#define mmNIC0_QM0_ARB_MST_CRED_STS_28 0xCE0C20
+
+#define mmNIC0_QM0_ARB_MST_CRED_STS_29 0xCE0C24
+
+#define mmNIC0_QM0_ARB_MST_CRED_STS_30 0xCE0C28
+
+#define mmNIC0_QM0_ARB_MST_CRED_STS_31 0xCE0C2C
+
+#define mmNIC0_QM0_CGM_CFG 0xCE0C70
+
+#define mmNIC0_QM0_CGM_STS 0xCE0C74
+
+#define mmNIC0_QM0_CGM_CFG1 0xCE0C78
+
+#define mmNIC0_QM0_LOCAL_RANGE_BASE 0xCE0C80
+
+#define mmNIC0_QM0_LOCAL_RANGE_SIZE 0xCE0C84
+
+#define mmNIC0_QM0_CSMR_STRICT_PRIO_CFG 0xCE0C90
+
+#define mmNIC0_QM0_HBW_RD_RATE_LIM_CFG_1 0xCE0C94
+
+#define mmNIC0_QM0_LBW_WR_RATE_LIM_CFG_0 0xCE0C98
+
+#define mmNIC0_QM0_LBW_WR_RATE_LIM_CFG_1 0xCE0C9C
+
+#define mmNIC0_QM0_HBW_RD_RATE_LIM_CFG_0 0xCE0CA0
+
+#define mmNIC0_QM0_GLBL_AXCACHE 0xCE0CA4
+
+#define mmNIC0_QM0_IND_GW_APB_CFG 0xCE0CB0
+
+#define mmNIC0_QM0_IND_GW_APB_WDATA 0xCE0CB4
+
+#define mmNIC0_QM0_IND_GW_APB_RDATA 0xCE0CB8
+
+#define mmNIC0_QM0_IND_GW_APB_STATUS 0xCE0CBC
+
+#define mmNIC0_QM0_GLBL_ERR_ADDR_LO 0xCE0CD0
+
+#define mmNIC0_QM0_GLBL_ERR_ADDR_HI 0xCE0CD4
+
+#define mmNIC0_QM0_GLBL_ERR_WDATA 0xCE0CD8
+
+#define mmNIC0_QM0_GLBL_MEM_INIT_BUSY 0xCE0D00
+
+#endif /* ASIC_REG_NIC0_QM0_REGS_H_ */
diff --git a/drivers/accel/habanalabs/include/gaudi/asic_reg/nic0_qm1_regs.h b/drivers/accel/habanalabs/include/gaudi/asic_reg/nic0_qm1_regs.h
new file mode 100644
index 0000000000..fe96c575b5
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi/asic_reg/nic0_qm1_regs.h
@@ -0,0 +1,834 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2016-2018 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ ** DO NOT EDIT BELOW **
+ ************************************/
+
+#ifndef ASIC_REG_NIC0_QM1_REGS_H_
+#define ASIC_REG_NIC0_QM1_REGS_H_
+
+/*
+ *****************************************
+ * NIC0_QM1 (Prototype: QMAN)
+ *****************************************
+ */
+
+#define mmNIC0_QM1_GLBL_CFG0 0xCE2000
+
+#define mmNIC0_QM1_GLBL_CFG1 0xCE2004
+
+#define mmNIC0_QM1_GLBL_PROT 0xCE2008
+
+#define mmNIC0_QM1_GLBL_ERR_CFG 0xCE200C
+
+#define mmNIC0_QM1_GLBL_SECURE_PROPS_0 0xCE2010
+
+#define mmNIC0_QM1_GLBL_SECURE_PROPS_1 0xCE2014
+
+#define mmNIC0_QM1_GLBL_SECURE_PROPS_2 0xCE2018
+
+#define mmNIC0_QM1_GLBL_SECURE_PROPS_3 0xCE201C
+
+#define mmNIC0_QM1_GLBL_SECURE_PROPS_4 0xCE2020
+
+#define mmNIC0_QM1_GLBL_NON_SECURE_PROPS_0 0xCE2024
+
+#define mmNIC0_QM1_GLBL_NON_SECURE_PROPS_1 0xCE2028
+
+#define mmNIC0_QM1_GLBL_NON_SECURE_PROPS_2 0xCE202C
+
+#define mmNIC0_QM1_GLBL_NON_SECURE_PROPS_3 0xCE2030
+
+#define mmNIC0_QM1_GLBL_NON_SECURE_PROPS_4 0xCE2034
+
+#define mmNIC0_QM1_GLBL_STS0 0xCE2038
+
+#define mmNIC0_QM1_GLBL_STS1_0 0xCE2040
+
+#define mmNIC0_QM1_GLBL_STS1_1 0xCE2044
+
+#define mmNIC0_QM1_GLBL_STS1_2 0xCE2048
+
+#define mmNIC0_QM1_GLBL_STS1_3 0xCE204C
+
+#define mmNIC0_QM1_GLBL_STS1_4 0xCE2050
+
+#define mmNIC0_QM1_GLBL_MSG_EN_0 0xCE2054
+
+#define mmNIC0_QM1_GLBL_MSG_EN_1 0xCE2058
+
+#define mmNIC0_QM1_GLBL_MSG_EN_2 0xCE205C
+
+#define mmNIC0_QM1_GLBL_MSG_EN_3 0xCE2060
+
+#define mmNIC0_QM1_GLBL_MSG_EN_4 0xCE2068
+
+#define mmNIC0_QM1_PQ_BASE_LO_0 0xCE2070
+
+#define mmNIC0_QM1_PQ_BASE_LO_1 0xCE2074
+
+#define mmNIC0_QM1_PQ_BASE_LO_2 0xCE2078
+
+#define mmNIC0_QM1_PQ_BASE_LO_3 0xCE207C
+
+#define mmNIC0_QM1_PQ_BASE_HI_0 0xCE2080
+
+#define mmNIC0_QM1_PQ_BASE_HI_1 0xCE2084
+
+#define mmNIC0_QM1_PQ_BASE_HI_2 0xCE2088
+
+#define mmNIC0_QM1_PQ_BASE_HI_3 0xCE208C
+
+#define mmNIC0_QM1_PQ_SIZE_0 0xCE2090
+
+#define mmNIC0_QM1_PQ_SIZE_1 0xCE2094
+
+#define mmNIC0_QM1_PQ_SIZE_2 0xCE2098
+
+#define mmNIC0_QM1_PQ_SIZE_3 0xCE209C
+
+#define mmNIC0_QM1_PQ_PI_0 0xCE20A0
+
+#define mmNIC0_QM1_PQ_PI_1 0xCE20A4
+
+#define mmNIC0_QM1_PQ_PI_2 0xCE20A8
+
+#define mmNIC0_QM1_PQ_PI_3 0xCE20AC
+
+#define mmNIC0_QM1_PQ_CI_0 0xCE20B0
+
+#define mmNIC0_QM1_PQ_CI_1 0xCE20B4
+
+#define mmNIC0_QM1_PQ_CI_2 0xCE20B8
+
+#define mmNIC0_QM1_PQ_CI_3 0xCE20BC
+
+#define mmNIC0_QM1_PQ_CFG0_0 0xCE20C0
+
+#define mmNIC0_QM1_PQ_CFG0_1 0xCE20C4
+
+#define mmNIC0_QM1_PQ_CFG0_2 0xCE20C8
+
+#define mmNIC0_QM1_PQ_CFG0_3 0xCE20CC
+
+#define mmNIC0_QM1_PQ_CFG1_0 0xCE20D0
+
+#define mmNIC0_QM1_PQ_CFG1_1 0xCE20D4
+
+#define mmNIC0_QM1_PQ_CFG1_2 0xCE20D8
+
+#define mmNIC0_QM1_PQ_CFG1_3 0xCE20DC
+
+#define mmNIC0_QM1_PQ_ARUSER_31_11_0 0xCE20E0
+
+#define mmNIC0_QM1_PQ_ARUSER_31_11_1 0xCE20E4
+
+#define mmNIC0_QM1_PQ_ARUSER_31_11_2 0xCE20E8
+
+#define mmNIC0_QM1_PQ_ARUSER_31_11_3 0xCE20EC
+
+#define mmNIC0_QM1_PQ_STS0_0 0xCE20F0
+
+#define mmNIC0_QM1_PQ_STS0_1 0xCE20F4
+
+#define mmNIC0_QM1_PQ_STS0_2 0xCE20F8
+
+#define mmNIC0_QM1_PQ_STS0_3 0xCE20FC
+
+#define mmNIC0_QM1_PQ_STS1_0 0xCE2100
+
+#define mmNIC0_QM1_PQ_STS1_1 0xCE2104
+
+#define mmNIC0_QM1_PQ_STS1_2 0xCE2108
+
+#define mmNIC0_QM1_PQ_STS1_3 0xCE210C
+
+#define mmNIC0_QM1_CQ_CFG0_0 0xCE2110
+
+#define mmNIC0_QM1_CQ_CFG0_1 0xCE2114
+
+#define mmNIC0_QM1_CQ_CFG0_2 0xCE2118
+
+#define mmNIC0_QM1_CQ_CFG0_3 0xCE211C
+
+#define mmNIC0_QM1_CQ_CFG0_4 0xCE2120
+
+#define mmNIC0_QM1_CQ_CFG1_0 0xCE2124
+
+#define mmNIC0_QM1_CQ_CFG1_1 0xCE2128
+
+#define mmNIC0_QM1_CQ_CFG1_2 0xCE212C
+
+#define mmNIC0_QM1_CQ_CFG1_3 0xCE2130
+
+#define mmNIC0_QM1_CQ_CFG1_4 0xCE2134
+
+#define mmNIC0_QM1_CQ_ARUSER_31_11_0 0xCE2138
+
+#define mmNIC0_QM1_CQ_ARUSER_31_11_1 0xCE213C
+
+#define mmNIC0_QM1_CQ_ARUSER_31_11_2 0xCE2140
+
+#define mmNIC0_QM1_CQ_ARUSER_31_11_3 0xCE2144
+
+#define mmNIC0_QM1_CQ_ARUSER_31_11_4 0xCE2148
+
+#define mmNIC0_QM1_CQ_STS0_0 0xCE214C
+
+#define mmNIC0_QM1_CQ_STS0_1 0xCE2150
+
+#define mmNIC0_QM1_CQ_STS0_2 0xCE2154
+
+#define mmNIC0_QM1_CQ_STS0_3 0xCE2158
+
+#define mmNIC0_QM1_CQ_STS0_4 0xCE215C
+
+#define mmNIC0_QM1_CQ_STS1_0 0xCE2160
+
+#define mmNIC0_QM1_CQ_STS1_1 0xCE2164
+
+#define mmNIC0_QM1_CQ_STS1_2 0xCE2168
+
+#define mmNIC0_QM1_CQ_STS1_3 0xCE216C
+
+#define mmNIC0_QM1_CQ_STS1_4 0xCE2170
+
+#define mmNIC0_QM1_CQ_PTR_LO_0 0xCE2174
+
+#define mmNIC0_QM1_CQ_PTR_HI_0 0xCE2178
+
+#define mmNIC0_QM1_CQ_TSIZE_0 0xCE217C
+
+#define mmNIC0_QM1_CQ_CTL_0 0xCE2180
+
+#define mmNIC0_QM1_CQ_PTR_LO_1 0xCE2184
+
+#define mmNIC0_QM1_CQ_PTR_HI_1 0xCE2188
+
+#define mmNIC0_QM1_CQ_TSIZE_1 0xCE218C
+
+#define mmNIC0_QM1_CQ_CTL_1 0xCE2190
+
+#define mmNIC0_QM1_CQ_PTR_LO_2 0xCE2194
+
+#define mmNIC0_QM1_CQ_PTR_HI_2 0xCE2198
+
+#define mmNIC0_QM1_CQ_TSIZE_2 0xCE219C
+
+#define mmNIC0_QM1_CQ_CTL_2 0xCE21A0
+
+#define mmNIC0_QM1_CQ_PTR_LO_3 0xCE21A4
+
+#define mmNIC0_QM1_CQ_PTR_HI_3 0xCE21A8
+
+#define mmNIC0_QM1_CQ_TSIZE_3 0xCE21AC
+
+#define mmNIC0_QM1_CQ_CTL_3 0xCE21B0
+
+#define mmNIC0_QM1_CQ_PTR_LO_4 0xCE21B4
+
+#define mmNIC0_QM1_CQ_PTR_HI_4 0xCE21B8
+
+#define mmNIC0_QM1_CQ_TSIZE_4 0xCE21BC
+
+#define mmNIC0_QM1_CQ_CTL_4 0xCE21C0
+
+#define mmNIC0_QM1_CQ_PTR_LO_STS_0 0xCE21C4
+
+#define mmNIC0_QM1_CQ_PTR_LO_STS_1 0xCE21C8
+
+#define mmNIC0_QM1_CQ_PTR_LO_STS_2 0xCE21CC
+
+#define mmNIC0_QM1_CQ_PTR_LO_STS_3 0xCE21D0
+
+#define mmNIC0_QM1_CQ_PTR_LO_STS_4 0xCE21D4
+
+#define mmNIC0_QM1_CQ_PTR_HI_STS_0 0xCE21D8
+
+#define mmNIC0_QM1_CQ_PTR_HI_STS_1 0xCE21DC
+
+#define mmNIC0_QM1_CQ_PTR_HI_STS_2 0xCE21E0
+
+#define mmNIC0_QM1_CQ_PTR_HI_STS_3 0xCE21E4
+
+#define mmNIC0_QM1_CQ_PTR_HI_STS_4 0xCE21E8
+
+#define mmNIC0_QM1_CQ_TSIZE_STS_0 0xCE21EC
+
+#define mmNIC0_QM1_CQ_TSIZE_STS_1 0xCE21F0
+
+#define mmNIC0_QM1_CQ_TSIZE_STS_2 0xCE21F4
+
+#define mmNIC0_QM1_CQ_TSIZE_STS_3 0xCE21F8
+
+#define mmNIC0_QM1_CQ_TSIZE_STS_4 0xCE21FC
+
+#define mmNIC0_QM1_CQ_CTL_STS_0 0xCE2200
+
+#define mmNIC0_QM1_CQ_CTL_STS_1 0xCE2204
+
+#define mmNIC0_QM1_CQ_CTL_STS_2 0xCE2208
+
+#define mmNIC0_QM1_CQ_CTL_STS_3 0xCE220C
+
+#define mmNIC0_QM1_CQ_CTL_STS_4 0xCE2210
+
+#define mmNIC0_QM1_CQ_IFIFO_CNT_0 0xCE2214
+
+#define mmNIC0_QM1_CQ_IFIFO_CNT_1 0xCE2218
+
+#define mmNIC0_QM1_CQ_IFIFO_CNT_2 0xCE221C
+
+#define mmNIC0_QM1_CQ_IFIFO_CNT_3 0xCE2220
+
+#define mmNIC0_QM1_CQ_IFIFO_CNT_4 0xCE2224
+
+#define mmNIC0_QM1_CP_MSG_BASE0_ADDR_LO_0 0xCE2228
+
+#define mmNIC0_QM1_CP_MSG_BASE0_ADDR_LO_1 0xCE222C
+
+#define mmNIC0_QM1_CP_MSG_BASE0_ADDR_LO_2 0xCE2230
+
+#define mmNIC0_QM1_CP_MSG_BASE0_ADDR_LO_3 0xCE2234
+
+#define mmNIC0_QM1_CP_MSG_BASE0_ADDR_LO_4 0xCE2238
+
+#define mmNIC0_QM1_CP_MSG_BASE0_ADDR_HI_0 0xCE223C
+
+#define mmNIC0_QM1_CP_MSG_BASE0_ADDR_HI_1 0xCE2240
+
+#define mmNIC0_QM1_CP_MSG_BASE0_ADDR_HI_2 0xCE2244
+
+#define mmNIC0_QM1_CP_MSG_BASE0_ADDR_HI_3 0xCE2248
+
+#define mmNIC0_QM1_CP_MSG_BASE0_ADDR_HI_4 0xCE224C
+
+#define mmNIC0_QM1_CP_MSG_BASE1_ADDR_LO_0 0xCE2250
+
+#define mmNIC0_QM1_CP_MSG_BASE1_ADDR_LO_1 0xCE2254
+
+#define mmNIC0_QM1_CP_MSG_BASE1_ADDR_LO_2 0xCE2258
+
+#define mmNIC0_QM1_CP_MSG_BASE1_ADDR_LO_3 0xCE225C
+
+#define mmNIC0_QM1_CP_MSG_BASE1_ADDR_LO_4 0xCE2260
+
+#define mmNIC0_QM1_CP_MSG_BASE1_ADDR_HI_0 0xCE2264
+
+#define mmNIC0_QM1_CP_MSG_BASE1_ADDR_HI_1 0xCE2268
+
+#define mmNIC0_QM1_CP_MSG_BASE1_ADDR_HI_2 0xCE226C
+
+#define mmNIC0_QM1_CP_MSG_BASE1_ADDR_HI_3 0xCE2270
+
+#define mmNIC0_QM1_CP_MSG_BASE1_ADDR_HI_4 0xCE2274
+
+#define mmNIC0_QM1_CP_MSG_BASE2_ADDR_LO_0 0xCE2278
+
+#define mmNIC0_QM1_CP_MSG_BASE2_ADDR_LO_1 0xCE227C
+
+#define mmNIC0_QM1_CP_MSG_BASE2_ADDR_LO_2 0xCE2280
+
+#define mmNIC0_QM1_CP_MSG_BASE2_ADDR_LO_3 0xCE2284
+
+#define mmNIC0_QM1_CP_MSG_BASE2_ADDR_LO_4 0xCE2288
+
+#define mmNIC0_QM1_CP_MSG_BASE2_ADDR_HI_0 0xCE228C
+
+#define mmNIC0_QM1_CP_MSG_BASE2_ADDR_HI_1 0xCE2290
+
+#define mmNIC0_QM1_CP_MSG_BASE2_ADDR_HI_2 0xCE2294
+
+#define mmNIC0_QM1_CP_MSG_BASE2_ADDR_HI_3 0xCE2298
+
+#define mmNIC0_QM1_CP_MSG_BASE2_ADDR_HI_4 0xCE229C
+
+#define mmNIC0_QM1_CP_MSG_BASE3_ADDR_LO_0 0xCE22A0
+
+#define mmNIC0_QM1_CP_MSG_BASE3_ADDR_LO_1 0xCE22A4
+
+#define mmNIC0_QM1_CP_MSG_BASE3_ADDR_LO_2 0xCE22A8
+
+#define mmNIC0_QM1_CP_MSG_BASE3_ADDR_LO_3 0xCE22AC
+
+#define mmNIC0_QM1_CP_MSG_BASE3_ADDR_LO_4 0xCE22B0
+
+#define mmNIC0_QM1_CP_MSG_BASE3_ADDR_HI_0 0xCE22B4
+
+#define mmNIC0_QM1_CP_MSG_BASE3_ADDR_HI_1 0xCE22B8
+
+#define mmNIC0_QM1_CP_MSG_BASE3_ADDR_HI_2 0xCE22BC
+
+#define mmNIC0_QM1_CP_MSG_BASE3_ADDR_HI_3 0xCE22C0
+
+#define mmNIC0_QM1_CP_MSG_BASE3_ADDR_HI_4 0xCE22C4
+
+#define mmNIC0_QM1_CP_LDMA_TSIZE_OFFSET_0 0xCE22C8
+
+#define mmNIC0_QM1_CP_LDMA_TSIZE_OFFSET_1 0xCE22CC
+
+#define mmNIC0_QM1_CP_LDMA_TSIZE_OFFSET_2 0xCE22D0
+
+#define mmNIC0_QM1_CP_LDMA_TSIZE_OFFSET_3 0xCE22D4
+
+#define mmNIC0_QM1_CP_LDMA_TSIZE_OFFSET_4 0xCE22D8
+
+#define mmNIC0_QM1_CP_LDMA_SRC_BASE_LO_OFFSET_0 0xCE22E0
+
+#define mmNIC0_QM1_CP_LDMA_SRC_BASE_LO_OFFSET_1 0xCE22E4
+
+#define mmNIC0_QM1_CP_LDMA_SRC_BASE_LO_OFFSET_2 0xCE22E8
+
+#define mmNIC0_QM1_CP_LDMA_SRC_BASE_LO_OFFSET_3 0xCE22EC
+
+#define mmNIC0_QM1_CP_LDMA_SRC_BASE_LO_OFFSET_4 0xCE22F0
+
+#define mmNIC0_QM1_CP_LDMA_DST_BASE_LO_OFFSET_0 0xCE22F4
+
+#define mmNIC0_QM1_CP_LDMA_DST_BASE_LO_OFFSET_1 0xCE22F8
+
+#define mmNIC0_QM1_CP_LDMA_DST_BASE_LO_OFFSET_2 0xCE22FC
+
+#define mmNIC0_QM1_CP_LDMA_DST_BASE_LO_OFFSET_3 0xCE2300
+
+#define mmNIC0_QM1_CP_LDMA_DST_BASE_LO_OFFSET_4 0xCE2304
+
+#define mmNIC0_QM1_CP_FENCE0_RDATA_0 0xCE2308
+
+#define mmNIC0_QM1_CP_FENCE0_RDATA_1 0xCE230C
+
+#define mmNIC0_QM1_CP_FENCE0_RDATA_2 0xCE2310
+
+#define mmNIC0_QM1_CP_FENCE0_RDATA_3 0xCE2314
+
+#define mmNIC0_QM1_CP_FENCE0_RDATA_4 0xCE2318
+
+#define mmNIC0_QM1_CP_FENCE1_RDATA_0 0xCE231C
+
+#define mmNIC0_QM1_CP_FENCE1_RDATA_1 0xCE2320
+
+#define mmNIC0_QM1_CP_FENCE1_RDATA_2 0xCE2324
+
+#define mmNIC0_QM1_CP_FENCE1_RDATA_3 0xCE2328
+
+#define mmNIC0_QM1_CP_FENCE1_RDATA_4 0xCE232C
+
+#define mmNIC0_QM1_CP_FENCE2_RDATA_0 0xCE2330
+
+#define mmNIC0_QM1_CP_FENCE2_RDATA_1 0xCE2334
+
+#define mmNIC0_QM1_CP_FENCE2_RDATA_2 0xCE2338
+
+#define mmNIC0_QM1_CP_FENCE2_RDATA_3 0xCE233C
+
+#define mmNIC0_QM1_CP_FENCE2_RDATA_4 0xCE2340
+
+#define mmNIC0_QM1_CP_FENCE3_RDATA_0 0xCE2344
+
+#define mmNIC0_QM1_CP_FENCE3_RDATA_1 0xCE2348
+
+#define mmNIC0_QM1_CP_FENCE3_RDATA_2 0xCE234C
+
+#define mmNIC0_QM1_CP_FENCE3_RDATA_3 0xCE2350
+
+#define mmNIC0_QM1_CP_FENCE3_RDATA_4 0xCE2354
+
+#define mmNIC0_QM1_CP_FENCE0_CNT_0 0xCE2358
+
+#define mmNIC0_QM1_CP_FENCE0_CNT_1 0xCE235C
+
+#define mmNIC0_QM1_CP_FENCE0_CNT_2 0xCE2360
+
+#define mmNIC0_QM1_CP_FENCE0_CNT_3 0xCE2364
+
+#define mmNIC0_QM1_CP_FENCE0_CNT_4 0xCE2368
+
+#define mmNIC0_QM1_CP_FENCE1_CNT_0 0xCE236C
+
+#define mmNIC0_QM1_CP_FENCE1_CNT_1 0xCE2370
+
+#define mmNIC0_QM1_CP_FENCE1_CNT_2 0xCE2374
+
+#define mmNIC0_QM1_CP_FENCE1_CNT_3 0xCE2378
+
+#define mmNIC0_QM1_CP_FENCE1_CNT_4 0xCE237C
+
+#define mmNIC0_QM1_CP_FENCE2_CNT_0 0xCE2380
+
+#define mmNIC0_QM1_CP_FENCE2_CNT_1 0xCE2384
+
+#define mmNIC0_QM1_CP_FENCE2_CNT_2 0xCE2388
+
+#define mmNIC0_QM1_CP_FENCE2_CNT_3 0xCE238C
+
+#define mmNIC0_QM1_CP_FENCE2_CNT_4 0xCE2390
+
+#define mmNIC0_QM1_CP_FENCE3_CNT_0 0xCE2394
+
+#define mmNIC0_QM1_CP_FENCE3_CNT_1 0xCE2398
+
+#define mmNIC0_QM1_CP_FENCE3_CNT_2 0xCE239C
+
+#define mmNIC0_QM1_CP_FENCE3_CNT_3 0xCE23A0
+
+#define mmNIC0_QM1_CP_FENCE3_CNT_4 0xCE23A4
+
+#define mmNIC0_QM1_CP_STS_0 0xCE23A8
+
+#define mmNIC0_QM1_CP_STS_1 0xCE23AC
+
+#define mmNIC0_QM1_CP_STS_2 0xCE23B0
+
+#define mmNIC0_QM1_CP_STS_3 0xCE23B4
+
+#define mmNIC0_QM1_CP_STS_4 0xCE23B8
+
+#define mmNIC0_QM1_CP_CURRENT_INST_LO_0 0xCE23BC
+
+#define mmNIC0_QM1_CP_CURRENT_INST_LO_1 0xCE23C0
+
+#define mmNIC0_QM1_CP_CURRENT_INST_LO_2 0xCE23C4
+
+#define mmNIC0_QM1_CP_CURRENT_INST_LO_3 0xCE23C8
+
+#define mmNIC0_QM1_CP_CURRENT_INST_LO_4 0xCE23CC
+
+#define mmNIC0_QM1_CP_CURRENT_INST_HI_0 0xCE23D0
+
+#define mmNIC0_QM1_CP_CURRENT_INST_HI_1 0xCE23D4
+
+#define mmNIC0_QM1_CP_CURRENT_INST_HI_2 0xCE23D8
+
+#define mmNIC0_QM1_CP_CURRENT_INST_HI_3 0xCE23DC
+
+#define mmNIC0_QM1_CP_CURRENT_INST_HI_4 0xCE23E0
+
+#define mmNIC0_QM1_CP_BARRIER_CFG_0 0xCE23F4
+
+#define mmNIC0_QM1_CP_BARRIER_CFG_1 0xCE23F8
+
+#define mmNIC0_QM1_CP_BARRIER_CFG_2 0xCE23FC
+
+#define mmNIC0_QM1_CP_BARRIER_CFG_3 0xCE2400
+
+#define mmNIC0_QM1_CP_BARRIER_CFG_4 0xCE2404
+
+#define mmNIC0_QM1_CP_DBG_0_0 0xCE2408
+
+#define mmNIC0_QM1_CP_DBG_0_1 0xCE240C
+
+#define mmNIC0_QM1_CP_DBG_0_2 0xCE2410
+
+#define mmNIC0_QM1_CP_DBG_0_3 0xCE2414
+
+#define mmNIC0_QM1_CP_DBG_0_4 0xCE2418
+
+#define mmNIC0_QM1_CP_ARUSER_31_11_0 0xCE241C
+
+#define mmNIC0_QM1_CP_ARUSER_31_11_1 0xCE2420
+
+#define mmNIC0_QM1_CP_ARUSER_31_11_2 0xCE2424
+
+#define mmNIC0_QM1_CP_ARUSER_31_11_3 0xCE2428
+
+#define mmNIC0_QM1_CP_ARUSER_31_11_4 0xCE242C
+
+#define mmNIC0_QM1_CP_AWUSER_31_11_0 0xCE2430
+
+#define mmNIC0_QM1_CP_AWUSER_31_11_1 0xCE2434
+
+#define mmNIC0_QM1_CP_AWUSER_31_11_2 0xCE2438
+
+#define mmNIC0_QM1_CP_AWUSER_31_11_3 0xCE243C
+
+#define mmNIC0_QM1_CP_AWUSER_31_11_4 0xCE2440
+
+#define mmNIC0_QM1_ARB_CFG_0 0xCE2A00
+
+#define mmNIC0_QM1_ARB_CHOISE_Q_PUSH 0xCE2A04
+
+#define mmNIC0_QM1_ARB_WRR_WEIGHT_0 0xCE2A08
+
+#define mmNIC0_QM1_ARB_WRR_WEIGHT_1 0xCE2A0C
+
+#define mmNIC0_QM1_ARB_WRR_WEIGHT_2 0xCE2A10
+
+#define mmNIC0_QM1_ARB_WRR_WEIGHT_3 0xCE2A14
+
+#define mmNIC0_QM1_ARB_CFG_1 0xCE2A18
+
+#define mmNIC0_QM1_ARB_MST_AVAIL_CRED_0 0xCE2A20
+
+#define mmNIC0_QM1_ARB_MST_AVAIL_CRED_1 0xCE2A24
+
+#define mmNIC0_QM1_ARB_MST_AVAIL_CRED_2 0xCE2A28
+
+#define mmNIC0_QM1_ARB_MST_AVAIL_CRED_3 0xCE2A2C
+
+#define mmNIC0_QM1_ARB_MST_AVAIL_CRED_4 0xCE2A30
+
+#define mmNIC0_QM1_ARB_MST_AVAIL_CRED_5 0xCE2A34
+
+#define mmNIC0_QM1_ARB_MST_AVAIL_CRED_6 0xCE2A38
+
+#define mmNIC0_QM1_ARB_MST_AVAIL_CRED_7 0xCE2A3C
+
+#define mmNIC0_QM1_ARB_MST_AVAIL_CRED_8 0xCE2A40
+
+#define mmNIC0_QM1_ARB_MST_AVAIL_CRED_9 0xCE2A44
+
+#define mmNIC0_QM1_ARB_MST_AVAIL_CRED_10 0xCE2A48
+
+#define mmNIC0_QM1_ARB_MST_AVAIL_CRED_11 0xCE2A4C
+
+#define mmNIC0_QM1_ARB_MST_AVAIL_CRED_12 0xCE2A50
+
+#define mmNIC0_QM1_ARB_MST_AVAIL_CRED_13 0xCE2A54
+
+#define mmNIC0_QM1_ARB_MST_AVAIL_CRED_14 0xCE2A58
+
+#define mmNIC0_QM1_ARB_MST_AVAIL_CRED_15 0xCE2A5C
+
+#define mmNIC0_QM1_ARB_MST_AVAIL_CRED_16 0xCE2A60
+
+#define mmNIC0_QM1_ARB_MST_AVAIL_CRED_17 0xCE2A64
+
+#define mmNIC0_QM1_ARB_MST_AVAIL_CRED_18 0xCE2A68
+
+#define mmNIC0_QM1_ARB_MST_AVAIL_CRED_19 0xCE2A6C
+
+#define mmNIC0_QM1_ARB_MST_AVAIL_CRED_20 0xCE2A70
+
+#define mmNIC0_QM1_ARB_MST_AVAIL_CRED_21 0xCE2A74
+
+#define mmNIC0_QM1_ARB_MST_AVAIL_CRED_22 0xCE2A78
+
+#define mmNIC0_QM1_ARB_MST_AVAIL_CRED_23 0xCE2A7C
+
+#define mmNIC0_QM1_ARB_MST_AVAIL_CRED_24 0xCE2A80
+
+#define mmNIC0_QM1_ARB_MST_AVAIL_CRED_25 0xCE2A84
+
+#define mmNIC0_QM1_ARB_MST_AVAIL_CRED_26 0xCE2A88
+
+#define mmNIC0_QM1_ARB_MST_AVAIL_CRED_27 0xCE2A8C
+
+#define mmNIC0_QM1_ARB_MST_AVAIL_CRED_28 0xCE2A90
+
+#define mmNIC0_QM1_ARB_MST_AVAIL_CRED_29 0xCE2A94
+
+#define mmNIC0_QM1_ARB_MST_AVAIL_CRED_30 0xCE2A98
+
+#define mmNIC0_QM1_ARB_MST_AVAIL_CRED_31 0xCE2A9C
+
+#define mmNIC0_QM1_ARB_MST_CRED_INC 0xCE2AA0
+
+#define mmNIC0_QM1_ARB_MST_CHOISE_PUSH_OFST_0 0xCE2AA4
+
+#define mmNIC0_QM1_ARB_MST_CHOISE_PUSH_OFST_1 0xCE2AA8
+
+#define mmNIC0_QM1_ARB_MST_CHOISE_PUSH_OFST_2 0xCE2AAC
+
+#define mmNIC0_QM1_ARB_MST_CHOISE_PUSH_OFST_3 0xCE2AB0
+
+#define mmNIC0_QM1_ARB_MST_CHOISE_PUSH_OFST_4 0xCE2AB4
+
+#define mmNIC0_QM1_ARB_MST_CHOISE_PUSH_OFST_5 0xCE2AB8
+
+#define mmNIC0_QM1_ARB_MST_CHOISE_PUSH_OFST_6 0xCE2ABC
+
+#define mmNIC0_QM1_ARB_MST_CHOISE_PUSH_OFST_7 0xCE2AC0
+
+#define mmNIC0_QM1_ARB_MST_CHOISE_PUSH_OFST_8 0xCE2AC4
+
+#define mmNIC0_QM1_ARB_MST_CHOISE_PUSH_OFST_9 0xCE2AC8
+
+#define mmNIC0_QM1_ARB_MST_CHOISE_PUSH_OFST_10 0xCE2ACC
+
+#define mmNIC0_QM1_ARB_MST_CHOISE_PUSH_OFST_11 0xCE2AD0
+
+#define mmNIC0_QM1_ARB_MST_CHOISE_PUSH_OFST_12 0xCE2AD4
+
+#define mmNIC0_QM1_ARB_MST_CHOISE_PUSH_OFST_13 0xCE2AD8
+
+#define mmNIC0_QM1_ARB_MST_CHOISE_PUSH_OFST_14 0xCE2ADC
+
+#define mmNIC0_QM1_ARB_MST_CHOISE_PUSH_OFST_15 0xCE2AE0
+
+#define mmNIC0_QM1_ARB_MST_CHOISE_PUSH_OFST_16 0xCE2AE4
+
+#define mmNIC0_QM1_ARB_MST_CHOISE_PUSH_OFST_17 0xCE2AE8
+
+#define mmNIC0_QM1_ARB_MST_CHOISE_PUSH_OFST_18 0xCE2AEC
+
+#define mmNIC0_QM1_ARB_MST_CHOISE_PUSH_OFST_19 0xCE2AF0
+
+#define mmNIC0_QM1_ARB_MST_CHOISE_PUSH_OFST_20 0xCE2AF4
+
+#define mmNIC0_QM1_ARB_MST_CHOISE_PUSH_OFST_21 0xCE2AF8
+
+#define mmNIC0_QM1_ARB_MST_CHOISE_PUSH_OFST_22 0xCE2AFC
+
+#define mmNIC0_QM1_ARB_MST_CHOISE_PUSH_OFST_23 0xCE2B00
+
+#define mmNIC0_QM1_ARB_MST_CHOISE_PUSH_OFST_24 0xCE2B04
+
+#define mmNIC0_QM1_ARB_MST_CHOISE_PUSH_OFST_25 0xCE2B08
+
+#define mmNIC0_QM1_ARB_MST_CHOISE_PUSH_OFST_26 0xCE2B0C
+
+#define mmNIC0_QM1_ARB_MST_CHOISE_PUSH_OFST_27 0xCE2B10
+
+#define mmNIC0_QM1_ARB_MST_CHOISE_PUSH_OFST_28 0xCE2B14
+
+#define mmNIC0_QM1_ARB_MST_CHOISE_PUSH_OFST_29 0xCE2B18
+
+#define mmNIC0_QM1_ARB_MST_CHOISE_PUSH_OFST_30 0xCE2B1C
+
+#define mmNIC0_QM1_ARB_MST_CHOISE_PUSH_OFST_31 0xCE2B20
+
+#define mmNIC0_QM1_ARB_SLV_MASTER_INC_CRED_OFST 0xCE2B28
+
+#define mmNIC0_QM1_ARB_MST_SLAVE_EN 0xCE2B2C
+
+#define mmNIC0_QM1_ARB_MST_QUIET_PER 0xCE2B34
+
+#define mmNIC0_QM1_ARB_SLV_CHOISE_WDT 0xCE2B38
+
+#define mmNIC0_QM1_ARB_SLV_ID 0xCE2B3C
+
+#define mmNIC0_QM1_ARB_MSG_MAX_INFLIGHT 0xCE2B44
+
+#define mmNIC0_QM1_ARB_MSG_AWUSER_31_11 0xCE2B48
+
+#define mmNIC0_QM1_ARB_MSG_AWUSER_SEC_PROP 0xCE2B4C
+
+#define mmNIC0_QM1_ARB_MSG_AWUSER_NON_SEC_PROP 0xCE2B50
+
+#define mmNIC0_QM1_ARB_BASE_LO 0xCE2B54
+
+#define mmNIC0_QM1_ARB_BASE_HI 0xCE2B58
+
+#define mmNIC0_QM1_ARB_STATE_STS 0xCE2B80
+
+#define mmNIC0_QM1_ARB_CHOISE_FULLNESS_STS 0xCE2B84
+
+#define mmNIC0_QM1_ARB_MSG_STS 0xCE2B88
+
+#define mmNIC0_QM1_ARB_SLV_CHOISE_Q_HEAD 0xCE2B8C
+
+#define mmNIC0_QM1_ARB_ERR_CAUSE 0xCE2B9C
+
+#define mmNIC0_QM1_ARB_ERR_MSG_EN 0xCE2BA0
+
+#define mmNIC0_QM1_ARB_ERR_STS_DRP 0xCE2BA8
+
+#define mmNIC0_QM1_ARB_MST_CRED_STS_0 0xCE2BB0
+
+#define mmNIC0_QM1_ARB_MST_CRED_STS_1 0xCE2BB4
+
+#define mmNIC0_QM1_ARB_MST_CRED_STS_2 0xCE2BB8
+
+#define mmNIC0_QM1_ARB_MST_CRED_STS_3 0xCE2BBC
+
+#define mmNIC0_QM1_ARB_MST_CRED_STS_4 0xCE2BC0
+
+#define mmNIC0_QM1_ARB_MST_CRED_STS_5 0xCE2BC4
+
+#define mmNIC0_QM1_ARB_MST_CRED_STS_6 0xCE2BC8
+
+#define mmNIC0_QM1_ARB_MST_CRED_STS_7 0xCE2BCC
+
+#define mmNIC0_QM1_ARB_MST_CRED_STS_8 0xCE2BD0
+
+#define mmNIC0_QM1_ARB_MST_CRED_STS_9 0xCE2BD4
+
+#define mmNIC0_QM1_ARB_MST_CRED_STS_10 0xCE2BD8
+
+#define mmNIC0_QM1_ARB_MST_CRED_STS_11 0xCE2BDC
+
+#define mmNIC0_QM1_ARB_MST_CRED_STS_12 0xCE2BE0
+
+#define mmNIC0_QM1_ARB_MST_CRED_STS_13 0xCE2BE4
+
+#define mmNIC0_QM1_ARB_MST_CRED_STS_14 0xCE2BE8
+
+#define mmNIC0_QM1_ARB_MST_CRED_STS_15 0xCE2BEC
+
+#define mmNIC0_QM1_ARB_MST_CRED_STS_16 0xCE2BF0
+
+#define mmNIC0_QM1_ARB_MST_CRED_STS_17 0xCE2BF4
+
+#define mmNIC0_QM1_ARB_MST_CRED_STS_18 0xCE2BF8
+
+#define mmNIC0_QM1_ARB_MST_CRED_STS_19 0xCE2BFC
+
+#define mmNIC0_QM1_ARB_MST_CRED_STS_20 0xCE2C00
+
+#define mmNIC0_QM1_ARB_MST_CRED_STS_21 0xCE2C04
+
+#define mmNIC0_QM1_ARB_MST_CRED_STS_22 0xCE2C08
+
+#define mmNIC0_QM1_ARB_MST_CRED_STS_23 0xCE2C0C
+
+#define mmNIC0_QM1_ARB_MST_CRED_STS_24 0xCE2C10
+
+#define mmNIC0_QM1_ARB_MST_CRED_STS_25 0xCE2C14
+
+#define mmNIC0_QM1_ARB_MST_CRED_STS_26 0xCE2C18
+
+#define mmNIC0_QM1_ARB_MST_CRED_STS_27 0xCE2C1C
+
+#define mmNIC0_QM1_ARB_MST_CRED_STS_28 0xCE2C20
+
+#define mmNIC0_QM1_ARB_MST_CRED_STS_29 0xCE2C24
+
+#define mmNIC0_QM1_ARB_MST_CRED_STS_30 0xCE2C28
+
+#define mmNIC0_QM1_ARB_MST_CRED_STS_31 0xCE2C2C
+
+#define mmNIC0_QM1_CGM_CFG 0xCE2C70
+
+#define mmNIC0_QM1_CGM_STS 0xCE2C74
+
+#define mmNIC0_QM1_CGM_CFG1 0xCE2C78
+
+#define mmNIC0_QM1_LOCAL_RANGE_BASE 0xCE2C80
+
+#define mmNIC0_QM1_LOCAL_RANGE_SIZE 0xCE2C84
+
+#define mmNIC0_QM1_CSMR_STRICT_PRIO_CFG 0xCE2C90
+
+#define mmNIC0_QM1_HBW_RD_RATE_LIM_CFG_1 0xCE2C94
+
+#define mmNIC0_QM1_LBW_WR_RATE_LIM_CFG_0 0xCE2C98
+
+#define mmNIC0_QM1_LBW_WR_RATE_LIM_CFG_1 0xCE2C9C
+
+#define mmNIC0_QM1_HBW_RD_RATE_LIM_CFG_0 0xCE2CA0
+
+#define mmNIC0_QM1_GLBL_AXCACHE 0xCE2CA4
+
+#define mmNIC0_QM1_IND_GW_APB_CFG 0xCE2CB0
+
+#define mmNIC0_QM1_IND_GW_APB_WDATA 0xCE2CB4
+
+#define mmNIC0_QM1_IND_GW_APB_RDATA 0xCE2CB8
+
+#define mmNIC0_QM1_IND_GW_APB_STATUS 0xCE2CBC
+
+#define mmNIC0_QM1_GLBL_ERR_ADDR_LO 0xCE2CD0
+
+#define mmNIC0_QM1_GLBL_ERR_ADDR_HI 0xCE2CD4
+
+#define mmNIC0_QM1_GLBL_ERR_WDATA 0xCE2CD8
+
+#define mmNIC0_QM1_GLBL_MEM_INIT_BUSY 0xCE2D00
+
+#endif /* ASIC_REG_NIC0_QM1_REGS_H_ */
diff --git a/drivers/accel/habanalabs/include/gaudi/asic_reg/nic1_qm0_regs.h b/drivers/accel/habanalabs/include/gaudi/asic_reg/nic1_qm0_regs.h
new file mode 100644
index 0000000000..0d1caf057a
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi/asic_reg/nic1_qm0_regs.h
@@ -0,0 +1,834 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2016-2018 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ ** DO NOT EDIT BELOW **
+ ************************************/
+
+#ifndef ASIC_REG_NIC1_QM0_REGS_H_
+#define ASIC_REG_NIC1_QM0_REGS_H_
+
+/*
+ *****************************************
+ * NIC1_QM0 (Prototype: QMAN)
+ *****************************************
+ */
+
+#define mmNIC1_QM0_GLBL_CFG0 0xD20000
+
+#define mmNIC1_QM0_GLBL_CFG1 0xD20004
+
+#define mmNIC1_QM0_GLBL_PROT 0xD20008
+
+#define mmNIC1_QM0_GLBL_ERR_CFG 0xD2000C
+
+#define mmNIC1_QM0_GLBL_SECURE_PROPS_0 0xD20010
+
+#define mmNIC1_QM0_GLBL_SECURE_PROPS_1 0xD20014
+
+#define mmNIC1_QM0_GLBL_SECURE_PROPS_2 0xD20018
+
+#define mmNIC1_QM0_GLBL_SECURE_PROPS_3 0xD2001C
+
+#define mmNIC1_QM0_GLBL_SECURE_PROPS_4 0xD20020
+
+#define mmNIC1_QM0_GLBL_NON_SECURE_PROPS_0 0xD20024
+
+#define mmNIC1_QM0_GLBL_NON_SECURE_PROPS_1 0xD20028
+
+#define mmNIC1_QM0_GLBL_NON_SECURE_PROPS_2 0xD2002C
+
+#define mmNIC1_QM0_GLBL_NON_SECURE_PROPS_3 0xD20030
+
+#define mmNIC1_QM0_GLBL_NON_SECURE_PROPS_4 0xD20034
+
+#define mmNIC1_QM0_GLBL_STS0 0xD20038
+
+#define mmNIC1_QM0_GLBL_STS1_0 0xD20040
+
+#define mmNIC1_QM0_GLBL_STS1_1 0xD20044
+
+#define mmNIC1_QM0_GLBL_STS1_2 0xD20048
+
+#define mmNIC1_QM0_GLBL_STS1_3 0xD2004C
+
+#define mmNIC1_QM0_GLBL_STS1_4 0xD20050
+
+#define mmNIC1_QM0_GLBL_MSG_EN_0 0xD20054
+
+#define mmNIC1_QM0_GLBL_MSG_EN_1 0xD20058
+
+#define mmNIC1_QM0_GLBL_MSG_EN_2 0xD2005C
+
+#define mmNIC1_QM0_GLBL_MSG_EN_3 0xD20060
+
+#define mmNIC1_QM0_GLBL_MSG_EN_4 0xD20068
+
+#define mmNIC1_QM0_PQ_BASE_LO_0 0xD20070
+
+#define mmNIC1_QM0_PQ_BASE_LO_1 0xD20074
+
+#define mmNIC1_QM0_PQ_BASE_LO_2 0xD20078
+
+#define mmNIC1_QM0_PQ_BASE_LO_3 0xD2007C
+
+#define mmNIC1_QM0_PQ_BASE_HI_0 0xD20080
+
+#define mmNIC1_QM0_PQ_BASE_HI_1 0xD20084
+
+#define mmNIC1_QM0_PQ_BASE_HI_2 0xD20088
+
+#define mmNIC1_QM0_PQ_BASE_HI_3 0xD2008C
+
+#define mmNIC1_QM0_PQ_SIZE_0 0xD20090
+
+#define mmNIC1_QM0_PQ_SIZE_1 0xD20094
+
+#define mmNIC1_QM0_PQ_SIZE_2 0xD20098
+
+#define mmNIC1_QM0_PQ_SIZE_3 0xD2009C
+
+#define mmNIC1_QM0_PQ_PI_0 0xD200A0
+
+#define mmNIC1_QM0_PQ_PI_1 0xD200A4
+
+#define mmNIC1_QM0_PQ_PI_2 0xD200A8
+
+#define mmNIC1_QM0_PQ_PI_3 0xD200AC
+
+#define mmNIC1_QM0_PQ_CI_0 0xD200B0
+
+#define mmNIC1_QM0_PQ_CI_1 0xD200B4
+
+#define mmNIC1_QM0_PQ_CI_2 0xD200B8
+
+#define mmNIC1_QM0_PQ_CI_3 0xD200BC
+
+#define mmNIC1_QM0_PQ_CFG0_0 0xD200C0
+
+#define mmNIC1_QM0_PQ_CFG0_1 0xD200C4
+
+#define mmNIC1_QM0_PQ_CFG0_2 0xD200C8
+
+#define mmNIC1_QM0_PQ_CFG0_3 0xD200CC
+
+#define mmNIC1_QM0_PQ_CFG1_0 0xD200D0
+
+#define mmNIC1_QM0_PQ_CFG1_1 0xD200D4
+
+#define mmNIC1_QM0_PQ_CFG1_2 0xD200D8
+
+#define mmNIC1_QM0_PQ_CFG1_3 0xD200DC
+
+#define mmNIC1_QM0_PQ_ARUSER_31_11_0 0xD200E0
+
+#define mmNIC1_QM0_PQ_ARUSER_31_11_1 0xD200E4
+
+#define mmNIC1_QM0_PQ_ARUSER_31_11_2 0xD200E8
+
+#define mmNIC1_QM0_PQ_ARUSER_31_11_3 0xD200EC
+
+#define mmNIC1_QM0_PQ_STS0_0 0xD200F0
+
+#define mmNIC1_QM0_PQ_STS0_1 0xD200F4
+
+#define mmNIC1_QM0_PQ_STS0_2 0xD200F8
+
+#define mmNIC1_QM0_PQ_STS0_3 0xD200FC
+
+#define mmNIC1_QM0_PQ_STS1_0 0xD20100
+
+#define mmNIC1_QM0_PQ_STS1_1 0xD20104
+
+#define mmNIC1_QM0_PQ_STS1_2 0xD20108
+
+#define mmNIC1_QM0_PQ_STS1_3 0xD2010C
+
+#define mmNIC1_QM0_CQ_CFG0_0 0xD20110
+
+#define mmNIC1_QM0_CQ_CFG0_1 0xD20114
+
+#define mmNIC1_QM0_CQ_CFG0_2 0xD20118
+
+#define mmNIC1_QM0_CQ_CFG0_3 0xD2011C
+
+#define mmNIC1_QM0_CQ_CFG0_4 0xD20120
+
+#define mmNIC1_QM0_CQ_CFG1_0 0xD20124
+
+#define mmNIC1_QM0_CQ_CFG1_1 0xD20128
+
+#define mmNIC1_QM0_CQ_CFG1_2 0xD2012C
+
+#define mmNIC1_QM0_CQ_CFG1_3 0xD20130
+
+#define mmNIC1_QM0_CQ_CFG1_4 0xD20134
+
+#define mmNIC1_QM0_CQ_ARUSER_31_11_0 0xD20138
+
+#define mmNIC1_QM0_CQ_ARUSER_31_11_1 0xD2013C
+
+#define mmNIC1_QM0_CQ_ARUSER_31_11_2 0xD20140
+
+#define mmNIC1_QM0_CQ_ARUSER_31_11_3 0xD20144
+
+#define mmNIC1_QM0_CQ_ARUSER_31_11_4 0xD20148
+
+#define mmNIC1_QM0_CQ_STS0_0 0xD2014C
+
+#define mmNIC1_QM0_CQ_STS0_1 0xD20150
+
+#define mmNIC1_QM0_CQ_STS0_2 0xD20154
+
+#define mmNIC1_QM0_CQ_STS0_3 0xD20158
+
+#define mmNIC1_QM0_CQ_STS0_4 0xD2015C
+
+#define mmNIC1_QM0_CQ_STS1_0 0xD20160
+
+#define mmNIC1_QM0_CQ_STS1_1 0xD20164
+
+#define mmNIC1_QM0_CQ_STS1_2 0xD20168
+
+#define mmNIC1_QM0_CQ_STS1_3 0xD2016C
+
+#define mmNIC1_QM0_CQ_STS1_4 0xD20170
+
+#define mmNIC1_QM0_CQ_PTR_LO_0 0xD20174
+
+#define mmNIC1_QM0_CQ_PTR_HI_0 0xD20178
+
+#define mmNIC1_QM0_CQ_TSIZE_0 0xD2017C
+
+#define mmNIC1_QM0_CQ_CTL_0 0xD20180
+
+#define mmNIC1_QM0_CQ_PTR_LO_1 0xD20184
+
+#define mmNIC1_QM0_CQ_PTR_HI_1 0xD20188
+
+#define mmNIC1_QM0_CQ_TSIZE_1 0xD2018C
+
+#define mmNIC1_QM0_CQ_CTL_1 0xD20190
+
+#define mmNIC1_QM0_CQ_PTR_LO_2 0xD20194
+
+#define mmNIC1_QM0_CQ_PTR_HI_2 0xD20198
+
+#define mmNIC1_QM0_CQ_TSIZE_2 0xD2019C
+
+#define mmNIC1_QM0_CQ_CTL_2 0xD201A0
+
+#define mmNIC1_QM0_CQ_PTR_LO_3 0xD201A4
+
+#define mmNIC1_QM0_CQ_PTR_HI_3 0xD201A8
+
+#define mmNIC1_QM0_CQ_TSIZE_3 0xD201AC
+
+#define mmNIC1_QM0_CQ_CTL_3 0xD201B0
+
+#define mmNIC1_QM0_CQ_PTR_LO_4 0xD201B4
+
+#define mmNIC1_QM0_CQ_PTR_HI_4 0xD201B8
+
+#define mmNIC1_QM0_CQ_TSIZE_4 0xD201BC
+
+#define mmNIC1_QM0_CQ_CTL_4 0xD201C0
+
+#define mmNIC1_QM0_CQ_PTR_LO_STS_0 0xD201C4
+
+#define mmNIC1_QM0_CQ_PTR_LO_STS_1 0xD201C8
+
+#define mmNIC1_QM0_CQ_PTR_LO_STS_2 0xD201CC
+
+#define mmNIC1_QM0_CQ_PTR_LO_STS_3 0xD201D0
+
+#define mmNIC1_QM0_CQ_PTR_LO_STS_4 0xD201D4
+
+#define mmNIC1_QM0_CQ_PTR_HI_STS_0 0xD201D8
+
+#define mmNIC1_QM0_CQ_PTR_HI_STS_1 0xD201DC
+
+#define mmNIC1_QM0_CQ_PTR_HI_STS_2 0xD201E0
+
+#define mmNIC1_QM0_CQ_PTR_HI_STS_3 0xD201E4
+
+#define mmNIC1_QM0_CQ_PTR_HI_STS_4 0xD201E8
+
+#define mmNIC1_QM0_CQ_TSIZE_STS_0 0xD201EC
+
+#define mmNIC1_QM0_CQ_TSIZE_STS_1 0xD201F0
+
+#define mmNIC1_QM0_CQ_TSIZE_STS_2 0xD201F4
+
+#define mmNIC1_QM0_CQ_TSIZE_STS_3 0xD201F8
+
+#define mmNIC1_QM0_CQ_TSIZE_STS_4 0xD201FC
+
+#define mmNIC1_QM0_CQ_CTL_STS_0 0xD20200
+
+#define mmNIC1_QM0_CQ_CTL_STS_1 0xD20204
+
+#define mmNIC1_QM0_CQ_CTL_STS_2 0xD20208
+
+#define mmNIC1_QM0_CQ_CTL_STS_3 0xD2020C
+
+#define mmNIC1_QM0_CQ_CTL_STS_4 0xD20210
+
+#define mmNIC1_QM0_CQ_IFIFO_CNT_0 0xD20214
+
+#define mmNIC1_QM0_CQ_IFIFO_CNT_1 0xD20218
+
+#define mmNIC1_QM0_CQ_IFIFO_CNT_2 0xD2021C
+
+#define mmNIC1_QM0_CQ_IFIFO_CNT_3 0xD20220
+
+#define mmNIC1_QM0_CQ_IFIFO_CNT_4 0xD20224
+
+#define mmNIC1_QM0_CP_MSG_BASE0_ADDR_LO_0 0xD20228
+
+#define mmNIC1_QM0_CP_MSG_BASE0_ADDR_LO_1 0xD2022C
+
+#define mmNIC1_QM0_CP_MSG_BASE0_ADDR_LO_2 0xD20230
+
+#define mmNIC1_QM0_CP_MSG_BASE0_ADDR_LO_3 0xD20234
+
+#define mmNIC1_QM0_CP_MSG_BASE0_ADDR_LO_4 0xD20238
+
+#define mmNIC1_QM0_CP_MSG_BASE0_ADDR_HI_0 0xD2023C
+
+#define mmNIC1_QM0_CP_MSG_BASE0_ADDR_HI_1 0xD20240
+
+#define mmNIC1_QM0_CP_MSG_BASE0_ADDR_HI_2 0xD20244
+
+#define mmNIC1_QM0_CP_MSG_BASE0_ADDR_HI_3 0xD20248
+
+#define mmNIC1_QM0_CP_MSG_BASE0_ADDR_HI_4 0xD2024C
+
+#define mmNIC1_QM0_CP_MSG_BASE1_ADDR_LO_0 0xD20250
+
+#define mmNIC1_QM0_CP_MSG_BASE1_ADDR_LO_1 0xD20254
+
+#define mmNIC1_QM0_CP_MSG_BASE1_ADDR_LO_2 0xD20258
+
+#define mmNIC1_QM0_CP_MSG_BASE1_ADDR_LO_3 0xD2025C
+
+#define mmNIC1_QM0_CP_MSG_BASE1_ADDR_LO_4 0xD20260
+
+#define mmNIC1_QM0_CP_MSG_BASE1_ADDR_HI_0 0xD20264
+
+#define mmNIC1_QM0_CP_MSG_BASE1_ADDR_HI_1 0xD20268
+
+#define mmNIC1_QM0_CP_MSG_BASE1_ADDR_HI_2 0xD2026C
+
+#define mmNIC1_QM0_CP_MSG_BASE1_ADDR_HI_3 0xD20270
+
+#define mmNIC1_QM0_CP_MSG_BASE1_ADDR_HI_4 0xD20274
+
+#define mmNIC1_QM0_CP_MSG_BASE2_ADDR_LO_0 0xD20278
+
+#define mmNIC1_QM0_CP_MSG_BASE2_ADDR_LO_1 0xD2027C
+
+#define mmNIC1_QM0_CP_MSG_BASE2_ADDR_LO_2 0xD20280
+
+#define mmNIC1_QM0_CP_MSG_BASE2_ADDR_LO_3 0xD20284
+
+#define mmNIC1_QM0_CP_MSG_BASE2_ADDR_LO_4 0xD20288
+
+#define mmNIC1_QM0_CP_MSG_BASE2_ADDR_HI_0 0xD2028C
+
+#define mmNIC1_QM0_CP_MSG_BASE2_ADDR_HI_1 0xD20290
+
+#define mmNIC1_QM0_CP_MSG_BASE2_ADDR_HI_2 0xD20294
+
+#define mmNIC1_QM0_CP_MSG_BASE2_ADDR_HI_3 0xD20298
+
+#define mmNIC1_QM0_CP_MSG_BASE2_ADDR_HI_4 0xD2029C
+
+#define mmNIC1_QM0_CP_MSG_BASE3_ADDR_LO_0 0xD202A0
+
+#define mmNIC1_QM0_CP_MSG_BASE3_ADDR_LO_1 0xD202A4
+
+#define mmNIC1_QM0_CP_MSG_BASE3_ADDR_LO_2 0xD202A8
+
+#define mmNIC1_QM0_CP_MSG_BASE3_ADDR_LO_3 0xD202AC
+
+#define mmNIC1_QM0_CP_MSG_BASE3_ADDR_LO_4 0xD202B0
+
+#define mmNIC1_QM0_CP_MSG_BASE3_ADDR_HI_0 0xD202B4
+
+#define mmNIC1_QM0_CP_MSG_BASE3_ADDR_HI_1 0xD202B8
+
+#define mmNIC1_QM0_CP_MSG_BASE3_ADDR_HI_2 0xD202BC
+
+#define mmNIC1_QM0_CP_MSG_BASE3_ADDR_HI_3 0xD202C0
+
+#define mmNIC1_QM0_CP_MSG_BASE3_ADDR_HI_4 0xD202C4
+
+#define mmNIC1_QM0_CP_LDMA_TSIZE_OFFSET_0 0xD202C8
+
+#define mmNIC1_QM0_CP_LDMA_TSIZE_OFFSET_1 0xD202CC
+
+#define mmNIC1_QM0_CP_LDMA_TSIZE_OFFSET_2 0xD202D0
+
+#define mmNIC1_QM0_CP_LDMA_TSIZE_OFFSET_3 0xD202D4
+
+#define mmNIC1_QM0_CP_LDMA_TSIZE_OFFSET_4 0xD202D8
+
+#define mmNIC1_QM0_CP_LDMA_SRC_BASE_LO_OFFSET_0 0xD202E0
+
+#define mmNIC1_QM0_CP_LDMA_SRC_BASE_LO_OFFSET_1 0xD202E4
+
+#define mmNIC1_QM0_CP_LDMA_SRC_BASE_LO_OFFSET_2 0xD202E8
+
+#define mmNIC1_QM0_CP_LDMA_SRC_BASE_LO_OFFSET_3 0xD202EC
+
+#define mmNIC1_QM0_CP_LDMA_SRC_BASE_LO_OFFSET_4 0xD202F0
+
+#define mmNIC1_QM0_CP_LDMA_DST_BASE_LO_OFFSET_0 0xD202F4
+
+#define mmNIC1_QM0_CP_LDMA_DST_BASE_LO_OFFSET_1 0xD202F8
+
+#define mmNIC1_QM0_CP_LDMA_DST_BASE_LO_OFFSET_2 0xD202FC
+
+#define mmNIC1_QM0_CP_LDMA_DST_BASE_LO_OFFSET_3 0xD20300
+
+#define mmNIC1_QM0_CP_LDMA_DST_BASE_LO_OFFSET_4 0xD20304
+
+#define mmNIC1_QM0_CP_FENCE0_RDATA_0 0xD20308
+
+#define mmNIC1_QM0_CP_FENCE0_RDATA_1 0xD2030C
+
+#define mmNIC1_QM0_CP_FENCE0_RDATA_2 0xD20310
+
+#define mmNIC1_QM0_CP_FENCE0_RDATA_3 0xD20314
+
+#define mmNIC1_QM0_CP_FENCE0_RDATA_4 0xD20318
+
+#define mmNIC1_QM0_CP_FENCE1_RDATA_0 0xD2031C
+
+#define mmNIC1_QM0_CP_FENCE1_RDATA_1 0xD20320
+
+#define mmNIC1_QM0_CP_FENCE1_RDATA_2 0xD20324
+
+#define mmNIC1_QM0_CP_FENCE1_RDATA_3 0xD20328
+
+#define mmNIC1_QM0_CP_FENCE1_RDATA_4 0xD2032C
+
+#define mmNIC1_QM0_CP_FENCE2_RDATA_0 0xD20330
+
+#define mmNIC1_QM0_CP_FENCE2_RDATA_1 0xD20334
+
+#define mmNIC1_QM0_CP_FENCE2_RDATA_2 0xD20338
+
+#define mmNIC1_QM0_CP_FENCE2_RDATA_3 0xD2033C
+
+#define mmNIC1_QM0_CP_FENCE2_RDATA_4 0xD20340
+
+#define mmNIC1_QM0_CP_FENCE3_RDATA_0 0xD20344
+
+#define mmNIC1_QM0_CP_FENCE3_RDATA_1 0xD20348
+
+#define mmNIC1_QM0_CP_FENCE3_RDATA_2 0xD2034C
+
+#define mmNIC1_QM0_CP_FENCE3_RDATA_3 0xD20350
+
+#define mmNIC1_QM0_CP_FENCE3_RDATA_4 0xD20354
+
+#define mmNIC1_QM0_CP_FENCE0_CNT_0 0xD20358
+
+#define mmNIC1_QM0_CP_FENCE0_CNT_1 0xD2035C
+
+#define mmNIC1_QM0_CP_FENCE0_CNT_2 0xD20360
+
+#define mmNIC1_QM0_CP_FENCE0_CNT_3 0xD20364
+
+#define mmNIC1_QM0_CP_FENCE0_CNT_4 0xD20368
+
+#define mmNIC1_QM0_CP_FENCE1_CNT_0 0xD2036C
+
+#define mmNIC1_QM0_CP_FENCE1_CNT_1 0xD20370
+
+#define mmNIC1_QM0_CP_FENCE1_CNT_2 0xD20374
+
+#define mmNIC1_QM0_CP_FENCE1_CNT_3 0xD20378
+
+#define mmNIC1_QM0_CP_FENCE1_CNT_4 0xD2037C
+
+#define mmNIC1_QM0_CP_FENCE2_CNT_0 0xD20380
+
+#define mmNIC1_QM0_CP_FENCE2_CNT_1 0xD20384
+
+#define mmNIC1_QM0_CP_FENCE2_CNT_2 0xD20388
+
+#define mmNIC1_QM0_CP_FENCE2_CNT_3 0xD2038C
+
+#define mmNIC1_QM0_CP_FENCE2_CNT_4 0xD20390
+
+#define mmNIC1_QM0_CP_FENCE3_CNT_0 0xD20394
+
+#define mmNIC1_QM0_CP_FENCE3_CNT_1 0xD20398
+
+#define mmNIC1_QM0_CP_FENCE3_CNT_2 0xD2039C
+
+#define mmNIC1_QM0_CP_FENCE3_CNT_3 0xD203A0
+
+#define mmNIC1_QM0_CP_FENCE3_CNT_4 0xD203A4
+
+#define mmNIC1_QM0_CP_STS_0 0xD203A8
+
+#define mmNIC1_QM0_CP_STS_1 0xD203AC
+
+#define mmNIC1_QM0_CP_STS_2 0xD203B0
+
+#define mmNIC1_QM0_CP_STS_3 0xD203B4
+
+#define mmNIC1_QM0_CP_STS_4 0xD203B8
+
+#define mmNIC1_QM0_CP_CURRENT_INST_LO_0 0xD203BC
+
+#define mmNIC1_QM0_CP_CURRENT_INST_LO_1 0xD203C0
+
+#define mmNIC1_QM0_CP_CURRENT_INST_LO_2 0xD203C4
+
+#define mmNIC1_QM0_CP_CURRENT_INST_LO_3 0xD203C8
+
+#define mmNIC1_QM0_CP_CURRENT_INST_LO_4 0xD203CC
+
+#define mmNIC1_QM0_CP_CURRENT_INST_HI_0 0xD203D0
+
+#define mmNIC1_QM0_CP_CURRENT_INST_HI_1 0xD203D4
+
+#define mmNIC1_QM0_CP_CURRENT_INST_HI_2 0xD203D8
+
+#define mmNIC1_QM0_CP_CURRENT_INST_HI_3 0xD203DC
+
+#define mmNIC1_QM0_CP_CURRENT_INST_HI_4 0xD203E0
+
+#define mmNIC1_QM0_CP_BARRIER_CFG_0 0xD203F4
+
+#define mmNIC1_QM0_CP_BARRIER_CFG_1 0xD203F8
+
+#define mmNIC1_QM0_CP_BARRIER_CFG_2 0xD203FC
+
+#define mmNIC1_QM0_CP_BARRIER_CFG_3 0xD20400
+
+#define mmNIC1_QM0_CP_BARRIER_CFG_4 0xD20404
+
+#define mmNIC1_QM0_CP_DBG_0_0 0xD20408
+
+#define mmNIC1_QM0_CP_DBG_0_1 0xD2040C
+
+#define mmNIC1_QM0_CP_DBG_0_2 0xD20410
+
+#define mmNIC1_QM0_CP_DBG_0_3 0xD20414
+
+#define mmNIC1_QM0_CP_DBG_0_4 0xD20418
+
+#define mmNIC1_QM0_CP_ARUSER_31_11_0 0xD2041C
+
+#define mmNIC1_QM0_CP_ARUSER_31_11_1 0xD20420
+
+#define mmNIC1_QM0_CP_ARUSER_31_11_2 0xD20424
+
+#define mmNIC1_QM0_CP_ARUSER_31_11_3 0xD20428
+
+#define mmNIC1_QM0_CP_ARUSER_31_11_4 0xD2042C
+
+#define mmNIC1_QM0_CP_AWUSER_31_11_0 0xD20430
+
+#define mmNIC1_QM0_CP_AWUSER_31_11_1 0xD20434
+
+#define mmNIC1_QM0_CP_AWUSER_31_11_2 0xD20438
+
+#define mmNIC1_QM0_CP_AWUSER_31_11_3 0xD2043C
+
+#define mmNIC1_QM0_CP_AWUSER_31_11_4 0xD20440
+
+#define mmNIC1_QM0_ARB_CFG_0 0xD20A00
+
+#define mmNIC1_QM0_ARB_CHOISE_Q_PUSH 0xD20A04
+
+#define mmNIC1_QM0_ARB_WRR_WEIGHT_0 0xD20A08
+
+#define mmNIC1_QM0_ARB_WRR_WEIGHT_1 0xD20A0C
+
+#define mmNIC1_QM0_ARB_WRR_WEIGHT_2 0xD20A10
+
+#define mmNIC1_QM0_ARB_WRR_WEIGHT_3 0xD20A14
+
+#define mmNIC1_QM0_ARB_CFG_1 0xD20A18
+
+#define mmNIC1_QM0_ARB_MST_AVAIL_CRED_0 0xD20A20
+
+#define mmNIC1_QM0_ARB_MST_AVAIL_CRED_1 0xD20A24
+
+#define mmNIC1_QM0_ARB_MST_AVAIL_CRED_2 0xD20A28
+
+#define mmNIC1_QM0_ARB_MST_AVAIL_CRED_3 0xD20A2C
+
+#define mmNIC1_QM0_ARB_MST_AVAIL_CRED_4 0xD20A30
+
+#define mmNIC1_QM0_ARB_MST_AVAIL_CRED_5 0xD20A34
+
+#define mmNIC1_QM0_ARB_MST_AVAIL_CRED_6 0xD20A38
+
+#define mmNIC1_QM0_ARB_MST_AVAIL_CRED_7 0xD20A3C
+
+#define mmNIC1_QM0_ARB_MST_AVAIL_CRED_8 0xD20A40
+
+#define mmNIC1_QM0_ARB_MST_AVAIL_CRED_9 0xD20A44
+
+#define mmNIC1_QM0_ARB_MST_AVAIL_CRED_10 0xD20A48
+
+#define mmNIC1_QM0_ARB_MST_AVAIL_CRED_11 0xD20A4C
+
+#define mmNIC1_QM0_ARB_MST_AVAIL_CRED_12 0xD20A50
+
+#define mmNIC1_QM0_ARB_MST_AVAIL_CRED_13 0xD20A54
+
+#define mmNIC1_QM0_ARB_MST_AVAIL_CRED_14 0xD20A58
+
+#define mmNIC1_QM0_ARB_MST_AVAIL_CRED_15 0xD20A5C
+
+#define mmNIC1_QM0_ARB_MST_AVAIL_CRED_16 0xD20A60
+
+#define mmNIC1_QM0_ARB_MST_AVAIL_CRED_17 0xD20A64
+
+#define mmNIC1_QM0_ARB_MST_AVAIL_CRED_18 0xD20A68
+
+#define mmNIC1_QM0_ARB_MST_AVAIL_CRED_19 0xD20A6C
+
+#define mmNIC1_QM0_ARB_MST_AVAIL_CRED_20 0xD20A70
+
+#define mmNIC1_QM0_ARB_MST_AVAIL_CRED_21 0xD20A74
+
+#define mmNIC1_QM0_ARB_MST_AVAIL_CRED_22 0xD20A78
+
+#define mmNIC1_QM0_ARB_MST_AVAIL_CRED_23 0xD20A7C
+
+#define mmNIC1_QM0_ARB_MST_AVAIL_CRED_24 0xD20A80
+
+#define mmNIC1_QM0_ARB_MST_AVAIL_CRED_25 0xD20A84
+
+#define mmNIC1_QM0_ARB_MST_AVAIL_CRED_26 0xD20A88
+
+#define mmNIC1_QM0_ARB_MST_AVAIL_CRED_27 0xD20A8C
+
+#define mmNIC1_QM0_ARB_MST_AVAIL_CRED_28 0xD20A90
+
+#define mmNIC1_QM0_ARB_MST_AVAIL_CRED_29 0xD20A94
+
+#define mmNIC1_QM0_ARB_MST_AVAIL_CRED_30 0xD20A98
+
+#define mmNIC1_QM0_ARB_MST_AVAIL_CRED_31 0xD20A9C
+
+#define mmNIC1_QM0_ARB_MST_CRED_INC 0xD20AA0
+
+#define mmNIC1_QM0_ARB_MST_CHOISE_PUSH_OFST_0 0xD20AA4
+
+#define mmNIC1_QM0_ARB_MST_CHOISE_PUSH_OFST_1 0xD20AA8
+
+#define mmNIC1_QM0_ARB_MST_CHOISE_PUSH_OFST_2 0xD20AAC
+
+#define mmNIC1_QM0_ARB_MST_CHOISE_PUSH_OFST_3 0xD20AB0
+
+#define mmNIC1_QM0_ARB_MST_CHOISE_PUSH_OFST_4 0xD20AB4
+
+#define mmNIC1_QM0_ARB_MST_CHOISE_PUSH_OFST_5 0xD20AB8
+
+#define mmNIC1_QM0_ARB_MST_CHOISE_PUSH_OFST_6 0xD20ABC
+
+#define mmNIC1_QM0_ARB_MST_CHOISE_PUSH_OFST_7 0xD20AC0
+
+#define mmNIC1_QM0_ARB_MST_CHOISE_PUSH_OFST_8 0xD20AC4
+
+#define mmNIC1_QM0_ARB_MST_CHOISE_PUSH_OFST_9 0xD20AC8
+
+#define mmNIC1_QM0_ARB_MST_CHOISE_PUSH_OFST_10 0xD20ACC
+
+#define mmNIC1_QM0_ARB_MST_CHOISE_PUSH_OFST_11 0xD20AD0
+
+#define mmNIC1_QM0_ARB_MST_CHOISE_PUSH_OFST_12 0xD20AD4
+
+#define mmNIC1_QM0_ARB_MST_CHOISE_PUSH_OFST_13 0xD20AD8
+
+#define mmNIC1_QM0_ARB_MST_CHOISE_PUSH_OFST_14 0xD20ADC
+
+#define mmNIC1_QM0_ARB_MST_CHOISE_PUSH_OFST_15 0xD20AE0
+
+#define mmNIC1_QM0_ARB_MST_CHOISE_PUSH_OFST_16 0xD20AE4
+
+#define mmNIC1_QM0_ARB_MST_CHOISE_PUSH_OFST_17 0xD20AE8
+
+#define mmNIC1_QM0_ARB_MST_CHOISE_PUSH_OFST_18 0xD20AEC
+
+#define mmNIC1_QM0_ARB_MST_CHOISE_PUSH_OFST_19 0xD20AF0
+
+#define mmNIC1_QM0_ARB_MST_CHOISE_PUSH_OFST_20 0xD20AF4
+
+#define mmNIC1_QM0_ARB_MST_CHOISE_PUSH_OFST_21 0xD20AF8
+
+#define mmNIC1_QM0_ARB_MST_CHOISE_PUSH_OFST_22 0xD20AFC
+
+#define mmNIC1_QM0_ARB_MST_CHOISE_PUSH_OFST_23 0xD20B00
+
+#define mmNIC1_QM0_ARB_MST_CHOISE_PUSH_OFST_24 0xD20B04
+
+#define mmNIC1_QM0_ARB_MST_CHOISE_PUSH_OFST_25 0xD20B08
+
+#define mmNIC1_QM0_ARB_MST_CHOISE_PUSH_OFST_26 0xD20B0C
+
+#define mmNIC1_QM0_ARB_MST_CHOISE_PUSH_OFST_27 0xD20B10
+
+#define mmNIC1_QM0_ARB_MST_CHOISE_PUSH_OFST_28 0xD20B14
+
+#define mmNIC1_QM0_ARB_MST_CHOISE_PUSH_OFST_29 0xD20B18
+
+#define mmNIC1_QM0_ARB_MST_CHOISE_PUSH_OFST_30 0xD20B1C
+
+#define mmNIC1_QM0_ARB_MST_CHOISE_PUSH_OFST_31 0xD20B20
+
+#define mmNIC1_QM0_ARB_SLV_MASTER_INC_CRED_OFST 0xD20B28
+
+#define mmNIC1_QM0_ARB_MST_SLAVE_EN 0xD20B2C
+
+#define mmNIC1_QM0_ARB_MST_QUIET_PER 0xD20B34
+
+#define mmNIC1_QM0_ARB_SLV_CHOISE_WDT 0xD20B38
+
+#define mmNIC1_QM0_ARB_SLV_ID 0xD20B3C
+
+#define mmNIC1_QM0_ARB_MSG_MAX_INFLIGHT 0xD20B44
+
+#define mmNIC1_QM0_ARB_MSG_AWUSER_31_11 0xD20B48
+
+#define mmNIC1_QM0_ARB_MSG_AWUSER_SEC_PROP 0xD20B4C
+
+#define mmNIC1_QM0_ARB_MSG_AWUSER_NON_SEC_PROP 0xD20B50
+
+#define mmNIC1_QM0_ARB_BASE_LO 0xD20B54
+
+#define mmNIC1_QM0_ARB_BASE_HI 0xD20B58
+
+#define mmNIC1_QM0_ARB_STATE_STS 0xD20B80
+
+#define mmNIC1_QM0_ARB_CHOISE_FULLNESS_STS 0xD20B84
+
+#define mmNIC1_QM0_ARB_MSG_STS 0xD20B88
+
+#define mmNIC1_QM0_ARB_SLV_CHOISE_Q_HEAD 0xD20B8C
+
+#define mmNIC1_QM0_ARB_ERR_CAUSE 0xD20B9C
+
+#define mmNIC1_QM0_ARB_ERR_MSG_EN 0xD20BA0
+
+#define mmNIC1_QM0_ARB_ERR_STS_DRP 0xD20BA8
+
+#define mmNIC1_QM0_ARB_MST_CRED_STS_0 0xD20BB0
+
+#define mmNIC1_QM0_ARB_MST_CRED_STS_1 0xD20BB4
+
+#define mmNIC1_QM0_ARB_MST_CRED_STS_2 0xD20BB8
+
+#define mmNIC1_QM0_ARB_MST_CRED_STS_3 0xD20BBC
+
+#define mmNIC1_QM0_ARB_MST_CRED_STS_4 0xD20BC0
+
+#define mmNIC1_QM0_ARB_MST_CRED_STS_5 0xD20BC4
+
+#define mmNIC1_QM0_ARB_MST_CRED_STS_6 0xD20BC8
+
+#define mmNIC1_QM0_ARB_MST_CRED_STS_7 0xD20BCC
+
+#define mmNIC1_QM0_ARB_MST_CRED_STS_8 0xD20BD0
+
+#define mmNIC1_QM0_ARB_MST_CRED_STS_9 0xD20BD4
+
+#define mmNIC1_QM0_ARB_MST_CRED_STS_10 0xD20BD8
+
+#define mmNIC1_QM0_ARB_MST_CRED_STS_11 0xD20BDC
+
+#define mmNIC1_QM0_ARB_MST_CRED_STS_12 0xD20BE0
+
+#define mmNIC1_QM0_ARB_MST_CRED_STS_13 0xD20BE4
+
+#define mmNIC1_QM0_ARB_MST_CRED_STS_14 0xD20BE8
+
+#define mmNIC1_QM0_ARB_MST_CRED_STS_15 0xD20BEC
+
+#define mmNIC1_QM0_ARB_MST_CRED_STS_16 0xD20BF0
+
+#define mmNIC1_QM0_ARB_MST_CRED_STS_17 0xD20BF4
+
+#define mmNIC1_QM0_ARB_MST_CRED_STS_18 0xD20BF8
+
+#define mmNIC1_QM0_ARB_MST_CRED_STS_19 0xD20BFC
+
+#define mmNIC1_QM0_ARB_MST_CRED_STS_20 0xD20C00
+
+#define mmNIC1_QM0_ARB_MST_CRED_STS_21 0xD20C04
+
+#define mmNIC1_QM0_ARB_MST_CRED_STS_22 0xD20C08
+
+#define mmNIC1_QM0_ARB_MST_CRED_STS_23 0xD20C0C
+
+#define mmNIC1_QM0_ARB_MST_CRED_STS_24 0xD20C10
+
+#define mmNIC1_QM0_ARB_MST_CRED_STS_25 0xD20C14
+
+#define mmNIC1_QM0_ARB_MST_CRED_STS_26 0xD20C18
+
+#define mmNIC1_QM0_ARB_MST_CRED_STS_27 0xD20C1C
+
+#define mmNIC1_QM0_ARB_MST_CRED_STS_28 0xD20C20
+
+#define mmNIC1_QM0_ARB_MST_CRED_STS_29 0xD20C24
+
+#define mmNIC1_QM0_ARB_MST_CRED_STS_30 0xD20C28
+
+#define mmNIC1_QM0_ARB_MST_CRED_STS_31 0xD20C2C
+
+#define mmNIC1_QM0_CGM_CFG 0xD20C70
+
+#define mmNIC1_QM0_CGM_STS 0xD20C74
+
+#define mmNIC1_QM0_CGM_CFG1 0xD20C78
+
+#define mmNIC1_QM0_LOCAL_RANGE_BASE 0xD20C80
+
+#define mmNIC1_QM0_LOCAL_RANGE_SIZE 0xD20C84
+
+#define mmNIC1_QM0_CSMR_STRICT_PRIO_CFG 0xD20C90
+
+#define mmNIC1_QM0_HBW_RD_RATE_LIM_CFG_1 0xD20C94
+
+#define mmNIC1_QM0_LBW_WR_RATE_LIM_CFG_0 0xD20C98
+
+#define mmNIC1_QM0_LBW_WR_RATE_LIM_CFG_1 0xD20C9C
+
+#define mmNIC1_QM0_HBW_RD_RATE_LIM_CFG_0 0xD20CA0
+
+#define mmNIC1_QM0_GLBL_AXCACHE 0xD20CA4
+
+#define mmNIC1_QM0_IND_GW_APB_CFG 0xD20CB0
+
+#define mmNIC1_QM0_IND_GW_APB_WDATA 0xD20CB4
+
+#define mmNIC1_QM0_IND_GW_APB_RDATA 0xD20CB8
+
+#define mmNIC1_QM0_IND_GW_APB_STATUS 0xD20CBC
+
+#define mmNIC1_QM0_GLBL_ERR_ADDR_LO 0xD20CD0
+
+#define mmNIC1_QM0_GLBL_ERR_ADDR_HI 0xD20CD4
+
+#define mmNIC1_QM0_GLBL_ERR_WDATA 0xD20CD8
+
+#define mmNIC1_QM0_GLBL_MEM_INIT_BUSY 0xD20D00
+
+#endif /* ASIC_REG_NIC1_QM0_REGS_H_ */
diff --git a/drivers/accel/habanalabs/include/gaudi/asic_reg/nic1_qm1_regs.h b/drivers/accel/habanalabs/include/gaudi/asic_reg/nic1_qm1_regs.h
new file mode 100644
index 0000000000..1b115ee6d6
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi/asic_reg/nic1_qm1_regs.h
@@ -0,0 +1,834 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2016-2018 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ ** DO NOT EDIT BELOW **
+ ************************************/
+
+#ifndef ASIC_REG_NIC1_QM1_REGS_H_
+#define ASIC_REG_NIC1_QM1_REGS_H_
+
+/*
+ *****************************************
+ * NIC1_QM1 (Prototype: QMAN)
+ *****************************************
+ */
+
+#define mmNIC1_QM1_GLBL_CFG0 0xD22000
+
+#define mmNIC1_QM1_GLBL_CFG1 0xD22004
+
+#define mmNIC1_QM1_GLBL_PROT 0xD22008
+
+#define mmNIC1_QM1_GLBL_ERR_CFG 0xD2200C
+
+#define mmNIC1_QM1_GLBL_SECURE_PROPS_0 0xD22010
+
+#define mmNIC1_QM1_GLBL_SECURE_PROPS_1 0xD22014
+
+#define mmNIC1_QM1_GLBL_SECURE_PROPS_2 0xD22018
+
+#define mmNIC1_QM1_GLBL_SECURE_PROPS_3 0xD2201C
+
+#define mmNIC1_QM1_GLBL_SECURE_PROPS_4 0xD22020
+
+#define mmNIC1_QM1_GLBL_NON_SECURE_PROPS_0 0xD22024
+
+#define mmNIC1_QM1_GLBL_NON_SECURE_PROPS_1 0xD22028
+
+#define mmNIC1_QM1_GLBL_NON_SECURE_PROPS_2 0xD2202C
+
+#define mmNIC1_QM1_GLBL_NON_SECURE_PROPS_3 0xD22030
+
+#define mmNIC1_QM1_GLBL_NON_SECURE_PROPS_4 0xD22034
+
+#define mmNIC1_QM1_GLBL_STS0 0xD22038
+
+#define mmNIC1_QM1_GLBL_STS1_0 0xD22040
+
+#define mmNIC1_QM1_GLBL_STS1_1 0xD22044
+
+#define mmNIC1_QM1_GLBL_STS1_2 0xD22048
+
+#define mmNIC1_QM1_GLBL_STS1_3 0xD2204C
+
+#define mmNIC1_QM1_GLBL_STS1_4 0xD22050
+
+#define mmNIC1_QM1_GLBL_MSG_EN_0 0xD22054
+
+#define mmNIC1_QM1_GLBL_MSG_EN_1 0xD22058
+
+#define mmNIC1_QM1_GLBL_MSG_EN_2 0xD2205C
+
+#define mmNIC1_QM1_GLBL_MSG_EN_3 0xD22060
+
+#define mmNIC1_QM1_GLBL_MSG_EN_4 0xD22068
+
+#define mmNIC1_QM1_PQ_BASE_LO_0 0xD22070
+
+#define mmNIC1_QM1_PQ_BASE_LO_1 0xD22074
+
+#define mmNIC1_QM1_PQ_BASE_LO_2 0xD22078
+
+#define mmNIC1_QM1_PQ_BASE_LO_3 0xD2207C
+
+#define mmNIC1_QM1_PQ_BASE_HI_0 0xD22080
+
+#define mmNIC1_QM1_PQ_BASE_HI_1 0xD22084
+
+#define mmNIC1_QM1_PQ_BASE_HI_2 0xD22088
+
+#define mmNIC1_QM1_PQ_BASE_HI_3 0xD2208C
+
+#define mmNIC1_QM1_PQ_SIZE_0 0xD22090
+
+#define mmNIC1_QM1_PQ_SIZE_1 0xD22094
+
+#define mmNIC1_QM1_PQ_SIZE_2 0xD22098
+
+#define mmNIC1_QM1_PQ_SIZE_3 0xD2209C
+
+#define mmNIC1_QM1_PQ_PI_0 0xD220A0
+
+#define mmNIC1_QM1_PQ_PI_1 0xD220A4
+
+#define mmNIC1_QM1_PQ_PI_2 0xD220A8
+
+#define mmNIC1_QM1_PQ_PI_3 0xD220AC
+
+#define mmNIC1_QM1_PQ_CI_0 0xD220B0
+
+#define mmNIC1_QM1_PQ_CI_1 0xD220B4
+
+#define mmNIC1_QM1_PQ_CI_2 0xD220B8
+
+#define mmNIC1_QM1_PQ_CI_3 0xD220BC
+
+#define mmNIC1_QM1_PQ_CFG0_0 0xD220C0
+
+#define mmNIC1_QM1_PQ_CFG0_1 0xD220C4
+
+#define mmNIC1_QM1_PQ_CFG0_2 0xD220C8
+
+#define mmNIC1_QM1_PQ_CFG0_3 0xD220CC
+
+#define mmNIC1_QM1_PQ_CFG1_0 0xD220D0
+
+#define mmNIC1_QM1_PQ_CFG1_1 0xD220D4
+
+#define mmNIC1_QM1_PQ_CFG1_2 0xD220D8
+
+#define mmNIC1_QM1_PQ_CFG1_3 0xD220DC
+
+#define mmNIC1_QM1_PQ_ARUSER_31_11_0 0xD220E0
+
+#define mmNIC1_QM1_PQ_ARUSER_31_11_1 0xD220E4
+
+#define mmNIC1_QM1_PQ_ARUSER_31_11_2 0xD220E8
+
+#define mmNIC1_QM1_PQ_ARUSER_31_11_3 0xD220EC
+
+#define mmNIC1_QM1_PQ_STS0_0 0xD220F0
+
+#define mmNIC1_QM1_PQ_STS0_1 0xD220F4
+
+#define mmNIC1_QM1_PQ_STS0_2 0xD220F8
+
+#define mmNIC1_QM1_PQ_STS0_3 0xD220FC
+
+#define mmNIC1_QM1_PQ_STS1_0 0xD22100
+
+#define mmNIC1_QM1_PQ_STS1_1 0xD22104
+
+#define mmNIC1_QM1_PQ_STS1_2 0xD22108
+
+#define mmNIC1_QM1_PQ_STS1_3 0xD2210C
+
+#define mmNIC1_QM1_CQ_CFG0_0 0xD22110
+
+#define mmNIC1_QM1_CQ_CFG0_1 0xD22114
+
+#define mmNIC1_QM1_CQ_CFG0_2 0xD22118
+
+#define mmNIC1_QM1_CQ_CFG0_3 0xD2211C
+
+#define mmNIC1_QM1_CQ_CFG0_4 0xD22120
+
+#define mmNIC1_QM1_CQ_CFG1_0 0xD22124
+
+#define mmNIC1_QM1_CQ_CFG1_1 0xD22128
+
+#define mmNIC1_QM1_CQ_CFG1_2 0xD2212C
+
+#define mmNIC1_QM1_CQ_CFG1_3 0xD22130
+
+#define mmNIC1_QM1_CQ_CFG1_4 0xD22134
+
+#define mmNIC1_QM1_CQ_ARUSER_31_11_0 0xD22138
+
+#define mmNIC1_QM1_CQ_ARUSER_31_11_1 0xD2213C
+
+#define mmNIC1_QM1_CQ_ARUSER_31_11_2 0xD22140
+
+#define mmNIC1_QM1_CQ_ARUSER_31_11_3 0xD22144
+
+#define mmNIC1_QM1_CQ_ARUSER_31_11_4 0xD22148
+
+#define mmNIC1_QM1_CQ_STS0_0 0xD2214C
+
+#define mmNIC1_QM1_CQ_STS0_1 0xD22150
+
+#define mmNIC1_QM1_CQ_STS0_2 0xD22154
+
+#define mmNIC1_QM1_CQ_STS0_3 0xD22158
+
+#define mmNIC1_QM1_CQ_STS0_4 0xD2215C
+
+#define mmNIC1_QM1_CQ_STS1_0 0xD22160
+
+#define mmNIC1_QM1_CQ_STS1_1 0xD22164
+
+#define mmNIC1_QM1_CQ_STS1_2 0xD22168
+
+#define mmNIC1_QM1_CQ_STS1_3 0xD2216C
+
+#define mmNIC1_QM1_CQ_STS1_4 0xD22170
+
+#define mmNIC1_QM1_CQ_PTR_LO_0 0xD22174
+
+#define mmNIC1_QM1_CQ_PTR_HI_0 0xD22178
+
+#define mmNIC1_QM1_CQ_TSIZE_0 0xD2217C
+
+#define mmNIC1_QM1_CQ_CTL_0 0xD22180
+
+#define mmNIC1_QM1_CQ_PTR_LO_1 0xD22184
+
+#define mmNIC1_QM1_CQ_PTR_HI_1 0xD22188
+
+#define mmNIC1_QM1_CQ_TSIZE_1 0xD2218C
+
+#define mmNIC1_QM1_CQ_CTL_1 0xD22190
+
+#define mmNIC1_QM1_CQ_PTR_LO_2 0xD22194
+
+#define mmNIC1_QM1_CQ_PTR_HI_2 0xD22198
+
+#define mmNIC1_QM1_CQ_TSIZE_2 0xD2219C
+
+#define mmNIC1_QM1_CQ_CTL_2 0xD221A0
+
+#define mmNIC1_QM1_CQ_PTR_LO_3 0xD221A4
+
+#define mmNIC1_QM1_CQ_PTR_HI_3 0xD221A8
+
+#define mmNIC1_QM1_CQ_TSIZE_3 0xD221AC
+
+#define mmNIC1_QM1_CQ_CTL_3 0xD221B0
+
+#define mmNIC1_QM1_CQ_PTR_LO_4 0xD221B4
+
+#define mmNIC1_QM1_CQ_PTR_HI_4 0xD221B8
+
+#define mmNIC1_QM1_CQ_TSIZE_4 0xD221BC
+
+#define mmNIC1_QM1_CQ_CTL_4 0xD221C0
+
+#define mmNIC1_QM1_CQ_PTR_LO_STS_0 0xD221C4
+
+#define mmNIC1_QM1_CQ_PTR_LO_STS_1 0xD221C8
+
+#define mmNIC1_QM1_CQ_PTR_LO_STS_2 0xD221CC
+
+#define mmNIC1_QM1_CQ_PTR_LO_STS_3 0xD221D0
+
+#define mmNIC1_QM1_CQ_PTR_LO_STS_4 0xD221D4
+
+#define mmNIC1_QM1_CQ_PTR_HI_STS_0 0xD221D8
+
+#define mmNIC1_QM1_CQ_PTR_HI_STS_1 0xD221DC
+
+#define mmNIC1_QM1_CQ_PTR_HI_STS_2 0xD221E0
+
+#define mmNIC1_QM1_CQ_PTR_HI_STS_3 0xD221E4
+
+#define mmNIC1_QM1_CQ_PTR_HI_STS_4 0xD221E8
+
+#define mmNIC1_QM1_CQ_TSIZE_STS_0 0xD221EC
+
+#define mmNIC1_QM1_CQ_TSIZE_STS_1 0xD221F0
+
+#define mmNIC1_QM1_CQ_TSIZE_STS_2 0xD221F4
+
+#define mmNIC1_QM1_CQ_TSIZE_STS_3 0xD221F8
+
+#define mmNIC1_QM1_CQ_TSIZE_STS_4 0xD221FC
+
+#define mmNIC1_QM1_CQ_CTL_STS_0 0xD22200
+
+#define mmNIC1_QM1_CQ_CTL_STS_1 0xD22204
+
+#define mmNIC1_QM1_CQ_CTL_STS_2 0xD22208
+
+#define mmNIC1_QM1_CQ_CTL_STS_3 0xD2220C
+
+#define mmNIC1_QM1_CQ_CTL_STS_4 0xD22210
+
+#define mmNIC1_QM1_CQ_IFIFO_CNT_0 0xD22214
+
+#define mmNIC1_QM1_CQ_IFIFO_CNT_1 0xD22218
+
+#define mmNIC1_QM1_CQ_IFIFO_CNT_2 0xD2221C
+
+#define mmNIC1_QM1_CQ_IFIFO_CNT_3 0xD22220
+
+#define mmNIC1_QM1_CQ_IFIFO_CNT_4 0xD22224
+
+#define mmNIC1_QM1_CP_MSG_BASE0_ADDR_LO_0 0xD22228
+
+#define mmNIC1_QM1_CP_MSG_BASE0_ADDR_LO_1 0xD2222C
+
+#define mmNIC1_QM1_CP_MSG_BASE0_ADDR_LO_2 0xD22230
+
+#define mmNIC1_QM1_CP_MSG_BASE0_ADDR_LO_3 0xD22234
+
+#define mmNIC1_QM1_CP_MSG_BASE0_ADDR_LO_4 0xD22238
+
+#define mmNIC1_QM1_CP_MSG_BASE0_ADDR_HI_0 0xD2223C
+
+#define mmNIC1_QM1_CP_MSG_BASE0_ADDR_HI_1 0xD22240
+
+#define mmNIC1_QM1_CP_MSG_BASE0_ADDR_HI_2 0xD22244
+
+#define mmNIC1_QM1_CP_MSG_BASE0_ADDR_HI_3 0xD22248
+
+#define mmNIC1_QM1_CP_MSG_BASE0_ADDR_HI_4 0xD2224C
+
+#define mmNIC1_QM1_CP_MSG_BASE1_ADDR_LO_0 0xD22250
+
+#define mmNIC1_QM1_CP_MSG_BASE1_ADDR_LO_1 0xD22254
+
+#define mmNIC1_QM1_CP_MSG_BASE1_ADDR_LO_2 0xD22258
+
+#define mmNIC1_QM1_CP_MSG_BASE1_ADDR_LO_3 0xD2225C
+
+#define mmNIC1_QM1_CP_MSG_BASE1_ADDR_LO_4 0xD22260
+
+#define mmNIC1_QM1_CP_MSG_BASE1_ADDR_HI_0 0xD22264
+
+#define mmNIC1_QM1_CP_MSG_BASE1_ADDR_HI_1 0xD22268
+
+#define mmNIC1_QM1_CP_MSG_BASE1_ADDR_HI_2 0xD2226C
+
+#define mmNIC1_QM1_CP_MSG_BASE1_ADDR_HI_3 0xD22270
+
+#define mmNIC1_QM1_CP_MSG_BASE1_ADDR_HI_4 0xD22274
+
+#define mmNIC1_QM1_CP_MSG_BASE2_ADDR_LO_0 0xD22278
+
+#define mmNIC1_QM1_CP_MSG_BASE2_ADDR_LO_1 0xD2227C
+
+#define mmNIC1_QM1_CP_MSG_BASE2_ADDR_LO_2 0xD22280
+
+#define mmNIC1_QM1_CP_MSG_BASE2_ADDR_LO_3 0xD22284
+
+#define mmNIC1_QM1_CP_MSG_BASE2_ADDR_LO_4 0xD22288
+
+#define mmNIC1_QM1_CP_MSG_BASE2_ADDR_HI_0 0xD2228C
+
+#define mmNIC1_QM1_CP_MSG_BASE2_ADDR_HI_1 0xD22290
+
+#define mmNIC1_QM1_CP_MSG_BASE2_ADDR_HI_2 0xD22294
+
+#define mmNIC1_QM1_CP_MSG_BASE2_ADDR_HI_3 0xD22298
+
+#define mmNIC1_QM1_CP_MSG_BASE2_ADDR_HI_4 0xD2229C
+
+#define mmNIC1_QM1_CP_MSG_BASE3_ADDR_LO_0 0xD222A0
+
+#define mmNIC1_QM1_CP_MSG_BASE3_ADDR_LO_1 0xD222A4
+
+#define mmNIC1_QM1_CP_MSG_BASE3_ADDR_LO_2 0xD222A8
+
+#define mmNIC1_QM1_CP_MSG_BASE3_ADDR_LO_3 0xD222AC
+
+#define mmNIC1_QM1_CP_MSG_BASE3_ADDR_LO_4 0xD222B0
+
+#define mmNIC1_QM1_CP_MSG_BASE3_ADDR_HI_0 0xD222B4
+
+#define mmNIC1_QM1_CP_MSG_BASE3_ADDR_HI_1 0xD222B8
+
+#define mmNIC1_QM1_CP_MSG_BASE3_ADDR_HI_2 0xD222BC
+
+#define mmNIC1_QM1_CP_MSG_BASE3_ADDR_HI_3 0xD222C0
+
+#define mmNIC1_QM1_CP_MSG_BASE3_ADDR_HI_4 0xD222C4
+
+#define mmNIC1_QM1_CP_LDMA_TSIZE_OFFSET_0 0xD222C8
+
+#define mmNIC1_QM1_CP_LDMA_TSIZE_OFFSET_1 0xD222CC
+
+#define mmNIC1_QM1_CP_LDMA_TSIZE_OFFSET_2 0xD222D0
+
+#define mmNIC1_QM1_CP_LDMA_TSIZE_OFFSET_3 0xD222D4
+
+#define mmNIC1_QM1_CP_LDMA_TSIZE_OFFSET_4 0xD222D8
+
+#define mmNIC1_QM1_CP_LDMA_SRC_BASE_LO_OFFSET_0 0xD222E0
+
+#define mmNIC1_QM1_CP_LDMA_SRC_BASE_LO_OFFSET_1 0xD222E4
+
+#define mmNIC1_QM1_CP_LDMA_SRC_BASE_LO_OFFSET_2 0xD222E8
+
+#define mmNIC1_QM1_CP_LDMA_SRC_BASE_LO_OFFSET_3 0xD222EC
+
+#define mmNIC1_QM1_CP_LDMA_SRC_BASE_LO_OFFSET_4 0xD222F0
+
+#define mmNIC1_QM1_CP_LDMA_DST_BASE_LO_OFFSET_0 0xD222F4
+
+#define mmNIC1_QM1_CP_LDMA_DST_BASE_LO_OFFSET_1 0xD222F8
+
+#define mmNIC1_QM1_CP_LDMA_DST_BASE_LO_OFFSET_2 0xD222FC
+
+#define mmNIC1_QM1_CP_LDMA_DST_BASE_LO_OFFSET_3 0xD22300
+
+#define mmNIC1_QM1_CP_LDMA_DST_BASE_LO_OFFSET_4 0xD22304
+
+#define mmNIC1_QM1_CP_FENCE0_RDATA_0 0xD22308
+
+#define mmNIC1_QM1_CP_FENCE0_RDATA_1 0xD2230C
+
+#define mmNIC1_QM1_CP_FENCE0_RDATA_2 0xD22310
+
+#define mmNIC1_QM1_CP_FENCE0_RDATA_3 0xD22314
+
+#define mmNIC1_QM1_CP_FENCE0_RDATA_4 0xD22318
+
+#define mmNIC1_QM1_CP_FENCE1_RDATA_0 0xD2231C
+
+#define mmNIC1_QM1_CP_FENCE1_RDATA_1 0xD22320
+
+#define mmNIC1_QM1_CP_FENCE1_RDATA_2 0xD22324
+
+#define mmNIC1_QM1_CP_FENCE1_RDATA_3 0xD22328
+
+#define mmNIC1_QM1_CP_FENCE1_RDATA_4 0xD2232C
+
+#define mmNIC1_QM1_CP_FENCE2_RDATA_0 0xD22330
+
+#define mmNIC1_QM1_CP_FENCE2_RDATA_1 0xD22334
+
+#define mmNIC1_QM1_CP_FENCE2_RDATA_2 0xD22338
+
+#define mmNIC1_QM1_CP_FENCE2_RDATA_3 0xD2233C
+
+#define mmNIC1_QM1_CP_FENCE2_RDATA_4 0xD22340
+
+#define mmNIC1_QM1_CP_FENCE3_RDATA_0 0xD22344
+
+#define mmNIC1_QM1_CP_FENCE3_RDATA_1 0xD22348
+
+#define mmNIC1_QM1_CP_FENCE3_RDATA_2 0xD2234C
+
+#define mmNIC1_QM1_CP_FENCE3_RDATA_3 0xD22350
+
+#define mmNIC1_QM1_CP_FENCE3_RDATA_4 0xD22354
+
+#define mmNIC1_QM1_CP_FENCE0_CNT_0 0xD22358
+
+#define mmNIC1_QM1_CP_FENCE0_CNT_1 0xD2235C
+
+#define mmNIC1_QM1_CP_FENCE0_CNT_2 0xD22360
+
+#define mmNIC1_QM1_CP_FENCE0_CNT_3 0xD22364
+
+#define mmNIC1_QM1_CP_FENCE0_CNT_4 0xD22368
+
+#define mmNIC1_QM1_CP_FENCE1_CNT_0 0xD2236C
+
+#define mmNIC1_QM1_CP_FENCE1_CNT_1 0xD22370
+
+#define mmNIC1_QM1_CP_FENCE1_CNT_2 0xD22374
+
+#define mmNIC1_QM1_CP_FENCE1_CNT_3 0xD22378
+
+#define mmNIC1_QM1_CP_FENCE1_CNT_4 0xD2237C
+
+#define mmNIC1_QM1_CP_FENCE2_CNT_0 0xD22380
+
+#define mmNIC1_QM1_CP_FENCE2_CNT_1 0xD22384
+
+#define mmNIC1_QM1_CP_FENCE2_CNT_2 0xD22388
+
+#define mmNIC1_QM1_CP_FENCE2_CNT_3 0xD2238C
+
+#define mmNIC1_QM1_CP_FENCE2_CNT_4 0xD22390
+
+#define mmNIC1_QM1_CP_FENCE3_CNT_0 0xD22394
+
+#define mmNIC1_QM1_CP_FENCE3_CNT_1 0xD22398
+
+#define mmNIC1_QM1_CP_FENCE3_CNT_2 0xD2239C
+
+#define mmNIC1_QM1_CP_FENCE3_CNT_3 0xD223A0
+
+#define mmNIC1_QM1_CP_FENCE3_CNT_4 0xD223A4
+
+#define mmNIC1_QM1_CP_STS_0 0xD223A8
+
+#define mmNIC1_QM1_CP_STS_1 0xD223AC
+
+#define mmNIC1_QM1_CP_STS_2 0xD223B0
+
+#define mmNIC1_QM1_CP_STS_3 0xD223B4
+
+#define mmNIC1_QM1_CP_STS_4 0xD223B8
+
+#define mmNIC1_QM1_CP_CURRENT_INST_LO_0 0xD223BC
+
+#define mmNIC1_QM1_CP_CURRENT_INST_LO_1 0xD223C0
+
+#define mmNIC1_QM1_CP_CURRENT_INST_LO_2 0xD223C4
+
+#define mmNIC1_QM1_CP_CURRENT_INST_LO_3 0xD223C8
+
+#define mmNIC1_QM1_CP_CURRENT_INST_LO_4 0xD223CC
+
+#define mmNIC1_QM1_CP_CURRENT_INST_HI_0 0xD223D0
+
+#define mmNIC1_QM1_CP_CURRENT_INST_HI_1 0xD223D4
+
+#define mmNIC1_QM1_CP_CURRENT_INST_HI_2 0xD223D8
+
+#define mmNIC1_QM1_CP_CURRENT_INST_HI_3 0xD223DC
+
+#define mmNIC1_QM1_CP_CURRENT_INST_HI_4 0xD223E0
+
+#define mmNIC1_QM1_CP_BARRIER_CFG_0 0xD223F4
+
+#define mmNIC1_QM1_CP_BARRIER_CFG_1 0xD223F8
+
+#define mmNIC1_QM1_CP_BARRIER_CFG_2 0xD223FC
+
+#define mmNIC1_QM1_CP_BARRIER_CFG_3 0xD22400
+
+#define mmNIC1_QM1_CP_BARRIER_CFG_4 0xD22404
+
+#define mmNIC1_QM1_CP_DBG_0_0 0xD22408
+
+#define mmNIC1_QM1_CP_DBG_0_1 0xD2240C
+
+#define mmNIC1_QM1_CP_DBG_0_2 0xD22410
+
+#define mmNIC1_QM1_CP_DBG_0_3 0xD22414
+
+#define mmNIC1_QM1_CP_DBG_0_4 0xD22418
+
+#define mmNIC1_QM1_CP_ARUSER_31_11_0 0xD2241C
+
+#define mmNIC1_QM1_CP_ARUSER_31_11_1 0xD22420
+
+#define mmNIC1_QM1_CP_ARUSER_31_11_2 0xD22424
+
+#define mmNIC1_QM1_CP_ARUSER_31_11_3 0xD22428
+
+#define mmNIC1_QM1_CP_ARUSER_31_11_4 0xD2242C
+
+#define mmNIC1_QM1_CP_AWUSER_31_11_0 0xD22430
+
+#define mmNIC1_QM1_CP_AWUSER_31_11_1 0xD22434
+
+#define mmNIC1_QM1_CP_AWUSER_31_11_2 0xD22438
+
+#define mmNIC1_QM1_CP_AWUSER_31_11_3 0xD2243C
+
+#define mmNIC1_QM1_CP_AWUSER_31_11_4 0xD22440
+
+#define mmNIC1_QM1_ARB_CFG_0 0xD22A00
+
+#define mmNIC1_QM1_ARB_CHOISE_Q_PUSH 0xD22A04
+
+#define mmNIC1_QM1_ARB_WRR_WEIGHT_0 0xD22A08
+
+#define mmNIC1_QM1_ARB_WRR_WEIGHT_1 0xD22A0C
+
+#define mmNIC1_QM1_ARB_WRR_WEIGHT_2 0xD22A10
+
+#define mmNIC1_QM1_ARB_WRR_WEIGHT_3 0xD22A14
+
+#define mmNIC1_QM1_ARB_CFG_1 0xD22A18
+
+#define mmNIC1_QM1_ARB_MST_AVAIL_CRED_0 0xD22A20
+
+#define mmNIC1_QM1_ARB_MST_AVAIL_CRED_1 0xD22A24
+
+#define mmNIC1_QM1_ARB_MST_AVAIL_CRED_2 0xD22A28
+
+#define mmNIC1_QM1_ARB_MST_AVAIL_CRED_3 0xD22A2C
+
+#define mmNIC1_QM1_ARB_MST_AVAIL_CRED_4 0xD22A30
+
+#define mmNIC1_QM1_ARB_MST_AVAIL_CRED_5 0xD22A34
+
+#define mmNIC1_QM1_ARB_MST_AVAIL_CRED_6 0xD22A38
+
+#define mmNIC1_QM1_ARB_MST_AVAIL_CRED_7 0xD22A3C
+
+#define mmNIC1_QM1_ARB_MST_AVAIL_CRED_8 0xD22A40
+
+#define mmNIC1_QM1_ARB_MST_AVAIL_CRED_9 0xD22A44
+
+#define mmNIC1_QM1_ARB_MST_AVAIL_CRED_10 0xD22A48
+
+#define mmNIC1_QM1_ARB_MST_AVAIL_CRED_11 0xD22A4C
+
+#define mmNIC1_QM1_ARB_MST_AVAIL_CRED_12 0xD22A50
+
+#define mmNIC1_QM1_ARB_MST_AVAIL_CRED_13 0xD22A54
+
+#define mmNIC1_QM1_ARB_MST_AVAIL_CRED_14 0xD22A58
+
+#define mmNIC1_QM1_ARB_MST_AVAIL_CRED_15 0xD22A5C
+
+#define mmNIC1_QM1_ARB_MST_AVAIL_CRED_16 0xD22A60
+
+#define mmNIC1_QM1_ARB_MST_AVAIL_CRED_17 0xD22A64
+
+#define mmNIC1_QM1_ARB_MST_AVAIL_CRED_18 0xD22A68
+
+#define mmNIC1_QM1_ARB_MST_AVAIL_CRED_19 0xD22A6C
+
+#define mmNIC1_QM1_ARB_MST_AVAIL_CRED_20 0xD22A70
+
+#define mmNIC1_QM1_ARB_MST_AVAIL_CRED_21 0xD22A74
+
+#define mmNIC1_QM1_ARB_MST_AVAIL_CRED_22 0xD22A78
+
+#define mmNIC1_QM1_ARB_MST_AVAIL_CRED_23 0xD22A7C
+
+#define mmNIC1_QM1_ARB_MST_AVAIL_CRED_24 0xD22A80
+
+#define mmNIC1_QM1_ARB_MST_AVAIL_CRED_25 0xD22A84
+
+#define mmNIC1_QM1_ARB_MST_AVAIL_CRED_26 0xD22A88
+
+#define mmNIC1_QM1_ARB_MST_AVAIL_CRED_27 0xD22A8C
+
+#define mmNIC1_QM1_ARB_MST_AVAIL_CRED_28 0xD22A90
+
+#define mmNIC1_QM1_ARB_MST_AVAIL_CRED_29 0xD22A94
+
+#define mmNIC1_QM1_ARB_MST_AVAIL_CRED_30 0xD22A98
+
+#define mmNIC1_QM1_ARB_MST_AVAIL_CRED_31 0xD22A9C
+
+#define mmNIC1_QM1_ARB_MST_CRED_INC 0xD22AA0
+
+#define mmNIC1_QM1_ARB_MST_CHOISE_PUSH_OFST_0 0xD22AA4
+
+#define mmNIC1_QM1_ARB_MST_CHOISE_PUSH_OFST_1 0xD22AA8
+
+#define mmNIC1_QM1_ARB_MST_CHOISE_PUSH_OFST_2 0xD22AAC
+
+#define mmNIC1_QM1_ARB_MST_CHOISE_PUSH_OFST_3 0xD22AB0
+
+#define mmNIC1_QM1_ARB_MST_CHOISE_PUSH_OFST_4 0xD22AB4
+
+#define mmNIC1_QM1_ARB_MST_CHOISE_PUSH_OFST_5 0xD22AB8
+
+#define mmNIC1_QM1_ARB_MST_CHOISE_PUSH_OFST_6 0xD22ABC
+
+#define mmNIC1_QM1_ARB_MST_CHOISE_PUSH_OFST_7 0xD22AC0
+
+#define mmNIC1_QM1_ARB_MST_CHOISE_PUSH_OFST_8 0xD22AC4
+
+#define mmNIC1_QM1_ARB_MST_CHOISE_PUSH_OFST_9 0xD22AC8
+
+#define mmNIC1_QM1_ARB_MST_CHOISE_PUSH_OFST_10 0xD22ACC
+
+#define mmNIC1_QM1_ARB_MST_CHOISE_PUSH_OFST_11 0xD22AD0
+
+#define mmNIC1_QM1_ARB_MST_CHOISE_PUSH_OFST_12 0xD22AD4
+
+#define mmNIC1_QM1_ARB_MST_CHOISE_PUSH_OFST_13 0xD22AD8
+
+#define mmNIC1_QM1_ARB_MST_CHOISE_PUSH_OFST_14 0xD22ADC
+
+#define mmNIC1_QM1_ARB_MST_CHOISE_PUSH_OFST_15 0xD22AE0
+
+#define mmNIC1_QM1_ARB_MST_CHOISE_PUSH_OFST_16 0xD22AE4
+
+#define mmNIC1_QM1_ARB_MST_CHOISE_PUSH_OFST_17 0xD22AE8
+
+#define mmNIC1_QM1_ARB_MST_CHOISE_PUSH_OFST_18 0xD22AEC
+
+#define mmNIC1_QM1_ARB_MST_CHOISE_PUSH_OFST_19 0xD22AF0
+
+#define mmNIC1_QM1_ARB_MST_CHOISE_PUSH_OFST_20 0xD22AF4
+
+#define mmNIC1_QM1_ARB_MST_CHOISE_PUSH_OFST_21 0xD22AF8
+
+#define mmNIC1_QM1_ARB_MST_CHOISE_PUSH_OFST_22 0xD22AFC
+
+#define mmNIC1_QM1_ARB_MST_CHOISE_PUSH_OFST_23 0xD22B00
+
+#define mmNIC1_QM1_ARB_MST_CHOISE_PUSH_OFST_24 0xD22B04
+
+#define mmNIC1_QM1_ARB_MST_CHOISE_PUSH_OFST_25 0xD22B08
+
+#define mmNIC1_QM1_ARB_MST_CHOISE_PUSH_OFST_26 0xD22B0C
+
+#define mmNIC1_QM1_ARB_MST_CHOISE_PUSH_OFST_27 0xD22B10
+
+#define mmNIC1_QM1_ARB_MST_CHOISE_PUSH_OFST_28 0xD22B14
+
+#define mmNIC1_QM1_ARB_MST_CHOISE_PUSH_OFST_29 0xD22B18
+
+#define mmNIC1_QM1_ARB_MST_CHOISE_PUSH_OFST_30 0xD22B1C
+
+#define mmNIC1_QM1_ARB_MST_CHOISE_PUSH_OFST_31 0xD22B20
+
+#define mmNIC1_QM1_ARB_SLV_MASTER_INC_CRED_OFST 0xD22B28
+
+#define mmNIC1_QM1_ARB_MST_SLAVE_EN 0xD22B2C
+
+#define mmNIC1_QM1_ARB_MST_QUIET_PER 0xD22B34
+
+#define mmNIC1_QM1_ARB_SLV_CHOISE_WDT 0xD22B38
+
+#define mmNIC1_QM1_ARB_SLV_ID 0xD22B3C
+
+#define mmNIC1_QM1_ARB_MSG_MAX_INFLIGHT 0xD22B44
+
+#define mmNIC1_QM1_ARB_MSG_AWUSER_31_11 0xD22B48
+
+#define mmNIC1_QM1_ARB_MSG_AWUSER_SEC_PROP 0xD22B4C
+
+#define mmNIC1_QM1_ARB_MSG_AWUSER_NON_SEC_PROP 0xD22B50
+
+#define mmNIC1_QM1_ARB_BASE_LO 0xD22B54
+
+#define mmNIC1_QM1_ARB_BASE_HI 0xD22B58
+
+#define mmNIC1_QM1_ARB_STATE_STS 0xD22B80
+
+#define mmNIC1_QM1_ARB_CHOISE_FULLNESS_STS 0xD22B84
+
+#define mmNIC1_QM1_ARB_MSG_STS 0xD22B88
+
+#define mmNIC1_QM1_ARB_SLV_CHOISE_Q_HEAD 0xD22B8C
+
+#define mmNIC1_QM1_ARB_ERR_CAUSE 0xD22B9C
+
+#define mmNIC1_QM1_ARB_ERR_MSG_EN 0xD22BA0
+
+#define mmNIC1_QM1_ARB_ERR_STS_DRP 0xD22BA8
+
+#define mmNIC1_QM1_ARB_MST_CRED_STS_0 0xD22BB0
+
+#define mmNIC1_QM1_ARB_MST_CRED_STS_1 0xD22BB4
+
+#define mmNIC1_QM1_ARB_MST_CRED_STS_2 0xD22BB8
+
+#define mmNIC1_QM1_ARB_MST_CRED_STS_3 0xD22BBC
+
+#define mmNIC1_QM1_ARB_MST_CRED_STS_4 0xD22BC0
+
+#define mmNIC1_QM1_ARB_MST_CRED_STS_5 0xD22BC4
+
+#define mmNIC1_QM1_ARB_MST_CRED_STS_6 0xD22BC8
+
+#define mmNIC1_QM1_ARB_MST_CRED_STS_7 0xD22BCC
+
+#define mmNIC1_QM1_ARB_MST_CRED_STS_8 0xD22BD0
+
+#define mmNIC1_QM1_ARB_MST_CRED_STS_9 0xD22BD4
+
+#define mmNIC1_QM1_ARB_MST_CRED_STS_10 0xD22BD8
+
+#define mmNIC1_QM1_ARB_MST_CRED_STS_11 0xD22BDC
+
+#define mmNIC1_QM1_ARB_MST_CRED_STS_12 0xD22BE0
+
+#define mmNIC1_QM1_ARB_MST_CRED_STS_13 0xD22BE4
+
+#define mmNIC1_QM1_ARB_MST_CRED_STS_14 0xD22BE8
+
+#define mmNIC1_QM1_ARB_MST_CRED_STS_15 0xD22BEC
+
+#define mmNIC1_QM1_ARB_MST_CRED_STS_16 0xD22BF0
+
+#define mmNIC1_QM1_ARB_MST_CRED_STS_17 0xD22BF4
+
+#define mmNIC1_QM1_ARB_MST_CRED_STS_18 0xD22BF8
+
+#define mmNIC1_QM1_ARB_MST_CRED_STS_19 0xD22BFC
+
+#define mmNIC1_QM1_ARB_MST_CRED_STS_20 0xD22C00
+
+#define mmNIC1_QM1_ARB_MST_CRED_STS_21 0xD22C04
+
+#define mmNIC1_QM1_ARB_MST_CRED_STS_22 0xD22C08
+
+#define mmNIC1_QM1_ARB_MST_CRED_STS_23 0xD22C0C
+
+#define mmNIC1_QM1_ARB_MST_CRED_STS_24 0xD22C10
+
+#define mmNIC1_QM1_ARB_MST_CRED_STS_25 0xD22C14
+
+#define mmNIC1_QM1_ARB_MST_CRED_STS_26 0xD22C18
+
+#define mmNIC1_QM1_ARB_MST_CRED_STS_27 0xD22C1C
+
+#define mmNIC1_QM1_ARB_MST_CRED_STS_28 0xD22C20
+
+#define mmNIC1_QM1_ARB_MST_CRED_STS_29 0xD22C24
+
+#define mmNIC1_QM1_ARB_MST_CRED_STS_30 0xD22C28
+
+#define mmNIC1_QM1_ARB_MST_CRED_STS_31 0xD22C2C
+
+#define mmNIC1_QM1_CGM_CFG 0xD22C70
+
+#define mmNIC1_QM1_CGM_STS 0xD22C74
+
+#define mmNIC1_QM1_CGM_CFG1 0xD22C78
+
+#define mmNIC1_QM1_LOCAL_RANGE_BASE 0xD22C80
+
+#define mmNIC1_QM1_LOCAL_RANGE_SIZE 0xD22C84
+
+#define mmNIC1_QM1_CSMR_STRICT_PRIO_CFG 0xD22C90
+
+#define mmNIC1_QM1_HBW_RD_RATE_LIM_CFG_1 0xD22C94
+
+#define mmNIC1_QM1_LBW_WR_RATE_LIM_CFG_0 0xD22C98
+
+#define mmNIC1_QM1_LBW_WR_RATE_LIM_CFG_1 0xD22C9C
+
+#define mmNIC1_QM1_HBW_RD_RATE_LIM_CFG_0 0xD22CA0
+
+#define mmNIC1_QM1_GLBL_AXCACHE 0xD22CA4
+
+#define mmNIC1_QM1_IND_GW_APB_CFG 0xD22CB0
+
+#define mmNIC1_QM1_IND_GW_APB_WDATA 0xD22CB4
+
+#define mmNIC1_QM1_IND_GW_APB_RDATA 0xD22CB8
+
+#define mmNIC1_QM1_IND_GW_APB_STATUS 0xD22CBC
+
+#define mmNIC1_QM1_GLBL_ERR_ADDR_LO 0xD22CD0
+
+#define mmNIC1_QM1_GLBL_ERR_ADDR_HI 0xD22CD4
+
+#define mmNIC1_QM1_GLBL_ERR_WDATA 0xD22CD8
+
+#define mmNIC1_QM1_GLBL_MEM_INIT_BUSY 0xD22D00
+
+#endif /* ASIC_REG_NIC1_QM1_REGS_H_ */
diff --git a/drivers/accel/habanalabs/include/gaudi/asic_reg/nic2_qm0_regs.h b/drivers/accel/habanalabs/include/gaudi/asic_reg/nic2_qm0_regs.h
new file mode 100644
index 0000000000..a89116a458
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi/asic_reg/nic2_qm0_regs.h
@@ -0,0 +1,834 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2016-2018 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ ** DO NOT EDIT BELOW **
+ ************************************/
+
+#ifndef ASIC_REG_NIC2_QM0_REGS_H_
+#define ASIC_REG_NIC2_QM0_REGS_H_
+
+/*
+ *****************************************
+ * NIC2_QM0 (Prototype: QMAN)
+ *****************************************
+ */
+
+#define mmNIC2_QM0_GLBL_CFG0 0xD60000
+
+#define mmNIC2_QM0_GLBL_CFG1 0xD60004
+
+#define mmNIC2_QM0_GLBL_PROT 0xD60008
+
+#define mmNIC2_QM0_GLBL_ERR_CFG 0xD6000C
+
+#define mmNIC2_QM0_GLBL_SECURE_PROPS_0 0xD60010
+
+#define mmNIC2_QM0_GLBL_SECURE_PROPS_1 0xD60014
+
+#define mmNIC2_QM0_GLBL_SECURE_PROPS_2 0xD60018
+
+#define mmNIC2_QM0_GLBL_SECURE_PROPS_3 0xD6001C
+
+#define mmNIC2_QM0_GLBL_SECURE_PROPS_4 0xD60020
+
+#define mmNIC2_QM0_GLBL_NON_SECURE_PROPS_0 0xD60024
+
+#define mmNIC2_QM0_GLBL_NON_SECURE_PROPS_1 0xD60028
+
+#define mmNIC2_QM0_GLBL_NON_SECURE_PROPS_2 0xD6002C
+
+#define mmNIC2_QM0_GLBL_NON_SECURE_PROPS_3 0xD60030
+
+#define mmNIC2_QM0_GLBL_NON_SECURE_PROPS_4 0xD60034
+
+#define mmNIC2_QM0_GLBL_STS0 0xD60038
+
+#define mmNIC2_QM0_GLBL_STS1_0 0xD60040
+
+#define mmNIC2_QM0_GLBL_STS1_1 0xD60044
+
+#define mmNIC2_QM0_GLBL_STS1_2 0xD60048
+
+#define mmNIC2_QM0_GLBL_STS1_3 0xD6004C
+
+#define mmNIC2_QM0_GLBL_STS1_4 0xD60050
+
+#define mmNIC2_QM0_GLBL_MSG_EN_0 0xD60054
+
+#define mmNIC2_QM0_GLBL_MSG_EN_1 0xD60058
+
+#define mmNIC2_QM0_GLBL_MSG_EN_2 0xD6005C
+
+#define mmNIC2_QM0_GLBL_MSG_EN_3 0xD60060
+
+#define mmNIC2_QM0_GLBL_MSG_EN_4 0xD60068
+
+#define mmNIC2_QM0_PQ_BASE_LO_0 0xD60070
+
+#define mmNIC2_QM0_PQ_BASE_LO_1 0xD60074
+
+#define mmNIC2_QM0_PQ_BASE_LO_2 0xD60078
+
+#define mmNIC2_QM0_PQ_BASE_LO_3 0xD6007C
+
+#define mmNIC2_QM0_PQ_BASE_HI_0 0xD60080
+
+#define mmNIC2_QM0_PQ_BASE_HI_1 0xD60084
+
+#define mmNIC2_QM0_PQ_BASE_HI_2 0xD60088
+
+#define mmNIC2_QM0_PQ_BASE_HI_3 0xD6008C
+
+#define mmNIC2_QM0_PQ_SIZE_0 0xD60090
+
+#define mmNIC2_QM0_PQ_SIZE_1 0xD60094
+
+#define mmNIC2_QM0_PQ_SIZE_2 0xD60098
+
+#define mmNIC2_QM0_PQ_SIZE_3 0xD6009C
+
+#define mmNIC2_QM0_PQ_PI_0 0xD600A0
+
+#define mmNIC2_QM0_PQ_PI_1 0xD600A4
+
+#define mmNIC2_QM0_PQ_PI_2 0xD600A8
+
+#define mmNIC2_QM0_PQ_PI_3 0xD600AC
+
+#define mmNIC2_QM0_PQ_CI_0 0xD600B0
+
+#define mmNIC2_QM0_PQ_CI_1 0xD600B4
+
+#define mmNIC2_QM0_PQ_CI_2 0xD600B8
+
+#define mmNIC2_QM0_PQ_CI_3 0xD600BC
+
+#define mmNIC2_QM0_PQ_CFG0_0 0xD600C0
+
+#define mmNIC2_QM0_PQ_CFG0_1 0xD600C4
+
+#define mmNIC2_QM0_PQ_CFG0_2 0xD600C8
+
+#define mmNIC2_QM0_PQ_CFG0_3 0xD600CC
+
+#define mmNIC2_QM0_PQ_CFG1_0 0xD600D0
+
+#define mmNIC2_QM0_PQ_CFG1_1 0xD600D4
+
+#define mmNIC2_QM0_PQ_CFG1_2 0xD600D8
+
+#define mmNIC2_QM0_PQ_CFG1_3 0xD600DC
+
+#define mmNIC2_QM0_PQ_ARUSER_31_11_0 0xD600E0
+
+#define mmNIC2_QM0_PQ_ARUSER_31_11_1 0xD600E4
+
+#define mmNIC2_QM0_PQ_ARUSER_31_11_2 0xD600E8
+
+#define mmNIC2_QM0_PQ_ARUSER_31_11_3 0xD600EC
+
+#define mmNIC2_QM0_PQ_STS0_0 0xD600F0
+
+#define mmNIC2_QM0_PQ_STS0_1 0xD600F4
+
+#define mmNIC2_QM0_PQ_STS0_2 0xD600F8
+
+#define mmNIC2_QM0_PQ_STS0_3 0xD600FC
+
+#define mmNIC2_QM0_PQ_STS1_0 0xD60100
+
+#define mmNIC2_QM0_PQ_STS1_1 0xD60104
+
+#define mmNIC2_QM0_PQ_STS1_2 0xD60108
+
+#define mmNIC2_QM0_PQ_STS1_3 0xD6010C
+
+#define mmNIC2_QM0_CQ_CFG0_0 0xD60110
+
+#define mmNIC2_QM0_CQ_CFG0_1 0xD60114
+
+#define mmNIC2_QM0_CQ_CFG0_2 0xD60118
+
+#define mmNIC2_QM0_CQ_CFG0_3 0xD6011C
+
+#define mmNIC2_QM0_CQ_CFG0_4 0xD60120
+
+#define mmNIC2_QM0_CQ_CFG1_0 0xD60124
+
+#define mmNIC2_QM0_CQ_CFG1_1 0xD60128
+
+#define mmNIC2_QM0_CQ_CFG1_2 0xD6012C
+
+#define mmNIC2_QM0_CQ_CFG1_3 0xD60130
+
+#define mmNIC2_QM0_CQ_CFG1_4 0xD60134
+
+#define mmNIC2_QM0_CQ_ARUSER_31_11_0 0xD60138
+
+#define mmNIC2_QM0_CQ_ARUSER_31_11_1 0xD6013C
+
+#define mmNIC2_QM0_CQ_ARUSER_31_11_2 0xD60140
+
+#define mmNIC2_QM0_CQ_ARUSER_31_11_3 0xD60144
+
+#define mmNIC2_QM0_CQ_ARUSER_31_11_4 0xD60148
+
+#define mmNIC2_QM0_CQ_STS0_0 0xD6014C
+
+#define mmNIC2_QM0_CQ_STS0_1 0xD60150
+
+#define mmNIC2_QM0_CQ_STS0_2 0xD60154
+
+#define mmNIC2_QM0_CQ_STS0_3 0xD60158
+
+#define mmNIC2_QM0_CQ_STS0_4 0xD6015C
+
+#define mmNIC2_QM0_CQ_STS1_0 0xD60160
+
+#define mmNIC2_QM0_CQ_STS1_1 0xD60164
+
+#define mmNIC2_QM0_CQ_STS1_2 0xD60168
+
+#define mmNIC2_QM0_CQ_STS1_3 0xD6016C
+
+#define mmNIC2_QM0_CQ_STS1_4 0xD60170
+
+#define mmNIC2_QM0_CQ_PTR_LO_0 0xD60174
+
+#define mmNIC2_QM0_CQ_PTR_HI_0 0xD60178
+
+#define mmNIC2_QM0_CQ_TSIZE_0 0xD6017C
+
+#define mmNIC2_QM0_CQ_CTL_0 0xD60180
+
+#define mmNIC2_QM0_CQ_PTR_LO_1 0xD60184
+
+#define mmNIC2_QM0_CQ_PTR_HI_1 0xD60188
+
+#define mmNIC2_QM0_CQ_TSIZE_1 0xD6018C
+
+#define mmNIC2_QM0_CQ_CTL_1 0xD60190
+
+#define mmNIC2_QM0_CQ_PTR_LO_2 0xD60194
+
+#define mmNIC2_QM0_CQ_PTR_HI_2 0xD60198
+
+#define mmNIC2_QM0_CQ_TSIZE_2 0xD6019C
+
+#define mmNIC2_QM0_CQ_CTL_2 0xD601A0
+
+#define mmNIC2_QM0_CQ_PTR_LO_3 0xD601A4
+
+#define mmNIC2_QM0_CQ_PTR_HI_3 0xD601A8
+
+#define mmNIC2_QM0_CQ_TSIZE_3 0xD601AC
+
+#define mmNIC2_QM0_CQ_CTL_3 0xD601B0
+
+#define mmNIC2_QM0_CQ_PTR_LO_4 0xD601B4
+
+#define mmNIC2_QM0_CQ_PTR_HI_4 0xD601B8
+
+#define mmNIC2_QM0_CQ_TSIZE_4 0xD601BC
+
+#define mmNIC2_QM0_CQ_CTL_4 0xD601C0
+
+#define mmNIC2_QM0_CQ_PTR_LO_STS_0 0xD601C4
+
+#define mmNIC2_QM0_CQ_PTR_LO_STS_1 0xD601C8
+
+#define mmNIC2_QM0_CQ_PTR_LO_STS_2 0xD601CC
+
+#define mmNIC2_QM0_CQ_PTR_LO_STS_3 0xD601D0
+
+#define mmNIC2_QM0_CQ_PTR_LO_STS_4 0xD601D4
+
+#define mmNIC2_QM0_CQ_PTR_HI_STS_0 0xD601D8
+
+#define mmNIC2_QM0_CQ_PTR_HI_STS_1 0xD601DC
+
+#define mmNIC2_QM0_CQ_PTR_HI_STS_2 0xD601E0
+
+#define mmNIC2_QM0_CQ_PTR_HI_STS_3 0xD601E4
+
+#define mmNIC2_QM0_CQ_PTR_HI_STS_4 0xD601E8
+
+#define mmNIC2_QM0_CQ_TSIZE_STS_0 0xD601EC
+
+#define mmNIC2_QM0_CQ_TSIZE_STS_1 0xD601F0
+
+#define mmNIC2_QM0_CQ_TSIZE_STS_2 0xD601F4
+
+#define mmNIC2_QM0_CQ_TSIZE_STS_3 0xD601F8
+
+#define mmNIC2_QM0_CQ_TSIZE_STS_4 0xD601FC
+
+#define mmNIC2_QM0_CQ_CTL_STS_0 0xD60200
+
+#define mmNIC2_QM0_CQ_CTL_STS_1 0xD60204
+
+#define mmNIC2_QM0_CQ_CTL_STS_2 0xD60208
+
+#define mmNIC2_QM0_CQ_CTL_STS_3 0xD6020C
+
+#define mmNIC2_QM0_CQ_CTL_STS_4 0xD60210
+
+#define mmNIC2_QM0_CQ_IFIFO_CNT_0 0xD60214
+
+#define mmNIC2_QM0_CQ_IFIFO_CNT_1 0xD60218
+
+#define mmNIC2_QM0_CQ_IFIFO_CNT_2 0xD6021C
+
+#define mmNIC2_QM0_CQ_IFIFO_CNT_3 0xD60220
+
+#define mmNIC2_QM0_CQ_IFIFO_CNT_4 0xD60224
+
+#define mmNIC2_QM0_CP_MSG_BASE0_ADDR_LO_0 0xD60228
+
+#define mmNIC2_QM0_CP_MSG_BASE0_ADDR_LO_1 0xD6022C
+
+#define mmNIC2_QM0_CP_MSG_BASE0_ADDR_LO_2 0xD60230
+
+#define mmNIC2_QM0_CP_MSG_BASE0_ADDR_LO_3 0xD60234
+
+#define mmNIC2_QM0_CP_MSG_BASE0_ADDR_LO_4 0xD60238
+
+#define mmNIC2_QM0_CP_MSG_BASE0_ADDR_HI_0 0xD6023C
+
+#define mmNIC2_QM0_CP_MSG_BASE0_ADDR_HI_1 0xD60240
+
+#define mmNIC2_QM0_CP_MSG_BASE0_ADDR_HI_2 0xD60244
+
+#define mmNIC2_QM0_CP_MSG_BASE0_ADDR_HI_3 0xD60248
+
+#define mmNIC2_QM0_CP_MSG_BASE0_ADDR_HI_4 0xD6024C
+
+#define mmNIC2_QM0_CP_MSG_BASE1_ADDR_LO_0 0xD60250
+
+#define mmNIC2_QM0_CP_MSG_BASE1_ADDR_LO_1 0xD60254
+
+#define mmNIC2_QM0_CP_MSG_BASE1_ADDR_LO_2 0xD60258
+
+#define mmNIC2_QM0_CP_MSG_BASE1_ADDR_LO_3 0xD6025C
+
+#define mmNIC2_QM0_CP_MSG_BASE1_ADDR_LO_4 0xD60260
+
+#define mmNIC2_QM0_CP_MSG_BASE1_ADDR_HI_0 0xD60264
+
+#define mmNIC2_QM0_CP_MSG_BASE1_ADDR_HI_1 0xD60268
+
+#define mmNIC2_QM0_CP_MSG_BASE1_ADDR_HI_2 0xD6026C
+
+#define mmNIC2_QM0_CP_MSG_BASE1_ADDR_HI_3 0xD60270
+
+#define mmNIC2_QM0_CP_MSG_BASE1_ADDR_HI_4 0xD60274
+
+#define mmNIC2_QM0_CP_MSG_BASE2_ADDR_LO_0 0xD60278
+
+#define mmNIC2_QM0_CP_MSG_BASE2_ADDR_LO_1 0xD6027C
+
+#define mmNIC2_QM0_CP_MSG_BASE2_ADDR_LO_2 0xD60280
+
+#define mmNIC2_QM0_CP_MSG_BASE2_ADDR_LO_3 0xD60284
+
+#define mmNIC2_QM0_CP_MSG_BASE2_ADDR_LO_4 0xD60288
+
+#define mmNIC2_QM0_CP_MSG_BASE2_ADDR_HI_0 0xD6028C
+
+#define mmNIC2_QM0_CP_MSG_BASE2_ADDR_HI_1 0xD60290
+
+#define mmNIC2_QM0_CP_MSG_BASE2_ADDR_HI_2 0xD60294
+
+#define mmNIC2_QM0_CP_MSG_BASE2_ADDR_HI_3 0xD60298
+
+#define mmNIC2_QM0_CP_MSG_BASE2_ADDR_HI_4 0xD6029C
+
+#define mmNIC2_QM0_CP_MSG_BASE3_ADDR_LO_0 0xD602A0
+
+#define mmNIC2_QM0_CP_MSG_BASE3_ADDR_LO_1 0xD602A4
+
+#define mmNIC2_QM0_CP_MSG_BASE3_ADDR_LO_2 0xD602A8
+
+#define mmNIC2_QM0_CP_MSG_BASE3_ADDR_LO_3 0xD602AC
+
+#define mmNIC2_QM0_CP_MSG_BASE3_ADDR_LO_4 0xD602B0
+
+#define mmNIC2_QM0_CP_MSG_BASE3_ADDR_HI_0 0xD602B4
+
+#define mmNIC2_QM0_CP_MSG_BASE3_ADDR_HI_1 0xD602B8
+
+#define mmNIC2_QM0_CP_MSG_BASE3_ADDR_HI_2 0xD602BC
+
+#define mmNIC2_QM0_CP_MSG_BASE3_ADDR_HI_3 0xD602C0
+
+#define mmNIC2_QM0_CP_MSG_BASE3_ADDR_HI_4 0xD602C4
+
+#define mmNIC2_QM0_CP_LDMA_TSIZE_OFFSET_0 0xD602C8
+
+#define mmNIC2_QM0_CP_LDMA_TSIZE_OFFSET_1 0xD602CC
+
+#define mmNIC2_QM0_CP_LDMA_TSIZE_OFFSET_2 0xD602D0
+
+#define mmNIC2_QM0_CP_LDMA_TSIZE_OFFSET_3 0xD602D4
+
+#define mmNIC2_QM0_CP_LDMA_TSIZE_OFFSET_4 0xD602D8
+
+#define mmNIC2_QM0_CP_LDMA_SRC_BASE_LO_OFFSET_0 0xD602E0
+
+#define mmNIC2_QM0_CP_LDMA_SRC_BASE_LO_OFFSET_1 0xD602E4
+
+#define mmNIC2_QM0_CP_LDMA_SRC_BASE_LO_OFFSET_2 0xD602E8
+
+#define mmNIC2_QM0_CP_LDMA_SRC_BASE_LO_OFFSET_3 0xD602EC
+
+#define mmNIC2_QM0_CP_LDMA_SRC_BASE_LO_OFFSET_4 0xD602F0
+
+#define mmNIC2_QM0_CP_LDMA_DST_BASE_LO_OFFSET_0 0xD602F4
+
+#define mmNIC2_QM0_CP_LDMA_DST_BASE_LO_OFFSET_1 0xD602F8
+
+#define mmNIC2_QM0_CP_LDMA_DST_BASE_LO_OFFSET_2 0xD602FC
+
+#define mmNIC2_QM0_CP_LDMA_DST_BASE_LO_OFFSET_3 0xD60300
+
+#define mmNIC2_QM0_CP_LDMA_DST_BASE_LO_OFFSET_4 0xD60304
+
+#define mmNIC2_QM0_CP_FENCE0_RDATA_0 0xD60308
+
+#define mmNIC2_QM0_CP_FENCE0_RDATA_1 0xD6030C
+
+#define mmNIC2_QM0_CP_FENCE0_RDATA_2 0xD60310
+
+#define mmNIC2_QM0_CP_FENCE0_RDATA_3 0xD60314
+
+#define mmNIC2_QM0_CP_FENCE0_RDATA_4 0xD60318
+
+#define mmNIC2_QM0_CP_FENCE1_RDATA_0 0xD6031C
+
+#define mmNIC2_QM0_CP_FENCE1_RDATA_1 0xD60320
+
+#define mmNIC2_QM0_CP_FENCE1_RDATA_2 0xD60324
+
+#define mmNIC2_QM0_CP_FENCE1_RDATA_3 0xD60328
+
+#define mmNIC2_QM0_CP_FENCE1_RDATA_4 0xD6032C
+
+#define mmNIC2_QM0_CP_FENCE2_RDATA_0 0xD60330
+
+#define mmNIC2_QM0_CP_FENCE2_RDATA_1 0xD60334
+
+#define mmNIC2_QM0_CP_FENCE2_RDATA_2 0xD60338
+
+#define mmNIC2_QM0_CP_FENCE2_RDATA_3 0xD6033C
+
+#define mmNIC2_QM0_CP_FENCE2_RDATA_4 0xD60340
+
+#define mmNIC2_QM0_CP_FENCE3_RDATA_0 0xD60344
+
+#define mmNIC2_QM0_CP_FENCE3_RDATA_1 0xD60348
+
+#define mmNIC2_QM0_CP_FENCE3_RDATA_2 0xD6034C
+
+#define mmNIC2_QM0_CP_FENCE3_RDATA_3 0xD60350
+
+#define mmNIC2_QM0_CP_FENCE3_RDATA_4 0xD60354
+
+#define mmNIC2_QM0_CP_FENCE0_CNT_0 0xD60358
+
+#define mmNIC2_QM0_CP_FENCE0_CNT_1 0xD6035C
+
+#define mmNIC2_QM0_CP_FENCE0_CNT_2 0xD60360
+
+#define mmNIC2_QM0_CP_FENCE0_CNT_3 0xD60364
+
+#define mmNIC2_QM0_CP_FENCE0_CNT_4 0xD60368
+
+#define mmNIC2_QM0_CP_FENCE1_CNT_0 0xD6036C
+
+#define mmNIC2_QM0_CP_FENCE1_CNT_1 0xD60370
+
+#define mmNIC2_QM0_CP_FENCE1_CNT_2 0xD60374
+
+#define mmNIC2_QM0_CP_FENCE1_CNT_3 0xD60378
+
+#define mmNIC2_QM0_CP_FENCE1_CNT_4 0xD6037C
+
+#define mmNIC2_QM0_CP_FENCE2_CNT_0 0xD60380
+
+#define mmNIC2_QM0_CP_FENCE2_CNT_1 0xD60384
+
+#define mmNIC2_QM0_CP_FENCE2_CNT_2 0xD60388
+
+#define mmNIC2_QM0_CP_FENCE2_CNT_3 0xD6038C
+
+#define mmNIC2_QM0_CP_FENCE2_CNT_4 0xD60390
+
+#define mmNIC2_QM0_CP_FENCE3_CNT_0 0xD60394
+
+#define mmNIC2_QM0_CP_FENCE3_CNT_1 0xD60398
+
+#define mmNIC2_QM0_CP_FENCE3_CNT_2 0xD6039C
+
+#define mmNIC2_QM0_CP_FENCE3_CNT_3 0xD603A0
+
+#define mmNIC2_QM0_CP_FENCE3_CNT_4 0xD603A4
+
+#define mmNIC2_QM0_CP_STS_0 0xD603A8
+
+#define mmNIC2_QM0_CP_STS_1 0xD603AC
+
+#define mmNIC2_QM0_CP_STS_2 0xD603B0
+
+#define mmNIC2_QM0_CP_STS_3 0xD603B4
+
+#define mmNIC2_QM0_CP_STS_4 0xD603B8
+
+#define mmNIC2_QM0_CP_CURRENT_INST_LO_0 0xD603BC
+
+#define mmNIC2_QM0_CP_CURRENT_INST_LO_1 0xD603C0
+
+#define mmNIC2_QM0_CP_CURRENT_INST_LO_2 0xD603C4
+
+#define mmNIC2_QM0_CP_CURRENT_INST_LO_3 0xD603C8
+
+#define mmNIC2_QM0_CP_CURRENT_INST_LO_4 0xD603CC
+
+#define mmNIC2_QM0_CP_CURRENT_INST_HI_0 0xD603D0
+
+#define mmNIC2_QM0_CP_CURRENT_INST_HI_1 0xD603D4
+
+#define mmNIC2_QM0_CP_CURRENT_INST_HI_2 0xD603D8
+
+#define mmNIC2_QM0_CP_CURRENT_INST_HI_3 0xD603DC
+
+#define mmNIC2_QM0_CP_CURRENT_INST_HI_4 0xD603E0
+
+#define mmNIC2_QM0_CP_BARRIER_CFG_0 0xD603F4
+
+#define mmNIC2_QM0_CP_BARRIER_CFG_1 0xD603F8
+
+#define mmNIC2_QM0_CP_BARRIER_CFG_2 0xD603FC
+
+#define mmNIC2_QM0_CP_BARRIER_CFG_3 0xD60400
+
+#define mmNIC2_QM0_CP_BARRIER_CFG_4 0xD60404
+
+#define mmNIC2_QM0_CP_DBG_0_0 0xD60408
+
+#define mmNIC2_QM0_CP_DBG_0_1 0xD6040C
+
+#define mmNIC2_QM0_CP_DBG_0_2 0xD60410
+
+#define mmNIC2_QM0_CP_DBG_0_3 0xD60414
+
+#define mmNIC2_QM0_CP_DBG_0_4 0xD60418
+
+#define mmNIC2_QM0_CP_ARUSER_31_11_0 0xD6041C
+
+#define mmNIC2_QM0_CP_ARUSER_31_11_1 0xD60420
+
+#define mmNIC2_QM0_CP_ARUSER_31_11_2 0xD60424
+
+#define mmNIC2_QM0_CP_ARUSER_31_11_3 0xD60428
+
+#define mmNIC2_QM0_CP_ARUSER_31_11_4 0xD6042C
+
+#define mmNIC2_QM0_CP_AWUSER_31_11_0 0xD60430
+
+#define mmNIC2_QM0_CP_AWUSER_31_11_1 0xD60434
+
+#define mmNIC2_QM0_CP_AWUSER_31_11_2 0xD60438
+
+#define mmNIC2_QM0_CP_AWUSER_31_11_3 0xD6043C
+
+#define mmNIC2_QM0_CP_AWUSER_31_11_4 0xD60440
+
+#define mmNIC2_QM0_ARB_CFG_0 0xD60A00
+
+#define mmNIC2_QM0_ARB_CHOISE_Q_PUSH 0xD60A04
+
+#define mmNIC2_QM0_ARB_WRR_WEIGHT_0 0xD60A08
+
+#define mmNIC2_QM0_ARB_WRR_WEIGHT_1 0xD60A0C
+
+#define mmNIC2_QM0_ARB_WRR_WEIGHT_2 0xD60A10
+
+#define mmNIC2_QM0_ARB_WRR_WEIGHT_3 0xD60A14
+
+#define mmNIC2_QM0_ARB_CFG_1 0xD60A18
+
+#define mmNIC2_QM0_ARB_MST_AVAIL_CRED_0 0xD60A20
+
+#define mmNIC2_QM0_ARB_MST_AVAIL_CRED_1 0xD60A24
+
+#define mmNIC2_QM0_ARB_MST_AVAIL_CRED_2 0xD60A28
+
+#define mmNIC2_QM0_ARB_MST_AVAIL_CRED_3 0xD60A2C
+
+#define mmNIC2_QM0_ARB_MST_AVAIL_CRED_4 0xD60A30
+
+#define mmNIC2_QM0_ARB_MST_AVAIL_CRED_5 0xD60A34
+
+#define mmNIC2_QM0_ARB_MST_AVAIL_CRED_6 0xD60A38
+
+#define mmNIC2_QM0_ARB_MST_AVAIL_CRED_7 0xD60A3C
+
+#define mmNIC2_QM0_ARB_MST_AVAIL_CRED_8 0xD60A40
+
+#define mmNIC2_QM0_ARB_MST_AVAIL_CRED_9 0xD60A44
+
+#define mmNIC2_QM0_ARB_MST_AVAIL_CRED_10 0xD60A48
+
+#define mmNIC2_QM0_ARB_MST_AVAIL_CRED_11 0xD60A4C
+
+#define mmNIC2_QM0_ARB_MST_AVAIL_CRED_12 0xD60A50
+
+#define mmNIC2_QM0_ARB_MST_AVAIL_CRED_13 0xD60A54
+
+#define mmNIC2_QM0_ARB_MST_AVAIL_CRED_14 0xD60A58
+
+#define mmNIC2_QM0_ARB_MST_AVAIL_CRED_15 0xD60A5C
+
+#define mmNIC2_QM0_ARB_MST_AVAIL_CRED_16 0xD60A60
+
+#define mmNIC2_QM0_ARB_MST_AVAIL_CRED_17 0xD60A64
+
+#define mmNIC2_QM0_ARB_MST_AVAIL_CRED_18 0xD60A68
+
+#define mmNIC2_QM0_ARB_MST_AVAIL_CRED_19 0xD60A6C
+
+#define mmNIC2_QM0_ARB_MST_AVAIL_CRED_20 0xD60A70
+
+#define mmNIC2_QM0_ARB_MST_AVAIL_CRED_21 0xD60A74
+
+#define mmNIC2_QM0_ARB_MST_AVAIL_CRED_22 0xD60A78
+
+#define mmNIC2_QM0_ARB_MST_AVAIL_CRED_23 0xD60A7C
+
+#define mmNIC2_QM0_ARB_MST_AVAIL_CRED_24 0xD60A80
+
+#define mmNIC2_QM0_ARB_MST_AVAIL_CRED_25 0xD60A84
+
+#define mmNIC2_QM0_ARB_MST_AVAIL_CRED_26 0xD60A88
+
+#define mmNIC2_QM0_ARB_MST_AVAIL_CRED_27 0xD60A8C
+
+#define mmNIC2_QM0_ARB_MST_AVAIL_CRED_28 0xD60A90
+
+#define mmNIC2_QM0_ARB_MST_AVAIL_CRED_29 0xD60A94
+
+#define mmNIC2_QM0_ARB_MST_AVAIL_CRED_30 0xD60A98
+
+#define mmNIC2_QM0_ARB_MST_AVAIL_CRED_31 0xD60A9C
+
+#define mmNIC2_QM0_ARB_MST_CRED_INC 0xD60AA0
+
+#define mmNIC2_QM0_ARB_MST_CHOISE_PUSH_OFST_0 0xD60AA4
+
+#define mmNIC2_QM0_ARB_MST_CHOISE_PUSH_OFST_1 0xD60AA8
+
+#define mmNIC2_QM0_ARB_MST_CHOISE_PUSH_OFST_2 0xD60AAC
+
+#define mmNIC2_QM0_ARB_MST_CHOISE_PUSH_OFST_3 0xD60AB0
+
+#define mmNIC2_QM0_ARB_MST_CHOISE_PUSH_OFST_4 0xD60AB4
+
+#define mmNIC2_QM0_ARB_MST_CHOISE_PUSH_OFST_5 0xD60AB8
+
+#define mmNIC2_QM0_ARB_MST_CHOISE_PUSH_OFST_6 0xD60ABC
+
+#define mmNIC2_QM0_ARB_MST_CHOISE_PUSH_OFST_7 0xD60AC0
+
+#define mmNIC2_QM0_ARB_MST_CHOISE_PUSH_OFST_8 0xD60AC4
+
+#define mmNIC2_QM0_ARB_MST_CHOISE_PUSH_OFST_9 0xD60AC8
+
+#define mmNIC2_QM0_ARB_MST_CHOISE_PUSH_OFST_10 0xD60ACC
+
+#define mmNIC2_QM0_ARB_MST_CHOISE_PUSH_OFST_11 0xD60AD0
+
+#define mmNIC2_QM0_ARB_MST_CHOISE_PUSH_OFST_12 0xD60AD4
+
+#define mmNIC2_QM0_ARB_MST_CHOISE_PUSH_OFST_13 0xD60AD8
+
+#define mmNIC2_QM0_ARB_MST_CHOISE_PUSH_OFST_14 0xD60ADC
+
+#define mmNIC2_QM0_ARB_MST_CHOISE_PUSH_OFST_15 0xD60AE0
+
+#define mmNIC2_QM0_ARB_MST_CHOISE_PUSH_OFST_16 0xD60AE4
+
+#define mmNIC2_QM0_ARB_MST_CHOISE_PUSH_OFST_17 0xD60AE8
+
+#define mmNIC2_QM0_ARB_MST_CHOISE_PUSH_OFST_18 0xD60AEC
+
+#define mmNIC2_QM0_ARB_MST_CHOISE_PUSH_OFST_19 0xD60AF0
+
+#define mmNIC2_QM0_ARB_MST_CHOISE_PUSH_OFST_20 0xD60AF4
+
+#define mmNIC2_QM0_ARB_MST_CHOISE_PUSH_OFST_21 0xD60AF8
+
+#define mmNIC2_QM0_ARB_MST_CHOISE_PUSH_OFST_22 0xD60AFC
+
+#define mmNIC2_QM0_ARB_MST_CHOISE_PUSH_OFST_23 0xD60B00
+
+#define mmNIC2_QM0_ARB_MST_CHOISE_PUSH_OFST_24 0xD60B04
+
+#define mmNIC2_QM0_ARB_MST_CHOISE_PUSH_OFST_25 0xD60B08
+
+#define mmNIC2_QM0_ARB_MST_CHOISE_PUSH_OFST_26 0xD60B0C
+
+#define mmNIC2_QM0_ARB_MST_CHOISE_PUSH_OFST_27 0xD60B10
+
+#define mmNIC2_QM0_ARB_MST_CHOISE_PUSH_OFST_28 0xD60B14
+
+#define mmNIC2_QM0_ARB_MST_CHOISE_PUSH_OFST_29 0xD60B18
+
+#define mmNIC2_QM0_ARB_MST_CHOISE_PUSH_OFST_30 0xD60B1C
+
+#define mmNIC2_QM0_ARB_MST_CHOISE_PUSH_OFST_31 0xD60B20
+
+#define mmNIC2_QM0_ARB_SLV_MASTER_INC_CRED_OFST 0xD60B28
+
+#define mmNIC2_QM0_ARB_MST_SLAVE_EN 0xD60B2C
+
+#define mmNIC2_QM0_ARB_MST_QUIET_PER 0xD60B34
+
+#define mmNIC2_QM0_ARB_SLV_CHOISE_WDT 0xD60B38
+
+#define mmNIC2_QM0_ARB_SLV_ID 0xD60B3C
+
+#define mmNIC2_QM0_ARB_MSG_MAX_INFLIGHT 0xD60B44
+
+#define mmNIC2_QM0_ARB_MSG_AWUSER_31_11 0xD60B48
+
+#define mmNIC2_QM0_ARB_MSG_AWUSER_SEC_PROP 0xD60B4C
+
+#define mmNIC2_QM0_ARB_MSG_AWUSER_NON_SEC_PROP 0xD60B50
+
+#define mmNIC2_QM0_ARB_BASE_LO 0xD60B54
+
+#define mmNIC2_QM0_ARB_BASE_HI 0xD60B58
+
+#define mmNIC2_QM0_ARB_STATE_STS 0xD60B80
+
+#define mmNIC2_QM0_ARB_CHOISE_FULLNESS_STS 0xD60B84
+
+#define mmNIC2_QM0_ARB_MSG_STS 0xD60B88
+
+#define mmNIC2_QM0_ARB_SLV_CHOISE_Q_HEAD 0xD60B8C
+
+#define mmNIC2_QM0_ARB_ERR_CAUSE 0xD60B9C
+
+#define mmNIC2_QM0_ARB_ERR_MSG_EN 0xD60BA0
+
+#define mmNIC2_QM0_ARB_ERR_STS_DRP 0xD60BA8
+
+#define mmNIC2_QM0_ARB_MST_CRED_STS_0 0xD60BB0
+
+#define mmNIC2_QM0_ARB_MST_CRED_STS_1 0xD60BB4
+
+#define mmNIC2_QM0_ARB_MST_CRED_STS_2 0xD60BB8
+
+#define mmNIC2_QM0_ARB_MST_CRED_STS_3 0xD60BBC
+
+#define mmNIC2_QM0_ARB_MST_CRED_STS_4 0xD60BC0
+
+#define mmNIC2_QM0_ARB_MST_CRED_STS_5 0xD60BC4
+
+#define mmNIC2_QM0_ARB_MST_CRED_STS_6 0xD60BC8
+
+#define mmNIC2_QM0_ARB_MST_CRED_STS_7 0xD60BCC
+
+#define mmNIC2_QM0_ARB_MST_CRED_STS_8 0xD60BD0
+
+#define mmNIC2_QM0_ARB_MST_CRED_STS_9 0xD60BD4
+
+#define mmNIC2_QM0_ARB_MST_CRED_STS_10 0xD60BD8
+
+#define mmNIC2_QM0_ARB_MST_CRED_STS_11 0xD60BDC
+
+#define mmNIC2_QM0_ARB_MST_CRED_STS_12 0xD60BE0
+
+#define mmNIC2_QM0_ARB_MST_CRED_STS_13 0xD60BE4
+
+#define mmNIC2_QM0_ARB_MST_CRED_STS_14 0xD60BE8
+
+#define mmNIC2_QM0_ARB_MST_CRED_STS_15 0xD60BEC
+
+#define mmNIC2_QM0_ARB_MST_CRED_STS_16 0xD60BF0
+
+#define mmNIC2_QM0_ARB_MST_CRED_STS_17 0xD60BF4
+
+#define mmNIC2_QM0_ARB_MST_CRED_STS_18 0xD60BF8
+
+#define mmNIC2_QM0_ARB_MST_CRED_STS_19 0xD60BFC
+
+#define mmNIC2_QM0_ARB_MST_CRED_STS_20 0xD60C00
+
+#define mmNIC2_QM0_ARB_MST_CRED_STS_21 0xD60C04
+
+#define mmNIC2_QM0_ARB_MST_CRED_STS_22 0xD60C08
+
+#define mmNIC2_QM0_ARB_MST_CRED_STS_23 0xD60C0C
+
+#define mmNIC2_QM0_ARB_MST_CRED_STS_24 0xD60C10
+
+#define mmNIC2_QM0_ARB_MST_CRED_STS_25 0xD60C14
+
+#define mmNIC2_QM0_ARB_MST_CRED_STS_26 0xD60C18
+
+#define mmNIC2_QM0_ARB_MST_CRED_STS_27 0xD60C1C
+
+#define mmNIC2_QM0_ARB_MST_CRED_STS_28 0xD60C20
+
+#define mmNIC2_QM0_ARB_MST_CRED_STS_29 0xD60C24
+
+#define mmNIC2_QM0_ARB_MST_CRED_STS_30 0xD60C28
+
+#define mmNIC2_QM0_ARB_MST_CRED_STS_31 0xD60C2C
+
+#define mmNIC2_QM0_CGM_CFG 0xD60C70
+
+#define mmNIC2_QM0_CGM_STS 0xD60C74
+
+#define mmNIC2_QM0_CGM_CFG1 0xD60C78
+
+#define mmNIC2_QM0_LOCAL_RANGE_BASE 0xD60C80
+
+#define mmNIC2_QM0_LOCAL_RANGE_SIZE 0xD60C84
+
+#define mmNIC2_QM0_CSMR_STRICT_PRIO_CFG 0xD60C90
+
+#define mmNIC2_QM0_HBW_RD_RATE_LIM_CFG_1 0xD60C94
+
+#define mmNIC2_QM0_LBW_WR_RATE_LIM_CFG_0 0xD60C98
+
+#define mmNIC2_QM0_LBW_WR_RATE_LIM_CFG_1 0xD60C9C
+
+#define mmNIC2_QM0_HBW_RD_RATE_LIM_CFG_0 0xD60CA0
+
+#define mmNIC2_QM0_GLBL_AXCACHE 0xD60CA4
+
+#define mmNIC2_QM0_IND_GW_APB_CFG 0xD60CB0
+
+#define mmNIC2_QM0_IND_GW_APB_WDATA 0xD60CB4
+
+#define mmNIC2_QM0_IND_GW_APB_RDATA 0xD60CB8
+
+#define mmNIC2_QM0_IND_GW_APB_STATUS 0xD60CBC
+
+#define mmNIC2_QM0_GLBL_ERR_ADDR_LO 0xD60CD0
+
+#define mmNIC2_QM0_GLBL_ERR_ADDR_HI 0xD60CD4
+
+#define mmNIC2_QM0_GLBL_ERR_WDATA 0xD60CD8
+
+#define mmNIC2_QM0_GLBL_MEM_INIT_BUSY 0xD60D00
+
+#endif /* ASIC_REG_NIC2_QM0_REGS_H_ */
diff --git a/drivers/accel/habanalabs/include/gaudi/asic_reg/nic2_qm1_regs.h b/drivers/accel/habanalabs/include/gaudi/asic_reg/nic2_qm1_regs.h
new file mode 100644
index 0000000000..b7f091ddc8
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi/asic_reg/nic2_qm1_regs.h
@@ -0,0 +1,834 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2016-2018 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ ** DO NOT EDIT BELOW **
+ ************************************/
+
+#ifndef ASIC_REG_NIC2_QM1_REGS_H_
+#define ASIC_REG_NIC2_QM1_REGS_H_
+
+/*
+ *****************************************
+ * NIC2_QM1 (Prototype: QMAN)
+ *****************************************
+ */
+
+#define mmNIC2_QM1_GLBL_CFG0 0xD62000
+
+#define mmNIC2_QM1_GLBL_CFG1 0xD62004
+
+#define mmNIC2_QM1_GLBL_PROT 0xD62008
+
+#define mmNIC2_QM1_GLBL_ERR_CFG 0xD6200C
+
+#define mmNIC2_QM1_GLBL_SECURE_PROPS_0 0xD62010
+
+#define mmNIC2_QM1_GLBL_SECURE_PROPS_1 0xD62014
+
+#define mmNIC2_QM1_GLBL_SECURE_PROPS_2 0xD62018
+
+#define mmNIC2_QM1_GLBL_SECURE_PROPS_3 0xD6201C
+
+#define mmNIC2_QM1_GLBL_SECURE_PROPS_4 0xD62020
+
+#define mmNIC2_QM1_GLBL_NON_SECURE_PROPS_0 0xD62024
+
+#define mmNIC2_QM1_GLBL_NON_SECURE_PROPS_1 0xD62028
+
+#define mmNIC2_QM1_GLBL_NON_SECURE_PROPS_2 0xD6202C
+
+#define mmNIC2_QM1_GLBL_NON_SECURE_PROPS_3 0xD62030
+
+#define mmNIC2_QM1_GLBL_NON_SECURE_PROPS_4 0xD62034
+
+#define mmNIC2_QM1_GLBL_STS0 0xD62038
+
+#define mmNIC2_QM1_GLBL_STS1_0 0xD62040
+
+#define mmNIC2_QM1_GLBL_STS1_1 0xD62044
+
+#define mmNIC2_QM1_GLBL_STS1_2 0xD62048
+
+#define mmNIC2_QM1_GLBL_STS1_3 0xD6204C
+
+#define mmNIC2_QM1_GLBL_STS1_4 0xD62050
+
+#define mmNIC2_QM1_GLBL_MSG_EN_0 0xD62054
+
+#define mmNIC2_QM1_GLBL_MSG_EN_1 0xD62058
+
+#define mmNIC2_QM1_GLBL_MSG_EN_2 0xD6205C
+
+#define mmNIC2_QM1_GLBL_MSG_EN_3 0xD62060
+
+#define mmNIC2_QM1_GLBL_MSG_EN_4 0xD62068
+
+#define mmNIC2_QM1_PQ_BASE_LO_0 0xD62070
+
+#define mmNIC2_QM1_PQ_BASE_LO_1 0xD62074
+
+#define mmNIC2_QM1_PQ_BASE_LO_2 0xD62078
+
+#define mmNIC2_QM1_PQ_BASE_LO_3 0xD6207C
+
+#define mmNIC2_QM1_PQ_BASE_HI_0 0xD62080
+
+#define mmNIC2_QM1_PQ_BASE_HI_1 0xD62084
+
+#define mmNIC2_QM1_PQ_BASE_HI_2 0xD62088
+
+#define mmNIC2_QM1_PQ_BASE_HI_3 0xD6208C
+
+#define mmNIC2_QM1_PQ_SIZE_0 0xD62090
+
+#define mmNIC2_QM1_PQ_SIZE_1 0xD62094
+
+#define mmNIC2_QM1_PQ_SIZE_2 0xD62098
+
+#define mmNIC2_QM1_PQ_SIZE_3 0xD6209C
+
+#define mmNIC2_QM1_PQ_PI_0 0xD620A0
+
+#define mmNIC2_QM1_PQ_PI_1 0xD620A4
+
+#define mmNIC2_QM1_PQ_PI_2 0xD620A8
+
+#define mmNIC2_QM1_PQ_PI_3 0xD620AC
+
+#define mmNIC2_QM1_PQ_CI_0 0xD620B0
+
+#define mmNIC2_QM1_PQ_CI_1 0xD620B4
+
+#define mmNIC2_QM1_PQ_CI_2 0xD620B8
+
+#define mmNIC2_QM1_PQ_CI_3 0xD620BC
+
+#define mmNIC2_QM1_PQ_CFG0_0 0xD620C0
+
+#define mmNIC2_QM1_PQ_CFG0_1 0xD620C4
+
+#define mmNIC2_QM1_PQ_CFG0_2 0xD620C8
+
+#define mmNIC2_QM1_PQ_CFG0_3 0xD620CC
+
+#define mmNIC2_QM1_PQ_CFG1_0 0xD620D0
+
+#define mmNIC2_QM1_PQ_CFG1_1 0xD620D4
+
+#define mmNIC2_QM1_PQ_CFG1_2 0xD620D8
+
+#define mmNIC2_QM1_PQ_CFG1_3 0xD620DC
+
+#define mmNIC2_QM1_PQ_ARUSER_31_11_0 0xD620E0
+
+#define mmNIC2_QM1_PQ_ARUSER_31_11_1 0xD620E4
+
+#define mmNIC2_QM1_PQ_ARUSER_31_11_2 0xD620E8
+
+#define mmNIC2_QM1_PQ_ARUSER_31_11_3 0xD620EC
+
+#define mmNIC2_QM1_PQ_STS0_0 0xD620F0
+
+#define mmNIC2_QM1_PQ_STS0_1 0xD620F4
+
+#define mmNIC2_QM1_PQ_STS0_2 0xD620F8
+
+#define mmNIC2_QM1_PQ_STS0_3 0xD620FC
+
+#define mmNIC2_QM1_PQ_STS1_0 0xD62100
+
+#define mmNIC2_QM1_PQ_STS1_1 0xD62104
+
+#define mmNIC2_QM1_PQ_STS1_2 0xD62108
+
+#define mmNIC2_QM1_PQ_STS1_3 0xD6210C
+
+#define mmNIC2_QM1_CQ_CFG0_0 0xD62110
+
+#define mmNIC2_QM1_CQ_CFG0_1 0xD62114
+
+#define mmNIC2_QM1_CQ_CFG0_2 0xD62118
+
+#define mmNIC2_QM1_CQ_CFG0_3 0xD6211C
+
+#define mmNIC2_QM1_CQ_CFG0_4 0xD62120
+
+#define mmNIC2_QM1_CQ_CFG1_0 0xD62124
+
+#define mmNIC2_QM1_CQ_CFG1_1 0xD62128
+
+#define mmNIC2_QM1_CQ_CFG1_2 0xD6212C
+
+#define mmNIC2_QM1_CQ_CFG1_3 0xD62130
+
+#define mmNIC2_QM1_CQ_CFG1_4 0xD62134
+
+#define mmNIC2_QM1_CQ_ARUSER_31_11_0 0xD62138
+
+#define mmNIC2_QM1_CQ_ARUSER_31_11_1 0xD6213C
+
+#define mmNIC2_QM1_CQ_ARUSER_31_11_2 0xD62140
+
+#define mmNIC2_QM1_CQ_ARUSER_31_11_3 0xD62144
+
+#define mmNIC2_QM1_CQ_ARUSER_31_11_4 0xD62148
+
+#define mmNIC2_QM1_CQ_STS0_0 0xD6214C
+
+#define mmNIC2_QM1_CQ_STS0_1 0xD62150
+
+#define mmNIC2_QM1_CQ_STS0_2 0xD62154
+
+#define mmNIC2_QM1_CQ_STS0_3 0xD62158
+
+#define mmNIC2_QM1_CQ_STS0_4 0xD6215C
+
+#define mmNIC2_QM1_CQ_STS1_0 0xD62160
+
+#define mmNIC2_QM1_CQ_STS1_1 0xD62164
+
+#define mmNIC2_QM1_CQ_STS1_2 0xD62168
+
+#define mmNIC2_QM1_CQ_STS1_3 0xD6216C
+
+#define mmNIC2_QM1_CQ_STS1_4 0xD62170
+
+#define mmNIC2_QM1_CQ_PTR_LO_0 0xD62174
+
+#define mmNIC2_QM1_CQ_PTR_HI_0 0xD62178
+
+#define mmNIC2_QM1_CQ_TSIZE_0 0xD6217C
+
+#define mmNIC2_QM1_CQ_CTL_0 0xD62180
+
+#define mmNIC2_QM1_CQ_PTR_LO_1 0xD62184
+
+#define mmNIC2_QM1_CQ_PTR_HI_1 0xD62188
+
+#define mmNIC2_QM1_CQ_TSIZE_1 0xD6218C
+
+#define mmNIC2_QM1_CQ_CTL_1 0xD62190
+
+#define mmNIC2_QM1_CQ_PTR_LO_2 0xD62194
+
+#define mmNIC2_QM1_CQ_PTR_HI_2 0xD62198
+
+#define mmNIC2_QM1_CQ_TSIZE_2 0xD6219C
+
+#define mmNIC2_QM1_CQ_CTL_2 0xD621A0
+
+#define mmNIC2_QM1_CQ_PTR_LO_3 0xD621A4
+
+#define mmNIC2_QM1_CQ_PTR_HI_3 0xD621A8
+
+#define mmNIC2_QM1_CQ_TSIZE_3 0xD621AC
+
+#define mmNIC2_QM1_CQ_CTL_3 0xD621B0
+
+#define mmNIC2_QM1_CQ_PTR_LO_4 0xD621B4
+
+#define mmNIC2_QM1_CQ_PTR_HI_4 0xD621B8
+
+#define mmNIC2_QM1_CQ_TSIZE_4 0xD621BC
+
+#define mmNIC2_QM1_CQ_CTL_4 0xD621C0
+
+#define mmNIC2_QM1_CQ_PTR_LO_STS_0 0xD621C4
+
+#define mmNIC2_QM1_CQ_PTR_LO_STS_1 0xD621C8
+
+#define mmNIC2_QM1_CQ_PTR_LO_STS_2 0xD621CC
+
+#define mmNIC2_QM1_CQ_PTR_LO_STS_3 0xD621D0
+
+#define mmNIC2_QM1_CQ_PTR_LO_STS_4 0xD621D4
+
+#define mmNIC2_QM1_CQ_PTR_HI_STS_0 0xD621D8
+
+#define mmNIC2_QM1_CQ_PTR_HI_STS_1 0xD621DC
+
+#define mmNIC2_QM1_CQ_PTR_HI_STS_2 0xD621E0
+
+#define mmNIC2_QM1_CQ_PTR_HI_STS_3 0xD621E4
+
+#define mmNIC2_QM1_CQ_PTR_HI_STS_4 0xD621E8
+
+#define mmNIC2_QM1_CQ_TSIZE_STS_0 0xD621EC
+
+#define mmNIC2_QM1_CQ_TSIZE_STS_1 0xD621F0
+
+#define mmNIC2_QM1_CQ_TSIZE_STS_2 0xD621F4
+
+#define mmNIC2_QM1_CQ_TSIZE_STS_3 0xD621F8
+
+#define mmNIC2_QM1_CQ_TSIZE_STS_4 0xD621FC
+
+#define mmNIC2_QM1_CQ_CTL_STS_0 0xD62200
+
+#define mmNIC2_QM1_CQ_CTL_STS_1 0xD62204
+
+#define mmNIC2_QM1_CQ_CTL_STS_2 0xD62208
+
+#define mmNIC2_QM1_CQ_CTL_STS_3 0xD6220C
+
+#define mmNIC2_QM1_CQ_CTL_STS_4 0xD62210
+
+#define mmNIC2_QM1_CQ_IFIFO_CNT_0 0xD62214
+
+#define mmNIC2_QM1_CQ_IFIFO_CNT_1 0xD62218
+
+#define mmNIC2_QM1_CQ_IFIFO_CNT_2 0xD6221C
+
+#define mmNIC2_QM1_CQ_IFIFO_CNT_3 0xD62220
+
+#define mmNIC2_QM1_CQ_IFIFO_CNT_4 0xD62224
+
+#define mmNIC2_QM1_CP_MSG_BASE0_ADDR_LO_0 0xD62228
+
+#define mmNIC2_QM1_CP_MSG_BASE0_ADDR_LO_1 0xD6222C
+
+#define mmNIC2_QM1_CP_MSG_BASE0_ADDR_LO_2 0xD62230
+
+#define mmNIC2_QM1_CP_MSG_BASE0_ADDR_LO_3 0xD62234
+
+#define mmNIC2_QM1_CP_MSG_BASE0_ADDR_LO_4 0xD62238
+
+#define mmNIC2_QM1_CP_MSG_BASE0_ADDR_HI_0 0xD6223C
+
+#define mmNIC2_QM1_CP_MSG_BASE0_ADDR_HI_1 0xD62240
+
+#define mmNIC2_QM1_CP_MSG_BASE0_ADDR_HI_2 0xD62244
+
+#define mmNIC2_QM1_CP_MSG_BASE0_ADDR_HI_3 0xD62248
+
+#define mmNIC2_QM1_CP_MSG_BASE0_ADDR_HI_4 0xD6224C
+
+#define mmNIC2_QM1_CP_MSG_BASE1_ADDR_LO_0 0xD62250
+
+#define mmNIC2_QM1_CP_MSG_BASE1_ADDR_LO_1 0xD62254
+
+#define mmNIC2_QM1_CP_MSG_BASE1_ADDR_LO_2 0xD62258
+
+#define mmNIC2_QM1_CP_MSG_BASE1_ADDR_LO_3 0xD6225C
+
+#define mmNIC2_QM1_CP_MSG_BASE1_ADDR_LO_4 0xD62260
+
+#define mmNIC2_QM1_CP_MSG_BASE1_ADDR_HI_0 0xD62264
+
+#define mmNIC2_QM1_CP_MSG_BASE1_ADDR_HI_1 0xD62268
+
+#define mmNIC2_QM1_CP_MSG_BASE1_ADDR_HI_2 0xD6226C
+
+#define mmNIC2_QM1_CP_MSG_BASE1_ADDR_HI_3 0xD62270
+
+#define mmNIC2_QM1_CP_MSG_BASE1_ADDR_HI_4 0xD62274
+
+#define mmNIC2_QM1_CP_MSG_BASE2_ADDR_LO_0 0xD62278
+
+#define mmNIC2_QM1_CP_MSG_BASE2_ADDR_LO_1 0xD6227C
+
+#define mmNIC2_QM1_CP_MSG_BASE2_ADDR_LO_2 0xD62280
+
+#define mmNIC2_QM1_CP_MSG_BASE2_ADDR_LO_3 0xD62284
+
+#define mmNIC2_QM1_CP_MSG_BASE2_ADDR_LO_4 0xD62288
+
+#define mmNIC2_QM1_CP_MSG_BASE2_ADDR_HI_0 0xD6228C
+
+#define mmNIC2_QM1_CP_MSG_BASE2_ADDR_HI_1 0xD62290
+
+#define mmNIC2_QM1_CP_MSG_BASE2_ADDR_HI_2 0xD62294
+
+#define mmNIC2_QM1_CP_MSG_BASE2_ADDR_HI_3 0xD62298
+
+#define mmNIC2_QM1_CP_MSG_BASE2_ADDR_HI_4 0xD6229C
+
+#define mmNIC2_QM1_CP_MSG_BASE3_ADDR_LO_0 0xD622A0
+
+#define mmNIC2_QM1_CP_MSG_BASE3_ADDR_LO_1 0xD622A4
+
+#define mmNIC2_QM1_CP_MSG_BASE3_ADDR_LO_2 0xD622A8
+
+#define mmNIC2_QM1_CP_MSG_BASE3_ADDR_LO_3 0xD622AC
+
+#define mmNIC2_QM1_CP_MSG_BASE3_ADDR_LO_4 0xD622B0
+
+#define mmNIC2_QM1_CP_MSG_BASE3_ADDR_HI_0 0xD622B4
+
+#define mmNIC2_QM1_CP_MSG_BASE3_ADDR_HI_1 0xD622B8
+
+#define mmNIC2_QM1_CP_MSG_BASE3_ADDR_HI_2 0xD622BC
+
+#define mmNIC2_QM1_CP_MSG_BASE3_ADDR_HI_3 0xD622C0
+
+#define mmNIC2_QM1_CP_MSG_BASE3_ADDR_HI_4 0xD622C4
+
+#define mmNIC2_QM1_CP_LDMA_TSIZE_OFFSET_0 0xD622C8
+
+#define mmNIC2_QM1_CP_LDMA_TSIZE_OFFSET_1 0xD622CC
+
+#define mmNIC2_QM1_CP_LDMA_TSIZE_OFFSET_2 0xD622D0
+
+#define mmNIC2_QM1_CP_LDMA_TSIZE_OFFSET_3 0xD622D4
+
+#define mmNIC2_QM1_CP_LDMA_TSIZE_OFFSET_4 0xD622D8
+
+#define mmNIC2_QM1_CP_LDMA_SRC_BASE_LO_OFFSET_0 0xD622E0
+
+#define mmNIC2_QM1_CP_LDMA_SRC_BASE_LO_OFFSET_1 0xD622E4
+
+#define mmNIC2_QM1_CP_LDMA_SRC_BASE_LO_OFFSET_2 0xD622E8
+
+#define mmNIC2_QM1_CP_LDMA_SRC_BASE_LO_OFFSET_3 0xD622EC
+
+#define mmNIC2_QM1_CP_LDMA_SRC_BASE_LO_OFFSET_4 0xD622F0
+
+#define mmNIC2_QM1_CP_LDMA_DST_BASE_LO_OFFSET_0 0xD622F4
+
+#define mmNIC2_QM1_CP_LDMA_DST_BASE_LO_OFFSET_1 0xD622F8
+
+#define mmNIC2_QM1_CP_LDMA_DST_BASE_LO_OFFSET_2 0xD622FC
+
+#define mmNIC2_QM1_CP_LDMA_DST_BASE_LO_OFFSET_3 0xD62300
+
+#define mmNIC2_QM1_CP_LDMA_DST_BASE_LO_OFFSET_4 0xD62304
+
+#define mmNIC2_QM1_CP_FENCE0_RDATA_0 0xD62308
+
+#define mmNIC2_QM1_CP_FENCE0_RDATA_1 0xD6230C
+
+#define mmNIC2_QM1_CP_FENCE0_RDATA_2 0xD62310
+
+#define mmNIC2_QM1_CP_FENCE0_RDATA_3 0xD62314
+
+#define mmNIC2_QM1_CP_FENCE0_RDATA_4 0xD62318
+
+#define mmNIC2_QM1_CP_FENCE1_RDATA_0 0xD6231C
+
+#define mmNIC2_QM1_CP_FENCE1_RDATA_1 0xD62320
+
+#define mmNIC2_QM1_CP_FENCE1_RDATA_2 0xD62324
+
+#define mmNIC2_QM1_CP_FENCE1_RDATA_3 0xD62328
+
+#define mmNIC2_QM1_CP_FENCE1_RDATA_4 0xD6232C
+
+#define mmNIC2_QM1_CP_FENCE2_RDATA_0 0xD62330
+
+#define mmNIC2_QM1_CP_FENCE2_RDATA_1 0xD62334
+
+#define mmNIC2_QM1_CP_FENCE2_RDATA_2 0xD62338
+
+#define mmNIC2_QM1_CP_FENCE2_RDATA_3 0xD6233C
+
+#define mmNIC2_QM1_CP_FENCE2_RDATA_4 0xD62340
+
+#define mmNIC2_QM1_CP_FENCE3_RDATA_0 0xD62344
+
+#define mmNIC2_QM1_CP_FENCE3_RDATA_1 0xD62348
+
+#define mmNIC2_QM1_CP_FENCE3_RDATA_2 0xD6234C
+
+#define mmNIC2_QM1_CP_FENCE3_RDATA_3 0xD62350
+
+#define mmNIC2_QM1_CP_FENCE3_RDATA_4 0xD62354
+
+#define mmNIC2_QM1_CP_FENCE0_CNT_0 0xD62358
+
+#define mmNIC2_QM1_CP_FENCE0_CNT_1 0xD6235C
+
+#define mmNIC2_QM1_CP_FENCE0_CNT_2 0xD62360
+
+#define mmNIC2_QM1_CP_FENCE0_CNT_3 0xD62364
+
+#define mmNIC2_QM1_CP_FENCE0_CNT_4 0xD62368
+
+#define mmNIC2_QM1_CP_FENCE1_CNT_0 0xD6236C
+
+#define mmNIC2_QM1_CP_FENCE1_CNT_1 0xD62370
+
+#define mmNIC2_QM1_CP_FENCE1_CNT_2 0xD62374
+
+#define mmNIC2_QM1_CP_FENCE1_CNT_3 0xD62378
+
+#define mmNIC2_QM1_CP_FENCE1_CNT_4 0xD6237C
+
+#define mmNIC2_QM1_CP_FENCE2_CNT_0 0xD62380
+
+#define mmNIC2_QM1_CP_FENCE2_CNT_1 0xD62384
+
+#define mmNIC2_QM1_CP_FENCE2_CNT_2 0xD62388
+
+#define mmNIC2_QM1_CP_FENCE2_CNT_3 0xD6238C
+
+#define mmNIC2_QM1_CP_FENCE2_CNT_4 0xD62390
+
+#define mmNIC2_QM1_CP_FENCE3_CNT_0 0xD62394
+
+#define mmNIC2_QM1_CP_FENCE3_CNT_1 0xD62398
+
+#define mmNIC2_QM1_CP_FENCE3_CNT_2 0xD6239C
+
+#define mmNIC2_QM1_CP_FENCE3_CNT_3 0xD623A0
+
+#define mmNIC2_QM1_CP_FENCE3_CNT_4 0xD623A4
+
+#define mmNIC2_QM1_CP_STS_0 0xD623A8
+
+#define mmNIC2_QM1_CP_STS_1 0xD623AC
+
+#define mmNIC2_QM1_CP_STS_2 0xD623B0
+
+#define mmNIC2_QM1_CP_STS_3 0xD623B4
+
+#define mmNIC2_QM1_CP_STS_4 0xD623B8
+
+#define mmNIC2_QM1_CP_CURRENT_INST_LO_0 0xD623BC
+
+#define mmNIC2_QM1_CP_CURRENT_INST_LO_1 0xD623C0
+
+#define mmNIC2_QM1_CP_CURRENT_INST_LO_2 0xD623C4
+
+#define mmNIC2_QM1_CP_CURRENT_INST_LO_3 0xD623C8
+
+#define mmNIC2_QM1_CP_CURRENT_INST_LO_4 0xD623CC
+
+#define mmNIC2_QM1_CP_CURRENT_INST_HI_0 0xD623D0
+
+#define mmNIC2_QM1_CP_CURRENT_INST_HI_1 0xD623D4
+
+#define mmNIC2_QM1_CP_CURRENT_INST_HI_2 0xD623D8
+
+#define mmNIC2_QM1_CP_CURRENT_INST_HI_3 0xD623DC
+
+#define mmNIC2_QM1_CP_CURRENT_INST_HI_4 0xD623E0
+
+#define mmNIC2_QM1_CP_BARRIER_CFG_0 0xD623F4
+
+#define mmNIC2_QM1_CP_BARRIER_CFG_1 0xD623F8
+
+#define mmNIC2_QM1_CP_BARRIER_CFG_2 0xD623FC
+
+#define mmNIC2_QM1_CP_BARRIER_CFG_3 0xD62400
+
+#define mmNIC2_QM1_CP_BARRIER_CFG_4 0xD62404
+
+#define mmNIC2_QM1_CP_DBG_0_0 0xD62408
+
+#define mmNIC2_QM1_CP_DBG_0_1 0xD6240C
+
+#define mmNIC2_QM1_CP_DBG_0_2 0xD62410
+
+#define mmNIC2_QM1_CP_DBG_0_3 0xD62414
+
+#define mmNIC2_QM1_CP_DBG_0_4 0xD62418
+
+#define mmNIC2_QM1_CP_ARUSER_31_11_0 0xD6241C
+
+#define mmNIC2_QM1_CP_ARUSER_31_11_1 0xD62420
+
+#define mmNIC2_QM1_CP_ARUSER_31_11_2 0xD62424
+
+#define mmNIC2_QM1_CP_ARUSER_31_11_3 0xD62428
+
+#define mmNIC2_QM1_CP_ARUSER_31_11_4 0xD6242C
+
+#define mmNIC2_QM1_CP_AWUSER_31_11_0 0xD62430
+
+#define mmNIC2_QM1_CP_AWUSER_31_11_1 0xD62434
+
+#define mmNIC2_QM1_CP_AWUSER_31_11_2 0xD62438
+
+#define mmNIC2_QM1_CP_AWUSER_31_11_3 0xD6243C
+
+#define mmNIC2_QM1_CP_AWUSER_31_11_4 0xD62440
+
+#define mmNIC2_QM1_ARB_CFG_0 0xD62A00
+
+#define mmNIC2_QM1_ARB_CHOISE_Q_PUSH 0xD62A04
+
+#define mmNIC2_QM1_ARB_WRR_WEIGHT_0 0xD62A08
+
+#define mmNIC2_QM1_ARB_WRR_WEIGHT_1 0xD62A0C
+
+#define mmNIC2_QM1_ARB_WRR_WEIGHT_2 0xD62A10
+
+#define mmNIC2_QM1_ARB_WRR_WEIGHT_3 0xD62A14
+
+#define mmNIC2_QM1_ARB_CFG_1 0xD62A18
+
+#define mmNIC2_QM1_ARB_MST_AVAIL_CRED_0 0xD62A20
+
+#define mmNIC2_QM1_ARB_MST_AVAIL_CRED_1 0xD62A24
+
+#define mmNIC2_QM1_ARB_MST_AVAIL_CRED_2 0xD62A28
+
+#define mmNIC2_QM1_ARB_MST_AVAIL_CRED_3 0xD62A2C
+
+#define mmNIC2_QM1_ARB_MST_AVAIL_CRED_4 0xD62A30
+
+#define mmNIC2_QM1_ARB_MST_AVAIL_CRED_5 0xD62A34
+
+#define mmNIC2_QM1_ARB_MST_AVAIL_CRED_6 0xD62A38
+
+#define mmNIC2_QM1_ARB_MST_AVAIL_CRED_7 0xD62A3C
+
+#define mmNIC2_QM1_ARB_MST_AVAIL_CRED_8 0xD62A40
+
+#define mmNIC2_QM1_ARB_MST_AVAIL_CRED_9 0xD62A44
+
+#define mmNIC2_QM1_ARB_MST_AVAIL_CRED_10 0xD62A48
+
+#define mmNIC2_QM1_ARB_MST_AVAIL_CRED_11 0xD62A4C
+
+#define mmNIC2_QM1_ARB_MST_AVAIL_CRED_12 0xD62A50
+
+#define mmNIC2_QM1_ARB_MST_AVAIL_CRED_13 0xD62A54
+
+#define mmNIC2_QM1_ARB_MST_AVAIL_CRED_14 0xD62A58
+
+#define mmNIC2_QM1_ARB_MST_AVAIL_CRED_15 0xD62A5C
+
+#define mmNIC2_QM1_ARB_MST_AVAIL_CRED_16 0xD62A60
+
+#define mmNIC2_QM1_ARB_MST_AVAIL_CRED_17 0xD62A64
+
+#define mmNIC2_QM1_ARB_MST_AVAIL_CRED_18 0xD62A68
+
+#define mmNIC2_QM1_ARB_MST_AVAIL_CRED_19 0xD62A6C
+
+#define mmNIC2_QM1_ARB_MST_AVAIL_CRED_20 0xD62A70
+
+#define mmNIC2_QM1_ARB_MST_AVAIL_CRED_21 0xD62A74
+
+#define mmNIC2_QM1_ARB_MST_AVAIL_CRED_22 0xD62A78
+
+#define mmNIC2_QM1_ARB_MST_AVAIL_CRED_23 0xD62A7C
+
+#define mmNIC2_QM1_ARB_MST_AVAIL_CRED_24 0xD62A80
+
+#define mmNIC2_QM1_ARB_MST_AVAIL_CRED_25 0xD62A84
+
+#define mmNIC2_QM1_ARB_MST_AVAIL_CRED_26 0xD62A88
+
+#define mmNIC2_QM1_ARB_MST_AVAIL_CRED_27 0xD62A8C
+
+#define mmNIC2_QM1_ARB_MST_AVAIL_CRED_28 0xD62A90
+
+#define mmNIC2_QM1_ARB_MST_AVAIL_CRED_29 0xD62A94
+
+#define mmNIC2_QM1_ARB_MST_AVAIL_CRED_30 0xD62A98
+
+#define mmNIC2_QM1_ARB_MST_AVAIL_CRED_31 0xD62A9C
+
+#define mmNIC2_QM1_ARB_MST_CRED_INC 0xD62AA0
+
+#define mmNIC2_QM1_ARB_MST_CHOISE_PUSH_OFST_0 0xD62AA4
+
+#define mmNIC2_QM1_ARB_MST_CHOISE_PUSH_OFST_1 0xD62AA8
+
+#define mmNIC2_QM1_ARB_MST_CHOISE_PUSH_OFST_2 0xD62AAC
+
+#define mmNIC2_QM1_ARB_MST_CHOISE_PUSH_OFST_3 0xD62AB0
+
+#define mmNIC2_QM1_ARB_MST_CHOISE_PUSH_OFST_4 0xD62AB4
+
+#define mmNIC2_QM1_ARB_MST_CHOISE_PUSH_OFST_5 0xD62AB8
+
+#define mmNIC2_QM1_ARB_MST_CHOISE_PUSH_OFST_6 0xD62ABC
+
+#define mmNIC2_QM1_ARB_MST_CHOISE_PUSH_OFST_7 0xD62AC0
+
+#define mmNIC2_QM1_ARB_MST_CHOISE_PUSH_OFST_8 0xD62AC4
+
+#define mmNIC2_QM1_ARB_MST_CHOISE_PUSH_OFST_9 0xD62AC8
+
+#define mmNIC2_QM1_ARB_MST_CHOISE_PUSH_OFST_10 0xD62ACC
+
+#define mmNIC2_QM1_ARB_MST_CHOISE_PUSH_OFST_11 0xD62AD0
+
+#define mmNIC2_QM1_ARB_MST_CHOISE_PUSH_OFST_12 0xD62AD4
+
+#define mmNIC2_QM1_ARB_MST_CHOISE_PUSH_OFST_13 0xD62AD8
+
+#define mmNIC2_QM1_ARB_MST_CHOISE_PUSH_OFST_14 0xD62ADC
+
+#define mmNIC2_QM1_ARB_MST_CHOISE_PUSH_OFST_15 0xD62AE0
+
+#define mmNIC2_QM1_ARB_MST_CHOISE_PUSH_OFST_16 0xD62AE4
+
+#define mmNIC2_QM1_ARB_MST_CHOISE_PUSH_OFST_17 0xD62AE8
+
+#define mmNIC2_QM1_ARB_MST_CHOISE_PUSH_OFST_18 0xD62AEC
+
+#define mmNIC2_QM1_ARB_MST_CHOISE_PUSH_OFST_19 0xD62AF0
+
+#define mmNIC2_QM1_ARB_MST_CHOISE_PUSH_OFST_20 0xD62AF4
+
+#define mmNIC2_QM1_ARB_MST_CHOISE_PUSH_OFST_21 0xD62AF8
+
+#define mmNIC2_QM1_ARB_MST_CHOISE_PUSH_OFST_22 0xD62AFC
+
+#define mmNIC2_QM1_ARB_MST_CHOISE_PUSH_OFST_23 0xD62B00
+
+#define mmNIC2_QM1_ARB_MST_CHOISE_PUSH_OFST_24 0xD62B04
+
+#define mmNIC2_QM1_ARB_MST_CHOISE_PUSH_OFST_25 0xD62B08
+
+#define mmNIC2_QM1_ARB_MST_CHOISE_PUSH_OFST_26 0xD62B0C
+
+#define mmNIC2_QM1_ARB_MST_CHOISE_PUSH_OFST_27 0xD62B10
+
+#define mmNIC2_QM1_ARB_MST_CHOISE_PUSH_OFST_28 0xD62B14
+
+#define mmNIC2_QM1_ARB_MST_CHOISE_PUSH_OFST_29 0xD62B18
+
+#define mmNIC2_QM1_ARB_MST_CHOISE_PUSH_OFST_30 0xD62B1C
+
+#define mmNIC2_QM1_ARB_MST_CHOISE_PUSH_OFST_31 0xD62B20
+
+#define mmNIC2_QM1_ARB_SLV_MASTER_INC_CRED_OFST 0xD62B28
+
+#define mmNIC2_QM1_ARB_MST_SLAVE_EN 0xD62B2C
+
+#define mmNIC2_QM1_ARB_MST_QUIET_PER 0xD62B34
+
+#define mmNIC2_QM1_ARB_SLV_CHOISE_WDT 0xD62B38
+
+#define mmNIC2_QM1_ARB_SLV_ID 0xD62B3C
+
+#define mmNIC2_QM1_ARB_MSG_MAX_INFLIGHT 0xD62B44
+
+#define mmNIC2_QM1_ARB_MSG_AWUSER_31_11 0xD62B48
+
+#define mmNIC2_QM1_ARB_MSG_AWUSER_SEC_PROP 0xD62B4C
+
+#define mmNIC2_QM1_ARB_MSG_AWUSER_NON_SEC_PROP 0xD62B50
+
+#define mmNIC2_QM1_ARB_BASE_LO 0xD62B54
+
+#define mmNIC2_QM1_ARB_BASE_HI 0xD62B58
+
+#define mmNIC2_QM1_ARB_STATE_STS 0xD62B80
+
+#define mmNIC2_QM1_ARB_CHOISE_FULLNESS_STS 0xD62B84
+
+#define mmNIC2_QM1_ARB_MSG_STS 0xD62B88
+
+#define mmNIC2_QM1_ARB_SLV_CHOISE_Q_HEAD 0xD62B8C
+
+#define mmNIC2_QM1_ARB_ERR_CAUSE 0xD62B9C
+
+#define mmNIC2_QM1_ARB_ERR_MSG_EN 0xD62BA0
+
+#define mmNIC2_QM1_ARB_ERR_STS_DRP 0xD62BA8
+
+#define mmNIC2_QM1_ARB_MST_CRED_STS_0 0xD62BB0
+
+#define mmNIC2_QM1_ARB_MST_CRED_STS_1 0xD62BB4
+
+#define mmNIC2_QM1_ARB_MST_CRED_STS_2 0xD62BB8
+
+#define mmNIC2_QM1_ARB_MST_CRED_STS_3 0xD62BBC
+
+#define mmNIC2_QM1_ARB_MST_CRED_STS_4 0xD62BC0
+
+#define mmNIC2_QM1_ARB_MST_CRED_STS_5 0xD62BC4
+
+#define mmNIC2_QM1_ARB_MST_CRED_STS_6 0xD62BC8
+
+#define mmNIC2_QM1_ARB_MST_CRED_STS_7 0xD62BCC
+
+#define mmNIC2_QM1_ARB_MST_CRED_STS_8 0xD62BD0
+
+#define mmNIC2_QM1_ARB_MST_CRED_STS_9 0xD62BD4
+
+#define mmNIC2_QM1_ARB_MST_CRED_STS_10 0xD62BD8
+
+#define mmNIC2_QM1_ARB_MST_CRED_STS_11 0xD62BDC
+
+#define mmNIC2_QM1_ARB_MST_CRED_STS_12 0xD62BE0
+
+#define mmNIC2_QM1_ARB_MST_CRED_STS_13 0xD62BE4
+
+#define mmNIC2_QM1_ARB_MST_CRED_STS_14 0xD62BE8
+
+#define mmNIC2_QM1_ARB_MST_CRED_STS_15 0xD62BEC
+
+#define mmNIC2_QM1_ARB_MST_CRED_STS_16 0xD62BF0
+
+#define mmNIC2_QM1_ARB_MST_CRED_STS_17 0xD62BF4
+
+#define mmNIC2_QM1_ARB_MST_CRED_STS_18 0xD62BF8
+
+#define mmNIC2_QM1_ARB_MST_CRED_STS_19 0xD62BFC
+
+#define mmNIC2_QM1_ARB_MST_CRED_STS_20 0xD62C00
+
+#define mmNIC2_QM1_ARB_MST_CRED_STS_21 0xD62C04
+
+#define mmNIC2_QM1_ARB_MST_CRED_STS_22 0xD62C08
+
+#define mmNIC2_QM1_ARB_MST_CRED_STS_23 0xD62C0C
+
+#define mmNIC2_QM1_ARB_MST_CRED_STS_24 0xD62C10
+
+#define mmNIC2_QM1_ARB_MST_CRED_STS_25 0xD62C14
+
+#define mmNIC2_QM1_ARB_MST_CRED_STS_26 0xD62C18
+
+#define mmNIC2_QM1_ARB_MST_CRED_STS_27 0xD62C1C
+
+#define mmNIC2_QM1_ARB_MST_CRED_STS_28 0xD62C20
+
+#define mmNIC2_QM1_ARB_MST_CRED_STS_29 0xD62C24
+
+#define mmNIC2_QM1_ARB_MST_CRED_STS_30 0xD62C28
+
+#define mmNIC2_QM1_ARB_MST_CRED_STS_31 0xD62C2C
+
+#define mmNIC2_QM1_CGM_CFG 0xD62C70
+
+#define mmNIC2_QM1_CGM_STS 0xD62C74
+
+#define mmNIC2_QM1_CGM_CFG1 0xD62C78
+
+#define mmNIC2_QM1_LOCAL_RANGE_BASE 0xD62C80
+
+#define mmNIC2_QM1_LOCAL_RANGE_SIZE 0xD62C84
+
+#define mmNIC2_QM1_CSMR_STRICT_PRIO_CFG 0xD62C90
+
+#define mmNIC2_QM1_HBW_RD_RATE_LIM_CFG_1 0xD62C94
+
+#define mmNIC2_QM1_LBW_WR_RATE_LIM_CFG_0 0xD62C98
+
+#define mmNIC2_QM1_LBW_WR_RATE_LIM_CFG_1 0xD62C9C
+
+#define mmNIC2_QM1_HBW_RD_RATE_LIM_CFG_0 0xD62CA0
+
+#define mmNIC2_QM1_GLBL_AXCACHE 0xD62CA4
+
+#define mmNIC2_QM1_IND_GW_APB_CFG 0xD62CB0
+
+#define mmNIC2_QM1_IND_GW_APB_WDATA 0xD62CB4
+
+#define mmNIC2_QM1_IND_GW_APB_RDATA 0xD62CB8
+
+#define mmNIC2_QM1_IND_GW_APB_STATUS 0xD62CBC
+
+#define mmNIC2_QM1_GLBL_ERR_ADDR_LO 0xD62CD0
+
+#define mmNIC2_QM1_GLBL_ERR_ADDR_HI 0xD62CD4
+
+#define mmNIC2_QM1_GLBL_ERR_WDATA 0xD62CD8
+
+#define mmNIC2_QM1_GLBL_MEM_INIT_BUSY 0xD62D00
+
+#endif /* ASIC_REG_NIC2_QM1_REGS_H_ */
diff --git a/drivers/accel/habanalabs/include/gaudi/asic_reg/nic3_qm0_regs.h b/drivers/accel/habanalabs/include/gaudi/asic_reg/nic3_qm0_regs.h
new file mode 100644
index 0000000000..4712cc62b0
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi/asic_reg/nic3_qm0_regs.h
@@ -0,0 +1,834 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2016-2018 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ ** DO NOT EDIT BELOW **
+ ************************************/
+
+#ifndef ASIC_REG_NIC3_QM0_REGS_H_
+#define ASIC_REG_NIC3_QM0_REGS_H_
+
+/*
+ *****************************************
+ * NIC3_QM0 (Prototype: QMAN)
+ *****************************************
+ */
+
+#define mmNIC3_QM0_GLBL_CFG0 0xDA0000
+
+#define mmNIC3_QM0_GLBL_CFG1 0xDA0004
+
+#define mmNIC3_QM0_GLBL_PROT 0xDA0008
+
+#define mmNIC3_QM0_GLBL_ERR_CFG 0xDA000C
+
+#define mmNIC3_QM0_GLBL_SECURE_PROPS_0 0xDA0010
+
+#define mmNIC3_QM0_GLBL_SECURE_PROPS_1 0xDA0014
+
+#define mmNIC3_QM0_GLBL_SECURE_PROPS_2 0xDA0018
+
+#define mmNIC3_QM0_GLBL_SECURE_PROPS_3 0xDA001C
+
+#define mmNIC3_QM0_GLBL_SECURE_PROPS_4 0xDA0020
+
+#define mmNIC3_QM0_GLBL_NON_SECURE_PROPS_0 0xDA0024
+
+#define mmNIC3_QM0_GLBL_NON_SECURE_PROPS_1 0xDA0028
+
+#define mmNIC3_QM0_GLBL_NON_SECURE_PROPS_2 0xDA002C
+
+#define mmNIC3_QM0_GLBL_NON_SECURE_PROPS_3 0xDA0030
+
+#define mmNIC3_QM0_GLBL_NON_SECURE_PROPS_4 0xDA0034
+
+#define mmNIC3_QM0_GLBL_STS0 0xDA0038
+
+#define mmNIC3_QM0_GLBL_STS1_0 0xDA0040
+
+#define mmNIC3_QM0_GLBL_STS1_1 0xDA0044
+
+#define mmNIC3_QM0_GLBL_STS1_2 0xDA0048
+
+#define mmNIC3_QM0_GLBL_STS1_3 0xDA004C
+
+#define mmNIC3_QM0_GLBL_STS1_4 0xDA0050
+
+#define mmNIC3_QM0_GLBL_MSG_EN_0 0xDA0054
+
+#define mmNIC3_QM0_GLBL_MSG_EN_1 0xDA0058
+
+#define mmNIC3_QM0_GLBL_MSG_EN_2 0xDA005C
+
+#define mmNIC3_QM0_GLBL_MSG_EN_3 0xDA0060
+
+#define mmNIC3_QM0_GLBL_MSG_EN_4 0xDA0068
+
+#define mmNIC3_QM0_PQ_BASE_LO_0 0xDA0070
+
+#define mmNIC3_QM0_PQ_BASE_LO_1 0xDA0074
+
+#define mmNIC3_QM0_PQ_BASE_LO_2 0xDA0078
+
+#define mmNIC3_QM0_PQ_BASE_LO_3 0xDA007C
+
+#define mmNIC3_QM0_PQ_BASE_HI_0 0xDA0080
+
+#define mmNIC3_QM0_PQ_BASE_HI_1 0xDA0084
+
+#define mmNIC3_QM0_PQ_BASE_HI_2 0xDA0088
+
+#define mmNIC3_QM0_PQ_BASE_HI_3 0xDA008C
+
+#define mmNIC3_QM0_PQ_SIZE_0 0xDA0090
+
+#define mmNIC3_QM0_PQ_SIZE_1 0xDA0094
+
+#define mmNIC3_QM0_PQ_SIZE_2 0xDA0098
+
+#define mmNIC3_QM0_PQ_SIZE_3 0xDA009C
+
+#define mmNIC3_QM0_PQ_PI_0 0xDA00A0
+
+#define mmNIC3_QM0_PQ_PI_1 0xDA00A4
+
+#define mmNIC3_QM0_PQ_PI_2 0xDA00A8
+
+#define mmNIC3_QM0_PQ_PI_3 0xDA00AC
+
+#define mmNIC3_QM0_PQ_CI_0 0xDA00B0
+
+#define mmNIC3_QM0_PQ_CI_1 0xDA00B4
+
+#define mmNIC3_QM0_PQ_CI_2 0xDA00B8
+
+#define mmNIC3_QM0_PQ_CI_3 0xDA00BC
+
+#define mmNIC3_QM0_PQ_CFG0_0 0xDA00C0
+
+#define mmNIC3_QM0_PQ_CFG0_1 0xDA00C4
+
+#define mmNIC3_QM0_PQ_CFG0_2 0xDA00C8
+
+#define mmNIC3_QM0_PQ_CFG0_3 0xDA00CC
+
+#define mmNIC3_QM0_PQ_CFG1_0 0xDA00D0
+
+#define mmNIC3_QM0_PQ_CFG1_1 0xDA00D4
+
+#define mmNIC3_QM0_PQ_CFG1_2 0xDA00D8
+
+#define mmNIC3_QM0_PQ_CFG1_3 0xDA00DC
+
+#define mmNIC3_QM0_PQ_ARUSER_31_11_0 0xDA00E0
+
+#define mmNIC3_QM0_PQ_ARUSER_31_11_1 0xDA00E4
+
+#define mmNIC3_QM0_PQ_ARUSER_31_11_2 0xDA00E8
+
+#define mmNIC3_QM0_PQ_ARUSER_31_11_3 0xDA00EC
+
+#define mmNIC3_QM0_PQ_STS0_0 0xDA00F0
+
+#define mmNIC3_QM0_PQ_STS0_1 0xDA00F4
+
+#define mmNIC3_QM0_PQ_STS0_2 0xDA00F8
+
+#define mmNIC3_QM0_PQ_STS0_3 0xDA00FC
+
+#define mmNIC3_QM0_PQ_STS1_0 0xDA0100
+
+#define mmNIC3_QM0_PQ_STS1_1 0xDA0104
+
+#define mmNIC3_QM0_PQ_STS1_2 0xDA0108
+
+#define mmNIC3_QM0_PQ_STS1_3 0xDA010C
+
+#define mmNIC3_QM0_CQ_CFG0_0 0xDA0110
+
+#define mmNIC3_QM0_CQ_CFG0_1 0xDA0114
+
+#define mmNIC3_QM0_CQ_CFG0_2 0xDA0118
+
+#define mmNIC3_QM0_CQ_CFG0_3 0xDA011C
+
+#define mmNIC3_QM0_CQ_CFG0_4 0xDA0120
+
+#define mmNIC3_QM0_CQ_CFG1_0 0xDA0124
+
+#define mmNIC3_QM0_CQ_CFG1_1 0xDA0128
+
+#define mmNIC3_QM0_CQ_CFG1_2 0xDA012C
+
+#define mmNIC3_QM0_CQ_CFG1_3 0xDA0130
+
+#define mmNIC3_QM0_CQ_CFG1_4 0xDA0134
+
+#define mmNIC3_QM0_CQ_ARUSER_31_11_0 0xDA0138
+
+#define mmNIC3_QM0_CQ_ARUSER_31_11_1 0xDA013C
+
+#define mmNIC3_QM0_CQ_ARUSER_31_11_2 0xDA0140
+
+#define mmNIC3_QM0_CQ_ARUSER_31_11_3 0xDA0144
+
+#define mmNIC3_QM0_CQ_ARUSER_31_11_4 0xDA0148
+
+#define mmNIC3_QM0_CQ_STS0_0 0xDA014C
+
+#define mmNIC3_QM0_CQ_STS0_1 0xDA0150
+
+#define mmNIC3_QM0_CQ_STS0_2 0xDA0154
+
+#define mmNIC3_QM0_CQ_STS0_3 0xDA0158
+
+#define mmNIC3_QM0_CQ_STS0_4 0xDA015C
+
+#define mmNIC3_QM0_CQ_STS1_0 0xDA0160
+
+#define mmNIC3_QM0_CQ_STS1_1 0xDA0164
+
+#define mmNIC3_QM0_CQ_STS1_2 0xDA0168
+
+#define mmNIC3_QM0_CQ_STS1_3 0xDA016C
+
+#define mmNIC3_QM0_CQ_STS1_4 0xDA0170
+
+#define mmNIC3_QM0_CQ_PTR_LO_0 0xDA0174
+
+#define mmNIC3_QM0_CQ_PTR_HI_0 0xDA0178
+
+#define mmNIC3_QM0_CQ_TSIZE_0 0xDA017C
+
+#define mmNIC3_QM0_CQ_CTL_0 0xDA0180
+
+#define mmNIC3_QM0_CQ_PTR_LO_1 0xDA0184
+
+#define mmNIC3_QM0_CQ_PTR_HI_1 0xDA0188
+
+#define mmNIC3_QM0_CQ_TSIZE_1 0xDA018C
+
+#define mmNIC3_QM0_CQ_CTL_1 0xDA0190
+
+#define mmNIC3_QM0_CQ_PTR_LO_2 0xDA0194
+
+#define mmNIC3_QM0_CQ_PTR_HI_2 0xDA0198
+
+#define mmNIC3_QM0_CQ_TSIZE_2 0xDA019C
+
+#define mmNIC3_QM0_CQ_CTL_2 0xDA01A0
+
+#define mmNIC3_QM0_CQ_PTR_LO_3 0xDA01A4
+
+#define mmNIC3_QM0_CQ_PTR_HI_3 0xDA01A8
+
+#define mmNIC3_QM0_CQ_TSIZE_3 0xDA01AC
+
+#define mmNIC3_QM0_CQ_CTL_3 0xDA01B0
+
+#define mmNIC3_QM0_CQ_PTR_LO_4 0xDA01B4
+
+#define mmNIC3_QM0_CQ_PTR_HI_4 0xDA01B8
+
+#define mmNIC3_QM0_CQ_TSIZE_4 0xDA01BC
+
+#define mmNIC3_QM0_CQ_CTL_4 0xDA01C0
+
+#define mmNIC3_QM0_CQ_PTR_LO_STS_0 0xDA01C4
+
+#define mmNIC3_QM0_CQ_PTR_LO_STS_1 0xDA01C8
+
+#define mmNIC3_QM0_CQ_PTR_LO_STS_2 0xDA01CC
+
+#define mmNIC3_QM0_CQ_PTR_LO_STS_3 0xDA01D0
+
+#define mmNIC3_QM0_CQ_PTR_LO_STS_4 0xDA01D4
+
+#define mmNIC3_QM0_CQ_PTR_HI_STS_0 0xDA01D8
+
+#define mmNIC3_QM0_CQ_PTR_HI_STS_1 0xDA01DC
+
+#define mmNIC3_QM0_CQ_PTR_HI_STS_2 0xDA01E0
+
+#define mmNIC3_QM0_CQ_PTR_HI_STS_3 0xDA01E4
+
+#define mmNIC3_QM0_CQ_PTR_HI_STS_4 0xDA01E8
+
+#define mmNIC3_QM0_CQ_TSIZE_STS_0 0xDA01EC
+
+#define mmNIC3_QM0_CQ_TSIZE_STS_1 0xDA01F0
+
+#define mmNIC3_QM0_CQ_TSIZE_STS_2 0xDA01F4
+
+#define mmNIC3_QM0_CQ_TSIZE_STS_3 0xDA01F8
+
+#define mmNIC3_QM0_CQ_TSIZE_STS_4 0xDA01FC
+
+#define mmNIC3_QM0_CQ_CTL_STS_0 0xDA0200
+
+#define mmNIC3_QM0_CQ_CTL_STS_1 0xDA0204
+
+#define mmNIC3_QM0_CQ_CTL_STS_2 0xDA0208
+
+#define mmNIC3_QM0_CQ_CTL_STS_3 0xDA020C
+
+#define mmNIC3_QM0_CQ_CTL_STS_4 0xDA0210
+
+#define mmNIC3_QM0_CQ_IFIFO_CNT_0 0xDA0214
+
+#define mmNIC3_QM0_CQ_IFIFO_CNT_1 0xDA0218
+
+#define mmNIC3_QM0_CQ_IFIFO_CNT_2 0xDA021C
+
+#define mmNIC3_QM0_CQ_IFIFO_CNT_3 0xDA0220
+
+#define mmNIC3_QM0_CQ_IFIFO_CNT_4 0xDA0224
+
+#define mmNIC3_QM0_CP_MSG_BASE0_ADDR_LO_0 0xDA0228
+
+#define mmNIC3_QM0_CP_MSG_BASE0_ADDR_LO_1 0xDA022C
+
+#define mmNIC3_QM0_CP_MSG_BASE0_ADDR_LO_2 0xDA0230
+
+#define mmNIC3_QM0_CP_MSG_BASE0_ADDR_LO_3 0xDA0234
+
+#define mmNIC3_QM0_CP_MSG_BASE0_ADDR_LO_4 0xDA0238
+
+#define mmNIC3_QM0_CP_MSG_BASE0_ADDR_HI_0 0xDA023C
+
+#define mmNIC3_QM0_CP_MSG_BASE0_ADDR_HI_1 0xDA0240
+
+#define mmNIC3_QM0_CP_MSG_BASE0_ADDR_HI_2 0xDA0244
+
+#define mmNIC3_QM0_CP_MSG_BASE0_ADDR_HI_3 0xDA0248
+
+#define mmNIC3_QM0_CP_MSG_BASE0_ADDR_HI_4 0xDA024C
+
+#define mmNIC3_QM0_CP_MSG_BASE1_ADDR_LO_0 0xDA0250
+
+#define mmNIC3_QM0_CP_MSG_BASE1_ADDR_LO_1 0xDA0254
+
+#define mmNIC3_QM0_CP_MSG_BASE1_ADDR_LO_2 0xDA0258
+
+#define mmNIC3_QM0_CP_MSG_BASE1_ADDR_LO_3 0xDA025C
+
+#define mmNIC3_QM0_CP_MSG_BASE1_ADDR_LO_4 0xDA0260
+
+#define mmNIC3_QM0_CP_MSG_BASE1_ADDR_HI_0 0xDA0264
+
+#define mmNIC3_QM0_CP_MSG_BASE1_ADDR_HI_1 0xDA0268
+
+#define mmNIC3_QM0_CP_MSG_BASE1_ADDR_HI_2 0xDA026C
+
+#define mmNIC3_QM0_CP_MSG_BASE1_ADDR_HI_3 0xDA0270
+
+#define mmNIC3_QM0_CP_MSG_BASE1_ADDR_HI_4 0xDA0274
+
+#define mmNIC3_QM0_CP_MSG_BASE2_ADDR_LO_0 0xDA0278
+
+#define mmNIC3_QM0_CP_MSG_BASE2_ADDR_LO_1 0xDA027C
+
+#define mmNIC3_QM0_CP_MSG_BASE2_ADDR_LO_2 0xDA0280
+
+#define mmNIC3_QM0_CP_MSG_BASE2_ADDR_LO_3 0xDA0284
+
+#define mmNIC3_QM0_CP_MSG_BASE2_ADDR_LO_4 0xDA0288
+
+#define mmNIC3_QM0_CP_MSG_BASE2_ADDR_HI_0 0xDA028C
+
+#define mmNIC3_QM0_CP_MSG_BASE2_ADDR_HI_1 0xDA0290
+
+#define mmNIC3_QM0_CP_MSG_BASE2_ADDR_HI_2 0xDA0294
+
+#define mmNIC3_QM0_CP_MSG_BASE2_ADDR_HI_3 0xDA0298
+
+#define mmNIC3_QM0_CP_MSG_BASE2_ADDR_HI_4 0xDA029C
+
+#define mmNIC3_QM0_CP_MSG_BASE3_ADDR_LO_0 0xDA02A0
+
+#define mmNIC3_QM0_CP_MSG_BASE3_ADDR_LO_1 0xDA02A4
+
+#define mmNIC3_QM0_CP_MSG_BASE3_ADDR_LO_2 0xDA02A8
+
+#define mmNIC3_QM0_CP_MSG_BASE3_ADDR_LO_3 0xDA02AC
+
+#define mmNIC3_QM0_CP_MSG_BASE3_ADDR_LO_4 0xDA02B0
+
+#define mmNIC3_QM0_CP_MSG_BASE3_ADDR_HI_0 0xDA02B4
+
+#define mmNIC3_QM0_CP_MSG_BASE3_ADDR_HI_1 0xDA02B8
+
+#define mmNIC3_QM0_CP_MSG_BASE3_ADDR_HI_2 0xDA02BC
+
+#define mmNIC3_QM0_CP_MSG_BASE3_ADDR_HI_3 0xDA02C0
+
+#define mmNIC3_QM0_CP_MSG_BASE3_ADDR_HI_4 0xDA02C4
+
+#define mmNIC3_QM0_CP_LDMA_TSIZE_OFFSET_0 0xDA02C8
+
+#define mmNIC3_QM0_CP_LDMA_TSIZE_OFFSET_1 0xDA02CC
+
+#define mmNIC3_QM0_CP_LDMA_TSIZE_OFFSET_2 0xDA02D0
+
+#define mmNIC3_QM0_CP_LDMA_TSIZE_OFFSET_3 0xDA02D4
+
+#define mmNIC3_QM0_CP_LDMA_TSIZE_OFFSET_4 0xDA02D8
+
+#define mmNIC3_QM0_CP_LDMA_SRC_BASE_LO_OFFSET_0 0xDA02E0
+
+#define mmNIC3_QM0_CP_LDMA_SRC_BASE_LO_OFFSET_1 0xDA02E4
+
+#define mmNIC3_QM0_CP_LDMA_SRC_BASE_LO_OFFSET_2 0xDA02E8
+
+#define mmNIC3_QM0_CP_LDMA_SRC_BASE_LO_OFFSET_3 0xDA02EC
+
+#define mmNIC3_QM0_CP_LDMA_SRC_BASE_LO_OFFSET_4 0xDA02F0
+
+#define mmNIC3_QM0_CP_LDMA_DST_BASE_LO_OFFSET_0 0xDA02F4
+
+#define mmNIC3_QM0_CP_LDMA_DST_BASE_LO_OFFSET_1 0xDA02F8
+
+#define mmNIC3_QM0_CP_LDMA_DST_BASE_LO_OFFSET_2 0xDA02FC
+
+#define mmNIC3_QM0_CP_LDMA_DST_BASE_LO_OFFSET_3 0xDA0300
+
+#define mmNIC3_QM0_CP_LDMA_DST_BASE_LO_OFFSET_4 0xDA0304
+
+#define mmNIC3_QM0_CP_FENCE0_RDATA_0 0xDA0308
+
+#define mmNIC3_QM0_CP_FENCE0_RDATA_1 0xDA030C
+
+#define mmNIC3_QM0_CP_FENCE0_RDATA_2 0xDA0310
+
+#define mmNIC3_QM0_CP_FENCE0_RDATA_3 0xDA0314
+
+#define mmNIC3_QM0_CP_FENCE0_RDATA_4 0xDA0318
+
+#define mmNIC3_QM0_CP_FENCE1_RDATA_0 0xDA031C
+
+#define mmNIC3_QM0_CP_FENCE1_RDATA_1 0xDA0320
+
+#define mmNIC3_QM0_CP_FENCE1_RDATA_2 0xDA0324
+
+#define mmNIC3_QM0_CP_FENCE1_RDATA_3 0xDA0328
+
+#define mmNIC3_QM0_CP_FENCE1_RDATA_4 0xDA032C
+
+#define mmNIC3_QM0_CP_FENCE2_RDATA_0 0xDA0330
+
+#define mmNIC3_QM0_CP_FENCE2_RDATA_1 0xDA0334
+
+#define mmNIC3_QM0_CP_FENCE2_RDATA_2 0xDA0338
+
+#define mmNIC3_QM0_CP_FENCE2_RDATA_3 0xDA033C
+
+#define mmNIC3_QM0_CP_FENCE2_RDATA_4 0xDA0340
+
+#define mmNIC3_QM0_CP_FENCE3_RDATA_0 0xDA0344
+
+#define mmNIC3_QM0_CP_FENCE3_RDATA_1 0xDA0348
+
+#define mmNIC3_QM0_CP_FENCE3_RDATA_2 0xDA034C
+
+#define mmNIC3_QM0_CP_FENCE3_RDATA_3 0xDA0350
+
+#define mmNIC3_QM0_CP_FENCE3_RDATA_4 0xDA0354
+
+#define mmNIC3_QM0_CP_FENCE0_CNT_0 0xDA0358
+
+#define mmNIC3_QM0_CP_FENCE0_CNT_1 0xDA035C
+
+#define mmNIC3_QM0_CP_FENCE0_CNT_2 0xDA0360
+
+#define mmNIC3_QM0_CP_FENCE0_CNT_3 0xDA0364
+
+#define mmNIC3_QM0_CP_FENCE0_CNT_4 0xDA0368
+
+#define mmNIC3_QM0_CP_FENCE1_CNT_0 0xDA036C
+
+#define mmNIC3_QM0_CP_FENCE1_CNT_1 0xDA0370
+
+#define mmNIC3_QM0_CP_FENCE1_CNT_2 0xDA0374
+
+#define mmNIC3_QM0_CP_FENCE1_CNT_3 0xDA0378
+
+#define mmNIC3_QM0_CP_FENCE1_CNT_4 0xDA037C
+
+#define mmNIC3_QM0_CP_FENCE2_CNT_0 0xDA0380
+
+#define mmNIC3_QM0_CP_FENCE2_CNT_1 0xDA0384
+
+#define mmNIC3_QM0_CP_FENCE2_CNT_2 0xDA0388
+
+#define mmNIC3_QM0_CP_FENCE2_CNT_3 0xDA038C
+
+#define mmNIC3_QM0_CP_FENCE2_CNT_4 0xDA0390
+
+#define mmNIC3_QM0_CP_FENCE3_CNT_0 0xDA0394
+
+#define mmNIC3_QM0_CP_FENCE3_CNT_1 0xDA0398
+
+#define mmNIC3_QM0_CP_FENCE3_CNT_2 0xDA039C
+
+#define mmNIC3_QM0_CP_FENCE3_CNT_3 0xDA03A0
+
+#define mmNIC3_QM0_CP_FENCE3_CNT_4 0xDA03A4
+
+#define mmNIC3_QM0_CP_STS_0 0xDA03A8
+
+#define mmNIC3_QM0_CP_STS_1 0xDA03AC
+
+#define mmNIC3_QM0_CP_STS_2 0xDA03B0
+
+#define mmNIC3_QM0_CP_STS_3 0xDA03B4
+
+#define mmNIC3_QM0_CP_STS_4 0xDA03B8
+
+#define mmNIC3_QM0_CP_CURRENT_INST_LO_0 0xDA03BC
+
+#define mmNIC3_QM0_CP_CURRENT_INST_LO_1 0xDA03C0
+
+#define mmNIC3_QM0_CP_CURRENT_INST_LO_2 0xDA03C4
+
+#define mmNIC3_QM0_CP_CURRENT_INST_LO_3 0xDA03C8
+
+#define mmNIC3_QM0_CP_CURRENT_INST_LO_4 0xDA03CC
+
+#define mmNIC3_QM0_CP_CURRENT_INST_HI_0 0xDA03D0
+
+#define mmNIC3_QM0_CP_CURRENT_INST_HI_1 0xDA03D4
+
+#define mmNIC3_QM0_CP_CURRENT_INST_HI_2 0xDA03D8
+
+#define mmNIC3_QM0_CP_CURRENT_INST_HI_3 0xDA03DC
+
+#define mmNIC3_QM0_CP_CURRENT_INST_HI_4 0xDA03E0
+
+#define mmNIC3_QM0_CP_BARRIER_CFG_0 0xDA03F4
+
+#define mmNIC3_QM0_CP_BARRIER_CFG_1 0xDA03F8
+
+#define mmNIC3_QM0_CP_BARRIER_CFG_2 0xDA03FC
+
+#define mmNIC3_QM0_CP_BARRIER_CFG_3 0xDA0400
+
+#define mmNIC3_QM0_CP_BARRIER_CFG_4 0xDA0404
+
+#define mmNIC3_QM0_CP_DBG_0_0 0xDA0408
+
+#define mmNIC3_QM0_CP_DBG_0_1 0xDA040C
+
+#define mmNIC3_QM0_CP_DBG_0_2 0xDA0410
+
+#define mmNIC3_QM0_CP_DBG_0_3 0xDA0414
+
+#define mmNIC3_QM0_CP_DBG_0_4 0xDA0418
+
+#define mmNIC3_QM0_CP_ARUSER_31_11_0 0xDA041C
+
+#define mmNIC3_QM0_CP_ARUSER_31_11_1 0xDA0420
+
+#define mmNIC3_QM0_CP_ARUSER_31_11_2 0xDA0424
+
+#define mmNIC3_QM0_CP_ARUSER_31_11_3 0xDA0428
+
+#define mmNIC3_QM0_CP_ARUSER_31_11_4 0xDA042C
+
+#define mmNIC3_QM0_CP_AWUSER_31_11_0 0xDA0430
+
+#define mmNIC3_QM0_CP_AWUSER_31_11_1 0xDA0434
+
+#define mmNIC3_QM0_CP_AWUSER_31_11_2 0xDA0438
+
+#define mmNIC3_QM0_CP_AWUSER_31_11_3 0xDA043C
+
+#define mmNIC3_QM0_CP_AWUSER_31_11_4 0xDA0440
+
+#define mmNIC3_QM0_ARB_CFG_0 0xDA0A00
+
+#define mmNIC3_QM0_ARB_CHOISE_Q_PUSH 0xDA0A04
+
+#define mmNIC3_QM0_ARB_WRR_WEIGHT_0 0xDA0A08
+
+#define mmNIC3_QM0_ARB_WRR_WEIGHT_1 0xDA0A0C
+
+#define mmNIC3_QM0_ARB_WRR_WEIGHT_2 0xDA0A10
+
+#define mmNIC3_QM0_ARB_WRR_WEIGHT_3 0xDA0A14
+
+#define mmNIC3_QM0_ARB_CFG_1 0xDA0A18
+
+#define mmNIC3_QM0_ARB_MST_AVAIL_CRED_0 0xDA0A20
+
+#define mmNIC3_QM0_ARB_MST_AVAIL_CRED_1 0xDA0A24
+
+#define mmNIC3_QM0_ARB_MST_AVAIL_CRED_2 0xDA0A28
+
+#define mmNIC3_QM0_ARB_MST_AVAIL_CRED_3 0xDA0A2C
+
+#define mmNIC3_QM0_ARB_MST_AVAIL_CRED_4 0xDA0A30
+
+#define mmNIC3_QM0_ARB_MST_AVAIL_CRED_5 0xDA0A34
+
+#define mmNIC3_QM0_ARB_MST_AVAIL_CRED_6 0xDA0A38
+
+#define mmNIC3_QM0_ARB_MST_AVAIL_CRED_7 0xDA0A3C
+
+#define mmNIC3_QM0_ARB_MST_AVAIL_CRED_8 0xDA0A40
+
+#define mmNIC3_QM0_ARB_MST_AVAIL_CRED_9 0xDA0A44
+
+#define mmNIC3_QM0_ARB_MST_AVAIL_CRED_10 0xDA0A48
+
+#define mmNIC3_QM0_ARB_MST_AVAIL_CRED_11 0xDA0A4C
+
+#define mmNIC3_QM0_ARB_MST_AVAIL_CRED_12 0xDA0A50
+
+#define mmNIC3_QM0_ARB_MST_AVAIL_CRED_13 0xDA0A54
+
+#define mmNIC3_QM0_ARB_MST_AVAIL_CRED_14 0xDA0A58
+
+#define mmNIC3_QM0_ARB_MST_AVAIL_CRED_15 0xDA0A5C
+
+#define mmNIC3_QM0_ARB_MST_AVAIL_CRED_16 0xDA0A60
+
+#define mmNIC3_QM0_ARB_MST_AVAIL_CRED_17 0xDA0A64
+
+#define mmNIC3_QM0_ARB_MST_AVAIL_CRED_18 0xDA0A68
+
+#define mmNIC3_QM0_ARB_MST_AVAIL_CRED_19 0xDA0A6C
+
+#define mmNIC3_QM0_ARB_MST_AVAIL_CRED_20 0xDA0A70
+
+#define mmNIC3_QM0_ARB_MST_AVAIL_CRED_21 0xDA0A74
+
+#define mmNIC3_QM0_ARB_MST_AVAIL_CRED_22 0xDA0A78
+
+#define mmNIC3_QM0_ARB_MST_AVAIL_CRED_23 0xDA0A7C
+
+#define mmNIC3_QM0_ARB_MST_AVAIL_CRED_24 0xDA0A80
+
+#define mmNIC3_QM0_ARB_MST_AVAIL_CRED_25 0xDA0A84
+
+#define mmNIC3_QM0_ARB_MST_AVAIL_CRED_26 0xDA0A88
+
+#define mmNIC3_QM0_ARB_MST_AVAIL_CRED_27 0xDA0A8C
+
+#define mmNIC3_QM0_ARB_MST_AVAIL_CRED_28 0xDA0A90
+
+#define mmNIC3_QM0_ARB_MST_AVAIL_CRED_29 0xDA0A94
+
+#define mmNIC3_QM0_ARB_MST_AVAIL_CRED_30 0xDA0A98
+
+#define mmNIC3_QM0_ARB_MST_AVAIL_CRED_31 0xDA0A9C
+
+#define mmNIC3_QM0_ARB_MST_CRED_INC 0xDA0AA0
+
+#define mmNIC3_QM0_ARB_MST_CHOISE_PUSH_OFST_0 0xDA0AA4
+
+#define mmNIC3_QM0_ARB_MST_CHOISE_PUSH_OFST_1 0xDA0AA8
+
+#define mmNIC3_QM0_ARB_MST_CHOISE_PUSH_OFST_2 0xDA0AAC
+
+#define mmNIC3_QM0_ARB_MST_CHOISE_PUSH_OFST_3 0xDA0AB0
+
+#define mmNIC3_QM0_ARB_MST_CHOISE_PUSH_OFST_4 0xDA0AB4
+
+#define mmNIC3_QM0_ARB_MST_CHOISE_PUSH_OFST_5 0xDA0AB8
+
+#define mmNIC3_QM0_ARB_MST_CHOISE_PUSH_OFST_6 0xDA0ABC
+
+#define mmNIC3_QM0_ARB_MST_CHOISE_PUSH_OFST_7 0xDA0AC0
+
+#define mmNIC3_QM0_ARB_MST_CHOISE_PUSH_OFST_8 0xDA0AC4
+
+#define mmNIC3_QM0_ARB_MST_CHOISE_PUSH_OFST_9 0xDA0AC8
+
+#define mmNIC3_QM0_ARB_MST_CHOISE_PUSH_OFST_10 0xDA0ACC
+
+#define mmNIC3_QM0_ARB_MST_CHOISE_PUSH_OFST_11 0xDA0AD0
+
+#define mmNIC3_QM0_ARB_MST_CHOISE_PUSH_OFST_12 0xDA0AD4
+
+#define mmNIC3_QM0_ARB_MST_CHOISE_PUSH_OFST_13 0xDA0AD8
+
+#define mmNIC3_QM0_ARB_MST_CHOISE_PUSH_OFST_14 0xDA0ADC
+
+#define mmNIC3_QM0_ARB_MST_CHOISE_PUSH_OFST_15 0xDA0AE0
+
+#define mmNIC3_QM0_ARB_MST_CHOISE_PUSH_OFST_16 0xDA0AE4
+
+#define mmNIC3_QM0_ARB_MST_CHOISE_PUSH_OFST_17 0xDA0AE8
+
+#define mmNIC3_QM0_ARB_MST_CHOISE_PUSH_OFST_18 0xDA0AEC
+
+#define mmNIC3_QM0_ARB_MST_CHOISE_PUSH_OFST_19 0xDA0AF0
+
+#define mmNIC3_QM0_ARB_MST_CHOISE_PUSH_OFST_20 0xDA0AF4
+
+#define mmNIC3_QM0_ARB_MST_CHOISE_PUSH_OFST_21 0xDA0AF8
+
+#define mmNIC3_QM0_ARB_MST_CHOISE_PUSH_OFST_22 0xDA0AFC
+
+#define mmNIC3_QM0_ARB_MST_CHOISE_PUSH_OFST_23 0xDA0B00
+
+#define mmNIC3_QM0_ARB_MST_CHOISE_PUSH_OFST_24 0xDA0B04
+
+#define mmNIC3_QM0_ARB_MST_CHOISE_PUSH_OFST_25 0xDA0B08
+
+#define mmNIC3_QM0_ARB_MST_CHOISE_PUSH_OFST_26 0xDA0B0C
+
+#define mmNIC3_QM0_ARB_MST_CHOISE_PUSH_OFST_27 0xDA0B10
+
+#define mmNIC3_QM0_ARB_MST_CHOISE_PUSH_OFST_28 0xDA0B14
+
+#define mmNIC3_QM0_ARB_MST_CHOISE_PUSH_OFST_29 0xDA0B18
+
+#define mmNIC3_QM0_ARB_MST_CHOISE_PUSH_OFST_30 0xDA0B1C
+
+#define mmNIC3_QM0_ARB_MST_CHOISE_PUSH_OFST_31 0xDA0B20
+
+#define mmNIC3_QM0_ARB_SLV_MASTER_INC_CRED_OFST 0xDA0B28
+
+#define mmNIC3_QM0_ARB_MST_SLAVE_EN 0xDA0B2C
+
+#define mmNIC3_QM0_ARB_MST_QUIET_PER 0xDA0B34
+
+#define mmNIC3_QM0_ARB_SLV_CHOISE_WDT 0xDA0B38
+
+#define mmNIC3_QM0_ARB_SLV_ID 0xDA0B3C
+
+#define mmNIC3_QM0_ARB_MSG_MAX_INFLIGHT 0xDA0B44
+
+#define mmNIC3_QM0_ARB_MSG_AWUSER_31_11 0xDA0B48
+
+#define mmNIC3_QM0_ARB_MSG_AWUSER_SEC_PROP 0xDA0B4C
+
+#define mmNIC3_QM0_ARB_MSG_AWUSER_NON_SEC_PROP 0xDA0B50
+
+#define mmNIC3_QM0_ARB_BASE_LO 0xDA0B54
+
+#define mmNIC3_QM0_ARB_BASE_HI 0xDA0B58
+
+#define mmNIC3_QM0_ARB_STATE_STS 0xDA0B80
+
+#define mmNIC3_QM0_ARB_CHOISE_FULLNESS_STS 0xDA0B84
+
+#define mmNIC3_QM0_ARB_MSG_STS 0xDA0B88
+
+#define mmNIC3_QM0_ARB_SLV_CHOISE_Q_HEAD 0xDA0B8C
+
+#define mmNIC3_QM0_ARB_ERR_CAUSE 0xDA0B9C
+
+#define mmNIC3_QM0_ARB_ERR_MSG_EN 0xDA0BA0
+
+#define mmNIC3_QM0_ARB_ERR_STS_DRP 0xDA0BA8
+
+#define mmNIC3_QM0_ARB_MST_CRED_STS_0 0xDA0BB0
+
+#define mmNIC3_QM0_ARB_MST_CRED_STS_1 0xDA0BB4
+
+#define mmNIC3_QM0_ARB_MST_CRED_STS_2 0xDA0BB8
+
+#define mmNIC3_QM0_ARB_MST_CRED_STS_3 0xDA0BBC
+
+#define mmNIC3_QM0_ARB_MST_CRED_STS_4 0xDA0BC0
+
+#define mmNIC3_QM0_ARB_MST_CRED_STS_5 0xDA0BC4
+
+#define mmNIC3_QM0_ARB_MST_CRED_STS_6 0xDA0BC8
+
+#define mmNIC3_QM0_ARB_MST_CRED_STS_7 0xDA0BCC
+
+#define mmNIC3_QM0_ARB_MST_CRED_STS_8 0xDA0BD0
+
+#define mmNIC3_QM0_ARB_MST_CRED_STS_9 0xDA0BD4
+
+#define mmNIC3_QM0_ARB_MST_CRED_STS_10 0xDA0BD8
+
+#define mmNIC3_QM0_ARB_MST_CRED_STS_11 0xDA0BDC
+
+#define mmNIC3_QM0_ARB_MST_CRED_STS_12 0xDA0BE0
+
+#define mmNIC3_QM0_ARB_MST_CRED_STS_13 0xDA0BE4
+
+#define mmNIC3_QM0_ARB_MST_CRED_STS_14 0xDA0BE8
+
+#define mmNIC3_QM0_ARB_MST_CRED_STS_15 0xDA0BEC
+
+#define mmNIC3_QM0_ARB_MST_CRED_STS_16 0xDA0BF0
+
+#define mmNIC3_QM0_ARB_MST_CRED_STS_17 0xDA0BF4
+
+#define mmNIC3_QM0_ARB_MST_CRED_STS_18 0xDA0BF8
+
+#define mmNIC3_QM0_ARB_MST_CRED_STS_19 0xDA0BFC
+
+#define mmNIC3_QM0_ARB_MST_CRED_STS_20 0xDA0C00
+
+#define mmNIC3_QM0_ARB_MST_CRED_STS_21 0xDA0C04
+
+#define mmNIC3_QM0_ARB_MST_CRED_STS_22 0xDA0C08
+
+#define mmNIC3_QM0_ARB_MST_CRED_STS_23 0xDA0C0C
+
+#define mmNIC3_QM0_ARB_MST_CRED_STS_24 0xDA0C10
+
+#define mmNIC3_QM0_ARB_MST_CRED_STS_25 0xDA0C14
+
+#define mmNIC3_QM0_ARB_MST_CRED_STS_26 0xDA0C18
+
+#define mmNIC3_QM0_ARB_MST_CRED_STS_27 0xDA0C1C
+
+#define mmNIC3_QM0_ARB_MST_CRED_STS_28 0xDA0C20
+
+#define mmNIC3_QM0_ARB_MST_CRED_STS_29 0xDA0C24
+
+#define mmNIC3_QM0_ARB_MST_CRED_STS_30 0xDA0C28
+
+#define mmNIC3_QM0_ARB_MST_CRED_STS_31 0xDA0C2C
+
+#define mmNIC3_QM0_CGM_CFG 0xDA0C70
+
+#define mmNIC3_QM0_CGM_STS 0xDA0C74
+
+#define mmNIC3_QM0_CGM_CFG1 0xDA0C78
+
+#define mmNIC3_QM0_LOCAL_RANGE_BASE 0xDA0C80
+
+#define mmNIC3_QM0_LOCAL_RANGE_SIZE 0xDA0C84
+
+#define mmNIC3_QM0_CSMR_STRICT_PRIO_CFG 0xDA0C90
+
+#define mmNIC3_QM0_HBW_RD_RATE_LIM_CFG_1 0xDA0C94
+
+#define mmNIC3_QM0_LBW_WR_RATE_LIM_CFG_0 0xDA0C98
+
+#define mmNIC3_QM0_LBW_WR_RATE_LIM_CFG_1 0xDA0C9C
+
+#define mmNIC3_QM0_HBW_RD_RATE_LIM_CFG_0 0xDA0CA0
+
+#define mmNIC3_QM0_GLBL_AXCACHE 0xDA0CA4
+
+#define mmNIC3_QM0_IND_GW_APB_CFG 0xDA0CB0
+
+#define mmNIC3_QM0_IND_GW_APB_WDATA 0xDA0CB4
+
+#define mmNIC3_QM0_IND_GW_APB_RDATA 0xDA0CB8
+
+#define mmNIC3_QM0_IND_GW_APB_STATUS 0xDA0CBC
+
+#define mmNIC3_QM0_GLBL_ERR_ADDR_LO 0xDA0CD0
+
+#define mmNIC3_QM0_GLBL_ERR_ADDR_HI 0xDA0CD4
+
+#define mmNIC3_QM0_GLBL_ERR_WDATA 0xDA0CD8
+
+#define mmNIC3_QM0_GLBL_MEM_INIT_BUSY 0xDA0D00
+
+#endif /* ASIC_REG_NIC3_QM0_REGS_H_ */
diff --git a/drivers/accel/habanalabs/include/gaudi/asic_reg/nic3_qm1_regs.h b/drivers/accel/habanalabs/include/gaudi/asic_reg/nic3_qm1_regs.h
new file mode 100644
index 0000000000..7fa040f650
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi/asic_reg/nic3_qm1_regs.h
@@ -0,0 +1,834 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2016-2018 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ ** DO NOT EDIT BELOW **
+ ************************************/
+
+#ifndef ASIC_REG_NIC3_QM1_REGS_H_
+#define ASIC_REG_NIC3_QM1_REGS_H_
+
+/*
+ *****************************************
+ * NIC3_QM1 (Prototype: QMAN)
+ *****************************************
+ */
+
+#define mmNIC3_QM1_GLBL_CFG0 0xDA2000
+
+#define mmNIC3_QM1_GLBL_CFG1 0xDA2004
+
+#define mmNIC3_QM1_GLBL_PROT 0xDA2008
+
+#define mmNIC3_QM1_GLBL_ERR_CFG 0xDA200C
+
+#define mmNIC3_QM1_GLBL_SECURE_PROPS_0 0xDA2010
+
+#define mmNIC3_QM1_GLBL_SECURE_PROPS_1 0xDA2014
+
+#define mmNIC3_QM1_GLBL_SECURE_PROPS_2 0xDA2018
+
+#define mmNIC3_QM1_GLBL_SECURE_PROPS_3 0xDA201C
+
+#define mmNIC3_QM1_GLBL_SECURE_PROPS_4 0xDA2020
+
+#define mmNIC3_QM1_GLBL_NON_SECURE_PROPS_0 0xDA2024
+
+#define mmNIC3_QM1_GLBL_NON_SECURE_PROPS_1 0xDA2028
+
+#define mmNIC3_QM1_GLBL_NON_SECURE_PROPS_2 0xDA202C
+
+#define mmNIC3_QM1_GLBL_NON_SECURE_PROPS_3 0xDA2030
+
+#define mmNIC3_QM1_GLBL_NON_SECURE_PROPS_4 0xDA2034
+
+#define mmNIC3_QM1_GLBL_STS0 0xDA2038
+
+#define mmNIC3_QM1_GLBL_STS1_0 0xDA2040
+
+#define mmNIC3_QM1_GLBL_STS1_1 0xDA2044
+
+#define mmNIC3_QM1_GLBL_STS1_2 0xDA2048
+
+#define mmNIC3_QM1_GLBL_STS1_3 0xDA204C
+
+#define mmNIC3_QM1_GLBL_STS1_4 0xDA2050
+
+#define mmNIC3_QM1_GLBL_MSG_EN_0 0xDA2054
+
+#define mmNIC3_QM1_GLBL_MSG_EN_1 0xDA2058
+
+#define mmNIC3_QM1_GLBL_MSG_EN_2 0xDA205C
+
+#define mmNIC3_QM1_GLBL_MSG_EN_3 0xDA2060
+
+#define mmNIC3_QM1_GLBL_MSG_EN_4 0xDA2068
+
+#define mmNIC3_QM1_PQ_BASE_LO_0 0xDA2070
+
+#define mmNIC3_QM1_PQ_BASE_LO_1 0xDA2074
+
+#define mmNIC3_QM1_PQ_BASE_LO_2 0xDA2078
+
+#define mmNIC3_QM1_PQ_BASE_LO_3 0xDA207C
+
+#define mmNIC3_QM1_PQ_BASE_HI_0 0xDA2080
+
+#define mmNIC3_QM1_PQ_BASE_HI_1 0xDA2084
+
+#define mmNIC3_QM1_PQ_BASE_HI_2 0xDA2088
+
+#define mmNIC3_QM1_PQ_BASE_HI_3 0xDA208C
+
+#define mmNIC3_QM1_PQ_SIZE_0 0xDA2090
+
+#define mmNIC3_QM1_PQ_SIZE_1 0xDA2094
+
+#define mmNIC3_QM1_PQ_SIZE_2 0xDA2098
+
+#define mmNIC3_QM1_PQ_SIZE_3 0xDA209C
+
+#define mmNIC3_QM1_PQ_PI_0 0xDA20A0
+
+#define mmNIC3_QM1_PQ_PI_1 0xDA20A4
+
+#define mmNIC3_QM1_PQ_PI_2 0xDA20A8
+
+#define mmNIC3_QM1_PQ_PI_3 0xDA20AC
+
+#define mmNIC3_QM1_PQ_CI_0 0xDA20B0
+
+#define mmNIC3_QM1_PQ_CI_1 0xDA20B4
+
+#define mmNIC3_QM1_PQ_CI_2 0xDA20B8
+
+#define mmNIC3_QM1_PQ_CI_3 0xDA20BC
+
+#define mmNIC3_QM1_PQ_CFG0_0 0xDA20C0
+
+#define mmNIC3_QM1_PQ_CFG0_1 0xDA20C4
+
+#define mmNIC3_QM1_PQ_CFG0_2 0xDA20C8
+
+#define mmNIC3_QM1_PQ_CFG0_3 0xDA20CC
+
+#define mmNIC3_QM1_PQ_CFG1_0 0xDA20D0
+
+#define mmNIC3_QM1_PQ_CFG1_1 0xDA20D4
+
+#define mmNIC3_QM1_PQ_CFG1_2 0xDA20D8
+
+#define mmNIC3_QM1_PQ_CFG1_3 0xDA20DC
+
+#define mmNIC3_QM1_PQ_ARUSER_31_11_0 0xDA20E0
+
+#define mmNIC3_QM1_PQ_ARUSER_31_11_1 0xDA20E4
+
+#define mmNIC3_QM1_PQ_ARUSER_31_11_2 0xDA20E8
+
+#define mmNIC3_QM1_PQ_ARUSER_31_11_3 0xDA20EC
+
+#define mmNIC3_QM1_PQ_STS0_0 0xDA20F0
+
+#define mmNIC3_QM1_PQ_STS0_1 0xDA20F4
+
+#define mmNIC3_QM1_PQ_STS0_2 0xDA20F8
+
+#define mmNIC3_QM1_PQ_STS0_3 0xDA20FC
+
+#define mmNIC3_QM1_PQ_STS1_0 0xDA2100
+
+#define mmNIC3_QM1_PQ_STS1_1 0xDA2104
+
+#define mmNIC3_QM1_PQ_STS1_2 0xDA2108
+
+#define mmNIC3_QM1_PQ_STS1_3 0xDA210C
+
+#define mmNIC3_QM1_CQ_CFG0_0 0xDA2110
+
+#define mmNIC3_QM1_CQ_CFG0_1 0xDA2114
+
+#define mmNIC3_QM1_CQ_CFG0_2 0xDA2118
+
+#define mmNIC3_QM1_CQ_CFG0_3 0xDA211C
+
+#define mmNIC3_QM1_CQ_CFG0_4 0xDA2120
+
+#define mmNIC3_QM1_CQ_CFG1_0 0xDA2124
+
+#define mmNIC3_QM1_CQ_CFG1_1 0xDA2128
+
+#define mmNIC3_QM1_CQ_CFG1_2 0xDA212C
+
+#define mmNIC3_QM1_CQ_CFG1_3 0xDA2130
+
+#define mmNIC3_QM1_CQ_CFG1_4 0xDA2134
+
+#define mmNIC3_QM1_CQ_ARUSER_31_11_0 0xDA2138
+
+#define mmNIC3_QM1_CQ_ARUSER_31_11_1 0xDA213C
+
+#define mmNIC3_QM1_CQ_ARUSER_31_11_2 0xDA2140
+
+#define mmNIC3_QM1_CQ_ARUSER_31_11_3 0xDA2144
+
+#define mmNIC3_QM1_CQ_ARUSER_31_11_4 0xDA2148
+
+#define mmNIC3_QM1_CQ_STS0_0 0xDA214C
+
+#define mmNIC3_QM1_CQ_STS0_1 0xDA2150
+
+#define mmNIC3_QM1_CQ_STS0_2 0xDA2154
+
+#define mmNIC3_QM1_CQ_STS0_3 0xDA2158
+
+#define mmNIC3_QM1_CQ_STS0_4 0xDA215C
+
+#define mmNIC3_QM1_CQ_STS1_0 0xDA2160
+
+#define mmNIC3_QM1_CQ_STS1_1 0xDA2164
+
+#define mmNIC3_QM1_CQ_STS1_2 0xDA2168
+
+#define mmNIC3_QM1_CQ_STS1_3 0xDA216C
+
+#define mmNIC3_QM1_CQ_STS1_4 0xDA2170
+
+#define mmNIC3_QM1_CQ_PTR_LO_0 0xDA2174
+
+#define mmNIC3_QM1_CQ_PTR_HI_0 0xDA2178
+
+#define mmNIC3_QM1_CQ_TSIZE_0 0xDA217C
+
+#define mmNIC3_QM1_CQ_CTL_0 0xDA2180
+
+#define mmNIC3_QM1_CQ_PTR_LO_1 0xDA2184
+
+#define mmNIC3_QM1_CQ_PTR_HI_1 0xDA2188
+
+#define mmNIC3_QM1_CQ_TSIZE_1 0xDA218C
+
+#define mmNIC3_QM1_CQ_CTL_1 0xDA2190
+
+#define mmNIC3_QM1_CQ_PTR_LO_2 0xDA2194
+
+#define mmNIC3_QM1_CQ_PTR_HI_2 0xDA2198
+
+#define mmNIC3_QM1_CQ_TSIZE_2 0xDA219C
+
+#define mmNIC3_QM1_CQ_CTL_2 0xDA21A0
+
+#define mmNIC3_QM1_CQ_PTR_LO_3 0xDA21A4
+
+#define mmNIC3_QM1_CQ_PTR_HI_3 0xDA21A8
+
+#define mmNIC3_QM1_CQ_TSIZE_3 0xDA21AC
+
+#define mmNIC3_QM1_CQ_CTL_3 0xDA21B0
+
+#define mmNIC3_QM1_CQ_PTR_LO_4 0xDA21B4
+
+#define mmNIC3_QM1_CQ_PTR_HI_4 0xDA21B8
+
+#define mmNIC3_QM1_CQ_TSIZE_4 0xDA21BC
+
+#define mmNIC3_QM1_CQ_CTL_4 0xDA21C0
+
+#define mmNIC3_QM1_CQ_PTR_LO_STS_0 0xDA21C4
+
+#define mmNIC3_QM1_CQ_PTR_LO_STS_1 0xDA21C8
+
+#define mmNIC3_QM1_CQ_PTR_LO_STS_2 0xDA21CC
+
+#define mmNIC3_QM1_CQ_PTR_LO_STS_3 0xDA21D0
+
+#define mmNIC3_QM1_CQ_PTR_LO_STS_4 0xDA21D4
+
+#define mmNIC3_QM1_CQ_PTR_HI_STS_0 0xDA21D8
+
+#define mmNIC3_QM1_CQ_PTR_HI_STS_1 0xDA21DC
+
+#define mmNIC3_QM1_CQ_PTR_HI_STS_2 0xDA21E0
+
+#define mmNIC3_QM1_CQ_PTR_HI_STS_3 0xDA21E4
+
+#define mmNIC3_QM1_CQ_PTR_HI_STS_4 0xDA21E8
+
+#define mmNIC3_QM1_CQ_TSIZE_STS_0 0xDA21EC
+
+#define mmNIC3_QM1_CQ_TSIZE_STS_1 0xDA21F0
+
+#define mmNIC3_QM1_CQ_TSIZE_STS_2 0xDA21F4
+
+#define mmNIC3_QM1_CQ_TSIZE_STS_3 0xDA21F8
+
+#define mmNIC3_QM1_CQ_TSIZE_STS_4 0xDA21FC
+
+#define mmNIC3_QM1_CQ_CTL_STS_0 0xDA2200
+
+#define mmNIC3_QM1_CQ_CTL_STS_1 0xDA2204
+
+#define mmNIC3_QM1_CQ_CTL_STS_2 0xDA2208
+
+#define mmNIC3_QM1_CQ_CTL_STS_3 0xDA220C
+
+#define mmNIC3_QM1_CQ_CTL_STS_4 0xDA2210
+
+#define mmNIC3_QM1_CQ_IFIFO_CNT_0 0xDA2214
+
+#define mmNIC3_QM1_CQ_IFIFO_CNT_1 0xDA2218
+
+#define mmNIC3_QM1_CQ_IFIFO_CNT_2 0xDA221C
+
+#define mmNIC3_QM1_CQ_IFIFO_CNT_3 0xDA2220
+
+#define mmNIC3_QM1_CQ_IFIFO_CNT_4 0xDA2224
+
+#define mmNIC3_QM1_CP_MSG_BASE0_ADDR_LO_0 0xDA2228
+
+#define mmNIC3_QM1_CP_MSG_BASE0_ADDR_LO_1 0xDA222C
+
+#define mmNIC3_QM1_CP_MSG_BASE0_ADDR_LO_2 0xDA2230
+
+#define mmNIC3_QM1_CP_MSG_BASE0_ADDR_LO_3 0xDA2234
+
+#define mmNIC3_QM1_CP_MSG_BASE0_ADDR_LO_4 0xDA2238
+
+#define mmNIC3_QM1_CP_MSG_BASE0_ADDR_HI_0 0xDA223C
+
+#define mmNIC3_QM1_CP_MSG_BASE0_ADDR_HI_1 0xDA2240
+
+#define mmNIC3_QM1_CP_MSG_BASE0_ADDR_HI_2 0xDA2244
+
+#define mmNIC3_QM1_CP_MSG_BASE0_ADDR_HI_3 0xDA2248
+
+#define mmNIC3_QM1_CP_MSG_BASE0_ADDR_HI_4 0xDA224C
+
+#define mmNIC3_QM1_CP_MSG_BASE1_ADDR_LO_0 0xDA2250
+
+#define mmNIC3_QM1_CP_MSG_BASE1_ADDR_LO_1 0xDA2254
+
+#define mmNIC3_QM1_CP_MSG_BASE1_ADDR_LO_2 0xDA2258
+
+#define mmNIC3_QM1_CP_MSG_BASE1_ADDR_LO_3 0xDA225C
+
+#define mmNIC3_QM1_CP_MSG_BASE1_ADDR_LO_4 0xDA2260
+
+#define mmNIC3_QM1_CP_MSG_BASE1_ADDR_HI_0 0xDA2264
+
+#define mmNIC3_QM1_CP_MSG_BASE1_ADDR_HI_1 0xDA2268
+
+#define mmNIC3_QM1_CP_MSG_BASE1_ADDR_HI_2 0xDA226C
+
+#define mmNIC3_QM1_CP_MSG_BASE1_ADDR_HI_3 0xDA2270
+
+#define mmNIC3_QM1_CP_MSG_BASE1_ADDR_HI_4 0xDA2274
+
+#define mmNIC3_QM1_CP_MSG_BASE2_ADDR_LO_0 0xDA2278
+
+#define mmNIC3_QM1_CP_MSG_BASE2_ADDR_LO_1 0xDA227C
+
+#define mmNIC3_QM1_CP_MSG_BASE2_ADDR_LO_2 0xDA2280
+
+#define mmNIC3_QM1_CP_MSG_BASE2_ADDR_LO_3 0xDA2284
+
+#define mmNIC3_QM1_CP_MSG_BASE2_ADDR_LO_4 0xDA2288
+
+#define mmNIC3_QM1_CP_MSG_BASE2_ADDR_HI_0 0xDA228C
+
+#define mmNIC3_QM1_CP_MSG_BASE2_ADDR_HI_1 0xDA2290
+
+#define mmNIC3_QM1_CP_MSG_BASE2_ADDR_HI_2 0xDA2294
+
+#define mmNIC3_QM1_CP_MSG_BASE2_ADDR_HI_3 0xDA2298
+
+#define mmNIC3_QM1_CP_MSG_BASE2_ADDR_HI_4 0xDA229C
+
+#define mmNIC3_QM1_CP_MSG_BASE3_ADDR_LO_0 0xDA22A0
+
+#define mmNIC3_QM1_CP_MSG_BASE3_ADDR_LO_1 0xDA22A4
+
+#define mmNIC3_QM1_CP_MSG_BASE3_ADDR_LO_2 0xDA22A8
+
+#define mmNIC3_QM1_CP_MSG_BASE3_ADDR_LO_3 0xDA22AC
+
+#define mmNIC3_QM1_CP_MSG_BASE3_ADDR_LO_4 0xDA22B0
+
+#define mmNIC3_QM1_CP_MSG_BASE3_ADDR_HI_0 0xDA22B4
+
+#define mmNIC3_QM1_CP_MSG_BASE3_ADDR_HI_1 0xDA22B8
+
+#define mmNIC3_QM1_CP_MSG_BASE3_ADDR_HI_2 0xDA22BC
+
+#define mmNIC3_QM1_CP_MSG_BASE3_ADDR_HI_3 0xDA22C0
+
+#define mmNIC3_QM1_CP_MSG_BASE3_ADDR_HI_4 0xDA22C4
+
+#define mmNIC3_QM1_CP_LDMA_TSIZE_OFFSET_0 0xDA22C8
+
+#define mmNIC3_QM1_CP_LDMA_TSIZE_OFFSET_1 0xDA22CC
+
+#define mmNIC3_QM1_CP_LDMA_TSIZE_OFFSET_2 0xDA22D0
+
+#define mmNIC3_QM1_CP_LDMA_TSIZE_OFFSET_3 0xDA22D4
+
+#define mmNIC3_QM1_CP_LDMA_TSIZE_OFFSET_4 0xDA22D8
+
+#define mmNIC3_QM1_CP_LDMA_SRC_BASE_LO_OFFSET_0 0xDA22E0
+
+#define mmNIC3_QM1_CP_LDMA_SRC_BASE_LO_OFFSET_1 0xDA22E4
+
+#define mmNIC3_QM1_CP_LDMA_SRC_BASE_LO_OFFSET_2 0xDA22E8
+
+#define mmNIC3_QM1_CP_LDMA_SRC_BASE_LO_OFFSET_3 0xDA22EC
+
+#define mmNIC3_QM1_CP_LDMA_SRC_BASE_LO_OFFSET_4 0xDA22F0
+
+#define mmNIC3_QM1_CP_LDMA_DST_BASE_LO_OFFSET_0 0xDA22F4
+
+#define mmNIC3_QM1_CP_LDMA_DST_BASE_LO_OFFSET_1 0xDA22F8
+
+#define mmNIC3_QM1_CP_LDMA_DST_BASE_LO_OFFSET_2 0xDA22FC
+
+#define mmNIC3_QM1_CP_LDMA_DST_BASE_LO_OFFSET_3 0xDA2300
+
+#define mmNIC3_QM1_CP_LDMA_DST_BASE_LO_OFFSET_4 0xDA2304
+
+#define mmNIC3_QM1_CP_FENCE0_RDATA_0 0xDA2308
+
+#define mmNIC3_QM1_CP_FENCE0_RDATA_1 0xDA230C
+
+#define mmNIC3_QM1_CP_FENCE0_RDATA_2 0xDA2310
+
+#define mmNIC3_QM1_CP_FENCE0_RDATA_3 0xDA2314
+
+#define mmNIC3_QM1_CP_FENCE0_RDATA_4 0xDA2318
+
+#define mmNIC3_QM1_CP_FENCE1_RDATA_0 0xDA231C
+
+#define mmNIC3_QM1_CP_FENCE1_RDATA_1 0xDA2320
+
+#define mmNIC3_QM1_CP_FENCE1_RDATA_2 0xDA2324
+
+#define mmNIC3_QM1_CP_FENCE1_RDATA_3 0xDA2328
+
+#define mmNIC3_QM1_CP_FENCE1_RDATA_4 0xDA232C
+
+#define mmNIC3_QM1_CP_FENCE2_RDATA_0 0xDA2330
+
+#define mmNIC3_QM1_CP_FENCE2_RDATA_1 0xDA2334
+
+#define mmNIC3_QM1_CP_FENCE2_RDATA_2 0xDA2338
+
+#define mmNIC3_QM1_CP_FENCE2_RDATA_3 0xDA233C
+
+#define mmNIC3_QM1_CP_FENCE2_RDATA_4 0xDA2340
+
+#define mmNIC3_QM1_CP_FENCE3_RDATA_0 0xDA2344
+
+#define mmNIC3_QM1_CP_FENCE3_RDATA_1 0xDA2348
+
+#define mmNIC3_QM1_CP_FENCE3_RDATA_2 0xDA234C
+
+#define mmNIC3_QM1_CP_FENCE3_RDATA_3 0xDA2350
+
+#define mmNIC3_QM1_CP_FENCE3_RDATA_4 0xDA2354
+
+#define mmNIC3_QM1_CP_FENCE0_CNT_0 0xDA2358
+
+#define mmNIC3_QM1_CP_FENCE0_CNT_1 0xDA235C
+
+#define mmNIC3_QM1_CP_FENCE0_CNT_2 0xDA2360
+
+#define mmNIC3_QM1_CP_FENCE0_CNT_3 0xDA2364
+
+#define mmNIC3_QM1_CP_FENCE0_CNT_4 0xDA2368
+
+#define mmNIC3_QM1_CP_FENCE1_CNT_0 0xDA236C
+
+#define mmNIC3_QM1_CP_FENCE1_CNT_1 0xDA2370
+
+#define mmNIC3_QM1_CP_FENCE1_CNT_2 0xDA2374
+
+#define mmNIC3_QM1_CP_FENCE1_CNT_3 0xDA2378
+
+#define mmNIC3_QM1_CP_FENCE1_CNT_4 0xDA237C
+
+#define mmNIC3_QM1_CP_FENCE2_CNT_0 0xDA2380
+
+#define mmNIC3_QM1_CP_FENCE2_CNT_1 0xDA2384
+
+#define mmNIC3_QM1_CP_FENCE2_CNT_2 0xDA2388
+
+#define mmNIC3_QM1_CP_FENCE2_CNT_3 0xDA238C
+
+#define mmNIC3_QM1_CP_FENCE2_CNT_4 0xDA2390
+
+#define mmNIC3_QM1_CP_FENCE3_CNT_0 0xDA2394
+
+#define mmNIC3_QM1_CP_FENCE3_CNT_1 0xDA2398
+
+#define mmNIC3_QM1_CP_FENCE3_CNT_2 0xDA239C
+
+#define mmNIC3_QM1_CP_FENCE3_CNT_3 0xDA23A0
+
+#define mmNIC3_QM1_CP_FENCE3_CNT_4 0xDA23A4
+
+#define mmNIC3_QM1_CP_STS_0 0xDA23A8
+
+#define mmNIC3_QM1_CP_STS_1 0xDA23AC
+
+#define mmNIC3_QM1_CP_STS_2 0xDA23B0
+
+#define mmNIC3_QM1_CP_STS_3 0xDA23B4
+
+#define mmNIC3_QM1_CP_STS_4 0xDA23B8
+
+#define mmNIC3_QM1_CP_CURRENT_INST_LO_0 0xDA23BC
+
+#define mmNIC3_QM1_CP_CURRENT_INST_LO_1 0xDA23C0
+
+#define mmNIC3_QM1_CP_CURRENT_INST_LO_2 0xDA23C4
+
+#define mmNIC3_QM1_CP_CURRENT_INST_LO_3 0xDA23C8
+
+#define mmNIC3_QM1_CP_CURRENT_INST_LO_4 0xDA23CC
+
+#define mmNIC3_QM1_CP_CURRENT_INST_HI_0 0xDA23D0
+
+#define mmNIC3_QM1_CP_CURRENT_INST_HI_1 0xDA23D4
+
+#define mmNIC3_QM1_CP_CURRENT_INST_HI_2 0xDA23D8
+
+#define mmNIC3_QM1_CP_CURRENT_INST_HI_3 0xDA23DC
+
+#define mmNIC3_QM1_CP_CURRENT_INST_HI_4 0xDA23E0
+
+#define mmNIC3_QM1_CP_BARRIER_CFG_0 0xDA23F4
+
+#define mmNIC3_QM1_CP_BARRIER_CFG_1 0xDA23F8
+
+#define mmNIC3_QM1_CP_BARRIER_CFG_2 0xDA23FC
+
+#define mmNIC3_QM1_CP_BARRIER_CFG_3 0xDA2400
+
+#define mmNIC3_QM1_CP_BARRIER_CFG_4 0xDA2404
+
+#define mmNIC3_QM1_CP_DBG_0_0 0xDA2408
+
+#define mmNIC3_QM1_CP_DBG_0_1 0xDA240C
+
+#define mmNIC3_QM1_CP_DBG_0_2 0xDA2410
+
+#define mmNIC3_QM1_CP_DBG_0_3 0xDA2414
+
+#define mmNIC3_QM1_CP_DBG_0_4 0xDA2418
+
+#define mmNIC3_QM1_CP_ARUSER_31_11_0 0xDA241C
+
+#define mmNIC3_QM1_CP_ARUSER_31_11_1 0xDA2420
+
+#define mmNIC3_QM1_CP_ARUSER_31_11_2 0xDA2424
+
+#define mmNIC3_QM1_CP_ARUSER_31_11_3 0xDA2428
+
+#define mmNIC3_QM1_CP_ARUSER_31_11_4 0xDA242C
+
+#define mmNIC3_QM1_CP_AWUSER_31_11_0 0xDA2430
+
+#define mmNIC3_QM1_CP_AWUSER_31_11_1 0xDA2434
+
+#define mmNIC3_QM1_CP_AWUSER_31_11_2 0xDA2438
+
+#define mmNIC3_QM1_CP_AWUSER_31_11_3 0xDA243C
+
+#define mmNIC3_QM1_CP_AWUSER_31_11_4 0xDA2440
+
+#define mmNIC3_QM1_ARB_CFG_0 0xDA2A00
+
+#define mmNIC3_QM1_ARB_CHOISE_Q_PUSH 0xDA2A04
+
+#define mmNIC3_QM1_ARB_WRR_WEIGHT_0 0xDA2A08
+
+#define mmNIC3_QM1_ARB_WRR_WEIGHT_1 0xDA2A0C
+
+#define mmNIC3_QM1_ARB_WRR_WEIGHT_2 0xDA2A10
+
+#define mmNIC3_QM1_ARB_WRR_WEIGHT_3 0xDA2A14
+
+#define mmNIC3_QM1_ARB_CFG_1 0xDA2A18
+
+#define mmNIC3_QM1_ARB_MST_AVAIL_CRED_0 0xDA2A20
+
+#define mmNIC3_QM1_ARB_MST_AVAIL_CRED_1 0xDA2A24
+
+#define mmNIC3_QM1_ARB_MST_AVAIL_CRED_2 0xDA2A28
+
+#define mmNIC3_QM1_ARB_MST_AVAIL_CRED_3 0xDA2A2C
+
+#define mmNIC3_QM1_ARB_MST_AVAIL_CRED_4 0xDA2A30
+
+#define mmNIC3_QM1_ARB_MST_AVAIL_CRED_5 0xDA2A34
+
+#define mmNIC3_QM1_ARB_MST_AVAIL_CRED_6 0xDA2A38
+
+#define mmNIC3_QM1_ARB_MST_AVAIL_CRED_7 0xDA2A3C
+
+#define mmNIC3_QM1_ARB_MST_AVAIL_CRED_8 0xDA2A40
+
+#define mmNIC3_QM1_ARB_MST_AVAIL_CRED_9 0xDA2A44
+
+#define mmNIC3_QM1_ARB_MST_AVAIL_CRED_10 0xDA2A48
+
+#define mmNIC3_QM1_ARB_MST_AVAIL_CRED_11 0xDA2A4C
+
+#define mmNIC3_QM1_ARB_MST_AVAIL_CRED_12 0xDA2A50
+
+#define mmNIC3_QM1_ARB_MST_AVAIL_CRED_13 0xDA2A54
+
+#define mmNIC3_QM1_ARB_MST_AVAIL_CRED_14 0xDA2A58
+
+#define mmNIC3_QM1_ARB_MST_AVAIL_CRED_15 0xDA2A5C
+
+#define mmNIC3_QM1_ARB_MST_AVAIL_CRED_16 0xDA2A60
+
+#define mmNIC3_QM1_ARB_MST_AVAIL_CRED_17 0xDA2A64
+
+#define mmNIC3_QM1_ARB_MST_AVAIL_CRED_18 0xDA2A68
+
+#define mmNIC3_QM1_ARB_MST_AVAIL_CRED_19 0xDA2A6C
+
+#define mmNIC3_QM1_ARB_MST_AVAIL_CRED_20 0xDA2A70
+
+#define mmNIC3_QM1_ARB_MST_AVAIL_CRED_21 0xDA2A74
+
+#define mmNIC3_QM1_ARB_MST_AVAIL_CRED_22 0xDA2A78
+
+#define mmNIC3_QM1_ARB_MST_AVAIL_CRED_23 0xDA2A7C
+
+#define mmNIC3_QM1_ARB_MST_AVAIL_CRED_24 0xDA2A80
+
+#define mmNIC3_QM1_ARB_MST_AVAIL_CRED_25 0xDA2A84
+
+#define mmNIC3_QM1_ARB_MST_AVAIL_CRED_26 0xDA2A88
+
+#define mmNIC3_QM1_ARB_MST_AVAIL_CRED_27 0xDA2A8C
+
+#define mmNIC3_QM1_ARB_MST_AVAIL_CRED_28 0xDA2A90
+
+#define mmNIC3_QM1_ARB_MST_AVAIL_CRED_29 0xDA2A94
+
+#define mmNIC3_QM1_ARB_MST_AVAIL_CRED_30 0xDA2A98
+
+#define mmNIC3_QM1_ARB_MST_AVAIL_CRED_31 0xDA2A9C
+
+#define mmNIC3_QM1_ARB_MST_CRED_INC 0xDA2AA0
+
+#define mmNIC3_QM1_ARB_MST_CHOISE_PUSH_OFST_0 0xDA2AA4
+
+#define mmNIC3_QM1_ARB_MST_CHOISE_PUSH_OFST_1 0xDA2AA8
+
+#define mmNIC3_QM1_ARB_MST_CHOISE_PUSH_OFST_2 0xDA2AAC
+
+#define mmNIC3_QM1_ARB_MST_CHOISE_PUSH_OFST_3 0xDA2AB0
+
+#define mmNIC3_QM1_ARB_MST_CHOISE_PUSH_OFST_4 0xDA2AB4
+
+#define mmNIC3_QM1_ARB_MST_CHOISE_PUSH_OFST_5 0xDA2AB8
+
+#define mmNIC3_QM1_ARB_MST_CHOISE_PUSH_OFST_6 0xDA2ABC
+
+#define mmNIC3_QM1_ARB_MST_CHOISE_PUSH_OFST_7 0xDA2AC0
+
+#define mmNIC3_QM1_ARB_MST_CHOISE_PUSH_OFST_8 0xDA2AC4
+
+#define mmNIC3_QM1_ARB_MST_CHOISE_PUSH_OFST_9 0xDA2AC8
+
+#define mmNIC3_QM1_ARB_MST_CHOISE_PUSH_OFST_10 0xDA2ACC
+
+#define mmNIC3_QM1_ARB_MST_CHOISE_PUSH_OFST_11 0xDA2AD0
+
+#define mmNIC3_QM1_ARB_MST_CHOISE_PUSH_OFST_12 0xDA2AD4
+
+#define mmNIC3_QM1_ARB_MST_CHOISE_PUSH_OFST_13 0xDA2AD8
+
+#define mmNIC3_QM1_ARB_MST_CHOISE_PUSH_OFST_14 0xDA2ADC
+
+#define mmNIC3_QM1_ARB_MST_CHOISE_PUSH_OFST_15 0xDA2AE0
+
+#define mmNIC3_QM1_ARB_MST_CHOISE_PUSH_OFST_16 0xDA2AE4
+
+#define mmNIC3_QM1_ARB_MST_CHOISE_PUSH_OFST_17 0xDA2AE8
+
+#define mmNIC3_QM1_ARB_MST_CHOISE_PUSH_OFST_18 0xDA2AEC
+
+#define mmNIC3_QM1_ARB_MST_CHOISE_PUSH_OFST_19 0xDA2AF0
+
+#define mmNIC3_QM1_ARB_MST_CHOISE_PUSH_OFST_20 0xDA2AF4
+
+#define mmNIC3_QM1_ARB_MST_CHOISE_PUSH_OFST_21 0xDA2AF8
+
+#define mmNIC3_QM1_ARB_MST_CHOISE_PUSH_OFST_22 0xDA2AFC
+
+#define mmNIC3_QM1_ARB_MST_CHOISE_PUSH_OFST_23 0xDA2B00
+
+#define mmNIC3_QM1_ARB_MST_CHOISE_PUSH_OFST_24 0xDA2B04
+
+#define mmNIC3_QM1_ARB_MST_CHOISE_PUSH_OFST_25 0xDA2B08
+
+#define mmNIC3_QM1_ARB_MST_CHOISE_PUSH_OFST_26 0xDA2B0C
+
+#define mmNIC3_QM1_ARB_MST_CHOISE_PUSH_OFST_27 0xDA2B10
+
+#define mmNIC3_QM1_ARB_MST_CHOISE_PUSH_OFST_28 0xDA2B14
+
+#define mmNIC3_QM1_ARB_MST_CHOISE_PUSH_OFST_29 0xDA2B18
+
+#define mmNIC3_QM1_ARB_MST_CHOISE_PUSH_OFST_30 0xDA2B1C
+
+#define mmNIC3_QM1_ARB_MST_CHOISE_PUSH_OFST_31 0xDA2B20
+
+#define mmNIC3_QM1_ARB_SLV_MASTER_INC_CRED_OFST 0xDA2B28
+
+#define mmNIC3_QM1_ARB_MST_SLAVE_EN 0xDA2B2C
+
+#define mmNIC3_QM1_ARB_MST_QUIET_PER 0xDA2B34
+
+#define mmNIC3_QM1_ARB_SLV_CHOISE_WDT 0xDA2B38
+
+#define mmNIC3_QM1_ARB_SLV_ID 0xDA2B3C
+
+#define mmNIC3_QM1_ARB_MSG_MAX_INFLIGHT 0xDA2B44
+
+#define mmNIC3_QM1_ARB_MSG_AWUSER_31_11 0xDA2B48
+
+#define mmNIC3_QM1_ARB_MSG_AWUSER_SEC_PROP 0xDA2B4C
+
+#define mmNIC3_QM1_ARB_MSG_AWUSER_NON_SEC_PROP 0xDA2B50
+
+#define mmNIC3_QM1_ARB_BASE_LO 0xDA2B54
+
+#define mmNIC3_QM1_ARB_BASE_HI 0xDA2B58
+
+#define mmNIC3_QM1_ARB_STATE_STS 0xDA2B80
+
+#define mmNIC3_QM1_ARB_CHOISE_FULLNESS_STS 0xDA2B84
+
+#define mmNIC3_QM1_ARB_MSG_STS 0xDA2B88
+
+#define mmNIC3_QM1_ARB_SLV_CHOISE_Q_HEAD 0xDA2B8C
+
+#define mmNIC3_QM1_ARB_ERR_CAUSE 0xDA2B9C
+
+#define mmNIC3_QM1_ARB_ERR_MSG_EN 0xDA2BA0
+
+#define mmNIC3_QM1_ARB_ERR_STS_DRP 0xDA2BA8
+
+#define mmNIC3_QM1_ARB_MST_CRED_STS_0 0xDA2BB0
+
+#define mmNIC3_QM1_ARB_MST_CRED_STS_1 0xDA2BB4
+
+#define mmNIC3_QM1_ARB_MST_CRED_STS_2 0xDA2BB8
+
+#define mmNIC3_QM1_ARB_MST_CRED_STS_3 0xDA2BBC
+
+#define mmNIC3_QM1_ARB_MST_CRED_STS_4 0xDA2BC0
+
+#define mmNIC3_QM1_ARB_MST_CRED_STS_5 0xDA2BC4
+
+#define mmNIC3_QM1_ARB_MST_CRED_STS_6 0xDA2BC8
+
+#define mmNIC3_QM1_ARB_MST_CRED_STS_7 0xDA2BCC
+
+#define mmNIC3_QM1_ARB_MST_CRED_STS_8 0xDA2BD0
+
+#define mmNIC3_QM1_ARB_MST_CRED_STS_9 0xDA2BD4
+
+#define mmNIC3_QM1_ARB_MST_CRED_STS_10 0xDA2BD8
+
+#define mmNIC3_QM1_ARB_MST_CRED_STS_11 0xDA2BDC
+
+#define mmNIC3_QM1_ARB_MST_CRED_STS_12 0xDA2BE0
+
+#define mmNIC3_QM1_ARB_MST_CRED_STS_13 0xDA2BE4
+
+#define mmNIC3_QM1_ARB_MST_CRED_STS_14 0xDA2BE8
+
+#define mmNIC3_QM1_ARB_MST_CRED_STS_15 0xDA2BEC
+
+#define mmNIC3_QM1_ARB_MST_CRED_STS_16 0xDA2BF0
+
+#define mmNIC3_QM1_ARB_MST_CRED_STS_17 0xDA2BF4
+
+#define mmNIC3_QM1_ARB_MST_CRED_STS_18 0xDA2BF8
+
+#define mmNIC3_QM1_ARB_MST_CRED_STS_19 0xDA2BFC
+
+#define mmNIC3_QM1_ARB_MST_CRED_STS_20 0xDA2C00
+
+#define mmNIC3_QM1_ARB_MST_CRED_STS_21 0xDA2C04
+
+#define mmNIC3_QM1_ARB_MST_CRED_STS_22 0xDA2C08
+
+#define mmNIC3_QM1_ARB_MST_CRED_STS_23 0xDA2C0C
+
+#define mmNIC3_QM1_ARB_MST_CRED_STS_24 0xDA2C10
+
+#define mmNIC3_QM1_ARB_MST_CRED_STS_25 0xDA2C14
+
+#define mmNIC3_QM1_ARB_MST_CRED_STS_26 0xDA2C18
+
+#define mmNIC3_QM1_ARB_MST_CRED_STS_27 0xDA2C1C
+
+#define mmNIC3_QM1_ARB_MST_CRED_STS_28 0xDA2C20
+
+#define mmNIC3_QM1_ARB_MST_CRED_STS_29 0xDA2C24
+
+#define mmNIC3_QM1_ARB_MST_CRED_STS_30 0xDA2C28
+
+#define mmNIC3_QM1_ARB_MST_CRED_STS_31 0xDA2C2C
+
+#define mmNIC3_QM1_CGM_CFG 0xDA2C70
+
+#define mmNIC3_QM1_CGM_STS 0xDA2C74
+
+#define mmNIC3_QM1_CGM_CFG1 0xDA2C78
+
+#define mmNIC3_QM1_LOCAL_RANGE_BASE 0xDA2C80
+
+#define mmNIC3_QM1_LOCAL_RANGE_SIZE 0xDA2C84
+
+#define mmNIC3_QM1_CSMR_STRICT_PRIO_CFG 0xDA2C90
+
+#define mmNIC3_QM1_HBW_RD_RATE_LIM_CFG_1 0xDA2C94
+
+#define mmNIC3_QM1_LBW_WR_RATE_LIM_CFG_0 0xDA2C98
+
+#define mmNIC3_QM1_LBW_WR_RATE_LIM_CFG_1 0xDA2C9C
+
+#define mmNIC3_QM1_HBW_RD_RATE_LIM_CFG_0 0xDA2CA0
+
+#define mmNIC3_QM1_GLBL_AXCACHE 0xDA2CA4
+
+#define mmNIC3_QM1_IND_GW_APB_CFG 0xDA2CB0
+
+#define mmNIC3_QM1_IND_GW_APB_WDATA 0xDA2CB4
+
+#define mmNIC3_QM1_IND_GW_APB_RDATA 0xDA2CB8
+
+#define mmNIC3_QM1_IND_GW_APB_STATUS 0xDA2CBC
+
+#define mmNIC3_QM1_GLBL_ERR_ADDR_LO 0xDA2CD0
+
+#define mmNIC3_QM1_GLBL_ERR_ADDR_HI 0xDA2CD4
+
+#define mmNIC3_QM1_GLBL_ERR_WDATA 0xDA2CD8
+
+#define mmNIC3_QM1_GLBL_MEM_INIT_BUSY 0xDA2D00
+
+#endif /* ASIC_REG_NIC3_QM1_REGS_H_ */
diff --git a/drivers/accel/habanalabs/include/gaudi/asic_reg/nic4_qm0_regs.h b/drivers/accel/habanalabs/include/gaudi/asic_reg/nic4_qm0_regs.h
new file mode 100644
index 0000000000..99d5319672
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi/asic_reg/nic4_qm0_regs.h
@@ -0,0 +1,834 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2016-2018 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ ** DO NOT EDIT BELOW **
+ ************************************/
+
+#ifndef ASIC_REG_NIC4_QM0_REGS_H_
+#define ASIC_REG_NIC4_QM0_REGS_H_
+
+/*
+ *****************************************
+ * NIC4_QM0 (Prototype: QMAN)
+ *****************************************
+ */
+
+#define mmNIC4_QM0_GLBL_CFG0 0xDE0000
+
+#define mmNIC4_QM0_GLBL_CFG1 0xDE0004
+
+#define mmNIC4_QM0_GLBL_PROT 0xDE0008
+
+#define mmNIC4_QM0_GLBL_ERR_CFG 0xDE000C
+
+#define mmNIC4_QM0_GLBL_SECURE_PROPS_0 0xDE0010
+
+#define mmNIC4_QM0_GLBL_SECURE_PROPS_1 0xDE0014
+
+#define mmNIC4_QM0_GLBL_SECURE_PROPS_2 0xDE0018
+
+#define mmNIC4_QM0_GLBL_SECURE_PROPS_3 0xDE001C
+
+#define mmNIC4_QM0_GLBL_SECURE_PROPS_4 0xDE0020
+
+#define mmNIC4_QM0_GLBL_NON_SECURE_PROPS_0 0xDE0024
+
+#define mmNIC4_QM0_GLBL_NON_SECURE_PROPS_1 0xDE0028
+
+#define mmNIC4_QM0_GLBL_NON_SECURE_PROPS_2 0xDE002C
+
+#define mmNIC4_QM0_GLBL_NON_SECURE_PROPS_3 0xDE0030
+
+#define mmNIC4_QM0_GLBL_NON_SECURE_PROPS_4 0xDE0034
+
+#define mmNIC4_QM0_GLBL_STS0 0xDE0038
+
+#define mmNIC4_QM0_GLBL_STS1_0 0xDE0040
+
+#define mmNIC4_QM0_GLBL_STS1_1 0xDE0044
+
+#define mmNIC4_QM0_GLBL_STS1_2 0xDE0048
+
+#define mmNIC4_QM0_GLBL_STS1_3 0xDE004C
+
+#define mmNIC4_QM0_GLBL_STS1_4 0xDE0050
+
+#define mmNIC4_QM0_GLBL_MSG_EN_0 0xDE0054
+
+#define mmNIC4_QM0_GLBL_MSG_EN_1 0xDE0058
+
+#define mmNIC4_QM0_GLBL_MSG_EN_2 0xDE005C
+
+#define mmNIC4_QM0_GLBL_MSG_EN_3 0xDE0060
+
+#define mmNIC4_QM0_GLBL_MSG_EN_4 0xDE0068
+
+#define mmNIC4_QM0_PQ_BASE_LO_0 0xDE0070
+
+#define mmNIC4_QM0_PQ_BASE_LO_1 0xDE0074
+
+#define mmNIC4_QM0_PQ_BASE_LO_2 0xDE0078
+
+#define mmNIC4_QM0_PQ_BASE_LO_3 0xDE007C
+
+#define mmNIC4_QM0_PQ_BASE_HI_0 0xDE0080
+
+#define mmNIC4_QM0_PQ_BASE_HI_1 0xDE0084
+
+#define mmNIC4_QM0_PQ_BASE_HI_2 0xDE0088
+
+#define mmNIC4_QM0_PQ_BASE_HI_3 0xDE008C
+
+#define mmNIC4_QM0_PQ_SIZE_0 0xDE0090
+
+#define mmNIC4_QM0_PQ_SIZE_1 0xDE0094
+
+#define mmNIC4_QM0_PQ_SIZE_2 0xDE0098
+
+#define mmNIC4_QM0_PQ_SIZE_3 0xDE009C
+
+#define mmNIC4_QM0_PQ_PI_0 0xDE00A0
+
+#define mmNIC4_QM0_PQ_PI_1 0xDE00A4
+
+#define mmNIC4_QM0_PQ_PI_2 0xDE00A8
+
+#define mmNIC4_QM0_PQ_PI_3 0xDE00AC
+
+#define mmNIC4_QM0_PQ_CI_0 0xDE00B0
+
+#define mmNIC4_QM0_PQ_CI_1 0xDE00B4
+
+#define mmNIC4_QM0_PQ_CI_2 0xDE00B8
+
+#define mmNIC4_QM0_PQ_CI_3 0xDE00BC
+
+#define mmNIC4_QM0_PQ_CFG0_0 0xDE00C0
+
+#define mmNIC4_QM0_PQ_CFG0_1 0xDE00C4
+
+#define mmNIC4_QM0_PQ_CFG0_2 0xDE00C8
+
+#define mmNIC4_QM0_PQ_CFG0_3 0xDE00CC
+
+#define mmNIC4_QM0_PQ_CFG1_0 0xDE00D0
+
+#define mmNIC4_QM0_PQ_CFG1_1 0xDE00D4
+
+#define mmNIC4_QM0_PQ_CFG1_2 0xDE00D8
+
+#define mmNIC4_QM0_PQ_CFG1_3 0xDE00DC
+
+#define mmNIC4_QM0_PQ_ARUSER_31_11_0 0xDE00E0
+
+#define mmNIC4_QM0_PQ_ARUSER_31_11_1 0xDE00E4
+
+#define mmNIC4_QM0_PQ_ARUSER_31_11_2 0xDE00E8
+
+#define mmNIC4_QM0_PQ_ARUSER_31_11_3 0xDE00EC
+
+#define mmNIC4_QM0_PQ_STS0_0 0xDE00F0
+
+#define mmNIC4_QM0_PQ_STS0_1 0xDE00F4
+
+#define mmNIC4_QM0_PQ_STS0_2 0xDE00F8
+
+#define mmNIC4_QM0_PQ_STS0_3 0xDE00FC
+
+#define mmNIC4_QM0_PQ_STS1_0 0xDE0100
+
+#define mmNIC4_QM0_PQ_STS1_1 0xDE0104
+
+#define mmNIC4_QM0_PQ_STS1_2 0xDE0108
+
+#define mmNIC4_QM0_PQ_STS1_3 0xDE010C
+
+#define mmNIC4_QM0_CQ_CFG0_0 0xDE0110
+
+#define mmNIC4_QM0_CQ_CFG0_1 0xDE0114
+
+#define mmNIC4_QM0_CQ_CFG0_2 0xDE0118
+
+#define mmNIC4_QM0_CQ_CFG0_3 0xDE011C
+
+#define mmNIC4_QM0_CQ_CFG0_4 0xDE0120
+
+#define mmNIC4_QM0_CQ_CFG1_0 0xDE0124
+
+#define mmNIC4_QM0_CQ_CFG1_1 0xDE0128
+
+#define mmNIC4_QM0_CQ_CFG1_2 0xDE012C
+
+#define mmNIC4_QM0_CQ_CFG1_3 0xDE0130
+
+#define mmNIC4_QM0_CQ_CFG1_4 0xDE0134
+
+#define mmNIC4_QM0_CQ_ARUSER_31_11_0 0xDE0138
+
+#define mmNIC4_QM0_CQ_ARUSER_31_11_1 0xDE013C
+
+#define mmNIC4_QM0_CQ_ARUSER_31_11_2 0xDE0140
+
+#define mmNIC4_QM0_CQ_ARUSER_31_11_3 0xDE0144
+
+#define mmNIC4_QM0_CQ_ARUSER_31_11_4 0xDE0148
+
+#define mmNIC4_QM0_CQ_STS0_0 0xDE014C
+
+#define mmNIC4_QM0_CQ_STS0_1 0xDE0150
+
+#define mmNIC4_QM0_CQ_STS0_2 0xDE0154
+
+#define mmNIC4_QM0_CQ_STS0_3 0xDE0158
+
+#define mmNIC4_QM0_CQ_STS0_4 0xDE015C
+
+#define mmNIC4_QM0_CQ_STS1_0 0xDE0160
+
+#define mmNIC4_QM0_CQ_STS1_1 0xDE0164
+
+#define mmNIC4_QM0_CQ_STS1_2 0xDE0168
+
+#define mmNIC4_QM0_CQ_STS1_3 0xDE016C
+
+#define mmNIC4_QM0_CQ_STS1_4 0xDE0170
+
+#define mmNIC4_QM0_CQ_PTR_LO_0 0xDE0174
+
+#define mmNIC4_QM0_CQ_PTR_HI_0 0xDE0178
+
+#define mmNIC4_QM0_CQ_TSIZE_0 0xDE017C
+
+#define mmNIC4_QM0_CQ_CTL_0 0xDE0180
+
+#define mmNIC4_QM0_CQ_PTR_LO_1 0xDE0184
+
+#define mmNIC4_QM0_CQ_PTR_HI_1 0xDE0188
+
+#define mmNIC4_QM0_CQ_TSIZE_1 0xDE018C
+
+#define mmNIC4_QM0_CQ_CTL_1 0xDE0190
+
+#define mmNIC4_QM0_CQ_PTR_LO_2 0xDE0194
+
+#define mmNIC4_QM0_CQ_PTR_HI_2 0xDE0198
+
+#define mmNIC4_QM0_CQ_TSIZE_2 0xDE019C
+
+#define mmNIC4_QM0_CQ_CTL_2 0xDE01A0
+
+#define mmNIC4_QM0_CQ_PTR_LO_3 0xDE01A4
+
+#define mmNIC4_QM0_CQ_PTR_HI_3 0xDE01A8
+
+#define mmNIC4_QM0_CQ_TSIZE_3 0xDE01AC
+
+#define mmNIC4_QM0_CQ_CTL_3 0xDE01B0
+
+#define mmNIC4_QM0_CQ_PTR_LO_4 0xDE01B4
+
+#define mmNIC4_QM0_CQ_PTR_HI_4 0xDE01B8
+
+#define mmNIC4_QM0_CQ_TSIZE_4 0xDE01BC
+
+#define mmNIC4_QM0_CQ_CTL_4 0xDE01C0
+
+#define mmNIC4_QM0_CQ_PTR_LO_STS_0 0xDE01C4
+
+#define mmNIC4_QM0_CQ_PTR_LO_STS_1 0xDE01C8
+
+#define mmNIC4_QM0_CQ_PTR_LO_STS_2 0xDE01CC
+
+#define mmNIC4_QM0_CQ_PTR_LO_STS_3 0xDE01D0
+
+#define mmNIC4_QM0_CQ_PTR_LO_STS_4 0xDE01D4
+
+#define mmNIC4_QM0_CQ_PTR_HI_STS_0 0xDE01D8
+
+#define mmNIC4_QM0_CQ_PTR_HI_STS_1 0xDE01DC
+
+#define mmNIC4_QM0_CQ_PTR_HI_STS_2 0xDE01E0
+
+#define mmNIC4_QM0_CQ_PTR_HI_STS_3 0xDE01E4
+
+#define mmNIC4_QM0_CQ_PTR_HI_STS_4 0xDE01E8
+
+#define mmNIC4_QM0_CQ_TSIZE_STS_0 0xDE01EC
+
+#define mmNIC4_QM0_CQ_TSIZE_STS_1 0xDE01F0
+
+#define mmNIC4_QM0_CQ_TSIZE_STS_2 0xDE01F4
+
+#define mmNIC4_QM0_CQ_TSIZE_STS_3 0xDE01F8
+
+#define mmNIC4_QM0_CQ_TSIZE_STS_4 0xDE01FC
+
+#define mmNIC4_QM0_CQ_CTL_STS_0 0xDE0200
+
+#define mmNIC4_QM0_CQ_CTL_STS_1 0xDE0204
+
+#define mmNIC4_QM0_CQ_CTL_STS_2 0xDE0208
+
+#define mmNIC4_QM0_CQ_CTL_STS_3 0xDE020C
+
+#define mmNIC4_QM0_CQ_CTL_STS_4 0xDE0210
+
+#define mmNIC4_QM0_CQ_IFIFO_CNT_0 0xDE0214
+
+#define mmNIC4_QM0_CQ_IFIFO_CNT_1 0xDE0218
+
+#define mmNIC4_QM0_CQ_IFIFO_CNT_2 0xDE021C
+
+#define mmNIC4_QM0_CQ_IFIFO_CNT_3 0xDE0220
+
+#define mmNIC4_QM0_CQ_IFIFO_CNT_4 0xDE0224
+
+#define mmNIC4_QM0_CP_MSG_BASE0_ADDR_LO_0 0xDE0228
+
+#define mmNIC4_QM0_CP_MSG_BASE0_ADDR_LO_1 0xDE022C
+
+#define mmNIC4_QM0_CP_MSG_BASE0_ADDR_LO_2 0xDE0230
+
+#define mmNIC4_QM0_CP_MSG_BASE0_ADDR_LO_3 0xDE0234
+
+#define mmNIC4_QM0_CP_MSG_BASE0_ADDR_LO_4 0xDE0238
+
+#define mmNIC4_QM0_CP_MSG_BASE0_ADDR_HI_0 0xDE023C
+
+#define mmNIC4_QM0_CP_MSG_BASE0_ADDR_HI_1 0xDE0240
+
+#define mmNIC4_QM0_CP_MSG_BASE0_ADDR_HI_2 0xDE0244
+
+#define mmNIC4_QM0_CP_MSG_BASE0_ADDR_HI_3 0xDE0248
+
+#define mmNIC4_QM0_CP_MSG_BASE0_ADDR_HI_4 0xDE024C
+
+#define mmNIC4_QM0_CP_MSG_BASE1_ADDR_LO_0 0xDE0250
+
+#define mmNIC4_QM0_CP_MSG_BASE1_ADDR_LO_1 0xDE0254
+
+#define mmNIC4_QM0_CP_MSG_BASE1_ADDR_LO_2 0xDE0258
+
+#define mmNIC4_QM0_CP_MSG_BASE1_ADDR_LO_3 0xDE025C
+
+#define mmNIC4_QM0_CP_MSG_BASE1_ADDR_LO_4 0xDE0260
+
+#define mmNIC4_QM0_CP_MSG_BASE1_ADDR_HI_0 0xDE0264
+
+#define mmNIC4_QM0_CP_MSG_BASE1_ADDR_HI_1 0xDE0268
+
+#define mmNIC4_QM0_CP_MSG_BASE1_ADDR_HI_2 0xDE026C
+
+#define mmNIC4_QM0_CP_MSG_BASE1_ADDR_HI_3 0xDE0270
+
+#define mmNIC4_QM0_CP_MSG_BASE1_ADDR_HI_4 0xDE0274
+
+#define mmNIC4_QM0_CP_MSG_BASE2_ADDR_LO_0 0xDE0278
+
+#define mmNIC4_QM0_CP_MSG_BASE2_ADDR_LO_1 0xDE027C
+
+#define mmNIC4_QM0_CP_MSG_BASE2_ADDR_LO_2 0xDE0280
+
+#define mmNIC4_QM0_CP_MSG_BASE2_ADDR_LO_3 0xDE0284
+
+#define mmNIC4_QM0_CP_MSG_BASE2_ADDR_LO_4 0xDE0288
+
+#define mmNIC4_QM0_CP_MSG_BASE2_ADDR_HI_0 0xDE028C
+
+#define mmNIC4_QM0_CP_MSG_BASE2_ADDR_HI_1 0xDE0290
+
+#define mmNIC4_QM0_CP_MSG_BASE2_ADDR_HI_2 0xDE0294
+
+#define mmNIC4_QM0_CP_MSG_BASE2_ADDR_HI_3 0xDE0298
+
+#define mmNIC4_QM0_CP_MSG_BASE2_ADDR_HI_4 0xDE029C
+
+#define mmNIC4_QM0_CP_MSG_BASE3_ADDR_LO_0 0xDE02A0
+
+#define mmNIC4_QM0_CP_MSG_BASE3_ADDR_LO_1 0xDE02A4
+
+#define mmNIC4_QM0_CP_MSG_BASE3_ADDR_LO_2 0xDE02A8
+
+#define mmNIC4_QM0_CP_MSG_BASE3_ADDR_LO_3 0xDE02AC
+
+#define mmNIC4_QM0_CP_MSG_BASE3_ADDR_LO_4 0xDE02B0
+
+#define mmNIC4_QM0_CP_MSG_BASE3_ADDR_HI_0 0xDE02B4
+
+#define mmNIC4_QM0_CP_MSG_BASE3_ADDR_HI_1 0xDE02B8
+
+#define mmNIC4_QM0_CP_MSG_BASE3_ADDR_HI_2 0xDE02BC
+
+#define mmNIC4_QM0_CP_MSG_BASE3_ADDR_HI_3 0xDE02C0
+
+#define mmNIC4_QM0_CP_MSG_BASE3_ADDR_HI_4 0xDE02C4
+
+#define mmNIC4_QM0_CP_LDMA_TSIZE_OFFSET_0 0xDE02C8
+
+#define mmNIC4_QM0_CP_LDMA_TSIZE_OFFSET_1 0xDE02CC
+
+#define mmNIC4_QM0_CP_LDMA_TSIZE_OFFSET_2 0xDE02D0
+
+#define mmNIC4_QM0_CP_LDMA_TSIZE_OFFSET_3 0xDE02D4
+
+#define mmNIC4_QM0_CP_LDMA_TSIZE_OFFSET_4 0xDE02D8
+
+#define mmNIC4_QM0_CP_LDMA_SRC_BASE_LO_OFFSET_0 0xDE02E0
+
+#define mmNIC4_QM0_CP_LDMA_SRC_BASE_LO_OFFSET_1 0xDE02E4
+
+#define mmNIC4_QM0_CP_LDMA_SRC_BASE_LO_OFFSET_2 0xDE02E8
+
+#define mmNIC4_QM0_CP_LDMA_SRC_BASE_LO_OFFSET_3 0xDE02EC
+
+#define mmNIC4_QM0_CP_LDMA_SRC_BASE_LO_OFFSET_4 0xDE02F0
+
+#define mmNIC4_QM0_CP_LDMA_DST_BASE_LO_OFFSET_0 0xDE02F4
+
+#define mmNIC4_QM0_CP_LDMA_DST_BASE_LO_OFFSET_1 0xDE02F8
+
+#define mmNIC4_QM0_CP_LDMA_DST_BASE_LO_OFFSET_2 0xDE02FC
+
+#define mmNIC4_QM0_CP_LDMA_DST_BASE_LO_OFFSET_3 0xDE0300
+
+#define mmNIC4_QM0_CP_LDMA_DST_BASE_LO_OFFSET_4 0xDE0304
+
+#define mmNIC4_QM0_CP_FENCE0_RDATA_0 0xDE0308
+
+#define mmNIC4_QM0_CP_FENCE0_RDATA_1 0xDE030C
+
+#define mmNIC4_QM0_CP_FENCE0_RDATA_2 0xDE0310
+
+#define mmNIC4_QM0_CP_FENCE0_RDATA_3 0xDE0314
+
+#define mmNIC4_QM0_CP_FENCE0_RDATA_4 0xDE0318
+
+#define mmNIC4_QM0_CP_FENCE1_RDATA_0 0xDE031C
+
+#define mmNIC4_QM0_CP_FENCE1_RDATA_1 0xDE0320
+
+#define mmNIC4_QM0_CP_FENCE1_RDATA_2 0xDE0324
+
+#define mmNIC4_QM0_CP_FENCE1_RDATA_3 0xDE0328
+
+#define mmNIC4_QM0_CP_FENCE1_RDATA_4 0xDE032C
+
+#define mmNIC4_QM0_CP_FENCE2_RDATA_0 0xDE0330
+
+#define mmNIC4_QM0_CP_FENCE2_RDATA_1 0xDE0334
+
+#define mmNIC4_QM0_CP_FENCE2_RDATA_2 0xDE0338
+
+#define mmNIC4_QM0_CP_FENCE2_RDATA_3 0xDE033C
+
+#define mmNIC4_QM0_CP_FENCE2_RDATA_4 0xDE0340
+
+#define mmNIC4_QM0_CP_FENCE3_RDATA_0 0xDE0344
+
+#define mmNIC4_QM0_CP_FENCE3_RDATA_1 0xDE0348
+
+#define mmNIC4_QM0_CP_FENCE3_RDATA_2 0xDE034C
+
+#define mmNIC4_QM0_CP_FENCE3_RDATA_3 0xDE0350
+
+#define mmNIC4_QM0_CP_FENCE3_RDATA_4 0xDE0354
+
+#define mmNIC4_QM0_CP_FENCE0_CNT_0 0xDE0358
+
+#define mmNIC4_QM0_CP_FENCE0_CNT_1 0xDE035C
+
+#define mmNIC4_QM0_CP_FENCE0_CNT_2 0xDE0360
+
+#define mmNIC4_QM0_CP_FENCE0_CNT_3 0xDE0364
+
+#define mmNIC4_QM0_CP_FENCE0_CNT_4 0xDE0368
+
+#define mmNIC4_QM0_CP_FENCE1_CNT_0 0xDE036C
+
+#define mmNIC4_QM0_CP_FENCE1_CNT_1 0xDE0370
+
+#define mmNIC4_QM0_CP_FENCE1_CNT_2 0xDE0374
+
+#define mmNIC4_QM0_CP_FENCE1_CNT_3 0xDE0378
+
+#define mmNIC4_QM0_CP_FENCE1_CNT_4 0xDE037C
+
+#define mmNIC4_QM0_CP_FENCE2_CNT_0 0xDE0380
+
+#define mmNIC4_QM0_CP_FENCE2_CNT_1 0xDE0384
+
+#define mmNIC4_QM0_CP_FENCE2_CNT_2 0xDE0388
+
+#define mmNIC4_QM0_CP_FENCE2_CNT_3 0xDE038C
+
+#define mmNIC4_QM0_CP_FENCE2_CNT_4 0xDE0390
+
+#define mmNIC4_QM0_CP_FENCE3_CNT_0 0xDE0394
+
+#define mmNIC4_QM0_CP_FENCE3_CNT_1 0xDE0398
+
+#define mmNIC4_QM0_CP_FENCE3_CNT_2 0xDE039C
+
+#define mmNIC4_QM0_CP_FENCE3_CNT_3 0xDE03A0
+
+#define mmNIC4_QM0_CP_FENCE3_CNT_4 0xDE03A4
+
+#define mmNIC4_QM0_CP_STS_0 0xDE03A8
+
+#define mmNIC4_QM0_CP_STS_1 0xDE03AC
+
+#define mmNIC4_QM0_CP_STS_2 0xDE03B0
+
+#define mmNIC4_QM0_CP_STS_3 0xDE03B4
+
+#define mmNIC4_QM0_CP_STS_4 0xDE03B8
+
+#define mmNIC4_QM0_CP_CURRENT_INST_LO_0 0xDE03BC
+
+#define mmNIC4_QM0_CP_CURRENT_INST_LO_1 0xDE03C0
+
+#define mmNIC4_QM0_CP_CURRENT_INST_LO_2 0xDE03C4
+
+#define mmNIC4_QM0_CP_CURRENT_INST_LO_3 0xDE03C8
+
+#define mmNIC4_QM0_CP_CURRENT_INST_LO_4 0xDE03CC
+
+#define mmNIC4_QM0_CP_CURRENT_INST_HI_0 0xDE03D0
+
+#define mmNIC4_QM0_CP_CURRENT_INST_HI_1 0xDE03D4
+
+#define mmNIC4_QM0_CP_CURRENT_INST_HI_2 0xDE03D8
+
+#define mmNIC4_QM0_CP_CURRENT_INST_HI_3 0xDE03DC
+
+#define mmNIC4_QM0_CP_CURRENT_INST_HI_4 0xDE03E0
+
+#define mmNIC4_QM0_CP_BARRIER_CFG_0 0xDE03F4
+
+#define mmNIC4_QM0_CP_BARRIER_CFG_1 0xDE03F8
+
+#define mmNIC4_QM0_CP_BARRIER_CFG_2 0xDE03FC
+
+#define mmNIC4_QM0_CP_BARRIER_CFG_3 0xDE0400
+
+#define mmNIC4_QM0_CP_BARRIER_CFG_4 0xDE0404
+
+#define mmNIC4_QM0_CP_DBG_0_0 0xDE0408
+
+#define mmNIC4_QM0_CP_DBG_0_1 0xDE040C
+
+#define mmNIC4_QM0_CP_DBG_0_2 0xDE0410
+
+#define mmNIC4_QM0_CP_DBG_0_3 0xDE0414
+
+#define mmNIC4_QM0_CP_DBG_0_4 0xDE0418
+
+#define mmNIC4_QM0_CP_ARUSER_31_11_0 0xDE041C
+
+#define mmNIC4_QM0_CP_ARUSER_31_11_1 0xDE0420
+
+#define mmNIC4_QM0_CP_ARUSER_31_11_2 0xDE0424
+
+#define mmNIC4_QM0_CP_ARUSER_31_11_3 0xDE0428
+
+#define mmNIC4_QM0_CP_ARUSER_31_11_4 0xDE042C
+
+#define mmNIC4_QM0_CP_AWUSER_31_11_0 0xDE0430
+
+#define mmNIC4_QM0_CP_AWUSER_31_11_1 0xDE0434
+
+#define mmNIC4_QM0_CP_AWUSER_31_11_2 0xDE0438
+
+#define mmNIC4_QM0_CP_AWUSER_31_11_3 0xDE043C
+
+#define mmNIC4_QM0_CP_AWUSER_31_11_4 0xDE0440
+
+#define mmNIC4_QM0_ARB_CFG_0 0xDE0A00
+
+#define mmNIC4_QM0_ARB_CHOISE_Q_PUSH 0xDE0A04
+
+#define mmNIC4_QM0_ARB_WRR_WEIGHT_0 0xDE0A08
+
+#define mmNIC4_QM0_ARB_WRR_WEIGHT_1 0xDE0A0C
+
+#define mmNIC4_QM0_ARB_WRR_WEIGHT_2 0xDE0A10
+
+#define mmNIC4_QM0_ARB_WRR_WEIGHT_3 0xDE0A14
+
+#define mmNIC4_QM0_ARB_CFG_1 0xDE0A18
+
+#define mmNIC4_QM0_ARB_MST_AVAIL_CRED_0 0xDE0A20
+
+#define mmNIC4_QM0_ARB_MST_AVAIL_CRED_1 0xDE0A24
+
+#define mmNIC4_QM0_ARB_MST_AVAIL_CRED_2 0xDE0A28
+
+#define mmNIC4_QM0_ARB_MST_AVAIL_CRED_3 0xDE0A2C
+
+#define mmNIC4_QM0_ARB_MST_AVAIL_CRED_4 0xDE0A30
+
+#define mmNIC4_QM0_ARB_MST_AVAIL_CRED_5 0xDE0A34
+
+#define mmNIC4_QM0_ARB_MST_AVAIL_CRED_6 0xDE0A38
+
+#define mmNIC4_QM0_ARB_MST_AVAIL_CRED_7 0xDE0A3C
+
+#define mmNIC4_QM0_ARB_MST_AVAIL_CRED_8 0xDE0A40
+
+#define mmNIC4_QM0_ARB_MST_AVAIL_CRED_9 0xDE0A44
+
+#define mmNIC4_QM0_ARB_MST_AVAIL_CRED_10 0xDE0A48
+
+#define mmNIC4_QM0_ARB_MST_AVAIL_CRED_11 0xDE0A4C
+
+#define mmNIC4_QM0_ARB_MST_AVAIL_CRED_12 0xDE0A50
+
+#define mmNIC4_QM0_ARB_MST_AVAIL_CRED_13 0xDE0A54
+
+#define mmNIC4_QM0_ARB_MST_AVAIL_CRED_14 0xDE0A58
+
+#define mmNIC4_QM0_ARB_MST_AVAIL_CRED_15 0xDE0A5C
+
+#define mmNIC4_QM0_ARB_MST_AVAIL_CRED_16 0xDE0A60
+
+#define mmNIC4_QM0_ARB_MST_AVAIL_CRED_17 0xDE0A64
+
+#define mmNIC4_QM0_ARB_MST_AVAIL_CRED_18 0xDE0A68
+
+#define mmNIC4_QM0_ARB_MST_AVAIL_CRED_19 0xDE0A6C
+
+#define mmNIC4_QM0_ARB_MST_AVAIL_CRED_20 0xDE0A70
+
+#define mmNIC4_QM0_ARB_MST_AVAIL_CRED_21 0xDE0A74
+
+#define mmNIC4_QM0_ARB_MST_AVAIL_CRED_22 0xDE0A78
+
+#define mmNIC4_QM0_ARB_MST_AVAIL_CRED_23 0xDE0A7C
+
+#define mmNIC4_QM0_ARB_MST_AVAIL_CRED_24 0xDE0A80
+
+#define mmNIC4_QM0_ARB_MST_AVAIL_CRED_25 0xDE0A84
+
+#define mmNIC4_QM0_ARB_MST_AVAIL_CRED_26 0xDE0A88
+
+#define mmNIC4_QM0_ARB_MST_AVAIL_CRED_27 0xDE0A8C
+
+#define mmNIC4_QM0_ARB_MST_AVAIL_CRED_28 0xDE0A90
+
+#define mmNIC4_QM0_ARB_MST_AVAIL_CRED_29 0xDE0A94
+
+#define mmNIC4_QM0_ARB_MST_AVAIL_CRED_30 0xDE0A98
+
+#define mmNIC4_QM0_ARB_MST_AVAIL_CRED_31 0xDE0A9C
+
+#define mmNIC4_QM0_ARB_MST_CRED_INC 0xDE0AA0
+
+#define mmNIC4_QM0_ARB_MST_CHOISE_PUSH_OFST_0 0xDE0AA4
+
+#define mmNIC4_QM0_ARB_MST_CHOISE_PUSH_OFST_1 0xDE0AA8
+
+#define mmNIC4_QM0_ARB_MST_CHOISE_PUSH_OFST_2 0xDE0AAC
+
+#define mmNIC4_QM0_ARB_MST_CHOISE_PUSH_OFST_3 0xDE0AB0
+
+#define mmNIC4_QM0_ARB_MST_CHOISE_PUSH_OFST_4 0xDE0AB4
+
+#define mmNIC4_QM0_ARB_MST_CHOISE_PUSH_OFST_5 0xDE0AB8
+
+#define mmNIC4_QM0_ARB_MST_CHOISE_PUSH_OFST_6 0xDE0ABC
+
+#define mmNIC4_QM0_ARB_MST_CHOISE_PUSH_OFST_7 0xDE0AC0
+
+#define mmNIC4_QM0_ARB_MST_CHOISE_PUSH_OFST_8 0xDE0AC4
+
+#define mmNIC4_QM0_ARB_MST_CHOISE_PUSH_OFST_9 0xDE0AC8
+
+#define mmNIC4_QM0_ARB_MST_CHOISE_PUSH_OFST_10 0xDE0ACC
+
+#define mmNIC4_QM0_ARB_MST_CHOISE_PUSH_OFST_11 0xDE0AD0
+
+#define mmNIC4_QM0_ARB_MST_CHOISE_PUSH_OFST_12 0xDE0AD4
+
+#define mmNIC4_QM0_ARB_MST_CHOISE_PUSH_OFST_13 0xDE0AD8
+
+#define mmNIC4_QM0_ARB_MST_CHOISE_PUSH_OFST_14 0xDE0ADC
+
+#define mmNIC4_QM0_ARB_MST_CHOISE_PUSH_OFST_15 0xDE0AE0
+
+#define mmNIC4_QM0_ARB_MST_CHOISE_PUSH_OFST_16 0xDE0AE4
+
+#define mmNIC4_QM0_ARB_MST_CHOISE_PUSH_OFST_17 0xDE0AE8
+
+#define mmNIC4_QM0_ARB_MST_CHOISE_PUSH_OFST_18 0xDE0AEC
+
+#define mmNIC4_QM0_ARB_MST_CHOISE_PUSH_OFST_19 0xDE0AF0
+
+#define mmNIC4_QM0_ARB_MST_CHOISE_PUSH_OFST_20 0xDE0AF4
+
+#define mmNIC4_QM0_ARB_MST_CHOISE_PUSH_OFST_21 0xDE0AF8
+
+#define mmNIC4_QM0_ARB_MST_CHOISE_PUSH_OFST_22 0xDE0AFC
+
+#define mmNIC4_QM0_ARB_MST_CHOISE_PUSH_OFST_23 0xDE0B00
+
+#define mmNIC4_QM0_ARB_MST_CHOISE_PUSH_OFST_24 0xDE0B04
+
+#define mmNIC4_QM0_ARB_MST_CHOISE_PUSH_OFST_25 0xDE0B08
+
+#define mmNIC4_QM0_ARB_MST_CHOISE_PUSH_OFST_26 0xDE0B0C
+
+#define mmNIC4_QM0_ARB_MST_CHOISE_PUSH_OFST_27 0xDE0B10
+
+#define mmNIC4_QM0_ARB_MST_CHOISE_PUSH_OFST_28 0xDE0B14
+
+#define mmNIC4_QM0_ARB_MST_CHOISE_PUSH_OFST_29 0xDE0B18
+
+#define mmNIC4_QM0_ARB_MST_CHOISE_PUSH_OFST_30 0xDE0B1C
+
+#define mmNIC4_QM0_ARB_MST_CHOISE_PUSH_OFST_31 0xDE0B20
+
+#define mmNIC4_QM0_ARB_SLV_MASTER_INC_CRED_OFST 0xDE0B28
+
+#define mmNIC4_QM0_ARB_MST_SLAVE_EN 0xDE0B2C
+
+#define mmNIC4_QM0_ARB_MST_QUIET_PER 0xDE0B34
+
+#define mmNIC4_QM0_ARB_SLV_CHOISE_WDT 0xDE0B38
+
+#define mmNIC4_QM0_ARB_SLV_ID 0xDE0B3C
+
+#define mmNIC4_QM0_ARB_MSG_MAX_INFLIGHT 0xDE0B44
+
+#define mmNIC4_QM0_ARB_MSG_AWUSER_31_11 0xDE0B48
+
+#define mmNIC4_QM0_ARB_MSG_AWUSER_SEC_PROP 0xDE0B4C
+
+#define mmNIC4_QM0_ARB_MSG_AWUSER_NON_SEC_PROP 0xDE0B50
+
+#define mmNIC4_QM0_ARB_BASE_LO 0xDE0B54
+
+#define mmNIC4_QM0_ARB_BASE_HI 0xDE0B58
+
+#define mmNIC4_QM0_ARB_STATE_STS 0xDE0B80
+
+#define mmNIC4_QM0_ARB_CHOISE_FULLNESS_STS 0xDE0B84
+
+#define mmNIC4_QM0_ARB_MSG_STS 0xDE0B88
+
+#define mmNIC4_QM0_ARB_SLV_CHOISE_Q_HEAD 0xDE0B8C
+
+#define mmNIC4_QM0_ARB_ERR_CAUSE 0xDE0B9C
+
+#define mmNIC4_QM0_ARB_ERR_MSG_EN 0xDE0BA0
+
+#define mmNIC4_QM0_ARB_ERR_STS_DRP 0xDE0BA8
+
+#define mmNIC4_QM0_ARB_MST_CRED_STS_0 0xDE0BB0
+
+#define mmNIC4_QM0_ARB_MST_CRED_STS_1 0xDE0BB4
+
+#define mmNIC4_QM0_ARB_MST_CRED_STS_2 0xDE0BB8
+
+#define mmNIC4_QM0_ARB_MST_CRED_STS_3 0xDE0BBC
+
+#define mmNIC4_QM0_ARB_MST_CRED_STS_4 0xDE0BC0
+
+#define mmNIC4_QM0_ARB_MST_CRED_STS_5 0xDE0BC4
+
+#define mmNIC4_QM0_ARB_MST_CRED_STS_6 0xDE0BC8
+
+#define mmNIC4_QM0_ARB_MST_CRED_STS_7 0xDE0BCC
+
+#define mmNIC4_QM0_ARB_MST_CRED_STS_8 0xDE0BD0
+
+#define mmNIC4_QM0_ARB_MST_CRED_STS_9 0xDE0BD4
+
+#define mmNIC4_QM0_ARB_MST_CRED_STS_10 0xDE0BD8
+
+#define mmNIC4_QM0_ARB_MST_CRED_STS_11 0xDE0BDC
+
+#define mmNIC4_QM0_ARB_MST_CRED_STS_12 0xDE0BE0
+
+#define mmNIC4_QM0_ARB_MST_CRED_STS_13 0xDE0BE4
+
+#define mmNIC4_QM0_ARB_MST_CRED_STS_14 0xDE0BE8
+
+#define mmNIC4_QM0_ARB_MST_CRED_STS_15 0xDE0BEC
+
+#define mmNIC4_QM0_ARB_MST_CRED_STS_16 0xDE0BF0
+
+#define mmNIC4_QM0_ARB_MST_CRED_STS_17 0xDE0BF4
+
+#define mmNIC4_QM0_ARB_MST_CRED_STS_18 0xDE0BF8
+
+#define mmNIC4_QM0_ARB_MST_CRED_STS_19 0xDE0BFC
+
+#define mmNIC4_QM0_ARB_MST_CRED_STS_20 0xDE0C00
+
+#define mmNIC4_QM0_ARB_MST_CRED_STS_21 0xDE0C04
+
+#define mmNIC4_QM0_ARB_MST_CRED_STS_22 0xDE0C08
+
+#define mmNIC4_QM0_ARB_MST_CRED_STS_23 0xDE0C0C
+
+#define mmNIC4_QM0_ARB_MST_CRED_STS_24 0xDE0C10
+
+#define mmNIC4_QM0_ARB_MST_CRED_STS_25 0xDE0C14
+
+#define mmNIC4_QM0_ARB_MST_CRED_STS_26 0xDE0C18
+
+#define mmNIC4_QM0_ARB_MST_CRED_STS_27 0xDE0C1C
+
+#define mmNIC4_QM0_ARB_MST_CRED_STS_28 0xDE0C20
+
+#define mmNIC4_QM0_ARB_MST_CRED_STS_29 0xDE0C24
+
+#define mmNIC4_QM0_ARB_MST_CRED_STS_30 0xDE0C28
+
+#define mmNIC4_QM0_ARB_MST_CRED_STS_31 0xDE0C2C
+
+#define mmNIC4_QM0_CGM_CFG 0xDE0C70
+
+#define mmNIC4_QM0_CGM_STS 0xDE0C74
+
+#define mmNIC4_QM0_CGM_CFG1 0xDE0C78
+
+#define mmNIC4_QM0_LOCAL_RANGE_BASE 0xDE0C80
+
+#define mmNIC4_QM0_LOCAL_RANGE_SIZE 0xDE0C84
+
+#define mmNIC4_QM0_CSMR_STRICT_PRIO_CFG 0xDE0C90
+
+#define mmNIC4_QM0_HBW_RD_RATE_LIM_CFG_1 0xDE0C94
+
+#define mmNIC4_QM0_LBW_WR_RATE_LIM_CFG_0 0xDE0C98
+
+#define mmNIC4_QM0_LBW_WR_RATE_LIM_CFG_1 0xDE0C9C
+
+#define mmNIC4_QM0_HBW_RD_RATE_LIM_CFG_0 0xDE0CA0
+
+#define mmNIC4_QM0_GLBL_AXCACHE 0xDE0CA4
+
+#define mmNIC4_QM0_IND_GW_APB_CFG 0xDE0CB0
+
+#define mmNIC4_QM0_IND_GW_APB_WDATA 0xDE0CB4
+
+#define mmNIC4_QM0_IND_GW_APB_RDATA 0xDE0CB8
+
+#define mmNIC4_QM0_IND_GW_APB_STATUS 0xDE0CBC
+
+#define mmNIC4_QM0_GLBL_ERR_ADDR_LO 0xDE0CD0
+
+#define mmNIC4_QM0_GLBL_ERR_ADDR_HI 0xDE0CD4
+
+#define mmNIC4_QM0_GLBL_ERR_WDATA 0xDE0CD8
+
+#define mmNIC4_QM0_GLBL_MEM_INIT_BUSY 0xDE0D00
+
+#endif /* ASIC_REG_NIC4_QM0_REGS_H_ */
diff --git a/drivers/accel/habanalabs/include/gaudi/asic_reg/nic4_qm1_regs.h b/drivers/accel/habanalabs/include/gaudi/asic_reg/nic4_qm1_regs.h
new file mode 100644
index 0000000000..34b21b21da
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi/asic_reg/nic4_qm1_regs.h
@@ -0,0 +1,834 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2016-2018 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ ** DO NOT EDIT BELOW **
+ ************************************/
+
+#ifndef ASIC_REG_NIC4_QM1_REGS_H_
+#define ASIC_REG_NIC4_QM1_REGS_H_
+
+/*
+ *****************************************
+ * NIC4_QM1 (Prototype: QMAN)
+ *****************************************
+ */
+
+#define mmNIC4_QM1_GLBL_CFG0 0xDE2000
+
+#define mmNIC4_QM1_GLBL_CFG1 0xDE2004
+
+#define mmNIC4_QM1_GLBL_PROT 0xDE2008
+
+#define mmNIC4_QM1_GLBL_ERR_CFG 0xDE200C
+
+#define mmNIC4_QM1_GLBL_SECURE_PROPS_0 0xDE2010
+
+#define mmNIC4_QM1_GLBL_SECURE_PROPS_1 0xDE2014
+
+#define mmNIC4_QM1_GLBL_SECURE_PROPS_2 0xDE2018
+
+#define mmNIC4_QM1_GLBL_SECURE_PROPS_3 0xDE201C
+
+#define mmNIC4_QM1_GLBL_SECURE_PROPS_4 0xDE2020
+
+#define mmNIC4_QM1_GLBL_NON_SECURE_PROPS_0 0xDE2024
+
+#define mmNIC4_QM1_GLBL_NON_SECURE_PROPS_1 0xDE2028
+
+#define mmNIC4_QM1_GLBL_NON_SECURE_PROPS_2 0xDE202C
+
+#define mmNIC4_QM1_GLBL_NON_SECURE_PROPS_3 0xDE2030
+
+#define mmNIC4_QM1_GLBL_NON_SECURE_PROPS_4 0xDE2034
+
+#define mmNIC4_QM1_GLBL_STS0 0xDE2038
+
+#define mmNIC4_QM1_GLBL_STS1_0 0xDE2040
+
+#define mmNIC4_QM1_GLBL_STS1_1 0xDE2044
+
+#define mmNIC4_QM1_GLBL_STS1_2 0xDE2048
+
+#define mmNIC4_QM1_GLBL_STS1_3 0xDE204C
+
+#define mmNIC4_QM1_GLBL_STS1_4 0xDE2050
+
+#define mmNIC4_QM1_GLBL_MSG_EN_0 0xDE2054
+
+#define mmNIC4_QM1_GLBL_MSG_EN_1 0xDE2058
+
+#define mmNIC4_QM1_GLBL_MSG_EN_2 0xDE205C
+
+#define mmNIC4_QM1_GLBL_MSG_EN_3 0xDE2060
+
+#define mmNIC4_QM1_GLBL_MSG_EN_4 0xDE2068
+
+#define mmNIC4_QM1_PQ_BASE_LO_0 0xDE2070
+
+#define mmNIC4_QM1_PQ_BASE_LO_1 0xDE2074
+
+#define mmNIC4_QM1_PQ_BASE_LO_2 0xDE2078
+
+#define mmNIC4_QM1_PQ_BASE_LO_3 0xDE207C
+
+#define mmNIC4_QM1_PQ_BASE_HI_0 0xDE2080
+
+#define mmNIC4_QM1_PQ_BASE_HI_1 0xDE2084
+
+#define mmNIC4_QM1_PQ_BASE_HI_2 0xDE2088
+
+#define mmNIC4_QM1_PQ_BASE_HI_3 0xDE208C
+
+#define mmNIC4_QM1_PQ_SIZE_0 0xDE2090
+
+#define mmNIC4_QM1_PQ_SIZE_1 0xDE2094
+
+#define mmNIC4_QM1_PQ_SIZE_2 0xDE2098
+
+#define mmNIC4_QM1_PQ_SIZE_3 0xDE209C
+
+#define mmNIC4_QM1_PQ_PI_0 0xDE20A0
+
+#define mmNIC4_QM1_PQ_PI_1 0xDE20A4
+
+#define mmNIC4_QM1_PQ_PI_2 0xDE20A8
+
+#define mmNIC4_QM1_PQ_PI_3 0xDE20AC
+
+#define mmNIC4_QM1_PQ_CI_0 0xDE20B0
+
+#define mmNIC4_QM1_PQ_CI_1 0xDE20B4
+
+#define mmNIC4_QM1_PQ_CI_2 0xDE20B8
+
+#define mmNIC4_QM1_PQ_CI_3 0xDE20BC
+
+#define mmNIC4_QM1_PQ_CFG0_0 0xDE20C0
+
+#define mmNIC4_QM1_PQ_CFG0_1 0xDE20C4
+
+#define mmNIC4_QM1_PQ_CFG0_2 0xDE20C8
+
+#define mmNIC4_QM1_PQ_CFG0_3 0xDE20CC
+
+#define mmNIC4_QM1_PQ_CFG1_0 0xDE20D0
+
+#define mmNIC4_QM1_PQ_CFG1_1 0xDE20D4
+
+#define mmNIC4_QM1_PQ_CFG1_2 0xDE20D8
+
+#define mmNIC4_QM1_PQ_CFG1_3 0xDE20DC
+
+#define mmNIC4_QM1_PQ_ARUSER_31_11_0 0xDE20E0
+
+#define mmNIC4_QM1_PQ_ARUSER_31_11_1 0xDE20E4
+
+#define mmNIC4_QM1_PQ_ARUSER_31_11_2 0xDE20E8
+
+#define mmNIC4_QM1_PQ_ARUSER_31_11_3 0xDE20EC
+
+#define mmNIC4_QM1_PQ_STS0_0 0xDE20F0
+
+#define mmNIC4_QM1_PQ_STS0_1 0xDE20F4
+
+#define mmNIC4_QM1_PQ_STS0_2 0xDE20F8
+
+#define mmNIC4_QM1_PQ_STS0_3 0xDE20FC
+
+#define mmNIC4_QM1_PQ_STS1_0 0xDE2100
+
+#define mmNIC4_QM1_PQ_STS1_1 0xDE2104
+
+#define mmNIC4_QM1_PQ_STS1_2 0xDE2108
+
+#define mmNIC4_QM1_PQ_STS1_3 0xDE210C
+
+#define mmNIC4_QM1_CQ_CFG0_0 0xDE2110
+
+#define mmNIC4_QM1_CQ_CFG0_1 0xDE2114
+
+#define mmNIC4_QM1_CQ_CFG0_2 0xDE2118
+
+#define mmNIC4_QM1_CQ_CFG0_3 0xDE211C
+
+#define mmNIC4_QM1_CQ_CFG0_4 0xDE2120
+
+#define mmNIC4_QM1_CQ_CFG1_0 0xDE2124
+
+#define mmNIC4_QM1_CQ_CFG1_1 0xDE2128
+
+#define mmNIC4_QM1_CQ_CFG1_2 0xDE212C
+
+#define mmNIC4_QM1_CQ_CFG1_3 0xDE2130
+
+#define mmNIC4_QM1_CQ_CFG1_4 0xDE2134
+
+#define mmNIC4_QM1_CQ_ARUSER_31_11_0 0xDE2138
+
+#define mmNIC4_QM1_CQ_ARUSER_31_11_1 0xDE213C
+
+#define mmNIC4_QM1_CQ_ARUSER_31_11_2 0xDE2140
+
+#define mmNIC4_QM1_CQ_ARUSER_31_11_3 0xDE2144
+
+#define mmNIC4_QM1_CQ_ARUSER_31_11_4 0xDE2148
+
+#define mmNIC4_QM1_CQ_STS0_0 0xDE214C
+
+#define mmNIC4_QM1_CQ_STS0_1 0xDE2150
+
+#define mmNIC4_QM1_CQ_STS0_2 0xDE2154
+
+#define mmNIC4_QM1_CQ_STS0_3 0xDE2158
+
+#define mmNIC4_QM1_CQ_STS0_4 0xDE215C
+
+#define mmNIC4_QM1_CQ_STS1_0 0xDE2160
+
+#define mmNIC4_QM1_CQ_STS1_1 0xDE2164
+
+#define mmNIC4_QM1_CQ_STS1_2 0xDE2168
+
+#define mmNIC4_QM1_CQ_STS1_3 0xDE216C
+
+#define mmNIC4_QM1_CQ_STS1_4 0xDE2170
+
+#define mmNIC4_QM1_CQ_PTR_LO_0 0xDE2174
+
+#define mmNIC4_QM1_CQ_PTR_HI_0 0xDE2178
+
+#define mmNIC4_QM1_CQ_TSIZE_0 0xDE217C
+
+#define mmNIC4_QM1_CQ_CTL_0 0xDE2180
+
+#define mmNIC4_QM1_CQ_PTR_LO_1 0xDE2184
+
+#define mmNIC4_QM1_CQ_PTR_HI_1 0xDE2188
+
+#define mmNIC4_QM1_CQ_TSIZE_1 0xDE218C
+
+#define mmNIC4_QM1_CQ_CTL_1 0xDE2190
+
+#define mmNIC4_QM1_CQ_PTR_LO_2 0xDE2194
+
+#define mmNIC4_QM1_CQ_PTR_HI_2 0xDE2198
+
+#define mmNIC4_QM1_CQ_TSIZE_2 0xDE219C
+
+#define mmNIC4_QM1_CQ_CTL_2 0xDE21A0
+
+#define mmNIC4_QM1_CQ_PTR_LO_3 0xDE21A4
+
+#define mmNIC4_QM1_CQ_PTR_HI_3 0xDE21A8
+
+#define mmNIC4_QM1_CQ_TSIZE_3 0xDE21AC
+
+#define mmNIC4_QM1_CQ_CTL_3 0xDE21B0
+
+#define mmNIC4_QM1_CQ_PTR_LO_4 0xDE21B4
+
+#define mmNIC4_QM1_CQ_PTR_HI_4 0xDE21B8
+
+#define mmNIC4_QM1_CQ_TSIZE_4 0xDE21BC
+
+#define mmNIC4_QM1_CQ_CTL_4 0xDE21C0
+
+#define mmNIC4_QM1_CQ_PTR_LO_STS_0 0xDE21C4
+
+#define mmNIC4_QM1_CQ_PTR_LO_STS_1 0xDE21C8
+
+#define mmNIC4_QM1_CQ_PTR_LO_STS_2 0xDE21CC
+
+#define mmNIC4_QM1_CQ_PTR_LO_STS_3 0xDE21D0
+
+#define mmNIC4_QM1_CQ_PTR_LO_STS_4 0xDE21D4
+
+#define mmNIC4_QM1_CQ_PTR_HI_STS_0 0xDE21D8
+
+#define mmNIC4_QM1_CQ_PTR_HI_STS_1 0xDE21DC
+
+#define mmNIC4_QM1_CQ_PTR_HI_STS_2 0xDE21E0
+
+#define mmNIC4_QM1_CQ_PTR_HI_STS_3 0xDE21E4
+
+#define mmNIC4_QM1_CQ_PTR_HI_STS_4 0xDE21E8
+
+#define mmNIC4_QM1_CQ_TSIZE_STS_0 0xDE21EC
+
+#define mmNIC4_QM1_CQ_TSIZE_STS_1 0xDE21F0
+
+#define mmNIC4_QM1_CQ_TSIZE_STS_2 0xDE21F4
+
+#define mmNIC4_QM1_CQ_TSIZE_STS_3 0xDE21F8
+
+#define mmNIC4_QM1_CQ_TSIZE_STS_4 0xDE21FC
+
+#define mmNIC4_QM1_CQ_CTL_STS_0 0xDE2200
+
+#define mmNIC4_QM1_CQ_CTL_STS_1 0xDE2204
+
+#define mmNIC4_QM1_CQ_CTL_STS_2 0xDE2208
+
+#define mmNIC4_QM1_CQ_CTL_STS_3 0xDE220C
+
+#define mmNIC4_QM1_CQ_CTL_STS_4 0xDE2210
+
+#define mmNIC4_QM1_CQ_IFIFO_CNT_0 0xDE2214
+
+#define mmNIC4_QM1_CQ_IFIFO_CNT_1 0xDE2218
+
+#define mmNIC4_QM1_CQ_IFIFO_CNT_2 0xDE221C
+
+#define mmNIC4_QM1_CQ_IFIFO_CNT_3 0xDE2220
+
+#define mmNIC4_QM1_CQ_IFIFO_CNT_4 0xDE2224
+
+#define mmNIC4_QM1_CP_MSG_BASE0_ADDR_LO_0 0xDE2228
+
+#define mmNIC4_QM1_CP_MSG_BASE0_ADDR_LO_1 0xDE222C
+
+#define mmNIC4_QM1_CP_MSG_BASE0_ADDR_LO_2 0xDE2230
+
+#define mmNIC4_QM1_CP_MSG_BASE0_ADDR_LO_3 0xDE2234
+
+#define mmNIC4_QM1_CP_MSG_BASE0_ADDR_LO_4 0xDE2238
+
+#define mmNIC4_QM1_CP_MSG_BASE0_ADDR_HI_0 0xDE223C
+
+#define mmNIC4_QM1_CP_MSG_BASE0_ADDR_HI_1 0xDE2240
+
+#define mmNIC4_QM1_CP_MSG_BASE0_ADDR_HI_2 0xDE2244
+
+#define mmNIC4_QM1_CP_MSG_BASE0_ADDR_HI_3 0xDE2248
+
+#define mmNIC4_QM1_CP_MSG_BASE0_ADDR_HI_4 0xDE224C
+
+#define mmNIC4_QM1_CP_MSG_BASE1_ADDR_LO_0 0xDE2250
+
+#define mmNIC4_QM1_CP_MSG_BASE1_ADDR_LO_1 0xDE2254
+
+#define mmNIC4_QM1_CP_MSG_BASE1_ADDR_LO_2 0xDE2258
+
+#define mmNIC4_QM1_CP_MSG_BASE1_ADDR_LO_3 0xDE225C
+
+#define mmNIC4_QM1_CP_MSG_BASE1_ADDR_LO_4 0xDE2260
+
+#define mmNIC4_QM1_CP_MSG_BASE1_ADDR_HI_0 0xDE2264
+
+#define mmNIC4_QM1_CP_MSG_BASE1_ADDR_HI_1 0xDE2268
+
+#define mmNIC4_QM1_CP_MSG_BASE1_ADDR_HI_2 0xDE226C
+
+#define mmNIC4_QM1_CP_MSG_BASE1_ADDR_HI_3 0xDE2270
+
+#define mmNIC4_QM1_CP_MSG_BASE1_ADDR_HI_4 0xDE2274
+
+#define mmNIC4_QM1_CP_MSG_BASE2_ADDR_LO_0 0xDE2278
+
+#define mmNIC4_QM1_CP_MSG_BASE2_ADDR_LO_1 0xDE227C
+
+#define mmNIC4_QM1_CP_MSG_BASE2_ADDR_LO_2 0xDE2280
+
+#define mmNIC4_QM1_CP_MSG_BASE2_ADDR_LO_3 0xDE2284
+
+#define mmNIC4_QM1_CP_MSG_BASE2_ADDR_LO_4 0xDE2288
+
+#define mmNIC4_QM1_CP_MSG_BASE2_ADDR_HI_0 0xDE228C
+
+#define mmNIC4_QM1_CP_MSG_BASE2_ADDR_HI_1 0xDE2290
+
+#define mmNIC4_QM1_CP_MSG_BASE2_ADDR_HI_2 0xDE2294
+
+#define mmNIC4_QM1_CP_MSG_BASE2_ADDR_HI_3 0xDE2298
+
+#define mmNIC4_QM1_CP_MSG_BASE2_ADDR_HI_4 0xDE229C
+
+#define mmNIC4_QM1_CP_MSG_BASE3_ADDR_LO_0 0xDE22A0
+
+#define mmNIC4_QM1_CP_MSG_BASE3_ADDR_LO_1 0xDE22A4
+
+#define mmNIC4_QM1_CP_MSG_BASE3_ADDR_LO_2 0xDE22A8
+
+#define mmNIC4_QM1_CP_MSG_BASE3_ADDR_LO_3 0xDE22AC
+
+#define mmNIC4_QM1_CP_MSG_BASE3_ADDR_LO_4 0xDE22B0
+
+#define mmNIC4_QM1_CP_MSG_BASE3_ADDR_HI_0 0xDE22B4
+
+#define mmNIC4_QM1_CP_MSG_BASE3_ADDR_HI_1 0xDE22B8
+
+#define mmNIC4_QM1_CP_MSG_BASE3_ADDR_HI_2 0xDE22BC
+
+#define mmNIC4_QM1_CP_MSG_BASE3_ADDR_HI_3 0xDE22C0
+
+#define mmNIC4_QM1_CP_MSG_BASE3_ADDR_HI_4 0xDE22C4
+
+#define mmNIC4_QM1_CP_LDMA_TSIZE_OFFSET_0 0xDE22C8
+
+#define mmNIC4_QM1_CP_LDMA_TSIZE_OFFSET_1 0xDE22CC
+
+#define mmNIC4_QM1_CP_LDMA_TSIZE_OFFSET_2 0xDE22D0
+
+#define mmNIC4_QM1_CP_LDMA_TSIZE_OFFSET_3 0xDE22D4
+
+#define mmNIC4_QM1_CP_LDMA_TSIZE_OFFSET_4 0xDE22D8
+
+#define mmNIC4_QM1_CP_LDMA_SRC_BASE_LO_OFFSET_0 0xDE22E0
+
+#define mmNIC4_QM1_CP_LDMA_SRC_BASE_LO_OFFSET_1 0xDE22E4
+
+#define mmNIC4_QM1_CP_LDMA_SRC_BASE_LO_OFFSET_2 0xDE22E8
+
+#define mmNIC4_QM1_CP_LDMA_SRC_BASE_LO_OFFSET_3 0xDE22EC
+
+#define mmNIC4_QM1_CP_LDMA_SRC_BASE_LO_OFFSET_4 0xDE22F0
+
+#define mmNIC4_QM1_CP_LDMA_DST_BASE_LO_OFFSET_0 0xDE22F4
+
+#define mmNIC4_QM1_CP_LDMA_DST_BASE_LO_OFFSET_1 0xDE22F8
+
+#define mmNIC4_QM1_CP_LDMA_DST_BASE_LO_OFFSET_2 0xDE22FC
+
+#define mmNIC4_QM1_CP_LDMA_DST_BASE_LO_OFFSET_3 0xDE2300
+
+#define mmNIC4_QM1_CP_LDMA_DST_BASE_LO_OFFSET_4 0xDE2304
+
+#define mmNIC4_QM1_CP_FENCE0_RDATA_0 0xDE2308
+
+#define mmNIC4_QM1_CP_FENCE0_RDATA_1 0xDE230C
+
+#define mmNIC4_QM1_CP_FENCE0_RDATA_2 0xDE2310
+
+#define mmNIC4_QM1_CP_FENCE0_RDATA_3 0xDE2314
+
+#define mmNIC4_QM1_CP_FENCE0_RDATA_4 0xDE2318
+
+#define mmNIC4_QM1_CP_FENCE1_RDATA_0 0xDE231C
+
+#define mmNIC4_QM1_CP_FENCE1_RDATA_1 0xDE2320
+
+#define mmNIC4_QM1_CP_FENCE1_RDATA_2 0xDE2324
+
+#define mmNIC4_QM1_CP_FENCE1_RDATA_3 0xDE2328
+
+#define mmNIC4_QM1_CP_FENCE1_RDATA_4 0xDE232C
+
+#define mmNIC4_QM1_CP_FENCE2_RDATA_0 0xDE2330
+
+#define mmNIC4_QM1_CP_FENCE2_RDATA_1 0xDE2334
+
+#define mmNIC4_QM1_CP_FENCE2_RDATA_2 0xDE2338
+
+#define mmNIC4_QM1_CP_FENCE2_RDATA_3 0xDE233C
+
+#define mmNIC4_QM1_CP_FENCE2_RDATA_4 0xDE2340
+
+#define mmNIC4_QM1_CP_FENCE3_RDATA_0 0xDE2344
+
+#define mmNIC4_QM1_CP_FENCE3_RDATA_1 0xDE2348
+
+#define mmNIC4_QM1_CP_FENCE3_RDATA_2 0xDE234C
+
+#define mmNIC4_QM1_CP_FENCE3_RDATA_3 0xDE2350
+
+#define mmNIC4_QM1_CP_FENCE3_RDATA_4 0xDE2354
+
+#define mmNIC4_QM1_CP_FENCE0_CNT_0 0xDE2358
+
+#define mmNIC4_QM1_CP_FENCE0_CNT_1 0xDE235C
+
+#define mmNIC4_QM1_CP_FENCE0_CNT_2 0xDE2360
+
+#define mmNIC4_QM1_CP_FENCE0_CNT_3 0xDE2364
+
+#define mmNIC4_QM1_CP_FENCE0_CNT_4 0xDE2368
+
+#define mmNIC4_QM1_CP_FENCE1_CNT_0 0xDE236C
+
+#define mmNIC4_QM1_CP_FENCE1_CNT_1 0xDE2370
+
+#define mmNIC4_QM1_CP_FENCE1_CNT_2 0xDE2374
+
+#define mmNIC4_QM1_CP_FENCE1_CNT_3 0xDE2378
+
+#define mmNIC4_QM1_CP_FENCE1_CNT_4 0xDE237C
+
+#define mmNIC4_QM1_CP_FENCE2_CNT_0 0xDE2380
+
+#define mmNIC4_QM1_CP_FENCE2_CNT_1 0xDE2384
+
+#define mmNIC4_QM1_CP_FENCE2_CNT_2 0xDE2388
+
+#define mmNIC4_QM1_CP_FENCE2_CNT_3 0xDE238C
+
+#define mmNIC4_QM1_CP_FENCE2_CNT_4 0xDE2390
+
+#define mmNIC4_QM1_CP_FENCE3_CNT_0 0xDE2394
+
+#define mmNIC4_QM1_CP_FENCE3_CNT_1 0xDE2398
+
+#define mmNIC4_QM1_CP_FENCE3_CNT_2 0xDE239C
+
+#define mmNIC4_QM1_CP_FENCE3_CNT_3 0xDE23A0
+
+#define mmNIC4_QM1_CP_FENCE3_CNT_4 0xDE23A4
+
+#define mmNIC4_QM1_CP_STS_0 0xDE23A8
+
+#define mmNIC4_QM1_CP_STS_1 0xDE23AC
+
+#define mmNIC4_QM1_CP_STS_2 0xDE23B0
+
+#define mmNIC4_QM1_CP_STS_3 0xDE23B4
+
+#define mmNIC4_QM1_CP_STS_4 0xDE23B8
+
+#define mmNIC4_QM1_CP_CURRENT_INST_LO_0 0xDE23BC
+
+#define mmNIC4_QM1_CP_CURRENT_INST_LO_1 0xDE23C0
+
+#define mmNIC4_QM1_CP_CURRENT_INST_LO_2 0xDE23C4
+
+#define mmNIC4_QM1_CP_CURRENT_INST_LO_3 0xDE23C8
+
+#define mmNIC4_QM1_CP_CURRENT_INST_LO_4 0xDE23CC
+
+#define mmNIC4_QM1_CP_CURRENT_INST_HI_0 0xDE23D0
+
+#define mmNIC4_QM1_CP_CURRENT_INST_HI_1 0xDE23D4
+
+#define mmNIC4_QM1_CP_CURRENT_INST_HI_2 0xDE23D8
+
+#define mmNIC4_QM1_CP_CURRENT_INST_HI_3 0xDE23DC
+
+#define mmNIC4_QM1_CP_CURRENT_INST_HI_4 0xDE23E0
+
+#define mmNIC4_QM1_CP_BARRIER_CFG_0 0xDE23F4
+
+#define mmNIC4_QM1_CP_BARRIER_CFG_1 0xDE23F8
+
+#define mmNIC4_QM1_CP_BARRIER_CFG_2 0xDE23FC
+
+#define mmNIC4_QM1_CP_BARRIER_CFG_3 0xDE2400
+
+#define mmNIC4_QM1_CP_BARRIER_CFG_4 0xDE2404
+
+#define mmNIC4_QM1_CP_DBG_0_0 0xDE2408
+
+#define mmNIC4_QM1_CP_DBG_0_1 0xDE240C
+
+#define mmNIC4_QM1_CP_DBG_0_2 0xDE2410
+
+#define mmNIC4_QM1_CP_DBG_0_3 0xDE2414
+
+#define mmNIC4_QM1_CP_DBG_0_4 0xDE2418
+
+#define mmNIC4_QM1_CP_ARUSER_31_11_0 0xDE241C
+
+#define mmNIC4_QM1_CP_ARUSER_31_11_1 0xDE2420
+
+#define mmNIC4_QM1_CP_ARUSER_31_11_2 0xDE2424
+
+#define mmNIC4_QM1_CP_ARUSER_31_11_3 0xDE2428
+
+#define mmNIC4_QM1_CP_ARUSER_31_11_4 0xDE242C
+
+#define mmNIC4_QM1_CP_AWUSER_31_11_0 0xDE2430
+
+#define mmNIC4_QM1_CP_AWUSER_31_11_1 0xDE2434
+
+#define mmNIC4_QM1_CP_AWUSER_31_11_2 0xDE2438
+
+#define mmNIC4_QM1_CP_AWUSER_31_11_3 0xDE243C
+
+#define mmNIC4_QM1_CP_AWUSER_31_11_4 0xDE2440
+
+#define mmNIC4_QM1_ARB_CFG_0 0xDE2A00
+
+#define mmNIC4_QM1_ARB_CHOISE_Q_PUSH 0xDE2A04
+
+#define mmNIC4_QM1_ARB_WRR_WEIGHT_0 0xDE2A08
+
+#define mmNIC4_QM1_ARB_WRR_WEIGHT_1 0xDE2A0C
+
+#define mmNIC4_QM1_ARB_WRR_WEIGHT_2 0xDE2A10
+
+#define mmNIC4_QM1_ARB_WRR_WEIGHT_3 0xDE2A14
+
+#define mmNIC4_QM1_ARB_CFG_1 0xDE2A18
+
+#define mmNIC4_QM1_ARB_MST_AVAIL_CRED_0 0xDE2A20
+
+#define mmNIC4_QM1_ARB_MST_AVAIL_CRED_1 0xDE2A24
+
+#define mmNIC4_QM1_ARB_MST_AVAIL_CRED_2 0xDE2A28
+
+#define mmNIC4_QM1_ARB_MST_AVAIL_CRED_3 0xDE2A2C
+
+#define mmNIC4_QM1_ARB_MST_AVAIL_CRED_4 0xDE2A30
+
+#define mmNIC4_QM1_ARB_MST_AVAIL_CRED_5 0xDE2A34
+
+#define mmNIC4_QM1_ARB_MST_AVAIL_CRED_6 0xDE2A38
+
+#define mmNIC4_QM1_ARB_MST_AVAIL_CRED_7 0xDE2A3C
+
+#define mmNIC4_QM1_ARB_MST_AVAIL_CRED_8 0xDE2A40
+
+#define mmNIC4_QM1_ARB_MST_AVAIL_CRED_9 0xDE2A44
+
+#define mmNIC4_QM1_ARB_MST_AVAIL_CRED_10 0xDE2A48
+
+#define mmNIC4_QM1_ARB_MST_AVAIL_CRED_11 0xDE2A4C
+
+#define mmNIC4_QM1_ARB_MST_AVAIL_CRED_12 0xDE2A50
+
+#define mmNIC4_QM1_ARB_MST_AVAIL_CRED_13 0xDE2A54
+
+#define mmNIC4_QM1_ARB_MST_AVAIL_CRED_14 0xDE2A58
+
+#define mmNIC4_QM1_ARB_MST_AVAIL_CRED_15 0xDE2A5C
+
+#define mmNIC4_QM1_ARB_MST_AVAIL_CRED_16 0xDE2A60
+
+#define mmNIC4_QM1_ARB_MST_AVAIL_CRED_17 0xDE2A64
+
+#define mmNIC4_QM1_ARB_MST_AVAIL_CRED_18 0xDE2A68
+
+#define mmNIC4_QM1_ARB_MST_AVAIL_CRED_19 0xDE2A6C
+
+#define mmNIC4_QM1_ARB_MST_AVAIL_CRED_20 0xDE2A70
+
+#define mmNIC4_QM1_ARB_MST_AVAIL_CRED_21 0xDE2A74
+
+#define mmNIC4_QM1_ARB_MST_AVAIL_CRED_22 0xDE2A78
+
+#define mmNIC4_QM1_ARB_MST_AVAIL_CRED_23 0xDE2A7C
+
+#define mmNIC4_QM1_ARB_MST_AVAIL_CRED_24 0xDE2A80
+
+#define mmNIC4_QM1_ARB_MST_AVAIL_CRED_25 0xDE2A84
+
+#define mmNIC4_QM1_ARB_MST_AVAIL_CRED_26 0xDE2A88
+
+#define mmNIC4_QM1_ARB_MST_AVAIL_CRED_27 0xDE2A8C
+
+#define mmNIC4_QM1_ARB_MST_AVAIL_CRED_28 0xDE2A90
+
+#define mmNIC4_QM1_ARB_MST_AVAIL_CRED_29 0xDE2A94
+
+#define mmNIC4_QM1_ARB_MST_AVAIL_CRED_30 0xDE2A98
+
+#define mmNIC4_QM1_ARB_MST_AVAIL_CRED_31 0xDE2A9C
+
+#define mmNIC4_QM1_ARB_MST_CRED_INC 0xDE2AA0
+
+#define mmNIC4_QM1_ARB_MST_CHOISE_PUSH_OFST_0 0xDE2AA4
+
+#define mmNIC4_QM1_ARB_MST_CHOISE_PUSH_OFST_1 0xDE2AA8
+
+#define mmNIC4_QM1_ARB_MST_CHOISE_PUSH_OFST_2 0xDE2AAC
+
+#define mmNIC4_QM1_ARB_MST_CHOISE_PUSH_OFST_3 0xDE2AB0
+
+#define mmNIC4_QM1_ARB_MST_CHOISE_PUSH_OFST_4 0xDE2AB4
+
+#define mmNIC4_QM1_ARB_MST_CHOISE_PUSH_OFST_5 0xDE2AB8
+
+#define mmNIC4_QM1_ARB_MST_CHOISE_PUSH_OFST_6 0xDE2ABC
+
+#define mmNIC4_QM1_ARB_MST_CHOISE_PUSH_OFST_7 0xDE2AC0
+
+#define mmNIC4_QM1_ARB_MST_CHOISE_PUSH_OFST_8 0xDE2AC4
+
+#define mmNIC4_QM1_ARB_MST_CHOISE_PUSH_OFST_9 0xDE2AC8
+
+#define mmNIC4_QM1_ARB_MST_CHOISE_PUSH_OFST_10 0xDE2ACC
+
+#define mmNIC4_QM1_ARB_MST_CHOISE_PUSH_OFST_11 0xDE2AD0
+
+#define mmNIC4_QM1_ARB_MST_CHOISE_PUSH_OFST_12 0xDE2AD4
+
+#define mmNIC4_QM1_ARB_MST_CHOISE_PUSH_OFST_13 0xDE2AD8
+
+#define mmNIC4_QM1_ARB_MST_CHOISE_PUSH_OFST_14 0xDE2ADC
+
+#define mmNIC4_QM1_ARB_MST_CHOISE_PUSH_OFST_15 0xDE2AE0
+
+#define mmNIC4_QM1_ARB_MST_CHOISE_PUSH_OFST_16 0xDE2AE4
+
+#define mmNIC4_QM1_ARB_MST_CHOISE_PUSH_OFST_17 0xDE2AE8
+
+#define mmNIC4_QM1_ARB_MST_CHOISE_PUSH_OFST_18 0xDE2AEC
+
+#define mmNIC4_QM1_ARB_MST_CHOISE_PUSH_OFST_19 0xDE2AF0
+
+#define mmNIC4_QM1_ARB_MST_CHOISE_PUSH_OFST_20 0xDE2AF4
+
+#define mmNIC4_QM1_ARB_MST_CHOISE_PUSH_OFST_21 0xDE2AF8
+
+#define mmNIC4_QM1_ARB_MST_CHOISE_PUSH_OFST_22 0xDE2AFC
+
+#define mmNIC4_QM1_ARB_MST_CHOISE_PUSH_OFST_23 0xDE2B00
+
+#define mmNIC4_QM1_ARB_MST_CHOISE_PUSH_OFST_24 0xDE2B04
+
+#define mmNIC4_QM1_ARB_MST_CHOISE_PUSH_OFST_25 0xDE2B08
+
+#define mmNIC4_QM1_ARB_MST_CHOISE_PUSH_OFST_26 0xDE2B0C
+
+#define mmNIC4_QM1_ARB_MST_CHOISE_PUSH_OFST_27 0xDE2B10
+
+#define mmNIC4_QM1_ARB_MST_CHOISE_PUSH_OFST_28 0xDE2B14
+
+#define mmNIC4_QM1_ARB_MST_CHOISE_PUSH_OFST_29 0xDE2B18
+
+#define mmNIC4_QM1_ARB_MST_CHOISE_PUSH_OFST_30 0xDE2B1C
+
+#define mmNIC4_QM1_ARB_MST_CHOISE_PUSH_OFST_31 0xDE2B20
+
+#define mmNIC4_QM1_ARB_SLV_MASTER_INC_CRED_OFST 0xDE2B28
+
+#define mmNIC4_QM1_ARB_MST_SLAVE_EN 0xDE2B2C
+
+#define mmNIC4_QM1_ARB_MST_QUIET_PER 0xDE2B34
+
+#define mmNIC4_QM1_ARB_SLV_CHOISE_WDT 0xDE2B38
+
+#define mmNIC4_QM1_ARB_SLV_ID 0xDE2B3C
+
+#define mmNIC4_QM1_ARB_MSG_MAX_INFLIGHT 0xDE2B44
+
+#define mmNIC4_QM1_ARB_MSG_AWUSER_31_11 0xDE2B48
+
+#define mmNIC4_QM1_ARB_MSG_AWUSER_SEC_PROP 0xDE2B4C
+
+#define mmNIC4_QM1_ARB_MSG_AWUSER_NON_SEC_PROP 0xDE2B50
+
+#define mmNIC4_QM1_ARB_BASE_LO 0xDE2B54
+
+#define mmNIC4_QM1_ARB_BASE_HI 0xDE2B58
+
+#define mmNIC4_QM1_ARB_STATE_STS 0xDE2B80
+
+#define mmNIC4_QM1_ARB_CHOISE_FULLNESS_STS 0xDE2B84
+
+#define mmNIC4_QM1_ARB_MSG_STS 0xDE2B88
+
+#define mmNIC4_QM1_ARB_SLV_CHOISE_Q_HEAD 0xDE2B8C
+
+#define mmNIC4_QM1_ARB_ERR_CAUSE 0xDE2B9C
+
+#define mmNIC4_QM1_ARB_ERR_MSG_EN 0xDE2BA0
+
+#define mmNIC4_QM1_ARB_ERR_STS_DRP 0xDE2BA8
+
+#define mmNIC4_QM1_ARB_MST_CRED_STS_0 0xDE2BB0
+
+#define mmNIC4_QM1_ARB_MST_CRED_STS_1 0xDE2BB4
+
+#define mmNIC4_QM1_ARB_MST_CRED_STS_2 0xDE2BB8
+
+#define mmNIC4_QM1_ARB_MST_CRED_STS_3 0xDE2BBC
+
+#define mmNIC4_QM1_ARB_MST_CRED_STS_4 0xDE2BC0
+
+#define mmNIC4_QM1_ARB_MST_CRED_STS_5 0xDE2BC4
+
+#define mmNIC4_QM1_ARB_MST_CRED_STS_6 0xDE2BC8
+
+#define mmNIC4_QM1_ARB_MST_CRED_STS_7 0xDE2BCC
+
+#define mmNIC4_QM1_ARB_MST_CRED_STS_8 0xDE2BD0
+
+#define mmNIC4_QM1_ARB_MST_CRED_STS_9 0xDE2BD4
+
+#define mmNIC4_QM1_ARB_MST_CRED_STS_10 0xDE2BD8
+
+#define mmNIC4_QM1_ARB_MST_CRED_STS_11 0xDE2BDC
+
+#define mmNIC4_QM1_ARB_MST_CRED_STS_12 0xDE2BE0
+
+#define mmNIC4_QM1_ARB_MST_CRED_STS_13 0xDE2BE4
+
+#define mmNIC4_QM1_ARB_MST_CRED_STS_14 0xDE2BE8
+
+#define mmNIC4_QM1_ARB_MST_CRED_STS_15 0xDE2BEC
+
+#define mmNIC4_QM1_ARB_MST_CRED_STS_16 0xDE2BF0
+
+#define mmNIC4_QM1_ARB_MST_CRED_STS_17 0xDE2BF4
+
+#define mmNIC4_QM1_ARB_MST_CRED_STS_18 0xDE2BF8
+
+#define mmNIC4_QM1_ARB_MST_CRED_STS_19 0xDE2BFC
+
+#define mmNIC4_QM1_ARB_MST_CRED_STS_20 0xDE2C00
+
+#define mmNIC4_QM1_ARB_MST_CRED_STS_21 0xDE2C04
+
+#define mmNIC4_QM1_ARB_MST_CRED_STS_22 0xDE2C08
+
+#define mmNIC4_QM1_ARB_MST_CRED_STS_23 0xDE2C0C
+
+#define mmNIC4_QM1_ARB_MST_CRED_STS_24 0xDE2C10
+
+#define mmNIC4_QM1_ARB_MST_CRED_STS_25 0xDE2C14
+
+#define mmNIC4_QM1_ARB_MST_CRED_STS_26 0xDE2C18
+
+#define mmNIC4_QM1_ARB_MST_CRED_STS_27 0xDE2C1C
+
+#define mmNIC4_QM1_ARB_MST_CRED_STS_28 0xDE2C20
+
+#define mmNIC4_QM1_ARB_MST_CRED_STS_29 0xDE2C24
+
+#define mmNIC4_QM1_ARB_MST_CRED_STS_30 0xDE2C28
+
+#define mmNIC4_QM1_ARB_MST_CRED_STS_31 0xDE2C2C
+
+#define mmNIC4_QM1_CGM_CFG 0xDE2C70
+
+#define mmNIC4_QM1_CGM_STS 0xDE2C74
+
+#define mmNIC4_QM1_CGM_CFG1 0xDE2C78
+
+#define mmNIC4_QM1_LOCAL_RANGE_BASE 0xDE2C80
+
+#define mmNIC4_QM1_LOCAL_RANGE_SIZE 0xDE2C84
+
+#define mmNIC4_QM1_CSMR_STRICT_PRIO_CFG 0xDE2C90
+
+#define mmNIC4_QM1_HBW_RD_RATE_LIM_CFG_1 0xDE2C94
+
+#define mmNIC4_QM1_LBW_WR_RATE_LIM_CFG_0 0xDE2C98
+
+#define mmNIC4_QM1_LBW_WR_RATE_LIM_CFG_1 0xDE2C9C
+
+#define mmNIC4_QM1_HBW_RD_RATE_LIM_CFG_0 0xDE2CA0
+
+#define mmNIC4_QM1_GLBL_AXCACHE 0xDE2CA4
+
+#define mmNIC4_QM1_IND_GW_APB_CFG 0xDE2CB0
+
+#define mmNIC4_QM1_IND_GW_APB_WDATA 0xDE2CB4
+
+#define mmNIC4_QM1_IND_GW_APB_RDATA 0xDE2CB8
+
+#define mmNIC4_QM1_IND_GW_APB_STATUS 0xDE2CBC
+
+#define mmNIC4_QM1_GLBL_ERR_ADDR_LO 0xDE2CD0
+
+#define mmNIC4_QM1_GLBL_ERR_ADDR_HI 0xDE2CD4
+
+#define mmNIC4_QM1_GLBL_ERR_WDATA 0xDE2CD8
+
+#define mmNIC4_QM1_GLBL_MEM_INIT_BUSY 0xDE2D00
+
+#endif /* ASIC_REG_NIC4_QM1_REGS_H_ */
diff --git a/drivers/accel/habanalabs/include/gaudi/asic_reg/nif_rtr_ctrl_0_regs.h b/drivers/accel/habanalabs/include/gaudi/asic_reg/nif_rtr_ctrl_0_regs.h
new file mode 100644
index 0000000000..2efa2a54de
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi/asic_reg/nif_rtr_ctrl_0_regs.h
@@ -0,0 +1,896 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2016-2018 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ ** DO NOT EDIT BELOW **
+ ************************************/
+
+#ifndef ASIC_REG_NIF_RTR_CTRL_0_REGS_H_
+#define ASIC_REG_NIF_RTR_CTRL_0_REGS_H_
+
+/*
+ *****************************************
+ * NIF_RTR_CTRL_0 (Prototype: RTR_CTRL)
+ *****************************************
+ */
+
+#define mmNIF_RTR_CTRL_0_PERM_SEL 0x386108
+
+#define mmNIF_RTR_CTRL_0_HBM_POLY_H3_0 0x386114
+
+#define mmNIF_RTR_CTRL_0_HBM_POLY_H3_1 0x386118
+
+#define mmNIF_RTR_CTRL_0_HBM_POLY_H3_2 0x38611C
+
+#define mmNIF_RTR_CTRL_0_HBM_POLY_H3_3 0x386120
+
+#define mmNIF_RTR_CTRL_0_HBM_POLY_H3_4 0x386124
+
+#define mmNIF_RTR_CTRL_0_HBM_POLY_H3_5 0x386128
+
+#define mmNIF_RTR_CTRL_0_HBM_POLY_H3_6 0x38612C
+
+#define mmNIF_RTR_CTRL_0_HBM_POLY_H3_7 0x386130
+
+#define mmNIF_RTR_CTRL_0_HBM_POLY_H3_8 0x386134
+
+#define mmNIF_RTR_CTRL_0_HBM_POLY_H3_9 0x386138
+
+#define mmNIF_RTR_CTRL_0_HBM_POLY_H3_10 0x38613C
+
+#define mmNIF_RTR_CTRL_0_HBM_POLY_H3_11 0x386140
+
+#define mmNIF_RTR_CTRL_0_HBM_POLY_H3_12 0x386144
+
+#define mmNIF_RTR_CTRL_0_HBM_POLY_H3_13 0x386148
+
+#define mmNIF_RTR_CTRL_0_HBM_POLY_H3_14 0x38614C
+
+#define mmNIF_RTR_CTRL_0_HBM_POLY_H3_15 0x386150
+
+#define mmNIF_RTR_CTRL_0_HBM_POLY_H3_16 0x386154
+
+#define mmNIF_RTR_CTRL_0_HBM_POLY_H3_17 0x386158
+
+#define mmNIF_RTR_CTRL_0_HBM_POLY_H3_18 0x38615C
+
+#define mmNIF_RTR_CTRL_0_HBM_POLY_H3_19 0x386160
+
+#define mmNIF_RTR_CTRL_0_HBM_POLY_H3_20 0x386164
+
+#define mmNIF_RTR_CTRL_0_HBM_POLY_H3_21 0x386168
+
+#define mmNIF_RTR_CTRL_0_HBM_POLY_H3_22 0x38616C
+
+#define mmNIF_RTR_CTRL_0_HBM_POLY_H3_23 0x386170
+
+#define mmNIF_RTR_CTRL_0_HBM_POLY_H3_24 0x386174
+
+#define mmNIF_RTR_CTRL_0_HBM_POLY_H3_25 0x386178
+
+#define mmNIF_RTR_CTRL_0_HBM_POLY_H3_26 0x38617C
+
+#define mmNIF_RTR_CTRL_0_HBM_POLY_H3_27 0x386180
+
+#define mmNIF_RTR_CTRL_0_SRAM_POLY_H3_0 0x386184
+
+#define mmNIF_RTR_CTRL_0_SRAM_POLY_H3_1 0x386188
+
+#define mmNIF_RTR_CTRL_0_SRAM_POLY_H3_2 0x38618C
+
+#define mmNIF_RTR_CTRL_0_SRAM_POLY_H3_3 0x386190
+
+#define mmNIF_RTR_CTRL_0_SRAM_POLY_H3_4 0x386194
+
+#define mmNIF_RTR_CTRL_0_SRAM_POLY_H3_5 0x386198
+
+#define mmNIF_RTR_CTRL_0_SRAM_POLY_H3_6 0x38619C
+
+#define mmNIF_RTR_CTRL_0_SRAM_POLY_H3_7 0x3861A0
+
+#define mmNIF_RTR_CTRL_0_SRAM_POLY_H3_8 0x3861A4
+
+#define mmNIF_RTR_CTRL_0_SRAM_POLY_H3_9 0x3861A8
+
+#define mmNIF_RTR_CTRL_0_SRAM_POLY_H3_10 0x3861AC
+
+#define mmNIF_RTR_CTRL_0_SRAM_POLY_H3_11 0x3861B0
+
+#define mmNIF_RTR_CTRL_0_SRAM_POLY_H3_12 0x3861B4
+
+#define mmNIF_RTR_CTRL_0_SRAM_POLY_H3_13 0x3861B8
+
+#define mmNIF_RTR_CTRL_0_SRAM_POLY_H3_14 0x3861BC
+
+#define mmNIF_RTR_CTRL_0_SCRAM_SRAM_EN 0x38626C
+
+#define mmNIF_RTR_CTRL_0_RL_HBM_EN 0x386274
+
+#define mmNIF_RTR_CTRL_0_RL_HBM_SAT 0x386278
+
+#define mmNIF_RTR_CTRL_0_RL_HBM_RST 0x38627C
+
+#define mmNIF_RTR_CTRL_0_RL_HBM_TIMEOUT 0x386280
+
+#define mmNIF_RTR_CTRL_0_SCRAM_HBM_EN 0x386284
+
+#define mmNIF_RTR_CTRL_0_RL_PCI_EN 0x386288
+
+#define mmNIF_RTR_CTRL_0_RL_PCI_SAT 0x38628C
+
+#define mmNIF_RTR_CTRL_0_RL_PCI_RST 0x386290
+
+#define mmNIF_RTR_CTRL_0_RL_PCI_TIMEOUT 0x386294
+
+#define mmNIF_RTR_CTRL_0_RL_SRAM_EN 0x38629C
+
+#define mmNIF_RTR_CTRL_0_RL_SRAM_SAT 0x3862A0
+
+#define mmNIF_RTR_CTRL_0_RL_SRAM_RST 0x3862A4
+
+#define mmNIF_RTR_CTRL_0_RL_SRAM_TIMEOUT 0x3862AC
+
+#define mmNIF_RTR_CTRL_0_RL_SRAM_RED 0x3862B4
+
+#define mmNIF_RTR_CTRL_0_E2E_HBM_EN 0x3862EC
+
+#define mmNIF_RTR_CTRL_0_E2E_PCI_EN 0x3862F0
+
+#define mmNIF_RTR_CTRL_0_E2E_HBM_WR_SIZE 0x3862F4
+
+#define mmNIF_RTR_CTRL_0_E2E_PCI_WR_SIZE 0x3862F8
+
+#define mmNIF_RTR_CTRL_0_E2E_AW_PCI_CTR_SET_EN 0x386404
+
+#define mmNIF_RTR_CTRL_0_E2E_AW_PCI_CTR_SET 0x386408
+
+#define mmNIF_RTR_CTRL_0_E2E_AW_PCI_CTR_WRAP 0x38640C
+
+#define mmNIF_RTR_CTRL_0_E2E_AW_PCI_CTR_CNT 0x386410
+
+#define mmNIF_RTR_CTRL_0_E2E_AW_HBM_CTR_SET_EN 0x386414
+
+#define mmNIF_RTR_CTRL_0_E2E_AW_HBM_CTR_SET 0x386418
+
+#define mmNIF_RTR_CTRL_0_E2E_HBM_RD_SIZE 0x38641C
+
+#define mmNIF_RTR_CTRL_0_E2E_PCI_RD_SIZE 0x386420
+
+#define mmNIF_RTR_CTRL_0_E2E_AR_PCI_CTR_SET_EN 0x386424
+
+#define mmNIF_RTR_CTRL_0_E2E_AR_PCI_CTR_SET 0x386428
+
+#define mmNIF_RTR_CTRL_0_E2E_AR_PCI_CTR_WRAP 0x38642C
+
+#define mmNIF_RTR_CTRL_0_E2E_AR_PCI_CTR_CNT 0x386430
+
+#define mmNIF_RTR_CTRL_0_E2E_AR_HBM_CTR_SET_EN 0x386434
+
+#define mmNIF_RTR_CTRL_0_E2E_AR_HBM_CTR_SET 0x386438
+
+#define mmNIF_RTR_CTRL_0_NL_HBM_SEL_0 0x386450
+
+#define mmNIF_RTR_CTRL_0_NL_HBM_SEL_1 0x386454
+
+#define mmNIF_RTR_CTRL_0_NON_LIN_EN 0x386480
+
+#define mmNIF_RTR_CTRL_0_NL_SRAM_BANK_0 0x386500
+
+#define mmNIF_RTR_CTRL_0_NL_SRAM_BANK_1 0x386504
+
+#define mmNIF_RTR_CTRL_0_NL_SRAM_BANK_2 0x386508
+
+#define mmNIF_RTR_CTRL_0_NL_SRAM_BANK_3 0x38650C
+
+#define mmNIF_RTR_CTRL_0_NL_SRAM_BANK_4 0x386510
+
+#define mmNIF_RTR_CTRL_0_NL_SRAM_OFFSET_0 0x386514
+
+#define mmNIF_RTR_CTRL_0_NL_SRAM_OFFSET_1 0x386520
+
+#define mmNIF_RTR_CTRL_0_NL_SRAM_OFFSET_2 0x386524
+
+#define mmNIF_RTR_CTRL_0_NL_SRAM_OFFSET_3 0x386528
+
+#define mmNIF_RTR_CTRL_0_NL_SRAM_OFFSET_4 0x38652C
+
+#define mmNIF_RTR_CTRL_0_NL_SRAM_OFFSET_5 0x386530
+
+#define mmNIF_RTR_CTRL_0_NL_SRAM_OFFSET_6 0x386534
+
+#define mmNIF_RTR_CTRL_0_NL_SRAM_OFFSET_7 0x386538
+
+#define mmNIF_RTR_CTRL_0_NL_SRAM_OFFSET_8 0x38653C
+
+#define mmNIF_RTR_CTRL_0_NL_SRAM_OFFSET_9 0x386540
+
+#define mmNIF_RTR_CTRL_0_NL_HBM_OFFSET_0 0x386550
+
+#define mmNIF_RTR_CTRL_0_NL_HBM_OFFSET_1 0x386554
+
+#define mmNIF_RTR_CTRL_0_NL_HBM_OFFSET_2 0x386558
+
+#define mmNIF_RTR_CTRL_0_NL_HBM_OFFSET_3 0x38655C
+
+#define mmNIF_RTR_CTRL_0_NL_HBM_OFFSET_4 0x386560
+
+#define mmNIF_RTR_CTRL_0_NL_HBM_OFFSET_5 0x386564
+
+#define mmNIF_RTR_CTRL_0_NL_HBM_OFFSET_6 0x386568
+
+#define mmNIF_RTR_CTRL_0_NL_HBM_OFFSET_7 0x38656C
+
+#define mmNIF_RTR_CTRL_0_NL_HBM_OFFSET_8 0x386570
+
+#define mmNIF_RTR_CTRL_0_NL_HBM_OFFSET_9 0x386574
+
+#define mmNIF_RTR_CTRL_0_NL_HBM_OFFSET_10 0x386578
+
+#define mmNIF_RTR_CTRL_0_NL_HBM_OFFSET_11 0x38657C
+
+#define mmNIF_RTR_CTRL_0_NL_HBM_OFFSET_12 0x386580
+
+#define mmNIF_RTR_CTRL_0_NL_HBM_OFFSET_13 0x386584
+
+#define mmNIF_RTR_CTRL_0_NL_HBM_OFFSET_14 0x386588
+
+#define mmNIF_RTR_CTRL_0_NL_HBM_OFFSET_15 0x38658C
+
+#define mmNIF_RTR_CTRL_0_NL_HBM_OFFSET_16 0x386590
+
+#define mmNIF_RTR_CTRL_0_NL_HBM_OFFSET_17 0x386594
+
+#define mmNIF_RTR_CTRL_0_NL_HBM_OFFSET_18 0x386598
+
+#define mmNIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AW_0 0x3865E4
+
+#define mmNIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AW_1 0x3865E8
+
+#define mmNIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AW_2 0x3865EC
+
+#define mmNIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AW_3 0x3865F0
+
+#define mmNIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AW_4 0x3865F4
+
+#define mmNIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AW_5 0x3865F8
+
+#define mmNIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AW_6 0x3865FC
+
+#define mmNIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AW_7 0x386600
+
+#define mmNIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AW_8 0x386604
+
+#define mmNIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AW_9 0x386608
+
+#define mmNIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AW_10 0x38660C
+
+#define mmNIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AW_11 0x386610
+
+#define mmNIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AW_12 0x386614
+
+#define mmNIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AW_13 0x386618
+
+#define mmNIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AW_14 0x38661C
+
+#define mmNIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AW_15 0x386620
+
+#define mmNIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AW_0 0x386624
+
+#define mmNIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AW_1 0x386628
+
+#define mmNIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AW_2 0x38662C
+
+#define mmNIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AW_3 0x386630
+
+#define mmNIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AW_4 0x386634
+
+#define mmNIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AW_5 0x386638
+
+#define mmNIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AW_6 0x38663C
+
+#define mmNIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AW_7 0x386640
+
+#define mmNIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AW_8 0x386644
+
+#define mmNIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AW_9 0x386648
+
+#define mmNIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AW_10 0x38664C
+
+#define mmNIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AW_11 0x386650
+
+#define mmNIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AW_12 0x386654
+
+#define mmNIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AW_13 0x386658
+
+#define mmNIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AW_14 0x38665C
+
+#define mmNIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AW_15 0x386660
+
+#define mmNIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AW_0 0x386664
+
+#define mmNIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AW_1 0x386668
+
+#define mmNIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AW_2 0x38666C
+
+#define mmNIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AW_3 0x386670
+
+#define mmNIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AW_4 0x386674
+
+#define mmNIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AW_5 0x386678
+
+#define mmNIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AW_6 0x38667C
+
+#define mmNIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AW_7 0x386680
+
+#define mmNIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AW_8 0x386684
+
+#define mmNIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AW_9 0x386688
+
+#define mmNIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AW_10 0x38668C
+
+#define mmNIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AW_11 0x386690
+
+#define mmNIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AW_12 0x386694
+
+#define mmNIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AW_13 0x386698
+
+#define mmNIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AW_14 0x38669C
+
+#define mmNIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AW_15 0x3866A0
+
+#define mmNIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AW_0 0x3866A4
+
+#define mmNIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AW_1 0x3866A8
+
+#define mmNIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AW_2 0x3866AC
+
+#define mmNIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AW_3 0x3866B0
+
+#define mmNIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AW_4 0x3866B4
+
+#define mmNIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AW_5 0x3866B8
+
+#define mmNIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AW_6 0x3866BC
+
+#define mmNIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AW_7 0x3866C0
+
+#define mmNIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AW_8 0x3866C4
+
+#define mmNIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AW_9 0x3866C8
+
+#define mmNIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AW_10 0x3866CC
+
+#define mmNIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AW_11 0x3866D0
+
+#define mmNIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AW_12 0x3866D4
+
+#define mmNIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AW_13 0x3866D8
+
+#define mmNIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AW_14 0x3866DC
+
+#define mmNIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AW_15 0x3866E0
+
+#define mmNIF_RTR_CTRL_0_RANGE_PRIV_BASE_LOW_AW_0 0x3866E4
+
+#define mmNIF_RTR_CTRL_0_RANGE_PRIV_BASE_LOW_AW_1 0x3866E8
+
+#define mmNIF_RTR_CTRL_0_RANGE_PRIV_BASE_LOW_AW_2 0x3866EC
+
+#define mmNIF_RTR_CTRL_0_RANGE_PRIV_BASE_LOW_AW_3 0x3866F0
+
+#define mmNIF_RTR_CTRL_0_RANGE_PRIV_BASE_LOW_AW_4 0x3866F4
+
+#define mmNIF_RTR_CTRL_0_RANGE_PRIV_BASE_LOW_AW_5 0x3866F8
+
+#define mmNIF_RTR_CTRL_0_RANGE_PRIV_BASE_LOW_AW_6 0x3866FC
+
+#define mmNIF_RTR_CTRL_0_RANGE_PRIV_BASE_LOW_AW_7 0x386700
+
+#define mmNIF_RTR_CTRL_0_RANGE_PRIV_BASE_LOW_AW_8 0x386704
+
+#define mmNIF_RTR_CTRL_0_RANGE_PRIV_BASE_LOW_AW_9 0x386708
+
+#define mmNIF_RTR_CTRL_0_RANGE_PRIV_BASE_LOW_AW_10 0x38670C
+
+#define mmNIF_RTR_CTRL_0_RANGE_PRIV_BASE_LOW_AW_11 0x386710
+
+#define mmNIF_RTR_CTRL_0_RANGE_PRIV_BASE_LOW_AW_12 0x386714
+
+#define mmNIF_RTR_CTRL_0_RANGE_PRIV_BASE_LOW_AW_13 0x386718
+
+#define mmNIF_RTR_CTRL_0_RANGE_PRIV_BASE_LOW_AW_14 0x38671C
+
+#define mmNIF_RTR_CTRL_0_RANGE_PRIV_BASE_LOW_AW_15 0x386720
+
+#define mmNIF_RTR_CTRL_0_RANGE_PRIV_BASE_HIGH_AW_0 0x386724
+
+#define mmNIF_RTR_CTRL_0_RANGE_PRIV_BASE_HIGH_AW_1 0x386728
+
+#define mmNIF_RTR_CTRL_0_RANGE_PRIV_BASE_HIGH_AW_2 0x38672C
+
+#define mmNIF_RTR_CTRL_0_RANGE_PRIV_BASE_HIGH_AW_3 0x386730
+
+#define mmNIF_RTR_CTRL_0_RANGE_PRIV_BASE_HIGH_AW_4 0x386734
+
+#define mmNIF_RTR_CTRL_0_RANGE_PRIV_BASE_HIGH_AW_5 0x386738
+
+#define mmNIF_RTR_CTRL_0_RANGE_PRIV_BASE_HIGH_AW_6 0x38673C
+
+#define mmNIF_RTR_CTRL_0_RANGE_PRIV_BASE_HIGH_AW_7 0x386740
+
+#define mmNIF_RTR_CTRL_0_RANGE_PRIV_BASE_HIGH_AW_8 0x386744
+
+#define mmNIF_RTR_CTRL_0_RANGE_PRIV_BASE_HIGH_AW_9 0x386748
+
+#define mmNIF_RTR_CTRL_0_RANGE_PRIV_BASE_HIGH_AW_10 0x38674C
+
+#define mmNIF_RTR_CTRL_0_RANGE_PRIV_BASE_HIGH_AW_11 0x386750
+
+#define mmNIF_RTR_CTRL_0_RANGE_PRIV_BASE_HIGH_AW_12 0x386754
+
+#define mmNIF_RTR_CTRL_0_RANGE_PRIV_BASE_HIGH_AW_13 0x386758
+
+#define mmNIF_RTR_CTRL_0_RANGE_PRIV_BASE_HIGH_AW_14 0x38675C
+
+#define mmNIF_RTR_CTRL_0_RANGE_PRIV_BASE_HIGH_AW_15 0x386760
+
+#define mmNIF_RTR_CTRL_0_RANGE_PRIV_MASK_LOW_AW_0 0x386764
+
+#define mmNIF_RTR_CTRL_0_RANGE_PRIV_MASK_LOW_AW_1 0x386768
+
+#define mmNIF_RTR_CTRL_0_RANGE_PRIV_MASK_LOW_AW_2 0x38676C
+
+#define mmNIF_RTR_CTRL_0_RANGE_PRIV_MASK_LOW_AW_3 0x386770
+
+#define mmNIF_RTR_CTRL_0_RANGE_PRIV_MASK_LOW_AW_4 0x386774
+
+#define mmNIF_RTR_CTRL_0_RANGE_PRIV_MASK_LOW_AW_5 0x386778
+
+#define mmNIF_RTR_CTRL_0_RANGE_PRIV_MASK_LOW_AW_6 0x38677C
+
+#define mmNIF_RTR_CTRL_0_RANGE_PRIV_MASK_LOW_AW_7 0x386780
+
+#define mmNIF_RTR_CTRL_0_RANGE_PRIV_MASK_LOW_AW_8 0x386784
+
+#define mmNIF_RTR_CTRL_0_RANGE_PRIV_MASK_LOW_AW_9 0x386788
+
+#define mmNIF_RTR_CTRL_0_RANGE_PRIV_MASK_LOW_AW_10 0x38678C
+
+#define mmNIF_RTR_CTRL_0_RANGE_PRIV_MASK_LOW_AW_11 0x386790
+
+#define mmNIF_RTR_CTRL_0_RANGE_PRIV_MASK_LOW_AW_12 0x386794
+
+#define mmNIF_RTR_CTRL_0_RANGE_PRIV_MASK_LOW_AW_13 0x386798
+
+#define mmNIF_RTR_CTRL_0_RANGE_PRIV_MASK_LOW_AW_14 0x38679C
+
+#define mmNIF_RTR_CTRL_0_RANGE_PRIV_MASK_LOW_AW_15 0x3867A0
+
+#define mmNIF_RTR_CTRL_0_RANGE_PRIV_MASK_HIGH_AW_0 0x3867A4
+
+#define mmNIF_RTR_CTRL_0_RANGE_PRIV_MASK_HIGH_AW_1 0x3867A8
+
+#define mmNIF_RTR_CTRL_0_RANGE_PRIV_MASK_HIGH_AW_2 0x3867AC
+
+#define mmNIF_RTR_CTRL_0_RANGE_PRIV_MASK_HIGH_AW_3 0x3867B0
+
+#define mmNIF_RTR_CTRL_0_RANGE_PRIV_MASK_HIGH_AW_4 0x3867B4
+
+#define mmNIF_RTR_CTRL_0_RANGE_PRIV_MASK_HIGH_AW_5 0x3867B8
+
+#define mmNIF_RTR_CTRL_0_RANGE_PRIV_MASK_HIGH_AW_6 0x3867BC
+
+#define mmNIF_RTR_CTRL_0_RANGE_PRIV_MASK_HIGH_AW_7 0x3867C0
+
+#define mmNIF_RTR_CTRL_0_RANGE_PRIV_MASK_HIGH_AW_8 0x3867C4
+
+#define mmNIF_RTR_CTRL_0_RANGE_PRIV_MASK_HIGH_AW_9 0x3867C8
+
+#define mmNIF_RTR_CTRL_0_RANGE_PRIV_MASK_HIGH_AW_10 0x3867CC
+
+#define mmNIF_RTR_CTRL_0_RANGE_PRIV_MASK_HIGH_AW_11 0x3867D0
+
+#define mmNIF_RTR_CTRL_0_RANGE_PRIV_MASK_HIGH_AW_12 0x3867D4
+
+#define mmNIF_RTR_CTRL_0_RANGE_PRIV_MASK_HIGH_AW_13 0x3867D8
+
+#define mmNIF_RTR_CTRL_0_RANGE_PRIV_MASK_HIGH_AW_14 0x3867DC
+
+#define mmNIF_RTR_CTRL_0_RANGE_PRIV_MASK_HIGH_AW_15 0x3867E0
+
+#define mmNIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AR_0 0x386824
+
+#define mmNIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AR_1 0x386828
+
+#define mmNIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AR_2 0x38682C
+
+#define mmNIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AR_3 0x386830
+
+#define mmNIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AR_4 0x386834
+
+#define mmNIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AR_5 0x386838
+
+#define mmNIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AR_6 0x38683C
+
+#define mmNIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AR_7 0x386840
+
+#define mmNIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AR_8 0x386844
+
+#define mmNIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AR_9 0x386848
+
+#define mmNIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AR_10 0x38684C
+
+#define mmNIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AR_11 0x386850
+
+#define mmNIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AR_12 0x386854
+
+#define mmNIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AR_13 0x386858
+
+#define mmNIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AR_14 0x38685C
+
+#define mmNIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AR_15 0x386860
+
+#define mmNIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AR_0 0x386864
+
+#define mmNIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AR_1 0x386868
+
+#define mmNIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AR_2 0x38686C
+
+#define mmNIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AR_3 0x386870
+
+#define mmNIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AR_4 0x386874
+
+#define mmNIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AR_5 0x386878
+
+#define mmNIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AR_6 0x38687C
+
+#define mmNIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AR_7 0x386880
+
+#define mmNIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AR_8 0x386884
+
+#define mmNIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AR_9 0x386888
+
+#define mmNIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AR_10 0x38688C
+
+#define mmNIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AR_11 0x386890
+
+#define mmNIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AR_12 0x386894
+
+#define mmNIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AR_13 0x386898
+
+#define mmNIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AR_14 0x38689C
+
+#define mmNIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AR_15 0x3868A0
+
+#define mmNIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AR_0 0x3868A4
+
+#define mmNIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AR_1 0x3868A8
+
+#define mmNIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AR_2 0x3868AC
+
+#define mmNIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AR_3 0x3868B0
+
+#define mmNIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AR_4 0x3868B4
+
+#define mmNIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AR_5 0x3868B8
+
+#define mmNIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AR_6 0x3868BC
+
+#define mmNIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AR_7 0x3868C0
+
+#define mmNIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AR_8 0x3868C4
+
+#define mmNIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AR_9 0x3868C8
+
+#define mmNIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AR_10 0x3868CC
+
+#define mmNIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AR_11 0x3868D0
+
+#define mmNIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AR_12 0x3868D4
+
+#define mmNIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AR_13 0x3868D8
+
+#define mmNIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AR_14 0x3868DC
+
+#define mmNIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AR_15 0x3868E0
+
+#define mmNIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AR_0 0x3868E4
+
+#define mmNIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AR_1 0x3868E8
+
+#define mmNIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AR_2 0x3868EC
+
+#define mmNIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AR_3 0x3868F0
+
+#define mmNIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AR_4 0x3868F4
+
+#define mmNIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AR_5 0x3868F8
+
+#define mmNIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AR_6 0x3868FC
+
+#define mmNIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AR_7 0x386900
+
+#define mmNIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AR_8 0x386904
+
+#define mmNIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AR_9 0x386908
+
+#define mmNIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AR_10 0x38690C
+
+#define mmNIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AR_11 0x386910
+
+#define mmNIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AR_12 0x386914
+
+#define mmNIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AR_13 0x386918
+
+#define mmNIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AR_14 0x38691C
+
+#define mmNIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AR_15 0x386920
+
+#define mmNIF_RTR_CTRL_0_RANGE_PRIV_BASE_LOW_AR_0 0x386924
+
+#define mmNIF_RTR_CTRL_0_RANGE_PRIV_BASE_LOW_AR_1 0x386928
+
+#define mmNIF_RTR_CTRL_0_RANGE_PRIV_BASE_LOW_AR_2 0x38692C
+
+#define mmNIF_RTR_CTRL_0_RANGE_PRIV_BASE_LOW_AR_3 0x386930
+
+#define mmNIF_RTR_CTRL_0_RANGE_PRIV_BASE_LOW_AR_4 0x386934
+
+#define mmNIF_RTR_CTRL_0_RANGE_PRIV_BASE_LOW_AR_5 0x386938
+
+#define mmNIF_RTR_CTRL_0_RANGE_PRIV_BASE_LOW_AR_6 0x38693C
+
+#define mmNIF_RTR_CTRL_0_RANGE_PRIV_BASE_LOW_AR_7 0x386940
+
+#define mmNIF_RTR_CTRL_0_RANGE_PRIV_BASE_LOW_AR_8 0x386944
+
+#define mmNIF_RTR_CTRL_0_RANGE_PRIV_BASE_LOW_AR_9 0x386948
+
+#define mmNIF_RTR_CTRL_0_RANGE_PRIV_BASE_LOW_AR_10 0x38694C
+
+#define mmNIF_RTR_CTRL_0_RANGE_PRIV_BASE_LOW_AR_11 0x386950
+
+#define mmNIF_RTR_CTRL_0_RANGE_PRIV_BASE_LOW_AR_12 0x386954
+
+#define mmNIF_RTR_CTRL_0_RANGE_PRIV_BASE_LOW_AR_13 0x386958
+
+#define mmNIF_RTR_CTRL_0_RANGE_PRIV_BASE_LOW_AR_14 0x38695C
+
+#define mmNIF_RTR_CTRL_0_RANGE_PRIV_BASE_LOW_AR_15 0x386960
+
+#define mmNIF_RTR_CTRL_0_RANGE_PRIV_BASE_HIGH_AR_0 0x386964
+
+#define mmNIF_RTR_CTRL_0_RANGE_PRIV_BASE_HIGH_AR_1 0x386968
+
+#define mmNIF_RTR_CTRL_0_RANGE_PRIV_BASE_HIGH_AR_2 0x38696C
+
+#define mmNIF_RTR_CTRL_0_RANGE_PRIV_BASE_HIGH_AR_3 0x386970
+
+#define mmNIF_RTR_CTRL_0_RANGE_PRIV_BASE_HIGH_AR_4 0x386974
+
+#define mmNIF_RTR_CTRL_0_RANGE_PRIV_BASE_HIGH_AR_5 0x386978
+
+#define mmNIF_RTR_CTRL_0_RANGE_PRIV_BASE_HIGH_AR_6 0x38697C
+
+#define mmNIF_RTR_CTRL_0_RANGE_PRIV_BASE_HIGH_AR_7 0x386980
+
+#define mmNIF_RTR_CTRL_0_RANGE_PRIV_BASE_HIGH_AR_8 0x386984
+
+#define mmNIF_RTR_CTRL_0_RANGE_PRIV_BASE_HIGH_AR_9 0x386988
+
+#define mmNIF_RTR_CTRL_0_RANGE_PRIV_BASE_HIGH_AR_10 0x38698C
+
+#define mmNIF_RTR_CTRL_0_RANGE_PRIV_BASE_HIGH_AR_11 0x386990
+
+#define mmNIF_RTR_CTRL_0_RANGE_PRIV_BASE_HIGH_AR_12 0x386994
+
+#define mmNIF_RTR_CTRL_0_RANGE_PRIV_BASE_HIGH_AR_13 0x386998
+
+#define mmNIF_RTR_CTRL_0_RANGE_PRIV_BASE_HIGH_AR_14 0x38699C
+
+#define mmNIF_RTR_CTRL_0_RANGE_PRIV_BASE_HIGH_AR_15 0x3869A0
+
+#define mmNIF_RTR_CTRL_0_RANGE_PRIV_MASK_LOW_AR_0 0x3869A4
+
+#define mmNIF_RTR_CTRL_0_RANGE_PRIV_MASK_LOW_AR_1 0x3869A8
+
+#define mmNIF_RTR_CTRL_0_RANGE_PRIV_MASK_LOW_AR_2 0x3869AC
+
+#define mmNIF_RTR_CTRL_0_RANGE_PRIV_MASK_LOW_AR_3 0x3869B0
+
+#define mmNIF_RTR_CTRL_0_RANGE_PRIV_MASK_LOW_AR_4 0x3869B4
+
+#define mmNIF_RTR_CTRL_0_RANGE_PRIV_MASK_LOW_AR_5 0x3869B8
+
+#define mmNIF_RTR_CTRL_0_RANGE_PRIV_MASK_LOW_AR_6 0x3869BC
+
+#define mmNIF_RTR_CTRL_0_RANGE_PRIV_MASK_LOW_AR_7 0x3869C0
+
+#define mmNIF_RTR_CTRL_0_RANGE_PRIV_MASK_LOW_AR_8 0x3869C4
+
+#define mmNIF_RTR_CTRL_0_RANGE_PRIV_MASK_LOW_AR_9 0x3869C8
+
+#define mmNIF_RTR_CTRL_0_RANGE_PRIV_MASK_LOW_AR_10 0x3869CC
+
+#define mmNIF_RTR_CTRL_0_RANGE_PRIV_MASK_LOW_AR_11 0x3869D0
+
+#define mmNIF_RTR_CTRL_0_RANGE_PRIV_MASK_LOW_AR_12 0x3869D4
+
+#define mmNIF_RTR_CTRL_0_RANGE_PRIV_MASK_LOW_AR_13 0x3869D8
+
+#define mmNIF_RTR_CTRL_0_RANGE_PRIV_MASK_LOW_AR_14 0x3869DC
+
+#define mmNIF_RTR_CTRL_0_RANGE_PRIV_MASK_LOW_AR_15 0x3869E0
+
+#define mmNIF_RTR_CTRL_0_RANGE_PRIV_MASK_HIGH_AR_0 0x3869E4
+
+#define mmNIF_RTR_CTRL_0_RANGE_PRIV_MASK_HIGH_AR_1 0x3869E8
+
+#define mmNIF_RTR_CTRL_0_RANGE_PRIV_MASK_HIGH_AR_2 0x3869EC
+
+#define mmNIF_RTR_CTRL_0_RANGE_PRIV_MASK_HIGH_AR_3 0x3869F0
+
+#define mmNIF_RTR_CTRL_0_RANGE_PRIV_MASK_HIGH_AR_4 0x3869F4
+
+#define mmNIF_RTR_CTRL_0_RANGE_PRIV_MASK_HIGH_AR_5 0x3869F8
+
+#define mmNIF_RTR_CTRL_0_RANGE_PRIV_MASK_HIGH_AR_6 0x3869FC
+
+#define mmNIF_RTR_CTRL_0_RANGE_PRIV_MASK_HIGH_AR_7 0x386A00
+
+#define mmNIF_RTR_CTRL_0_RANGE_PRIV_MASK_HIGH_AR_8 0x386A04
+
+#define mmNIF_RTR_CTRL_0_RANGE_PRIV_MASK_HIGH_AR_9 0x386A08
+
+#define mmNIF_RTR_CTRL_0_RANGE_PRIV_MASK_HIGH_AR_10 0x386A0C
+
+#define mmNIF_RTR_CTRL_0_RANGE_PRIV_MASK_HIGH_AR_11 0x386A10
+
+#define mmNIF_RTR_CTRL_0_RANGE_PRIV_MASK_HIGH_AR_12 0x386A14
+
+#define mmNIF_RTR_CTRL_0_RANGE_PRIV_MASK_HIGH_AR_13 0x386A18
+
+#define mmNIF_RTR_CTRL_0_RANGE_PRIV_MASK_HIGH_AR_14 0x386A1C
+
+#define mmNIF_RTR_CTRL_0_RANGE_PRIV_MASK_HIGH_AR_15 0x386A20
+
+#define mmNIF_RTR_CTRL_0_RANGE_SEC_HIT_AW 0x386A64
+
+#define mmNIF_RTR_CTRL_0_RANGE_SEC_HIT_AR 0x386A68
+
+#define mmNIF_RTR_CTRL_0_RANGE_PRIV_HIT_AW 0x386A6C
+
+#define mmNIF_RTR_CTRL_0_RANGE_PRIV_HIT_AR 0x386A70
+
+#define mmNIF_RTR_CTRL_0_RGL_CFG 0x386B64
+
+#define mmNIF_RTR_CTRL_0_RGL_SHIFT 0x386B68
+
+#define mmNIF_RTR_CTRL_0_RGL_EXPECTED_LAT_0 0x386B6C
+
+#define mmNIF_RTR_CTRL_0_RGL_EXPECTED_LAT_1 0x386B70
+
+#define mmNIF_RTR_CTRL_0_RGL_EXPECTED_LAT_2 0x386B74
+
+#define mmNIF_RTR_CTRL_0_RGL_EXPECTED_LAT_3 0x386B78
+
+#define mmNIF_RTR_CTRL_0_RGL_EXPECTED_LAT_4 0x386B7C
+
+#define mmNIF_RTR_CTRL_0_RGL_EXPECTED_LAT_5 0x386B80
+
+#define mmNIF_RTR_CTRL_0_RGL_EXPECTED_LAT_6 0x386B84
+
+#define mmNIF_RTR_CTRL_0_RGL_EXPECTED_LAT_7 0x386B88
+
+#define mmNIF_RTR_CTRL_0_RGL_TOKEN_0 0x386BAC
+
+#define mmNIF_RTR_CTRL_0_RGL_TOKEN_1 0x386BB0
+
+#define mmNIF_RTR_CTRL_0_RGL_TOKEN_2 0x386BB4
+
+#define mmNIF_RTR_CTRL_0_RGL_TOKEN_3 0x386BB8
+
+#define mmNIF_RTR_CTRL_0_RGL_TOKEN_4 0x386BBC
+
+#define mmNIF_RTR_CTRL_0_RGL_TOKEN_5 0x386BC0
+
+#define mmNIF_RTR_CTRL_0_RGL_TOKEN_6 0x386BC4
+
+#define mmNIF_RTR_CTRL_0_RGL_TOKEN_7 0x386BC8
+
+#define mmNIF_RTR_CTRL_0_RGL_BANK_ID_0 0x386BEC
+
+#define mmNIF_RTR_CTRL_0_RGL_BANK_ID_1 0x386BF0
+
+#define mmNIF_RTR_CTRL_0_RGL_BANK_ID_2 0x386BF4
+
+#define mmNIF_RTR_CTRL_0_RGL_BANK_ID_3 0x386BF8
+
+#define mmNIF_RTR_CTRL_0_RGL_BANK_ID_4 0x386BFC
+
+#define mmNIF_RTR_CTRL_0_RGL_BANK_ID_5 0x386C00
+
+#define mmNIF_RTR_CTRL_0_RGL_BANK_ID_6 0x386C04
+
+#define mmNIF_RTR_CTRL_0_RGL_BANK_ID_7 0x386C08
+
+#define mmNIF_RTR_CTRL_0_RGL_WDT 0x386C2C
+
+#define mmNIF_RTR_CTRL_0_E2E_AR_HBM0_CH0_CTR_WRAP 0x386C30
+
+#define mmNIF_RTR_CTRL_0_E2E_AR_HBM0_CH1_CTR_WRAP 0x386C34
+
+#define mmNIF_RTR_CTRL_0_E2E_AR_HBM1_CH0_CTR_WRAP 0x386C38
+
+#define mmNIF_RTR_CTRL_0_E2E_AR_HBM1_CH1_CTR_WRAP 0x386C3C
+
+#define mmNIF_RTR_CTRL_0_E2E_AR_HBM2_CH0_CTR_WRAP 0x386C40
+
+#define mmNIF_RTR_CTRL_0_E2E_AR_HBM2_CH1_CTR_WRAP 0x386C44
+
+#define mmNIF_RTR_CTRL_0_E2E_AR_HBM3_CH0_CTR_WRAP 0x386C48
+
+#define mmNIF_RTR_CTRL_0_E2E_AR_HBM3_CH1_CTR_WRAP 0x386C4C
+
+#define mmNIF_RTR_CTRL_0_E2E_AR_HBM0_CH0_CTR_CNT 0x386C50
+
+#define mmNIF_RTR_CTRL_0_E2E_AR_HBM0_CH1_CTR_CNT 0x386C54
+
+#define mmNIF_RTR_CTRL_0_E2E_AR_HBM1_CH0_CTR_CNT 0x386C58
+
+#define mmNIF_RTR_CTRL_0_E2E_AR_HBM1_CH1_CTR_CNT 0x386C5C
+
+#define mmNIF_RTR_CTRL_0_E2E_AR_HBM2_CH0_CTR_CNT 0x386C60
+
+#define mmNIF_RTR_CTRL_0_E2E_AR_HBM2_CH1_CTR_CNT 0x386C64
+
+#define mmNIF_RTR_CTRL_0_E2E_AR_HBM3_CH0_CTR_CNT 0x386C68
+
+#define mmNIF_RTR_CTRL_0_E2E_AR_HBM3_CH1_CTR_CNT 0x386C6C
+
+#define mmNIF_RTR_CTRL_0_E2E_AW_HBM0_CH0_CTR_WRAP 0x386C70
+
+#define mmNIF_RTR_CTRL_0_E2E_AW_HBM0_CH1_CTR_WRAP 0x386C74
+
+#define mmNIF_RTR_CTRL_0_E2E_AW_HBM1_CH0_CTR_WRAP 0x386C78
+
+#define mmNIF_RTR_CTRL_0_E2E_AW_HBM1_CH1_CTR_WRAP 0x386C7C
+
+#define mmNIF_RTR_CTRL_0_E2E_AW_HBM2_CH0_CTR_WRAP 0x386C80
+
+#define mmNIF_RTR_CTRL_0_E2E_AW_HBM2_CH1_CTR_WRAP 0x386C84
+
+#define mmNIF_RTR_CTRL_0_E2E_AW_HBM3_CH0_CTR_WRAP 0x386C88
+
+#define mmNIF_RTR_CTRL_0_E2E_AW_HBM3_CH1_CTR_WRAP 0x386C8C
+
+#define mmNIF_RTR_CTRL_0_E2E_AW_HBM0_CH0_CTR_CNT 0x386C90
+
+#define mmNIF_RTR_CTRL_0_E2E_AW_HBM0_CH1_CTR_CNT 0x386C94
+
+#define mmNIF_RTR_CTRL_0_E2E_AW_HBM1_CH0_CTR_CNT 0x386C98
+
+#define mmNIF_RTR_CTRL_0_E2E_AW_HBM1_CH1_CTR_CNT 0x386C9C
+
+#define mmNIF_RTR_CTRL_0_E2E_AW_HBM2_CH0_CTR_CNT 0x386CA0
+
+#define mmNIF_RTR_CTRL_0_E2E_AW_HBM2_CH1_CTR_CNT 0x386CA4
+
+#define mmNIF_RTR_CTRL_0_E2E_AW_HBM3_CH0_CTR_CNT 0x386CA8
+
+#define mmNIF_RTR_CTRL_0_E2E_AW_HBM3_CH1_CTR_CNT 0x386CAC
+
+#define mmNIF_RTR_CTRL_0_NL_HBM_PC_SEL_0 0x386CB0
+
+#define mmNIF_RTR_CTRL_0_NL_HBM_PC_SEL_1 0x386CB4
+
+#define mmNIF_RTR_CTRL_0_NL_HBM_PC_SEL_2 0x386CB8
+
+#define mmNIF_RTR_CTRL_0_NL_HBM_PC_SEL_3 0x386CBC
+
+#endif /* ASIC_REG_NIF_RTR_CTRL_0_REGS_H_ */
diff --git a/drivers/accel/habanalabs/include/gaudi/asic_reg/nif_rtr_ctrl_1_regs.h b/drivers/accel/habanalabs/include/gaudi/asic_reg/nif_rtr_ctrl_1_regs.h
new file mode 100644
index 0000000000..a6047d4e25
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi/asic_reg/nif_rtr_ctrl_1_regs.h
@@ -0,0 +1,896 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2016-2018 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ ** DO NOT EDIT BELOW **
+ ************************************/
+
+#ifndef ASIC_REG_NIF_RTR_CTRL_1_REGS_H_
+#define ASIC_REG_NIF_RTR_CTRL_1_REGS_H_
+
+/*
+ *****************************************
+ * NIF_RTR_CTRL_1 (Prototype: RTR_CTRL)
+ *****************************************
+ */
+
+#define mmNIF_RTR_CTRL_1_PERM_SEL 0x396108
+
+#define mmNIF_RTR_CTRL_1_HBM_POLY_H3_0 0x396114
+
+#define mmNIF_RTR_CTRL_1_HBM_POLY_H3_1 0x396118
+
+#define mmNIF_RTR_CTRL_1_HBM_POLY_H3_2 0x39611C
+
+#define mmNIF_RTR_CTRL_1_HBM_POLY_H3_3 0x396120
+
+#define mmNIF_RTR_CTRL_1_HBM_POLY_H3_4 0x396124
+
+#define mmNIF_RTR_CTRL_1_HBM_POLY_H3_5 0x396128
+
+#define mmNIF_RTR_CTRL_1_HBM_POLY_H3_6 0x39612C
+
+#define mmNIF_RTR_CTRL_1_HBM_POLY_H3_7 0x396130
+
+#define mmNIF_RTR_CTRL_1_HBM_POLY_H3_8 0x396134
+
+#define mmNIF_RTR_CTRL_1_HBM_POLY_H3_9 0x396138
+
+#define mmNIF_RTR_CTRL_1_HBM_POLY_H3_10 0x39613C
+
+#define mmNIF_RTR_CTRL_1_HBM_POLY_H3_11 0x396140
+
+#define mmNIF_RTR_CTRL_1_HBM_POLY_H3_12 0x396144
+
+#define mmNIF_RTR_CTRL_1_HBM_POLY_H3_13 0x396148
+
+#define mmNIF_RTR_CTRL_1_HBM_POLY_H3_14 0x39614C
+
+#define mmNIF_RTR_CTRL_1_HBM_POLY_H3_15 0x396150
+
+#define mmNIF_RTR_CTRL_1_HBM_POLY_H3_16 0x396154
+
+#define mmNIF_RTR_CTRL_1_HBM_POLY_H3_17 0x396158
+
+#define mmNIF_RTR_CTRL_1_HBM_POLY_H3_18 0x39615C
+
+#define mmNIF_RTR_CTRL_1_HBM_POLY_H3_19 0x396160
+
+#define mmNIF_RTR_CTRL_1_HBM_POLY_H3_20 0x396164
+
+#define mmNIF_RTR_CTRL_1_HBM_POLY_H3_21 0x396168
+
+#define mmNIF_RTR_CTRL_1_HBM_POLY_H3_22 0x39616C
+
+#define mmNIF_RTR_CTRL_1_HBM_POLY_H3_23 0x396170
+
+#define mmNIF_RTR_CTRL_1_HBM_POLY_H3_24 0x396174
+
+#define mmNIF_RTR_CTRL_1_HBM_POLY_H3_25 0x396178
+
+#define mmNIF_RTR_CTRL_1_HBM_POLY_H3_26 0x39617C
+
+#define mmNIF_RTR_CTRL_1_HBM_POLY_H3_27 0x396180
+
+#define mmNIF_RTR_CTRL_1_SRAM_POLY_H3_0 0x396184
+
+#define mmNIF_RTR_CTRL_1_SRAM_POLY_H3_1 0x396188
+
+#define mmNIF_RTR_CTRL_1_SRAM_POLY_H3_2 0x39618C
+
+#define mmNIF_RTR_CTRL_1_SRAM_POLY_H3_3 0x396190
+
+#define mmNIF_RTR_CTRL_1_SRAM_POLY_H3_4 0x396194
+
+#define mmNIF_RTR_CTRL_1_SRAM_POLY_H3_5 0x396198
+
+#define mmNIF_RTR_CTRL_1_SRAM_POLY_H3_6 0x39619C
+
+#define mmNIF_RTR_CTRL_1_SRAM_POLY_H3_7 0x3961A0
+
+#define mmNIF_RTR_CTRL_1_SRAM_POLY_H3_8 0x3961A4
+
+#define mmNIF_RTR_CTRL_1_SRAM_POLY_H3_9 0x3961A8
+
+#define mmNIF_RTR_CTRL_1_SRAM_POLY_H3_10 0x3961AC
+
+#define mmNIF_RTR_CTRL_1_SRAM_POLY_H3_11 0x3961B0
+
+#define mmNIF_RTR_CTRL_1_SRAM_POLY_H3_12 0x3961B4
+
+#define mmNIF_RTR_CTRL_1_SRAM_POLY_H3_13 0x3961B8
+
+#define mmNIF_RTR_CTRL_1_SRAM_POLY_H3_14 0x3961BC
+
+#define mmNIF_RTR_CTRL_1_SCRAM_SRAM_EN 0x39626C
+
+#define mmNIF_RTR_CTRL_1_RL_HBM_EN 0x396274
+
+#define mmNIF_RTR_CTRL_1_RL_HBM_SAT 0x396278
+
+#define mmNIF_RTR_CTRL_1_RL_HBM_RST 0x39627C
+
+#define mmNIF_RTR_CTRL_1_RL_HBM_TIMEOUT 0x396280
+
+#define mmNIF_RTR_CTRL_1_SCRAM_HBM_EN 0x396284
+
+#define mmNIF_RTR_CTRL_1_RL_PCI_EN 0x396288
+
+#define mmNIF_RTR_CTRL_1_RL_PCI_SAT 0x39628C
+
+#define mmNIF_RTR_CTRL_1_RL_PCI_RST 0x396290
+
+#define mmNIF_RTR_CTRL_1_RL_PCI_TIMEOUT 0x396294
+
+#define mmNIF_RTR_CTRL_1_RL_SRAM_EN 0x39629C
+
+#define mmNIF_RTR_CTRL_1_RL_SRAM_SAT 0x3962A0
+
+#define mmNIF_RTR_CTRL_1_RL_SRAM_RST 0x3962A4
+
+#define mmNIF_RTR_CTRL_1_RL_SRAM_TIMEOUT 0x3962AC
+
+#define mmNIF_RTR_CTRL_1_RL_SRAM_RED 0x3962B4
+
+#define mmNIF_RTR_CTRL_1_E2E_HBM_EN 0x3962EC
+
+#define mmNIF_RTR_CTRL_1_E2E_PCI_EN 0x3962F0
+
+#define mmNIF_RTR_CTRL_1_E2E_HBM_WR_SIZE 0x3962F4
+
+#define mmNIF_RTR_CTRL_1_E2E_PCI_WR_SIZE 0x3962F8
+
+#define mmNIF_RTR_CTRL_1_E2E_AW_PCI_CTR_SET_EN 0x396404
+
+#define mmNIF_RTR_CTRL_1_E2E_AW_PCI_CTR_SET 0x396408
+
+#define mmNIF_RTR_CTRL_1_E2E_AW_PCI_CTR_WRAP 0x39640C
+
+#define mmNIF_RTR_CTRL_1_E2E_AW_PCI_CTR_CNT 0x396410
+
+#define mmNIF_RTR_CTRL_1_E2E_AW_HBM_CTR_SET_EN 0x396414
+
+#define mmNIF_RTR_CTRL_1_E2E_AW_HBM_CTR_SET 0x396418
+
+#define mmNIF_RTR_CTRL_1_E2E_HBM_RD_SIZE 0x39641C
+
+#define mmNIF_RTR_CTRL_1_E2E_PCI_RD_SIZE 0x396420
+
+#define mmNIF_RTR_CTRL_1_E2E_AR_PCI_CTR_SET_EN 0x396424
+
+#define mmNIF_RTR_CTRL_1_E2E_AR_PCI_CTR_SET 0x396428
+
+#define mmNIF_RTR_CTRL_1_E2E_AR_PCI_CTR_WRAP 0x39642C
+
+#define mmNIF_RTR_CTRL_1_E2E_AR_PCI_CTR_CNT 0x396430
+
+#define mmNIF_RTR_CTRL_1_E2E_AR_HBM_CTR_SET_EN 0x396434
+
+#define mmNIF_RTR_CTRL_1_E2E_AR_HBM_CTR_SET 0x396438
+
+#define mmNIF_RTR_CTRL_1_NL_HBM_SEL_0 0x396450
+
+#define mmNIF_RTR_CTRL_1_NL_HBM_SEL_1 0x396454
+
+#define mmNIF_RTR_CTRL_1_NON_LIN_EN 0x396480
+
+#define mmNIF_RTR_CTRL_1_NL_SRAM_BANK_0 0x396500
+
+#define mmNIF_RTR_CTRL_1_NL_SRAM_BANK_1 0x396504
+
+#define mmNIF_RTR_CTRL_1_NL_SRAM_BANK_2 0x396508
+
+#define mmNIF_RTR_CTRL_1_NL_SRAM_BANK_3 0x39650C
+
+#define mmNIF_RTR_CTRL_1_NL_SRAM_BANK_4 0x396510
+
+#define mmNIF_RTR_CTRL_1_NL_SRAM_OFFSET_0 0x396514
+
+#define mmNIF_RTR_CTRL_1_NL_SRAM_OFFSET_1 0x396520
+
+#define mmNIF_RTR_CTRL_1_NL_SRAM_OFFSET_2 0x396524
+
+#define mmNIF_RTR_CTRL_1_NL_SRAM_OFFSET_3 0x396528
+
+#define mmNIF_RTR_CTRL_1_NL_SRAM_OFFSET_4 0x39652C
+
+#define mmNIF_RTR_CTRL_1_NL_SRAM_OFFSET_5 0x396530
+
+#define mmNIF_RTR_CTRL_1_NL_SRAM_OFFSET_6 0x396534
+
+#define mmNIF_RTR_CTRL_1_NL_SRAM_OFFSET_7 0x396538
+
+#define mmNIF_RTR_CTRL_1_NL_SRAM_OFFSET_8 0x39653C
+
+#define mmNIF_RTR_CTRL_1_NL_SRAM_OFFSET_9 0x396540
+
+#define mmNIF_RTR_CTRL_1_NL_HBM_OFFSET_0 0x396550
+
+#define mmNIF_RTR_CTRL_1_NL_HBM_OFFSET_1 0x396554
+
+#define mmNIF_RTR_CTRL_1_NL_HBM_OFFSET_2 0x396558
+
+#define mmNIF_RTR_CTRL_1_NL_HBM_OFFSET_3 0x39655C
+
+#define mmNIF_RTR_CTRL_1_NL_HBM_OFFSET_4 0x396560
+
+#define mmNIF_RTR_CTRL_1_NL_HBM_OFFSET_5 0x396564
+
+#define mmNIF_RTR_CTRL_1_NL_HBM_OFFSET_6 0x396568
+
+#define mmNIF_RTR_CTRL_1_NL_HBM_OFFSET_7 0x39656C
+
+#define mmNIF_RTR_CTRL_1_NL_HBM_OFFSET_8 0x396570
+
+#define mmNIF_RTR_CTRL_1_NL_HBM_OFFSET_9 0x396574
+
+#define mmNIF_RTR_CTRL_1_NL_HBM_OFFSET_10 0x396578
+
+#define mmNIF_RTR_CTRL_1_NL_HBM_OFFSET_11 0x39657C
+
+#define mmNIF_RTR_CTRL_1_NL_HBM_OFFSET_12 0x396580
+
+#define mmNIF_RTR_CTRL_1_NL_HBM_OFFSET_13 0x396584
+
+#define mmNIF_RTR_CTRL_1_NL_HBM_OFFSET_14 0x396588
+
+#define mmNIF_RTR_CTRL_1_NL_HBM_OFFSET_15 0x39658C
+
+#define mmNIF_RTR_CTRL_1_NL_HBM_OFFSET_16 0x396590
+
+#define mmNIF_RTR_CTRL_1_NL_HBM_OFFSET_17 0x396594
+
+#define mmNIF_RTR_CTRL_1_NL_HBM_OFFSET_18 0x396598
+
+#define mmNIF_RTR_CTRL_1_RANGE_SEC_BASE_LOW_AW_0 0x3965E4
+
+#define mmNIF_RTR_CTRL_1_RANGE_SEC_BASE_LOW_AW_1 0x3965E8
+
+#define mmNIF_RTR_CTRL_1_RANGE_SEC_BASE_LOW_AW_2 0x3965EC
+
+#define mmNIF_RTR_CTRL_1_RANGE_SEC_BASE_LOW_AW_3 0x3965F0
+
+#define mmNIF_RTR_CTRL_1_RANGE_SEC_BASE_LOW_AW_4 0x3965F4
+
+#define mmNIF_RTR_CTRL_1_RANGE_SEC_BASE_LOW_AW_5 0x3965F8
+
+#define mmNIF_RTR_CTRL_1_RANGE_SEC_BASE_LOW_AW_6 0x3965FC
+
+#define mmNIF_RTR_CTRL_1_RANGE_SEC_BASE_LOW_AW_7 0x396600
+
+#define mmNIF_RTR_CTRL_1_RANGE_SEC_BASE_LOW_AW_8 0x396604
+
+#define mmNIF_RTR_CTRL_1_RANGE_SEC_BASE_LOW_AW_9 0x396608
+
+#define mmNIF_RTR_CTRL_1_RANGE_SEC_BASE_LOW_AW_10 0x39660C
+
+#define mmNIF_RTR_CTRL_1_RANGE_SEC_BASE_LOW_AW_11 0x396610
+
+#define mmNIF_RTR_CTRL_1_RANGE_SEC_BASE_LOW_AW_12 0x396614
+
+#define mmNIF_RTR_CTRL_1_RANGE_SEC_BASE_LOW_AW_13 0x396618
+
+#define mmNIF_RTR_CTRL_1_RANGE_SEC_BASE_LOW_AW_14 0x39661C
+
+#define mmNIF_RTR_CTRL_1_RANGE_SEC_BASE_LOW_AW_15 0x396620
+
+#define mmNIF_RTR_CTRL_1_RANGE_SEC_BASE_HIGH_AW_0 0x396624
+
+#define mmNIF_RTR_CTRL_1_RANGE_SEC_BASE_HIGH_AW_1 0x396628
+
+#define mmNIF_RTR_CTRL_1_RANGE_SEC_BASE_HIGH_AW_2 0x39662C
+
+#define mmNIF_RTR_CTRL_1_RANGE_SEC_BASE_HIGH_AW_3 0x396630
+
+#define mmNIF_RTR_CTRL_1_RANGE_SEC_BASE_HIGH_AW_4 0x396634
+
+#define mmNIF_RTR_CTRL_1_RANGE_SEC_BASE_HIGH_AW_5 0x396638
+
+#define mmNIF_RTR_CTRL_1_RANGE_SEC_BASE_HIGH_AW_6 0x39663C
+
+#define mmNIF_RTR_CTRL_1_RANGE_SEC_BASE_HIGH_AW_7 0x396640
+
+#define mmNIF_RTR_CTRL_1_RANGE_SEC_BASE_HIGH_AW_8 0x396644
+
+#define mmNIF_RTR_CTRL_1_RANGE_SEC_BASE_HIGH_AW_9 0x396648
+
+#define mmNIF_RTR_CTRL_1_RANGE_SEC_BASE_HIGH_AW_10 0x39664C
+
+#define mmNIF_RTR_CTRL_1_RANGE_SEC_BASE_HIGH_AW_11 0x396650
+
+#define mmNIF_RTR_CTRL_1_RANGE_SEC_BASE_HIGH_AW_12 0x396654
+
+#define mmNIF_RTR_CTRL_1_RANGE_SEC_BASE_HIGH_AW_13 0x396658
+
+#define mmNIF_RTR_CTRL_1_RANGE_SEC_BASE_HIGH_AW_14 0x39665C
+
+#define mmNIF_RTR_CTRL_1_RANGE_SEC_BASE_HIGH_AW_15 0x396660
+
+#define mmNIF_RTR_CTRL_1_RANGE_SEC_MASK_LOW_AW_0 0x396664
+
+#define mmNIF_RTR_CTRL_1_RANGE_SEC_MASK_LOW_AW_1 0x396668
+
+#define mmNIF_RTR_CTRL_1_RANGE_SEC_MASK_LOW_AW_2 0x39666C
+
+#define mmNIF_RTR_CTRL_1_RANGE_SEC_MASK_LOW_AW_3 0x396670
+
+#define mmNIF_RTR_CTRL_1_RANGE_SEC_MASK_LOW_AW_4 0x396674
+
+#define mmNIF_RTR_CTRL_1_RANGE_SEC_MASK_LOW_AW_5 0x396678
+
+#define mmNIF_RTR_CTRL_1_RANGE_SEC_MASK_LOW_AW_6 0x39667C
+
+#define mmNIF_RTR_CTRL_1_RANGE_SEC_MASK_LOW_AW_7 0x396680
+
+#define mmNIF_RTR_CTRL_1_RANGE_SEC_MASK_LOW_AW_8 0x396684
+
+#define mmNIF_RTR_CTRL_1_RANGE_SEC_MASK_LOW_AW_9 0x396688
+
+#define mmNIF_RTR_CTRL_1_RANGE_SEC_MASK_LOW_AW_10 0x39668C
+
+#define mmNIF_RTR_CTRL_1_RANGE_SEC_MASK_LOW_AW_11 0x396690
+
+#define mmNIF_RTR_CTRL_1_RANGE_SEC_MASK_LOW_AW_12 0x396694
+
+#define mmNIF_RTR_CTRL_1_RANGE_SEC_MASK_LOW_AW_13 0x396698
+
+#define mmNIF_RTR_CTRL_1_RANGE_SEC_MASK_LOW_AW_14 0x39669C
+
+#define mmNIF_RTR_CTRL_1_RANGE_SEC_MASK_LOW_AW_15 0x3966A0
+
+#define mmNIF_RTR_CTRL_1_RANGE_SEC_MASK_HIGH_AW_0 0x3966A4
+
+#define mmNIF_RTR_CTRL_1_RANGE_SEC_MASK_HIGH_AW_1 0x3966A8
+
+#define mmNIF_RTR_CTRL_1_RANGE_SEC_MASK_HIGH_AW_2 0x3966AC
+
+#define mmNIF_RTR_CTRL_1_RANGE_SEC_MASK_HIGH_AW_3 0x3966B0
+
+#define mmNIF_RTR_CTRL_1_RANGE_SEC_MASK_HIGH_AW_4 0x3966B4
+
+#define mmNIF_RTR_CTRL_1_RANGE_SEC_MASK_HIGH_AW_5 0x3966B8
+
+#define mmNIF_RTR_CTRL_1_RANGE_SEC_MASK_HIGH_AW_6 0x3966BC
+
+#define mmNIF_RTR_CTRL_1_RANGE_SEC_MASK_HIGH_AW_7 0x3966C0
+
+#define mmNIF_RTR_CTRL_1_RANGE_SEC_MASK_HIGH_AW_8 0x3966C4
+
+#define mmNIF_RTR_CTRL_1_RANGE_SEC_MASK_HIGH_AW_9 0x3966C8
+
+#define mmNIF_RTR_CTRL_1_RANGE_SEC_MASK_HIGH_AW_10 0x3966CC
+
+#define mmNIF_RTR_CTRL_1_RANGE_SEC_MASK_HIGH_AW_11 0x3966D0
+
+#define mmNIF_RTR_CTRL_1_RANGE_SEC_MASK_HIGH_AW_12 0x3966D4
+
+#define mmNIF_RTR_CTRL_1_RANGE_SEC_MASK_HIGH_AW_13 0x3966D8
+
+#define mmNIF_RTR_CTRL_1_RANGE_SEC_MASK_HIGH_AW_14 0x3966DC
+
+#define mmNIF_RTR_CTRL_1_RANGE_SEC_MASK_HIGH_AW_15 0x3966E0
+
+#define mmNIF_RTR_CTRL_1_RANGE_PRIV_BASE_LOW_AW_0 0x3966E4
+
+#define mmNIF_RTR_CTRL_1_RANGE_PRIV_BASE_LOW_AW_1 0x3966E8
+
+#define mmNIF_RTR_CTRL_1_RANGE_PRIV_BASE_LOW_AW_2 0x3966EC
+
+#define mmNIF_RTR_CTRL_1_RANGE_PRIV_BASE_LOW_AW_3 0x3966F0
+
+#define mmNIF_RTR_CTRL_1_RANGE_PRIV_BASE_LOW_AW_4 0x3966F4
+
+#define mmNIF_RTR_CTRL_1_RANGE_PRIV_BASE_LOW_AW_5 0x3966F8
+
+#define mmNIF_RTR_CTRL_1_RANGE_PRIV_BASE_LOW_AW_6 0x3966FC
+
+#define mmNIF_RTR_CTRL_1_RANGE_PRIV_BASE_LOW_AW_7 0x396700
+
+#define mmNIF_RTR_CTRL_1_RANGE_PRIV_BASE_LOW_AW_8 0x396704
+
+#define mmNIF_RTR_CTRL_1_RANGE_PRIV_BASE_LOW_AW_9 0x396708
+
+#define mmNIF_RTR_CTRL_1_RANGE_PRIV_BASE_LOW_AW_10 0x39670C
+
+#define mmNIF_RTR_CTRL_1_RANGE_PRIV_BASE_LOW_AW_11 0x396710
+
+#define mmNIF_RTR_CTRL_1_RANGE_PRIV_BASE_LOW_AW_12 0x396714
+
+#define mmNIF_RTR_CTRL_1_RANGE_PRIV_BASE_LOW_AW_13 0x396718
+
+#define mmNIF_RTR_CTRL_1_RANGE_PRIV_BASE_LOW_AW_14 0x39671C
+
+#define mmNIF_RTR_CTRL_1_RANGE_PRIV_BASE_LOW_AW_15 0x396720
+
+#define mmNIF_RTR_CTRL_1_RANGE_PRIV_BASE_HIGH_AW_0 0x396724
+
+#define mmNIF_RTR_CTRL_1_RANGE_PRIV_BASE_HIGH_AW_1 0x396728
+
+#define mmNIF_RTR_CTRL_1_RANGE_PRIV_BASE_HIGH_AW_2 0x39672C
+
+#define mmNIF_RTR_CTRL_1_RANGE_PRIV_BASE_HIGH_AW_3 0x396730
+
+#define mmNIF_RTR_CTRL_1_RANGE_PRIV_BASE_HIGH_AW_4 0x396734
+
+#define mmNIF_RTR_CTRL_1_RANGE_PRIV_BASE_HIGH_AW_5 0x396738
+
+#define mmNIF_RTR_CTRL_1_RANGE_PRIV_BASE_HIGH_AW_6 0x39673C
+
+#define mmNIF_RTR_CTRL_1_RANGE_PRIV_BASE_HIGH_AW_7 0x396740
+
+#define mmNIF_RTR_CTRL_1_RANGE_PRIV_BASE_HIGH_AW_8 0x396744
+
+#define mmNIF_RTR_CTRL_1_RANGE_PRIV_BASE_HIGH_AW_9 0x396748
+
+#define mmNIF_RTR_CTRL_1_RANGE_PRIV_BASE_HIGH_AW_10 0x39674C
+
+#define mmNIF_RTR_CTRL_1_RANGE_PRIV_BASE_HIGH_AW_11 0x396750
+
+#define mmNIF_RTR_CTRL_1_RANGE_PRIV_BASE_HIGH_AW_12 0x396754
+
+#define mmNIF_RTR_CTRL_1_RANGE_PRIV_BASE_HIGH_AW_13 0x396758
+
+#define mmNIF_RTR_CTRL_1_RANGE_PRIV_BASE_HIGH_AW_14 0x39675C
+
+#define mmNIF_RTR_CTRL_1_RANGE_PRIV_BASE_HIGH_AW_15 0x396760
+
+#define mmNIF_RTR_CTRL_1_RANGE_PRIV_MASK_LOW_AW_0 0x396764
+
+#define mmNIF_RTR_CTRL_1_RANGE_PRIV_MASK_LOW_AW_1 0x396768
+
+#define mmNIF_RTR_CTRL_1_RANGE_PRIV_MASK_LOW_AW_2 0x39676C
+
+#define mmNIF_RTR_CTRL_1_RANGE_PRIV_MASK_LOW_AW_3 0x396770
+
+#define mmNIF_RTR_CTRL_1_RANGE_PRIV_MASK_LOW_AW_4 0x396774
+
+#define mmNIF_RTR_CTRL_1_RANGE_PRIV_MASK_LOW_AW_5 0x396778
+
+#define mmNIF_RTR_CTRL_1_RANGE_PRIV_MASK_LOW_AW_6 0x39677C
+
+#define mmNIF_RTR_CTRL_1_RANGE_PRIV_MASK_LOW_AW_7 0x396780
+
+#define mmNIF_RTR_CTRL_1_RANGE_PRIV_MASK_LOW_AW_8 0x396784
+
+#define mmNIF_RTR_CTRL_1_RANGE_PRIV_MASK_LOW_AW_9 0x396788
+
+#define mmNIF_RTR_CTRL_1_RANGE_PRIV_MASK_LOW_AW_10 0x39678C
+
+#define mmNIF_RTR_CTRL_1_RANGE_PRIV_MASK_LOW_AW_11 0x396790
+
+#define mmNIF_RTR_CTRL_1_RANGE_PRIV_MASK_LOW_AW_12 0x396794
+
+#define mmNIF_RTR_CTRL_1_RANGE_PRIV_MASK_LOW_AW_13 0x396798
+
+#define mmNIF_RTR_CTRL_1_RANGE_PRIV_MASK_LOW_AW_14 0x39679C
+
+#define mmNIF_RTR_CTRL_1_RANGE_PRIV_MASK_LOW_AW_15 0x3967A0
+
+#define mmNIF_RTR_CTRL_1_RANGE_PRIV_MASK_HIGH_AW_0 0x3967A4
+
+#define mmNIF_RTR_CTRL_1_RANGE_PRIV_MASK_HIGH_AW_1 0x3967A8
+
+#define mmNIF_RTR_CTRL_1_RANGE_PRIV_MASK_HIGH_AW_2 0x3967AC
+
+#define mmNIF_RTR_CTRL_1_RANGE_PRIV_MASK_HIGH_AW_3 0x3967B0
+
+#define mmNIF_RTR_CTRL_1_RANGE_PRIV_MASK_HIGH_AW_4 0x3967B4
+
+#define mmNIF_RTR_CTRL_1_RANGE_PRIV_MASK_HIGH_AW_5 0x3967B8
+
+#define mmNIF_RTR_CTRL_1_RANGE_PRIV_MASK_HIGH_AW_6 0x3967BC
+
+#define mmNIF_RTR_CTRL_1_RANGE_PRIV_MASK_HIGH_AW_7 0x3967C0
+
+#define mmNIF_RTR_CTRL_1_RANGE_PRIV_MASK_HIGH_AW_8 0x3967C4
+
+#define mmNIF_RTR_CTRL_1_RANGE_PRIV_MASK_HIGH_AW_9 0x3967C8
+
+#define mmNIF_RTR_CTRL_1_RANGE_PRIV_MASK_HIGH_AW_10 0x3967CC
+
+#define mmNIF_RTR_CTRL_1_RANGE_PRIV_MASK_HIGH_AW_11 0x3967D0
+
+#define mmNIF_RTR_CTRL_1_RANGE_PRIV_MASK_HIGH_AW_12 0x3967D4
+
+#define mmNIF_RTR_CTRL_1_RANGE_PRIV_MASK_HIGH_AW_13 0x3967D8
+
+#define mmNIF_RTR_CTRL_1_RANGE_PRIV_MASK_HIGH_AW_14 0x3967DC
+
+#define mmNIF_RTR_CTRL_1_RANGE_PRIV_MASK_HIGH_AW_15 0x3967E0
+
+#define mmNIF_RTR_CTRL_1_RANGE_SEC_BASE_LOW_AR_0 0x396824
+
+#define mmNIF_RTR_CTRL_1_RANGE_SEC_BASE_LOW_AR_1 0x396828
+
+#define mmNIF_RTR_CTRL_1_RANGE_SEC_BASE_LOW_AR_2 0x39682C
+
+#define mmNIF_RTR_CTRL_1_RANGE_SEC_BASE_LOW_AR_3 0x396830
+
+#define mmNIF_RTR_CTRL_1_RANGE_SEC_BASE_LOW_AR_4 0x396834
+
+#define mmNIF_RTR_CTRL_1_RANGE_SEC_BASE_LOW_AR_5 0x396838
+
+#define mmNIF_RTR_CTRL_1_RANGE_SEC_BASE_LOW_AR_6 0x39683C
+
+#define mmNIF_RTR_CTRL_1_RANGE_SEC_BASE_LOW_AR_7 0x396840
+
+#define mmNIF_RTR_CTRL_1_RANGE_SEC_BASE_LOW_AR_8 0x396844
+
+#define mmNIF_RTR_CTRL_1_RANGE_SEC_BASE_LOW_AR_9 0x396848
+
+#define mmNIF_RTR_CTRL_1_RANGE_SEC_BASE_LOW_AR_10 0x39684C
+
+#define mmNIF_RTR_CTRL_1_RANGE_SEC_BASE_LOW_AR_11 0x396850
+
+#define mmNIF_RTR_CTRL_1_RANGE_SEC_BASE_LOW_AR_12 0x396854
+
+#define mmNIF_RTR_CTRL_1_RANGE_SEC_BASE_LOW_AR_13 0x396858
+
+#define mmNIF_RTR_CTRL_1_RANGE_SEC_BASE_LOW_AR_14 0x39685C
+
+#define mmNIF_RTR_CTRL_1_RANGE_SEC_BASE_LOW_AR_15 0x396860
+
+#define mmNIF_RTR_CTRL_1_RANGE_SEC_BASE_HIGH_AR_0 0x396864
+
+#define mmNIF_RTR_CTRL_1_RANGE_SEC_BASE_HIGH_AR_1 0x396868
+
+#define mmNIF_RTR_CTRL_1_RANGE_SEC_BASE_HIGH_AR_2 0x39686C
+
+#define mmNIF_RTR_CTRL_1_RANGE_SEC_BASE_HIGH_AR_3 0x396870
+
+#define mmNIF_RTR_CTRL_1_RANGE_SEC_BASE_HIGH_AR_4 0x396874
+
+#define mmNIF_RTR_CTRL_1_RANGE_SEC_BASE_HIGH_AR_5 0x396878
+
+#define mmNIF_RTR_CTRL_1_RANGE_SEC_BASE_HIGH_AR_6 0x39687C
+
+#define mmNIF_RTR_CTRL_1_RANGE_SEC_BASE_HIGH_AR_7 0x396880
+
+#define mmNIF_RTR_CTRL_1_RANGE_SEC_BASE_HIGH_AR_8 0x396884
+
+#define mmNIF_RTR_CTRL_1_RANGE_SEC_BASE_HIGH_AR_9 0x396888
+
+#define mmNIF_RTR_CTRL_1_RANGE_SEC_BASE_HIGH_AR_10 0x39688C
+
+#define mmNIF_RTR_CTRL_1_RANGE_SEC_BASE_HIGH_AR_11 0x396890
+
+#define mmNIF_RTR_CTRL_1_RANGE_SEC_BASE_HIGH_AR_12 0x396894
+
+#define mmNIF_RTR_CTRL_1_RANGE_SEC_BASE_HIGH_AR_13 0x396898
+
+#define mmNIF_RTR_CTRL_1_RANGE_SEC_BASE_HIGH_AR_14 0x39689C
+
+#define mmNIF_RTR_CTRL_1_RANGE_SEC_BASE_HIGH_AR_15 0x3968A0
+
+#define mmNIF_RTR_CTRL_1_RANGE_SEC_MASK_LOW_AR_0 0x3968A4
+
+#define mmNIF_RTR_CTRL_1_RANGE_SEC_MASK_LOW_AR_1 0x3968A8
+
+#define mmNIF_RTR_CTRL_1_RANGE_SEC_MASK_LOW_AR_2 0x3968AC
+
+#define mmNIF_RTR_CTRL_1_RANGE_SEC_MASK_LOW_AR_3 0x3968B0
+
+#define mmNIF_RTR_CTRL_1_RANGE_SEC_MASK_LOW_AR_4 0x3968B4
+
+#define mmNIF_RTR_CTRL_1_RANGE_SEC_MASK_LOW_AR_5 0x3968B8
+
+#define mmNIF_RTR_CTRL_1_RANGE_SEC_MASK_LOW_AR_6 0x3968BC
+
+#define mmNIF_RTR_CTRL_1_RANGE_SEC_MASK_LOW_AR_7 0x3968C0
+
+#define mmNIF_RTR_CTRL_1_RANGE_SEC_MASK_LOW_AR_8 0x3968C4
+
+#define mmNIF_RTR_CTRL_1_RANGE_SEC_MASK_LOW_AR_9 0x3968C8
+
+#define mmNIF_RTR_CTRL_1_RANGE_SEC_MASK_LOW_AR_10 0x3968CC
+
+#define mmNIF_RTR_CTRL_1_RANGE_SEC_MASK_LOW_AR_11 0x3968D0
+
+#define mmNIF_RTR_CTRL_1_RANGE_SEC_MASK_LOW_AR_12 0x3968D4
+
+#define mmNIF_RTR_CTRL_1_RANGE_SEC_MASK_LOW_AR_13 0x3968D8
+
+#define mmNIF_RTR_CTRL_1_RANGE_SEC_MASK_LOW_AR_14 0x3968DC
+
+#define mmNIF_RTR_CTRL_1_RANGE_SEC_MASK_LOW_AR_15 0x3968E0
+
+#define mmNIF_RTR_CTRL_1_RANGE_SEC_MASK_HIGH_AR_0 0x3968E4
+
+#define mmNIF_RTR_CTRL_1_RANGE_SEC_MASK_HIGH_AR_1 0x3968E8
+
+#define mmNIF_RTR_CTRL_1_RANGE_SEC_MASK_HIGH_AR_2 0x3968EC
+
+#define mmNIF_RTR_CTRL_1_RANGE_SEC_MASK_HIGH_AR_3 0x3968F0
+
+#define mmNIF_RTR_CTRL_1_RANGE_SEC_MASK_HIGH_AR_4 0x3968F4
+
+#define mmNIF_RTR_CTRL_1_RANGE_SEC_MASK_HIGH_AR_5 0x3968F8
+
+#define mmNIF_RTR_CTRL_1_RANGE_SEC_MASK_HIGH_AR_6 0x3968FC
+
+#define mmNIF_RTR_CTRL_1_RANGE_SEC_MASK_HIGH_AR_7 0x396900
+
+#define mmNIF_RTR_CTRL_1_RANGE_SEC_MASK_HIGH_AR_8 0x396904
+
+#define mmNIF_RTR_CTRL_1_RANGE_SEC_MASK_HIGH_AR_9 0x396908
+
+#define mmNIF_RTR_CTRL_1_RANGE_SEC_MASK_HIGH_AR_10 0x39690C
+
+#define mmNIF_RTR_CTRL_1_RANGE_SEC_MASK_HIGH_AR_11 0x396910
+
+#define mmNIF_RTR_CTRL_1_RANGE_SEC_MASK_HIGH_AR_12 0x396914
+
+#define mmNIF_RTR_CTRL_1_RANGE_SEC_MASK_HIGH_AR_13 0x396918
+
+#define mmNIF_RTR_CTRL_1_RANGE_SEC_MASK_HIGH_AR_14 0x39691C
+
+#define mmNIF_RTR_CTRL_1_RANGE_SEC_MASK_HIGH_AR_15 0x396920
+
+#define mmNIF_RTR_CTRL_1_RANGE_PRIV_BASE_LOW_AR_0 0x396924
+
+#define mmNIF_RTR_CTRL_1_RANGE_PRIV_BASE_LOW_AR_1 0x396928
+
+#define mmNIF_RTR_CTRL_1_RANGE_PRIV_BASE_LOW_AR_2 0x39692C
+
+#define mmNIF_RTR_CTRL_1_RANGE_PRIV_BASE_LOW_AR_3 0x396930
+
+#define mmNIF_RTR_CTRL_1_RANGE_PRIV_BASE_LOW_AR_4 0x396934
+
+#define mmNIF_RTR_CTRL_1_RANGE_PRIV_BASE_LOW_AR_5 0x396938
+
+#define mmNIF_RTR_CTRL_1_RANGE_PRIV_BASE_LOW_AR_6 0x39693C
+
+#define mmNIF_RTR_CTRL_1_RANGE_PRIV_BASE_LOW_AR_7 0x396940
+
+#define mmNIF_RTR_CTRL_1_RANGE_PRIV_BASE_LOW_AR_8 0x396944
+
+#define mmNIF_RTR_CTRL_1_RANGE_PRIV_BASE_LOW_AR_9 0x396948
+
+#define mmNIF_RTR_CTRL_1_RANGE_PRIV_BASE_LOW_AR_10 0x39694C
+
+#define mmNIF_RTR_CTRL_1_RANGE_PRIV_BASE_LOW_AR_11 0x396950
+
+#define mmNIF_RTR_CTRL_1_RANGE_PRIV_BASE_LOW_AR_12 0x396954
+
+#define mmNIF_RTR_CTRL_1_RANGE_PRIV_BASE_LOW_AR_13 0x396958
+
+#define mmNIF_RTR_CTRL_1_RANGE_PRIV_BASE_LOW_AR_14 0x39695C
+
+#define mmNIF_RTR_CTRL_1_RANGE_PRIV_BASE_LOW_AR_15 0x396960
+
+#define mmNIF_RTR_CTRL_1_RANGE_PRIV_BASE_HIGH_AR_0 0x396964
+
+#define mmNIF_RTR_CTRL_1_RANGE_PRIV_BASE_HIGH_AR_1 0x396968
+
+#define mmNIF_RTR_CTRL_1_RANGE_PRIV_BASE_HIGH_AR_2 0x39696C
+
+#define mmNIF_RTR_CTRL_1_RANGE_PRIV_BASE_HIGH_AR_3 0x396970
+
+#define mmNIF_RTR_CTRL_1_RANGE_PRIV_BASE_HIGH_AR_4 0x396974
+
+#define mmNIF_RTR_CTRL_1_RANGE_PRIV_BASE_HIGH_AR_5 0x396978
+
+#define mmNIF_RTR_CTRL_1_RANGE_PRIV_BASE_HIGH_AR_6 0x39697C
+
+#define mmNIF_RTR_CTRL_1_RANGE_PRIV_BASE_HIGH_AR_7 0x396980
+
+#define mmNIF_RTR_CTRL_1_RANGE_PRIV_BASE_HIGH_AR_8 0x396984
+
+#define mmNIF_RTR_CTRL_1_RANGE_PRIV_BASE_HIGH_AR_9 0x396988
+
+#define mmNIF_RTR_CTRL_1_RANGE_PRIV_BASE_HIGH_AR_10 0x39698C
+
+#define mmNIF_RTR_CTRL_1_RANGE_PRIV_BASE_HIGH_AR_11 0x396990
+
+#define mmNIF_RTR_CTRL_1_RANGE_PRIV_BASE_HIGH_AR_12 0x396994
+
+#define mmNIF_RTR_CTRL_1_RANGE_PRIV_BASE_HIGH_AR_13 0x396998
+
+#define mmNIF_RTR_CTRL_1_RANGE_PRIV_BASE_HIGH_AR_14 0x39699C
+
+#define mmNIF_RTR_CTRL_1_RANGE_PRIV_BASE_HIGH_AR_15 0x3969A0
+
+#define mmNIF_RTR_CTRL_1_RANGE_PRIV_MASK_LOW_AR_0 0x3969A4
+
+#define mmNIF_RTR_CTRL_1_RANGE_PRIV_MASK_LOW_AR_1 0x3969A8
+
+#define mmNIF_RTR_CTRL_1_RANGE_PRIV_MASK_LOW_AR_2 0x3969AC
+
+#define mmNIF_RTR_CTRL_1_RANGE_PRIV_MASK_LOW_AR_3 0x3969B0
+
+#define mmNIF_RTR_CTRL_1_RANGE_PRIV_MASK_LOW_AR_4 0x3969B4
+
+#define mmNIF_RTR_CTRL_1_RANGE_PRIV_MASK_LOW_AR_5 0x3969B8
+
+#define mmNIF_RTR_CTRL_1_RANGE_PRIV_MASK_LOW_AR_6 0x3969BC
+
+#define mmNIF_RTR_CTRL_1_RANGE_PRIV_MASK_LOW_AR_7 0x3969C0
+
+#define mmNIF_RTR_CTRL_1_RANGE_PRIV_MASK_LOW_AR_8 0x3969C4
+
+#define mmNIF_RTR_CTRL_1_RANGE_PRIV_MASK_LOW_AR_9 0x3969C8
+
+#define mmNIF_RTR_CTRL_1_RANGE_PRIV_MASK_LOW_AR_10 0x3969CC
+
+#define mmNIF_RTR_CTRL_1_RANGE_PRIV_MASK_LOW_AR_11 0x3969D0
+
+#define mmNIF_RTR_CTRL_1_RANGE_PRIV_MASK_LOW_AR_12 0x3969D4
+
+#define mmNIF_RTR_CTRL_1_RANGE_PRIV_MASK_LOW_AR_13 0x3969D8
+
+#define mmNIF_RTR_CTRL_1_RANGE_PRIV_MASK_LOW_AR_14 0x3969DC
+
+#define mmNIF_RTR_CTRL_1_RANGE_PRIV_MASK_LOW_AR_15 0x3969E0
+
+#define mmNIF_RTR_CTRL_1_RANGE_PRIV_MASK_HIGH_AR_0 0x3969E4
+
+#define mmNIF_RTR_CTRL_1_RANGE_PRIV_MASK_HIGH_AR_1 0x3969E8
+
+#define mmNIF_RTR_CTRL_1_RANGE_PRIV_MASK_HIGH_AR_2 0x3969EC
+
+#define mmNIF_RTR_CTRL_1_RANGE_PRIV_MASK_HIGH_AR_3 0x3969F0
+
+#define mmNIF_RTR_CTRL_1_RANGE_PRIV_MASK_HIGH_AR_4 0x3969F4
+
+#define mmNIF_RTR_CTRL_1_RANGE_PRIV_MASK_HIGH_AR_5 0x3969F8
+
+#define mmNIF_RTR_CTRL_1_RANGE_PRIV_MASK_HIGH_AR_6 0x3969FC
+
+#define mmNIF_RTR_CTRL_1_RANGE_PRIV_MASK_HIGH_AR_7 0x396A00
+
+#define mmNIF_RTR_CTRL_1_RANGE_PRIV_MASK_HIGH_AR_8 0x396A04
+
+#define mmNIF_RTR_CTRL_1_RANGE_PRIV_MASK_HIGH_AR_9 0x396A08
+
+#define mmNIF_RTR_CTRL_1_RANGE_PRIV_MASK_HIGH_AR_10 0x396A0C
+
+#define mmNIF_RTR_CTRL_1_RANGE_PRIV_MASK_HIGH_AR_11 0x396A10
+
+#define mmNIF_RTR_CTRL_1_RANGE_PRIV_MASK_HIGH_AR_12 0x396A14
+
+#define mmNIF_RTR_CTRL_1_RANGE_PRIV_MASK_HIGH_AR_13 0x396A18
+
+#define mmNIF_RTR_CTRL_1_RANGE_PRIV_MASK_HIGH_AR_14 0x396A1C
+
+#define mmNIF_RTR_CTRL_1_RANGE_PRIV_MASK_HIGH_AR_15 0x396A20
+
+#define mmNIF_RTR_CTRL_1_RANGE_SEC_HIT_AW 0x396A64
+
+#define mmNIF_RTR_CTRL_1_RANGE_SEC_HIT_AR 0x396A68
+
+#define mmNIF_RTR_CTRL_1_RANGE_PRIV_HIT_AW 0x396A6C
+
+#define mmNIF_RTR_CTRL_1_RANGE_PRIV_HIT_AR 0x396A70
+
+#define mmNIF_RTR_CTRL_1_RGL_CFG 0x396B64
+
+#define mmNIF_RTR_CTRL_1_RGL_SHIFT 0x396B68
+
+#define mmNIF_RTR_CTRL_1_RGL_EXPECTED_LAT_0 0x396B6C
+
+#define mmNIF_RTR_CTRL_1_RGL_EXPECTED_LAT_1 0x396B70
+
+#define mmNIF_RTR_CTRL_1_RGL_EXPECTED_LAT_2 0x396B74
+
+#define mmNIF_RTR_CTRL_1_RGL_EXPECTED_LAT_3 0x396B78
+
+#define mmNIF_RTR_CTRL_1_RGL_EXPECTED_LAT_4 0x396B7C
+
+#define mmNIF_RTR_CTRL_1_RGL_EXPECTED_LAT_5 0x396B80
+
+#define mmNIF_RTR_CTRL_1_RGL_EXPECTED_LAT_6 0x396B84
+
+#define mmNIF_RTR_CTRL_1_RGL_EXPECTED_LAT_7 0x396B88
+
+#define mmNIF_RTR_CTRL_1_RGL_TOKEN_0 0x396BAC
+
+#define mmNIF_RTR_CTRL_1_RGL_TOKEN_1 0x396BB0
+
+#define mmNIF_RTR_CTRL_1_RGL_TOKEN_2 0x396BB4
+
+#define mmNIF_RTR_CTRL_1_RGL_TOKEN_3 0x396BB8
+
+#define mmNIF_RTR_CTRL_1_RGL_TOKEN_4 0x396BBC
+
+#define mmNIF_RTR_CTRL_1_RGL_TOKEN_5 0x396BC0
+
+#define mmNIF_RTR_CTRL_1_RGL_TOKEN_6 0x396BC4
+
+#define mmNIF_RTR_CTRL_1_RGL_TOKEN_7 0x396BC8
+
+#define mmNIF_RTR_CTRL_1_RGL_BANK_ID_0 0x396BEC
+
+#define mmNIF_RTR_CTRL_1_RGL_BANK_ID_1 0x396BF0
+
+#define mmNIF_RTR_CTRL_1_RGL_BANK_ID_2 0x396BF4
+
+#define mmNIF_RTR_CTRL_1_RGL_BANK_ID_3 0x396BF8
+
+#define mmNIF_RTR_CTRL_1_RGL_BANK_ID_4 0x396BFC
+
+#define mmNIF_RTR_CTRL_1_RGL_BANK_ID_5 0x396C00
+
+#define mmNIF_RTR_CTRL_1_RGL_BANK_ID_6 0x396C04
+
+#define mmNIF_RTR_CTRL_1_RGL_BANK_ID_7 0x396C08
+
+#define mmNIF_RTR_CTRL_1_RGL_WDT 0x396C2C
+
+#define mmNIF_RTR_CTRL_1_E2E_AR_HBM0_CH0_CTR_WRAP 0x396C30
+
+#define mmNIF_RTR_CTRL_1_E2E_AR_HBM0_CH1_CTR_WRAP 0x396C34
+
+#define mmNIF_RTR_CTRL_1_E2E_AR_HBM1_CH0_CTR_WRAP 0x396C38
+
+#define mmNIF_RTR_CTRL_1_E2E_AR_HBM1_CH1_CTR_WRAP 0x396C3C
+
+#define mmNIF_RTR_CTRL_1_E2E_AR_HBM2_CH0_CTR_WRAP 0x396C40
+
+#define mmNIF_RTR_CTRL_1_E2E_AR_HBM2_CH1_CTR_WRAP 0x396C44
+
+#define mmNIF_RTR_CTRL_1_E2E_AR_HBM3_CH0_CTR_WRAP 0x396C48
+
+#define mmNIF_RTR_CTRL_1_E2E_AR_HBM3_CH1_CTR_WRAP 0x396C4C
+
+#define mmNIF_RTR_CTRL_1_E2E_AR_HBM0_CH0_CTR_CNT 0x396C50
+
+#define mmNIF_RTR_CTRL_1_E2E_AR_HBM0_CH1_CTR_CNT 0x396C54
+
+#define mmNIF_RTR_CTRL_1_E2E_AR_HBM1_CH0_CTR_CNT 0x396C58
+
+#define mmNIF_RTR_CTRL_1_E2E_AR_HBM1_CH1_CTR_CNT 0x396C5C
+
+#define mmNIF_RTR_CTRL_1_E2E_AR_HBM2_CH0_CTR_CNT 0x396C60
+
+#define mmNIF_RTR_CTRL_1_E2E_AR_HBM2_CH1_CTR_CNT 0x396C64
+
+#define mmNIF_RTR_CTRL_1_E2E_AR_HBM3_CH0_CTR_CNT 0x396C68
+
+#define mmNIF_RTR_CTRL_1_E2E_AR_HBM3_CH1_CTR_CNT 0x396C6C
+
+#define mmNIF_RTR_CTRL_1_E2E_AW_HBM0_CH0_CTR_WRAP 0x396C70
+
+#define mmNIF_RTR_CTRL_1_E2E_AW_HBM0_CH1_CTR_WRAP 0x396C74
+
+#define mmNIF_RTR_CTRL_1_E2E_AW_HBM1_CH0_CTR_WRAP 0x396C78
+
+#define mmNIF_RTR_CTRL_1_E2E_AW_HBM1_CH1_CTR_WRAP 0x396C7C
+
+#define mmNIF_RTR_CTRL_1_E2E_AW_HBM2_CH0_CTR_WRAP 0x396C80
+
+#define mmNIF_RTR_CTRL_1_E2E_AW_HBM2_CH1_CTR_WRAP 0x396C84
+
+#define mmNIF_RTR_CTRL_1_E2E_AW_HBM3_CH0_CTR_WRAP 0x396C88
+
+#define mmNIF_RTR_CTRL_1_E2E_AW_HBM3_CH1_CTR_WRAP 0x396C8C
+
+#define mmNIF_RTR_CTRL_1_E2E_AW_HBM0_CH0_CTR_CNT 0x396C90
+
+#define mmNIF_RTR_CTRL_1_E2E_AW_HBM0_CH1_CTR_CNT 0x396C94
+
+#define mmNIF_RTR_CTRL_1_E2E_AW_HBM1_CH0_CTR_CNT 0x396C98
+
+#define mmNIF_RTR_CTRL_1_E2E_AW_HBM1_CH1_CTR_CNT 0x396C9C
+
+#define mmNIF_RTR_CTRL_1_E2E_AW_HBM2_CH0_CTR_CNT 0x396CA0
+
+#define mmNIF_RTR_CTRL_1_E2E_AW_HBM2_CH1_CTR_CNT 0x396CA4
+
+#define mmNIF_RTR_CTRL_1_E2E_AW_HBM3_CH0_CTR_CNT 0x396CA8
+
+#define mmNIF_RTR_CTRL_1_E2E_AW_HBM3_CH1_CTR_CNT 0x396CAC
+
+#define mmNIF_RTR_CTRL_1_NL_HBM_PC_SEL_0 0x396CB0
+
+#define mmNIF_RTR_CTRL_1_NL_HBM_PC_SEL_1 0x396CB4
+
+#define mmNIF_RTR_CTRL_1_NL_HBM_PC_SEL_2 0x396CB8
+
+#define mmNIF_RTR_CTRL_1_NL_HBM_PC_SEL_3 0x396CBC
+
+#endif /* ASIC_REG_NIF_RTR_CTRL_1_REGS_H_ */
diff --git a/drivers/accel/habanalabs/include/gaudi/asic_reg/nif_rtr_ctrl_2_regs.h b/drivers/accel/habanalabs/include/gaudi/asic_reg/nif_rtr_ctrl_2_regs.h
new file mode 100644
index 0000000000..9de8442f9b
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi/asic_reg/nif_rtr_ctrl_2_regs.h
@@ -0,0 +1,896 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2016-2018 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ ** DO NOT EDIT BELOW **
+ ************************************/
+
+#ifndef ASIC_REG_NIF_RTR_CTRL_2_REGS_H_
+#define ASIC_REG_NIF_RTR_CTRL_2_REGS_H_
+
+/*
+ *****************************************
+ * NIF_RTR_CTRL_2 (Prototype: RTR_CTRL)
+ *****************************************
+ */
+
+#define mmNIF_RTR_CTRL_2_PERM_SEL 0x3A6108
+
+#define mmNIF_RTR_CTRL_2_HBM_POLY_H3_0 0x3A6114
+
+#define mmNIF_RTR_CTRL_2_HBM_POLY_H3_1 0x3A6118
+
+#define mmNIF_RTR_CTRL_2_HBM_POLY_H3_2 0x3A611C
+
+#define mmNIF_RTR_CTRL_2_HBM_POLY_H3_3 0x3A6120
+
+#define mmNIF_RTR_CTRL_2_HBM_POLY_H3_4 0x3A6124
+
+#define mmNIF_RTR_CTRL_2_HBM_POLY_H3_5 0x3A6128
+
+#define mmNIF_RTR_CTRL_2_HBM_POLY_H3_6 0x3A612C
+
+#define mmNIF_RTR_CTRL_2_HBM_POLY_H3_7 0x3A6130
+
+#define mmNIF_RTR_CTRL_2_HBM_POLY_H3_8 0x3A6134
+
+#define mmNIF_RTR_CTRL_2_HBM_POLY_H3_9 0x3A6138
+
+#define mmNIF_RTR_CTRL_2_HBM_POLY_H3_10 0x3A613C
+
+#define mmNIF_RTR_CTRL_2_HBM_POLY_H3_11 0x3A6140
+
+#define mmNIF_RTR_CTRL_2_HBM_POLY_H3_12 0x3A6144
+
+#define mmNIF_RTR_CTRL_2_HBM_POLY_H3_13 0x3A6148
+
+#define mmNIF_RTR_CTRL_2_HBM_POLY_H3_14 0x3A614C
+
+#define mmNIF_RTR_CTRL_2_HBM_POLY_H3_15 0x3A6150
+
+#define mmNIF_RTR_CTRL_2_HBM_POLY_H3_16 0x3A6154
+
+#define mmNIF_RTR_CTRL_2_HBM_POLY_H3_17 0x3A6158
+
+#define mmNIF_RTR_CTRL_2_HBM_POLY_H3_18 0x3A615C
+
+#define mmNIF_RTR_CTRL_2_HBM_POLY_H3_19 0x3A6160
+
+#define mmNIF_RTR_CTRL_2_HBM_POLY_H3_20 0x3A6164
+
+#define mmNIF_RTR_CTRL_2_HBM_POLY_H3_21 0x3A6168
+
+#define mmNIF_RTR_CTRL_2_HBM_POLY_H3_22 0x3A616C
+
+#define mmNIF_RTR_CTRL_2_HBM_POLY_H3_23 0x3A6170
+
+#define mmNIF_RTR_CTRL_2_HBM_POLY_H3_24 0x3A6174
+
+#define mmNIF_RTR_CTRL_2_HBM_POLY_H3_25 0x3A6178
+
+#define mmNIF_RTR_CTRL_2_HBM_POLY_H3_26 0x3A617C
+
+#define mmNIF_RTR_CTRL_2_HBM_POLY_H3_27 0x3A6180
+
+#define mmNIF_RTR_CTRL_2_SRAM_POLY_H3_0 0x3A6184
+
+#define mmNIF_RTR_CTRL_2_SRAM_POLY_H3_1 0x3A6188
+
+#define mmNIF_RTR_CTRL_2_SRAM_POLY_H3_2 0x3A618C
+
+#define mmNIF_RTR_CTRL_2_SRAM_POLY_H3_3 0x3A6190
+
+#define mmNIF_RTR_CTRL_2_SRAM_POLY_H3_4 0x3A6194
+
+#define mmNIF_RTR_CTRL_2_SRAM_POLY_H3_5 0x3A6198
+
+#define mmNIF_RTR_CTRL_2_SRAM_POLY_H3_6 0x3A619C
+
+#define mmNIF_RTR_CTRL_2_SRAM_POLY_H3_7 0x3A61A0
+
+#define mmNIF_RTR_CTRL_2_SRAM_POLY_H3_8 0x3A61A4
+
+#define mmNIF_RTR_CTRL_2_SRAM_POLY_H3_9 0x3A61A8
+
+#define mmNIF_RTR_CTRL_2_SRAM_POLY_H3_10 0x3A61AC
+
+#define mmNIF_RTR_CTRL_2_SRAM_POLY_H3_11 0x3A61B0
+
+#define mmNIF_RTR_CTRL_2_SRAM_POLY_H3_12 0x3A61B4
+
+#define mmNIF_RTR_CTRL_2_SRAM_POLY_H3_13 0x3A61B8
+
+#define mmNIF_RTR_CTRL_2_SRAM_POLY_H3_14 0x3A61BC
+
+#define mmNIF_RTR_CTRL_2_SCRAM_SRAM_EN 0x3A626C
+
+#define mmNIF_RTR_CTRL_2_RL_HBM_EN 0x3A6274
+
+#define mmNIF_RTR_CTRL_2_RL_HBM_SAT 0x3A6278
+
+#define mmNIF_RTR_CTRL_2_RL_HBM_RST 0x3A627C
+
+#define mmNIF_RTR_CTRL_2_RL_HBM_TIMEOUT 0x3A6280
+
+#define mmNIF_RTR_CTRL_2_SCRAM_HBM_EN 0x3A6284
+
+#define mmNIF_RTR_CTRL_2_RL_PCI_EN 0x3A6288
+
+#define mmNIF_RTR_CTRL_2_RL_PCI_SAT 0x3A628C
+
+#define mmNIF_RTR_CTRL_2_RL_PCI_RST 0x3A6290
+
+#define mmNIF_RTR_CTRL_2_RL_PCI_TIMEOUT 0x3A6294
+
+#define mmNIF_RTR_CTRL_2_RL_SRAM_EN 0x3A629C
+
+#define mmNIF_RTR_CTRL_2_RL_SRAM_SAT 0x3A62A0
+
+#define mmNIF_RTR_CTRL_2_RL_SRAM_RST 0x3A62A4
+
+#define mmNIF_RTR_CTRL_2_RL_SRAM_TIMEOUT 0x3A62AC
+
+#define mmNIF_RTR_CTRL_2_RL_SRAM_RED 0x3A62B4
+
+#define mmNIF_RTR_CTRL_2_E2E_HBM_EN 0x3A62EC
+
+#define mmNIF_RTR_CTRL_2_E2E_PCI_EN 0x3A62F0
+
+#define mmNIF_RTR_CTRL_2_E2E_HBM_WR_SIZE 0x3A62F4
+
+#define mmNIF_RTR_CTRL_2_E2E_PCI_WR_SIZE 0x3A62F8
+
+#define mmNIF_RTR_CTRL_2_E2E_AW_PCI_CTR_SET_EN 0x3A6404
+
+#define mmNIF_RTR_CTRL_2_E2E_AW_PCI_CTR_SET 0x3A6408
+
+#define mmNIF_RTR_CTRL_2_E2E_AW_PCI_CTR_WRAP 0x3A640C
+
+#define mmNIF_RTR_CTRL_2_E2E_AW_PCI_CTR_CNT 0x3A6410
+
+#define mmNIF_RTR_CTRL_2_E2E_AW_HBM_CTR_SET_EN 0x3A6414
+
+#define mmNIF_RTR_CTRL_2_E2E_AW_HBM_CTR_SET 0x3A6418
+
+#define mmNIF_RTR_CTRL_2_E2E_HBM_RD_SIZE 0x3A641C
+
+#define mmNIF_RTR_CTRL_2_E2E_PCI_RD_SIZE 0x3A6420
+
+#define mmNIF_RTR_CTRL_2_E2E_AR_PCI_CTR_SET_EN 0x3A6424
+
+#define mmNIF_RTR_CTRL_2_E2E_AR_PCI_CTR_SET 0x3A6428
+
+#define mmNIF_RTR_CTRL_2_E2E_AR_PCI_CTR_WRAP 0x3A642C
+
+#define mmNIF_RTR_CTRL_2_E2E_AR_PCI_CTR_CNT 0x3A6430
+
+#define mmNIF_RTR_CTRL_2_E2E_AR_HBM_CTR_SET_EN 0x3A6434
+
+#define mmNIF_RTR_CTRL_2_E2E_AR_HBM_CTR_SET 0x3A6438
+
+#define mmNIF_RTR_CTRL_2_NL_HBM_SEL_0 0x3A6450
+
+#define mmNIF_RTR_CTRL_2_NL_HBM_SEL_1 0x3A6454
+
+#define mmNIF_RTR_CTRL_2_NON_LIN_EN 0x3A6480
+
+#define mmNIF_RTR_CTRL_2_NL_SRAM_BANK_0 0x3A6500
+
+#define mmNIF_RTR_CTRL_2_NL_SRAM_BANK_1 0x3A6504
+
+#define mmNIF_RTR_CTRL_2_NL_SRAM_BANK_2 0x3A6508
+
+#define mmNIF_RTR_CTRL_2_NL_SRAM_BANK_3 0x3A650C
+
+#define mmNIF_RTR_CTRL_2_NL_SRAM_BANK_4 0x3A6510
+
+#define mmNIF_RTR_CTRL_2_NL_SRAM_OFFSET_0 0x3A6514
+
+#define mmNIF_RTR_CTRL_2_NL_SRAM_OFFSET_1 0x3A6520
+
+#define mmNIF_RTR_CTRL_2_NL_SRAM_OFFSET_2 0x3A6524
+
+#define mmNIF_RTR_CTRL_2_NL_SRAM_OFFSET_3 0x3A6528
+
+#define mmNIF_RTR_CTRL_2_NL_SRAM_OFFSET_4 0x3A652C
+
+#define mmNIF_RTR_CTRL_2_NL_SRAM_OFFSET_5 0x3A6530
+
+#define mmNIF_RTR_CTRL_2_NL_SRAM_OFFSET_6 0x3A6534
+
+#define mmNIF_RTR_CTRL_2_NL_SRAM_OFFSET_7 0x3A6538
+
+#define mmNIF_RTR_CTRL_2_NL_SRAM_OFFSET_8 0x3A653C
+
+#define mmNIF_RTR_CTRL_2_NL_SRAM_OFFSET_9 0x3A6540
+
+#define mmNIF_RTR_CTRL_2_NL_HBM_OFFSET_0 0x3A6550
+
+#define mmNIF_RTR_CTRL_2_NL_HBM_OFFSET_1 0x3A6554
+
+#define mmNIF_RTR_CTRL_2_NL_HBM_OFFSET_2 0x3A6558
+
+#define mmNIF_RTR_CTRL_2_NL_HBM_OFFSET_3 0x3A655C
+
+#define mmNIF_RTR_CTRL_2_NL_HBM_OFFSET_4 0x3A6560
+
+#define mmNIF_RTR_CTRL_2_NL_HBM_OFFSET_5 0x3A6564
+
+#define mmNIF_RTR_CTRL_2_NL_HBM_OFFSET_6 0x3A6568
+
+#define mmNIF_RTR_CTRL_2_NL_HBM_OFFSET_7 0x3A656C
+
+#define mmNIF_RTR_CTRL_2_NL_HBM_OFFSET_8 0x3A6570
+
+#define mmNIF_RTR_CTRL_2_NL_HBM_OFFSET_9 0x3A6574
+
+#define mmNIF_RTR_CTRL_2_NL_HBM_OFFSET_10 0x3A6578
+
+#define mmNIF_RTR_CTRL_2_NL_HBM_OFFSET_11 0x3A657C
+
+#define mmNIF_RTR_CTRL_2_NL_HBM_OFFSET_12 0x3A6580
+
+#define mmNIF_RTR_CTRL_2_NL_HBM_OFFSET_13 0x3A6584
+
+#define mmNIF_RTR_CTRL_2_NL_HBM_OFFSET_14 0x3A6588
+
+#define mmNIF_RTR_CTRL_2_NL_HBM_OFFSET_15 0x3A658C
+
+#define mmNIF_RTR_CTRL_2_NL_HBM_OFFSET_16 0x3A6590
+
+#define mmNIF_RTR_CTRL_2_NL_HBM_OFFSET_17 0x3A6594
+
+#define mmNIF_RTR_CTRL_2_NL_HBM_OFFSET_18 0x3A6598
+
+#define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AW_0 0x3A65E4
+
+#define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AW_1 0x3A65E8
+
+#define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AW_2 0x3A65EC
+
+#define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AW_3 0x3A65F0
+
+#define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AW_4 0x3A65F4
+
+#define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AW_5 0x3A65F8
+
+#define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AW_6 0x3A65FC
+
+#define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AW_7 0x3A6600
+
+#define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AW_8 0x3A6604
+
+#define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AW_9 0x3A6608
+
+#define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AW_10 0x3A660C
+
+#define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AW_11 0x3A6610
+
+#define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AW_12 0x3A6614
+
+#define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AW_13 0x3A6618
+
+#define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AW_14 0x3A661C
+
+#define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AW_15 0x3A6620
+
+#define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AW_0 0x3A6624
+
+#define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AW_1 0x3A6628
+
+#define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AW_2 0x3A662C
+
+#define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AW_3 0x3A6630
+
+#define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AW_4 0x3A6634
+
+#define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AW_5 0x3A6638
+
+#define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AW_6 0x3A663C
+
+#define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AW_7 0x3A6640
+
+#define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AW_8 0x3A6644
+
+#define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AW_9 0x3A6648
+
+#define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AW_10 0x3A664C
+
+#define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AW_11 0x3A6650
+
+#define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AW_12 0x3A6654
+
+#define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AW_13 0x3A6658
+
+#define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AW_14 0x3A665C
+
+#define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AW_15 0x3A6660
+
+#define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AW_0 0x3A6664
+
+#define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AW_1 0x3A6668
+
+#define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AW_2 0x3A666C
+
+#define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AW_3 0x3A6670
+
+#define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AW_4 0x3A6674
+
+#define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AW_5 0x3A6678
+
+#define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AW_6 0x3A667C
+
+#define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AW_7 0x3A6680
+
+#define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AW_8 0x3A6684
+
+#define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AW_9 0x3A6688
+
+#define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AW_10 0x3A668C
+
+#define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AW_11 0x3A6690
+
+#define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AW_12 0x3A6694
+
+#define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AW_13 0x3A6698
+
+#define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AW_14 0x3A669C
+
+#define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AW_15 0x3A66A0
+
+#define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AW_0 0x3A66A4
+
+#define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AW_1 0x3A66A8
+
+#define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AW_2 0x3A66AC
+
+#define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AW_3 0x3A66B0
+
+#define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AW_4 0x3A66B4
+
+#define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AW_5 0x3A66B8
+
+#define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AW_6 0x3A66BC
+
+#define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AW_7 0x3A66C0
+
+#define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AW_8 0x3A66C4
+
+#define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AW_9 0x3A66C8
+
+#define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AW_10 0x3A66CC
+
+#define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AW_11 0x3A66D0
+
+#define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AW_12 0x3A66D4
+
+#define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AW_13 0x3A66D8
+
+#define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AW_14 0x3A66DC
+
+#define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AW_15 0x3A66E0
+
+#define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_LOW_AW_0 0x3A66E4
+
+#define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_LOW_AW_1 0x3A66E8
+
+#define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_LOW_AW_2 0x3A66EC
+
+#define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_LOW_AW_3 0x3A66F0
+
+#define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_LOW_AW_4 0x3A66F4
+
+#define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_LOW_AW_5 0x3A66F8
+
+#define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_LOW_AW_6 0x3A66FC
+
+#define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_LOW_AW_7 0x3A6700
+
+#define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_LOW_AW_8 0x3A6704
+
+#define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_LOW_AW_9 0x3A6708
+
+#define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_LOW_AW_10 0x3A670C
+
+#define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_LOW_AW_11 0x3A6710
+
+#define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_LOW_AW_12 0x3A6714
+
+#define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_LOW_AW_13 0x3A6718
+
+#define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_LOW_AW_14 0x3A671C
+
+#define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_LOW_AW_15 0x3A6720
+
+#define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_HIGH_AW_0 0x3A6724
+
+#define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_HIGH_AW_1 0x3A6728
+
+#define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_HIGH_AW_2 0x3A672C
+
+#define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_HIGH_AW_3 0x3A6730
+
+#define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_HIGH_AW_4 0x3A6734
+
+#define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_HIGH_AW_5 0x3A6738
+
+#define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_HIGH_AW_6 0x3A673C
+
+#define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_HIGH_AW_7 0x3A6740
+
+#define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_HIGH_AW_8 0x3A6744
+
+#define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_HIGH_AW_9 0x3A6748
+
+#define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_HIGH_AW_10 0x3A674C
+
+#define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_HIGH_AW_11 0x3A6750
+
+#define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_HIGH_AW_12 0x3A6754
+
+#define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_HIGH_AW_13 0x3A6758
+
+#define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_HIGH_AW_14 0x3A675C
+
+#define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_HIGH_AW_15 0x3A6760
+
+#define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_LOW_AW_0 0x3A6764
+
+#define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_LOW_AW_1 0x3A6768
+
+#define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_LOW_AW_2 0x3A676C
+
+#define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_LOW_AW_3 0x3A6770
+
+#define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_LOW_AW_4 0x3A6774
+
+#define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_LOW_AW_5 0x3A6778
+
+#define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_LOW_AW_6 0x3A677C
+
+#define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_LOW_AW_7 0x3A6780
+
+#define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_LOW_AW_8 0x3A6784
+
+#define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_LOW_AW_9 0x3A6788
+
+#define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_LOW_AW_10 0x3A678C
+
+#define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_LOW_AW_11 0x3A6790
+
+#define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_LOW_AW_12 0x3A6794
+
+#define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_LOW_AW_13 0x3A6798
+
+#define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_LOW_AW_14 0x3A679C
+
+#define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_LOW_AW_15 0x3A67A0
+
+#define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_HIGH_AW_0 0x3A67A4
+
+#define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_HIGH_AW_1 0x3A67A8
+
+#define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_HIGH_AW_2 0x3A67AC
+
+#define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_HIGH_AW_3 0x3A67B0
+
+#define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_HIGH_AW_4 0x3A67B4
+
+#define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_HIGH_AW_5 0x3A67B8
+
+#define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_HIGH_AW_6 0x3A67BC
+
+#define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_HIGH_AW_7 0x3A67C0
+
+#define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_HIGH_AW_8 0x3A67C4
+
+#define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_HIGH_AW_9 0x3A67C8
+
+#define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_HIGH_AW_10 0x3A67CC
+
+#define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_HIGH_AW_11 0x3A67D0
+
+#define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_HIGH_AW_12 0x3A67D4
+
+#define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_HIGH_AW_13 0x3A67D8
+
+#define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_HIGH_AW_14 0x3A67DC
+
+#define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_HIGH_AW_15 0x3A67E0
+
+#define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AR_0 0x3A6824
+
+#define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AR_1 0x3A6828
+
+#define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AR_2 0x3A682C
+
+#define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AR_3 0x3A6830
+
+#define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AR_4 0x3A6834
+
+#define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AR_5 0x3A6838
+
+#define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AR_6 0x3A683C
+
+#define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AR_7 0x3A6840
+
+#define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AR_8 0x3A6844
+
+#define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AR_9 0x3A6848
+
+#define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AR_10 0x3A684C
+
+#define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AR_11 0x3A6850
+
+#define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AR_12 0x3A6854
+
+#define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AR_13 0x3A6858
+
+#define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AR_14 0x3A685C
+
+#define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AR_15 0x3A6860
+
+#define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AR_0 0x3A6864
+
+#define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AR_1 0x3A6868
+
+#define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AR_2 0x3A686C
+
+#define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AR_3 0x3A6870
+
+#define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AR_4 0x3A6874
+
+#define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AR_5 0x3A6878
+
+#define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AR_6 0x3A687C
+
+#define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AR_7 0x3A6880
+
+#define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AR_8 0x3A6884
+
+#define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AR_9 0x3A6888
+
+#define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AR_10 0x3A688C
+
+#define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AR_11 0x3A6890
+
+#define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AR_12 0x3A6894
+
+#define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AR_13 0x3A6898
+
+#define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AR_14 0x3A689C
+
+#define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AR_15 0x3A68A0
+
+#define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AR_0 0x3A68A4
+
+#define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AR_1 0x3A68A8
+
+#define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AR_2 0x3A68AC
+
+#define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AR_3 0x3A68B0
+
+#define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AR_4 0x3A68B4
+
+#define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AR_5 0x3A68B8
+
+#define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AR_6 0x3A68BC
+
+#define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AR_7 0x3A68C0
+
+#define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AR_8 0x3A68C4
+
+#define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AR_9 0x3A68C8
+
+#define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AR_10 0x3A68CC
+
+#define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AR_11 0x3A68D0
+
+#define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AR_12 0x3A68D4
+
+#define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AR_13 0x3A68D8
+
+#define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AR_14 0x3A68DC
+
+#define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AR_15 0x3A68E0
+
+#define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AR_0 0x3A68E4
+
+#define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AR_1 0x3A68E8
+
+#define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AR_2 0x3A68EC
+
+#define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AR_3 0x3A68F0
+
+#define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AR_4 0x3A68F4
+
+#define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AR_5 0x3A68F8
+
+#define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AR_6 0x3A68FC
+
+#define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AR_7 0x3A6900
+
+#define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AR_8 0x3A6904
+
+#define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AR_9 0x3A6908
+
+#define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AR_10 0x3A690C
+
+#define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AR_11 0x3A6910
+
+#define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AR_12 0x3A6914
+
+#define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AR_13 0x3A6918
+
+#define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AR_14 0x3A691C
+
+#define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AR_15 0x3A6920
+
+#define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_LOW_AR_0 0x3A6924
+
+#define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_LOW_AR_1 0x3A6928
+
+#define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_LOW_AR_2 0x3A692C
+
+#define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_LOW_AR_3 0x3A6930
+
+#define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_LOW_AR_4 0x3A6934
+
+#define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_LOW_AR_5 0x3A6938
+
+#define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_LOW_AR_6 0x3A693C
+
+#define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_LOW_AR_7 0x3A6940
+
+#define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_LOW_AR_8 0x3A6944
+
+#define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_LOW_AR_9 0x3A6948
+
+#define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_LOW_AR_10 0x3A694C
+
+#define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_LOW_AR_11 0x3A6950
+
+#define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_LOW_AR_12 0x3A6954
+
+#define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_LOW_AR_13 0x3A6958
+
+#define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_LOW_AR_14 0x3A695C
+
+#define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_LOW_AR_15 0x3A6960
+
+#define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_HIGH_AR_0 0x3A6964
+
+#define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_HIGH_AR_1 0x3A6968
+
+#define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_HIGH_AR_2 0x3A696C
+
+#define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_HIGH_AR_3 0x3A6970
+
+#define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_HIGH_AR_4 0x3A6974
+
+#define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_HIGH_AR_5 0x3A6978
+
+#define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_HIGH_AR_6 0x3A697C
+
+#define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_HIGH_AR_7 0x3A6980
+
+#define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_HIGH_AR_8 0x3A6984
+
+#define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_HIGH_AR_9 0x3A6988
+
+#define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_HIGH_AR_10 0x3A698C
+
+#define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_HIGH_AR_11 0x3A6990
+
+#define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_HIGH_AR_12 0x3A6994
+
+#define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_HIGH_AR_13 0x3A6998
+
+#define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_HIGH_AR_14 0x3A699C
+
+#define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_HIGH_AR_15 0x3A69A0
+
+#define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_LOW_AR_0 0x3A69A4
+
+#define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_LOW_AR_1 0x3A69A8
+
+#define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_LOW_AR_2 0x3A69AC
+
+#define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_LOW_AR_3 0x3A69B0
+
+#define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_LOW_AR_4 0x3A69B4
+
+#define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_LOW_AR_5 0x3A69B8
+
+#define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_LOW_AR_6 0x3A69BC
+
+#define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_LOW_AR_7 0x3A69C0
+
+#define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_LOW_AR_8 0x3A69C4
+
+#define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_LOW_AR_9 0x3A69C8
+
+#define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_LOW_AR_10 0x3A69CC
+
+#define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_LOW_AR_11 0x3A69D0
+
+#define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_LOW_AR_12 0x3A69D4
+
+#define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_LOW_AR_13 0x3A69D8
+
+#define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_LOW_AR_14 0x3A69DC
+
+#define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_LOW_AR_15 0x3A69E0
+
+#define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_HIGH_AR_0 0x3A69E4
+
+#define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_HIGH_AR_1 0x3A69E8
+
+#define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_HIGH_AR_2 0x3A69EC
+
+#define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_HIGH_AR_3 0x3A69F0
+
+#define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_HIGH_AR_4 0x3A69F4
+
+#define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_HIGH_AR_5 0x3A69F8
+
+#define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_HIGH_AR_6 0x3A69FC
+
+#define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_HIGH_AR_7 0x3A6A00
+
+#define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_HIGH_AR_8 0x3A6A04
+
+#define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_HIGH_AR_9 0x3A6A08
+
+#define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_HIGH_AR_10 0x3A6A0C
+
+#define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_HIGH_AR_11 0x3A6A10
+
+#define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_HIGH_AR_12 0x3A6A14
+
+#define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_HIGH_AR_13 0x3A6A18
+
+#define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_HIGH_AR_14 0x3A6A1C
+
+#define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_HIGH_AR_15 0x3A6A20
+
+#define mmNIF_RTR_CTRL_2_RANGE_SEC_HIT_AW 0x3A6A64
+
+#define mmNIF_RTR_CTRL_2_RANGE_SEC_HIT_AR 0x3A6A68
+
+#define mmNIF_RTR_CTRL_2_RANGE_PRIV_HIT_AW 0x3A6A6C
+
+#define mmNIF_RTR_CTRL_2_RANGE_PRIV_HIT_AR 0x3A6A70
+
+#define mmNIF_RTR_CTRL_2_RGL_CFG 0x3A6B64
+
+#define mmNIF_RTR_CTRL_2_RGL_SHIFT 0x3A6B68
+
+#define mmNIF_RTR_CTRL_2_RGL_EXPECTED_LAT_0 0x3A6B6C
+
+#define mmNIF_RTR_CTRL_2_RGL_EXPECTED_LAT_1 0x3A6B70
+
+#define mmNIF_RTR_CTRL_2_RGL_EXPECTED_LAT_2 0x3A6B74
+
+#define mmNIF_RTR_CTRL_2_RGL_EXPECTED_LAT_3 0x3A6B78
+
+#define mmNIF_RTR_CTRL_2_RGL_EXPECTED_LAT_4 0x3A6B7C
+
+#define mmNIF_RTR_CTRL_2_RGL_EXPECTED_LAT_5 0x3A6B80
+
+#define mmNIF_RTR_CTRL_2_RGL_EXPECTED_LAT_6 0x3A6B84
+
+#define mmNIF_RTR_CTRL_2_RGL_EXPECTED_LAT_7 0x3A6B88
+
+#define mmNIF_RTR_CTRL_2_RGL_TOKEN_0 0x3A6BAC
+
+#define mmNIF_RTR_CTRL_2_RGL_TOKEN_1 0x3A6BB0
+
+#define mmNIF_RTR_CTRL_2_RGL_TOKEN_2 0x3A6BB4
+
+#define mmNIF_RTR_CTRL_2_RGL_TOKEN_3 0x3A6BB8
+
+#define mmNIF_RTR_CTRL_2_RGL_TOKEN_4 0x3A6BBC
+
+#define mmNIF_RTR_CTRL_2_RGL_TOKEN_5 0x3A6BC0
+
+#define mmNIF_RTR_CTRL_2_RGL_TOKEN_6 0x3A6BC4
+
+#define mmNIF_RTR_CTRL_2_RGL_TOKEN_7 0x3A6BC8
+
+#define mmNIF_RTR_CTRL_2_RGL_BANK_ID_0 0x3A6BEC
+
+#define mmNIF_RTR_CTRL_2_RGL_BANK_ID_1 0x3A6BF0
+
+#define mmNIF_RTR_CTRL_2_RGL_BANK_ID_2 0x3A6BF4
+
+#define mmNIF_RTR_CTRL_2_RGL_BANK_ID_3 0x3A6BF8
+
+#define mmNIF_RTR_CTRL_2_RGL_BANK_ID_4 0x3A6BFC
+
+#define mmNIF_RTR_CTRL_2_RGL_BANK_ID_5 0x3A6C00
+
+#define mmNIF_RTR_CTRL_2_RGL_BANK_ID_6 0x3A6C04
+
+#define mmNIF_RTR_CTRL_2_RGL_BANK_ID_7 0x3A6C08
+
+#define mmNIF_RTR_CTRL_2_RGL_WDT 0x3A6C2C
+
+#define mmNIF_RTR_CTRL_2_E2E_AR_HBM0_CH0_CTR_WRAP 0x3A6C30
+
+#define mmNIF_RTR_CTRL_2_E2E_AR_HBM0_CH1_CTR_WRAP 0x3A6C34
+
+#define mmNIF_RTR_CTRL_2_E2E_AR_HBM1_CH0_CTR_WRAP 0x3A6C38
+
+#define mmNIF_RTR_CTRL_2_E2E_AR_HBM1_CH1_CTR_WRAP 0x3A6C3C
+
+#define mmNIF_RTR_CTRL_2_E2E_AR_HBM2_CH0_CTR_WRAP 0x3A6C40
+
+#define mmNIF_RTR_CTRL_2_E2E_AR_HBM2_CH1_CTR_WRAP 0x3A6C44
+
+#define mmNIF_RTR_CTRL_2_E2E_AR_HBM3_CH0_CTR_WRAP 0x3A6C48
+
+#define mmNIF_RTR_CTRL_2_E2E_AR_HBM3_CH1_CTR_WRAP 0x3A6C4C
+
+#define mmNIF_RTR_CTRL_2_E2E_AR_HBM0_CH0_CTR_CNT 0x3A6C50
+
+#define mmNIF_RTR_CTRL_2_E2E_AR_HBM0_CH1_CTR_CNT 0x3A6C54
+
+#define mmNIF_RTR_CTRL_2_E2E_AR_HBM1_CH0_CTR_CNT 0x3A6C58
+
+#define mmNIF_RTR_CTRL_2_E2E_AR_HBM1_CH1_CTR_CNT 0x3A6C5C
+
+#define mmNIF_RTR_CTRL_2_E2E_AR_HBM2_CH0_CTR_CNT 0x3A6C60
+
+#define mmNIF_RTR_CTRL_2_E2E_AR_HBM2_CH1_CTR_CNT 0x3A6C64
+
+#define mmNIF_RTR_CTRL_2_E2E_AR_HBM3_CH0_CTR_CNT 0x3A6C68
+
+#define mmNIF_RTR_CTRL_2_E2E_AR_HBM3_CH1_CTR_CNT 0x3A6C6C
+
+#define mmNIF_RTR_CTRL_2_E2E_AW_HBM0_CH0_CTR_WRAP 0x3A6C70
+
+#define mmNIF_RTR_CTRL_2_E2E_AW_HBM0_CH1_CTR_WRAP 0x3A6C74
+
+#define mmNIF_RTR_CTRL_2_E2E_AW_HBM1_CH0_CTR_WRAP 0x3A6C78
+
+#define mmNIF_RTR_CTRL_2_E2E_AW_HBM1_CH1_CTR_WRAP 0x3A6C7C
+
+#define mmNIF_RTR_CTRL_2_E2E_AW_HBM2_CH0_CTR_WRAP 0x3A6C80
+
+#define mmNIF_RTR_CTRL_2_E2E_AW_HBM2_CH1_CTR_WRAP 0x3A6C84
+
+#define mmNIF_RTR_CTRL_2_E2E_AW_HBM3_CH0_CTR_WRAP 0x3A6C88
+
+#define mmNIF_RTR_CTRL_2_E2E_AW_HBM3_CH1_CTR_WRAP 0x3A6C8C
+
+#define mmNIF_RTR_CTRL_2_E2E_AW_HBM0_CH0_CTR_CNT 0x3A6C90
+
+#define mmNIF_RTR_CTRL_2_E2E_AW_HBM0_CH1_CTR_CNT 0x3A6C94
+
+#define mmNIF_RTR_CTRL_2_E2E_AW_HBM1_CH0_CTR_CNT 0x3A6C98
+
+#define mmNIF_RTR_CTRL_2_E2E_AW_HBM1_CH1_CTR_CNT 0x3A6C9C
+
+#define mmNIF_RTR_CTRL_2_E2E_AW_HBM2_CH0_CTR_CNT 0x3A6CA0
+
+#define mmNIF_RTR_CTRL_2_E2E_AW_HBM2_CH1_CTR_CNT 0x3A6CA4
+
+#define mmNIF_RTR_CTRL_2_E2E_AW_HBM3_CH0_CTR_CNT 0x3A6CA8
+
+#define mmNIF_RTR_CTRL_2_E2E_AW_HBM3_CH1_CTR_CNT 0x3A6CAC
+
+#define mmNIF_RTR_CTRL_2_NL_HBM_PC_SEL_0 0x3A6CB0
+
+#define mmNIF_RTR_CTRL_2_NL_HBM_PC_SEL_1 0x3A6CB4
+
+#define mmNIF_RTR_CTRL_2_NL_HBM_PC_SEL_2 0x3A6CB8
+
+#define mmNIF_RTR_CTRL_2_NL_HBM_PC_SEL_3 0x3A6CBC
+
+#endif /* ASIC_REG_NIF_RTR_CTRL_2_REGS_H_ */
diff --git a/drivers/accel/habanalabs/include/gaudi/asic_reg/nif_rtr_ctrl_3_regs.h b/drivers/accel/habanalabs/include/gaudi/asic_reg/nif_rtr_ctrl_3_regs.h
new file mode 100644
index 0000000000..34fd47685e
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi/asic_reg/nif_rtr_ctrl_3_regs.h
@@ -0,0 +1,896 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2016-2018 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ ** DO NOT EDIT BELOW **
+ ************************************/
+
+#ifndef ASIC_REG_NIF_RTR_CTRL_3_REGS_H_
+#define ASIC_REG_NIF_RTR_CTRL_3_REGS_H_
+
+/*
+ *****************************************
+ * NIF_RTR_CTRL_3 (Prototype: RTR_CTRL)
+ *****************************************
+ */
+
+#define mmNIF_RTR_CTRL_3_PERM_SEL 0x3B6108
+
+#define mmNIF_RTR_CTRL_3_HBM_POLY_H3_0 0x3B6114
+
+#define mmNIF_RTR_CTRL_3_HBM_POLY_H3_1 0x3B6118
+
+#define mmNIF_RTR_CTRL_3_HBM_POLY_H3_2 0x3B611C
+
+#define mmNIF_RTR_CTRL_3_HBM_POLY_H3_3 0x3B6120
+
+#define mmNIF_RTR_CTRL_3_HBM_POLY_H3_4 0x3B6124
+
+#define mmNIF_RTR_CTRL_3_HBM_POLY_H3_5 0x3B6128
+
+#define mmNIF_RTR_CTRL_3_HBM_POLY_H3_6 0x3B612C
+
+#define mmNIF_RTR_CTRL_3_HBM_POLY_H3_7 0x3B6130
+
+#define mmNIF_RTR_CTRL_3_HBM_POLY_H3_8 0x3B6134
+
+#define mmNIF_RTR_CTRL_3_HBM_POLY_H3_9 0x3B6138
+
+#define mmNIF_RTR_CTRL_3_HBM_POLY_H3_10 0x3B613C
+
+#define mmNIF_RTR_CTRL_3_HBM_POLY_H3_11 0x3B6140
+
+#define mmNIF_RTR_CTRL_3_HBM_POLY_H3_12 0x3B6144
+
+#define mmNIF_RTR_CTRL_3_HBM_POLY_H3_13 0x3B6148
+
+#define mmNIF_RTR_CTRL_3_HBM_POLY_H3_14 0x3B614C
+
+#define mmNIF_RTR_CTRL_3_HBM_POLY_H3_15 0x3B6150
+
+#define mmNIF_RTR_CTRL_3_HBM_POLY_H3_16 0x3B6154
+
+#define mmNIF_RTR_CTRL_3_HBM_POLY_H3_17 0x3B6158
+
+#define mmNIF_RTR_CTRL_3_HBM_POLY_H3_18 0x3B615C
+
+#define mmNIF_RTR_CTRL_3_HBM_POLY_H3_19 0x3B6160
+
+#define mmNIF_RTR_CTRL_3_HBM_POLY_H3_20 0x3B6164
+
+#define mmNIF_RTR_CTRL_3_HBM_POLY_H3_21 0x3B6168
+
+#define mmNIF_RTR_CTRL_3_HBM_POLY_H3_22 0x3B616C
+
+#define mmNIF_RTR_CTRL_3_HBM_POLY_H3_23 0x3B6170
+
+#define mmNIF_RTR_CTRL_3_HBM_POLY_H3_24 0x3B6174
+
+#define mmNIF_RTR_CTRL_3_HBM_POLY_H3_25 0x3B6178
+
+#define mmNIF_RTR_CTRL_3_HBM_POLY_H3_26 0x3B617C
+
+#define mmNIF_RTR_CTRL_3_HBM_POLY_H3_27 0x3B6180
+
+#define mmNIF_RTR_CTRL_3_SRAM_POLY_H3_0 0x3B6184
+
+#define mmNIF_RTR_CTRL_3_SRAM_POLY_H3_1 0x3B6188
+
+#define mmNIF_RTR_CTRL_3_SRAM_POLY_H3_2 0x3B618C
+
+#define mmNIF_RTR_CTRL_3_SRAM_POLY_H3_3 0x3B6190
+
+#define mmNIF_RTR_CTRL_3_SRAM_POLY_H3_4 0x3B6194
+
+#define mmNIF_RTR_CTRL_3_SRAM_POLY_H3_5 0x3B6198
+
+#define mmNIF_RTR_CTRL_3_SRAM_POLY_H3_6 0x3B619C
+
+#define mmNIF_RTR_CTRL_3_SRAM_POLY_H3_7 0x3B61A0
+
+#define mmNIF_RTR_CTRL_3_SRAM_POLY_H3_8 0x3B61A4
+
+#define mmNIF_RTR_CTRL_3_SRAM_POLY_H3_9 0x3B61A8
+
+#define mmNIF_RTR_CTRL_3_SRAM_POLY_H3_10 0x3B61AC
+
+#define mmNIF_RTR_CTRL_3_SRAM_POLY_H3_11 0x3B61B0
+
+#define mmNIF_RTR_CTRL_3_SRAM_POLY_H3_12 0x3B61B4
+
+#define mmNIF_RTR_CTRL_3_SRAM_POLY_H3_13 0x3B61B8
+
+#define mmNIF_RTR_CTRL_3_SRAM_POLY_H3_14 0x3B61BC
+
+#define mmNIF_RTR_CTRL_3_SCRAM_SRAM_EN 0x3B626C
+
+#define mmNIF_RTR_CTRL_3_RL_HBM_EN 0x3B6274
+
+#define mmNIF_RTR_CTRL_3_RL_HBM_SAT 0x3B6278
+
+#define mmNIF_RTR_CTRL_3_RL_HBM_RST 0x3B627C
+
+#define mmNIF_RTR_CTRL_3_RL_HBM_TIMEOUT 0x3B6280
+
+#define mmNIF_RTR_CTRL_3_SCRAM_HBM_EN 0x3B6284
+
+#define mmNIF_RTR_CTRL_3_RL_PCI_EN 0x3B6288
+
+#define mmNIF_RTR_CTRL_3_RL_PCI_SAT 0x3B628C
+
+#define mmNIF_RTR_CTRL_3_RL_PCI_RST 0x3B6290
+
+#define mmNIF_RTR_CTRL_3_RL_PCI_TIMEOUT 0x3B6294
+
+#define mmNIF_RTR_CTRL_3_RL_SRAM_EN 0x3B629C
+
+#define mmNIF_RTR_CTRL_3_RL_SRAM_SAT 0x3B62A0
+
+#define mmNIF_RTR_CTRL_3_RL_SRAM_RST 0x3B62A4
+
+#define mmNIF_RTR_CTRL_3_RL_SRAM_TIMEOUT 0x3B62AC
+
+#define mmNIF_RTR_CTRL_3_RL_SRAM_RED 0x3B62B4
+
+#define mmNIF_RTR_CTRL_3_E2E_HBM_EN 0x3B62EC
+
+#define mmNIF_RTR_CTRL_3_E2E_PCI_EN 0x3B62F0
+
+#define mmNIF_RTR_CTRL_3_E2E_HBM_WR_SIZE 0x3B62F4
+
+#define mmNIF_RTR_CTRL_3_E2E_PCI_WR_SIZE 0x3B62F8
+
+#define mmNIF_RTR_CTRL_3_E2E_AW_PCI_CTR_SET_EN 0x3B6404
+
+#define mmNIF_RTR_CTRL_3_E2E_AW_PCI_CTR_SET 0x3B6408
+
+#define mmNIF_RTR_CTRL_3_E2E_AW_PCI_CTR_WRAP 0x3B640C
+
+#define mmNIF_RTR_CTRL_3_E2E_AW_PCI_CTR_CNT 0x3B6410
+
+#define mmNIF_RTR_CTRL_3_E2E_AW_HBM_CTR_SET_EN 0x3B6414
+
+#define mmNIF_RTR_CTRL_3_E2E_AW_HBM_CTR_SET 0x3B6418
+
+#define mmNIF_RTR_CTRL_3_E2E_HBM_RD_SIZE 0x3B641C
+
+#define mmNIF_RTR_CTRL_3_E2E_PCI_RD_SIZE 0x3B6420
+
+#define mmNIF_RTR_CTRL_3_E2E_AR_PCI_CTR_SET_EN 0x3B6424
+
+#define mmNIF_RTR_CTRL_3_E2E_AR_PCI_CTR_SET 0x3B6428
+
+#define mmNIF_RTR_CTRL_3_E2E_AR_PCI_CTR_WRAP 0x3B642C
+
+#define mmNIF_RTR_CTRL_3_E2E_AR_PCI_CTR_CNT 0x3B6430
+
+#define mmNIF_RTR_CTRL_3_E2E_AR_HBM_CTR_SET_EN 0x3B6434
+
+#define mmNIF_RTR_CTRL_3_E2E_AR_HBM_CTR_SET 0x3B6438
+
+#define mmNIF_RTR_CTRL_3_NL_HBM_SEL_0 0x3B6450
+
+#define mmNIF_RTR_CTRL_3_NL_HBM_SEL_1 0x3B6454
+
+#define mmNIF_RTR_CTRL_3_NON_LIN_EN 0x3B6480
+
+#define mmNIF_RTR_CTRL_3_NL_SRAM_BANK_0 0x3B6500
+
+#define mmNIF_RTR_CTRL_3_NL_SRAM_BANK_1 0x3B6504
+
+#define mmNIF_RTR_CTRL_3_NL_SRAM_BANK_2 0x3B6508
+
+#define mmNIF_RTR_CTRL_3_NL_SRAM_BANK_3 0x3B650C
+
+#define mmNIF_RTR_CTRL_3_NL_SRAM_BANK_4 0x3B6510
+
+#define mmNIF_RTR_CTRL_3_NL_SRAM_OFFSET_0 0x3B6514
+
+#define mmNIF_RTR_CTRL_3_NL_SRAM_OFFSET_1 0x3B6520
+
+#define mmNIF_RTR_CTRL_3_NL_SRAM_OFFSET_2 0x3B6524
+
+#define mmNIF_RTR_CTRL_3_NL_SRAM_OFFSET_3 0x3B6528
+
+#define mmNIF_RTR_CTRL_3_NL_SRAM_OFFSET_4 0x3B652C
+
+#define mmNIF_RTR_CTRL_3_NL_SRAM_OFFSET_5 0x3B6530
+
+#define mmNIF_RTR_CTRL_3_NL_SRAM_OFFSET_6 0x3B6534
+
+#define mmNIF_RTR_CTRL_3_NL_SRAM_OFFSET_7 0x3B6538
+
+#define mmNIF_RTR_CTRL_3_NL_SRAM_OFFSET_8 0x3B653C
+
+#define mmNIF_RTR_CTRL_3_NL_SRAM_OFFSET_9 0x3B6540
+
+#define mmNIF_RTR_CTRL_3_NL_HBM_OFFSET_0 0x3B6550
+
+#define mmNIF_RTR_CTRL_3_NL_HBM_OFFSET_1 0x3B6554
+
+#define mmNIF_RTR_CTRL_3_NL_HBM_OFFSET_2 0x3B6558
+
+#define mmNIF_RTR_CTRL_3_NL_HBM_OFFSET_3 0x3B655C
+
+#define mmNIF_RTR_CTRL_3_NL_HBM_OFFSET_4 0x3B6560
+
+#define mmNIF_RTR_CTRL_3_NL_HBM_OFFSET_5 0x3B6564
+
+#define mmNIF_RTR_CTRL_3_NL_HBM_OFFSET_6 0x3B6568
+
+#define mmNIF_RTR_CTRL_3_NL_HBM_OFFSET_7 0x3B656C
+
+#define mmNIF_RTR_CTRL_3_NL_HBM_OFFSET_8 0x3B6570
+
+#define mmNIF_RTR_CTRL_3_NL_HBM_OFFSET_9 0x3B6574
+
+#define mmNIF_RTR_CTRL_3_NL_HBM_OFFSET_10 0x3B6578
+
+#define mmNIF_RTR_CTRL_3_NL_HBM_OFFSET_11 0x3B657C
+
+#define mmNIF_RTR_CTRL_3_NL_HBM_OFFSET_12 0x3B6580
+
+#define mmNIF_RTR_CTRL_3_NL_HBM_OFFSET_13 0x3B6584
+
+#define mmNIF_RTR_CTRL_3_NL_HBM_OFFSET_14 0x3B6588
+
+#define mmNIF_RTR_CTRL_3_NL_HBM_OFFSET_15 0x3B658C
+
+#define mmNIF_RTR_CTRL_3_NL_HBM_OFFSET_16 0x3B6590
+
+#define mmNIF_RTR_CTRL_3_NL_HBM_OFFSET_17 0x3B6594
+
+#define mmNIF_RTR_CTRL_3_NL_HBM_OFFSET_18 0x3B6598
+
+#define mmNIF_RTR_CTRL_3_RANGE_SEC_BASE_LOW_AW_0 0x3B65E4
+
+#define mmNIF_RTR_CTRL_3_RANGE_SEC_BASE_LOW_AW_1 0x3B65E8
+
+#define mmNIF_RTR_CTRL_3_RANGE_SEC_BASE_LOW_AW_2 0x3B65EC
+
+#define mmNIF_RTR_CTRL_3_RANGE_SEC_BASE_LOW_AW_3 0x3B65F0
+
+#define mmNIF_RTR_CTRL_3_RANGE_SEC_BASE_LOW_AW_4 0x3B65F4
+
+#define mmNIF_RTR_CTRL_3_RANGE_SEC_BASE_LOW_AW_5 0x3B65F8
+
+#define mmNIF_RTR_CTRL_3_RANGE_SEC_BASE_LOW_AW_6 0x3B65FC
+
+#define mmNIF_RTR_CTRL_3_RANGE_SEC_BASE_LOW_AW_7 0x3B6600
+
+#define mmNIF_RTR_CTRL_3_RANGE_SEC_BASE_LOW_AW_8 0x3B6604
+
+#define mmNIF_RTR_CTRL_3_RANGE_SEC_BASE_LOW_AW_9 0x3B6608
+
+#define mmNIF_RTR_CTRL_3_RANGE_SEC_BASE_LOW_AW_10 0x3B660C
+
+#define mmNIF_RTR_CTRL_3_RANGE_SEC_BASE_LOW_AW_11 0x3B6610
+
+#define mmNIF_RTR_CTRL_3_RANGE_SEC_BASE_LOW_AW_12 0x3B6614
+
+#define mmNIF_RTR_CTRL_3_RANGE_SEC_BASE_LOW_AW_13 0x3B6618
+
+#define mmNIF_RTR_CTRL_3_RANGE_SEC_BASE_LOW_AW_14 0x3B661C
+
+#define mmNIF_RTR_CTRL_3_RANGE_SEC_BASE_LOW_AW_15 0x3B6620
+
+#define mmNIF_RTR_CTRL_3_RANGE_SEC_BASE_HIGH_AW_0 0x3B6624
+
+#define mmNIF_RTR_CTRL_3_RANGE_SEC_BASE_HIGH_AW_1 0x3B6628
+
+#define mmNIF_RTR_CTRL_3_RANGE_SEC_BASE_HIGH_AW_2 0x3B662C
+
+#define mmNIF_RTR_CTRL_3_RANGE_SEC_BASE_HIGH_AW_3 0x3B6630
+
+#define mmNIF_RTR_CTRL_3_RANGE_SEC_BASE_HIGH_AW_4 0x3B6634
+
+#define mmNIF_RTR_CTRL_3_RANGE_SEC_BASE_HIGH_AW_5 0x3B6638
+
+#define mmNIF_RTR_CTRL_3_RANGE_SEC_BASE_HIGH_AW_6 0x3B663C
+
+#define mmNIF_RTR_CTRL_3_RANGE_SEC_BASE_HIGH_AW_7 0x3B6640
+
+#define mmNIF_RTR_CTRL_3_RANGE_SEC_BASE_HIGH_AW_8 0x3B6644
+
+#define mmNIF_RTR_CTRL_3_RANGE_SEC_BASE_HIGH_AW_9 0x3B6648
+
+#define mmNIF_RTR_CTRL_3_RANGE_SEC_BASE_HIGH_AW_10 0x3B664C
+
+#define mmNIF_RTR_CTRL_3_RANGE_SEC_BASE_HIGH_AW_11 0x3B6650
+
+#define mmNIF_RTR_CTRL_3_RANGE_SEC_BASE_HIGH_AW_12 0x3B6654
+
+#define mmNIF_RTR_CTRL_3_RANGE_SEC_BASE_HIGH_AW_13 0x3B6658
+
+#define mmNIF_RTR_CTRL_3_RANGE_SEC_BASE_HIGH_AW_14 0x3B665C
+
+#define mmNIF_RTR_CTRL_3_RANGE_SEC_BASE_HIGH_AW_15 0x3B6660
+
+#define mmNIF_RTR_CTRL_3_RANGE_SEC_MASK_LOW_AW_0 0x3B6664
+
+#define mmNIF_RTR_CTRL_3_RANGE_SEC_MASK_LOW_AW_1 0x3B6668
+
+#define mmNIF_RTR_CTRL_3_RANGE_SEC_MASK_LOW_AW_2 0x3B666C
+
+#define mmNIF_RTR_CTRL_3_RANGE_SEC_MASK_LOW_AW_3 0x3B6670
+
+#define mmNIF_RTR_CTRL_3_RANGE_SEC_MASK_LOW_AW_4 0x3B6674
+
+#define mmNIF_RTR_CTRL_3_RANGE_SEC_MASK_LOW_AW_5 0x3B6678
+
+#define mmNIF_RTR_CTRL_3_RANGE_SEC_MASK_LOW_AW_6 0x3B667C
+
+#define mmNIF_RTR_CTRL_3_RANGE_SEC_MASK_LOW_AW_7 0x3B6680
+
+#define mmNIF_RTR_CTRL_3_RANGE_SEC_MASK_LOW_AW_8 0x3B6684
+
+#define mmNIF_RTR_CTRL_3_RANGE_SEC_MASK_LOW_AW_9 0x3B6688
+
+#define mmNIF_RTR_CTRL_3_RANGE_SEC_MASK_LOW_AW_10 0x3B668C
+
+#define mmNIF_RTR_CTRL_3_RANGE_SEC_MASK_LOW_AW_11 0x3B6690
+
+#define mmNIF_RTR_CTRL_3_RANGE_SEC_MASK_LOW_AW_12 0x3B6694
+
+#define mmNIF_RTR_CTRL_3_RANGE_SEC_MASK_LOW_AW_13 0x3B6698
+
+#define mmNIF_RTR_CTRL_3_RANGE_SEC_MASK_LOW_AW_14 0x3B669C
+
+#define mmNIF_RTR_CTRL_3_RANGE_SEC_MASK_LOW_AW_15 0x3B66A0
+
+#define mmNIF_RTR_CTRL_3_RANGE_SEC_MASK_HIGH_AW_0 0x3B66A4
+
+#define mmNIF_RTR_CTRL_3_RANGE_SEC_MASK_HIGH_AW_1 0x3B66A8
+
+#define mmNIF_RTR_CTRL_3_RANGE_SEC_MASK_HIGH_AW_2 0x3B66AC
+
+#define mmNIF_RTR_CTRL_3_RANGE_SEC_MASK_HIGH_AW_3 0x3B66B0
+
+#define mmNIF_RTR_CTRL_3_RANGE_SEC_MASK_HIGH_AW_4 0x3B66B4
+
+#define mmNIF_RTR_CTRL_3_RANGE_SEC_MASK_HIGH_AW_5 0x3B66B8
+
+#define mmNIF_RTR_CTRL_3_RANGE_SEC_MASK_HIGH_AW_6 0x3B66BC
+
+#define mmNIF_RTR_CTRL_3_RANGE_SEC_MASK_HIGH_AW_7 0x3B66C0
+
+#define mmNIF_RTR_CTRL_3_RANGE_SEC_MASK_HIGH_AW_8 0x3B66C4
+
+#define mmNIF_RTR_CTRL_3_RANGE_SEC_MASK_HIGH_AW_9 0x3B66C8
+
+#define mmNIF_RTR_CTRL_3_RANGE_SEC_MASK_HIGH_AW_10 0x3B66CC
+
+#define mmNIF_RTR_CTRL_3_RANGE_SEC_MASK_HIGH_AW_11 0x3B66D0
+
+#define mmNIF_RTR_CTRL_3_RANGE_SEC_MASK_HIGH_AW_12 0x3B66D4
+
+#define mmNIF_RTR_CTRL_3_RANGE_SEC_MASK_HIGH_AW_13 0x3B66D8
+
+#define mmNIF_RTR_CTRL_3_RANGE_SEC_MASK_HIGH_AW_14 0x3B66DC
+
+#define mmNIF_RTR_CTRL_3_RANGE_SEC_MASK_HIGH_AW_15 0x3B66E0
+
+#define mmNIF_RTR_CTRL_3_RANGE_PRIV_BASE_LOW_AW_0 0x3B66E4
+
+#define mmNIF_RTR_CTRL_3_RANGE_PRIV_BASE_LOW_AW_1 0x3B66E8
+
+#define mmNIF_RTR_CTRL_3_RANGE_PRIV_BASE_LOW_AW_2 0x3B66EC
+
+#define mmNIF_RTR_CTRL_3_RANGE_PRIV_BASE_LOW_AW_3 0x3B66F0
+
+#define mmNIF_RTR_CTRL_3_RANGE_PRIV_BASE_LOW_AW_4 0x3B66F4
+
+#define mmNIF_RTR_CTRL_3_RANGE_PRIV_BASE_LOW_AW_5 0x3B66F8
+
+#define mmNIF_RTR_CTRL_3_RANGE_PRIV_BASE_LOW_AW_6 0x3B66FC
+
+#define mmNIF_RTR_CTRL_3_RANGE_PRIV_BASE_LOW_AW_7 0x3B6700
+
+#define mmNIF_RTR_CTRL_3_RANGE_PRIV_BASE_LOW_AW_8 0x3B6704
+
+#define mmNIF_RTR_CTRL_3_RANGE_PRIV_BASE_LOW_AW_9 0x3B6708
+
+#define mmNIF_RTR_CTRL_3_RANGE_PRIV_BASE_LOW_AW_10 0x3B670C
+
+#define mmNIF_RTR_CTRL_3_RANGE_PRIV_BASE_LOW_AW_11 0x3B6710
+
+#define mmNIF_RTR_CTRL_3_RANGE_PRIV_BASE_LOW_AW_12 0x3B6714
+
+#define mmNIF_RTR_CTRL_3_RANGE_PRIV_BASE_LOW_AW_13 0x3B6718
+
+#define mmNIF_RTR_CTRL_3_RANGE_PRIV_BASE_LOW_AW_14 0x3B671C
+
+#define mmNIF_RTR_CTRL_3_RANGE_PRIV_BASE_LOW_AW_15 0x3B6720
+
+#define mmNIF_RTR_CTRL_3_RANGE_PRIV_BASE_HIGH_AW_0 0x3B6724
+
+#define mmNIF_RTR_CTRL_3_RANGE_PRIV_BASE_HIGH_AW_1 0x3B6728
+
+#define mmNIF_RTR_CTRL_3_RANGE_PRIV_BASE_HIGH_AW_2 0x3B672C
+
+#define mmNIF_RTR_CTRL_3_RANGE_PRIV_BASE_HIGH_AW_3 0x3B6730
+
+#define mmNIF_RTR_CTRL_3_RANGE_PRIV_BASE_HIGH_AW_4 0x3B6734
+
+#define mmNIF_RTR_CTRL_3_RANGE_PRIV_BASE_HIGH_AW_5 0x3B6738
+
+#define mmNIF_RTR_CTRL_3_RANGE_PRIV_BASE_HIGH_AW_6 0x3B673C
+
+#define mmNIF_RTR_CTRL_3_RANGE_PRIV_BASE_HIGH_AW_7 0x3B6740
+
+#define mmNIF_RTR_CTRL_3_RANGE_PRIV_BASE_HIGH_AW_8 0x3B6744
+
+#define mmNIF_RTR_CTRL_3_RANGE_PRIV_BASE_HIGH_AW_9 0x3B6748
+
+#define mmNIF_RTR_CTRL_3_RANGE_PRIV_BASE_HIGH_AW_10 0x3B674C
+
+#define mmNIF_RTR_CTRL_3_RANGE_PRIV_BASE_HIGH_AW_11 0x3B6750
+
+#define mmNIF_RTR_CTRL_3_RANGE_PRIV_BASE_HIGH_AW_12 0x3B6754
+
+#define mmNIF_RTR_CTRL_3_RANGE_PRIV_BASE_HIGH_AW_13 0x3B6758
+
+#define mmNIF_RTR_CTRL_3_RANGE_PRIV_BASE_HIGH_AW_14 0x3B675C
+
+#define mmNIF_RTR_CTRL_3_RANGE_PRIV_BASE_HIGH_AW_15 0x3B6760
+
+#define mmNIF_RTR_CTRL_3_RANGE_PRIV_MASK_LOW_AW_0 0x3B6764
+
+#define mmNIF_RTR_CTRL_3_RANGE_PRIV_MASK_LOW_AW_1 0x3B6768
+
+#define mmNIF_RTR_CTRL_3_RANGE_PRIV_MASK_LOW_AW_2 0x3B676C
+
+#define mmNIF_RTR_CTRL_3_RANGE_PRIV_MASK_LOW_AW_3 0x3B6770
+
+#define mmNIF_RTR_CTRL_3_RANGE_PRIV_MASK_LOW_AW_4 0x3B6774
+
+#define mmNIF_RTR_CTRL_3_RANGE_PRIV_MASK_LOW_AW_5 0x3B6778
+
+#define mmNIF_RTR_CTRL_3_RANGE_PRIV_MASK_LOW_AW_6 0x3B677C
+
+#define mmNIF_RTR_CTRL_3_RANGE_PRIV_MASK_LOW_AW_7 0x3B6780
+
+#define mmNIF_RTR_CTRL_3_RANGE_PRIV_MASK_LOW_AW_8 0x3B6784
+
+#define mmNIF_RTR_CTRL_3_RANGE_PRIV_MASK_LOW_AW_9 0x3B6788
+
+#define mmNIF_RTR_CTRL_3_RANGE_PRIV_MASK_LOW_AW_10 0x3B678C
+
+#define mmNIF_RTR_CTRL_3_RANGE_PRIV_MASK_LOW_AW_11 0x3B6790
+
+#define mmNIF_RTR_CTRL_3_RANGE_PRIV_MASK_LOW_AW_12 0x3B6794
+
+#define mmNIF_RTR_CTRL_3_RANGE_PRIV_MASK_LOW_AW_13 0x3B6798
+
+#define mmNIF_RTR_CTRL_3_RANGE_PRIV_MASK_LOW_AW_14 0x3B679C
+
+#define mmNIF_RTR_CTRL_3_RANGE_PRIV_MASK_LOW_AW_15 0x3B67A0
+
+#define mmNIF_RTR_CTRL_3_RANGE_PRIV_MASK_HIGH_AW_0 0x3B67A4
+
+#define mmNIF_RTR_CTRL_3_RANGE_PRIV_MASK_HIGH_AW_1 0x3B67A8
+
+#define mmNIF_RTR_CTRL_3_RANGE_PRIV_MASK_HIGH_AW_2 0x3B67AC
+
+#define mmNIF_RTR_CTRL_3_RANGE_PRIV_MASK_HIGH_AW_3 0x3B67B0
+
+#define mmNIF_RTR_CTRL_3_RANGE_PRIV_MASK_HIGH_AW_4 0x3B67B4
+
+#define mmNIF_RTR_CTRL_3_RANGE_PRIV_MASK_HIGH_AW_5 0x3B67B8
+
+#define mmNIF_RTR_CTRL_3_RANGE_PRIV_MASK_HIGH_AW_6 0x3B67BC
+
+#define mmNIF_RTR_CTRL_3_RANGE_PRIV_MASK_HIGH_AW_7 0x3B67C0
+
+#define mmNIF_RTR_CTRL_3_RANGE_PRIV_MASK_HIGH_AW_8 0x3B67C4
+
+#define mmNIF_RTR_CTRL_3_RANGE_PRIV_MASK_HIGH_AW_9 0x3B67C8
+
+#define mmNIF_RTR_CTRL_3_RANGE_PRIV_MASK_HIGH_AW_10 0x3B67CC
+
+#define mmNIF_RTR_CTRL_3_RANGE_PRIV_MASK_HIGH_AW_11 0x3B67D0
+
+#define mmNIF_RTR_CTRL_3_RANGE_PRIV_MASK_HIGH_AW_12 0x3B67D4
+
+#define mmNIF_RTR_CTRL_3_RANGE_PRIV_MASK_HIGH_AW_13 0x3B67D8
+
+#define mmNIF_RTR_CTRL_3_RANGE_PRIV_MASK_HIGH_AW_14 0x3B67DC
+
+#define mmNIF_RTR_CTRL_3_RANGE_PRIV_MASK_HIGH_AW_15 0x3B67E0
+
+#define mmNIF_RTR_CTRL_3_RANGE_SEC_BASE_LOW_AR_0 0x3B6824
+
+#define mmNIF_RTR_CTRL_3_RANGE_SEC_BASE_LOW_AR_1 0x3B6828
+
+#define mmNIF_RTR_CTRL_3_RANGE_SEC_BASE_LOW_AR_2 0x3B682C
+
+#define mmNIF_RTR_CTRL_3_RANGE_SEC_BASE_LOW_AR_3 0x3B6830
+
+#define mmNIF_RTR_CTRL_3_RANGE_SEC_BASE_LOW_AR_4 0x3B6834
+
+#define mmNIF_RTR_CTRL_3_RANGE_SEC_BASE_LOW_AR_5 0x3B6838
+
+#define mmNIF_RTR_CTRL_3_RANGE_SEC_BASE_LOW_AR_6 0x3B683C
+
+#define mmNIF_RTR_CTRL_3_RANGE_SEC_BASE_LOW_AR_7 0x3B6840
+
+#define mmNIF_RTR_CTRL_3_RANGE_SEC_BASE_LOW_AR_8 0x3B6844
+
+#define mmNIF_RTR_CTRL_3_RANGE_SEC_BASE_LOW_AR_9 0x3B6848
+
+#define mmNIF_RTR_CTRL_3_RANGE_SEC_BASE_LOW_AR_10 0x3B684C
+
+#define mmNIF_RTR_CTRL_3_RANGE_SEC_BASE_LOW_AR_11 0x3B6850
+
+#define mmNIF_RTR_CTRL_3_RANGE_SEC_BASE_LOW_AR_12 0x3B6854
+
+#define mmNIF_RTR_CTRL_3_RANGE_SEC_BASE_LOW_AR_13 0x3B6858
+
+#define mmNIF_RTR_CTRL_3_RANGE_SEC_BASE_LOW_AR_14 0x3B685C
+
+#define mmNIF_RTR_CTRL_3_RANGE_SEC_BASE_LOW_AR_15 0x3B6860
+
+#define mmNIF_RTR_CTRL_3_RANGE_SEC_BASE_HIGH_AR_0 0x3B6864
+
+#define mmNIF_RTR_CTRL_3_RANGE_SEC_BASE_HIGH_AR_1 0x3B6868
+
+#define mmNIF_RTR_CTRL_3_RANGE_SEC_BASE_HIGH_AR_2 0x3B686C
+
+#define mmNIF_RTR_CTRL_3_RANGE_SEC_BASE_HIGH_AR_3 0x3B6870
+
+#define mmNIF_RTR_CTRL_3_RANGE_SEC_BASE_HIGH_AR_4 0x3B6874
+
+#define mmNIF_RTR_CTRL_3_RANGE_SEC_BASE_HIGH_AR_5 0x3B6878
+
+#define mmNIF_RTR_CTRL_3_RANGE_SEC_BASE_HIGH_AR_6 0x3B687C
+
+#define mmNIF_RTR_CTRL_3_RANGE_SEC_BASE_HIGH_AR_7 0x3B6880
+
+#define mmNIF_RTR_CTRL_3_RANGE_SEC_BASE_HIGH_AR_8 0x3B6884
+
+#define mmNIF_RTR_CTRL_3_RANGE_SEC_BASE_HIGH_AR_9 0x3B6888
+
+#define mmNIF_RTR_CTRL_3_RANGE_SEC_BASE_HIGH_AR_10 0x3B688C
+
+#define mmNIF_RTR_CTRL_3_RANGE_SEC_BASE_HIGH_AR_11 0x3B6890
+
+#define mmNIF_RTR_CTRL_3_RANGE_SEC_BASE_HIGH_AR_12 0x3B6894
+
+#define mmNIF_RTR_CTRL_3_RANGE_SEC_BASE_HIGH_AR_13 0x3B6898
+
+#define mmNIF_RTR_CTRL_3_RANGE_SEC_BASE_HIGH_AR_14 0x3B689C
+
+#define mmNIF_RTR_CTRL_3_RANGE_SEC_BASE_HIGH_AR_15 0x3B68A0
+
+#define mmNIF_RTR_CTRL_3_RANGE_SEC_MASK_LOW_AR_0 0x3B68A4
+
+#define mmNIF_RTR_CTRL_3_RANGE_SEC_MASK_LOW_AR_1 0x3B68A8
+
+#define mmNIF_RTR_CTRL_3_RANGE_SEC_MASK_LOW_AR_2 0x3B68AC
+
+#define mmNIF_RTR_CTRL_3_RANGE_SEC_MASK_LOW_AR_3 0x3B68B0
+
+#define mmNIF_RTR_CTRL_3_RANGE_SEC_MASK_LOW_AR_4 0x3B68B4
+
+#define mmNIF_RTR_CTRL_3_RANGE_SEC_MASK_LOW_AR_5 0x3B68B8
+
+#define mmNIF_RTR_CTRL_3_RANGE_SEC_MASK_LOW_AR_6 0x3B68BC
+
+#define mmNIF_RTR_CTRL_3_RANGE_SEC_MASK_LOW_AR_7 0x3B68C0
+
+#define mmNIF_RTR_CTRL_3_RANGE_SEC_MASK_LOW_AR_8 0x3B68C4
+
+#define mmNIF_RTR_CTRL_3_RANGE_SEC_MASK_LOW_AR_9 0x3B68C8
+
+#define mmNIF_RTR_CTRL_3_RANGE_SEC_MASK_LOW_AR_10 0x3B68CC
+
+#define mmNIF_RTR_CTRL_3_RANGE_SEC_MASK_LOW_AR_11 0x3B68D0
+
+#define mmNIF_RTR_CTRL_3_RANGE_SEC_MASK_LOW_AR_12 0x3B68D4
+
+#define mmNIF_RTR_CTRL_3_RANGE_SEC_MASK_LOW_AR_13 0x3B68D8
+
+#define mmNIF_RTR_CTRL_3_RANGE_SEC_MASK_LOW_AR_14 0x3B68DC
+
+#define mmNIF_RTR_CTRL_3_RANGE_SEC_MASK_LOW_AR_15 0x3B68E0
+
+#define mmNIF_RTR_CTRL_3_RANGE_SEC_MASK_HIGH_AR_0 0x3B68E4
+
+#define mmNIF_RTR_CTRL_3_RANGE_SEC_MASK_HIGH_AR_1 0x3B68E8
+
+#define mmNIF_RTR_CTRL_3_RANGE_SEC_MASK_HIGH_AR_2 0x3B68EC
+
+#define mmNIF_RTR_CTRL_3_RANGE_SEC_MASK_HIGH_AR_3 0x3B68F0
+
+#define mmNIF_RTR_CTRL_3_RANGE_SEC_MASK_HIGH_AR_4 0x3B68F4
+
+#define mmNIF_RTR_CTRL_3_RANGE_SEC_MASK_HIGH_AR_5 0x3B68F8
+
+#define mmNIF_RTR_CTRL_3_RANGE_SEC_MASK_HIGH_AR_6 0x3B68FC
+
+#define mmNIF_RTR_CTRL_3_RANGE_SEC_MASK_HIGH_AR_7 0x3B6900
+
+#define mmNIF_RTR_CTRL_3_RANGE_SEC_MASK_HIGH_AR_8 0x3B6904
+
+#define mmNIF_RTR_CTRL_3_RANGE_SEC_MASK_HIGH_AR_9 0x3B6908
+
+#define mmNIF_RTR_CTRL_3_RANGE_SEC_MASK_HIGH_AR_10 0x3B690C
+
+#define mmNIF_RTR_CTRL_3_RANGE_SEC_MASK_HIGH_AR_11 0x3B6910
+
+#define mmNIF_RTR_CTRL_3_RANGE_SEC_MASK_HIGH_AR_12 0x3B6914
+
+#define mmNIF_RTR_CTRL_3_RANGE_SEC_MASK_HIGH_AR_13 0x3B6918
+
+#define mmNIF_RTR_CTRL_3_RANGE_SEC_MASK_HIGH_AR_14 0x3B691C
+
+#define mmNIF_RTR_CTRL_3_RANGE_SEC_MASK_HIGH_AR_15 0x3B6920
+
+#define mmNIF_RTR_CTRL_3_RANGE_PRIV_BASE_LOW_AR_0 0x3B6924
+
+#define mmNIF_RTR_CTRL_3_RANGE_PRIV_BASE_LOW_AR_1 0x3B6928
+
+#define mmNIF_RTR_CTRL_3_RANGE_PRIV_BASE_LOW_AR_2 0x3B692C
+
+#define mmNIF_RTR_CTRL_3_RANGE_PRIV_BASE_LOW_AR_3 0x3B6930
+
+#define mmNIF_RTR_CTRL_3_RANGE_PRIV_BASE_LOW_AR_4 0x3B6934
+
+#define mmNIF_RTR_CTRL_3_RANGE_PRIV_BASE_LOW_AR_5 0x3B6938
+
+#define mmNIF_RTR_CTRL_3_RANGE_PRIV_BASE_LOW_AR_6 0x3B693C
+
+#define mmNIF_RTR_CTRL_3_RANGE_PRIV_BASE_LOW_AR_7 0x3B6940
+
+#define mmNIF_RTR_CTRL_3_RANGE_PRIV_BASE_LOW_AR_8 0x3B6944
+
+#define mmNIF_RTR_CTRL_3_RANGE_PRIV_BASE_LOW_AR_9 0x3B6948
+
+#define mmNIF_RTR_CTRL_3_RANGE_PRIV_BASE_LOW_AR_10 0x3B694C
+
+#define mmNIF_RTR_CTRL_3_RANGE_PRIV_BASE_LOW_AR_11 0x3B6950
+
+#define mmNIF_RTR_CTRL_3_RANGE_PRIV_BASE_LOW_AR_12 0x3B6954
+
+#define mmNIF_RTR_CTRL_3_RANGE_PRIV_BASE_LOW_AR_13 0x3B6958
+
+#define mmNIF_RTR_CTRL_3_RANGE_PRIV_BASE_LOW_AR_14 0x3B695C
+
+#define mmNIF_RTR_CTRL_3_RANGE_PRIV_BASE_LOW_AR_15 0x3B6960
+
+#define mmNIF_RTR_CTRL_3_RANGE_PRIV_BASE_HIGH_AR_0 0x3B6964
+
+#define mmNIF_RTR_CTRL_3_RANGE_PRIV_BASE_HIGH_AR_1 0x3B6968
+
+#define mmNIF_RTR_CTRL_3_RANGE_PRIV_BASE_HIGH_AR_2 0x3B696C
+
+#define mmNIF_RTR_CTRL_3_RANGE_PRIV_BASE_HIGH_AR_3 0x3B6970
+
+#define mmNIF_RTR_CTRL_3_RANGE_PRIV_BASE_HIGH_AR_4 0x3B6974
+
+#define mmNIF_RTR_CTRL_3_RANGE_PRIV_BASE_HIGH_AR_5 0x3B6978
+
+#define mmNIF_RTR_CTRL_3_RANGE_PRIV_BASE_HIGH_AR_6 0x3B697C
+
+#define mmNIF_RTR_CTRL_3_RANGE_PRIV_BASE_HIGH_AR_7 0x3B6980
+
+#define mmNIF_RTR_CTRL_3_RANGE_PRIV_BASE_HIGH_AR_8 0x3B6984
+
+#define mmNIF_RTR_CTRL_3_RANGE_PRIV_BASE_HIGH_AR_9 0x3B6988
+
+#define mmNIF_RTR_CTRL_3_RANGE_PRIV_BASE_HIGH_AR_10 0x3B698C
+
+#define mmNIF_RTR_CTRL_3_RANGE_PRIV_BASE_HIGH_AR_11 0x3B6990
+
+#define mmNIF_RTR_CTRL_3_RANGE_PRIV_BASE_HIGH_AR_12 0x3B6994
+
+#define mmNIF_RTR_CTRL_3_RANGE_PRIV_BASE_HIGH_AR_13 0x3B6998
+
+#define mmNIF_RTR_CTRL_3_RANGE_PRIV_BASE_HIGH_AR_14 0x3B699C
+
+#define mmNIF_RTR_CTRL_3_RANGE_PRIV_BASE_HIGH_AR_15 0x3B69A0
+
+#define mmNIF_RTR_CTRL_3_RANGE_PRIV_MASK_LOW_AR_0 0x3B69A4
+
+#define mmNIF_RTR_CTRL_3_RANGE_PRIV_MASK_LOW_AR_1 0x3B69A8
+
+#define mmNIF_RTR_CTRL_3_RANGE_PRIV_MASK_LOW_AR_2 0x3B69AC
+
+#define mmNIF_RTR_CTRL_3_RANGE_PRIV_MASK_LOW_AR_3 0x3B69B0
+
+#define mmNIF_RTR_CTRL_3_RANGE_PRIV_MASK_LOW_AR_4 0x3B69B4
+
+#define mmNIF_RTR_CTRL_3_RANGE_PRIV_MASK_LOW_AR_5 0x3B69B8
+
+#define mmNIF_RTR_CTRL_3_RANGE_PRIV_MASK_LOW_AR_6 0x3B69BC
+
+#define mmNIF_RTR_CTRL_3_RANGE_PRIV_MASK_LOW_AR_7 0x3B69C0
+
+#define mmNIF_RTR_CTRL_3_RANGE_PRIV_MASK_LOW_AR_8 0x3B69C4
+
+#define mmNIF_RTR_CTRL_3_RANGE_PRIV_MASK_LOW_AR_9 0x3B69C8
+
+#define mmNIF_RTR_CTRL_3_RANGE_PRIV_MASK_LOW_AR_10 0x3B69CC
+
+#define mmNIF_RTR_CTRL_3_RANGE_PRIV_MASK_LOW_AR_11 0x3B69D0
+
+#define mmNIF_RTR_CTRL_3_RANGE_PRIV_MASK_LOW_AR_12 0x3B69D4
+
+#define mmNIF_RTR_CTRL_3_RANGE_PRIV_MASK_LOW_AR_13 0x3B69D8
+
+#define mmNIF_RTR_CTRL_3_RANGE_PRIV_MASK_LOW_AR_14 0x3B69DC
+
+#define mmNIF_RTR_CTRL_3_RANGE_PRIV_MASK_LOW_AR_15 0x3B69E0
+
+#define mmNIF_RTR_CTRL_3_RANGE_PRIV_MASK_HIGH_AR_0 0x3B69E4
+
+#define mmNIF_RTR_CTRL_3_RANGE_PRIV_MASK_HIGH_AR_1 0x3B69E8
+
+#define mmNIF_RTR_CTRL_3_RANGE_PRIV_MASK_HIGH_AR_2 0x3B69EC
+
+#define mmNIF_RTR_CTRL_3_RANGE_PRIV_MASK_HIGH_AR_3 0x3B69F0
+
+#define mmNIF_RTR_CTRL_3_RANGE_PRIV_MASK_HIGH_AR_4 0x3B69F4
+
+#define mmNIF_RTR_CTRL_3_RANGE_PRIV_MASK_HIGH_AR_5 0x3B69F8
+
+#define mmNIF_RTR_CTRL_3_RANGE_PRIV_MASK_HIGH_AR_6 0x3B69FC
+
+#define mmNIF_RTR_CTRL_3_RANGE_PRIV_MASK_HIGH_AR_7 0x3B6A00
+
+#define mmNIF_RTR_CTRL_3_RANGE_PRIV_MASK_HIGH_AR_8 0x3B6A04
+
+#define mmNIF_RTR_CTRL_3_RANGE_PRIV_MASK_HIGH_AR_9 0x3B6A08
+
+#define mmNIF_RTR_CTRL_3_RANGE_PRIV_MASK_HIGH_AR_10 0x3B6A0C
+
+#define mmNIF_RTR_CTRL_3_RANGE_PRIV_MASK_HIGH_AR_11 0x3B6A10
+
+#define mmNIF_RTR_CTRL_3_RANGE_PRIV_MASK_HIGH_AR_12 0x3B6A14
+
+#define mmNIF_RTR_CTRL_3_RANGE_PRIV_MASK_HIGH_AR_13 0x3B6A18
+
+#define mmNIF_RTR_CTRL_3_RANGE_PRIV_MASK_HIGH_AR_14 0x3B6A1C
+
+#define mmNIF_RTR_CTRL_3_RANGE_PRIV_MASK_HIGH_AR_15 0x3B6A20
+
+#define mmNIF_RTR_CTRL_3_RANGE_SEC_HIT_AW 0x3B6A64
+
+#define mmNIF_RTR_CTRL_3_RANGE_SEC_HIT_AR 0x3B6A68
+
+#define mmNIF_RTR_CTRL_3_RANGE_PRIV_HIT_AW 0x3B6A6C
+
+#define mmNIF_RTR_CTRL_3_RANGE_PRIV_HIT_AR 0x3B6A70
+
+#define mmNIF_RTR_CTRL_3_RGL_CFG 0x3B6B64
+
+#define mmNIF_RTR_CTRL_3_RGL_SHIFT 0x3B6B68
+
+#define mmNIF_RTR_CTRL_3_RGL_EXPECTED_LAT_0 0x3B6B6C
+
+#define mmNIF_RTR_CTRL_3_RGL_EXPECTED_LAT_1 0x3B6B70
+
+#define mmNIF_RTR_CTRL_3_RGL_EXPECTED_LAT_2 0x3B6B74
+
+#define mmNIF_RTR_CTRL_3_RGL_EXPECTED_LAT_3 0x3B6B78
+
+#define mmNIF_RTR_CTRL_3_RGL_EXPECTED_LAT_4 0x3B6B7C
+
+#define mmNIF_RTR_CTRL_3_RGL_EXPECTED_LAT_5 0x3B6B80
+
+#define mmNIF_RTR_CTRL_3_RGL_EXPECTED_LAT_6 0x3B6B84
+
+#define mmNIF_RTR_CTRL_3_RGL_EXPECTED_LAT_7 0x3B6B88
+
+#define mmNIF_RTR_CTRL_3_RGL_TOKEN_0 0x3B6BAC
+
+#define mmNIF_RTR_CTRL_3_RGL_TOKEN_1 0x3B6BB0
+
+#define mmNIF_RTR_CTRL_3_RGL_TOKEN_2 0x3B6BB4
+
+#define mmNIF_RTR_CTRL_3_RGL_TOKEN_3 0x3B6BB8
+
+#define mmNIF_RTR_CTRL_3_RGL_TOKEN_4 0x3B6BBC
+
+#define mmNIF_RTR_CTRL_3_RGL_TOKEN_5 0x3B6BC0
+
+#define mmNIF_RTR_CTRL_3_RGL_TOKEN_6 0x3B6BC4
+
+#define mmNIF_RTR_CTRL_3_RGL_TOKEN_7 0x3B6BC8
+
+#define mmNIF_RTR_CTRL_3_RGL_BANK_ID_0 0x3B6BEC
+
+#define mmNIF_RTR_CTRL_3_RGL_BANK_ID_1 0x3B6BF0
+
+#define mmNIF_RTR_CTRL_3_RGL_BANK_ID_2 0x3B6BF4
+
+#define mmNIF_RTR_CTRL_3_RGL_BANK_ID_3 0x3B6BF8
+
+#define mmNIF_RTR_CTRL_3_RGL_BANK_ID_4 0x3B6BFC
+
+#define mmNIF_RTR_CTRL_3_RGL_BANK_ID_5 0x3B6C00
+
+#define mmNIF_RTR_CTRL_3_RGL_BANK_ID_6 0x3B6C04
+
+#define mmNIF_RTR_CTRL_3_RGL_BANK_ID_7 0x3B6C08
+
+#define mmNIF_RTR_CTRL_3_RGL_WDT 0x3B6C2C
+
+#define mmNIF_RTR_CTRL_3_E2E_AR_HBM0_CH0_CTR_WRAP 0x3B6C30
+
+#define mmNIF_RTR_CTRL_3_E2E_AR_HBM0_CH1_CTR_WRAP 0x3B6C34
+
+#define mmNIF_RTR_CTRL_3_E2E_AR_HBM1_CH0_CTR_WRAP 0x3B6C38
+
+#define mmNIF_RTR_CTRL_3_E2E_AR_HBM1_CH1_CTR_WRAP 0x3B6C3C
+
+#define mmNIF_RTR_CTRL_3_E2E_AR_HBM2_CH0_CTR_WRAP 0x3B6C40
+
+#define mmNIF_RTR_CTRL_3_E2E_AR_HBM2_CH1_CTR_WRAP 0x3B6C44
+
+#define mmNIF_RTR_CTRL_3_E2E_AR_HBM3_CH0_CTR_WRAP 0x3B6C48
+
+#define mmNIF_RTR_CTRL_3_E2E_AR_HBM3_CH1_CTR_WRAP 0x3B6C4C
+
+#define mmNIF_RTR_CTRL_3_E2E_AR_HBM0_CH0_CTR_CNT 0x3B6C50
+
+#define mmNIF_RTR_CTRL_3_E2E_AR_HBM0_CH1_CTR_CNT 0x3B6C54
+
+#define mmNIF_RTR_CTRL_3_E2E_AR_HBM1_CH0_CTR_CNT 0x3B6C58
+
+#define mmNIF_RTR_CTRL_3_E2E_AR_HBM1_CH1_CTR_CNT 0x3B6C5C
+
+#define mmNIF_RTR_CTRL_3_E2E_AR_HBM2_CH0_CTR_CNT 0x3B6C60
+
+#define mmNIF_RTR_CTRL_3_E2E_AR_HBM2_CH1_CTR_CNT 0x3B6C64
+
+#define mmNIF_RTR_CTRL_3_E2E_AR_HBM3_CH0_CTR_CNT 0x3B6C68
+
+#define mmNIF_RTR_CTRL_3_E2E_AR_HBM3_CH1_CTR_CNT 0x3B6C6C
+
+#define mmNIF_RTR_CTRL_3_E2E_AW_HBM0_CH0_CTR_WRAP 0x3B6C70
+
+#define mmNIF_RTR_CTRL_3_E2E_AW_HBM0_CH1_CTR_WRAP 0x3B6C74
+
+#define mmNIF_RTR_CTRL_3_E2E_AW_HBM1_CH0_CTR_WRAP 0x3B6C78
+
+#define mmNIF_RTR_CTRL_3_E2E_AW_HBM1_CH1_CTR_WRAP 0x3B6C7C
+
+#define mmNIF_RTR_CTRL_3_E2E_AW_HBM2_CH0_CTR_WRAP 0x3B6C80
+
+#define mmNIF_RTR_CTRL_3_E2E_AW_HBM2_CH1_CTR_WRAP 0x3B6C84
+
+#define mmNIF_RTR_CTRL_3_E2E_AW_HBM3_CH0_CTR_WRAP 0x3B6C88
+
+#define mmNIF_RTR_CTRL_3_E2E_AW_HBM3_CH1_CTR_WRAP 0x3B6C8C
+
+#define mmNIF_RTR_CTRL_3_E2E_AW_HBM0_CH0_CTR_CNT 0x3B6C90
+
+#define mmNIF_RTR_CTRL_3_E2E_AW_HBM0_CH1_CTR_CNT 0x3B6C94
+
+#define mmNIF_RTR_CTRL_3_E2E_AW_HBM1_CH0_CTR_CNT 0x3B6C98
+
+#define mmNIF_RTR_CTRL_3_E2E_AW_HBM1_CH1_CTR_CNT 0x3B6C9C
+
+#define mmNIF_RTR_CTRL_3_E2E_AW_HBM2_CH0_CTR_CNT 0x3B6CA0
+
+#define mmNIF_RTR_CTRL_3_E2E_AW_HBM2_CH1_CTR_CNT 0x3B6CA4
+
+#define mmNIF_RTR_CTRL_3_E2E_AW_HBM3_CH0_CTR_CNT 0x3B6CA8
+
+#define mmNIF_RTR_CTRL_3_E2E_AW_HBM3_CH1_CTR_CNT 0x3B6CAC
+
+#define mmNIF_RTR_CTRL_3_NL_HBM_PC_SEL_0 0x3B6CB0
+
+#define mmNIF_RTR_CTRL_3_NL_HBM_PC_SEL_1 0x3B6CB4
+
+#define mmNIF_RTR_CTRL_3_NL_HBM_PC_SEL_2 0x3B6CB8
+
+#define mmNIF_RTR_CTRL_3_NL_HBM_PC_SEL_3 0x3B6CBC
+
+#endif /* ASIC_REG_NIF_RTR_CTRL_3_REGS_H_ */
diff --git a/drivers/accel/habanalabs/include/gaudi/asic_reg/nif_rtr_ctrl_4_regs.h b/drivers/accel/habanalabs/include/gaudi/asic_reg/nif_rtr_ctrl_4_regs.h
new file mode 100644
index 0000000000..543a98f817
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi/asic_reg/nif_rtr_ctrl_4_regs.h
@@ -0,0 +1,896 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2016-2018 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ ** DO NOT EDIT BELOW **
+ ************************************/
+
+#ifndef ASIC_REG_NIF_RTR_CTRL_4_REGS_H_
+#define ASIC_REG_NIF_RTR_CTRL_4_REGS_H_
+
+/*
+ *****************************************
+ * NIF_RTR_CTRL_4 (Prototype: RTR_CTRL)
+ *****************************************
+ */
+
+#define mmNIF_RTR_CTRL_4_PERM_SEL 0x3C6108
+
+#define mmNIF_RTR_CTRL_4_HBM_POLY_H3_0 0x3C6114
+
+#define mmNIF_RTR_CTRL_4_HBM_POLY_H3_1 0x3C6118
+
+#define mmNIF_RTR_CTRL_4_HBM_POLY_H3_2 0x3C611C
+
+#define mmNIF_RTR_CTRL_4_HBM_POLY_H3_3 0x3C6120
+
+#define mmNIF_RTR_CTRL_4_HBM_POLY_H3_4 0x3C6124
+
+#define mmNIF_RTR_CTRL_4_HBM_POLY_H3_5 0x3C6128
+
+#define mmNIF_RTR_CTRL_4_HBM_POLY_H3_6 0x3C612C
+
+#define mmNIF_RTR_CTRL_4_HBM_POLY_H3_7 0x3C6130
+
+#define mmNIF_RTR_CTRL_4_HBM_POLY_H3_8 0x3C6134
+
+#define mmNIF_RTR_CTRL_4_HBM_POLY_H3_9 0x3C6138
+
+#define mmNIF_RTR_CTRL_4_HBM_POLY_H3_10 0x3C613C
+
+#define mmNIF_RTR_CTRL_4_HBM_POLY_H3_11 0x3C6140
+
+#define mmNIF_RTR_CTRL_4_HBM_POLY_H3_12 0x3C6144
+
+#define mmNIF_RTR_CTRL_4_HBM_POLY_H3_13 0x3C6148
+
+#define mmNIF_RTR_CTRL_4_HBM_POLY_H3_14 0x3C614C
+
+#define mmNIF_RTR_CTRL_4_HBM_POLY_H3_15 0x3C6150
+
+#define mmNIF_RTR_CTRL_4_HBM_POLY_H3_16 0x3C6154
+
+#define mmNIF_RTR_CTRL_4_HBM_POLY_H3_17 0x3C6158
+
+#define mmNIF_RTR_CTRL_4_HBM_POLY_H3_18 0x3C615C
+
+#define mmNIF_RTR_CTRL_4_HBM_POLY_H3_19 0x3C6160
+
+#define mmNIF_RTR_CTRL_4_HBM_POLY_H3_20 0x3C6164
+
+#define mmNIF_RTR_CTRL_4_HBM_POLY_H3_21 0x3C6168
+
+#define mmNIF_RTR_CTRL_4_HBM_POLY_H3_22 0x3C616C
+
+#define mmNIF_RTR_CTRL_4_HBM_POLY_H3_23 0x3C6170
+
+#define mmNIF_RTR_CTRL_4_HBM_POLY_H3_24 0x3C6174
+
+#define mmNIF_RTR_CTRL_4_HBM_POLY_H3_25 0x3C6178
+
+#define mmNIF_RTR_CTRL_4_HBM_POLY_H3_26 0x3C617C
+
+#define mmNIF_RTR_CTRL_4_HBM_POLY_H3_27 0x3C6180
+
+#define mmNIF_RTR_CTRL_4_SRAM_POLY_H3_0 0x3C6184
+
+#define mmNIF_RTR_CTRL_4_SRAM_POLY_H3_1 0x3C6188
+
+#define mmNIF_RTR_CTRL_4_SRAM_POLY_H3_2 0x3C618C
+
+#define mmNIF_RTR_CTRL_4_SRAM_POLY_H3_3 0x3C6190
+
+#define mmNIF_RTR_CTRL_4_SRAM_POLY_H3_4 0x3C6194
+
+#define mmNIF_RTR_CTRL_4_SRAM_POLY_H3_5 0x3C6198
+
+#define mmNIF_RTR_CTRL_4_SRAM_POLY_H3_6 0x3C619C
+
+#define mmNIF_RTR_CTRL_4_SRAM_POLY_H3_7 0x3C61A0
+
+#define mmNIF_RTR_CTRL_4_SRAM_POLY_H3_8 0x3C61A4
+
+#define mmNIF_RTR_CTRL_4_SRAM_POLY_H3_9 0x3C61A8
+
+#define mmNIF_RTR_CTRL_4_SRAM_POLY_H3_10 0x3C61AC
+
+#define mmNIF_RTR_CTRL_4_SRAM_POLY_H3_11 0x3C61B0
+
+#define mmNIF_RTR_CTRL_4_SRAM_POLY_H3_12 0x3C61B4
+
+#define mmNIF_RTR_CTRL_4_SRAM_POLY_H3_13 0x3C61B8
+
+#define mmNIF_RTR_CTRL_4_SRAM_POLY_H3_14 0x3C61BC
+
+#define mmNIF_RTR_CTRL_4_SCRAM_SRAM_EN 0x3C626C
+
+#define mmNIF_RTR_CTRL_4_RL_HBM_EN 0x3C6274
+
+#define mmNIF_RTR_CTRL_4_RL_HBM_SAT 0x3C6278
+
+#define mmNIF_RTR_CTRL_4_RL_HBM_RST 0x3C627C
+
+#define mmNIF_RTR_CTRL_4_RL_HBM_TIMEOUT 0x3C6280
+
+#define mmNIF_RTR_CTRL_4_SCRAM_HBM_EN 0x3C6284
+
+#define mmNIF_RTR_CTRL_4_RL_PCI_EN 0x3C6288
+
+#define mmNIF_RTR_CTRL_4_RL_PCI_SAT 0x3C628C
+
+#define mmNIF_RTR_CTRL_4_RL_PCI_RST 0x3C6290
+
+#define mmNIF_RTR_CTRL_4_RL_PCI_TIMEOUT 0x3C6294
+
+#define mmNIF_RTR_CTRL_4_RL_SRAM_EN 0x3C629C
+
+#define mmNIF_RTR_CTRL_4_RL_SRAM_SAT 0x3C62A0
+
+#define mmNIF_RTR_CTRL_4_RL_SRAM_RST 0x3C62A4
+
+#define mmNIF_RTR_CTRL_4_RL_SRAM_TIMEOUT 0x3C62AC
+
+#define mmNIF_RTR_CTRL_4_RL_SRAM_RED 0x3C62B4
+
+#define mmNIF_RTR_CTRL_4_E2E_HBM_EN 0x3C62EC
+
+#define mmNIF_RTR_CTRL_4_E2E_PCI_EN 0x3C62F0
+
+#define mmNIF_RTR_CTRL_4_E2E_HBM_WR_SIZE 0x3C62F4
+
+#define mmNIF_RTR_CTRL_4_E2E_PCI_WR_SIZE 0x3C62F8
+
+#define mmNIF_RTR_CTRL_4_E2E_AW_PCI_CTR_SET_EN 0x3C6404
+
+#define mmNIF_RTR_CTRL_4_E2E_AW_PCI_CTR_SET 0x3C6408
+
+#define mmNIF_RTR_CTRL_4_E2E_AW_PCI_CTR_WRAP 0x3C640C
+
+#define mmNIF_RTR_CTRL_4_E2E_AW_PCI_CTR_CNT 0x3C6410
+
+#define mmNIF_RTR_CTRL_4_E2E_AW_HBM_CTR_SET_EN 0x3C6414
+
+#define mmNIF_RTR_CTRL_4_E2E_AW_HBM_CTR_SET 0x3C6418
+
+#define mmNIF_RTR_CTRL_4_E2E_HBM_RD_SIZE 0x3C641C
+
+#define mmNIF_RTR_CTRL_4_E2E_PCI_RD_SIZE 0x3C6420
+
+#define mmNIF_RTR_CTRL_4_E2E_AR_PCI_CTR_SET_EN 0x3C6424
+
+#define mmNIF_RTR_CTRL_4_E2E_AR_PCI_CTR_SET 0x3C6428
+
+#define mmNIF_RTR_CTRL_4_E2E_AR_PCI_CTR_WRAP 0x3C642C
+
+#define mmNIF_RTR_CTRL_4_E2E_AR_PCI_CTR_CNT 0x3C6430
+
+#define mmNIF_RTR_CTRL_4_E2E_AR_HBM_CTR_SET_EN 0x3C6434
+
+#define mmNIF_RTR_CTRL_4_E2E_AR_HBM_CTR_SET 0x3C6438
+
+#define mmNIF_RTR_CTRL_4_NL_HBM_SEL_0 0x3C6450
+
+#define mmNIF_RTR_CTRL_4_NL_HBM_SEL_1 0x3C6454
+
+#define mmNIF_RTR_CTRL_4_NON_LIN_EN 0x3C6480
+
+#define mmNIF_RTR_CTRL_4_NL_SRAM_BANK_0 0x3C6500
+
+#define mmNIF_RTR_CTRL_4_NL_SRAM_BANK_1 0x3C6504
+
+#define mmNIF_RTR_CTRL_4_NL_SRAM_BANK_2 0x3C6508
+
+#define mmNIF_RTR_CTRL_4_NL_SRAM_BANK_3 0x3C650C
+
+#define mmNIF_RTR_CTRL_4_NL_SRAM_BANK_4 0x3C6510
+
+#define mmNIF_RTR_CTRL_4_NL_SRAM_OFFSET_0 0x3C6514
+
+#define mmNIF_RTR_CTRL_4_NL_SRAM_OFFSET_1 0x3C6520
+
+#define mmNIF_RTR_CTRL_4_NL_SRAM_OFFSET_2 0x3C6524
+
+#define mmNIF_RTR_CTRL_4_NL_SRAM_OFFSET_3 0x3C6528
+
+#define mmNIF_RTR_CTRL_4_NL_SRAM_OFFSET_4 0x3C652C
+
+#define mmNIF_RTR_CTRL_4_NL_SRAM_OFFSET_5 0x3C6530
+
+#define mmNIF_RTR_CTRL_4_NL_SRAM_OFFSET_6 0x3C6534
+
+#define mmNIF_RTR_CTRL_4_NL_SRAM_OFFSET_7 0x3C6538
+
+#define mmNIF_RTR_CTRL_4_NL_SRAM_OFFSET_8 0x3C653C
+
+#define mmNIF_RTR_CTRL_4_NL_SRAM_OFFSET_9 0x3C6540
+
+#define mmNIF_RTR_CTRL_4_NL_HBM_OFFSET_0 0x3C6550
+
+#define mmNIF_RTR_CTRL_4_NL_HBM_OFFSET_1 0x3C6554
+
+#define mmNIF_RTR_CTRL_4_NL_HBM_OFFSET_2 0x3C6558
+
+#define mmNIF_RTR_CTRL_4_NL_HBM_OFFSET_3 0x3C655C
+
+#define mmNIF_RTR_CTRL_4_NL_HBM_OFFSET_4 0x3C6560
+
+#define mmNIF_RTR_CTRL_4_NL_HBM_OFFSET_5 0x3C6564
+
+#define mmNIF_RTR_CTRL_4_NL_HBM_OFFSET_6 0x3C6568
+
+#define mmNIF_RTR_CTRL_4_NL_HBM_OFFSET_7 0x3C656C
+
+#define mmNIF_RTR_CTRL_4_NL_HBM_OFFSET_8 0x3C6570
+
+#define mmNIF_RTR_CTRL_4_NL_HBM_OFFSET_9 0x3C6574
+
+#define mmNIF_RTR_CTRL_4_NL_HBM_OFFSET_10 0x3C6578
+
+#define mmNIF_RTR_CTRL_4_NL_HBM_OFFSET_11 0x3C657C
+
+#define mmNIF_RTR_CTRL_4_NL_HBM_OFFSET_12 0x3C6580
+
+#define mmNIF_RTR_CTRL_4_NL_HBM_OFFSET_13 0x3C6584
+
+#define mmNIF_RTR_CTRL_4_NL_HBM_OFFSET_14 0x3C6588
+
+#define mmNIF_RTR_CTRL_4_NL_HBM_OFFSET_15 0x3C658C
+
+#define mmNIF_RTR_CTRL_4_NL_HBM_OFFSET_16 0x3C6590
+
+#define mmNIF_RTR_CTRL_4_NL_HBM_OFFSET_17 0x3C6594
+
+#define mmNIF_RTR_CTRL_4_NL_HBM_OFFSET_18 0x3C6598
+
+#define mmNIF_RTR_CTRL_4_RANGE_SEC_BASE_LOW_AW_0 0x3C65E4
+
+#define mmNIF_RTR_CTRL_4_RANGE_SEC_BASE_LOW_AW_1 0x3C65E8
+
+#define mmNIF_RTR_CTRL_4_RANGE_SEC_BASE_LOW_AW_2 0x3C65EC
+
+#define mmNIF_RTR_CTRL_4_RANGE_SEC_BASE_LOW_AW_3 0x3C65F0
+
+#define mmNIF_RTR_CTRL_4_RANGE_SEC_BASE_LOW_AW_4 0x3C65F4
+
+#define mmNIF_RTR_CTRL_4_RANGE_SEC_BASE_LOW_AW_5 0x3C65F8
+
+#define mmNIF_RTR_CTRL_4_RANGE_SEC_BASE_LOW_AW_6 0x3C65FC
+
+#define mmNIF_RTR_CTRL_4_RANGE_SEC_BASE_LOW_AW_7 0x3C6600
+
+#define mmNIF_RTR_CTRL_4_RANGE_SEC_BASE_LOW_AW_8 0x3C6604
+
+#define mmNIF_RTR_CTRL_4_RANGE_SEC_BASE_LOW_AW_9 0x3C6608
+
+#define mmNIF_RTR_CTRL_4_RANGE_SEC_BASE_LOW_AW_10 0x3C660C
+
+#define mmNIF_RTR_CTRL_4_RANGE_SEC_BASE_LOW_AW_11 0x3C6610
+
+#define mmNIF_RTR_CTRL_4_RANGE_SEC_BASE_LOW_AW_12 0x3C6614
+
+#define mmNIF_RTR_CTRL_4_RANGE_SEC_BASE_LOW_AW_13 0x3C6618
+
+#define mmNIF_RTR_CTRL_4_RANGE_SEC_BASE_LOW_AW_14 0x3C661C
+
+#define mmNIF_RTR_CTRL_4_RANGE_SEC_BASE_LOW_AW_15 0x3C6620
+
+#define mmNIF_RTR_CTRL_4_RANGE_SEC_BASE_HIGH_AW_0 0x3C6624
+
+#define mmNIF_RTR_CTRL_4_RANGE_SEC_BASE_HIGH_AW_1 0x3C6628
+
+#define mmNIF_RTR_CTRL_4_RANGE_SEC_BASE_HIGH_AW_2 0x3C662C
+
+#define mmNIF_RTR_CTRL_4_RANGE_SEC_BASE_HIGH_AW_3 0x3C6630
+
+#define mmNIF_RTR_CTRL_4_RANGE_SEC_BASE_HIGH_AW_4 0x3C6634
+
+#define mmNIF_RTR_CTRL_4_RANGE_SEC_BASE_HIGH_AW_5 0x3C6638
+
+#define mmNIF_RTR_CTRL_4_RANGE_SEC_BASE_HIGH_AW_6 0x3C663C
+
+#define mmNIF_RTR_CTRL_4_RANGE_SEC_BASE_HIGH_AW_7 0x3C6640
+
+#define mmNIF_RTR_CTRL_4_RANGE_SEC_BASE_HIGH_AW_8 0x3C6644
+
+#define mmNIF_RTR_CTRL_4_RANGE_SEC_BASE_HIGH_AW_9 0x3C6648
+
+#define mmNIF_RTR_CTRL_4_RANGE_SEC_BASE_HIGH_AW_10 0x3C664C
+
+#define mmNIF_RTR_CTRL_4_RANGE_SEC_BASE_HIGH_AW_11 0x3C6650
+
+#define mmNIF_RTR_CTRL_4_RANGE_SEC_BASE_HIGH_AW_12 0x3C6654
+
+#define mmNIF_RTR_CTRL_4_RANGE_SEC_BASE_HIGH_AW_13 0x3C6658
+
+#define mmNIF_RTR_CTRL_4_RANGE_SEC_BASE_HIGH_AW_14 0x3C665C
+
+#define mmNIF_RTR_CTRL_4_RANGE_SEC_BASE_HIGH_AW_15 0x3C6660
+
+#define mmNIF_RTR_CTRL_4_RANGE_SEC_MASK_LOW_AW_0 0x3C6664
+
+#define mmNIF_RTR_CTRL_4_RANGE_SEC_MASK_LOW_AW_1 0x3C6668
+
+#define mmNIF_RTR_CTRL_4_RANGE_SEC_MASK_LOW_AW_2 0x3C666C
+
+#define mmNIF_RTR_CTRL_4_RANGE_SEC_MASK_LOW_AW_3 0x3C6670
+
+#define mmNIF_RTR_CTRL_4_RANGE_SEC_MASK_LOW_AW_4 0x3C6674
+
+#define mmNIF_RTR_CTRL_4_RANGE_SEC_MASK_LOW_AW_5 0x3C6678
+
+#define mmNIF_RTR_CTRL_4_RANGE_SEC_MASK_LOW_AW_6 0x3C667C
+
+#define mmNIF_RTR_CTRL_4_RANGE_SEC_MASK_LOW_AW_7 0x3C6680
+
+#define mmNIF_RTR_CTRL_4_RANGE_SEC_MASK_LOW_AW_8 0x3C6684
+
+#define mmNIF_RTR_CTRL_4_RANGE_SEC_MASK_LOW_AW_9 0x3C6688
+
+#define mmNIF_RTR_CTRL_4_RANGE_SEC_MASK_LOW_AW_10 0x3C668C
+
+#define mmNIF_RTR_CTRL_4_RANGE_SEC_MASK_LOW_AW_11 0x3C6690
+
+#define mmNIF_RTR_CTRL_4_RANGE_SEC_MASK_LOW_AW_12 0x3C6694
+
+#define mmNIF_RTR_CTRL_4_RANGE_SEC_MASK_LOW_AW_13 0x3C6698
+
+#define mmNIF_RTR_CTRL_4_RANGE_SEC_MASK_LOW_AW_14 0x3C669C
+
+#define mmNIF_RTR_CTRL_4_RANGE_SEC_MASK_LOW_AW_15 0x3C66A0
+
+#define mmNIF_RTR_CTRL_4_RANGE_SEC_MASK_HIGH_AW_0 0x3C66A4
+
+#define mmNIF_RTR_CTRL_4_RANGE_SEC_MASK_HIGH_AW_1 0x3C66A8
+
+#define mmNIF_RTR_CTRL_4_RANGE_SEC_MASK_HIGH_AW_2 0x3C66AC
+
+#define mmNIF_RTR_CTRL_4_RANGE_SEC_MASK_HIGH_AW_3 0x3C66B0
+
+#define mmNIF_RTR_CTRL_4_RANGE_SEC_MASK_HIGH_AW_4 0x3C66B4
+
+#define mmNIF_RTR_CTRL_4_RANGE_SEC_MASK_HIGH_AW_5 0x3C66B8
+
+#define mmNIF_RTR_CTRL_4_RANGE_SEC_MASK_HIGH_AW_6 0x3C66BC
+
+#define mmNIF_RTR_CTRL_4_RANGE_SEC_MASK_HIGH_AW_7 0x3C66C0
+
+#define mmNIF_RTR_CTRL_4_RANGE_SEC_MASK_HIGH_AW_8 0x3C66C4
+
+#define mmNIF_RTR_CTRL_4_RANGE_SEC_MASK_HIGH_AW_9 0x3C66C8
+
+#define mmNIF_RTR_CTRL_4_RANGE_SEC_MASK_HIGH_AW_10 0x3C66CC
+
+#define mmNIF_RTR_CTRL_4_RANGE_SEC_MASK_HIGH_AW_11 0x3C66D0
+
+#define mmNIF_RTR_CTRL_4_RANGE_SEC_MASK_HIGH_AW_12 0x3C66D4
+
+#define mmNIF_RTR_CTRL_4_RANGE_SEC_MASK_HIGH_AW_13 0x3C66D8
+
+#define mmNIF_RTR_CTRL_4_RANGE_SEC_MASK_HIGH_AW_14 0x3C66DC
+
+#define mmNIF_RTR_CTRL_4_RANGE_SEC_MASK_HIGH_AW_15 0x3C66E0
+
+#define mmNIF_RTR_CTRL_4_RANGE_PRIV_BASE_LOW_AW_0 0x3C66E4
+
+#define mmNIF_RTR_CTRL_4_RANGE_PRIV_BASE_LOW_AW_1 0x3C66E8
+
+#define mmNIF_RTR_CTRL_4_RANGE_PRIV_BASE_LOW_AW_2 0x3C66EC
+
+#define mmNIF_RTR_CTRL_4_RANGE_PRIV_BASE_LOW_AW_3 0x3C66F0
+
+#define mmNIF_RTR_CTRL_4_RANGE_PRIV_BASE_LOW_AW_4 0x3C66F4
+
+#define mmNIF_RTR_CTRL_4_RANGE_PRIV_BASE_LOW_AW_5 0x3C66F8
+
+#define mmNIF_RTR_CTRL_4_RANGE_PRIV_BASE_LOW_AW_6 0x3C66FC
+
+#define mmNIF_RTR_CTRL_4_RANGE_PRIV_BASE_LOW_AW_7 0x3C6700
+
+#define mmNIF_RTR_CTRL_4_RANGE_PRIV_BASE_LOW_AW_8 0x3C6704
+
+#define mmNIF_RTR_CTRL_4_RANGE_PRIV_BASE_LOW_AW_9 0x3C6708
+
+#define mmNIF_RTR_CTRL_4_RANGE_PRIV_BASE_LOW_AW_10 0x3C670C
+
+#define mmNIF_RTR_CTRL_4_RANGE_PRIV_BASE_LOW_AW_11 0x3C6710
+
+#define mmNIF_RTR_CTRL_4_RANGE_PRIV_BASE_LOW_AW_12 0x3C6714
+
+#define mmNIF_RTR_CTRL_4_RANGE_PRIV_BASE_LOW_AW_13 0x3C6718
+
+#define mmNIF_RTR_CTRL_4_RANGE_PRIV_BASE_LOW_AW_14 0x3C671C
+
+#define mmNIF_RTR_CTRL_4_RANGE_PRIV_BASE_LOW_AW_15 0x3C6720
+
+#define mmNIF_RTR_CTRL_4_RANGE_PRIV_BASE_HIGH_AW_0 0x3C6724
+
+#define mmNIF_RTR_CTRL_4_RANGE_PRIV_BASE_HIGH_AW_1 0x3C6728
+
+#define mmNIF_RTR_CTRL_4_RANGE_PRIV_BASE_HIGH_AW_2 0x3C672C
+
+#define mmNIF_RTR_CTRL_4_RANGE_PRIV_BASE_HIGH_AW_3 0x3C6730
+
+#define mmNIF_RTR_CTRL_4_RANGE_PRIV_BASE_HIGH_AW_4 0x3C6734
+
+#define mmNIF_RTR_CTRL_4_RANGE_PRIV_BASE_HIGH_AW_5 0x3C6738
+
+#define mmNIF_RTR_CTRL_4_RANGE_PRIV_BASE_HIGH_AW_6 0x3C673C
+
+#define mmNIF_RTR_CTRL_4_RANGE_PRIV_BASE_HIGH_AW_7 0x3C6740
+
+#define mmNIF_RTR_CTRL_4_RANGE_PRIV_BASE_HIGH_AW_8 0x3C6744
+
+#define mmNIF_RTR_CTRL_4_RANGE_PRIV_BASE_HIGH_AW_9 0x3C6748
+
+#define mmNIF_RTR_CTRL_4_RANGE_PRIV_BASE_HIGH_AW_10 0x3C674C
+
+#define mmNIF_RTR_CTRL_4_RANGE_PRIV_BASE_HIGH_AW_11 0x3C6750
+
+#define mmNIF_RTR_CTRL_4_RANGE_PRIV_BASE_HIGH_AW_12 0x3C6754
+
+#define mmNIF_RTR_CTRL_4_RANGE_PRIV_BASE_HIGH_AW_13 0x3C6758
+
+#define mmNIF_RTR_CTRL_4_RANGE_PRIV_BASE_HIGH_AW_14 0x3C675C
+
+#define mmNIF_RTR_CTRL_4_RANGE_PRIV_BASE_HIGH_AW_15 0x3C6760
+
+#define mmNIF_RTR_CTRL_4_RANGE_PRIV_MASK_LOW_AW_0 0x3C6764
+
+#define mmNIF_RTR_CTRL_4_RANGE_PRIV_MASK_LOW_AW_1 0x3C6768
+
+#define mmNIF_RTR_CTRL_4_RANGE_PRIV_MASK_LOW_AW_2 0x3C676C
+
+#define mmNIF_RTR_CTRL_4_RANGE_PRIV_MASK_LOW_AW_3 0x3C6770
+
+#define mmNIF_RTR_CTRL_4_RANGE_PRIV_MASK_LOW_AW_4 0x3C6774
+
+#define mmNIF_RTR_CTRL_4_RANGE_PRIV_MASK_LOW_AW_5 0x3C6778
+
+#define mmNIF_RTR_CTRL_4_RANGE_PRIV_MASK_LOW_AW_6 0x3C677C
+
+#define mmNIF_RTR_CTRL_4_RANGE_PRIV_MASK_LOW_AW_7 0x3C6780
+
+#define mmNIF_RTR_CTRL_4_RANGE_PRIV_MASK_LOW_AW_8 0x3C6784
+
+#define mmNIF_RTR_CTRL_4_RANGE_PRIV_MASK_LOW_AW_9 0x3C6788
+
+#define mmNIF_RTR_CTRL_4_RANGE_PRIV_MASK_LOW_AW_10 0x3C678C
+
+#define mmNIF_RTR_CTRL_4_RANGE_PRIV_MASK_LOW_AW_11 0x3C6790
+
+#define mmNIF_RTR_CTRL_4_RANGE_PRIV_MASK_LOW_AW_12 0x3C6794
+
+#define mmNIF_RTR_CTRL_4_RANGE_PRIV_MASK_LOW_AW_13 0x3C6798
+
+#define mmNIF_RTR_CTRL_4_RANGE_PRIV_MASK_LOW_AW_14 0x3C679C
+
+#define mmNIF_RTR_CTRL_4_RANGE_PRIV_MASK_LOW_AW_15 0x3C67A0
+
+#define mmNIF_RTR_CTRL_4_RANGE_PRIV_MASK_HIGH_AW_0 0x3C67A4
+
+#define mmNIF_RTR_CTRL_4_RANGE_PRIV_MASK_HIGH_AW_1 0x3C67A8
+
+#define mmNIF_RTR_CTRL_4_RANGE_PRIV_MASK_HIGH_AW_2 0x3C67AC
+
+#define mmNIF_RTR_CTRL_4_RANGE_PRIV_MASK_HIGH_AW_3 0x3C67B0
+
+#define mmNIF_RTR_CTRL_4_RANGE_PRIV_MASK_HIGH_AW_4 0x3C67B4
+
+#define mmNIF_RTR_CTRL_4_RANGE_PRIV_MASK_HIGH_AW_5 0x3C67B8
+
+#define mmNIF_RTR_CTRL_4_RANGE_PRIV_MASK_HIGH_AW_6 0x3C67BC
+
+#define mmNIF_RTR_CTRL_4_RANGE_PRIV_MASK_HIGH_AW_7 0x3C67C0
+
+#define mmNIF_RTR_CTRL_4_RANGE_PRIV_MASK_HIGH_AW_8 0x3C67C4
+
+#define mmNIF_RTR_CTRL_4_RANGE_PRIV_MASK_HIGH_AW_9 0x3C67C8
+
+#define mmNIF_RTR_CTRL_4_RANGE_PRIV_MASK_HIGH_AW_10 0x3C67CC
+
+#define mmNIF_RTR_CTRL_4_RANGE_PRIV_MASK_HIGH_AW_11 0x3C67D0
+
+#define mmNIF_RTR_CTRL_4_RANGE_PRIV_MASK_HIGH_AW_12 0x3C67D4
+
+#define mmNIF_RTR_CTRL_4_RANGE_PRIV_MASK_HIGH_AW_13 0x3C67D8
+
+#define mmNIF_RTR_CTRL_4_RANGE_PRIV_MASK_HIGH_AW_14 0x3C67DC
+
+#define mmNIF_RTR_CTRL_4_RANGE_PRIV_MASK_HIGH_AW_15 0x3C67E0
+
+#define mmNIF_RTR_CTRL_4_RANGE_SEC_BASE_LOW_AR_0 0x3C6824
+
+#define mmNIF_RTR_CTRL_4_RANGE_SEC_BASE_LOW_AR_1 0x3C6828
+
+#define mmNIF_RTR_CTRL_4_RANGE_SEC_BASE_LOW_AR_2 0x3C682C
+
+#define mmNIF_RTR_CTRL_4_RANGE_SEC_BASE_LOW_AR_3 0x3C6830
+
+#define mmNIF_RTR_CTRL_4_RANGE_SEC_BASE_LOW_AR_4 0x3C6834
+
+#define mmNIF_RTR_CTRL_4_RANGE_SEC_BASE_LOW_AR_5 0x3C6838
+
+#define mmNIF_RTR_CTRL_4_RANGE_SEC_BASE_LOW_AR_6 0x3C683C
+
+#define mmNIF_RTR_CTRL_4_RANGE_SEC_BASE_LOW_AR_7 0x3C6840
+
+#define mmNIF_RTR_CTRL_4_RANGE_SEC_BASE_LOW_AR_8 0x3C6844
+
+#define mmNIF_RTR_CTRL_4_RANGE_SEC_BASE_LOW_AR_9 0x3C6848
+
+#define mmNIF_RTR_CTRL_4_RANGE_SEC_BASE_LOW_AR_10 0x3C684C
+
+#define mmNIF_RTR_CTRL_4_RANGE_SEC_BASE_LOW_AR_11 0x3C6850
+
+#define mmNIF_RTR_CTRL_4_RANGE_SEC_BASE_LOW_AR_12 0x3C6854
+
+#define mmNIF_RTR_CTRL_4_RANGE_SEC_BASE_LOW_AR_13 0x3C6858
+
+#define mmNIF_RTR_CTRL_4_RANGE_SEC_BASE_LOW_AR_14 0x3C685C
+
+#define mmNIF_RTR_CTRL_4_RANGE_SEC_BASE_LOW_AR_15 0x3C6860
+
+#define mmNIF_RTR_CTRL_4_RANGE_SEC_BASE_HIGH_AR_0 0x3C6864
+
+#define mmNIF_RTR_CTRL_4_RANGE_SEC_BASE_HIGH_AR_1 0x3C6868
+
+#define mmNIF_RTR_CTRL_4_RANGE_SEC_BASE_HIGH_AR_2 0x3C686C
+
+#define mmNIF_RTR_CTRL_4_RANGE_SEC_BASE_HIGH_AR_3 0x3C6870
+
+#define mmNIF_RTR_CTRL_4_RANGE_SEC_BASE_HIGH_AR_4 0x3C6874
+
+#define mmNIF_RTR_CTRL_4_RANGE_SEC_BASE_HIGH_AR_5 0x3C6878
+
+#define mmNIF_RTR_CTRL_4_RANGE_SEC_BASE_HIGH_AR_6 0x3C687C
+
+#define mmNIF_RTR_CTRL_4_RANGE_SEC_BASE_HIGH_AR_7 0x3C6880
+
+#define mmNIF_RTR_CTRL_4_RANGE_SEC_BASE_HIGH_AR_8 0x3C6884
+
+#define mmNIF_RTR_CTRL_4_RANGE_SEC_BASE_HIGH_AR_9 0x3C6888
+
+#define mmNIF_RTR_CTRL_4_RANGE_SEC_BASE_HIGH_AR_10 0x3C688C
+
+#define mmNIF_RTR_CTRL_4_RANGE_SEC_BASE_HIGH_AR_11 0x3C6890
+
+#define mmNIF_RTR_CTRL_4_RANGE_SEC_BASE_HIGH_AR_12 0x3C6894
+
+#define mmNIF_RTR_CTRL_4_RANGE_SEC_BASE_HIGH_AR_13 0x3C6898
+
+#define mmNIF_RTR_CTRL_4_RANGE_SEC_BASE_HIGH_AR_14 0x3C689C
+
+#define mmNIF_RTR_CTRL_4_RANGE_SEC_BASE_HIGH_AR_15 0x3C68A0
+
+#define mmNIF_RTR_CTRL_4_RANGE_SEC_MASK_LOW_AR_0 0x3C68A4
+
+#define mmNIF_RTR_CTRL_4_RANGE_SEC_MASK_LOW_AR_1 0x3C68A8
+
+#define mmNIF_RTR_CTRL_4_RANGE_SEC_MASK_LOW_AR_2 0x3C68AC
+
+#define mmNIF_RTR_CTRL_4_RANGE_SEC_MASK_LOW_AR_3 0x3C68B0
+
+#define mmNIF_RTR_CTRL_4_RANGE_SEC_MASK_LOW_AR_4 0x3C68B4
+
+#define mmNIF_RTR_CTRL_4_RANGE_SEC_MASK_LOW_AR_5 0x3C68B8
+
+#define mmNIF_RTR_CTRL_4_RANGE_SEC_MASK_LOW_AR_6 0x3C68BC
+
+#define mmNIF_RTR_CTRL_4_RANGE_SEC_MASK_LOW_AR_7 0x3C68C0
+
+#define mmNIF_RTR_CTRL_4_RANGE_SEC_MASK_LOW_AR_8 0x3C68C4
+
+#define mmNIF_RTR_CTRL_4_RANGE_SEC_MASK_LOW_AR_9 0x3C68C8
+
+#define mmNIF_RTR_CTRL_4_RANGE_SEC_MASK_LOW_AR_10 0x3C68CC
+
+#define mmNIF_RTR_CTRL_4_RANGE_SEC_MASK_LOW_AR_11 0x3C68D0
+
+#define mmNIF_RTR_CTRL_4_RANGE_SEC_MASK_LOW_AR_12 0x3C68D4
+
+#define mmNIF_RTR_CTRL_4_RANGE_SEC_MASK_LOW_AR_13 0x3C68D8
+
+#define mmNIF_RTR_CTRL_4_RANGE_SEC_MASK_LOW_AR_14 0x3C68DC
+
+#define mmNIF_RTR_CTRL_4_RANGE_SEC_MASK_LOW_AR_15 0x3C68E0
+
+#define mmNIF_RTR_CTRL_4_RANGE_SEC_MASK_HIGH_AR_0 0x3C68E4
+
+#define mmNIF_RTR_CTRL_4_RANGE_SEC_MASK_HIGH_AR_1 0x3C68E8
+
+#define mmNIF_RTR_CTRL_4_RANGE_SEC_MASK_HIGH_AR_2 0x3C68EC
+
+#define mmNIF_RTR_CTRL_4_RANGE_SEC_MASK_HIGH_AR_3 0x3C68F0
+
+#define mmNIF_RTR_CTRL_4_RANGE_SEC_MASK_HIGH_AR_4 0x3C68F4
+
+#define mmNIF_RTR_CTRL_4_RANGE_SEC_MASK_HIGH_AR_5 0x3C68F8
+
+#define mmNIF_RTR_CTRL_4_RANGE_SEC_MASK_HIGH_AR_6 0x3C68FC
+
+#define mmNIF_RTR_CTRL_4_RANGE_SEC_MASK_HIGH_AR_7 0x3C6900
+
+#define mmNIF_RTR_CTRL_4_RANGE_SEC_MASK_HIGH_AR_8 0x3C6904
+
+#define mmNIF_RTR_CTRL_4_RANGE_SEC_MASK_HIGH_AR_9 0x3C6908
+
+#define mmNIF_RTR_CTRL_4_RANGE_SEC_MASK_HIGH_AR_10 0x3C690C
+
+#define mmNIF_RTR_CTRL_4_RANGE_SEC_MASK_HIGH_AR_11 0x3C6910
+
+#define mmNIF_RTR_CTRL_4_RANGE_SEC_MASK_HIGH_AR_12 0x3C6914
+
+#define mmNIF_RTR_CTRL_4_RANGE_SEC_MASK_HIGH_AR_13 0x3C6918
+
+#define mmNIF_RTR_CTRL_4_RANGE_SEC_MASK_HIGH_AR_14 0x3C691C
+
+#define mmNIF_RTR_CTRL_4_RANGE_SEC_MASK_HIGH_AR_15 0x3C6920
+
+#define mmNIF_RTR_CTRL_4_RANGE_PRIV_BASE_LOW_AR_0 0x3C6924
+
+#define mmNIF_RTR_CTRL_4_RANGE_PRIV_BASE_LOW_AR_1 0x3C6928
+
+#define mmNIF_RTR_CTRL_4_RANGE_PRIV_BASE_LOW_AR_2 0x3C692C
+
+#define mmNIF_RTR_CTRL_4_RANGE_PRIV_BASE_LOW_AR_3 0x3C6930
+
+#define mmNIF_RTR_CTRL_4_RANGE_PRIV_BASE_LOW_AR_4 0x3C6934
+
+#define mmNIF_RTR_CTRL_4_RANGE_PRIV_BASE_LOW_AR_5 0x3C6938
+
+#define mmNIF_RTR_CTRL_4_RANGE_PRIV_BASE_LOW_AR_6 0x3C693C
+
+#define mmNIF_RTR_CTRL_4_RANGE_PRIV_BASE_LOW_AR_7 0x3C6940
+
+#define mmNIF_RTR_CTRL_4_RANGE_PRIV_BASE_LOW_AR_8 0x3C6944
+
+#define mmNIF_RTR_CTRL_4_RANGE_PRIV_BASE_LOW_AR_9 0x3C6948
+
+#define mmNIF_RTR_CTRL_4_RANGE_PRIV_BASE_LOW_AR_10 0x3C694C
+
+#define mmNIF_RTR_CTRL_4_RANGE_PRIV_BASE_LOW_AR_11 0x3C6950
+
+#define mmNIF_RTR_CTRL_4_RANGE_PRIV_BASE_LOW_AR_12 0x3C6954
+
+#define mmNIF_RTR_CTRL_4_RANGE_PRIV_BASE_LOW_AR_13 0x3C6958
+
+#define mmNIF_RTR_CTRL_4_RANGE_PRIV_BASE_LOW_AR_14 0x3C695C
+
+#define mmNIF_RTR_CTRL_4_RANGE_PRIV_BASE_LOW_AR_15 0x3C6960
+
+#define mmNIF_RTR_CTRL_4_RANGE_PRIV_BASE_HIGH_AR_0 0x3C6964
+
+#define mmNIF_RTR_CTRL_4_RANGE_PRIV_BASE_HIGH_AR_1 0x3C6968
+
+#define mmNIF_RTR_CTRL_4_RANGE_PRIV_BASE_HIGH_AR_2 0x3C696C
+
+#define mmNIF_RTR_CTRL_4_RANGE_PRIV_BASE_HIGH_AR_3 0x3C6970
+
+#define mmNIF_RTR_CTRL_4_RANGE_PRIV_BASE_HIGH_AR_4 0x3C6974
+
+#define mmNIF_RTR_CTRL_4_RANGE_PRIV_BASE_HIGH_AR_5 0x3C6978
+
+#define mmNIF_RTR_CTRL_4_RANGE_PRIV_BASE_HIGH_AR_6 0x3C697C
+
+#define mmNIF_RTR_CTRL_4_RANGE_PRIV_BASE_HIGH_AR_7 0x3C6980
+
+#define mmNIF_RTR_CTRL_4_RANGE_PRIV_BASE_HIGH_AR_8 0x3C6984
+
+#define mmNIF_RTR_CTRL_4_RANGE_PRIV_BASE_HIGH_AR_9 0x3C6988
+
+#define mmNIF_RTR_CTRL_4_RANGE_PRIV_BASE_HIGH_AR_10 0x3C698C
+
+#define mmNIF_RTR_CTRL_4_RANGE_PRIV_BASE_HIGH_AR_11 0x3C6990
+
+#define mmNIF_RTR_CTRL_4_RANGE_PRIV_BASE_HIGH_AR_12 0x3C6994
+
+#define mmNIF_RTR_CTRL_4_RANGE_PRIV_BASE_HIGH_AR_13 0x3C6998
+
+#define mmNIF_RTR_CTRL_4_RANGE_PRIV_BASE_HIGH_AR_14 0x3C699C
+
+#define mmNIF_RTR_CTRL_4_RANGE_PRIV_BASE_HIGH_AR_15 0x3C69A0
+
+#define mmNIF_RTR_CTRL_4_RANGE_PRIV_MASK_LOW_AR_0 0x3C69A4
+
+#define mmNIF_RTR_CTRL_4_RANGE_PRIV_MASK_LOW_AR_1 0x3C69A8
+
+#define mmNIF_RTR_CTRL_4_RANGE_PRIV_MASK_LOW_AR_2 0x3C69AC
+
+#define mmNIF_RTR_CTRL_4_RANGE_PRIV_MASK_LOW_AR_3 0x3C69B0
+
+#define mmNIF_RTR_CTRL_4_RANGE_PRIV_MASK_LOW_AR_4 0x3C69B4
+
+#define mmNIF_RTR_CTRL_4_RANGE_PRIV_MASK_LOW_AR_5 0x3C69B8
+
+#define mmNIF_RTR_CTRL_4_RANGE_PRIV_MASK_LOW_AR_6 0x3C69BC
+
+#define mmNIF_RTR_CTRL_4_RANGE_PRIV_MASK_LOW_AR_7 0x3C69C0
+
+#define mmNIF_RTR_CTRL_4_RANGE_PRIV_MASK_LOW_AR_8 0x3C69C4
+
+#define mmNIF_RTR_CTRL_4_RANGE_PRIV_MASK_LOW_AR_9 0x3C69C8
+
+#define mmNIF_RTR_CTRL_4_RANGE_PRIV_MASK_LOW_AR_10 0x3C69CC
+
+#define mmNIF_RTR_CTRL_4_RANGE_PRIV_MASK_LOW_AR_11 0x3C69D0
+
+#define mmNIF_RTR_CTRL_4_RANGE_PRIV_MASK_LOW_AR_12 0x3C69D4
+
+#define mmNIF_RTR_CTRL_4_RANGE_PRIV_MASK_LOW_AR_13 0x3C69D8
+
+#define mmNIF_RTR_CTRL_4_RANGE_PRIV_MASK_LOW_AR_14 0x3C69DC
+
+#define mmNIF_RTR_CTRL_4_RANGE_PRIV_MASK_LOW_AR_15 0x3C69E0
+
+#define mmNIF_RTR_CTRL_4_RANGE_PRIV_MASK_HIGH_AR_0 0x3C69E4
+
+#define mmNIF_RTR_CTRL_4_RANGE_PRIV_MASK_HIGH_AR_1 0x3C69E8
+
+#define mmNIF_RTR_CTRL_4_RANGE_PRIV_MASK_HIGH_AR_2 0x3C69EC
+
+#define mmNIF_RTR_CTRL_4_RANGE_PRIV_MASK_HIGH_AR_3 0x3C69F0
+
+#define mmNIF_RTR_CTRL_4_RANGE_PRIV_MASK_HIGH_AR_4 0x3C69F4
+
+#define mmNIF_RTR_CTRL_4_RANGE_PRIV_MASK_HIGH_AR_5 0x3C69F8
+
+#define mmNIF_RTR_CTRL_4_RANGE_PRIV_MASK_HIGH_AR_6 0x3C69FC
+
+#define mmNIF_RTR_CTRL_4_RANGE_PRIV_MASK_HIGH_AR_7 0x3C6A00
+
+#define mmNIF_RTR_CTRL_4_RANGE_PRIV_MASK_HIGH_AR_8 0x3C6A04
+
+#define mmNIF_RTR_CTRL_4_RANGE_PRIV_MASK_HIGH_AR_9 0x3C6A08
+
+#define mmNIF_RTR_CTRL_4_RANGE_PRIV_MASK_HIGH_AR_10 0x3C6A0C
+
+#define mmNIF_RTR_CTRL_4_RANGE_PRIV_MASK_HIGH_AR_11 0x3C6A10
+
+#define mmNIF_RTR_CTRL_4_RANGE_PRIV_MASK_HIGH_AR_12 0x3C6A14
+
+#define mmNIF_RTR_CTRL_4_RANGE_PRIV_MASK_HIGH_AR_13 0x3C6A18
+
+#define mmNIF_RTR_CTRL_4_RANGE_PRIV_MASK_HIGH_AR_14 0x3C6A1C
+
+#define mmNIF_RTR_CTRL_4_RANGE_PRIV_MASK_HIGH_AR_15 0x3C6A20
+
+#define mmNIF_RTR_CTRL_4_RANGE_SEC_HIT_AW 0x3C6A64
+
+#define mmNIF_RTR_CTRL_4_RANGE_SEC_HIT_AR 0x3C6A68
+
+#define mmNIF_RTR_CTRL_4_RANGE_PRIV_HIT_AW 0x3C6A6C
+
+#define mmNIF_RTR_CTRL_4_RANGE_PRIV_HIT_AR 0x3C6A70
+
+#define mmNIF_RTR_CTRL_4_RGL_CFG 0x3C6B64
+
+#define mmNIF_RTR_CTRL_4_RGL_SHIFT 0x3C6B68
+
+#define mmNIF_RTR_CTRL_4_RGL_EXPECTED_LAT_0 0x3C6B6C
+
+#define mmNIF_RTR_CTRL_4_RGL_EXPECTED_LAT_1 0x3C6B70
+
+#define mmNIF_RTR_CTRL_4_RGL_EXPECTED_LAT_2 0x3C6B74
+
+#define mmNIF_RTR_CTRL_4_RGL_EXPECTED_LAT_3 0x3C6B78
+
+#define mmNIF_RTR_CTRL_4_RGL_EXPECTED_LAT_4 0x3C6B7C
+
+#define mmNIF_RTR_CTRL_4_RGL_EXPECTED_LAT_5 0x3C6B80
+
+#define mmNIF_RTR_CTRL_4_RGL_EXPECTED_LAT_6 0x3C6B84
+
+#define mmNIF_RTR_CTRL_4_RGL_EXPECTED_LAT_7 0x3C6B88
+
+#define mmNIF_RTR_CTRL_4_RGL_TOKEN_0 0x3C6BAC
+
+#define mmNIF_RTR_CTRL_4_RGL_TOKEN_1 0x3C6BB0
+
+#define mmNIF_RTR_CTRL_4_RGL_TOKEN_2 0x3C6BB4
+
+#define mmNIF_RTR_CTRL_4_RGL_TOKEN_3 0x3C6BB8
+
+#define mmNIF_RTR_CTRL_4_RGL_TOKEN_4 0x3C6BBC
+
+#define mmNIF_RTR_CTRL_4_RGL_TOKEN_5 0x3C6BC0
+
+#define mmNIF_RTR_CTRL_4_RGL_TOKEN_6 0x3C6BC4
+
+#define mmNIF_RTR_CTRL_4_RGL_TOKEN_7 0x3C6BC8
+
+#define mmNIF_RTR_CTRL_4_RGL_BANK_ID_0 0x3C6BEC
+
+#define mmNIF_RTR_CTRL_4_RGL_BANK_ID_1 0x3C6BF0
+
+#define mmNIF_RTR_CTRL_4_RGL_BANK_ID_2 0x3C6BF4
+
+#define mmNIF_RTR_CTRL_4_RGL_BANK_ID_3 0x3C6BF8
+
+#define mmNIF_RTR_CTRL_4_RGL_BANK_ID_4 0x3C6BFC
+
+#define mmNIF_RTR_CTRL_4_RGL_BANK_ID_5 0x3C6C00
+
+#define mmNIF_RTR_CTRL_4_RGL_BANK_ID_6 0x3C6C04
+
+#define mmNIF_RTR_CTRL_4_RGL_BANK_ID_7 0x3C6C08
+
+#define mmNIF_RTR_CTRL_4_RGL_WDT 0x3C6C2C
+
+#define mmNIF_RTR_CTRL_4_E2E_AR_HBM0_CH0_CTR_WRAP 0x3C6C30
+
+#define mmNIF_RTR_CTRL_4_E2E_AR_HBM0_CH1_CTR_WRAP 0x3C6C34
+
+#define mmNIF_RTR_CTRL_4_E2E_AR_HBM1_CH0_CTR_WRAP 0x3C6C38
+
+#define mmNIF_RTR_CTRL_4_E2E_AR_HBM1_CH1_CTR_WRAP 0x3C6C3C
+
+#define mmNIF_RTR_CTRL_4_E2E_AR_HBM2_CH0_CTR_WRAP 0x3C6C40
+
+#define mmNIF_RTR_CTRL_4_E2E_AR_HBM2_CH1_CTR_WRAP 0x3C6C44
+
+#define mmNIF_RTR_CTRL_4_E2E_AR_HBM3_CH0_CTR_WRAP 0x3C6C48
+
+#define mmNIF_RTR_CTRL_4_E2E_AR_HBM3_CH1_CTR_WRAP 0x3C6C4C
+
+#define mmNIF_RTR_CTRL_4_E2E_AR_HBM0_CH0_CTR_CNT 0x3C6C50
+
+#define mmNIF_RTR_CTRL_4_E2E_AR_HBM0_CH1_CTR_CNT 0x3C6C54
+
+#define mmNIF_RTR_CTRL_4_E2E_AR_HBM1_CH0_CTR_CNT 0x3C6C58
+
+#define mmNIF_RTR_CTRL_4_E2E_AR_HBM1_CH1_CTR_CNT 0x3C6C5C
+
+#define mmNIF_RTR_CTRL_4_E2E_AR_HBM2_CH0_CTR_CNT 0x3C6C60
+
+#define mmNIF_RTR_CTRL_4_E2E_AR_HBM2_CH1_CTR_CNT 0x3C6C64
+
+#define mmNIF_RTR_CTRL_4_E2E_AR_HBM3_CH0_CTR_CNT 0x3C6C68
+
+#define mmNIF_RTR_CTRL_4_E2E_AR_HBM3_CH1_CTR_CNT 0x3C6C6C
+
+#define mmNIF_RTR_CTRL_4_E2E_AW_HBM0_CH0_CTR_WRAP 0x3C6C70
+
+#define mmNIF_RTR_CTRL_4_E2E_AW_HBM0_CH1_CTR_WRAP 0x3C6C74
+
+#define mmNIF_RTR_CTRL_4_E2E_AW_HBM1_CH0_CTR_WRAP 0x3C6C78
+
+#define mmNIF_RTR_CTRL_4_E2E_AW_HBM1_CH1_CTR_WRAP 0x3C6C7C
+
+#define mmNIF_RTR_CTRL_4_E2E_AW_HBM2_CH0_CTR_WRAP 0x3C6C80
+
+#define mmNIF_RTR_CTRL_4_E2E_AW_HBM2_CH1_CTR_WRAP 0x3C6C84
+
+#define mmNIF_RTR_CTRL_4_E2E_AW_HBM3_CH0_CTR_WRAP 0x3C6C88
+
+#define mmNIF_RTR_CTRL_4_E2E_AW_HBM3_CH1_CTR_WRAP 0x3C6C8C
+
+#define mmNIF_RTR_CTRL_4_E2E_AW_HBM0_CH0_CTR_CNT 0x3C6C90
+
+#define mmNIF_RTR_CTRL_4_E2E_AW_HBM0_CH1_CTR_CNT 0x3C6C94
+
+#define mmNIF_RTR_CTRL_4_E2E_AW_HBM1_CH0_CTR_CNT 0x3C6C98
+
+#define mmNIF_RTR_CTRL_4_E2E_AW_HBM1_CH1_CTR_CNT 0x3C6C9C
+
+#define mmNIF_RTR_CTRL_4_E2E_AW_HBM2_CH0_CTR_CNT 0x3C6CA0
+
+#define mmNIF_RTR_CTRL_4_E2E_AW_HBM2_CH1_CTR_CNT 0x3C6CA4
+
+#define mmNIF_RTR_CTRL_4_E2E_AW_HBM3_CH0_CTR_CNT 0x3C6CA8
+
+#define mmNIF_RTR_CTRL_4_E2E_AW_HBM3_CH1_CTR_CNT 0x3C6CAC
+
+#define mmNIF_RTR_CTRL_4_NL_HBM_PC_SEL_0 0x3C6CB0
+
+#define mmNIF_RTR_CTRL_4_NL_HBM_PC_SEL_1 0x3C6CB4
+
+#define mmNIF_RTR_CTRL_4_NL_HBM_PC_SEL_2 0x3C6CB8
+
+#define mmNIF_RTR_CTRL_4_NL_HBM_PC_SEL_3 0x3C6CBC
+
+#endif /* ASIC_REG_NIF_RTR_CTRL_4_REGS_H_ */
diff --git a/drivers/accel/habanalabs/include/gaudi/asic_reg/nif_rtr_ctrl_5_regs.h b/drivers/accel/habanalabs/include/gaudi/asic_reg/nif_rtr_ctrl_5_regs.h
new file mode 100644
index 0000000000..95486b7ddf
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi/asic_reg/nif_rtr_ctrl_5_regs.h
@@ -0,0 +1,896 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2016-2018 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ ** DO NOT EDIT BELOW **
+ ************************************/
+
+#ifndef ASIC_REG_NIF_RTR_CTRL_5_REGS_H_
+#define ASIC_REG_NIF_RTR_CTRL_5_REGS_H_
+
+/*
+ *****************************************
+ * NIF_RTR_CTRL_5 (Prototype: RTR_CTRL)
+ *****************************************
+ */
+
+#define mmNIF_RTR_CTRL_5_PERM_SEL 0x3D6108
+
+#define mmNIF_RTR_CTRL_5_HBM_POLY_H3_0 0x3D6114
+
+#define mmNIF_RTR_CTRL_5_HBM_POLY_H3_1 0x3D6118
+
+#define mmNIF_RTR_CTRL_5_HBM_POLY_H3_2 0x3D611C
+
+#define mmNIF_RTR_CTRL_5_HBM_POLY_H3_3 0x3D6120
+
+#define mmNIF_RTR_CTRL_5_HBM_POLY_H3_4 0x3D6124
+
+#define mmNIF_RTR_CTRL_5_HBM_POLY_H3_5 0x3D6128
+
+#define mmNIF_RTR_CTRL_5_HBM_POLY_H3_6 0x3D612C
+
+#define mmNIF_RTR_CTRL_5_HBM_POLY_H3_7 0x3D6130
+
+#define mmNIF_RTR_CTRL_5_HBM_POLY_H3_8 0x3D6134
+
+#define mmNIF_RTR_CTRL_5_HBM_POLY_H3_9 0x3D6138
+
+#define mmNIF_RTR_CTRL_5_HBM_POLY_H3_10 0x3D613C
+
+#define mmNIF_RTR_CTRL_5_HBM_POLY_H3_11 0x3D6140
+
+#define mmNIF_RTR_CTRL_5_HBM_POLY_H3_12 0x3D6144
+
+#define mmNIF_RTR_CTRL_5_HBM_POLY_H3_13 0x3D6148
+
+#define mmNIF_RTR_CTRL_5_HBM_POLY_H3_14 0x3D614C
+
+#define mmNIF_RTR_CTRL_5_HBM_POLY_H3_15 0x3D6150
+
+#define mmNIF_RTR_CTRL_5_HBM_POLY_H3_16 0x3D6154
+
+#define mmNIF_RTR_CTRL_5_HBM_POLY_H3_17 0x3D6158
+
+#define mmNIF_RTR_CTRL_5_HBM_POLY_H3_18 0x3D615C
+
+#define mmNIF_RTR_CTRL_5_HBM_POLY_H3_19 0x3D6160
+
+#define mmNIF_RTR_CTRL_5_HBM_POLY_H3_20 0x3D6164
+
+#define mmNIF_RTR_CTRL_5_HBM_POLY_H3_21 0x3D6168
+
+#define mmNIF_RTR_CTRL_5_HBM_POLY_H3_22 0x3D616C
+
+#define mmNIF_RTR_CTRL_5_HBM_POLY_H3_23 0x3D6170
+
+#define mmNIF_RTR_CTRL_5_HBM_POLY_H3_24 0x3D6174
+
+#define mmNIF_RTR_CTRL_5_HBM_POLY_H3_25 0x3D6178
+
+#define mmNIF_RTR_CTRL_5_HBM_POLY_H3_26 0x3D617C
+
+#define mmNIF_RTR_CTRL_5_HBM_POLY_H3_27 0x3D6180
+
+#define mmNIF_RTR_CTRL_5_SRAM_POLY_H3_0 0x3D6184
+
+#define mmNIF_RTR_CTRL_5_SRAM_POLY_H3_1 0x3D6188
+
+#define mmNIF_RTR_CTRL_5_SRAM_POLY_H3_2 0x3D618C
+
+#define mmNIF_RTR_CTRL_5_SRAM_POLY_H3_3 0x3D6190
+
+#define mmNIF_RTR_CTRL_5_SRAM_POLY_H3_4 0x3D6194
+
+#define mmNIF_RTR_CTRL_5_SRAM_POLY_H3_5 0x3D6198
+
+#define mmNIF_RTR_CTRL_5_SRAM_POLY_H3_6 0x3D619C
+
+#define mmNIF_RTR_CTRL_5_SRAM_POLY_H3_7 0x3D61A0
+
+#define mmNIF_RTR_CTRL_5_SRAM_POLY_H3_8 0x3D61A4
+
+#define mmNIF_RTR_CTRL_5_SRAM_POLY_H3_9 0x3D61A8
+
+#define mmNIF_RTR_CTRL_5_SRAM_POLY_H3_10 0x3D61AC
+
+#define mmNIF_RTR_CTRL_5_SRAM_POLY_H3_11 0x3D61B0
+
+#define mmNIF_RTR_CTRL_5_SRAM_POLY_H3_12 0x3D61B4
+
+#define mmNIF_RTR_CTRL_5_SRAM_POLY_H3_13 0x3D61B8
+
+#define mmNIF_RTR_CTRL_5_SRAM_POLY_H3_14 0x3D61BC
+
+#define mmNIF_RTR_CTRL_5_SCRAM_SRAM_EN 0x3D626C
+
+#define mmNIF_RTR_CTRL_5_RL_HBM_EN 0x3D6274
+
+#define mmNIF_RTR_CTRL_5_RL_HBM_SAT 0x3D6278
+
+#define mmNIF_RTR_CTRL_5_RL_HBM_RST 0x3D627C
+
+#define mmNIF_RTR_CTRL_5_RL_HBM_TIMEOUT 0x3D6280
+
+#define mmNIF_RTR_CTRL_5_SCRAM_HBM_EN 0x3D6284
+
+#define mmNIF_RTR_CTRL_5_RL_PCI_EN 0x3D6288
+
+#define mmNIF_RTR_CTRL_5_RL_PCI_SAT 0x3D628C
+
+#define mmNIF_RTR_CTRL_5_RL_PCI_RST 0x3D6290
+
+#define mmNIF_RTR_CTRL_5_RL_PCI_TIMEOUT 0x3D6294
+
+#define mmNIF_RTR_CTRL_5_RL_SRAM_EN 0x3D629C
+
+#define mmNIF_RTR_CTRL_5_RL_SRAM_SAT 0x3D62A0
+
+#define mmNIF_RTR_CTRL_5_RL_SRAM_RST 0x3D62A4
+
+#define mmNIF_RTR_CTRL_5_RL_SRAM_TIMEOUT 0x3D62AC
+
+#define mmNIF_RTR_CTRL_5_RL_SRAM_RED 0x3D62B4
+
+#define mmNIF_RTR_CTRL_5_E2E_HBM_EN 0x3D62EC
+
+#define mmNIF_RTR_CTRL_5_E2E_PCI_EN 0x3D62F0
+
+#define mmNIF_RTR_CTRL_5_E2E_HBM_WR_SIZE 0x3D62F4
+
+#define mmNIF_RTR_CTRL_5_E2E_PCI_WR_SIZE 0x3D62F8
+
+#define mmNIF_RTR_CTRL_5_E2E_AW_PCI_CTR_SET_EN 0x3D6404
+
+#define mmNIF_RTR_CTRL_5_E2E_AW_PCI_CTR_SET 0x3D6408
+
+#define mmNIF_RTR_CTRL_5_E2E_AW_PCI_CTR_WRAP 0x3D640C
+
+#define mmNIF_RTR_CTRL_5_E2E_AW_PCI_CTR_CNT 0x3D6410
+
+#define mmNIF_RTR_CTRL_5_E2E_AW_HBM_CTR_SET_EN 0x3D6414
+
+#define mmNIF_RTR_CTRL_5_E2E_AW_HBM_CTR_SET 0x3D6418
+
+#define mmNIF_RTR_CTRL_5_E2E_HBM_RD_SIZE 0x3D641C
+
+#define mmNIF_RTR_CTRL_5_E2E_PCI_RD_SIZE 0x3D6420
+
+#define mmNIF_RTR_CTRL_5_E2E_AR_PCI_CTR_SET_EN 0x3D6424
+
+#define mmNIF_RTR_CTRL_5_E2E_AR_PCI_CTR_SET 0x3D6428
+
+#define mmNIF_RTR_CTRL_5_E2E_AR_PCI_CTR_WRAP 0x3D642C
+
+#define mmNIF_RTR_CTRL_5_E2E_AR_PCI_CTR_CNT 0x3D6430
+
+#define mmNIF_RTR_CTRL_5_E2E_AR_HBM_CTR_SET_EN 0x3D6434
+
+#define mmNIF_RTR_CTRL_5_E2E_AR_HBM_CTR_SET 0x3D6438
+
+#define mmNIF_RTR_CTRL_5_NL_HBM_SEL_0 0x3D6450
+
+#define mmNIF_RTR_CTRL_5_NL_HBM_SEL_1 0x3D6454
+
+#define mmNIF_RTR_CTRL_5_NON_LIN_EN 0x3D6480
+
+#define mmNIF_RTR_CTRL_5_NL_SRAM_BANK_0 0x3D6500
+
+#define mmNIF_RTR_CTRL_5_NL_SRAM_BANK_1 0x3D6504
+
+#define mmNIF_RTR_CTRL_5_NL_SRAM_BANK_2 0x3D6508
+
+#define mmNIF_RTR_CTRL_5_NL_SRAM_BANK_3 0x3D650C
+
+#define mmNIF_RTR_CTRL_5_NL_SRAM_BANK_4 0x3D6510
+
+#define mmNIF_RTR_CTRL_5_NL_SRAM_OFFSET_0 0x3D6514
+
+#define mmNIF_RTR_CTRL_5_NL_SRAM_OFFSET_1 0x3D6520
+
+#define mmNIF_RTR_CTRL_5_NL_SRAM_OFFSET_2 0x3D6524
+
+#define mmNIF_RTR_CTRL_5_NL_SRAM_OFFSET_3 0x3D6528
+
+#define mmNIF_RTR_CTRL_5_NL_SRAM_OFFSET_4 0x3D652C
+
+#define mmNIF_RTR_CTRL_5_NL_SRAM_OFFSET_5 0x3D6530
+
+#define mmNIF_RTR_CTRL_5_NL_SRAM_OFFSET_6 0x3D6534
+
+#define mmNIF_RTR_CTRL_5_NL_SRAM_OFFSET_7 0x3D6538
+
+#define mmNIF_RTR_CTRL_5_NL_SRAM_OFFSET_8 0x3D653C
+
+#define mmNIF_RTR_CTRL_5_NL_SRAM_OFFSET_9 0x3D6540
+
+#define mmNIF_RTR_CTRL_5_NL_HBM_OFFSET_0 0x3D6550
+
+#define mmNIF_RTR_CTRL_5_NL_HBM_OFFSET_1 0x3D6554
+
+#define mmNIF_RTR_CTRL_5_NL_HBM_OFFSET_2 0x3D6558
+
+#define mmNIF_RTR_CTRL_5_NL_HBM_OFFSET_3 0x3D655C
+
+#define mmNIF_RTR_CTRL_5_NL_HBM_OFFSET_4 0x3D6560
+
+#define mmNIF_RTR_CTRL_5_NL_HBM_OFFSET_5 0x3D6564
+
+#define mmNIF_RTR_CTRL_5_NL_HBM_OFFSET_6 0x3D6568
+
+#define mmNIF_RTR_CTRL_5_NL_HBM_OFFSET_7 0x3D656C
+
+#define mmNIF_RTR_CTRL_5_NL_HBM_OFFSET_8 0x3D6570
+
+#define mmNIF_RTR_CTRL_5_NL_HBM_OFFSET_9 0x3D6574
+
+#define mmNIF_RTR_CTRL_5_NL_HBM_OFFSET_10 0x3D6578
+
+#define mmNIF_RTR_CTRL_5_NL_HBM_OFFSET_11 0x3D657C
+
+#define mmNIF_RTR_CTRL_5_NL_HBM_OFFSET_12 0x3D6580
+
+#define mmNIF_RTR_CTRL_5_NL_HBM_OFFSET_13 0x3D6584
+
+#define mmNIF_RTR_CTRL_5_NL_HBM_OFFSET_14 0x3D6588
+
+#define mmNIF_RTR_CTRL_5_NL_HBM_OFFSET_15 0x3D658C
+
+#define mmNIF_RTR_CTRL_5_NL_HBM_OFFSET_16 0x3D6590
+
+#define mmNIF_RTR_CTRL_5_NL_HBM_OFFSET_17 0x3D6594
+
+#define mmNIF_RTR_CTRL_5_NL_HBM_OFFSET_18 0x3D6598
+
+#define mmNIF_RTR_CTRL_5_RANGE_SEC_BASE_LOW_AW_0 0x3D65E4
+
+#define mmNIF_RTR_CTRL_5_RANGE_SEC_BASE_LOW_AW_1 0x3D65E8
+
+#define mmNIF_RTR_CTRL_5_RANGE_SEC_BASE_LOW_AW_2 0x3D65EC
+
+#define mmNIF_RTR_CTRL_5_RANGE_SEC_BASE_LOW_AW_3 0x3D65F0
+
+#define mmNIF_RTR_CTRL_5_RANGE_SEC_BASE_LOW_AW_4 0x3D65F4
+
+#define mmNIF_RTR_CTRL_5_RANGE_SEC_BASE_LOW_AW_5 0x3D65F8
+
+#define mmNIF_RTR_CTRL_5_RANGE_SEC_BASE_LOW_AW_6 0x3D65FC
+
+#define mmNIF_RTR_CTRL_5_RANGE_SEC_BASE_LOW_AW_7 0x3D6600
+
+#define mmNIF_RTR_CTRL_5_RANGE_SEC_BASE_LOW_AW_8 0x3D6604
+
+#define mmNIF_RTR_CTRL_5_RANGE_SEC_BASE_LOW_AW_9 0x3D6608
+
+#define mmNIF_RTR_CTRL_5_RANGE_SEC_BASE_LOW_AW_10 0x3D660C
+
+#define mmNIF_RTR_CTRL_5_RANGE_SEC_BASE_LOW_AW_11 0x3D6610
+
+#define mmNIF_RTR_CTRL_5_RANGE_SEC_BASE_LOW_AW_12 0x3D6614
+
+#define mmNIF_RTR_CTRL_5_RANGE_SEC_BASE_LOW_AW_13 0x3D6618
+
+#define mmNIF_RTR_CTRL_5_RANGE_SEC_BASE_LOW_AW_14 0x3D661C
+
+#define mmNIF_RTR_CTRL_5_RANGE_SEC_BASE_LOW_AW_15 0x3D6620
+
+#define mmNIF_RTR_CTRL_5_RANGE_SEC_BASE_HIGH_AW_0 0x3D6624
+
+#define mmNIF_RTR_CTRL_5_RANGE_SEC_BASE_HIGH_AW_1 0x3D6628
+
+#define mmNIF_RTR_CTRL_5_RANGE_SEC_BASE_HIGH_AW_2 0x3D662C
+
+#define mmNIF_RTR_CTRL_5_RANGE_SEC_BASE_HIGH_AW_3 0x3D6630
+
+#define mmNIF_RTR_CTRL_5_RANGE_SEC_BASE_HIGH_AW_4 0x3D6634
+
+#define mmNIF_RTR_CTRL_5_RANGE_SEC_BASE_HIGH_AW_5 0x3D6638
+
+#define mmNIF_RTR_CTRL_5_RANGE_SEC_BASE_HIGH_AW_6 0x3D663C
+
+#define mmNIF_RTR_CTRL_5_RANGE_SEC_BASE_HIGH_AW_7 0x3D6640
+
+#define mmNIF_RTR_CTRL_5_RANGE_SEC_BASE_HIGH_AW_8 0x3D6644
+
+#define mmNIF_RTR_CTRL_5_RANGE_SEC_BASE_HIGH_AW_9 0x3D6648
+
+#define mmNIF_RTR_CTRL_5_RANGE_SEC_BASE_HIGH_AW_10 0x3D664C
+
+#define mmNIF_RTR_CTRL_5_RANGE_SEC_BASE_HIGH_AW_11 0x3D6650
+
+#define mmNIF_RTR_CTRL_5_RANGE_SEC_BASE_HIGH_AW_12 0x3D6654
+
+#define mmNIF_RTR_CTRL_5_RANGE_SEC_BASE_HIGH_AW_13 0x3D6658
+
+#define mmNIF_RTR_CTRL_5_RANGE_SEC_BASE_HIGH_AW_14 0x3D665C
+
+#define mmNIF_RTR_CTRL_5_RANGE_SEC_BASE_HIGH_AW_15 0x3D6660
+
+#define mmNIF_RTR_CTRL_5_RANGE_SEC_MASK_LOW_AW_0 0x3D6664
+
+#define mmNIF_RTR_CTRL_5_RANGE_SEC_MASK_LOW_AW_1 0x3D6668
+
+#define mmNIF_RTR_CTRL_5_RANGE_SEC_MASK_LOW_AW_2 0x3D666C
+
+#define mmNIF_RTR_CTRL_5_RANGE_SEC_MASK_LOW_AW_3 0x3D6670
+
+#define mmNIF_RTR_CTRL_5_RANGE_SEC_MASK_LOW_AW_4 0x3D6674
+
+#define mmNIF_RTR_CTRL_5_RANGE_SEC_MASK_LOW_AW_5 0x3D6678
+
+#define mmNIF_RTR_CTRL_5_RANGE_SEC_MASK_LOW_AW_6 0x3D667C
+
+#define mmNIF_RTR_CTRL_5_RANGE_SEC_MASK_LOW_AW_7 0x3D6680
+
+#define mmNIF_RTR_CTRL_5_RANGE_SEC_MASK_LOW_AW_8 0x3D6684
+
+#define mmNIF_RTR_CTRL_5_RANGE_SEC_MASK_LOW_AW_9 0x3D6688
+
+#define mmNIF_RTR_CTRL_5_RANGE_SEC_MASK_LOW_AW_10 0x3D668C
+
+#define mmNIF_RTR_CTRL_5_RANGE_SEC_MASK_LOW_AW_11 0x3D6690
+
+#define mmNIF_RTR_CTRL_5_RANGE_SEC_MASK_LOW_AW_12 0x3D6694
+
+#define mmNIF_RTR_CTRL_5_RANGE_SEC_MASK_LOW_AW_13 0x3D6698
+
+#define mmNIF_RTR_CTRL_5_RANGE_SEC_MASK_LOW_AW_14 0x3D669C
+
+#define mmNIF_RTR_CTRL_5_RANGE_SEC_MASK_LOW_AW_15 0x3D66A0
+
+#define mmNIF_RTR_CTRL_5_RANGE_SEC_MASK_HIGH_AW_0 0x3D66A4
+
+#define mmNIF_RTR_CTRL_5_RANGE_SEC_MASK_HIGH_AW_1 0x3D66A8
+
+#define mmNIF_RTR_CTRL_5_RANGE_SEC_MASK_HIGH_AW_2 0x3D66AC
+
+#define mmNIF_RTR_CTRL_5_RANGE_SEC_MASK_HIGH_AW_3 0x3D66B0
+
+#define mmNIF_RTR_CTRL_5_RANGE_SEC_MASK_HIGH_AW_4 0x3D66B4
+
+#define mmNIF_RTR_CTRL_5_RANGE_SEC_MASK_HIGH_AW_5 0x3D66B8
+
+#define mmNIF_RTR_CTRL_5_RANGE_SEC_MASK_HIGH_AW_6 0x3D66BC
+
+#define mmNIF_RTR_CTRL_5_RANGE_SEC_MASK_HIGH_AW_7 0x3D66C0
+
+#define mmNIF_RTR_CTRL_5_RANGE_SEC_MASK_HIGH_AW_8 0x3D66C4
+
+#define mmNIF_RTR_CTRL_5_RANGE_SEC_MASK_HIGH_AW_9 0x3D66C8
+
+#define mmNIF_RTR_CTRL_5_RANGE_SEC_MASK_HIGH_AW_10 0x3D66CC
+
+#define mmNIF_RTR_CTRL_5_RANGE_SEC_MASK_HIGH_AW_11 0x3D66D0
+
+#define mmNIF_RTR_CTRL_5_RANGE_SEC_MASK_HIGH_AW_12 0x3D66D4
+
+#define mmNIF_RTR_CTRL_5_RANGE_SEC_MASK_HIGH_AW_13 0x3D66D8
+
+#define mmNIF_RTR_CTRL_5_RANGE_SEC_MASK_HIGH_AW_14 0x3D66DC
+
+#define mmNIF_RTR_CTRL_5_RANGE_SEC_MASK_HIGH_AW_15 0x3D66E0
+
+#define mmNIF_RTR_CTRL_5_RANGE_PRIV_BASE_LOW_AW_0 0x3D66E4
+
+#define mmNIF_RTR_CTRL_5_RANGE_PRIV_BASE_LOW_AW_1 0x3D66E8
+
+#define mmNIF_RTR_CTRL_5_RANGE_PRIV_BASE_LOW_AW_2 0x3D66EC
+
+#define mmNIF_RTR_CTRL_5_RANGE_PRIV_BASE_LOW_AW_3 0x3D66F0
+
+#define mmNIF_RTR_CTRL_5_RANGE_PRIV_BASE_LOW_AW_4 0x3D66F4
+
+#define mmNIF_RTR_CTRL_5_RANGE_PRIV_BASE_LOW_AW_5 0x3D66F8
+
+#define mmNIF_RTR_CTRL_5_RANGE_PRIV_BASE_LOW_AW_6 0x3D66FC
+
+#define mmNIF_RTR_CTRL_5_RANGE_PRIV_BASE_LOW_AW_7 0x3D6700
+
+#define mmNIF_RTR_CTRL_5_RANGE_PRIV_BASE_LOW_AW_8 0x3D6704
+
+#define mmNIF_RTR_CTRL_5_RANGE_PRIV_BASE_LOW_AW_9 0x3D6708
+
+#define mmNIF_RTR_CTRL_5_RANGE_PRIV_BASE_LOW_AW_10 0x3D670C
+
+#define mmNIF_RTR_CTRL_5_RANGE_PRIV_BASE_LOW_AW_11 0x3D6710
+
+#define mmNIF_RTR_CTRL_5_RANGE_PRIV_BASE_LOW_AW_12 0x3D6714
+
+#define mmNIF_RTR_CTRL_5_RANGE_PRIV_BASE_LOW_AW_13 0x3D6718
+
+#define mmNIF_RTR_CTRL_5_RANGE_PRIV_BASE_LOW_AW_14 0x3D671C
+
+#define mmNIF_RTR_CTRL_5_RANGE_PRIV_BASE_LOW_AW_15 0x3D6720
+
+#define mmNIF_RTR_CTRL_5_RANGE_PRIV_BASE_HIGH_AW_0 0x3D6724
+
+#define mmNIF_RTR_CTRL_5_RANGE_PRIV_BASE_HIGH_AW_1 0x3D6728
+
+#define mmNIF_RTR_CTRL_5_RANGE_PRIV_BASE_HIGH_AW_2 0x3D672C
+
+#define mmNIF_RTR_CTRL_5_RANGE_PRIV_BASE_HIGH_AW_3 0x3D6730
+
+#define mmNIF_RTR_CTRL_5_RANGE_PRIV_BASE_HIGH_AW_4 0x3D6734
+
+#define mmNIF_RTR_CTRL_5_RANGE_PRIV_BASE_HIGH_AW_5 0x3D6738
+
+#define mmNIF_RTR_CTRL_5_RANGE_PRIV_BASE_HIGH_AW_6 0x3D673C
+
+#define mmNIF_RTR_CTRL_5_RANGE_PRIV_BASE_HIGH_AW_7 0x3D6740
+
+#define mmNIF_RTR_CTRL_5_RANGE_PRIV_BASE_HIGH_AW_8 0x3D6744
+
+#define mmNIF_RTR_CTRL_5_RANGE_PRIV_BASE_HIGH_AW_9 0x3D6748
+
+#define mmNIF_RTR_CTRL_5_RANGE_PRIV_BASE_HIGH_AW_10 0x3D674C
+
+#define mmNIF_RTR_CTRL_5_RANGE_PRIV_BASE_HIGH_AW_11 0x3D6750
+
+#define mmNIF_RTR_CTRL_5_RANGE_PRIV_BASE_HIGH_AW_12 0x3D6754
+
+#define mmNIF_RTR_CTRL_5_RANGE_PRIV_BASE_HIGH_AW_13 0x3D6758
+
+#define mmNIF_RTR_CTRL_5_RANGE_PRIV_BASE_HIGH_AW_14 0x3D675C
+
+#define mmNIF_RTR_CTRL_5_RANGE_PRIV_BASE_HIGH_AW_15 0x3D6760
+
+#define mmNIF_RTR_CTRL_5_RANGE_PRIV_MASK_LOW_AW_0 0x3D6764
+
+#define mmNIF_RTR_CTRL_5_RANGE_PRIV_MASK_LOW_AW_1 0x3D6768
+
+#define mmNIF_RTR_CTRL_5_RANGE_PRIV_MASK_LOW_AW_2 0x3D676C
+
+#define mmNIF_RTR_CTRL_5_RANGE_PRIV_MASK_LOW_AW_3 0x3D6770
+
+#define mmNIF_RTR_CTRL_5_RANGE_PRIV_MASK_LOW_AW_4 0x3D6774
+
+#define mmNIF_RTR_CTRL_5_RANGE_PRIV_MASK_LOW_AW_5 0x3D6778
+
+#define mmNIF_RTR_CTRL_5_RANGE_PRIV_MASK_LOW_AW_6 0x3D677C
+
+#define mmNIF_RTR_CTRL_5_RANGE_PRIV_MASK_LOW_AW_7 0x3D6780
+
+#define mmNIF_RTR_CTRL_5_RANGE_PRIV_MASK_LOW_AW_8 0x3D6784
+
+#define mmNIF_RTR_CTRL_5_RANGE_PRIV_MASK_LOW_AW_9 0x3D6788
+
+#define mmNIF_RTR_CTRL_5_RANGE_PRIV_MASK_LOW_AW_10 0x3D678C
+
+#define mmNIF_RTR_CTRL_5_RANGE_PRIV_MASK_LOW_AW_11 0x3D6790
+
+#define mmNIF_RTR_CTRL_5_RANGE_PRIV_MASK_LOW_AW_12 0x3D6794
+
+#define mmNIF_RTR_CTRL_5_RANGE_PRIV_MASK_LOW_AW_13 0x3D6798
+
+#define mmNIF_RTR_CTRL_5_RANGE_PRIV_MASK_LOW_AW_14 0x3D679C
+
+#define mmNIF_RTR_CTRL_5_RANGE_PRIV_MASK_LOW_AW_15 0x3D67A0
+
+#define mmNIF_RTR_CTRL_5_RANGE_PRIV_MASK_HIGH_AW_0 0x3D67A4
+
+#define mmNIF_RTR_CTRL_5_RANGE_PRIV_MASK_HIGH_AW_1 0x3D67A8
+
+#define mmNIF_RTR_CTRL_5_RANGE_PRIV_MASK_HIGH_AW_2 0x3D67AC
+
+#define mmNIF_RTR_CTRL_5_RANGE_PRIV_MASK_HIGH_AW_3 0x3D67B0
+
+#define mmNIF_RTR_CTRL_5_RANGE_PRIV_MASK_HIGH_AW_4 0x3D67B4
+
+#define mmNIF_RTR_CTRL_5_RANGE_PRIV_MASK_HIGH_AW_5 0x3D67B8
+
+#define mmNIF_RTR_CTRL_5_RANGE_PRIV_MASK_HIGH_AW_6 0x3D67BC
+
+#define mmNIF_RTR_CTRL_5_RANGE_PRIV_MASK_HIGH_AW_7 0x3D67C0
+
+#define mmNIF_RTR_CTRL_5_RANGE_PRIV_MASK_HIGH_AW_8 0x3D67C4
+
+#define mmNIF_RTR_CTRL_5_RANGE_PRIV_MASK_HIGH_AW_9 0x3D67C8
+
+#define mmNIF_RTR_CTRL_5_RANGE_PRIV_MASK_HIGH_AW_10 0x3D67CC
+
+#define mmNIF_RTR_CTRL_5_RANGE_PRIV_MASK_HIGH_AW_11 0x3D67D0
+
+#define mmNIF_RTR_CTRL_5_RANGE_PRIV_MASK_HIGH_AW_12 0x3D67D4
+
+#define mmNIF_RTR_CTRL_5_RANGE_PRIV_MASK_HIGH_AW_13 0x3D67D8
+
+#define mmNIF_RTR_CTRL_5_RANGE_PRIV_MASK_HIGH_AW_14 0x3D67DC
+
+#define mmNIF_RTR_CTRL_5_RANGE_PRIV_MASK_HIGH_AW_15 0x3D67E0
+
+#define mmNIF_RTR_CTRL_5_RANGE_SEC_BASE_LOW_AR_0 0x3D6824
+
+#define mmNIF_RTR_CTRL_5_RANGE_SEC_BASE_LOW_AR_1 0x3D6828
+
+#define mmNIF_RTR_CTRL_5_RANGE_SEC_BASE_LOW_AR_2 0x3D682C
+
+#define mmNIF_RTR_CTRL_5_RANGE_SEC_BASE_LOW_AR_3 0x3D6830
+
+#define mmNIF_RTR_CTRL_5_RANGE_SEC_BASE_LOW_AR_4 0x3D6834
+
+#define mmNIF_RTR_CTRL_5_RANGE_SEC_BASE_LOW_AR_5 0x3D6838
+
+#define mmNIF_RTR_CTRL_5_RANGE_SEC_BASE_LOW_AR_6 0x3D683C
+
+#define mmNIF_RTR_CTRL_5_RANGE_SEC_BASE_LOW_AR_7 0x3D6840
+
+#define mmNIF_RTR_CTRL_5_RANGE_SEC_BASE_LOW_AR_8 0x3D6844
+
+#define mmNIF_RTR_CTRL_5_RANGE_SEC_BASE_LOW_AR_9 0x3D6848
+
+#define mmNIF_RTR_CTRL_5_RANGE_SEC_BASE_LOW_AR_10 0x3D684C
+
+#define mmNIF_RTR_CTRL_5_RANGE_SEC_BASE_LOW_AR_11 0x3D6850
+
+#define mmNIF_RTR_CTRL_5_RANGE_SEC_BASE_LOW_AR_12 0x3D6854
+
+#define mmNIF_RTR_CTRL_5_RANGE_SEC_BASE_LOW_AR_13 0x3D6858
+
+#define mmNIF_RTR_CTRL_5_RANGE_SEC_BASE_LOW_AR_14 0x3D685C
+
+#define mmNIF_RTR_CTRL_5_RANGE_SEC_BASE_LOW_AR_15 0x3D6860
+
+#define mmNIF_RTR_CTRL_5_RANGE_SEC_BASE_HIGH_AR_0 0x3D6864
+
+#define mmNIF_RTR_CTRL_5_RANGE_SEC_BASE_HIGH_AR_1 0x3D6868
+
+#define mmNIF_RTR_CTRL_5_RANGE_SEC_BASE_HIGH_AR_2 0x3D686C
+
+#define mmNIF_RTR_CTRL_5_RANGE_SEC_BASE_HIGH_AR_3 0x3D6870
+
+#define mmNIF_RTR_CTRL_5_RANGE_SEC_BASE_HIGH_AR_4 0x3D6874
+
+#define mmNIF_RTR_CTRL_5_RANGE_SEC_BASE_HIGH_AR_5 0x3D6878
+
+#define mmNIF_RTR_CTRL_5_RANGE_SEC_BASE_HIGH_AR_6 0x3D687C
+
+#define mmNIF_RTR_CTRL_5_RANGE_SEC_BASE_HIGH_AR_7 0x3D6880
+
+#define mmNIF_RTR_CTRL_5_RANGE_SEC_BASE_HIGH_AR_8 0x3D6884
+
+#define mmNIF_RTR_CTRL_5_RANGE_SEC_BASE_HIGH_AR_9 0x3D6888
+
+#define mmNIF_RTR_CTRL_5_RANGE_SEC_BASE_HIGH_AR_10 0x3D688C
+
+#define mmNIF_RTR_CTRL_5_RANGE_SEC_BASE_HIGH_AR_11 0x3D6890
+
+#define mmNIF_RTR_CTRL_5_RANGE_SEC_BASE_HIGH_AR_12 0x3D6894
+
+#define mmNIF_RTR_CTRL_5_RANGE_SEC_BASE_HIGH_AR_13 0x3D6898
+
+#define mmNIF_RTR_CTRL_5_RANGE_SEC_BASE_HIGH_AR_14 0x3D689C
+
+#define mmNIF_RTR_CTRL_5_RANGE_SEC_BASE_HIGH_AR_15 0x3D68A0
+
+#define mmNIF_RTR_CTRL_5_RANGE_SEC_MASK_LOW_AR_0 0x3D68A4
+
+#define mmNIF_RTR_CTRL_5_RANGE_SEC_MASK_LOW_AR_1 0x3D68A8
+
+#define mmNIF_RTR_CTRL_5_RANGE_SEC_MASK_LOW_AR_2 0x3D68AC
+
+#define mmNIF_RTR_CTRL_5_RANGE_SEC_MASK_LOW_AR_3 0x3D68B0
+
+#define mmNIF_RTR_CTRL_5_RANGE_SEC_MASK_LOW_AR_4 0x3D68B4
+
+#define mmNIF_RTR_CTRL_5_RANGE_SEC_MASK_LOW_AR_5 0x3D68B8
+
+#define mmNIF_RTR_CTRL_5_RANGE_SEC_MASK_LOW_AR_6 0x3D68BC
+
+#define mmNIF_RTR_CTRL_5_RANGE_SEC_MASK_LOW_AR_7 0x3D68C0
+
+#define mmNIF_RTR_CTRL_5_RANGE_SEC_MASK_LOW_AR_8 0x3D68C4
+
+#define mmNIF_RTR_CTRL_5_RANGE_SEC_MASK_LOW_AR_9 0x3D68C8
+
+#define mmNIF_RTR_CTRL_5_RANGE_SEC_MASK_LOW_AR_10 0x3D68CC
+
+#define mmNIF_RTR_CTRL_5_RANGE_SEC_MASK_LOW_AR_11 0x3D68D0
+
+#define mmNIF_RTR_CTRL_5_RANGE_SEC_MASK_LOW_AR_12 0x3D68D4
+
+#define mmNIF_RTR_CTRL_5_RANGE_SEC_MASK_LOW_AR_13 0x3D68D8
+
+#define mmNIF_RTR_CTRL_5_RANGE_SEC_MASK_LOW_AR_14 0x3D68DC
+
+#define mmNIF_RTR_CTRL_5_RANGE_SEC_MASK_LOW_AR_15 0x3D68E0
+
+#define mmNIF_RTR_CTRL_5_RANGE_SEC_MASK_HIGH_AR_0 0x3D68E4
+
+#define mmNIF_RTR_CTRL_5_RANGE_SEC_MASK_HIGH_AR_1 0x3D68E8
+
+#define mmNIF_RTR_CTRL_5_RANGE_SEC_MASK_HIGH_AR_2 0x3D68EC
+
+#define mmNIF_RTR_CTRL_5_RANGE_SEC_MASK_HIGH_AR_3 0x3D68F0
+
+#define mmNIF_RTR_CTRL_5_RANGE_SEC_MASK_HIGH_AR_4 0x3D68F4
+
+#define mmNIF_RTR_CTRL_5_RANGE_SEC_MASK_HIGH_AR_5 0x3D68F8
+
+#define mmNIF_RTR_CTRL_5_RANGE_SEC_MASK_HIGH_AR_6 0x3D68FC
+
+#define mmNIF_RTR_CTRL_5_RANGE_SEC_MASK_HIGH_AR_7 0x3D6900
+
+#define mmNIF_RTR_CTRL_5_RANGE_SEC_MASK_HIGH_AR_8 0x3D6904
+
+#define mmNIF_RTR_CTRL_5_RANGE_SEC_MASK_HIGH_AR_9 0x3D6908
+
+#define mmNIF_RTR_CTRL_5_RANGE_SEC_MASK_HIGH_AR_10 0x3D690C
+
+#define mmNIF_RTR_CTRL_5_RANGE_SEC_MASK_HIGH_AR_11 0x3D6910
+
+#define mmNIF_RTR_CTRL_5_RANGE_SEC_MASK_HIGH_AR_12 0x3D6914
+
+#define mmNIF_RTR_CTRL_5_RANGE_SEC_MASK_HIGH_AR_13 0x3D6918
+
+#define mmNIF_RTR_CTRL_5_RANGE_SEC_MASK_HIGH_AR_14 0x3D691C
+
+#define mmNIF_RTR_CTRL_5_RANGE_SEC_MASK_HIGH_AR_15 0x3D6920
+
+#define mmNIF_RTR_CTRL_5_RANGE_PRIV_BASE_LOW_AR_0 0x3D6924
+
+#define mmNIF_RTR_CTRL_5_RANGE_PRIV_BASE_LOW_AR_1 0x3D6928
+
+#define mmNIF_RTR_CTRL_5_RANGE_PRIV_BASE_LOW_AR_2 0x3D692C
+
+#define mmNIF_RTR_CTRL_5_RANGE_PRIV_BASE_LOW_AR_3 0x3D6930
+
+#define mmNIF_RTR_CTRL_5_RANGE_PRIV_BASE_LOW_AR_4 0x3D6934
+
+#define mmNIF_RTR_CTRL_5_RANGE_PRIV_BASE_LOW_AR_5 0x3D6938
+
+#define mmNIF_RTR_CTRL_5_RANGE_PRIV_BASE_LOW_AR_6 0x3D693C
+
+#define mmNIF_RTR_CTRL_5_RANGE_PRIV_BASE_LOW_AR_7 0x3D6940
+
+#define mmNIF_RTR_CTRL_5_RANGE_PRIV_BASE_LOW_AR_8 0x3D6944
+
+#define mmNIF_RTR_CTRL_5_RANGE_PRIV_BASE_LOW_AR_9 0x3D6948
+
+#define mmNIF_RTR_CTRL_5_RANGE_PRIV_BASE_LOW_AR_10 0x3D694C
+
+#define mmNIF_RTR_CTRL_5_RANGE_PRIV_BASE_LOW_AR_11 0x3D6950
+
+#define mmNIF_RTR_CTRL_5_RANGE_PRIV_BASE_LOW_AR_12 0x3D6954
+
+#define mmNIF_RTR_CTRL_5_RANGE_PRIV_BASE_LOW_AR_13 0x3D6958
+
+#define mmNIF_RTR_CTRL_5_RANGE_PRIV_BASE_LOW_AR_14 0x3D695C
+
+#define mmNIF_RTR_CTRL_5_RANGE_PRIV_BASE_LOW_AR_15 0x3D6960
+
+#define mmNIF_RTR_CTRL_5_RANGE_PRIV_BASE_HIGH_AR_0 0x3D6964
+
+#define mmNIF_RTR_CTRL_5_RANGE_PRIV_BASE_HIGH_AR_1 0x3D6968
+
+#define mmNIF_RTR_CTRL_5_RANGE_PRIV_BASE_HIGH_AR_2 0x3D696C
+
+#define mmNIF_RTR_CTRL_5_RANGE_PRIV_BASE_HIGH_AR_3 0x3D6970
+
+#define mmNIF_RTR_CTRL_5_RANGE_PRIV_BASE_HIGH_AR_4 0x3D6974
+
+#define mmNIF_RTR_CTRL_5_RANGE_PRIV_BASE_HIGH_AR_5 0x3D6978
+
+#define mmNIF_RTR_CTRL_5_RANGE_PRIV_BASE_HIGH_AR_6 0x3D697C
+
+#define mmNIF_RTR_CTRL_5_RANGE_PRIV_BASE_HIGH_AR_7 0x3D6980
+
+#define mmNIF_RTR_CTRL_5_RANGE_PRIV_BASE_HIGH_AR_8 0x3D6984
+
+#define mmNIF_RTR_CTRL_5_RANGE_PRIV_BASE_HIGH_AR_9 0x3D6988
+
+#define mmNIF_RTR_CTRL_5_RANGE_PRIV_BASE_HIGH_AR_10 0x3D698C
+
+#define mmNIF_RTR_CTRL_5_RANGE_PRIV_BASE_HIGH_AR_11 0x3D6990
+
+#define mmNIF_RTR_CTRL_5_RANGE_PRIV_BASE_HIGH_AR_12 0x3D6994
+
+#define mmNIF_RTR_CTRL_5_RANGE_PRIV_BASE_HIGH_AR_13 0x3D6998
+
+#define mmNIF_RTR_CTRL_5_RANGE_PRIV_BASE_HIGH_AR_14 0x3D699C
+
+#define mmNIF_RTR_CTRL_5_RANGE_PRIV_BASE_HIGH_AR_15 0x3D69A0
+
+#define mmNIF_RTR_CTRL_5_RANGE_PRIV_MASK_LOW_AR_0 0x3D69A4
+
+#define mmNIF_RTR_CTRL_5_RANGE_PRIV_MASK_LOW_AR_1 0x3D69A8
+
+#define mmNIF_RTR_CTRL_5_RANGE_PRIV_MASK_LOW_AR_2 0x3D69AC
+
+#define mmNIF_RTR_CTRL_5_RANGE_PRIV_MASK_LOW_AR_3 0x3D69B0
+
+#define mmNIF_RTR_CTRL_5_RANGE_PRIV_MASK_LOW_AR_4 0x3D69B4
+
+#define mmNIF_RTR_CTRL_5_RANGE_PRIV_MASK_LOW_AR_5 0x3D69B8
+
+#define mmNIF_RTR_CTRL_5_RANGE_PRIV_MASK_LOW_AR_6 0x3D69BC
+
+#define mmNIF_RTR_CTRL_5_RANGE_PRIV_MASK_LOW_AR_7 0x3D69C0
+
+#define mmNIF_RTR_CTRL_5_RANGE_PRIV_MASK_LOW_AR_8 0x3D69C4
+
+#define mmNIF_RTR_CTRL_5_RANGE_PRIV_MASK_LOW_AR_9 0x3D69C8
+
+#define mmNIF_RTR_CTRL_5_RANGE_PRIV_MASK_LOW_AR_10 0x3D69CC
+
+#define mmNIF_RTR_CTRL_5_RANGE_PRIV_MASK_LOW_AR_11 0x3D69D0
+
+#define mmNIF_RTR_CTRL_5_RANGE_PRIV_MASK_LOW_AR_12 0x3D69D4
+
+#define mmNIF_RTR_CTRL_5_RANGE_PRIV_MASK_LOW_AR_13 0x3D69D8
+
+#define mmNIF_RTR_CTRL_5_RANGE_PRIV_MASK_LOW_AR_14 0x3D69DC
+
+#define mmNIF_RTR_CTRL_5_RANGE_PRIV_MASK_LOW_AR_15 0x3D69E0
+
+#define mmNIF_RTR_CTRL_5_RANGE_PRIV_MASK_HIGH_AR_0 0x3D69E4
+
+#define mmNIF_RTR_CTRL_5_RANGE_PRIV_MASK_HIGH_AR_1 0x3D69E8
+
+#define mmNIF_RTR_CTRL_5_RANGE_PRIV_MASK_HIGH_AR_2 0x3D69EC
+
+#define mmNIF_RTR_CTRL_5_RANGE_PRIV_MASK_HIGH_AR_3 0x3D69F0
+
+#define mmNIF_RTR_CTRL_5_RANGE_PRIV_MASK_HIGH_AR_4 0x3D69F4
+
+#define mmNIF_RTR_CTRL_5_RANGE_PRIV_MASK_HIGH_AR_5 0x3D69F8
+
+#define mmNIF_RTR_CTRL_5_RANGE_PRIV_MASK_HIGH_AR_6 0x3D69FC
+
+#define mmNIF_RTR_CTRL_5_RANGE_PRIV_MASK_HIGH_AR_7 0x3D6A00
+
+#define mmNIF_RTR_CTRL_5_RANGE_PRIV_MASK_HIGH_AR_8 0x3D6A04
+
+#define mmNIF_RTR_CTRL_5_RANGE_PRIV_MASK_HIGH_AR_9 0x3D6A08
+
+#define mmNIF_RTR_CTRL_5_RANGE_PRIV_MASK_HIGH_AR_10 0x3D6A0C
+
+#define mmNIF_RTR_CTRL_5_RANGE_PRIV_MASK_HIGH_AR_11 0x3D6A10
+
+#define mmNIF_RTR_CTRL_5_RANGE_PRIV_MASK_HIGH_AR_12 0x3D6A14
+
+#define mmNIF_RTR_CTRL_5_RANGE_PRIV_MASK_HIGH_AR_13 0x3D6A18
+
+#define mmNIF_RTR_CTRL_5_RANGE_PRIV_MASK_HIGH_AR_14 0x3D6A1C
+
+#define mmNIF_RTR_CTRL_5_RANGE_PRIV_MASK_HIGH_AR_15 0x3D6A20
+
+#define mmNIF_RTR_CTRL_5_RANGE_SEC_HIT_AW 0x3D6A64
+
+#define mmNIF_RTR_CTRL_5_RANGE_SEC_HIT_AR 0x3D6A68
+
+#define mmNIF_RTR_CTRL_5_RANGE_PRIV_HIT_AW 0x3D6A6C
+
+#define mmNIF_RTR_CTRL_5_RANGE_PRIV_HIT_AR 0x3D6A70
+
+#define mmNIF_RTR_CTRL_5_RGL_CFG 0x3D6B64
+
+#define mmNIF_RTR_CTRL_5_RGL_SHIFT 0x3D6B68
+
+#define mmNIF_RTR_CTRL_5_RGL_EXPECTED_LAT_0 0x3D6B6C
+
+#define mmNIF_RTR_CTRL_5_RGL_EXPECTED_LAT_1 0x3D6B70
+
+#define mmNIF_RTR_CTRL_5_RGL_EXPECTED_LAT_2 0x3D6B74
+
+#define mmNIF_RTR_CTRL_5_RGL_EXPECTED_LAT_3 0x3D6B78
+
+#define mmNIF_RTR_CTRL_5_RGL_EXPECTED_LAT_4 0x3D6B7C
+
+#define mmNIF_RTR_CTRL_5_RGL_EXPECTED_LAT_5 0x3D6B80
+
+#define mmNIF_RTR_CTRL_5_RGL_EXPECTED_LAT_6 0x3D6B84
+
+#define mmNIF_RTR_CTRL_5_RGL_EXPECTED_LAT_7 0x3D6B88
+
+#define mmNIF_RTR_CTRL_5_RGL_TOKEN_0 0x3D6BAC
+
+#define mmNIF_RTR_CTRL_5_RGL_TOKEN_1 0x3D6BB0
+
+#define mmNIF_RTR_CTRL_5_RGL_TOKEN_2 0x3D6BB4
+
+#define mmNIF_RTR_CTRL_5_RGL_TOKEN_3 0x3D6BB8
+
+#define mmNIF_RTR_CTRL_5_RGL_TOKEN_4 0x3D6BBC
+
+#define mmNIF_RTR_CTRL_5_RGL_TOKEN_5 0x3D6BC0
+
+#define mmNIF_RTR_CTRL_5_RGL_TOKEN_6 0x3D6BC4
+
+#define mmNIF_RTR_CTRL_5_RGL_TOKEN_7 0x3D6BC8
+
+#define mmNIF_RTR_CTRL_5_RGL_BANK_ID_0 0x3D6BEC
+
+#define mmNIF_RTR_CTRL_5_RGL_BANK_ID_1 0x3D6BF0
+
+#define mmNIF_RTR_CTRL_5_RGL_BANK_ID_2 0x3D6BF4
+
+#define mmNIF_RTR_CTRL_5_RGL_BANK_ID_3 0x3D6BF8
+
+#define mmNIF_RTR_CTRL_5_RGL_BANK_ID_4 0x3D6BFC
+
+#define mmNIF_RTR_CTRL_5_RGL_BANK_ID_5 0x3D6C00
+
+#define mmNIF_RTR_CTRL_5_RGL_BANK_ID_6 0x3D6C04
+
+#define mmNIF_RTR_CTRL_5_RGL_BANK_ID_7 0x3D6C08
+
+#define mmNIF_RTR_CTRL_5_RGL_WDT 0x3D6C2C
+
+#define mmNIF_RTR_CTRL_5_E2E_AR_HBM0_CH0_CTR_WRAP 0x3D6C30
+
+#define mmNIF_RTR_CTRL_5_E2E_AR_HBM0_CH1_CTR_WRAP 0x3D6C34
+
+#define mmNIF_RTR_CTRL_5_E2E_AR_HBM1_CH0_CTR_WRAP 0x3D6C38
+
+#define mmNIF_RTR_CTRL_5_E2E_AR_HBM1_CH1_CTR_WRAP 0x3D6C3C
+
+#define mmNIF_RTR_CTRL_5_E2E_AR_HBM2_CH0_CTR_WRAP 0x3D6C40
+
+#define mmNIF_RTR_CTRL_5_E2E_AR_HBM2_CH1_CTR_WRAP 0x3D6C44
+
+#define mmNIF_RTR_CTRL_5_E2E_AR_HBM3_CH0_CTR_WRAP 0x3D6C48
+
+#define mmNIF_RTR_CTRL_5_E2E_AR_HBM3_CH1_CTR_WRAP 0x3D6C4C
+
+#define mmNIF_RTR_CTRL_5_E2E_AR_HBM0_CH0_CTR_CNT 0x3D6C50
+
+#define mmNIF_RTR_CTRL_5_E2E_AR_HBM0_CH1_CTR_CNT 0x3D6C54
+
+#define mmNIF_RTR_CTRL_5_E2E_AR_HBM1_CH0_CTR_CNT 0x3D6C58
+
+#define mmNIF_RTR_CTRL_5_E2E_AR_HBM1_CH1_CTR_CNT 0x3D6C5C
+
+#define mmNIF_RTR_CTRL_5_E2E_AR_HBM2_CH0_CTR_CNT 0x3D6C60
+
+#define mmNIF_RTR_CTRL_5_E2E_AR_HBM2_CH1_CTR_CNT 0x3D6C64
+
+#define mmNIF_RTR_CTRL_5_E2E_AR_HBM3_CH0_CTR_CNT 0x3D6C68
+
+#define mmNIF_RTR_CTRL_5_E2E_AR_HBM3_CH1_CTR_CNT 0x3D6C6C
+
+#define mmNIF_RTR_CTRL_5_E2E_AW_HBM0_CH0_CTR_WRAP 0x3D6C70
+
+#define mmNIF_RTR_CTRL_5_E2E_AW_HBM0_CH1_CTR_WRAP 0x3D6C74
+
+#define mmNIF_RTR_CTRL_5_E2E_AW_HBM1_CH0_CTR_WRAP 0x3D6C78
+
+#define mmNIF_RTR_CTRL_5_E2E_AW_HBM1_CH1_CTR_WRAP 0x3D6C7C
+
+#define mmNIF_RTR_CTRL_5_E2E_AW_HBM2_CH0_CTR_WRAP 0x3D6C80
+
+#define mmNIF_RTR_CTRL_5_E2E_AW_HBM2_CH1_CTR_WRAP 0x3D6C84
+
+#define mmNIF_RTR_CTRL_5_E2E_AW_HBM3_CH0_CTR_WRAP 0x3D6C88
+
+#define mmNIF_RTR_CTRL_5_E2E_AW_HBM3_CH1_CTR_WRAP 0x3D6C8C
+
+#define mmNIF_RTR_CTRL_5_E2E_AW_HBM0_CH0_CTR_CNT 0x3D6C90
+
+#define mmNIF_RTR_CTRL_5_E2E_AW_HBM0_CH1_CTR_CNT 0x3D6C94
+
+#define mmNIF_RTR_CTRL_5_E2E_AW_HBM1_CH0_CTR_CNT 0x3D6C98
+
+#define mmNIF_RTR_CTRL_5_E2E_AW_HBM1_CH1_CTR_CNT 0x3D6C9C
+
+#define mmNIF_RTR_CTRL_5_E2E_AW_HBM2_CH0_CTR_CNT 0x3D6CA0
+
+#define mmNIF_RTR_CTRL_5_E2E_AW_HBM2_CH1_CTR_CNT 0x3D6CA4
+
+#define mmNIF_RTR_CTRL_5_E2E_AW_HBM3_CH0_CTR_CNT 0x3D6CA8
+
+#define mmNIF_RTR_CTRL_5_E2E_AW_HBM3_CH1_CTR_CNT 0x3D6CAC
+
+#define mmNIF_RTR_CTRL_5_NL_HBM_PC_SEL_0 0x3D6CB0
+
+#define mmNIF_RTR_CTRL_5_NL_HBM_PC_SEL_1 0x3D6CB4
+
+#define mmNIF_RTR_CTRL_5_NL_HBM_PC_SEL_2 0x3D6CB8
+
+#define mmNIF_RTR_CTRL_5_NL_HBM_PC_SEL_3 0x3D6CBC
+
+#endif /* ASIC_REG_NIF_RTR_CTRL_5_REGS_H_ */
diff --git a/drivers/accel/habanalabs/include/gaudi/asic_reg/nif_rtr_ctrl_6_regs.h b/drivers/accel/habanalabs/include/gaudi/asic_reg/nif_rtr_ctrl_6_regs.h
new file mode 100644
index 0000000000..b79c59887b
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi/asic_reg/nif_rtr_ctrl_6_regs.h
@@ -0,0 +1,896 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2016-2018 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ ** DO NOT EDIT BELOW **
+ ************************************/
+
+#ifndef ASIC_REG_NIF_RTR_CTRL_6_REGS_H_
+#define ASIC_REG_NIF_RTR_CTRL_6_REGS_H_
+
+/*
+ *****************************************
+ * NIF_RTR_CTRL_6 (Prototype: RTR_CTRL)
+ *****************************************
+ */
+
+#define mmNIF_RTR_CTRL_6_PERM_SEL 0x3E6108
+
+#define mmNIF_RTR_CTRL_6_HBM_POLY_H3_0 0x3E6114
+
+#define mmNIF_RTR_CTRL_6_HBM_POLY_H3_1 0x3E6118
+
+#define mmNIF_RTR_CTRL_6_HBM_POLY_H3_2 0x3E611C
+
+#define mmNIF_RTR_CTRL_6_HBM_POLY_H3_3 0x3E6120
+
+#define mmNIF_RTR_CTRL_6_HBM_POLY_H3_4 0x3E6124
+
+#define mmNIF_RTR_CTRL_6_HBM_POLY_H3_5 0x3E6128
+
+#define mmNIF_RTR_CTRL_6_HBM_POLY_H3_6 0x3E612C
+
+#define mmNIF_RTR_CTRL_6_HBM_POLY_H3_7 0x3E6130
+
+#define mmNIF_RTR_CTRL_6_HBM_POLY_H3_8 0x3E6134
+
+#define mmNIF_RTR_CTRL_6_HBM_POLY_H3_9 0x3E6138
+
+#define mmNIF_RTR_CTRL_6_HBM_POLY_H3_10 0x3E613C
+
+#define mmNIF_RTR_CTRL_6_HBM_POLY_H3_11 0x3E6140
+
+#define mmNIF_RTR_CTRL_6_HBM_POLY_H3_12 0x3E6144
+
+#define mmNIF_RTR_CTRL_6_HBM_POLY_H3_13 0x3E6148
+
+#define mmNIF_RTR_CTRL_6_HBM_POLY_H3_14 0x3E614C
+
+#define mmNIF_RTR_CTRL_6_HBM_POLY_H3_15 0x3E6150
+
+#define mmNIF_RTR_CTRL_6_HBM_POLY_H3_16 0x3E6154
+
+#define mmNIF_RTR_CTRL_6_HBM_POLY_H3_17 0x3E6158
+
+#define mmNIF_RTR_CTRL_6_HBM_POLY_H3_18 0x3E615C
+
+#define mmNIF_RTR_CTRL_6_HBM_POLY_H3_19 0x3E6160
+
+#define mmNIF_RTR_CTRL_6_HBM_POLY_H3_20 0x3E6164
+
+#define mmNIF_RTR_CTRL_6_HBM_POLY_H3_21 0x3E6168
+
+#define mmNIF_RTR_CTRL_6_HBM_POLY_H3_22 0x3E616C
+
+#define mmNIF_RTR_CTRL_6_HBM_POLY_H3_23 0x3E6170
+
+#define mmNIF_RTR_CTRL_6_HBM_POLY_H3_24 0x3E6174
+
+#define mmNIF_RTR_CTRL_6_HBM_POLY_H3_25 0x3E6178
+
+#define mmNIF_RTR_CTRL_6_HBM_POLY_H3_26 0x3E617C
+
+#define mmNIF_RTR_CTRL_6_HBM_POLY_H3_27 0x3E6180
+
+#define mmNIF_RTR_CTRL_6_SRAM_POLY_H3_0 0x3E6184
+
+#define mmNIF_RTR_CTRL_6_SRAM_POLY_H3_1 0x3E6188
+
+#define mmNIF_RTR_CTRL_6_SRAM_POLY_H3_2 0x3E618C
+
+#define mmNIF_RTR_CTRL_6_SRAM_POLY_H3_3 0x3E6190
+
+#define mmNIF_RTR_CTRL_6_SRAM_POLY_H3_4 0x3E6194
+
+#define mmNIF_RTR_CTRL_6_SRAM_POLY_H3_5 0x3E6198
+
+#define mmNIF_RTR_CTRL_6_SRAM_POLY_H3_6 0x3E619C
+
+#define mmNIF_RTR_CTRL_6_SRAM_POLY_H3_7 0x3E61A0
+
+#define mmNIF_RTR_CTRL_6_SRAM_POLY_H3_8 0x3E61A4
+
+#define mmNIF_RTR_CTRL_6_SRAM_POLY_H3_9 0x3E61A8
+
+#define mmNIF_RTR_CTRL_6_SRAM_POLY_H3_10 0x3E61AC
+
+#define mmNIF_RTR_CTRL_6_SRAM_POLY_H3_11 0x3E61B0
+
+#define mmNIF_RTR_CTRL_6_SRAM_POLY_H3_12 0x3E61B4
+
+#define mmNIF_RTR_CTRL_6_SRAM_POLY_H3_13 0x3E61B8
+
+#define mmNIF_RTR_CTRL_6_SRAM_POLY_H3_14 0x3E61BC
+
+#define mmNIF_RTR_CTRL_6_SCRAM_SRAM_EN 0x3E626C
+
+#define mmNIF_RTR_CTRL_6_RL_HBM_EN 0x3E6274
+
+#define mmNIF_RTR_CTRL_6_RL_HBM_SAT 0x3E6278
+
+#define mmNIF_RTR_CTRL_6_RL_HBM_RST 0x3E627C
+
+#define mmNIF_RTR_CTRL_6_RL_HBM_TIMEOUT 0x3E6280
+
+#define mmNIF_RTR_CTRL_6_SCRAM_HBM_EN 0x3E6284
+
+#define mmNIF_RTR_CTRL_6_RL_PCI_EN 0x3E6288
+
+#define mmNIF_RTR_CTRL_6_RL_PCI_SAT 0x3E628C
+
+#define mmNIF_RTR_CTRL_6_RL_PCI_RST 0x3E6290
+
+#define mmNIF_RTR_CTRL_6_RL_PCI_TIMEOUT 0x3E6294
+
+#define mmNIF_RTR_CTRL_6_RL_SRAM_EN 0x3E629C
+
+#define mmNIF_RTR_CTRL_6_RL_SRAM_SAT 0x3E62A0
+
+#define mmNIF_RTR_CTRL_6_RL_SRAM_RST 0x3E62A4
+
+#define mmNIF_RTR_CTRL_6_RL_SRAM_TIMEOUT 0x3E62AC
+
+#define mmNIF_RTR_CTRL_6_RL_SRAM_RED 0x3E62B4
+
+#define mmNIF_RTR_CTRL_6_E2E_HBM_EN 0x3E62EC
+
+#define mmNIF_RTR_CTRL_6_E2E_PCI_EN 0x3E62F0
+
+#define mmNIF_RTR_CTRL_6_E2E_HBM_WR_SIZE 0x3E62F4
+
+#define mmNIF_RTR_CTRL_6_E2E_PCI_WR_SIZE 0x3E62F8
+
+#define mmNIF_RTR_CTRL_6_E2E_AW_PCI_CTR_SET_EN 0x3E6404
+
+#define mmNIF_RTR_CTRL_6_E2E_AW_PCI_CTR_SET 0x3E6408
+
+#define mmNIF_RTR_CTRL_6_E2E_AW_PCI_CTR_WRAP 0x3E640C
+
+#define mmNIF_RTR_CTRL_6_E2E_AW_PCI_CTR_CNT 0x3E6410
+
+#define mmNIF_RTR_CTRL_6_E2E_AW_HBM_CTR_SET_EN 0x3E6414
+
+#define mmNIF_RTR_CTRL_6_E2E_AW_HBM_CTR_SET 0x3E6418
+
+#define mmNIF_RTR_CTRL_6_E2E_HBM_RD_SIZE 0x3E641C
+
+#define mmNIF_RTR_CTRL_6_E2E_PCI_RD_SIZE 0x3E6420
+
+#define mmNIF_RTR_CTRL_6_E2E_AR_PCI_CTR_SET_EN 0x3E6424
+
+#define mmNIF_RTR_CTRL_6_E2E_AR_PCI_CTR_SET 0x3E6428
+
+#define mmNIF_RTR_CTRL_6_E2E_AR_PCI_CTR_WRAP 0x3E642C
+
+#define mmNIF_RTR_CTRL_6_E2E_AR_PCI_CTR_CNT 0x3E6430
+
+#define mmNIF_RTR_CTRL_6_E2E_AR_HBM_CTR_SET_EN 0x3E6434
+
+#define mmNIF_RTR_CTRL_6_E2E_AR_HBM_CTR_SET 0x3E6438
+
+#define mmNIF_RTR_CTRL_6_NL_HBM_SEL_0 0x3E6450
+
+#define mmNIF_RTR_CTRL_6_NL_HBM_SEL_1 0x3E6454
+
+#define mmNIF_RTR_CTRL_6_NON_LIN_EN 0x3E6480
+
+#define mmNIF_RTR_CTRL_6_NL_SRAM_BANK_0 0x3E6500
+
+#define mmNIF_RTR_CTRL_6_NL_SRAM_BANK_1 0x3E6504
+
+#define mmNIF_RTR_CTRL_6_NL_SRAM_BANK_2 0x3E6508
+
+#define mmNIF_RTR_CTRL_6_NL_SRAM_BANK_3 0x3E650C
+
+#define mmNIF_RTR_CTRL_6_NL_SRAM_BANK_4 0x3E6510
+
+#define mmNIF_RTR_CTRL_6_NL_SRAM_OFFSET_0 0x3E6514
+
+#define mmNIF_RTR_CTRL_6_NL_SRAM_OFFSET_1 0x3E6520
+
+#define mmNIF_RTR_CTRL_6_NL_SRAM_OFFSET_2 0x3E6524
+
+#define mmNIF_RTR_CTRL_6_NL_SRAM_OFFSET_3 0x3E6528
+
+#define mmNIF_RTR_CTRL_6_NL_SRAM_OFFSET_4 0x3E652C
+
+#define mmNIF_RTR_CTRL_6_NL_SRAM_OFFSET_5 0x3E6530
+
+#define mmNIF_RTR_CTRL_6_NL_SRAM_OFFSET_6 0x3E6534
+
+#define mmNIF_RTR_CTRL_6_NL_SRAM_OFFSET_7 0x3E6538
+
+#define mmNIF_RTR_CTRL_6_NL_SRAM_OFFSET_8 0x3E653C
+
+#define mmNIF_RTR_CTRL_6_NL_SRAM_OFFSET_9 0x3E6540
+
+#define mmNIF_RTR_CTRL_6_NL_HBM_OFFSET_0 0x3E6550
+
+#define mmNIF_RTR_CTRL_6_NL_HBM_OFFSET_1 0x3E6554
+
+#define mmNIF_RTR_CTRL_6_NL_HBM_OFFSET_2 0x3E6558
+
+#define mmNIF_RTR_CTRL_6_NL_HBM_OFFSET_3 0x3E655C
+
+#define mmNIF_RTR_CTRL_6_NL_HBM_OFFSET_4 0x3E6560
+
+#define mmNIF_RTR_CTRL_6_NL_HBM_OFFSET_5 0x3E6564
+
+#define mmNIF_RTR_CTRL_6_NL_HBM_OFFSET_6 0x3E6568
+
+#define mmNIF_RTR_CTRL_6_NL_HBM_OFFSET_7 0x3E656C
+
+#define mmNIF_RTR_CTRL_6_NL_HBM_OFFSET_8 0x3E6570
+
+#define mmNIF_RTR_CTRL_6_NL_HBM_OFFSET_9 0x3E6574
+
+#define mmNIF_RTR_CTRL_6_NL_HBM_OFFSET_10 0x3E6578
+
+#define mmNIF_RTR_CTRL_6_NL_HBM_OFFSET_11 0x3E657C
+
+#define mmNIF_RTR_CTRL_6_NL_HBM_OFFSET_12 0x3E6580
+
+#define mmNIF_RTR_CTRL_6_NL_HBM_OFFSET_13 0x3E6584
+
+#define mmNIF_RTR_CTRL_6_NL_HBM_OFFSET_14 0x3E6588
+
+#define mmNIF_RTR_CTRL_6_NL_HBM_OFFSET_15 0x3E658C
+
+#define mmNIF_RTR_CTRL_6_NL_HBM_OFFSET_16 0x3E6590
+
+#define mmNIF_RTR_CTRL_6_NL_HBM_OFFSET_17 0x3E6594
+
+#define mmNIF_RTR_CTRL_6_NL_HBM_OFFSET_18 0x3E6598
+
+#define mmNIF_RTR_CTRL_6_RANGE_SEC_BASE_LOW_AW_0 0x3E65E4
+
+#define mmNIF_RTR_CTRL_6_RANGE_SEC_BASE_LOW_AW_1 0x3E65E8
+
+#define mmNIF_RTR_CTRL_6_RANGE_SEC_BASE_LOW_AW_2 0x3E65EC
+
+#define mmNIF_RTR_CTRL_6_RANGE_SEC_BASE_LOW_AW_3 0x3E65F0
+
+#define mmNIF_RTR_CTRL_6_RANGE_SEC_BASE_LOW_AW_4 0x3E65F4
+
+#define mmNIF_RTR_CTRL_6_RANGE_SEC_BASE_LOW_AW_5 0x3E65F8
+
+#define mmNIF_RTR_CTRL_6_RANGE_SEC_BASE_LOW_AW_6 0x3E65FC
+
+#define mmNIF_RTR_CTRL_6_RANGE_SEC_BASE_LOW_AW_7 0x3E6600
+
+#define mmNIF_RTR_CTRL_6_RANGE_SEC_BASE_LOW_AW_8 0x3E6604
+
+#define mmNIF_RTR_CTRL_6_RANGE_SEC_BASE_LOW_AW_9 0x3E6608
+
+#define mmNIF_RTR_CTRL_6_RANGE_SEC_BASE_LOW_AW_10 0x3E660C
+
+#define mmNIF_RTR_CTRL_6_RANGE_SEC_BASE_LOW_AW_11 0x3E6610
+
+#define mmNIF_RTR_CTRL_6_RANGE_SEC_BASE_LOW_AW_12 0x3E6614
+
+#define mmNIF_RTR_CTRL_6_RANGE_SEC_BASE_LOW_AW_13 0x3E6618
+
+#define mmNIF_RTR_CTRL_6_RANGE_SEC_BASE_LOW_AW_14 0x3E661C
+
+#define mmNIF_RTR_CTRL_6_RANGE_SEC_BASE_LOW_AW_15 0x3E6620
+
+#define mmNIF_RTR_CTRL_6_RANGE_SEC_BASE_HIGH_AW_0 0x3E6624
+
+#define mmNIF_RTR_CTRL_6_RANGE_SEC_BASE_HIGH_AW_1 0x3E6628
+
+#define mmNIF_RTR_CTRL_6_RANGE_SEC_BASE_HIGH_AW_2 0x3E662C
+
+#define mmNIF_RTR_CTRL_6_RANGE_SEC_BASE_HIGH_AW_3 0x3E6630
+
+#define mmNIF_RTR_CTRL_6_RANGE_SEC_BASE_HIGH_AW_4 0x3E6634
+
+#define mmNIF_RTR_CTRL_6_RANGE_SEC_BASE_HIGH_AW_5 0x3E6638
+
+#define mmNIF_RTR_CTRL_6_RANGE_SEC_BASE_HIGH_AW_6 0x3E663C
+
+#define mmNIF_RTR_CTRL_6_RANGE_SEC_BASE_HIGH_AW_7 0x3E6640
+
+#define mmNIF_RTR_CTRL_6_RANGE_SEC_BASE_HIGH_AW_8 0x3E6644
+
+#define mmNIF_RTR_CTRL_6_RANGE_SEC_BASE_HIGH_AW_9 0x3E6648
+
+#define mmNIF_RTR_CTRL_6_RANGE_SEC_BASE_HIGH_AW_10 0x3E664C
+
+#define mmNIF_RTR_CTRL_6_RANGE_SEC_BASE_HIGH_AW_11 0x3E6650
+
+#define mmNIF_RTR_CTRL_6_RANGE_SEC_BASE_HIGH_AW_12 0x3E6654
+
+#define mmNIF_RTR_CTRL_6_RANGE_SEC_BASE_HIGH_AW_13 0x3E6658
+
+#define mmNIF_RTR_CTRL_6_RANGE_SEC_BASE_HIGH_AW_14 0x3E665C
+
+#define mmNIF_RTR_CTRL_6_RANGE_SEC_BASE_HIGH_AW_15 0x3E6660
+
+#define mmNIF_RTR_CTRL_6_RANGE_SEC_MASK_LOW_AW_0 0x3E6664
+
+#define mmNIF_RTR_CTRL_6_RANGE_SEC_MASK_LOW_AW_1 0x3E6668
+
+#define mmNIF_RTR_CTRL_6_RANGE_SEC_MASK_LOW_AW_2 0x3E666C
+
+#define mmNIF_RTR_CTRL_6_RANGE_SEC_MASK_LOW_AW_3 0x3E6670
+
+#define mmNIF_RTR_CTRL_6_RANGE_SEC_MASK_LOW_AW_4 0x3E6674
+
+#define mmNIF_RTR_CTRL_6_RANGE_SEC_MASK_LOW_AW_5 0x3E6678
+
+#define mmNIF_RTR_CTRL_6_RANGE_SEC_MASK_LOW_AW_6 0x3E667C
+
+#define mmNIF_RTR_CTRL_6_RANGE_SEC_MASK_LOW_AW_7 0x3E6680
+
+#define mmNIF_RTR_CTRL_6_RANGE_SEC_MASK_LOW_AW_8 0x3E6684
+
+#define mmNIF_RTR_CTRL_6_RANGE_SEC_MASK_LOW_AW_9 0x3E6688
+
+#define mmNIF_RTR_CTRL_6_RANGE_SEC_MASK_LOW_AW_10 0x3E668C
+
+#define mmNIF_RTR_CTRL_6_RANGE_SEC_MASK_LOW_AW_11 0x3E6690
+
+#define mmNIF_RTR_CTRL_6_RANGE_SEC_MASK_LOW_AW_12 0x3E6694
+
+#define mmNIF_RTR_CTRL_6_RANGE_SEC_MASK_LOW_AW_13 0x3E6698
+
+#define mmNIF_RTR_CTRL_6_RANGE_SEC_MASK_LOW_AW_14 0x3E669C
+
+#define mmNIF_RTR_CTRL_6_RANGE_SEC_MASK_LOW_AW_15 0x3E66A0
+
+#define mmNIF_RTR_CTRL_6_RANGE_SEC_MASK_HIGH_AW_0 0x3E66A4
+
+#define mmNIF_RTR_CTRL_6_RANGE_SEC_MASK_HIGH_AW_1 0x3E66A8
+
+#define mmNIF_RTR_CTRL_6_RANGE_SEC_MASK_HIGH_AW_2 0x3E66AC
+
+#define mmNIF_RTR_CTRL_6_RANGE_SEC_MASK_HIGH_AW_3 0x3E66B0
+
+#define mmNIF_RTR_CTRL_6_RANGE_SEC_MASK_HIGH_AW_4 0x3E66B4
+
+#define mmNIF_RTR_CTRL_6_RANGE_SEC_MASK_HIGH_AW_5 0x3E66B8
+
+#define mmNIF_RTR_CTRL_6_RANGE_SEC_MASK_HIGH_AW_6 0x3E66BC
+
+#define mmNIF_RTR_CTRL_6_RANGE_SEC_MASK_HIGH_AW_7 0x3E66C0
+
+#define mmNIF_RTR_CTRL_6_RANGE_SEC_MASK_HIGH_AW_8 0x3E66C4
+
+#define mmNIF_RTR_CTRL_6_RANGE_SEC_MASK_HIGH_AW_9 0x3E66C8
+
+#define mmNIF_RTR_CTRL_6_RANGE_SEC_MASK_HIGH_AW_10 0x3E66CC
+
+#define mmNIF_RTR_CTRL_6_RANGE_SEC_MASK_HIGH_AW_11 0x3E66D0
+
+#define mmNIF_RTR_CTRL_6_RANGE_SEC_MASK_HIGH_AW_12 0x3E66D4
+
+#define mmNIF_RTR_CTRL_6_RANGE_SEC_MASK_HIGH_AW_13 0x3E66D8
+
+#define mmNIF_RTR_CTRL_6_RANGE_SEC_MASK_HIGH_AW_14 0x3E66DC
+
+#define mmNIF_RTR_CTRL_6_RANGE_SEC_MASK_HIGH_AW_15 0x3E66E0
+
+#define mmNIF_RTR_CTRL_6_RANGE_PRIV_BASE_LOW_AW_0 0x3E66E4
+
+#define mmNIF_RTR_CTRL_6_RANGE_PRIV_BASE_LOW_AW_1 0x3E66E8
+
+#define mmNIF_RTR_CTRL_6_RANGE_PRIV_BASE_LOW_AW_2 0x3E66EC
+
+#define mmNIF_RTR_CTRL_6_RANGE_PRIV_BASE_LOW_AW_3 0x3E66F0
+
+#define mmNIF_RTR_CTRL_6_RANGE_PRIV_BASE_LOW_AW_4 0x3E66F4
+
+#define mmNIF_RTR_CTRL_6_RANGE_PRIV_BASE_LOW_AW_5 0x3E66F8
+
+#define mmNIF_RTR_CTRL_6_RANGE_PRIV_BASE_LOW_AW_6 0x3E66FC
+
+#define mmNIF_RTR_CTRL_6_RANGE_PRIV_BASE_LOW_AW_7 0x3E6700
+
+#define mmNIF_RTR_CTRL_6_RANGE_PRIV_BASE_LOW_AW_8 0x3E6704
+
+#define mmNIF_RTR_CTRL_6_RANGE_PRIV_BASE_LOW_AW_9 0x3E6708
+
+#define mmNIF_RTR_CTRL_6_RANGE_PRIV_BASE_LOW_AW_10 0x3E670C
+
+#define mmNIF_RTR_CTRL_6_RANGE_PRIV_BASE_LOW_AW_11 0x3E6710
+
+#define mmNIF_RTR_CTRL_6_RANGE_PRIV_BASE_LOW_AW_12 0x3E6714
+
+#define mmNIF_RTR_CTRL_6_RANGE_PRIV_BASE_LOW_AW_13 0x3E6718
+
+#define mmNIF_RTR_CTRL_6_RANGE_PRIV_BASE_LOW_AW_14 0x3E671C
+
+#define mmNIF_RTR_CTRL_6_RANGE_PRIV_BASE_LOW_AW_15 0x3E6720
+
+#define mmNIF_RTR_CTRL_6_RANGE_PRIV_BASE_HIGH_AW_0 0x3E6724
+
+#define mmNIF_RTR_CTRL_6_RANGE_PRIV_BASE_HIGH_AW_1 0x3E6728
+
+#define mmNIF_RTR_CTRL_6_RANGE_PRIV_BASE_HIGH_AW_2 0x3E672C
+
+#define mmNIF_RTR_CTRL_6_RANGE_PRIV_BASE_HIGH_AW_3 0x3E6730
+
+#define mmNIF_RTR_CTRL_6_RANGE_PRIV_BASE_HIGH_AW_4 0x3E6734
+
+#define mmNIF_RTR_CTRL_6_RANGE_PRIV_BASE_HIGH_AW_5 0x3E6738
+
+#define mmNIF_RTR_CTRL_6_RANGE_PRIV_BASE_HIGH_AW_6 0x3E673C
+
+#define mmNIF_RTR_CTRL_6_RANGE_PRIV_BASE_HIGH_AW_7 0x3E6740
+
+#define mmNIF_RTR_CTRL_6_RANGE_PRIV_BASE_HIGH_AW_8 0x3E6744
+
+#define mmNIF_RTR_CTRL_6_RANGE_PRIV_BASE_HIGH_AW_9 0x3E6748
+
+#define mmNIF_RTR_CTRL_6_RANGE_PRIV_BASE_HIGH_AW_10 0x3E674C
+
+#define mmNIF_RTR_CTRL_6_RANGE_PRIV_BASE_HIGH_AW_11 0x3E6750
+
+#define mmNIF_RTR_CTRL_6_RANGE_PRIV_BASE_HIGH_AW_12 0x3E6754
+
+#define mmNIF_RTR_CTRL_6_RANGE_PRIV_BASE_HIGH_AW_13 0x3E6758
+
+#define mmNIF_RTR_CTRL_6_RANGE_PRIV_BASE_HIGH_AW_14 0x3E675C
+
+#define mmNIF_RTR_CTRL_6_RANGE_PRIV_BASE_HIGH_AW_15 0x3E6760
+
+#define mmNIF_RTR_CTRL_6_RANGE_PRIV_MASK_LOW_AW_0 0x3E6764
+
+#define mmNIF_RTR_CTRL_6_RANGE_PRIV_MASK_LOW_AW_1 0x3E6768
+
+#define mmNIF_RTR_CTRL_6_RANGE_PRIV_MASK_LOW_AW_2 0x3E676C
+
+#define mmNIF_RTR_CTRL_6_RANGE_PRIV_MASK_LOW_AW_3 0x3E6770
+
+#define mmNIF_RTR_CTRL_6_RANGE_PRIV_MASK_LOW_AW_4 0x3E6774
+
+#define mmNIF_RTR_CTRL_6_RANGE_PRIV_MASK_LOW_AW_5 0x3E6778
+
+#define mmNIF_RTR_CTRL_6_RANGE_PRIV_MASK_LOW_AW_6 0x3E677C
+
+#define mmNIF_RTR_CTRL_6_RANGE_PRIV_MASK_LOW_AW_7 0x3E6780
+
+#define mmNIF_RTR_CTRL_6_RANGE_PRIV_MASK_LOW_AW_8 0x3E6784
+
+#define mmNIF_RTR_CTRL_6_RANGE_PRIV_MASK_LOW_AW_9 0x3E6788
+
+#define mmNIF_RTR_CTRL_6_RANGE_PRIV_MASK_LOW_AW_10 0x3E678C
+
+#define mmNIF_RTR_CTRL_6_RANGE_PRIV_MASK_LOW_AW_11 0x3E6790
+
+#define mmNIF_RTR_CTRL_6_RANGE_PRIV_MASK_LOW_AW_12 0x3E6794
+
+#define mmNIF_RTR_CTRL_6_RANGE_PRIV_MASK_LOW_AW_13 0x3E6798
+
+#define mmNIF_RTR_CTRL_6_RANGE_PRIV_MASK_LOW_AW_14 0x3E679C
+
+#define mmNIF_RTR_CTRL_6_RANGE_PRIV_MASK_LOW_AW_15 0x3E67A0
+
+#define mmNIF_RTR_CTRL_6_RANGE_PRIV_MASK_HIGH_AW_0 0x3E67A4
+
+#define mmNIF_RTR_CTRL_6_RANGE_PRIV_MASK_HIGH_AW_1 0x3E67A8
+
+#define mmNIF_RTR_CTRL_6_RANGE_PRIV_MASK_HIGH_AW_2 0x3E67AC
+
+#define mmNIF_RTR_CTRL_6_RANGE_PRIV_MASK_HIGH_AW_3 0x3E67B0
+
+#define mmNIF_RTR_CTRL_6_RANGE_PRIV_MASK_HIGH_AW_4 0x3E67B4
+
+#define mmNIF_RTR_CTRL_6_RANGE_PRIV_MASK_HIGH_AW_5 0x3E67B8
+
+#define mmNIF_RTR_CTRL_6_RANGE_PRIV_MASK_HIGH_AW_6 0x3E67BC
+
+#define mmNIF_RTR_CTRL_6_RANGE_PRIV_MASK_HIGH_AW_7 0x3E67C0
+
+#define mmNIF_RTR_CTRL_6_RANGE_PRIV_MASK_HIGH_AW_8 0x3E67C4
+
+#define mmNIF_RTR_CTRL_6_RANGE_PRIV_MASK_HIGH_AW_9 0x3E67C8
+
+#define mmNIF_RTR_CTRL_6_RANGE_PRIV_MASK_HIGH_AW_10 0x3E67CC
+
+#define mmNIF_RTR_CTRL_6_RANGE_PRIV_MASK_HIGH_AW_11 0x3E67D0
+
+#define mmNIF_RTR_CTRL_6_RANGE_PRIV_MASK_HIGH_AW_12 0x3E67D4
+
+#define mmNIF_RTR_CTRL_6_RANGE_PRIV_MASK_HIGH_AW_13 0x3E67D8
+
+#define mmNIF_RTR_CTRL_6_RANGE_PRIV_MASK_HIGH_AW_14 0x3E67DC
+
+#define mmNIF_RTR_CTRL_6_RANGE_PRIV_MASK_HIGH_AW_15 0x3E67E0
+
+#define mmNIF_RTR_CTRL_6_RANGE_SEC_BASE_LOW_AR_0 0x3E6824
+
+#define mmNIF_RTR_CTRL_6_RANGE_SEC_BASE_LOW_AR_1 0x3E6828
+
+#define mmNIF_RTR_CTRL_6_RANGE_SEC_BASE_LOW_AR_2 0x3E682C
+
+#define mmNIF_RTR_CTRL_6_RANGE_SEC_BASE_LOW_AR_3 0x3E6830
+
+#define mmNIF_RTR_CTRL_6_RANGE_SEC_BASE_LOW_AR_4 0x3E6834
+
+#define mmNIF_RTR_CTRL_6_RANGE_SEC_BASE_LOW_AR_5 0x3E6838
+
+#define mmNIF_RTR_CTRL_6_RANGE_SEC_BASE_LOW_AR_6 0x3E683C
+
+#define mmNIF_RTR_CTRL_6_RANGE_SEC_BASE_LOW_AR_7 0x3E6840
+
+#define mmNIF_RTR_CTRL_6_RANGE_SEC_BASE_LOW_AR_8 0x3E6844
+
+#define mmNIF_RTR_CTRL_6_RANGE_SEC_BASE_LOW_AR_9 0x3E6848
+
+#define mmNIF_RTR_CTRL_6_RANGE_SEC_BASE_LOW_AR_10 0x3E684C
+
+#define mmNIF_RTR_CTRL_6_RANGE_SEC_BASE_LOW_AR_11 0x3E6850
+
+#define mmNIF_RTR_CTRL_6_RANGE_SEC_BASE_LOW_AR_12 0x3E6854
+
+#define mmNIF_RTR_CTRL_6_RANGE_SEC_BASE_LOW_AR_13 0x3E6858
+
+#define mmNIF_RTR_CTRL_6_RANGE_SEC_BASE_LOW_AR_14 0x3E685C
+
+#define mmNIF_RTR_CTRL_6_RANGE_SEC_BASE_LOW_AR_15 0x3E6860
+
+#define mmNIF_RTR_CTRL_6_RANGE_SEC_BASE_HIGH_AR_0 0x3E6864
+
+#define mmNIF_RTR_CTRL_6_RANGE_SEC_BASE_HIGH_AR_1 0x3E6868
+
+#define mmNIF_RTR_CTRL_6_RANGE_SEC_BASE_HIGH_AR_2 0x3E686C
+
+#define mmNIF_RTR_CTRL_6_RANGE_SEC_BASE_HIGH_AR_3 0x3E6870
+
+#define mmNIF_RTR_CTRL_6_RANGE_SEC_BASE_HIGH_AR_4 0x3E6874
+
+#define mmNIF_RTR_CTRL_6_RANGE_SEC_BASE_HIGH_AR_5 0x3E6878
+
+#define mmNIF_RTR_CTRL_6_RANGE_SEC_BASE_HIGH_AR_6 0x3E687C
+
+#define mmNIF_RTR_CTRL_6_RANGE_SEC_BASE_HIGH_AR_7 0x3E6880
+
+#define mmNIF_RTR_CTRL_6_RANGE_SEC_BASE_HIGH_AR_8 0x3E6884
+
+#define mmNIF_RTR_CTRL_6_RANGE_SEC_BASE_HIGH_AR_9 0x3E6888
+
+#define mmNIF_RTR_CTRL_6_RANGE_SEC_BASE_HIGH_AR_10 0x3E688C
+
+#define mmNIF_RTR_CTRL_6_RANGE_SEC_BASE_HIGH_AR_11 0x3E6890
+
+#define mmNIF_RTR_CTRL_6_RANGE_SEC_BASE_HIGH_AR_12 0x3E6894
+
+#define mmNIF_RTR_CTRL_6_RANGE_SEC_BASE_HIGH_AR_13 0x3E6898
+
+#define mmNIF_RTR_CTRL_6_RANGE_SEC_BASE_HIGH_AR_14 0x3E689C
+
+#define mmNIF_RTR_CTRL_6_RANGE_SEC_BASE_HIGH_AR_15 0x3E68A0
+
+#define mmNIF_RTR_CTRL_6_RANGE_SEC_MASK_LOW_AR_0 0x3E68A4
+
+#define mmNIF_RTR_CTRL_6_RANGE_SEC_MASK_LOW_AR_1 0x3E68A8
+
+#define mmNIF_RTR_CTRL_6_RANGE_SEC_MASK_LOW_AR_2 0x3E68AC
+
+#define mmNIF_RTR_CTRL_6_RANGE_SEC_MASK_LOW_AR_3 0x3E68B0
+
+#define mmNIF_RTR_CTRL_6_RANGE_SEC_MASK_LOW_AR_4 0x3E68B4
+
+#define mmNIF_RTR_CTRL_6_RANGE_SEC_MASK_LOW_AR_5 0x3E68B8
+
+#define mmNIF_RTR_CTRL_6_RANGE_SEC_MASK_LOW_AR_6 0x3E68BC
+
+#define mmNIF_RTR_CTRL_6_RANGE_SEC_MASK_LOW_AR_7 0x3E68C0
+
+#define mmNIF_RTR_CTRL_6_RANGE_SEC_MASK_LOW_AR_8 0x3E68C4
+
+#define mmNIF_RTR_CTRL_6_RANGE_SEC_MASK_LOW_AR_9 0x3E68C8
+
+#define mmNIF_RTR_CTRL_6_RANGE_SEC_MASK_LOW_AR_10 0x3E68CC
+
+#define mmNIF_RTR_CTRL_6_RANGE_SEC_MASK_LOW_AR_11 0x3E68D0
+
+#define mmNIF_RTR_CTRL_6_RANGE_SEC_MASK_LOW_AR_12 0x3E68D4
+
+#define mmNIF_RTR_CTRL_6_RANGE_SEC_MASK_LOW_AR_13 0x3E68D8
+
+#define mmNIF_RTR_CTRL_6_RANGE_SEC_MASK_LOW_AR_14 0x3E68DC
+
+#define mmNIF_RTR_CTRL_6_RANGE_SEC_MASK_LOW_AR_15 0x3E68E0
+
+#define mmNIF_RTR_CTRL_6_RANGE_SEC_MASK_HIGH_AR_0 0x3E68E4
+
+#define mmNIF_RTR_CTRL_6_RANGE_SEC_MASK_HIGH_AR_1 0x3E68E8
+
+#define mmNIF_RTR_CTRL_6_RANGE_SEC_MASK_HIGH_AR_2 0x3E68EC
+
+#define mmNIF_RTR_CTRL_6_RANGE_SEC_MASK_HIGH_AR_3 0x3E68F0
+
+#define mmNIF_RTR_CTRL_6_RANGE_SEC_MASK_HIGH_AR_4 0x3E68F4
+
+#define mmNIF_RTR_CTRL_6_RANGE_SEC_MASK_HIGH_AR_5 0x3E68F8
+
+#define mmNIF_RTR_CTRL_6_RANGE_SEC_MASK_HIGH_AR_6 0x3E68FC
+
+#define mmNIF_RTR_CTRL_6_RANGE_SEC_MASK_HIGH_AR_7 0x3E6900
+
+#define mmNIF_RTR_CTRL_6_RANGE_SEC_MASK_HIGH_AR_8 0x3E6904
+
+#define mmNIF_RTR_CTRL_6_RANGE_SEC_MASK_HIGH_AR_9 0x3E6908
+
+#define mmNIF_RTR_CTRL_6_RANGE_SEC_MASK_HIGH_AR_10 0x3E690C
+
+#define mmNIF_RTR_CTRL_6_RANGE_SEC_MASK_HIGH_AR_11 0x3E6910
+
+#define mmNIF_RTR_CTRL_6_RANGE_SEC_MASK_HIGH_AR_12 0x3E6914
+
+#define mmNIF_RTR_CTRL_6_RANGE_SEC_MASK_HIGH_AR_13 0x3E6918
+
+#define mmNIF_RTR_CTRL_6_RANGE_SEC_MASK_HIGH_AR_14 0x3E691C
+
+#define mmNIF_RTR_CTRL_6_RANGE_SEC_MASK_HIGH_AR_15 0x3E6920
+
+#define mmNIF_RTR_CTRL_6_RANGE_PRIV_BASE_LOW_AR_0 0x3E6924
+
+#define mmNIF_RTR_CTRL_6_RANGE_PRIV_BASE_LOW_AR_1 0x3E6928
+
+#define mmNIF_RTR_CTRL_6_RANGE_PRIV_BASE_LOW_AR_2 0x3E692C
+
+#define mmNIF_RTR_CTRL_6_RANGE_PRIV_BASE_LOW_AR_3 0x3E6930
+
+#define mmNIF_RTR_CTRL_6_RANGE_PRIV_BASE_LOW_AR_4 0x3E6934
+
+#define mmNIF_RTR_CTRL_6_RANGE_PRIV_BASE_LOW_AR_5 0x3E6938
+
+#define mmNIF_RTR_CTRL_6_RANGE_PRIV_BASE_LOW_AR_6 0x3E693C
+
+#define mmNIF_RTR_CTRL_6_RANGE_PRIV_BASE_LOW_AR_7 0x3E6940
+
+#define mmNIF_RTR_CTRL_6_RANGE_PRIV_BASE_LOW_AR_8 0x3E6944
+
+#define mmNIF_RTR_CTRL_6_RANGE_PRIV_BASE_LOW_AR_9 0x3E6948
+
+#define mmNIF_RTR_CTRL_6_RANGE_PRIV_BASE_LOW_AR_10 0x3E694C
+
+#define mmNIF_RTR_CTRL_6_RANGE_PRIV_BASE_LOW_AR_11 0x3E6950
+
+#define mmNIF_RTR_CTRL_6_RANGE_PRIV_BASE_LOW_AR_12 0x3E6954
+
+#define mmNIF_RTR_CTRL_6_RANGE_PRIV_BASE_LOW_AR_13 0x3E6958
+
+#define mmNIF_RTR_CTRL_6_RANGE_PRIV_BASE_LOW_AR_14 0x3E695C
+
+#define mmNIF_RTR_CTRL_6_RANGE_PRIV_BASE_LOW_AR_15 0x3E6960
+
+#define mmNIF_RTR_CTRL_6_RANGE_PRIV_BASE_HIGH_AR_0 0x3E6964
+
+#define mmNIF_RTR_CTRL_6_RANGE_PRIV_BASE_HIGH_AR_1 0x3E6968
+
+#define mmNIF_RTR_CTRL_6_RANGE_PRIV_BASE_HIGH_AR_2 0x3E696C
+
+#define mmNIF_RTR_CTRL_6_RANGE_PRIV_BASE_HIGH_AR_3 0x3E6970
+
+#define mmNIF_RTR_CTRL_6_RANGE_PRIV_BASE_HIGH_AR_4 0x3E6974
+
+#define mmNIF_RTR_CTRL_6_RANGE_PRIV_BASE_HIGH_AR_5 0x3E6978
+
+#define mmNIF_RTR_CTRL_6_RANGE_PRIV_BASE_HIGH_AR_6 0x3E697C
+
+#define mmNIF_RTR_CTRL_6_RANGE_PRIV_BASE_HIGH_AR_7 0x3E6980
+
+#define mmNIF_RTR_CTRL_6_RANGE_PRIV_BASE_HIGH_AR_8 0x3E6984
+
+#define mmNIF_RTR_CTRL_6_RANGE_PRIV_BASE_HIGH_AR_9 0x3E6988
+
+#define mmNIF_RTR_CTRL_6_RANGE_PRIV_BASE_HIGH_AR_10 0x3E698C
+
+#define mmNIF_RTR_CTRL_6_RANGE_PRIV_BASE_HIGH_AR_11 0x3E6990
+
+#define mmNIF_RTR_CTRL_6_RANGE_PRIV_BASE_HIGH_AR_12 0x3E6994
+
+#define mmNIF_RTR_CTRL_6_RANGE_PRIV_BASE_HIGH_AR_13 0x3E6998
+
+#define mmNIF_RTR_CTRL_6_RANGE_PRIV_BASE_HIGH_AR_14 0x3E699C
+
+#define mmNIF_RTR_CTRL_6_RANGE_PRIV_BASE_HIGH_AR_15 0x3E69A0
+
+#define mmNIF_RTR_CTRL_6_RANGE_PRIV_MASK_LOW_AR_0 0x3E69A4
+
+#define mmNIF_RTR_CTRL_6_RANGE_PRIV_MASK_LOW_AR_1 0x3E69A8
+
+#define mmNIF_RTR_CTRL_6_RANGE_PRIV_MASK_LOW_AR_2 0x3E69AC
+
+#define mmNIF_RTR_CTRL_6_RANGE_PRIV_MASK_LOW_AR_3 0x3E69B0
+
+#define mmNIF_RTR_CTRL_6_RANGE_PRIV_MASK_LOW_AR_4 0x3E69B4
+
+#define mmNIF_RTR_CTRL_6_RANGE_PRIV_MASK_LOW_AR_5 0x3E69B8
+
+#define mmNIF_RTR_CTRL_6_RANGE_PRIV_MASK_LOW_AR_6 0x3E69BC
+
+#define mmNIF_RTR_CTRL_6_RANGE_PRIV_MASK_LOW_AR_7 0x3E69C0
+
+#define mmNIF_RTR_CTRL_6_RANGE_PRIV_MASK_LOW_AR_8 0x3E69C4
+
+#define mmNIF_RTR_CTRL_6_RANGE_PRIV_MASK_LOW_AR_9 0x3E69C8
+
+#define mmNIF_RTR_CTRL_6_RANGE_PRIV_MASK_LOW_AR_10 0x3E69CC
+
+#define mmNIF_RTR_CTRL_6_RANGE_PRIV_MASK_LOW_AR_11 0x3E69D0
+
+#define mmNIF_RTR_CTRL_6_RANGE_PRIV_MASK_LOW_AR_12 0x3E69D4
+
+#define mmNIF_RTR_CTRL_6_RANGE_PRIV_MASK_LOW_AR_13 0x3E69D8
+
+#define mmNIF_RTR_CTRL_6_RANGE_PRIV_MASK_LOW_AR_14 0x3E69DC
+
+#define mmNIF_RTR_CTRL_6_RANGE_PRIV_MASK_LOW_AR_15 0x3E69E0
+
+#define mmNIF_RTR_CTRL_6_RANGE_PRIV_MASK_HIGH_AR_0 0x3E69E4
+
+#define mmNIF_RTR_CTRL_6_RANGE_PRIV_MASK_HIGH_AR_1 0x3E69E8
+
+#define mmNIF_RTR_CTRL_6_RANGE_PRIV_MASK_HIGH_AR_2 0x3E69EC
+
+#define mmNIF_RTR_CTRL_6_RANGE_PRIV_MASK_HIGH_AR_3 0x3E69F0
+
+#define mmNIF_RTR_CTRL_6_RANGE_PRIV_MASK_HIGH_AR_4 0x3E69F4
+
+#define mmNIF_RTR_CTRL_6_RANGE_PRIV_MASK_HIGH_AR_5 0x3E69F8
+
+#define mmNIF_RTR_CTRL_6_RANGE_PRIV_MASK_HIGH_AR_6 0x3E69FC
+
+#define mmNIF_RTR_CTRL_6_RANGE_PRIV_MASK_HIGH_AR_7 0x3E6A00
+
+#define mmNIF_RTR_CTRL_6_RANGE_PRIV_MASK_HIGH_AR_8 0x3E6A04
+
+#define mmNIF_RTR_CTRL_6_RANGE_PRIV_MASK_HIGH_AR_9 0x3E6A08
+
+#define mmNIF_RTR_CTRL_6_RANGE_PRIV_MASK_HIGH_AR_10 0x3E6A0C
+
+#define mmNIF_RTR_CTRL_6_RANGE_PRIV_MASK_HIGH_AR_11 0x3E6A10
+
+#define mmNIF_RTR_CTRL_6_RANGE_PRIV_MASK_HIGH_AR_12 0x3E6A14
+
+#define mmNIF_RTR_CTRL_6_RANGE_PRIV_MASK_HIGH_AR_13 0x3E6A18
+
+#define mmNIF_RTR_CTRL_6_RANGE_PRIV_MASK_HIGH_AR_14 0x3E6A1C
+
+#define mmNIF_RTR_CTRL_6_RANGE_PRIV_MASK_HIGH_AR_15 0x3E6A20
+
+#define mmNIF_RTR_CTRL_6_RANGE_SEC_HIT_AW 0x3E6A64
+
+#define mmNIF_RTR_CTRL_6_RANGE_SEC_HIT_AR 0x3E6A68
+
+#define mmNIF_RTR_CTRL_6_RANGE_PRIV_HIT_AW 0x3E6A6C
+
+#define mmNIF_RTR_CTRL_6_RANGE_PRIV_HIT_AR 0x3E6A70
+
+#define mmNIF_RTR_CTRL_6_RGL_CFG 0x3E6B64
+
+#define mmNIF_RTR_CTRL_6_RGL_SHIFT 0x3E6B68
+
+#define mmNIF_RTR_CTRL_6_RGL_EXPECTED_LAT_0 0x3E6B6C
+
+#define mmNIF_RTR_CTRL_6_RGL_EXPECTED_LAT_1 0x3E6B70
+
+#define mmNIF_RTR_CTRL_6_RGL_EXPECTED_LAT_2 0x3E6B74
+
+#define mmNIF_RTR_CTRL_6_RGL_EXPECTED_LAT_3 0x3E6B78
+
+#define mmNIF_RTR_CTRL_6_RGL_EXPECTED_LAT_4 0x3E6B7C
+
+#define mmNIF_RTR_CTRL_6_RGL_EXPECTED_LAT_5 0x3E6B80
+
+#define mmNIF_RTR_CTRL_6_RGL_EXPECTED_LAT_6 0x3E6B84
+
+#define mmNIF_RTR_CTRL_6_RGL_EXPECTED_LAT_7 0x3E6B88
+
+#define mmNIF_RTR_CTRL_6_RGL_TOKEN_0 0x3E6BAC
+
+#define mmNIF_RTR_CTRL_6_RGL_TOKEN_1 0x3E6BB0
+
+#define mmNIF_RTR_CTRL_6_RGL_TOKEN_2 0x3E6BB4
+
+#define mmNIF_RTR_CTRL_6_RGL_TOKEN_3 0x3E6BB8
+
+#define mmNIF_RTR_CTRL_6_RGL_TOKEN_4 0x3E6BBC
+
+#define mmNIF_RTR_CTRL_6_RGL_TOKEN_5 0x3E6BC0
+
+#define mmNIF_RTR_CTRL_6_RGL_TOKEN_6 0x3E6BC4
+
+#define mmNIF_RTR_CTRL_6_RGL_TOKEN_7 0x3E6BC8
+
+#define mmNIF_RTR_CTRL_6_RGL_BANK_ID_0 0x3E6BEC
+
+#define mmNIF_RTR_CTRL_6_RGL_BANK_ID_1 0x3E6BF0
+
+#define mmNIF_RTR_CTRL_6_RGL_BANK_ID_2 0x3E6BF4
+
+#define mmNIF_RTR_CTRL_6_RGL_BANK_ID_3 0x3E6BF8
+
+#define mmNIF_RTR_CTRL_6_RGL_BANK_ID_4 0x3E6BFC
+
+#define mmNIF_RTR_CTRL_6_RGL_BANK_ID_5 0x3E6C00
+
+#define mmNIF_RTR_CTRL_6_RGL_BANK_ID_6 0x3E6C04
+
+#define mmNIF_RTR_CTRL_6_RGL_BANK_ID_7 0x3E6C08
+
+#define mmNIF_RTR_CTRL_6_RGL_WDT 0x3E6C2C
+
+#define mmNIF_RTR_CTRL_6_E2E_AR_HBM0_CH0_CTR_WRAP 0x3E6C30
+
+#define mmNIF_RTR_CTRL_6_E2E_AR_HBM0_CH1_CTR_WRAP 0x3E6C34
+
+#define mmNIF_RTR_CTRL_6_E2E_AR_HBM1_CH0_CTR_WRAP 0x3E6C38
+
+#define mmNIF_RTR_CTRL_6_E2E_AR_HBM1_CH1_CTR_WRAP 0x3E6C3C
+
+#define mmNIF_RTR_CTRL_6_E2E_AR_HBM2_CH0_CTR_WRAP 0x3E6C40
+
+#define mmNIF_RTR_CTRL_6_E2E_AR_HBM2_CH1_CTR_WRAP 0x3E6C44
+
+#define mmNIF_RTR_CTRL_6_E2E_AR_HBM3_CH0_CTR_WRAP 0x3E6C48
+
+#define mmNIF_RTR_CTRL_6_E2E_AR_HBM3_CH1_CTR_WRAP 0x3E6C4C
+
+#define mmNIF_RTR_CTRL_6_E2E_AR_HBM0_CH0_CTR_CNT 0x3E6C50
+
+#define mmNIF_RTR_CTRL_6_E2E_AR_HBM0_CH1_CTR_CNT 0x3E6C54
+
+#define mmNIF_RTR_CTRL_6_E2E_AR_HBM1_CH0_CTR_CNT 0x3E6C58
+
+#define mmNIF_RTR_CTRL_6_E2E_AR_HBM1_CH1_CTR_CNT 0x3E6C5C
+
+#define mmNIF_RTR_CTRL_6_E2E_AR_HBM2_CH0_CTR_CNT 0x3E6C60
+
+#define mmNIF_RTR_CTRL_6_E2E_AR_HBM2_CH1_CTR_CNT 0x3E6C64
+
+#define mmNIF_RTR_CTRL_6_E2E_AR_HBM3_CH0_CTR_CNT 0x3E6C68
+
+#define mmNIF_RTR_CTRL_6_E2E_AR_HBM3_CH1_CTR_CNT 0x3E6C6C
+
+#define mmNIF_RTR_CTRL_6_E2E_AW_HBM0_CH0_CTR_WRAP 0x3E6C70
+
+#define mmNIF_RTR_CTRL_6_E2E_AW_HBM0_CH1_CTR_WRAP 0x3E6C74
+
+#define mmNIF_RTR_CTRL_6_E2E_AW_HBM1_CH0_CTR_WRAP 0x3E6C78
+
+#define mmNIF_RTR_CTRL_6_E2E_AW_HBM1_CH1_CTR_WRAP 0x3E6C7C
+
+#define mmNIF_RTR_CTRL_6_E2E_AW_HBM2_CH0_CTR_WRAP 0x3E6C80
+
+#define mmNIF_RTR_CTRL_6_E2E_AW_HBM2_CH1_CTR_WRAP 0x3E6C84
+
+#define mmNIF_RTR_CTRL_6_E2E_AW_HBM3_CH0_CTR_WRAP 0x3E6C88
+
+#define mmNIF_RTR_CTRL_6_E2E_AW_HBM3_CH1_CTR_WRAP 0x3E6C8C
+
+#define mmNIF_RTR_CTRL_6_E2E_AW_HBM0_CH0_CTR_CNT 0x3E6C90
+
+#define mmNIF_RTR_CTRL_6_E2E_AW_HBM0_CH1_CTR_CNT 0x3E6C94
+
+#define mmNIF_RTR_CTRL_6_E2E_AW_HBM1_CH0_CTR_CNT 0x3E6C98
+
+#define mmNIF_RTR_CTRL_6_E2E_AW_HBM1_CH1_CTR_CNT 0x3E6C9C
+
+#define mmNIF_RTR_CTRL_6_E2E_AW_HBM2_CH0_CTR_CNT 0x3E6CA0
+
+#define mmNIF_RTR_CTRL_6_E2E_AW_HBM2_CH1_CTR_CNT 0x3E6CA4
+
+#define mmNIF_RTR_CTRL_6_E2E_AW_HBM3_CH0_CTR_CNT 0x3E6CA8
+
+#define mmNIF_RTR_CTRL_6_E2E_AW_HBM3_CH1_CTR_CNT 0x3E6CAC
+
+#define mmNIF_RTR_CTRL_6_NL_HBM_PC_SEL_0 0x3E6CB0
+
+#define mmNIF_RTR_CTRL_6_NL_HBM_PC_SEL_1 0x3E6CB4
+
+#define mmNIF_RTR_CTRL_6_NL_HBM_PC_SEL_2 0x3E6CB8
+
+#define mmNIF_RTR_CTRL_6_NL_HBM_PC_SEL_3 0x3E6CBC
+
+#endif /* ASIC_REG_NIF_RTR_CTRL_6_REGS_H_ */
diff --git a/drivers/accel/habanalabs/include/gaudi/asic_reg/nif_rtr_ctrl_7_regs.h b/drivers/accel/habanalabs/include/gaudi/asic_reg/nif_rtr_ctrl_7_regs.h
new file mode 100644
index 0000000000..3a6a34ba29
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi/asic_reg/nif_rtr_ctrl_7_regs.h
@@ -0,0 +1,896 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2016-2018 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ ** DO NOT EDIT BELOW **
+ ************************************/
+
+#ifndef ASIC_REG_NIF_RTR_CTRL_7_REGS_H_
+#define ASIC_REG_NIF_RTR_CTRL_7_REGS_H_
+
+/*
+ *****************************************
+ * NIF_RTR_CTRL_7 (Prototype: RTR_CTRL)
+ *****************************************
+ */
+
+#define mmNIF_RTR_CTRL_7_PERM_SEL 0x3F6108
+
+#define mmNIF_RTR_CTRL_7_HBM_POLY_H3_0 0x3F6114
+
+#define mmNIF_RTR_CTRL_7_HBM_POLY_H3_1 0x3F6118
+
+#define mmNIF_RTR_CTRL_7_HBM_POLY_H3_2 0x3F611C
+
+#define mmNIF_RTR_CTRL_7_HBM_POLY_H3_3 0x3F6120
+
+#define mmNIF_RTR_CTRL_7_HBM_POLY_H3_4 0x3F6124
+
+#define mmNIF_RTR_CTRL_7_HBM_POLY_H3_5 0x3F6128
+
+#define mmNIF_RTR_CTRL_7_HBM_POLY_H3_6 0x3F612C
+
+#define mmNIF_RTR_CTRL_7_HBM_POLY_H3_7 0x3F6130
+
+#define mmNIF_RTR_CTRL_7_HBM_POLY_H3_8 0x3F6134
+
+#define mmNIF_RTR_CTRL_7_HBM_POLY_H3_9 0x3F6138
+
+#define mmNIF_RTR_CTRL_7_HBM_POLY_H3_10 0x3F613C
+
+#define mmNIF_RTR_CTRL_7_HBM_POLY_H3_11 0x3F6140
+
+#define mmNIF_RTR_CTRL_7_HBM_POLY_H3_12 0x3F6144
+
+#define mmNIF_RTR_CTRL_7_HBM_POLY_H3_13 0x3F6148
+
+#define mmNIF_RTR_CTRL_7_HBM_POLY_H3_14 0x3F614C
+
+#define mmNIF_RTR_CTRL_7_HBM_POLY_H3_15 0x3F6150
+
+#define mmNIF_RTR_CTRL_7_HBM_POLY_H3_16 0x3F6154
+
+#define mmNIF_RTR_CTRL_7_HBM_POLY_H3_17 0x3F6158
+
+#define mmNIF_RTR_CTRL_7_HBM_POLY_H3_18 0x3F615C
+
+#define mmNIF_RTR_CTRL_7_HBM_POLY_H3_19 0x3F6160
+
+#define mmNIF_RTR_CTRL_7_HBM_POLY_H3_20 0x3F6164
+
+#define mmNIF_RTR_CTRL_7_HBM_POLY_H3_21 0x3F6168
+
+#define mmNIF_RTR_CTRL_7_HBM_POLY_H3_22 0x3F616C
+
+#define mmNIF_RTR_CTRL_7_HBM_POLY_H3_23 0x3F6170
+
+#define mmNIF_RTR_CTRL_7_HBM_POLY_H3_24 0x3F6174
+
+#define mmNIF_RTR_CTRL_7_HBM_POLY_H3_25 0x3F6178
+
+#define mmNIF_RTR_CTRL_7_HBM_POLY_H3_26 0x3F617C
+
+#define mmNIF_RTR_CTRL_7_HBM_POLY_H3_27 0x3F6180
+
+#define mmNIF_RTR_CTRL_7_SRAM_POLY_H3_0 0x3F6184
+
+#define mmNIF_RTR_CTRL_7_SRAM_POLY_H3_1 0x3F6188
+
+#define mmNIF_RTR_CTRL_7_SRAM_POLY_H3_2 0x3F618C
+
+#define mmNIF_RTR_CTRL_7_SRAM_POLY_H3_3 0x3F6190
+
+#define mmNIF_RTR_CTRL_7_SRAM_POLY_H3_4 0x3F6194
+
+#define mmNIF_RTR_CTRL_7_SRAM_POLY_H3_5 0x3F6198
+
+#define mmNIF_RTR_CTRL_7_SRAM_POLY_H3_6 0x3F619C
+
+#define mmNIF_RTR_CTRL_7_SRAM_POLY_H3_7 0x3F61A0
+
+#define mmNIF_RTR_CTRL_7_SRAM_POLY_H3_8 0x3F61A4
+
+#define mmNIF_RTR_CTRL_7_SRAM_POLY_H3_9 0x3F61A8
+
+#define mmNIF_RTR_CTRL_7_SRAM_POLY_H3_10 0x3F61AC
+
+#define mmNIF_RTR_CTRL_7_SRAM_POLY_H3_11 0x3F61B0
+
+#define mmNIF_RTR_CTRL_7_SRAM_POLY_H3_12 0x3F61B4
+
+#define mmNIF_RTR_CTRL_7_SRAM_POLY_H3_13 0x3F61B8
+
+#define mmNIF_RTR_CTRL_7_SRAM_POLY_H3_14 0x3F61BC
+
+#define mmNIF_RTR_CTRL_7_SCRAM_SRAM_EN 0x3F626C
+
+#define mmNIF_RTR_CTRL_7_RL_HBM_EN 0x3F6274
+
+#define mmNIF_RTR_CTRL_7_RL_HBM_SAT 0x3F6278
+
+#define mmNIF_RTR_CTRL_7_RL_HBM_RST 0x3F627C
+
+#define mmNIF_RTR_CTRL_7_RL_HBM_TIMEOUT 0x3F6280
+
+#define mmNIF_RTR_CTRL_7_SCRAM_HBM_EN 0x3F6284
+
+#define mmNIF_RTR_CTRL_7_RL_PCI_EN 0x3F6288
+
+#define mmNIF_RTR_CTRL_7_RL_PCI_SAT 0x3F628C
+
+#define mmNIF_RTR_CTRL_7_RL_PCI_RST 0x3F6290
+
+#define mmNIF_RTR_CTRL_7_RL_PCI_TIMEOUT 0x3F6294
+
+#define mmNIF_RTR_CTRL_7_RL_SRAM_EN 0x3F629C
+
+#define mmNIF_RTR_CTRL_7_RL_SRAM_SAT 0x3F62A0
+
+#define mmNIF_RTR_CTRL_7_RL_SRAM_RST 0x3F62A4
+
+#define mmNIF_RTR_CTRL_7_RL_SRAM_TIMEOUT 0x3F62AC
+
+#define mmNIF_RTR_CTRL_7_RL_SRAM_RED 0x3F62B4
+
+#define mmNIF_RTR_CTRL_7_E2E_HBM_EN 0x3F62EC
+
+#define mmNIF_RTR_CTRL_7_E2E_PCI_EN 0x3F62F0
+
+#define mmNIF_RTR_CTRL_7_E2E_HBM_WR_SIZE 0x3F62F4
+
+#define mmNIF_RTR_CTRL_7_E2E_PCI_WR_SIZE 0x3F62F8
+
+#define mmNIF_RTR_CTRL_7_E2E_AW_PCI_CTR_SET_EN 0x3F6404
+
+#define mmNIF_RTR_CTRL_7_E2E_AW_PCI_CTR_SET 0x3F6408
+
+#define mmNIF_RTR_CTRL_7_E2E_AW_PCI_CTR_WRAP 0x3F640C
+
+#define mmNIF_RTR_CTRL_7_E2E_AW_PCI_CTR_CNT 0x3F6410
+
+#define mmNIF_RTR_CTRL_7_E2E_AW_HBM_CTR_SET_EN 0x3F6414
+
+#define mmNIF_RTR_CTRL_7_E2E_AW_HBM_CTR_SET 0x3F6418
+
+#define mmNIF_RTR_CTRL_7_E2E_HBM_RD_SIZE 0x3F641C
+
+#define mmNIF_RTR_CTRL_7_E2E_PCI_RD_SIZE 0x3F6420
+
+#define mmNIF_RTR_CTRL_7_E2E_AR_PCI_CTR_SET_EN 0x3F6424
+
+#define mmNIF_RTR_CTRL_7_E2E_AR_PCI_CTR_SET 0x3F6428
+
+#define mmNIF_RTR_CTRL_7_E2E_AR_PCI_CTR_WRAP 0x3F642C
+
+#define mmNIF_RTR_CTRL_7_E2E_AR_PCI_CTR_CNT 0x3F6430
+
+#define mmNIF_RTR_CTRL_7_E2E_AR_HBM_CTR_SET_EN 0x3F6434
+
+#define mmNIF_RTR_CTRL_7_E2E_AR_HBM_CTR_SET 0x3F6438
+
+#define mmNIF_RTR_CTRL_7_NL_HBM_SEL_0 0x3F6450
+
+#define mmNIF_RTR_CTRL_7_NL_HBM_SEL_1 0x3F6454
+
+#define mmNIF_RTR_CTRL_7_NON_LIN_EN 0x3F6480
+
+#define mmNIF_RTR_CTRL_7_NL_SRAM_BANK_0 0x3F6500
+
+#define mmNIF_RTR_CTRL_7_NL_SRAM_BANK_1 0x3F6504
+
+#define mmNIF_RTR_CTRL_7_NL_SRAM_BANK_2 0x3F6508
+
+#define mmNIF_RTR_CTRL_7_NL_SRAM_BANK_3 0x3F650C
+
+#define mmNIF_RTR_CTRL_7_NL_SRAM_BANK_4 0x3F6510
+
+#define mmNIF_RTR_CTRL_7_NL_SRAM_OFFSET_0 0x3F6514
+
+#define mmNIF_RTR_CTRL_7_NL_SRAM_OFFSET_1 0x3F6520
+
+#define mmNIF_RTR_CTRL_7_NL_SRAM_OFFSET_2 0x3F6524
+
+#define mmNIF_RTR_CTRL_7_NL_SRAM_OFFSET_3 0x3F6528
+
+#define mmNIF_RTR_CTRL_7_NL_SRAM_OFFSET_4 0x3F652C
+
+#define mmNIF_RTR_CTRL_7_NL_SRAM_OFFSET_5 0x3F6530
+
+#define mmNIF_RTR_CTRL_7_NL_SRAM_OFFSET_6 0x3F6534
+
+#define mmNIF_RTR_CTRL_7_NL_SRAM_OFFSET_7 0x3F6538
+
+#define mmNIF_RTR_CTRL_7_NL_SRAM_OFFSET_8 0x3F653C
+
+#define mmNIF_RTR_CTRL_7_NL_SRAM_OFFSET_9 0x3F6540
+
+#define mmNIF_RTR_CTRL_7_NL_HBM_OFFSET_0 0x3F6550
+
+#define mmNIF_RTR_CTRL_7_NL_HBM_OFFSET_1 0x3F6554
+
+#define mmNIF_RTR_CTRL_7_NL_HBM_OFFSET_2 0x3F6558
+
+#define mmNIF_RTR_CTRL_7_NL_HBM_OFFSET_3 0x3F655C
+
+#define mmNIF_RTR_CTRL_7_NL_HBM_OFFSET_4 0x3F6560
+
+#define mmNIF_RTR_CTRL_7_NL_HBM_OFFSET_5 0x3F6564
+
+#define mmNIF_RTR_CTRL_7_NL_HBM_OFFSET_6 0x3F6568
+
+#define mmNIF_RTR_CTRL_7_NL_HBM_OFFSET_7 0x3F656C
+
+#define mmNIF_RTR_CTRL_7_NL_HBM_OFFSET_8 0x3F6570
+
+#define mmNIF_RTR_CTRL_7_NL_HBM_OFFSET_9 0x3F6574
+
+#define mmNIF_RTR_CTRL_7_NL_HBM_OFFSET_10 0x3F6578
+
+#define mmNIF_RTR_CTRL_7_NL_HBM_OFFSET_11 0x3F657C
+
+#define mmNIF_RTR_CTRL_7_NL_HBM_OFFSET_12 0x3F6580
+
+#define mmNIF_RTR_CTRL_7_NL_HBM_OFFSET_13 0x3F6584
+
+#define mmNIF_RTR_CTRL_7_NL_HBM_OFFSET_14 0x3F6588
+
+#define mmNIF_RTR_CTRL_7_NL_HBM_OFFSET_15 0x3F658C
+
+#define mmNIF_RTR_CTRL_7_NL_HBM_OFFSET_16 0x3F6590
+
+#define mmNIF_RTR_CTRL_7_NL_HBM_OFFSET_17 0x3F6594
+
+#define mmNIF_RTR_CTRL_7_NL_HBM_OFFSET_18 0x3F6598
+
+#define mmNIF_RTR_CTRL_7_RANGE_SEC_BASE_LOW_AW_0 0x3F65E4
+
+#define mmNIF_RTR_CTRL_7_RANGE_SEC_BASE_LOW_AW_1 0x3F65E8
+
+#define mmNIF_RTR_CTRL_7_RANGE_SEC_BASE_LOW_AW_2 0x3F65EC
+
+#define mmNIF_RTR_CTRL_7_RANGE_SEC_BASE_LOW_AW_3 0x3F65F0
+
+#define mmNIF_RTR_CTRL_7_RANGE_SEC_BASE_LOW_AW_4 0x3F65F4
+
+#define mmNIF_RTR_CTRL_7_RANGE_SEC_BASE_LOW_AW_5 0x3F65F8
+
+#define mmNIF_RTR_CTRL_7_RANGE_SEC_BASE_LOW_AW_6 0x3F65FC
+
+#define mmNIF_RTR_CTRL_7_RANGE_SEC_BASE_LOW_AW_7 0x3F6600
+
+#define mmNIF_RTR_CTRL_7_RANGE_SEC_BASE_LOW_AW_8 0x3F6604
+
+#define mmNIF_RTR_CTRL_7_RANGE_SEC_BASE_LOW_AW_9 0x3F6608
+
+#define mmNIF_RTR_CTRL_7_RANGE_SEC_BASE_LOW_AW_10 0x3F660C
+
+#define mmNIF_RTR_CTRL_7_RANGE_SEC_BASE_LOW_AW_11 0x3F6610
+
+#define mmNIF_RTR_CTRL_7_RANGE_SEC_BASE_LOW_AW_12 0x3F6614
+
+#define mmNIF_RTR_CTRL_7_RANGE_SEC_BASE_LOW_AW_13 0x3F6618
+
+#define mmNIF_RTR_CTRL_7_RANGE_SEC_BASE_LOW_AW_14 0x3F661C
+
+#define mmNIF_RTR_CTRL_7_RANGE_SEC_BASE_LOW_AW_15 0x3F6620
+
+#define mmNIF_RTR_CTRL_7_RANGE_SEC_BASE_HIGH_AW_0 0x3F6624
+
+#define mmNIF_RTR_CTRL_7_RANGE_SEC_BASE_HIGH_AW_1 0x3F6628
+
+#define mmNIF_RTR_CTRL_7_RANGE_SEC_BASE_HIGH_AW_2 0x3F662C
+
+#define mmNIF_RTR_CTRL_7_RANGE_SEC_BASE_HIGH_AW_3 0x3F6630
+
+#define mmNIF_RTR_CTRL_7_RANGE_SEC_BASE_HIGH_AW_4 0x3F6634
+
+#define mmNIF_RTR_CTRL_7_RANGE_SEC_BASE_HIGH_AW_5 0x3F6638
+
+#define mmNIF_RTR_CTRL_7_RANGE_SEC_BASE_HIGH_AW_6 0x3F663C
+
+#define mmNIF_RTR_CTRL_7_RANGE_SEC_BASE_HIGH_AW_7 0x3F6640
+
+#define mmNIF_RTR_CTRL_7_RANGE_SEC_BASE_HIGH_AW_8 0x3F6644
+
+#define mmNIF_RTR_CTRL_7_RANGE_SEC_BASE_HIGH_AW_9 0x3F6648
+
+#define mmNIF_RTR_CTRL_7_RANGE_SEC_BASE_HIGH_AW_10 0x3F664C
+
+#define mmNIF_RTR_CTRL_7_RANGE_SEC_BASE_HIGH_AW_11 0x3F6650
+
+#define mmNIF_RTR_CTRL_7_RANGE_SEC_BASE_HIGH_AW_12 0x3F6654
+
+#define mmNIF_RTR_CTRL_7_RANGE_SEC_BASE_HIGH_AW_13 0x3F6658
+
+#define mmNIF_RTR_CTRL_7_RANGE_SEC_BASE_HIGH_AW_14 0x3F665C
+
+#define mmNIF_RTR_CTRL_7_RANGE_SEC_BASE_HIGH_AW_15 0x3F6660
+
+#define mmNIF_RTR_CTRL_7_RANGE_SEC_MASK_LOW_AW_0 0x3F6664
+
+#define mmNIF_RTR_CTRL_7_RANGE_SEC_MASK_LOW_AW_1 0x3F6668
+
+#define mmNIF_RTR_CTRL_7_RANGE_SEC_MASK_LOW_AW_2 0x3F666C
+
+#define mmNIF_RTR_CTRL_7_RANGE_SEC_MASK_LOW_AW_3 0x3F6670
+
+#define mmNIF_RTR_CTRL_7_RANGE_SEC_MASK_LOW_AW_4 0x3F6674
+
+#define mmNIF_RTR_CTRL_7_RANGE_SEC_MASK_LOW_AW_5 0x3F6678
+
+#define mmNIF_RTR_CTRL_7_RANGE_SEC_MASK_LOW_AW_6 0x3F667C
+
+#define mmNIF_RTR_CTRL_7_RANGE_SEC_MASK_LOW_AW_7 0x3F6680
+
+#define mmNIF_RTR_CTRL_7_RANGE_SEC_MASK_LOW_AW_8 0x3F6684
+
+#define mmNIF_RTR_CTRL_7_RANGE_SEC_MASK_LOW_AW_9 0x3F6688
+
+#define mmNIF_RTR_CTRL_7_RANGE_SEC_MASK_LOW_AW_10 0x3F668C
+
+#define mmNIF_RTR_CTRL_7_RANGE_SEC_MASK_LOW_AW_11 0x3F6690
+
+#define mmNIF_RTR_CTRL_7_RANGE_SEC_MASK_LOW_AW_12 0x3F6694
+
+#define mmNIF_RTR_CTRL_7_RANGE_SEC_MASK_LOW_AW_13 0x3F6698
+
+#define mmNIF_RTR_CTRL_7_RANGE_SEC_MASK_LOW_AW_14 0x3F669C
+
+#define mmNIF_RTR_CTRL_7_RANGE_SEC_MASK_LOW_AW_15 0x3F66A0
+
+#define mmNIF_RTR_CTRL_7_RANGE_SEC_MASK_HIGH_AW_0 0x3F66A4
+
+#define mmNIF_RTR_CTRL_7_RANGE_SEC_MASK_HIGH_AW_1 0x3F66A8
+
+#define mmNIF_RTR_CTRL_7_RANGE_SEC_MASK_HIGH_AW_2 0x3F66AC
+
+#define mmNIF_RTR_CTRL_7_RANGE_SEC_MASK_HIGH_AW_3 0x3F66B0
+
+#define mmNIF_RTR_CTRL_7_RANGE_SEC_MASK_HIGH_AW_4 0x3F66B4
+
+#define mmNIF_RTR_CTRL_7_RANGE_SEC_MASK_HIGH_AW_5 0x3F66B8
+
+#define mmNIF_RTR_CTRL_7_RANGE_SEC_MASK_HIGH_AW_6 0x3F66BC
+
+#define mmNIF_RTR_CTRL_7_RANGE_SEC_MASK_HIGH_AW_7 0x3F66C0
+
+#define mmNIF_RTR_CTRL_7_RANGE_SEC_MASK_HIGH_AW_8 0x3F66C4
+
+#define mmNIF_RTR_CTRL_7_RANGE_SEC_MASK_HIGH_AW_9 0x3F66C8
+
+#define mmNIF_RTR_CTRL_7_RANGE_SEC_MASK_HIGH_AW_10 0x3F66CC
+
+#define mmNIF_RTR_CTRL_7_RANGE_SEC_MASK_HIGH_AW_11 0x3F66D0
+
+#define mmNIF_RTR_CTRL_7_RANGE_SEC_MASK_HIGH_AW_12 0x3F66D4
+
+#define mmNIF_RTR_CTRL_7_RANGE_SEC_MASK_HIGH_AW_13 0x3F66D8
+
+#define mmNIF_RTR_CTRL_7_RANGE_SEC_MASK_HIGH_AW_14 0x3F66DC
+
+#define mmNIF_RTR_CTRL_7_RANGE_SEC_MASK_HIGH_AW_15 0x3F66E0
+
+#define mmNIF_RTR_CTRL_7_RANGE_PRIV_BASE_LOW_AW_0 0x3F66E4
+
+#define mmNIF_RTR_CTRL_7_RANGE_PRIV_BASE_LOW_AW_1 0x3F66E8
+
+#define mmNIF_RTR_CTRL_7_RANGE_PRIV_BASE_LOW_AW_2 0x3F66EC
+
+#define mmNIF_RTR_CTRL_7_RANGE_PRIV_BASE_LOW_AW_3 0x3F66F0
+
+#define mmNIF_RTR_CTRL_7_RANGE_PRIV_BASE_LOW_AW_4 0x3F66F4
+
+#define mmNIF_RTR_CTRL_7_RANGE_PRIV_BASE_LOW_AW_5 0x3F66F8
+
+#define mmNIF_RTR_CTRL_7_RANGE_PRIV_BASE_LOW_AW_6 0x3F66FC
+
+#define mmNIF_RTR_CTRL_7_RANGE_PRIV_BASE_LOW_AW_7 0x3F6700
+
+#define mmNIF_RTR_CTRL_7_RANGE_PRIV_BASE_LOW_AW_8 0x3F6704
+
+#define mmNIF_RTR_CTRL_7_RANGE_PRIV_BASE_LOW_AW_9 0x3F6708
+
+#define mmNIF_RTR_CTRL_7_RANGE_PRIV_BASE_LOW_AW_10 0x3F670C
+
+#define mmNIF_RTR_CTRL_7_RANGE_PRIV_BASE_LOW_AW_11 0x3F6710
+
+#define mmNIF_RTR_CTRL_7_RANGE_PRIV_BASE_LOW_AW_12 0x3F6714
+
+#define mmNIF_RTR_CTRL_7_RANGE_PRIV_BASE_LOW_AW_13 0x3F6718
+
+#define mmNIF_RTR_CTRL_7_RANGE_PRIV_BASE_LOW_AW_14 0x3F671C
+
+#define mmNIF_RTR_CTRL_7_RANGE_PRIV_BASE_LOW_AW_15 0x3F6720
+
+#define mmNIF_RTR_CTRL_7_RANGE_PRIV_BASE_HIGH_AW_0 0x3F6724
+
+#define mmNIF_RTR_CTRL_7_RANGE_PRIV_BASE_HIGH_AW_1 0x3F6728
+
+#define mmNIF_RTR_CTRL_7_RANGE_PRIV_BASE_HIGH_AW_2 0x3F672C
+
+#define mmNIF_RTR_CTRL_7_RANGE_PRIV_BASE_HIGH_AW_3 0x3F6730
+
+#define mmNIF_RTR_CTRL_7_RANGE_PRIV_BASE_HIGH_AW_4 0x3F6734
+
+#define mmNIF_RTR_CTRL_7_RANGE_PRIV_BASE_HIGH_AW_5 0x3F6738
+
+#define mmNIF_RTR_CTRL_7_RANGE_PRIV_BASE_HIGH_AW_6 0x3F673C
+
+#define mmNIF_RTR_CTRL_7_RANGE_PRIV_BASE_HIGH_AW_7 0x3F6740
+
+#define mmNIF_RTR_CTRL_7_RANGE_PRIV_BASE_HIGH_AW_8 0x3F6744
+
+#define mmNIF_RTR_CTRL_7_RANGE_PRIV_BASE_HIGH_AW_9 0x3F6748
+
+#define mmNIF_RTR_CTRL_7_RANGE_PRIV_BASE_HIGH_AW_10 0x3F674C
+
+#define mmNIF_RTR_CTRL_7_RANGE_PRIV_BASE_HIGH_AW_11 0x3F6750
+
+#define mmNIF_RTR_CTRL_7_RANGE_PRIV_BASE_HIGH_AW_12 0x3F6754
+
+#define mmNIF_RTR_CTRL_7_RANGE_PRIV_BASE_HIGH_AW_13 0x3F6758
+
+#define mmNIF_RTR_CTRL_7_RANGE_PRIV_BASE_HIGH_AW_14 0x3F675C
+
+#define mmNIF_RTR_CTRL_7_RANGE_PRIV_BASE_HIGH_AW_15 0x3F6760
+
+#define mmNIF_RTR_CTRL_7_RANGE_PRIV_MASK_LOW_AW_0 0x3F6764
+
+#define mmNIF_RTR_CTRL_7_RANGE_PRIV_MASK_LOW_AW_1 0x3F6768
+
+#define mmNIF_RTR_CTRL_7_RANGE_PRIV_MASK_LOW_AW_2 0x3F676C
+
+#define mmNIF_RTR_CTRL_7_RANGE_PRIV_MASK_LOW_AW_3 0x3F6770
+
+#define mmNIF_RTR_CTRL_7_RANGE_PRIV_MASK_LOW_AW_4 0x3F6774
+
+#define mmNIF_RTR_CTRL_7_RANGE_PRIV_MASK_LOW_AW_5 0x3F6778
+
+#define mmNIF_RTR_CTRL_7_RANGE_PRIV_MASK_LOW_AW_6 0x3F677C
+
+#define mmNIF_RTR_CTRL_7_RANGE_PRIV_MASK_LOW_AW_7 0x3F6780
+
+#define mmNIF_RTR_CTRL_7_RANGE_PRIV_MASK_LOW_AW_8 0x3F6784
+
+#define mmNIF_RTR_CTRL_7_RANGE_PRIV_MASK_LOW_AW_9 0x3F6788
+
+#define mmNIF_RTR_CTRL_7_RANGE_PRIV_MASK_LOW_AW_10 0x3F678C
+
+#define mmNIF_RTR_CTRL_7_RANGE_PRIV_MASK_LOW_AW_11 0x3F6790
+
+#define mmNIF_RTR_CTRL_7_RANGE_PRIV_MASK_LOW_AW_12 0x3F6794
+
+#define mmNIF_RTR_CTRL_7_RANGE_PRIV_MASK_LOW_AW_13 0x3F6798
+
+#define mmNIF_RTR_CTRL_7_RANGE_PRIV_MASK_LOW_AW_14 0x3F679C
+
+#define mmNIF_RTR_CTRL_7_RANGE_PRIV_MASK_LOW_AW_15 0x3F67A0
+
+#define mmNIF_RTR_CTRL_7_RANGE_PRIV_MASK_HIGH_AW_0 0x3F67A4
+
+#define mmNIF_RTR_CTRL_7_RANGE_PRIV_MASK_HIGH_AW_1 0x3F67A8
+
+#define mmNIF_RTR_CTRL_7_RANGE_PRIV_MASK_HIGH_AW_2 0x3F67AC
+
+#define mmNIF_RTR_CTRL_7_RANGE_PRIV_MASK_HIGH_AW_3 0x3F67B0
+
+#define mmNIF_RTR_CTRL_7_RANGE_PRIV_MASK_HIGH_AW_4 0x3F67B4
+
+#define mmNIF_RTR_CTRL_7_RANGE_PRIV_MASK_HIGH_AW_5 0x3F67B8
+
+#define mmNIF_RTR_CTRL_7_RANGE_PRIV_MASK_HIGH_AW_6 0x3F67BC
+
+#define mmNIF_RTR_CTRL_7_RANGE_PRIV_MASK_HIGH_AW_7 0x3F67C0
+
+#define mmNIF_RTR_CTRL_7_RANGE_PRIV_MASK_HIGH_AW_8 0x3F67C4
+
+#define mmNIF_RTR_CTRL_7_RANGE_PRIV_MASK_HIGH_AW_9 0x3F67C8
+
+#define mmNIF_RTR_CTRL_7_RANGE_PRIV_MASK_HIGH_AW_10 0x3F67CC
+
+#define mmNIF_RTR_CTRL_7_RANGE_PRIV_MASK_HIGH_AW_11 0x3F67D0
+
+#define mmNIF_RTR_CTRL_7_RANGE_PRIV_MASK_HIGH_AW_12 0x3F67D4
+
+#define mmNIF_RTR_CTRL_7_RANGE_PRIV_MASK_HIGH_AW_13 0x3F67D8
+
+#define mmNIF_RTR_CTRL_7_RANGE_PRIV_MASK_HIGH_AW_14 0x3F67DC
+
+#define mmNIF_RTR_CTRL_7_RANGE_PRIV_MASK_HIGH_AW_15 0x3F67E0
+
+#define mmNIF_RTR_CTRL_7_RANGE_SEC_BASE_LOW_AR_0 0x3F6824
+
+#define mmNIF_RTR_CTRL_7_RANGE_SEC_BASE_LOW_AR_1 0x3F6828
+
+#define mmNIF_RTR_CTRL_7_RANGE_SEC_BASE_LOW_AR_2 0x3F682C
+
+#define mmNIF_RTR_CTRL_7_RANGE_SEC_BASE_LOW_AR_3 0x3F6830
+
+#define mmNIF_RTR_CTRL_7_RANGE_SEC_BASE_LOW_AR_4 0x3F6834
+
+#define mmNIF_RTR_CTRL_7_RANGE_SEC_BASE_LOW_AR_5 0x3F6838
+
+#define mmNIF_RTR_CTRL_7_RANGE_SEC_BASE_LOW_AR_6 0x3F683C
+
+#define mmNIF_RTR_CTRL_7_RANGE_SEC_BASE_LOW_AR_7 0x3F6840
+
+#define mmNIF_RTR_CTRL_7_RANGE_SEC_BASE_LOW_AR_8 0x3F6844
+
+#define mmNIF_RTR_CTRL_7_RANGE_SEC_BASE_LOW_AR_9 0x3F6848
+
+#define mmNIF_RTR_CTRL_7_RANGE_SEC_BASE_LOW_AR_10 0x3F684C
+
+#define mmNIF_RTR_CTRL_7_RANGE_SEC_BASE_LOW_AR_11 0x3F6850
+
+#define mmNIF_RTR_CTRL_7_RANGE_SEC_BASE_LOW_AR_12 0x3F6854
+
+#define mmNIF_RTR_CTRL_7_RANGE_SEC_BASE_LOW_AR_13 0x3F6858
+
+#define mmNIF_RTR_CTRL_7_RANGE_SEC_BASE_LOW_AR_14 0x3F685C
+
+#define mmNIF_RTR_CTRL_7_RANGE_SEC_BASE_LOW_AR_15 0x3F6860
+
+#define mmNIF_RTR_CTRL_7_RANGE_SEC_BASE_HIGH_AR_0 0x3F6864
+
+#define mmNIF_RTR_CTRL_7_RANGE_SEC_BASE_HIGH_AR_1 0x3F6868
+
+#define mmNIF_RTR_CTRL_7_RANGE_SEC_BASE_HIGH_AR_2 0x3F686C
+
+#define mmNIF_RTR_CTRL_7_RANGE_SEC_BASE_HIGH_AR_3 0x3F6870
+
+#define mmNIF_RTR_CTRL_7_RANGE_SEC_BASE_HIGH_AR_4 0x3F6874
+
+#define mmNIF_RTR_CTRL_7_RANGE_SEC_BASE_HIGH_AR_5 0x3F6878
+
+#define mmNIF_RTR_CTRL_7_RANGE_SEC_BASE_HIGH_AR_6 0x3F687C
+
+#define mmNIF_RTR_CTRL_7_RANGE_SEC_BASE_HIGH_AR_7 0x3F6880
+
+#define mmNIF_RTR_CTRL_7_RANGE_SEC_BASE_HIGH_AR_8 0x3F6884
+
+#define mmNIF_RTR_CTRL_7_RANGE_SEC_BASE_HIGH_AR_9 0x3F6888
+
+#define mmNIF_RTR_CTRL_7_RANGE_SEC_BASE_HIGH_AR_10 0x3F688C
+
+#define mmNIF_RTR_CTRL_7_RANGE_SEC_BASE_HIGH_AR_11 0x3F6890
+
+#define mmNIF_RTR_CTRL_7_RANGE_SEC_BASE_HIGH_AR_12 0x3F6894
+
+#define mmNIF_RTR_CTRL_7_RANGE_SEC_BASE_HIGH_AR_13 0x3F6898
+
+#define mmNIF_RTR_CTRL_7_RANGE_SEC_BASE_HIGH_AR_14 0x3F689C
+
+#define mmNIF_RTR_CTRL_7_RANGE_SEC_BASE_HIGH_AR_15 0x3F68A0
+
+#define mmNIF_RTR_CTRL_7_RANGE_SEC_MASK_LOW_AR_0 0x3F68A4
+
+#define mmNIF_RTR_CTRL_7_RANGE_SEC_MASK_LOW_AR_1 0x3F68A8
+
+#define mmNIF_RTR_CTRL_7_RANGE_SEC_MASK_LOW_AR_2 0x3F68AC
+
+#define mmNIF_RTR_CTRL_7_RANGE_SEC_MASK_LOW_AR_3 0x3F68B0
+
+#define mmNIF_RTR_CTRL_7_RANGE_SEC_MASK_LOW_AR_4 0x3F68B4
+
+#define mmNIF_RTR_CTRL_7_RANGE_SEC_MASK_LOW_AR_5 0x3F68B8
+
+#define mmNIF_RTR_CTRL_7_RANGE_SEC_MASK_LOW_AR_6 0x3F68BC
+
+#define mmNIF_RTR_CTRL_7_RANGE_SEC_MASK_LOW_AR_7 0x3F68C0
+
+#define mmNIF_RTR_CTRL_7_RANGE_SEC_MASK_LOW_AR_8 0x3F68C4
+
+#define mmNIF_RTR_CTRL_7_RANGE_SEC_MASK_LOW_AR_9 0x3F68C8
+
+#define mmNIF_RTR_CTRL_7_RANGE_SEC_MASK_LOW_AR_10 0x3F68CC
+
+#define mmNIF_RTR_CTRL_7_RANGE_SEC_MASK_LOW_AR_11 0x3F68D0
+
+#define mmNIF_RTR_CTRL_7_RANGE_SEC_MASK_LOW_AR_12 0x3F68D4
+
+#define mmNIF_RTR_CTRL_7_RANGE_SEC_MASK_LOW_AR_13 0x3F68D8
+
+#define mmNIF_RTR_CTRL_7_RANGE_SEC_MASK_LOW_AR_14 0x3F68DC
+
+#define mmNIF_RTR_CTRL_7_RANGE_SEC_MASK_LOW_AR_15 0x3F68E0
+
+#define mmNIF_RTR_CTRL_7_RANGE_SEC_MASK_HIGH_AR_0 0x3F68E4
+
+#define mmNIF_RTR_CTRL_7_RANGE_SEC_MASK_HIGH_AR_1 0x3F68E8
+
+#define mmNIF_RTR_CTRL_7_RANGE_SEC_MASK_HIGH_AR_2 0x3F68EC
+
+#define mmNIF_RTR_CTRL_7_RANGE_SEC_MASK_HIGH_AR_3 0x3F68F0
+
+#define mmNIF_RTR_CTRL_7_RANGE_SEC_MASK_HIGH_AR_4 0x3F68F4
+
+#define mmNIF_RTR_CTRL_7_RANGE_SEC_MASK_HIGH_AR_5 0x3F68F8
+
+#define mmNIF_RTR_CTRL_7_RANGE_SEC_MASK_HIGH_AR_6 0x3F68FC
+
+#define mmNIF_RTR_CTRL_7_RANGE_SEC_MASK_HIGH_AR_7 0x3F6900
+
+#define mmNIF_RTR_CTRL_7_RANGE_SEC_MASK_HIGH_AR_8 0x3F6904
+
+#define mmNIF_RTR_CTRL_7_RANGE_SEC_MASK_HIGH_AR_9 0x3F6908
+
+#define mmNIF_RTR_CTRL_7_RANGE_SEC_MASK_HIGH_AR_10 0x3F690C
+
+#define mmNIF_RTR_CTRL_7_RANGE_SEC_MASK_HIGH_AR_11 0x3F6910
+
+#define mmNIF_RTR_CTRL_7_RANGE_SEC_MASK_HIGH_AR_12 0x3F6914
+
+#define mmNIF_RTR_CTRL_7_RANGE_SEC_MASK_HIGH_AR_13 0x3F6918
+
+#define mmNIF_RTR_CTRL_7_RANGE_SEC_MASK_HIGH_AR_14 0x3F691C
+
+#define mmNIF_RTR_CTRL_7_RANGE_SEC_MASK_HIGH_AR_15 0x3F6920
+
+#define mmNIF_RTR_CTRL_7_RANGE_PRIV_BASE_LOW_AR_0 0x3F6924
+
+#define mmNIF_RTR_CTRL_7_RANGE_PRIV_BASE_LOW_AR_1 0x3F6928
+
+#define mmNIF_RTR_CTRL_7_RANGE_PRIV_BASE_LOW_AR_2 0x3F692C
+
+#define mmNIF_RTR_CTRL_7_RANGE_PRIV_BASE_LOW_AR_3 0x3F6930
+
+#define mmNIF_RTR_CTRL_7_RANGE_PRIV_BASE_LOW_AR_4 0x3F6934
+
+#define mmNIF_RTR_CTRL_7_RANGE_PRIV_BASE_LOW_AR_5 0x3F6938
+
+#define mmNIF_RTR_CTRL_7_RANGE_PRIV_BASE_LOW_AR_6 0x3F693C
+
+#define mmNIF_RTR_CTRL_7_RANGE_PRIV_BASE_LOW_AR_7 0x3F6940
+
+#define mmNIF_RTR_CTRL_7_RANGE_PRIV_BASE_LOW_AR_8 0x3F6944
+
+#define mmNIF_RTR_CTRL_7_RANGE_PRIV_BASE_LOW_AR_9 0x3F6948
+
+#define mmNIF_RTR_CTRL_7_RANGE_PRIV_BASE_LOW_AR_10 0x3F694C
+
+#define mmNIF_RTR_CTRL_7_RANGE_PRIV_BASE_LOW_AR_11 0x3F6950
+
+#define mmNIF_RTR_CTRL_7_RANGE_PRIV_BASE_LOW_AR_12 0x3F6954
+
+#define mmNIF_RTR_CTRL_7_RANGE_PRIV_BASE_LOW_AR_13 0x3F6958
+
+#define mmNIF_RTR_CTRL_7_RANGE_PRIV_BASE_LOW_AR_14 0x3F695C
+
+#define mmNIF_RTR_CTRL_7_RANGE_PRIV_BASE_LOW_AR_15 0x3F6960
+
+#define mmNIF_RTR_CTRL_7_RANGE_PRIV_BASE_HIGH_AR_0 0x3F6964
+
+#define mmNIF_RTR_CTRL_7_RANGE_PRIV_BASE_HIGH_AR_1 0x3F6968
+
+#define mmNIF_RTR_CTRL_7_RANGE_PRIV_BASE_HIGH_AR_2 0x3F696C
+
+#define mmNIF_RTR_CTRL_7_RANGE_PRIV_BASE_HIGH_AR_3 0x3F6970
+
+#define mmNIF_RTR_CTRL_7_RANGE_PRIV_BASE_HIGH_AR_4 0x3F6974
+
+#define mmNIF_RTR_CTRL_7_RANGE_PRIV_BASE_HIGH_AR_5 0x3F6978
+
+#define mmNIF_RTR_CTRL_7_RANGE_PRIV_BASE_HIGH_AR_6 0x3F697C
+
+#define mmNIF_RTR_CTRL_7_RANGE_PRIV_BASE_HIGH_AR_7 0x3F6980
+
+#define mmNIF_RTR_CTRL_7_RANGE_PRIV_BASE_HIGH_AR_8 0x3F6984
+
+#define mmNIF_RTR_CTRL_7_RANGE_PRIV_BASE_HIGH_AR_9 0x3F6988
+
+#define mmNIF_RTR_CTRL_7_RANGE_PRIV_BASE_HIGH_AR_10 0x3F698C
+
+#define mmNIF_RTR_CTRL_7_RANGE_PRIV_BASE_HIGH_AR_11 0x3F6990
+
+#define mmNIF_RTR_CTRL_7_RANGE_PRIV_BASE_HIGH_AR_12 0x3F6994
+
+#define mmNIF_RTR_CTRL_7_RANGE_PRIV_BASE_HIGH_AR_13 0x3F6998
+
+#define mmNIF_RTR_CTRL_7_RANGE_PRIV_BASE_HIGH_AR_14 0x3F699C
+
+#define mmNIF_RTR_CTRL_7_RANGE_PRIV_BASE_HIGH_AR_15 0x3F69A0
+
+#define mmNIF_RTR_CTRL_7_RANGE_PRIV_MASK_LOW_AR_0 0x3F69A4
+
+#define mmNIF_RTR_CTRL_7_RANGE_PRIV_MASK_LOW_AR_1 0x3F69A8
+
+#define mmNIF_RTR_CTRL_7_RANGE_PRIV_MASK_LOW_AR_2 0x3F69AC
+
+#define mmNIF_RTR_CTRL_7_RANGE_PRIV_MASK_LOW_AR_3 0x3F69B0
+
+#define mmNIF_RTR_CTRL_7_RANGE_PRIV_MASK_LOW_AR_4 0x3F69B4
+
+#define mmNIF_RTR_CTRL_7_RANGE_PRIV_MASK_LOW_AR_5 0x3F69B8
+
+#define mmNIF_RTR_CTRL_7_RANGE_PRIV_MASK_LOW_AR_6 0x3F69BC
+
+#define mmNIF_RTR_CTRL_7_RANGE_PRIV_MASK_LOW_AR_7 0x3F69C0
+
+#define mmNIF_RTR_CTRL_7_RANGE_PRIV_MASK_LOW_AR_8 0x3F69C4
+
+#define mmNIF_RTR_CTRL_7_RANGE_PRIV_MASK_LOW_AR_9 0x3F69C8
+
+#define mmNIF_RTR_CTRL_7_RANGE_PRIV_MASK_LOW_AR_10 0x3F69CC
+
+#define mmNIF_RTR_CTRL_7_RANGE_PRIV_MASK_LOW_AR_11 0x3F69D0
+
+#define mmNIF_RTR_CTRL_7_RANGE_PRIV_MASK_LOW_AR_12 0x3F69D4
+
+#define mmNIF_RTR_CTRL_7_RANGE_PRIV_MASK_LOW_AR_13 0x3F69D8
+
+#define mmNIF_RTR_CTRL_7_RANGE_PRIV_MASK_LOW_AR_14 0x3F69DC
+
+#define mmNIF_RTR_CTRL_7_RANGE_PRIV_MASK_LOW_AR_15 0x3F69E0
+
+#define mmNIF_RTR_CTRL_7_RANGE_PRIV_MASK_HIGH_AR_0 0x3F69E4
+
+#define mmNIF_RTR_CTRL_7_RANGE_PRIV_MASK_HIGH_AR_1 0x3F69E8
+
+#define mmNIF_RTR_CTRL_7_RANGE_PRIV_MASK_HIGH_AR_2 0x3F69EC
+
+#define mmNIF_RTR_CTRL_7_RANGE_PRIV_MASK_HIGH_AR_3 0x3F69F0
+
+#define mmNIF_RTR_CTRL_7_RANGE_PRIV_MASK_HIGH_AR_4 0x3F69F4
+
+#define mmNIF_RTR_CTRL_7_RANGE_PRIV_MASK_HIGH_AR_5 0x3F69F8
+
+#define mmNIF_RTR_CTRL_7_RANGE_PRIV_MASK_HIGH_AR_6 0x3F69FC
+
+#define mmNIF_RTR_CTRL_7_RANGE_PRIV_MASK_HIGH_AR_7 0x3F6A00
+
+#define mmNIF_RTR_CTRL_7_RANGE_PRIV_MASK_HIGH_AR_8 0x3F6A04
+
+#define mmNIF_RTR_CTRL_7_RANGE_PRIV_MASK_HIGH_AR_9 0x3F6A08
+
+#define mmNIF_RTR_CTRL_7_RANGE_PRIV_MASK_HIGH_AR_10 0x3F6A0C
+
+#define mmNIF_RTR_CTRL_7_RANGE_PRIV_MASK_HIGH_AR_11 0x3F6A10
+
+#define mmNIF_RTR_CTRL_7_RANGE_PRIV_MASK_HIGH_AR_12 0x3F6A14
+
+#define mmNIF_RTR_CTRL_7_RANGE_PRIV_MASK_HIGH_AR_13 0x3F6A18
+
+#define mmNIF_RTR_CTRL_7_RANGE_PRIV_MASK_HIGH_AR_14 0x3F6A1C
+
+#define mmNIF_RTR_CTRL_7_RANGE_PRIV_MASK_HIGH_AR_15 0x3F6A20
+
+#define mmNIF_RTR_CTRL_7_RANGE_SEC_HIT_AW 0x3F6A64
+
+#define mmNIF_RTR_CTRL_7_RANGE_SEC_HIT_AR 0x3F6A68
+
+#define mmNIF_RTR_CTRL_7_RANGE_PRIV_HIT_AW 0x3F6A6C
+
+#define mmNIF_RTR_CTRL_7_RANGE_PRIV_HIT_AR 0x3F6A70
+
+#define mmNIF_RTR_CTRL_7_RGL_CFG 0x3F6B64
+
+#define mmNIF_RTR_CTRL_7_RGL_SHIFT 0x3F6B68
+
+#define mmNIF_RTR_CTRL_7_RGL_EXPECTED_LAT_0 0x3F6B6C
+
+#define mmNIF_RTR_CTRL_7_RGL_EXPECTED_LAT_1 0x3F6B70
+
+#define mmNIF_RTR_CTRL_7_RGL_EXPECTED_LAT_2 0x3F6B74
+
+#define mmNIF_RTR_CTRL_7_RGL_EXPECTED_LAT_3 0x3F6B78
+
+#define mmNIF_RTR_CTRL_7_RGL_EXPECTED_LAT_4 0x3F6B7C
+
+#define mmNIF_RTR_CTRL_7_RGL_EXPECTED_LAT_5 0x3F6B80
+
+#define mmNIF_RTR_CTRL_7_RGL_EXPECTED_LAT_6 0x3F6B84
+
+#define mmNIF_RTR_CTRL_7_RGL_EXPECTED_LAT_7 0x3F6B88
+
+#define mmNIF_RTR_CTRL_7_RGL_TOKEN_0 0x3F6BAC
+
+#define mmNIF_RTR_CTRL_7_RGL_TOKEN_1 0x3F6BB0
+
+#define mmNIF_RTR_CTRL_7_RGL_TOKEN_2 0x3F6BB4
+
+#define mmNIF_RTR_CTRL_7_RGL_TOKEN_3 0x3F6BB8
+
+#define mmNIF_RTR_CTRL_7_RGL_TOKEN_4 0x3F6BBC
+
+#define mmNIF_RTR_CTRL_7_RGL_TOKEN_5 0x3F6BC0
+
+#define mmNIF_RTR_CTRL_7_RGL_TOKEN_6 0x3F6BC4
+
+#define mmNIF_RTR_CTRL_7_RGL_TOKEN_7 0x3F6BC8
+
+#define mmNIF_RTR_CTRL_7_RGL_BANK_ID_0 0x3F6BEC
+
+#define mmNIF_RTR_CTRL_7_RGL_BANK_ID_1 0x3F6BF0
+
+#define mmNIF_RTR_CTRL_7_RGL_BANK_ID_2 0x3F6BF4
+
+#define mmNIF_RTR_CTRL_7_RGL_BANK_ID_3 0x3F6BF8
+
+#define mmNIF_RTR_CTRL_7_RGL_BANK_ID_4 0x3F6BFC
+
+#define mmNIF_RTR_CTRL_7_RGL_BANK_ID_5 0x3F6C00
+
+#define mmNIF_RTR_CTRL_7_RGL_BANK_ID_6 0x3F6C04
+
+#define mmNIF_RTR_CTRL_7_RGL_BANK_ID_7 0x3F6C08
+
+#define mmNIF_RTR_CTRL_7_RGL_WDT 0x3F6C2C
+
+#define mmNIF_RTR_CTRL_7_E2E_AR_HBM0_CH0_CTR_WRAP 0x3F6C30
+
+#define mmNIF_RTR_CTRL_7_E2E_AR_HBM0_CH1_CTR_WRAP 0x3F6C34
+
+#define mmNIF_RTR_CTRL_7_E2E_AR_HBM1_CH0_CTR_WRAP 0x3F6C38
+
+#define mmNIF_RTR_CTRL_7_E2E_AR_HBM1_CH1_CTR_WRAP 0x3F6C3C
+
+#define mmNIF_RTR_CTRL_7_E2E_AR_HBM2_CH0_CTR_WRAP 0x3F6C40
+
+#define mmNIF_RTR_CTRL_7_E2E_AR_HBM2_CH1_CTR_WRAP 0x3F6C44
+
+#define mmNIF_RTR_CTRL_7_E2E_AR_HBM3_CH0_CTR_WRAP 0x3F6C48
+
+#define mmNIF_RTR_CTRL_7_E2E_AR_HBM3_CH1_CTR_WRAP 0x3F6C4C
+
+#define mmNIF_RTR_CTRL_7_E2E_AR_HBM0_CH0_CTR_CNT 0x3F6C50
+
+#define mmNIF_RTR_CTRL_7_E2E_AR_HBM0_CH1_CTR_CNT 0x3F6C54
+
+#define mmNIF_RTR_CTRL_7_E2E_AR_HBM1_CH0_CTR_CNT 0x3F6C58
+
+#define mmNIF_RTR_CTRL_7_E2E_AR_HBM1_CH1_CTR_CNT 0x3F6C5C
+
+#define mmNIF_RTR_CTRL_7_E2E_AR_HBM2_CH0_CTR_CNT 0x3F6C60
+
+#define mmNIF_RTR_CTRL_7_E2E_AR_HBM2_CH1_CTR_CNT 0x3F6C64
+
+#define mmNIF_RTR_CTRL_7_E2E_AR_HBM3_CH0_CTR_CNT 0x3F6C68
+
+#define mmNIF_RTR_CTRL_7_E2E_AR_HBM3_CH1_CTR_CNT 0x3F6C6C
+
+#define mmNIF_RTR_CTRL_7_E2E_AW_HBM0_CH0_CTR_WRAP 0x3F6C70
+
+#define mmNIF_RTR_CTRL_7_E2E_AW_HBM0_CH1_CTR_WRAP 0x3F6C74
+
+#define mmNIF_RTR_CTRL_7_E2E_AW_HBM1_CH0_CTR_WRAP 0x3F6C78
+
+#define mmNIF_RTR_CTRL_7_E2E_AW_HBM1_CH1_CTR_WRAP 0x3F6C7C
+
+#define mmNIF_RTR_CTRL_7_E2E_AW_HBM2_CH0_CTR_WRAP 0x3F6C80
+
+#define mmNIF_RTR_CTRL_7_E2E_AW_HBM2_CH1_CTR_WRAP 0x3F6C84
+
+#define mmNIF_RTR_CTRL_7_E2E_AW_HBM3_CH0_CTR_WRAP 0x3F6C88
+
+#define mmNIF_RTR_CTRL_7_E2E_AW_HBM3_CH1_CTR_WRAP 0x3F6C8C
+
+#define mmNIF_RTR_CTRL_7_E2E_AW_HBM0_CH0_CTR_CNT 0x3F6C90
+
+#define mmNIF_RTR_CTRL_7_E2E_AW_HBM0_CH1_CTR_CNT 0x3F6C94
+
+#define mmNIF_RTR_CTRL_7_E2E_AW_HBM1_CH0_CTR_CNT 0x3F6C98
+
+#define mmNIF_RTR_CTRL_7_E2E_AW_HBM1_CH1_CTR_CNT 0x3F6C9C
+
+#define mmNIF_RTR_CTRL_7_E2E_AW_HBM2_CH0_CTR_CNT 0x3F6CA0
+
+#define mmNIF_RTR_CTRL_7_E2E_AW_HBM2_CH1_CTR_CNT 0x3F6CA4
+
+#define mmNIF_RTR_CTRL_7_E2E_AW_HBM3_CH0_CTR_CNT 0x3F6CA8
+
+#define mmNIF_RTR_CTRL_7_E2E_AW_HBM3_CH1_CTR_CNT 0x3F6CAC
+
+#define mmNIF_RTR_CTRL_7_NL_HBM_PC_SEL_0 0x3F6CB0
+
+#define mmNIF_RTR_CTRL_7_NL_HBM_PC_SEL_1 0x3F6CB4
+
+#define mmNIF_RTR_CTRL_7_NL_HBM_PC_SEL_2 0x3F6CB8
+
+#define mmNIF_RTR_CTRL_7_NL_HBM_PC_SEL_3 0x3F6CBC
+
+#endif /* ASIC_REG_NIF_RTR_CTRL_7_REGS_H_ */
diff --git a/drivers/accel/habanalabs/include/gaudi/asic_reg/psoc_cpu_pll_regs.h b/drivers/accel/habanalabs/include/gaudi/asic_reg/psoc_cpu_pll_regs.h
new file mode 100644
index 0000000000..2585c70f59
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi/asic_reg/psoc_cpu_pll_regs.h
@@ -0,0 +1,114 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2016-2018 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ ** DO NOT EDIT BELOW **
+ ************************************/
+
+#ifndef ASIC_REG_PSOC_CPU_PLL_REGS_H_
+#define ASIC_REG_PSOC_CPU_PLL_REGS_H_
+
+/*
+ *****************************************
+ * PSOC_CPU_PLL (Prototype: PLL)
+ *****************************************
+ */
+
+#define mmPSOC_CPU_PLL_NR 0xC70100
+
+#define mmPSOC_CPU_PLL_NF 0xC70104
+
+#define mmPSOC_CPU_PLL_OD 0xC70108
+
+#define mmPSOC_CPU_PLL_NB 0xC7010C
+
+#define mmPSOC_CPU_PLL_CFG 0xC70110
+
+#define mmPSOC_CPU_PLL_LOSE_MASK 0xC70120
+
+#define mmPSOC_CPU_PLL_LOCK_INTR 0xC70128
+
+#define mmPSOC_CPU_PLL_LOCK_BYPASS 0xC7012C
+
+#define mmPSOC_CPU_PLL_DATA_CHNG 0xC70130
+
+#define mmPSOC_CPU_PLL_RST 0xC70134
+
+#define mmPSOC_CPU_PLL_SLIP_WD_CNTR 0xC70150
+
+#define mmPSOC_CPU_PLL_DIV_FACTOR_0 0xC70200
+
+#define mmPSOC_CPU_PLL_DIV_FACTOR_1 0xC70204
+
+#define mmPSOC_CPU_PLL_DIV_FACTOR_2 0xC70208
+
+#define mmPSOC_CPU_PLL_DIV_FACTOR_3 0xC7020C
+
+#define mmPSOC_CPU_PLL_DIV_FACTOR_CMD_0 0xC70220
+
+#define mmPSOC_CPU_PLL_DIV_FACTOR_CMD_1 0xC70224
+
+#define mmPSOC_CPU_PLL_DIV_FACTOR_CMD_2 0xC70228
+
+#define mmPSOC_CPU_PLL_DIV_FACTOR_CMD_3 0xC7022C
+
+#define mmPSOC_CPU_PLL_DIV_SEL_0 0xC70280
+
+#define mmPSOC_CPU_PLL_DIV_SEL_1 0xC70284
+
+#define mmPSOC_CPU_PLL_DIV_SEL_2 0xC70288
+
+#define mmPSOC_CPU_PLL_DIV_SEL_3 0xC7028C
+
+#define mmPSOC_CPU_PLL_DIV_EN_0 0xC702A0
+
+#define mmPSOC_CPU_PLL_DIV_EN_1 0xC702A4
+
+#define mmPSOC_CPU_PLL_DIV_EN_2 0xC702A8
+
+#define mmPSOC_CPU_PLL_DIV_EN_3 0xC702AC
+
+#define mmPSOC_CPU_PLL_DIV_FACTOR_BUSY_0 0xC702C0
+
+#define mmPSOC_CPU_PLL_DIV_FACTOR_BUSY_1 0xC702C4
+
+#define mmPSOC_CPU_PLL_DIV_FACTOR_BUSY_2 0xC702C8
+
+#define mmPSOC_CPU_PLL_DIV_FACTOR_BUSY_3 0xC702CC
+
+#define mmPSOC_CPU_PLL_CLK_GATER 0xC70300
+
+#define mmPSOC_CPU_PLL_CLK_RLX_0 0xC70310
+
+#define mmPSOC_CPU_PLL_CLK_RLX_1 0xC70314
+
+#define mmPSOC_CPU_PLL_CLK_RLX_2 0xC70318
+
+#define mmPSOC_CPU_PLL_CLK_RLX_3 0xC7031C
+
+#define mmPSOC_CPU_PLL_REF_CNTR_PERIOD 0xC70400
+
+#define mmPSOC_CPU_PLL_REF_LOW_THRESHOLD 0xC70410
+
+#define mmPSOC_CPU_PLL_REF_HIGH_THRESHOLD 0xC70420
+
+#define mmPSOC_CPU_PLL_PLL_NOT_STABLE 0xC70430
+
+#define mmPSOC_CPU_PLL_FREQ_CALC_EN 0xC70440
+
+#define mmPSOC_CPU_PLL_RLX_BITMAP_CFG 0xC70500
+
+#define mmPSOC_CPU_PLL_RLX_BITMAP_0 0xC70510
+
+#define mmPSOC_CPU_PLL_RLX_BITMAP_1 0xC70514
+
+#define mmPSOC_CPU_PLL_RLX_BITMAP_2 0xC70518
+
+#define mmPSOC_CPU_PLL_RLX_BITMAP_3 0xC7051C
+
+#endif /* ASIC_REG_PSOC_CPU_PLL_REGS_H_ */
diff --git a/drivers/accel/habanalabs/include/gaudi/asic_reg/psoc_etr_regs.h b/drivers/accel/habanalabs/include/gaudi/asic_reg/psoc_etr_regs.h
new file mode 100644
index 0000000000..b7c33e025d
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi/asic_reg/psoc_etr_regs.h
@@ -0,0 +1,114 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2016-2018 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ ** DO NOT EDIT BELOW **
+ ************************************/
+
+#ifndef ASIC_REG_PSOC_ETR_REGS_H_
+#define ASIC_REG_PSOC_ETR_REGS_H_
+
+/*
+ *****************************************
+ * PSOC_ETR (Prototype: ETR)
+ *****************************************
+ */
+
+#define mmPSOC_ETR_RSZ 0x2C43004
+
+#define mmPSOC_ETR_STS 0x2C4300C
+
+#define mmPSOC_ETR_RRD 0x2C43010
+
+#define mmPSOC_ETR_RRP 0x2C43014
+
+#define mmPSOC_ETR_RWP 0x2C43018
+
+#define mmPSOC_ETR_TRG 0x2C4301C
+
+#define mmPSOC_ETR_CTL 0x2C43020
+
+#define mmPSOC_ETR_RWD 0x2C43024
+
+#define mmPSOC_ETR_MODE 0x2C43028
+
+#define mmPSOC_ETR_LBUFLEVEL 0x2C4302C
+
+#define mmPSOC_ETR_CBUFLEVEL 0x2C43030
+
+#define mmPSOC_ETR_BUFWM 0x2C43034
+
+#define mmPSOC_ETR_RRPHI 0x2C43038
+
+#define mmPSOC_ETR_RWPHI 0x2C4303C
+
+#define mmPSOC_ETR_AXICTL 0x2C43110
+
+#define mmPSOC_ETR_DBALO 0x2C43118
+
+#define mmPSOC_ETR_DBAHI 0x2C4311C
+
+#define mmPSOC_ETR_FFSR 0x2C43300
+
+#define mmPSOC_ETR_FFCR 0x2C43304
+
+#define mmPSOC_ETR_PSCR 0x2C43308
+
+#define mmPSOC_ETR_ITMISCOP0 0x2C43EE0
+
+#define mmPSOC_ETR_ITTRFLIN 0x2C43EE8
+
+#define mmPSOC_ETR_ITATBDATA0 0x2C43EEC
+
+#define mmPSOC_ETR_ITATBCTR2 0x2C43EF0
+
+#define mmPSOC_ETR_ITATBCTR1 0x2C43EF4
+
+#define mmPSOC_ETR_ITATBCTR0 0x2C43EF8
+
+#define mmPSOC_ETR_ITCTRL 0x2C43F00
+
+#define mmPSOC_ETR_CLAIMSET 0x2C43FA0
+
+#define mmPSOC_ETR_CLAIMCLR 0x2C43FA4
+
+#define mmPSOC_ETR_LAR 0x2C43FB0
+
+#define mmPSOC_ETR_LSR 0x2C43FB4
+
+#define mmPSOC_ETR_AUTHSTATUS 0x2C43FB8
+
+#define mmPSOC_ETR_DEVID 0x2C43FC8
+
+#define mmPSOC_ETR_DEVTYPE 0x2C43FCC
+
+#define mmPSOC_ETR_PERIPHID4 0x2C43FD0
+
+#define mmPSOC_ETR_PERIPHID5 0x2C43FD4
+
+#define mmPSOC_ETR_PERIPHID6 0x2C43FD8
+
+#define mmPSOC_ETR_PERIPHID7 0x2C43FDC
+
+#define mmPSOC_ETR_PERIPHID0 0x2C43FE0
+
+#define mmPSOC_ETR_PERIPHID1 0x2C43FE4
+
+#define mmPSOC_ETR_PERIPHID2 0x2C43FE8
+
+#define mmPSOC_ETR_PERIPHID3 0x2C43FEC
+
+#define mmPSOC_ETR_COMPID0 0x2C43FF0
+
+#define mmPSOC_ETR_COMPID1 0x2C43FF4
+
+#define mmPSOC_ETR_COMPID2 0x2C43FF8
+
+#define mmPSOC_ETR_COMPID3 0x2C43FFC
+
+#endif /* ASIC_REG_PSOC_ETR_REGS_H_ */
diff --git a/drivers/accel/habanalabs/include/gaudi/asic_reg/psoc_global_conf_masks.h b/drivers/accel/habanalabs/include/gaudi/asic_reg/psoc_global_conf_masks.h
new file mode 100644
index 0000000000..6703e678ee
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi/asic_reg/psoc_global_conf_masks.h
@@ -0,0 +1,502 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2016-2018 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ ** DO NOT EDIT BELOW **
+ ************************************/
+
+#ifndef ASIC_REG_PSOC_GLOBAL_CONF_MASKS_H_
+#define ASIC_REG_PSOC_GLOBAL_CONF_MASKS_H_
+
+/*
+ *****************************************
+ * PSOC_GLOBAL_CONF (Prototype: GLOBAL_CONF)
+ *****************************************
+ */
+
+/* PSOC_GLOBAL_CONF_NON_RST_FLOPS */
+#define PSOC_GLOBAL_CONF_NON_RST_FLOPS_VAL_SHIFT 0
+#define PSOC_GLOBAL_CONF_NON_RST_FLOPS_VAL_MASK 0xFFFFFFFF
+
+/* PSOC_GLOBAL_CONF_PCI_FW_FSM */
+#define PSOC_GLOBAL_CONF_PCI_FW_FSM_EN_SHIFT 0
+#define PSOC_GLOBAL_CONF_PCI_FW_FSM_EN_MASK 0x1
+
+/* PSOC_GLOBAL_CONF_BOOT_SEQ_RE_START */
+#define PSOC_GLOBAL_CONF_BOOT_SEQ_RE_START_IND_SHIFT 0
+#define PSOC_GLOBAL_CONF_BOOT_SEQ_RE_START_IND_MASK 0x1
+
+/* PSOC_GLOBAL_CONF_BTM_FSM */
+#define PSOC_GLOBAL_CONF_BTM_FSM_STATE_SHIFT 0
+#define PSOC_GLOBAL_CONF_BTM_FSM_STATE_MASK 0xF
+
+/* PSOC_GLOBAL_CONF_SW_BTM_FSM */
+#define PSOC_GLOBAL_CONF_SW_BTM_FSM_CTRL_SHIFT 0
+#define PSOC_GLOBAL_CONF_SW_BTM_FSM_CTRL_MASK 0xF
+
+/* PSOC_GLOBAL_CONF_SW_BOOT_SEQ_FSM */
+#define PSOC_GLOBAL_CONF_SW_BOOT_SEQ_FSM_CTRL_SHIFT 0
+#define PSOC_GLOBAL_CONF_SW_BOOT_SEQ_FSM_CTRL_MASK 0xF
+
+/* PSOC_GLOBAL_CONF_BOOT_SEQ_TIMEOUT */
+#define PSOC_GLOBAL_CONF_BOOT_SEQ_TIMEOUT_VAL_SHIFT 0
+#define PSOC_GLOBAL_CONF_BOOT_SEQ_TIMEOUT_VAL_MASK 0xFFFFFFFF
+
+/* PSOC_GLOBAL_CONF_SPI_MEM_EN */
+#define PSOC_GLOBAL_CONF_SPI_MEM_EN_IND_SHIFT 0
+#define PSOC_GLOBAL_CONF_SPI_MEM_EN_IND_MASK 0x1
+
+/* PSOC_GLOBAL_CONF_PRSTN */
+#define PSOC_GLOBAL_CONF_PRSTN_VAL_SHIFT 0
+#define PSOC_GLOBAL_CONF_PRSTN_VAL_MASK 0x1
+
+/* PSOC_GLOBAL_CONF_PCIE_EN */
+#define PSOC_GLOBAL_CONF_PCIE_EN_MASK_SHIFT 0
+#define PSOC_GLOBAL_CONF_PCIE_EN_MASK_MASK 0x1
+
+/* PSOC_GLOBAL_CONF_PCIE_PRSTN_INTR */
+#define PSOC_GLOBAL_CONF_PCIE_PRSTN_INTR_IND_SHIFT 0
+#define PSOC_GLOBAL_CONF_PCIE_PRSTN_INTR_IND_MASK 0x1
+
+/* PSOC_GLOBAL_CONF_SPI_IMG_STS */
+#define PSOC_GLOBAL_CONF_SPI_IMG_STS_PRI_SHIFT 0
+#define PSOC_GLOBAL_CONF_SPI_IMG_STS_PRI_MASK 0x1
+#define PSOC_GLOBAL_CONF_SPI_IMG_STS_SEC_SHIFT 1
+#define PSOC_GLOBAL_CONF_SPI_IMG_STS_SEC_MASK 0x2
+#define PSOC_GLOBAL_CONF_SPI_IMG_STS_PRSTN_SHIFT 2
+#define PSOC_GLOBAL_CONF_SPI_IMG_STS_PRSTN_MASK 0x4
+#define PSOC_GLOBAL_CONF_SPI_IMG_STS_PCI_SHIFT 3
+#define PSOC_GLOBAL_CONF_SPI_IMG_STS_PCI_MASK 0x8
+
+/* PSOC_GLOBAL_CONF_BOOT_SEQ_FSM */
+#define PSOC_GLOBAL_CONF_BOOT_SEQ_FSM_IDLE_SHIFT 0
+#define PSOC_GLOBAL_CONF_BOOT_SEQ_FSM_IDLE_MASK 0x1
+#define PSOC_GLOBAL_CONF_BOOT_SEQ_FSM_BOOT_INIT_SHIFT 1
+#define PSOC_GLOBAL_CONF_BOOT_SEQ_FSM_BOOT_INIT_MASK 0x2
+#define PSOC_GLOBAL_CONF_BOOT_SEQ_FSM_SPI_PRI_SHIFT 2
+#define PSOC_GLOBAL_CONF_BOOT_SEQ_FSM_SPI_PRI_MASK 0x4
+#define PSOC_GLOBAL_CONF_BOOT_SEQ_FSM_SPI_SEC_SHIFT 3
+#define PSOC_GLOBAL_CONF_BOOT_SEQ_FSM_SPI_SEC_MASK 0x8
+#define PSOC_GLOBAL_CONF_BOOT_SEQ_FSM_SPI_PRSTN_SHIFT 4
+#define PSOC_GLOBAL_CONF_BOOT_SEQ_FSM_SPI_PRSTN_MASK 0x10
+#define PSOC_GLOBAL_CONF_BOOT_SEQ_FSM_SPI_PCIE_SHIFT 5
+#define PSOC_GLOBAL_CONF_BOOT_SEQ_FSM_SPI_PCIE_MASK 0x20
+#define PSOC_GLOBAL_CONF_BOOT_SEQ_FSM_ROM_SHIFT 6
+#define PSOC_GLOBAL_CONF_BOOT_SEQ_FSM_ROM_MASK 0x40
+#define PSOC_GLOBAL_CONF_BOOT_SEQ_FSM_PCLK_READY_SHIFT 7
+#define PSOC_GLOBAL_CONF_BOOT_SEQ_FSM_PCLK_READY_MASK 0x80
+#define PSOC_GLOBAL_CONF_BOOT_SEQ_FSM_LTSSM_EN_SHIFT 8
+#define PSOC_GLOBAL_CONF_BOOT_SEQ_FSM_LTSSM_EN_MASK 0x100
+
+/* PSOC_GLOBAL_CONF_BOOT_SEQ_EXT_LD */
+#define PSOC_GLOBAL_CONF_BOOT_SEQ_EXT_LD_DONE_SHIFT 0
+#define PSOC_GLOBAL_CONF_BOOT_SEQ_EXT_LD_DONE_MASK 0x1
+
+/* PSOC_GLOBAL_CONF_PHY_STABLE */
+#define PSOC_GLOBAL_CONF_PHY_STABLE_PRSTN_SHIFT 0
+#define PSOC_GLOBAL_CONF_PHY_STABLE_PRSTN_MASK 0x1
+
+/* PSOC_GLOBAL_CONF_PRSTN_OVR */
+#define PSOC_GLOBAL_CONF_PRSTN_OVR_EN_SHIFT 0
+#define PSOC_GLOBAL_CONF_PRSTN_OVR_EN_MASK 0x1
+#define PSOC_GLOBAL_CONF_PRSTN_OVR_VAL_SHIFT 4
+#define PSOC_GLOBAL_CONF_PRSTN_OVR_VAL_MASK 0x10
+
+/* PSOC_GLOBAL_CONF_ETR_FLUSH */
+#define PSOC_GLOBAL_CONF_ETR_FLUSH_MASK_SHIFT 0
+#define PSOC_GLOBAL_CONF_ETR_FLUSH_MASK_MASK 0x1
+
+/* PSOC_GLOBAL_CONF_COLD_RST_FLOPS */
+#define PSOC_GLOBAL_CONF_COLD_RST_FLOPS_VAL_SHIFT 0
+#define PSOC_GLOBAL_CONF_COLD_RST_FLOPS_VAL_MASK 0xFFFFFFFF
+
+/* PSOC_GLOBAL_CONF_DIS_RAZWI_ERR */
+#define PSOC_GLOBAL_CONF_DIS_RAZWI_ERR_IND_SHIFT 0
+#define PSOC_GLOBAL_CONF_DIS_RAZWI_ERR_IND_MASK 0x1
+
+/* PSOC_GLOBAL_CONF_PCIE_PHY_RST_N */
+#define PSOC_GLOBAL_CONF_PCIE_PHY_RST_N_IND_SHIFT 0
+#define PSOC_GLOBAL_CONF_PCIE_PHY_RST_N_IND_MASK 0x1
+
+/* PSOC_GLOBAL_CONF_RAZWI */
+#define PSOC_GLOBAL_CONF_RAZWI_INTR_SHIFT 0
+#define PSOC_GLOBAL_CONF_RAZWI_INTR_MASK 0x1
+#define PSOC_GLOBAL_CONF_RAZWI_MASK_SHIFT 4
+#define PSOC_GLOBAL_CONF_RAZWI_MASK_MASK 0x10
+
+/* PSOC_GLOBAL_CONF_PROT */
+#define PSOC_GLOBAL_CONF_PROT_AR_SHIFT 0
+#define PSOC_GLOBAL_CONF_PROT_AR_MASK 0x7
+#define PSOC_GLOBAL_CONF_PROT_AW_SHIFT 4
+#define PSOC_GLOBAL_CONF_PROT_AW_MASK 0x70
+
+/* PSOC_GLOBAL_CONF_ADC */
+#define PSOC_GLOBAL_CONF_ADC_INTR_SHIFT 0
+#define PSOC_GLOBAL_CONF_ADC_INTR_MASK 0x1
+#define PSOC_GLOBAL_CONF_ADC_MASK_SHIFT 4
+#define PSOC_GLOBAL_CONF_ADC_MASK_MASK 0x10
+
+/* PSOC_GLOBAL_CONF_BOOT_SEQ_TO */
+#define PSOC_GLOBAL_CONF_BOOT_SEQ_TO_MASK_SHIFT 0
+#define PSOC_GLOBAL_CONF_BOOT_SEQ_TO_MASK_MASK 0x1
+
+/* PSOC_GLOBAL_CONF_SCRATCHPAD */
+#define PSOC_GLOBAL_CONF_SCRATCHPAD_REG_SHIFT 0
+#define PSOC_GLOBAL_CONF_SCRATCHPAD_REG_MASK 0xFFFFFFFF
+
+/* PSOC_GLOBAL_CONF_SEMAPHORE */
+#define PSOC_GLOBAL_CONF_SEMAPHORE_REG_SHIFT 0
+#define PSOC_GLOBAL_CONF_SEMAPHORE_REG_MASK 0xFFFFFFFF
+
+/* PSOC_GLOBAL_CONF_CPU_BOOT_STATUS */
+#define PSOC_GLOBAL_CONF_CPU_BOOT_STATUS_CNTR_SHIFT 0
+#define PSOC_GLOBAL_CONF_CPU_BOOT_STATUS_CNTR_MASK 0xFFFFFFFF
+
+/* PSOC_GLOBAL_CONF_KMD_MSG_TO_CPU */
+#define PSOC_GLOBAL_CONF_KMD_MSG_TO_CPU_VAL_SHIFT 0
+#define PSOC_GLOBAL_CONF_KMD_MSG_TO_CPU_VAL_MASK 0xFFFFFFFF
+
+/* PSOC_GLOBAL_CONF_SPL_SOURCE */
+#define PSOC_GLOBAL_CONF_SPL_SOURCE_VAL_SHIFT 0
+#define PSOC_GLOBAL_CONF_SPL_SOURCE_VAL_MASK 0x7
+
+/* PSOC_GLOBAL_CONF_I2C_MSTR1_DBG */
+#define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_S_GEN_SHIFT 0
+#define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_S_GEN_MASK 0x1
+#define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_P_GEN_SHIFT 1
+#define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_P_GEN_MASK 0x2
+#define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_DATA_SHIFT 2
+#define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_DATA_MASK 0x4
+#define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_ADDR_SHIFT 3
+#define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_ADDR_MASK 0x8
+#define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_RD_SHIFT 4
+#define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_RD_MASK 0x10
+#define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_WR_SHIFT 5
+#define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_WR_MASK 0x20
+#define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_HS_SHIFT 6
+#define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_HS_MASK 0x40
+#define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_MASTER_ACT_SHIFT 7
+#define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_MASTER_ACT_MASK 0x80
+#define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_SLAVE_ACT_SHIFT 8
+#define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_SLAVE_ACT_MASK 0x100
+#define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_ADDR_10BIT_SHIFT 9
+#define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_ADDR_10BIT_MASK 0x200
+#define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_MST_CSTATE_SHIFT 10
+#define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_MST_CSTATE_MASK 0x7C00
+#define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_SLV_CSTATE_SHIFT 15
+#define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_SLV_CSTATE_MASK 0x78000
+#define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_IC_EN_SHIFT 19
+#define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_IC_EN_MASK 0x80000
+
+/* PSOC_GLOBAL_CONF_I2C_SLV */
+#define PSOC_GLOBAL_CONF_I2C_SLV_CPU_CTRL_SHIFT 0
+#define PSOC_GLOBAL_CONF_I2C_SLV_CPU_CTRL_MASK 0x1
+
+/* PSOC_GLOBAL_CONF_I2C_SLV_INTR_MASK */
+#define PSOC_GLOBAL_CONF_I2C_SLV_INTR_MASK_FLD_INT_SHIFT 0
+#define PSOC_GLOBAL_CONF_I2C_SLV_INTR_MASK_FLD_INT_MASK 0x1
+
+/* PSOC_GLOBAL_CONF_TRACE_ADDR */
+#define PSOC_GLOBAL_CONF_TRACE_ADDR_MSB_SHIFT 0
+#define PSOC_GLOBAL_CONF_TRACE_ADDR_MSB_MASK 0x3FF
+
+/* PSOC_GLOBAL_CONF_ARUSER */
+#define PSOC_GLOBAL_CONF_ARUSER_VAL_SHIFT 0
+#define PSOC_GLOBAL_CONF_ARUSER_VAL_MASK 0xFFFFFFFF
+
+/* PSOC_GLOBAL_CONF_AWUSER */
+#define PSOC_GLOBAL_CONF_AWUSER_VAL_SHIFT 0
+#define PSOC_GLOBAL_CONF_AWUSER_VAL_MASK 0xFFFFFFFF
+
+/* PSOC_GLOBAL_CONF_TRACE_AWUSER */
+#define PSOC_GLOBAL_CONF_TRACE_AWUSER_VAL_SHIFT 0
+#define PSOC_GLOBAL_CONF_TRACE_AWUSER_VAL_MASK 0xFFFFFFFF
+
+/* PSOC_GLOBAL_CONF_TRACE_ARUSER */
+#define PSOC_GLOBAL_CONF_TRACE_ARUSER_VAL_SHIFT 0
+#define PSOC_GLOBAL_CONF_TRACE_ARUSER_VAL_MASK 0xFFFFFFFF
+
+/* PSOC_GLOBAL_CONF_BTL_STS */
+#define PSOC_GLOBAL_CONF_BTL_STS_DONE_SHIFT 0
+#define PSOC_GLOBAL_CONF_BTL_STS_DONE_MASK 0x1
+#define PSOC_GLOBAL_CONF_BTL_STS_FAIL_SHIFT 4
+#define PSOC_GLOBAL_CONF_BTL_STS_FAIL_MASK 0x10
+#define PSOC_GLOBAL_CONF_BTL_STS_FAIL_CODE_SHIFT 8
+#define PSOC_GLOBAL_CONF_BTL_STS_FAIL_CODE_MASK 0xF00
+
+/* PSOC_GLOBAL_CONF_TIMEOUT_INTR */
+#define PSOC_GLOBAL_CONF_TIMEOUT_INTR_GPIO_0_SHIFT 0
+#define PSOC_GLOBAL_CONF_TIMEOUT_INTR_GPIO_0_MASK 0x1
+#define PSOC_GLOBAL_CONF_TIMEOUT_INTR_GPIO_1_SHIFT 1
+#define PSOC_GLOBAL_CONF_TIMEOUT_INTR_GPIO_1_MASK 0x2
+#define PSOC_GLOBAL_CONF_TIMEOUT_INTR_GPIO_2_SHIFT 2
+#define PSOC_GLOBAL_CONF_TIMEOUT_INTR_GPIO_2_MASK 0x4
+#define PSOC_GLOBAL_CONF_TIMEOUT_INTR_GPIO_3_SHIFT 3
+#define PSOC_GLOBAL_CONF_TIMEOUT_INTR_GPIO_3_MASK 0x8
+#define PSOC_GLOBAL_CONF_TIMEOUT_INTR_GPIO_4_SHIFT 4
+#define PSOC_GLOBAL_CONF_TIMEOUT_INTR_GPIO_4_MASK 0x10
+#define PSOC_GLOBAL_CONF_TIMEOUT_INTR_TIMER_SHIFT 5
+#define PSOC_GLOBAL_CONF_TIMEOUT_INTR_TIMER_MASK 0x20
+#define PSOC_GLOBAL_CONF_TIMEOUT_INTR_UART_0_SHIFT 6
+#define PSOC_GLOBAL_CONF_TIMEOUT_INTR_UART_0_MASK 0x40
+#define PSOC_GLOBAL_CONF_TIMEOUT_INTR_UART_1_SHIFT 7
+#define PSOC_GLOBAL_CONF_TIMEOUT_INTR_UART_1_MASK 0x80
+#define PSOC_GLOBAL_CONF_TIMEOUT_INTR_GPIO_5_SHIFT 8
+#define PSOC_GLOBAL_CONF_TIMEOUT_INTR_GPIO_5_MASK 0x100
+#define PSOC_GLOBAL_CONF_TIMEOUT_INTR_GPIO_6_SHIFT 9
+#define PSOC_GLOBAL_CONF_TIMEOUT_INTR_GPIO_6_MASK 0x200
+
+/* PSOC_GLOBAL_CONF_COMB_TIMEOUT_INTR */
+#define PSOC_GLOBAL_CONF_COMB_TIMEOUT_INTR_IND_SHIFT 0
+#define PSOC_GLOBAL_CONF_COMB_TIMEOUT_INTR_IND_MASK 0x1
+
+/* PSOC_GLOBAL_CONF_PERIPH_INTR */
+#define PSOC_GLOBAL_CONF_PERIPH_INTR_UART_0_TX_SHIFT 0
+#define PSOC_GLOBAL_CONF_PERIPH_INTR_UART_0_TX_MASK 0x1
+#define PSOC_GLOBAL_CONF_PERIPH_INTR_UART_0_RX_SHIFT 1
+#define PSOC_GLOBAL_CONF_PERIPH_INTR_UART_0_RX_MASK 0x2
+#define PSOC_GLOBAL_CONF_PERIPH_INTR_UART_0_TXOVR_SHIFT 2
+#define PSOC_GLOBAL_CONF_PERIPH_INTR_UART_0_TXOVR_MASK 0x4
+#define PSOC_GLOBAL_CONF_PERIPH_INTR_UART_0_RXOVR_SHIFT 3
+#define PSOC_GLOBAL_CONF_PERIPH_INTR_UART_0_RXOVR_MASK 0x8
+#define PSOC_GLOBAL_CONF_PERIPH_INTR_UART_1_TX_SHIFT 4
+#define PSOC_GLOBAL_CONF_PERIPH_INTR_UART_1_TX_MASK 0x10
+#define PSOC_GLOBAL_CONF_PERIPH_INTR_UART_1_RX_SHIFT 5
+#define PSOC_GLOBAL_CONF_PERIPH_INTR_UART_1_RX_MASK 0x20
+#define PSOC_GLOBAL_CONF_PERIPH_INTR_UART_1_TXOVR_SHIFT 6
+#define PSOC_GLOBAL_CONF_PERIPH_INTR_UART_1_TXOVR_MASK 0x40
+#define PSOC_GLOBAL_CONF_PERIPH_INTR_UART_1_RXOVR_SHIFT 7
+#define PSOC_GLOBAL_CONF_PERIPH_INTR_UART_1_RXOVR_MASK 0x80
+#define PSOC_GLOBAL_CONF_PERIPH_INTR_EMMC_SHIFT 12
+#define PSOC_GLOBAL_CONF_PERIPH_INTR_EMMC_MASK 0x1000
+#define PSOC_GLOBAL_CONF_PERIPH_INTR_EMMC_WAKEUP_SHIFT 13
+#define PSOC_GLOBAL_CONF_PERIPH_INTR_EMMC_WAKEUP_MASK 0x2000
+#define PSOC_GLOBAL_CONF_PERIPH_INTR_MII_SHIFT 16
+#define PSOC_GLOBAL_CONF_PERIPH_INTR_MII_MASK 0x10000
+
+/* PSOC_GLOBAL_CONF_COMB_PERIPH_INTR */
+#define PSOC_GLOBAL_CONF_COMB_PERIPH_INTR_IND_SHIFT 0
+#define PSOC_GLOBAL_CONF_COMB_PERIPH_INTR_IND_MASK 0x1
+
+/* PSOC_GLOBAL_CONF_AXI_ERR_INTR */
+#define PSOC_GLOBAL_CONF_AXI_ERR_INTR_IND_SHIFT 0
+#define PSOC_GLOBAL_CONF_AXI_ERR_INTR_IND_MASK 0x1
+
+/* PSOC_GLOBAL_CONF_TARGETID */
+#define PSOC_GLOBAL_CONF_TARGETID_TDESIGNER_SHIFT 1
+#define PSOC_GLOBAL_CONF_TARGETID_TDESIGNER_MASK 0xFFE
+#define PSOC_GLOBAL_CONF_TARGETID_TPARTNO_SHIFT 16
+#define PSOC_GLOBAL_CONF_TARGETID_TPARTNO_MASK 0xFFF0000
+#define PSOC_GLOBAL_CONF_TARGETID_TREVISION_SHIFT 28
+#define PSOC_GLOBAL_CONF_TARGETID_TREVISION_MASK 0xF0000000
+
+/* PSOC_GLOBAL_CONF_EMMC_INT_VOL_STABLE */
+#define PSOC_GLOBAL_CONF_EMMC_INT_VOL_STABLE_IND_SHIFT 0
+#define PSOC_GLOBAL_CONF_EMMC_INT_VOL_STABLE_IND_MASK 0x1
+
+/* PSOC_GLOBAL_CONF_BOOT_STRAP_PINS */
+#define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_I2C_SLV_ADDR_SHIFT 0
+#define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_I2C_SLV_ADDR_MASK 0x1
+#define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_PCIE_EN_SHIFT 1
+#define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_PCIE_EN_MASK 0x2
+#define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_REPAIR_CFG_SHIFT 2
+#define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_REPAIR_CFG_MASK 0xC
+#define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_CPOL_SHIFT 4
+#define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_CPOL_MASK 0x10
+#define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_CPHA_SHIFT 5
+#define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_CPHA_MASK 0x20
+#define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_BTL_EN_SHIFT 6
+#define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_BTL_EN_MASK 0x40
+#define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_BTL_ROM_EN_SHIFT 7
+#define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_BTL_ROM_EN_MASK 0x80
+#define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_DUMP_SEL_SHIFT 8
+#define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_DUMP_SEL_MASK 0x1FFF00
+#define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_GRAD_RST_SHIFT 22
+#define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_GRAD_RST_MASK 0x400000
+#define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_DUMP_DIS_SHIFT 23
+#define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_DUMP_DIS_MASK 0x800000
+#define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_I2C_SHIFT 24
+#define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_I2C_MASK 0x1F000000
+
+/* PSOC_GLOBAL_CONF_MEM_REPAIR_DIV */
+#define PSOC_GLOBAL_CONF_MEM_REPAIR_DIV_EN_SHIFT 0
+#define PSOC_GLOBAL_CONF_MEM_REPAIR_DIV_EN_MASK 0x1
+#define PSOC_GLOBAL_CONF_MEM_REPAIR_DIV_VAL_SHIFT 8
+#define PSOC_GLOBAL_CONF_MEM_REPAIR_DIV_VAL_MASK 0xFF00
+
+/* PSOC_GLOBAL_CONF_MEM_REPAIR_CTRL */
+#define PSOC_GLOBAL_CONF_MEM_REPAIR_CTRL_SET_SHIFT 0
+#define PSOC_GLOBAL_CONF_MEM_REPAIR_CTRL_SET_MASK 0x1
+#define PSOC_GLOBAL_CONF_MEM_REPAIR_CTRL_CLR_SHIFT 1
+#define PSOC_GLOBAL_CONF_MEM_REPAIR_CTRL_CLR_MASK 0x2
+
+/* PSOC_GLOBAL_CONF_MEM_REPAIR_STS */
+#define PSOC_GLOBAL_CONF_MEM_REPAIR_STS_IND_SHIFT 0
+#define PSOC_GLOBAL_CONF_MEM_REPAIR_STS_IND_MASK 0x1
+#define PSOC_GLOBAL_CONF_MEM_REPAIR_STS_FAIL_SHIFT 4
+#define PSOC_GLOBAL_CONF_MEM_REPAIR_STS_FAIL_MASK 0x10
+
+/* PSOC_GLOBAL_CONF_OUTSTANT_TRANS */
+#define PSOC_GLOBAL_CONF_OUTSTANT_TRANS_RD_SHIFT 0
+#define PSOC_GLOBAL_CONF_OUTSTANT_TRANS_RD_MASK 0x1
+#define PSOC_GLOBAL_CONF_OUTSTANT_TRANS_WR_SHIFT 1
+#define PSOC_GLOBAL_CONF_OUTSTANT_TRANS_WR_MASK 0x2
+
+/* PSOC_GLOBAL_CONF_MASK_REQ */
+#define PSOC_GLOBAL_CONF_MASK_REQ_IND_SHIFT 0
+#define PSOC_GLOBAL_CONF_MASK_REQ_IND_MASK 0x1
+
+/* PSOC_GLOBAL_CONF_WD_RST_CFG_L */
+#define PSOC_GLOBAL_CONF_WD_RST_CFG_L_VAL_SHIFT 0
+#define PSOC_GLOBAL_CONF_WD_RST_CFG_L_VAL_MASK 0xFFFFFFFF
+
+/* PSOC_GLOBAL_CONF_WD_RST_CFG_H */
+#define PSOC_GLOBAL_CONF_WD_RST_CFG_H_VAL_SHIFT 0
+#define PSOC_GLOBAL_CONF_WD_RST_CFG_H_VAL_MASK 0x3FFFFF
+
+/* PSOC_GLOBAL_CONF_MNL_RST_CFG_L */
+#define PSOC_GLOBAL_CONF_MNL_RST_CFG_L_VAL_SHIFT 0
+#define PSOC_GLOBAL_CONF_MNL_RST_CFG_L_VAL_MASK 0xFFFFFFFF
+
+/* PSOC_GLOBAL_CONF_MNL_RST_CFG_H */
+#define PSOC_GLOBAL_CONF_MNL_RST_CFG_H_VAL_SHIFT 0
+#define PSOC_GLOBAL_CONF_MNL_RST_CFG_H_VAL_MASK 0x3FFFFF
+
+/* PSOC_GLOBAL_CONF_PRSTN_RST_CFG_L */
+#define PSOC_GLOBAL_CONF_PRSTN_RST_CFG_L_VAL_SHIFT 0
+#define PSOC_GLOBAL_CONF_PRSTN_RST_CFG_L_VAL_MASK 0xFFFFFFFF
+
+/* PSOC_GLOBAL_CONF_PRSTN_RST_CFG_H */
+#define PSOC_GLOBAL_CONF_PRSTN_RST_CFG_H_VAL_SHIFT 0
+#define PSOC_GLOBAL_CONF_PRSTN_RST_CFG_H_VAL_MASK 0xFFFFFFFF
+
+/* PSOC_GLOBAL_CONF_SW_ALL_RST_CFG_L */
+#define PSOC_GLOBAL_CONF_SW_ALL_RST_CFG_L_VAL_SHIFT 0
+#define PSOC_GLOBAL_CONF_SW_ALL_RST_CFG_L_VAL_MASK 0xFFFFFFFF
+
+/* PSOC_GLOBAL_CONF_SW_ALL_RST_CFG_H */
+#define PSOC_GLOBAL_CONF_SW_ALL_RST_CFG_H_VAL_SHIFT 0
+#define PSOC_GLOBAL_CONF_SW_ALL_RST_CFG_H_VAL_MASK 0x3FFFFF
+
+/* PSOC_GLOBAL_CONF_SW_ALL_RST */
+#define PSOC_GLOBAL_CONF_SW_ALL_RST_IND_SHIFT 0
+#define PSOC_GLOBAL_CONF_SW_ALL_RST_IND_MASK 0x1
+
+/* PSOC_GLOBAL_CONF_SOFT_RST */
+#define PSOC_GLOBAL_CONF_SOFT_RST_IND_SHIFT 0
+#define PSOC_GLOBAL_CONF_SOFT_RST_IND_MASK 0x1
+
+/* PSOC_GLOBAL_CONF_SOFT_RST_CFG_L */
+#define PSOC_GLOBAL_CONF_SOFT_RST_CFG_L_VAL_SHIFT 0
+#define PSOC_GLOBAL_CONF_SOFT_RST_CFG_L_VAL_MASK 0xFFFFFFFF
+
+/* PSOC_GLOBAL_CONF_SOFT_RST_CFG_H */
+#define PSOC_GLOBAL_CONF_SOFT_RST_CFG_H_VAL_SHIFT 0
+#define PSOC_GLOBAL_CONF_SOFT_RST_CFG_H_VAL_MASK 0x3FFFFF
+
+/* PSOC_GLOBAL_CONF_UNIT_RST_N */
+#define PSOC_GLOBAL_CONF_UNIT_RST_N_IND_SHIFT 0
+#define PSOC_GLOBAL_CONF_UNIT_RST_N_IND_MASK 0x1
+
+/* PSOC_GLOBAL_CONF_UNIT_RST_N_L */
+#define PSOC_GLOBAL_CONF_UNIT_RST_N_L_VAL_SHIFT 0
+#define PSOC_GLOBAL_CONF_UNIT_RST_N_L_VAL_MASK 0xFFFFFFFF
+
+/* PSOC_GLOBAL_CONF_UNIT_RST_N_H */
+#define PSOC_GLOBAL_CONF_UNIT_RST_N_H_VAL_SHIFT 0
+#define PSOC_GLOBAL_CONF_UNIT_RST_N_H_VAL_MASK 0x3FFFFF
+
+/* PSOC_GLOBAL_CONF_BTL_IMG */
+#define PSOC_GLOBAL_CONF_BTL_IMG_SEL_SHIFT 0
+#define PSOC_GLOBAL_CONF_BTL_IMG_SEL_MASK 0x1
+
+/* PSOC_GLOBAL_CONF_PRSTN_MASK */
+#define PSOC_GLOBAL_CONF_PRSTN_MASK_IND_SHIFT 0
+#define PSOC_GLOBAL_CONF_PRSTN_MASK_IND_MASK 0x1
+
+/* PSOC_GLOBAL_CONF_WD_MASK */
+#define PSOC_GLOBAL_CONF_WD_MASK_IND_SHIFT 0
+#define PSOC_GLOBAL_CONF_WD_MASK_IND_MASK 0x1
+
+/* PSOC_GLOBAL_CONF_RST_SRC */
+#define PSOC_GLOBAL_CONF_RST_SRC_VAL_SHIFT 0
+#define PSOC_GLOBAL_CONF_RST_SRC_VAL_MASK 0xF
+
+/* PSOC_GLOBAL_CONF_BOOT_STATE */
+#define PSOC_GLOBAL_CONF_BOOT_STATE_VAL_SHIFT 0
+#define PSOC_GLOBAL_CONF_BOOT_STATE_VAL_MASK 0x1
+
+/* PSOC_GLOBAL_CONF_PAD_1V8_CFG */
+#define PSOC_GLOBAL_CONF_PAD_1V8_CFG_VAL_SHIFT 0
+#define PSOC_GLOBAL_CONF_PAD_1V8_CFG_VAL_MASK 0x7F
+
+/* PSOC_GLOBAL_CONF_PAD_3V3_CFG */
+#define PSOC_GLOBAL_CONF_PAD_3V3_CFG_VAL_SHIFT 0
+#define PSOC_GLOBAL_CONF_PAD_3V3_CFG_VAL_MASK 0x7F
+
+/* PSOC_GLOBAL_CONF_PAD_1V8_INPUT */
+#define PSOC_GLOBAL_CONF_PAD_1V8_INPUT_CFG_SHIFT 0
+#define PSOC_GLOBAL_CONF_PAD_1V8_INPUT_CFG_MASK 0x7
+
+/* PSOC_GLOBAL_CONF_BNK3V3_MS */
+#define PSOC_GLOBAL_CONF_BNK3V3_MS_VAL_SHIFT 0
+#define PSOC_GLOBAL_CONF_BNK3V3_MS_VAL_MASK 0x3
+
+/* PSOC_GLOBAL_CONF_ADC_CLK_FREQ */
+#define PSOC_GLOBAL_CONF_ADC_CLK_FREQ_VAL_SHIFT 0
+#define PSOC_GLOBAL_CONF_ADC_CLK_FREQ_VAL_MASK 0xFF
+
+/* PSOC_GLOBAL_CONF_ADC_DELAY_FROM_START */
+#define PSOC_GLOBAL_CONF_ADC_DELAY_FROM_START_VAL_SHIFT 0
+#define PSOC_GLOBAL_CONF_ADC_DELAY_FROM_START_VAL_MASK 0xFF
+
+/* PSOC_GLOBAL_CONF_ADC_DATA_SAMPLES */
+#define PSOC_GLOBAL_CONF_ADC_DATA_SAMPLES_VAL_SHIFT 0
+#define PSOC_GLOBAL_CONF_ADC_DATA_SAMPLES_VAL_MASK 0x1F
+
+/* PSOC_GLOBAL_CONF_ADC_TPH_CS */
+#define PSOC_GLOBAL_CONF_ADC_TPH_CS_VAL_SHIFT 0
+#define PSOC_GLOBAL_CONF_ADC_TPH_CS_VAL_MASK 0xFF
+
+/* PSOC_GLOBAL_CONF_ADC_LSB_NMSB */
+#define PSOC_GLOBAL_CONF_ADC_LSB_NMSB_VAL_SHIFT 0
+#define PSOC_GLOBAL_CONF_ADC_LSB_NMSB_VAL_MASK 0x1
+
+/* PSOC_GLOBAL_CONF_ADC_ONE_NCONTIUES */
+#define PSOC_GLOBAL_CONF_ADC_ONE_NCONTIUES_VAL_SHIFT 0
+#define PSOC_GLOBAL_CONF_ADC_ONE_NCONTIUES_VAL_MASK 0x1
+
+/* PSOC_GLOBAL_CONF_ADC_BLOCK_ENABLE */
+#define PSOC_GLOBAL_CONF_ADC_BLOCK_ENABLE_VAL_SHIFT 0
+#define PSOC_GLOBAL_CONF_ADC_BLOCK_ENABLE_VAL_MASK 0x1
+
+/* PSOC_GLOBAL_CONF_ADC_CFG_DATA */
+#define PSOC_GLOBAL_CONF_ADC_CFG_DATA_VAL_SHIFT 0
+#define PSOC_GLOBAL_CONF_ADC_CFG_DATA_VAL_MASK 0xFFFFFFFF
+
+/* PSOC_GLOBAL_CONF_ADC_TDV_CSDO */
+#define PSOC_GLOBAL_CONF_ADC_TDV_CSDO_VAL_SHIFT 0
+#define PSOC_GLOBAL_CONF_ADC_TDV_CSDO_VAL_MASK 0xFF
+
+/* PSOC_GLOBAL_CONF_ADC_TSU_CSCK */
+#define PSOC_GLOBAL_CONF_ADC_TSU_CSCK_VAL_SHIFT 0
+#define PSOC_GLOBAL_CONF_ADC_TSU_CSCK_VAL_MASK 0xFF
+
+/* PSOC_GLOBAL_CONF_PAD_DEFAULT */
+#define PSOC_GLOBAL_CONF_PAD_DEFAULT_VAL_SHIFT 0
+#define PSOC_GLOBAL_CONF_PAD_DEFAULT_VAL_MASK 0xF
+
+/* PSOC_GLOBAL_CONF_PAD_SEL */
+#define PSOC_GLOBAL_CONF_PAD_SEL_VAL_SHIFT 0
+#define PSOC_GLOBAL_CONF_PAD_SEL_VAL_MASK 0x3
+
+/* PSOC_GLOBAL_CONF_RST_CTRL */
+#define PSOC_GLOBAL_CONF_RST_CTRL_SEL_SHIFT 0
+#define PSOC_GLOBAL_CONF_RST_CTRL_SEL_MASK 0xFF
+
+#endif /* ASIC_REG_PSOC_GLOBAL_CONF_MASKS_H_ */
diff --git a/drivers/accel/habanalabs/include/gaudi/asic_reg/psoc_global_conf_regs.h b/drivers/accel/habanalabs/include/gaudi/asic_reg/psoc_global_conf_regs.h
new file mode 100644
index 0000000000..1b5cfcc1d8
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi/asic_reg/psoc_global_conf_regs.h
@@ -0,0 +1,1062 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2016-2018 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ ** DO NOT EDIT BELOW **
+ ************************************/
+
+#ifndef ASIC_REG_PSOC_GLOBAL_CONF_REGS_H_
+#define ASIC_REG_PSOC_GLOBAL_CONF_REGS_H_
+
+/*
+ *****************************************
+ * PSOC_GLOBAL_CONF (Prototype: GLOBAL_CONF)
+ *****************************************
+ */
+
+#define mmPSOC_GLOBAL_CONF_NON_RST_FLOPS_0 0xC4B000
+
+#define mmPSOC_GLOBAL_CONF_NON_RST_FLOPS_1 0xC4B004
+
+#define mmPSOC_GLOBAL_CONF_NON_RST_FLOPS_2 0xC4B008
+
+#define mmPSOC_GLOBAL_CONF_NON_RST_FLOPS_3 0xC4B00C
+
+#define mmPSOC_GLOBAL_CONF_PCI_FW_FSM 0xC4B020
+
+#define mmPSOC_GLOBAL_CONF_BOOT_SEQ_RE_START 0xC4B024
+
+#define mmPSOC_GLOBAL_CONF_BTM_FSM 0xC4B028
+
+#define mmPSOC_GLOBAL_CONF_SW_BTM_FSM 0xC4B030
+
+#define mmPSOC_GLOBAL_CONF_SW_BOOT_SEQ_FSM 0xC4B034
+
+#define mmPSOC_GLOBAL_CONF_BOOT_SEQ_TIMEOUT 0xC4B038
+
+#define mmPSOC_GLOBAL_CONF_SPI_MEM_EN 0xC4B040
+
+#define mmPSOC_GLOBAL_CONF_PRSTN 0xC4B044
+
+#define mmPSOC_GLOBAL_CONF_PCIE_EN 0xC4B048
+
+#define mmPSOC_GLOBAL_CONF_PCIE_PRSTN_INTR 0xC4B04C
+
+#define mmPSOC_GLOBAL_CONF_SPI_IMG_STS 0xC4B050
+
+#define mmPSOC_GLOBAL_CONF_BOOT_SEQ_FSM 0xC4B054
+
+#define mmPSOC_GLOBAL_CONF_BOOT_SEQ_EXT_LD 0xC4B058
+
+#define mmPSOC_GLOBAL_CONF_PHY_STABLE 0xC4B060
+
+#define mmPSOC_GLOBAL_CONF_PRSTN_OVR 0xC4B064
+
+#define mmPSOC_GLOBAL_CONF_ETR_FLUSH 0xC4B068
+
+#define mmPSOC_GLOBAL_CONF_COLD_RST_FLOPS_0 0xC4B070
+
+#define mmPSOC_GLOBAL_CONF_COLD_RST_FLOPS_1 0xC4B074
+
+#define mmPSOC_GLOBAL_CONF_COLD_RST_FLOPS_2 0xC4B078
+
+#define mmPSOC_GLOBAL_CONF_COLD_RST_FLOPS_3 0xC4B07C
+
+#define mmPSOC_GLOBAL_CONF_DIS_RAZWI_ERR 0xC4B080
+
+#define mmPSOC_GLOBAL_CONF_PCIE_PHY_RST_N 0xC4B084
+
+#define mmPSOC_GLOBAL_CONF_RAZWI 0xC4B088
+
+#define mmPSOC_GLOBAL_CONF_PROT 0xC4B090
+
+#define mmPSOC_GLOBAL_CONF_ADC 0xC4B094
+
+#define mmPSOC_GLOBAL_CONF_BOOT_SEQ_TO 0xC4B098
+
+#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_0 0xC4B100
+
+#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_1 0xC4B104
+
+#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_2 0xC4B108
+
+#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_3 0xC4B10C
+
+#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_4 0xC4B110
+
+#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_5 0xC4B114
+
+#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_6 0xC4B118
+
+#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_7 0xC4B11C
+
+#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_8 0xC4B120
+
+#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_9 0xC4B124
+
+#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_10 0xC4B128
+
+#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_11 0xC4B12C
+
+#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_12 0xC4B130
+
+#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_13 0xC4B134
+
+#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_14 0xC4B138
+
+#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_15 0xC4B13C
+
+#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_16 0xC4B140
+
+#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_17 0xC4B144
+
+#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_18 0xC4B148
+
+#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_19 0xC4B14C
+
+#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_20 0xC4B150
+
+#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_21 0xC4B154
+
+#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_22 0xC4B158
+
+#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_23 0xC4B15C
+
+#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_24 0xC4B160
+
+#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_25 0xC4B164
+
+#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_26 0xC4B168
+
+#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_27 0xC4B16C
+
+#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_28 0xC4B170
+
+#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_29 0xC4B174
+
+#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_30 0xC4B178
+
+#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_31 0xC4B17C
+
+#define mmPSOC_GLOBAL_CONF_SEMAPHORE_0 0xC4B200
+
+#define mmPSOC_GLOBAL_CONF_SEMAPHORE_1 0xC4B204
+
+#define mmPSOC_GLOBAL_CONF_SEMAPHORE_2 0xC4B208
+
+#define mmPSOC_GLOBAL_CONF_SEMAPHORE_3 0xC4B20C
+
+#define mmPSOC_GLOBAL_CONF_SEMAPHORE_4 0xC4B210
+
+#define mmPSOC_GLOBAL_CONF_SEMAPHORE_5 0xC4B214
+
+#define mmPSOC_GLOBAL_CONF_SEMAPHORE_6 0xC4B218
+
+#define mmPSOC_GLOBAL_CONF_SEMAPHORE_7 0xC4B21C
+
+#define mmPSOC_GLOBAL_CONF_SEMAPHORE_8 0xC4B220
+
+#define mmPSOC_GLOBAL_CONF_SEMAPHORE_9 0xC4B224
+
+#define mmPSOC_GLOBAL_CONF_SEMAPHORE_10 0xC4B228
+
+#define mmPSOC_GLOBAL_CONF_SEMAPHORE_11 0xC4B22C
+
+#define mmPSOC_GLOBAL_CONF_SEMAPHORE_12 0xC4B230
+
+#define mmPSOC_GLOBAL_CONF_SEMAPHORE_13 0xC4B234
+
+#define mmPSOC_GLOBAL_CONF_SEMAPHORE_14 0xC4B238
+
+#define mmPSOC_GLOBAL_CONF_SEMAPHORE_15 0xC4B23C
+
+#define mmPSOC_GLOBAL_CONF_SEMAPHORE_16 0xC4B240
+
+#define mmPSOC_GLOBAL_CONF_SEMAPHORE_17 0xC4B244
+
+#define mmPSOC_GLOBAL_CONF_SEMAPHORE_18 0xC4B248
+
+#define mmPSOC_GLOBAL_CONF_SEMAPHORE_19 0xC4B24C
+
+#define mmPSOC_GLOBAL_CONF_SEMAPHORE_20 0xC4B250
+
+#define mmPSOC_GLOBAL_CONF_SEMAPHORE_21 0xC4B254
+
+#define mmPSOC_GLOBAL_CONF_SEMAPHORE_22 0xC4B258
+
+#define mmPSOC_GLOBAL_CONF_SEMAPHORE_23 0xC4B25C
+
+#define mmPSOC_GLOBAL_CONF_SEMAPHORE_24 0xC4B260
+
+#define mmPSOC_GLOBAL_CONF_SEMAPHORE_25 0xC4B264
+
+#define mmPSOC_GLOBAL_CONF_SEMAPHORE_26 0xC4B268
+
+#define mmPSOC_GLOBAL_CONF_SEMAPHORE_27 0xC4B26C
+
+#define mmPSOC_GLOBAL_CONF_SEMAPHORE_28 0xC4B270
+
+#define mmPSOC_GLOBAL_CONF_SEMAPHORE_29 0xC4B274
+
+#define mmPSOC_GLOBAL_CONF_SEMAPHORE_30 0xC4B278
+
+#define mmPSOC_GLOBAL_CONF_SEMAPHORE_31 0xC4B27C
+
+#define mmPSOC_GLOBAL_CONF_CPU_BOOT_STATUS 0xC4B300
+
+#define mmPSOC_GLOBAL_CONF_KMD_MSG_TO_CPU 0xC4B304
+
+#define mmPSOC_GLOBAL_CONF_SPL_SOURCE 0xC4B308
+
+#define mmPSOC_GLOBAL_CONF_I2C_MSTR1_DBG 0xC4B30C
+
+#define mmPSOC_GLOBAL_CONF_I2C_SLV 0xC4B310
+
+#define mmPSOC_GLOBAL_CONF_I2C_SLV_INTR_MASK 0xC4B314
+
+#define mmPSOC_GLOBAL_CONF_TRACE_ADDR 0xC4B320
+
+#define mmPSOC_GLOBAL_CONF_ARUSER 0xC4B330
+
+#define mmPSOC_GLOBAL_CONF_AWUSER 0xC4B334
+
+#define mmPSOC_GLOBAL_CONF_TRACE_AWUSER 0xC4B338
+
+#define mmPSOC_GLOBAL_CONF_TRACE_ARUSER 0xC4B33C
+
+#define mmPSOC_GLOBAL_CONF_BTL_STS 0xC4B340
+
+#define mmPSOC_GLOBAL_CONF_TIMEOUT_INTR 0xC4B350
+
+#define mmPSOC_GLOBAL_CONF_COMB_TIMEOUT_INTR 0xC4B354
+
+#define mmPSOC_GLOBAL_CONF_PERIPH_INTR 0xC4B358
+
+#define mmPSOC_GLOBAL_CONF_COMB_PERIPH_INTR 0xC4B35C
+
+#define mmPSOC_GLOBAL_CONF_AXI_ERR_INTR 0xC4B360
+
+#define mmPSOC_GLOBAL_CONF_TARGETID 0xC4B400
+
+#define mmPSOC_GLOBAL_CONF_EMMC_INT_VOL_STABLE 0xC4B420
+
+#define mmPSOC_GLOBAL_CONF_BOOT_STRAP_PINS 0xC4B430
+
+#define mmPSOC_GLOBAL_CONF_MEM_REPAIR_DIV 0xC4B44C
+
+#define mmPSOC_GLOBAL_CONF_MEM_REPAIR_CTRL 0xC4B450
+
+#define mmPSOC_GLOBAL_CONF_MEM_REPAIR_STS 0xC4B454
+
+#define mmPSOC_GLOBAL_CONF_OUTSTANT_TRANS 0xC4B458
+
+#define mmPSOC_GLOBAL_CONF_MASK_REQ 0xC4B45C
+
+#define mmPSOC_GLOBAL_CONF_WD_RST_CFG_L 0xC4B460
+
+#define mmPSOC_GLOBAL_CONF_WD_RST_CFG_H 0xC4B464
+
+#define mmPSOC_GLOBAL_CONF_MNL_RST_CFG_L 0xC4B470
+
+#define mmPSOC_GLOBAL_CONF_MNL_RST_CFG_H 0xC4B474
+
+#define mmPSOC_GLOBAL_CONF_PRSTN_RST_CFG_L 0xC4B480
+
+#define mmPSOC_GLOBAL_CONF_PRSTN_RST_CFG_H 0xC4B484
+
+#define mmPSOC_GLOBAL_CONF_SW_ALL_RST_CFG_L 0xC4B490
+
+#define mmPSOC_GLOBAL_CONF_SW_ALL_RST_CFG_H 0xC4B494
+
+#define mmPSOC_GLOBAL_CONF_SW_ALL_RST 0xC4B498
+
+#define mmPSOC_GLOBAL_CONF_SOFT_RST 0xC4B4A0
+
+#define mmPSOC_GLOBAL_CONF_SOFT_RST_CFG_L 0xC4B4A4
+
+#define mmPSOC_GLOBAL_CONF_SOFT_RST_CFG_H 0xC4B4A8
+
+#define mmPSOC_GLOBAL_CONF_UNIT_RST_N 0xC4B4B0
+
+#define mmPSOC_GLOBAL_CONF_UNIT_RST_N_L 0xC4B4B4
+
+#define mmPSOC_GLOBAL_CONF_UNIT_RST_N_H 0xC4B4B8
+
+#define mmPSOC_GLOBAL_CONF_BTL_IMG 0xC4B4E0
+
+#define mmPSOC_GLOBAL_CONF_PRSTN_MASK 0xC4B4E4
+
+#define mmPSOC_GLOBAL_CONF_WD_MASK 0xC4B4E8
+
+#define mmPSOC_GLOBAL_CONF_RST_SRC 0xC4B4F0
+
+#define mmPSOC_GLOBAL_CONF_BOOT_STATE 0xC4B4F4
+
+#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_0 0xC4B500
+
+#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_1 0xC4B504
+
+#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_2 0xC4B508
+
+#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_3 0xC4B50C
+
+#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_4 0xC4B510
+
+#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_5 0xC4B514
+
+#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_6 0xC4B518
+
+#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_7 0xC4B51C
+
+#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_8 0xC4B520
+
+#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_9 0xC4B524
+
+#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_10 0xC4B528
+
+#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_11 0xC4B52C
+
+#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_12 0xC4B530
+
+#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_13 0xC4B534
+
+#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_14 0xC4B538
+
+#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_15 0xC4B53C
+
+#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_16 0xC4B540
+
+#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_17 0xC4B544
+
+#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_18 0xC4B548
+
+#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_19 0xC4B54C
+
+#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_20 0xC4B550
+
+#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_21 0xC4B554
+
+#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_22 0xC4B558
+
+#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_23 0xC4B55C
+
+#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_24 0xC4B560
+
+#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_25 0xC4B564
+
+#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_26 0xC4B568
+
+#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_27 0xC4B56C
+
+#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_28 0xC4B570
+
+#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_29 0xC4B574
+
+#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_30 0xC4B578
+
+#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_31 0xC4B57C
+
+#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_32 0xC4B580
+
+#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_33 0xC4B584
+
+#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_34 0xC4B588
+
+#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_35 0xC4B58C
+
+#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_36 0xC4B590
+
+#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_37 0xC4B594
+
+#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_38 0xC4B598
+
+#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_39 0xC4B59C
+
+#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_40 0xC4B5A0
+
+#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_41 0xC4B5A4
+
+#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_42 0xC4B5A8
+
+#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_43 0xC4B5AC
+
+#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_44 0xC4B5B0
+
+#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_45 0xC4B5B4
+
+#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_46 0xC4B5B8
+
+#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_47 0xC4B5BC
+
+#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_48 0xC4B5C0
+
+#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_49 0xC4B5C4
+
+#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_50 0xC4B5C8
+
+#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_51 0xC4B5CC
+
+#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_52 0xC4B5D0
+
+#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_53 0xC4B5D4
+
+#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_54 0xC4B5D8
+
+#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_55 0xC4B5DC
+
+#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_56 0xC4B5E0
+
+#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_57 0xC4B5E4
+
+#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_58 0xC4B5E8
+
+#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_59 0xC4B5EC
+
+#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_60 0xC4B5F0
+
+#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_61 0xC4B5F4
+
+#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_62 0xC4B5F8
+
+#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_63 0xC4B5FC
+
+#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_64 0xC4B600
+
+#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_65 0xC4B604
+
+#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_66 0xC4B608
+
+#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_67 0xC4B60C
+
+#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_68 0xC4B610
+
+#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_69 0xC4B614
+
+#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_70 0xC4B618
+
+#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_71 0xC4B61C
+
+#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_72 0xC4B620
+
+#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_73 0xC4B624
+
+#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_74 0xC4B628
+
+#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_75 0xC4B62C
+
+#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_76 0xC4B630
+
+#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_77 0xC4B634
+
+#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_78 0xC4B638
+
+#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_79 0xC4B63C
+
+#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_80 0xC4B640
+
+#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_81 0xC4B644
+
+#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_82 0xC4B648
+
+#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_83 0xC4B64C
+
+#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_84 0xC4B650
+
+#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_85 0xC4B654
+
+#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_86 0xC4B658
+
+#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_87 0xC4B65C
+
+#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_88 0xC4B660
+
+#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_89 0xC4B664
+
+#define mmPSOC_GLOBAL_CONF_PAD_3V3_CFG_0 0xC4B690
+
+#define mmPSOC_GLOBAL_CONF_PAD_3V3_CFG_1 0xC4B694
+
+#define mmPSOC_GLOBAL_CONF_PAD_3V3_CFG_2 0xC4B698
+
+#define mmPSOC_GLOBAL_CONF_PAD_3V3_CFG_3 0xC4B69C
+
+#define mmPSOC_GLOBAL_CONF_PAD_3V3_CFG_4 0xC4B6A0
+
+#define mmPSOC_GLOBAL_CONF_PAD_3V3_CFG_5 0xC4B6A4
+
+#define mmPSOC_GLOBAL_CONF_PAD_3V3_CFG_6 0xC4B6A8
+
+#define mmPSOC_GLOBAL_CONF_PAD_3V3_CFG_7 0xC4B6AC
+
+#define mmPSOC_GLOBAL_CONF_PAD_3V3_CFG_8 0xC4B6B0
+
+#define mmPSOC_GLOBAL_CONF_PAD_3V3_CFG_9 0xC4B6B4
+
+#define mmPSOC_GLOBAL_CONF_PAD_3V3_CFG_10 0xC4B6B8
+
+#define mmPSOC_GLOBAL_CONF_PAD_3V3_CFG_11 0xC4B6BC
+
+#define mmPSOC_GLOBAL_CONF_PAD_1V8_INPUT_0 0xC4B6C0
+
+#define mmPSOC_GLOBAL_CONF_PAD_1V8_INPUT_1 0xC4B6C4
+
+#define mmPSOC_GLOBAL_CONF_PAD_1V8_INPUT_2 0xC4B6C8
+
+#define mmPSOC_GLOBAL_CONF_PAD_1V8_INPUT_3 0xC4B6CC
+
+#define mmPSOC_GLOBAL_CONF_PAD_1V8_INPUT_4 0xC4B6D0
+
+#define mmPSOC_GLOBAL_CONF_PAD_1V8_INPUT_5 0xC4B6D4
+
+#define mmPSOC_GLOBAL_CONF_PAD_1V8_INPUT_6 0xC4B6D8
+
+#define mmPSOC_GLOBAL_CONF_PAD_1V8_INPUT_7 0xC4B6DC
+
+#define mmPSOC_GLOBAL_CONF_BNK3V3_MS 0xC4B710
+
+#define mmPSOC_GLOBAL_CONF_ADC_CLK_FREQ 0xC4B720
+
+#define mmPSOC_GLOBAL_CONF_ADC_DELAY_FROM_START 0xC4B724
+
+#define mmPSOC_GLOBAL_CONF_ADC_DATA_SAMPLES 0xC4B728
+
+#define mmPSOC_GLOBAL_CONF_ADC_TPH_CS 0xC4B72C
+
+#define mmPSOC_GLOBAL_CONF_ADC_LSB_NMSB 0xC4B730
+
+#define mmPSOC_GLOBAL_CONF_ADC_ONE_NCONTIUES 0xC4B734
+
+#define mmPSOC_GLOBAL_CONF_ADC_BLOCK_ENABLE 0xC4B738
+
+#define mmPSOC_GLOBAL_CONF_ADC_CFG_DATA 0xC4B73C
+
+#define mmPSOC_GLOBAL_CONF_ADC_TDV_CSDO 0xC4B740
+
+#define mmPSOC_GLOBAL_CONF_ADC_TSU_CSCK 0xC4B744
+
+#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_0 0xC4B800
+
+#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_1 0xC4B804
+
+#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_2 0xC4B808
+
+#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_3 0xC4B80C
+
+#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_4 0xC4B810
+
+#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_5 0xC4B814
+
+#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_6 0xC4B818
+
+#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_7 0xC4B81C
+
+#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_8 0xC4B820
+
+#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_9 0xC4B824
+
+#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_10 0xC4B828
+
+#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_11 0xC4B82C
+
+#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_12 0xC4B830
+
+#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_13 0xC4B834
+
+#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_14 0xC4B838
+
+#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_15 0xC4B83C
+
+#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_16 0xC4B840
+
+#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_17 0xC4B844
+
+#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_18 0xC4B848
+
+#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_19 0xC4B84C
+
+#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_20 0xC4B850
+
+#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_21 0xC4B854
+
+#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_22 0xC4B858
+
+#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_23 0xC4B85C
+
+#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_24 0xC4B860
+
+#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_25 0xC4B864
+
+#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_26 0xC4B868
+
+#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_27 0xC4B86C
+
+#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_28 0xC4B870
+
+#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_29 0xC4B874
+
+#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_30 0xC4B878
+
+#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_31 0xC4B87C
+
+#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_32 0xC4B880
+
+#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_33 0xC4B884
+
+#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_34 0xC4B888
+
+#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_35 0xC4B88C
+
+#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_36 0xC4B890
+
+#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_37 0xC4B894
+
+#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_38 0xC4B898
+
+#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_39 0xC4B89C
+
+#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_40 0xC4B8A0
+
+#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_41 0xC4B8A4
+
+#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_42 0xC4B8A8
+
+#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_43 0xC4B8AC
+
+#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_44 0xC4B8B0
+
+#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_45 0xC4B8B4
+
+#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_46 0xC4B8B8
+
+#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_47 0xC4B8BC
+
+#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_48 0xC4B8C0
+
+#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_49 0xC4B8C4
+
+#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_50 0xC4B8C8
+
+#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_51 0xC4B8CC
+
+#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_52 0xC4B8D0
+
+#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_53 0xC4B8D4
+
+#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_54 0xC4B8D8
+
+#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_55 0xC4B8DC
+
+#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_56 0xC4B8E0
+
+#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_57 0xC4B8E4
+
+#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_58 0xC4B8E8
+
+#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_59 0xC4B8EC
+
+#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_60 0xC4B8F0
+
+#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_61 0xC4B8F4
+
+#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_62 0xC4B8F8
+
+#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_63 0xC4B8FC
+
+#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_64 0xC4B900
+
+#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_65 0xC4B904
+
+#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_66 0xC4B908
+
+#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_67 0xC4B90C
+
+#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_68 0xC4B910
+
+#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_69 0xC4B914
+
+#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_70 0xC4B918
+
+#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_71 0xC4B91C
+
+#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_72 0xC4B920
+
+#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_73 0xC4B924
+
+#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_74 0xC4B928
+
+#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_75 0xC4B92C
+
+#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_76 0xC4B930
+
+#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_77 0xC4B934
+
+#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_78 0xC4B938
+
+#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_79 0xC4B93C
+
+#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_80 0xC4B940
+
+#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_81 0xC4B944
+
+#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_82 0xC4B948
+
+#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_83 0xC4B94C
+
+#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_84 0xC4B950
+
+#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_85 0xC4B954
+
+#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_86 0xC4B958
+
+#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_87 0xC4B95C
+
+#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_88 0xC4B960
+
+#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_89 0xC4B964
+
+#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_90 0xC4B968
+
+#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_91 0xC4B96C
+
+#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_92 0xC4B970
+
+#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_93 0xC4B974
+
+#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_94 0xC4B978
+
+#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_95 0xC4B97C
+
+#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_96 0xC4B980
+
+#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_97 0xC4B984
+
+#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_98 0xC4B988
+
+#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_99 0xC4B98C
+
+#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_100 0xC4B990
+
+#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_101 0xC4B994
+
+#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_102 0xC4B998
+
+#define mmPSOC_GLOBAL_CONF_PAD_SEL_0 0xC4BA00
+
+#define mmPSOC_GLOBAL_CONF_PAD_SEL_1 0xC4BA04
+
+#define mmPSOC_GLOBAL_CONF_PAD_SEL_2 0xC4BA08
+
+#define mmPSOC_GLOBAL_CONF_PAD_SEL_3 0xC4BA0C
+
+#define mmPSOC_GLOBAL_CONF_PAD_SEL_4 0xC4BA10
+
+#define mmPSOC_GLOBAL_CONF_PAD_SEL_5 0xC4BA14
+
+#define mmPSOC_GLOBAL_CONF_PAD_SEL_6 0xC4BA18
+
+#define mmPSOC_GLOBAL_CONF_PAD_SEL_7 0xC4BA1C
+
+#define mmPSOC_GLOBAL_CONF_PAD_SEL_8 0xC4BA20
+
+#define mmPSOC_GLOBAL_CONF_PAD_SEL_9 0xC4BA24
+
+#define mmPSOC_GLOBAL_CONF_PAD_SEL_10 0xC4BA28
+
+#define mmPSOC_GLOBAL_CONF_PAD_SEL_11 0xC4BA2C
+
+#define mmPSOC_GLOBAL_CONF_PAD_SEL_12 0xC4BA30
+
+#define mmPSOC_GLOBAL_CONF_PAD_SEL_13 0xC4BA34
+
+#define mmPSOC_GLOBAL_CONF_PAD_SEL_14 0xC4BA38
+
+#define mmPSOC_GLOBAL_CONF_PAD_SEL_15 0xC4BA3C
+
+#define mmPSOC_GLOBAL_CONF_PAD_SEL_16 0xC4BA40
+
+#define mmPSOC_GLOBAL_CONF_PAD_SEL_17 0xC4BA44
+
+#define mmPSOC_GLOBAL_CONF_PAD_SEL_18 0xC4BA48
+
+#define mmPSOC_GLOBAL_CONF_PAD_SEL_19 0xC4BA4C
+
+#define mmPSOC_GLOBAL_CONF_PAD_SEL_20 0xC4BA50
+
+#define mmPSOC_GLOBAL_CONF_PAD_SEL_21 0xC4BA54
+
+#define mmPSOC_GLOBAL_CONF_PAD_SEL_22 0xC4BA58
+
+#define mmPSOC_GLOBAL_CONF_PAD_SEL_23 0xC4BA5C
+
+#define mmPSOC_GLOBAL_CONF_PAD_SEL_24 0xC4BA60
+
+#define mmPSOC_GLOBAL_CONF_PAD_SEL_25 0xC4BA64
+
+#define mmPSOC_GLOBAL_CONF_PAD_SEL_26 0xC4BA68
+
+#define mmPSOC_GLOBAL_CONF_PAD_SEL_27 0xC4BA6C
+
+#define mmPSOC_GLOBAL_CONF_PAD_SEL_28 0xC4BA70
+
+#define mmPSOC_GLOBAL_CONF_PAD_SEL_29 0xC4BA74
+
+#define mmPSOC_GLOBAL_CONF_PAD_SEL_30 0xC4BA78
+
+#define mmPSOC_GLOBAL_CONF_PAD_SEL_31 0xC4BA7C
+
+#define mmPSOC_GLOBAL_CONF_PAD_SEL_32 0xC4BA80
+
+#define mmPSOC_GLOBAL_CONF_PAD_SEL_33 0xC4BA84
+
+#define mmPSOC_GLOBAL_CONF_PAD_SEL_34 0xC4BA88
+
+#define mmPSOC_GLOBAL_CONF_PAD_SEL_35 0xC4BA8C
+
+#define mmPSOC_GLOBAL_CONF_PAD_SEL_36 0xC4BA90
+
+#define mmPSOC_GLOBAL_CONF_PAD_SEL_37 0xC4BA94
+
+#define mmPSOC_GLOBAL_CONF_PAD_SEL_38 0xC4BA98
+
+#define mmPSOC_GLOBAL_CONF_PAD_SEL_39 0xC4BA9C
+
+#define mmPSOC_GLOBAL_CONF_PAD_SEL_40 0xC4BAA0
+
+#define mmPSOC_GLOBAL_CONF_PAD_SEL_41 0xC4BAA4
+
+#define mmPSOC_GLOBAL_CONF_PAD_SEL_42 0xC4BAA8
+
+#define mmPSOC_GLOBAL_CONF_PAD_SEL_43 0xC4BAAC
+
+#define mmPSOC_GLOBAL_CONF_PAD_SEL_44 0xC4BAB0
+
+#define mmPSOC_GLOBAL_CONF_PAD_SEL_45 0xC4BAB4
+
+#define mmPSOC_GLOBAL_CONF_PAD_SEL_46 0xC4BAB8
+
+#define mmPSOC_GLOBAL_CONF_PAD_SEL_47 0xC4BABC
+
+#define mmPSOC_GLOBAL_CONF_PAD_SEL_48 0xC4BAC0
+
+#define mmPSOC_GLOBAL_CONF_PAD_SEL_49 0xC4BAC4
+
+#define mmPSOC_GLOBAL_CONF_PAD_SEL_50 0xC4BAC8
+
+#define mmPSOC_GLOBAL_CONF_PAD_SEL_51 0xC4BACC
+
+#define mmPSOC_GLOBAL_CONF_PAD_SEL_52 0xC4BAD0
+
+#define mmPSOC_GLOBAL_CONF_PAD_SEL_53 0xC4BAD4
+
+#define mmPSOC_GLOBAL_CONF_PAD_SEL_54 0xC4BAD8
+
+#define mmPSOC_GLOBAL_CONF_PAD_SEL_55 0xC4BADC
+
+#define mmPSOC_GLOBAL_CONF_PAD_SEL_56 0xC4BAE0
+
+#define mmPSOC_GLOBAL_CONF_PAD_SEL_57 0xC4BAE4
+
+#define mmPSOC_GLOBAL_CONF_PAD_SEL_58 0xC4BAE8
+
+#define mmPSOC_GLOBAL_CONF_PAD_SEL_59 0xC4BAEC
+
+#define mmPSOC_GLOBAL_CONF_PAD_SEL_60 0xC4BAF0
+
+#define mmPSOC_GLOBAL_CONF_PAD_SEL_61 0xC4BAF4
+
+#define mmPSOC_GLOBAL_CONF_PAD_SEL_62 0xC4BAF8
+
+#define mmPSOC_GLOBAL_CONF_PAD_SEL_63 0xC4BAFC
+
+#define mmPSOC_GLOBAL_CONF_PAD_SEL_64 0xC4BB00
+
+#define mmPSOC_GLOBAL_CONF_PAD_SEL_65 0xC4BB04
+
+#define mmPSOC_GLOBAL_CONF_PAD_SEL_66 0xC4BB08
+
+#define mmPSOC_GLOBAL_CONF_PAD_SEL_67 0xC4BB0C
+
+#define mmPSOC_GLOBAL_CONF_PAD_SEL_68 0xC4BB10
+
+#define mmPSOC_GLOBAL_CONF_PAD_SEL_69 0xC4BB14
+
+#define mmPSOC_GLOBAL_CONF_PAD_SEL_70 0xC4BB18
+
+#define mmPSOC_GLOBAL_CONF_PAD_SEL_71 0xC4BB1C
+
+#define mmPSOC_GLOBAL_CONF_PAD_SEL_72 0xC4BB20
+
+#define mmPSOC_GLOBAL_CONF_PAD_SEL_73 0xC4BB24
+
+#define mmPSOC_GLOBAL_CONF_PAD_SEL_74 0xC4BB28
+
+#define mmPSOC_GLOBAL_CONF_PAD_SEL_75 0xC4BB2C
+
+#define mmPSOC_GLOBAL_CONF_PAD_SEL_76 0xC4BB30
+
+#define mmPSOC_GLOBAL_CONF_PAD_SEL_77 0xC4BB34
+
+#define mmPSOC_GLOBAL_CONF_PAD_SEL_78 0xC4BB38
+
+#define mmPSOC_GLOBAL_CONF_PAD_SEL_79 0xC4BB3C
+
+#define mmPSOC_GLOBAL_CONF_PAD_SEL_80 0xC4BB40
+
+#define mmPSOC_GLOBAL_CONF_PAD_SEL_81 0xC4BB44
+
+#define mmPSOC_GLOBAL_CONF_PAD_SEL_82 0xC4BB48
+
+#define mmPSOC_GLOBAL_CONF_PAD_SEL_83 0xC4BB4C
+
+#define mmPSOC_GLOBAL_CONF_PAD_SEL_84 0xC4BB50
+
+#define mmPSOC_GLOBAL_CONF_PAD_SEL_85 0xC4BB54
+
+#define mmPSOC_GLOBAL_CONF_PAD_SEL_86 0xC4BB58
+
+#define mmPSOC_GLOBAL_CONF_PAD_SEL_87 0xC4BB5C
+
+#define mmPSOC_GLOBAL_CONF_PAD_SEL_88 0xC4BB60
+
+#define mmPSOC_GLOBAL_CONF_PAD_SEL_89 0xC4BB64
+
+#define mmPSOC_GLOBAL_CONF_PAD_SEL_90 0xC4BB68
+
+#define mmPSOC_GLOBAL_CONF_PAD_SEL_91 0xC4BB6C
+
+#define mmPSOC_GLOBAL_CONF_PAD_SEL_92 0xC4BB70
+
+#define mmPSOC_GLOBAL_CONF_PAD_SEL_93 0xC4BB74
+
+#define mmPSOC_GLOBAL_CONF_PAD_SEL_94 0xC4BB78
+
+#define mmPSOC_GLOBAL_CONF_PAD_SEL_95 0xC4BB7C
+
+#define mmPSOC_GLOBAL_CONF_PAD_SEL_96 0xC4BB80
+
+#define mmPSOC_GLOBAL_CONF_PAD_SEL_97 0xC4BB84
+
+#define mmPSOC_GLOBAL_CONF_PAD_SEL_98 0xC4BB88
+
+#define mmPSOC_GLOBAL_CONF_PAD_SEL_99 0xC4BB8C
+
+#define mmPSOC_GLOBAL_CONF_PAD_SEL_100 0xC4BB90
+
+#define mmPSOC_GLOBAL_CONF_PAD_SEL_101 0xC4BB94
+
+#define mmPSOC_GLOBAL_CONF_PAD_SEL_102 0xC4BB98
+
+#define mmPSOC_GLOBAL_CONF_RST_CTRL_0 0xC4BC00
+
+#define mmPSOC_GLOBAL_CONF_RST_CTRL_1 0xC4BC04
+
+#define mmPSOC_GLOBAL_CONF_RST_CTRL_2 0xC4BC08
+
+#define mmPSOC_GLOBAL_CONF_RST_CTRL_3 0xC4BC0C
+
+#define mmPSOC_GLOBAL_CONF_RST_CTRL_4 0xC4BC10
+
+#define mmPSOC_GLOBAL_CONF_RST_CTRL_5 0xC4BC14
+
+#define mmPSOC_GLOBAL_CONF_RST_CTRL_6 0xC4BC18
+
+#define mmPSOC_GLOBAL_CONF_RST_CTRL_7 0xC4BC1C
+
+#define mmPSOC_GLOBAL_CONF_RST_CTRL_8 0xC4BC20
+
+#define mmPSOC_GLOBAL_CONF_RST_CTRL_9 0xC4BC24
+
+#define mmPSOC_GLOBAL_CONF_RST_CTRL_10 0xC4BC28
+
+#define mmPSOC_GLOBAL_CONF_RST_CTRL_11 0xC4BC2C
+
+#define mmPSOC_GLOBAL_CONF_RST_CTRL_12 0xC4BC30
+
+#define mmPSOC_GLOBAL_CONF_RST_CTRL_13 0xC4BC34
+
+#define mmPSOC_GLOBAL_CONF_RST_CTRL_14 0xC4BC38
+
+#define mmPSOC_GLOBAL_CONF_RST_CTRL_15 0xC4BC3C
+
+#define mmPSOC_GLOBAL_CONF_RST_CTRL_16 0xC4BC40
+
+#define mmPSOC_GLOBAL_CONF_RST_CTRL_17 0xC4BC44
+
+#define mmPSOC_GLOBAL_CONF_RST_CTRL_18 0xC4BC48
+
+#define mmPSOC_GLOBAL_CONF_RST_CTRL_19 0xC4BC4C
+
+#define mmPSOC_GLOBAL_CONF_RST_CTRL_20 0xC4BC50
+
+#define mmPSOC_GLOBAL_CONF_RST_CTRL_21 0xC4BC54
+
+#define mmPSOC_GLOBAL_CONF_RST_CTRL_22 0xC4BC58
+
+#define mmPSOC_GLOBAL_CONF_RST_CTRL_23 0xC4BC5C
+
+#define mmPSOC_GLOBAL_CONF_RST_CTRL_24 0xC4BC60
+
+#define mmPSOC_GLOBAL_CONF_RST_CTRL_25 0xC4BC64
+
+#define mmPSOC_GLOBAL_CONF_RST_CTRL_26 0xC4BC68
+
+#define mmPSOC_GLOBAL_CONF_RST_CTRL_27 0xC4BC6C
+
+#define mmPSOC_GLOBAL_CONF_RST_CTRL_28 0xC4BC70
+
+#define mmPSOC_GLOBAL_CONF_RST_CTRL_29 0xC4BC74
+
+#define mmPSOC_GLOBAL_CONF_RST_CTRL_30 0xC4BC78
+
+#define mmPSOC_GLOBAL_CONF_RST_CTRL_31 0xC4BC7C
+
+#define mmPSOC_GLOBAL_CONF_RST_CTRL_32 0xC4BC80
+
+#define mmPSOC_GLOBAL_CONF_RST_CTRL_33 0xC4BC84
+
+#define mmPSOC_GLOBAL_CONF_RST_CTRL_34 0xC4BC88
+
+#define mmPSOC_GLOBAL_CONF_RST_CTRL_35 0xC4BC8C
+
+#define mmPSOC_GLOBAL_CONF_RST_CTRL_36 0xC4BC90
+
+#define mmPSOC_GLOBAL_CONF_RST_CTRL_37 0xC4BC94
+
+#define mmPSOC_GLOBAL_CONF_RST_CTRL_38 0xC4BC98
+
+#define mmPSOC_GLOBAL_CONF_RST_CTRL_39 0xC4BC9C
+
+#define mmPSOC_GLOBAL_CONF_RST_CTRL_40 0xC4BCA0
+
+#define mmPSOC_GLOBAL_CONF_RST_CTRL_41 0xC4BCA4
+
+#define mmPSOC_GLOBAL_CONF_RST_CTRL_42 0xC4BCA8
+
+#define mmPSOC_GLOBAL_CONF_RST_CTRL_43 0xC4BCAC
+
+#define mmPSOC_GLOBAL_CONF_RST_CTRL_44 0xC4BCB0
+
+#define mmPSOC_GLOBAL_CONF_RST_CTRL_45 0xC4BCB4
+
+#define mmPSOC_GLOBAL_CONF_RST_CTRL_46 0xC4BCB8
+
+#define mmPSOC_GLOBAL_CONF_RST_CTRL_47 0xC4BCBC
+
+#define mmPSOC_GLOBAL_CONF_RST_CTRL_48 0xC4BCC0
+
+#define mmPSOC_GLOBAL_CONF_RST_CTRL_49 0xC4BCC4
+
+#define mmPSOC_GLOBAL_CONF_RST_CTRL_50 0xC4BCC8
+
+#define mmPSOC_GLOBAL_CONF_RST_CTRL_51 0xC4BCCC
+
+#define mmPSOC_GLOBAL_CONF_RST_CTRL_52 0xC4BCD0
+
+#define mmPSOC_GLOBAL_CONF_RST_CTRL_53 0xC4BCD4
+
+#endif /* ASIC_REG_PSOC_GLOBAL_CONF_REGS_H_ */
diff --git a/drivers/accel/habanalabs/include/gaudi/asic_reg/psoc_timestamp_regs.h b/drivers/accel/habanalabs/include/gaudi/asic_reg/psoc_timestamp_regs.h
new file mode 100644
index 0000000000..9ce24597d4
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi/asic_reg/psoc_timestamp_regs.h
@@ -0,0 +1,56 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2016-2018 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ ** DO NOT EDIT BELOW **
+ ************************************/
+
+#ifndef ASIC_REG_PSOC_TIMESTAMP_REGS_H_
+#define ASIC_REG_PSOC_TIMESTAMP_REGS_H_
+
+/*
+ *****************************************
+ * PSOC_TIMESTAMP (Prototype: TIMESTAMP)
+ *****************************************
+ */
+
+#define mmPSOC_TIMESTAMP_CNTCR 0xC49000
+
+#define mmPSOC_TIMESTAMP_CNTSR 0xC49004
+
+#define mmPSOC_TIMESTAMP_CNTCVL 0xC49008
+
+#define mmPSOC_TIMESTAMP_CNTCVU 0xC4900C
+
+#define mmPSOC_TIMESTAMP_CNTFID0 0xC49020
+
+#define mmPSOC_TIMESTAMP_PIDR4 0xC49FD0
+
+#define mmPSOC_TIMESTAMP_PIDR5 0xC49FD4
+
+#define mmPSOC_TIMESTAMP_PIDR6 0xC49FD8
+
+#define mmPSOC_TIMESTAMP_PIDR7 0xC49FDC
+
+#define mmPSOC_TIMESTAMP_PIDR0 0xC49FE0
+
+#define mmPSOC_TIMESTAMP_PIDR1 0xC49FE4
+
+#define mmPSOC_TIMESTAMP_PIDR2 0xC49FE8
+
+#define mmPSOC_TIMESTAMP_PIDR3 0xC49FEC
+
+#define mmPSOC_TIMESTAMP_CIDR0 0xC49FF0
+
+#define mmPSOC_TIMESTAMP_CIDR1 0xC49FF4
+
+#define mmPSOC_TIMESTAMP_CIDR2 0xC49FF8
+
+#define mmPSOC_TIMESTAMP_CIDR3 0xC49FFC
+
+#endif /* ASIC_REG_PSOC_TIMESTAMP_REGS_H_ */
diff --git a/drivers/accel/habanalabs/include/gaudi/asic_reg/sif_rtr_ctrl_0_regs.h b/drivers/accel/habanalabs/include/gaudi/asic_reg/sif_rtr_ctrl_0_regs.h
new file mode 100644
index 0000000000..ddf824392c
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi/asic_reg/sif_rtr_ctrl_0_regs.h
@@ -0,0 +1,896 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2016-2018 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ ** DO NOT EDIT BELOW **
+ ************************************/
+
+#ifndef ASIC_REG_SIF_RTR_CTRL_0_REGS_H_
+#define ASIC_REG_SIF_RTR_CTRL_0_REGS_H_
+
+/*
+ *****************************************
+ * SIF_RTR_CTRL_0 (Prototype: RTR_CTRL)
+ *****************************************
+ */
+
+#define mmSIF_RTR_CTRL_0_PERM_SEL 0x306108
+
+#define mmSIF_RTR_CTRL_0_HBM_POLY_H3_0 0x306114
+
+#define mmSIF_RTR_CTRL_0_HBM_POLY_H3_1 0x306118
+
+#define mmSIF_RTR_CTRL_0_HBM_POLY_H3_2 0x30611C
+
+#define mmSIF_RTR_CTRL_0_HBM_POLY_H3_3 0x306120
+
+#define mmSIF_RTR_CTRL_0_HBM_POLY_H3_4 0x306124
+
+#define mmSIF_RTR_CTRL_0_HBM_POLY_H3_5 0x306128
+
+#define mmSIF_RTR_CTRL_0_HBM_POLY_H3_6 0x30612C
+
+#define mmSIF_RTR_CTRL_0_HBM_POLY_H3_7 0x306130
+
+#define mmSIF_RTR_CTRL_0_HBM_POLY_H3_8 0x306134
+
+#define mmSIF_RTR_CTRL_0_HBM_POLY_H3_9 0x306138
+
+#define mmSIF_RTR_CTRL_0_HBM_POLY_H3_10 0x30613C
+
+#define mmSIF_RTR_CTRL_0_HBM_POLY_H3_11 0x306140
+
+#define mmSIF_RTR_CTRL_0_HBM_POLY_H3_12 0x306144
+
+#define mmSIF_RTR_CTRL_0_HBM_POLY_H3_13 0x306148
+
+#define mmSIF_RTR_CTRL_0_HBM_POLY_H3_14 0x30614C
+
+#define mmSIF_RTR_CTRL_0_HBM_POLY_H3_15 0x306150
+
+#define mmSIF_RTR_CTRL_0_HBM_POLY_H3_16 0x306154
+
+#define mmSIF_RTR_CTRL_0_HBM_POLY_H3_17 0x306158
+
+#define mmSIF_RTR_CTRL_0_HBM_POLY_H3_18 0x30615C
+
+#define mmSIF_RTR_CTRL_0_HBM_POLY_H3_19 0x306160
+
+#define mmSIF_RTR_CTRL_0_HBM_POLY_H3_20 0x306164
+
+#define mmSIF_RTR_CTRL_0_HBM_POLY_H3_21 0x306168
+
+#define mmSIF_RTR_CTRL_0_HBM_POLY_H3_22 0x30616C
+
+#define mmSIF_RTR_CTRL_0_HBM_POLY_H3_23 0x306170
+
+#define mmSIF_RTR_CTRL_0_HBM_POLY_H3_24 0x306174
+
+#define mmSIF_RTR_CTRL_0_HBM_POLY_H3_25 0x306178
+
+#define mmSIF_RTR_CTRL_0_HBM_POLY_H3_26 0x30617C
+
+#define mmSIF_RTR_CTRL_0_HBM_POLY_H3_27 0x306180
+
+#define mmSIF_RTR_CTRL_0_SRAM_POLY_H3_0 0x306184
+
+#define mmSIF_RTR_CTRL_0_SRAM_POLY_H3_1 0x306188
+
+#define mmSIF_RTR_CTRL_0_SRAM_POLY_H3_2 0x30618C
+
+#define mmSIF_RTR_CTRL_0_SRAM_POLY_H3_3 0x306190
+
+#define mmSIF_RTR_CTRL_0_SRAM_POLY_H3_4 0x306194
+
+#define mmSIF_RTR_CTRL_0_SRAM_POLY_H3_5 0x306198
+
+#define mmSIF_RTR_CTRL_0_SRAM_POLY_H3_6 0x30619C
+
+#define mmSIF_RTR_CTRL_0_SRAM_POLY_H3_7 0x3061A0
+
+#define mmSIF_RTR_CTRL_0_SRAM_POLY_H3_8 0x3061A4
+
+#define mmSIF_RTR_CTRL_0_SRAM_POLY_H3_9 0x3061A8
+
+#define mmSIF_RTR_CTRL_0_SRAM_POLY_H3_10 0x3061AC
+
+#define mmSIF_RTR_CTRL_0_SRAM_POLY_H3_11 0x3061B0
+
+#define mmSIF_RTR_CTRL_0_SRAM_POLY_H3_12 0x3061B4
+
+#define mmSIF_RTR_CTRL_0_SRAM_POLY_H3_13 0x3061B8
+
+#define mmSIF_RTR_CTRL_0_SRAM_POLY_H3_14 0x3061BC
+
+#define mmSIF_RTR_CTRL_0_SCRAM_SRAM_EN 0x30626C
+
+#define mmSIF_RTR_CTRL_0_RL_HBM_EN 0x306274
+
+#define mmSIF_RTR_CTRL_0_RL_HBM_SAT 0x306278
+
+#define mmSIF_RTR_CTRL_0_RL_HBM_RST 0x30627C
+
+#define mmSIF_RTR_CTRL_0_RL_HBM_TIMEOUT 0x306280
+
+#define mmSIF_RTR_CTRL_0_SCRAM_HBM_EN 0x306284
+
+#define mmSIF_RTR_CTRL_0_RL_PCI_EN 0x306288
+
+#define mmSIF_RTR_CTRL_0_RL_PCI_SAT 0x30628C
+
+#define mmSIF_RTR_CTRL_0_RL_PCI_RST 0x306290
+
+#define mmSIF_RTR_CTRL_0_RL_PCI_TIMEOUT 0x306294
+
+#define mmSIF_RTR_CTRL_0_RL_SRAM_EN 0x30629C
+
+#define mmSIF_RTR_CTRL_0_RL_SRAM_SAT 0x3062A0
+
+#define mmSIF_RTR_CTRL_0_RL_SRAM_RST 0x3062A4
+
+#define mmSIF_RTR_CTRL_0_RL_SRAM_TIMEOUT 0x3062AC
+
+#define mmSIF_RTR_CTRL_0_RL_SRAM_RED 0x3062B4
+
+#define mmSIF_RTR_CTRL_0_E2E_HBM_EN 0x3062EC
+
+#define mmSIF_RTR_CTRL_0_E2E_PCI_EN 0x3062F0
+
+#define mmSIF_RTR_CTRL_0_E2E_HBM_WR_SIZE 0x3062F4
+
+#define mmSIF_RTR_CTRL_0_E2E_PCI_WR_SIZE 0x3062F8
+
+#define mmSIF_RTR_CTRL_0_E2E_AW_PCI_CTR_SET_EN 0x306404
+
+#define mmSIF_RTR_CTRL_0_E2E_AW_PCI_CTR_SET 0x306408
+
+#define mmSIF_RTR_CTRL_0_E2E_AW_PCI_CTR_WRAP 0x30640C
+
+#define mmSIF_RTR_CTRL_0_E2E_AW_PCI_CTR_CNT 0x306410
+
+#define mmSIF_RTR_CTRL_0_E2E_AW_HBM_CTR_SET_EN 0x306414
+
+#define mmSIF_RTR_CTRL_0_E2E_AW_HBM_CTR_SET 0x306418
+
+#define mmSIF_RTR_CTRL_0_E2E_HBM_RD_SIZE 0x30641C
+
+#define mmSIF_RTR_CTRL_0_E2E_PCI_RD_SIZE 0x306420
+
+#define mmSIF_RTR_CTRL_0_E2E_AR_PCI_CTR_SET_EN 0x306424
+
+#define mmSIF_RTR_CTRL_0_E2E_AR_PCI_CTR_SET 0x306428
+
+#define mmSIF_RTR_CTRL_0_E2E_AR_PCI_CTR_WRAP 0x30642C
+
+#define mmSIF_RTR_CTRL_0_E2E_AR_PCI_CTR_CNT 0x306430
+
+#define mmSIF_RTR_CTRL_0_E2E_AR_HBM_CTR_SET_EN 0x306434
+
+#define mmSIF_RTR_CTRL_0_E2E_AR_HBM_CTR_SET 0x306438
+
+#define mmSIF_RTR_CTRL_0_NL_HBM_SEL_0 0x306450
+
+#define mmSIF_RTR_CTRL_0_NL_HBM_SEL_1 0x306454
+
+#define mmSIF_RTR_CTRL_0_NON_LIN_EN 0x306480
+
+#define mmSIF_RTR_CTRL_0_NL_SRAM_BANK_0 0x306500
+
+#define mmSIF_RTR_CTRL_0_NL_SRAM_BANK_1 0x306504
+
+#define mmSIF_RTR_CTRL_0_NL_SRAM_BANK_2 0x306508
+
+#define mmSIF_RTR_CTRL_0_NL_SRAM_BANK_3 0x30650C
+
+#define mmSIF_RTR_CTRL_0_NL_SRAM_BANK_4 0x306510
+
+#define mmSIF_RTR_CTRL_0_NL_SRAM_OFFSET_0 0x306514
+
+#define mmSIF_RTR_CTRL_0_NL_SRAM_OFFSET_1 0x306520
+
+#define mmSIF_RTR_CTRL_0_NL_SRAM_OFFSET_2 0x306524
+
+#define mmSIF_RTR_CTRL_0_NL_SRAM_OFFSET_3 0x306528
+
+#define mmSIF_RTR_CTRL_0_NL_SRAM_OFFSET_4 0x30652C
+
+#define mmSIF_RTR_CTRL_0_NL_SRAM_OFFSET_5 0x306530
+
+#define mmSIF_RTR_CTRL_0_NL_SRAM_OFFSET_6 0x306534
+
+#define mmSIF_RTR_CTRL_0_NL_SRAM_OFFSET_7 0x306538
+
+#define mmSIF_RTR_CTRL_0_NL_SRAM_OFFSET_8 0x30653C
+
+#define mmSIF_RTR_CTRL_0_NL_SRAM_OFFSET_9 0x306540
+
+#define mmSIF_RTR_CTRL_0_NL_HBM_OFFSET_0 0x306550
+
+#define mmSIF_RTR_CTRL_0_NL_HBM_OFFSET_1 0x306554
+
+#define mmSIF_RTR_CTRL_0_NL_HBM_OFFSET_2 0x306558
+
+#define mmSIF_RTR_CTRL_0_NL_HBM_OFFSET_3 0x30655C
+
+#define mmSIF_RTR_CTRL_0_NL_HBM_OFFSET_4 0x306560
+
+#define mmSIF_RTR_CTRL_0_NL_HBM_OFFSET_5 0x306564
+
+#define mmSIF_RTR_CTRL_0_NL_HBM_OFFSET_6 0x306568
+
+#define mmSIF_RTR_CTRL_0_NL_HBM_OFFSET_7 0x30656C
+
+#define mmSIF_RTR_CTRL_0_NL_HBM_OFFSET_8 0x306570
+
+#define mmSIF_RTR_CTRL_0_NL_HBM_OFFSET_9 0x306574
+
+#define mmSIF_RTR_CTRL_0_NL_HBM_OFFSET_10 0x306578
+
+#define mmSIF_RTR_CTRL_0_NL_HBM_OFFSET_11 0x30657C
+
+#define mmSIF_RTR_CTRL_0_NL_HBM_OFFSET_12 0x306580
+
+#define mmSIF_RTR_CTRL_0_NL_HBM_OFFSET_13 0x306584
+
+#define mmSIF_RTR_CTRL_0_NL_HBM_OFFSET_14 0x306588
+
+#define mmSIF_RTR_CTRL_0_NL_HBM_OFFSET_15 0x30658C
+
+#define mmSIF_RTR_CTRL_0_NL_HBM_OFFSET_16 0x306590
+
+#define mmSIF_RTR_CTRL_0_NL_HBM_OFFSET_17 0x306594
+
+#define mmSIF_RTR_CTRL_0_NL_HBM_OFFSET_18 0x306598
+
+#define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AW_0 0x3065E4
+
+#define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AW_1 0x3065E8
+
+#define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AW_2 0x3065EC
+
+#define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AW_3 0x3065F0
+
+#define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AW_4 0x3065F4
+
+#define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AW_5 0x3065F8
+
+#define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AW_6 0x3065FC
+
+#define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AW_7 0x306600
+
+#define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AW_8 0x306604
+
+#define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AW_9 0x306608
+
+#define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AW_10 0x30660C
+
+#define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AW_11 0x306610
+
+#define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AW_12 0x306614
+
+#define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AW_13 0x306618
+
+#define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AW_14 0x30661C
+
+#define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AW_15 0x306620
+
+#define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AW_0 0x306624
+
+#define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AW_1 0x306628
+
+#define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AW_2 0x30662C
+
+#define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AW_3 0x306630
+
+#define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AW_4 0x306634
+
+#define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AW_5 0x306638
+
+#define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AW_6 0x30663C
+
+#define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AW_7 0x306640
+
+#define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AW_8 0x306644
+
+#define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AW_9 0x306648
+
+#define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AW_10 0x30664C
+
+#define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AW_11 0x306650
+
+#define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AW_12 0x306654
+
+#define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AW_13 0x306658
+
+#define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AW_14 0x30665C
+
+#define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AW_15 0x306660
+
+#define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AW_0 0x306664
+
+#define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AW_1 0x306668
+
+#define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AW_2 0x30666C
+
+#define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AW_3 0x306670
+
+#define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AW_4 0x306674
+
+#define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AW_5 0x306678
+
+#define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AW_6 0x30667C
+
+#define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AW_7 0x306680
+
+#define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AW_8 0x306684
+
+#define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AW_9 0x306688
+
+#define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AW_10 0x30668C
+
+#define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AW_11 0x306690
+
+#define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AW_12 0x306694
+
+#define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AW_13 0x306698
+
+#define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AW_14 0x30669C
+
+#define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AW_15 0x3066A0
+
+#define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AW_0 0x3066A4
+
+#define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AW_1 0x3066A8
+
+#define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AW_2 0x3066AC
+
+#define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AW_3 0x3066B0
+
+#define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AW_4 0x3066B4
+
+#define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AW_5 0x3066B8
+
+#define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AW_6 0x3066BC
+
+#define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AW_7 0x3066C0
+
+#define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AW_8 0x3066C4
+
+#define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AW_9 0x3066C8
+
+#define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AW_10 0x3066CC
+
+#define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AW_11 0x3066D0
+
+#define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AW_12 0x3066D4
+
+#define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AW_13 0x3066D8
+
+#define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AW_14 0x3066DC
+
+#define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AW_15 0x3066E0
+
+#define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_LOW_AW_0 0x3066E4
+
+#define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_LOW_AW_1 0x3066E8
+
+#define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_LOW_AW_2 0x3066EC
+
+#define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_LOW_AW_3 0x3066F0
+
+#define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_LOW_AW_4 0x3066F4
+
+#define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_LOW_AW_5 0x3066F8
+
+#define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_LOW_AW_6 0x3066FC
+
+#define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_LOW_AW_7 0x306700
+
+#define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_LOW_AW_8 0x306704
+
+#define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_LOW_AW_9 0x306708
+
+#define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_LOW_AW_10 0x30670C
+
+#define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_LOW_AW_11 0x306710
+
+#define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_LOW_AW_12 0x306714
+
+#define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_LOW_AW_13 0x306718
+
+#define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_LOW_AW_14 0x30671C
+
+#define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_LOW_AW_15 0x306720
+
+#define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_HIGH_AW_0 0x306724
+
+#define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_HIGH_AW_1 0x306728
+
+#define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_HIGH_AW_2 0x30672C
+
+#define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_HIGH_AW_3 0x306730
+
+#define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_HIGH_AW_4 0x306734
+
+#define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_HIGH_AW_5 0x306738
+
+#define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_HIGH_AW_6 0x30673C
+
+#define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_HIGH_AW_7 0x306740
+
+#define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_HIGH_AW_8 0x306744
+
+#define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_HIGH_AW_9 0x306748
+
+#define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_HIGH_AW_10 0x30674C
+
+#define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_HIGH_AW_11 0x306750
+
+#define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_HIGH_AW_12 0x306754
+
+#define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_HIGH_AW_13 0x306758
+
+#define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_HIGH_AW_14 0x30675C
+
+#define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_HIGH_AW_15 0x306760
+
+#define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_LOW_AW_0 0x306764
+
+#define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_LOW_AW_1 0x306768
+
+#define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_LOW_AW_2 0x30676C
+
+#define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_LOW_AW_3 0x306770
+
+#define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_LOW_AW_4 0x306774
+
+#define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_LOW_AW_5 0x306778
+
+#define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_LOW_AW_6 0x30677C
+
+#define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_LOW_AW_7 0x306780
+
+#define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_LOW_AW_8 0x306784
+
+#define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_LOW_AW_9 0x306788
+
+#define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_LOW_AW_10 0x30678C
+
+#define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_LOW_AW_11 0x306790
+
+#define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_LOW_AW_12 0x306794
+
+#define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_LOW_AW_13 0x306798
+
+#define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_LOW_AW_14 0x30679C
+
+#define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_LOW_AW_15 0x3067A0
+
+#define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_HIGH_AW_0 0x3067A4
+
+#define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_HIGH_AW_1 0x3067A8
+
+#define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_HIGH_AW_2 0x3067AC
+
+#define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_HIGH_AW_3 0x3067B0
+
+#define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_HIGH_AW_4 0x3067B4
+
+#define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_HIGH_AW_5 0x3067B8
+
+#define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_HIGH_AW_6 0x3067BC
+
+#define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_HIGH_AW_7 0x3067C0
+
+#define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_HIGH_AW_8 0x3067C4
+
+#define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_HIGH_AW_9 0x3067C8
+
+#define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_HIGH_AW_10 0x3067CC
+
+#define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_HIGH_AW_11 0x3067D0
+
+#define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_HIGH_AW_12 0x3067D4
+
+#define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_HIGH_AW_13 0x3067D8
+
+#define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_HIGH_AW_14 0x3067DC
+
+#define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_HIGH_AW_15 0x3067E0
+
+#define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AR_0 0x306824
+
+#define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AR_1 0x306828
+
+#define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AR_2 0x30682C
+
+#define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AR_3 0x306830
+
+#define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AR_4 0x306834
+
+#define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AR_5 0x306838
+
+#define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AR_6 0x30683C
+
+#define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AR_7 0x306840
+
+#define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AR_8 0x306844
+
+#define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AR_9 0x306848
+
+#define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AR_10 0x30684C
+
+#define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AR_11 0x306850
+
+#define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AR_12 0x306854
+
+#define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AR_13 0x306858
+
+#define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AR_14 0x30685C
+
+#define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AR_15 0x306860
+
+#define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AR_0 0x306864
+
+#define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AR_1 0x306868
+
+#define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AR_2 0x30686C
+
+#define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AR_3 0x306870
+
+#define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AR_4 0x306874
+
+#define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AR_5 0x306878
+
+#define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AR_6 0x30687C
+
+#define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AR_7 0x306880
+
+#define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AR_8 0x306884
+
+#define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AR_9 0x306888
+
+#define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AR_10 0x30688C
+
+#define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AR_11 0x306890
+
+#define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AR_12 0x306894
+
+#define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AR_13 0x306898
+
+#define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AR_14 0x30689C
+
+#define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AR_15 0x3068A0
+
+#define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AR_0 0x3068A4
+
+#define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AR_1 0x3068A8
+
+#define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AR_2 0x3068AC
+
+#define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AR_3 0x3068B0
+
+#define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AR_4 0x3068B4
+
+#define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AR_5 0x3068B8
+
+#define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AR_6 0x3068BC
+
+#define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AR_7 0x3068C0
+
+#define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AR_8 0x3068C4
+
+#define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AR_9 0x3068C8
+
+#define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AR_10 0x3068CC
+
+#define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AR_11 0x3068D0
+
+#define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AR_12 0x3068D4
+
+#define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AR_13 0x3068D8
+
+#define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AR_14 0x3068DC
+
+#define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AR_15 0x3068E0
+
+#define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AR_0 0x3068E4
+
+#define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AR_1 0x3068E8
+
+#define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AR_2 0x3068EC
+
+#define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AR_3 0x3068F0
+
+#define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AR_4 0x3068F4
+
+#define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AR_5 0x3068F8
+
+#define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AR_6 0x3068FC
+
+#define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AR_7 0x306900
+
+#define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AR_8 0x306904
+
+#define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AR_9 0x306908
+
+#define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AR_10 0x30690C
+
+#define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AR_11 0x306910
+
+#define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AR_12 0x306914
+
+#define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AR_13 0x306918
+
+#define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AR_14 0x30691C
+
+#define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AR_15 0x306920
+
+#define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_LOW_AR_0 0x306924
+
+#define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_LOW_AR_1 0x306928
+
+#define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_LOW_AR_2 0x30692C
+
+#define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_LOW_AR_3 0x306930
+
+#define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_LOW_AR_4 0x306934
+
+#define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_LOW_AR_5 0x306938
+
+#define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_LOW_AR_6 0x30693C
+
+#define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_LOW_AR_7 0x306940
+
+#define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_LOW_AR_8 0x306944
+
+#define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_LOW_AR_9 0x306948
+
+#define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_LOW_AR_10 0x30694C
+
+#define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_LOW_AR_11 0x306950
+
+#define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_LOW_AR_12 0x306954
+
+#define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_LOW_AR_13 0x306958
+
+#define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_LOW_AR_14 0x30695C
+
+#define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_LOW_AR_15 0x306960
+
+#define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_HIGH_AR_0 0x306964
+
+#define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_HIGH_AR_1 0x306968
+
+#define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_HIGH_AR_2 0x30696C
+
+#define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_HIGH_AR_3 0x306970
+
+#define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_HIGH_AR_4 0x306974
+
+#define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_HIGH_AR_5 0x306978
+
+#define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_HIGH_AR_6 0x30697C
+
+#define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_HIGH_AR_7 0x306980
+
+#define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_HIGH_AR_8 0x306984
+
+#define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_HIGH_AR_9 0x306988
+
+#define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_HIGH_AR_10 0x30698C
+
+#define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_HIGH_AR_11 0x306990
+
+#define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_HIGH_AR_12 0x306994
+
+#define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_HIGH_AR_13 0x306998
+
+#define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_HIGH_AR_14 0x30699C
+
+#define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_HIGH_AR_15 0x3069A0
+
+#define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_LOW_AR_0 0x3069A4
+
+#define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_LOW_AR_1 0x3069A8
+
+#define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_LOW_AR_2 0x3069AC
+
+#define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_LOW_AR_3 0x3069B0
+
+#define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_LOW_AR_4 0x3069B4
+
+#define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_LOW_AR_5 0x3069B8
+
+#define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_LOW_AR_6 0x3069BC
+
+#define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_LOW_AR_7 0x3069C0
+
+#define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_LOW_AR_8 0x3069C4
+
+#define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_LOW_AR_9 0x3069C8
+
+#define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_LOW_AR_10 0x3069CC
+
+#define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_LOW_AR_11 0x3069D0
+
+#define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_LOW_AR_12 0x3069D4
+
+#define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_LOW_AR_13 0x3069D8
+
+#define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_LOW_AR_14 0x3069DC
+
+#define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_LOW_AR_15 0x3069E0
+
+#define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_HIGH_AR_0 0x3069E4
+
+#define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_HIGH_AR_1 0x3069E8
+
+#define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_HIGH_AR_2 0x3069EC
+
+#define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_HIGH_AR_3 0x3069F0
+
+#define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_HIGH_AR_4 0x3069F4
+
+#define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_HIGH_AR_5 0x3069F8
+
+#define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_HIGH_AR_6 0x3069FC
+
+#define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_HIGH_AR_7 0x306A00
+
+#define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_HIGH_AR_8 0x306A04
+
+#define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_HIGH_AR_9 0x306A08
+
+#define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_HIGH_AR_10 0x306A0C
+
+#define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_HIGH_AR_11 0x306A10
+
+#define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_HIGH_AR_12 0x306A14
+
+#define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_HIGH_AR_13 0x306A18
+
+#define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_HIGH_AR_14 0x306A1C
+
+#define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_HIGH_AR_15 0x306A20
+
+#define mmSIF_RTR_CTRL_0_RANGE_SEC_HIT_AW 0x306A64
+
+#define mmSIF_RTR_CTRL_0_RANGE_SEC_HIT_AR 0x306A68
+
+#define mmSIF_RTR_CTRL_0_RANGE_PRIV_HIT_AW 0x306A6C
+
+#define mmSIF_RTR_CTRL_0_RANGE_PRIV_HIT_AR 0x306A70
+
+#define mmSIF_RTR_CTRL_0_RGL_CFG 0x306B64
+
+#define mmSIF_RTR_CTRL_0_RGL_SHIFT 0x306B68
+
+#define mmSIF_RTR_CTRL_0_RGL_EXPECTED_LAT_0 0x306B6C
+
+#define mmSIF_RTR_CTRL_0_RGL_EXPECTED_LAT_1 0x306B70
+
+#define mmSIF_RTR_CTRL_0_RGL_EXPECTED_LAT_2 0x306B74
+
+#define mmSIF_RTR_CTRL_0_RGL_EXPECTED_LAT_3 0x306B78
+
+#define mmSIF_RTR_CTRL_0_RGL_EXPECTED_LAT_4 0x306B7C
+
+#define mmSIF_RTR_CTRL_0_RGL_EXPECTED_LAT_5 0x306B80
+
+#define mmSIF_RTR_CTRL_0_RGL_EXPECTED_LAT_6 0x306B84
+
+#define mmSIF_RTR_CTRL_0_RGL_EXPECTED_LAT_7 0x306B88
+
+#define mmSIF_RTR_CTRL_0_RGL_TOKEN_0 0x306BAC
+
+#define mmSIF_RTR_CTRL_0_RGL_TOKEN_1 0x306BB0
+
+#define mmSIF_RTR_CTRL_0_RGL_TOKEN_2 0x306BB4
+
+#define mmSIF_RTR_CTRL_0_RGL_TOKEN_3 0x306BB8
+
+#define mmSIF_RTR_CTRL_0_RGL_TOKEN_4 0x306BBC
+
+#define mmSIF_RTR_CTRL_0_RGL_TOKEN_5 0x306BC0
+
+#define mmSIF_RTR_CTRL_0_RGL_TOKEN_6 0x306BC4
+
+#define mmSIF_RTR_CTRL_0_RGL_TOKEN_7 0x306BC8
+
+#define mmSIF_RTR_CTRL_0_RGL_BANK_ID_0 0x306BEC
+
+#define mmSIF_RTR_CTRL_0_RGL_BANK_ID_1 0x306BF0
+
+#define mmSIF_RTR_CTRL_0_RGL_BANK_ID_2 0x306BF4
+
+#define mmSIF_RTR_CTRL_0_RGL_BANK_ID_3 0x306BF8
+
+#define mmSIF_RTR_CTRL_0_RGL_BANK_ID_4 0x306BFC
+
+#define mmSIF_RTR_CTRL_0_RGL_BANK_ID_5 0x306C00
+
+#define mmSIF_RTR_CTRL_0_RGL_BANK_ID_6 0x306C04
+
+#define mmSIF_RTR_CTRL_0_RGL_BANK_ID_7 0x306C08
+
+#define mmSIF_RTR_CTRL_0_RGL_WDT 0x306C2C
+
+#define mmSIF_RTR_CTRL_0_E2E_AR_HBM0_CH0_CTR_WRAP 0x306C30
+
+#define mmSIF_RTR_CTRL_0_E2E_AR_HBM0_CH1_CTR_WRAP 0x306C34
+
+#define mmSIF_RTR_CTRL_0_E2E_AR_HBM1_CH0_CTR_WRAP 0x306C38
+
+#define mmSIF_RTR_CTRL_0_E2E_AR_HBM1_CH1_CTR_WRAP 0x306C3C
+
+#define mmSIF_RTR_CTRL_0_E2E_AR_HBM2_CH0_CTR_WRAP 0x306C40
+
+#define mmSIF_RTR_CTRL_0_E2E_AR_HBM2_CH1_CTR_WRAP 0x306C44
+
+#define mmSIF_RTR_CTRL_0_E2E_AR_HBM3_CH0_CTR_WRAP 0x306C48
+
+#define mmSIF_RTR_CTRL_0_E2E_AR_HBM3_CH1_CTR_WRAP 0x306C4C
+
+#define mmSIF_RTR_CTRL_0_E2E_AR_HBM0_CH0_CTR_CNT 0x306C50
+
+#define mmSIF_RTR_CTRL_0_E2E_AR_HBM0_CH1_CTR_CNT 0x306C54
+
+#define mmSIF_RTR_CTRL_0_E2E_AR_HBM1_CH0_CTR_CNT 0x306C58
+
+#define mmSIF_RTR_CTRL_0_E2E_AR_HBM1_CH1_CTR_CNT 0x306C5C
+
+#define mmSIF_RTR_CTRL_0_E2E_AR_HBM2_CH0_CTR_CNT 0x306C60
+
+#define mmSIF_RTR_CTRL_0_E2E_AR_HBM2_CH1_CTR_CNT 0x306C64
+
+#define mmSIF_RTR_CTRL_0_E2E_AR_HBM3_CH0_CTR_CNT 0x306C68
+
+#define mmSIF_RTR_CTRL_0_E2E_AR_HBM3_CH1_CTR_CNT 0x306C6C
+
+#define mmSIF_RTR_CTRL_0_E2E_AW_HBM0_CH0_CTR_WRAP 0x306C70
+
+#define mmSIF_RTR_CTRL_0_E2E_AW_HBM0_CH1_CTR_WRAP 0x306C74
+
+#define mmSIF_RTR_CTRL_0_E2E_AW_HBM1_CH0_CTR_WRAP 0x306C78
+
+#define mmSIF_RTR_CTRL_0_E2E_AW_HBM1_CH1_CTR_WRAP 0x306C7C
+
+#define mmSIF_RTR_CTRL_0_E2E_AW_HBM2_CH0_CTR_WRAP 0x306C80
+
+#define mmSIF_RTR_CTRL_0_E2E_AW_HBM2_CH1_CTR_WRAP 0x306C84
+
+#define mmSIF_RTR_CTRL_0_E2E_AW_HBM3_CH0_CTR_WRAP 0x306C88
+
+#define mmSIF_RTR_CTRL_0_E2E_AW_HBM3_CH1_CTR_WRAP 0x306C8C
+
+#define mmSIF_RTR_CTRL_0_E2E_AW_HBM0_CH0_CTR_CNT 0x306C90
+
+#define mmSIF_RTR_CTRL_0_E2E_AW_HBM0_CH1_CTR_CNT 0x306C94
+
+#define mmSIF_RTR_CTRL_0_E2E_AW_HBM1_CH0_CTR_CNT 0x306C98
+
+#define mmSIF_RTR_CTRL_0_E2E_AW_HBM1_CH1_CTR_CNT 0x306C9C
+
+#define mmSIF_RTR_CTRL_0_E2E_AW_HBM2_CH0_CTR_CNT 0x306CA0
+
+#define mmSIF_RTR_CTRL_0_E2E_AW_HBM2_CH1_CTR_CNT 0x306CA4
+
+#define mmSIF_RTR_CTRL_0_E2E_AW_HBM3_CH0_CTR_CNT 0x306CA8
+
+#define mmSIF_RTR_CTRL_0_E2E_AW_HBM3_CH1_CTR_CNT 0x306CAC
+
+#define mmSIF_RTR_CTRL_0_NL_HBM_PC_SEL_0 0x306CB0
+
+#define mmSIF_RTR_CTRL_0_NL_HBM_PC_SEL_1 0x306CB4
+
+#define mmSIF_RTR_CTRL_0_NL_HBM_PC_SEL_2 0x306CB8
+
+#define mmSIF_RTR_CTRL_0_NL_HBM_PC_SEL_3 0x306CBC
+
+#endif /* ASIC_REG_SIF_RTR_CTRL_0_REGS_H_ */
diff --git a/drivers/accel/habanalabs/include/gaudi/asic_reg/sif_rtr_ctrl_1_regs.h b/drivers/accel/habanalabs/include/gaudi/asic_reg/sif_rtr_ctrl_1_regs.h
new file mode 100644
index 0000000000..c6d517dbbd
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi/asic_reg/sif_rtr_ctrl_1_regs.h
@@ -0,0 +1,896 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2016-2018 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ ** DO NOT EDIT BELOW **
+ ************************************/
+
+#ifndef ASIC_REG_SIF_RTR_CTRL_1_REGS_H_
+#define ASIC_REG_SIF_RTR_CTRL_1_REGS_H_
+
+/*
+ *****************************************
+ * SIF_RTR_CTRL_1 (Prototype: RTR_CTRL)
+ *****************************************
+ */
+
+#define mmSIF_RTR_CTRL_1_PERM_SEL 0x316108
+
+#define mmSIF_RTR_CTRL_1_HBM_POLY_H3_0 0x316114
+
+#define mmSIF_RTR_CTRL_1_HBM_POLY_H3_1 0x316118
+
+#define mmSIF_RTR_CTRL_1_HBM_POLY_H3_2 0x31611C
+
+#define mmSIF_RTR_CTRL_1_HBM_POLY_H3_3 0x316120
+
+#define mmSIF_RTR_CTRL_1_HBM_POLY_H3_4 0x316124
+
+#define mmSIF_RTR_CTRL_1_HBM_POLY_H3_5 0x316128
+
+#define mmSIF_RTR_CTRL_1_HBM_POLY_H3_6 0x31612C
+
+#define mmSIF_RTR_CTRL_1_HBM_POLY_H3_7 0x316130
+
+#define mmSIF_RTR_CTRL_1_HBM_POLY_H3_8 0x316134
+
+#define mmSIF_RTR_CTRL_1_HBM_POLY_H3_9 0x316138
+
+#define mmSIF_RTR_CTRL_1_HBM_POLY_H3_10 0x31613C
+
+#define mmSIF_RTR_CTRL_1_HBM_POLY_H3_11 0x316140
+
+#define mmSIF_RTR_CTRL_1_HBM_POLY_H3_12 0x316144
+
+#define mmSIF_RTR_CTRL_1_HBM_POLY_H3_13 0x316148
+
+#define mmSIF_RTR_CTRL_1_HBM_POLY_H3_14 0x31614C
+
+#define mmSIF_RTR_CTRL_1_HBM_POLY_H3_15 0x316150
+
+#define mmSIF_RTR_CTRL_1_HBM_POLY_H3_16 0x316154
+
+#define mmSIF_RTR_CTRL_1_HBM_POLY_H3_17 0x316158
+
+#define mmSIF_RTR_CTRL_1_HBM_POLY_H3_18 0x31615C
+
+#define mmSIF_RTR_CTRL_1_HBM_POLY_H3_19 0x316160
+
+#define mmSIF_RTR_CTRL_1_HBM_POLY_H3_20 0x316164
+
+#define mmSIF_RTR_CTRL_1_HBM_POLY_H3_21 0x316168
+
+#define mmSIF_RTR_CTRL_1_HBM_POLY_H3_22 0x31616C
+
+#define mmSIF_RTR_CTRL_1_HBM_POLY_H3_23 0x316170
+
+#define mmSIF_RTR_CTRL_1_HBM_POLY_H3_24 0x316174
+
+#define mmSIF_RTR_CTRL_1_HBM_POLY_H3_25 0x316178
+
+#define mmSIF_RTR_CTRL_1_HBM_POLY_H3_26 0x31617C
+
+#define mmSIF_RTR_CTRL_1_HBM_POLY_H3_27 0x316180
+
+#define mmSIF_RTR_CTRL_1_SRAM_POLY_H3_0 0x316184
+
+#define mmSIF_RTR_CTRL_1_SRAM_POLY_H3_1 0x316188
+
+#define mmSIF_RTR_CTRL_1_SRAM_POLY_H3_2 0x31618C
+
+#define mmSIF_RTR_CTRL_1_SRAM_POLY_H3_3 0x316190
+
+#define mmSIF_RTR_CTRL_1_SRAM_POLY_H3_4 0x316194
+
+#define mmSIF_RTR_CTRL_1_SRAM_POLY_H3_5 0x316198
+
+#define mmSIF_RTR_CTRL_1_SRAM_POLY_H3_6 0x31619C
+
+#define mmSIF_RTR_CTRL_1_SRAM_POLY_H3_7 0x3161A0
+
+#define mmSIF_RTR_CTRL_1_SRAM_POLY_H3_8 0x3161A4
+
+#define mmSIF_RTR_CTRL_1_SRAM_POLY_H3_9 0x3161A8
+
+#define mmSIF_RTR_CTRL_1_SRAM_POLY_H3_10 0x3161AC
+
+#define mmSIF_RTR_CTRL_1_SRAM_POLY_H3_11 0x3161B0
+
+#define mmSIF_RTR_CTRL_1_SRAM_POLY_H3_12 0x3161B4
+
+#define mmSIF_RTR_CTRL_1_SRAM_POLY_H3_13 0x3161B8
+
+#define mmSIF_RTR_CTRL_1_SRAM_POLY_H3_14 0x3161BC
+
+#define mmSIF_RTR_CTRL_1_SCRAM_SRAM_EN 0x31626C
+
+#define mmSIF_RTR_CTRL_1_RL_HBM_EN 0x316274
+
+#define mmSIF_RTR_CTRL_1_RL_HBM_SAT 0x316278
+
+#define mmSIF_RTR_CTRL_1_RL_HBM_RST 0x31627C
+
+#define mmSIF_RTR_CTRL_1_RL_HBM_TIMEOUT 0x316280
+
+#define mmSIF_RTR_CTRL_1_SCRAM_HBM_EN 0x316284
+
+#define mmSIF_RTR_CTRL_1_RL_PCI_EN 0x316288
+
+#define mmSIF_RTR_CTRL_1_RL_PCI_SAT 0x31628C
+
+#define mmSIF_RTR_CTRL_1_RL_PCI_RST 0x316290
+
+#define mmSIF_RTR_CTRL_1_RL_PCI_TIMEOUT 0x316294
+
+#define mmSIF_RTR_CTRL_1_RL_SRAM_EN 0x31629C
+
+#define mmSIF_RTR_CTRL_1_RL_SRAM_SAT 0x3162A0
+
+#define mmSIF_RTR_CTRL_1_RL_SRAM_RST 0x3162A4
+
+#define mmSIF_RTR_CTRL_1_RL_SRAM_TIMEOUT 0x3162AC
+
+#define mmSIF_RTR_CTRL_1_RL_SRAM_RED 0x3162B4
+
+#define mmSIF_RTR_CTRL_1_E2E_HBM_EN 0x3162EC
+
+#define mmSIF_RTR_CTRL_1_E2E_PCI_EN 0x3162F0
+
+#define mmSIF_RTR_CTRL_1_E2E_HBM_WR_SIZE 0x3162F4
+
+#define mmSIF_RTR_CTRL_1_E2E_PCI_WR_SIZE 0x3162F8
+
+#define mmSIF_RTR_CTRL_1_E2E_AW_PCI_CTR_SET_EN 0x316404
+
+#define mmSIF_RTR_CTRL_1_E2E_AW_PCI_CTR_SET 0x316408
+
+#define mmSIF_RTR_CTRL_1_E2E_AW_PCI_CTR_WRAP 0x31640C
+
+#define mmSIF_RTR_CTRL_1_E2E_AW_PCI_CTR_CNT 0x316410
+
+#define mmSIF_RTR_CTRL_1_E2E_AW_HBM_CTR_SET_EN 0x316414
+
+#define mmSIF_RTR_CTRL_1_E2E_AW_HBM_CTR_SET 0x316418
+
+#define mmSIF_RTR_CTRL_1_E2E_HBM_RD_SIZE 0x31641C
+
+#define mmSIF_RTR_CTRL_1_E2E_PCI_RD_SIZE 0x316420
+
+#define mmSIF_RTR_CTRL_1_E2E_AR_PCI_CTR_SET_EN 0x316424
+
+#define mmSIF_RTR_CTRL_1_E2E_AR_PCI_CTR_SET 0x316428
+
+#define mmSIF_RTR_CTRL_1_E2E_AR_PCI_CTR_WRAP 0x31642C
+
+#define mmSIF_RTR_CTRL_1_E2E_AR_PCI_CTR_CNT 0x316430
+
+#define mmSIF_RTR_CTRL_1_E2E_AR_HBM_CTR_SET_EN 0x316434
+
+#define mmSIF_RTR_CTRL_1_E2E_AR_HBM_CTR_SET 0x316438
+
+#define mmSIF_RTR_CTRL_1_NL_HBM_SEL_0 0x316450
+
+#define mmSIF_RTR_CTRL_1_NL_HBM_SEL_1 0x316454
+
+#define mmSIF_RTR_CTRL_1_NON_LIN_EN 0x316480
+
+#define mmSIF_RTR_CTRL_1_NL_SRAM_BANK_0 0x316500
+
+#define mmSIF_RTR_CTRL_1_NL_SRAM_BANK_1 0x316504
+
+#define mmSIF_RTR_CTRL_1_NL_SRAM_BANK_2 0x316508
+
+#define mmSIF_RTR_CTRL_1_NL_SRAM_BANK_3 0x31650C
+
+#define mmSIF_RTR_CTRL_1_NL_SRAM_BANK_4 0x316510
+
+#define mmSIF_RTR_CTRL_1_NL_SRAM_OFFSET_0 0x316514
+
+#define mmSIF_RTR_CTRL_1_NL_SRAM_OFFSET_1 0x316520
+
+#define mmSIF_RTR_CTRL_1_NL_SRAM_OFFSET_2 0x316524
+
+#define mmSIF_RTR_CTRL_1_NL_SRAM_OFFSET_3 0x316528
+
+#define mmSIF_RTR_CTRL_1_NL_SRAM_OFFSET_4 0x31652C
+
+#define mmSIF_RTR_CTRL_1_NL_SRAM_OFFSET_5 0x316530
+
+#define mmSIF_RTR_CTRL_1_NL_SRAM_OFFSET_6 0x316534
+
+#define mmSIF_RTR_CTRL_1_NL_SRAM_OFFSET_7 0x316538
+
+#define mmSIF_RTR_CTRL_1_NL_SRAM_OFFSET_8 0x31653C
+
+#define mmSIF_RTR_CTRL_1_NL_SRAM_OFFSET_9 0x316540
+
+#define mmSIF_RTR_CTRL_1_NL_HBM_OFFSET_0 0x316550
+
+#define mmSIF_RTR_CTRL_1_NL_HBM_OFFSET_1 0x316554
+
+#define mmSIF_RTR_CTRL_1_NL_HBM_OFFSET_2 0x316558
+
+#define mmSIF_RTR_CTRL_1_NL_HBM_OFFSET_3 0x31655C
+
+#define mmSIF_RTR_CTRL_1_NL_HBM_OFFSET_4 0x316560
+
+#define mmSIF_RTR_CTRL_1_NL_HBM_OFFSET_5 0x316564
+
+#define mmSIF_RTR_CTRL_1_NL_HBM_OFFSET_6 0x316568
+
+#define mmSIF_RTR_CTRL_1_NL_HBM_OFFSET_7 0x31656C
+
+#define mmSIF_RTR_CTRL_1_NL_HBM_OFFSET_8 0x316570
+
+#define mmSIF_RTR_CTRL_1_NL_HBM_OFFSET_9 0x316574
+
+#define mmSIF_RTR_CTRL_1_NL_HBM_OFFSET_10 0x316578
+
+#define mmSIF_RTR_CTRL_1_NL_HBM_OFFSET_11 0x31657C
+
+#define mmSIF_RTR_CTRL_1_NL_HBM_OFFSET_12 0x316580
+
+#define mmSIF_RTR_CTRL_1_NL_HBM_OFFSET_13 0x316584
+
+#define mmSIF_RTR_CTRL_1_NL_HBM_OFFSET_14 0x316588
+
+#define mmSIF_RTR_CTRL_1_NL_HBM_OFFSET_15 0x31658C
+
+#define mmSIF_RTR_CTRL_1_NL_HBM_OFFSET_16 0x316590
+
+#define mmSIF_RTR_CTRL_1_NL_HBM_OFFSET_17 0x316594
+
+#define mmSIF_RTR_CTRL_1_NL_HBM_OFFSET_18 0x316598
+
+#define mmSIF_RTR_CTRL_1_RANGE_SEC_BASE_LOW_AW_0 0x3165E4
+
+#define mmSIF_RTR_CTRL_1_RANGE_SEC_BASE_LOW_AW_1 0x3165E8
+
+#define mmSIF_RTR_CTRL_1_RANGE_SEC_BASE_LOW_AW_2 0x3165EC
+
+#define mmSIF_RTR_CTRL_1_RANGE_SEC_BASE_LOW_AW_3 0x3165F0
+
+#define mmSIF_RTR_CTRL_1_RANGE_SEC_BASE_LOW_AW_4 0x3165F4
+
+#define mmSIF_RTR_CTRL_1_RANGE_SEC_BASE_LOW_AW_5 0x3165F8
+
+#define mmSIF_RTR_CTRL_1_RANGE_SEC_BASE_LOW_AW_6 0x3165FC
+
+#define mmSIF_RTR_CTRL_1_RANGE_SEC_BASE_LOW_AW_7 0x316600
+
+#define mmSIF_RTR_CTRL_1_RANGE_SEC_BASE_LOW_AW_8 0x316604
+
+#define mmSIF_RTR_CTRL_1_RANGE_SEC_BASE_LOW_AW_9 0x316608
+
+#define mmSIF_RTR_CTRL_1_RANGE_SEC_BASE_LOW_AW_10 0x31660C
+
+#define mmSIF_RTR_CTRL_1_RANGE_SEC_BASE_LOW_AW_11 0x316610
+
+#define mmSIF_RTR_CTRL_1_RANGE_SEC_BASE_LOW_AW_12 0x316614
+
+#define mmSIF_RTR_CTRL_1_RANGE_SEC_BASE_LOW_AW_13 0x316618
+
+#define mmSIF_RTR_CTRL_1_RANGE_SEC_BASE_LOW_AW_14 0x31661C
+
+#define mmSIF_RTR_CTRL_1_RANGE_SEC_BASE_LOW_AW_15 0x316620
+
+#define mmSIF_RTR_CTRL_1_RANGE_SEC_BASE_HIGH_AW_0 0x316624
+
+#define mmSIF_RTR_CTRL_1_RANGE_SEC_BASE_HIGH_AW_1 0x316628
+
+#define mmSIF_RTR_CTRL_1_RANGE_SEC_BASE_HIGH_AW_2 0x31662C
+
+#define mmSIF_RTR_CTRL_1_RANGE_SEC_BASE_HIGH_AW_3 0x316630
+
+#define mmSIF_RTR_CTRL_1_RANGE_SEC_BASE_HIGH_AW_4 0x316634
+
+#define mmSIF_RTR_CTRL_1_RANGE_SEC_BASE_HIGH_AW_5 0x316638
+
+#define mmSIF_RTR_CTRL_1_RANGE_SEC_BASE_HIGH_AW_6 0x31663C
+
+#define mmSIF_RTR_CTRL_1_RANGE_SEC_BASE_HIGH_AW_7 0x316640
+
+#define mmSIF_RTR_CTRL_1_RANGE_SEC_BASE_HIGH_AW_8 0x316644
+
+#define mmSIF_RTR_CTRL_1_RANGE_SEC_BASE_HIGH_AW_9 0x316648
+
+#define mmSIF_RTR_CTRL_1_RANGE_SEC_BASE_HIGH_AW_10 0x31664C
+
+#define mmSIF_RTR_CTRL_1_RANGE_SEC_BASE_HIGH_AW_11 0x316650
+
+#define mmSIF_RTR_CTRL_1_RANGE_SEC_BASE_HIGH_AW_12 0x316654
+
+#define mmSIF_RTR_CTRL_1_RANGE_SEC_BASE_HIGH_AW_13 0x316658
+
+#define mmSIF_RTR_CTRL_1_RANGE_SEC_BASE_HIGH_AW_14 0x31665C
+
+#define mmSIF_RTR_CTRL_1_RANGE_SEC_BASE_HIGH_AW_15 0x316660
+
+#define mmSIF_RTR_CTRL_1_RANGE_SEC_MASK_LOW_AW_0 0x316664
+
+#define mmSIF_RTR_CTRL_1_RANGE_SEC_MASK_LOW_AW_1 0x316668
+
+#define mmSIF_RTR_CTRL_1_RANGE_SEC_MASK_LOW_AW_2 0x31666C
+
+#define mmSIF_RTR_CTRL_1_RANGE_SEC_MASK_LOW_AW_3 0x316670
+
+#define mmSIF_RTR_CTRL_1_RANGE_SEC_MASK_LOW_AW_4 0x316674
+
+#define mmSIF_RTR_CTRL_1_RANGE_SEC_MASK_LOW_AW_5 0x316678
+
+#define mmSIF_RTR_CTRL_1_RANGE_SEC_MASK_LOW_AW_6 0x31667C
+
+#define mmSIF_RTR_CTRL_1_RANGE_SEC_MASK_LOW_AW_7 0x316680
+
+#define mmSIF_RTR_CTRL_1_RANGE_SEC_MASK_LOW_AW_8 0x316684
+
+#define mmSIF_RTR_CTRL_1_RANGE_SEC_MASK_LOW_AW_9 0x316688
+
+#define mmSIF_RTR_CTRL_1_RANGE_SEC_MASK_LOW_AW_10 0x31668C
+
+#define mmSIF_RTR_CTRL_1_RANGE_SEC_MASK_LOW_AW_11 0x316690
+
+#define mmSIF_RTR_CTRL_1_RANGE_SEC_MASK_LOW_AW_12 0x316694
+
+#define mmSIF_RTR_CTRL_1_RANGE_SEC_MASK_LOW_AW_13 0x316698
+
+#define mmSIF_RTR_CTRL_1_RANGE_SEC_MASK_LOW_AW_14 0x31669C
+
+#define mmSIF_RTR_CTRL_1_RANGE_SEC_MASK_LOW_AW_15 0x3166A0
+
+#define mmSIF_RTR_CTRL_1_RANGE_SEC_MASK_HIGH_AW_0 0x3166A4
+
+#define mmSIF_RTR_CTRL_1_RANGE_SEC_MASK_HIGH_AW_1 0x3166A8
+
+#define mmSIF_RTR_CTRL_1_RANGE_SEC_MASK_HIGH_AW_2 0x3166AC
+
+#define mmSIF_RTR_CTRL_1_RANGE_SEC_MASK_HIGH_AW_3 0x3166B0
+
+#define mmSIF_RTR_CTRL_1_RANGE_SEC_MASK_HIGH_AW_4 0x3166B4
+
+#define mmSIF_RTR_CTRL_1_RANGE_SEC_MASK_HIGH_AW_5 0x3166B8
+
+#define mmSIF_RTR_CTRL_1_RANGE_SEC_MASK_HIGH_AW_6 0x3166BC
+
+#define mmSIF_RTR_CTRL_1_RANGE_SEC_MASK_HIGH_AW_7 0x3166C0
+
+#define mmSIF_RTR_CTRL_1_RANGE_SEC_MASK_HIGH_AW_8 0x3166C4
+
+#define mmSIF_RTR_CTRL_1_RANGE_SEC_MASK_HIGH_AW_9 0x3166C8
+
+#define mmSIF_RTR_CTRL_1_RANGE_SEC_MASK_HIGH_AW_10 0x3166CC
+
+#define mmSIF_RTR_CTRL_1_RANGE_SEC_MASK_HIGH_AW_11 0x3166D0
+
+#define mmSIF_RTR_CTRL_1_RANGE_SEC_MASK_HIGH_AW_12 0x3166D4
+
+#define mmSIF_RTR_CTRL_1_RANGE_SEC_MASK_HIGH_AW_13 0x3166D8
+
+#define mmSIF_RTR_CTRL_1_RANGE_SEC_MASK_HIGH_AW_14 0x3166DC
+
+#define mmSIF_RTR_CTRL_1_RANGE_SEC_MASK_HIGH_AW_15 0x3166E0
+
+#define mmSIF_RTR_CTRL_1_RANGE_PRIV_BASE_LOW_AW_0 0x3166E4
+
+#define mmSIF_RTR_CTRL_1_RANGE_PRIV_BASE_LOW_AW_1 0x3166E8
+
+#define mmSIF_RTR_CTRL_1_RANGE_PRIV_BASE_LOW_AW_2 0x3166EC
+
+#define mmSIF_RTR_CTRL_1_RANGE_PRIV_BASE_LOW_AW_3 0x3166F0
+
+#define mmSIF_RTR_CTRL_1_RANGE_PRIV_BASE_LOW_AW_4 0x3166F4
+
+#define mmSIF_RTR_CTRL_1_RANGE_PRIV_BASE_LOW_AW_5 0x3166F8
+
+#define mmSIF_RTR_CTRL_1_RANGE_PRIV_BASE_LOW_AW_6 0x3166FC
+
+#define mmSIF_RTR_CTRL_1_RANGE_PRIV_BASE_LOW_AW_7 0x316700
+
+#define mmSIF_RTR_CTRL_1_RANGE_PRIV_BASE_LOW_AW_8 0x316704
+
+#define mmSIF_RTR_CTRL_1_RANGE_PRIV_BASE_LOW_AW_9 0x316708
+
+#define mmSIF_RTR_CTRL_1_RANGE_PRIV_BASE_LOW_AW_10 0x31670C
+
+#define mmSIF_RTR_CTRL_1_RANGE_PRIV_BASE_LOW_AW_11 0x316710
+
+#define mmSIF_RTR_CTRL_1_RANGE_PRIV_BASE_LOW_AW_12 0x316714
+
+#define mmSIF_RTR_CTRL_1_RANGE_PRIV_BASE_LOW_AW_13 0x316718
+
+#define mmSIF_RTR_CTRL_1_RANGE_PRIV_BASE_LOW_AW_14 0x31671C
+
+#define mmSIF_RTR_CTRL_1_RANGE_PRIV_BASE_LOW_AW_15 0x316720
+
+#define mmSIF_RTR_CTRL_1_RANGE_PRIV_BASE_HIGH_AW_0 0x316724
+
+#define mmSIF_RTR_CTRL_1_RANGE_PRIV_BASE_HIGH_AW_1 0x316728
+
+#define mmSIF_RTR_CTRL_1_RANGE_PRIV_BASE_HIGH_AW_2 0x31672C
+
+#define mmSIF_RTR_CTRL_1_RANGE_PRIV_BASE_HIGH_AW_3 0x316730
+
+#define mmSIF_RTR_CTRL_1_RANGE_PRIV_BASE_HIGH_AW_4 0x316734
+
+#define mmSIF_RTR_CTRL_1_RANGE_PRIV_BASE_HIGH_AW_5 0x316738
+
+#define mmSIF_RTR_CTRL_1_RANGE_PRIV_BASE_HIGH_AW_6 0x31673C
+
+#define mmSIF_RTR_CTRL_1_RANGE_PRIV_BASE_HIGH_AW_7 0x316740
+
+#define mmSIF_RTR_CTRL_1_RANGE_PRIV_BASE_HIGH_AW_8 0x316744
+
+#define mmSIF_RTR_CTRL_1_RANGE_PRIV_BASE_HIGH_AW_9 0x316748
+
+#define mmSIF_RTR_CTRL_1_RANGE_PRIV_BASE_HIGH_AW_10 0x31674C
+
+#define mmSIF_RTR_CTRL_1_RANGE_PRIV_BASE_HIGH_AW_11 0x316750
+
+#define mmSIF_RTR_CTRL_1_RANGE_PRIV_BASE_HIGH_AW_12 0x316754
+
+#define mmSIF_RTR_CTRL_1_RANGE_PRIV_BASE_HIGH_AW_13 0x316758
+
+#define mmSIF_RTR_CTRL_1_RANGE_PRIV_BASE_HIGH_AW_14 0x31675C
+
+#define mmSIF_RTR_CTRL_1_RANGE_PRIV_BASE_HIGH_AW_15 0x316760
+
+#define mmSIF_RTR_CTRL_1_RANGE_PRIV_MASK_LOW_AW_0 0x316764
+
+#define mmSIF_RTR_CTRL_1_RANGE_PRIV_MASK_LOW_AW_1 0x316768
+
+#define mmSIF_RTR_CTRL_1_RANGE_PRIV_MASK_LOW_AW_2 0x31676C
+
+#define mmSIF_RTR_CTRL_1_RANGE_PRIV_MASK_LOW_AW_3 0x316770
+
+#define mmSIF_RTR_CTRL_1_RANGE_PRIV_MASK_LOW_AW_4 0x316774
+
+#define mmSIF_RTR_CTRL_1_RANGE_PRIV_MASK_LOW_AW_5 0x316778
+
+#define mmSIF_RTR_CTRL_1_RANGE_PRIV_MASK_LOW_AW_6 0x31677C
+
+#define mmSIF_RTR_CTRL_1_RANGE_PRIV_MASK_LOW_AW_7 0x316780
+
+#define mmSIF_RTR_CTRL_1_RANGE_PRIV_MASK_LOW_AW_8 0x316784
+
+#define mmSIF_RTR_CTRL_1_RANGE_PRIV_MASK_LOW_AW_9 0x316788
+
+#define mmSIF_RTR_CTRL_1_RANGE_PRIV_MASK_LOW_AW_10 0x31678C
+
+#define mmSIF_RTR_CTRL_1_RANGE_PRIV_MASK_LOW_AW_11 0x316790
+
+#define mmSIF_RTR_CTRL_1_RANGE_PRIV_MASK_LOW_AW_12 0x316794
+
+#define mmSIF_RTR_CTRL_1_RANGE_PRIV_MASK_LOW_AW_13 0x316798
+
+#define mmSIF_RTR_CTRL_1_RANGE_PRIV_MASK_LOW_AW_14 0x31679C
+
+#define mmSIF_RTR_CTRL_1_RANGE_PRIV_MASK_LOW_AW_15 0x3167A0
+
+#define mmSIF_RTR_CTRL_1_RANGE_PRIV_MASK_HIGH_AW_0 0x3167A4
+
+#define mmSIF_RTR_CTRL_1_RANGE_PRIV_MASK_HIGH_AW_1 0x3167A8
+
+#define mmSIF_RTR_CTRL_1_RANGE_PRIV_MASK_HIGH_AW_2 0x3167AC
+
+#define mmSIF_RTR_CTRL_1_RANGE_PRIV_MASK_HIGH_AW_3 0x3167B0
+
+#define mmSIF_RTR_CTRL_1_RANGE_PRIV_MASK_HIGH_AW_4 0x3167B4
+
+#define mmSIF_RTR_CTRL_1_RANGE_PRIV_MASK_HIGH_AW_5 0x3167B8
+
+#define mmSIF_RTR_CTRL_1_RANGE_PRIV_MASK_HIGH_AW_6 0x3167BC
+
+#define mmSIF_RTR_CTRL_1_RANGE_PRIV_MASK_HIGH_AW_7 0x3167C0
+
+#define mmSIF_RTR_CTRL_1_RANGE_PRIV_MASK_HIGH_AW_8 0x3167C4
+
+#define mmSIF_RTR_CTRL_1_RANGE_PRIV_MASK_HIGH_AW_9 0x3167C8
+
+#define mmSIF_RTR_CTRL_1_RANGE_PRIV_MASK_HIGH_AW_10 0x3167CC
+
+#define mmSIF_RTR_CTRL_1_RANGE_PRIV_MASK_HIGH_AW_11 0x3167D0
+
+#define mmSIF_RTR_CTRL_1_RANGE_PRIV_MASK_HIGH_AW_12 0x3167D4
+
+#define mmSIF_RTR_CTRL_1_RANGE_PRIV_MASK_HIGH_AW_13 0x3167D8
+
+#define mmSIF_RTR_CTRL_1_RANGE_PRIV_MASK_HIGH_AW_14 0x3167DC
+
+#define mmSIF_RTR_CTRL_1_RANGE_PRIV_MASK_HIGH_AW_15 0x3167E0
+
+#define mmSIF_RTR_CTRL_1_RANGE_SEC_BASE_LOW_AR_0 0x316824
+
+#define mmSIF_RTR_CTRL_1_RANGE_SEC_BASE_LOW_AR_1 0x316828
+
+#define mmSIF_RTR_CTRL_1_RANGE_SEC_BASE_LOW_AR_2 0x31682C
+
+#define mmSIF_RTR_CTRL_1_RANGE_SEC_BASE_LOW_AR_3 0x316830
+
+#define mmSIF_RTR_CTRL_1_RANGE_SEC_BASE_LOW_AR_4 0x316834
+
+#define mmSIF_RTR_CTRL_1_RANGE_SEC_BASE_LOW_AR_5 0x316838
+
+#define mmSIF_RTR_CTRL_1_RANGE_SEC_BASE_LOW_AR_6 0x31683C
+
+#define mmSIF_RTR_CTRL_1_RANGE_SEC_BASE_LOW_AR_7 0x316840
+
+#define mmSIF_RTR_CTRL_1_RANGE_SEC_BASE_LOW_AR_8 0x316844
+
+#define mmSIF_RTR_CTRL_1_RANGE_SEC_BASE_LOW_AR_9 0x316848
+
+#define mmSIF_RTR_CTRL_1_RANGE_SEC_BASE_LOW_AR_10 0x31684C
+
+#define mmSIF_RTR_CTRL_1_RANGE_SEC_BASE_LOW_AR_11 0x316850
+
+#define mmSIF_RTR_CTRL_1_RANGE_SEC_BASE_LOW_AR_12 0x316854
+
+#define mmSIF_RTR_CTRL_1_RANGE_SEC_BASE_LOW_AR_13 0x316858
+
+#define mmSIF_RTR_CTRL_1_RANGE_SEC_BASE_LOW_AR_14 0x31685C
+
+#define mmSIF_RTR_CTRL_1_RANGE_SEC_BASE_LOW_AR_15 0x316860
+
+#define mmSIF_RTR_CTRL_1_RANGE_SEC_BASE_HIGH_AR_0 0x316864
+
+#define mmSIF_RTR_CTRL_1_RANGE_SEC_BASE_HIGH_AR_1 0x316868
+
+#define mmSIF_RTR_CTRL_1_RANGE_SEC_BASE_HIGH_AR_2 0x31686C
+
+#define mmSIF_RTR_CTRL_1_RANGE_SEC_BASE_HIGH_AR_3 0x316870
+
+#define mmSIF_RTR_CTRL_1_RANGE_SEC_BASE_HIGH_AR_4 0x316874
+
+#define mmSIF_RTR_CTRL_1_RANGE_SEC_BASE_HIGH_AR_5 0x316878
+
+#define mmSIF_RTR_CTRL_1_RANGE_SEC_BASE_HIGH_AR_6 0x31687C
+
+#define mmSIF_RTR_CTRL_1_RANGE_SEC_BASE_HIGH_AR_7 0x316880
+
+#define mmSIF_RTR_CTRL_1_RANGE_SEC_BASE_HIGH_AR_8 0x316884
+
+#define mmSIF_RTR_CTRL_1_RANGE_SEC_BASE_HIGH_AR_9 0x316888
+
+#define mmSIF_RTR_CTRL_1_RANGE_SEC_BASE_HIGH_AR_10 0x31688C
+
+#define mmSIF_RTR_CTRL_1_RANGE_SEC_BASE_HIGH_AR_11 0x316890
+
+#define mmSIF_RTR_CTRL_1_RANGE_SEC_BASE_HIGH_AR_12 0x316894
+
+#define mmSIF_RTR_CTRL_1_RANGE_SEC_BASE_HIGH_AR_13 0x316898
+
+#define mmSIF_RTR_CTRL_1_RANGE_SEC_BASE_HIGH_AR_14 0x31689C
+
+#define mmSIF_RTR_CTRL_1_RANGE_SEC_BASE_HIGH_AR_15 0x3168A0
+
+#define mmSIF_RTR_CTRL_1_RANGE_SEC_MASK_LOW_AR_0 0x3168A4
+
+#define mmSIF_RTR_CTRL_1_RANGE_SEC_MASK_LOW_AR_1 0x3168A8
+
+#define mmSIF_RTR_CTRL_1_RANGE_SEC_MASK_LOW_AR_2 0x3168AC
+
+#define mmSIF_RTR_CTRL_1_RANGE_SEC_MASK_LOW_AR_3 0x3168B0
+
+#define mmSIF_RTR_CTRL_1_RANGE_SEC_MASK_LOW_AR_4 0x3168B4
+
+#define mmSIF_RTR_CTRL_1_RANGE_SEC_MASK_LOW_AR_5 0x3168B8
+
+#define mmSIF_RTR_CTRL_1_RANGE_SEC_MASK_LOW_AR_6 0x3168BC
+
+#define mmSIF_RTR_CTRL_1_RANGE_SEC_MASK_LOW_AR_7 0x3168C0
+
+#define mmSIF_RTR_CTRL_1_RANGE_SEC_MASK_LOW_AR_8 0x3168C4
+
+#define mmSIF_RTR_CTRL_1_RANGE_SEC_MASK_LOW_AR_9 0x3168C8
+
+#define mmSIF_RTR_CTRL_1_RANGE_SEC_MASK_LOW_AR_10 0x3168CC
+
+#define mmSIF_RTR_CTRL_1_RANGE_SEC_MASK_LOW_AR_11 0x3168D0
+
+#define mmSIF_RTR_CTRL_1_RANGE_SEC_MASK_LOW_AR_12 0x3168D4
+
+#define mmSIF_RTR_CTRL_1_RANGE_SEC_MASK_LOW_AR_13 0x3168D8
+
+#define mmSIF_RTR_CTRL_1_RANGE_SEC_MASK_LOW_AR_14 0x3168DC
+
+#define mmSIF_RTR_CTRL_1_RANGE_SEC_MASK_LOW_AR_15 0x3168E0
+
+#define mmSIF_RTR_CTRL_1_RANGE_SEC_MASK_HIGH_AR_0 0x3168E4
+
+#define mmSIF_RTR_CTRL_1_RANGE_SEC_MASK_HIGH_AR_1 0x3168E8
+
+#define mmSIF_RTR_CTRL_1_RANGE_SEC_MASK_HIGH_AR_2 0x3168EC
+
+#define mmSIF_RTR_CTRL_1_RANGE_SEC_MASK_HIGH_AR_3 0x3168F0
+
+#define mmSIF_RTR_CTRL_1_RANGE_SEC_MASK_HIGH_AR_4 0x3168F4
+
+#define mmSIF_RTR_CTRL_1_RANGE_SEC_MASK_HIGH_AR_5 0x3168F8
+
+#define mmSIF_RTR_CTRL_1_RANGE_SEC_MASK_HIGH_AR_6 0x3168FC
+
+#define mmSIF_RTR_CTRL_1_RANGE_SEC_MASK_HIGH_AR_7 0x316900
+
+#define mmSIF_RTR_CTRL_1_RANGE_SEC_MASK_HIGH_AR_8 0x316904
+
+#define mmSIF_RTR_CTRL_1_RANGE_SEC_MASK_HIGH_AR_9 0x316908
+
+#define mmSIF_RTR_CTRL_1_RANGE_SEC_MASK_HIGH_AR_10 0x31690C
+
+#define mmSIF_RTR_CTRL_1_RANGE_SEC_MASK_HIGH_AR_11 0x316910
+
+#define mmSIF_RTR_CTRL_1_RANGE_SEC_MASK_HIGH_AR_12 0x316914
+
+#define mmSIF_RTR_CTRL_1_RANGE_SEC_MASK_HIGH_AR_13 0x316918
+
+#define mmSIF_RTR_CTRL_1_RANGE_SEC_MASK_HIGH_AR_14 0x31691C
+
+#define mmSIF_RTR_CTRL_1_RANGE_SEC_MASK_HIGH_AR_15 0x316920
+
+#define mmSIF_RTR_CTRL_1_RANGE_PRIV_BASE_LOW_AR_0 0x316924
+
+#define mmSIF_RTR_CTRL_1_RANGE_PRIV_BASE_LOW_AR_1 0x316928
+
+#define mmSIF_RTR_CTRL_1_RANGE_PRIV_BASE_LOW_AR_2 0x31692C
+
+#define mmSIF_RTR_CTRL_1_RANGE_PRIV_BASE_LOW_AR_3 0x316930
+
+#define mmSIF_RTR_CTRL_1_RANGE_PRIV_BASE_LOW_AR_4 0x316934
+
+#define mmSIF_RTR_CTRL_1_RANGE_PRIV_BASE_LOW_AR_5 0x316938
+
+#define mmSIF_RTR_CTRL_1_RANGE_PRIV_BASE_LOW_AR_6 0x31693C
+
+#define mmSIF_RTR_CTRL_1_RANGE_PRIV_BASE_LOW_AR_7 0x316940
+
+#define mmSIF_RTR_CTRL_1_RANGE_PRIV_BASE_LOW_AR_8 0x316944
+
+#define mmSIF_RTR_CTRL_1_RANGE_PRIV_BASE_LOW_AR_9 0x316948
+
+#define mmSIF_RTR_CTRL_1_RANGE_PRIV_BASE_LOW_AR_10 0x31694C
+
+#define mmSIF_RTR_CTRL_1_RANGE_PRIV_BASE_LOW_AR_11 0x316950
+
+#define mmSIF_RTR_CTRL_1_RANGE_PRIV_BASE_LOW_AR_12 0x316954
+
+#define mmSIF_RTR_CTRL_1_RANGE_PRIV_BASE_LOW_AR_13 0x316958
+
+#define mmSIF_RTR_CTRL_1_RANGE_PRIV_BASE_LOW_AR_14 0x31695C
+
+#define mmSIF_RTR_CTRL_1_RANGE_PRIV_BASE_LOW_AR_15 0x316960
+
+#define mmSIF_RTR_CTRL_1_RANGE_PRIV_BASE_HIGH_AR_0 0x316964
+
+#define mmSIF_RTR_CTRL_1_RANGE_PRIV_BASE_HIGH_AR_1 0x316968
+
+#define mmSIF_RTR_CTRL_1_RANGE_PRIV_BASE_HIGH_AR_2 0x31696C
+
+#define mmSIF_RTR_CTRL_1_RANGE_PRIV_BASE_HIGH_AR_3 0x316970
+
+#define mmSIF_RTR_CTRL_1_RANGE_PRIV_BASE_HIGH_AR_4 0x316974
+
+#define mmSIF_RTR_CTRL_1_RANGE_PRIV_BASE_HIGH_AR_5 0x316978
+
+#define mmSIF_RTR_CTRL_1_RANGE_PRIV_BASE_HIGH_AR_6 0x31697C
+
+#define mmSIF_RTR_CTRL_1_RANGE_PRIV_BASE_HIGH_AR_7 0x316980
+
+#define mmSIF_RTR_CTRL_1_RANGE_PRIV_BASE_HIGH_AR_8 0x316984
+
+#define mmSIF_RTR_CTRL_1_RANGE_PRIV_BASE_HIGH_AR_9 0x316988
+
+#define mmSIF_RTR_CTRL_1_RANGE_PRIV_BASE_HIGH_AR_10 0x31698C
+
+#define mmSIF_RTR_CTRL_1_RANGE_PRIV_BASE_HIGH_AR_11 0x316990
+
+#define mmSIF_RTR_CTRL_1_RANGE_PRIV_BASE_HIGH_AR_12 0x316994
+
+#define mmSIF_RTR_CTRL_1_RANGE_PRIV_BASE_HIGH_AR_13 0x316998
+
+#define mmSIF_RTR_CTRL_1_RANGE_PRIV_BASE_HIGH_AR_14 0x31699C
+
+#define mmSIF_RTR_CTRL_1_RANGE_PRIV_BASE_HIGH_AR_15 0x3169A0
+
+#define mmSIF_RTR_CTRL_1_RANGE_PRIV_MASK_LOW_AR_0 0x3169A4
+
+#define mmSIF_RTR_CTRL_1_RANGE_PRIV_MASK_LOW_AR_1 0x3169A8
+
+#define mmSIF_RTR_CTRL_1_RANGE_PRIV_MASK_LOW_AR_2 0x3169AC
+
+#define mmSIF_RTR_CTRL_1_RANGE_PRIV_MASK_LOW_AR_3 0x3169B0
+
+#define mmSIF_RTR_CTRL_1_RANGE_PRIV_MASK_LOW_AR_4 0x3169B4
+
+#define mmSIF_RTR_CTRL_1_RANGE_PRIV_MASK_LOW_AR_5 0x3169B8
+
+#define mmSIF_RTR_CTRL_1_RANGE_PRIV_MASK_LOW_AR_6 0x3169BC
+
+#define mmSIF_RTR_CTRL_1_RANGE_PRIV_MASK_LOW_AR_7 0x3169C0
+
+#define mmSIF_RTR_CTRL_1_RANGE_PRIV_MASK_LOW_AR_8 0x3169C4
+
+#define mmSIF_RTR_CTRL_1_RANGE_PRIV_MASK_LOW_AR_9 0x3169C8
+
+#define mmSIF_RTR_CTRL_1_RANGE_PRIV_MASK_LOW_AR_10 0x3169CC
+
+#define mmSIF_RTR_CTRL_1_RANGE_PRIV_MASK_LOW_AR_11 0x3169D0
+
+#define mmSIF_RTR_CTRL_1_RANGE_PRIV_MASK_LOW_AR_12 0x3169D4
+
+#define mmSIF_RTR_CTRL_1_RANGE_PRIV_MASK_LOW_AR_13 0x3169D8
+
+#define mmSIF_RTR_CTRL_1_RANGE_PRIV_MASK_LOW_AR_14 0x3169DC
+
+#define mmSIF_RTR_CTRL_1_RANGE_PRIV_MASK_LOW_AR_15 0x3169E0
+
+#define mmSIF_RTR_CTRL_1_RANGE_PRIV_MASK_HIGH_AR_0 0x3169E4
+
+#define mmSIF_RTR_CTRL_1_RANGE_PRIV_MASK_HIGH_AR_1 0x3169E8
+
+#define mmSIF_RTR_CTRL_1_RANGE_PRIV_MASK_HIGH_AR_2 0x3169EC
+
+#define mmSIF_RTR_CTRL_1_RANGE_PRIV_MASK_HIGH_AR_3 0x3169F0
+
+#define mmSIF_RTR_CTRL_1_RANGE_PRIV_MASK_HIGH_AR_4 0x3169F4
+
+#define mmSIF_RTR_CTRL_1_RANGE_PRIV_MASK_HIGH_AR_5 0x3169F8
+
+#define mmSIF_RTR_CTRL_1_RANGE_PRIV_MASK_HIGH_AR_6 0x3169FC
+
+#define mmSIF_RTR_CTRL_1_RANGE_PRIV_MASK_HIGH_AR_7 0x316A00
+
+#define mmSIF_RTR_CTRL_1_RANGE_PRIV_MASK_HIGH_AR_8 0x316A04
+
+#define mmSIF_RTR_CTRL_1_RANGE_PRIV_MASK_HIGH_AR_9 0x316A08
+
+#define mmSIF_RTR_CTRL_1_RANGE_PRIV_MASK_HIGH_AR_10 0x316A0C
+
+#define mmSIF_RTR_CTRL_1_RANGE_PRIV_MASK_HIGH_AR_11 0x316A10
+
+#define mmSIF_RTR_CTRL_1_RANGE_PRIV_MASK_HIGH_AR_12 0x316A14
+
+#define mmSIF_RTR_CTRL_1_RANGE_PRIV_MASK_HIGH_AR_13 0x316A18
+
+#define mmSIF_RTR_CTRL_1_RANGE_PRIV_MASK_HIGH_AR_14 0x316A1C
+
+#define mmSIF_RTR_CTRL_1_RANGE_PRIV_MASK_HIGH_AR_15 0x316A20
+
+#define mmSIF_RTR_CTRL_1_RANGE_SEC_HIT_AW 0x316A64
+
+#define mmSIF_RTR_CTRL_1_RANGE_SEC_HIT_AR 0x316A68
+
+#define mmSIF_RTR_CTRL_1_RANGE_PRIV_HIT_AW 0x316A6C
+
+#define mmSIF_RTR_CTRL_1_RANGE_PRIV_HIT_AR 0x316A70
+
+#define mmSIF_RTR_CTRL_1_RGL_CFG 0x316B64
+
+#define mmSIF_RTR_CTRL_1_RGL_SHIFT 0x316B68
+
+#define mmSIF_RTR_CTRL_1_RGL_EXPECTED_LAT_0 0x316B6C
+
+#define mmSIF_RTR_CTRL_1_RGL_EXPECTED_LAT_1 0x316B70
+
+#define mmSIF_RTR_CTRL_1_RGL_EXPECTED_LAT_2 0x316B74
+
+#define mmSIF_RTR_CTRL_1_RGL_EXPECTED_LAT_3 0x316B78
+
+#define mmSIF_RTR_CTRL_1_RGL_EXPECTED_LAT_4 0x316B7C
+
+#define mmSIF_RTR_CTRL_1_RGL_EXPECTED_LAT_5 0x316B80
+
+#define mmSIF_RTR_CTRL_1_RGL_EXPECTED_LAT_6 0x316B84
+
+#define mmSIF_RTR_CTRL_1_RGL_EXPECTED_LAT_7 0x316B88
+
+#define mmSIF_RTR_CTRL_1_RGL_TOKEN_0 0x316BAC
+
+#define mmSIF_RTR_CTRL_1_RGL_TOKEN_1 0x316BB0
+
+#define mmSIF_RTR_CTRL_1_RGL_TOKEN_2 0x316BB4
+
+#define mmSIF_RTR_CTRL_1_RGL_TOKEN_3 0x316BB8
+
+#define mmSIF_RTR_CTRL_1_RGL_TOKEN_4 0x316BBC
+
+#define mmSIF_RTR_CTRL_1_RGL_TOKEN_5 0x316BC0
+
+#define mmSIF_RTR_CTRL_1_RGL_TOKEN_6 0x316BC4
+
+#define mmSIF_RTR_CTRL_1_RGL_TOKEN_7 0x316BC8
+
+#define mmSIF_RTR_CTRL_1_RGL_BANK_ID_0 0x316BEC
+
+#define mmSIF_RTR_CTRL_1_RGL_BANK_ID_1 0x316BF0
+
+#define mmSIF_RTR_CTRL_1_RGL_BANK_ID_2 0x316BF4
+
+#define mmSIF_RTR_CTRL_1_RGL_BANK_ID_3 0x316BF8
+
+#define mmSIF_RTR_CTRL_1_RGL_BANK_ID_4 0x316BFC
+
+#define mmSIF_RTR_CTRL_1_RGL_BANK_ID_5 0x316C00
+
+#define mmSIF_RTR_CTRL_1_RGL_BANK_ID_6 0x316C04
+
+#define mmSIF_RTR_CTRL_1_RGL_BANK_ID_7 0x316C08
+
+#define mmSIF_RTR_CTRL_1_RGL_WDT 0x316C2C
+
+#define mmSIF_RTR_CTRL_1_E2E_AR_HBM0_CH0_CTR_WRAP 0x316C30
+
+#define mmSIF_RTR_CTRL_1_E2E_AR_HBM0_CH1_CTR_WRAP 0x316C34
+
+#define mmSIF_RTR_CTRL_1_E2E_AR_HBM1_CH0_CTR_WRAP 0x316C38
+
+#define mmSIF_RTR_CTRL_1_E2E_AR_HBM1_CH1_CTR_WRAP 0x316C3C
+
+#define mmSIF_RTR_CTRL_1_E2E_AR_HBM2_CH0_CTR_WRAP 0x316C40
+
+#define mmSIF_RTR_CTRL_1_E2E_AR_HBM2_CH1_CTR_WRAP 0x316C44
+
+#define mmSIF_RTR_CTRL_1_E2E_AR_HBM3_CH0_CTR_WRAP 0x316C48
+
+#define mmSIF_RTR_CTRL_1_E2E_AR_HBM3_CH1_CTR_WRAP 0x316C4C
+
+#define mmSIF_RTR_CTRL_1_E2E_AR_HBM0_CH0_CTR_CNT 0x316C50
+
+#define mmSIF_RTR_CTRL_1_E2E_AR_HBM0_CH1_CTR_CNT 0x316C54
+
+#define mmSIF_RTR_CTRL_1_E2E_AR_HBM1_CH0_CTR_CNT 0x316C58
+
+#define mmSIF_RTR_CTRL_1_E2E_AR_HBM1_CH1_CTR_CNT 0x316C5C
+
+#define mmSIF_RTR_CTRL_1_E2E_AR_HBM2_CH0_CTR_CNT 0x316C60
+
+#define mmSIF_RTR_CTRL_1_E2E_AR_HBM2_CH1_CTR_CNT 0x316C64
+
+#define mmSIF_RTR_CTRL_1_E2E_AR_HBM3_CH0_CTR_CNT 0x316C68
+
+#define mmSIF_RTR_CTRL_1_E2E_AR_HBM3_CH1_CTR_CNT 0x316C6C
+
+#define mmSIF_RTR_CTRL_1_E2E_AW_HBM0_CH0_CTR_WRAP 0x316C70
+
+#define mmSIF_RTR_CTRL_1_E2E_AW_HBM0_CH1_CTR_WRAP 0x316C74
+
+#define mmSIF_RTR_CTRL_1_E2E_AW_HBM1_CH0_CTR_WRAP 0x316C78
+
+#define mmSIF_RTR_CTRL_1_E2E_AW_HBM1_CH1_CTR_WRAP 0x316C7C
+
+#define mmSIF_RTR_CTRL_1_E2E_AW_HBM2_CH0_CTR_WRAP 0x316C80
+
+#define mmSIF_RTR_CTRL_1_E2E_AW_HBM2_CH1_CTR_WRAP 0x316C84
+
+#define mmSIF_RTR_CTRL_1_E2E_AW_HBM3_CH0_CTR_WRAP 0x316C88
+
+#define mmSIF_RTR_CTRL_1_E2E_AW_HBM3_CH1_CTR_WRAP 0x316C8C
+
+#define mmSIF_RTR_CTRL_1_E2E_AW_HBM0_CH0_CTR_CNT 0x316C90
+
+#define mmSIF_RTR_CTRL_1_E2E_AW_HBM0_CH1_CTR_CNT 0x316C94
+
+#define mmSIF_RTR_CTRL_1_E2E_AW_HBM1_CH0_CTR_CNT 0x316C98
+
+#define mmSIF_RTR_CTRL_1_E2E_AW_HBM1_CH1_CTR_CNT 0x316C9C
+
+#define mmSIF_RTR_CTRL_1_E2E_AW_HBM2_CH0_CTR_CNT 0x316CA0
+
+#define mmSIF_RTR_CTRL_1_E2E_AW_HBM2_CH1_CTR_CNT 0x316CA4
+
+#define mmSIF_RTR_CTRL_1_E2E_AW_HBM3_CH0_CTR_CNT 0x316CA8
+
+#define mmSIF_RTR_CTRL_1_E2E_AW_HBM3_CH1_CTR_CNT 0x316CAC
+
+#define mmSIF_RTR_CTRL_1_NL_HBM_PC_SEL_0 0x316CB0
+
+#define mmSIF_RTR_CTRL_1_NL_HBM_PC_SEL_1 0x316CB4
+
+#define mmSIF_RTR_CTRL_1_NL_HBM_PC_SEL_2 0x316CB8
+
+#define mmSIF_RTR_CTRL_1_NL_HBM_PC_SEL_3 0x316CBC
+
+#endif /* ASIC_REG_SIF_RTR_CTRL_1_REGS_H_ */
diff --git a/drivers/accel/habanalabs/include/gaudi/asic_reg/sif_rtr_ctrl_2_regs.h b/drivers/accel/habanalabs/include/gaudi/asic_reg/sif_rtr_ctrl_2_regs.h
new file mode 100644
index 0000000000..330e5b42d6
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi/asic_reg/sif_rtr_ctrl_2_regs.h
@@ -0,0 +1,896 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2016-2018 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ ** DO NOT EDIT BELOW **
+ ************************************/
+
+#ifndef ASIC_REG_SIF_RTR_CTRL_2_REGS_H_
+#define ASIC_REG_SIF_RTR_CTRL_2_REGS_H_
+
+/*
+ *****************************************
+ * SIF_RTR_CTRL_2 (Prototype: RTR_CTRL)
+ *****************************************
+ */
+
+#define mmSIF_RTR_CTRL_2_PERM_SEL 0x326108
+
+#define mmSIF_RTR_CTRL_2_HBM_POLY_H3_0 0x326114
+
+#define mmSIF_RTR_CTRL_2_HBM_POLY_H3_1 0x326118
+
+#define mmSIF_RTR_CTRL_2_HBM_POLY_H3_2 0x32611C
+
+#define mmSIF_RTR_CTRL_2_HBM_POLY_H3_3 0x326120
+
+#define mmSIF_RTR_CTRL_2_HBM_POLY_H3_4 0x326124
+
+#define mmSIF_RTR_CTRL_2_HBM_POLY_H3_5 0x326128
+
+#define mmSIF_RTR_CTRL_2_HBM_POLY_H3_6 0x32612C
+
+#define mmSIF_RTR_CTRL_2_HBM_POLY_H3_7 0x326130
+
+#define mmSIF_RTR_CTRL_2_HBM_POLY_H3_8 0x326134
+
+#define mmSIF_RTR_CTRL_2_HBM_POLY_H3_9 0x326138
+
+#define mmSIF_RTR_CTRL_2_HBM_POLY_H3_10 0x32613C
+
+#define mmSIF_RTR_CTRL_2_HBM_POLY_H3_11 0x326140
+
+#define mmSIF_RTR_CTRL_2_HBM_POLY_H3_12 0x326144
+
+#define mmSIF_RTR_CTRL_2_HBM_POLY_H3_13 0x326148
+
+#define mmSIF_RTR_CTRL_2_HBM_POLY_H3_14 0x32614C
+
+#define mmSIF_RTR_CTRL_2_HBM_POLY_H3_15 0x326150
+
+#define mmSIF_RTR_CTRL_2_HBM_POLY_H3_16 0x326154
+
+#define mmSIF_RTR_CTRL_2_HBM_POLY_H3_17 0x326158
+
+#define mmSIF_RTR_CTRL_2_HBM_POLY_H3_18 0x32615C
+
+#define mmSIF_RTR_CTRL_2_HBM_POLY_H3_19 0x326160
+
+#define mmSIF_RTR_CTRL_2_HBM_POLY_H3_20 0x326164
+
+#define mmSIF_RTR_CTRL_2_HBM_POLY_H3_21 0x326168
+
+#define mmSIF_RTR_CTRL_2_HBM_POLY_H3_22 0x32616C
+
+#define mmSIF_RTR_CTRL_2_HBM_POLY_H3_23 0x326170
+
+#define mmSIF_RTR_CTRL_2_HBM_POLY_H3_24 0x326174
+
+#define mmSIF_RTR_CTRL_2_HBM_POLY_H3_25 0x326178
+
+#define mmSIF_RTR_CTRL_2_HBM_POLY_H3_26 0x32617C
+
+#define mmSIF_RTR_CTRL_2_HBM_POLY_H3_27 0x326180
+
+#define mmSIF_RTR_CTRL_2_SRAM_POLY_H3_0 0x326184
+
+#define mmSIF_RTR_CTRL_2_SRAM_POLY_H3_1 0x326188
+
+#define mmSIF_RTR_CTRL_2_SRAM_POLY_H3_2 0x32618C
+
+#define mmSIF_RTR_CTRL_2_SRAM_POLY_H3_3 0x326190
+
+#define mmSIF_RTR_CTRL_2_SRAM_POLY_H3_4 0x326194
+
+#define mmSIF_RTR_CTRL_2_SRAM_POLY_H3_5 0x326198
+
+#define mmSIF_RTR_CTRL_2_SRAM_POLY_H3_6 0x32619C
+
+#define mmSIF_RTR_CTRL_2_SRAM_POLY_H3_7 0x3261A0
+
+#define mmSIF_RTR_CTRL_2_SRAM_POLY_H3_8 0x3261A4
+
+#define mmSIF_RTR_CTRL_2_SRAM_POLY_H3_9 0x3261A8
+
+#define mmSIF_RTR_CTRL_2_SRAM_POLY_H3_10 0x3261AC
+
+#define mmSIF_RTR_CTRL_2_SRAM_POLY_H3_11 0x3261B0
+
+#define mmSIF_RTR_CTRL_2_SRAM_POLY_H3_12 0x3261B4
+
+#define mmSIF_RTR_CTRL_2_SRAM_POLY_H3_13 0x3261B8
+
+#define mmSIF_RTR_CTRL_2_SRAM_POLY_H3_14 0x3261BC
+
+#define mmSIF_RTR_CTRL_2_SCRAM_SRAM_EN 0x32626C
+
+#define mmSIF_RTR_CTRL_2_RL_HBM_EN 0x326274
+
+#define mmSIF_RTR_CTRL_2_RL_HBM_SAT 0x326278
+
+#define mmSIF_RTR_CTRL_2_RL_HBM_RST 0x32627C
+
+#define mmSIF_RTR_CTRL_2_RL_HBM_TIMEOUT 0x326280
+
+#define mmSIF_RTR_CTRL_2_SCRAM_HBM_EN 0x326284
+
+#define mmSIF_RTR_CTRL_2_RL_PCI_EN 0x326288
+
+#define mmSIF_RTR_CTRL_2_RL_PCI_SAT 0x32628C
+
+#define mmSIF_RTR_CTRL_2_RL_PCI_RST 0x326290
+
+#define mmSIF_RTR_CTRL_2_RL_PCI_TIMEOUT 0x326294
+
+#define mmSIF_RTR_CTRL_2_RL_SRAM_EN 0x32629C
+
+#define mmSIF_RTR_CTRL_2_RL_SRAM_SAT 0x3262A0
+
+#define mmSIF_RTR_CTRL_2_RL_SRAM_RST 0x3262A4
+
+#define mmSIF_RTR_CTRL_2_RL_SRAM_TIMEOUT 0x3262AC
+
+#define mmSIF_RTR_CTRL_2_RL_SRAM_RED 0x3262B4
+
+#define mmSIF_RTR_CTRL_2_E2E_HBM_EN 0x3262EC
+
+#define mmSIF_RTR_CTRL_2_E2E_PCI_EN 0x3262F0
+
+#define mmSIF_RTR_CTRL_2_E2E_HBM_WR_SIZE 0x3262F4
+
+#define mmSIF_RTR_CTRL_2_E2E_PCI_WR_SIZE 0x3262F8
+
+#define mmSIF_RTR_CTRL_2_E2E_AW_PCI_CTR_SET_EN 0x326404
+
+#define mmSIF_RTR_CTRL_2_E2E_AW_PCI_CTR_SET 0x326408
+
+#define mmSIF_RTR_CTRL_2_E2E_AW_PCI_CTR_WRAP 0x32640C
+
+#define mmSIF_RTR_CTRL_2_E2E_AW_PCI_CTR_CNT 0x326410
+
+#define mmSIF_RTR_CTRL_2_E2E_AW_HBM_CTR_SET_EN 0x326414
+
+#define mmSIF_RTR_CTRL_2_E2E_AW_HBM_CTR_SET 0x326418
+
+#define mmSIF_RTR_CTRL_2_E2E_HBM_RD_SIZE 0x32641C
+
+#define mmSIF_RTR_CTRL_2_E2E_PCI_RD_SIZE 0x326420
+
+#define mmSIF_RTR_CTRL_2_E2E_AR_PCI_CTR_SET_EN 0x326424
+
+#define mmSIF_RTR_CTRL_2_E2E_AR_PCI_CTR_SET 0x326428
+
+#define mmSIF_RTR_CTRL_2_E2E_AR_PCI_CTR_WRAP 0x32642C
+
+#define mmSIF_RTR_CTRL_2_E2E_AR_PCI_CTR_CNT 0x326430
+
+#define mmSIF_RTR_CTRL_2_E2E_AR_HBM_CTR_SET_EN 0x326434
+
+#define mmSIF_RTR_CTRL_2_E2E_AR_HBM_CTR_SET 0x326438
+
+#define mmSIF_RTR_CTRL_2_NL_HBM_SEL_0 0x326450
+
+#define mmSIF_RTR_CTRL_2_NL_HBM_SEL_1 0x326454
+
+#define mmSIF_RTR_CTRL_2_NON_LIN_EN 0x326480
+
+#define mmSIF_RTR_CTRL_2_NL_SRAM_BANK_0 0x326500
+
+#define mmSIF_RTR_CTRL_2_NL_SRAM_BANK_1 0x326504
+
+#define mmSIF_RTR_CTRL_2_NL_SRAM_BANK_2 0x326508
+
+#define mmSIF_RTR_CTRL_2_NL_SRAM_BANK_3 0x32650C
+
+#define mmSIF_RTR_CTRL_2_NL_SRAM_BANK_4 0x326510
+
+#define mmSIF_RTR_CTRL_2_NL_SRAM_OFFSET_0 0x326514
+
+#define mmSIF_RTR_CTRL_2_NL_SRAM_OFFSET_1 0x326520
+
+#define mmSIF_RTR_CTRL_2_NL_SRAM_OFFSET_2 0x326524
+
+#define mmSIF_RTR_CTRL_2_NL_SRAM_OFFSET_3 0x326528
+
+#define mmSIF_RTR_CTRL_2_NL_SRAM_OFFSET_4 0x32652C
+
+#define mmSIF_RTR_CTRL_2_NL_SRAM_OFFSET_5 0x326530
+
+#define mmSIF_RTR_CTRL_2_NL_SRAM_OFFSET_6 0x326534
+
+#define mmSIF_RTR_CTRL_2_NL_SRAM_OFFSET_7 0x326538
+
+#define mmSIF_RTR_CTRL_2_NL_SRAM_OFFSET_8 0x32653C
+
+#define mmSIF_RTR_CTRL_2_NL_SRAM_OFFSET_9 0x326540
+
+#define mmSIF_RTR_CTRL_2_NL_HBM_OFFSET_0 0x326550
+
+#define mmSIF_RTR_CTRL_2_NL_HBM_OFFSET_1 0x326554
+
+#define mmSIF_RTR_CTRL_2_NL_HBM_OFFSET_2 0x326558
+
+#define mmSIF_RTR_CTRL_2_NL_HBM_OFFSET_3 0x32655C
+
+#define mmSIF_RTR_CTRL_2_NL_HBM_OFFSET_4 0x326560
+
+#define mmSIF_RTR_CTRL_2_NL_HBM_OFFSET_5 0x326564
+
+#define mmSIF_RTR_CTRL_2_NL_HBM_OFFSET_6 0x326568
+
+#define mmSIF_RTR_CTRL_2_NL_HBM_OFFSET_7 0x32656C
+
+#define mmSIF_RTR_CTRL_2_NL_HBM_OFFSET_8 0x326570
+
+#define mmSIF_RTR_CTRL_2_NL_HBM_OFFSET_9 0x326574
+
+#define mmSIF_RTR_CTRL_2_NL_HBM_OFFSET_10 0x326578
+
+#define mmSIF_RTR_CTRL_2_NL_HBM_OFFSET_11 0x32657C
+
+#define mmSIF_RTR_CTRL_2_NL_HBM_OFFSET_12 0x326580
+
+#define mmSIF_RTR_CTRL_2_NL_HBM_OFFSET_13 0x326584
+
+#define mmSIF_RTR_CTRL_2_NL_HBM_OFFSET_14 0x326588
+
+#define mmSIF_RTR_CTRL_2_NL_HBM_OFFSET_15 0x32658C
+
+#define mmSIF_RTR_CTRL_2_NL_HBM_OFFSET_16 0x326590
+
+#define mmSIF_RTR_CTRL_2_NL_HBM_OFFSET_17 0x326594
+
+#define mmSIF_RTR_CTRL_2_NL_HBM_OFFSET_18 0x326598
+
+#define mmSIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AW_0 0x3265E4
+
+#define mmSIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AW_1 0x3265E8
+
+#define mmSIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AW_2 0x3265EC
+
+#define mmSIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AW_3 0x3265F0
+
+#define mmSIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AW_4 0x3265F4
+
+#define mmSIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AW_5 0x3265F8
+
+#define mmSIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AW_6 0x3265FC
+
+#define mmSIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AW_7 0x326600
+
+#define mmSIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AW_8 0x326604
+
+#define mmSIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AW_9 0x326608
+
+#define mmSIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AW_10 0x32660C
+
+#define mmSIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AW_11 0x326610
+
+#define mmSIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AW_12 0x326614
+
+#define mmSIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AW_13 0x326618
+
+#define mmSIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AW_14 0x32661C
+
+#define mmSIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AW_15 0x326620
+
+#define mmSIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AW_0 0x326624
+
+#define mmSIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AW_1 0x326628
+
+#define mmSIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AW_2 0x32662C
+
+#define mmSIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AW_3 0x326630
+
+#define mmSIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AW_4 0x326634
+
+#define mmSIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AW_5 0x326638
+
+#define mmSIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AW_6 0x32663C
+
+#define mmSIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AW_7 0x326640
+
+#define mmSIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AW_8 0x326644
+
+#define mmSIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AW_9 0x326648
+
+#define mmSIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AW_10 0x32664C
+
+#define mmSIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AW_11 0x326650
+
+#define mmSIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AW_12 0x326654
+
+#define mmSIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AW_13 0x326658
+
+#define mmSIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AW_14 0x32665C
+
+#define mmSIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AW_15 0x326660
+
+#define mmSIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AW_0 0x326664
+
+#define mmSIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AW_1 0x326668
+
+#define mmSIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AW_2 0x32666C
+
+#define mmSIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AW_3 0x326670
+
+#define mmSIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AW_4 0x326674
+
+#define mmSIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AW_5 0x326678
+
+#define mmSIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AW_6 0x32667C
+
+#define mmSIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AW_7 0x326680
+
+#define mmSIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AW_8 0x326684
+
+#define mmSIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AW_9 0x326688
+
+#define mmSIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AW_10 0x32668C
+
+#define mmSIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AW_11 0x326690
+
+#define mmSIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AW_12 0x326694
+
+#define mmSIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AW_13 0x326698
+
+#define mmSIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AW_14 0x32669C
+
+#define mmSIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AW_15 0x3266A0
+
+#define mmSIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AW_0 0x3266A4
+
+#define mmSIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AW_1 0x3266A8
+
+#define mmSIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AW_2 0x3266AC
+
+#define mmSIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AW_3 0x3266B0
+
+#define mmSIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AW_4 0x3266B4
+
+#define mmSIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AW_5 0x3266B8
+
+#define mmSIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AW_6 0x3266BC
+
+#define mmSIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AW_7 0x3266C0
+
+#define mmSIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AW_8 0x3266C4
+
+#define mmSIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AW_9 0x3266C8
+
+#define mmSIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AW_10 0x3266CC
+
+#define mmSIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AW_11 0x3266D0
+
+#define mmSIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AW_12 0x3266D4
+
+#define mmSIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AW_13 0x3266D8
+
+#define mmSIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AW_14 0x3266DC
+
+#define mmSIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AW_15 0x3266E0
+
+#define mmSIF_RTR_CTRL_2_RANGE_PRIV_BASE_LOW_AW_0 0x3266E4
+
+#define mmSIF_RTR_CTRL_2_RANGE_PRIV_BASE_LOW_AW_1 0x3266E8
+
+#define mmSIF_RTR_CTRL_2_RANGE_PRIV_BASE_LOW_AW_2 0x3266EC
+
+#define mmSIF_RTR_CTRL_2_RANGE_PRIV_BASE_LOW_AW_3 0x3266F0
+
+#define mmSIF_RTR_CTRL_2_RANGE_PRIV_BASE_LOW_AW_4 0x3266F4
+
+#define mmSIF_RTR_CTRL_2_RANGE_PRIV_BASE_LOW_AW_5 0x3266F8
+
+#define mmSIF_RTR_CTRL_2_RANGE_PRIV_BASE_LOW_AW_6 0x3266FC
+
+#define mmSIF_RTR_CTRL_2_RANGE_PRIV_BASE_LOW_AW_7 0x326700
+
+#define mmSIF_RTR_CTRL_2_RANGE_PRIV_BASE_LOW_AW_8 0x326704
+
+#define mmSIF_RTR_CTRL_2_RANGE_PRIV_BASE_LOW_AW_9 0x326708
+
+#define mmSIF_RTR_CTRL_2_RANGE_PRIV_BASE_LOW_AW_10 0x32670C
+
+#define mmSIF_RTR_CTRL_2_RANGE_PRIV_BASE_LOW_AW_11 0x326710
+
+#define mmSIF_RTR_CTRL_2_RANGE_PRIV_BASE_LOW_AW_12 0x326714
+
+#define mmSIF_RTR_CTRL_2_RANGE_PRIV_BASE_LOW_AW_13 0x326718
+
+#define mmSIF_RTR_CTRL_2_RANGE_PRIV_BASE_LOW_AW_14 0x32671C
+
+#define mmSIF_RTR_CTRL_2_RANGE_PRIV_BASE_LOW_AW_15 0x326720
+
+#define mmSIF_RTR_CTRL_2_RANGE_PRIV_BASE_HIGH_AW_0 0x326724
+
+#define mmSIF_RTR_CTRL_2_RANGE_PRIV_BASE_HIGH_AW_1 0x326728
+
+#define mmSIF_RTR_CTRL_2_RANGE_PRIV_BASE_HIGH_AW_2 0x32672C
+
+#define mmSIF_RTR_CTRL_2_RANGE_PRIV_BASE_HIGH_AW_3 0x326730
+
+#define mmSIF_RTR_CTRL_2_RANGE_PRIV_BASE_HIGH_AW_4 0x326734
+
+#define mmSIF_RTR_CTRL_2_RANGE_PRIV_BASE_HIGH_AW_5 0x326738
+
+#define mmSIF_RTR_CTRL_2_RANGE_PRIV_BASE_HIGH_AW_6 0x32673C
+
+#define mmSIF_RTR_CTRL_2_RANGE_PRIV_BASE_HIGH_AW_7 0x326740
+
+#define mmSIF_RTR_CTRL_2_RANGE_PRIV_BASE_HIGH_AW_8 0x326744
+
+#define mmSIF_RTR_CTRL_2_RANGE_PRIV_BASE_HIGH_AW_9 0x326748
+
+#define mmSIF_RTR_CTRL_2_RANGE_PRIV_BASE_HIGH_AW_10 0x32674C
+
+#define mmSIF_RTR_CTRL_2_RANGE_PRIV_BASE_HIGH_AW_11 0x326750
+
+#define mmSIF_RTR_CTRL_2_RANGE_PRIV_BASE_HIGH_AW_12 0x326754
+
+#define mmSIF_RTR_CTRL_2_RANGE_PRIV_BASE_HIGH_AW_13 0x326758
+
+#define mmSIF_RTR_CTRL_2_RANGE_PRIV_BASE_HIGH_AW_14 0x32675C
+
+#define mmSIF_RTR_CTRL_2_RANGE_PRIV_BASE_HIGH_AW_15 0x326760
+
+#define mmSIF_RTR_CTRL_2_RANGE_PRIV_MASK_LOW_AW_0 0x326764
+
+#define mmSIF_RTR_CTRL_2_RANGE_PRIV_MASK_LOW_AW_1 0x326768
+
+#define mmSIF_RTR_CTRL_2_RANGE_PRIV_MASK_LOW_AW_2 0x32676C
+
+#define mmSIF_RTR_CTRL_2_RANGE_PRIV_MASK_LOW_AW_3 0x326770
+
+#define mmSIF_RTR_CTRL_2_RANGE_PRIV_MASK_LOW_AW_4 0x326774
+
+#define mmSIF_RTR_CTRL_2_RANGE_PRIV_MASK_LOW_AW_5 0x326778
+
+#define mmSIF_RTR_CTRL_2_RANGE_PRIV_MASK_LOW_AW_6 0x32677C
+
+#define mmSIF_RTR_CTRL_2_RANGE_PRIV_MASK_LOW_AW_7 0x326780
+
+#define mmSIF_RTR_CTRL_2_RANGE_PRIV_MASK_LOW_AW_8 0x326784
+
+#define mmSIF_RTR_CTRL_2_RANGE_PRIV_MASK_LOW_AW_9 0x326788
+
+#define mmSIF_RTR_CTRL_2_RANGE_PRIV_MASK_LOW_AW_10 0x32678C
+
+#define mmSIF_RTR_CTRL_2_RANGE_PRIV_MASK_LOW_AW_11 0x326790
+
+#define mmSIF_RTR_CTRL_2_RANGE_PRIV_MASK_LOW_AW_12 0x326794
+
+#define mmSIF_RTR_CTRL_2_RANGE_PRIV_MASK_LOW_AW_13 0x326798
+
+#define mmSIF_RTR_CTRL_2_RANGE_PRIV_MASK_LOW_AW_14 0x32679C
+
+#define mmSIF_RTR_CTRL_2_RANGE_PRIV_MASK_LOW_AW_15 0x3267A0
+
+#define mmSIF_RTR_CTRL_2_RANGE_PRIV_MASK_HIGH_AW_0 0x3267A4
+
+#define mmSIF_RTR_CTRL_2_RANGE_PRIV_MASK_HIGH_AW_1 0x3267A8
+
+#define mmSIF_RTR_CTRL_2_RANGE_PRIV_MASK_HIGH_AW_2 0x3267AC
+
+#define mmSIF_RTR_CTRL_2_RANGE_PRIV_MASK_HIGH_AW_3 0x3267B0
+
+#define mmSIF_RTR_CTRL_2_RANGE_PRIV_MASK_HIGH_AW_4 0x3267B4
+
+#define mmSIF_RTR_CTRL_2_RANGE_PRIV_MASK_HIGH_AW_5 0x3267B8
+
+#define mmSIF_RTR_CTRL_2_RANGE_PRIV_MASK_HIGH_AW_6 0x3267BC
+
+#define mmSIF_RTR_CTRL_2_RANGE_PRIV_MASK_HIGH_AW_7 0x3267C0
+
+#define mmSIF_RTR_CTRL_2_RANGE_PRIV_MASK_HIGH_AW_8 0x3267C4
+
+#define mmSIF_RTR_CTRL_2_RANGE_PRIV_MASK_HIGH_AW_9 0x3267C8
+
+#define mmSIF_RTR_CTRL_2_RANGE_PRIV_MASK_HIGH_AW_10 0x3267CC
+
+#define mmSIF_RTR_CTRL_2_RANGE_PRIV_MASK_HIGH_AW_11 0x3267D0
+
+#define mmSIF_RTR_CTRL_2_RANGE_PRIV_MASK_HIGH_AW_12 0x3267D4
+
+#define mmSIF_RTR_CTRL_2_RANGE_PRIV_MASK_HIGH_AW_13 0x3267D8
+
+#define mmSIF_RTR_CTRL_2_RANGE_PRIV_MASK_HIGH_AW_14 0x3267DC
+
+#define mmSIF_RTR_CTRL_2_RANGE_PRIV_MASK_HIGH_AW_15 0x3267E0
+
+#define mmSIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AR_0 0x326824
+
+#define mmSIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AR_1 0x326828
+
+#define mmSIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AR_2 0x32682C
+
+#define mmSIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AR_3 0x326830
+
+#define mmSIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AR_4 0x326834
+
+#define mmSIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AR_5 0x326838
+
+#define mmSIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AR_6 0x32683C
+
+#define mmSIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AR_7 0x326840
+
+#define mmSIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AR_8 0x326844
+
+#define mmSIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AR_9 0x326848
+
+#define mmSIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AR_10 0x32684C
+
+#define mmSIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AR_11 0x326850
+
+#define mmSIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AR_12 0x326854
+
+#define mmSIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AR_13 0x326858
+
+#define mmSIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AR_14 0x32685C
+
+#define mmSIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AR_15 0x326860
+
+#define mmSIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AR_0 0x326864
+
+#define mmSIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AR_1 0x326868
+
+#define mmSIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AR_2 0x32686C
+
+#define mmSIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AR_3 0x326870
+
+#define mmSIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AR_4 0x326874
+
+#define mmSIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AR_5 0x326878
+
+#define mmSIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AR_6 0x32687C
+
+#define mmSIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AR_7 0x326880
+
+#define mmSIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AR_8 0x326884
+
+#define mmSIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AR_9 0x326888
+
+#define mmSIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AR_10 0x32688C
+
+#define mmSIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AR_11 0x326890
+
+#define mmSIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AR_12 0x326894
+
+#define mmSIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AR_13 0x326898
+
+#define mmSIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AR_14 0x32689C
+
+#define mmSIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AR_15 0x3268A0
+
+#define mmSIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AR_0 0x3268A4
+
+#define mmSIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AR_1 0x3268A8
+
+#define mmSIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AR_2 0x3268AC
+
+#define mmSIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AR_3 0x3268B0
+
+#define mmSIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AR_4 0x3268B4
+
+#define mmSIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AR_5 0x3268B8
+
+#define mmSIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AR_6 0x3268BC
+
+#define mmSIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AR_7 0x3268C0
+
+#define mmSIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AR_8 0x3268C4
+
+#define mmSIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AR_9 0x3268C8
+
+#define mmSIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AR_10 0x3268CC
+
+#define mmSIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AR_11 0x3268D0
+
+#define mmSIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AR_12 0x3268D4
+
+#define mmSIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AR_13 0x3268D8
+
+#define mmSIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AR_14 0x3268DC
+
+#define mmSIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AR_15 0x3268E0
+
+#define mmSIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AR_0 0x3268E4
+
+#define mmSIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AR_1 0x3268E8
+
+#define mmSIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AR_2 0x3268EC
+
+#define mmSIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AR_3 0x3268F0
+
+#define mmSIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AR_4 0x3268F4
+
+#define mmSIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AR_5 0x3268F8
+
+#define mmSIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AR_6 0x3268FC
+
+#define mmSIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AR_7 0x326900
+
+#define mmSIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AR_8 0x326904
+
+#define mmSIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AR_9 0x326908
+
+#define mmSIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AR_10 0x32690C
+
+#define mmSIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AR_11 0x326910
+
+#define mmSIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AR_12 0x326914
+
+#define mmSIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AR_13 0x326918
+
+#define mmSIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AR_14 0x32691C
+
+#define mmSIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AR_15 0x326920
+
+#define mmSIF_RTR_CTRL_2_RANGE_PRIV_BASE_LOW_AR_0 0x326924
+
+#define mmSIF_RTR_CTRL_2_RANGE_PRIV_BASE_LOW_AR_1 0x326928
+
+#define mmSIF_RTR_CTRL_2_RANGE_PRIV_BASE_LOW_AR_2 0x32692C
+
+#define mmSIF_RTR_CTRL_2_RANGE_PRIV_BASE_LOW_AR_3 0x326930
+
+#define mmSIF_RTR_CTRL_2_RANGE_PRIV_BASE_LOW_AR_4 0x326934
+
+#define mmSIF_RTR_CTRL_2_RANGE_PRIV_BASE_LOW_AR_5 0x326938
+
+#define mmSIF_RTR_CTRL_2_RANGE_PRIV_BASE_LOW_AR_6 0x32693C
+
+#define mmSIF_RTR_CTRL_2_RANGE_PRIV_BASE_LOW_AR_7 0x326940
+
+#define mmSIF_RTR_CTRL_2_RANGE_PRIV_BASE_LOW_AR_8 0x326944
+
+#define mmSIF_RTR_CTRL_2_RANGE_PRIV_BASE_LOW_AR_9 0x326948
+
+#define mmSIF_RTR_CTRL_2_RANGE_PRIV_BASE_LOW_AR_10 0x32694C
+
+#define mmSIF_RTR_CTRL_2_RANGE_PRIV_BASE_LOW_AR_11 0x326950
+
+#define mmSIF_RTR_CTRL_2_RANGE_PRIV_BASE_LOW_AR_12 0x326954
+
+#define mmSIF_RTR_CTRL_2_RANGE_PRIV_BASE_LOW_AR_13 0x326958
+
+#define mmSIF_RTR_CTRL_2_RANGE_PRIV_BASE_LOW_AR_14 0x32695C
+
+#define mmSIF_RTR_CTRL_2_RANGE_PRIV_BASE_LOW_AR_15 0x326960
+
+#define mmSIF_RTR_CTRL_2_RANGE_PRIV_BASE_HIGH_AR_0 0x326964
+
+#define mmSIF_RTR_CTRL_2_RANGE_PRIV_BASE_HIGH_AR_1 0x326968
+
+#define mmSIF_RTR_CTRL_2_RANGE_PRIV_BASE_HIGH_AR_2 0x32696C
+
+#define mmSIF_RTR_CTRL_2_RANGE_PRIV_BASE_HIGH_AR_3 0x326970
+
+#define mmSIF_RTR_CTRL_2_RANGE_PRIV_BASE_HIGH_AR_4 0x326974
+
+#define mmSIF_RTR_CTRL_2_RANGE_PRIV_BASE_HIGH_AR_5 0x326978
+
+#define mmSIF_RTR_CTRL_2_RANGE_PRIV_BASE_HIGH_AR_6 0x32697C
+
+#define mmSIF_RTR_CTRL_2_RANGE_PRIV_BASE_HIGH_AR_7 0x326980
+
+#define mmSIF_RTR_CTRL_2_RANGE_PRIV_BASE_HIGH_AR_8 0x326984
+
+#define mmSIF_RTR_CTRL_2_RANGE_PRIV_BASE_HIGH_AR_9 0x326988
+
+#define mmSIF_RTR_CTRL_2_RANGE_PRIV_BASE_HIGH_AR_10 0x32698C
+
+#define mmSIF_RTR_CTRL_2_RANGE_PRIV_BASE_HIGH_AR_11 0x326990
+
+#define mmSIF_RTR_CTRL_2_RANGE_PRIV_BASE_HIGH_AR_12 0x326994
+
+#define mmSIF_RTR_CTRL_2_RANGE_PRIV_BASE_HIGH_AR_13 0x326998
+
+#define mmSIF_RTR_CTRL_2_RANGE_PRIV_BASE_HIGH_AR_14 0x32699C
+
+#define mmSIF_RTR_CTRL_2_RANGE_PRIV_BASE_HIGH_AR_15 0x3269A0
+
+#define mmSIF_RTR_CTRL_2_RANGE_PRIV_MASK_LOW_AR_0 0x3269A4
+
+#define mmSIF_RTR_CTRL_2_RANGE_PRIV_MASK_LOW_AR_1 0x3269A8
+
+#define mmSIF_RTR_CTRL_2_RANGE_PRIV_MASK_LOW_AR_2 0x3269AC
+
+#define mmSIF_RTR_CTRL_2_RANGE_PRIV_MASK_LOW_AR_3 0x3269B0
+
+#define mmSIF_RTR_CTRL_2_RANGE_PRIV_MASK_LOW_AR_4 0x3269B4
+
+#define mmSIF_RTR_CTRL_2_RANGE_PRIV_MASK_LOW_AR_5 0x3269B8
+
+#define mmSIF_RTR_CTRL_2_RANGE_PRIV_MASK_LOW_AR_6 0x3269BC
+
+#define mmSIF_RTR_CTRL_2_RANGE_PRIV_MASK_LOW_AR_7 0x3269C0
+
+#define mmSIF_RTR_CTRL_2_RANGE_PRIV_MASK_LOW_AR_8 0x3269C4
+
+#define mmSIF_RTR_CTRL_2_RANGE_PRIV_MASK_LOW_AR_9 0x3269C8
+
+#define mmSIF_RTR_CTRL_2_RANGE_PRIV_MASK_LOW_AR_10 0x3269CC
+
+#define mmSIF_RTR_CTRL_2_RANGE_PRIV_MASK_LOW_AR_11 0x3269D0
+
+#define mmSIF_RTR_CTRL_2_RANGE_PRIV_MASK_LOW_AR_12 0x3269D4
+
+#define mmSIF_RTR_CTRL_2_RANGE_PRIV_MASK_LOW_AR_13 0x3269D8
+
+#define mmSIF_RTR_CTRL_2_RANGE_PRIV_MASK_LOW_AR_14 0x3269DC
+
+#define mmSIF_RTR_CTRL_2_RANGE_PRIV_MASK_LOW_AR_15 0x3269E0
+
+#define mmSIF_RTR_CTRL_2_RANGE_PRIV_MASK_HIGH_AR_0 0x3269E4
+
+#define mmSIF_RTR_CTRL_2_RANGE_PRIV_MASK_HIGH_AR_1 0x3269E8
+
+#define mmSIF_RTR_CTRL_2_RANGE_PRIV_MASK_HIGH_AR_2 0x3269EC
+
+#define mmSIF_RTR_CTRL_2_RANGE_PRIV_MASK_HIGH_AR_3 0x3269F0
+
+#define mmSIF_RTR_CTRL_2_RANGE_PRIV_MASK_HIGH_AR_4 0x3269F4
+
+#define mmSIF_RTR_CTRL_2_RANGE_PRIV_MASK_HIGH_AR_5 0x3269F8
+
+#define mmSIF_RTR_CTRL_2_RANGE_PRIV_MASK_HIGH_AR_6 0x3269FC
+
+#define mmSIF_RTR_CTRL_2_RANGE_PRIV_MASK_HIGH_AR_7 0x326A00
+
+#define mmSIF_RTR_CTRL_2_RANGE_PRIV_MASK_HIGH_AR_8 0x326A04
+
+#define mmSIF_RTR_CTRL_2_RANGE_PRIV_MASK_HIGH_AR_9 0x326A08
+
+#define mmSIF_RTR_CTRL_2_RANGE_PRIV_MASK_HIGH_AR_10 0x326A0C
+
+#define mmSIF_RTR_CTRL_2_RANGE_PRIV_MASK_HIGH_AR_11 0x326A10
+
+#define mmSIF_RTR_CTRL_2_RANGE_PRIV_MASK_HIGH_AR_12 0x326A14
+
+#define mmSIF_RTR_CTRL_2_RANGE_PRIV_MASK_HIGH_AR_13 0x326A18
+
+#define mmSIF_RTR_CTRL_2_RANGE_PRIV_MASK_HIGH_AR_14 0x326A1C
+
+#define mmSIF_RTR_CTRL_2_RANGE_PRIV_MASK_HIGH_AR_15 0x326A20
+
+#define mmSIF_RTR_CTRL_2_RANGE_SEC_HIT_AW 0x326A64
+
+#define mmSIF_RTR_CTRL_2_RANGE_SEC_HIT_AR 0x326A68
+
+#define mmSIF_RTR_CTRL_2_RANGE_PRIV_HIT_AW 0x326A6C
+
+#define mmSIF_RTR_CTRL_2_RANGE_PRIV_HIT_AR 0x326A70
+
+#define mmSIF_RTR_CTRL_2_RGL_CFG 0x326B64
+
+#define mmSIF_RTR_CTRL_2_RGL_SHIFT 0x326B68
+
+#define mmSIF_RTR_CTRL_2_RGL_EXPECTED_LAT_0 0x326B6C
+
+#define mmSIF_RTR_CTRL_2_RGL_EXPECTED_LAT_1 0x326B70
+
+#define mmSIF_RTR_CTRL_2_RGL_EXPECTED_LAT_2 0x326B74
+
+#define mmSIF_RTR_CTRL_2_RGL_EXPECTED_LAT_3 0x326B78
+
+#define mmSIF_RTR_CTRL_2_RGL_EXPECTED_LAT_4 0x326B7C
+
+#define mmSIF_RTR_CTRL_2_RGL_EXPECTED_LAT_5 0x326B80
+
+#define mmSIF_RTR_CTRL_2_RGL_EXPECTED_LAT_6 0x326B84
+
+#define mmSIF_RTR_CTRL_2_RGL_EXPECTED_LAT_7 0x326B88
+
+#define mmSIF_RTR_CTRL_2_RGL_TOKEN_0 0x326BAC
+
+#define mmSIF_RTR_CTRL_2_RGL_TOKEN_1 0x326BB0
+
+#define mmSIF_RTR_CTRL_2_RGL_TOKEN_2 0x326BB4
+
+#define mmSIF_RTR_CTRL_2_RGL_TOKEN_3 0x326BB8
+
+#define mmSIF_RTR_CTRL_2_RGL_TOKEN_4 0x326BBC
+
+#define mmSIF_RTR_CTRL_2_RGL_TOKEN_5 0x326BC0
+
+#define mmSIF_RTR_CTRL_2_RGL_TOKEN_6 0x326BC4
+
+#define mmSIF_RTR_CTRL_2_RGL_TOKEN_7 0x326BC8
+
+#define mmSIF_RTR_CTRL_2_RGL_BANK_ID_0 0x326BEC
+
+#define mmSIF_RTR_CTRL_2_RGL_BANK_ID_1 0x326BF0
+
+#define mmSIF_RTR_CTRL_2_RGL_BANK_ID_2 0x326BF4
+
+#define mmSIF_RTR_CTRL_2_RGL_BANK_ID_3 0x326BF8
+
+#define mmSIF_RTR_CTRL_2_RGL_BANK_ID_4 0x326BFC
+
+#define mmSIF_RTR_CTRL_2_RGL_BANK_ID_5 0x326C00
+
+#define mmSIF_RTR_CTRL_2_RGL_BANK_ID_6 0x326C04
+
+#define mmSIF_RTR_CTRL_2_RGL_BANK_ID_7 0x326C08
+
+#define mmSIF_RTR_CTRL_2_RGL_WDT 0x326C2C
+
+#define mmSIF_RTR_CTRL_2_E2E_AR_HBM0_CH0_CTR_WRAP 0x326C30
+
+#define mmSIF_RTR_CTRL_2_E2E_AR_HBM0_CH1_CTR_WRAP 0x326C34
+
+#define mmSIF_RTR_CTRL_2_E2E_AR_HBM1_CH0_CTR_WRAP 0x326C38
+
+#define mmSIF_RTR_CTRL_2_E2E_AR_HBM1_CH1_CTR_WRAP 0x326C3C
+
+#define mmSIF_RTR_CTRL_2_E2E_AR_HBM2_CH0_CTR_WRAP 0x326C40
+
+#define mmSIF_RTR_CTRL_2_E2E_AR_HBM2_CH1_CTR_WRAP 0x326C44
+
+#define mmSIF_RTR_CTRL_2_E2E_AR_HBM3_CH0_CTR_WRAP 0x326C48
+
+#define mmSIF_RTR_CTRL_2_E2E_AR_HBM3_CH1_CTR_WRAP 0x326C4C
+
+#define mmSIF_RTR_CTRL_2_E2E_AR_HBM0_CH0_CTR_CNT 0x326C50
+
+#define mmSIF_RTR_CTRL_2_E2E_AR_HBM0_CH1_CTR_CNT 0x326C54
+
+#define mmSIF_RTR_CTRL_2_E2E_AR_HBM1_CH0_CTR_CNT 0x326C58
+
+#define mmSIF_RTR_CTRL_2_E2E_AR_HBM1_CH1_CTR_CNT 0x326C5C
+
+#define mmSIF_RTR_CTRL_2_E2E_AR_HBM2_CH0_CTR_CNT 0x326C60
+
+#define mmSIF_RTR_CTRL_2_E2E_AR_HBM2_CH1_CTR_CNT 0x326C64
+
+#define mmSIF_RTR_CTRL_2_E2E_AR_HBM3_CH0_CTR_CNT 0x326C68
+
+#define mmSIF_RTR_CTRL_2_E2E_AR_HBM3_CH1_CTR_CNT 0x326C6C
+
+#define mmSIF_RTR_CTRL_2_E2E_AW_HBM0_CH0_CTR_WRAP 0x326C70
+
+#define mmSIF_RTR_CTRL_2_E2E_AW_HBM0_CH1_CTR_WRAP 0x326C74
+
+#define mmSIF_RTR_CTRL_2_E2E_AW_HBM1_CH0_CTR_WRAP 0x326C78
+
+#define mmSIF_RTR_CTRL_2_E2E_AW_HBM1_CH1_CTR_WRAP 0x326C7C
+
+#define mmSIF_RTR_CTRL_2_E2E_AW_HBM2_CH0_CTR_WRAP 0x326C80
+
+#define mmSIF_RTR_CTRL_2_E2E_AW_HBM2_CH1_CTR_WRAP 0x326C84
+
+#define mmSIF_RTR_CTRL_2_E2E_AW_HBM3_CH0_CTR_WRAP 0x326C88
+
+#define mmSIF_RTR_CTRL_2_E2E_AW_HBM3_CH1_CTR_WRAP 0x326C8C
+
+#define mmSIF_RTR_CTRL_2_E2E_AW_HBM0_CH0_CTR_CNT 0x326C90
+
+#define mmSIF_RTR_CTRL_2_E2E_AW_HBM0_CH1_CTR_CNT 0x326C94
+
+#define mmSIF_RTR_CTRL_2_E2E_AW_HBM1_CH0_CTR_CNT 0x326C98
+
+#define mmSIF_RTR_CTRL_2_E2E_AW_HBM1_CH1_CTR_CNT 0x326C9C
+
+#define mmSIF_RTR_CTRL_2_E2E_AW_HBM2_CH0_CTR_CNT 0x326CA0
+
+#define mmSIF_RTR_CTRL_2_E2E_AW_HBM2_CH1_CTR_CNT 0x326CA4
+
+#define mmSIF_RTR_CTRL_2_E2E_AW_HBM3_CH0_CTR_CNT 0x326CA8
+
+#define mmSIF_RTR_CTRL_2_E2E_AW_HBM3_CH1_CTR_CNT 0x326CAC
+
+#define mmSIF_RTR_CTRL_2_NL_HBM_PC_SEL_0 0x326CB0
+
+#define mmSIF_RTR_CTRL_2_NL_HBM_PC_SEL_1 0x326CB4
+
+#define mmSIF_RTR_CTRL_2_NL_HBM_PC_SEL_2 0x326CB8
+
+#define mmSIF_RTR_CTRL_2_NL_HBM_PC_SEL_3 0x326CBC
+
+#endif /* ASIC_REG_SIF_RTR_CTRL_2_REGS_H_ */
diff --git a/drivers/accel/habanalabs/include/gaudi/asic_reg/sif_rtr_ctrl_3_regs.h b/drivers/accel/habanalabs/include/gaudi/asic_reg/sif_rtr_ctrl_3_regs.h
new file mode 100644
index 0000000000..d749f1968e
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi/asic_reg/sif_rtr_ctrl_3_regs.h
@@ -0,0 +1,896 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2016-2018 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ ** DO NOT EDIT BELOW **
+ ************************************/
+
+#ifndef ASIC_REG_SIF_RTR_CTRL_3_REGS_H_
+#define ASIC_REG_SIF_RTR_CTRL_3_REGS_H_
+
+/*
+ *****************************************
+ * SIF_RTR_CTRL_3 (Prototype: RTR_CTRL)
+ *****************************************
+ */
+
+#define mmSIF_RTR_CTRL_3_PERM_SEL 0x336108
+
+#define mmSIF_RTR_CTRL_3_HBM_POLY_H3_0 0x336114
+
+#define mmSIF_RTR_CTRL_3_HBM_POLY_H3_1 0x336118
+
+#define mmSIF_RTR_CTRL_3_HBM_POLY_H3_2 0x33611C
+
+#define mmSIF_RTR_CTRL_3_HBM_POLY_H3_3 0x336120
+
+#define mmSIF_RTR_CTRL_3_HBM_POLY_H3_4 0x336124
+
+#define mmSIF_RTR_CTRL_3_HBM_POLY_H3_5 0x336128
+
+#define mmSIF_RTR_CTRL_3_HBM_POLY_H3_6 0x33612C
+
+#define mmSIF_RTR_CTRL_3_HBM_POLY_H3_7 0x336130
+
+#define mmSIF_RTR_CTRL_3_HBM_POLY_H3_8 0x336134
+
+#define mmSIF_RTR_CTRL_3_HBM_POLY_H3_9 0x336138
+
+#define mmSIF_RTR_CTRL_3_HBM_POLY_H3_10 0x33613C
+
+#define mmSIF_RTR_CTRL_3_HBM_POLY_H3_11 0x336140
+
+#define mmSIF_RTR_CTRL_3_HBM_POLY_H3_12 0x336144
+
+#define mmSIF_RTR_CTRL_3_HBM_POLY_H3_13 0x336148
+
+#define mmSIF_RTR_CTRL_3_HBM_POLY_H3_14 0x33614C
+
+#define mmSIF_RTR_CTRL_3_HBM_POLY_H3_15 0x336150
+
+#define mmSIF_RTR_CTRL_3_HBM_POLY_H3_16 0x336154
+
+#define mmSIF_RTR_CTRL_3_HBM_POLY_H3_17 0x336158
+
+#define mmSIF_RTR_CTRL_3_HBM_POLY_H3_18 0x33615C
+
+#define mmSIF_RTR_CTRL_3_HBM_POLY_H3_19 0x336160
+
+#define mmSIF_RTR_CTRL_3_HBM_POLY_H3_20 0x336164
+
+#define mmSIF_RTR_CTRL_3_HBM_POLY_H3_21 0x336168
+
+#define mmSIF_RTR_CTRL_3_HBM_POLY_H3_22 0x33616C
+
+#define mmSIF_RTR_CTRL_3_HBM_POLY_H3_23 0x336170
+
+#define mmSIF_RTR_CTRL_3_HBM_POLY_H3_24 0x336174
+
+#define mmSIF_RTR_CTRL_3_HBM_POLY_H3_25 0x336178
+
+#define mmSIF_RTR_CTRL_3_HBM_POLY_H3_26 0x33617C
+
+#define mmSIF_RTR_CTRL_3_HBM_POLY_H3_27 0x336180
+
+#define mmSIF_RTR_CTRL_3_SRAM_POLY_H3_0 0x336184
+
+#define mmSIF_RTR_CTRL_3_SRAM_POLY_H3_1 0x336188
+
+#define mmSIF_RTR_CTRL_3_SRAM_POLY_H3_2 0x33618C
+
+#define mmSIF_RTR_CTRL_3_SRAM_POLY_H3_3 0x336190
+
+#define mmSIF_RTR_CTRL_3_SRAM_POLY_H3_4 0x336194
+
+#define mmSIF_RTR_CTRL_3_SRAM_POLY_H3_5 0x336198
+
+#define mmSIF_RTR_CTRL_3_SRAM_POLY_H3_6 0x33619C
+
+#define mmSIF_RTR_CTRL_3_SRAM_POLY_H3_7 0x3361A0
+
+#define mmSIF_RTR_CTRL_3_SRAM_POLY_H3_8 0x3361A4
+
+#define mmSIF_RTR_CTRL_3_SRAM_POLY_H3_9 0x3361A8
+
+#define mmSIF_RTR_CTRL_3_SRAM_POLY_H3_10 0x3361AC
+
+#define mmSIF_RTR_CTRL_3_SRAM_POLY_H3_11 0x3361B0
+
+#define mmSIF_RTR_CTRL_3_SRAM_POLY_H3_12 0x3361B4
+
+#define mmSIF_RTR_CTRL_3_SRAM_POLY_H3_13 0x3361B8
+
+#define mmSIF_RTR_CTRL_3_SRAM_POLY_H3_14 0x3361BC
+
+#define mmSIF_RTR_CTRL_3_SCRAM_SRAM_EN 0x33626C
+
+#define mmSIF_RTR_CTRL_3_RL_HBM_EN 0x336274
+
+#define mmSIF_RTR_CTRL_3_RL_HBM_SAT 0x336278
+
+#define mmSIF_RTR_CTRL_3_RL_HBM_RST 0x33627C
+
+#define mmSIF_RTR_CTRL_3_RL_HBM_TIMEOUT 0x336280
+
+#define mmSIF_RTR_CTRL_3_SCRAM_HBM_EN 0x336284
+
+#define mmSIF_RTR_CTRL_3_RL_PCI_EN 0x336288
+
+#define mmSIF_RTR_CTRL_3_RL_PCI_SAT 0x33628C
+
+#define mmSIF_RTR_CTRL_3_RL_PCI_RST 0x336290
+
+#define mmSIF_RTR_CTRL_3_RL_PCI_TIMEOUT 0x336294
+
+#define mmSIF_RTR_CTRL_3_RL_SRAM_EN 0x33629C
+
+#define mmSIF_RTR_CTRL_3_RL_SRAM_SAT 0x3362A0
+
+#define mmSIF_RTR_CTRL_3_RL_SRAM_RST 0x3362A4
+
+#define mmSIF_RTR_CTRL_3_RL_SRAM_TIMEOUT 0x3362AC
+
+#define mmSIF_RTR_CTRL_3_RL_SRAM_RED 0x3362B4
+
+#define mmSIF_RTR_CTRL_3_E2E_HBM_EN 0x3362EC
+
+#define mmSIF_RTR_CTRL_3_E2E_PCI_EN 0x3362F0
+
+#define mmSIF_RTR_CTRL_3_E2E_HBM_WR_SIZE 0x3362F4
+
+#define mmSIF_RTR_CTRL_3_E2E_PCI_WR_SIZE 0x3362F8
+
+#define mmSIF_RTR_CTRL_3_E2E_AW_PCI_CTR_SET_EN 0x336404
+
+#define mmSIF_RTR_CTRL_3_E2E_AW_PCI_CTR_SET 0x336408
+
+#define mmSIF_RTR_CTRL_3_E2E_AW_PCI_CTR_WRAP 0x33640C
+
+#define mmSIF_RTR_CTRL_3_E2E_AW_PCI_CTR_CNT 0x336410
+
+#define mmSIF_RTR_CTRL_3_E2E_AW_HBM_CTR_SET_EN 0x336414
+
+#define mmSIF_RTR_CTRL_3_E2E_AW_HBM_CTR_SET 0x336418
+
+#define mmSIF_RTR_CTRL_3_E2E_HBM_RD_SIZE 0x33641C
+
+#define mmSIF_RTR_CTRL_3_E2E_PCI_RD_SIZE 0x336420
+
+#define mmSIF_RTR_CTRL_3_E2E_AR_PCI_CTR_SET_EN 0x336424
+
+#define mmSIF_RTR_CTRL_3_E2E_AR_PCI_CTR_SET 0x336428
+
+#define mmSIF_RTR_CTRL_3_E2E_AR_PCI_CTR_WRAP 0x33642C
+
+#define mmSIF_RTR_CTRL_3_E2E_AR_PCI_CTR_CNT 0x336430
+
+#define mmSIF_RTR_CTRL_3_E2E_AR_HBM_CTR_SET_EN 0x336434
+
+#define mmSIF_RTR_CTRL_3_E2E_AR_HBM_CTR_SET 0x336438
+
+#define mmSIF_RTR_CTRL_3_NL_HBM_SEL_0 0x336450
+
+#define mmSIF_RTR_CTRL_3_NL_HBM_SEL_1 0x336454
+
+#define mmSIF_RTR_CTRL_3_NON_LIN_EN 0x336480
+
+#define mmSIF_RTR_CTRL_3_NL_SRAM_BANK_0 0x336500
+
+#define mmSIF_RTR_CTRL_3_NL_SRAM_BANK_1 0x336504
+
+#define mmSIF_RTR_CTRL_3_NL_SRAM_BANK_2 0x336508
+
+#define mmSIF_RTR_CTRL_3_NL_SRAM_BANK_3 0x33650C
+
+#define mmSIF_RTR_CTRL_3_NL_SRAM_BANK_4 0x336510
+
+#define mmSIF_RTR_CTRL_3_NL_SRAM_OFFSET_0 0x336514
+
+#define mmSIF_RTR_CTRL_3_NL_SRAM_OFFSET_1 0x336520
+
+#define mmSIF_RTR_CTRL_3_NL_SRAM_OFFSET_2 0x336524
+
+#define mmSIF_RTR_CTRL_3_NL_SRAM_OFFSET_3 0x336528
+
+#define mmSIF_RTR_CTRL_3_NL_SRAM_OFFSET_4 0x33652C
+
+#define mmSIF_RTR_CTRL_3_NL_SRAM_OFFSET_5 0x336530
+
+#define mmSIF_RTR_CTRL_3_NL_SRAM_OFFSET_6 0x336534
+
+#define mmSIF_RTR_CTRL_3_NL_SRAM_OFFSET_7 0x336538
+
+#define mmSIF_RTR_CTRL_3_NL_SRAM_OFFSET_8 0x33653C
+
+#define mmSIF_RTR_CTRL_3_NL_SRAM_OFFSET_9 0x336540
+
+#define mmSIF_RTR_CTRL_3_NL_HBM_OFFSET_0 0x336550
+
+#define mmSIF_RTR_CTRL_3_NL_HBM_OFFSET_1 0x336554
+
+#define mmSIF_RTR_CTRL_3_NL_HBM_OFFSET_2 0x336558
+
+#define mmSIF_RTR_CTRL_3_NL_HBM_OFFSET_3 0x33655C
+
+#define mmSIF_RTR_CTRL_3_NL_HBM_OFFSET_4 0x336560
+
+#define mmSIF_RTR_CTRL_3_NL_HBM_OFFSET_5 0x336564
+
+#define mmSIF_RTR_CTRL_3_NL_HBM_OFFSET_6 0x336568
+
+#define mmSIF_RTR_CTRL_3_NL_HBM_OFFSET_7 0x33656C
+
+#define mmSIF_RTR_CTRL_3_NL_HBM_OFFSET_8 0x336570
+
+#define mmSIF_RTR_CTRL_3_NL_HBM_OFFSET_9 0x336574
+
+#define mmSIF_RTR_CTRL_3_NL_HBM_OFFSET_10 0x336578
+
+#define mmSIF_RTR_CTRL_3_NL_HBM_OFFSET_11 0x33657C
+
+#define mmSIF_RTR_CTRL_3_NL_HBM_OFFSET_12 0x336580
+
+#define mmSIF_RTR_CTRL_3_NL_HBM_OFFSET_13 0x336584
+
+#define mmSIF_RTR_CTRL_3_NL_HBM_OFFSET_14 0x336588
+
+#define mmSIF_RTR_CTRL_3_NL_HBM_OFFSET_15 0x33658C
+
+#define mmSIF_RTR_CTRL_3_NL_HBM_OFFSET_16 0x336590
+
+#define mmSIF_RTR_CTRL_3_NL_HBM_OFFSET_17 0x336594
+
+#define mmSIF_RTR_CTRL_3_NL_HBM_OFFSET_18 0x336598
+
+#define mmSIF_RTR_CTRL_3_RANGE_SEC_BASE_LOW_AW_0 0x3365E4
+
+#define mmSIF_RTR_CTRL_3_RANGE_SEC_BASE_LOW_AW_1 0x3365E8
+
+#define mmSIF_RTR_CTRL_3_RANGE_SEC_BASE_LOW_AW_2 0x3365EC
+
+#define mmSIF_RTR_CTRL_3_RANGE_SEC_BASE_LOW_AW_3 0x3365F0
+
+#define mmSIF_RTR_CTRL_3_RANGE_SEC_BASE_LOW_AW_4 0x3365F4
+
+#define mmSIF_RTR_CTRL_3_RANGE_SEC_BASE_LOW_AW_5 0x3365F8
+
+#define mmSIF_RTR_CTRL_3_RANGE_SEC_BASE_LOW_AW_6 0x3365FC
+
+#define mmSIF_RTR_CTRL_3_RANGE_SEC_BASE_LOW_AW_7 0x336600
+
+#define mmSIF_RTR_CTRL_3_RANGE_SEC_BASE_LOW_AW_8 0x336604
+
+#define mmSIF_RTR_CTRL_3_RANGE_SEC_BASE_LOW_AW_9 0x336608
+
+#define mmSIF_RTR_CTRL_3_RANGE_SEC_BASE_LOW_AW_10 0x33660C
+
+#define mmSIF_RTR_CTRL_3_RANGE_SEC_BASE_LOW_AW_11 0x336610
+
+#define mmSIF_RTR_CTRL_3_RANGE_SEC_BASE_LOW_AW_12 0x336614
+
+#define mmSIF_RTR_CTRL_3_RANGE_SEC_BASE_LOW_AW_13 0x336618
+
+#define mmSIF_RTR_CTRL_3_RANGE_SEC_BASE_LOW_AW_14 0x33661C
+
+#define mmSIF_RTR_CTRL_3_RANGE_SEC_BASE_LOW_AW_15 0x336620
+
+#define mmSIF_RTR_CTRL_3_RANGE_SEC_BASE_HIGH_AW_0 0x336624
+
+#define mmSIF_RTR_CTRL_3_RANGE_SEC_BASE_HIGH_AW_1 0x336628
+
+#define mmSIF_RTR_CTRL_3_RANGE_SEC_BASE_HIGH_AW_2 0x33662C
+
+#define mmSIF_RTR_CTRL_3_RANGE_SEC_BASE_HIGH_AW_3 0x336630
+
+#define mmSIF_RTR_CTRL_3_RANGE_SEC_BASE_HIGH_AW_4 0x336634
+
+#define mmSIF_RTR_CTRL_3_RANGE_SEC_BASE_HIGH_AW_5 0x336638
+
+#define mmSIF_RTR_CTRL_3_RANGE_SEC_BASE_HIGH_AW_6 0x33663C
+
+#define mmSIF_RTR_CTRL_3_RANGE_SEC_BASE_HIGH_AW_7 0x336640
+
+#define mmSIF_RTR_CTRL_3_RANGE_SEC_BASE_HIGH_AW_8 0x336644
+
+#define mmSIF_RTR_CTRL_3_RANGE_SEC_BASE_HIGH_AW_9 0x336648
+
+#define mmSIF_RTR_CTRL_3_RANGE_SEC_BASE_HIGH_AW_10 0x33664C
+
+#define mmSIF_RTR_CTRL_3_RANGE_SEC_BASE_HIGH_AW_11 0x336650
+
+#define mmSIF_RTR_CTRL_3_RANGE_SEC_BASE_HIGH_AW_12 0x336654
+
+#define mmSIF_RTR_CTRL_3_RANGE_SEC_BASE_HIGH_AW_13 0x336658
+
+#define mmSIF_RTR_CTRL_3_RANGE_SEC_BASE_HIGH_AW_14 0x33665C
+
+#define mmSIF_RTR_CTRL_3_RANGE_SEC_BASE_HIGH_AW_15 0x336660
+
+#define mmSIF_RTR_CTRL_3_RANGE_SEC_MASK_LOW_AW_0 0x336664
+
+#define mmSIF_RTR_CTRL_3_RANGE_SEC_MASK_LOW_AW_1 0x336668
+
+#define mmSIF_RTR_CTRL_3_RANGE_SEC_MASK_LOW_AW_2 0x33666C
+
+#define mmSIF_RTR_CTRL_3_RANGE_SEC_MASK_LOW_AW_3 0x336670
+
+#define mmSIF_RTR_CTRL_3_RANGE_SEC_MASK_LOW_AW_4 0x336674
+
+#define mmSIF_RTR_CTRL_3_RANGE_SEC_MASK_LOW_AW_5 0x336678
+
+#define mmSIF_RTR_CTRL_3_RANGE_SEC_MASK_LOW_AW_6 0x33667C
+
+#define mmSIF_RTR_CTRL_3_RANGE_SEC_MASK_LOW_AW_7 0x336680
+
+#define mmSIF_RTR_CTRL_3_RANGE_SEC_MASK_LOW_AW_8 0x336684
+
+#define mmSIF_RTR_CTRL_3_RANGE_SEC_MASK_LOW_AW_9 0x336688
+
+#define mmSIF_RTR_CTRL_3_RANGE_SEC_MASK_LOW_AW_10 0x33668C
+
+#define mmSIF_RTR_CTRL_3_RANGE_SEC_MASK_LOW_AW_11 0x336690
+
+#define mmSIF_RTR_CTRL_3_RANGE_SEC_MASK_LOW_AW_12 0x336694
+
+#define mmSIF_RTR_CTRL_3_RANGE_SEC_MASK_LOW_AW_13 0x336698
+
+#define mmSIF_RTR_CTRL_3_RANGE_SEC_MASK_LOW_AW_14 0x33669C
+
+#define mmSIF_RTR_CTRL_3_RANGE_SEC_MASK_LOW_AW_15 0x3366A0
+
+#define mmSIF_RTR_CTRL_3_RANGE_SEC_MASK_HIGH_AW_0 0x3366A4
+
+#define mmSIF_RTR_CTRL_3_RANGE_SEC_MASK_HIGH_AW_1 0x3366A8
+
+#define mmSIF_RTR_CTRL_3_RANGE_SEC_MASK_HIGH_AW_2 0x3366AC
+
+#define mmSIF_RTR_CTRL_3_RANGE_SEC_MASK_HIGH_AW_3 0x3366B0
+
+#define mmSIF_RTR_CTRL_3_RANGE_SEC_MASK_HIGH_AW_4 0x3366B4
+
+#define mmSIF_RTR_CTRL_3_RANGE_SEC_MASK_HIGH_AW_5 0x3366B8
+
+#define mmSIF_RTR_CTRL_3_RANGE_SEC_MASK_HIGH_AW_6 0x3366BC
+
+#define mmSIF_RTR_CTRL_3_RANGE_SEC_MASK_HIGH_AW_7 0x3366C0
+
+#define mmSIF_RTR_CTRL_3_RANGE_SEC_MASK_HIGH_AW_8 0x3366C4
+
+#define mmSIF_RTR_CTRL_3_RANGE_SEC_MASK_HIGH_AW_9 0x3366C8
+
+#define mmSIF_RTR_CTRL_3_RANGE_SEC_MASK_HIGH_AW_10 0x3366CC
+
+#define mmSIF_RTR_CTRL_3_RANGE_SEC_MASK_HIGH_AW_11 0x3366D0
+
+#define mmSIF_RTR_CTRL_3_RANGE_SEC_MASK_HIGH_AW_12 0x3366D4
+
+#define mmSIF_RTR_CTRL_3_RANGE_SEC_MASK_HIGH_AW_13 0x3366D8
+
+#define mmSIF_RTR_CTRL_3_RANGE_SEC_MASK_HIGH_AW_14 0x3366DC
+
+#define mmSIF_RTR_CTRL_3_RANGE_SEC_MASK_HIGH_AW_15 0x3366E0
+
+#define mmSIF_RTR_CTRL_3_RANGE_PRIV_BASE_LOW_AW_0 0x3366E4
+
+#define mmSIF_RTR_CTRL_3_RANGE_PRIV_BASE_LOW_AW_1 0x3366E8
+
+#define mmSIF_RTR_CTRL_3_RANGE_PRIV_BASE_LOW_AW_2 0x3366EC
+
+#define mmSIF_RTR_CTRL_3_RANGE_PRIV_BASE_LOW_AW_3 0x3366F0
+
+#define mmSIF_RTR_CTRL_3_RANGE_PRIV_BASE_LOW_AW_4 0x3366F4
+
+#define mmSIF_RTR_CTRL_3_RANGE_PRIV_BASE_LOW_AW_5 0x3366F8
+
+#define mmSIF_RTR_CTRL_3_RANGE_PRIV_BASE_LOW_AW_6 0x3366FC
+
+#define mmSIF_RTR_CTRL_3_RANGE_PRIV_BASE_LOW_AW_7 0x336700
+
+#define mmSIF_RTR_CTRL_3_RANGE_PRIV_BASE_LOW_AW_8 0x336704
+
+#define mmSIF_RTR_CTRL_3_RANGE_PRIV_BASE_LOW_AW_9 0x336708
+
+#define mmSIF_RTR_CTRL_3_RANGE_PRIV_BASE_LOW_AW_10 0x33670C
+
+#define mmSIF_RTR_CTRL_3_RANGE_PRIV_BASE_LOW_AW_11 0x336710
+
+#define mmSIF_RTR_CTRL_3_RANGE_PRIV_BASE_LOW_AW_12 0x336714
+
+#define mmSIF_RTR_CTRL_3_RANGE_PRIV_BASE_LOW_AW_13 0x336718
+
+#define mmSIF_RTR_CTRL_3_RANGE_PRIV_BASE_LOW_AW_14 0x33671C
+
+#define mmSIF_RTR_CTRL_3_RANGE_PRIV_BASE_LOW_AW_15 0x336720
+
+#define mmSIF_RTR_CTRL_3_RANGE_PRIV_BASE_HIGH_AW_0 0x336724
+
+#define mmSIF_RTR_CTRL_3_RANGE_PRIV_BASE_HIGH_AW_1 0x336728
+
+#define mmSIF_RTR_CTRL_3_RANGE_PRIV_BASE_HIGH_AW_2 0x33672C
+
+#define mmSIF_RTR_CTRL_3_RANGE_PRIV_BASE_HIGH_AW_3 0x336730
+
+#define mmSIF_RTR_CTRL_3_RANGE_PRIV_BASE_HIGH_AW_4 0x336734
+
+#define mmSIF_RTR_CTRL_3_RANGE_PRIV_BASE_HIGH_AW_5 0x336738
+
+#define mmSIF_RTR_CTRL_3_RANGE_PRIV_BASE_HIGH_AW_6 0x33673C
+
+#define mmSIF_RTR_CTRL_3_RANGE_PRIV_BASE_HIGH_AW_7 0x336740
+
+#define mmSIF_RTR_CTRL_3_RANGE_PRIV_BASE_HIGH_AW_8 0x336744
+
+#define mmSIF_RTR_CTRL_3_RANGE_PRIV_BASE_HIGH_AW_9 0x336748
+
+#define mmSIF_RTR_CTRL_3_RANGE_PRIV_BASE_HIGH_AW_10 0x33674C
+
+#define mmSIF_RTR_CTRL_3_RANGE_PRIV_BASE_HIGH_AW_11 0x336750
+
+#define mmSIF_RTR_CTRL_3_RANGE_PRIV_BASE_HIGH_AW_12 0x336754
+
+#define mmSIF_RTR_CTRL_3_RANGE_PRIV_BASE_HIGH_AW_13 0x336758
+
+#define mmSIF_RTR_CTRL_3_RANGE_PRIV_BASE_HIGH_AW_14 0x33675C
+
+#define mmSIF_RTR_CTRL_3_RANGE_PRIV_BASE_HIGH_AW_15 0x336760
+
+#define mmSIF_RTR_CTRL_3_RANGE_PRIV_MASK_LOW_AW_0 0x336764
+
+#define mmSIF_RTR_CTRL_3_RANGE_PRIV_MASK_LOW_AW_1 0x336768
+
+#define mmSIF_RTR_CTRL_3_RANGE_PRIV_MASK_LOW_AW_2 0x33676C
+
+#define mmSIF_RTR_CTRL_3_RANGE_PRIV_MASK_LOW_AW_3 0x336770
+
+#define mmSIF_RTR_CTRL_3_RANGE_PRIV_MASK_LOW_AW_4 0x336774
+
+#define mmSIF_RTR_CTRL_3_RANGE_PRIV_MASK_LOW_AW_5 0x336778
+
+#define mmSIF_RTR_CTRL_3_RANGE_PRIV_MASK_LOW_AW_6 0x33677C
+
+#define mmSIF_RTR_CTRL_3_RANGE_PRIV_MASK_LOW_AW_7 0x336780
+
+#define mmSIF_RTR_CTRL_3_RANGE_PRIV_MASK_LOW_AW_8 0x336784
+
+#define mmSIF_RTR_CTRL_3_RANGE_PRIV_MASK_LOW_AW_9 0x336788
+
+#define mmSIF_RTR_CTRL_3_RANGE_PRIV_MASK_LOW_AW_10 0x33678C
+
+#define mmSIF_RTR_CTRL_3_RANGE_PRIV_MASK_LOW_AW_11 0x336790
+
+#define mmSIF_RTR_CTRL_3_RANGE_PRIV_MASK_LOW_AW_12 0x336794
+
+#define mmSIF_RTR_CTRL_3_RANGE_PRIV_MASK_LOW_AW_13 0x336798
+
+#define mmSIF_RTR_CTRL_3_RANGE_PRIV_MASK_LOW_AW_14 0x33679C
+
+#define mmSIF_RTR_CTRL_3_RANGE_PRIV_MASK_LOW_AW_15 0x3367A0
+
+#define mmSIF_RTR_CTRL_3_RANGE_PRIV_MASK_HIGH_AW_0 0x3367A4
+
+#define mmSIF_RTR_CTRL_3_RANGE_PRIV_MASK_HIGH_AW_1 0x3367A8
+
+#define mmSIF_RTR_CTRL_3_RANGE_PRIV_MASK_HIGH_AW_2 0x3367AC
+
+#define mmSIF_RTR_CTRL_3_RANGE_PRIV_MASK_HIGH_AW_3 0x3367B0
+
+#define mmSIF_RTR_CTRL_3_RANGE_PRIV_MASK_HIGH_AW_4 0x3367B4
+
+#define mmSIF_RTR_CTRL_3_RANGE_PRIV_MASK_HIGH_AW_5 0x3367B8
+
+#define mmSIF_RTR_CTRL_3_RANGE_PRIV_MASK_HIGH_AW_6 0x3367BC
+
+#define mmSIF_RTR_CTRL_3_RANGE_PRIV_MASK_HIGH_AW_7 0x3367C0
+
+#define mmSIF_RTR_CTRL_3_RANGE_PRIV_MASK_HIGH_AW_8 0x3367C4
+
+#define mmSIF_RTR_CTRL_3_RANGE_PRIV_MASK_HIGH_AW_9 0x3367C8
+
+#define mmSIF_RTR_CTRL_3_RANGE_PRIV_MASK_HIGH_AW_10 0x3367CC
+
+#define mmSIF_RTR_CTRL_3_RANGE_PRIV_MASK_HIGH_AW_11 0x3367D0
+
+#define mmSIF_RTR_CTRL_3_RANGE_PRIV_MASK_HIGH_AW_12 0x3367D4
+
+#define mmSIF_RTR_CTRL_3_RANGE_PRIV_MASK_HIGH_AW_13 0x3367D8
+
+#define mmSIF_RTR_CTRL_3_RANGE_PRIV_MASK_HIGH_AW_14 0x3367DC
+
+#define mmSIF_RTR_CTRL_3_RANGE_PRIV_MASK_HIGH_AW_15 0x3367E0
+
+#define mmSIF_RTR_CTRL_3_RANGE_SEC_BASE_LOW_AR_0 0x336824
+
+#define mmSIF_RTR_CTRL_3_RANGE_SEC_BASE_LOW_AR_1 0x336828
+
+#define mmSIF_RTR_CTRL_3_RANGE_SEC_BASE_LOW_AR_2 0x33682C
+
+#define mmSIF_RTR_CTRL_3_RANGE_SEC_BASE_LOW_AR_3 0x336830
+
+#define mmSIF_RTR_CTRL_3_RANGE_SEC_BASE_LOW_AR_4 0x336834
+
+#define mmSIF_RTR_CTRL_3_RANGE_SEC_BASE_LOW_AR_5 0x336838
+
+#define mmSIF_RTR_CTRL_3_RANGE_SEC_BASE_LOW_AR_6 0x33683C
+
+#define mmSIF_RTR_CTRL_3_RANGE_SEC_BASE_LOW_AR_7 0x336840
+
+#define mmSIF_RTR_CTRL_3_RANGE_SEC_BASE_LOW_AR_8 0x336844
+
+#define mmSIF_RTR_CTRL_3_RANGE_SEC_BASE_LOW_AR_9 0x336848
+
+#define mmSIF_RTR_CTRL_3_RANGE_SEC_BASE_LOW_AR_10 0x33684C
+
+#define mmSIF_RTR_CTRL_3_RANGE_SEC_BASE_LOW_AR_11 0x336850
+
+#define mmSIF_RTR_CTRL_3_RANGE_SEC_BASE_LOW_AR_12 0x336854
+
+#define mmSIF_RTR_CTRL_3_RANGE_SEC_BASE_LOW_AR_13 0x336858
+
+#define mmSIF_RTR_CTRL_3_RANGE_SEC_BASE_LOW_AR_14 0x33685C
+
+#define mmSIF_RTR_CTRL_3_RANGE_SEC_BASE_LOW_AR_15 0x336860
+
+#define mmSIF_RTR_CTRL_3_RANGE_SEC_BASE_HIGH_AR_0 0x336864
+
+#define mmSIF_RTR_CTRL_3_RANGE_SEC_BASE_HIGH_AR_1 0x336868
+
+#define mmSIF_RTR_CTRL_3_RANGE_SEC_BASE_HIGH_AR_2 0x33686C
+
+#define mmSIF_RTR_CTRL_3_RANGE_SEC_BASE_HIGH_AR_3 0x336870
+
+#define mmSIF_RTR_CTRL_3_RANGE_SEC_BASE_HIGH_AR_4 0x336874
+
+#define mmSIF_RTR_CTRL_3_RANGE_SEC_BASE_HIGH_AR_5 0x336878
+
+#define mmSIF_RTR_CTRL_3_RANGE_SEC_BASE_HIGH_AR_6 0x33687C
+
+#define mmSIF_RTR_CTRL_3_RANGE_SEC_BASE_HIGH_AR_7 0x336880
+
+#define mmSIF_RTR_CTRL_3_RANGE_SEC_BASE_HIGH_AR_8 0x336884
+
+#define mmSIF_RTR_CTRL_3_RANGE_SEC_BASE_HIGH_AR_9 0x336888
+
+#define mmSIF_RTR_CTRL_3_RANGE_SEC_BASE_HIGH_AR_10 0x33688C
+
+#define mmSIF_RTR_CTRL_3_RANGE_SEC_BASE_HIGH_AR_11 0x336890
+
+#define mmSIF_RTR_CTRL_3_RANGE_SEC_BASE_HIGH_AR_12 0x336894
+
+#define mmSIF_RTR_CTRL_3_RANGE_SEC_BASE_HIGH_AR_13 0x336898
+
+#define mmSIF_RTR_CTRL_3_RANGE_SEC_BASE_HIGH_AR_14 0x33689C
+
+#define mmSIF_RTR_CTRL_3_RANGE_SEC_BASE_HIGH_AR_15 0x3368A0
+
+#define mmSIF_RTR_CTRL_3_RANGE_SEC_MASK_LOW_AR_0 0x3368A4
+
+#define mmSIF_RTR_CTRL_3_RANGE_SEC_MASK_LOW_AR_1 0x3368A8
+
+#define mmSIF_RTR_CTRL_3_RANGE_SEC_MASK_LOW_AR_2 0x3368AC
+
+#define mmSIF_RTR_CTRL_3_RANGE_SEC_MASK_LOW_AR_3 0x3368B0
+
+#define mmSIF_RTR_CTRL_3_RANGE_SEC_MASK_LOW_AR_4 0x3368B4
+
+#define mmSIF_RTR_CTRL_3_RANGE_SEC_MASK_LOW_AR_5 0x3368B8
+
+#define mmSIF_RTR_CTRL_3_RANGE_SEC_MASK_LOW_AR_6 0x3368BC
+
+#define mmSIF_RTR_CTRL_3_RANGE_SEC_MASK_LOW_AR_7 0x3368C0
+
+#define mmSIF_RTR_CTRL_3_RANGE_SEC_MASK_LOW_AR_8 0x3368C4
+
+#define mmSIF_RTR_CTRL_3_RANGE_SEC_MASK_LOW_AR_9 0x3368C8
+
+#define mmSIF_RTR_CTRL_3_RANGE_SEC_MASK_LOW_AR_10 0x3368CC
+
+#define mmSIF_RTR_CTRL_3_RANGE_SEC_MASK_LOW_AR_11 0x3368D0
+
+#define mmSIF_RTR_CTRL_3_RANGE_SEC_MASK_LOW_AR_12 0x3368D4
+
+#define mmSIF_RTR_CTRL_3_RANGE_SEC_MASK_LOW_AR_13 0x3368D8
+
+#define mmSIF_RTR_CTRL_3_RANGE_SEC_MASK_LOW_AR_14 0x3368DC
+
+#define mmSIF_RTR_CTRL_3_RANGE_SEC_MASK_LOW_AR_15 0x3368E0
+
+#define mmSIF_RTR_CTRL_3_RANGE_SEC_MASK_HIGH_AR_0 0x3368E4
+
+#define mmSIF_RTR_CTRL_3_RANGE_SEC_MASK_HIGH_AR_1 0x3368E8
+
+#define mmSIF_RTR_CTRL_3_RANGE_SEC_MASK_HIGH_AR_2 0x3368EC
+
+#define mmSIF_RTR_CTRL_3_RANGE_SEC_MASK_HIGH_AR_3 0x3368F0
+
+#define mmSIF_RTR_CTRL_3_RANGE_SEC_MASK_HIGH_AR_4 0x3368F4
+
+#define mmSIF_RTR_CTRL_3_RANGE_SEC_MASK_HIGH_AR_5 0x3368F8
+
+#define mmSIF_RTR_CTRL_3_RANGE_SEC_MASK_HIGH_AR_6 0x3368FC
+
+#define mmSIF_RTR_CTRL_3_RANGE_SEC_MASK_HIGH_AR_7 0x336900
+
+#define mmSIF_RTR_CTRL_3_RANGE_SEC_MASK_HIGH_AR_8 0x336904
+
+#define mmSIF_RTR_CTRL_3_RANGE_SEC_MASK_HIGH_AR_9 0x336908
+
+#define mmSIF_RTR_CTRL_3_RANGE_SEC_MASK_HIGH_AR_10 0x33690C
+
+#define mmSIF_RTR_CTRL_3_RANGE_SEC_MASK_HIGH_AR_11 0x336910
+
+#define mmSIF_RTR_CTRL_3_RANGE_SEC_MASK_HIGH_AR_12 0x336914
+
+#define mmSIF_RTR_CTRL_3_RANGE_SEC_MASK_HIGH_AR_13 0x336918
+
+#define mmSIF_RTR_CTRL_3_RANGE_SEC_MASK_HIGH_AR_14 0x33691C
+
+#define mmSIF_RTR_CTRL_3_RANGE_SEC_MASK_HIGH_AR_15 0x336920
+
+#define mmSIF_RTR_CTRL_3_RANGE_PRIV_BASE_LOW_AR_0 0x336924
+
+#define mmSIF_RTR_CTRL_3_RANGE_PRIV_BASE_LOW_AR_1 0x336928
+
+#define mmSIF_RTR_CTRL_3_RANGE_PRIV_BASE_LOW_AR_2 0x33692C
+
+#define mmSIF_RTR_CTRL_3_RANGE_PRIV_BASE_LOW_AR_3 0x336930
+
+#define mmSIF_RTR_CTRL_3_RANGE_PRIV_BASE_LOW_AR_4 0x336934
+
+#define mmSIF_RTR_CTRL_3_RANGE_PRIV_BASE_LOW_AR_5 0x336938
+
+#define mmSIF_RTR_CTRL_3_RANGE_PRIV_BASE_LOW_AR_6 0x33693C
+
+#define mmSIF_RTR_CTRL_3_RANGE_PRIV_BASE_LOW_AR_7 0x336940
+
+#define mmSIF_RTR_CTRL_3_RANGE_PRIV_BASE_LOW_AR_8 0x336944
+
+#define mmSIF_RTR_CTRL_3_RANGE_PRIV_BASE_LOW_AR_9 0x336948
+
+#define mmSIF_RTR_CTRL_3_RANGE_PRIV_BASE_LOW_AR_10 0x33694C
+
+#define mmSIF_RTR_CTRL_3_RANGE_PRIV_BASE_LOW_AR_11 0x336950
+
+#define mmSIF_RTR_CTRL_3_RANGE_PRIV_BASE_LOW_AR_12 0x336954
+
+#define mmSIF_RTR_CTRL_3_RANGE_PRIV_BASE_LOW_AR_13 0x336958
+
+#define mmSIF_RTR_CTRL_3_RANGE_PRIV_BASE_LOW_AR_14 0x33695C
+
+#define mmSIF_RTR_CTRL_3_RANGE_PRIV_BASE_LOW_AR_15 0x336960
+
+#define mmSIF_RTR_CTRL_3_RANGE_PRIV_BASE_HIGH_AR_0 0x336964
+
+#define mmSIF_RTR_CTRL_3_RANGE_PRIV_BASE_HIGH_AR_1 0x336968
+
+#define mmSIF_RTR_CTRL_3_RANGE_PRIV_BASE_HIGH_AR_2 0x33696C
+
+#define mmSIF_RTR_CTRL_3_RANGE_PRIV_BASE_HIGH_AR_3 0x336970
+
+#define mmSIF_RTR_CTRL_3_RANGE_PRIV_BASE_HIGH_AR_4 0x336974
+
+#define mmSIF_RTR_CTRL_3_RANGE_PRIV_BASE_HIGH_AR_5 0x336978
+
+#define mmSIF_RTR_CTRL_3_RANGE_PRIV_BASE_HIGH_AR_6 0x33697C
+
+#define mmSIF_RTR_CTRL_3_RANGE_PRIV_BASE_HIGH_AR_7 0x336980
+
+#define mmSIF_RTR_CTRL_3_RANGE_PRIV_BASE_HIGH_AR_8 0x336984
+
+#define mmSIF_RTR_CTRL_3_RANGE_PRIV_BASE_HIGH_AR_9 0x336988
+
+#define mmSIF_RTR_CTRL_3_RANGE_PRIV_BASE_HIGH_AR_10 0x33698C
+
+#define mmSIF_RTR_CTRL_3_RANGE_PRIV_BASE_HIGH_AR_11 0x336990
+
+#define mmSIF_RTR_CTRL_3_RANGE_PRIV_BASE_HIGH_AR_12 0x336994
+
+#define mmSIF_RTR_CTRL_3_RANGE_PRIV_BASE_HIGH_AR_13 0x336998
+
+#define mmSIF_RTR_CTRL_3_RANGE_PRIV_BASE_HIGH_AR_14 0x33699C
+
+#define mmSIF_RTR_CTRL_3_RANGE_PRIV_BASE_HIGH_AR_15 0x3369A0
+
+#define mmSIF_RTR_CTRL_3_RANGE_PRIV_MASK_LOW_AR_0 0x3369A4
+
+#define mmSIF_RTR_CTRL_3_RANGE_PRIV_MASK_LOW_AR_1 0x3369A8
+
+#define mmSIF_RTR_CTRL_3_RANGE_PRIV_MASK_LOW_AR_2 0x3369AC
+
+#define mmSIF_RTR_CTRL_3_RANGE_PRIV_MASK_LOW_AR_3 0x3369B0
+
+#define mmSIF_RTR_CTRL_3_RANGE_PRIV_MASK_LOW_AR_4 0x3369B4
+
+#define mmSIF_RTR_CTRL_3_RANGE_PRIV_MASK_LOW_AR_5 0x3369B8
+
+#define mmSIF_RTR_CTRL_3_RANGE_PRIV_MASK_LOW_AR_6 0x3369BC
+
+#define mmSIF_RTR_CTRL_3_RANGE_PRIV_MASK_LOW_AR_7 0x3369C0
+
+#define mmSIF_RTR_CTRL_3_RANGE_PRIV_MASK_LOW_AR_8 0x3369C4
+
+#define mmSIF_RTR_CTRL_3_RANGE_PRIV_MASK_LOW_AR_9 0x3369C8
+
+#define mmSIF_RTR_CTRL_3_RANGE_PRIV_MASK_LOW_AR_10 0x3369CC
+
+#define mmSIF_RTR_CTRL_3_RANGE_PRIV_MASK_LOW_AR_11 0x3369D0
+
+#define mmSIF_RTR_CTRL_3_RANGE_PRIV_MASK_LOW_AR_12 0x3369D4
+
+#define mmSIF_RTR_CTRL_3_RANGE_PRIV_MASK_LOW_AR_13 0x3369D8
+
+#define mmSIF_RTR_CTRL_3_RANGE_PRIV_MASK_LOW_AR_14 0x3369DC
+
+#define mmSIF_RTR_CTRL_3_RANGE_PRIV_MASK_LOW_AR_15 0x3369E0
+
+#define mmSIF_RTR_CTRL_3_RANGE_PRIV_MASK_HIGH_AR_0 0x3369E4
+
+#define mmSIF_RTR_CTRL_3_RANGE_PRIV_MASK_HIGH_AR_1 0x3369E8
+
+#define mmSIF_RTR_CTRL_3_RANGE_PRIV_MASK_HIGH_AR_2 0x3369EC
+
+#define mmSIF_RTR_CTRL_3_RANGE_PRIV_MASK_HIGH_AR_3 0x3369F0
+
+#define mmSIF_RTR_CTRL_3_RANGE_PRIV_MASK_HIGH_AR_4 0x3369F4
+
+#define mmSIF_RTR_CTRL_3_RANGE_PRIV_MASK_HIGH_AR_5 0x3369F8
+
+#define mmSIF_RTR_CTRL_3_RANGE_PRIV_MASK_HIGH_AR_6 0x3369FC
+
+#define mmSIF_RTR_CTRL_3_RANGE_PRIV_MASK_HIGH_AR_7 0x336A00
+
+#define mmSIF_RTR_CTRL_3_RANGE_PRIV_MASK_HIGH_AR_8 0x336A04
+
+#define mmSIF_RTR_CTRL_3_RANGE_PRIV_MASK_HIGH_AR_9 0x336A08
+
+#define mmSIF_RTR_CTRL_3_RANGE_PRIV_MASK_HIGH_AR_10 0x336A0C
+
+#define mmSIF_RTR_CTRL_3_RANGE_PRIV_MASK_HIGH_AR_11 0x336A10
+
+#define mmSIF_RTR_CTRL_3_RANGE_PRIV_MASK_HIGH_AR_12 0x336A14
+
+#define mmSIF_RTR_CTRL_3_RANGE_PRIV_MASK_HIGH_AR_13 0x336A18
+
+#define mmSIF_RTR_CTRL_3_RANGE_PRIV_MASK_HIGH_AR_14 0x336A1C
+
+#define mmSIF_RTR_CTRL_3_RANGE_PRIV_MASK_HIGH_AR_15 0x336A20
+
+#define mmSIF_RTR_CTRL_3_RANGE_SEC_HIT_AW 0x336A64
+
+#define mmSIF_RTR_CTRL_3_RANGE_SEC_HIT_AR 0x336A68
+
+#define mmSIF_RTR_CTRL_3_RANGE_PRIV_HIT_AW 0x336A6C
+
+#define mmSIF_RTR_CTRL_3_RANGE_PRIV_HIT_AR 0x336A70
+
+#define mmSIF_RTR_CTRL_3_RGL_CFG 0x336B64
+
+#define mmSIF_RTR_CTRL_3_RGL_SHIFT 0x336B68
+
+#define mmSIF_RTR_CTRL_3_RGL_EXPECTED_LAT_0 0x336B6C
+
+#define mmSIF_RTR_CTRL_3_RGL_EXPECTED_LAT_1 0x336B70
+
+#define mmSIF_RTR_CTRL_3_RGL_EXPECTED_LAT_2 0x336B74
+
+#define mmSIF_RTR_CTRL_3_RGL_EXPECTED_LAT_3 0x336B78
+
+#define mmSIF_RTR_CTRL_3_RGL_EXPECTED_LAT_4 0x336B7C
+
+#define mmSIF_RTR_CTRL_3_RGL_EXPECTED_LAT_5 0x336B80
+
+#define mmSIF_RTR_CTRL_3_RGL_EXPECTED_LAT_6 0x336B84
+
+#define mmSIF_RTR_CTRL_3_RGL_EXPECTED_LAT_7 0x336B88
+
+#define mmSIF_RTR_CTRL_3_RGL_TOKEN_0 0x336BAC
+
+#define mmSIF_RTR_CTRL_3_RGL_TOKEN_1 0x336BB0
+
+#define mmSIF_RTR_CTRL_3_RGL_TOKEN_2 0x336BB4
+
+#define mmSIF_RTR_CTRL_3_RGL_TOKEN_3 0x336BB8
+
+#define mmSIF_RTR_CTRL_3_RGL_TOKEN_4 0x336BBC
+
+#define mmSIF_RTR_CTRL_3_RGL_TOKEN_5 0x336BC0
+
+#define mmSIF_RTR_CTRL_3_RGL_TOKEN_6 0x336BC4
+
+#define mmSIF_RTR_CTRL_3_RGL_TOKEN_7 0x336BC8
+
+#define mmSIF_RTR_CTRL_3_RGL_BANK_ID_0 0x336BEC
+
+#define mmSIF_RTR_CTRL_3_RGL_BANK_ID_1 0x336BF0
+
+#define mmSIF_RTR_CTRL_3_RGL_BANK_ID_2 0x336BF4
+
+#define mmSIF_RTR_CTRL_3_RGL_BANK_ID_3 0x336BF8
+
+#define mmSIF_RTR_CTRL_3_RGL_BANK_ID_4 0x336BFC
+
+#define mmSIF_RTR_CTRL_3_RGL_BANK_ID_5 0x336C00
+
+#define mmSIF_RTR_CTRL_3_RGL_BANK_ID_6 0x336C04
+
+#define mmSIF_RTR_CTRL_3_RGL_BANK_ID_7 0x336C08
+
+#define mmSIF_RTR_CTRL_3_RGL_WDT 0x336C2C
+
+#define mmSIF_RTR_CTRL_3_E2E_AR_HBM0_CH0_CTR_WRAP 0x336C30
+
+#define mmSIF_RTR_CTRL_3_E2E_AR_HBM0_CH1_CTR_WRAP 0x336C34
+
+#define mmSIF_RTR_CTRL_3_E2E_AR_HBM1_CH0_CTR_WRAP 0x336C38
+
+#define mmSIF_RTR_CTRL_3_E2E_AR_HBM1_CH1_CTR_WRAP 0x336C3C
+
+#define mmSIF_RTR_CTRL_3_E2E_AR_HBM2_CH0_CTR_WRAP 0x336C40
+
+#define mmSIF_RTR_CTRL_3_E2E_AR_HBM2_CH1_CTR_WRAP 0x336C44
+
+#define mmSIF_RTR_CTRL_3_E2E_AR_HBM3_CH0_CTR_WRAP 0x336C48
+
+#define mmSIF_RTR_CTRL_3_E2E_AR_HBM3_CH1_CTR_WRAP 0x336C4C
+
+#define mmSIF_RTR_CTRL_3_E2E_AR_HBM0_CH0_CTR_CNT 0x336C50
+
+#define mmSIF_RTR_CTRL_3_E2E_AR_HBM0_CH1_CTR_CNT 0x336C54
+
+#define mmSIF_RTR_CTRL_3_E2E_AR_HBM1_CH0_CTR_CNT 0x336C58
+
+#define mmSIF_RTR_CTRL_3_E2E_AR_HBM1_CH1_CTR_CNT 0x336C5C
+
+#define mmSIF_RTR_CTRL_3_E2E_AR_HBM2_CH0_CTR_CNT 0x336C60
+
+#define mmSIF_RTR_CTRL_3_E2E_AR_HBM2_CH1_CTR_CNT 0x336C64
+
+#define mmSIF_RTR_CTRL_3_E2E_AR_HBM3_CH0_CTR_CNT 0x336C68
+
+#define mmSIF_RTR_CTRL_3_E2E_AR_HBM3_CH1_CTR_CNT 0x336C6C
+
+#define mmSIF_RTR_CTRL_3_E2E_AW_HBM0_CH0_CTR_WRAP 0x336C70
+
+#define mmSIF_RTR_CTRL_3_E2E_AW_HBM0_CH1_CTR_WRAP 0x336C74
+
+#define mmSIF_RTR_CTRL_3_E2E_AW_HBM1_CH0_CTR_WRAP 0x336C78
+
+#define mmSIF_RTR_CTRL_3_E2E_AW_HBM1_CH1_CTR_WRAP 0x336C7C
+
+#define mmSIF_RTR_CTRL_3_E2E_AW_HBM2_CH0_CTR_WRAP 0x336C80
+
+#define mmSIF_RTR_CTRL_3_E2E_AW_HBM2_CH1_CTR_WRAP 0x336C84
+
+#define mmSIF_RTR_CTRL_3_E2E_AW_HBM3_CH0_CTR_WRAP 0x336C88
+
+#define mmSIF_RTR_CTRL_3_E2E_AW_HBM3_CH1_CTR_WRAP 0x336C8C
+
+#define mmSIF_RTR_CTRL_3_E2E_AW_HBM0_CH0_CTR_CNT 0x336C90
+
+#define mmSIF_RTR_CTRL_3_E2E_AW_HBM0_CH1_CTR_CNT 0x336C94
+
+#define mmSIF_RTR_CTRL_3_E2E_AW_HBM1_CH0_CTR_CNT 0x336C98
+
+#define mmSIF_RTR_CTRL_3_E2E_AW_HBM1_CH1_CTR_CNT 0x336C9C
+
+#define mmSIF_RTR_CTRL_3_E2E_AW_HBM2_CH0_CTR_CNT 0x336CA0
+
+#define mmSIF_RTR_CTRL_3_E2E_AW_HBM2_CH1_CTR_CNT 0x336CA4
+
+#define mmSIF_RTR_CTRL_3_E2E_AW_HBM3_CH0_CTR_CNT 0x336CA8
+
+#define mmSIF_RTR_CTRL_3_E2E_AW_HBM3_CH1_CTR_CNT 0x336CAC
+
+#define mmSIF_RTR_CTRL_3_NL_HBM_PC_SEL_0 0x336CB0
+
+#define mmSIF_RTR_CTRL_3_NL_HBM_PC_SEL_1 0x336CB4
+
+#define mmSIF_RTR_CTRL_3_NL_HBM_PC_SEL_2 0x336CB8
+
+#define mmSIF_RTR_CTRL_3_NL_HBM_PC_SEL_3 0x336CBC
+
+#endif /* ASIC_REG_SIF_RTR_CTRL_3_REGS_H_ */
diff --git a/drivers/accel/habanalabs/include/gaudi/asic_reg/sif_rtr_ctrl_4_regs.h b/drivers/accel/habanalabs/include/gaudi/asic_reg/sif_rtr_ctrl_4_regs.h
new file mode 100644
index 0000000000..ad48773c4b
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi/asic_reg/sif_rtr_ctrl_4_regs.h
@@ -0,0 +1,896 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2016-2018 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ ** DO NOT EDIT BELOW **
+ ************************************/
+
+#ifndef ASIC_REG_SIF_RTR_CTRL_4_REGS_H_
+#define ASIC_REG_SIF_RTR_CTRL_4_REGS_H_
+
+/*
+ *****************************************
+ * SIF_RTR_CTRL_4 (Prototype: RTR_CTRL)
+ *****************************************
+ */
+
+#define mmSIF_RTR_CTRL_4_PERM_SEL 0x346108
+
+#define mmSIF_RTR_CTRL_4_HBM_POLY_H3_0 0x346114
+
+#define mmSIF_RTR_CTRL_4_HBM_POLY_H3_1 0x346118
+
+#define mmSIF_RTR_CTRL_4_HBM_POLY_H3_2 0x34611C
+
+#define mmSIF_RTR_CTRL_4_HBM_POLY_H3_3 0x346120
+
+#define mmSIF_RTR_CTRL_4_HBM_POLY_H3_4 0x346124
+
+#define mmSIF_RTR_CTRL_4_HBM_POLY_H3_5 0x346128
+
+#define mmSIF_RTR_CTRL_4_HBM_POLY_H3_6 0x34612C
+
+#define mmSIF_RTR_CTRL_4_HBM_POLY_H3_7 0x346130
+
+#define mmSIF_RTR_CTRL_4_HBM_POLY_H3_8 0x346134
+
+#define mmSIF_RTR_CTRL_4_HBM_POLY_H3_9 0x346138
+
+#define mmSIF_RTR_CTRL_4_HBM_POLY_H3_10 0x34613C
+
+#define mmSIF_RTR_CTRL_4_HBM_POLY_H3_11 0x346140
+
+#define mmSIF_RTR_CTRL_4_HBM_POLY_H3_12 0x346144
+
+#define mmSIF_RTR_CTRL_4_HBM_POLY_H3_13 0x346148
+
+#define mmSIF_RTR_CTRL_4_HBM_POLY_H3_14 0x34614C
+
+#define mmSIF_RTR_CTRL_4_HBM_POLY_H3_15 0x346150
+
+#define mmSIF_RTR_CTRL_4_HBM_POLY_H3_16 0x346154
+
+#define mmSIF_RTR_CTRL_4_HBM_POLY_H3_17 0x346158
+
+#define mmSIF_RTR_CTRL_4_HBM_POLY_H3_18 0x34615C
+
+#define mmSIF_RTR_CTRL_4_HBM_POLY_H3_19 0x346160
+
+#define mmSIF_RTR_CTRL_4_HBM_POLY_H3_20 0x346164
+
+#define mmSIF_RTR_CTRL_4_HBM_POLY_H3_21 0x346168
+
+#define mmSIF_RTR_CTRL_4_HBM_POLY_H3_22 0x34616C
+
+#define mmSIF_RTR_CTRL_4_HBM_POLY_H3_23 0x346170
+
+#define mmSIF_RTR_CTRL_4_HBM_POLY_H3_24 0x346174
+
+#define mmSIF_RTR_CTRL_4_HBM_POLY_H3_25 0x346178
+
+#define mmSIF_RTR_CTRL_4_HBM_POLY_H3_26 0x34617C
+
+#define mmSIF_RTR_CTRL_4_HBM_POLY_H3_27 0x346180
+
+#define mmSIF_RTR_CTRL_4_SRAM_POLY_H3_0 0x346184
+
+#define mmSIF_RTR_CTRL_4_SRAM_POLY_H3_1 0x346188
+
+#define mmSIF_RTR_CTRL_4_SRAM_POLY_H3_2 0x34618C
+
+#define mmSIF_RTR_CTRL_4_SRAM_POLY_H3_3 0x346190
+
+#define mmSIF_RTR_CTRL_4_SRAM_POLY_H3_4 0x346194
+
+#define mmSIF_RTR_CTRL_4_SRAM_POLY_H3_5 0x346198
+
+#define mmSIF_RTR_CTRL_4_SRAM_POLY_H3_6 0x34619C
+
+#define mmSIF_RTR_CTRL_4_SRAM_POLY_H3_7 0x3461A0
+
+#define mmSIF_RTR_CTRL_4_SRAM_POLY_H3_8 0x3461A4
+
+#define mmSIF_RTR_CTRL_4_SRAM_POLY_H3_9 0x3461A8
+
+#define mmSIF_RTR_CTRL_4_SRAM_POLY_H3_10 0x3461AC
+
+#define mmSIF_RTR_CTRL_4_SRAM_POLY_H3_11 0x3461B0
+
+#define mmSIF_RTR_CTRL_4_SRAM_POLY_H3_12 0x3461B4
+
+#define mmSIF_RTR_CTRL_4_SRAM_POLY_H3_13 0x3461B8
+
+#define mmSIF_RTR_CTRL_4_SRAM_POLY_H3_14 0x3461BC
+
+#define mmSIF_RTR_CTRL_4_SCRAM_SRAM_EN 0x34626C
+
+#define mmSIF_RTR_CTRL_4_RL_HBM_EN 0x346274
+
+#define mmSIF_RTR_CTRL_4_RL_HBM_SAT 0x346278
+
+#define mmSIF_RTR_CTRL_4_RL_HBM_RST 0x34627C
+
+#define mmSIF_RTR_CTRL_4_RL_HBM_TIMEOUT 0x346280
+
+#define mmSIF_RTR_CTRL_4_SCRAM_HBM_EN 0x346284
+
+#define mmSIF_RTR_CTRL_4_RL_PCI_EN 0x346288
+
+#define mmSIF_RTR_CTRL_4_RL_PCI_SAT 0x34628C
+
+#define mmSIF_RTR_CTRL_4_RL_PCI_RST 0x346290
+
+#define mmSIF_RTR_CTRL_4_RL_PCI_TIMEOUT 0x346294
+
+#define mmSIF_RTR_CTRL_4_RL_SRAM_EN 0x34629C
+
+#define mmSIF_RTR_CTRL_4_RL_SRAM_SAT 0x3462A0
+
+#define mmSIF_RTR_CTRL_4_RL_SRAM_RST 0x3462A4
+
+#define mmSIF_RTR_CTRL_4_RL_SRAM_TIMEOUT 0x3462AC
+
+#define mmSIF_RTR_CTRL_4_RL_SRAM_RED 0x3462B4
+
+#define mmSIF_RTR_CTRL_4_E2E_HBM_EN 0x3462EC
+
+#define mmSIF_RTR_CTRL_4_E2E_PCI_EN 0x3462F0
+
+#define mmSIF_RTR_CTRL_4_E2E_HBM_WR_SIZE 0x3462F4
+
+#define mmSIF_RTR_CTRL_4_E2E_PCI_WR_SIZE 0x3462F8
+
+#define mmSIF_RTR_CTRL_4_E2E_AW_PCI_CTR_SET_EN 0x346404
+
+#define mmSIF_RTR_CTRL_4_E2E_AW_PCI_CTR_SET 0x346408
+
+#define mmSIF_RTR_CTRL_4_E2E_AW_PCI_CTR_WRAP 0x34640C
+
+#define mmSIF_RTR_CTRL_4_E2E_AW_PCI_CTR_CNT 0x346410
+
+#define mmSIF_RTR_CTRL_4_E2E_AW_HBM_CTR_SET_EN 0x346414
+
+#define mmSIF_RTR_CTRL_4_E2E_AW_HBM_CTR_SET 0x346418
+
+#define mmSIF_RTR_CTRL_4_E2E_HBM_RD_SIZE 0x34641C
+
+#define mmSIF_RTR_CTRL_4_E2E_PCI_RD_SIZE 0x346420
+
+#define mmSIF_RTR_CTRL_4_E2E_AR_PCI_CTR_SET_EN 0x346424
+
+#define mmSIF_RTR_CTRL_4_E2E_AR_PCI_CTR_SET 0x346428
+
+#define mmSIF_RTR_CTRL_4_E2E_AR_PCI_CTR_WRAP 0x34642C
+
+#define mmSIF_RTR_CTRL_4_E2E_AR_PCI_CTR_CNT 0x346430
+
+#define mmSIF_RTR_CTRL_4_E2E_AR_HBM_CTR_SET_EN 0x346434
+
+#define mmSIF_RTR_CTRL_4_E2E_AR_HBM_CTR_SET 0x346438
+
+#define mmSIF_RTR_CTRL_4_NL_HBM_SEL_0 0x346450
+
+#define mmSIF_RTR_CTRL_4_NL_HBM_SEL_1 0x346454
+
+#define mmSIF_RTR_CTRL_4_NON_LIN_EN 0x346480
+
+#define mmSIF_RTR_CTRL_4_NL_SRAM_BANK_0 0x346500
+
+#define mmSIF_RTR_CTRL_4_NL_SRAM_BANK_1 0x346504
+
+#define mmSIF_RTR_CTRL_4_NL_SRAM_BANK_2 0x346508
+
+#define mmSIF_RTR_CTRL_4_NL_SRAM_BANK_3 0x34650C
+
+#define mmSIF_RTR_CTRL_4_NL_SRAM_BANK_4 0x346510
+
+#define mmSIF_RTR_CTRL_4_NL_SRAM_OFFSET_0 0x346514
+
+#define mmSIF_RTR_CTRL_4_NL_SRAM_OFFSET_1 0x346520
+
+#define mmSIF_RTR_CTRL_4_NL_SRAM_OFFSET_2 0x346524
+
+#define mmSIF_RTR_CTRL_4_NL_SRAM_OFFSET_3 0x346528
+
+#define mmSIF_RTR_CTRL_4_NL_SRAM_OFFSET_4 0x34652C
+
+#define mmSIF_RTR_CTRL_4_NL_SRAM_OFFSET_5 0x346530
+
+#define mmSIF_RTR_CTRL_4_NL_SRAM_OFFSET_6 0x346534
+
+#define mmSIF_RTR_CTRL_4_NL_SRAM_OFFSET_7 0x346538
+
+#define mmSIF_RTR_CTRL_4_NL_SRAM_OFFSET_8 0x34653C
+
+#define mmSIF_RTR_CTRL_4_NL_SRAM_OFFSET_9 0x346540
+
+#define mmSIF_RTR_CTRL_4_NL_HBM_OFFSET_0 0x346550
+
+#define mmSIF_RTR_CTRL_4_NL_HBM_OFFSET_1 0x346554
+
+#define mmSIF_RTR_CTRL_4_NL_HBM_OFFSET_2 0x346558
+
+#define mmSIF_RTR_CTRL_4_NL_HBM_OFFSET_3 0x34655C
+
+#define mmSIF_RTR_CTRL_4_NL_HBM_OFFSET_4 0x346560
+
+#define mmSIF_RTR_CTRL_4_NL_HBM_OFFSET_5 0x346564
+
+#define mmSIF_RTR_CTRL_4_NL_HBM_OFFSET_6 0x346568
+
+#define mmSIF_RTR_CTRL_4_NL_HBM_OFFSET_7 0x34656C
+
+#define mmSIF_RTR_CTRL_4_NL_HBM_OFFSET_8 0x346570
+
+#define mmSIF_RTR_CTRL_4_NL_HBM_OFFSET_9 0x346574
+
+#define mmSIF_RTR_CTRL_4_NL_HBM_OFFSET_10 0x346578
+
+#define mmSIF_RTR_CTRL_4_NL_HBM_OFFSET_11 0x34657C
+
+#define mmSIF_RTR_CTRL_4_NL_HBM_OFFSET_12 0x346580
+
+#define mmSIF_RTR_CTRL_4_NL_HBM_OFFSET_13 0x346584
+
+#define mmSIF_RTR_CTRL_4_NL_HBM_OFFSET_14 0x346588
+
+#define mmSIF_RTR_CTRL_4_NL_HBM_OFFSET_15 0x34658C
+
+#define mmSIF_RTR_CTRL_4_NL_HBM_OFFSET_16 0x346590
+
+#define mmSIF_RTR_CTRL_4_NL_HBM_OFFSET_17 0x346594
+
+#define mmSIF_RTR_CTRL_4_NL_HBM_OFFSET_18 0x346598
+
+#define mmSIF_RTR_CTRL_4_RANGE_SEC_BASE_LOW_AW_0 0x3465E4
+
+#define mmSIF_RTR_CTRL_4_RANGE_SEC_BASE_LOW_AW_1 0x3465E8
+
+#define mmSIF_RTR_CTRL_4_RANGE_SEC_BASE_LOW_AW_2 0x3465EC
+
+#define mmSIF_RTR_CTRL_4_RANGE_SEC_BASE_LOW_AW_3 0x3465F0
+
+#define mmSIF_RTR_CTRL_4_RANGE_SEC_BASE_LOW_AW_4 0x3465F4
+
+#define mmSIF_RTR_CTRL_4_RANGE_SEC_BASE_LOW_AW_5 0x3465F8
+
+#define mmSIF_RTR_CTRL_4_RANGE_SEC_BASE_LOW_AW_6 0x3465FC
+
+#define mmSIF_RTR_CTRL_4_RANGE_SEC_BASE_LOW_AW_7 0x346600
+
+#define mmSIF_RTR_CTRL_4_RANGE_SEC_BASE_LOW_AW_8 0x346604
+
+#define mmSIF_RTR_CTRL_4_RANGE_SEC_BASE_LOW_AW_9 0x346608
+
+#define mmSIF_RTR_CTRL_4_RANGE_SEC_BASE_LOW_AW_10 0x34660C
+
+#define mmSIF_RTR_CTRL_4_RANGE_SEC_BASE_LOW_AW_11 0x346610
+
+#define mmSIF_RTR_CTRL_4_RANGE_SEC_BASE_LOW_AW_12 0x346614
+
+#define mmSIF_RTR_CTRL_4_RANGE_SEC_BASE_LOW_AW_13 0x346618
+
+#define mmSIF_RTR_CTRL_4_RANGE_SEC_BASE_LOW_AW_14 0x34661C
+
+#define mmSIF_RTR_CTRL_4_RANGE_SEC_BASE_LOW_AW_15 0x346620
+
+#define mmSIF_RTR_CTRL_4_RANGE_SEC_BASE_HIGH_AW_0 0x346624
+
+#define mmSIF_RTR_CTRL_4_RANGE_SEC_BASE_HIGH_AW_1 0x346628
+
+#define mmSIF_RTR_CTRL_4_RANGE_SEC_BASE_HIGH_AW_2 0x34662C
+
+#define mmSIF_RTR_CTRL_4_RANGE_SEC_BASE_HIGH_AW_3 0x346630
+
+#define mmSIF_RTR_CTRL_4_RANGE_SEC_BASE_HIGH_AW_4 0x346634
+
+#define mmSIF_RTR_CTRL_4_RANGE_SEC_BASE_HIGH_AW_5 0x346638
+
+#define mmSIF_RTR_CTRL_4_RANGE_SEC_BASE_HIGH_AW_6 0x34663C
+
+#define mmSIF_RTR_CTRL_4_RANGE_SEC_BASE_HIGH_AW_7 0x346640
+
+#define mmSIF_RTR_CTRL_4_RANGE_SEC_BASE_HIGH_AW_8 0x346644
+
+#define mmSIF_RTR_CTRL_4_RANGE_SEC_BASE_HIGH_AW_9 0x346648
+
+#define mmSIF_RTR_CTRL_4_RANGE_SEC_BASE_HIGH_AW_10 0x34664C
+
+#define mmSIF_RTR_CTRL_4_RANGE_SEC_BASE_HIGH_AW_11 0x346650
+
+#define mmSIF_RTR_CTRL_4_RANGE_SEC_BASE_HIGH_AW_12 0x346654
+
+#define mmSIF_RTR_CTRL_4_RANGE_SEC_BASE_HIGH_AW_13 0x346658
+
+#define mmSIF_RTR_CTRL_4_RANGE_SEC_BASE_HIGH_AW_14 0x34665C
+
+#define mmSIF_RTR_CTRL_4_RANGE_SEC_BASE_HIGH_AW_15 0x346660
+
+#define mmSIF_RTR_CTRL_4_RANGE_SEC_MASK_LOW_AW_0 0x346664
+
+#define mmSIF_RTR_CTRL_4_RANGE_SEC_MASK_LOW_AW_1 0x346668
+
+#define mmSIF_RTR_CTRL_4_RANGE_SEC_MASK_LOW_AW_2 0x34666C
+
+#define mmSIF_RTR_CTRL_4_RANGE_SEC_MASK_LOW_AW_3 0x346670
+
+#define mmSIF_RTR_CTRL_4_RANGE_SEC_MASK_LOW_AW_4 0x346674
+
+#define mmSIF_RTR_CTRL_4_RANGE_SEC_MASK_LOW_AW_5 0x346678
+
+#define mmSIF_RTR_CTRL_4_RANGE_SEC_MASK_LOW_AW_6 0x34667C
+
+#define mmSIF_RTR_CTRL_4_RANGE_SEC_MASK_LOW_AW_7 0x346680
+
+#define mmSIF_RTR_CTRL_4_RANGE_SEC_MASK_LOW_AW_8 0x346684
+
+#define mmSIF_RTR_CTRL_4_RANGE_SEC_MASK_LOW_AW_9 0x346688
+
+#define mmSIF_RTR_CTRL_4_RANGE_SEC_MASK_LOW_AW_10 0x34668C
+
+#define mmSIF_RTR_CTRL_4_RANGE_SEC_MASK_LOW_AW_11 0x346690
+
+#define mmSIF_RTR_CTRL_4_RANGE_SEC_MASK_LOW_AW_12 0x346694
+
+#define mmSIF_RTR_CTRL_4_RANGE_SEC_MASK_LOW_AW_13 0x346698
+
+#define mmSIF_RTR_CTRL_4_RANGE_SEC_MASK_LOW_AW_14 0x34669C
+
+#define mmSIF_RTR_CTRL_4_RANGE_SEC_MASK_LOW_AW_15 0x3466A0
+
+#define mmSIF_RTR_CTRL_4_RANGE_SEC_MASK_HIGH_AW_0 0x3466A4
+
+#define mmSIF_RTR_CTRL_4_RANGE_SEC_MASK_HIGH_AW_1 0x3466A8
+
+#define mmSIF_RTR_CTRL_4_RANGE_SEC_MASK_HIGH_AW_2 0x3466AC
+
+#define mmSIF_RTR_CTRL_4_RANGE_SEC_MASK_HIGH_AW_3 0x3466B0
+
+#define mmSIF_RTR_CTRL_4_RANGE_SEC_MASK_HIGH_AW_4 0x3466B4
+
+#define mmSIF_RTR_CTRL_4_RANGE_SEC_MASK_HIGH_AW_5 0x3466B8
+
+#define mmSIF_RTR_CTRL_4_RANGE_SEC_MASK_HIGH_AW_6 0x3466BC
+
+#define mmSIF_RTR_CTRL_4_RANGE_SEC_MASK_HIGH_AW_7 0x3466C0
+
+#define mmSIF_RTR_CTRL_4_RANGE_SEC_MASK_HIGH_AW_8 0x3466C4
+
+#define mmSIF_RTR_CTRL_4_RANGE_SEC_MASK_HIGH_AW_9 0x3466C8
+
+#define mmSIF_RTR_CTRL_4_RANGE_SEC_MASK_HIGH_AW_10 0x3466CC
+
+#define mmSIF_RTR_CTRL_4_RANGE_SEC_MASK_HIGH_AW_11 0x3466D0
+
+#define mmSIF_RTR_CTRL_4_RANGE_SEC_MASK_HIGH_AW_12 0x3466D4
+
+#define mmSIF_RTR_CTRL_4_RANGE_SEC_MASK_HIGH_AW_13 0x3466D8
+
+#define mmSIF_RTR_CTRL_4_RANGE_SEC_MASK_HIGH_AW_14 0x3466DC
+
+#define mmSIF_RTR_CTRL_4_RANGE_SEC_MASK_HIGH_AW_15 0x3466E0
+
+#define mmSIF_RTR_CTRL_4_RANGE_PRIV_BASE_LOW_AW_0 0x3466E4
+
+#define mmSIF_RTR_CTRL_4_RANGE_PRIV_BASE_LOW_AW_1 0x3466E8
+
+#define mmSIF_RTR_CTRL_4_RANGE_PRIV_BASE_LOW_AW_2 0x3466EC
+
+#define mmSIF_RTR_CTRL_4_RANGE_PRIV_BASE_LOW_AW_3 0x3466F0
+
+#define mmSIF_RTR_CTRL_4_RANGE_PRIV_BASE_LOW_AW_4 0x3466F4
+
+#define mmSIF_RTR_CTRL_4_RANGE_PRIV_BASE_LOW_AW_5 0x3466F8
+
+#define mmSIF_RTR_CTRL_4_RANGE_PRIV_BASE_LOW_AW_6 0x3466FC
+
+#define mmSIF_RTR_CTRL_4_RANGE_PRIV_BASE_LOW_AW_7 0x346700
+
+#define mmSIF_RTR_CTRL_4_RANGE_PRIV_BASE_LOW_AW_8 0x346704
+
+#define mmSIF_RTR_CTRL_4_RANGE_PRIV_BASE_LOW_AW_9 0x346708
+
+#define mmSIF_RTR_CTRL_4_RANGE_PRIV_BASE_LOW_AW_10 0x34670C
+
+#define mmSIF_RTR_CTRL_4_RANGE_PRIV_BASE_LOW_AW_11 0x346710
+
+#define mmSIF_RTR_CTRL_4_RANGE_PRIV_BASE_LOW_AW_12 0x346714
+
+#define mmSIF_RTR_CTRL_4_RANGE_PRIV_BASE_LOW_AW_13 0x346718
+
+#define mmSIF_RTR_CTRL_4_RANGE_PRIV_BASE_LOW_AW_14 0x34671C
+
+#define mmSIF_RTR_CTRL_4_RANGE_PRIV_BASE_LOW_AW_15 0x346720
+
+#define mmSIF_RTR_CTRL_4_RANGE_PRIV_BASE_HIGH_AW_0 0x346724
+
+#define mmSIF_RTR_CTRL_4_RANGE_PRIV_BASE_HIGH_AW_1 0x346728
+
+#define mmSIF_RTR_CTRL_4_RANGE_PRIV_BASE_HIGH_AW_2 0x34672C
+
+#define mmSIF_RTR_CTRL_4_RANGE_PRIV_BASE_HIGH_AW_3 0x346730
+
+#define mmSIF_RTR_CTRL_4_RANGE_PRIV_BASE_HIGH_AW_4 0x346734
+
+#define mmSIF_RTR_CTRL_4_RANGE_PRIV_BASE_HIGH_AW_5 0x346738
+
+#define mmSIF_RTR_CTRL_4_RANGE_PRIV_BASE_HIGH_AW_6 0x34673C
+
+#define mmSIF_RTR_CTRL_4_RANGE_PRIV_BASE_HIGH_AW_7 0x346740
+
+#define mmSIF_RTR_CTRL_4_RANGE_PRIV_BASE_HIGH_AW_8 0x346744
+
+#define mmSIF_RTR_CTRL_4_RANGE_PRIV_BASE_HIGH_AW_9 0x346748
+
+#define mmSIF_RTR_CTRL_4_RANGE_PRIV_BASE_HIGH_AW_10 0x34674C
+
+#define mmSIF_RTR_CTRL_4_RANGE_PRIV_BASE_HIGH_AW_11 0x346750
+
+#define mmSIF_RTR_CTRL_4_RANGE_PRIV_BASE_HIGH_AW_12 0x346754
+
+#define mmSIF_RTR_CTRL_4_RANGE_PRIV_BASE_HIGH_AW_13 0x346758
+
+#define mmSIF_RTR_CTRL_4_RANGE_PRIV_BASE_HIGH_AW_14 0x34675C
+
+#define mmSIF_RTR_CTRL_4_RANGE_PRIV_BASE_HIGH_AW_15 0x346760
+
+#define mmSIF_RTR_CTRL_4_RANGE_PRIV_MASK_LOW_AW_0 0x346764
+
+#define mmSIF_RTR_CTRL_4_RANGE_PRIV_MASK_LOW_AW_1 0x346768
+
+#define mmSIF_RTR_CTRL_4_RANGE_PRIV_MASK_LOW_AW_2 0x34676C
+
+#define mmSIF_RTR_CTRL_4_RANGE_PRIV_MASK_LOW_AW_3 0x346770
+
+#define mmSIF_RTR_CTRL_4_RANGE_PRIV_MASK_LOW_AW_4 0x346774
+
+#define mmSIF_RTR_CTRL_4_RANGE_PRIV_MASK_LOW_AW_5 0x346778
+
+#define mmSIF_RTR_CTRL_4_RANGE_PRIV_MASK_LOW_AW_6 0x34677C
+
+#define mmSIF_RTR_CTRL_4_RANGE_PRIV_MASK_LOW_AW_7 0x346780
+
+#define mmSIF_RTR_CTRL_4_RANGE_PRIV_MASK_LOW_AW_8 0x346784
+
+#define mmSIF_RTR_CTRL_4_RANGE_PRIV_MASK_LOW_AW_9 0x346788
+
+#define mmSIF_RTR_CTRL_4_RANGE_PRIV_MASK_LOW_AW_10 0x34678C
+
+#define mmSIF_RTR_CTRL_4_RANGE_PRIV_MASK_LOW_AW_11 0x346790
+
+#define mmSIF_RTR_CTRL_4_RANGE_PRIV_MASK_LOW_AW_12 0x346794
+
+#define mmSIF_RTR_CTRL_4_RANGE_PRIV_MASK_LOW_AW_13 0x346798
+
+#define mmSIF_RTR_CTRL_4_RANGE_PRIV_MASK_LOW_AW_14 0x34679C
+
+#define mmSIF_RTR_CTRL_4_RANGE_PRIV_MASK_LOW_AW_15 0x3467A0
+
+#define mmSIF_RTR_CTRL_4_RANGE_PRIV_MASK_HIGH_AW_0 0x3467A4
+
+#define mmSIF_RTR_CTRL_4_RANGE_PRIV_MASK_HIGH_AW_1 0x3467A8
+
+#define mmSIF_RTR_CTRL_4_RANGE_PRIV_MASK_HIGH_AW_2 0x3467AC
+
+#define mmSIF_RTR_CTRL_4_RANGE_PRIV_MASK_HIGH_AW_3 0x3467B0
+
+#define mmSIF_RTR_CTRL_4_RANGE_PRIV_MASK_HIGH_AW_4 0x3467B4
+
+#define mmSIF_RTR_CTRL_4_RANGE_PRIV_MASK_HIGH_AW_5 0x3467B8
+
+#define mmSIF_RTR_CTRL_4_RANGE_PRIV_MASK_HIGH_AW_6 0x3467BC
+
+#define mmSIF_RTR_CTRL_4_RANGE_PRIV_MASK_HIGH_AW_7 0x3467C0
+
+#define mmSIF_RTR_CTRL_4_RANGE_PRIV_MASK_HIGH_AW_8 0x3467C4
+
+#define mmSIF_RTR_CTRL_4_RANGE_PRIV_MASK_HIGH_AW_9 0x3467C8
+
+#define mmSIF_RTR_CTRL_4_RANGE_PRIV_MASK_HIGH_AW_10 0x3467CC
+
+#define mmSIF_RTR_CTRL_4_RANGE_PRIV_MASK_HIGH_AW_11 0x3467D0
+
+#define mmSIF_RTR_CTRL_4_RANGE_PRIV_MASK_HIGH_AW_12 0x3467D4
+
+#define mmSIF_RTR_CTRL_4_RANGE_PRIV_MASK_HIGH_AW_13 0x3467D8
+
+#define mmSIF_RTR_CTRL_4_RANGE_PRIV_MASK_HIGH_AW_14 0x3467DC
+
+#define mmSIF_RTR_CTRL_4_RANGE_PRIV_MASK_HIGH_AW_15 0x3467E0
+
+#define mmSIF_RTR_CTRL_4_RANGE_SEC_BASE_LOW_AR_0 0x346824
+
+#define mmSIF_RTR_CTRL_4_RANGE_SEC_BASE_LOW_AR_1 0x346828
+
+#define mmSIF_RTR_CTRL_4_RANGE_SEC_BASE_LOW_AR_2 0x34682C
+
+#define mmSIF_RTR_CTRL_4_RANGE_SEC_BASE_LOW_AR_3 0x346830
+
+#define mmSIF_RTR_CTRL_4_RANGE_SEC_BASE_LOW_AR_4 0x346834
+
+#define mmSIF_RTR_CTRL_4_RANGE_SEC_BASE_LOW_AR_5 0x346838
+
+#define mmSIF_RTR_CTRL_4_RANGE_SEC_BASE_LOW_AR_6 0x34683C
+
+#define mmSIF_RTR_CTRL_4_RANGE_SEC_BASE_LOW_AR_7 0x346840
+
+#define mmSIF_RTR_CTRL_4_RANGE_SEC_BASE_LOW_AR_8 0x346844
+
+#define mmSIF_RTR_CTRL_4_RANGE_SEC_BASE_LOW_AR_9 0x346848
+
+#define mmSIF_RTR_CTRL_4_RANGE_SEC_BASE_LOW_AR_10 0x34684C
+
+#define mmSIF_RTR_CTRL_4_RANGE_SEC_BASE_LOW_AR_11 0x346850
+
+#define mmSIF_RTR_CTRL_4_RANGE_SEC_BASE_LOW_AR_12 0x346854
+
+#define mmSIF_RTR_CTRL_4_RANGE_SEC_BASE_LOW_AR_13 0x346858
+
+#define mmSIF_RTR_CTRL_4_RANGE_SEC_BASE_LOW_AR_14 0x34685C
+
+#define mmSIF_RTR_CTRL_4_RANGE_SEC_BASE_LOW_AR_15 0x346860
+
+#define mmSIF_RTR_CTRL_4_RANGE_SEC_BASE_HIGH_AR_0 0x346864
+
+#define mmSIF_RTR_CTRL_4_RANGE_SEC_BASE_HIGH_AR_1 0x346868
+
+#define mmSIF_RTR_CTRL_4_RANGE_SEC_BASE_HIGH_AR_2 0x34686C
+
+#define mmSIF_RTR_CTRL_4_RANGE_SEC_BASE_HIGH_AR_3 0x346870
+
+#define mmSIF_RTR_CTRL_4_RANGE_SEC_BASE_HIGH_AR_4 0x346874
+
+#define mmSIF_RTR_CTRL_4_RANGE_SEC_BASE_HIGH_AR_5 0x346878
+
+#define mmSIF_RTR_CTRL_4_RANGE_SEC_BASE_HIGH_AR_6 0x34687C
+
+#define mmSIF_RTR_CTRL_4_RANGE_SEC_BASE_HIGH_AR_7 0x346880
+
+#define mmSIF_RTR_CTRL_4_RANGE_SEC_BASE_HIGH_AR_8 0x346884
+
+#define mmSIF_RTR_CTRL_4_RANGE_SEC_BASE_HIGH_AR_9 0x346888
+
+#define mmSIF_RTR_CTRL_4_RANGE_SEC_BASE_HIGH_AR_10 0x34688C
+
+#define mmSIF_RTR_CTRL_4_RANGE_SEC_BASE_HIGH_AR_11 0x346890
+
+#define mmSIF_RTR_CTRL_4_RANGE_SEC_BASE_HIGH_AR_12 0x346894
+
+#define mmSIF_RTR_CTRL_4_RANGE_SEC_BASE_HIGH_AR_13 0x346898
+
+#define mmSIF_RTR_CTRL_4_RANGE_SEC_BASE_HIGH_AR_14 0x34689C
+
+#define mmSIF_RTR_CTRL_4_RANGE_SEC_BASE_HIGH_AR_15 0x3468A0
+
+#define mmSIF_RTR_CTRL_4_RANGE_SEC_MASK_LOW_AR_0 0x3468A4
+
+#define mmSIF_RTR_CTRL_4_RANGE_SEC_MASK_LOW_AR_1 0x3468A8
+
+#define mmSIF_RTR_CTRL_4_RANGE_SEC_MASK_LOW_AR_2 0x3468AC
+
+#define mmSIF_RTR_CTRL_4_RANGE_SEC_MASK_LOW_AR_3 0x3468B0
+
+#define mmSIF_RTR_CTRL_4_RANGE_SEC_MASK_LOW_AR_4 0x3468B4
+
+#define mmSIF_RTR_CTRL_4_RANGE_SEC_MASK_LOW_AR_5 0x3468B8
+
+#define mmSIF_RTR_CTRL_4_RANGE_SEC_MASK_LOW_AR_6 0x3468BC
+
+#define mmSIF_RTR_CTRL_4_RANGE_SEC_MASK_LOW_AR_7 0x3468C0
+
+#define mmSIF_RTR_CTRL_4_RANGE_SEC_MASK_LOW_AR_8 0x3468C4
+
+#define mmSIF_RTR_CTRL_4_RANGE_SEC_MASK_LOW_AR_9 0x3468C8
+
+#define mmSIF_RTR_CTRL_4_RANGE_SEC_MASK_LOW_AR_10 0x3468CC
+
+#define mmSIF_RTR_CTRL_4_RANGE_SEC_MASK_LOW_AR_11 0x3468D0
+
+#define mmSIF_RTR_CTRL_4_RANGE_SEC_MASK_LOW_AR_12 0x3468D4
+
+#define mmSIF_RTR_CTRL_4_RANGE_SEC_MASK_LOW_AR_13 0x3468D8
+
+#define mmSIF_RTR_CTRL_4_RANGE_SEC_MASK_LOW_AR_14 0x3468DC
+
+#define mmSIF_RTR_CTRL_4_RANGE_SEC_MASK_LOW_AR_15 0x3468E0
+
+#define mmSIF_RTR_CTRL_4_RANGE_SEC_MASK_HIGH_AR_0 0x3468E4
+
+#define mmSIF_RTR_CTRL_4_RANGE_SEC_MASK_HIGH_AR_1 0x3468E8
+
+#define mmSIF_RTR_CTRL_4_RANGE_SEC_MASK_HIGH_AR_2 0x3468EC
+
+#define mmSIF_RTR_CTRL_4_RANGE_SEC_MASK_HIGH_AR_3 0x3468F0
+
+#define mmSIF_RTR_CTRL_4_RANGE_SEC_MASK_HIGH_AR_4 0x3468F4
+
+#define mmSIF_RTR_CTRL_4_RANGE_SEC_MASK_HIGH_AR_5 0x3468F8
+
+#define mmSIF_RTR_CTRL_4_RANGE_SEC_MASK_HIGH_AR_6 0x3468FC
+
+#define mmSIF_RTR_CTRL_4_RANGE_SEC_MASK_HIGH_AR_7 0x346900
+
+#define mmSIF_RTR_CTRL_4_RANGE_SEC_MASK_HIGH_AR_8 0x346904
+
+#define mmSIF_RTR_CTRL_4_RANGE_SEC_MASK_HIGH_AR_9 0x346908
+
+#define mmSIF_RTR_CTRL_4_RANGE_SEC_MASK_HIGH_AR_10 0x34690C
+
+#define mmSIF_RTR_CTRL_4_RANGE_SEC_MASK_HIGH_AR_11 0x346910
+
+#define mmSIF_RTR_CTRL_4_RANGE_SEC_MASK_HIGH_AR_12 0x346914
+
+#define mmSIF_RTR_CTRL_4_RANGE_SEC_MASK_HIGH_AR_13 0x346918
+
+#define mmSIF_RTR_CTRL_4_RANGE_SEC_MASK_HIGH_AR_14 0x34691C
+
+#define mmSIF_RTR_CTRL_4_RANGE_SEC_MASK_HIGH_AR_15 0x346920
+
+#define mmSIF_RTR_CTRL_4_RANGE_PRIV_BASE_LOW_AR_0 0x346924
+
+#define mmSIF_RTR_CTRL_4_RANGE_PRIV_BASE_LOW_AR_1 0x346928
+
+#define mmSIF_RTR_CTRL_4_RANGE_PRIV_BASE_LOW_AR_2 0x34692C
+
+#define mmSIF_RTR_CTRL_4_RANGE_PRIV_BASE_LOW_AR_3 0x346930
+
+#define mmSIF_RTR_CTRL_4_RANGE_PRIV_BASE_LOW_AR_4 0x346934
+
+#define mmSIF_RTR_CTRL_4_RANGE_PRIV_BASE_LOW_AR_5 0x346938
+
+#define mmSIF_RTR_CTRL_4_RANGE_PRIV_BASE_LOW_AR_6 0x34693C
+
+#define mmSIF_RTR_CTRL_4_RANGE_PRIV_BASE_LOW_AR_7 0x346940
+
+#define mmSIF_RTR_CTRL_4_RANGE_PRIV_BASE_LOW_AR_8 0x346944
+
+#define mmSIF_RTR_CTRL_4_RANGE_PRIV_BASE_LOW_AR_9 0x346948
+
+#define mmSIF_RTR_CTRL_4_RANGE_PRIV_BASE_LOW_AR_10 0x34694C
+
+#define mmSIF_RTR_CTRL_4_RANGE_PRIV_BASE_LOW_AR_11 0x346950
+
+#define mmSIF_RTR_CTRL_4_RANGE_PRIV_BASE_LOW_AR_12 0x346954
+
+#define mmSIF_RTR_CTRL_4_RANGE_PRIV_BASE_LOW_AR_13 0x346958
+
+#define mmSIF_RTR_CTRL_4_RANGE_PRIV_BASE_LOW_AR_14 0x34695C
+
+#define mmSIF_RTR_CTRL_4_RANGE_PRIV_BASE_LOW_AR_15 0x346960
+
+#define mmSIF_RTR_CTRL_4_RANGE_PRIV_BASE_HIGH_AR_0 0x346964
+
+#define mmSIF_RTR_CTRL_4_RANGE_PRIV_BASE_HIGH_AR_1 0x346968
+
+#define mmSIF_RTR_CTRL_4_RANGE_PRIV_BASE_HIGH_AR_2 0x34696C
+
+#define mmSIF_RTR_CTRL_4_RANGE_PRIV_BASE_HIGH_AR_3 0x346970
+
+#define mmSIF_RTR_CTRL_4_RANGE_PRIV_BASE_HIGH_AR_4 0x346974
+
+#define mmSIF_RTR_CTRL_4_RANGE_PRIV_BASE_HIGH_AR_5 0x346978
+
+#define mmSIF_RTR_CTRL_4_RANGE_PRIV_BASE_HIGH_AR_6 0x34697C
+
+#define mmSIF_RTR_CTRL_4_RANGE_PRIV_BASE_HIGH_AR_7 0x346980
+
+#define mmSIF_RTR_CTRL_4_RANGE_PRIV_BASE_HIGH_AR_8 0x346984
+
+#define mmSIF_RTR_CTRL_4_RANGE_PRIV_BASE_HIGH_AR_9 0x346988
+
+#define mmSIF_RTR_CTRL_4_RANGE_PRIV_BASE_HIGH_AR_10 0x34698C
+
+#define mmSIF_RTR_CTRL_4_RANGE_PRIV_BASE_HIGH_AR_11 0x346990
+
+#define mmSIF_RTR_CTRL_4_RANGE_PRIV_BASE_HIGH_AR_12 0x346994
+
+#define mmSIF_RTR_CTRL_4_RANGE_PRIV_BASE_HIGH_AR_13 0x346998
+
+#define mmSIF_RTR_CTRL_4_RANGE_PRIV_BASE_HIGH_AR_14 0x34699C
+
+#define mmSIF_RTR_CTRL_4_RANGE_PRIV_BASE_HIGH_AR_15 0x3469A0
+
+#define mmSIF_RTR_CTRL_4_RANGE_PRIV_MASK_LOW_AR_0 0x3469A4
+
+#define mmSIF_RTR_CTRL_4_RANGE_PRIV_MASK_LOW_AR_1 0x3469A8
+
+#define mmSIF_RTR_CTRL_4_RANGE_PRIV_MASK_LOW_AR_2 0x3469AC
+
+#define mmSIF_RTR_CTRL_4_RANGE_PRIV_MASK_LOW_AR_3 0x3469B0
+
+#define mmSIF_RTR_CTRL_4_RANGE_PRIV_MASK_LOW_AR_4 0x3469B4
+
+#define mmSIF_RTR_CTRL_4_RANGE_PRIV_MASK_LOW_AR_5 0x3469B8
+
+#define mmSIF_RTR_CTRL_4_RANGE_PRIV_MASK_LOW_AR_6 0x3469BC
+
+#define mmSIF_RTR_CTRL_4_RANGE_PRIV_MASK_LOW_AR_7 0x3469C0
+
+#define mmSIF_RTR_CTRL_4_RANGE_PRIV_MASK_LOW_AR_8 0x3469C4
+
+#define mmSIF_RTR_CTRL_4_RANGE_PRIV_MASK_LOW_AR_9 0x3469C8
+
+#define mmSIF_RTR_CTRL_4_RANGE_PRIV_MASK_LOW_AR_10 0x3469CC
+
+#define mmSIF_RTR_CTRL_4_RANGE_PRIV_MASK_LOW_AR_11 0x3469D0
+
+#define mmSIF_RTR_CTRL_4_RANGE_PRIV_MASK_LOW_AR_12 0x3469D4
+
+#define mmSIF_RTR_CTRL_4_RANGE_PRIV_MASK_LOW_AR_13 0x3469D8
+
+#define mmSIF_RTR_CTRL_4_RANGE_PRIV_MASK_LOW_AR_14 0x3469DC
+
+#define mmSIF_RTR_CTRL_4_RANGE_PRIV_MASK_LOW_AR_15 0x3469E0
+
+#define mmSIF_RTR_CTRL_4_RANGE_PRIV_MASK_HIGH_AR_0 0x3469E4
+
+#define mmSIF_RTR_CTRL_4_RANGE_PRIV_MASK_HIGH_AR_1 0x3469E8
+
+#define mmSIF_RTR_CTRL_4_RANGE_PRIV_MASK_HIGH_AR_2 0x3469EC
+
+#define mmSIF_RTR_CTRL_4_RANGE_PRIV_MASK_HIGH_AR_3 0x3469F0
+
+#define mmSIF_RTR_CTRL_4_RANGE_PRIV_MASK_HIGH_AR_4 0x3469F4
+
+#define mmSIF_RTR_CTRL_4_RANGE_PRIV_MASK_HIGH_AR_5 0x3469F8
+
+#define mmSIF_RTR_CTRL_4_RANGE_PRIV_MASK_HIGH_AR_6 0x3469FC
+
+#define mmSIF_RTR_CTRL_4_RANGE_PRIV_MASK_HIGH_AR_7 0x346A00
+
+#define mmSIF_RTR_CTRL_4_RANGE_PRIV_MASK_HIGH_AR_8 0x346A04
+
+#define mmSIF_RTR_CTRL_4_RANGE_PRIV_MASK_HIGH_AR_9 0x346A08
+
+#define mmSIF_RTR_CTRL_4_RANGE_PRIV_MASK_HIGH_AR_10 0x346A0C
+
+#define mmSIF_RTR_CTRL_4_RANGE_PRIV_MASK_HIGH_AR_11 0x346A10
+
+#define mmSIF_RTR_CTRL_4_RANGE_PRIV_MASK_HIGH_AR_12 0x346A14
+
+#define mmSIF_RTR_CTRL_4_RANGE_PRIV_MASK_HIGH_AR_13 0x346A18
+
+#define mmSIF_RTR_CTRL_4_RANGE_PRIV_MASK_HIGH_AR_14 0x346A1C
+
+#define mmSIF_RTR_CTRL_4_RANGE_PRIV_MASK_HIGH_AR_15 0x346A20
+
+#define mmSIF_RTR_CTRL_4_RANGE_SEC_HIT_AW 0x346A64
+
+#define mmSIF_RTR_CTRL_4_RANGE_SEC_HIT_AR 0x346A68
+
+#define mmSIF_RTR_CTRL_4_RANGE_PRIV_HIT_AW 0x346A6C
+
+#define mmSIF_RTR_CTRL_4_RANGE_PRIV_HIT_AR 0x346A70
+
+#define mmSIF_RTR_CTRL_4_RGL_CFG 0x346B64
+
+#define mmSIF_RTR_CTRL_4_RGL_SHIFT 0x346B68
+
+#define mmSIF_RTR_CTRL_4_RGL_EXPECTED_LAT_0 0x346B6C
+
+#define mmSIF_RTR_CTRL_4_RGL_EXPECTED_LAT_1 0x346B70
+
+#define mmSIF_RTR_CTRL_4_RGL_EXPECTED_LAT_2 0x346B74
+
+#define mmSIF_RTR_CTRL_4_RGL_EXPECTED_LAT_3 0x346B78
+
+#define mmSIF_RTR_CTRL_4_RGL_EXPECTED_LAT_4 0x346B7C
+
+#define mmSIF_RTR_CTRL_4_RGL_EXPECTED_LAT_5 0x346B80
+
+#define mmSIF_RTR_CTRL_4_RGL_EXPECTED_LAT_6 0x346B84
+
+#define mmSIF_RTR_CTRL_4_RGL_EXPECTED_LAT_7 0x346B88
+
+#define mmSIF_RTR_CTRL_4_RGL_TOKEN_0 0x346BAC
+
+#define mmSIF_RTR_CTRL_4_RGL_TOKEN_1 0x346BB0
+
+#define mmSIF_RTR_CTRL_4_RGL_TOKEN_2 0x346BB4
+
+#define mmSIF_RTR_CTRL_4_RGL_TOKEN_3 0x346BB8
+
+#define mmSIF_RTR_CTRL_4_RGL_TOKEN_4 0x346BBC
+
+#define mmSIF_RTR_CTRL_4_RGL_TOKEN_5 0x346BC0
+
+#define mmSIF_RTR_CTRL_4_RGL_TOKEN_6 0x346BC4
+
+#define mmSIF_RTR_CTRL_4_RGL_TOKEN_7 0x346BC8
+
+#define mmSIF_RTR_CTRL_4_RGL_BANK_ID_0 0x346BEC
+
+#define mmSIF_RTR_CTRL_4_RGL_BANK_ID_1 0x346BF0
+
+#define mmSIF_RTR_CTRL_4_RGL_BANK_ID_2 0x346BF4
+
+#define mmSIF_RTR_CTRL_4_RGL_BANK_ID_3 0x346BF8
+
+#define mmSIF_RTR_CTRL_4_RGL_BANK_ID_4 0x346BFC
+
+#define mmSIF_RTR_CTRL_4_RGL_BANK_ID_5 0x346C00
+
+#define mmSIF_RTR_CTRL_4_RGL_BANK_ID_6 0x346C04
+
+#define mmSIF_RTR_CTRL_4_RGL_BANK_ID_7 0x346C08
+
+#define mmSIF_RTR_CTRL_4_RGL_WDT 0x346C2C
+
+#define mmSIF_RTR_CTRL_4_E2E_AR_HBM0_CH0_CTR_WRAP 0x346C30
+
+#define mmSIF_RTR_CTRL_4_E2E_AR_HBM0_CH1_CTR_WRAP 0x346C34
+
+#define mmSIF_RTR_CTRL_4_E2E_AR_HBM1_CH0_CTR_WRAP 0x346C38
+
+#define mmSIF_RTR_CTRL_4_E2E_AR_HBM1_CH1_CTR_WRAP 0x346C3C
+
+#define mmSIF_RTR_CTRL_4_E2E_AR_HBM2_CH0_CTR_WRAP 0x346C40
+
+#define mmSIF_RTR_CTRL_4_E2E_AR_HBM2_CH1_CTR_WRAP 0x346C44
+
+#define mmSIF_RTR_CTRL_4_E2E_AR_HBM3_CH0_CTR_WRAP 0x346C48
+
+#define mmSIF_RTR_CTRL_4_E2E_AR_HBM3_CH1_CTR_WRAP 0x346C4C
+
+#define mmSIF_RTR_CTRL_4_E2E_AR_HBM0_CH0_CTR_CNT 0x346C50
+
+#define mmSIF_RTR_CTRL_4_E2E_AR_HBM0_CH1_CTR_CNT 0x346C54
+
+#define mmSIF_RTR_CTRL_4_E2E_AR_HBM1_CH0_CTR_CNT 0x346C58
+
+#define mmSIF_RTR_CTRL_4_E2E_AR_HBM1_CH1_CTR_CNT 0x346C5C
+
+#define mmSIF_RTR_CTRL_4_E2E_AR_HBM2_CH0_CTR_CNT 0x346C60
+
+#define mmSIF_RTR_CTRL_4_E2E_AR_HBM2_CH1_CTR_CNT 0x346C64
+
+#define mmSIF_RTR_CTRL_4_E2E_AR_HBM3_CH0_CTR_CNT 0x346C68
+
+#define mmSIF_RTR_CTRL_4_E2E_AR_HBM3_CH1_CTR_CNT 0x346C6C
+
+#define mmSIF_RTR_CTRL_4_E2E_AW_HBM0_CH0_CTR_WRAP 0x346C70
+
+#define mmSIF_RTR_CTRL_4_E2E_AW_HBM0_CH1_CTR_WRAP 0x346C74
+
+#define mmSIF_RTR_CTRL_4_E2E_AW_HBM1_CH0_CTR_WRAP 0x346C78
+
+#define mmSIF_RTR_CTRL_4_E2E_AW_HBM1_CH1_CTR_WRAP 0x346C7C
+
+#define mmSIF_RTR_CTRL_4_E2E_AW_HBM2_CH0_CTR_WRAP 0x346C80
+
+#define mmSIF_RTR_CTRL_4_E2E_AW_HBM2_CH1_CTR_WRAP 0x346C84
+
+#define mmSIF_RTR_CTRL_4_E2E_AW_HBM3_CH0_CTR_WRAP 0x346C88
+
+#define mmSIF_RTR_CTRL_4_E2E_AW_HBM3_CH1_CTR_WRAP 0x346C8C
+
+#define mmSIF_RTR_CTRL_4_E2E_AW_HBM0_CH0_CTR_CNT 0x346C90
+
+#define mmSIF_RTR_CTRL_4_E2E_AW_HBM0_CH1_CTR_CNT 0x346C94
+
+#define mmSIF_RTR_CTRL_4_E2E_AW_HBM1_CH0_CTR_CNT 0x346C98
+
+#define mmSIF_RTR_CTRL_4_E2E_AW_HBM1_CH1_CTR_CNT 0x346C9C
+
+#define mmSIF_RTR_CTRL_4_E2E_AW_HBM2_CH0_CTR_CNT 0x346CA0
+
+#define mmSIF_RTR_CTRL_4_E2E_AW_HBM2_CH1_CTR_CNT 0x346CA4
+
+#define mmSIF_RTR_CTRL_4_E2E_AW_HBM3_CH0_CTR_CNT 0x346CA8
+
+#define mmSIF_RTR_CTRL_4_E2E_AW_HBM3_CH1_CTR_CNT 0x346CAC
+
+#define mmSIF_RTR_CTRL_4_NL_HBM_PC_SEL_0 0x346CB0
+
+#define mmSIF_RTR_CTRL_4_NL_HBM_PC_SEL_1 0x346CB4
+
+#define mmSIF_RTR_CTRL_4_NL_HBM_PC_SEL_2 0x346CB8
+
+#define mmSIF_RTR_CTRL_4_NL_HBM_PC_SEL_3 0x346CBC
+
+#endif /* ASIC_REG_SIF_RTR_CTRL_4_REGS_H_ */
diff --git a/drivers/accel/habanalabs/include/gaudi/asic_reg/sif_rtr_ctrl_5_regs.h b/drivers/accel/habanalabs/include/gaudi/asic_reg/sif_rtr_ctrl_5_regs.h
new file mode 100644
index 0000000000..6c27850ca3
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi/asic_reg/sif_rtr_ctrl_5_regs.h
@@ -0,0 +1,896 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2016-2018 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ ** DO NOT EDIT BELOW **
+ ************************************/
+
+#ifndef ASIC_REG_SIF_RTR_CTRL_5_REGS_H_
+#define ASIC_REG_SIF_RTR_CTRL_5_REGS_H_
+
+/*
+ *****************************************
+ * SIF_RTR_CTRL_5 (Prototype: RTR_CTRL)
+ *****************************************
+ */
+
+#define mmSIF_RTR_CTRL_5_PERM_SEL 0x356108
+
+#define mmSIF_RTR_CTRL_5_HBM_POLY_H3_0 0x356114
+
+#define mmSIF_RTR_CTRL_5_HBM_POLY_H3_1 0x356118
+
+#define mmSIF_RTR_CTRL_5_HBM_POLY_H3_2 0x35611C
+
+#define mmSIF_RTR_CTRL_5_HBM_POLY_H3_3 0x356120
+
+#define mmSIF_RTR_CTRL_5_HBM_POLY_H3_4 0x356124
+
+#define mmSIF_RTR_CTRL_5_HBM_POLY_H3_5 0x356128
+
+#define mmSIF_RTR_CTRL_5_HBM_POLY_H3_6 0x35612C
+
+#define mmSIF_RTR_CTRL_5_HBM_POLY_H3_7 0x356130
+
+#define mmSIF_RTR_CTRL_5_HBM_POLY_H3_8 0x356134
+
+#define mmSIF_RTR_CTRL_5_HBM_POLY_H3_9 0x356138
+
+#define mmSIF_RTR_CTRL_5_HBM_POLY_H3_10 0x35613C
+
+#define mmSIF_RTR_CTRL_5_HBM_POLY_H3_11 0x356140
+
+#define mmSIF_RTR_CTRL_5_HBM_POLY_H3_12 0x356144
+
+#define mmSIF_RTR_CTRL_5_HBM_POLY_H3_13 0x356148
+
+#define mmSIF_RTR_CTRL_5_HBM_POLY_H3_14 0x35614C
+
+#define mmSIF_RTR_CTRL_5_HBM_POLY_H3_15 0x356150
+
+#define mmSIF_RTR_CTRL_5_HBM_POLY_H3_16 0x356154
+
+#define mmSIF_RTR_CTRL_5_HBM_POLY_H3_17 0x356158
+
+#define mmSIF_RTR_CTRL_5_HBM_POLY_H3_18 0x35615C
+
+#define mmSIF_RTR_CTRL_5_HBM_POLY_H3_19 0x356160
+
+#define mmSIF_RTR_CTRL_5_HBM_POLY_H3_20 0x356164
+
+#define mmSIF_RTR_CTRL_5_HBM_POLY_H3_21 0x356168
+
+#define mmSIF_RTR_CTRL_5_HBM_POLY_H3_22 0x35616C
+
+#define mmSIF_RTR_CTRL_5_HBM_POLY_H3_23 0x356170
+
+#define mmSIF_RTR_CTRL_5_HBM_POLY_H3_24 0x356174
+
+#define mmSIF_RTR_CTRL_5_HBM_POLY_H3_25 0x356178
+
+#define mmSIF_RTR_CTRL_5_HBM_POLY_H3_26 0x35617C
+
+#define mmSIF_RTR_CTRL_5_HBM_POLY_H3_27 0x356180
+
+#define mmSIF_RTR_CTRL_5_SRAM_POLY_H3_0 0x356184
+
+#define mmSIF_RTR_CTRL_5_SRAM_POLY_H3_1 0x356188
+
+#define mmSIF_RTR_CTRL_5_SRAM_POLY_H3_2 0x35618C
+
+#define mmSIF_RTR_CTRL_5_SRAM_POLY_H3_3 0x356190
+
+#define mmSIF_RTR_CTRL_5_SRAM_POLY_H3_4 0x356194
+
+#define mmSIF_RTR_CTRL_5_SRAM_POLY_H3_5 0x356198
+
+#define mmSIF_RTR_CTRL_5_SRAM_POLY_H3_6 0x35619C
+
+#define mmSIF_RTR_CTRL_5_SRAM_POLY_H3_7 0x3561A0
+
+#define mmSIF_RTR_CTRL_5_SRAM_POLY_H3_8 0x3561A4
+
+#define mmSIF_RTR_CTRL_5_SRAM_POLY_H3_9 0x3561A8
+
+#define mmSIF_RTR_CTRL_5_SRAM_POLY_H3_10 0x3561AC
+
+#define mmSIF_RTR_CTRL_5_SRAM_POLY_H3_11 0x3561B0
+
+#define mmSIF_RTR_CTRL_5_SRAM_POLY_H3_12 0x3561B4
+
+#define mmSIF_RTR_CTRL_5_SRAM_POLY_H3_13 0x3561B8
+
+#define mmSIF_RTR_CTRL_5_SRAM_POLY_H3_14 0x3561BC
+
+#define mmSIF_RTR_CTRL_5_SCRAM_SRAM_EN 0x35626C
+
+#define mmSIF_RTR_CTRL_5_RL_HBM_EN 0x356274
+
+#define mmSIF_RTR_CTRL_5_RL_HBM_SAT 0x356278
+
+#define mmSIF_RTR_CTRL_5_RL_HBM_RST 0x35627C
+
+#define mmSIF_RTR_CTRL_5_RL_HBM_TIMEOUT 0x356280
+
+#define mmSIF_RTR_CTRL_5_SCRAM_HBM_EN 0x356284
+
+#define mmSIF_RTR_CTRL_5_RL_PCI_EN 0x356288
+
+#define mmSIF_RTR_CTRL_5_RL_PCI_SAT 0x35628C
+
+#define mmSIF_RTR_CTRL_5_RL_PCI_RST 0x356290
+
+#define mmSIF_RTR_CTRL_5_RL_PCI_TIMEOUT 0x356294
+
+#define mmSIF_RTR_CTRL_5_RL_SRAM_EN 0x35629C
+
+#define mmSIF_RTR_CTRL_5_RL_SRAM_SAT 0x3562A0
+
+#define mmSIF_RTR_CTRL_5_RL_SRAM_RST 0x3562A4
+
+#define mmSIF_RTR_CTRL_5_RL_SRAM_TIMEOUT 0x3562AC
+
+#define mmSIF_RTR_CTRL_5_RL_SRAM_RED 0x3562B4
+
+#define mmSIF_RTR_CTRL_5_E2E_HBM_EN 0x3562EC
+
+#define mmSIF_RTR_CTRL_5_E2E_PCI_EN 0x3562F0
+
+#define mmSIF_RTR_CTRL_5_E2E_HBM_WR_SIZE 0x3562F4
+
+#define mmSIF_RTR_CTRL_5_E2E_PCI_WR_SIZE 0x3562F8
+
+#define mmSIF_RTR_CTRL_5_E2E_AW_PCI_CTR_SET_EN 0x356404
+
+#define mmSIF_RTR_CTRL_5_E2E_AW_PCI_CTR_SET 0x356408
+
+#define mmSIF_RTR_CTRL_5_E2E_AW_PCI_CTR_WRAP 0x35640C
+
+#define mmSIF_RTR_CTRL_5_E2E_AW_PCI_CTR_CNT 0x356410
+
+#define mmSIF_RTR_CTRL_5_E2E_AW_HBM_CTR_SET_EN 0x356414
+
+#define mmSIF_RTR_CTRL_5_E2E_AW_HBM_CTR_SET 0x356418
+
+#define mmSIF_RTR_CTRL_5_E2E_HBM_RD_SIZE 0x35641C
+
+#define mmSIF_RTR_CTRL_5_E2E_PCI_RD_SIZE 0x356420
+
+#define mmSIF_RTR_CTRL_5_E2E_AR_PCI_CTR_SET_EN 0x356424
+
+#define mmSIF_RTR_CTRL_5_E2E_AR_PCI_CTR_SET 0x356428
+
+#define mmSIF_RTR_CTRL_5_E2E_AR_PCI_CTR_WRAP 0x35642C
+
+#define mmSIF_RTR_CTRL_5_E2E_AR_PCI_CTR_CNT 0x356430
+
+#define mmSIF_RTR_CTRL_5_E2E_AR_HBM_CTR_SET_EN 0x356434
+
+#define mmSIF_RTR_CTRL_5_E2E_AR_HBM_CTR_SET 0x356438
+
+#define mmSIF_RTR_CTRL_5_NL_HBM_SEL_0 0x356450
+
+#define mmSIF_RTR_CTRL_5_NL_HBM_SEL_1 0x356454
+
+#define mmSIF_RTR_CTRL_5_NON_LIN_EN 0x356480
+
+#define mmSIF_RTR_CTRL_5_NL_SRAM_BANK_0 0x356500
+
+#define mmSIF_RTR_CTRL_5_NL_SRAM_BANK_1 0x356504
+
+#define mmSIF_RTR_CTRL_5_NL_SRAM_BANK_2 0x356508
+
+#define mmSIF_RTR_CTRL_5_NL_SRAM_BANK_3 0x35650C
+
+#define mmSIF_RTR_CTRL_5_NL_SRAM_BANK_4 0x356510
+
+#define mmSIF_RTR_CTRL_5_NL_SRAM_OFFSET_0 0x356514
+
+#define mmSIF_RTR_CTRL_5_NL_SRAM_OFFSET_1 0x356520
+
+#define mmSIF_RTR_CTRL_5_NL_SRAM_OFFSET_2 0x356524
+
+#define mmSIF_RTR_CTRL_5_NL_SRAM_OFFSET_3 0x356528
+
+#define mmSIF_RTR_CTRL_5_NL_SRAM_OFFSET_4 0x35652C
+
+#define mmSIF_RTR_CTRL_5_NL_SRAM_OFFSET_5 0x356530
+
+#define mmSIF_RTR_CTRL_5_NL_SRAM_OFFSET_6 0x356534
+
+#define mmSIF_RTR_CTRL_5_NL_SRAM_OFFSET_7 0x356538
+
+#define mmSIF_RTR_CTRL_5_NL_SRAM_OFFSET_8 0x35653C
+
+#define mmSIF_RTR_CTRL_5_NL_SRAM_OFFSET_9 0x356540
+
+#define mmSIF_RTR_CTRL_5_NL_HBM_OFFSET_0 0x356550
+
+#define mmSIF_RTR_CTRL_5_NL_HBM_OFFSET_1 0x356554
+
+#define mmSIF_RTR_CTRL_5_NL_HBM_OFFSET_2 0x356558
+
+#define mmSIF_RTR_CTRL_5_NL_HBM_OFFSET_3 0x35655C
+
+#define mmSIF_RTR_CTRL_5_NL_HBM_OFFSET_4 0x356560
+
+#define mmSIF_RTR_CTRL_5_NL_HBM_OFFSET_5 0x356564
+
+#define mmSIF_RTR_CTRL_5_NL_HBM_OFFSET_6 0x356568
+
+#define mmSIF_RTR_CTRL_5_NL_HBM_OFFSET_7 0x35656C
+
+#define mmSIF_RTR_CTRL_5_NL_HBM_OFFSET_8 0x356570
+
+#define mmSIF_RTR_CTRL_5_NL_HBM_OFFSET_9 0x356574
+
+#define mmSIF_RTR_CTRL_5_NL_HBM_OFFSET_10 0x356578
+
+#define mmSIF_RTR_CTRL_5_NL_HBM_OFFSET_11 0x35657C
+
+#define mmSIF_RTR_CTRL_5_NL_HBM_OFFSET_12 0x356580
+
+#define mmSIF_RTR_CTRL_5_NL_HBM_OFFSET_13 0x356584
+
+#define mmSIF_RTR_CTRL_5_NL_HBM_OFFSET_14 0x356588
+
+#define mmSIF_RTR_CTRL_5_NL_HBM_OFFSET_15 0x35658C
+
+#define mmSIF_RTR_CTRL_5_NL_HBM_OFFSET_16 0x356590
+
+#define mmSIF_RTR_CTRL_5_NL_HBM_OFFSET_17 0x356594
+
+#define mmSIF_RTR_CTRL_5_NL_HBM_OFFSET_18 0x356598
+
+#define mmSIF_RTR_CTRL_5_RANGE_SEC_BASE_LOW_AW_0 0x3565E4
+
+#define mmSIF_RTR_CTRL_5_RANGE_SEC_BASE_LOW_AW_1 0x3565E8
+
+#define mmSIF_RTR_CTRL_5_RANGE_SEC_BASE_LOW_AW_2 0x3565EC
+
+#define mmSIF_RTR_CTRL_5_RANGE_SEC_BASE_LOW_AW_3 0x3565F0
+
+#define mmSIF_RTR_CTRL_5_RANGE_SEC_BASE_LOW_AW_4 0x3565F4
+
+#define mmSIF_RTR_CTRL_5_RANGE_SEC_BASE_LOW_AW_5 0x3565F8
+
+#define mmSIF_RTR_CTRL_5_RANGE_SEC_BASE_LOW_AW_6 0x3565FC
+
+#define mmSIF_RTR_CTRL_5_RANGE_SEC_BASE_LOW_AW_7 0x356600
+
+#define mmSIF_RTR_CTRL_5_RANGE_SEC_BASE_LOW_AW_8 0x356604
+
+#define mmSIF_RTR_CTRL_5_RANGE_SEC_BASE_LOW_AW_9 0x356608
+
+#define mmSIF_RTR_CTRL_5_RANGE_SEC_BASE_LOW_AW_10 0x35660C
+
+#define mmSIF_RTR_CTRL_5_RANGE_SEC_BASE_LOW_AW_11 0x356610
+
+#define mmSIF_RTR_CTRL_5_RANGE_SEC_BASE_LOW_AW_12 0x356614
+
+#define mmSIF_RTR_CTRL_5_RANGE_SEC_BASE_LOW_AW_13 0x356618
+
+#define mmSIF_RTR_CTRL_5_RANGE_SEC_BASE_LOW_AW_14 0x35661C
+
+#define mmSIF_RTR_CTRL_5_RANGE_SEC_BASE_LOW_AW_15 0x356620
+
+#define mmSIF_RTR_CTRL_5_RANGE_SEC_BASE_HIGH_AW_0 0x356624
+
+#define mmSIF_RTR_CTRL_5_RANGE_SEC_BASE_HIGH_AW_1 0x356628
+
+#define mmSIF_RTR_CTRL_5_RANGE_SEC_BASE_HIGH_AW_2 0x35662C
+
+#define mmSIF_RTR_CTRL_5_RANGE_SEC_BASE_HIGH_AW_3 0x356630
+
+#define mmSIF_RTR_CTRL_5_RANGE_SEC_BASE_HIGH_AW_4 0x356634
+
+#define mmSIF_RTR_CTRL_5_RANGE_SEC_BASE_HIGH_AW_5 0x356638
+
+#define mmSIF_RTR_CTRL_5_RANGE_SEC_BASE_HIGH_AW_6 0x35663C
+
+#define mmSIF_RTR_CTRL_5_RANGE_SEC_BASE_HIGH_AW_7 0x356640
+
+#define mmSIF_RTR_CTRL_5_RANGE_SEC_BASE_HIGH_AW_8 0x356644
+
+#define mmSIF_RTR_CTRL_5_RANGE_SEC_BASE_HIGH_AW_9 0x356648
+
+#define mmSIF_RTR_CTRL_5_RANGE_SEC_BASE_HIGH_AW_10 0x35664C
+
+#define mmSIF_RTR_CTRL_5_RANGE_SEC_BASE_HIGH_AW_11 0x356650
+
+#define mmSIF_RTR_CTRL_5_RANGE_SEC_BASE_HIGH_AW_12 0x356654
+
+#define mmSIF_RTR_CTRL_5_RANGE_SEC_BASE_HIGH_AW_13 0x356658
+
+#define mmSIF_RTR_CTRL_5_RANGE_SEC_BASE_HIGH_AW_14 0x35665C
+
+#define mmSIF_RTR_CTRL_5_RANGE_SEC_BASE_HIGH_AW_15 0x356660
+
+#define mmSIF_RTR_CTRL_5_RANGE_SEC_MASK_LOW_AW_0 0x356664
+
+#define mmSIF_RTR_CTRL_5_RANGE_SEC_MASK_LOW_AW_1 0x356668
+
+#define mmSIF_RTR_CTRL_5_RANGE_SEC_MASK_LOW_AW_2 0x35666C
+
+#define mmSIF_RTR_CTRL_5_RANGE_SEC_MASK_LOW_AW_3 0x356670
+
+#define mmSIF_RTR_CTRL_5_RANGE_SEC_MASK_LOW_AW_4 0x356674
+
+#define mmSIF_RTR_CTRL_5_RANGE_SEC_MASK_LOW_AW_5 0x356678
+
+#define mmSIF_RTR_CTRL_5_RANGE_SEC_MASK_LOW_AW_6 0x35667C
+
+#define mmSIF_RTR_CTRL_5_RANGE_SEC_MASK_LOW_AW_7 0x356680
+
+#define mmSIF_RTR_CTRL_5_RANGE_SEC_MASK_LOW_AW_8 0x356684
+
+#define mmSIF_RTR_CTRL_5_RANGE_SEC_MASK_LOW_AW_9 0x356688
+
+#define mmSIF_RTR_CTRL_5_RANGE_SEC_MASK_LOW_AW_10 0x35668C
+
+#define mmSIF_RTR_CTRL_5_RANGE_SEC_MASK_LOW_AW_11 0x356690
+
+#define mmSIF_RTR_CTRL_5_RANGE_SEC_MASK_LOW_AW_12 0x356694
+
+#define mmSIF_RTR_CTRL_5_RANGE_SEC_MASK_LOW_AW_13 0x356698
+
+#define mmSIF_RTR_CTRL_5_RANGE_SEC_MASK_LOW_AW_14 0x35669C
+
+#define mmSIF_RTR_CTRL_5_RANGE_SEC_MASK_LOW_AW_15 0x3566A0
+
+#define mmSIF_RTR_CTRL_5_RANGE_SEC_MASK_HIGH_AW_0 0x3566A4
+
+#define mmSIF_RTR_CTRL_5_RANGE_SEC_MASK_HIGH_AW_1 0x3566A8
+
+#define mmSIF_RTR_CTRL_5_RANGE_SEC_MASK_HIGH_AW_2 0x3566AC
+
+#define mmSIF_RTR_CTRL_5_RANGE_SEC_MASK_HIGH_AW_3 0x3566B0
+
+#define mmSIF_RTR_CTRL_5_RANGE_SEC_MASK_HIGH_AW_4 0x3566B4
+
+#define mmSIF_RTR_CTRL_5_RANGE_SEC_MASK_HIGH_AW_5 0x3566B8
+
+#define mmSIF_RTR_CTRL_5_RANGE_SEC_MASK_HIGH_AW_6 0x3566BC
+
+#define mmSIF_RTR_CTRL_5_RANGE_SEC_MASK_HIGH_AW_7 0x3566C0
+
+#define mmSIF_RTR_CTRL_5_RANGE_SEC_MASK_HIGH_AW_8 0x3566C4
+
+#define mmSIF_RTR_CTRL_5_RANGE_SEC_MASK_HIGH_AW_9 0x3566C8
+
+#define mmSIF_RTR_CTRL_5_RANGE_SEC_MASK_HIGH_AW_10 0x3566CC
+
+#define mmSIF_RTR_CTRL_5_RANGE_SEC_MASK_HIGH_AW_11 0x3566D0
+
+#define mmSIF_RTR_CTRL_5_RANGE_SEC_MASK_HIGH_AW_12 0x3566D4
+
+#define mmSIF_RTR_CTRL_5_RANGE_SEC_MASK_HIGH_AW_13 0x3566D8
+
+#define mmSIF_RTR_CTRL_5_RANGE_SEC_MASK_HIGH_AW_14 0x3566DC
+
+#define mmSIF_RTR_CTRL_5_RANGE_SEC_MASK_HIGH_AW_15 0x3566E0
+
+#define mmSIF_RTR_CTRL_5_RANGE_PRIV_BASE_LOW_AW_0 0x3566E4
+
+#define mmSIF_RTR_CTRL_5_RANGE_PRIV_BASE_LOW_AW_1 0x3566E8
+
+#define mmSIF_RTR_CTRL_5_RANGE_PRIV_BASE_LOW_AW_2 0x3566EC
+
+#define mmSIF_RTR_CTRL_5_RANGE_PRIV_BASE_LOW_AW_3 0x3566F0
+
+#define mmSIF_RTR_CTRL_5_RANGE_PRIV_BASE_LOW_AW_4 0x3566F4
+
+#define mmSIF_RTR_CTRL_5_RANGE_PRIV_BASE_LOW_AW_5 0x3566F8
+
+#define mmSIF_RTR_CTRL_5_RANGE_PRIV_BASE_LOW_AW_6 0x3566FC
+
+#define mmSIF_RTR_CTRL_5_RANGE_PRIV_BASE_LOW_AW_7 0x356700
+
+#define mmSIF_RTR_CTRL_5_RANGE_PRIV_BASE_LOW_AW_8 0x356704
+
+#define mmSIF_RTR_CTRL_5_RANGE_PRIV_BASE_LOW_AW_9 0x356708
+
+#define mmSIF_RTR_CTRL_5_RANGE_PRIV_BASE_LOW_AW_10 0x35670C
+
+#define mmSIF_RTR_CTRL_5_RANGE_PRIV_BASE_LOW_AW_11 0x356710
+
+#define mmSIF_RTR_CTRL_5_RANGE_PRIV_BASE_LOW_AW_12 0x356714
+
+#define mmSIF_RTR_CTRL_5_RANGE_PRIV_BASE_LOW_AW_13 0x356718
+
+#define mmSIF_RTR_CTRL_5_RANGE_PRIV_BASE_LOW_AW_14 0x35671C
+
+#define mmSIF_RTR_CTRL_5_RANGE_PRIV_BASE_LOW_AW_15 0x356720
+
+#define mmSIF_RTR_CTRL_5_RANGE_PRIV_BASE_HIGH_AW_0 0x356724
+
+#define mmSIF_RTR_CTRL_5_RANGE_PRIV_BASE_HIGH_AW_1 0x356728
+
+#define mmSIF_RTR_CTRL_5_RANGE_PRIV_BASE_HIGH_AW_2 0x35672C
+
+#define mmSIF_RTR_CTRL_5_RANGE_PRIV_BASE_HIGH_AW_3 0x356730
+
+#define mmSIF_RTR_CTRL_5_RANGE_PRIV_BASE_HIGH_AW_4 0x356734
+
+#define mmSIF_RTR_CTRL_5_RANGE_PRIV_BASE_HIGH_AW_5 0x356738
+
+#define mmSIF_RTR_CTRL_5_RANGE_PRIV_BASE_HIGH_AW_6 0x35673C
+
+#define mmSIF_RTR_CTRL_5_RANGE_PRIV_BASE_HIGH_AW_7 0x356740
+
+#define mmSIF_RTR_CTRL_5_RANGE_PRIV_BASE_HIGH_AW_8 0x356744
+
+#define mmSIF_RTR_CTRL_5_RANGE_PRIV_BASE_HIGH_AW_9 0x356748
+
+#define mmSIF_RTR_CTRL_5_RANGE_PRIV_BASE_HIGH_AW_10 0x35674C
+
+#define mmSIF_RTR_CTRL_5_RANGE_PRIV_BASE_HIGH_AW_11 0x356750
+
+#define mmSIF_RTR_CTRL_5_RANGE_PRIV_BASE_HIGH_AW_12 0x356754
+
+#define mmSIF_RTR_CTRL_5_RANGE_PRIV_BASE_HIGH_AW_13 0x356758
+
+#define mmSIF_RTR_CTRL_5_RANGE_PRIV_BASE_HIGH_AW_14 0x35675C
+
+#define mmSIF_RTR_CTRL_5_RANGE_PRIV_BASE_HIGH_AW_15 0x356760
+
+#define mmSIF_RTR_CTRL_5_RANGE_PRIV_MASK_LOW_AW_0 0x356764
+
+#define mmSIF_RTR_CTRL_5_RANGE_PRIV_MASK_LOW_AW_1 0x356768
+
+#define mmSIF_RTR_CTRL_5_RANGE_PRIV_MASK_LOW_AW_2 0x35676C
+
+#define mmSIF_RTR_CTRL_5_RANGE_PRIV_MASK_LOW_AW_3 0x356770
+
+#define mmSIF_RTR_CTRL_5_RANGE_PRIV_MASK_LOW_AW_4 0x356774
+
+#define mmSIF_RTR_CTRL_5_RANGE_PRIV_MASK_LOW_AW_5 0x356778
+
+#define mmSIF_RTR_CTRL_5_RANGE_PRIV_MASK_LOW_AW_6 0x35677C
+
+#define mmSIF_RTR_CTRL_5_RANGE_PRIV_MASK_LOW_AW_7 0x356780
+
+#define mmSIF_RTR_CTRL_5_RANGE_PRIV_MASK_LOW_AW_8 0x356784
+
+#define mmSIF_RTR_CTRL_5_RANGE_PRIV_MASK_LOW_AW_9 0x356788
+
+#define mmSIF_RTR_CTRL_5_RANGE_PRIV_MASK_LOW_AW_10 0x35678C
+
+#define mmSIF_RTR_CTRL_5_RANGE_PRIV_MASK_LOW_AW_11 0x356790
+
+#define mmSIF_RTR_CTRL_5_RANGE_PRIV_MASK_LOW_AW_12 0x356794
+
+#define mmSIF_RTR_CTRL_5_RANGE_PRIV_MASK_LOW_AW_13 0x356798
+
+#define mmSIF_RTR_CTRL_5_RANGE_PRIV_MASK_LOW_AW_14 0x35679C
+
+#define mmSIF_RTR_CTRL_5_RANGE_PRIV_MASK_LOW_AW_15 0x3567A0
+
+#define mmSIF_RTR_CTRL_5_RANGE_PRIV_MASK_HIGH_AW_0 0x3567A4
+
+#define mmSIF_RTR_CTRL_5_RANGE_PRIV_MASK_HIGH_AW_1 0x3567A8
+
+#define mmSIF_RTR_CTRL_5_RANGE_PRIV_MASK_HIGH_AW_2 0x3567AC
+
+#define mmSIF_RTR_CTRL_5_RANGE_PRIV_MASK_HIGH_AW_3 0x3567B0
+
+#define mmSIF_RTR_CTRL_5_RANGE_PRIV_MASK_HIGH_AW_4 0x3567B4
+
+#define mmSIF_RTR_CTRL_5_RANGE_PRIV_MASK_HIGH_AW_5 0x3567B8
+
+#define mmSIF_RTR_CTRL_5_RANGE_PRIV_MASK_HIGH_AW_6 0x3567BC
+
+#define mmSIF_RTR_CTRL_5_RANGE_PRIV_MASK_HIGH_AW_7 0x3567C0
+
+#define mmSIF_RTR_CTRL_5_RANGE_PRIV_MASK_HIGH_AW_8 0x3567C4
+
+#define mmSIF_RTR_CTRL_5_RANGE_PRIV_MASK_HIGH_AW_9 0x3567C8
+
+#define mmSIF_RTR_CTRL_5_RANGE_PRIV_MASK_HIGH_AW_10 0x3567CC
+
+#define mmSIF_RTR_CTRL_5_RANGE_PRIV_MASK_HIGH_AW_11 0x3567D0
+
+#define mmSIF_RTR_CTRL_5_RANGE_PRIV_MASK_HIGH_AW_12 0x3567D4
+
+#define mmSIF_RTR_CTRL_5_RANGE_PRIV_MASK_HIGH_AW_13 0x3567D8
+
+#define mmSIF_RTR_CTRL_5_RANGE_PRIV_MASK_HIGH_AW_14 0x3567DC
+
+#define mmSIF_RTR_CTRL_5_RANGE_PRIV_MASK_HIGH_AW_15 0x3567E0
+
+#define mmSIF_RTR_CTRL_5_RANGE_SEC_BASE_LOW_AR_0 0x356824
+
+#define mmSIF_RTR_CTRL_5_RANGE_SEC_BASE_LOW_AR_1 0x356828
+
+#define mmSIF_RTR_CTRL_5_RANGE_SEC_BASE_LOW_AR_2 0x35682C
+
+#define mmSIF_RTR_CTRL_5_RANGE_SEC_BASE_LOW_AR_3 0x356830
+
+#define mmSIF_RTR_CTRL_5_RANGE_SEC_BASE_LOW_AR_4 0x356834
+
+#define mmSIF_RTR_CTRL_5_RANGE_SEC_BASE_LOW_AR_5 0x356838
+
+#define mmSIF_RTR_CTRL_5_RANGE_SEC_BASE_LOW_AR_6 0x35683C
+
+#define mmSIF_RTR_CTRL_5_RANGE_SEC_BASE_LOW_AR_7 0x356840
+
+#define mmSIF_RTR_CTRL_5_RANGE_SEC_BASE_LOW_AR_8 0x356844
+
+#define mmSIF_RTR_CTRL_5_RANGE_SEC_BASE_LOW_AR_9 0x356848
+
+#define mmSIF_RTR_CTRL_5_RANGE_SEC_BASE_LOW_AR_10 0x35684C
+
+#define mmSIF_RTR_CTRL_5_RANGE_SEC_BASE_LOW_AR_11 0x356850
+
+#define mmSIF_RTR_CTRL_5_RANGE_SEC_BASE_LOW_AR_12 0x356854
+
+#define mmSIF_RTR_CTRL_5_RANGE_SEC_BASE_LOW_AR_13 0x356858
+
+#define mmSIF_RTR_CTRL_5_RANGE_SEC_BASE_LOW_AR_14 0x35685C
+
+#define mmSIF_RTR_CTRL_5_RANGE_SEC_BASE_LOW_AR_15 0x356860
+
+#define mmSIF_RTR_CTRL_5_RANGE_SEC_BASE_HIGH_AR_0 0x356864
+
+#define mmSIF_RTR_CTRL_5_RANGE_SEC_BASE_HIGH_AR_1 0x356868
+
+#define mmSIF_RTR_CTRL_5_RANGE_SEC_BASE_HIGH_AR_2 0x35686C
+
+#define mmSIF_RTR_CTRL_5_RANGE_SEC_BASE_HIGH_AR_3 0x356870
+
+#define mmSIF_RTR_CTRL_5_RANGE_SEC_BASE_HIGH_AR_4 0x356874
+
+#define mmSIF_RTR_CTRL_5_RANGE_SEC_BASE_HIGH_AR_5 0x356878
+
+#define mmSIF_RTR_CTRL_5_RANGE_SEC_BASE_HIGH_AR_6 0x35687C
+
+#define mmSIF_RTR_CTRL_5_RANGE_SEC_BASE_HIGH_AR_7 0x356880
+
+#define mmSIF_RTR_CTRL_5_RANGE_SEC_BASE_HIGH_AR_8 0x356884
+
+#define mmSIF_RTR_CTRL_5_RANGE_SEC_BASE_HIGH_AR_9 0x356888
+
+#define mmSIF_RTR_CTRL_5_RANGE_SEC_BASE_HIGH_AR_10 0x35688C
+
+#define mmSIF_RTR_CTRL_5_RANGE_SEC_BASE_HIGH_AR_11 0x356890
+
+#define mmSIF_RTR_CTRL_5_RANGE_SEC_BASE_HIGH_AR_12 0x356894
+
+#define mmSIF_RTR_CTRL_5_RANGE_SEC_BASE_HIGH_AR_13 0x356898
+
+#define mmSIF_RTR_CTRL_5_RANGE_SEC_BASE_HIGH_AR_14 0x35689C
+
+#define mmSIF_RTR_CTRL_5_RANGE_SEC_BASE_HIGH_AR_15 0x3568A0
+
+#define mmSIF_RTR_CTRL_5_RANGE_SEC_MASK_LOW_AR_0 0x3568A4
+
+#define mmSIF_RTR_CTRL_5_RANGE_SEC_MASK_LOW_AR_1 0x3568A8
+
+#define mmSIF_RTR_CTRL_5_RANGE_SEC_MASK_LOW_AR_2 0x3568AC
+
+#define mmSIF_RTR_CTRL_5_RANGE_SEC_MASK_LOW_AR_3 0x3568B0
+
+#define mmSIF_RTR_CTRL_5_RANGE_SEC_MASK_LOW_AR_4 0x3568B4
+
+#define mmSIF_RTR_CTRL_5_RANGE_SEC_MASK_LOW_AR_5 0x3568B8
+
+#define mmSIF_RTR_CTRL_5_RANGE_SEC_MASK_LOW_AR_6 0x3568BC
+
+#define mmSIF_RTR_CTRL_5_RANGE_SEC_MASK_LOW_AR_7 0x3568C0
+
+#define mmSIF_RTR_CTRL_5_RANGE_SEC_MASK_LOW_AR_8 0x3568C4
+
+#define mmSIF_RTR_CTRL_5_RANGE_SEC_MASK_LOW_AR_9 0x3568C8
+
+#define mmSIF_RTR_CTRL_5_RANGE_SEC_MASK_LOW_AR_10 0x3568CC
+
+#define mmSIF_RTR_CTRL_5_RANGE_SEC_MASK_LOW_AR_11 0x3568D0
+
+#define mmSIF_RTR_CTRL_5_RANGE_SEC_MASK_LOW_AR_12 0x3568D4
+
+#define mmSIF_RTR_CTRL_5_RANGE_SEC_MASK_LOW_AR_13 0x3568D8
+
+#define mmSIF_RTR_CTRL_5_RANGE_SEC_MASK_LOW_AR_14 0x3568DC
+
+#define mmSIF_RTR_CTRL_5_RANGE_SEC_MASK_LOW_AR_15 0x3568E0
+
+#define mmSIF_RTR_CTRL_5_RANGE_SEC_MASK_HIGH_AR_0 0x3568E4
+
+#define mmSIF_RTR_CTRL_5_RANGE_SEC_MASK_HIGH_AR_1 0x3568E8
+
+#define mmSIF_RTR_CTRL_5_RANGE_SEC_MASK_HIGH_AR_2 0x3568EC
+
+#define mmSIF_RTR_CTRL_5_RANGE_SEC_MASK_HIGH_AR_3 0x3568F0
+
+#define mmSIF_RTR_CTRL_5_RANGE_SEC_MASK_HIGH_AR_4 0x3568F4
+
+#define mmSIF_RTR_CTRL_5_RANGE_SEC_MASK_HIGH_AR_5 0x3568F8
+
+#define mmSIF_RTR_CTRL_5_RANGE_SEC_MASK_HIGH_AR_6 0x3568FC
+
+#define mmSIF_RTR_CTRL_5_RANGE_SEC_MASK_HIGH_AR_7 0x356900
+
+#define mmSIF_RTR_CTRL_5_RANGE_SEC_MASK_HIGH_AR_8 0x356904
+
+#define mmSIF_RTR_CTRL_5_RANGE_SEC_MASK_HIGH_AR_9 0x356908
+
+#define mmSIF_RTR_CTRL_5_RANGE_SEC_MASK_HIGH_AR_10 0x35690C
+
+#define mmSIF_RTR_CTRL_5_RANGE_SEC_MASK_HIGH_AR_11 0x356910
+
+#define mmSIF_RTR_CTRL_5_RANGE_SEC_MASK_HIGH_AR_12 0x356914
+
+#define mmSIF_RTR_CTRL_5_RANGE_SEC_MASK_HIGH_AR_13 0x356918
+
+#define mmSIF_RTR_CTRL_5_RANGE_SEC_MASK_HIGH_AR_14 0x35691C
+
+#define mmSIF_RTR_CTRL_5_RANGE_SEC_MASK_HIGH_AR_15 0x356920
+
+#define mmSIF_RTR_CTRL_5_RANGE_PRIV_BASE_LOW_AR_0 0x356924
+
+#define mmSIF_RTR_CTRL_5_RANGE_PRIV_BASE_LOW_AR_1 0x356928
+
+#define mmSIF_RTR_CTRL_5_RANGE_PRIV_BASE_LOW_AR_2 0x35692C
+
+#define mmSIF_RTR_CTRL_5_RANGE_PRIV_BASE_LOW_AR_3 0x356930
+
+#define mmSIF_RTR_CTRL_5_RANGE_PRIV_BASE_LOW_AR_4 0x356934
+
+#define mmSIF_RTR_CTRL_5_RANGE_PRIV_BASE_LOW_AR_5 0x356938
+
+#define mmSIF_RTR_CTRL_5_RANGE_PRIV_BASE_LOW_AR_6 0x35693C
+
+#define mmSIF_RTR_CTRL_5_RANGE_PRIV_BASE_LOW_AR_7 0x356940
+
+#define mmSIF_RTR_CTRL_5_RANGE_PRIV_BASE_LOW_AR_8 0x356944
+
+#define mmSIF_RTR_CTRL_5_RANGE_PRIV_BASE_LOW_AR_9 0x356948
+
+#define mmSIF_RTR_CTRL_5_RANGE_PRIV_BASE_LOW_AR_10 0x35694C
+
+#define mmSIF_RTR_CTRL_5_RANGE_PRIV_BASE_LOW_AR_11 0x356950
+
+#define mmSIF_RTR_CTRL_5_RANGE_PRIV_BASE_LOW_AR_12 0x356954
+
+#define mmSIF_RTR_CTRL_5_RANGE_PRIV_BASE_LOW_AR_13 0x356958
+
+#define mmSIF_RTR_CTRL_5_RANGE_PRIV_BASE_LOW_AR_14 0x35695C
+
+#define mmSIF_RTR_CTRL_5_RANGE_PRIV_BASE_LOW_AR_15 0x356960
+
+#define mmSIF_RTR_CTRL_5_RANGE_PRIV_BASE_HIGH_AR_0 0x356964
+
+#define mmSIF_RTR_CTRL_5_RANGE_PRIV_BASE_HIGH_AR_1 0x356968
+
+#define mmSIF_RTR_CTRL_5_RANGE_PRIV_BASE_HIGH_AR_2 0x35696C
+
+#define mmSIF_RTR_CTRL_5_RANGE_PRIV_BASE_HIGH_AR_3 0x356970
+
+#define mmSIF_RTR_CTRL_5_RANGE_PRIV_BASE_HIGH_AR_4 0x356974
+
+#define mmSIF_RTR_CTRL_5_RANGE_PRIV_BASE_HIGH_AR_5 0x356978
+
+#define mmSIF_RTR_CTRL_5_RANGE_PRIV_BASE_HIGH_AR_6 0x35697C
+
+#define mmSIF_RTR_CTRL_5_RANGE_PRIV_BASE_HIGH_AR_7 0x356980
+
+#define mmSIF_RTR_CTRL_5_RANGE_PRIV_BASE_HIGH_AR_8 0x356984
+
+#define mmSIF_RTR_CTRL_5_RANGE_PRIV_BASE_HIGH_AR_9 0x356988
+
+#define mmSIF_RTR_CTRL_5_RANGE_PRIV_BASE_HIGH_AR_10 0x35698C
+
+#define mmSIF_RTR_CTRL_5_RANGE_PRIV_BASE_HIGH_AR_11 0x356990
+
+#define mmSIF_RTR_CTRL_5_RANGE_PRIV_BASE_HIGH_AR_12 0x356994
+
+#define mmSIF_RTR_CTRL_5_RANGE_PRIV_BASE_HIGH_AR_13 0x356998
+
+#define mmSIF_RTR_CTRL_5_RANGE_PRIV_BASE_HIGH_AR_14 0x35699C
+
+#define mmSIF_RTR_CTRL_5_RANGE_PRIV_BASE_HIGH_AR_15 0x3569A0
+
+#define mmSIF_RTR_CTRL_5_RANGE_PRIV_MASK_LOW_AR_0 0x3569A4
+
+#define mmSIF_RTR_CTRL_5_RANGE_PRIV_MASK_LOW_AR_1 0x3569A8
+
+#define mmSIF_RTR_CTRL_5_RANGE_PRIV_MASK_LOW_AR_2 0x3569AC
+
+#define mmSIF_RTR_CTRL_5_RANGE_PRIV_MASK_LOW_AR_3 0x3569B0
+
+#define mmSIF_RTR_CTRL_5_RANGE_PRIV_MASK_LOW_AR_4 0x3569B4
+
+#define mmSIF_RTR_CTRL_5_RANGE_PRIV_MASK_LOW_AR_5 0x3569B8
+
+#define mmSIF_RTR_CTRL_5_RANGE_PRIV_MASK_LOW_AR_6 0x3569BC
+
+#define mmSIF_RTR_CTRL_5_RANGE_PRIV_MASK_LOW_AR_7 0x3569C0
+
+#define mmSIF_RTR_CTRL_5_RANGE_PRIV_MASK_LOW_AR_8 0x3569C4
+
+#define mmSIF_RTR_CTRL_5_RANGE_PRIV_MASK_LOW_AR_9 0x3569C8
+
+#define mmSIF_RTR_CTRL_5_RANGE_PRIV_MASK_LOW_AR_10 0x3569CC
+
+#define mmSIF_RTR_CTRL_5_RANGE_PRIV_MASK_LOW_AR_11 0x3569D0
+
+#define mmSIF_RTR_CTRL_5_RANGE_PRIV_MASK_LOW_AR_12 0x3569D4
+
+#define mmSIF_RTR_CTRL_5_RANGE_PRIV_MASK_LOW_AR_13 0x3569D8
+
+#define mmSIF_RTR_CTRL_5_RANGE_PRIV_MASK_LOW_AR_14 0x3569DC
+
+#define mmSIF_RTR_CTRL_5_RANGE_PRIV_MASK_LOW_AR_15 0x3569E0
+
+#define mmSIF_RTR_CTRL_5_RANGE_PRIV_MASK_HIGH_AR_0 0x3569E4
+
+#define mmSIF_RTR_CTRL_5_RANGE_PRIV_MASK_HIGH_AR_1 0x3569E8
+
+#define mmSIF_RTR_CTRL_5_RANGE_PRIV_MASK_HIGH_AR_2 0x3569EC
+
+#define mmSIF_RTR_CTRL_5_RANGE_PRIV_MASK_HIGH_AR_3 0x3569F0
+
+#define mmSIF_RTR_CTRL_5_RANGE_PRIV_MASK_HIGH_AR_4 0x3569F4
+
+#define mmSIF_RTR_CTRL_5_RANGE_PRIV_MASK_HIGH_AR_5 0x3569F8
+
+#define mmSIF_RTR_CTRL_5_RANGE_PRIV_MASK_HIGH_AR_6 0x3569FC
+
+#define mmSIF_RTR_CTRL_5_RANGE_PRIV_MASK_HIGH_AR_7 0x356A00
+
+#define mmSIF_RTR_CTRL_5_RANGE_PRIV_MASK_HIGH_AR_8 0x356A04
+
+#define mmSIF_RTR_CTRL_5_RANGE_PRIV_MASK_HIGH_AR_9 0x356A08
+
+#define mmSIF_RTR_CTRL_5_RANGE_PRIV_MASK_HIGH_AR_10 0x356A0C
+
+#define mmSIF_RTR_CTRL_5_RANGE_PRIV_MASK_HIGH_AR_11 0x356A10
+
+#define mmSIF_RTR_CTRL_5_RANGE_PRIV_MASK_HIGH_AR_12 0x356A14
+
+#define mmSIF_RTR_CTRL_5_RANGE_PRIV_MASK_HIGH_AR_13 0x356A18
+
+#define mmSIF_RTR_CTRL_5_RANGE_PRIV_MASK_HIGH_AR_14 0x356A1C
+
+#define mmSIF_RTR_CTRL_5_RANGE_PRIV_MASK_HIGH_AR_15 0x356A20
+
+#define mmSIF_RTR_CTRL_5_RANGE_SEC_HIT_AW 0x356A64
+
+#define mmSIF_RTR_CTRL_5_RANGE_SEC_HIT_AR 0x356A68
+
+#define mmSIF_RTR_CTRL_5_RANGE_PRIV_HIT_AW 0x356A6C
+
+#define mmSIF_RTR_CTRL_5_RANGE_PRIV_HIT_AR 0x356A70
+
+#define mmSIF_RTR_CTRL_5_RGL_CFG 0x356B64
+
+#define mmSIF_RTR_CTRL_5_RGL_SHIFT 0x356B68
+
+#define mmSIF_RTR_CTRL_5_RGL_EXPECTED_LAT_0 0x356B6C
+
+#define mmSIF_RTR_CTRL_5_RGL_EXPECTED_LAT_1 0x356B70
+
+#define mmSIF_RTR_CTRL_5_RGL_EXPECTED_LAT_2 0x356B74
+
+#define mmSIF_RTR_CTRL_5_RGL_EXPECTED_LAT_3 0x356B78
+
+#define mmSIF_RTR_CTRL_5_RGL_EXPECTED_LAT_4 0x356B7C
+
+#define mmSIF_RTR_CTRL_5_RGL_EXPECTED_LAT_5 0x356B80
+
+#define mmSIF_RTR_CTRL_5_RGL_EXPECTED_LAT_6 0x356B84
+
+#define mmSIF_RTR_CTRL_5_RGL_EXPECTED_LAT_7 0x356B88
+
+#define mmSIF_RTR_CTRL_5_RGL_TOKEN_0 0x356BAC
+
+#define mmSIF_RTR_CTRL_5_RGL_TOKEN_1 0x356BB0
+
+#define mmSIF_RTR_CTRL_5_RGL_TOKEN_2 0x356BB4
+
+#define mmSIF_RTR_CTRL_5_RGL_TOKEN_3 0x356BB8
+
+#define mmSIF_RTR_CTRL_5_RGL_TOKEN_4 0x356BBC
+
+#define mmSIF_RTR_CTRL_5_RGL_TOKEN_5 0x356BC0
+
+#define mmSIF_RTR_CTRL_5_RGL_TOKEN_6 0x356BC4
+
+#define mmSIF_RTR_CTRL_5_RGL_TOKEN_7 0x356BC8
+
+#define mmSIF_RTR_CTRL_5_RGL_BANK_ID_0 0x356BEC
+
+#define mmSIF_RTR_CTRL_5_RGL_BANK_ID_1 0x356BF0
+
+#define mmSIF_RTR_CTRL_5_RGL_BANK_ID_2 0x356BF4
+
+#define mmSIF_RTR_CTRL_5_RGL_BANK_ID_3 0x356BF8
+
+#define mmSIF_RTR_CTRL_5_RGL_BANK_ID_4 0x356BFC
+
+#define mmSIF_RTR_CTRL_5_RGL_BANK_ID_5 0x356C00
+
+#define mmSIF_RTR_CTRL_5_RGL_BANK_ID_6 0x356C04
+
+#define mmSIF_RTR_CTRL_5_RGL_BANK_ID_7 0x356C08
+
+#define mmSIF_RTR_CTRL_5_RGL_WDT 0x356C2C
+
+#define mmSIF_RTR_CTRL_5_E2E_AR_HBM0_CH0_CTR_WRAP 0x356C30
+
+#define mmSIF_RTR_CTRL_5_E2E_AR_HBM0_CH1_CTR_WRAP 0x356C34
+
+#define mmSIF_RTR_CTRL_5_E2E_AR_HBM1_CH0_CTR_WRAP 0x356C38
+
+#define mmSIF_RTR_CTRL_5_E2E_AR_HBM1_CH1_CTR_WRAP 0x356C3C
+
+#define mmSIF_RTR_CTRL_5_E2E_AR_HBM2_CH0_CTR_WRAP 0x356C40
+
+#define mmSIF_RTR_CTRL_5_E2E_AR_HBM2_CH1_CTR_WRAP 0x356C44
+
+#define mmSIF_RTR_CTRL_5_E2E_AR_HBM3_CH0_CTR_WRAP 0x356C48
+
+#define mmSIF_RTR_CTRL_5_E2E_AR_HBM3_CH1_CTR_WRAP 0x356C4C
+
+#define mmSIF_RTR_CTRL_5_E2E_AR_HBM0_CH0_CTR_CNT 0x356C50
+
+#define mmSIF_RTR_CTRL_5_E2E_AR_HBM0_CH1_CTR_CNT 0x356C54
+
+#define mmSIF_RTR_CTRL_5_E2E_AR_HBM1_CH0_CTR_CNT 0x356C58
+
+#define mmSIF_RTR_CTRL_5_E2E_AR_HBM1_CH1_CTR_CNT 0x356C5C
+
+#define mmSIF_RTR_CTRL_5_E2E_AR_HBM2_CH0_CTR_CNT 0x356C60
+
+#define mmSIF_RTR_CTRL_5_E2E_AR_HBM2_CH1_CTR_CNT 0x356C64
+
+#define mmSIF_RTR_CTRL_5_E2E_AR_HBM3_CH0_CTR_CNT 0x356C68
+
+#define mmSIF_RTR_CTRL_5_E2E_AR_HBM3_CH1_CTR_CNT 0x356C6C
+
+#define mmSIF_RTR_CTRL_5_E2E_AW_HBM0_CH0_CTR_WRAP 0x356C70
+
+#define mmSIF_RTR_CTRL_5_E2E_AW_HBM0_CH1_CTR_WRAP 0x356C74
+
+#define mmSIF_RTR_CTRL_5_E2E_AW_HBM1_CH0_CTR_WRAP 0x356C78
+
+#define mmSIF_RTR_CTRL_5_E2E_AW_HBM1_CH1_CTR_WRAP 0x356C7C
+
+#define mmSIF_RTR_CTRL_5_E2E_AW_HBM2_CH0_CTR_WRAP 0x356C80
+
+#define mmSIF_RTR_CTRL_5_E2E_AW_HBM2_CH1_CTR_WRAP 0x356C84
+
+#define mmSIF_RTR_CTRL_5_E2E_AW_HBM3_CH0_CTR_WRAP 0x356C88
+
+#define mmSIF_RTR_CTRL_5_E2E_AW_HBM3_CH1_CTR_WRAP 0x356C8C
+
+#define mmSIF_RTR_CTRL_5_E2E_AW_HBM0_CH0_CTR_CNT 0x356C90
+
+#define mmSIF_RTR_CTRL_5_E2E_AW_HBM0_CH1_CTR_CNT 0x356C94
+
+#define mmSIF_RTR_CTRL_5_E2E_AW_HBM1_CH0_CTR_CNT 0x356C98
+
+#define mmSIF_RTR_CTRL_5_E2E_AW_HBM1_CH1_CTR_CNT 0x356C9C
+
+#define mmSIF_RTR_CTRL_5_E2E_AW_HBM2_CH0_CTR_CNT 0x356CA0
+
+#define mmSIF_RTR_CTRL_5_E2E_AW_HBM2_CH1_CTR_CNT 0x356CA4
+
+#define mmSIF_RTR_CTRL_5_E2E_AW_HBM3_CH0_CTR_CNT 0x356CA8
+
+#define mmSIF_RTR_CTRL_5_E2E_AW_HBM3_CH1_CTR_CNT 0x356CAC
+
+#define mmSIF_RTR_CTRL_5_NL_HBM_PC_SEL_0 0x356CB0
+
+#define mmSIF_RTR_CTRL_5_NL_HBM_PC_SEL_1 0x356CB4
+
+#define mmSIF_RTR_CTRL_5_NL_HBM_PC_SEL_2 0x356CB8
+
+#define mmSIF_RTR_CTRL_5_NL_HBM_PC_SEL_3 0x356CBC
+
+#endif /* ASIC_REG_SIF_RTR_CTRL_5_REGS_H_ */
diff --git a/drivers/accel/habanalabs/include/gaudi/asic_reg/sif_rtr_ctrl_6_regs.h b/drivers/accel/habanalabs/include/gaudi/asic_reg/sif_rtr_ctrl_6_regs.h
new file mode 100644
index 0000000000..a9ea89aa64
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi/asic_reg/sif_rtr_ctrl_6_regs.h
@@ -0,0 +1,896 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2016-2018 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ ** DO NOT EDIT BELOW **
+ ************************************/
+
+#ifndef ASIC_REG_SIF_RTR_CTRL_6_REGS_H_
+#define ASIC_REG_SIF_RTR_CTRL_6_REGS_H_
+
+/*
+ *****************************************
+ * SIF_RTR_CTRL_6 (Prototype: RTR_CTRL)
+ *****************************************
+ */
+
+#define mmSIF_RTR_CTRL_6_PERM_SEL 0x366108
+
+#define mmSIF_RTR_CTRL_6_HBM_POLY_H3_0 0x366114
+
+#define mmSIF_RTR_CTRL_6_HBM_POLY_H3_1 0x366118
+
+#define mmSIF_RTR_CTRL_6_HBM_POLY_H3_2 0x36611C
+
+#define mmSIF_RTR_CTRL_6_HBM_POLY_H3_3 0x366120
+
+#define mmSIF_RTR_CTRL_6_HBM_POLY_H3_4 0x366124
+
+#define mmSIF_RTR_CTRL_6_HBM_POLY_H3_5 0x366128
+
+#define mmSIF_RTR_CTRL_6_HBM_POLY_H3_6 0x36612C
+
+#define mmSIF_RTR_CTRL_6_HBM_POLY_H3_7 0x366130
+
+#define mmSIF_RTR_CTRL_6_HBM_POLY_H3_8 0x366134
+
+#define mmSIF_RTR_CTRL_6_HBM_POLY_H3_9 0x366138
+
+#define mmSIF_RTR_CTRL_6_HBM_POLY_H3_10 0x36613C
+
+#define mmSIF_RTR_CTRL_6_HBM_POLY_H3_11 0x366140
+
+#define mmSIF_RTR_CTRL_6_HBM_POLY_H3_12 0x366144
+
+#define mmSIF_RTR_CTRL_6_HBM_POLY_H3_13 0x366148
+
+#define mmSIF_RTR_CTRL_6_HBM_POLY_H3_14 0x36614C
+
+#define mmSIF_RTR_CTRL_6_HBM_POLY_H3_15 0x366150
+
+#define mmSIF_RTR_CTRL_6_HBM_POLY_H3_16 0x366154
+
+#define mmSIF_RTR_CTRL_6_HBM_POLY_H3_17 0x366158
+
+#define mmSIF_RTR_CTRL_6_HBM_POLY_H3_18 0x36615C
+
+#define mmSIF_RTR_CTRL_6_HBM_POLY_H3_19 0x366160
+
+#define mmSIF_RTR_CTRL_6_HBM_POLY_H3_20 0x366164
+
+#define mmSIF_RTR_CTRL_6_HBM_POLY_H3_21 0x366168
+
+#define mmSIF_RTR_CTRL_6_HBM_POLY_H3_22 0x36616C
+
+#define mmSIF_RTR_CTRL_6_HBM_POLY_H3_23 0x366170
+
+#define mmSIF_RTR_CTRL_6_HBM_POLY_H3_24 0x366174
+
+#define mmSIF_RTR_CTRL_6_HBM_POLY_H3_25 0x366178
+
+#define mmSIF_RTR_CTRL_6_HBM_POLY_H3_26 0x36617C
+
+#define mmSIF_RTR_CTRL_6_HBM_POLY_H3_27 0x366180
+
+#define mmSIF_RTR_CTRL_6_SRAM_POLY_H3_0 0x366184
+
+#define mmSIF_RTR_CTRL_6_SRAM_POLY_H3_1 0x366188
+
+#define mmSIF_RTR_CTRL_6_SRAM_POLY_H3_2 0x36618C
+
+#define mmSIF_RTR_CTRL_6_SRAM_POLY_H3_3 0x366190
+
+#define mmSIF_RTR_CTRL_6_SRAM_POLY_H3_4 0x366194
+
+#define mmSIF_RTR_CTRL_6_SRAM_POLY_H3_5 0x366198
+
+#define mmSIF_RTR_CTRL_6_SRAM_POLY_H3_6 0x36619C
+
+#define mmSIF_RTR_CTRL_6_SRAM_POLY_H3_7 0x3661A0
+
+#define mmSIF_RTR_CTRL_6_SRAM_POLY_H3_8 0x3661A4
+
+#define mmSIF_RTR_CTRL_6_SRAM_POLY_H3_9 0x3661A8
+
+#define mmSIF_RTR_CTRL_6_SRAM_POLY_H3_10 0x3661AC
+
+#define mmSIF_RTR_CTRL_6_SRAM_POLY_H3_11 0x3661B0
+
+#define mmSIF_RTR_CTRL_6_SRAM_POLY_H3_12 0x3661B4
+
+#define mmSIF_RTR_CTRL_6_SRAM_POLY_H3_13 0x3661B8
+
+#define mmSIF_RTR_CTRL_6_SRAM_POLY_H3_14 0x3661BC
+
+#define mmSIF_RTR_CTRL_6_SCRAM_SRAM_EN 0x36626C
+
+#define mmSIF_RTR_CTRL_6_RL_HBM_EN 0x366274
+
+#define mmSIF_RTR_CTRL_6_RL_HBM_SAT 0x366278
+
+#define mmSIF_RTR_CTRL_6_RL_HBM_RST 0x36627C
+
+#define mmSIF_RTR_CTRL_6_RL_HBM_TIMEOUT 0x366280
+
+#define mmSIF_RTR_CTRL_6_SCRAM_HBM_EN 0x366284
+
+#define mmSIF_RTR_CTRL_6_RL_PCI_EN 0x366288
+
+#define mmSIF_RTR_CTRL_6_RL_PCI_SAT 0x36628C
+
+#define mmSIF_RTR_CTRL_6_RL_PCI_RST 0x366290
+
+#define mmSIF_RTR_CTRL_6_RL_PCI_TIMEOUT 0x366294
+
+#define mmSIF_RTR_CTRL_6_RL_SRAM_EN 0x36629C
+
+#define mmSIF_RTR_CTRL_6_RL_SRAM_SAT 0x3662A0
+
+#define mmSIF_RTR_CTRL_6_RL_SRAM_RST 0x3662A4
+
+#define mmSIF_RTR_CTRL_6_RL_SRAM_TIMEOUT 0x3662AC
+
+#define mmSIF_RTR_CTRL_6_RL_SRAM_RED 0x3662B4
+
+#define mmSIF_RTR_CTRL_6_E2E_HBM_EN 0x3662EC
+
+#define mmSIF_RTR_CTRL_6_E2E_PCI_EN 0x3662F0
+
+#define mmSIF_RTR_CTRL_6_E2E_HBM_WR_SIZE 0x3662F4
+
+#define mmSIF_RTR_CTRL_6_E2E_PCI_WR_SIZE 0x3662F8
+
+#define mmSIF_RTR_CTRL_6_E2E_AW_PCI_CTR_SET_EN 0x366404
+
+#define mmSIF_RTR_CTRL_6_E2E_AW_PCI_CTR_SET 0x366408
+
+#define mmSIF_RTR_CTRL_6_E2E_AW_PCI_CTR_WRAP 0x36640C
+
+#define mmSIF_RTR_CTRL_6_E2E_AW_PCI_CTR_CNT 0x366410
+
+#define mmSIF_RTR_CTRL_6_E2E_AW_HBM_CTR_SET_EN 0x366414
+
+#define mmSIF_RTR_CTRL_6_E2E_AW_HBM_CTR_SET 0x366418
+
+#define mmSIF_RTR_CTRL_6_E2E_HBM_RD_SIZE 0x36641C
+
+#define mmSIF_RTR_CTRL_6_E2E_PCI_RD_SIZE 0x366420
+
+#define mmSIF_RTR_CTRL_6_E2E_AR_PCI_CTR_SET_EN 0x366424
+
+#define mmSIF_RTR_CTRL_6_E2E_AR_PCI_CTR_SET 0x366428
+
+#define mmSIF_RTR_CTRL_6_E2E_AR_PCI_CTR_WRAP 0x36642C
+
+#define mmSIF_RTR_CTRL_6_E2E_AR_PCI_CTR_CNT 0x366430
+
+#define mmSIF_RTR_CTRL_6_E2E_AR_HBM_CTR_SET_EN 0x366434
+
+#define mmSIF_RTR_CTRL_6_E2E_AR_HBM_CTR_SET 0x366438
+
+#define mmSIF_RTR_CTRL_6_NL_HBM_SEL_0 0x366450
+
+#define mmSIF_RTR_CTRL_6_NL_HBM_SEL_1 0x366454
+
+#define mmSIF_RTR_CTRL_6_NON_LIN_EN 0x366480
+
+#define mmSIF_RTR_CTRL_6_NL_SRAM_BANK_0 0x366500
+
+#define mmSIF_RTR_CTRL_6_NL_SRAM_BANK_1 0x366504
+
+#define mmSIF_RTR_CTRL_6_NL_SRAM_BANK_2 0x366508
+
+#define mmSIF_RTR_CTRL_6_NL_SRAM_BANK_3 0x36650C
+
+#define mmSIF_RTR_CTRL_6_NL_SRAM_BANK_4 0x366510
+
+#define mmSIF_RTR_CTRL_6_NL_SRAM_OFFSET_0 0x366514
+
+#define mmSIF_RTR_CTRL_6_NL_SRAM_OFFSET_1 0x366520
+
+#define mmSIF_RTR_CTRL_6_NL_SRAM_OFFSET_2 0x366524
+
+#define mmSIF_RTR_CTRL_6_NL_SRAM_OFFSET_3 0x366528
+
+#define mmSIF_RTR_CTRL_6_NL_SRAM_OFFSET_4 0x36652C
+
+#define mmSIF_RTR_CTRL_6_NL_SRAM_OFFSET_5 0x366530
+
+#define mmSIF_RTR_CTRL_6_NL_SRAM_OFFSET_6 0x366534
+
+#define mmSIF_RTR_CTRL_6_NL_SRAM_OFFSET_7 0x366538
+
+#define mmSIF_RTR_CTRL_6_NL_SRAM_OFFSET_8 0x36653C
+
+#define mmSIF_RTR_CTRL_6_NL_SRAM_OFFSET_9 0x366540
+
+#define mmSIF_RTR_CTRL_6_NL_HBM_OFFSET_0 0x366550
+
+#define mmSIF_RTR_CTRL_6_NL_HBM_OFFSET_1 0x366554
+
+#define mmSIF_RTR_CTRL_6_NL_HBM_OFFSET_2 0x366558
+
+#define mmSIF_RTR_CTRL_6_NL_HBM_OFFSET_3 0x36655C
+
+#define mmSIF_RTR_CTRL_6_NL_HBM_OFFSET_4 0x366560
+
+#define mmSIF_RTR_CTRL_6_NL_HBM_OFFSET_5 0x366564
+
+#define mmSIF_RTR_CTRL_6_NL_HBM_OFFSET_6 0x366568
+
+#define mmSIF_RTR_CTRL_6_NL_HBM_OFFSET_7 0x36656C
+
+#define mmSIF_RTR_CTRL_6_NL_HBM_OFFSET_8 0x366570
+
+#define mmSIF_RTR_CTRL_6_NL_HBM_OFFSET_9 0x366574
+
+#define mmSIF_RTR_CTRL_6_NL_HBM_OFFSET_10 0x366578
+
+#define mmSIF_RTR_CTRL_6_NL_HBM_OFFSET_11 0x36657C
+
+#define mmSIF_RTR_CTRL_6_NL_HBM_OFFSET_12 0x366580
+
+#define mmSIF_RTR_CTRL_6_NL_HBM_OFFSET_13 0x366584
+
+#define mmSIF_RTR_CTRL_6_NL_HBM_OFFSET_14 0x366588
+
+#define mmSIF_RTR_CTRL_6_NL_HBM_OFFSET_15 0x36658C
+
+#define mmSIF_RTR_CTRL_6_NL_HBM_OFFSET_16 0x366590
+
+#define mmSIF_RTR_CTRL_6_NL_HBM_OFFSET_17 0x366594
+
+#define mmSIF_RTR_CTRL_6_NL_HBM_OFFSET_18 0x366598
+
+#define mmSIF_RTR_CTRL_6_RANGE_SEC_BASE_LOW_AW_0 0x3665E4
+
+#define mmSIF_RTR_CTRL_6_RANGE_SEC_BASE_LOW_AW_1 0x3665E8
+
+#define mmSIF_RTR_CTRL_6_RANGE_SEC_BASE_LOW_AW_2 0x3665EC
+
+#define mmSIF_RTR_CTRL_6_RANGE_SEC_BASE_LOW_AW_3 0x3665F0
+
+#define mmSIF_RTR_CTRL_6_RANGE_SEC_BASE_LOW_AW_4 0x3665F4
+
+#define mmSIF_RTR_CTRL_6_RANGE_SEC_BASE_LOW_AW_5 0x3665F8
+
+#define mmSIF_RTR_CTRL_6_RANGE_SEC_BASE_LOW_AW_6 0x3665FC
+
+#define mmSIF_RTR_CTRL_6_RANGE_SEC_BASE_LOW_AW_7 0x366600
+
+#define mmSIF_RTR_CTRL_6_RANGE_SEC_BASE_LOW_AW_8 0x366604
+
+#define mmSIF_RTR_CTRL_6_RANGE_SEC_BASE_LOW_AW_9 0x366608
+
+#define mmSIF_RTR_CTRL_6_RANGE_SEC_BASE_LOW_AW_10 0x36660C
+
+#define mmSIF_RTR_CTRL_6_RANGE_SEC_BASE_LOW_AW_11 0x366610
+
+#define mmSIF_RTR_CTRL_6_RANGE_SEC_BASE_LOW_AW_12 0x366614
+
+#define mmSIF_RTR_CTRL_6_RANGE_SEC_BASE_LOW_AW_13 0x366618
+
+#define mmSIF_RTR_CTRL_6_RANGE_SEC_BASE_LOW_AW_14 0x36661C
+
+#define mmSIF_RTR_CTRL_6_RANGE_SEC_BASE_LOW_AW_15 0x366620
+
+#define mmSIF_RTR_CTRL_6_RANGE_SEC_BASE_HIGH_AW_0 0x366624
+
+#define mmSIF_RTR_CTRL_6_RANGE_SEC_BASE_HIGH_AW_1 0x366628
+
+#define mmSIF_RTR_CTRL_6_RANGE_SEC_BASE_HIGH_AW_2 0x36662C
+
+#define mmSIF_RTR_CTRL_6_RANGE_SEC_BASE_HIGH_AW_3 0x366630
+
+#define mmSIF_RTR_CTRL_6_RANGE_SEC_BASE_HIGH_AW_4 0x366634
+
+#define mmSIF_RTR_CTRL_6_RANGE_SEC_BASE_HIGH_AW_5 0x366638
+
+#define mmSIF_RTR_CTRL_6_RANGE_SEC_BASE_HIGH_AW_6 0x36663C
+
+#define mmSIF_RTR_CTRL_6_RANGE_SEC_BASE_HIGH_AW_7 0x366640
+
+#define mmSIF_RTR_CTRL_6_RANGE_SEC_BASE_HIGH_AW_8 0x366644
+
+#define mmSIF_RTR_CTRL_6_RANGE_SEC_BASE_HIGH_AW_9 0x366648
+
+#define mmSIF_RTR_CTRL_6_RANGE_SEC_BASE_HIGH_AW_10 0x36664C
+
+#define mmSIF_RTR_CTRL_6_RANGE_SEC_BASE_HIGH_AW_11 0x366650
+
+#define mmSIF_RTR_CTRL_6_RANGE_SEC_BASE_HIGH_AW_12 0x366654
+
+#define mmSIF_RTR_CTRL_6_RANGE_SEC_BASE_HIGH_AW_13 0x366658
+
+#define mmSIF_RTR_CTRL_6_RANGE_SEC_BASE_HIGH_AW_14 0x36665C
+
+#define mmSIF_RTR_CTRL_6_RANGE_SEC_BASE_HIGH_AW_15 0x366660
+
+#define mmSIF_RTR_CTRL_6_RANGE_SEC_MASK_LOW_AW_0 0x366664
+
+#define mmSIF_RTR_CTRL_6_RANGE_SEC_MASK_LOW_AW_1 0x366668
+
+#define mmSIF_RTR_CTRL_6_RANGE_SEC_MASK_LOW_AW_2 0x36666C
+
+#define mmSIF_RTR_CTRL_6_RANGE_SEC_MASK_LOW_AW_3 0x366670
+
+#define mmSIF_RTR_CTRL_6_RANGE_SEC_MASK_LOW_AW_4 0x366674
+
+#define mmSIF_RTR_CTRL_6_RANGE_SEC_MASK_LOW_AW_5 0x366678
+
+#define mmSIF_RTR_CTRL_6_RANGE_SEC_MASK_LOW_AW_6 0x36667C
+
+#define mmSIF_RTR_CTRL_6_RANGE_SEC_MASK_LOW_AW_7 0x366680
+
+#define mmSIF_RTR_CTRL_6_RANGE_SEC_MASK_LOW_AW_8 0x366684
+
+#define mmSIF_RTR_CTRL_6_RANGE_SEC_MASK_LOW_AW_9 0x366688
+
+#define mmSIF_RTR_CTRL_6_RANGE_SEC_MASK_LOW_AW_10 0x36668C
+
+#define mmSIF_RTR_CTRL_6_RANGE_SEC_MASK_LOW_AW_11 0x366690
+
+#define mmSIF_RTR_CTRL_6_RANGE_SEC_MASK_LOW_AW_12 0x366694
+
+#define mmSIF_RTR_CTRL_6_RANGE_SEC_MASK_LOW_AW_13 0x366698
+
+#define mmSIF_RTR_CTRL_6_RANGE_SEC_MASK_LOW_AW_14 0x36669C
+
+#define mmSIF_RTR_CTRL_6_RANGE_SEC_MASK_LOW_AW_15 0x3666A0
+
+#define mmSIF_RTR_CTRL_6_RANGE_SEC_MASK_HIGH_AW_0 0x3666A4
+
+#define mmSIF_RTR_CTRL_6_RANGE_SEC_MASK_HIGH_AW_1 0x3666A8
+
+#define mmSIF_RTR_CTRL_6_RANGE_SEC_MASK_HIGH_AW_2 0x3666AC
+
+#define mmSIF_RTR_CTRL_6_RANGE_SEC_MASK_HIGH_AW_3 0x3666B0
+
+#define mmSIF_RTR_CTRL_6_RANGE_SEC_MASK_HIGH_AW_4 0x3666B4
+
+#define mmSIF_RTR_CTRL_6_RANGE_SEC_MASK_HIGH_AW_5 0x3666B8
+
+#define mmSIF_RTR_CTRL_6_RANGE_SEC_MASK_HIGH_AW_6 0x3666BC
+
+#define mmSIF_RTR_CTRL_6_RANGE_SEC_MASK_HIGH_AW_7 0x3666C0
+
+#define mmSIF_RTR_CTRL_6_RANGE_SEC_MASK_HIGH_AW_8 0x3666C4
+
+#define mmSIF_RTR_CTRL_6_RANGE_SEC_MASK_HIGH_AW_9 0x3666C8
+
+#define mmSIF_RTR_CTRL_6_RANGE_SEC_MASK_HIGH_AW_10 0x3666CC
+
+#define mmSIF_RTR_CTRL_6_RANGE_SEC_MASK_HIGH_AW_11 0x3666D0
+
+#define mmSIF_RTR_CTRL_6_RANGE_SEC_MASK_HIGH_AW_12 0x3666D4
+
+#define mmSIF_RTR_CTRL_6_RANGE_SEC_MASK_HIGH_AW_13 0x3666D8
+
+#define mmSIF_RTR_CTRL_6_RANGE_SEC_MASK_HIGH_AW_14 0x3666DC
+
+#define mmSIF_RTR_CTRL_6_RANGE_SEC_MASK_HIGH_AW_15 0x3666E0
+
+#define mmSIF_RTR_CTRL_6_RANGE_PRIV_BASE_LOW_AW_0 0x3666E4
+
+#define mmSIF_RTR_CTRL_6_RANGE_PRIV_BASE_LOW_AW_1 0x3666E8
+
+#define mmSIF_RTR_CTRL_6_RANGE_PRIV_BASE_LOW_AW_2 0x3666EC
+
+#define mmSIF_RTR_CTRL_6_RANGE_PRIV_BASE_LOW_AW_3 0x3666F0
+
+#define mmSIF_RTR_CTRL_6_RANGE_PRIV_BASE_LOW_AW_4 0x3666F4
+
+#define mmSIF_RTR_CTRL_6_RANGE_PRIV_BASE_LOW_AW_5 0x3666F8
+
+#define mmSIF_RTR_CTRL_6_RANGE_PRIV_BASE_LOW_AW_6 0x3666FC
+
+#define mmSIF_RTR_CTRL_6_RANGE_PRIV_BASE_LOW_AW_7 0x366700
+
+#define mmSIF_RTR_CTRL_6_RANGE_PRIV_BASE_LOW_AW_8 0x366704
+
+#define mmSIF_RTR_CTRL_6_RANGE_PRIV_BASE_LOW_AW_9 0x366708
+
+#define mmSIF_RTR_CTRL_6_RANGE_PRIV_BASE_LOW_AW_10 0x36670C
+
+#define mmSIF_RTR_CTRL_6_RANGE_PRIV_BASE_LOW_AW_11 0x366710
+
+#define mmSIF_RTR_CTRL_6_RANGE_PRIV_BASE_LOW_AW_12 0x366714
+
+#define mmSIF_RTR_CTRL_6_RANGE_PRIV_BASE_LOW_AW_13 0x366718
+
+#define mmSIF_RTR_CTRL_6_RANGE_PRIV_BASE_LOW_AW_14 0x36671C
+
+#define mmSIF_RTR_CTRL_6_RANGE_PRIV_BASE_LOW_AW_15 0x366720
+
+#define mmSIF_RTR_CTRL_6_RANGE_PRIV_BASE_HIGH_AW_0 0x366724
+
+#define mmSIF_RTR_CTRL_6_RANGE_PRIV_BASE_HIGH_AW_1 0x366728
+
+#define mmSIF_RTR_CTRL_6_RANGE_PRIV_BASE_HIGH_AW_2 0x36672C
+
+#define mmSIF_RTR_CTRL_6_RANGE_PRIV_BASE_HIGH_AW_3 0x366730
+
+#define mmSIF_RTR_CTRL_6_RANGE_PRIV_BASE_HIGH_AW_4 0x366734
+
+#define mmSIF_RTR_CTRL_6_RANGE_PRIV_BASE_HIGH_AW_5 0x366738
+
+#define mmSIF_RTR_CTRL_6_RANGE_PRIV_BASE_HIGH_AW_6 0x36673C
+
+#define mmSIF_RTR_CTRL_6_RANGE_PRIV_BASE_HIGH_AW_7 0x366740
+
+#define mmSIF_RTR_CTRL_6_RANGE_PRIV_BASE_HIGH_AW_8 0x366744
+
+#define mmSIF_RTR_CTRL_6_RANGE_PRIV_BASE_HIGH_AW_9 0x366748
+
+#define mmSIF_RTR_CTRL_6_RANGE_PRIV_BASE_HIGH_AW_10 0x36674C
+
+#define mmSIF_RTR_CTRL_6_RANGE_PRIV_BASE_HIGH_AW_11 0x366750
+
+#define mmSIF_RTR_CTRL_6_RANGE_PRIV_BASE_HIGH_AW_12 0x366754
+
+#define mmSIF_RTR_CTRL_6_RANGE_PRIV_BASE_HIGH_AW_13 0x366758
+
+#define mmSIF_RTR_CTRL_6_RANGE_PRIV_BASE_HIGH_AW_14 0x36675C
+
+#define mmSIF_RTR_CTRL_6_RANGE_PRIV_BASE_HIGH_AW_15 0x366760
+
+#define mmSIF_RTR_CTRL_6_RANGE_PRIV_MASK_LOW_AW_0 0x366764
+
+#define mmSIF_RTR_CTRL_6_RANGE_PRIV_MASK_LOW_AW_1 0x366768
+
+#define mmSIF_RTR_CTRL_6_RANGE_PRIV_MASK_LOW_AW_2 0x36676C
+
+#define mmSIF_RTR_CTRL_6_RANGE_PRIV_MASK_LOW_AW_3 0x366770
+
+#define mmSIF_RTR_CTRL_6_RANGE_PRIV_MASK_LOW_AW_4 0x366774
+
+#define mmSIF_RTR_CTRL_6_RANGE_PRIV_MASK_LOW_AW_5 0x366778
+
+#define mmSIF_RTR_CTRL_6_RANGE_PRIV_MASK_LOW_AW_6 0x36677C
+
+#define mmSIF_RTR_CTRL_6_RANGE_PRIV_MASK_LOW_AW_7 0x366780
+
+#define mmSIF_RTR_CTRL_6_RANGE_PRIV_MASK_LOW_AW_8 0x366784
+
+#define mmSIF_RTR_CTRL_6_RANGE_PRIV_MASK_LOW_AW_9 0x366788
+
+#define mmSIF_RTR_CTRL_6_RANGE_PRIV_MASK_LOW_AW_10 0x36678C
+
+#define mmSIF_RTR_CTRL_6_RANGE_PRIV_MASK_LOW_AW_11 0x366790
+
+#define mmSIF_RTR_CTRL_6_RANGE_PRIV_MASK_LOW_AW_12 0x366794
+
+#define mmSIF_RTR_CTRL_6_RANGE_PRIV_MASK_LOW_AW_13 0x366798
+
+#define mmSIF_RTR_CTRL_6_RANGE_PRIV_MASK_LOW_AW_14 0x36679C
+
+#define mmSIF_RTR_CTRL_6_RANGE_PRIV_MASK_LOW_AW_15 0x3667A0
+
+#define mmSIF_RTR_CTRL_6_RANGE_PRIV_MASK_HIGH_AW_0 0x3667A4
+
+#define mmSIF_RTR_CTRL_6_RANGE_PRIV_MASK_HIGH_AW_1 0x3667A8
+
+#define mmSIF_RTR_CTRL_6_RANGE_PRIV_MASK_HIGH_AW_2 0x3667AC
+
+#define mmSIF_RTR_CTRL_6_RANGE_PRIV_MASK_HIGH_AW_3 0x3667B0
+
+#define mmSIF_RTR_CTRL_6_RANGE_PRIV_MASK_HIGH_AW_4 0x3667B4
+
+#define mmSIF_RTR_CTRL_6_RANGE_PRIV_MASK_HIGH_AW_5 0x3667B8
+
+#define mmSIF_RTR_CTRL_6_RANGE_PRIV_MASK_HIGH_AW_6 0x3667BC
+
+#define mmSIF_RTR_CTRL_6_RANGE_PRIV_MASK_HIGH_AW_7 0x3667C0
+
+#define mmSIF_RTR_CTRL_6_RANGE_PRIV_MASK_HIGH_AW_8 0x3667C4
+
+#define mmSIF_RTR_CTRL_6_RANGE_PRIV_MASK_HIGH_AW_9 0x3667C8
+
+#define mmSIF_RTR_CTRL_6_RANGE_PRIV_MASK_HIGH_AW_10 0x3667CC
+
+#define mmSIF_RTR_CTRL_6_RANGE_PRIV_MASK_HIGH_AW_11 0x3667D0
+
+#define mmSIF_RTR_CTRL_6_RANGE_PRIV_MASK_HIGH_AW_12 0x3667D4
+
+#define mmSIF_RTR_CTRL_6_RANGE_PRIV_MASK_HIGH_AW_13 0x3667D8
+
+#define mmSIF_RTR_CTRL_6_RANGE_PRIV_MASK_HIGH_AW_14 0x3667DC
+
+#define mmSIF_RTR_CTRL_6_RANGE_PRIV_MASK_HIGH_AW_15 0x3667E0
+
+#define mmSIF_RTR_CTRL_6_RANGE_SEC_BASE_LOW_AR_0 0x366824
+
+#define mmSIF_RTR_CTRL_6_RANGE_SEC_BASE_LOW_AR_1 0x366828
+
+#define mmSIF_RTR_CTRL_6_RANGE_SEC_BASE_LOW_AR_2 0x36682C
+
+#define mmSIF_RTR_CTRL_6_RANGE_SEC_BASE_LOW_AR_3 0x366830
+
+#define mmSIF_RTR_CTRL_6_RANGE_SEC_BASE_LOW_AR_4 0x366834
+
+#define mmSIF_RTR_CTRL_6_RANGE_SEC_BASE_LOW_AR_5 0x366838
+
+#define mmSIF_RTR_CTRL_6_RANGE_SEC_BASE_LOW_AR_6 0x36683C
+
+#define mmSIF_RTR_CTRL_6_RANGE_SEC_BASE_LOW_AR_7 0x366840
+
+#define mmSIF_RTR_CTRL_6_RANGE_SEC_BASE_LOW_AR_8 0x366844
+
+#define mmSIF_RTR_CTRL_6_RANGE_SEC_BASE_LOW_AR_9 0x366848
+
+#define mmSIF_RTR_CTRL_6_RANGE_SEC_BASE_LOW_AR_10 0x36684C
+
+#define mmSIF_RTR_CTRL_6_RANGE_SEC_BASE_LOW_AR_11 0x366850
+
+#define mmSIF_RTR_CTRL_6_RANGE_SEC_BASE_LOW_AR_12 0x366854
+
+#define mmSIF_RTR_CTRL_6_RANGE_SEC_BASE_LOW_AR_13 0x366858
+
+#define mmSIF_RTR_CTRL_6_RANGE_SEC_BASE_LOW_AR_14 0x36685C
+
+#define mmSIF_RTR_CTRL_6_RANGE_SEC_BASE_LOW_AR_15 0x366860
+
+#define mmSIF_RTR_CTRL_6_RANGE_SEC_BASE_HIGH_AR_0 0x366864
+
+#define mmSIF_RTR_CTRL_6_RANGE_SEC_BASE_HIGH_AR_1 0x366868
+
+#define mmSIF_RTR_CTRL_6_RANGE_SEC_BASE_HIGH_AR_2 0x36686C
+
+#define mmSIF_RTR_CTRL_6_RANGE_SEC_BASE_HIGH_AR_3 0x366870
+
+#define mmSIF_RTR_CTRL_6_RANGE_SEC_BASE_HIGH_AR_4 0x366874
+
+#define mmSIF_RTR_CTRL_6_RANGE_SEC_BASE_HIGH_AR_5 0x366878
+
+#define mmSIF_RTR_CTRL_6_RANGE_SEC_BASE_HIGH_AR_6 0x36687C
+
+#define mmSIF_RTR_CTRL_6_RANGE_SEC_BASE_HIGH_AR_7 0x366880
+
+#define mmSIF_RTR_CTRL_6_RANGE_SEC_BASE_HIGH_AR_8 0x366884
+
+#define mmSIF_RTR_CTRL_6_RANGE_SEC_BASE_HIGH_AR_9 0x366888
+
+#define mmSIF_RTR_CTRL_6_RANGE_SEC_BASE_HIGH_AR_10 0x36688C
+
+#define mmSIF_RTR_CTRL_6_RANGE_SEC_BASE_HIGH_AR_11 0x366890
+
+#define mmSIF_RTR_CTRL_6_RANGE_SEC_BASE_HIGH_AR_12 0x366894
+
+#define mmSIF_RTR_CTRL_6_RANGE_SEC_BASE_HIGH_AR_13 0x366898
+
+#define mmSIF_RTR_CTRL_6_RANGE_SEC_BASE_HIGH_AR_14 0x36689C
+
+#define mmSIF_RTR_CTRL_6_RANGE_SEC_BASE_HIGH_AR_15 0x3668A0
+
+#define mmSIF_RTR_CTRL_6_RANGE_SEC_MASK_LOW_AR_0 0x3668A4
+
+#define mmSIF_RTR_CTRL_6_RANGE_SEC_MASK_LOW_AR_1 0x3668A8
+
+#define mmSIF_RTR_CTRL_6_RANGE_SEC_MASK_LOW_AR_2 0x3668AC
+
+#define mmSIF_RTR_CTRL_6_RANGE_SEC_MASK_LOW_AR_3 0x3668B0
+
+#define mmSIF_RTR_CTRL_6_RANGE_SEC_MASK_LOW_AR_4 0x3668B4
+
+#define mmSIF_RTR_CTRL_6_RANGE_SEC_MASK_LOW_AR_5 0x3668B8
+
+#define mmSIF_RTR_CTRL_6_RANGE_SEC_MASK_LOW_AR_6 0x3668BC
+
+#define mmSIF_RTR_CTRL_6_RANGE_SEC_MASK_LOW_AR_7 0x3668C0
+
+#define mmSIF_RTR_CTRL_6_RANGE_SEC_MASK_LOW_AR_8 0x3668C4
+
+#define mmSIF_RTR_CTRL_6_RANGE_SEC_MASK_LOW_AR_9 0x3668C8
+
+#define mmSIF_RTR_CTRL_6_RANGE_SEC_MASK_LOW_AR_10 0x3668CC
+
+#define mmSIF_RTR_CTRL_6_RANGE_SEC_MASK_LOW_AR_11 0x3668D0
+
+#define mmSIF_RTR_CTRL_6_RANGE_SEC_MASK_LOW_AR_12 0x3668D4
+
+#define mmSIF_RTR_CTRL_6_RANGE_SEC_MASK_LOW_AR_13 0x3668D8
+
+#define mmSIF_RTR_CTRL_6_RANGE_SEC_MASK_LOW_AR_14 0x3668DC
+
+#define mmSIF_RTR_CTRL_6_RANGE_SEC_MASK_LOW_AR_15 0x3668E0
+
+#define mmSIF_RTR_CTRL_6_RANGE_SEC_MASK_HIGH_AR_0 0x3668E4
+
+#define mmSIF_RTR_CTRL_6_RANGE_SEC_MASK_HIGH_AR_1 0x3668E8
+
+#define mmSIF_RTR_CTRL_6_RANGE_SEC_MASK_HIGH_AR_2 0x3668EC
+
+#define mmSIF_RTR_CTRL_6_RANGE_SEC_MASK_HIGH_AR_3 0x3668F0
+
+#define mmSIF_RTR_CTRL_6_RANGE_SEC_MASK_HIGH_AR_4 0x3668F4
+
+#define mmSIF_RTR_CTRL_6_RANGE_SEC_MASK_HIGH_AR_5 0x3668F8
+
+#define mmSIF_RTR_CTRL_6_RANGE_SEC_MASK_HIGH_AR_6 0x3668FC
+
+#define mmSIF_RTR_CTRL_6_RANGE_SEC_MASK_HIGH_AR_7 0x366900
+
+#define mmSIF_RTR_CTRL_6_RANGE_SEC_MASK_HIGH_AR_8 0x366904
+
+#define mmSIF_RTR_CTRL_6_RANGE_SEC_MASK_HIGH_AR_9 0x366908
+
+#define mmSIF_RTR_CTRL_6_RANGE_SEC_MASK_HIGH_AR_10 0x36690C
+
+#define mmSIF_RTR_CTRL_6_RANGE_SEC_MASK_HIGH_AR_11 0x366910
+
+#define mmSIF_RTR_CTRL_6_RANGE_SEC_MASK_HIGH_AR_12 0x366914
+
+#define mmSIF_RTR_CTRL_6_RANGE_SEC_MASK_HIGH_AR_13 0x366918
+
+#define mmSIF_RTR_CTRL_6_RANGE_SEC_MASK_HIGH_AR_14 0x36691C
+
+#define mmSIF_RTR_CTRL_6_RANGE_SEC_MASK_HIGH_AR_15 0x366920
+
+#define mmSIF_RTR_CTRL_6_RANGE_PRIV_BASE_LOW_AR_0 0x366924
+
+#define mmSIF_RTR_CTRL_6_RANGE_PRIV_BASE_LOW_AR_1 0x366928
+
+#define mmSIF_RTR_CTRL_6_RANGE_PRIV_BASE_LOW_AR_2 0x36692C
+
+#define mmSIF_RTR_CTRL_6_RANGE_PRIV_BASE_LOW_AR_3 0x366930
+
+#define mmSIF_RTR_CTRL_6_RANGE_PRIV_BASE_LOW_AR_4 0x366934
+
+#define mmSIF_RTR_CTRL_6_RANGE_PRIV_BASE_LOW_AR_5 0x366938
+
+#define mmSIF_RTR_CTRL_6_RANGE_PRIV_BASE_LOW_AR_6 0x36693C
+
+#define mmSIF_RTR_CTRL_6_RANGE_PRIV_BASE_LOW_AR_7 0x366940
+
+#define mmSIF_RTR_CTRL_6_RANGE_PRIV_BASE_LOW_AR_8 0x366944
+
+#define mmSIF_RTR_CTRL_6_RANGE_PRIV_BASE_LOW_AR_9 0x366948
+
+#define mmSIF_RTR_CTRL_6_RANGE_PRIV_BASE_LOW_AR_10 0x36694C
+
+#define mmSIF_RTR_CTRL_6_RANGE_PRIV_BASE_LOW_AR_11 0x366950
+
+#define mmSIF_RTR_CTRL_6_RANGE_PRIV_BASE_LOW_AR_12 0x366954
+
+#define mmSIF_RTR_CTRL_6_RANGE_PRIV_BASE_LOW_AR_13 0x366958
+
+#define mmSIF_RTR_CTRL_6_RANGE_PRIV_BASE_LOW_AR_14 0x36695C
+
+#define mmSIF_RTR_CTRL_6_RANGE_PRIV_BASE_LOW_AR_15 0x366960
+
+#define mmSIF_RTR_CTRL_6_RANGE_PRIV_BASE_HIGH_AR_0 0x366964
+
+#define mmSIF_RTR_CTRL_6_RANGE_PRIV_BASE_HIGH_AR_1 0x366968
+
+#define mmSIF_RTR_CTRL_6_RANGE_PRIV_BASE_HIGH_AR_2 0x36696C
+
+#define mmSIF_RTR_CTRL_6_RANGE_PRIV_BASE_HIGH_AR_3 0x366970
+
+#define mmSIF_RTR_CTRL_6_RANGE_PRIV_BASE_HIGH_AR_4 0x366974
+
+#define mmSIF_RTR_CTRL_6_RANGE_PRIV_BASE_HIGH_AR_5 0x366978
+
+#define mmSIF_RTR_CTRL_6_RANGE_PRIV_BASE_HIGH_AR_6 0x36697C
+
+#define mmSIF_RTR_CTRL_6_RANGE_PRIV_BASE_HIGH_AR_7 0x366980
+
+#define mmSIF_RTR_CTRL_6_RANGE_PRIV_BASE_HIGH_AR_8 0x366984
+
+#define mmSIF_RTR_CTRL_6_RANGE_PRIV_BASE_HIGH_AR_9 0x366988
+
+#define mmSIF_RTR_CTRL_6_RANGE_PRIV_BASE_HIGH_AR_10 0x36698C
+
+#define mmSIF_RTR_CTRL_6_RANGE_PRIV_BASE_HIGH_AR_11 0x366990
+
+#define mmSIF_RTR_CTRL_6_RANGE_PRIV_BASE_HIGH_AR_12 0x366994
+
+#define mmSIF_RTR_CTRL_6_RANGE_PRIV_BASE_HIGH_AR_13 0x366998
+
+#define mmSIF_RTR_CTRL_6_RANGE_PRIV_BASE_HIGH_AR_14 0x36699C
+
+#define mmSIF_RTR_CTRL_6_RANGE_PRIV_BASE_HIGH_AR_15 0x3669A0
+
+#define mmSIF_RTR_CTRL_6_RANGE_PRIV_MASK_LOW_AR_0 0x3669A4
+
+#define mmSIF_RTR_CTRL_6_RANGE_PRIV_MASK_LOW_AR_1 0x3669A8
+
+#define mmSIF_RTR_CTRL_6_RANGE_PRIV_MASK_LOW_AR_2 0x3669AC
+
+#define mmSIF_RTR_CTRL_6_RANGE_PRIV_MASK_LOW_AR_3 0x3669B0
+
+#define mmSIF_RTR_CTRL_6_RANGE_PRIV_MASK_LOW_AR_4 0x3669B4
+
+#define mmSIF_RTR_CTRL_6_RANGE_PRIV_MASK_LOW_AR_5 0x3669B8
+
+#define mmSIF_RTR_CTRL_6_RANGE_PRIV_MASK_LOW_AR_6 0x3669BC
+
+#define mmSIF_RTR_CTRL_6_RANGE_PRIV_MASK_LOW_AR_7 0x3669C0
+
+#define mmSIF_RTR_CTRL_6_RANGE_PRIV_MASK_LOW_AR_8 0x3669C4
+
+#define mmSIF_RTR_CTRL_6_RANGE_PRIV_MASK_LOW_AR_9 0x3669C8
+
+#define mmSIF_RTR_CTRL_6_RANGE_PRIV_MASK_LOW_AR_10 0x3669CC
+
+#define mmSIF_RTR_CTRL_6_RANGE_PRIV_MASK_LOW_AR_11 0x3669D0
+
+#define mmSIF_RTR_CTRL_6_RANGE_PRIV_MASK_LOW_AR_12 0x3669D4
+
+#define mmSIF_RTR_CTRL_6_RANGE_PRIV_MASK_LOW_AR_13 0x3669D8
+
+#define mmSIF_RTR_CTRL_6_RANGE_PRIV_MASK_LOW_AR_14 0x3669DC
+
+#define mmSIF_RTR_CTRL_6_RANGE_PRIV_MASK_LOW_AR_15 0x3669E0
+
+#define mmSIF_RTR_CTRL_6_RANGE_PRIV_MASK_HIGH_AR_0 0x3669E4
+
+#define mmSIF_RTR_CTRL_6_RANGE_PRIV_MASK_HIGH_AR_1 0x3669E8
+
+#define mmSIF_RTR_CTRL_6_RANGE_PRIV_MASK_HIGH_AR_2 0x3669EC
+
+#define mmSIF_RTR_CTRL_6_RANGE_PRIV_MASK_HIGH_AR_3 0x3669F0
+
+#define mmSIF_RTR_CTRL_6_RANGE_PRIV_MASK_HIGH_AR_4 0x3669F4
+
+#define mmSIF_RTR_CTRL_6_RANGE_PRIV_MASK_HIGH_AR_5 0x3669F8
+
+#define mmSIF_RTR_CTRL_6_RANGE_PRIV_MASK_HIGH_AR_6 0x3669FC
+
+#define mmSIF_RTR_CTRL_6_RANGE_PRIV_MASK_HIGH_AR_7 0x366A00
+
+#define mmSIF_RTR_CTRL_6_RANGE_PRIV_MASK_HIGH_AR_8 0x366A04
+
+#define mmSIF_RTR_CTRL_6_RANGE_PRIV_MASK_HIGH_AR_9 0x366A08
+
+#define mmSIF_RTR_CTRL_6_RANGE_PRIV_MASK_HIGH_AR_10 0x366A0C
+
+#define mmSIF_RTR_CTRL_6_RANGE_PRIV_MASK_HIGH_AR_11 0x366A10
+
+#define mmSIF_RTR_CTRL_6_RANGE_PRIV_MASK_HIGH_AR_12 0x366A14
+
+#define mmSIF_RTR_CTRL_6_RANGE_PRIV_MASK_HIGH_AR_13 0x366A18
+
+#define mmSIF_RTR_CTRL_6_RANGE_PRIV_MASK_HIGH_AR_14 0x366A1C
+
+#define mmSIF_RTR_CTRL_6_RANGE_PRIV_MASK_HIGH_AR_15 0x366A20
+
+#define mmSIF_RTR_CTRL_6_RANGE_SEC_HIT_AW 0x366A64
+
+#define mmSIF_RTR_CTRL_6_RANGE_SEC_HIT_AR 0x366A68
+
+#define mmSIF_RTR_CTRL_6_RANGE_PRIV_HIT_AW 0x366A6C
+
+#define mmSIF_RTR_CTRL_6_RANGE_PRIV_HIT_AR 0x366A70
+
+#define mmSIF_RTR_CTRL_6_RGL_CFG 0x366B64
+
+#define mmSIF_RTR_CTRL_6_RGL_SHIFT 0x366B68
+
+#define mmSIF_RTR_CTRL_6_RGL_EXPECTED_LAT_0 0x366B6C
+
+#define mmSIF_RTR_CTRL_6_RGL_EXPECTED_LAT_1 0x366B70
+
+#define mmSIF_RTR_CTRL_6_RGL_EXPECTED_LAT_2 0x366B74
+
+#define mmSIF_RTR_CTRL_6_RGL_EXPECTED_LAT_3 0x366B78
+
+#define mmSIF_RTR_CTRL_6_RGL_EXPECTED_LAT_4 0x366B7C
+
+#define mmSIF_RTR_CTRL_6_RGL_EXPECTED_LAT_5 0x366B80
+
+#define mmSIF_RTR_CTRL_6_RGL_EXPECTED_LAT_6 0x366B84
+
+#define mmSIF_RTR_CTRL_6_RGL_EXPECTED_LAT_7 0x366B88
+
+#define mmSIF_RTR_CTRL_6_RGL_TOKEN_0 0x366BAC
+
+#define mmSIF_RTR_CTRL_6_RGL_TOKEN_1 0x366BB0
+
+#define mmSIF_RTR_CTRL_6_RGL_TOKEN_2 0x366BB4
+
+#define mmSIF_RTR_CTRL_6_RGL_TOKEN_3 0x366BB8
+
+#define mmSIF_RTR_CTRL_6_RGL_TOKEN_4 0x366BBC
+
+#define mmSIF_RTR_CTRL_6_RGL_TOKEN_5 0x366BC0
+
+#define mmSIF_RTR_CTRL_6_RGL_TOKEN_6 0x366BC4
+
+#define mmSIF_RTR_CTRL_6_RGL_TOKEN_7 0x366BC8
+
+#define mmSIF_RTR_CTRL_6_RGL_BANK_ID_0 0x366BEC
+
+#define mmSIF_RTR_CTRL_6_RGL_BANK_ID_1 0x366BF0
+
+#define mmSIF_RTR_CTRL_6_RGL_BANK_ID_2 0x366BF4
+
+#define mmSIF_RTR_CTRL_6_RGL_BANK_ID_3 0x366BF8
+
+#define mmSIF_RTR_CTRL_6_RGL_BANK_ID_4 0x366BFC
+
+#define mmSIF_RTR_CTRL_6_RGL_BANK_ID_5 0x366C00
+
+#define mmSIF_RTR_CTRL_6_RGL_BANK_ID_6 0x366C04
+
+#define mmSIF_RTR_CTRL_6_RGL_BANK_ID_7 0x366C08
+
+#define mmSIF_RTR_CTRL_6_RGL_WDT 0x366C2C
+
+#define mmSIF_RTR_CTRL_6_E2E_AR_HBM0_CH0_CTR_WRAP 0x366C30
+
+#define mmSIF_RTR_CTRL_6_E2E_AR_HBM0_CH1_CTR_WRAP 0x366C34
+
+#define mmSIF_RTR_CTRL_6_E2E_AR_HBM1_CH0_CTR_WRAP 0x366C38
+
+#define mmSIF_RTR_CTRL_6_E2E_AR_HBM1_CH1_CTR_WRAP 0x366C3C
+
+#define mmSIF_RTR_CTRL_6_E2E_AR_HBM2_CH0_CTR_WRAP 0x366C40
+
+#define mmSIF_RTR_CTRL_6_E2E_AR_HBM2_CH1_CTR_WRAP 0x366C44
+
+#define mmSIF_RTR_CTRL_6_E2E_AR_HBM3_CH0_CTR_WRAP 0x366C48
+
+#define mmSIF_RTR_CTRL_6_E2E_AR_HBM3_CH1_CTR_WRAP 0x366C4C
+
+#define mmSIF_RTR_CTRL_6_E2E_AR_HBM0_CH0_CTR_CNT 0x366C50
+
+#define mmSIF_RTR_CTRL_6_E2E_AR_HBM0_CH1_CTR_CNT 0x366C54
+
+#define mmSIF_RTR_CTRL_6_E2E_AR_HBM1_CH0_CTR_CNT 0x366C58
+
+#define mmSIF_RTR_CTRL_6_E2E_AR_HBM1_CH1_CTR_CNT 0x366C5C
+
+#define mmSIF_RTR_CTRL_6_E2E_AR_HBM2_CH0_CTR_CNT 0x366C60
+
+#define mmSIF_RTR_CTRL_6_E2E_AR_HBM2_CH1_CTR_CNT 0x366C64
+
+#define mmSIF_RTR_CTRL_6_E2E_AR_HBM3_CH0_CTR_CNT 0x366C68
+
+#define mmSIF_RTR_CTRL_6_E2E_AR_HBM3_CH1_CTR_CNT 0x366C6C
+
+#define mmSIF_RTR_CTRL_6_E2E_AW_HBM0_CH0_CTR_WRAP 0x366C70
+
+#define mmSIF_RTR_CTRL_6_E2E_AW_HBM0_CH1_CTR_WRAP 0x366C74
+
+#define mmSIF_RTR_CTRL_6_E2E_AW_HBM1_CH0_CTR_WRAP 0x366C78
+
+#define mmSIF_RTR_CTRL_6_E2E_AW_HBM1_CH1_CTR_WRAP 0x366C7C
+
+#define mmSIF_RTR_CTRL_6_E2E_AW_HBM2_CH0_CTR_WRAP 0x366C80
+
+#define mmSIF_RTR_CTRL_6_E2E_AW_HBM2_CH1_CTR_WRAP 0x366C84
+
+#define mmSIF_RTR_CTRL_6_E2E_AW_HBM3_CH0_CTR_WRAP 0x366C88
+
+#define mmSIF_RTR_CTRL_6_E2E_AW_HBM3_CH1_CTR_WRAP 0x366C8C
+
+#define mmSIF_RTR_CTRL_6_E2E_AW_HBM0_CH0_CTR_CNT 0x366C90
+
+#define mmSIF_RTR_CTRL_6_E2E_AW_HBM0_CH1_CTR_CNT 0x366C94
+
+#define mmSIF_RTR_CTRL_6_E2E_AW_HBM1_CH0_CTR_CNT 0x366C98
+
+#define mmSIF_RTR_CTRL_6_E2E_AW_HBM1_CH1_CTR_CNT 0x366C9C
+
+#define mmSIF_RTR_CTRL_6_E2E_AW_HBM2_CH0_CTR_CNT 0x366CA0
+
+#define mmSIF_RTR_CTRL_6_E2E_AW_HBM2_CH1_CTR_CNT 0x366CA4
+
+#define mmSIF_RTR_CTRL_6_E2E_AW_HBM3_CH0_CTR_CNT 0x366CA8
+
+#define mmSIF_RTR_CTRL_6_E2E_AW_HBM3_CH1_CTR_CNT 0x366CAC
+
+#define mmSIF_RTR_CTRL_6_NL_HBM_PC_SEL_0 0x366CB0
+
+#define mmSIF_RTR_CTRL_6_NL_HBM_PC_SEL_1 0x366CB4
+
+#define mmSIF_RTR_CTRL_6_NL_HBM_PC_SEL_2 0x366CB8
+
+#define mmSIF_RTR_CTRL_6_NL_HBM_PC_SEL_3 0x366CBC
+
+#endif /* ASIC_REG_SIF_RTR_CTRL_6_REGS_H_ */
diff --git a/drivers/accel/habanalabs/include/gaudi/asic_reg/sif_rtr_ctrl_7_regs.h b/drivers/accel/habanalabs/include/gaudi/asic_reg/sif_rtr_ctrl_7_regs.h
new file mode 100644
index 0000000000..a37772c531
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi/asic_reg/sif_rtr_ctrl_7_regs.h
@@ -0,0 +1,896 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2016-2018 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ ** DO NOT EDIT BELOW **
+ ************************************/
+
+#ifndef ASIC_REG_SIF_RTR_CTRL_7_REGS_H_
+#define ASIC_REG_SIF_RTR_CTRL_7_REGS_H_
+
+/*
+ *****************************************
+ * SIF_RTR_CTRL_7 (Prototype: RTR_CTRL)
+ *****************************************
+ */
+
+#define mmSIF_RTR_CTRL_7_PERM_SEL 0x376108
+
+#define mmSIF_RTR_CTRL_7_HBM_POLY_H3_0 0x376114
+
+#define mmSIF_RTR_CTRL_7_HBM_POLY_H3_1 0x376118
+
+#define mmSIF_RTR_CTRL_7_HBM_POLY_H3_2 0x37611C
+
+#define mmSIF_RTR_CTRL_7_HBM_POLY_H3_3 0x376120
+
+#define mmSIF_RTR_CTRL_7_HBM_POLY_H3_4 0x376124
+
+#define mmSIF_RTR_CTRL_7_HBM_POLY_H3_5 0x376128
+
+#define mmSIF_RTR_CTRL_7_HBM_POLY_H3_6 0x37612C
+
+#define mmSIF_RTR_CTRL_7_HBM_POLY_H3_7 0x376130
+
+#define mmSIF_RTR_CTRL_7_HBM_POLY_H3_8 0x376134
+
+#define mmSIF_RTR_CTRL_7_HBM_POLY_H3_9 0x376138
+
+#define mmSIF_RTR_CTRL_7_HBM_POLY_H3_10 0x37613C
+
+#define mmSIF_RTR_CTRL_7_HBM_POLY_H3_11 0x376140
+
+#define mmSIF_RTR_CTRL_7_HBM_POLY_H3_12 0x376144
+
+#define mmSIF_RTR_CTRL_7_HBM_POLY_H3_13 0x376148
+
+#define mmSIF_RTR_CTRL_7_HBM_POLY_H3_14 0x37614C
+
+#define mmSIF_RTR_CTRL_7_HBM_POLY_H3_15 0x376150
+
+#define mmSIF_RTR_CTRL_7_HBM_POLY_H3_16 0x376154
+
+#define mmSIF_RTR_CTRL_7_HBM_POLY_H3_17 0x376158
+
+#define mmSIF_RTR_CTRL_7_HBM_POLY_H3_18 0x37615C
+
+#define mmSIF_RTR_CTRL_7_HBM_POLY_H3_19 0x376160
+
+#define mmSIF_RTR_CTRL_7_HBM_POLY_H3_20 0x376164
+
+#define mmSIF_RTR_CTRL_7_HBM_POLY_H3_21 0x376168
+
+#define mmSIF_RTR_CTRL_7_HBM_POLY_H3_22 0x37616C
+
+#define mmSIF_RTR_CTRL_7_HBM_POLY_H3_23 0x376170
+
+#define mmSIF_RTR_CTRL_7_HBM_POLY_H3_24 0x376174
+
+#define mmSIF_RTR_CTRL_7_HBM_POLY_H3_25 0x376178
+
+#define mmSIF_RTR_CTRL_7_HBM_POLY_H3_26 0x37617C
+
+#define mmSIF_RTR_CTRL_7_HBM_POLY_H3_27 0x376180
+
+#define mmSIF_RTR_CTRL_7_SRAM_POLY_H3_0 0x376184
+
+#define mmSIF_RTR_CTRL_7_SRAM_POLY_H3_1 0x376188
+
+#define mmSIF_RTR_CTRL_7_SRAM_POLY_H3_2 0x37618C
+
+#define mmSIF_RTR_CTRL_7_SRAM_POLY_H3_3 0x376190
+
+#define mmSIF_RTR_CTRL_7_SRAM_POLY_H3_4 0x376194
+
+#define mmSIF_RTR_CTRL_7_SRAM_POLY_H3_5 0x376198
+
+#define mmSIF_RTR_CTRL_7_SRAM_POLY_H3_6 0x37619C
+
+#define mmSIF_RTR_CTRL_7_SRAM_POLY_H3_7 0x3761A0
+
+#define mmSIF_RTR_CTRL_7_SRAM_POLY_H3_8 0x3761A4
+
+#define mmSIF_RTR_CTRL_7_SRAM_POLY_H3_9 0x3761A8
+
+#define mmSIF_RTR_CTRL_7_SRAM_POLY_H3_10 0x3761AC
+
+#define mmSIF_RTR_CTRL_7_SRAM_POLY_H3_11 0x3761B0
+
+#define mmSIF_RTR_CTRL_7_SRAM_POLY_H3_12 0x3761B4
+
+#define mmSIF_RTR_CTRL_7_SRAM_POLY_H3_13 0x3761B8
+
+#define mmSIF_RTR_CTRL_7_SRAM_POLY_H3_14 0x3761BC
+
+#define mmSIF_RTR_CTRL_7_SCRAM_SRAM_EN 0x37626C
+
+#define mmSIF_RTR_CTRL_7_RL_HBM_EN 0x376274
+
+#define mmSIF_RTR_CTRL_7_RL_HBM_SAT 0x376278
+
+#define mmSIF_RTR_CTRL_7_RL_HBM_RST 0x37627C
+
+#define mmSIF_RTR_CTRL_7_RL_HBM_TIMEOUT 0x376280
+
+#define mmSIF_RTR_CTRL_7_SCRAM_HBM_EN 0x376284
+
+#define mmSIF_RTR_CTRL_7_RL_PCI_EN 0x376288
+
+#define mmSIF_RTR_CTRL_7_RL_PCI_SAT 0x37628C
+
+#define mmSIF_RTR_CTRL_7_RL_PCI_RST 0x376290
+
+#define mmSIF_RTR_CTRL_7_RL_PCI_TIMEOUT 0x376294
+
+#define mmSIF_RTR_CTRL_7_RL_SRAM_EN 0x37629C
+
+#define mmSIF_RTR_CTRL_7_RL_SRAM_SAT 0x3762A0
+
+#define mmSIF_RTR_CTRL_7_RL_SRAM_RST 0x3762A4
+
+#define mmSIF_RTR_CTRL_7_RL_SRAM_TIMEOUT 0x3762AC
+
+#define mmSIF_RTR_CTRL_7_RL_SRAM_RED 0x3762B4
+
+#define mmSIF_RTR_CTRL_7_E2E_HBM_EN 0x3762EC
+
+#define mmSIF_RTR_CTRL_7_E2E_PCI_EN 0x3762F0
+
+#define mmSIF_RTR_CTRL_7_E2E_HBM_WR_SIZE 0x3762F4
+
+#define mmSIF_RTR_CTRL_7_E2E_PCI_WR_SIZE 0x3762F8
+
+#define mmSIF_RTR_CTRL_7_E2E_AW_PCI_CTR_SET_EN 0x376404
+
+#define mmSIF_RTR_CTRL_7_E2E_AW_PCI_CTR_SET 0x376408
+
+#define mmSIF_RTR_CTRL_7_E2E_AW_PCI_CTR_WRAP 0x37640C
+
+#define mmSIF_RTR_CTRL_7_E2E_AW_PCI_CTR_CNT 0x376410
+
+#define mmSIF_RTR_CTRL_7_E2E_AW_HBM_CTR_SET_EN 0x376414
+
+#define mmSIF_RTR_CTRL_7_E2E_AW_HBM_CTR_SET 0x376418
+
+#define mmSIF_RTR_CTRL_7_E2E_HBM_RD_SIZE 0x37641C
+
+#define mmSIF_RTR_CTRL_7_E2E_PCI_RD_SIZE 0x376420
+
+#define mmSIF_RTR_CTRL_7_E2E_AR_PCI_CTR_SET_EN 0x376424
+
+#define mmSIF_RTR_CTRL_7_E2E_AR_PCI_CTR_SET 0x376428
+
+#define mmSIF_RTR_CTRL_7_E2E_AR_PCI_CTR_WRAP 0x37642C
+
+#define mmSIF_RTR_CTRL_7_E2E_AR_PCI_CTR_CNT 0x376430
+
+#define mmSIF_RTR_CTRL_7_E2E_AR_HBM_CTR_SET_EN 0x376434
+
+#define mmSIF_RTR_CTRL_7_E2E_AR_HBM_CTR_SET 0x376438
+
+#define mmSIF_RTR_CTRL_7_NL_HBM_SEL_0 0x376450
+
+#define mmSIF_RTR_CTRL_7_NL_HBM_SEL_1 0x376454
+
+#define mmSIF_RTR_CTRL_7_NON_LIN_EN 0x376480
+
+#define mmSIF_RTR_CTRL_7_NL_SRAM_BANK_0 0x376500
+
+#define mmSIF_RTR_CTRL_7_NL_SRAM_BANK_1 0x376504
+
+#define mmSIF_RTR_CTRL_7_NL_SRAM_BANK_2 0x376508
+
+#define mmSIF_RTR_CTRL_7_NL_SRAM_BANK_3 0x37650C
+
+#define mmSIF_RTR_CTRL_7_NL_SRAM_BANK_4 0x376510
+
+#define mmSIF_RTR_CTRL_7_NL_SRAM_OFFSET_0 0x376514
+
+#define mmSIF_RTR_CTRL_7_NL_SRAM_OFFSET_1 0x376520
+
+#define mmSIF_RTR_CTRL_7_NL_SRAM_OFFSET_2 0x376524
+
+#define mmSIF_RTR_CTRL_7_NL_SRAM_OFFSET_3 0x376528
+
+#define mmSIF_RTR_CTRL_7_NL_SRAM_OFFSET_4 0x37652C
+
+#define mmSIF_RTR_CTRL_7_NL_SRAM_OFFSET_5 0x376530
+
+#define mmSIF_RTR_CTRL_7_NL_SRAM_OFFSET_6 0x376534
+
+#define mmSIF_RTR_CTRL_7_NL_SRAM_OFFSET_7 0x376538
+
+#define mmSIF_RTR_CTRL_7_NL_SRAM_OFFSET_8 0x37653C
+
+#define mmSIF_RTR_CTRL_7_NL_SRAM_OFFSET_9 0x376540
+
+#define mmSIF_RTR_CTRL_7_NL_HBM_OFFSET_0 0x376550
+
+#define mmSIF_RTR_CTRL_7_NL_HBM_OFFSET_1 0x376554
+
+#define mmSIF_RTR_CTRL_7_NL_HBM_OFFSET_2 0x376558
+
+#define mmSIF_RTR_CTRL_7_NL_HBM_OFFSET_3 0x37655C
+
+#define mmSIF_RTR_CTRL_7_NL_HBM_OFFSET_4 0x376560
+
+#define mmSIF_RTR_CTRL_7_NL_HBM_OFFSET_5 0x376564
+
+#define mmSIF_RTR_CTRL_7_NL_HBM_OFFSET_6 0x376568
+
+#define mmSIF_RTR_CTRL_7_NL_HBM_OFFSET_7 0x37656C
+
+#define mmSIF_RTR_CTRL_7_NL_HBM_OFFSET_8 0x376570
+
+#define mmSIF_RTR_CTRL_7_NL_HBM_OFFSET_9 0x376574
+
+#define mmSIF_RTR_CTRL_7_NL_HBM_OFFSET_10 0x376578
+
+#define mmSIF_RTR_CTRL_7_NL_HBM_OFFSET_11 0x37657C
+
+#define mmSIF_RTR_CTRL_7_NL_HBM_OFFSET_12 0x376580
+
+#define mmSIF_RTR_CTRL_7_NL_HBM_OFFSET_13 0x376584
+
+#define mmSIF_RTR_CTRL_7_NL_HBM_OFFSET_14 0x376588
+
+#define mmSIF_RTR_CTRL_7_NL_HBM_OFFSET_15 0x37658C
+
+#define mmSIF_RTR_CTRL_7_NL_HBM_OFFSET_16 0x376590
+
+#define mmSIF_RTR_CTRL_7_NL_HBM_OFFSET_17 0x376594
+
+#define mmSIF_RTR_CTRL_7_NL_HBM_OFFSET_18 0x376598
+
+#define mmSIF_RTR_CTRL_7_RANGE_SEC_BASE_LOW_AW_0 0x3765E4
+
+#define mmSIF_RTR_CTRL_7_RANGE_SEC_BASE_LOW_AW_1 0x3765E8
+
+#define mmSIF_RTR_CTRL_7_RANGE_SEC_BASE_LOW_AW_2 0x3765EC
+
+#define mmSIF_RTR_CTRL_7_RANGE_SEC_BASE_LOW_AW_3 0x3765F0
+
+#define mmSIF_RTR_CTRL_7_RANGE_SEC_BASE_LOW_AW_4 0x3765F4
+
+#define mmSIF_RTR_CTRL_7_RANGE_SEC_BASE_LOW_AW_5 0x3765F8
+
+#define mmSIF_RTR_CTRL_7_RANGE_SEC_BASE_LOW_AW_6 0x3765FC
+
+#define mmSIF_RTR_CTRL_7_RANGE_SEC_BASE_LOW_AW_7 0x376600
+
+#define mmSIF_RTR_CTRL_7_RANGE_SEC_BASE_LOW_AW_8 0x376604
+
+#define mmSIF_RTR_CTRL_7_RANGE_SEC_BASE_LOW_AW_9 0x376608
+
+#define mmSIF_RTR_CTRL_7_RANGE_SEC_BASE_LOW_AW_10 0x37660C
+
+#define mmSIF_RTR_CTRL_7_RANGE_SEC_BASE_LOW_AW_11 0x376610
+
+#define mmSIF_RTR_CTRL_7_RANGE_SEC_BASE_LOW_AW_12 0x376614
+
+#define mmSIF_RTR_CTRL_7_RANGE_SEC_BASE_LOW_AW_13 0x376618
+
+#define mmSIF_RTR_CTRL_7_RANGE_SEC_BASE_LOW_AW_14 0x37661C
+
+#define mmSIF_RTR_CTRL_7_RANGE_SEC_BASE_LOW_AW_15 0x376620
+
+#define mmSIF_RTR_CTRL_7_RANGE_SEC_BASE_HIGH_AW_0 0x376624
+
+#define mmSIF_RTR_CTRL_7_RANGE_SEC_BASE_HIGH_AW_1 0x376628
+
+#define mmSIF_RTR_CTRL_7_RANGE_SEC_BASE_HIGH_AW_2 0x37662C
+
+#define mmSIF_RTR_CTRL_7_RANGE_SEC_BASE_HIGH_AW_3 0x376630
+
+#define mmSIF_RTR_CTRL_7_RANGE_SEC_BASE_HIGH_AW_4 0x376634
+
+#define mmSIF_RTR_CTRL_7_RANGE_SEC_BASE_HIGH_AW_5 0x376638
+
+#define mmSIF_RTR_CTRL_7_RANGE_SEC_BASE_HIGH_AW_6 0x37663C
+
+#define mmSIF_RTR_CTRL_7_RANGE_SEC_BASE_HIGH_AW_7 0x376640
+
+#define mmSIF_RTR_CTRL_7_RANGE_SEC_BASE_HIGH_AW_8 0x376644
+
+#define mmSIF_RTR_CTRL_7_RANGE_SEC_BASE_HIGH_AW_9 0x376648
+
+#define mmSIF_RTR_CTRL_7_RANGE_SEC_BASE_HIGH_AW_10 0x37664C
+
+#define mmSIF_RTR_CTRL_7_RANGE_SEC_BASE_HIGH_AW_11 0x376650
+
+#define mmSIF_RTR_CTRL_7_RANGE_SEC_BASE_HIGH_AW_12 0x376654
+
+#define mmSIF_RTR_CTRL_7_RANGE_SEC_BASE_HIGH_AW_13 0x376658
+
+#define mmSIF_RTR_CTRL_7_RANGE_SEC_BASE_HIGH_AW_14 0x37665C
+
+#define mmSIF_RTR_CTRL_7_RANGE_SEC_BASE_HIGH_AW_15 0x376660
+
+#define mmSIF_RTR_CTRL_7_RANGE_SEC_MASK_LOW_AW_0 0x376664
+
+#define mmSIF_RTR_CTRL_7_RANGE_SEC_MASK_LOW_AW_1 0x376668
+
+#define mmSIF_RTR_CTRL_7_RANGE_SEC_MASK_LOW_AW_2 0x37666C
+
+#define mmSIF_RTR_CTRL_7_RANGE_SEC_MASK_LOW_AW_3 0x376670
+
+#define mmSIF_RTR_CTRL_7_RANGE_SEC_MASK_LOW_AW_4 0x376674
+
+#define mmSIF_RTR_CTRL_7_RANGE_SEC_MASK_LOW_AW_5 0x376678
+
+#define mmSIF_RTR_CTRL_7_RANGE_SEC_MASK_LOW_AW_6 0x37667C
+
+#define mmSIF_RTR_CTRL_7_RANGE_SEC_MASK_LOW_AW_7 0x376680
+
+#define mmSIF_RTR_CTRL_7_RANGE_SEC_MASK_LOW_AW_8 0x376684
+
+#define mmSIF_RTR_CTRL_7_RANGE_SEC_MASK_LOW_AW_9 0x376688
+
+#define mmSIF_RTR_CTRL_7_RANGE_SEC_MASK_LOW_AW_10 0x37668C
+
+#define mmSIF_RTR_CTRL_7_RANGE_SEC_MASK_LOW_AW_11 0x376690
+
+#define mmSIF_RTR_CTRL_7_RANGE_SEC_MASK_LOW_AW_12 0x376694
+
+#define mmSIF_RTR_CTRL_7_RANGE_SEC_MASK_LOW_AW_13 0x376698
+
+#define mmSIF_RTR_CTRL_7_RANGE_SEC_MASK_LOW_AW_14 0x37669C
+
+#define mmSIF_RTR_CTRL_7_RANGE_SEC_MASK_LOW_AW_15 0x3766A0
+
+#define mmSIF_RTR_CTRL_7_RANGE_SEC_MASK_HIGH_AW_0 0x3766A4
+
+#define mmSIF_RTR_CTRL_7_RANGE_SEC_MASK_HIGH_AW_1 0x3766A8
+
+#define mmSIF_RTR_CTRL_7_RANGE_SEC_MASK_HIGH_AW_2 0x3766AC
+
+#define mmSIF_RTR_CTRL_7_RANGE_SEC_MASK_HIGH_AW_3 0x3766B0
+
+#define mmSIF_RTR_CTRL_7_RANGE_SEC_MASK_HIGH_AW_4 0x3766B4
+
+#define mmSIF_RTR_CTRL_7_RANGE_SEC_MASK_HIGH_AW_5 0x3766B8
+
+#define mmSIF_RTR_CTRL_7_RANGE_SEC_MASK_HIGH_AW_6 0x3766BC
+
+#define mmSIF_RTR_CTRL_7_RANGE_SEC_MASK_HIGH_AW_7 0x3766C0
+
+#define mmSIF_RTR_CTRL_7_RANGE_SEC_MASK_HIGH_AW_8 0x3766C4
+
+#define mmSIF_RTR_CTRL_7_RANGE_SEC_MASK_HIGH_AW_9 0x3766C8
+
+#define mmSIF_RTR_CTRL_7_RANGE_SEC_MASK_HIGH_AW_10 0x3766CC
+
+#define mmSIF_RTR_CTRL_7_RANGE_SEC_MASK_HIGH_AW_11 0x3766D0
+
+#define mmSIF_RTR_CTRL_7_RANGE_SEC_MASK_HIGH_AW_12 0x3766D4
+
+#define mmSIF_RTR_CTRL_7_RANGE_SEC_MASK_HIGH_AW_13 0x3766D8
+
+#define mmSIF_RTR_CTRL_7_RANGE_SEC_MASK_HIGH_AW_14 0x3766DC
+
+#define mmSIF_RTR_CTRL_7_RANGE_SEC_MASK_HIGH_AW_15 0x3766E0
+
+#define mmSIF_RTR_CTRL_7_RANGE_PRIV_BASE_LOW_AW_0 0x3766E4
+
+#define mmSIF_RTR_CTRL_7_RANGE_PRIV_BASE_LOW_AW_1 0x3766E8
+
+#define mmSIF_RTR_CTRL_7_RANGE_PRIV_BASE_LOW_AW_2 0x3766EC
+
+#define mmSIF_RTR_CTRL_7_RANGE_PRIV_BASE_LOW_AW_3 0x3766F0
+
+#define mmSIF_RTR_CTRL_7_RANGE_PRIV_BASE_LOW_AW_4 0x3766F4
+
+#define mmSIF_RTR_CTRL_7_RANGE_PRIV_BASE_LOW_AW_5 0x3766F8
+
+#define mmSIF_RTR_CTRL_7_RANGE_PRIV_BASE_LOW_AW_6 0x3766FC
+
+#define mmSIF_RTR_CTRL_7_RANGE_PRIV_BASE_LOW_AW_7 0x376700
+
+#define mmSIF_RTR_CTRL_7_RANGE_PRIV_BASE_LOW_AW_8 0x376704
+
+#define mmSIF_RTR_CTRL_7_RANGE_PRIV_BASE_LOW_AW_9 0x376708
+
+#define mmSIF_RTR_CTRL_7_RANGE_PRIV_BASE_LOW_AW_10 0x37670C
+
+#define mmSIF_RTR_CTRL_7_RANGE_PRIV_BASE_LOW_AW_11 0x376710
+
+#define mmSIF_RTR_CTRL_7_RANGE_PRIV_BASE_LOW_AW_12 0x376714
+
+#define mmSIF_RTR_CTRL_7_RANGE_PRIV_BASE_LOW_AW_13 0x376718
+
+#define mmSIF_RTR_CTRL_7_RANGE_PRIV_BASE_LOW_AW_14 0x37671C
+
+#define mmSIF_RTR_CTRL_7_RANGE_PRIV_BASE_LOW_AW_15 0x376720
+
+#define mmSIF_RTR_CTRL_7_RANGE_PRIV_BASE_HIGH_AW_0 0x376724
+
+#define mmSIF_RTR_CTRL_7_RANGE_PRIV_BASE_HIGH_AW_1 0x376728
+
+#define mmSIF_RTR_CTRL_7_RANGE_PRIV_BASE_HIGH_AW_2 0x37672C
+
+#define mmSIF_RTR_CTRL_7_RANGE_PRIV_BASE_HIGH_AW_3 0x376730
+
+#define mmSIF_RTR_CTRL_7_RANGE_PRIV_BASE_HIGH_AW_4 0x376734
+
+#define mmSIF_RTR_CTRL_7_RANGE_PRIV_BASE_HIGH_AW_5 0x376738
+
+#define mmSIF_RTR_CTRL_7_RANGE_PRIV_BASE_HIGH_AW_6 0x37673C
+
+#define mmSIF_RTR_CTRL_7_RANGE_PRIV_BASE_HIGH_AW_7 0x376740
+
+#define mmSIF_RTR_CTRL_7_RANGE_PRIV_BASE_HIGH_AW_8 0x376744
+
+#define mmSIF_RTR_CTRL_7_RANGE_PRIV_BASE_HIGH_AW_9 0x376748
+
+#define mmSIF_RTR_CTRL_7_RANGE_PRIV_BASE_HIGH_AW_10 0x37674C
+
+#define mmSIF_RTR_CTRL_7_RANGE_PRIV_BASE_HIGH_AW_11 0x376750
+
+#define mmSIF_RTR_CTRL_7_RANGE_PRIV_BASE_HIGH_AW_12 0x376754
+
+#define mmSIF_RTR_CTRL_7_RANGE_PRIV_BASE_HIGH_AW_13 0x376758
+
+#define mmSIF_RTR_CTRL_7_RANGE_PRIV_BASE_HIGH_AW_14 0x37675C
+
+#define mmSIF_RTR_CTRL_7_RANGE_PRIV_BASE_HIGH_AW_15 0x376760
+
+#define mmSIF_RTR_CTRL_7_RANGE_PRIV_MASK_LOW_AW_0 0x376764
+
+#define mmSIF_RTR_CTRL_7_RANGE_PRIV_MASK_LOW_AW_1 0x376768
+
+#define mmSIF_RTR_CTRL_7_RANGE_PRIV_MASK_LOW_AW_2 0x37676C
+
+#define mmSIF_RTR_CTRL_7_RANGE_PRIV_MASK_LOW_AW_3 0x376770
+
+#define mmSIF_RTR_CTRL_7_RANGE_PRIV_MASK_LOW_AW_4 0x376774
+
+#define mmSIF_RTR_CTRL_7_RANGE_PRIV_MASK_LOW_AW_5 0x376778
+
+#define mmSIF_RTR_CTRL_7_RANGE_PRIV_MASK_LOW_AW_6 0x37677C
+
+#define mmSIF_RTR_CTRL_7_RANGE_PRIV_MASK_LOW_AW_7 0x376780
+
+#define mmSIF_RTR_CTRL_7_RANGE_PRIV_MASK_LOW_AW_8 0x376784
+
+#define mmSIF_RTR_CTRL_7_RANGE_PRIV_MASK_LOW_AW_9 0x376788
+
+#define mmSIF_RTR_CTRL_7_RANGE_PRIV_MASK_LOW_AW_10 0x37678C
+
+#define mmSIF_RTR_CTRL_7_RANGE_PRIV_MASK_LOW_AW_11 0x376790
+
+#define mmSIF_RTR_CTRL_7_RANGE_PRIV_MASK_LOW_AW_12 0x376794
+
+#define mmSIF_RTR_CTRL_7_RANGE_PRIV_MASK_LOW_AW_13 0x376798
+
+#define mmSIF_RTR_CTRL_7_RANGE_PRIV_MASK_LOW_AW_14 0x37679C
+
+#define mmSIF_RTR_CTRL_7_RANGE_PRIV_MASK_LOW_AW_15 0x3767A0
+
+#define mmSIF_RTR_CTRL_7_RANGE_PRIV_MASK_HIGH_AW_0 0x3767A4
+
+#define mmSIF_RTR_CTRL_7_RANGE_PRIV_MASK_HIGH_AW_1 0x3767A8
+
+#define mmSIF_RTR_CTRL_7_RANGE_PRIV_MASK_HIGH_AW_2 0x3767AC
+
+#define mmSIF_RTR_CTRL_7_RANGE_PRIV_MASK_HIGH_AW_3 0x3767B0
+
+#define mmSIF_RTR_CTRL_7_RANGE_PRIV_MASK_HIGH_AW_4 0x3767B4
+
+#define mmSIF_RTR_CTRL_7_RANGE_PRIV_MASK_HIGH_AW_5 0x3767B8
+
+#define mmSIF_RTR_CTRL_7_RANGE_PRIV_MASK_HIGH_AW_6 0x3767BC
+
+#define mmSIF_RTR_CTRL_7_RANGE_PRIV_MASK_HIGH_AW_7 0x3767C0
+
+#define mmSIF_RTR_CTRL_7_RANGE_PRIV_MASK_HIGH_AW_8 0x3767C4
+
+#define mmSIF_RTR_CTRL_7_RANGE_PRIV_MASK_HIGH_AW_9 0x3767C8
+
+#define mmSIF_RTR_CTRL_7_RANGE_PRIV_MASK_HIGH_AW_10 0x3767CC
+
+#define mmSIF_RTR_CTRL_7_RANGE_PRIV_MASK_HIGH_AW_11 0x3767D0
+
+#define mmSIF_RTR_CTRL_7_RANGE_PRIV_MASK_HIGH_AW_12 0x3767D4
+
+#define mmSIF_RTR_CTRL_7_RANGE_PRIV_MASK_HIGH_AW_13 0x3767D8
+
+#define mmSIF_RTR_CTRL_7_RANGE_PRIV_MASK_HIGH_AW_14 0x3767DC
+
+#define mmSIF_RTR_CTRL_7_RANGE_PRIV_MASK_HIGH_AW_15 0x3767E0
+
+#define mmSIF_RTR_CTRL_7_RANGE_SEC_BASE_LOW_AR_0 0x376824
+
+#define mmSIF_RTR_CTRL_7_RANGE_SEC_BASE_LOW_AR_1 0x376828
+
+#define mmSIF_RTR_CTRL_7_RANGE_SEC_BASE_LOW_AR_2 0x37682C
+
+#define mmSIF_RTR_CTRL_7_RANGE_SEC_BASE_LOW_AR_3 0x376830
+
+#define mmSIF_RTR_CTRL_7_RANGE_SEC_BASE_LOW_AR_4 0x376834
+
+#define mmSIF_RTR_CTRL_7_RANGE_SEC_BASE_LOW_AR_5 0x376838
+
+#define mmSIF_RTR_CTRL_7_RANGE_SEC_BASE_LOW_AR_6 0x37683C
+
+#define mmSIF_RTR_CTRL_7_RANGE_SEC_BASE_LOW_AR_7 0x376840
+
+#define mmSIF_RTR_CTRL_7_RANGE_SEC_BASE_LOW_AR_8 0x376844
+
+#define mmSIF_RTR_CTRL_7_RANGE_SEC_BASE_LOW_AR_9 0x376848
+
+#define mmSIF_RTR_CTRL_7_RANGE_SEC_BASE_LOW_AR_10 0x37684C
+
+#define mmSIF_RTR_CTRL_7_RANGE_SEC_BASE_LOW_AR_11 0x376850
+
+#define mmSIF_RTR_CTRL_7_RANGE_SEC_BASE_LOW_AR_12 0x376854
+
+#define mmSIF_RTR_CTRL_7_RANGE_SEC_BASE_LOW_AR_13 0x376858
+
+#define mmSIF_RTR_CTRL_7_RANGE_SEC_BASE_LOW_AR_14 0x37685C
+
+#define mmSIF_RTR_CTRL_7_RANGE_SEC_BASE_LOW_AR_15 0x376860
+
+#define mmSIF_RTR_CTRL_7_RANGE_SEC_BASE_HIGH_AR_0 0x376864
+
+#define mmSIF_RTR_CTRL_7_RANGE_SEC_BASE_HIGH_AR_1 0x376868
+
+#define mmSIF_RTR_CTRL_7_RANGE_SEC_BASE_HIGH_AR_2 0x37686C
+
+#define mmSIF_RTR_CTRL_7_RANGE_SEC_BASE_HIGH_AR_3 0x376870
+
+#define mmSIF_RTR_CTRL_7_RANGE_SEC_BASE_HIGH_AR_4 0x376874
+
+#define mmSIF_RTR_CTRL_7_RANGE_SEC_BASE_HIGH_AR_5 0x376878
+
+#define mmSIF_RTR_CTRL_7_RANGE_SEC_BASE_HIGH_AR_6 0x37687C
+
+#define mmSIF_RTR_CTRL_7_RANGE_SEC_BASE_HIGH_AR_7 0x376880
+
+#define mmSIF_RTR_CTRL_7_RANGE_SEC_BASE_HIGH_AR_8 0x376884
+
+#define mmSIF_RTR_CTRL_7_RANGE_SEC_BASE_HIGH_AR_9 0x376888
+
+#define mmSIF_RTR_CTRL_7_RANGE_SEC_BASE_HIGH_AR_10 0x37688C
+
+#define mmSIF_RTR_CTRL_7_RANGE_SEC_BASE_HIGH_AR_11 0x376890
+
+#define mmSIF_RTR_CTRL_7_RANGE_SEC_BASE_HIGH_AR_12 0x376894
+
+#define mmSIF_RTR_CTRL_7_RANGE_SEC_BASE_HIGH_AR_13 0x376898
+
+#define mmSIF_RTR_CTRL_7_RANGE_SEC_BASE_HIGH_AR_14 0x37689C
+
+#define mmSIF_RTR_CTRL_7_RANGE_SEC_BASE_HIGH_AR_15 0x3768A0
+
+#define mmSIF_RTR_CTRL_7_RANGE_SEC_MASK_LOW_AR_0 0x3768A4
+
+#define mmSIF_RTR_CTRL_7_RANGE_SEC_MASK_LOW_AR_1 0x3768A8
+
+#define mmSIF_RTR_CTRL_7_RANGE_SEC_MASK_LOW_AR_2 0x3768AC
+
+#define mmSIF_RTR_CTRL_7_RANGE_SEC_MASK_LOW_AR_3 0x3768B0
+
+#define mmSIF_RTR_CTRL_7_RANGE_SEC_MASK_LOW_AR_4 0x3768B4
+
+#define mmSIF_RTR_CTRL_7_RANGE_SEC_MASK_LOW_AR_5 0x3768B8
+
+#define mmSIF_RTR_CTRL_7_RANGE_SEC_MASK_LOW_AR_6 0x3768BC
+
+#define mmSIF_RTR_CTRL_7_RANGE_SEC_MASK_LOW_AR_7 0x3768C0
+
+#define mmSIF_RTR_CTRL_7_RANGE_SEC_MASK_LOW_AR_8 0x3768C4
+
+#define mmSIF_RTR_CTRL_7_RANGE_SEC_MASK_LOW_AR_9 0x3768C8
+
+#define mmSIF_RTR_CTRL_7_RANGE_SEC_MASK_LOW_AR_10 0x3768CC
+
+#define mmSIF_RTR_CTRL_7_RANGE_SEC_MASK_LOW_AR_11 0x3768D0
+
+#define mmSIF_RTR_CTRL_7_RANGE_SEC_MASK_LOW_AR_12 0x3768D4
+
+#define mmSIF_RTR_CTRL_7_RANGE_SEC_MASK_LOW_AR_13 0x3768D8
+
+#define mmSIF_RTR_CTRL_7_RANGE_SEC_MASK_LOW_AR_14 0x3768DC
+
+#define mmSIF_RTR_CTRL_7_RANGE_SEC_MASK_LOW_AR_15 0x3768E0
+
+#define mmSIF_RTR_CTRL_7_RANGE_SEC_MASK_HIGH_AR_0 0x3768E4
+
+#define mmSIF_RTR_CTRL_7_RANGE_SEC_MASK_HIGH_AR_1 0x3768E8
+
+#define mmSIF_RTR_CTRL_7_RANGE_SEC_MASK_HIGH_AR_2 0x3768EC
+
+#define mmSIF_RTR_CTRL_7_RANGE_SEC_MASK_HIGH_AR_3 0x3768F0
+
+#define mmSIF_RTR_CTRL_7_RANGE_SEC_MASK_HIGH_AR_4 0x3768F4
+
+#define mmSIF_RTR_CTRL_7_RANGE_SEC_MASK_HIGH_AR_5 0x3768F8
+
+#define mmSIF_RTR_CTRL_7_RANGE_SEC_MASK_HIGH_AR_6 0x3768FC
+
+#define mmSIF_RTR_CTRL_7_RANGE_SEC_MASK_HIGH_AR_7 0x376900
+
+#define mmSIF_RTR_CTRL_7_RANGE_SEC_MASK_HIGH_AR_8 0x376904
+
+#define mmSIF_RTR_CTRL_7_RANGE_SEC_MASK_HIGH_AR_9 0x376908
+
+#define mmSIF_RTR_CTRL_7_RANGE_SEC_MASK_HIGH_AR_10 0x37690C
+
+#define mmSIF_RTR_CTRL_7_RANGE_SEC_MASK_HIGH_AR_11 0x376910
+
+#define mmSIF_RTR_CTRL_7_RANGE_SEC_MASK_HIGH_AR_12 0x376914
+
+#define mmSIF_RTR_CTRL_7_RANGE_SEC_MASK_HIGH_AR_13 0x376918
+
+#define mmSIF_RTR_CTRL_7_RANGE_SEC_MASK_HIGH_AR_14 0x37691C
+
+#define mmSIF_RTR_CTRL_7_RANGE_SEC_MASK_HIGH_AR_15 0x376920
+
+#define mmSIF_RTR_CTRL_7_RANGE_PRIV_BASE_LOW_AR_0 0x376924
+
+#define mmSIF_RTR_CTRL_7_RANGE_PRIV_BASE_LOW_AR_1 0x376928
+
+#define mmSIF_RTR_CTRL_7_RANGE_PRIV_BASE_LOW_AR_2 0x37692C
+
+#define mmSIF_RTR_CTRL_7_RANGE_PRIV_BASE_LOW_AR_3 0x376930
+
+#define mmSIF_RTR_CTRL_7_RANGE_PRIV_BASE_LOW_AR_4 0x376934
+
+#define mmSIF_RTR_CTRL_7_RANGE_PRIV_BASE_LOW_AR_5 0x376938
+
+#define mmSIF_RTR_CTRL_7_RANGE_PRIV_BASE_LOW_AR_6 0x37693C
+
+#define mmSIF_RTR_CTRL_7_RANGE_PRIV_BASE_LOW_AR_7 0x376940
+
+#define mmSIF_RTR_CTRL_7_RANGE_PRIV_BASE_LOW_AR_8 0x376944
+
+#define mmSIF_RTR_CTRL_7_RANGE_PRIV_BASE_LOW_AR_9 0x376948
+
+#define mmSIF_RTR_CTRL_7_RANGE_PRIV_BASE_LOW_AR_10 0x37694C
+
+#define mmSIF_RTR_CTRL_7_RANGE_PRIV_BASE_LOW_AR_11 0x376950
+
+#define mmSIF_RTR_CTRL_7_RANGE_PRIV_BASE_LOW_AR_12 0x376954
+
+#define mmSIF_RTR_CTRL_7_RANGE_PRIV_BASE_LOW_AR_13 0x376958
+
+#define mmSIF_RTR_CTRL_7_RANGE_PRIV_BASE_LOW_AR_14 0x37695C
+
+#define mmSIF_RTR_CTRL_7_RANGE_PRIV_BASE_LOW_AR_15 0x376960
+
+#define mmSIF_RTR_CTRL_7_RANGE_PRIV_BASE_HIGH_AR_0 0x376964
+
+#define mmSIF_RTR_CTRL_7_RANGE_PRIV_BASE_HIGH_AR_1 0x376968
+
+#define mmSIF_RTR_CTRL_7_RANGE_PRIV_BASE_HIGH_AR_2 0x37696C
+
+#define mmSIF_RTR_CTRL_7_RANGE_PRIV_BASE_HIGH_AR_3 0x376970
+
+#define mmSIF_RTR_CTRL_7_RANGE_PRIV_BASE_HIGH_AR_4 0x376974
+
+#define mmSIF_RTR_CTRL_7_RANGE_PRIV_BASE_HIGH_AR_5 0x376978
+
+#define mmSIF_RTR_CTRL_7_RANGE_PRIV_BASE_HIGH_AR_6 0x37697C
+
+#define mmSIF_RTR_CTRL_7_RANGE_PRIV_BASE_HIGH_AR_7 0x376980
+
+#define mmSIF_RTR_CTRL_7_RANGE_PRIV_BASE_HIGH_AR_8 0x376984
+
+#define mmSIF_RTR_CTRL_7_RANGE_PRIV_BASE_HIGH_AR_9 0x376988
+
+#define mmSIF_RTR_CTRL_7_RANGE_PRIV_BASE_HIGH_AR_10 0x37698C
+
+#define mmSIF_RTR_CTRL_7_RANGE_PRIV_BASE_HIGH_AR_11 0x376990
+
+#define mmSIF_RTR_CTRL_7_RANGE_PRIV_BASE_HIGH_AR_12 0x376994
+
+#define mmSIF_RTR_CTRL_7_RANGE_PRIV_BASE_HIGH_AR_13 0x376998
+
+#define mmSIF_RTR_CTRL_7_RANGE_PRIV_BASE_HIGH_AR_14 0x37699C
+
+#define mmSIF_RTR_CTRL_7_RANGE_PRIV_BASE_HIGH_AR_15 0x3769A0
+
+#define mmSIF_RTR_CTRL_7_RANGE_PRIV_MASK_LOW_AR_0 0x3769A4
+
+#define mmSIF_RTR_CTRL_7_RANGE_PRIV_MASK_LOW_AR_1 0x3769A8
+
+#define mmSIF_RTR_CTRL_7_RANGE_PRIV_MASK_LOW_AR_2 0x3769AC
+
+#define mmSIF_RTR_CTRL_7_RANGE_PRIV_MASK_LOW_AR_3 0x3769B0
+
+#define mmSIF_RTR_CTRL_7_RANGE_PRIV_MASK_LOW_AR_4 0x3769B4
+
+#define mmSIF_RTR_CTRL_7_RANGE_PRIV_MASK_LOW_AR_5 0x3769B8
+
+#define mmSIF_RTR_CTRL_7_RANGE_PRIV_MASK_LOW_AR_6 0x3769BC
+
+#define mmSIF_RTR_CTRL_7_RANGE_PRIV_MASK_LOW_AR_7 0x3769C0
+
+#define mmSIF_RTR_CTRL_7_RANGE_PRIV_MASK_LOW_AR_8 0x3769C4
+
+#define mmSIF_RTR_CTRL_7_RANGE_PRIV_MASK_LOW_AR_9 0x3769C8
+
+#define mmSIF_RTR_CTRL_7_RANGE_PRIV_MASK_LOW_AR_10 0x3769CC
+
+#define mmSIF_RTR_CTRL_7_RANGE_PRIV_MASK_LOW_AR_11 0x3769D0
+
+#define mmSIF_RTR_CTRL_7_RANGE_PRIV_MASK_LOW_AR_12 0x3769D4
+
+#define mmSIF_RTR_CTRL_7_RANGE_PRIV_MASK_LOW_AR_13 0x3769D8
+
+#define mmSIF_RTR_CTRL_7_RANGE_PRIV_MASK_LOW_AR_14 0x3769DC
+
+#define mmSIF_RTR_CTRL_7_RANGE_PRIV_MASK_LOW_AR_15 0x3769E0
+
+#define mmSIF_RTR_CTRL_7_RANGE_PRIV_MASK_HIGH_AR_0 0x3769E4
+
+#define mmSIF_RTR_CTRL_7_RANGE_PRIV_MASK_HIGH_AR_1 0x3769E8
+
+#define mmSIF_RTR_CTRL_7_RANGE_PRIV_MASK_HIGH_AR_2 0x3769EC
+
+#define mmSIF_RTR_CTRL_7_RANGE_PRIV_MASK_HIGH_AR_3 0x3769F0
+
+#define mmSIF_RTR_CTRL_7_RANGE_PRIV_MASK_HIGH_AR_4 0x3769F4
+
+#define mmSIF_RTR_CTRL_7_RANGE_PRIV_MASK_HIGH_AR_5 0x3769F8
+
+#define mmSIF_RTR_CTRL_7_RANGE_PRIV_MASK_HIGH_AR_6 0x3769FC
+
+#define mmSIF_RTR_CTRL_7_RANGE_PRIV_MASK_HIGH_AR_7 0x376A00
+
+#define mmSIF_RTR_CTRL_7_RANGE_PRIV_MASK_HIGH_AR_8 0x376A04
+
+#define mmSIF_RTR_CTRL_7_RANGE_PRIV_MASK_HIGH_AR_9 0x376A08
+
+#define mmSIF_RTR_CTRL_7_RANGE_PRIV_MASK_HIGH_AR_10 0x376A0C
+
+#define mmSIF_RTR_CTRL_7_RANGE_PRIV_MASK_HIGH_AR_11 0x376A10
+
+#define mmSIF_RTR_CTRL_7_RANGE_PRIV_MASK_HIGH_AR_12 0x376A14
+
+#define mmSIF_RTR_CTRL_7_RANGE_PRIV_MASK_HIGH_AR_13 0x376A18
+
+#define mmSIF_RTR_CTRL_7_RANGE_PRIV_MASK_HIGH_AR_14 0x376A1C
+
+#define mmSIF_RTR_CTRL_7_RANGE_PRIV_MASK_HIGH_AR_15 0x376A20
+
+#define mmSIF_RTR_CTRL_7_RANGE_SEC_HIT_AW 0x376A64
+
+#define mmSIF_RTR_CTRL_7_RANGE_SEC_HIT_AR 0x376A68
+
+#define mmSIF_RTR_CTRL_7_RANGE_PRIV_HIT_AW 0x376A6C
+
+#define mmSIF_RTR_CTRL_7_RANGE_PRIV_HIT_AR 0x376A70
+
+#define mmSIF_RTR_CTRL_7_RGL_CFG 0x376B64
+
+#define mmSIF_RTR_CTRL_7_RGL_SHIFT 0x376B68
+
+#define mmSIF_RTR_CTRL_7_RGL_EXPECTED_LAT_0 0x376B6C
+
+#define mmSIF_RTR_CTRL_7_RGL_EXPECTED_LAT_1 0x376B70
+
+#define mmSIF_RTR_CTRL_7_RGL_EXPECTED_LAT_2 0x376B74
+
+#define mmSIF_RTR_CTRL_7_RGL_EXPECTED_LAT_3 0x376B78
+
+#define mmSIF_RTR_CTRL_7_RGL_EXPECTED_LAT_4 0x376B7C
+
+#define mmSIF_RTR_CTRL_7_RGL_EXPECTED_LAT_5 0x376B80
+
+#define mmSIF_RTR_CTRL_7_RGL_EXPECTED_LAT_6 0x376B84
+
+#define mmSIF_RTR_CTRL_7_RGL_EXPECTED_LAT_7 0x376B88
+
+#define mmSIF_RTR_CTRL_7_RGL_TOKEN_0 0x376BAC
+
+#define mmSIF_RTR_CTRL_7_RGL_TOKEN_1 0x376BB0
+
+#define mmSIF_RTR_CTRL_7_RGL_TOKEN_2 0x376BB4
+
+#define mmSIF_RTR_CTRL_7_RGL_TOKEN_3 0x376BB8
+
+#define mmSIF_RTR_CTRL_7_RGL_TOKEN_4 0x376BBC
+
+#define mmSIF_RTR_CTRL_7_RGL_TOKEN_5 0x376BC0
+
+#define mmSIF_RTR_CTRL_7_RGL_TOKEN_6 0x376BC4
+
+#define mmSIF_RTR_CTRL_7_RGL_TOKEN_7 0x376BC8
+
+#define mmSIF_RTR_CTRL_7_RGL_BANK_ID_0 0x376BEC
+
+#define mmSIF_RTR_CTRL_7_RGL_BANK_ID_1 0x376BF0
+
+#define mmSIF_RTR_CTRL_7_RGL_BANK_ID_2 0x376BF4
+
+#define mmSIF_RTR_CTRL_7_RGL_BANK_ID_3 0x376BF8
+
+#define mmSIF_RTR_CTRL_7_RGL_BANK_ID_4 0x376BFC
+
+#define mmSIF_RTR_CTRL_7_RGL_BANK_ID_5 0x376C00
+
+#define mmSIF_RTR_CTRL_7_RGL_BANK_ID_6 0x376C04
+
+#define mmSIF_RTR_CTRL_7_RGL_BANK_ID_7 0x376C08
+
+#define mmSIF_RTR_CTRL_7_RGL_WDT 0x376C2C
+
+#define mmSIF_RTR_CTRL_7_E2E_AR_HBM0_CH0_CTR_WRAP 0x376C30
+
+#define mmSIF_RTR_CTRL_7_E2E_AR_HBM0_CH1_CTR_WRAP 0x376C34
+
+#define mmSIF_RTR_CTRL_7_E2E_AR_HBM1_CH0_CTR_WRAP 0x376C38
+
+#define mmSIF_RTR_CTRL_7_E2E_AR_HBM1_CH1_CTR_WRAP 0x376C3C
+
+#define mmSIF_RTR_CTRL_7_E2E_AR_HBM2_CH0_CTR_WRAP 0x376C40
+
+#define mmSIF_RTR_CTRL_7_E2E_AR_HBM2_CH1_CTR_WRAP 0x376C44
+
+#define mmSIF_RTR_CTRL_7_E2E_AR_HBM3_CH0_CTR_WRAP 0x376C48
+
+#define mmSIF_RTR_CTRL_7_E2E_AR_HBM3_CH1_CTR_WRAP 0x376C4C
+
+#define mmSIF_RTR_CTRL_7_E2E_AR_HBM0_CH0_CTR_CNT 0x376C50
+
+#define mmSIF_RTR_CTRL_7_E2E_AR_HBM0_CH1_CTR_CNT 0x376C54
+
+#define mmSIF_RTR_CTRL_7_E2E_AR_HBM1_CH0_CTR_CNT 0x376C58
+
+#define mmSIF_RTR_CTRL_7_E2E_AR_HBM1_CH1_CTR_CNT 0x376C5C
+
+#define mmSIF_RTR_CTRL_7_E2E_AR_HBM2_CH0_CTR_CNT 0x376C60
+
+#define mmSIF_RTR_CTRL_7_E2E_AR_HBM2_CH1_CTR_CNT 0x376C64
+
+#define mmSIF_RTR_CTRL_7_E2E_AR_HBM3_CH0_CTR_CNT 0x376C68
+
+#define mmSIF_RTR_CTRL_7_E2E_AR_HBM3_CH1_CTR_CNT 0x376C6C
+
+#define mmSIF_RTR_CTRL_7_E2E_AW_HBM0_CH0_CTR_WRAP 0x376C70
+
+#define mmSIF_RTR_CTRL_7_E2E_AW_HBM0_CH1_CTR_WRAP 0x376C74
+
+#define mmSIF_RTR_CTRL_7_E2E_AW_HBM1_CH0_CTR_WRAP 0x376C78
+
+#define mmSIF_RTR_CTRL_7_E2E_AW_HBM1_CH1_CTR_WRAP 0x376C7C
+
+#define mmSIF_RTR_CTRL_7_E2E_AW_HBM2_CH0_CTR_WRAP 0x376C80
+
+#define mmSIF_RTR_CTRL_7_E2E_AW_HBM2_CH1_CTR_WRAP 0x376C84
+
+#define mmSIF_RTR_CTRL_7_E2E_AW_HBM3_CH0_CTR_WRAP 0x376C88
+
+#define mmSIF_RTR_CTRL_7_E2E_AW_HBM3_CH1_CTR_WRAP 0x376C8C
+
+#define mmSIF_RTR_CTRL_7_E2E_AW_HBM0_CH0_CTR_CNT 0x376C90
+
+#define mmSIF_RTR_CTRL_7_E2E_AW_HBM0_CH1_CTR_CNT 0x376C94
+
+#define mmSIF_RTR_CTRL_7_E2E_AW_HBM1_CH0_CTR_CNT 0x376C98
+
+#define mmSIF_RTR_CTRL_7_E2E_AW_HBM1_CH1_CTR_CNT 0x376C9C
+
+#define mmSIF_RTR_CTRL_7_E2E_AW_HBM2_CH0_CTR_CNT 0x376CA0
+
+#define mmSIF_RTR_CTRL_7_E2E_AW_HBM2_CH1_CTR_CNT 0x376CA4
+
+#define mmSIF_RTR_CTRL_7_E2E_AW_HBM3_CH0_CTR_CNT 0x376CA8
+
+#define mmSIF_RTR_CTRL_7_E2E_AW_HBM3_CH1_CTR_CNT 0x376CAC
+
+#define mmSIF_RTR_CTRL_7_NL_HBM_PC_SEL_0 0x376CB0
+
+#define mmSIF_RTR_CTRL_7_NL_HBM_PC_SEL_1 0x376CB4
+
+#define mmSIF_RTR_CTRL_7_NL_HBM_PC_SEL_2 0x376CB8
+
+#define mmSIF_RTR_CTRL_7_NL_HBM_PC_SEL_3 0x376CBC
+
+#endif /* ASIC_REG_SIF_RTR_CTRL_7_REGS_H_ */
diff --git a/drivers/accel/habanalabs/include/gaudi/asic_reg/stlb_regs.h b/drivers/accel/habanalabs/include/gaudi/asic_reg/stlb_regs.h
new file mode 100644
index 0000000000..07d2a90001
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi/asic_reg/stlb_regs.h
@@ -0,0 +1,82 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2016-2018 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ ** DO NOT EDIT BELOW **
+ ************************************/
+
+#ifndef ASIC_REG_STLB_REGS_H_
+#define ASIC_REG_STLB_REGS_H_
+
+/*
+ *****************************************
+ * STLB (Prototype: STLB)
+ *****************************************
+ */
+
+#define mmSTLB_CACHE_INV 0xC12010
+
+#define mmSTLB_CACHE_INV_BASE_39_8 0xC12014
+
+#define mmSTLB_CACHE_INV_BASE_49_40 0xC12018
+
+#define mmSTLB_STLB_FEATURE_EN 0xC1201C
+
+#define mmSTLB_STLB_AXI_CACHE 0xC12020
+
+#define mmSTLB_HOP_CONFIGURATION 0xC12024
+
+#define mmSTLB_LINK_LIST_LOOKUP_MASK_49_32 0xC12028
+
+#define mmSTLB_LINK_LIST_LOOKUP_MASK_31_0 0xC1202C
+
+#define mmSTLB_LINK_LIST 0xC12030
+
+#define mmSTLB_INV_ALL_START 0xC12034
+
+#define mmSTLB_INV_ALL_SET 0xC12038
+
+#define mmSTLB_INV_PS 0xC1203C
+
+#define mmSTLB_INV_CONSUMER_INDEX 0xC12040
+
+#define mmSTLB_INV_HIT_COUNT 0xC12044
+
+#define mmSTLB_INV_SET 0xC12048
+
+#define mmSTLB_SRAM_INIT 0xC1204C
+
+#define mmSTLB_MEM_CACHE_INVALIDATION 0xC12050
+
+#define mmSTLB_MEM_CACHE_INV_STATUS 0xC12054
+
+#define mmSTLB_MEM_CACHE_BASE_38_7 0xC12058
+
+#define mmSTLB_MEM_CACHE_BASE_49_39 0xC1205C
+
+#define mmSTLB_MEM_CACHE_CONFIG 0xC12060
+
+#define mmSTLB_SET_THRESHOLD_HOP4 0xC12064
+
+#define mmSTLB_SET_THRESHOLD_HOP3 0xC12068
+
+#define mmSTLB_SET_THRESHOLD_HOP2 0xC1206C
+
+#define mmSTLB_SET_THRESHOLD_HOP1 0xC12070
+
+#define mmSTLB_SET_THRESHOLD_HOP0 0xC12074
+
+#define mmSTLB_MULTI_HIT_INTERRUPT_CLR 0xC12078
+
+#define mmSTLB_MULTI_HIT_INTERRUPT_MASK 0xC1207C
+
+#define mmSTLB_MEM_L0_CACHE_CFG 0xC12080
+
+#define mmSTLB_MEM_READ_ARPROT 0xC12084
+
+#endif /* ASIC_REG_STLB_REGS_H_ */
diff --git a/drivers/accel/habanalabs/include/gaudi/asic_reg/tpc0_cfg_masks.h b/drivers/accel/habanalabs/include/gaudi/asic_reg/tpc0_cfg_masks.h
new file mode 100644
index 0000000000..8f67c11c8d
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi/asic_reg/tpc0_cfg_masks.h
@@ -0,0 +1,2578 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2016-2018 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ ** DO NOT EDIT BELOW **
+ ************************************/
+
+#ifndef ASIC_REG_TPC0_CFG_MASKS_H_
+#define ASIC_REG_TPC0_CFG_MASKS_H_
+
+/*
+ *****************************************
+ * TPC0_CFG (Prototype: TPC)
+ *****************************************
+ */
+
+/* TPC0_CFG_KERNEL_TENSOR_0_BASE_ADDR_LOW */
+#define TPC0_CFG_KERNEL_TENSOR_0_BASE_ADDR_LOW_V_SHIFT 0
+#define TPC0_CFG_KERNEL_TENSOR_0_BASE_ADDR_LOW_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_0_BASE_ADDR_HIGH */
+#define TPC0_CFG_KERNEL_TENSOR_0_BASE_ADDR_HIGH_V_SHIFT 0
+#define TPC0_CFG_KERNEL_TENSOR_0_BASE_ADDR_HIGH_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_0_PADDING_VALUE */
+#define TPC0_CFG_KERNEL_TENSOR_0_PADDING_VALUE_V_SHIFT 0
+#define TPC0_CFG_KERNEL_TENSOR_0_PADDING_VALUE_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_0_TENSOR_CONFIG */
+#define TPC0_CFG_KERNEL_TENSOR_0_TENSOR_CONFIG_DATA_TYPE_SHIFT 0
+#define TPC0_CFG_KERNEL_TENSOR_0_TENSOR_CONFIG_DATA_TYPE_MASK 0x7
+#define TPC0_CFG_KERNEL_TENSOR_0_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT 8
+#define TPC0_CFG_KERNEL_TENSOR_0_TENSOR_CONFIG_VALID_DIM_MASK_MASK 0x1F00
+#define TPC0_CFG_KERNEL_TENSOR_0_TENSOR_CONFIG_LAST_DIM_SHIFT 16
+#define TPC0_CFG_KERNEL_TENSOR_0_TENSOR_CONFIG_LAST_DIM_MASK 0x70000
+#define TPC0_CFG_KERNEL_TENSOR_0_TENSOR_CONFIG_RMW_SET_SHIFT 19
+#define TPC0_CFG_KERNEL_TENSOR_0_TENSOR_CONFIG_RMW_SET_MASK 0x80000
+#define TPC0_CFG_KERNEL_TENSOR_0_TENSOR_CONFIG_RMW_RESERV_SHIFT 20
+#define TPC0_CFG_KERNEL_TENSOR_0_TENSOR_CONFIG_RMW_RESERV_MASK 0x100000
+#define TPC0_CFG_KERNEL_TENSOR_0_TENSOR_CONFIG_RMW_OP_SHIFT 21
+#define TPC0_CFG_KERNEL_TENSOR_0_TENSOR_CONFIG_RMW_OP_MASK 0x600000
+
+/* TPC0_CFG_KERNEL_TENSOR_0_DIM_0_SIZE */
+#define TPC0_CFG_KERNEL_TENSOR_0_DIM_0_SIZE_V_SHIFT 0
+#define TPC0_CFG_KERNEL_TENSOR_0_DIM_0_SIZE_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_0_DIM_0_STRIDE */
+#define TPC0_CFG_KERNEL_TENSOR_0_DIM_0_STRIDE_V_SHIFT 0
+#define TPC0_CFG_KERNEL_TENSOR_0_DIM_0_STRIDE_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_0_DIM_1_SIZE */
+#define TPC0_CFG_KERNEL_TENSOR_0_DIM_1_SIZE_V_SHIFT 0
+#define TPC0_CFG_KERNEL_TENSOR_0_DIM_1_SIZE_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_0_DIM_1_STRIDE */
+#define TPC0_CFG_KERNEL_TENSOR_0_DIM_1_STRIDE_V_SHIFT 0
+#define TPC0_CFG_KERNEL_TENSOR_0_DIM_1_STRIDE_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_0_DIM_2_SIZE */
+#define TPC0_CFG_KERNEL_TENSOR_0_DIM_2_SIZE_V_SHIFT 0
+#define TPC0_CFG_KERNEL_TENSOR_0_DIM_2_SIZE_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_0_DIM_2_STRIDE */
+#define TPC0_CFG_KERNEL_TENSOR_0_DIM_2_STRIDE_V_SHIFT 0
+#define TPC0_CFG_KERNEL_TENSOR_0_DIM_2_STRIDE_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_0_DIM_3_SIZE */
+#define TPC0_CFG_KERNEL_TENSOR_0_DIM_3_SIZE_V_SHIFT 0
+#define TPC0_CFG_KERNEL_TENSOR_0_DIM_3_SIZE_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_0_DIM_3_STRIDE */
+#define TPC0_CFG_KERNEL_TENSOR_0_DIM_3_STRIDE_V_SHIFT 0
+#define TPC0_CFG_KERNEL_TENSOR_0_DIM_3_STRIDE_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_0_DIM_4_SIZE */
+#define TPC0_CFG_KERNEL_TENSOR_0_DIM_4_SIZE_V_SHIFT 0
+#define TPC0_CFG_KERNEL_TENSOR_0_DIM_4_SIZE_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_0_DIM_4_STRIDE */
+#define TPC0_CFG_KERNEL_TENSOR_0_DIM_4_STRIDE_V_SHIFT 0
+#define TPC0_CFG_KERNEL_TENSOR_0_DIM_4_STRIDE_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_1_BASE_ADDR_LOW */
+#define TPC0_CFG_KERNEL_TENSOR_1_BASE_ADDR_LOW_V_SHIFT 0
+#define TPC0_CFG_KERNEL_TENSOR_1_BASE_ADDR_LOW_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_1_BASE_ADDR_HIGH */
+#define TPC0_CFG_KERNEL_TENSOR_1_BASE_ADDR_HIGH_V_SHIFT 0
+#define TPC0_CFG_KERNEL_TENSOR_1_BASE_ADDR_HIGH_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_1_PADDING_VALUE */
+#define TPC0_CFG_KERNEL_TENSOR_1_PADDING_VALUE_V_SHIFT 0
+#define TPC0_CFG_KERNEL_TENSOR_1_PADDING_VALUE_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_1_TENSOR_CONFIG */
+#define TPC0_CFG_KERNEL_TENSOR_1_TENSOR_CONFIG_DATA_TYPE_SHIFT 0
+#define TPC0_CFG_KERNEL_TENSOR_1_TENSOR_CONFIG_DATA_TYPE_MASK 0x7
+#define TPC0_CFG_KERNEL_TENSOR_1_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT 8
+#define TPC0_CFG_KERNEL_TENSOR_1_TENSOR_CONFIG_VALID_DIM_MASK_MASK 0x1F00
+#define TPC0_CFG_KERNEL_TENSOR_1_TENSOR_CONFIG_LAST_DIM_SHIFT 16
+#define TPC0_CFG_KERNEL_TENSOR_1_TENSOR_CONFIG_LAST_DIM_MASK 0x70000
+#define TPC0_CFG_KERNEL_TENSOR_1_TENSOR_CONFIG_RMW_SET_SHIFT 19
+#define TPC0_CFG_KERNEL_TENSOR_1_TENSOR_CONFIG_RMW_SET_MASK 0x80000
+#define TPC0_CFG_KERNEL_TENSOR_1_TENSOR_CONFIG_RMW_RESERV_SHIFT 20
+#define TPC0_CFG_KERNEL_TENSOR_1_TENSOR_CONFIG_RMW_RESERV_MASK 0x100000
+#define TPC0_CFG_KERNEL_TENSOR_1_TENSOR_CONFIG_RMW_OP_SHIFT 21
+#define TPC0_CFG_KERNEL_TENSOR_1_TENSOR_CONFIG_RMW_OP_MASK 0x600000
+
+/* TPC0_CFG_KERNEL_TENSOR_1_DIM_0_SIZE */
+#define TPC0_CFG_KERNEL_TENSOR_1_DIM_0_SIZE_V_SHIFT 0
+#define TPC0_CFG_KERNEL_TENSOR_1_DIM_0_SIZE_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_1_DIM_0_STRIDE */
+#define TPC0_CFG_KERNEL_TENSOR_1_DIM_0_STRIDE_V_SHIFT 0
+#define TPC0_CFG_KERNEL_TENSOR_1_DIM_0_STRIDE_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_1_DIM_1_SIZE */
+#define TPC0_CFG_KERNEL_TENSOR_1_DIM_1_SIZE_V_SHIFT 0
+#define TPC0_CFG_KERNEL_TENSOR_1_DIM_1_SIZE_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_1_DIM_1_STRIDE */
+#define TPC0_CFG_KERNEL_TENSOR_1_DIM_1_STRIDE_V_SHIFT 0
+#define TPC0_CFG_KERNEL_TENSOR_1_DIM_1_STRIDE_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_1_DIM_2_SIZE */
+#define TPC0_CFG_KERNEL_TENSOR_1_DIM_2_SIZE_V_SHIFT 0
+#define TPC0_CFG_KERNEL_TENSOR_1_DIM_2_SIZE_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_1_DIM_2_STRIDE */
+#define TPC0_CFG_KERNEL_TENSOR_1_DIM_2_STRIDE_V_SHIFT 0
+#define TPC0_CFG_KERNEL_TENSOR_1_DIM_2_STRIDE_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_1_DIM_3_SIZE */
+#define TPC0_CFG_KERNEL_TENSOR_1_DIM_3_SIZE_V_SHIFT 0
+#define TPC0_CFG_KERNEL_TENSOR_1_DIM_3_SIZE_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_1_DIM_3_STRIDE */
+#define TPC0_CFG_KERNEL_TENSOR_1_DIM_3_STRIDE_V_SHIFT 0
+#define TPC0_CFG_KERNEL_TENSOR_1_DIM_3_STRIDE_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_1_DIM_4_SIZE */
+#define TPC0_CFG_KERNEL_TENSOR_1_DIM_4_SIZE_V_SHIFT 0
+#define TPC0_CFG_KERNEL_TENSOR_1_DIM_4_SIZE_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_1_DIM_4_STRIDE */
+#define TPC0_CFG_KERNEL_TENSOR_1_DIM_4_STRIDE_V_SHIFT 0
+#define TPC0_CFG_KERNEL_TENSOR_1_DIM_4_STRIDE_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_2_BASE_ADDR_LOW */
+#define TPC0_CFG_KERNEL_TENSOR_2_BASE_ADDR_LOW_V_SHIFT 0
+#define TPC0_CFG_KERNEL_TENSOR_2_BASE_ADDR_LOW_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_2_BASE_ADDR_HIGH */
+#define TPC0_CFG_KERNEL_TENSOR_2_BASE_ADDR_HIGH_V_SHIFT 0
+#define TPC0_CFG_KERNEL_TENSOR_2_BASE_ADDR_HIGH_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_2_PADDING_VALUE */
+#define TPC0_CFG_KERNEL_TENSOR_2_PADDING_VALUE_V_SHIFT 0
+#define TPC0_CFG_KERNEL_TENSOR_2_PADDING_VALUE_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_2_TENSOR_CONFIG */
+#define TPC0_CFG_KERNEL_TENSOR_2_TENSOR_CONFIG_DATA_TYPE_SHIFT 0
+#define TPC0_CFG_KERNEL_TENSOR_2_TENSOR_CONFIG_DATA_TYPE_MASK 0x7
+#define TPC0_CFG_KERNEL_TENSOR_2_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT 8
+#define TPC0_CFG_KERNEL_TENSOR_2_TENSOR_CONFIG_VALID_DIM_MASK_MASK 0x1F00
+#define TPC0_CFG_KERNEL_TENSOR_2_TENSOR_CONFIG_LAST_DIM_SHIFT 16
+#define TPC0_CFG_KERNEL_TENSOR_2_TENSOR_CONFIG_LAST_DIM_MASK 0x70000
+#define TPC0_CFG_KERNEL_TENSOR_2_TENSOR_CONFIG_RMW_SET_SHIFT 19
+#define TPC0_CFG_KERNEL_TENSOR_2_TENSOR_CONFIG_RMW_SET_MASK 0x80000
+#define TPC0_CFG_KERNEL_TENSOR_2_TENSOR_CONFIG_RMW_RESERV_SHIFT 20
+#define TPC0_CFG_KERNEL_TENSOR_2_TENSOR_CONFIG_RMW_RESERV_MASK 0x100000
+#define TPC0_CFG_KERNEL_TENSOR_2_TENSOR_CONFIG_RMW_OP_SHIFT 21
+#define TPC0_CFG_KERNEL_TENSOR_2_TENSOR_CONFIG_RMW_OP_MASK 0x600000
+
+/* TPC0_CFG_KERNEL_TENSOR_2_DIM_0_SIZE */
+#define TPC0_CFG_KERNEL_TENSOR_2_DIM_0_SIZE_V_SHIFT 0
+#define TPC0_CFG_KERNEL_TENSOR_2_DIM_0_SIZE_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_2_DIM_0_STRIDE */
+#define TPC0_CFG_KERNEL_TENSOR_2_DIM_0_STRIDE_V_SHIFT 0
+#define TPC0_CFG_KERNEL_TENSOR_2_DIM_0_STRIDE_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_2_DIM_1_SIZE */
+#define TPC0_CFG_KERNEL_TENSOR_2_DIM_1_SIZE_V_SHIFT 0
+#define TPC0_CFG_KERNEL_TENSOR_2_DIM_1_SIZE_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_2_DIM_1_STRIDE */
+#define TPC0_CFG_KERNEL_TENSOR_2_DIM_1_STRIDE_V_SHIFT 0
+#define TPC0_CFG_KERNEL_TENSOR_2_DIM_1_STRIDE_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_2_DIM_2_SIZE */
+#define TPC0_CFG_KERNEL_TENSOR_2_DIM_2_SIZE_V_SHIFT 0
+#define TPC0_CFG_KERNEL_TENSOR_2_DIM_2_SIZE_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_2_DIM_2_STRIDE */
+#define TPC0_CFG_KERNEL_TENSOR_2_DIM_2_STRIDE_V_SHIFT 0
+#define TPC0_CFG_KERNEL_TENSOR_2_DIM_2_STRIDE_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_2_DIM_3_SIZE */
+#define TPC0_CFG_KERNEL_TENSOR_2_DIM_3_SIZE_V_SHIFT 0
+#define TPC0_CFG_KERNEL_TENSOR_2_DIM_3_SIZE_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_2_DIM_3_STRIDE */
+#define TPC0_CFG_KERNEL_TENSOR_2_DIM_3_STRIDE_V_SHIFT 0
+#define TPC0_CFG_KERNEL_TENSOR_2_DIM_3_STRIDE_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_2_DIM_4_SIZE */
+#define TPC0_CFG_KERNEL_TENSOR_2_DIM_4_SIZE_V_SHIFT 0
+#define TPC0_CFG_KERNEL_TENSOR_2_DIM_4_SIZE_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_2_DIM_4_STRIDE */
+#define TPC0_CFG_KERNEL_TENSOR_2_DIM_4_STRIDE_V_SHIFT 0
+#define TPC0_CFG_KERNEL_TENSOR_2_DIM_4_STRIDE_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_3_BASE_ADDR_LOW */
+#define TPC0_CFG_KERNEL_TENSOR_3_BASE_ADDR_LOW_V_SHIFT 0
+#define TPC0_CFG_KERNEL_TENSOR_3_BASE_ADDR_LOW_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_3_BASE_ADDR_HIGH */
+#define TPC0_CFG_KERNEL_TENSOR_3_BASE_ADDR_HIGH_V_SHIFT 0
+#define TPC0_CFG_KERNEL_TENSOR_3_BASE_ADDR_HIGH_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_3_PADDING_VALUE */
+#define TPC0_CFG_KERNEL_TENSOR_3_PADDING_VALUE_V_SHIFT 0
+#define TPC0_CFG_KERNEL_TENSOR_3_PADDING_VALUE_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_3_TENSOR_CONFIG */
+#define TPC0_CFG_KERNEL_TENSOR_3_TENSOR_CONFIG_DATA_TYPE_SHIFT 0
+#define TPC0_CFG_KERNEL_TENSOR_3_TENSOR_CONFIG_DATA_TYPE_MASK 0x7
+#define TPC0_CFG_KERNEL_TENSOR_3_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT 8
+#define TPC0_CFG_KERNEL_TENSOR_3_TENSOR_CONFIG_VALID_DIM_MASK_MASK 0x1F00
+#define TPC0_CFG_KERNEL_TENSOR_3_TENSOR_CONFIG_LAST_DIM_SHIFT 16
+#define TPC0_CFG_KERNEL_TENSOR_3_TENSOR_CONFIG_LAST_DIM_MASK 0x70000
+#define TPC0_CFG_KERNEL_TENSOR_3_TENSOR_CONFIG_RMW_SET_SHIFT 19
+#define TPC0_CFG_KERNEL_TENSOR_3_TENSOR_CONFIG_RMW_SET_MASK 0x80000
+#define TPC0_CFG_KERNEL_TENSOR_3_TENSOR_CONFIG_RMW_RESERV_SHIFT 20
+#define TPC0_CFG_KERNEL_TENSOR_3_TENSOR_CONFIG_RMW_RESERV_MASK 0x100000
+#define TPC0_CFG_KERNEL_TENSOR_3_TENSOR_CONFIG_RMW_OP_SHIFT 21
+#define TPC0_CFG_KERNEL_TENSOR_3_TENSOR_CONFIG_RMW_OP_MASK 0x600000
+
+/* TPC0_CFG_KERNEL_TENSOR_3_DIM_0_SIZE */
+#define TPC0_CFG_KERNEL_TENSOR_3_DIM_0_SIZE_V_SHIFT 0
+#define TPC0_CFG_KERNEL_TENSOR_3_DIM_0_SIZE_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_3_DIM_0_STRIDE */
+#define TPC0_CFG_KERNEL_TENSOR_3_DIM_0_STRIDE_V_SHIFT 0
+#define TPC0_CFG_KERNEL_TENSOR_3_DIM_0_STRIDE_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_3_DIM_1_SIZE */
+#define TPC0_CFG_KERNEL_TENSOR_3_DIM_1_SIZE_V_SHIFT 0
+#define TPC0_CFG_KERNEL_TENSOR_3_DIM_1_SIZE_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_3_DIM_1_STRIDE */
+#define TPC0_CFG_KERNEL_TENSOR_3_DIM_1_STRIDE_V_SHIFT 0
+#define TPC0_CFG_KERNEL_TENSOR_3_DIM_1_STRIDE_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_3_DIM_2_SIZE */
+#define TPC0_CFG_KERNEL_TENSOR_3_DIM_2_SIZE_V_SHIFT 0
+#define TPC0_CFG_KERNEL_TENSOR_3_DIM_2_SIZE_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_3_DIM_2_STRIDE */
+#define TPC0_CFG_KERNEL_TENSOR_3_DIM_2_STRIDE_V_SHIFT 0
+#define TPC0_CFG_KERNEL_TENSOR_3_DIM_2_STRIDE_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_3_DIM_3_SIZE */
+#define TPC0_CFG_KERNEL_TENSOR_3_DIM_3_SIZE_V_SHIFT 0
+#define TPC0_CFG_KERNEL_TENSOR_3_DIM_3_SIZE_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_3_DIM_3_STRIDE */
+#define TPC0_CFG_KERNEL_TENSOR_3_DIM_3_STRIDE_V_SHIFT 0
+#define TPC0_CFG_KERNEL_TENSOR_3_DIM_3_STRIDE_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_3_DIM_4_SIZE */
+#define TPC0_CFG_KERNEL_TENSOR_3_DIM_4_SIZE_V_SHIFT 0
+#define TPC0_CFG_KERNEL_TENSOR_3_DIM_4_SIZE_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_3_DIM_4_STRIDE */
+#define TPC0_CFG_KERNEL_TENSOR_3_DIM_4_STRIDE_V_SHIFT 0
+#define TPC0_CFG_KERNEL_TENSOR_3_DIM_4_STRIDE_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_4_BASE_ADDR_LOW */
+#define TPC0_CFG_KERNEL_TENSOR_4_BASE_ADDR_LOW_V_SHIFT 0
+#define TPC0_CFG_KERNEL_TENSOR_4_BASE_ADDR_LOW_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_4_BASE_ADDR_HIGH */
+#define TPC0_CFG_KERNEL_TENSOR_4_BASE_ADDR_HIGH_V_SHIFT 0
+#define TPC0_CFG_KERNEL_TENSOR_4_BASE_ADDR_HIGH_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_4_PADDING_VALUE */
+#define TPC0_CFG_KERNEL_TENSOR_4_PADDING_VALUE_V_SHIFT 0
+#define TPC0_CFG_KERNEL_TENSOR_4_PADDING_VALUE_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_4_TENSOR_CONFIG */
+#define TPC0_CFG_KERNEL_TENSOR_4_TENSOR_CONFIG_DATA_TYPE_SHIFT 0
+#define TPC0_CFG_KERNEL_TENSOR_4_TENSOR_CONFIG_DATA_TYPE_MASK 0x7
+#define TPC0_CFG_KERNEL_TENSOR_4_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT 8
+#define TPC0_CFG_KERNEL_TENSOR_4_TENSOR_CONFIG_VALID_DIM_MASK_MASK 0x1F00
+#define TPC0_CFG_KERNEL_TENSOR_4_TENSOR_CONFIG_LAST_DIM_SHIFT 16
+#define TPC0_CFG_KERNEL_TENSOR_4_TENSOR_CONFIG_LAST_DIM_MASK 0x70000
+#define TPC0_CFG_KERNEL_TENSOR_4_TENSOR_CONFIG_RMW_SET_SHIFT 19
+#define TPC0_CFG_KERNEL_TENSOR_4_TENSOR_CONFIG_RMW_SET_MASK 0x80000
+#define TPC0_CFG_KERNEL_TENSOR_4_TENSOR_CONFIG_RMW_RESERV_SHIFT 20
+#define TPC0_CFG_KERNEL_TENSOR_4_TENSOR_CONFIG_RMW_RESERV_MASK 0x100000
+#define TPC0_CFG_KERNEL_TENSOR_4_TENSOR_CONFIG_RMW_OP_SHIFT 21
+#define TPC0_CFG_KERNEL_TENSOR_4_TENSOR_CONFIG_RMW_OP_MASK 0x600000
+
+/* TPC0_CFG_KERNEL_TENSOR_4_DIM_0_SIZE */
+#define TPC0_CFG_KERNEL_TENSOR_4_DIM_0_SIZE_V_SHIFT 0
+#define TPC0_CFG_KERNEL_TENSOR_4_DIM_0_SIZE_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_4_DIM_0_STRIDE */
+#define TPC0_CFG_KERNEL_TENSOR_4_DIM_0_STRIDE_V_SHIFT 0
+#define TPC0_CFG_KERNEL_TENSOR_4_DIM_0_STRIDE_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_4_DIM_1_SIZE */
+#define TPC0_CFG_KERNEL_TENSOR_4_DIM_1_SIZE_V_SHIFT 0
+#define TPC0_CFG_KERNEL_TENSOR_4_DIM_1_SIZE_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_4_DIM_1_STRIDE */
+#define TPC0_CFG_KERNEL_TENSOR_4_DIM_1_STRIDE_V_SHIFT 0
+#define TPC0_CFG_KERNEL_TENSOR_4_DIM_1_STRIDE_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_4_DIM_2_SIZE */
+#define TPC0_CFG_KERNEL_TENSOR_4_DIM_2_SIZE_V_SHIFT 0
+#define TPC0_CFG_KERNEL_TENSOR_4_DIM_2_SIZE_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_4_DIM_2_STRIDE */
+#define TPC0_CFG_KERNEL_TENSOR_4_DIM_2_STRIDE_V_SHIFT 0
+#define TPC0_CFG_KERNEL_TENSOR_4_DIM_2_STRIDE_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_4_DIM_3_SIZE */
+#define TPC0_CFG_KERNEL_TENSOR_4_DIM_3_SIZE_V_SHIFT 0
+#define TPC0_CFG_KERNEL_TENSOR_4_DIM_3_SIZE_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_4_DIM_3_STRIDE */
+#define TPC0_CFG_KERNEL_TENSOR_4_DIM_3_STRIDE_V_SHIFT 0
+#define TPC0_CFG_KERNEL_TENSOR_4_DIM_3_STRIDE_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_4_DIM_4_SIZE */
+#define TPC0_CFG_KERNEL_TENSOR_4_DIM_4_SIZE_V_SHIFT 0
+#define TPC0_CFG_KERNEL_TENSOR_4_DIM_4_SIZE_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_4_DIM_4_STRIDE */
+#define TPC0_CFG_KERNEL_TENSOR_4_DIM_4_STRIDE_V_SHIFT 0
+#define TPC0_CFG_KERNEL_TENSOR_4_DIM_4_STRIDE_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_5_BASE_ADDR_LOW */
+#define TPC0_CFG_KERNEL_TENSOR_5_BASE_ADDR_LOW_V_SHIFT 0
+#define TPC0_CFG_KERNEL_TENSOR_5_BASE_ADDR_LOW_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_5_BASE_ADDR_HIGH */
+#define TPC0_CFG_KERNEL_TENSOR_5_BASE_ADDR_HIGH_V_SHIFT 0
+#define TPC0_CFG_KERNEL_TENSOR_5_BASE_ADDR_HIGH_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_5_PADDING_VALUE */
+#define TPC0_CFG_KERNEL_TENSOR_5_PADDING_VALUE_V_SHIFT 0
+#define TPC0_CFG_KERNEL_TENSOR_5_PADDING_VALUE_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_5_TENSOR_CONFIG */
+#define TPC0_CFG_KERNEL_TENSOR_5_TENSOR_CONFIG_DATA_TYPE_SHIFT 0
+#define TPC0_CFG_KERNEL_TENSOR_5_TENSOR_CONFIG_DATA_TYPE_MASK 0x7
+#define TPC0_CFG_KERNEL_TENSOR_5_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT 8
+#define TPC0_CFG_KERNEL_TENSOR_5_TENSOR_CONFIG_VALID_DIM_MASK_MASK 0x1F00
+#define TPC0_CFG_KERNEL_TENSOR_5_TENSOR_CONFIG_LAST_DIM_SHIFT 16
+#define TPC0_CFG_KERNEL_TENSOR_5_TENSOR_CONFIG_LAST_DIM_MASK 0x70000
+#define TPC0_CFG_KERNEL_TENSOR_5_TENSOR_CONFIG_RMW_SET_SHIFT 19
+#define TPC0_CFG_KERNEL_TENSOR_5_TENSOR_CONFIG_RMW_SET_MASK 0x80000
+#define TPC0_CFG_KERNEL_TENSOR_5_TENSOR_CONFIG_RMW_RESERV_SHIFT 20
+#define TPC0_CFG_KERNEL_TENSOR_5_TENSOR_CONFIG_RMW_RESERV_MASK 0x100000
+#define TPC0_CFG_KERNEL_TENSOR_5_TENSOR_CONFIG_RMW_OP_SHIFT 21
+#define TPC0_CFG_KERNEL_TENSOR_5_TENSOR_CONFIG_RMW_OP_MASK 0x600000
+
+/* TPC0_CFG_KERNEL_TENSOR_5_DIM_0_SIZE */
+#define TPC0_CFG_KERNEL_TENSOR_5_DIM_0_SIZE_V_SHIFT 0
+#define TPC0_CFG_KERNEL_TENSOR_5_DIM_0_SIZE_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_5_DIM_0_STRIDE */
+#define TPC0_CFG_KERNEL_TENSOR_5_DIM_0_STRIDE_V_SHIFT 0
+#define TPC0_CFG_KERNEL_TENSOR_5_DIM_0_STRIDE_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_5_DIM_1_SIZE */
+#define TPC0_CFG_KERNEL_TENSOR_5_DIM_1_SIZE_V_SHIFT 0
+#define TPC0_CFG_KERNEL_TENSOR_5_DIM_1_SIZE_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_5_DIM_1_STRIDE */
+#define TPC0_CFG_KERNEL_TENSOR_5_DIM_1_STRIDE_V_SHIFT 0
+#define TPC0_CFG_KERNEL_TENSOR_5_DIM_1_STRIDE_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_5_DIM_2_SIZE */
+#define TPC0_CFG_KERNEL_TENSOR_5_DIM_2_SIZE_V_SHIFT 0
+#define TPC0_CFG_KERNEL_TENSOR_5_DIM_2_SIZE_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_5_DIM_2_STRIDE */
+#define TPC0_CFG_KERNEL_TENSOR_5_DIM_2_STRIDE_V_SHIFT 0
+#define TPC0_CFG_KERNEL_TENSOR_5_DIM_2_STRIDE_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_5_DIM_3_SIZE */
+#define TPC0_CFG_KERNEL_TENSOR_5_DIM_3_SIZE_V_SHIFT 0
+#define TPC0_CFG_KERNEL_TENSOR_5_DIM_3_SIZE_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_5_DIM_3_STRIDE */
+#define TPC0_CFG_KERNEL_TENSOR_5_DIM_3_STRIDE_V_SHIFT 0
+#define TPC0_CFG_KERNEL_TENSOR_5_DIM_3_STRIDE_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_5_DIM_4_SIZE */
+#define TPC0_CFG_KERNEL_TENSOR_5_DIM_4_SIZE_V_SHIFT 0
+#define TPC0_CFG_KERNEL_TENSOR_5_DIM_4_SIZE_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_5_DIM_4_STRIDE */
+#define TPC0_CFG_KERNEL_TENSOR_5_DIM_4_STRIDE_V_SHIFT 0
+#define TPC0_CFG_KERNEL_TENSOR_5_DIM_4_STRIDE_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_6_BASE_ADDR_LOW */
+#define TPC0_CFG_KERNEL_TENSOR_6_BASE_ADDR_LOW_V_SHIFT 0
+#define TPC0_CFG_KERNEL_TENSOR_6_BASE_ADDR_LOW_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_6_BASE_ADDR_HIGH */
+#define TPC0_CFG_KERNEL_TENSOR_6_BASE_ADDR_HIGH_V_SHIFT 0
+#define TPC0_CFG_KERNEL_TENSOR_6_BASE_ADDR_HIGH_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_6_PADDING_VALUE */
+#define TPC0_CFG_KERNEL_TENSOR_6_PADDING_VALUE_V_SHIFT 0
+#define TPC0_CFG_KERNEL_TENSOR_6_PADDING_VALUE_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_6_TENSOR_CONFIG */
+#define TPC0_CFG_KERNEL_TENSOR_6_TENSOR_CONFIG_DATA_TYPE_SHIFT 0
+#define TPC0_CFG_KERNEL_TENSOR_6_TENSOR_CONFIG_DATA_TYPE_MASK 0x7
+#define TPC0_CFG_KERNEL_TENSOR_6_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT 8
+#define TPC0_CFG_KERNEL_TENSOR_6_TENSOR_CONFIG_VALID_DIM_MASK_MASK 0x1F00
+#define TPC0_CFG_KERNEL_TENSOR_6_TENSOR_CONFIG_LAST_DIM_SHIFT 16
+#define TPC0_CFG_KERNEL_TENSOR_6_TENSOR_CONFIG_LAST_DIM_MASK 0x70000
+#define TPC0_CFG_KERNEL_TENSOR_6_TENSOR_CONFIG_RMW_SET_SHIFT 19
+#define TPC0_CFG_KERNEL_TENSOR_6_TENSOR_CONFIG_RMW_SET_MASK 0x80000
+#define TPC0_CFG_KERNEL_TENSOR_6_TENSOR_CONFIG_RMW_RESERV_SHIFT 20
+#define TPC0_CFG_KERNEL_TENSOR_6_TENSOR_CONFIG_RMW_RESERV_MASK 0x100000
+#define TPC0_CFG_KERNEL_TENSOR_6_TENSOR_CONFIG_RMW_OP_SHIFT 21
+#define TPC0_CFG_KERNEL_TENSOR_6_TENSOR_CONFIG_RMW_OP_MASK 0x600000
+
+/* TPC0_CFG_KERNEL_TENSOR_6_DIM_0_SIZE */
+#define TPC0_CFG_KERNEL_TENSOR_6_DIM_0_SIZE_V_SHIFT 0
+#define TPC0_CFG_KERNEL_TENSOR_6_DIM_0_SIZE_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_6_DIM_0_STRIDE */
+#define TPC0_CFG_KERNEL_TENSOR_6_DIM_0_STRIDE_V_SHIFT 0
+#define TPC0_CFG_KERNEL_TENSOR_6_DIM_0_STRIDE_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_6_DIM_1_SIZE */
+#define TPC0_CFG_KERNEL_TENSOR_6_DIM_1_SIZE_V_SHIFT 0
+#define TPC0_CFG_KERNEL_TENSOR_6_DIM_1_SIZE_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_6_DIM_1_STRIDE */
+#define TPC0_CFG_KERNEL_TENSOR_6_DIM_1_STRIDE_V_SHIFT 0
+#define TPC0_CFG_KERNEL_TENSOR_6_DIM_1_STRIDE_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_6_DIM_2_SIZE */
+#define TPC0_CFG_KERNEL_TENSOR_6_DIM_2_SIZE_V_SHIFT 0
+#define TPC0_CFG_KERNEL_TENSOR_6_DIM_2_SIZE_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_6_DIM_2_STRIDE */
+#define TPC0_CFG_KERNEL_TENSOR_6_DIM_2_STRIDE_V_SHIFT 0
+#define TPC0_CFG_KERNEL_TENSOR_6_DIM_2_STRIDE_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_6_DIM_3_SIZE */
+#define TPC0_CFG_KERNEL_TENSOR_6_DIM_3_SIZE_V_SHIFT 0
+#define TPC0_CFG_KERNEL_TENSOR_6_DIM_3_SIZE_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_6_DIM_3_STRIDE */
+#define TPC0_CFG_KERNEL_TENSOR_6_DIM_3_STRIDE_V_SHIFT 0
+#define TPC0_CFG_KERNEL_TENSOR_6_DIM_3_STRIDE_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_6_DIM_4_SIZE */
+#define TPC0_CFG_KERNEL_TENSOR_6_DIM_4_SIZE_V_SHIFT 0
+#define TPC0_CFG_KERNEL_TENSOR_6_DIM_4_SIZE_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_6_DIM_4_STRIDE */
+#define TPC0_CFG_KERNEL_TENSOR_6_DIM_4_STRIDE_V_SHIFT 0
+#define TPC0_CFG_KERNEL_TENSOR_6_DIM_4_STRIDE_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_7_BASE_ADDR_LOW */
+#define TPC0_CFG_KERNEL_TENSOR_7_BASE_ADDR_LOW_V_SHIFT 0
+#define TPC0_CFG_KERNEL_TENSOR_7_BASE_ADDR_LOW_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_7_BASE_ADDR_HIGH */
+#define TPC0_CFG_KERNEL_TENSOR_7_BASE_ADDR_HIGH_V_SHIFT 0
+#define TPC0_CFG_KERNEL_TENSOR_7_BASE_ADDR_HIGH_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_7_PADDING_VALUE */
+#define TPC0_CFG_KERNEL_TENSOR_7_PADDING_VALUE_V_SHIFT 0
+#define TPC0_CFG_KERNEL_TENSOR_7_PADDING_VALUE_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_7_TENSOR_CONFIG */
+#define TPC0_CFG_KERNEL_TENSOR_7_TENSOR_CONFIG_DATA_TYPE_SHIFT 0
+#define TPC0_CFG_KERNEL_TENSOR_7_TENSOR_CONFIG_DATA_TYPE_MASK 0x7
+#define TPC0_CFG_KERNEL_TENSOR_7_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT 8
+#define TPC0_CFG_KERNEL_TENSOR_7_TENSOR_CONFIG_VALID_DIM_MASK_MASK 0x1F00
+#define TPC0_CFG_KERNEL_TENSOR_7_TENSOR_CONFIG_LAST_DIM_SHIFT 16
+#define TPC0_CFG_KERNEL_TENSOR_7_TENSOR_CONFIG_LAST_DIM_MASK 0x70000
+#define TPC0_CFG_KERNEL_TENSOR_7_TENSOR_CONFIG_RMW_SET_SHIFT 19
+#define TPC0_CFG_KERNEL_TENSOR_7_TENSOR_CONFIG_RMW_SET_MASK 0x80000
+#define TPC0_CFG_KERNEL_TENSOR_7_TENSOR_CONFIG_RMW_RESERV_SHIFT 20
+#define TPC0_CFG_KERNEL_TENSOR_7_TENSOR_CONFIG_RMW_RESERV_MASK 0x100000
+#define TPC0_CFG_KERNEL_TENSOR_7_TENSOR_CONFIG_RMW_OP_SHIFT 21
+#define TPC0_CFG_KERNEL_TENSOR_7_TENSOR_CONFIG_RMW_OP_MASK 0x600000
+
+/* TPC0_CFG_KERNEL_TENSOR_7_DIM_0_SIZE */
+#define TPC0_CFG_KERNEL_TENSOR_7_DIM_0_SIZE_V_SHIFT 0
+#define TPC0_CFG_KERNEL_TENSOR_7_DIM_0_SIZE_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_7_DIM_0_STRIDE */
+#define TPC0_CFG_KERNEL_TENSOR_7_DIM_0_STRIDE_V_SHIFT 0
+#define TPC0_CFG_KERNEL_TENSOR_7_DIM_0_STRIDE_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_7_DIM_1_SIZE */
+#define TPC0_CFG_KERNEL_TENSOR_7_DIM_1_SIZE_V_SHIFT 0
+#define TPC0_CFG_KERNEL_TENSOR_7_DIM_1_SIZE_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_7_DIM_1_STRIDE */
+#define TPC0_CFG_KERNEL_TENSOR_7_DIM_1_STRIDE_V_SHIFT 0
+#define TPC0_CFG_KERNEL_TENSOR_7_DIM_1_STRIDE_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_7_DIM_2_SIZE */
+#define TPC0_CFG_KERNEL_TENSOR_7_DIM_2_SIZE_V_SHIFT 0
+#define TPC0_CFG_KERNEL_TENSOR_7_DIM_2_SIZE_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_7_DIM_2_STRIDE */
+#define TPC0_CFG_KERNEL_TENSOR_7_DIM_2_STRIDE_V_SHIFT 0
+#define TPC0_CFG_KERNEL_TENSOR_7_DIM_2_STRIDE_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_7_DIM_3_SIZE */
+#define TPC0_CFG_KERNEL_TENSOR_7_DIM_3_SIZE_V_SHIFT 0
+#define TPC0_CFG_KERNEL_TENSOR_7_DIM_3_SIZE_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_7_DIM_3_STRIDE */
+#define TPC0_CFG_KERNEL_TENSOR_7_DIM_3_STRIDE_V_SHIFT 0
+#define TPC0_CFG_KERNEL_TENSOR_7_DIM_3_STRIDE_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_7_DIM_4_SIZE */
+#define TPC0_CFG_KERNEL_TENSOR_7_DIM_4_SIZE_V_SHIFT 0
+#define TPC0_CFG_KERNEL_TENSOR_7_DIM_4_SIZE_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_7_DIM_4_STRIDE */
+#define TPC0_CFG_KERNEL_TENSOR_7_DIM_4_STRIDE_V_SHIFT 0
+#define TPC0_CFG_KERNEL_TENSOR_7_DIM_4_STRIDE_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_8_BASE_ADDR_LOW */
+#define TPC0_CFG_KERNEL_TENSOR_8_BASE_ADDR_LOW_V_SHIFT 0
+#define TPC0_CFG_KERNEL_TENSOR_8_BASE_ADDR_LOW_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_8_BASE_ADDR_HIGH */
+#define TPC0_CFG_KERNEL_TENSOR_8_BASE_ADDR_HIGH_V_SHIFT 0
+#define TPC0_CFG_KERNEL_TENSOR_8_BASE_ADDR_HIGH_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_8_PADDING_VALUE */
+#define TPC0_CFG_KERNEL_TENSOR_8_PADDING_VALUE_V_SHIFT 0
+#define TPC0_CFG_KERNEL_TENSOR_8_PADDING_VALUE_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_8_TENSOR_CONFIG */
+#define TPC0_CFG_KERNEL_TENSOR_8_TENSOR_CONFIG_DATA_TYPE_SHIFT 0
+#define TPC0_CFG_KERNEL_TENSOR_8_TENSOR_CONFIG_DATA_TYPE_MASK 0x7
+#define TPC0_CFG_KERNEL_TENSOR_8_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT 8
+#define TPC0_CFG_KERNEL_TENSOR_8_TENSOR_CONFIG_VALID_DIM_MASK_MASK 0x1F00
+#define TPC0_CFG_KERNEL_TENSOR_8_TENSOR_CONFIG_LAST_DIM_SHIFT 16
+#define TPC0_CFG_KERNEL_TENSOR_8_TENSOR_CONFIG_LAST_DIM_MASK 0x70000
+#define TPC0_CFG_KERNEL_TENSOR_8_TENSOR_CONFIG_RMW_SET_SHIFT 19
+#define TPC0_CFG_KERNEL_TENSOR_8_TENSOR_CONFIG_RMW_SET_MASK 0x80000
+#define TPC0_CFG_KERNEL_TENSOR_8_TENSOR_CONFIG_RMW_RESERV_SHIFT 20
+#define TPC0_CFG_KERNEL_TENSOR_8_TENSOR_CONFIG_RMW_RESERV_MASK 0x100000
+#define TPC0_CFG_KERNEL_TENSOR_8_TENSOR_CONFIG_RMW_OP_SHIFT 21
+#define TPC0_CFG_KERNEL_TENSOR_8_TENSOR_CONFIG_RMW_OP_MASK 0x600000
+
+/* TPC0_CFG_KERNEL_TENSOR_8_DIM_0_SIZE */
+#define TPC0_CFG_KERNEL_TENSOR_8_DIM_0_SIZE_V_SHIFT 0
+#define TPC0_CFG_KERNEL_TENSOR_8_DIM_0_SIZE_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_8_DIM_0_STRIDE */
+#define TPC0_CFG_KERNEL_TENSOR_8_DIM_0_STRIDE_V_SHIFT 0
+#define TPC0_CFG_KERNEL_TENSOR_8_DIM_0_STRIDE_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_8_DIM_1_SIZE */
+#define TPC0_CFG_KERNEL_TENSOR_8_DIM_1_SIZE_V_SHIFT 0
+#define TPC0_CFG_KERNEL_TENSOR_8_DIM_1_SIZE_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_8_DIM_1_STRIDE */
+#define TPC0_CFG_KERNEL_TENSOR_8_DIM_1_STRIDE_V_SHIFT 0
+#define TPC0_CFG_KERNEL_TENSOR_8_DIM_1_STRIDE_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_8_DIM_2_SIZE */
+#define TPC0_CFG_KERNEL_TENSOR_8_DIM_2_SIZE_V_SHIFT 0
+#define TPC0_CFG_KERNEL_TENSOR_8_DIM_2_SIZE_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_8_DIM_2_STRIDE */
+#define TPC0_CFG_KERNEL_TENSOR_8_DIM_2_STRIDE_V_SHIFT 0
+#define TPC0_CFG_KERNEL_TENSOR_8_DIM_2_STRIDE_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_8_DIM_3_SIZE */
+#define TPC0_CFG_KERNEL_TENSOR_8_DIM_3_SIZE_V_SHIFT 0
+#define TPC0_CFG_KERNEL_TENSOR_8_DIM_3_SIZE_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_8_DIM_3_STRIDE */
+#define TPC0_CFG_KERNEL_TENSOR_8_DIM_3_STRIDE_V_SHIFT 0
+#define TPC0_CFG_KERNEL_TENSOR_8_DIM_3_STRIDE_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_8_DIM_4_SIZE */
+#define TPC0_CFG_KERNEL_TENSOR_8_DIM_4_SIZE_V_SHIFT 0
+#define TPC0_CFG_KERNEL_TENSOR_8_DIM_4_SIZE_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_8_DIM_4_STRIDE */
+#define TPC0_CFG_KERNEL_TENSOR_8_DIM_4_STRIDE_V_SHIFT 0
+#define TPC0_CFG_KERNEL_TENSOR_8_DIM_4_STRIDE_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_9_BASE_ADDR_LOW */
+#define TPC0_CFG_KERNEL_TENSOR_9_BASE_ADDR_LOW_V_SHIFT 0
+#define TPC0_CFG_KERNEL_TENSOR_9_BASE_ADDR_LOW_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_9_BASE_ADDR_HIGH */
+#define TPC0_CFG_KERNEL_TENSOR_9_BASE_ADDR_HIGH_V_SHIFT 0
+#define TPC0_CFG_KERNEL_TENSOR_9_BASE_ADDR_HIGH_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_9_PADDING_VALUE */
+#define TPC0_CFG_KERNEL_TENSOR_9_PADDING_VALUE_V_SHIFT 0
+#define TPC0_CFG_KERNEL_TENSOR_9_PADDING_VALUE_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_9_TENSOR_CONFIG */
+#define TPC0_CFG_KERNEL_TENSOR_9_TENSOR_CONFIG_DATA_TYPE_SHIFT 0
+#define TPC0_CFG_KERNEL_TENSOR_9_TENSOR_CONFIG_DATA_TYPE_MASK 0x7
+#define TPC0_CFG_KERNEL_TENSOR_9_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT 8
+#define TPC0_CFG_KERNEL_TENSOR_9_TENSOR_CONFIG_VALID_DIM_MASK_MASK 0x1F00
+#define TPC0_CFG_KERNEL_TENSOR_9_TENSOR_CONFIG_LAST_DIM_SHIFT 16
+#define TPC0_CFG_KERNEL_TENSOR_9_TENSOR_CONFIG_LAST_DIM_MASK 0x70000
+#define TPC0_CFG_KERNEL_TENSOR_9_TENSOR_CONFIG_RMW_SET_SHIFT 19
+#define TPC0_CFG_KERNEL_TENSOR_9_TENSOR_CONFIG_RMW_SET_MASK 0x80000
+#define TPC0_CFG_KERNEL_TENSOR_9_TENSOR_CONFIG_RMW_RESERV_SHIFT 20
+#define TPC0_CFG_KERNEL_TENSOR_9_TENSOR_CONFIG_RMW_RESERV_MASK 0x100000
+#define TPC0_CFG_KERNEL_TENSOR_9_TENSOR_CONFIG_RMW_OP_SHIFT 21
+#define TPC0_CFG_KERNEL_TENSOR_9_TENSOR_CONFIG_RMW_OP_MASK 0x600000
+
+/* TPC0_CFG_KERNEL_TENSOR_9_DIM_0_SIZE */
+#define TPC0_CFG_KERNEL_TENSOR_9_DIM_0_SIZE_V_SHIFT 0
+#define TPC0_CFG_KERNEL_TENSOR_9_DIM_0_SIZE_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_9_DIM_0_STRIDE */
+#define TPC0_CFG_KERNEL_TENSOR_9_DIM_0_STRIDE_V_SHIFT 0
+#define TPC0_CFG_KERNEL_TENSOR_9_DIM_0_STRIDE_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_9_DIM_1_SIZE */
+#define TPC0_CFG_KERNEL_TENSOR_9_DIM_1_SIZE_V_SHIFT 0
+#define TPC0_CFG_KERNEL_TENSOR_9_DIM_1_SIZE_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_9_DIM_1_STRIDE */
+#define TPC0_CFG_KERNEL_TENSOR_9_DIM_1_STRIDE_V_SHIFT 0
+#define TPC0_CFG_KERNEL_TENSOR_9_DIM_1_STRIDE_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_9_DIM_2_SIZE */
+#define TPC0_CFG_KERNEL_TENSOR_9_DIM_2_SIZE_V_SHIFT 0
+#define TPC0_CFG_KERNEL_TENSOR_9_DIM_2_SIZE_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_9_DIM_2_STRIDE */
+#define TPC0_CFG_KERNEL_TENSOR_9_DIM_2_STRIDE_V_SHIFT 0
+#define TPC0_CFG_KERNEL_TENSOR_9_DIM_2_STRIDE_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_9_DIM_3_SIZE */
+#define TPC0_CFG_KERNEL_TENSOR_9_DIM_3_SIZE_V_SHIFT 0
+#define TPC0_CFG_KERNEL_TENSOR_9_DIM_3_SIZE_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_9_DIM_3_STRIDE */
+#define TPC0_CFG_KERNEL_TENSOR_9_DIM_3_STRIDE_V_SHIFT 0
+#define TPC0_CFG_KERNEL_TENSOR_9_DIM_3_STRIDE_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_9_DIM_4_SIZE */
+#define TPC0_CFG_KERNEL_TENSOR_9_DIM_4_SIZE_V_SHIFT 0
+#define TPC0_CFG_KERNEL_TENSOR_9_DIM_4_SIZE_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_9_DIM_4_STRIDE */
+#define TPC0_CFG_KERNEL_TENSOR_9_DIM_4_STRIDE_V_SHIFT 0
+#define TPC0_CFG_KERNEL_TENSOR_9_DIM_4_STRIDE_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_10_BASE_ADDR_LOW */
+#define TPC0_CFG_KERNEL_TENSOR_10_BASE_ADDR_LOW_V_SHIFT 0
+#define TPC0_CFG_KERNEL_TENSOR_10_BASE_ADDR_LOW_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_10_BASE_ADDR_HIGH */
+#define TPC0_CFG_KERNEL_TENSOR_10_BASE_ADDR_HIGH_V_SHIFT 0
+#define TPC0_CFG_KERNEL_TENSOR_10_BASE_ADDR_HIGH_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_10_PADDING_VALUE */
+#define TPC0_CFG_KERNEL_TENSOR_10_PADDING_VALUE_V_SHIFT 0
+#define TPC0_CFG_KERNEL_TENSOR_10_PADDING_VALUE_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_10_TENSOR_CONFIG */
+#define TPC0_CFG_KERNEL_TENSOR_10_TENSOR_CONFIG_DATA_TYPE_SHIFT 0
+#define TPC0_CFG_KERNEL_TENSOR_10_TENSOR_CONFIG_DATA_TYPE_MASK 0x7
+#define TPC0_CFG_KERNEL_TENSOR_10_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT 8
+#define TPC0_CFG_KERNEL_TENSOR_10_TENSOR_CONFIG_VALID_DIM_MASK_MASK 0x1F00
+#define TPC0_CFG_KERNEL_TENSOR_10_TENSOR_CONFIG_LAST_DIM_SHIFT 16
+#define TPC0_CFG_KERNEL_TENSOR_10_TENSOR_CONFIG_LAST_DIM_MASK 0x70000
+#define TPC0_CFG_KERNEL_TENSOR_10_TENSOR_CONFIG_RMW_SET_SHIFT 19
+#define TPC0_CFG_KERNEL_TENSOR_10_TENSOR_CONFIG_RMW_SET_MASK 0x80000
+#define TPC0_CFG_KERNEL_TENSOR_10_TENSOR_CONFIG_RMW_RESERV_SHIFT 20
+#define TPC0_CFG_KERNEL_TENSOR_10_TENSOR_CONFIG_RMW_RESERV_MASK 0x100000
+#define TPC0_CFG_KERNEL_TENSOR_10_TENSOR_CONFIG_RMW_OP_SHIFT 21
+#define TPC0_CFG_KERNEL_TENSOR_10_TENSOR_CONFIG_RMW_OP_MASK 0x600000
+
+/* TPC0_CFG_KERNEL_TENSOR_10_DIM_0_SIZE */
+#define TPC0_CFG_KERNEL_TENSOR_10_DIM_0_SIZE_V_SHIFT 0
+#define TPC0_CFG_KERNEL_TENSOR_10_DIM_0_SIZE_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_10_DIM_0_STRIDE */
+#define TPC0_CFG_KERNEL_TENSOR_10_DIM_0_STRIDE_V_SHIFT 0
+#define TPC0_CFG_KERNEL_TENSOR_10_DIM_0_STRIDE_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_10_DIM_1_SIZE */
+#define TPC0_CFG_KERNEL_TENSOR_10_DIM_1_SIZE_V_SHIFT 0
+#define TPC0_CFG_KERNEL_TENSOR_10_DIM_1_SIZE_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_10_DIM_1_STRIDE */
+#define TPC0_CFG_KERNEL_TENSOR_10_DIM_1_STRIDE_V_SHIFT 0
+#define TPC0_CFG_KERNEL_TENSOR_10_DIM_1_STRIDE_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_10_DIM_2_SIZE */
+#define TPC0_CFG_KERNEL_TENSOR_10_DIM_2_SIZE_V_SHIFT 0
+#define TPC0_CFG_KERNEL_TENSOR_10_DIM_2_SIZE_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_10_DIM_2_STRIDE */
+#define TPC0_CFG_KERNEL_TENSOR_10_DIM_2_STRIDE_V_SHIFT 0
+#define TPC0_CFG_KERNEL_TENSOR_10_DIM_2_STRIDE_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_10_DIM_3_SIZE */
+#define TPC0_CFG_KERNEL_TENSOR_10_DIM_3_SIZE_V_SHIFT 0
+#define TPC0_CFG_KERNEL_TENSOR_10_DIM_3_SIZE_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_10_DIM_3_STRIDE */
+#define TPC0_CFG_KERNEL_TENSOR_10_DIM_3_STRIDE_V_SHIFT 0
+#define TPC0_CFG_KERNEL_TENSOR_10_DIM_3_STRIDE_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_10_DIM_4_SIZE */
+#define TPC0_CFG_KERNEL_TENSOR_10_DIM_4_SIZE_V_SHIFT 0
+#define TPC0_CFG_KERNEL_TENSOR_10_DIM_4_SIZE_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_10_DIM_4_STRIDE */
+#define TPC0_CFG_KERNEL_TENSOR_10_DIM_4_STRIDE_V_SHIFT 0
+#define TPC0_CFG_KERNEL_TENSOR_10_DIM_4_STRIDE_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_11_BASE_ADDR_LOW */
+#define TPC0_CFG_KERNEL_TENSOR_11_BASE_ADDR_LOW_V_SHIFT 0
+#define TPC0_CFG_KERNEL_TENSOR_11_BASE_ADDR_LOW_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_11_BASE_ADDR_HIGH */
+#define TPC0_CFG_KERNEL_TENSOR_11_BASE_ADDR_HIGH_V_SHIFT 0
+#define TPC0_CFG_KERNEL_TENSOR_11_BASE_ADDR_HIGH_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_11_PADDING_VALUE */
+#define TPC0_CFG_KERNEL_TENSOR_11_PADDING_VALUE_V_SHIFT 0
+#define TPC0_CFG_KERNEL_TENSOR_11_PADDING_VALUE_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_11_TENSOR_CONFIG */
+#define TPC0_CFG_KERNEL_TENSOR_11_TENSOR_CONFIG_DATA_TYPE_SHIFT 0
+#define TPC0_CFG_KERNEL_TENSOR_11_TENSOR_CONFIG_DATA_TYPE_MASK 0x7
+#define TPC0_CFG_KERNEL_TENSOR_11_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT 8
+#define TPC0_CFG_KERNEL_TENSOR_11_TENSOR_CONFIG_VALID_DIM_MASK_MASK 0x1F00
+#define TPC0_CFG_KERNEL_TENSOR_11_TENSOR_CONFIG_LAST_DIM_SHIFT 16
+#define TPC0_CFG_KERNEL_TENSOR_11_TENSOR_CONFIG_LAST_DIM_MASK 0x70000
+#define TPC0_CFG_KERNEL_TENSOR_11_TENSOR_CONFIG_RMW_SET_SHIFT 19
+#define TPC0_CFG_KERNEL_TENSOR_11_TENSOR_CONFIG_RMW_SET_MASK 0x80000
+#define TPC0_CFG_KERNEL_TENSOR_11_TENSOR_CONFIG_RMW_RESERV_SHIFT 20
+#define TPC0_CFG_KERNEL_TENSOR_11_TENSOR_CONFIG_RMW_RESERV_MASK 0x100000
+#define TPC0_CFG_KERNEL_TENSOR_11_TENSOR_CONFIG_RMW_OP_SHIFT 21
+#define TPC0_CFG_KERNEL_TENSOR_11_TENSOR_CONFIG_RMW_OP_MASK 0x600000
+
+/* TPC0_CFG_KERNEL_TENSOR_11_DIM_0_SIZE */
+#define TPC0_CFG_KERNEL_TENSOR_11_DIM_0_SIZE_V_SHIFT 0
+#define TPC0_CFG_KERNEL_TENSOR_11_DIM_0_SIZE_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_11_DIM_0_STRIDE */
+#define TPC0_CFG_KERNEL_TENSOR_11_DIM_0_STRIDE_V_SHIFT 0
+#define TPC0_CFG_KERNEL_TENSOR_11_DIM_0_STRIDE_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_11_DIM_1_SIZE */
+#define TPC0_CFG_KERNEL_TENSOR_11_DIM_1_SIZE_V_SHIFT 0
+#define TPC0_CFG_KERNEL_TENSOR_11_DIM_1_SIZE_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_11_DIM_1_STRIDE */
+#define TPC0_CFG_KERNEL_TENSOR_11_DIM_1_STRIDE_V_SHIFT 0
+#define TPC0_CFG_KERNEL_TENSOR_11_DIM_1_STRIDE_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_11_DIM_2_SIZE */
+#define TPC0_CFG_KERNEL_TENSOR_11_DIM_2_SIZE_V_SHIFT 0
+#define TPC0_CFG_KERNEL_TENSOR_11_DIM_2_SIZE_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_11_DIM_2_STRIDE */
+#define TPC0_CFG_KERNEL_TENSOR_11_DIM_2_STRIDE_V_SHIFT 0
+#define TPC0_CFG_KERNEL_TENSOR_11_DIM_2_STRIDE_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_11_DIM_3_SIZE */
+#define TPC0_CFG_KERNEL_TENSOR_11_DIM_3_SIZE_V_SHIFT 0
+#define TPC0_CFG_KERNEL_TENSOR_11_DIM_3_SIZE_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_11_DIM_3_STRIDE */
+#define TPC0_CFG_KERNEL_TENSOR_11_DIM_3_STRIDE_V_SHIFT 0
+#define TPC0_CFG_KERNEL_TENSOR_11_DIM_3_STRIDE_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_11_DIM_4_SIZE */
+#define TPC0_CFG_KERNEL_TENSOR_11_DIM_4_SIZE_V_SHIFT 0
+#define TPC0_CFG_KERNEL_TENSOR_11_DIM_4_SIZE_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_11_DIM_4_STRIDE */
+#define TPC0_CFG_KERNEL_TENSOR_11_DIM_4_STRIDE_V_SHIFT 0
+#define TPC0_CFG_KERNEL_TENSOR_11_DIM_4_STRIDE_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_12_BASE_ADDR_LOW */
+#define TPC0_CFG_KERNEL_TENSOR_12_BASE_ADDR_LOW_V_SHIFT 0
+#define TPC0_CFG_KERNEL_TENSOR_12_BASE_ADDR_LOW_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_12_BASE_ADDR_HIGH */
+#define TPC0_CFG_KERNEL_TENSOR_12_BASE_ADDR_HIGH_V_SHIFT 0
+#define TPC0_CFG_KERNEL_TENSOR_12_BASE_ADDR_HIGH_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_12_PADDING_VALUE */
+#define TPC0_CFG_KERNEL_TENSOR_12_PADDING_VALUE_V_SHIFT 0
+#define TPC0_CFG_KERNEL_TENSOR_12_PADDING_VALUE_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_12_TENSOR_CONFIG */
+#define TPC0_CFG_KERNEL_TENSOR_12_TENSOR_CONFIG_DATA_TYPE_SHIFT 0
+#define TPC0_CFG_KERNEL_TENSOR_12_TENSOR_CONFIG_DATA_TYPE_MASK 0x7
+#define TPC0_CFG_KERNEL_TENSOR_12_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT 8
+#define TPC0_CFG_KERNEL_TENSOR_12_TENSOR_CONFIG_VALID_DIM_MASK_MASK 0x1F00
+#define TPC0_CFG_KERNEL_TENSOR_12_TENSOR_CONFIG_LAST_DIM_SHIFT 16
+#define TPC0_CFG_KERNEL_TENSOR_12_TENSOR_CONFIG_LAST_DIM_MASK 0x70000
+#define TPC0_CFG_KERNEL_TENSOR_12_TENSOR_CONFIG_RMW_SET_SHIFT 19
+#define TPC0_CFG_KERNEL_TENSOR_12_TENSOR_CONFIG_RMW_SET_MASK 0x80000
+#define TPC0_CFG_KERNEL_TENSOR_12_TENSOR_CONFIG_RMW_RESERV_SHIFT 20
+#define TPC0_CFG_KERNEL_TENSOR_12_TENSOR_CONFIG_RMW_RESERV_MASK 0x100000
+#define TPC0_CFG_KERNEL_TENSOR_12_TENSOR_CONFIG_RMW_OP_SHIFT 21
+#define TPC0_CFG_KERNEL_TENSOR_12_TENSOR_CONFIG_RMW_OP_MASK 0x600000
+
+/* TPC0_CFG_KERNEL_TENSOR_12_DIM_0_SIZE */
+#define TPC0_CFG_KERNEL_TENSOR_12_DIM_0_SIZE_V_SHIFT 0
+#define TPC0_CFG_KERNEL_TENSOR_12_DIM_0_SIZE_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_12_DIM_0_STRIDE */
+#define TPC0_CFG_KERNEL_TENSOR_12_DIM_0_STRIDE_V_SHIFT 0
+#define TPC0_CFG_KERNEL_TENSOR_12_DIM_0_STRIDE_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_12_DIM_1_SIZE */
+#define TPC0_CFG_KERNEL_TENSOR_12_DIM_1_SIZE_V_SHIFT 0
+#define TPC0_CFG_KERNEL_TENSOR_12_DIM_1_SIZE_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_12_DIM_1_STRIDE */
+#define TPC0_CFG_KERNEL_TENSOR_12_DIM_1_STRIDE_V_SHIFT 0
+#define TPC0_CFG_KERNEL_TENSOR_12_DIM_1_STRIDE_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_12_DIM_2_SIZE */
+#define TPC0_CFG_KERNEL_TENSOR_12_DIM_2_SIZE_V_SHIFT 0
+#define TPC0_CFG_KERNEL_TENSOR_12_DIM_2_SIZE_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_12_DIM_2_STRIDE */
+#define TPC0_CFG_KERNEL_TENSOR_12_DIM_2_STRIDE_V_SHIFT 0
+#define TPC0_CFG_KERNEL_TENSOR_12_DIM_2_STRIDE_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_12_DIM_3_SIZE */
+#define TPC0_CFG_KERNEL_TENSOR_12_DIM_3_SIZE_V_SHIFT 0
+#define TPC0_CFG_KERNEL_TENSOR_12_DIM_3_SIZE_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_12_DIM_3_STRIDE */
+#define TPC0_CFG_KERNEL_TENSOR_12_DIM_3_STRIDE_V_SHIFT 0
+#define TPC0_CFG_KERNEL_TENSOR_12_DIM_3_STRIDE_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_12_DIM_4_SIZE */
+#define TPC0_CFG_KERNEL_TENSOR_12_DIM_4_SIZE_V_SHIFT 0
+#define TPC0_CFG_KERNEL_TENSOR_12_DIM_4_SIZE_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_12_DIM_4_STRIDE */
+#define TPC0_CFG_KERNEL_TENSOR_12_DIM_4_STRIDE_V_SHIFT 0
+#define TPC0_CFG_KERNEL_TENSOR_12_DIM_4_STRIDE_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_13_BASE_ADDR_LOW */
+#define TPC0_CFG_KERNEL_TENSOR_13_BASE_ADDR_LOW_V_SHIFT 0
+#define TPC0_CFG_KERNEL_TENSOR_13_BASE_ADDR_LOW_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_13_BASE_ADDR_HIGH */
+#define TPC0_CFG_KERNEL_TENSOR_13_BASE_ADDR_HIGH_V_SHIFT 0
+#define TPC0_CFG_KERNEL_TENSOR_13_BASE_ADDR_HIGH_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_13_PADDING_VALUE */
+#define TPC0_CFG_KERNEL_TENSOR_13_PADDING_VALUE_V_SHIFT 0
+#define TPC0_CFG_KERNEL_TENSOR_13_PADDING_VALUE_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_13_TENSOR_CONFIG */
+#define TPC0_CFG_KERNEL_TENSOR_13_TENSOR_CONFIG_DATA_TYPE_SHIFT 0
+#define TPC0_CFG_KERNEL_TENSOR_13_TENSOR_CONFIG_DATA_TYPE_MASK 0x7
+#define TPC0_CFG_KERNEL_TENSOR_13_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT 8
+#define TPC0_CFG_KERNEL_TENSOR_13_TENSOR_CONFIG_VALID_DIM_MASK_MASK 0x1F00
+#define TPC0_CFG_KERNEL_TENSOR_13_TENSOR_CONFIG_LAST_DIM_SHIFT 16
+#define TPC0_CFG_KERNEL_TENSOR_13_TENSOR_CONFIG_LAST_DIM_MASK 0x70000
+#define TPC0_CFG_KERNEL_TENSOR_13_TENSOR_CONFIG_RMW_SET_SHIFT 19
+#define TPC0_CFG_KERNEL_TENSOR_13_TENSOR_CONFIG_RMW_SET_MASK 0x80000
+#define TPC0_CFG_KERNEL_TENSOR_13_TENSOR_CONFIG_RMW_RESERV_SHIFT 20
+#define TPC0_CFG_KERNEL_TENSOR_13_TENSOR_CONFIG_RMW_RESERV_MASK 0x100000
+#define TPC0_CFG_KERNEL_TENSOR_13_TENSOR_CONFIG_RMW_OP_SHIFT 21
+#define TPC0_CFG_KERNEL_TENSOR_13_TENSOR_CONFIG_RMW_OP_MASK 0x600000
+
+/* TPC0_CFG_KERNEL_TENSOR_13_DIM_0_SIZE */
+#define TPC0_CFG_KERNEL_TENSOR_13_DIM_0_SIZE_V_SHIFT 0
+#define TPC0_CFG_KERNEL_TENSOR_13_DIM_0_SIZE_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_13_DIM_0_STRIDE */
+#define TPC0_CFG_KERNEL_TENSOR_13_DIM_0_STRIDE_V_SHIFT 0
+#define TPC0_CFG_KERNEL_TENSOR_13_DIM_0_STRIDE_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_13_DIM_1_SIZE */
+#define TPC0_CFG_KERNEL_TENSOR_13_DIM_1_SIZE_V_SHIFT 0
+#define TPC0_CFG_KERNEL_TENSOR_13_DIM_1_SIZE_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_13_DIM_1_STRIDE */
+#define TPC0_CFG_KERNEL_TENSOR_13_DIM_1_STRIDE_V_SHIFT 0
+#define TPC0_CFG_KERNEL_TENSOR_13_DIM_1_STRIDE_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_13_DIM_2_SIZE */
+#define TPC0_CFG_KERNEL_TENSOR_13_DIM_2_SIZE_V_SHIFT 0
+#define TPC0_CFG_KERNEL_TENSOR_13_DIM_2_SIZE_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_13_DIM_2_STRIDE */
+#define TPC0_CFG_KERNEL_TENSOR_13_DIM_2_STRIDE_V_SHIFT 0
+#define TPC0_CFG_KERNEL_TENSOR_13_DIM_2_STRIDE_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_13_DIM_3_SIZE */
+#define TPC0_CFG_KERNEL_TENSOR_13_DIM_3_SIZE_V_SHIFT 0
+#define TPC0_CFG_KERNEL_TENSOR_13_DIM_3_SIZE_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_13_DIM_3_STRIDE */
+#define TPC0_CFG_KERNEL_TENSOR_13_DIM_3_STRIDE_V_SHIFT 0
+#define TPC0_CFG_KERNEL_TENSOR_13_DIM_3_STRIDE_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_13_DIM_4_SIZE */
+#define TPC0_CFG_KERNEL_TENSOR_13_DIM_4_SIZE_V_SHIFT 0
+#define TPC0_CFG_KERNEL_TENSOR_13_DIM_4_SIZE_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_13_DIM_4_STRIDE */
+#define TPC0_CFG_KERNEL_TENSOR_13_DIM_4_STRIDE_V_SHIFT 0
+#define TPC0_CFG_KERNEL_TENSOR_13_DIM_4_STRIDE_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_14_BASE_ADDR_LOW */
+#define TPC0_CFG_KERNEL_TENSOR_14_BASE_ADDR_LOW_V_SHIFT 0
+#define TPC0_CFG_KERNEL_TENSOR_14_BASE_ADDR_LOW_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_14_BASE_ADDR_HIGH */
+#define TPC0_CFG_KERNEL_TENSOR_14_BASE_ADDR_HIGH_V_SHIFT 0
+#define TPC0_CFG_KERNEL_TENSOR_14_BASE_ADDR_HIGH_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_14_PADDING_VALUE */
+#define TPC0_CFG_KERNEL_TENSOR_14_PADDING_VALUE_V_SHIFT 0
+#define TPC0_CFG_KERNEL_TENSOR_14_PADDING_VALUE_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_14_TENSOR_CONFIG */
+#define TPC0_CFG_KERNEL_TENSOR_14_TENSOR_CONFIG_DATA_TYPE_SHIFT 0
+#define TPC0_CFG_KERNEL_TENSOR_14_TENSOR_CONFIG_DATA_TYPE_MASK 0x7
+#define TPC0_CFG_KERNEL_TENSOR_14_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT 8
+#define TPC0_CFG_KERNEL_TENSOR_14_TENSOR_CONFIG_VALID_DIM_MASK_MASK 0x1F00
+#define TPC0_CFG_KERNEL_TENSOR_14_TENSOR_CONFIG_LAST_DIM_SHIFT 16
+#define TPC0_CFG_KERNEL_TENSOR_14_TENSOR_CONFIG_LAST_DIM_MASK 0x70000
+#define TPC0_CFG_KERNEL_TENSOR_14_TENSOR_CONFIG_RMW_SET_SHIFT 19
+#define TPC0_CFG_KERNEL_TENSOR_14_TENSOR_CONFIG_RMW_SET_MASK 0x80000
+#define TPC0_CFG_KERNEL_TENSOR_14_TENSOR_CONFIG_RMW_RESERV_SHIFT 20
+#define TPC0_CFG_KERNEL_TENSOR_14_TENSOR_CONFIG_RMW_RESERV_MASK 0x100000
+#define TPC0_CFG_KERNEL_TENSOR_14_TENSOR_CONFIG_RMW_OP_SHIFT 21
+#define TPC0_CFG_KERNEL_TENSOR_14_TENSOR_CONFIG_RMW_OP_MASK 0x600000
+
+/* TPC0_CFG_KERNEL_TENSOR_14_DIM_0_SIZE */
+#define TPC0_CFG_KERNEL_TENSOR_14_DIM_0_SIZE_V_SHIFT 0
+#define TPC0_CFG_KERNEL_TENSOR_14_DIM_0_SIZE_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_14_DIM_0_STRIDE */
+#define TPC0_CFG_KERNEL_TENSOR_14_DIM_0_STRIDE_V_SHIFT 0
+#define TPC0_CFG_KERNEL_TENSOR_14_DIM_0_STRIDE_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_14_DIM_1_SIZE */
+#define TPC0_CFG_KERNEL_TENSOR_14_DIM_1_SIZE_V_SHIFT 0
+#define TPC0_CFG_KERNEL_TENSOR_14_DIM_1_SIZE_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_14_DIM_1_STRIDE */
+#define TPC0_CFG_KERNEL_TENSOR_14_DIM_1_STRIDE_V_SHIFT 0
+#define TPC0_CFG_KERNEL_TENSOR_14_DIM_1_STRIDE_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_14_DIM_2_SIZE */
+#define TPC0_CFG_KERNEL_TENSOR_14_DIM_2_SIZE_V_SHIFT 0
+#define TPC0_CFG_KERNEL_TENSOR_14_DIM_2_SIZE_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_14_DIM_2_STRIDE */
+#define TPC0_CFG_KERNEL_TENSOR_14_DIM_2_STRIDE_V_SHIFT 0
+#define TPC0_CFG_KERNEL_TENSOR_14_DIM_2_STRIDE_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_14_DIM_3_SIZE */
+#define TPC0_CFG_KERNEL_TENSOR_14_DIM_3_SIZE_V_SHIFT 0
+#define TPC0_CFG_KERNEL_TENSOR_14_DIM_3_SIZE_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_14_DIM_3_STRIDE */
+#define TPC0_CFG_KERNEL_TENSOR_14_DIM_3_STRIDE_V_SHIFT 0
+#define TPC0_CFG_KERNEL_TENSOR_14_DIM_3_STRIDE_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_14_DIM_4_SIZE */
+#define TPC0_CFG_KERNEL_TENSOR_14_DIM_4_SIZE_V_SHIFT 0
+#define TPC0_CFG_KERNEL_TENSOR_14_DIM_4_SIZE_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_14_DIM_4_STRIDE */
+#define TPC0_CFG_KERNEL_TENSOR_14_DIM_4_STRIDE_V_SHIFT 0
+#define TPC0_CFG_KERNEL_TENSOR_14_DIM_4_STRIDE_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_15_BASE_ADDR_LOW */
+#define TPC0_CFG_KERNEL_TENSOR_15_BASE_ADDR_LOW_V_SHIFT 0
+#define TPC0_CFG_KERNEL_TENSOR_15_BASE_ADDR_LOW_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_15_BASE_ADDR_HIGH */
+#define TPC0_CFG_KERNEL_TENSOR_15_BASE_ADDR_HIGH_V_SHIFT 0
+#define TPC0_CFG_KERNEL_TENSOR_15_BASE_ADDR_HIGH_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_15_PADDING_VALUE */
+#define TPC0_CFG_KERNEL_TENSOR_15_PADDING_VALUE_V_SHIFT 0
+#define TPC0_CFG_KERNEL_TENSOR_15_PADDING_VALUE_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_15_TENSOR_CONFIG */
+#define TPC0_CFG_KERNEL_TENSOR_15_TENSOR_CONFIG_DATA_TYPE_SHIFT 0
+#define TPC0_CFG_KERNEL_TENSOR_15_TENSOR_CONFIG_DATA_TYPE_MASK 0x7
+#define TPC0_CFG_KERNEL_TENSOR_15_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT 8
+#define TPC0_CFG_KERNEL_TENSOR_15_TENSOR_CONFIG_VALID_DIM_MASK_MASK 0x1F00
+#define TPC0_CFG_KERNEL_TENSOR_15_TENSOR_CONFIG_LAST_DIM_SHIFT 16
+#define TPC0_CFG_KERNEL_TENSOR_15_TENSOR_CONFIG_LAST_DIM_MASK 0x70000
+#define TPC0_CFG_KERNEL_TENSOR_15_TENSOR_CONFIG_RMW_SET_SHIFT 19
+#define TPC0_CFG_KERNEL_TENSOR_15_TENSOR_CONFIG_RMW_SET_MASK 0x80000
+#define TPC0_CFG_KERNEL_TENSOR_15_TENSOR_CONFIG_RMW_RESERV_SHIFT 20
+#define TPC0_CFG_KERNEL_TENSOR_15_TENSOR_CONFIG_RMW_RESERV_MASK 0x100000
+#define TPC0_CFG_KERNEL_TENSOR_15_TENSOR_CONFIG_RMW_OP_SHIFT 21
+#define TPC0_CFG_KERNEL_TENSOR_15_TENSOR_CONFIG_RMW_OP_MASK 0x600000
+
+/* TPC0_CFG_KERNEL_TENSOR_15_DIM_0_SIZE */
+#define TPC0_CFG_KERNEL_TENSOR_15_DIM_0_SIZE_V_SHIFT 0
+#define TPC0_CFG_KERNEL_TENSOR_15_DIM_0_SIZE_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_15_DIM_0_STRIDE */
+#define TPC0_CFG_KERNEL_TENSOR_15_DIM_0_STRIDE_V_SHIFT 0
+#define TPC0_CFG_KERNEL_TENSOR_15_DIM_0_STRIDE_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_15_DIM_1_SIZE */
+#define TPC0_CFG_KERNEL_TENSOR_15_DIM_1_SIZE_V_SHIFT 0
+#define TPC0_CFG_KERNEL_TENSOR_15_DIM_1_SIZE_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_15_DIM_1_STRIDE */
+#define TPC0_CFG_KERNEL_TENSOR_15_DIM_1_STRIDE_V_SHIFT 0
+#define TPC0_CFG_KERNEL_TENSOR_15_DIM_1_STRIDE_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_15_DIM_2_SIZE */
+#define TPC0_CFG_KERNEL_TENSOR_15_DIM_2_SIZE_V_SHIFT 0
+#define TPC0_CFG_KERNEL_TENSOR_15_DIM_2_SIZE_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_15_DIM_2_STRIDE */
+#define TPC0_CFG_KERNEL_TENSOR_15_DIM_2_STRIDE_V_SHIFT 0
+#define TPC0_CFG_KERNEL_TENSOR_15_DIM_2_STRIDE_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_15_DIM_3_SIZE */
+#define TPC0_CFG_KERNEL_TENSOR_15_DIM_3_SIZE_V_SHIFT 0
+#define TPC0_CFG_KERNEL_TENSOR_15_DIM_3_SIZE_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_15_DIM_3_STRIDE */
+#define TPC0_CFG_KERNEL_TENSOR_15_DIM_3_STRIDE_V_SHIFT 0
+#define TPC0_CFG_KERNEL_TENSOR_15_DIM_3_STRIDE_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_15_DIM_4_SIZE */
+#define TPC0_CFG_KERNEL_TENSOR_15_DIM_4_SIZE_V_SHIFT 0
+#define TPC0_CFG_KERNEL_TENSOR_15_DIM_4_SIZE_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TENSOR_15_DIM_4_STRIDE */
+#define TPC0_CFG_KERNEL_TENSOR_15_DIM_4_STRIDE_V_SHIFT 0
+#define TPC0_CFG_KERNEL_TENSOR_15_DIM_4_STRIDE_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_SYNC_OBJECT_MESSAGE */
+#define TPC0_CFG_KERNEL_SYNC_OBJECT_MESSAGE_SO_WRITE_VALUE_SHIFT 0
+#define TPC0_CFG_KERNEL_SYNC_OBJECT_MESSAGE_SO_WRITE_VALUE_MASK 0xFFFF
+#define TPC0_CFG_KERNEL_SYNC_OBJECT_MESSAGE_RSV_SHIFT 16
+#define TPC0_CFG_KERNEL_SYNC_OBJECT_MESSAGE_RSV_MASK 0x1FFF0000
+#define TPC0_CFG_KERNEL_SYNC_OBJECT_MESSAGE_SO_OPERATION_SHIFT 29
+#define TPC0_CFG_KERNEL_SYNC_OBJECT_MESSAGE_SO_OPERATION_MASK 0xE0000000
+
+/* TPC0_CFG_KERNEL_SYNC_OBJECT_ADDR */
+#define TPC0_CFG_KERNEL_SYNC_OBJECT_ADDR_V_SHIFT 0
+#define TPC0_CFG_KERNEL_SYNC_OBJECT_ADDR_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_KERNEL_BASE_ADDRESS_LOW */
+#define TPC0_CFG_KERNEL_KERNEL_BASE_ADDRESS_LOW_V_SHIFT 0
+#define TPC0_CFG_KERNEL_KERNEL_BASE_ADDRESS_LOW_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_KERNEL_BASE_ADDRESS_HIGH */
+#define TPC0_CFG_KERNEL_KERNEL_BASE_ADDRESS_HIGH_V_SHIFT 0
+#define TPC0_CFG_KERNEL_KERNEL_BASE_ADDRESS_HIGH_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TID_BASE_DIM_0 */
+#define TPC0_CFG_KERNEL_TID_BASE_DIM_0_V_SHIFT 0
+#define TPC0_CFG_KERNEL_TID_BASE_DIM_0_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TID_SIZE_DIM_0 */
+#define TPC0_CFG_KERNEL_TID_SIZE_DIM_0_V_SHIFT 0
+#define TPC0_CFG_KERNEL_TID_SIZE_DIM_0_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TID_BASE_DIM_1 */
+#define TPC0_CFG_KERNEL_TID_BASE_DIM_1_V_SHIFT 0
+#define TPC0_CFG_KERNEL_TID_BASE_DIM_1_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TID_SIZE_DIM_1 */
+#define TPC0_CFG_KERNEL_TID_SIZE_DIM_1_V_SHIFT 0
+#define TPC0_CFG_KERNEL_TID_SIZE_DIM_1_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TID_BASE_DIM_2 */
+#define TPC0_CFG_KERNEL_TID_BASE_DIM_2_V_SHIFT 0
+#define TPC0_CFG_KERNEL_TID_BASE_DIM_2_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TID_SIZE_DIM_2 */
+#define TPC0_CFG_KERNEL_TID_SIZE_DIM_2_V_SHIFT 0
+#define TPC0_CFG_KERNEL_TID_SIZE_DIM_2_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TID_BASE_DIM_3 */
+#define TPC0_CFG_KERNEL_TID_BASE_DIM_3_V_SHIFT 0
+#define TPC0_CFG_KERNEL_TID_BASE_DIM_3_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TID_SIZE_DIM_3 */
+#define TPC0_CFG_KERNEL_TID_SIZE_DIM_3_V_SHIFT 0
+#define TPC0_CFG_KERNEL_TID_SIZE_DIM_3_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TID_BASE_DIM_4 */
+#define TPC0_CFG_KERNEL_TID_BASE_DIM_4_V_SHIFT 0
+#define TPC0_CFG_KERNEL_TID_BASE_DIM_4_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_TID_SIZE_DIM_4 */
+#define TPC0_CFG_KERNEL_TID_SIZE_DIM_4_V_SHIFT 0
+#define TPC0_CFG_KERNEL_TID_SIZE_DIM_4_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_KERNEL_KERNEL_CONFIG */
+#define TPC0_CFG_KERNEL_KERNEL_CONFIG_SMALL_VLM_SHIFT 0
+#define TPC0_CFG_KERNEL_KERNEL_CONFIG_SMALL_VLM_MASK 0x1
+#define TPC0_CFG_KERNEL_KERNEL_CONFIG_ASO_EVICT_L0_SHIFT 1
+#define TPC0_CFG_KERNEL_KERNEL_CONFIG_ASO_EVICT_L0_MASK 0x2
+#define TPC0_CFG_KERNEL_KERNEL_CONFIG_NUM_VALID_SRFS_SHIFT 2
+#define TPC0_CFG_KERNEL_KERNEL_CONFIG_NUM_VALID_SRFS_MASK 0xFC
+#define TPC0_CFG_KERNEL_KERNEL_CONFIG_RD_RATE_LIMIT_RST_TOKEN_SHIFT 8
+#define TPC0_CFG_KERNEL_KERNEL_CONFIG_RD_RATE_LIMIT_RST_TOKEN_MASK 0xFF00
+#define TPC0_CFG_KERNEL_KERNEL_CONFIG_WR_RATE_LIMIT_RST_TOKEN_SHIFT 16
+#define TPC0_CFG_KERNEL_KERNEL_CONFIG_WR_RATE_LIMIT_RST_TOKEN_MASK 0xFF0000
+
+/* TPC0_CFG_KERNEL_KERNEL_ID */
+#define TPC0_CFG_KERNEL_KERNEL_ID_V_SHIFT 0
+#define TPC0_CFG_KERNEL_KERNEL_ID_V_MASK 0xFFFF
+
+/* TPC0_CFG_KERNEL_SRF */
+#define TPC0_CFG_KERNEL_SRF_V_SHIFT 0
+#define TPC0_CFG_KERNEL_SRF_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_ROUND_CSR */
+#define TPC0_CFG_ROUND_CSR_MODE_SHIFT 0
+#define TPC0_CFG_ROUND_CSR_MODE_MASK 0x7
+
+/* TPC0_CFG_PROT */
+#define TPC0_CFG_PROT_AWPROT_SHIFT 0
+#define TPC0_CFG_PROT_AWPROT_MASK 0x7
+#define TPC0_CFG_PROT_ARPROT_SHIFT 3
+#define TPC0_CFG_PROT_ARPROT_MASK 0x38
+
+/* TPC0_CFG_SEMAPHORE */
+#define TPC0_CFG_SEMAPHORE_V_SHIFT 0
+#define TPC0_CFG_SEMAPHORE_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_VFLAGS */
+#define TPC0_CFG_VFLAGS_V_SHIFT 0
+#define TPC0_CFG_VFLAGS_V_MASK 0xF
+
+/* TPC0_CFG_SFLAGS */
+#define TPC0_CFG_SFLAGS_V_SHIFT 0
+#define TPC0_CFG_SFLAGS_V_MASK 0xF
+
+/* TPC0_CFG_LFSR_POLYNOM */
+#define TPC0_CFG_LFSR_POLYNOM_V_SHIFT 0
+#define TPC0_CFG_LFSR_POLYNOM_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_STATUS */
+#define TPC0_CFG_STATUS_SCALAR_PIPE_EMPTY_SHIFT 1
+#define TPC0_CFG_STATUS_SCALAR_PIPE_EMPTY_MASK 0x2
+#define TPC0_CFG_STATUS_VECTOR_PIPE_EMPTY_SHIFT 2
+#define TPC0_CFG_STATUS_VECTOR_PIPE_EMPTY_MASK 0x4
+#define TPC0_CFG_STATUS_IQ_EMPTY_SHIFT 3
+#define TPC0_CFG_STATUS_IQ_EMPTY_MASK 0x8
+#define TPC0_CFG_STATUS_SB_EMPTY_SHIFT 5
+#define TPC0_CFG_STATUS_SB_EMPTY_MASK 0x20
+#define TPC0_CFG_STATUS_QM_IDLE_SHIFT 6
+#define TPC0_CFG_STATUS_QM_IDLE_MASK 0x40
+#define TPC0_CFG_STATUS_QM_RDY_SHIFT 7
+#define TPC0_CFG_STATUS_QM_RDY_MASK 0x80
+
+/* TPC0_CFG_CFG_BASE_ADDRESS_HIGH */
+#define TPC0_CFG_CFG_BASE_ADDRESS_HIGH_V_SHIFT 0
+#define TPC0_CFG_CFG_BASE_ADDRESS_HIGH_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_CFG_SUBTRACT_VALUE */
+#define TPC0_CFG_CFG_SUBTRACT_VALUE_V_SHIFT 0
+#define TPC0_CFG_CFG_SUBTRACT_VALUE_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_SM_BASE_ADDRESS_HIGH */
+#define TPC0_CFG_SM_BASE_ADDRESS_HIGH_V_SHIFT 0
+#define TPC0_CFG_SM_BASE_ADDRESS_HIGH_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_TPC_CMD */
+#define TPC0_CFG_TPC_CMD_ICACHE_INVALIDATE_SHIFT 0
+#define TPC0_CFG_TPC_CMD_ICACHE_INVALIDATE_MASK 0x1
+#define TPC0_CFG_TPC_CMD_DCACHE_INVALIDATE_SHIFT 1
+#define TPC0_CFG_TPC_CMD_DCACHE_INVALIDATE_MASK 0x2
+#define TPC0_CFG_TPC_CMD_LCACHE_INVALIDATE_SHIFT 2
+#define TPC0_CFG_TPC_CMD_LCACHE_INVALIDATE_MASK 0x4
+#define TPC0_CFG_TPC_CMD_TCACHE_INVALIDATE_SHIFT 3
+#define TPC0_CFG_TPC_CMD_TCACHE_INVALIDATE_MASK 0x8
+#define TPC0_CFG_TPC_CMD_ICACHE_PREFETCH_64KB_SHIFT 4
+#define TPC0_CFG_TPC_CMD_ICACHE_PREFETCH_64KB_MASK 0x10
+#define TPC0_CFG_TPC_CMD_ICACHE_PREFETCH_32KB_SHIFT 5
+#define TPC0_CFG_TPC_CMD_ICACHE_PREFETCH_32KB_MASK 0x20
+#define TPC0_CFG_TPC_CMD_QMAN_STOP_SHIFT 6
+#define TPC0_CFG_TPC_CMD_QMAN_STOP_MASK 0x40
+
+/* TPC0_CFG_TPC_EXECUTE */
+#define TPC0_CFG_TPC_EXECUTE_V_SHIFT 0
+#define TPC0_CFG_TPC_EXECUTE_V_MASK 0x1
+
+/* TPC0_CFG_TPC_STALL */
+#define TPC0_CFG_TPC_STALL_V_SHIFT 0
+#define TPC0_CFG_TPC_STALL_V_MASK 0x1
+
+/* TPC0_CFG_ICACHE_BASE_ADDERESS_LOW */
+#define TPC0_CFG_ICACHE_BASE_ADDERESS_LOW_V_SHIFT 0
+#define TPC0_CFG_ICACHE_BASE_ADDERESS_LOW_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_ICACHE_BASE_ADDERESS_HIGH */
+#define TPC0_CFG_ICACHE_BASE_ADDERESS_HIGH_V_SHIFT 0
+#define TPC0_CFG_ICACHE_BASE_ADDERESS_HIGH_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_RD_RATE_LIMIT */
+#define TPC0_CFG_RD_RATE_LIMIT_ENABLE_SHIFT 0
+#define TPC0_CFG_RD_RATE_LIMIT_ENABLE_MASK 0x1
+#define TPC0_CFG_RD_RATE_LIMIT_SATURATION_SHIFT 1
+#define TPC0_CFG_RD_RATE_LIMIT_SATURATION_MASK 0x1FE
+#define TPC0_CFG_RD_RATE_LIMIT_TIMEOUT_SHIFT 9
+#define TPC0_CFG_RD_RATE_LIMIT_TIMEOUT_MASK 0x1FE00
+
+/* TPC0_CFG_WR_RATE_LIMIT */
+#define TPC0_CFG_WR_RATE_LIMIT_ENABLE_SHIFT 0
+#define TPC0_CFG_WR_RATE_LIMIT_ENABLE_MASK 0x1
+#define TPC0_CFG_WR_RATE_LIMIT_SATURATION_SHIFT 1
+#define TPC0_CFG_WR_RATE_LIMIT_SATURATION_MASK 0x1FE
+#define TPC0_CFG_WR_RATE_LIMIT_TIMEOUT_SHIFT 9
+#define TPC0_CFG_WR_RATE_LIMIT_TIMEOUT_MASK 0x1FE00
+
+/* TPC0_CFG_MSS_CONFIG */
+#define TPC0_CFG_MSS_CONFIG_AWCACHE_SHIFT 0
+#define TPC0_CFG_MSS_CONFIG_AWCACHE_MASK 0xF
+#define TPC0_CFG_MSS_CONFIG_ARCACHE_SHIFT 4
+#define TPC0_CFG_MSS_CONFIG_ARCACHE_MASK 0xF0
+#define TPC0_CFG_MSS_CONFIG_ICACHE_FETCH_LINE_NUM_SHIFT 8
+#define TPC0_CFG_MSS_CONFIG_ICACHE_FETCH_LINE_NUM_MASK 0x300
+#define TPC0_CFG_MSS_CONFIG_EXPOSED_PIPE_DIS_SHIFT 10
+#define TPC0_CFG_MSS_CONFIG_EXPOSED_PIPE_DIS_MASK 0x400
+#define TPC0_CFG_MSS_CONFIG_DCACHE_PREFETCH_DIS_SHIFT 11
+#define TPC0_CFG_MSS_CONFIG_DCACHE_PREFETCH_DIS_MASK 0x800
+
+/* TPC0_CFG_TPC_INTR_CAUSE */
+#define TPC0_CFG_TPC_INTR_CAUSE_CAUSE_SHIFT 0
+#define TPC0_CFG_TPC_INTR_CAUSE_CAUSE_MASK 0xFFFFF
+
+/* TPC0_CFG_TPC_INTR_MASK */
+#define TPC0_CFG_TPC_INTR_MASK_MASK_SHIFT 0
+#define TPC0_CFG_TPC_INTR_MASK_MASK_MASK 0xFFFFF
+
+/* TPC0_CFG_WQ_CREDITS */
+#define TPC0_CFG_WQ_CREDITS_ST_G_SHIFT 0
+#define TPC0_CFG_WQ_CREDITS_ST_G_MASK 0xF
+#define TPC0_CFG_WQ_CREDITS_KERNEL_FIFO_SHIFT 4
+#define TPC0_CFG_WQ_CREDITS_KERNEL_FIFO_MASK 0x70
+
+/* TPC0_CFG_ARUSER_LO */
+#define TPC0_CFG_ARUSER_LO_V_SHIFT 0
+#define TPC0_CFG_ARUSER_LO_V_MASK 0x7FF
+
+/* TPC0_CFG_ARUSER_HI */
+#define TPC0_CFG_ARUSER_HI_V_SHIFT 11
+#define TPC0_CFG_ARUSER_HI_V_MASK 0x1800
+#define TPC0_CFG_ARUSER_HI_RSRV_SHIFT 13
+#define TPC0_CFG_ARUSER_HI_RSRV_MASK 0xFFFFE000
+
+/* TPC0_CFG_AWUSER_LO */
+#define TPC0_CFG_AWUSER_LO_V_SHIFT 0
+#define TPC0_CFG_AWUSER_LO_V_MASK 0x7FF
+
+/* TPC0_CFG_AWUSER_HI */
+#define TPC0_CFG_AWUSER_HI_V_SHIFT 11
+#define TPC0_CFG_AWUSER_HI_V_MASK 0x1800
+#define TPC0_CFG_AWUSER_HI_RSRV_SHIFT 13
+#define TPC0_CFG_AWUSER_HI_RSRV_MASK 0xFFFFE000
+
+/* TPC0_CFG_OPCODE_EXEC */
+#define TPC0_CFG_OPCODE_EXEC_SPU_OP_SHIFT 0
+#define TPC0_CFG_OPCODE_EXEC_SPU_OP_MASK 0x7F
+#define TPC0_CFG_OPCODE_EXEC_SPU_EN_SHIFT 7
+#define TPC0_CFG_OPCODE_EXEC_SPU_EN_MASK 0x80
+#define TPC0_CFG_OPCODE_EXEC_VPU_OP_SHIFT 8
+#define TPC0_CFG_OPCODE_EXEC_VPU_OP_MASK 0x7F00
+#define TPC0_CFG_OPCODE_EXEC_VPU_EN_SHIFT 15
+#define TPC0_CFG_OPCODE_EXEC_VPU_EN_MASK 0x8000
+#define TPC0_CFG_OPCODE_EXEC_LD_OP_SHIFT 16
+#define TPC0_CFG_OPCODE_EXEC_LD_OP_MASK 0x7F0000
+#define TPC0_CFG_OPCODE_EXEC_LD_EN_SHIFT 23
+#define TPC0_CFG_OPCODE_EXEC_LD_EN_MASK 0x800000
+#define TPC0_CFG_OPCODE_EXEC_ST_OP_SHIFT 24
+#define TPC0_CFG_OPCODE_EXEC_ST_OP_MASK 0x7F000000
+#define TPC0_CFG_OPCODE_EXEC_ST_EN_SHIFT 31
+#define TPC0_CFG_OPCODE_EXEC_ST_EN_MASK 0x80000000
+
+/* TPC0_CFG_LUT_FUNC32_BASE_ADDR_LO */
+#define TPC0_CFG_LUT_FUNC32_BASE_ADDR_LO_V_SHIFT 0
+#define TPC0_CFG_LUT_FUNC32_BASE_ADDR_LO_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_LUT_FUNC32_BASE_ADDR_HI */
+#define TPC0_CFG_LUT_FUNC32_BASE_ADDR_HI_V_SHIFT 0
+#define TPC0_CFG_LUT_FUNC32_BASE_ADDR_HI_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_LUT_FUNC64_BASE_ADDR_LO */
+#define TPC0_CFG_LUT_FUNC64_BASE_ADDR_LO_V_SHIFT 0
+#define TPC0_CFG_LUT_FUNC64_BASE_ADDR_LO_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_LUT_FUNC64_BASE_ADDR_HI */
+#define TPC0_CFG_LUT_FUNC64_BASE_ADDR_HI_V_SHIFT 0
+#define TPC0_CFG_LUT_FUNC64_BASE_ADDR_HI_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_LUT_FUNC128_BASE_ADDR_LO */
+#define TPC0_CFG_LUT_FUNC128_BASE_ADDR_LO_V_SHIFT 0
+#define TPC0_CFG_LUT_FUNC128_BASE_ADDR_LO_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_LUT_FUNC128_BASE_ADDR_HI */
+#define TPC0_CFG_LUT_FUNC128_BASE_ADDR_HI_V_SHIFT 0
+#define TPC0_CFG_LUT_FUNC128_BASE_ADDR_HI_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_LUT_FUNC256_BASE_ADDR_LO */
+#define TPC0_CFG_LUT_FUNC256_BASE_ADDR_LO_V_SHIFT 0
+#define TPC0_CFG_LUT_FUNC256_BASE_ADDR_LO_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_LUT_FUNC256_BASE_ADDR_HI */
+#define TPC0_CFG_LUT_FUNC256_BASE_ADDR_HI_V_SHIFT 0
+#define TPC0_CFG_LUT_FUNC256_BASE_ADDR_HI_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_TSB_CFG_MAX_SIZE */
+#define TPC0_CFG_TSB_CFG_MAX_SIZE_DATA_SHIFT 0
+#define TPC0_CFG_TSB_CFG_MAX_SIZE_DATA_MASK 0xFFFF
+#define TPC0_CFG_TSB_CFG_MAX_SIZE_MD_SHIFT 16
+#define TPC0_CFG_TSB_CFG_MAX_SIZE_MD_MASK 0xFFFF0000
+
+/* TPC0_CFG_TSB_CFG */
+#define TPC0_CFG_TSB_CFG_FORCE_MISS_SHIFT 0
+#define TPC0_CFG_TSB_CFG_FORCE_MISS_MASK 0x1
+#define TPC0_CFG_TSB_CFG_MAX_OS_SHIFT 1
+#define TPC0_CFG_TSB_CFG_MAX_OS_MASK 0x1FFFE
+
+/* TPC0_CFG_DBGMEM_ADD */
+#define TPC0_CFG_DBGMEM_ADD_V_SHIFT 0
+#define TPC0_CFG_DBGMEM_ADD_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_DBGMEM_DATA_WR */
+#define TPC0_CFG_DBGMEM_DATA_WR_V_SHIFT 0
+#define TPC0_CFG_DBGMEM_DATA_WR_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_DBGMEM_DATA_RD */
+#define TPC0_CFG_DBGMEM_DATA_RD_V_SHIFT 0
+#define TPC0_CFG_DBGMEM_DATA_RD_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_DBGMEM_CTRL */
+#define TPC0_CFG_DBGMEM_CTRL_WR_NRD_SHIFT 0
+#define TPC0_CFG_DBGMEM_CTRL_WR_NRD_MASK 0x1
+
+/* TPC0_CFG_DBGMEM_RC */
+#define TPC0_CFG_DBGMEM_RC_VALID_SHIFT 0
+#define TPC0_CFG_DBGMEM_RC_VALID_MASK 0x1
+
+/* TPC0_CFG_TSB_INFLIGHT_CNTR */
+#define TPC0_CFG_TSB_INFLIGHT_CNTR_V_SHIFT 0
+#define TPC0_CFG_TSB_INFLIGHT_CNTR_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_WQ_INFLIGHT_CNTR */
+#define TPC0_CFG_WQ_INFLIGHT_CNTR_HBW_SHIFT 0
+#define TPC0_CFG_WQ_INFLIGHT_CNTR_HBW_MASK 0xFFFF
+#define TPC0_CFG_WQ_INFLIGHT_CNTR_LBW_SHIFT 16
+#define TPC0_CFG_WQ_INFLIGHT_CNTR_LBW_MASK 0xF0000
+
+/* TPC0_CFG_WQ_LBW_TOTAL_CNTR */
+#define TPC0_CFG_WQ_LBW_TOTAL_CNTR_V_SHIFT 0
+#define TPC0_CFG_WQ_LBW_TOTAL_CNTR_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_WQ_HBW_TOTAL_CNTR */
+#define TPC0_CFG_WQ_HBW_TOTAL_CNTR_V_SHIFT 0
+#define TPC0_CFG_WQ_HBW_TOTAL_CNTR_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_IRQ_OCCOUPY_CNTR */
+#define TPC0_CFG_IRQ_OCCOUPY_CNTR_V_SHIFT 0
+#define TPC0_CFG_IRQ_OCCOUPY_CNTR_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_FUNC_MBIST_CNTRL */
+#define TPC0_CFG_FUNC_MBIST_CNTRL_MBIST_START_SHIFT 0
+#define TPC0_CFG_FUNC_MBIST_CNTRL_MBIST_START_MASK 0x1
+#define TPC0_CFG_FUNC_MBIST_CNTRL_MBIST_DONE_SHIFT 1
+#define TPC0_CFG_FUNC_MBIST_CNTRL_MBIST_DONE_MASK 0x2
+#define TPC0_CFG_FUNC_MBIST_CNTRL_MBIST_ACTIVE_SHIFT 2
+#define TPC0_CFG_FUNC_MBIST_CNTRL_MBIST_ACTIVE_MASK 0x4
+#define TPC0_CFG_FUNC_MBIST_CNTRL_MBIST_FAILED_SHIFT 16
+#define TPC0_CFG_FUNC_MBIST_CNTRL_MBIST_FAILED_MASK 0x3FF0000
+
+/* TPC0_CFG_FUNC_MBIST_PAT */
+#define TPC0_CFG_FUNC_MBIST_PAT_MBIST_PATTERN0_EVEN_SHIFT 0
+#define TPC0_CFG_FUNC_MBIST_PAT_MBIST_PATTERN0_EVEN_MASK 0x3
+#define TPC0_CFG_FUNC_MBIST_PAT_MBIST_PATTERN0_ODD_SHIFT 2
+#define TPC0_CFG_FUNC_MBIST_PAT_MBIST_PATTERN0_ODD_MASK 0xC
+#define TPC0_CFG_FUNC_MBIST_PAT_MBIST_PATTERN1_EVEN_SHIFT 4
+#define TPC0_CFG_FUNC_MBIST_PAT_MBIST_PATTERN1_EVEN_MASK 0x30
+#define TPC0_CFG_FUNC_MBIST_PAT_MBIST_PATTERN1_ODD_SHIFT 6
+#define TPC0_CFG_FUNC_MBIST_PAT_MBIST_PATTERN1_ODD_MASK 0xC0
+#define TPC0_CFG_FUNC_MBIST_PAT_MBIST_PATTERN2_EVEN_SHIFT 8
+#define TPC0_CFG_FUNC_MBIST_PAT_MBIST_PATTERN2_EVEN_MASK 0x300
+#define TPC0_CFG_FUNC_MBIST_PAT_MBIST_PATTERN2_ODD_SHIFT 10
+#define TPC0_CFG_FUNC_MBIST_PAT_MBIST_PATTERN2_ODD_MASK 0xC00
+
+/* TPC0_CFG_FUNC_MBIST_MEM */
+#define TPC0_CFG_FUNC_MBIST_MEM_MAX_ADDR_SHIFT 0
+#define TPC0_CFG_FUNC_MBIST_MEM_MAX_ADDR_MASK 0x7FF
+#define TPC0_CFG_FUNC_MBIST_MEM_PATTERN_EN_SHIFT 12
+#define TPC0_CFG_FUNC_MBIST_MEM_PATTERN_EN_MASK 0x7000
+#define TPC0_CFG_FUNC_MBIST_MEM_LAST_FAILED_ADDR_SHIFT 16
+#define TPC0_CFG_FUNC_MBIST_MEM_LAST_FAILED_ADDR_MASK 0x7FF0000
+#define TPC0_CFG_FUNC_MBIST_MEM_LAST_FAILED_PATTERN_SHIFT 28
+#define TPC0_CFG_FUNC_MBIST_MEM_LAST_FAILED_PATTERN_MASK 0x70000000
+
+/* TPC0_CFG_QM_TENSOR_0_BASE_ADDR_LOW */
+#define TPC0_CFG_QM_TENSOR_0_BASE_ADDR_LOW_V_SHIFT 0
+#define TPC0_CFG_QM_TENSOR_0_BASE_ADDR_LOW_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_0_BASE_ADDR_HIGH */
+#define TPC0_CFG_QM_TENSOR_0_BASE_ADDR_HIGH_V_SHIFT 0
+#define TPC0_CFG_QM_TENSOR_0_BASE_ADDR_HIGH_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_0_PADDING_VALUE */
+#define TPC0_CFG_QM_TENSOR_0_PADDING_VALUE_V_SHIFT 0
+#define TPC0_CFG_QM_TENSOR_0_PADDING_VALUE_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_0_TENSOR_CONFIG */
+#define TPC0_CFG_QM_TENSOR_0_TENSOR_CONFIG_DATA_TYPE_SHIFT 0
+#define TPC0_CFG_QM_TENSOR_0_TENSOR_CONFIG_DATA_TYPE_MASK 0x7
+#define TPC0_CFG_QM_TENSOR_0_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT 8
+#define TPC0_CFG_QM_TENSOR_0_TENSOR_CONFIG_VALID_DIM_MASK_MASK 0x1F00
+#define TPC0_CFG_QM_TENSOR_0_TENSOR_CONFIG_LAST_DIM_SHIFT 16
+#define TPC0_CFG_QM_TENSOR_0_TENSOR_CONFIG_LAST_DIM_MASK 0x70000
+#define TPC0_CFG_QM_TENSOR_0_TENSOR_CONFIG_RMW_SET_SHIFT 19
+#define TPC0_CFG_QM_TENSOR_0_TENSOR_CONFIG_RMW_SET_MASK 0x80000
+#define TPC0_CFG_QM_TENSOR_0_TENSOR_CONFIG_RMW_RESERV_SHIFT 20
+#define TPC0_CFG_QM_TENSOR_0_TENSOR_CONFIG_RMW_RESERV_MASK 0x100000
+#define TPC0_CFG_QM_TENSOR_0_TENSOR_CONFIG_RMW_OP_SHIFT 21
+#define TPC0_CFG_QM_TENSOR_0_TENSOR_CONFIG_RMW_OP_MASK 0x600000
+
+/* TPC0_CFG_QM_TENSOR_0_DIM_0_SIZE */
+#define TPC0_CFG_QM_TENSOR_0_DIM_0_SIZE_V_SHIFT 0
+#define TPC0_CFG_QM_TENSOR_0_DIM_0_SIZE_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_0_DIM_0_STRIDE */
+#define TPC0_CFG_QM_TENSOR_0_DIM_0_STRIDE_V_SHIFT 0
+#define TPC0_CFG_QM_TENSOR_0_DIM_0_STRIDE_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_0_DIM_1_SIZE */
+#define TPC0_CFG_QM_TENSOR_0_DIM_1_SIZE_V_SHIFT 0
+#define TPC0_CFG_QM_TENSOR_0_DIM_1_SIZE_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_0_DIM_1_STRIDE */
+#define TPC0_CFG_QM_TENSOR_0_DIM_1_STRIDE_V_SHIFT 0
+#define TPC0_CFG_QM_TENSOR_0_DIM_1_STRIDE_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_0_DIM_2_SIZE */
+#define TPC0_CFG_QM_TENSOR_0_DIM_2_SIZE_V_SHIFT 0
+#define TPC0_CFG_QM_TENSOR_0_DIM_2_SIZE_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_0_DIM_2_STRIDE */
+#define TPC0_CFG_QM_TENSOR_0_DIM_2_STRIDE_V_SHIFT 0
+#define TPC0_CFG_QM_TENSOR_0_DIM_2_STRIDE_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_0_DIM_3_SIZE */
+#define TPC0_CFG_QM_TENSOR_0_DIM_3_SIZE_V_SHIFT 0
+#define TPC0_CFG_QM_TENSOR_0_DIM_3_SIZE_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_0_DIM_3_STRIDE */
+#define TPC0_CFG_QM_TENSOR_0_DIM_3_STRIDE_V_SHIFT 0
+#define TPC0_CFG_QM_TENSOR_0_DIM_3_STRIDE_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_0_DIM_4_SIZE */
+#define TPC0_CFG_QM_TENSOR_0_DIM_4_SIZE_V_SHIFT 0
+#define TPC0_CFG_QM_TENSOR_0_DIM_4_SIZE_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_0_DIM_4_STRIDE */
+#define TPC0_CFG_QM_TENSOR_0_DIM_4_STRIDE_V_SHIFT 0
+#define TPC0_CFG_QM_TENSOR_0_DIM_4_STRIDE_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_1_BASE_ADDR_LOW */
+#define TPC0_CFG_QM_TENSOR_1_BASE_ADDR_LOW_V_SHIFT 0
+#define TPC0_CFG_QM_TENSOR_1_BASE_ADDR_LOW_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_1_BASE_ADDR_HIGH */
+#define TPC0_CFG_QM_TENSOR_1_BASE_ADDR_HIGH_V_SHIFT 0
+#define TPC0_CFG_QM_TENSOR_1_BASE_ADDR_HIGH_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_1_PADDING_VALUE */
+#define TPC0_CFG_QM_TENSOR_1_PADDING_VALUE_V_SHIFT 0
+#define TPC0_CFG_QM_TENSOR_1_PADDING_VALUE_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_1_TENSOR_CONFIG */
+#define TPC0_CFG_QM_TENSOR_1_TENSOR_CONFIG_DATA_TYPE_SHIFT 0
+#define TPC0_CFG_QM_TENSOR_1_TENSOR_CONFIG_DATA_TYPE_MASK 0x7
+#define TPC0_CFG_QM_TENSOR_1_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT 8
+#define TPC0_CFG_QM_TENSOR_1_TENSOR_CONFIG_VALID_DIM_MASK_MASK 0x1F00
+#define TPC0_CFG_QM_TENSOR_1_TENSOR_CONFIG_LAST_DIM_SHIFT 16
+#define TPC0_CFG_QM_TENSOR_1_TENSOR_CONFIG_LAST_DIM_MASK 0x70000
+#define TPC0_CFG_QM_TENSOR_1_TENSOR_CONFIG_RMW_SET_SHIFT 19
+#define TPC0_CFG_QM_TENSOR_1_TENSOR_CONFIG_RMW_SET_MASK 0x80000
+#define TPC0_CFG_QM_TENSOR_1_TENSOR_CONFIG_RMW_RESERV_SHIFT 20
+#define TPC0_CFG_QM_TENSOR_1_TENSOR_CONFIG_RMW_RESERV_MASK 0x100000
+#define TPC0_CFG_QM_TENSOR_1_TENSOR_CONFIG_RMW_OP_SHIFT 21
+#define TPC0_CFG_QM_TENSOR_1_TENSOR_CONFIG_RMW_OP_MASK 0x600000
+
+/* TPC0_CFG_QM_TENSOR_1_DIM_0_SIZE */
+#define TPC0_CFG_QM_TENSOR_1_DIM_0_SIZE_V_SHIFT 0
+#define TPC0_CFG_QM_TENSOR_1_DIM_0_SIZE_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_1_DIM_0_STRIDE */
+#define TPC0_CFG_QM_TENSOR_1_DIM_0_STRIDE_V_SHIFT 0
+#define TPC0_CFG_QM_TENSOR_1_DIM_0_STRIDE_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_1_DIM_1_SIZE */
+#define TPC0_CFG_QM_TENSOR_1_DIM_1_SIZE_V_SHIFT 0
+#define TPC0_CFG_QM_TENSOR_1_DIM_1_SIZE_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_1_DIM_1_STRIDE */
+#define TPC0_CFG_QM_TENSOR_1_DIM_1_STRIDE_V_SHIFT 0
+#define TPC0_CFG_QM_TENSOR_1_DIM_1_STRIDE_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_1_DIM_2_SIZE */
+#define TPC0_CFG_QM_TENSOR_1_DIM_2_SIZE_V_SHIFT 0
+#define TPC0_CFG_QM_TENSOR_1_DIM_2_SIZE_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_1_DIM_2_STRIDE */
+#define TPC0_CFG_QM_TENSOR_1_DIM_2_STRIDE_V_SHIFT 0
+#define TPC0_CFG_QM_TENSOR_1_DIM_2_STRIDE_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_1_DIM_3_SIZE */
+#define TPC0_CFG_QM_TENSOR_1_DIM_3_SIZE_V_SHIFT 0
+#define TPC0_CFG_QM_TENSOR_1_DIM_3_SIZE_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_1_DIM_3_STRIDE */
+#define TPC0_CFG_QM_TENSOR_1_DIM_3_STRIDE_V_SHIFT 0
+#define TPC0_CFG_QM_TENSOR_1_DIM_3_STRIDE_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_1_DIM_4_SIZE */
+#define TPC0_CFG_QM_TENSOR_1_DIM_4_SIZE_V_SHIFT 0
+#define TPC0_CFG_QM_TENSOR_1_DIM_4_SIZE_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_1_DIM_4_STRIDE */
+#define TPC0_CFG_QM_TENSOR_1_DIM_4_STRIDE_V_SHIFT 0
+#define TPC0_CFG_QM_TENSOR_1_DIM_4_STRIDE_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_2_BASE_ADDR_LOW */
+#define TPC0_CFG_QM_TENSOR_2_BASE_ADDR_LOW_V_SHIFT 0
+#define TPC0_CFG_QM_TENSOR_2_BASE_ADDR_LOW_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_2_BASE_ADDR_HIGH */
+#define TPC0_CFG_QM_TENSOR_2_BASE_ADDR_HIGH_V_SHIFT 0
+#define TPC0_CFG_QM_TENSOR_2_BASE_ADDR_HIGH_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_2_PADDING_VALUE */
+#define TPC0_CFG_QM_TENSOR_2_PADDING_VALUE_V_SHIFT 0
+#define TPC0_CFG_QM_TENSOR_2_PADDING_VALUE_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_2_TENSOR_CONFIG */
+#define TPC0_CFG_QM_TENSOR_2_TENSOR_CONFIG_DATA_TYPE_SHIFT 0
+#define TPC0_CFG_QM_TENSOR_2_TENSOR_CONFIG_DATA_TYPE_MASK 0x7
+#define TPC0_CFG_QM_TENSOR_2_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT 8
+#define TPC0_CFG_QM_TENSOR_2_TENSOR_CONFIG_VALID_DIM_MASK_MASK 0x1F00
+#define TPC0_CFG_QM_TENSOR_2_TENSOR_CONFIG_LAST_DIM_SHIFT 16
+#define TPC0_CFG_QM_TENSOR_2_TENSOR_CONFIG_LAST_DIM_MASK 0x70000
+#define TPC0_CFG_QM_TENSOR_2_TENSOR_CONFIG_RMW_SET_SHIFT 19
+#define TPC0_CFG_QM_TENSOR_2_TENSOR_CONFIG_RMW_SET_MASK 0x80000
+#define TPC0_CFG_QM_TENSOR_2_TENSOR_CONFIG_RMW_RESERV_SHIFT 20
+#define TPC0_CFG_QM_TENSOR_2_TENSOR_CONFIG_RMW_RESERV_MASK 0x100000
+#define TPC0_CFG_QM_TENSOR_2_TENSOR_CONFIG_RMW_OP_SHIFT 21
+#define TPC0_CFG_QM_TENSOR_2_TENSOR_CONFIG_RMW_OP_MASK 0x600000
+
+/* TPC0_CFG_QM_TENSOR_2_DIM_0_SIZE */
+#define TPC0_CFG_QM_TENSOR_2_DIM_0_SIZE_V_SHIFT 0
+#define TPC0_CFG_QM_TENSOR_2_DIM_0_SIZE_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_2_DIM_0_STRIDE */
+#define TPC0_CFG_QM_TENSOR_2_DIM_0_STRIDE_V_SHIFT 0
+#define TPC0_CFG_QM_TENSOR_2_DIM_0_STRIDE_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_2_DIM_1_SIZE */
+#define TPC0_CFG_QM_TENSOR_2_DIM_1_SIZE_V_SHIFT 0
+#define TPC0_CFG_QM_TENSOR_2_DIM_1_SIZE_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_2_DIM_1_STRIDE */
+#define TPC0_CFG_QM_TENSOR_2_DIM_1_STRIDE_V_SHIFT 0
+#define TPC0_CFG_QM_TENSOR_2_DIM_1_STRIDE_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_2_DIM_2_SIZE */
+#define TPC0_CFG_QM_TENSOR_2_DIM_2_SIZE_V_SHIFT 0
+#define TPC0_CFG_QM_TENSOR_2_DIM_2_SIZE_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_2_DIM_2_STRIDE */
+#define TPC0_CFG_QM_TENSOR_2_DIM_2_STRIDE_V_SHIFT 0
+#define TPC0_CFG_QM_TENSOR_2_DIM_2_STRIDE_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_2_DIM_3_SIZE */
+#define TPC0_CFG_QM_TENSOR_2_DIM_3_SIZE_V_SHIFT 0
+#define TPC0_CFG_QM_TENSOR_2_DIM_3_SIZE_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_2_DIM_3_STRIDE */
+#define TPC0_CFG_QM_TENSOR_2_DIM_3_STRIDE_V_SHIFT 0
+#define TPC0_CFG_QM_TENSOR_2_DIM_3_STRIDE_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_2_DIM_4_SIZE */
+#define TPC0_CFG_QM_TENSOR_2_DIM_4_SIZE_V_SHIFT 0
+#define TPC0_CFG_QM_TENSOR_2_DIM_4_SIZE_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_2_DIM_4_STRIDE */
+#define TPC0_CFG_QM_TENSOR_2_DIM_4_STRIDE_V_SHIFT 0
+#define TPC0_CFG_QM_TENSOR_2_DIM_4_STRIDE_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_3_BASE_ADDR_LOW */
+#define TPC0_CFG_QM_TENSOR_3_BASE_ADDR_LOW_V_SHIFT 0
+#define TPC0_CFG_QM_TENSOR_3_BASE_ADDR_LOW_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_3_BASE_ADDR_HIGH */
+#define TPC0_CFG_QM_TENSOR_3_BASE_ADDR_HIGH_V_SHIFT 0
+#define TPC0_CFG_QM_TENSOR_3_BASE_ADDR_HIGH_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_3_PADDING_VALUE */
+#define TPC0_CFG_QM_TENSOR_3_PADDING_VALUE_V_SHIFT 0
+#define TPC0_CFG_QM_TENSOR_3_PADDING_VALUE_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_3_TENSOR_CONFIG */
+#define TPC0_CFG_QM_TENSOR_3_TENSOR_CONFIG_DATA_TYPE_SHIFT 0
+#define TPC0_CFG_QM_TENSOR_3_TENSOR_CONFIG_DATA_TYPE_MASK 0x7
+#define TPC0_CFG_QM_TENSOR_3_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT 8
+#define TPC0_CFG_QM_TENSOR_3_TENSOR_CONFIG_VALID_DIM_MASK_MASK 0x1F00
+#define TPC0_CFG_QM_TENSOR_3_TENSOR_CONFIG_LAST_DIM_SHIFT 16
+#define TPC0_CFG_QM_TENSOR_3_TENSOR_CONFIG_LAST_DIM_MASK 0x70000
+#define TPC0_CFG_QM_TENSOR_3_TENSOR_CONFIG_RMW_SET_SHIFT 19
+#define TPC0_CFG_QM_TENSOR_3_TENSOR_CONFIG_RMW_SET_MASK 0x80000
+#define TPC0_CFG_QM_TENSOR_3_TENSOR_CONFIG_RMW_RESERV_SHIFT 20
+#define TPC0_CFG_QM_TENSOR_3_TENSOR_CONFIG_RMW_RESERV_MASK 0x100000
+#define TPC0_CFG_QM_TENSOR_3_TENSOR_CONFIG_RMW_OP_SHIFT 21
+#define TPC0_CFG_QM_TENSOR_3_TENSOR_CONFIG_RMW_OP_MASK 0x600000
+
+/* TPC0_CFG_QM_TENSOR_3_DIM_0_SIZE */
+#define TPC0_CFG_QM_TENSOR_3_DIM_0_SIZE_V_SHIFT 0
+#define TPC0_CFG_QM_TENSOR_3_DIM_0_SIZE_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_3_DIM_0_STRIDE */
+#define TPC0_CFG_QM_TENSOR_3_DIM_0_STRIDE_V_SHIFT 0
+#define TPC0_CFG_QM_TENSOR_3_DIM_0_STRIDE_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_3_DIM_1_SIZE */
+#define TPC0_CFG_QM_TENSOR_3_DIM_1_SIZE_V_SHIFT 0
+#define TPC0_CFG_QM_TENSOR_3_DIM_1_SIZE_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_3_DIM_1_STRIDE */
+#define TPC0_CFG_QM_TENSOR_3_DIM_1_STRIDE_V_SHIFT 0
+#define TPC0_CFG_QM_TENSOR_3_DIM_1_STRIDE_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_3_DIM_2_SIZE */
+#define TPC0_CFG_QM_TENSOR_3_DIM_2_SIZE_V_SHIFT 0
+#define TPC0_CFG_QM_TENSOR_3_DIM_2_SIZE_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_3_DIM_2_STRIDE */
+#define TPC0_CFG_QM_TENSOR_3_DIM_2_STRIDE_V_SHIFT 0
+#define TPC0_CFG_QM_TENSOR_3_DIM_2_STRIDE_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_3_DIM_3_SIZE */
+#define TPC0_CFG_QM_TENSOR_3_DIM_3_SIZE_V_SHIFT 0
+#define TPC0_CFG_QM_TENSOR_3_DIM_3_SIZE_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_3_DIM_3_STRIDE */
+#define TPC0_CFG_QM_TENSOR_3_DIM_3_STRIDE_V_SHIFT 0
+#define TPC0_CFG_QM_TENSOR_3_DIM_3_STRIDE_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_3_DIM_4_SIZE */
+#define TPC0_CFG_QM_TENSOR_3_DIM_4_SIZE_V_SHIFT 0
+#define TPC0_CFG_QM_TENSOR_3_DIM_4_SIZE_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_3_DIM_4_STRIDE */
+#define TPC0_CFG_QM_TENSOR_3_DIM_4_STRIDE_V_SHIFT 0
+#define TPC0_CFG_QM_TENSOR_3_DIM_4_STRIDE_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_4_BASE_ADDR_LOW */
+#define TPC0_CFG_QM_TENSOR_4_BASE_ADDR_LOW_V_SHIFT 0
+#define TPC0_CFG_QM_TENSOR_4_BASE_ADDR_LOW_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_4_BASE_ADDR_HIGH */
+#define TPC0_CFG_QM_TENSOR_4_BASE_ADDR_HIGH_V_SHIFT 0
+#define TPC0_CFG_QM_TENSOR_4_BASE_ADDR_HIGH_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_4_PADDING_VALUE */
+#define TPC0_CFG_QM_TENSOR_4_PADDING_VALUE_V_SHIFT 0
+#define TPC0_CFG_QM_TENSOR_4_PADDING_VALUE_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_4_TENSOR_CONFIG */
+#define TPC0_CFG_QM_TENSOR_4_TENSOR_CONFIG_DATA_TYPE_SHIFT 0
+#define TPC0_CFG_QM_TENSOR_4_TENSOR_CONFIG_DATA_TYPE_MASK 0x7
+#define TPC0_CFG_QM_TENSOR_4_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT 8
+#define TPC0_CFG_QM_TENSOR_4_TENSOR_CONFIG_VALID_DIM_MASK_MASK 0x1F00
+#define TPC0_CFG_QM_TENSOR_4_TENSOR_CONFIG_LAST_DIM_SHIFT 16
+#define TPC0_CFG_QM_TENSOR_4_TENSOR_CONFIG_LAST_DIM_MASK 0x70000
+#define TPC0_CFG_QM_TENSOR_4_TENSOR_CONFIG_RMW_SET_SHIFT 19
+#define TPC0_CFG_QM_TENSOR_4_TENSOR_CONFIG_RMW_SET_MASK 0x80000
+#define TPC0_CFG_QM_TENSOR_4_TENSOR_CONFIG_RMW_RESERV_SHIFT 20
+#define TPC0_CFG_QM_TENSOR_4_TENSOR_CONFIG_RMW_RESERV_MASK 0x100000
+#define TPC0_CFG_QM_TENSOR_4_TENSOR_CONFIG_RMW_OP_SHIFT 21
+#define TPC0_CFG_QM_TENSOR_4_TENSOR_CONFIG_RMW_OP_MASK 0x600000
+
+/* TPC0_CFG_QM_TENSOR_4_DIM_0_SIZE */
+#define TPC0_CFG_QM_TENSOR_4_DIM_0_SIZE_V_SHIFT 0
+#define TPC0_CFG_QM_TENSOR_4_DIM_0_SIZE_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_4_DIM_0_STRIDE */
+#define TPC0_CFG_QM_TENSOR_4_DIM_0_STRIDE_V_SHIFT 0
+#define TPC0_CFG_QM_TENSOR_4_DIM_0_STRIDE_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_4_DIM_1_SIZE */
+#define TPC0_CFG_QM_TENSOR_4_DIM_1_SIZE_V_SHIFT 0
+#define TPC0_CFG_QM_TENSOR_4_DIM_1_SIZE_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_4_DIM_1_STRIDE */
+#define TPC0_CFG_QM_TENSOR_4_DIM_1_STRIDE_V_SHIFT 0
+#define TPC0_CFG_QM_TENSOR_4_DIM_1_STRIDE_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_4_DIM_2_SIZE */
+#define TPC0_CFG_QM_TENSOR_4_DIM_2_SIZE_V_SHIFT 0
+#define TPC0_CFG_QM_TENSOR_4_DIM_2_SIZE_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_4_DIM_2_STRIDE */
+#define TPC0_CFG_QM_TENSOR_4_DIM_2_STRIDE_V_SHIFT 0
+#define TPC0_CFG_QM_TENSOR_4_DIM_2_STRIDE_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_4_DIM_3_SIZE */
+#define TPC0_CFG_QM_TENSOR_4_DIM_3_SIZE_V_SHIFT 0
+#define TPC0_CFG_QM_TENSOR_4_DIM_3_SIZE_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_4_DIM_3_STRIDE */
+#define TPC0_CFG_QM_TENSOR_4_DIM_3_STRIDE_V_SHIFT 0
+#define TPC0_CFG_QM_TENSOR_4_DIM_3_STRIDE_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_4_DIM_4_SIZE */
+#define TPC0_CFG_QM_TENSOR_4_DIM_4_SIZE_V_SHIFT 0
+#define TPC0_CFG_QM_TENSOR_4_DIM_4_SIZE_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_4_DIM_4_STRIDE */
+#define TPC0_CFG_QM_TENSOR_4_DIM_4_STRIDE_V_SHIFT 0
+#define TPC0_CFG_QM_TENSOR_4_DIM_4_STRIDE_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_5_BASE_ADDR_LOW */
+#define TPC0_CFG_QM_TENSOR_5_BASE_ADDR_LOW_V_SHIFT 0
+#define TPC0_CFG_QM_TENSOR_5_BASE_ADDR_LOW_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_5_BASE_ADDR_HIGH */
+#define TPC0_CFG_QM_TENSOR_5_BASE_ADDR_HIGH_V_SHIFT 0
+#define TPC0_CFG_QM_TENSOR_5_BASE_ADDR_HIGH_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_5_PADDING_VALUE */
+#define TPC0_CFG_QM_TENSOR_5_PADDING_VALUE_V_SHIFT 0
+#define TPC0_CFG_QM_TENSOR_5_PADDING_VALUE_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_5_TENSOR_CONFIG */
+#define TPC0_CFG_QM_TENSOR_5_TENSOR_CONFIG_DATA_TYPE_SHIFT 0
+#define TPC0_CFG_QM_TENSOR_5_TENSOR_CONFIG_DATA_TYPE_MASK 0x7
+#define TPC0_CFG_QM_TENSOR_5_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT 8
+#define TPC0_CFG_QM_TENSOR_5_TENSOR_CONFIG_VALID_DIM_MASK_MASK 0x1F00
+#define TPC0_CFG_QM_TENSOR_5_TENSOR_CONFIG_LAST_DIM_SHIFT 16
+#define TPC0_CFG_QM_TENSOR_5_TENSOR_CONFIG_LAST_DIM_MASK 0x70000
+#define TPC0_CFG_QM_TENSOR_5_TENSOR_CONFIG_RMW_SET_SHIFT 19
+#define TPC0_CFG_QM_TENSOR_5_TENSOR_CONFIG_RMW_SET_MASK 0x80000
+#define TPC0_CFG_QM_TENSOR_5_TENSOR_CONFIG_RMW_RESERV_SHIFT 20
+#define TPC0_CFG_QM_TENSOR_5_TENSOR_CONFIG_RMW_RESERV_MASK 0x100000
+#define TPC0_CFG_QM_TENSOR_5_TENSOR_CONFIG_RMW_OP_SHIFT 21
+#define TPC0_CFG_QM_TENSOR_5_TENSOR_CONFIG_RMW_OP_MASK 0x600000
+
+/* TPC0_CFG_QM_TENSOR_5_DIM_0_SIZE */
+#define TPC0_CFG_QM_TENSOR_5_DIM_0_SIZE_V_SHIFT 0
+#define TPC0_CFG_QM_TENSOR_5_DIM_0_SIZE_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_5_DIM_0_STRIDE */
+#define TPC0_CFG_QM_TENSOR_5_DIM_0_STRIDE_V_SHIFT 0
+#define TPC0_CFG_QM_TENSOR_5_DIM_0_STRIDE_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_5_DIM_1_SIZE */
+#define TPC0_CFG_QM_TENSOR_5_DIM_1_SIZE_V_SHIFT 0
+#define TPC0_CFG_QM_TENSOR_5_DIM_1_SIZE_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_5_DIM_1_STRIDE */
+#define TPC0_CFG_QM_TENSOR_5_DIM_1_STRIDE_V_SHIFT 0
+#define TPC0_CFG_QM_TENSOR_5_DIM_1_STRIDE_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_5_DIM_2_SIZE */
+#define TPC0_CFG_QM_TENSOR_5_DIM_2_SIZE_V_SHIFT 0
+#define TPC0_CFG_QM_TENSOR_5_DIM_2_SIZE_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_5_DIM_2_STRIDE */
+#define TPC0_CFG_QM_TENSOR_5_DIM_2_STRIDE_V_SHIFT 0
+#define TPC0_CFG_QM_TENSOR_5_DIM_2_STRIDE_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_5_DIM_3_SIZE */
+#define TPC0_CFG_QM_TENSOR_5_DIM_3_SIZE_V_SHIFT 0
+#define TPC0_CFG_QM_TENSOR_5_DIM_3_SIZE_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_5_DIM_3_STRIDE */
+#define TPC0_CFG_QM_TENSOR_5_DIM_3_STRIDE_V_SHIFT 0
+#define TPC0_CFG_QM_TENSOR_5_DIM_3_STRIDE_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_5_DIM_4_SIZE */
+#define TPC0_CFG_QM_TENSOR_5_DIM_4_SIZE_V_SHIFT 0
+#define TPC0_CFG_QM_TENSOR_5_DIM_4_SIZE_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_5_DIM_4_STRIDE */
+#define TPC0_CFG_QM_TENSOR_5_DIM_4_STRIDE_V_SHIFT 0
+#define TPC0_CFG_QM_TENSOR_5_DIM_4_STRIDE_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_6_BASE_ADDR_LOW */
+#define TPC0_CFG_QM_TENSOR_6_BASE_ADDR_LOW_V_SHIFT 0
+#define TPC0_CFG_QM_TENSOR_6_BASE_ADDR_LOW_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_6_BASE_ADDR_HIGH */
+#define TPC0_CFG_QM_TENSOR_6_BASE_ADDR_HIGH_V_SHIFT 0
+#define TPC0_CFG_QM_TENSOR_6_BASE_ADDR_HIGH_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_6_PADDING_VALUE */
+#define TPC0_CFG_QM_TENSOR_6_PADDING_VALUE_V_SHIFT 0
+#define TPC0_CFG_QM_TENSOR_6_PADDING_VALUE_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_6_TENSOR_CONFIG */
+#define TPC0_CFG_QM_TENSOR_6_TENSOR_CONFIG_DATA_TYPE_SHIFT 0
+#define TPC0_CFG_QM_TENSOR_6_TENSOR_CONFIG_DATA_TYPE_MASK 0x7
+#define TPC0_CFG_QM_TENSOR_6_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT 8
+#define TPC0_CFG_QM_TENSOR_6_TENSOR_CONFIG_VALID_DIM_MASK_MASK 0x1F00
+#define TPC0_CFG_QM_TENSOR_6_TENSOR_CONFIG_LAST_DIM_SHIFT 16
+#define TPC0_CFG_QM_TENSOR_6_TENSOR_CONFIG_LAST_DIM_MASK 0x70000
+#define TPC0_CFG_QM_TENSOR_6_TENSOR_CONFIG_RMW_SET_SHIFT 19
+#define TPC0_CFG_QM_TENSOR_6_TENSOR_CONFIG_RMW_SET_MASK 0x80000
+#define TPC0_CFG_QM_TENSOR_6_TENSOR_CONFIG_RMW_RESERV_SHIFT 20
+#define TPC0_CFG_QM_TENSOR_6_TENSOR_CONFIG_RMW_RESERV_MASK 0x100000
+#define TPC0_CFG_QM_TENSOR_6_TENSOR_CONFIG_RMW_OP_SHIFT 21
+#define TPC0_CFG_QM_TENSOR_6_TENSOR_CONFIG_RMW_OP_MASK 0x600000
+
+/* TPC0_CFG_QM_TENSOR_6_DIM_0_SIZE */
+#define TPC0_CFG_QM_TENSOR_6_DIM_0_SIZE_V_SHIFT 0
+#define TPC0_CFG_QM_TENSOR_6_DIM_0_SIZE_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_6_DIM_0_STRIDE */
+#define TPC0_CFG_QM_TENSOR_6_DIM_0_STRIDE_V_SHIFT 0
+#define TPC0_CFG_QM_TENSOR_6_DIM_0_STRIDE_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_6_DIM_1_SIZE */
+#define TPC0_CFG_QM_TENSOR_6_DIM_1_SIZE_V_SHIFT 0
+#define TPC0_CFG_QM_TENSOR_6_DIM_1_SIZE_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_6_DIM_1_STRIDE */
+#define TPC0_CFG_QM_TENSOR_6_DIM_1_STRIDE_V_SHIFT 0
+#define TPC0_CFG_QM_TENSOR_6_DIM_1_STRIDE_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_6_DIM_2_SIZE */
+#define TPC0_CFG_QM_TENSOR_6_DIM_2_SIZE_V_SHIFT 0
+#define TPC0_CFG_QM_TENSOR_6_DIM_2_SIZE_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_6_DIM_2_STRIDE */
+#define TPC0_CFG_QM_TENSOR_6_DIM_2_STRIDE_V_SHIFT 0
+#define TPC0_CFG_QM_TENSOR_6_DIM_2_STRIDE_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_6_DIM_3_SIZE */
+#define TPC0_CFG_QM_TENSOR_6_DIM_3_SIZE_V_SHIFT 0
+#define TPC0_CFG_QM_TENSOR_6_DIM_3_SIZE_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_6_DIM_3_STRIDE */
+#define TPC0_CFG_QM_TENSOR_6_DIM_3_STRIDE_V_SHIFT 0
+#define TPC0_CFG_QM_TENSOR_6_DIM_3_STRIDE_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_6_DIM_4_SIZE */
+#define TPC0_CFG_QM_TENSOR_6_DIM_4_SIZE_V_SHIFT 0
+#define TPC0_CFG_QM_TENSOR_6_DIM_4_SIZE_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_6_DIM_4_STRIDE */
+#define TPC0_CFG_QM_TENSOR_6_DIM_4_STRIDE_V_SHIFT 0
+#define TPC0_CFG_QM_TENSOR_6_DIM_4_STRIDE_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_7_BASE_ADDR_LOW */
+#define TPC0_CFG_QM_TENSOR_7_BASE_ADDR_LOW_V_SHIFT 0
+#define TPC0_CFG_QM_TENSOR_7_BASE_ADDR_LOW_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_7_BASE_ADDR_HIGH */
+#define TPC0_CFG_QM_TENSOR_7_BASE_ADDR_HIGH_V_SHIFT 0
+#define TPC0_CFG_QM_TENSOR_7_BASE_ADDR_HIGH_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_7_PADDING_VALUE */
+#define TPC0_CFG_QM_TENSOR_7_PADDING_VALUE_V_SHIFT 0
+#define TPC0_CFG_QM_TENSOR_7_PADDING_VALUE_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_7_TENSOR_CONFIG */
+#define TPC0_CFG_QM_TENSOR_7_TENSOR_CONFIG_DATA_TYPE_SHIFT 0
+#define TPC0_CFG_QM_TENSOR_7_TENSOR_CONFIG_DATA_TYPE_MASK 0x7
+#define TPC0_CFG_QM_TENSOR_7_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT 8
+#define TPC0_CFG_QM_TENSOR_7_TENSOR_CONFIG_VALID_DIM_MASK_MASK 0x1F00
+#define TPC0_CFG_QM_TENSOR_7_TENSOR_CONFIG_LAST_DIM_SHIFT 16
+#define TPC0_CFG_QM_TENSOR_7_TENSOR_CONFIG_LAST_DIM_MASK 0x70000
+#define TPC0_CFG_QM_TENSOR_7_TENSOR_CONFIG_RMW_SET_SHIFT 19
+#define TPC0_CFG_QM_TENSOR_7_TENSOR_CONFIG_RMW_SET_MASK 0x80000
+#define TPC0_CFG_QM_TENSOR_7_TENSOR_CONFIG_RMW_RESERV_SHIFT 20
+#define TPC0_CFG_QM_TENSOR_7_TENSOR_CONFIG_RMW_RESERV_MASK 0x100000
+#define TPC0_CFG_QM_TENSOR_7_TENSOR_CONFIG_RMW_OP_SHIFT 21
+#define TPC0_CFG_QM_TENSOR_7_TENSOR_CONFIG_RMW_OP_MASK 0x600000
+
+/* TPC0_CFG_QM_TENSOR_7_DIM_0_SIZE */
+#define TPC0_CFG_QM_TENSOR_7_DIM_0_SIZE_V_SHIFT 0
+#define TPC0_CFG_QM_TENSOR_7_DIM_0_SIZE_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_7_DIM_0_STRIDE */
+#define TPC0_CFG_QM_TENSOR_7_DIM_0_STRIDE_V_SHIFT 0
+#define TPC0_CFG_QM_TENSOR_7_DIM_0_STRIDE_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_7_DIM_1_SIZE */
+#define TPC0_CFG_QM_TENSOR_7_DIM_1_SIZE_V_SHIFT 0
+#define TPC0_CFG_QM_TENSOR_7_DIM_1_SIZE_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_7_DIM_1_STRIDE */
+#define TPC0_CFG_QM_TENSOR_7_DIM_1_STRIDE_V_SHIFT 0
+#define TPC0_CFG_QM_TENSOR_7_DIM_1_STRIDE_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_7_DIM_2_SIZE */
+#define TPC0_CFG_QM_TENSOR_7_DIM_2_SIZE_V_SHIFT 0
+#define TPC0_CFG_QM_TENSOR_7_DIM_2_SIZE_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_7_DIM_2_STRIDE */
+#define TPC0_CFG_QM_TENSOR_7_DIM_2_STRIDE_V_SHIFT 0
+#define TPC0_CFG_QM_TENSOR_7_DIM_2_STRIDE_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_7_DIM_3_SIZE */
+#define TPC0_CFG_QM_TENSOR_7_DIM_3_SIZE_V_SHIFT 0
+#define TPC0_CFG_QM_TENSOR_7_DIM_3_SIZE_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_7_DIM_3_STRIDE */
+#define TPC0_CFG_QM_TENSOR_7_DIM_3_STRIDE_V_SHIFT 0
+#define TPC0_CFG_QM_TENSOR_7_DIM_3_STRIDE_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_7_DIM_4_SIZE */
+#define TPC0_CFG_QM_TENSOR_7_DIM_4_SIZE_V_SHIFT 0
+#define TPC0_CFG_QM_TENSOR_7_DIM_4_SIZE_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_7_DIM_4_STRIDE */
+#define TPC0_CFG_QM_TENSOR_7_DIM_4_STRIDE_V_SHIFT 0
+#define TPC0_CFG_QM_TENSOR_7_DIM_4_STRIDE_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_8_BASE_ADDR_LOW */
+#define TPC0_CFG_QM_TENSOR_8_BASE_ADDR_LOW_V_SHIFT 0
+#define TPC0_CFG_QM_TENSOR_8_BASE_ADDR_LOW_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_8_BASE_ADDR_HIGH */
+#define TPC0_CFG_QM_TENSOR_8_BASE_ADDR_HIGH_V_SHIFT 0
+#define TPC0_CFG_QM_TENSOR_8_BASE_ADDR_HIGH_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_8_PADDING_VALUE */
+#define TPC0_CFG_QM_TENSOR_8_PADDING_VALUE_V_SHIFT 0
+#define TPC0_CFG_QM_TENSOR_8_PADDING_VALUE_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_8_TENSOR_CONFIG */
+#define TPC0_CFG_QM_TENSOR_8_TENSOR_CONFIG_DATA_TYPE_SHIFT 0
+#define TPC0_CFG_QM_TENSOR_8_TENSOR_CONFIG_DATA_TYPE_MASK 0x7
+#define TPC0_CFG_QM_TENSOR_8_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT 8
+#define TPC0_CFG_QM_TENSOR_8_TENSOR_CONFIG_VALID_DIM_MASK_MASK 0x1F00
+#define TPC0_CFG_QM_TENSOR_8_TENSOR_CONFIG_LAST_DIM_SHIFT 16
+#define TPC0_CFG_QM_TENSOR_8_TENSOR_CONFIG_LAST_DIM_MASK 0x70000
+#define TPC0_CFG_QM_TENSOR_8_TENSOR_CONFIG_RMW_SET_SHIFT 19
+#define TPC0_CFG_QM_TENSOR_8_TENSOR_CONFIG_RMW_SET_MASK 0x80000
+#define TPC0_CFG_QM_TENSOR_8_TENSOR_CONFIG_RMW_RESERV_SHIFT 20
+#define TPC0_CFG_QM_TENSOR_8_TENSOR_CONFIG_RMW_RESERV_MASK 0x100000
+#define TPC0_CFG_QM_TENSOR_8_TENSOR_CONFIG_RMW_OP_SHIFT 21
+#define TPC0_CFG_QM_TENSOR_8_TENSOR_CONFIG_RMW_OP_MASK 0x600000
+
+/* TPC0_CFG_QM_TENSOR_8_DIM_0_SIZE */
+#define TPC0_CFG_QM_TENSOR_8_DIM_0_SIZE_V_SHIFT 0
+#define TPC0_CFG_QM_TENSOR_8_DIM_0_SIZE_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_8_DIM_0_STRIDE */
+#define TPC0_CFG_QM_TENSOR_8_DIM_0_STRIDE_V_SHIFT 0
+#define TPC0_CFG_QM_TENSOR_8_DIM_0_STRIDE_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_8_DIM_1_SIZE */
+#define TPC0_CFG_QM_TENSOR_8_DIM_1_SIZE_V_SHIFT 0
+#define TPC0_CFG_QM_TENSOR_8_DIM_1_SIZE_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_8_DIM_1_STRIDE */
+#define TPC0_CFG_QM_TENSOR_8_DIM_1_STRIDE_V_SHIFT 0
+#define TPC0_CFG_QM_TENSOR_8_DIM_1_STRIDE_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_8_DIM_2_SIZE */
+#define TPC0_CFG_QM_TENSOR_8_DIM_2_SIZE_V_SHIFT 0
+#define TPC0_CFG_QM_TENSOR_8_DIM_2_SIZE_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_8_DIM_2_STRIDE */
+#define TPC0_CFG_QM_TENSOR_8_DIM_2_STRIDE_V_SHIFT 0
+#define TPC0_CFG_QM_TENSOR_8_DIM_2_STRIDE_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_8_DIM_3_SIZE */
+#define TPC0_CFG_QM_TENSOR_8_DIM_3_SIZE_V_SHIFT 0
+#define TPC0_CFG_QM_TENSOR_8_DIM_3_SIZE_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_8_DIM_3_STRIDE */
+#define TPC0_CFG_QM_TENSOR_8_DIM_3_STRIDE_V_SHIFT 0
+#define TPC0_CFG_QM_TENSOR_8_DIM_3_STRIDE_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_8_DIM_4_SIZE */
+#define TPC0_CFG_QM_TENSOR_8_DIM_4_SIZE_V_SHIFT 0
+#define TPC0_CFG_QM_TENSOR_8_DIM_4_SIZE_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_8_DIM_4_STRIDE */
+#define TPC0_CFG_QM_TENSOR_8_DIM_4_STRIDE_V_SHIFT 0
+#define TPC0_CFG_QM_TENSOR_8_DIM_4_STRIDE_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_9_BASE_ADDR_LOW */
+#define TPC0_CFG_QM_TENSOR_9_BASE_ADDR_LOW_V_SHIFT 0
+#define TPC0_CFG_QM_TENSOR_9_BASE_ADDR_LOW_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_9_BASE_ADDR_HIGH */
+#define TPC0_CFG_QM_TENSOR_9_BASE_ADDR_HIGH_V_SHIFT 0
+#define TPC0_CFG_QM_TENSOR_9_BASE_ADDR_HIGH_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_9_PADDING_VALUE */
+#define TPC0_CFG_QM_TENSOR_9_PADDING_VALUE_V_SHIFT 0
+#define TPC0_CFG_QM_TENSOR_9_PADDING_VALUE_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_9_TENSOR_CONFIG */
+#define TPC0_CFG_QM_TENSOR_9_TENSOR_CONFIG_DATA_TYPE_SHIFT 0
+#define TPC0_CFG_QM_TENSOR_9_TENSOR_CONFIG_DATA_TYPE_MASK 0x7
+#define TPC0_CFG_QM_TENSOR_9_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT 8
+#define TPC0_CFG_QM_TENSOR_9_TENSOR_CONFIG_VALID_DIM_MASK_MASK 0x1F00
+#define TPC0_CFG_QM_TENSOR_9_TENSOR_CONFIG_LAST_DIM_SHIFT 16
+#define TPC0_CFG_QM_TENSOR_9_TENSOR_CONFIG_LAST_DIM_MASK 0x70000
+#define TPC0_CFG_QM_TENSOR_9_TENSOR_CONFIG_RMW_SET_SHIFT 19
+#define TPC0_CFG_QM_TENSOR_9_TENSOR_CONFIG_RMW_SET_MASK 0x80000
+#define TPC0_CFG_QM_TENSOR_9_TENSOR_CONFIG_RMW_RESERV_SHIFT 20
+#define TPC0_CFG_QM_TENSOR_9_TENSOR_CONFIG_RMW_RESERV_MASK 0x100000
+#define TPC0_CFG_QM_TENSOR_9_TENSOR_CONFIG_RMW_OP_SHIFT 21
+#define TPC0_CFG_QM_TENSOR_9_TENSOR_CONFIG_RMW_OP_MASK 0x600000
+
+/* TPC0_CFG_QM_TENSOR_9_DIM_0_SIZE */
+#define TPC0_CFG_QM_TENSOR_9_DIM_0_SIZE_V_SHIFT 0
+#define TPC0_CFG_QM_TENSOR_9_DIM_0_SIZE_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_9_DIM_0_STRIDE */
+#define TPC0_CFG_QM_TENSOR_9_DIM_0_STRIDE_V_SHIFT 0
+#define TPC0_CFG_QM_TENSOR_9_DIM_0_STRIDE_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_9_DIM_1_SIZE */
+#define TPC0_CFG_QM_TENSOR_9_DIM_1_SIZE_V_SHIFT 0
+#define TPC0_CFG_QM_TENSOR_9_DIM_1_SIZE_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_9_DIM_1_STRIDE */
+#define TPC0_CFG_QM_TENSOR_9_DIM_1_STRIDE_V_SHIFT 0
+#define TPC0_CFG_QM_TENSOR_9_DIM_1_STRIDE_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_9_DIM_2_SIZE */
+#define TPC0_CFG_QM_TENSOR_9_DIM_2_SIZE_V_SHIFT 0
+#define TPC0_CFG_QM_TENSOR_9_DIM_2_SIZE_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_9_DIM_2_STRIDE */
+#define TPC0_CFG_QM_TENSOR_9_DIM_2_STRIDE_V_SHIFT 0
+#define TPC0_CFG_QM_TENSOR_9_DIM_2_STRIDE_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_9_DIM_3_SIZE */
+#define TPC0_CFG_QM_TENSOR_9_DIM_3_SIZE_V_SHIFT 0
+#define TPC0_CFG_QM_TENSOR_9_DIM_3_SIZE_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_9_DIM_3_STRIDE */
+#define TPC0_CFG_QM_TENSOR_9_DIM_3_STRIDE_V_SHIFT 0
+#define TPC0_CFG_QM_TENSOR_9_DIM_3_STRIDE_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_9_DIM_4_SIZE */
+#define TPC0_CFG_QM_TENSOR_9_DIM_4_SIZE_V_SHIFT 0
+#define TPC0_CFG_QM_TENSOR_9_DIM_4_SIZE_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_9_DIM_4_STRIDE */
+#define TPC0_CFG_QM_TENSOR_9_DIM_4_STRIDE_V_SHIFT 0
+#define TPC0_CFG_QM_TENSOR_9_DIM_4_STRIDE_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_10_BASE_ADDR_LOW */
+#define TPC0_CFG_QM_TENSOR_10_BASE_ADDR_LOW_V_SHIFT 0
+#define TPC0_CFG_QM_TENSOR_10_BASE_ADDR_LOW_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_10_BASE_ADDR_HIGH */
+#define TPC0_CFG_QM_TENSOR_10_BASE_ADDR_HIGH_V_SHIFT 0
+#define TPC0_CFG_QM_TENSOR_10_BASE_ADDR_HIGH_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_10_PADDING_VALUE */
+#define TPC0_CFG_QM_TENSOR_10_PADDING_VALUE_V_SHIFT 0
+#define TPC0_CFG_QM_TENSOR_10_PADDING_VALUE_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_10_TENSOR_CONFIG */
+#define TPC0_CFG_QM_TENSOR_10_TENSOR_CONFIG_DATA_TYPE_SHIFT 0
+#define TPC0_CFG_QM_TENSOR_10_TENSOR_CONFIG_DATA_TYPE_MASK 0x7
+#define TPC0_CFG_QM_TENSOR_10_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT 8
+#define TPC0_CFG_QM_TENSOR_10_TENSOR_CONFIG_VALID_DIM_MASK_MASK 0x1F00
+#define TPC0_CFG_QM_TENSOR_10_TENSOR_CONFIG_LAST_DIM_SHIFT 16
+#define TPC0_CFG_QM_TENSOR_10_TENSOR_CONFIG_LAST_DIM_MASK 0x70000
+#define TPC0_CFG_QM_TENSOR_10_TENSOR_CONFIG_RMW_SET_SHIFT 19
+#define TPC0_CFG_QM_TENSOR_10_TENSOR_CONFIG_RMW_SET_MASK 0x80000
+#define TPC0_CFG_QM_TENSOR_10_TENSOR_CONFIG_RMW_RESERV_SHIFT 20
+#define TPC0_CFG_QM_TENSOR_10_TENSOR_CONFIG_RMW_RESERV_MASK 0x100000
+#define TPC0_CFG_QM_TENSOR_10_TENSOR_CONFIG_RMW_OP_SHIFT 21
+#define TPC0_CFG_QM_TENSOR_10_TENSOR_CONFIG_RMW_OP_MASK 0x600000
+
+/* TPC0_CFG_QM_TENSOR_10_DIM_0_SIZE */
+#define TPC0_CFG_QM_TENSOR_10_DIM_0_SIZE_V_SHIFT 0
+#define TPC0_CFG_QM_TENSOR_10_DIM_0_SIZE_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_10_DIM_0_STRIDE */
+#define TPC0_CFG_QM_TENSOR_10_DIM_0_STRIDE_V_SHIFT 0
+#define TPC0_CFG_QM_TENSOR_10_DIM_0_STRIDE_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_10_DIM_1_SIZE */
+#define TPC0_CFG_QM_TENSOR_10_DIM_1_SIZE_V_SHIFT 0
+#define TPC0_CFG_QM_TENSOR_10_DIM_1_SIZE_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_10_DIM_1_STRIDE */
+#define TPC0_CFG_QM_TENSOR_10_DIM_1_STRIDE_V_SHIFT 0
+#define TPC0_CFG_QM_TENSOR_10_DIM_1_STRIDE_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_10_DIM_2_SIZE */
+#define TPC0_CFG_QM_TENSOR_10_DIM_2_SIZE_V_SHIFT 0
+#define TPC0_CFG_QM_TENSOR_10_DIM_2_SIZE_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_10_DIM_2_STRIDE */
+#define TPC0_CFG_QM_TENSOR_10_DIM_2_STRIDE_V_SHIFT 0
+#define TPC0_CFG_QM_TENSOR_10_DIM_2_STRIDE_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_10_DIM_3_SIZE */
+#define TPC0_CFG_QM_TENSOR_10_DIM_3_SIZE_V_SHIFT 0
+#define TPC0_CFG_QM_TENSOR_10_DIM_3_SIZE_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_10_DIM_3_STRIDE */
+#define TPC0_CFG_QM_TENSOR_10_DIM_3_STRIDE_V_SHIFT 0
+#define TPC0_CFG_QM_TENSOR_10_DIM_3_STRIDE_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_10_DIM_4_SIZE */
+#define TPC0_CFG_QM_TENSOR_10_DIM_4_SIZE_V_SHIFT 0
+#define TPC0_CFG_QM_TENSOR_10_DIM_4_SIZE_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_10_DIM_4_STRIDE */
+#define TPC0_CFG_QM_TENSOR_10_DIM_4_STRIDE_V_SHIFT 0
+#define TPC0_CFG_QM_TENSOR_10_DIM_4_STRIDE_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_11_BASE_ADDR_LOW */
+#define TPC0_CFG_QM_TENSOR_11_BASE_ADDR_LOW_V_SHIFT 0
+#define TPC0_CFG_QM_TENSOR_11_BASE_ADDR_LOW_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_11_BASE_ADDR_HIGH */
+#define TPC0_CFG_QM_TENSOR_11_BASE_ADDR_HIGH_V_SHIFT 0
+#define TPC0_CFG_QM_TENSOR_11_BASE_ADDR_HIGH_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_11_PADDING_VALUE */
+#define TPC0_CFG_QM_TENSOR_11_PADDING_VALUE_V_SHIFT 0
+#define TPC0_CFG_QM_TENSOR_11_PADDING_VALUE_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_11_TENSOR_CONFIG */
+#define TPC0_CFG_QM_TENSOR_11_TENSOR_CONFIG_DATA_TYPE_SHIFT 0
+#define TPC0_CFG_QM_TENSOR_11_TENSOR_CONFIG_DATA_TYPE_MASK 0x7
+#define TPC0_CFG_QM_TENSOR_11_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT 8
+#define TPC0_CFG_QM_TENSOR_11_TENSOR_CONFIG_VALID_DIM_MASK_MASK 0x1F00
+#define TPC0_CFG_QM_TENSOR_11_TENSOR_CONFIG_LAST_DIM_SHIFT 16
+#define TPC0_CFG_QM_TENSOR_11_TENSOR_CONFIG_LAST_DIM_MASK 0x70000
+#define TPC0_CFG_QM_TENSOR_11_TENSOR_CONFIG_RMW_SET_SHIFT 19
+#define TPC0_CFG_QM_TENSOR_11_TENSOR_CONFIG_RMW_SET_MASK 0x80000
+#define TPC0_CFG_QM_TENSOR_11_TENSOR_CONFIG_RMW_RESERV_SHIFT 20
+#define TPC0_CFG_QM_TENSOR_11_TENSOR_CONFIG_RMW_RESERV_MASK 0x100000
+#define TPC0_CFG_QM_TENSOR_11_TENSOR_CONFIG_RMW_OP_SHIFT 21
+#define TPC0_CFG_QM_TENSOR_11_TENSOR_CONFIG_RMW_OP_MASK 0x600000
+
+/* TPC0_CFG_QM_TENSOR_11_DIM_0_SIZE */
+#define TPC0_CFG_QM_TENSOR_11_DIM_0_SIZE_V_SHIFT 0
+#define TPC0_CFG_QM_TENSOR_11_DIM_0_SIZE_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_11_DIM_0_STRIDE */
+#define TPC0_CFG_QM_TENSOR_11_DIM_0_STRIDE_V_SHIFT 0
+#define TPC0_CFG_QM_TENSOR_11_DIM_0_STRIDE_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_11_DIM_1_SIZE */
+#define TPC0_CFG_QM_TENSOR_11_DIM_1_SIZE_V_SHIFT 0
+#define TPC0_CFG_QM_TENSOR_11_DIM_1_SIZE_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_11_DIM_1_STRIDE */
+#define TPC0_CFG_QM_TENSOR_11_DIM_1_STRIDE_V_SHIFT 0
+#define TPC0_CFG_QM_TENSOR_11_DIM_1_STRIDE_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_11_DIM_2_SIZE */
+#define TPC0_CFG_QM_TENSOR_11_DIM_2_SIZE_V_SHIFT 0
+#define TPC0_CFG_QM_TENSOR_11_DIM_2_SIZE_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_11_DIM_2_STRIDE */
+#define TPC0_CFG_QM_TENSOR_11_DIM_2_STRIDE_V_SHIFT 0
+#define TPC0_CFG_QM_TENSOR_11_DIM_2_STRIDE_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_11_DIM_3_SIZE */
+#define TPC0_CFG_QM_TENSOR_11_DIM_3_SIZE_V_SHIFT 0
+#define TPC0_CFG_QM_TENSOR_11_DIM_3_SIZE_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_11_DIM_3_STRIDE */
+#define TPC0_CFG_QM_TENSOR_11_DIM_3_STRIDE_V_SHIFT 0
+#define TPC0_CFG_QM_TENSOR_11_DIM_3_STRIDE_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_11_DIM_4_SIZE */
+#define TPC0_CFG_QM_TENSOR_11_DIM_4_SIZE_V_SHIFT 0
+#define TPC0_CFG_QM_TENSOR_11_DIM_4_SIZE_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_11_DIM_4_STRIDE */
+#define TPC0_CFG_QM_TENSOR_11_DIM_4_STRIDE_V_SHIFT 0
+#define TPC0_CFG_QM_TENSOR_11_DIM_4_STRIDE_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_12_BASE_ADDR_LOW */
+#define TPC0_CFG_QM_TENSOR_12_BASE_ADDR_LOW_V_SHIFT 0
+#define TPC0_CFG_QM_TENSOR_12_BASE_ADDR_LOW_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_12_BASE_ADDR_HIGH */
+#define TPC0_CFG_QM_TENSOR_12_BASE_ADDR_HIGH_V_SHIFT 0
+#define TPC0_CFG_QM_TENSOR_12_BASE_ADDR_HIGH_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_12_PADDING_VALUE */
+#define TPC0_CFG_QM_TENSOR_12_PADDING_VALUE_V_SHIFT 0
+#define TPC0_CFG_QM_TENSOR_12_PADDING_VALUE_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_12_TENSOR_CONFIG */
+#define TPC0_CFG_QM_TENSOR_12_TENSOR_CONFIG_DATA_TYPE_SHIFT 0
+#define TPC0_CFG_QM_TENSOR_12_TENSOR_CONFIG_DATA_TYPE_MASK 0x7
+#define TPC0_CFG_QM_TENSOR_12_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT 8
+#define TPC0_CFG_QM_TENSOR_12_TENSOR_CONFIG_VALID_DIM_MASK_MASK 0x1F00
+#define TPC0_CFG_QM_TENSOR_12_TENSOR_CONFIG_LAST_DIM_SHIFT 16
+#define TPC0_CFG_QM_TENSOR_12_TENSOR_CONFIG_LAST_DIM_MASK 0x70000
+#define TPC0_CFG_QM_TENSOR_12_TENSOR_CONFIG_RMW_SET_SHIFT 19
+#define TPC0_CFG_QM_TENSOR_12_TENSOR_CONFIG_RMW_SET_MASK 0x80000
+#define TPC0_CFG_QM_TENSOR_12_TENSOR_CONFIG_RMW_RESERV_SHIFT 20
+#define TPC0_CFG_QM_TENSOR_12_TENSOR_CONFIG_RMW_RESERV_MASK 0x100000
+#define TPC0_CFG_QM_TENSOR_12_TENSOR_CONFIG_RMW_OP_SHIFT 21
+#define TPC0_CFG_QM_TENSOR_12_TENSOR_CONFIG_RMW_OP_MASK 0x600000
+
+/* TPC0_CFG_QM_TENSOR_12_DIM_0_SIZE */
+#define TPC0_CFG_QM_TENSOR_12_DIM_0_SIZE_V_SHIFT 0
+#define TPC0_CFG_QM_TENSOR_12_DIM_0_SIZE_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_12_DIM_0_STRIDE */
+#define TPC0_CFG_QM_TENSOR_12_DIM_0_STRIDE_V_SHIFT 0
+#define TPC0_CFG_QM_TENSOR_12_DIM_0_STRIDE_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_12_DIM_1_SIZE */
+#define TPC0_CFG_QM_TENSOR_12_DIM_1_SIZE_V_SHIFT 0
+#define TPC0_CFG_QM_TENSOR_12_DIM_1_SIZE_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_12_DIM_1_STRIDE */
+#define TPC0_CFG_QM_TENSOR_12_DIM_1_STRIDE_V_SHIFT 0
+#define TPC0_CFG_QM_TENSOR_12_DIM_1_STRIDE_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_12_DIM_2_SIZE */
+#define TPC0_CFG_QM_TENSOR_12_DIM_2_SIZE_V_SHIFT 0
+#define TPC0_CFG_QM_TENSOR_12_DIM_2_SIZE_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_12_DIM_2_STRIDE */
+#define TPC0_CFG_QM_TENSOR_12_DIM_2_STRIDE_V_SHIFT 0
+#define TPC0_CFG_QM_TENSOR_12_DIM_2_STRIDE_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_12_DIM_3_SIZE */
+#define TPC0_CFG_QM_TENSOR_12_DIM_3_SIZE_V_SHIFT 0
+#define TPC0_CFG_QM_TENSOR_12_DIM_3_SIZE_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_12_DIM_3_STRIDE */
+#define TPC0_CFG_QM_TENSOR_12_DIM_3_STRIDE_V_SHIFT 0
+#define TPC0_CFG_QM_TENSOR_12_DIM_3_STRIDE_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_12_DIM_4_SIZE */
+#define TPC0_CFG_QM_TENSOR_12_DIM_4_SIZE_V_SHIFT 0
+#define TPC0_CFG_QM_TENSOR_12_DIM_4_SIZE_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_12_DIM_4_STRIDE */
+#define TPC0_CFG_QM_TENSOR_12_DIM_4_STRIDE_V_SHIFT 0
+#define TPC0_CFG_QM_TENSOR_12_DIM_4_STRIDE_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_13_BASE_ADDR_LOW */
+#define TPC0_CFG_QM_TENSOR_13_BASE_ADDR_LOW_V_SHIFT 0
+#define TPC0_CFG_QM_TENSOR_13_BASE_ADDR_LOW_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_13_BASE_ADDR_HIGH */
+#define TPC0_CFG_QM_TENSOR_13_BASE_ADDR_HIGH_V_SHIFT 0
+#define TPC0_CFG_QM_TENSOR_13_BASE_ADDR_HIGH_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_13_PADDING_VALUE */
+#define TPC0_CFG_QM_TENSOR_13_PADDING_VALUE_V_SHIFT 0
+#define TPC0_CFG_QM_TENSOR_13_PADDING_VALUE_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_13_TENSOR_CONFIG */
+#define TPC0_CFG_QM_TENSOR_13_TENSOR_CONFIG_DATA_TYPE_SHIFT 0
+#define TPC0_CFG_QM_TENSOR_13_TENSOR_CONFIG_DATA_TYPE_MASK 0x7
+#define TPC0_CFG_QM_TENSOR_13_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT 8
+#define TPC0_CFG_QM_TENSOR_13_TENSOR_CONFIG_VALID_DIM_MASK_MASK 0x1F00
+#define TPC0_CFG_QM_TENSOR_13_TENSOR_CONFIG_LAST_DIM_SHIFT 16
+#define TPC0_CFG_QM_TENSOR_13_TENSOR_CONFIG_LAST_DIM_MASK 0x70000
+#define TPC0_CFG_QM_TENSOR_13_TENSOR_CONFIG_RMW_SET_SHIFT 19
+#define TPC0_CFG_QM_TENSOR_13_TENSOR_CONFIG_RMW_SET_MASK 0x80000
+#define TPC0_CFG_QM_TENSOR_13_TENSOR_CONFIG_RMW_RESERV_SHIFT 20
+#define TPC0_CFG_QM_TENSOR_13_TENSOR_CONFIG_RMW_RESERV_MASK 0x100000
+#define TPC0_CFG_QM_TENSOR_13_TENSOR_CONFIG_RMW_OP_SHIFT 21
+#define TPC0_CFG_QM_TENSOR_13_TENSOR_CONFIG_RMW_OP_MASK 0x600000
+
+/* TPC0_CFG_QM_TENSOR_13_DIM_0_SIZE */
+#define TPC0_CFG_QM_TENSOR_13_DIM_0_SIZE_V_SHIFT 0
+#define TPC0_CFG_QM_TENSOR_13_DIM_0_SIZE_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_13_DIM_0_STRIDE */
+#define TPC0_CFG_QM_TENSOR_13_DIM_0_STRIDE_V_SHIFT 0
+#define TPC0_CFG_QM_TENSOR_13_DIM_0_STRIDE_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_13_DIM_1_SIZE */
+#define TPC0_CFG_QM_TENSOR_13_DIM_1_SIZE_V_SHIFT 0
+#define TPC0_CFG_QM_TENSOR_13_DIM_1_SIZE_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_13_DIM_1_STRIDE */
+#define TPC0_CFG_QM_TENSOR_13_DIM_1_STRIDE_V_SHIFT 0
+#define TPC0_CFG_QM_TENSOR_13_DIM_1_STRIDE_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_13_DIM_2_SIZE */
+#define TPC0_CFG_QM_TENSOR_13_DIM_2_SIZE_V_SHIFT 0
+#define TPC0_CFG_QM_TENSOR_13_DIM_2_SIZE_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_13_DIM_2_STRIDE */
+#define TPC0_CFG_QM_TENSOR_13_DIM_2_STRIDE_V_SHIFT 0
+#define TPC0_CFG_QM_TENSOR_13_DIM_2_STRIDE_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_13_DIM_3_SIZE */
+#define TPC0_CFG_QM_TENSOR_13_DIM_3_SIZE_V_SHIFT 0
+#define TPC0_CFG_QM_TENSOR_13_DIM_3_SIZE_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_13_DIM_3_STRIDE */
+#define TPC0_CFG_QM_TENSOR_13_DIM_3_STRIDE_V_SHIFT 0
+#define TPC0_CFG_QM_TENSOR_13_DIM_3_STRIDE_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_13_DIM_4_SIZE */
+#define TPC0_CFG_QM_TENSOR_13_DIM_4_SIZE_V_SHIFT 0
+#define TPC0_CFG_QM_TENSOR_13_DIM_4_SIZE_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_13_DIM_4_STRIDE */
+#define TPC0_CFG_QM_TENSOR_13_DIM_4_STRIDE_V_SHIFT 0
+#define TPC0_CFG_QM_TENSOR_13_DIM_4_STRIDE_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_14_BASE_ADDR_LOW */
+#define TPC0_CFG_QM_TENSOR_14_BASE_ADDR_LOW_V_SHIFT 0
+#define TPC0_CFG_QM_TENSOR_14_BASE_ADDR_LOW_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_14_BASE_ADDR_HIGH */
+#define TPC0_CFG_QM_TENSOR_14_BASE_ADDR_HIGH_V_SHIFT 0
+#define TPC0_CFG_QM_TENSOR_14_BASE_ADDR_HIGH_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_14_PADDING_VALUE */
+#define TPC0_CFG_QM_TENSOR_14_PADDING_VALUE_V_SHIFT 0
+#define TPC0_CFG_QM_TENSOR_14_PADDING_VALUE_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_14_TENSOR_CONFIG */
+#define TPC0_CFG_QM_TENSOR_14_TENSOR_CONFIG_DATA_TYPE_SHIFT 0
+#define TPC0_CFG_QM_TENSOR_14_TENSOR_CONFIG_DATA_TYPE_MASK 0x7
+#define TPC0_CFG_QM_TENSOR_14_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT 8
+#define TPC0_CFG_QM_TENSOR_14_TENSOR_CONFIG_VALID_DIM_MASK_MASK 0x1F00
+#define TPC0_CFG_QM_TENSOR_14_TENSOR_CONFIG_LAST_DIM_SHIFT 16
+#define TPC0_CFG_QM_TENSOR_14_TENSOR_CONFIG_LAST_DIM_MASK 0x70000
+#define TPC0_CFG_QM_TENSOR_14_TENSOR_CONFIG_RMW_SET_SHIFT 19
+#define TPC0_CFG_QM_TENSOR_14_TENSOR_CONFIG_RMW_SET_MASK 0x80000
+#define TPC0_CFG_QM_TENSOR_14_TENSOR_CONFIG_RMW_RESERV_SHIFT 20
+#define TPC0_CFG_QM_TENSOR_14_TENSOR_CONFIG_RMW_RESERV_MASK 0x100000
+#define TPC0_CFG_QM_TENSOR_14_TENSOR_CONFIG_RMW_OP_SHIFT 21
+#define TPC0_CFG_QM_TENSOR_14_TENSOR_CONFIG_RMW_OP_MASK 0x600000
+
+/* TPC0_CFG_QM_TENSOR_14_DIM_0_SIZE */
+#define TPC0_CFG_QM_TENSOR_14_DIM_0_SIZE_V_SHIFT 0
+#define TPC0_CFG_QM_TENSOR_14_DIM_0_SIZE_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_14_DIM_0_STRIDE */
+#define TPC0_CFG_QM_TENSOR_14_DIM_0_STRIDE_V_SHIFT 0
+#define TPC0_CFG_QM_TENSOR_14_DIM_0_STRIDE_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_14_DIM_1_SIZE */
+#define TPC0_CFG_QM_TENSOR_14_DIM_1_SIZE_V_SHIFT 0
+#define TPC0_CFG_QM_TENSOR_14_DIM_1_SIZE_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_14_DIM_1_STRIDE */
+#define TPC0_CFG_QM_TENSOR_14_DIM_1_STRIDE_V_SHIFT 0
+#define TPC0_CFG_QM_TENSOR_14_DIM_1_STRIDE_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_14_DIM_2_SIZE */
+#define TPC0_CFG_QM_TENSOR_14_DIM_2_SIZE_V_SHIFT 0
+#define TPC0_CFG_QM_TENSOR_14_DIM_2_SIZE_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_14_DIM_2_STRIDE */
+#define TPC0_CFG_QM_TENSOR_14_DIM_2_STRIDE_V_SHIFT 0
+#define TPC0_CFG_QM_TENSOR_14_DIM_2_STRIDE_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_14_DIM_3_SIZE */
+#define TPC0_CFG_QM_TENSOR_14_DIM_3_SIZE_V_SHIFT 0
+#define TPC0_CFG_QM_TENSOR_14_DIM_3_SIZE_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_14_DIM_3_STRIDE */
+#define TPC0_CFG_QM_TENSOR_14_DIM_3_STRIDE_V_SHIFT 0
+#define TPC0_CFG_QM_TENSOR_14_DIM_3_STRIDE_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_14_DIM_4_SIZE */
+#define TPC0_CFG_QM_TENSOR_14_DIM_4_SIZE_V_SHIFT 0
+#define TPC0_CFG_QM_TENSOR_14_DIM_4_SIZE_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_14_DIM_4_STRIDE */
+#define TPC0_CFG_QM_TENSOR_14_DIM_4_STRIDE_V_SHIFT 0
+#define TPC0_CFG_QM_TENSOR_14_DIM_4_STRIDE_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_15_BASE_ADDR_LOW */
+#define TPC0_CFG_QM_TENSOR_15_BASE_ADDR_LOW_V_SHIFT 0
+#define TPC0_CFG_QM_TENSOR_15_BASE_ADDR_LOW_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_15_BASE_ADDR_HIGH */
+#define TPC0_CFG_QM_TENSOR_15_BASE_ADDR_HIGH_V_SHIFT 0
+#define TPC0_CFG_QM_TENSOR_15_BASE_ADDR_HIGH_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_15_PADDING_VALUE */
+#define TPC0_CFG_QM_TENSOR_15_PADDING_VALUE_V_SHIFT 0
+#define TPC0_CFG_QM_TENSOR_15_PADDING_VALUE_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_15_TENSOR_CONFIG */
+#define TPC0_CFG_QM_TENSOR_15_TENSOR_CONFIG_DATA_TYPE_SHIFT 0
+#define TPC0_CFG_QM_TENSOR_15_TENSOR_CONFIG_DATA_TYPE_MASK 0x7
+#define TPC0_CFG_QM_TENSOR_15_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT 8
+#define TPC0_CFG_QM_TENSOR_15_TENSOR_CONFIG_VALID_DIM_MASK_MASK 0x1F00
+#define TPC0_CFG_QM_TENSOR_15_TENSOR_CONFIG_LAST_DIM_SHIFT 16
+#define TPC0_CFG_QM_TENSOR_15_TENSOR_CONFIG_LAST_DIM_MASK 0x70000
+#define TPC0_CFG_QM_TENSOR_15_TENSOR_CONFIG_RMW_SET_SHIFT 19
+#define TPC0_CFG_QM_TENSOR_15_TENSOR_CONFIG_RMW_SET_MASK 0x80000
+#define TPC0_CFG_QM_TENSOR_15_TENSOR_CONFIG_RMW_RESERV_SHIFT 20
+#define TPC0_CFG_QM_TENSOR_15_TENSOR_CONFIG_RMW_RESERV_MASK 0x100000
+#define TPC0_CFG_QM_TENSOR_15_TENSOR_CONFIG_RMW_OP_SHIFT 21
+#define TPC0_CFG_QM_TENSOR_15_TENSOR_CONFIG_RMW_OP_MASK 0x600000
+
+/* TPC0_CFG_QM_TENSOR_15_DIM_0_SIZE */
+#define TPC0_CFG_QM_TENSOR_15_DIM_0_SIZE_V_SHIFT 0
+#define TPC0_CFG_QM_TENSOR_15_DIM_0_SIZE_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_15_DIM_0_STRIDE */
+#define TPC0_CFG_QM_TENSOR_15_DIM_0_STRIDE_V_SHIFT 0
+#define TPC0_CFG_QM_TENSOR_15_DIM_0_STRIDE_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_15_DIM_1_SIZE */
+#define TPC0_CFG_QM_TENSOR_15_DIM_1_SIZE_V_SHIFT 0
+#define TPC0_CFG_QM_TENSOR_15_DIM_1_SIZE_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_15_DIM_1_STRIDE */
+#define TPC0_CFG_QM_TENSOR_15_DIM_1_STRIDE_V_SHIFT 0
+#define TPC0_CFG_QM_TENSOR_15_DIM_1_STRIDE_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_15_DIM_2_SIZE */
+#define TPC0_CFG_QM_TENSOR_15_DIM_2_SIZE_V_SHIFT 0
+#define TPC0_CFG_QM_TENSOR_15_DIM_2_SIZE_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_15_DIM_2_STRIDE */
+#define TPC0_CFG_QM_TENSOR_15_DIM_2_STRIDE_V_SHIFT 0
+#define TPC0_CFG_QM_TENSOR_15_DIM_2_STRIDE_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_15_DIM_3_SIZE */
+#define TPC0_CFG_QM_TENSOR_15_DIM_3_SIZE_V_SHIFT 0
+#define TPC0_CFG_QM_TENSOR_15_DIM_3_SIZE_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_15_DIM_3_STRIDE */
+#define TPC0_CFG_QM_TENSOR_15_DIM_3_STRIDE_V_SHIFT 0
+#define TPC0_CFG_QM_TENSOR_15_DIM_3_STRIDE_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_15_DIM_4_SIZE */
+#define TPC0_CFG_QM_TENSOR_15_DIM_4_SIZE_V_SHIFT 0
+#define TPC0_CFG_QM_TENSOR_15_DIM_4_SIZE_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_QM_TENSOR_15_DIM_4_STRIDE */
+#define TPC0_CFG_QM_TENSOR_15_DIM_4_STRIDE_V_SHIFT 0
+#define TPC0_CFG_QM_TENSOR_15_DIM_4_STRIDE_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_QM_SYNC_OBJECT_MESSAGE */
+#define TPC0_CFG_QM_SYNC_OBJECT_MESSAGE_SO_WRITE_VALUE_SHIFT 0
+#define TPC0_CFG_QM_SYNC_OBJECT_MESSAGE_SO_WRITE_VALUE_MASK 0xFFFF
+#define TPC0_CFG_QM_SYNC_OBJECT_MESSAGE_RSV_SHIFT 16
+#define TPC0_CFG_QM_SYNC_OBJECT_MESSAGE_RSV_MASK 0x1FFF0000
+#define TPC0_CFG_QM_SYNC_OBJECT_MESSAGE_SO_OPERATION_SHIFT 29
+#define TPC0_CFG_QM_SYNC_OBJECT_MESSAGE_SO_OPERATION_MASK 0xE0000000
+
+/* TPC0_CFG_QM_SYNC_OBJECT_ADDR */
+#define TPC0_CFG_QM_SYNC_OBJECT_ADDR_V_SHIFT 0
+#define TPC0_CFG_QM_SYNC_OBJECT_ADDR_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_QM_KERNEL_BASE_ADDRESS_LOW */
+#define TPC0_CFG_QM_KERNEL_BASE_ADDRESS_LOW_V_SHIFT 0
+#define TPC0_CFG_QM_KERNEL_BASE_ADDRESS_LOW_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_QM_KERNEL_BASE_ADDRESS_HIGH */
+#define TPC0_CFG_QM_KERNEL_BASE_ADDRESS_HIGH_V_SHIFT 0
+#define TPC0_CFG_QM_KERNEL_BASE_ADDRESS_HIGH_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_QM_TID_BASE_DIM_0 */
+#define TPC0_CFG_QM_TID_BASE_DIM_0_V_SHIFT 0
+#define TPC0_CFG_QM_TID_BASE_DIM_0_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_QM_TID_SIZE_DIM_0 */
+#define TPC0_CFG_QM_TID_SIZE_DIM_0_V_SHIFT 0
+#define TPC0_CFG_QM_TID_SIZE_DIM_0_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_QM_TID_BASE_DIM_1 */
+#define TPC0_CFG_QM_TID_BASE_DIM_1_V_SHIFT 0
+#define TPC0_CFG_QM_TID_BASE_DIM_1_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_QM_TID_SIZE_DIM_1 */
+#define TPC0_CFG_QM_TID_SIZE_DIM_1_V_SHIFT 0
+#define TPC0_CFG_QM_TID_SIZE_DIM_1_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_QM_TID_BASE_DIM_2 */
+#define TPC0_CFG_QM_TID_BASE_DIM_2_V_SHIFT 0
+#define TPC0_CFG_QM_TID_BASE_DIM_2_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_QM_TID_SIZE_DIM_2 */
+#define TPC0_CFG_QM_TID_SIZE_DIM_2_V_SHIFT 0
+#define TPC0_CFG_QM_TID_SIZE_DIM_2_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_QM_TID_BASE_DIM_3 */
+#define TPC0_CFG_QM_TID_BASE_DIM_3_V_SHIFT 0
+#define TPC0_CFG_QM_TID_BASE_DIM_3_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_QM_TID_SIZE_DIM_3 */
+#define TPC0_CFG_QM_TID_SIZE_DIM_3_V_SHIFT 0
+#define TPC0_CFG_QM_TID_SIZE_DIM_3_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_QM_TID_BASE_DIM_4 */
+#define TPC0_CFG_QM_TID_BASE_DIM_4_V_SHIFT 0
+#define TPC0_CFG_QM_TID_BASE_DIM_4_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_QM_TID_SIZE_DIM_4 */
+#define TPC0_CFG_QM_TID_SIZE_DIM_4_V_SHIFT 0
+#define TPC0_CFG_QM_TID_SIZE_DIM_4_V_MASK 0xFFFFFFFF
+
+/* TPC0_CFG_QM_KERNEL_CONFIG */
+#define TPC0_CFG_QM_KERNEL_CONFIG_SMALL_VLM_SHIFT 0
+#define TPC0_CFG_QM_KERNEL_CONFIG_SMALL_VLM_MASK 0x1
+#define TPC0_CFG_QM_KERNEL_CONFIG_ASO_EVICT_L0_SHIFT 1
+#define TPC0_CFG_QM_KERNEL_CONFIG_ASO_EVICT_L0_MASK 0x2
+#define TPC0_CFG_QM_KERNEL_CONFIG_NUM_VALID_SRFS_SHIFT 2
+#define TPC0_CFG_QM_KERNEL_CONFIG_NUM_VALID_SRFS_MASK 0xFC
+#define TPC0_CFG_QM_KERNEL_CONFIG_RD_RATE_LIMIT_RST_TOKEN_SHIFT 8
+#define TPC0_CFG_QM_KERNEL_CONFIG_RD_RATE_LIMIT_RST_TOKEN_MASK 0xFF00
+#define TPC0_CFG_QM_KERNEL_CONFIG_WR_RATE_LIMIT_RST_TOKEN_SHIFT 16
+#define TPC0_CFG_QM_KERNEL_CONFIG_WR_RATE_LIMIT_RST_TOKEN_MASK 0xFF0000
+
+/* TPC0_CFG_QM_KERNEL_ID */
+#define TPC0_CFG_QM_KERNEL_ID_V_SHIFT 0
+#define TPC0_CFG_QM_KERNEL_ID_V_MASK 0xFFFF
+
+/* TPC0_CFG_QM_SRF */
+#define TPC0_CFG_QM_SRF_V_SHIFT 0
+#define TPC0_CFG_QM_SRF_V_MASK 0xFFFFFFFF
+
+#endif /* ASIC_REG_TPC0_CFG_MASKS_H_ */
diff --git a/drivers/accel/habanalabs/include/gaudi/asic_reg/tpc0_cfg_regs.h b/drivers/accel/habanalabs/include/gaudi/asic_reg/tpc0_cfg_regs.h
new file mode 100644
index 0000000000..b82a906265
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi/asic_reg/tpc0_cfg_regs.h
@@ -0,0 +1,1226 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2016-2018 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ ** DO NOT EDIT BELOW **
+ ************************************/
+
+#ifndef ASIC_REG_TPC0_CFG_REGS_H_
+#define ASIC_REG_TPC0_CFG_REGS_H_
+
+/*
+ *****************************************
+ * TPC0_CFG (Prototype: TPC)
+ *****************************************
+ */
+
+#define mmTPC0_CFG_KERNEL_TENSOR_0_BASE_ADDR_LOW 0xE06400
+
+#define mmTPC0_CFG_KERNEL_TENSOR_0_BASE_ADDR_HIGH 0xE06404
+
+#define mmTPC0_CFG_KERNEL_TENSOR_0_PADDING_VALUE 0xE06408
+
+#define mmTPC0_CFG_KERNEL_TENSOR_0_TENSOR_CONFIG 0xE0640C
+
+#define mmTPC0_CFG_KERNEL_TENSOR_0_DIM_0_SIZE 0xE06410
+
+#define mmTPC0_CFG_KERNEL_TENSOR_0_DIM_0_STRIDE 0xE06414
+
+#define mmTPC0_CFG_KERNEL_TENSOR_0_DIM_1_SIZE 0xE06418
+
+#define mmTPC0_CFG_KERNEL_TENSOR_0_DIM_1_STRIDE 0xE0641C
+
+#define mmTPC0_CFG_KERNEL_TENSOR_0_DIM_2_SIZE 0xE06420
+
+#define mmTPC0_CFG_KERNEL_TENSOR_0_DIM_2_STRIDE 0xE06424
+
+#define mmTPC0_CFG_KERNEL_TENSOR_0_DIM_3_SIZE 0xE06428
+
+#define mmTPC0_CFG_KERNEL_TENSOR_0_DIM_3_STRIDE 0xE0642C
+
+#define mmTPC0_CFG_KERNEL_TENSOR_0_DIM_4_SIZE 0xE06430
+
+#define mmTPC0_CFG_KERNEL_TENSOR_0_DIM_4_STRIDE 0xE06434
+
+#define mmTPC0_CFG_KERNEL_TENSOR_1_BASE_ADDR_LOW 0xE06438
+
+#define mmTPC0_CFG_KERNEL_TENSOR_1_BASE_ADDR_HIGH 0xE0643C
+
+#define mmTPC0_CFG_KERNEL_TENSOR_1_PADDING_VALUE 0xE06440
+
+#define mmTPC0_CFG_KERNEL_TENSOR_1_TENSOR_CONFIG 0xE06444
+
+#define mmTPC0_CFG_KERNEL_TENSOR_1_DIM_0_SIZE 0xE06448
+
+#define mmTPC0_CFG_KERNEL_TENSOR_1_DIM_0_STRIDE 0xE0644C
+
+#define mmTPC0_CFG_KERNEL_TENSOR_1_DIM_1_SIZE 0xE06450
+
+#define mmTPC0_CFG_KERNEL_TENSOR_1_DIM_1_STRIDE 0xE06454
+
+#define mmTPC0_CFG_KERNEL_TENSOR_1_DIM_2_SIZE 0xE06458
+
+#define mmTPC0_CFG_KERNEL_TENSOR_1_DIM_2_STRIDE 0xE0645C
+
+#define mmTPC0_CFG_KERNEL_TENSOR_1_DIM_3_SIZE 0xE06460
+
+#define mmTPC0_CFG_KERNEL_TENSOR_1_DIM_3_STRIDE 0xE06464
+
+#define mmTPC0_CFG_KERNEL_TENSOR_1_DIM_4_SIZE 0xE06468
+
+#define mmTPC0_CFG_KERNEL_TENSOR_1_DIM_4_STRIDE 0xE0646C
+
+#define mmTPC0_CFG_KERNEL_TENSOR_2_BASE_ADDR_LOW 0xE06470
+
+#define mmTPC0_CFG_KERNEL_TENSOR_2_BASE_ADDR_HIGH 0xE06474
+
+#define mmTPC0_CFG_KERNEL_TENSOR_2_PADDING_VALUE 0xE06478
+
+#define mmTPC0_CFG_KERNEL_TENSOR_2_TENSOR_CONFIG 0xE0647C
+
+#define mmTPC0_CFG_KERNEL_TENSOR_2_DIM_0_SIZE 0xE06480
+
+#define mmTPC0_CFG_KERNEL_TENSOR_2_DIM_0_STRIDE 0xE06484
+
+#define mmTPC0_CFG_KERNEL_TENSOR_2_DIM_1_SIZE 0xE06488
+
+#define mmTPC0_CFG_KERNEL_TENSOR_2_DIM_1_STRIDE 0xE0648C
+
+#define mmTPC0_CFG_KERNEL_TENSOR_2_DIM_2_SIZE 0xE06490
+
+#define mmTPC0_CFG_KERNEL_TENSOR_2_DIM_2_STRIDE 0xE06494
+
+#define mmTPC0_CFG_KERNEL_TENSOR_2_DIM_3_SIZE 0xE06498
+
+#define mmTPC0_CFG_KERNEL_TENSOR_2_DIM_3_STRIDE 0xE0649C
+
+#define mmTPC0_CFG_KERNEL_TENSOR_2_DIM_4_SIZE 0xE064A0
+
+#define mmTPC0_CFG_KERNEL_TENSOR_2_DIM_4_STRIDE 0xE064A4
+
+#define mmTPC0_CFG_KERNEL_TENSOR_3_BASE_ADDR_LOW 0xE064A8
+
+#define mmTPC0_CFG_KERNEL_TENSOR_3_BASE_ADDR_HIGH 0xE064AC
+
+#define mmTPC0_CFG_KERNEL_TENSOR_3_PADDING_VALUE 0xE064B0
+
+#define mmTPC0_CFG_KERNEL_TENSOR_3_TENSOR_CONFIG 0xE064B4
+
+#define mmTPC0_CFG_KERNEL_TENSOR_3_DIM_0_SIZE 0xE064B8
+
+#define mmTPC0_CFG_KERNEL_TENSOR_3_DIM_0_STRIDE 0xE064BC
+
+#define mmTPC0_CFG_KERNEL_TENSOR_3_DIM_1_SIZE 0xE064C0
+
+#define mmTPC0_CFG_KERNEL_TENSOR_3_DIM_1_STRIDE 0xE064C4
+
+#define mmTPC0_CFG_KERNEL_TENSOR_3_DIM_2_SIZE 0xE064C8
+
+#define mmTPC0_CFG_KERNEL_TENSOR_3_DIM_2_STRIDE 0xE064CC
+
+#define mmTPC0_CFG_KERNEL_TENSOR_3_DIM_3_SIZE 0xE064D0
+
+#define mmTPC0_CFG_KERNEL_TENSOR_3_DIM_3_STRIDE 0xE064D4
+
+#define mmTPC0_CFG_KERNEL_TENSOR_3_DIM_4_SIZE 0xE064D8
+
+#define mmTPC0_CFG_KERNEL_TENSOR_3_DIM_4_STRIDE 0xE064DC
+
+#define mmTPC0_CFG_KERNEL_TENSOR_4_BASE_ADDR_LOW 0xE064E0
+
+#define mmTPC0_CFG_KERNEL_TENSOR_4_BASE_ADDR_HIGH 0xE064E4
+
+#define mmTPC0_CFG_KERNEL_TENSOR_4_PADDING_VALUE 0xE064E8
+
+#define mmTPC0_CFG_KERNEL_TENSOR_4_TENSOR_CONFIG 0xE064EC
+
+#define mmTPC0_CFG_KERNEL_TENSOR_4_DIM_0_SIZE 0xE064F0
+
+#define mmTPC0_CFG_KERNEL_TENSOR_4_DIM_0_STRIDE 0xE064F4
+
+#define mmTPC0_CFG_KERNEL_TENSOR_4_DIM_1_SIZE 0xE064F8
+
+#define mmTPC0_CFG_KERNEL_TENSOR_4_DIM_1_STRIDE 0xE064FC
+
+#define mmTPC0_CFG_KERNEL_TENSOR_4_DIM_2_SIZE 0xE06500
+
+#define mmTPC0_CFG_KERNEL_TENSOR_4_DIM_2_STRIDE 0xE06504
+
+#define mmTPC0_CFG_KERNEL_TENSOR_4_DIM_3_SIZE 0xE06508
+
+#define mmTPC0_CFG_KERNEL_TENSOR_4_DIM_3_STRIDE 0xE0650C
+
+#define mmTPC0_CFG_KERNEL_TENSOR_4_DIM_4_SIZE 0xE06510
+
+#define mmTPC0_CFG_KERNEL_TENSOR_4_DIM_4_STRIDE 0xE06514
+
+#define mmTPC0_CFG_KERNEL_TENSOR_5_BASE_ADDR_LOW 0xE06518
+
+#define mmTPC0_CFG_KERNEL_TENSOR_5_BASE_ADDR_HIGH 0xE0651C
+
+#define mmTPC0_CFG_KERNEL_TENSOR_5_PADDING_VALUE 0xE06520
+
+#define mmTPC0_CFG_KERNEL_TENSOR_5_TENSOR_CONFIG 0xE06524
+
+#define mmTPC0_CFG_KERNEL_TENSOR_5_DIM_0_SIZE 0xE06528
+
+#define mmTPC0_CFG_KERNEL_TENSOR_5_DIM_0_STRIDE 0xE0652C
+
+#define mmTPC0_CFG_KERNEL_TENSOR_5_DIM_1_SIZE 0xE06530
+
+#define mmTPC0_CFG_KERNEL_TENSOR_5_DIM_1_STRIDE 0xE06534
+
+#define mmTPC0_CFG_KERNEL_TENSOR_5_DIM_2_SIZE 0xE06538
+
+#define mmTPC0_CFG_KERNEL_TENSOR_5_DIM_2_STRIDE 0xE0653C
+
+#define mmTPC0_CFG_KERNEL_TENSOR_5_DIM_3_SIZE 0xE06540
+
+#define mmTPC0_CFG_KERNEL_TENSOR_5_DIM_3_STRIDE 0xE06544
+
+#define mmTPC0_CFG_KERNEL_TENSOR_5_DIM_4_SIZE 0xE06548
+
+#define mmTPC0_CFG_KERNEL_TENSOR_5_DIM_4_STRIDE 0xE0654C
+
+#define mmTPC0_CFG_KERNEL_TENSOR_6_BASE_ADDR_LOW 0xE06550
+
+#define mmTPC0_CFG_KERNEL_TENSOR_6_BASE_ADDR_HIGH 0xE06554
+
+#define mmTPC0_CFG_KERNEL_TENSOR_6_PADDING_VALUE 0xE06558
+
+#define mmTPC0_CFG_KERNEL_TENSOR_6_TENSOR_CONFIG 0xE0655C
+
+#define mmTPC0_CFG_KERNEL_TENSOR_6_DIM_0_SIZE 0xE06560
+
+#define mmTPC0_CFG_KERNEL_TENSOR_6_DIM_0_STRIDE 0xE06564
+
+#define mmTPC0_CFG_KERNEL_TENSOR_6_DIM_1_SIZE 0xE06568
+
+#define mmTPC0_CFG_KERNEL_TENSOR_6_DIM_1_STRIDE 0xE0656C
+
+#define mmTPC0_CFG_KERNEL_TENSOR_6_DIM_2_SIZE 0xE06570
+
+#define mmTPC0_CFG_KERNEL_TENSOR_6_DIM_2_STRIDE 0xE06574
+
+#define mmTPC0_CFG_KERNEL_TENSOR_6_DIM_3_SIZE 0xE06578
+
+#define mmTPC0_CFG_KERNEL_TENSOR_6_DIM_3_STRIDE 0xE0657C
+
+#define mmTPC0_CFG_KERNEL_TENSOR_6_DIM_4_SIZE 0xE06580
+
+#define mmTPC0_CFG_KERNEL_TENSOR_6_DIM_4_STRIDE 0xE06584
+
+#define mmTPC0_CFG_KERNEL_TENSOR_7_BASE_ADDR_LOW 0xE06588
+
+#define mmTPC0_CFG_KERNEL_TENSOR_7_BASE_ADDR_HIGH 0xE0658C
+
+#define mmTPC0_CFG_KERNEL_TENSOR_7_PADDING_VALUE 0xE06590
+
+#define mmTPC0_CFG_KERNEL_TENSOR_7_TENSOR_CONFIG 0xE06594
+
+#define mmTPC0_CFG_KERNEL_TENSOR_7_DIM_0_SIZE 0xE06598
+
+#define mmTPC0_CFG_KERNEL_TENSOR_7_DIM_0_STRIDE 0xE0659C
+
+#define mmTPC0_CFG_KERNEL_TENSOR_7_DIM_1_SIZE 0xE065A0
+
+#define mmTPC0_CFG_KERNEL_TENSOR_7_DIM_1_STRIDE 0xE065A4
+
+#define mmTPC0_CFG_KERNEL_TENSOR_7_DIM_2_SIZE 0xE065A8
+
+#define mmTPC0_CFG_KERNEL_TENSOR_7_DIM_2_STRIDE 0xE065AC
+
+#define mmTPC0_CFG_KERNEL_TENSOR_7_DIM_3_SIZE 0xE065B0
+
+#define mmTPC0_CFG_KERNEL_TENSOR_7_DIM_3_STRIDE 0xE065B4
+
+#define mmTPC0_CFG_KERNEL_TENSOR_7_DIM_4_SIZE 0xE065B8
+
+#define mmTPC0_CFG_KERNEL_TENSOR_7_DIM_4_STRIDE 0xE065BC
+
+#define mmTPC0_CFG_KERNEL_TENSOR_8_BASE_ADDR_LOW 0xE065C0
+
+#define mmTPC0_CFG_KERNEL_TENSOR_8_BASE_ADDR_HIGH 0xE065C4
+
+#define mmTPC0_CFG_KERNEL_TENSOR_8_PADDING_VALUE 0xE065C8
+
+#define mmTPC0_CFG_KERNEL_TENSOR_8_TENSOR_CONFIG 0xE065CC
+
+#define mmTPC0_CFG_KERNEL_TENSOR_8_DIM_0_SIZE 0xE065D0
+
+#define mmTPC0_CFG_KERNEL_TENSOR_8_DIM_0_STRIDE 0xE065D4
+
+#define mmTPC0_CFG_KERNEL_TENSOR_8_DIM_1_SIZE 0xE065D8
+
+#define mmTPC0_CFG_KERNEL_TENSOR_8_DIM_1_STRIDE 0xE065DC
+
+#define mmTPC0_CFG_KERNEL_TENSOR_8_DIM_2_SIZE 0xE065E0
+
+#define mmTPC0_CFG_KERNEL_TENSOR_8_DIM_2_STRIDE 0xE065E4
+
+#define mmTPC0_CFG_KERNEL_TENSOR_8_DIM_3_SIZE 0xE065E8
+
+#define mmTPC0_CFG_KERNEL_TENSOR_8_DIM_3_STRIDE 0xE065EC
+
+#define mmTPC0_CFG_KERNEL_TENSOR_8_DIM_4_SIZE 0xE065F0
+
+#define mmTPC0_CFG_KERNEL_TENSOR_8_DIM_4_STRIDE 0xE065F4
+
+#define mmTPC0_CFG_KERNEL_TENSOR_9_BASE_ADDR_LOW 0xE065F8
+
+#define mmTPC0_CFG_KERNEL_TENSOR_9_BASE_ADDR_HIGH 0xE065FC
+
+#define mmTPC0_CFG_KERNEL_TENSOR_9_PADDING_VALUE 0xE06600
+
+#define mmTPC0_CFG_KERNEL_TENSOR_9_TENSOR_CONFIG 0xE06604
+
+#define mmTPC0_CFG_KERNEL_TENSOR_9_DIM_0_SIZE 0xE06608
+
+#define mmTPC0_CFG_KERNEL_TENSOR_9_DIM_0_STRIDE 0xE0660C
+
+#define mmTPC0_CFG_KERNEL_TENSOR_9_DIM_1_SIZE 0xE06610
+
+#define mmTPC0_CFG_KERNEL_TENSOR_9_DIM_1_STRIDE 0xE06614
+
+#define mmTPC0_CFG_KERNEL_TENSOR_9_DIM_2_SIZE 0xE06618
+
+#define mmTPC0_CFG_KERNEL_TENSOR_9_DIM_2_STRIDE 0xE0661C
+
+#define mmTPC0_CFG_KERNEL_TENSOR_9_DIM_3_SIZE 0xE06620
+
+#define mmTPC0_CFG_KERNEL_TENSOR_9_DIM_3_STRIDE 0xE06624
+
+#define mmTPC0_CFG_KERNEL_TENSOR_9_DIM_4_SIZE 0xE06628
+
+#define mmTPC0_CFG_KERNEL_TENSOR_9_DIM_4_STRIDE 0xE0662C
+
+#define mmTPC0_CFG_KERNEL_TENSOR_10_BASE_ADDR_LOW 0xE06630
+
+#define mmTPC0_CFG_KERNEL_TENSOR_10_BASE_ADDR_HIGH 0xE06634
+
+#define mmTPC0_CFG_KERNEL_TENSOR_10_PADDING_VALUE 0xE06638
+
+#define mmTPC0_CFG_KERNEL_TENSOR_10_TENSOR_CONFIG 0xE0663C
+
+#define mmTPC0_CFG_KERNEL_TENSOR_10_DIM_0_SIZE 0xE06640
+
+#define mmTPC0_CFG_KERNEL_TENSOR_10_DIM_0_STRIDE 0xE06644
+
+#define mmTPC0_CFG_KERNEL_TENSOR_10_DIM_1_SIZE 0xE06648
+
+#define mmTPC0_CFG_KERNEL_TENSOR_10_DIM_1_STRIDE 0xE0664C
+
+#define mmTPC0_CFG_KERNEL_TENSOR_10_DIM_2_SIZE 0xE06650
+
+#define mmTPC0_CFG_KERNEL_TENSOR_10_DIM_2_STRIDE 0xE06654
+
+#define mmTPC0_CFG_KERNEL_TENSOR_10_DIM_3_SIZE 0xE06658
+
+#define mmTPC0_CFG_KERNEL_TENSOR_10_DIM_3_STRIDE 0xE0665C
+
+#define mmTPC0_CFG_KERNEL_TENSOR_10_DIM_4_SIZE 0xE06660
+
+#define mmTPC0_CFG_KERNEL_TENSOR_10_DIM_4_STRIDE 0xE06664
+
+#define mmTPC0_CFG_KERNEL_TENSOR_11_BASE_ADDR_LOW 0xE06668
+
+#define mmTPC0_CFG_KERNEL_TENSOR_11_BASE_ADDR_HIGH 0xE0666C
+
+#define mmTPC0_CFG_KERNEL_TENSOR_11_PADDING_VALUE 0xE06670
+
+#define mmTPC0_CFG_KERNEL_TENSOR_11_TENSOR_CONFIG 0xE06674
+
+#define mmTPC0_CFG_KERNEL_TENSOR_11_DIM_0_SIZE 0xE06678
+
+#define mmTPC0_CFG_KERNEL_TENSOR_11_DIM_0_STRIDE 0xE0667C
+
+#define mmTPC0_CFG_KERNEL_TENSOR_11_DIM_1_SIZE 0xE06680
+
+#define mmTPC0_CFG_KERNEL_TENSOR_11_DIM_1_STRIDE 0xE06684
+
+#define mmTPC0_CFG_KERNEL_TENSOR_11_DIM_2_SIZE 0xE06688
+
+#define mmTPC0_CFG_KERNEL_TENSOR_11_DIM_2_STRIDE 0xE0668C
+
+#define mmTPC0_CFG_KERNEL_TENSOR_11_DIM_3_SIZE 0xE06690
+
+#define mmTPC0_CFG_KERNEL_TENSOR_11_DIM_3_STRIDE 0xE06694
+
+#define mmTPC0_CFG_KERNEL_TENSOR_11_DIM_4_SIZE 0xE06698
+
+#define mmTPC0_CFG_KERNEL_TENSOR_11_DIM_4_STRIDE 0xE0669C
+
+#define mmTPC0_CFG_KERNEL_TENSOR_12_BASE_ADDR_LOW 0xE066A0
+
+#define mmTPC0_CFG_KERNEL_TENSOR_12_BASE_ADDR_HIGH 0xE066A4
+
+#define mmTPC0_CFG_KERNEL_TENSOR_12_PADDING_VALUE 0xE066A8
+
+#define mmTPC0_CFG_KERNEL_TENSOR_12_TENSOR_CONFIG 0xE066AC
+
+#define mmTPC0_CFG_KERNEL_TENSOR_12_DIM_0_SIZE 0xE066B0
+
+#define mmTPC0_CFG_KERNEL_TENSOR_12_DIM_0_STRIDE 0xE066B4
+
+#define mmTPC0_CFG_KERNEL_TENSOR_12_DIM_1_SIZE 0xE066B8
+
+#define mmTPC0_CFG_KERNEL_TENSOR_12_DIM_1_STRIDE 0xE066BC
+
+#define mmTPC0_CFG_KERNEL_TENSOR_12_DIM_2_SIZE 0xE066C0
+
+#define mmTPC0_CFG_KERNEL_TENSOR_12_DIM_2_STRIDE 0xE066C4
+
+#define mmTPC0_CFG_KERNEL_TENSOR_12_DIM_3_SIZE 0xE066C8
+
+#define mmTPC0_CFG_KERNEL_TENSOR_12_DIM_3_STRIDE 0xE066CC
+
+#define mmTPC0_CFG_KERNEL_TENSOR_12_DIM_4_SIZE 0xE066D0
+
+#define mmTPC0_CFG_KERNEL_TENSOR_12_DIM_4_STRIDE 0xE066D4
+
+#define mmTPC0_CFG_KERNEL_TENSOR_13_BASE_ADDR_LOW 0xE066D8
+
+#define mmTPC0_CFG_KERNEL_TENSOR_13_BASE_ADDR_HIGH 0xE066DC
+
+#define mmTPC0_CFG_KERNEL_TENSOR_13_PADDING_VALUE 0xE066E0
+
+#define mmTPC0_CFG_KERNEL_TENSOR_13_TENSOR_CONFIG 0xE066E4
+
+#define mmTPC0_CFG_KERNEL_TENSOR_13_DIM_0_SIZE 0xE066E8
+
+#define mmTPC0_CFG_KERNEL_TENSOR_13_DIM_0_STRIDE 0xE066EC
+
+#define mmTPC0_CFG_KERNEL_TENSOR_13_DIM_1_SIZE 0xE066F0
+
+#define mmTPC0_CFG_KERNEL_TENSOR_13_DIM_1_STRIDE 0xE066F4
+
+#define mmTPC0_CFG_KERNEL_TENSOR_13_DIM_2_SIZE 0xE066F8
+
+#define mmTPC0_CFG_KERNEL_TENSOR_13_DIM_2_STRIDE 0xE066FC
+
+#define mmTPC0_CFG_KERNEL_TENSOR_13_DIM_3_SIZE 0xE06700
+
+#define mmTPC0_CFG_KERNEL_TENSOR_13_DIM_3_STRIDE 0xE06704
+
+#define mmTPC0_CFG_KERNEL_TENSOR_13_DIM_4_SIZE 0xE06708
+
+#define mmTPC0_CFG_KERNEL_TENSOR_13_DIM_4_STRIDE 0xE0670C
+
+#define mmTPC0_CFG_KERNEL_TENSOR_14_BASE_ADDR_LOW 0xE06710
+
+#define mmTPC0_CFG_KERNEL_TENSOR_14_BASE_ADDR_HIGH 0xE06714
+
+#define mmTPC0_CFG_KERNEL_TENSOR_14_PADDING_VALUE 0xE06718
+
+#define mmTPC0_CFG_KERNEL_TENSOR_14_TENSOR_CONFIG 0xE0671C
+
+#define mmTPC0_CFG_KERNEL_TENSOR_14_DIM_0_SIZE 0xE06720
+
+#define mmTPC0_CFG_KERNEL_TENSOR_14_DIM_0_STRIDE 0xE06724
+
+#define mmTPC0_CFG_KERNEL_TENSOR_14_DIM_1_SIZE 0xE06728
+
+#define mmTPC0_CFG_KERNEL_TENSOR_14_DIM_1_STRIDE 0xE0672C
+
+#define mmTPC0_CFG_KERNEL_TENSOR_14_DIM_2_SIZE 0xE06730
+
+#define mmTPC0_CFG_KERNEL_TENSOR_14_DIM_2_STRIDE 0xE06734
+
+#define mmTPC0_CFG_KERNEL_TENSOR_14_DIM_3_SIZE 0xE06738
+
+#define mmTPC0_CFG_KERNEL_TENSOR_14_DIM_3_STRIDE 0xE0673C
+
+#define mmTPC0_CFG_KERNEL_TENSOR_14_DIM_4_SIZE 0xE06740
+
+#define mmTPC0_CFG_KERNEL_TENSOR_14_DIM_4_STRIDE 0xE06744
+
+#define mmTPC0_CFG_KERNEL_TENSOR_15_BASE_ADDR_LOW 0xE06748
+
+#define mmTPC0_CFG_KERNEL_TENSOR_15_BASE_ADDR_HIGH 0xE0674C
+
+#define mmTPC0_CFG_KERNEL_TENSOR_15_PADDING_VALUE 0xE06750
+
+#define mmTPC0_CFG_KERNEL_TENSOR_15_TENSOR_CONFIG 0xE06754
+
+#define mmTPC0_CFG_KERNEL_TENSOR_15_DIM_0_SIZE 0xE06758
+
+#define mmTPC0_CFG_KERNEL_TENSOR_15_DIM_0_STRIDE 0xE0675C
+
+#define mmTPC0_CFG_KERNEL_TENSOR_15_DIM_1_SIZE 0xE06760
+
+#define mmTPC0_CFG_KERNEL_TENSOR_15_DIM_1_STRIDE 0xE06764
+
+#define mmTPC0_CFG_KERNEL_TENSOR_15_DIM_2_SIZE 0xE06768
+
+#define mmTPC0_CFG_KERNEL_TENSOR_15_DIM_2_STRIDE 0xE0676C
+
+#define mmTPC0_CFG_KERNEL_TENSOR_15_DIM_3_SIZE 0xE06770
+
+#define mmTPC0_CFG_KERNEL_TENSOR_15_DIM_3_STRIDE 0xE06774
+
+#define mmTPC0_CFG_KERNEL_TENSOR_15_DIM_4_SIZE 0xE06778
+
+#define mmTPC0_CFG_KERNEL_TENSOR_15_DIM_4_STRIDE 0xE0677C
+
+#define mmTPC0_CFG_KERNEL_SYNC_OBJECT_MESSAGE 0xE06780
+
+#define mmTPC0_CFG_KERNEL_SYNC_OBJECT_ADDR 0xE06784
+
+#define mmTPC0_CFG_KERNEL_KERNEL_BASE_ADDRESS_LOW 0xE06788
+
+#define mmTPC0_CFG_KERNEL_KERNEL_BASE_ADDRESS_HIGH 0xE0678C
+
+#define mmTPC0_CFG_KERNEL_TID_BASE_DIM_0 0xE06790
+
+#define mmTPC0_CFG_KERNEL_TID_SIZE_DIM_0 0xE06794
+
+#define mmTPC0_CFG_KERNEL_TID_BASE_DIM_1 0xE06798
+
+#define mmTPC0_CFG_KERNEL_TID_SIZE_DIM_1 0xE0679C
+
+#define mmTPC0_CFG_KERNEL_TID_BASE_DIM_2 0xE067A0
+
+#define mmTPC0_CFG_KERNEL_TID_SIZE_DIM_2 0xE067A4
+
+#define mmTPC0_CFG_KERNEL_TID_BASE_DIM_3 0xE067A8
+
+#define mmTPC0_CFG_KERNEL_TID_SIZE_DIM_3 0xE067AC
+
+#define mmTPC0_CFG_KERNEL_TID_BASE_DIM_4 0xE067B0
+
+#define mmTPC0_CFG_KERNEL_TID_SIZE_DIM_4 0xE067B4
+
+#define mmTPC0_CFG_KERNEL_KERNEL_CONFIG 0xE067B8
+
+#define mmTPC0_CFG_KERNEL_KERNEL_ID 0xE067BC
+
+#define mmTPC0_CFG_KERNEL_SRF_0 0xE067C0
+
+#define mmTPC0_CFG_KERNEL_SRF_1 0xE067C4
+
+#define mmTPC0_CFG_KERNEL_SRF_2 0xE067C8
+
+#define mmTPC0_CFG_KERNEL_SRF_3 0xE067CC
+
+#define mmTPC0_CFG_KERNEL_SRF_4 0xE067D0
+
+#define mmTPC0_CFG_KERNEL_SRF_5 0xE067D4
+
+#define mmTPC0_CFG_KERNEL_SRF_6 0xE067D8
+
+#define mmTPC0_CFG_KERNEL_SRF_7 0xE067DC
+
+#define mmTPC0_CFG_KERNEL_SRF_8 0xE067E0
+
+#define mmTPC0_CFG_KERNEL_SRF_9 0xE067E4
+
+#define mmTPC0_CFG_KERNEL_SRF_10 0xE067E8
+
+#define mmTPC0_CFG_KERNEL_SRF_11 0xE067EC
+
+#define mmTPC0_CFG_KERNEL_SRF_12 0xE067F0
+
+#define mmTPC0_CFG_KERNEL_SRF_13 0xE067F4
+
+#define mmTPC0_CFG_KERNEL_SRF_14 0xE067F8
+
+#define mmTPC0_CFG_KERNEL_SRF_15 0xE067FC
+
+#define mmTPC0_CFG_KERNEL_SRF_16 0xE06800
+
+#define mmTPC0_CFG_KERNEL_SRF_17 0xE06804
+
+#define mmTPC0_CFG_KERNEL_SRF_18 0xE06808
+
+#define mmTPC0_CFG_KERNEL_SRF_19 0xE0680C
+
+#define mmTPC0_CFG_KERNEL_SRF_20 0xE06810
+
+#define mmTPC0_CFG_KERNEL_SRF_21 0xE06814
+
+#define mmTPC0_CFG_KERNEL_SRF_22 0xE06818
+
+#define mmTPC0_CFG_KERNEL_SRF_23 0xE0681C
+
+#define mmTPC0_CFG_KERNEL_SRF_24 0xE06820
+
+#define mmTPC0_CFG_KERNEL_SRF_25 0xE06824
+
+#define mmTPC0_CFG_KERNEL_SRF_26 0xE06828
+
+#define mmTPC0_CFG_KERNEL_SRF_27 0xE0682C
+
+#define mmTPC0_CFG_KERNEL_SRF_28 0xE06830
+
+#define mmTPC0_CFG_KERNEL_SRF_29 0xE06834
+
+#define mmTPC0_CFG_KERNEL_SRF_30 0xE06838
+
+#define mmTPC0_CFG_KERNEL_SRF_31 0xE0683C
+
+#define mmTPC0_CFG_ROUND_CSR 0xE068FC
+
+#define mmTPC0_CFG_PROT 0xE06900
+
+#define mmTPC0_CFG_SEMAPHORE 0xE06908
+
+#define mmTPC0_CFG_VFLAGS 0xE0690C
+
+#define mmTPC0_CFG_SFLAGS 0xE06910
+
+#define mmTPC0_CFG_LFSR_POLYNOM 0xE06918
+
+#define mmTPC0_CFG_STATUS 0xE0691C
+
+#define mmTPC0_CFG_CFG_BASE_ADDRESS_HIGH 0xE06920
+
+#define mmTPC0_CFG_CFG_SUBTRACT_VALUE 0xE06924
+
+#define mmTPC0_CFG_SM_BASE_ADDRESS_HIGH 0xE0692C
+
+#define mmTPC0_CFG_TPC_CMD 0xE06930
+
+#define mmTPC0_CFG_TPC_EXECUTE 0xE06938
+
+#define mmTPC0_CFG_TPC_STALL 0xE0693C
+
+#define mmTPC0_CFG_ICACHE_BASE_ADDERESS_LOW 0xE06940
+
+#define mmTPC0_CFG_ICACHE_BASE_ADDERESS_HIGH 0xE06944
+
+#define mmTPC0_CFG_RD_RATE_LIMIT 0xE06948
+
+#define mmTPC0_CFG_WR_RATE_LIMIT 0xE06950
+
+#define mmTPC0_CFG_MSS_CONFIG 0xE06954
+
+#define mmTPC0_CFG_TPC_INTR_CAUSE 0xE06958
+
+#define mmTPC0_CFG_TPC_INTR_MASK 0xE0695C
+
+#define mmTPC0_CFG_WQ_CREDITS 0xE06960
+
+#define mmTPC0_CFG_ARUSER_LO 0xE06964
+
+#define mmTPC0_CFG_ARUSER_HI 0xE06968
+
+#define mmTPC0_CFG_AWUSER_LO 0xE0696C
+
+#define mmTPC0_CFG_AWUSER_HI 0xE06970
+
+#define mmTPC0_CFG_OPCODE_EXEC 0xE06974
+
+#define mmTPC0_CFG_LUT_FUNC32_BASE_ADDR_LO 0xE06978
+
+#define mmTPC0_CFG_LUT_FUNC32_BASE_ADDR_HI 0xE0697C
+
+#define mmTPC0_CFG_LUT_FUNC64_BASE_ADDR_LO 0xE06980
+
+#define mmTPC0_CFG_LUT_FUNC64_BASE_ADDR_HI 0xE06984
+
+#define mmTPC0_CFG_LUT_FUNC128_BASE_ADDR_LO 0xE06988
+
+#define mmTPC0_CFG_LUT_FUNC128_BASE_ADDR_HI 0xE0698C
+
+#define mmTPC0_CFG_LUT_FUNC256_BASE_ADDR_LO 0xE06990
+
+#define mmTPC0_CFG_LUT_FUNC256_BASE_ADDR_HI 0xE06994
+
+#define mmTPC0_CFG_TSB_CFG_MAX_SIZE 0xE06998
+
+#define mmTPC0_CFG_TSB_CFG 0xE0699C
+
+#define mmTPC0_CFG_DBGMEM_ADD 0xE069A0
+
+#define mmTPC0_CFG_DBGMEM_DATA_WR 0xE069A4
+
+#define mmTPC0_CFG_DBGMEM_DATA_RD 0xE069A8
+
+#define mmTPC0_CFG_DBGMEM_CTRL 0xE069AC
+
+#define mmTPC0_CFG_DBGMEM_RC 0xE069B0
+
+#define mmTPC0_CFG_TSB_INFLIGHT_CNTR 0xE069B4
+
+#define mmTPC0_CFG_WQ_INFLIGHT_CNTR 0xE069B8
+
+#define mmTPC0_CFG_WQ_LBW_TOTAL_CNTR 0xE069BC
+
+#define mmTPC0_CFG_WQ_HBW_TOTAL_CNTR 0xE069C0
+
+#define mmTPC0_CFG_IRQ_OCCOUPY_CNTR 0xE069C4
+
+#define mmTPC0_CFG_FUNC_MBIST_CNTRL 0xE069D0
+
+#define mmTPC0_CFG_FUNC_MBIST_PAT 0xE069D4
+
+#define mmTPC0_CFG_FUNC_MBIST_MEM_0 0xE069D8
+
+#define mmTPC0_CFG_FUNC_MBIST_MEM_1 0xE069DC
+
+#define mmTPC0_CFG_FUNC_MBIST_MEM_2 0xE069E0
+
+#define mmTPC0_CFG_FUNC_MBIST_MEM_3 0xE069E4
+
+#define mmTPC0_CFG_FUNC_MBIST_MEM_4 0xE069E8
+
+#define mmTPC0_CFG_FUNC_MBIST_MEM_5 0xE069EC
+
+#define mmTPC0_CFG_FUNC_MBIST_MEM_6 0xE069F0
+
+#define mmTPC0_CFG_FUNC_MBIST_MEM_7 0xE069F4
+
+#define mmTPC0_CFG_FUNC_MBIST_MEM_8 0xE069F8
+
+#define mmTPC0_CFG_FUNC_MBIST_MEM_9 0xE069FC
+
+#define mmTPC0_CFG_QM_TENSOR_0_BASE_ADDR_LOW 0xE06A00
+
+#define mmTPC0_CFG_QM_TENSOR_0_BASE_ADDR_HIGH 0xE06A04
+
+#define mmTPC0_CFG_QM_TENSOR_0_PADDING_VALUE 0xE06A08
+
+#define mmTPC0_CFG_QM_TENSOR_0_TENSOR_CONFIG 0xE06A0C
+
+#define mmTPC0_CFG_QM_TENSOR_0_DIM_0_SIZE 0xE06A10
+
+#define mmTPC0_CFG_QM_TENSOR_0_DIM_0_STRIDE 0xE06A14
+
+#define mmTPC0_CFG_QM_TENSOR_0_DIM_1_SIZE 0xE06A18
+
+#define mmTPC0_CFG_QM_TENSOR_0_DIM_1_STRIDE 0xE06A1C
+
+#define mmTPC0_CFG_QM_TENSOR_0_DIM_2_SIZE 0xE06A20
+
+#define mmTPC0_CFG_QM_TENSOR_0_DIM_2_STRIDE 0xE06A24
+
+#define mmTPC0_CFG_QM_TENSOR_0_DIM_3_SIZE 0xE06A28
+
+#define mmTPC0_CFG_QM_TENSOR_0_DIM_3_STRIDE 0xE06A2C
+
+#define mmTPC0_CFG_QM_TENSOR_0_DIM_4_SIZE 0xE06A30
+
+#define mmTPC0_CFG_QM_TENSOR_0_DIM_4_STRIDE 0xE06A34
+
+#define mmTPC0_CFG_QM_TENSOR_1_BASE_ADDR_LOW 0xE06A38
+
+#define mmTPC0_CFG_QM_TENSOR_1_BASE_ADDR_HIGH 0xE06A3C
+
+#define mmTPC0_CFG_QM_TENSOR_1_PADDING_VALUE 0xE06A40
+
+#define mmTPC0_CFG_QM_TENSOR_1_TENSOR_CONFIG 0xE06A44
+
+#define mmTPC0_CFG_QM_TENSOR_1_DIM_0_SIZE 0xE06A48
+
+#define mmTPC0_CFG_QM_TENSOR_1_DIM_0_STRIDE 0xE06A4C
+
+#define mmTPC0_CFG_QM_TENSOR_1_DIM_1_SIZE 0xE06A50
+
+#define mmTPC0_CFG_QM_TENSOR_1_DIM_1_STRIDE 0xE06A54
+
+#define mmTPC0_CFG_QM_TENSOR_1_DIM_2_SIZE 0xE06A58
+
+#define mmTPC0_CFG_QM_TENSOR_1_DIM_2_STRIDE 0xE06A5C
+
+#define mmTPC0_CFG_QM_TENSOR_1_DIM_3_SIZE 0xE06A60
+
+#define mmTPC0_CFG_QM_TENSOR_1_DIM_3_STRIDE 0xE06A64
+
+#define mmTPC0_CFG_QM_TENSOR_1_DIM_4_SIZE 0xE06A68
+
+#define mmTPC0_CFG_QM_TENSOR_1_DIM_4_STRIDE 0xE06A6C
+
+#define mmTPC0_CFG_QM_TENSOR_2_BASE_ADDR_LOW 0xE06A70
+
+#define mmTPC0_CFG_QM_TENSOR_2_BASE_ADDR_HIGH 0xE06A74
+
+#define mmTPC0_CFG_QM_TENSOR_2_PADDING_VALUE 0xE06A78
+
+#define mmTPC0_CFG_QM_TENSOR_2_TENSOR_CONFIG 0xE06A7C
+
+#define mmTPC0_CFG_QM_TENSOR_2_DIM_0_SIZE 0xE06A80
+
+#define mmTPC0_CFG_QM_TENSOR_2_DIM_0_STRIDE 0xE06A84
+
+#define mmTPC0_CFG_QM_TENSOR_2_DIM_1_SIZE 0xE06A88
+
+#define mmTPC0_CFG_QM_TENSOR_2_DIM_1_STRIDE 0xE06A8C
+
+#define mmTPC0_CFG_QM_TENSOR_2_DIM_2_SIZE 0xE06A90
+
+#define mmTPC0_CFG_QM_TENSOR_2_DIM_2_STRIDE 0xE06A94
+
+#define mmTPC0_CFG_QM_TENSOR_2_DIM_3_SIZE 0xE06A98
+
+#define mmTPC0_CFG_QM_TENSOR_2_DIM_3_STRIDE 0xE06A9C
+
+#define mmTPC0_CFG_QM_TENSOR_2_DIM_4_SIZE 0xE06AA0
+
+#define mmTPC0_CFG_QM_TENSOR_2_DIM_4_STRIDE 0xE06AA4
+
+#define mmTPC0_CFG_QM_TENSOR_3_BASE_ADDR_LOW 0xE06AA8
+
+#define mmTPC0_CFG_QM_TENSOR_3_BASE_ADDR_HIGH 0xE06AAC
+
+#define mmTPC0_CFG_QM_TENSOR_3_PADDING_VALUE 0xE06AB0
+
+#define mmTPC0_CFG_QM_TENSOR_3_TENSOR_CONFIG 0xE06AB4
+
+#define mmTPC0_CFG_QM_TENSOR_3_DIM_0_SIZE 0xE06AB8
+
+#define mmTPC0_CFG_QM_TENSOR_3_DIM_0_STRIDE 0xE06ABC
+
+#define mmTPC0_CFG_QM_TENSOR_3_DIM_1_SIZE 0xE06AC0
+
+#define mmTPC0_CFG_QM_TENSOR_3_DIM_1_STRIDE 0xE06AC4
+
+#define mmTPC0_CFG_QM_TENSOR_3_DIM_2_SIZE 0xE06AC8
+
+#define mmTPC0_CFG_QM_TENSOR_3_DIM_2_STRIDE 0xE06ACC
+
+#define mmTPC0_CFG_QM_TENSOR_3_DIM_3_SIZE 0xE06AD0
+
+#define mmTPC0_CFG_QM_TENSOR_3_DIM_3_STRIDE 0xE06AD4
+
+#define mmTPC0_CFG_QM_TENSOR_3_DIM_4_SIZE 0xE06AD8
+
+#define mmTPC0_CFG_QM_TENSOR_3_DIM_4_STRIDE 0xE06ADC
+
+#define mmTPC0_CFG_QM_TENSOR_4_BASE_ADDR_LOW 0xE06AE0
+
+#define mmTPC0_CFG_QM_TENSOR_4_BASE_ADDR_HIGH 0xE06AE4
+
+#define mmTPC0_CFG_QM_TENSOR_4_PADDING_VALUE 0xE06AE8
+
+#define mmTPC0_CFG_QM_TENSOR_4_TENSOR_CONFIG 0xE06AEC
+
+#define mmTPC0_CFG_QM_TENSOR_4_DIM_0_SIZE 0xE06AF0
+
+#define mmTPC0_CFG_QM_TENSOR_4_DIM_0_STRIDE 0xE06AF4
+
+#define mmTPC0_CFG_QM_TENSOR_4_DIM_1_SIZE 0xE06AF8
+
+#define mmTPC0_CFG_QM_TENSOR_4_DIM_1_STRIDE 0xE06AFC
+
+#define mmTPC0_CFG_QM_TENSOR_4_DIM_2_SIZE 0xE06B00
+
+#define mmTPC0_CFG_QM_TENSOR_4_DIM_2_STRIDE 0xE06B04
+
+#define mmTPC0_CFG_QM_TENSOR_4_DIM_3_SIZE 0xE06B08
+
+#define mmTPC0_CFG_QM_TENSOR_4_DIM_3_STRIDE 0xE06B0C
+
+#define mmTPC0_CFG_QM_TENSOR_4_DIM_4_SIZE 0xE06B10
+
+#define mmTPC0_CFG_QM_TENSOR_4_DIM_4_STRIDE 0xE06B14
+
+#define mmTPC0_CFG_QM_TENSOR_5_BASE_ADDR_LOW 0xE06B18
+
+#define mmTPC0_CFG_QM_TENSOR_5_BASE_ADDR_HIGH 0xE06B1C
+
+#define mmTPC0_CFG_QM_TENSOR_5_PADDING_VALUE 0xE06B20
+
+#define mmTPC0_CFG_QM_TENSOR_5_TENSOR_CONFIG 0xE06B24
+
+#define mmTPC0_CFG_QM_TENSOR_5_DIM_0_SIZE 0xE06B28
+
+#define mmTPC0_CFG_QM_TENSOR_5_DIM_0_STRIDE 0xE06B2C
+
+#define mmTPC0_CFG_QM_TENSOR_5_DIM_1_SIZE 0xE06B30
+
+#define mmTPC0_CFG_QM_TENSOR_5_DIM_1_STRIDE 0xE06B34
+
+#define mmTPC0_CFG_QM_TENSOR_5_DIM_2_SIZE 0xE06B38
+
+#define mmTPC0_CFG_QM_TENSOR_5_DIM_2_STRIDE 0xE06B3C
+
+#define mmTPC0_CFG_QM_TENSOR_5_DIM_3_SIZE 0xE06B40
+
+#define mmTPC0_CFG_QM_TENSOR_5_DIM_3_STRIDE 0xE06B44
+
+#define mmTPC0_CFG_QM_TENSOR_5_DIM_4_SIZE 0xE06B48
+
+#define mmTPC0_CFG_QM_TENSOR_5_DIM_4_STRIDE 0xE06B4C
+
+#define mmTPC0_CFG_QM_TENSOR_6_BASE_ADDR_LOW 0xE06B50
+
+#define mmTPC0_CFG_QM_TENSOR_6_BASE_ADDR_HIGH 0xE06B54
+
+#define mmTPC0_CFG_QM_TENSOR_6_PADDING_VALUE 0xE06B58
+
+#define mmTPC0_CFG_QM_TENSOR_6_TENSOR_CONFIG 0xE06B5C
+
+#define mmTPC0_CFG_QM_TENSOR_6_DIM_0_SIZE 0xE06B60
+
+#define mmTPC0_CFG_QM_TENSOR_6_DIM_0_STRIDE 0xE06B64
+
+#define mmTPC0_CFG_QM_TENSOR_6_DIM_1_SIZE 0xE06B68
+
+#define mmTPC0_CFG_QM_TENSOR_6_DIM_1_STRIDE 0xE06B6C
+
+#define mmTPC0_CFG_QM_TENSOR_6_DIM_2_SIZE 0xE06B70
+
+#define mmTPC0_CFG_QM_TENSOR_6_DIM_2_STRIDE 0xE06B74
+
+#define mmTPC0_CFG_QM_TENSOR_6_DIM_3_SIZE 0xE06B78
+
+#define mmTPC0_CFG_QM_TENSOR_6_DIM_3_STRIDE 0xE06B7C
+
+#define mmTPC0_CFG_QM_TENSOR_6_DIM_4_SIZE 0xE06B80
+
+#define mmTPC0_CFG_QM_TENSOR_6_DIM_4_STRIDE 0xE06B84
+
+#define mmTPC0_CFG_QM_TENSOR_7_BASE_ADDR_LOW 0xE06B88
+
+#define mmTPC0_CFG_QM_TENSOR_7_BASE_ADDR_HIGH 0xE06B8C
+
+#define mmTPC0_CFG_QM_TENSOR_7_PADDING_VALUE 0xE06B90
+
+#define mmTPC0_CFG_QM_TENSOR_7_TENSOR_CONFIG 0xE06B94
+
+#define mmTPC0_CFG_QM_TENSOR_7_DIM_0_SIZE 0xE06B98
+
+#define mmTPC0_CFG_QM_TENSOR_7_DIM_0_STRIDE 0xE06B9C
+
+#define mmTPC0_CFG_QM_TENSOR_7_DIM_1_SIZE 0xE06BA0
+
+#define mmTPC0_CFG_QM_TENSOR_7_DIM_1_STRIDE 0xE06BA4
+
+#define mmTPC0_CFG_QM_TENSOR_7_DIM_2_SIZE 0xE06BA8
+
+#define mmTPC0_CFG_QM_TENSOR_7_DIM_2_STRIDE 0xE06BAC
+
+#define mmTPC0_CFG_QM_TENSOR_7_DIM_3_SIZE 0xE06BB0
+
+#define mmTPC0_CFG_QM_TENSOR_7_DIM_3_STRIDE 0xE06BB4
+
+#define mmTPC0_CFG_QM_TENSOR_7_DIM_4_SIZE 0xE06BB8
+
+#define mmTPC0_CFG_QM_TENSOR_7_DIM_4_STRIDE 0xE06BBC
+
+#define mmTPC0_CFG_QM_TENSOR_8_BASE_ADDR_LOW 0xE06BC0
+
+#define mmTPC0_CFG_QM_TENSOR_8_BASE_ADDR_HIGH 0xE06BC4
+
+#define mmTPC0_CFG_QM_TENSOR_8_PADDING_VALUE 0xE06BC8
+
+#define mmTPC0_CFG_QM_TENSOR_8_TENSOR_CONFIG 0xE06BCC
+
+#define mmTPC0_CFG_QM_TENSOR_8_DIM_0_SIZE 0xE06BD0
+
+#define mmTPC0_CFG_QM_TENSOR_8_DIM_0_STRIDE 0xE06BD4
+
+#define mmTPC0_CFG_QM_TENSOR_8_DIM_1_SIZE 0xE06BD8
+
+#define mmTPC0_CFG_QM_TENSOR_8_DIM_1_STRIDE 0xE06BDC
+
+#define mmTPC0_CFG_QM_TENSOR_8_DIM_2_SIZE 0xE06BE0
+
+#define mmTPC0_CFG_QM_TENSOR_8_DIM_2_STRIDE 0xE06BE4
+
+#define mmTPC0_CFG_QM_TENSOR_8_DIM_3_SIZE 0xE06BE8
+
+#define mmTPC0_CFG_QM_TENSOR_8_DIM_3_STRIDE 0xE06BEC
+
+#define mmTPC0_CFG_QM_TENSOR_8_DIM_4_SIZE 0xE06BF0
+
+#define mmTPC0_CFG_QM_TENSOR_8_DIM_4_STRIDE 0xE06BF4
+
+#define mmTPC0_CFG_QM_TENSOR_9_BASE_ADDR_LOW 0xE06BF8
+
+#define mmTPC0_CFG_QM_TENSOR_9_BASE_ADDR_HIGH 0xE06BFC
+
+#define mmTPC0_CFG_QM_TENSOR_9_PADDING_VALUE 0xE06C00
+
+#define mmTPC0_CFG_QM_TENSOR_9_TENSOR_CONFIG 0xE06C04
+
+#define mmTPC0_CFG_QM_TENSOR_9_DIM_0_SIZE 0xE06C08
+
+#define mmTPC0_CFG_QM_TENSOR_9_DIM_0_STRIDE 0xE06C0C
+
+#define mmTPC0_CFG_QM_TENSOR_9_DIM_1_SIZE 0xE06C10
+
+#define mmTPC0_CFG_QM_TENSOR_9_DIM_1_STRIDE 0xE06C14
+
+#define mmTPC0_CFG_QM_TENSOR_9_DIM_2_SIZE 0xE06C18
+
+#define mmTPC0_CFG_QM_TENSOR_9_DIM_2_STRIDE 0xE06C1C
+
+#define mmTPC0_CFG_QM_TENSOR_9_DIM_3_SIZE 0xE06C20
+
+#define mmTPC0_CFG_QM_TENSOR_9_DIM_3_STRIDE 0xE06C24
+
+#define mmTPC0_CFG_QM_TENSOR_9_DIM_4_SIZE 0xE06C28
+
+#define mmTPC0_CFG_QM_TENSOR_9_DIM_4_STRIDE 0xE06C2C
+
+#define mmTPC0_CFG_QM_TENSOR_10_BASE_ADDR_LOW 0xE06C30
+
+#define mmTPC0_CFG_QM_TENSOR_10_BASE_ADDR_HIGH 0xE06C34
+
+#define mmTPC0_CFG_QM_TENSOR_10_PADDING_VALUE 0xE06C38
+
+#define mmTPC0_CFG_QM_TENSOR_10_TENSOR_CONFIG 0xE06C3C
+
+#define mmTPC0_CFG_QM_TENSOR_10_DIM_0_SIZE 0xE06C40
+
+#define mmTPC0_CFG_QM_TENSOR_10_DIM_0_STRIDE 0xE06C44
+
+#define mmTPC0_CFG_QM_TENSOR_10_DIM_1_SIZE 0xE06C48
+
+#define mmTPC0_CFG_QM_TENSOR_10_DIM_1_STRIDE 0xE06C4C
+
+#define mmTPC0_CFG_QM_TENSOR_10_DIM_2_SIZE 0xE06C50
+
+#define mmTPC0_CFG_QM_TENSOR_10_DIM_2_STRIDE 0xE06C54
+
+#define mmTPC0_CFG_QM_TENSOR_10_DIM_3_SIZE 0xE06C58
+
+#define mmTPC0_CFG_QM_TENSOR_10_DIM_3_STRIDE 0xE06C5C
+
+#define mmTPC0_CFG_QM_TENSOR_10_DIM_4_SIZE 0xE06C60
+
+#define mmTPC0_CFG_QM_TENSOR_10_DIM_4_STRIDE 0xE06C64
+
+#define mmTPC0_CFG_QM_TENSOR_11_BASE_ADDR_LOW 0xE06C68
+
+#define mmTPC0_CFG_QM_TENSOR_11_BASE_ADDR_HIGH 0xE06C6C
+
+#define mmTPC0_CFG_QM_TENSOR_11_PADDING_VALUE 0xE06C70
+
+#define mmTPC0_CFG_QM_TENSOR_11_TENSOR_CONFIG 0xE06C74
+
+#define mmTPC0_CFG_QM_TENSOR_11_DIM_0_SIZE 0xE06C78
+
+#define mmTPC0_CFG_QM_TENSOR_11_DIM_0_STRIDE 0xE06C7C
+
+#define mmTPC0_CFG_QM_TENSOR_11_DIM_1_SIZE 0xE06C80
+
+#define mmTPC0_CFG_QM_TENSOR_11_DIM_1_STRIDE 0xE06C84
+
+#define mmTPC0_CFG_QM_TENSOR_11_DIM_2_SIZE 0xE06C88
+
+#define mmTPC0_CFG_QM_TENSOR_11_DIM_2_STRIDE 0xE06C8C
+
+#define mmTPC0_CFG_QM_TENSOR_11_DIM_3_SIZE 0xE06C90
+
+#define mmTPC0_CFG_QM_TENSOR_11_DIM_3_STRIDE 0xE06C94
+
+#define mmTPC0_CFG_QM_TENSOR_11_DIM_4_SIZE 0xE06C98
+
+#define mmTPC0_CFG_QM_TENSOR_11_DIM_4_STRIDE 0xE06C9C
+
+#define mmTPC0_CFG_QM_TENSOR_12_BASE_ADDR_LOW 0xE06CA0
+
+#define mmTPC0_CFG_QM_TENSOR_12_BASE_ADDR_HIGH 0xE06CA4
+
+#define mmTPC0_CFG_QM_TENSOR_12_PADDING_VALUE 0xE06CA8
+
+#define mmTPC0_CFG_QM_TENSOR_12_TENSOR_CONFIG 0xE06CAC
+
+#define mmTPC0_CFG_QM_TENSOR_12_DIM_0_SIZE 0xE06CB0
+
+#define mmTPC0_CFG_QM_TENSOR_12_DIM_0_STRIDE 0xE06CB4
+
+#define mmTPC0_CFG_QM_TENSOR_12_DIM_1_SIZE 0xE06CB8
+
+#define mmTPC0_CFG_QM_TENSOR_12_DIM_1_STRIDE 0xE06CBC
+
+#define mmTPC0_CFG_QM_TENSOR_12_DIM_2_SIZE 0xE06CC0
+
+#define mmTPC0_CFG_QM_TENSOR_12_DIM_2_STRIDE 0xE06CC4
+
+#define mmTPC0_CFG_QM_TENSOR_12_DIM_3_SIZE 0xE06CC8
+
+#define mmTPC0_CFG_QM_TENSOR_12_DIM_3_STRIDE 0xE06CCC
+
+#define mmTPC0_CFG_QM_TENSOR_12_DIM_4_SIZE 0xE06CD0
+
+#define mmTPC0_CFG_QM_TENSOR_12_DIM_4_STRIDE 0xE06CD4
+
+#define mmTPC0_CFG_QM_TENSOR_13_BASE_ADDR_LOW 0xE06CD8
+
+#define mmTPC0_CFG_QM_TENSOR_13_BASE_ADDR_HIGH 0xE06CDC
+
+#define mmTPC0_CFG_QM_TENSOR_13_PADDING_VALUE 0xE06CE0
+
+#define mmTPC0_CFG_QM_TENSOR_13_TENSOR_CONFIG 0xE06CE4
+
+#define mmTPC0_CFG_QM_TENSOR_13_DIM_0_SIZE 0xE06CE8
+
+#define mmTPC0_CFG_QM_TENSOR_13_DIM_0_STRIDE 0xE06CEC
+
+#define mmTPC0_CFG_QM_TENSOR_13_DIM_1_SIZE 0xE06CF0
+
+#define mmTPC0_CFG_QM_TENSOR_13_DIM_1_STRIDE 0xE06CF4
+
+#define mmTPC0_CFG_QM_TENSOR_13_DIM_2_SIZE 0xE06CF8
+
+#define mmTPC0_CFG_QM_TENSOR_13_DIM_2_STRIDE 0xE06CFC
+
+#define mmTPC0_CFG_QM_TENSOR_13_DIM_3_SIZE 0xE06D00
+
+#define mmTPC0_CFG_QM_TENSOR_13_DIM_3_STRIDE 0xE06D04
+
+#define mmTPC0_CFG_QM_TENSOR_13_DIM_4_SIZE 0xE06D08
+
+#define mmTPC0_CFG_QM_TENSOR_13_DIM_4_STRIDE 0xE06D0C
+
+#define mmTPC0_CFG_QM_TENSOR_14_BASE_ADDR_LOW 0xE06D10
+
+#define mmTPC0_CFG_QM_TENSOR_14_BASE_ADDR_HIGH 0xE06D14
+
+#define mmTPC0_CFG_QM_TENSOR_14_PADDING_VALUE 0xE06D18
+
+#define mmTPC0_CFG_QM_TENSOR_14_TENSOR_CONFIG 0xE06D1C
+
+#define mmTPC0_CFG_QM_TENSOR_14_DIM_0_SIZE 0xE06D20
+
+#define mmTPC0_CFG_QM_TENSOR_14_DIM_0_STRIDE 0xE06D24
+
+#define mmTPC0_CFG_QM_TENSOR_14_DIM_1_SIZE 0xE06D28
+
+#define mmTPC0_CFG_QM_TENSOR_14_DIM_1_STRIDE 0xE06D2C
+
+#define mmTPC0_CFG_QM_TENSOR_14_DIM_2_SIZE 0xE06D30
+
+#define mmTPC0_CFG_QM_TENSOR_14_DIM_2_STRIDE 0xE06D34
+
+#define mmTPC0_CFG_QM_TENSOR_14_DIM_3_SIZE 0xE06D38
+
+#define mmTPC0_CFG_QM_TENSOR_14_DIM_3_STRIDE 0xE06D3C
+
+#define mmTPC0_CFG_QM_TENSOR_14_DIM_4_SIZE 0xE06D40
+
+#define mmTPC0_CFG_QM_TENSOR_14_DIM_4_STRIDE 0xE06D44
+
+#define mmTPC0_CFG_QM_TENSOR_15_BASE_ADDR_LOW 0xE06D48
+
+#define mmTPC0_CFG_QM_TENSOR_15_BASE_ADDR_HIGH 0xE06D4C
+
+#define mmTPC0_CFG_QM_TENSOR_15_PADDING_VALUE 0xE06D50
+
+#define mmTPC0_CFG_QM_TENSOR_15_TENSOR_CONFIG 0xE06D54
+
+#define mmTPC0_CFG_QM_TENSOR_15_DIM_0_SIZE 0xE06D58
+
+#define mmTPC0_CFG_QM_TENSOR_15_DIM_0_STRIDE 0xE06D5C
+
+#define mmTPC0_CFG_QM_TENSOR_15_DIM_1_SIZE 0xE06D60
+
+#define mmTPC0_CFG_QM_TENSOR_15_DIM_1_STRIDE 0xE06D64
+
+#define mmTPC0_CFG_QM_TENSOR_15_DIM_2_SIZE 0xE06D68
+
+#define mmTPC0_CFG_QM_TENSOR_15_DIM_2_STRIDE 0xE06D6C
+
+#define mmTPC0_CFG_QM_TENSOR_15_DIM_3_SIZE 0xE06D70
+
+#define mmTPC0_CFG_QM_TENSOR_15_DIM_3_STRIDE 0xE06D74
+
+#define mmTPC0_CFG_QM_TENSOR_15_DIM_4_SIZE 0xE06D78
+
+#define mmTPC0_CFG_QM_TENSOR_15_DIM_4_STRIDE 0xE06D7C
+
+#define mmTPC0_CFG_QM_SYNC_OBJECT_MESSAGE 0xE06D80
+
+#define mmTPC0_CFG_QM_SYNC_OBJECT_ADDR 0xE06D84
+
+#define mmTPC0_CFG_QM_KERNEL_BASE_ADDRESS_LOW 0xE06D88
+
+#define mmTPC0_CFG_QM_KERNEL_BASE_ADDRESS_HIGH 0xE06D8C
+
+#define mmTPC0_CFG_QM_TID_BASE_DIM_0 0xE06D90
+
+#define mmTPC0_CFG_QM_TID_SIZE_DIM_0 0xE06D94
+
+#define mmTPC0_CFG_QM_TID_BASE_DIM_1 0xE06D98
+
+#define mmTPC0_CFG_QM_TID_SIZE_DIM_1 0xE06D9C
+
+#define mmTPC0_CFG_QM_TID_BASE_DIM_2 0xE06DA0
+
+#define mmTPC0_CFG_QM_TID_SIZE_DIM_2 0xE06DA4
+
+#define mmTPC0_CFG_QM_TID_BASE_DIM_3 0xE06DA8
+
+#define mmTPC0_CFG_QM_TID_SIZE_DIM_3 0xE06DAC
+
+#define mmTPC0_CFG_QM_TID_BASE_DIM_4 0xE06DB0
+
+#define mmTPC0_CFG_QM_TID_SIZE_DIM_4 0xE06DB4
+
+#define mmTPC0_CFG_QM_KERNEL_CONFIG 0xE06DB8
+
+#define mmTPC0_CFG_QM_KERNEL_ID 0xE06DBC
+
+#define mmTPC0_CFG_QM_SRF_0 0xE06DC0
+
+#define mmTPC0_CFG_QM_SRF_1 0xE06DC4
+
+#define mmTPC0_CFG_QM_SRF_2 0xE06DC8
+
+#define mmTPC0_CFG_QM_SRF_3 0xE06DCC
+
+#define mmTPC0_CFG_QM_SRF_4 0xE06DD0
+
+#define mmTPC0_CFG_QM_SRF_5 0xE06DD4
+
+#define mmTPC0_CFG_QM_SRF_6 0xE06DD8
+
+#define mmTPC0_CFG_QM_SRF_7 0xE06DDC
+
+#define mmTPC0_CFG_QM_SRF_8 0xE06DE0
+
+#define mmTPC0_CFG_QM_SRF_9 0xE06DE4
+
+#define mmTPC0_CFG_QM_SRF_10 0xE06DE8
+
+#define mmTPC0_CFG_QM_SRF_11 0xE06DEC
+
+#define mmTPC0_CFG_QM_SRF_12 0xE06DF0
+
+#define mmTPC0_CFG_QM_SRF_13 0xE06DF4
+
+#define mmTPC0_CFG_QM_SRF_14 0xE06DF8
+
+#define mmTPC0_CFG_QM_SRF_15 0xE06DFC
+
+#define mmTPC0_CFG_QM_SRF_16 0xE06E00
+
+#define mmTPC0_CFG_QM_SRF_17 0xE06E04
+
+#define mmTPC0_CFG_QM_SRF_18 0xE06E08
+
+#define mmTPC0_CFG_QM_SRF_19 0xE06E0C
+
+#define mmTPC0_CFG_QM_SRF_20 0xE06E10
+
+#define mmTPC0_CFG_QM_SRF_21 0xE06E14
+
+#define mmTPC0_CFG_QM_SRF_22 0xE06E18
+
+#define mmTPC0_CFG_QM_SRF_23 0xE06E1C
+
+#define mmTPC0_CFG_QM_SRF_24 0xE06E20
+
+#define mmTPC0_CFG_QM_SRF_25 0xE06E24
+
+#define mmTPC0_CFG_QM_SRF_26 0xE06E28
+
+#define mmTPC0_CFG_QM_SRF_27 0xE06E2C
+
+#define mmTPC0_CFG_QM_SRF_28 0xE06E30
+
+#define mmTPC0_CFG_QM_SRF_29 0xE06E34
+
+#define mmTPC0_CFG_QM_SRF_30 0xE06E38
+
+#define mmTPC0_CFG_QM_SRF_31 0xE06E3C
+
+#endif /* ASIC_REG_TPC0_CFG_REGS_H_ */
diff --git a/drivers/accel/habanalabs/include/gaudi/asic_reg/tpc0_qm_masks.h b/drivers/accel/habanalabs/include/gaudi/asic_reg/tpc0_qm_masks.h
new file mode 100644
index 0000000000..8e71532c6f
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi/asic_reg/tpc0_qm_masks.h
@@ -0,0 +1,800 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2016-2018 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ ** DO NOT EDIT BELOW **
+ ************************************/
+
+#ifndef ASIC_REG_TPC0_QM_MASKS_H_
+#define ASIC_REG_TPC0_QM_MASKS_H_
+
+/*
+ *****************************************
+ * TPC0_QM (Prototype: QMAN)
+ *****************************************
+ */
+
+/* TPC0_QM_GLBL_CFG0 */
+#define TPC0_QM_GLBL_CFG0_PQF_EN_SHIFT 0
+#define TPC0_QM_GLBL_CFG0_PQF_EN_MASK 0xF
+#define TPC0_QM_GLBL_CFG0_CQF_EN_SHIFT 4
+#define TPC0_QM_GLBL_CFG0_CQF_EN_MASK 0x1F0
+#define TPC0_QM_GLBL_CFG0_CP_EN_SHIFT 9
+#define TPC0_QM_GLBL_CFG0_CP_EN_MASK 0x3E00
+
+/* TPC0_QM_GLBL_CFG1 */
+#define TPC0_QM_GLBL_CFG1_PQF_STOP_SHIFT 0
+#define TPC0_QM_GLBL_CFG1_PQF_STOP_MASK 0xF
+#define TPC0_QM_GLBL_CFG1_CQF_STOP_SHIFT 4
+#define TPC0_QM_GLBL_CFG1_CQF_STOP_MASK 0x1F0
+#define TPC0_QM_GLBL_CFG1_CP_STOP_SHIFT 9
+#define TPC0_QM_GLBL_CFG1_CP_STOP_MASK 0x3E00
+#define TPC0_QM_GLBL_CFG1_PQF_FLUSH_SHIFT 16
+#define TPC0_QM_GLBL_CFG1_PQF_FLUSH_MASK 0xF0000
+#define TPC0_QM_GLBL_CFG1_CQF_FLUSH_SHIFT 20
+#define TPC0_QM_GLBL_CFG1_CQF_FLUSH_MASK 0x1F00000
+#define TPC0_QM_GLBL_CFG1_CP_FLUSH_SHIFT 25
+#define TPC0_QM_GLBL_CFG1_CP_FLUSH_MASK 0x3E000000
+
+/* TPC0_QM_GLBL_PROT */
+#define TPC0_QM_GLBL_PROT_PQF_SHIFT 0
+#define TPC0_QM_GLBL_PROT_PQF_MASK 0xF
+#define TPC0_QM_GLBL_PROT_CQF_SHIFT 4
+#define TPC0_QM_GLBL_PROT_CQF_MASK 0x1F0
+#define TPC0_QM_GLBL_PROT_CP_SHIFT 9
+#define TPC0_QM_GLBL_PROT_CP_MASK 0x3E00
+#define TPC0_QM_GLBL_PROT_ERR_SHIFT 14
+#define TPC0_QM_GLBL_PROT_ERR_MASK 0x4000
+#define TPC0_QM_GLBL_PROT_ARB_SHIFT 15
+#define TPC0_QM_GLBL_PROT_ARB_MASK 0x8000
+
+/* TPC0_QM_GLBL_ERR_CFG */
+#define TPC0_QM_GLBL_ERR_CFG_PQF_ERR_MSG_EN_SHIFT 0
+#define TPC0_QM_GLBL_ERR_CFG_PQF_ERR_MSG_EN_MASK 0xF
+#define TPC0_QM_GLBL_ERR_CFG_CQF_ERR_MSG_EN_SHIFT 4
+#define TPC0_QM_GLBL_ERR_CFG_CQF_ERR_MSG_EN_MASK 0x1F0
+#define TPC0_QM_GLBL_ERR_CFG_CP_ERR_MSG_EN_SHIFT 9
+#define TPC0_QM_GLBL_ERR_CFG_CP_ERR_MSG_EN_MASK 0x3E00
+#define TPC0_QM_GLBL_ERR_CFG_PQF_STOP_ON_ERR_SHIFT 16
+#define TPC0_QM_GLBL_ERR_CFG_PQF_STOP_ON_ERR_MASK 0xF0000
+#define TPC0_QM_GLBL_ERR_CFG_CQF_STOP_ON_ERR_SHIFT 20
+#define TPC0_QM_GLBL_ERR_CFG_CQF_STOP_ON_ERR_MASK 0x1F00000
+#define TPC0_QM_GLBL_ERR_CFG_CP_STOP_ON_ERR_SHIFT 25
+#define TPC0_QM_GLBL_ERR_CFG_CP_STOP_ON_ERR_MASK 0x3E000000
+#define TPC0_QM_GLBL_ERR_CFG_ARB_STOP_ON_ERR_SHIFT 31
+#define TPC0_QM_GLBL_ERR_CFG_ARB_STOP_ON_ERR_MASK 0x80000000
+
+/* TPC0_QM_GLBL_SECURE_PROPS */
+#define TPC0_QM_GLBL_SECURE_PROPS_0_ASID_SHIFT 0
+#define TPC0_QM_GLBL_SECURE_PROPS_0_ASID_MASK 0x3FF
+#define TPC0_QM_GLBL_SECURE_PROPS_1_ASID_SHIFT 0
+#define TPC0_QM_GLBL_SECURE_PROPS_1_ASID_MASK 0x3FF
+#define TPC0_QM_GLBL_SECURE_PROPS_2_ASID_SHIFT 0
+#define TPC0_QM_GLBL_SECURE_PROPS_2_ASID_MASK 0x3FF
+#define TPC0_QM_GLBL_SECURE_PROPS_3_ASID_SHIFT 0
+#define TPC0_QM_GLBL_SECURE_PROPS_3_ASID_MASK 0x3FF
+#define TPC0_QM_GLBL_SECURE_PROPS_4_ASID_SHIFT 0
+#define TPC0_QM_GLBL_SECURE_PROPS_4_ASID_MASK 0x3FF
+#define TPC0_QM_GLBL_SECURE_PROPS_0_MMBP_SHIFT 10
+#define TPC0_QM_GLBL_SECURE_PROPS_0_MMBP_MASK 0x400
+#define TPC0_QM_GLBL_SECURE_PROPS_1_MMBP_SHIFT 10
+#define TPC0_QM_GLBL_SECURE_PROPS_1_MMBP_MASK 0x400
+#define TPC0_QM_GLBL_SECURE_PROPS_2_MMBP_SHIFT 10
+#define TPC0_QM_GLBL_SECURE_PROPS_2_MMBP_MASK 0x400
+#define TPC0_QM_GLBL_SECURE_PROPS_3_MMBP_SHIFT 10
+#define TPC0_QM_GLBL_SECURE_PROPS_3_MMBP_MASK 0x400
+#define TPC0_QM_GLBL_SECURE_PROPS_4_MMBP_SHIFT 10
+#define TPC0_QM_GLBL_SECURE_PROPS_4_MMBP_MASK 0x400
+
+/* TPC0_QM_GLBL_NON_SECURE_PROPS */
+#define TPC0_QM_GLBL_NON_SECURE_PROPS_0_ASID_SHIFT 0
+#define TPC0_QM_GLBL_NON_SECURE_PROPS_0_ASID_MASK 0x3FF
+#define TPC0_QM_GLBL_NON_SECURE_PROPS_1_ASID_SHIFT 0
+#define TPC0_QM_GLBL_NON_SECURE_PROPS_1_ASID_MASK 0x3FF
+#define TPC0_QM_GLBL_NON_SECURE_PROPS_2_ASID_SHIFT 0
+#define TPC0_QM_GLBL_NON_SECURE_PROPS_2_ASID_MASK 0x3FF
+#define TPC0_QM_GLBL_NON_SECURE_PROPS_3_ASID_SHIFT 0
+#define TPC0_QM_GLBL_NON_SECURE_PROPS_3_ASID_MASK 0x3FF
+#define TPC0_QM_GLBL_NON_SECURE_PROPS_4_ASID_SHIFT 0
+#define TPC0_QM_GLBL_NON_SECURE_PROPS_4_ASID_MASK 0x3FF
+#define TPC0_QM_GLBL_NON_SECURE_PROPS_0_MMBP_SHIFT 10
+#define TPC0_QM_GLBL_NON_SECURE_PROPS_0_MMBP_MASK 0x400
+#define TPC0_QM_GLBL_NON_SECURE_PROPS_1_MMBP_SHIFT 10
+#define TPC0_QM_GLBL_NON_SECURE_PROPS_1_MMBP_MASK 0x400
+#define TPC0_QM_GLBL_NON_SECURE_PROPS_2_MMBP_SHIFT 10
+#define TPC0_QM_GLBL_NON_SECURE_PROPS_2_MMBP_MASK 0x400
+#define TPC0_QM_GLBL_NON_SECURE_PROPS_3_MMBP_SHIFT 10
+#define TPC0_QM_GLBL_NON_SECURE_PROPS_3_MMBP_MASK 0x400
+#define TPC0_QM_GLBL_NON_SECURE_PROPS_4_MMBP_SHIFT 10
+#define TPC0_QM_GLBL_NON_SECURE_PROPS_4_MMBP_MASK 0x400
+
+/* TPC0_QM_GLBL_STS0 */
+#define TPC0_QM_GLBL_STS0_PQF_IDLE_SHIFT 0
+#define TPC0_QM_GLBL_STS0_PQF_IDLE_MASK 0xF
+#define TPC0_QM_GLBL_STS0_CQF_IDLE_SHIFT 4
+#define TPC0_QM_GLBL_STS0_CQF_IDLE_MASK 0x1F0
+#define TPC0_QM_GLBL_STS0_CP_IDLE_SHIFT 9
+#define TPC0_QM_GLBL_STS0_CP_IDLE_MASK 0x3E00
+#define TPC0_QM_GLBL_STS0_PQF_IS_STOP_SHIFT 16
+#define TPC0_QM_GLBL_STS0_PQF_IS_STOP_MASK 0xF0000
+#define TPC0_QM_GLBL_STS0_CQF_IS_STOP_SHIFT 20
+#define TPC0_QM_GLBL_STS0_CQF_IS_STOP_MASK 0x1F00000
+#define TPC0_QM_GLBL_STS0_CP_IS_STOP_SHIFT 25
+#define TPC0_QM_GLBL_STS0_CP_IS_STOP_MASK 0x3E000000
+#define TPC0_QM_GLBL_STS0_ARB_IS_STOP_SHIFT 31
+#define TPC0_QM_GLBL_STS0_ARB_IS_STOP_MASK 0x80000000
+
+/* TPC0_QM_GLBL_STS1 */
+#define TPC0_QM_GLBL_STS1_PQF_RD_ERR_SHIFT 0
+#define TPC0_QM_GLBL_STS1_PQF_RD_ERR_MASK 0x1
+#define TPC0_QM_GLBL_STS1_CQF_RD_ERR_SHIFT 1
+#define TPC0_QM_GLBL_STS1_CQF_RD_ERR_MASK 0x2
+#define TPC0_QM_GLBL_STS1_CP_RD_ERR_SHIFT 2
+#define TPC0_QM_GLBL_STS1_CP_RD_ERR_MASK 0x4
+#define TPC0_QM_GLBL_STS1_CP_UNDEF_CMD_ERR_SHIFT 3
+#define TPC0_QM_GLBL_STS1_CP_UNDEF_CMD_ERR_MASK 0x8
+#define TPC0_QM_GLBL_STS1_CP_STOP_OP_SHIFT 4
+#define TPC0_QM_GLBL_STS1_CP_STOP_OP_MASK 0x10
+#define TPC0_QM_GLBL_STS1_CP_MSG_WR_ERR_SHIFT 5
+#define TPC0_QM_GLBL_STS1_CP_MSG_WR_ERR_MASK 0x20
+#define TPC0_QM_GLBL_STS1_CP_WREG_ERR_SHIFT 6
+#define TPC0_QM_GLBL_STS1_CP_WREG_ERR_MASK 0x40
+#define TPC0_QM_GLBL_STS1_CP_FENCE0_OVF_ERR_SHIFT 8
+#define TPC0_QM_GLBL_STS1_CP_FENCE0_OVF_ERR_MASK 0x100
+#define TPC0_QM_GLBL_STS1_CP_FENCE1_OVF_ERR_SHIFT 9
+#define TPC0_QM_GLBL_STS1_CP_FENCE1_OVF_ERR_MASK 0x200
+#define TPC0_QM_GLBL_STS1_CP_FENCE2_OVF_ERR_SHIFT 10
+#define TPC0_QM_GLBL_STS1_CP_FENCE2_OVF_ERR_MASK 0x400
+#define TPC0_QM_GLBL_STS1_CP_FENCE3_OVF_ERR_SHIFT 11
+#define TPC0_QM_GLBL_STS1_CP_FENCE3_OVF_ERR_MASK 0x800
+#define TPC0_QM_GLBL_STS1_CP_FENCE0_UDF_ERR_SHIFT 12
+#define TPC0_QM_GLBL_STS1_CP_FENCE0_UDF_ERR_MASK 0x1000
+#define TPC0_QM_GLBL_STS1_CP_FENCE1_UDF_ERR_SHIFT 13
+#define TPC0_QM_GLBL_STS1_CP_FENCE1_UDF_ERR_MASK 0x2000
+#define TPC0_QM_GLBL_STS1_CP_FENCE2_UDF_ERR_SHIFT 14
+#define TPC0_QM_GLBL_STS1_CP_FENCE2_UDF_ERR_MASK 0x4000
+#define TPC0_QM_GLBL_STS1_CP_FENCE3_UDF_ERR_SHIFT 15
+#define TPC0_QM_GLBL_STS1_CP_FENCE3_UDF_ERR_MASK 0x8000
+
+/* TPC0_QM_GLBL_STS1_4 */
+#define TPC0_QM_GLBL_STS1_4_CQF_RD_ERR_SHIFT 1
+#define TPC0_QM_GLBL_STS1_4_CQF_RD_ERR_MASK 0x2
+#define TPC0_QM_GLBL_STS1_4_CP_RD_ERR_SHIFT 2
+#define TPC0_QM_GLBL_STS1_4_CP_RD_ERR_MASK 0x4
+#define TPC0_QM_GLBL_STS1_4_CP_UNDEF_CMD_ERR_SHIFT 3
+#define TPC0_QM_GLBL_STS1_4_CP_UNDEF_CMD_ERR_MASK 0x8
+#define TPC0_QM_GLBL_STS1_4_CP_STOP_OP_SHIFT 4
+#define TPC0_QM_GLBL_STS1_4_CP_STOP_OP_MASK 0x10
+#define TPC0_QM_GLBL_STS1_4_CP_MSG_WR_ERR_SHIFT 5
+#define TPC0_QM_GLBL_STS1_4_CP_MSG_WR_ERR_MASK 0x20
+#define TPC0_QM_GLBL_STS1_4_CP_WREG_ERR_SHIFT 6
+#define TPC0_QM_GLBL_STS1_4_CP_WREG_ERR_MASK 0x40
+#define TPC0_QM_GLBL_STS1_4_CP_FENCE0_OVF_ERR_SHIFT 8
+#define TPC0_QM_GLBL_STS1_4_CP_FENCE0_OVF_ERR_MASK 0x100
+#define TPC0_QM_GLBL_STS1_4_CP_FENCE1_OVF_ERR_SHIFT 9
+#define TPC0_QM_GLBL_STS1_4_CP_FENCE1_OVF_ERR_MASK 0x200
+#define TPC0_QM_GLBL_STS1_4_CP_FENCE2_OVF_ERR_SHIFT 10
+#define TPC0_QM_GLBL_STS1_4_CP_FENCE2_OVF_ERR_MASK 0x400
+#define TPC0_QM_GLBL_STS1_4_CP_FENCE3_OVF_ERR_SHIFT 11
+#define TPC0_QM_GLBL_STS1_4_CP_FENCE3_OVF_ERR_MASK 0x800
+#define TPC0_QM_GLBL_STS1_4_CP_FENCE0_UDF_ERR_SHIFT 12
+#define TPC0_QM_GLBL_STS1_4_CP_FENCE0_UDF_ERR_MASK 0x1000
+#define TPC0_QM_GLBL_STS1_4_CP_FENCE1_UDF_ERR_SHIFT 13
+#define TPC0_QM_GLBL_STS1_4_CP_FENCE1_UDF_ERR_MASK 0x2000
+#define TPC0_QM_GLBL_STS1_4_CP_FENCE2_UDF_ERR_SHIFT 14
+#define TPC0_QM_GLBL_STS1_4_CP_FENCE2_UDF_ERR_MASK 0x4000
+#define TPC0_QM_GLBL_STS1_4_CP_FENCE3_UDF_ERR_SHIFT 15
+#define TPC0_QM_GLBL_STS1_4_CP_FENCE3_UDF_ERR_MASK 0x8000
+
+/* TPC0_QM_GLBL_MSG_EN */
+#define TPC0_QM_GLBL_MSG_EN_PQF_RD_ERR_SHIFT 0
+#define TPC0_QM_GLBL_MSG_EN_PQF_RD_ERR_MASK 0x1
+#define TPC0_QM_GLBL_MSG_EN_CQF_RD_ERR_SHIFT 1
+#define TPC0_QM_GLBL_MSG_EN_CQF_RD_ERR_MASK 0x2
+#define TPC0_QM_GLBL_MSG_EN_CP_RD_ERR_SHIFT 2
+#define TPC0_QM_GLBL_MSG_EN_CP_RD_ERR_MASK 0x4
+#define TPC0_QM_GLBL_MSG_EN_CP_UNDEF_CMD_ERR_SHIFT 3
+#define TPC0_QM_GLBL_MSG_EN_CP_UNDEF_CMD_ERR_MASK 0x8
+#define TPC0_QM_GLBL_MSG_EN_CP_STOP_OP_SHIFT 4
+#define TPC0_QM_GLBL_MSG_EN_CP_STOP_OP_MASK 0x10
+#define TPC0_QM_GLBL_MSG_EN_CP_MSG_WR_ERR_SHIFT 5
+#define TPC0_QM_GLBL_MSG_EN_CP_MSG_WR_ERR_MASK 0x20
+#define TPC0_QM_GLBL_MSG_EN_CP_WREG_ERR_SHIFT 6
+#define TPC0_QM_GLBL_MSG_EN_CP_WREG_ERR_MASK 0x40
+#define TPC0_QM_GLBL_MSG_EN_CP_FENCE0_OVF_ERR_SHIFT 8
+#define TPC0_QM_GLBL_MSG_EN_CP_FENCE0_OVF_ERR_MASK 0x100
+#define TPC0_QM_GLBL_MSG_EN_CP_FENCE1_OVF_ERR_SHIFT 9
+#define TPC0_QM_GLBL_MSG_EN_CP_FENCE1_OVF_ERR_MASK 0x200
+#define TPC0_QM_GLBL_MSG_EN_CP_FENCE2_OVF_ERR_SHIFT 10
+#define TPC0_QM_GLBL_MSG_EN_CP_FENCE2_OVF_ERR_MASK 0x400
+#define TPC0_QM_GLBL_MSG_EN_CP_FENCE3_OVF_ERR_SHIFT 11
+#define TPC0_QM_GLBL_MSG_EN_CP_FENCE3_OVF_ERR_MASK 0x800
+#define TPC0_QM_GLBL_MSG_EN_CP_FENCE0_UDF_ERR_SHIFT 12
+#define TPC0_QM_GLBL_MSG_EN_CP_FENCE0_UDF_ERR_MASK 0x1000
+#define TPC0_QM_GLBL_MSG_EN_CP_FENCE1_UDF_ERR_SHIFT 13
+#define TPC0_QM_GLBL_MSG_EN_CP_FENCE1_UDF_ERR_MASK 0x2000
+#define TPC0_QM_GLBL_MSG_EN_CP_FENCE2_UDF_ERR_SHIFT 14
+#define TPC0_QM_GLBL_MSG_EN_CP_FENCE2_UDF_ERR_MASK 0x4000
+#define TPC0_QM_GLBL_MSG_EN_CP_FENCE3_UDF_ERR_SHIFT 15
+#define TPC0_QM_GLBL_MSG_EN_CP_FENCE3_UDF_ERR_MASK 0x8000
+
+/* TPC0_QM_GLBL_MSG_EN_4 */
+#define TPC0_QM_GLBL_MSG_EN_4_CQF_RD_ERR_SHIFT 1
+#define TPC0_QM_GLBL_MSG_EN_4_CQF_RD_ERR_MASK 0x2
+#define TPC0_QM_GLBL_MSG_EN_4_CP_RD_ERR_SHIFT 2
+#define TPC0_QM_GLBL_MSG_EN_4_CP_RD_ERR_MASK 0x4
+#define TPC0_QM_GLBL_MSG_EN_4_CP_UNDEF_CMD_ERR_SHIFT 3
+#define TPC0_QM_GLBL_MSG_EN_4_CP_UNDEF_CMD_ERR_MASK 0x8
+#define TPC0_QM_GLBL_MSG_EN_4_CP_STOP_OP_SHIFT 4
+#define TPC0_QM_GLBL_MSG_EN_4_CP_STOP_OP_MASK 0x10
+#define TPC0_QM_GLBL_MSG_EN_4_CP_MSG_WR_ERR_SHIFT 5
+#define TPC0_QM_GLBL_MSG_EN_4_CP_MSG_WR_ERR_MASK 0x20
+#define TPC0_QM_GLBL_MSG_EN_4_CP_WREG_ERR_SHIFT 6
+#define TPC0_QM_GLBL_MSG_EN_4_CP_WREG_ERR_MASK 0x40
+#define TPC0_QM_GLBL_MSG_EN_4_CP_FENCE0_OVF_ERR_SHIFT 8
+#define TPC0_QM_GLBL_MSG_EN_4_CP_FENCE0_OVF_ERR_MASK 0x100
+#define TPC0_QM_GLBL_MSG_EN_4_CP_FENCE1_OVF_ERR_SHIFT 9
+#define TPC0_QM_GLBL_MSG_EN_4_CP_FENCE1_OVF_ERR_MASK 0x200
+#define TPC0_QM_GLBL_MSG_EN_4_CP_FENCE2_OVF_ERR_SHIFT 10
+#define TPC0_QM_GLBL_MSG_EN_4_CP_FENCE2_OVF_ERR_MASK 0x400
+#define TPC0_QM_GLBL_MSG_EN_4_CP_FENCE3_OVF_ERR_SHIFT 11
+#define TPC0_QM_GLBL_MSG_EN_4_CP_FENCE3_OVF_ERR_MASK 0x800
+#define TPC0_QM_GLBL_MSG_EN_4_CP_FENCE0_UDF_ERR_SHIFT 12
+#define TPC0_QM_GLBL_MSG_EN_4_CP_FENCE0_UDF_ERR_MASK 0x1000
+#define TPC0_QM_GLBL_MSG_EN_4_CP_FENCE1_UDF_ERR_SHIFT 13
+#define TPC0_QM_GLBL_MSG_EN_4_CP_FENCE1_UDF_ERR_MASK 0x2000
+#define TPC0_QM_GLBL_MSG_EN_4_CP_FENCE2_UDF_ERR_SHIFT 14
+#define TPC0_QM_GLBL_MSG_EN_4_CP_FENCE2_UDF_ERR_MASK 0x4000
+#define TPC0_QM_GLBL_MSG_EN_4_CP_FENCE3_UDF_ERR_SHIFT 15
+#define TPC0_QM_GLBL_MSG_EN_4_CP_FENCE3_UDF_ERR_MASK 0x8000
+
+/* TPC0_QM_PQ_BASE_LO */
+#define TPC0_QM_PQ_BASE_LO_VAL_SHIFT 0
+#define TPC0_QM_PQ_BASE_LO_VAL_MASK 0xFFFFFFFF
+
+/* TPC0_QM_PQ_BASE_HI */
+#define TPC0_QM_PQ_BASE_HI_VAL_SHIFT 0
+#define TPC0_QM_PQ_BASE_HI_VAL_MASK 0xFFFFFFFF
+
+/* TPC0_QM_PQ_SIZE */
+#define TPC0_QM_PQ_SIZE_VAL_SHIFT 0
+#define TPC0_QM_PQ_SIZE_VAL_MASK 0xFFFFFFFF
+
+/* TPC0_QM_PQ_PI */
+#define TPC0_QM_PQ_PI_VAL_SHIFT 0
+#define TPC0_QM_PQ_PI_VAL_MASK 0xFFFFFFFF
+
+/* TPC0_QM_PQ_CI */
+#define TPC0_QM_PQ_CI_VAL_SHIFT 0
+#define TPC0_QM_PQ_CI_VAL_MASK 0xFFFFFFFF
+
+/* TPC0_QM_PQ_CFG0 */
+#define TPC0_QM_PQ_CFG0_RESERVED_SHIFT 0
+#define TPC0_QM_PQ_CFG0_RESERVED_MASK 0x1
+
+/* TPC0_QM_PQ_CFG1 */
+#define TPC0_QM_PQ_CFG1_CREDIT_LIM_SHIFT 0
+#define TPC0_QM_PQ_CFG1_CREDIT_LIM_MASK 0xFFFF
+#define TPC0_QM_PQ_CFG1_MAX_INFLIGHT_SHIFT 16
+#define TPC0_QM_PQ_CFG1_MAX_INFLIGHT_MASK 0xFFFF0000
+
+/* TPC0_QM_PQ_ARUSER_31_11 */
+#define TPC0_QM_PQ_ARUSER_31_11_VAL_SHIFT 0
+#define TPC0_QM_PQ_ARUSER_31_11_VAL_MASK 0x1FFFFF
+
+/* TPC0_QM_PQ_STS0 */
+#define TPC0_QM_PQ_STS0_PQ_CREDIT_CNT_SHIFT 0
+#define TPC0_QM_PQ_STS0_PQ_CREDIT_CNT_MASK 0xFFFF
+#define TPC0_QM_PQ_STS0_PQ_FREE_CNT_SHIFT 16
+#define TPC0_QM_PQ_STS0_PQ_FREE_CNT_MASK 0xFFFF0000
+
+/* TPC0_QM_PQ_STS1 */
+#define TPC0_QM_PQ_STS1_PQ_INFLIGHT_CNT_SHIFT 0
+#define TPC0_QM_PQ_STS1_PQ_INFLIGHT_CNT_MASK 0xFFFF
+#define TPC0_QM_PQ_STS1_PQ_BUF_EMPTY_SHIFT 30
+#define TPC0_QM_PQ_STS1_PQ_BUF_EMPTY_MASK 0x40000000
+#define TPC0_QM_PQ_STS1_PQ_BUSY_SHIFT 31
+#define TPC0_QM_PQ_STS1_PQ_BUSY_MASK 0x80000000
+
+/* TPC0_QM_CQ_CFG0 */
+#define TPC0_QM_CQ_CFG0_RESERVED_SHIFT 0
+#define TPC0_QM_CQ_CFG0_RESERVED_MASK 0x1
+
+/* TPC0_QM_CQ_CFG1 */
+#define TPC0_QM_CQ_CFG1_CREDIT_LIM_SHIFT 0
+#define TPC0_QM_CQ_CFG1_CREDIT_LIM_MASK 0xFFFF
+#define TPC0_QM_CQ_CFG1_MAX_INFLIGHT_SHIFT 16
+#define TPC0_QM_CQ_CFG1_MAX_INFLIGHT_MASK 0xFFFF0000
+
+/* TPC0_QM_CQ_ARUSER_31_11 */
+#define TPC0_QM_CQ_ARUSER_31_11_VAL_SHIFT 0
+#define TPC0_QM_CQ_ARUSER_31_11_VAL_MASK 0x1FFFFF
+
+/* TPC0_QM_CQ_STS0 */
+#define TPC0_QM_CQ_STS0_CQ_CREDIT_CNT_SHIFT 0
+#define TPC0_QM_CQ_STS0_CQ_CREDIT_CNT_MASK 0xFFFF
+#define TPC0_QM_CQ_STS0_CQ_FREE_CNT_SHIFT 16
+#define TPC0_QM_CQ_STS0_CQ_FREE_CNT_MASK 0xFFFF0000
+
+/* TPC0_QM_CQ_STS1 */
+#define TPC0_QM_CQ_STS1_CQ_INFLIGHT_CNT_SHIFT 0
+#define TPC0_QM_CQ_STS1_CQ_INFLIGHT_CNT_MASK 0xFFFF
+#define TPC0_QM_CQ_STS1_CQ_BUF_EMPTY_SHIFT 30
+#define TPC0_QM_CQ_STS1_CQ_BUF_EMPTY_MASK 0x40000000
+#define TPC0_QM_CQ_STS1_CQ_BUSY_SHIFT 31
+#define TPC0_QM_CQ_STS1_CQ_BUSY_MASK 0x80000000
+
+/* TPC0_QM_CQ_PTR_LO_0 */
+#define TPC0_QM_CQ_PTR_LO_0_VAL_SHIFT 0
+#define TPC0_QM_CQ_PTR_LO_0_VAL_MASK 0xFFFFFFFF
+
+/* TPC0_QM_CQ_PTR_HI_0 */
+#define TPC0_QM_CQ_PTR_HI_0_VAL_SHIFT 0
+#define TPC0_QM_CQ_PTR_HI_0_VAL_MASK 0xFFFFFFFF
+
+/* TPC0_QM_CQ_TSIZE_0 */
+#define TPC0_QM_CQ_TSIZE_0_VAL_SHIFT 0
+#define TPC0_QM_CQ_TSIZE_0_VAL_MASK 0xFFFFFFFF
+
+/* TPC0_QM_CQ_CTL_0 */
+#define TPC0_QM_CQ_CTL_0_RPT_SHIFT 0
+#define TPC0_QM_CQ_CTL_0_RPT_MASK 0xFFFF
+#define TPC0_QM_CQ_CTL_0_CTL_SHIFT 16
+#define TPC0_QM_CQ_CTL_0_CTL_MASK 0xFFFF0000
+
+/* TPC0_QM_CQ_PTR_LO_1 */
+#define TPC0_QM_CQ_PTR_LO_1_VAL_SHIFT 0
+#define TPC0_QM_CQ_PTR_LO_1_VAL_MASK 0xFFFFFFFF
+
+/* TPC0_QM_CQ_PTR_HI_1 */
+#define TPC0_QM_CQ_PTR_HI_1_VAL_SHIFT 0
+#define TPC0_QM_CQ_PTR_HI_1_VAL_MASK 0xFFFFFFFF
+
+/* TPC0_QM_CQ_TSIZE_1 */
+#define TPC0_QM_CQ_TSIZE_1_VAL_SHIFT 0
+#define TPC0_QM_CQ_TSIZE_1_VAL_MASK 0xFFFFFFFF
+
+/* TPC0_QM_CQ_CTL_1 */
+#define TPC0_QM_CQ_CTL_1_RPT_SHIFT 0
+#define TPC0_QM_CQ_CTL_1_RPT_MASK 0xFFFF
+#define TPC0_QM_CQ_CTL_1_CTL_SHIFT 16
+#define TPC0_QM_CQ_CTL_1_CTL_MASK 0xFFFF0000
+
+/* TPC0_QM_CQ_PTR_LO_2 */
+#define TPC0_QM_CQ_PTR_LO_2_VAL_SHIFT 0
+#define TPC0_QM_CQ_PTR_LO_2_VAL_MASK 0xFFFFFFFF
+
+/* TPC0_QM_CQ_PTR_HI_2 */
+#define TPC0_QM_CQ_PTR_HI_2_VAL_SHIFT 0
+#define TPC0_QM_CQ_PTR_HI_2_VAL_MASK 0xFFFFFFFF
+
+/* TPC0_QM_CQ_TSIZE_2 */
+#define TPC0_QM_CQ_TSIZE_2_VAL_SHIFT 0
+#define TPC0_QM_CQ_TSIZE_2_VAL_MASK 0xFFFFFFFF
+
+/* TPC0_QM_CQ_CTL_2 */
+#define TPC0_QM_CQ_CTL_2_RPT_SHIFT 0
+#define TPC0_QM_CQ_CTL_2_RPT_MASK 0xFFFF
+#define TPC0_QM_CQ_CTL_2_CTL_SHIFT 16
+#define TPC0_QM_CQ_CTL_2_CTL_MASK 0xFFFF0000
+
+/* TPC0_QM_CQ_PTR_LO_3 */
+#define TPC0_QM_CQ_PTR_LO_3_VAL_SHIFT 0
+#define TPC0_QM_CQ_PTR_LO_3_VAL_MASK 0xFFFFFFFF
+
+/* TPC0_QM_CQ_PTR_HI_3 */
+#define TPC0_QM_CQ_PTR_HI_3_VAL_SHIFT 0
+#define TPC0_QM_CQ_PTR_HI_3_VAL_MASK 0xFFFFFFFF
+
+/* TPC0_QM_CQ_TSIZE_3 */
+#define TPC0_QM_CQ_TSIZE_3_VAL_SHIFT 0
+#define TPC0_QM_CQ_TSIZE_3_VAL_MASK 0xFFFFFFFF
+
+/* TPC0_QM_CQ_CTL_3 */
+#define TPC0_QM_CQ_CTL_3_RPT_SHIFT 0
+#define TPC0_QM_CQ_CTL_3_RPT_MASK 0xFFFF
+#define TPC0_QM_CQ_CTL_3_CTL_SHIFT 16
+#define TPC0_QM_CQ_CTL_3_CTL_MASK 0xFFFF0000
+
+/* TPC0_QM_CQ_PTR_LO_4 */
+#define TPC0_QM_CQ_PTR_LO_4_VAL_SHIFT 0
+#define TPC0_QM_CQ_PTR_LO_4_VAL_MASK 0xFFFFFFFF
+
+/* TPC0_QM_CQ_PTR_HI_4 */
+#define TPC0_QM_CQ_PTR_HI_4_VAL_SHIFT 0
+#define TPC0_QM_CQ_PTR_HI_4_VAL_MASK 0xFFFFFFFF
+
+/* TPC0_QM_CQ_TSIZE_4 */
+#define TPC0_QM_CQ_TSIZE_4_VAL_SHIFT 0
+#define TPC0_QM_CQ_TSIZE_4_VAL_MASK 0xFFFFFFFF
+
+/* TPC0_QM_CQ_CTL_4 */
+#define TPC0_QM_CQ_CTL_4_RPT_SHIFT 0
+#define TPC0_QM_CQ_CTL_4_RPT_MASK 0xFFFF
+#define TPC0_QM_CQ_CTL_4_CTL_SHIFT 16
+#define TPC0_QM_CQ_CTL_4_CTL_MASK 0xFFFF0000
+
+/* TPC0_QM_CQ_PTR_LO_STS */
+#define TPC0_QM_CQ_PTR_LO_STS_VAL_SHIFT 0
+#define TPC0_QM_CQ_PTR_LO_STS_VAL_MASK 0xFFFFFFFF
+
+/* TPC0_QM_CQ_PTR_HI_STS */
+#define TPC0_QM_CQ_PTR_HI_STS_VAL_SHIFT 0
+#define TPC0_QM_CQ_PTR_HI_STS_VAL_MASK 0xFFFFFFFF
+
+/* TPC0_QM_CQ_TSIZE_STS */
+#define TPC0_QM_CQ_TSIZE_STS_VAL_SHIFT 0
+#define TPC0_QM_CQ_TSIZE_STS_VAL_MASK 0xFFFFFFFF
+
+/* TPC0_QM_CQ_CTL_STS */
+#define TPC0_QM_CQ_CTL_STS_RPT_SHIFT 0
+#define TPC0_QM_CQ_CTL_STS_RPT_MASK 0xFFFF
+#define TPC0_QM_CQ_CTL_STS_CTL_SHIFT 16
+#define TPC0_QM_CQ_CTL_STS_CTL_MASK 0xFFFF0000
+
+/* TPC0_QM_CQ_IFIFO_CNT */
+#define TPC0_QM_CQ_IFIFO_CNT_VAL_SHIFT 0
+#define TPC0_QM_CQ_IFIFO_CNT_VAL_MASK 0x3
+
+/* TPC0_QM_CP_MSG_BASE0_ADDR_LO */
+#define TPC0_QM_CP_MSG_BASE0_ADDR_LO_VAL_SHIFT 0
+#define TPC0_QM_CP_MSG_BASE0_ADDR_LO_VAL_MASK 0xFFFFFFFF
+
+/* TPC0_QM_CP_MSG_BASE0_ADDR_HI */
+#define TPC0_QM_CP_MSG_BASE0_ADDR_HI_VAL_SHIFT 0
+#define TPC0_QM_CP_MSG_BASE0_ADDR_HI_VAL_MASK 0xFFFFFFFF
+
+/* TPC0_QM_CP_MSG_BASE1_ADDR_LO */
+#define TPC0_QM_CP_MSG_BASE1_ADDR_LO_VAL_SHIFT 0
+#define TPC0_QM_CP_MSG_BASE1_ADDR_LO_VAL_MASK 0xFFFFFFFF
+
+/* TPC0_QM_CP_MSG_BASE1_ADDR_HI */
+#define TPC0_QM_CP_MSG_BASE1_ADDR_HI_VAL_SHIFT 0
+#define TPC0_QM_CP_MSG_BASE1_ADDR_HI_VAL_MASK 0xFFFFFFFF
+
+/* TPC0_QM_CP_MSG_BASE2_ADDR_LO */
+#define TPC0_QM_CP_MSG_BASE2_ADDR_LO_VAL_SHIFT 0
+#define TPC0_QM_CP_MSG_BASE2_ADDR_LO_VAL_MASK 0xFFFFFFFF
+
+/* TPC0_QM_CP_MSG_BASE2_ADDR_HI */
+#define TPC0_QM_CP_MSG_BASE2_ADDR_HI_VAL_SHIFT 0
+#define TPC0_QM_CP_MSG_BASE2_ADDR_HI_VAL_MASK 0xFFFFFFFF
+
+/* TPC0_QM_CP_MSG_BASE3_ADDR_LO */
+#define TPC0_QM_CP_MSG_BASE3_ADDR_LO_VAL_SHIFT 0
+#define TPC0_QM_CP_MSG_BASE3_ADDR_LO_VAL_MASK 0xFFFFFFFF
+
+/* TPC0_QM_CP_MSG_BASE3_ADDR_HI */
+#define TPC0_QM_CP_MSG_BASE3_ADDR_HI_VAL_SHIFT 0
+#define TPC0_QM_CP_MSG_BASE3_ADDR_HI_VAL_MASK 0xFFFFFFFF
+
+/* TPC0_QM_CP_LDMA_TSIZE_OFFSET */
+#define TPC0_QM_CP_LDMA_TSIZE_OFFSET_VAL_SHIFT 0
+#define TPC0_QM_CP_LDMA_TSIZE_OFFSET_VAL_MASK 0xFFFFFFFF
+
+/* TPC0_QM_CP_LDMA_SRC_BASE_LO_OFFSET */
+#define TPC0_QM_CP_LDMA_SRC_BASE_LO_OFFSET_VAL_SHIFT 0
+#define TPC0_QM_CP_LDMA_SRC_BASE_LO_OFFSET_VAL_MASK 0xFFFFFFFF
+
+/* TPC0_QM_CP_LDMA_DST_BASE_LO_OFFSET */
+#define TPC0_QM_CP_LDMA_DST_BASE_LO_OFFSET_VAL_SHIFT 0
+#define TPC0_QM_CP_LDMA_DST_BASE_LO_OFFSET_VAL_MASK 0xFFFFFFFF
+
+/* TPC0_QM_CP_FENCE0_RDATA */
+#define TPC0_QM_CP_FENCE0_RDATA_INC_VAL_SHIFT 0
+#define TPC0_QM_CP_FENCE0_RDATA_INC_VAL_MASK 0xF
+
+/* TPC0_QM_CP_FENCE1_RDATA */
+#define TPC0_QM_CP_FENCE1_RDATA_INC_VAL_SHIFT 0
+#define TPC0_QM_CP_FENCE1_RDATA_INC_VAL_MASK 0xF
+
+/* TPC0_QM_CP_FENCE2_RDATA */
+#define TPC0_QM_CP_FENCE2_RDATA_INC_VAL_SHIFT 0
+#define TPC0_QM_CP_FENCE2_RDATA_INC_VAL_MASK 0xF
+
+/* TPC0_QM_CP_FENCE3_RDATA */
+#define TPC0_QM_CP_FENCE3_RDATA_INC_VAL_SHIFT 0
+#define TPC0_QM_CP_FENCE3_RDATA_INC_VAL_MASK 0xF
+
+/* TPC0_QM_CP_FENCE0_CNT */
+#define TPC0_QM_CP_FENCE0_CNT_VAL_SHIFT 0
+#define TPC0_QM_CP_FENCE0_CNT_VAL_MASK 0x3FFF
+
+/* TPC0_QM_CP_FENCE1_CNT */
+#define TPC0_QM_CP_FENCE1_CNT_VAL_SHIFT 0
+#define TPC0_QM_CP_FENCE1_CNT_VAL_MASK 0x3FFF
+
+/* TPC0_QM_CP_FENCE2_CNT */
+#define TPC0_QM_CP_FENCE2_CNT_VAL_SHIFT 0
+#define TPC0_QM_CP_FENCE2_CNT_VAL_MASK 0x3FFF
+
+/* TPC0_QM_CP_FENCE3_CNT */
+#define TPC0_QM_CP_FENCE3_CNT_VAL_SHIFT 0
+#define TPC0_QM_CP_FENCE3_CNT_VAL_MASK 0x3FFF
+
+/* TPC0_QM_CP_STS */
+#define TPC0_QM_CP_STS_MSG_INFLIGHT_CNT_SHIFT 0
+#define TPC0_QM_CP_STS_MSG_INFLIGHT_CNT_MASK 0xFFFF
+#define TPC0_QM_CP_STS_ERDY_SHIFT 16
+#define TPC0_QM_CP_STS_ERDY_MASK 0x10000
+#define TPC0_QM_CP_STS_RRDY_SHIFT 17
+#define TPC0_QM_CP_STS_RRDY_MASK 0x20000
+#define TPC0_QM_CP_STS_MRDY_SHIFT 18
+#define TPC0_QM_CP_STS_MRDY_MASK 0x40000
+#define TPC0_QM_CP_STS_SW_STOP_SHIFT 19
+#define TPC0_QM_CP_STS_SW_STOP_MASK 0x80000
+#define TPC0_QM_CP_STS_FENCE_ID_SHIFT 20
+#define TPC0_QM_CP_STS_FENCE_ID_MASK 0x300000
+#define TPC0_QM_CP_STS_FENCE_IN_PROGRESS_SHIFT 22
+#define TPC0_QM_CP_STS_FENCE_IN_PROGRESS_MASK 0x400000
+
+/* TPC0_QM_CP_CURRENT_INST_LO */
+#define TPC0_QM_CP_CURRENT_INST_LO_VAL_SHIFT 0
+#define TPC0_QM_CP_CURRENT_INST_LO_VAL_MASK 0xFFFFFFFF
+
+/* TPC0_QM_CP_CURRENT_INST_HI */
+#define TPC0_QM_CP_CURRENT_INST_HI_VAL_SHIFT 0
+#define TPC0_QM_CP_CURRENT_INST_HI_VAL_MASK 0xFFFFFFFF
+
+/* TPC0_QM_CP_BARRIER_CFG */
+#define TPC0_QM_CP_BARRIER_CFG_EBGUARD_SHIFT 0
+#define TPC0_QM_CP_BARRIER_CFG_EBGUARD_MASK 0xFFF
+#define TPC0_QM_CP_BARRIER_CFG_RBGUARD_SHIFT 16
+#define TPC0_QM_CP_BARRIER_CFG_RBGUARD_MASK 0xF0000
+
+/* TPC0_QM_CP_DBG_0 */
+#define TPC0_QM_CP_DBG_0_CS_SHIFT 0
+#define TPC0_QM_CP_DBG_0_CS_MASK 0xF
+#define TPC0_QM_CP_DBG_0_EB_CNT_NOT_ZERO_SHIFT 4
+#define TPC0_QM_CP_DBG_0_EB_CNT_NOT_ZERO_MASK 0x10
+#define TPC0_QM_CP_DBG_0_BULK_CNT_NOT_ZERO_SHIFT 5
+#define TPC0_QM_CP_DBG_0_BULK_CNT_NOT_ZERO_MASK 0x20
+#define TPC0_QM_CP_DBG_0_MREB_STALL_SHIFT 6
+#define TPC0_QM_CP_DBG_0_MREB_STALL_MASK 0x40
+#define TPC0_QM_CP_DBG_0_STALL_SHIFT 7
+#define TPC0_QM_CP_DBG_0_STALL_MASK 0x80
+
+/* TPC0_QM_CP_ARUSER_31_11 */
+#define TPC0_QM_CP_ARUSER_31_11_VAL_SHIFT 0
+#define TPC0_QM_CP_ARUSER_31_11_VAL_MASK 0x1FFFFF
+
+/* TPC0_QM_CP_AWUSER_31_11 */
+#define TPC0_QM_CP_AWUSER_31_11_VAL_SHIFT 0
+#define TPC0_QM_CP_AWUSER_31_11_VAL_MASK 0x1FFFFF
+
+/* TPC0_QM_ARB_CFG_0 */
+#define TPC0_QM_ARB_CFG_0_TYPE_SHIFT 0
+#define TPC0_QM_ARB_CFG_0_TYPE_MASK 0x1
+#define TPC0_QM_ARB_CFG_0_IS_MASTER_SHIFT 4
+#define TPC0_QM_ARB_CFG_0_IS_MASTER_MASK 0x10
+#define TPC0_QM_ARB_CFG_0_EN_SHIFT 8
+#define TPC0_QM_ARB_CFG_0_EN_MASK 0x100
+#define TPC0_QM_ARB_CFG_0_MASK_SHIFT 12
+#define TPC0_QM_ARB_CFG_0_MASK_MASK 0xF000
+#define TPC0_QM_ARB_CFG_0_MST_MSG_NOSTALL_SHIFT 16
+#define TPC0_QM_ARB_CFG_0_MST_MSG_NOSTALL_MASK 0x10000
+
+/* TPC0_QM_ARB_CHOISE_Q_PUSH */
+#define TPC0_QM_ARB_CHOISE_Q_PUSH_VAL_SHIFT 0
+#define TPC0_QM_ARB_CHOISE_Q_PUSH_VAL_MASK 0x3
+
+/* TPC0_QM_ARB_WRR_WEIGHT */
+#define TPC0_QM_ARB_WRR_WEIGHT_VAL_SHIFT 0
+#define TPC0_QM_ARB_WRR_WEIGHT_VAL_MASK 0xFFFFFFFF
+
+/* TPC0_QM_ARB_CFG_1 */
+#define TPC0_QM_ARB_CFG_1_CLR_SHIFT 0
+#define TPC0_QM_ARB_CFG_1_CLR_MASK 0x1
+
+/* TPC0_QM_ARB_MST_AVAIL_CRED */
+#define TPC0_QM_ARB_MST_AVAIL_CRED_VAL_SHIFT 0
+#define TPC0_QM_ARB_MST_AVAIL_CRED_VAL_MASK 0x7F
+
+/* TPC0_QM_ARB_MST_CRED_INC */
+#define TPC0_QM_ARB_MST_CRED_INC_VAL_SHIFT 0
+#define TPC0_QM_ARB_MST_CRED_INC_VAL_MASK 0xFFFFFFFF
+
+/* TPC0_QM_ARB_MST_CHOISE_PUSH_OFST */
+#define TPC0_QM_ARB_MST_CHOISE_PUSH_OFST_VAL_SHIFT 0
+#define TPC0_QM_ARB_MST_CHOISE_PUSH_OFST_VAL_MASK 0xFFFFFFFF
+
+/* TPC0_QM_ARB_SLV_MASTER_INC_CRED_OFST */
+#define TPC0_QM_ARB_SLV_MASTER_INC_CRED_OFST_VAL_SHIFT 0
+#define TPC0_QM_ARB_SLV_MASTER_INC_CRED_OFST_VAL_MASK 0xFFFFFFFF
+
+/* TPC0_QM_ARB_MST_SLAVE_EN */
+#define TPC0_QM_ARB_MST_SLAVE_EN_VAL_SHIFT 0
+#define TPC0_QM_ARB_MST_SLAVE_EN_VAL_MASK 0xFFFFFFFF
+
+/* TPC0_QM_ARB_MST_QUIET_PER */
+#define TPC0_QM_ARB_MST_QUIET_PER_VAL_SHIFT 0
+#define TPC0_QM_ARB_MST_QUIET_PER_VAL_MASK 0xFFFFFFFF
+
+/* TPC0_QM_ARB_SLV_CHOISE_WDT */
+#define TPC0_QM_ARB_SLV_CHOISE_WDT_VAL_SHIFT 0
+#define TPC0_QM_ARB_SLV_CHOISE_WDT_VAL_MASK 0xFFFFFFFF
+
+/* TPC0_QM_ARB_SLV_ID */
+#define TPC0_QM_ARB_SLV_ID_VAL_SHIFT 0
+#define TPC0_QM_ARB_SLV_ID_VAL_MASK 0x1F
+
+/* TPC0_QM_ARB_MSG_MAX_INFLIGHT */
+#define TPC0_QM_ARB_MSG_MAX_INFLIGHT_VAL_SHIFT 0
+#define TPC0_QM_ARB_MSG_MAX_INFLIGHT_VAL_MASK 0x3F
+
+/* TPC0_QM_ARB_MSG_AWUSER_31_11 */
+#define TPC0_QM_ARB_MSG_AWUSER_31_11_VAL_SHIFT 0
+#define TPC0_QM_ARB_MSG_AWUSER_31_11_VAL_MASK 0x1FFFFF
+
+/* TPC0_QM_ARB_MSG_AWUSER_SEC_PROP */
+#define TPC0_QM_ARB_MSG_AWUSER_SEC_PROP_ASID_SHIFT 0
+#define TPC0_QM_ARB_MSG_AWUSER_SEC_PROP_ASID_MASK 0x3FF
+#define TPC0_QM_ARB_MSG_AWUSER_SEC_PROP_MMBP_SHIFT 10
+#define TPC0_QM_ARB_MSG_AWUSER_SEC_PROP_MMBP_MASK 0x400
+
+/* TPC0_QM_ARB_MSG_AWUSER_NON_SEC_PROP */
+#define TPC0_QM_ARB_MSG_AWUSER_NON_SEC_PROP_ASID_SHIFT 0
+#define TPC0_QM_ARB_MSG_AWUSER_NON_SEC_PROP_ASID_MASK 0x3FF
+#define TPC0_QM_ARB_MSG_AWUSER_NON_SEC_PROP_MMBP_SHIFT 10
+#define TPC0_QM_ARB_MSG_AWUSER_NON_SEC_PROP_MMBP_MASK 0x400
+
+/* TPC0_QM_ARB_BASE_LO */
+#define TPC0_QM_ARB_BASE_LO_VAL_SHIFT 0
+#define TPC0_QM_ARB_BASE_LO_VAL_MASK 0xFFFFFFFF
+
+/* TPC0_QM_ARB_BASE_HI */
+#define TPC0_QM_ARB_BASE_HI_VAL_SHIFT 0
+#define TPC0_QM_ARB_BASE_HI_VAL_MASK 0xFFFFFFFF
+
+/* TPC0_QM_ARB_STATE_STS */
+#define TPC0_QM_ARB_STATE_STS_VAL_SHIFT 0
+#define TPC0_QM_ARB_STATE_STS_VAL_MASK 0xFFFFFFFF
+
+/* TPC0_QM_ARB_CHOISE_FULLNESS_STS */
+#define TPC0_QM_ARB_CHOISE_FULLNESS_STS_VAL_SHIFT 0
+#define TPC0_QM_ARB_CHOISE_FULLNESS_STS_VAL_MASK 0x7F
+
+/* TPC0_QM_ARB_MSG_STS */
+#define TPC0_QM_ARB_MSG_STS_FULL_SHIFT 0
+#define TPC0_QM_ARB_MSG_STS_FULL_MASK 0x1
+#define TPC0_QM_ARB_MSG_STS_NO_INFLIGHT_SHIFT 1
+#define TPC0_QM_ARB_MSG_STS_NO_INFLIGHT_MASK 0x2
+
+/* TPC0_QM_ARB_SLV_CHOISE_Q_HEAD */
+#define TPC0_QM_ARB_SLV_CHOISE_Q_HEAD_VAL_SHIFT 0
+#define TPC0_QM_ARB_SLV_CHOISE_Q_HEAD_VAL_MASK 0x3
+
+/* TPC0_QM_ARB_ERR_CAUSE */
+#define TPC0_QM_ARB_ERR_CAUSE_CHOISE_OVF_SHIFT 0
+#define TPC0_QM_ARB_ERR_CAUSE_CHOISE_OVF_MASK 0x1
+#define TPC0_QM_ARB_ERR_CAUSE_CHOISE_WDT_SHIFT 1
+#define TPC0_QM_ARB_ERR_CAUSE_CHOISE_WDT_MASK 0x2
+#define TPC0_QM_ARB_ERR_CAUSE_AXI_LBW_ERR_SHIFT 2
+#define TPC0_QM_ARB_ERR_CAUSE_AXI_LBW_ERR_MASK 0x4
+
+/* TPC0_QM_ARB_ERR_MSG_EN */
+#define TPC0_QM_ARB_ERR_MSG_EN_CHOISE_OVF_SHIFT 0
+#define TPC0_QM_ARB_ERR_MSG_EN_CHOISE_OVF_MASK 0x1
+#define TPC0_QM_ARB_ERR_MSG_EN_CHOISE_WDT_SHIFT 1
+#define TPC0_QM_ARB_ERR_MSG_EN_CHOISE_WDT_MASK 0x2
+#define TPC0_QM_ARB_ERR_MSG_EN_AXI_LBW_ERR_SHIFT 2
+#define TPC0_QM_ARB_ERR_MSG_EN_AXI_LBW_ERR_MASK 0x4
+
+/* TPC0_QM_ARB_ERR_STS_DRP */
+#define TPC0_QM_ARB_ERR_STS_DRP_VAL_SHIFT 0
+#define TPC0_QM_ARB_ERR_STS_DRP_VAL_MASK 0x3
+
+/* TPC0_QM_ARB_MST_CRED_STS */
+#define TPC0_QM_ARB_MST_CRED_STS_VAL_SHIFT 0
+#define TPC0_QM_ARB_MST_CRED_STS_VAL_MASK 0x7F
+
+/* TPC0_QM_CGM_CFG */
+#define TPC0_QM_CGM_CFG_IDLE_TH_SHIFT 0
+#define TPC0_QM_CGM_CFG_IDLE_TH_MASK 0xFFF
+#define TPC0_QM_CGM_CFG_G2F_TH_SHIFT 16
+#define TPC0_QM_CGM_CFG_G2F_TH_MASK 0xFF0000
+#define TPC0_QM_CGM_CFG_CP_IDLE_MASK_SHIFT 24
+#define TPC0_QM_CGM_CFG_CP_IDLE_MASK_MASK 0x1F000000
+#define TPC0_QM_CGM_CFG_EN_SHIFT 31
+#define TPC0_QM_CGM_CFG_EN_MASK 0x80000000
+
+/* TPC0_QM_CGM_STS */
+#define TPC0_QM_CGM_STS_ST_SHIFT 0
+#define TPC0_QM_CGM_STS_ST_MASK 0x3
+#define TPC0_QM_CGM_STS_CG_SHIFT 4
+#define TPC0_QM_CGM_STS_CG_MASK 0x10
+#define TPC0_QM_CGM_STS_AGENT_IDLE_SHIFT 8
+#define TPC0_QM_CGM_STS_AGENT_IDLE_MASK 0x100
+#define TPC0_QM_CGM_STS_AXI_IDLE_SHIFT 9
+#define TPC0_QM_CGM_STS_AXI_IDLE_MASK 0x200
+#define TPC0_QM_CGM_STS_CP_IDLE_SHIFT 10
+#define TPC0_QM_CGM_STS_CP_IDLE_MASK 0x400
+
+/* TPC0_QM_CGM_CFG1 */
+#define TPC0_QM_CGM_CFG1_MASK_TH_SHIFT 0
+#define TPC0_QM_CGM_CFG1_MASK_TH_MASK 0xFF
+
+/* TPC0_QM_LOCAL_RANGE_BASE */
+#define TPC0_QM_LOCAL_RANGE_BASE_VAL_SHIFT 0
+#define TPC0_QM_LOCAL_RANGE_BASE_VAL_MASK 0xFFFF
+
+/* TPC0_QM_LOCAL_RANGE_SIZE */
+#define TPC0_QM_LOCAL_RANGE_SIZE_VAL_SHIFT 0
+#define TPC0_QM_LOCAL_RANGE_SIZE_VAL_MASK 0xFFFF
+
+/* TPC0_QM_CSMR_STRICT_PRIO_CFG */
+#define TPC0_QM_CSMR_STRICT_PRIO_CFG_TYPE_SHIFT 0
+#define TPC0_QM_CSMR_STRICT_PRIO_CFG_TYPE_MASK 0x1
+
+/* TPC0_QM_HBW_RD_RATE_LIM_CFG_1 */
+#define TPC0_QM_HBW_RD_RATE_LIM_CFG_1_TOUT_SHIFT 0
+#define TPC0_QM_HBW_RD_RATE_LIM_CFG_1_TOUT_MASK 0xFF
+#define TPC0_QM_HBW_RD_RATE_LIM_CFG_1_EN_SHIFT 31
+#define TPC0_QM_HBW_RD_RATE_LIM_CFG_1_EN_MASK 0x80000000
+
+/* TPC0_QM_LBW_WR_RATE_LIM_CFG_0 */
+#define TPC0_QM_LBW_WR_RATE_LIM_CFG_0_RST_TOKEN_SHIFT 0
+#define TPC0_QM_LBW_WR_RATE_LIM_CFG_0_RST_TOKEN_MASK 0xFF
+#define TPC0_QM_LBW_WR_RATE_LIM_CFG_0_SAT_SHIFT 16
+#define TPC0_QM_LBW_WR_RATE_LIM_CFG_0_SAT_MASK 0xFF0000
+
+/* TPC0_QM_LBW_WR_RATE_LIM_CFG_1 */
+#define TPC0_QM_LBW_WR_RATE_LIM_CFG_1_TOUT_SHIFT 0
+#define TPC0_QM_LBW_WR_RATE_LIM_CFG_1_TOUT_MASK 0xFF
+#define TPC0_QM_LBW_WR_RATE_LIM_CFG_1_EN_SHIFT 31
+#define TPC0_QM_LBW_WR_RATE_LIM_CFG_1_EN_MASK 0x80000000
+
+/* TPC0_QM_HBW_RD_RATE_LIM_CFG_0 */
+#define TPC0_QM_HBW_RD_RATE_LIM_CFG_0_RST_TOKEN_SHIFT 0
+#define TPC0_QM_HBW_RD_RATE_LIM_CFG_0_RST_TOKEN_MASK 0xFF
+#define TPC0_QM_HBW_RD_RATE_LIM_CFG_0_SAT_SHIFT 16
+#define TPC0_QM_HBW_RD_RATE_LIM_CFG_0_SAT_MASK 0xFF0000
+
+/* TPC0_QM_GLBL_AXCACHE */
+#define TPC0_QM_GLBL_AXCACHE_AR_SHIFT 0
+#define TPC0_QM_GLBL_AXCACHE_AR_MASK 0xF
+#define TPC0_QM_GLBL_AXCACHE_AW_SHIFT 16
+#define TPC0_QM_GLBL_AXCACHE_AW_MASK 0xF0000
+
+/* TPC0_QM_IND_GW_APB_CFG */
+#define TPC0_QM_IND_GW_APB_CFG_ADDR_SHIFT 0
+#define TPC0_QM_IND_GW_APB_CFG_ADDR_MASK 0x7FFFFFFF
+#define TPC0_QM_IND_GW_APB_CFG_CMD_SHIFT 31
+#define TPC0_QM_IND_GW_APB_CFG_CMD_MASK 0x80000000
+
+/* TPC0_QM_IND_GW_APB_WDATA */
+#define TPC0_QM_IND_GW_APB_WDATA_VAL_SHIFT 0
+#define TPC0_QM_IND_GW_APB_WDATA_VAL_MASK 0xFFFFFFFF
+
+/* TPC0_QM_IND_GW_APB_RDATA */
+#define TPC0_QM_IND_GW_APB_RDATA_VAL_SHIFT 0
+#define TPC0_QM_IND_GW_APB_RDATA_VAL_MASK 0xFFFFFFFF
+
+/* TPC0_QM_IND_GW_APB_STATUS */
+#define TPC0_QM_IND_GW_APB_STATUS_RDY_SHIFT 0
+#define TPC0_QM_IND_GW_APB_STATUS_RDY_MASK 0x1
+#define TPC0_QM_IND_GW_APB_STATUS_ERR_SHIFT 1
+#define TPC0_QM_IND_GW_APB_STATUS_ERR_MASK 0x2
+
+/* TPC0_QM_GLBL_ERR_ADDR_LO */
+#define TPC0_QM_GLBL_ERR_ADDR_LO_VAL_SHIFT 0
+#define TPC0_QM_GLBL_ERR_ADDR_LO_VAL_MASK 0xFFFFFFFF
+
+/* TPC0_QM_GLBL_ERR_ADDR_HI */
+#define TPC0_QM_GLBL_ERR_ADDR_HI_VAL_SHIFT 0
+#define TPC0_QM_GLBL_ERR_ADDR_HI_VAL_MASK 0xFFFFFFFF
+
+/* TPC0_QM_GLBL_ERR_WDATA */
+#define TPC0_QM_GLBL_ERR_WDATA_VAL_SHIFT 0
+#define TPC0_QM_GLBL_ERR_WDATA_VAL_MASK 0xFFFFFFFF
+
+/* TPC0_QM_GLBL_MEM_INIT_BUSY */
+#define TPC0_QM_GLBL_MEM_INIT_BUSY_RBUF_SHIFT 0
+#define TPC0_QM_GLBL_MEM_INIT_BUSY_RBUF_MASK 0xF
+
+#endif /* ASIC_REG_TPC0_QM_MASKS_H_ */
diff --git a/drivers/accel/habanalabs/include/gaudi/asic_reg/tpc0_qm_regs.h b/drivers/accel/habanalabs/include/gaudi/asic_reg/tpc0_qm_regs.h
new file mode 100644
index 0000000000..f9e310ab6d
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi/asic_reg/tpc0_qm_regs.h
@@ -0,0 +1,834 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2016-2018 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ ** DO NOT EDIT BELOW **
+ ************************************/
+
+#ifndef ASIC_REG_TPC0_QM_REGS_H_
+#define ASIC_REG_TPC0_QM_REGS_H_
+
+/*
+ *****************************************
+ * TPC0_QM (Prototype: QMAN)
+ *****************************************
+ */
+
+#define mmTPC0_QM_GLBL_CFG0 0xE08000
+
+#define mmTPC0_QM_GLBL_CFG1 0xE08004
+
+#define mmTPC0_QM_GLBL_PROT 0xE08008
+
+#define mmTPC0_QM_GLBL_ERR_CFG 0xE0800C
+
+#define mmTPC0_QM_GLBL_SECURE_PROPS_0 0xE08010
+
+#define mmTPC0_QM_GLBL_SECURE_PROPS_1 0xE08014
+
+#define mmTPC0_QM_GLBL_SECURE_PROPS_2 0xE08018
+
+#define mmTPC0_QM_GLBL_SECURE_PROPS_3 0xE0801C
+
+#define mmTPC0_QM_GLBL_SECURE_PROPS_4 0xE08020
+
+#define mmTPC0_QM_GLBL_NON_SECURE_PROPS_0 0xE08024
+
+#define mmTPC0_QM_GLBL_NON_SECURE_PROPS_1 0xE08028
+
+#define mmTPC0_QM_GLBL_NON_SECURE_PROPS_2 0xE0802C
+
+#define mmTPC0_QM_GLBL_NON_SECURE_PROPS_3 0xE08030
+
+#define mmTPC0_QM_GLBL_NON_SECURE_PROPS_4 0xE08034
+
+#define mmTPC0_QM_GLBL_STS0 0xE08038
+
+#define mmTPC0_QM_GLBL_STS1_0 0xE08040
+
+#define mmTPC0_QM_GLBL_STS1_1 0xE08044
+
+#define mmTPC0_QM_GLBL_STS1_2 0xE08048
+
+#define mmTPC0_QM_GLBL_STS1_3 0xE0804C
+
+#define mmTPC0_QM_GLBL_STS1_4 0xE08050
+
+#define mmTPC0_QM_GLBL_MSG_EN_0 0xE08054
+
+#define mmTPC0_QM_GLBL_MSG_EN_1 0xE08058
+
+#define mmTPC0_QM_GLBL_MSG_EN_2 0xE0805C
+
+#define mmTPC0_QM_GLBL_MSG_EN_3 0xE08060
+
+#define mmTPC0_QM_GLBL_MSG_EN_4 0xE08068
+
+#define mmTPC0_QM_PQ_BASE_LO_0 0xE08070
+
+#define mmTPC0_QM_PQ_BASE_LO_1 0xE08074
+
+#define mmTPC0_QM_PQ_BASE_LO_2 0xE08078
+
+#define mmTPC0_QM_PQ_BASE_LO_3 0xE0807C
+
+#define mmTPC0_QM_PQ_BASE_HI_0 0xE08080
+
+#define mmTPC0_QM_PQ_BASE_HI_1 0xE08084
+
+#define mmTPC0_QM_PQ_BASE_HI_2 0xE08088
+
+#define mmTPC0_QM_PQ_BASE_HI_3 0xE0808C
+
+#define mmTPC0_QM_PQ_SIZE_0 0xE08090
+
+#define mmTPC0_QM_PQ_SIZE_1 0xE08094
+
+#define mmTPC0_QM_PQ_SIZE_2 0xE08098
+
+#define mmTPC0_QM_PQ_SIZE_3 0xE0809C
+
+#define mmTPC0_QM_PQ_PI_0 0xE080A0
+
+#define mmTPC0_QM_PQ_PI_1 0xE080A4
+
+#define mmTPC0_QM_PQ_PI_2 0xE080A8
+
+#define mmTPC0_QM_PQ_PI_3 0xE080AC
+
+#define mmTPC0_QM_PQ_CI_0 0xE080B0
+
+#define mmTPC0_QM_PQ_CI_1 0xE080B4
+
+#define mmTPC0_QM_PQ_CI_2 0xE080B8
+
+#define mmTPC0_QM_PQ_CI_3 0xE080BC
+
+#define mmTPC0_QM_PQ_CFG0_0 0xE080C0
+
+#define mmTPC0_QM_PQ_CFG0_1 0xE080C4
+
+#define mmTPC0_QM_PQ_CFG0_2 0xE080C8
+
+#define mmTPC0_QM_PQ_CFG0_3 0xE080CC
+
+#define mmTPC0_QM_PQ_CFG1_0 0xE080D0
+
+#define mmTPC0_QM_PQ_CFG1_1 0xE080D4
+
+#define mmTPC0_QM_PQ_CFG1_2 0xE080D8
+
+#define mmTPC0_QM_PQ_CFG1_3 0xE080DC
+
+#define mmTPC0_QM_PQ_ARUSER_31_11_0 0xE080E0
+
+#define mmTPC0_QM_PQ_ARUSER_31_11_1 0xE080E4
+
+#define mmTPC0_QM_PQ_ARUSER_31_11_2 0xE080E8
+
+#define mmTPC0_QM_PQ_ARUSER_31_11_3 0xE080EC
+
+#define mmTPC0_QM_PQ_STS0_0 0xE080F0
+
+#define mmTPC0_QM_PQ_STS0_1 0xE080F4
+
+#define mmTPC0_QM_PQ_STS0_2 0xE080F8
+
+#define mmTPC0_QM_PQ_STS0_3 0xE080FC
+
+#define mmTPC0_QM_PQ_STS1_0 0xE08100
+
+#define mmTPC0_QM_PQ_STS1_1 0xE08104
+
+#define mmTPC0_QM_PQ_STS1_2 0xE08108
+
+#define mmTPC0_QM_PQ_STS1_3 0xE0810C
+
+#define mmTPC0_QM_CQ_CFG0_0 0xE08110
+
+#define mmTPC0_QM_CQ_CFG0_1 0xE08114
+
+#define mmTPC0_QM_CQ_CFG0_2 0xE08118
+
+#define mmTPC0_QM_CQ_CFG0_3 0xE0811C
+
+#define mmTPC0_QM_CQ_CFG0_4 0xE08120
+
+#define mmTPC0_QM_CQ_CFG1_0 0xE08124
+
+#define mmTPC0_QM_CQ_CFG1_1 0xE08128
+
+#define mmTPC0_QM_CQ_CFG1_2 0xE0812C
+
+#define mmTPC0_QM_CQ_CFG1_3 0xE08130
+
+#define mmTPC0_QM_CQ_CFG1_4 0xE08134
+
+#define mmTPC0_QM_CQ_ARUSER_31_11_0 0xE08138
+
+#define mmTPC0_QM_CQ_ARUSER_31_11_1 0xE0813C
+
+#define mmTPC0_QM_CQ_ARUSER_31_11_2 0xE08140
+
+#define mmTPC0_QM_CQ_ARUSER_31_11_3 0xE08144
+
+#define mmTPC0_QM_CQ_ARUSER_31_11_4 0xE08148
+
+#define mmTPC0_QM_CQ_STS0_0 0xE0814C
+
+#define mmTPC0_QM_CQ_STS0_1 0xE08150
+
+#define mmTPC0_QM_CQ_STS0_2 0xE08154
+
+#define mmTPC0_QM_CQ_STS0_3 0xE08158
+
+#define mmTPC0_QM_CQ_STS0_4 0xE0815C
+
+#define mmTPC0_QM_CQ_STS1_0 0xE08160
+
+#define mmTPC0_QM_CQ_STS1_1 0xE08164
+
+#define mmTPC0_QM_CQ_STS1_2 0xE08168
+
+#define mmTPC0_QM_CQ_STS1_3 0xE0816C
+
+#define mmTPC0_QM_CQ_STS1_4 0xE08170
+
+#define mmTPC0_QM_CQ_PTR_LO_0 0xE08174
+
+#define mmTPC0_QM_CQ_PTR_HI_0 0xE08178
+
+#define mmTPC0_QM_CQ_TSIZE_0 0xE0817C
+
+#define mmTPC0_QM_CQ_CTL_0 0xE08180
+
+#define mmTPC0_QM_CQ_PTR_LO_1 0xE08184
+
+#define mmTPC0_QM_CQ_PTR_HI_1 0xE08188
+
+#define mmTPC0_QM_CQ_TSIZE_1 0xE0818C
+
+#define mmTPC0_QM_CQ_CTL_1 0xE08190
+
+#define mmTPC0_QM_CQ_PTR_LO_2 0xE08194
+
+#define mmTPC0_QM_CQ_PTR_HI_2 0xE08198
+
+#define mmTPC0_QM_CQ_TSIZE_2 0xE0819C
+
+#define mmTPC0_QM_CQ_CTL_2 0xE081A0
+
+#define mmTPC0_QM_CQ_PTR_LO_3 0xE081A4
+
+#define mmTPC0_QM_CQ_PTR_HI_3 0xE081A8
+
+#define mmTPC0_QM_CQ_TSIZE_3 0xE081AC
+
+#define mmTPC0_QM_CQ_CTL_3 0xE081B0
+
+#define mmTPC0_QM_CQ_PTR_LO_4 0xE081B4
+
+#define mmTPC0_QM_CQ_PTR_HI_4 0xE081B8
+
+#define mmTPC0_QM_CQ_TSIZE_4 0xE081BC
+
+#define mmTPC0_QM_CQ_CTL_4 0xE081C0
+
+#define mmTPC0_QM_CQ_PTR_LO_STS_0 0xE081C4
+
+#define mmTPC0_QM_CQ_PTR_LO_STS_1 0xE081C8
+
+#define mmTPC0_QM_CQ_PTR_LO_STS_2 0xE081CC
+
+#define mmTPC0_QM_CQ_PTR_LO_STS_3 0xE081D0
+
+#define mmTPC0_QM_CQ_PTR_LO_STS_4 0xE081D4
+
+#define mmTPC0_QM_CQ_PTR_HI_STS_0 0xE081D8
+
+#define mmTPC0_QM_CQ_PTR_HI_STS_1 0xE081DC
+
+#define mmTPC0_QM_CQ_PTR_HI_STS_2 0xE081E0
+
+#define mmTPC0_QM_CQ_PTR_HI_STS_3 0xE081E4
+
+#define mmTPC0_QM_CQ_PTR_HI_STS_4 0xE081E8
+
+#define mmTPC0_QM_CQ_TSIZE_STS_0 0xE081EC
+
+#define mmTPC0_QM_CQ_TSIZE_STS_1 0xE081F0
+
+#define mmTPC0_QM_CQ_TSIZE_STS_2 0xE081F4
+
+#define mmTPC0_QM_CQ_TSIZE_STS_3 0xE081F8
+
+#define mmTPC0_QM_CQ_TSIZE_STS_4 0xE081FC
+
+#define mmTPC0_QM_CQ_CTL_STS_0 0xE08200
+
+#define mmTPC0_QM_CQ_CTL_STS_1 0xE08204
+
+#define mmTPC0_QM_CQ_CTL_STS_2 0xE08208
+
+#define mmTPC0_QM_CQ_CTL_STS_3 0xE0820C
+
+#define mmTPC0_QM_CQ_CTL_STS_4 0xE08210
+
+#define mmTPC0_QM_CQ_IFIFO_CNT_0 0xE08214
+
+#define mmTPC0_QM_CQ_IFIFO_CNT_1 0xE08218
+
+#define mmTPC0_QM_CQ_IFIFO_CNT_2 0xE0821C
+
+#define mmTPC0_QM_CQ_IFIFO_CNT_3 0xE08220
+
+#define mmTPC0_QM_CQ_IFIFO_CNT_4 0xE08224
+
+#define mmTPC0_QM_CP_MSG_BASE0_ADDR_LO_0 0xE08228
+
+#define mmTPC0_QM_CP_MSG_BASE0_ADDR_LO_1 0xE0822C
+
+#define mmTPC0_QM_CP_MSG_BASE0_ADDR_LO_2 0xE08230
+
+#define mmTPC0_QM_CP_MSG_BASE0_ADDR_LO_3 0xE08234
+
+#define mmTPC0_QM_CP_MSG_BASE0_ADDR_LO_4 0xE08238
+
+#define mmTPC0_QM_CP_MSG_BASE0_ADDR_HI_0 0xE0823C
+
+#define mmTPC0_QM_CP_MSG_BASE0_ADDR_HI_1 0xE08240
+
+#define mmTPC0_QM_CP_MSG_BASE0_ADDR_HI_2 0xE08244
+
+#define mmTPC0_QM_CP_MSG_BASE0_ADDR_HI_3 0xE08248
+
+#define mmTPC0_QM_CP_MSG_BASE0_ADDR_HI_4 0xE0824C
+
+#define mmTPC0_QM_CP_MSG_BASE1_ADDR_LO_0 0xE08250
+
+#define mmTPC0_QM_CP_MSG_BASE1_ADDR_LO_1 0xE08254
+
+#define mmTPC0_QM_CP_MSG_BASE1_ADDR_LO_2 0xE08258
+
+#define mmTPC0_QM_CP_MSG_BASE1_ADDR_LO_3 0xE0825C
+
+#define mmTPC0_QM_CP_MSG_BASE1_ADDR_LO_4 0xE08260
+
+#define mmTPC0_QM_CP_MSG_BASE1_ADDR_HI_0 0xE08264
+
+#define mmTPC0_QM_CP_MSG_BASE1_ADDR_HI_1 0xE08268
+
+#define mmTPC0_QM_CP_MSG_BASE1_ADDR_HI_2 0xE0826C
+
+#define mmTPC0_QM_CP_MSG_BASE1_ADDR_HI_3 0xE08270
+
+#define mmTPC0_QM_CP_MSG_BASE1_ADDR_HI_4 0xE08274
+
+#define mmTPC0_QM_CP_MSG_BASE2_ADDR_LO_0 0xE08278
+
+#define mmTPC0_QM_CP_MSG_BASE2_ADDR_LO_1 0xE0827C
+
+#define mmTPC0_QM_CP_MSG_BASE2_ADDR_LO_2 0xE08280
+
+#define mmTPC0_QM_CP_MSG_BASE2_ADDR_LO_3 0xE08284
+
+#define mmTPC0_QM_CP_MSG_BASE2_ADDR_LO_4 0xE08288
+
+#define mmTPC0_QM_CP_MSG_BASE2_ADDR_HI_0 0xE0828C
+
+#define mmTPC0_QM_CP_MSG_BASE2_ADDR_HI_1 0xE08290
+
+#define mmTPC0_QM_CP_MSG_BASE2_ADDR_HI_2 0xE08294
+
+#define mmTPC0_QM_CP_MSG_BASE2_ADDR_HI_3 0xE08298
+
+#define mmTPC0_QM_CP_MSG_BASE2_ADDR_HI_4 0xE0829C
+
+#define mmTPC0_QM_CP_MSG_BASE3_ADDR_LO_0 0xE082A0
+
+#define mmTPC0_QM_CP_MSG_BASE3_ADDR_LO_1 0xE082A4
+
+#define mmTPC0_QM_CP_MSG_BASE3_ADDR_LO_2 0xE082A8
+
+#define mmTPC0_QM_CP_MSG_BASE3_ADDR_LO_3 0xE082AC
+
+#define mmTPC0_QM_CP_MSG_BASE3_ADDR_LO_4 0xE082B0
+
+#define mmTPC0_QM_CP_MSG_BASE3_ADDR_HI_0 0xE082B4
+
+#define mmTPC0_QM_CP_MSG_BASE3_ADDR_HI_1 0xE082B8
+
+#define mmTPC0_QM_CP_MSG_BASE3_ADDR_HI_2 0xE082BC
+
+#define mmTPC0_QM_CP_MSG_BASE3_ADDR_HI_3 0xE082C0
+
+#define mmTPC0_QM_CP_MSG_BASE3_ADDR_HI_4 0xE082C4
+
+#define mmTPC0_QM_CP_LDMA_TSIZE_OFFSET_0 0xE082C8
+
+#define mmTPC0_QM_CP_LDMA_TSIZE_OFFSET_1 0xE082CC
+
+#define mmTPC0_QM_CP_LDMA_TSIZE_OFFSET_2 0xE082D0
+
+#define mmTPC0_QM_CP_LDMA_TSIZE_OFFSET_3 0xE082D4
+
+#define mmTPC0_QM_CP_LDMA_TSIZE_OFFSET_4 0xE082D8
+
+#define mmTPC0_QM_CP_LDMA_SRC_BASE_LO_OFFSET_0 0xE082E0
+
+#define mmTPC0_QM_CP_LDMA_SRC_BASE_LO_OFFSET_1 0xE082E4
+
+#define mmTPC0_QM_CP_LDMA_SRC_BASE_LO_OFFSET_2 0xE082E8
+
+#define mmTPC0_QM_CP_LDMA_SRC_BASE_LO_OFFSET_3 0xE082EC
+
+#define mmTPC0_QM_CP_LDMA_SRC_BASE_LO_OFFSET_4 0xE082F0
+
+#define mmTPC0_QM_CP_LDMA_DST_BASE_LO_OFFSET_0 0xE082F4
+
+#define mmTPC0_QM_CP_LDMA_DST_BASE_LO_OFFSET_1 0xE082F8
+
+#define mmTPC0_QM_CP_LDMA_DST_BASE_LO_OFFSET_2 0xE082FC
+
+#define mmTPC0_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 0xE08300
+
+#define mmTPC0_QM_CP_LDMA_DST_BASE_LO_OFFSET_4 0xE08304
+
+#define mmTPC0_QM_CP_FENCE0_RDATA_0 0xE08308
+
+#define mmTPC0_QM_CP_FENCE0_RDATA_1 0xE0830C
+
+#define mmTPC0_QM_CP_FENCE0_RDATA_2 0xE08310
+
+#define mmTPC0_QM_CP_FENCE0_RDATA_3 0xE08314
+
+#define mmTPC0_QM_CP_FENCE0_RDATA_4 0xE08318
+
+#define mmTPC0_QM_CP_FENCE1_RDATA_0 0xE0831C
+
+#define mmTPC0_QM_CP_FENCE1_RDATA_1 0xE08320
+
+#define mmTPC0_QM_CP_FENCE1_RDATA_2 0xE08324
+
+#define mmTPC0_QM_CP_FENCE1_RDATA_3 0xE08328
+
+#define mmTPC0_QM_CP_FENCE1_RDATA_4 0xE0832C
+
+#define mmTPC0_QM_CP_FENCE2_RDATA_0 0xE08330
+
+#define mmTPC0_QM_CP_FENCE2_RDATA_1 0xE08334
+
+#define mmTPC0_QM_CP_FENCE2_RDATA_2 0xE08338
+
+#define mmTPC0_QM_CP_FENCE2_RDATA_3 0xE0833C
+
+#define mmTPC0_QM_CP_FENCE2_RDATA_4 0xE08340
+
+#define mmTPC0_QM_CP_FENCE3_RDATA_0 0xE08344
+
+#define mmTPC0_QM_CP_FENCE3_RDATA_1 0xE08348
+
+#define mmTPC0_QM_CP_FENCE3_RDATA_2 0xE0834C
+
+#define mmTPC0_QM_CP_FENCE3_RDATA_3 0xE08350
+
+#define mmTPC0_QM_CP_FENCE3_RDATA_4 0xE08354
+
+#define mmTPC0_QM_CP_FENCE0_CNT_0 0xE08358
+
+#define mmTPC0_QM_CP_FENCE0_CNT_1 0xE0835C
+
+#define mmTPC0_QM_CP_FENCE0_CNT_2 0xE08360
+
+#define mmTPC0_QM_CP_FENCE0_CNT_3 0xE08364
+
+#define mmTPC0_QM_CP_FENCE0_CNT_4 0xE08368
+
+#define mmTPC0_QM_CP_FENCE1_CNT_0 0xE0836C
+
+#define mmTPC0_QM_CP_FENCE1_CNT_1 0xE08370
+
+#define mmTPC0_QM_CP_FENCE1_CNT_2 0xE08374
+
+#define mmTPC0_QM_CP_FENCE1_CNT_3 0xE08378
+
+#define mmTPC0_QM_CP_FENCE1_CNT_4 0xE0837C
+
+#define mmTPC0_QM_CP_FENCE2_CNT_0 0xE08380
+
+#define mmTPC0_QM_CP_FENCE2_CNT_1 0xE08384
+
+#define mmTPC0_QM_CP_FENCE2_CNT_2 0xE08388
+
+#define mmTPC0_QM_CP_FENCE2_CNT_3 0xE0838C
+
+#define mmTPC0_QM_CP_FENCE2_CNT_4 0xE08390
+
+#define mmTPC0_QM_CP_FENCE3_CNT_0 0xE08394
+
+#define mmTPC0_QM_CP_FENCE3_CNT_1 0xE08398
+
+#define mmTPC0_QM_CP_FENCE3_CNT_2 0xE0839C
+
+#define mmTPC0_QM_CP_FENCE3_CNT_3 0xE083A0
+
+#define mmTPC0_QM_CP_FENCE3_CNT_4 0xE083A4
+
+#define mmTPC0_QM_CP_STS_0 0xE083A8
+
+#define mmTPC0_QM_CP_STS_1 0xE083AC
+
+#define mmTPC0_QM_CP_STS_2 0xE083B0
+
+#define mmTPC0_QM_CP_STS_3 0xE083B4
+
+#define mmTPC0_QM_CP_STS_4 0xE083B8
+
+#define mmTPC0_QM_CP_CURRENT_INST_LO_0 0xE083BC
+
+#define mmTPC0_QM_CP_CURRENT_INST_LO_1 0xE083C0
+
+#define mmTPC0_QM_CP_CURRENT_INST_LO_2 0xE083C4
+
+#define mmTPC0_QM_CP_CURRENT_INST_LO_3 0xE083C8
+
+#define mmTPC0_QM_CP_CURRENT_INST_LO_4 0xE083CC
+
+#define mmTPC0_QM_CP_CURRENT_INST_HI_0 0xE083D0
+
+#define mmTPC0_QM_CP_CURRENT_INST_HI_1 0xE083D4
+
+#define mmTPC0_QM_CP_CURRENT_INST_HI_2 0xE083D8
+
+#define mmTPC0_QM_CP_CURRENT_INST_HI_3 0xE083DC
+
+#define mmTPC0_QM_CP_CURRENT_INST_HI_4 0xE083E0
+
+#define mmTPC0_QM_CP_BARRIER_CFG_0 0xE083F4
+
+#define mmTPC0_QM_CP_BARRIER_CFG_1 0xE083F8
+
+#define mmTPC0_QM_CP_BARRIER_CFG_2 0xE083FC
+
+#define mmTPC0_QM_CP_BARRIER_CFG_3 0xE08400
+
+#define mmTPC0_QM_CP_BARRIER_CFG_4 0xE08404
+
+#define mmTPC0_QM_CP_DBG_0_0 0xE08408
+
+#define mmTPC0_QM_CP_DBG_0_1 0xE0840C
+
+#define mmTPC0_QM_CP_DBG_0_2 0xE08410
+
+#define mmTPC0_QM_CP_DBG_0_3 0xE08414
+
+#define mmTPC0_QM_CP_DBG_0_4 0xE08418
+
+#define mmTPC0_QM_CP_ARUSER_31_11_0 0xE0841C
+
+#define mmTPC0_QM_CP_ARUSER_31_11_1 0xE08420
+
+#define mmTPC0_QM_CP_ARUSER_31_11_2 0xE08424
+
+#define mmTPC0_QM_CP_ARUSER_31_11_3 0xE08428
+
+#define mmTPC0_QM_CP_ARUSER_31_11_4 0xE0842C
+
+#define mmTPC0_QM_CP_AWUSER_31_11_0 0xE08430
+
+#define mmTPC0_QM_CP_AWUSER_31_11_1 0xE08434
+
+#define mmTPC0_QM_CP_AWUSER_31_11_2 0xE08438
+
+#define mmTPC0_QM_CP_AWUSER_31_11_3 0xE0843C
+
+#define mmTPC0_QM_CP_AWUSER_31_11_4 0xE08440
+
+#define mmTPC0_QM_ARB_CFG_0 0xE08A00
+
+#define mmTPC0_QM_ARB_CHOISE_Q_PUSH 0xE08A04
+
+#define mmTPC0_QM_ARB_WRR_WEIGHT_0 0xE08A08
+
+#define mmTPC0_QM_ARB_WRR_WEIGHT_1 0xE08A0C
+
+#define mmTPC0_QM_ARB_WRR_WEIGHT_2 0xE08A10
+
+#define mmTPC0_QM_ARB_WRR_WEIGHT_3 0xE08A14
+
+#define mmTPC0_QM_ARB_CFG_1 0xE08A18
+
+#define mmTPC0_QM_ARB_MST_AVAIL_CRED_0 0xE08A20
+
+#define mmTPC0_QM_ARB_MST_AVAIL_CRED_1 0xE08A24
+
+#define mmTPC0_QM_ARB_MST_AVAIL_CRED_2 0xE08A28
+
+#define mmTPC0_QM_ARB_MST_AVAIL_CRED_3 0xE08A2C
+
+#define mmTPC0_QM_ARB_MST_AVAIL_CRED_4 0xE08A30
+
+#define mmTPC0_QM_ARB_MST_AVAIL_CRED_5 0xE08A34
+
+#define mmTPC0_QM_ARB_MST_AVAIL_CRED_6 0xE08A38
+
+#define mmTPC0_QM_ARB_MST_AVAIL_CRED_7 0xE08A3C
+
+#define mmTPC0_QM_ARB_MST_AVAIL_CRED_8 0xE08A40
+
+#define mmTPC0_QM_ARB_MST_AVAIL_CRED_9 0xE08A44
+
+#define mmTPC0_QM_ARB_MST_AVAIL_CRED_10 0xE08A48
+
+#define mmTPC0_QM_ARB_MST_AVAIL_CRED_11 0xE08A4C
+
+#define mmTPC0_QM_ARB_MST_AVAIL_CRED_12 0xE08A50
+
+#define mmTPC0_QM_ARB_MST_AVAIL_CRED_13 0xE08A54
+
+#define mmTPC0_QM_ARB_MST_AVAIL_CRED_14 0xE08A58
+
+#define mmTPC0_QM_ARB_MST_AVAIL_CRED_15 0xE08A5C
+
+#define mmTPC0_QM_ARB_MST_AVAIL_CRED_16 0xE08A60
+
+#define mmTPC0_QM_ARB_MST_AVAIL_CRED_17 0xE08A64
+
+#define mmTPC0_QM_ARB_MST_AVAIL_CRED_18 0xE08A68
+
+#define mmTPC0_QM_ARB_MST_AVAIL_CRED_19 0xE08A6C
+
+#define mmTPC0_QM_ARB_MST_AVAIL_CRED_20 0xE08A70
+
+#define mmTPC0_QM_ARB_MST_AVAIL_CRED_21 0xE08A74
+
+#define mmTPC0_QM_ARB_MST_AVAIL_CRED_22 0xE08A78
+
+#define mmTPC0_QM_ARB_MST_AVAIL_CRED_23 0xE08A7C
+
+#define mmTPC0_QM_ARB_MST_AVAIL_CRED_24 0xE08A80
+
+#define mmTPC0_QM_ARB_MST_AVAIL_CRED_25 0xE08A84
+
+#define mmTPC0_QM_ARB_MST_AVAIL_CRED_26 0xE08A88
+
+#define mmTPC0_QM_ARB_MST_AVAIL_CRED_27 0xE08A8C
+
+#define mmTPC0_QM_ARB_MST_AVAIL_CRED_28 0xE08A90
+
+#define mmTPC0_QM_ARB_MST_AVAIL_CRED_29 0xE08A94
+
+#define mmTPC0_QM_ARB_MST_AVAIL_CRED_30 0xE08A98
+
+#define mmTPC0_QM_ARB_MST_AVAIL_CRED_31 0xE08A9C
+
+#define mmTPC0_QM_ARB_MST_CRED_INC 0xE08AA0
+
+#define mmTPC0_QM_ARB_MST_CHOISE_PUSH_OFST_0 0xE08AA4
+
+#define mmTPC0_QM_ARB_MST_CHOISE_PUSH_OFST_1 0xE08AA8
+
+#define mmTPC0_QM_ARB_MST_CHOISE_PUSH_OFST_2 0xE08AAC
+
+#define mmTPC0_QM_ARB_MST_CHOISE_PUSH_OFST_3 0xE08AB0
+
+#define mmTPC0_QM_ARB_MST_CHOISE_PUSH_OFST_4 0xE08AB4
+
+#define mmTPC0_QM_ARB_MST_CHOISE_PUSH_OFST_5 0xE08AB8
+
+#define mmTPC0_QM_ARB_MST_CHOISE_PUSH_OFST_6 0xE08ABC
+
+#define mmTPC0_QM_ARB_MST_CHOISE_PUSH_OFST_7 0xE08AC0
+
+#define mmTPC0_QM_ARB_MST_CHOISE_PUSH_OFST_8 0xE08AC4
+
+#define mmTPC0_QM_ARB_MST_CHOISE_PUSH_OFST_9 0xE08AC8
+
+#define mmTPC0_QM_ARB_MST_CHOISE_PUSH_OFST_10 0xE08ACC
+
+#define mmTPC0_QM_ARB_MST_CHOISE_PUSH_OFST_11 0xE08AD0
+
+#define mmTPC0_QM_ARB_MST_CHOISE_PUSH_OFST_12 0xE08AD4
+
+#define mmTPC0_QM_ARB_MST_CHOISE_PUSH_OFST_13 0xE08AD8
+
+#define mmTPC0_QM_ARB_MST_CHOISE_PUSH_OFST_14 0xE08ADC
+
+#define mmTPC0_QM_ARB_MST_CHOISE_PUSH_OFST_15 0xE08AE0
+
+#define mmTPC0_QM_ARB_MST_CHOISE_PUSH_OFST_16 0xE08AE4
+
+#define mmTPC0_QM_ARB_MST_CHOISE_PUSH_OFST_17 0xE08AE8
+
+#define mmTPC0_QM_ARB_MST_CHOISE_PUSH_OFST_18 0xE08AEC
+
+#define mmTPC0_QM_ARB_MST_CHOISE_PUSH_OFST_19 0xE08AF0
+
+#define mmTPC0_QM_ARB_MST_CHOISE_PUSH_OFST_20 0xE08AF4
+
+#define mmTPC0_QM_ARB_MST_CHOISE_PUSH_OFST_21 0xE08AF8
+
+#define mmTPC0_QM_ARB_MST_CHOISE_PUSH_OFST_22 0xE08AFC
+
+#define mmTPC0_QM_ARB_MST_CHOISE_PUSH_OFST_23 0xE08B00
+
+#define mmTPC0_QM_ARB_MST_CHOISE_PUSH_OFST_24 0xE08B04
+
+#define mmTPC0_QM_ARB_MST_CHOISE_PUSH_OFST_25 0xE08B08
+
+#define mmTPC0_QM_ARB_MST_CHOISE_PUSH_OFST_26 0xE08B0C
+
+#define mmTPC0_QM_ARB_MST_CHOISE_PUSH_OFST_27 0xE08B10
+
+#define mmTPC0_QM_ARB_MST_CHOISE_PUSH_OFST_28 0xE08B14
+
+#define mmTPC0_QM_ARB_MST_CHOISE_PUSH_OFST_29 0xE08B18
+
+#define mmTPC0_QM_ARB_MST_CHOISE_PUSH_OFST_30 0xE08B1C
+
+#define mmTPC0_QM_ARB_MST_CHOISE_PUSH_OFST_31 0xE08B20
+
+#define mmTPC0_QM_ARB_SLV_MASTER_INC_CRED_OFST 0xE08B28
+
+#define mmTPC0_QM_ARB_MST_SLAVE_EN 0xE08B2C
+
+#define mmTPC0_QM_ARB_MST_QUIET_PER 0xE08B34
+
+#define mmTPC0_QM_ARB_SLV_CHOISE_WDT 0xE08B38
+
+#define mmTPC0_QM_ARB_SLV_ID 0xE08B3C
+
+#define mmTPC0_QM_ARB_MSG_MAX_INFLIGHT 0xE08B44
+
+#define mmTPC0_QM_ARB_MSG_AWUSER_31_11 0xE08B48
+
+#define mmTPC0_QM_ARB_MSG_AWUSER_SEC_PROP 0xE08B4C
+
+#define mmTPC0_QM_ARB_MSG_AWUSER_NON_SEC_PROP 0xE08B50
+
+#define mmTPC0_QM_ARB_BASE_LO 0xE08B54
+
+#define mmTPC0_QM_ARB_BASE_HI 0xE08B58
+
+#define mmTPC0_QM_ARB_STATE_STS 0xE08B80
+
+#define mmTPC0_QM_ARB_CHOISE_FULLNESS_STS 0xE08B84
+
+#define mmTPC0_QM_ARB_MSG_STS 0xE08B88
+
+#define mmTPC0_QM_ARB_SLV_CHOISE_Q_HEAD 0xE08B8C
+
+#define mmTPC0_QM_ARB_ERR_CAUSE 0xE08B9C
+
+#define mmTPC0_QM_ARB_ERR_MSG_EN 0xE08BA0
+
+#define mmTPC0_QM_ARB_ERR_STS_DRP 0xE08BA8
+
+#define mmTPC0_QM_ARB_MST_CRED_STS_0 0xE08BB0
+
+#define mmTPC0_QM_ARB_MST_CRED_STS_1 0xE08BB4
+
+#define mmTPC0_QM_ARB_MST_CRED_STS_2 0xE08BB8
+
+#define mmTPC0_QM_ARB_MST_CRED_STS_3 0xE08BBC
+
+#define mmTPC0_QM_ARB_MST_CRED_STS_4 0xE08BC0
+
+#define mmTPC0_QM_ARB_MST_CRED_STS_5 0xE08BC4
+
+#define mmTPC0_QM_ARB_MST_CRED_STS_6 0xE08BC8
+
+#define mmTPC0_QM_ARB_MST_CRED_STS_7 0xE08BCC
+
+#define mmTPC0_QM_ARB_MST_CRED_STS_8 0xE08BD0
+
+#define mmTPC0_QM_ARB_MST_CRED_STS_9 0xE08BD4
+
+#define mmTPC0_QM_ARB_MST_CRED_STS_10 0xE08BD8
+
+#define mmTPC0_QM_ARB_MST_CRED_STS_11 0xE08BDC
+
+#define mmTPC0_QM_ARB_MST_CRED_STS_12 0xE08BE0
+
+#define mmTPC0_QM_ARB_MST_CRED_STS_13 0xE08BE4
+
+#define mmTPC0_QM_ARB_MST_CRED_STS_14 0xE08BE8
+
+#define mmTPC0_QM_ARB_MST_CRED_STS_15 0xE08BEC
+
+#define mmTPC0_QM_ARB_MST_CRED_STS_16 0xE08BF0
+
+#define mmTPC0_QM_ARB_MST_CRED_STS_17 0xE08BF4
+
+#define mmTPC0_QM_ARB_MST_CRED_STS_18 0xE08BF8
+
+#define mmTPC0_QM_ARB_MST_CRED_STS_19 0xE08BFC
+
+#define mmTPC0_QM_ARB_MST_CRED_STS_20 0xE08C00
+
+#define mmTPC0_QM_ARB_MST_CRED_STS_21 0xE08C04
+
+#define mmTPC0_QM_ARB_MST_CRED_STS_22 0xE08C08
+
+#define mmTPC0_QM_ARB_MST_CRED_STS_23 0xE08C0C
+
+#define mmTPC0_QM_ARB_MST_CRED_STS_24 0xE08C10
+
+#define mmTPC0_QM_ARB_MST_CRED_STS_25 0xE08C14
+
+#define mmTPC0_QM_ARB_MST_CRED_STS_26 0xE08C18
+
+#define mmTPC0_QM_ARB_MST_CRED_STS_27 0xE08C1C
+
+#define mmTPC0_QM_ARB_MST_CRED_STS_28 0xE08C20
+
+#define mmTPC0_QM_ARB_MST_CRED_STS_29 0xE08C24
+
+#define mmTPC0_QM_ARB_MST_CRED_STS_30 0xE08C28
+
+#define mmTPC0_QM_ARB_MST_CRED_STS_31 0xE08C2C
+
+#define mmTPC0_QM_CGM_CFG 0xE08C70
+
+#define mmTPC0_QM_CGM_STS 0xE08C74
+
+#define mmTPC0_QM_CGM_CFG1 0xE08C78
+
+#define mmTPC0_QM_LOCAL_RANGE_BASE 0xE08C80
+
+#define mmTPC0_QM_LOCAL_RANGE_SIZE 0xE08C84
+
+#define mmTPC0_QM_CSMR_STRICT_PRIO_CFG 0xE08C90
+
+#define mmTPC0_QM_HBW_RD_RATE_LIM_CFG_1 0xE08C94
+
+#define mmTPC0_QM_LBW_WR_RATE_LIM_CFG_0 0xE08C98
+
+#define mmTPC0_QM_LBW_WR_RATE_LIM_CFG_1 0xE08C9C
+
+#define mmTPC0_QM_HBW_RD_RATE_LIM_CFG_0 0xE08CA0
+
+#define mmTPC0_QM_GLBL_AXCACHE 0xE08CA4
+
+#define mmTPC0_QM_IND_GW_APB_CFG 0xE08CB0
+
+#define mmTPC0_QM_IND_GW_APB_WDATA 0xE08CB4
+
+#define mmTPC0_QM_IND_GW_APB_RDATA 0xE08CB8
+
+#define mmTPC0_QM_IND_GW_APB_STATUS 0xE08CBC
+
+#define mmTPC0_QM_GLBL_ERR_ADDR_LO 0xE08CD0
+
+#define mmTPC0_QM_GLBL_ERR_ADDR_HI 0xE08CD4
+
+#define mmTPC0_QM_GLBL_ERR_WDATA 0xE08CD8
+
+#define mmTPC0_QM_GLBL_MEM_INIT_BUSY 0xE08D00
+
+#endif /* ASIC_REG_TPC0_QM_REGS_H_ */
diff --git a/drivers/accel/habanalabs/include/gaudi/asic_reg/tpc1_cfg_regs.h b/drivers/accel/habanalabs/include/gaudi/asic_reg/tpc1_cfg_regs.h
new file mode 100644
index 0000000000..6736c476d9
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi/asic_reg/tpc1_cfg_regs.h
@@ -0,0 +1,1226 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2016-2018 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ ** DO NOT EDIT BELOW **
+ ************************************/
+
+#ifndef ASIC_REG_TPC1_CFG_REGS_H_
+#define ASIC_REG_TPC1_CFG_REGS_H_
+
+/*
+ *****************************************
+ * TPC1_CFG (Prototype: TPC)
+ *****************************************
+ */
+
+#define mmTPC1_CFG_KERNEL_TENSOR_0_BASE_ADDR_LOW 0xE46400
+
+#define mmTPC1_CFG_KERNEL_TENSOR_0_BASE_ADDR_HIGH 0xE46404
+
+#define mmTPC1_CFG_KERNEL_TENSOR_0_PADDING_VALUE 0xE46408
+
+#define mmTPC1_CFG_KERNEL_TENSOR_0_TENSOR_CONFIG 0xE4640C
+
+#define mmTPC1_CFG_KERNEL_TENSOR_0_DIM_0_SIZE 0xE46410
+
+#define mmTPC1_CFG_KERNEL_TENSOR_0_DIM_0_STRIDE 0xE46414
+
+#define mmTPC1_CFG_KERNEL_TENSOR_0_DIM_1_SIZE 0xE46418
+
+#define mmTPC1_CFG_KERNEL_TENSOR_0_DIM_1_STRIDE 0xE4641C
+
+#define mmTPC1_CFG_KERNEL_TENSOR_0_DIM_2_SIZE 0xE46420
+
+#define mmTPC1_CFG_KERNEL_TENSOR_0_DIM_2_STRIDE 0xE46424
+
+#define mmTPC1_CFG_KERNEL_TENSOR_0_DIM_3_SIZE 0xE46428
+
+#define mmTPC1_CFG_KERNEL_TENSOR_0_DIM_3_STRIDE 0xE4642C
+
+#define mmTPC1_CFG_KERNEL_TENSOR_0_DIM_4_SIZE 0xE46430
+
+#define mmTPC1_CFG_KERNEL_TENSOR_0_DIM_4_STRIDE 0xE46434
+
+#define mmTPC1_CFG_KERNEL_TENSOR_1_BASE_ADDR_LOW 0xE46438
+
+#define mmTPC1_CFG_KERNEL_TENSOR_1_BASE_ADDR_HIGH 0xE4643C
+
+#define mmTPC1_CFG_KERNEL_TENSOR_1_PADDING_VALUE 0xE46440
+
+#define mmTPC1_CFG_KERNEL_TENSOR_1_TENSOR_CONFIG 0xE46444
+
+#define mmTPC1_CFG_KERNEL_TENSOR_1_DIM_0_SIZE 0xE46448
+
+#define mmTPC1_CFG_KERNEL_TENSOR_1_DIM_0_STRIDE 0xE4644C
+
+#define mmTPC1_CFG_KERNEL_TENSOR_1_DIM_1_SIZE 0xE46450
+
+#define mmTPC1_CFG_KERNEL_TENSOR_1_DIM_1_STRIDE 0xE46454
+
+#define mmTPC1_CFG_KERNEL_TENSOR_1_DIM_2_SIZE 0xE46458
+
+#define mmTPC1_CFG_KERNEL_TENSOR_1_DIM_2_STRIDE 0xE4645C
+
+#define mmTPC1_CFG_KERNEL_TENSOR_1_DIM_3_SIZE 0xE46460
+
+#define mmTPC1_CFG_KERNEL_TENSOR_1_DIM_3_STRIDE 0xE46464
+
+#define mmTPC1_CFG_KERNEL_TENSOR_1_DIM_4_SIZE 0xE46468
+
+#define mmTPC1_CFG_KERNEL_TENSOR_1_DIM_4_STRIDE 0xE4646C
+
+#define mmTPC1_CFG_KERNEL_TENSOR_2_BASE_ADDR_LOW 0xE46470
+
+#define mmTPC1_CFG_KERNEL_TENSOR_2_BASE_ADDR_HIGH 0xE46474
+
+#define mmTPC1_CFG_KERNEL_TENSOR_2_PADDING_VALUE 0xE46478
+
+#define mmTPC1_CFG_KERNEL_TENSOR_2_TENSOR_CONFIG 0xE4647C
+
+#define mmTPC1_CFG_KERNEL_TENSOR_2_DIM_0_SIZE 0xE46480
+
+#define mmTPC1_CFG_KERNEL_TENSOR_2_DIM_0_STRIDE 0xE46484
+
+#define mmTPC1_CFG_KERNEL_TENSOR_2_DIM_1_SIZE 0xE46488
+
+#define mmTPC1_CFG_KERNEL_TENSOR_2_DIM_1_STRIDE 0xE4648C
+
+#define mmTPC1_CFG_KERNEL_TENSOR_2_DIM_2_SIZE 0xE46490
+
+#define mmTPC1_CFG_KERNEL_TENSOR_2_DIM_2_STRIDE 0xE46494
+
+#define mmTPC1_CFG_KERNEL_TENSOR_2_DIM_3_SIZE 0xE46498
+
+#define mmTPC1_CFG_KERNEL_TENSOR_2_DIM_3_STRIDE 0xE4649C
+
+#define mmTPC1_CFG_KERNEL_TENSOR_2_DIM_4_SIZE 0xE464A0
+
+#define mmTPC1_CFG_KERNEL_TENSOR_2_DIM_4_STRIDE 0xE464A4
+
+#define mmTPC1_CFG_KERNEL_TENSOR_3_BASE_ADDR_LOW 0xE464A8
+
+#define mmTPC1_CFG_KERNEL_TENSOR_3_BASE_ADDR_HIGH 0xE464AC
+
+#define mmTPC1_CFG_KERNEL_TENSOR_3_PADDING_VALUE 0xE464B0
+
+#define mmTPC1_CFG_KERNEL_TENSOR_3_TENSOR_CONFIG 0xE464B4
+
+#define mmTPC1_CFG_KERNEL_TENSOR_3_DIM_0_SIZE 0xE464B8
+
+#define mmTPC1_CFG_KERNEL_TENSOR_3_DIM_0_STRIDE 0xE464BC
+
+#define mmTPC1_CFG_KERNEL_TENSOR_3_DIM_1_SIZE 0xE464C0
+
+#define mmTPC1_CFG_KERNEL_TENSOR_3_DIM_1_STRIDE 0xE464C4
+
+#define mmTPC1_CFG_KERNEL_TENSOR_3_DIM_2_SIZE 0xE464C8
+
+#define mmTPC1_CFG_KERNEL_TENSOR_3_DIM_2_STRIDE 0xE464CC
+
+#define mmTPC1_CFG_KERNEL_TENSOR_3_DIM_3_SIZE 0xE464D0
+
+#define mmTPC1_CFG_KERNEL_TENSOR_3_DIM_3_STRIDE 0xE464D4
+
+#define mmTPC1_CFG_KERNEL_TENSOR_3_DIM_4_SIZE 0xE464D8
+
+#define mmTPC1_CFG_KERNEL_TENSOR_3_DIM_4_STRIDE 0xE464DC
+
+#define mmTPC1_CFG_KERNEL_TENSOR_4_BASE_ADDR_LOW 0xE464E0
+
+#define mmTPC1_CFG_KERNEL_TENSOR_4_BASE_ADDR_HIGH 0xE464E4
+
+#define mmTPC1_CFG_KERNEL_TENSOR_4_PADDING_VALUE 0xE464E8
+
+#define mmTPC1_CFG_KERNEL_TENSOR_4_TENSOR_CONFIG 0xE464EC
+
+#define mmTPC1_CFG_KERNEL_TENSOR_4_DIM_0_SIZE 0xE464F0
+
+#define mmTPC1_CFG_KERNEL_TENSOR_4_DIM_0_STRIDE 0xE464F4
+
+#define mmTPC1_CFG_KERNEL_TENSOR_4_DIM_1_SIZE 0xE464F8
+
+#define mmTPC1_CFG_KERNEL_TENSOR_4_DIM_1_STRIDE 0xE464FC
+
+#define mmTPC1_CFG_KERNEL_TENSOR_4_DIM_2_SIZE 0xE46500
+
+#define mmTPC1_CFG_KERNEL_TENSOR_4_DIM_2_STRIDE 0xE46504
+
+#define mmTPC1_CFG_KERNEL_TENSOR_4_DIM_3_SIZE 0xE46508
+
+#define mmTPC1_CFG_KERNEL_TENSOR_4_DIM_3_STRIDE 0xE4650C
+
+#define mmTPC1_CFG_KERNEL_TENSOR_4_DIM_4_SIZE 0xE46510
+
+#define mmTPC1_CFG_KERNEL_TENSOR_4_DIM_4_STRIDE 0xE46514
+
+#define mmTPC1_CFG_KERNEL_TENSOR_5_BASE_ADDR_LOW 0xE46518
+
+#define mmTPC1_CFG_KERNEL_TENSOR_5_BASE_ADDR_HIGH 0xE4651C
+
+#define mmTPC1_CFG_KERNEL_TENSOR_5_PADDING_VALUE 0xE46520
+
+#define mmTPC1_CFG_KERNEL_TENSOR_5_TENSOR_CONFIG 0xE46524
+
+#define mmTPC1_CFG_KERNEL_TENSOR_5_DIM_0_SIZE 0xE46528
+
+#define mmTPC1_CFG_KERNEL_TENSOR_5_DIM_0_STRIDE 0xE4652C
+
+#define mmTPC1_CFG_KERNEL_TENSOR_5_DIM_1_SIZE 0xE46530
+
+#define mmTPC1_CFG_KERNEL_TENSOR_5_DIM_1_STRIDE 0xE46534
+
+#define mmTPC1_CFG_KERNEL_TENSOR_5_DIM_2_SIZE 0xE46538
+
+#define mmTPC1_CFG_KERNEL_TENSOR_5_DIM_2_STRIDE 0xE4653C
+
+#define mmTPC1_CFG_KERNEL_TENSOR_5_DIM_3_SIZE 0xE46540
+
+#define mmTPC1_CFG_KERNEL_TENSOR_5_DIM_3_STRIDE 0xE46544
+
+#define mmTPC1_CFG_KERNEL_TENSOR_5_DIM_4_SIZE 0xE46548
+
+#define mmTPC1_CFG_KERNEL_TENSOR_5_DIM_4_STRIDE 0xE4654C
+
+#define mmTPC1_CFG_KERNEL_TENSOR_6_BASE_ADDR_LOW 0xE46550
+
+#define mmTPC1_CFG_KERNEL_TENSOR_6_BASE_ADDR_HIGH 0xE46554
+
+#define mmTPC1_CFG_KERNEL_TENSOR_6_PADDING_VALUE 0xE46558
+
+#define mmTPC1_CFG_KERNEL_TENSOR_6_TENSOR_CONFIG 0xE4655C
+
+#define mmTPC1_CFG_KERNEL_TENSOR_6_DIM_0_SIZE 0xE46560
+
+#define mmTPC1_CFG_KERNEL_TENSOR_6_DIM_0_STRIDE 0xE46564
+
+#define mmTPC1_CFG_KERNEL_TENSOR_6_DIM_1_SIZE 0xE46568
+
+#define mmTPC1_CFG_KERNEL_TENSOR_6_DIM_1_STRIDE 0xE4656C
+
+#define mmTPC1_CFG_KERNEL_TENSOR_6_DIM_2_SIZE 0xE46570
+
+#define mmTPC1_CFG_KERNEL_TENSOR_6_DIM_2_STRIDE 0xE46574
+
+#define mmTPC1_CFG_KERNEL_TENSOR_6_DIM_3_SIZE 0xE46578
+
+#define mmTPC1_CFG_KERNEL_TENSOR_6_DIM_3_STRIDE 0xE4657C
+
+#define mmTPC1_CFG_KERNEL_TENSOR_6_DIM_4_SIZE 0xE46580
+
+#define mmTPC1_CFG_KERNEL_TENSOR_6_DIM_4_STRIDE 0xE46584
+
+#define mmTPC1_CFG_KERNEL_TENSOR_7_BASE_ADDR_LOW 0xE46588
+
+#define mmTPC1_CFG_KERNEL_TENSOR_7_BASE_ADDR_HIGH 0xE4658C
+
+#define mmTPC1_CFG_KERNEL_TENSOR_7_PADDING_VALUE 0xE46590
+
+#define mmTPC1_CFG_KERNEL_TENSOR_7_TENSOR_CONFIG 0xE46594
+
+#define mmTPC1_CFG_KERNEL_TENSOR_7_DIM_0_SIZE 0xE46598
+
+#define mmTPC1_CFG_KERNEL_TENSOR_7_DIM_0_STRIDE 0xE4659C
+
+#define mmTPC1_CFG_KERNEL_TENSOR_7_DIM_1_SIZE 0xE465A0
+
+#define mmTPC1_CFG_KERNEL_TENSOR_7_DIM_1_STRIDE 0xE465A4
+
+#define mmTPC1_CFG_KERNEL_TENSOR_7_DIM_2_SIZE 0xE465A8
+
+#define mmTPC1_CFG_KERNEL_TENSOR_7_DIM_2_STRIDE 0xE465AC
+
+#define mmTPC1_CFG_KERNEL_TENSOR_7_DIM_3_SIZE 0xE465B0
+
+#define mmTPC1_CFG_KERNEL_TENSOR_7_DIM_3_STRIDE 0xE465B4
+
+#define mmTPC1_CFG_KERNEL_TENSOR_7_DIM_4_SIZE 0xE465B8
+
+#define mmTPC1_CFG_KERNEL_TENSOR_7_DIM_4_STRIDE 0xE465BC
+
+#define mmTPC1_CFG_KERNEL_TENSOR_8_BASE_ADDR_LOW 0xE465C0
+
+#define mmTPC1_CFG_KERNEL_TENSOR_8_BASE_ADDR_HIGH 0xE465C4
+
+#define mmTPC1_CFG_KERNEL_TENSOR_8_PADDING_VALUE 0xE465C8
+
+#define mmTPC1_CFG_KERNEL_TENSOR_8_TENSOR_CONFIG 0xE465CC
+
+#define mmTPC1_CFG_KERNEL_TENSOR_8_DIM_0_SIZE 0xE465D0
+
+#define mmTPC1_CFG_KERNEL_TENSOR_8_DIM_0_STRIDE 0xE465D4
+
+#define mmTPC1_CFG_KERNEL_TENSOR_8_DIM_1_SIZE 0xE465D8
+
+#define mmTPC1_CFG_KERNEL_TENSOR_8_DIM_1_STRIDE 0xE465DC
+
+#define mmTPC1_CFG_KERNEL_TENSOR_8_DIM_2_SIZE 0xE465E0
+
+#define mmTPC1_CFG_KERNEL_TENSOR_8_DIM_2_STRIDE 0xE465E4
+
+#define mmTPC1_CFG_KERNEL_TENSOR_8_DIM_3_SIZE 0xE465E8
+
+#define mmTPC1_CFG_KERNEL_TENSOR_8_DIM_3_STRIDE 0xE465EC
+
+#define mmTPC1_CFG_KERNEL_TENSOR_8_DIM_4_SIZE 0xE465F0
+
+#define mmTPC1_CFG_KERNEL_TENSOR_8_DIM_4_STRIDE 0xE465F4
+
+#define mmTPC1_CFG_KERNEL_TENSOR_9_BASE_ADDR_LOW 0xE465F8
+
+#define mmTPC1_CFG_KERNEL_TENSOR_9_BASE_ADDR_HIGH 0xE465FC
+
+#define mmTPC1_CFG_KERNEL_TENSOR_9_PADDING_VALUE 0xE46600
+
+#define mmTPC1_CFG_KERNEL_TENSOR_9_TENSOR_CONFIG 0xE46604
+
+#define mmTPC1_CFG_KERNEL_TENSOR_9_DIM_0_SIZE 0xE46608
+
+#define mmTPC1_CFG_KERNEL_TENSOR_9_DIM_0_STRIDE 0xE4660C
+
+#define mmTPC1_CFG_KERNEL_TENSOR_9_DIM_1_SIZE 0xE46610
+
+#define mmTPC1_CFG_KERNEL_TENSOR_9_DIM_1_STRIDE 0xE46614
+
+#define mmTPC1_CFG_KERNEL_TENSOR_9_DIM_2_SIZE 0xE46618
+
+#define mmTPC1_CFG_KERNEL_TENSOR_9_DIM_2_STRIDE 0xE4661C
+
+#define mmTPC1_CFG_KERNEL_TENSOR_9_DIM_3_SIZE 0xE46620
+
+#define mmTPC1_CFG_KERNEL_TENSOR_9_DIM_3_STRIDE 0xE46624
+
+#define mmTPC1_CFG_KERNEL_TENSOR_9_DIM_4_SIZE 0xE46628
+
+#define mmTPC1_CFG_KERNEL_TENSOR_9_DIM_4_STRIDE 0xE4662C
+
+#define mmTPC1_CFG_KERNEL_TENSOR_10_BASE_ADDR_LOW 0xE46630
+
+#define mmTPC1_CFG_KERNEL_TENSOR_10_BASE_ADDR_HIGH 0xE46634
+
+#define mmTPC1_CFG_KERNEL_TENSOR_10_PADDING_VALUE 0xE46638
+
+#define mmTPC1_CFG_KERNEL_TENSOR_10_TENSOR_CONFIG 0xE4663C
+
+#define mmTPC1_CFG_KERNEL_TENSOR_10_DIM_0_SIZE 0xE46640
+
+#define mmTPC1_CFG_KERNEL_TENSOR_10_DIM_0_STRIDE 0xE46644
+
+#define mmTPC1_CFG_KERNEL_TENSOR_10_DIM_1_SIZE 0xE46648
+
+#define mmTPC1_CFG_KERNEL_TENSOR_10_DIM_1_STRIDE 0xE4664C
+
+#define mmTPC1_CFG_KERNEL_TENSOR_10_DIM_2_SIZE 0xE46650
+
+#define mmTPC1_CFG_KERNEL_TENSOR_10_DIM_2_STRIDE 0xE46654
+
+#define mmTPC1_CFG_KERNEL_TENSOR_10_DIM_3_SIZE 0xE46658
+
+#define mmTPC1_CFG_KERNEL_TENSOR_10_DIM_3_STRIDE 0xE4665C
+
+#define mmTPC1_CFG_KERNEL_TENSOR_10_DIM_4_SIZE 0xE46660
+
+#define mmTPC1_CFG_KERNEL_TENSOR_10_DIM_4_STRIDE 0xE46664
+
+#define mmTPC1_CFG_KERNEL_TENSOR_11_BASE_ADDR_LOW 0xE46668
+
+#define mmTPC1_CFG_KERNEL_TENSOR_11_BASE_ADDR_HIGH 0xE4666C
+
+#define mmTPC1_CFG_KERNEL_TENSOR_11_PADDING_VALUE 0xE46670
+
+#define mmTPC1_CFG_KERNEL_TENSOR_11_TENSOR_CONFIG 0xE46674
+
+#define mmTPC1_CFG_KERNEL_TENSOR_11_DIM_0_SIZE 0xE46678
+
+#define mmTPC1_CFG_KERNEL_TENSOR_11_DIM_0_STRIDE 0xE4667C
+
+#define mmTPC1_CFG_KERNEL_TENSOR_11_DIM_1_SIZE 0xE46680
+
+#define mmTPC1_CFG_KERNEL_TENSOR_11_DIM_1_STRIDE 0xE46684
+
+#define mmTPC1_CFG_KERNEL_TENSOR_11_DIM_2_SIZE 0xE46688
+
+#define mmTPC1_CFG_KERNEL_TENSOR_11_DIM_2_STRIDE 0xE4668C
+
+#define mmTPC1_CFG_KERNEL_TENSOR_11_DIM_3_SIZE 0xE46690
+
+#define mmTPC1_CFG_KERNEL_TENSOR_11_DIM_3_STRIDE 0xE46694
+
+#define mmTPC1_CFG_KERNEL_TENSOR_11_DIM_4_SIZE 0xE46698
+
+#define mmTPC1_CFG_KERNEL_TENSOR_11_DIM_4_STRIDE 0xE4669C
+
+#define mmTPC1_CFG_KERNEL_TENSOR_12_BASE_ADDR_LOW 0xE466A0
+
+#define mmTPC1_CFG_KERNEL_TENSOR_12_BASE_ADDR_HIGH 0xE466A4
+
+#define mmTPC1_CFG_KERNEL_TENSOR_12_PADDING_VALUE 0xE466A8
+
+#define mmTPC1_CFG_KERNEL_TENSOR_12_TENSOR_CONFIG 0xE466AC
+
+#define mmTPC1_CFG_KERNEL_TENSOR_12_DIM_0_SIZE 0xE466B0
+
+#define mmTPC1_CFG_KERNEL_TENSOR_12_DIM_0_STRIDE 0xE466B4
+
+#define mmTPC1_CFG_KERNEL_TENSOR_12_DIM_1_SIZE 0xE466B8
+
+#define mmTPC1_CFG_KERNEL_TENSOR_12_DIM_1_STRIDE 0xE466BC
+
+#define mmTPC1_CFG_KERNEL_TENSOR_12_DIM_2_SIZE 0xE466C0
+
+#define mmTPC1_CFG_KERNEL_TENSOR_12_DIM_2_STRIDE 0xE466C4
+
+#define mmTPC1_CFG_KERNEL_TENSOR_12_DIM_3_SIZE 0xE466C8
+
+#define mmTPC1_CFG_KERNEL_TENSOR_12_DIM_3_STRIDE 0xE466CC
+
+#define mmTPC1_CFG_KERNEL_TENSOR_12_DIM_4_SIZE 0xE466D0
+
+#define mmTPC1_CFG_KERNEL_TENSOR_12_DIM_4_STRIDE 0xE466D4
+
+#define mmTPC1_CFG_KERNEL_TENSOR_13_BASE_ADDR_LOW 0xE466D8
+
+#define mmTPC1_CFG_KERNEL_TENSOR_13_BASE_ADDR_HIGH 0xE466DC
+
+#define mmTPC1_CFG_KERNEL_TENSOR_13_PADDING_VALUE 0xE466E0
+
+#define mmTPC1_CFG_KERNEL_TENSOR_13_TENSOR_CONFIG 0xE466E4
+
+#define mmTPC1_CFG_KERNEL_TENSOR_13_DIM_0_SIZE 0xE466E8
+
+#define mmTPC1_CFG_KERNEL_TENSOR_13_DIM_0_STRIDE 0xE466EC
+
+#define mmTPC1_CFG_KERNEL_TENSOR_13_DIM_1_SIZE 0xE466F0
+
+#define mmTPC1_CFG_KERNEL_TENSOR_13_DIM_1_STRIDE 0xE466F4
+
+#define mmTPC1_CFG_KERNEL_TENSOR_13_DIM_2_SIZE 0xE466F8
+
+#define mmTPC1_CFG_KERNEL_TENSOR_13_DIM_2_STRIDE 0xE466FC
+
+#define mmTPC1_CFG_KERNEL_TENSOR_13_DIM_3_SIZE 0xE46700
+
+#define mmTPC1_CFG_KERNEL_TENSOR_13_DIM_3_STRIDE 0xE46704
+
+#define mmTPC1_CFG_KERNEL_TENSOR_13_DIM_4_SIZE 0xE46708
+
+#define mmTPC1_CFG_KERNEL_TENSOR_13_DIM_4_STRIDE 0xE4670C
+
+#define mmTPC1_CFG_KERNEL_TENSOR_14_BASE_ADDR_LOW 0xE46710
+
+#define mmTPC1_CFG_KERNEL_TENSOR_14_BASE_ADDR_HIGH 0xE46714
+
+#define mmTPC1_CFG_KERNEL_TENSOR_14_PADDING_VALUE 0xE46718
+
+#define mmTPC1_CFG_KERNEL_TENSOR_14_TENSOR_CONFIG 0xE4671C
+
+#define mmTPC1_CFG_KERNEL_TENSOR_14_DIM_0_SIZE 0xE46720
+
+#define mmTPC1_CFG_KERNEL_TENSOR_14_DIM_0_STRIDE 0xE46724
+
+#define mmTPC1_CFG_KERNEL_TENSOR_14_DIM_1_SIZE 0xE46728
+
+#define mmTPC1_CFG_KERNEL_TENSOR_14_DIM_1_STRIDE 0xE4672C
+
+#define mmTPC1_CFG_KERNEL_TENSOR_14_DIM_2_SIZE 0xE46730
+
+#define mmTPC1_CFG_KERNEL_TENSOR_14_DIM_2_STRIDE 0xE46734
+
+#define mmTPC1_CFG_KERNEL_TENSOR_14_DIM_3_SIZE 0xE46738
+
+#define mmTPC1_CFG_KERNEL_TENSOR_14_DIM_3_STRIDE 0xE4673C
+
+#define mmTPC1_CFG_KERNEL_TENSOR_14_DIM_4_SIZE 0xE46740
+
+#define mmTPC1_CFG_KERNEL_TENSOR_14_DIM_4_STRIDE 0xE46744
+
+#define mmTPC1_CFG_KERNEL_TENSOR_15_BASE_ADDR_LOW 0xE46748
+
+#define mmTPC1_CFG_KERNEL_TENSOR_15_BASE_ADDR_HIGH 0xE4674C
+
+#define mmTPC1_CFG_KERNEL_TENSOR_15_PADDING_VALUE 0xE46750
+
+#define mmTPC1_CFG_KERNEL_TENSOR_15_TENSOR_CONFIG 0xE46754
+
+#define mmTPC1_CFG_KERNEL_TENSOR_15_DIM_0_SIZE 0xE46758
+
+#define mmTPC1_CFG_KERNEL_TENSOR_15_DIM_0_STRIDE 0xE4675C
+
+#define mmTPC1_CFG_KERNEL_TENSOR_15_DIM_1_SIZE 0xE46760
+
+#define mmTPC1_CFG_KERNEL_TENSOR_15_DIM_1_STRIDE 0xE46764
+
+#define mmTPC1_CFG_KERNEL_TENSOR_15_DIM_2_SIZE 0xE46768
+
+#define mmTPC1_CFG_KERNEL_TENSOR_15_DIM_2_STRIDE 0xE4676C
+
+#define mmTPC1_CFG_KERNEL_TENSOR_15_DIM_3_SIZE 0xE46770
+
+#define mmTPC1_CFG_KERNEL_TENSOR_15_DIM_3_STRIDE 0xE46774
+
+#define mmTPC1_CFG_KERNEL_TENSOR_15_DIM_4_SIZE 0xE46778
+
+#define mmTPC1_CFG_KERNEL_TENSOR_15_DIM_4_STRIDE 0xE4677C
+
+#define mmTPC1_CFG_KERNEL_SYNC_OBJECT_MESSAGE 0xE46780
+
+#define mmTPC1_CFG_KERNEL_SYNC_OBJECT_ADDR 0xE46784
+
+#define mmTPC1_CFG_KERNEL_KERNEL_BASE_ADDRESS_LOW 0xE46788
+
+#define mmTPC1_CFG_KERNEL_KERNEL_BASE_ADDRESS_HIGH 0xE4678C
+
+#define mmTPC1_CFG_KERNEL_TID_BASE_DIM_0 0xE46790
+
+#define mmTPC1_CFG_KERNEL_TID_SIZE_DIM_0 0xE46794
+
+#define mmTPC1_CFG_KERNEL_TID_BASE_DIM_1 0xE46798
+
+#define mmTPC1_CFG_KERNEL_TID_SIZE_DIM_1 0xE4679C
+
+#define mmTPC1_CFG_KERNEL_TID_BASE_DIM_2 0xE467A0
+
+#define mmTPC1_CFG_KERNEL_TID_SIZE_DIM_2 0xE467A4
+
+#define mmTPC1_CFG_KERNEL_TID_BASE_DIM_3 0xE467A8
+
+#define mmTPC1_CFG_KERNEL_TID_SIZE_DIM_3 0xE467AC
+
+#define mmTPC1_CFG_KERNEL_TID_BASE_DIM_4 0xE467B0
+
+#define mmTPC1_CFG_KERNEL_TID_SIZE_DIM_4 0xE467B4
+
+#define mmTPC1_CFG_KERNEL_KERNEL_CONFIG 0xE467B8
+
+#define mmTPC1_CFG_KERNEL_KERNEL_ID 0xE467BC
+
+#define mmTPC1_CFG_KERNEL_SRF_0 0xE467C0
+
+#define mmTPC1_CFG_KERNEL_SRF_1 0xE467C4
+
+#define mmTPC1_CFG_KERNEL_SRF_2 0xE467C8
+
+#define mmTPC1_CFG_KERNEL_SRF_3 0xE467CC
+
+#define mmTPC1_CFG_KERNEL_SRF_4 0xE467D0
+
+#define mmTPC1_CFG_KERNEL_SRF_5 0xE467D4
+
+#define mmTPC1_CFG_KERNEL_SRF_6 0xE467D8
+
+#define mmTPC1_CFG_KERNEL_SRF_7 0xE467DC
+
+#define mmTPC1_CFG_KERNEL_SRF_8 0xE467E0
+
+#define mmTPC1_CFG_KERNEL_SRF_9 0xE467E4
+
+#define mmTPC1_CFG_KERNEL_SRF_10 0xE467E8
+
+#define mmTPC1_CFG_KERNEL_SRF_11 0xE467EC
+
+#define mmTPC1_CFG_KERNEL_SRF_12 0xE467F0
+
+#define mmTPC1_CFG_KERNEL_SRF_13 0xE467F4
+
+#define mmTPC1_CFG_KERNEL_SRF_14 0xE467F8
+
+#define mmTPC1_CFG_KERNEL_SRF_15 0xE467FC
+
+#define mmTPC1_CFG_KERNEL_SRF_16 0xE46800
+
+#define mmTPC1_CFG_KERNEL_SRF_17 0xE46804
+
+#define mmTPC1_CFG_KERNEL_SRF_18 0xE46808
+
+#define mmTPC1_CFG_KERNEL_SRF_19 0xE4680C
+
+#define mmTPC1_CFG_KERNEL_SRF_20 0xE46810
+
+#define mmTPC1_CFG_KERNEL_SRF_21 0xE46814
+
+#define mmTPC1_CFG_KERNEL_SRF_22 0xE46818
+
+#define mmTPC1_CFG_KERNEL_SRF_23 0xE4681C
+
+#define mmTPC1_CFG_KERNEL_SRF_24 0xE46820
+
+#define mmTPC1_CFG_KERNEL_SRF_25 0xE46824
+
+#define mmTPC1_CFG_KERNEL_SRF_26 0xE46828
+
+#define mmTPC1_CFG_KERNEL_SRF_27 0xE4682C
+
+#define mmTPC1_CFG_KERNEL_SRF_28 0xE46830
+
+#define mmTPC1_CFG_KERNEL_SRF_29 0xE46834
+
+#define mmTPC1_CFG_KERNEL_SRF_30 0xE46838
+
+#define mmTPC1_CFG_KERNEL_SRF_31 0xE4683C
+
+#define mmTPC1_CFG_ROUND_CSR 0xE468FC
+
+#define mmTPC1_CFG_PROT 0xE46900
+
+#define mmTPC1_CFG_SEMAPHORE 0xE46908
+
+#define mmTPC1_CFG_VFLAGS 0xE4690C
+
+#define mmTPC1_CFG_SFLAGS 0xE46910
+
+#define mmTPC1_CFG_LFSR_POLYNOM 0xE46918
+
+#define mmTPC1_CFG_STATUS 0xE4691C
+
+#define mmTPC1_CFG_CFG_BASE_ADDRESS_HIGH 0xE46920
+
+#define mmTPC1_CFG_CFG_SUBTRACT_VALUE 0xE46924
+
+#define mmTPC1_CFG_SM_BASE_ADDRESS_HIGH 0xE4692C
+
+#define mmTPC1_CFG_TPC_CMD 0xE46930
+
+#define mmTPC1_CFG_TPC_EXECUTE 0xE46938
+
+#define mmTPC1_CFG_TPC_STALL 0xE4693C
+
+#define mmTPC1_CFG_ICACHE_BASE_ADDERESS_LOW 0xE46940
+
+#define mmTPC1_CFG_ICACHE_BASE_ADDERESS_HIGH 0xE46944
+
+#define mmTPC1_CFG_RD_RATE_LIMIT 0xE46948
+
+#define mmTPC1_CFG_WR_RATE_LIMIT 0xE46950
+
+#define mmTPC1_CFG_MSS_CONFIG 0xE46954
+
+#define mmTPC1_CFG_TPC_INTR_CAUSE 0xE46958
+
+#define mmTPC1_CFG_TPC_INTR_MASK 0xE4695C
+
+#define mmTPC1_CFG_WQ_CREDITS 0xE46960
+
+#define mmTPC1_CFG_ARUSER_LO 0xE46964
+
+#define mmTPC1_CFG_ARUSER_HI 0xE46968
+
+#define mmTPC1_CFG_AWUSER_LO 0xE4696C
+
+#define mmTPC1_CFG_AWUSER_HI 0xE46970
+
+#define mmTPC1_CFG_OPCODE_EXEC 0xE46974
+
+#define mmTPC1_CFG_LUT_FUNC32_BASE_ADDR_LO 0xE46978
+
+#define mmTPC1_CFG_LUT_FUNC32_BASE_ADDR_HI 0xE4697C
+
+#define mmTPC1_CFG_LUT_FUNC64_BASE_ADDR_LO 0xE46980
+
+#define mmTPC1_CFG_LUT_FUNC64_BASE_ADDR_HI 0xE46984
+
+#define mmTPC1_CFG_LUT_FUNC128_BASE_ADDR_LO 0xE46988
+
+#define mmTPC1_CFG_LUT_FUNC128_BASE_ADDR_HI 0xE4698C
+
+#define mmTPC1_CFG_LUT_FUNC256_BASE_ADDR_LO 0xE46990
+
+#define mmTPC1_CFG_LUT_FUNC256_BASE_ADDR_HI 0xE46994
+
+#define mmTPC1_CFG_TSB_CFG_MAX_SIZE 0xE46998
+
+#define mmTPC1_CFG_TSB_CFG 0xE4699C
+
+#define mmTPC1_CFG_DBGMEM_ADD 0xE469A0
+
+#define mmTPC1_CFG_DBGMEM_DATA_WR 0xE469A4
+
+#define mmTPC1_CFG_DBGMEM_DATA_RD 0xE469A8
+
+#define mmTPC1_CFG_DBGMEM_CTRL 0xE469AC
+
+#define mmTPC1_CFG_DBGMEM_RC 0xE469B0
+
+#define mmTPC1_CFG_TSB_INFLIGHT_CNTR 0xE469B4
+
+#define mmTPC1_CFG_WQ_INFLIGHT_CNTR 0xE469B8
+
+#define mmTPC1_CFG_WQ_LBW_TOTAL_CNTR 0xE469BC
+
+#define mmTPC1_CFG_WQ_HBW_TOTAL_CNTR 0xE469C0
+
+#define mmTPC1_CFG_IRQ_OCCOUPY_CNTR 0xE469C4
+
+#define mmTPC1_CFG_FUNC_MBIST_CNTRL 0xE469D0
+
+#define mmTPC1_CFG_FUNC_MBIST_PAT 0xE469D4
+
+#define mmTPC1_CFG_FUNC_MBIST_MEM_0 0xE469D8
+
+#define mmTPC1_CFG_FUNC_MBIST_MEM_1 0xE469DC
+
+#define mmTPC1_CFG_FUNC_MBIST_MEM_2 0xE469E0
+
+#define mmTPC1_CFG_FUNC_MBIST_MEM_3 0xE469E4
+
+#define mmTPC1_CFG_FUNC_MBIST_MEM_4 0xE469E8
+
+#define mmTPC1_CFG_FUNC_MBIST_MEM_5 0xE469EC
+
+#define mmTPC1_CFG_FUNC_MBIST_MEM_6 0xE469F0
+
+#define mmTPC1_CFG_FUNC_MBIST_MEM_7 0xE469F4
+
+#define mmTPC1_CFG_FUNC_MBIST_MEM_8 0xE469F8
+
+#define mmTPC1_CFG_FUNC_MBIST_MEM_9 0xE469FC
+
+#define mmTPC1_CFG_QM_TENSOR_0_BASE_ADDR_LOW 0xE46A00
+
+#define mmTPC1_CFG_QM_TENSOR_0_BASE_ADDR_HIGH 0xE46A04
+
+#define mmTPC1_CFG_QM_TENSOR_0_PADDING_VALUE 0xE46A08
+
+#define mmTPC1_CFG_QM_TENSOR_0_TENSOR_CONFIG 0xE46A0C
+
+#define mmTPC1_CFG_QM_TENSOR_0_DIM_0_SIZE 0xE46A10
+
+#define mmTPC1_CFG_QM_TENSOR_0_DIM_0_STRIDE 0xE46A14
+
+#define mmTPC1_CFG_QM_TENSOR_0_DIM_1_SIZE 0xE46A18
+
+#define mmTPC1_CFG_QM_TENSOR_0_DIM_1_STRIDE 0xE46A1C
+
+#define mmTPC1_CFG_QM_TENSOR_0_DIM_2_SIZE 0xE46A20
+
+#define mmTPC1_CFG_QM_TENSOR_0_DIM_2_STRIDE 0xE46A24
+
+#define mmTPC1_CFG_QM_TENSOR_0_DIM_3_SIZE 0xE46A28
+
+#define mmTPC1_CFG_QM_TENSOR_0_DIM_3_STRIDE 0xE46A2C
+
+#define mmTPC1_CFG_QM_TENSOR_0_DIM_4_SIZE 0xE46A30
+
+#define mmTPC1_CFG_QM_TENSOR_0_DIM_4_STRIDE 0xE46A34
+
+#define mmTPC1_CFG_QM_TENSOR_1_BASE_ADDR_LOW 0xE46A38
+
+#define mmTPC1_CFG_QM_TENSOR_1_BASE_ADDR_HIGH 0xE46A3C
+
+#define mmTPC1_CFG_QM_TENSOR_1_PADDING_VALUE 0xE46A40
+
+#define mmTPC1_CFG_QM_TENSOR_1_TENSOR_CONFIG 0xE46A44
+
+#define mmTPC1_CFG_QM_TENSOR_1_DIM_0_SIZE 0xE46A48
+
+#define mmTPC1_CFG_QM_TENSOR_1_DIM_0_STRIDE 0xE46A4C
+
+#define mmTPC1_CFG_QM_TENSOR_1_DIM_1_SIZE 0xE46A50
+
+#define mmTPC1_CFG_QM_TENSOR_1_DIM_1_STRIDE 0xE46A54
+
+#define mmTPC1_CFG_QM_TENSOR_1_DIM_2_SIZE 0xE46A58
+
+#define mmTPC1_CFG_QM_TENSOR_1_DIM_2_STRIDE 0xE46A5C
+
+#define mmTPC1_CFG_QM_TENSOR_1_DIM_3_SIZE 0xE46A60
+
+#define mmTPC1_CFG_QM_TENSOR_1_DIM_3_STRIDE 0xE46A64
+
+#define mmTPC1_CFG_QM_TENSOR_1_DIM_4_SIZE 0xE46A68
+
+#define mmTPC1_CFG_QM_TENSOR_1_DIM_4_STRIDE 0xE46A6C
+
+#define mmTPC1_CFG_QM_TENSOR_2_BASE_ADDR_LOW 0xE46A70
+
+#define mmTPC1_CFG_QM_TENSOR_2_BASE_ADDR_HIGH 0xE46A74
+
+#define mmTPC1_CFG_QM_TENSOR_2_PADDING_VALUE 0xE46A78
+
+#define mmTPC1_CFG_QM_TENSOR_2_TENSOR_CONFIG 0xE46A7C
+
+#define mmTPC1_CFG_QM_TENSOR_2_DIM_0_SIZE 0xE46A80
+
+#define mmTPC1_CFG_QM_TENSOR_2_DIM_0_STRIDE 0xE46A84
+
+#define mmTPC1_CFG_QM_TENSOR_2_DIM_1_SIZE 0xE46A88
+
+#define mmTPC1_CFG_QM_TENSOR_2_DIM_1_STRIDE 0xE46A8C
+
+#define mmTPC1_CFG_QM_TENSOR_2_DIM_2_SIZE 0xE46A90
+
+#define mmTPC1_CFG_QM_TENSOR_2_DIM_2_STRIDE 0xE46A94
+
+#define mmTPC1_CFG_QM_TENSOR_2_DIM_3_SIZE 0xE46A98
+
+#define mmTPC1_CFG_QM_TENSOR_2_DIM_3_STRIDE 0xE46A9C
+
+#define mmTPC1_CFG_QM_TENSOR_2_DIM_4_SIZE 0xE46AA0
+
+#define mmTPC1_CFG_QM_TENSOR_2_DIM_4_STRIDE 0xE46AA4
+
+#define mmTPC1_CFG_QM_TENSOR_3_BASE_ADDR_LOW 0xE46AA8
+
+#define mmTPC1_CFG_QM_TENSOR_3_BASE_ADDR_HIGH 0xE46AAC
+
+#define mmTPC1_CFG_QM_TENSOR_3_PADDING_VALUE 0xE46AB0
+
+#define mmTPC1_CFG_QM_TENSOR_3_TENSOR_CONFIG 0xE46AB4
+
+#define mmTPC1_CFG_QM_TENSOR_3_DIM_0_SIZE 0xE46AB8
+
+#define mmTPC1_CFG_QM_TENSOR_3_DIM_0_STRIDE 0xE46ABC
+
+#define mmTPC1_CFG_QM_TENSOR_3_DIM_1_SIZE 0xE46AC0
+
+#define mmTPC1_CFG_QM_TENSOR_3_DIM_1_STRIDE 0xE46AC4
+
+#define mmTPC1_CFG_QM_TENSOR_3_DIM_2_SIZE 0xE46AC8
+
+#define mmTPC1_CFG_QM_TENSOR_3_DIM_2_STRIDE 0xE46ACC
+
+#define mmTPC1_CFG_QM_TENSOR_3_DIM_3_SIZE 0xE46AD0
+
+#define mmTPC1_CFG_QM_TENSOR_3_DIM_3_STRIDE 0xE46AD4
+
+#define mmTPC1_CFG_QM_TENSOR_3_DIM_4_SIZE 0xE46AD8
+
+#define mmTPC1_CFG_QM_TENSOR_3_DIM_4_STRIDE 0xE46ADC
+
+#define mmTPC1_CFG_QM_TENSOR_4_BASE_ADDR_LOW 0xE46AE0
+
+#define mmTPC1_CFG_QM_TENSOR_4_BASE_ADDR_HIGH 0xE46AE4
+
+#define mmTPC1_CFG_QM_TENSOR_4_PADDING_VALUE 0xE46AE8
+
+#define mmTPC1_CFG_QM_TENSOR_4_TENSOR_CONFIG 0xE46AEC
+
+#define mmTPC1_CFG_QM_TENSOR_4_DIM_0_SIZE 0xE46AF0
+
+#define mmTPC1_CFG_QM_TENSOR_4_DIM_0_STRIDE 0xE46AF4
+
+#define mmTPC1_CFG_QM_TENSOR_4_DIM_1_SIZE 0xE46AF8
+
+#define mmTPC1_CFG_QM_TENSOR_4_DIM_1_STRIDE 0xE46AFC
+
+#define mmTPC1_CFG_QM_TENSOR_4_DIM_2_SIZE 0xE46B00
+
+#define mmTPC1_CFG_QM_TENSOR_4_DIM_2_STRIDE 0xE46B04
+
+#define mmTPC1_CFG_QM_TENSOR_4_DIM_3_SIZE 0xE46B08
+
+#define mmTPC1_CFG_QM_TENSOR_4_DIM_3_STRIDE 0xE46B0C
+
+#define mmTPC1_CFG_QM_TENSOR_4_DIM_4_SIZE 0xE46B10
+
+#define mmTPC1_CFG_QM_TENSOR_4_DIM_4_STRIDE 0xE46B14
+
+#define mmTPC1_CFG_QM_TENSOR_5_BASE_ADDR_LOW 0xE46B18
+
+#define mmTPC1_CFG_QM_TENSOR_5_BASE_ADDR_HIGH 0xE46B1C
+
+#define mmTPC1_CFG_QM_TENSOR_5_PADDING_VALUE 0xE46B20
+
+#define mmTPC1_CFG_QM_TENSOR_5_TENSOR_CONFIG 0xE46B24
+
+#define mmTPC1_CFG_QM_TENSOR_5_DIM_0_SIZE 0xE46B28
+
+#define mmTPC1_CFG_QM_TENSOR_5_DIM_0_STRIDE 0xE46B2C
+
+#define mmTPC1_CFG_QM_TENSOR_5_DIM_1_SIZE 0xE46B30
+
+#define mmTPC1_CFG_QM_TENSOR_5_DIM_1_STRIDE 0xE46B34
+
+#define mmTPC1_CFG_QM_TENSOR_5_DIM_2_SIZE 0xE46B38
+
+#define mmTPC1_CFG_QM_TENSOR_5_DIM_2_STRIDE 0xE46B3C
+
+#define mmTPC1_CFG_QM_TENSOR_5_DIM_3_SIZE 0xE46B40
+
+#define mmTPC1_CFG_QM_TENSOR_5_DIM_3_STRIDE 0xE46B44
+
+#define mmTPC1_CFG_QM_TENSOR_5_DIM_4_SIZE 0xE46B48
+
+#define mmTPC1_CFG_QM_TENSOR_5_DIM_4_STRIDE 0xE46B4C
+
+#define mmTPC1_CFG_QM_TENSOR_6_BASE_ADDR_LOW 0xE46B50
+
+#define mmTPC1_CFG_QM_TENSOR_6_BASE_ADDR_HIGH 0xE46B54
+
+#define mmTPC1_CFG_QM_TENSOR_6_PADDING_VALUE 0xE46B58
+
+#define mmTPC1_CFG_QM_TENSOR_6_TENSOR_CONFIG 0xE46B5C
+
+#define mmTPC1_CFG_QM_TENSOR_6_DIM_0_SIZE 0xE46B60
+
+#define mmTPC1_CFG_QM_TENSOR_6_DIM_0_STRIDE 0xE46B64
+
+#define mmTPC1_CFG_QM_TENSOR_6_DIM_1_SIZE 0xE46B68
+
+#define mmTPC1_CFG_QM_TENSOR_6_DIM_1_STRIDE 0xE46B6C
+
+#define mmTPC1_CFG_QM_TENSOR_6_DIM_2_SIZE 0xE46B70
+
+#define mmTPC1_CFG_QM_TENSOR_6_DIM_2_STRIDE 0xE46B74
+
+#define mmTPC1_CFG_QM_TENSOR_6_DIM_3_SIZE 0xE46B78
+
+#define mmTPC1_CFG_QM_TENSOR_6_DIM_3_STRIDE 0xE46B7C
+
+#define mmTPC1_CFG_QM_TENSOR_6_DIM_4_SIZE 0xE46B80
+
+#define mmTPC1_CFG_QM_TENSOR_6_DIM_4_STRIDE 0xE46B84
+
+#define mmTPC1_CFG_QM_TENSOR_7_BASE_ADDR_LOW 0xE46B88
+
+#define mmTPC1_CFG_QM_TENSOR_7_BASE_ADDR_HIGH 0xE46B8C
+
+#define mmTPC1_CFG_QM_TENSOR_7_PADDING_VALUE 0xE46B90
+
+#define mmTPC1_CFG_QM_TENSOR_7_TENSOR_CONFIG 0xE46B94
+
+#define mmTPC1_CFG_QM_TENSOR_7_DIM_0_SIZE 0xE46B98
+
+#define mmTPC1_CFG_QM_TENSOR_7_DIM_0_STRIDE 0xE46B9C
+
+#define mmTPC1_CFG_QM_TENSOR_7_DIM_1_SIZE 0xE46BA0
+
+#define mmTPC1_CFG_QM_TENSOR_7_DIM_1_STRIDE 0xE46BA4
+
+#define mmTPC1_CFG_QM_TENSOR_7_DIM_2_SIZE 0xE46BA8
+
+#define mmTPC1_CFG_QM_TENSOR_7_DIM_2_STRIDE 0xE46BAC
+
+#define mmTPC1_CFG_QM_TENSOR_7_DIM_3_SIZE 0xE46BB0
+
+#define mmTPC1_CFG_QM_TENSOR_7_DIM_3_STRIDE 0xE46BB4
+
+#define mmTPC1_CFG_QM_TENSOR_7_DIM_4_SIZE 0xE46BB8
+
+#define mmTPC1_CFG_QM_TENSOR_7_DIM_4_STRIDE 0xE46BBC
+
+#define mmTPC1_CFG_QM_TENSOR_8_BASE_ADDR_LOW 0xE46BC0
+
+#define mmTPC1_CFG_QM_TENSOR_8_BASE_ADDR_HIGH 0xE46BC4
+
+#define mmTPC1_CFG_QM_TENSOR_8_PADDING_VALUE 0xE46BC8
+
+#define mmTPC1_CFG_QM_TENSOR_8_TENSOR_CONFIG 0xE46BCC
+
+#define mmTPC1_CFG_QM_TENSOR_8_DIM_0_SIZE 0xE46BD0
+
+#define mmTPC1_CFG_QM_TENSOR_8_DIM_0_STRIDE 0xE46BD4
+
+#define mmTPC1_CFG_QM_TENSOR_8_DIM_1_SIZE 0xE46BD8
+
+#define mmTPC1_CFG_QM_TENSOR_8_DIM_1_STRIDE 0xE46BDC
+
+#define mmTPC1_CFG_QM_TENSOR_8_DIM_2_SIZE 0xE46BE0
+
+#define mmTPC1_CFG_QM_TENSOR_8_DIM_2_STRIDE 0xE46BE4
+
+#define mmTPC1_CFG_QM_TENSOR_8_DIM_3_SIZE 0xE46BE8
+
+#define mmTPC1_CFG_QM_TENSOR_8_DIM_3_STRIDE 0xE46BEC
+
+#define mmTPC1_CFG_QM_TENSOR_8_DIM_4_SIZE 0xE46BF0
+
+#define mmTPC1_CFG_QM_TENSOR_8_DIM_4_STRIDE 0xE46BF4
+
+#define mmTPC1_CFG_QM_TENSOR_9_BASE_ADDR_LOW 0xE46BF8
+
+#define mmTPC1_CFG_QM_TENSOR_9_BASE_ADDR_HIGH 0xE46BFC
+
+#define mmTPC1_CFG_QM_TENSOR_9_PADDING_VALUE 0xE46C00
+
+#define mmTPC1_CFG_QM_TENSOR_9_TENSOR_CONFIG 0xE46C04
+
+#define mmTPC1_CFG_QM_TENSOR_9_DIM_0_SIZE 0xE46C08
+
+#define mmTPC1_CFG_QM_TENSOR_9_DIM_0_STRIDE 0xE46C0C
+
+#define mmTPC1_CFG_QM_TENSOR_9_DIM_1_SIZE 0xE46C10
+
+#define mmTPC1_CFG_QM_TENSOR_9_DIM_1_STRIDE 0xE46C14
+
+#define mmTPC1_CFG_QM_TENSOR_9_DIM_2_SIZE 0xE46C18
+
+#define mmTPC1_CFG_QM_TENSOR_9_DIM_2_STRIDE 0xE46C1C
+
+#define mmTPC1_CFG_QM_TENSOR_9_DIM_3_SIZE 0xE46C20
+
+#define mmTPC1_CFG_QM_TENSOR_9_DIM_3_STRIDE 0xE46C24
+
+#define mmTPC1_CFG_QM_TENSOR_9_DIM_4_SIZE 0xE46C28
+
+#define mmTPC1_CFG_QM_TENSOR_9_DIM_4_STRIDE 0xE46C2C
+
+#define mmTPC1_CFG_QM_TENSOR_10_BASE_ADDR_LOW 0xE46C30
+
+#define mmTPC1_CFG_QM_TENSOR_10_BASE_ADDR_HIGH 0xE46C34
+
+#define mmTPC1_CFG_QM_TENSOR_10_PADDING_VALUE 0xE46C38
+
+#define mmTPC1_CFG_QM_TENSOR_10_TENSOR_CONFIG 0xE46C3C
+
+#define mmTPC1_CFG_QM_TENSOR_10_DIM_0_SIZE 0xE46C40
+
+#define mmTPC1_CFG_QM_TENSOR_10_DIM_0_STRIDE 0xE46C44
+
+#define mmTPC1_CFG_QM_TENSOR_10_DIM_1_SIZE 0xE46C48
+
+#define mmTPC1_CFG_QM_TENSOR_10_DIM_1_STRIDE 0xE46C4C
+
+#define mmTPC1_CFG_QM_TENSOR_10_DIM_2_SIZE 0xE46C50
+
+#define mmTPC1_CFG_QM_TENSOR_10_DIM_2_STRIDE 0xE46C54
+
+#define mmTPC1_CFG_QM_TENSOR_10_DIM_3_SIZE 0xE46C58
+
+#define mmTPC1_CFG_QM_TENSOR_10_DIM_3_STRIDE 0xE46C5C
+
+#define mmTPC1_CFG_QM_TENSOR_10_DIM_4_SIZE 0xE46C60
+
+#define mmTPC1_CFG_QM_TENSOR_10_DIM_4_STRIDE 0xE46C64
+
+#define mmTPC1_CFG_QM_TENSOR_11_BASE_ADDR_LOW 0xE46C68
+
+#define mmTPC1_CFG_QM_TENSOR_11_BASE_ADDR_HIGH 0xE46C6C
+
+#define mmTPC1_CFG_QM_TENSOR_11_PADDING_VALUE 0xE46C70
+
+#define mmTPC1_CFG_QM_TENSOR_11_TENSOR_CONFIG 0xE46C74
+
+#define mmTPC1_CFG_QM_TENSOR_11_DIM_0_SIZE 0xE46C78
+
+#define mmTPC1_CFG_QM_TENSOR_11_DIM_0_STRIDE 0xE46C7C
+
+#define mmTPC1_CFG_QM_TENSOR_11_DIM_1_SIZE 0xE46C80
+
+#define mmTPC1_CFG_QM_TENSOR_11_DIM_1_STRIDE 0xE46C84
+
+#define mmTPC1_CFG_QM_TENSOR_11_DIM_2_SIZE 0xE46C88
+
+#define mmTPC1_CFG_QM_TENSOR_11_DIM_2_STRIDE 0xE46C8C
+
+#define mmTPC1_CFG_QM_TENSOR_11_DIM_3_SIZE 0xE46C90
+
+#define mmTPC1_CFG_QM_TENSOR_11_DIM_3_STRIDE 0xE46C94
+
+#define mmTPC1_CFG_QM_TENSOR_11_DIM_4_SIZE 0xE46C98
+
+#define mmTPC1_CFG_QM_TENSOR_11_DIM_4_STRIDE 0xE46C9C
+
+#define mmTPC1_CFG_QM_TENSOR_12_BASE_ADDR_LOW 0xE46CA0
+
+#define mmTPC1_CFG_QM_TENSOR_12_BASE_ADDR_HIGH 0xE46CA4
+
+#define mmTPC1_CFG_QM_TENSOR_12_PADDING_VALUE 0xE46CA8
+
+#define mmTPC1_CFG_QM_TENSOR_12_TENSOR_CONFIG 0xE46CAC
+
+#define mmTPC1_CFG_QM_TENSOR_12_DIM_0_SIZE 0xE46CB0
+
+#define mmTPC1_CFG_QM_TENSOR_12_DIM_0_STRIDE 0xE46CB4
+
+#define mmTPC1_CFG_QM_TENSOR_12_DIM_1_SIZE 0xE46CB8
+
+#define mmTPC1_CFG_QM_TENSOR_12_DIM_1_STRIDE 0xE46CBC
+
+#define mmTPC1_CFG_QM_TENSOR_12_DIM_2_SIZE 0xE46CC0
+
+#define mmTPC1_CFG_QM_TENSOR_12_DIM_2_STRIDE 0xE46CC4
+
+#define mmTPC1_CFG_QM_TENSOR_12_DIM_3_SIZE 0xE46CC8
+
+#define mmTPC1_CFG_QM_TENSOR_12_DIM_3_STRIDE 0xE46CCC
+
+#define mmTPC1_CFG_QM_TENSOR_12_DIM_4_SIZE 0xE46CD0
+
+#define mmTPC1_CFG_QM_TENSOR_12_DIM_4_STRIDE 0xE46CD4
+
+#define mmTPC1_CFG_QM_TENSOR_13_BASE_ADDR_LOW 0xE46CD8
+
+#define mmTPC1_CFG_QM_TENSOR_13_BASE_ADDR_HIGH 0xE46CDC
+
+#define mmTPC1_CFG_QM_TENSOR_13_PADDING_VALUE 0xE46CE0
+
+#define mmTPC1_CFG_QM_TENSOR_13_TENSOR_CONFIG 0xE46CE4
+
+#define mmTPC1_CFG_QM_TENSOR_13_DIM_0_SIZE 0xE46CE8
+
+#define mmTPC1_CFG_QM_TENSOR_13_DIM_0_STRIDE 0xE46CEC
+
+#define mmTPC1_CFG_QM_TENSOR_13_DIM_1_SIZE 0xE46CF0
+
+#define mmTPC1_CFG_QM_TENSOR_13_DIM_1_STRIDE 0xE46CF4
+
+#define mmTPC1_CFG_QM_TENSOR_13_DIM_2_SIZE 0xE46CF8
+
+#define mmTPC1_CFG_QM_TENSOR_13_DIM_2_STRIDE 0xE46CFC
+
+#define mmTPC1_CFG_QM_TENSOR_13_DIM_3_SIZE 0xE46D00
+
+#define mmTPC1_CFG_QM_TENSOR_13_DIM_3_STRIDE 0xE46D04
+
+#define mmTPC1_CFG_QM_TENSOR_13_DIM_4_SIZE 0xE46D08
+
+#define mmTPC1_CFG_QM_TENSOR_13_DIM_4_STRIDE 0xE46D0C
+
+#define mmTPC1_CFG_QM_TENSOR_14_BASE_ADDR_LOW 0xE46D10
+
+#define mmTPC1_CFG_QM_TENSOR_14_BASE_ADDR_HIGH 0xE46D14
+
+#define mmTPC1_CFG_QM_TENSOR_14_PADDING_VALUE 0xE46D18
+
+#define mmTPC1_CFG_QM_TENSOR_14_TENSOR_CONFIG 0xE46D1C
+
+#define mmTPC1_CFG_QM_TENSOR_14_DIM_0_SIZE 0xE46D20
+
+#define mmTPC1_CFG_QM_TENSOR_14_DIM_0_STRIDE 0xE46D24
+
+#define mmTPC1_CFG_QM_TENSOR_14_DIM_1_SIZE 0xE46D28
+
+#define mmTPC1_CFG_QM_TENSOR_14_DIM_1_STRIDE 0xE46D2C
+
+#define mmTPC1_CFG_QM_TENSOR_14_DIM_2_SIZE 0xE46D30
+
+#define mmTPC1_CFG_QM_TENSOR_14_DIM_2_STRIDE 0xE46D34
+
+#define mmTPC1_CFG_QM_TENSOR_14_DIM_3_SIZE 0xE46D38
+
+#define mmTPC1_CFG_QM_TENSOR_14_DIM_3_STRIDE 0xE46D3C
+
+#define mmTPC1_CFG_QM_TENSOR_14_DIM_4_SIZE 0xE46D40
+
+#define mmTPC1_CFG_QM_TENSOR_14_DIM_4_STRIDE 0xE46D44
+
+#define mmTPC1_CFG_QM_TENSOR_15_BASE_ADDR_LOW 0xE46D48
+
+#define mmTPC1_CFG_QM_TENSOR_15_BASE_ADDR_HIGH 0xE46D4C
+
+#define mmTPC1_CFG_QM_TENSOR_15_PADDING_VALUE 0xE46D50
+
+#define mmTPC1_CFG_QM_TENSOR_15_TENSOR_CONFIG 0xE46D54
+
+#define mmTPC1_CFG_QM_TENSOR_15_DIM_0_SIZE 0xE46D58
+
+#define mmTPC1_CFG_QM_TENSOR_15_DIM_0_STRIDE 0xE46D5C
+
+#define mmTPC1_CFG_QM_TENSOR_15_DIM_1_SIZE 0xE46D60
+
+#define mmTPC1_CFG_QM_TENSOR_15_DIM_1_STRIDE 0xE46D64
+
+#define mmTPC1_CFG_QM_TENSOR_15_DIM_2_SIZE 0xE46D68
+
+#define mmTPC1_CFG_QM_TENSOR_15_DIM_2_STRIDE 0xE46D6C
+
+#define mmTPC1_CFG_QM_TENSOR_15_DIM_3_SIZE 0xE46D70
+
+#define mmTPC1_CFG_QM_TENSOR_15_DIM_3_STRIDE 0xE46D74
+
+#define mmTPC1_CFG_QM_TENSOR_15_DIM_4_SIZE 0xE46D78
+
+#define mmTPC1_CFG_QM_TENSOR_15_DIM_4_STRIDE 0xE46D7C
+
+#define mmTPC1_CFG_QM_SYNC_OBJECT_MESSAGE 0xE46D80
+
+#define mmTPC1_CFG_QM_SYNC_OBJECT_ADDR 0xE46D84
+
+#define mmTPC1_CFG_QM_KERNEL_BASE_ADDRESS_LOW 0xE46D88
+
+#define mmTPC1_CFG_QM_KERNEL_BASE_ADDRESS_HIGH 0xE46D8C
+
+#define mmTPC1_CFG_QM_TID_BASE_DIM_0 0xE46D90
+
+#define mmTPC1_CFG_QM_TID_SIZE_DIM_0 0xE46D94
+
+#define mmTPC1_CFG_QM_TID_BASE_DIM_1 0xE46D98
+
+#define mmTPC1_CFG_QM_TID_SIZE_DIM_1 0xE46D9C
+
+#define mmTPC1_CFG_QM_TID_BASE_DIM_2 0xE46DA0
+
+#define mmTPC1_CFG_QM_TID_SIZE_DIM_2 0xE46DA4
+
+#define mmTPC1_CFG_QM_TID_BASE_DIM_3 0xE46DA8
+
+#define mmTPC1_CFG_QM_TID_SIZE_DIM_3 0xE46DAC
+
+#define mmTPC1_CFG_QM_TID_BASE_DIM_4 0xE46DB0
+
+#define mmTPC1_CFG_QM_TID_SIZE_DIM_4 0xE46DB4
+
+#define mmTPC1_CFG_QM_KERNEL_CONFIG 0xE46DB8
+
+#define mmTPC1_CFG_QM_KERNEL_ID 0xE46DBC
+
+#define mmTPC1_CFG_QM_SRF_0 0xE46DC0
+
+#define mmTPC1_CFG_QM_SRF_1 0xE46DC4
+
+#define mmTPC1_CFG_QM_SRF_2 0xE46DC8
+
+#define mmTPC1_CFG_QM_SRF_3 0xE46DCC
+
+#define mmTPC1_CFG_QM_SRF_4 0xE46DD0
+
+#define mmTPC1_CFG_QM_SRF_5 0xE46DD4
+
+#define mmTPC1_CFG_QM_SRF_6 0xE46DD8
+
+#define mmTPC1_CFG_QM_SRF_7 0xE46DDC
+
+#define mmTPC1_CFG_QM_SRF_8 0xE46DE0
+
+#define mmTPC1_CFG_QM_SRF_9 0xE46DE4
+
+#define mmTPC1_CFG_QM_SRF_10 0xE46DE8
+
+#define mmTPC1_CFG_QM_SRF_11 0xE46DEC
+
+#define mmTPC1_CFG_QM_SRF_12 0xE46DF0
+
+#define mmTPC1_CFG_QM_SRF_13 0xE46DF4
+
+#define mmTPC1_CFG_QM_SRF_14 0xE46DF8
+
+#define mmTPC1_CFG_QM_SRF_15 0xE46DFC
+
+#define mmTPC1_CFG_QM_SRF_16 0xE46E00
+
+#define mmTPC1_CFG_QM_SRF_17 0xE46E04
+
+#define mmTPC1_CFG_QM_SRF_18 0xE46E08
+
+#define mmTPC1_CFG_QM_SRF_19 0xE46E0C
+
+#define mmTPC1_CFG_QM_SRF_20 0xE46E10
+
+#define mmTPC1_CFG_QM_SRF_21 0xE46E14
+
+#define mmTPC1_CFG_QM_SRF_22 0xE46E18
+
+#define mmTPC1_CFG_QM_SRF_23 0xE46E1C
+
+#define mmTPC1_CFG_QM_SRF_24 0xE46E20
+
+#define mmTPC1_CFG_QM_SRF_25 0xE46E24
+
+#define mmTPC1_CFG_QM_SRF_26 0xE46E28
+
+#define mmTPC1_CFG_QM_SRF_27 0xE46E2C
+
+#define mmTPC1_CFG_QM_SRF_28 0xE46E30
+
+#define mmTPC1_CFG_QM_SRF_29 0xE46E34
+
+#define mmTPC1_CFG_QM_SRF_30 0xE46E38
+
+#define mmTPC1_CFG_QM_SRF_31 0xE46E3C
+
+#endif /* ASIC_REG_TPC1_CFG_REGS_H_ */
diff --git a/drivers/accel/habanalabs/include/gaudi/asic_reg/tpc1_qm_regs.h b/drivers/accel/habanalabs/include/gaudi/asic_reg/tpc1_qm_regs.h
new file mode 100644
index 0000000000..af10ef7a87
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi/asic_reg/tpc1_qm_regs.h
@@ -0,0 +1,834 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2016-2018 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ ** DO NOT EDIT BELOW **
+ ************************************/
+
+#ifndef ASIC_REG_TPC1_QM_REGS_H_
+#define ASIC_REG_TPC1_QM_REGS_H_
+
+/*
+ *****************************************
+ * TPC1_QM (Prototype: QMAN)
+ *****************************************
+ */
+
+#define mmTPC1_QM_GLBL_CFG0 0xE48000
+
+#define mmTPC1_QM_GLBL_CFG1 0xE48004
+
+#define mmTPC1_QM_GLBL_PROT 0xE48008
+
+#define mmTPC1_QM_GLBL_ERR_CFG 0xE4800C
+
+#define mmTPC1_QM_GLBL_SECURE_PROPS_0 0xE48010
+
+#define mmTPC1_QM_GLBL_SECURE_PROPS_1 0xE48014
+
+#define mmTPC1_QM_GLBL_SECURE_PROPS_2 0xE48018
+
+#define mmTPC1_QM_GLBL_SECURE_PROPS_3 0xE4801C
+
+#define mmTPC1_QM_GLBL_SECURE_PROPS_4 0xE48020
+
+#define mmTPC1_QM_GLBL_NON_SECURE_PROPS_0 0xE48024
+
+#define mmTPC1_QM_GLBL_NON_SECURE_PROPS_1 0xE48028
+
+#define mmTPC1_QM_GLBL_NON_SECURE_PROPS_2 0xE4802C
+
+#define mmTPC1_QM_GLBL_NON_SECURE_PROPS_3 0xE48030
+
+#define mmTPC1_QM_GLBL_NON_SECURE_PROPS_4 0xE48034
+
+#define mmTPC1_QM_GLBL_STS0 0xE48038
+
+#define mmTPC1_QM_GLBL_STS1_0 0xE48040
+
+#define mmTPC1_QM_GLBL_STS1_1 0xE48044
+
+#define mmTPC1_QM_GLBL_STS1_2 0xE48048
+
+#define mmTPC1_QM_GLBL_STS1_3 0xE4804C
+
+#define mmTPC1_QM_GLBL_STS1_4 0xE48050
+
+#define mmTPC1_QM_GLBL_MSG_EN_0 0xE48054
+
+#define mmTPC1_QM_GLBL_MSG_EN_1 0xE48058
+
+#define mmTPC1_QM_GLBL_MSG_EN_2 0xE4805C
+
+#define mmTPC1_QM_GLBL_MSG_EN_3 0xE48060
+
+#define mmTPC1_QM_GLBL_MSG_EN_4 0xE48068
+
+#define mmTPC1_QM_PQ_BASE_LO_0 0xE48070
+
+#define mmTPC1_QM_PQ_BASE_LO_1 0xE48074
+
+#define mmTPC1_QM_PQ_BASE_LO_2 0xE48078
+
+#define mmTPC1_QM_PQ_BASE_LO_3 0xE4807C
+
+#define mmTPC1_QM_PQ_BASE_HI_0 0xE48080
+
+#define mmTPC1_QM_PQ_BASE_HI_1 0xE48084
+
+#define mmTPC1_QM_PQ_BASE_HI_2 0xE48088
+
+#define mmTPC1_QM_PQ_BASE_HI_3 0xE4808C
+
+#define mmTPC1_QM_PQ_SIZE_0 0xE48090
+
+#define mmTPC1_QM_PQ_SIZE_1 0xE48094
+
+#define mmTPC1_QM_PQ_SIZE_2 0xE48098
+
+#define mmTPC1_QM_PQ_SIZE_3 0xE4809C
+
+#define mmTPC1_QM_PQ_PI_0 0xE480A0
+
+#define mmTPC1_QM_PQ_PI_1 0xE480A4
+
+#define mmTPC1_QM_PQ_PI_2 0xE480A8
+
+#define mmTPC1_QM_PQ_PI_3 0xE480AC
+
+#define mmTPC1_QM_PQ_CI_0 0xE480B0
+
+#define mmTPC1_QM_PQ_CI_1 0xE480B4
+
+#define mmTPC1_QM_PQ_CI_2 0xE480B8
+
+#define mmTPC1_QM_PQ_CI_3 0xE480BC
+
+#define mmTPC1_QM_PQ_CFG0_0 0xE480C0
+
+#define mmTPC1_QM_PQ_CFG0_1 0xE480C4
+
+#define mmTPC1_QM_PQ_CFG0_2 0xE480C8
+
+#define mmTPC1_QM_PQ_CFG0_3 0xE480CC
+
+#define mmTPC1_QM_PQ_CFG1_0 0xE480D0
+
+#define mmTPC1_QM_PQ_CFG1_1 0xE480D4
+
+#define mmTPC1_QM_PQ_CFG1_2 0xE480D8
+
+#define mmTPC1_QM_PQ_CFG1_3 0xE480DC
+
+#define mmTPC1_QM_PQ_ARUSER_31_11_0 0xE480E0
+
+#define mmTPC1_QM_PQ_ARUSER_31_11_1 0xE480E4
+
+#define mmTPC1_QM_PQ_ARUSER_31_11_2 0xE480E8
+
+#define mmTPC1_QM_PQ_ARUSER_31_11_3 0xE480EC
+
+#define mmTPC1_QM_PQ_STS0_0 0xE480F0
+
+#define mmTPC1_QM_PQ_STS0_1 0xE480F4
+
+#define mmTPC1_QM_PQ_STS0_2 0xE480F8
+
+#define mmTPC1_QM_PQ_STS0_3 0xE480FC
+
+#define mmTPC1_QM_PQ_STS1_0 0xE48100
+
+#define mmTPC1_QM_PQ_STS1_1 0xE48104
+
+#define mmTPC1_QM_PQ_STS1_2 0xE48108
+
+#define mmTPC1_QM_PQ_STS1_3 0xE4810C
+
+#define mmTPC1_QM_CQ_CFG0_0 0xE48110
+
+#define mmTPC1_QM_CQ_CFG0_1 0xE48114
+
+#define mmTPC1_QM_CQ_CFG0_2 0xE48118
+
+#define mmTPC1_QM_CQ_CFG0_3 0xE4811C
+
+#define mmTPC1_QM_CQ_CFG0_4 0xE48120
+
+#define mmTPC1_QM_CQ_CFG1_0 0xE48124
+
+#define mmTPC1_QM_CQ_CFG1_1 0xE48128
+
+#define mmTPC1_QM_CQ_CFG1_2 0xE4812C
+
+#define mmTPC1_QM_CQ_CFG1_3 0xE48130
+
+#define mmTPC1_QM_CQ_CFG1_4 0xE48134
+
+#define mmTPC1_QM_CQ_ARUSER_31_11_0 0xE48138
+
+#define mmTPC1_QM_CQ_ARUSER_31_11_1 0xE4813C
+
+#define mmTPC1_QM_CQ_ARUSER_31_11_2 0xE48140
+
+#define mmTPC1_QM_CQ_ARUSER_31_11_3 0xE48144
+
+#define mmTPC1_QM_CQ_ARUSER_31_11_4 0xE48148
+
+#define mmTPC1_QM_CQ_STS0_0 0xE4814C
+
+#define mmTPC1_QM_CQ_STS0_1 0xE48150
+
+#define mmTPC1_QM_CQ_STS0_2 0xE48154
+
+#define mmTPC1_QM_CQ_STS0_3 0xE48158
+
+#define mmTPC1_QM_CQ_STS0_4 0xE4815C
+
+#define mmTPC1_QM_CQ_STS1_0 0xE48160
+
+#define mmTPC1_QM_CQ_STS1_1 0xE48164
+
+#define mmTPC1_QM_CQ_STS1_2 0xE48168
+
+#define mmTPC1_QM_CQ_STS1_3 0xE4816C
+
+#define mmTPC1_QM_CQ_STS1_4 0xE48170
+
+#define mmTPC1_QM_CQ_PTR_LO_0 0xE48174
+
+#define mmTPC1_QM_CQ_PTR_HI_0 0xE48178
+
+#define mmTPC1_QM_CQ_TSIZE_0 0xE4817C
+
+#define mmTPC1_QM_CQ_CTL_0 0xE48180
+
+#define mmTPC1_QM_CQ_PTR_LO_1 0xE48184
+
+#define mmTPC1_QM_CQ_PTR_HI_1 0xE48188
+
+#define mmTPC1_QM_CQ_TSIZE_1 0xE4818C
+
+#define mmTPC1_QM_CQ_CTL_1 0xE48190
+
+#define mmTPC1_QM_CQ_PTR_LO_2 0xE48194
+
+#define mmTPC1_QM_CQ_PTR_HI_2 0xE48198
+
+#define mmTPC1_QM_CQ_TSIZE_2 0xE4819C
+
+#define mmTPC1_QM_CQ_CTL_2 0xE481A0
+
+#define mmTPC1_QM_CQ_PTR_LO_3 0xE481A4
+
+#define mmTPC1_QM_CQ_PTR_HI_3 0xE481A8
+
+#define mmTPC1_QM_CQ_TSIZE_3 0xE481AC
+
+#define mmTPC1_QM_CQ_CTL_3 0xE481B0
+
+#define mmTPC1_QM_CQ_PTR_LO_4 0xE481B4
+
+#define mmTPC1_QM_CQ_PTR_HI_4 0xE481B8
+
+#define mmTPC1_QM_CQ_TSIZE_4 0xE481BC
+
+#define mmTPC1_QM_CQ_CTL_4 0xE481C0
+
+#define mmTPC1_QM_CQ_PTR_LO_STS_0 0xE481C4
+
+#define mmTPC1_QM_CQ_PTR_LO_STS_1 0xE481C8
+
+#define mmTPC1_QM_CQ_PTR_LO_STS_2 0xE481CC
+
+#define mmTPC1_QM_CQ_PTR_LO_STS_3 0xE481D0
+
+#define mmTPC1_QM_CQ_PTR_LO_STS_4 0xE481D4
+
+#define mmTPC1_QM_CQ_PTR_HI_STS_0 0xE481D8
+
+#define mmTPC1_QM_CQ_PTR_HI_STS_1 0xE481DC
+
+#define mmTPC1_QM_CQ_PTR_HI_STS_2 0xE481E0
+
+#define mmTPC1_QM_CQ_PTR_HI_STS_3 0xE481E4
+
+#define mmTPC1_QM_CQ_PTR_HI_STS_4 0xE481E8
+
+#define mmTPC1_QM_CQ_TSIZE_STS_0 0xE481EC
+
+#define mmTPC1_QM_CQ_TSIZE_STS_1 0xE481F0
+
+#define mmTPC1_QM_CQ_TSIZE_STS_2 0xE481F4
+
+#define mmTPC1_QM_CQ_TSIZE_STS_3 0xE481F8
+
+#define mmTPC1_QM_CQ_TSIZE_STS_4 0xE481FC
+
+#define mmTPC1_QM_CQ_CTL_STS_0 0xE48200
+
+#define mmTPC1_QM_CQ_CTL_STS_1 0xE48204
+
+#define mmTPC1_QM_CQ_CTL_STS_2 0xE48208
+
+#define mmTPC1_QM_CQ_CTL_STS_3 0xE4820C
+
+#define mmTPC1_QM_CQ_CTL_STS_4 0xE48210
+
+#define mmTPC1_QM_CQ_IFIFO_CNT_0 0xE48214
+
+#define mmTPC1_QM_CQ_IFIFO_CNT_1 0xE48218
+
+#define mmTPC1_QM_CQ_IFIFO_CNT_2 0xE4821C
+
+#define mmTPC1_QM_CQ_IFIFO_CNT_3 0xE48220
+
+#define mmTPC1_QM_CQ_IFIFO_CNT_4 0xE48224
+
+#define mmTPC1_QM_CP_MSG_BASE0_ADDR_LO_0 0xE48228
+
+#define mmTPC1_QM_CP_MSG_BASE0_ADDR_LO_1 0xE4822C
+
+#define mmTPC1_QM_CP_MSG_BASE0_ADDR_LO_2 0xE48230
+
+#define mmTPC1_QM_CP_MSG_BASE0_ADDR_LO_3 0xE48234
+
+#define mmTPC1_QM_CP_MSG_BASE0_ADDR_LO_4 0xE48238
+
+#define mmTPC1_QM_CP_MSG_BASE0_ADDR_HI_0 0xE4823C
+
+#define mmTPC1_QM_CP_MSG_BASE0_ADDR_HI_1 0xE48240
+
+#define mmTPC1_QM_CP_MSG_BASE0_ADDR_HI_2 0xE48244
+
+#define mmTPC1_QM_CP_MSG_BASE0_ADDR_HI_3 0xE48248
+
+#define mmTPC1_QM_CP_MSG_BASE0_ADDR_HI_4 0xE4824C
+
+#define mmTPC1_QM_CP_MSG_BASE1_ADDR_LO_0 0xE48250
+
+#define mmTPC1_QM_CP_MSG_BASE1_ADDR_LO_1 0xE48254
+
+#define mmTPC1_QM_CP_MSG_BASE1_ADDR_LO_2 0xE48258
+
+#define mmTPC1_QM_CP_MSG_BASE1_ADDR_LO_3 0xE4825C
+
+#define mmTPC1_QM_CP_MSG_BASE1_ADDR_LO_4 0xE48260
+
+#define mmTPC1_QM_CP_MSG_BASE1_ADDR_HI_0 0xE48264
+
+#define mmTPC1_QM_CP_MSG_BASE1_ADDR_HI_1 0xE48268
+
+#define mmTPC1_QM_CP_MSG_BASE1_ADDR_HI_2 0xE4826C
+
+#define mmTPC1_QM_CP_MSG_BASE1_ADDR_HI_3 0xE48270
+
+#define mmTPC1_QM_CP_MSG_BASE1_ADDR_HI_4 0xE48274
+
+#define mmTPC1_QM_CP_MSG_BASE2_ADDR_LO_0 0xE48278
+
+#define mmTPC1_QM_CP_MSG_BASE2_ADDR_LO_1 0xE4827C
+
+#define mmTPC1_QM_CP_MSG_BASE2_ADDR_LO_2 0xE48280
+
+#define mmTPC1_QM_CP_MSG_BASE2_ADDR_LO_3 0xE48284
+
+#define mmTPC1_QM_CP_MSG_BASE2_ADDR_LO_4 0xE48288
+
+#define mmTPC1_QM_CP_MSG_BASE2_ADDR_HI_0 0xE4828C
+
+#define mmTPC1_QM_CP_MSG_BASE2_ADDR_HI_1 0xE48290
+
+#define mmTPC1_QM_CP_MSG_BASE2_ADDR_HI_2 0xE48294
+
+#define mmTPC1_QM_CP_MSG_BASE2_ADDR_HI_3 0xE48298
+
+#define mmTPC1_QM_CP_MSG_BASE2_ADDR_HI_4 0xE4829C
+
+#define mmTPC1_QM_CP_MSG_BASE3_ADDR_LO_0 0xE482A0
+
+#define mmTPC1_QM_CP_MSG_BASE3_ADDR_LO_1 0xE482A4
+
+#define mmTPC1_QM_CP_MSG_BASE3_ADDR_LO_2 0xE482A8
+
+#define mmTPC1_QM_CP_MSG_BASE3_ADDR_LO_3 0xE482AC
+
+#define mmTPC1_QM_CP_MSG_BASE3_ADDR_LO_4 0xE482B0
+
+#define mmTPC1_QM_CP_MSG_BASE3_ADDR_HI_0 0xE482B4
+
+#define mmTPC1_QM_CP_MSG_BASE3_ADDR_HI_1 0xE482B8
+
+#define mmTPC1_QM_CP_MSG_BASE3_ADDR_HI_2 0xE482BC
+
+#define mmTPC1_QM_CP_MSG_BASE3_ADDR_HI_3 0xE482C0
+
+#define mmTPC1_QM_CP_MSG_BASE3_ADDR_HI_4 0xE482C4
+
+#define mmTPC1_QM_CP_LDMA_TSIZE_OFFSET_0 0xE482C8
+
+#define mmTPC1_QM_CP_LDMA_TSIZE_OFFSET_1 0xE482CC
+
+#define mmTPC1_QM_CP_LDMA_TSIZE_OFFSET_2 0xE482D0
+
+#define mmTPC1_QM_CP_LDMA_TSIZE_OFFSET_3 0xE482D4
+
+#define mmTPC1_QM_CP_LDMA_TSIZE_OFFSET_4 0xE482D8
+
+#define mmTPC1_QM_CP_LDMA_SRC_BASE_LO_OFFSET_0 0xE482E0
+
+#define mmTPC1_QM_CP_LDMA_SRC_BASE_LO_OFFSET_1 0xE482E4
+
+#define mmTPC1_QM_CP_LDMA_SRC_BASE_LO_OFFSET_2 0xE482E8
+
+#define mmTPC1_QM_CP_LDMA_SRC_BASE_LO_OFFSET_3 0xE482EC
+
+#define mmTPC1_QM_CP_LDMA_SRC_BASE_LO_OFFSET_4 0xE482F0
+
+#define mmTPC1_QM_CP_LDMA_DST_BASE_LO_OFFSET_0 0xE482F4
+
+#define mmTPC1_QM_CP_LDMA_DST_BASE_LO_OFFSET_1 0xE482F8
+
+#define mmTPC1_QM_CP_LDMA_DST_BASE_LO_OFFSET_2 0xE482FC
+
+#define mmTPC1_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 0xE48300
+
+#define mmTPC1_QM_CP_LDMA_DST_BASE_LO_OFFSET_4 0xE48304
+
+#define mmTPC1_QM_CP_FENCE0_RDATA_0 0xE48308
+
+#define mmTPC1_QM_CP_FENCE0_RDATA_1 0xE4830C
+
+#define mmTPC1_QM_CP_FENCE0_RDATA_2 0xE48310
+
+#define mmTPC1_QM_CP_FENCE0_RDATA_3 0xE48314
+
+#define mmTPC1_QM_CP_FENCE0_RDATA_4 0xE48318
+
+#define mmTPC1_QM_CP_FENCE1_RDATA_0 0xE4831C
+
+#define mmTPC1_QM_CP_FENCE1_RDATA_1 0xE48320
+
+#define mmTPC1_QM_CP_FENCE1_RDATA_2 0xE48324
+
+#define mmTPC1_QM_CP_FENCE1_RDATA_3 0xE48328
+
+#define mmTPC1_QM_CP_FENCE1_RDATA_4 0xE4832C
+
+#define mmTPC1_QM_CP_FENCE2_RDATA_0 0xE48330
+
+#define mmTPC1_QM_CP_FENCE2_RDATA_1 0xE48334
+
+#define mmTPC1_QM_CP_FENCE2_RDATA_2 0xE48338
+
+#define mmTPC1_QM_CP_FENCE2_RDATA_3 0xE4833C
+
+#define mmTPC1_QM_CP_FENCE2_RDATA_4 0xE48340
+
+#define mmTPC1_QM_CP_FENCE3_RDATA_0 0xE48344
+
+#define mmTPC1_QM_CP_FENCE3_RDATA_1 0xE48348
+
+#define mmTPC1_QM_CP_FENCE3_RDATA_2 0xE4834C
+
+#define mmTPC1_QM_CP_FENCE3_RDATA_3 0xE48350
+
+#define mmTPC1_QM_CP_FENCE3_RDATA_4 0xE48354
+
+#define mmTPC1_QM_CP_FENCE0_CNT_0 0xE48358
+
+#define mmTPC1_QM_CP_FENCE0_CNT_1 0xE4835C
+
+#define mmTPC1_QM_CP_FENCE0_CNT_2 0xE48360
+
+#define mmTPC1_QM_CP_FENCE0_CNT_3 0xE48364
+
+#define mmTPC1_QM_CP_FENCE0_CNT_4 0xE48368
+
+#define mmTPC1_QM_CP_FENCE1_CNT_0 0xE4836C
+
+#define mmTPC1_QM_CP_FENCE1_CNT_1 0xE48370
+
+#define mmTPC1_QM_CP_FENCE1_CNT_2 0xE48374
+
+#define mmTPC1_QM_CP_FENCE1_CNT_3 0xE48378
+
+#define mmTPC1_QM_CP_FENCE1_CNT_4 0xE4837C
+
+#define mmTPC1_QM_CP_FENCE2_CNT_0 0xE48380
+
+#define mmTPC1_QM_CP_FENCE2_CNT_1 0xE48384
+
+#define mmTPC1_QM_CP_FENCE2_CNT_2 0xE48388
+
+#define mmTPC1_QM_CP_FENCE2_CNT_3 0xE4838C
+
+#define mmTPC1_QM_CP_FENCE2_CNT_4 0xE48390
+
+#define mmTPC1_QM_CP_FENCE3_CNT_0 0xE48394
+
+#define mmTPC1_QM_CP_FENCE3_CNT_1 0xE48398
+
+#define mmTPC1_QM_CP_FENCE3_CNT_2 0xE4839C
+
+#define mmTPC1_QM_CP_FENCE3_CNT_3 0xE483A0
+
+#define mmTPC1_QM_CP_FENCE3_CNT_4 0xE483A4
+
+#define mmTPC1_QM_CP_STS_0 0xE483A8
+
+#define mmTPC1_QM_CP_STS_1 0xE483AC
+
+#define mmTPC1_QM_CP_STS_2 0xE483B0
+
+#define mmTPC1_QM_CP_STS_3 0xE483B4
+
+#define mmTPC1_QM_CP_STS_4 0xE483B8
+
+#define mmTPC1_QM_CP_CURRENT_INST_LO_0 0xE483BC
+
+#define mmTPC1_QM_CP_CURRENT_INST_LO_1 0xE483C0
+
+#define mmTPC1_QM_CP_CURRENT_INST_LO_2 0xE483C4
+
+#define mmTPC1_QM_CP_CURRENT_INST_LO_3 0xE483C8
+
+#define mmTPC1_QM_CP_CURRENT_INST_LO_4 0xE483CC
+
+#define mmTPC1_QM_CP_CURRENT_INST_HI_0 0xE483D0
+
+#define mmTPC1_QM_CP_CURRENT_INST_HI_1 0xE483D4
+
+#define mmTPC1_QM_CP_CURRENT_INST_HI_2 0xE483D8
+
+#define mmTPC1_QM_CP_CURRENT_INST_HI_3 0xE483DC
+
+#define mmTPC1_QM_CP_CURRENT_INST_HI_4 0xE483E0
+
+#define mmTPC1_QM_CP_BARRIER_CFG_0 0xE483F4
+
+#define mmTPC1_QM_CP_BARRIER_CFG_1 0xE483F8
+
+#define mmTPC1_QM_CP_BARRIER_CFG_2 0xE483FC
+
+#define mmTPC1_QM_CP_BARRIER_CFG_3 0xE48400
+
+#define mmTPC1_QM_CP_BARRIER_CFG_4 0xE48404
+
+#define mmTPC1_QM_CP_DBG_0_0 0xE48408
+
+#define mmTPC1_QM_CP_DBG_0_1 0xE4840C
+
+#define mmTPC1_QM_CP_DBG_0_2 0xE48410
+
+#define mmTPC1_QM_CP_DBG_0_3 0xE48414
+
+#define mmTPC1_QM_CP_DBG_0_4 0xE48418
+
+#define mmTPC1_QM_CP_ARUSER_31_11_0 0xE4841C
+
+#define mmTPC1_QM_CP_ARUSER_31_11_1 0xE48420
+
+#define mmTPC1_QM_CP_ARUSER_31_11_2 0xE48424
+
+#define mmTPC1_QM_CP_ARUSER_31_11_3 0xE48428
+
+#define mmTPC1_QM_CP_ARUSER_31_11_4 0xE4842C
+
+#define mmTPC1_QM_CP_AWUSER_31_11_0 0xE48430
+
+#define mmTPC1_QM_CP_AWUSER_31_11_1 0xE48434
+
+#define mmTPC1_QM_CP_AWUSER_31_11_2 0xE48438
+
+#define mmTPC1_QM_CP_AWUSER_31_11_3 0xE4843C
+
+#define mmTPC1_QM_CP_AWUSER_31_11_4 0xE48440
+
+#define mmTPC1_QM_ARB_CFG_0 0xE48A00
+
+#define mmTPC1_QM_ARB_CHOISE_Q_PUSH 0xE48A04
+
+#define mmTPC1_QM_ARB_WRR_WEIGHT_0 0xE48A08
+
+#define mmTPC1_QM_ARB_WRR_WEIGHT_1 0xE48A0C
+
+#define mmTPC1_QM_ARB_WRR_WEIGHT_2 0xE48A10
+
+#define mmTPC1_QM_ARB_WRR_WEIGHT_3 0xE48A14
+
+#define mmTPC1_QM_ARB_CFG_1 0xE48A18
+
+#define mmTPC1_QM_ARB_MST_AVAIL_CRED_0 0xE48A20
+
+#define mmTPC1_QM_ARB_MST_AVAIL_CRED_1 0xE48A24
+
+#define mmTPC1_QM_ARB_MST_AVAIL_CRED_2 0xE48A28
+
+#define mmTPC1_QM_ARB_MST_AVAIL_CRED_3 0xE48A2C
+
+#define mmTPC1_QM_ARB_MST_AVAIL_CRED_4 0xE48A30
+
+#define mmTPC1_QM_ARB_MST_AVAIL_CRED_5 0xE48A34
+
+#define mmTPC1_QM_ARB_MST_AVAIL_CRED_6 0xE48A38
+
+#define mmTPC1_QM_ARB_MST_AVAIL_CRED_7 0xE48A3C
+
+#define mmTPC1_QM_ARB_MST_AVAIL_CRED_8 0xE48A40
+
+#define mmTPC1_QM_ARB_MST_AVAIL_CRED_9 0xE48A44
+
+#define mmTPC1_QM_ARB_MST_AVAIL_CRED_10 0xE48A48
+
+#define mmTPC1_QM_ARB_MST_AVAIL_CRED_11 0xE48A4C
+
+#define mmTPC1_QM_ARB_MST_AVAIL_CRED_12 0xE48A50
+
+#define mmTPC1_QM_ARB_MST_AVAIL_CRED_13 0xE48A54
+
+#define mmTPC1_QM_ARB_MST_AVAIL_CRED_14 0xE48A58
+
+#define mmTPC1_QM_ARB_MST_AVAIL_CRED_15 0xE48A5C
+
+#define mmTPC1_QM_ARB_MST_AVAIL_CRED_16 0xE48A60
+
+#define mmTPC1_QM_ARB_MST_AVAIL_CRED_17 0xE48A64
+
+#define mmTPC1_QM_ARB_MST_AVAIL_CRED_18 0xE48A68
+
+#define mmTPC1_QM_ARB_MST_AVAIL_CRED_19 0xE48A6C
+
+#define mmTPC1_QM_ARB_MST_AVAIL_CRED_20 0xE48A70
+
+#define mmTPC1_QM_ARB_MST_AVAIL_CRED_21 0xE48A74
+
+#define mmTPC1_QM_ARB_MST_AVAIL_CRED_22 0xE48A78
+
+#define mmTPC1_QM_ARB_MST_AVAIL_CRED_23 0xE48A7C
+
+#define mmTPC1_QM_ARB_MST_AVAIL_CRED_24 0xE48A80
+
+#define mmTPC1_QM_ARB_MST_AVAIL_CRED_25 0xE48A84
+
+#define mmTPC1_QM_ARB_MST_AVAIL_CRED_26 0xE48A88
+
+#define mmTPC1_QM_ARB_MST_AVAIL_CRED_27 0xE48A8C
+
+#define mmTPC1_QM_ARB_MST_AVAIL_CRED_28 0xE48A90
+
+#define mmTPC1_QM_ARB_MST_AVAIL_CRED_29 0xE48A94
+
+#define mmTPC1_QM_ARB_MST_AVAIL_CRED_30 0xE48A98
+
+#define mmTPC1_QM_ARB_MST_AVAIL_CRED_31 0xE48A9C
+
+#define mmTPC1_QM_ARB_MST_CRED_INC 0xE48AA0
+
+#define mmTPC1_QM_ARB_MST_CHOISE_PUSH_OFST_0 0xE48AA4
+
+#define mmTPC1_QM_ARB_MST_CHOISE_PUSH_OFST_1 0xE48AA8
+
+#define mmTPC1_QM_ARB_MST_CHOISE_PUSH_OFST_2 0xE48AAC
+
+#define mmTPC1_QM_ARB_MST_CHOISE_PUSH_OFST_3 0xE48AB0
+
+#define mmTPC1_QM_ARB_MST_CHOISE_PUSH_OFST_4 0xE48AB4
+
+#define mmTPC1_QM_ARB_MST_CHOISE_PUSH_OFST_5 0xE48AB8
+
+#define mmTPC1_QM_ARB_MST_CHOISE_PUSH_OFST_6 0xE48ABC
+
+#define mmTPC1_QM_ARB_MST_CHOISE_PUSH_OFST_7 0xE48AC0
+
+#define mmTPC1_QM_ARB_MST_CHOISE_PUSH_OFST_8 0xE48AC4
+
+#define mmTPC1_QM_ARB_MST_CHOISE_PUSH_OFST_9 0xE48AC8
+
+#define mmTPC1_QM_ARB_MST_CHOISE_PUSH_OFST_10 0xE48ACC
+
+#define mmTPC1_QM_ARB_MST_CHOISE_PUSH_OFST_11 0xE48AD0
+
+#define mmTPC1_QM_ARB_MST_CHOISE_PUSH_OFST_12 0xE48AD4
+
+#define mmTPC1_QM_ARB_MST_CHOISE_PUSH_OFST_13 0xE48AD8
+
+#define mmTPC1_QM_ARB_MST_CHOISE_PUSH_OFST_14 0xE48ADC
+
+#define mmTPC1_QM_ARB_MST_CHOISE_PUSH_OFST_15 0xE48AE0
+
+#define mmTPC1_QM_ARB_MST_CHOISE_PUSH_OFST_16 0xE48AE4
+
+#define mmTPC1_QM_ARB_MST_CHOISE_PUSH_OFST_17 0xE48AE8
+
+#define mmTPC1_QM_ARB_MST_CHOISE_PUSH_OFST_18 0xE48AEC
+
+#define mmTPC1_QM_ARB_MST_CHOISE_PUSH_OFST_19 0xE48AF0
+
+#define mmTPC1_QM_ARB_MST_CHOISE_PUSH_OFST_20 0xE48AF4
+
+#define mmTPC1_QM_ARB_MST_CHOISE_PUSH_OFST_21 0xE48AF8
+
+#define mmTPC1_QM_ARB_MST_CHOISE_PUSH_OFST_22 0xE48AFC
+
+#define mmTPC1_QM_ARB_MST_CHOISE_PUSH_OFST_23 0xE48B00
+
+#define mmTPC1_QM_ARB_MST_CHOISE_PUSH_OFST_24 0xE48B04
+
+#define mmTPC1_QM_ARB_MST_CHOISE_PUSH_OFST_25 0xE48B08
+
+#define mmTPC1_QM_ARB_MST_CHOISE_PUSH_OFST_26 0xE48B0C
+
+#define mmTPC1_QM_ARB_MST_CHOISE_PUSH_OFST_27 0xE48B10
+
+#define mmTPC1_QM_ARB_MST_CHOISE_PUSH_OFST_28 0xE48B14
+
+#define mmTPC1_QM_ARB_MST_CHOISE_PUSH_OFST_29 0xE48B18
+
+#define mmTPC1_QM_ARB_MST_CHOISE_PUSH_OFST_30 0xE48B1C
+
+#define mmTPC1_QM_ARB_MST_CHOISE_PUSH_OFST_31 0xE48B20
+
+#define mmTPC1_QM_ARB_SLV_MASTER_INC_CRED_OFST 0xE48B28
+
+#define mmTPC1_QM_ARB_MST_SLAVE_EN 0xE48B2C
+
+#define mmTPC1_QM_ARB_MST_QUIET_PER 0xE48B34
+
+#define mmTPC1_QM_ARB_SLV_CHOISE_WDT 0xE48B38
+
+#define mmTPC1_QM_ARB_SLV_ID 0xE48B3C
+
+#define mmTPC1_QM_ARB_MSG_MAX_INFLIGHT 0xE48B44
+
+#define mmTPC1_QM_ARB_MSG_AWUSER_31_11 0xE48B48
+
+#define mmTPC1_QM_ARB_MSG_AWUSER_SEC_PROP 0xE48B4C
+
+#define mmTPC1_QM_ARB_MSG_AWUSER_NON_SEC_PROP 0xE48B50
+
+#define mmTPC1_QM_ARB_BASE_LO 0xE48B54
+
+#define mmTPC1_QM_ARB_BASE_HI 0xE48B58
+
+#define mmTPC1_QM_ARB_STATE_STS 0xE48B80
+
+#define mmTPC1_QM_ARB_CHOISE_FULLNESS_STS 0xE48B84
+
+#define mmTPC1_QM_ARB_MSG_STS 0xE48B88
+
+#define mmTPC1_QM_ARB_SLV_CHOISE_Q_HEAD 0xE48B8C
+
+#define mmTPC1_QM_ARB_ERR_CAUSE 0xE48B9C
+
+#define mmTPC1_QM_ARB_ERR_MSG_EN 0xE48BA0
+
+#define mmTPC1_QM_ARB_ERR_STS_DRP 0xE48BA8
+
+#define mmTPC1_QM_ARB_MST_CRED_STS_0 0xE48BB0
+
+#define mmTPC1_QM_ARB_MST_CRED_STS_1 0xE48BB4
+
+#define mmTPC1_QM_ARB_MST_CRED_STS_2 0xE48BB8
+
+#define mmTPC1_QM_ARB_MST_CRED_STS_3 0xE48BBC
+
+#define mmTPC1_QM_ARB_MST_CRED_STS_4 0xE48BC0
+
+#define mmTPC1_QM_ARB_MST_CRED_STS_5 0xE48BC4
+
+#define mmTPC1_QM_ARB_MST_CRED_STS_6 0xE48BC8
+
+#define mmTPC1_QM_ARB_MST_CRED_STS_7 0xE48BCC
+
+#define mmTPC1_QM_ARB_MST_CRED_STS_8 0xE48BD0
+
+#define mmTPC1_QM_ARB_MST_CRED_STS_9 0xE48BD4
+
+#define mmTPC1_QM_ARB_MST_CRED_STS_10 0xE48BD8
+
+#define mmTPC1_QM_ARB_MST_CRED_STS_11 0xE48BDC
+
+#define mmTPC1_QM_ARB_MST_CRED_STS_12 0xE48BE0
+
+#define mmTPC1_QM_ARB_MST_CRED_STS_13 0xE48BE4
+
+#define mmTPC1_QM_ARB_MST_CRED_STS_14 0xE48BE8
+
+#define mmTPC1_QM_ARB_MST_CRED_STS_15 0xE48BEC
+
+#define mmTPC1_QM_ARB_MST_CRED_STS_16 0xE48BF0
+
+#define mmTPC1_QM_ARB_MST_CRED_STS_17 0xE48BF4
+
+#define mmTPC1_QM_ARB_MST_CRED_STS_18 0xE48BF8
+
+#define mmTPC1_QM_ARB_MST_CRED_STS_19 0xE48BFC
+
+#define mmTPC1_QM_ARB_MST_CRED_STS_20 0xE48C00
+
+#define mmTPC1_QM_ARB_MST_CRED_STS_21 0xE48C04
+
+#define mmTPC1_QM_ARB_MST_CRED_STS_22 0xE48C08
+
+#define mmTPC1_QM_ARB_MST_CRED_STS_23 0xE48C0C
+
+#define mmTPC1_QM_ARB_MST_CRED_STS_24 0xE48C10
+
+#define mmTPC1_QM_ARB_MST_CRED_STS_25 0xE48C14
+
+#define mmTPC1_QM_ARB_MST_CRED_STS_26 0xE48C18
+
+#define mmTPC1_QM_ARB_MST_CRED_STS_27 0xE48C1C
+
+#define mmTPC1_QM_ARB_MST_CRED_STS_28 0xE48C20
+
+#define mmTPC1_QM_ARB_MST_CRED_STS_29 0xE48C24
+
+#define mmTPC1_QM_ARB_MST_CRED_STS_30 0xE48C28
+
+#define mmTPC1_QM_ARB_MST_CRED_STS_31 0xE48C2C
+
+#define mmTPC1_QM_CGM_CFG 0xE48C70
+
+#define mmTPC1_QM_CGM_STS 0xE48C74
+
+#define mmTPC1_QM_CGM_CFG1 0xE48C78
+
+#define mmTPC1_QM_LOCAL_RANGE_BASE 0xE48C80
+
+#define mmTPC1_QM_LOCAL_RANGE_SIZE 0xE48C84
+
+#define mmTPC1_QM_CSMR_STRICT_PRIO_CFG 0xE48C90
+
+#define mmTPC1_QM_HBW_RD_RATE_LIM_CFG_1 0xE48C94
+
+#define mmTPC1_QM_LBW_WR_RATE_LIM_CFG_0 0xE48C98
+
+#define mmTPC1_QM_LBW_WR_RATE_LIM_CFG_1 0xE48C9C
+
+#define mmTPC1_QM_HBW_RD_RATE_LIM_CFG_0 0xE48CA0
+
+#define mmTPC1_QM_GLBL_AXCACHE 0xE48CA4
+
+#define mmTPC1_QM_IND_GW_APB_CFG 0xE48CB0
+
+#define mmTPC1_QM_IND_GW_APB_WDATA 0xE48CB4
+
+#define mmTPC1_QM_IND_GW_APB_RDATA 0xE48CB8
+
+#define mmTPC1_QM_IND_GW_APB_STATUS 0xE48CBC
+
+#define mmTPC1_QM_GLBL_ERR_ADDR_LO 0xE48CD0
+
+#define mmTPC1_QM_GLBL_ERR_ADDR_HI 0xE48CD4
+
+#define mmTPC1_QM_GLBL_ERR_WDATA 0xE48CD8
+
+#define mmTPC1_QM_GLBL_MEM_INIT_BUSY 0xE48D00
+
+#endif /* ASIC_REG_TPC1_QM_REGS_H_ */
diff --git a/drivers/accel/habanalabs/include/gaudi/asic_reg/tpc2_cfg_regs.h b/drivers/accel/habanalabs/include/gaudi/asic_reg/tpc2_cfg_regs.h
new file mode 100644
index 0000000000..3e77c37952
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi/asic_reg/tpc2_cfg_regs.h
@@ -0,0 +1,1226 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2016-2018 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ ** DO NOT EDIT BELOW **
+ ************************************/
+
+#ifndef ASIC_REG_TPC2_CFG_REGS_H_
+#define ASIC_REG_TPC2_CFG_REGS_H_
+
+/*
+ *****************************************
+ * TPC2_CFG (Prototype: TPC)
+ *****************************************
+ */
+
+#define mmTPC2_CFG_KERNEL_TENSOR_0_BASE_ADDR_LOW 0xE86400
+
+#define mmTPC2_CFG_KERNEL_TENSOR_0_BASE_ADDR_HIGH 0xE86404
+
+#define mmTPC2_CFG_KERNEL_TENSOR_0_PADDING_VALUE 0xE86408
+
+#define mmTPC2_CFG_KERNEL_TENSOR_0_TENSOR_CONFIG 0xE8640C
+
+#define mmTPC2_CFG_KERNEL_TENSOR_0_DIM_0_SIZE 0xE86410
+
+#define mmTPC2_CFG_KERNEL_TENSOR_0_DIM_0_STRIDE 0xE86414
+
+#define mmTPC2_CFG_KERNEL_TENSOR_0_DIM_1_SIZE 0xE86418
+
+#define mmTPC2_CFG_KERNEL_TENSOR_0_DIM_1_STRIDE 0xE8641C
+
+#define mmTPC2_CFG_KERNEL_TENSOR_0_DIM_2_SIZE 0xE86420
+
+#define mmTPC2_CFG_KERNEL_TENSOR_0_DIM_2_STRIDE 0xE86424
+
+#define mmTPC2_CFG_KERNEL_TENSOR_0_DIM_3_SIZE 0xE86428
+
+#define mmTPC2_CFG_KERNEL_TENSOR_0_DIM_3_STRIDE 0xE8642C
+
+#define mmTPC2_CFG_KERNEL_TENSOR_0_DIM_4_SIZE 0xE86430
+
+#define mmTPC2_CFG_KERNEL_TENSOR_0_DIM_4_STRIDE 0xE86434
+
+#define mmTPC2_CFG_KERNEL_TENSOR_1_BASE_ADDR_LOW 0xE86438
+
+#define mmTPC2_CFG_KERNEL_TENSOR_1_BASE_ADDR_HIGH 0xE8643C
+
+#define mmTPC2_CFG_KERNEL_TENSOR_1_PADDING_VALUE 0xE86440
+
+#define mmTPC2_CFG_KERNEL_TENSOR_1_TENSOR_CONFIG 0xE86444
+
+#define mmTPC2_CFG_KERNEL_TENSOR_1_DIM_0_SIZE 0xE86448
+
+#define mmTPC2_CFG_KERNEL_TENSOR_1_DIM_0_STRIDE 0xE8644C
+
+#define mmTPC2_CFG_KERNEL_TENSOR_1_DIM_1_SIZE 0xE86450
+
+#define mmTPC2_CFG_KERNEL_TENSOR_1_DIM_1_STRIDE 0xE86454
+
+#define mmTPC2_CFG_KERNEL_TENSOR_1_DIM_2_SIZE 0xE86458
+
+#define mmTPC2_CFG_KERNEL_TENSOR_1_DIM_2_STRIDE 0xE8645C
+
+#define mmTPC2_CFG_KERNEL_TENSOR_1_DIM_3_SIZE 0xE86460
+
+#define mmTPC2_CFG_KERNEL_TENSOR_1_DIM_3_STRIDE 0xE86464
+
+#define mmTPC2_CFG_KERNEL_TENSOR_1_DIM_4_SIZE 0xE86468
+
+#define mmTPC2_CFG_KERNEL_TENSOR_1_DIM_4_STRIDE 0xE8646C
+
+#define mmTPC2_CFG_KERNEL_TENSOR_2_BASE_ADDR_LOW 0xE86470
+
+#define mmTPC2_CFG_KERNEL_TENSOR_2_BASE_ADDR_HIGH 0xE86474
+
+#define mmTPC2_CFG_KERNEL_TENSOR_2_PADDING_VALUE 0xE86478
+
+#define mmTPC2_CFG_KERNEL_TENSOR_2_TENSOR_CONFIG 0xE8647C
+
+#define mmTPC2_CFG_KERNEL_TENSOR_2_DIM_0_SIZE 0xE86480
+
+#define mmTPC2_CFG_KERNEL_TENSOR_2_DIM_0_STRIDE 0xE86484
+
+#define mmTPC2_CFG_KERNEL_TENSOR_2_DIM_1_SIZE 0xE86488
+
+#define mmTPC2_CFG_KERNEL_TENSOR_2_DIM_1_STRIDE 0xE8648C
+
+#define mmTPC2_CFG_KERNEL_TENSOR_2_DIM_2_SIZE 0xE86490
+
+#define mmTPC2_CFG_KERNEL_TENSOR_2_DIM_2_STRIDE 0xE86494
+
+#define mmTPC2_CFG_KERNEL_TENSOR_2_DIM_3_SIZE 0xE86498
+
+#define mmTPC2_CFG_KERNEL_TENSOR_2_DIM_3_STRIDE 0xE8649C
+
+#define mmTPC2_CFG_KERNEL_TENSOR_2_DIM_4_SIZE 0xE864A0
+
+#define mmTPC2_CFG_KERNEL_TENSOR_2_DIM_4_STRIDE 0xE864A4
+
+#define mmTPC2_CFG_KERNEL_TENSOR_3_BASE_ADDR_LOW 0xE864A8
+
+#define mmTPC2_CFG_KERNEL_TENSOR_3_BASE_ADDR_HIGH 0xE864AC
+
+#define mmTPC2_CFG_KERNEL_TENSOR_3_PADDING_VALUE 0xE864B0
+
+#define mmTPC2_CFG_KERNEL_TENSOR_3_TENSOR_CONFIG 0xE864B4
+
+#define mmTPC2_CFG_KERNEL_TENSOR_3_DIM_0_SIZE 0xE864B8
+
+#define mmTPC2_CFG_KERNEL_TENSOR_3_DIM_0_STRIDE 0xE864BC
+
+#define mmTPC2_CFG_KERNEL_TENSOR_3_DIM_1_SIZE 0xE864C0
+
+#define mmTPC2_CFG_KERNEL_TENSOR_3_DIM_1_STRIDE 0xE864C4
+
+#define mmTPC2_CFG_KERNEL_TENSOR_3_DIM_2_SIZE 0xE864C8
+
+#define mmTPC2_CFG_KERNEL_TENSOR_3_DIM_2_STRIDE 0xE864CC
+
+#define mmTPC2_CFG_KERNEL_TENSOR_3_DIM_3_SIZE 0xE864D0
+
+#define mmTPC2_CFG_KERNEL_TENSOR_3_DIM_3_STRIDE 0xE864D4
+
+#define mmTPC2_CFG_KERNEL_TENSOR_3_DIM_4_SIZE 0xE864D8
+
+#define mmTPC2_CFG_KERNEL_TENSOR_3_DIM_4_STRIDE 0xE864DC
+
+#define mmTPC2_CFG_KERNEL_TENSOR_4_BASE_ADDR_LOW 0xE864E0
+
+#define mmTPC2_CFG_KERNEL_TENSOR_4_BASE_ADDR_HIGH 0xE864E4
+
+#define mmTPC2_CFG_KERNEL_TENSOR_4_PADDING_VALUE 0xE864E8
+
+#define mmTPC2_CFG_KERNEL_TENSOR_4_TENSOR_CONFIG 0xE864EC
+
+#define mmTPC2_CFG_KERNEL_TENSOR_4_DIM_0_SIZE 0xE864F0
+
+#define mmTPC2_CFG_KERNEL_TENSOR_4_DIM_0_STRIDE 0xE864F4
+
+#define mmTPC2_CFG_KERNEL_TENSOR_4_DIM_1_SIZE 0xE864F8
+
+#define mmTPC2_CFG_KERNEL_TENSOR_4_DIM_1_STRIDE 0xE864FC
+
+#define mmTPC2_CFG_KERNEL_TENSOR_4_DIM_2_SIZE 0xE86500
+
+#define mmTPC2_CFG_KERNEL_TENSOR_4_DIM_2_STRIDE 0xE86504
+
+#define mmTPC2_CFG_KERNEL_TENSOR_4_DIM_3_SIZE 0xE86508
+
+#define mmTPC2_CFG_KERNEL_TENSOR_4_DIM_3_STRIDE 0xE8650C
+
+#define mmTPC2_CFG_KERNEL_TENSOR_4_DIM_4_SIZE 0xE86510
+
+#define mmTPC2_CFG_KERNEL_TENSOR_4_DIM_4_STRIDE 0xE86514
+
+#define mmTPC2_CFG_KERNEL_TENSOR_5_BASE_ADDR_LOW 0xE86518
+
+#define mmTPC2_CFG_KERNEL_TENSOR_5_BASE_ADDR_HIGH 0xE8651C
+
+#define mmTPC2_CFG_KERNEL_TENSOR_5_PADDING_VALUE 0xE86520
+
+#define mmTPC2_CFG_KERNEL_TENSOR_5_TENSOR_CONFIG 0xE86524
+
+#define mmTPC2_CFG_KERNEL_TENSOR_5_DIM_0_SIZE 0xE86528
+
+#define mmTPC2_CFG_KERNEL_TENSOR_5_DIM_0_STRIDE 0xE8652C
+
+#define mmTPC2_CFG_KERNEL_TENSOR_5_DIM_1_SIZE 0xE86530
+
+#define mmTPC2_CFG_KERNEL_TENSOR_5_DIM_1_STRIDE 0xE86534
+
+#define mmTPC2_CFG_KERNEL_TENSOR_5_DIM_2_SIZE 0xE86538
+
+#define mmTPC2_CFG_KERNEL_TENSOR_5_DIM_2_STRIDE 0xE8653C
+
+#define mmTPC2_CFG_KERNEL_TENSOR_5_DIM_3_SIZE 0xE86540
+
+#define mmTPC2_CFG_KERNEL_TENSOR_5_DIM_3_STRIDE 0xE86544
+
+#define mmTPC2_CFG_KERNEL_TENSOR_5_DIM_4_SIZE 0xE86548
+
+#define mmTPC2_CFG_KERNEL_TENSOR_5_DIM_4_STRIDE 0xE8654C
+
+#define mmTPC2_CFG_KERNEL_TENSOR_6_BASE_ADDR_LOW 0xE86550
+
+#define mmTPC2_CFG_KERNEL_TENSOR_6_BASE_ADDR_HIGH 0xE86554
+
+#define mmTPC2_CFG_KERNEL_TENSOR_6_PADDING_VALUE 0xE86558
+
+#define mmTPC2_CFG_KERNEL_TENSOR_6_TENSOR_CONFIG 0xE8655C
+
+#define mmTPC2_CFG_KERNEL_TENSOR_6_DIM_0_SIZE 0xE86560
+
+#define mmTPC2_CFG_KERNEL_TENSOR_6_DIM_0_STRIDE 0xE86564
+
+#define mmTPC2_CFG_KERNEL_TENSOR_6_DIM_1_SIZE 0xE86568
+
+#define mmTPC2_CFG_KERNEL_TENSOR_6_DIM_1_STRIDE 0xE8656C
+
+#define mmTPC2_CFG_KERNEL_TENSOR_6_DIM_2_SIZE 0xE86570
+
+#define mmTPC2_CFG_KERNEL_TENSOR_6_DIM_2_STRIDE 0xE86574
+
+#define mmTPC2_CFG_KERNEL_TENSOR_6_DIM_3_SIZE 0xE86578
+
+#define mmTPC2_CFG_KERNEL_TENSOR_6_DIM_3_STRIDE 0xE8657C
+
+#define mmTPC2_CFG_KERNEL_TENSOR_6_DIM_4_SIZE 0xE86580
+
+#define mmTPC2_CFG_KERNEL_TENSOR_6_DIM_4_STRIDE 0xE86584
+
+#define mmTPC2_CFG_KERNEL_TENSOR_7_BASE_ADDR_LOW 0xE86588
+
+#define mmTPC2_CFG_KERNEL_TENSOR_7_BASE_ADDR_HIGH 0xE8658C
+
+#define mmTPC2_CFG_KERNEL_TENSOR_7_PADDING_VALUE 0xE86590
+
+#define mmTPC2_CFG_KERNEL_TENSOR_7_TENSOR_CONFIG 0xE86594
+
+#define mmTPC2_CFG_KERNEL_TENSOR_7_DIM_0_SIZE 0xE86598
+
+#define mmTPC2_CFG_KERNEL_TENSOR_7_DIM_0_STRIDE 0xE8659C
+
+#define mmTPC2_CFG_KERNEL_TENSOR_7_DIM_1_SIZE 0xE865A0
+
+#define mmTPC2_CFG_KERNEL_TENSOR_7_DIM_1_STRIDE 0xE865A4
+
+#define mmTPC2_CFG_KERNEL_TENSOR_7_DIM_2_SIZE 0xE865A8
+
+#define mmTPC2_CFG_KERNEL_TENSOR_7_DIM_2_STRIDE 0xE865AC
+
+#define mmTPC2_CFG_KERNEL_TENSOR_7_DIM_3_SIZE 0xE865B0
+
+#define mmTPC2_CFG_KERNEL_TENSOR_7_DIM_3_STRIDE 0xE865B4
+
+#define mmTPC2_CFG_KERNEL_TENSOR_7_DIM_4_SIZE 0xE865B8
+
+#define mmTPC2_CFG_KERNEL_TENSOR_7_DIM_4_STRIDE 0xE865BC
+
+#define mmTPC2_CFG_KERNEL_TENSOR_8_BASE_ADDR_LOW 0xE865C0
+
+#define mmTPC2_CFG_KERNEL_TENSOR_8_BASE_ADDR_HIGH 0xE865C4
+
+#define mmTPC2_CFG_KERNEL_TENSOR_8_PADDING_VALUE 0xE865C8
+
+#define mmTPC2_CFG_KERNEL_TENSOR_8_TENSOR_CONFIG 0xE865CC
+
+#define mmTPC2_CFG_KERNEL_TENSOR_8_DIM_0_SIZE 0xE865D0
+
+#define mmTPC2_CFG_KERNEL_TENSOR_8_DIM_0_STRIDE 0xE865D4
+
+#define mmTPC2_CFG_KERNEL_TENSOR_8_DIM_1_SIZE 0xE865D8
+
+#define mmTPC2_CFG_KERNEL_TENSOR_8_DIM_1_STRIDE 0xE865DC
+
+#define mmTPC2_CFG_KERNEL_TENSOR_8_DIM_2_SIZE 0xE865E0
+
+#define mmTPC2_CFG_KERNEL_TENSOR_8_DIM_2_STRIDE 0xE865E4
+
+#define mmTPC2_CFG_KERNEL_TENSOR_8_DIM_3_SIZE 0xE865E8
+
+#define mmTPC2_CFG_KERNEL_TENSOR_8_DIM_3_STRIDE 0xE865EC
+
+#define mmTPC2_CFG_KERNEL_TENSOR_8_DIM_4_SIZE 0xE865F0
+
+#define mmTPC2_CFG_KERNEL_TENSOR_8_DIM_4_STRIDE 0xE865F4
+
+#define mmTPC2_CFG_KERNEL_TENSOR_9_BASE_ADDR_LOW 0xE865F8
+
+#define mmTPC2_CFG_KERNEL_TENSOR_9_BASE_ADDR_HIGH 0xE865FC
+
+#define mmTPC2_CFG_KERNEL_TENSOR_9_PADDING_VALUE 0xE86600
+
+#define mmTPC2_CFG_KERNEL_TENSOR_9_TENSOR_CONFIG 0xE86604
+
+#define mmTPC2_CFG_KERNEL_TENSOR_9_DIM_0_SIZE 0xE86608
+
+#define mmTPC2_CFG_KERNEL_TENSOR_9_DIM_0_STRIDE 0xE8660C
+
+#define mmTPC2_CFG_KERNEL_TENSOR_9_DIM_1_SIZE 0xE86610
+
+#define mmTPC2_CFG_KERNEL_TENSOR_9_DIM_1_STRIDE 0xE86614
+
+#define mmTPC2_CFG_KERNEL_TENSOR_9_DIM_2_SIZE 0xE86618
+
+#define mmTPC2_CFG_KERNEL_TENSOR_9_DIM_2_STRIDE 0xE8661C
+
+#define mmTPC2_CFG_KERNEL_TENSOR_9_DIM_3_SIZE 0xE86620
+
+#define mmTPC2_CFG_KERNEL_TENSOR_9_DIM_3_STRIDE 0xE86624
+
+#define mmTPC2_CFG_KERNEL_TENSOR_9_DIM_4_SIZE 0xE86628
+
+#define mmTPC2_CFG_KERNEL_TENSOR_9_DIM_4_STRIDE 0xE8662C
+
+#define mmTPC2_CFG_KERNEL_TENSOR_10_BASE_ADDR_LOW 0xE86630
+
+#define mmTPC2_CFG_KERNEL_TENSOR_10_BASE_ADDR_HIGH 0xE86634
+
+#define mmTPC2_CFG_KERNEL_TENSOR_10_PADDING_VALUE 0xE86638
+
+#define mmTPC2_CFG_KERNEL_TENSOR_10_TENSOR_CONFIG 0xE8663C
+
+#define mmTPC2_CFG_KERNEL_TENSOR_10_DIM_0_SIZE 0xE86640
+
+#define mmTPC2_CFG_KERNEL_TENSOR_10_DIM_0_STRIDE 0xE86644
+
+#define mmTPC2_CFG_KERNEL_TENSOR_10_DIM_1_SIZE 0xE86648
+
+#define mmTPC2_CFG_KERNEL_TENSOR_10_DIM_1_STRIDE 0xE8664C
+
+#define mmTPC2_CFG_KERNEL_TENSOR_10_DIM_2_SIZE 0xE86650
+
+#define mmTPC2_CFG_KERNEL_TENSOR_10_DIM_2_STRIDE 0xE86654
+
+#define mmTPC2_CFG_KERNEL_TENSOR_10_DIM_3_SIZE 0xE86658
+
+#define mmTPC2_CFG_KERNEL_TENSOR_10_DIM_3_STRIDE 0xE8665C
+
+#define mmTPC2_CFG_KERNEL_TENSOR_10_DIM_4_SIZE 0xE86660
+
+#define mmTPC2_CFG_KERNEL_TENSOR_10_DIM_4_STRIDE 0xE86664
+
+#define mmTPC2_CFG_KERNEL_TENSOR_11_BASE_ADDR_LOW 0xE86668
+
+#define mmTPC2_CFG_KERNEL_TENSOR_11_BASE_ADDR_HIGH 0xE8666C
+
+#define mmTPC2_CFG_KERNEL_TENSOR_11_PADDING_VALUE 0xE86670
+
+#define mmTPC2_CFG_KERNEL_TENSOR_11_TENSOR_CONFIG 0xE86674
+
+#define mmTPC2_CFG_KERNEL_TENSOR_11_DIM_0_SIZE 0xE86678
+
+#define mmTPC2_CFG_KERNEL_TENSOR_11_DIM_0_STRIDE 0xE8667C
+
+#define mmTPC2_CFG_KERNEL_TENSOR_11_DIM_1_SIZE 0xE86680
+
+#define mmTPC2_CFG_KERNEL_TENSOR_11_DIM_1_STRIDE 0xE86684
+
+#define mmTPC2_CFG_KERNEL_TENSOR_11_DIM_2_SIZE 0xE86688
+
+#define mmTPC2_CFG_KERNEL_TENSOR_11_DIM_2_STRIDE 0xE8668C
+
+#define mmTPC2_CFG_KERNEL_TENSOR_11_DIM_3_SIZE 0xE86690
+
+#define mmTPC2_CFG_KERNEL_TENSOR_11_DIM_3_STRIDE 0xE86694
+
+#define mmTPC2_CFG_KERNEL_TENSOR_11_DIM_4_SIZE 0xE86698
+
+#define mmTPC2_CFG_KERNEL_TENSOR_11_DIM_4_STRIDE 0xE8669C
+
+#define mmTPC2_CFG_KERNEL_TENSOR_12_BASE_ADDR_LOW 0xE866A0
+
+#define mmTPC2_CFG_KERNEL_TENSOR_12_BASE_ADDR_HIGH 0xE866A4
+
+#define mmTPC2_CFG_KERNEL_TENSOR_12_PADDING_VALUE 0xE866A8
+
+#define mmTPC2_CFG_KERNEL_TENSOR_12_TENSOR_CONFIG 0xE866AC
+
+#define mmTPC2_CFG_KERNEL_TENSOR_12_DIM_0_SIZE 0xE866B0
+
+#define mmTPC2_CFG_KERNEL_TENSOR_12_DIM_0_STRIDE 0xE866B4
+
+#define mmTPC2_CFG_KERNEL_TENSOR_12_DIM_1_SIZE 0xE866B8
+
+#define mmTPC2_CFG_KERNEL_TENSOR_12_DIM_1_STRIDE 0xE866BC
+
+#define mmTPC2_CFG_KERNEL_TENSOR_12_DIM_2_SIZE 0xE866C0
+
+#define mmTPC2_CFG_KERNEL_TENSOR_12_DIM_2_STRIDE 0xE866C4
+
+#define mmTPC2_CFG_KERNEL_TENSOR_12_DIM_3_SIZE 0xE866C8
+
+#define mmTPC2_CFG_KERNEL_TENSOR_12_DIM_3_STRIDE 0xE866CC
+
+#define mmTPC2_CFG_KERNEL_TENSOR_12_DIM_4_SIZE 0xE866D0
+
+#define mmTPC2_CFG_KERNEL_TENSOR_12_DIM_4_STRIDE 0xE866D4
+
+#define mmTPC2_CFG_KERNEL_TENSOR_13_BASE_ADDR_LOW 0xE866D8
+
+#define mmTPC2_CFG_KERNEL_TENSOR_13_BASE_ADDR_HIGH 0xE866DC
+
+#define mmTPC2_CFG_KERNEL_TENSOR_13_PADDING_VALUE 0xE866E0
+
+#define mmTPC2_CFG_KERNEL_TENSOR_13_TENSOR_CONFIG 0xE866E4
+
+#define mmTPC2_CFG_KERNEL_TENSOR_13_DIM_0_SIZE 0xE866E8
+
+#define mmTPC2_CFG_KERNEL_TENSOR_13_DIM_0_STRIDE 0xE866EC
+
+#define mmTPC2_CFG_KERNEL_TENSOR_13_DIM_1_SIZE 0xE866F0
+
+#define mmTPC2_CFG_KERNEL_TENSOR_13_DIM_1_STRIDE 0xE866F4
+
+#define mmTPC2_CFG_KERNEL_TENSOR_13_DIM_2_SIZE 0xE866F8
+
+#define mmTPC2_CFG_KERNEL_TENSOR_13_DIM_2_STRIDE 0xE866FC
+
+#define mmTPC2_CFG_KERNEL_TENSOR_13_DIM_3_SIZE 0xE86700
+
+#define mmTPC2_CFG_KERNEL_TENSOR_13_DIM_3_STRIDE 0xE86704
+
+#define mmTPC2_CFG_KERNEL_TENSOR_13_DIM_4_SIZE 0xE86708
+
+#define mmTPC2_CFG_KERNEL_TENSOR_13_DIM_4_STRIDE 0xE8670C
+
+#define mmTPC2_CFG_KERNEL_TENSOR_14_BASE_ADDR_LOW 0xE86710
+
+#define mmTPC2_CFG_KERNEL_TENSOR_14_BASE_ADDR_HIGH 0xE86714
+
+#define mmTPC2_CFG_KERNEL_TENSOR_14_PADDING_VALUE 0xE86718
+
+#define mmTPC2_CFG_KERNEL_TENSOR_14_TENSOR_CONFIG 0xE8671C
+
+#define mmTPC2_CFG_KERNEL_TENSOR_14_DIM_0_SIZE 0xE86720
+
+#define mmTPC2_CFG_KERNEL_TENSOR_14_DIM_0_STRIDE 0xE86724
+
+#define mmTPC2_CFG_KERNEL_TENSOR_14_DIM_1_SIZE 0xE86728
+
+#define mmTPC2_CFG_KERNEL_TENSOR_14_DIM_1_STRIDE 0xE8672C
+
+#define mmTPC2_CFG_KERNEL_TENSOR_14_DIM_2_SIZE 0xE86730
+
+#define mmTPC2_CFG_KERNEL_TENSOR_14_DIM_2_STRIDE 0xE86734
+
+#define mmTPC2_CFG_KERNEL_TENSOR_14_DIM_3_SIZE 0xE86738
+
+#define mmTPC2_CFG_KERNEL_TENSOR_14_DIM_3_STRIDE 0xE8673C
+
+#define mmTPC2_CFG_KERNEL_TENSOR_14_DIM_4_SIZE 0xE86740
+
+#define mmTPC2_CFG_KERNEL_TENSOR_14_DIM_4_STRIDE 0xE86744
+
+#define mmTPC2_CFG_KERNEL_TENSOR_15_BASE_ADDR_LOW 0xE86748
+
+#define mmTPC2_CFG_KERNEL_TENSOR_15_BASE_ADDR_HIGH 0xE8674C
+
+#define mmTPC2_CFG_KERNEL_TENSOR_15_PADDING_VALUE 0xE86750
+
+#define mmTPC2_CFG_KERNEL_TENSOR_15_TENSOR_CONFIG 0xE86754
+
+#define mmTPC2_CFG_KERNEL_TENSOR_15_DIM_0_SIZE 0xE86758
+
+#define mmTPC2_CFG_KERNEL_TENSOR_15_DIM_0_STRIDE 0xE8675C
+
+#define mmTPC2_CFG_KERNEL_TENSOR_15_DIM_1_SIZE 0xE86760
+
+#define mmTPC2_CFG_KERNEL_TENSOR_15_DIM_1_STRIDE 0xE86764
+
+#define mmTPC2_CFG_KERNEL_TENSOR_15_DIM_2_SIZE 0xE86768
+
+#define mmTPC2_CFG_KERNEL_TENSOR_15_DIM_2_STRIDE 0xE8676C
+
+#define mmTPC2_CFG_KERNEL_TENSOR_15_DIM_3_SIZE 0xE86770
+
+#define mmTPC2_CFG_KERNEL_TENSOR_15_DIM_3_STRIDE 0xE86774
+
+#define mmTPC2_CFG_KERNEL_TENSOR_15_DIM_4_SIZE 0xE86778
+
+#define mmTPC2_CFG_KERNEL_TENSOR_15_DIM_4_STRIDE 0xE8677C
+
+#define mmTPC2_CFG_KERNEL_SYNC_OBJECT_MESSAGE 0xE86780
+
+#define mmTPC2_CFG_KERNEL_SYNC_OBJECT_ADDR 0xE86784
+
+#define mmTPC2_CFG_KERNEL_KERNEL_BASE_ADDRESS_LOW 0xE86788
+
+#define mmTPC2_CFG_KERNEL_KERNEL_BASE_ADDRESS_HIGH 0xE8678C
+
+#define mmTPC2_CFG_KERNEL_TID_BASE_DIM_0 0xE86790
+
+#define mmTPC2_CFG_KERNEL_TID_SIZE_DIM_0 0xE86794
+
+#define mmTPC2_CFG_KERNEL_TID_BASE_DIM_1 0xE86798
+
+#define mmTPC2_CFG_KERNEL_TID_SIZE_DIM_1 0xE8679C
+
+#define mmTPC2_CFG_KERNEL_TID_BASE_DIM_2 0xE867A0
+
+#define mmTPC2_CFG_KERNEL_TID_SIZE_DIM_2 0xE867A4
+
+#define mmTPC2_CFG_KERNEL_TID_BASE_DIM_3 0xE867A8
+
+#define mmTPC2_CFG_KERNEL_TID_SIZE_DIM_3 0xE867AC
+
+#define mmTPC2_CFG_KERNEL_TID_BASE_DIM_4 0xE867B0
+
+#define mmTPC2_CFG_KERNEL_TID_SIZE_DIM_4 0xE867B4
+
+#define mmTPC2_CFG_KERNEL_KERNEL_CONFIG 0xE867B8
+
+#define mmTPC2_CFG_KERNEL_KERNEL_ID 0xE867BC
+
+#define mmTPC2_CFG_KERNEL_SRF_0 0xE867C0
+
+#define mmTPC2_CFG_KERNEL_SRF_1 0xE867C4
+
+#define mmTPC2_CFG_KERNEL_SRF_2 0xE867C8
+
+#define mmTPC2_CFG_KERNEL_SRF_3 0xE867CC
+
+#define mmTPC2_CFG_KERNEL_SRF_4 0xE867D0
+
+#define mmTPC2_CFG_KERNEL_SRF_5 0xE867D4
+
+#define mmTPC2_CFG_KERNEL_SRF_6 0xE867D8
+
+#define mmTPC2_CFG_KERNEL_SRF_7 0xE867DC
+
+#define mmTPC2_CFG_KERNEL_SRF_8 0xE867E0
+
+#define mmTPC2_CFG_KERNEL_SRF_9 0xE867E4
+
+#define mmTPC2_CFG_KERNEL_SRF_10 0xE867E8
+
+#define mmTPC2_CFG_KERNEL_SRF_11 0xE867EC
+
+#define mmTPC2_CFG_KERNEL_SRF_12 0xE867F0
+
+#define mmTPC2_CFG_KERNEL_SRF_13 0xE867F4
+
+#define mmTPC2_CFG_KERNEL_SRF_14 0xE867F8
+
+#define mmTPC2_CFG_KERNEL_SRF_15 0xE867FC
+
+#define mmTPC2_CFG_KERNEL_SRF_16 0xE86800
+
+#define mmTPC2_CFG_KERNEL_SRF_17 0xE86804
+
+#define mmTPC2_CFG_KERNEL_SRF_18 0xE86808
+
+#define mmTPC2_CFG_KERNEL_SRF_19 0xE8680C
+
+#define mmTPC2_CFG_KERNEL_SRF_20 0xE86810
+
+#define mmTPC2_CFG_KERNEL_SRF_21 0xE86814
+
+#define mmTPC2_CFG_KERNEL_SRF_22 0xE86818
+
+#define mmTPC2_CFG_KERNEL_SRF_23 0xE8681C
+
+#define mmTPC2_CFG_KERNEL_SRF_24 0xE86820
+
+#define mmTPC2_CFG_KERNEL_SRF_25 0xE86824
+
+#define mmTPC2_CFG_KERNEL_SRF_26 0xE86828
+
+#define mmTPC2_CFG_KERNEL_SRF_27 0xE8682C
+
+#define mmTPC2_CFG_KERNEL_SRF_28 0xE86830
+
+#define mmTPC2_CFG_KERNEL_SRF_29 0xE86834
+
+#define mmTPC2_CFG_KERNEL_SRF_30 0xE86838
+
+#define mmTPC2_CFG_KERNEL_SRF_31 0xE8683C
+
+#define mmTPC2_CFG_ROUND_CSR 0xE868FC
+
+#define mmTPC2_CFG_PROT 0xE86900
+
+#define mmTPC2_CFG_SEMAPHORE 0xE86908
+
+#define mmTPC2_CFG_VFLAGS 0xE8690C
+
+#define mmTPC2_CFG_SFLAGS 0xE86910
+
+#define mmTPC2_CFG_LFSR_POLYNOM 0xE86918
+
+#define mmTPC2_CFG_STATUS 0xE8691C
+
+#define mmTPC2_CFG_CFG_BASE_ADDRESS_HIGH 0xE86920
+
+#define mmTPC2_CFG_CFG_SUBTRACT_VALUE 0xE86924
+
+#define mmTPC2_CFG_SM_BASE_ADDRESS_HIGH 0xE8692C
+
+#define mmTPC2_CFG_TPC_CMD 0xE86930
+
+#define mmTPC2_CFG_TPC_EXECUTE 0xE86938
+
+#define mmTPC2_CFG_TPC_STALL 0xE8693C
+
+#define mmTPC2_CFG_ICACHE_BASE_ADDERESS_LOW 0xE86940
+
+#define mmTPC2_CFG_ICACHE_BASE_ADDERESS_HIGH 0xE86944
+
+#define mmTPC2_CFG_RD_RATE_LIMIT 0xE86948
+
+#define mmTPC2_CFG_WR_RATE_LIMIT 0xE86950
+
+#define mmTPC2_CFG_MSS_CONFIG 0xE86954
+
+#define mmTPC2_CFG_TPC_INTR_CAUSE 0xE86958
+
+#define mmTPC2_CFG_TPC_INTR_MASK 0xE8695C
+
+#define mmTPC2_CFG_WQ_CREDITS 0xE86960
+
+#define mmTPC2_CFG_ARUSER_LO 0xE86964
+
+#define mmTPC2_CFG_ARUSER_HI 0xE86968
+
+#define mmTPC2_CFG_AWUSER_LO 0xE8696C
+
+#define mmTPC2_CFG_AWUSER_HI 0xE86970
+
+#define mmTPC2_CFG_OPCODE_EXEC 0xE86974
+
+#define mmTPC2_CFG_LUT_FUNC32_BASE_ADDR_LO 0xE86978
+
+#define mmTPC2_CFG_LUT_FUNC32_BASE_ADDR_HI 0xE8697C
+
+#define mmTPC2_CFG_LUT_FUNC64_BASE_ADDR_LO 0xE86980
+
+#define mmTPC2_CFG_LUT_FUNC64_BASE_ADDR_HI 0xE86984
+
+#define mmTPC2_CFG_LUT_FUNC128_BASE_ADDR_LO 0xE86988
+
+#define mmTPC2_CFG_LUT_FUNC128_BASE_ADDR_HI 0xE8698C
+
+#define mmTPC2_CFG_LUT_FUNC256_BASE_ADDR_LO 0xE86990
+
+#define mmTPC2_CFG_LUT_FUNC256_BASE_ADDR_HI 0xE86994
+
+#define mmTPC2_CFG_TSB_CFG_MAX_SIZE 0xE86998
+
+#define mmTPC2_CFG_TSB_CFG 0xE8699C
+
+#define mmTPC2_CFG_DBGMEM_ADD 0xE869A0
+
+#define mmTPC2_CFG_DBGMEM_DATA_WR 0xE869A4
+
+#define mmTPC2_CFG_DBGMEM_DATA_RD 0xE869A8
+
+#define mmTPC2_CFG_DBGMEM_CTRL 0xE869AC
+
+#define mmTPC2_CFG_DBGMEM_RC 0xE869B0
+
+#define mmTPC2_CFG_TSB_INFLIGHT_CNTR 0xE869B4
+
+#define mmTPC2_CFG_WQ_INFLIGHT_CNTR 0xE869B8
+
+#define mmTPC2_CFG_WQ_LBW_TOTAL_CNTR 0xE869BC
+
+#define mmTPC2_CFG_WQ_HBW_TOTAL_CNTR 0xE869C0
+
+#define mmTPC2_CFG_IRQ_OCCOUPY_CNTR 0xE869C4
+
+#define mmTPC2_CFG_FUNC_MBIST_CNTRL 0xE869D0
+
+#define mmTPC2_CFG_FUNC_MBIST_PAT 0xE869D4
+
+#define mmTPC2_CFG_FUNC_MBIST_MEM_0 0xE869D8
+
+#define mmTPC2_CFG_FUNC_MBIST_MEM_1 0xE869DC
+
+#define mmTPC2_CFG_FUNC_MBIST_MEM_2 0xE869E0
+
+#define mmTPC2_CFG_FUNC_MBIST_MEM_3 0xE869E4
+
+#define mmTPC2_CFG_FUNC_MBIST_MEM_4 0xE869E8
+
+#define mmTPC2_CFG_FUNC_MBIST_MEM_5 0xE869EC
+
+#define mmTPC2_CFG_FUNC_MBIST_MEM_6 0xE869F0
+
+#define mmTPC2_CFG_FUNC_MBIST_MEM_7 0xE869F4
+
+#define mmTPC2_CFG_FUNC_MBIST_MEM_8 0xE869F8
+
+#define mmTPC2_CFG_FUNC_MBIST_MEM_9 0xE869FC
+
+#define mmTPC2_CFG_QM_TENSOR_0_BASE_ADDR_LOW 0xE86A00
+
+#define mmTPC2_CFG_QM_TENSOR_0_BASE_ADDR_HIGH 0xE86A04
+
+#define mmTPC2_CFG_QM_TENSOR_0_PADDING_VALUE 0xE86A08
+
+#define mmTPC2_CFG_QM_TENSOR_0_TENSOR_CONFIG 0xE86A0C
+
+#define mmTPC2_CFG_QM_TENSOR_0_DIM_0_SIZE 0xE86A10
+
+#define mmTPC2_CFG_QM_TENSOR_0_DIM_0_STRIDE 0xE86A14
+
+#define mmTPC2_CFG_QM_TENSOR_0_DIM_1_SIZE 0xE86A18
+
+#define mmTPC2_CFG_QM_TENSOR_0_DIM_1_STRIDE 0xE86A1C
+
+#define mmTPC2_CFG_QM_TENSOR_0_DIM_2_SIZE 0xE86A20
+
+#define mmTPC2_CFG_QM_TENSOR_0_DIM_2_STRIDE 0xE86A24
+
+#define mmTPC2_CFG_QM_TENSOR_0_DIM_3_SIZE 0xE86A28
+
+#define mmTPC2_CFG_QM_TENSOR_0_DIM_3_STRIDE 0xE86A2C
+
+#define mmTPC2_CFG_QM_TENSOR_0_DIM_4_SIZE 0xE86A30
+
+#define mmTPC2_CFG_QM_TENSOR_0_DIM_4_STRIDE 0xE86A34
+
+#define mmTPC2_CFG_QM_TENSOR_1_BASE_ADDR_LOW 0xE86A38
+
+#define mmTPC2_CFG_QM_TENSOR_1_BASE_ADDR_HIGH 0xE86A3C
+
+#define mmTPC2_CFG_QM_TENSOR_1_PADDING_VALUE 0xE86A40
+
+#define mmTPC2_CFG_QM_TENSOR_1_TENSOR_CONFIG 0xE86A44
+
+#define mmTPC2_CFG_QM_TENSOR_1_DIM_0_SIZE 0xE86A48
+
+#define mmTPC2_CFG_QM_TENSOR_1_DIM_0_STRIDE 0xE86A4C
+
+#define mmTPC2_CFG_QM_TENSOR_1_DIM_1_SIZE 0xE86A50
+
+#define mmTPC2_CFG_QM_TENSOR_1_DIM_1_STRIDE 0xE86A54
+
+#define mmTPC2_CFG_QM_TENSOR_1_DIM_2_SIZE 0xE86A58
+
+#define mmTPC2_CFG_QM_TENSOR_1_DIM_2_STRIDE 0xE86A5C
+
+#define mmTPC2_CFG_QM_TENSOR_1_DIM_3_SIZE 0xE86A60
+
+#define mmTPC2_CFG_QM_TENSOR_1_DIM_3_STRIDE 0xE86A64
+
+#define mmTPC2_CFG_QM_TENSOR_1_DIM_4_SIZE 0xE86A68
+
+#define mmTPC2_CFG_QM_TENSOR_1_DIM_4_STRIDE 0xE86A6C
+
+#define mmTPC2_CFG_QM_TENSOR_2_BASE_ADDR_LOW 0xE86A70
+
+#define mmTPC2_CFG_QM_TENSOR_2_BASE_ADDR_HIGH 0xE86A74
+
+#define mmTPC2_CFG_QM_TENSOR_2_PADDING_VALUE 0xE86A78
+
+#define mmTPC2_CFG_QM_TENSOR_2_TENSOR_CONFIG 0xE86A7C
+
+#define mmTPC2_CFG_QM_TENSOR_2_DIM_0_SIZE 0xE86A80
+
+#define mmTPC2_CFG_QM_TENSOR_2_DIM_0_STRIDE 0xE86A84
+
+#define mmTPC2_CFG_QM_TENSOR_2_DIM_1_SIZE 0xE86A88
+
+#define mmTPC2_CFG_QM_TENSOR_2_DIM_1_STRIDE 0xE86A8C
+
+#define mmTPC2_CFG_QM_TENSOR_2_DIM_2_SIZE 0xE86A90
+
+#define mmTPC2_CFG_QM_TENSOR_2_DIM_2_STRIDE 0xE86A94
+
+#define mmTPC2_CFG_QM_TENSOR_2_DIM_3_SIZE 0xE86A98
+
+#define mmTPC2_CFG_QM_TENSOR_2_DIM_3_STRIDE 0xE86A9C
+
+#define mmTPC2_CFG_QM_TENSOR_2_DIM_4_SIZE 0xE86AA0
+
+#define mmTPC2_CFG_QM_TENSOR_2_DIM_4_STRIDE 0xE86AA4
+
+#define mmTPC2_CFG_QM_TENSOR_3_BASE_ADDR_LOW 0xE86AA8
+
+#define mmTPC2_CFG_QM_TENSOR_3_BASE_ADDR_HIGH 0xE86AAC
+
+#define mmTPC2_CFG_QM_TENSOR_3_PADDING_VALUE 0xE86AB0
+
+#define mmTPC2_CFG_QM_TENSOR_3_TENSOR_CONFIG 0xE86AB4
+
+#define mmTPC2_CFG_QM_TENSOR_3_DIM_0_SIZE 0xE86AB8
+
+#define mmTPC2_CFG_QM_TENSOR_3_DIM_0_STRIDE 0xE86ABC
+
+#define mmTPC2_CFG_QM_TENSOR_3_DIM_1_SIZE 0xE86AC0
+
+#define mmTPC2_CFG_QM_TENSOR_3_DIM_1_STRIDE 0xE86AC4
+
+#define mmTPC2_CFG_QM_TENSOR_3_DIM_2_SIZE 0xE86AC8
+
+#define mmTPC2_CFG_QM_TENSOR_3_DIM_2_STRIDE 0xE86ACC
+
+#define mmTPC2_CFG_QM_TENSOR_3_DIM_3_SIZE 0xE86AD0
+
+#define mmTPC2_CFG_QM_TENSOR_3_DIM_3_STRIDE 0xE86AD4
+
+#define mmTPC2_CFG_QM_TENSOR_3_DIM_4_SIZE 0xE86AD8
+
+#define mmTPC2_CFG_QM_TENSOR_3_DIM_4_STRIDE 0xE86ADC
+
+#define mmTPC2_CFG_QM_TENSOR_4_BASE_ADDR_LOW 0xE86AE0
+
+#define mmTPC2_CFG_QM_TENSOR_4_BASE_ADDR_HIGH 0xE86AE4
+
+#define mmTPC2_CFG_QM_TENSOR_4_PADDING_VALUE 0xE86AE8
+
+#define mmTPC2_CFG_QM_TENSOR_4_TENSOR_CONFIG 0xE86AEC
+
+#define mmTPC2_CFG_QM_TENSOR_4_DIM_0_SIZE 0xE86AF0
+
+#define mmTPC2_CFG_QM_TENSOR_4_DIM_0_STRIDE 0xE86AF4
+
+#define mmTPC2_CFG_QM_TENSOR_4_DIM_1_SIZE 0xE86AF8
+
+#define mmTPC2_CFG_QM_TENSOR_4_DIM_1_STRIDE 0xE86AFC
+
+#define mmTPC2_CFG_QM_TENSOR_4_DIM_2_SIZE 0xE86B00
+
+#define mmTPC2_CFG_QM_TENSOR_4_DIM_2_STRIDE 0xE86B04
+
+#define mmTPC2_CFG_QM_TENSOR_4_DIM_3_SIZE 0xE86B08
+
+#define mmTPC2_CFG_QM_TENSOR_4_DIM_3_STRIDE 0xE86B0C
+
+#define mmTPC2_CFG_QM_TENSOR_4_DIM_4_SIZE 0xE86B10
+
+#define mmTPC2_CFG_QM_TENSOR_4_DIM_4_STRIDE 0xE86B14
+
+#define mmTPC2_CFG_QM_TENSOR_5_BASE_ADDR_LOW 0xE86B18
+
+#define mmTPC2_CFG_QM_TENSOR_5_BASE_ADDR_HIGH 0xE86B1C
+
+#define mmTPC2_CFG_QM_TENSOR_5_PADDING_VALUE 0xE86B20
+
+#define mmTPC2_CFG_QM_TENSOR_5_TENSOR_CONFIG 0xE86B24
+
+#define mmTPC2_CFG_QM_TENSOR_5_DIM_0_SIZE 0xE86B28
+
+#define mmTPC2_CFG_QM_TENSOR_5_DIM_0_STRIDE 0xE86B2C
+
+#define mmTPC2_CFG_QM_TENSOR_5_DIM_1_SIZE 0xE86B30
+
+#define mmTPC2_CFG_QM_TENSOR_5_DIM_1_STRIDE 0xE86B34
+
+#define mmTPC2_CFG_QM_TENSOR_5_DIM_2_SIZE 0xE86B38
+
+#define mmTPC2_CFG_QM_TENSOR_5_DIM_2_STRIDE 0xE86B3C
+
+#define mmTPC2_CFG_QM_TENSOR_5_DIM_3_SIZE 0xE86B40
+
+#define mmTPC2_CFG_QM_TENSOR_5_DIM_3_STRIDE 0xE86B44
+
+#define mmTPC2_CFG_QM_TENSOR_5_DIM_4_SIZE 0xE86B48
+
+#define mmTPC2_CFG_QM_TENSOR_5_DIM_4_STRIDE 0xE86B4C
+
+#define mmTPC2_CFG_QM_TENSOR_6_BASE_ADDR_LOW 0xE86B50
+
+#define mmTPC2_CFG_QM_TENSOR_6_BASE_ADDR_HIGH 0xE86B54
+
+#define mmTPC2_CFG_QM_TENSOR_6_PADDING_VALUE 0xE86B58
+
+#define mmTPC2_CFG_QM_TENSOR_6_TENSOR_CONFIG 0xE86B5C
+
+#define mmTPC2_CFG_QM_TENSOR_6_DIM_0_SIZE 0xE86B60
+
+#define mmTPC2_CFG_QM_TENSOR_6_DIM_0_STRIDE 0xE86B64
+
+#define mmTPC2_CFG_QM_TENSOR_6_DIM_1_SIZE 0xE86B68
+
+#define mmTPC2_CFG_QM_TENSOR_6_DIM_1_STRIDE 0xE86B6C
+
+#define mmTPC2_CFG_QM_TENSOR_6_DIM_2_SIZE 0xE86B70
+
+#define mmTPC2_CFG_QM_TENSOR_6_DIM_2_STRIDE 0xE86B74
+
+#define mmTPC2_CFG_QM_TENSOR_6_DIM_3_SIZE 0xE86B78
+
+#define mmTPC2_CFG_QM_TENSOR_6_DIM_3_STRIDE 0xE86B7C
+
+#define mmTPC2_CFG_QM_TENSOR_6_DIM_4_SIZE 0xE86B80
+
+#define mmTPC2_CFG_QM_TENSOR_6_DIM_4_STRIDE 0xE86B84
+
+#define mmTPC2_CFG_QM_TENSOR_7_BASE_ADDR_LOW 0xE86B88
+
+#define mmTPC2_CFG_QM_TENSOR_7_BASE_ADDR_HIGH 0xE86B8C
+
+#define mmTPC2_CFG_QM_TENSOR_7_PADDING_VALUE 0xE86B90
+
+#define mmTPC2_CFG_QM_TENSOR_7_TENSOR_CONFIG 0xE86B94
+
+#define mmTPC2_CFG_QM_TENSOR_7_DIM_0_SIZE 0xE86B98
+
+#define mmTPC2_CFG_QM_TENSOR_7_DIM_0_STRIDE 0xE86B9C
+
+#define mmTPC2_CFG_QM_TENSOR_7_DIM_1_SIZE 0xE86BA0
+
+#define mmTPC2_CFG_QM_TENSOR_7_DIM_1_STRIDE 0xE86BA4
+
+#define mmTPC2_CFG_QM_TENSOR_7_DIM_2_SIZE 0xE86BA8
+
+#define mmTPC2_CFG_QM_TENSOR_7_DIM_2_STRIDE 0xE86BAC
+
+#define mmTPC2_CFG_QM_TENSOR_7_DIM_3_SIZE 0xE86BB0
+
+#define mmTPC2_CFG_QM_TENSOR_7_DIM_3_STRIDE 0xE86BB4
+
+#define mmTPC2_CFG_QM_TENSOR_7_DIM_4_SIZE 0xE86BB8
+
+#define mmTPC2_CFG_QM_TENSOR_7_DIM_4_STRIDE 0xE86BBC
+
+#define mmTPC2_CFG_QM_TENSOR_8_BASE_ADDR_LOW 0xE86BC0
+
+#define mmTPC2_CFG_QM_TENSOR_8_BASE_ADDR_HIGH 0xE86BC4
+
+#define mmTPC2_CFG_QM_TENSOR_8_PADDING_VALUE 0xE86BC8
+
+#define mmTPC2_CFG_QM_TENSOR_8_TENSOR_CONFIG 0xE86BCC
+
+#define mmTPC2_CFG_QM_TENSOR_8_DIM_0_SIZE 0xE86BD0
+
+#define mmTPC2_CFG_QM_TENSOR_8_DIM_0_STRIDE 0xE86BD4
+
+#define mmTPC2_CFG_QM_TENSOR_8_DIM_1_SIZE 0xE86BD8
+
+#define mmTPC2_CFG_QM_TENSOR_8_DIM_1_STRIDE 0xE86BDC
+
+#define mmTPC2_CFG_QM_TENSOR_8_DIM_2_SIZE 0xE86BE0
+
+#define mmTPC2_CFG_QM_TENSOR_8_DIM_2_STRIDE 0xE86BE4
+
+#define mmTPC2_CFG_QM_TENSOR_8_DIM_3_SIZE 0xE86BE8
+
+#define mmTPC2_CFG_QM_TENSOR_8_DIM_3_STRIDE 0xE86BEC
+
+#define mmTPC2_CFG_QM_TENSOR_8_DIM_4_SIZE 0xE86BF0
+
+#define mmTPC2_CFG_QM_TENSOR_8_DIM_4_STRIDE 0xE86BF4
+
+#define mmTPC2_CFG_QM_TENSOR_9_BASE_ADDR_LOW 0xE86BF8
+
+#define mmTPC2_CFG_QM_TENSOR_9_BASE_ADDR_HIGH 0xE86BFC
+
+#define mmTPC2_CFG_QM_TENSOR_9_PADDING_VALUE 0xE86C00
+
+#define mmTPC2_CFG_QM_TENSOR_9_TENSOR_CONFIG 0xE86C04
+
+#define mmTPC2_CFG_QM_TENSOR_9_DIM_0_SIZE 0xE86C08
+
+#define mmTPC2_CFG_QM_TENSOR_9_DIM_0_STRIDE 0xE86C0C
+
+#define mmTPC2_CFG_QM_TENSOR_9_DIM_1_SIZE 0xE86C10
+
+#define mmTPC2_CFG_QM_TENSOR_9_DIM_1_STRIDE 0xE86C14
+
+#define mmTPC2_CFG_QM_TENSOR_9_DIM_2_SIZE 0xE86C18
+
+#define mmTPC2_CFG_QM_TENSOR_9_DIM_2_STRIDE 0xE86C1C
+
+#define mmTPC2_CFG_QM_TENSOR_9_DIM_3_SIZE 0xE86C20
+
+#define mmTPC2_CFG_QM_TENSOR_9_DIM_3_STRIDE 0xE86C24
+
+#define mmTPC2_CFG_QM_TENSOR_9_DIM_4_SIZE 0xE86C28
+
+#define mmTPC2_CFG_QM_TENSOR_9_DIM_4_STRIDE 0xE86C2C
+
+#define mmTPC2_CFG_QM_TENSOR_10_BASE_ADDR_LOW 0xE86C30
+
+#define mmTPC2_CFG_QM_TENSOR_10_BASE_ADDR_HIGH 0xE86C34
+
+#define mmTPC2_CFG_QM_TENSOR_10_PADDING_VALUE 0xE86C38
+
+#define mmTPC2_CFG_QM_TENSOR_10_TENSOR_CONFIG 0xE86C3C
+
+#define mmTPC2_CFG_QM_TENSOR_10_DIM_0_SIZE 0xE86C40
+
+#define mmTPC2_CFG_QM_TENSOR_10_DIM_0_STRIDE 0xE86C44
+
+#define mmTPC2_CFG_QM_TENSOR_10_DIM_1_SIZE 0xE86C48
+
+#define mmTPC2_CFG_QM_TENSOR_10_DIM_1_STRIDE 0xE86C4C
+
+#define mmTPC2_CFG_QM_TENSOR_10_DIM_2_SIZE 0xE86C50
+
+#define mmTPC2_CFG_QM_TENSOR_10_DIM_2_STRIDE 0xE86C54
+
+#define mmTPC2_CFG_QM_TENSOR_10_DIM_3_SIZE 0xE86C58
+
+#define mmTPC2_CFG_QM_TENSOR_10_DIM_3_STRIDE 0xE86C5C
+
+#define mmTPC2_CFG_QM_TENSOR_10_DIM_4_SIZE 0xE86C60
+
+#define mmTPC2_CFG_QM_TENSOR_10_DIM_4_STRIDE 0xE86C64
+
+#define mmTPC2_CFG_QM_TENSOR_11_BASE_ADDR_LOW 0xE86C68
+
+#define mmTPC2_CFG_QM_TENSOR_11_BASE_ADDR_HIGH 0xE86C6C
+
+#define mmTPC2_CFG_QM_TENSOR_11_PADDING_VALUE 0xE86C70
+
+#define mmTPC2_CFG_QM_TENSOR_11_TENSOR_CONFIG 0xE86C74
+
+#define mmTPC2_CFG_QM_TENSOR_11_DIM_0_SIZE 0xE86C78
+
+#define mmTPC2_CFG_QM_TENSOR_11_DIM_0_STRIDE 0xE86C7C
+
+#define mmTPC2_CFG_QM_TENSOR_11_DIM_1_SIZE 0xE86C80
+
+#define mmTPC2_CFG_QM_TENSOR_11_DIM_1_STRIDE 0xE86C84
+
+#define mmTPC2_CFG_QM_TENSOR_11_DIM_2_SIZE 0xE86C88
+
+#define mmTPC2_CFG_QM_TENSOR_11_DIM_2_STRIDE 0xE86C8C
+
+#define mmTPC2_CFG_QM_TENSOR_11_DIM_3_SIZE 0xE86C90
+
+#define mmTPC2_CFG_QM_TENSOR_11_DIM_3_STRIDE 0xE86C94
+
+#define mmTPC2_CFG_QM_TENSOR_11_DIM_4_SIZE 0xE86C98
+
+#define mmTPC2_CFG_QM_TENSOR_11_DIM_4_STRIDE 0xE86C9C
+
+#define mmTPC2_CFG_QM_TENSOR_12_BASE_ADDR_LOW 0xE86CA0
+
+#define mmTPC2_CFG_QM_TENSOR_12_BASE_ADDR_HIGH 0xE86CA4
+
+#define mmTPC2_CFG_QM_TENSOR_12_PADDING_VALUE 0xE86CA8
+
+#define mmTPC2_CFG_QM_TENSOR_12_TENSOR_CONFIG 0xE86CAC
+
+#define mmTPC2_CFG_QM_TENSOR_12_DIM_0_SIZE 0xE86CB0
+
+#define mmTPC2_CFG_QM_TENSOR_12_DIM_0_STRIDE 0xE86CB4
+
+#define mmTPC2_CFG_QM_TENSOR_12_DIM_1_SIZE 0xE86CB8
+
+#define mmTPC2_CFG_QM_TENSOR_12_DIM_1_STRIDE 0xE86CBC
+
+#define mmTPC2_CFG_QM_TENSOR_12_DIM_2_SIZE 0xE86CC0
+
+#define mmTPC2_CFG_QM_TENSOR_12_DIM_2_STRIDE 0xE86CC4
+
+#define mmTPC2_CFG_QM_TENSOR_12_DIM_3_SIZE 0xE86CC8
+
+#define mmTPC2_CFG_QM_TENSOR_12_DIM_3_STRIDE 0xE86CCC
+
+#define mmTPC2_CFG_QM_TENSOR_12_DIM_4_SIZE 0xE86CD0
+
+#define mmTPC2_CFG_QM_TENSOR_12_DIM_4_STRIDE 0xE86CD4
+
+#define mmTPC2_CFG_QM_TENSOR_13_BASE_ADDR_LOW 0xE86CD8
+
+#define mmTPC2_CFG_QM_TENSOR_13_BASE_ADDR_HIGH 0xE86CDC
+
+#define mmTPC2_CFG_QM_TENSOR_13_PADDING_VALUE 0xE86CE0
+
+#define mmTPC2_CFG_QM_TENSOR_13_TENSOR_CONFIG 0xE86CE4
+
+#define mmTPC2_CFG_QM_TENSOR_13_DIM_0_SIZE 0xE86CE8
+
+#define mmTPC2_CFG_QM_TENSOR_13_DIM_0_STRIDE 0xE86CEC
+
+#define mmTPC2_CFG_QM_TENSOR_13_DIM_1_SIZE 0xE86CF0
+
+#define mmTPC2_CFG_QM_TENSOR_13_DIM_1_STRIDE 0xE86CF4
+
+#define mmTPC2_CFG_QM_TENSOR_13_DIM_2_SIZE 0xE86CF8
+
+#define mmTPC2_CFG_QM_TENSOR_13_DIM_2_STRIDE 0xE86CFC
+
+#define mmTPC2_CFG_QM_TENSOR_13_DIM_3_SIZE 0xE86D00
+
+#define mmTPC2_CFG_QM_TENSOR_13_DIM_3_STRIDE 0xE86D04
+
+#define mmTPC2_CFG_QM_TENSOR_13_DIM_4_SIZE 0xE86D08
+
+#define mmTPC2_CFG_QM_TENSOR_13_DIM_4_STRIDE 0xE86D0C
+
+#define mmTPC2_CFG_QM_TENSOR_14_BASE_ADDR_LOW 0xE86D10
+
+#define mmTPC2_CFG_QM_TENSOR_14_BASE_ADDR_HIGH 0xE86D14
+
+#define mmTPC2_CFG_QM_TENSOR_14_PADDING_VALUE 0xE86D18
+
+#define mmTPC2_CFG_QM_TENSOR_14_TENSOR_CONFIG 0xE86D1C
+
+#define mmTPC2_CFG_QM_TENSOR_14_DIM_0_SIZE 0xE86D20
+
+#define mmTPC2_CFG_QM_TENSOR_14_DIM_0_STRIDE 0xE86D24
+
+#define mmTPC2_CFG_QM_TENSOR_14_DIM_1_SIZE 0xE86D28
+
+#define mmTPC2_CFG_QM_TENSOR_14_DIM_1_STRIDE 0xE86D2C
+
+#define mmTPC2_CFG_QM_TENSOR_14_DIM_2_SIZE 0xE86D30
+
+#define mmTPC2_CFG_QM_TENSOR_14_DIM_2_STRIDE 0xE86D34
+
+#define mmTPC2_CFG_QM_TENSOR_14_DIM_3_SIZE 0xE86D38
+
+#define mmTPC2_CFG_QM_TENSOR_14_DIM_3_STRIDE 0xE86D3C
+
+#define mmTPC2_CFG_QM_TENSOR_14_DIM_4_SIZE 0xE86D40
+
+#define mmTPC2_CFG_QM_TENSOR_14_DIM_4_STRIDE 0xE86D44
+
+#define mmTPC2_CFG_QM_TENSOR_15_BASE_ADDR_LOW 0xE86D48
+
+#define mmTPC2_CFG_QM_TENSOR_15_BASE_ADDR_HIGH 0xE86D4C
+
+#define mmTPC2_CFG_QM_TENSOR_15_PADDING_VALUE 0xE86D50
+
+#define mmTPC2_CFG_QM_TENSOR_15_TENSOR_CONFIG 0xE86D54
+
+#define mmTPC2_CFG_QM_TENSOR_15_DIM_0_SIZE 0xE86D58
+
+#define mmTPC2_CFG_QM_TENSOR_15_DIM_0_STRIDE 0xE86D5C
+
+#define mmTPC2_CFG_QM_TENSOR_15_DIM_1_SIZE 0xE86D60
+
+#define mmTPC2_CFG_QM_TENSOR_15_DIM_1_STRIDE 0xE86D64
+
+#define mmTPC2_CFG_QM_TENSOR_15_DIM_2_SIZE 0xE86D68
+
+#define mmTPC2_CFG_QM_TENSOR_15_DIM_2_STRIDE 0xE86D6C
+
+#define mmTPC2_CFG_QM_TENSOR_15_DIM_3_SIZE 0xE86D70
+
+#define mmTPC2_CFG_QM_TENSOR_15_DIM_3_STRIDE 0xE86D74
+
+#define mmTPC2_CFG_QM_TENSOR_15_DIM_4_SIZE 0xE86D78
+
+#define mmTPC2_CFG_QM_TENSOR_15_DIM_4_STRIDE 0xE86D7C
+
+#define mmTPC2_CFG_QM_SYNC_OBJECT_MESSAGE 0xE86D80
+
+#define mmTPC2_CFG_QM_SYNC_OBJECT_ADDR 0xE86D84
+
+#define mmTPC2_CFG_QM_KERNEL_BASE_ADDRESS_LOW 0xE86D88
+
+#define mmTPC2_CFG_QM_KERNEL_BASE_ADDRESS_HIGH 0xE86D8C
+
+#define mmTPC2_CFG_QM_TID_BASE_DIM_0 0xE86D90
+
+#define mmTPC2_CFG_QM_TID_SIZE_DIM_0 0xE86D94
+
+#define mmTPC2_CFG_QM_TID_BASE_DIM_1 0xE86D98
+
+#define mmTPC2_CFG_QM_TID_SIZE_DIM_1 0xE86D9C
+
+#define mmTPC2_CFG_QM_TID_BASE_DIM_2 0xE86DA0
+
+#define mmTPC2_CFG_QM_TID_SIZE_DIM_2 0xE86DA4
+
+#define mmTPC2_CFG_QM_TID_BASE_DIM_3 0xE86DA8
+
+#define mmTPC2_CFG_QM_TID_SIZE_DIM_3 0xE86DAC
+
+#define mmTPC2_CFG_QM_TID_BASE_DIM_4 0xE86DB0
+
+#define mmTPC2_CFG_QM_TID_SIZE_DIM_4 0xE86DB4
+
+#define mmTPC2_CFG_QM_KERNEL_CONFIG 0xE86DB8
+
+#define mmTPC2_CFG_QM_KERNEL_ID 0xE86DBC
+
+#define mmTPC2_CFG_QM_SRF_0 0xE86DC0
+
+#define mmTPC2_CFG_QM_SRF_1 0xE86DC4
+
+#define mmTPC2_CFG_QM_SRF_2 0xE86DC8
+
+#define mmTPC2_CFG_QM_SRF_3 0xE86DCC
+
+#define mmTPC2_CFG_QM_SRF_4 0xE86DD0
+
+#define mmTPC2_CFG_QM_SRF_5 0xE86DD4
+
+#define mmTPC2_CFG_QM_SRF_6 0xE86DD8
+
+#define mmTPC2_CFG_QM_SRF_7 0xE86DDC
+
+#define mmTPC2_CFG_QM_SRF_8 0xE86DE0
+
+#define mmTPC2_CFG_QM_SRF_9 0xE86DE4
+
+#define mmTPC2_CFG_QM_SRF_10 0xE86DE8
+
+#define mmTPC2_CFG_QM_SRF_11 0xE86DEC
+
+#define mmTPC2_CFG_QM_SRF_12 0xE86DF0
+
+#define mmTPC2_CFG_QM_SRF_13 0xE86DF4
+
+#define mmTPC2_CFG_QM_SRF_14 0xE86DF8
+
+#define mmTPC2_CFG_QM_SRF_15 0xE86DFC
+
+#define mmTPC2_CFG_QM_SRF_16 0xE86E00
+
+#define mmTPC2_CFG_QM_SRF_17 0xE86E04
+
+#define mmTPC2_CFG_QM_SRF_18 0xE86E08
+
+#define mmTPC2_CFG_QM_SRF_19 0xE86E0C
+
+#define mmTPC2_CFG_QM_SRF_20 0xE86E10
+
+#define mmTPC2_CFG_QM_SRF_21 0xE86E14
+
+#define mmTPC2_CFG_QM_SRF_22 0xE86E18
+
+#define mmTPC2_CFG_QM_SRF_23 0xE86E1C
+
+#define mmTPC2_CFG_QM_SRF_24 0xE86E20
+
+#define mmTPC2_CFG_QM_SRF_25 0xE86E24
+
+#define mmTPC2_CFG_QM_SRF_26 0xE86E28
+
+#define mmTPC2_CFG_QM_SRF_27 0xE86E2C
+
+#define mmTPC2_CFG_QM_SRF_28 0xE86E30
+
+#define mmTPC2_CFG_QM_SRF_29 0xE86E34
+
+#define mmTPC2_CFG_QM_SRF_30 0xE86E38
+
+#define mmTPC2_CFG_QM_SRF_31 0xE86E3C
+
+#endif /* ASIC_REG_TPC2_CFG_REGS_H_ */
diff --git a/drivers/accel/habanalabs/include/gaudi/asic_reg/tpc2_qm_regs.h b/drivers/accel/habanalabs/include/gaudi/asic_reg/tpc2_qm_regs.h
new file mode 100644
index 0000000000..2919e2fa58
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi/asic_reg/tpc2_qm_regs.h
@@ -0,0 +1,834 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2016-2018 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ ** DO NOT EDIT BELOW **
+ ************************************/
+
+#ifndef ASIC_REG_TPC2_QM_REGS_H_
+#define ASIC_REG_TPC2_QM_REGS_H_
+
+/*
+ *****************************************
+ * TPC2_QM (Prototype: QMAN)
+ *****************************************
+ */
+
+#define mmTPC2_QM_GLBL_CFG0 0xE88000
+
+#define mmTPC2_QM_GLBL_CFG1 0xE88004
+
+#define mmTPC2_QM_GLBL_PROT 0xE88008
+
+#define mmTPC2_QM_GLBL_ERR_CFG 0xE8800C
+
+#define mmTPC2_QM_GLBL_SECURE_PROPS_0 0xE88010
+
+#define mmTPC2_QM_GLBL_SECURE_PROPS_1 0xE88014
+
+#define mmTPC2_QM_GLBL_SECURE_PROPS_2 0xE88018
+
+#define mmTPC2_QM_GLBL_SECURE_PROPS_3 0xE8801C
+
+#define mmTPC2_QM_GLBL_SECURE_PROPS_4 0xE88020
+
+#define mmTPC2_QM_GLBL_NON_SECURE_PROPS_0 0xE88024
+
+#define mmTPC2_QM_GLBL_NON_SECURE_PROPS_1 0xE88028
+
+#define mmTPC2_QM_GLBL_NON_SECURE_PROPS_2 0xE8802C
+
+#define mmTPC2_QM_GLBL_NON_SECURE_PROPS_3 0xE88030
+
+#define mmTPC2_QM_GLBL_NON_SECURE_PROPS_4 0xE88034
+
+#define mmTPC2_QM_GLBL_STS0 0xE88038
+
+#define mmTPC2_QM_GLBL_STS1_0 0xE88040
+
+#define mmTPC2_QM_GLBL_STS1_1 0xE88044
+
+#define mmTPC2_QM_GLBL_STS1_2 0xE88048
+
+#define mmTPC2_QM_GLBL_STS1_3 0xE8804C
+
+#define mmTPC2_QM_GLBL_STS1_4 0xE88050
+
+#define mmTPC2_QM_GLBL_MSG_EN_0 0xE88054
+
+#define mmTPC2_QM_GLBL_MSG_EN_1 0xE88058
+
+#define mmTPC2_QM_GLBL_MSG_EN_2 0xE8805C
+
+#define mmTPC2_QM_GLBL_MSG_EN_3 0xE88060
+
+#define mmTPC2_QM_GLBL_MSG_EN_4 0xE88068
+
+#define mmTPC2_QM_PQ_BASE_LO_0 0xE88070
+
+#define mmTPC2_QM_PQ_BASE_LO_1 0xE88074
+
+#define mmTPC2_QM_PQ_BASE_LO_2 0xE88078
+
+#define mmTPC2_QM_PQ_BASE_LO_3 0xE8807C
+
+#define mmTPC2_QM_PQ_BASE_HI_0 0xE88080
+
+#define mmTPC2_QM_PQ_BASE_HI_1 0xE88084
+
+#define mmTPC2_QM_PQ_BASE_HI_2 0xE88088
+
+#define mmTPC2_QM_PQ_BASE_HI_3 0xE8808C
+
+#define mmTPC2_QM_PQ_SIZE_0 0xE88090
+
+#define mmTPC2_QM_PQ_SIZE_1 0xE88094
+
+#define mmTPC2_QM_PQ_SIZE_2 0xE88098
+
+#define mmTPC2_QM_PQ_SIZE_3 0xE8809C
+
+#define mmTPC2_QM_PQ_PI_0 0xE880A0
+
+#define mmTPC2_QM_PQ_PI_1 0xE880A4
+
+#define mmTPC2_QM_PQ_PI_2 0xE880A8
+
+#define mmTPC2_QM_PQ_PI_3 0xE880AC
+
+#define mmTPC2_QM_PQ_CI_0 0xE880B0
+
+#define mmTPC2_QM_PQ_CI_1 0xE880B4
+
+#define mmTPC2_QM_PQ_CI_2 0xE880B8
+
+#define mmTPC2_QM_PQ_CI_3 0xE880BC
+
+#define mmTPC2_QM_PQ_CFG0_0 0xE880C0
+
+#define mmTPC2_QM_PQ_CFG0_1 0xE880C4
+
+#define mmTPC2_QM_PQ_CFG0_2 0xE880C8
+
+#define mmTPC2_QM_PQ_CFG0_3 0xE880CC
+
+#define mmTPC2_QM_PQ_CFG1_0 0xE880D0
+
+#define mmTPC2_QM_PQ_CFG1_1 0xE880D4
+
+#define mmTPC2_QM_PQ_CFG1_2 0xE880D8
+
+#define mmTPC2_QM_PQ_CFG1_3 0xE880DC
+
+#define mmTPC2_QM_PQ_ARUSER_31_11_0 0xE880E0
+
+#define mmTPC2_QM_PQ_ARUSER_31_11_1 0xE880E4
+
+#define mmTPC2_QM_PQ_ARUSER_31_11_2 0xE880E8
+
+#define mmTPC2_QM_PQ_ARUSER_31_11_3 0xE880EC
+
+#define mmTPC2_QM_PQ_STS0_0 0xE880F0
+
+#define mmTPC2_QM_PQ_STS0_1 0xE880F4
+
+#define mmTPC2_QM_PQ_STS0_2 0xE880F8
+
+#define mmTPC2_QM_PQ_STS0_3 0xE880FC
+
+#define mmTPC2_QM_PQ_STS1_0 0xE88100
+
+#define mmTPC2_QM_PQ_STS1_1 0xE88104
+
+#define mmTPC2_QM_PQ_STS1_2 0xE88108
+
+#define mmTPC2_QM_PQ_STS1_3 0xE8810C
+
+#define mmTPC2_QM_CQ_CFG0_0 0xE88110
+
+#define mmTPC2_QM_CQ_CFG0_1 0xE88114
+
+#define mmTPC2_QM_CQ_CFG0_2 0xE88118
+
+#define mmTPC2_QM_CQ_CFG0_3 0xE8811C
+
+#define mmTPC2_QM_CQ_CFG0_4 0xE88120
+
+#define mmTPC2_QM_CQ_CFG1_0 0xE88124
+
+#define mmTPC2_QM_CQ_CFG1_1 0xE88128
+
+#define mmTPC2_QM_CQ_CFG1_2 0xE8812C
+
+#define mmTPC2_QM_CQ_CFG1_3 0xE88130
+
+#define mmTPC2_QM_CQ_CFG1_4 0xE88134
+
+#define mmTPC2_QM_CQ_ARUSER_31_11_0 0xE88138
+
+#define mmTPC2_QM_CQ_ARUSER_31_11_1 0xE8813C
+
+#define mmTPC2_QM_CQ_ARUSER_31_11_2 0xE88140
+
+#define mmTPC2_QM_CQ_ARUSER_31_11_3 0xE88144
+
+#define mmTPC2_QM_CQ_ARUSER_31_11_4 0xE88148
+
+#define mmTPC2_QM_CQ_STS0_0 0xE8814C
+
+#define mmTPC2_QM_CQ_STS0_1 0xE88150
+
+#define mmTPC2_QM_CQ_STS0_2 0xE88154
+
+#define mmTPC2_QM_CQ_STS0_3 0xE88158
+
+#define mmTPC2_QM_CQ_STS0_4 0xE8815C
+
+#define mmTPC2_QM_CQ_STS1_0 0xE88160
+
+#define mmTPC2_QM_CQ_STS1_1 0xE88164
+
+#define mmTPC2_QM_CQ_STS1_2 0xE88168
+
+#define mmTPC2_QM_CQ_STS1_3 0xE8816C
+
+#define mmTPC2_QM_CQ_STS1_4 0xE88170
+
+#define mmTPC2_QM_CQ_PTR_LO_0 0xE88174
+
+#define mmTPC2_QM_CQ_PTR_HI_0 0xE88178
+
+#define mmTPC2_QM_CQ_TSIZE_0 0xE8817C
+
+#define mmTPC2_QM_CQ_CTL_0 0xE88180
+
+#define mmTPC2_QM_CQ_PTR_LO_1 0xE88184
+
+#define mmTPC2_QM_CQ_PTR_HI_1 0xE88188
+
+#define mmTPC2_QM_CQ_TSIZE_1 0xE8818C
+
+#define mmTPC2_QM_CQ_CTL_1 0xE88190
+
+#define mmTPC2_QM_CQ_PTR_LO_2 0xE88194
+
+#define mmTPC2_QM_CQ_PTR_HI_2 0xE88198
+
+#define mmTPC2_QM_CQ_TSIZE_2 0xE8819C
+
+#define mmTPC2_QM_CQ_CTL_2 0xE881A0
+
+#define mmTPC2_QM_CQ_PTR_LO_3 0xE881A4
+
+#define mmTPC2_QM_CQ_PTR_HI_3 0xE881A8
+
+#define mmTPC2_QM_CQ_TSIZE_3 0xE881AC
+
+#define mmTPC2_QM_CQ_CTL_3 0xE881B0
+
+#define mmTPC2_QM_CQ_PTR_LO_4 0xE881B4
+
+#define mmTPC2_QM_CQ_PTR_HI_4 0xE881B8
+
+#define mmTPC2_QM_CQ_TSIZE_4 0xE881BC
+
+#define mmTPC2_QM_CQ_CTL_4 0xE881C0
+
+#define mmTPC2_QM_CQ_PTR_LO_STS_0 0xE881C4
+
+#define mmTPC2_QM_CQ_PTR_LO_STS_1 0xE881C8
+
+#define mmTPC2_QM_CQ_PTR_LO_STS_2 0xE881CC
+
+#define mmTPC2_QM_CQ_PTR_LO_STS_3 0xE881D0
+
+#define mmTPC2_QM_CQ_PTR_LO_STS_4 0xE881D4
+
+#define mmTPC2_QM_CQ_PTR_HI_STS_0 0xE881D8
+
+#define mmTPC2_QM_CQ_PTR_HI_STS_1 0xE881DC
+
+#define mmTPC2_QM_CQ_PTR_HI_STS_2 0xE881E0
+
+#define mmTPC2_QM_CQ_PTR_HI_STS_3 0xE881E4
+
+#define mmTPC2_QM_CQ_PTR_HI_STS_4 0xE881E8
+
+#define mmTPC2_QM_CQ_TSIZE_STS_0 0xE881EC
+
+#define mmTPC2_QM_CQ_TSIZE_STS_1 0xE881F0
+
+#define mmTPC2_QM_CQ_TSIZE_STS_2 0xE881F4
+
+#define mmTPC2_QM_CQ_TSIZE_STS_3 0xE881F8
+
+#define mmTPC2_QM_CQ_TSIZE_STS_4 0xE881FC
+
+#define mmTPC2_QM_CQ_CTL_STS_0 0xE88200
+
+#define mmTPC2_QM_CQ_CTL_STS_1 0xE88204
+
+#define mmTPC2_QM_CQ_CTL_STS_2 0xE88208
+
+#define mmTPC2_QM_CQ_CTL_STS_3 0xE8820C
+
+#define mmTPC2_QM_CQ_CTL_STS_4 0xE88210
+
+#define mmTPC2_QM_CQ_IFIFO_CNT_0 0xE88214
+
+#define mmTPC2_QM_CQ_IFIFO_CNT_1 0xE88218
+
+#define mmTPC2_QM_CQ_IFIFO_CNT_2 0xE8821C
+
+#define mmTPC2_QM_CQ_IFIFO_CNT_3 0xE88220
+
+#define mmTPC2_QM_CQ_IFIFO_CNT_4 0xE88224
+
+#define mmTPC2_QM_CP_MSG_BASE0_ADDR_LO_0 0xE88228
+
+#define mmTPC2_QM_CP_MSG_BASE0_ADDR_LO_1 0xE8822C
+
+#define mmTPC2_QM_CP_MSG_BASE0_ADDR_LO_2 0xE88230
+
+#define mmTPC2_QM_CP_MSG_BASE0_ADDR_LO_3 0xE88234
+
+#define mmTPC2_QM_CP_MSG_BASE0_ADDR_LO_4 0xE88238
+
+#define mmTPC2_QM_CP_MSG_BASE0_ADDR_HI_0 0xE8823C
+
+#define mmTPC2_QM_CP_MSG_BASE0_ADDR_HI_1 0xE88240
+
+#define mmTPC2_QM_CP_MSG_BASE0_ADDR_HI_2 0xE88244
+
+#define mmTPC2_QM_CP_MSG_BASE0_ADDR_HI_3 0xE88248
+
+#define mmTPC2_QM_CP_MSG_BASE0_ADDR_HI_4 0xE8824C
+
+#define mmTPC2_QM_CP_MSG_BASE1_ADDR_LO_0 0xE88250
+
+#define mmTPC2_QM_CP_MSG_BASE1_ADDR_LO_1 0xE88254
+
+#define mmTPC2_QM_CP_MSG_BASE1_ADDR_LO_2 0xE88258
+
+#define mmTPC2_QM_CP_MSG_BASE1_ADDR_LO_3 0xE8825C
+
+#define mmTPC2_QM_CP_MSG_BASE1_ADDR_LO_4 0xE88260
+
+#define mmTPC2_QM_CP_MSG_BASE1_ADDR_HI_0 0xE88264
+
+#define mmTPC2_QM_CP_MSG_BASE1_ADDR_HI_1 0xE88268
+
+#define mmTPC2_QM_CP_MSG_BASE1_ADDR_HI_2 0xE8826C
+
+#define mmTPC2_QM_CP_MSG_BASE1_ADDR_HI_3 0xE88270
+
+#define mmTPC2_QM_CP_MSG_BASE1_ADDR_HI_4 0xE88274
+
+#define mmTPC2_QM_CP_MSG_BASE2_ADDR_LO_0 0xE88278
+
+#define mmTPC2_QM_CP_MSG_BASE2_ADDR_LO_1 0xE8827C
+
+#define mmTPC2_QM_CP_MSG_BASE2_ADDR_LO_2 0xE88280
+
+#define mmTPC2_QM_CP_MSG_BASE2_ADDR_LO_3 0xE88284
+
+#define mmTPC2_QM_CP_MSG_BASE2_ADDR_LO_4 0xE88288
+
+#define mmTPC2_QM_CP_MSG_BASE2_ADDR_HI_0 0xE8828C
+
+#define mmTPC2_QM_CP_MSG_BASE2_ADDR_HI_1 0xE88290
+
+#define mmTPC2_QM_CP_MSG_BASE2_ADDR_HI_2 0xE88294
+
+#define mmTPC2_QM_CP_MSG_BASE2_ADDR_HI_3 0xE88298
+
+#define mmTPC2_QM_CP_MSG_BASE2_ADDR_HI_4 0xE8829C
+
+#define mmTPC2_QM_CP_MSG_BASE3_ADDR_LO_0 0xE882A0
+
+#define mmTPC2_QM_CP_MSG_BASE3_ADDR_LO_1 0xE882A4
+
+#define mmTPC2_QM_CP_MSG_BASE3_ADDR_LO_2 0xE882A8
+
+#define mmTPC2_QM_CP_MSG_BASE3_ADDR_LO_3 0xE882AC
+
+#define mmTPC2_QM_CP_MSG_BASE3_ADDR_LO_4 0xE882B0
+
+#define mmTPC2_QM_CP_MSG_BASE3_ADDR_HI_0 0xE882B4
+
+#define mmTPC2_QM_CP_MSG_BASE3_ADDR_HI_1 0xE882B8
+
+#define mmTPC2_QM_CP_MSG_BASE3_ADDR_HI_2 0xE882BC
+
+#define mmTPC2_QM_CP_MSG_BASE3_ADDR_HI_3 0xE882C0
+
+#define mmTPC2_QM_CP_MSG_BASE3_ADDR_HI_4 0xE882C4
+
+#define mmTPC2_QM_CP_LDMA_TSIZE_OFFSET_0 0xE882C8
+
+#define mmTPC2_QM_CP_LDMA_TSIZE_OFFSET_1 0xE882CC
+
+#define mmTPC2_QM_CP_LDMA_TSIZE_OFFSET_2 0xE882D0
+
+#define mmTPC2_QM_CP_LDMA_TSIZE_OFFSET_3 0xE882D4
+
+#define mmTPC2_QM_CP_LDMA_TSIZE_OFFSET_4 0xE882D8
+
+#define mmTPC2_QM_CP_LDMA_SRC_BASE_LO_OFFSET_0 0xE882E0
+
+#define mmTPC2_QM_CP_LDMA_SRC_BASE_LO_OFFSET_1 0xE882E4
+
+#define mmTPC2_QM_CP_LDMA_SRC_BASE_LO_OFFSET_2 0xE882E8
+
+#define mmTPC2_QM_CP_LDMA_SRC_BASE_LO_OFFSET_3 0xE882EC
+
+#define mmTPC2_QM_CP_LDMA_SRC_BASE_LO_OFFSET_4 0xE882F0
+
+#define mmTPC2_QM_CP_LDMA_DST_BASE_LO_OFFSET_0 0xE882F4
+
+#define mmTPC2_QM_CP_LDMA_DST_BASE_LO_OFFSET_1 0xE882F8
+
+#define mmTPC2_QM_CP_LDMA_DST_BASE_LO_OFFSET_2 0xE882FC
+
+#define mmTPC2_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 0xE88300
+
+#define mmTPC2_QM_CP_LDMA_DST_BASE_LO_OFFSET_4 0xE88304
+
+#define mmTPC2_QM_CP_FENCE0_RDATA_0 0xE88308
+
+#define mmTPC2_QM_CP_FENCE0_RDATA_1 0xE8830C
+
+#define mmTPC2_QM_CP_FENCE0_RDATA_2 0xE88310
+
+#define mmTPC2_QM_CP_FENCE0_RDATA_3 0xE88314
+
+#define mmTPC2_QM_CP_FENCE0_RDATA_4 0xE88318
+
+#define mmTPC2_QM_CP_FENCE1_RDATA_0 0xE8831C
+
+#define mmTPC2_QM_CP_FENCE1_RDATA_1 0xE88320
+
+#define mmTPC2_QM_CP_FENCE1_RDATA_2 0xE88324
+
+#define mmTPC2_QM_CP_FENCE1_RDATA_3 0xE88328
+
+#define mmTPC2_QM_CP_FENCE1_RDATA_4 0xE8832C
+
+#define mmTPC2_QM_CP_FENCE2_RDATA_0 0xE88330
+
+#define mmTPC2_QM_CP_FENCE2_RDATA_1 0xE88334
+
+#define mmTPC2_QM_CP_FENCE2_RDATA_2 0xE88338
+
+#define mmTPC2_QM_CP_FENCE2_RDATA_3 0xE8833C
+
+#define mmTPC2_QM_CP_FENCE2_RDATA_4 0xE88340
+
+#define mmTPC2_QM_CP_FENCE3_RDATA_0 0xE88344
+
+#define mmTPC2_QM_CP_FENCE3_RDATA_1 0xE88348
+
+#define mmTPC2_QM_CP_FENCE3_RDATA_2 0xE8834C
+
+#define mmTPC2_QM_CP_FENCE3_RDATA_3 0xE88350
+
+#define mmTPC2_QM_CP_FENCE3_RDATA_4 0xE88354
+
+#define mmTPC2_QM_CP_FENCE0_CNT_0 0xE88358
+
+#define mmTPC2_QM_CP_FENCE0_CNT_1 0xE8835C
+
+#define mmTPC2_QM_CP_FENCE0_CNT_2 0xE88360
+
+#define mmTPC2_QM_CP_FENCE0_CNT_3 0xE88364
+
+#define mmTPC2_QM_CP_FENCE0_CNT_4 0xE88368
+
+#define mmTPC2_QM_CP_FENCE1_CNT_0 0xE8836C
+
+#define mmTPC2_QM_CP_FENCE1_CNT_1 0xE88370
+
+#define mmTPC2_QM_CP_FENCE1_CNT_2 0xE88374
+
+#define mmTPC2_QM_CP_FENCE1_CNT_3 0xE88378
+
+#define mmTPC2_QM_CP_FENCE1_CNT_4 0xE8837C
+
+#define mmTPC2_QM_CP_FENCE2_CNT_0 0xE88380
+
+#define mmTPC2_QM_CP_FENCE2_CNT_1 0xE88384
+
+#define mmTPC2_QM_CP_FENCE2_CNT_2 0xE88388
+
+#define mmTPC2_QM_CP_FENCE2_CNT_3 0xE8838C
+
+#define mmTPC2_QM_CP_FENCE2_CNT_4 0xE88390
+
+#define mmTPC2_QM_CP_FENCE3_CNT_0 0xE88394
+
+#define mmTPC2_QM_CP_FENCE3_CNT_1 0xE88398
+
+#define mmTPC2_QM_CP_FENCE3_CNT_2 0xE8839C
+
+#define mmTPC2_QM_CP_FENCE3_CNT_3 0xE883A0
+
+#define mmTPC2_QM_CP_FENCE3_CNT_4 0xE883A4
+
+#define mmTPC2_QM_CP_STS_0 0xE883A8
+
+#define mmTPC2_QM_CP_STS_1 0xE883AC
+
+#define mmTPC2_QM_CP_STS_2 0xE883B0
+
+#define mmTPC2_QM_CP_STS_3 0xE883B4
+
+#define mmTPC2_QM_CP_STS_4 0xE883B8
+
+#define mmTPC2_QM_CP_CURRENT_INST_LO_0 0xE883BC
+
+#define mmTPC2_QM_CP_CURRENT_INST_LO_1 0xE883C0
+
+#define mmTPC2_QM_CP_CURRENT_INST_LO_2 0xE883C4
+
+#define mmTPC2_QM_CP_CURRENT_INST_LO_3 0xE883C8
+
+#define mmTPC2_QM_CP_CURRENT_INST_LO_4 0xE883CC
+
+#define mmTPC2_QM_CP_CURRENT_INST_HI_0 0xE883D0
+
+#define mmTPC2_QM_CP_CURRENT_INST_HI_1 0xE883D4
+
+#define mmTPC2_QM_CP_CURRENT_INST_HI_2 0xE883D8
+
+#define mmTPC2_QM_CP_CURRENT_INST_HI_3 0xE883DC
+
+#define mmTPC2_QM_CP_CURRENT_INST_HI_4 0xE883E0
+
+#define mmTPC2_QM_CP_BARRIER_CFG_0 0xE883F4
+
+#define mmTPC2_QM_CP_BARRIER_CFG_1 0xE883F8
+
+#define mmTPC2_QM_CP_BARRIER_CFG_2 0xE883FC
+
+#define mmTPC2_QM_CP_BARRIER_CFG_3 0xE88400
+
+#define mmTPC2_QM_CP_BARRIER_CFG_4 0xE88404
+
+#define mmTPC2_QM_CP_DBG_0_0 0xE88408
+
+#define mmTPC2_QM_CP_DBG_0_1 0xE8840C
+
+#define mmTPC2_QM_CP_DBG_0_2 0xE88410
+
+#define mmTPC2_QM_CP_DBG_0_3 0xE88414
+
+#define mmTPC2_QM_CP_DBG_0_4 0xE88418
+
+#define mmTPC2_QM_CP_ARUSER_31_11_0 0xE8841C
+
+#define mmTPC2_QM_CP_ARUSER_31_11_1 0xE88420
+
+#define mmTPC2_QM_CP_ARUSER_31_11_2 0xE88424
+
+#define mmTPC2_QM_CP_ARUSER_31_11_3 0xE88428
+
+#define mmTPC2_QM_CP_ARUSER_31_11_4 0xE8842C
+
+#define mmTPC2_QM_CP_AWUSER_31_11_0 0xE88430
+
+#define mmTPC2_QM_CP_AWUSER_31_11_1 0xE88434
+
+#define mmTPC2_QM_CP_AWUSER_31_11_2 0xE88438
+
+#define mmTPC2_QM_CP_AWUSER_31_11_3 0xE8843C
+
+#define mmTPC2_QM_CP_AWUSER_31_11_4 0xE88440
+
+#define mmTPC2_QM_ARB_CFG_0 0xE88A00
+
+#define mmTPC2_QM_ARB_CHOISE_Q_PUSH 0xE88A04
+
+#define mmTPC2_QM_ARB_WRR_WEIGHT_0 0xE88A08
+
+#define mmTPC2_QM_ARB_WRR_WEIGHT_1 0xE88A0C
+
+#define mmTPC2_QM_ARB_WRR_WEIGHT_2 0xE88A10
+
+#define mmTPC2_QM_ARB_WRR_WEIGHT_3 0xE88A14
+
+#define mmTPC2_QM_ARB_CFG_1 0xE88A18
+
+#define mmTPC2_QM_ARB_MST_AVAIL_CRED_0 0xE88A20
+
+#define mmTPC2_QM_ARB_MST_AVAIL_CRED_1 0xE88A24
+
+#define mmTPC2_QM_ARB_MST_AVAIL_CRED_2 0xE88A28
+
+#define mmTPC2_QM_ARB_MST_AVAIL_CRED_3 0xE88A2C
+
+#define mmTPC2_QM_ARB_MST_AVAIL_CRED_4 0xE88A30
+
+#define mmTPC2_QM_ARB_MST_AVAIL_CRED_5 0xE88A34
+
+#define mmTPC2_QM_ARB_MST_AVAIL_CRED_6 0xE88A38
+
+#define mmTPC2_QM_ARB_MST_AVAIL_CRED_7 0xE88A3C
+
+#define mmTPC2_QM_ARB_MST_AVAIL_CRED_8 0xE88A40
+
+#define mmTPC2_QM_ARB_MST_AVAIL_CRED_9 0xE88A44
+
+#define mmTPC2_QM_ARB_MST_AVAIL_CRED_10 0xE88A48
+
+#define mmTPC2_QM_ARB_MST_AVAIL_CRED_11 0xE88A4C
+
+#define mmTPC2_QM_ARB_MST_AVAIL_CRED_12 0xE88A50
+
+#define mmTPC2_QM_ARB_MST_AVAIL_CRED_13 0xE88A54
+
+#define mmTPC2_QM_ARB_MST_AVAIL_CRED_14 0xE88A58
+
+#define mmTPC2_QM_ARB_MST_AVAIL_CRED_15 0xE88A5C
+
+#define mmTPC2_QM_ARB_MST_AVAIL_CRED_16 0xE88A60
+
+#define mmTPC2_QM_ARB_MST_AVAIL_CRED_17 0xE88A64
+
+#define mmTPC2_QM_ARB_MST_AVAIL_CRED_18 0xE88A68
+
+#define mmTPC2_QM_ARB_MST_AVAIL_CRED_19 0xE88A6C
+
+#define mmTPC2_QM_ARB_MST_AVAIL_CRED_20 0xE88A70
+
+#define mmTPC2_QM_ARB_MST_AVAIL_CRED_21 0xE88A74
+
+#define mmTPC2_QM_ARB_MST_AVAIL_CRED_22 0xE88A78
+
+#define mmTPC2_QM_ARB_MST_AVAIL_CRED_23 0xE88A7C
+
+#define mmTPC2_QM_ARB_MST_AVAIL_CRED_24 0xE88A80
+
+#define mmTPC2_QM_ARB_MST_AVAIL_CRED_25 0xE88A84
+
+#define mmTPC2_QM_ARB_MST_AVAIL_CRED_26 0xE88A88
+
+#define mmTPC2_QM_ARB_MST_AVAIL_CRED_27 0xE88A8C
+
+#define mmTPC2_QM_ARB_MST_AVAIL_CRED_28 0xE88A90
+
+#define mmTPC2_QM_ARB_MST_AVAIL_CRED_29 0xE88A94
+
+#define mmTPC2_QM_ARB_MST_AVAIL_CRED_30 0xE88A98
+
+#define mmTPC2_QM_ARB_MST_AVAIL_CRED_31 0xE88A9C
+
+#define mmTPC2_QM_ARB_MST_CRED_INC 0xE88AA0
+
+#define mmTPC2_QM_ARB_MST_CHOISE_PUSH_OFST_0 0xE88AA4
+
+#define mmTPC2_QM_ARB_MST_CHOISE_PUSH_OFST_1 0xE88AA8
+
+#define mmTPC2_QM_ARB_MST_CHOISE_PUSH_OFST_2 0xE88AAC
+
+#define mmTPC2_QM_ARB_MST_CHOISE_PUSH_OFST_3 0xE88AB0
+
+#define mmTPC2_QM_ARB_MST_CHOISE_PUSH_OFST_4 0xE88AB4
+
+#define mmTPC2_QM_ARB_MST_CHOISE_PUSH_OFST_5 0xE88AB8
+
+#define mmTPC2_QM_ARB_MST_CHOISE_PUSH_OFST_6 0xE88ABC
+
+#define mmTPC2_QM_ARB_MST_CHOISE_PUSH_OFST_7 0xE88AC0
+
+#define mmTPC2_QM_ARB_MST_CHOISE_PUSH_OFST_8 0xE88AC4
+
+#define mmTPC2_QM_ARB_MST_CHOISE_PUSH_OFST_9 0xE88AC8
+
+#define mmTPC2_QM_ARB_MST_CHOISE_PUSH_OFST_10 0xE88ACC
+
+#define mmTPC2_QM_ARB_MST_CHOISE_PUSH_OFST_11 0xE88AD0
+
+#define mmTPC2_QM_ARB_MST_CHOISE_PUSH_OFST_12 0xE88AD4
+
+#define mmTPC2_QM_ARB_MST_CHOISE_PUSH_OFST_13 0xE88AD8
+
+#define mmTPC2_QM_ARB_MST_CHOISE_PUSH_OFST_14 0xE88ADC
+
+#define mmTPC2_QM_ARB_MST_CHOISE_PUSH_OFST_15 0xE88AE0
+
+#define mmTPC2_QM_ARB_MST_CHOISE_PUSH_OFST_16 0xE88AE4
+
+#define mmTPC2_QM_ARB_MST_CHOISE_PUSH_OFST_17 0xE88AE8
+
+#define mmTPC2_QM_ARB_MST_CHOISE_PUSH_OFST_18 0xE88AEC
+
+#define mmTPC2_QM_ARB_MST_CHOISE_PUSH_OFST_19 0xE88AF0
+
+#define mmTPC2_QM_ARB_MST_CHOISE_PUSH_OFST_20 0xE88AF4
+
+#define mmTPC2_QM_ARB_MST_CHOISE_PUSH_OFST_21 0xE88AF8
+
+#define mmTPC2_QM_ARB_MST_CHOISE_PUSH_OFST_22 0xE88AFC
+
+#define mmTPC2_QM_ARB_MST_CHOISE_PUSH_OFST_23 0xE88B00
+
+#define mmTPC2_QM_ARB_MST_CHOISE_PUSH_OFST_24 0xE88B04
+
+#define mmTPC2_QM_ARB_MST_CHOISE_PUSH_OFST_25 0xE88B08
+
+#define mmTPC2_QM_ARB_MST_CHOISE_PUSH_OFST_26 0xE88B0C
+
+#define mmTPC2_QM_ARB_MST_CHOISE_PUSH_OFST_27 0xE88B10
+
+#define mmTPC2_QM_ARB_MST_CHOISE_PUSH_OFST_28 0xE88B14
+
+#define mmTPC2_QM_ARB_MST_CHOISE_PUSH_OFST_29 0xE88B18
+
+#define mmTPC2_QM_ARB_MST_CHOISE_PUSH_OFST_30 0xE88B1C
+
+#define mmTPC2_QM_ARB_MST_CHOISE_PUSH_OFST_31 0xE88B20
+
+#define mmTPC2_QM_ARB_SLV_MASTER_INC_CRED_OFST 0xE88B28
+
+#define mmTPC2_QM_ARB_MST_SLAVE_EN 0xE88B2C
+
+#define mmTPC2_QM_ARB_MST_QUIET_PER 0xE88B34
+
+#define mmTPC2_QM_ARB_SLV_CHOISE_WDT 0xE88B38
+
+#define mmTPC2_QM_ARB_SLV_ID 0xE88B3C
+
+#define mmTPC2_QM_ARB_MSG_MAX_INFLIGHT 0xE88B44
+
+#define mmTPC2_QM_ARB_MSG_AWUSER_31_11 0xE88B48
+
+#define mmTPC2_QM_ARB_MSG_AWUSER_SEC_PROP 0xE88B4C
+
+#define mmTPC2_QM_ARB_MSG_AWUSER_NON_SEC_PROP 0xE88B50
+
+#define mmTPC2_QM_ARB_BASE_LO 0xE88B54
+
+#define mmTPC2_QM_ARB_BASE_HI 0xE88B58
+
+#define mmTPC2_QM_ARB_STATE_STS 0xE88B80
+
+#define mmTPC2_QM_ARB_CHOISE_FULLNESS_STS 0xE88B84
+
+#define mmTPC2_QM_ARB_MSG_STS 0xE88B88
+
+#define mmTPC2_QM_ARB_SLV_CHOISE_Q_HEAD 0xE88B8C
+
+#define mmTPC2_QM_ARB_ERR_CAUSE 0xE88B9C
+
+#define mmTPC2_QM_ARB_ERR_MSG_EN 0xE88BA0
+
+#define mmTPC2_QM_ARB_ERR_STS_DRP 0xE88BA8
+
+#define mmTPC2_QM_ARB_MST_CRED_STS_0 0xE88BB0
+
+#define mmTPC2_QM_ARB_MST_CRED_STS_1 0xE88BB4
+
+#define mmTPC2_QM_ARB_MST_CRED_STS_2 0xE88BB8
+
+#define mmTPC2_QM_ARB_MST_CRED_STS_3 0xE88BBC
+
+#define mmTPC2_QM_ARB_MST_CRED_STS_4 0xE88BC0
+
+#define mmTPC2_QM_ARB_MST_CRED_STS_5 0xE88BC4
+
+#define mmTPC2_QM_ARB_MST_CRED_STS_6 0xE88BC8
+
+#define mmTPC2_QM_ARB_MST_CRED_STS_7 0xE88BCC
+
+#define mmTPC2_QM_ARB_MST_CRED_STS_8 0xE88BD0
+
+#define mmTPC2_QM_ARB_MST_CRED_STS_9 0xE88BD4
+
+#define mmTPC2_QM_ARB_MST_CRED_STS_10 0xE88BD8
+
+#define mmTPC2_QM_ARB_MST_CRED_STS_11 0xE88BDC
+
+#define mmTPC2_QM_ARB_MST_CRED_STS_12 0xE88BE0
+
+#define mmTPC2_QM_ARB_MST_CRED_STS_13 0xE88BE4
+
+#define mmTPC2_QM_ARB_MST_CRED_STS_14 0xE88BE8
+
+#define mmTPC2_QM_ARB_MST_CRED_STS_15 0xE88BEC
+
+#define mmTPC2_QM_ARB_MST_CRED_STS_16 0xE88BF0
+
+#define mmTPC2_QM_ARB_MST_CRED_STS_17 0xE88BF4
+
+#define mmTPC2_QM_ARB_MST_CRED_STS_18 0xE88BF8
+
+#define mmTPC2_QM_ARB_MST_CRED_STS_19 0xE88BFC
+
+#define mmTPC2_QM_ARB_MST_CRED_STS_20 0xE88C00
+
+#define mmTPC2_QM_ARB_MST_CRED_STS_21 0xE88C04
+
+#define mmTPC2_QM_ARB_MST_CRED_STS_22 0xE88C08
+
+#define mmTPC2_QM_ARB_MST_CRED_STS_23 0xE88C0C
+
+#define mmTPC2_QM_ARB_MST_CRED_STS_24 0xE88C10
+
+#define mmTPC2_QM_ARB_MST_CRED_STS_25 0xE88C14
+
+#define mmTPC2_QM_ARB_MST_CRED_STS_26 0xE88C18
+
+#define mmTPC2_QM_ARB_MST_CRED_STS_27 0xE88C1C
+
+#define mmTPC2_QM_ARB_MST_CRED_STS_28 0xE88C20
+
+#define mmTPC2_QM_ARB_MST_CRED_STS_29 0xE88C24
+
+#define mmTPC2_QM_ARB_MST_CRED_STS_30 0xE88C28
+
+#define mmTPC2_QM_ARB_MST_CRED_STS_31 0xE88C2C
+
+#define mmTPC2_QM_CGM_CFG 0xE88C70
+
+#define mmTPC2_QM_CGM_STS 0xE88C74
+
+#define mmTPC2_QM_CGM_CFG1 0xE88C78
+
+#define mmTPC2_QM_LOCAL_RANGE_BASE 0xE88C80
+
+#define mmTPC2_QM_LOCAL_RANGE_SIZE 0xE88C84
+
+#define mmTPC2_QM_CSMR_STRICT_PRIO_CFG 0xE88C90
+
+#define mmTPC2_QM_HBW_RD_RATE_LIM_CFG_1 0xE88C94
+
+#define mmTPC2_QM_LBW_WR_RATE_LIM_CFG_0 0xE88C98
+
+#define mmTPC2_QM_LBW_WR_RATE_LIM_CFG_1 0xE88C9C
+
+#define mmTPC2_QM_HBW_RD_RATE_LIM_CFG_0 0xE88CA0
+
+#define mmTPC2_QM_GLBL_AXCACHE 0xE88CA4
+
+#define mmTPC2_QM_IND_GW_APB_CFG 0xE88CB0
+
+#define mmTPC2_QM_IND_GW_APB_WDATA 0xE88CB4
+
+#define mmTPC2_QM_IND_GW_APB_RDATA 0xE88CB8
+
+#define mmTPC2_QM_IND_GW_APB_STATUS 0xE88CBC
+
+#define mmTPC2_QM_GLBL_ERR_ADDR_LO 0xE88CD0
+
+#define mmTPC2_QM_GLBL_ERR_ADDR_HI 0xE88CD4
+
+#define mmTPC2_QM_GLBL_ERR_WDATA 0xE88CD8
+
+#define mmTPC2_QM_GLBL_MEM_INIT_BUSY 0xE88D00
+
+#endif /* ASIC_REG_TPC2_QM_REGS_H_ */
diff --git a/drivers/accel/habanalabs/include/gaudi/asic_reg/tpc3_cfg_regs.h b/drivers/accel/habanalabs/include/gaudi/asic_reg/tpc3_cfg_regs.h
new file mode 100644
index 0000000000..6d42469659
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi/asic_reg/tpc3_cfg_regs.h
@@ -0,0 +1,1226 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2016-2018 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ ** DO NOT EDIT BELOW **
+ ************************************/
+
+#ifndef ASIC_REG_TPC3_CFG_REGS_H_
+#define ASIC_REG_TPC3_CFG_REGS_H_
+
+/*
+ *****************************************
+ * TPC3_CFG (Prototype: TPC)
+ *****************************************
+ */
+
+#define mmTPC3_CFG_KERNEL_TENSOR_0_BASE_ADDR_LOW 0xEC6400
+
+#define mmTPC3_CFG_KERNEL_TENSOR_0_BASE_ADDR_HIGH 0xEC6404
+
+#define mmTPC3_CFG_KERNEL_TENSOR_0_PADDING_VALUE 0xEC6408
+
+#define mmTPC3_CFG_KERNEL_TENSOR_0_TENSOR_CONFIG 0xEC640C
+
+#define mmTPC3_CFG_KERNEL_TENSOR_0_DIM_0_SIZE 0xEC6410
+
+#define mmTPC3_CFG_KERNEL_TENSOR_0_DIM_0_STRIDE 0xEC6414
+
+#define mmTPC3_CFG_KERNEL_TENSOR_0_DIM_1_SIZE 0xEC6418
+
+#define mmTPC3_CFG_KERNEL_TENSOR_0_DIM_1_STRIDE 0xEC641C
+
+#define mmTPC3_CFG_KERNEL_TENSOR_0_DIM_2_SIZE 0xEC6420
+
+#define mmTPC3_CFG_KERNEL_TENSOR_0_DIM_2_STRIDE 0xEC6424
+
+#define mmTPC3_CFG_KERNEL_TENSOR_0_DIM_3_SIZE 0xEC6428
+
+#define mmTPC3_CFG_KERNEL_TENSOR_0_DIM_3_STRIDE 0xEC642C
+
+#define mmTPC3_CFG_KERNEL_TENSOR_0_DIM_4_SIZE 0xEC6430
+
+#define mmTPC3_CFG_KERNEL_TENSOR_0_DIM_4_STRIDE 0xEC6434
+
+#define mmTPC3_CFG_KERNEL_TENSOR_1_BASE_ADDR_LOW 0xEC6438
+
+#define mmTPC3_CFG_KERNEL_TENSOR_1_BASE_ADDR_HIGH 0xEC643C
+
+#define mmTPC3_CFG_KERNEL_TENSOR_1_PADDING_VALUE 0xEC6440
+
+#define mmTPC3_CFG_KERNEL_TENSOR_1_TENSOR_CONFIG 0xEC6444
+
+#define mmTPC3_CFG_KERNEL_TENSOR_1_DIM_0_SIZE 0xEC6448
+
+#define mmTPC3_CFG_KERNEL_TENSOR_1_DIM_0_STRIDE 0xEC644C
+
+#define mmTPC3_CFG_KERNEL_TENSOR_1_DIM_1_SIZE 0xEC6450
+
+#define mmTPC3_CFG_KERNEL_TENSOR_1_DIM_1_STRIDE 0xEC6454
+
+#define mmTPC3_CFG_KERNEL_TENSOR_1_DIM_2_SIZE 0xEC6458
+
+#define mmTPC3_CFG_KERNEL_TENSOR_1_DIM_2_STRIDE 0xEC645C
+
+#define mmTPC3_CFG_KERNEL_TENSOR_1_DIM_3_SIZE 0xEC6460
+
+#define mmTPC3_CFG_KERNEL_TENSOR_1_DIM_3_STRIDE 0xEC6464
+
+#define mmTPC3_CFG_KERNEL_TENSOR_1_DIM_4_SIZE 0xEC6468
+
+#define mmTPC3_CFG_KERNEL_TENSOR_1_DIM_4_STRIDE 0xEC646C
+
+#define mmTPC3_CFG_KERNEL_TENSOR_2_BASE_ADDR_LOW 0xEC6470
+
+#define mmTPC3_CFG_KERNEL_TENSOR_2_BASE_ADDR_HIGH 0xEC6474
+
+#define mmTPC3_CFG_KERNEL_TENSOR_2_PADDING_VALUE 0xEC6478
+
+#define mmTPC3_CFG_KERNEL_TENSOR_2_TENSOR_CONFIG 0xEC647C
+
+#define mmTPC3_CFG_KERNEL_TENSOR_2_DIM_0_SIZE 0xEC6480
+
+#define mmTPC3_CFG_KERNEL_TENSOR_2_DIM_0_STRIDE 0xEC6484
+
+#define mmTPC3_CFG_KERNEL_TENSOR_2_DIM_1_SIZE 0xEC6488
+
+#define mmTPC3_CFG_KERNEL_TENSOR_2_DIM_1_STRIDE 0xEC648C
+
+#define mmTPC3_CFG_KERNEL_TENSOR_2_DIM_2_SIZE 0xEC6490
+
+#define mmTPC3_CFG_KERNEL_TENSOR_2_DIM_2_STRIDE 0xEC6494
+
+#define mmTPC3_CFG_KERNEL_TENSOR_2_DIM_3_SIZE 0xEC6498
+
+#define mmTPC3_CFG_KERNEL_TENSOR_2_DIM_3_STRIDE 0xEC649C
+
+#define mmTPC3_CFG_KERNEL_TENSOR_2_DIM_4_SIZE 0xEC64A0
+
+#define mmTPC3_CFG_KERNEL_TENSOR_2_DIM_4_STRIDE 0xEC64A4
+
+#define mmTPC3_CFG_KERNEL_TENSOR_3_BASE_ADDR_LOW 0xEC64A8
+
+#define mmTPC3_CFG_KERNEL_TENSOR_3_BASE_ADDR_HIGH 0xEC64AC
+
+#define mmTPC3_CFG_KERNEL_TENSOR_3_PADDING_VALUE 0xEC64B0
+
+#define mmTPC3_CFG_KERNEL_TENSOR_3_TENSOR_CONFIG 0xEC64B4
+
+#define mmTPC3_CFG_KERNEL_TENSOR_3_DIM_0_SIZE 0xEC64B8
+
+#define mmTPC3_CFG_KERNEL_TENSOR_3_DIM_0_STRIDE 0xEC64BC
+
+#define mmTPC3_CFG_KERNEL_TENSOR_3_DIM_1_SIZE 0xEC64C0
+
+#define mmTPC3_CFG_KERNEL_TENSOR_3_DIM_1_STRIDE 0xEC64C4
+
+#define mmTPC3_CFG_KERNEL_TENSOR_3_DIM_2_SIZE 0xEC64C8
+
+#define mmTPC3_CFG_KERNEL_TENSOR_3_DIM_2_STRIDE 0xEC64CC
+
+#define mmTPC3_CFG_KERNEL_TENSOR_3_DIM_3_SIZE 0xEC64D0
+
+#define mmTPC3_CFG_KERNEL_TENSOR_3_DIM_3_STRIDE 0xEC64D4
+
+#define mmTPC3_CFG_KERNEL_TENSOR_3_DIM_4_SIZE 0xEC64D8
+
+#define mmTPC3_CFG_KERNEL_TENSOR_3_DIM_4_STRIDE 0xEC64DC
+
+#define mmTPC3_CFG_KERNEL_TENSOR_4_BASE_ADDR_LOW 0xEC64E0
+
+#define mmTPC3_CFG_KERNEL_TENSOR_4_BASE_ADDR_HIGH 0xEC64E4
+
+#define mmTPC3_CFG_KERNEL_TENSOR_4_PADDING_VALUE 0xEC64E8
+
+#define mmTPC3_CFG_KERNEL_TENSOR_4_TENSOR_CONFIG 0xEC64EC
+
+#define mmTPC3_CFG_KERNEL_TENSOR_4_DIM_0_SIZE 0xEC64F0
+
+#define mmTPC3_CFG_KERNEL_TENSOR_4_DIM_0_STRIDE 0xEC64F4
+
+#define mmTPC3_CFG_KERNEL_TENSOR_4_DIM_1_SIZE 0xEC64F8
+
+#define mmTPC3_CFG_KERNEL_TENSOR_4_DIM_1_STRIDE 0xEC64FC
+
+#define mmTPC3_CFG_KERNEL_TENSOR_4_DIM_2_SIZE 0xEC6500
+
+#define mmTPC3_CFG_KERNEL_TENSOR_4_DIM_2_STRIDE 0xEC6504
+
+#define mmTPC3_CFG_KERNEL_TENSOR_4_DIM_3_SIZE 0xEC6508
+
+#define mmTPC3_CFG_KERNEL_TENSOR_4_DIM_3_STRIDE 0xEC650C
+
+#define mmTPC3_CFG_KERNEL_TENSOR_4_DIM_4_SIZE 0xEC6510
+
+#define mmTPC3_CFG_KERNEL_TENSOR_4_DIM_4_STRIDE 0xEC6514
+
+#define mmTPC3_CFG_KERNEL_TENSOR_5_BASE_ADDR_LOW 0xEC6518
+
+#define mmTPC3_CFG_KERNEL_TENSOR_5_BASE_ADDR_HIGH 0xEC651C
+
+#define mmTPC3_CFG_KERNEL_TENSOR_5_PADDING_VALUE 0xEC6520
+
+#define mmTPC3_CFG_KERNEL_TENSOR_5_TENSOR_CONFIG 0xEC6524
+
+#define mmTPC3_CFG_KERNEL_TENSOR_5_DIM_0_SIZE 0xEC6528
+
+#define mmTPC3_CFG_KERNEL_TENSOR_5_DIM_0_STRIDE 0xEC652C
+
+#define mmTPC3_CFG_KERNEL_TENSOR_5_DIM_1_SIZE 0xEC6530
+
+#define mmTPC3_CFG_KERNEL_TENSOR_5_DIM_1_STRIDE 0xEC6534
+
+#define mmTPC3_CFG_KERNEL_TENSOR_5_DIM_2_SIZE 0xEC6538
+
+#define mmTPC3_CFG_KERNEL_TENSOR_5_DIM_2_STRIDE 0xEC653C
+
+#define mmTPC3_CFG_KERNEL_TENSOR_5_DIM_3_SIZE 0xEC6540
+
+#define mmTPC3_CFG_KERNEL_TENSOR_5_DIM_3_STRIDE 0xEC6544
+
+#define mmTPC3_CFG_KERNEL_TENSOR_5_DIM_4_SIZE 0xEC6548
+
+#define mmTPC3_CFG_KERNEL_TENSOR_5_DIM_4_STRIDE 0xEC654C
+
+#define mmTPC3_CFG_KERNEL_TENSOR_6_BASE_ADDR_LOW 0xEC6550
+
+#define mmTPC3_CFG_KERNEL_TENSOR_6_BASE_ADDR_HIGH 0xEC6554
+
+#define mmTPC3_CFG_KERNEL_TENSOR_6_PADDING_VALUE 0xEC6558
+
+#define mmTPC3_CFG_KERNEL_TENSOR_6_TENSOR_CONFIG 0xEC655C
+
+#define mmTPC3_CFG_KERNEL_TENSOR_6_DIM_0_SIZE 0xEC6560
+
+#define mmTPC3_CFG_KERNEL_TENSOR_6_DIM_0_STRIDE 0xEC6564
+
+#define mmTPC3_CFG_KERNEL_TENSOR_6_DIM_1_SIZE 0xEC6568
+
+#define mmTPC3_CFG_KERNEL_TENSOR_6_DIM_1_STRIDE 0xEC656C
+
+#define mmTPC3_CFG_KERNEL_TENSOR_6_DIM_2_SIZE 0xEC6570
+
+#define mmTPC3_CFG_KERNEL_TENSOR_6_DIM_2_STRIDE 0xEC6574
+
+#define mmTPC3_CFG_KERNEL_TENSOR_6_DIM_3_SIZE 0xEC6578
+
+#define mmTPC3_CFG_KERNEL_TENSOR_6_DIM_3_STRIDE 0xEC657C
+
+#define mmTPC3_CFG_KERNEL_TENSOR_6_DIM_4_SIZE 0xEC6580
+
+#define mmTPC3_CFG_KERNEL_TENSOR_6_DIM_4_STRIDE 0xEC6584
+
+#define mmTPC3_CFG_KERNEL_TENSOR_7_BASE_ADDR_LOW 0xEC6588
+
+#define mmTPC3_CFG_KERNEL_TENSOR_7_BASE_ADDR_HIGH 0xEC658C
+
+#define mmTPC3_CFG_KERNEL_TENSOR_7_PADDING_VALUE 0xEC6590
+
+#define mmTPC3_CFG_KERNEL_TENSOR_7_TENSOR_CONFIG 0xEC6594
+
+#define mmTPC3_CFG_KERNEL_TENSOR_7_DIM_0_SIZE 0xEC6598
+
+#define mmTPC3_CFG_KERNEL_TENSOR_7_DIM_0_STRIDE 0xEC659C
+
+#define mmTPC3_CFG_KERNEL_TENSOR_7_DIM_1_SIZE 0xEC65A0
+
+#define mmTPC3_CFG_KERNEL_TENSOR_7_DIM_1_STRIDE 0xEC65A4
+
+#define mmTPC3_CFG_KERNEL_TENSOR_7_DIM_2_SIZE 0xEC65A8
+
+#define mmTPC3_CFG_KERNEL_TENSOR_7_DIM_2_STRIDE 0xEC65AC
+
+#define mmTPC3_CFG_KERNEL_TENSOR_7_DIM_3_SIZE 0xEC65B0
+
+#define mmTPC3_CFG_KERNEL_TENSOR_7_DIM_3_STRIDE 0xEC65B4
+
+#define mmTPC3_CFG_KERNEL_TENSOR_7_DIM_4_SIZE 0xEC65B8
+
+#define mmTPC3_CFG_KERNEL_TENSOR_7_DIM_4_STRIDE 0xEC65BC
+
+#define mmTPC3_CFG_KERNEL_TENSOR_8_BASE_ADDR_LOW 0xEC65C0
+
+#define mmTPC3_CFG_KERNEL_TENSOR_8_BASE_ADDR_HIGH 0xEC65C4
+
+#define mmTPC3_CFG_KERNEL_TENSOR_8_PADDING_VALUE 0xEC65C8
+
+#define mmTPC3_CFG_KERNEL_TENSOR_8_TENSOR_CONFIG 0xEC65CC
+
+#define mmTPC3_CFG_KERNEL_TENSOR_8_DIM_0_SIZE 0xEC65D0
+
+#define mmTPC3_CFG_KERNEL_TENSOR_8_DIM_0_STRIDE 0xEC65D4
+
+#define mmTPC3_CFG_KERNEL_TENSOR_8_DIM_1_SIZE 0xEC65D8
+
+#define mmTPC3_CFG_KERNEL_TENSOR_8_DIM_1_STRIDE 0xEC65DC
+
+#define mmTPC3_CFG_KERNEL_TENSOR_8_DIM_2_SIZE 0xEC65E0
+
+#define mmTPC3_CFG_KERNEL_TENSOR_8_DIM_2_STRIDE 0xEC65E4
+
+#define mmTPC3_CFG_KERNEL_TENSOR_8_DIM_3_SIZE 0xEC65E8
+
+#define mmTPC3_CFG_KERNEL_TENSOR_8_DIM_3_STRIDE 0xEC65EC
+
+#define mmTPC3_CFG_KERNEL_TENSOR_8_DIM_4_SIZE 0xEC65F0
+
+#define mmTPC3_CFG_KERNEL_TENSOR_8_DIM_4_STRIDE 0xEC65F4
+
+#define mmTPC3_CFG_KERNEL_TENSOR_9_BASE_ADDR_LOW 0xEC65F8
+
+#define mmTPC3_CFG_KERNEL_TENSOR_9_BASE_ADDR_HIGH 0xEC65FC
+
+#define mmTPC3_CFG_KERNEL_TENSOR_9_PADDING_VALUE 0xEC6600
+
+#define mmTPC3_CFG_KERNEL_TENSOR_9_TENSOR_CONFIG 0xEC6604
+
+#define mmTPC3_CFG_KERNEL_TENSOR_9_DIM_0_SIZE 0xEC6608
+
+#define mmTPC3_CFG_KERNEL_TENSOR_9_DIM_0_STRIDE 0xEC660C
+
+#define mmTPC3_CFG_KERNEL_TENSOR_9_DIM_1_SIZE 0xEC6610
+
+#define mmTPC3_CFG_KERNEL_TENSOR_9_DIM_1_STRIDE 0xEC6614
+
+#define mmTPC3_CFG_KERNEL_TENSOR_9_DIM_2_SIZE 0xEC6618
+
+#define mmTPC3_CFG_KERNEL_TENSOR_9_DIM_2_STRIDE 0xEC661C
+
+#define mmTPC3_CFG_KERNEL_TENSOR_9_DIM_3_SIZE 0xEC6620
+
+#define mmTPC3_CFG_KERNEL_TENSOR_9_DIM_3_STRIDE 0xEC6624
+
+#define mmTPC3_CFG_KERNEL_TENSOR_9_DIM_4_SIZE 0xEC6628
+
+#define mmTPC3_CFG_KERNEL_TENSOR_9_DIM_4_STRIDE 0xEC662C
+
+#define mmTPC3_CFG_KERNEL_TENSOR_10_BASE_ADDR_LOW 0xEC6630
+
+#define mmTPC3_CFG_KERNEL_TENSOR_10_BASE_ADDR_HIGH 0xEC6634
+
+#define mmTPC3_CFG_KERNEL_TENSOR_10_PADDING_VALUE 0xEC6638
+
+#define mmTPC3_CFG_KERNEL_TENSOR_10_TENSOR_CONFIG 0xEC663C
+
+#define mmTPC3_CFG_KERNEL_TENSOR_10_DIM_0_SIZE 0xEC6640
+
+#define mmTPC3_CFG_KERNEL_TENSOR_10_DIM_0_STRIDE 0xEC6644
+
+#define mmTPC3_CFG_KERNEL_TENSOR_10_DIM_1_SIZE 0xEC6648
+
+#define mmTPC3_CFG_KERNEL_TENSOR_10_DIM_1_STRIDE 0xEC664C
+
+#define mmTPC3_CFG_KERNEL_TENSOR_10_DIM_2_SIZE 0xEC6650
+
+#define mmTPC3_CFG_KERNEL_TENSOR_10_DIM_2_STRIDE 0xEC6654
+
+#define mmTPC3_CFG_KERNEL_TENSOR_10_DIM_3_SIZE 0xEC6658
+
+#define mmTPC3_CFG_KERNEL_TENSOR_10_DIM_3_STRIDE 0xEC665C
+
+#define mmTPC3_CFG_KERNEL_TENSOR_10_DIM_4_SIZE 0xEC6660
+
+#define mmTPC3_CFG_KERNEL_TENSOR_10_DIM_4_STRIDE 0xEC6664
+
+#define mmTPC3_CFG_KERNEL_TENSOR_11_BASE_ADDR_LOW 0xEC6668
+
+#define mmTPC3_CFG_KERNEL_TENSOR_11_BASE_ADDR_HIGH 0xEC666C
+
+#define mmTPC3_CFG_KERNEL_TENSOR_11_PADDING_VALUE 0xEC6670
+
+#define mmTPC3_CFG_KERNEL_TENSOR_11_TENSOR_CONFIG 0xEC6674
+
+#define mmTPC3_CFG_KERNEL_TENSOR_11_DIM_0_SIZE 0xEC6678
+
+#define mmTPC3_CFG_KERNEL_TENSOR_11_DIM_0_STRIDE 0xEC667C
+
+#define mmTPC3_CFG_KERNEL_TENSOR_11_DIM_1_SIZE 0xEC6680
+
+#define mmTPC3_CFG_KERNEL_TENSOR_11_DIM_1_STRIDE 0xEC6684
+
+#define mmTPC3_CFG_KERNEL_TENSOR_11_DIM_2_SIZE 0xEC6688
+
+#define mmTPC3_CFG_KERNEL_TENSOR_11_DIM_2_STRIDE 0xEC668C
+
+#define mmTPC3_CFG_KERNEL_TENSOR_11_DIM_3_SIZE 0xEC6690
+
+#define mmTPC3_CFG_KERNEL_TENSOR_11_DIM_3_STRIDE 0xEC6694
+
+#define mmTPC3_CFG_KERNEL_TENSOR_11_DIM_4_SIZE 0xEC6698
+
+#define mmTPC3_CFG_KERNEL_TENSOR_11_DIM_4_STRIDE 0xEC669C
+
+#define mmTPC3_CFG_KERNEL_TENSOR_12_BASE_ADDR_LOW 0xEC66A0
+
+#define mmTPC3_CFG_KERNEL_TENSOR_12_BASE_ADDR_HIGH 0xEC66A4
+
+#define mmTPC3_CFG_KERNEL_TENSOR_12_PADDING_VALUE 0xEC66A8
+
+#define mmTPC3_CFG_KERNEL_TENSOR_12_TENSOR_CONFIG 0xEC66AC
+
+#define mmTPC3_CFG_KERNEL_TENSOR_12_DIM_0_SIZE 0xEC66B0
+
+#define mmTPC3_CFG_KERNEL_TENSOR_12_DIM_0_STRIDE 0xEC66B4
+
+#define mmTPC3_CFG_KERNEL_TENSOR_12_DIM_1_SIZE 0xEC66B8
+
+#define mmTPC3_CFG_KERNEL_TENSOR_12_DIM_1_STRIDE 0xEC66BC
+
+#define mmTPC3_CFG_KERNEL_TENSOR_12_DIM_2_SIZE 0xEC66C0
+
+#define mmTPC3_CFG_KERNEL_TENSOR_12_DIM_2_STRIDE 0xEC66C4
+
+#define mmTPC3_CFG_KERNEL_TENSOR_12_DIM_3_SIZE 0xEC66C8
+
+#define mmTPC3_CFG_KERNEL_TENSOR_12_DIM_3_STRIDE 0xEC66CC
+
+#define mmTPC3_CFG_KERNEL_TENSOR_12_DIM_4_SIZE 0xEC66D0
+
+#define mmTPC3_CFG_KERNEL_TENSOR_12_DIM_4_STRIDE 0xEC66D4
+
+#define mmTPC3_CFG_KERNEL_TENSOR_13_BASE_ADDR_LOW 0xEC66D8
+
+#define mmTPC3_CFG_KERNEL_TENSOR_13_BASE_ADDR_HIGH 0xEC66DC
+
+#define mmTPC3_CFG_KERNEL_TENSOR_13_PADDING_VALUE 0xEC66E0
+
+#define mmTPC3_CFG_KERNEL_TENSOR_13_TENSOR_CONFIG 0xEC66E4
+
+#define mmTPC3_CFG_KERNEL_TENSOR_13_DIM_0_SIZE 0xEC66E8
+
+#define mmTPC3_CFG_KERNEL_TENSOR_13_DIM_0_STRIDE 0xEC66EC
+
+#define mmTPC3_CFG_KERNEL_TENSOR_13_DIM_1_SIZE 0xEC66F0
+
+#define mmTPC3_CFG_KERNEL_TENSOR_13_DIM_1_STRIDE 0xEC66F4
+
+#define mmTPC3_CFG_KERNEL_TENSOR_13_DIM_2_SIZE 0xEC66F8
+
+#define mmTPC3_CFG_KERNEL_TENSOR_13_DIM_2_STRIDE 0xEC66FC
+
+#define mmTPC3_CFG_KERNEL_TENSOR_13_DIM_3_SIZE 0xEC6700
+
+#define mmTPC3_CFG_KERNEL_TENSOR_13_DIM_3_STRIDE 0xEC6704
+
+#define mmTPC3_CFG_KERNEL_TENSOR_13_DIM_4_SIZE 0xEC6708
+
+#define mmTPC3_CFG_KERNEL_TENSOR_13_DIM_4_STRIDE 0xEC670C
+
+#define mmTPC3_CFG_KERNEL_TENSOR_14_BASE_ADDR_LOW 0xEC6710
+
+#define mmTPC3_CFG_KERNEL_TENSOR_14_BASE_ADDR_HIGH 0xEC6714
+
+#define mmTPC3_CFG_KERNEL_TENSOR_14_PADDING_VALUE 0xEC6718
+
+#define mmTPC3_CFG_KERNEL_TENSOR_14_TENSOR_CONFIG 0xEC671C
+
+#define mmTPC3_CFG_KERNEL_TENSOR_14_DIM_0_SIZE 0xEC6720
+
+#define mmTPC3_CFG_KERNEL_TENSOR_14_DIM_0_STRIDE 0xEC6724
+
+#define mmTPC3_CFG_KERNEL_TENSOR_14_DIM_1_SIZE 0xEC6728
+
+#define mmTPC3_CFG_KERNEL_TENSOR_14_DIM_1_STRIDE 0xEC672C
+
+#define mmTPC3_CFG_KERNEL_TENSOR_14_DIM_2_SIZE 0xEC6730
+
+#define mmTPC3_CFG_KERNEL_TENSOR_14_DIM_2_STRIDE 0xEC6734
+
+#define mmTPC3_CFG_KERNEL_TENSOR_14_DIM_3_SIZE 0xEC6738
+
+#define mmTPC3_CFG_KERNEL_TENSOR_14_DIM_3_STRIDE 0xEC673C
+
+#define mmTPC3_CFG_KERNEL_TENSOR_14_DIM_4_SIZE 0xEC6740
+
+#define mmTPC3_CFG_KERNEL_TENSOR_14_DIM_4_STRIDE 0xEC6744
+
+#define mmTPC3_CFG_KERNEL_TENSOR_15_BASE_ADDR_LOW 0xEC6748
+
+#define mmTPC3_CFG_KERNEL_TENSOR_15_BASE_ADDR_HIGH 0xEC674C
+
+#define mmTPC3_CFG_KERNEL_TENSOR_15_PADDING_VALUE 0xEC6750
+
+#define mmTPC3_CFG_KERNEL_TENSOR_15_TENSOR_CONFIG 0xEC6754
+
+#define mmTPC3_CFG_KERNEL_TENSOR_15_DIM_0_SIZE 0xEC6758
+
+#define mmTPC3_CFG_KERNEL_TENSOR_15_DIM_0_STRIDE 0xEC675C
+
+#define mmTPC3_CFG_KERNEL_TENSOR_15_DIM_1_SIZE 0xEC6760
+
+#define mmTPC3_CFG_KERNEL_TENSOR_15_DIM_1_STRIDE 0xEC6764
+
+#define mmTPC3_CFG_KERNEL_TENSOR_15_DIM_2_SIZE 0xEC6768
+
+#define mmTPC3_CFG_KERNEL_TENSOR_15_DIM_2_STRIDE 0xEC676C
+
+#define mmTPC3_CFG_KERNEL_TENSOR_15_DIM_3_SIZE 0xEC6770
+
+#define mmTPC3_CFG_KERNEL_TENSOR_15_DIM_3_STRIDE 0xEC6774
+
+#define mmTPC3_CFG_KERNEL_TENSOR_15_DIM_4_SIZE 0xEC6778
+
+#define mmTPC3_CFG_KERNEL_TENSOR_15_DIM_4_STRIDE 0xEC677C
+
+#define mmTPC3_CFG_KERNEL_SYNC_OBJECT_MESSAGE 0xEC6780
+
+#define mmTPC3_CFG_KERNEL_SYNC_OBJECT_ADDR 0xEC6784
+
+#define mmTPC3_CFG_KERNEL_KERNEL_BASE_ADDRESS_LOW 0xEC6788
+
+#define mmTPC3_CFG_KERNEL_KERNEL_BASE_ADDRESS_HIGH 0xEC678C
+
+#define mmTPC3_CFG_KERNEL_TID_BASE_DIM_0 0xEC6790
+
+#define mmTPC3_CFG_KERNEL_TID_SIZE_DIM_0 0xEC6794
+
+#define mmTPC3_CFG_KERNEL_TID_BASE_DIM_1 0xEC6798
+
+#define mmTPC3_CFG_KERNEL_TID_SIZE_DIM_1 0xEC679C
+
+#define mmTPC3_CFG_KERNEL_TID_BASE_DIM_2 0xEC67A0
+
+#define mmTPC3_CFG_KERNEL_TID_SIZE_DIM_2 0xEC67A4
+
+#define mmTPC3_CFG_KERNEL_TID_BASE_DIM_3 0xEC67A8
+
+#define mmTPC3_CFG_KERNEL_TID_SIZE_DIM_3 0xEC67AC
+
+#define mmTPC3_CFG_KERNEL_TID_BASE_DIM_4 0xEC67B0
+
+#define mmTPC3_CFG_KERNEL_TID_SIZE_DIM_4 0xEC67B4
+
+#define mmTPC3_CFG_KERNEL_KERNEL_CONFIG 0xEC67B8
+
+#define mmTPC3_CFG_KERNEL_KERNEL_ID 0xEC67BC
+
+#define mmTPC3_CFG_KERNEL_SRF_0 0xEC67C0
+
+#define mmTPC3_CFG_KERNEL_SRF_1 0xEC67C4
+
+#define mmTPC3_CFG_KERNEL_SRF_2 0xEC67C8
+
+#define mmTPC3_CFG_KERNEL_SRF_3 0xEC67CC
+
+#define mmTPC3_CFG_KERNEL_SRF_4 0xEC67D0
+
+#define mmTPC3_CFG_KERNEL_SRF_5 0xEC67D4
+
+#define mmTPC3_CFG_KERNEL_SRF_6 0xEC67D8
+
+#define mmTPC3_CFG_KERNEL_SRF_7 0xEC67DC
+
+#define mmTPC3_CFG_KERNEL_SRF_8 0xEC67E0
+
+#define mmTPC3_CFG_KERNEL_SRF_9 0xEC67E4
+
+#define mmTPC3_CFG_KERNEL_SRF_10 0xEC67E8
+
+#define mmTPC3_CFG_KERNEL_SRF_11 0xEC67EC
+
+#define mmTPC3_CFG_KERNEL_SRF_12 0xEC67F0
+
+#define mmTPC3_CFG_KERNEL_SRF_13 0xEC67F4
+
+#define mmTPC3_CFG_KERNEL_SRF_14 0xEC67F8
+
+#define mmTPC3_CFG_KERNEL_SRF_15 0xEC67FC
+
+#define mmTPC3_CFG_KERNEL_SRF_16 0xEC6800
+
+#define mmTPC3_CFG_KERNEL_SRF_17 0xEC6804
+
+#define mmTPC3_CFG_KERNEL_SRF_18 0xEC6808
+
+#define mmTPC3_CFG_KERNEL_SRF_19 0xEC680C
+
+#define mmTPC3_CFG_KERNEL_SRF_20 0xEC6810
+
+#define mmTPC3_CFG_KERNEL_SRF_21 0xEC6814
+
+#define mmTPC3_CFG_KERNEL_SRF_22 0xEC6818
+
+#define mmTPC3_CFG_KERNEL_SRF_23 0xEC681C
+
+#define mmTPC3_CFG_KERNEL_SRF_24 0xEC6820
+
+#define mmTPC3_CFG_KERNEL_SRF_25 0xEC6824
+
+#define mmTPC3_CFG_KERNEL_SRF_26 0xEC6828
+
+#define mmTPC3_CFG_KERNEL_SRF_27 0xEC682C
+
+#define mmTPC3_CFG_KERNEL_SRF_28 0xEC6830
+
+#define mmTPC3_CFG_KERNEL_SRF_29 0xEC6834
+
+#define mmTPC3_CFG_KERNEL_SRF_30 0xEC6838
+
+#define mmTPC3_CFG_KERNEL_SRF_31 0xEC683C
+
+#define mmTPC3_CFG_ROUND_CSR 0xEC68FC
+
+#define mmTPC3_CFG_PROT 0xEC6900
+
+#define mmTPC3_CFG_SEMAPHORE 0xEC6908
+
+#define mmTPC3_CFG_VFLAGS 0xEC690C
+
+#define mmTPC3_CFG_SFLAGS 0xEC6910
+
+#define mmTPC3_CFG_LFSR_POLYNOM 0xEC6918
+
+#define mmTPC3_CFG_STATUS 0xEC691C
+
+#define mmTPC3_CFG_CFG_BASE_ADDRESS_HIGH 0xEC6920
+
+#define mmTPC3_CFG_CFG_SUBTRACT_VALUE 0xEC6924
+
+#define mmTPC3_CFG_SM_BASE_ADDRESS_HIGH 0xEC692C
+
+#define mmTPC3_CFG_TPC_CMD 0xEC6930
+
+#define mmTPC3_CFG_TPC_EXECUTE 0xEC6938
+
+#define mmTPC3_CFG_TPC_STALL 0xEC693C
+
+#define mmTPC3_CFG_ICACHE_BASE_ADDERESS_LOW 0xEC6940
+
+#define mmTPC3_CFG_ICACHE_BASE_ADDERESS_HIGH 0xEC6944
+
+#define mmTPC3_CFG_RD_RATE_LIMIT 0xEC6948
+
+#define mmTPC3_CFG_WR_RATE_LIMIT 0xEC6950
+
+#define mmTPC3_CFG_MSS_CONFIG 0xEC6954
+
+#define mmTPC3_CFG_TPC_INTR_CAUSE 0xEC6958
+
+#define mmTPC3_CFG_TPC_INTR_MASK 0xEC695C
+
+#define mmTPC3_CFG_WQ_CREDITS 0xEC6960
+
+#define mmTPC3_CFG_ARUSER_LO 0xEC6964
+
+#define mmTPC3_CFG_ARUSER_HI 0xEC6968
+
+#define mmTPC3_CFG_AWUSER_LO 0xEC696C
+
+#define mmTPC3_CFG_AWUSER_HI 0xEC6970
+
+#define mmTPC3_CFG_OPCODE_EXEC 0xEC6974
+
+#define mmTPC3_CFG_LUT_FUNC32_BASE_ADDR_LO 0xEC6978
+
+#define mmTPC3_CFG_LUT_FUNC32_BASE_ADDR_HI 0xEC697C
+
+#define mmTPC3_CFG_LUT_FUNC64_BASE_ADDR_LO 0xEC6980
+
+#define mmTPC3_CFG_LUT_FUNC64_BASE_ADDR_HI 0xEC6984
+
+#define mmTPC3_CFG_LUT_FUNC128_BASE_ADDR_LO 0xEC6988
+
+#define mmTPC3_CFG_LUT_FUNC128_BASE_ADDR_HI 0xEC698C
+
+#define mmTPC3_CFG_LUT_FUNC256_BASE_ADDR_LO 0xEC6990
+
+#define mmTPC3_CFG_LUT_FUNC256_BASE_ADDR_HI 0xEC6994
+
+#define mmTPC3_CFG_TSB_CFG_MAX_SIZE 0xEC6998
+
+#define mmTPC3_CFG_TSB_CFG 0xEC699C
+
+#define mmTPC3_CFG_DBGMEM_ADD 0xEC69A0
+
+#define mmTPC3_CFG_DBGMEM_DATA_WR 0xEC69A4
+
+#define mmTPC3_CFG_DBGMEM_DATA_RD 0xEC69A8
+
+#define mmTPC3_CFG_DBGMEM_CTRL 0xEC69AC
+
+#define mmTPC3_CFG_DBGMEM_RC 0xEC69B0
+
+#define mmTPC3_CFG_TSB_INFLIGHT_CNTR 0xEC69B4
+
+#define mmTPC3_CFG_WQ_INFLIGHT_CNTR 0xEC69B8
+
+#define mmTPC3_CFG_WQ_LBW_TOTAL_CNTR 0xEC69BC
+
+#define mmTPC3_CFG_WQ_HBW_TOTAL_CNTR 0xEC69C0
+
+#define mmTPC3_CFG_IRQ_OCCOUPY_CNTR 0xEC69C4
+
+#define mmTPC3_CFG_FUNC_MBIST_CNTRL 0xEC69D0
+
+#define mmTPC3_CFG_FUNC_MBIST_PAT 0xEC69D4
+
+#define mmTPC3_CFG_FUNC_MBIST_MEM_0 0xEC69D8
+
+#define mmTPC3_CFG_FUNC_MBIST_MEM_1 0xEC69DC
+
+#define mmTPC3_CFG_FUNC_MBIST_MEM_2 0xEC69E0
+
+#define mmTPC3_CFG_FUNC_MBIST_MEM_3 0xEC69E4
+
+#define mmTPC3_CFG_FUNC_MBIST_MEM_4 0xEC69E8
+
+#define mmTPC3_CFG_FUNC_MBIST_MEM_5 0xEC69EC
+
+#define mmTPC3_CFG_FUNC_MBIST_MEM_6 0xEC69F0
+
+#define mmTPC3_CFG_FUNC_MBIST_MEM_7 0xEC69F4
+
+#define mmTPC3_CFG_FUNC_MBIST_MEM_8 0xEC69F8
+
+#define mmTPC3_CFG_FUNC_MBIST_MEM_9 0xEC69FC
+
+#define mmTPC3_CFG_QM_TENSOR_0_BASE_ADDR_LOW 0xEC6A00
+
+#define mmTPC3_CFG_QM_TENSOR_0_BASE_ADDR_HIGH 0xEC6A04
+
+#define mmTPC3_CFG_QM_TENSOR_0_PADDING_VALUE 0xEC6A08
+
+#define mmTPC3_CFG_QM_TENSOR_0_TENSOR_CONFIG 0xEC6A0C
+
+#define mmTPC3_CFG_QM_TENSOR_0_DIM_0_SIZE 0xEC6A10
+
+#define mmTPC3_CFG_QM_TENSOR_0_DIM_0_STRIDE 0xEC6A14
+
+#define mmTPC3_CFG_QM_TENSOR_0_DIM_1_SIZE 0xEC6A18
+
+#define mmTPC3_CFG_QM_TENSOR_0_DIM_1_STRIDE 0xEC6A1C
+
+#define mmTPC3_CFG_QM_TENSOR_0_DIM_2_SIZE 0xEC6A20
+
+#define mmTPC3_CFG_QM_TENSOR_0_DIM_2_STRIDE 0xEC6A24
+
+#define mmTPC3_CFG_QM_TENSOR_0_DIM_3_SIZE 0xEC6A28
+
+#define mmTPC3_CFG_QM_TENSOR_0_DIM_3_STRIDE 0xEC6A2C
+
+#define mmTPC3_CFG_QM_TENSOR_0_DIM_4_SIZE 0xEC6A30
+
+#define mmTPC3_CFG_QM_TENSOR_0_DIM_4_STRIDE 0xEC6A34
+
+#define mmTPC3_CFG_QM_TENSOR_1_BASE_ADDR_LOW 0xEC6A38
+
+#define mmTPC3_CFG_QM_TENSOR_1_BASE_ADDR_HIGH 0xEC6A3C
+
+#define mmTPC3_CFG_QM_TENSOR_1_PADDING_VALUE 0xEC6A40
+
+#define mmTPC3_CFG_QM_TENSOR_1_TENSOR_CONFIG 0xEC6A44
+
+#define mmTPC3_CFG_QM_TENSOR_1_DIM_0_SIZE 0xEC6A48
+
+#define mmTPC3_CFG_QM_TENSOR_1_DIM_0_STRIDE 0xEC6A4C
+
+#define mmTPC3_CFG_QM_TENSOR_1_DIM_1_SIZE 0xEC6A50
+
+#define mmTPC3_CFG_QM_TENSOR_1_DIM_1_STRIDE 0xEC6A54
+
+#define mmTPC3_CFG_QM_TENSOR_1_DIM_2_SIZE 0xEC6A58
+
+#define mmTPC3_CFG_QM_TENSOR_1_DIM_2_STRIDE 0xEC6A5C
+
+#define mmTPC3_CFG_QM_TENSOR_1_DIM_3_SIZE 0xEC6A60
+
+#define mmTPC3_CFG_QM_TENSOR_1_DIM_3_STRIDE 0xEC6A64
+
+#define mmTPC3_CFG_QM_TENSOR_1_DIM_4_SIZE 0xEC6A68
+
+#define mmTPC3_CFG_QM_TENSOR_1_DIM_4_STRIDE 0xEC6A6C
+
+#define mmTPC3_CFG_QM_TENSOR_2_BASE_ADDR_LOW 0xEC6A70
+
+#define mmTPC3_CFG_QM_TENSOR_2_BASE_ADDR_HIGH 0xEC6A74
+
+#define mmTPC3_CFG_QM_TENSOR_2_PADDING_VALUE 0xEC6A78
+
+#define mmTPC3_CFG_QM_TENSOR_2_TENSOR_CONFIG 0xEC6A7C
+
+#define mmTPC3_CFG_QM_TENSOR_2_DIM_0_SIZE 0xEC6A80
+
+#define mmTPC3_CFG_QM_TENSOR_2_DIM_0_STRIDE 0xEC6A84
+
+#define mmTPC3_CFG_QM_TENSOR_2_DIM_1_SIZE 0xEC6A88
+
+#define mmTPC3_CFG_QM_TENSOR_2_DIM_1_STRIDE 0xEC6A8C
+
+#define mmTPC3_CFG_QM_TENSOR_2_DIM_2_SIZE 0xEC6A90
+
+#define mmTPC3_CFG_QM_TENSOR_2_DIM_2_STRIDE 0xEC6A94
+
+#define mmTPC3_CFG_QM_TENSOR_2_DIM_3_SIZE 0xEC6A98
+
+#define mmTPC3_CFG_QM_TENSOR_2_DIM_3_STRIDE 0xEC6A9C
+
+#define mmTPC3_CFG_QM_TENSOR_2_DIM_4_SIZE 0xEC6AA0
+
+#define mmTPC3_CFG_QM_TENSOR_2_DIM_4_STRIDE 0xEC6AA4
+
+#define mmTPC3_CFG_QM_TENSOR_3_BASE_ADDR_LOW 0xEC6AA8
+
+#define mmTPC3_CFG_QM_TENSOR_3_BASE_ADDR_HIGH 0xEC6AAC
+
+#define mmTPC3_CFG_QM_TENSOR_3_PADDING_VALUE 0xEC6AB0
+
+#define mmTPC3_CFG_QM_TENSOR_3_TENSOR_CONFIG 0xEC6AB4
+
+#define mmTPC3_CFG_QM_TENSOR_3_DIM_0_SIZE 0xEC6AB8
+
+#define mmTPC3_CFG_QM_TENSOR_3_DIM_0_STRIDE 0xEC6ABC
+
+#define mmTPC3_CFG_QM_TENSOR_3_DIM_1_SIZE 0xEC6AC0
+
+#define mmTPC3_CFG_QM_TENSOR_3_DIM_1_STRIDE 0xEC6AC4
+
+#define mmTPC3_CFG_QM_TENSOR_3_DIM_2_SIZE 0xEC6AC8
+
+#define mmTPC3_CFG_QM_TENSOR_3_DIM_2_STRIDE 0xEC6ACC
+
+#define mmTPC3_CFG_QM_TENSOR_3_DIM_3_SIZE 0xEC6AD0
+
+#define mmTPC3_CFG_QM_TENSOR_3_DIM_3_STRIDE 0xEC6AD4
+
+#define mmTPC3_CFG_QM_TENSOR_3_DIM_4_SIZE 0xEC6AD8
+
+#define mmTPC3_CFG_QM_TENSOR_3_DIM_4_STRIDE 0xEC6ADC
+
+#define mmTPC3_CFG_QM_TENSOR_4_BASE_ADDR_LOW 0xEC6AE0
+
+#define mmTPC3_CFG_QM_TENSOR_4_BASE_ADDR_HIGH 0xEC6AE4
+
+#define mmTPC3_CFG_QM_TENSOR_4_PADDING_VALUE 0xEC6AE8
+
+#define mmTPC3_CFG_QM_TENSOR_4_TENSOR_CONFIG 0xEC6AEC
+
+#define mmTPC3_CFG_QM_TENSOR_4_DIM_0_SIZE 0xEC6AF0
+
+#define mmTPC3_CFG_QM_TENSOR_4_DIM_0_STRIDE 0xEC6AF4
+
+#define mmTPC3_CFG_QM_TENSOR_4_DIM_1_SIZE 0xEC6AF8
+
+#define mmTPC3_CFG_QM_TENSOR_4_DIM_1_STRIDE 0xEC6AFC
+
+#define mmTPC3_CFG_QM_TENSOR_4_DIM_2_SIZE 0xEC6B00
+
+#define mmTPC3_CFG_QM_TENSOR_4_DIM_2_STRIDE 0xEC6B04
+
+#define mmTPC3_CFG_QM_TENSOR_4_DIM_3_SIZE 0xEC6B08
+
+#define mmTPC3_CFG_QM_TENSOR_4_DIM_3_STRIDE 0xEC6B0C
+
+#define mmTPC3_CFG_QM_TENSOR_4_DIM_4_SIZE 0xEC6B10
+
+#define mmTPC3_CFG_QM_TENSOR_4_DIM_4_STRIDE 0xEC6B14
+
+#define mmTPC3_CFG_QM_TENSOR_5_BASE_ADDR_LOW 0xEC6B18
+
+#define mmTPC3_CFG_QM_TENSOR_5_BASE_ADDR_HIGH 0xEC6B1C
+
+#define mmTPC3_CFG_QM_TENSOR_5_PADDING_VALUE 0xEC6B20
+
+#define mmTPC3_CFG_QM_TENSOR_5_TENSOR_CONFIG 0xEC6B24
+
+#define mmTPC3_CFG_QM_TENSOR_5_DIM_0_SIZE 0xEC6B28
+
+#define mmTPC3_CFG_QM_TENSOR_5_DIM_0_STRIDE 0xEC6B2C
+
+#define mmTPC3_CFG_QM_TENSOR_5_DIM_1_SIZE 0xEC6B30
+
+#define mmTPC3_CFG_QM_TENSOR_5_DIM_1_STRIDE 0xEC6B34
+
+#define mmTPC3_CFG_QM_TENSOR_5_DIM_2_SIZE 0xEC6B38
+
+#define mmTPC3_CFG_QM_TENSOR_5_DIM_2_STRIDE 0xEC6B3C
+
+#define mmTPC3_CFG_QM_TENSOR_5_DIM_3_SIZE 0xEC6B40
+
+#define mmTPC3_CFG_QM_TENSOR_5_DIM_3_STRIDE 0xEC6B44
+
+#define mmTPC3_CFG_QM_TENSOR_5_DIM_4_SIZE 0xEC6B48
+
+#define mmTPC3_CFG_QM_TENSOR_5_DIM_4_STRIDE 0xEC6B4C
+
+#define mmTPC3_CFG_QM_TENSOR_6_BASE_ADDR_LOW 0xEC6B50
+
+#define mmTPC3_CFG_QM_TENSOR_6_BASE_ADDR_HIGH 0xEC6B54
+
+#define mmTPC3_CFG_QM_TENSOR_6_PADDING_VALUE 0xEC6B58
+
+#define mmTPC3_CFG_QM_TENSOR_6_TENSOR_CONFIG 0xEC6B5C
+
+#define mmTPC3_CFG_QM_TENSOR_6_DIM_0_SIZE 0xEC6B60
+
+#define mmTPC3_CFG_QM_TENSOR_6_DIM_0_STRIDE 0xEC6B64
+
+#define mmTPC3_CFG_QM_TENSOR_6_DIM_1_SIZE 0xEC6B68
+
+#define mmTPC3_CFG_QM_TENSOR_6_DIM_1_STRIDE 0xEC6B6C
+
+#define mmTPC3_CFG_QM_TENSOR_6_DIM_2_SIZE 0xEC6B70
+
+#define mmTPC3_CFG_QM_TENSOR_6_DIM_2_STRIDE 0xEC6B74
+
+#define mmTPC3_CFG_QM_TENSOR_6_DIM_3_SIZE 0xEC6B78
+
+#define mmTPC3_CFG_QM_TENSOR_6_DIM_3_STRIDE 0xEC6B7C
+
+#define mmTPC3_CFG_QM_TENSOR_6_DIM_4_SIZE 0xEC6B80
+
+#define mmTPC3_CFG_QM_TENSOR_6_DIM_4_STRIDE 0xEC6B84
+
+#define mmTPC3_CFG_QM_TENSOR_7_BASE_ADDR_LOW 0xEC6B88
+
+#define mmTPC3_CFG_QM_TENSOR_7_BASE_ADDR_HIGH 0xEC6B8C
+
+#define mmTPC3_CFG_QM_TENSOR_7_PADDING_VALUE 0xEC6B90
+
+#define mmTPC3_CFG_QM_TENSOR_7_TENSOR_CONFIG 0xEC6B94
+
+#define mmTPC3_CFG_QM_TENSOR_7_DIM_0_SIZE 0xEC6B98
+
+#define mmTPC3_CFG_QM_TENSOR_7_DIM_0_STRIDE 0xEC6B9C
+
+#define mmTPC3_CFG_QM_TENSOR_7_DIM_1_SIZE 0xEC6BA0
+
+#define mmTPC3_CFG_QM_TENSOR_7_DIM_1_STRIDE 0xEC6BA4
+
+#define mmTPC3_CFG_QM_TENSOR_7_DIM_2_SIZE 0xEC6BA8
+
+#define mmTPC3_CFG_QM_TENSOR_7_DIM_2_STRIDE 0xEC6BAC
+
+#define mmTPC3_CFG_QM_TENSOR_7_DIM_3_SIZE 0xEC6BB0
+
+#define mmTPC3_CFG_QM_TENSOR_7_DIM_3_STRIDE 0xEC6BB4
+
+#define mmTPC3_CFG_QM_TENSOR_7_DIM_4_SIZE 0xEC6BB8
+
+#define mmTPC3_CFG_QM_TENSOR_7_DIM_4_STRIDE 0xEC6BBC
+
+#define mmTPC3_CFG_QM_TENSOR_8_BASE_ADDR_LOW 0xEC6BC0
+
+#define mmTPC3_CFG_QM_TENSOR_8_BASE_ADDR_HIGH 0xEC6BC4
+
+#define mmTPC3_CFG_QM_TENSOR_8_PADDING_VALUE 0xEC6BC8
+
+#define mmTPC3_CFG_QM_TENSOR_8_TENSOR_CONFIG 0xEC6BCC
+
+#define mmTPC3_CFG_QM_TENSOR_8_DIM_0_SIZE 0xEC6BD0
+
+#define mmTPC3_CFG_QM_TENSOR_8_DIM_0_STRIDE 0xEC6BD4
+
+#define mmTPC3_CFG_QM_TENSOR_8_DIM_1_SIZE 0xEC6BD8
+
+#define mmTPC3_CFG_QM_TENSOR_8_DIM_1_STRIDE 0xEC6BDC
+
+#define mmTPC3_CFG_QM_TENSOR_8_DIM_2_SIZE 0xEC6BE0
+
+#define mmTPC3_CFG_QM_TENSOR_8_DIM_2_STRIDE 0xEC6BE4
+
+#define mmTPC3_CFG_QM_TENSOR_8_DIM_3_SIZE 0xEC6BE8
+
+#define mmTPC3_CFG_QM_TENSOR_8_DIM_3_STRIDE 0xEC6BEC
+
+#define mmTPC3_CFG_QM_TENSOR_8_DIM_4_SIZE 0xEC6BF0
+
+#define mmTPC3_CFG_QM_TENSOR_8_DIM_4_STRIDE 0xEC6BF4
+
+#define mmTPC3_CFG_QM_TENSOR_9_BASE_ADDR_LOW 0xEC6BF8
+
+#define mmTPC3_CFG_QM_TENSOR_9_BASE_ADDR_HIGH 0xEC6BFC
+
+#define mmTPC3_CFG_QM_TENSOR_9_PADDING_VALUE 0xEC6C00
+
+#define mmTPC3_CFG_QM_TENSOR_9_TENSOR_CONFIG 0xEC6C04
+
+#define mmTPC3_CFG_QM_TENSOR_9_DIM_0_SIZE 0xEC6C08
+
+#define mmTPC3_CFG_QM_TENSOR_9_DIM_0_STRIDE 0xEC6C0C
+
+#define mmTPC3_CFG_QM_TENSOR_9_DIM_1_SIZE 0xEC6C10
+
+#define mmTPC3_CFG_QM_TENSOR_9_DIM_1_STRIDE 0xEC6C14
+
+#define mmTPC3_CFG_QM_TENSOR_9_DIM_2_SIZE 0xEC6C18
+
+#define mmTPC3_CFG_QM_TENSOR_9_DIM_2_STRIDE 0xEC6C1C
+
+#define mmTPC3_CFG_QM_TENSOR_9_DIM_3_SIZE 0xEC6C20
+
+#define mmTPC3_CFG_QM_TENSOR_9_DIM_3_STRIDE 0xEC6C24
+
+#define mmTPC3_CFG_QM_TENSOR_9_DIM_4_SIZE 0xEC6C28
+
+#define mmTPC3_CFG_QM_TENSOR_9_DIM_4_STRIDE 0xEC6C2C
+
+#define mmTPC3_CFG_QM_TENSOR_10_BASE_ADDR_LOW 0xEC6C30
+
+#define mmTPC3_CFG_QM_TENSOR_10_BASE_ADDR_HIGH 0xEC6C34
+
+#define mmTPC3_CFG_QM_TENSOR_10_PADDING_VALUE 0xEC6C38
+
+#define mmTPC3_CFG_QM_TENSOR_10_TENSOR_CONFIG 0xEC6C3C
+
+#define mmTPC3_CFG_QM_TENSOR_10_DIM_0_SIZE 0xEC6C40
+
+#define mmTPC3_CFG_QM_TENSOR_10_DIM_0_STRIDE 0xEC6C44
+
+#define mmTPC3_CFG_QM_TENSOR_10_DIM_1_SIZE 0xEC6C48
+
+#define mmTPC3_CFG_QM_TENSOR_10_DIM_1_STRIDE 0xEC6C4C
+
+#define mmTPC3_CFG_QM_TENSOR_10_DIM_2_SIZE 0xEC6C50
+
+#define mmTPC3_CFG_QM_TENSOR_10_DIM_2_STRIDE 0xEC6C54
+
+#define mmTPC3_CFG_QM_TENSOR_10_DIM_3_SIZE 0xEC6C58
+
+#define mmTPC3_CFG_QM_TENSOR_10_DIM_3_STRIDE 0xEC6C5C
+
+#define mmTPC3_CFG_QM_TENSOR_10_DIM_4_SIZE 0xEC6C60
+
+#define mmTPC3_CFG_QM_TENSOR_10_DIM_4_STRIDE 0xEC6C64
+
+#define mmTPC3_CFG_QM_TENSOR_11_BASE_ADDR_LOW 0xEC6C68
+
+#define mmTPC3_CFG_QM_TENSOR_11_BASE_ADDR_HIGH 0xEC6C6C
+
+#define mmTPC3_CFG_QM_TENSOR_11_PADDING_VALUE 0xEC6C70
+
+#define mmTPC3_CFG_QM_TENSOR_11_TENSOR_CONFIG 0xEC6C74
+
+#define mmTPC3_CFG_QM_TENSOR_11_DIM_0_SIZE 0xEC6C78
+
+#define mmTPC3_CFG_QM_TENSOR_11_DIM_0_STRIDE 0xEC6C7C
+
+#define mmTPC3_CFG_QM_TENSOR_11_DIM_1_SIZE 0xEC6C80
+
+#define mmTPC3_CFG_QM_TENSOR_11_DIM_1_STRIDE 0xEC6C84
+
+#define mmTPC3_CFG_QM_TENSOR_11_DIM_2_SIZE 0xEC6C88
+
+#define mmTPC3_CFG_QM_TENSOR_11_DIM_2_STRIDE 0xEC6C8C
+
+#define mmTPC3_CFG_QM_TENSOR_11_DIM_3_SIZE 0xEC6C90
+
+#define mmTPC3_CFG_QM_TENSOR_11_DIM_3_STRIDE 0xEC6C94
+
+#define mmTPC3_CFG_QM_TENSOR_11_DIM_4_SIZE 0xEC6C98
+
+#define mmTPC3_CFG_QM_TENSOR_11_DIM_4_STRIDE 0xEC6C9C
+
+#define mmTPC3_CFG_QM_TENSOR_12_BASE_ADDR_LOW 0xEC6CA0
+
+#define mmTPC3_CFG_QM_TENSOR_12_BASE_ADDR_HIGH 0xEC6CA4
+
+#define mmTPC3_CFG_QM_TENSOR_12_PADDING_VALUE 0xEC6CA8
+
+#define mmTPC3_CFG_QM_TENSOR_12_TENSOR_CONFIG 0xEC6CAC
+
+#define mmTPC3_CFG_QM_TENSOR_12_DIM_0_SIZE 0xEC6CB0
+
+#define mmTPC3_CFG_QM_TENSOR_12_DIM_0_STRIDE 0xEC6CB4
+
+#define mmTPC3_CFG_QM_TENSOR_12_DIM_1_SIZE 0xEC6CB8
+
+#define mmTPC3_CFG_QM_TENSOR_12_DIM_1_STRIDE 0xEC6CBC
+
+#define mmTPC3_CFG_QM_TENSOR_12_DIM_2_SIZE 0xEC6CC0
+
+#define mmTPC3_CFG_QM_TENSOR_12_DIM_2_STRIDE 0xEC6CC4
+
+#define mmTPC3_CFG_QM_TENSOR_12_DIM_3_SIZE 0xEC6CC8
+
+#define mmTPC3_CFG_QM_TENSOR_12_DIM_3_STRIDE 0xEC6CCC
+
+#define mmTPC3_CFG_QM_TENSOR_12_DIM_4_SIZE 0xEC6CD0
+
+#define mmTPC3_CFG_QM_TENSOR_12_DIM_4_STRIDE 0xEC6CD4
+
+#define mmTPC3_CFG_QM_TENSOR_13_BASE_ADDR_LOW 0xEC6CD8
+
+#define mmTPC3_CFG_QM_TENSOR_13_BASE_ADDR_HIGH 0xEC6CDC
+
+#define mmTPC3_CFG_QM_TENSOR_13_PADDING_VALUE 0xEC6CE0
+
+#define mmTPC3_CFG_QM_TENSOR_13_TENSOR_CONFIG 0xEC6CE4
+
+#define mmTPC3_CFG_QM_TENSOR_13_DIM_0_SIZE 0xEC6CE8
+
+#define mmTPC3_CFG_QM_TENSOR_13_DIM_0_STRIDE 0xEC6CEC
+
+#define mmTPC3_CFG_QM_TENSOR_13_DIM_1_SIZE 0xEC6CF0
+
+#define mmTPC3_CFG_QM_TENSOR_13_DIM_1_STRIDE 0xEC6CF4
+
+#define mmTPC3_CFG_QM_TENSOR_13_DIM_2_SIZE 0xEC6CF8
+
+#define mmTPC3_CFG_QM_TENSOR_13_DIM_2_STRIDE 0xEC6CFC
+
+#define mmTPC3_CFG_QM_TENSOR_13_DIM_3_SIZE 0xEC6D00
+
+#define mmTPC3_CFG_QM_TENSOR_13_DIM_3_STRIDE 0xEC6D04
+
+#define mmTPC3_CFG_QM_TENSOR_13_DIM_4_SIZE 0xEC6D08
+
+#define mmTPC3_CFG_QM_TENSOR_13_DIM_4_STRIDE 0xEC6D0C
+
+#define mmTPC3_CFG_QM_TENSOR_14_BASE_ADDR_LOW 0xEC6D10
+
+#define mmTPC3_CFG_QM_TENSOR_14_BASE_ADDR_HIGH 0xEC6D14
+
+#define mmTPC3_CFG_QM_TENSOR_14_PADDING_VALUE 0xEC6D18
+
+#define mmTPC3_CFG_QM_TENSOR_14_TENSOR_CONFIG 0xEC6D1C
+
+#define mmTPC3_CFG_QM_TENSOR_14_DIM_0_SIZE 0xEC6D20
+
+#define mmTPC3_CFG_QM_TENSOR_14_DIM_0_STRIDE 0xEC6D24
+
+#define mmTPC3_CFG_QM_TENSOR_14_DIM_1_SIZE 0xEC6D28
+
+#define mmTPC3_CFG_QM_TENSOR_14_DIM_1_STRIDE 0xEC6D2C
+
+#define mmTPC3_CFG_QM_TENSOR_14_DIM_2_SIZE 0xEC6D30
+
+#define mmTPC3_CFG_QM_TENSOR_14_DIM_2_STRIDE 0xEC6D34
+
+#define mmTPC3_CFG_QM_TENSOR_14_DIM_3_SIZE 0xEC6D38
+
+#define mmTPC3_CFG_QM_TENSOR_14_DIM_3_STRIDE 0xEC6D3C
+
+#define mmTPC3_CFG_QM_TENSOR_14_DIM_4_SIZE 0xEC6D40
+
+#define mmTPC3_CFG_QM_TENSOR_14_DIM_4_STRIDE 0xEC6D44
+
+#define mmTPC3_CFG_QM_TENSOR_15_BASE_ADDR_LOW 0xEC6D48
+
+#define mmTPC3_CFG_QM_TENSOR_15_BASE_ADDR_HIGH 0xEC6D4C
+
+#define mmTPC3_CFG_QM_TENSOR_15_PADDING_VALUE 0xEC6D50
+
+#define mmTPC3_CFG_QM_TENSOR_15_TENSOR_CONFIG 0xEC6D54
+
+#define mmTPC3_CFG_QM_TENSOR_15_DIM_0_SIZE 0xEC6D58
+
+#define mmTPC3_CFG_QM_TENSOR_15_DIM_0_STRIDE 0xEC6D5C
+
+#define mmTPC3_CFG_QM_TENSOR_15_DIM_1_SIZE 0xEC6D60
+
+#define mmTPC3_CFG_QM_TENSOR_15_DIM_1_STRIDE 0xEC6D64
+
+#define mmTPC3_CFG_QM_TENSOR_15_DIM_2_SIZE 0xEC6D68
+
+#define mmTPC3_CFG_QM_TENSOR_15_DIM_2_STRIDE 0xEC6D6C
+
+#define mmTPC3_CFG_QM_TENSOR_15_DIM_3_SIZE 0xEC6D70
+
+#define mmTPC3_CFG_QM_TENSOR_15_DIM_3_STRIDE 0xEC6D74
+
+#define mmTPC3_CFG_QM_TENSOR_15_DIM_4_SIZE 0xEC6D78
+
+#define mmTPC3_CFG_QM_TENSOR_15_DIM_4_STRIDE 0xEC6D7C
+
+#define mmTPC3_CFG_QM_SYNC_OBJECT_MESSAGE 0xEC6D80
+
+#define mmTPC3_CFG_QM_SYNC_OBJECT_ADDR 0xEC6D84
+
+#define mmTPC3_CFG_QM_KERNEL_BASE_ADDRESS_LOW 0xEC6D88
+
+#define mmTPC3_CFG_QM_KERNEL_BASE_ADDRESS_HIGH 0xEC6D8C
+
+#define mmTPC3_CFG_QM_TID_BASE_DIM_0 0xEC6D90
+
+#define mmTPC3_CFG_QM_TID_SIZE_DIM_0 0xEC6D94
+
+#define mmTPC3_CFG_QM_TID_BASE_DIM_1 0xEC6D98
+
+#define mmTPC3_CFG_QM_TID_SIZE_DIM_1 0xEC6D9C
+
+#define mmTPC3_CFG_QM_TID_BASE_DIM_2 0xEC6DA0
+
+#define mmTPC3_CFG_QM_TID_SIZE_DIM_2 0xEC6DA4
+
+#define mmTPC3_CFG_QM_TID_BASE_DIM_3 0xEC6DA8
+
+#define mmTPC3_CFG_QM_TID_SIZE_DIM_3 0xEC6DAC
+
+#define mmTPC3_CFG_QM_TID_BASE_DIM_4 0xEC6DB0
+
+#define mmTPC3_CFG_QM_TID_SIZE_DIM_4 0xEC6DB4
+
+#define mmTPC3_CFG_QM_KERNEL_CONFIG 0xEC6DB8
+
+#define mmTPC3_CFG_QM_KERNEL_ID 0xEC6DBC
+
+#define mmTPC3_CFG_QM_SRF_0 0xEC6DC0
+
+#define mmTPC3_CFG_QM_SRF_1 0xEC6DC4
+
+#define mmTPC3_CFG_QM_SRF_2 0xEC6DC8
+
+#define mmTPC3_CFG_QM_SRF_3 0xEC6DCC
+
+#define mmTPC3_CFG_QM_SRF_4 0xEC6DD0
+
+#define mmTPC3_CFG_QM_SRF_5 0xEC6DD4
+
+#define mmTPC3_CFG_QM_SRF_6 0xEC6DD8
+
+#define mmTPC3_CFG_QM_SRF_7 0xEC6DDC
+
+#define mmTPC3_CFG_QM_SRF_8 0xEC6DE0
+
+#define mmTPC3_CFG_QM_SRF_9 0xEC6DE4
+
+#define mmTPC3_CFG_QM_SRF_10 0xEC6DE8
+
+#define mmTPC3_CFG_QM_SRF_11 0xEC6DEC
+
+#define mmTPC3_CFG_QM_SRF_12 0xEC6DF0
+
+#define mmTPC3_CFG_QM_SRF_13 0xEC6DF4
+
+#define mmTPC3_CFG_QM_SRF_14 0xEC6DF8
+
+#define mmTPC3_CFG_QM_SRF_15 0xEC6DFC
+
+#define mmTPC3_CFG_QM_SRF_16 0xEC6E00
+
+#define mmTPC3_CFG_QM_SRF_17 0xEC6E04
+
+#define mmTPC3_CFG_QM_SRF_18 0xEC6E08
+
+#define mmTPC3_CFG_QM_SRF_19 0xEC6E0C
+
+#define mmTPC3_CFG_QM_SRF_20 0xEC6E10
+
+#define mmTPC3_CFG_QM_SRF_21 0xEC6E14
+
+#define mmTPC3_CFG_QM_SRF_22 0xEC6E18
+
+#define mmTPC3_CFG_QM_SRF_23 0xEC6E1C
+
+#define mmTPC3_CFG_QM_SRF_24 0xEC6E20
+
+#define mmTPC3_CFG_QM_SRF_25 0xEC6E24
+
+#define mmTPC3_CFG_QM_SRF_26 0xEC6E28
+
+#define mmTPC3_CFG_QM_SRF_27 0xEC6E2C
+
+#define mmTPC3_CFG_QM_SRF_28 0xEC6E30
+
+#define mmTPC3_CFG_QM_SRF_29 0xEC6E34
+
+#define mmTPC3_CFG_QM_SRF_30 0xEC6E38
+
+#define mmTPC3_CFG_QM_SRF_31 0xEC6E3C
+
+#endif /* ASIC_REG_TPC3_CFG_REGS_H_ */
diff --git a/drivers/accel/habanalabs/include/gaudi/asic_reg/tpc3_qm_regs.h b/drivers/accel/habanalabs/include/gaudi/asic_reg/tpc3_qm_regs.h
new file mode 100644
index 0000000000..5f2a0fd86c
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi/asic_reg/tpc3_qm_regs.h
@@ -0,0 +1,834 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2016-2018 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ ** DO NOT EDIT BELOW **
+ ************************************/
+
+#ifndef ASIC_REG_TPC3_QM_REGS_H_
+#define ASIC_REG_TPC3_QM_REGS_H_
+
+/*
+ *****************************************
+ * TPC3_QM (Prototype: QMAN)
+ *****************************************
+ */
+
+#define mmTPC3_QM_GLBL_CFG0 0xEC8000
+
+#define mmTPC3_QM_GLBL_CFG1 0xEC8004
+
+#define mmTPC3_QM_GLBL_PROT 0xEC8008
+
+#define mmTPC3_QM_GLBL_ERR_CFG 0xEC800C
+
+#define mmTPC3_QM_GLBL_SECURE_PROPS_0 0xEC8010
+
+#define mmTPC3_QM_GLBL_SECURE_PROPS_1 0xEC8014
+
+#define mmTPC3_QM_GLBL_SECURE_PROPS_2 0xEC8018
+
+#define mmTPC3_QM_GLBL_SECURE_PROPS_3 0xEC801C
+
+#define mmTPC3_QM_GLBL_SECURE_PROPS_4 0xEC8020
+
+#define mmTPC3_QM_GLBL_NON_SECURE_PROPS_0 0xEC8024
+
+#define mmTPC3_QM_GLBL_NON_SECURE_PROPS_1 0xEC8028
+
+#define mmTPC3_QM_GLBL_NON_SECURE_PROPS_2 0xEC802C
+
+#define mmTPC3_QM_GLBL_NON_SECURE_PROPS_3 0xEC8030
+
+#define mmTPC3_QM_GLBL_NON_SECURE_PROPS_4 0xEC8034
+
+#define mmTPC3_QM_GLBL_STS0 0xEC8038
+
+#define mmTPC3_QM_GLBL_STS1_0 0xEC8040
+
+#define mmTPC3_QM_GLBL_STS1_1 0xEC8044
+
+#define mmTPC3_QM_GLBL_STS1_2 0xEC8048
+
+#define mmTPC3_QM_GLBL_STS1_3 0xEC804C
+
+#define mmTPC3_QM_GLBL_STS1_4 0xEC8050
+
+#define mmTPC3_QM_GLBL_MSG_EN_0 0xEC8054
+
+#define mmTPC3_QM_GLBL_MSG_EN_1 0xEC8058
+
+#define mmTPC3_QM_GLBL_MSG_EN_2 0xEC805C
+
+#define mmTPC3_QM_GLBL_MSG_EN_3 0xEC8060
+
+#define mmTPC3_QM_GLBL_MSG_EN_4 0xEC8068
+
+#define mmTPC3_QM_PQ_BASE_LO_0 0xEC8070
+
+#define mmTPC3_QM_PQ_BASE_LO_1 0xEC8074
+
+#define mmTPC3_QM_PQ_BASE_LO_2 0xEC8078
+
+#define mmTPC3_QM_PQ_BASE_LO_3 0xEC807C
+
+#define mmTPC3_QM_PQ_BASE_HI_0 0xEC8080
+
+#define mmTPC3_QM_PQ_BASE_HI_1 0xEC8084
+
+#define mmTPC3_QM_PQ_BASE_HI_2 0xEC8088
+
+#define mmTPC3_QM_PQ_BASE_HI_3 0xEC808C
+
+#define mmTPC3_QM_PQ_SIZE_0 0xEC8090
+
+#define mmTPC3_QM_PQ_SIZE_1 0xEC8094
+
+#define mmTPC3_QM_PQ_SIZE_2 0xEC8098
+
+#define mmTPC3_QM_PQ_SIZE_3 0xEC809C
+
+#define mmTPC3_QM_PQ_PI_0 0xEC80A0
+
+#define mmTPC3_QM_PQ_PI_1 0xEC80A4
+
+#define mmTPC3_QM_PQ_PI_2 0xEC80A8
+
+#define mmTPC3_QM_PQ_PI_3 0xEC80AC
+
+#define mmTPC3_QM_PQ_CI_0 0xEC80B0
+
+#define mmTPC3_QM_PQ_CI_1 0xEC80B4
+
+#define mmTPC3_QM_PQ_CI_2 0xEC80B8
+
+#define mmTPC3_QM_PQ_CI_3 0xEC80BC
+
+#define mmTPC3_QM_PQ_CFG0_0 0xEC80C0
+
+#define mmTPC3_QM_PQ_CFG0_1 0xEC80C4
+
+#define mmTPC3_QM_PQ_CFG0_2 0xEC80C8
+
+#define mmTPC3_QM_PQ_CFG0_3 0xEC80CC
+
+#define mmTPC3_QM_PQ_CFG1_0 0xEC80D0
+
+#define mmTPC3_QM_PQ_CFG1_1 0xEC80D4
+
+#define mmTPC3_QM_PQ_CFG1_2 0xEC80D8
+
+#define mmTPC3_QM_PQ_CFG1_3 0xEC80DC
+
+#define mmTPC3_QM_PQ_ARUSER_31_11_0 0xEC80E0
+
+#define mmTPC3_QM_PQ_ARUSER_31_11_1 0xEC80E4
+
+#define mmTPC3_QM_PQ_ARUSER_31_11_2 0xEC80E8
+
+#define mmTPC3_QM_PQ_ARUSER_31_11_3 0xEC80EC
+
+#define mmTPC3_QM_PQ_STS0_0 0xEC80F0
+
+#define mmTPC3_QM_PQ_STS0_1 0xEC80F4
+
+#define mmTPC3_QM_PQ_STS0_2 0xEC80F8
+
+#define mmTPC3_QM_PQ_STS0_3 0xEC80FC
+
+#define mmTPC3_QM_PQ_STS1_0 0xEC8100
+
+#define mmTPC3_QM_PQ_STS1_1 0xEC8104
+
+#define mmTPC3_QM_PQ_STS1_2 0xEC8108
+
+#define mmTPC3_QM_PQ_STS1_3 0xEC810C
+
+#define mmTPC3_QM_CQ_CFG0_0 0xEC8110
+
+#define mmTPC3_QM_CQ_CFG0_1 0xEC8114
+
+#define mmTPC3_QM_CQ_CFG0_2 0xEC8118
+
+#define mmTPC3_QM_CQ_CFG0_3 0xEC811C
+
+#define mmTPC3_QM_CQ_CFG0_4 0xEC8120
+
+#define mmTPC3_QM_CQ_CFG1_0 0xEC8124
+
+#define mmTPC3_QM_CQ_CFG1_1 0xEC8128
+
+#define mmTPC3_QM_CQ_CFG1_2 0xEC812C
+
+#define mmTPC3_QM_CQ_CFG1_3 0xEC8130
+
+#define mmTPC3_QM_CQ_CFG1_4 0xEC8134
+
+#define mmTPC3_QM_CQ_ARUSER_31_11_0 0xEC8138
+
+#define mmTPC3_QM_CQ_ARUSER_31_11_1 0xEC813C
+
+#define mmTPC3_QM_CQ_ARUSER_31_11_2 0xEC8140
+
+#define mmTPC3_QM_CQ_ARUSER_31_11_3 0xEC8144
+
+#define mmTPC3_QM_CQ_ARUSER_31_11_4 0xEC8148
+
+#define mmTPC3_QM_CQ_STS0_0 0xEC814C
+
+#define mmTPC3_QM_CQ_STS0_1 0xEC8150
+
+#define mmTPC3_QM_CQ_STS0_2 0xEC8154
+
+#define mmTPC3_QM_CQ_STS0_3 0xEC8158
+
+#define mmTPC3_QM_CQ_STS0_4 0xEC815C
+
+#define mmTPC3_QM_CQ_STS1_0 0xEC8160
+
+#define mmTPC3_QM_CQ_STS1_1 0xEC8164
+
+#define mmTPC3_QM_CQ_STS1_2 0xEC8168
+
+#define mmTPC3_QM_CQ_STS1_3 0xEC816C
+
+#define mmTPC3_QM_CQ_STS1_4 0xEC8170
+
+#define mmTPC3_QM_CQ_PTR_LO_0 0xEC8174
+
+#define mmTPC3_QM_CQ_PTR_HI_0 0xEC8178
+
+#define mmTPC3_QM_CQ_TSIZE_0 0xEC817C
+
+#define mmTPC3_QM_CQ_CTL_0 0xEC8180
+
+#define mmTPC3_QM_CQ_PTR_LO_1 0xEC8184
+
+#define mmTPC3_QM_CQ_PTR_HI_1 0xEC8188
+
+#define mmTPC3_QM_CQ_TSIZE_1 0xEC818C
+
+#define mmTPC3_QM_CQ_CTL_1 0xEC8190
+
+#define mmTPC3_QM_CQ_PTR_LO_2 0xEC8194
+
+#define mmTPC3_QM_CQ_PTR_HI_2 0xEC8198
+
+#define mmTPC3_QM_CQ_TSIZE_2 0xEC819C
+
+#define mmTPC3_QM_CQ_CTL_2 0xEC81A0
+
+#define mmTPC3_QM_CQ_PTR_LO_3 0xEC81A4
+
+#define mmTPC3_QM_CQ_PTR_HI_3 0xEC81A8
+
+#define mmTPC3_QM_CQ_TSIZE_3 0xEC81AC
+
+#define mmTPC3_QM_CQ_CTL_3 0xEC81B0
+
+#define mmTPC3_QM_CQ_PTR_LO_4 0xEC81B4
+
+#define mmTPC3_QM_CQ_PTR_HI_4 0xEC81B8
+
+#define mmTPC3_QM_CQ_TSIZE_4 0xEC81BC
+
+#define mmTPC3_QM_CQ_CTL_4 0xEC81C0
+
+#define mmTPC3_QM_CQ_PTR_LO_STS_0 0xEC81C4
+
+#define mmTPC3_QM_CQ_PTR_LO_STS_1 0xEC81C8
+
+#define mmTPC3_QM_CQ_PTR_LO_STS_2 0xEC81CC
+
+#define mmTPC3_QM_CQ_PTR_LO_STS_3 0xEC81D0
+
+#define mmTPC3_QM_CQ_PTR_LO_STS_4 0xEC81D4
+
+#define mmTPC3_QM_CQ_PTR_HI_STS_0 0xEC81D8
+
+#define mmTPC3_QM_CQ_PTR_HI_STS_1 0xEC81DC
+
+#define mmTPC3_QM_CQ_PTR_HI_STS_2 0xEC81E0
+
+#define mmTPC3_QM_CQ_PTR_HI_STS_3 0xEC81E4
+
+#define mmTPC3_QM_CQ_PTR_HI_STS_4 0xEC81E8
+
+#define mmTPC3_QM_CQ_TSIZE_STS_0 0xEC81EC
+
+#define mmTPC3_QM_CQ_TSIZE_STS_1 0xEC81F0
+
+#define mmTPC3_QM_CQ_TSIZE_STS_2 0xEC81F4
+
+#define mmTPC3_QM_CQ_TSIZE_STS_3 0xEC81F8
+
+#define mmTPC3_QM_CQ_TSIZE_STS_4 0xEC81FC
+
+#define mmTPC3_QM_CQ_CTL_STS_0 0xEC8200
+
+#define mmTPC3_QM_CQ_CTL_STS_1 0xEC8204
+
+#define mmTPC3_QM_CQ_CTL_STS_2 0xEC8208
+
+#define mmTPC3_QM_CQ_CTL_STS_3 0xEC820C
+
+#define mmTPC3_QM_CQ_CTL_STS_4 0xEC8210
+
+#define mmTPC3_QM_CQ_IFIFO_CNT_0 0xEC8214
+
+#define mmTPC3_QM_CQ_IFIFO_CNT_1 0xEC8218
+
+#define mmTPC3_QM_CQ_IFIFO_CNT_2 0xEC821C
+
+#define mmTPC3_QM_CQ_IFIFO_CNT_3 0xEC8220
+
+#define mmTPC3_QM_CQ_IFIFO_CNT_4 0xEC8224
+
+#define mmTPC3_QM_CP_MSG_BASE0_ADDR_LO_0 0xEC8228
+
+#define mmTPC3_QM_CP_MSG_BASE0_ADDR_LO_1 0xEC822C
+
+#define mmTPC3_QM_CP_MSG_BASE0_ADDR_LO_2 0xEC8230
+
+#define mmTPC3_QM_CP_MSG_BASE0_ADDR_LO_3 0xEC8234
+
+#define mmTPC3_QM_CP_MSG_BASE0_ADDR_LO_4 0xEC8238
+
+#define mmTPC3_QM_CP_MSG_BASE0_ADDR_HI_0 0xEC823C
+
+#define mmTPC3_QM_CP_MSG_BASE0_ADDR_HI_1 0xEC8240
+
+#define mmTPC3_QM_CP_MSG_BASE0_ADDR_HI_2 0xEC8244
+
+#define mmTPC3_QM_CP_MSG_BASE0_ADDR_HI_3 0xEC8248
+
+#define mmTPC3_QM_CP_MSG_BASE0_ADDR_HI_4 0xEC824C
+
+#define mmTPC3_QM_CP_MSG_BASE1_ADDR_LO_0 0xEC8250
+
+#define mmTPC3_QM_CP_MSG_BASE1_ADDR_LO_1 0xEC8254
+
+#define mmTPC3_QM_CP_MSG_BASE1_ADDR_LO_2 0xEC8258
+
+#define mmTPC3_QM_CP_MSG_BASE1_ADDR_LO_3 0xEC825C
+
+#define mmTPC3_QM_CP_MSG_BASE1_ADDR_LO_4 0xEC8260
+
+#define mmTPC3_QM_CP_MSG_BASE1_ADDR_HI_0 0xEC8264
+
+#define mmTPC3_QM_CP_MSG_BASE1_ADDR_HI_1 0xEC8268
+
+#define mmTPC3_QM_CP_MSG_BASE1_ADDR_HI_2 0xEC826C
+
+#define mmTPC3_QM_CP_MSG_BASE1_ADDR_HI_3 0xEC8270
+
+#define mmTPC3_QM_CP_MSG_BASE1_ADDR_HI_4 0xEC8274
+
+#define mmTPC3_QM_CP_MSG_BASE2_ADDR_LO_0 0xEC8278
+
+#define mmTPC3_QM_CP_MSG_BASE2_ADDR_LO_1 0xEC827C
+
+#define mmTPC3_QM_CP_MSG_BASE2_ADDR_LO_2 0xEC8280
+
+#define mmTPC3_QM_CP_MSG_BASE2_ADDR_LO_3 0xEC8284
+
+#define mmTPC3_QM_CP_MSG_BASE2_ADDR_LO_4 0xEC8288
+
+#define mmTPC3_QM_CP_MSG_BASE2_ADDR_HI_0 0xEC828C
+
+#define mmTPC3_QM_CP_MSG_BASE2_ADDR_HI_1 0xEC8290
+
+#define mmTPC3_QM_CP_MSG_BASE2_ADDR_HI_2 0xEC8294
+
+#define mmTPC3_QM_CP_MSG_BASE2_ADDR_HI_3 0xEC8298
+
+#define mmTPC3_QM_CP_MSG_BASE2_ADDR_HI_4 0xEC829C
+
+#define mmTPC3_QM_CP_MSG_BASE3_ADDR_LO_0 0xEC82A0
+
+#define mmTPC3_QM_CP_MSG_BASE3_ADDR_LO_1 0xEC82A4
+
+#define mmTPC3_QM_CP_MSG_BASE3_ADDR_LO_2 0xEC82A8
+
+#define mmTPC3_QM_CP_MSG_BASE3_ADDR_LO_3 0xEC82AC
+
+#define mmTPC3_QM_CP_MSG_BASE3_ADDR_LO_4 0xEC82B0
+
+#define mmTPC3_QM_CP_MSG_BASE3_ADDR_HI_0 0xEC82B4
+
+#define mmTPC3_QM_CP_MSG_BASE3_ADDR_HI_1 0xEC82B8
+
+#define mmTPC3_QM_CP_MSG_BASE3_ADDR_HI_2 0xEC82BC
+
+#define mmTPC3_QM_CP_MSG_BASE3_ADDR_HI_3 0xEC82C0
+
+#define mmTPC3_QM_CP_MSG_BASE3_ADDR_HI_4 0xEC82C4
+
+#define mmTPC3_QM_CP_LDMA_TSIZE_OFFSET_0 0xEC82C8
+
+#define mmTPC3_QM_CP_LDMA_TSIZE_OFFSET_1 0xEC82CC
+
+#define mmTPC3_QM_CP_LDMA_TSIZE_OFFSET_2 0xEC82D0
+
+#define mmTPC3_QM_CP_LDMA_TSIZE_OFFSET_3 0xEC82D4
+
+#define mmTPC3_QM_CP_LDMA_TSIZE_OFFSET_4 0xEC82D8
+
+#define mmTPC3_QM_CP_LDMA_SRC_BASE_LO_OFFSET_0 0xEC82E0
+
+#define mmTPC3_QM_CP_LDMA_SRC_BASE_LO_OFFSET_1 0xEC82E4
+
+#define mmTPC3_QM_CP_LDMA_SRC_BASE_LO_OFFSET_2 0xEC82E8
+
+#define mmTPC3_QM_CP_LDMA_SRC_BASE_LO_OFFSET_3 0xEC82EC
+
+#define mmTPC3_QM_CP_LDMA_SRC_BASE_LO_OFFSET_4 0xEC82F0
+
+#define mmTPC3_QM_CP_LDMA_DST_BASE_LO_OFFSET_0 0xEC82F4
+
+#define mmTPC3_QM_CP_LDMA_DST_BASE_LO_OFFSET_1 0xEC82F8
+
+#define mmTPC3_QM_CP_LDMA_DST_BASE_LO_OFFSET_2 0xEC82FC
+
+#define mmTPC3_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 0xEC8300
+
+#define mmTPC3_QM_CP_LDMA_DST_BASE_LO_OFFSET_4 0xEC8304
+
+#define mmTPC3_QM_CP_FENCE0_RDATA_0 0xEC8308
+
+#define mmTPC3_QM_CP_FENCE0_RDATA_1 0xEC830C
+
+#define mmTPC3_QM_CP_FENCE0_RDATA_2 0xEC8310
+
+#define mmTPC3_QM_CP_FENCE0_RDATA_3 0xEC8314
+
+#define mmTPC3_QM_CP_FENCE0_RDATA_4 0xEC8318
+
+#define mmTPC3_QM_CP_FENCE1_RDATA_0 0xEC831C
+
+#define mmTPC3_QM_CP_FENCE1_RDATA_1 0xEC8320
+
+#define mmTPC3_QM_CP_FENCE1_RDATA_2 0xEC8324
+
+#define mmTPC3_QM_CP_FENCE1_RDATA_3 0xEC8328
+
+#define mmTPC3_QM_CP_FENCE1_RDATA_4 0xEC832C
+
+#define mmTPC3_QM_CP_FENCE2_RDATA_0 0xEC8330
+
+#define mmTPC3_QM_CP_FENCE2_RDATA_1 0xEC8334
+
+#define mmTPC3_QM_CP_FENCE2_RDATA_2 0xEC8338
+
+#define mmTPC3_QM_CP_FENCE2_RDATA_3 0xEC833C
+
+#define mmTPC3_QM_CP_FENCE2_RDATA_4 0xEC8340
+
+#define mmTPC3_QM_CP_FENCE3_RDATA_0 0xEC8344
+
+#define mmTPC3_QM_CP_FENCE3_RDATA_1 0xEC8348
+
+#define mmTPC3_QM_CP_FENCE3_RDATA_2 0xEC834C
+
+#define mmTPC3_QM_CP_FENCE3_RDATA_3 0xEC8350
+
+#define mmTPC3_QM_CP_FENCE3_RDATA_4 0xEC8354
+
+#define mmTPC3_QM_CP_FENCE0_CNT_0 0xEC8358
+
+#define mmTPC3_QM_CP_FENCE0_CNT_1 0xEC835C
+
+#define mmTPC3_QM_CP_FENCE0_CNT_2 0xEC8360
+
+#define mmTPC3_QM_CP_FENCE0_CNT_3 0xEC8364
+
+#define mmTPC3_QM_CP_FENCE0_CNT_4 0xEC8368
+
+#define mmTPC3_QM_CP_FENCE1_CNT_0 0xEC836C
+
+#define mmTPC3_QM_CP_FENCE1_CNT_1 0xEC8370
+
+#define mmTPC3_QM_CP_FENCE1_CNT_2 0xEC8374
+
+#define mmTPC3_QM_CP_FENCE1_CNT_3 0xEC8378
+
+#define mmTPC3_QM_CP_FENCE1_CNT_4 0xEC837C
+
+#define mmTPC3_QM_CP_FENCE2_CNT_0 0xEC8380
+
+#define mmTPC3_QM_CP_FENCE2_CNT_1 0xEC8384
+
+#define mmTPC3_QM_CP_FENCE2_CNT_2 0xEC8388
+
+#define mmTPC3_QM_CP_FENCE2_CNT_3 0xEC838C
+
+#define mmTPC3_QM_CP_FENCE2_CNT_4 0xEC8390
+
+#define mmTPC3_QM_CP_FENCE3_CNT_0 0xEC8394
+
+#define mmTPC3_QM_CP_FENCE3_CNT_1 0xEC8398
+
+#define mmTPC3_QM_CP_FENCE3_CNT_2 0xEC839C
+
+#define mmTPC3_QM_CP_FENCE3_CNT_3 0xEC83A0
+
+#define mmTPC3_QM_CP_FENCE3_CNT_4 0xEC83A4
+
+#define mmTPC3_QM_CP_STS_0 0xEC83A8
+
+#define mmTPC3_QM_CP_STS_1 0xEC83AC
+
+#define mmTPC3_QM_CP_STS_2 0xEC83B0
+
+#define mmTPC3_QM_CP_STS_3 0xEC83B4
+
+#define mmTPC3_QM_CP_STS_4 0xEC83B8
+
+#define mmTPC3_QM_CP_CURRENT_INST_LO_0 0xEC83BC
+
+#define mmTPC3_QM_CP_CURRENT_INST_LO_1 0xEC83C0
+
+#define mmTPC3_QM_CP_CURRENT_INST_LO_2 0xEC83C4
+
+#define mmTPC3_QM_CP_CURRENT_INST_LO_3 0xEC83C8
+
+#define mmTPC3_QM_CP_CURRENT_INST_LO_4 0xEC83CC
+
+#define mmTPC3_QM_CP_CURRENT_INST_HI_0 0xEC83D0
+
+#define mmTPC3_QM_CP_CURRENT_INST_HI_1 0xEC83D4
+
+#define mmTPC3_QM_CP_CURRENT_INST_HI_2 0xEC83D8
+
+#define mmTPC3_QM_CP_CURRENT_INST_HI_3 0xEC83DC
+
+#define mmTPC3_QM_CP_CURRENT_INST_HI_4 0xEC83E0
+
+#define mmTPC3_QM_CP_BARRIER_CFG_0 0xEC83F4
+
+#define mmTPC3_QM_CP_BARRIER_CFG_1 0xEC83F8
+
+#define mmTPC3_QM_CP_BARRIER_CFG_2 0xEC83FC
+
+#define mmTPC3_QM_CP_BARRIER_CFG_3 0xEC8400
+
+#define mmTPC3_QM_CP_BARRIER_CFG_4 0xEC8404
+
+#define mmTPC3_QM_CP_DBG_0_0 0xEC8408
+
+#define mmTPC3_QM_CP_DBG_0_1 0xEC840C
+
+#define mmTPC3_QM_CP_DBG_0_2 0xEC8410
+
+#define mmTPC3_QM_CP_DBG_0_3 0xEC8414
+
+#define mmTPC3_QM_CP_DBG_0_4 0xEC8418
+
+#define mmTPC3_QM_CP_ARUSER_31_11_0 0xEC841C
+
+#define mmTPC3_QM_CP_ARUSER_31_11_1 0xEC8420
+
+#define mmTPC3_QM_CP_ARUSER_31_11_2 0xEC8424
+
+#define mmTPC3_QM_CP_ARUSER_31_11_3 0xEC8428
+
+#define mmTPC3_QM_CP_ARUSER_31_11_4 0xEC842C
+
+#define mmTPC3_QM_CP_AWUSER_31_11_0 0xEC8430
+
+#define mmTPC3_QM_CP_AWUSER_31_11_1 0xEC8434
+
+#define mmTPC3_QM_CP_AWUSER_31_11_2 0xEC8438
+
+#define mmTPC3_QM_CP_AWUSER_31_11_3 0xEC843C
+
+#define mmTPC3_QM_CP_AWUSER_31_11_4 0xEC8440
+
+#define mmTPC3_QM_ARB_CFG_0 0xEC8A00
+
+#define mmTPC3_QM_ARB_CHOISE_Q_PUSH 0xEC8A04
+
+#define mmTPC3_QM_ARB_WRR_WEIGHT_0 0xEC8A08
+
+#define mmTPC3_QM_ARB_WRR_WEIGHT_1 0xEC8A0C
+
+#define mmTPC3_QM_ARB_WRR_WEIGHT_2 0xEC8A10
+
+#define mmTPC3_QM_ARB_WRR_WEIGHT_3 0xEC8A14
+
+#define mmTPC3_QM_ARB_CFG_1 0xEC8A18
+
+#define mmTPC3_QM_ARB_MST_AVAIL_CRED_0 0xEC8A20
+
+#define mmTPC3_QM_ARB_MST_AVAIL_CRED_1 0xEC8A24
+
+#define mmTPC3_QM_ARB_MST_AVAIL_CRED_2 0xEC8A28
+
+#define mmTPC3_QM_ARB_MST_AVAIL_CRED_3 0xEC8A2C
+
+#define mmTPC3_QM_ARB_MST_AVAIL_CRED_4 0xEC8A30
+
+#define mmTPC3_QM_ARB_MST_AVAIL_CRED_5 0xEC8A34
+
+#define mmTPC3_QM_ARB_MST_AVAIL_CRED_6 0xEC8A38
+
+#define mmTPC3_QM_ARB_MST_AVAIL_CRED_7 0xEC8A3C
+
+#define mmTPC3_QM_ARB_MST_AVAIL_CRED_8 0xEC8A40
+
+#define mmTPC3_QM_ARB_MST_AVAIL_CRED_9 0xEC8A44
+
+#define mmTPC3_QM_ARB_MST_AVAIL_CRED_10 0xEC8A48
+
+#define mmTPC3_QM_ARB_MST_AVAIL_CRED_11 0xEC8A4C
+
+#define mmTPC3_QM_ARB_MST_AVAIL_CRED_12 0xEC8A50
+
+#define mmTPC3_QM_ARB_MST_AVAIL_CRED_13 0xEC8A54
+
+#define mmTPC3_QM_ARB_MST_AVAIL_CRED_14 0xEC8A58
+
+#define mmTPC3_QM_ARB_MST_AVAIL_CRED_15 0xEC8A5C
+
+#define mmTPC3_QM_ARB_MST_AVAIL_CRED_16 0xEC8A60
+
+#define mmTPC3_QM_ARB_MST_AVAIL_CRED_17 0xEC8A64
+
+#define mmTPC3_QM_ARB_MST_AVAIL_CRED_18 0xEC8A68
+
+#define mmTPC3_QM_ARB_MST_AVAIL_CRED_19 0xEC8A6C
+
+#define mmTPC3_QM_ARB_MST_AVAIL_CRED_20 0xEC8A70
+
+#define mmTPC3_QM_ARB_MST_AVAIL_CRED_21 0xEC8A74
+
+#define mmTPC3_QM_ARB_MST_AVAIL_CRED_22 0xEC8A78
+
+#define mmTPC3_QM_ARB_MST_AVAIL_CRED_23 0xEC8A7C
+
+#define mmTPC3_QM_ARB_MST_AVAIL_CRED_24 0xEC8A80
+
+#define mmTPC3_QM_ARB_MST_AVAIL_CRED_25 0xEC8A84
+
+#define mmTPC3_QM_ARB_MST_AVAIL_CRED_26 0xEC8A88
+
+#define mmTPC3_QM_ARB_MST_AVAIL_CRED_27 0xEC8A8C
+
+#define mmTPC3_QM_ARB_MST_AVAIL_CRED_28 0xEC8A90
+
+#define mmTPC3_QM_ARB_MST_AVAIL_CRED_29 0xEC8A94
+
+#define mmTPC3_QM_ARB_MST_AVAIL_CRED_30 0xEC8A98
+
+#define mmTPC3_QM_ARB_MST_AVAIL_CRED_31 0xEC8A9C
+
+#define mmTPC3_QM_ARB_MST_CRED_INC 0xEC8AA0
+
+#define mmTPC3_QM_ARB_MST_CHOISE_PUSH_OFST_0 0xEC8AA4
+
+#define mmTPC3_QM_ARB_MST_CHOISE_PUSH_OFST_1 0xEC8AA8
+
+#define mmTPC3_QM_ARB_MST_CHOISE_PUSH_OFST_2 0xEC8AAC
+
+#define mmTPC3_QM_ARB_MST_CHOISE_PUSH_OFST_3 0xEC8AB0
+
+#define mmTPC3_QM_ARB_MST_CHOISE_PUSH_OFST_4 0xEC8AB4
+
+#define mmTPC3_QM_ARB_MST_CHOISE_PUSH_OFST_5 0xEC8AB8
+
+#define mmTPC3_QM_ARB_MST_CHOISE_PUSH_OFST_6 0xEC8ABC
+
+#define mmTPC3_QM_ARB_MST_CHOISE_PUSH_OFST_7 0xEC8AC0
+
+#define mmTPC3_QM_ARB_MST_CHOISE_PUSH_OFST_8 0xEC8AC4
+
+#define mmTPC3_QM_ARB_MST_CHOISE_PUSH_OFST_9 0xEC8AC8
+
+#define mmTPC3_QM_ARB_MST_CHOISE_PUSH_OFST_10 0xEC8ACC
+
+#define mmTPC3_QM_ARB_MST_CHOISE_PUSH_OFST_11 0xEC8AD0
+
+#define mmTPC3_QM_ARB_MST_CHOISE_PUSH_OFST_12 0xEC8AD4
+
+#define mmTPC3_QM_ARB_MST_CHOISE_PUSH_OFST_13 0xEC8AD8
+
+#define mmTPC3_QM_ARB_MST_CHOISE_PUSH_OFST_14 0xEC8ADC
+
+#define mmTPC3_QM_ARB_MST_CHOISE_PUSH_OFST_15 0xEC8AE0
+
+#define mmTPC3_QM_ARB_MST_CHOISE_PUSH_OFST_16 0xEC8AE4
+
+#define mmTPC3_QM_ARB_MST_CHOISE_PUSH_OFST_17 0xEC8AE8
+
+#define mmTPC3_QM_ARB_MST_CHOISE_PUSH_OFST_18 0xEC8AEC
+
+#define mmTPC3_QM_ARB_MST_CHOISE_PUSH_OFST_19 0xEC8AF0
+
+#define mmTPC3_QM_ARB_MST_CHOISE_PUSH_OFST_20 0xEC8AF4
+
+#define mmTPC3_QM_ARB_MST_CHOISE_PUSH_OFST_21 0xEC8AF8
+
+#define mmTPC3_QM_ARB_MST_CHOISE_PUSH_OFST_22 0xEC8AFC
+
+#define mmTPC3_QM_ARB_MST_CHOISE_PUSH_OFST_23 0xEC8B00
+
+#define mmTPC3_QM_ARB_MST_CHOISE_PUSH_OFST_24 0xEC8B04
+
+#define mmTPC3_QM_ARB_MST_CHOISE_PUSH_OFST_25 0xEC8B08
+
+#define mmTPC3_QM_ARB_MST_CHOISE_PUSH_OFST_26 0xEC8B0C
+
+#define mmTPC3_QM_ARB_MST_CHOISE_PUSH_OFST_27 0xEC8B10
+
+#define mmTPC3_QM_ARB_MST_CHOISE_PUSH_OFST_28 0xEC8B14
+
+#define mmTPC3_QM_ARB_MST_CHOISE_PUSH_OFST_29 0xEC8B18
+
+#define mmTPC3_QM_ARB_MST_CHOISE_PUSH_OFST_30 0xEC8B1C
+
+#define mmTPC3_QM_ARB_MST_CHOISE_PUSH_OFST_31 0xEC8B20
+
+#define mmTPC3_QM_ARB_SLV_MASTER_INC_CRED_OFST 0xEC8B28
+
+#define mmTPC3_QM_ARB_MST_SLAVE_EN 0xEC8B2C
+
+#define mmTPC3_QM_ARB_MST_QUIET_PER 0xEC8B34
+
+#define mmTPC3_QM_ARB_SLV_CHOISE_WDT 0xEC8B38
+
+#define mmTPC3_QM_ARB_SLV_ID 0xEC8B3C
+
+#define mmTPC3_QM_ARB_MSG_MAX_INFLIGHT 0xEC8B44
+
+#define mmTPC3_QM_ARB_MSG_AWUSER_31_11 0xEC8B48
+
+#define mmTPC3_QM_ARB_MSG_AWUSER_SEC_PROP 0xEC8B4C
+
+#define mmTPC3_QM_ARB_MSG_AWUSER_NON_SEC_PROP 0xEC8B50
+
+#define mmTPC3_QM_ARB_BASE_LO 0xEC8B54
+
+#define mmTPC3_QM_ARB_BASE_HI 0xEC8B58
+
+#define mmTPC3_QM_ARB_STATE_STS 0xEC8B80
+
+#define mmTPC3_QM_ARB_CHOISE_FULLNESS_STS 0xEC8B84
+
+#define mmTPC3_QM_ARB_MSG_STS 0xEC8B88
+
+#define mmTPC3_QM_ARB_SLV_CHOISE_Q_HEAD 0xEC8B8C
+
+#define mmTPC3_QM_ARB_ERR_CAUSE 0xEC8B9C
+
+#define mmTPC3_QM_ARB_ERR_MSG_EN 0xEC8BA0
+
+#define mmTPC3_QM_ARB_ERR_STS_DRP 0xEC8BA8
+
+#define mmTPC3_QM_ARB_MST_CRED_STS_0 0xEC8BB0
+
+#define mmTPC3_QM_ARB_MST_CRED_STS_1 0xEC8BB4
+
+#define mmTPC3_QM_ARB_MST_CRED_STS_2 0xEC8BB8
+
+#define mmTPC3_QM_ARB_MST_CRED_STS_3 0xEC8BBC
+
+#define mmTPC3_QM_ARB_MST_CRED_STS_4 0xEC8BC0
+
+#define mmTPC3_QM_ARB_MST_CRED_STS_5 0xEC8BC4
+
+#define mmTPC3_QM_ARB_MST_CRED_STS_6 0xEC8BC8
+
+#define mmTPC3_QM_ARB_MST_CRED_STS_7 0xEC8BCC
+
+#define mmTPC3_QM_ARB_MST_CRED_STS_8 0xEC8BD0
+
+#define mmTPC3_QM_ARB_MST_CRED_STS_9 0xEC8BD4
+
+#define mmTPC3_QM_ARB_MST_CRED_STS_10 0xEC8BD8
+
+#define mmTPC3_QM_ARB_MST_CRED_STS_11 0xEC8BDC
+
+#define mmTPC3_QM_ARB_MST_CRED_STS_12 0xEC8BE0
+
+#define mmTPC3_QM_ARB_MST_CRED_STS_13 0xEC8BE4
+
+#define mmTPC3_QM_ARB_MST_CRED_STS_14 0xEC8BE8
+
+#define mmTPC3_QM_ARB_MST_CRED_STS_15 0xEC8BEC
+
+#define mmTPC3_QM_ARB_MST_CRED_STS_16 0xEC8BF0
+
+#define mmTPC3_QM_ARB_MST_CRED_STS_17 0xEC8BF4
+
+#define mmTPC3_QM_ARB_MST_CRED_STS_18 0xEC8BF8
+
+#define mmTPC3_QM_ARB_MST_CRED_STS_19 0xEC8BFC
+
+#define mmTPC3_QM_ARB_MST_CRED_STS_20 0xEC8C00
+
+#define mmTPC3_QM_ARB_MST_CRED_STS_21 0xEC8C04
+
+#define mmTPC3_QM_ARB_MST_CRED_STS_22 0xEC8C08
+
+#define mmTPC3_QM_ARB_MST_CRED_STS_23 0xEC8C0C
+
+#define mmTPC3_QM_ARB_MST_CRED_STS_24 0xEC8C10
+
+#define mmTPC3_QM_ARB_MST_CRED_STS_25 0xEC8C14
+
+#define mmTPC3_QM_ARB_MST_CRED_STS_26 0xEC8C18
+
+#define mmTPC3_QM_ARB_MST_CRED_STS_27 0xEC8C1C
+
+#define mmTPC3_QM_ARB_MST_CRED_STS_28 0xEC8C20
+
+#define mmTPC3_QM_ARB_MST_CRED_STS_29 0xEC8C24
+
+#define mmTPC3_QM_ARB_MST_CRED_STS_30 0xEC8C28
+
+#define mmTPC3_QM_ARB_MST_CRED_STS_31 0xEC8C2C
+
+#define mmTPC3_QM_CGM_CFG 0xEC8C70
+
+#define mmTPC3_QM_CGM_STS 0xEC8C74
+
+#define mmTPC3_QM_CGM_CFG1 0xEC8C78
+
+#define mmTPC3_QM_LOCAL_RANGE_BASE 0xEC8C80
+
+#define mmTPC3_QM_LOCAL_RANGE_SIZE 0xEC8C84
+
+#define mmTPC3_QM_CSMR_STRICT_PRIO_CFG 0xEC8C90
+
+#define mmTPC3_QM_HBW_RD_RATE_LIM_CFG_1 0xEC8C94
+
+#define mmTPC3_QM_LBW_WR_RATE_LIM_CFG_0 0xEC8C98
+
+#define mmTPC3_QM_LBW_WR_RATE_LIM_CFG_1 0xEC8C9C
+
+#define mmTPC3_QM_HBW_RD_RATE_LIM_CFG_0 0xEC8CA0
+
+#define mmTPC3_QM_GLBL_AXCACHE 0xEC8CA4
+
+#define mmTPC3_QM_IND_GW_APB_CFG 0xEC8CB0
+
+#define mmTPC3_QM_IND_GW_APB_WDATA 0xEC8CB4
+
+#define mmTPC3_QM_IND_GW_APB_RDATA 0xEC8CB8
+
+#define mmTPC3_QM_IND_GW_APB_STATUS 0xEC8CBC
+
+#define mmTPC3_QM_GLBL_ERR_ADDR_LO 0xEC8CD0
+
+#define mmTPC3_QM_GLBL_ERR_ADDR_HI 0xEC8CD4
+
+#define mmTPC3_QM_GLBL_ERR_WDATA 0xEC8CD8
+
+#define mmTPC3_QM_GLBL_MEM_INIT_BUSY 0xEC8D00
+
+#endif /* ASIC_REG_TPC3_QM_REGS_H_ */
diff --git a/drivers/accel/habanalabs/include/gaudi/asic_reg/tpc4_cfg_regs.h b/drivers/accel/habanalabs/include/gaudi/asic_reg/tpc4_cfg_regs.h
new file mode 100644
index 0000000000..7a9447f39a
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi/asic_reg/tpc4_cfg_regs.h
@@ -0,0 +1,1226 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2016-2018 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ ** DO NOT EDIT BELOW **
+ ************************************/
+
+#ifndef ASIC_REG_TPC4_CFG_REGS_H_
+#define ASIC_REG_TPC4_CFG_REGS_H_
+
+/*
+ *****************************************
+ * TPC4_CFG (Prototype: TPC)
+ *****************************************
+ */
+
+#define mmTPC4_CFG_KERNEL_TENSOR_0_BASE_ADDR_LOW 0xF06400
+
+#define mmTPC4_CFG_KERNEL_TENSOR_0_BASE_ADDR_HIGH 0xF06404
+
+#define mmTPC4_CFG_KERNEL_TENSOR_0_PADDING_VALUE 0xF06408
+
+#define mmTPC4_CFG_KERNEL_TENSOR_0_TENSOR_CONFIG 0xF0640C
+
+#define mmTPC4_CFG_KERNEL_TENSOR_0_DIM_0_SIZE 0xF06410
+
+#define mmTPC4_CFG_KERNEL_TENSOR_0_DIM_0_STRIDE 0xF06414
+
+#define mmTPC4_CFG_KERNEL_TENSOR_0_DIM_1_SIZE 0xF06418
+
+#define mmTPC4_CFG_KERNEL_TENSOR_0_DIM_1_STRIDE 0xF0641C
+
+#define mmTPC4_CFG_KERNEL_TENSOR_0_DIM_2_SIZE 0xF06420
+
+#define mmTPC4_CFG_KERNEL_TENSOR_0_DIM_2_STRIDE 0xF06424
+
+#define mmTPC4_CFG_KERNEL_TENSOR_0_DIM_3_SIZE 0xF06428
+
+#define mmTPC4_CFG_KERNEL_TENSOR_0_DIM_3_STRIDE 0xF0642C
+
+#define mmTPC4_CFG_KERNEL_TENSOR_0_DIM_4_SIZE 0xF06430
+
+#define mmTPC4_CFG_KERNEL_TENSOR_0_DIM_4_STRIDE 0xF06434
+
+#define mmTPC4_CFG_KERNEL_TENSOR_1_BASE_ADDR_LOW 0xF06438
+
+#define mmTPC4_CFG_KERNEL_TENSOR_1_BASE_ADDR_HIGH 0xF0643C
+
+#define mmTPC4_CFG_KERNEL_TENSOR_1_PADDING_VALUE 0xF06440
+
+#define mmTPC4_CFG_KERNEL_TENSOR_1_TENSOR_CONFIG 0xF06444
+
+#define mmTPC4_CFG_KERNEL_TENSOR_1_DIM_0_SIZE 0xF06448
+
+#define mmTPC4_CFG_KERNEL_TENSOR_1_DIM_0_STRIDE 0xF0644C
+
+#define mmTPC4_CFG_KERNEL_TENSOR_1_DIM_1_SIZE 0xF06450
+
+#define mmTPC4_CFG_KERNEL_TENSOR_1_DIM_1_STRIDE 0xF06454
+
+#define mmTPC4_CFG_KERNEL_TENSOR_1_DIM_2_SIZE 0xF06458
+
+#define mmTPC4_CFG_KERNEL_TENSOR_1_DIM_2_STRIDE 0xF0645C
+
+#define mmTPC4_CFG_KERNEL_TENSOR_1_DIM_3_SIZE 0xF06460
+
+#define mmTPC4_CFG_KERNEL_TENSOR_1_DIM_3_STRIDE 0xF06464
+
+#define mmTPC4_CFG_KERNEL_TENSOR_1_DIM_4_SIZE 0xF06468
+
+#define mmTPC4_CFG_KERNEL_TENSOR_1_DIM_4_STRIDE 0xF0646C
+
+#define mmTPC4_CFG_KERNEL_TENSOR_2_BASE_ADDR_LOW 0xF06470
+
+#define mmTPC4_CFG_KERNEL_TENSOR_2_BASE_ADDR_HIGH 0xF06474
+
+#define mmTPC4_CFG_KERNEL_TENSOR_2_PADDING_VALUE 0xF06478
+
+#define mmTPC4_CFG_KERNEL_TENSOR_2_TENSOR_CONFIG 0xF0647C
+
+#define mmTPC4_CFG_KERNEL_TENSOR_2_DIM_0_SIZE 0xF06480
+
+#define mmTPC4_CFG_KERNEL_TENSOR_2_DIM_0_STRIDE 0xF06484
+
+#define mmTPC4_CFG_KERNEL_TENSOR_2_DIM_1_SIZE 0xF06488
+
+#define mmTPC4_CFG_KERNEL_TENSOR_2_DIM_1_STRIDE 0xF0648C
+
+#define mmTPC4_CFG_KERNEL_TENSOR_2_DIM_2_SIZE 0xF06490
+
+#define mmTPC4_CFG_KERNEL_TENSOR_2_DIM_2_STRIDE 0xF06494
+
+#define mmTPC4_CFG_KERNEL_TENSOR_2_DIM_3_SIZE 0xF06498
+
+#define mmTPC4_CFG_KERNEL_TENSOR_2_DIM_3_STRIDE 0xF0649C
+
+#define mmTPC4_CFG_KERNEL_TENSOR_2_DIM_4_SIZE 0xF064A0
+
+#define mmTPC4_CFG_KERNEL_TENSOR_2_DIM_4_STRIDE 0xF064A4
+
+#define mmTPC4_CFG_KERNEL_TENSOR_3_BASE_ADDR_LOW 0xF064A8
+
+#define mmTPC4_CFG_KERNEL_TENSOR_3_BASE_ADDR_HIGH 0xF064AC
+
+#define mmTPC4_CFG_KERNEL_TENSOR_3_PADDING_VALUE 0xF064B0
+
+#define mmTPC4_CFG_KERNEL_TENSOR_3_TENSOR_CONFIG 0xF064B4
+
+#define mmTPC4_CFG_KERNEL_TENSOR_3_DIM_0_SIZE 0xF064B8
+
+#define mmTPC4_CFG_KERNEL_TENSOR_3_DIM_0_STRIDE 0xF064BC
+
+#define mmTPC4_CFG_KERNEL_TENSOR_3_DIM_1_SIZE 0xF064C0
+
+#define mmTPC4_CFG_KERNEL_TENSOR_3_DIM_1_STRIDE 0xF064C4
+
+#define mmTPC4_CFG_KERNEL_TENSOR_3_DIM_2_SIZE 0xF064C8
+
+#define mmTPC4_CFG_KERNEL_TENSOR_3_DIM_2_STRIDE 0xF064CC
+
+#define mmTPC4_CFG_KERNEL_TENSOR_3_DIM_3_SIZE 0xF064D0
+
+#define mmTPC4_CFG_KERNEL_TENSOR_3_DIM_3_STRIDE 0xF064D4
+
+#define mmTPC4_CFG_KERNEL_TENSOR_3_DIM_4_SIZE 0xF064D8
+
+#define mmTPC4_CFG_KERNEL_TENSOR_3_DIM_4_STRIDE 0xF064DC
+
+#define mmTPC4_CFG_KERNEL_TENSOR_4_BASE_ADDR_LOW 0xF064E0
+
+#define mmTPC4_CFG_KERNEL_TENSOR_4_BASE_ADDR_HIGH 0xF064E4
+
+#define mmTPC4_CFG_KERNEL_TENSOR_4_PADDING_VALUE 0xF064E8
+
+#define mmTPC4_CFG_KERNEL_TENSOR_4_TENSOR_CONFIG 0xF064EC
+
+#define mmTPC4_CFG_KERNEL_TENSOR_4_DIM_0_SIZE 0xF064F0
+
+#define mmTPC4_CFG_KERNEL_TENSOR_4_DIM_0_STRIDE 0xF064F4
+
+#define mmTPC4_CFG_KERNEL_TENSOR_4_DIM_1_SIZE 0xF064F8
+
+#define mmTPC4_CFG_KERNEL_TENSOR_4_DIM_1_STRIDE 0xF064FC
+
+#define mmTPC4_CFG_KERNEL_TENSOR_4_DIM_2_SIZE 0xF06500
+
+#define mmTPC4_CFG_KERNEL_TENSOR_4_DIM_2_STRIDE 0xF06504
+
+#define mmTPC4_CFG_KERNEL_TENSOR_4_DIM_3_SIZE 0xF06508
+
+#define mmTPC4_CFG_KERNEL_TENSOR_4_DIM_3_STRIDE 0xF0650C
+
+#define mmTPC4_CFG_KERNEL_TENSOR_4_DIM_4_SIZE 0xF06510
+
+#define mmTPC4_CFG_KERNEL_TENSOR_4_DIM_4_STRIDE 0xF06514
+
+#define mmTPC4_CFG_KERNEL_TENSOR_5_BASE_ADDR_LOW 0xF06518
+
+#define mmTPC4_CFG_KERNEL_TENSOR_5_BASE_ADDR_HIGH 0xF0651C
+
+#define mmTPC4_CFG_KERNEL_TENSOR_5_PADDING_VALUE 0xF06520
+
+#define mmTPC4_CFG_KERNEL_TENSOR_5_TENSOR_CONFIG 0xF06524
+
+#define mmTPC4_CFG_KERNEL_TENSOR_5_DIM_0_SIZE 0xF06528
+
+#define mmTPC4_CFG_KERNEL_TENSOR_5_DIM_0_STRIDE 0xF0652C
+
+#define mmTPC4_CFG_KERNEL_TENSOR_5_DIM_1_SIZE 0xF06530
+
+#define mmTPC4_CFG_KERNEL_TENSOR_5_DIM_1_STRIDE 0xF06534
+
+#define mmTPC4_CFG_KERNEL_TENSOR_5_DIM_2_SIZE 0xF06538
+
+#define mmTPC4_CFG_KERNEL_TENSOR_5_DIM_2_STRIDE 0xF0653C
+
+#define mmTPC4_CFG_KERNEL_TENSOR_5_DIM_3_SIZE 0xF06540
+
+#define mmTPC4_CFG_KERNEL_TENSOR_5_DIM_3_STRIDE 0xF06544
+
+#define mmTPC4_CFG_KERNEL_TENSOR_5_DIM_4_SIZE 0xF06548
+
+#define mmTPC4_CFG_KERNEL_TENSOR_5_DIM_4_STRIDE 0xF0654C
+
+#define mmTPC4_CFG_KERNEL_TENSOR_6_BASE_ADDR_LOW 0xF06550
+
+#define mmTPC4_CFG_KERNEL_TENSOR_6_BASE_ADDR_HIGH 0xF06554
+
+#define mmTPC4_CFG_KERNEL_TENSOR_6_PADDING_VALUE 0xF06558
+
+#define mmTPC4_CFG_KERNEL_TENSOR_6_TENSOR_CONFIG 0xF0655C
+
+#define mmTPC4_CFG_KERNEL_TENSOR_6_DIM_0_SIZE 0xF06560
+
+#define mmTPC4_CFG_KERNEL_TENSOR_6_DIM_0_STRIDE 0xF06564
+
+#define mmTPC4_CFG_KERNEL_TENSOR_6_DIM_1_SIZE 0xF06568
+
+#define mmTPC4_CFG_KERNEL_TENSOR_6_DIM_1_STRIDE 0xF0656C
+
+#define mmTPC4_CFG_KERNEL_TENSOR_6_DIM_2_SIZE 0xF06570
+
+#define mmTPC4_CFG_KERNEL_TENSOR_6_DIM_2_STRIDE 0xF06574
+
+#define mmTPC4_CFG_KERNEL_TENSOR_6_DIM_3_SIZE 0xF06578
+
+#define mmTPC4_CFG_KERNEL_TENSOR_6_DIM_3_STRIDE 0xF0657C
+
+#define mmTPC4_CFG_KERNEL_TENSOR_6_DIM_4_SIZE 0xF06580
+
+#define mmTPC4_CFG_KERNEL_TENSOR_6_DIM_4_STRIDE 0xF06584
+
+#define mmTPC4_CFG_KERNEL_TENSOR_7_BASE_ADDR_LOW 0xF06588
+
+#define mmTPC4_CFG_KERNEL_TENSOR_7_BASE_ADDR_HIGH 0xF0658C
+
+#define mmTPC4_CFG_KERNEL_TENSOR_7_PADDING_VALUE 0xF06590
+
+#define mmTPC4_CFG_KERNEL_TENSOR_7_TENSOR_CONFIG 0xF06594
+
+#define mmTPC4_CFG_KERNEL_TENSOR_7_DIM_0_SIZE 0xF06598
+
+#define mmTPC4_CFG_KERNEL_TENSOR_7_DIM_0_STRIDE 0xF0659C
+
+#define mmTPC4_CFG_KERNEL_TENSOR_7_DIM_1_SIZE 0xF065A0
+
+#define mmTPC4_CFG_KERNEL_TENSOR_7_DIM_1_STRIDE 0xF065A4
+
+#define mmTPC4_CFG_KERNEL_TENSOR_7_DIM_2_SIZE 0xF065A8
+
+#define mmTPC4_CFG_KERNEL_TENSOR_7_DIM_2_STRIDE 0xF065AC
+
+#define mmTPC4_CFG_KERNEL_TENSOR_7_DIM_3_SIZE 0xF065B0
+
+#define mmTPC4_CFG_KERNEL_TENSOR_7_DIM_3_STRIDE 0xF065B4
+
+#define mmTPC4_CFG_KERNEL_TENSOR_7_DIM_4_SIZE 0xF065B8
+
+#define mmTPC4_CFG_KERNEL_TENSOR_7_DIM_4_STRIDE 0xF065BC
+
+#define mmTPC4_CFG_KERNEL_TENSOR_8_BASE_ADDR_LOW 0xF065C0
+
+#define mmTPC4_CFG_KERNEL_TENSOR_8_BASE_ADDR_HIGH 0xF065C4
+
+#define mmTPC4_CFG_KERNEL_TENSOR_8_PADDING_VALUE 0xF065C8
+
+#define mmTPC4_CFG_KERNEL_TENSOR_8_TENSOR_CONFIG 0xF065CC
+
+#define mmTPC4_CFG_KERNEL_TENSOR_8_DIM_0_SIZE 0xF065D0
+
+#define mmTPC4_CFG_KERNEL_TENSOR_8_DIM_0_STRIDE 0xF065D4
+
+#define mmTPC4_CFG_KERNEL_TENSOR_8_DIM_1_SIZE 0xF065D8
+
+#define mmTPC4_CFG_KERNEL_TENSOR_8_DIM_1_STRIDE 0xF065DC
+
+#define mmTPC4_CFG_KERNEL_TENSOR_8_DIM_2_SIZE 0xF065E0
+
+#define mmTPC4_CFG_KERNEL_TENSOR_8_DIM_2_STRIDE 0xF065E4
+
+#define mmTPC4_CFG_KERNEL_TENSOR_8_DIM_3_SIZE 0xF065E8
+
+#define mmTPC4_CFG_KERNEL_TENSOR_8_DIM_3_STRIDE 0xF065EC
+
+#define mmTPC4_CFG_KERNEL_TENSOR_8_DIM_4_SIZE 0xF065F0
+
+#define mmTPC4_CFG_KERNEL_TENSOR_8_DIM_4_STRIDE 0xF065F4
+
+#define mmTPC4_CFG_KERNEL_TENSOR_9_BASE_ADDR_LOW 0xF065F8
+
+#define mmTPC4_CFG_KERNEL_TENSOR_9_BASE_ADDR_HIGH 0xF065FC
+
+#define mmTPC4_CFG_KERNEL_TENSOR_9_PADDING_VALUE 0xF06600
+
+#define mmTPC4_CFG_KERNEL_TENSOR_9_TENSOR_CONFIG 0xF06604
+
+#define mmTPC4_CFG_KERNEL_TENSOR_9_DIM_0_SIZE 0xF06608
+
+#define mmTPC4_CFG_KERNEL_TENSOR_9_DIM_0_STRIDE 0xF0660C
+
+#define mmTPC4_CFG_KERNEL_TENSOR_9_DIM_1_SIZE 0xF06610
+
+#define mmTPC4_CFG_KERNEL_TENSOR_9_DIM_1_STRIDE 0xF06614
+
+#define mmTPC4_CFG_KERNEL_TENSOR_9_DIM_2_SIZE 0xF06618
+
+#define mmTPC4_CFG_KERNEL_TENSOR_9_DIM_2_STRIDE 0xF0661C
+
+#define mmTPC4_CFG_KERNEL_TENSOR_9_DIM_3_SIZE 0xF06620
+
+#define mmTPC4_CFG_KERNEL_TENSOR_9_DIM_3_STRIDE 0xF06624
+
+#define mmTPC4_CFG_KERNEL_TENSOR_9_DIM_4_SIZE 0xF06628
+
+#define mmTPC4_CFG_KERNEL_TENSOR_9_DIM_4_STRIDE 0xF0662C
+
+#define mmTPC4_CFG_KERNEL_TENSOR_10_BASE_ADDR_LOW 0xF06630
+
+#define mmTPC4_CFG_KERNEL_TENSOR_10_BASE_ADDR_HIGH 0xF06634
+
+#define mmTPC4_CFG_KERNEL_TENSOR_10_PADDING_VALUE 0xF06638
+
+#define mmTPC4_CFG_KERNEL_TENSOR_10_TENSOR_CONFIG 0xF0663C
+
+#define mmTPC4_CFG_KERNEL_TENSOR_10_DIM_0_SIZE 0xF06640
+
+#define mmTPC4_CFG_KERNEL_TENSOR_10_DIM_0_STRIDE 0xF06644
+
+#define mmTPC4_CFG_KERNEL_TENSOR_10_DIM_1_SIZE 0xF06648
+
+#define mmTPC4_CFG_KERNEL_TENSOR_10_DIM_1_STRIDE 0xF0664C
+
+#define mmTPC4_CFG_KERNEL_TENSOR_10_DIM_2_SIZE 0xF06650
+
+#define mmTPC4_CFG_KERNEL_TENSOR_10_DIM_2_STRIDE 0xF06654
+
+#define mmTPC4_CFG_KERNEL_TENSOR_10_DIM_3_SIZE 0xF06658
+
+#define mmTPC4_CFG_KERNEL_TENSOR_10_DIM_3_STRIDE 0xF0665C
+
+#define mmTPC4_CFG_KERNEL_TENSOR_10_DIM_4_SIZE 0xF06660
+
+#define mmTPC4_CFG_KERNEL_TENSOR_10_DIM_4_STRIDE 0xF06664
+
+#define mmTPC4_CFG_KERNEL_TENSOR_11_BASE_ADDR_LOW 0xF06668
+
+#define mmTPC4_CFG_KERNEL_TENSOR_11_BASE_ADDR_HIGH 0xF0666C
+
+#define mmTPC4_CFG_KERNEL_TENSOR_11_PADDING_VALUE 0xF06670
+
+#define mmTPC4_CFG_KERNEL_TENSOR_11_TENSOR_CONFIG 0xF06674
+
+#define mmTPC4_CFG_KERNEL_TENSOR_11_DIM_0_SIZE 0xF06678
+
+#define mmTPC4_CFG_KERNEL_TENSOR_11_DIM_0_STRIDE 0xF0667C
+
+#define mmTPC4_CFG_KERNEL_TENSOR_11_DIM_1_SIZE 0xF06680
+
+#define mmTPC4_CFG_KERNEL_TENSOR_11_DIM_1_STRIDE 0xF06684
+
+#define mmTPC4_CFG_KERNEL_TENSOR_11_DIM_2_SIZE 0xF06688
+
+#define mmTPC4_CFG_KERNEL_TENSOR_11_DIM_2_STRIDE 0xF0668C
+
+#define mmTPC4_CFG_KERNEL_TENSOR_11_DIM_3_SIZE 0xF06690
+
+#define mmTPC4_CFG_KERNEL_TENSOR_11_DIM_3_STRIDE 0xF06694
+
+#define mmTPC4_CFG_KERNEL_TENSOR_11_DIM_4_SIZE 0xF06698
+
+#define mmTPC4_CFG_KERNEL_TENSOR_11_DIM_4_STRIDE 0xF0669C
+
+#define mmTPC4_CFG_KERNEL_TENSOR_12_BASE_ADDR_LOW 0xF066A0
+
+#define mmTPC4_CFG_KERNEL_TENSOR_12_BASE_ADDR_HIGH 0xF066A4
+
+#define mmTPC4_CFG_KERNEL_TENSOR_12_PADDING_VALUE 0xF066A8
+
+#define mmTPC4_CFG_KERNEL_TENSOR_12_TENSOR_CONFIG 0xF066AC
+
+#define mmTPC4_CFG_KERNEL_TENSOR_12_DIM_0_SIZE 0xF066B0
+
+#define mmTPC4_CFG_KERNEL_TENSOR_12_DIM_0_STRIDE 0xF066B4
+
+#define mmTPC4_CFG_KERNEL_TENSOR_12_DIM_1_SIZE 0xF066B8
+
+#define mmTPC4_CFG_KERNEL_TENSOR_12_DIM_1_STRIDE 0xF066BC
+
+#define mmTPC4_CFG_KERNEL_TENSOR_12_DIM_2_SIZE 0xF066C0
+
+#define mmTPC4_CFG_KERNEL_TENSOR_12_DIM_2_STRIDE 0xF066C4
+
+#define mmTPC4_CFG_KERNEL_TENSOR_12_DIM_3_SIZE 0xF066C8
+
+#define mmTPC4_CFG_KERNEL_TENSOR_12_DIM_3_STRIDE 0xF066CC
+
+#define mmTPC4_CFG_KERNEL_TENSOR_12_DIM_4_SIZE 0xF066D0
+
+#define mmTPC4_CFG_KERNEL_TENSOR_12_DIM_4_STRIDE 0xF066D4
+
+#define mmTPC4_CFG_KERNEL_TENSOR_13_BASE_ADDR_LOW 0xF066D8
+
+#define mmTPC4_CFG_KERNEL_TENSOR_13_BASE_ADDR_HIGH 0xF066DC
+
+#define mmTPC4_CFG_KERNEL_TENSOR_13_PADDING_VALUE 0xF066E0
+
+#define mmTPC4_CFG_KERNEL_TENSOR_13_TENSOR_CONFIG 0xF066E4
+
+#define mmTPC4_CFG_KERNEL_TENSOR_13_DIM_0_SIZE 0xF066E8
+
+#define mmTPC4_CFG_KERNEL_TENSOR_13_DIM_0_STRIDE 0xF066EC
+
+#define mmTPC4_CFG_KERNEL_TENSOR_13_DIM_1_SIZE 0xF066F0
+
+#define mmTPC4_CFG_KERNEL_TENSOR_13_DIM_1_STRIDE 0xF066F4
+
+#define mmTPC4_CFG_KERNEL_TENSOR_13_DIM_2_SIZE 0xF066F8
+
+#define mmTPC4_CFG_KERNEL_TENSOR_13_DIM_2_STRIDE 0xF066FC
+
+#define mmTPC4_CFG_KERNEL_TENSOR_13_DIM_3_SIZE 0xF06700
+
+#define mmTPC4_CFG_KERNEL_TENSOR_13_DIM_3_STRIDE 0xF06704
+
+#define mmTPC4_CFG_KERNEL_TENSOR_13_DIM_4_SIZE 0xF06708
+
+#define mmTPC4_CFG_KERNEL_TENSOR_13_DIM_4_STRIDE 0xF0670C
+
+#define mmTPC4_CFG_KERNEL_TENSOR_14_BASE_ADDR_LOW 0xF06710
+
+#define mmTPC4_CFG_KERNEL_TENSOR_14_BASE_ADDR_HIGH 0xF06714
+
+#define mmTPC4_CFG_KERNEL_TENSOR_14_PADDING_VALUE 0xF06718
+
+#define mmTPC4_CFG_KERNEL_TENSOR_14_TENSOR_CONFIG 0xF0671C
+
+#define mmTPC4_CFG_KERNEL_TENSOR_14_DIM_0_SIZE 0xF06720
+
+#define mmTPC4_CFG_KERNEL_TENSOR_14_DIM_0_STRIDE 0xF06724
+
+#define mmTPC4_CFG_KERNEL_TENSOR_14_DIM_1_SIZE 0xF06728
+
+#define mmTPC4_CFG_KERNEL_TENSOR_14_DIM_1_STRIDE 0xF0672C
+
+#define mmTPC4_CFG_KERNEL_TENSOR_14_DIM_2_SIZE 0xF06730
+
+#define mmTPC4_CFG_KERNEL_TENSOR_14_DIM_2_STRIDE 0xF06734
+
+#define mmTPC4_CFG_KERNEL_TENSOR_14_DIM_3_SIZE 0xF06738
+
+#define mmTPC4_CFG_KERNEL_TENSOR_14_DIM_3_STRIDE 0xF0673C
+
+#define mmTPC4_CFG_KERNEL_TENSOR_14_DIM_4_SIZE 0xF06740
+
+#define mmTPC4_CFG_KERNEL_TENSOR_14_DIM_4_STRIDE 0xF06744
+
+#define mmTPC4_CFG_KERNEL_TENSOR_15_BASE_ADDR_LOW 0xF06748
+
+#define mmTPC4_CFG_KERNEL_TENSOR_15_BASE_ADDR_HIGH 0xF0674C
+
+#define mmTPC4_CFG_KERNEL_TENSOR_15_PADDING_VALUE 0xF06750
+
+#define mmTPC4_CFG_KERNEL_TENSOR_15_TENSOR_CONFIG 0xF06754
+
+#define mmTPC4_CFG_KERNEL_TENSOR_15_DIM_0_SIZE 0xF06758
+
+#define mmTPC4_CFG_KERNEL_TENSOR_15_DIM_0_STRIDE 0xF0675C
+
+#define mmTPC4_CFG_KERNEL_TENSOR_15_DIM_1_SIZE 0xF06760
+
+#define mmTPC4_CFG_KERNEL_TENSOR_15_DIM_1_STRIDE 0xF06764
+
+#define mmTPC4_CFG_KERNEL_TENSOR_15_DIM_2_SIZE 0xF06768
+
+#define mmTPC4_CFG_KERNEL_TENSOR_15_DIM_2_STRIDE 0xF0676C
+
+#define mmTPC4_CFG_KERNEL_TENSOR_15_DIM_3_SIZE 0xF06770
+
+#define mmTPC4_CFG_KERNEL_TENSOR_15_DIM_3_STRIDE 0xF06774
+
+#define mmTPC4_CFG_KERNEL_TENSOR_15_DIM_4_SIZE 0xF06778
+
+#define mmTPC4_CFG_KERNEL_TENSOR_15_DIM_4_STRIDE 0xF0677C
+
+#define mmTPC4_CFG_KERNEL_SYNC_OBJECT_MESSAGE 0xF06780
+
+#define mmTPC4_CFG_KERNEL_SYNC_OBJECT_ADDR 0xF06784
+
+#define mmTPC4_CFG_KERNEL_KERNEL_BASE_ADDRESS_LOW 0xF06788
+
+#define mmTPC4_CFG_KERNEL_KERNEL_BASE_ADDRESS_HIGH 0xF0678C
+
+#define mmTPC4_CFG_KERNEL_TID_BASE_DIM_0 0xF06790
+
+#define mmTPC4_CFG_KERNEL_TID_SIZE_DIM_0 0xF06794
+
+#define mmTPC4_CFG_KERNEL_TID_BASE_DIM_1 0xF06798
+
+#define mmTPC4_CFG_KERNEL_TID_SIZE_DIM_1 0xF0679C
+
+#define mmTPC4_CFG_KERNEL_TID_BASE_DIM_2 0xF067A0
+
+#define mmTPC4_CFG_KERNEL_TID_SIZE_DIM_2 0xF067A4
+
+#define mmTPC4_CFG_KERNEL_TID_BASE_DIM_3 0xF067A8
+
+#define mmTPC4_CFG_KERNEL_TID_SIZE_DIM_3 0xF067AC
+
+#define mmTPC4_CFG_KERNEL_TID_BASE_DIM_4 0xF067B0
+
+#define mmTPC4_CFG_KERNEL_TID_SIZE_DIM_4 0xF067B4
+
+#define mmTPC4_CFG_KERNEL_KERNEL_CONFIG 0xF067B8
+
+#define mmTPC4_CFG_KERNEL_KERNEL_ID 0xF067BC
+
+#define mmTPC4_CFG_KERNEL_SRF_0 0xF067C0
+
+#define mmTPC4_CFG_KERNEL_SRF_1 0xF067C4
+
+#define mmTPC4_CFG_KERNEL_SRF_2 0xF067C8
+
+#define mmTPC4_CFG_KERNEL_SRF_3 0xF067CC
+
+#define mmTPC4_CFG_KERNEL_SRF_4 0xF067D0
+
+#define mmTPC4_CFG_KERNEL_SRF_5 0xF067D4
+
+#define mmTPC4_CFG_KERNEL_SRF_6 0xF067D8
+
+#define mmTPC4_CFG_KERNEL_SRF_7 0xF067DC
+
+#define mmTPC4_CFG_KERNEL_SRF_8 0xF067E0
+
+#define mmTPC4_CFG_KERNEL_SRF_9 0xF067E4
+
+#define mmTPC4_CFG_KERNEL_SRF_10 0xF067E8
+
+#define mmTPC4_CFG_KERNEL_SRF_11 0xF067EC
+
+#define mmTPC4_CFG_KERNEL_SRF_12 0xF067F0
+
+#define mmTPC4_CFG_KERNEL_SRF_13 0xF067F4
+
+#define mmTPC4_CFG_KERNEL_SRF_14 0xF067F8
+
+#define mmTPC4_CFG_KERNEL_SRF_15 0xF067FC
+
+#define mmTPC4_CFG_KERNEL_SRF_16 0xF06800
+
+#define mmTPC4_CFG_KERNEL_SRF_17 0xF06804
+
+#define mmTPC4_CFG_KERNEL_SRF_18 0xF06808
+
+#define mmTPC4_CFG_KERNEL_SRF_19 0xF0680C
+
+#define mmTPC4_CFG_KERNEL_SRF_20 0xF06810
+
+#define mmTPC4_CFG_KERNEL_SRF_21 0xF06814
+
+#define mmTPC4_CFG_KERNEL_SRF_22 0xF06818
+
+#define mmTPC4_CFG_KERNEL_SRF_23 0xF0681C
+
+#define mmTPC4_CFG_KERNEL_SRF_24 0xF06820
+
+#define mmTPC4_CFG_KERNEL_SRF_25 0xF06824
+
+#define mmTPC4_CFG_KERNEL_SRF_26 0xF06828
+
+#define mmTPC4_CFG_KERNEL_SRF_27 0xF0682C
+
+#define mmTPC4_CFG_KERNEL_SRF_28 0xF06830
+
+#define mmTPC4_CFG_KERNEL_SRF_29 0xF06834
+
+#define mmTPC4_CFG_KERNEL_SRF_30 0xF06838
+
+#define mmTPC4_CFG_KERNEL_SRF_31 0xF0683C
+
+#define mmTPC4_CFG_ROUND_CSR 0xF068FC
+
+#define mmTPC4_CFG_PROT 0xF06900
+
+#define mmTPC4_CFG_SEMAPHORE 0xF06908
+
+#define mmTPC4_CFG_VFLAGS 0xF0690C
+
+#define mmTPC4_CFG_SFLAGS 0xF06910
+
+#define mmTPC4_CFG_LFSR_POLYNOM 0xF06918
+
+#define mmTPC4_CFG_STATUS 0xF0691C
+
+#define mmTPC4_CFG_CFG_BASE_ADDRESS_HIGH 0xF06920
+
+#define mmTPC4_CFG_CFG_SUBTRACT_VALUE 0xF06924
+
+#define mmTPC4_CFG_SM_BASE_ADDRESS_HIGH 0xF0692C
+
+#define mmTPC4_CFG_TPC_CMD 0xF06930
+
+#define mmTPC4_CFG_TPC_EXECUTE 0xF06938
+
+#define mmTPC4_CFG_TPC_STALL 0xF0693C
+
+#define mmTPC4_CFG_ICACHE_BASE_ADDERESS_LOW 0xF06940
+
+#define mmTPC4_CFG_ICACHE_BASE_ADDERESS_HIGH 0xF06944
+
+#define mmTPC4_CFG_RD_RATE_LIMIT 0xF06948
+
+#define mmTPC4_CFG_WR_RATE_LIMIT 0xF06950
+
+#define mmTPC4_CFG_MSS_CONFIG 0xF06954
+
+#define mmTPC4_CFG_TPC_INTR_CAUSE 0xF06958
+
+#define mmTPC4_CFG_TPC_INTR_MASK 0xF0695C
+
+#define mmTPC4_CFG_WQ_CREDITS 0xF06960
+
+#define mmTPC4_CFG_ARUSER_LO 0xF06964
+
+#define mmTPC4_CFG_ARUSER_HI 0xF06968
+
+#define mmTPC4_CFG_AWUSER_LO 0xF0696C
+
+#define mmTPC4_CFG_AWUSER_HI 0xF06970
+
+#define mmTPC4_CFG_OPCODE_EXEC 0xF06974
+
+#define mmTPC4_CFG_LUT_FUNC32_BASE_ADDR_LO 0xF06978
+
+#define mmTPC4_CFG_LUT_FUNC32_BASE_ADDR_HI 0xF0697C
+
+#define mmTPC4_CFG_LUT_FUNC64_BASE_ADDR_LO 0xF06980
+
+#define mmTPC4_CFG_LUT_FUNC64_BASE_ADDR_HI 0xF06984
+
+#define mmTPC4_CFG_LUT_FUNC128_BASE_ADDR_LO 0xF06988
+
+#define mmTPC4_CFG_LUT_FUNC128_BASE_ADDR_HI 0xF0698C
+
+#define mmTPC4_CFG_LUT_FUNC256_BASE_ADDR_LO 0xF06990
+
+#define mmTPC4_CFG_LUT_FUNC256_BASE_ADDR_HI 0xF06994
+
+#define mmTPC4_CFG_TSB_CFG_MAX_SIZE 0xF06998
+
+#define mmTPC4_CFG_TSB_CFG 0xF0699C
+
+#define mmTPC4_CFG_DBGMEM_ADD 0xF069A0
+
+#define mmTPC4_CFG_DBGMEM_DATA_WR 0xF069A4
+
+#define mmTPC4_CFG_DBGMEM_DATA_RD 0xF069A8
+
+#define mmTPC4_CFG_DBGMEM_CTRL 0xF069AC
+
+#define mmTPC4_CFG_DBGMEM_RC 0xF069B0
+
+#define mmTPC4_CFG_TSB_INFLIGHT_CNTR 0xF069B4
+
+#define mmTPC4_CFG_WQ_INFLIGHT_CNTR 0xF069B8
+
+#define mmTPC4_CFG_WQ_LBW_TOTAL_CNTR 0xF069BC
+
+#define mmTPC4_CFG_WQ_HBW_TOTAL_CNTR 0xF069C0
+
+#define mmTPC4_CFG_IRQ_OCCOUPY_CNTR 0xF069C4
+
+#define mmTPC4_CFG_FUNC_MBIST_CNTRL 0xF069D0
+
+#define mmTPC4_CFG_FUNC_MBIST_PAT 0xF069D4
+
+#define mmTPC4_CFG_FUNC_MBIST_MEM_0 0xF069D8
+
+#define mmTPC4_CFG_FUNC_MBIST_MEM_1 0xF069DC
+
+#define mmTPC4_CFG_FUNC_MBIST_MEM_2 0xF069E0
+
+#define mmTPC4_CFG_FUNC_MBIST_MEM_3 0xF069E4
+
+#define mmTPC4_CFG_FUNC_MBIST_MEM_4 0xF069E8
+
+#define mmTPC4_CFG_FUNC_MBIST_MEM_5 0xF069EC
+
+#define mmTPC4_CFG_FUNC_MBIST_MEM_6 0xF069F0
+
+#define mmTPC4_CFG_FUNC_MBIST_MEM_7 0xF069F4
+
+#define mmTPC4_CFG_FUNC_MBIST_MEM_8 0xF069F8
+
+#define mmTPC4_CFG_FUNC_MBIST_MEM_9 0xF069FC
+
+#define mmTPC4_CFG_QM_TENSOR_0_BASE_ADDR_LOW 0xF06A00
+
+#define mmTPC4_CFG_QM_TENSOR_0_BASE_ADDR_HIGH 0xF06A04
+
+#define mmTPC4_CFG_QM_TENSOR_0_PADDING_VALUE 0xF06A08
+
+#define mmTPC4_CFG_QM_TENSOR_0_TENSOR_CONFIG 0xF06A0C
+
+#define mmTPC4_CFG_QM_TENSOR_0_DIM_0_SIZE 0xF06A10
+
+#define mmTPC4_CFG_QM_TENSOR_0_DIM_0_STRIDE 0xF06A14
+
+#define mmTPC4_CFG_QM_TENSOR_0_DIM_1_SIZE 0xF06A18
+
+#define mmTPC4_CFG_QM_TENSOR_0_DIM_1_STRIDE 0xF06A1C
+
+#define mmTPC4_CFG_QM_TENSOR_0_DIM_2_SIZE 0xF06A20
+
+#define mmTPC4_CFG_QM_TENSOR_0_DIM_2_STRIDE 0xF06A24
+
+#define mmTPC4_CFG_QM_TENSOR_0_DIM_3_SIZE 0xF06A28
+
+#define mmTPC4_CFG_QM_TENSOR_0_DIM_3_STRIDE 0xF06A2C
+
+#define mmTPC4_CFG_QM_TENSOR_0_DIM_4_SIZE 0xF06A30
+
+#define mmTPC4_CFG_QM_TENSOR_0_DIM_4_STRIDE 0xF06A34
+
+#define mmTPC4_CFG_QM_TENSOR_1_BASE_ADDR_LOW 0xF06A38
+
+#define mmTPC4_CFG_QM_TENSOR_1_BASE_ADDR_HIGH 0xF06A3C
+
+#define mmTPC4_CFG_QM_TENSOR_1_PADDING_VALUE 0xF06A40
+
+#define mmTPC4_CFG_QM_TENSOR_1_TENSOR_CONFIG 0xF06A44
+
+#define mmTPC4_CFG_QM_TENSOR_1_DIM_0_SIZE 0xF06A48
+
+#define mmTPC4_CFG_QM_TENSOR_1_DIM_0_STRIDE 0xF06A4C
+
+#define mmTPC4_CFG_QM_TENSOR_1_DIM_1_SIZE 0xF06A50
+
+#define mmTPC4_CFG_QM_TENSOR_1_DIM_1_STRIDE 0xF06A54
+
+#define mmTPC4_CFG_QM_TENSOR_1_DIM_2_SIZE 0xF06A58
+
+#define mmTPC4_CFG_QM_TENSOR_1_DIM_2_STRIDE 0xF06A5C
+
+#define mmTPC4_CFG_QM_TENSOR_1_DIM_3_SIZE 0xF06A60
+
+#define mmTPC4_CFG_QM_TENSOR_1_DIM_3_STRIDE 0xF06A64
+
+#define mmTPC4_CFG_QM_TENSOR_1_DIM_4_SIZE 0xF06A68
+
+#define mmTPC4_CFG_QM_TENSOR_1_DIM_4_STRIDE 0xF06A6C
+
+#define mmTPC4_CFG_QM_TENSOR_2_BASE_ADDR_LOW 0xF06A70
+
+#define mmTPC4_CFG_QM_TENSOR_2_BASE_ADDR_HIGH 0xF06A74
+
+#define mmTPC4_CFG_QM_TENSOR_2_PADDING_VALUE 0xF06A78
+
+#define mmTPC4_CFG_QM_TENSOR_2_TENSOR_CONFIG 0xF06A7C
+
+#define mmTPC4_CFG_QM_TENSOR_2_DIM_0_SIZE 0xF06A80
+
+#define mmTPC4_CFG_QM_TENSOR_2_DIM_0_STRIDE 0xF06A84
+
+#define mmTPC4_CFG_QM_TENSOR_2_DIM_1_SIZE 0xF06A88
+
+#define mmTPC4_CFG_QM_TENSOR_2_DIM_1_STRIDE 0xF06A8C
+
+#define mmTPC4_CFG_QM_TENSOR_2_DIM_2_SIZE 0xF06A90
+
+#define mmTPC4_CFG_QM_TENSOR_2_DIM_2_STRIDE 0xF06A94
+
+#define mmTPC4_CFG_QM_TENSOR_2_DIM_3_SIZE 0xF06A98
+
+#define mmTPC4_CFG_QM_TENSOR_2_DIM_3_STRIDE 0xF06A9C
+
+#define mmTPC4_CFG_QM_TENSOR_2_DIM_4_SIZE 0xF06AA0
+
+#define mmTPC4_CFG_QM_TENSOR_2_DIM_4_STRIDE 0xF06AA4
+
+#define mmTPC4_CFG_QM_TENSOR_3_BASE_ADDR_LOW 0xF06AA8
+
+#define mmTPC4_CFG_QM_TENSOR_3_BASE_ADDR_HIGH 0xF06AAC
+
+#define mmTPC4_CFG_QM_TENSOR_3_PADDING_VALUE 0xF06AB0
+
+#define mmTPC4_CFG_QM_TENSOR_3_TENSOR_CONFIG 0xF06AB4
+
+#define mmTPC4_CFG_QM_TENSOR_3_DIM_0_SIZE 0xF06AB8
+
+#define mmTPC4_CFG_QM_TENSOR_3_DIM_0_STRIDE 0xF06ABC
+
+#define mmTPC4_CFG_QM_TENSOR_3_DIM_1_SIZE 0xF06AC0
+
+#define mmTPC4_CFG_QM_TENSOR_3_DIM_1_STRIDE 0xF06AC4
+
+#define mmTPC4_CFG_QM_TENSOR_3_DIM_2_SIZE 0xF06AC8
+
+#define mmTPC4_CFG_QM_TENSOR_3_DIM_2_STRIDE 0xF06ACC
+
+#define mmTPC4_CFG_QM_TENSOR_3_DIM_3_SIZE 0xF06AD0
+
+#define mmTPC4_CFG_QM_TENSOR_3_DIM_3_STRIDE 0xF06AD4
+
+#define mmTPC4_CFG_QM_TENSOR_3_DIM_4_SIZE 0xF06AD8
+
+#define mmTPC4_CFG_QM_TENSOR_3_DIM_4_STRIDE 0xF06ADC
+
+#define mmTPC4_CFG_QM_TENSOR_4_BASE_ADDR_LOW 0xF06AE0
+
+#define mmTPC4_CFG_QM_TENSOR_4_BASE_ADDR_HIGH 0xF06AE4
+
+#define mmTPC4_CFG_QM_TENSOR_4_PADDING_VALUE 0xF06AE8
+
+#define mmTPC4_CFG_QM_TENSOR_4_TENSOR_CONFIG 0xF06AEC
+
+#define mmTPC4_CFG_QM_TENSOR_4_DIM_0_SIZE 0xF06AF0
+
+#define mmTPC4_CFG_QM_TENSOR_4_DIM_0_STRIDE 0xF06AF4
+
+#define mmTPC4_CFG_QM_TENSOR_4_DIM_1_SIZE 0xF06AF8
+
+#define mmTPC4_CFG_QM_TENSOR_4_DIM_1_STRIDE 0xF06AFC
+
+#define mmTPC4_CFG_QM_TENSOR_4_DIM_2_SIZE 0xF06B00
+
+#define mmTPC4_CFG_QM_TENSOR_4_DIM_2_STRIDE 0xF06B04
+
+#define mmTPC4_CFG_QM_TENSOR_4_DIM_3_SIZE 0xF06B08
+
+#define mmTPC4_CFG_QM_TENSOR_4_DIM_3_STRIDE 0xF06B0C
+
+#define mmTPC4_CFG_QM_TENSOR_4_DIM_4_SIZE 0xF06B10
+
+#define mmTPC4_CFG_QM_TENSOR_4_DIM_4_STRIDE 0xF06B14
+
+#define mmTPC4_CFG_QM_TENSOR_5_BASE_ADDR_LOW 0xF06B18
+
+#define mmTPC4_CFG_QM_TENSOR_5_BASE_ADDR_HIGH 0xF06B1C
+
+#define mmTPC4_CFG_QM_TENSOR_5_PADDING_VALUE 0xF06B20
+
+#define mmTPC4_CFG_QM_TENSOR_5_TENSOR_CONFIG 0xF06B24
+
+#define mmTPC4_CFG_QM_TENSOR_5_DIM_0_SIZE 0xF06B28
+
+#define mmTPC4_CFG_QM_TENSOR_5_DIM_0_STRIDE 0xF06B2C
+
+#define mmTPC4_CFG_QM_TENSOR_5_DIM_1_SIZE 0xF06B30
+
+#define mmTPC4_CFG_QM_TENSOR_5_DIM_1_STRIDE 0xF06B34
+
+#define mmTPC4_CFG_QM_TENSOR_5_DIM_2_SIZE 0xF06B38
+
+#define mmTPC4_CFG_QM_TENSOR_5_DIM_2_STRIDE 0xF06B3C
+
+#define mmTPC4_CFG_QM_TENSOR_5_DIM_3_SIZE 0xF06B40
+
+#define mmTPC4_CFG_QM_TENSOR_5_DIM_3_STRIDE 0xF06B44
+
+#define mmTPC4_CFG_QM_TENSOR_5_DIM_4_SIZE 0xF06B48
+
+#define mmTPC4_CFG_QM_TENSOR_5_DIM_4_STRIDE 0xF06B4C
+
+#define mmTPC4_CFG_QM_TENSOR_6_BASE_ADDR_LOW 0xF06B50
+
+#define mmTPC4_CFG_QM_TENSOR_6_BASE_ADDR_HIGH 0xF06B54
+
+#define mmTPC4_CFG_QM_TENSOR_6_PADDING_VALUE 0xF06B58
+
+#define mmTPC4_CFG_QM_TENSOR_6_TENSOR_CONFIG 0xF06B5C
+
+#define mmTPC4_CFG_QM_TENSOR_6_DIM_0_SIZE 0xF06B60
+
+#define mmTPC4_CFG_QM_TENSOR_6_DIM_0_STRIDE 0xF06B64
+
+#define mmTPC4_CFG_QM_TENSOR_6_DIM_1_SIZE 0xF06B68
+
+#define mmTPC4_CFG_QM_TENSOR_6_DIM_1_STRIDE 0xF06B6C
+
+#define mmTPC4_CFG_QM_TENSOR_6_DIM_2_SIZE 0xF06B70
+
+#define mmTPC4_CFG_QM_TENSOR_6_DIM_2_STRIDE 0xF06B74
+
+#define mmTPC4_CFG_QM_TENSOR_6_DIM_3_SIZE 0xF06B78
+
+#define mmTPC4_CFG_QM_TENSOR_6_DIM_3_STRIDE 0xF06B7C
+
+#define mmTPC4_CFG_QM_TENSOR_6_DIM_4_SIZE 0xF06B80
+
+#define mmTPC4_CFG_QM_TENSOR_6_DIM_4_STRIDE 0xF06B84
+
+#define mmTPC4_CFG_QM_TENSOR_7_BASE_ADDR_LOW 0xF06B88
+
+#define mmTPC4_CFG_QM_TENSOR_7_BASE_ADDR_HIGH 0xF06B8C
+
+#define mmTPC4_CFG_QM_TENSOR_7_PADDING_VALUE 0xF06B90
+
+#define mmTPC4_CFG_QM_TENSOR_7_TENSOR_CONFIG 0xF06B94
+
+#define mmTPC4_CFG_QM_TENSOR_7_DIM_0_SIZE 0xF06B98
+
+#define mmTPC4_CFG_QM_TENSOR_7_DIM_0_STRIDE 0xF06B9C
+
+#define mmTPC4_CFG_QM_TENSOR_7_DIM_1_SIZE 0xF06BA0
+
+#define mmTPC4_CFG_QM_TENSOR_7_DIM_1_STRIDE 0xF06BA4
+
+#define mmTPC4_CFG_QM_TENSOR_7_DIM_2_SIZE 0xF06BA8
+
+#define mmTPC4_CFG_QM_TENSOR_7_DIM_2_STRIDE 0xF06BAC
+
+#define mmTPC4_CFG_QM_TENSOR_7_DIM_3_SIZE 0xF06BB0
+
+#define mmTPC4_CFG_QM_TENSOR_7_DIM_3_STRIDE 0xF06BB4
+
+#define mmTPC4_CFG_QM_TENSOR_7_DIM_4_SIZE 0xF06BB8
+
+#define mmTPC4_CFG_QM_TENSOR_7_DIM_4_STRIDE 0xF06BBC
+
+#define mmTPC4_CFG_QM_TENSOR_8_BASE_ADDR_LOW 0xF06BC0
+
+#define mmTPC4_CFG_QM_TENSOR_8_BASE_ADDR_HIGH 0xF06BC4
+
+#define mmTPC4_CFG_QM_TENSOR_8_PADDING_VALUE 0xF06BC8
+
+#define mmTPC4_CFG_QM_TENSOR_8_TENSOR_CONFIG 0xF06BCC
+
+#define mmTPC4_CFG_QM_TENSOR_8_DIM_0_SIZE 0xF06BD0
+
+#define mmTPC4_CFG_QM_TENSOR_8_DIM_0_STRIDE 0xF06BD4
+
+#define mmTPC4_CFG_QM_TENSOR_8_DIM_1_SIZE 0xF06BD8
+
+#define mmTPC4_CFG_QM_TENSOR_8_DIM_1_STRIDE 0xF06BDC
+
+#define mmTPC4_CFG_QM_TENSOR_8_DIM_2_SIZE 0xF06BE0
+
+#define mmTPC4_CFG_QM_TENSOR_8_DIM_2_STRIDE 0xF06BE4
+
+#define mmTPC4_CFG_QM_TENSOR_8_DIM_3_SIZE 0xF06BE8
+
+#define mmTPC4_CFG_QM_TENSOR_8_DIM_3_STRIDE 0xF06BEC
+
+#define mmTPC4_CFG_QM_TENSOR_8_DIM_4_SIZE 0xF06BF0
+
+#define mmTPC4_CFG_QM_TENSOR_8_DIM_4_STRIDE 0xF06BF4
+
+#define mmTPC4_CFG_QM_TENSOR_9_BASE_ADDR_LOW 0xF06BF8
+
+#define mmTPC4_CFG_QM_TENSOR_9_BASE_ADDR_HIGH 0xF06BFC
+
+#define mmTPC4_CFG_QM_TENSOR_9_PADDING_VALUE 0xF06C00
+
+#define mmTPC4_CFG_QM_TENSOR_9_TENSOR_CONFIG 0xF06C04
+
+#define mmTPC4_CFG_QM_TENSOR_9_DIM_0_SIZE 0xF06C08
+
+#define mmTPC4_CFG_QM_TENSOR_9_DIM_0_STRIDE 0xF06C0C
+
+#define mmTPC4_CFG_QM_TENSOR_9_DIM_1_SIZE 0xF06C10
+
+#define mmTPC4_CFG_QM_TENSOR_9_DIM_1_STRIDE 0xF06C14
+
+#define mmTPC4_CFG_QM_TENSOR_9_DIM_2_SIZE 0xF06C18
+
+#define mmTPC4_CFG_QM_TENSOR_9_DIM_2_STRIDE 0xF06C1C
+
+#define mmTPC4_CFG_QM_TENSOR_9_DIM_3_SIZE 0xF06C20
+
+#define mmTPC4_CFG_QM_TENSOR_9_DIM_3_STRIDE 0xF06C24
+
+#define mmTPC4_CFG_QM_TENSOR_9_DIM_4_SIZE 0xF06C28
+
+#define mmTPC4_CFG_QM_TENSOR_9_DIM_4_STRIDE 0xF06C2C
+
+#define mmTPC4_CFG_QM_TENSOR_10_BASE_ADDR_LOW 0xF06C30
+
+#define mmTPC4_CFG_QM_TENSOR_10_BASE_ADDR_HIGH 0xF06C34
+
+#define mmTPC4_CFG_QM_TENSOR_10_PADDING_VALUE 0xF06C38
+
+#define mmTPC4_CFG_QM_TENSOR_10_TENSOR_CONFIG 0xF06C3C
+
+#define mmTPC4_CFG_QM_TENSOR_10_DIM_0_SIZE 0xF06C40
+
+#define mmTPC4_CFG_QM_TENSOR_10_DIM_0_STRIDE 0xF06C44
+
+#define mmTPC4_CFG_QM_TENSOR_10_DIM_1_SIZE 0xF06C48
+
+#define mmTPC4_CFG_QM_TENSOR_10_DIM_1_STRIDE 0xF06C4C
+
+#define mmTPC4_CFG_QM_TENSOR_10_DIM_2_SIZE 0xF06C50
+
+#define mmTPC4_CFG_QM_TENSOR_10_DIM_2_STRIDE 0xF06C54
+
+#define mmTPC4_CFG_QM_TENSOR_10_DIM_3_SIZE 0xF06C58
+
+#define mmTPC4_CFG_QM_TENSOR_10_DIM_3_STRIDE 0xF06C5C
+
+#define mmTPC4_CFG_QM_TENSOR_10_DIM_4_SIZE 0xF06C60
+
+#define mmTPC4_CFG_QM_TENSOR_10_DIM_4_STRIDE 0xF06C64
+
+#define mmTPC4_CFG_QM_TENSOR_11_BASE_ADDR_LOW 0xF06C68
+
+#define mmTPC4_CFG_QM_TENSOR_11_BASE_ADDR_HIGH 0xF06C6C
+
+#define mmTPC4_CFG_QM_TENSOR_11_PADDING_VALUE 0xF06C70
+
+#define mmTPC4_CFG_QM_TENSOR_11_TENSOR_CONFIG 0xF06C74
+
+#define mmTPC4_CFG_QM_TENSOR_11_DIM_0_SIZE 0xF06C78
+
+#define mmTPC4_CFG_QM_TENSOR_11_DIM_0_STRIDE 0xF06C7C
+
+#define mmTPC4_CFG_QM_TENSOR_11_DIM_1_SIZE 0xF06C80
+
+#define mmTPC4_CFG_QM_TENSOR_11_DIM_1_STRIDE 0xF06C84
+
+#define mmTPC4_CFG_QM_TENSOR_11_DIM_2_SIZE 0xF06C88
+
+#define mmTPC4_CFG_QM_TENSOR_11_DIM_2_STRIDE 0xF06C8C
+
+#define mmTPC4_CFG_QM_TENSOR_11_DIM_3_SIZE 0xF06C90
+
+#define mmTPC4_CFG_QM_TENSOR_11_DIM_3_STRIDE 0xF06C94
+
+#define mmTPC4_CFG_QM_TENSOR_11_DIM_4_SIZE 0xF06C98
+
+#define mmTPC4_CFG_QM_TENSOR_11_DIM_4_STRIDE 0xF06C9C
+
+#define mmTPC4_CFG_QM_TENSOR_12_BASE_ADDR_LOW 0xF06CA0
+
+#define mmTPC4_CFG_QM_TENSOR_12_BASE_ADDR_HIGH 0xF06CA4
+
+#define mmTPC4_CFG_QM_TENSOR_12_PADDING_VALUE 0xF06CA8
+
+#define mmTPC4_CFG_QM_TENSOR_12_TENSOR_CONFIG 0xF06CAC
+
+#define mmTPC4_CFG_QM_TENSOR_12_DIM_0_SIZE 0xF06CB0
+
+#define mmTPC4_CFG_QM_TENSOR_12_DIM_0_STRIDE 0xF06CB4
+
+#define mmTPC4_CFG_QM_TENSOR_12_DIM_1_SIZE 0xF06CB8
+
+#define mmTPC4_CFG_QM_TENSOR_12_DIM_1_STRIDE 0xF06CBC
+
+#define mmTPC4_CFG_QM_TENSOR_12_DIM_2_SIZE 0xF06CC0
+
+#define mmTPC4_CFG_QM_TENSOR_12_DIM_2_STRIDE 0xF06CC4
+
+#define mmTPC4_CFG_QM_TENSOR_12_DIM_3_SIZE 0xF06CC8
+
+#define mmTPC4_CFG_QM_TENSOR_12_DIM_3_STRIDE 0xF06CCC
+
+#define mmTPC4_CFG_QM_TENSOR_12_DIM_4_SIZE 0xF06CD0
+
+#define mmTPC4_CFG_QM_TENSOR_12_DIM_4_STRIDE 0xF06CD4
+
+#define mmTPC4_CFG_QM_TENSOR_13_BASE_ADDR_LOW 0xF06CD8
+
+#define mmTPC4_CFG_QM_TENSOR_13_BASE_ADDR_HIGH 0xF06CDC
+
+#define mmTPC4_CFG_QM_TENSOR_13_PADDING_VALUE 0xF06CE0
+
+#define mmTPC4_CFG_QM_TENSOR_13_TENSOR_CONFIG 0xF06CE4
+
+#define mmTPC4_CFG_QM_TENSOR_13_DIM_0_SIZE 0xF06CE8
+
+#define mmTPC4_CFG_QM_TENSOR_13_DIM_0_STRIDE 0xF06CEC
+
+#define mmTPC4_CFG_QM_TENSOR_13_DIM_1_SIZE 0xF06CF0
+
+#define mmTPC4_CFG_QM_TENSOR_13_DIM_1_STRIDE 0xF06CF4
+
+#define mmTPC4_CFG_QM_TENSOR_13_DIM_2_SIZE 0xF06CF8
+
+#define mmTPC4_CFG_QM_TENSOR_13_DIM_2_STRIDE 0xF06CFC
+
+#define mmTPC4_CFG_QM_TENSOR_13_DIM_3_SIZE 0xF06D00
+
+#define mmTPC4_CFG_QM_TENSOR_13_DIM_3_STRIDE 0xF06D04
+
+#define mmTPC4_CFG_QM_TENSOR_13_DIM_4_SIZE 0xF06D08
+
+#define mmTPC4_CFG_QM_TENSOR_13_DIM_4_STRIDE 0xF06D0C
+
+#define mmTPC4_CFG_QM_TENSOR_14_BASE_ADDR_LOW 0xF06D10
+
+#define mmTPC4_CFG_QM_TENSOR_14_BASE_ADDR_HIGH 0xF06D14
+
+#define mmTPC4_CFG_QM_TENSOR_14_PADDING_VALUE 0xF06D18
+
+#define mmTPC4_CFG_QM_TENSOR_14_TENSOR_CONFIG 0xF06D1C
+
+#define mmTPC4_CFG_QM_TENSOR_14_DIM_0_SIZE 0xF06D20
+
+#define mmTPC4_CFG_QM_TENSOR_14_DIM_0_STRIDE 0xF06D24
+
+#define mmTPC4_CFG_QM_TENSOR_14_DIM_1_SIZE 0xF06D28
+
+#define mmTPC4_CFG_QM_TENSOR_14_DIM_1_STRIDE 0xF06D2C
+
+#define mmTPC4_CFG_QM_TENSOR_14_DIM_2_SIZE 0xF06D30
+
+#define mmTPC4_CFG_QM_TENSOR_14_DIM_2_STRIDE 0xF06D34
+
+#define mmTPC4_CFG_QM_TENSOR_14_DIM_3_SIZE 0xF06D38
+
+#define mmTPC4_CFG_QM_TENSOR_14_DIM_3_STRIDE 0xF06D3C
+
+#define mmTPC4_CFG_QM_TENSOR_14_DIM_4_SIZE 0xF06D40
+
+#define mmTPC4_CFG_QM_TENSOR_14_DIM_4_STRIDE 0xF06D44
+
+#define mmTPC4_CFG_QM_TENSOR_15_BASE_ADDR_LOW 0xF06D48
+
+#define mmTPC4_CFG_QM_TENSOR_15_BASE_ADDR_HIGH 0xF06D4C
+
+#define mmTPC4_CFG_QM_TENSOR_15_PADDING_VALUE 0xF06D50
+
+#define mmTPC4_CFG_QM_TENSOR_15_TENSOR_CONFIG 0xF06D54
+
+#define mmTPC4_CFG_QM_TENSOR_15_DIM_0_SIZE 0xF06D58
+
+#define mmTPC4_CFG_QM_TENSOR_15_DIM_0_STRIDE 0xF06D5C
+
+#define mmTPC4_CFG_QM_TENSOR_15_DIM_1_SIZE 0xF06D60
+
+#define mmTPC4_CFG_QM_TENSOR_15_DIM_1_STRIDE 0xF06D64
+
+#define mmTPC4_CFG_QM_TENSOR_15_DIM_2_SIZE 0xF06D68
+
+#define mmTPC4_CFG_QM_TENSOR_15_DIM_2_STRIDE 0xF06D6C
+
+#define mmTPC4_CFG_QM_TENSOR_15_DIM_3_SIZE 0xF06D70
+
+#define mmTPC4_CFG_QM_TENSOR_15_DIM_3_STRIDE 0xF06D74
+
+#define mmTPC4_CFG_QM_TENSOR_15_DIM_4_SIZE 0xF06D78
+
+#define mmTPC4_CFG_QM_TENSOR_15_DIM_4_STRIDE 0xF06D7C
+
+#define mmTPC4_CFG_QM_SYNC_OBJECT_MESSAGE 0xF06D80
+
+#define mmTPC4_CFG_QM_SYNC_OBJECT_ADDR 0xF06D84
+
+#define mmTPC4_CFG_QM_KERNEL_BASE_ADDRESS_LOW 0xF06D88
+
+#define mmTPC4_CFG_QM_KERNEL_BASE_ADDRESS_HIGH 0xF06D8C
+
+#define mmTPC4_CFG_QM_TID_BASE_DIM_0 0xF06D90
+
+#define mmTPC4_CFG_QM_TID_SIZE_DIM_0 0xF06D94
+
+#define mmTPC4_CFG_QM_TID_BASE_DIM_1 0xF06D98
+
+#define mmTPC4_CFG_QM_TID_SIZE_DIM_1 0xF06D9C
+
+#define mmTPC4_CFG_QM_TID_BASE_DIM_2 0xF06DA0
+
+#define mmTPC4_CFG_QM_TID_SIZE_DIM_2 0xF06DA4
+
+#define mmTPC4_CFG_QM_TID_BASE_DIM_3 0xF06DA8
+
+#define mmTPC4_CFG_QM_TID_SIZE_DIM_3 0xF06DAC
+
+#define mmTPC4_CFG_QM_TID_BASE_DIM_4 0xF06DB0
+
+#define mmTPC4_CFG_QM_TID_SIZE_DIM_4 0xF06DB4
+
+#define mmTPC4_CFG_QM_KERNEL_CONFIG 0xF06DB8
+
+#define mmTPC4_CFG_QM_KERNEL_ID 0xF06DBC
+
+#define mmTPC4_CFG_QM_SRF_0 0xF06DC0
+
+#define mmTPC4_CFG_QM_SRF_1 0xF06DC4
+
+#define mmTPC4_CFG_QM_SRF_2 0xF06DC8
+
+#define mmTPC4_CFG_QM_SRF_3 0xF06DCC
+
+#define mmTPC4_CFG_QM_SRF_4 0xF06DD0
+
+#define mmTPC4_CFG_QM_SRF_5 0xF06DD4
+
+#define mmTPC4_CFG_QM_SRF_6 0xF06DD8
+
+#define mmTPC4_CFG_QM_SRF_7 0xF06DDC
+
+#define mmTPC4_CFG_QM_SRF_8 0xF06DE0
+
+#define mmTPC4_CFG_QM_SRF_9 0xF06DE4
+
+#define mmTPC4_CFG_QM_SRF_10 0xF06DE8
+
+#define mmTPC4_CFG_QM_SRF_11 0xF06DEC
+
+#define mmTPC4_CFG_QM_SRF_12 0xF06DF0
+
+#define mmTPC4_CFG_QM_SRF_13 0xF06DF4
+
+#define mmTPC4_CFG_QM_SRF_14 0xF06DF8
+
+#define mmTPC4_CFG_QM_SRF_15 0xF06DFC
+
+#define mmTPC4_CFG_QM_SRF_16 0xF06E00
+
+#define mmTPC4_CFG_QM_SRF_17 0xF06E04
+
+#define mmTPC4_CFG_QM_SRF_18 0xF06E08
+
+#define mmTPC4_CFG_QM_SRF_19 0xF06E0C
+
+#define mmTPC4_CFG_QM_SRF_20 0xF06E10
+
+#define mmTPC4_CFG_QM_SRF_21 0xF06E14
+
+#define mmTPC4_CFG_QM_SRF_22 0xF06E18
+
+#define mmTPC4_CFG_QM_SRF_23 0xF06E1C
+
+#define mmTPC4_CFG_QM_SRF_24 0xF06E20
+
+#define mmTPC4_CFG_QM_SRF_25 0xF06E24
+
+#define mmTPC4_CFG_QM_SRF_26 0xF06E28
+
+#define mmTPC4_CFG_QM_SRF_27 0xF06E2C
+
+#define mmTPC4_CFG_QM_SRF_28 0xF06E30
+
+#define mmTPC4_CFG_QM_SRF_29 0xF06E34
+
+#define mmTPC4_CFG_QM_SRF_30 0xF06E38
+
+#define mmTPC4_CFG_QM_SRF_31 0xF06E3C
+
+#endif /* ASIC_REG_TPC4_CFG_REGS_H_ */
diff --git a/drivers/accel/habanalabs/include/gaudi/asic_reg/tpc4_qm_regs.h b/drivers/accel/habanalabs/include/gaudi/asic_reg/tpc4_qm_regs.h
new file mode 100644
index 0000000000..80e63402f6
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi/asic_reg/tpc4_qm_regs.h
@@ -0,0 +1,834 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2016-2018 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ ** DO NOT EDIT BELOW **
+ ************************************/
+
+#ifndef ASIC_REG_TPC4_QM_REGS_H_
+#define ASIC_REG_TPC4_QM_REGS_H_
+
+/*
+ *****************************************
+ * TPC4_QM (Prototype: QMAN)
+ *****************************************
+ */
+
+#define mmTPC4_QM_GLBL_CFG0 0xF08000
+
+#define mmTPC4_QM_GLBL_CFG1 0xF08004
+
+#define mmTPC4_QM_GLBL_PROT 0xF08008
+
+#define mmTPC4_QM_GLBL_ERR_CFG 0xF0800C
+
+#define mmTPC4_QM_GLBL_SECURE_PROPS_0 0xF08010
+
+#define mmTPC4_QM_GLBL_SECURE_PROPS_1 0xF08014
+
+#define mmTPC4_QM_GLBL_SECURE_PROPS_2 0xF08018
+
+#define mmTPC4_QM_GLBL_SECURE_PROPS_3 0xF0801C
+
+#define mmTPC4_QM_GLBL_SECURE_PROPS_4 0xF08020
+
+#define mmTPC4_QM_GLBL_NON_SECURE_PROPS_0 0xF08024
+
+#define mmTPC4_QM_GLBL_NON_SECURE_PROPS_1 0xF08028
+
+#define mmTPC4_QM_GLBL_NON_SECURE_PROPS_2 0xF0802C
+
+#define mmTPC4_QM_GLBL_NON_SECURE_PROPS_3 0xF08030
+
+#define mmTPC4_QM_GLBL_NON_SECURE_PROPS_4 0xF08034
+
+#define mmTPC4_QM_GLBL_STS0 0xF08038
+
+#define mmTPC4_QM_GLBL_STS1_0 0xF08040
+
+#define mmTPC4_QM_GLBL_STS1_1 0xF08044
+
+#define mmTPC4_QM_GLBL_STS1_2 0xF08048
+
+#define mmTPC4_QM_GLBL_STS1_3 0xF0804C
+
+#define mmTPC4_QM_GLBL_STS1_4 0xF08050
+
+#define mmTPC4_QM_GLBL_MSG_EN_0 0xF08054
+
+#define mmTPC4_QM_GLBL_MSG_EN_1 0xF08058
+
+#define mmTPC4_QM_GLBL_MSG_EN_2 0xF0805C
+
+#define mmTPC4_QM_GLBL_MSG_EN_3 0xF08060
+
+#define mmTPC4_QM_GLBL_MSG_EN_4 0xF08068
+
+#define mmTPC4_QM_PQ_BASE_LO_0 0xF08070
+
+#define mmTPC4_QM_PQ_BASE_LO_1 0xF08074
+
+#define mmTPC4_QM_PQ_BASE_LO_2 0xF08078
+
+#define mmTPC4_QM_PQ_BASE_LO_3 0xF0807C
+
+#define mmTPC4_QM_PQ_BASE_HI_0 0xF08080
+
+#define mmTPC4_QM_PQ_BASE_HI_1 0xF08084
+
+#define mmTPC4_QM_PQ_BASE_HI_2 0xF08088
+
+#define mmTPC4_QM_PQ_BASE_HI_3 0xF0808C
+
+#define mmTPC4_QM_PQ_SIZE_0 0xF08090
+
+#define mmTPC4_QM_PQ_SIZE_1 0xF08094
+
+#define mmTPC4_QM_PQ_SIZE_2 0xF08098
+
+#define mmTPC4_QM_PQ_SIZE_3 0xF0809C
+
+#define mmTPC4_QM_PQ_PI_0 0xF080A0
+
+#define mmTPC4_QM_PQ_PI_1 0xF080A4
+
+#define mmTPC4_QM_PQ_PI_2 0xF080A8
+
+#define mmTPC4_QM_PQ_PI_3 0xF080AC
+
+#define mmTPC4_QM_PQ_CI_0 0xF080B0
+
+#define mmTPC4_QM_PQ_CI_1 0xF080B4
+
+#define mmTPC4_QM_PQ_CI_2 0xF080B8
+
+#define mmTPC4_QM_PQ_CI_3 0xF080BC
+
+#define mmTPC4_QM_PQ_CFG0_0 0xF080C0
+
+#define mmTPC4_QM_PQ_CFG0_1 0xF080C4
+
+#define mmTPC4_QM_PQ_CFG0_2 0xF080C8
+
+#define mmTPC4_QM_PQ_CFG0_3 0xF080CC
+
+#define mmTPC4_QM_PQ_CFG1_0 0xF080D0
+
+#define mmTPC4_QM_PQ_CFG1_1 0xF080D4
+
+#define mmTPC4_QM_PQ_CFG1_2 0xF080D8
+
+#define mmTPC4_QM_PQ_CFG1_3 0xF080DC
+
+#define mmTPC4_QM_PQ_ARUSER_31_11_0 0xF080E0
+
+#define mmTPC4_QM_PQ_ARUSER_31_11_1 0xF080E4
+
+#define mmTPC4_QM_PQ_ARUSER_31_11_2 0xF080E8
+
+#define mmTPC4_QM_PQ_ARUSER_31_11_3 0xF080EC
+
+#define mmTPC4_QM_PQ_STS0_0 0xF080F0
+
+#define mmTPC4_QM_PQ_STS0_1 0xF080F4
+
+#define mmTPC4_QM_PQ_STS0_2 0xF080F8
+
+#define mmTPC4_QM_PQ_STS0_3 0xF080FC
+
+#define mmTPC4_QM_PQ_STS1_0 0xF08100
+
+#define mmTPC4_QM_PQ_STS1_1 0xF08104
+
+#define mmTPC4_QM_PQ_STS1_2 0xF08108
+
+#define mmTPC4_QM_PQ_STS1_3 0xF0810C
+
+#define mmTPC4_QM_CQ_CFG0_0 0xF08110
+
+#define mmTPC4_QM_CQ_CFG0_1 0xF08114
+
+#define mmTPC4_QM_CQ_CFG0_2 0xF08118
+
+#define mmTPC4_QM_CQ_CFG0_3 0xF0811C
+
+#define mmTPC4_QM_CQ_CFG0_4 0xF08120
+
+#define mmTPC4_QM_CQ_CFG1_0 0xF08124
+
+#define mmTPC4_QM_CQ_CFG1_1 0xF08128
+
+#define mmTPC4_QM_CQ_CFG1_2 0xF0812C
+
+#define mmTPC4_QM_CQ_CFG1_3 0xF08130
+
+#define mmTPC4_QM_CQ_CFG1_4 0xF08134
+
+#define mmTPC4_QM_CQ_ARUSER_31_11_0 0xF08138
+
+#define mmTPC4_QM_CQ_ARUSER_31_11_1 0xF0813C
+
+#define mmTPC4_QM_CQ_ARUSER_31_11_2 0xF08140
+
+#define mmTPC4_QM_CQ_ARUSER_31_11_3 0xF08144
+
+#define mmTPC4_QM_CQ_ARUSER_31_11_4 0xF08148
+
+#define mmTPC4_QM_CQ_STS0_0 0xF0814C
+
+#define mmTPC4_QM_CQ_STS0_1 0xF08150
+
+#define mmTPC4_QM_CQ_STS0_2 0xF08154
+
+#define mmTPC4_QM_CQ_STS0_3 0xF08158
+
+#define mmTPC4_QM_CQ_STS0_4 0xF0815C
+
+#define mmTPC4_QM_CQ_STS1_0 0xF08160
+
+#define mmTPC4_QM_CQ_STS1_1 0xF08164
+
+#define mmTPC4_QM_CQ_STS1_2 0xF08168
+
+#define mmTPC4_QM_CQ_STS1_3 0xF0816C
+
+#define mmTPC4_QM_CQ_STS1_4 0xF08170
+
+#define mmTPC4_QM_CQ_PTR_LO_0 0xF08174
+
+#define mmTPC4_QM_CQ_PTR_HI_0 0xF08178
+
+#define mmTPC4_QM_CQ_TSIZE_0 0xF0817C
+
+#define mmTPC4_QM_CQ_CTL_0 0xF08180
+
+#define mmTPC4_QM_CQ_PTR_LO_1 0xF08184
+
+#define mmTPC4_QM_CQ_PTR_HI_1 0xF08188
+
+#define mmTPC4_QM_CQ_TSIZE_1 0xF0818C
+
+#define mmTPC4_QM_CQ_CTL_1 0xF08190
+
+#define mmTPC4_QM_CQ_PTR_LO_2 0xF08194
+
+#define mmTPC4_QM_CQ_PTR_HI_2 0xF08198
+
+#define mmTPC4_QM_CQ_TSIZE_2 0xF0819C
+
+#define mmTPC4_QM_CQ_CTL_2 0xF081A0
+
+#define mmTPC4_QM_CQ_PTR_LO_3 0xF081A4
+
+#define mmTPC4_QM_CQ_PTR_HI_3 0xF081A8
+
+#define mmTPC4_QM_CQ_TSIZE_3 0xF081AC
+
+#define mmTPC4_QM_CQ_CTL_3 0xF081B0
+
+#define mmTPC4_QM_CQ_PTR_LO_4 0xF081B4
+
+#define mmTPC4_QM_CQ_PTR_HI_4 0xF081B8
+
+#define mmTPC4_QM_CQ_TSIZE_4 0xF081BC
+
+#define mmTPC4_QM_CQ_CTL_4 0xF081C0
+
+#define mmTPC4_QM_CQ_PTR_LO_STS_0 0xF081C4
+
+#define mmTPC4_QM_CQ_PTR_LO_STS_1 0xF081C8
+
+#define mmTPC4_QM_CQ_PTR_LO_STS_2 0xF081CC
+
+#define mmTPC4_QM_CQ_PTR_LO_STS_3 0xF081D0
+
+#define mmTPC4_QM_CQ_PTR_LO_STS_4 0xF081D4
+
+#define mmTPC4_QM_CQ_PTR_HI_STS_0 0xF081D8
+
+#define mmTPC4_QM_CQ_PTR_HI_STS_1 0xF081DC
+
+#define mmTPC4_QM_CQ_PTR_HI_STS_2 0xF081E0
+
+#define mmTPC4_QM_CQ_PTR_HI_STS_3 0xF081E4
+
+#define mmTPC4_QM_CQ_PTR_HI_STS_4 0xF081E8
+
+#define mmTPC4_QM_CQ_TSIZE_STS_0 0xF081EC
+
+#define mmTPC4_QM_CQ_TSIZE_STS_1 0xF081F0
+
+#define mmTPC4_QM_CQ_TSIZE_STS_2 0xF081F4
+
+#define mmTPC4_QM_CQ_TSIZE_STS_3 0xF081F8
+
+#define mmTPC4_QM_CQ_TSIZE_STS_4 0xF081FC
+
+#define mmTPC4_QM_CQ_CTL_STS_0 0xF08200
+
+#define mmTPC4_QM_CQ_CTL_STS_1 0xF08204
+
+#define mmTPC4_QM_CQ_CTL_STS_2 0xF08208
+
+#define mmTPC4_QM_CQ_CTL_STS_3 0xF0820C
+
+#define mmTPC4_QM_CQ_CTL_STS_4 0xF08210
+
+#define mmTPC4_QM_CQ_IFIFO_CNT_0 0xF08214
+
+#define mmTPC4_QM_CQ_IFIFO_CNT_1 0xF08218
+
+#define mmTPC4_QM_CQ_IFIFO_CNT_2 0xF0821C
+
+#define mmTPC4_QM_CQ_IFIFO_CNT_3 0xF08220
+
+#define mmTPC4_QM_CQ_IFIFO_CNT_4 0xF08224
+
+#define mmTPC4_QM_CP_MSG_BASE0_ADDR_LO_0 0xF08228
+
+#define mmTPC4_QM_CP_MSG_BASE0_ADDR_LO_1 0xF0822C
+
+#define mmTPC4_QM_CP_MSG_BASE0_ADDR_LO_2 0xF08230
+
+#define mmTPC4_QM_CP_MSG_BASE0_ADDR_LO_3 0xF08234
+
+#define mmTPC4_QM_CP_MSG_BASE0_ADDR_LO_4 0xF08238
+
+#define mmTPC4_QM_CP_MSG_BASE0_ADDR_HI_0 0xF0823C
+
+#define mmTPC4_QM_CP_MSG_BASE0_ADDR_HI_1 0xF08240
+
+#define mmTPC4_QM_CP_MSG_BASE0_ADDR_HI_2 0xF08244
+
+#define mmTPC4_QM_CP_MSG_BASE0_ADDR_HI_3 0xF08248
+
+#define mmTPC4_QM_CP_MSG_BASE0_ADDR_HI_4 0xF0824C
+
+#define mmTPC4_QM_CP_MSG_BASE1_ADDR_LO_0 0xF08250
+
+#define mmTPC4_QM_CP_MSG_BASE1_ADDR_LO_1 0xF08254
+
+#define mmTPC4_QM_CP_MSG_BASE1_ADDR_LO_2 0xF08258
+
+#define mmTPC4_QM_CP_MSG_BASE1_ADDR_LO_3 0xF0825C
+
+#define mmTPC4_QM_CP_MSG_BASE1_ADDR_LO_4 0xF08260
+
+#define mmTPC4_QM_CP_MSG_BASE1_ADDR_HI_0 0xF08264
+
+#define mmTPC4_QM_CP_MSG_BASE1_ADDR_HI_1 0xF08268
+
+#define mmTPC4_QM_CP_MSG_BASE1_ADDR_HI_2 0xF0826C
+
+#define mmTPC4_QM_CP_MSG_BASE1_ADDR_HI_3 0xF08270
+
+#define mmTPC4_QM_CP_MSG_BASE1_ADDR_HI_4 0xF08274
+
+#define mmTPC4_QM_CP_MSG_BASE2_ADDR_LO_0 0xF08278
+
+#define mmTPC4_QM_CP_MSG_BASE2_ADDR_LO_1 0xF0827C
+
+#define mmTPC4_QM_CP_MSG_BASE2_ADDR_LO_2 0xF08280
+
+#define mmTPC4_QM_CP_MSG_BASE2_ADDR_LO_3 0xF08284
+
+#define mmTPC4_QM_CP_MSG_BASE2_ADDR_LO_4 0xF08288
+
+#define mmTPC4_QM_CP_MSG_BASE2_ADDR_HI_0 0xF0828C
+
+#define mmTPC4_QM_CP_MSG_BASE2_ADDR_HI_1 0xF08290
+
+#define mmTPC4_QM_CP_MSG_BASE2_ADDR_HI_2 0xF08294
+
+#define mmTPC4_QM_CP_MSG_BASE2_ADDR_HI_3 0xF08298
+
+#define mmTPC4_QM_CP_MSG_BASE2_ADDR_HI_4 0xF0829C
+
+#define mmTPC4_QM_CP_MSG_BASE3_ADDR_LO_0 0xF082A0
+
+#define mmTPC4_QM_CP_MSG_BASE3_ADDR_LO_1 0xF082A4
+
+#define mmTPC4_QM_CP_MSG_BASE3_ADDR_LO_2 0xF082A8
+
+#define mmTPC4_QM_CP_MSG_BASE3_ADDR_LO_3 0xF082AC
+
+#define mmTPC4_QM_CP_MSG_BASE3_ADDR_LO_4 0xF082B0
+
+#define mmTPC4_QM_CP_MSG_BASE3_ADDR_HI_0 0xF082B4
+
+#define mmTPC4_QM_CP_MSG_BASE3_ADDR_HI_1 0xF082B8
+
+#define mmTPC4_QM_CP_MSG_BASE3_ADDR_HI_2 0xF082BC
+
+#define mmTPC4_QM_CP_MSG_BASE3_ADDR_HI_3 0xF082C0
+
+#define mmTPC4_QM_CP_MSG_BASE3_ADDR_HI_4 0xF082C4
+
+#define mmTPC4_QM_CP_LDMA_TSIZE_OFFSET_0 0xF082C8
+
+#define mmTPC4_QM_CP_LDMA_TSIZE_OFFSET_1 0xF082CC
+
+#define mmTPC4_QM_CP_LDMA_TSIZE_OFFSET_2 0xF082D0
+
+#define mmTPC4_QM_CP_LDMA_TSIZE_OFFSET_3 0xF082D4
+
+#define mmTPC4_QM_CP_LDMA_TSIZE_OFFSET_4 0xF082D8
+
+#define mmTPC4_QM_CP_LDMA_SRC_BASE_LO_OFFSET_0 0xF082E0
+
+#define mmTPC4_QM_CP_LDMA_SRC_BASE_LO_OFFSET_1 0xF082E4
+
+#define mmTPC4_QM_CP_LDMA_SRC_BASE_LO_OFFSET_2 0xF082E8
+
+#define mmTPC4_QM_CP_LDMA_SRC_BASE_LO_OFFSET_3 0xF082EC
+
+#define mmTPC4_QM_CP_LDMA_SRC_BASE_LO_OFFSET_4 0xF082F0
+
+#define mmTPC4_QM_CP_LDMA_DST_BASE_LO_OFFSET_0 0xF082F4
+
+#define mmTPC4_QM_CP_LDMA_DST_BASE_LO_OFFSET_1 0xF082F8
+
+#define mmTPC4_QM_CP_LDMA_DST_BASE_LO_OFFSET_2 0xF082FC
+
+#define mmTPC4_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 0xF08300
+
+#define mmTPC4_QM_CP_LDMA_DST_BASE_LO_OFFSET_4 0xF08304
+
+#define mmTPC4_QM_CP_FENCE0_RDATA_0 0xF08308
+
+#define mmTPC4_QM_CP_FENCE0_RDATA_1 0xF0830C
+
+#define mmTPC4_QM_CP_FENCE0_RDATA_2 0xF08310
+
+#define mmTPC4_QM_CP_FENCE0_RDATA_3 0xF08314
+
+#define mmTPC4_QM_CP_FENCE0_RDATA_4 0xF08318
+
+#define mmTPC4_QM_CP_FENCE1_RDATA_0 0xF0831C
+
+#define mmTPC4_QM_CP_FENCE1_RDATA_1 0xF08320
+
+#define mmTPC4_QM_CP_FENCE1_RDATA_2 0xF08324
+
+#define mmTPC4_QM_CP_FENCE1_RDATA_3 0xF08328
+
+#define mmTPC4_QM_CP_FENCE1_RDATA_4 0xF0832C
+
+#define mmTPC4_QM_CP_FENCE2_RDATA_0 0xF08330
+
+#define mmTPC4_QM_CP_FENCE2_RDATA_1 0xF08334
+
+#define mmTPC4_QM_CP_FENCE2_RDATA_2 0xF08338
+
+#define mmTPC4_QM_CP_FENCE2_RDATA_3 0xF0833C
+
+#define mmTPC4_QM_CP_FENCE2_RDATA_4 0xF08340
+
+#define mmTPC4_QM_CP_FENCE3_RDATA_0 0xF08344
+
+#define mmTPC4_QM_CP_FENCE3_RDATA_1 0xF08348
+
+#define mmTPC4_QM_CP_FENCE3_RDATA_2 0xF0834C
+
+#define mmTPC4_QM_CP_FENCE3_RDATA_3 0xF08350
+
+#define mmTPC4_QM_CP_FENCE3_RDATA_4 0xF08354
+
+#define mmTPC4_QM_CP_FENCE0_CNT_0 0xF08358
+
+#define mmTPC4_QM_CP_FENCE0_CNT_1 0xF0835C
+
+#define mmTPC4_QM_CP_FENCE0_CNT_2 0xF08360
+
+#define mmTPC4_QM_CP_FENCE0_CNT_3 0xF08364
+
+#define mmTPC4_QM_CP_FENCE0_CNT_4 0xF08368
+
+#define mmTPC4_QM_CP_FENCE1_CNT_0 0xF0836C
+
+#define mmTPC4_QM_CP_FENCE1_CNT_1 0xF08370
+
+#define mmTPC4_QM_CP_FENCE1_CNT_2 0xF08374
+
+#define mmTPC4_QM_CP_FENCE1_CNT_3 0xF08378
+
+#define mmTPC4_QM_CP_FENCE1_CNT_4 0xF0837C
+
+#define mmTPC4_QM_CP_FENCE2_CNT_0 0xF08380
+
+#define mmTPC4_QM_CP_FENCE2_CNT_1 0xF08384
+
+#define mmTPC4_QM_CP_FENCE2_CNT_2 0xF08388
+
+#define mmTPC4_QM_CP_FENCE2_CNT_3 0xF0838C
+
+#define mmTPC4_QM_CP_FENCE2_CNT_4 0xF08390
+
+#define mmTPC4_QM_CP_FENCE3_CNT_0 0xF08394
+
+#define mmTPC4_QM_CP_FENCE3_CNT_1 0xF08398
+
+#define mmTPC4_QM_CP_FENCE3_CNT_2 0xF0839C
+
+#define mmTPC4_QM_CP_FENCE3_CNT_3 0xF083A0
+
+#define mmTPC4_QM_CP_FENCE3_CNT_4 0xF083A4
+
+#define mmTPC4_QM_CP_STS_0 0xF083A8
+
+#define mmTPC4_QM_CP_STS_1 0xF083AC
+
+#define mmTPC4_QM_CP_STS_2 0xF083B0
+
+#define mmTPC4_QM_CP_STS_3 0xF083B4
+
+#define mmTPC4_QM_CP_STS_4 0xF083B8
+
+#define mmTPC4_QM_CP_CURRENT_INST_LO_0 0xF083BC
+
+#define mmTPC4_QM_CP_CURRENT_INST_LO_1 0xF083C0
+
+#define mmTPC4_QM_CP_CURRENT_INST_LO_2 0xF083C4
+
+#define mmTPC4_QM_CP_CURRENT_INST_LO_3 0xF083C8
+
+#define mmTPC4_QM_CP_CURRENT_INST_LO_4 0xF083CC
+
+#define mmTPC4_QM_CP_CURRENT_INST_HI_0 0xF083D0
+
+#define mmTPC4_QM_CP_CURRENT_INST_HI_1 0xF083D4
+
+#define mmTPC4_QM_CP_CURRENT_INST_HI_2 0xF083D8
+
+#define mmTPC4_QM_CP_CURRENT_INST_HI_3 0xF083DC
+
+#define mmTPC4_QM_CP_CURRENT_INST_HI_4 0xF083E0
+
+#define mmTPC4_QM_CP_BARRIER_CFG_0 0xF083F4
+
+#define mmTPC4_QM_CP_BARRIER_CFG_1 0xF083F8
+
+#define mmTPC4_QM_CP_BARRIER_CFG_2 0xF083FC
+
+#define mmTPC4_QM_CP_BARRIER_CFG_3 0xF08400
+
+#define mmTPC4_QM_CP_BARRIER_CFG_4 0xF08404
+
+#define mmTPC4_QM_CP_DBG_0_0 0xF08408
+
+#define mmTPC4_QM_CP_DBG_0_1 0xF0840C
+
+#define mmTPC4_QM_CP_DBG_0_2 0xF08410
+
+#define mmTPC4_QM_CP_DBG_0_3 0xF08414
+
+#define mmTPC4_QM_CP_DBG_0_4 0xF08418
+
+#define mmTPC4_QM_CP_ARUSER_31_11_0 0xF0841C
+
+#define mmTPC4_QM_CP_ARUSER_31_11_1 0xF08420
+
+#define mmTPC4_QM_CP_ARUSER_31_11_2 0xF08424
+
+#define mmTPC4_QM_CP_ARUSER_31_11_3 0xF08428
+
+#define mmTPC4_QM_CP_ARUSER_31_11_4 0xF0842C
+
+#define mmTPC4_QM_CP_AWUSER_31_11_0 0xF08430
+
+#define mmTPC4_QM_CP_AWUSER_31_11_1 0xF08434
+
+#define mmTPC4_QM_CP_AWUSER_31_11_2 0xF08438
+
+#define mmTPC4_QM_CP_AWUSER_31_11_3 0xF0843C
+
+#define mmTPC4_QM_CP_AWUSER_31_11_4 0xF08440
+
+#define mmTPC4_QM_ARB_CFG_0 0xF08A00
+
+#define mmTPC4_QM_ARB_CHOISE_Q_PUSH 0xF08A04
+
+#define mmTPC4_QM_ARB_WRR_WEIGHT_0 0xF08A08
+
+#define mmTPC4_QM_ARB_WRR_WEIGHT_1 0xF08A0C
+
+#define mmTPC4_QM_ARB_WRR_WEIGHT_2 0xF08A10
+
+#define mmTPC4_QM_ARB_WRR_WEIGHT_3 0xF08A14
+
+#define mmTPC4_QM_ARB_CFG_1 0xF08A18
+
+#define mmTPC4_QM_ARB_MST_AVAIL_CRED_0 0xF08A20
+
+#define mmTPC4_QM_ARB_MST_AVAIL_CRED_1 0xF08A24
+
+#define mmTPC4_QM_ARB_MST_AVAIL_CRED_2 0xF08A28
+
+#define mmTPC4_QM_ARB_MST_AVAIL_CRED_3 0xF08A2C
+
+#define mmTPC4_QM_ARB_MST_AVAIL_CRED_4 0xF08A30
+
+#define mmTPC4_QM_ARB_MST_AVAIL_CRED_5 0xF08A34
+
+#define mmTPC4_QM_ARB_MST_AVAIL_CRED_6 0xF08A38
+
+#define mmTPC4_QM_ARB_MST_AVAIL_CRED_7 0xF08A3C
+
+#define mmTPC4_QM_ARB_MST_AVAIL_CRED_8 0xF08A40
+
+#define mmTPC4_QM_ARB_MST_AVAIL_CRED_9 0xF08A44
+
+#define mmTPC4_QM_ARB_MST_AVAIL_CRED_10 0xF08A48
+
+#define mmTPC4_QM_ARB_MST_AVAIL_CRED_11 0xF08A4C
+
+#define mmTPC4_QM_ARB_MST_AVAIL_CRED_12 0xF08A50
+
+#define mmTPC4_QM_ARB_MST_AVAIL_CRED_13 0xF08A54
+
+#define mmTPC4_QM_ARB_MST_AVAIL_CRED_14 0xF08A58
+
+#define mmTPC4_QM_ARB_MST_AVAIL_CRED_15 0xF08A5C
+
+#define mmTPC4_QM_ARB_MST_AVAIL_CRED_16 0xF08A60
+
+#define mmTPC4_QM_ARB_MST_AVAIL_CRED_17 0xF08A64
+
+#define mmTPC4_QM_ARB_MST_AVAIL_CRED_18 0xF08A68
+
+#define mmTPC4_QM_ARB_MST_AVAIL_CRED_19 0xF08A6C
+
+#define mmTPC4_QM_ARB_MST_AVAIL_CRED_20 0xF08A70
+
+#define mmTPC4_QM_ARB_MST_AVAIL_CRED_21 0xF08A74
+
+#define mmTPC4_QM_ARB_MST_AVAIL_CRED_22 0xF08A78
+
+#define mmTPC4_QM_ARB_MST_AVAIL_CRED_23 0xF08A7C
+
+#define mmTPC4_QM_ARB_MST_AVAIL_CRED_24 0xF08A80
+
+#define mmTPC4_QM_ARB_MST_AVAIL_CRED_25 0xF08A84
+
+#define mmTPC4_QM_ARB_MST_AVAIL_CRED_26 0xF08A88
+
+#define mmTPC4_QM_ARB_MST_AVAIL_CRED_27 0xF08A8C
+
+#define mmTPC4_QM_ARB_MST_AVAIL_CRED_28 0xF08A90
+
+#define mmTPC4_QM_ARB_MST_AVAIL_CRED_29 0xF08A94
+
+#define mmTPC4_QM_ARB_MST_AVAIL_CRED_30 0xF08A98
+
+#define mmTPC4_QM_ARB_MST_AVAIL_CRED_31 0xF08A9C
+
+#define mmTPC4_QM_ARB_MST_CRED_INC 0xF08AA0
+
+#define mmTPC4_QM_ARB_MST_CHOISE_PUSH_OFST_0 0xF08AA4
+
+#define mmTPC4_QM_ARB_MST_CHOISE_PUSH_OFST_1 0xF08AA8
+
+#define mmTPC4_QM_ARB_MST_CHOISE_PUSH_OFST_2 0xF08AAC
+
+#define mmTPC4_QM_ARB_MST_CHOISE_PUSH_OFST_3 0xF08AB0
+
+#define mmTPC4_QM_ARB_MST_CHOISE_PUSH_OFST_4 0xF08AB4
+
+#define mmTPC4_QM_ARB_MST_CHOISE_PUSH_OFST_5 0xF08AB8
+
+#define mmTPC4_QM_ARB_MST_CHOISE_PUSH_OFST_6 0xF08ABC
+
+#define mmTPC4_QM_ARB_MST_CHOISE_PUSH_OFST_7 0xF08AC0
+
+#define mmTPC4_QM_ARB_MST_CHOISE_PUSH_OFST_8 0xF08AC4
+
+#define mmTPC4_QM_ARB_MST_CHOISE_PUSH_OFST_9 0xF08AC8
+
+#define mmTPC4_QM_ARB_MST_CHOISE_PUSH_OFST_10 0xF08ACC
+
+#define mmTPC4_QM_ARB_MST_CHOISE_PUSH_OFST_11 0xF08AD0
+
+#define mmTPC4_QM_ARB_MST_CHOISE_PUSH_OFST_12 0xF08AD4
+
+#define mmTPC4_QM_ARB_MST_CHOISE_PUSH_OFST_13 0xF08AD8
+
+#define mmTPC4_QM_ARB_MST_CHOISE_PUSH_OFST_14 0xF08ADC
+
+#define mmTPC4_QM_ARB_MST_CHOISE_PUSH_OFST_15 0xF08AE0
+
+#define mmTPC4_QM_ARB_MST_CHOISE_PUSH_OFST_16 0xF08AE4
+
+#define mmTPC4_QM_ARB_MST_CHOISE_PUSH_OFST_17 0xF08AE8
+
+#define mmTPC4_QM_ARB_MST_CHOISE_PUSH_OFST_18 0xF08AEC
+
+#define mmTPC4_QM_ARB_MST_CHOISE_PUSH_OFST_19 0xF08AF0
+
+#define mmTPC4_QM_ARB_MST_CHOISE_PUSH_OFST_20 0xF08AF4
+
+#define mmTPC4_QM_ARB_MST_CHOISE_PUSH_OFST_21 0xF08AF8
+
+#define mmTPC4_QM_ARB_MST_CHOISE_PUSH_OFST_22 0xF08AFC
+
+#define mmTPC4_QM_ARB_MST_CHOISE_PUSH_OFST_23 0xF08B00
+
+#define mmTPC4_QM_ARB_MST_CHOISE_PUSH_OFST_24 0xF08B04
+
+#define mmTPC4_QM_ARB_MST_CHOISE_PUSH_OFST_25 0xF08B08
+
+#define mmTPC4_QM_ARB_MST_CHOISE_PUSH_OFST_26 0xF08B0C
+
+#define mmTPC4_QM_ARB_MST_CHOISE_PUSH_OFST_27 0xF08B10
+
+#define mmTPC4_QM_ARB_MST_CHOISE_PUSH_OFST_28 0xF08B14
+
+#define mmTPC4_QM_ARB_MST_CHOISE_PUSH_OFST_29 0xF08B18
+
+#define mmTPC4_QM_ARB_MST_CHOISE_PUSH_OFST_30 0xF08B1C
+
+#define mmTPC4_QM_ARB_MST_CHOISE_PUSH_OFST_31 0xF08B20
+
+#define mmTPC4_QM_ARB_SLV_MASTER_INC_CRED_OFST 0xF08B28
+
+#define mmTPC4_QM_ARB_MST_SLAVE_EN 0xF08B2C
+
+#define mmTPC4_QM_ARB_MST_QUIET_PER 0xF08B34
+
+#define mmTPC4_QM_ARB_SLV_CHOISE_WDT 0xF08B38
+
+#define mmTPC4_QM_ARB_SLV_ID 0xF08B3C
+
+#define mmTPC4_QM_ARB_MSG_MAX_INFLIGHT 0xF08B44
+
+#define mmTPC4_QM_ARB_MSG_AWUSER_31_11 0xF08B48
+
+#define mmTPC4_QM_ARB_MSG_AWUSER_SEC_PROP 0xF08B4C
+
+#define mmTPC4_QM_ARB_MSG_AWUSER_NON_SEC_PROP 0xF08B50
+
+#define mmTPC4_QM_ARB_BASE_LO 0xF08B54
+
+#define mmTPC4_QM_ARB_BASE_HI 0xF08B58
+
+#define mmTPC4_QM_ARB_STATE_STS 0xF08B80
+
+#define mmTPC4_QM_ARB_CHOISE_FULLNESS_STS 0xF08B84
+
+#define mmTPC4_QM_ARB_MSG_STS 0xF08B88
+
+#define mmTPC4_QM_ARB_SLV_CHOISE_Q_HEAD 0xF08B8C
+
+#define mmTPC4_QM_ARB_ERR_CAUSE 0xF08B9C
+
+#define mmTPC4_QM_ARB_ERR_MSG_EN 0xF08BA0
+
+#define mmTPC4_QM_ARB_ERR_STS_DRP 0xF08BA8
+
+#define mmTPC4_QM_ARB_MST_CRED_STS_0 0xF08BB0
+
+#define mmTPC4_QM_ARB_MST_CRED_STS_1 0xF08BB4
+
+#define mmTPC4_QM_ARB_MST_CRED_STS_2 0xF08BB8
+
+#define mmTPC4_QM_ARB_MST_CRED_STS_3 0xF08BBC
+
+#define mmTPC4_QM_ARB_MST_CRED_STS_4 0xF08BC0
+
+#define mmTPC4_QM_ARB_MST_CRED_STS_5 0xF08BC4
+
+#define mmTPC4_QM_ARB_MST_CRED_STS_6 0xF08BC8
+
+#define mmTPC4_QM_ARB_MST_CRED_STS_7 0xF08BCC
+
+#define mmTPC4_QM_ARB_MST_CRED_STS_8 0xF08BD0
+
+#define mmTPC4_QM_ARB_MST_CRED_STS_9 0xF08BD4
+
+#define mmTPC4_QM_ARB_MST_CRED_STS_10 0xF08BD8
+
+#define mmTPC4_QM_ARB_MST_CRED_STS_11 0xF08BDC
+
+#define mmTPC4_QM_ARB_MST_CRED_STS_12 0xF08BE0
+
+#define mmTPC4_QM_ARB_MST_CRED_STS_13 0xF08BE4
+
+#define mmTPC4_QM_ARB_MST_CRED_STS_14 0xF08BE8
+
+#define mmTPC4_QM_ARB_MST_CRED_STS_15 0xF08BEC
+
+#define mmTPC4_QM_ARB_MST_CRED_STS_16 0xF08BF0
+
+#define mmTPC4_QM_ARB_MST_CRED_STS_17 0xF08BF4
+
+#define mmTPC4_QM_ARB_MST_CRED_STS_18 0xF08BF8
+
+#define mmTPC4_QM_ARB_MST_CRED_STS_19 0xF08BFC
+
+#define mmTPC4_QM_ARB_MST_CRED_STS_20 0xF08C00
+
+#define mmTPC4_QM_ARB_MST_CRED_STS_21 0xF08C04
+
+#define mmTPC4_QM_ARB_MST_CRED_STS_22 0xF08C08
+
+#define mmTPC4_QM_ARB_MST_CRED_STS_23 0xF08C0C
+
+#define mmTPC4_QM_ARB_MST_CRED_STS_24 0xF08C10
+
+#define mmTPC4_QM_ARB_MST_CRED_STS_25 0xF08C14
+
+#define mmTPC4_QM_ARB_MST_CRED_STS_26 0xF08C18
+
+#define mmTPC4_QM_ARB_MST_CRED_STS_27 0xF08C1C
+
+#define mmTPC4_QM_ARB_MST_CRED_STS_28 0xF08C20
+
+#define mmTPC4_QM_ARB_MST_CRED_STS_29 0xF08C24
+
+#define mmTPC4_QM_ARB_MST_CRED_STS_30 0xF08C28
+
+#define mmTPC4_QM_ARB_MST_CRED_STS_31 0xF08C2C
+
+#define mmTPC4_QM_CGM_CFG 0xF08C70
+
+#define mmTPC4_QM_CGM_STS 0xF08C74
+
+#define mmTPC4_QM_CGM_CFG1 0xF08C78
+
+#define mmTPC4_QM_LOCAL_RANGE_BASE 0xF08C80
+
+#define mmTPC4_QM_LOCAL_RANGE_SIZE 0xF08C84
+
+#define mmTPC4_QM_CSMR_STRICT_PRIO_CFG 0xF08C90
+
+#define mmTPC4_QM_HBW_RD_RATE_LIM_CFG_1 0xF08C94
+
+#define mmTPC4_QM_LBW_WR_RATE_LIM_CFG_0 0xF08C98
+
+#define mmTPC4_QM_LBW_WR_RATE_LIM_CFG_1 0xF08C9C
+
+#define mmTPC4_QM_HBW_RD_RATE_LIM_CFG_0 0xF08CA0
+
+#define mmTPC4_QM_GLBL_AXCACHE 0xF08CA4
+
+#define mmTPC4_QM_IND_GW_APB_CFG 0xF08CB0
+
+#define mmTPC4_QM_IND_GW_APB_WDATA 0xF08CB4
+
+#define mmTPC4_QM_IND_GW_APB_RDATA 0xF08CB8
+
+#define mmTPC4_QM_IND_GW_APB_STATUS 0xF08CBC
+
+#define mmTPC4_QM_GLBL_ERR_ADDR_LO 0xF08CD0
+
+#define mmTPC4_QM_GLBL_ERR_ADDR_HI 0xF08CD4
+
+#define mmTPC4_QM_GLBL_ERR_WDATA 0xF08CD8
+
+#define mmTPC4_QM_GLBL_MEM_INIT_BUSY 0xF08D00
+
+#endif /* ASIC_REG_TPC4_QM_REGS_H_ */
diff --git a/drivers/accel/habanalabs/include/gaudi/asic_reg/tpc5_cfg_regs.h b/drivers/accel/habanalabs/include/gaudi/asic_reg/tpc5_cfg_regs.h
new file mode 100644
index 0000000000..f428f89193
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi/asic_reg/tpc5_cfg_regs.h
@@ -0,0 +1,1226 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2016-2018 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ ** DO NOT EDIT BELOW **
+ ************************************/
+
+#ifndef ASIC_REG_TPC5_CFG_REGS_H_
+#define ASIC_REG_TPC5_CFG_REGS_H_
+
+/*
+ *****************************************
+ * TPC5_CFG (Prototype: TPC)
+ *****************************************
+ */
+
+#define mmTPC5_CFG_KERNEL_TENSOR_0_BASE_ADDR_LOW 0xF46400
+
+#define mmTPC5_CFG_KERNEL_TENSOR_0_BASE_ADDR_HIGH 0xF46404
+
+#define mmTPC5_CFG_KERNEL_TENSOR_0_PADDING_VALUE 0xF46408
+
+#define mmTPC5_CFG_KERNEL_TENSOR_0_TENSOR_CONFIG 0xF4640C
+
+#define mmTPC5_CFG_KERNEL_TENSOR_0_DIM_0_SIZE 0xF46410
+
+#define mmTPC5_CFG_KERNEL_TENSOR_0_DIM_0_STRIDE 0xF46414
+
+#define mmTPC5_CFG_KERNEL_TENSOR_0_DIM_1_SIZE 0xF46418
+
+#define mmTPC5_CFG_KERNEL_TENSOR_0_DIM_1_STRIDE 0xF4641C
+
+#define mmTPC5_CFG_KERNEL_TENSOR_0_DIM_2_SIZE 0xF46420
+
+#define mmTPC5_CFG_KERNEL_TENSOR_0_DIM_2_STRIDE 0xF46424
+
+#define mmTPC5_CFG_KERNEL_TENSOR_0_DIM_3_SIZE 0xF46428
+
+#define mmTPC5_CFG_KERNEL_TENSOR_0_DIM_3_STRIDE 0xF4642C
+
+#define mmTPC5_CFG_KERNEL_TENSOR_0_DIM_4_SIZE 0xF46430
+
+#define mmTPC5_CFG_KERNEL_TENSOR_0_DIM_4_STRIDE 0xF46434
+
+#define mmTPC5_CFG_KERNEL_TENSOR_1_BASE_ADDR_LOW 0xF46438
+
+#define mmTPC5_CFG_KERNEL_TENSOR_1_BASE_ADDR_HIGH 0xF4643C
+
+#define mmTPC5_CFG_KERNEL_TENSOR_1_PADDING_VALUE 0xF46440
+
+#define mmTPC5_CFG_KERNEL_TENSOR_1_TENSOR_CONFIG 0xF46444
+
+#define mmTPC5_CFG_KERNEL_TENSOR_1_DIM_0_SIZE 0xF46448
+
+#define mmTPC5_CFG_KERNEL_TENSOR_1_DIM_0_STRIDE 0xF4644C
+
+#define mmTPC5_CFG_KERNEL_TENSOR_1_DIM_1_SIZE 0xF46450
+
+#define mmTPC5_CFG_KERNEL_TENSOR_1_DIM_1_STRIDE 0xF46454
+
+#define mmTPC5_CFG_KERNEL_TENSOR_1_DIM_2_SIZE 0xF46458
+
+#define mmTPC5_CFG_KERNEL_TENSOR_1_DIM_2_STRIDE 0xF4645C
+
+#define mmTPC5_CFG_KERNEL_TENSOR_1_DIM_3_SIZE 0xF46460
+
+#define mmTPC5_CFG_KERNEL_TENSOR_1_DIM_3_STRIDE 0xF46464
+
+#define mmTPC5_CFG_KERNEL_TENSOR_1_DIM_4_SIZE 0xF46468
+
+#define mmTPC5_CFG_KERNEL_TENSOR_1_DIM_4_STRIDE 0xF4646C
+
+#define mmTPC5_CFG_KERNEL_TENSOR_2_BASE_ADDR_LOW 0xF46470
+
+#define mmTPC5_CFG_KERNEL_TENSOR_2_BASE_ADDR_HIGH 0xF46474
+
+#define mmTPC5_CFG_KERNEL_TENSOR_2_PADDING_VALUE 0xF46478
+
+#define mmTPC5_CFG_KERNEL_TENSOR_2_TENSOR_CONFIG 0xF4647C
+
+#define mmTPC5_CFG_KERNEL_TENSOR_2_DIM_0_SIZE 0xF46480
+
+#define mmTPC5_CFG_KERNEL_TENSOR_2_DIM_0_STRIDE 0xF46484
+
+#define mmTPC5_CFG_KERNEL_TENSOR_2_DIM_1_SIZE 0xF46488
+
+#define mmTPC5_CFG_KERNEL_TENSOR_2_DIM_1_STRIDE 0xF4648C
+
+#define mmTPC5_CFG_KERNEL_TENSOR_2_DIM_2_SIZE 0xF46490
+
+#define mmTPC5_CFG_KERNEL_TENSOR_2_DIM_2_STRIDE 0xF46494
+
+#define mmTPC5_CFG_KERNEL_TENSOR_2_DIM_3_SIZE 0xF46498
+
+#define mmTPC5_CFG_KERNEL_TENSOR_2_DIM_3_STRIDE 0xF4649C
+
+#define mmTPC5_CFG_KERNEL_TENSOR_2_DIM_4_SIZE 0xF464A0
+
+#define mmTPC5_CFG_KERNEL_TENSOR_2_DIM_4_STRIDE 0xF464A4
+
+#define mmTPC5_CFG_KERNEL_TENSOR_3_BASE_ADDR_LOW 0xF464A8
+
+#define mmTPC5_CFG_KERNEL_TENSOR_3_BASE_ADDR_HIGH 0xF464AC
+
+#define mmTPC5_CFG_KERNEL_TENSOR_3_PADDING_VALUE 0xF464B0
+
+#define mmTPC5_CFG_KERNEL_TENSOR_3_TENSOR_CONFIG 0xF464B4
+
+#define mmTPC5_CFG_KERNEL_TENSOR_3_DIM_0_SIZE 0xF464B8
+
+#define mmTPC5_CFG_KERNEL_TENSOR_3_DIM_0_STRIDE 0xF464BC
+
+#define mmTPC5_CFG_KERNEL_TENSOR_3_DIM_1_SIZE 0xF464C0
+
+#define mmTPC5_CFG_KERNEL_TENSOR_3_DIM_1_STRIDE 0xF464C4
+
+#define mmTPC5_CFG_KERNEL_TENSOR_3_DIM_2_SIZE 0xF464C8
+
+#define mmTPC5_CFG_KERNEL_TENSOR_3_DIM_2_STRIDE 0xF464CC
+
+#define mmTPC5_CFG_KERNEL_TENSOR_3_DIM_3_SIZE 0xF464D0
+
+#define mmTPC5_CFG_KERNEL_TENSOR_3_DIM_3_STRIDE 0xF464D4
+
+#define mmTPC5_CFG_KERNEL_TENSOR_3_DIM_4_SIZE 0xF464D8
+
+#define mmTPC5_CFG_KERNEL_TENSOR_3_DIM_4_STRIDE 0xF464DC
+
+#define mmTPC5_CFG_KERNEL_TENSOR_4_BASE_ADDR_LOW 0xF464E0
+
+#define mmTPC5_CFG_KERNEL_TENSOR_4_BASE_ADDR_HIGH 0xF464E4
+
+#define mmTPC5_CFG_KERNEL_TENSOR_4_PADDING_VALUE 0xF464E8
+
+#define mmTPC5_CFG_KERNEL_TENSOR_4_TENSOR_CONFIG 0xF464EC
+
+#define mmTPC5_CFG_KERNEL_TENSOR_4_DIM_0_SIZE 0xF464F0
+
+#define mmTPC5_CFG_KERNEL_TENSOR_4_DIM_0_STRIDE 0xF464F4
+
+#define mmTPC5_CFG_KERNEL_TENSOR_4_DIM_1_SIZE 0xF464F8
+
+#define mmTPC5_CFG_KERNEL_TENSOR_4_DIM_1_STRIDE 0xF464FC
+
+#define mmTPC5_CFG_KERNEL_TENSOR_4_DIM_2_SIZE 0xF46500
+
+#define mmTPC5_CFG_KERNEL_TENSOR_4_DIM_2_STRIDE 0xF46504
+
+#define mmTPC5_CFG_KERNEL_TENSOR_4_DIM_3_SIZE 0xF46508
+
+#define mmTPC5_CFG_KERNEL_TENSOR_4_DIM_3_STRIDE 0xF4650C
+
+#define mmTPC5_CFG_KERNEL_TENSOR_4_DIM_4_SIZE 0xF46510
+
+#define mmTPC5_CFG_KERNEL_TENSOR_4_DIM_4_STRIDE 0xF46514
+
+#define mmTPC5_CFG_KERNEL_TENSOR_5_BASE_ADDR_LOW 0xF46518
+
+#define mmTPC5_CFG_KERNEL_TENSOR_5_BASE_ADDR_HIGH 0xF4651C
+
+#define mmTPC5_CFG_KERNEL_TENSOR_5_PADDING_VALUE 0xF46520
+
+#define mmTPC5_CFG_KERNEL_TENSOR_5_TENSOR_CONFIG 0xF46524
+
+#define mmTPC5_CFG_KERNEL_TENSOR_5_DIM_0_SIZE 0xF46528
+
+#define mmTPC5_CFG_KERNEL_TENSOR_5_DIM_0_STRIDE 0xF4652C
+
+#define mmTPC5_CFG_KERNEL_TENSOR_5_DIM_1_SIZE 0xF46530
+
+#define mmTPC5_CFG_KERNEL_TENSOR_5_DIM_1_STRIDE 0xF46534
+
+#define mmTPC5_CFG_KERNEL_TENSOR_5_DIM_2_SIZE 0xF46538
+
+#define mmTPC5_CFG_KERNEL_TENSOR_5_DIM_2_STRIDE 0xF4653C
+
+#define mmTPC5_CFG_KERNEL_TENSOR_5_DIM_3_SIZE 0xF46540
+
+#define mmTPC5_CFG_KERNEL_TENSOR_5_DIM_3_STRIDE 0xF46544
+
+#define mmTPC5_CFG_KERNEL_TENSOR_5_DIM_4_SIZE 0xF46548
+
+#define mmTPC5_CFG_KERNEL_TENSOR_5_DIM_4_STRIDE 0xF4654C
+
+#define mmTPC5_CFG_KERNEL_TENSOR_6_BASE_ADDR_LOW 0xF46550
+
+#define mmTPC5_CFG_KERNEL_TENSOR_6_BASE_ADDR_HIGH 0xF46554
+
+#define mmTPC5_CFG_KERNEL_TENSOR_6_PADDING_VALUE 0xF46558
+
+#define mmTPC5_CFG_KERNEL_TENSOR_6_TENSOR_CONFIG 0xF4655C
+
+#define mmTPC5_CFG_KERNEL_TENSOR_6_DIM_0_SIZE 0xF46560
+
+#define mmTPC5_CFG_KERNEL_TENSOR_6_DIM_0_STRIDE 0xF46564
+
+#define mmTPC5_CFG_KERNEL_TENSOR_6_DIM_1_SIZE 0xF46568
+
+#define mmTPC5_CFG_KERNEL_TENSOR_6_DIM_1_STRIDE 0xF4656C
+
+#define mmTPC5_CFG_KERNEL_TENSOR_6_DIM_2_SIZE 0xF46570
+
+#define mmTPC5_CFG_KERNEL_TENSOR_6_DIM_2_STRIDE 0xF46574
+
+#define mmTPC5_CFG_KERNEL_TENSOR_6_DIM_3_SIZE 0xF46578
+
+#define mmTPC5_CFG_KERNEL_TENSOR_6_DIM_3_STRIDE 0xF4657C
+
+#define mmTPC5_CFG_KERNEL_TENSOR_6_DIM_4_SIZE 0xF46580
+
+#define mmTPC5_CFG_KERNEL_TENSOR_6_DIM_4_STRIDE 0xF46584
+
+#define mmTPC5_CFG_KERNEL_TENSOR_7_BASE_ADDR_LOW 0xF46588
+
+#define mmTPC5_CFG_KERNEL_TENSOR_7_BASE_ADDR_HIGH 0xF4658C
+
+#define mmTPC5_CFG_KERNEL_TENSOR_7_PADDING_VALUE 0xF46590
+
+#define mmTPC5_CFG_KERNEL_TENSOR_7_TENSOR_CONFIG 0xF46594
+
+#define mmTPC5_CFG_KERNEL_TENSOR_7_DIM_0_SIZE 0xF46598
+
+#define mmTPC5_CFG_KERNEL_TENSOR_7_DIM_0_STRIDE 0xF4659C
+
+#define mmTPC5_CFG_KERNEL_TENSOR_7_DIM_1_SIZE 0xF465A0
+
+#define mmTPC5_CFG_KERNEL_TENSOR_7_DIM_1_STRIDE 0xF465A4
+
+#define mmTPC5_CFG_KERNEL_TENSOR_7_DIM_2_SIZE 0xF465A8
+
+#define mmTPC5_CFG_KERNEL_TENSOR_7_DIM_2_STRIDE 0xF465AC
+
+#define mmTPC5_CFG_KERNEL_TENSOR_7_DIM_3_SIZE 0xF465B0
+
+#define mmTPC5_CFG_KERNEL_TENSOR_7_DIM_3_STRIDE 0xF465B4
+
+#define mmTPC5_CFG_KERNEL_TENSOR_7_DIM_4_SIZE 0xF465B8
+
+#define mmTPC5_CFG_KERNEL_TENSOR_7_DIM_4_STRIDE 0xF465BC
+
+#define mmTPC5_CFG_KERNEL_TENSOR_8_BASE_ADDR_LOW 0xF465C0
+
+#define mmTPC5_CFG_KERNEL_TENSOR_8_BASE_ADDR_HIGH 0xF465C4
+
+#define mmTPC5_CFG_KERNEL_TENSOR_8_PADDING_VALUE 0xF465C8
+
+#define mmTPC5_CFG_KERNEL_TENSOR_8_TENSOR_CONFIG 0xF465CC
+
+#define mmTPC5_CFG_KERNEL_TENSOR_8_DIM_0_SIZE 0xF465D0
+
+#define mmTPC5_CFG_KERNEL_TENSOR_8_DIM_0_STRIDE 0xF465D4
+
+#define mmTPC5_CFG_KERNEL_TENSOR_8_DIM_1_SIZE 0xF465D8
+
+#define mmTPC5_CFG_KERNEL_TENSOR_8_DIM_1_STRIDE 0xF465DC
+
+#define mmTPC5_CFG_KERNEL_TENSOR_8_DIM_2_SIZE 0xF465E0
+
+#define mmTPC5_CFG_KERNEL_TENSOR_8_DIM_2_STRIDE 0xF465E4
+
+#define mmTPC5_CFG_KERNEL_TENSOR_8_DIM_3_SIZE 0xF465E8
+
+#define mmTPC5_CFG_KERNEL_TENSOR_8_DIM_3_STRIDE 0xF465EC
+
+#define mmTPC5_CFG_KERNEL_TENSOR_8_DIM_4_SIZE 0xF465F0
+
+#define mmTPC5_CFG_KERNEL_TENSOR_8_DIM_4_STRIDE 0xF465F4
+
+#define mmTPC5_CFG_KERNEL_TENSOR_9_BASE_ADDR_LOW 0xF465F8
+
+#define mmTPC5_CFG_KERNEL_TENSOR_9_BASE_ADDR_HIGH 0xF465FC
+
+#define mmTPC5_CFG_KERNEL_TENSOR_9_PADDING_VALUE 0xF46600
+
+#define mmTPC5_CFG_KERNEL_TENSOR_9_TENSOR_CONFIG 0xF46604
+
+#define mmTPC5_CFG_KERNEL_TENSOR_9_DIM_0_SIZE 0xF46608
+
+#define mmTPC5_CFG_KERNEL_TENSOR_9_DIM_0_STRIDE 0xF4660C
+
+#define mmTPC5_CFG_KERNEL_TENSOR_9_DIM_1_SIZE 0xF46610
+
+#define mmTPC5_CFG_KERNEL_TENSOR_9_DIM_1_STRIDE 0xF46614
+
+#define mmTPC5_CFG_KERNEL_TENSOR_9_DIM_2_SIZE 0xF46618
+
+#define mmTPC5_CFG_KERNEL_TENSOR_9_DIM_2_STRIDE 0xF4661C
+
+#define mmTPC5_CFG_KERNEL_TENSOR_9_DIM_3_SIZE 0xF46620
+
+#define mmTPC5_CFG_KERNEL_TENSOR_9_DIM_3_STRIDE 0xF46624
+
+#define mmTPC5_CFG_KERNEL_TENSOR_9_DIM_4_SIZE 0xF46628
+
+#define mmTPC5_CFG_KERNEL_TENSOR_9_DIM_4_STRIDE 0xF4662C
+
+#define mmTPC5_CFG_KERNEL_TENSOR_10_BASE_ADDR_LOW 0xF46630
+
+#define mmTPC5_CFG_KERNEL_TENSOR_10_BASE_ADDR_HIGH 0xF46634
+
+#define mmTPC5_CFG_KERNEL_TENSOR_10_PADDING_VALUE 0xF46638
+
+#define mmTPC5_CFG_KERNEL_TENSOR_10_TENSOR_CONFIG 0xF4663C
+
+#define mmTPC5_CFG_KERNEL_TENSOR_10_DIM_0_SIZE 0xF46640
+
+#define mmTPC5_CFG_KERNEL_TENSOR_10_DIM_0_STRIDE 0xF46644
+
+#define mmTPC5_CFG_KERNEL_TENSOR_10_DIM_1_SIZE 0xF46648
+
+#define mmTPC5_CFG_KERNEL_TENSOR_10_DIM_1_STRIDE 0xF4664C
+
+#define mmTPC5_CFG_KERNEL_TENSOR_10_DIM_2_SIZE 0xF46650
+
+#define mmTPC5_CFG_KERNEL_TENSOR_10_DIM_2_STRIDE 0xF46654
+
+#define mmTPC5_CFG_KERNEL_TENSOR_10_DIM_3_SIZE 0xF46658
+
+#define mmTPC5_CFG_KERNEL_TENSOR_10_DIM_3_STRIDE 0xF4665C
+
+#define mmTPC5_CFG_KERNEL_TENSOR_10_DIM_4_SIZE 0xF46660
+
+#define mmTPC5_CFG_KERNEL_TENSOR_10_DIM_4_STRIDE 0xF46664
+
+#define mmTPC5_CFG_KERNEL_TENSOR_11_BASE_ADDR_LOW 0xF46668
+
+#define mmTPC5_CFG_KERNEL_TENSOR_11_BASE_ADDR_HIGH 0xF4666C
+
+#define mmTPC5_CFG_KERNEL_TENSOR_11_PADDING_VALUE 0xF46670
+
+#define mmTPC5_CFG_KERNEL_TENSOR_11_TENSOR_CONFIG 0xF46674
+
+#define mmTPC5_CFG_KERNEL_TENSOR_11_DIM_0_SIZE 0xF46678
+
+#define mmTPC5_CFG_KERNEL_TENSOR_11_DIM_0_STRIDE 0xF4667C
+
+#define mmTPC5_CFG_KERNEL_TENSOR_11_DIM_1_SIZE 0xF46680
+
+#define mmTPC5_CFG_KERNEL_TENSOR_11_DIM_1_STRIDE 0xF46684
+
+#define mmTPC5_CFG_KERNEL_TENSOR_11_DIM_2_SIZE 0xF46688
+
+#define mmTPC5_CFG_KERNEL_TENSOR_11_DIM_2_STRIDE 0xF4668C
+
+#define mmTPC5_CFG_KERNEL_TENSOR_11_DIM_3_SIZE 0xF46690
+
+#define mmTPC5_CFG_KERNEL_TENSOR_11_DIM_3_STRIDE 0xF46694
+
+#define mmTPC5_CFG_KERNEL_TENSOR_11_DIM_4_SIZE 0xF46698
+
+#define mmTPC5_CFG_KERNEL_TENSOR_11_DIM_4_STRIDE 0xF4669C
+
+#define mmTPC5_CFG_KERNEL_TENSOR_12_BASE_ADDR_LOW 0xF466A0
+
+#define mmTPC5_CFG_KERNEL_TENSOR_12_BASE_ADDR_HIGH 0xF466A4
+
+#define mmTPC5_CFG_KERNEL_TENSOR_12_PADDING_VALUE 0xF466A8
+
+#define mmTPC5_CFG_KERNEL_TENSOR_12_TENSOR_CONFIG 0xF466AC
+
+#define mmTPC5_CFG_KERNEL_TENSOR_12_DIM_0_SIZE 0xF466B0
+
+#define mmTPC5_CFG_KERNEL_TENSOR_12_DIM_0_STRIDE 0xF466B4
+
+#define mmTPC5_CFG_KERNEL_TENSOR_12_DIM_1_SIZE 0xF466B8
+
+#define mmTPC5_CFG_KERNEL_TENSOR_12_DIM_1_STRIDE 0xF466BC
+
+#define mmTPC5_CFG_KERNEL_TENSOR_12_DIM_2_SIZE 0xF466C0
+
+#define mmTPC5_CFG_KERNEL_TENSOR_12_DIM_2_STRIDE 0xF466C4
+
+#define mmTPC5_CFG_KERNEL_TENSOR_12_DIM_3_SIZE 0xF466C8
+
+#define mmTPC5_CFG_KERNEL_TENSOR_12_DIM_3_STRIDE 0xF466CC
+
+#define mmTPC5_CFG_KERNEL_TENSOR_12_DIM_4_SIZE 0xF466D0
+
+#define mmTPC5_CFG_KERNEL_TENSOR_12_DIM_4_STRIDE 0xF466D4
+
+#define mmTPC5_CFG_KERNEL_TENSOR_13_BASE_ADDR_LOW 0xF466D8
+
+#define mmTPC5_CFG_KERNEL_TENSOR_13_BASE_ADDR_HIGH 0xF466DC
+
+#define mmTPC5_CFG_KERNEL_TENSOR_13_PADDING_VALUE 0xF466E0
+
+#define mmTPC5_CFG_KERNEL_TENSOR_13_TENSOR_CONFIG 0xF466E4
+
+#define mmTPC5_CFG_KERNEL_TENSOR_13_DIM_0_SIZE 0xF466E8
+
+#define mmTPC5_CFG_KERNEL_TENSOR_13_DIM_0_STRIDE 0xF466EC
+
+#define mmTPC5_CFG_KERNEL_TENSOR_13_DIM_1_SIZE 0xF466F0
+
+#define mmTPC5_CFG_KERNEL_TENSOR_13_DIM_1_STRIDE 0xF466F4
+
+#define mmTPC5_CFG_KERNEL_TENSOR_13_DIM_2_SIZE 0xF466F8
+
+#define mmTPC5_CFG_KERNEL_TENSOR_13_DIM_2_STRIDE 0xF466FC
+
+#define mmTPC5_CFG_KERNEL_TENSOR_13_DIM_3_SIZE 0xF46700
+
+#define mmTPC5_CFG_KERNEL_TENSOR_13_DIM_3_STRIDE 0xF46704
+
+#define mmTPC5_CFG_KERNEL_TENSOR_13_DIM_4_SIZE 0xF46708
+
+#define mmTPC5_CFG_KERNEL_TENSOR_13_DIM_4_STRIDE 0xF4670C
+
+#define mmTPC5_CFG_KERNEL_TENSOR_14_BASE_ADDR_LOW 0xF46710
+
+#define mmTPC5_CFG_KERNEL_TENSOR_14_BASE_ADDR_HIGH 0xF46714
+
+#define mmTPC5_CFG_KERNEL_TENSOR_14_PADDING_VALUE 0xF46718
+
+#define mmTPC5_CFG_KERNEL_TENSOR_14_TENSOR_CONFIG 0xF4671C
+
+#define mmTPC5_CFG_KERNEL_TENSOR_14_DIM_0_SIZE 0xF46720
+
+#define mmTPC5_CFG_KERNEL_TENSOR_14_DIM_0_STRIDE 0xF46724
+
+#define mmTPC5_CFG_KERNEL_TENSOR_14_DIM_1_SIZE 0xF46728
+
+#define mmTPC5_CFG_KERNEL_TENSOR_14_DIM_1_STRIDE 0xF4672C
+
+#define mmTPC5_CFG_KERNEL_TENSOR_14_DIM_2_SIZE 0xF46730
+
+#define mmTPC5_CFG_KERNEL_TENSOR_14_DIM_2_STRIDE 0xF46734
+
+#define mmTPC5_CFG_KERNEL_TENSOR_14_DIM_3_SIZE 0xF46738
+
+#define mmTPC5_CFG_KERNEL_TENSOR_14_DIM_3_STRIDE 0xF4673C
+
+#define mmTPC5_CFG_KERNEL_TENSOR_14_DIM_4_SIZE 0xF46740
+
+#define mmTPC5_CFG_KERNEL_TENSOR_14_DIM_4_STRIDE 0xF46744
+
+#define mmTPC5_CFG_KERNEL_TENSOR_15_BASE_ADDR_LOW 0xF46748
+
+#define mmTPC5_CFG_KERNEL_TENSOR_15_BASE_ADDR_HIGH 0xF4674C
+
+#define mmTPC5_CFG_KERNEL_TENSOR_15_PADDING_VALUE 0xF46750
+
+#define mmTPC5_CFG_KERNEL_TENSOR_15_TENSOR_CONFIG 0xF46754
+
+#define mmTPC5_CFG_KERNEL_TENSOR_15_DIM_0_SIZE 0xF46758
+
+#define mmTPC5_CFG_KERNEL_TENSOR_15_DIM_0_STRIDE 0xF4675C
+
+#define mmTPC5_CFG_KERNEL_TENSOR_15_DIM_1_SIZE 0xF46760
+
+#define mmTPC5_CFG_KERNEL_TENSOR_15_DIM_1_STRIDE 0xF46764
+
+#define mmTPC5_CFG_KERNEL_TENSOR_15_DIM_2_SIZE 0xF46768
+
+#define mmTPC5_CFG_KERNEL_TENSOR_15_DIM_2_STRIDE 0xF4676C
+
+#define mmTPC5_CFG_KERNEL_TENSOR_15_DIM_3_SIZE 0xF46770
+
+#define mmTPC5_CFG_KERNEL_TENSOR_15_DIM_3_STRIDE 0xF46774
+
+#define mmTPC5_CFG_KERNEL_TENSOR_15_DIM_4_SIZE 0xF46778
+
+#define mmTPC5_CFG_KERNEL_TENSOR_15_DIM_4_STRIDE 0xF4677C
+
+#define mmTPC5_CFG_KERNEL_SYNC_OBJECT_MESSAGE 0xF46780
+
+#define mmTPC5_CFG_KERNEL_SYNC_OBJECT_ADDR 0xF46784
+
+#define mmTPC5_CFG_KERNEL_KERNEL_BASE_ADDRESS_LOW 0xF46788
+
+#define mmTPC5_CFG_KERNEL_KERNEL_BASE_ADDRESS_HIGH 0xF4678C
+
+#define mmTPC5_CFG_KERNEL_TID_BASE_DIM_0 0xF46790
+
+#define mmTPC5_CFG_KERNEL_TID_SIZE_DIM_0 0xF46794
+
+#define mmTPC5_CFG_KERNEL_TID_BASE_DIM_1 0xF46798
+
+#define mmTPC5_CFG_KERNEL_TID_SIZE_DIM_1 0xF4679C
+
+#define mmTPC5_CFG_KERNEL_TID_BASE_DIM_2 0xF467A0
+
+#define mmTPC5_CFG_KERNEL_TID_SIZE_DIM_2 0xF467A4
+
+#define mmTPC5_CFG_KERNEL_TID_BASE_DIM_3 0xF467A8
+
+#define mmTPC5_CFG_KERNEL_TID_SIZE_DIM_3 0xF467AC
+
+#define mmTPC5_CFG_KERNEL_TID_BASE_DIM_4 0xF467B0
+
+#define mmTPC5_CFG_KERNEL_TID_SIZE_DIM_4 0xF467B4
+
+#define mmTPC5_CFG_KERNEL_KERNEL_CONFIG 0xF467B8
+
+#define mmTPC5_CFG_KERNEL_KERNEL_ID 0xF467BC
+
+#define mmTPC5_CFG_KERNEL_SRF_0 0xF467C0
+
+#define mmTPC5_CFG_KERNEL_SRF_1 0xF467C4
+
+#define mmTPC5_CFG_KERNEL_SRF_2 0xF467C8
+
+#define mmTPC5_CFG_KERNEL_SRF_3 0xF467CC
+
+#define mmTPC5_CFG_KERNEL_SRF_4 0xF467D0
+
+#define mmTPC5_CFG_KERNEL_SRF_5 0xF467D4
+
+#define mmTPC5_CFG_KERNEL_SRF_6 0xF467D8
+
+#define mmTPC5_CFG_KERNEL_SRF_7 0xF467DC
+
+#define mmTPC5_CFG_KERNEL_SRF_8 0xF467E0
+
+#define mmTPC5_CFG_KERNEL_SRF_9 0xF467E4
+
+#define mmTPC5_CFG_KERNEL_SRF_10 0xF467E8
+
+#define mmTPC5_CFG_KERNEL_SRF_11 0xF467EC
+
+#define mmTPC5_CFG_KERNEL_SRF_12 0xF467F0
+
+#define mmTPC5_CFG_KERNEL_SRF_13 0xF467F4
+
+#define mmTPC5_CFG_KERNEL_SRF_14 0xF467F8
+
+#define mmTPC5_CFG_KERNEL_SRF_15 0xF467FC
+
+#define mmTPC5_CFG_KERNEL_SRF_16 0xF46800
+
+#define mmTPC5_CFG_KERNEL_SRF_17 0xF46804
+
+#define mmTPC5_CFG_KERNEL_SRF_18 0xF46808
+
+#define mmTPC5_CFG_KERNEL_SRF_19 0xF4680C
+
+#define mmTPC5_CFG_KERNEL_SRF_20 0xF46810
+
+#define mmTPC5_CFG_KERNEL_SRF_21 0xF46814
+
+#define mmTPC5_CFG_KERNEL_SRF_22 0xF46818
+
+#define mmTPC5_CFG_KERNEL_SRF_23 0xF4681C
+
+#define mmTPC5_CFG_KERNEL_SRF_24 0xF46820
+
+#define mmTPC5_CFG_KERNEL_SRF_25 0xF46824
+
+#define mmTPC5_CFG_KERNEL_SRF_26 0xF46828
+
+#define mmTPC5_CFG_KERNEL_SRF_27 0xF4682C
+
+#define mmTPC5_CFG_KERNEL_SRF_28 0xF46830
+
+#define mmTPC5_CFG_KERNEL_SRF_29 0xF46834
+
+#define mmTPC5_CFG_KERNEL_SRF_30 0xF46838
+
+#define mmTPC5_CFG_KERNEL_SRF_31 0xF4683C
+
+#define mmTPC5_CFG_ROUND_CSR 0xF468FC
+
+#define mmTPC5_CFG_PROT 0xF46900
+
+#define mmTPC5_CFG_SEMAPHORE 0xF46908
+
+#define mmTPC5_CFG_VFLAGS 0xF4690C
+
+#define mmTPC5_CFG_SFLAGS 0xF46910
+
+#define mmTPC5_CFG_LFSR_POLYNOM 0xF46918
+
+#define mmTPC5_CFG_STATUS 0xF4691C
+
+#define mmTPC5_CFG_CFG_BASE_ADDRESS_HIGH 0xF46920
+
+#define mmTPC5_CFG_CFG_SUBTRACT_VALUE 0xF46924
+
+#define mmTPC5_CFG_SM_BASE_ADDRESS_HIGH 0xF4692C
+
+#define mmTPC5_CFG_TPC_CMD 0xF46930
+
+#define mmTPC5_CFG_TPC_EXECUTE 0xF46938
+
+#define mmTPC5_CFG_TPC_STALL 0xF4693C
+
+#define mmTPC5_CFG_ICACHE_BASE_ADDERESS_LOW 0xF46940
+
+#define mmTPC5_CFG_ICACHE_BASE_ADDERESS_HIGH 0xF46944
+
+#define mmTPC5_CFG_RD_RATE_LIMIT 0xF46948
+
+#define mmTPC5_CFG_WR_RATE_LIMIT 0xF46950
+
+#define mmTPC5_CFG_MSS_CONFIG 0xF46954
+
+#define mmTPC5_CFG_TPC_INTR_CAUSE 0xF46958
+
+#define mmTPC5_CFG_TPC_INTR_MASK 0xF4695C
+
+#define mmTPC5_CFG_WQ_CREDITS 0xF46960
+
+#define mmTPC5_CFG_ARUSER_LO 0xF46964
+
+#define mmTPC5_CFG_ARUSER_HI 0xF46968
+
+#define mmTPC5_CFG_AWUSER_LO 0xF4696C
+
+#define mmTPC5_CFG_AWUSER_HI 0xF46970
+
+#define mmTPC5_CFG_OPCODE_EXEC 0xF46974
+
+#define mmTPC5_CFG_LUT_FUNC32_BASE_ADDR_LO 0xF46978
+
+#define mmTPC5_CFG_LUT_FUNC32_BASE_ADDR_HI 0xF4697C
+
+#define mmTPC5_CFG_LUT_FUNC64_BASE_ADDR_LO 0xF46980
+
+#define mmTPC5_CFG_LUT_FUNC64_BASE_ADDR_HI 0xF46984
+
+#define mmTPC5_CFG_LUT_FUNC128_BASE_ADDR_LO 0xF46988
+
+#define mmTPC5_CFG_LUT_FUNC128_BASE_ADDR_HI 0xF4698C
+
+#define mmTPC5_CFG_LUT_FUNC256_BASE_ADDR_LO 0xF46990
+
+#define mmTPC5_CFG_LUT_FUNC256_BASE_ADDR_HI 0xF46994
+
+#define mmTPC5_CFG_TSB_CFG_MAX_SIZE 0xF46998
+
+#define mmTPC5_CFG_TSB_CFG 0xF4699C
+
+#define mmTPC5_CFG_DBGMEM_ADD 0xF469A0
+
+#define mmTPC5_CFG_DBGMEM_DATA_WR 0xF469A4
+
+#define mmTPC5_CFG_DBGMEM_DATA_RD 0xF469A8
+
+#define mmTPC5_CFG_DBGMEM_CTRL 0xF469AC
+
+#define mmTPC5_CFG_DBGMEM_RC 0xF469B0
+
+#define mmTPC5_CFG_TSB_INFLIGHT_CNTR 0xF469B4
+
+#define mmTPC5_CFG_WQ_INFLIGHT_CNTR 0xF469B8
+
+#define mmTPC5_CFG_WQ_LBW_TOTAL_CNTR 0xF469BC
+
+#define mmTPC5_CFG_WQ_HBW_TOTAL_CNTR 0xF469C0
+
+#define mmTPC5_CFG_IRQ_OCCOUPY_CNTR 0xF469C4
+
+#define mmTPC5_CFG_FUNC_MBIST_CNTRL 0xF469D0
+
+#define mmTPC5_CFG_FUNC_MBIST_PAT 0xF469D4
+
+#define mmTPC5_CFG_FUNC_MBIST_MEM_0 0xF469D8
+
+#define mmTPC5_CFG_FUNC_MBIST_MEM_1 0xF469DC
+
+#define mmTPC5_CFG_FUNC_MBIST_MEM_2 0xF469E0
+
+#define mmTPC5_CFG_FUNC_MBIST_MEM_3 0xF469E4
+
+#define mmTPC5_CFG_FUNC_MBIST_MEM_4 0xF469E8
+
+#define mmTPC5_CFG_FUNC_MBIST_MEM_5 0xF469EC
+
+#define mmTPC5_CFG_FUNC_MBIST_MEM_6 0xF469F0
+
+#define mmTPC5_CFG_FUNC_MBIST_MEM_7 0xF469F4
+
+#define mmTPC5_CFG_FUNC_MBIST_MEM_8 0xF469F8
+
+#define mmTPC5_CFG_FUNC_MBIST_MEM_9 0xF469FC
+
+#define mmTPC5_CFG_QM_TENSOR_0_BASE_ADDR_LOW 0xF46A00
+
+#define mmTPC5_CFG_QM_TENSOR_0_BASE_ADDR_HIGH 0xF46A04
+
+#define mmTPC5_CFG_QM_TENSOR_0_PADDING_VALUE 0xF46A08
+
+#define mmTPC5_CFG_QM_TENSOR_0_TENSOR_CONFIG 0xF46A0C
+
+#define mmTPC5_CFG_QM_TENSOR_0_DIM_0_SIZE 0xF46A10
+
+#define mmTPC5_CFG_QM_TENSOR_0_DIM_0_STRIDE 0xF46A14
+
+#define mmTPC5_CFG_QM_TENSOR_0_DIM_1_SIZE 0xF46A18
+
+#define mmTPC5_CFG_QM_TENSOR_0_DIM_1_STRIDE 0xF46A1C
+
+#define mmTPC5_CFG_QM_TENSOR_0_DIM_2_SIZE 0xF46A20
+
+#define mmTPC5_CFG_QM_TENSOR_0_DIM_2_STRIDE 0xF46A24
+
+#define mmTPC5_CFG_QM_TENSOR_0_DIM_3_SIZE 0xF46A28
+
+#define mmTPC5_CFG_QM_TENSOR_0_DIM_3_STRIDE 0xF46A2C
+
+#define mmTPC5_CFG_QM_TENSOR_0_DIM_4_SIZE 0xF46A30
+
+#define mmTPC5_CFG_QM_TENSOR_0_DIM_4_STRIDE 0xF46A34
+
+#define mmTPC5_CFG_QM_TENSOR_1_BASE_ADDR_LOW 0xF46A38
+
+#define mmTPC5_CFG_QM_TENSOR_1_BASE_ADDR_HIGH 0xF46A3C
+
+#define mmTPC5_CFG_QM_TENSOR_1_PADDING_VALUE 0xF46A40
+
+#define mmTPC5_CFG_QM_TENSOR_1_TENSOR_CONFIG 0xF46A44
+
+#define mmTPC5_CFG_QM_TENSOR_1_DIM_0_SIZE 0xF46A48
+
+#define mmTPC5_CFG_QM_TENSOR_1_DIM_0_STRIDE 0xF46A4C
+
+#define mmTPC5_CFG_QM_TENSOR_1_DIM_1_SIZE 0xF46A50
+
+#define mmTPC5_CFG_QM_TENSOR_1_DIM_1_STRIDE 0xF46A54
+
+#define mmTPC5_CFG_QM_TENSOR_1_DIM_2_SIZE 0xF46A58
+
+#define mmTPC5_CFG_QM_TENSOR_1_DIM_2_STRIDE 0xF46A5C
+
+#define mmTPC5_CFG_QM_TENSOR_1_DIM_3_SIZE 0xF46A60
+
+#define mmTPC5_CFG_QM_TENSOR_1_DIM_3_STRIDE 0xF46A64
+
+#define mmTPC5_CFG_QM_TENSOR_1_DIM_4_SIZE 0xF46A68
+
+#define mmTPC5_CFG_QM_TENSOR_1_DIM_4_STRIDE 0xF46A6C
+
+#define mmTPC5_CFG_QM_TENSOR_2_BASE_ADDR_LOW 0xF46A70
+
+#define mmTPC5_CFG_QM_TENSOR_2_BASE_ADDR_HIGH 0xF46A74
+
+#define mmTPC5_CFG_QM_TENSOR_2_PADDING_VALUE 0xF46A78
+
+#define mmTPC5_CFG_QM_TENSOR_2_TENSOR_CONFIG 0xF46A7C
+
+#define mmTPC5_CFG_QM_TENSOR_2_DIM_0_SIZE 0xF46A80
+
+#define mmTPC5_CFG_QM_TENSOR_2_DIM_0_STRIDE 0xF46A84
+
+#define mmTPC5_CFG_QM_TENSOR_2_DIM_1_SIZE 0xF46A88
+
+#define mmTPC5_CFG_QM_TENSOR_2_DIM_1_STRIDE 0xF46A8C
+
+#define mmTPC5_CFG_QM_TENSOR_2_DIM_2_SIZE 0xF46A90
+
+#define mmTPC5_CFG_QM_TENSOR_2_DIM_2_STRIDE 0xF46A94
+
+#define mmTPC5_CFG_QM_TENSOR_2_DIM_3_SIZE 0xF46A98
+
+#define mmTPC5_CFG_QM_TENSOR_2_DIM_3_STRIDE 0xF46A9C
+
+#define mmTPC5_CFG_QM_TENSOR_2_DIM_4_SIZE 0xF46AA0
+
+#define mmTPC5_CFG_QM_TENSOR_2_DIM_4_STRIDE 0xF46AA4
+
+#define mmTPC5_CFG_QM_TENSOR_3_BASE_ADDR_LOW 0xF46AA8
+
+#define mmTPC5_CFG_QM_TENSOR_3_BASE_ADDR_HIGH 0xF46AAC
+
+#define mmTPC5_CFG_QM_TENSOR_3_PADDING_VALUE 0xF46AB0
+
+#define mmTPC5_CFG_QM_TENSOR_3_TENSOR_CONFIG 0xF46AB4
+
+#define mmTPC5_CFG_QM_TENSOR_3_DIM_0_SIZE 0xF46AB8
+
+#define mmTPC5_CFG_QM_TENSOR_3_DIM_0_STRIDE 0xF46ABC
+
+#define mmTPC5_CFG_QM_TENSOR_3_DIM_1_SIZE 0xF46AC0
+
+#define mmTPC5_CFG_QM_TENSOR_3_DIM_1_STRIDE 0xF46AC4
+
+#define mmTPC5_CFG_QM_TENSOR_3_DIM_2_SIZE 0xF46AC8
+
+#define mmTPC5_CFG_QM_TENSOR_3_DIM_2_STRIDE 0xF46ACC
+
+#define mmTPC5_CFG_QM_TENSOR_3_DIM_3_SIZE 0xF46AD0
+
+#define mmTPC5_CFG_QM_TENSOR_3_DIM_3_STRIDE 0xF46AD4
+
+#define mmTPC5_CFG_QM_TENSOR_3_DIM_4_SIZE 0xF46AD8
+
+#define mmTPC5_CFG_QM_TENSOR_3_DIM_4_STRIDE 0xF46ADC
+
+#define mmTPC5_CFG_QM_TENSOR_4_BASE_ADDR_LOW 0xF46AE0
+
+#define mmTPC5_CFG_QM_TENSOR_4_BASE_ADDR_HIGH 0xF46AE4
+
+#define mmTPC5_CFG_QM_TENSOR_4_PADDING_VALUE 0xF46AE8
+
+#define mmTPC5_CFG_QM_TENSOR_4_TENSOR_CONFIG 0xF46AEC
+
+#define mmTPC5_CFG_QM_TENSOR_4_DIM_0_SIZE 0xF46AF0
+
+#define mmTPC5_CFG_QM_TENSOR_4_DIM_0_STRIDE 0xF46AF4
+
+#define mmTPC5_CFG_QM_TENSOR_4_DIM_1_SIZE 0xF46AF8
+
+#define mmTPC5_CFG_QM_TENSOR_4_DIM_1_STRIDE 0xF46AFC
+
+#define mmTPC5_CFG_QM_TENSOR_4_DIM_2_SIZE 0xF46B00
+
+#define mmTPC5_CFG_QM_TENSOR_4_DIM_2_STRIDE 0xF46B04
+
+#define mmTPC5_CFG_QM_TENSOR_4_DIM_3_SIZE 0xF46B08
+
+#define mmTPC5_CFG_QM_TENSOR_4_DIM_3_STRIDE 0xF46B0C
+
+#define mmTPC5_CFG_QM_TENSOR_4_DIM_4_SIZE 0xF46B10
+
+#define mmTPC5_CFG_QM_TENSOR_4_DIM_4_STRIDE 0xF46B14
+
+#define mmTPC5_CFG_QM_TENSOR_5_BASE_ADDR_LOW 0xF46B18
+
+#define mmTPC5_CFG_QM_TENSOR_5_BASE_ADDR_HIGH 0xF46B1C
+
+#define mmTPC5_CFG_QM_TENSOR_5_PADDING_VALUE 0xF46B20
+
+#define mmTPC5_CFG_QM_TENSOR_5_TENSOR_CONFIG 0xF46B24
+
+#define mmTPC5_CFG_QM_TENSOR_5_DIM_0_SIZE 0xF46B28
+
+#define mmTPC5_CFG_QM_TENSOR_5_DIM_0_STRIDE 0xF46B2C
+
+#define mmTPC5_CFG_QM_TENSOR_5_DIM_1_SIZE 0xF46B30
+
+#define mmTPC5_CFG_QM_TENSOR_5_DIM_1_STRIDE 0xF46B34
+
+#define mmTPC5_CFG_QM_TENSOR_5_DIM_2_SIZE 0xF46B38
+
+#define mmTPC5_CFG_QM_TENSOR_5_DIM_2_STRIDE 0xF46B3C
+
+#define mmTPC5_CFG_QM_TENSOR_5_DIM_3_SIZE 0xF46B40
+
+#define mmTPC5_CFG_QM_TENSOR_5_DIM_3_STRIDE 0xF46B44
+
+#define mmTPC5_CFG_QM_TENSOR_5_DIM_4_SIZE 0xF46B48
+
+#define mmTPC5_CFG_QM_TENSOR_5_DIM_4_STRIDE 0xF46B4C
+
+#define mmTPC5_CFG_QM_TENSOR_6_BASE_ADDR_LOW 0xF46B50
+
+#define mmTPC5_CFG_QM_TENSOR_6_BASE_ADDR_HIGH 0xF46B54
+
+#define mmTPC5_CFG_QM_TENSOR_6_PADDING_VALUE 0xF46B58
+
+#define mmTPC5_CFG_QM_TENSOR_6_TENSOR_CONFIG 0xF46B5C
+
+#define mmTPC5_CFG_QM_TENSOR_6_DIM_0_SIZE 0xF46B60
+
+#define mmTPC5_CFG_QM_TENSOR_6_DIM_0_STRIDE 0xF46B64
+
+#define mmTPC5_CFG_QM_TENSOR_6_DIM_1_SIZE 0xF46B68
+
+#define mmTPC5_CFG_QM_TENSOR_6_DIM_1_STRIDE 0xF46B6C
+
+#define mmTPC5_CFG_QM_TENSOR_6_DIM_2_SIZE 0xF46B70
+
+#define mmTPC5_CFG_QM_TENSOR_6_DIM_2_STRIDE 0xF46B74
+
+#define mmTPC5_CFG_QM_TENSOR_6_DIM_3_SIZE 0xF46B78
+
+#define mmTPC5_CFG_QM_TENSOR_6_DIM_3_STRIDE 0xF46B7C
+
+#define mmTPC5_CFG_QM_TENSOR_6_DIM_4_SIZE 0xF46B80
+
+#define mmTPC5_CFG_QM_TENSOR_6_DIM_4_STRIDE 0xF46B84
+
+#define mmTPC5_CFG_QM_TENSOR_7_BASE_ADDR_LOW 0xF46B88
+
+#define mmTPC5_CFG_QM_TENSOR_7_BASE_ADDR_HIGH 0xF46B8C
+
+#define mmTPC5_CFG_QM_TENSOR_7_PADDING_VALUE 0xF46B90
+
+#define mmTPC5_CFG_QM_TENSOR_7_TENSOR_CONFIG 0xF46B94
+
+#define mmTPC5_CFG_QM_TENSOR_7_DIM_0_SIZE 0xF46B98
+
+#define mmTPC5_CFG_QM_TENSOR_7_DIM_0_STRIDE 0xF46B9C
+
+#define mmTPC5_CFG_QM_TENSOR_7_DIM_1_SIZE 0xF46BA0
+
+#define mmTPC5_CFG_QM_TENSOR_7_DIM_1_STRIDE 0xF46BA4
+
+#define mmTPC5_CFG_QM_TENSOR_7_DIM_2_SIZE 0xF46BA8
+
+#define mmTPC5_CFG_QM_TENSOR_7_DIM_2_STRIDE 0xF46BAC
+
+#define mmTPC5_CFG_QM_TENSOR_7_DIM_3_SIZE 0xF46BB0
+
+#define mmTPC5_CFG_QM_TENSOR_7_DIM_3_STRIDE 0xF46BB4
+
+#define mmTPC5_CFG_QM_TENSOR_7_DIM_4_SIZE 0xF46BB8
+
+#define mmTPC5_CFG_QM_TENSOR_7_DIM_4_STRIDE 0xF46BBC
+
+#define mmTPC5_CFG_QM_TENSOR_8_BASE_ADDR_LOW 0xF46BC0
+
+#define mmTPC5_CFG_QM_TENSOR_8_BASE_ADDR_HIGH 0xF46BC4
+
+#define mmTPC5_CFG_QM_TENSOR_8_PADDING_VALUE 0xF46BC8
+
+#define mmTPC5_CFG_QM_TENSOR_8_TENSOR_CONFIG 0xF46BCC
+
+#define mmTPC5_CFG_QM_TENSOR_8_DIM_0_SIZE 0xF46BD0
+
+#define mmTPC5_CFG_QM_TENSOR_8_DIM_0_STRIDE 0xF46BD4
+
+#define mmTPC5_CFG_QM_TENSOR_8_DIM_1_SIZE 0xF46BD8
+
+#define mmTPC5_CFG_QM_TENSOR_8_DIM_1_STRIDE 0xF46BDC
+
+#define mmTPC5_CFG_QM_TENSOR_8_DIM_2_SIZE 0xF46BE0
+
+#define mmTPC5_CFG_QM_TENSOR_8_DIM_2_STRIDE 0xF46BE4
+
+#define mmTPC5_CFG_QM_TENSOR_8_DIM_3_SIZE 0xF46BE8
+
+#define mmTPC5_CFG_QM_TENSOR_8_DIM_3_STRIDE 0xF46BEC
+
+#define mmTPC5_CFG_QM_TENSOR_8_DIM_4_SIZE 0xF46BF0
+
+#define mmTPC5_CFG_QM_TENSOR_8_DIM_4_STRIDE 0xF46BF4
+
+#define mmTPC5_CFG_QM_TENSOR_9_BASE_ADDR_LOW 0xF46BF8
+
+#define mmTPC5_CFG_QM_TENSOR_9_BASE_ADDR_HIGH 0xF46BFC
+
+#define mmTPC5_CFG_QM_TENSOR_9_PADDING_VALUE 0xF46C00
+
+#define mmTPC5_CFG_QM_TENSOR_9_TENSOR_CONFIG 0xF46C04
+
+#define mmTPC5_CFG_QM_TENSOR_9_DIM_0_SIZE 0xF46C08
+
+#define mmTPC5_CFG_QM_TENSOR_9_DIM_0_STRIDE 0xF46C0C
+
+#define mmTPC5_CFG_QM_TENSOR_9_DIM_1_SIZE 0xF46C10
+
+#define mmTPC5_CFG_QM_TENSOR_9_DIM_1_STRIDE 0xF46C14
+
+#define mmTPC5_CFG_QM_TENSOR_9_DIM_2_SIZE 0xF46C18
+
+#define mmTPC5_CFG_QM_TENSOR_9_DIM_2_STRIDE 0xF46C1C
+
+#define mmTPC5_CFG_QM_TENSOR_9_DIM_3_SIZE 0xF46C20
+
+#define mmTPC5_CFG_QM_TENSOR_9_DIM_3_STRIDE 0xF46C24
+
+#define mmTPC5_CFG_QM_TENSOR_9_DIM_4_SIZE 0xF46C28
+
+#define mmTPC5_CFG_QM_TENSOR_9_DIM_4_STRIDE 0xF46C2C
+
+#define mmTPC5_CFG_QM_TENSOR_10_BASE_ADDR_LOW 0xF46C30
+
+#define mmTPC5_CFG_QM_TENSOR_10_BASE_ADDR_HIGH 0xF46C34
+
+#define mmTPC5_CFG_QM_TENSOR_10_PADDING_VALUE 0xF46C38
+
+#define mmTPC5_CFG_QM_TENSOR_10_TENSOR_CONFIG 0xF46C3C
+
+#define mmTPC5_CFG_QM_TENSOR_10_DIM_0_SIZE 0xF46C40
+
+#define mmTPC5_CFG_QM_TENSOR_10_DIM_0_STRIDE 0xF46C44
+
+#define mmTPC5_CFG_QM_TENSOR_10_DIM_1_SIZE 0xF46C48
+
+#define mmTPC5_CFG_QM_TENSOR_10_DIM_1_STRIDE 0xF46C4C
+
+#define mmTPC5_CFG_QM_TENSOR_10_DIM_2_SIZE 0xF46C50
+
+#define mmTPC5_CFG_QM_TENSOR_10_DIM_2_STRIDE 0xF46C54
+
+#define mmTPC5_CFG_QM_TENSOR_10_DIM_3_SIZE 0xF46C58
+
+#define mmTPC5_CFG_QM_TENSOR_10_DIM_3_STRIDE 0xF46C5C
+
+#define mmTPC5_CFG_QM_TENSOR_10_DIM_4_SIZE 0xF46C60
+
+#define mmTPC5_CFG_QM_TENSOR_10_DIM_4_STRIDE 0xF46C64
+
+#define mmTPC5_CFG_QM_TENSOR_11_BASE_ADDR_LOW 0xF46C68
+
+#define mmTPC5_CFG_QM_TENSOR_11_BASE_ADDR_HIGH 0xF46C6C
+
+#define mmTPC5_CFG_QM_TENSOR_11_PADDING_VALUE 0xF46C70
+
+#define mmTPC5_CFG_QM_TENSOR_11_TENSOR_CONFIG 0xF46C74
+
+#define mmTPC5_CFG_QM_TENSOR_11_DIM_0_SIZE 0xF46C78
+
+#define mmTPC5_CFG_QM_TENSOR_11_DIM_0_STRIDE 0xF46C7C
+
+#define mmTPC5_CFG_QM_TENSOR_11_DIM_1_SIZE 0xF46C80
+
+#define mmTPC5_CFG_QM_TENSOR_11_DIM_1_STRIDE 0xF46C84
+
+#define mmTPC5_CFG_QM_TENSOR_11_DIM_2_SIZE 0xF46C88
+
+#define mmTPC5_CFG_QM_TENSOR_11_DIM_2_STRIDE 0xF46C8C
+
+#define mmTPC5_CFG_QM_TENSOR_11_DIM_3_SIZE 0xF46C90
+
+#define mmTPC5_CFG_QM_TENSOR_11_DIM_3_STRIDE 0xF46C94
+
+#define mmTPC5_CFG_QM_TENSOR_11_DIM_4_SIZE 0xF46C98
+
+#define mmTPC5_CFG_QM_TENSOR_11_DIM_4_STRIDE 0xF46C9C
+
+#define mmTPC5_CFG_QM_TENSOR_12_BASE_ADDR_LOW 0xF46CA0
+
+#define mmTPC5_CFG_QM_TENSOR_12_BASE_ADDR_HIGH 0xF46CA4
+
+#define mmTPC5_CFG_QM_TENSOR_12_PADDING_VALUE 0xF46CA8
+
+#define mmTPC5_CFG_QM_TENSOR_12_TENSOR_CONFIG 0xF46CAC
+
+#define mmTPC5_CFG_QM_TENSOR_12_DIM_0_SIZE 0xF46CB0
+
+#define mmTPC5_CFG_QM_TENSOR_12_DIM_0_STRIDE 0xF46CB4
+
+#define mmTPC5_CFG_QM_TENSOR_12_DIM_1_SIZE 0xF46CB8
+
+#define mmTPC5_CFG_QM_TENSOR_12_DIM_1_STRIDE 0xF46CBC
+
+#define mmTPC5_CFG_QM_TENSOR_12_DIM_2_SIZE 0xF46CC0
+
+#define mmTPC5_CFG_QM_TENSOR_12_DIM_2_STRIDE 0xF46CC4
+
+#define mmTPC5_CFG_QM_TENSOR_12_DIM_3_SIZE 0xF46CC8
+
+#define mmTPC5_CFG_QM_TENSOR_12_DIM_3_STRIDE 0xF46CCC
+
+#define mmTPC5_CFG_QM_TENSOR_12_DIM_4_SIZE 0xF46CD0
+
+#define mmTPC5_CFG_QM_TENSOR_12_DIM_4_STRIDE 0xF46CD4
+
+#define mmTPC5_CFG_QM_TENSOR_13_BASE_ADDR_LOW 0xF46CD8
+
+#define mmTPC5_CFG_QM_TENSOR_13_BASE_ADDR_HIGH 0xF46CDC
+
+#define mmTPC5_CFG_QM_TENSOR_13_PADDING_VALUE 0xF46CE0
+
+#define mmTPC5_CFG_QM_TENSOR_13_TENSOR_CONFIG 0xF46CE4
+
+#define mmTPC5_CFG_QM_TENSOR_13_DIM_0_SIZE 0xF46CE8
+
+#define mmTPC5_CFG_QM_TENSOR_13_DIM_0_STRIDE 0xF46CEC
+
+#define mmTPC5_CFG_QM_TENSOR_13_DIM_1_SIZE 0xF46CF0
+
+#define mmTPC5_CFG_QM_TENSOR_13_DIM_1_STRIDE 0xF46CF4
+
+#define mmTPC5_CFG_QM_TENSOR_13_DIM_2_SIZE 0xF46CF8
+
+#define mmTPC5_CFG_QM_TENSOR_13_DIM_2_STRIDE 0xF46CFC
+
+#define mmTPC5_CFG_QM_TENSOR_13_DIM_3_SIZE 0xF46D00
+
+#define mmTPC5_CFG_QM_TENSOR_13_DIM_3_STRIDE 0xF46D04
+
+#define mmTPC5_CFG_QM_TENSOR_13_DIM_4_SIZE 0xF46D08
+
+#define mmTPC5_CFG_QM_TENSOR_13_DIM_4_STRIDE 0xF46D0C
+
+#define mmTPC5_CFG_QM_TENSOR_14_BASE_ADDR_LOW 0xF46D10
+
+#define mmTPC5_CFG_QM_TENSOR_14_BASE_ADDR_HIGH 0xF46D14
+
+#define mmTPC5_CFG_QM_TENSOR_14_PADDING_VALUE 0xF46D18
+
+#define mmTPC5_CFG_QM_TENSOR_14_TENSOR_CONFIG 0xF46D1C
+
+#define mmTPC5_CFG_QM_TENSOR_14_DIM_0_SIZE 0xF46D20
+
+#define mmTPC5_CFG_QM_TENSOR_14_DIM_0_STRIDE 0xF46D24
+
+#define mmTPC5_CFG_QM_TENSOR_14_DIM_1_SIZE 0xF46D28
+
+#define mmTPC5_CFG_QM_TENSOR_14_DIM_1_STRIDE 0xF46D2C
+
+#define mmTPC5_CFG_QM_TENSOR_14_DIM_2_SIZE 0xF46D30
+
+#define mmTPC5_CFG_QM_TENSOR_14_DIM_2_STRIDE 0xF46D34
+
+#define mmTPC5_CFG_QM_TENSOR_14_DIM_3_SIZE 0xF46D38
+
+#define mmTPC5_CFG_QM_TENSOR_14_DIM_3_STRIDE 0xF46D3C
+
+#define mmTPC5_CFG_QM_TENSOR_14_DIM_4_SIZE 0xF46D40
+
+#define mmTPC5_CFG_QM_TENSOR_14_DIM_4_STRIDE 0xF46D44
+
+#define mmTPC5_CFG_QM_TENSOR_15_BASE_ADDR_LOW 0xF46D48
+
+#define mmTPC5_CFG_QM_TENSOR_15_BASE_ADDR_HIGH 0xF46D4C
+
+#define mmTPC5_CFG_QM_TENSOR_15_PADDING_VALUE 0xF46D50
+
+#define mmTPC5_CFG_QM_TENSOR_15_TENSOR_CONFIG 0xF46D54
+
+#define mmTPC5_CFG_QM_TENSOR_15_DIM_0_SIZE 0xF46D58
+
+#define mmTPC5_CFG_QM_TENSOR_15_DIM_0_STRIDE 0xF46D5C
+
+#define mmTPC5_CFG_QM_TENSOR_15_DIM_1_SIZE 0xF46D60
+
+#define mmTPC5_CFG_QM_TENSOR_15_DIM_1_STRIDE 0xF46D64
+
+#define mmTPC5_CFG_QM_TENSOR_15_DIM_2_SIZE 0xF46D68
+
+#define mmTPC5_CFG_QM_TENSOR_15_DIM_2_STRIDE 0xF46D6C
+
+#define mmTPC5_CFG_QM_TENSOR_15_DIM_3_SIZE 0xF46D70
+
+#define mmTPC5_CFG_QM_TENSOR_15_DIM_3_STRIDE 0xF46D74
+
+#define mmTPC5_CFG_QM_TENSOR_15_DIM_4_SIZE 0xF46D78
+
+#define mmTPC5_CFG_QM_TENSOR_15_DIM_4_STRIDE 0xF46D7C
+
+#define mmTPC5_CFG_QM_SYNC_OBJECT_MESSAGE 0xF46D80
+
+#define mmTPC5_CFG_QM_SYNC_OBJECT_ADDR 0xF46D84
+
+#define mmTPC5_CFG_QM_KERNEL_BASE_ADDRESS_LOW 0xF46D88
+
+#define mmTPC5_CFG_QM_KERNEL_BASE_ADDRESS_HIGH 0xF46D8C
+
+#define mmTPC5_CFG_QM_TID_BASE_DIM_0 0xF46D90
+
+#define mmTPC5_CFG_QM_TID_SIZE_DIM_0 0xF46D94
+
+#define mmTPC5_CFG_QM_TID_BASE_DIM_1 0xF46D98
+
+#define mmTPC5_CFG_QM_TID_SIZE_DIM_1 0xF46D9C
+
+#define mmTPC5_CFG_QM_TID_BASE_DIM_2 0xF46DA0
+
+#define mmTPC5_CFG_QM_TID_SIZE_DIM_2 0xF46DA4
+
+#define mmTPC5_CFG_QM_TID_BASE_DIM_3 0xF46DA8
+
+#define mmTPC5_CFG_QM_TID_SIZE_DIM_3 0xF46DAC
+
+#define mmTPC5_CFG_QM_TID_BASE_DIM_4 0xF46DB0
+
+#define mmTPC5_CFG_QM_TID_SIZE_DIM_4 0xF46DB4
+
+#define mmTPC5_CFG_QM_KERNEL_CONFIG 0xF46DB8
+
+#define mmTPC5_CFG_QM_KERNEL_ID 0xF46DBC
+
+#define mmTPC5_CFG_QM_SRF_0 0xF46DC0
+
+#define mmTPC5_CFG_QM_SRF_1 0xF46DC4
+
+#define mmTPC5_CFG_QM_SRF_2 0xF46DC8
+
+#define mmTPC5_CFG_QM_SRF_3 0xF46DCC
+
+#define mmTPC5_CFG_QM_SRF_4 0xF46DD0
+
+#define mmTPC5_CFG_QM_SRF_5 0xF46DD4
+
+#define mmTPC5_CFG_QM_SRF_6 0xF46DD8
+
+#define mmTPC5_CFG_QM_SRF_7 0xF46DDC
+
+#define mmTPC5_CFG_QM_SRF_8 0xF46DE0
+
+#define mmTPC5_CFG_QM_SRF_9 0xF46DE4
+
+#define mmTPC5_CFG_QM_SRF_10 0xF46DE8
+
+#define mmTPC5_CFG_QM_SRF_11 0xF46DEC
+
+#define mmTPC5_CFG_QM_SRF_12 0xF46DF0
+
+#define mmTPC5_CFG_QM_SRF_13 0xF46DF4
+
+#define mmTPC5_CFG_QM_SRF_14 0xF46DF8
+
+#define mmTPC5_CFG_QM_SRF_15 0xF46DFC
+
+#define mmTPC5_CFG_QM_SRF_16 0xF46E00
+
+#define mmTPC5_CFG_QM_SRF_17 0xF46E04
+
+#define mmTPC5_CFG_QM_SRF_18 0xF46E08
+
+#define mmTPC5_CFG_QM_SRF_19 0xF46E0C
+
+#define mmTPC5_CFG_QM_SRF_20 0xF46E10
+
+#define mmTPC5_CFG_QM_SRF_21 0xF46E14
+
+#define mmTPC5_CFG_QM_SRF_22 0xF46E18
+
+#define mmTPC5_CFG_QM_SRF_23 0xF46E1C
+
+#define mmTPC5_CFG_QM_SRF_24 0xF46E20
+
+#define mmTPC5_CFG_QM_SRF_25 0xF46E24
+
+#define mmTPC5_CFG_QM_SRF_26 0xF46E28
+
+#define mmTPC5_CFG_QM_SRF_27 0xF46E2C
+
+#define mmTPC5_CFG_QM_SRF_28 0xF46E30
+
+#define mmTPC5_CFG_QM_SRF_29 0xF46E34
+
+#define mmTPC5_CFG_QM_SRF_30 0xF46E38
+
+#define mmTPC5_CFG_QM_SRF_31 0xF46E3C
+
+#endif /* ASIC_REG_TPC5_CFG_REGS_H_ */
diff --git a/drivers/accel/habanalabs/include/gaudi/asic_reg/tpc5_qm_regs.h b/drivers/accel/habanalabs/include/gaudi/asic_reg/tpc5_qm_regs.h
new file mode 100644
index 0000000000..cd3a810ff4
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi/asic_reg/tpc5_qm_regs.h
@@ -0,0 +1,834 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2016-2018 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ ** DO NOT EDIT BELOW **
+ ************************************/
+
+#ifndef ASIC_REG_TPC5_QM_REGS_H_
+#define ASIC_REG_TPC5_QM_REGS_H_
+
+/*
+ *****************************************
+ * TPC5_QM (Prototype: QMAN)
+ *****************************************
+ */
+
+#define mmTPC5_QM_GLBL_CFG0 0xF48000
+
+#define mmTPC5_QM_GLBL_CFG1 0xF48004
+
+#define mmTPC5_QM_GLBL_PROT 0xF48008
+
+#define mmTPC5_QM_GLBL_ERR_CFG 0xF4800C
+
+#define mmTPC5_QM_GLBL_SECURE_PROPS_0 0xF48010
+
+#define mmTPC5_QM_GLBL_SECURE_PROPS_1 0xF48014
+
+#define mmTPC5_QM_GLBL_SECURE_PROPS_2 0xF48018
+
+#define mmTPC5_QM_GLBL_SECURE_PROPS_3 0xF4801C
+
+#define mmTPC5_QM_GLBL_SECURE_PROPS_4 0xF48020
+
+#define mmTPC5_QM_GLBL_NON_SECURE_PROPS_0 0xF48024
+
+#define mmTPC5_QM_GLBL_NON_SECURE_PROPS_1 0xF48028
+
+#define mmTPC5_QM_GLBL_NON_SECURE_PROPS_2 0xF4802C
+
+#define mmTPC5_QM_GLBL_NON_SECURE_PROPS_3 0xF48030
+
+#define mmTPC5_QM_GLBL_NON_SECURE_PROPS_4 0xF48034
+
+#define mmTPC5_QM_GLBL_STS0 0xF48038
+
+#define mmTPC5_QM_GLBL_STS1_0 0xF48040
+
+#define mmTPC5_QM_GLBL_STS1_1 0xF48044
+
+#define mmTPC5_QM_GLBL_STS1_2 0xF48048
+
+#define mmTPC5_QM_GLBL_STS1_3 0xF4804C
+
+#define mmTPC5_QM_GLBL_STS1_4 0xF48050
+
+#define mmTPC5_QM_GLBL_MSG_EN_0 0xF48054
+
+#define mmTPC5_QM_GLBL_MSG_EN_1 0xF48058
+
+#define mmTPC5_QM_GLBL_MSG_EN_2 0xF4805C
+
+#define mmTPC5_QM_GLBL_MSG_EN_3 0xF48060
+
+#define mmTPC5_QM_GLBL_MSG_EN_4 0xF48068
+
+#define mmTPC5_QM_PQ_BASE_LO_0 0xF48070
+
+#define mmTPC5_QM_PQ_BASE_LO_1 0xF48074
+
+#define mmTPC5_QM_PQ_BASE_LO_2 0xF48078
+
+#define mmTPC5_QM_PQ_BASE_LO_3 0xF4807C
+
+#define mmTPC5_QM_PQ_BASE_HI_0 0xF48080
+
+#define mmTPC5_QM_PQ_BASE_HI_1 0xF48084
+
+#define mmTPC5_QM_PQ_BASE_HI_2 0xF48088
+
+#define mmTPC5_QM_PQ_BASE_HI_3 0xF4808C
+
+#define mmTPC5_QM_PQ_SIZE_0 0xF48090
+
+#define mmTPC5_QM_PQ_SIZE_1 0xF48094
+
+#define mmTPC5_QM_PQ_SIZE_2 0xF48098
+
+#define mmTPC5_QM_PQ_SIZE_3 0xF4809C
+
+#define mmTPC5_QM_PQ_PI_0 0xF480A0
+
+#define mmTPC5_QM_PQ_PI_1 0xF480A4
+
+#define mmTPC5_QM_PQ_PI_2 0xF480A8
+
+#define mmTPC5_QM_PQ_PI_3 0xF480AC
+
+#define mmTPC5_QM_PQ_CI_0 0xF480B0
+
+#define mmTPC5_QM_PQ_CI_1 0xF480B4
+
+#define mmTPC5_QM_PQ_CI_2 0xF480B8
+
+#define mmTPC5_QM_PQ_CI_3 0xF480BC
+
+#define mmTPC5_QM_PQ_CFG0_0 0xF480C0
+
+#define mmTPC5_QM_PQ_CFG0_1 0xF480C4
+
+#define mmTPC5_QM_PQ_CFG0_2 0xF480C8
+
+#define mmTPC5_QM_PQ_CFG0_3 0xF480CC
+
+#define mmTPC5_QM_PQ_CFG1_0 0xF480D0
+
+#define mmTPC5_QM_PQ_CFG1_1 0xF480D4
+
+#define mmTPC5_QM_PQ_CFG1_2 0xF480D8
+
+#define mmTPC5_QM_PQ_CFG1_3 0xF480DC
+
+#define mmTPC5_QM_PQ_ARUSER_31_11_0 0xF480E0
+
+#define mmTPC5_QM_PQ_ARUSER_31_11_1 0xF480E4
+
+#define mmTPC5_QM_PQ_ARUSER_31_11_2 0xF480E8
+
+#define mmTPC5_QM_PQ_ARUSER_31_11_3 0xF480EC
+
+#define mmTPC5_QM_PQ_STS0_0 0xF480F0
+
+#define mmTPC5_QM_PQ_STS0_1 0xF480F4
+
+#define mmTPC5_QM_PQ_STS0_2 0xF480F8
+
+#define mmTPC5_QM_PQ_STS0_3 0xF480FC
+
+#define mmTPC5_QM_PQ_STS1_0 0xF48100
+
+#define mmTPC5_QM_PQ_STS1_1 0xF48104
+
+#define mmTPC5_QM_PQ_STS1_2 0xF48108
+
+#define mmTPC5_QM_PQ_STS1_3 0xF4810C
+
+#define mmTPC5_QM_CQ_CFG0_0 0xF48110
+
+#define mmTPC5_QM_CQ_CFG0_1 0xF48114
+
+#define mmTPC5_QM_CQ_CFG0_2 0xF48118
+
+#define mmTPC5_QM_CQ_CFG0_3 0xF4811C
+
+#define mmTPC5_QM_CQ_CFG0_4 0xF48120
+
+#define mmTPC5_QM_CQ_CFG1_0 0xF48124
+
+#define mmTPC5_QM_CQ_CFG1_1 0xF48128
+
+#define mmTPC5_QM_CQ_CFG1_2 0xF4812C
+
+#define mmTPC5_QM_CQ_CFG1_3 0xF48130
+
+#define mmTPC5_QM_CQ_CFG1_4 0xF48134
+
+#define mmTPC5_QM_CQ_ARUSER_31_11_0 0xF48138
+
+#define mmTPC5_QM_CQ_ARUSER_31_11_1 0xF4813C
+
+#define mmTPC5_QM_CQ_ARUSER_31_11_2 0xF48140
+
+#define mmTPC5_QM_CQ_ARUSER_31_11_3 0xF48144
+
+#define mmTPC5_QM_CQ_ARUSER_31_11_4 0xF48148
+
+#define mmTPC5_QM_CQ_STS0_0 0xF4814C
+
+#define mmTPC5_QM_CQ_STS0_1 0xF48150
+
+#define mmTPC5_QM_CQ_STS0_2 0xF48154
+
+#define mmTPC5_QM_CQ_STS0_3 0xF48158
+
+#define mmTPC5_QM_CQ_STS0_4 0xF4815C
+
+#define mmTPC5_QM_CQ_STS1_0 0xF48160
+
+#define mmTPC5_QM_CQ_STS1_1 0xF48164
+
+#define mmTPC5_QM_CQ_STS1_2 0xF48168
+
+#define mmTPC5_QM_CQ_STS1_3 0xF4816C
+
+#define mmTPC5_QM_CQ_STS1_4 0xF48170
+
+#define mmTPC5_QM_CQ_PTR_LO_0 0xF48174
+
+#define mmTPC5_QM_CQ_PTR_HI_0 0xF48178
+
+#define mmTPC5_QM_CQ_TSIZE_0 0xF4817C
+
+#define mmTPC5_QM_CQ_CTL_0 0xF48180
+
+#define mmTPC5_QM_CQ_PTR_LO_1 0xF48184
+
+#define mmTPC5_QM_CQ_PTR_HI_1 0xF48188
+
+#define mmTPC5_QM_CQ_TSIZE_1 0xF4818C
+
+#define mmTPC5_QM_CQ_CTL_1 0xF48190
+
+#define mmTPC5_QM_CQ_PTR_LO_2 0xF48194
+
+#define mmTPC5_QM_CQ_PTR_HI_2 0xF48198
+
+#define mmTPC5_QM_CQ_TSIZE_2 0xF4819C
+
+#define mmTPC5_QM_CQ_CTL_2 0xF481A0
+
+#define mmTPC5_QM_CQ_PTR_LO_3 0xF481A4
+
+#define mmTPC5_QM_CQ_PTR_HI_3 0xF481A8
+
+#define mmTPC5_QM_CQ_TSIZE_3 0xF481AC
+
+#define mmTPC5_QM_CQ_CTL_3 0xF481B0
+
+#define mmTPC5_QM_CQ_PTR_LO_4 0xF481B4
+
+#define mmTPC5_QM_CQ_PTR_HI_4 0xF481B8
+
+#define mmTPC5_QM_CQ_TSIZE_4 0xF481BC
+
+#define mmTPC5_QM_CQ_CTL_4 0xF481C0
+
+#define mmTPC5_QM_CQ_PTR_LO_STS_0 0xF481C4
+
+#define mmTPC5_QM_CQ_PTR_LO_STS_1 0xF481C8
+
+#define mmTPC5_QM_CQ_PTR_LO_STS_2 0xF481CC
+
+#define mmTPC5_QM_CQ_PTR_LO_STS_3 0xF481D0
+
+#define mmTPC5_QM_CQ_PTR_LO_STS_4 0xF481D4
+
+#define mmTPC5_QM_CQ_PTR_HI_STS_0 0xF481D8
+
+#define mmTPC5_QM_CQ_PTR_HI_STS_1 0xF481DC
+
+#define mmTPC5_QM_CQ_PTR_HI_STS_2 0xF481E0
+
+#define mmTPC5_QM_CQ_PTR_HI_STS_3 0xF481E4
+
+#define mmTPC5_QM_CQ_PTR_HI_STS_4 0xF481E8
+
+#define mmTPC5_QM_CQ_TSIZE_STS_0 0xF481EC
+
+#define mmTPC5_QM_CQ_TSIZE_STS_1 0xF481F0
+
+#define mmTPC5_QM_CQ_TSIZE_STS_2 0xF481F4
+
+#define mmTPC5_QM_CQ_TSIZE_STS_3 0xF481F8
+
+#define mmTPC5_QM_CQ_TSIZE_STS_4 0xF481FC
+
+#define mmTPC5_QM_CQ_CTL_STS_0 0xF48200
+
+#define mmTPC5_QM_CQ_CTL_STS_1 0xF48204
+
+#define mmTPC5_QM_CQ_CTL_STS_2 0xF48208
+
+#define mmTPC5_QM_CQ_CTL_STS_3 0xF4820C
+
+#define mmTPC5_QM_CQ_CTL_STS_4 0xF48210
+
+#define mmTPC5_QM_CQ_IFIFO_CNT_0 0xF48214
+
+#define mmTPC5_QM_CQ_IFIFO_CNT_1 0xF48218
+
+#define mmTPC5_QM_CQ_IFIFO_CNT_2 0xF4821C
+
+#define mmTPC5_QM_CQ_IFIFO_CNT_3 0xF48220
+
+#define mmTPC5_QM_CQ_IFIFO_CNT_4 0xF48224
+
+#define mmTPC5_QM_CP_MSG_BASE0_ADDR_LO_0 0xF48228
+
+#define mmTPC5_QM_CP_MSG_BASE0_ADDR_LO_1 0xF4822C
+
+#define mmTPC5_QM_CP_MSG_BASE0_ADDR_LO_2 0xF48230
+
+#define mmTPC5_QM_CP_MSG_BASE0_ADDR_LO_3 0xF48234
+
+#define mmTPC5_QM_CP_MSG_BASE0_ADDR_LO_4 0xF48238
+
+#define mmTPC5_QM_CP_MSG_BASE0_ADDR_HI_0 0xF4823C
+
+#define mmTPC5_QM_CP_MSG_BASE0_ADDR_HI_1 0xF48240
+
+#define mmTPC5_QM_CP_MSG_BASE0_ADDR_HI_2 0xF48244
+
+#define mmTPC5_QM_CP_MSG_BASE0_ADDR_HI_3 0xF48248
+
+#define mmTPC5_QM_CP_MSG_BASE0_ADDR_HI_4 0xF4824C
+
+#define mmTPC5_QM_CP_MSG_BASE1_ADDR_LO_0 0xF48250
+
+#define mmTPC5_QM_CP_MSG_BASE1_ADDR_LO_1 0xF48254
+
+#define mmTPC5_QM_CP_MSG_BASE1_ADDR_LO_2 0xF48258
+
+#define mmTPC5_QM_CP_MSG_BASE1_ADDR_LO_3 0xF4825C
+
+#define mmTPC5_QM_CP_MSG_BASE1_ADDR_LO_4 0xF48260
+
+#define mmTPC5_QM_CP_MSG_BASE1_ADDR_HI_0 0xF48264
+
+#define mmTPC5_QM_CP_MSG_BASE1_ADDR_HI_1 0xF48268
+
+#define mmTPC5_QM_CP_MSG_BASE1_ADDR_HI_2 0xF4826C
+
+#define mmTPC5_QM_CP_MSG_BASE1_ADDR_HI_3 0xF48270
+
+#define mmTPC5_QM_CP_MSG_BASE1_ADDR_HI_4 0xF48274
+
+#define mmTPC5_QM_CP_MSG_BASE2_ADDR_LO_0 0xF48278
+
+#define mmTPC5_QM_CP_MSG_BASE2_ADDR_LO_1 0xF4827C
+
+#define mmTPC5_QM_CP_MSG_BASE2_ADDR_LO_2 0xF48280
+
+#define mmTPC5_QM_CP_MSG_BASE2_ADDR_LO_3 0xF48284
+
+#define mmTPC5_QM_CP_MSG_BASE2_ADDR_LO_4 0xF48288
+
+#define mmTPC5_QM_CP_MSG_BASE2_ADDR_HI_0 0xF4828C
+
+#define mmTPC5_QM_CP_MSG_BASE2_ADDR_HI_1 0xF48290
+
+#define mmTPC5_QM_CP_MSG_BASE2_ADDR_HI_2 0xF48294
+
+#define mmTPC5_QM_CP_MSG_BASE2_ADDR_HI_3 0xF48298
+
+#define mmTPC5_QM_CP_MSG_BASE2_ADDR_HI_4 0xF4829C
+
+#define mmTPC5_QM_CP_MSG_BASE3_ADDR_LO_0 0xF482A0
+
+#define mmTPC5_QM_CP_MSG_BASE3_ADDR_LO_1 0xF482A4
+
+#define mmTPC5_QM_CP_MSG_BASE3_ADDR_LO_2 0xF482A8
+
+#define mmTPC5_QM_CP_MSG_BASE3_ADDR_LO_3 0xF482AC
+
+#define mmTPC5_QM_CP_MSG_BASE3_ADDR_LO_4 0xF482B0
+
+#define mmTPC5_QM_CP_MSG_BASE3_ADDR_HI_0 0xF482B4
+
+#define mmTPC5_QM_CP_MSG_BASE3_ADDR_HI_1 0xF482B8
+
+#define mmTPC5_QM_CP_MSG_BASE3_ADDR_HI_2 0xF482BC
+
+#define mmTPC5_QM_CP_MSG_BASE3_ADDR_HI_3 0xF482C0
+
+#define mmTPC5_QM_CP_MSG_BASE3_ADDR_HI_4 0xF482C4
+
+#define mmTPC5_QM_CP_LDMA_TSIZE_OFFSET_0 0xF482C8
+
+#define mmTPC5_QM_CP_LDMA_TSIZE_OFFSET_1 0xF482CC
+
+#define mmTPC5_QM_CP_LDMA_TSIZE_OFFSET_2 0xF482D0
+
+#define mmTPC5_QM_CP_LDMA_TSIZE_OFFSET_3 0xF482D4
+
+#define mmTPC5_QM_CP_LDMA_TSIZE_OFFSET_4 0xF482D8
+
+#define mmTPC5_QM_CP_LDMA_SRC_BASE_LO_OFFSET_0 0xF482E0
+
+#define mmTPC5_QM_CP_LDMA_SRC_BASE_LO_OFFSET_1 0xF482E4
+
+#define mmTPC5_QM_CP_LDMA_SRC_BASE_LO_OFFSET_2 0xF482E8
+
+#define mmTPC5_QM_CP_LDMA_SRC_BASE_LO_OFFSET_3 0xF482EC
+
+#define mmTPC5_QM_CP_LDMA_SRC_BASE_LO_OFFSET_4 0xF482F0
+
+#define mmTPC5_QM_CP_LDMA_DST_BASE_LO_OFFSET_0 0xF482F4
+
+#define mmTPC5_QM_CP_LDMA_DST_BASE_LO_OFFSET_1 0xF482F8
+
+#define mmTPC5_QM_CP_LDMA_DST_BASE_LO_OFFSET_2 0xF482FC
+
+#define mmTPC5_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 0xF48300
+
+#define mmTPC5_QM_CP_LDMA_DST_BASE_LO_OFFSET_4 0xF48304
+
+#define mmTPC5_QM_CP_FENCE0_RDATA_0 0xF48308
+
+#define mmTPC5_QM_CP_FENCE0_RDATA_1 0xF4830C
+
+#define mmTPC5_QM_CP_FENCE0_RDATA_2 0xF48310
+
+#define mmTPC5_QM_CP_FENCE0_RDATA_3 0xF48314
+
+#define mmTPC5_QM_CP_FENCE0_RDATA_4 0xF48318
+
+#define mmTPC5_QM_CP_FENCE1_RDATA_0 0xF4831C
+
+#define mmTPC5_QM_CP_FENCE1_RDATA_1 0xF48320
+
+#define mmTPC5_QM_CP_FENCE1_RDATA_2 0xF48324
+
+#define mmTPC5_QM_CP_FENCE1_RDATA_3 0xF48328
+
+#define mmTPC5_QM_CP_FENCE1_RDATA_4 0xF4832C
+
+#define mmTPC5_QM_CP_FENCE2_RDATA_0 0xF48330
+
+#define mmTPC5_QM_CP_FENCE2_RDATA_1 0xF48334
+
+#define mmTPC5_QM_CP_FENCE2_RDATA_2 0xF48338
+
+#define mmTPC5_QM_CP_FENCE2_RDATA_3 0xF4833C
+
+#define mmTPC5_QM_CP_FENCE2_RDATA_4 0xF48340
+
+#define mmTPC5_QM_CP_FENCE3_RDATA_0 0xF48344
+
+#define mmTPC5_QM_CP_FENCE3_RDATA_1 0xF48348
+
+#define mmTPC5_QM_CP_FENCE3_RDATA_2 0xF4834C
+
+#define mmTPC5_QM_CP_FENCE3_RDATA_3 0xF48350
+
+#define mmTPC5_QM_CP_FENCE3_RDATA_4 0xF48354
+
+#define mmTPC5_QM_CP_FENCE0_CNT_0 0xF48358
+
+#define mmTPC5_QM_CP_FENCE0_CNT_1 0xF4835C
+
+#define mmTPC5_QM_CP_FENCE0_CNT_2 0xF48360
+
+#define mmTPC5_QM_CP_FENCE0_CNT_3 0xF48364
+
+#define mmTPC5_QM_CP_FENCE0_CNT_4 0xF48368
+
+#define mmTPC5_QM_CP_FENCE1_CNT_0 0xF4836C
+
+#define mmTPC5_QM_CP_FENCE1_CNT_1 0xF48370
+
+#define mmTPC5_QM_CP_FENCE1_CNT_2 0xF48374
+
+#define mmTPC5_QM_CP_FENCE1_CNT_3 0xF48378
+
+#define mmTPC5_QM_CP_FENCE1_CNT_4 0xF4837C
+
+#define mmTPC5_QM_CP_FENCE2_CNT_0 0xF48380
+
+#define mmTPC5_QM_CP_FENCE2_CNT_1 0xF48384
+
+#define mmTPC5_QM_CP_FENCE2_CNT_2 0xF48388
+
+#define mmTPC5_QM_CP_FENCE2_CNT_3 0xF4838C
+
+#define mmTPC5_QM_CP_FENCE2_CNT_4 0xF48390
+
+#define mmTPC5_QM_CP_FENCE3_CNT_0 0xF48394
+
+#define mmTPC5_QM_CP_FENCE3_CNT_1 0xF48398
+
+#define mmTPC5_QM_CP_FENCE3_CNT_2 0xF4839C
+
+#define mmTPC5_QM_CP_FENCE3_CNT_3 0xF483A0
+
+#define mmTPC5_QM_CP_FENCE3_CNT_4 0xF483A4
+
+#define mmTPC5_QM_CP_STS_0 0xF483A8
+
+#define mmTPC5_QM_CP_STS_1 0xF483AC
+
+#define mmTPC5_QM_CP_STS_2 0xF483B0
+
+#define mmTPC5_QM_CP_STS_3 0xF483B4
+
+#define mmTPC5_QM_CP_STS_4 0xF483B8
+
+#define mmTPC5_QM_CP_CURRENT_INST_LO_0 0xF483BC
+
+#define mmTPC5_QM_CP_CURRENT_INST_LO_1 0xF483C0
+
+#define mmTPC5_QM_CP_CURRENT_INST_LO_2 0xF483C4
+
+#define mmTPC5_QM_CP_CURRENT_INST_LO_3 0xF483C8
+
+#define mmTPC5_QM_CP_CURRENT_INST_LO_4 0xF483CC
+
+#define mmTPC5_QM_CP_CURRENT_INST_HI_0 0xF483D0
+
+#define mmTPC5_QM_CP_CURRENT_INST_HI_1 0xF483D4
+
+#define mmTPC5_QM_CP_CURRENT_INST_HI_2 0xF483D8
+
+#define mmTPC5_QM_CP_CURRENT_INST_HI_3 0xF483DC
+
+#define mmTPC5_QM_CP_CURRENT_INST_HI_4 0xF483E0
+
+#define mmTPC5_QM_CP_BARRIER_CFG_0 0xF483F4
+
+#define mmTPC5_QM_CP_BARRIER_CFG_1 0xF483F8
+
+#define mmTPC5_QM_CP_BARRIER_CFG_2 0xF483FC
+
+#define mmTPC5_QM_CP_BARRIER_CFG_3 0xF48400
+
+#define mmTPC5_QM_CP_BARRIER_CFG_4 0xF48404
+
+#define mmTPC5_QM_CP_DBG_0_0 0xF48408
+
+#define mmTPC5_QM_CP_DBG_0_1 0xF4840C
+
+#define mmTPC5_QM_CP_DBG_0_2 0xF48410
+
+#define mmTPC5_QM_CP_DBG_0_3 0xF48414
+
+#define mmTPC5_QM_CP_DBG_0_4 0xF48418
+
+#define mmTPC5_QM_CP_ARUSER_31_11_0 0xF4841C
+
+#define mmTPC5_QM_CP_ARUSER_31_11_1 0xF48420
+
+#define mmTPC5_QM_CP_ARUSER_31_11_2 0xF48424
+
+#define mmTPC5_QM_CP_ARUSER_31_11_3 0xF48428
+
+#define mmTPC5_QM_CP_ARUSER_31_11_4 0xF4842C
+
+#define mmTPC5_QM_CP_AWUSER_31_11_0 0xF48430
+
+#define mmTPC5_QM_CP_AWUSER_31_11_1 0xF48434
+
+#define mmTPC5_QM_CP_AWUSER_31_11_2 0xF48438
+
+#define mmTPC5_QM_CP_AWUSER_31_11_3 0xF4843C
+
+#define mmTPC5_QM_CP_AWUSER_31_11_4 0xF48440
+
+#define mmTPC5_QM_ARB_CFG_0 0xF48A00
+
+#define mmTPC5_QM_ARB_CHOISE_Q_PUSH 0xF48A04
+
+#define mmTPC5_QM_ARB_WRR_WEIGHT_0 0xF48A08
+
+#define mmTPC5_QM_ARB_WRR_WEIGHT_1 0xF48A0C
+
+#define mmTPC5_QM_ARB_WRR_WEIGHT_2 0xF48A10
+
+#define mmTPC5_QM_ARB_WRR_WEIGHT_3 0xF48A14
+
+#define mmTPC5_QM_ARB_CFG_1 0xF48A18
+
+#define mmTPC5_QM_ARB_MST_AVAIL_CRED_0 0xF48A20
+
+#define mmTPC5_QM_ARB_MST_AVAIL_CRED_1 0xF48A24
+
+#define mmTPC5_QM_ARB_MST_AVAIL_CRED_2 0xF48A28
+
+#define mmTPC5_QM_ARB_MST_AVAIL_CRED_3 0xF48A2C
+
+#define mmTPC5_QM_ARB_MST_AVAIL_CRED_4 0xF48A30
+
+#define mmTPC5_QM_ARB_MST_AVAIL_CRED_5 0xF48A34
+
+#define mmTPC5_QM_ARB_MST_AVAIL_CRED_6 0xF48A38
+
+#define mmTPC5_QM_ARB_MST_AVAIL_CRED_7 0xF48A3C
+
+#define mmTPC5_QM_ARB_MST_AVAIL_CRED_8 0xF48A40
+
+#define mmTPC5_QM_ARB_MST_AVAIL_CRED_9 0xF48A44
+
+#define mmTPC5_QM_ARB_MST_AVAIL_CRED_10 0xF48A48
+
+#define mmTPC5_QM_ARB_MST_AVAIL_CRED_11 0xF48A4C
+
+#define mmTPC5_QM_ARB_MST_AVAIL_CRED_12 0xF48A50
+
+#define mmTPC5_QM_ARB_MST_AVAIL_CRED_13 0xF48A54
+
+#define mmTPC5_QM_ARB_MST_AVAIL_CRED_14 0xF48A58
+
+#define mmTPC5_QM_ARB_MST_AVAIL_CRED_15 0xF48A5C
+
+#define mmTPC5_QM_ARB_MST_AVAIL_CRED_16 0xF48A60
+
+#define mmTPC5_QM_ARB_MST_AVAIL_CRED_17 0xF48A64
+
+#define mmTPC5_QM_ARB_MST_AVAIL_CRED_18 0xF48A68
+
+#define mmTPC5_QM_ARB_MST_AVAIL_CRED_19 0xF48A6C
+
+#define mmTPC5_QM_ARB_MST_AVAIL_CRED_20 0xF48A70
+
+#define mmTPC5_QM_ARB_MST_AVAIL_CRED_21 0xF48A74
+
+#define mmTPC5_QM_ARB_MST_AVAIL_CRED_22 0xF48A78
+
+#define mmTPC5_QM_ARB_MST_AVAIL_CRED_23 0xF48A7C
+
+#define mmTPC5_QM_ARB_MST_AVAIL_CRED_24 0xF48A80
+
+#define mmTPC5_QM_ARB_MST_AVAIL_CRED_25 0xF48A84
+
+#define mmTPC5_QM_ARB_MST_AVAIL_CRED_26 0xF48A88
+
+#define mmTPC5_QM_ARB_MST_AVAIL_CRED_27 0xF48A8C
+
+#define mmTPC5_QM_ARB_MST_AVAIL_CRED_28 0xF48A90
+
+#define mmTPC5_QM_ARB_MST_AVAIL_CRED_29 0xF48A94
+
+#define mmTPC5_QM_ARB_MST_AVAIL_CRED_30 0xF48A98
+
+#define mmTPC5_QM_ARB_MST_AVAIL_CRED_31 0xF48A9C
+
+#define mmTPC5_QM_ARB_MST_CRED_INC 0xF48AA0
+
+#define mmTPC5_QM_ARB_MST_CHOISE_PUSH_OFST_0 0xF48AA4
+
+#define mmTPC5_QM_ARB_MST_CHOISE_PUSH_OFST_1 0xF48AA8
+
+#define mmTPC5_QM_ARB_MST_CHOISE_PUSH_OFST_2 0xF48AAC
+
+#define mmTPC5_QM_ARB_MST_CHOISE_PUSH_OFST_3 0xF48AB0
+
+#define mmTPC5_QM_ARB_MST_CHOISE_PUSH_OFST_4 0xF48AB4
+
+#define mmTPC5_QM_ARB_MST_CHOISE_PUSH_OFST_5 0xF48AB8
+
+#define mmTPC5_QM_ARB_MST_CHOISE_PUSH_OFST_6 0xF48ABC
+
+#define mmTPC5_QM_ARB_MST_CHOISE_PUSH_OFST_7 0xF48AC0
+
+#define mmTPC5_QM_ARB_MST_CHOISE_PUSH_OFST_8 0xF48AC4
+
+#define mmTPC5_QM_ARB_MST_CHOISE_PUSH_OFST_9 0xF48AC8
+
+#define mmTPC5_QM_ARB_MST_CHOISE_PUSH_OFST_10 0xF48ACC
+
+#define mmTPC5_QM_ARB_MST_CHOISE_PUSH_OFST_11 0xF48AD0
+
+#define mmTPC5_QM_ARB_MST_CHOISE_PUSH_OFST_12 0xF48AD4
+
+#define mmTPC5_QM_ARB_MST_CHOISE_PUSH_OFST_13 0xF48AD8
+
+#define mmTPC5_QM_ARB_MST_CHOISE_PUSH_OFST_14 0xF48ADC
+
+#define mmTPC5_QM_ARB_MST_CHOISE_PUSH_OFST_15 0xF48AE0
+
+#define mmTPC5_QM_ARB_MST_CHOISE_PUSH_OFST_16 0xF48AE4
+
+#define mmTPC5_QM_ARB_MST_CHOISE_PUSH_OFST_17 0xF48AE8
+
+#define mmTPC5_QM_ARB_MST_CHOISE_PUSH_OFST_18 0xF48AEC
+
+#define mmTPC5_QM_ARB_MST_CHOISE_PUSH_OFST_19 0xF48AF0
+
+#define mmTPC5_QM_ARB_MST_CHOISE_PUSH_OFST_20 0xF48AF4
+
+#define mmTPC5_QM_ARB_MST_CHOISE_PUSH_OFST_21 0xF48AF8
+
+#define mmTPC5_QM_ARB_MST_CHOISE_PUSH_OFST_22 0xF48AFC
+
+#define mmTPC5_QM_ARB_MST_CHOISE_PUSH_OFST_23 0xF48B00
+
+#define mmTPC5_QM_ARB_MST_CHOISE_PUSH_OFST_24 0xF48B04
+
+#define mmTPC5_QM_ARB_MST_CHOISE_PUSH_OFST_25 0xF48B08
+
+#define mmTPC5_QM_ARB_MST_CHOISE_PUSH_OFST_26 0xF48B0C
+
+#define mmTPC5_QM_ARB_MST_CHOISE_PUSH_OFST_27 0xF48B10
+
+#define mmTPC5_QM_ARB_MST_CHOISE_PUSH_OFST_28 0xF48B14
+
+#define mmTPC5_QM_ARB_MST_CHOISE_PUSH_OFST_29 0xF48B18
+
+#define mmTPC5_QM_ARB_MST_CHOISE_PUSH_OFST_30 0xF48B1C
+
+#define mmTPC5_QM_ARB_MST_CHOISE_PUSH_OFST_31 0xF48B20
+
+#define mmTPC5_QM_ARB_SLV_MASTER_INC_CRED_OFST 0xF48B28
+
+#define mmTPC5_QM_ARB_MST_SLAVE_EN 0xF48B2C
+
+#define mmTPC5_QM_ARB_MST_QUIET_PER 0xF48B34
+
+#define mmTPC5_QM_ARB_SLV_CHOISE_WDT 0xF48B38
+
+#define mmTPC5_QM_ARB_SLV_ID 0xF48B3C
+
+#define mmTPC5_QM_ARB_MSG_MAX_INFLIGHT 0xF48B44
+
+#define mmTPC5_QM_ARB_MSG_AWUSER_31_11 0xF48B48
+
+#define mmTPC5_QM_ARB_MSG_AWUSER_SEC_PROP 0xF48B4C
+
+#define mmTPC5_QM_ARB_MSG_AWUSER_NON_SEC_PROP 0xF48B50
+
+#define mmTPC5_QM_ARB_BASE_LO 0xF48B54
+
+#define mmTPC5_QM_ARB_BASE_HI 0xF48B58
+
+#define mmTPC5_QM_ARB_STATE_STS 0xF48B80
+
+#define mmTPC5_QM_ARB_CHOISE_FULLNESS_STS 0xF48B84
+
+#define mmTPC5_QM_ARB_MSG_STS 0xF48B88
+
+#define mmTPC5_QM_ARB_SLV_CHOISE_Q_HEAD 0xF48B8C
+
+#define mmTPC5_QM_ARB_ERR_CAUSE 0xF48B9C
+
+#define mmTPC5_QM_ARB_ERR_MSG_EN 0xF48BA0
+
+#define mmTPC5_QM_ARB_ERR_STS_DRP 0xF48BA8
+
+#define mmTPC5_QM_ARB_MST_CRED_STS_0 0xF48BB0
+
+#define mmTPC5_QM_ARB_MST_CRED_STS_1 0xF48BB4
+
+#define mmTPC5_QM_ARB_MST_CRED_STS_2 0xF48BB8
+
+#define mmTPC5_QM_ARB_MST_CRED_STS_3 0xF48BBC
+
+#define mmTPC5_QM_ARB_MST_CRED_STS_4 0xF48BC0
+
+#define mmTPC5_QM_ARB_MST_CRED_STS_5 0xF48BC4
+
+#define mmTPC5_QM_ARB_MST_CRED_STS_6 0xF48BC8
+
+#define mmTPC5_QM_ARB_MST_CRED_STS_7 0xF48BCC
+
+#define mmTPC5_QM_ARB_MST_CRED_STS_8 0xF48BD0
+
+#define mmTPC5_QM_ARB_MST_CRED_STS_9 0xF48BD4
+
+#define mmTPC5_QM_ARB_MST_CRED_STS_10 0xF48BD8
+
+#define mmTPC5_QM_ARB_MST_CRED_STS_11 0xF48BDC
+
+#define mmTPC5_QM_ARB_MST_CRED_STS_12 0xF48BE0
+
+#define mmTPC5_QM_ARB_MST_CRED_STS_13 0xF48BE4
+
+#define mmTPC5_QM_ARB_MST_CRED_STS_14 0xF48BE8
+
+#define mmTPC5_QM_ARB_MST_CRED_STS_15 0xF48BEC
+
+#define mmTPC5_QM_ARB_MST_CRED_STS_16 0xF48BF0
+
+#define mmTPC5_QM_ARB_MST_CRED_STS_17 0xF48BF4
+
+#define mmTPC5_QM_ARB_MST_CRED_STS_18 0xF48BF8
+
+#define mmTPC5_QM_ARB_MST_CRED_STS_19 0xF48BFC
+
+#define mmTPC5_QM_ARB_MST_CRED_STS_20 0xF48C00
+
+#define mmTPC5_QM_ARB_MST_CRED_STS_21 0xF48C04
+
+#define mmTPC5_QM_ARB_MST_CRED_STS_22 0xF48C08
+
+#define mmTPC5_QM_ARB_MST_CRED_STS_23 0xF48C0C
+
+#define mmTPC5_QM_ARB_MST_CRED_STS_24 0xF48C10
+
+#define mmTPC5_QM_ARB_MST_CRED_STS_25 0xF48C14
+
+#define mmTPC5_QM_ARB_MST_CRED_STS_26 0xF48C18
+
+#define mmTPC5_QM_ARB_MST_CRED_STS_27 0xF48C1C
+
+#define mmTPC5_QM_ARB_MST_CRED_STS_28 0xF48C20
+
+#define mmTPC5_QM_ARB_MST_CRED_STS_29 0xF48C24
+
+#define mmTPC5_QM_ARB_MST_CRED_STS_30 0xF48C28
+
+#define mmTPC5_QM_ARB_MST_CRED_STS_31 0xF48C2C
+
+#define mmTPC5_QM_CGM_CFG 0xF48C70
+
+#define mmTPC5_QM_CGM_STS 0xF48C74
+
+#define mmTPC5_QM_CGM_CFG1 0xF48C78
+
+#define mmTPC5_QM_LOCAL_RANGE_BASE 0xF48C80
+
+#define mmTPC5_QM_LOCAL_RANGE_SIZE 0xF48C84
+
+#define mmTPC5_QM_CSMR_STRICT_PRIO_CFG 0xF48C90
+
+#define mmTPC5_QM_HBW_RD_RATE_LIM_CFG_1 0xF48C94
+
+#define mmTPC5_QM_LBW_WR_RATE_LIM_CFG_0 0xF48C98
+
+#define mmTPC5_QM_LBW_WR_RATE_LIM_CFG_1 0xF48C9C
+
+#define mmTPC5_QM_HBW_RD_RATE_LIM_CFG_0 0xF48CA0
+
+#define mmTPC5_QM_GLBL_AXCACHE 0xF48CA4
+
+#define mmTPC5_QM_IND_GW_APB_CFG 0xF48CB0
+
+#define mmTPC5_QM_IND_GW_APB_WDATA 0xF48CB4
+
+#define mmTPC5_QM_IND_GW_APB_RDATA 0xF48CB8
+
+#define mmTPC5_QM_IND_GW_APB_STATUS 0xF48CBC
+
+#define mmTPC5_QM_GLBL_ERR_ADDR_LO 0xF48CD0
+
+#define mmTPC5_QM_GLBL_ERR_ADDR_HI 0xF48CD4
+
+#define mmTPC5_QM_GLBL_ERR_WDATA 0xF48CD8
+
+#define mmTPC5_QM_GLBL_MEM_INIT_BUSY 0xF48D00
+
+#endif /* ASIC_REG_TPC5_QM_REGS_H_ */
diff --git a/drivers/accel/habanalabs/include/gaudi/asic_reg/tpc6_cfg_regs.h b/drivers/accel/habanalabs/include/gaudi/asic_reg/tpc6_cfg_regs.h
new file mode 100644
index 0000000000..eb251e7281
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi/asic_reg/tpc6_cfg_regs.h
@@ -0,0 +1,1226 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2016-2018 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ ** DO NOT EDIT BELOW **
+ ************************************/
+
+#ifndef ASIC_REG_TPC6_CFG_REGS_H_
+#define ASIC_REG_TPC6_CFG_REGS_H_
+
+/*
+ *****************************************
+ * TPC6_CFG (Prototype: TPC)
+ *****************************************
+ */
+
+#define mmTPC6_CFG_KERNEL_TENSOR_0_BASE_ADDR_LOW 0xF86400
+
+#define mmTPC6_CFG_KERNEL_TENSOR_0_BASE_ADDR_HIGH 0xF86404
+
+#define mmTPC6_CFG_KERNEL_TENSOR_0_PADDING_VALUE 0xF86408
+
+#define mmTPC6_CFG_KERNEL_TENSOR_0_TENSOR_CONFIG 0xF8640C
+
+#define mmTPC6_CFG_KERNEL_TENSOR_0_DIM_0_SIZE 0xF86410
+
+#define mmTPC6_CFG_KERNEL_TENSOR_0_DIM_0_STRIDE 0xF86414
+
+#define mmTPC6_CFG_KERNEL_TENSOR_0_DIM_1_SIZE 0xF86418
+
+#define mmTPC6_CFG_KERNEL_TENSOR_0_DIM_1_STRIDE 0xF8641C
+
+#define mmTPC6_CFG_KERNEL_TENSOR_0_DIM_2_SIZE 0xF86420
+
+#define mmTPC6_CFG_KERNEL_TENSOR_0_DIM_2_STRIDE 0xF86424
+
+#define mmTPC6_CFG_KERNEL_TENSOR_0_DIM_3_SIZE 0xF86428
+
+#define mmTPC6_CFG_KERNEL_TENSOR_0_DIM_3_STRIDE 0xF8642C
+
+#define mmTPC6_CFG_KERNEL_TENSOR_0_DIM_4_SIZE 0xF86430
+
+#define mmTPC6_CFG_KERNEL_TENSOR_0_DIM_4_STRIDE 0xF86434
+
+#define mmTPC6_CFG_KERNEL_TENSOR_1_BASE_ADDR_LOW 0xF86438
+
+#define mmTPC6_CFG_KERNEL_TENSOR_1_BASE_ADDR_HIGH 0xF8643C
+
+#define mmTPC6_CFG_KERNEL_TENSOR_1_PADDING_VALUE 0xF86440
+
+#define mmTPC6_CFG_KERNEL_TENSOR_1_TENSOR_CONFIG 0xF86444
+
+#define mmTPC6_CFG_KERNEL_TENSOR_1_DIM_0_SIZE 0xF86448
+
+#define mmTPC6_CFG_KERNEL_TENSOR_1_DIM_0_STRIDE 0xF8644C
+
+#define mmTPC6_CFG_KERNEL_TENSOR_1_DIM_1_SIZE 0xF86450
+
+#define mmTPC6_CFG_KERNEL_TENSOR_1_DIM_1_STRIDE 0xF86454
+
+#define mmTPC6_CFG_KERNEL_TENSOR_1_DIM_2_SIZE 0xF86458
+
+#define mmTPC6_CFG_KERNEL_TENSOR_1_DIM_2_STRIDE 0xF8645C
+
+#define mmTPC6_CFG_KERNEL_TENSOR_1_DIM_3_SIZE 0xF86460
+
+#define mmTPC6_CFG_KERNEL_TENSOR_1_DIM_3_STRIDE 0xF86464
+
+#define mmTPC6_CFG_KERNEL_TENSOR_1_DIM_4_SIZE 0xF86468
+
+#define mmTPC6_CFG_KERNEL_TENSOR_1_DIM_4_STRIDE 0xF8646C
+
+#define mmTPC6_CFG_KERNEL_TENSOR_2_BASE_ADDR_LOW 0xF86470
+
+#define mmTPC6_CFG_KERNEL_TENSOR_2_BASE_ADDR_HIGH 0xF86474
+
+#define mmTPC6_CFG_KERNEL_TENSOR_2_PADDING_VALUE 0xF86478
+
+#define mmTPC6_CFG_KERNEL_TENSOR_2_TENSOR_CONFIG 0xF8647C
+
+#define mmTPC6_CFG_KERNEL_TENSOR_2_DIM_0_SIZE 0xF86480
+
+#define mmTPC6_CFG_KERNEL_TENSOR_2_DIM_0_STRIDE 0xF86484
+
+#define mmTPC6_CFG_KERNEL_TENSOR_2_DIM_1_SIZE 0xF86488
+
+#define mmTPC6_CFG_KERNEL_TENSOR_2_DIM_1_STRIDE 0xF8648C
+
+#define mmTPC6_CFG_KERNEL_TENSOR_2_DIM_2_SIZE 0xF86490
+
+#define mmTPC6_CFG_KERNEL_TENSOR_2_DIM_2_STRIDE 0xF86494
+
+#define mmTPC6_CFG_KERNEL_TENSOR_2_DIM_3_SIZE 0xF86498
+
+#define mmTPC6_CFG_KERNEL_TENSOR_2_DIM_3_STRIDE 0xF8649C
+
+#define mmTPC6_CFG_KERNEL_TENSOR_2_DIM_4_SIZE 0xF864A0
+
+#define mmTPC6_CFG_KERNEL_TENSOR_2_DIM_4_STRIDE 0xF864A4
+
+#define mmTPC6_CFG_KERNEL_TENSOR_3_BASE_ADDR_LOW 0xF864A8
+
+#define mmTPC6_CFG_KERNEL_TENSOR_3_BASE_ADDR_HIGH 0xF864AC
+
+#define mmTPC6_CFG_KERNEL_TENSOR_3_PADDING_VALUE 0xF864B0
+
+#define mmTPC6_CFG_KERNEL_TENSOR_3_TENSOR_CONFIG 0xF864B4
+
+#define mmTPC6_CFG_KERNEL_TENSOR_3_DIM_0_SIZE 0xF864B8
+
+#define mmTPC6_CFG_KERNEL_TENSOR_3_DIM_0_STRIDE 0xF864BC
+
+#define mmTPC6_CFG_KERNEL_TENSOR_3_DIM_1_SIZE 0xF864C0
+
+#define mmTPC6_CFG_KERNEL_TENSOR_3_DIM_1_STRIDE 0xF864C4
+
+#define mmTPC6_CFG_KERNEL_TENSOR_3_DIM_2_SIZE 0xF864C8
+
+#define mmTPC6_CFG_KERNEL_TENSOR_3_DIM_2_STRIDE 0xF864CC
+
+#define mmTPC6_CFG_KERNEL_TENSOR_3_DIM_3_SIZE 0xF864D0
+
+#define mmTPC6_CFG_KERNEL_TENSOR_3_DIM_3_STRIDE 0xF864D4
+
+#define mmTPC6_CFG_KERNEL_TENSOR_3_DIM_4_SIZE 0xF864D8
+
+#define mmTPC6_CFG_KERNEL_TENSOR_3_DIM_4_STRIDE 0xF864DC
+
+#define mmTPC6_CFG_KERNEL_TENSOR_4_BASE_ADDR_LOW 0xF864E0
+
+#define mmTPC6_CFG_KERNEL_TENSOR_4_BASE_ADDR_HIGH 0xF864E4
+
+#define mmTPC6_CFG_KERNEL_TENSOR_4_PADDING_VALUE 0xF864E8
+
+#define mmTPC6_CFG_KERNEL_TENSOR_4_TENSOR_CONFIG 0xF864EC
+
+#define mmTPC6_CFG_KERNEL_TENSOR_4_DIM_0_SIZE 0xF864F0
+
+#define mmTPC6_CFG_KERNEL_TENSOR_4_DIM_0_STRIDE 0xF864F4
+
+#define mmTPC6_CFG_KERNEL_TENSOR_4_DIM_1_SIZE 0xF864F8
+
+#define mmTPC6_CFG_KERNEL_TENSOR_4_DIM_1_STRIDE 0xF864FC
+
+#define mmTPC6_CFG_KERNEL_TENSOR_4_DIM_2_SIZE 0xF86500
+
+#define mmTPC6_CFG_KERNEL_TENSOR_4_DIM_2_STRIDE 0xF86504
+
+#define mmTPC6_CFG_KERNEL_TENSOR_4_DIM_3_SIZE 0xF86508
+
+#define mmTPC6_CFG_KERNEL_TENSOR_4_DIM_3_STRIDE 0xF8650C
+
+#define mmTPC6_CFG_KERNEL_TENSOR_4_DIM_4_SIZE 0xF86510
+
+#define mmTPC6_CFG_KERNEL_TENSOR_4_DIM_4_STRIDE 0xF86514
+
+#define mmTPC6_CFG_KERNEL_TENSOR_5_BASE_ADDR_LOW 0xF86518
+
+#define mmTPC6_CFG_KERNEL_TENSOR_5_BASE_ADDR_HIGH 0xF8651C
+
+#define mmTPC6_CFG_KERNEL_TENSOR_5_PADDING_VALUE 0xF86520
+
+#define mmTPC6_CFG_KERNEL_TENSOR_5_TENSOR_CONFIG 0xF86524
+
+#define mmTPC6_CFG_KERNEL_TENSOR_5_DIM_0_SIZE 0xF86528
+
+#define mmTPC6_CFG_KERNEL_TENSOR_5_DIM_0_STRIDE 0xF8652C
+
+#define mmTPC6_CFG_KERNEL_TENSOR_5_DIM_1_SIZE 0xF86530
+
+#define mmTPC6_CFG_KERNEL_TENSOR_5_DIM_1_STRIDE 0xF86534
+
+#define mmTPC6_CFG_KERNEL_TENSOR_5_DIM_2_SIZE 0xF86538
+
+#define mmTPC6_CFG_KERNEL_TENSOR_5_DIM_2_STRIDE 0xF8653C
+
+#define mmTPC6_CFG_KERNEL_TENSOR_5_DIM_3_SIZE 0xF86540
+
+#define mmTPC6_CFG_KERNEL_TENSOR_5_DIM_3_STRIDE 0xF86544
+
+#define mmTPC6_CFG_KERNEL_TENSOR_5_DIM_4_SIZE 0xF86548
+
+#define mmTPC6_CFG_KERNEL_TENSOR_5_DIM_4_STRIDE 0xF8654C
+
+#define mmTPC6_CFG_KERNEL_TENSOR_6_BASE_ADDR_LOW 0xF86550
+
+#define mmTPC6_CFG_KERNEL_TENSOR_6_BASE_ADDR_HIGH 0xF86554
+
+#define mmTPC6_CFG_KERNEL_TENSOR_6_PADDING_VALUE 0xF86558
+
+#define mmTPC6_CFG_KERNEL_TENSOR_6_TENSOR_CONFIG 0xF8655C
+
+#define mmTPC6_CFG_KERNEL_TENSOR_6_DIM_0_SIZE 0xF86560
+
+#define mmTPC6_CFG_KERNEL_TENSOR_6_DIM_0_STRIDE 0xF86564
+
+#define mmTPC6_CFG_KERNEL_TENSOR_6_DIM_1_SIZE 0xF86568
+
+#define mmTPC6_CFG_KERNEL_TENSOR_6_DIM_1_STRIDE 0xF8656C
+
+#define mmTPC6_CFG_KERNEL_TENSOR_6_DIM_2_SIZE 0xF86570
+
+#define mmTPC6_CFG_KERNEL_TENSOR_6_DIM_2_STRIDE 0xF86574
+
+#define mmTPC6_CFG_KERNEL_TENSOR_6_DIM_3_SIZE 0xF86578
+
+#define mmTPC6_CFG_KERNEL_TENSOR_6_DIM_3_STRIDE 0xF8657C
+
+#define mmTPC6_CFG_KERNEL_TENSOR_6_DIM_4_SIZE 0xF86580
+
+#define mmTPC6_CFG_KERNEL_TENSOR_6_DIM_4_STRIDE 0xF86584
+
+#define mmTPC6_CFG_KERNEL_TENSOR_7_BASE_ADDR_LOW 0xF86588
+
+#define mmTPC6_CFG_KERNEL_TENSOR_7_BASE_ADDR_HIGH 0xF8658C
+
+#define mmTPC6_CFG_KERNEL_TENSOR_7_PADDING_VALUE 0xF86590
+
+#define mmTPC6_CFG_KERNEL_TENSOR_7_TENSOR_CONFIG 0xF86594
+
+#define mmTPC6_CFG_KERNEL_TENSOR_7_DIM_0_SIZE 0xF86598
+
+#define mmTPC6_CFG_KERNEL_TENSOR_7_DIM_0_STRIDE 0xF8659C
+
+#define mmTPC6_CFG_KERNEL_TENSOR_7_DIM_1_SIZE 0xF865A0
+
+#define mmTPC6_CFG_KERNEL_TENSOR_7_DIM_1_STRIDE 0xF865A4
+
+#define mmTPC6_CFG_KERNEL_TENSOR_7_DIM_2_SIZE 0xF865A8
+
+#define mmTPC6_CFG_KERNEL_TENSOR_7_DIM_2_STRIDE 0xF865AC
+
+#define mmTPC6_CFG_KERNEL_TENSOR_7_DIM_3_SIZE 0xF865B0
+
+#define mmTPC6_CFG_KERNEL_TENSOR_7_DIM_3_STRIDE 0xF865B4
+
+#define mmTPC6_CFG_KERNEL_TENSOR_7_DIM_4_SIZE 0xF865B8
+
+#define mmTPC6_CFG_KERNEL_TENSOR_7_DIM_4_STRIDE 0xF865BC
+
+#define mmTPC6_CFG_KERNEL_TENSOR_8_BASE_ADDR_LOW 0xF865C0
+
+#define mmTPC6_CFG_KERNEL_TENSOR_8_BASE_ADDR_HIGH 0xF865C4
+
+#define mmTPC6_CFG_KERNEL_TENSOR_8_PADDING_VALUE 0xF865C8
+
+#define mmTPC6_CFG_KERNEL_TENSOR_8_TENSOR_CONFIG 0xF865CC
+
+#define mmTPC6_CFG_KERNEL_TENSOR_8_DIM_0_SIZE 0xF865D0
+
+#define mmTPC6_CFG_KERNEL_TENSOR_8_DIM_0_STRIDE 0xF865D4
+
+#define mmTPC6_CFG_KERNEL_TENSOR_8_DIM_1_SIZE 0xF865D8
+
+#define mmTPC6_CFG_KERNEL_TENSOR_8_DIM_1_STRIDE 0xF865DC
+
+#define mmTPC6_CFG_KERNEL_TENSOR_8_DIM_2_SIZE 0xF865E0
+
+#define mmTPC6_CFG_KERNEL_TENSOR_8_DIM_2_STRIDE 0xF865E4
+
+#define mmTPC6_CFG_KERNEL_TENSOR_8_DIM_3_SIZE 0xF865E8
+
+#define mmTPC6_CFG_KERNEL_TENSOR_8_DIM_3_STRIDE 0xF865EC
+
+#define mmTPC6_CFG_KERNEL_TENSOR_8_DIM_4_SIZE 0xF865F0
+
+#define mmTPC6_CFG_KERNEL_TENSOR_8_DIM_4_STRIDE 0xF865F4
+
+#define mmTPC6_CFG_KERNEL_TENSOR_9_BASE_ADDR_LOW 0xF865F8
+
+#define mmTPC6_CFG_KERNEL_TENSOR_9_BASE_ADDR_HIGH 0xF865FC
+
+#define mmTPC6_CFG_KERNEL_TENSOR_9_PADDING_VALUE 0xF86600
+
+#define mmTPC6_CFG_KERNEL_TENSOR_9_TENSOR_CONFIG 0xF86604
+
+#define mmTPC6_CFG_KERNEL_TENSOR_9_DIM_0_SIZE 0xF86608
+
+#define mmTPC6_CFG_KERNEL_TENSOR_9_DIM_0_STRIDE 0xF8660C
+
+#define mmTPC6_CFG_KERNEL_TENSOR_9_DIM_1_SIZE 0xF86610
+
+#define mmTPC6_CFG_KERNEL_TENSOR_9_DIM_1_STRIDE 0xF86614
+
+#define mmTPC6_CFG_KERNEL_TENSOR_9_DIM_2_SIZE 0xF86618
+
+#define mmTPC6_CFG_KERNEL_TENSOR_9_DIM_2_STRIDE 0xF8661C
+
+#define mmTPC6_CFG_KERNEL_TENSOR_9_DIM_3_SIZE 0xF86620
+
+#define mmTPC6_CFG_KERNEL_TENSOR_9_DIM_3_STRIDE 0xF86624
+
+#define mmTPC6_CFG_KERNEL_TENSOR_9_DIM_4_SIZE 0xF86628
+
+#define mmTPC6_CFG_KERNEL_TENSOR_9_DIM_4_STRIDE 0xF8662C
+
+#define mmTPC6_CFG_KERNEL_TENSOR_10_BASE_ADDR_LOW 0xF86630
+
+#define mmTPC6_CFG_KERNEL_TENSOR_10_BASE_ADDR_HIGH 0xF86634
+
+#define mmTPC6_CFG_KERNEL_TENSOR_10_PADDING_VALUE 0xF86638
+
+#define mmTPC6_CFG_KERNEL_TENSOR_10_TENSOR_CONFIG 0xF8663C
+
+#define mmTPC6_CFG_KERNEL_TENSOR_10_DIM_0_SIZE 0xF86640
+
+#define mmTPC6_CFG_KERNEL_TENSOR_10_DIM_0_STRIDE 0xF86644
+
+#define mmTPC6_CFG_KERNEL_TENSOR_10_DIM_1_SIZE 0xF86648
+
+#define mmTPC6_CFG_KERNEL_TENSOR_10_DIM_1_STRIDE 0xF8664C
+
+#define mmTPC6_CFG_KERNEL_TENSOR_10_DIM_2_SIZE 0xF86650
+
+#define mmTPC6_CFG_KERNEL_TENSOR_10_DIM_2_STRIDE 0xF86654
+
+#define mmTPC6_CFG_KERNEL_TENSOR_10_DIM_3_SIZE 0xF86658
+
+#define mmTPC6_CFG_KERNEL_TENSOR_10_DIM_3_STRIDE 0xF8665C
+
+#define mmTPC6_CFG_KERNEL_TENSOR_10_DIM_4_SIZE 0xF86660
+
+#define mmTPC6_CFG_KERNEL_TENSOR_10_DIM_4_STRIDE 0xF86664
+
+#define mmTPC6_CFG_KERNEL_TENSOR_11_BASE_ADDR_LOW 0xF86668
+
+#define mmTPC6_CFG_KERNEL_TENSOR_11_BASE_ADDR_HIGH 0xF8666C
+
+#define mmTPC6_CFG_KERNEL_TENSOR_11_PADDING_VALUE 0xF86670
+
+#define mmTPC6_CFG_KERNEL_TENSOR_11_TENSOR_CONFIG 0xF86674
+
+#define mmTPC6_CFG_KERNEL_TENSOR_11_DIM_0_SIZE 0xF86678
+
+#define mmTPC6_CFG_KERNEL_TENSOR_11_DIM_0_STRIDE 0xF8667C
+
+#define mmTPC6_CFG_KERNEL_TENSOR_11_DIM_1_SIZE 0xF86680
+
+#define mmTPC6_CFG_KERNEL_TENSOR_11_DIM_1_STRIDE 0xF86684
+
+#define mmTPC6_CFG_KERNEL_TENSOR_11_DIM_2_SIZE 0xF86688
+
+#define mmTPC6_CFG_KERNEL_TENSOR_11_DIM_2_STRIDE 0xF8668C
+
+#define mmTPC6_CFG_KERNEL_TENSOR_11_DIM_3_SIZE 0xF86690
+
+#define mmTPC6_CFG_KERNEL_TENSOR_11_DIM_3_STRIDE 0xF86694
+
+#define mmTPC6_CFG_KERNEL_TENSOR_11_DIM_4_SIZE 0xF86698
+
+#define mmTPC6_CFG_KERNEL_TENSOR_11_DIM_4_STRIDE 0xF8669C
+
+#define mmTPC6_CFG_KERNEL_TENSOR_12_BASE_ADDR_LOW 0xF866A0
+
+#define mmTPC6_CFG_KERNEL_TENSOR_12_BASE_ADDR_HIGH 0xF866A4
+
+#define mmTPC6_CFG_KERNEL_TENSOR_12_PADDING_VALUE 0xF866A8
+
+#define mmTPC6_CFG_KERNEL_TENSOR_12_TENSOR_CONFIG 0xF866AC
+
+#define mmTPC6_CFG_KERNEL_TENSOR_12_DIM_0_SIZE 0xF866B0
+
+#define mmTPC6_CFG_KERNEL_TENSOR_12_DIM_0_STRIDE 0xF866B4
+
+#define mmTPC6_CFG_KERNEL_TENSOR_12_DIM_1_SIZE 0xF866B8
+
+#define mmTPC6_CFG_KERNEL_TENSOR_12_DIM_1_STRIDE 0xF866BC
+
+#define mmTPC6_CFG_KERNEL_TENSOR_12_DIM_2_SIZE 0xF866C0
+
+#define mmTPC6_CFG_KERNEL_TENSOR_12_DIM_2_STRIDE 0xF866C4
+
+#define mmTPC6_CFG_KERNEL_TENSOR_12_DIM_3_SIZE 0xF866C8
+
+#define mmTPC6_CFG_KERNEL_TENSOR_12_DIM_3_STRIDE 0xF866CC
+
+#define mmTPC6_CFG_KERNEL_TENSOR_12_DIM_4_SIZE 0xF866D0
+
+#define mmTPC6_CFG_KERNEL_TENSOR_12_DIM_4_STRIDE 0xF866D4
+
+#define mmTPC6_CFG_KERNEL_TENSOR_13_BASE_ADDR_LOW 0xF866D8
+
+#define mmTPC6_CFG_KERNEL_TENSOR_13_BASE_ADDR_HIGH 0xF866DC
+
+#define mmTPC6_CFG_KERNEL_TENSOR_13_PADDING_VALUE 0xF866E0
+
+#define mmTPC6_CFG_KERNEL_TENSOR_13_TENSOR_CONFIG 0xF866E4
+
+#define mmTPC6_CFG_KERNEL_TENSOR_13_DIM_0_SIZE 0xF866E8
+
+#define mmTPC6_CFG_KERNEL_TENSOR_13_DIM_0_STRIDE 0xF866EC
+
+#define mmTPC6_CFG_KERNEL_TENSOR_13_DIM_1_SIZE 0xF866F0
+
+#define mmTPC6_CFG_KERNEL_TENSOR_13_DIM_1_STRIDE 0xF866F4
+
+#define mmTPC6_CFG_KERNEL_TENSOR_13_DIM_2_SIZE 0xF866F8
+
+#define mmTPC6_CFG_KERNEL_TENSOR_13_DIM_2_STRIDE 0xF866FC
+
+#define mmTPC6_CFG_KERNEL_TENSOR_13_DIM_3_SIZE 0xF86700
+
+#define mmTPC6_CFG_KERNEL_TENSOR_13_DIM_3_STRIDE 0xF86704
+
+#define mmTPC6_CFG_KERNEL_TENSOR_13_DIM_4_SIZE 0xF86708
+
+#define mmTPC6_CFG_KERNEL_TENSOR_13_DIM_4_STRIDE 0xF8670C
+
+#define mmTPC6_CFG_KERNEL_TENSOR_14_BASE_ADDR_LOW 0xF86710
+
+#define mmTPC6_CFG_KERNEL_TENSOR_14_BASE_ADDR_HIGH 0xF86714
+
+#define mmTPC6_CFG_KERNEL_TENSOR_14_PADDING_VALUE 0xF86718
+
+#define mmTPC6_CFG_KERNEL_TENSOR_14_TENSOR_CONFIG 0xF8671C
+
+#define mmTPC6_CFG_KERNEL_TENSOR_14_DIM_0_SIZE 0xF86720
+
+#define mmTPC6_CFG_KERNEL_TENSOR_14_DIM_0_STRIDE 0xF86724
+
+#define mmTPC6_CFG_KERNEL_TENSOR_14_DIM_1_SIZE 0xF86728
+
+#define mmTPC6_CFG_KERNEL_TENSOR_14_DIM_1_STRIDE 0xF8672C
+
+#define mmTPC6_CFG_KERNEL_TENSOR_14_DIM_2_SIZE 0xF86730
+
+#define mmTPC6_CFG_KERNEL_TENSOR_14_DIM_2_STRIDE 0xF86734
+
+#define mmTPC6_CFG_KERNEL_TENSOR_14_DIM_3_SIZE 0xF86738
+
+#define mmTPC6_CFG_KERNEL_TENSOR_14_DIM_3_STRIDE 0xF8673C
+
+#define mmTPC6_CFG_KERNEL_TENSOR_14_DIM_4_SIZE 0xF86740
+
+#define mmTPC6_CFG_KERNEL_TENSOR_14_DIM_4_STRIDE 0xF86744
+
+#define mmTPC6_CFG_KERNEL_TENSOR_15_BASE_ADDR_LOW 0xF86748
+
+#define mmTPC6_CFG_KERNEL_TENSOR_15_BASE_ADDR_HIGH 0xF8674C
+
+#define mmTPC6_CFG_KERNEL_TENSOR_15_PADDING_VALUE 0xF86750
+
+#define mmTPC6_CFG_KERNEL_TENSOR_15_TENSOR_CONFIG 0xF86754
+
+#define mmTPC6_CFG_KERNEL_TENSOR_15_DIM_0_SIZE 0xF86758
+
+#define mmTPC6_CFG_KERNEL_TENSOR_15_DIM_0_STRIDE 0xF8675C
+
+#define mmTPC6_CFG_KERNEL_TENSOR_15_DIM_1_SIZE 0xF86760
+
+#define mmTPC6_CFG_KERNEL_TENSOR_15_DIM_1_STRIDE 0xF86764
+
+#define mmTPC6_CFG_KERNEL_TENSOR_15_DIM_2_SIZE 0xF86768
+
+#define mmTPC6_CFG_KERNEL_TENSOR_15_DIM_2_STRIDE 0xF8676C
+
+#define mmTPC6_CFG_KERNEL_TENSOR_15_DIM_3_SIZE 0xF86770
+
+#define mmTPC6_CFG_KERNEL_TENSOR_15_DIM_3_STRIDE 0xF86774
+
+#define mmTPC6_CFG_KERNEL_TENSOR_15_DIM_4_SIZE 0xF86778
+
+#define mmTPC6_CFG_KERNEL_TENSOR_15_DIM_4_STRIDE 0xF8677C
+
+#define mmTPC6_CFG_KERNEL_SYNC_OBJECT_MESSAGE 0xF86780
+
+#define mmTPC6_CFG_KERNEL_SYNC_OBJECT_ADDR 0xF86784
+
+#define mmTPC6_CFG_KERNEL_KERNEL_BASE_ADDRESS_LOW 0xF86788
+
+#define mmTPC6_CFG_KERNEL_KERNEL_BASE_ADDRESS_HIGH 0xF8678C
+
+#define mmTPC6_CFG_KERNEL_TID_BASE_DIM_0 0xF86790
+
+#define mmTPC6_CFG_KERNEL_TID_SIZE_DIM_0 0xF86794
+
+#define mmTPC6_CFG_KERNEL_TID_BASE_DIM_1 0xF86798
+
+#define mmTPC6_CFG_KERNEL_TID_SIZE_DIM_1 0xF8679C
+
+#define mmTPC6_CFG_KERNEL_TID_BASE_DIM_2 0xF867A0
+
+#define mmTPC6_CFG_KERNEL_TID_SIZE_DIM_2 0xF867A4
+
+#define mmTPC6_CFG_KERNEL_TID_BASE_DIM_3 0xF867A8
+
+#define mmTPC6_CFG_KERNEL_TID_SIZE_DIM_3 0xF867AC
+
+#define mmTPC6_CFG_KERNEL_TID_BASE_DIM_4 0xF867B0
+
+#define mmTPC6_CFG_KERNEL_TID_SIZE_DIM_4 0xF867B4
+
+#define mmTPC6_CFG_KERNEL_KERNEL_CONFIG 0xF867B8
+
+#define mmTPC6_CFG_KERNEL_KERNEL_ID 0xF867BC
+
+#define mmTPC6_CFG_KERNEL_SRF_0 0xF867C0
+
+#define mmTPC6_CFG_KERNEL_SRF_1 0xF867C4
+
+#define mmTPC6_CFG_KERNEL_SRF_2 0xF867C8
+
+#define mmTPC6_CFG_KERNEL_SRF_3 0xF867CC
+
+#define mmTPC6_CFG_KERNEL_SRF_4 0xF867D0
+
+#define mmTPC6_CFG_KERNEL_SRF_5 0xF867D4
+
+#define mmTPC6_CFG_KERNEL_SRF_6 0xF867D8
+
+#define mmTPC6_CFG_KERNEL_SRF_7 0xF867DC
+
+#define mmTPC6_CFG_KERNEL_SRF_8 0xF867E0
+
+#define mmTPC6_CFG_KERNEL_SRF_9 0xF867E4
+
+#define mmTPC6_CFG_KERNEL_SRF_10 0xF867E8
+
+#define mmTPC6_CFG_KERNEL_SRF_11 0xF867EC
+
+#define mmTPC6_CFG_KERNEL_SRF_12 0xF867F0
+
+#define mmTPC6_CFG_KERNEL_SRF_13 0xF867F4
+
+#define mmTPC6_CFG_KERNEL_SRF_14 0xF867F8
+
+#define mmTPC6_CFG_KERNEL_SRF_15 0xF867FC
+
+#define mmTPC6_CFG_KERNEL_SRF_16 0xF86800
+
+#define mmTPC6_CFG_KERNEL_SRF_17 0xF86804
+
+#define mmTPC6_CFG_KERNEL_SRF_18 0xF86808
+
+#define mmTPC6_CFG_KERNEL_SRF_19 0xF8680C
+
+#define mmTPC6_CFG_KERNEL_SRF_20 0xF86810
+
+#define mmTPC6_CFG_KERNEL_SRF_21 0xF86814
+
+#define mmTPC6_CFG_KERNEL_SRF_22 0xF86818
+
+#define mmTPC6_CFG_KERNEL_SRF_23 0xF8681C
+
+#define mmTPC6_CFG_KERNEL_SRF_24 0xF86820
+
+#define mmTPC6_CFG_KERNEL_SRF_25 0xF86824
+
+#define mmTPC6_CFG_KERNEL_SRF_26 0xF86828
+
+#define mmTPC6_CFG_KERNEL_SRF_27 0xF8682C
+
+#define mmTPC6_CFG_KERNEL_SRF_28 0xF86830
+
+#define mmTPC6_CFG_KERNEL_SRF_29 0xF86834
+
+#define mmTPC6_CFG_KERNEL_SRF_30 0xF86838
+
+#define mmTPC6_CFG_KERNEL_SRF_31 0xF8683C
+
+#define mmTPC6_CFG_ROUND_CSR 0xF868FC
+
+#define mmTPC6_CFG_PROT 0xF86900
+
+#define mmTPC6_CFG_SEMAPHORE 0xF86908
+
+#define mmTPC6_CFG_VFLAGS 0xF8690C
+
+#define mmTPC6_CFG_SFLAGS 0xF86910
+
+#define mmTPC6_CFG_LFSR_POLYNOM 0xF86918
+
+#define mmTPC6_CFG_STATUS 0xF8691C
+
+#define mmTPC6_CFG_CFG_BASE_ADDRESS_HIGH 0xF86920
+
+#define mmTPC6_CFG_CFG_SUBTRACT_VALUE 0xF86924
+
+#define mmTPC6_CFG_SM_BASE_ADDRESS_HIGH 0xF8692C
+
+#define mmTPC6_CFG_TPC_CMD 0xF86930
+
+#define mmTPC6_CFG_TPC_EXECUTE 0xF86938
+
+#define mmTPC6_CFG_TPC_STALL 0xF8693C
+
+#define mmTPC6_CFG_ICACHE_BASE_ADDERESS_LOW 0xF86940
+
+#define mmTPC6_CFG_ICACHE_BASE_ADDERESS_HIGH 0xF86944
+
+#define mmTPC6_CFG_RD_RATE_LIMIT 0xF86948
+
+#define mmTPC6_CFG_WR_RATE_LIMIT 0xF86950
+
+#define mmTPC6_CFG_MSS_CONFIG 0xF86954
+
+#define mmTPC6_CFG_TPC_INTR_CAUSE 0xF86958
+
+#define mmTPC6_CFG_TPC_INTR_MASK 0xF8695C
+
+#define mmTPC6_CFG_WQ_CREDITS 0xF86960
+
+#define mmTPC6_CFG_ARUSER_LO 0xF86964
+
+#define mmTPC6_CFG_ARUSER_HI 0xF86968
+
+#define mmTPC6_CFG_AWUSER_LO 0xF8696C
+
+#define mmTPC6_CFG_AWUSER_HI 0xF86970
+
+#define mmTPC6_CFG_OPCODE_EXEC 0xF86974
+
+#define mmTPC6_CFG_LUT_FUNC32_BASE_ADDR_LO 0xF86978
+
+#define mmTPC6_CFG_LUT_FUNC32_BASE_ADDR_HI 0xF8697C
+
+#define mmTPC6_CFG_LUT_FUNC64_BASE_ADDR_LO 0xF86980
+
+#define mmTPC6_CFG_LUT_FUNC64_BASE_ADDR_HI 0xF86984
+
+#define mmTPC6_CFG_LUT_FUNC128_BASE_ADDR_LO 0xF86988
+
+#define mmTPC6_CFG_LUT_FUNC128_BASE_ADDR_HI 0xF8698C
+
+#define mmTPC6_CFG_LUT_FUNC256_BASE_ADDR_LO 0xF86990
+
+#define mmTPC6_CFG_LUT_FUNC256_BASE_ADDR_HI 0xF86994
+
+#define mmTPC6_CFG_TSB_CFG_MAX_SIZE 0xF86998
+
+#define mmTPC6_CFG_TSB_CFG 0xF8699C
+
+#define mmTPC6_CFG_DBGMEM_ADD 0xF869A0
+
+#define mmTPC6_CFG_DBGMEM_DATA_WR 0xF869A4
+
+#define mmTPC6_CFG_DBGMEM_DATA_RD 0xF869A8
+
+#define mmTPC6_CFG_DBGMEM_CTRL 0xF869AC
+
+#define mmTPC6_CFG_DBGMEM_RC 0xF869B0
+
+#define mmTPC6_CFG_TSB_INFLIGHT_CNTR 0xF869B4
+
+#define mmTPC6_CFG_WQ_INFLIGHT_CNTR 0xF869B8
+
+#define mmTPC6_CFG_WQ_LBW_TOTAL_CNTR 0xF869BC
+
+#define mmTPC6_CFG_WQ_HBW_TOTAL_CNTR 0xF869C0
+
+#define mmTPC6_CFG_IRQ_OCCOUPY_CNTR 0xF869C4
+
+#define mmTPC6_CFG_FUNC_MBIST_CNTRL 0xF869D0
+
+#define mmTPC6_CFG_FUNC_MBIST_PAT 0xF869D4
+
+#define mmTPC6_CFG_FUNC_MBIST_MEM_0 0xF869D8
+
+#define mmTPC6_CFG_FUNC_MBIST_MEM_1 0xF869DC
+
+#define mmTPC6_CFG_FUNC_MBIST_MEM_2 0xF869E0
+
+#define mmTPC6_CFG_FUNC_MBIST_MEM_3 0xF869E4
+
+#define mmTPC6_CFG_FUNC_MBIST_MEM_4 0xF869E8
+
+#define mmTPC6_CFG_FUNC_MBIST_MEM_5 0xF869EC
+
+#define mmTPC6_CFG_FUNC_MBIST_MEM_6 0xF869F0
+
+#define mmTPC6_CFG_FUNC_MBIST_MEM_7 0xF869F4
+
+#define mmTPC6_CFG_FUNC_MBIST_MEM_8 0xF869F8
+
+#define mmTPC6_CFG_FUNC_MBIST_MEM_9 0xF869FC
+
+#define mmTPC6_CFG_QM_TENSOR_0_BASE_ADDR_LOW 0xF86A00
+
+#define mmTPC6_CFG_QM_TENSOR_0_BASE_ADDR_HIGH 0xF86A04
+
+#define mmTPC6_CFG_QM_TENSOR_0_PADDING_VALUE 0xF86A08
+
+#define mmTPC6_CFG_QM_TENSOR_0_TENSOR_CONFIG 0xF86A0C
+
+#define mmTPC6_CFG_QM_TENSOR_0_DIM_0_SIZE 0xF86A10
+
+#define mmTPC6_CFG_QM_TENSOR_0_DIM_0_STRIDE 0xF86A14
+
+#define mmTPC6_CFG_QM_TENSOR_0_DIM_1_SIZE 0xF86A18
+
+#define mmTPC6_CFG_QM_TENSOR_0_DIM_1_STRIDE 0xF86A1C
+
+#define mmTPC6_CFG_QM_TENSOR_0_DIM_2_SIZE 0xF86A20
+
+#define mmTPC6_CFG_QM_TENSOR_0_DIM_2_STRIDE 0xF86A24
+
+#define mmTPC6_CFG_QM_TENSOR_0_DIM_3_SIZE 0xF86A28
+
+#define mmTPC6_CFG_QM_TENSOR_0_DIM_3_STRIDE 0xF86A2C
+
+#define mmTPC6_CFG_QM_TENSOR_0_DIM_4_SIZE 0xF86A30
+
+#define mmTPC6_CFG_QM_TENSOR_0_DIM_4_STRIDE 0xF86A34
+
+#define mmTPC6_CFG_QM_TENSOR_1_BASE_ADDR_LOW 0xF86A38
+
+#define mmTPC6_CFG_QM_TENSOR_1_BASE_ADDR_HIGH 0xF86A3C
+
+#define mmTPC6_CFG_QM_TENSOR_1_PADDING_VALUE 0xF86A40
+
+#define mmTPC6_CFG_QM_TENSOR_1_TENSOR_CONFIG 0xF86A44
+
+#define mmTPC6_CFG_QM_TENSOR_1_DIM_0_SIZE 0xF86A48
+
+#define mmTPC6_CFG_QM_TENSOR_1_DIM_0_STRIDE 0xF86A4C
+
+#define mmTPC6_CFG_QM_TENSOR_1_DIM_1_SIZE 0xF86A50
+
+#define mmTPC6_CFG_QM_TENSOR_1_DIM_1_STRIDE 0xF86A54
+
+#define mmTPC6_CFG_QM_TENSOR_1_DIM_2_SIZE 0xF86A58
+
+#define mmTPC6_CFG_QM_TENSOR_1_DIM_2_STRIDE 0xF86A5C
+
+#define mmTPC6_CFG_QM_TENSOR_1_DIM_3_SIZE 0xF86A60
+
+#define mmTPC6_CFG_QM_TENSOR_1_DIM_3_STRIDE 0xF86A64
+
+#define mmTPC6_CFG_QM_TENSOR_1_DIM_4_SIZE 0xF86A68
+
+#define mmTPC6_CFG_QM_TENSOR_1_DIM_4_STRIDE 0xF86A6C
+
+#define mmTPC6_CFG_QM_TENSOR_2_BASE_ADDR_LOW 0xF86A70
+
+#define mmTPC6_CFG_QM_TENSOR_2_BASE_ADDR_HIGH 0xF86A74
+
+#define mmTPC6_CFG_QM_TENSOR_2_PADDING_VALUE 0xF86A78
+
+#define mmTPC6_CFG_QM_TENSOR_2_TENSOR_CONFIG 0xF86A7C
+
+#define mmTPC6_CFG_QM_TENSOR_2_DIM_0_SIZE 0xF86A80
+
+#define mmTPC6_CFG_QM_TENSOR_2_DIM_0_STRIDE 0xF86A84
+
+#define mmTPC6_CFG_QM_TENSOR_2_DIM_1_SIZE 0xF86A88
+
+#define mmTPC6_CFG_QM_TENSOR_2_DIM_1_STRIDE 0xF86A8C
+
+#define mmTPC6_CFG_QM_TENSOR_2_DIM_2_SIZE 0xF86A90
+
+#define mmTPC6_CFG_QM_TENSOR_2_DIM_2_STRIDE 0xF86A94
+
+#define mmTPC6_CFG_QM_TENSOR_2_DIM_3_SIZE 0xF86A98
+
+#define mmTPC6_CFG_QM_TENSOR_2_DIM_3_STRIDE 0xF86A9C
+
+#define mmTPC6_CFG_QM_TENSOR_2_DIM_4_SIZE 0xF86AA0
+
+#define mmTPC6_CFG_QM_TENSOR_2_DIM_4_STRIDE 0xF86AA4
+
+#define mmTPC6_CFG_QM_TENSOR_3_BASE_ADDR_LOW 0xF86AA8
+
+#define mmTPC6_CFG_QM_TENSOR_3_BASE_ADDR_HIGH 0xF86AAC
+
+#define mmTPC6_CFG_QM_TENSOR_3_PADDING_VALUE 0xF86AB0
+
+#define mmTPC6_CFG_QM_TENSOR_3_TENSOR_CONFIG 0xF86AB4
+
+#define mmTPC6_CFG_QM_TENSOR_3_DIM_0_SIZE 0xF86AB8
+
+#define mmTPC6_CFG_QM_TENSOR_3_DIM_0_STRIDE 0xF86ABC
+
+#define mmTPC6_CFG_QM_TENSOR_3_DIM_1_SIZE 0xF86AC0
+
+#define mmTPC6_CFG_QM_TENSOR_3_DIM_1_STRIDE 0xF86AC4
+
+#define mmTPC6_CFG_QM_TENSOR_3_DIM_2_SIZE 0xF86AC8
+
+#define mmTPC6_CFG_QM_TENSOR_3_DIM_2_STRIDE 0xF86ACC
+
+#define mmTPC6_CFG_QM_TENSOR_3_DIM_3_SIZE 0xF86AD0
+
+#define mmTPC6_CFG_QM_TENSOR_3_DIM_3_STRIDE 0xF86AD4
+
+#define mmTPC6_CFG_QM_TENSOR_3_DIM_4_SIZE 0xF86AD8
+
+#define mmTPC6_CFG_QM_TENSOR_3_DIM_4_STRIDE 0xF86ADC
+
+#define mmTPC6_CFG_QM_TENSOR_4_BASE_ADDR_LOW 0xF86AE0
+
+#define mmTPC6_CFG_QM_TENSOR_4_BASE_ADDR_HIGH 0xF86AE4
+
+#define mmTPC6_CFG_QM_TENSOR_4_PADDING_VALUE 0xF86AE8
+
+#define mmTPC6_CFG_QM_TENSOR_4_TENSOR_CONFIG 0xF86AEC
+
+#define mmTPC6_CFG_QM_TENSOR_4_DIM_0_SIZE 0xF86AF0
+
+#define mmTPC6_CFG_QM_TENSOR_4_DIM_0_STRIDE 0xF86AF4
+
+#define mmTPC6_CFG_QM_TENSOR_4_DIM_1_SIZE 0xF86AF8
+
+#define mmTPC6_CFG_QM_TENSOR_4_DIM_1_STRIDE 0xF86AFC
+
+#define mmTPC6_CFG_QM_TENSOR_4_DIM_2_SIZE 0xF86B00
+
+#define mmTPC6_CFG_QM_TENSOR_4_DIM_2_STRIDE 0xF86B04
+
+#define mmTPC6_CFG_QM_TENSOR_4_DIM_3_SIZE 0xF86B08
+
+#define mmTPC6_CFG_QM_TENSOR_4_DIM_3_STRIDE 0xF86B0C
+
+#define mmTPC6_CFG_QM_TENSOR_4_DIM_4_SIZE 0xF86B10
+
+#define mmTPC6_CFG_QM_TENSOR_4_DIM_4_STRIDE 0xF86B14
+
+#define mmTPC6_CFG_QM_TENSOR_5_BASE_ADDR_LOW 0xF86B18
+
+#define mmTPC6_CFG_QM_TENSOR_5_BASE_ADDR_HIGH 0xF86B1C
+
+#define mmTPC6_CFG_QM_TENSOR_5_PADDING_VALUE 0xF86B20
+
+#define mmTPC6_CFG_QM_TENSOR_5_TENSOR_CONFIG 0xF86B24
+
+#define mmTPC6_CFG_QM_TENSOR_5_DIM_0_SIZE 0xF86B28
+
+#define mmTPC6_CFG_QM_TENSOR_5_DIM_0_STRIDE 0xF86B2C
+
+#define mmTPC6_CFG_QM_TENSOR_5_DIM_1_SIZE 0xF86B30
+
+#define mmTPC6_CFG_QM_TENSOR_5_DIM_1_STRIDE 0xF86B34
+
+#define mmTPC6_CFG_QM_TENSOR_5_DIM_2_SIZE 0xF86B38
+
+#define mmTPC6_CFG_QM_TENSOR_5_DIM_2_STRIDE 0xF86B3C
+
+#define mmTPC6_CFG_QM_TENSOR_5_DIM_3_SIZE 0xF86B40
+
+#define mmTPC6_CFG_QM_TENSOR_5_DIM_3_STRIDE 0xF86B44
+
+#define mmTPC6_CFG_QM_TENSOR_5_DIM_4_SIZE 0xF86B48
+
+#define mmTPC6_CFG_QM_TENSOR_5_DIM_4_STRIDE 0xF86B4C
+
+#define mmTPC6_CFG_QM_TENSOR_6_BASE_ADDR_LOW 0xF86B50
+
+#define mmTPC6_CFG_QM_TENSOR_6_BASE_ADDR_HIGH 0xF86B54
+
+#define mmTPC6_CFG_QM_TENSOR_6_PADDING_VALUE 0xF86B58
+
+#define mmTPC6_CFG_QM_TENSOR_6_TENSOR_CONFIG 0xF86B5C
+
+#define mmTPC6_CFG_QM_TENSOR_6_DIM_0_SIZE 0xF86B60
+
+#define mmTPC6_CFG_QM_TENSOR_6_DIM_0_STRIDE 0xF86B64
+
+#define mmTPC6_CFG_QM_TENSOR_6_DIM_1_SIZE 0xF86B68
+
+#define mmTPC6_CFG_QM_TENSOR_6_DIM_1_STRIDE 0xF86B6C
+
+#define mmTPC6_CFG_QM_TENSOR_6_DIM_2_SIZE 0xF86B70
+
+#define mmTPC6_CFG_QM_TENSOR_6_DIM_2_STRIDE 0xF86B74
+
+#define mmTPC6_CFG_QM_TENSOR_6_DIM_3_SIZE 0xF86B78
+
+#define mmTPC6_CFG_QM_TENSOR_6_DIM_3_STRIDE 0xF86B7C
+
+#define mmTPC6_CFG_QM_TENSOR_6_DIM_4_SIZE 0xF86B80
+
+#define mmTPC6_CFG_QM_TENSOR_6_DIM_4_STRIDE 0xF86B84
+
+#define mmTPC6_CFG_QM_TENSOR_7_BASE_ADDR_LOW 0xF86B88
+
+#define mmTPC6_CFG_QM_TENSOR_7_BASE_ADDR_HIGH 0xF86B8C
+
+#define mmTPC6_CFG_QM_TENSOR_7_PADDING_VALUE 0xF86B90
+
+#define mmTPC6_CFG_QM_TENSOR_7_TENSOR_CONFIG 0xF86B94
+
+#define mmTPC6_CFG_QM_TENSOR_7_DIM_0_SIZE 0xF86B98
+
+#define mmTPC6_CFG_QM_TENSOR_7_DIM_0_STRIDE 0xF86B9C
+
+#define mmTPC6_CFG_QM_TENSOR_7_DIM_1_SIZE 0xF86BA0
+
+#define mmTPC6_CFG_QM_TENSOR_7_DIM_1_STRIDE 0xF86BA4
+
+#define mmTPC6_CFG_QM_TENSOR_7_DIM_2_SIZE 0xF86BA8
+
+#define mmTPC6_CFG_QM_TENSOR_7_DIM_2_STRIDE 0xF86BAC
+
+#define mmTPC6_CFG_QM_TENSOR_7_DIM_3_SIZE 0xF86BB0
+
+#define mmTPC6_CFG_QM_TENSOR_7_DIM_3_STRIDE 0xF86BB4
+
+#define mmTPC6_CFG_QM_TENSOR_7_DIM_4_SIZE 0xF86BB8
+
+#define mmTPC6_CFG_QM_TENSOR_7_DIM_4_STRIDE 0xF86BBC
+
+#define mmTPC6_CFG_QM_TENSOR_8_BASE_ADDR_LOW 0xF86BC0
+
+#define mmTPC6_CFG_QM_TENSOR_8_BASE_ADDR_HIGH 0xF86BC4
+
+#define mmTPC6_CFG_QM_TENSOR_8_PADDING_VALUE 0xF86BC8
+
+#define mmTPC6_CFG_QM_TENSOR_8_TENSOR_CONFIG 0xF86BCC
+
+#define mmTPC6_CFG_QM_TENSOR_8_DIM_0_SIZE 0xF86BD0
+
+#define mmTPC6_CFG_QM_TENSOR_8_DIM_0_STRIDE 0xF86BD4
+
+#define mmTPC6_CFG_QM_TENSOR_8_DIM_1_SIZE 0xF86BD8
+
+#define mmTPC6_CFG_QM_TENSOR_8_DIM_1_STRIDE 0xF86BDC
+
+#define mmTPC6_CFG_QM_TENSOR_8_DIM_2_SIZE 0xF86BE0
+
+#define mmTPC6_CFG_QM_TENSOR_8_DIM_2_STRIDE 0xF86BE4
+
+#define mmTPC6_CFG_QM_TENSOR_8_DIM_3_SIZE 0xF86BE8
+
+#define mmTPC6_CFG_QM_TENSOR_8_DIM_3_STRIDE 0xF86BEC
+
+#define mmTPC6_CFG_QM_TENSOR_8_DIM_4_SIZE 0xF86BF0
+
+#define mmTPC6_CFG_QM_TENSOR_8_DIM_4_STRIDE 0xF86BF4
+
+#define mmTPC6_CFG_QM_TENSOR_9_BASE_ADDR_LOW 0xF86BF8
+
+#define mmTPC6_CFG_QM_TENSOR_9_BASE_ADDR_HIGH 0xF86BFC
+
+#define mmTPC6_CFG_QM_TENSOR_9_PADDING_VALUE 0xF86C00
+
+#define mmTPC6_CFG_QM_TENSOR_9_TENSOR_CONFIG 0xF86C04
+
+#define mmTPC6_CFG_QM_TENSOR_9_DIM_0_SIZE 0xF86C08
+
+#define mmTPC6_CFG_QM_TENSOR_9_DIM_0_STRIDE 0xF86C0C
+
+#define mmTPC6_CFG_QM_TENSOR_9_DIM_1_SIZE 0xF86C10
+
+#define mmTPC6_CFG_QM_TENSOR_9_DIM_1_STRIDE 0xF86C14
+
+#define mmTPC6_CFG_QM_TENSOR_9_DIM_2_SIZE 0xF86C18
+
+#define mmTPC6_CFG_QM_TENSOR_9_DIM_2_STRIDE 0xF86C1C
+
+#define mmTPC6_CFG_QM_TENSOR_9_DIM_3_SIZE 0xF86C20
+
+#define mmTPC6_CFG_QM_TENSOR_9_DIM_3_STRIDE 0xF86C24
+
+#define mmTPC6_CFG_QM_TENSOR_9_DIM_4_SIZE 0xF86C28
+
+#define mmTPC6_CFG_QM_TENSOR_9_DIM_4_STRIDE 0xF86C2C
+
+#define mmTPC6_CFG_QM_TENSOR_10_BASE_ADDR_LOW 0xF86C30
+
+#define mmTPC6_CFG_QM_TENSOR_10_BASE_ADDR_HIGH 0xF86C34
+
+#define mmTPC6_CFG_QM_TENSOR_10_PADDING_VALUE 0xF86C38
+
+#define mmTPC6_CFG_QM_TENSOR_10_TENSOR_CONFIG 0xF86C3C
+
+#define mmTPC6_CFG_QM_TENSOR_10_DIM_0_SIZE 0xF86C40
+
+#define mmTPC6_CFG_QM_TENSOR_10_DIM_0_STRIDE 0xF86C44
+
+#define mmTPC6_CFG_QM_TENSOR_10_DIM_1_SIZE 0xF86C48
+
+#define mmTPC6_CFG_QM_TENSOR_10_DIM_1_STRIDE 0xF86C4C
+
+#define mmTPC6_CFG_QM_TENSOR_10_DIM_2_SIZE 0xF86C50
+
+#define mmTPC6_CFG_QM_TENSOR_10_DIM_2_STRIDE 0xF86C54
+
+#define mmTPC6_CFG_QM_TENSOR_10_DIM_3_SIZE 0xF86C58
+
+#define mmTPC6_CFG_QM_TENSOR_10_DIM_3_STRIDE 0xF86C5C
+
+#define mmTPC6_CFG_QM_TENSOR_10_DIM_4_SIZE 0xF86C60
+
+#define mmTPC6_CFG_QM_TENSOR_10_DIM_4_STRIDE 0xF86C64
+
+#define mmTPC6_CFG_QM_TENSOR_11_BASE_ADDR_LOW 0xF86C68
+
+#define mmTPC6_CFG_QM_TENSOR_11_BASE_ADDR_HIGH 0xF86C6C
+
+#define mmTPC6_CFG_QM_TENSOR_11_PADDING_VALUE 0xF86C70
+
+#define mmTPC6_CFG_QM_TENSOR_11_TENSOR_CONFIG 0xF86C74
+
+#define mmTPC6_CFG_QM_TENSOR_11_DIM_0_SIZE 0xF86C78
+
+#define mmTPC6_CFG_QM_TENSOR_11_DIM_0_STRIDE 0xF86C7C
+
+#define mmTPC6_CFG_QM_TENSOR_11_DIM_1_SIZE 0xF86C80
+
+#define mmTPC6_CFG_QM_TENSOR_11_DIM_1_STRIDE 0xF86C84
+
+#define mmTPC6_CFG_QM_TENSOR_11_DIM_2_SIZE 0xF86C88
+
+#define mmTPC6_CFG_QM_TENSOR_11_DIM_2_STRIDE 0xF86C8C
+
+#define mmTPC6_CFG_QM_TENSOR_11_DIM_3_SIZE 0xF86C90
+
+#define mmTPC6_CFG_QM_TENSOR_11_DIM_3_STRIDE 0xF86C94
+
+#define mmTPC6_CFG_QM_TENSOR_11_DIM_4_SIZE 0xF86C98
+
+#define mmTPC6_CFG_QM_TENSOR_11_DIM_4_STRIDE 0xF86C9C
+
+#define mmTPC6_CFG_QM_TENSOR_12_BASE_ADDR_LOW 0xF86CA0
+
+#define mmTPC6_CFG_QM_TENSOR_12_BASE_ADDR_HIGH 0xF86CA4
+
+#define mmTPC6_CFG_QM_TENSOR_12_PADDING_VALUE 0xF86CA8
+
+#define mmTPC6_CFG_QM_TENSOR_12_TENSOR_CONFIG 0xF86CAC
+
+#define mmTPC6_CFG_QM_TENSOR_12_DIM_0_SIZE 0xF86CB0
+
+#define mmTPC6_CFG_QM_TENSOR_12_DIM_0_STRIDE 0xF86CB4
+
+#define mmTPC6_CFG_QM_TENSOR_12_DIM_1_SIZE 0xF86CB8
+
+#define mmTPC6_CFG_QM_TENSOR_12_DIM_1_STRIDE 0xF86CBC
+
+#define mmTPC6_CFG_QM_TENSOR_12_DIM_2_SIZE 0xF86CC0
+
+#define mmTPC6_CFG_QM_TENSOR_12_DIM_2_STRIDE 0xF86CC4
+
+#define mmTPC6_CFG_QM_TENSOR_12_DIM_3_SIZE 0xF86CC8
+
+#define mmTPC6_CFG_QM_TENSOR_12_DIM_3_STRIDE 0xF86CCC
+
+#define mmTPC6_CFG_QM_TENSOR_12_DIM_4_SIZE 0xF86CD0
+
+#define mmTPC6_CFG_QM_TENSOR_12_DIM_4_STRIDE 0xF86CD4
+
+#define mmTPC6_CFG_QM_TENSOR_13_BASE_ADDR_LOW 0xF86CD8
+
+#define mmTPC6_CFG_QM_TENSOR_13_BASE_ADDR_HIGH 0xF86CDC
+
+#define mmTPC6_CFG_QM_TENSOR_13_PADDING_VALUE 0xF86CE0
+
+#define mmTPC6_CFG_QM_TENSOR_13_TENSOR_CONFIG 0xF86CE4
+
+#define mmTPC6_CFG_QM_TENSOR_13_DIM_0_SIZE 0xF86CE8
+
+#define mmTPC6_CFG_QM_TENSOR_13_DIM_0_STRIDE 0xF86CEC
+
+#define mmTPC6_CFG_QM_TENSOR_13_DIM_1_SIZE 0xF86CF0
+
+#define mmTPC6_CFG_QM_TENSOR_13_DIM_1_STRIDE 0xF86CF4
+
+#define mmTPC6_CFG_QM_TENSOR_13_DIM_2_SIZE 0xF86CF8
+
+#define mmTPC6_CFG_QM_TENSOR_13_DIM_2_STRIDE 0xF86CFC
+
+#define mmTPC6_CFG_QM_TENSOR_13_DIM_3_SIZE 0xF86D00
+
+#define mmTPC6_CFG_QM_TENSOR_13_DIM_3_STRIDE 0xF86D04
+
+#define mmTPC6_CFG_QM_TENSOR_13_DIM_4_SIZE 0xF86D08
+
+#define mmTPC6_CFG_QM_TENSOR_13_DIM_4_STRIDE 0xF86D0C
+
+#define mmTPC6_CFG_QM_TENSOR_14_BASE_ADDR_LOW 0xF86D10
+
+#define mmTPC6_CFG_QM_TENSOR_14_BASE_ADDR_HIGH 0xF86D14
+
+#define mmTPC6_CFG_QM_TENSOR_14_PADDING_VALUE 0xF86D18
+
+#define mmTPC6_CFG_QM_TENSOR_14_TENSOR_CONFIG 0xF86D1C
+
+#define mmTPC6_CFG_QM_TENSOR_14_DIM_0_SIZE 0xF86D20
+
+#define mmTPC6_CFG_QM_TENSOR_14_DIM_0_STRIDE 0xF86D24
+
+#define mmTPC6_CFG_QM_TENSOR_14_DIM_1_SIZE 0xF86D28
+
+#define mmTPC6_CFG_QM_TENSOR_14_DIM_1_STRIDE 0xF86D2C
+
+#define mmTPC6_CFG_QM_TENSOR_14_DIM_2_SIZE 0xF86D30
+
+#define mmTPC6_CFG_QM_TENSOR_14_DIM_2_STRIDE 0xF86D34
+
+#define mmTPC6_CFG_QM_TENSOR_14_DIM_3_SIZE 0xF86D38
+
+#define mmTPC6_CFG_QM_TENSOR_14_DIM_3_STRIDE 0xF86D3C
+
+#define mmTPC6_CFG_QM_TENSOR_14_DIM_4_SIZE 0xF86D40
+
+#define mmTPC6_CFG_QM_TENSOR_14_DIM_4_STRIDE 0xF86D44
+
+#define mmTPC6_CFG_QM_TENSOR_15_BASE_ADDR_LOW 0xF86D48
+
+#define mmTPC6_CFG_QM_TENSOR_15_BASE_ADDR_HIGH 0xF86D4C
+
+#define mmTPC6_CFG_QM_TENSOR_15_PADDING_VALUE 0xF86D50
+
+#define mmTPC6_CFG_QM_TENSOR_15_TENSOR_CONFIG 0xF86D54
+
+#define mmTPC6_CFG_QM_TENSOR_15_DIM_0_SIZE 0xF86D58
+
+#define mmTPC6_CFG_QM_TENSOR_15_DIM_0_STRIDE 0xF86D5C
+
+#define mmTPC6_CFG_QM_TENSOR_15_DIM_1_SIZE 0xF86D60
+
+#define mmTPC6_CFG_QM_TENSOR_15_DIM_1_STRIDE 0xF86D64
+
+#define mmTPC6_CFG_QM_TENSOR_15_DIM_2_SIZE 0xF86D68
+
+#define mmTPC6_CFG_QM_TENSOR_15_DIM_2_STRIDE 0xF86D6C
+
+#define mmTPC6_CFG_QM_TENSOR_15_DIM_3_SIZE 0xF86D70
+
+#define mmTPC6_CFG_QM_TENSOR_15_DIM_3_STRIDE 0xF86D74
+
+#define mmTPC6_CFG_QM_TENSOR_15_DIM_4_SIZE 0xF86D78
+
+#define mmTPC6_CFG_QM_TENSOR_15_DIM_4_STRIDE 0xF86D7C
+
+#define mmTPC6_CFG_QM_SYNC_OBJECT_MESSAGE 0xF86D80
+
+#define mmTPC6_CFG_QM_SYNC_OBJECT_ADDR 0xF86D84
+
+#define mmTPC6_CFG_QM_KERNEL_BASE_ADDRESS_LOW 0xF86D88
+
+#define mmTPC6_CFG_QM_KERNEL_BASE_ADDRESS_HIGH 0xF86D8C
+
+#define mmTPC6_CFG_QM_TID_BASE_DIM_0 0xF86D90
+
+#define mmTPC6_CFG_QM_TID_SIZE_DIM_0 0xF86D94
+
+#define mmTPC6_CFG_QM_TID_BASE_DIM_1 0xF86D98
+
+#define mmTPC6_CFG_QM_TID_SIZE_DIM_1 0xF86D9C
+
+#define mmTPC6_CFG_QM_TID_BASE_DIM_2 0xF86DA0
+
+#define mmTPC6_CFG_QM_TID_SIZE_DIM_2 0xF86DA4
+
+#define mmTPC6_CFG_QM_TID_BASE_DIM_3 0xF86DA8
+
+#define mmTPC6_CFG_QM_TID_SIZE_DIM_3 0xF86DAC
+
+#define mmTPC6_CFG_QM_TID_BASE_DIM_4 0xF86DB0
+
+#define mmTPC6_CFG_QM_TID_SIZE_DIM_4 0xF86DB4
+
+#define mmTPC6_CFG_QM_KERNEL_CONFIG 0xF86DB8
+
+#define mmTPC6_CFG_QM_KERNEL_ID 0xF86DBC
+
+#define mmTPC6_CFG_QM_SRF_0 0xF86DC0
+
+#define mmTPC6_CFG_QM_SRF_1 0xF86DC4
+
+#define mmTPC6_CFG_QM_SRF_2 0xF86DC8
+
+#define mmTPC6_CFG_QM_SRF_3 0xF86DCC
+
+#define mmTPC6_CFG_QM_SRF_4 0xF86DD0
+
+#define mmTPC6_CFG_QM_SRF_5 0xF86DD4
+
+#define mmTPC6_CFG_QM_SRF_6 0xF86DD8
+
+#define mmTPC6_CFG_QM_SRF_7 0xF86DDC
+
+#define mmTPC6_CFG_QM_SRF_8 0xF86DE0
+
+#define mmTPC6_CFG_QM_SRF_9 0xF86DE4
+
+#define mmTPC6_CFG_QM_SRF_10 0xF86DE8
+
+#define mmTPC6_CFG_QM_SRF_11 0xF86DEC
+
+#define mmTPC6_CFG_QM_SRF_12 0xF86DF0
+
+#define mmTPC6_CFG_QM_SRF_13 0xF86DF4
+
+#define mmTPC6_CFG_QM_SRF_14 0xF86DF8
+
+#define mmTPC6_CFG_QM_SRF_15 0xF86DFC
+
+#define mmTPC6_CFG_QM_SRF_16 0xF86E00
+
+#define mmTPC6_CFG_QM_SRF_17 0xF86E04
+
+#define mmTPC6_CFG_QM_SRF_18 0xF86E08
+
+#define mmTPC6_CFG_QM_SRF_19 0xF86E0C
+
+#define mmTPC6_CFG_QM_SRF_20 0xF86E10
+
+#define mmTPC6_CFG_QM_SRF_21 0xF86E14
+
+#define mmTPC6_CFG_QM_SRF_22 0xF86E18
+
+#define mmTPC6_CFG_QM_SRF_23 0xF86E1C
+
+#define mmTPC6_CFG_QM_SRF_24 0xF86E20
+
+#define mmTPC6_CFG_QM_SRF_25 0xF86E24
+
+#define mmTPC6_CFG_QM_SRF_26 0xF86E28
+
+#define mmTPC6_CFG_QM_SRF_27 0xF86E2C
+
+#define mmTPC6_CFG_QM_SRF_28 0xF86E30
+
+#define mmTPC6_CFG_QM_SRF_29 0xF86E34
+
+#define mmTPC6_CFG_QM_SRF_30 0xF86E38
+
+#define mmTPC6_CFG_QM_SRF_31 0xF86E3C
+
+#endif /* ASIC_REG_TPC6_CFG_REGS_H_ */
diff --git a/drivers/accel/habanalabs/include/gaudi/asic_reg/tpc6_qm_regs.h b/drivers/accel/habanalabs/include/gaudi/asic_reg/tpc6_qm_regs.h
new file mode 100644
index 0000000000..e35ef7fd8b
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi/asic_reg/tpc6_qm_regs.h
@@ -0,0 +1,834 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2016-2018 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ ** DO NOT EDIT BELOW **
+ ************************************/
+
+#ifndef ASIC_REG_TPC6_QM_REGS_H_
+#define ASIC_REG_TPC6_QM_REGS_H_
+
+/*
+ *****************************************
+ * TPC6_QM (Prototype: QMAN)
+ *****************************************
+ */
+
+#define mmTPC6_QM_GLBL_CFG0 0xF88000
+
+#define mmTPC6_QM_GLBL_CFG1 0xF88004
+
+#define mmTPC6_QM_GLBL_PROT 0xF88008
+
+#define mmTPC6_QM_GLBL_ERR_CFG 0xF8800C
+
+#define mmTPC6_QM_GLBL_SECURE_PROPS_0 0xF88010
+
+#define mmTPC6_QM_GLBL_SECURE_PROPS_1 0xF88014
+
+#define mmTPC6_QM_GLBL_SECURE_PROPS_2 0xF88018
+
+#define mmTPC6_QM_GLBL_SECURE_PROPS_3 0xF8801C
+
+#define mmTPC6_QM_GLBL_SECURE_PROPS_4 0xF88020
+
+#define mmTPC6_QM_GLBL_NON_SECURE_PROPS_0 0xF88024
+
+#define mmTPC6_QM_GLBL_NON_SECURE_PROPS_1 0xF88028
+
+#define mmTPC6_QM_GLBL_NON_SECURE_PROPS_2 0xF8802C
+
+#define mmTPC6_QM_GLBL_NON_SECURE_PROPS_3 0xF88030
+
+#define mmTPC6_QM_GLBL_NON_SECURE_PROPS_4 0xF88034
+
+#define mmTPC6_QM_GLBL_STS0 0xF88038
+
+#define mmTPC6_QM_GLBL_STS1_0 0xF88040
+
+#define mmTPC6_QM_GLBL_STS1_1 0xF88044
+
+#define mmTPC6_QM_GLBL_STS1_2 0xF88048
+
+#define mmTPC6_QM_GLBL_STS1_3 0xF8804C
+
+#define mmTPC6_QM_GLBL_STS1_4 0xF88050
+
+#define mmTPC6_QM_GLBL_MSG_EN_0 0xF88054
+
+#define mmTPC6_QM_GLBL_MSG_EN_1 0xF88058
+
+#define mmTPC6_QM_GLBL_MSG_EN_2 0xF8805C
+
+#define mmTPC6_QM_GLBL_MSG_EN_3 0xF88060
+
+#define mmTPC6_QM_GLBL_MSG_EN_4 0xF88068
+
+#define mmTPC6_QM_PQ_BASE_LO_0 0xF88070
+
+#define mmTPC6_QM_PQ_BASE_LO_1 0xF88074
+
+#define mmTPC6_QM_PQ_BASE_LO_2 0xF88078
+
+#define mmTPC6_QM_PQ_BASE_LO_3 0xF8807C
+
+#define mmTPC6_QM_PQ_BASE_HI_0 0xF88080
+
+#define mmTPC6_QM_PQ_BASE_HI_1 0xF88084
+
+#define mmTPC6_QM_PQ_BASE_HI_2 0xF88088
+
+#define mmTPC6_QM_PQ_BASE_HI_3 0xF8808C
+
+#define mmTPC6_QM_PQ_SIZE_0 0xF88090
+
+#define mmTPC6_QM_PQ_SIZE_1 0xF88094
+
+#define mmTPC6_QM_PQ_SIZE_2 0xF88098
+
+#define mmTPC6_QM_PQ_SIZE_3 0xF8809C
+
+#define mmTPC6_QM_PQ_PI_0 0xF880A0
+
+#define mmTPC6_QM_PQ_PI_1 0xF880A4
+
+#define mmTPC6_QM_PQ_PI_2 0xF880A8
+
+#define mmTPC6_QM_PQ_PI_3 0xF880AC
+
+#define mmTPC6_QM_PQ_CI_0 0xF880B0
+
+#define mmTPC6_QM_PQ_CI_1 0xF880B4
+
+#define mmTPC6_QM_PQ_CI_2 0xF880B8
+
+#define mmTPC6_QM_PQ_CI_3 0xF880BC
+
+#define mmTPC6_QM_PQ_CFG0_0 0xF880C0
+
+#define mmTPC6_QM_PQ_CFG0_1 0xF880C4
+
+#define mmTPC6_QM_PQ_CFG0_2 0xF880C8
+
+#define mmTPC6_QM_PQ_CFG0_3 0xF880CC
+
+#define mmTPC6_QM_PQ_CFG1_0 0xF880D0
+
+#define mmTPC6_QM_PQ_CFG1_1 0xF880D4
+
+#define mmTPC6_QM_PQ_CFG1_2 0xF880D8
+
+#define mmTPC6_QM_PQ_CFG1_3 0xF880DC
+
+#define mmTPC6_QM_PQ_ARUSER_31_11_0 0xF880E0
+
+#define mmTPC6_QM_PQ_ARUSER_31_11_1 0xF880E4
+
+#define mmTPC6_QM_PQ_ARUSER_31_11_2 0xF880E8
+
+#define mmTPC6_QM_PQ_ARUSER_31_11_3 0xF880EC
+
+#define mmTPC6_QM_PQ_STS0_0 0xF880F0
+
+#define mmTPC6_QM_PQ_STS0_1 0xF880F4
+
+#define mmTPC6_QM_PQ_STS0_2 0xF880F8
+
+#define mmTPC6_QM_PQ_STS0_3 0xF880FC
+
+#define mmTPC6_QM_PQ_STS1_0 0xF88100
+
+#define mmTPC6_QM_PQ_STS1_1 0xF88104
+
+#define mmTPC6_QM_PQ_STS1_2 0xF88108
+
+#define mmTPC6_QM_PQ_STS1_3 0xF8810C
+
+#define mmTPC6_QM_CQ_CFG0_0 0xF88110
+
+#define mmTPC6_QM_CQ_CFG0_1 0xF88114
+
+#define mmTPC6_QM_CQ_CFG0_2 0xF88118
+
+#define mmTPC6_QM_CQ_CFG0_3 0xF8811C
+
+#define mmTPC6_QM_CQ_CFG0_4 0xF88120
+
+#define mmTPC6_QM_CQ_CFG1_0 0xF88124
+
+#define mmTPC6_QM_CQ_CFG1_1 0xF88128
+
+#define mmTPC6_QM_CQ_CFG1_2 0xF8812C
+
+#define mmTPC6_QM_CQ_CFG1_3 0xF88130
+
+#define mmTPC6_QM_CQ_CFG1_4 0xF88134
+
+#define mmTPC6_QM_CQ_ARUSER_31_11_0 0xF88138
+
+#define mmTPC6_QM_CQ_ARUSER_31_11_1 0xF8813C
+
+#define mmTPC6_QM_CQ_ARUSER_31_11_2 0xF88140
+
+#define mmTPC6_QM_CQ_ARUSER_31_11_3 0xF88144
+
+#define mmTPC6_QM_CQ_ARUSER_31_11_4 0xF88148
+
+#define mmTPC6_QM_CQ_STS0_0 0xF8814C
+
+#define mmTPC6_QM_CQ_STS0_1 0xF88150
+
+#define mmTPC6_QM_CQ_STS0_2 0xF88154
+
+#define mmTPC6_QM_CQ_STS0_3 0xF88158
+
+#define mmTPC6_QM_CQ_STS0_4 0xF8815C
+
+#define mmTPC6_QM_CQ_STS1_0 0xF88160
+
+#define mmTPC6_QM_CQ_STS1_1 0xF88164
+
+#define mmTPC6_QM_CQ_STS1_2 0xF88168
+
+#define mmTPC6_QM_CQ_STS1_3 0xF8816C
+
+#define mmTPC6_QM_CQ_STS1_4 0xF88170
+
+#define mmTPC6_QM_CQ_PTR_LO_0 0xF88174
+
+#define mmTPC6_QM_CQ_PTR_HI_0 0xF88178
+
+#define mmTPC6_QM_CQ_TSIZE_0 0xF8817C
+
+#define mmTPC6_QM_CQ_CTL_0 0xF88180
+
+#define mmTPC6_QM_CQ_PTR_LO_1 0xF88184
+
+#define mmTPC6_QM_CQ_PTR_HI_1 0xF88188
+
+#define mmTPC6_QM_CQ_TSIZE_1 0xF8818C
+
+#define mmTPC6_QM_CQ_CTL_1 0xF88190
+
+#define mmTPC6_QM_CQ_PTR_LO_2 0xF88194
+
+#define mmTPC6_QM_CQ_PTR_HI_2 0xF88198
+
+#define mmTPC6_QM_CQ_TSIZE_2 0xF8819C
+
+#define mmTPC6_QM_CQ_CTL_2 0xF881A0
+
+#define mmTPC6_QM_CQ_PTR_LO_3 0xF881A4
+
+#define mmTPC6_QM_CQ_PTR_HI_3 0xF881A8
+
+#define mmTPC6_QM_CQ_TSIZE_3 0xF881AC
+
+#define mmTPC6_QM_CQ_CTL_3 0xF881B0
+
+#define mmTPC6_QM_CQ_PTR_LO_4 0xF881B4
+
+#define mmTPC6_QM_CQ_PTR_HI_4 0xF881B8
+
+#define mmTPC6_QM_CQ_TSIZE_4 0xF881BC
+
+#define mmTPC6_QM_CQ_CTL_4 0xF881C0
+
+#define mmTPC6_QM_CQ_PTR_LO_STS_0 0xF881C4
+
+#define mmTPC6_QM_CQ_PTR_LO_STS_1 0xF881C8
+
+#define mmTPC6_QM_CQ_PTR_LO_STS_2 0xF881CC
+
+#define mmTPC6_QM_CQ_PTR_LO_STS_3 0xF881D0
+
+#define mmTPC6_QM_CQ_PTR_LO_STS_4 0xF881D4
+
+#define mmTPC6_QM_CQ_PTR_HI_STS_0 0xF881D8
+
+#define mmTPC6_QM_CQ_PTR_HI_STS_1 0xF881DC
+
+#define mmTPC6_QM_CQ_PTR_HI_STS_2 0xF881E0
+
+#define mmTPC6_QM_CQ_PTR_HI_STS_3 0xF881E4
+
+#define mmTPC6_QM_CQ_PTR_HI_STS_4 0xF881E8
+
+#define mmTPC6_QM_CQ_TSIZE_STS_0 0xF881EC
+
+#define mmTPC6_QM_CQ_TSIZE_STS_1 0xF881F0
+
+#define mmTPC6_QM_CQ_TSIZE_STS_2 0xF881F4
+
+#define mmTPC6_QM_CQ_TSIZE_STS_3 0xF881F8
+
+#define mmTPC6_QM_CQ_TSIZE_STS_4 0xF881FC
+
+#define mmTPC6_QM_CQ_CTL_STS_0 0xF88200
+
+#define mmTPC6_QM_CQ_CTL_STS_1 0xF88204
+
+#define mmTPC6_QM_CQ_CTL_STS_2 0xF88208
+
+#define mmTPC6_QM_CQ_CTL_STS_3 0xF8820C
+
+#define mmTPC6_QM_CQ_CTL_STS_4 0xF88210
+
+#define mmTPC6_QM_CQ_IFIFO_CNT_0 0xF88214
+
+#define mmTPC6_QM_CQ_IFIFO_CNT_1 0xF88218
+
+#define mmTPC6_QM_CQ_IFIFO_CNT_2 0xF8821C
+
+#define mmTPC6_QM_CQ_IFIFO_CNT_3 0xF88220
+
+#define mmTPC6_QM_CQ_IFIFO_CNT_4 0xF88224
+
+#define mmTPC6_QM_CP_MSG_BASE0_ADDR_LO_0 0xF88228
+
+#define mmTPC6_QM_CP_MSG_BASE0_ADDR_LO_1 0xF8822C
+
+#define mmTPC6_QM_CP_MSG_BASE0_ADDR_LO_2 0xF88230
+
+#define mmTPC6_QM_CP_MSG_BASE0_ADDR_LO_3 0xF88234
+
+#define mmTPC6_QM_CP_MSG_BASE0_ADDR_LO_4 0xF88238
+
+#define mmTPC6_QM_CP_MSG_BASE0_ADDR_HI_0 0xF8823C
+
+#define mmTPC6_QM_CP_MSG_BASE0_ADDR_HI_1 0xF88240
+
+#define mmTPC6_QM_CP_MSG_BASE0_ADDR_HI_2 0xF88244
+
+#define mmTPC6_QM_CP_MSG_BASE0_ADDR_HI_3 0xF88248
+
+#define mmTPC6_QM_CP_MSG_BASE0_ADDR_HI_4 0xF8824C
+
+#define mmTPC6_QM_CP_MSG_BASE1_ADDR_LO_0 0xF88250
+
+#define mmTPC6_QM_CP_MSG_BASE1_ADDR_LO_1 0xF88254
+
+#define mmTPC6_QM_CP_MSG_BASE1_ADDR_LO_2 0xF88258
+
+#define mmTPC6_QM_CP_MSG_BASE1_ADDR_LO_3 0xF8825C
+
+#define mmTPC6_QM_CP_MSG_BASE1_ADDR_LO_4 0xF88260
+
+#define mmTPC6_QM_CP_MSG_BASE1_ADDR_HI_0 0xF88264
+
+#define mmTPC6_QM_CP_MSG_BASE1_ADDR_HI_1 0xF88268
+
+#define mmTPC6_QM_CP_MSG_BASE1_ADDR_HI_2 0xF8826C
+
+#define mmTPC6_QM_CP_MSG_BASE1_ADDR_HI_3 0xF88270
+
+#define mmTPC6_QM_CP_MSG_BASE1_ADDR_HI_4 0xF88274
+
+#define mmTPC6_QM_CP_MSG_BASE2_ADDR_LO_0 0xF88278
+
+#define mmTPC6_QM_CP_MSG_BASE2_ADDR_LO_1 0xF8827C
+
+#define mmTPC6_QM_CP_MSG_BASE2_ADDR_LO_2 0xF88280
+
+#define mmTPC6_QM_CP_MSG_BASE2_ADDR_LO_3 0xF88284
+
+#define mmTPC6_QM_CP_MSG_BASE2_ADDR_LO_4 0xF88288
+
+#define mmTPC6_QM_CP_MSG_BASE2_ADDR_HI_0 0xF8828C
+
+#define mmTPC6_QM_CP_MSG_BASE2_ADDR_HI_1 0xF88290
+
+#define mmTPC6_QM_CP_MSG_BASE2_ADDR_HI_2 0xF88294
+
+#define mmTPC6_QM_CP_MSG_BASE2_ADDR_HI_3 0xF88298
+
+#define mmTPC6_QM_CP_MSG_BASE2_ADDR_HI_4 0xF8829C
+
+#define mmTPC6_QM_CP_MSG_BASE3_ADDR_LO_0 0xF882A0
+
+#define mmTPC6_QM_CP_MSG_BASE3_ADDR_LO_1 0xF882A4
+
+#define mmTPC6_QM_CP_MSG_BASE3_ADDR_LO_2 0xF882A8
+
+#define mmTPC6_QM_CP_MSG_BASE3_ADDR_LO_3 0xF882AC
+
+#define mmTPC6_QM_CP_MSG_BASE3_ADDR_LO_4 0xF882B0
+
+#define mmTPC6_QM_CP_MSG_BASE3_ADDR_HI_0 0xF882B4
+
+#define mmTPC6_QM_CP_MSG_BASE3_ADDR_HI_1 0xF882B8
+
+#define mmTPC6_QM_CP_MSG_BASE3_ADDR_HI_2 0xF882BC
+
+#define mmTPC6_QM_CP_MSG_BASE3_ADDR_HI_3 0xF882C0
+
+#define mmTPC6_QM_CP_MSG_BASE3_ADDR_HI_4 0xF882C4
+
+#define mmTPC6_QM_CP_LDMA_TSIZE_OFFSET_0 0xF882C8
+
+#define mmTPC6_QM_CP_LDMA_TSIZE_OFFSET_1 0xF882CC
+
+#define mmTPC6_QM_CP_LDMA_TSIZE_OFFSET_2 0xF882D0
+
+#define mmTPC6_QM_CP_LDMA_TSIZE_OFFSET_3 0xF882D4
+
+#define mmTPC6_QM_CP_LDMA_TSIZE_OFFSET_4 0xF882D8
+
+#define mmTPC6_QM_CP_LDMA_SRC_BASE_LO_OFFSET_0 0xF882E0
+
+#define mmTPC6_QM_CP_LDMA_SRC_BASE_LO_OFFSET_1 0xF882E4
+
+#define mmTPC6_QM_CP_LDMA_SRC_BASE_LO_OFFSET_2 0xF882E8
+
+#define mmTPC6_QM_CP_LDMA_SRC_BASE_LO_OFFSET_3 0xF882EC
+
+#define mmTPC6_QM_CP_LDMA_SRC_BASE_LO_OFFSET_4 0xF882F0
+
+#define mmTPC6_QM_CP_LDMA_DST_BASE_LO_OFFSET_0 0xF882F4
+
+#define mmTPC6_QM_CP_LDMA_DST_BASE_LO_OFFSET_1 0xF882F8
+
+#define mmTPC6_QM_CP_LDMA_DST_BASE_LO_OFFSET_2 0xF882FC
+
+#define mmTPC6_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 0xF88300
+
+#define mmTPC6_QM_CP_LDMA_DST_BASE_LO_OFFSET_4 0xF88304
+
+#define mmTPC6_QM_CP_FENCE0_RDATA_0 0xF88308
+
+#define mmTPC6_QM_CP_FENCE0_RDATA_1 0xF8830C
+
+#define mmTPC6_QM_CP_FENCE0_RDATA_2 0xF88310
+
+#define mmTPC6_QM_CP_FENCE0_RDATA_3 0xF88314
+
+#define mmTPC6_QM_CP_FENCE0_RDATA_4 0xF88318
+
+#define mmTPC6_QM_CP_FENCE1_RDATA_0 0xF8831C
+
+#define mmTPC6_QM_CP_FENCE1_RDATA_1 0xF88320
+
+#define mmTPC6_QM_CP_FENCE1_RDATA_2 0xF88324
+
+#define mmTPC6_QM_CP_FENCE1_RDATA_3 0xF88328
+
+#define mmTPC6_QM_CP_FENCE1_RDATA_4 0xF8832C
+
+#define mmTPC6_QM_CP_FENCE2_RDATA_0 0xF88330
+
+#define mmTPC6_QM_CP_FENCE2_RDATA_1 0xF88334
+
+#define mmTPC6_QM_CP_FENCE2_RDATA_2 0xF88338
+
+#define mmTPC6_QM_CP_FENCE2_RDATA_3 0xF8833C
+
+#define mmTPC6_QM_CP_FENCE2_RDATA_4 0xF88340
+
+#define mmTPC6_QM_CP_FENCE3_RDATA_0 0xF88344
+
+#define mmTPC6_QM_CP_FENCE3_RDATA_1 0xF88348
+
+#define mmTPC6_QM_CP_FENCE3_RDATA_2 0xF8834C
+
+#define mmTPC6_QM_CP_FENCE3_RDATA_3 0xF88350
+
+#define mmTPC6_QM_CP_FENCE3_RDATA_4 0xF88354
+
+#define mmTPC6_QM_CP_FENCE0_CNT_0 0xF88358
+
+#define mmTPC6_QM_CP_FENCE0_CNT_1 0xF8835C
+
+#define mmTPC6_QM_CP_FENCE0_CNT_2 0xF88360
+
+#define mmTPC6_QM_CP_FENCE0_CNT_3 0xF88364
+
+#define mmTPC6_QM_CP_FENCE0_CNT_4 0xF88368
+
+#define mmTPC6_QM_CP_FENCE1_CNT_0 0xF8836C
+
+#define mmTPC6_QM_CP_FENCE1_CNT_1 0xF88370
+
+#define mmTPC6_QM_CP_FENCE1_CNT_2 0xF88374
+
+#define mmTPC6_QM_CP_FENCE1_CNT_3 0xF88378
+
+#define mmTPC6_QM_CP_FENCE1_CNT_4 0xF8837C
+
+#define mmTPC6_QM_CP_FENCE2_CNT_0 0xF88380
+
+#define mmTPC6_QM_CP_FENCE2_CNT_1 0xF88384
+
+#define mmTPC6_QM_CP_FENCE2_CNT_2 0xF88388
+
+#define mmTPC6_QM_CP_FENCE2_CNT_3 0xF8838C
+
+#define mmTPC6_QM_CP_FENCE2_CNT_4 0xF88390
+
+#define mmTPC6_QM_CP_FENCE3_CNT_0 0xF88394
+
+#define mmTPC6_QM_CP_FENCE3_CNT_1 0xF88398
+
+#define mmTPC6_QM_CP_FENCE3_CNT_2 0xF8839C
+
+#define mmTPC6_QM_CP_FENCE3_CNT_3 0xF883A0
+
+#define mmTPC6_QM_CP_FENCE3_CNT_4 0xF883A4
+
+#define mmTPC6_QM_CP_STS_0 0xF883A8
+
+#define mmTPC6_QM_CP_STS_1 0xF883AC
+
+#define mmTPC6_QM_CP_STS_2 0xF883B0
+
+#define mmTPC6_QM_CP_STS_3 0xF883B4
+
+#define mmTPC6_QM_CP_STS_4 0xF883B8
+
+#define mmTPC6_QM_CP_CURRENT_INST_LO_0 0xF883BC
+
+#define mmTPC6_QM_CP_CURRENT_INST_LO_1 0xF883C0
+
+#define mmTPC6_QM_CP_CURRENT_INST_LO_2 0xF883C4
+
+#define mmTPC6_QM_CP_CURRENT_INST_LO_3 0xF883C8
+
+#define mmTPC6_QM_CP_CURRENT_INST_LO_4 0xF883CC
+
+#define mmTPC6_QM_CP_CURRENT_INST_HI_0 0xF883D0
+
+#define mmTPC6_QM_CP_CURRENT_INST_HI_1 0xF883D4
+
+#define mmTPC6_QM_CP_CURRENT_INST_HI_2 0xF883D8
+
+#define mmTPC6_QM_CP_CURRENT_INST_HI_3 0xF883DC
+
+#define mmTPC6_QM_CP_CURRENT_INST_HI_4 0xF883E0
+
+#define mmTPC6_QM_CP_BARRIER_CFG_0 0xF883F4
+
+#define mmTPC6_QM_CP_BARRIER_CFG_1 0xF883F8
+
+#define mmTPC6_QM_CP_BARRIER_CFG_2 0xF883FC
+
+#define mmTPC6_QM_CP_BARRIER_CFG_3 0xF88400
+
+#define mmTPC6_QM_CP_BARRIER_CFG_4 0xF88404
+
+#define mmTPC6_QM_CP_DBG_0_0 0xF88408
+
+#define mmTPC6_QM_CP_DBG_0_1 0xF8840C
+
+#define mmTPC6_QM_CP_DBG_0_2 0xF88410
+
+#define mmTPC6_QM_CP_DBG_0_3 0xF88414
+
+#define mmTPC6_QM_CP_DBG_0_4 0xF88418
+
+#define mmTPC6_QM_CP_ARUSER_31_11_0 0xF8841C
+
+#define mmTPC6_QM_CP_ARUSER_31_11_1 0xF88420
+
+#define mmTPC6_QM_CP_ARUSER_31_11_2 0xF88424
+
+#define mmTPC6_QM_CP_ARUSER_31_11_3 0xF88428
+
+#define mmTPC6_QM_CP_ARUSER_31_11_4 0xF8842C
+
+#define mmTPC6_QM_CP_AWUSER_31_11_0 0xF88430
+
+#define mmTPC6_QM_CP_AWUSER_31_11_1 0xF88434
+
+#define mmTPC6_QM_CP_AWUSER_31_11_2 0xF88438
+
+#define mmTPC6_QM_CP_AWUSER_31_11_3 0xF8843C
+
+#define mmTPC6_QM_CP_AWUSER_31_11_4 0xF88440
+
+#define mmTPC6_QM_ARB_CFG_0 0xF88A00
+
+#define mmTPC6_QM_ARB_CHOISE_Q_PUSH 0xF88A04
+
+#define mmTPC6_QM_ARB_WRR_WEIGHT_0 0xF88A08
+
+#define mmTPC6_QM_ARB_WRR_WEIGHT_1 0xF88A0C
+
+#define mmTPC6_QM_ARB_WRR_WEIGHT_2 0xF88A10
+
+#define mmTPC6_QM_ARB_WRR_WEIGHT_3 0xF88A14
+
+#define mmTPC6_QM_ARB_CFG_1 0xF88A18
+
+#define mmTPC6_QM_ARB_MST_AVAIL_CRED_0 0xF88A20
+
+#define mmTPC6_QM_ARB_MST_AVAIL_CRED_1 0xF88A24
+
+#define mmTPC6_QM_ARB_MST_AVAIL_CRED_2 0xF88A28
+
+#define mmTPC6_QM_ARB_MST_AVAIL_CRED_3 0xF88A2C
+
+#define mmTPC6_QM_ARB_MST_AVAIL_CRED_4 0xF88A30
+
+#define mmTPC6_QM_ARB_MST_AVAIL_CRED_5 0xF88A34
+
+#define mmTPC6_QM_ARB_MST_AVAIL_CRED_6 0xF88A38
+
+#define mmTPC6_QM_ARB_MST_AVAIL_CRED_7 0xF88A3C
+
+#define mmTPC6_QM_ARB_MST_AVAIL_CRED_8 0xF88A40
+
+#define mmTPC6_QM_ARB_MST_AVAIL_CRED_9 0xF88A44
+
+#define mmTPC6_QM_ARB_MST_AVAIL_CRED_10 0xF88A48
+
+#define mmTPC6_QM_ARB_MST_AVAIL_CRED_11 0xF88A4C
+
+#define mmTPC6_QM_ARB_MST_AVAIL_CRED_12 0xF88A50
+
+#define mmTPC6_QM_ARB_MST_AVAIL_CRED_13 0xF88A54
+
+#define mmTPC6_QM_ARB_MST_AVAIL_CRED_14 0xF88A58
+
+#define mmTPC6_QM_ARB_MST_AVAIL_CRED_15 0xF88A5C
+
+#define mmTPC6_QM_ARB_MST_AVAIL_CRED_16 0xF88A60
+
+#define mmTPC6_QM_ARB_MST_AVAIL_CRED_17 0xF88A64
+
+#define mmTPC6_QM_ARB_MST_AVAIL_CRED_18 0xF88A68
+
+#define mmTPC6_QM_ARB_MST_AVAIL_CRED_19 0xF88A6C
+
+#define mmTPC6_QM_ARB_MST_AVAIL_CRED_20 0xF88A70
+
+#define mmTPC6_QM_ARB_MST_AVAIL_CRED_21 0xF88A74
+
+#define mmTPC6_QM_ARB_MST_AVAIL_CRED_22 0xF88A78
+
+#define mmTPC6_QM_ARB_MST_AVAIL_CRED_23 0xF88A7C
+
+#define mmTPC6_QM_ARB_MST_AVAIL_CRED_24 0xF88A80
+
+#define mmTPC6_QM_ARB_MST_AVAIL_CRED_25 0xF88A84
+
+#define mmTPC6_QM_ARB_MST_AVAIL_CRED_26 0xF88A88
+
+#define mmTPC6_QM_ARB_MST_AVAIL_CRED_27 0xF88A8C
+
+#define mmTPC6_QM_ARB_MST_AVAIL_CRED_28 0xF88A90
+
+#define mmTPC6_QM_ARB_MST_AVAIL_CRED_29 0xF88A94
+
+#define mmTPC6_QM_ARB_MST_AVAIL_CRED_30 0xF88A98
+
+#define mmTPC6_QM_ARB_MST_AVAIL_CRED_31 0xF88A9C
+
+#define mmTPC6_QM_ARB_MST_CRED_INC 0xF88AA0
+
+#define mmTPC6_QM_ARB_MST_CHOISE_PUSH_OFST_0 0xF88AA4
+
+#define mmTPC6_QM_ARB_MST_CHOISE_PUSH_OFST_1 0xF88AA8
+
+#define mmTPC6_QM_ARB_MST_CHOISE_PUSH_OFST_2 0xF88AAC
+
+#define mmTPC6_QM_ARB_MST_CHOISE_PUSH_OFST_3 0xF88AB0
+
+#define mmTPC6_QM_ARB_MST_CHOISE_PUSH_OFST_4 0xF88AB4
+
+#define mmTPC6_QM_ARB_MST_CHOISE_PUSH_OFST_5 0xF88AB8
+
+#define mmTPC6_QM_ARB_MST_CHOISE_PUSH_OFST_6 0xF88ABC
+
+#define mmTPC6_QM_ARB_MST_CHOISE_PUSH_OFST_7 0xF88AC0
+
+#define mmTPC6_QM_ARB_MST_CHOISE_PUSH_OFST_8 0xF88AC4
+
+#define mmTPC6_QM_ARB_MST_CHOISE_PUSH_OFST_9 0xF88AC8
+
+#define mmTPC6_QM_ARB_MST_CHOISE_PUSH_OFST_10 0xF88ACC
+
+#define mmTPC6_QM_ARB_MST_CHOISE_PUSH_OFST_11 0xF88AD0
+
+#define mmTPC6_QM_ARB_MST_CHOISE_PUSH_OFST_12 0xF88AD4
+
+#define mmTPC6_QM_ARB_MST_CHOISE_PUSH_OFST_13 0xF88AD8
+
+#define mmTPC6_QM_ARB_MST_CHOISE_PUSH_OFST_14 0xF88ADC
+
+#define mmTPC6_QM_ARB_MST_CHOISE_PUSH_OFST_15 0xF88AE0
+
+#define mmTPC6_QM_ARB_MST_CHOISE_PUSH_OFST_16 0xF88AE4
+
+#define mmTPC6_QM_ARB_MST_CHOISE_PUSH_OFST_17 0xF88AE8
+
+#define mmTPC6_QM_ARB_MST_CHOISE_PUSH_OFST_18 0xF88AEC
+
+#define mmTPC6_QM_ARB_MST_CHOISE_PUSH_OFST_19 0xF88AF0
+
+#define mmTPC6_QM_ARB_MST_CHOISE_PUSH_OFST_20 0xF88AF4
+
+#define mmTPC6_QM_ARB_MST_CHOISE_PUSH_OFST_21 0xF88AF8
+
+#define mmTPC6_QM_ARB_MST_CHOISE_PUSH_OFST_22 0xF88AFC
+
+#define mmTPC6_QM_ARB_MST_CHOISE_PUSH_OFST_23 0xF88B00
+
+#define mmTPC6_QM_ARB_MST_CHOISE_PUSH_OFST_24 0xF88B04
+
+#define mmTPC6_QM_ARB_MST_CHOISE_PUSH_OFST_25 0xF88B08
+
+#define mmTPC6_QM_ARB_MST_CHOISE_PUSH_OFST_26 0xF88B0C
+
+#define mmTPC6_QM_ARB_MST_CHOISE_PUSH_OFST_27 0xF88B10
+
+#define mmTPC6_QM_ARB_MST_CHOISE_PUSH_OFST_28 0xF88B14
+
+#define mmTPC6_QM_ARB_MST_CHOISE_PUSH_OFST_29 0xF88B18
+
+#define mmTPC6_QM_ARB_MST_CHOISE_PUSH_OFST_30 0xF88B1C
+
+#define mmTPC6_QM_ARB_MST_CHOISE_PUSH_OFST_31 0xF88B20
+
+#define mmTPC6_QM_ARB_SLV_MASTER_INC_CRED_OFST 0xF88B28
+
+#define mmTPC6_QM_ARB_MST_SLAVE_EN 0xF88B2C
+
+#define mmTPC6_QM_ARB_MST_QUIET_PER 0xF88B34
+
+#define mmTPC6_QM_ARB_SLV_CHOISE_WDT 0xF88B38
+
+#define mmTPC6_QM_ARB_SLV_ID 0xF88B3C
+
+#define mmTPC6_QM_ARB_MSG_MAX_INFLIGHT 0xF88B44
+
+#define mmTPC6_QM_ARB_MSG_AWUSER_31_11 0xF88B48
+
+#define mmTPC6_QM_ARB_MSG_AWUSER_SEC_PROP 0xF88B4C
+
+#define mmTPC6_QM_ARB_MSG_AWUSER_NON_SEC_PROP 0xF88B50
+
+#define mmTPC6_QM_ARB_BASE_LO 0xF88B54
+
+#define mmTPC6_QM_ARB_BASE_HI 0xF88B58
+
+#define mmTPC6_QM_ARB_STATE_STS 0xF88B80
+
+#define mmTPC6_QM_ARB_CHOISE_FULLNESS_STS 0xF88B84
+
+#define mmTPC6_QM_ARB_MSG_STS 0xF88B88
+
+#define mmTPC6_QM_ARB_SLV_CHOISE_Q_HEAD 0xF88B8C
+
+#define mmTPC6_QM_ARB_ERR_CAUSE 0xF88B9C
+
+#define mmTPC6_QM_ARB_ERR_MSG_EN 0xF88BA0
+
+#define mmTPC6_QM_ARB_ERR_STS_DRP 0xF88BA8
+
+#define mmTPC6_QM_ARB_MST_CRED_STS_0 0xF88BB0
+
+#define mmTPC6_QM_ARB_MST_CRED_STS_1 0xF88BB4
+
+#define mmTPC6_QM_ARB_MST_CRED_STS_2 0xF88BB8
+
+#define mmTPC6_QM_ARB_MST_CRED_STS_3 0xF88BBC
+
+#define mmTPC6_QM_ARB_MST_CRED_STS_4 0xF88BC0
+
+#define mmTPC6_QM_ARB_MST_CRED_STS_5 0xF88BC4
+
+#define mmTPC6_QM_ARB_MST_CRED_STS_6 0xF88BC8
+
+#define mmTPC6_QM_ARB_MST_CRED_STS_7 0xF88BCC
+
+#define mmTPC6_QM_ARB_MST_CRED_STS_8 0xF88BD0
+
+#define mmTPC6_QM_ARB_MST_CRED_STS_9 0xF88BD4
+
+#define mmTPC6_QM_ARB_MST_CRED_STS_10 0xF88BD8
+
+#define mmTPC6_QM_ARB_MST_CRED_STS_11 0xF88BDC
+
+#define mmTPC6_QM_ARB_MST_CRED_STS_12 0xF88BE0
+
+#define mmTPC6_QM_ARB_MST_CRED_STS_13 0xF88BE4
+
+#define mmTPC6_QM_ARB_MST_CRED_STS_14 0xF88BE8
+
+#define mmTPC6_QM_ARB_MST_CRED_STS_15 0xF88BEC
+
+#define mmTPC6_QM_ARB_MST_CRED_STS_16 0xF88BF0
+
+#define mmTPC6_QM_ARB_MST_CRED_STS_17 0xF88BF4
+
+#define mmTPC6_QM_ARB_MST_CRED_STS_18 0xF88BF8
+
+#define mmTPC6_QM_ARB_MST_CRED_STS_19 0xF88BFC
+
+#define mmTPC6_QM_ARB_MST_CRED_STS_20 0xF88C00
+
+#define mmTPC6_QM_ARB_MST_CRED_STS_21 0xF88C04
+
+#define mmTPC6_QM_ARB_MST_CRED_STS_22 0xF88C08
+
+#define mmTPC6_QM_ARB_MST_CRED_STS_23 0xF88C0C
+
+#define mmTPC6_QM_ARB_MST_CRED_STS_24 0xF88C10
+
+#define mmTPC6_QM_ARB_MST_CRED_STS_25 0xF88C14
+
+#define mmTPC6_QM_ARB_MST_CRED_STS_26 0xF88C18
+
+#define mmTPC6_QM_ARB_MST_CRED_STS_27 0xF88C1C
+
+#define mmTPC6_QM_ARB_MST_CRED_STS_28 0xF88C20
+
+#define mmTPC6_QM_ARB_MST_CRED_STS_29 0xF88C24
+
+#define mmTPC6_QM_ARB_MST_CRED_STS_30 0xF88C28
+
+#define mmTPC6_QM_ARB_MST_CRED_STS_31 0xF88C2C
+
+#define mmTPC6_QM_CGM_CFG 0xF88C70
+
+#define mmTPC6_QM_CGM_STS 0xF88C74
+
+#define mmTPC6_QM_CGM_CFG1 0xF88C78
+
+#define mmTPC6_QM_LOCAL_RANGE_BASE 0xF88C80
+
+#define mmTPC6_QM_LOCAL_RANGE_SIZE 0xF88C84
+
+#define mmTPC6_QM_CSMR_STRICT_PRIO_CFG 0xF88C90
+
+#define mmTPC6_QM_HBW_RD_RATE_LIM_CFG_1 0xF88C94
+
+#define mmTPC6_QM_LBW_WR_RATE_LIM_CFG_0 0xF88C98
+
+#define mmTPC6_QM_LBW_WR_RATE_LIM_CFG_1 0xF88C9C
+
+#define mmTPC6_QM_HBW_RD_RATE_LIM_CFG_0 0xF88CA0
+
+#define mmTPC6_QM_GLBL_AXCACHE 0xF88CA4
+
+#define mmTPC6_QM_IND_GW_APB_CFG 0xF88CB0
+
+#define mmTPC6_QM_IND_GW_APB_WDATA 0xF88CB4
+
+#define mmTPC6_QM_IND_GW_APB_RDATA 0xF88CB8
+
+#define mmTPC6_QM_IND_GW_APB_STATUS 0xF88CBC
+
+#define mmTPC6_QM_GLBL_ERR_ADDR_LO 0xF88CD0
+
+#define mmTPC6_QM_GLBL_ERR_ADDR_HI 0xF88CD4
+
+#define mmTPC6_QM_GLBL_ERR_WDATA 0xF88CD8
+
+#define mmTPC6_QM_GLBL_MEM_INIT_BUSY 0xF88D00
+
+#endif /* ASIC_REG_TPC6_QM_REGS_H_ */
diff --git a/drivers/accel/habanalabs/include/gaudi/asic_reg/tpc7_cfg_regs.h b/drivers/accel/habanalabs/include/gaudi/asic_reg/tpc7_cfg_regs.h
new file mode 100644
index 0000000000..1887b10e58
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi/asic_reg/tpc7_cfg_regs.h
@@ -0,0 +1,1226 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2016-2018 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ ** DO NOT EDIT BELOW **
+ ************************************/
+
+#ifndef ASIC_REG_TPC7_CFG_REGS_H_
+#define ASIC_REG_TPC7_CFG_REGS_H_
+
+/*
+ *****************************************
+ * TPC7_CFG (Prototype: TPC)
+ *****************************************
+ */
+
+#define mmTPC7_CFG_KERNEL_TENSOR_0_BASE_ADDR_LOW 0xFC6400
+
+#define mmTPC7_CFG_KERNEL_TENSOR_0_BASE_ADDR_HIGH 0xFC6404
+
+#define mmTPC7_CFG_KERNEL_TENSOR_0_PADDING_VALUE 0xFC6408
+
+#define mmTPC7_CFG_KERNEL_TENSOR_0_TENSOR_CONFIG 0xFC640C
+
+#define mmTPC7_CFG_KERNEL_TENSOR_0_DIM_0_SIZE 0xFC6410
+
+#define mmTPC7_CFG_KERNEL_TENSOR_0_DIM_0_STRIDE 0xFC6414
+
+#define mmTPC7_CFG_KERNEL_TENSOR_0_DIM_1_SIZE 0xFC6418
+
+#define mmTPC7_CFG_KERNEL_TENSOR_0_DIM_1_STRIDE 0xFC641C
+
+#define mmTPC7_CFG_KERNEL_TENSOR_0_DIM_2_SIZE 0xFC6420
+
+#define mmTPC7_CFG_KERNEL_TENSOR_0_DIM_2_STRIDE 0xFC6424
+
+#define mmTPC7_CFG_KERNEL_TENSOR_0_DIM_3_SIZE 0xFC6428
+
+#define mmTPC7_CFG_KERNEL_TENSOR_0_DIM_3_STRIDE 0xFC642C
+
+#define mmTPC7_CFG_KERNEL_TENSOR_0_DIM_4_SIZE 0xFC6430
+
+#define mmTPC7_CFG_KERNEL_TENSOR_0_DIM_4_STRIDE 0xFC6434
+
+#define mmTPC7_CFG_KERNEL_TENSOR_1_BASE_ADDR_LOW 0xFC6438
+
+#define mmTPC7_CFG_KERNEL_TENSOR_1_BASE_ADDR_HIGH 0xFC643C
+
+#define mmTPC7_CFG_KERNEL_TENSOR_1_PADDING_VALUE 0xFC6440
+
+#define mmTPC7_CFG_KERNEL_TENSOR_1_TENSOR_CONFIG 0xFC6444
+
+#define mmTPC7_CFG_KERNEL_TENSOR_1_DIM_0_SIZE 0xFC6448
+
+#define mmTPC7_CFG_KERNEL_TENSOR_1_DIM_0_STRIDE 0xFC644C
+
+#define mmTPC7_CFG_KERNEL_TENSOR_1_DIM_1_SIZE 0xFC6450
+
+#define mmTPC7_CFG_KERNEL_TENSOR_1_DIM_1_STRIDE 0xFC6454
+
+#define mmTPC7_CFG_KERNEL_TENSOR_1_DIM_2_SIZE 0xFC6458
+
+#define mmTPC7_CFG_KERNEL_TENSOR_1_DIM_2_STRIDE 0xFC645C
+
+#define mmTPC7_CFG_KERNEL_TENSOR_1_DIM_3_SIZE 0xFC6460
+
+#define mmTPC7_CFG_KERNEL_TENSOR_1_DIM_3_STRIDE 0xFC6464
+
+#define mmTPC7_CFG_KERNEL_TENSOR_1_DIM_4_SIZE 0xFC6468
+
+#define mmTPC7_CFG_KERNEL_TENSOR_1_DIM_4_STRIDE 0xFC646C
+
+#define mmTPC7_CFG_KERNEL_TENSOR_2_BASE_ADDR_LOW 0xFC6470
+
+#define mmTPC7_CFG_KERNEL_TENSOR_2_BASE_ADDR_HIGH 0xFC6474
+
+#define mmTPC7_CFG_KERNEL_TENSOR_2_PADDING_VALUE 0xFC6478
+
+#define mmTPC7_CFG_KERNEL_TENSOR_2_TENSOR_CONFIG 0xFC647C
+
+#define mmTPC7_CFG_KERNEL_TENSOR_2_DIM_0_SIZE 0xFC6480
+
+#define mmTPC7_CFG_KERNEL_TENSOR_2_DIM_0_STRIDE 0xFC6484
+
+#define mmTPC7_CFG_KERNEL_TENSOR_2_DIM_1_SIZE 0xFC6488
+
+#define mmTPC7_CFG_KERNEL_TENSOR_2_DIM_1_STRIDE 0xFC648C
+
+#define mmTPC7_CFG_KERNEL_TENSOR_2_DIM_2_SIZE 0xFC6490
+
+#define mmTPC7_CFG_KERNEL_TENSOR_2_DIM_2_STRIDE 0xFC6494
+
+#define mmTPC7_CFG_KERNEL_TENSOR_2_DIM_3_SIZE 0xFC6498
+
+#define mmTPC7_CFG_KERNEL_TENSOR_2_DIM_3_STRIDE 0xFC649C
+
+#define mmTPC7_CFG_KERNEL_TENSOR_2_DIM_4_SIZE 0xFC64A0
+
+#define mmTPC7_CFG_KERNEL_TENSOR_2_DIM_4_STRIDE 0xFC64A4
+
+#define mmTPC7_CFG_KERNEL_TENSOR_3_BASE_ADDR_LOW 0xFC64A8
+
+#define mmTPC7_CFG_KERNEL_TENSOR_3_BASE_ADDR_HIGH 0xFC64AC
+
+#define mmTPC7_CFG_KERNEL_TENSOR_3_PADDING_VALUE 0xFC64B0
+
+#define mmTPC7_CFG_KERNEL_TENSOR_3_TENSOR_CONFIG 0xFC64B4
+
+#define mmTPC7_CFG_KERNEL_TENSOR_3_DIM_0_SIZE 0xFC64B8
+
+#define mmTPC7_CFG_KERNEL_TENSOR_3_DIM_0_STRIDE 0xFC64BC
+
+#define mmTPC7_CFG_KERNEL_TENSOR_3_DIM_1_SIZE 0xFC64C0
+
+#define mmTPC7_CFG_KERNEL_TENSOR_3_DIM_1_STRIDE 0xFC64C4
+
+#define mmTPC7_CFG_KERNEL_TENSOR_3_DIM_2_SIZE 0xFC64C8
+
+#define mmTPC7_CFG_KERNEL_TENSOR_3_DIM_2_STRIDE 0xFC64CC
+
+#define mmTPC7_CFG_KERNEL_TENSOR_3_DIM_3_SIZE 0xFC64D0
+
+#define mmTPC7_CFG_KERNEL_TENSOR_3_DIM_3_STRIDE 0xFC64D4
+
+#define mmTPC7_CFG_KERNEL_TENSOR_3_DIM_4_SIZE 0xFC64D8
+
+#define mmTPC7_CFG_KERNEL_TENSOR_3_DIM_4_STRIDE 0xFC64DC
+
+#define mmTPC7_CFG_KERNEL_TENSOR_4_BASE_ADDR_LOW 0xFC64E0
+
+#define mmTPC7_CFG_KERNEL_TENSOR_4_BASE_ADDR_HIGH 0xFC64E4
+
+#define mmTPC7_CFG_KERNEL_TENSOR_4_PADDING_VALUE 0xFC64E8
+
+#define mmTPC7_CFG_KERNEL_TENSOR_4_TENSOR_CONFIG 0xFC64EC
+
+#define mmTPC7_CFG_KERNEL_TENSOR_4_DIM_0_SIZE 0xFC64F0
+
+#define mmTPC7_CFG_KERNEL_TENSOR_4_DIM_0_STRIDE 0xFC64F4
+
+#define mmTPC7_CFG_KERNEL_TENSOR_4_DIM_1_SIZE 0xFC64F8
+
+#define mmTPC7_CFG_KERNEL_TENSOR_4_DIM_1_STRIDE 0xFC64FC
+
+#define mmTPC7_CFG_KERNEL_TENSOR_4_DIM_2_SIZE 0xFC6500
+
+#define mmTPC7_CFG_KERNEL_TENSOR_4_DIM_2_STRIDE 0xFC6504
+
+#define mmTPC7_CFG_KERNEL_TENSOR_4_DIM_3_SIZE 0xFC6508
+
+#define mmTPC7_CFG_KERNEL_TENSOR_4_DIM_3_STRIDE 0xFC650C
+
+#define mmTPC7_CFG_KERNEL_TENSOR_4_DIM_4_SIZE 0xFC6510
+
+#define mmTPC7_CFG_KERNEL_TENSOR_4_DIM_4_STRIDE 0xFC6514
+
+#define mmTPC7_CFG_KERNEL_TENSOR_5_BASE_ADDR_LOW 0xFC6518
+
+#define mmTPC7_CFG_KERNEL_TENSOR_5_BASE_ADDR_HIGH 0xFC651C
+
+#define mmTPC7_CFG_KERNEL_TENSOR_5_PADDING_VALUE 0xFC6520
+
+#define mmTPC7_CFG_KERNEL_TENSOR_5_TENSOR_CONFIG 0xFC6524
+
+#define mmTPC7_CFG_KERNEL_TENSOR_5_DIM_0_SIZE 0xFC6528
+
+#define mmTPC7_CFG_KERNEL_TENSOR_5_DIM_0_STRIDE 0xFC652C
+
+#define mmTPC7_CFG_KERNEL_TENSOR_5_DIM_1_SIZE 0xFC6530
+
+#define mmTPC7_CFG_KERNEL_TENSOR_5_DIM_1_STRIDE 0xFC6534
+
+#define mmTPC7_CFG_KERNEL_TENSOR_5_DIM_2_SIZE 0xFC6538
+
+#define mmTPC7_CFG_KERNEL_TENSOR_5_DIM_2_STRIDE 0xFC653C
+
+#define mmTPC7_CFG_KERNEL_TENSOR_5_DIM_3_SIZE 0xFC6540
+
+#define mmTPC7_CFG_KERNEL_TENSOR_5_DIM_3_STRIDE 0xFC6544
+
+#define mmTPC7_CFG_KERNEL_TENSOR_5_DIM_4_SIZE 0xFC6548
+
+#define mmTPC7_CFG_KERNEL_TENSOR_5_DIM_4_STRIDE 0xFC654C
+
+#define mmTPC7_CFG_KERNEL_TENSOR_6_BASE_ADDR_LOW 0xFC6550
+
+#define mmTPC7_CFG_KERNEL_TENSOR_6_BASE_ADDR_HIGH 0xFC6554
+
+#define mmTPC7_CFG_KERNEL_TENSOR_6_PADDING_VALUE 0xFC6558
+
+#define mmTPC7_CFG_KERNEL_TENSOR_6_TENSOR_CONFIG 0xFC655C
+
+#define mmTPC7_CFG_KERNEL_TENSOR_6_DIM_0_SIZE 0xFC6560
+
+#define mmTPC7_CFG_KERNEL_TENSOR_6_DIM_0_STRIDE 0xFC6564
+
+#define mmTPC7_CFG_KERNEL_TENSOR_6_DIM_1_SIZE 0xFC6568
+
+#define mmTPC7_CFG_KERNEL_TENSOR_6_DIM_1_STRIDE 0xFC656C
+
+#define mmTPC7_CFG_KERNEL_TENSOR_6_DIM_2_SIZE 0xFC6570
+
+#define mmTPC7_CFG_KERNEL_TENSOR_6_DIM_2_STRIDE 0xFC6574
+
+#define mmTPC7_CFG_KERNEL_TENSOR_6_DIM_3_SIZE 0xFC6578
+
+#define mmTPC7_CFG_KERNEL_TENSOR_6_DIM_3_STRIDE 0xFC657C
+
+#define mmTPC7_CFG_KERNEL_TENSOR_6_DIM_4_SIZE 0xFC6580
+
+#define mmTPC7_CFG_KERNEL_TENSOR_6_DIM_4_STRIDE 0xFC6584
+
+#define mmTPC7_CFG_KERNEL_TENSOR_7_BASE_ADDR_LOW 0xFC6588
+
+#define mmTPC7_CFG_KERNEL_TENSOR_7_BASE_ADDR_HIGH 0xFC658C
+
+#define mmTPC7_CFG_KERNEL_TENSOR_7_PADDING_VALUE 0xFC6590
+
+#define mmTPC7_CFG_KERNEL_TENSOR_7_TENSOR_CONFIG 0xFC6594
+
+#define mmTPC7_CFG_KERNEL_TENSOR_7_DIM_0_SIZE 0xFC6598
+
+#define mmTPC7_CFG_KERNEL_TENSOR_7_DIM_0_STRIDE 0xFC659C
+
+#define mmTPC7_CFG_KERNEL_TENSOR_7_DIM_1_SIZE 0xFC65A0
+
+#define mmTPC7_CFG_KERNEL_TENSOR_7_DIM_1_STRIDE 0xFC65A4
+
+#define mmTPC7_CFG_KERNEL_TENSOR_7_DIM_2_SIZE 0xFC65A8
+
+#define mmTPC7_CFG_KERNEL_TENSOR_7_DIM_2_STRIDE 0xFC65AC
+
+#define mmTPC7_CFG_KERNEL_TENSOR_7_DIM_3_SIZE 0xFC65B0
+
+#define mmTPC7_CFG_KERNEL_TENSOR_7_DIM_3_STRIDE 0xFC65B4
+
+#define mmTPC7_CFG_KERNEL_TENSOR_7_DIM_4_SIZE 0xFC65B8
+
+#define mmTPC7_CFG_KERNEL_TENSOR_7_DIM_4_STRIDE 0xFC65BC
+
+#define mmTPC7_CFG_KERNEL_TENSOR_8_BASE_ADDR_LOW 0xFC65C0
+
+#define mmTPC7_CFG_KERNEL_TENSOR_8_BASE_ADDR_HIGH 0xFC65C4
+
+#define mmTPC7_CFG_KERNEL_TENSOR_8_PADDING_VALUE 0xFC65C8
+
+#define mmTPC7_CFG_KERNEL_TENSOR_8_TENSOR_CONFIG 0xFC65CC
+
+#define mmTPC7_CFG_KERNEL_TENSOR_8_DIM_0_SIZE 0xFC65D0
+
+#define mmTPC7_CFG_KERNEL_TENSOR_8_DIM_0_STRIDE 0xFC65D4
+
+#define mmTPC7_CFG_KERNEL_TENSOR_8_DIM_1_SIZE 0xFC65D8
+
+#define mmTPC7_CFG_KERNEL_TENSOR_8_DIM_1_STRIDE 0xFC65DC
+
+#define mmTPC7_CFG_KERNEL_TENSOR_8_DIM_2_SIZE 0xFC65E0
+
+#define mmTPC7_CFG_KERNEL_TENSOR_8_DIM_2_STRIDE 0xFC65E4
+
+#define mmTPC7_CFG_KERNEL_TENSOR_8_DIM_3_SIZE 0xFC65E8
+
+#define mmTPC7_CFG_KERNEL_TENSOR_8_DIM_3_STRIDE 0xFC65EC
+
+#define mmTPC7_CFG_KERNEL_TENSOR_8_DIM_4_SIZE 0xFC65F0
+
+#define mmTPC7_CFG_KERNEL_TENSOR_8_DIM_4_STRIDE 0xFC65F4
+
+#define mmTPC7_CFG_KERNEL_TENSOR_9_BASE_ADDR_LOW 0xFC65F8
+
+#define mmTPC7_CFG_KERNEL_TENSOR_9_BASE_ADDR_HIGH 0xFC65FC
+
+#define mmTPC7_CFG_KERNEL_TENSOR_9_PADDING_VALUE 0xFC6600
+
+#define mmTPC7_CFG_KERNEL_TENSOR_9_TENSOR_CONFIG 0xFC6604
+
+#define mmTPC7_CFG_KERNEL_TENSOR_9_DIM_0_SIZE 0xFC6608
+
+#define mmTPC7_CFG_KERNEL_TENSOR_9_DIM_0_STRIDE 0xFC660C
+
+#define mmTPC7_CFG_KERNEL_TENSOR_9_DIM_1_SIZE 0xFC6610
+
+#define mmTPC7_CFG_KERNEL_TENSOR_9_DIM_1_STRIDE 0xFC6614
+
+#define mmTPC7_CFG_KERNEL_TENSOR_9_DIM_2_SIZE 0xFC6618
+
+#define mmTPC7_CFG_KERNEL_TENSOR_9_DIM_2_STRIDE 0xFC661C
+
+#define mmTPC7_CFG_KERNEL_TENSOR_9_DIM_3_SIZE 0xFC6620
+
+#define mmTPC7_CFG_KERNEL_TENSOR_9_DIM_3_STRIDE 0xFC6624
+
+#define mmTPC7_CFG_KERNEL_TENSOR_9_DIM_4_SIZE 0xFC6628
+
+#define mmTPC7_CFG_KERNEL_TENSOR_9_DIM_4_STRIDE 0xFC662C
+
+#define mmTPC7_CFG_KERNEL_TENSOR_10_BASE_ADDR_LOW 0xFC6630
+
+#define mmTPC7_CFG_KERNEL_TENSOR_10_BASE_ADDR_HIGH 0xFC6634
+
+#define mmTPC7_CFG_KERNEL_TENSOR_10_PADDING_VALUE 0xFC6638
+
+#define mmTPC7_CFG_KERNEL_TENSOR_10_TENSOR_CONFIG 0xFC663C
+
+#define mmTPC7_CFG_KERNEL_TENSOR_10_DIM_0_SIZE 0xFC6640
+
+#define mmTPC7_CFG_KERNEL_TENSOR_10_DIM_0_STRIDE 0xFC6644
+
+#define mmTPC7_CFG_KERNEL_TENSOR_10_DIM_1_SIZE 0xFC6648
+
+#define mmTPC7_CFG_KERNEL_TENSOR_10_DIM_1_STRIDE 0xFC664C
+
+#define mmTPC7_CFG_KERNEL_TENSOR_10_DIM_2_SIZE 0xFC6650
+
+#define mmTPC7_CFG_KERNEL_TENSOR_10_DIM_2_STRIDE 0xFC6654
+
+#define mmTPC7_CFG_KERNEL_TENSOR_10_DIM_3_SIZE 0xFC6658
+
+#define mmTPC7_CFG_KERNEL_TENSOR_10_DIM_3_STRIDE 0xFC665C
+
+#define mmTPC7_CFG_KERNEL_TENSOR_10_DIM_4_SIZE 0xFC6660
+
+#define mmTPC7_CFG_KERNEL_TENSOR_10_DIM_4_STRIDE 0xFC6664
+
+#define mmTPC7_CFG_KERNEL_TENSOR_11_BASE_ADDR_LOW 0xFC6668
+
+#define mmTPC7_CFG_KERNEL_TENSOR_11_BASE_ADDR_HIGH 0xFC666C
+
+#define mmTPC7_CFG_KERNEL_TENSOR_11_PADDING_VALUE 0xFC6670
+
+#define mmTPC7_CFG_KERNEL_TENSOR_11_TENSOR_CONFIG 0xFC6674
+
+#define mmTPC7_CFG_KERNEL_TENSOR_11_DIM_0_SIZE 0xFC6678
+
+#define mmTPC7_CFG_KERNEL_TENSOR_11_DIM_0_STRIDE 0xFC667C
+
+#define mmTPC7_CFG_KERNEL_TENSOR_11_DIM_1_SIZE 0xFC6680
+
+#define mmTPC7_CFG_KERNEL_TENSOR_11_DIM_1_STRIDE 0xFC6684
+
+#define mmTPC7_CFG_KERNEL_TENSOR_11_DIM_2_SIZE 0xFC6688
+
+#define mmTPC7_CFG_KERNEL_TENSOR_11_DIM_2_STRIDE 0xFC668C
+
+#define mmTPC7_CFG_KERNEL_TENSOR_11_DIM_3_SIZE 0xFC6690
+
+#define mmTPC7_CFG_KERNEL_TENSOR_11_DIM_3_STRIDE 0xFC6694
+
+#define mmTPC7_CFG_KERNEL_TENSOR_11_DIM_4_SIZE 0xFC6698
+
+#define mmTPC7_CFG_KERNEL_TENSOR_11_DIM_4_STRIDE 0xFC669C
+
+#define mmTPC7_CFG_KERNEL_TENSOR_12_BASE_ADDR_LOW 0xFC66A0
+
+#define mmTPC7_CFG_KERNEL_TENSOR_12_BASE_ADDR_HIGH 0xFC66A4
+
+#define mmTPC7_CFG_KERNEL_TENSOR_12_PADDING_VALUE 0xFC66A8
+
+#define mmTPC7_CFG_KERNEL_TENSOR_12_TENSOR_CONFIG 0xFC66AC
+
+#define mmTPC7_CFG_KERNEL_TENSOR_12_DIM_0_SIZE 0xFC66B0
+
+#define mmTPC7_CFG_KERNEL_TENSOR_12_DIM_0_STRIDE 0xFC66B4
+
+#define mmTPC7_CFG_KERNEL_TENSOR_12_DIM_1_SIZE 0xFC66B8
+
+#define mmTPC7_CFG_KERNEL_TENSOR_12_DIM_1_STRIDE 0xFC66BC
+
+#define mmTPC7_CFG_KERNEL_TENSOR_12_DIM_2_SIZE 0xFC66C0
+
+#define mmTPC7_CFG_KERNEL_TENSOR_12_DIM_2_STRIDE 0xFC66C4
+
+#define mmTPC7_CFG_KERNEL_TENSOR_12_DIM_3_SIZE 0xFC66C8
+
+#define mmTPC7_CFG_KERNEL_TENSOR_12_DIM_3_STRIDE 0xFC66CC
+
+#define mmTPC7_CFG_KERNEL_TENSOR_12_DIM_4_SIZE 0xFC66D0
+
+#define mmTPC7_CFG_KERNEL_TENSOR_12_DIM_4_STRIDE 0xFC66D4
+
+#define mmTPC7_CFG_KERNEL_TENSOR_13_BASE_ADDR_LOW 0xFC66D8
+
+#define mmTPC7_CFG_KERNEL_TENSOR_13_BASE_ADDR_HIGH 0xFC66DC
+
+#define mmTPC7_CFG_KERNEL_TENSOR_13_PADDING_VALUE 0xFC66E0
+
+#define mmTPC7_CFG_KERNEL_TENSOR_13_TENSOR_CONFIG 0xFC66E4
+
+#define mmTPC7_CFG_KERNEL_TENSOR_13_DIM_0_SIZE 0xFC66E8
+
+#define mmTPC7_CFG_KERNEL_TENSOR_13_DIM_0_STRIDE 0xFC66EC
+
+#define mmTPC7_CFG_KERNEL_TENSOR_13_DIM_1_SIZE 0xFC66F0
+
+#define mmTPC7_CFG_KERNEL_TENSOR_13_DIM_1_STRIDE 0xFC66F4
+
+#define mmTPC7_CFG_KERNEL_TENSOR_13_DIM_2_SIZE 0xFC66F8
+
+#define mmTPC7_CFG_KERNEL_TENSOR_13_DIM_2_STRIDE 0xFC66FC
+
+#define mmTPC7_CFG_KERNEL_TENSOR_13_DIM_3_SIZE 0xFC6700
+
+#define mmTPC7_CFG_KERNEL_TENSOR_13_DIM_3_STRIDE 0xFC6704
+
+#define mmTPC7_CFG_KERNEL_TENSOR_13_DIM_4_SIZE 0xFC6708
+
+#define mmTPC7_CFG_KERNEL_TENSOR_13_DIM_4_STRIDE 0xFC670C
+
+#define mmTPC7_CFG_KERNEL_TENSOR_14_BASE_ADDR_LOW 0xFC6710
+
+#define mmTPC7_CFG_KERNEL_TENSOR_14_BASE_ADDR_HIGH 0xFC6714
+
+#define mmTPC7_CFG_KERNEL_TENSOR_14_PADDING_VALUE 0xFC6718
+
+#define mmTPC7_CFG_KERNEL_TENSOR_14_TENSOR_CONFIG 0xFC671C
+
+#define mmTPC7_CFG_KERNEL_TENSOR_14_DIM_0_SIZE 0xFC6720
+
+#define mmTPC7_CFG_KERNEL_TENSOR_14_DIM_0_STRIDE 0xFC6724
+
+#define mmTPC7_CFG_KERNEL_TENSOR_14_DIM_1_SIZE 0xFC6728
+
+#define mmTPC7_CFG_KERNEL_TENSOR_14_DIM_1_STRIDE 0xFC672C
+
+#define mmTPC7_CFG_KERNEL_TENSOR_14_DIM_2_SIZE 0xFC6730
+
+#define mmTPC7_CFG_KERNEL_TENSOR_14_DIM_2_STRIDE 0xFC6734
+
+#define mmTPC7_CFG_KERNEL_TENSOR_14_DIM_3_SIZE 0xFC6738
+
+#define mmTPC7_CFG_KERNEL_TENSOR_14_DIM_3_STRIDE 0xFC673C
+
+#define mmTPC7_CFG_KERNEL_TENSOR_14_DIM_4_SIZE 0xFC6740
+
+#define mmTPC7_CFG_KERNEL_TENSOR_14_DIM_4_STRIDE 0xFC6744
+
+#define mmTPC7_CFG_KERNEL_TENSOR_15_BASE_ADDR_LOW 0xFC6748
+
+#define mmTPC7_CFG_KERNEL_TENSOR_15_BASE_ADDR_HIGH 0xFC674C
+
+#define mmTPC7_CFG_KERNEL_TENSOR_15_PADDING_VALUE 0xFC6750
+
+#define mmTPC7_CFG_KERNEL_TENSOR_15_TENSOR_CONFIG 0xFC6754
+
+#define mmTPC7_CFG_KERNEL_TENSOR_15_DIM_0_SIZE 0xFC6758
+
+#define mmTPC7_CFG_KERNEL_TENSOR_15_DIM_0_STRIDE 0xFC675C
+
+#define mmTPC7_CFG_KERNEL_TENSOR_15_DIM_1_SIZE 0xFC6760
+
+#define mmTPC7_CFG_KERNEL_TENSOR_15_DIM_1_STRIDE 0xFC6764
+
+#define mmTPC7_CFG_KERNEL_TENSOR_15_DIM_2_SIZE 0xFC6768
+
+#define mmTPC7_CFG_KERNEL_TENSOR_15_DIM_2_STRIDE 0xFC676C
+
+#define mmTPC7_CFG_KERNEL_TENSOR_15_DIM_3_SIZE 0xFC6770
+
+#define mmTPC7_CFG_KERNEL_TENSOR_15_DIM_3_STRIDE 0xFC6774
+
+#define mmTPC7_CFG_KERNEL_TENSOR_15_DIM_4_SIZE 0xFC6778
+
+#define mmTPC7_CFG_KERNEL_TENSOR_15_DIM_4_STRIDE 0xFC677C
+
+#define mmTPC7_CFG_KERNEL_SYNC_OBJECT_MESSAGE 0xFC6780
+
+#define mmTPC7_CFG_KERNEL_SYNC_OBJECT_ADDR 0xFC6784
+
+#define mmTPC7_CFG_KERNEL_KERNEL_BASE_ADDRESS_LOW 0xFC6788
+
+#define mmTPC7_CFG_KERNEL_KERNEL_BASE_ADDRESS_HIGH 0xFC678C
+
+#define mmTPC7_CFG_KERNEL_TID_BASE_DIM_0 0xFC6790
+
+#define mmTPC7_CFG_KERNEL_TID_SIZE_DIM_0 0xFC6794
+
+#define mmTPC7_CFG_KERNEL_TID_BASE_DIM_1 0xFC6798
+
+#define mmTPC7_CFG_KERNEL_TID_SIZE_DIM_1 0xFC679C
+
+#define mmTPC7_CFG_KERNEL_TID_BASE_DIM_2 0xFC67A0
+
+#define mmTPC7_CFG_KERNEL_TID_SIZE_DIM_2 0xFC67A4
+
+#define mmTPC7_CFG_KERNEL_TID_BASE_DIM_3 0xFC67A8
+
+#define mmTPC7_CFG_KERNEL_TID_SIZE_DIM_3 0xFC67AC
+
+#define mmTPC7_CFG_KERNEL_TID_BASE_DIM_4 0xFC67B0
+
+#define mmTPC7_CFG_KERNEL_TID_SIZE_DIM_4 0xFC67B4
+
+#define mmTPC7_CFG_KERNEL_KERNEL_CONFIG 0xFC67B8
+
+#define mmTPC7_CFG_KERNEL_KERNEL_ID 0xFC67BC
+
+#define mmTPC7_CFG_KERNEL_SRF_0 0xFC67C0
+
+#define mmTPC7_CFG_KERNEL_SRF_1 0xFC67C4
+
+#define mmTPC7_CFG_KERNEL_SRF_2 0xFC67C8
+
+#define mmTPC7_CFG_KERNEL_SRF_3 0xFC67CC
+
+#define mmTPC7_CFG_KERNEL_SRF_4 0xFC67D0
+
+#define mmTPC7_CFG_KERNEL_SRF_5 0xFC67D4
+
+#define mmTPC7_CFG_KERNEL_SRF_6 0xFC67D8
+
+#define mmTPC7_CFG_KERNEL_SRF_7 0xFC67DC
+
+#define mmTPC7_CFG_KERNEL_SRF_8 0xFC67E0
+
+#define mmTPC7_CFG_KERNEL_SRF_9 0xFC67E4
+
+#define mmTPC7_CFG_KERNEL_SRF_10 0xFC67E8
+
+#define mmTPC7_CFG_KERNEL_SRF_11 0xFC67EC
+
+#define mmTPC7_CFG_KERNEL_SRF_12 0xFC67F0
+
+#define mmTPC7_CFG_KERNEL_SRF_13 0xFC67F4
+
+#define mmTPC7_CFG_KERNEL_SRF_14 0xFC67F8
+
+#define mmTPC7_CFG_KERNEL_SRF_15 0xFC67FC
+
+#define mmTPC7_CFG_KERNEL_SRF_16 0xFC6800
+
+#define mmTPC7_CFG_KERNEL_SRF_17 0xFC6804
+
+#define mmTPC7_CFG_KERNEL_SRF_18 0xFC6808
+
+#define mmTPC7_CFG_KERNEL_SRF_19 0xFC680C
+
+#define mmTPC7_CFG_KERNEL_SRF_20 0xFC6810
+
+#define mmTPC7_CFG_KERNEL_SRF_21 0xFC6814
+
+#define mmTPC7_CFG_KERNEL_SRF_22 0xFC6818
+
+#define mmTPC7_CFG_KERNEL_SRF_23 0xFC681C
+
+#define mmTPC7_CFG_KERNEL_SRF_24 0xFC6820
+
+#define mmTPC7_CFG_KERNEL_SRF_25 0xFC6824
+
+#define mmTPC7_CFG_KERNEL_SRF_26 0xFC6828
+
+#define mmTPC7_CFG_KERNEL_SRF_27 0xFC682C
+
+#define mmTPC7_CFG_KERNEL_SRF_28 0xFC6830
+
+#define mmTPC7_CFG_KERNEL_SRF_29 0xFC6834
+
+#define mmTPC7_CFG_KERNEL_SRF_30 0xFC6838
+
+#define mmTPC7_CFG_KERNEL_SRF_31 0xFC683C
+
+#define mmTPC7_CFG_ROUND_CSR 0xFC68FC
+
+#define mmTPC7_CFG_PROT 0xFC6900
+
+#define mmTPC7_CFG_SEMAPHORE 0xFC6908
+
+#define mmTPC7_CFG_VFLAGS 0xFC690C
+
+#define mmTPC7_CFG_SFLAGS 0xFC6910
+
+#define mmTPC7_CFG_LFSR_POLYNOM 0xFC6918
+
+#define mmTPC7_CFG_STATUS 0xFC691C
+
+#define mmTPC7_CFG_CFG_BASE_ADDRESS_HIGH 0xFC6920
+
+#define mmTPC7_CFG_CFG_SUBTRACT_VALUE 0xFC6924
+
+#define mmTPC7_CFG_SM_BASE_ADDRESS_HIGH 0xFC692C
+
+#define mmTPC7_CFG_TPC_CMD 0xFC6930
+
+#define mmTPC7_CFG_TPC_EXECUTE 0xFC6938
+
+#define mmTPC7_CFG_TPC_STALL 0xFC693C
+
+#define mmTPC7_CFG_ICACHE_BASE_ADDERESS_LOW 0xFC6940
+
+#define mmTPC7_CFG_ICACHE_BASE_ADDERESS_HIGH 0xFC6944
+
+#define mmTPC7_CFG_RD_RATE_LIMIT 0xFC6948
+
+#define mmTPC7_CFG_WR_RATE_LIMIT 0xFC6950
+
+#define mmTPC7_CFG_MSS_CONFIG 0xFC6954
+
+#define mmTPC7_CFG_TPC_INTR_CAUSE 0xFC6958
+
+#define mmTPC7_CFG_TPC_INTR_MASK 0xFC695C
+
+#define mmTPC7_CFG_WQ_CREDITS 0xFC6960
+
+#define mmTPC7_CFG_ARUSER_LO 0xFC6964
+
+#define mmTPC7_CFG_ARUSER_HI 0xFC6968
+
+#define mmTPC7_CFG_AWUSER_LO 0xFC696C
+
+#define mmTPC7_CFG_AWUSER_HI 0xFC6970
+
+#define mmTPC7_CFG_OPCODE_EXEC 0xFC6974
+
+#define mmTPC7_CFG_LUT_FUNC32_BASE_ADDR_LO 0xFC6978
+
+#define mmTPC7_CFG_LUT_FUNC32_BASE_ADDR_HI 0xFC697C
+
+#define mmTPC7_CFG_LUT_FUNC64_BASE_ADDR_LO 0xFC6980
+
+#define mmTPC7_CFG_LUT_FUNC64_BASE_ADDR_HI 0xFC6984
+
+#define mmTPC7_CFG_LUT_FUNC128_BASE_ADDR_LO 0xFC6988
+
+#define mmTPC7_CFG_LUT_FUNC128_BASE_ADDR_HI 0xFC698C
+
+#define mmTPC7_CFG_LUT_FUNC256_BASE_ADDR_LO 0xFC6990
+
+#define mmTPC7_CFG_LUT_FUNC256_BASE_ADDR_HI 0xFC6994
+
+#define mmTPC7_CFG_TSB_CFG_MAX_SIZE 0xFC6998
+
+#define mmTPC7_CFG_TSB_CFG 0xFC699C
+
+#define mmTPC7_CFG_DBGMEM_ADD 0xFC69A0
+
+#define mmTPC7_CFG_DBGMEM_DATA_WR 0xFC69A4
+
+#define mmTPC7_CFG_DBGMEM_DATA_RD 0xFC69A8
+
+#define mmTPC7_CFG_DBGMEM_CTRL 0xFC69AC
+
+#define mmTPC7_CFG_DBGMEM_RC 0xFC69B0
+
+#define mmTPC7_CFG_TSB_INFLIGHT_CNTR 0xFC69B4
+
+#define mmTPC7_CFG_WQ_INFLIGHT_CNTR 0xFC69B8
+
+#define mmTPC7_CFG_WQ_LBW_TOTAL_CNTR 0xFC69BC
+
+#define mmTPC7_CFG_WQ_HBW_TOTAL_CNTR 0xFC69C0
+
+#define mmTPC7_CFG_IRQ_OCCOUPY_CNTR 0xFC69C4
+
+#define mmTPC7_CFG_FUNC_MBIST_CNTRL 0xFC69D0
+
+#define mmTPC7_CFG_FUNC_MBIST_PAT 0xFC69D4
+
+#define mmTPC7_CFG_FUNC_MBIST_MEM_0 0xFC69D8
+
+#define mmTPC7_CFG_FUNC_MBIST_MEM_1 0xFC69DC
+
+#define mmTPC7_CFG_FUNC_MBIST_MEM_2 0xFC69E0
+
+#define mmTPC7_CFG_FUNC_MBIST_MEM_3 0xFC69E4
+
+#define mmTPC7_CFG_FUNC_MBIST_MEM_4 0xFC69E8
+
+#define mmTPC7_CFG_FUNC_MBIST_MEM_5 0xFC69EC
+
+#define mmTPC7_CFG_FUNC_MBIST_MEM_6 0xFC69F0
+
+#define mmTPC7_CFG_FUNC_MBIST_MEM_7 0xFC69F4
+
+#define mmTPC7_CFG_FUNC_MBIST_MEM_8 0xFC69F8
+
+#define mmTPC7_CFG_FUNC_MBIST_MEM_9 0xFC69FC
+
+#define mmTPC7_CFG_QM_TENSOR_0_BASE_ADDR_LOW 0xFC6A00
+
+#define mmTPC7_CFG_QM_TENSOR_0_BASE_ADDR_HIGH 0xFC6A04
+
+#define mmTPC7_CFG_QM_TENSOR_0_PADDING_VALUE 0xFC6A08
+
+#define mmTPC7_CFG_QM_TENSOR_0_TENSOR_CONFIG 0xFC6A0C
+
+#define mmTPC7_CFG_QM_TENSOR_0_DIM_0_SIZE 0xFC6A10
+
+#define mmTPC7_CFG_QM_TENSOR_0_DIM_0_STRIDE 0xFC6A14
+
+#define mmTPC7_CFG_QM_TENSOR_0_DIM_1_SIZE 0xFC6A18
+
+#define mmTPC7_CFG_QM_TENSOR_0_DIM_1_STRIDE 0xFC6A1C
+
+#define mmTPC7_CFG_QM_TENSOR_0_DIM_2_SIZE 0xFC6A20
+
+#define mmTPC7_CFG_QM_TENSOR_0_DIM_2_STRIDE 0xFC6A24
+
+#define mmTPC7_CFG_QM_TENSOR_0_DIM_3_SIZE 0xFC6A28
+
+#define mmTPC7_CFG_QM_TENSOR_0_DIM_3_STRIDE 0xFC6A2C
+
+#define mmTPC7_CFG_QM_TENSOR_0_DIM_4_SIZE 0xFC6A30
+
+#define mmTPC7_CFG_QM_TENSOR_0_DIM_4_STRIDE 0xFC6A34
+
+#define mmTPC7_CFG_QM_TENSOR_1_BASE_ADDR_LOW 0xFC6A38
+
+#define mmTPC7_CFG_QM_TENSOR_1_BASE_ADDR_HIGH 0xFC6A3C
+
+#define mmTPC7_CFG_QM_TENSOR_1_PADDING_VALUE 0xFC6A40
+
+#define mmTPC7_CFG_QM_TENSOR_1_TENSOR_CONFIG 0xFC6A44
+
+#define mmTPC7_CFG_QM_TENSOR_1_DIM_0_SIZE 0xFC6A48
+
+#define mmTPC7_CFG_QM_TENSOR_1_DIM_0_STRIDE 0xFC6A4C
+
+#define mmTPC7_CFG_QM_TENSOR_1_DIM_1_SIZE 0xFC6A50
+
+#define mmTPC7_CFG_QM_TENSOR_1_DIM_1_STRIDE 0xFC6A54
+
+#define mmTPC7_CFG_QM_TENSOR_1_DIM_2_SIZE 0xFC6A58
+
+#define mmTPC7_CFG_QM_TENSOR_1_DIM_2_STRIDE 0xFC6A5C
+
+#define mmTPC7_CFG_QM_TENSOR_1_DIM_3_SIZE 0xFC6A60
+
+#define mmTPC7_CFG_QM_TENSOR_1_DIM_3_STRIDE 0xFC6A64
+
+#define mmTPC7_CFG_QM_TENSOR_1_DIM_4_SIZE 0xFC6A68
+
+#define mmTPC7_CFG_QM_TENSOR_1_DIM_4_STRIDE 0xFC6A6C
+
+#define mmTPC7_CFG_QM_TENSOR_2_BASE_ADDR_LOW 0xFC6A70
+
+#define mmTPC7_CFG_QM_TENSOR_2_BASE_ADDR_HIGH 0xFC6A74
+
+#define mmTPC7_CFG_QM_TENSOR_2_PADDING_VALUE 0xFC6A78
+
+#define mmTPC7_CFG_QM_TENSOR_2_TENSOR_CONFIG 0xFC6A7C
+
+#define mmTPC7_CFG_QM_TENSOR_2_DIM_0_SIZE 0xFC6A80
+
+#define mmTPC7_CFG_QM_TENSOR_2_DIM_0_STRIDE 0xFC6A84
+
+#define mmTPC7_CFG_QM_TENSOR_2_DIM_1_SIZE 0xFC6A88
+
+#define mmTPC7_CFG_QM_TENSOR_2_DIM_1_STRIDE 0xFC6A8C
+
+#define mmTPC7_CFG_QM_TENSOR_2_DIM_2_SIZE 0xFC6A90
+
+#define mmTPC7_CFG_QM_TENSOR_2_DIM_2_STRIDE 0xFC6A94
+
+#define mmTPC7_CFG_QM_TENSOR_2_DIM_3_SIZE 0xFC6A98
+
+#define mmTPC7_CFG_QM_TENSOR_2_DIM_3_STRIDE 0xFC6A9C
+
+#define mmTPC7_CFG_QM_TENSOR_2_DIM_4_SIZE 0xFC6AA0
+
+#define mmTPC7_CFG_QM_TENSOR_2_DIM_4_STRIDE 0xFC6AA4
+
+#define mmTPC7_CFG_QM_TENSOR_3_BASE_ADDR_LOW 0xFC6AA8
+
+#define mmTPC7_CFG_QM_TENSOR_3_BASE_ADDR_HIGH 0xFC6AAC
+
+#define mmTPC7_CFG_QM_TENSOR_3_PADDING_VALUE 0xFC6AB0
+
+#define mmTPC7_CFG_QM_TENSOR_3_TENSOR_CONFIG 0xFC6AB4
+
+#define mmTPC7_CFG_QM_TENSOR_3_DIM_0_SIZE 0xFC6AB8
+
+#define mmTPC7_CFG_QM_TENSOR_3_DIM_0_STRIDE 0xFC6ABC
+
+#define mmTPC7_CFG_QM_TENSOR_3_DIM_1_SIZE 0xFC6AC0
+
+#define mmTPC7_CFG_QM_TENSOR_3_DIM_1_STRIDE 0xFC6AC4
+
+#define mmTPC7_CFG_QM_TENSOR_3_DIM_2_SIZE 0xFC6AC8
+
+#define mmTPC7_CFG_QM_TENSOR_3_DIM_2_STRIDE 0xFC6ACC
+
+#define mmTPC7_CFG_QM_TENSOR_3_DIM_3_SIZE 0xFC6AD0
+
+#define mmTPC7_CFG_QM_TENSOR_3_DIM_3_STRIDE 0xFC6AD4
+
+#define mmTPC7_CFG_QM_TENSOR_3_DIM_4_SIZE 0xFC6AD8
+
+#define mmTPC7_CFG_QM_TENSOR_3_DIM_4_STRIDE 0xFC6ADC
+
+#define mmTPC7_CFG_QM_TENSOR_4_BASE_ADDR_LOW 0xFC6AE0
+
+#define mmTPC7_CFG_QM_TENSOR_4_BASE_ADDR_HIGH 0xFC6AE4
+
+#define mmTPC7_CFG_QM_TENSOR_4_PADDING_VALUE 0xFC6AE8
+
+#define mmTPC7_CFG_QM_TENSOR_4_TENSOR_CONFIG 0xFC6AEC
+
+#define mmTPC7_CFG_QM_TENSOR_4_DIM_0_SIZE 0xFC6AF0
+
+#define mmTPC7_CFG_QM_TENSOR_4_DIM_0_STRIDE 0xFC6AF4
+
+#define mmTPC7_CFG_QM_TENSOR_4_DIM_1_SIZE 0xFC6AF8
+
+#define mmTPC7_CFG_QM_TENSOR_4_DIM_1_STRIDE 0xFC6AFC
+
+#define mmTPC7_CFG_QM_TENSOR_4_DIM_2_SIZE 0xFC6B00
+
+#define mmTPC7_CFG_QM_TENSOR_4_DIM_2_STRIDE 0xFC6B04
+
+#define mmTPC7_CFG_QM_TENSOR_4_DIM_3_SIZE 0xFC6B08
+
+#define mmTPC7_CFG_QM_TENSOR_4_DIM_3_STRIDE 0xFC6B0C
+
+#define mmTPC7_CFG_QM_TENSOR_4_DIM_4_SIZE 0xFC6B10
+
+#define mmTPC7_CFG_QM_TENSOR_4_DIM_4_STRIDE 0xFC6B14
+
+#define mmTPC7_CFG_QM_TENSOR_5_BASE_ADDR_LOW 0xFC6B18
+
+#define mmTPC7_CFG_QM_TENSOR_5_BASE_ADDR_HIGH 0xFC6B1C
+
+#define mmTPC7_CFG_QM_TENSOR_5_PADDING_VALUE 0xFC6B20
+
+#define mmTPC7_CFG_QM_TENSOR_5_TENSOR_CONFIG 0xFC6B24
+
+#define mmTPC7_CFG_QM_TENSOR_5_DIM_0_SIZE 0xFC6B28
+
+#define mmTPC7_CFG_QM_TENSOR_5_DIM_0_STRIDE 0xFC6B2C
+
+#define mmTPC7_CFG_QM_TENSOR_5_DIM_1_SIZE 0xFC6B30
+
+#define mmTPC7_CFG_QM_TENSOR_5_DIM_1_STRIDE 0xFC6B34
+
+#define mmTPC7_CFG_QM_TENSOR_5_DIM_2_SIZE 0xFC6B38
+
+#define mmTPC7_CFG_QM_TENSOR_5_DIM_2_STRIDE 0xFC6B3C
+
+#define mmTPC7_CFG_QM_TENSOR_5_DIM_3_SIZE 0xFC6B40
+
+#define mmTPC7_CFG_QM_TENSOR_5_DIM_3_STRIDE 0xFC6B44
+
+#define mmTPC7_CFG_QM_TENSOR_5_DIM_4_SIZE 0xFC6B48
+
+#define mmTPC7_CFG_QM_TENSOR_5_DIM_4_STRIDE 0xFC6B4C
+
+#define mmTPC7_CFG_QM_TENSOR_6_BASE_ADDR_LOW 0xFC6B50
+
+#define mmTPC7_CFG_QM_TENSOR_6_BASE_ADDR_HIGH 0xFC6B54
+
+#define mmTPC7_CFG_QM_TENSOR_6_PADDING_VALUE 0xFC6B58
+
+#define mmTPC7_CFG_QM_TENSOR_6_TENSOR_CONFIG 0xFC6B5C
+
+#define mmTPC7_CFG_QM_TENSOR_6_DIM_0_SIZE 0xFC6B60
+
+#define mmTPC7_CFG_QM_TENSOR_6_DIM_0_STRIDE 0xFC6B64
+
+#define mmTPC7_CFG_QM_TENSOR_6_DIM_1_SIZE 0xFC6B68
+
+#define mmTPC7_CFG_QM_TENSOR_6_DIM_1_STRIDE 0xFC6B6C
+
+#define mmTPC7_CFG_QM_TENSOR_6_DIM_2_SIZE 0xFC6B70
+
+#define mmTPC7_CFG_QM_TENSOR_6_DIM_2_STRIDE 0xFC6B74
+
+#define mmTPC7_CFG_QM_TENSOR_6_DIM_3_SIZE 0xFC6B78
+
+#define mmTPC7_CFG_QM_TENSOR_6_DIM_3_STRIDE 0xFC6B7C
+
+#define mmTPC7_CFG_QM_TENSOR_6_DIM_4_SIZE 0xFC6B80
+
+#define mmTPC7_CFG_QM_TENSOR_6_DIM_4_STRIDE 0xFC6B84
+
+#define mmTPC7_CFG_QM_TENSOR_7_BASE_ADDR_LOW 0xFC6B88
+
+#define mmTPC7_CFG_QM_TENSOR_7_BASE_ADDR_HIGH 0xFC6B8C
+
+#define mmTPC7_CFG_QM_TENSOR_7_PADDING_VALUE 0xFC6B90
+
+#define mmTPC7_CFG_QM_TENSOR_7_TENSOR_CONFIG 0xFC6B94
+
+#define mmTPC7_CFG_QM_TENSOR_7_DIM_0_SIZE 0xFC6B98
+
+#define mmTPC7_CFG_QM_TENSOR_7_DIM_0_STRIDE 0xFC6B9C
+
+#define mmTPC7_CFG_QM_TENSOR_7_DIM_1_SIZE 0xFC6BA0
+
+#define mmTPC7_CFG_QM_TENSOR_7_DIM_1_STRIDE 0xFC6BA4
+
+#define mmTPC7_CFG_QM_TENSOR_7_DIM_2_SIZE 0xFC6BA8
+
+#define mmTPC7_CFG_QM_TENSOR_7_DIM_2_STRIDE 0xFC6BAC
+
+#define mmTPC7_CFG_QM_TENSOR_7_DIM_3_SIZE 0xFC6BB0
+
+#define mmTPC7_CFG_QM_TENSOR_7_DIM_3_STRIDE 0xFC6BB4
+
+#define mmTPC7_CFG_QM_TENSOR_7_DIM_4_SIZE 0xFC6BB8
+
+#define mmTPC7_CFG_QM_TENSOR_7_DIM_4_STRIDE 0xFC6BBC
+
+#define mmTPC7_CFG_QM_TENSOR_8_BASE_ADDR_LOW 0xFC6BC0
+
+#define mmTPC7_CFG_QM_TENSOR_8_BASE_ADDR_HIGH 0xFC6BC4
+
+#define mmTPC7_CFG_QM_TENSOR_8_PADDING_VALUE 0xFC6BC8
+
+#define mmTPC7_CFG_QM_TENSOR_8_TENSOR_CONFIG 0xFC6BCC
+
+#define mmTPC7_CFG_QM_TENSOR_8_DIM_0_SIZE 0xFC6BD0
+
+#define mmTPC7_CFG_QM_TENSOR_8_DIM_0_STRIDE 0xFC6BD4
+
+#define mmTPC7_CFG_QM_TENSOR_8_DIM_1_SIZE 0xFC6BD8
+
+#define mmTPC7_CFG_QM_TENSOR_8_DIM_1_STRIDE 0xFC6BDC
+
+#define mmTPC7_CFG_QM_TENSOR_8_DIM_2_SIZE 0xFC6BE0
+
+#define mmTPC7_CFG_QM_TENSOR_8_DIM_2_STRIDE 0xFC6BE4
+
+#define mmTPC7_CFG_QM_TENSOR_8_DIM_3_SIZE 0xFC6BE8
+
+#define mmTPC7_CFG_QM_TENSOR_8_DIM_3_STRIDE 0xFC6BEC
+
+#define mmTPC7_CFG_QM_TENSOR_8_DIM_4_SIZE 0xFC6BF0
+
+#define mmTPC7_CFG_QM_TENSOR_8_DIM_4_STRIDE 0xFC6BF4
+
+#define mmTPC7_CFG_QM_TENSOR_9_BASE_ADDR_LOW 0xFC6BF8
+
+#define mmTPC7_CFG_QM_TENSOR_9_BASE_ADDR_HIGH 0xFC6BFC
+
+#define mmTPC7_CFG_QM_TENSOR_9_PADDING_VALUE 0xFC6C00
+
+#define mmTPC7_CFG_QM_TENSOR_9_TENSOR_CONFIG 0xFC6C04
+
+#define mmTPC7_CFG_QM_TENSOR_9_DIM_0_SIZE 0xFC6C08
+
+#define mmTPC7_CFG_QM_TENSOR_9_DIM_0_STRIDE 0xFC6C0C
+
+#define mmTPC7_CFG_QM_TENSOR_9_DIM_1_SIZE 0xFC6C10
+
+#define mmTPC7_CFG_QM_TENSOR_9_DIM_1_STRIDE 0xFC6C14
+
+#define mmTPC7_CFG_QM_TENSOR_9_DIM_2_SIZE 0xFC6C18
+
+#define mmTPC7_CFG_QM_TENSOR_9_DIM_2_STRIDE 0xFC6C1C
+
+#define mmTPC7_CFG_QM_TENSOR_9_DIM_3_SIZE 0xFC6C20
+
+#define mmTPC7_CFG_QM_TENSOR_9_DIM_3_STRIDE 0xFC6C24
+
+#define mmTPC7_CFG_QM_TENSOR_9_DIM_4_SIZE 0xFC6C28
+
+#define mmTPC7_CFG_QM_TENSOR_9_DIM_4_STRIDE 0xFC6C2C
+
+#define mmTPC7_CFG_QM_TENSOR_10_BASE_ADDR_LOW 0xFC6C30
+
+#define mmTPC7_CFG_QM_TENSOR_10_BASE_ADDR_HIGH 0xFC6C34
+
+#define mmTPC7_CFG_QM_TENSOR_10_PADDING_VALUE 0xFC6C38
+
+#define mmTPC7_CFG_QM_TENSOR_10_TENSOR_CONFIG 0xFC6C3C
+
+#define mmTPC7_CFG_QM_TENSOR_10_DIM_0_SIZE 0xFC6C40
+
+#define mmTPC7_CFG_QM_TENSOR_10_DIM_0_STRIDE 0xFC6C44
+
+#define mmTPC7_CFG_QM_TENSOR_10_DIM_1_SIZE 0xFC6C48
+
+#define mmTPC7_CFG_QM_TENSOR_10_DIM_1_STRIDE 0xFC6C4C
+
+#define mmTPC7_CFG_QM_TENSOR_10_DIM_2_SIZE 0xFC6C50
+
+#define mmTPC7_CFG_QM_TENSOR_10_DIM_2_STRIDE 0xFC6C54
+
+#define mmTPC7_CFG_QM_TENSOR_10_DIM_3_SIZE 0xFC6C58
+
+#define mmTPC7_CFG_QM_TENSOR_10_DIM_3_STRIDE 0xFC6C5C
+
+#define mmTPC7_CFG_QM_TENSOR_10_DIM_4_SIZE 0xFC6C60
+
+#define mmTPC7_CFG_QM_TENSOR_10_DIM_4_STRIDE 0xFC6C64
+
+#define mmTPC7_CFG_QM_TENSOR_11_BASE_ADDR_LOW 0xFC6C68
+
+#define mmTPC7_CFG_QM_TENSOR_11_BASE_ADDR_HIGH 0xFC6C6C
+
+#define mmTPC7_CFG_QM_TENSOR_11_PADDING_VALUE 0xFC6C70
+
+#define mmTPC7_CFG_QM_TENSOR_11_TENSOR_CONFIG 0xFC6C74
+
+#define mmTPC7_CFG_QM_TENSOR_11_DIM_0_SIZE 0xFC6C78
+
+#define mmTPC7_CFG_QM_TENSOR_11_DIM_0_STRIDE 0xFC6C7C
+
+#define mmTPC7_CFG_QM_TENSOR_11_DIM_1_SIZE 0xFC6C80
+
+#define mmTPC7_CFG_QM_TENSOR_11_DIM_1_STRIDE 0xFC6C84
+
+#define mmTPC7_CFG_QM_TENSOR_11_DIM_2_SIZE 0xFC6C88
+
+#define mmTPC7_CFG_QM_TENSOR_11_DIM_2_STRIDE 0xFC6C8C
+
+#define mmTPC7_CFG_QM_TENSOR_11_DIM_3_SIZE 0xFC6C90
+
+#define mmTPC7_CFG_QM_TENSOR_11_DIM_3_STRIDE 0xFC6C94
+
+#define mmTPC7_CFG_QM_TENSOR_11_DIM_4_SIZE 0xFC6C98
+
+#define mmTPC7_CFG_QM_TENSOR_11_DIM_4_STRIDE 0xFC6C9C
+
+#define mmTPC7_CFG_QM_TENSOR_12_BASE_ADDR_LOW 0xFC6CA0
+
+#define mmTPC7_CFG_QM_TENSOR_12_BASE_ADDR_HIGH 0xFC6CA4
+
+#define mmTPC7_CFG_QM_TENSOR_12_PADDING_VALUE 0xFC6CA8
+
+#define mmTPC7_CFG_QM_TENSOR_12_TENSOR_CONFIG 0xFC6CAC
+
+#define mmTPC7_CFG_QM_TENSOR_12_DIM_0_SIZE 0xFC6CB0
+
+#define mmTPC7_CFG_QM_TENSOR_12_DIM_0_STRIDE 0xFC6CB4
+
+#define mmTPC7_CFG_QM_TENSOR_12_DIM_1_SIZE 0xFC6CB8
+
+#define mmTPC7_CFG_QM_TENSOR_12_DIM_1_STRIDE 0xFC6CBC
+
+#define mmTPC7_CFG_QM_TENSOR_12_DIM_2_SIZE 0xFC6CC0
+
+#define mmTPC7_CFG_QM_TENSOR_12_DIM_2_STRIDE 0xFC6CC4
+
+#define mmTPC7_CFG_QM_TENSOR_12_DIM_3_SIZE 0xFC6CC8
+
+#define mmTPC7_CFG_QM_TENSOR_12_DIM_3_STRIDE 0xFC6CCC
+
+#define mmTPC7_CFG_QM_TENSOR_12_DIM_4_SIZE 0xFC6CD0
+
+#define mmTPC7_CFG_QM_TENSOR_12_DIM_4_STRIDE 0xFC6CD4
+
+#define mmTPC7_CFG_QM_TENSOR_13_BASE_ADDR_LOW 0xFC6CD8
+
+#define mmTPC7_CFG_QM_TENSOR_13_BASE_ADDR_HIGH 0xFC6CDC
+
+#define mmTPC7_CFG_QM_TENSOR_13_PADDING_VALUE 0xFC6CE0
+
+#define mmTPC7_CFG_QM_TENSOR_13_TENSOR_CONFIG 0xFC6CE4
+
+#define mmTPC7_CFG_QM_TENSOR_13_DIM_0_SIZE 0xFC6CE8
+
+#define mmTPC7_CFG_QM_TENSOR_13_DIM_0_STRIDE 0xFC6CEC
+
+#define mmTPC7_CFG_QM_TENSOR_13_DIM_1_SIZE 0xFC6CF0
+
+#define mmTPC7_CFG_QM_TENSOR_13_DIM_1_STRIDE 0xFC6CF4
+
+#define mmTPC7_CFG_QM_TENSOR_13_DIM_2_SIZE 0xFC6CF8
+
+#define mmTPC7_CFG_QM_TENSOR_13_DIM_2_STRIDE 0xFC6CFC
+
+#define mmTPC7_CFG_QM_TENSOR_13_DIM_3_SIZE 0xFC6D00
+
+#define mmTPC7_CFG_QM_TENSOR_13_DIM_3_STRIDE 0xFC6D04
+
+#define mmTPC7_CFG_QM_TENSOR_13_DIM_4_SIZE 0xFC6D08
+
+#define mmTPC7_CFG_QM_TENSOR_13_DIM_4_STRIDE 0xFC6D0C
+
+#define mmTPC7_CFG_QM_TENSOR_14_BASE_ADDR_LOW 0xFC6D10
+
+#define mmTPC7_CFG_QM_TENSOR_14_BASE_ADDR_HIGH 0xFC6D14
+
+#define mmTPC7_CFG_QM_TENSOR_14_PADDING_VALUE 0xFC6D18
+
+#define mmTPC7_CFG_QM_TENSOR_14_TENSOR_CONFIG 0xFC6D1C
+
+#define mmTPC7_CFG_QM_TENSOR_14_DIM_0_SIZE 0xFC6D20
+
+#define mmTPC7_CFG_QM_TENSOR_14_DIM_0_STRIDE 0xFC6D24
+
+#define mmTPC7_CFG_QM_TENSOR_14_DIM_1_SIZE 0xFC6D28
+
+#define mmTPC7_CFG_QM_TENSOR_14_DIM_1_STRIDE 0xFC6D2C
+
+#define mmTPC7_CFG_QM_TENSOR_14_DIM_2_SIZE 0xFC6D30
+
+#define mmTPC7_CFG_QM_TENSOR_14_DIM_2_STRIDE 0xFC6D34
+
+#define mmTPC7_CFG_QM_TENSOR_14_DIM_3_SIZE 0xFC6D38
+
+#define mmTPC7_CFG_QM_TENSOR_14_DIM_3_STRIDE 0xFC6D3C
+
+#define mmTPC7_CFG_QM_TENSOR_14_DIM_4_SIZE 0xFC6D40
+
+#define mmTPC7_CFG_QM_TENSOR_14_DIM_4_STRIDE 0xFC6D44
+
+#define mmTPC7_CFG_QM_TENSOR_15_BASE_ADDR_LOW 0xFC6D48
+
+#define mmTPC7_CFG_QM_TENSOR_15_BASE_ADDR_HIGH 0xFC6D4C
+
+#define mmTPC7_CFG_QM_TENSOR_15_PADDING_VALUE 0xFC6D50
+
+#define mmTPC7_CFG_QM_TENSOR_15_TENSOR_CONFIG 0xFC6D54
+
+#define mmTPC7_CFG_QM_TENSOR_15_DIM_0_SIZE 0xFC6D58
+
+#define mmTPC7_CFG_QM_TENSOR_15_DIM_0_STRIDE 0xFC6D5C
+
+#define mmTPC7_CFG_QM_TENSOR_15_DIM_1_SIZE 0xFC6D60
+
+#define mmTPC7_CFG_QM_TENSOR_15_DIM_1_STRIDE 0xFC6D64
+
+#define mmTPC7_CFG_QM_TENSOR_15_DIM_2_SIZE 0xFC6D68
+
+#define mmTPC7_CFG_QM_TENSOR_15_DIM_2_STRIDE 0xFC6D6C
+
+#define mmTPC7_CFG_QM_TENSOR_15_DIM_3_SIZE 0xFC6D70
+
+#define mmTPC7_CFG_QM_TENSOR_15_DIM_3_STRIDE 0xFC6D74
+
+#define mmTPC7_CFG_QM_TENSOR_15_DIM_4_SIZE 0xFC6D78
+
+#define mmTPC7_CFG_QM_TENSOR_15_DIM_4_STRIDE 0xFC6D7C
+
+#define mmTPC7_CFG_QM_SYNC_OBJECT_MESSAGE 0xFC6D80
+
+#define mmTPC7_CFG_QM_SYNC_OBJECT_ADDR 0xFC6D84
+
+#define mmTPC7_CFG_QM_KERNEL_BASE_ADDRESS_LOW 0xFC6D88
+
+#define mmTPC7_CFG_QM_KERNEL_BASE_ADDRESS_HIGH 0xFC6D8C
+
+#define mmTPC7_CFG_QM_TID_BASE_DIM_0 0xFC6D90
+
+#define mmTPC7_CFG_QM_TID_SIZE_DIM_0 0xFC6D94
+
+#define mmTPC7_CFG_QM_TID_BASE_DIM_1 0xFC6D98
+
+#define mmTPC7_CFG_QM_TID_SIZE_DIM_1 0xFC6D9C
+
+#define mmTPC7_CFG_QM_TID_BASE_DIM_2 0xFC6DA0
+
+#define mmTPC7_CFG_QM_TID_SIZE_DIM_2 0xFC6DA4
+
+#define mmTPC7_CFG_QM_TID_BASE_DIM_3 0xFC6DA8
+
+#define mmTPC7_CFG_QM_TID_SIZE_DIM_3 0xFC6DAC
+
+#define mmTPC7_CFG_QM_TID_BASE_DIM_4 0xFC6DB0
+
+#define mmTPC7_CFG_QM_TID_SIZE_DIM_4 0xFC6DB4
+
+#define mmTPC7_CFG_QM_KERNEL_CONFIG 0xFC6DB8
+
+#define mmTPC7_CFG_QM_KERNEL_ID 0xFC6DBC
+
+#define mmTPC7_CFG_QM_SRF_0 0xFC6DC0
+
+#define mmTPC7_CFG_QM_SRF_1 0xFC6DC4
+
+#define mmTPC7_CFG_QM_SRF_2 0xFC6DC8
+
+#define mmTPC7_CFG_QM_SRF_3 0xFC6DCC
+
+#define mmTPC7_CFG_QM_SRF_4 0xFC6DD0
+
+#define mmTPC7_CFG_QM_SRF_5 0xFC6DD4
+
+#define mmTPC7_CFG_QM_SRF_6 0xFC6DD8
+
+#define mmTPC7_CFG_QM_SRF_7 0xFC6DDC
+
+#define mmTPC7_CFG_QM_SRF_8 0xFC6DE0
+
+#define mmTPC7_CFG_QM_SRF_9 0xFC6DE4
+
+#define mmTPC7_CFG_QM_SRF_10 0xFC6DE8
+
+#define mmTPC7_CFG_QM_SRF_11 0xFC6DEC
+
+#define mmTPC7_CFG_QM_SRF_12 0xFC6DF0
+
+#define mmTPC7_CFG_QM_SRF_13 0xFC6DF4
+
+#define mmTPC7_CFG_QM_SRF_14 0xFC6DF8
+
+#define mmTPC7_CFG_QM_SRF_15 0xFC6DFC
+
+#define mmTPC7_CFG_QM_SRF_16 0xFC6E00
+
+#define mmTPC7_CFG_QM_SRF_17 0xFC6E04
+
+#define mmTPC7_CFG_QM_SRF_18 0xFC6E08
+
+#define mmTPC7_CFG_QM_SRF_19 0xFC6E0C
+
+#define mmTPC7_CFG_QM_SRF_20 0xFC6E10
+
+#define mmTPC7_CFG_QM_SRF_21 0xFC6E14
+
+#define mmTPC7_CFG_QM_SRF_22 0xFC6E18
+
+#define mmTPC7_CFG_QM_SRF_23 0xFC6E1C
+
+#define mmTPC7_CFG_QM_SRF_24 0xFC6E20
+
+#define mmTPC7_CFG_QM_SRF_25 0xFC6E24
+
+#define mmTPC7_CFG_QM_SRF_26 0xFC6E28
+
+#define mmTPC7_CFG_QM_SRF_27 0xFC6E2C
+
+#define mmTPC7_CFG_QM_SRF_28 0xFC6E30
+
+#define mmTPC7_CFG_QM_SRF_29 0xFC6E34
+
+#define mmTPC7_CFG_QM_SRF_30 0xFC6E38
+
+#define mmTPC7_CFG_QM_SRF_31 0xFC6E3C
+
+#endif /* ASIC_REG_TPC7_CFG_REGS_H_ */
diff --git a/drivers/accel/habanalabs/include/gaudi/asic_reg/tpc7_qm_regs.h b/drivers/accel/habanalabs/include/gaudi/asic_reg/tpc7_qm_regs.h
new file mode 100644
index 0000000000..5c36c972c0
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi/asic_reg/tpc7_qm_regs.h
@@ -0,0 +1,834 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2016-2018 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ ** DO NOT EDIT BELOW **
+ ************************************/
+
+#ifndef ASIC_REG_TPC7_QM_REGS_H_
+#define ASIC_REG_TPC7_QM_REGS_H_
+
+/*
+ *****************************************
+ * TPC7_QM (Prototype: QMAN)
+ *****************************************
+ */
+
+#define mmTPC7_QM_GLBL_CFG0 0xFC8000
+
+#define mmTPC7_QM_GLBL_CFG1 0xFC8004
+
+#define mmTPC7_QM_GLBL_PROT 0xFC8008
+
+#define mmTPC7_QM_GLBL_ERR_CFG 0xFC800C
+
+#define mmTPC7_QM_GLBL_SECURE_PROPS_0 0xFC8010
+
+#define mmTPC7_QM_GLBL_SECURE_PROPS_1 0xFC8014
+
+#define mmTPC7_QM_GLBL_SECURE_PROPS_2 0xFC8018
+
+#define mmTPC7_QM_GLBL_SECURE_PROPS_3 0xFC801C
+
+#define mmTPC7_QM_GLBL_SECURE_PROPS_4 0xFC8020
+
+#define mmTPC7_QM_GLBL_NON_SECURE_PROPS_0 0xFC8024
+
+#define mmTPC7_QM_GLBL_NON_SECURE_PROPS_1 0xFC8028
+
+#define mmTPC7_QM_GLBL_NON_SECURE_PROPS_2 0xFC802C
+
+#define mmTPC7_QM_GLBL_NON_SECURE_PROPS_3 0xFC8030
+
+#define mmTPC7_QM_GLBL_NON_SECURE_PROPS_4 0xFC8034
+
+#define mmTPC7_QM_GLBL_STS0 0xFC8038
+
+#define mmTPC7_QM_GLBL_STS1_0 0xFC8040
+
+#define mmTPC7_QM_GLBL_STS1_1 0xFC8044
+
+#define mmTPC7_QM_GLBL_STS1_2 0xFC8048
+
+#define mmTPC7_QM_GLBL_STS1_3 0xFC804C
+
+#define mmTPC7_QM_GLBL_STS1_4 0xFC8050
+
+#define mmTPC7_QM_GLBL_MSG_EN_0 0xFC8054
+
+#define mmTPC7_QM_GLBL_MSG_EN_1 0xFC8058
+
+#define mmTPC7_QM_GLBL_MSG_EN_2 0xFC805C
+
+#define mmTPC7_QM_GLBL_MSG_EN_3 0xFC8060
+
+#define mmTPC7_QM_GLBL_MSG_EN_4 0xFC8068
+
+#define mmTPC7_QM_PQ_BASE_LO_0 0xFC8070
+
+#define mmTPC7_QM_PQ_BASE_LO_1 0xFC8074
+
+#define mmTPC7_QM_PQ_BASE_LO_2 0xFC8078
+
+#define mmTPC7_QM_PQ_BASE_LO_3 0xFC807C
+
+#define mmTPC7_QM_PQ_BASE_HI_0 0xFC8080
+
+#define mmTPC7_QM_PQ_BASE_HI_1 0xFC8084
+
+#define mmTPC7_QM_PQ_BASE_HI_2 0xFC8088
+
+#define mmTPC7_QM_PQ_BASE_HI_3 0xFC808C
+
+#define mmTPC7_QM_PQ_SIZE_0 0xFC8090
+
+#define mmTPC7_QM_PQ_SIZE_1 0xFC8094
+
+#define mmTPC7_QM_PQ_SIZE_2 0xFC8098
+
+#define mmTPC7_QM_PQ_SIZE_3 0xFC809C
+
+#define mmTPC7_QM_PQ_PI_0 0xFC80A0
+
+#define mmTPC7_QM_PQ_PI_1 0xFC80A4
+
+#define mmTPC7_QM_PQ_PI_2 0xFC80A8
+
+#define mmTPC7_QM_PQ_PI_3 0xFC80AC
+
+#define mmTPC7_QM_PQ_CI_0 0xFC80B0
+
+#define mmTPC7_QM_PQ_CI_1 0xFC80B4
+
+#define mmTPC7_QM_PQ_CI_2 0xFC80B8
+
+#define mmTPC7_QM_PQ_CI_3 0xFC80BC
+
+#define mmTPC7_QM_PQ_CFG0_0 0xFC80C0
+
+#define mmTPC7_QM_PQ_CFG0_1 0xFC80C4
+
+#define mmTPC7_QM_PQ_CFG0_2 0xFC80C8
+
+#define mmTPC7_QM_PQ_CFG0_3 0xFC80CC
+
+#define mmTPC7_QM_PQ_CFG1_0 0xFC80D0
+
+#define mmTPC7_QM_PQ_CFG1_1 0xFC80D4
+
+#define mmTPC7_QM_PQ_CFG1_2 0xFC80D8
+
+#define mmTPC7_QM_PQ_CFG1_3 0xFC80DC
+
+#define mmTPC7_QM_PQ_ARUSER_31_11_0 0xFC80E0
+
+#define mmTPC7_QM_PQ_ARUSER_31_11_1 0xFC80E4
+
+#define mmTPC7_QM_PQ_ARUSER_31_11_2 0xFC80E8
+
+#define mmTPC7_QM_PQ_ARUSER_31_11_3 0xFC80EC
+
+#define mmTPC7_QM_PQ_STS0_0 0xFC80F0
+
+#define mmTPC7_QM_PQ_STS0_1 0xFC80F4
+
+#define mmTPC7_QM_PQ_STS0_2 0xFC80F8
+
+#define mmTPC7_QM_PQ_STS0_3 0xFC80FC
+
+#define mmTPC7_QM_PQ_STS1_0 0xFC8100
+
+#define mmTPC7_QM_PQ_STS1_1 0xFC8104
+
+#define mmTPC7_QM_PQ_STS1_2 0xFC8108
+
+#define mmTPC7_QM_PQ_STS1_3 0xFC810C
+
+#define mmTPC7_QM_CQ_CFG0_0 0xFC8110
+
+#define mmTPC7_QM_CQ_CFG0_1 0xFC8114
+
+#define mmTPC7_QM_CQ_CFG0_2 0xFC8118
+
+#define mmTPC7_QM_CQ_CFG0_3 0xFC811C
+
+#define mmTPC7_QM_CQ_CFG0_4 0xFC8120
+
+#define mmTPC7_QM_CQ_CFG1_0 0xFC8124
+
+#define mmTPC7_QM_CQ_CFG1_1 0xFC8128
+
+#define mmTPC7_QM_CQ_CFG1_2 0xFC812C
+
+#define mmTPC7_QM_CQ_CFG1_3 0xFC8130
+
+#define mmTPC7_QM_CQ_CFG1_4 0xFC8134
+
+#define mmTPC7_QM_CQ_ARUSER_31_11_0 0xFC8138
+
+#define mmTPC7_QM_CQ_ARUSER_31_11_1 0xFC813C
+
+#define mmTPC7_QM_CQ_ARUSER_31_11_2 0xFC8140
+
+#define mmTPC7_QM_CQ_ARUSER_31_11_3 0xFC8144
+
+#define mmTPC7_QM_CQ_ARUSER_31_11_4 0xFC8148
+
+#define mmTPC7_QM_CQ_STS0_0 0xFC814C
+
+#define mmTPC7_QM_CQ_STS0_1 0xFC8150
+
+#define mmTPC7_QM_CQ_STS0_2 0xFC8154
+
+#define mmTPC7_QM_CQ_STS0_3 0xFC8158
+
+#define mmTPC7_QM_CQ_STS0_4 0xFC815C
+
+#define mmTPC7_QM_CQ_STS1_0 0xFC8160
+
+#define mmTPC7_QM_CQ_STS1_1 0xFC8164
+
+#define mmTPC7_QM_CQ_STS1_2 0xFC8168
+
+#define mmTPC7_QM_CQ_STS1_3 0xFC816C
+
+#define mmTPC7_QM_CQ_STS1_4 0xFC8170
+
+#define mmTPC7_QM_CQ_PTR_LO_0 0xFC8174
+
+#define mmTPC7_QM_CQ_PTR_HI_0 0xFC8178
+
+#define mmTPC7_QM_CQ_TSIZE_0 0xFC817C
+
+#define mmTPC7_QM_CQ_CTL_0 0xFC8180
+
+#define mmTPC7_QM_CQ_PTR_LO_1 0xFC8184
+
+#define mmTPC7_QM_CQ_PTR_HI_1 0xFC8188
+
+#define mmTPC7_QM_CQ_TSIZE_1 0xFC818C
+
+#define mmTPC7_QM_CQ_CTL_1 0xFC8190
+
+#define mmTPC7_QM_CQ_PTR_LO_2 0xFC8194
+
+#define mmTPC7_QM_CQ_PTR_HI_2 0xFC8198
+
+#define mmTPC7_QM_CQ_TSIZE_2 0xFC819C
+
+#define mmTPC7_QM_CQ_CTL_2 0xFC81A0
+
+#define mmTPC7_QM_CQ_PTR_LO_3 0xFC81A4
+
+#define mmTPC7_QM_CQ_PTR_HI_3 0xFC81A8
+
+#define mmTPC7_QM_CQ_TSIZE_3 0xFC81AC
+
+#define mmTPC7_QM_CQ_CTL_3 0xFC81B0
+
+#define mmTPC7_QM_CQ_PTR_LO_4 0xFC81B4
+
+#define mmTPC7_QM_CQ_PTR_HI_4 0xFC81B8
+
+#define mmTPC7_QM_CQ_TSIZE_4 0xFC81BC
+
+#define mmTPC7_QM_CQ_CTL_4 0xFC81C0
+
+#define mmTPC7_QM_CQ_PTR_LO_STS_0 0xFC81C4
+
+#define mmTPC7_QM_CQ_PTR_LO_STS_1 0xFC81C8
+
+#define mmTPC7_QM_CQ_PTR_LO_STS_2 0xFC81CC
+
+#define mmTPC7_QM_CQ_PTR_LO_STS_3 0xFC81D0
+
+#define mmTPC7_QM_CQ_PTR_LO_STS_4 0xFC81D4
+
+#define mmTPC7_QM_CQ_PTR_HI_STS_0 0xFC81D8
+
+#define mmTPC7_QM_CQ_PTR_HI_STS_1 0xFC81DC
+
+#define mmTPC7_QM_CQ_PTR_HI_STS_2 0xFC81E0
+
+#define mmTPC7_QM_CQ_PTR_HI_STS_3 0xFC81E4
+
+#define mmTPC7_QM_CQ_PTR_HI_STS_4 0xFC81E8
+
+#define mmTPC7_QM_CQ_TSIZE_STS_0 0xFC81EC
+
+#define mmTPC7_QM_CQ_TSIZE_STS_1 0xFC81F0
+
+#define mmTPC7_QM_CQ_TSIZE_STS_2 0xFC81F4
+
+#define mmTPC7_QM_CQ_TSIZE_STS_3 0xFC81F8
+
+#define mmTPC7_QM_CQ_TSIZE_STS_4 0xFC81FC
+
+#define mmTPC7_QM_CQ_CTL_STS_0 0xFC8200
+
+#define mmTPC7_QM_CQ_CTL_STS_1 0xFC8204
+
+#define mmTPC7_QM_CQ_CTL_STS_2 0xFC8208
+
+#define mmTPC7_QM_CQ_CTL_STS_3 0xFC820C
+
+#define mmTPC7_QM_CQ_CTL_STS_4 0xFC8210
+
+#define mmTPC7_QM_CQ_IFIFO_CNT_0 0xFC8214
+
+#define mmTPC7_QM_CQ_IFIFO_CNT_1 0xFC8218
+
+#define mmTPC7_QM_CQ_IFIFO_CNT_2 0xFC821C
+
+#define mmTPC7_QM_CQ_IFIFO_CNT_3 0xFC8220
+
+#define mmTPC7_QM_CQ_IFIFO_CNT_4 0xFC8224
+
+#define mmTPC7_QM_CP_MSG_BASE0_ADDR_LO_0 0xFC8228
+
+#define mmTPC7_QM_CP_MSG_BASE0_ADDR_LO_1 0xFC822C
+
+#define mmTPC7_QM_CP_MSG_BASE0_ADDR_LO_2 0xFC8230
+
+#define mmTPC7_QM_CP_MSG_BASE0_ADDR_LO_3 0xFC8234
+
+#define mmTPC7_QM_CP_MSG_BASE0_ADDR_LO_4 0xFC8238
+
+#define mmTPC7_QM_CP_MSG_BASE0_ADDR_HI_0 0xFC823C
+
+#define mmTPC7_QM_CP_MSG_BASE0_ADDR_HI_1 0xFC8240
+
+#define mmTPC7_QM_CP_MSG_BASE0_ADDR_HI_2 0xFC8244
+
+#define mmTPC7_QM_CP_MSG_BASE0_ADDR_HI_3 0xFC8248
+
+#define mmTPC7_QM_CP_MSG_BASE0_ADDR_HI_4 0xFC824C
+
+#define mmTPC7_QM_CP_MSG_BASE1_ADDR_LO_0 0xFC8250
+
+#define mmTPC7_QM_CP_MSG_BASE1_ADDR_LO_1 0xFC8254
+
+#define mmTPC7_QM_CP_MSG_BASE1_ADDR_LO_2 0xFC8258
+
+#define mmTPC7_QM_CP_MSG_BASE1_ADDR_LO_3 0xFC825C
+
+#define mmTPC7_QM_CP_MSG_BASE1_ADDR_LO_4 0xFC8260
+
+#define mmTPC7_QM_CP_MSG_BASE1_ADDR_HI_0 0xFC8264
+
+#define mmTPC7_QM_CP_MSG_BASE1_ADDR_HI_1 0xFC8268
+
+#define mmTPC7_QM_CP_MSG_BASE1_ADDR_HI_2 0xFC826C
+
+#define mmTPC7_QM_CP_MSG_BASE1_ADDR_HI_3 0xFC8270
+
+#define mmTPC7_QM_CP_MSG_BASE1_ADDR_HI_4 0xFC8274
+
+#define mmTPC7_QM_CP_MSG_BASE2_ADDR_LO_0 0xFC8278
+
+#define mmTPC7_QM_CP_MSG_BASE2_ADDR_LO_1 0xFC827C
+
+#define mmTPC7_QM_CP_MSG_BASE2_ADDR_LO_2 0xFC8280
+
+#define mmTPC7_QM_CP_MSG_BASE2_ADDR_LO_3 0xFC8284
+
+#define mmTPC7_QM_CP_MSG_BASE2_ADDR_LO_4 0xFC8288
+
+#define mmTPC7_QM_CP_MSG_BASE2_ADDR_HI_0 0xFC828C
+
+#define mmTPC7_QM_CP_MSG_BASE2_ADDR_HI_1 0xFC8290
+
+#define mmTPC7_QM_CP_MSG_BASE2_ADDR_HI_2 0xFC8294
+
+#define mmTPC7_QM_CP_MSG_BASE2_ADDR_HI_3 0xFC8298
+
+#define mmTPC7_QM_CP_MSG_BASE2_ADDR_HI_4 0xFC829C
+
+#define mmTPC7_QM_CP_MSG_BASE3_ADDR_LO_0 0xFC82A0
+
+#define mmTPC7_QM_CP_MSG_BASE3_ADDR_LO_1 0xFC82A4
+
+#define mmTPC7_QM_CP_MSG_BASE3_ADDR_LO_2 0xFC82A8
+
+#define mmTPC7_QM_CP_MSG_BASE3_ADDR_LO_3 0xFC82AC
+
+#define mmTPC7_QM_CP_MSG_BASE3_ADDR_LO_4 0xFC82B0
+
+#define mmTPC7_QM_CP_MSG_BASE3_ADDR_HI_0 0xFC82B4
+
+#define mmTPC7_QM_CP_MSG_BASE3_ADDR_HI_1 0xFC82B8
+
+#define mmTPC7_QM_CP_MSG_BASE3_ADDR_HI_2 0xFC82BC
+
+#define mmTPC7_QM_CP_MSG_BASE3_ADDR_HI_3 0xFC82C0
+
+#define mmTPC7_QM_CP_MSG_BASE3_ADDR_HI_4 0xFC82C4
+
+#define mmTPC7_QM_CP_LDMA_TSIZE_OFFSET_0 0xFC82C8
+
+#define mmTPC7_QM_CP_LDMA_TSIZE_OFFSET_1 0xFC82CC
+
+#define mmTPC7_QM_CP_LDMA_TSIZE_OFFSET_2 0xFC82D0
+
+#define mmTPC7_QM_CP_LDMA_TSIZE_OFFSET_3 0xFC82D4
+
+#define mmTPC7_QM_CP_LDMA_TSIZE_OFFSET_4 0xFC82D8
+
+#define mmTPC7_QM_CP_LDMA_SRC_BASE_LO_OFFSET_0 0xFC82E0
+
+#define mmTPC7_QM_CP_LDMA_SRC_BASE_LO_OFFSET_1 0xFC82E4
+
+#define mmTPC7_QM_CP_LDMA_SRC_BASE_LO_OFFSET_2 0xFC82E8
+
+#define mmTPC7_QM_CP_LDMA_SRC_BASE_LO_OFFSET_3 0xFC82EC
+
+#define mmTPC7_QM_CP_LDMA_SRC_BASE_LO_OFFSET_4 0xFC82F0
+
+#define mmTPC7_QM_CP_LDMA_DST_BASE_LO_OFFSET_0 0xFC82F4
+
+#define mmTPC7_QM_CP_LDMA_DST_BASE_LO_OFFSET_1 0xFC82F8
+
+#define mmTPC7_QM_CP_LDMA_DST_BASE_LO_OFFSET_2 0xFC82FC
+
+#define mmTPC7_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 0xFC8300
+
+#define mmTPC7_QM_CP_LDMA_DST_BASE_LO_OFFSET_4 0xFC8304
+
+#define mmTPC7_QM_CP_FENCE0_RDATA_0 0xFC8308
+
+#define mmTPC7_QM_CP_FENCE0_RDATA_1 0xFC830C
+
+#define mmTPC7_QM_CP_FENCE0_RDATA_2 0xFC8310
+
+#define mmTPC7_QM_CP_FENCE0_RDATA_3 0xFC8314
+
+#define mmTPC7_QM_CP_FENCE0_RDATA_4 0xFC8318
+
+#define mmTPC7_QM_CP_FENCE1_RDATA_0 0xFC831C
+
+#define mmTPC7_QM_CP_FENCE1_RDATA_1 0xFC8320
+
+#define mmTPC7_QM_CP_FENCE1_RDATA_2 0xFC8324
+
+#define mmTPC7_QM_CP_FENCE1_RDATA_3 0xFC8328
+
+#define mmTPC7_QM_CP_FENCE1_RDATA_4 0xFC832C
+
+#define mmTPC7_QM_CP_FENCE2_RDATA_0 0xFC8330
+
+#define mmTPC7_QM_CP_FENCE2_RDATA_1 0xFC8334
+
+#define mmTPC7_QM_CP_FENCE2_RDATA_2 0xFC8338
+
+#define mmTPC7_QM_CP_FENCE2_RDATA_3 0xFC833C
+
+#define mmTPC7_QM_CP_FENCE2_RDATA_4 0xFC8340
+
+#define mmTPC7_QM_CP_FENCE3_RDATA_0 0xFC8344
+
+#define mmTPC7_QM_CP_FENCE3_RDATA_1 0xFC8348
+
+#define mmTPC7_QM_CP_FENCE3_RDATA_2 0xFC834C
+
+#define mmTPC7_QM_CP_FENCE3_RDATA_3 0xFC8350
+
+#define mmTPC7_QM_CP_FENCE3_RDATA_4 0xFC8354
+
+#define mmTPC7_QM_CP_FENCE0_CNT_0 0xFC8358
+
+#define mmTPC7_QM_CP_FENCE0_CNT_1 0xFC835C
+
+#define mmTPC7_QM_CP_FENCE0_CNT_2 0xFC8360
+
+#define mmTPC7_QM_CP_FENCE0_CNT_3 0xFC8364
+
+#define mmTPC7_QM_CP_FENCE0_CNT_4 0xFC8368
+
+#define mmTPC7_QM_CP_FENCE1_CNT_0 0xFC836C
+
+#define mmTPC7_QM_CP_FENCE1_CNT_1 0xFC8370
+
+#define mmTPC7_QM_CP_FENCE1_CNT_2 0xFC8374
+
+#define mmTPC7_QM_CP_FENCE1_CNT_3 0xFC8378
+
+#define mmTPC7_QM_CP_FENCE1_CNT_4 0xFC837C
+
+#define mmTPC7_QM_CP_FENCE2_CNT_0 0xFC8380
+
+#define mmTPC7_QM_CP_FENCE2_CNT_1 0xFC8384
+
+#define mmTPC7_QM_CP_FENCE2_CNT_2 0xFC8388
+
+#define mmTPC7_QM_CP_FENCE2_CNT_3 0xFC838C
+
+#define mmTPC7_QM_CP_FENCE2_CNT_4 0xFC8390
+
+#define mmTPC7_QM_CP_FENCE3_CNT_0 0xFC8394
+
+#define mmTPC7_QM_CP_FENCE3_CNT_1 0xFC8398
+
+#define mmTPC7_QM_CP_FENCE3_CNT_2 0xFC839C
+
+#define mmTPC7_QM_CP_FENCE3_CNT_3 0xFC83A0
+
+#define mmTPC7_QM_CP_FENCE3_CNT_4 0xFC83A4
+
+#define mmTPC7_QM_CP_STS_0 0xFC83A8
+
+#define mmTPC7_QM_CP_STS_1 0xFC83AC
+
+#define mmTPC7_QM_CP_STS_2 0xFC83B0
+
+#define mmTPC7_QM_CP_STS_3 0xFC83B4
+
+#define mmTPC7_QM_CP_STS_4 0xFC83B8
+
+#define mmTPC7_QM_CP_CURRENT_INST_LO_0 0xFC83BC
+
+#define mmTPC7_QM_CP_CURRENT_INST_LO_1 0xFC83C0
+
+#define mmTPC7_QM_CP_CURRENT_INST_LO_2 0xFC83C4
+
+#define mmTPC7_QM_CP_CURRENT_INST_LO_3 0xFC83C8
+
+#define mmTPC7_QM_CP_CURRENT_INST_LO_4 0xFC83CC
+
+#define mmTPC7_QM_CP_CURRENT_INST_HI_0 0xFC83D0
+
+#define mmTPC7_QM_CP_CURRENT_INST_HI_1 0xFC83D4
+
+#define mmTPC7_QM_CP_CURRENT_INST_HI_2 0xFC83D8
+
+#define mmTPC7_QM_CP_CURRENT_INST_HI_3 0xFC83DC
+
+#define mmTPC7_QM_CP_CURRENT_INST_HI_4 0xFC83E0
+
+#define mmTPC7_QM_CP_BARRIER_CFG_0 0xFC83F4
+
+#define mmTPC7_QM_CP_BARRIER_CFG_1 0xFC83F8
+
+#define mmTPC7_QM_CP_BARRIER_CFG_2 0xFC83FC
+
+#define mmTPC7_QM_CP_BARRIER_CFG_3 0xFC8400
+
+#define mmTPC7_QM_CP_BARRIER_CFG_4 0xFC8404
+
+#define mmTPC7_QM_CP_DBG_0_0 0xFC8408
+
+#define mmTPC7_QM_CP_DBG_0_1 0xFC840C
+
+#define mmTPC7_QM_CP_DBG_0_2 0xFC8410
+
+#define mmTPC7_QM_CP_DBG_0_3 0xFC8414
+
+#define mmTPC7_QM_CP_DBG_0_4 0xFC8418
+
+#define mmTPC7_QM_CP_ARUSER_31_11_0 0xFC841C
+
+#define mmTPC7_QM_CP_ARUSER_31_11_1 0xFC8420
+
+#define mmTPC7_QM_CP_ARUSER_31_11_2 0xFC8424
+
+#define mmTPC7_QM_CP_ARUSER_31_11_3 0xFC8428
+
+#define mmTPC7_QM_CP_ARUSER_31_11_4 0xFC842C
+
+#define mmTPC7_QM_CP_AWUSER_31_11_0 0xFC8430
+
+#define mmTPC7_QM_CP_AWUSER_31_11_1 0xFC8434
+
+#define mmTPC7_QM_CP_AWUSER_31_11_2 0xFC8438
+
+#define mmTPC7_QM_CP_AWUSER_31_11_3 0xFC843C
+
+#define mmTPC7_QM_CP_AWUSER_31_11_4 0xFC8440
+
+#define mmTPC7_QM_ARB_CFG_0 0xFC8A00
+
+#define mmTPC7_QM_ARB_CHOISE_Q_PUSH 0xFC8A04
+
+#define mmTPC7_QM_ARB_WRR_WEIGHT_0 0xFC8A08
+
+#define mmTPC7_QM_ARB_WRR_WEIGHT_1 0xFC8A0C
+
+#define mmTPC7_QM_ARB_WRR_WEIGHT_2 0xFC8A10
+
+#define mmTPC7_QM_ARB_WRR_WEIGHT_3 0xFC8A14
+
+#define mmTPC7_QM_ARB_CFG_1 0xFC8A18
+
+#define mmTPC7_QM_ARB_MST_AVAIL_CRED_0 0xFC8A20
+
+#define mmTPC7_QM_ARB_MST_AVAIL_CRED_1 0xFC8A24
+
+#define mmTPC7_QM_ARB_MST_AVAIL_CRED_2 0xFC8A28
+
+#define mmTPC7_QM_ARB_MST_AVAIL_CRED_3 0xFC8A2C
+
+#define mmTPC7_QM_ARB_MST_AVAIL_CRED_4 0xFC8A30
+
+#define mmTPC7_QM_ARB_MST_AVAIL_CRED_5 0xFC8A34
+
+#define mmTPC7_QM_ARB_MST_AVAIL_CRED_6 0xFC8A38
+
+#define mmTPC7_QM_ARB_MST_AVAIL_CRED_7 0xFC8A3C
+
+#define mmTPC7_QM_ARB_MST_AVAIL_CRED_8 0xFC8A40
+
+#define mmTPC7_QM_ARB_MST_AVAIL_CRED_9 0xFC8A44
+
+#define mmTPC7_QM_ARB_MST_AVAIL_CRED_10 0xFC8A48
+
+#define mmTPC7_QM_ARB_MST_AVAIL_CRED_11 0xFC8A4C
+
+#define mmTPC7_QM_ARB_MST_AVAIL_CRED_12 0xFC8A50
+
+#define mmTPC7_QM_ARB_MST_AVAIL_CRED_13 0xFC8A54
+
+#define mmTPC7_QM_ARB_MST_AVAIL_CRED_14 0xFC8A58
+
+#define mmTPC7_QM_ARB_MST_AVAIL_CRED_15 0xFC8A5C
+
+#define mmTPC7_QM_ARB_MST_AVAIL_CRED_16 0xFC8A60
+
+#define mmTPC7_QM_ARB_MST_AVAIL_CRED_17 0xFC8A64
+
+#define mmTPC7_QM_ARB_MST_AVAIL_CRED_18 0xFC8A68
+
+#define mmTPC7_QM_ARB_MST_AVAIL_CRED_19 0xFC8A6C
+
+#define mmTPC7_QM_ARB_MST_AVAIL_CRED_20 0xFC8A70
+
+#define mmTPC7_QM_ARB_MST_AVAIL_CRED_21 0xFC8A74
+
+#define mmTPC7_QM_ARB_MST_AVAIL_CRED_22 0xFC8A78
+
+#define mmTPC7_QM_ARB_MST_AVAIL_CRED_23 0xFC8A7C
+
+#define mmTPC7_QM_ARB_MST_AVAIL_CRED_24 0xFC8A80
+
+#define mmTPC7_QM_ARB_MST_AVAIL_CRED_25 0xFC8A84
+
+#define mmTPC7_QM_ARB_MST_AVAIL_CRED_26 0xFC8A88
+
+#define mmTPC7_QM_ARB_MST_AVAIL_CRED_27 0xFC8A8C
+
+#define mmTPC7_QM_ARB_MST_AVAIL_CRED_28 0xFC8A90
+
+#define mmTPC7_QM_ARB_MST_AVAIL_CRED_29 0xFC8A94
+
+#define mmTPC7_QM_ARB_MST_AVAIL_CRED_30 0xFC8A98
+
+#define mmTPC7_QM_ARB_MST_AVAIL_CRED_31 0xFC8A9C
+
+#define mmTPC7_QM_ARB_MST_CRED_INC 0xFC8AA0
+
+#define mmTPC7_QM_ARB_MST_CHOISE_PUSH_OFST_0 0xFC8AA4
+
+#define mmTPC7_QM_ARB_MST_CHOISE_PUSH_OFST_1 0xFC8AA8
+
+#define mmTPC7_QM_ARB_MST_CHOISE_PUSH_OFST_2 0xFC8AAC
+
+#define mmTPC7_QM_ARB_MST_CHOISE_PUSH_OFST_3 0xFC8AB0
+
+#define mmTPC7_QM_ARB_MST_CHOISE_PUSH_OFST_4 0xFC8AB4
+
+#define mmTPC7_QM_ARB_MST_CHOISE_PUSH_OFST_5 0xFC8AB8
+
+#define mmTPC7_QM_ARB_MST_CHOISE_PUSH_OFST_6 0xFC8ABC
+
+#define mmTPC7_QM_ARB_MST_CHOISE_PUSH_OFST_7 0xFC8AC0
+
+#define mmTPC7_QM_ARB_MST_CHOISE_PUSH_OFST_8 0xFC8AC4
+
+#define mmTPC7_QM_ARB_MST_CHOISE_PUSH_OFST_9 0xFC8AC8
+
+#define mmTPC7_QM_ARB_MST_CHOISE_PUSH_OFST_10 0xFC8ACC
+
+#define mmTPC7_QM_ARB_MST_CHOISE_PUSH_OFST_11 0xFC8AD0
+
+#define mmTPC7_QM_ARB_MST_CHOISE_PUSH_OFST_12 0xFC8AD4
+
+#define mmTPC7_QM_ARB_MST_CHOISE_PUSH_OFST_13 0xFC8AD8
+
+#define mmTPC7_QM_ARB_MST_CHOISE_PUSH_OFST_14 0xFC8ADC
+
+#define mmTPC7_QM_ARB_MST_CHOISE_PUSH_OFST_15 0xFC8AE0
+
+#define mmTPC7_QM_ARB_MST_CHOISE_PUSH_OFST_16 0xFC8AE4
+
+#define mmTPC7_QM_ARB_MST_CHOISE_PUSH_OFST_17 0xFC8AE8
+
+#define mmTPC7_QM_ARB_MST_CHOISE_PUSH_OFST_18 0xFC8AEC
+
+#define mmTPC7_QM_ARB_MST_CHOISE_PUSH_OFST_19 0xFC8AF0
+
+#define mmTPC7_QM_ARB_MST_CHOISE_PUSH_OFST_20 0xFC8AF4
+
+#define mmTPC7_QM_ARB_MST_CHOISE_PUSH_OFST_21 0xFC8AF8
+
+#define mmTPC7_QM_ARB_MST_CHOISE_PUSH_OFST_22 0xFC8AFC
+
+#define mmTPC7_QM_ARB_MST_CHOISE_PUSH_OFST_23 0xFC8B00
+
+#define mmTPC7_QM_ARB_MST_CHOISE_PUSH_OFST_24 0xFC8B04
+
+#define mmTPC7_QM_ARB_MST_CHOISE_PUSH_OFST_25 0xFC8B08
+
+#define mmTPC7_QM_ARB_MST_CHOISE_PUSH_OFST_26 0xFC8B0C
+
+#define mmTPC7_QM_ARB_MST_CHOISE_PUSH_OFST_27 0xFC8B10
+
+#define mmTPC7_QM_ARB_MST_CHOISE_PUSH_OFST_28 0xFC8B14
+
+#define mmTPC7_QM_ARB_MST_CHOISE_PUSH_OFST_29 0xFC8B18
+
+#define mmTPC7_QM_ARB_MST_CHOISE_PUSH_OFST_30 0xFC8B1C
+
+#define mmTPC7_QM_ARB_MST_CHOISE_PUSH_OFST_31 0xFC8B20
+
+#define mmTPC7_QM_ARB_SLV_MASTER_INC_CRED_OFST 0xFC8B28
+
+#define mmTPC7_QM_ARB_MST_SLAVE_EN 0xFC8B2C
+
+#define mmTPC7_QM_ARB_MST_QUIET_PER 0xFC8B34
+
+#define mmTPC7_QM_ARB_SLV_CHOISE_WDT 0xFC8B38
+
+#define mmTPC7_QM_ARB_SLV_ID 0xFC8B3C
+
+#define mmTPC7_QM_ARB_MSG_MAX_INFLIGHT 0xFC8B44
+
+#define mmTPC7_QM_ARB_MSG_AWUSER_31_11 0xFC8B48
+
+#define mmTPC7_QM_ARB_MSG_AWUSER_SEC_PROP 0xFC8B4C
+
+#define mmTPC7_QM_ARB_MSG_AWUSER_NON_SEC_PROP 0xFC8B50
+
+#define mmTPC7_QM_ARB_BASE_LO 0xFC8B54
+
+#define mmTPC7_QM_ARB_BASE_HI 0xFC8B58
+
+#define mmTPC7_QM_ARB_STATE_STS 0xFC8B80
+
+#define mmTPC7_QM_ARB_CHOISE_FULLNESS_STS 0xFC8B84
+
+#define mmTPC7_QM_ARB_MSG_STS 0xFC8B88
+
+#define mmTPC7_QM_ARB_SLV_CHOISE_Q_HEAD 0xFC8B8C
+
+#define mmTPC7_QM_ARB_ERR_CAUSE 0xFC8B9C
+
+#define mmTPC7_QM_ARB_ERR_MSG_EN 0xFC8BA0
+
+#define mmTPC7_QM_ARB_ERR_STS_DRP 0xFC8BA8
+
+#define mmTPC7_QM_ARB_MST_CRED_STS_0 0xFC8BB0
+
+#define mmTPC7_QM_ARB_MST_CRED_STS_1 0xFC8BB4
+
+#define mmTPC7_QM_ARB_MST_CRED_STS_2 0xFC8BB8
+
+#define mmTPC7_QM_ARB_MST_CRED_STS_3 0xFC8BBC
+
+#define mmTPC7_QM_ARB_MST_CRED_STS_4 0xFC8BC0
+
+#define mmTPC7_QM_ARB_MST_CRED_STS_5 0xFC8BC4
+
+#define mmTPC7_QM_ARB_MST_CRED_STS_6 0xFC8BC8
+
+#define mmTPC7_QM_ARB_MST_CRED_STS_7 0xFC8BCC
+
+#define mmTPC7_QM_ARB_MST_CRED_STS_8 0xFC8BD0
+
+#define mmTPC7_QM_ARB_MST_CRED_STS_9 0xFC8BD4
+
+#define mmTPC7_QM_ARB_MST_CRED_STS_10 0xFC8BD8
+
+#define mmTPC7_QM_ARB_MST_CRED_STS_11 0xFC8BDC
+
+#define mmTPC7_QM_ARB_MST_CRED_STS_12 0xFC8BE0
+
+#define mmTPC7_QM_ARB_MST_CRED_STS_13 0xFC8BE4
+
+#define mmTPC7_QM_ARB_MST_CRED_STS_14 0xFC8BE8
+
+#define mmTPC7_QM_ARB_MST_CRED_STS_15 0xFC8BEC
+
+#define mmTPC7_QM_ARB_MST_CRED_STS_16 0xFC8BF0
+
+#define mmTPC7_QM_ARB_MST_CRED_STS_17 0xFC8BF4
+
+#define mmTPC7_QM_ARB_MST_CRED_STS_18 0xFC8BF8
+
+#define mmTPC7_QM_ARB_MST_CRED_STS_19 0xFC8BFC
+
+#define mmTPC7_QM_ARB_MST_CRED_STS_20 0xFC8C00
+
+#define mmTPC7_QM_ARB_MST_CRED_STS_21 0xFC8C04
+
+#define mmTPC7_QM_ARB_MST_CRED_STS_22 0xFC8C08
+
+#define mmTPC7_QM_ARB_MST_CRED_STS_23 0xFC8C0C
+
+#define mmTPC7_QM_ARB_MST_CRED_STS_24 0xFC8C10
+
+#define mmTPC7_QM_ARB_MST_CRED_STS_25 0xFC8C14
+
+#define mmTPC7_QM_ARB_MST_CRED_STS_26 0xFC8C18
+
+#define mmTPC7_QM_ARB_MST_CRED_STS_27 0xFC8C1C
+
+#define mmTPC7_QM_ARB_MST_CRED_STS_28 0xFC8C20
+
+#define mmTPC7_QM_ARB_MST_CRED_STS_29 0xFC8C24
+
+#define mmTPC7_QM_ARB_MST_CRED_STS_30 0xFC8C28
+
+#define mmTPC7_QM_ARB_MST_CRED_STS_31 0xFC8C2C
+
+#define mmTPC7_QM_CGM_CFG 0xFC8C70
+
+#define mmTPC7_QM_CGM_STS 0xFC8C74
+
+#define mmTPC7_QM_CGM_CFG1 0xFC8C78
+
+#define mmTPC7_QM_LOCAL_RANGE_BASE 0xFC8C80
+
+#define mmTPC7_QM_LOCAL_RANGE_SIZE 0xFC8C84
+
+#define mmTPC7_QM_CSMR_STRICT_PRIO_CFG 0xFC8C90
+
+#define mmTPC7_QM_HBW_RD_RATE_LIM_CFG_1 0xFC8C94
+
+#define mmTPC7_QM_LBW_WR_RATE_LIM_CFG_0 0xFC8C98
+
+#define mmTPC7_QM_LBW_WR_RATE_LIM_CFG_1 0xFC8C9C
+
+#define mmTPC7_QM_HBW_RD_RATE_LIM_CFG_0 0xFC8CA0
+
+#define mmTPC7_QM_GLBL_AXCACHE 0xFC8CA4
+
+#define mmTPC7_QM_IND_GW_APB_CFG 0xFC8CB0
+
+#define mmTPC7_QM_IND_GW_APB_WDATA 0xFC8CB4
+
+#define mmTPC7_QM_IND_GW_APB_RDATA 0xFC8CB8
+
+#define mmTPC7_QM_IND_GW_APB_STATUS 0xFC8CBC
+
+#define mmTPC7_QM_GLBL_ERR_ADDR_LO 0xFC8CD0
+
+#define mmTPC7_QM_GLBL_ERR_ADDR_HI 0xFC8CD4
+
+#define mmTPC7_QM_GLBL_ERR_WDATA 0xFC8CD8
+
+#define mmTPC7_QM_GLBL_MEM_INIT_BUSY 0xFC8D00
+
+#endif /* ASIC_REG_TPC7_QM_REGS_H_ */
diff --git a/drivers/accel/habanalabs/include/gaudi/gaudi.h b/drivers/accel/habanalabs/include/gaudi/gaudi.h
new file mode 100644
index 0000000000..ffae107b16
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi/gaudi.h
@@ -0,0 +1,61 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2018-2020 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+#ifndef GAUDI_H
+#define GAUDI_H
+
+#define SRAM_BAR_ID 0
+#define CFG_BAR_ID 2
+#define HBM_BAR_ID 4
+
+#define SRAM_BAR_SIZE 0x4000000ull /* 64MB */
+#define CFG_BAR_SIZE 0x8000000ull /* 128MB */
+
+#define CFG_BASE 0x7FFC000000ull
+#define CFG_SIZE 0x4000000 /* 32MB CFG + 32MB DBG*/
+
+#define SRAM_BASE_ADDR 0x7FF0000000ull
+#define SRAM_SIZE 0x1400000 /* 20MB */
+
+#define SPI_FLASH_BASE_ADDR 0x7FF8000000ull
+
+#define PSOC_SCRATCHPAD_ADDR 0x7FFBFE0000ull
+#define PSOC_SCRATCHPAD_SIZE 0x10000 /* 64KB */
+
+#define PCIE_FW_SRAM_ADDR 0x7FFBFF0000ull
+#define PCIE_FW_SRAM_SIZE 0x8000 /* 32KB */
+
+#define DRAM_PHYS_BASE 0x0ull
+
+#define HOST_PHYS_BASE 0x8000000000ull /* 0.5TB */
+#define HOST_PHYS_SIZE 0x1000000000000ull /* 0.25PB (48 bits) */
+
+#define GAUDI_MSI_ENTRIES 32
+
+#define QMAN_PQ_ENTRY_SIZE 16 /* Bytes */
+
+#define MAX_ASID 2
+
+#define PROT_BITS_OFFS 0xF80
+
+#define MME_NUMBER_OF_MASTER_ENGINES 2
+
+#define MME_NUMBER_OF_SLAVE_ENGINES 2
+
+#define TPC_NUMBER_OF_ENGINES 8
+
+#define DMA_NUMBER_OF_CHANNELS 8
+
+#define NIC_NUMBER_OF_MACROS 5
+
+#define NIC_NUMBER_OF_ENGINES (NIC_NUMBER_OF_MACROS * 2)
+
+#define NUMBER_OF_IF 8
+
+#define DEVICE_CACHE_LINE_SIZE 128
+
+#endif /* GAUDI_H */
diff --git a/drivers/accel/habanalabs/include/gaudi/gaudi_async_events.h b/drivers/accel/habanalabs/include/gaudi/gaudi_async_events.h
new file mode 100644
index 0000000000..c07ed4ed30
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi/gaudi_async_events.h
@@ -0,0 +1,332 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2018-2020 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ ** DO NOT EDIT BELOW **
+ ************************************/
+
+#ifndef __GAUDI_ASYNC_EVENTS_H_
+#define __GAUDI_ASYNC_EVENTS_H_
+
+enum gaudi_async_event_id {
+ GAUDI_EVENT_PCIE_CORE_SERR = 32,
+ GAUDI_EVENT_PCIE_CORE_DERR = 33,
+ GAUDI_EVENT_PCIE_IF_SERR = 34,
+ GAUDI_EVENT_PCIE_IF_DERR = 35,
+ GAUDI_EVENT_PCIE_PHY_SERR = 36,
+ GAUDI_EVENT_PCIE_PHY_DERR = 37,
+ GAUDI_EVENT_TPC0_SERR = 38,
+ GAUDI_EVENT_TPC1_SERR = 39,
+ GAUDI_EVENT_TPC2_SERR = 40,
+ GAUDI_EVENT_TPC3_SERR = 41,
+ GAUDI_EVENT_TPC4_SERR = 42,
+ GAUDI_EVENT_TPC5_SERR = 43,
+ GAUDI_EVENT_TPC6_SERR = 44,
+ GAUDI_EVENT_TPC7_SERR = 45,
+ GAUDI_EVENT_TPC0_DERR = 46,
+ GAUDI_EVENT_TPC1_DERR = 47,
+ GAUDI_EVENT_TPC2_DERR = 48,
+ GAUDI_EVENT_TPC3_DERR = 49,
+ GAUDI_EVENT_TPC4_DERR = 50,
+ GAUDI_EVENT_TPC5_DERR = 51,
+ GAUDI_EVENT_TPC6_DERR = 52,
+ GAUDI_EVENT_TPC7_DERR = 53,
+ GAUDI_EVENT_MME0_ACC_SERR = 54,
+ GAUDI_EVENT_MME0_ACC_DERR = 55,
+ GAUDI_EVENT_MME0_SBAB_SERR = 56,
+ GAUDI_EVENT_MME0_SBAB_DERR = 57,
+ GAUDI_EVENT_MME1_ACC_SERR = 58,
+ GAUDI_EVENT_MME1_ACC_DERR = 59,
+ GAUDI_EVENT_MME1_SBAB_SERR = 60,
+ GAUDI_EVENT_MME1_SBAB_DERR = 61,
+ GAUDI_EVENT_MME2_ACC_SERR = 62,
+ GAUDI_EVENT_MME2_ACC_DERR = 63,
+ GAUDI_EVENT_MME2_SBAB_SERR = 64,
+ GAUDI_EVENT_MME2_SBAB_DERR = 65,
+ GAUDI_EVENT_MME3_ACC_SERR = 66,
+ GAUDI_EVENT_MME3_ACC_DERR = 67,
+ GAUDI_EVENT_MME3_SBAB_SERR = 68,
+ GAUDI_EVENT_MME3_SBAB_DERR = 69,
+ GAUDI_EVENT_DMA0_SERR_ECC = 70,
+ GAUDI_EVENT_DMA1_SERR_ECC = 71,
+ GAUDI_EVENT_DMA2_SERR_ECC = 72,
+ GAUDI_EVENT_DMA3_SERR_ECC = 73,
+ GAUDI_EVENT_DMA4_SERR_ECC = 74,
+ GAUDI_EVENT_DMA5_SERR_ECC = 75,
+ GAUDI_EVENT_DMA6_SERR_ECC = 76,
+ GAUDI_EVENT_DMA7_SERR_ECC = 77,
+ GAUDI_EVENT_DMA0_DERR_ECC = 78,
+ GAUDI_EVENT_DMA1_DERR_ECC = 79,
+ GAUDI_EVENT_DMA2_DERR_ECC = 80,
+ GAUDI_EVENT_DMA3_DERR_ECC = 81,
+ GAUDI_EVENT_DMA4_DERR_ECC = 82,
+ GAUDI_EVENT_DMA5_DERR_ECC = 83,
+ GAUDI_EVENT_DMA6_DERR_ECC = 84,
+ GAUDI_EVENT_DMA7_DERR_ECC = 85,
+ GAUDI_EVENT_CPU_IF_ECC_SERR = 86,
+ GAUDI_EVENT_CPU_IF_ECC_DERR = 87,
+ GAUDI_EVENT_PSOC_MEM_SERR = 88,
+ GAUDI_EVENT_PSOC_CORESIGHT_SERR = 89,
+ GAUDI_EVENT_PSOC_MEM_DERR = 90,
+ GAUDI_EVENT_PSOC_CORESIGHT_DERR = 91,
+ GAUDI_EVENT_SRAM0_SERR = 92,
+ GAUDI_EVENT_SRAM1_SERR = 93,
+ GAUDI_EVENT_SRAM2_SERR = 94,
+ GAUDI_EVENT_SRAM3_SERR = 95,
+ GAUDI_EVENT_SRAM7_SERR = 96,
+ GAUDI_EVENT_SRAM6_SERR = 97,
+ GAUDI_EVENT_SRAM5_SERR = 98,
+ GAUDI_EVENT_SRAM4_SERR = 99,
+ GAUDI_EVENT_SRAM8_SERR = 100,
+ GAUDI_EVENT_SRAM9_SERR = 101,
+ GAUDI_EVENT_SRAM10_SERR = 102,
+ GAUDI_EVENT_SRAM11_SERR = 103,
+ GAUDI_EVENT_SRAM15_SERR = 104,
+ GAUDI_EVENT_SRAM14_SERR = 105,
+ GAUDI_EVENT_SRAM13_SERR = 106,
+ GAUDI_EVENT_SRAM12_SERR = 107,
+ GAUDI_EVENT_SRAM16_SERR = 108,
+ GAUDI_EVENT_SRAM17_SERR = 109,
+ GAUDI_EVENT_SRAM18_SERR = 110,
+ GAUDI_EVENT_SRAM19_SERR = 111,
+ GAUDI_EVENT_SRAM23_SERR = 112,
+ GAUDI_EVENT_SRAM22_SERR = 113,
+ GAUDI_EVENT_SRAM21_SERR = 114,
+ GAUDI_EVENT_SRAM20_SERR = 115,
+ GAUDI_EVENT_SRAM24_SERR = 116,
+ GAUDI_EVENT_SRAM25_SERR = 117,
+ GAUDI_EVENT_SRAM26_SERR = 118,
+ GAUDI_EVENT_SRAM27_SERR = 119,
+ GAUDI_EVENT_SRAM31_SERR = 120,
+ GAUDI_EVENT_SRAM30_SERR = 121,
+ GAUDI_EVENT_SRAM29_SERR = 122,
+ GAUDI_EVENT_SRAM28_SERR = 123,
+ GAUDI_EVENT_SRAM0_DERR = 124,
+ GAUDI_EVENT_SRAM1_DERR = 125,
+ GAUDI_EVENT_SRAM2_DERR = 126,
+ GAUDI_EVENT_SRAM3_DERR = 127,
+ GAUDI_EVENT_SRAM7_DERR = 128,
+ GAUDI_EVENT_SRAM6_DERR = 129,
+ GAUDI_EVENT_SRAM5_DERR = 130,
+ GAUDI_EVENT_SRAM4_DERR = 131,
+ GAUDI_EVENT_SRAM8_DERR = 132,
+ GAUDI_EVENT_SRAM9_DERR = 133,
+ GAUDI_EVENT_SRAM10_DERR = 134,
+ GAUDI_EVENT_SRAM11_DERR = 135,
+ GAUDI_EVENT_SRAM15_DERR = 136,
+ GAUDI_EVENT_SRAM14_DERR = 137,
+ GAUDI_EVENT_SRAM13_DERR = 138,
+ GAUDI_EVENT_SRAM12_DERR = 139,
+ GAUDI_EVENT_SRAM16_DERR = 140,
+ GAUDI_EVENT_SRAM17_DERR = 141,
+ GAUDI_EVENT_SRAM18_DERR = 142,
+ GAUDI_EVENT_SRAM19_DERR = 143,
+ GAUDI_EVENT_SRAM23_DERR = 144,
+ GAUDI_EVENT_SRAM22_DERR = 145,
+ GAUDI_EVENT_SRAM21_DERR = 146,
+ GAUDI_EVENT_SRAM20_DERR = 147,
+ GAUDI_EVENT_SRAM24_DERR = 148,
+ GAUDI_EVENT_SRAM25_DERR = 149,
+ GAUDI_EVENT_SRAM26_DERR = 150,
+ GAUDI_EVENT_SRAM27_DERR = 151,
+ GAUDI_EVENT_SRAM31_DERR = 152,
+ GAUDI_EVENT_SRAM30_DERR = 153,
+ GAUDI_EVENT_SRAM29_DERR = 154,
+ GAUDI_EVENT_SRAM28_DERR = 155,
+ GAUDI_EVENT_NIC0_SERR = 156,
+ GAUDI_EVENT_NIC1_SERR = 157,
+ GAUDI_EVENT_NIC2_SERR = 158,
+ GAUDI_EVENT_NIC3_SERR = 159,
+ GAUDI_EVENT_NIC4_SERR = 160,
+ GAUDI_EVENT_NIC0_DERR = 166,
+ GAUDI_EVENT_NIC1_DERR = 167,
+ GAUDI_EVENT_NIC2_DERR = 168,
+ GAUDI_EVENT_NIC3_DERR = 169,
+ GAUDI_EVENT_NIC4_DERR = 170,
+ GAUDI_EVENT_DMA_IF0_SERR = 176,
+ GAUDI_EVENT_DMA_IF1_SERR = 177,
+ GAUDI_EVENT_DMA_IF2_SERR = 178,
+ GAUDI_EVENT_DMA_IF3_SERR = 179,
+ GAUDI_EVENT_DMA_IF0_DERR = 180,
+ GAUDI_EVENT_DMA_IF1_DERR = 181,
+ GAUDI_EVENT_DMA_IF2_DERR = 182,
+ GAUDI_EVENT_DMA_IF3_DERR = 183,
+ GAUDI_EVENT_GIC500 = 184,
+ GAUDI_EVENT_HBM_0_SERR = 185,
+ GAUDI_EVENT_HBM_1_SERR = 186,
+ GAUDI_EVENT_HBM_2_SERR = 187,
+ GAUDI_EVENT_HBM_3_SERR = 188,
+ GAUDI_EVENT_HBM_0_DERR = 189,
+ GAUDI_EVENT_HBM_1_DERR = 190,
+ GAUDI_EVENT_HBM_2_DERR = 191,
+ GAUDI_EVENT_HBM_3_DERR = 192,
+ GAUDI_EVENT_MMU_SERR = 193,
+ GAUDI_EVENT_MMU_DERR = 194,
+ GAUDI_EVENT_PCIE_DEC = 200,
+ GAUDI_EVENT_TPC0_DEC = 201,
+ GAUDI_EVENT_TPC1_DEC = 203,
+ GAUDI_EVENT_TPC2_DEC = 205,
+ GAUDI_EVENT_TPC3_DEC = 207,
+ GAUDI_EVENT_TPC4_DEC = 209,
+ GAUDI_EVENT_TPC5_DEC = 211,
+ GAUDI_EVENT_TPC6_DEC = 213,
+ GAUDI_EVENT_TPC7_DEC = 215,
+ GAUDI_EVENT_AXI_ECC = 217,
+ GAUDI_EVENT_L2_RAM_ECC = 218,
+ GAUDI_EVENT_MME0_WBC_RSP = 219,
+ GAUDI_EVENT_MME0_SBAB0_RSP = 220,
+ GAUDI_EVENT_MME1_WBC_RSP = 224,
+ GAUDI_EVENT_MME1_SBAB0_RSP = 225,
+ GAUDI_EVENT_MME2_WBC_RSP = 229,
+ GAUDI_EVENT_MME2_SBAB0_RSP = 230,
+ GAUDI_EVENT_MME3_WBC_RSP = 234,
+ GAUDI_EVENT_MME3_SBAB0_RSP = 235,
+ GAUDI_EVENT_PLL0 = 239,
+ GAUDI_EVENT_PLL1 = 240,
+ GAUDI_EVENT_PLL2 = 241,
+ GAUDI_EVENT_PLL3 = 242,
+ GAUDI_EVENT_PLL4 = 243,
+ GAUDI_EVENT_PLL5 = 244,
+ GAUDI_EVENT_PLL6 = 245,
+ GAUDI_EVENT_PLL7 = 246,
+ GAUDI_EVENT_PLL8 = 247,
+ GAUDI_EVENT_PLL9 = 248,
+ GAUDI_EVENT_PLL10 = 249,
+ GAUDI_EVENT_PLL11 = 250,
+ GAUDI_EVENT_PLL12 = 251,
+ GAUDI_EVENT_PLL13 = 252,
+ GAUDI_EVENT_PLL14 = 253,
+ GAUDI_EVENT_PLL15 = 254,
+ GAUDI_EVENT_PLL16 = 255,
+ GAUDI_EVENT_PLL17 = 256,
+ GAUDI_EVENT_CPU_AXI_SPLITTER = 257,
+ GAUDI_EVENT_PSOC_AXI_DEC = 262,
+ GAUDI_EVENT_PSOC_PRSTN_FALL = 263,
+ GAUDI_EVENT_NIC_SEI_0 = 264,
+ GAUDI_EVENT_NIC_SEI_1 = 265,
+ GAUDI_EVENT_NIC_SEI_2 = 266,
+ GAUDI_EVENT_NIC_SEI_3 = 267,
+ GAUDI_EVENT_NIC_SEI_4 = 268,
+ GAUDI_EVENT_DMA_IF_SEI_0 = 277,
+ GAUDI_EVENT_DMA_IF_SEI_1 = 278,
+ GAUDI_EVENT_DMA_IF_SEI_2 = 279,
+ GAUDI_EVENT_DMA_IF_SEI_3 = 280,
+ GAUDI_EVENT_PCIE_FLR = 290,
+ GAUDI_EVENT_TPC0_BMON_SPMU = 300,
+ GAUDI_EVENT_TPC0_KRN_ERR = 301,
+ GAUDI_EVENT_TPC1_BMON_SPMU = 306,
+ GAUDI_EVENT_TPC1_KRN_ERR = 307,
+ GAUDI_EVENT_TPC2_BMON_SPMU = 312,
+ GAUDI_EVENT_TPC2_KRN_ERR = 313,
+ GAUDI_EVENT_TPC3_BMON_SPMU = 318,
+ GAUDI_EVENT_TPC3_KRN_ERR = 319,
+ GAUDI_EVENT_TPC4_BMON_SPMU = 324,
+ GAUDI_EVENT_TPC4_KRN_ERR = 325,
+ GAUDI_EVENT_TPC5_BMON_SPMU = 330,
+ GAUDI_EVENT_TPC5_KRN_ERR = 331,
+ GAUDI_EVENT_TPC6_BMON_SPMU = 336,
+ GAUDI_EVENT_TPC6_KRN_ERR = 337,
+ GAUDI_EVENT_TPC7_BMON_SPMU = 342,
+ GAUDI_EVENT_TPC7_KRN_ERR = 343,
+ GAUDI_EVENT_MMU_PAGE_FAULT = 380,
+ GAUDI_EVENT_MMU_WR_PERM = 381,
+ GAUDI_EVENT_DMA_BM_CH0 = 383,
+ GAUDI_EVENT_DMA_BM_CH1 = 384,
+ GAUDI_EVENT_DMA_BM_CH2 = 385,
+ GAUDI_EVENT_DMA_BM_CH3 = 386,
+ GAUDI_EVENT_DMA_BM_CH4 = 387,
+ GAUDI_EVENT_DMA_BM_CH5 = 388,
+ GAUDI_EVENT_DMA_BM_CH6 = 389,
+ GAUDI_EVENT_DMA_BM_CH7 = 390,
+ GAUDI_EVENT_HBM0_SPI_0 = 395,
+ GAUDI_EVENT_HBM0_SPI_1 = 396,
+ GAUDI_EVENT_HBM1_SPI_0 = 399,
+ GAUDI_EVENT_HBM1_SPI_1 = 400,
+ GAUDI_EVENT_HBM2_SPI_0 = 403,
+ GAUDI_EVENT_HBM2_SPI_1 = 404,
+ GAUDI_EVENT_HBM3_SPI_0 = 407,
+ GAUDI_EVENT_HBM3_SPI_1 = 408,
+ GAUDI_EVENT_PSOC_GPIO_U16_0 = 421,
+ GAUDI_EVENT_NIC0_CS_DBG_DERR = 483,
+ GAUDI_EVENT_NIC1_CS_DBG_DERR = 487,
+ GAUDI_EVENT_NIC2_CS_DBG_DERR = 491,
+ GAUDI_EVENT_NIC3_CS_DBG_DERR = 495,
+ GAUDI_EVENT_NIC4_CS_DBG_DERR = 499,
+ GAUDI_EVENT_RAZWI_OR_ADC = 548,
+ GAUDI_EVENT_TPC0_QM = 572,
+ GAUDI_EVENT_TPC1_QM = 573,
+ GAUDI_EVENT_TPC2_QM = 574,
+ GAUDI_EVENT_TPC3_QM = 575,
+ GAUDI_EVENT_TPC4_QM = 576,
+ GAUDI_EVENT_TPC5_QM = 577,
+ GAUDI_EVENT_TPC6_QM = 578,
+ GAUDI_EVENT_TPC7_QM = 579,
+ GAUDI_EVENT_MME0_QM = 581,
+ GAUDI_EVENT_MME2_QM = 582,
+ GAUDI_EVENT_DMA0_QM = 583,
+ GAUDI_EVENT_DMA1_QM = 584,
+ GAUDI_EVENT_DMA2_QM = 585,
+ GAUDI_EVENT_DMA3_QM = 586,
+ GAUDI_EVENT_DMA4_QM = 587,
+ GAUDI_EVENT_DMA5_QM = 588,
+ GAUDI_EVENT_DMA6_QM = 589,
+ GAUDI_EVENT_DMA7_QM = 590,
+ GAUDI_EVENT_NIC0_QM0 = 594,
+ GAUDI_EVENT_NIC0_QM1 = 595,
+ GAUDI_EVENT_NIC1_QM0 = 596,
+ GAUDI_EVENT_NIC1_QM1 = 597,
+ GAUDI_EVENT_NIC2_QM0 = 598,
+ GAUDI_EVENT_NIC2_QM1 = 599,
+ GAUDI_EVENT_NIC3_QM0 = 600,
+ GAUDI_EVENT_NIC3_QM1 = 601,
+ GAUDI_EVENT_NIC4_QM0 = 602,
+ GAUDI_EVENT_NIC4_QM1 = 603,
+ GAUDI_EVENT_DMA0_CORE = 604,
+ GAUDI_EVENT_DMA1_CORE = 605,
+ GAUDI_EVENT_DMA2_CORE = 606,
+ GAUDI_EVENT_DMA3_CORE = 607,
+ GAUDI_EVENT_DMA4_CORE = 608,
+ GAUDI_EVENT_DMA5_CORE = 609,
+ GAUDI_EVENT_DMA6_CORE = 610,
+ GAUDI_EVENT_DMA7_CORE = 611,
+ GAUDI_EVENT_NIC0_QP0 = 612,
+ GAUDI_EVENT_NIC0_QP1 = 613,
+ GAUDI_EVENT_NIC1_QP0 = 614,
+ GAUDI_EVENT_NIC1_QP1 = 615,
+ GAUDI_EVENT_NIC2_QP0 = 616,
+ GAUDI_EVENT_NIC2_QP1 = 617,
+ GAUDI_EVENT_NIC3_QP0 = 618,
+ GAUDI_EVENT_NIC3_QP1 = 619,
+ GAUDI_EVENT_NIC4_QP0 = 620,
+ GAUDI_EVENT_NIC4_QP1 = 621,
+ GAUDI_EVENT_PI_UPDATE = 635,
+ GAUDI_EVENT_HALT_MACHINE = 636,
+ GAUDI_EVENT_INTS_REGISTER = 637,
+ GAUDI_EVENT_SOFT_RESET = 638,
+ GAUDI_EVENT_FW_ALIVE_S = 645,
+ GAUDI_EVENT_DEV_RESET_REQ = 646,
+ GAUDI_EVENT_PKT_QUEUE_OUT_SYNC = 647,
+ GAUDI_EVENT_STATUS_NIC0_ENG0 = 648,
+ GAUDI_EVENT_STATUS_NIC0_ENG1 = 649,
+ GAUDI_EVENT_STATUS_NIC1_ENG0 = 650,
+ GAUDI_EVENT_STATUS_NIC1_ENG1 = 651,
+ GAUDI_EVENT_STATUS_NIC2_ENG0 = 652,
+ GAUDI_EVENT_STATUS_NIC2_ENG1 = 653,
+ GAUDI_EVENT_STATUS_NIC3_ENG0 = 654,
+ GAUDI_EVENT_STATUS_NIC3_ENG1 = 655,
+ GAUDI_EVENT_STATUS_NIC4_ENG0 = 656,
+ GAUDI_EVENT_STATUS_NIC4_ENG1 = 657,
+ GAUDI_EVENT_FIX_POWER_ENV_S = 658,
+ GAUDI_EVENT_FIX_POWER_ENV_E = 659,
+ GAUDI_EVENT_FIX_THERMAL_ENV_S = 660,
+ GAUDI_EVENT_FIX_THERMAL_ENV_E = 661,
+ GAUDI_EVENT_RAZWI_OR_ADC_SW = 662,
+ GAUDI_EVENT_SIZE,
+};
+
+#endif /* __GAUDI_ASYNC_EVENTS_H_ */
diff --git a/drivers/accel/habanalabs/include/gaudi/gaudi_async_ids_map_extended.h b/drivers/accel/habanalabs/include/gaudi/gaudi_async_ids_map_extended.h
new file mode 100644
index 0000000000..479b6b0382
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi/gaudi_async_ids_map_extended.h
@@ -0,0 +1,710 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2018-2020 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ ** DO NOT EDIT BELOW **
+ ************************************/
+
+#ifndef __GAUDI_ASYNC_IDS_MAP_EVENTS_EXT_H_
+#define __GAUDI_ASYNC_IDS_MAP_EVENTS_EXT_H_
+
+struct gaudi_async_events_ids_map {
+ int fc_id;
+ int cpu_id;
+ int valid;
+ char name[64];
+};
+
+static struct gaudi_async_events_ids_map gaudi_irq_map_table[] = {
+ { .fc_id = 0, .cpu_id = 0, .valid = 0, .name = "" },
+ { .fc_id = 1, .cpu_id = 1, .valid = 0, .name = "" },
+ { .fc_id = 2, .cpu_id = 2, .valid = 0, .name = "" },
+ { .fc_id = 3, .cpu_id = 3, .valid = 0, .name = "" },
+ { .fc_id = 4, .cpu_id = 4, .valid = 0, .name = "" },
+ { .fc_id = 5, .cpu_id = 5, .valid = 0, .name = "" },
+ { .fc_id = 6, .cpu_id = 6, .valid = 0, .name = "" },
+ { .fc_id = 7, .cpu_id = 7, .valid = 0, .name = "" },
+ { .fc_id = 8, .cpu_id = 8, .valid = 0, .name = "" },
+ { .fc_id = 9, .cpu_id = 9, .valid = 0, .name = "" },
+ { .fc_id = 10, .cpu_id = 10, .valid = 0, .name = "" },
+ { .fc_id = 11, .cpu_id = 11, .valid = 0, .name = "" },
+ { .fc_id = 12, .cpu_id = 12, .valid = 0, .name = "" },
+ { .fc_id = 13, .cpu_id = 13, .valid = 0, .name = "" },
+ { .fc_id = 14, .cpu_id = 14, .valid = 0, .name = "" },
+ { .fc_id = 15, .cpu_id = 15, .valid = 0, .name = "" },
+ { .fc_id = 16, .cpu_id = 16, .valid = 0, .name = "" },
+ { .fc_id = 17, .cpu_id = 17, .valid = 0, .name = "" },
+ { .fc_id = 18, .cpu_id = 18, .valid = 0, .name = "" },
+ { .fc_id = 19, .cpu_id = 19, .valid = 0, .name = "" },
+ { .fc_id = 20, .cpu_id = 20, .valid = 0, .name = "" },
+ { .fc_id = 21, .cpu_id = 21, .valid = 0, .name = "" },
+ { .fc_id = 22, .cpu_id = 22, .valid = 0, .name = "" },
+ { .fc_id = 23, .cpu_id = 23, .valid = 0, .name = "" },
+ { .fc_id = 24, .cpu_id = 24, .valid = 0, .name = "" },
+ { .fc_id = 25, .cpu_id = 25, .valid = 0, .name = "" },
+ { .fc_id = 26, .cpu_id = 26, .valid = 0, .name = "" },
+ { .fc_id = 27, .cpu_id = 27, .valid = 0, .name = "" },
+ { .fc_id = 28, .cpu_id = 28, .valid = 0, .name = "" },
+ { .fc_id = 29, .cpu_id = 29, .valid = 0, .name = "" },
+ { .fc_id = 30, .cpu_id = 30, .valid = 0, .name = "" },
+ { .fc_id = 31, .cpu_id = 31, .valid = 0, .name = "" },
+ { .fc_id = 32, .cpu_id = 32, .valid = 1, .name = "PCIE_CORE_SERR" },
+ { .fc_id = 33, .cpu_id = 33, .valid = 1, .name = "PCIE_CORE_DERR" },
+ { .fc_id = 34, .cpu_id = 34, .valid = 1, .name = "PCIE_IF_SERR" },
+ { .fc_id = 35, .cpu_id = 35, .valid = 1, .name = "PCIE_IF_DERR" },
+ { .fc_id = 36, .cpu_id = 36, .valid = 1, .name = "PCIE_PHY_SERR" },
+ { .fc_id = 37, .cpu_id = 37, .valid = 1, .name = "PCIE_PHY_DERR" },
+ { .fc_id = 38, .cpu_id = 38, .valid = 1, .name = "TPC0_SERR" },
+ { .fc_id = 39, .cpu_id = 38, .valid = 1, .name = "TPC1_SERR" },
+ { .fc_id = 40, .cpu_id = 38, .valid = 1, .name = "TPC2_SERR" },
+ { .fc_id = 41, .cpu_id = 38, .valid = 1, .name = "TPC3_SERR" },
+ { .fc_id = 42, .cpu_id = 38, .valid = 1, .name = "TPC4_SERR" },
+ { .fc_id = 43, .cpu_id = 38, .valid = 1, .name = "TPC5_SERR" },
+ { .fc_id = 44, .cpu_id = 38, .valid = 1, .name = "TPC6_SERR" },
+ { .fc_id = 45, .cpu_id = 38, .valid = 1, .name = "TPC7_SERR" },
+ { .fc_id = 46, .cpu_id = 39, .valid = 1, .name = "TPC0_DERR" },
+ { .fc_id = 47, .cpu_id = 39, .valid = 1, .name = "TPC1_DERR" },
+ { .fc_id = 48, .cpu_id = 39, .valid = 1, .name = "TPC2_DERR" },
+ { .fc_id = 49, .cpu_id = 39, .valid = 1, .name = "TPC3_DERR" },
+ { .fc_id = 50, .cpu_id = 39, .valid = 1, .name = "TPC4_DERR" },
+ { .fc_id = 51, .cpu_id = 39, .valid = 1, .name = "TPC5_DERR" },
+ { .fc_id = 52, .cpu_id = 39, .valid = 1, .name = "TPC6_DERR" },
+ { .fc_id = 53, .cpu_id = 39, .valid = 1, .name = "TPC7_DERR" },
+ { .fc_id = 54, .cpu_id = 40, .valid = 1, .name = "MME0_ACC_SERR" },
+ { .fc_id = 55, .cpu_id = 41, .valid = 1, .name = "MME0_ACC_DERR" },
+ { .fc_id = 56, .cpu_id = 42, .valid = 1, .name = "MME0_SBAB_SERR" },
+ { .fc_id = 57, .cpu_id = 43, .valid = 1, .name = "MME0_SBAB_DERR" },
+ { .fc_id = 58, .cpu_id = 44, .valid = 1, .name = "MME1_ACC_SERR" },
+ { .fc_id = 59, .cpu_id = 45, .valid = 1, .name = "MME1_ACC_DERR" },
+ { .fc_id = 60, .cpu_id = 46, .valid = 1, .name = "MME1_SBAB_SERR" },
+ { .fc_id = 61, .cpu_id = 47, .valid = 1, .name = "MME1_SBAB_DERR" },
+ { .fc_id = 62, .cpu_id = 48, .valid = 1, .name = "MME2_ACC_SERR" },
+ { .fc_id = 63, .cpu_id = 49, .valid = 1, .name = "MME2_ACC_DERR" },
+ { .fc_id = 64, .cpu_id = 50, .valid = 1, .name = "MME2_SBAB_SERR" },
+ { .fc_id = 65, .cpu_id = 51, .valid = 1, .name = "MME2_SBAB_DERR" },
+ { .fc_id = 66, .cpu_id = 52, .valid = 1, .name = "MME3_ACC_SERR" },
+ { .fc_id = 67, .cpu_id = 53, .valid = 1, .name = "MME3_ACC_DERR" },
+ { .fc_id = 68, .cpu_id = 54, .valid = 1, .name = "MME3_SBAB_SERR" },
+ { .fc_id = 69, .cpu_id = 55, .valid = 1, .name = "MME3_SBAB_DERR" },
+ { .fc_id = 70, .cpu_id = 56, .valid = 1, .name = "DMA0_SERR_ECC" },
+ { .fc_id = 71, .cpu_id = 56, .valid = 1, .name = "DMA1_SERR_ECC" },
+ { .fc_id = 72, .cpu_id = 56, .valid = 1, .name = "DMA2_SERR_ECC" },
+ { .fc_id = 73, .cpu_id = 56, .valid = 1, .name = "DMA3_SERR_ECC" },
+ { .fc_id = 74, .cpu_id = 56, .valid = 1, .name = "DMA4_SERR_ECC" },
+ { .fc_id = 75, .cpu_id = 56, .valid = 1, .name = "DMA5_SERR_ECC" },
+ { .fc_id = 76, .cpu_id = 56, .valid = 1, .name = "DMA6_SERR_ECC" },
+ { .fc_id = 77, .cpu_id = 56, .valid = 1, .name = "DMA7_SERR_ECC" },
+ { .fc_id = 78, .cpu_id = 57, .valid = 1, .name = "DMA0_DERR_ECC" },
+ { .fc_id = 79, .cpu_id = 57, .valid = 1, .name = "DMA1_DERR_ECC" },
+ { .fc_id = 80, .cpu_id = 57, .valid = 1, .name = "DMA2_DERR_ECC" },
+ { .fc_id = 81, .cpu_id = 57, .valid = 1, .name = "DMA3_DERR_ECC" },
+ { .fc_id = 82, .cpu_id = 57, .valid = 1, .name = "DMA4_DERR_ECC" },
+ { .fc_id = 83, .cpu_id = 57, .valid = 1, .name = "DMA5_DERR_ECC" },
+ { .fc_id = 84, .cpu_id = 57, .valid = 1, .name = "DMA6_DERR_ECC" },
+ { .fc_id = 85, .cpu_id = 57, .valid = 1, .name = "DMA7_DERR_ECC" },
+ { .fc_id = 86, .cpu_id = 58, .valid = 1, .name = "CPU_IF_ECC_SERR" },
+ { .fc_id = 87, .cpu_id = 59, .valid = 1, .name = "CPU_IF_ECC_DERR" },
+ { .fc_id = 88, .cpu_id = 60, .valid = 1, .name = "PSOC_MEM_SERR" },
+ { .fc_id = 89, .cpu_id = 61, .valid = 1,
+ .name = "PSOC_CORESIGHT_SERR" },
+ { .fc_id = 90, .cpu_id = 62, .valid = 1, .name = "PSOC_MEM_DERR" },
+ { .fc_id = 91, .cpu_id = 63, .valid = 1,
+ .name = "PSOC_CORESIGHT_DERR" },
+ { .fc_id = 92, .cpu_id = 64, .valid = 1, .name = "SRAM0_SERR" },
+ { .fc_id = 93, .cpu_id = 64, .valid = 1, .name = "SRAM1_SERR" },
+ { .fc_id = 94, .cpu_id = 64, .valid = 1, .name = "SRAM2_SERR" },
+ { .fc_id = 95, .cpu_id = 64, .valid = 1, .name = "SRAM3_SERR" },
+ { .fc_id = 96, .cpu_id = 64, .valid = 1, .name = "SRAM7_SERR" },
+ { .fc_id = 97, .cpu_id = 64, .valid = 1, .name = "SRAM6_SERR" },
+ { .fc_id = 98, .cpu_id = 64, .valid = 1, .name = "SRAM5_SERR" },
+ { .fc_id = 99, .cpu_id = 64, .valid = 1, .name = "SRAM4_SERR" },
+ { .fc_id = 100, .cpu_id = 64, .valid = 1, .name = "SRAM8_SERR" },
+ { .fc_id = 101, .cpu_id = 64, .valid = 1, .name = "SRAM9_SERR" },
+ { .fc_id = 102, .cpu_id = 64, .valid = 1, .name = "SRAM10_SERR" },
+ { .fc_id = 103, .cpu_id = 64, .valid = 1, .name = "SRAM11_SERR" },
+ { .fc_id = 104, .cpu_id = 64, .valid = 1, .name = "SRAM15_SERR" },
+ { .fc_id = 105, .cpu_id = 64, .valid = 1, .name = "SRAM14_SERR" },
+ { .fc_id = 106, .cpu_id = 64, .valid = 1, .name = "SRAM13_SERR" },
+ { .fc_id = 107, .cpu_id = 64, .valid = 1, .name = "SRAM12_SERR" },
+ { .fc_id = 108, .cpu_id = 64, .valid = 1, .name = "SRAM16_SERR" },
+ { .fc_id = 109, .cpu_id = 64, .valid = 1, .name = "SRAM17_SERR" },
+ { .fc_id = 110, .cpu_id = 64, .valid = 1, .name = "SRAM18_SERR" },
+ { .fc_id = 111, .cpu_id = 64, .valid = 1, .name = "SRAM19_SERR" },
+ { .fc_id = 112, .cpu_id = 64, .valid = 1, .name = "SRAM23_SERR" },
+ { .fc_id = 113, .cpu_id = 64, .valid = 1, .name = "SRAM22_SERR" },
+ { .fc_id = 114, .cpu_id = 64, .valid = 1, .name = "SRAM21_SERR" },
+ { .fc_id = 115, .cpu_id = 64, .valid = 1, .name = "SRAM20_SERR" },
+ { .fc_id = 116, .cpu_id = 64, .valid = 1, .name = "SRAM24_SERR" },
+ { .fc_id = 117, .cpu_id = 64, .valid = 1, .name = "SRAM25_SERR" },
+ { .fc_id = 118, .cpu_id = 64, .valid = 1, .name = "SRAM26_SERR" },
+ { .fc_id = 119, .cpu_id = 64, .valid = 1, .name = "SRAM27_SERR" },
+ { .fc_id = 120, .cpu_id = 64, .valid = 1, .name = "SRAM31_SERR" },
+ { .fc_id = 121, .cpu_id = 64, .valid = 1, .name = "SRAM30_SERR" },
+ { .fc_id = 122, .cpu_id = 64, .valid = 1, .name = "SRAM29_SERR" },
+ { .fc_id = 123, .cpu_id = 64, .valid = 1, .name = "SRAM28_SERR" },
+ { .fc_id = 124, .cpu_id = 65, .valid = 1, .name = "SRAM0_DERR" },
+ { .fc_id = 125, .cpu_id = 65, .valid = 1, .name = "SRAM1_DERR" },
+ { .fc_id = 126, .cpu_id = 65, .valid = 1, .name = "SRAM2_DERR" },
+ { .fc_id = 127, .cpu_id = 65, .valid = 1, .name = "SRAM3_DERR" },
+ { .fc_id = 128, .cpu_id = 65, .valid = 1, .name = "SRAM7_DERR" },
+ { .fc_id = 129, .cpu_id = 65, .valid = 1, .name = "SRAM6_DERR" },
+ { .fc_id = 130, .cpu_id = 65, .valid = 1, .name = "SRAM5_DERR" },
+ { .fc_id = 131, .cpu_id = 65, .valid = 1, .name = "SRAM4_DERR" },
+ { .fc_id = 132, .cpu_id = 65, .valid = 1, .name = "SRAM8_DERR" },
+ { .fc_id = 133, .cpu_id = 65, .valid = 1, .name = "SRAM9_DERR" },
+ { .fc_id = 134, .cpu_id = 65, .valid = 1, .name = "SRAM10_DERR" },
+ { .fc_id = 135, .cpu_id = 65, .valid = 1, .name = "SRAM11_DERR" },
+ { .fc_id = 136, .cpu_id = 65, .valid = 1, .name = "SRAM15_DERR" },
+ { .fc_id = 137, .cpu_id = 65, .valid = 1, .name = "SRAM14_DERR" },
+ { .fc_id = 138, .cpu_id = 65, .valid = 1, .name = "SRAM13_DERR" },
+ { .fc_id = 139, .cpu_id = 65, .valid = 1, .name = "SRAM12_DERR" },
+ { .fc_id = 140, .cpu_id = 65, .valid = 1, .name = "SRAM16_DERR" },
+ { .fc_id = 141, .cpu_id = 65, .valid = 1, .name = "SRAM17_DERR" },
+ { .fc_id = 142, .cpu_id = 65, .valid = 1, .name = "SRAM18_DERR" },
+ { .fc_id = 143, .cpu_id = 65, .valid = 1, .name = "SRAM19_DERR" },
+ { .fc_id = 144, .cpu_id = 65, .valid = 1, .name = "SRAM23_DERR" },
+ { .fc_id = 145, .cpu_id = 65, .valid = 1, .name = "SRAM22_DERR" },
+ { .fc_id = 146, .cpu_id = 65, .valid = 1, .name = "SRAM21_DERR" },
+ { .fc_id = 147, .cpu_id = 65, .valid = 1, .name = "SRAM20_DERR" },
+ { .fc_id = 148, .cpu_id = 65, .valid = 1, .name = "SRAM24_DERR" },
+ { .fc_id = 149, .cpu_id = 65, .valid = 1, .name = "SRAM25_DERR" },
+ { .fc_id = 150, .cpu_id = 65, .valid = 1, .name = "SRAM26_DERR" },
+ { .fc_id = 151, .cpu_id = 65, .valid = 1, .name = "SRAM27_DERR" },
+ { .fc_id = 152, .cpu_id = 65, .valid = 1, .name = "SRAM31_DERR" },
+ { .fc_id = 153, .cpu_id = 65, .valid = 1, .name = "SRAM30_DERR" },
+ { .fc_id = 154, .cpu_id = 65, .valid = 1, .name = "SRAM29_DERR" },
+ { .fc_id = 155, .cpu_id = 65, .valid = 1, .name = "SRAM28_DERR" },
+ { .fc_id = 156, .cpu_id = 66, .valid = 1, .name = "NIC0_SERR" },
+ { .fc_id = 157, .cpu_id = 66, .valid = 1, .name = "NIC1_SERR" },
+ { .fc_id = 158, .cpu_id = 66, .valid = 1, .name = "NIC2_SERR" },
+ { .fc_id = 159, .cpu_id = 66, .valid = 1, .name = "NIC3_SERR" },
+ { .fc_id = 160, .cpu_id = 66, .valid = 1, .name = "NIC4_SERR" },
+ { .fc_id = 161, .cpu_id = 66, .valid = 0, .name = "" },
+ { .fc_id = 162, .cpu_id = 66, .valid = 0, .name = "" },
+ { .fc_id = 163, .cpu_id = 66, .valid = 0, .name = "" },
+ { .fc_id = 164, .cpu_id = 66, .valid = 0, .name = "" },
+ { .fc_id = 165, .cpu_id = 66, .valid = 0, .name = "" },
+ { .fc_id = 166, .cpu_id = 67, .valid = 1, .name = "NIC0_DERR" },
+ { .fc_id = 167, .cpu_id = 67, .valid = 1, .name = "NIC1_DERR" },
+ { .fc_id = 168, .cpu_id = 67, .valid = 1, .name = "NIC2_DERR" },
+ { .fc_id = 169, .cpu_id = 67, .valid = 1, .name = "NIC3_DERR" },
+ { .fc_id = 170, .cpu_id = 67, .valid = 1, .name = "NIC4_DERR" },
+ { .fc_id = 171, .cpu_id = 67, .valid = 0, .name = "" },
+ { .fc_id = 172, .cpu_id = 67, .valid = 0, .name = "" },
+ { .fc_id = 173, .cpu_id = 67, .valid = 0, .name = "" },
+ { .fc_id = 174, .cpu_id = 67, .valid = 0, .name = "" },
+ { .fc_id = 175, .cpu_id = 67, .valid = 0, .name = "" },
+ { .fc_id = 176, .cpu_id = 68, .valid = 1, .name = "DMA_IF0_SERR" },
+ { .fc_id = 177, .cpu_id = 68, .valid = 1, .name = "DMA_IF1_SERR" },
+ { .fc_id = 178, .cpu_id = 68, .valid = 1, .name = "DMA_IF2_SERR" },
+ { .fc_id = 179, .cpu_id = 68, .valid = 1, .name = "DMA_IF3_SERR" },
+ { .fc_id = 180, .cpu_id = 69, .valid = 1, .name = "DMA_IF0_DERR" },
+ { .fc_id = 181, .cpu_id = 69, .valid = 1, .name = "DMA_IF1_DERR" },
+ { .fc_id = 182, .cpu_id = 69, .valid = 1, .name = "DMA_IF2_DERR" },
+ { .fc_id = 183, .cpu_id = 69, .valid = 1, .name = "DMA_IF3_DERR" },
+ { .fc_id = 184, .cpu_id = 70, .valid = 1, .name = "GIC500" },
+ { .fc_id = 185, .cpu_id = 71, .valid = 1, .name = "HBM_0_SERR" },
+ { .fc_id = 186, .cpu_id = 71, .valid = 1, .name = "HBM_1_SERR" },
+ { .fc_id = 187, .cpu_id = 71, .valid = 1, .name = "HBM_2_SERR" },
+ { .fc_id = 188, .cpu_id = 71, .valid = 1, .name = "HBM_3_SERR" },
+ { .fc_id = 189, .cpu_id = 72, .valid = 1, .name = "HBM_0_DERR" },
+ { .fc_id = 190, .cpu_id = 72, .valid = 1, .name = "HBM_1_DERR" },
+ { .fc_id = 191, .cpu_id = 72, .valid = 1, .name = "HBM_2_DERR" },
+ { .fc_id = 192, .cpu_id = 72, .valid = 1, .name = "HBM_3_DERR" },
+ { .fc_id = 193, .cpu_id = 73, .valid = 1, .name = "MMU_SERR" },
+ { .fc_id = 194, .cpu_id = 74, .valid = 1, .name = "MMU_DERR" },
+ { .fc_id = 195, .cpu_id = 75, .valid = 0, .name = "" },
+ { .fc_id = 196, .cpu_id = 76, .valid = 0, .name = "" },
+ { .fc_id = 197, .cpu_id = 77, .valid = 0, .name = "" },
+ { .fc_id = 198, .cpu_id = 78, .valid = 0, .name = "" },
+ { .fc_id = 199, .cpu_id = 79, .valid = 0, .name = "" },
+ { .fc_id = 200, .cpu_id = 80, .valid = 1, .name = "PCIE_DEC" },
+ { .fc_id = 201, .cpu_id = 81, .valid = 1, .name = "TPC0_DEC" },
+ { .fc_id = 202, .cpu_id = 82, .valid = 0, .name = "" },
+ { .fc_id = 203, .cpu_id = 83, .valid = 1, .name = "TPC1_DEC" },
+ { .fc_id = 204, .cpu_id = 84, .valid = 0, .name = "" },
+ { .fc_id = 205, .cpu_id = 85, .valid = 1, .name = "TPC2_DEC" },
+ { .fc_id = 206, .cpu_id = 86, .valid = 0, .name = "" },
+ { .fc_id = 207, .cpu_id = 87, .valid = 1, .name = "TPC3_DEC" },
+ { .fc_id = 208, .cpu_id = 88, .valid = 0, .name = "" },
+ { .fc_id = 209, .cpu_id = 89, .valid = 1, .name = "TPC4_DEC" },
+ { .fc_id = 210, .cpu_id = 90, .valid = 0, .name = "" },
+ { .fc_id = 211, .cpu_id = 91, .valid = 1, .name = "TPC5_DEC" },
+ { .fc_id = 212, .cpu_id = 92, .valid = 0, .name = "" },
+ { .fc_id = 213, .cpu_id = 93, .valid = 1, .name = "TPC6_DEC" },
+ { .fc_id = 214, .cpu_id = 94, .valid = 0, .name = "" },
+ { .fc_id = 215, .cpu_id = 95, .valid = 1, .name = "TPC7_DEC" },
+ { .fc_id = 216, .cpu_id = 96, .valid = 0, .name = "" },
+ { .fc_id = 217, .cpu_id = 97, .valid = 1, .name = "AXI_ECC" },
+ { .fc_id = 218, .cpu_id = 98, .valid = 1, .name = "L2_RAM_ECC" },
+ { .fc_id = 219, .cpu_id = 99, .valid = 1, .name = "MME0_WBC_RSP" },
+ { .fc_id = 220, .cpu_id = 100, .valid = 1, .name = "MME0_SBAB0_RSP" },
+ { .fc_id = 221, .cpu_id = 101, .valid = 0, .name = "" },
+ { .fc_id = 222, .cpu_id = 102, .valid = 0, .name = "" },
+ { .fc_id = 223, .cpu_id = 103, .valid = 0, .name = "" },
+ { .fc_id = 224, .cpu_id = 104, .valid = 1, .name = "MME1_WBC_RSP" },
+ { .fc_id = 225, .cpu_id = 105, .valid = 1, .name = "MME1_SBAB0_RSP" },
+ { .fc_id = 226, .cpu_id = 106, .valid = 0, .name = "" },
+ { .fc_id = 227, .cpu_id = 107, .valid = 0, .name = "" },
+ { .fc_id = 228, .cpu_id = 108, .valid = 0, .name = "" },
+ { .fc_id = 229, .cpu_id = 109, .valid = 1, .name = "MME2_WBC_RSP" },
+ { .fc_id = 230, .cpu_id = 110, .valid = 1, .name = "MME2_SBAB0_RSP" },
+ { .fc_id = 231, .cpu_id = 111, .valid = 0, .name = "" },
+ { .fc_id = 232, .cpu_id = 112, .valid = 0, .name = "" },
+ { .fc_id = 233, .cpu_id = 113, .valid = 0, .name = "" },
+ { .fc_id = 234, .cpu_id = 114, .valid = 1, .name = "MME3_WBC_RSP" },
+ { .fc_id = 235, .cpu_id = 115, .valid = 1, .name = "MME3_SBAB0_RSP" },
+ { .fc_id = 236, .cpu_id = 116, .valid = 0, .name = "" },
+ { .fc_id = 237, .cpu_id = 117, .valid = 0, .name = "" },
+ { .fc_id = 238, .cpu_id = 118, .valid = 0, .name = "" },
+ { .fc_id = 239, .cpu_id = 119, .valid = 1, .name = "PLL0" },
+ { .fc_id = 240, .cpu_id = 119, .valid = 1, .name = "PLL1" },
+ { .fc_id = 241, .cpu_id = 119, .valid = 1, .name = "PLL2" },
+ { .fc_id = 242, .cpu_id = 119, .valid = 1, .name = "PLL3" },
+ { .fc_id = 243, .cpu_id = 119, .valid = 1, .name = "PLL4" },
+ { .fc_id = 244, .cpu_id = 119, .valid = 1, .name = "PLL5" },
+ { .fc_id = 245, .cpu_id = 119, .valid = 1, .name = "PLL6" },
+ { .fc_id = 246, .cpu_id = 119, .valid = 1, .name = "PLL7" },
+ { .fc_id = 247, .cpu_id = 119, .valid = 1, .name = "PLL8" },
+ { .fc_id = 248, .cpu_id = 119, .valid = 1, .name = "PLL9" },
+ { .fc_id = 249, .cpu_id = 119, .valid = 1, .name = "PLL10" },
+ { .fc_id = 250, .cpu_id = 119, .valid = 1, .name = "PLL11" },
+ { .fc_id = 251, .cpu_id = 119, .valid = 1, .name = "PLL12" },
+ { .fc_id = 252, .cpu_id = 119, .valid = 1, .name = "PLL13" },
+ { .fc_id = 253, .cpu_id = 119, .valid = 1, .name = "PLL14" },
+ { .fc_id = 254, .cpu_id = 119, .valid = 1, .name = "PLL15" },
+ { .fc_id = 255, .cpu_id = 119, .valid = 1, .name = "PLL16" },
+ { .fc_id = 256, .cpu_id = 119, .valid = 1, .name = "PLL17" },
+ { .fc_id = 257, .cpu_id = 120, .valid = 1,
+ .name = "CPU_AXI_SPLITTER" },
+ { .fc_id = 258, .cpu_id = 121, .valid = 0, .name = "" },
+ { .fc_id = 259, .cpu_id = 122, .valid = 0, .name = "" },
+ { .fc_id = 260, .cpu_id = 123, .valid = 0, .name = "" },
+ { .fc_id = 261, .cpu_id = 124, .valid = 0, .name = "" },
+ { .fc_id = 262, .cpu_id = 125, .valid = 1, .name = "PSOC_AXI_DEC" },
+ { .fc_id = 263, .cpu_id = 126, .valid = 1, .name = "PSOC_PRSTN_FALL" },
+ { .fc_id = 264, .cpu_id = 127, .valid = 1, .name = "NIC_SEI_0" },
+ { .fc_id = 265, .cpu_id = 127, .valid = 1, .name = "NIC_SEI_1" },
+ { .fc_id = 266, .cpu_id = 127, .valid = 1, .name = "NIC_SEI_2" },
+ { .fc_id = 267, .cpu_id = 127, .valid = 1, .name = "NIC_SEI_3" },
+ { .fc_id = 268, .cpu_id = 127, .valid = 1, .name = "NIC_SEI_4" },
+ { .fc_id = 269, .cpu_id = 128, .valid = 0, .name = "" },
+ { .fc_id = 270, .cpu_id = 128, .valid = 0, .name = "" },
+ { .fc_id = 271, .cpu_id = 128, .valid = 0, .name = "" },
+ { .fc_id = 272, .cpu_id = 128, .valid = 0, .name = "" },
+ { .fc_id = 273, .cpu_id = 128, .valid = 0, .name = "" },
+ { .fc_id = 274, .cpu_id = 128, .valid = 0, .name = "" },
+ { .fc_id = 275, .cpu_id = 128, .valid = 0, .name = "" },
+ { .fc_id = 276, .cpu_id = 128, .valid = 0, .name = "" },
+ { .fc_id = 277, .cpu_id = 129, .valid = 1, .name = "DMA_IF_SEI_0" },
+ { .fc_id = 278, .cpu_id = 129, .valid = 1, .name = "DMA_IF_SEI_1" },
+ { .fc_id = 279, .cpu_id = 129, .valid = 1, .name = "DMA_IF_SEI_2" },
+ { .fc_id = 280, .cpu_id = 129, .valid = 1, .name = "DMA_IF_SEI_3" },
+ { .fc_id = 281, .cpu_id = 130, .valid = 0, .name = "" },
+ { .fc_id = 282, .cpu_id = 131, .valid = 0, .name = "" },
+ { .fc_id = 283, .cpu_id = 132, .valid = 0, .name = "" },
+ { .fc_id = 284, .cpu_id = 133, .valid = 0, .name = "" },
+ { .fc_id = 285, .cpu_id = 134, .valid = 0, .name = "" },
+ { .fc_id = 286, .cpu_id = 135, .valid = 0, .name = "" },
+ { .fc_id = 287, .cpu_id = 136, .valid = 0, .name = "" },
+ { .fc_id = 288, .cpu_id = 137, .valid = 0, .name = "" },
+ { .fc_id = 289, .cpu_id = 138, .valid = 0, .name = "" },
+ { .fc_id = 290, .cpu_id = 139, .valid = 1, .name = "PCIE_FLR" },
+ { .fc_id = 291, .cpu_id = 140, .valid = 0, .name = "" },
+ { .fc_id = 292, .cpu_id = 141, .valid = 0, .name = "" },
+ { .fc_id = 293, .cpu_id = 142, .valid = 0, .name = "" },
+ { .fc_id = 294, .cpu_id = 143, .valid = 0, .name = "" },
+ { .fc_id = 295, .cpu_id = 144, .valid = 0, .name = "" },
+ { .fc_id = 296, .cpu_id = 145, .valid = 0, .name = "" },
+ { .fc_id = 297, .cpu_id = 146, .valid = 0, .name = "" },
+ { .fc_id = 298, .cpu_id = 147, .valid = 0, .name = "" },
+ { .fc_id = 299, .cpu_id = 148, .valid = 0, .name = "" },
+ { .fc_id = 300, .cpu_id = 149, .valid = 1, .name = "TPC0_BMON_SPMU" },
+ { .fc_id = 301, .cpu_id = 150, .valid = 1, .name = "TPC0_KRN_ERR" },
+ { .fc_id = 302, .cpu_id = 151, .valid = 0, .name = "" },
+ { .fc_id = 303, .cpu_id = 152, .valid = 0, .name = "" },
+ { .fc_id = 304, .cpu_id = 153, .valid = 0, .name = "" },
+ { .fc_id = 305, .cpu_id = 154, .valid = 0, .name = "" },
+ { .fc_id = 306, .cpu_id = 155, .valid = 1, .name = "TPC1_BMON_SPMU" },
+ { .fc_id = 307, .cpu_id = 156, .valid = 1, .name = "TPC1_KRN_ERR" },
+ { .fc_id = 308, .cpu_id = 157, .valid = 0, .name = "" },
+ { .fc_id = 309, .cpu_id = 158, .valid = 0, .name = "" },
+ { .fc_id = 310, .cpu_id = 159, .valid = 0, .name = "" },
+ { .fc_id = 311, .cpu_id = 160, .valid = 0, .name = "" },
+ { .fc_id = 312, .cpu_id = 161, .valid = 1, .name = "TPC2_BMON_SPMU" },
+ { .fc_id = 313, .cpu_id = 162, .valid = 1, .name = "TPC2_KRN_ERR" },
+ { .fc_id = 314, .cpu_id = 163, .valid = 0, .name = "" },
+ { .fc_id = 315, .cpu_id = 164, .valid = 0, .name = "" },
+ { .fc_id = 316, .cpu_id = 165, .valid = 0, .name = "" },
+ { .fc_id = 317, .cpu_id = 166, .valid = 0, .name = "" },
+ { .fc_id = 318, .cpu_id = 167, .valid = 1, .name = "TPC3_BMON_SPMU" },
+ { .fc_id = 319, .cpu_id = 168, .valid = 1, .name = "TPC3_KRN_ERR" },
+ { .fc_id = 320, .cpu_id = 169, .valid = 0, .name = "" },
+ { .fc_id = 321, .cpu_id = 170, .valid = 0, .name = "" },
+ { .fc_id = 322, .cpu_id = 171, .valid = 0, .name = "" },
+ { .fc_id = 323, .cpu_id = 172, .valid = 0, .name = "" },
+ { .fc_id = 324, .cpu_id = 173, .valid = 1, .name = "TPC4_BMON_SPMU" },
+ { .fc_id = 325, .cpu_id = 174, .valid = 1, .name = "TPC4_KRN_ERR" },
+ { .fc_id = 326, .cpu_id = 175, .valid = 0, .name = "" },
+ { .fc_id = 327, .cpu_id = 176, .valid = 0, .name = "" },
+ { .fc_id = 328, .cpu_id = 177, .valid = 0, .name = "" },
+ { .fc_id = 329, .cpu_id = 178, .valid = 0, .name = "" },
+ { .fc_id = 330, .cpu_id = 179, .valid = 1, .name = "TPC5_BMON_SPMU" },
+ { .fc_id = 331, .cpu_id = 180, .valid = 1, .name = "TPC5_KRN_ERR" },
+ { .fc_id = 332, .cpu_id = 181, .valid = 0, .name = "" },
+ { .fc_id = 333, .cpu_id = 182, .valid = 0, .name = "" },
+ { .fc_id = 334, .cpu_id = 183, .valid = 0, .name = "" },
+ { .fc_id = 335, .cpu_id = 184, .valid = 0, .name = "" },
+ { .fc_id = 336, .cpu_id = 185, .valid = 1, .name = "TPC6_BMON_SPMU" },
+ { .fc_id = 337, .cpu_id = 186, .valid = 1, .name = "TPC6_KRN_ERR" },
+ { .fc_id = 338, .cpu_id = 187, .valid = 0, .name = "" },
+ { .fc_id = 339, .cpu_id = 188, .valid = 0, .name = "" },
+ { .fc_id = 340, .cpu_id = 189, .valid = 0, .name = "" },
+ { .fc_id = 341, .cpu_id = 190, .valid = 0, .name = "" },
+ { .fc_id = 342, .cpu_id = 191, .valid = 1, .name = "TPC7_BMON_SPMU" },
+ { .fc_id = 343, .cpu_id = 192, .valid = 1, .name = "TPC7_KRN_ERR" },
+ { .fc_id = 344, .cpu_id = 193, .valid = 0, .name = "" },
+ { .fc_id = 345, .cpu_id = 194, .valid = 0, .name = "" },
+ { .fc_id = 346, .cpu_id = 195, .valid = 0, .name = "" },
+ { .fc_id = 347, .cpu_id = 196, .valid = 0, .name = "" },
+ { .fc_id = 348, .cpu_id = 197, .valid = 0, .name = "" },
+ { .fc_id = 349, .cpu_id = 198, .valid = 0, .name = "" },
+ { .fc_id = 350, .cpu_id = 199, .valid = 0, .name = "" },
+ { .fc_id = 351, .cpu_id = 200, .valid = 0, .name = "" },
+ { .fc_id = 352, .cpu_id = 201, .valid = 0, .name = "" },
+ { .fc_id = 353, .cpu_id = 202, .valid = 0, .name = "" },
+ { .fc_id = 354, .cpu_id = 203, .valid = 0, .name = "" },
+ { .fc_id = 355, .cpu_id = 204, .valid = 0, .name = "" },
+ { .fc_id = 356, .cpu_id = 205, .valid = 0, .name = "" },
+ { .fc_id = 357, .cpu_id = 206, .valid = 0, .name = "" },
+ { .fc_id = 358, .cpu_id = 207, .valid = 0, .name = "" },
+ { .fc_id = 359, .cpu_id = 208, .valid = 0, .name = "" },
+ { .fc_id = 360, .cpu_id = 209, .valid = 0, .name = "" },
+ { .fc_id = 361, .cpu_id = 210, .valid = 0, .name = "" },
+ { .fc_id = 362, .cpu_id = 211, .valid = 0, .name = "" },
+ { .fc_id = 363, .cpu_id = 212, .valid = 0, .name = "" },
+ { .fc_id = 364, .cpu_id = 213, .valid = 0, .name = "" },
+ { .fc_id = 365, .cpu_id = 214, .valid = 0, .name = "" },
+ { .fc_id = 366, .cpu_id = 215, .valid = 0, .name = "" },
+ { .fc_id = 367, .cpu_id = 216, .valid = 0, .name = "" },
+ { .fc_id = 368, .cpu_id = 217, .valid = 0, .name = "" },
+ { .fc_id = 369, .cpu_id = 218, .valid = 0, .name = "" },
+ { .fc_id = 370, .cpu_id = 219, .valid = 0, .name = "" },
+ { .fc_id = 371, .cpu_id = 220, .valid = 0, .name = "" },
+ { .fc_id = 372, .cpu_id = 221, .valid = 0, .name = "" },
+ { .fc_id = 373, .cpu_id = 222, .valid = 0, .name = "" },
+ { .fc_id = 374, .cpu_id = 223, .valid = 0, .name = "" },
+ { .fc_id = 375, .cpu_id = 224, .valid = 0, .name = "" },
+ { .fc_id = 376, .cpu_id = 225, .valid = 0, .name = "" },
+ { .fc_id = 377, .cpu_id = 226, .valid = 0, .name = "" },
+ { .fc_id = 378, .cpu_id = 227, .valid = 0, .name = "" },
+ { .fc_id = 379, .cpu_id = 228, .valid = 0, .name = "" },
+ { .fc_id = 380, .cpu_id = 229, .valid = 1, .name = "MMU_PAGE_FAULT" },
+ { .fc_id = 381, .cpu_id = 230, .valid = 1, .name = "MMU_WR_PERM" },
+ { .fc_id = 382, .cpu_id = 231, .valid = 0, .name = "" },
+ { .fc_id = 383, .cpu_id = 232, .valid = 1, .name = "DMA_BM_CH0" },
+ { .fc_id = 384, .cpu_id = 233, .valid = 1, .name = "DMA_BM_CH1" },
+ { .fc_id = 385, .cpu_id = 234, .valid = 1, .name = "DMA_BM_CH2" },
+ { .fc_id = 386, .cpu_id = 235, .valid = 1, .name = "DMA_BM_CH3" },
+ { .fc_id = 387, .cpu_id = 236, .valid = 1, .name = "DMA_BM_CH4" },
+ { .fc_id = 388, .cpu_id = 237, .valid = 1, .name = "DMA_BM_CH5" },
+ { .fc_id = 389, .cpu_id = 238, .valid = 1, .name = "DMA_BM_CH6" },
+ { .fc_id = 390, .cpu_id = 239, .valid = 1, .name = "DMA_BM_CH7" },
+ { .fc_id = 391, .cpu_id = 240, .valid = 0, .name = "" },
+ { .fc_id = 392, .cpu_id = 241, .valid = 0, .name = "" },
+ { .fc_id = 393, .cpu_id = 242, .valid = 0, .name = "" },
+ { .fc_id = 394, .cpu_id = 243, .valid = 0, .name = "" },
+ { .fc_id = 395, .cpu_id = 244, .valid = 1, .name = "HBM0_SPI_0" },
+ { .fc_id = 396, .cpu_id = 245, .valid = 1, .name = "HBM0_SPI_1" },
+ { .fc_id = 397, .cpu_id = 246, .valid = 0, .name = "" },
+ { .fc_id = 398, .cpu_id = 247, .valid = 0, .name = "" },
+ { .fc_id = 399, .cpu_id = 248, .valid = 1, .name = "HBM1_SPI_0" },
+ { .fc_id = 400, .cpu_id = 249, .valid = 1, .name = "HBM1_SPI_1" },
+ { .fc_id = 401, .cpu_id = 250, .valid = 0, .name = "" },
+ { .fc_id = 402, .cpu_id = 251, .valid = 0, .name = "" },
+ { .fc_id = 403, .cpu_id = 252, .valid = 1, .name = "HBM2_SPI_0" },
+ { .fc_id = 404, .cpu_id = 253, .valid = 1, .name = "HBM2_SPI_1" },
+ { .fc_id = 405, .cpu_id = 254, .valid = 0, .name = "" },
+ { .fc_id = 406, .cpu_id = 255, .valid = 0, .name = "" },
+ { .fc_id = 407, .cpu_id = 256, .valid = 1, .name = "HBM3_SPI_0" },
+ { .fc_id = 408, .cpu_id = 257, .valid = 1, .name = "HBM3_SPI_1" },
+ { .fc_id = 409, .cpu_id = 258, .valid = 0, .name = "" },
+ { .fc_id = 410, .cpu_id = 259, .valid = 0, .name = "" },
+ { .fc_id = 411, .cpu_id = 260, .valid = 0, .name = "" },
+ { .fc_id = 412, .cpu_id = 261, .valid = 0, .name = "" },
+ { .fc_id = 413, .cpu_id = 262, .valid = 0, .name = "" },
+ { .fc_id = 414, .cpu_id = 263, .valid = 0, .name = "" },
+ { .fc_id = 415, .cpu_id = 264, .valid = 0, .name = "" },
+ { .fc_id = 416, .cpu_id = 265, .valid = 0, .name = "" },
+ { .fc_id = 417, .cpu_id = 266, .valid = 0, .name = "" },
+ { .fc_id = 418, .cpu_id = 267, .valid = 0, .name = "" },
+ { .fc_id = 419, .cpu_id = 268, .valid = 0, .name = "" },
+ { .fc_id = 420, .cpu_id = 269, .valid = 0, .name = "" },
+ { .fc_id = 421, .cpu_id = 270, .valid = 1, .name = "PSOC_GPIO_U16_0" },
+ { .fc_id = 422, .cpu_id = 271, .valid = 0, .name = "" },
+ { .fc_id = 423, .cpu_id = 272, .valid = 0, .name = "" },
+ { .fc_id = 424, .cpu_id = 273, .valid = 0, .name = "" },
+ { .fc_id = 425, .cpu_id = 274, .valid = 0, .name = "" },
+ { .fc_id = 426, .cpu_id = 275, .valid = 0, .name = "" },
+ { .fc_id = 427, .cpu_id = 276, .valid = 0, .name = "" },
+ { .fc_id = 428, .cpu_id = 277, .valid = 0, .name = "" },
+ { .fc_id = 429, .cpu_id = 278, .valid = 0, .name = "" },
+ { .fc_id = 430, .cpu_id = 279, .valid = 0, .name = "" },
+ { .fc_id = 431, .cpu_id = 280, .valid = 0, .name = "" },
+ { .fc_id = 432, .cpu_id = 281, .valid = 0, .name = "" },
+ { .fc_id = 433, .cpu_id = 282, .valid = 0, .name = "" },
+ { .fc_id = 434, .cpu_id = 283, .valid = 0, .name = "" },
+ { .fc_id = 435, .cpu_id = 284, .valid = 0, .name = "" },
+ { .fc_id = 436, .cpu_id = 285, .valid = 0, .name = "" },
+ { .fc_id = 437, .cpu_id = 286, .valid = 0, .name = "" },
+ { .fc_id = 438, .cpu_id = 287, .valid = 0, .name = "" },
+ { .fc_id = 439, .cpu_id = 288, .valid = 0, .name = "" },
+ { .fc_id = 440, .cpu_id = 289, .valid = 0, .name = "" },
+ { .fc_id = 441, .cpu_id = 290, .valid = 0, .name = "" },
+ { .fc_id = 442, .cpu_id = 291, .valid = 0, .name = "" },
+ { .fc_id = 443, .cpu_id = 292, .valid = 0, .name = "" },
+ { .fc_id = 444, .cpu_id = 293, .valid = 0, .name = "" },
+ { .fc_id = 445, .cpu_id = 294, .valid = 0, .name = "" },
+ { .fc_id = 446, .cpu_id = 295, .valid = 0, .name = "" },
+ { .fc_id = 447, .cpu_id = 296, .valid = 0, .name = "" },
+ { .fc_id = 448, .cpu_id = 297, .valid = 0, .name = "" },
+ { .fc_id = 449, .cpu_id = 298, .valid = 0, .name = "" },
+ { .fc_id = 450, .cpu_id = 299, .valid = 0, .name = "" },
+ { .fc_id = 451, .cpu_id = 300, .valid = 0, .name = "" },
+ { .fc_id = 452, .cpu_id = 301, .valid = 0, .name = "" },
+ { .fc_id = 453, .cpu_id = 302, .valid = 0, .name = "" },
+ { .fc_id = 454, .cpu_id = 303, .valid = 0, .name = "" },
+ { .fc_id = 455, .cpu_id = 304, .valid = 0, .name = "" },
+ { .fc_id = 456, .cpu_id = 305, .valid = 0, .name = "" },
+ { .fc_id = 457, .cpu_id = 306, .valid = 0, .name = "" },
+ { .fc_id = 458, .cpu_id = 307, .valid = 0, .name = "" },
+ { .fc_id = 459, .cpu_id = 308, .valid = 0, .name = "" },
+ { .fc_id = 460, .cpu_id = 309, .valid = 0, .name = "" },
+ { .fc_id = 461, .cpu_id = 310, .valid = 0, .name = "" },
+ { .fc_id = 462, .cpu_id = 311, .valid = 0, .name = "" },
+ { .fc_id = 463, .cpu_id = 312, .valid = 0, .name = "" },
+ { .fc_id = 464, .cpu_id = 313, .valid = 0, .name = "" },
+ { .fc_id = 465, .cpu_id = 314, .valid = 0, .name = "" },
+ { .fc_id = 466, .cpu_id = 315, .valid = 0, .name = "" },
+ { .fc_id = 467, .cpu_id = 316, .valid = 0, .name = "" },
+ { .fc_id = 468, .cpu_id = 317, .valid = 0, .name = "" },
+ { .fc_id = 469, .cpu_id = 318, .valid = 0, .name = "" },
+ { .fc_id = 470, .cpu_id = 319, .valid = 0, .name = "" },
+ { .fc_id = 471, .cpu_id = 320, .valid = 0, .name = "" },
+ { .fc_id = 472, .cpu_id = 321, .valid = 0, .name = "" },
+ { .fc_id = 473, .cpu_id = 322, .valid = 0, .name = "" },
+ { .fc_id = 474, .cpu_id = 323, .valid = 0, .name = "" },
+ { .fc_id = 475, .cpu_id = 324, .valid = 0, .name = "" },
+ { .fc_id = 476, .cpu_id = 325, .valid = 0, .name = "" },
+ { .fc_id = 477, .cpu_id = 326, .valid = 0, .name = "" },
+ { .fc_id = 478, .cpu_id = 327, .valid = 0, .name = "" },
+ { .fc_id = 479, .cpu_id = 328, .valid = 0, .name = "" },
+ { .fc_id = 480, .cpu_id = 329, .valid = 0, .name = "" },
+ { .fc_id = 481, .cpu_id = 330, .valid = 0, .name = "" },
+ { .fc_id = 482, .cpu_id = 331, .valid = 0, .name = "" },
+ { .fc_id = 483, .cpu_id = 332, .valid = 1,
+ .name = "NIC0_CS_DBG_DERR" },
+ { .fc_id = 484, .cpu_id = 333, .valid = 0, .name = "" },
+ { .fc_id = 485, .cpu_id = 334, .valid = 0, .name = "" },
+ { .fc_id = 486, .cpu_id = 335, .valid = 0, .name = "" },
+ { .fc_id = 487, .cpu_id = 336, .valid = 1,
+ .name = "NIC1_CS_DBG_DERR" },
+ { .fc_id = 488, .cpu_id = 337, .valid = 0, .name = "" },
+ { .fc_id = 489, .cpu_id = 338, .valid = 0, .name = "" },
+ { .fc_id = 490, .cpu_id = 339, .valid = 0, .name = "" },
+ { .fc_id = 491, .cpu_id = 340, .valid = 1,
+ .name = "NIC2_CS_DBG_DERR" },
+ { .fc_id = 492, .cpu_id = 341, .valid = 0, .name = "" },
+ { .fc_id = 493, .cpu_id = 342, .valid = 0, .name = "" },
+ { .fc_id = 494, .cpu_id = 343, .valid = 0, .name = "" },
+ { .fc_id = 495, .cpu_id = 344, .valid = 1,
+ .name = "NIC3_CS_DBG_DERR" },
+ { .fc_id = 496, .cpu_id = 345, .valid = 0, .name = "" },
+ { .fc_id = 497, .cpu_id = 346, .valid = 0, .name = "" },
+ { .fc_id = 498, .cpu_id = 347, .valid = 0, .name = "" },
+ { .fc_id = 499, .cpu_id = 348, .valid = 1,
+ .name = "NIC4_CS_DBG_DERR" },
+ { .fc_id = 500, .cpu_id = 349, .valid = 0, .name = "" },
+ { .fc_id = 501, .cpu_id = 350, .valid = 0, .name = "" },
+ { .fc_id = 502, .cpu_id = 351, .valid = 0, .name = "" },
+ { .fc_id = 503, .cpu_id = 352, .valid = 0, .name = "" },
+ { .fc_id = 504, .cpu_id = 353, .valid = 0, .name = "" },
+ { .fc_id = 505, .cpu_id = 354, .valid = 0, .name = "" },
+ { .fc_id = 506, .cpu_id = 355, .valid = 0, .name = "" },
+ { .fc_id = 507, .cpu_id = 356, .valid = 0, .name = "" },
+ { .fc_id = 508, .cpu_id = 357, .valid = 0, .name = "" },
+ { .fc_id = 509, .cpu_id = 358, .valid = 0, .name = "" },
+ { .fc_id = 510, .cpu_id = 359, .valid = 0, .name = "" },
+ { .fc_id = 511, .cpu_id = 360, .valid = 0, .name = "" },
+ { .fc_id = 512, .cpu_id = 361, .valid = 0, .name = "" },
+ { .fc_id = 513, .cpu_id = 362, .valid = 0, .name = "" },
+ { .fc_id = 514, .cpu_id = 363, .valid = 0, .name = "" },
+ { .fc_id = 515, .cpu_id = 364, .valid = 0, .name = "" },
+ { .fc_id = 516, .cpu_id = 365, .valid = 0, .name = "" },
+ { .fc_id = 517, .cpu_id = 366, .valid = 0, .name = "" },
+ { .fc_id = 518, .cpu_id = 367, .valid = 0, .name = "" },
+ { .fc_id = 519, .cpu_id = 368, .valid = 0, .name = "" },
+ { .fc_id = 520, .cpu_id = 369, .valid = 0, .name = "" },
+ { .fc_id = 521, .cpu_id = 370, .valid = 0, .name = "" },
+ { .fc_id = 522, .cpu_id = 371, .valid = 0, .name = "" },
+ { .fc_id = 523, .cpu_id = 372, .valid = 0, .name = "" },
+ { .fc_id = 524, .cpu_id = 373, .valid = 0, .name = "" },
+ { .fc_id = 525, .cpu_id = 374, .valid = 0, .name = "" },
+ { .fc_id = 526, .cpu_id = 375, .valid = 0, .name = "" },
+ { .fc_id = 527, .cpu_id = 376, .valid = 0, .name = "" },
+ { .fc_id = 528, .cpu_id = 377, .valid = 0, .name = "" },
+ { .fc_id = 529, .cpu_id = 378, .valid = 0, .name = "" },
+ { .fc_id = 530, .cpu_id = 379, .valid = 0, .name = "" },
+ { .fc_id = 531, .cpu_id = 380, .valid = 0, .name = "" },
+ { .fc_id = 532, .cpu_id = 381, .valid = 0, .name = "" },
+ { .fc_id = 533, .cpu_id = 382, .valid = 0, .name = "" },
+ { .fc_id = 534, .cpu_id = 383, .valid = 0, .name = "" },
+ { .fc_id = 535, .cpu_id = 384, .valid = 0, .name = "" },
+ { .fc_id = 536, .cpu_id = 385, .valid = 0, .name = "" },
+ { .fc_id = 537, .cpu_id = 386, .valid = 0, .name = "" },
+ { .fc_id = 538, .cpu_id = 387, .valid = 0, .name = "" },
+ { .fc_id = 539, .cpu_id = 388, .valid = 0, .name = "" },
+ { .fc_id = 540, .cpu_id = 389, .valid = 0, .name = "" },
+ { .fc_id = 541, .cpu_id = 390, .valid = 0, .name = "" },
+ { .fc_id = 542, .cpu_id = 391, .valid = 0, .name = "" },
+ { .fc_id = 543, .cpu_id = 392, .valid = 0, .name = "" },
+ { .fc_id = 544, .cpu_id = 393, .valid = 0, .name = "" },
+ { .fc_id = 545, .cpu_id = 394, .valid = 0, .name = "" },
+ { .fc_id = 546, .cpu_id = 395, .valid = 0, .name = "" },
+ { .fc_id = 547, .cpu_id = 396, .valid = 0, .name = "" },
+ { .fc_id = 548, .cpu_id = 397, .valid = 1, .name = "RAZWI_OR_ADC" },
+ { .fc_id = 549, .cpu_id = 398, .valid = 0, .name = "" },
+ { .fc_id = 550, .cpu_id = 399, .valid = 0, .name = "" },
+ { .fc_id = 551, .cpu_id = 400, .valid = 0, .name = "" },
+ { .fc_id = 552, .cpu_id = 401, .valid = 0, .name = "" },
+ { .fc_id = 553, .cpu_id = 402, .valid = 0, .name = "" },
+ { .fc_id = 554, .cpu_id = 403, .valid = 0, .name = "" },
+ { .fc_id = 555, .cpu_id = 404, .valid = 0, .name = "" },
+ { .fc_id = 556, .cpu_id = 405, .valid = 0, .name = "" },
+ { .fc_id = 557, .cpu_id = 406, .valid = 0, .name = "" },
+ { .fc_id = 558, .cpu_id = 407, .valid = 0, .name = "" },
+ { .fc_id = 559, .cpu_id = 408, .valid = 0, .name = "" },
+ { .fc_id = 560, .cpu_id = 409, .valid = 0, .name = "" },
+ { .fc_id = 561, .cpu_id = 410, .valid = 0, .name = "" },
+ { .fc_id = 562, .cpu_id = 411, .valid = 0, .name = "" },
+ { .fc_id = 563, .cpu_id = 412, .valid = 0, .name = "" },
+ { .fc_id = 564, .cpu_id = 413, .valid = 0, .name = "" },
+ { .fc_id = 565, .cpu_id = 414, .valid = 0, .name = "" },
+ { .fc_id = 566, .cpu_id = 415, .valid = 0, .name = "" },
+ { .fc_id = 567, .cpu_id = 416, .valid = 0, .name = "" },
+ { .fc_id = 568, .cpu_id = 417, .valid = 0, .name = "" },
+ { .fc_id = 569, .cpu_id = 418, .valid = 0, .name = "" },
+ { .fc_id = 570, .cpu_id = 419, .valid = 0, .name = "" },
+ { .fc_id = 571, .cpu_id = 420, .valid = 0, .name = "" },
+ { .fc_id = 572, .cpu_id = 421, .valid = 1, .name = "TPC0_QM" },
+ { .fc_id = 573, .cpu_id = 422, .valid = 1, .name = "TPC1_QM" },
+ { .fc_id = 574, .cpu_id = 423, .valid = 1, .name = "TPC2_QM" },
+ { .fc_id = 575, .cpu_id = 424, .valid = 1, .name = "TPC3_QM" },
+ { .fc_id = 576, .cpu_id = 425, .valid = 1, .name = "TPC4_QM" },
+ { .fc_id = 577, .cpu_id = 426, .valid = 1, .name = "TPC5_QM" },
+ { .fc_id = 578, .cpu_id = 427, .valid = 1, .name = "TPC6_QM" },
+ { .fc_id = 579, .cpu_id = 428, .valid = 1, .name = "TPC7_QM" },
+ { .fc_id = 580, .cpu_id = 429, .valid = 0, .name = "" },
+ { .fc_id = 581, .cpu_id = 430, .valid = 1, .name = "MME0_QM" },
+ { .fc_id = 582, .cpu_id = 431, .valid = 1, .name = "MME2_QM" },
+ { .fc_id = 583, .cpu_id = 432, .valid = 1, .name = "DMA0_QM" },
+ { .fc_id = 584, .cpu_id = 433, .valid = 1, .name = "DMA1_QM" },
+ { .fc_id = 585, .cpu_id = 434, .valid = 1, .name = "DMA2_QM" },
+ { .fc_id = 586, .cpu_id = 435, .valid = 1, .name = "DMA3_QM" },
+ { .fc_id = 587, .cpu_id = 436, .valid = 1, .name = "DMA4_QM" },
+ { .fc_id = 588, .cpu_id = 437, .valid = 1, .name = "DMA5_QM" },
+ { .fc_id = 589, .cpu_id = 438, .valid = 1, .name = "DMA6_QM" },
+ { .fc_id = 590, .cpu_id = 439, .valid = 1, .name = "DMA7_QM" },
+ { .fc_id = 591, .cpu_id = 440, .valid = 0, .name = "" },
+ { .fc_id = 592, .cpu_id = 441, .valid = 0, .name = "" },
+ { .fc_id = 593, .cpu_id = 442, .valid = 0, .name = "" },
+ { .fc_id = 594, .cpu_id = 443, .valid = 1, .name = "NIC0_QM0" },
+ { .fc_id = 595, .cpu_id = 444, .valid = 1, .name = "NIC0_QM1" },
+ { .fc_id = 596, .cpu_id = 445, .valid = 1, .name = "NIC1_QM0" },
+ { .fc_id = 597, .cpu_id = 446, .valid = 1, .name = "NIC1_QM1" },
+ { .fc_id = 598, .cpu_id = 447, .valid = 1, .name = "NIC2_QM0" },
+ { .fc_id = 599, .cpu_id = 448, .valid = 1, .name = "NIC2_QM1" },
+ { .fc_id = 600, .cpu_id = 449, .valid = 1, .name = "NIC3_QM0" },
+ { .fc_id = 601, .cpu_id = 450, .valid = 1, .name = "NIC3_QM1" },
+ { .fc_id = 602, .cpu_id = 451, .valid = 1, .name = "NIC4_QM0" },
+ { .fc_id = 603, .cpu_id = 452, .valid = 1, .name = "NIC4_QM1" },
+ { .fc_id = 604, .cpu_id = 453, .valid = 1, .name = "DMA0_CORE" },
+ { .fc_id = 605, .cpu_id = 454, .valid = 1, .name = "DMA1_CORE" },
+ { .fc_id = 606, .cpu_id = 455, .valid = 1, .name = "DMA2_CORE" },
+ { .fc_id = 607, .cpu_id = 456, .valid = 1, .name = "DMA3_CORE" },
+ { .fc_id = 608, .cpu_id = 457, .valid = 1, .name = "DMA4_CORE" },
+ { .fc_id = 609, .cpu_id = 458, .valid = 1, .name = "DMA5_CORE" },
+ { .fc_id = 610, .cpu_id = 459, .valid = 1, .name = "DMA6_CORE" },
+ { .fc_id = 611, .cpu_id = 460, .valid = 1, .name = "DMA7_CORE" },
+ { .fc_id = 612, .cpu_id = 461, .valid = 1, .name = "NIC0_QP0" },
+ { .fc_id = 613, .cpu_id = 462, .valid = 1, .name = "NIC0_QP1" },
+ { .fc_id = 614, .cpu_id = 463, .valid = 1, .name = "NIC1_QP0" },
+ { .fc_id = 615, .cpu_id = 464, .valid = 1, .name = "NIC1_QP1" },
+ { .fc_id = 616, .cpu_id = 465, .valid = 1, .name = "NIC2_QP0" },
+ { .fc_id = 617, .cpu_id = 466, .valid = 1, .name = "NIC2_QP1" },
+ { .fc_id = 618, .cpu_id = 467, .valid = 1, .name = "NIC3_QP0" },
+ { .fc_id = 619, .cpu_id = 468, .valid = 1, .name = "NIC3_QP1" },
+ { .fc_id = 620, .cpu_id = 469, .valid = 1, .name = "NIC4_QP0" },
+ { .fc_id = 621, .cpu_id = 470, .valid = 1, .name = "NIC4_QP1" },
+ { .fc_id = 622, .cpu_id = 471, .valid = 0, .name = "" },
+ { .fc_id = 623, .cpu_id = 472, .valid = 0, .name = "" },
+ { .fc_id = 624, .cpu_id = 473, .valid = 0, .name = "" },
+ { .fc_id = 625, .cpu_id = 474, .valid = 0, .name = "" },
+ { .fc_id = 626, .cpu_id = 475, .valid = 0, .name = "" },
+ { .fc_id = 627, .cpu_id = 476, .valid = 0, .name = "" },
+ { .fc_id = 628, .cpu_id = 477, .valid = 0, .name = "" },
+ { .fc_id = 629, .cpu_id = 478, .valid = 0, .name = "" },
+ { .fc_id = 630, .cpu_id = 479, .valid = 0, .name = "" },
+ { .fc_id = 631, .cpu_id = 480, .valid = 0, .name = "" },
+ { .fc_id = 632, .cpu_id = 481, .valid = 0, .name = "" },
+ { .fc_id = 633, .cpu_id = 482, .valid = 0, .name = "" },
+ { .fc_id = 634, .cpu_id = 483, .valid = 0, .name = "" },
+ { .fc_id = 635, .cpu_id = 484, .valid = 1, .name = "PI_UPDATE" },
+ { .fc_id = 636, .cpu_id = 485, .valid = 1, .name = "HALT_MACHINE" },
+ { .fc_id = 637, .cpu_id = 486, .valid = 1, .name = "INTS_REGISTER" },
+ { .fc_id = 638, .cpu_id = 487, .valid = 1, .name = "SOFT_RESET" },
+ { .fc_id = 639, .cpu_id = 488, .valid = 0, .name = "" },
+ { .fc_id = 640, .cpu_id = 489, .valid = 0, .name = "" },
+ { .fc_id = 641, .cpu_id = 490, .valid = 0, .name = "" },
+ { .fc_id = 642, .cpu_id = 491, .valid = 0, .name = "" },
+ { .fc_id = 643, .cpu_id = 492, .valid = 0, .name = "" },
+ { .fc_id = 644, .cpu_id = 493, .valid = 0, .name = "" },
+ { .fc_id = 645, .cpu_id = 494, .valid = 1, .name = "FW_ALIVE_S" },
+ { .fc_id = 646, .cpu_id = 495, .valid = 1, .name = "DEV_RESET_REQ" },
+ { .fc_id = 647, .cpu_id = 496, .valid = 1,
+ .name = "PKT_QUEUE_OUT_SYNC" },
+ { .fc_id = 648, .cpu_id = 497, .valid = 1,
+ .name = "STATUS_NIC0_ENG0" },
+ { .fc_id = 649, .cpu_id = 498, .valid = 1,
+ .name = "STATUS_NIC0_ENG1" },
+ { .fc_id = 650, .cpu_id = 499, .valid = 1,
+ .name = "STATUS_NIC1_ENG0" },
+ { .fc_id = 651, .cpu_id = 500, .valid = 1,
+ .name = "STATUS_NIC1_ENG1" },
+ { .fc_id = 652, .cpu_id = 501, .valid = 1,
+ .name = "STATUS_NIC2_ENG0" },
+ { .fc_id = 653, .cpu_id = 502, .valid = 1,
+ .name = "STATUS_NIC2_ENG1" },
+ { .fc_id = 654, .cpu_id = 503, .valid = 1,
+ .name = "STATUS_NIC3_ENG0" },
+ { .fc_id = 655, .cpu_id = 504, .valid = 1,
+ .name = "STATUS_NIC3_ENG1" },
+ { .fc_id = 656, .cpu_id = 505, .valid = 1,
+ .name = "STATUS_NIC4_ENG0" },
+ { .fc_id = 657, .cpu_id = 506, .valid = 1,
+ .name = "STATUS_NIC4_ENG1" },
+ { .fc_id = 658, .cpu_id = 507, .valid = 1, .name = "FIX_POWER_ENV_S" },
+ { .fc_id = 659, .cpu_id = 508, .valid = 1, .name = "FIX_POWER_ENV_E" },
+ { .fc_id = 660, .cpu_id = 509, .valid = 1,
+ .name = "FIX_THERMAL_ENV_S" },
+ { .fc_id = 661, .cpu_id = 510, .valid = 1,
+ .name = "FIX_THERMAL_ENV_E" },
+ { .fc_id = 662, .cpu_id = 511, .valid = 1, .name = "RAZWI_OR_ADC_SW" },
+};
+
+#endif /* __GAUDI_ASYNC_IDS_MAP_EVENTS_EXT_H_ */
diff --git a/drivers/accel/habanalabs/include/gaudi/gaudi_coresight.h b/drivers/accel/habanalabs/include/gaudi/gaudi_coresight.h
new file mode 100644
index 0000000000..c45cc7f4d4
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi/gaudi_coresight.h
@@ -0,0 +1,367 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2016-2020 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+#ifndef GAUDI_CORESIGHT_H
+#define GAUDI_CORESIGHT_H
+
+enum gaudi_debug_stm_regs_index {
+ GAUDI_STM_FIRST = 0,
+ GAUDI_STM_MME0_ACC = GAUDI_STM_FIRST,
+ GAUDI_STM_MME0_SBAB,
+ GAUDI_STM_MME0_CTRL,
+ GAUDI_STM_MME1_ACC,
+ GAUDI_STM_MME1_SBAB,
+ GAUDI_STM_MME1_CTRL,
+ GAUDI_STM_MME2_ACC,
+ GAUDI_STM_MME2_SBAB,
+ GAUDI_STM_MME2_CTRL,
+ GAUDI_STM_MME3_ACC,
+ GAUDI_STM_MME3_SBAB,
+ GAUDI_STM_MME3_CTRL,
+ GAUDI_STM_DMA_IF_W_S,
+ GAUDI_STM_DMA_IF_E_S,
+ GAUDI_STM_DMA_IF_W_N,
+ GAUDI_STM_DMA_IF_E_N,
+ GAUDI_STM_CPU,
+ GAUDI_STM_DMA_CH_0_CS,
+ GAUDI_STM_DMA_CH_1_CS,
+ GAUDI_STM_DMA_CH_2_CS,
+ GAUDI_STM_DMA_CH_3_CS,
+ GAUDI_STM_DMA_CH_4_CS,
+ GAUDI_STM_DMA_CH_5_CS,
+ GAUDI_STM_DMA_CH_6_CS,
+ GAUDI_STM_DMA_CH_7_CS,
+ GAUDI_STM_PCIE,
+ GAUDI_STM_MMU_CS,
+ GAUDI_STM_PSOC,
+ GAUDI_STM_NIC0_0,
+ GAUDI_STM_NIC0_1,
+ GAUDI_STM_NIC1_0,
+ GAUDI_STM_NIC1_1,
+ GAUDI_STM_NIC2_0,
+ GAUDI_STM_NIC2_1,
+ GAUDI_STM_NIC3_0,
+ GAUDI_STM_NIC3_1,
+ GAUDI_STM_NIC4_0,
+ GAUDI_STM_NIC4_1,
+ GAUDI_STM_TPC0_EML,
+ GAUDI_STM_TPC1_EML,
+ GAUDI_STM_TPC2_EML,
+ GAUDI_STM_TPC3_EML,
+ GAUDI_STM_TPC4_EML,
+ GAUDI_STM_TPC5_EML,
+ GAUDI_STM_TPC6_EML,
+ GAUDI_STM_TPC7_EML,
+ GAUDI_STM_LAST = GAUDI_STM_TPC7_EML
+};
+
+enum gaudi_debug_etf_regs_index {
+ GAUDI_ETF_FIRST = 0,
+ GAUDI_ETF_MME0_ACC = GAUDI_ETF_FIRST,
+ GAUDI_ETF_MME0_SBAB,
+ GAUDI_ETF_MME0_CTRL,
+ GAUDI_ETF_MME1_ACC,
+ GAUDI_ETF_MME1_SBAB,
+ GAUDI_ETF_MME1_CTRL,
+ GAUDI_ETF_MME2_ACC,
+ GAUDI_ETF_MME2_SBAB,
+ GAUDI_ETF_MME2_CTRL,
+ GAUDI_ETF_MME3_ACC,
+ GAUDI_ETF_MME3_SBAB,
+ GAUDI_ETF_MME3_CTRL,
+ GAUDI_ETF_DMA_IF_W_S,
+ GAUDI_ETF_DMA_IF_E_S,
+ GAUDI_ETF_DMA_IF_W_N,
+ GAUDI_ETF_DMA_IF_E_N,
+ GAUDI_ETF_CPU_0,
+ GAUDI_ETF_CPU_1,
+ GAUDI_ETF_CPU_TRACE,
+ GAUDI_ETF_DMA_CH_0_CS,
+ GAUDI_ETF_DMA_CH_1_CS,
+ GAUDI_ETF_DMA_CH_2_CS,
+ GAUDI_ETF_DMA_CH_3_CS,
+ GAUDI_ETF_DMA_CH_4_CS,
+ GAUDI_ETF_DMA_CH_5_CS,
+ GAUDI_ETF_DMA_CH_6_CS,
+ GAUDI_ETF_DMA_CH_7_CS,
+ GAUDI_ETF_PCIE,
+ GAUDI_ETF_MMU_CS,
+ GAUDI_ETF_PSOC,
+ GAUDI_ETF_NIC0_0,
+ GAUDI_ETF_NIC0_1,
+ GAUDI_ETF_NIC1_0,
+ GAUDI_ETF_NIC1_1,
+ GAUDI_ETF_NIC2_0,
+ GAUDI_ETF_NIC2_1,
+ GAUDI_ETF_NIC3_0,
+ GAUDI_ETF_NIC3_1,
+ GAUDI_ETF_NIC4_0,
+ GAUDI_ETF_NIC4_1,
+ GAUDI_ETF_TPC0_EML,
+ GAUDI_ETF_TPC1_EML,
+ GAUDI_ETF_TPC2_EML,
+ GAUDI_ETF_TPC3_EML,
+ GAUDI_ETF_TPC4_EML,
+ GAUDI_ETF_TPC5_EML,
+ GAUDI_ETF_TPC6_EML,
+ GAUDI_ETF_TPC7_EML,
+ GAUDI_ETF_LAST = GAUDI_ETF_TPC7_EML
+};
+
+enum gaudi_debug_funnel_regs_index {
+ GAUDI_FUNNEL_FIRST = 0,
+ GAUDI_FUNNEL_MME0_ACC = GAUDI_FUNNEL_FIRST,
+ GAUDI_FUNNEL_MME1_ACC,
+ GAUDI_FUNNEL_MME2_ACC,
+ GAUDI_FUNNEL_MME3_ACC,
+ GAUDI_FUNNEL_SRAM_Y0_X0,
+ GAUDI_FUNNEL_SRAM_Y0_X1,
+ GAUDI_FUNNEL_SRAM_Y0_X2,
+ GAUDI_FUNNEL_SRAM_Y0_X3,
+ GAUDI_FUNNEL_SRAM_Y0_X4,
+ GAUDI_FUNNEL_SRAM_Y0_X5,
+ GAUDI_FUNNEL_SRAM_Y0_X6,
+ GAUDI_FUNNEL_SRAM_Y0_X7,
+ GAUDI_FUNNEL_SRAM_Y1_X0,
+ GAUDI_FUNNEL_SRAM_Y1_X1,
+ GAUDI_FUNNEL_SRAM_Y1_X2,
+ GAUDI_FUNNEL_SRAM_Y1_X3,
+ GAUDI_FUNNEL_SRAM_Y1_X4,
+ GAUDI_FUNNEL_SRAM_Y1_X5,
+ GAUDI_FUNNEL_SRAM_Y1_X6,
+ GAUDI_FUNNEL_SRAM_Y1_X7,
+ GAUDI_FUNNEL_SRAM_Y2_X0,
+ GAUDI_FUNNEL_SRAM_Y2_X1,
+ GAUDI_FUNNEL_SRAM_Y2_X2,
+ GAUDI_FUNNEL_SRAM_Y2_X3,
+ GAUDI_FUNNEL_SRAM_Y2_X4,
+ GAUDI_FUNNEL_SRAM_Y2_X5,
+ GAUDI_FUNNEL_SRAM_Y2_X6,
+ GAUDI_FUNNEL_SRAM_Y2_X7,
+ GAUDI_FUNNEL_SRAM_Y3_X0,
+ GAUDI_FUNNEL_SRAM_Y3_X1,
+ GAUDI_FUNNEL_SRAM_Y3_X2,
+ GAUDI_FUNNEL_SRAM_Y3_X4,
+ GAUDI_FUNNEL_SRAM_Y3_X3,
+ GAUDI_FUNNEL_SRAM_Y3_X5,
+ GAUDI_FUNNEL_SRAM_Y3_X6,
+ GAUDI_FUNNEL_SRAM_Y3_X7,
+ GAUDI_FUNNEL_SIF_0,
+ GAUDI_FUNNEL_SIF_1,
+ GAUDI_FUNNEL_SIF_2,
+ GAUDI_FUNNEL_SIF_3,
+ GAUDI_FUNNEL_SIF_4,
+ GAUDI_FUNNEL_SIF_5,
+ GAUDI_FUNNEL_SIF_6,
+ GAUDI_FUNNEL_SIF_7,
+ GAUDI_FUNNEL_NIF_0,
+ GAUDI_FUNNEL_NIF_1,
+ GAUDI_FUNNEL_NIF_2,
+ GAUDI_FUNNEL_NIF_3,
+ GAUDI_FUNNEL_NIF_4,
+ GAUDI_FUNNEL_NIF_5,
+ GAUDI_FUNNEL_NIF_6,
+ GAUDI_FUNNEL_NIF_7,
+ GAUDI_FUNNEL_DMA_IF_W_S,
+ GAUDI_FUNNEL_DMA_IF_E_S,
+ GAUDI_FUNNEL_DMA_IF_W_N,
+ GAUDI_FUNNEL_DMA_IF_E_N,
+ GAUDI_FUNNEL_CPU,
+ GAUDI_FUNNEL_NIC_TPC_W_S,
+ GAUDI_FUNNEL_NIC_TPC_E_S,
+ GAUDI_FUNNEL_NIC_TPC_W_N,
+ GAUDI_FUNNEL_NIC_TPC_E_N,
+ GAUDI_FUNNEL_PCIE,
+ GAUDI_FUNNEL_PSOC,
+ GAUDI_FUNNEL_NIC0,
+ GAUDI_FUNNEL_NIC1,
+ GAUDI_FUNNEL_NIC2,
+ GAUDI_FUNNEL_NIC3,
+ GAUDI_FUNNEL_NIC4,
+ GAUDI_FUNNEL_TPC0_EML,
+ GAUDI_FUNNEL_TPC1_EML,
+ GAUDI_FUNNEL_TPC2_EML,
+ GAUDI_FUNNEL_TPC3_EML,
+ GAUDI_FUNNEL_TPC4_EML,
+ GAUDI_FUNNEL_TPC5_EML,
+ GAUDI_FUNNEL_TPC6_EML,
+ GAUDI_FUNNEL_TPC7_EML,
+ GAUDI_FUNNEL_LAST = GAUDI_FUNNEL_TPC7_EML
+};
+
+enum gaudi_debug_bmon_regs_index {
+ GAUDI_BMON_FIRST = 0,
+ GAUDI_BMON_MME0_ACC_0 = GAUDI_BMON_FIRST,
+ GAUDI_BMON_MME0_SBAB_0,
+ GAUDI_BMON_MME0_SBAB_1,
+ GAUDI_BMON_MME0_CTRL_0,
+ GAUDI_BMON_MME0_CTRL_1,
+ GAUDI_BMON_MME1_ACC_0,
+ GAUDI_BMON_MME1_SBAB_0,
+ GAUDI_BMON_MME1_SBAB_1,
+ GAUDI_BMON_MME1_CTRL_0,
+ GAUDI_BMON_MME1_CTRL_1,
+ GAUDI_BMON_MME2_ACC_0,
+ GAUDI_BMON_MME2_SBAB_0,
+ GAUDI_BMON_MME2_SBAB_1,
+ GAUDI_BMON_MME2_CTRL_0,
+ GAUDI_BMON_MME2_CTRL_1,
+ GAUDI_BMON_MME3_ACC_0,
+ GAUDI_BMON_MME3_SBAB_0,
+ GAUDI_BMON_MME3_SBAB_1,
+ GAUDI_BMON_MME3_CTRL_0,
+ GAUDI_BMON_MME3_CTRL_1,
+ GAUDI_BMON_DMA_IF_W_S_SOB_WR,
+ GAUDI_BMON_DMA_IF_W_S_0_WR,
+ GAUDI_BMON_DMA_IF_W_S_0_RD,
+ GAUDI_BMON_DMA_IF_W_S_1_WR,
+ GAUDI_BMON_DMA_IF_W_S_1_RD,
+ GAUDI_BMON_DMA_IF_E_S_SOB_WR,
+ GAUDI_BMON_DMA_IF_E_S_0_WR,
+ GAUDI_BMON_DMA_IF_E_S_0_RD,
+ GAUDI_BMON_DMA_IF_E_S_1_WR,
+ GAUDI_BMON_DMA_IF_E_S_1_RD,
+ GAUDI_BMON_DMA_IF_W_N_SOB_WR,
+ GAUDI_BMON_DMA_IF_W_N_HBM0_WR,
+ GAUDI_BMON_DMA_IF_W_N_HBM0_RD,
+ GAUDI_BMON_DMA_IF_W_N_HBM1_WR,
+ GAUDI_BMON_DMA_IF_W_N_HBM1_RD,
+ GAUDI_BMON_DMA_IF_E_N_SOB_WR,
+ GAUDI_BMON_DMA_IF_E_N_HBM0_WR,
+ GAUDI_BMON_DMA_IF_E_N_HBM0_RD,
+ GAUDI_BMON_DMA_IF_E_N_HBM1_WR,
+ GAUDI_BMON_DMA_IF_E_N_HBM1_RD,
+ GAUDI_BMON_CPU_WR,
+ GAUDI_BMON_CPU_RD,
+ GAUDI_BMON_DMA_CH_0_0,
+ GAUDI_BMON_DMA_CH_0_1,
+ GAUDI_BMON_DMA_CH_1_0,
+ GAUDI_BMON_DMA_CH_1_1,
+ GAUDI_BMON_DMA_CH_2_0,
+ GAUDI_BMON_DMA_CH_2_1,
+ GAUDI_BMON_DMA_CH_3_0,
+ GAUDI_BMON_DMA_CH_3_1,
+ GAUDI_BMON_DMA_CH_4_0,
+ GAUDI_BMON_DMA_CH_4_1,
+ GAUDI_BMON_DMA_CH_5_0,
+ GAUDI_BMON_DMA_CH_5_1,
+ GAUDI_BMON_DMA_CH_6_0,
+ GAUDI_BMON_DMA_CH_6_1,
+ GAUDI_BMON_DMA_CH_7_0,
+ GAUDI_BMON_DMA_CH_7_1,
+ GAUDI_BMON_PCIE_MSTR_WR,
+ GAUDI_BMON_PCIE_MSTR_RD,
+ GAUDI_BMON_PCIE_SLV_WR,
+ GAUDI_BMON_PCIE_SLV_RD,
+ GAUDI_BMON_MMU_0,
+ GAUDI_BMON_MMU_1,
+ GAUDI_BMON_NIC0_0,
+ GAUDI_BMON_NIC0_1,
+ GAUDI_BMON_NIC0_2,
+ GAUDI_BMON_NIC0_3,
+ GAUDI_BMON_NIC0_4,
+ GAUDI_BMON_NIC1_0,
+ GAUDI_BMON_NIC1_1,
+ GAUDI_BMON_NIC1_2,
+ GAUDI_BMON_NIC1_3,
+ GAUDI_BMON_NIC1_4,
+ GAUDI_BMON_NIC2_0,
+ GAUDI_BMON_NIC2_1,
+ GAUDI_BMON_NIC2_2,
+ GAUDI_BMON_NIC2_3,
+ GAUDI_BMON_NIC2_4,
+ GAUDI_BMON_NIC3_0,
+ GAUDI_BMON_NIC3_1,
+ GAUDI_BMON_NIC3_2,
+ GAUDI_BMON_NIC3_3,
+ GAUDI_BMON_NIC3_4,
+ GAUDI_BMON_NIC4_0,
+ GAUDI_BMON_NIC4_1,
+ GAUDI_BMON_NIC4_2,
+ GAUDI_BMON_NIC4_3,
+ GAUDI_BMON_NIC4_4,
+ GAUDI_BMON_TPC0_EML_0,
+ GAUDI_BMON_TPC0_EML_1,
+ GAUDI_BMON_TPC0_EML_2,
+ GAUDI_BMON_TPC0_EML_3,
+ GAUDI_BMON_TPC1_EML_0,
+ GAUDI_BMON_TPC1_EML_1,
+ GAUDI_BMON_TPC1_EML_2,
+ GAUDI_BMON_TPC1_EML_3,
+ GAUDI_BMON_TPC2_EML_0,
+ GAUDI_BMON_TPC2_EML_1,
+ GAUDI_BMON_TPC2_EML_2,
+ GAUDI_BMON_TPC2_EML_3,
+ GAUDI_BMON_TPC3_EML_0,
+ GAUDI_BMON_TPC3_EML_1,
+ GAUDI_BMON_TPC3_EML_2,
+ GAUDI_BMON_TPC3_EML_3,
+ GAUDI_BMON_TPC4_EML_0,
+ GAUDI_BMON_TPC4_EML_1,
+ GAUDI_BMON_TPC4_EML_2,
+ GAUDI_BMON_TPC4_EML_3,
+ GAUDI_BMON_TPC5_EML_0,
+ GAUDI_BMON_TPC5_EML_1,
+ GAUDI_BMON_TPC5_EML_2,
+ GAUDI_BMON_TPC5_EML_3,
+ GAUDI_BMON_TPC6_EML_0,
+ GAUDI_BMON_TPC6_EML_1,
+ GAUDI_BMON_TPC6_EML_2,
+ GAUDI_BMON_TPC6_EML_3,
+ GAUDI_BMON_TPC7_EML_0,
+ GAUDI_BMON_TPC7_EML_1,
+ GAUDI_BMON_TPC7_EML_2,
+ GAUDI_BMON_TPC7_EML_3,
+ GAUDI_BMON_LAST = GAUDI_BMON_TPC7_EML_3
+};
+
+enum gaudi_debug_spmu_regs_index {
+ GAUDI_SPMU_FIRST = 0,
+ GAUDI_SPMU_MME0_ACC = GAUDI_SPMU_FIRST,
+ GAUDI_SPMU_MME0_SBAB,
+ GAUDI_SPMU_MME0_CTRL,
+ GAUDI_SPMU_MME1_ACC,
+ GAUDI_SPMU_MME1_SBAB,
+ GAUDI_SPMU_MME1_CTRL,
+ GAUDI_SPMU_MME2_MME2_ACC,
+ GAUDI_SPMU_MME2_SBAB,
+ GAUDI_SPMU_MME2_CTRL,
+ GAUDI_SPMU_MME3_ACC,
+ GAUDI_SPMU_MME3_SBAB,
+ GAUDI_SPMU_MME3_CTRL,
+ GAUDI_SPMU_DMA_CH_0_CS,
+ GAUDI_SPMU_DMA_CH_1_CS,
+ GAUDI_SPMU_DMA_CH_2_CS,
+ GAUDI_SPMU_DMA_CH_3_CS,
+ GAUDI_SPMU_DMA_CH_4_CS,
+ GAUDI_SPMU_DMA_CH_5_CS,
+ GAUDI_SPMU_DMA_CH_6_CS,
+ GAUDI_SPMU_DMA_CH_7_CS,
+ GAUDI_SPMU_PCIE,
+ GAUDI_SPMU_MMU_CS,
+ GAUDI_SPMU_NIC0_0,
+ GAUDI_SPMU_NIC0_1,
+ GAUDI_SPMU_NIC1_0,
+ GAUDI_SPMU_NIC1_1,
+ GAUDI_SPMU_NIC2_0,
+ GAUDI_SPMU_NIC2_1,
+ GAUDI_SPMU_NIC3_0,
+ GAUDI_SPMU_NIC3_1,
+ GAUDI_SPMU_NIC4_0,
+ GAUDI_SPMU_NIC4_1,
+ GAUDI_SPMU_TPC0_EML,
+ GAUDI_SPMU_TPC1_EML,
+ GAUDI_SPMU_TPC2_EML,
+ GAUDI_SPMU_TPC3_EML,
+ GAUDI_SPMU_TPC4_EML,
+ GAUDI_SPMU_TPC5_EML,
+ GAUDI_SPMU_TPC6_EML,
+ GAUDI_SPMU_TPC7_EML,
+ GAUDI_SPMU_LAST = GAUDI_SPMU_TPC7_EML
+};
+
+#endif /* GAUDI_CORESIGHT_H */
diff --git a/drivers/accel/habanalabs/include/gaudi/gaudi_fw_if.h b/drivers/accel/habanalabs/include/gaudi/gaudi_fw_if.h
new file mode 100644
index 0000000000..2dba02757d
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi/gaudi_fw_if.h
@@ -0,0 +1,91 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2019-2020 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+#ifndef GAUDI_FW_IF_H
+#define GAUDI_FW_IF_H
+
+#define GAUDI_EVENT_QUEUE_MSI_IDX 8
+#define GAUDI_NIC_PORT1_MSI_IDX 10
+#define GAUDI_NIC_PORT3_MSI_IDX 12
+#define GAUDI_NIC_PORT5_MSI_IDX 14
+#define GAUDI_NIC_PORT7_MSI_IDX 16
+#define GAUDI_NIC_PORT9_MSI_IDX 18
+
+#define UBOOT_FW_OFFSET 0x100000 /* 1MB in SRAM */
+#define LINUX_FW_OFFSET 0x800000 /* 8MB in HBM */
+
+/* HBM thermal delta in [Deg] added to composite (CTemp) */
+#define HBM_TEMP_ADJUST_COEFF 6
+
+enum gaudi_nic_axi_error {
+ RXB,
+ RXE,
+ TXS,
+ TXE,
+ QPC_RESP,
+ NON_AXI_ERR,
+ TMR,
+};
+
+/*
+ * struct eq_nic_sei_event - describes an AXI error cause.
+ * @axi_error_cause: one of the events defined in enum gaudi_nic_axi_error.
+ * @id: can be either 0 or 1, to further describe unit with interrupt cause
+ * (i.e. TXE0 or TXE1).
+ * @pad[6]: padding structure to 64bit.
+ */
+struct eq_nic_sei_event {
+ __u8 axi_error_cause;
+ __u8 id;
+ __u8 pad[6];
+};
+
+/*
+ * struct gaudi_nic_status - describes the status of a NIC port.
+ * @port: NIC port index.
+ * @bad_format_cnt: e.g. CRC.
+ * @responder_out_of_sequence_psn_cnt: e.g NAK.
+ * @high_ber_reinit_cnt: link reinit due to high BER.
+ * @correctable_err_cnt: e.g. bit-flip.
+ * @uncorrectable_err_cnt: e.g. MAC errors.
+ * @retraining_cnt: re-training counter.
+ * @up: is port up.
+ * @pcs_link: has PCS link.
+ * @phy_ready: is PHY ready.
+ * @auto_neg: is Autoneg enabled.
+ * @timeout_retransmission_cnt: timeout retransmission events
+ * @high_ber_cnt: high ber events
+ */
+struct gaudi_nic_status {
+ __u32 port;
+ __u32 bad_format_cnt;
+ __u32 responder_out_of_sequence_psn_cnt;
+ __u32 high_ber_reinit;
+ __u32 correctable_err_cnt;
+ __u32 uncorrectable_err_cnt;
+ __u32 retraining_cnt;
+ __u8 up;
+ __u8 pcs_link;
+ __u8 phy_ready;
+ __u8 auto_neg;
+ __u32 timeout_retransmission_cnt;
+ __u32 high_ber_cnt;
+};
+
+struct gaudi_cold_rst_data {
+ union {
+ struct {
+ u32 spsram_init_done : 1;
+ u32 reserved : 31;
+ };
+ __le32 data;
+ };
+};
+
+#define GAUDI_PLL_FREQ_LOW 200000000 /* 200 MHz */
+
+#endif /* GAUDI_FW_IF_H */
diff --git a/drivers/accel/habanalabs/include/gaudi/gaudi_masks.h b/drivers/accel/habanalabs/include/gaudi/gaudi_masks.h
new file mode 100644
index 0000000000..880c57b26c
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi/gaudi_masks.h
@@ -0,0 +1,470 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2016-2020 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+#ifndef GAUDI_MASKS_H_
+#define GAUDI_MASKS_H_
+
+#include "asic_reg/gaudi_regs.h"
+
+/* Useful masks for bits in various registers */
+#define PCI_DMA_QMAN_ENABLE (\
+ (FIELD_PREP(DMA0_QM_GLBL_CFG0_PQF_EN_MASK, 0xF)) | \
+ (FIELD_PREP(DMA0_QM_GLBL_CFG0_CQF_EN_MASK, 0xF)) | \
+ (FIELD_PREP(DMA0_QM_GLBL_CFG0_CP_EN_MASK, 0xF)))
+
+#define QMAN_EXTERNAL_MAKE_TRUSTED (\
+ (FIELD_PREP(DMA0_QM_GLBL_PROT_PQF_MASK, 0xF)) | \
+ (FIELD_PREP(DMA0_QM_GLBL_PROT_CQF_MASK, 0xF)) | \
+ (FIELD_PREP(DMA0_QM_GLBL_PROT_CP_MASK, 0xF)) | \
+ (FIELD_PREP(DMA0_QM_GLBL_PROT_ERR_MASK, 0x1)))
+
+#define QMAN_INTERNAL_MAKE_TRUSTED (\
+ (FIELD_PREP(DMA0_QM_GLBL_PROT_PQF_MASK, 0xF)) | \
+ (FIELD_PREP(DMA0_QM_GLBL_PROT_ERR_MASK, 0x1)))
+
+#define HBM_DMA_QMAN_ENABLE (\
+ (FIELD_PREP(DMA0_QM_GLBL_CFG0_PQF_EN_MASK, 0xF)) | \
+ (FIELD_PREP(DMA0_QM_GLBL_CFG0_CQF_EN_MASK, 0x1F)) | \
+ (FIELD_PREP(DMA0_QM_GLBL_CFG0_CP_EN_MASK, 0x1F)))
+
+#define QMAN_MME_ENABLE (\
+ (FIELD_PREP(MME0_QM_GLBL_CFG0_PQF_EN_MASK, 0xF)) | \
+ (FIELD_PREP(MME0_QM_GLBL_CFG0_CQF_EN_MASK, 0x1F)) | \
+ (FIELD_PREP(MME0_QM_GLBL_CFG0_CP_EN_MASK, 0x1F)))
+
+#define QMAN_TPC_ENABLE (\
+ (FIELD_PREP(TPC0_QM_GLBL_CFG0_PQF_EN_MASK, 0xF)) | \
+ (FIELD_PREP(TPC0_QM_GLBL_CFG0_CQF_EN_MASK, 0x1F)) | \
+ (FIELD_PREP(TPC0_QM_GLBL_CFG0_CP_EN_MASK, 0x1F)))
+
+#define NIC_QMAN_ENABLE (\
+ (FIELD_PREP(NIC0_QM0_GLBL_CFG0_PQF_EN_MASK, 0xF)) | \
+ (FIELD_PREP(NIC0_QM0_GLBL_CFG0_CQF_EN_MASK, 0xF)) | \
+ (FIELD_PREP(NIC0_QM0_GLBL_CFG0_CP_EN_MASK, 0xF)))
+
+#define QMAN_UPPER_CP_CGM_PWR_GATE_EN (\
+ (FIELD_PREP(DMA0_QM_CGM_CFG_IDLE_TH_MASK, 0x20)) | \
+ (FIELD_PREP(DMA0_QM_CGM_CFG_G2F_TH_MASK, 0xA)) | \
+ (FIELD_PREP(DMA0_QM_CGM_CFG_CP_IDLE_MASK_MASK, 0x10)) | \
+ (FIELD_PREP(DMA0_QM_CGM_CFG_EN_MASK, 0x1)))
+
+#define QMAN_COMMON_CP_CGM_PWR_GATE_EN (\
+ (FIELD_PREP(DMA0_QM_CGM_CFG_IDLE_TH_MASK, 0x20)) | \
+ (FIELD_PREP(DMA0_QM_CGM_CFG_G2F_TH_MASK, 0xA)) | \
+ (FIELD_PREP(DMA0_QM_CGM_CFG_CP_IDLE_MASK_MASK, 0xF)) | \
+ (FIELD_PREP(DMA0_QM_CGM_CFG_EN_MASK, 0x1)))
+
+#define PCI_DMA_QMAN_GLBL_ERR_CFG_MSG_EN_MASK (\
+ (FIELD_PREP(DMA0_QM_GLBL_ERR_CFG_PQF_ERR_MSG_EN_MASK, 0xF)) | \
+ (FIELD_PREP(DMA0_QM_GLBL_ERR_CFG_CQF_ERR_MSG_EN_MASK, 0xF)) | \
+ (FIELD_PREP(DMA0_QM_GLBL_ERR_CFG_CP_ERR_MSG_EN_MASK, 0xF)))
+
+#define PCI_DMA_QMAN_GLBL_ERR_CFG_STOP_ON_ERR_EN_MASK (\
+ (FIELD_PREP(DMA0_QM_GLBL_ERR_CFG_PQF_STOP_ON_ERR_MASK, 0xF)) | \
+ (FIELD_PREP(DMA0_QM_GLBL_ERR_CFG_CQF_STOP_ON_ERR_MASK, 0xF)) | \
+ (FIELD_PREP(DMA0_QM_GLBL_ERR_CFG_CP_STOP_ON_ERR_MASK, 0xF)) | \
+ (FIELD_PREP(DMA0_QM_GLBL_ERR_CFG_ARB_STOP_ON_ERR_MASK, 0x1)))
+
+#define HBM_DMA_QMAN_GLBL_ERR_CFG_MSG_EN_MASK (\
+ (FIELD_PREP(DMA0_QM_GLBL_ERR_CFG_PQF_ERR_MSG_EN_MASK, 0xF)) | \
+ (FIELD_PREP(DMA0_QM_GLBL_ERR_CFG_CQF_ERR_MSG_EN_MASK, 0x1F)) | \
+ (FIELD_PREP(DMA0_QM_GLBL_ERR_CFG_CP_ERR_MSG_EN_MASK, 0x1F)))
+
+#define HBM_DMA_QMAN_GLBL_ERR_CFG_STOP_ON_ERR_EN_MASK (\
+ (FIELD_PREP(DMA0_QM_GLBL_ERR_CFG_PQF_STOP_ON_ERR_MASK, 0xF)) | \
+ (FIELD_PREP(DMA0_QM_GLBL_ERR_CFG_CQF_STOP_ON_ERR_MASK, 0x1F)) | \
+ (FIELD_PREP(DMA0_QM_GLBL_ERR_CFG_CP_STOP_ON_ERR_MASK, 0x1F)) | \
+ (FIELD_PREP(DMA0_QM_GLBL_ERR_CFG_ARB_STOP_ON_ERR_MASK, 0x1)))
+
+#define TPC_QMAN_GLBL_ERR_CFG_MSG_EN_MASK (\
+ (FIELD_PREP(TPC0_QM_GLBL_ERR_CFG_PQF_ERR_MSG_EN_MASK, 0xF)) | \
+ (FIELD_PREP(TPC0_QM_GLBL_ERR_CFG_CQF_ERR_MSG_EN_MASK, 0x1F)) | \
+ (FIELD_PREP(TPC0_QM_GLBL_ERR_CFG_CP_ERR_MSG_EN_MASK, 0x1F)))
+
+#define TPC_QMAN_GLBL_ERR_CFG_STOP_ON_ERR_EN_MASK (\
+ (FIELD_PREP(TPC0_QM_GLBL_ERR_CFG_PQF_STOP_ON_ERR_MASK, 0xF)) | \
+ (FIELD_PREP(TPC0_QM_GLBL_ERR_CFG_CQF_STOP_ON_ERR_MASK, 0x1F)) | \
+ (FIELD_PREP(TPC0_QM_GLBL_ERR_CFG_CP_STOP_ON_ERR_MASK, 0x1F)) | \
+ (FIELD_PREP(TPC0_QM_GLBL_ERR_CFG_ARB_STOP_ON_ERR_MASK, 0x1)))
+
+#define MME_QMAN_GLBL_ERR_CFG_MSG_EN_MASK (\
+ (FIELD_PREP(MME0_QM_GLBL_ERR_CFG_PQF_ERR_MSG_EN_MASK, 0xF)) | \
+ (FIELD_PREP(MME0_QM_GLBL_ERR_CFG_CQF_ERR_MSG_EN_MASK, 0x1F)) | \
+ (FIELD_PREP(MME0_QM_GLBL_ERR_CFG_CP_ERR_MSG_EN_MASK, 0x1F)))
+
+#define MME_QMAN_GLBL_ERR_CFG_STOP_ON_ERR_EN_MASK (\
+ (FIELD_PREP(MME0_QM_GLBL_ERR_CFG_PQF_STOP_ON_ERR_MASK, 0xF)) | \
+ (FIELD_PREP(MME0_QM_GLBL_ERR_CFG_CQF_STOP_ON_ERR_MASK, 0x1F)) | \
+ (FIELD_PREP(MME0_QM_GLBL_ERR_CFG_CP_STOP_ON_ERR_MASK, 0x1F)) | \
+ (FIELD_PREP(MME0_QM_GLBL_ERR_CFG_ARB_STOP_ON_ERR_MASK, 0x1)))
+
+#define NIC_QMAN_GLBL_ERR_CFG_MSG_EN_MASK (\
+ (FIELD_PREP(NIC0_QM0_GLBL_ERR_CFG_PQF_ERR_MSG_EN_MASK, 0xF)) | \
+ (FIELD_PREP(NIC0_QM0_GLBL_ERR_CFG_CQF_ERR_MSG_EN_MASK, 0xF)) | \
+ (FIELD_PREP(NIC0_QM0_GLBL_ERR_CFG_CP_ERR_MSG_EN_MASK, 0xF)))
+
+#define NIC_QMAN_GLBL_ERR_CFG_STOP_ON_ERR_EN_MASK (\
+ (FIELD_PREP(NIC0_QM0_GLBL_ERR_CFG_PQF_STOP_ON_ERR_MASK, 0xF)) | \
+ (FIELD_PREP(NIC0_QM0_GLBL_ERR_CFG_CQF_STOP_ON_ERR_MASK, 0xF)) | \
+ (FIELD_PREP(NIC0_QM0_GLBL_ERR_CFG_CP_STOP_ON_ERR_MASK, 0xF)) | \
+ (FIELD_PREP(NIC0_QM0_GLBL_ERR_CFG_ARB_STOP_ON_ERR_MASK, 0x1)))
+
+#define QMAN_CGM1_PWR_GATE_EN (FIELD_PREP(DMA0_QM_CGM_CFG1_MASK_TH_MASK, 0xA))
+
+/* RESET registers configuration */
+#define CFG_RST_L_PSOC_MASK BIT_MASK(0)
+#define CFG_RST_L_PCIE_MASK BIT_MASK(1)
+#define CFG_RST_L_PCIE_IF_MASK BIT_MASK(2)
+#define CFG_RST_L_HBM_S_PLL_MASK BIT_MASK(3)
+#define CFG_RST_L_TPC_S_PLL_MASK BIT_MASK(4)
+#define CFG_RST_L_MME_S_PLL_MASK BIT_MASK(5)
+#define CFG_RST_L_CPU_PLL_MASK BIT_MASK(6)
+#define CFG_RST_L_PCIE_PLL_MASK BIT_MASK(7)
+#define CFG_RST_L_NIC_S_PLL_MASK BIT_MASK(8)
+#define CFG_RST_L_HBM_N_PLL_MASK BIT_MASK(9)
+#define CFG_RST_L_TPC_N_PLL_MASK BIT_MASK(10)
+#define CFG_RST_L_MME_N_PLL_MASK BIT_MASK(11)
+#define CFG_RST_L_NIC_N_PLL_MASK BIT_MASK(12)
+#define CFG_RST_L_DMA_W_PLL_MASK BIT_MASK(13)
+#define CFG_RST_L_SIF_W_PLL_MASK BIT_MASK(14)
+#define CFG_RST_L_MESH_W_PLL_MASK BIT_MASK(15)
+#define CFG_RST_L_SRAM_W_PLL_MASK BIT_MASK(16)
+#define CFG_RST_L_DMA_E_PLL_MASK BIT_MASK(17)
+#define CFG_RST_L_SIF_E_PLL_MASK BIT_MASK(18)
+#define CFG_RST_L_MESH_E_PLL_MASK BIT_MASK(19)
+#define CFG_RST_L_SRAM_E_PLL_MASK BIT_MASK(20)
+
+#define CFG_RST_L_IF_1_MASK BIT_MASK(21)
+#define CFG_RST_L_IF_0_MASK BIT_MASK(22)
+#define CFG_RST_L_IF_2_MASK BIT_MASK(23)
+#define CFG_RST_L_IF_3_MASK BIT_MASK(24)
+#define CFG_RST_L_IF_MASK GENMASK(24, 21)
+
+#define CFG_RST_L_TPC_0_MASK BIT_MASK(25)
+#define CFG_RST_L_TPC_1_MASK BIT_MASK(26)
+#define CFG_RST_L_TPC_2_MASK BIT_MASK(27)
+#define CFG_RST_L_TPC_3_MASK BIT_MASK(28)
+#define CFG_RST_L_TPC_4_MASK BIT_MASK(29)
+#define CFG_RST_L_TPC_5_MASK BIT_MASK(30)
+#define CFG_RST_L_TPC_6_MASK BIT_MASK(31)
+#define CFG_RST_L_TPC_MASK GENMASK(31, 25)
+
+#define CFG_RST_H_TPC_7_MASK BIT_MASK(0)
+
+#define CFG_RST_H_MME_0_MASK BIT_MASK(1)
+#define CFG_RST_H_MME_1_MASK BIT_MASK(2)
+#define CFG_RST_H_MME_2_MASK BIT_MASK(3)
+#define CFG_RST_H_MME_3_MASK BIT_MASK(4)
+#define CFG_RST_H_MME_MASK GENMASK(4, 1)
+
+#define CFG_RST_H_HBM_0_MASK BIT_MASK(5)
+#define CFG_RST_H_HBM_1_MASK BIT_MASK(6)
+#define CFG_RST_H_HBM_2_MASK BIT_MASK(7)
+#define CFG_RST_H_HBM_3_MASK BIT_MASK(8)
+#define CFG_RST_H_HBM_MASK GENMASK(8, 5)
+
+#define CFG_RST_H_NIC_0_MASK BIT_MASK(9)
+#define CFG_RST_H_NIC_1_MASK BIT_MASK(10)
+#define CFG_RST_H_NIC_2_MASK BIT_MASK(11)
+#define CFG_RST_H_NIC_3_MASK BIT_MASK(12)
+#define CFG_RST_H_NIC_4_MASK BIT_MASK(13)
+#define CFG_RST_H_NIC_MASK GENMASK(13, 9)
+
+#define CFG_RST_H_SM_0_MASK BIT_MASK(14)
+#define CFG_RST_H_SM_1_MASK BIT_MASK(15)
+#define CFG_RST_H_SM_2_MASK BIT_MASK(16)
+#define CFG_RST_H_SM_3_MASK BIT_MASK(17)
+#define CFG_RST_H_SM_MASK GENMASK(17, 14)
+
+#define CFG_RST_H_DMA_0_MASK BIT_MASK(18)
+#define CFG_RST_H_DMA_1_MASK BIT_MASK(19)
+#define CFG_RST_H_DMA_MASK GENMASK(19, 18)
+
+#define CFG_RST_H_CPU_MASK BIT_MASK(20)
+#define CFG_RST_H_MMU_MASK BIT_MASK(21)
+
+#define UNIT_RST_L_PSOC_SHIFT 0
+#define UNIT_RST_L_PCIE_SHIFT 1
+#define UNIT_RST_L_PCIE_IF_SHIFT 2
+#define UNIT_RST_L_HBM_S_PLL_SHIFT 3
+#define UNIT_RST_L_TPC_S_PLL_SHIFT 4
+#define UNIT_RST_L_MME_S_PLL_SHIFT 5
+#define UNIT_RST_L_CPU_PLL_SHIFT 6
+#define UNIT_RST_L_PCIE_PLL_SHIFT 7
+#define UNIT_RST_L_NIC_S_PLL_SHIFT 8
+#define UNIT_RST_L_HBM_N_PLL_SHIFT 9
+#define UNIT_RST_L_TPC_N_PLL_SHIFT 10
+#define UNIT_RST_L_MME_N_PLL_SHIFT 11
+#define UNIT_RST_L_NIC_N_PLL_SHIFT 12
+#define UNIT_RST_L_DMA_W_PLL_SHIFT 13
+#define UNIT_RST_L_SIF_W_PLL_SHIFT 14
+#define UNIT_RST_L_MESH_W_PLL_SHIFT 15
+#define UNIT_RST_L_SRAM_W_PLL_SHIFT 16
+#define UNIT_RST_L_DMA_E_PLL_SHIFT 17
+#define UNIT_RST_L_SIF_E_PLL_SHIFT 18
+#define UNIT_RST_L_MESH_E_PLL_SHIFT 19
+#define UNIT_RST_L_SRAM_E_PLL_SHIFT 20
+#define UNIT_RST_L_TPC_0_SHIFT 21
+#define UNIT_RST_L_TPC_1_SHIFT 22
+#define UNIT_RST_L_TPC_2_SHIFT 23
+#define UNIT_RST_L_TPC_3_SHIFT 24
+#define UNIT_RST_L_TPC_4_SHIFT 25
+#define UNIT_RST_L_TPC_5_SHIFT 26
+#define UNIT_RST_L_TPC_6_SHIFT 27
+#define UNIT_RST_L_TPC_7_SHIFT 28
+#define UNIT_RST_L_MME_0_SHIFT 29
+#define UNIT_RST_L_MME_1_SHIFT 30
+#define UNIT_RST_L_MME_2_SHIFT 31
+
+#define UNIT_RST_H_MME_3_SHIFT 0
+#define UNIT_RST_H_HBM_0_SHIFT 1
+#define UNIT_RST_H_HBM_1_SHIFT 2
+#define UNIT_RST_H_HBM_2_SHIFT 3
+#define UNIT_RST_H_HBM_3_SHIFT 4
+#define UNIT_RST_H_NIC_0_SHIFT 5
+#define UNIT_RST_H_NIC_1_SHIFT 6
+#define UNIT_RST_H_NIC_2_SHIFT 7
+#define UNIT_RST_H_NIC_3_SHIFT 8
+#define UNIT_RST_H_NIC_4_SHIFT 9
+#define UNIT_RST_H_SM_0_SHIFT 10
+#define UNIT_RST_H_SM_1_SHIFT 11
+#define UNIT_RST_H_SM_2_SHIFT 12
+#define UNIT_RST_H_SM_3_SHIFT 13
+#define UNIT_RST_H_IF_0_SHIFT 14
+#define UNIT_RST_H_IF_1_SHIFT 15
+#define UNIT_RST_H_IF_2_SHIFT 16
+#define UNIT_RST_H_IF_3_SHIFT 17
+#define UNIT_RST_H_DMA_0_SHIFT 18
+#define UNIT_RST_H_DMA_1_SHIFT 19
+#define UNIT_RST_H_CPU_SHIFT 20
+#define UNIT_RST_H_MMU_SHIFT 21
+
+#define UNIT_RST_H_HBM_MASK ((1 << UNIT_RST_H_HBM_0_SHIFT) | \
+ (1 << UNIT_RST_H_HBM_1_SHIFT) | \
+ (1 << UNIT_RST_H_HBM_2_SHIFT) | \
+ (1 << UNIT_RST_H_HBM_3_SHIFT))
+
+#define UNIT_RST_H_NIC_MASK ((1 << UNIT_RST_H_NIC_0_SHIFT) | \
+ (1 << UNIT_RST_H_NIC_1_SHIFT) | \
+ (1 << UNIT_RST_H_NIC_2_SHIFT) | \
+ (1 << UNIT_RST_H_NIC_3_SHIFT) | \
+ (1 << UNIT_RST_H_NIC_4_SHIFT))
+
+#define UNIT_RST_H_SM_MASK ((1 << UNIT_RST_H_SM_0_SHIFT) | \
+ (1 << UNIT_RST_H_SM_1_SHIFT) | \
+ (1 << UNIT_RST_H_SM_2_SHIFT) | \
+ (1 << UNIT_RST_H_SM_3_SHIFT))
+
+#define UNIT_RST_H_MME_MASK ((1 << UNIT_RST_H_MME_0_SHIFT) | \
+ (1 << UNIT_RST_H_MME_1_SHIFT) | \
+ (1 << UNIT_RST_H_MME_2_SHIFT))
+
+#define UNIT_RST_L_MME_MASK (1 << UNIT_RST_L_MME_3_SHIFT)
+
+#define UNIT_RST_L_IF_MASK ((1 << UNIT_RST_L_IF_0_SHIFT) | \
+ (1 << UNIT_RST_L_IF_1_SHIFT) | \
+ (1 << UNIT_RST_L_IF_2_SHIFT) | \
+ (1 << UNIT_RST_L_IF_3_SHIFT))
+
+#define UNIT_RST_L_TPC_MASK ((1 << UNIT_RST_L_TPC_0_SHIFT) | \
+ (1 << UNIT_RST_L_TPC_1_SHIFT) | \
+ (1 << UNIT_RST_L_TPC_2_SHIFT) | \
+ (1 << UNIT_RST_L_TPC_3_SHIFT) | \
+ (1 << UNIT_RST_L_TPC_4_SHIFT) | \
+ (1 << UNIT_RST_L_TPC_5_SHIFT) | \
+ (1 << UNIT_RST_L_TPC_6_SHIFT) | \
+ (1 << UNIT_RST_L_TPC_7_SHIFT))
+
+/* CPU_CA53_CFG_ARM_RST_CONTROL */
+#define CPU_CA53_CFG_ARM_RST_CONTROL_NCPUPORESET_SHIFT 0
+#define CPU_CA53_CFG_ARM_RST_CONTROL_NCPUPORESET_MASK 0x3
+#define CPU_CA53_CFG_ARM_RST_CONTROL_NCORERESET_SHIFT 4
+#define CPU_CA53_CFG_ARM_RST_CONTROL_NCORERESET_MASK 0x30
+#define CPU_CA53_CFG_ARM_RST_CONTROL_NL2RESET_SHIFT 8
+#define CPU_CA53_CFG_ARM_RST_CONTROL_NL2RESET_MASK 0x100
+#define CPU_CA53_CFG_ARM_RST_CONTROL_NPRESETDBG_SHIFT 12
+#define CPU_CA53_CFG_ARM_RST_CONTROL_NPRESETDBG_MASK 0x1000
+#define CPU_CA53_CFG_ARM_RST_CONTROL_NMBISTRESET_SHIFT 16
+#define CPU_CA53_CFG_ARM_RST_CONTROL_NMBISTRESET_MASK 0x10000
+#define CPU_CA53_CFG_ARM_RST_CONTROL_WARMRSTREQ_SHIFT 20
+#define CPU_CA53_CFG_ARM_RST_CONTROL_WARMRSTREQ_MASK 0x300000
+
+#define CPU_RESET_ASSERT (\
+ 1 << CPU_CA53_CFG_ARM_RST_CONTROL_NMBISTRESET_SHIFT)
+
+#define CPU_RESET_CORE0_DEASSERT (\
+ 1 << CPU_CA53_CFG_ARM_RST_CONTROL_NCPUPORESET_SHIFT |\
+ 1 << CPU_CA53_CFG_ARM_RST_CONTROL_NCORERESET_SHIFT |\
+ 1 << CPU_CA53_CFG_ARM_RST_CONTROL_NL2RESET_SHIFT |\
+ 1 << CPU_CA53_CFG_ARM_RST_CONTROL_NMBISTRESET_SHIFT)
+
+/* QM_IDLE_MASK is valid for all engines QM idle check */
+#define QM_IDLE_MASK (DMA0_QM_GLBL_STS0_PQF_IDLE_MASK | \
+ DMA0_QM_GLBL_STS0_CQF_IDLE_MASK | \
+ DMA0_QM_GLBL_STS0_CP_IDLE_MASK)
+
+/* CGM_IDLE_MASK is valid for all engines CGM idle check */
+#define CGM_IDLE_MASK DMA0_QM_CGM_STS_AGENT_IDLE_MASK
+
+#define TPC_IDLE_MASK ((1 << TPC0_CFG_STATUS_SCALAR_PIPE_EMPTY_SHIFT) | \
+ (1 << TPC0_CFG_STATUS_VECTOR_PIPE_EMPTY_SHIFT) | \
+ (1 << TPC0_CFG_STATUS_IQ_EMPTY_SHIFT) | \
+ (1 << TPC0_CFG_STATUS_SB_EMPTY_SHIFT) | \
+ (1 << TPC0_CFG_STATUS_QM_IDLE_SHIFT) | \
+ (1 << TPC0_CFG_STATUS_QM_RDY_SHIFT))
+
+#define MME0_CTRL_ARCH_STATUS_SB_A_EMPTY_MASK 0x80
+#define MME0_CTRL_ARCH_STATUS_SB_B_EMPTY_MASK 0x100
+#define MME0_CTRL_ARCH_STATUS_WBC_AXI_IDLE_MASK 0x1000
+
+#define MME_ARCH_IDLE_MASK (MME0_CTRL_ARCH_STATUS_SB_A_EMPTY_MASK | \
+ MME0_CTRL_ARCH_STATUS_SB_B_EMPTY_MASK | \
+ MME0_CTRL_ARCH_STATUS_WBC_AXI_IDLE_MASK)
+
+#define IS_QM_IDLE(qm_glbl_sts0, qm_cgm_sts) \
+ ((((qm_glbl_sts0) & QM_IDLE_MASK) == QM_IDLE_MASK) && \
+ (((qm_cgm_sts) & CGM_IDLE_MASK) == CGM_IDLE_MASK))
+
+#define IS_DMA_IDLE(dma_core_sts0) \
+ !(dma_core_sts0 & DMA0_CORE_STS0_BUSY_MASK)
+
+#define IS_TPC_IDLE(tpc_cfg_sts) \
+ (((tpc_cfg_sts) & TPC_IDLE_MASK) == TPC_IDLE_MASK)
+
+#define IS_MME_IDLE(mme_arch_sts) \
+ (((mme_arch_sts) & MME_ARCH_IDLE_MASK) == MME_ARCH_IDLE_MASK)
+
+enum axi_id {
+ AXI_ID_MME,
+ AXI_ID_TPC,
+ AXI_ID_DMA,
+ AXI_ID_NIC, /* Local NIC */
+ AXI_ID_PCI,
+ AXI_ID_CPU,
+ AXI_ID_PSOC,
+ AXI_ID_MMU,
+ AXI_ID_NIC_FT /* Feed-Through NIC */
+};
+
+/* RAZWI initiator ID is built from the location in the chip and the AXI ID */
+
+#define RAZWI_INITIATOR_AXI_ID_SHIFT 20
+#define RAZWI_INITIATOR_AXI_ID_MASK 0xF
+#define RAZWI_INITIATOR_X_SHIFT 24
+#define RAZWI_INITIATOR_X_MASK 0xF
+#define RAZWI_INITIATOR_Y_SHIFT 28
+#define RAZWI_INITIATOR_Y_MASK 0x7
+
+#define RAZWI_INITIATOR_ID_AXI_ID(axi_id) \
+ (((axi_id) & RAZWI_INITIATOR_AXI_ID_MASK) << \
+ RAZWI_INITIATOR_AXI_ID_SHIFT)
+
+#define RAZWI_INITIATOR_ID_X_Y(x, y) \
+ ((((y) & RAZWI_INITIATOR_Y_MASK) << RAZWI_INITIATOR_Y_SHIFT) | \
+ (((x) & RAZWI_INITIATOR_X_MASK) << RAZWI_INITIATOR_X_SHIFT))
+
+#define RAZWI_INITIATOR_ID_X_Y_TPC0_NIC0 RAZWI_INITIATOR_ID_X_Y(1, 1)
+#define RAZWI_INITIATOR_ID_X_Y_TPC1 RAZWI_INITIATOR_ID_X_Y(2, 1)
+#define RAZWI_INITIATOR_ID_X_Y_MME0_0 RAZWI_INITIATOR_ID_X_Y(3, 1)
+#define RAZWI_INITIATOR_ID_X_Y_MME0_1 RAZWI_INITIATOR_ID_X_Y(4, 1)
+#define RAZWI_INITIATOR_ID_X_Y_MME1_0 RAZWI_INITIATOR_ID_X_Y(5, 1)
+#define RAZWI_INITIATOR_ID_X_Y_MME1_1 RAZWI_INITIATOR_ID_X_Y(6, 1)
+#define RAZWI_INITIATOR_ID_X_Y_TPC2 RAZWI_INITIATOR_ID_X_Y(7, 1)
+#define RAZWI_INITIATOR_ID_X_Y_TPC3_PCI_CPU_PSOC \
+ RAZWI_INITIATOR_ID_X_Y(8, 1)
+#define RAZWI_INITIATOR_ID_X_Y_DMA_IF_W_S_0 RAZWI_INITIATOR_ID_X_Y(0, 1)
+#define RAZWI_INITIATOR_ID_X_Y_DMA_IF_E_S_0 RAZWI_INITIATOR_ID_X_Y(9, 1)
+#define RAZWI_INITIATOR_ID_X_Y_DMA_IF_W_S_1 RAZWI_INITIATOR_ID_X_Y(0, 2)
+#define RAZWI_INITIATOR_ID_X_Y_DMA_IF_E_S_1 RAZWI_INITIATOR_ID_X_Y(9, 2)
+#define RAZWI_INITIATOR_ID_X_Y_DMA_IF_W_N_0 RAZWI_INITIATOR_ID_X_Y(0, 3)
+#define RAZWI_INITIATOR_ID_X_Y_DMA_IF_E_N_0 RAZWI_INITIATOR_ID_X_Y(9, 3)
+#define RAZWI_INITIATOR_ID_X_Y_DMA_IF_W_N_1 RAZWI_INITIATOR_ID_X_Y(0, 4)
+#define RAZWI_INITIATOR_ID_X_Y_DMA_IF_E_N_1 RAZWI_INITIATOR_ID_X_Y(9, 4)
+#define RAZWI_INITIATOR_ID_X_Y_TPC4_NIC1_NIC2 RAZWI_INITIATOR_ID_X_Y(1, 6)
+#define RAZWI_INITIATOR_ID_X_Y_TPC5 RAZWI_INITIATOR_ID_X_Y(2, 6)
+#define RAZWI_INITIATOR_ID_X_Y_MME2_0 RAZWI_INITIATOR_ID_X_Y(3, 6)
+#define RAZWI_INITIATOR_ID_X_Y_MME2_1 RAZWI_INITIATOR_ID_X_Y(4, 6)
+#define RAZWI_INITIATOR_ID_X_Y_MME3_0 RAZWI_INITIATOR_ID_X_Y(5, 6)
+#define RAZWI_INITIATOR_ID_X_Y_MME3_1 RAZWI_INITIATOR_ID_X_Y(6, 6)
+#define RAZWI_INITIATOR_ID_X_Y_TPC6 RAZWI_INITIATOR_ID_X_Y(7, 6)
+#define RAZWI_INITIATOR_ID_X_Y_TPC7_NIC4_NIC5 RAZWI_INITIATOR_ID_X_Y(8, 6)
+
+#define PSOC_ETR_AXICTL_PROTCTRLBIT1_SHIFT 1
+#define PSOC_ETR_AXICTL_PROTCTRLBIT0_MASK 0x1
+#define PSOC_ETR_AXICTL_PROTCTRLBIT1_MASK 0x2
+#define PSOC_ETR_AXICTL_WRBURSTLEN_MASK 0xF00
+
+/* STLB_CACHE_INV */
+#define STLB_CACHE_INV_PRODUCER_INDEX_SHIFT 0
+#define STLB_CACHE_INV_PRODUCER_INDEX_MASK 0xFF
+#define STLB_CACHE_INV_INDEX_MASK_SHIFT 8
+#define STLB_CACHE_INV_INDEX_MASK_MASK 0xFF00
+
+#define MME_ACC_ACC_STALL_R_SHIFT 0
+#define MME_SBAB_SB_STALL_R_SHIFT 0
+
+#define PCIE_WRAP_LBW_PROT_OVR_RD_EN_MASK 0x700
+#define PCIE_WRAP_LBW_PROT_OVR_WR_EN_MASK 0x7000
+
+#define PCIE_WRAP_LBW_DRAIN_CFG_EN_SHIFT 0
+#define PCIE_WRAP_HBW_DRAIN_CFG_EN_SHIFT 0
+
+/* DMA_IF_HBM_CRED_EN */
+#define DMA_IF_HBM_CRED_EN_READ_CREDIT_EN_SHIFT 0
+#define DMA_IF_HBM_CRED_EN_READ_CREDIT_EN_MASK 0x1
+#define DMA_IF_HBM_CRED_EN_WRITE_CREDIT_EN_SHIFT 1
+#define DMA_IF_HBM_CRED_EN_WRITE_CREDIT_EN_MASK 0x2
+
+#define DMA_IF_DOWN_CHX_SCRAM_SRAM_EN_VAL_SHIFT 0
+#define DMA_IF_DOWN_CHX_SCRAM_HBM_EN_VAL_SHIFT 0
+#define DMA_IF_DOWN_CHX_E2E_HBM_EN_VAL_SHIFT 0
+#define DMA_IF_DOWN_CHX_E2E_PCI_EN_VAL_SHIFT 0
+
+#define IF_RTR_CTRL_SCRAM_SRAM_EN_VAL_SHIFT 0
+#define IF_RTR_CTRL_SCRAM_HBM_EN_VAL_SHIFT 0
+
+#define IF_RTR_CTRL_E2E_HBM_EN_VAL_SHIFT 0
+#define IF_RTR_CTRL_E2E_PCI_EN_VAL_SHIFT 0
+
+/* MMU_UP_PAGE_ERROR_CAPTURE */
+#define MMU_UP_PAGE_ERROR_CAPTURE_VA_49_32_MASK 0x3FFFF
+#define MMU_UP_PAGE_ERROR_CAPTURE_ENTRY_VALID_MASK 0x40000
+
+/* MMU_UP_ACCESS_ERROR_CAPTURE */
+#define MMU_UP_ACCESS_ERROR_CAPTURE_VA_49_32_MASK 0x3FFFF
+#define MMU_UP_ACCESS_ERROR_CAPTURE_ENTRY_VALID_MASK 0x40000
+
+#define QM_ARB_ERR_MSG_EN_CHOISE_OVF_MASK 0x1
+#define QM_ARB_ERR_MSG_EN_CHOISE_WDT_MASK 0x2
+#define QM_ARB_ERR_MSG_EN_AXI_LBW_ERR_MASK 0x4
+
+#define QM_ARB_ERR_MSG_EN_MASK (\
+ QM_ARB_ERR_MSG_EN_CHOISE_OVF_MASK |\
+ QM_ARB_ERR_MSG_EN_CHOISE_WDT_MASK |\
+ QM_ARB_ERR_MSG_EN_AXI_LBW_ERR_MASK)
+
+#define PCIE_AUX_FLR_CTRL_HW_CTRL_MASK 0x1
+#define PCIE_AUX_FLR_CTRL_INT_MASK_MASK 0x2
+
+#define SYNC_MNGR_W_S_SYNC_MNGR_OBJS_MON_STATUS_0_VALID_SHIFT 0
+#define SYNC_MNGR_W_S_SYNC_MNGR_OBJS_MON_STATUS_0_VALID_MASK 0x1
+#define SYNC_MNGR_W_S_SYNC_MNGR_OBJS_MON_STATUS_0_PENDING_SHIFT 1
+#define SYNC_MNGR_W_S_SYNC_MNGR_OBJS_MON_STATUS_0_PENDING_MASK 0x1FE
+#define SYNC_MNGR_W_S_SYNC_MNGR_OBJS_MON_ARM_0_SID_SHIFT 0
+#define SYNC_MNGR_W_S_SYNC_MNGR_OBJS_MON_ARM_0_SID_MASK 0xFF
+#define SYNC_MNGR_W_S_SYNC_MNGR_OBJS_MON_ARM_0_MASK_SHIFT 8
+#define SYNC_MNGR_W_S_SYNC_MNGR_OBJS_MON_ARM_0_MASK_MASK 0xFF00
+#define SYNC_MNGR_W_S_SYNC_MNGR_OBJS_MON_ARM_0_SOP_SHIFT 16
+#define SYNC_MNGR_W_S_SYNC_MNGR_OBJS_MON_ARM_0_SOP_MASK 0x10000
+#define SYNC_MNGR_W_S_SYNC_MNGR_OBJS_MON_ARM_0_SOD_SHIFT 17
+#define SYNC_MNGR_W_S_SYNC_MNGR_OBJS_MON_ARM_0_SOD_MASK 0xFFFE0000
+#define TPC0_QM_CP_STS_0_FENCE_ID_SHIFT 20
+#define TPC0_QM_CP_STS_0_FENCE_ID_MASK 0x300000
+#define TPC0_QM_CP_STS_0_FENCE_IN_PROGRESS_SHIFT 22
+#define TPC0_QM_CP_STS_0_FENCE_IN_PROGRESS_MASK 0x400000
+
+#endif /* GAUDI_MASKS_H_ */
diff --git a/drivers/accel/habanalabs/include/gaudi/gaudi_packets.h b/drivers/accel/habanalabs/include/gaudi/gaudi_packets.h
new file mode 100644
index 0000000000..66fc083a7c
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi/gaudi_packets.h
@@ -0,0 +1,194 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2017-2020 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+#ifndef GAUDI_PACKETS_H
+#define GAUDI_PACKETS_H
+
+#include <linux/types.h>
+
+#define PACKET_HEADER_PACKET_ID_SHIFT 56
+#define PACKET_HEADER_PACKET_ID_MASK 0x1F00000000000000ull
+
+enum packet_id {
+ PACKET_WREG_32 = 0x1,
+ PACKET_WREG_BULK = 0x2,
+ PACKET_MSG_LONG = 0x3,
+ PACKET_MSG_SHORT = 0x4,
+ PACKET_CP_DMA = 0x5,
+ PACKET_REPEAT = 0x6,
+ PACKET_MSG_PROT = 0x7,
+ PACKET_FENCE = 0x8,
+ PACKET_LIN_DMA = 0x9,
+ PACKET_NOP = 0xA,
+ PACKET_STOP = 0xB,
+ PACKET_ARB_POINT = 0xC,
+ PACKET_WAIT = 0xD,
+ PACKET_LOAD_AND_EXE = 0xF,
+ MAX_PACKET_ID = (PACKET_HEADER_PACKET_ID_MASK >>
+ PACKET_HEADER_PACKET_ID_SHIFT) + 1
+};
+
+#define GAUDI_PKT_CTL_OPCODE_SHIFT 24
+#define GAUDI_PKT_CTL_OPCODE_MASK 0x1F000000
+
+#define GAUDI_PKT_CTL_EB_SHIFT 29
+#define GAUDI_PKT_CTL_EB_MASK 0x20000000
+
+#define GAUDI_PKT_CTL_RB_SHIFT 30
+#define GAUDI_PKT_CTL_RB_MASK 0x40000000
+
+#define GAUDI_PKT_CTL_MB_SHIFT 31
+#define GAUDI_PKT_CTL_MB_MASK 0x80000000
+
+/* All packets have, at least, an 8-byte header, which contains
+ * the packet type. The kernel driver uses the packet header for packet
+ * validation and to perform any necessary required preparation before
+ * sending them off to the hardware.
+ */
+struct gaudi_packet {
+ __le64 header;
+ /* The rest of the packet data follows. Use the corresponding
+ * packet_XXX struct to deference the data, based on packet type
+ */
+ u8 contents[];
+};
+
+struct packet_nop {
+ __le32 reserved;
+ __le32 ctl;
+};
+
+struct packet_stop {
+ __le32 reserved;
+ __le32 ctl;
+};
+
+struct packet_wreg32 {
+ __le32 value;
+ __le32 ctl;
+};
+
+struct packet_wreg_bulk {
+ __le32 size64;
+ __le32 ctl;
+ __le64 values[]; /* data starts here */
+};
+
+#define GAUDI_PKT_LONG_CTL_OP_SHIFT 20
+#define GAUDI_PKT_LONG_CTL_OP_MASK 0x00300000
+
+struct packet_msg_long {
+ __le32 value;
+ __le32 ctl;
+ __le64 addr;
+};
+
+#define GAUDI_PKT_SHORT_VAL_SOB_SYNC_VAL_SHIFT 0
+#define GAUDI_PKT_SHORT_VAL_SOB_SYNC_VAL_MASK 0x00007FFF
+
+#define GAUDI_PKT_SHORT_VAL_SOB_MOD_SHIFT 31
+#define GAUDI_PKT_SHORT_VAL_SOB_MOD_MASK 0x80000000
+
+#define GAUDI_PKT_SHORT_VAL_MON_SYNC_GID_SHIFT 0
+#define GAUDI_PKT_SHORT_VAL_MON_SYNC_GID_MASK 0x000000FF
+
+#define GAUDI_PKT_SHORT_VAL_MON_MASK_SHIFT 8
+#define GAUDI_PKT_SHORT_VAL_MON_MASK_MASK 0x0000FF00
+
+#define GAUDI_PKT_SHORT_VAL_MON_MODE_SHIFT 16
+#define GAUDI_PKT_SHORT_VAL_MON_MODE_MASK 0x00010000
+
+#define GAUDI_PKT_SHORT_VAL_MON_SYNC_VAL_SHIFT 17
+#define GAUDI_PKT_SHORT_VAL_MON_SYNC_VAL_MASK 0xFFFE0000
+
+#define GAUDI_PKT_SHORT_CTL_ADDR_SHIFT 0
+#define GAUDI_PKT_SHORT_CTL_ADDR_MASK 0x0000FFFF
+
+#define GAUDI_PKT_SHORT_CTL_OP_SHIFT 20
+#define GAUDI_PKT_SHORT_CTL_OP_MASK 0x00300000
+
+#define GAUDI_PKT_SHORT_CTL_BASE_SHIFT 22
+#define GAUDI_PKT_SHORT_CTL_BASE_MASK 0x00C00000
+
+struct packet_msg_short {
+ __le32 value;
+ __le32 ctl;
+};
+
+struct packet_msg_prot {
+ __le32 value;
+ __le32 ctl;
+ __le64 addr;
+};
+
+#define GAUDI_PKT_FENCE_CFG_DEC_VAL_SHIFT 0
+#define GAUDI_PKT_FENCE_CFG_DEC_VAL_MASK 0x0000000F
+
+#define GAUDI_PKT_FENCE_CFG_TARGET_VAL_SHIFT 16
+#define GAUDI_PKT_FENCE_CFG_TARGET_VAL_MASK 0x00FF0000
+
+#define GAUDI_PKT_FENCE_CFG_ID_SHIFT 30
+#define GAUDI_PKT_FENCE_CFG_ID_MASK 0xC0000000
+
+#define GAUDI_PKT_FENCE_CTL_PRED_SHIFT 0
+#define GAUDI_PKT_FENCE_CTL_PRED_MASK 0x0000001F
+
+struct packet_fence {
+ __le32 cfg;
+ __le32 ctl;
+};
+
+#define GAUDI_PKT_LIN_DMA_CTL_WRCOMP_EN_SHIFT 0
+#define GAUDI_PKT_LIN_DMA_CTL_WRCOMP_EN_MASK 0x00000001
+
+#define GAUDI_PKT_LIN_DMA_CTL_LIN_SHIFT 3
+#define GAUDI_PKT_LIN_DMA_CTL_LIN_MASK 0x00000008
+
+#define GAUDI_PKT_LIN_DMA_CTL_MEMSET_SHIFT 4
+#define GAUDI_PKT_LIN_DMA_CTL_MEMSET_MASK 0x00000010
+
+#define GAUDI_PKT_LIN_DMA_DST_ADDR_SHIFT 0
+#define GAUDI_PKT_LIN_DMA_DST_ADDR_MASK 0x00FFFFFFFFFFFFFFull
+
+struct packet_lin_dma {
+ __le32 tsize;
+ __le32 ctl;
+ __le64 src_addr;
+ __le64 dst_addr;
+};
+
+struct packet_arb_point {
+ __le32 cfg;
+ __le32 ctl;
+};
+
+struct packet_repeat {
+ __le32 cfg;
+ __le32 ctl;
+};
+
+struct packet_wait {
+ __le32 cfg;
+ __le32 ctl;
+};
+
+#define GAUDI_PKT_LOAD_AND_EXE_CFG_DST_SHIFT 0
+#define GAUDI_PKT_LOAD_AND_EXE_CFG_DST_MASK 0x00000001
+
+struct packet_load_and_exe {
+ __le32 cfg;
+ __le32 ctl;
+ __le64 src_addr;
+};
+
+struct packet_cp_dma {
+ __le32 tsize;
+ __le32 ctl;
+ __le64 src_addr;
+};
+
+#endif /* GAUDI_PACKETS_H */
diff --git a/drivers/accel/habanalabs/include/gaudi/gaudi_reg_map.h b/drivers/accel/habanalabs/include/gaudi/gaudi_reg_map.h
new file mode 100644
index 0000000000..92f25c2ae0
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi/gaudi_reg_map.h
@@ -0,0 +1,39 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2019-2020 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+#ifndef GAUDI_REG_MAP_H_
+#define GAUDI_REG_MAP_H_
+
+/*
+ * PSOC scratch-pad registers
+ */
+#define mmHW_STATE mmPSOC_GLOBAL_CONF_SCRATCHPAD_0
+#define mmGIC_HOST_PI_UPD_IRQ_POLL_REG mmPSOC_GLOBAL_CONF_SCRATCHPAD_1
+#define mmGIC_TPC_QM_IRQ_CTRL_POLL_REG mmPSOC_GLOBAL_CONF_SCRATCHPAD_2
+#define mmGIC_MME_QM_IRQ_CTRL_POLL_REG mmPSOC_GLOBAL_CONF_SCRATCHPAD_3
+#define mmGIC_DMA_QM_IRQ_CTRL_POLL_REG mmPSOC_GLOBAL_CONF_SCRATCHPAD_4
+#define mmGIC_NIC_QM_IRQ_CTRL_POLL_REG mmPSOC_GLOBAL_CONF_SCRATCHPAD_5
+#define mmGIC_DMA_CR_IRQ_CTRL_POLL_REG mmPSOC_GLOBAL_CONF_SCRATCHPAD_6
+#define mmGIC_HOST_HALT_IRQ_POLL_REG mmPSOC_GLOBAL_CONF_SCRATCHPAD_7
+#define mmGIC_HOST_INTS_IRQ_POLL_REG mmPSOC_GLOBAL_CONF_SCRATCHPAD_8
+#define mmCPU_BOOT_DEV_STS0 mmPSOC_GLOBAL_CONF_SCRATCHPAD_20
+#define mmCPU_BOOT_DEV_STS1 mmPSOC_GLOBAL_CONF_SCRATCHPAD_21
+#define mmFUSE_VER_OFFSET mmPSOC_GLOBAL_CONF_SCRATCHPAD_22
+#define mmCPU_CMD_STATUS_TO_HOST mmPSOC_GLOBAL_CONF_SCRATCHPAD_23
+#define mmCPU_BOOT_ERR0 mmPSOC_GLOBAL_CONF_SCRATCHPAD_24
+#define mmCPU_BOOT_ERR1 mmPSOC_GLOBAL_CONF_SCRATCHPAD_25
+#define mmUPD_STS mmPSOC_GLOBAL_CONF_SCRATCHPAD_26
+#define mmUPD_CMD mmPSOC_GLOBAL_CONF_SCRATCHPAD_27
+#define mmPREBOOT_VER_OFFSET mmPSOC_GLOBAL_CONF_SCRATCHPAD_28
+#define mmUBOOT_VER_OFFSET mmPSOC_GLOBAL_CONF_SCRATCHPAD_29
+#define mmRDWR_TEST mmPSOC_GLOBAL_CONF_SCRATCHPAD_30
+#define mmBTL_ID mmPSOC_GLOBAL_CONF_SCRATCHPAD_31
+#define mmPREBOOT_PCIE_EN mmPSOC_GLOBAL_CONF_COLD_RST_FLOPS_1
+#define mmCOLD_RST_DATA mmPSOC_GLOBAL_CONF_COLD_RST_FLOPS_2
+#define mmUPD_PENDING_STS mmPSOC_GLOBAL_CONF_COLD_RST_FLOPS_3
+
+#endif /* GAUDI_REG_MAP_H_ */