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| author | Daniel Baumann <daniel.baumann@progress-linux.org> | 2024-08-07 13:18:06 +0000 |
|---|---|---|
| committer | Daniel Baumann <daniel.baumann@progress-linux.org> | 2024-08-07 13:18:06 +0000 |
| commit | 638a9e433ecd61e64761352dbec1fa4f5874c941 (patch) | |
| tree | fdbff74a238d7a5a7d1cef071b7230bc064b9f25 /drivers/ata/pata_macio.c | |
| parent | Releasing progress-linux version 6.9.12-1~progress7.99u1. (diff) | |
| download | linux-638a9e433ecd61e64761352dbec1fa4f5874c941.tar.xz linux-638a9e433ecd61e64761352dbec1fa4f5874c941.zip | |
Merging upstream version 6.10.3.
Signed-off-by: Daniel Baumann <daniel.baumann@progress-linux.org>
Diffstat (limited to '')
| -rw-r--r-- | drivers/ata/pata_macio.c | 20 |
1 files changed, 12 insertions, 8 deletions
diff --git a/drivers/ata/pata_macio.c b/drivers/ata/pata_macio.c index 88b2e9817f..3cb455a32d 100644 --- a/drivers/ata/pata_macio.c +++ b/drivers/ata/pata_macio.c @@ -796,7 +796,8 @@ static void pata_macio_reset_hw(struct pata_macio_priv *priv, int resume) /* Hook the standard slave config to fixup some HW related alignment * restrictions */ -static int pata_macio_slave_config(struct scsi_device *sdev) +static int pata_macio_device_configure(struct scsi_device *sdev, + struct queue_limits *lim) { struct ata_port *ap = ata_shost_to_port(sdev->host); struct pata_macio_priv *priv = ap->private_data; @@ -805,7 +806,7 @@ static int pata_macio_slave_config(struct scsi_device *sdev) int rc; /* First call original */ - rc = ata_scsi_slave_config(sdev); + rc = ata_scsi_device_configure(sdev, lim); if (rc) return rc; @@ -814,7 +815,7 @@ static int pata_macio_slave_config(struct scsi_device *sdev) /* OHare has issues with non cache aligned DMA on some chipsets */ if (priv->kind == controller_ohare) { - blk_queue_update_dma_alignment(sdev->request_queue, 31); + lim->dma_alignment = 31; blk_queue_update_dma_pad(sdev->request_queue, 31); /* Tell the world about it */ @@ -829,7 +830,7 @@ static int pata_macio_slave_config(struct scsi_device *sdev) /* Shasta and K2 seem to have "issues" with reads ... */ if (priv->kind == controller_sh_ata6 || priv->kind == controller_k2_ata6) { /* Allright these are bad, apply restrictions */ - blk_queue_update_dma_alignment(sdev->request_queue, 15); + lim->dma_alignment = 15; blk_queue_update_dma_pad(sdev->request_queue, 15); /* We enable MWI and hack cache line size directly here, this @@ -914,11 +915,14 @@ static const struct scsi_host_template pata_macio_sht = { .sg_tablesize = MAX_DCMDS, /* We may not need that strict one */ .dma_boundary = ATA_DMA_BOUNDARY, - /* Not sure what the real max is but we know it's less than 64K, let's - * use 64K minus 256 + /* + * The SCSI core requires the segment size to cover at least a page, so + * for 64K page size kernels this must be at least 64K. However the + * hardware can't handle 64K, so pata_macio_qc_prep() will split large + * requests. */ - .max_segment_size = MAX_DBDMA_SEG, - .slave_configure = pata_macio_slave_config, + .max_segment_size = SZ_64K, + .device_configure = pata_macio_device_configure, .sdev_groups = ata_common_sdev_groups, .can_queue = ATA_DEF_QUEUE, .tag_alloc_policy = BLK_TAG_ALLOC_RR, |