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| author | Daniel Baumann <daniel.baumann@progress-linux.org> | 2024-05-18 17:35:05 +0000 |
|---|---|---|
| committer | Daniel Baumann <daniel.baumann@progress-linux.org> | 2024-05-18 17:39:31 +0000 |
| commit | 85c675d0d09a45a135bddd15d7b385f8758c32fb (patch) | |
| tree | 76267dbc9b9a130337be3640948fe397b04ac629 /drivers/clk/analogbits | |
| parent | Adding upstream version 6.6.15. (diff) | |
| download | linux-85c675d0d09a45a135bddd15d7b385f8758c32fb.tar.xz linux-85c675d0d09a45a135bddd15d7b385f8758c32fb.zip | |
Adding upstream version 6.7.7.upstream/6.7.7
Signed-off-by: Daniel Baumann <daniel.baumann@progress-linux.org>
Diffstat (limited to 'drivers/clk/analogbits')
| -rw-r--r-- | drivers/clk/analogbits/Kconfig | 2 | ||||
| -rw-r--r-- | drivers/clk/analogbits/wrpll-cln28hpc.c | 8 |
2 files changed, 9 insertions, 1 deletions
diff --git a/drivers/clk/analogbits/Kconfig b/drivers/clk/analogbits/Kconfig index 1e291b1854..7d73db0fcd 100644 --- a/drivers/clk/analogbits/Kconfig +++ b/drivers/clk/analogbits/Kconfig @@ -1,3 +1,3 @@ # SPDX-License-Identifier: GPL-2.0-only config CLK_ANALOGBITS_WRPLL_CLN28HPC - bool + tristate diff --git a/drivers/clk/analogbits/wrpll-cln28hpc.c b/drivers/clk/analogbits/wrpll-cln28hpc.c index 09ca823563..65d422a588 100644 --- a/drivers/clk/analogbits/wrpll-cln28hpc.c +++ b/drivers/clk/analogbits/wrpll-cln28hpc.c @@ -28,6 +28,7 @@ #include <linux/math64.h> #include <linux/math.h> #include <linux/minmax.h> +#include <linux/module.h> #include <linux/clk/analogbits-wrpll-cln28hpc.h> @@ -312,6 +313,7 @@ int wrpll_configure_for_rate(struct wrpll_cfg *c, u32 target_rate, return 0; } +EXPORT_SYMBOL_GPL(wrpll_configure_for_rate); /** * wrpll_calc_output_rate() - calculate the PLL's target output rate @@ -349,6 +351,7 @@ unsigned long wrpll_calc_output_rate(const struct wrpll_cfg *c, return n; } +EXPORT_SYMBOL_GPL(wrpll_calc_output_rate); /** * wrpll_calc_max_lock_us() - return the time for the PLL to lock @@ -366,3 +369,8 @@ unsigned int wrpll_calc_max_lock_us(const struct wrpll_cfg *c) { return MAX_LOCK_US; } +EXPORT_SYMBOL_GPL(wrpll_calc_max_lock_us); + +MODULE_AUTHOR("Paul Walmsley <paul.walmsley@sifive.com>"); +MODULE_DESCRIPTION("Analog Bits Wide-Range PLL library"); +MODULE_LICENSE("GPL"); |