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authorDaniel Baumann <daniel.baumann@progress-linux.org>2024-05-18 17:39:57 +0000
committerDaniel Baumann <daniel.baumann@progress-linux.org>2024-05-18 17:39:57 +0000
commitdc50eab76b709d68175a358d6e23a5a3890764d3 (patch)
treec754d0390db060af0213ff994f0ac310e4cfd6e9 /drivers/gpu/drm/amd/display/dc/dce112
parentAdding debian version 6.6.15-2. (diff)
downloadlinux-dc50eab76b709d68175a358d6e23a5a3890764d3.tar.xz
linux-dc50eab76b709d68175a358d6e23a5a3890764d3.zip
Merging upstream version 6.7.7.
Signed-off-by: Daniel Baumann <daniel.baumann@progress-linux.org>
Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/dce112')
-rw-r--r--drivers/gpu/drm/amd/display/dc/dce112/Makefile2
-rw-r--r--drivers/gpu/drm/amd/display/dc/dce112/dce112_hw_sequencer.c160
-rw-r--r--drivers/gpu/drm/amd/display/dc/dce112/dce112_hw_sequencer.h37
-rw-r--r--drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c2
4 files changed, 2 insertions, 199 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/dce112/Makefile b/drivers/gpu/drm/amd/display/dc/dce112/Makefile
index 9de6501702..e846ef58ca 100644
--- a/drivers/gpu/drm/amd/display/dc/dce112/Makefile
+++ b/drivers/gpu/drm/amd/display/dc/dce112/Makefile
@@ -25,7 +25,7 @@
CFLAGS_$(AMDDALPATH)/dc/dce112/dce112_resource.o = $(call cc-disable-warning, override-init)
-DCE112 = dce112_compressor.o dce112_hw_sequencer.o \
+DCE112 = dce112_compressor.o \
dce112_resource.o
AMD_DAL_DCE112 = $(addprefix $(AMDDALPATH)/dc/dce112/,$(DCE112))
diff --git a/drivers/gpu/drm/amd/display/dc/dce112/dce112_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce112/dce112_hw_sequencer.c
deleted file mode 100644
index 0ef9ebb3c1..0000000000
--- a/drivers/gpu/drm/amd/display/dc/dce112/dce112_hw_sequencer.c
+++ /dev/null
@@ -1,160 +0,0 @@
-/*
- * Copyright 2015 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: AMD
- *
- */
-
-#include "dm_services.h"
-#include "dc.h"
-#include "core_types.h"
-#include "dce112_hw_sequencer.h"
-
-#include "dce110/dce110_hw_sequencer.h"
-
-/* include DCE11.2 register header files */
-#include "dce/dce_11_2_d.h"
-#include "dce/dce_11_2_sh_mask.h"
-
-struct dce112_hw_seq_reg_offsets {
- uint32_t crtc;
-};
-
-
-static const struct dce112_hw_seq_reg_offsets reg_offsets[] = {
-{
- .crtc = (mmCRTC0_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
-},
-{
- .crtc = (mmCRTC1_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
-},
-{
- .crtc = (mmCRTC2_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
-},
-{
- .crtc = (mmCRTC3_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
-},
-{
- .crtc = (mmCRTC4_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
-},
-{
- .crtc = (mmCRTC5_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
-}
-};
-#define HW_REG_CRTC(reg, id)\
- (reg + reg_offsets[id].crtc)
-
-/*******************************************************************************
- * Private definitions
- ******************************************************************************/
-
-static void dce112_init_pte(struct dc_context *ctx)
-{
- uint32_t addr;
- uint32_t value = 0;
- uint32_t chunk_int = 0;
- uint32_t chunk_mul = 0;
-
- addr = mmDVMM_PTE_REQ;
- value = dm_read_reg(ctx, addr);
-
- chunk_int = get_reg_field_value(
- value,
- DVMM_PTE_REQ,
- HFLIP_PTEREQ_PER_CHUNK_INT);
-
- chunk_mul = get_reg_field_value(
- value,
- DVMM_PTE_REQ,
- HFLIP_PTEREQ_PER_CHUNK_MULTIPLIER);
-
- if (chunk_int != 0x4 || chunk_mul != 0x4) {
-
- set_reg_field_value(
- value,
- 255,
- DVMM_PTE_REQ,
- MAX_PTEREQ_TO_ISSUE);
-
- set_reg_field_value(
- value,
- 4,
- DVMM_PTE_REQ,
- HFLIP_PTEREQ_PER_CHUNK_INT);
-
- set_reg_field_value(
- value,
- 4,
- DVMM_PTE_REQ,
- HFLIP_PTEREQ_PER_CHUNK_MULTIPLIER);
-
- dm_write_reg(ctx, addr, value);
- }
-}
-
-static bool dce112_enable_display_power_gating(
- struct dc *dc,
- uint8_t controller_id,
- struct dc_bios *dcb,
- enum pipe_gating_control power_gating)
-{
- enum bp_result bp_result = BP_RESULT_OK;
- enum bp_pipe_control_action cntl;
- struct dc_context *ctx = dc->ctx;
-
- if (power_gating == PIPE_GATING_CONTROL_INIT)
- cntl = ASIC_PIPE_INIT;
- else if (power_gating == PIPE_GATING_CONTROL_ENABLE)
- cntl = ASIC_PIPE_ENABLE;
- else
- cntl = ASIC_PIPE_DISABLE;
-
- if (power_gating != PIPE_GATING_CONTROL_INIT || controller_id == 0) {
-
- bp_result = dcb->funcs->enable_disp_power_gating(
- dcb, controller_id + 1, cntl);
-
- /* Revert MASTER_UPDATE_MODE to 0 because bios sets it 2
- * by default when command table is called
- */
- dm_write_reg(ctx,
- HW_REG_CRTC(mmCRTC_MASTER_UPDATE_MODE, controller_id),
- 0);
- }
-
- if (power_gating != PIPE_GATING_CONTROL_ENABLE)
- dce112_init_pte(ctx);
-
- if (bp_result == BP_RESULT_OK)
- return true;
- else
- return false;
-}
-
-void dce112_hw_sequencer_construct(struct dc *dc)
-{
- /* All registers used by dce11.2 match those in dce11 in offset and
- * structure
- */
- dce110_hw_sequencer_construct(dc);
- dc->hwseq->funcs.enable_display_power_gating = dce112_enable_display_power_gating;
-}
-
diff --git a/drivers/gpu/drm/amd/display/dc/dce112/dce112_hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/dce112/dce112_hw_sequencer.h
deleted file mode 100644
index 943f1b2c5b..0000000000
--- a/drivers/gpu/drm/amd/display/dc/dce112/dce112_hw_sequencer.h
+++ /dev/null
@@ -1,37 +0,0 @@
-/*
-* Copyright 2012-15 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: AMD
- *
- */
-
-#ifndef __DC_HWSS_DCE112_H__
-#define __DC_HWSS_DCE112_H__
-
-#include "core_types.h"
-#include "hw_sequencer_private.h"
-
-struct dc;
-
-void dce112_hw_sequencer_construct(struct dc *dc);
-
-#endif /* __DC_HWSS_DCE112_H__ */
-
diff --git a/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c b/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c
index 2b20180f1a..d1edac46c9 100644
--- a/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c
@@ -44,7 +44,7 @@
#include "dce/dce_clock_source.h"
#include "dce/dce_hwseq.h"
-#include "dce112/dce112_hw_sequencer.h"
+#include "dce112/dce112_hwseq.h"
#include "dce/dce_abm.h"
#include "dce/dce_dmcu.h"
#include "dce/dce_aux.h"