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author | Daniel Baumann <daniel.baumann@progress-linux.org> | 2024-05-18 17:35:05 +0000 |
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committer | Daniel Baumann <daniel.baumann@progress-linux.org> | 2024-05-18 17:39:31 +0000 |
commit | 85c675d0d09a45a135bddd15d7b385f8758c32fb (patch) | |
tree | 76267dbc9b9a130337be3640948fe397b04ac629 /drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.h | |
parent | Adding upstream version 6.6.15. (diff) | |
download | linux-85c675d0d09a45a135bddd15d7b385f8758c32fb.tar.xz linux-85c675d0d09a45a135bddd15d7b385f8758c32fb.zip |
Adding upstream version 6.7.7.upstream/6.7.7
Signed-off-by: Daniel Baumann <daniel.baumann@progress-linux.org>
Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.h')
-rw-r--r-- | drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.h | 64 |
1 files changed, 64 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.h b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.h index c8602bcfa..ab6d09c6f 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.h +++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.h @@ -240,12 +240,66 @@ type DTBCLK_P3_EN;\ type DENTIST_DISPCLK_CHG_DONE; +#define DCCG35_REG_FIELD_LIST(type) \ + type DPPCLK0_EN;\ + type DPPCLK1_EN;\ + type DPPCLK2_EN;\ + type DPPCLK3_EN;\ + type DSCCLK0_EN;\ + type DSCCLK1_EN;\ + type DSCCLK2_EN;\ + type DSCCLK3_EN;\ + type DISPCLK_DCCG_GATE_DISABLE;\ + type DCCG_GLOBAL_FGCG_REP_DIS; \ + type PHYASYMCLK_EN;\ + type PHYASYMCLK_SRC_SEL;\ + type PHYBSYMCLK_EN;\ + type PHYBSYMCLK_SRC_SEL;\ + type PHYCSYMCLK_EN;\ + type PHYCSYMCLK_SRC_SEL;\ + type PHYDSYMCLK_EN;\ + type PHYDSYMCLK_SRC_SEL;\ + type PHYESYMCLK_EN;\ + type PHYESYMCLK_SRC_SEL;\ + type PHYASYMCLK_ROOT_GATE_DISABLE;\ + type PHYBSYMCLK_ROOT_GATE_DISABLE;\ + type PHYCSYMCLK_ROOT_GATE_DISABLE;\ + type PHYDSYMCLK_ROOT_GATE_DISABLE;\ + type PHYESYMCLK_ROOT_GATE_DISABLE;\ + type HDMISTREAMCLK0_GATE_DISABLE;\ + type HDMISTREAMCLK1_GATE_DISABLE;\ + type HDMISTREAMCLK2_GATE_DISABLE;\ + type HDMISTREAMCLK3_GATE_DISABLE;\ + type HDMISTREAMCLK4_GATE_DISABLE;\ + type HDMISTREAMCLK5_GATE_DISABLE;\ + type SYMCLKA_CLOCK_ENABLE;\ + type SYMCLKB_CLOCK_ENABLE;\ + type SYMCLKC_CLOCK_ENABLE;\ + type SYMCLKD_CLOCK_ENABLE;\ + type SYMCLKE_CLOCK_ENABLE;\ + type SYMCLKA_FE_EN;\ + type SYMCLKB_FE_EN;\ + type SYMCLKC_FE_EN;\ + type SYMCLKD_FE_EN;\ + type SYMCLKE_FE_EN;\ + type SYMCLKA_SRC_SEL;\ + type SYMCLKB_SRC_SEL;\ + type SYMCLKC_SRC_SEL;\ + type SYMCLKD_SRC_SEL;\ + type SYMCLKE_SRC_SEL;\ + type SYMCLKA_FE_SRC_SEL;\ + type SYMCLKB_FE_SRC_SEL;\ + type SYMCLKC_FE_SRC_SEL;\ + type SYMCLKD_FE_SRC_SEL;\ + type SYMCLKE_FE_SRC_SEL; + struct dccg_shift { DCCG_REG_FIELD_LIST(uint8_t) DCCG3_REG_FIELD_LIST(uint8_t) DCCG31_REG_FIELD_LIST(uint8_t) DCCG314_REG_FIELD_LIST(uint8_t) DCCG32_REG_FIELD_LIST(uint8_t) + DCCG35_REG_FIELD_LIST(uint8_t) }; struct dccg_mask { @@ -254,6 +308,7 @@ struct dccg_mask { DCCG31_REG_FIELD_LIST(uint32_t) DCCG314_REG_FIELD_LIST(uint32_t) DCCG32_REG_FIELD_LIST(uint32_t) + DCCG35_REG_FIELD_LIST(uint32_t) }; struct dccg_registers { @@ -292,6 +347,15 @@ struct dccg_registers { uint32_t DCCG_GATE_DISABLE_CNTL4; uint32_t OTG_PIXEL_RATE_DIV; uint32_t DTBCLK_P_CNTL; + uint32_t DPPCLK_CTRL; + uint32_t DCCG_GATE_DISABLE_CNTL5; + uint32_t DCCG_GATE_DISABLE_CNTL6; + uint32_t DCCG_GLOBAL_FGCG_REP_CNTL; + uint32_t SYMCLKA_CLOCK_ENABLE; + uint32_t SYMCLKB_CLOCK_ENABLE; + uint32_t SYMCLKC_CLOCK_ENABLE; + uint32_t SYMCLKD_CLOCK_ENABLE; + uint32_t SYMCLKE_CLOCK_ENABLE; }; struct dcn_dccg { |