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author | Daniel Baumann <daniel.baumann@progress-linux.org> | 2024-05-18 17:39:57 +0000 |
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committer | Daniel Baumann <daniel.baumann@progress-linux.org> | 2024-05-18 17:39:57 +0000 |
commit | dc50eab76b709d68175a358d6e23a5a3890764d3 (patch) | |
tree | c754d0390db060af0213ff994f0ac310e4cfd6e9 /drivers/gpu/drm/amd/include/asic_reg/mp/mp_13_0_6_sh_mask.h | |
parent | Adding debian version 6.6.15-2. (diff) | |
download | linux-dc50eab76b709d68175a358d6e23a5a3890764d3.tar.xz linux-dc50eab76b709d68175a358d6e23a5a3890764d3.zip |
Merging upstream version 6.7.7.
Signed-off-by: Daniel Baumann <daniel.baumann@progress-linux.org>
Diffstat (limited to 'drivers/gpu/drm/amd/include/asic_reg/mp/mp_13_0_6_sh_mask.h')
-rw-r--r-- | drivers/gpu/drm/amd/include/asic_reg/mp/mp_13_0_6_sh_mask.h | 28 |
1 files changed, 28 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/include/asic_reg/mp/mp_13_0_6_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/mp/mp_13_0_6_sh_mask.h index 780d9824d5..2684e396f5 100644 --- a/drivers/gpu/drm/amd/include/asic_reg/mp/mp_13_0_6_sh_mask.h +++ b/drivers/gpu/drm/amd/include/asic_reg/mp/mp_13_0_6_sh_mask.h @@ -670,5 +670,33 @@ #define MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK 0x00000001L #define MP1_FIRMWARE_FLAGS__RESERVED_MASK 0xFFFFFFFEL +//MCMP1_IPIDT0 +#define MCMP1_IPIDT0__InstanceIdLo__SHIFT 0x0 +#define MCMP1_IPIDT0__HardwareID__SHIFT 0x20 +#define MCMP1_IPIDT0__InstanceIdHi__SHIFT 0x2c +#define MCMP1_IPIDT0__McaType__SHIFT 0x30 + +#define MCMP1_IPIDT0__InstanceIdLo_MASK 0x00000000FFFFFFFFL +#define MCMP1_IPIDT0__HardwareID_MASK 0x00000FFF00000000L +#define MCMP1_IPIDT0__InstanceIdHi_MASK 0x0000F00000000000L +#define MCMP1_IPIDT0__McaType_MASK 0xFFFF000000000000L + +//MCMP1_STATUST0 +#define MCMP1_STATUST0__ErrorCode__SHIFT 0x0 +#define MCMP1_STATUST0__ErrorCodeExt__SHIFT 0x10 +#define MCMP1_STATUST0__PCC__SHIFT 0x39 +#define MCMP1_STATUST0__UC__SHIFT 0x3d +#define MCMP1_STATUST0__Val__SHIFT 0x3f + +#define MCMP1_STATUST0__ErrorCode_MASK 0x000000000000FFFFL +#define MCMP1_STATUST0__ErrorCodeExt_MASK 0x00000000003F0000L +#define MCMP1_STATUST0__PCC_MASK 0x0200000000000000L +#define MCMP1_STATUST0__UC_MASK 0x2000000000000000L +#define MCMP1_STATUST0__Val_MASK 0x8000000000000000L + +//MCMP1_MISC0T0 +#define MCMP1_MISC0T0__ErrCnt__SHIFT 0x20 + +#define MCMP1_MISC0T0__ErrCnt_MASK 0x00000FFF00000000L #endif |