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| author | Daniel Baumann <daniel.baumann@progress-linux.org> | 2024-04-11 08:27:49 +0000 |
|---|---|---|
| committer | Daniel Baumann <daniel.baumann@progress-linux.org> | 2024-04-11 08:27:49 +0000 |
| commit | ace9429bb58fd418f0c81d4c2835699bddf6bde6 (patch) | |
| tree | b2d64bc10158fdd5497876388cd68142ca374ed3 /drivers/pinctrl/qcom | |
| parent | Initial commit. (diff) | |
| download | linux-ace9429bb58fd418f0c81d4c2835699bddf6bde6.tar.xz linux-ace9429bb58fd418f0c81d4c2835699bddf6bde6.zip | |
Adding upstream version 6.6.15.upstream/6.6.15
Signed-off-by: Daniel Baumann <daniel.baumann@progress-linux.org>
Diffstat (limited to 'drivers/pinctrl/qcom')
65 files changed, 65446 insertions, 0 deletions
diff --git a/drivers/pinctrl/qcom/Kconfig b/drivers/pinctrl/qcom/Kconfig new file mode 100644 index 0000000000..f84c0d3b79 --- /dev/null +++ b/drivers/pinctrl/qcom/Kconfig @@ -0,0 +1,127 @@ +# SPDX-License-Identifier: GPL-2.0-only +if (ARCH_QCOM || COMPILE_TEST) + +config PINCTRL_MSM + tristate "Qualcomm core pin controller driver" + depends on GPIOLIB + # OF for pinconf_generic_dt_node_to_map_group() from GENERIC_PINCONF + depends on OF + select QCOM_SCM + select PINMUX + select PINCONF + select GENERIC_PINCONF + select GPIOLIB_IRQCHIP + select IRQ_DOMAIN_HIERARCHY + select IRQ_FASTEOI_HIERARCHY_HANDLERS + +source "drivers/pinctrl/qcom/Kconfig.msm" + +config PINCTRL_QCOM_SPMI_PMIC + tristate "Qualcomm SPMI PMIC pin controller driver" + depends on OF && SPMI + select REGMAP_SPMI + select PINMUX + select PINCONF + select GENERIC_PINCONF + select GPIOLIB + select GPIOLIB_IRQCHIP + select IRQ_DOMAIN_HIERARCHY + help + This is the pinctrl, pinmux, pinconf and gpiolib driver for the + Qualcomm GPIO and MPP blocks found in the Qualcomm PMIC's chips, + which are using SPMI for communication with SoC. Example PMIC's + devices are pm8841, pm8941 and pma8084. + +config PINCTRL_QCOM_SSBI_PMIC + tristate "Qualcomm SSBI PMIC pin controller driver" + depends on OF + select PINMUX + select PINCONF + select GENERIC_PINCONF + select GPIOLIB + select GPIOLIB_IRQCHIP + select IRQ_DOMAIN_HIERARCHY + help + This is the pinctrl, pinmux, pinconf and gpiolib driver for the + Qualcomm GPIO and MPP blocks found in the Qualcomm PMIC's chips, + which are using SSBI for communication with SoC. Example PMIC's + devices are pm8058 and pm8921. + +config PINCTRL_LPASS_LPI + tristate "Qualcomm Technologies Inc LPASS LPI pin controller driver" + select PINMUX + select PINCONF + select GENERIC_PINCONF + select GENERIC_PINCTRL_GROUPS + depends on GPIOLIB + help + This is the pinctrl, pinmux, pinconf and gpiolib driver for the + Qualcomm Technologies Inc LPASS (Low Power Audio SubSystem) LPI + (Low Power Island) found on the Qualcomm Technologies Inc SoCs. + +config PINCTRL_SC7280_LPASS_LPI + tristate "Qualcomm Technologies Inc SC7280 LPASS LPI pin controller driver" + depends on ARM64 || COMPILE_TEST + depends on PINCTRL_LPASS_LPI + help + This is the pinctrl, pinmux, pinconf and gpiolib driver for the + Qualcomm Technologies Inc LPASS (Low Power Audio SubSystem) LPI + (Low Power Island) found on the Qualcomm Technologies Inc SC7280 platform. + +config PINCTRL_SM6115_LPASS_LPI + tristate "Qualcomm Technologies Inc SM6115 LPASS LPI pin controller driver" + depends on ARM64 || COMPILE_TEST + depends on PINCTRL_LPASS_LPI + help + This is the pinctrl, pinmux, pinconf and gpiolib driver for the + Qualcomm Technologies Inc LPASS (Low Power Audio SubSystem) LPI + (Low Power Island) found on the Qualcomm Technologies Inc SM6115 platform. + +config PINCTRL_SM8250_LPASS_LPI + tristate "Qualcomm Technologies Inc SM8250 LPASS LPI pin controller driver" + depends on ARM64 || COMPILE_TEST + depends on PINCTRL_LPASS_LPI + help + This is the pinctrl, pinmux, pinconf and gpiolib driver for the + Qualcomm Technologies Inc LPASS (Low Power Audio SubSystem) LPI + (Low Power Island) found on the Qualcomm Technologies Inc SM8250 platform. + +config PINCTRL_SM8350_LPASS_LPI + tristate "Qualcomm Technologies Inc SM8350 LPASS LPI pin controller driver" + depends on ARM64 || COMPILE_TEST + depends on PINCTRL_LPASS_LPI + help + This is the pinctrl, pinmux, pinconf and gpiolib driver for the + Qualcomm Technologies Inc LPASS (Low Power Audio SubSystem) LPI + (Low Power Island) found on the Qualcomm Technologies Inc SM8350 + platform. + +config PINCTRL_SM8450_LPASS_LPI + tristate "Qualcomm Technologies Inc SM8450 LPASS LPI pin controller driver" + depends on ARM64 || COMPILE_TEST + depends on PINCTRL_LPASS_LPI + help + This is the pinctrl, pinmux, pinconf and gpiolib driver for the + Qualcomm Technologies Inc LPASS (Low Power Audio SubSystem) LPI + (Low Power Island) found on the Qualcomm Technologies Inc SM8450 platform. + +config PINCTRL_SC8280XP_LPASS_LPI + tristate "Qualcomm Technologies Inc SC8280XP LPASS LPI pin controller driver" + depends on ARM64 || COMPILE_TEST + depends on PINCTRL_LPASS_LPI + help + This is the pinctrl, pinmux, pinconf and gpiolib driver for the + Qualcomm Technologies Inc LPASS (Low Power Audio SubSystem) LPI + (Low Power Island) found on the Qualcomm Technologies Inc SC8280XP platform. + +config PINCTRL_SM8550_LPASS_LPI + tristate "Qualcomm Technologies Inc SM8550 LPASS LPI pin controller driver" + depends on ARM64 || COMPILE_TEST + depends on PINCTRL_LPASS_LPI + help + This is the pinctrl, pinmux, pinconf and gpiolib driver for the + Qualcomm Technologies Inc LPASS (Low Power Audio SubSystem) LPI + (Low Power Island) found on the Qualcomm Technologies Inc SM8550 + platform. + +endif diff --git a/drivers/pinctrl/qcom/Kconfig.msm b/drivers/pinctrl/qcom/Kconfig.msm new file mode 100644 index 0000000000..01dd7b1343 --- /dev/null +++ b/drivers/pinctrl/qcom/Kconfig.msm @@ -0,0 +1,369 @@ +# SPDX-License-Identifier: GPL-2.0-only +if PINCTRL_MSM + +config PINCTRL_APQ8064 + tristate "Qualcomm APQ8064 pin controller driver" + depends on ARM || COMPILE_TEST + help + This is the pinctrl, pinmux, pinconf and gpiolib driver for the + Qualcomm TLMM block found in the Qualcomm APQ8064 platform. + +config PINCTRL_APQ8084 + tristate "Qualcomm APQ8084 pin controller driver" + depends on ARM || COMPILE_TEST + help + This is the pinctrl, pinmux, pinconf and gpiolib driver for the + Qualcomm TLMM block found in the Qualcomm APQ8084 platform. + +config PINCTRL_IPQ4019 + tristate "Qualcomm IPQ4019 pin controller driver" + depends on ARM || COMPILE_TEST + help + This is the pinctrl, pinmux, pinconf and gpiolib driver for the + Qualcomm TLMM block found in the Qualcomm IPQ4019 platform. + +config PINCTRL_IPQ5018 + tristate "Qualcomm Technologies, Inc. IPQ5018 pin controller driver" + depends on ARM64 || COMPILE_TEST + help + This is the pinctrl, pinmux, pinconf and gpiolib driver for + the Qualcomm Technologies Inc. TLMM block found on the + Qualcomm Technologies Inc. IPQ5018 platform. Select this for + IPQ5018. + +config PINCTRL_IPQ8064 + tristate "Qualcomm IPQ8064 pin controller driver" + depends on ARM || COMPILE_TEST + help + This is the pinctrl, pinmux, pinconf and gpiolib driver for the + Qualcomm TLMM block found in the Qualcomm IPQ8064 platform. + +config PINCTRL_IPQ5332 + tristate "Qualcomm Technologies Inc IPQ5332 pin controller driver" + depends on ARM64 || COMPILE_TEST + help + This is the pinctrl, pinmux, pinconf and gpiolib driver for the + Qualcomm Technologies Inc TLMM block found on the Qualcomm + Technologies Inc IPQ5332 platform. + +config PINCTRL_IPQ8074 + tristate "Qualcomm Technologies, Inc. IPQ8074 pin controller driver" + depends on ARM64 || COMPILE_TEST + help + This is the pinctrl, pinmux, pinconf and gpiolib driver for + the Qualcomm Technologies Inc. TLMM block found on the + Qualcomm Technologies Inc. IPQ8074 platform. Select this for + IPQ8074. + +config PINCTRL_IPQ6018 + tristate "Qualcomm Technologies, Inc. IPQ6018 pin controller driver" + depends on ARM64 || COMPILE_TEST + help + This is the pinctrl, pinmux, pinconf and gpiolib driver for + the Qualcomm Technologies Inc. TLMM block found on the + Qualcomm Technologies Inc. IPQ6018 platform. Select this for + IPQ6018. + +config PINCTRL_IPQ9574 + tristate "Qualcomm Technologies, Inc. IPQ9574 pin controller driver" + depends on ARM64 || COMPILE_TEST + help + This is the pinctrl, pinmux, pinconf and gpiolib driver for + the Qualcomm Technologies Inc. TLMM block found on the + Qualcomm Technologies Inc. IPQ9574 platform. Select this for + IPQ9574. + +config PINCTRL_MSM8226 + tristate "Qualcomm 8226 pin controller driver" + depends on ARM || COMPILE_TEST + help + This is the pinctrl, pinmux, pinconf and gpiolib driver for the + Qualcomm Technologies Inc TLMM block found on the Qualcomm + Technologies Inc MSM8226 platform. + +config PINCTRL_MSM8660 + tristate "Qualcomm 8660 pin controller driver" + depends on ARM || COMPILE_TEST + help + This is the pinctrl, pinmux, pinconf and gpiolib driver for the + Qualcomm TLMM block found in the Qualcomm 8660 platform. + +config PINCTRL_MSM8960 + tristate "Qualcomm 8960 pin controller driver" + depends on ARM || COMPILE_TEST + help + This is the pinctrl, pinmux, pinconf and gpiolib driver for the + Qualcomm TLMM block found in the Qualcomm 8960 platform. + +config PINCTRL_MDM9607 + tristate "Qualcomm 9607 pin controller driver" + help + This is the pinctrl, pinmux, pinconf and gpiolib driver for the + Qualcomm TLMM block found in the Qualcomm 9607 platform. + +config PINCTRL_MDM9615 + tristate "Qualcomm 9615 pin controller driver" + depends on ARM || COMPILE_TEST + help + This is the pinctrl, pinmux, pinconf and gpiolib driver for the + Qualcomm TLMM block found in the Qualcomm 9615 platform. + +config PINCTRL_MSM8X74 + tristate "Qualcomm 8x74 pin controller driver" + depends on ARM || COMPILE_TEST + help + This is the pinctrl, pinmux, pinconf and gpiolib driver for the + Qualcomm TLMM block found in the Qualcomm 8974 platform. + +config PINCTRL_MSM8909 + tristate "Qualcomm 8909 pin controller driver" + depends on ARM || COMPILE_TEST + help + This is the pinctrl, pinmux, pinconf and gpiolib driver for the + Qualcomm TLMM block found on the Qualcomm MSM8909 platform. + +config PINCTRL_MSM8916 + tristate "Qualcomm 8916 pin controller driver" + help + This is the pinctrl, pinmux, pinconf and gpiolib driver for the + Qualcomm TLMM block found on the Qualcomm 8916 platform. + +config PINCTRL_MSM8953 + tristate "Qualcomm 8953 pin controller driver" + depends on ARM64 || COMPILE_TEST + help + This is the pinctrl, pinmux, pinconf and gpiolib driver for the + Qualcomm TLMM block found on the Qualcomm MSM8953 platform. + The Qualcomm APQ8053, SDM450, SDM632 platforms are also + supported by this driver. + +config PINCTRL_MSM8976 + tristate "Qualcomm 8976 pin controller driver" + depends on ARM64 || COMPILE_TEST + help + This is the pinctrl, pinmux, pinconf and gpiolib driver for the + Qualcomm TLMM block found on the Qualcomm MSM8976 platform. + The Qualcomm MSM8956, APQ8056, APQ8076 platforms are also + supported by this driver. + +config PINCTRL_MSM8994 + tristate "Qualcomm 8994 pin controller driver" + depends on ARM64 || COMPILE_TEST + help + This is the pinctrl, pinmux, pinconf and gpiolib driver for the + Qualcomm TLMM block found in the Qualcomm 8994 platform. The + Qualcomm 8992 platform is also supported by this driver. + +config PINCTRL_MSM8996 + tristate "Qualcomm MSM8996 pin controller driver" + depends on ARM64 || COMPILE_TEST + help + This is the pinctrl, pinmux, pinconf and gpiolib driver for the + Qualcomm TLMM block found in the Qualcomm MSM8996 platform. + +config PINCTRL_MSM8998 + tristate "Qualcomm MSM8998 pin controller driver" + depends on ARM64 || COMPILE_TEST + help + This is the pinctrl, pinmux, pinconf and gpiolib driver for the + Qualcomm TLMM block found in the Qualcomm MSM8998 platform. + +config PINCTRL_QCM2290 + tristate "Qualcomm QCM2290 pin controller driver" + depends on ARM64 || COMPILE_TEST + help + This is the pinctrl, pinmux, pinconf and gpiolib driver for the + TLMM block found in the Qualcomm QCM2290 platform. + +config PINCTRL_QCS404 + tristate "Qualcomm QCS404 pin controller driver" + depends on ARM64 || COMPILE_TEST + help + This is the pinctrl, pinmux, pinconf and gpiolib driver for the + TLMM block found in the Qualcomm QCS404 platform. + +config PINCTRL_QDF2XXX + tristate "Qualcomm Technologies QDF2xxx pin controller driver" + depends on ACPI + help + This is the GPIO driver for the TLMM block found on the + Qualcomm Technologies QDF2xxx SOCs. + +config PINCTRL_QDU1000 + tristate "Qualcomm Technologies Inc QDU1000/QRU1000 pin controller driver" + depends on ARM64 || COMPILE_TEST + help + This is the pinctrl, pinmux, pinconf, and gpiolib driver for the + Qualcomm Technologies Inc TLMM block found on the Qualcomm + Technologies Inc QDU1000 and QRU1000 platforms. + +config PINCTRL_SA8775P + tristate "Qualcomm Technologies Inc SA8775P pin controller driver" + depends on ARM64 || COMPILE_TEST + help + This is the pinctrl, pinmux and pinconf driver for the Qualcomm + TLMM block found on the Qualcomm SA8775P platforms. + +config PINCTRL_SC7180 + tristate "Qualcomm Technologies Inc SC7180 pin controller driver" + depends on ARM64 || COMPILE_TEST + help + This is the pinctrl, pinmux, pinconf and gpiolib driver for the + Qualcomm Technologies Inc TLMM block found on the Qualcomm + Technologies Inc SC7180 platform. + +config PINCTRL_SC7280 + tristate "Qualcomm Technologies Inc SC7280 pin controller driver" + depends on ARM64 || COMPILE_TEST + help + This is the pinctrl, pinmux, pinconf and gpiolib driver for the + Qualcomm Technologies Inc TLMM block found on the Qualcomm + Technologies Inc SC7280 platform. + +config PINCTRL_SC8180X + tristate "Qualcomm Technologies Inc SC8180x pin controller driver" + depends on (OF || ACPI) + depends on ARM64 || COMPILE_TEST + help + This is the pinctrl, pinmux, pinconf and gpiolib driver for the + Qualcomm Technologies Inc TLMM block found on the Qualcomm + Technologies Inc SC8180x platform. + +config PINCTRL_SC8280XP + tristate "Qualcomm Technologies Inc SC8280xp pin controller driver" + depends on ARM64 || COMPILE_TEST + help + This is the pinctrl, pinmux, pinconf and gpiolib driver for the + Qualcomm Technologies Inc TLMM block found on the Qualcomm + Technologies Inc SC8280xp platform. + +config PINCTRL_SDM660 + tristate "Qualcomm Technologies Inc SDM660 pin controller driver" + depends on ARM64 || COMPILE_TEST + help + This is the pinctrl, pinmux, pinconf and gpiolib driver for the + Qualcomm Technologies Inc TLMM block found on the Qualcomm + Technologies Inc SDM660 platform. + +config PINCTRL_SDM670 + tristate "Qualcomm Technologies Inc SDM670 pin controller driver" + depends on ARM64 || COMPILE_TEST + help + This is the pinctrl, pinmux, pinconf and gpiolib driver for the + Qualcomm Technologies Inc TLMM block found on the Qualcomm + Technologies Inc SDM670 platform. + +config PINCTRL_SDM845 + tristate "Qualcomm Technologies Inc SDM845 pin controller driver" + depends on (OF || ACPI) + depends on ARM64 || COMPILE_TEST + help + This is the pinctrl, pinmux, pinconf and gpiolib driver for the + Qualcomm Technologies Inc TLMM block found on the Qualcomm + Technologies Inc SDM845 platform. + +config PINCTRL_SDX55 + tristate "Qualcomm Technologies Inc SDX55 pin controller driver" + depends on ARM || COMPILE_TEST + help + This is the pinctrl, pinmux, pinconf and gpiolib driver for the + Qualcomm Technologies Inc TLMM block found on the Qualcomm + Technologies Inc SDX55 platform. + +config PINCTRL_SDX65 + tristate "Qualcomm Technologies Inc SDX65 pin controller driver" + depends on ARM || COMPILE_TEST + help + This is the pinctrl, pinmux, pinconf and gpiolib driver for the + Qualcomm Technologies Inc TLMM block found on the Qualcomm + Technologies Inc SDX65 platform. + +config PINCTRL_SDX75 + tristate "Qualcomm Technologies Inc SDX75 pin controller driver" + depends on ARM64 || COMPILE_TEST + help + This is the pinctrl, pinmux, pinconf and gpiolib driver for the + Qualcomm Technologies Inc TLMM block found on the Qualcomm + Technologies Inc SDX75 platform. + +config PINCTRL_SM6115 + tristate "Qualcomm Technologies Inc SM6115,SM4250 pin controller driver" + depends on ARM64 || COMPILE_TEST + help + This is the pinctrl, pinmux, pinconf and gpiolib driver for the + Qualcomm Technologies Inc TLMM block found on the Qualcomm + Technologies Inc SM6115 and SM4250 platforms. + +config PINCTRL_SM6125 + tristate "Qualcomm Technologies Inc SM6125 pin controller driver" + depends on ARM64 || COMPILE_TEST + help + This is the pinctrl, pinmux, pinconf and gpiolib driver for the + Qualcomm Technologies Inc TLMM block found on the Qualcomm + Technologies Inc SM6125 platform. + +config PINCTRL_SM6350 + tristate "Qualcomm Technologies Inc SM6350 pin controller driver" + depends on ARM64 || COMPILE_TEST + help + This is the pinctrl, pinmux, pinconf and gpiolib driver for the + Qualcomm Technologies Inc TLMM block found on the Qualcomm + Technologies Inc SM6350 platform. + +config PINCTRL_SM6375 + tristate "Qualcomm Technologies Inc SM6375 pin controller driver" + depends on ARM64 || COMPILE_TEST + help + This is the pinctrl, pinmux, pinconf and gpiolib driver for the + Qualcomm Technologies Inc TLMM block found on the Qualcomm + Technologies Inc SM6375 platform. + +config PINCTRL_SM7150 + tristate "Qualcomm Technologies Inc SM7150 pin controller driver" + depends on ARM64 || COMPILE_TEST + help + This is the pinctrl, pinmux, pinconf and gpiolib driver for the + Qualcomm Technologies Inc TLMM block found on the Qualcomm + Technologies Inc SM7150 platform. + +config PINCTRL_SM8150 + tristate "Qualcomm Technologies Inc SM8150 pin controller driver" + depends on ARM64 || COMPILE_TEST + help + This is the pinctrl, pinmux, pinconf and gpiolib driver for the + Qualcomm Technologies Inc TLMM block found on the Qualcomm + Technologies Inc SM8150 platform. + +config PINCTRL_SM8250 + tristate "Qualcomm Technologies Inc SM8250 pin controller driver" + depends on ARM64 || COMPILE_TEST + help + This is the pinctrl, pinmux, pinconf and gpiolib driver for the + Qualcomm Technologies Inc TLMM block found on the Qualcomm + Technologies Inc SM8250 platform. + +config PINCTRL_SM8350 + tristate "Qualcomm Technologies Inc SM8350 pin controller driver" + depends on ARM64 || COMPILE_TEST + help + This is the pinctrl, pinmux, pinconf and gpiolib driver for the + Qualcomm Technologies Inc TLMM block found on the Qualcomm + Technologies Inc SM8350 platform. + +config PINCTRL_SM8450 + tristate "Qualcomm Technologies Inc SM8450 pin controller driver" + depends on ARM64 || COMPILE_TEST + help + This is the pinctrl, pinmux, pinconf and gpiolib driver for the + Qualcomm Technologies Inc TLMM block found on the Qualcomm + Technologies Inc SM8450 platform. + +config PINCTRL_SM8550 + tristate "Qualcomm Technologies Inc SM8550 pin controller driver" + depends on ARM64 || COMPILE_TEST + help + This is the pinctrl, pinmux, pinconf and gpiolib driver for the + Qualcomm Technologies Inc TLMM block found on the Qualcomm + Technologies Inc SM8550 platform. + +endif diff --git a/drivers/pinctrl/qcom/Makefile b/drivers/pinctrl/qcom/Makefile new file mode 100644 index 0000000000..5910e08c84 --- /dev/null +++ b/drivers/pinctrl/qcom/Makefile @@ -0,0 +1,62 @@ +# SPDX-License-Identifier: GPL-2.0 +# Qualcomm pin control drivers +obj-$(CONFIG_PINCTRL_MSM) += pinctrl-msm.o +obj-$(CONFIG_PINCTRL_APQ8064) += pinctrl-apq8064.o +obj-$(CONFIG_PINCTRL_APQ8084) += pinctrl-apq8084.o +obj-$(CONFIG_PINCTRL_IPQ4019) += pinctrl-ipq4019.o +obj-$(CONFIG_PINCTRL_IPQ5018) += pinctrl-ipq5018.o +obj-$(CONFIG_PINCTRL_IPQ8064) += pinctrl-ipq8064.o +obj-$(CONFIG_PINCTRL_IPQ5332) += pinctrl-ipq5332.o +obj-$(CONFIG_PINCTRL_IPQ8074) += pinctrl-ipq8074.o +obj-$(CONFIG_PINCTRL_IPQ6018) += pinctrl-ipq6018.o +obj-$(CONFIG_PINCTRL_IPQ9574) += pinctrl-ipq9574.o +obj-$(CONFIG_PINCTRL_MSM8226) += pinctrl-msm8226.o +obj-$(CONFIG_PINCTRL_MSM8660) += pinctrl-msm8660.o +obj-$(CONFIG_PINCTRL_MSM8960) += pinctrl-msm8960.o +obj-$(CONFIG_PINCTRL_MSM8X74) += pinctrl-msm8x74.o +obj-$(CONFIG_PINCTRL_MSM8909) += pinctrl-msm8909.o +obj-$(CONFIG_PINCTRL_MSM8916) += pinctrl-msm8916.o +obj-$(CONFIG_PINCTRL_MSM8953) += pinctrl-msm8953.o +obj-$(CONFIG_PINCTRL_MSM8976) += pinctrl-msm8976.o +obj-$(CONFIG_PINCTRL_MSM8994) += pinctrl-msm8994.o +obj-$(CONFIG_PINCTRL_MSM8996) += pinctrl-msm8996.o +obj-$(CONFIG_PINCTRL_MSM8998) += pinctrl-msm8998.o +obj-$(CONFIG_PINCTRL_QCM2290) += pinctrl-qcm2290.o +obj-$(CONFIG_PINCTRL_QCS404) += pinctrl-qcs404.o +obj-$(CONFIG_PINCTRL_QDF2XXX) += pinctrl-qdf2xxx.o +obj-$(CONFIG_PINCTRL_MDM9607) += pinctrl-mdm9607.o +obj-$(CONFIG_PINCTRL_MDM9615) += pinctrl-mdm9615.o +obj-$(CONFIG_PINCTRL_QCOM_SPMI_PMIC) += pinctrl-spmi-gpio.o +obj-$(CONFIG_PINCTRL_QCOM_SPMI_PMIC) += pinctrl-spmi-mpp.o +obj-$(CONFIG_PINCTRL_QCOM_SSBI_PMIC) += pinctrl-ssbi-gpio.o +obj-$(CONFIG_PINCTRL_QCOM_SSBI_PMIC) += pinctrl-ssbi-mpp.o +obj-$(CONFIG_PINCTRL_QDU1000) += pinctrl-qdu1000.o +obj-$(CONFIG_PINCTRL_SA8775P) += pinctrl-sa8775p.o +obj-$(CONFIG_PINCTRL_SC7180) += pinctrl-sc7180.o +obj-$(CONFIG_PINCTRL_SC7280) += pinctrl-sc7280.o +obj-$(CONFIG_PINCTRL_SC7280_LPASS_LPI) += pinctrl-sc7280-lpass-lpi.o +obj-$(CONFIG_PINCTRL_SC8180X) += pinctrl-sc8180x.o +obj-$(CONFIG_PINCTRL_SC8280XP) += pinctrl-sc8280xp.o +obj-$(CONFIG_PINCTRL_SDM660) += pinctrl-sdm660.o +obj-$(CONFIG_PINCTRL_SDM670) += pinctrl-sdm670.o +obj-$(CONFIG_PINCTRL_SDM845) += pinctrl-sdm845.o +obj-$(CONFIG_PINCTRL_SDX55) += pinctrl-sdx55.o +obj-$(CONFIG_PINCTRL_SDX65) += pinctrl-sdx65.o +obj-$(CONFIG_PINCTRL_SDX75) += pinctrl-sdx75.o +obj-$(CONFIG_PINCTRL_SM6115) += pinctrl-sm6115.o +obj-$(CONFIG_PINCTRL_SM6115_LPASS_LPI) += pinctrl-sm6115-lpass-lpi.o +obj-$(CONFIG_PINCTRL_SM6125) += pinctrl-sm6125.o +obj-$(CONFIG_PINCTRL_SM6350) += pinctrl-sm6350.o +obj-$(CONFIG_PINCTRL_SM6375) += pinctrl-sm6375.o +obj-$(CONFIG_PINCTRL_SM7150) += pinctrl-sm7150.o +obj-$(CONFIG_PINCTRL_SM8150) += pinctrl-sm8150.o +obj-$(CONFIG_PINCTRL_SM8250) += pinctrl-sm8250.o +obj-$(CONFIG_PINCTRL_SM8250_LPASS_LPI) += pinctrl-sm8250-lpass-lpi.o +obj-$(CONFIG_PINCTRL_SM8350) += pinctrl-sm8350.o +obj-$(CONFIG_PINCTRL_SM8350_LPASS_LPI) += pinctrl-sm8350-lpass-lpi.o +obj-$(CONFIG_PINCTRL_SM8450) += pinctrl-sm8450.o +obj-$(CONFIG_PINCTRL_SM8450_LPASS_LPI) += pinctrl-sm8450-lpass-lpi.o +obj-$(CONFIG_PINCTRL_SM8550) += pinctrl-sm8550.o +obj-$(CONFIG_PINCTRL_SM8550_LPASS_LPI) += pinctrl-sm8550-lpass-lpi.o +obj-$(CONFIG_PINCTRL_SC8280XP_LPASS_LPI) += pinctrl-sc8280xp-lpass-lpi.o +obj-$(CONFIG_PINCTRL_LPASS_LPI) += pinctrl-lpass-lpi.o diff --git a/drivers/pinctrl/qcom/pinctrl-apq8064.c b/drivers/pinctrl/qcom/pinctrl-apq8064.c new file mode 100644 index 0000000000..20c3b90250 --- /dev/null +++ b/drivers/pinctrl/qcom/pinctrl-apq8064.c @@ -0,0 +1,650 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2014, Sony Mobile Communications AB. + */ + +#include <linux/module.h> +#include <linux/of.h> +#include <linux/platform_device.h> + +#include "pinctrl-msm.h" + +static const struct pinctrl_pin_desc apq8064_pins[] = { + PINCTRL_PIN(0, "GPIO_0"), + PINCTRL_PIN(1, "GPIO_1"), + PINCTRL_PIN(2, "GPIO_2"), + PINCTRL_PIN(3, "GPIO_3"), + PINCTRL_PIN(4, "GPIO_4"), + PINCTRL_PIN(5, "GPIO_5"), + PINCTRL_PIN(6, "GPIO_6"), + PINCTRL_PIN(7, "GPIO_7"), + PINCTRL_PIN(8, "GPIO_8"), + PINCTRL_PIN(9, "GPIO_9"), + PINCTRL_PIN(10, "GPIO_10"), + PINCTRL_PIN(11, "GPIO_11"), + PINCTRL_PIN(12, "GPIO_12"), + PINCTRL_PIN(13, "GPIO_13"), + PINCTRL_PIN(14, "GPIO_14"), + PINCTRL_PIN(15, "GPIO_15"), + PINCTRL_PIN(16, "GPIO_16"), + PINCTRL_PIN(17, "GPIO_17"), + PINCTRL_PIN(18, "GPIO_18"), + PINCTRL_PIN(19, "GPIO_19"), + PINCTRL_PIN(20, "GPIO_20"), + PINCTRL_PIN(21, "GPIO_21"), + PINCTRL_PIN(22, "GPIO_22"), + PINCTRL_PIN(23, "GPIO_23"), + PINCTRL_PIN(24, "GPIO_24"), + PINCTRL_PIN(25, "GPIO_25"), + PINCTRL_PIN(26, "GPIO_26"), + PINCTRL_PIN(27, "GPIO_27"), + PINCTRL_PIN(28, "GPIO_28"), + PINCTRL_PIN(29, "GPIO_29"), + PINCTRL_PIN(30, "GPIO_30"), + PINCTRL_PIN(31, "GPIO_31"), + PINCTRL_PIN(32, "GPIO_32"), + PINCTRL_PIN(33, "GPIO_33"), + PINCTRL_PIN(34, "GPIO_34"), + PINCTRL_PIN(35, "GPIO_35"), + PINCTRL_PIN(36, "GPIO_36"), + PINCTRL_PIN(37, "GPIO_37"), + PINCTRL_PIN(38, "GPIO_38"), + PINCTRL_PIN(39, "GPIO_39"), + PINCTRL_PIN(40, "GPIO_40"), + PINCTRL_PIN(41, "GPIO_41"), + PINCTRL_PIN(42, "GPIO_42"), + PINCTRL_PIN(43, "GPIO_43"), + PINCTRL_PIN(44, "GPIO_44"), + PINCTRL_PIN(45, "GPIO_45"), + PINCTRL_PIN(46, "GPIO_46"), + PINCTRL_PIN(47, "GPIO_47"), + PINCTRL_PIN(48, "GPIO_48"), + PINCTRL_PIN(49, "GPIO_49"), + PINCTRL_PIN(50, "GPIO_50"), + PINCTRL_PIN(51, "GPIO_51"), + PINCTRL_PIN(52, "GPIO_52"), + PINCTRL_PIN(53, "GPIO_53"), + PINCTRL_PIN(54, "GPIO_54"), + PINCTRL_PIN(55, "GPIO_55"), + PINCTRL_PIN(56, "GPIO_56"), + PINCTRL_PIN(57, "GPIO_57"), + PINCTRL_PIN(58, "GPIO_58"), + PINCTRL_PIN(59, "GPIO_59"), + PINCTRL_PIN(60, "GPIO_60"), + PINCTRL_PIN(61, "GPIO_61"), + PINCTRL_PIN(62, "GPIO_62"), + PINCTRL_PIN(63, "GPIO_63"), + PINCTRL_PIN(64, "GPIO_64"), + PINCTRL_PIN(65, "GPIO_65"), + PINCTRL_PIN(66, "GPIO_66"), + PINCTRL_PIN(67, "GPIO_67"), + PINCTRL_PIN(68, "GPIO_68"), + PINCTRL_PIN(69, "GPIO_69"), + PINCTRL_PIN(70, "GPIO_70"), + PINCTRL_PIN(71, "GPIO_71"), + PINCTRL_PIN(72, "GPIO_72"), + PINCTRL_PIN(73, "GPIO_73"), + PINCTRL_PIN(74, "GPIO_74"), + PINCTRL_PIN(75, "GPIO_75"), + PINCTRL_PIN(76, "GPIO_76"), + PINCTRL_PIN(77, "GPIO_77"), + PINCTRL_PIN(78, "GPIO_78"), + PINCTRL_PIN(79, "GPIO_79"), + PINCTRL_PIN(80, "GPIO_80"), + PINCTRL_PIN(81, "GPIO_81"), + PINCTRL_PIN(82, "GPIO_82"), + PINCTRL_PIN(83, "GPIO_83"), + PINCTRL_PIN(84, "GPIO_84"), + PINCTRL_PIN(85, "GPIO_85"), + PINCTRL_PIN(86, "GPIO_86"), + PINCTRL_PIN(87, "GPIO_87"), + PINCTRL_PIN(88, "GPIO_88"), + PINCTRL_PIN(89, "GPIO_89"), + + PINCTRL_PIN(90, "SDC1_CLK"), + PINCTRL_PIN(91, "SDC1_CMD"), + PINCTRL_PIN(92, "SDC1_DATA"), + PINCTRL_PIN(93, "SDC3_CLK"), + PINCTRL_PIN(94, "SDC3_CMD"), + PINCTRL_PIN(95, "SDC3_DATA"), +}; + +#define DECLARE_APQ_GPIO_PINS(pin) static const unsigned int gpio##pin##_pins[] = { pin } +DECLARE_APQ_GPIO_PINS(0); +DECLARE_APQ_GPIO_PINS(1); +DECLARE_APQ_GPIO_PINS(2); +DECLARE_APQ_GPIO_PINS(3); +DECLARE_APQ_GPIO_PINS(4); +DECLARE_APQ_GPIO_PINS(5); +DECLARE_APQ_GPIO_PINS(6); +DECLARE_APQ_GPIO_PINS(7); +DECLARE_APQ_GPIO_PINS(8); +DECLARE_APQ_GPIO_PINS(9); +DECLARE_APQ_GPIO_PINS(10); +DECLARE_APQ_GPIO_PINS(11); +DECLARE_APQ_GPIO_PINS(12); +DECLARE_APQ_GPIO_PINS(13); +DECLARE_APQ_GPIO_PINS(14); +DECLARE_APQ_GPIO_PINS(15); +DECLARE_APQ_GPIO_PINS(16); +DECLARE_APQ_GPIO_PINS(17); +DECLARE_APQ_GPIO_PINS(18); +DECLARE_APQ_GPIO_PINS(19); +DECLARE_APQ_GPIO_PINS(20); +DECLARE_APQ_GPIO_PINS(21); +DECLARE_APQ_GPIO_PINS(22); +DECLARE_APQ_GPIO_PINS(23); +DECLARE_APQ_GPIO_PINS(24); +DECLARE_APQ_GPIO_PINS(25); +DECLARE_APQ_GPIO_PINS(26); +DECLARE_APQ_GPIO_PINS(27); +DECLARE_APQ_GPIO_PINS(28); +DECLARE_APQ_GPIO_PINS(29); +DECLARE_APQ_GPIO_PINS(30); +DECLARE_APQ_GPIO_PINS(31); +DECLARE_APQ_GPIO_PINS(32); +DECLARE_APQ_GPIO_PINS(33); +DECLARE_APQ_GPIO_PINS(34); +DECLARE_APQ_GPIO_PINS(35); +DECLARE_APQ_GPIO_PINS(36); +DECLARE_APQ_GPIO_PINS(37); +DECLARE_APQ_GPIO_PINS(38); +DECLARE_APQ_GPIO_PINS(39); +DECLARE_APQ_GPIO_PINS(40); +DECLARE_APQ_GPIO_PINS(41); +DECLARE_APQ_GPIO_PINS(42); +DECLARE_APQ_GPIO_PINS(43); +DECLARE_APQ_GPIO_PINS(44); +DECLARE_APQ_GPIO_PINS(45); +DECLARE_APQ_GPIO_PINS(46); +DECLARE_APQ_GPIO_PINS(47); +DECLARE_APQ_GPIO_PINS(48); +DECLARE_APQ_GPIO_PINS(49); +DECLARE_APQ_GPIO_PINS(50); +DECLARE_APQ_GPIO_PINS(51); +DECLARE_APQ_GPIO_PINS(52); +DECLARE_APQ_GPIO_PINS(53); +DECLARE_APQ_GPIO_PINS(54); +DECLARE_APQ_GPIO_PINS(55); +DECLARE_APQ_GPIO_PINS(56); +DECLARE_APQ_GPIO_PINS(57); +DECLARE_APQ_GPIO_PINS(58); +DECLARE_APQ_GPIO_PINS(59); +DECLARE_APQ_GPIO_PINS(60); +DECLARE_APQ_GPIO_PINS(61); +DECLARE_APQ_GPIO_PINS(62); +DECLARE_APQ_GPIO_PINS(63); +DECLARE_APQ_GPIO_PINS(64); +DECLARE_APQ_GPIO_PINS(65); +DECLARE_APQ_GPIO_PINS(66); +DECLARE_APQ_GPIO_PINS(67); +DECLARE_APQ_GPIO_PINS(68); +DECLARE_APQ_GPIO_PINS(69); +DECLARE_APQ_GPIO_PINS(70); +DECLARE_APQ_GPIO_PINS(71); +DECLARE_APQ_GPIO_PINS(72); +DECLARE_APQ_GPIO_PINS(73); +DECLARE_APQ_GPIO_PINS(74); +DECLARE_APQ_GPIO_PINS(75); +DECLARE_APQ_GPIO_PINS(76); +DECLARE_APQ_GPIO_PINS(77); +DECLARE_APQ_GPIO_PINS(78); +DECLARE_APQ_GPIO_PINS(79); +DECLARE_APQ_GPIO_PINS(80); +DECLARE_APQ_GPIO_PINS(81); +DECLARE_APQ_GPIO_PINS(82); +DECLARE_APQ_GPIO_PINS(83); +DECLARE_APQ_GPIO_PINS(84); +DECLARE_APQ_GPIO_PINS(85); +DECLARE_APQ_GPIO_PINS(86); +DECLARE_APQ_GPIO_PINS(87); +DECLARE_APQ_GPIO_PINS(88); +DECLARE_APQ_GPIO_PINS(89); + +static const unsigned int sdc1_clk_pins[] = { 90 }; +static const unsigned int sdc1_cmd_pins[] = { 91 }; +static const unsigned int sdc1_data_pins[] = { 92 }; +static const unsigned int sdc3_clk_pins[] = { 93 }; +static const unsigned int sdc3_cmd_pins[] = { 94 }; +static const unsigned int sdc3_data_pins[] = { 95 }; + +#define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7, f8, f9, f10) \ + { \ + .grp = PINCTRL_PINGROUP("gpio" #id, \ + gpio##id##_pins, \ + ARRAY_SIZE(gpio##id##_pins)), \ + .funcs = (int[]){ \ + APQ_MUX_gpio, \ + APQ_MUX_##f1, \ + APQ_MUX_##f2, \ + APQ_MUX_##f3, \ + APQ_MUX_##f4, \ + APQ_MUX_##f5, \ + APQ_MUX_##f6, \ + APQ_MUX_##f7, \ + APQ_MUX_##f8, \ + APQ_MUX_##f9, \ + APQ_MUX_##f10, \ + }, \ + .nfuncs = 11, \ + .ctl_reg = 0x1000 + 0x10 * id, \ + .io_reg = 0x1004 + 0x10 * id, \ + .intr_cfg_reg = 0x1008 + 0x10 * id, \ + .intr_status_reg = 0x100c + 0x10 * id, \ + .intr_target_reg = 0x400 + 0x4 * id, \ + .mux_bit = 2, \ + .pull_bit = 0, \ + .drv_bit = 6, \ + .oe_bit = 9, \ + .in_bit = 0, \ + .out_bit = 1, \ + .intr_enable_bit = 0, \ + .intr_status_bit = 0, \ + .intr_ack_high = 1, \ + .intr_target_bit = 0, \ + .intr_target_kpss_val = 4, \ + .intr_raw_status_bit = 3, \ + .intr_polarity_bit = 1, \ + .intr_detection_bit = 2, \ + .intr_detection_width = 1, \ + } + +#define SDC_PINGROUP(pg_name, ctl, pull, drv) \ + { \ + .grp = PINCTRL_PINGROUP(#pg_name, \ + pg_name##_pins, \ + ARRAY_SIZE(pg_name##_pins)), \ + .ctl_reg = ctl, \ + .io_reg = 0, \ + .intr_cfg_reg = 0, \ + .intr_status_reg = 0, \ + .intr_target_reg = 0, \ + .mux_bit = -1, \ + .pull_bit = pull, \ + .drv_bit = drv, \ + .oe_bit = -1, \ + .in_bit = -1, \ + .out_bit = -1, \ + .intr_enable_bit = -1, \ + .intr_status_bit = -1, \ + .intr_target_bit = -1, \ + .intr_target_kpss_val = -1, \ + .intr_raw_status_bit = -1, \ + .intr_polarity_bit = -1, \ + .intr_detection_bit = -1, \ + .intr_detection_width = -1, \ + } + +enum apq8064_functions { + APQ_MUX_cam_mclk, + APQ_MUX_codec_mic_i2s, + APQ_MUX_codec_spkr_i2s, + APQ_MUX_gp_clk_0a, + APQ_MUX_gp_clk_0b, + APQ_MUX_gp_clk_1a, + APQ_MUX_gp_clk_1b, + APQ_MUX_gp_clk_2a, + APQ_MUX_gp_clk_2b, + APQ_MUX_gpio, + APQ_MUX_gsbi1, + APQ_MUX_gsbi2, + APQ_MUX_gsbi3, + APQ_MUX_gsbi4, + APQ_MUX_gsbi4_cam_i2c, + APQ_MUX_gsbi5, + APQ_MUX_gsbi5_spi_cs1, + APQ_MUX_gsbi5_spi_cs2, + APQ_MUX_gsbi5_spi_cs3, + APQ_MUX_gsbi6, + APQ_MUX_gsbi6_spi_cs1, + APQ_MUX_gsbi6_spi_cs2, + APQ_MUX_gsbi6_spi_cs3, + APQ_MUX_gsbi7, + APQ_MUX_gsbi7_spi_cs1, + APQ_MUX_gsbi7_spi_cs2, + APQ_MUX_gsbi7_spi_cs3, + APQ_MUX_gsbi_cam_i2c, + APQ_MUX_hdmi, + APQ_MUX_mi2s, + APQ_MUX_riva_bt, + APQ_MUX_riva_fm, + APQ_MUX_riva_wlan, + APQ_MUX_sdc2, + APQ_MUX_sdc4, + APQ_MUX_slimbus, + APQ_MUX_spkr_i2s, + APQ_MUX_tsif1, + APQ_MUX_tsif2, + APQ_MUX_usb2_hsic, + APQ_MUX_ps_hold, + APQ_MUX_NA, +}; + +static const char * const cam_mclk_groups[] = { + "gpio4" "gpio5" +}; +static const char * const codec_mic_i2s_groups[] = { + "gpio34", "gpio35", "gpio36", "gpio37", "gpio38" +}; +static const char * const codec_spkr_i2s_groups[] = { + "gpio39", "gpio40", "gpio41", "gpio42" +}; +static const char * const gpio_groups[] = { + "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7", + "gpio8", "gpio9", "gpio10", "gpio11", "gpio12", "gpio13", "gpio14", + "gpio15", "gpio16", "gpio17", "gpio18", "gpio19", "gpio20", "gpio21", + "gpio22", "gpio23", "gpio24", "gpio25", "gpio26", "gpio27", "gpio28", + "gpio29", "gpio30", "gpio31", "gpio32", "gpio33", "gpio34", "gpio35", + "gpio36", "gpio37", "gpio38", "gpio39", "gpio40", "gpio41", "gpio42", + "gpio43", "gpio44", "gpio45", "gpio46", "gpio47", "gpio48", "gpio49", + "gpio50", "gpio51", "gpio52", "gpio53", "gpio54", "gpio55", "gpio56", + "gpio57", "gpio58", "gpio59", "gpio60", "gpio61", "gpio62", "gpio63", + "gpio64", "gpio65", "gpio66", "gpio67", "gpio68", "gpio69", "gpio70", + "gpio71", "gpio72", "gpio73", "gpio74", "gpio75", "gpio76", "gpio77", + "gpio78", "gpio79", "gpio80", "gpio81", "gpio82", "gpio83", "gpio84", + "gpio85", "gpio86", "gpio87", "gpio88", "gpio89" +}; +static const char * const gp_clk_0a_groups[] = { + "gpio3" +}; +static const char * const gp_clk_0b_groups[] = { + "gpio34" +}; +static const char * const gp_clk_1a_groups[] = { + "gpio4" +}; +static const char * const gp_clk_1b_groups[] = { + "gpio50" +}; +static const char * const gp_clk_2a_groups[] = { + "gpio32" +}; +static const char * const gp_clk_2b_groups[] = { + "gpio25" +}; +static const char * const ps_hold_groups[] = { + "gpio78" +}; +static const char * const gsbi1_groups[] = { + "gpio18", "gpio19", "gpio20", "gpio21" +}; +static const char * const gsbi2_groups[] = { + "gpio22", "gpio23", "gpio24", "gpio25" +}; +static const char * const gsbi3_groups[] = { + "gpio6", "gpio7", "gpio8", "gpio9" +}; +static const char * const gsbi4_groups[] = { + "gpio10", "gpio11", "gpio12", "gpio13" +}; +static const char * const gsbi4_cam_i2c_groups[] = { + "gpio10", "gpio11", "gpio12", "gpio13" +}; +static const char * const gsbi5_groups[] = { + "gpio51", "gpio52", "gpio53", "gpio54" +}; +static const char * const gsbi5_spi_cs1_groups[] = { + "gpio47" +}; +static const char * const gsbi5_spi_cs2_groups[] = { + "gpio31" +}; +static const char * const gsbi5_spi_cs3_groups[] = { + "gpio32" +}; +static const char * const gsbi6_groups[] = { + "gpio14", "gpio15", "gpio16", "gpio17" +}; +static const char * const gsbi6_spi_cs1_groups[] = { + "gpio47" +}; +static const char * const gsbi6_spi_cs2_groups[] = { + "gpio31" +}; +static const char * const gsbi6_spi_cs3_groups[] = { + "gpio32" +}; +static const char * const gsbi7_groups[] = { + "gpio82", "gpio83", "gpio84", "gpio85" +}; +static const char * const gsbi7_spi_cs1_groups[] = { + "gpio47" +}; +static const char * const gsbi7_spi_cs2_groups[] = { + "gpio31" +}; +static const char * const gsbi7_spi_cs3_groups[] = { + "gpio32" +}; +static const char * const gsbi_cam_i2c_groups[] = { + "gpio10", "gpio11", "gpio12", "gpio13" +}; +static const char * const hdmi_groups[] = { + "gpio69", "gpio70", "gpio71", "gpio72" +}; +static const char * const mi2s_groups[] = { + "gpio27", "gpio28", "gpio29", "gpio30", "gpio31", "gpio32", "gpio33" +}; +static const char * const riva_bt_groups[] = { + "gpio16", "gpio17" +}; +static const char * const riva_fm_groups[] = { + "gpio14", "gpio15" +}; +static const char * const riva_wlan_groups[] = { + "gpio64", "gpio65", "gpio66", "gpio67", "gpio68" +}; +static const char * const sdc2_groups[] = { + "gpio57", "gpio58", "gpio59", "gpio60", "gpio61", "gpio62" +}; +static const char * const sdc4_groups[] = { + "gpio63", "gpio64", "gpio65", "gpio66", "gpio67", "gpio68" +}; +static const char * const slimbus_groups[] = { + "gpio40", "gpio41" +}; +static const char * const spkr_i2s_groups[] = { + "gpio47", "gpio48", "gpio49", "gpio50" +}; +static const char * const tsif1_groups[] = { + "gpio55", "gpio56", "gpio57" +}; +static const char * const tsif2_groups[] = { + "gpio58", "gpio59", "gpio60" +}; +static const char * const usb2_hsic_groups[] = { + "gpio88", "gpio89" +}; + +static const struct pinfunction apq8064_functions[] = { + APQ_PIN_FUNCTION(cam_mclk), + APQ_PIN_FUNCTION(codec_mic_i2s), + APQ_PIN_FUNCTION(codec_spkr_i2s), + APQ_PIN_FUNCTION(gp_clk_0a), + APQ_PIN_FUNCTION(gp_clk_0b), + APQ_PIN_FUNCTION(gp_clk_1a), + APQ_PIN_FUNCTION(gp_clk_1b), + APQ_PIN_FUNCTION(gp_clk_2a), + APQ_PIN_FUNCTION(gp_clk_2b), + APQ_PIN_FUNCTION(gpio), + APQ_PIN_FUNCTION(gsbi1), + APQ_PIN_FUNCTION(gsbi2), + APQ_PIN_FUNCTION(gsbi3), + APQ_PIN_FUNCTION(gsbi4), + APQ_PIN_FUNCTION(gsbi4_cam_i2c), + APQ_PIN_FUNCTION(gsbi5), + APQ_PIN_FUNCTION(gsbi5_spi_cs1), + APQ_PIN_FUNCTION(gsbi5_spi_cs2), + APQ_PIN_FUNCTION(gsbi5_spi_cs3), + APQ_PIN_FUNCTION(gsbi6), + APQ_PIN_FUNCTION(gsbi6_spi_cs1), + APQ_PIN_FUNCTION(gsbi6_spi_cs2), + APQ_PIN_FUNCTION(gsbi6_spi_cs3), + APQ_PIN_FUNCTION(gsbi7), + APQ_PIN_FUNCTION(gsbi7_spi_cs1), + APQ_PIN_FUNCTION(gsbi7_spi_cs2), + APQ_PIN_FUNCTION(gsbi7_spi_cs3), + APQ_PIN_FUNCTION(gsbi_cam_i2c), + APQ_PIN_FUNCTION(hdmi), + APQ_PIN_FUNCTION(mi2s), + APQ_PIN_FUNCTION(riva_bt), + APQ_PIN_FUNCTION(riva_fm), + APQ_PIN_FUNCTION(riva_wlan), + APQ_PIN_FUNCTION(sdc2), + APQ_PIN_FUNCTION(sdc4), + APQ_PIN_FUNCTION(slimbus), + APQ_PIN_FUNCTION(spkr_i2s), + APQ_PIN_FUNCTION(tsif1), + APQ_PIN_FUNCTION(tsif2), + APQ_PIN_FUNCTION(usb2_hsic), + APQ_PIN_FUNCTION(ps_hold), +}; + +static const struct msm_pingroup apq8064_groups[] = { + PINGROUP(0, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(1, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(2, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(3, NA, gp_clk_0a, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(4, NA, NA, cam_mclk, gp_clk_1a, NA, NA, NA, NA, NA, NA), + PINGROUP(5, NA, cam_mclk, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(6, gsbi3, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(7, gsbi3, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(8, gsbi3, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(9, gsbi3, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(10, gsbi4, NA, NA, NA, NA, NA, NA, NA, gsbi4_cam_i2c, NA), + PINGROUP(11, gsbi4, NA, NA, NA, NA, NA, NA, NA, NA, gsbi4_cam_i2c), + PINGROUP(12, gsbi4, NA, NA, NA, NA, gsbi4_cam_i2c, NA, NA, NA, NA), + PINGROUP(13, gsbi4, NA, NA, NA, NA, gsbi4_cam_i2c, NA, NA, NA, NA), + PINGROUP(14, riva_fm, gsbi6, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(15, riva_fm, gsbi6, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(16, riva_bt, gsbi6, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(17, riva_bt, gsbi6, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(18, gsbi1, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(19, gsbi1, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(20, gsbi1, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(21, gsbi1, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(22, gsbi2, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(23, gsbi2, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(24, gsbi2, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(25, gsbi2, gp_clk_2b, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(26, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(27, mi2s, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(28, mi2s, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(29, mi2s, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(30, mi2s, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(31, mi2s, NA, gsbi5_spi_cs2, gsbi6_spi_cs2, gsbi7_spi_cs2, NA, NA, NA, NA, NA), + PINGROUP(32, mi2s, gp_clk_2a, NA, NA, NA, gsbi5_spi_cs3, gsbi6_spi_cs3, gsbi7_spi_cs3, NA, NA), + PINGROUP(33, mi2s, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(34, codec_mic_i2s, gp_clk_0b, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(35, codec_mic_i2s, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(36, codec_mic_i2s, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(37, codec_mic_i2s, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(38, codec_mic_i2s, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(39, codec_spkr_i2s, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(40, slimbus, codec_spkr_i2s, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(41, slimbus, codec_spkr_i2s, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(42, codec_spkr_i2s, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(43, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(44, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(45, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(46, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(47, spkr_i2s, gsbi5_spi_cs1, gsbi6_spi_cs1, gsbi7_spi_cs1, NA, NA, NA, NA, NA, NA), + PINGROUP(48, spkr_i2s, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(49, spkr_i2s, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(50, spkr_i2s, gp_clk_1b, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(51, NA, gsbi5, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(52, NA, gsbi5, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(53, NA, gsbi5, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(54, NA, gsbi5, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(55, tsif1, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(56, tsif1, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(57, tsif1, sdc2, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(58, tsif2, sdc2, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(59, tsif2, sdc2, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(60, tsif2, sdc2, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(61, NA, sdc2, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(62, NA, sdc2, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(63, NA, sdc4, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(64, riva_wlan, sdc4, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(65, riva_wlan, sdc4, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(66, riva_wlan, sdc4, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(67, riva_wlan, sdc4, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(68, riva_wlan, sdc4, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(69, hdmi, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(70, hdmi, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(71, hdmi, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(72, hdmi, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(73, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(74, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(75, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(76, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(77, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(78, ps_hold, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(79, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(80, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(81, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(82, NA, gsbi7, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(83, gsbi7, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(84, NA, gsbi7, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(85, NA, NA, gsbi7, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(86, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(87, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(88, usb2_hsic, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(89, usb2_hsic, NA, NA, NA, NA, NA, NA, NA, NA, NA), + + SDC_PINGROUP(sdc1_clk, 0x20a0, 13, 6), + SDC_PINGROUP(sdc1_cmd, 0x20a0, 11, 3), + SDC_PINGROUP(sdc1_data, 0x20a0, 9, 0), + + SDC_PINGROUP(sdc3_clk, 0x20a4, 14, 6), + SDC_PINGROUP(sdc3_cmd, 0x20a4, 11, 3), + SDC_PINGROUP(sdc3_data, 0x20a4, 9, 0), +}; + +#define NUM_GPIO_PINGROUPS 90 + +static const struct msm_pinctrl_soc_data apq8064_pinctrl = { + .pins = apq8064_pins, + .npins = ARRAY_SIZE(apq8064_pins), + .functions = apq8064_functions, + .nfunctions = ARRAY_SIZE(apq8064_functions), + .groups = apq8064_groups, + .ngroups = ARRAY_SIZE(apq8064_groups), + .ngpios = NUM_GPIO_PINGROUPS, +}; + +static int apq8064_pinctrl_probe(struct platform_device *pdev) +{ + return msm_pinctrl_probe(pdev, &apq8064_pinctrl); +} + +static const struct of_device_id apq8064_pinctrl_of_match[] = { + { .compatible = "qcom,apq8064-pinctrl", }, + { }, +}; + +static struct platform_driver apq8064_pinctrl_driver = { + .driver = { + .name = "apq8064-pinctrl", + .of_match_table = apq8064_pinctrl_of_match, + }, + .probe = apq8064_pinctrl_probe, + .remove = msm_pinctrl_remove, +}; + +static int __init apq8064_pinctrl_init(void) +{ + return platform_driver_register(&apq8064_pinctrl_driver); +} +arch_initcall(apq8064_pinctrl_init); + +static void __exit apq8064_pinctrl_exit(void) +{ + platform_driver_unregister(&apq8064_pinctrl_driver); +} +module_exit(apq8064_pinctrl_exit); + +MODULE_AUTHOR("Bjorn Andersson <bjorn.andersson@sonymobile.com>"); +MODULE_DESCRIPTION("Qualcomm APQ8064 pinctrl driver"); +MODULE_LICENSE("GPL v2"); +MODULE_DEVICE_TABLE(of, apq8064_pinctrl_of_match); diff --git a/drivers/pinctrl/qcom/pinctrl-apq8084.c b/drivers/pinctrl/qcom/pinctrl-apq8084.c new file mode 100644 index 0000000000..3fc0a40762 --- /dev/null +++ b/drivers/pinctrl/qcom/pinctrl-apq8084.c @@ -0,0 +1,1227 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2014, The Linux Foundation. All rights reserved. + */ + +#include <linux/module.h> +#include <linux/of.h> +#include <linux/platform_device.h> + +#include "pinctrl-msm.h" + +static const struct pinctrl_pin_desc apq8084_pins[] = { + PINCTRL_PIN(0, "GPIO_0"), + PINCTRL_PIN(1, "GPIO_1"), + PINCTRL_PIN(2, "GPIO_2"), + PINCTRL_PIN(3, "GPIO_3"), + PINCTRL_PIN(4, "GPIO_4"), + PINCTRL_PIN(5, "GPIO_5"), + PINCTRL_PIN(6, "GPIO_6"), + PINCTRL_PIN(7, "GPIO_7"), + PINCTRL_PIN(8, "GPIO_8"), + PINCTRL_PIN(9, "GPIO_9"), + PINCTRL_PIN(10, "GPIO_10"), + PINCTRL_PIN(11, "GPIO_11"), + PINCTRL_PIN(12, "GPIO_12"), + PINCTRL_PIN(13, "GPIO_13"), + PINCTRL_PIN(14, "GPIO_14"), + PINCTRL_PIN(15, "GPIO_15"), + PINCTRL_PIN(16, "GPIO_16"), + PINCTRL_PIN(17, "GPIO_17"), + PINCTRL_PIN(18, "GPIO_18"), + PINCTRL_PIN(19, "GPIO_19"), + PINCTRL_PIN(20, "GPIO_20"), + PINCTRL_PIN(21, "GPIO_21"), + PINCTRL_PIN(22, "GPIO_22"), + PINCTRL_PIN(23, "GPIO_23"), + PINCTRL_PIN(24, "GPIO_24"), + PINCTRL_PIN(25, "GPIO_25"), + PINCTRL_PIN(26, "GPIO_26"), + PINCTRL_PIN(27, "GPIO_27"), + PINCTRL_PIN(28, "GPIO_28"), + PINCTRL_PIN(29, "GPIO_29"), + PINCTRL_PIN(30, "GPIO_30"), + PINCTRL_PIN(31, "GPIO_31"), + PINCTRL_PIN(32, "GPIO_32"), + PINCTRL_PIN(33, "GPIO_33"), + PINCTRL_PIN(34, "GPIO_34"), + PINCTRL_PIN(35, "GPIO_35"), + PINCTRL_PIN(36, "GPIO_36"), + PINCTRL_PIN(37, "GPIO_37"), + PINCTRL_PIN(38, "GPIO_38"), + PINCTRL_PIN(39, "GPIO_39"), + PINCTRL_PIN(40, "GPIO_40"), + PINCTRL_PIN(41, "GPIO_41"), + PINCTRL_PIN(42, "GPIO_42"), + PINCTRL_PIN(43, "GPIO_43"), + PINCTRL_PIN(44, "GPIO_44"), + PINCTRL_PIN(45, "GPIO_45"), + PINCTRL_PIN(46, "GPIO_46"), + PINCTRL_PIN(47, "GPIO_47"), + PINCTRL_PIN(48, "GPIO_48"), + PINCTRL_PIN(49, "GPIO_49"), + PINCTRL_PIN(50, "GPIO_50"), + PINCTRL_PIN(51, "GPIO_51"), + PINCTRL_PIN(52, "GPIO_52"), + PINCTRL_PIN(53, "GPIO_53"), + PINCTRL_PIN(54, "GPIO_54"), + PINCTRL_PIN(55, "GPIO_55"), + PINCTRL_PIN(56, "GPIO_56"), + PINCTRL_PIN(57, "GPIO_57"), + PINCTRL_PIN(58, "GPIO_58"), + PINCTRL_PIN(59, "GPIO_59"), + PINCTRL_PIN(60, "GPIO_60"), + PINCTRL_PIN(61, "GPIO_61"), + PINCTRL_PIN(62, "GPIO_62"), + PINCTRL_PIN(63, "GPIO_63"), + PINCTRL_PIN(64, "GPIO_64"), + PINCTRL_PIN(65, "GPIO_65"), + PINCTRL_PIN(66, "GPIO_66"), + PINCTRL_PIN(67, "GPIO_67"), + PINCTRL_PIN(68, "GPIO_68"), + PINCTRL_PIN(69, "GPIO_69"), + PINCTRL_PIN(70, "GPIO_70"), + PINCTRL_PIN(71, "GPIO_71"), + PINCTRL_PIN(72, "GPIO_72"), + PINCTRL_PIN(73, "GPIO_73"), + PINCTRL_PIN(74, "GPIO_74"), + PINCTRL_PIN(75, "GPIO_75"), + PINCTRL_PIN(76, "GPIO_76"), + PINCTRL_PIN(77, "GPIO_77"), + PINCTRL_PIN(78, "GPIO_78"), + PINCTRL_PIN(79, "GPIO_79"), + PINCTRL_PIN(80, "GPIO_80"), + PINCTRL_PIN(81, "GPIO_81"), + PINCTRL_PIN(82, "GPIO_82"), + PINCTRL_PIN(83, "GPIO_83"), + PINCTRL_PIN(84, "GPIO_84"), + PINCTRL_PIN(85, "GPIO_85"), + PINCTRL_PIN(86, "GPIO_86"), + PINCTRL_PIN(87, "GPIO_87"), + PINCTRL_PIN(88, "GPIO_88"), + PINCTRL_PIN(89, "GPIO_89"), + PINCTRL_PIN(90, "GPIO_90"), + PINCTRL_PIN(91, "GPIO_91"), + PINCTRL_PIN(92, "GPIO_92"), + PINCTRL_PIN(93, "GPIO_93"), + PINCTRL_PIN(94, "GPIO_94"), + PINCTRL_PIN(95, "GPIO_95"), + PINCTRL_PIN(96, "GPIO_96"), + PINCTRL_PIN(97, "GPIO_97"), + PINCTRL_PIN(98, "GPIO_98"), + PINCTRL_PIN(99, "GPIO_99"), + PINCTRL_PIN(100, "GPIO_100"), + PINCTRL_PIN(101, "GPIO_101"), + PINCTRL_PIN(102, "GPIO_102"), + PINCTRL_PIN(103, "GPIO_103"), + PINCTRL_PIN(104, "GPIO_104"), + PINCTRL_PIN(105, "GPIO_105"), + PINCTRL_PIN(106, "GPIO_106"), + PINCTRL_PIN(107, "GPIO_107"), + PINCTRL_PIN(108, "GPIO_108"), + PINCTRL_PIN(109, "GPIO_109"), + PINCTRL_PIN(110, "GPIO_110"), + PINCTRL_PIN(111, "GPIO_111"), + PINCTRL_PIN(112, "GPIO_112"), + PINCTRL_PIN(113, "GPIO_113"), + PINCTRL_PIN(114, "GPIO_114"), + PINCTRL_PIN(115, "GPIO_115"), + PINCTRL_PIN(116, "GPIO_116"), + PINCTRL_PIN(117, "GPIO_117"), + PINCTRL_PIN(118, "GPIO_118"), + PINCTRL_PIN(119, "GPIO_119"), + PINCTRL_PIN(120, "GPIO_120"), + PINCTRL_PIN(121, "GPIO_121"), + PINCTRL_PIN(122, "GPIO_122"), + PINCTRL_PIN(123, "GPIO_123"), + PINCTRL_PIN(124, "GPIO_124"), + PINCTRL_PIN(125, "GPIO_125"), + PINCTRL_PIN(126, "GPIO_126"), + PINCTRL_PIN(127, "GPIO_127"), + PINCTRL_PIN(128, "GPIO_128"), + PINCTRL_PIN(129, "GPIO_129"), + PINCTRL_PIN(130, "GPIO_130"), + PINCTRL_PIN(131, "GPIO_131"), + PINCTRL_PIN(132, "GPIO_132"), + PINCTRL_PIN(133, "GPIO_133"), + PINCTRL_PIN(134, "GPIO_134"), + PINCTRL_PIN(135, "GPIO_135"), + PINCTRL_PIN(136, "GPIO_136"), + PINCTRL_PIN(137, "GPIO_137"), + PINCTRL_PIN(138, "GPIO_138"), + PINCTRL_PIN(139, "GPIO_139"), + PINCTRL_PIN(140, "GPIO_140"), + PINCTRL_PIN(141, "GPIO_141"), + PINCTRL_PIN(142, "GPIO_142"), + PINCTRL_PIN(143, "GPIO_143"), + PINCTRL_PIN(144, "GPIO_144"), + PINCTRL_PIN(145, "GPIO_145"), + PINCTRL_PIN(146, "GPIO_146"), + + PINCTRL_PIN(147, "SDC1_CLK"), + PINCTRL_PIN(148, "SDC1_CMD"), + PINCTRL_PIN(149, "SDC1_DATA"), + PINCTRL_PIN(150, "SDC2_CLK"), + PINCTRL_PIN(151, "SDC2_CMD"), + PINCTRL_PIN(152, "SDC2_DATA"), +}; + +#define DECLARE_APQ_GPIO_PINS(pin) static const unsigned int gpio##pin##_pins[] = { pin } + +DECLARE_APQ_GPIO_PINS(0); +DECLARE_APQ_GPIO_PINS(1); +DECLARE_APQ_GPIO_PINS(2); +DECLARE_APQ_GPIO_PINS(3); +DECLARE_APQ_GPIO_PINS(4); +DECLARE_APQ_GPIO_PINS(5); +DECLARE_APQ_GPIO_PINS(6); +DECLARE_APQ_GPIO_PINS(7); +DECLARE_APQ_GPIO_PINS(8); +DECLARE_APQ_GPIO_PINS(9); +DECLARE_APQ_GPIO_PINS(10); +DECLARE_APQ_GPIO_PINS(11); +DECLARE_APQ_GPIO_PINS(12); +DECLARE_APQ_GPIO_PINS(13); +DECLARE_APQ_GPIO_PINS(14); +DECLARE_APQ_GPIO_PINS(15); +DECLARE_APQ_GPIO_PINS(16); +DECLARE_APQ_GPIO_PINS(17); +DECLARE_APQ_GPIO_PINS(18); +DECLARE_APQ_GPIO_PINS(19); +DECLARE_APQ_GPIO_PINS(20); +DECLARE_APQ_GPIO_PINS(21); +DECLARE_APQ_GPIO_PINS(22); +DECLARE_APQ_GPIO_PINS(23); +DECLARE_APQ_GPIO_PINS(24); +DECLARE_APQ_GPIO_PINS(25); +DECLARE_APQ_GPIO_PINS(26); +DECLARE_APQ_GPIO_PINS(27); +DECLARE_APQ_GPIO_PINS(28); +DECLARE_APQ_GPIO_PINS(29); +DECLARE_APQ_GPIO_PINS(30); +DECLARE_APQ_GPIO_PINS(31); +DECLARE_APQ_GPIO_PINS(32); +DECLARE_APQ_GPIO_PINS(33); +DECLARE_APQ_GPIO_PINS(34); +DECLARE_APQ_GPIO_PINS(35); +DECLARE_APQ_GPIO_PINS(36); +DECLARE_APQ_GPIO_PINS(37); +DECLARE_APQ_GPIO_PINS(38); +DECLARE_APQ_GPIO_PINS(39); +DECLARE_APQ_GPIO_PINS(40); +DECLARE_APQ_GPIO_PINS(41); +DECLARE_APQ_GPIO_PINS(42); +DECLARE_APQ_GPIO_PINS(43); +DECLARE_APQ_GPIO_PINS(44); +DECLARE_APQ_GPIO_PINS(45); +DECLARE_APQ_GPIO_PINS(46); +DECLARE_APQ_GPIO_PINS(47); +DECLARE_APQ_GPIO_PINS(48); +DECLARE_APQ_GPIO_PINS(49); +DECLARE_APQ_GPIO_PINS(50); +DECLARE_APQ_GPIO_PINS(51); +DECLARE_APQ_GPIO_PINS(52); +DECLARE_APQ_GPIO_PINS(53); +DECLARE_APQ_GPIO_PINS(54); +DECLARE_APQ_GPIO_PINS(55); +DECLARE_APQ_GPIO_PINS(56); +DECLARE_APQ_GPIO_PINS(57); +DECLARE_APQ_GPIO_PINS(58); +DECLARE_APQ_GPIO_PINS(59); +DECLARE_APQ_GPIO_PINS(60); +DECLARE_APQ_GPIO_PINS(61); +DECLARE_APQ_GPIO_PINS(62); +DECLARE_APQ_GPIO_PINS(63); +DECLARE_APQ_GPIO_PINS(64); +DECLARE_APQ_GPIO_PINS(65); +DECLARE_APQ_GPIO_PINS(66); +DECLARE_APQ_GPIO_PINS(67); +DECLARE_APQ_GPIO_PINS(68); +DECLARE_APQ_GPIO_PINS(69); +DECLARE_APQ_GPIO_PINS(70); +DECLARE_APQ_GPIO_PINS(71); +DECLARE_APQ_GPIO_PINS(72); +DECLARE_APQ_GPIO_PINS(73); +DECLARE_APQ_GPIO_PINS(74); +DECLARE_APQ_GPIO_PINS(75); +DECLARE_APQ_GPIO_PINS(76); +DECLARE_APQ_GPIO_PINS(77); +DECLARE_APQ_GPIO_PINS(78); +DECLARE_APQ_GPIO_PINS(79); +DECLARE_APQ_GPIO_PINS(80); +DECLARE_APQ_GPIO_PINS(81); +DECLARE_APQ_GPIO_PINS(82); +DECLARE_APQ_GPIO_PINS(83); +DECLARE_APQ_GPIO_PINS(84); +DECLARE_APQ_GPIO_PINS(85); +DECLARE_APQ_GPIO_PINS(86); +DECLARE_APQ_GPIO_PINS(87); +DECLARE_APQ_GPIO_PINS(88); +DECLARE_APQ_GPIO_PINS(89); +DECLARE_APQ_GPIO_PINS(90); +DECLARE_APQ_GPIO_PINS(91); +DECLARE_APQ_GPIO_PINS(92); +DECLARE_APQ_GPIO_PINS(93); +DECLARE_APQ_GPIO_PINS(94); +DECLARE_APQ_GPIO_PINS(95); +DECLARE_APQ_GPIO_PINS(96); +DECLARE_APQ_GPIO_PINS(97); +DECLARE_APQ_GPIO_PINS(98); +DECLARE_APQ_GPIO_PINS(99); +DECLARE_APQ_GPIO_PINS(100); +DECLARE_APQ_GPIO_PINS(101); +DECLARE_APQ_GPIO_PINS(102); +DECLARE_APQ_GPIO_PINS(103); +DECLARE_APQ_GPIO_PINS(104); +DECLARE_APQ_GPIO_PINS(105); +DECLARE_APQ_GPIO_PINS(106); +DECLARE_APQ_GPIO_PINS(107); +DECLARE_APQ_GPIO_PINS(108); +DECLARE_APQ_GPIO_PINS(109); +DECLARE_APQ_GPIO_PINS(110); +DECLARE_APQ_GPIO_PINS(111); +DECLARE_APQ_GPIO_PINS(112); +DECLARE_APQ_GPIO_PINS(113); +DECLARE_APQ_GPIO_PINS(114); +DECLARE_APQ_GPIO_PINS(115); +DECLARE_APQ_GPIO_PINS(116); +DECLARE_APQ_GPIO_PINS(117); +DECLARE_APQ_GPIO_PINS(118); +DECLARE_APQ_GPIO_PINS(119); +DECLARE_APQ_GPIO_PINS(120); +DECLARE_APQ_GPIO_PINS(121); +DECLARE_APQ_GPIO_PINS(122); +DECLARE_APQ_GPIO_PINS(123); +DECLARE_APQ_GPIO_PINS(124); +DECLARE_APQ_GPIO_PINS(125); +DECLARE_APQ_GPIO_PINS(126); +DECLARE_APQ_GPIO_PINS(127); +DECLARE_APQ_GPIO_PINS(128); +DECLARE_APQ_GPIO_PINS(129); +DECLARE_APQ_GPIO_PINS(130); +DECLARE_APQ_GPIO_PINS(131); +DECLARE_APQ_GPIO_PINS(132); +DECLARE_APQ_GPIO_PINS(133); +DECLARE_APQ_GPIO_PINS(134); +DECLARE_APQ_GPIO_PINS(135); +DECLARE_APQ_GPIO_PINS(136); +DECLARE_APQ_GPIO_PINS(137); +DECLARE_APQ_GPIO_PINS(138); +DECLARE_APQ_GPIO_PINS(139); +DECLARE_APQ_GPIO_PINS(140); +DECLARE_APQ_GPIO_PINS(141); +DECLARE_APQ_GPIO_PINS(142); +DECLARE_APQ_GPIO_PINS(143); +DECLARE_APQ_GPIO_PINS(144); +DECLARE_APQ_GPIO_PINS(145); +DECLARE_APQ_GPIO_PINS(146); + +static const unsigned int sdc1_clk_pins[] = { 147 }; +static const unsigned int sdc1_cmd_pins[] = { 148 }; +static const unsigned int sdc1_data_pins[] = { 149 }; +static const unsigned int sdc2_clk_pins[] = { 150 }; +static const unsigned int sdc2_cmd_pins[] = { 151 }; +static const unsigned int sdc2_data_pins[] = { 152 }; + +#define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7) \ + { \ + .grp = PINCTRL_PINGROUP("gpio" #id, \ + gpio##id##_pins, \ + ARRAY_SIZE(gpio##id##_pins)), \ + .funcs = (int[]){ \ + APQ_MUX_gpio, \ + APQ_MUX_##f1, \ + APQ_MUX_##f2, \ + APQ_MUX_##f3, \ + APQ_MUX_##f4, \ + APQ_MUX_##f5, \ + APQ_MUX_##f6, \ + APQ_MUX_##f7 \ + }, \ + .nfuncs = 8, \ + .ctl_reg = 0x1000 + 0x10 * id, \ + .io_reg = 0x1004 + 0x10 * id, \ + .intr_cfg_reg = 0x1008 + 0x10 * id, \ + .intr_status_reg = 0x100c + 0x10 * id, \ + .intr_target_reg = 0x1008 + 0x10 * id, \ + .mux_bit = 2, \ + .pull_bit = 0, \ + .drv_bit = 6, \ + .oe_bit = 9, \ + .in_bit = 0, \ + .out_bit = 1, \ + .intr_enable_bit = 0, \ + .intr_status_bit = 0, \ + .intr_ack_high = 0, \ + .intr_target_bit = 5, \ + .intr_target_kpss_val = 3, \ + .intr_raw_status_bit = 4, \ + .intr_polarity_bit = 1, \ + .intr_detection_bit = 2, \ + .intr_detection_width = 2, \ + } + +#define SDC_PINGROUP(pg_name, ctl, pull, drv) \ + { \ + .grp = PINCTRL_PINGROUP(#pg_name, \ + pg_name##_pins, \ + ARRAY_SIZE(pg_name##_pins)), \ + .ctl_reg = ctl, \ + .io_reg = 0, \ + .intr_cfg_reg = 0, \ + .intr_status_reg = 0, \ + .intr_target_reg = 0, \ + .mux_bit = -1, \ + .pull_bit = pull, \ + .drv_bit = drv, \ + .oe_bit = -1, \ + .in_bit = -1, \ + .out_bit = -1, \ + .intr_enable_bit = -1, \ + .intr_status_bit = -1, \ + .intr_target_bit = -1, \ + .intr_target_kpss_val = -1, \ + .intr_raw_status_bit = -1, \ + .intr_polarity_bit = -1, \ + .intr_detection_bit = -1, \ + .intr_detection_width = -1, \ + } + +enum apq8084_functions { + APQ_MUX_adsp_ext, + APQ_MUX_audio_ref, + APQ_MUX_blsp_i2c1, + APQ_MUX_blsp_i2c2, + APQ_MUX_blsp_i2c3, + APQ_MUX_blsp_i2c4, + APQ_MUX_blsp_i2c5, + APQ_MUX_blsp_i2c6, + APQ_MUX_blsp_i2c7, + APQ_MUX_blsp_i2c8, + APQ_MUX_blsp_i2c9, + APQ_MUX_blsp_i2c10, + APQ_MUX_blsp_i2c11, + APQ_MUX_blsp_i2c12, + APQ_MUX_blsp_spi1, + APQ_MUX_blsp_spi1_cs1, + APQ_MUX_blsp_spi1_cs2, + APQ_MUX_blsp_spi1_cs3, + APQ_MUX_blsp_spi2, + APQ_MUX_blsp_spi3, + APQ_MUX_blsp_spi3_cs1, + APQ_MUX_blsp_spi3_cs2, + APQ_MUX_blsp_spi3_cs3, + APQ_MUX_blsp_spi4, + APQ_MUX_blsp_spi5, + APQ_MUX_blsp_spi6, + APQ_MUX_blsp_spi7, + APQ_MUX_blsp_spi8, + APQ_MUX_blsp_spi9, + APQ_MUX_blsp_spi10, + APQ_MUX_blsp_spi10_cs1, + APQ_MUX_blsp_spi10_cs2, + APQ_MUX_blsp_spi10_cs3, + APQ_MUX_blsp_spi11, + APQ_MUX_blsp_spi12, + APQ_MUX_blsp_uart1, + APQ_MUX_blsp_uart2, + APQ_MUX_blsp_uart3, + APQ_MUX_blsp_uart4, + APQ_MUX_blsp_uart5, + APQ_MUX_blsp_uart6, + APQ_MUX_blsp_uart7, + APQ_MUX_blsp_uart8, + APQ_MUX_blsp_uart9, + APQ_MUX_blsp_uart10, + APQ_MUX_blsp_uart11, + APQ_MUX_blsp_uart12, + APQ_MUX_blsp_uim1, + APQ_MUX_blsp_uim2, + APQ_MUX_blsp_uim3, + APQ_MUX_blsp_uim4, + APQ_MUX_blsp_uim5, + APQ_MUX_blsp_uim6, + APQ_MUX_blsp_uim7, + APQ_MUX_blsp_uim8, + APQ_MUX_blsp_uim9, + APQ_MUX_blsp_uim10, + APQ_MUX_blsp_uim11, + APQ_MUX_blsp_uim12, + APQ_MUX_cam_mclk0, + APQ_MUX_cam_mclk1, + APQ_MUX_cam_mclk2, + APQ_MUX_cam_mclk3, + APQ_MUX_cci_async, + APQ_MUX_cci_async_in0, + APQ_MUX_cci_i2c0, + APQ_MUX_cci_i2c1, + APQ_MUX_cci_timer0, + APQ_MUX_cci_timer1, + APQ_MUX_cci_timer2, + APQ_MUX_cci_timer3, + APQ_MUX_cci_timer4, + APQ_MUX_edp_hpd, + APQ_MUX_gcc_gp1, + APQ_MUX_gcc_gp2, + APQ_MUX_gcc_gp3, + APQ_MUX_gcc_obt, + APQ_MUX_gcc_vtt, + APQ_MUX_gp_mn, + APQ_MUX_gp_pdm0, + APQ_MUX_gp_pdm1, + APQ_MUX_gp_pdm2, + APQ_MUX_gp0_clk, + APQ_MUX_gp1_clk, + APQ_MUX_gpio, + APQ_MUX_hdmi_cec, + APQ_MUX_hdmi_ddc, + APQ_MUX_hdmi_dtest, + APQ_MUX_hdmi_hpd, + APQ_MUX_hdmi_rcv, + APQ_MUX_hsic, + APQ_MUX_ldo_en, + APQ_MUX_ldo_update, + APQ_MUX_mdp_vsync, + APQ_MUX_pci_e0, + APQ_MUX_pci_e0_n, + APQ_MUX_pci_e0_rst, + APQ_MUX_pci_e1, + APQ_MUX_pci_e1_rst, + APQ_MUX_pci_e1_rst_n, + APQ_MUX_pci_e1_clkreq_n, + APQ_MUX_pri_mi2s, + APQ_MUX_qua_mi2s, + APQ_MUX_sata_act, + APQ_MUX_sata_devsleep, + APQ_MUX_sata_devsleep_n, + APQ_MUX_sd_write, + APQ_MUX_sdc_emmc_mode, + APQ_MUX_sdc3, + APQ_MUX_sdc4, + APQ_MUX_sec_mi2s, + APQ_MUX_slimbus, + APQ_MUX_spdif_tx, + APQ_MUX_spkr_i2s, + APQ_MUX_spkr_i2s_ws, + APQ_MUX_spss_geni, + APQ_MUX_ter_mi2s, + APQ_MUX_tsif1, + APQ_MUX_tsif2, + APQ_MUX_uim, + APQ_MUX_uim_batt_alarm, + APQ_MUX_NA, +}; + +static const char * const gpio_groups[] = { + "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7", + "gpio8", "gpio9", "gpio10", "gpio11", "gpio12", "gpio13", "gpio14", + "gpio15", "gpio16", "gpio17", "gpio18", "gpio19", "gpio20", "gpio21", + "gpio22", "gpio23", "gpio24", "gpio25", "gpio26", "gpio27", "gpio28", + "gpio29", "gpio30", "gpio31", "gpio32", "gpio33", "gpio34", "gpio35", + "gpio36", "gpio37", "gpio38", "gpio39", "gpio40", "gpio41", "gpio42", + "gpio43", "gpio44", "gpio45", "gpio46", "gpio47", "gpio48", "gpio49", + "gpio50", "gpio51", "gpio52", "gpio53", "gpio54", "gpio55", "gpio56", + "gpio57", "gpio58", "gpio59", "gpio60", "gpio61", "gpio62", "gpio63", + "gpio64", "gpio65", "gpio66", "gpio67", "gpio68", "gpio69", "gpio70", + "gpio71", "gpio72", "gpio73", "gpio74", "gpio75", "gpio76", "gpio77", + "gpio78", "gpio79", "gpio80", "gpio81", "gpio82", "gpio83", "gpio84", + "gpio85", "gpio86", "gpio87", "gpio88", "gpio89", "gpio90", "gpio91", + "gpio92", "gpio93", "gpio94", "gpio95", "gpio96", "gpio97", "gpio98", + "gpio99", "gpio100", "gpio101", "gpio102", "gpio103", "gpio104", + "gpio105", "gpio106", "gpio107", "gpio108", "gpio109", "gpio110", + "gpio111", "gpio112", "gpio113", "gpio114", "gpio115", "gpio116", + "gpio117", "gpio118", "gpio119", "gpio120", "gpio121", "gpio122", + "gpio123", "gpio124", "gpio125", "gpio126", "gpio127", "gpio128", + "gpio129", "gpio130", "gpio131", "gpio132", "gpio133", "gpio134", + "gpio135", "gpio136", "gpio137", "gpio138", "gpio139", "gpio140", + "gpio141", "gpio142", "gpio143", "gpio144", "gpio145", "gpio146" +}; + +static const char * const adsp_ext_groups[] = { + "gpio34" +}; +static const char * const audio_ref_groups[] = { + "gpio100" +}; +static const char * const blsp_i2c1_groups[] = { + "gpio2", "gpio3" +}; +static const char * const blsp_i2c2_groups[] = { + "gpio6", "gpio7" +}; +static const char * const blsp_i2c3_groups[] = { + "gpio10", "gpio11" +}; +static const char * const blsp_i2c4_groups[] = { + "gpio29", "gpio30" +}; +static const char * const blsp_i2c5_groups[] = { + "gpio41", "gpio42" +}; +static const char * const blsp_i2c6_groups[] = { + "gpio45", "gpio46" +}; +static const char * const blsp_i2c7_groups[] = { + "gpio132", "gpio133" +}; +static const char * const blsp_i2c8_groups[] = { + "gpio53", "gpio54" +}; +static const char * const blsp_i2c9_groups[] = { + "gpio57", "gpio58" +}; +static const char * const blsp_i2c10_groups[] = { + "gpio61", "gpio62" +}; +static const char * const blsp_i2c11_groups[] = { + "gpio65", "gpio66" +}; +static const char * const blsp_i2c12_groups[] = { + "gpio49", "gpio50" +}; +static const char * const blsp_spi1_groups[] = { + "gpio0", "gpio1", "gpio2", "gpio3" +}; +static const char * const blsp_spi2_groups[] = { + "gpio4", "gpio5", "gpio6", "gpio7" +}; +static const char * const blsp_spi3_groups[] = { + "gpio8", "gpio9", "gpio10", "gpio11" +}; +static const char * const blsp_spi4_groups[] = { + "gpio27", "gpio28", "gpio29", "gpio30" +}; +static const char * const blsp_spi5_groups[] = { + "gpio39", "gpio40", "gpio41", "gpio42" +}; +static const char * const blsp_spi6_groups[] = { + "gpio43", "gpio44", "gpio45", "gpio46" +}; +static const char * const blsp_spi7_groups[] = { + "gpio130", "gpio131", "gpio132", "gpio133" +}; +static const char * const blsp_spi8_groups[] = { + "gpio51", "gpio52", "gpio53", "gpio54" +}; +static const char * const blsp_spi9_groups[] = { + "gpio55", "gpio56", "gpio57", "gpio58" +}; +static const char * const blsp_spi10_groups[] = { + "gpio59", "gpio60", "gpio61", "gpio62" +}; +static const char * const blsp_spi11_groups[] = { + "gpio63", "gpio64", "gpio65", "gpio66" +}; +static const char * const blsp_spi12_groups[] = { + "gpio47", "gpio48", "gpio49", "gpio50" +}; +static const char * const blsp_uart1_groups[] = { + "gpio0", "gpio1", "gpio2", "gpio3" +}; +static const char * const blsp_uart2_groups[] = { + "gpio4", "gpio5", "gpio6", "gpio7" +}; +static const char * const blsp_uart3_groups[] = { + "gpio8" +}; +static const char * const blsp_uart4_groups[] = { + "gpio27", "gpio28", "gpio29", "gpio30" +}; +static const char * const blsp_uart5_groups[] = { + "gpio39", "gpio40", "gpio41", "gpio42" +}; +static const char * const blsp_uart6_groups[] = { + "gpio43", "gpio44", "gpio45", "gpio46" +}; +static const char * const blsp_uart7_groups[] = { + "gpio130", "gpio131", "gpio132", "gpio133" +}; +static const char * const blsp_uart8_groups[] = { + "gpio51", "gpio52", "gpio53", "gpio54" +}; +static const char * const blsp_uart9_groups[] = { + "gpio55", "gpio56", "gpio57", "gpio58" +}; +static const char * const blsp_uart10_groups[] = { + "gpio59", "gpio60", "gpio61", "gpio62" +}; +static const char * const blsp_uart11_groups[] = { + "gpio63", "gpio64", "gpio65", "gpio66" +}; +static const char * const blsp_uart12_groups[] = { + "gpio47", "gpio48", "gpio49", "gpio50" +}; +static const char * const blsp_uim1_groups[] = { + "gpio0", "gpio1" +}; +static const char * const blsp_uim2_groups[] = { + "gpio4", "gpio5" +}; +static const char * const blsp_uim3_groups[] = { + "gpio8", "gpio9" +}; +static const char * const blsp_uim4_groups[] = { + "gpio27", "gpio28" +}; +static const char * const blsp_uim5_groups[] = { + "gpio39", "gpio40" +}; +static const char * const blsp_uim6_groups[] = { + "gpio43", "gpio44" +}; +static const char * const blsp_uim7_groups[] = { + "gpio130", "gpio131" +}; +static const char * const blsp_uim8_groups[] = { + "gpio51", "gpio52" +}; +static const char * const blsp_uim9_groups[] = { + "gpio55", "gpio56" +}; +static const char * const blsp_uim10_groups[] = { + "gpio59", "gpio60" +}; +static const char * const blsp_uim11_groups[] = { + "gpio63", "gpio64" +}; +static const char * const blsp_uim12_groups[] = { + "gpio47", "gpio48" +}; +static const char * const blsp_spi1_cs1_groups[] = { + "gpio116" +}; +static const char * const blsp_spi1_cs2_groups[] = { + "gpio117" +}; +static const char * const blsp_spi1_cs3_groups[] = { + "gpio118" +}; +static const char * const blsp_spi3_cs1_groups[] = { + "gpio67" +}; +static const char * const blsp_spi3_cs2_groups[] = { + "gpio71" +}; +static const char * const blsp_spi3_cs3_groups[] = { + "gpio72" +}; +static const char * const blsp_spi10_cs1_groups[] = { + "gpio106" +}; +static const char * const blsp_spi10_cs2_groups[] = { + "gpio111" +}; +static const char * const blsp_spi10_cs3_groups[] = { + "gpio128" +}; +static const char * const cam_mclk0_groups[] = { + "gpio15" +}; +static const char * const cam_mclk1_groups[] = { + "gpio16" +}; +static const char * const cam_mclk2_groups[] = { + "gpio17" +}; +static const char * const cam_mclk3_groups[] = { + "gpio18" +}; +static const char * const cci_async_groups[] = { + "gpio26", "gpio119" +}; +static const char * const cci_async_in0_groups[] = { + "gpio120" +}; +static const char * const cci_i2c0_groups[] = { + "gpio19", "gpio20" +}; +static const char * const cci_i2c1_groups[] = { + "gpio21", "gpio22" +}; +static const char * const cci_timer0_groups[] = { + "gpio23" +}; +static const char * const cci_timer1_groups[] = { + "gpio24" +}; +static const char * const cci_timer2_groups[] = { + "gpio25" +}; +static const char * const cci_timer3_groups[] = { + "gpio26" +}; +static const char * const cci_timer4_groups[] = { + "gpio119" +}; +static const char * const edp_hpd_groups[] = { + "gpio103" +}; +static const char * const gcc_gp1_groups[] = { + "gpio37" +}; +static const char * const gcc_gp2_groups[] = { + "gpio38" +}; +static const char * const gcc_gp3_groups[] = { + "gpio86" +}; +static const char * const gcc_obt_groups[] = { + "gpio127" +}; +static const char * const gcc_vtt_groups[] = { + "gpio126" +}; +static const char * const gp_mn_groups[] = { + "gpio29" +}; +static const char * const gp_pdm0_groups[] = { + "gpio48", "gpio83" +}; +static const char * const gp_pdm1_groups[] = { + "gpio84", "gpio101" +}; +static const char * const gp_pdm2_groups[] = { + "gpio85", "gpio110" +}; +static const char * const gp0_clk_groups[] = { + "gpio25" +}; +static const char * const gp1_clk_groups[] = { + "gpio26" +}; +static const char * const hdmi_cec_groups[] = { + "gpio31" +}; +static const char * const hdmi_ddc_groups[] = { + "gpio32", "gpio33" +}; +static const char * const hdmi_dtest_groups[] = { + "gpio123" +}; +static const char * const hdmi_hpd_groups[] = { + "gpio34" +}; +static const char * const hdmi_rcv_groups[] = { + "gpio125" +}; +static const char * const hsic_groups[] = { + "gpio134", "gpio135" +}; +static const char * const ldo_en_groups[] = { + "gpio124" +}; +static const char * const ldo_update_groups[] = { + "gpio125" +}; +static const char * const mdp_vsync_groups[] = { + "gpio12", "gpio13", "gpio14" +}; +static const char * const pci_e0_groups[] = { + "gpio68", "gpio70" +}; +static const char * const pci_e0_n_groups[] = { + "gpio68", "gpio70" +}; +static const char * const pci_e0_rst_groups[] = { + "gpio70" +}; +static const char * const pci_e1_groups[] = { + "gpio140" +}; +static const char * const pci_e1_rst_groups[] = { + "gpio140" +}; +static const char * const pci_e1_rst_n_groups[] = { + "gpio140" +}; +static const char * const pci_e1_clkreq_n_groups[] = { + "gpio141" +}; +static const char * const pri_mi2s_groups[] = { + "gpio76", "gpio77", "gpio78", "gpio79", "gpio80" +}; +static const char * const qua_mi2s_groups[] = { + "gpio91", "gpio92", "gpio93", "gpio94", "gpio95", "gpio96", "gpio97" +}; +static const char * const sata_act_groups[] = { + "gpio129" +}; +static const char * const sata_devsleep_groups[] = { + "gpio119" +}; +static const char * const sata_devsleep_n_groups[] = { + "gpio119" +}; +static const char * const sd_write_groups[] = { + "gpio75" +}; +static const char * const sdc_emmc_mode_groups[] = { + "gpio146" +}; +static const char * const sdc3_groups[] = { + "gpio67", "gpio68", "gpio69", "gpio70", "gpio71", "gpio72" +}; +static const char * const sdc4_groups[] = { + "gpio82", "gpio83", "gpio84", "gpio85", "gpio86", + "gpio91", "gpio95", "gpio96", "gpio97", "gpio101" +}; +static const char * const sec_mi2s_groups[] = { + "gpio81", "gpio82", "gpio83", "gpio84", "gpio85" +}; +static const char * const slimbus_groups[] = { + "gpio98", "gpio99" +}; +static const char * const spdif_tx_groups[] = { + "gpio124", "gpio136", "gpio142" +}; +static const char * const spkr_i2s_groups[] = { + "gpio98", "gpio99", "gpio100" +}; +static const char * const spkr_i2s_ws_groups[] = { + "gpio104" +}; +static const char * const spss_geni_groups[] = { + "gpio8", "gpio9" +}; +static const char * const ter_mi2s_groups[] = { + "gpio86", "gpio87", "gpio88", "gpio89", "gpio90" +}; +static const char * const tsif1_groups[] = { + "gpio82", "gpio83", "gpio84", "gpio85", "gpio86" +}; +static const char * const tsif2_groups[] = { + "gpio91", "gpio95", "gpio96", "gpio97", "gpio101" +}; +static const char * const uim_groups[] = { + "gpio130", "gpio131", "gpio132", "gpio133" +}; +static const char * const uim_batt_alarm_groups[] = { + "gpio102" +}; +static const struct pinfunction apq8084_functions[] = { + APQ_PIN_FUNCTION(adsp_ext), + APQ_PIN_FUNCTION(audio_ref), + APQ_PIN_FUNCTION(blsp_i2c1), + APQ_PIN_FUNCTION(blsp_i2c2), + APQ_PIN_FUNCTION(blsp_i2c3), + APQ_PIN_FUNCTION(blsp_i2c4), + APQ_PIN_FUNCTION(blsp_i2c5), + APQ_PIN_FUNCTION(blsp_i2c6), + APQ_PIN_FUNCTION(blsp_i2c7), + APQ_PIN_FUNCTION(blsp_i2c8), + APQ_PIN_FUNCTION(blsp_i2c9), + APQ_PIN_FUNCTION(blsp_i2c10), + APQ_PIN_FUNCTION(blsp_i2c11), + APQ_PIN_FUNCTION(blsp_i2c12), + APQ_PIN_FUNCTION(blsp_spi1), + APQ_PIN_FUNCTION(blsp_spi1_cs1), + APQ_PIN_FUNCTION(blsp_spi1_cs2), + APQ_PIN_FUNCTION(blsp_spi1_cs3), + APQ_PIN_FUNCTION(blsp_spi2), + APQ_PIN_FUNCTION(blsp_spi3), + APQ_PIN_FUNCTION(blsp_spi3_cs1), + APQ_PIN_FUNCTION(blsp_spi3_cs2), + APQ_PIN_FUNCTION(blsp_spi3_cs3), + APQ_PIN_FUNCTION(blsp_spi4), + APQ_PIN_FUNCTION(blsp_spi5), + APQ_PIN_FUNCTION(blsp_spi6), + APQ_PIN_FUNCTION(blsp_spi7), + APQ_PIN_FUNCTION(blsp_spi8), + APQ_PIN_FUNCTION(blsp_spi9), + APQ_PIN_FUNCTION(blsp_spi10), + APQ_PIN_FUNCTION(blsp_spi10_cs1), + APQ_PIN_FUNCTION(blsp_spi10_cs2), + APQ_PIN_FUNCTION(blsp_spi10_cs3), + APQ_PIN_FUNCTION(blsp_spi11), + APQ_PIN_FUNCTION(blsp_spi12), + APQ_PIN_FUNCTION(blsp_uart1), + APQ_PIN_FUNCTION(blsp_uart2), + APQ_PIN_FUNCTION(blsp_uart3), + APQ_PIN_FUNCTION(blsp_uart4), + APQ_PIN_FUNCTION(blsp_uart5), + APQ_PIN_FUNCTION(blsp_uart6), + APQ_PIN_FUNCTION(blsp_uart7), + APQ_PIN_FUNCTION(blsp_uart8), + APQ_PIN_FUNCTION(blsp_uart9), + APQ_PIN_FUNCTION(blsp_uart10), + APQ_PIN_FUNCTION(blsp_uart11), + APQ_PIN_FUNCTION(blsp_uart12), + APQ_PIN_FUNCTION(blsp_uim1), + APQ_PIN_FUNCTION(blsp_uim2), + APQ_PIN_FUNCTION(blsp_uim3), + APQ_PIN_FUNCTION(blsp_uim4), + APQ_PIN_FUNCTION(blsp_uim5), + APQ_PIN_FUNCTION(blsp_uim6), + APQ_PIN_FUNCTION(blsp_uim7), + APQ_PIN_FUNCTION(blsp_uim8), + APQ_PIN_FUNCTION(blsp_uim9), + APQ_PIN_FUNCTION(blsp_uim10), + APQ_PIN_FUNCTION(blsp_uim11), + APQ_PIN_FUNCTION(blsp_uim12), + APQ_PIN_FUNCTION(cam_mclk0), + APQ_PIN_FUNCTION(cam_mclk1), + APQ_PIN_FUNCTION(cam_mclk2), + APQ_PIN_FUNCTION(cam_mclk3), + APQ_PIN_FUNCTION(cci_async), + APQ_PIN_FUNCTION(cci_async_in0), + APQ_PIN_FUNCTION(cci_i2c0), + APQ_PIN_FUNCTION(cci_i2c1), + APQ_PIN_FUNCTION(cci_timer0), + APQ_PIN_FUNCTION(cci_timer1), + APQ_PIN_FUNCTION(cci_timer2), + APQ_PIN_FUNCTION(cci_timer3), + APQ_PIN_FUNCTION(cci_timer4), + APQ_PIN_FUNCTION(edp_hpd), + APQ_PIN_FUNCTION(gcc_gp1), + APQ_PIN_FUNCTION(gcc_gp2), + APQ_PIN_FUNCTION(gcc_gp3), + APQ_PIN_FUNCTION(gcc_obt), + APQ_PIN_FUNCTION(gcc_vtt), + APQ_PIN_FUNCTION(gp_mn), + APQ_PIN_FUNCTION(gp_pdm0), + APQ_PIN_FUNCTION(gp_pdm1), + APQ_PIN_FUNCTION(gp_pdm2), + APQ_PIN_FUNCTION(gp0_clk), + APQ_PIN_FUNCTION(gp1_clk), + APQ_PIN_FUNCTION(gpio), + APQ_PIN_FUNCTION(hdmi_cec), + APQ_PIN_FUNCTION(hdmi_ddc), + APQ_PIN_FUNCTION(hdmi_dtest), + APQ_PIN_FUNCTION(hdmi_hpd), + APQ_PIN_FUNCTION(hdmi_rcv), + APQ_PIN_FUNCTION(hsic), + APQ_PIN_FUNCTION(ldo_en), + APQ_PIN_FUNCTION(ldo_update), + APQ_PIN_FUNCTION(mdp_vsync), + APQ_PIN_FUNCTION(pci_e0), + APQ_PIN_FUNCTION(pci_e0_n), + APQ_PIN_FUNCTION(pci_e0_rst), + APQ_PIN_FUNCTION(pci_e1), + APQ_PIN_FUNCTION(pci_e1_rst), + APQ_PIN_FUNCTION(pci_e1_rst_n), + APQ_PIN_FUNCTION(pci_e1_clkreq_n), + APQ_PIN_FUNCTION(pri_mi2s), + APQ_PIN_FUNCTION(qua_mi2s), + APQ_PIN_FUNCTION(sata_act), + APQ_PIN_FUNCTION(sata_devsleep), + APQ_PIN_FUNCTION(sata_devsleep_n), + APQ_PIN_FUNCTION(sd_write), + APQ_PIN_FUNCTION(sdc_emmc_mode), + APQ_PIN_FUNCTION(sdc3), + APQ_PIN_FUNCTION(sdc4), + APQ_PIN_FUNCTION(sec_mi2s), + APQ_PIN_FUNCTION(slimbus), + APQ_PIN_FUNCTION(spdif_tx), + APQ_PIN_FUNCTION(spkr_i2s), + APQ_PIN_FUNCTION(spkr_i2s_ws), + APQ_PIN_FUNCTION(spss_geni), + APQ_PIN_FUNCTION(ter_mi2s), + APQ_PIN_FUNCTION(tsif1), + APQ_PIN_FUNCTION(tsif2), + APQ_PIN_FUNCTION(uim), + APQ_PIN_FUNCTION(uim_batt_alarm), +}; + +static const struct msm_pingroup apq8084_groups[] = { + PINGROUP(0, blsp_spi1, blsp_uart1, blsp_uim1, NA, NA, NA, NA), + PINGROUP(1, blsp_spi1, blsp_uart1, blsp_uim1, NA, NA, NA, NA), + PINGROUP(2, blsp_spi1, blsp_uart1, blsp_i2c1, NA, NA, NA, NA), + PINGROUP(3, blsp_spi1, blsp_uart1, blsp_i2c1, NA, NA, NA, NA), + PINGROUP(4, blsp_spi2, blsp_uart2, blsp_uim2, NA, NA, NA, NA), + PINGROUP(5, blsp_spi2, blsp_uart2, blsp_uim2, NA, NA, NA, NA), + PINGROUP(6, blsp_spi2, blsp_uart2, blsp_i2c2, NA, NA, NA, NA), + PINGROUP(7, blsp_spi2, blsp_uart2, blsp_i2c2, NA, NA, NA, NA), + PINGROUP(8, blsp_spi3, blsp_uart3, blsp_uim3, spss_geni, NA, NA, NA), + PINGROUP(9, blsp_spi3, blsp_uim3, blsp_uart3, spss_geni, NA, NA, NA), + PINGROUP(10, blsp_spi3, blsp_uart3, blsp_i2c3, NA, NA, NA, NA), + PINGROUP(11, blsp_spi3, blsp_uart3, blsp_i2c3, NA, NA, NA, NA), + PINGROUP(12, mdp_vsync, NA, NA, NA, NA, NA, NA), + PINGROUP(13, mdp_vsync, NA, NA, NA, NA, NA, NA), + PINGROUP(14, mdp_vsync, NA, NA, NA, NA, NA, NA), + PINGROUP(15, cam_mclk0, NA, NA, NA, NA, NA, NA), + PINGROUP(16, cam_mclk1, NA, NA, NA, NA, NA, NA), + PINGROUP(17, cam_mclk2, NA, NA, NA, NA, NA, NA), + PINGROUP(18, cam_mclk3, NA, NA, NA, NA, NA, NA), + PINGROUP(19, cci_i2c0, NA, NA, NA, NA, NA, NA), + PINGROUP(20, cci_i2c0, NA, NA, NA, NA, NA, NA), + PINGROUP(21, cci_i2c1, NA, NA, NA, NA, NA, NA), + PINGROUP(22, cci_i2c1, NA, NA, NA, NA, NA, NA), + PINGROUP(23, cci_timer0, NA, NA, NA, NA, NA, NA), + PINGROUP(24, cci_timer1, NA, NA, NA, NA, NA, NA), + PINGROUP(25, cci_timer2, gp0_clk, NA, NA, NA, NA, NA), + PINGROUP(26, cci_timer3, cci_async, gp1_clk, NA, NA, NA, NA), + PINGROUP(27, blsp_spi4, blsp_uart4, blsp_uim4, NA, NA, NA, NA), + PINGROUP(28, blsp_spi4, blsp_uart4, blsp_uim4, NA, NA, NA, NA), + PINGROUP(29, blsp_spi4, blsp_uart4, blsp_i2c4, gp_mn, NA, NA, NA), + PINGROUP(30, blsp_spi4, blsp_uart4, blsp_i2c4, NA, NA, NA, NA), + PINGROUP(31, hdmi_cec, NA, NA, NA, NA, NA, NA), + PINGROUP(32, hdmi_ddc, NA, NA, NA, NA, NA, NA), + PINGROUP(33, hdmi_ddc, NA, NA, NA, NA, NA, NA), + PINGROUP(34, hdmi_hpd, NA, adsp_ext, NA, NA, NA, NA), + PINGROUP(35, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(36, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(37, gcc_gp1, NA, NA, NA, NA, NA, NA), + PINGROUP(38, gcc_gp2, NA, NA, NA, NA, NA, NA), + PINGROUP(39, blsp_spi5, blsp_uart5, blsp_uim5, NA, NA, NA, NA), + PINGROUP(40, blsp_spi5, blsp_uart5, blsp_uim5, NA, NA, NA, NA), + PINGROUP(41, blsp_spi5, blsp_uart5, blsp_i2c5, NA, NA, NA, NA), + PINGROUP(42, blsp_spi5, blsp_uart5, blsp_i2c5, NA, NA, NA, NA), + PINGROUP(43, blsp_spi6, blsp_uart6, blsp_uim6, NA, NA, NA, NA), + PINGROUP(44, blsp_spi6, blsp_uart6, blsp_uim6, NA, NA, NA, NA), + PINGROUP(45, blsp_spi6, blsp_uart6, blsp_i2c6, NA, NA, NA, NA), + PINGROUP(46, blsp_spi6, blsp_uart6, blsp_i2c6, NA, NA, NA, NA), + PINGROUP(47, blsp_spi12, blsp_uart12, blsp_uim12, NA, NA, NA, NA), + PINGROUP(48, blsp_spi12, blsp_uart12, blsp_uim12, gp_pdm0, NA, NA, NA), + PINGROUP(49, blsp_spi12, blsp_uart12, blsp_i2c12, NA, NA, NA, NA), + PINGROUP(50, blsp_spi12, blsp_uart12, blsp_i2c12, NA, NA, NA, NA), + PINGROUP(51, blsp_spi8, blsp_uart8, blsp_uim8, NA, NA, NA, NA), + PINGROUP(52, blsp_spi8, blsp_uart8, blsp_uim8, NA, NA, NA, NA), + PINGROUP(53, blsp_spi8, blsp_uart8, blsp_i2c8, NA, NA, NA, NA), + PINGROUP(54, blsp_spi8, blsp_uart8, blsp_i2c8, NA, NA, NA, NA), + PINGROUP(55, blsp_spi9, blsp_uart9, blsp_uim9, NA, NA, NA, NA), + PINGROUP(56, blsp_spi9, blsp_uart9, blsp_uim9, NA, NA, NA, NA), + PINGROUP(57, blsp_spi9, blsp_uart9, blsp_i2c9, NA, NA, NA, NA), + PINGROUP(58, blsp_spi9, blsp_uart9, blsp_i2c9, NA, NA, NA, NA), + PINGROUP(59, blsp_spi10, blsp_uart10, blsp_uim10, NA, NA, NA, NA), + PINGROUP(60, blsp_spi10, blsp_uart10, blsp_uim10, NA, NA, NA, NA), + PINGROUP(61, blsp_spi10, blsp_uart10, blsp_i2c10, NA, NA, NA, NA), + PINGROUP(62, blsp_spi10, blsp_uart10, blsp_i2c10, NA, NA, NA, NA), + PINGROUP(63, blsp_spi11, blsp_uart11, blsp_uim11, NA, NA, NA, NA), + PINGROUP(64, blsp_spi11, blsp_uart11, blsp_uim11, NA, NA, NA, NA), + PINGROUP(65, blsp_spi11, blsp_uart11, blsp_i2c11, NA, NA, NA, NA), + PINGROUP(66, blsp_spi11, blsp_uart11, blsp_i2c11, NA, NA, NA, NA), + PINGROUP(67, sdc3, blsp_spi3_cs1, NA, NA, NA, NA, NA), + PINGROUP(68, sdc3, pci_e0, NA, NA, NA, NA, NA), + PINGROUP(69, sdc3, NA, NA, NA, NA, NA, NA), + PINGROUP(70, sdc3, pci_e0_n, pci_e0, NA, NA, NA, NA), + PINGROUP(71, sdc3, blsp_spi3_cs2, NA, NA, NA, NA, NA), + PINGROUP(72, sdc3, blsp_spi3_cs3, NA, NA, NA, NA, NA), + PINGROUP(73, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(74, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(75, sd_write, NA, NA, NA, NA, NA, NA), + PINGROUP(76, pri_mi2s, NA, NA, NA, NA, NA, NA), + PINGROUP(77, pri_mi2s, NA, NA, NA, NA, NA, NA), + PINGROUP(78, pri_mi2s, NA, NA, NA, NA, NA, NA), + PINGROUP(79, pri_mi2s, NA, NA, NA, NA, NA, NA), + PINGROUP(80, pri_mi2s, NA, NA, NA, NA, NA, NA), + PINGROUP(81, sec_mi2s, NA, NA, NA, NA, NA, NA), + PINGROUP(82, sec_mi2s, sdc4, tsif1, NA, NA, NA, NA), + PINGROUP(83, sec_mi2s, sdc4, tsif1, NA, NA, NA, gp_pdm0), + PINGROUP(84, sec_mi2s, sdc4, tsif1, NA, NA, NA, gp_pdm1), + PINGROUP(85, sec_mi2s, sdc4, tsif1, NA, gp_pdm2, NA, NA), + PINGROUP(86, ter_mi2s, sdc4, tsif1, NA, NA, NA, gcc_gp3), + PINGROUP(87, ter_mi2s, NA, NA, NA, NA, NA, NA), + PINGROUP(88, ter_mi2s, NA, NA, NA, NA, NA, NA), + PINGROUP(89, ter_mi2s, NA, NA, NA, NA, NA, NA), + PINGROUP(90, ter_mi2s, NA, NA, NA, NA, NA, NA), + PINGROUP(91, qua_mi2s, sdc4, tsif2, NA, NA, NA, NA), + PINGROUP(92, qua_mi2s, NA, NA, NA, NA, NA, NA), + PINGROUP(93, qua_mi2s, NA, NA, NA, NA, NA, NA), + PINGROUP(94, qua_mi2s, NA, NA, NA, NA, NA, NA), + PINGROUP(95, qua_mi2s, sdc4, tsif2, NA, NA, NA, gcc_gp1), + PINGROUP(96, qua_mi2s, sdc4, tsif2, NA, NA, NA, gcc_gp2), + PINGROUP(97, qua_mi2s, sdc4, tsif2, NA, gcc_gp3, NA, NA), + PINGROUP(98, slimbus, spkr_i2s, NA, NA, NA, NA, NA), + PINGROUP(99, slimbus, spkr_i2s, NA, NA, NA, NA, NA), + PINGROUP(100, audio_ref, spkr_i2s, NA, NA, NA, NA, NA), + PINGROUP(101, sdc4, tsif2, gp_pdm1, NA, NA, NA, NA), + PINGROUP(102, uim_batt_alarm, NA, NA, NA, NA, NA, NA), + PINGROUP(103, edp_hpd, NA, NA, NA, NA, NA, NA), + PINGROUP(104, spkr_i2s, NA, NA, NA, NA, NA, NA), + PINGROUP(105, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(106, blsp_spi10_cs1, NA, NA, NA, NA, NA, NA), + PINGROUP(107, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(108, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(109, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(110, gp_pdm2, NA, NA, NA, NA, NA, NA), + PINGROUP(111, blsp_spi10_cs2, NA, NA, NA, NA, NA, NA), + PINGROUP(112, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(113, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(114, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(115, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(116, blsp_spi1_cs1, NA, NA, NA, NA, NA, NA), + PINGROUP(117, blsp_spi1_cs2, NA, NA, NA, NA, NA, NA), + PINGROUP(118, blsp_spi1_cs3, NA, NA, NA, NA, NA, NA), + PINGROUP(119, cci_timer4, cci_async, sata_devsleep, sata_devsleep_n, NA, NA, NA), + PINGROUP(120, cci_async, NA, NA, NA, NA, NA, NA), + PINGROUP(121, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(122, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(123, hdmi_dtest, NA, NA, NA, NA, NA, NA), + PINGROUP(124, spdif_tx, ldo_en, NA, NA, NA, NA, NA), + PINGROUP(125, ldo_update, hdmi_rcv, NA, NA, NA, NA, NA), + PINGROUP(126, gcc_vtt, NA, NA, NA, NA, NA, NA), + PINGROUP(127, gcc_obt, NA, NA, NA, NA, NA, NA), + PINGROUP(128, blsp_spi10_cs3, NA, NA, NA, NA, NA, NA), + PINGROUP(129, sata_act, NA, NA, NA, NA, NA, NA), + PINGROUP(130, uim, blsp_spi7, blsp_uart7, blsp_uim7, NA, NA, NA), + PINGROUP(131, uim, blsp_spi7, blsp_uart7, blsp_uim7, NA, NA, NA), + PINGROUP(132, uim, blsp_spi7, blsp_uart7, blsp_i2c7, NA, NA, NA), + PINGROUP(133, uim, blsp_spi7, blsp_uart7, blsp_i2c7, NA, NA, NA), + PINGROUP(134, hsic, NA, NA, NA, NA, NA, NA), + PINGROUP(135, hsic, NA, NA, NA, NA, NA, NA), + PINGROUP(136, spdif_tx, NA, NA, NA, NA, NA, NA), + PINGROUP(137, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(138, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(139, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(140, pci_e1_rst_n, pci_e1_rst, NA, NA, NA, NA, NA), + PINGROUP(141, pci_e1_clkreq_n, NA, NA, NA, NA, NA, NA), + PINGROUP(142, spdif_tx, NA, NA, NA, NA, NA, NA), + PINGROUP(143, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(144, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(145, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(146, sdc_emmc_mode, NA, NA, NA, NA, NA, NA), + + SDC_PINGROUP(sdc1_clk, 0x2044, 13, 6), + SDC_PINGROUP(sdc1_cmd, 0x2044, 11, 3), + SDC_PINGROUP(sdc1_data, 0x2044, 9, 0), + SDC_PINGROUP(sdc2_clk, 0x2048, 14, 6), + SDC_PINGROUP(sdc2_cmd, 0x2048, 11, 3), + SDC_PINGROUP(sdc2_data, 0x2048, 9, 0), +}; + +#define NUM_GPIO_PINGROUPS 147 + +static const struct msm_pinctrl_soc_data apq8084_pinctrl = { + .pins = apq8084_pins, + .npins = ARRAY_SIZE(apq8084_pins), + .functions = apq8084_functions, + .nfunctions = ARRAY_SIZE(apq8084_functions), + .groups = apq8084_groups, + .ngroups = ARRAY_SIZE(apq8084_groups), + .ngpios = NUM_GPIO_PINGROUPS, +}; + +static int apq8084_pinctrl_probe(struct platform_device *pdev) +{ + return msm_pinctrl_probe(pdev, &apq8084_pinctrl); +} + +static const struct of_device_id apq8084_pinctrl_of_match[] = { + { .compatible = "qcom,apq8084-pinctrl", }, + { }, +}; + +static struct platform_driver apq8084_pinctrl_driver = { + .driver = { + .name = "apq8084-pinctrl", + .of_match_table = apq8084_pinctrl_of_match, + }, + .probe = apq8084_pinctrl_probe, + .remove = msm_pinctrl_remove, +}; + +static int __init apq8084_pinctrl_init(void) +{ + return platform_driver_register(&apq8084_pinctrl_driver); +} +arch_initcall(apq8084_pinctrl_init); + +static void __exit apq8084_pinctrl_exit(void) +{ + platform_driver_unregister(&apq8084_pinctrl_driver); +} +module_exit(apq8084_pinctrl_exit); + +MODULE_DESCRIPTION("Qualcomm APQ8084 pinctrl driver"); +MODULE_LICENSE("GPL v2"); +MODULE_DEVICE_TABLE(of, apq8084_pinctrl_of_match); diff --git a/drivers/pinctrl/qcom/pinctrl-ipq4019.c b/drivers/pinctrl/qcom/pinctrl-ipq4019.c new file mode 100644 index 0000000000..1f7944dd82 --- /dev/null +++ b/drivers/pinctrl/qcom/pinctrl-ipq4019.c @@ -0,0 +1,730 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2015, The Linux Foundation. All rights reserved. + */ + +#include <linux/module.h> +#include <linux/of.h> +#include <linux/platform_device.h> + +#include "pinctrl-msm.h" + +static const struct pinctrl_pin_desc ipq4019_pins[] = { + PINCTRL_PIN(0, "GPIO_0"), + PINCTRL_PIN(1, "GPIO_1"), + PINCTRL_PIN(2, "GPIO_2"), + PINCTRL_PIN(3, "GPIO_3"), + PINCTRL_PIN(4, "GPIO_4"), + PINCTRL_PIN(5, "GPIO_5"), + PINCTRL_PIN(6, "GPIO_6"), + PINCTRL_PIN(7, "GPIO_7"), + PINCTRL_PIN(8, "GPIO_8"), + PINCTRL_PIN(9, "GPIO_9"), + PINCTRL_PIN(10, "GPIO_10"), + PINCTRL_PIN(11, "GPIO_11"), + PINCTRL_PIN(12, "GPIO_12"), + PINCTRL_PIN(13, "GPIO_13"), + PINCTRL_PIN(14, "GPIO_14"), + PINCTRL_PIN(15, "GPIO_15"), + PINCTRL_PIN(16, "GPIO_16"), + PINCTRL_PIN(17, "GPIO_17"), + PINCTRL_PIN(18, "GPIO_18"), + PINCTRL_PIN(19, "GPIO_19"), + PINCTRL_PIN(20, "GPIO_20"), + PINCTRL_PIN(21, "GPIO_21"), + PINCTRL_PIN(22, "GPIO_22"), + PINCTRL_PIN(23, "GPIO_23"), + PINCTRL_PIN(24, "GPIO_24"), + PINCTRL_PIN(25, "GPIO_25"), + PINCTRL_PIN(26, "GPIO_26"), + PINCTRL_PIN(27, "GPIO_27"), + PINCTRL_PIN(28, "GPIO_28"), + PINCTRL_PIN(29, "GPIO_29"), + PINCTRL_PIN(30, "GPIO_30"), + PINCTRL_PIN(31, "GPIO_31"), + PINCTRL_PIN(32, "GPIO_32"), + PINCTRL_PIN(33, "GPIO_33"), + PINCTRL_PIN(34, "GPIO_34"), + PINCTRL_PIN(35, "GPIO_35"), + PINCTRL_PIN(36, "GPIO_36"), + PINCTRL_PIN(37, "GPIO_37"), + PINCTRL_PIN(38, "GPIO_38"), + PINCTRL_PIN(39, "GPIO_39"), + PINCTRL_PIN(40, "GPIO_40"), + PINCTRL_PIN(41, "GPIO_41"), + PINCTRL_PIN(42, "GPIO_42"), + PINCTRL_PIN(43, "GPIO_43"), + PINCTRL_PIN(44, "GPIO_44"), + PINCTRL_PIN(45, "GPIO_45"), + PINCTRL_PIN(46, "GPIO_46"), + PINCTRL_PIN(47, "GPIO_47"), + PINCTRL_PIN(48, "GPIO_48"), + PINCTRL_PIN(49, "GPIO_49"), + PINCTRL_PIN(50, "GPIO_50"), + PINCTRL_PIN(51, "GPIO_51"), + PINCTRL_PIN(52, "GPIO_52"), + PINCTRL_PIN(53, "GPIO_53"), + PINCTRL_PIN(54, "GPIO_54"), + PINCTRL_PIN(55, "GPIO_55"), + PINCTRL_PIN(56, "GPIO_56"), + PINCTRL_PIN(57, "GPIO_57"), + PINCTRL_PIN(58, "GPIO_58"), + PINCTRL_PIN(59, "GPIO_59"), + PINCTRL_PIN(60, "GPIO_60"), + PINCTRL_PIN(61, "GPIO_61"), + PINCTRL_PIN(62, "GPIO_62"), + PINCTRL_PIN(63, "GPIO_63"), + PINCTRL_PIN(64, "GPIO_64"), + PINCTRL_PIN(65, "GPIO_65"), + PINCTRL_PIN(66, "GPIO_66"), + PINCTRL_PIN(67, "GPIO_67"), + PINCTRL_PIN(68, "GPIO_68"), + PINCTRL_PIN(69, "GPIO_69"), + PINCTRL_PIN(70, "GPIO_70"), + PINCTRL_PIN(71, "GPIO_71"), + PINCTRL_PIN(72, "GPIO_72"), + PINCTRL_PIN(73, "GPIO_73"), + PINCTRL_PIN(74, "GPIO_74"), + PINCTRL_PIN(75, "GPIO_75"), + PINCTRL_PIN(76, "GPIO_76"), + PINCTRL_PIN(77, "GPIO_77"), + PINCTRL_PIN(78, "GPIO_78"), + PINCTRL_PIN(79, "GPIO_79"), + PINCTRL_PIN(80, "GPIO_80"), + PINCTRL_PIN(81, "GPIO_81"), + PINCTRL_PIN(82, "GPIO_82"), + PINCTRL_PIN(83, "GPIO_83"), + PINCTRL_PIN(84, "GPIO_84"), + PINCTRL_PIN(85, "GPIO_85"), + PINCTRL_PIN(86, "GPIO_86"), + PINCTRL_PIN(87, "GPIO_87"), + PINCTRL_PIN(88, "GPIO_88"), + PINCTRL_PIN(89, "GPIO_89"), + PINCTRL_PIN(90, "GPIO_90"), + PINCTRL_PIN(91, "GPIO_91"), + PINCTRL_PIN(92, "GPIO_92"), + PINCTRL_PIN(93, "GPIO_93"), + PINCTRL_PIN(94, "GPIO_94"), + PINCTRL_PIN(95, "GPIO_95"), + PINCTRL_PIN(96, "GPIO_96"), + PINCTRL_PIN(97, "GPIO_97"), + PINCTRL_PIN(98, "GPIO_98"), + PINCTRL_PIN(99, "GPIO_99"), +}; + +#define DECLARE_QCA_GPIO_PINS(pin) \ + static const unsigned int gpio##pin##_pins[] = { pin } +DECLARE_QCA_GPIO_PINS(0); +DECLARE_QCA_GPIO_PINS(1); +DECLARE_QCA_GPIO_PINS(2); +DECLARE_QCA_GPIO_PINS(3); +DECLARE_QCA_GPIO_PINS(4); +DECLARE_QCA_GPIO_PINS(5); +DECLARE_QCA_GPIO_PINS(6); +DECLARE_QCA_GPIO_PINS(7); +DECLARE_QCA_GPIO_PINS(8); +DECLARE_QCA_GPIO_PINS(9); +DECLARE_QCA_GPIO_PINS(10); +DECLARE_QCA_GPIO_PINS(11); +DECLARE_QCA_GPIO_PINS(12); +DECLARE_QCA_GPIO_PINS(13); +DECLARE_QCA_GPIO_PINS(14); +DECLARE_QCA_GPIO_PINS(15); +DECLARE_QCA_GPIO_PINS(16); +DECLARE_QCA_GPIO_PINS(17); +DECLARE_QCA_GPIO_PINS(18); +DECLARE_QCA_GPIO_PINS(19); +DECLARE_QCA_GPIO_PINS(20); +DECLARE_QCA_GPIO_PINS(21); +DECLARE_QCA_GPIO_PINS(22); +DECLARE_QCA_GPIO_PINS(23); +DECLARE_QCA_GPIO_PINS(24); +DECLARE_QCA_GPIO_PINS(25); +DECLARE_QCA_GPIO_PINS(26); +DECLARE_QCA_GPIO_PINS(27); +DECLARE_QCA_GPIO_PINS(28); +DECLARE_QCA_GPIO_PINS(29); +DECLARE_QCA_GPIO_PINS(30); +DECLARE_QCA_GPIO_PINS(31); +DECLARE_QCA_GPIO_PINS(32); +DECLARE_QCA_GPIO_PINS(33); +DECLARE_QCA_GPIO_PINS(34); +DECLARE_QCA_GPIO_PINS(35); +DECLARE_QCA_GPIO_PINS(36); +DECLARE_QCA_GPIO_PINS(37); +DECLARE_QCA_GPIO_PINS(38); +DECLARE_QCA_GPIO_PINS(39); +DECLARE_QCA_GPIO_PINS(40); +DECLARE_QCA_GPIO_PINS(41); +DECLARE_QCA_GPIO_PINS(42); +DECLARE_QCA_GPIO_PINS(43); +DECLARE_QCA_GPIO_PINS(44); +DECLARE_QCA_GPIO_PINS(45); +DECLARE_QCA_GPIO_PINS(46); +DECLARE_QCA_GPIO_PINS(47); +DECLARE_QCA_GPIO_PINS(48); +DECLARE_QCA_GPIO_PINS(49); +DECLARE_QCA_GPIO_PINS(50); +DECLARE_QCA_GPIO_PINS(51); +DECLARE_QCA_GPIO_PINS(52); +DECLARE_QCA_GPIO_PINS(53); +DECLARE_QCA_GPIO_PINS(54); +DECLARE_QCA_GPIO_PINS(55); +DECLARE_QCA_GPIO_PINS(56); +DECLARE_QCA_GPIO_PINS(57); +DECLARE_QCA_GPIO_PINS(58); +DECLARE_QCA_GPIO_PINS(59); +DECLARE_QCA_GPIO_PINS(60); +DECLARE_QCA_GPIO_PINS(61); +DECLARE_QCA_GPIO_PINS(62); +DECLARE_QCA_GPIO_PINS(63); +DECLARE_QCA_GPIO_PINS(64); +DECLARE_QCA_GPIO_PINS(65); +DECLARE_QCA_GPIO_PINS(66); +DECLARE_QCA_GPIO_PINS(67); +DECLARE_QCA_GPIO_PINS(68); +DECLARE_QCA_GPIO_PINS(69); +DECLARE_QCA_GPIO_PINS(70); +DECLARE_QCA_GPIO_PINS(71); +DECLARE_QCA_GPIO_PINS(72); +DECLARE_QCA_GPIO_PINS(73); +DECLARE_QCA_GPIO_PINS(74); +DECLARE_QCA_GPIO_PINS(75); +DECLARE_QCA_GPIO_PINS(76); +DECLARE_QCA_GPIO_PINS(77); +DECLARE_QCA_GPIO_PINS(78); +DECLARE_QCA_GPIO_PINS(79); +DECLARE_QCA_GPIO_PINS(80); +DECLARE_QCA_GPIO_PINS(81); +DECLARE_QCA_GPIO_PINS(82); +DECLARE_QCA_GPIO_PINS(83); +DECLARE_QCA_GPIO_PINS(84); +DECLARE_QCA_GPIO_PINS(85); +DECLARE_QCA_GPIO_PINS(86); +DECLARE_QCA_GPIO_PINS(87); +DECLARE_QCA_GPIO_PINS(88); +DECLARE_QCA_GPIO_PINS(89); +DECLARE_QCA_GPIO_PINS(90); +DECLARE_QCA_GPIO_PINS(91); +DECLARE_QCA_GPIO_PINS(92); +DECLARE_QCA_GPIO_PINS(93); +DECLARE_QCA_GPIO_PINS(94); +DECLARE_QCA_GPIO_PINS(95); +DECLARE_QCA_GPIO_PINS(96); +DECLARE_QCA_GPIO_PINS(97); +DECLARE_QCA_GPIO_PINS(98); +DECLARE_QCA_GPIO_PINS(99); + +#define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7, f8, f9, f10, f11, f12, f13, f14) \ + { \ + .grp = PINCTRL_PINGROUP("gpio" #id, \ + gpio##id##_pins, \ + ARRAY_SIZE(gpio##id##_pins)), \ + .funcs = (int[]){ \ + qca_mux_gpio, /* gpio mode */ \ + qca_mux_##f1, \ + qca_mux_##f2, \ + qca_mux_##f3, \ + qca_mux_##f4, \ + qca_mux_##f5, \ + qca_mux_##f6, \ + qca_mux_##f7, \ + qca_mux_##f8, \ + qca_mux_##f9, \ + qca_mux_##f10, \ + qca_mux_##f11, \ + qca_mux_##f12, \ + qca_mux_##f13, \ + qca_mux_##f14 \ + }, \ + .nfuncs = 15, \ + .ctl_reg = 0x0 + 0x1000 * id, \ + .io_reg = 0x4 + 0x1000 * id, \ + .intr_cfg_reg = 0x8 + 0x1000 * id, \ + .intr_status_reg = 0xc + 0x1000 * id, \ + .intr_target_reg = 0x8 + 0x1000 * id, \ + .mux_bit = 2, \ + .pull_bit = 0, \ + .drv_bit = 6, \ + .od_bit = 12, \ + .oe_bit = 9, \ + .in_bit = 0, \ + .out_bit = 1, \ + .intr_enable_bit = 0, \ + .intr_status_bit = 0, \ + .intr_target_bit = 5, \ + .intr_raw_status_bit = 4, \ + .intr_polarity_bit = 1, \ + .intr_detection_bit = 2, \ + .intr_detection_width = 2, \ + } + + +enum ipq4019_functions { + qca_mux_gpio, + qca_mux_aud_pin, + qca_mux_audio_pwm, + qca_mux_blsp_i2c0, + qca_mux_blsp_i2c1, + qca_mux_blsp_spi0, + qca_mux_blsp_spi1, + qca_mux_blsp_uart0, + qca_mux_blsp_uart1, + qca_mux_chip_rst, + qca_mux_i2s_rx, + qca_mux_i2s_spdif_in, + qca_mux_i2s_spdif_out, + qca_mux_i2s_td, + qca_mux_i2s_tx, + qca_mux_jtag, + qca_mux_led0, + qca_mux_led1, + qca_mux_led2, + qca_mux_led3, + qca_mux_led4, + qca_mux_led5, + qca_mux_led6, + qca_mux_led7, + qca_mux_led8, + qca_mux_led9, + qca_mux_led10, + qca_mux_led11, + qca_mux_mdc, + qca_mux_mdio, + qca_mux_pcie, + qca_mux_pmu, + qca_mux_prng_rosc, + qca_mux_qpic, + qca_mux_rgmii, + qca_mux_rmii, + qca_mux_sdio, + qca_mux_smart0, + qca_mux_smart1, + qca_mux_smart2, + qca_mux_smart3, + qca_mux_tm, + qca_mux_wifi0, + qca_mux_wifi1, + qca_mux_NA, +}; + +static const char * const gpio_groups[] = { + "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7", + "gpio8", "gpio9", "gpio10", "gpio11", "gpio12", "gpio13", "gpio14", + "gpio15", "gpio16", "gpio17", "gpio18", "gpio19", "gpio20", "gpio21", + "gpio22", "gpio23", "gpio24", "gpio25", "gpio26", "gpio27", "gpio28", + "gpio29", "gpio30", "gpio31", "gpio32", "gpio33", "gpio34", "gpio35", + "gpio36", "gpio37", "gpio38", "gpio39", "gpio40", "gpio41", "gpio42", + "gpio43", "gpio44", "gpio45", "gpio46", "gpio47", "gpio48", "gpio49", + "gpio50", "gpio51", "gpio52", "gpio53", "gpio54", "gpio55", "gpio56", + "gpio57", "gpio58", "gpio59", "gpio60", "gpio61", "gpio62", "gpio63", + "gpio64", "gpio65", "gpio66", "gpio67", "gpio68", "gpio69", "gpio70", + "gpio71", "gpio72", "gpio73", "gpio74", "gpio75", "gpio76", "gpio77", + "gpio78", "gpio79", "gpio80", "gpio81", "gpio82", "gpio83", "gpio84", + "gpio85", "gpio86", "gpio87", "gpio88", "gpio89", "gpio90", "gpio91", + "gpio92", "gpio93", "gpio94", "gpio95", "gpio96", "gpio97", "gpio98", + "gpio99", +}; +static const char * const aud_pin_groups[] = { + "gpio48", "gpio49", "gpio50", "gpio51", +}; +static const char * const audio_pwm_groups[] = { + "gpio30", "gpio31", "gpio32", "gpio33", "gpio64", "gpio65", "gpio66", + "gpio67", +}; +static const char * const blsp_i2c0_groups[] = { + "gpio10", "gpio11", "gpio20", "gpio21", "gpio58", "gpio59", +}; +static const char * const blsp_i2c1_groups[] = { + "gpio12", "gpio13", "gpio34", "gpio35", +}; +static const char * const blsp_spi0_groups[] = { + "gpio12", "gpio13", "gpio14", "gpio15", "gpio45", "gpio54", "gpio55", + "gpio56", "gpio57", +}; +static const char * const blsp_spi1_groups[] = { + "gpio44", "gpio45", "gpio46", "gpio47", +}; +static const char * const blsp_uart0_groups[] = { + "gpio16", "gpio17", "gpio60", "gpio61", +}; +static const char * const blsp_uart1_groups[] = { + "gpio8", "gpio9", "gpio10", "gpio11", +}; +static const char * const chip_rst_groups[] = { + "gpio62", +}; +static const char * const i2s_rx_groups[] = { + "gpio0", "gpio1", "gpio2", "gpio20", "gpio21", "gpio22", "gpio23", + "gpio58", "gpio60", "gpio61", "gpio63", +}; +static const char * const i2s_spdif_in_groups[] = { + "gpio34", "gpio59", "gpio63", +}; +static const char * const i2s_spdif_out_groups[] = { + "gpio35", "gpio62", "gpio63", +}; +static const char * const i2s_td_groups[] = { + "gpio27", "gpio28", "gpio29", "gpio54", "gpio55", "gpio56", "gpio63", +}; +static const char * const i2s_tx_groups[] = { + "gpio24", "gpio25", "gpio26", "gpio52", "gpio53", "gpio57", "gpio60", + "gpio61", +}; +static const char * const jtag_groups[] = { + "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", +}; +static const char * const led0_groups[] = { + "gpio16", "gpio36", "gpio60", +}; +static const char * const led1_groups[] = { + "gpio17", "gpio37", "gpio61", +}; +static const char * const led2_groups[] = { + "gpio36", "gpio38", "gpio58", +}; +static const char * const led3_groups[] = { + "gpio39", +}; +static const char * const led4_groups[] = { + "gpio40", +}; +static const char * const led5_groups[] = { + "gpio44", +}; +static const char * const led6_groups[] = { + "gpio45", +}; +static const char * const led7_groups[] = { + "gpio46", +}; +static const char * const led8_groups[] = { + "gpio47", +}; +static const char * const led9_groups[] = { + "gpio48", +}; +static const char * const led10_groups[] = { + "gpio49", +}; +static const char * const led11_groups[] = { + "gpio50", +}; +static const char * const mdc_groups[] = { + "gpio7", "gpio52", +}; +static const char * const mdio_groups[] = { + "gpio6", "gpio53", +}; +static const char * const pcie_groups[] = { + "gpio39", "gpio52", +}; +static const char * const pmu_groups[] = { + "gpio54", "gpio55", +}; +static const char * const prng_rosc_groups[] = { + "gpio53", +}; +static const char * const qpic_groups[] = { + "gpio52", "gpio53", "gpio54", "gpio55", "gpio56", "gpio57", "gpio58", + "gpio59", "gpio60", "gpio61", "gpio62", "gpio63", "gpio64", "gpio65", + "gpio66", "gpio67", "gpio68", "gpio69", +}; +static const char * const rgmii_groups[] = { + "gpio22", "gpio23", "gpio24", "gpio25", "gpio26", "gpio27", "gpio28", + "gpio29", "gpio30", "gpio31", "gpio32", "gpio33", +}; +static const char * const rmii_groups[] = { + "gpio36", "gpio37", "gpio38", "gpio39", "gpio40", "gpio41", "gpio42", + "gpio43", "gpio44", "gpio45", "gpio46", "gpio47", "gpio48", "gpio49", + "gpio50", "gpio51", +}; +static const char * const sdio_groups[] = { + "gpio23", "gpio24", "gpio25", "gpio26", "gpio27", "gpio28", "gpio29", + "gpio30", "gpio31", "gpio32", +}; +static const char * const smart0_groups[] = { + "gpio0", "gpio1", "gpio2", "gpio5", "gpio44", "gpio45", "gpio46", + "gpio47", +}; +static const char * const smart1_groups[] = { + "gpio8", "gpio9", "gpio16", "gpio17", "gpio58", "gpio59", "gpio60", + "gpio61", +}; +static const char * const smart2_groups[] = { + "gpio40", "gpio41", "gpio48", "gpio49", +}; +static const char * const smart3_groups[] = { + "gpio58", "gpio59", "gpio60", "gpio61", +}; +static const char * const tm_groups[] = { + "gpio52", "gpio53", "gpio54", "gpio55", "gpio56", "gpio57", "gpio58", + "gpio59", "gpio60", "gpio61", "gpio62", "gpio63", +}; +static const char * const wifi0_groups[] = { + "gpio37", "gpio40", "gpio41", "gpio42", "gpio50", "gpio51", "gpio52", + "gpio53", "gpio56", "gpio57", "gpio58", "gpio98", +}; +static const char * const wifi1_groups[] = { + "gpio37", "gpio40", "gpio41", "gpio43", "gpio50", "gpio51", "gpio52", + "gpio53", "gpio56", "gpio57", "gpio58", "gpio98", +}; + +static const struct pinfunction ipq4019_functions[] = { + QCA_PIN_FUNCTION(aud_pin), + QCA_PIN_FUNCTION(audio_pwm), + QCA_PIN_FUNCTION(blsp_i2c0), + QCA_PIN_FUNCTION(blsp_i2c1), + QCA_PIN_FUNCTION(blsp_spi0), + QCA_PIN_FUNCTION(blsp_spi1), + QCA_PIN_FUNCTION(blsp_uart0), + QCA_PIN_FUNCTION(blsp_uart1), + QCA_PIN_FUNCTION(chip_rst), + QCA_PIN_FUNCTION(gpio), + QCA_PIN_FUNCTION(i2s_rx), + QCA_PIN_FUNCTION(i2s_spdif_in), + QCA_PIN_FUNCTION(i2s_spdif_out), + QCA_PIN_FUNCTION(i2s_td), + QCA_PIN_FUNCTION(i2s_tx), + QCA_PIN_FUNCTION(jtag), + QCA_PIN_FUNCTION(led0), + QCA_PIN_FUNCTION(led1), + QCA_PIN_FUNCTION(led2), + QCA_PIN_FUNCTION(led3), + QCA_PIN_FUNCTION(led4), + QCA_PIN_FUNCTION(led5), + QCA_PIN_FUNCTION(led6), + QCA_PIN_FUNCTION(led7), + QCA_PIN_FUNCTION(led8), + QCA_PIN_FUNCTION(led9), + QCA_PIN_FUNCTION(led10), + QCA_PIN_FUNCTION(led11), + QCA_PIN_FUNCTION(mdc), + QCA_PIN_FUNCTION(mdio), + QCA_PIN_FUNCTION(pcie), + QCA_PIN_FUNCTION(pmu), + QCA_PIN_FUNCTION(prng_rosc), + QCA_PIN_FUNCTION(qpic), + QCA_PIN_FUNCTION(rgmii), + QCA_PIN_FUNCTION(rmii), + QCA_PIN_FUNCTION(sdio), + QCA_PIN_FUNCTION(smart0), + QCA_PIN_FUNCTION(smart1), + QCA_PIN_FUNCTION(smart2), + QCA_PIN_FUNCTION(smart3), + QCA_PIN_FUNCTION(tm), + QCA_PIN_FUNCTION(wifi0), + QCA_PIN_FUNCTION(wifi1), +}; + +static const struct msm_pingroup ipq4019_groups[] = { + PINGROUP(0, jtag, smart0, i2s_rx, NA, NA, NA, NA, NA, NA, NA, NA, NA, + NA, NA), + PINGROUP(1, jtag, smart0, i2s_rx, NA, NA, NA, NA, NA, NA, NA, NA, NA, + NA, NA), + PINGROUP(2, jtag, smart0, i2s_rx, NA, NA, NA, NA, NA, NA, NA, NA, NA, + NA, NA), + PINGROUP(3, jtag, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(4, jtag, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(5, jtag, smart0, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, + NA), + PINGROUP(6, mdio, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(7, mdc, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(8, blsp_uart1, NA, NA, smart1, NA, NA, NA, NA, NA, NA, NA, + NA, NA, NA), + PINGROUP(9, blsp_uart1, NA, NA, smart1, NA, NA, NA, NA, NA, NA, NA, + NA, NA, NA), + PINGROUP(10, blsp_uart1, NA, NA, blsp_i2c0, NA, NA, NA, NA, NA, NA, NA, + NA, NA, NA), + PINGROUP(11, blsp_uart1, NA, NA, blsp_i2c0, NA, NA, NA, NA, NA, NA, NA, + NA, NA, NA), + PINGROUP(12, blsp_spi0, blsp_i2c1, NA, NA, NA, NA, NA, NA, NA, NA, NA, + NA, NA, NA), + PINGROUP(13, blsp_spi0, blsp_i2c1, NA, NA, NA, NA, NA, NA, NA, NA, NA, + NA, NA, NA), + PINGROUP(14, blsp_spi0, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, + NA), + PINGROUP(15, blsp_spi0, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, + NA), + PINGROUP(16, blsp_uart0, led0, smart1, NA, NA, NA, NA, NA, NA, NA, NA, + NA, NA, NA), + PINGROUP(17, blsp_uart0, led1, smart1, NA, NA, NA, NA, NA, NA, NA, NA, + NA, NA, NA), + PINGROUP(18, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(19, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(20, blsp_i2c0, i2s_rx, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, + NA, NA), + PINGROUP(21, blsp_i2c0, i2s_rx, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, + NA, NA), + PINGROUP(22, rgmii, i2s_rx, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, + NA), + PINGROUP(23, sdio, rgmii, i2s_rx, NA, NA, NA, NA, NA, NA, NA, NA, NA, + NA, NA), + PINGROUP(24, sdio, rgmii, i2s_tx, NA, NA, NA, NA, NA, NA, NA, NA, NA, + NA, NA), + PINGROUP(25, sdio, rgmii, i2s_tx, NA, NA, NA, NA, NA, NA, NA, NA, NA, + NA, NA), + PINGROUP(26, sdio, rgmii, i2s_tx, NA, NA, NA, NA, NA, NA, NA, NA, NA, + NA, NA), + PINGROUP(27, sdio, rgmii, i2s_td, NA, NA, NA, NA, NA, NA, NA, NA, NA, + NA, NA), + PINGROUP(28, sdio, rgmii, i2s_td, NA, NA, NA, NA, NA, NA, NA, NA, NA, + NA, NA), + PINGROUP(29, sdio, rgmii, i2s_td, NA, NA, NA, NA, NA, NA, NA, NA, NA, + NA, NA), + PINGROUP(30, sdio, rgmii, audio_pwm, NA, NA, NA, NA, NA, NA, NA, NA, + NA, NA, NA), + PINGROUP(31, sdio, rgmii, audio_pwm, NA, NA, NA, NA, NA, NA, NA, NA, + NA, NA, NA), + PINGROUP(32, sdio, rgmii, audio_pwm, NA, NA, NA, NA, NA, NA, NA, NA, + NA, NA, NA), + PINGROUP(33, rgmii, audio_pwm, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, + NA, NA), + PINGROUP(34, blsp_i2c1, i2s_spdif_in, NA, NA, NA, NA, NA, NA, NA, NA, + NA, NA, NA, NA), + PINGROUP(35, blsp_i2c1, i2s_spdif_out, NA, NA, NA, NA, NA, NA, NA, NA, + NA, NA, NA, NA), + PINGROUP(36, rmii, led2, led0, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, + NA), + PINGROUP(37, rmii, wifi0, wifi1, led1, NA, NA, NA, NA, NA, NA, NA, NA, + NA, NA), + PINGROUP(38, rmii, led2, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, + NA), + PINGROUP(39, rmii, pcie, led3, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, + NA), + PINGROUP(40, rmii, wifi0, wifi1, smart2, led4, NA, NA, NA, NA, NA, NA, + NA, NA, NA), + PINGROUP(41, rmii, wifi0, wifi1, smart2, NA, NA, NA, NA, NA, NA, NA, + NA, NA, NA), + PINGROUP(42, rmii, wifi0, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, + NA), + PINGROUP(43, rmii, wifi1, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, + NA), + PINGROUP(44, rmii, blsp_spi1, smart0, led5, NA, NA, NA, NA, NA, NA, NA, + NA, NA, NA), + PINGROUP(45, rmii, blsp_spi1, blsp_spi0, smart0, led6, NA, NA, NA, NA, + NA, NA, NA, NA, NA), + PINGROUP(46, rmii, blsp_spi1, smart0, led7, NA, NA, NA, NA, NA, NA, NA, + NA, NA, NA), + PINGROUP(47, rmii, blsp_spi1, smart0, led8, NA, NA, NA, NA, NA, NA, NA, + NA, NA, NA), + PINGROUP(48, rmii, aud_pin, smart2, led9, NA, NA, NA, NA, NA, NA, NA, + NA, NA, NA), + PINGROUP(49, rmii, aud_pin, smart2, led10, NA, NA, NA, NA, NA, NA, NA, + NA, NA, NA), + PINGROUP(50, rmii, aud_pin, wifi0, wifi1, led11, NA, NA, NA, NA, NA, + NA, NA, NA, NA), + PINGROUP(51, rmii, aud_pin, wifi0, wifi1, NA, NA, NA, NA, NA, NA, NA, + NA, NA, NA), + PINGROUP(52, qpic, mdc, pcie, i2s_tx, NA, NA, NA, tm, wifi0, wifi1, NA, + NA, NA, NA), + PINGROUP(53, qpic, mdio, i2s_tx, prng_rosc, NA, tm, wifi0, wifi1, NA, + NA, NA, NA, NA, NA), + PINGROUP(54, qpic, blsp_spi0, i2s_td, NA, pmu, NA, NA, NA, tm, NA, NA, + NA, NA, NA), + PINGROUP(55, qpic, blsp_spi0, i2s_td, NA, pmu, NA, NA, NA, tm, NA, NA, + NA, NA, NA), + PINGROUP(56, qpic, blsp_spi0, i2s_td, NA, NA, tm, wifi0, wifi1, NA, NA, + NA, NA, NA, NA), + PINGROUP(57, qpic, blsp_spi0, i2s_tx, NA, NA, tm, wifi0, wifi1, NA, NA, + NA, NA, NA, NA), + PINGROUP(58, qpic, led2, blsp_i2c0, smart3, smart1, i2s_rx, NA, NA, tm, + wifi0, wifi1, NA, NA, NA), + PINGROUP(59, qpic, blsp_i2c0, smart3, smart1, i2s_spdif_in, NA, NA, NA, + NA, NA, tm, NA, NA, NA), + PINGROUP(60, qpic, blsp_uart0, smart1, smart3, led0, i2s_tx, i2s_rx, + NA, NA, NA, NA, NA, tm, NA), + PINGROUP(61, qpic, blsp_uart0, smart1, smart3, led1, i2s_tx, i2s_rx, + NA, NA, NA, NA, NA, tm, NA), + PINGROUP(62, qpic, chip_rst, NA, NA, i2s_spdif_out, NA, NA, NA, NA, NA, + tm, NA, NA, NA), + PINGROUP(63, qpic, NA, NA, NA, i2s_td, i2s_rx, i2s_spdif_out, + i2s_spdif_in, NA, NA, NA, NA, tm, NA), + PINGROUP(64, qpic, audio_pwm, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, + NA, NA), + PINGROUP(65, qpic, audio_pwm, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, + NA, NA), + PINGROUP(66, qpic, audio_pwm, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, + NA, NA), + PINGROUP(67, qpic, audio_pwm, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, + NA, NA), + PINGROUP(68, qpic, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(69, qpic, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(70, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(71, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(72, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(73, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(74, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(75, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(76, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(77, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(78, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(79, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(80, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(81, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(82, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(83, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(84, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(85, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(86, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(87, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(88, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(89, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(90, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(91, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(92, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(93, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(94, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(95, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(96, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(97, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(98, wifi0, wifi1, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, + NA), + PINGROUP(99, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), +}; + +static const struct msm_pinctrl_soc_data ipq4019_pinctrl = { + .pins = ipq4019_pins, + .npins = ARRAY_SIZE(ipq4019_pins), + .functions = ipq4019_functions, + .nfunctions = ARRAY_SIZE(ipq4019_functions), + .groups = ipq4019_groups, + .ngroups = ARRAY_SIZE(ipq4019_groups), + .ngpios = 100, + .pull_no_keeper = true, +}; + +static int ipq4019_pinctrl_probe(struct platform_device *pdev) +{ + return msm_pinctrl_probe(pdev, &ipq4019_pinctrl); +} + +static const struct of_device_id ipq4019_pinctrl_of_match[] = { + { .compatible = "qcom,ipq4019-pinctrl", }, + { }, +}; + +static struct platform_driver ipq4019_pinctrl_driver = { + .driver = { + .name = "ipq4019-pinctrl", + .of_match_table = ipq4019_pinctrl_of_match, + }, + .probe = ipq4019_pinctrl_probe, + .remove = msm_pinctrl_remove, +}; + +static int __init ipq4019_pinctrl_init(void) +{ + return platform_driver_register(&ipq4019_pinctrl_driver); +} +arch_initcall(ipq4019_pinctrl_init); + +static void __exit ipq4019_pinctrl_exit(void) +{ + platform_driver_unregister(&ipq4019_pinctrl_driver); +} +module_exit(ipq4019_pinctrl_exit); + +MODULE_DESCRIPTION("Qualcomm ipq4019 pinctrl driver"); +MODULE_LICENSE("GPL v2"); +MODULE_DEVICE_TABLE(of, ipq4019_pinctrl_of_match); diff --git a/drivers/pinctrl/qcom/pinctrl-ipq5018.c b/drivers/pinctrl/qcom/pinctrl-ipq5018.c new file mode 100644 index 0000000000..e2951f81c3 --- /dev/null +++ b/drivers/pinctrl/qcom/pinctrl-ipq5018.c @@ -0,0 +1,773 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2019-2021, 2023 The Linux Foundation. All rights reserved. + */ + +#include <linux/module.h> +#include <linux/mod_devicetable.h> +#include <linux/platform_device.h> + +#include "pinctrl-msm.h" + +#define REG_SIZE 0x1000 +#define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7, f8, f9) \ + { \ + .grp = PINCTRL_PINGROUP("gpio" #id, \ + gpio##id##_pins, \ + ARRAY_SIZE(gpio##id##_pins)), \ + .funcs = (int[]){ \ + msm_mux_gpio, /* gpio mode */ \ + msm_mux_##f1, \ + msm_mux_##f2, \ + msm_mux_##f3, \ + msm_mux_##f4, \ + msm_mux_##f5, \ + msm_mux_##f6, \ + msm_mux_##f7, \ + msm_mux_##f8, \ + msm_mux_##f9 \ + }, \ + .nfuncs = 10, \ + .ctl_reg = REG_SIZE * id, \ + .io_reg = 0x4 + REG_SIZE * id, \ + .intr_cfg_reg = 0x8 + REG_SIZE * id, \ + .intr_status_reg = 0xc + REG_SIZE * id, \ + .intr_target_reg = 0x8 + REG_SIZE * id, \ + .mux_bit = 2, \ + .pull_bit = 0, \ + .drv_bit = 6, \ + .oe_bit = 9, \ + .in_bit = 0, \ + .out_bit = 1, \ + .intr_enable_bit = 0, \ + .intr_status_bit = 0, \ + .intr_target_bit = 5, \ + .intr_target_kpss_val = 3, \ + .intr_raw_status_bit = 4, \ + .intr_polarity_bit = 1, \ + .intr_detection_bit = 2, \ + .intr_detection_width = 2, \ + } + +static const struct pinctrl_pin_desc ipq5018_pins[] = { + PINCTRL_PIN(0, "GPIO_0"), + PINCTRL_PIN(1, "GPIO_1"), + PINCTRL_PIN(2, "GPIO_2"), + PINCTRL_PIN(3, "GPIO_3"), + PINCTRL_PIN(4, "GPIO_4"), + PINCTRL_PIN(5, "GPIO_5"), + PINCTRL_PIN(6, "GPIO_6"), + PINCTRL_PIN(7, "GPIO_7"), + PINCTRL_PIN(8, "GPIO_8"), + PINCTRL_PIN(9, "GPIO_9"), + PINCTRL_PIN(10, "GPIO_10"), + PINCTRL_PIN(11, "GPIO_11"), + PINCTRL_PIN(12, "GPIO_12"), + PINCTRL_PIN(13, "GPIO_13"), + PINCTRL_PIN(14, "GPIO_14"), + PINCTRL_PIN(15, "GPIO_15"), + PINCTRL_PIN(16, "GPIO_16"), + PINCTRL_PIN(17, "GPIO_17"), + PINCTRL_PIN(18, "GPIO_18"), + PINCTRL_PIN(19, "GPIO_19"), + PINCTRL_PIN(20, "GPIO_20"), + PINCTRL_PIN(21, "GPIO_21"), + PINCTRL_PIN(22, "GPIO_22"), + PINCTRL_PIN(23, "GPIO_23"), + PINCTRL_PIN(24, "GPIO_24"), + PINCTRL_PIN(25, "GPIO_25"), + PINCTRL_PIN(26, "GPIO_26"), + PINCTRL_PIN(27, "GPIO_27"), + PINCTRL_PIN(28, "GPIO_28"), + PINCTRL_PIN(29, "GPIO_29"), + PINCTRL_PIN(30, "GPIO_30"), + PINCTRL_PIN(31, "GPIO_31"), + PINCTRL_PIN(32, "GPIO_32"), + PINCTRL_PIN(33, "GPIO_33"), + PINCTRL_PIN(34, "GPIO_34"), + PINCTRL_PIN(35, "GPIO_35"), + PINCTRL_PIN(36, "GPIO_36"), + PINCTRL_PIN(37, "GPIO_37"), + PINCTRL_PIN(38, "GPIO_38"), + PINCTRL_PIN(39, "GPIO_39"), + PINCTRL_PIN(40, "GPIO_40"), + PINCTRL_PIN(41, "GPIO_41"), + PINCTRL_PIN(42, "GPIO_42"), + PINCTRL_PIN(43, "GPIO_43"), + PINCTRL_PIN(44, "GPIO_44"), + PINCTRL_PIN(45, "GPIO_45"), + PINCTRL_PIN(46, "GPIO_46"), +}; + +#define DECLARE_MSM_GPIO_PINS(pin) \ + static const unsigned int gpio##pin##_pins[] = { pin } +DECLARE_MSM_GPIO_PINS(0); +DECLARE_MSM_GPIO_PINS(1); +DECLARE_MSM_GPIO_PINS(2); +DECLARE_MSM_GPIO_PINS(3); +DECLARE_MSM_GPIO_PINS(4); +DECLARE_MSM_GPIO_PINS(5); +DECLARE_MSM_GPIO_PINS(6); +DECLARE_MSM_GPIO_PINS(7); +DECLARE_MSM_GPIO_PINS(8); +DECLARE_MSM_GPIO_PINS(9); +DECLARE_MSM_GPIO_PINS(10); +DECLARE_MSM_GPIO_PINS(11); +DECLARE_MSM_GPIO_PINS(12); +DECLARE_MSM_GPIO_PINS(13); +DECLARE_MSM_GPIO_PINS(14); +DECLARE_MSM_GPIO_PINS(15); +DECLARE_MSM_GPIO_PINS(16); +DECLARE_MSM_GPIO_PINS(17); +DECLARE_MSM_GPIO_PINS(18); +DECLARE_MSM_GPIO_PINS(19); +DECLARE_MSM_GPIO_PINS(20); +DECLARE_MSM_GPIO_PINS(21); +DECLARE_MSM_GPIO_PINS(22); +DECLARE_MSM_GPIO_PINS(23); +DECLARE_MSM_GPIO_PINS(24); +DECLARE_MSM_GPIO_PINS(25); +DECLARE_MSM_GPIO_PINS(26); +DECLARE_MSM_GPIO_PINS(27); +DECLARE_MSM_GPIO_PINS(28); +DECLARE_MSM_GPIO_PINS(29); +DECLARE_MSM_GPIO_PINS(30); +DECLARE_MSM_GPIO_PINS(31); +DECLARE_MSM_GPIO_PINS(32); +DECLARE_MSM_GPIO_PINS(33); +DECLARE_MSM_GPIO_PINS(34); +DECLARE_MSM_GPIO_PINS(35); +DECLARE_MSM_GPIO_PINS(36); +DECLARE_MSM_GPIO_PINS(37); +DECLARE_MSM_GPIO_PINS(38); +DECLARE_MSM_GPIO_PINS(39); +DECLARE_MSM_GPIO_PINS(40); +DECLARE_MSM_GPIO_PINS(41); +DECLARE_MSM_GPIO_PINS(42); +DECLARE_MSM_GPIO_PINS(43); +DECLARE_MSM_GPIO_PINS(44); +DECLARE_MSM_GPIO_PINS(45); +DECLARE_MSM_GPIO_PINS(46); + +enum ipq5018_functions { + msm_mux_atest_char, + msm_mux_audio_pdm0, + msm_mux_audio_pdm1, + msm_mux_audio_rxbclk, + msm_mux_audio_rxd, + msm_mux_audio_rxfsync, + msm_mux_audio_rxmclk, + msm_mux_audio_txbclk, + msm_mux_audio_txd, + msm_mux_audio_txfsync, + msm_mux_audio_txmclk, + msm_mux_blsp0_i2c, + msm_mux_blsp0_spi, + msm_mux_blsp0_uart0, + msm_mux_blsp0_uart1, + msm_mux_blsp1_i2c0, + msm_mux_blsp1_i2c1, + msm_mux_blsp1_spi0, + msm_mux_blsp1_spi1, + msm_mux_blsp1_uart0, + msm_mux_blsp1_uart1, + msm_mux_blsp1_uart2, + msm_mux_blsp2_i2c0, + msm_mux_blsp2_i2c1, + msm_mux_blsp2_spi, + msm_mux_blsp2_spi0, + msm_mux_blsp2_spi1, + msm_mux_btss, + msm_mux_burn0, + msm_mux_burn1, + msm_mux_cri_trng, + msm_mux_cri_trng0, + msm_mux_cri_trng1, + msm_mux_cxc_clk, + msm_mux_cxc_data, + msm_mux_dbg_out, + msm_mux_eud_gpio, + msm_mux_gcc_plltest, + msm_mux_gcc_tlmm, + msm_mux_gpio, + msm_mux_led0, + msm_mux_led2, + msm_mux_mac0, + msm_mux_mac1, + msm_mux_mdc, + msm_mux_mdio, + msm_mux_pcie0_clk, + msm_mux_pcie0_wake, + msm_mux_pcie1_clk, + msm_mux_pcie1_wake, + msm_mux_pll_test, + msm_mux_prng_rosc, + msm_mux_pwm0, + msm_mux_pwm1, + msm_mux_pwm2, + msm_mux_pwm3, + msm_mux_qdss_cti_trig_in_a0, + msm_mux_qdss_cti_trig_in_a1, + msm_mux_qdss_cti_trig_in_b0, + msm_mux_qdss_cti_trig_in_b1, + msm_mux_qdss_cti_trig_out_a0, + msm_mux_qdss_cti_trig_out_a1, + msm_mux_qdss_cti_trig_out_b0, + msm_mux_qdss_cti_trig_out_b1, + msm_mux_qdss_traceclk_a, + msm_mux_qdss_traceclk_b, + msm_mux_qdss_tracectl_a, + msm_mux_qdss_tracectl_b, + msm_mux_qdss_tracedata_a, + msm_mux_qdss_tracedata_b, + msm_mux_qspi_clk, + msm_mux_qspi_cs, + msm_mux_qspi_data, + msm_mux_reset_out, + msm_mux_sdc1_clk, + msm_mux_sdc1_cmd, + msm_mux_sdc1_data, + msm_mux_wci_txd, + msm_mux_wci_rxd, + msm_mux_wsa_swrm, + msm_mux_wsi_clk3, + msm_mux_wsi_data3, + msm_mux_wsis_reset, + msm_mux_xfem, + msm_mux__, +}; + +static const char * const atest_char_groups[] = { + "gpio0", "gpio1", "gpio2", "gpio3", "gpio37", +}; + +static const char * const wci_txd_groups[] = { + "gpio0", "gpio1", "gpio2", "gpio3", + "gpio42", "gpio43", "gpio44", "gpio45", +}; + +static const char * const wci_rxd_groups[] = { + "gpio0", "gpio1", "gpio2", "gpio3", + "gpio42", "gpio43", "gpio44", "gpio45", +}; + +static const char * const xfem_groups[] = { + "gpio0", "gpio1", "gpio2", "gpio3", + "gpio42", "gpio43", "gpio44", "gpio45", +}; + +static const char * const qdss_cti_trig_out_a0_groups[] = { + "gpio0", +}; + +static const char * const qdss_cti_trig_in_a0_groups[] = { + "gpio1", +}; + +static const char * const qdss_cti_trig_out_a1_groups[] = { + "gpio2", +}; + +static const char * const qdss_cti_trig_in_a1_groups[] = { + "gpio3", +}; + +static const char * const sdc1_data_groups[] = { + "gpio4", "gpio5", "gpio6", "gpio7", +}; + +static const char * const qspi_data_groups[] = { + "gpio4", + "gpio5", + "gpio6", + "gpio7", +}; + +static const char * const blsp1_spi1_groups[] = { + "gpio4", "gpio5", "gpio6", "gpio7", +}; + +static const char * const btss_groups[] = { + "gpio4", "gpio5", "gpio6", "gpio7", "gpio8", "gpio17", "gpio18", + "gpio19", "gpio23", "gpio24", "gpio25", "gpio26", "gpio27", "gpio28", +}; + +static const char * const dbg_out_groups[] = { + "gpio4", +}; + +static const char * const qdss_traceclk_a_groups[] = { + "gpio4", +}; + +static const char * const burn0_groups[] = { + "gpio4", +}; + +static const char * const cxc_clk_groups[] = { + "gpio5", +}; + +static const char * const blsp1_i2c1_groups[] = { + "gpio5", "gpio6", +}; + +static const char * const qdss_tracectl_a_groups[] = { + "gpio5", +}; + +static const char * const burn1_groups[] = { + "gpio5", +}; + +static const char * const cxc_data_groups[] = { + "gpio6", +}; + +static const char * const qdss_tracedata_a_groups[] = { + "gpio6", "gpio7", "gpio8", "gpio9", "gpio10", "gpio11", "gpio12", + "gpio13", "gpio14", "gpio15", "gpio16", "gpio17", "gpio18", "gpio19", + "gpio20", "gpio21", +}; + +static const char * const mac0_groups[] = { + "gpio7", +}; + +static const char * const sdc1_cmd_groups[] = { + "gpio8", +}; + +static const char * const qspi_cs_groups[] = { + "gpio8", +}; + +static const char * const mac1_groups[] = { + "gpio8", +}; + +static const char * const sdc1_clk_groups[] = { + "gpio9", +}; + +static const char * const qspi_clk_groups[] = { + "gpio9", +}; + +static const char * const blsp0_spi_groups[] = { + "gpio10", "gpio11", "gpio12", "gpio13", +}; + +static const char * const blsp1_uart0_groups[] = { + "gpio10", "gpio11", "gpio12", "gpio13", +}; + +static const char * const gcc_plltest_groups[] = { + "gpio10", "gpio12", +}; + +static const char * const gcc_tlmm_groups[] = { + "gpio11", +}; + +static const char * const blsp0_i2c_groups[] = { + "gpio12", "gpio13", +}; + +static const char * const pcie0_clk_groups[] = { + "gpio14", +}; + +static const char * const cri_trng0_groups[] = { + "gpio14", +}; + +static const char * const cri_trng1_groups[] = { + "gpio15", +}; + +static const char * const pcie0_wake_groups[] = { + "gpio16", +}; + +static const char * const cri_trng_groups[] = { + "gpio16", +}; + +static const char * const pcie1_clk_groups[] = { + "gpio17", +}; + +static const char * const prng_rosc_groups[] = { + "gpio17", +}; + +static const char * const blsp1_spi0_groups[] = { + "gpio18", "gpio19", "gpio20", "gpio21", +}; + +static const char * const pcie1_wake_groups[] = { + "gpio19", +}; + +static const char * const blsp1_i2c0_groups[] = { + "gpio19", "gpio20", +}; + +static const char * const blsp0_uart0_groups[] = { + "gpio20", "gpio21", +}; + +static const char * const pll_test_groups[] = { + "gpio22", +}; + +static const char * const eud_gpio_groups[] = { + "gpio22", "gpio31", "gpio32", "gpio33", "gpio34", "gpio35", +}; + +static const char * const audio_rxmclk_groups[] = { + "gpio23", "gpio23", +}; + +static const char * const audio_pdm0_groups[] = { + "gpio23", "gpio24", +}; + +static const char * const blsp2_spi1_groups[] = { + "gpio23", "gpio24", "gpio25", "gpio26", +}; + +static const char * const blsp1_uart2_groups[] = { + "gpio23", "gpio24", "gpio25", "gpio26", +}; + +static const char * const qdss_tracedata_b_groups[] = { + "gpio23", "gpio24", "gpio25", "gpio26", "gpio27", "gpio28", "gpio29", + "gpio30", "gpio31", "gpio32", "gpio33", "gpio34", "gpio35", "gpio36", + "gpio37", "gpio38", +}; + +static const char * const audio_rxbclk_groups[] = { + "gpio24", +}; + +static const char * const audio_rxfsync_groups[] = { + "gpio25", +}; + +static const char * const audio_pdm1_groups[] = { + "gpio25", "gpio26", +}; + +static const char * const blsp2_i2c1_groups[] = { + "gpio25", "gpio26", +}; + +static const char * const audio_rxd_groups[] = { + "gpio26", +}; + +static const char * const audio_txmclk_groups[] = { + "gpio27", "gpio27", +}; + +static const char * const wsa_swrm_groups[] = { + "gpio27", "gpio28", +}; + +static const char * const blsp2_spi_groups[] = { + "gpio27", +}; + +static const char * const audio_txbclk_groups[] = { + "gpio28", +}; + +static const char * const blsp0_uart1_groups[] = { + "gpio28", "gpio29", +}; + +static const char * const audio_txfsync_groups[] = { + "gpio29", +}; + +static const char * const audio_txd_groups[] = { + "gpio30", +}; + +static const char * const wsis_reset_groups[] = { + "gpio30", +}; + +static const char * const blsp2_spi0_groups[] = { + "gpio31", "gpio32", "gpio33", "gpio34", +}; + +static const char * const blsp1_uart1_groups[] = { + "gpio31", "gpio32", "gpio33", "gpio34", +}; + +static const char * const blsp2_i2c0_groups[] = { + "gpio33", "gpio34", +}; + +static const char * const mdc_groups[] = { + "gpio36", +}; + +static const char * const wsi_clk3_groups[] = { + "gpio36", +}; + +static const char * const mdio_groups[] = { + "gpio37", +}; + +static const char * const wsi_data3_groups[] = { + "gpio37", +}; + +static const char * const qdss_traceclk_b_groups[] = { + "gpio39", +}; + +static const char * const reset_out_groups[] = { + "gpio40", +}; + +static const char * const qdss_tracectl_b_groups[] = { + "gpio40", +}; + +static const char * const pwm0_groups[] = { + "gpio42", +}; + +static const char * const qdss_cti_trig_out_b0_groups[] = { + "gpio42", +}; + +static const char * const pwm1_groups[] = { + "gpio43", +}; + +static const char * const qdss_cti_trig_in_b0_groups[] = { + "gpio43", +}; + +static const char * const pwm2_groups[] = { + "gpio44", +}; + +static const char * const qdss_cti_trig_out_b1_groups[] = { + "gpio44", +}; + +static const char * const pwm3_groups[] = { + "gpio45", +}; + +static const char * const qdss_cti_trig_in_b1_groups[] = { + "gpio45", +}; + +static const char * const led0_groups[] = { + "gpio46", "gpio30", "gpio10", +}; + +static const char * const led2_groups[] = { + "gpio30", +}; + +static const char * const gpio_groups[] = { + "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7", + "gpio8", "gpio9", "gpio10", "gpio11", "gpio12", "gpio13", "gpio14", + "gpio15", "gpio16", "gpio17", "gpio18", "gpio19", "gpio20", "gpio21", + "gpio22", "gpio23", "gpio24", "gpio25", "gpio26", "gpio27", "gpio28", + "gpio29", "gpio30", "gpio31", "gpio32", "gpio33", "gpio34", "gpio35", + "gpio36", "gpio37", "gpio38", "gpio39", "gpio40", "gpio41", "gpio42", + "gpio43", "gpio44", "gpio45", "gpio46", +}; + +static const struct pinfunction ipq5018_functions[] = { + MSM_PIN_FUNCTION(atest_char), + MSM_PIN_FUNCTION(audio_pdm0), + MSM_PIN_FUNCTION(audio_pdm1), + MSM_PIN_FUNCTION(audio_rxbclk), + MSM_PIN_FUNCTION(audio_rxd), + MSM_PIN_FUNCTION(audio_rxfsync), + MSM_PIN_FUNCTION(audio_rxmclk), + MSM_PIN_FUNCTION(audio_txbclk), + MSM_PIN_FUNCTION(audio_txd), + MSM_PIN_FUNCTION(audio_txfsync), + MSM_PIN_FUNCTION(audio_txmclk), + MSM_PIN_FUNCTION(blsp0_i2c), + MSM_PIN_FUNCTION(blsp0_spi), + MSM_PIN_FUNCTION(blsp0_uart0), + MSM_PIN_FUNCTION(blsp0_uart1), + MSM_PIN_FUNCTION(blsp1_i2c0), + MSM_PIN_FUNCTION(blsp1_i2c1), + MSM_PIN_FUNCTION(blsp1_spi0), + MSM_PIN_FUNCTION(blsp1_spi1), + MSM_PIN_FUNCTION(blsp1_uart0), + MSM_PIN_FUNCTION(blsp1_uart1), + MSM_PIN_FUNCTION(blsp1_uart2), + MSM_PIN_FUNCTION(blsp2_i2c0), + MSM_PIN_FUNCTION(blsp2_i2c1), + MSM_PIN_FUNCTION(blsp2_spi), + MSM_PIN_FUNCTION(blsp2_spi0), + MSM_PIN_FUNCTION(blsp2_spi1), + MSM_PIN_FUNCTION(btss), + MSM_PIN_FUNCTION(burn0), + MSM_PIN_FUNCTION(burn1), + MSM_PIN_FUNCTION(cri_trng), + MSM_PIN_FUNCTION(cri_trng0), + MSM_PIN_FUNCTION(cri_trng1), + MSM_PIN_FUNCTION(cxc_clk), + MSM_PIN_FUNCTION(cxc_data), + MSM_PIN_FUNCTION(dbg_out), + MSM_PIN_FUNCTION(eud_gpio), + MSM_PIN_FUNCTION(gcc_plltest), + MSM_PIN_FUNCTION(gcc_tlmm), + MSM_PIN_FUNCTION(gpio), + MSM_PIN_FUNCTION(led0), + MSM_PIN_FUNCTION(led2), + MSM_PIN_FUNCTION(mac0), + MSM_PIN_FUNCTION(mac1), + MSM_PIN_FUNCTION(mdc), + MSM_PIN_FUNCTION(mdio), + MSM_PIN_FUNCTION(pcie0_clk), + MSM_PIN_FUNCTION(pcie0_wake), + MSM_PIN_FUNCTION(pcie1_clk), + MSM_PIN_FUNCTION(pcie1_wake), + MSM_PIN_FUNCTION(pll_test), + MSM_PIN_FUNCTION(prng_rosc), + MSM_PIN_FUNCTION(pwm0), + MSM_PIN_FUNCTION(pwm1), + MSM_PIN_FUNCTION(pwm2), + MSM_PIN_FUNCTION(pwm3), + MSM_PIN_FUNCTION(qdss_cti_trig_in_a0), + MSM_PIN_FUNCTION(qdss_cti_trig_in_a1), + MSM_PIN_FUNCTION(qdss_cti_trig_in_b0), + MSM_PIN_FUNCTION(qdss_cti_trig_in_b1), + MSM_PIN_FUNCTION(qdss_cti_trig_out_a0), + MSM_PIN_FUNCTION(qdss_cti_trig_out_a1), + MSM_PIN_FUNCTION(qdss_cti_trig_out_b0), + MSM_PIN_FUNCTION(qdss_cti_trig_out_b1), + MSM_PIN_FUNCTION(qdss_traceclk_a), + MSM_PIN_FUNCTION(qdss_traceclk_b), + MSM_PIN_FUNCTION(qdss_tracectl_a), + MSM_PIN_FUNCTION(qdss_tracectl_b), + MSM_PIN_FUNCTION(qdss_tracedata_a), + MSM_PIN_FUNCTION(qdss_tracedata_b), + MSM_PIN_FUNCTION(qspi_clk), + MSM_PIN_FUNCTION(qspi_cs), + MSM_PIN_FUNCTION(qspi_data), + MSM_PIN_FUNCTION(reset_out), + MSM_PIN_FUNCTION(sdc1_clk), + MSM_PIN_FUNCTION(sdc1_cmd), + MSM_PIN_FUNCTION(sdc1_data), + MSM_PIN_FUNCTION(wci_txd), + MSM_PIN_FUNCTION(wci_rxd), + MSM_PIN_FUNCTION(wsa_swrm), + MSM_PIN_FUNCTION(wsi_clk3), + MSM_PIN_FUNCTION(wsi_data3), + MSM_PIN_FUNCTION(wsis_reset), + MSM_PIN_FUNCTION(xfem), +}; + +static const struct msm_pingroup ipq5018_groups[] = { + PINGROUP(0, atest_char, _, qdss_cti_trig_out_a0, wci_txd, wci_rxd, xfem, _, _, _), + PINGROUP(1, atest_char, _, qdss_cti_trig_in_a0, wci_txd, wci_rxd, xfem, _, _, _), + PINGROUP(2, atest_char, _, qdss_cti_trig_out_a1, wci_txd, wci_rxd, xfem, _, _, _), + PINGROUP(3, atest_char, _, qdss_cti_trig_in_a1, wci_txd, wci_rxd, xfem, _, _, _), + PINGROUP(4, sdc1_data, qspi_data, blsp1_spi1, btss, dbg_out, qdss_traceclk_a, _, burn0, _), + PINGROUP(5, sdc1_data, qspi_data, cxc_clk, blsp1_spi1, blsp1_i2c1, btss, _, qdss_tracectl_a, _), + PINGROUP(6, sdc1_data, qspi_data, cxc_data, blsp1_spi1, blsp1_i2c1, btss, _, qdss_tracedata_a, _), + PINGROUP(7, sdc1_data, qspi_data, mac0, blsp1_spi1, btss, _, qdss_tracedata_a, _, _), + PINGROUP(8, sdc1_cmd, qspi_cs, mac1, btss, _, qdss_tracedata_a, _, _, _), + PINGROUP(9, sdc1_clk, qspi_clk, _, qdss_tracedata_a, _, _, _, _, _), + PINGROUP(10, blsp0_spi, blsp1_uart0, led0, gcc_plltest, qdss_tracedata_a, _, _, _, _), + PINGROUP(11, blsp0_spi, blsp1_uart0, _, gcc_tlmm, qdss_tracedata_a, _, _, _, _), + PINGROUP(12, blsp0_spi, blsp0_i2c, blsp1_uart0, _, gcc_plltest, qdss_tracedata_a, _, _, _), + PINGROUP(13, blsp0_spi, blsp0_i2c, blsp1_uart0, _, qdss_tracedata_a, _, _, _, _), + PINGROUP(14, pcie0_clk, _, _, cri_trng0, qdss_tracedata_a, _, _, _, _), + PINGROUP(15, _, _, cri_trng1, qdss_tracedata_a, _, _, _, _, _), + PINGROUP(16, pcie0_wake, _, _, cri_trng, qdss_tracedata_a, _, _, _, _), + PINGROUP(17, pcie1_clk, btss, _, prng_rosc, qdss_tracedata_a, _, _, _, _), + PINGROUP(18, blsp1_spi0, btss, _, qdss_tracedata_a, _, _, _, _, _), + PINGROUP(19, pcie1_wake, blsp1_spi0, blsp1_i2c0, btss, _, qdss_tracedata_a, _, _, _), + PINGROUP(20, blsp0_uart0, blsp1_spi0, blsp1_i2c0, _, qdss_tracedata_a, _, _, _, _), + PINGROUP(21, blsp0_uart0, blsp1_spi0, _, qdss_tracedata_a, _, _, _, _, _), + PINGROUP(22, _, pll_test, eud_gpio, _, _, _, _, _, _), + PINGROUP(23, audio_rxmclk, audio_pdm0, audio_rxmclk, blsp2_spi1, blsp1_uart2, btss, _, qdss_tracedata_b, _), + PINGROUP(24, audio_rxbclk, audio_pdm0, blsp2_spi1, blsp1_uart2, btss, _, qdss_tracedata_b, _, _), + PINGROUP(25, audio_rxfsync, audio_pdm1, blsp2_i2c1, blsp2_spi1, blsp1_uart2, btss, _, qdss_tracedata_b, _), + PINGROUP(26, audio_rxd, audio_pdm1, blsp2_i2c1, blsp2_spi1, blsp1_uart2, btss, _, qdss_tracedata_b, _), + PINGROUP(27, audio_txmclk, wsa_swrm, audio_txmclk, blsp2_spi, btss, _, qdss_tracedata_b, _, _), + PINGROUP(28, audio_txbclk, wsa_swrm, blsp0_uart1, btss, qdss_tracedata_b, _, _, _, _), + PINGROUP(29, audio_txfsync, _, blsp0_uart1, _, qdss_tracedata_b, _, _, _, _), + PINGROUP(30, audio_txd, led2, led0, _, _, _, _, _, _), + PINGROUP(31, blsp2_spi0, blsp1_uart1, _, qdss_tracedata_b, eud_gpio, _, _, _, _), + PINGROUP(32, blsp2_spi0, blsp1_uart1, _, qdss_tracedata_b, eud_gpio, _, _, _, _), + PINGROUP(33, blsp2_i2c0, blsp2_spi0, blsp1_uart1, _, qdss_tracedata_b, eud_gpio, _, _, _), + PINGROUP(34, blsp2_i2c0, blsp2_spi0, blsp1_uart1, _, qdss_tracedata_b, eud_gpio, _, _, _), + PINGROUP(35, _, qdss_tracedata_b, eud_gpio, _, _, _, _, _, _), + PINGROUP(36, mdc, qdss_tracedata_b, _, wsi_clk3, _, _, _, _, _), + PINGROUP(37, mdio, atest_char, qdss_tracedata_b, _, wsi_data3, _, _, _, _), + PINGROUP(38, qdss_tracedata_b, _, _, _, _, _, _, _, _), + PINGROUP(39, qdss_traceclk_b, _, _, _, _, _, _, _, _), + PINGROUP(40, reset_out, qdss_tracectl_b, _, _, _, _, _, _, _), + PINGROUP(41, _, _, _, _, _, _, _, _, _), + PINGROUP(42, pwm0, qdss_cti_trig_out_b0, wci_txd, wci_rxd, xfem, _, _, _, _), + PINGROUP(43, pwm1, qdss_cti_trig_in_b0, wci_txd, wci_rxd, xfem, _, _, _, _), + PINGROUP(44, pwm2, qdss_cti_trig_out_b1, wci_txd, wci_rxd, xfem, _, _, _, _), + PINGROUP(45, pwm3, qdss_cti_trig_in_b1, wci_txd, wci_rxd, xfem, _, _, _, _), + PINGROUP(46, led0, _, _, _, _, _, _, _, _), +}; + +static const struct msm_pinctrl_soc_data ipq5018_pinctrl = { + .pins = ipq5018_pins, + .npins = ARRAY_SIZE(ipq5018_pins), + .functions = ipq5018_functions, + .nfunctions = ARRAY_SIZE(ipq5018_functions), + .groups = ipq5018_groups, + .ngroups = ARRAY_SIZE(ipq5018_groups), + .ngpios = 47, +}; + +static int ipq5018_pinctrl_probe(struct platform_device *pdev) +{ + return msm_pinctrl_probe(pdev, &ipq5018_pinctrl); +} + +static const struct of_device_id ipq5018_pinctrl_of_match[] = { + { .compatible = "qcom,ipq5018-tlmm", }, + { } +}; +MODULE_DEVICE_TABLE(of, ipq5018_pinctrl_of_match); + +static struct platform_driver ipq5018_pinctrl_driver = { + .driver = { + .name = "ipq5018-tlmm", + .of_match_table = ipq5018_pinctrl_of_match, + }, + .probe = ipq5018_pinctrl_probe, + .remove = msm_pinctrl_remove, +}; + +static int __init ipq5018_pinctrl_init(void) +{ + return platform_driver_register(&ipq5018_pinctrl_driver); +} +arch_initcall(ipq5018_pinctrl_init); + +static void __exit ipq5018_pinctrl_exit(void) +{ + platform_driver_unregister(&ipq5018_pinctrl_driver); +} +module_exit(ipq5018_pinctrl_exit); + +MODULE_DESCRIPTION("Qualcomm Technologies Inc ipq5018 pinctrl driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/pinctrl/qcom/pinctrl-ipq5332.c b/drivers/pinctrl/qcom/pinctrl-ipq5332.c new file mode 100644 index 0000000000..625f801405 --- /dev/null +++ b/drivers/pinctrl/qcom/pinctrl-ipq5332.c @@ -0,0 +1,853 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* + * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include <linux/module.h> +#include <linux/of.h> +#include <linux/platform_device.h> + +#include "pinctrl-msm.h" + +#define REG_SIZE 0x1000 +#define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7, f8, f9) \ + { \ + .grp = PINCTRL_PINGROUP("gpio" #id, \ + gpio##id##_pins, \ + ARRAY_SIZE(gpio##id##_pins)), \ + .funcs = (int[]){ \ + msm_mux_gpio, /* gpio mode */ \ + msm_mux_##f1, \ + msm_mux_##f2, \ + msm_mux_##f3, \ + msm_mux_##f4, \ + msm_mux_##f5, \ + msm_mux_##f6, \ + msm_mux_##f7, \ + msm_mux_##f8, \ + msm_mux_##f9 \ + }, \ + .nfuncs = 10, \ + .ctl_reg = REG_SIZE * id, \ + .io_reg = 0x4 + REG_SIZE * id, \ + .intr_cfg_reg = 0x8 + REG_SIZE * id, \ + .intr_status_reg = 0xc + REG_SIZE * id, \ + .intr_target_reg = 0x8 + REG_SIZE * id, \ + .mux_bit = 2, \ + .pull_bit = 0, \ + .drv_bit = 6, \ + .oe_bit = 9, \ + .in_bit = 0, \ + .out_bit = 1, \ + .intr_enable_bit = 0, \ + .intr_status_bit = 0, \ + .intr_target_bit = 5, \ + .intr_target_kpss_val = 3, \ + .intr_raw_status_bit = 4, \ + .intr_polarity_bit = 1, \ + .intr_detection_bit = 2, \ + .intr_detection_width = 2, \ + } + +static const struct pinctrl_pin_desc ipq5332_pins[] = { + PINCTRL_PIN(0, "GPIO_0"), + PINCTRL_PIN(1, "GPIO_1"), + PINCTRL_PIN(2, "GPIO_2"), + PINCTRL_PIN(3, "GPIO_3"), + PINCTRL_PIN(4, "GPIO_4"), + PINCTRL_PIN(5, "GPIO_5"), + PINCTRL_PIN(6, "GPIO_6"), + PINCTRL_PIN(7, "GPIO_7"), + PINCTRL_PIN(8, "GPIO_8"), + PINCTRL_PIN(9, "GPIO_9"), + PINCTRL_PIN(10, "GPIO_10"), + PINCTRL_PIN(11, "GPIO_11"), + PINCTRL_PIN(12, "GPIO_12"), + PINCTRL_PIN(13, "GPIO_13"), + PINCTRL_PIN(14, "GPIO_14"), + PINCTRL_PIN(15, "GPIO_15"), + PINCTRL_PIN(16, "GPIO_16"), + PINCTRL_PIN(17, "GPIO_17"), + PINCTRL_PIN(18, "GPIO_18"), + PINCTRL_PIN(19, "GPIO_19"), + PINCTRL_PIN(20, "GPIO_20"), + PINCTRL_PIN(21, "GPIO_21"), + PINCTRL_PIN(22, "GPIO_22"), + PINCTRL_PIN(23, "GPIO_23"), + PINCTRL_PIN(24, "GPIO_24"), + PINCTRL_PIN(25, "GPIO_25"), + PINCTRL_PIN(26, "GPIO_26"), + PINCTRL_PIN(27, "GPIO_27"), + PINCTRL_PIN(28, "GPIO_28"), + PINCTRL_PIN(29, "GPIO_29"), + PINCTRL_PIN(30, "GPIO_30"), + PINCTRL_PIN(31, "GPIO_31"), + PINCTRL_PIN(32, "GPIO_32"), + PINCTRL_PIN(33, "GPIO_33"), + PINCTRL_PIN(34, "GPIO_34"), + PINCTRL_PIN(35, "GPIO_35"), + PINCTRL_PIN(36, "GPIO_36"), + PINCTRL_PIN(37, "GPIO_37"), + PINCTRL_PIN(38, "GPIO_38"), + PINCTRL_PIN(39, "GPIO_39"), + PINCTRL_PIN(40, "GPIO_40"), + PINCTRL_PIN(41, "GPIO_41"), + PINCTRL_PIN(42, "GPIO_42"), + PINCTRL_PIN(43, "GPIO_43"), + PINCTRL_PIN(44, "GPIO_44"), + PINCTRL_PIN(45, "GPIO_45"), + PINCTRL_PIN(46, "GPIO_46"), + PINCTRL_PIN(47, "GPIO_47"), + PINCTRL_PIN(48, "GPIO_48"), + PINCTRL_PIN(49, "GPIO_49"), + PINCTRL_PIN(50, "GPIO_50"), + PINCTRL_PIN(51, "GPIO_51"), + PINCTRL_PIN(52, "GPIO_52"), +}; + +#define DECLARE_MSM_GPIO_PINS(pin) \ + static const unsigned int gpio##pin##_pins[] = { pin } +DECLARE_MSM_GPIO_PINS(0); +DECLARE_MSM_GPIO_PINS(1); +DECLARE_MSM_GPIO_PINS(2); +DECLARE_MSM_GPIO_PINS(3); +DECLARE_MSM_GPIO_PINS(4); +DECLARE_MSM_GPIO_PINS(5); +DECLARE_MSM_GPIO_PINS(6); +DECLARE_MSM_GPIO_PINS(7); +DECLARE_MSM_GPIO_PINS(8); +DECLARE_MSM_GPIO_PINS(9); +DECLARE_MSM_GPIO_PINS(10); +DECLARE_MSM_GPIO_PINS(11); +DECLARE_MSM_GPIO_PINS(12); +DECLARE_MSM_GPIO_PINS(13); +DECLARE_MSM_GPIO_PINS(14); +DECLARE_MSM_GPIO_PINS(15); +DECLARE_MSM_GPIO_PINS(16); +DECLARE_MSM_GPIO_PINS(17); +DECLARE_MSM_GPIO_PINS(18); +DECLARE_MSM_GPIO_PINS(19); +DECLARE_MSM_GPIO_PINS(20); +DECLARE_MSM_GPIO_PINS(21); +DECLARE_MSM_GPIO_PINS(22); +DECLARE_MSM_GPIO_PINS(23); +DECLARE_MSM_GPIO_PINS(24); +DECLARE_MSM_GPIO_PINS(25); +DECLARE_MSM_GPIO_PINS(26); +DECLARE_MSM_GPIO_PINS(27); +DECLARE_MSM_GPIO_PINS(28); +DECLARE_MSM_GPIO_PINS(29); +DECLARE_MSM_GPIO_PINS(30); +DECLARE_MSM_GPIO_PINS(31); +DECLARE_MSM_GPIO_PINS(32); +DECLARE_MSM_GPIO_PINS(33); +DECLARE_MSM_GPIO_PINS(34); +DECLARE_MSM_GPIO_PINS(35); +DECLARE_MSM_GPIO_PINS(36); +DECLARE_MSM_GPIO_PINS(37); +DECLARE_MSM_GPIO_PINS(38); +DECLARE_MSM_GPIO_PINS(39); +DECLARE_MSM_GPIO_PINS(40); +DECLARE_MSM_GPIO_PINS(41); +DECLARE_MSM_GPIO_PINS(42); +DECLARE_MSM_GPIO_PINS(43); +DECLARE_MSM_GPIO_PINS(44); +DECLARE_MSM_GPIO_PINS(45); +DECLARE_MSM_GPIO_PINS(46); +DECLARE_MSM_GPIO_PINS(47); +DECLARE_MSM_GPIO_PINS(48); +DECLARE_MSM_GPIO_PINS(49); +DECLARE_MSM_GPIO_PINS(50); +DECLARE_MSM_GPIO_PINS(51); +DECLARE_MSM_GPIO_PINS(52); + +enum ipq5332_functions { + msm_mux_atest_char, + msm_mux_atest_char0, + msm_mux_atest_char1, + msm_mux_atest_char2, + msm_mux_atest_char3, + msm_mux_atest_tic, + msm_mux_audio_pri, + msm_mux_audio_pri0, + msm_mux_audio_pri1, + msm_mux_audio_sec, + msm_mux_audio_sec0, + msm_mux_audio_sec1, + msm_mux_blsp0_i2c, + msm_mux_blsp0_spi, + msm_mux_blsp0_uart0, + msm_mux_blsp0_uart1, + msm_mux_blsp1_i2c0, + msm_mux_blsp1_i2c1, + msm_mux_blsp1_spi0, + msm_mux_blsp1_spi1, + msm_mux_blsp1_uart0, + msm_mux_blsp1_uart1, + msm_mux_blsp1_uart2, + msm_mux_blsp2_i2c0, + msm_mux_blsp2_i2c1, + msm_mux_blsp2_spi, + msm_mux_blsp2_spi0, + msm_mux_blsp2_spi1, + msm_mux_core_voltage, + msm_mux_cri_trng0, + msm_mux_cri_trng1, + msm_mux_cri_trng2, + msm_mux_cri_trng3, + msm_mux_cxc_clk, + msm_mux_cxc_data, + msm_mux_dbg_out, + msm_mux_gcc_plltest, + msm_mux_gcc_tlmm, + msm_mux_gpio, + msm_mux_lock_det, + msm_mux_mac0, + msm_mux_mac1, + msm_mux_mdc0, + msm_mux_mdc1, + msm_mux_mdio0, + msm_mux_mdio1, + msm_mux_pc, + msm_mux_pcie0_clk, + msm_mux_pcie0_wake, + msm_mux_pcie1_clk, + msm_mux_pcie1_wake, + msm_mux_pcie2_clk, + msm_mux_pcie2_wake, + msm_mux_pll_test, + msm_mux_prng_rosc0, + msm_mux_prng_rosc1, + msm_mux_prng_rosc2, + msm_mux_prng_rosc3, + msm_mux_pta, + msm_mux_pwm0, + msm_mux_pwm1, + msm_mux_pwm2, + msm_mux_pwm3, + msm_mux_qdss_cti_trig_in_a0, + msm_mux_qdss_cti_trig_in_a1, + msm_mux_qdss_cti_trig_in_b0, + msm_mux_qdss_cti_trig_in_b1, + msm_mux_qdss_cti_trig_out_a0, + msm_mux_qdss_cti_trig_out_a1, + msm_mux_qdss_cti_trig_out_b0, + msm_mux_qdss_cti_trig_out_b1, + msm_mux_qdss_traceclk_a, + msm_mux_qdss_traceclk_b, + msm_mux_qdss_tracectl_a, + msm_mux_qdss_tracectl_b, + msm_mux_qdss_tracedata_a, + msm_mux_qdss_tracedata_b, + msm_mux_qspi_data, + msm_mux_qspi_clk, + msm_mux_qspi_cs, + msm_mux_resout, + msm_mux_rx0, + msm_mux_rx1, + msm_mux_sdc_data, + msm_mux_sdc_clk, + msm_mux_sdc_cmd, + msm_mux_tsens_max, + msm_mux_wci_txd, + msm_mux_wci_rxd, + msm_mux_wsi_clk, + msm_mux_wsi_clk3, + msm_mux_wsi_data, + msm_mux_wsi_data3, + msm_mux_wsis_reset, + msm_mux_xfem, + msm_mux__, +}; + +static const char * const gpio_groups[] = { + "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7", + "gpio8", "gpio9", "gpio10", "gpio11", "gpio12", "gpio13", "gpio14", + "gpio15", "gpio16", "gpio17", "gpio18", "gpio19", "gpio20", "gpio21", + "gpio22", "gpio23", "gpio24", "gpio25", "gpio26", "gpio27", "gpio28", + "gpio29", "gpio30", "gpio31", "gpio32", "gpio33", "gpio34", "gpio35", + "gpio36", "gpio37", "gpio38", "gpio39", "gpio40", "gpio41", "gpio42", + "gpio43", "gpio44", "gpio45", "gpio46", "gpio47", "gpio48", "gpio49", + "gpio50", "gpio51", "gpio52", +}; + +static const char * const atest_char_groups[] = { + "gpio46", +}; + +static const char * const atest_char0_groups[] = { + "gpio0", +}; + +static const char * const atest_char1_groups[] = { + "gpio1", +}; + +static const char * const atest_char2_groups[] = { + "gpio2", +}; + +static const char * const atest_char3_groups[] = { + "gpio3", +}; + +static const char * const atest_tic_groups[] = { + "gpio9", +}; + +static const char * const audio_pri_groups[] = { + "gpio29", "gpio30", "gpio31", "gpio32", +}; + +static const char * const audio_pri0_groups[] = { + "gpio34", "gpio34", +}; + +static const char * const audio_pri1_groups[] = { + "gpio43", "gpio43", +}; + +static const char * const audio_sec_groups[] = { + "gpio33", "gpio34", "gpio35", "gpio36", +}; + +static const char * const audio_sec0_groups[] = { + "gpio30", "gpio30", +}; + +static const char * const audio_sec1_groups[] = { + "gpio45", "gpio45", +}; + +static const char * const blsp0_i2c_groups[] = { + "gpio16", "gpio17", +}; + +static const char * const blsp0_spi_groups[] = { + "gpio14", "gpio15", "gpio16", "gpio17", +}; + +static const char * const blsp0_uart0_groups[] = { + "gpio18", "gpio19", +}; + +static const char * const blsp0_uart1_groups[] = { + "gpio27", "gpio28", +}; + +static const char * const blsp1_i2c0_groups[] = { + "gpio29", "gpio30", +}; + +static const char * const blsp1_i2c1_groups[] = { + "gpio40", "gpio41", +}; + +static const char * const blsp1_spi0_groups[] = { + "gpio29", "gpio30", "gpio31", "gpio32", +}; + +static const char * const blsp1_spi1_groups[] = { + "gpio25", "gpio26", "gpio27", "gpio28", +}; + +static const char * const blsp1_uart0_groups[] = { + "gpio14", "gpio15", "gpio16", "gpio17", +}; + +static const char * const blsp1_uart1_groups[] = { + "gpio25", "gpio26", "gpio27", "gpio28", +}; + +static const char * const blsp1_uart2_groups[] = { + "gpio33", "gpio34", "gpio35", "gpio36", +}; + +static const char * const blsp2_i2c0_groups[] = { + "gpio43", "gpio45", +}; + +static const char * const blsp2_i2c1_groups[] = { + "gpio33", "gpio34", +}; + +static const char * const blsp2_spi_groups[] = { + "gpio37", +}; + +static const char * const blsp2_spi0_groups[] = { + "gpio33", "gpio34", "gpio35", "gpio36", +}; + +static const char * const blsp2_spi1_groups[] = { + "gpio40", "gpio41", "gpio42", "gpio52", +}; + +static const char * const core_voltage_groups[] = { + "gpio21", "gpio23", +}; + +static const char * const cri_trng0_groups[] = { + "gpio17", +}; + +static const char * const cri_trng1_groups[] = { + "gpio18", +}; + +static const char * const cri_trng2_groups[] = { + "gpio19", +}; + +static const char * const cri_trng3_groups[] = { + "gpio20", +}; + +static const char * const cxc_clk_groups[] = { + "gpio49", +}; + +static const char * const cxc_data_groups[] = { + "gpio50", +}; + +static const char * const dbg_out_groups[] = { + "gpio48", +}; + +static const char * const gcc_plltest_groups[] = { + "gpio43", "gpio45", +}; + +static const char * const gcc_tlmm_groups[] = { + "gpio44", +}; + +static const char * const lock_det_groups[] = { + "gpio51", +}; + +static const char * const mac0_groups[] = { + "gpio18", +}; + +static const char * const mac1_groups[] = { + "gpio19", +}; + +static const char * const mdc0_groups[] = { + "gpio25", +}; + +static const char * const mdc1_groups[] = { + "gpio27", +}; + +static const char * const mdio0_groups[] = { + "gpio26", +}; + +static const char * const mdio1_groups[] = { + "gpio28", +}; + +static const char * const pc_groups[] = { + "gpio35", +}; + +static const char * const pcie0_clk_groups[] = { + "gpio37", +}; + +static const char * const pcie0_wake_groups[] = { + "gpio39", +}; + +static const char * const pcie1_clk_groups[] = { + "gpio46", +}; + +static const char * const pcie1_wake_groups[] = { + "gpio48", +}; + +static const char * const pcie2_clk_groups[] = { + "gpio43", +}; + +static const char * const pcie2_wake_groups[] = { + "gpio45", +}; + +static const char * const pll_test_groups[] = { + "gpio49", +}; + +static const char * const prng_rosc0_groups[] = { + "gpio22", +}; + +static const char * const prng_rosc1_groups[] = { + "gpio24", +}; + +static const char * const prng_rosc2_groups[] = { + "gpio25", +}; + +static const char * const prng_rosc3_groups[] = { + "gpio26", +}; + +static const char * const pta_groups[] = { + "gpio49", "gpio50", "gpio51", +}; + +static const char * const pwm0_groups[] = { + "gpio43", "gpio44", "gpio45", "gpio46", +}; + +static const char * const pwm1_groups[] = { + "gpio29", "gpio30", "gpio31", "gpio32", +}; + +static const char * const pwm2_groups[] = { + "gpio25", "gpio26", "gpio27", "gpio28", +}; + +static const char * const pwm3_groups[] = { + "gpio8", "gpio9", "gpio10", "gpio11", +}; + +static const char * const qdss_cti_trig_in_a0_groups[] = { + "gpio5", +}; + +static const char * const qdss_cti_trig_in_a1_groups[] = { + "gpio7", +}; + +static const char * const qdss_cti_trig_in_b0_groups[] = { + "gpio47", +}; + +static const char * const qdss_cti_trig_in_b1_groups[] = { + "gpio49", +}; + +static const char * const qdss_cti_trig_out_a0_groups[] = { + "gpio4", +}; + +static const char * const qdss_cti_trig_out_a1_groups[] = { + "gpio6", +}; + +static const char * const qdss_cti_trig_out_b0_groups[] = { + "gpio46", +}; + +static const char * const qdss_cti_trig_out_b1_groups[] = { + "gpio48", +}; + +static const char * const qdss_traceclk_a_groups[] = { + "gpio8", +}; + +static const char * const qdss_traceclk_b_groups[] = { + "gpio45", +}; + +static const char * const qdss_tracectl_a_groups[] = { + "gpio9", +}; + +static const char * const qdss_tracectl_b_groups[] = { + "gpio44", +}; + +static const char * const qdss_tracedata_a_groups[] = { + "gpio10", "gpio11", "gpio12", "gpio13", "gpio14", "gpio15", "gpio16", + "gpio17", "gpio18", "gpio19", "gpio20", "gpio22", "gpio24", "gpio25", + "gpio26", "gpio27", +}; + +static const char * const qdss_tracedata_b_groups[] = { + "gpio29", "gpio30", "gpio31", "gpio32", "gpio33", "gpio34", "gpio35", + "gpio36", "gpio37", "gpio38", "gpio39", "gpio40", "gpio41", "gpio42", + "gpio43", "gpio52", +}; + +static const char * const qspi_clk_groups[] = { + "gpio13", +}; + +static const char * const qspi_cs_groups[] = { + "gpio12", +}; + +static const char * const qspi_data_groups[] = { + "gpio8", "gpio9", "gpio10", "gpio11", +}; + +static const char * const resout_groups[] = { + "gpio20", +}; + +static const char * const rx0_groups[] = { + "gpio48", +}; + +static const char * const rx1_groups[] = { + "gpio45", +}; + +static const char * const sdc_clk_groups[] = { + "gpio13", +}; + +static const char * const sdc_cmd_groups[] = { + "gpio12", +}; + +static const char * const sdc_data_groups[] = { + "gpio8", "gpio9", "gpio10", "gpio11", +}; + +static const char * const tsens_max_groups[] = { + "gpio28", +}; + +static const char * const wci_txd_groups[] = { + "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7", + "gpio36", "gpio43", "gpio45", +}; + +static const char * const wci_rxd_groups[] = { + "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7", + "gpio35", "gpio36", "gpio43", "gpio45", +}; + +static const char * const wsi_clk_groups[] = { + "gpio40", "gpio42", +}; + +static const char * const wsi_clk3_groups[] = { + "gpio43", +}; + +static const char * const wsi_data_groups[] = { + "gpio41", "gpio52", +}; + +static const char * const wsi_data3_groups[] = { + "gpio44", +}; + +static const char * const wsis_reset_groups[] = { + "gpio41", +}; + +static const char * const xfem_groups[] = { + "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7", +}; + +static const struct pinfunction ipq5332_functions[] = { + MSM_PIN_FUNCTION(atest_char), + MSM_PIN_FUNCTION(atest_char0), + MSM_PIN_FUNCTION(atest_char1), + MSM_PIN_FUNCTION(atest_char2), + MSM_PIN_FUNCTION(atest_char3), + MSM_PIN_FUNCTION(atest_tic), + MSM_PIN_FUNCTION(audio_pri), + MSM_PIN_FUNCTION(audio_pri0), + MSM_PIN_FUNCTION(audio_pri1), + MSM_PIN_FUNCTION(audio_sec), + MSM_PIN_FUNCTION(audio_sec0), + MSM_PIN_FUNCTION(audio_sec1), + MSM_PIN_FUNCTION(blsp0_i2c), + MSM_PIN_FUNCTION(blsp0_spi), + MSM_PIN_FUNCTION(blsp0_uart0), + MSM_PIN_FUNCTION(blsp0_uart1), + MSM_PIN_FUNCTION(blsp1_i2c0), + MSM_PIN_FUNCTION(blsp1_i2c1), + MSM_PIN_FUNCTION(blsp1_spi0), + MSM_PIN_FUNCTION(blsp1_spi1), + MSM_PIN_FUNCTION(blsp1_uart0), + MSM_PIN_FUNCTION(blsp1_uart1), + MSM_PIN_FUNCTION(blsp1_uart2), + MSM_PIN_FUNCTION(blsp2_i2c0), + MSM_PIN_FUNCTION(blsp2_i2c1), + MSM_PIN_FUNCTION(blsp2_spi), + MSM_PIN_FUNCTION(blsp2_spi0), + MSM_PIN_FUNCTION(blsp2_spi1), + MSM_PIN_FUNCTION(core_voltage), + MSM_PIN_FUNCTION(cri_trng0), + MSM_PIN_FUNCTION(cri_trng1), + MSM_PIN_FUNCTION(cri_trng2), + MSM_PIN_FUNCTION(cri_trng3), + MSM_PIN_FUNCTION(cxc_clk), + MSM_PIN_FUNCTION(cxc_data), + MSM_PIN_FUNCTION(dbg_out), + MSM_PIN_FUNCTION(gcc_plltest), + MSM_PIN_FUNCTION(gcc_tlmm), + MSM_PIN_FUNCTION(gpio), + MSM_PIN_FUNCTION(lock_det), + MSM_PIN_FUNCTION(mac0), + MSM_PIN_FUNCTION(mac1), + MSM_PIN_FUNCTION(mdc0), + MSM_PIN_FUNCTION(mdc1), + MSM_PIN_FUNCTION(mdio0), + MSM_PIN_FUNCTION(mdio1), + MSM_PIN_FUNCTION(pc), + MSM_PIN_FUNCTION(pcie0_clk), + MSM_PIN_FUNCTION(pcie0_wake), + MSM_PIN_FUNCTION(pcie1_clk), + MSM_PIN_FUNCTION(pcie1_wake), + MSM_PIN_FUNCTION(pcie2_clk), + MSM_PIN_FUNCTION(pcie2_wake), + MSM_PIN_FUNCTION(pll_test), + MSM_PIN_FUNCTION(prng_rosc0), + MSM_PIN_FUNCTION(prng_rosc1), + MSM_PIN_FUNCTION(prng_rosc2), + MSM_PIN_FUNCTION(prng_rosc3), + MSM_PIN_FUNCTION(pta), + MSM_PIN_FUNCTION(pwm0), + MSM_PIN_FUNCTION(pwm1), + MSM_PIN_FUNCTION(pwm2), + MSM_PIN_FUNCTION(pwm3), + MSM_PIN_FUNCTION(qdss_cti_trig_in_a0), + MSM_PIN_FUNCTION(qdss_cti_trig_in_a1), + MSM_PIN_FUNCTION(qdss_cti_trig_in_b0), + MSM_PIN_FUNCTION(qdss_cti_trig_in_b1), + MSM_PIN_FUNCTION(qdss_cti_trig_out_a0), + MSM_PIN_FUNCTION(qdss_cti_trig_out_a1), + MSM_PIN_FUNCTION(qdss_cti_trig_out_b0), + MSM_PIN_FUNCTION(qdss_cti_trig_out_b1), + MSM_PIN_FUNCTION(qdss_traceclk_a), + MSM_PIN_FUNCTION(qdss_traceclk_b), + MSM_PIN_FUNCTION(qdss_tracectl_a), + MSM_PIN_FUNCTION(qdss_tracectl_b), + MSM_PIN_FUNCTION(qdss_tracedata_a), + MSM_PIN_FUNCTION(qdss_tracedata_b), + MSM_PIN_FUNCTION(qspi_data), + MSM_PIN_FUNCTION(qspi_clk), + MSM_PIN_FUNCTION(qspi_cs), + MSM_PIN_FUNCTION(resout), + MSM_PIN_FUNCTION(rx0), + MSM_PIN_FUNCTION(rx1), + MSM_PIN_FUNCTION(sdc_data), + MSM_PIN_FUNCTION(sdc_clk), + MSM_PIN_FUNCTION(sdc_cmd), + MSM_PIN_FUNCTION(tsens_max), + MSM_PIN_FUNCTION(wci_txd), + MSM_PIN_FUNCTION(wci_rxd), + MSM_PIN_FUNCTION(wsi_clk), + MSM_PIN_FUNCTION(wsi_clk3), + MSM_PIN_FUNCTION(wsi_data), + MSM_PIN_FUNCTION(wsi_data3), + MSM_PIN_FUNCTION(wsis_reset), + MSM_PIN_FUNCTION(xfem), +}; + +static const struct msm_pingroup ipq5332_groups[] = { + PINGROUP(0, atest_char0, wci_txd, wci_rxd, xfem, _, _, _, _, _), + PINGROUP(1, atest_char1, wci_txd, wci_rxd, xfem, _, _, _, _, _), + PINGROUP(2, atest_char2, wci_txd, wci_rxd, xfem, _, _, _, _, _), + PINGROUP(3, atest_char3, wci_txd, wci_rxd, xfem, _, _, _, _, _), + PINGROUP(4, qdss_cti_trig_out_a0, wci_txd, wci_rxd, xfem, _, _, _, _, _), + PINGROUP(5, qdss_cti_trig_in_a0, wci_txd, wci_rxd, xfem, _, _, _, _, _), + PINGROUP(6, qdss_cti_trig_out_a1, wci_txd, wci_rxd, xfem, _, _, _, _, _), + PINGROUP(7, qdss_cti_trig_in_a1, wci_txd, wci_rxd, xfem, _, _, _, _, _), + PINGROUP(8, sdc_data, qspi_data, pwm3, qdss_traceclk_a, _, _, _, _, _), + PINGROUP(9, sdc_data, qspi_data, pwm3, qdss_tracectl_a, _, atest_tic, _, _, _), + PINGROUP(10, sdc_data, qspi_data, pwm3, qdss_tracedata_a, _, _, _, _, _), + PINGROUP(11, sdc_data, qspi_data, pwm3, qdss_tracedata_a, _, _, _, _, _), + PINGROUP(12, sdc_cmd, qspi_cs, qdss_tracedata_a, _, _, _, _, _, _), + PINGROUP(13, sdc_clk, qspi_clk, qdss_tracedata_a, _, _, _, _, _, _), + PINGROUP(14, blsp0_spi, blsp1_uart0, qdss_tracedata_a, _, _, _, _, _, _), + PINGROUP(15, blsp0_spi, blsp1_uart0, qdss_tracedata_a, _, _, _, _, _, _), + PINGROUP(16, blsp0_spi, blsp0_i2c, blsp1_uart0, _, qdss_tracedata_a, _, _, _, _), + PINGROUP(17, blsp0_spi, blsp0_i2c, blsp1_uart0, _, cri_trng0, qdss_tracedata_a, _, _, _), + PINGROUP(18, blsp0_uart0, mac0, _, cri_trng1, qdss_tracedata_a, _, _, _, _), + PINGROUP(19, blsp0_uart0, mac1, _, cri_trng2, qdss_tracedata_a, _, _, _, _), + PINGROUP(20, resout, _, cri_trng3, qdss_tracedata_a, _, _, _, _, _), + PINGROUP(21, core_voltage, _, _, _, _, _, _, _, _), + PINGROUP(22, _, prng_rosc0, qdss_tracedata_a, _, _, _, _, _, _), + PINGROUP(23, core_voltage, _, _, _, _, _, _, _, _), + PINGROUP(24, _, prng_rosc1, qdss_tracedata_a, _, _, _, _, _, _), + PINGROUP(25, mdc0, blsp1_uart1, blsp1_spi1, pwm2, _, _, prng_rosc2, qdss_tracedata_a, _), + PINGROUP(26, mdio0, blsp1_uart1, blsp1_spi1, pwm2, _, _, prng_rosc3, qdss_tracedata_a, _), + PINGROUP(27, mdc1, blsp0_uart1, blsp1_uart1, blsp1_spi1, pwm2, _, _, qdss_tracedata_a, _), + PINGROUP(28, mdio1, blsp0_uart1, blsp1_uart1, blsp1_spi1, pwm2, _, tsens_max, _, _), + PINGROUP(29, audio_pri, blsp1_spi0, blsp1_i2c0, pwm1, _, qdss_tracedata_b, _, _, _), + PINGROUP(30, audio_pri, blsp1_spi0, blsp1_i2c0, pwm1, audio_sec0, audio_sec0, _, qdss_tracedata_b, _), + PINGROUP(31, audio_pri, blsp1_spi0, pwm1, _, qdss_tracedata_b, _, _, _, _), + PINGROUP(32, audio_pri, blsp1_spi0, pwm1, _, qdss_tracedata_b, _, _, _, _), + PINGROUP(33, audio_sec, blsp1_uart2, blsp2_i2c1, blsp2_spi0, _, qdss_tracedata_b, _, _, _), + PINGROUP(34, audio_sec, blsp1_uart2, blsp2_i2c1, blsp2_spi0, audio_pri0, audio_pri0, _, qdss_tracedata_b, _), + PINGROUP(35, audio_sec, blsp1_uart2, pc, wci_rxd, blsp2_spi0, _, qdss_tracedata_b, _, _), + PINGROUP(36, audio_sec, blsp1_uart2, wci_txd, wci_rxd, blsp2_spi0, _, qdss_tracedata_b, _, _), + PINGROUP(37, pcie0_clk, blsp2_spi, _, qdss_tracedata_b, _, _, _, _, _), + PINGROUP(38, _, qdss_tracedata_b, _, _, _, _, _, _, _), + PINGROUP(39, pcie0_wake, _, qdss_tracedata_b, _, _, _, _, _, _), + PINGROUP(40, wsi_clk, blsp1_i2c1, blsp2_spi1, _, _, qdss_tracedata_b, _, _, _), + PINGROUP(41, wsi_data, blsp1_i2c1, blsp2_spi1, _, _, qdss_tracedata_b, _, wsis_reset, _), + PINGROUP(42, wsi_clk, blsp2_spi1, _, qdss_tracedata_b, _, _, _, _, _), + PINGROUP(43, pcie2_clk, wci_txd, wci_rxd, blsp2_i2c0, pwm0, audio_pri1, audio_pri1, _, gcc_plltest), + PINGROUP(44, pwm0, _, gcc_tlmm, qdss_tracectl_b, _, wsi_data3, _, _, _), + PINGROUP(45, pcie2_wake, wci_txd, wci_rxd, blsp2_i2c0, rx1, pwm0, audio_sec1, audio_sec1, _), + PINGROUP(46, pcie1_clk, atest_char, pwm0, _, qdss_cti_trig_out_b0, _, _, _, _), + PINGROUP(47, _, qdss_cti_trig_in_b0, _, _, _, _, _, _, _), + PINGROUP(48, pcie1_wake, rx0, dbg_out, qdss_cti_trig_out_b1, _, _, _, _, _), + PINGROUP(49, pta, cxc_clk, pll_test, _, qdss_cti_trig_in_b1, _, _, _, _), + PINGROUP(50, pta, cxc_data, _, _, _, _, _, _, _), + PINGROUP(51, pta, lock_det, _, _, _, _, _, _, _), + PINGROUP(52, wsi_data, blsp2_spi1, _, qdss_tracedata_b, _, _, _, _, _), +}; + +static const struct msm_pinctrl_soc_data ipq5332_pinctrl = { + .pins = ipq5332_pins, + .npins = ARRAY_SIZE(ipq5332_pins), + .functions = ipq5332_functions, + .nfunctions = ARRAY_SIZE(ipq5332_functions), + .groups = ipq5332_groups, + .ngroups = ARRAY_SIZE(ipq5332_groups), + .ngpios = 53, +}; + +static int ipq5332_pinctrl_probe(struct platform_device *pdev) +{ + return msm_pinctrl_probe(pdev, &ipq5332_pinctrl); +} + +static const struct of_device_id ipq5332_pinctrl_of_match[] = { + { .compatible = "qcom,ipq5332-tlmm", }, + { }, +}; +MODULE_DEVICE_TABLE(of, ipq5332_pinctrl_of_match); + +static struct platform_driver ipq5332_pinctrl_driver = { + .driver = { + .name = "ipq5332-tlmm", + .of_match_table = ipq5332_pinctrl_of_match, + }, + .probe = ipq5332_pinctrl_probe, + .remove = msm_pinctrl_remove, +}; + +static int __init ipq5332_pinctrl_init(void) +{ + return platform_driver_register(&ipq5332_pinctrl_driver); +} +arch_initcall(ipq5332_pinctrl_init); + +static void __exit ipq5332_pinctrl_exit(void) +{ + platform_driver_unregister(&ipq5332_pinctrl_driver); +} +module_exit(ipq5332_pinctrl_exit); + +MODULE_DESCRIPTION("QTI IPQ5332 TLMM driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/pinctrl/qcom/pinctrl-ipq6018.c b/drivers/pinctrl/qcom/pinctrl-ipq6018.c new file mode 100644 index 0000000000..0ad08647db --- /dev/null +++ b/drivers/pinctrl/qcom/pinctrl-ipq6018.c @@ -0,0 +1,1100 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2016-2018, The Linux Foundation. All rights reserved. + */ + +#include <linux/module.h> +#include <linux/of.h> +#include <linux/platform_device.h> + +#include "pinctrl-msm.h" + +#define REG_SIZE 0x1000 +#define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7, f8, f9) \ + { \ + .grp = PINCTRL_PINGROUP("gpio" #id, \ + gpio##id##_pins, \ + ARRAY_SIZE(gpio##id##_pins)), \ + .funcs = (int[]){ \ + msm_mux_gpio, /* gpio mode */ \ + msm_mux_##f1, \ + msm_mux_##f2, \ + msm_mux_##f3, \ + msm_mux_##f4, \ + msm_mux_##f5, \ + msm_mux_##f6, \ + msm_mux_##f7, \ + msm_mux_##f8, \ + msm_mux_##f9 \ + }, \ + .nfuncs = 10, \ + .ctl_reg = REG_SIZE * id, \ + .io_reg = 0x4 + REG_SIZE * id, \ + .intr_cfg_reg = 0x8 + REG_SIZE * id, \ + .intr_status_reg = 0xc + REG_SIZE * id, \ + .intr_target_reg = 0x8 + REG_SIZE * id, \ + .mux_bit = 2, \ + .pull_bit = 0, \ + .drv_bit = 6, \ + .oe_bit = 9, \ + .in_bit = 0, \ + .out_bit = 1, \ + .intr_enable_bit = 0, \ + .intr_status_bit = 0, \ + .intr_target_bit = 5, \ + .intr_target_kpss_val = 3, \ + .intr_raw_status_bit = 4, \ + .intr_polarity_bit = 1, \ + .intr_detection_bit = 2, \ + .intr_detection_width = 2, \ + } + +static const struct pinctrl_pin_desc ipq6018_pins[] = { + PINCTRL_PIN(0, "GPIO_0"), + PINCTRL_PIN(1, "GPIO_1"), + PINCTRL_PIN(2, "GPIO_2"), + PINCTRL_PIN(3, "GPIO_3"), + PINCTRL_PIN(4, "GPIO_4"), + PINCTRL_PIN(5, "GPIO_5"), + PINCTRL_PIN(6, "GPIO_6"), + PINCTRL_PIN(7, "GPIO_7"), + PINCTRL_PIN(8, "GPIO_8"), + PINCTRL_PIN(9, "GPIO_9"), + PINCTRL_PIN(10, "GPIO_10"), + PINCTRL_PIN(11, "GPIO_11"), + PINCTRL_PIN(12, "GPIO_12"), + PINCTRL_PIN(13, "GPIO_13"), + PINCTRL_PIN(14, "GPIO_14"), + PINCTRL_PIN(15, "GPIO_15"), + PINCTRL_PIN(16, "GPIO_16"), + PINCTRL_PIN(17, "GPIO_17"), + PINCTRL_PIN(18, "GPIO_18"), + PINCTRL_PIN(19, "GPIO_19"), + PINCTRL_PIN(20, "GPIO_20"), + PINCTRL_PIN(21, "GPIO_21"), + PINCTRL_PIN(22, "GPIO_22"), + PINCTRL_PIN(23, "GPIO_23"), + PINCTRL_PIN(24, "GPIO_24"), + PINCTRL_PIN(25, "GPIO_25"), + PINCTRL_PIN(26, "GPIO_26"), + PINCTRL_PIN(27, "GPIO_27"), + PINCTRL_PIN(28, "GPIO_28"), + PINCTRL_PIN(29, "GPIO_29"), + PINCTRL_PIN(30, "GPIO_30"), + PINCTRL_PIN(31, "GPIO_31"), + PINCTRL_PIN(32, "GPIO_32"), + PINCTRL_PIN(33, "GPIO_33"), + PINCTRL_PIN(34, "GPIO_34"), + PINCTRL_PIN(35, "GPIO_35"), + PINCTRL_PIN(36, "GPIO_36"), + PINCTRL_PIN(37, "GPIO_37"), + PINCTRL_PIN(38, "GPIO_38"), + PINCTRL_PIN(39, "GPIO_39"), + PINCTRL_PIN(40, "GPIO_40"), + PINCTRL_PIN(41, "GPIO_41"), + PINCTRL_PIN(42, "GPIO_42"), + PINCTRL_PIN(43, "GPIO_43"), + PINCTRL_PIN(44, "GPIO_44"), + PINCTRL_PIN(45, "GPIO_45"), + PINCTRL_PIN(46, "GPIO_46"), + PINCTRL_PIN(47, "GPIO_47"), + PINCTRL_PIN(48, "GPIO_48"), + PINCTRL_PIN(49, "GPIO_49"), + PINCTRL_PIN(50, "GPIO_50"), + PINCTRL_PIN(51, "GPIO_51"), + PINCTRL_PIN(52, "GPIO_52"), + PINCTRL_PIN(53, "GPIO_53"), + PINCTRL_PIN(54, "GPIO_54"), + PINCTRL_PIN(55, "GPIO_55"), + PINCTRL_PIN(56, "GPIO_56"), + PINCTRL_PIN(57, "GPIO_57"), + PINCTRL_PIN(58, "GPIO_58"), + PINCTRL_PIN(59, "GPIO_59"), + PINCTRL_PIN(60, "GPIO_60"), + PINCTRL_PIN(61, "GPIO_61"), + PINCTRL_PIN(62, "GPIO_62"), + PINCTRL_PIN(63, "GPIO_63"), + PINCTRL_PIN(64, "GPIO_64"), + PINCTRL_PIN(65, "GPIO_65"), + PINCTRL_PIN(66, "GPIO_66"), + PINCTRL_PIN(67, "GPIO_67"), + PINCTRL_PIN(68, "GPIO_68"), + PINCTRL_PIN(69, "GPIO_69"), + PINCTRL_PIN(70, "GPIO_70"), + PINCTRL_PIN(71, "GPIO_71"), + PINCTRL_PIN(72, "GPIO_72"), + PINCTRL_PIN(73, "GPIO_73"), + PINCTRL_PIN(74, "GPIO_74"), + PINCTRL_PIN(75, "GPIO_75"), + PINCTRL_PIN(76, "GPIO_76"), + PINCTRL_PIN(77, "GPIO_77"), + PINCTRL_PIN(78, "GPIO_78"), + PINCTRL_PIN(79, "GPIO_79"), +}; + +#define DECLARE_MSM_GPIO_PINS(pin) \ + static const unsigned int gpio##pin##_pins[] = { pin } +DECLARE_MSM_GPIO_PINS(0); +DECLARE_MSM_GPIO_PINS(1); +DECLARE_MSM_GPIO_PINS(2); +DECLARE_MSM_GPIO_PINS(3); +DECLARE_MSM_GPIO_PINS(4); +DECLARE_MSM_GPIO_PINS(5); +DECLARE_MSM_GPIO_PINS(6); +DECLARE_MSM_GPIO_PINS(7); +DECLARE_MSM_GPIO_PINS(8); +DECLARE_MSM_GPIO_PINS(9); +DECLARE_MSM_GPIO_PINS(10); +DECLARE_MSM_GPIO_PINS(11); +DECLARE_MSM_GPIO_PINS(12); +DECLARE_MSM_GPIO_PINS(13); +DECLARE_MSM_GPIO_PINS(14); +DECLARE_MSM_GPIO_PINS(15); +DECLARE_MSM_GPIO_PINS(16); +DECLARE_MSM_GPIO_PINS(17); +DECLARE_MSM_GPIO_PINS(18); +DECLARE_MSM_GPIO_PINS(19); +DECLARE_MSM_GPIO_PINS(20); +DECLARE_MSM_GPIO_PINS(21); +DECLARE_MSM_GPIO_PINS(22); +DECLARE_MSM_GPIO_PINS(23); +DECLARE_MSM_GPIO_PINS(24); +DECLARE_MSM_GPIO_PINS(25); +DECLARE_MSM_GPIO_PINS(26); +DECLARE_MSM_GPIO_PINS(27); +DECLARE_MSM_GPIO_PINS(28); +DECLARE_MSM_GPIO_PINS(29); +DECLARE_MSM_GPIO_PINS(30); +DECLARE_MSM_GPIO_PINS(31); +DECLARE_MSM_GPIO_PINS(32); +DECLARE_MSM_GPIO_PINS(33); +DECLARE_MSM_GPIO_PINS(34); +DECLARE_MSM_GPIO_PINS(35); +DECLARE_MSM_GPIO_PINS(36); +DECLARE_MSM_GPIO_PINS(37); +DECLARE_MSM_GPIO_PINS(38); +DECLARE_MSM_GPIO_PINS(39); +DECLARE_MSM_GPIO_PINS(40); +DECLARE_MSM_GPIO_PINS(41); +DECLARE_MSM_GPIO_PINS(42); +DECLARE_MSM_GPIO_PINS(43); +DECLARE_MSM_GPIO_PINS(44); +DECLARE_MSM_GPIO_PINS(45); +DECLARE_MSM_GPIO_PINS(46); +DECLARE_MSM_GPIO_PINS(47); +DECLARE_MSM_GPIO_PINS(48); +DECLARE_MSM_GPIO_PINS(49); +DECLARE_MSM_GPIO_PINS(50); +DECLARE_MSM_GPIO_PINS(51); +DECLARE_MSM_GPIO_PINS(52); +DECLARE_MSM_GPIO_PINS(53); +DECLARE_MSM_GPIO_PINS(54); +DECLARE_MSM_GPIO_PINS(55); +DECLARE_MSM_GPIO_PINS(56); +DECLARE_MSM_GPIO_PINS(57); +DECLARE_MSM_GPIO_PINS(58); +DECLARE_MSM_GPIO_PINS(59); +DECLARE_MSM_GPIO_PINS(60); +DECLARE_MSM_GPIO_PINS(61); +DECLARE_MSM_GPIO_PINS(62); +DECLARE_MSM_GPIO_PINS(63); +DECLARE_MSM_GPIO_PINS(64); +DECLARE_MSM_GPIO_PINS(65); +DECLARE_MSM_GPIO_PINS(66); +DECLARE_MSM_GPIO_PINS(67); +DECLARE_MSM_GPIO_PINS(68); +DECLARE_MSM_GPIO_PINS(69); +DECLARE_MSM_GPIO_PINS(70); +DECLARE_MSM_GPIO_PINS(71); +DECLARE_MSM_GPIO_PINS(72); +DECLARE_MSM_GPIO_PINS(73); +DECLARE_MSM_GPIO_PINS(74); +DECLARE_MSM_GPIO_PINS(75); +DECLARE_MSM_GPIO_PINS(76); +DECLARE_MSM_GPIO_PINS(77); +DECLARE_MSM_GPIO_PINS(78); +DECLARE_MSM_GPIO_PINS(79); + +enum ipq6018_functions { + msm_mux_atest_char, + msm_mux_atest_char0, + msm_mux_atest_char1, + msm_mux_atest_char2, + msm_mux_atest_char3, + msm_mux_audio0, + msm_mux_audio1, + msm_mux_audio2, + msm_mux_audio3, + msm_mux_audio_rxbclk, + msm_mux_audio_rxfsync, + msm_mux_audio_rxmclk, + msm_mux_audio_rxmclkin, + msm_mux_audio_txbclk, + msm_mux_audio_txfsync, + msm_mux_audio_txmclk, + msm_mux_audio_txmclkin, + msm_mux_blsp0_i2c, + msm_mux_blsp0_spi, + msm_mux_blsp0_uart, + msm_mux_blsp1_i2c, + msm_mux_blsp1_spi, + msm_mux_blsp1_uart, + msm_mux_blsp2_i2c, + msm_mux_blsp2_spi, + msm_mux_blsp2_uart, + msm_mux_blsp3_i2c, + msm_mux_blsp3_spi, + msm_mux_blsp3_uart, + msm_mux_blsp4_i2c, + msm_mux_blsp4_spi, + msm_mux_blsp4_uart, + msm_mux_blsp5_i2c, + msm_mux_blsp5_uart, + msm_mux_burn0, + msm_mux_burn1, + msm_mux_cri_trng, + msm_mux_cri_trng0, + msm_mux_cri_trng1, + msm_mux_cxc0, + msm_mux_cxc1, + msm_mux_dbg_out, + msm_mux_gcc_plltest, + msm_mux_gcc_tlmm, + msm_mux_gpio, + msm_mux_lpass_aud, + msm_mux_lpass_aud0, + msm_mux_lpass_aud1, + msm_mux_lpass_aud2, + msm_mux_lpass_pcm, + msm_mux_lpass_pdm, + msm_mux_mac00, + msm_mux_mac01, + msm_mux_mac10, + msm_mux_mac11, + msm_mux_mac12, + msm_mux_mac13, + msm_mux_mac20, + msm_mux_mac21, + msm_mux_mdc, + msm_mux_mdio, + msm_mux_pcie0_clk, + msm_mux_pcie0_rst, + msm_mux_pcie0_wake, + msm_mux_prng_rosc, + msm_mux_pta1_0, + msm_mux_pta1_1, + msm_mux_pta1_2, + msm_mux_pta2_0, + msm_mux_pta2_1, + msm_mux_pta2_2, + msm_mux_pwm00, + msm_mux_pwm01, + msm_mux_pwm02, + msm_mux_pwm03, + msm_mux_pwm04, + msm_mux_pwm10, + msm_mux_pwm11, + msm_mux_pwm12, + msm_mux_pwm13, + msm_mux_pwm14, + msm_mux_pwm20, + msm_mux_pwm21, + msm_mux_pwm22, + msm_mux_pwm23, + msm_mux_pwm24, + msm_mux_pwm30, + msm_mux_pwm31, + msm_mux_pwm32, + msm_mux_pwm33, + msm_mux_qdss_cti_trig_in_a0, + msm_mux_qdss_cti_trig_in_a1, + msm_mux_qdss_cti_trig_out_a0, + msm_mux_qdss_cti_trig_out_a1, + msm_mux_qdss_cti_trig_in_b0, + msm_mux_qdss_cti_trig_in_b1, + msm_mux_qdss_cti_trig_out_b0, + msm_mux_qdss_cti_trig_out_b1, + msm_mux_qdss_traceclk_a, + msm_mux_qdss_tracectl_a, + msm_mux_qdss_tracedata_a, + msm_mux_qdss_traceclk_b, + msm_mux_qdss_tracectl_b, + msm_mux_qdss_tracedata_b, + msm_mux_qpic_pad, + msm_mux_rx0, + msm_mux_rx1, + msm_mux_rx_swrm, + msm_mux_rx_swrm0, + msm_mux_rx_swrm1, + msm_mux_sd_card, + msm_mux_sd_write, + msm_mux_tsens_max, + msm_mux_tx_swrm, + msm_mux_tx_swrm0, + msm_mux_tx_swrm1, + msm_mux_tx_swrm2, + msm_mux_wci20, + msm_mux_wci21, + msm_mux_wci22, + msm_mux_wci23, + msm_mux_wsa_swrm, + msm_mux__, +}; + +static const char * const blsp3_uart_groups[] = { + "gpio73", "gpio74", "gpio75", "gpio76", +}; + +static const char * const blsp3_i2c_groups[] = { + "gpio73", "gpio74", +}; + +static const char * const blsp3_spi_groups[] = { + "gpio73", "gpio74", "gpio75", "gpio76", "gpio77", "gpio78", "gpio79", +}; + +static const char * const wci20_groups[] = { + "gpio0", "gpio2", +}; + +static const char * const qpic_pad_groups[] = { + "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio9", "gpio10", + "gpio11", "gpio17", "gpio15", "gpio12", "gpio13", "gpio14", "gpio5", + "gpio6", "gpio7", "gpio8", +}; + +static const char * const burn0_groups[] = { + "gpio0", +}; + +static const char * const mac12_groups[] = { + "gpio1", "gpio11", +}; + +static const char * const qdss_tracectl_b_groups[] = { + "gpio1", +}; + +static const char * const burn1_groups[] = { + "gpio1", +}; + +static const char * const qdss_traceclk_b_groups[] = { + "gpio0", +}; + +static const char * const qdss_tracedata_b_groups[] = { + "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7", "gpio8", "gpio9", + "gpio10", "gpio11", "gpio12", "gpio13", "gpio14", "gpio15", "gpio16", + "gpio17", +}; + +static const char * const mac01_groups[] = { + "gpio3", "gpio4", +}; + +static const char * const mac21_groups[] = { + "gpio5", "gpio6", +}; + +static const char * const atest_char_groups[] = { + "gpio9", +}; + +static const char * const cxc0_groups[] = { + "gpio9", "gpio16", +}; + +static const char * const mac13_groups[] = { + "gpio9", "gpio16", +}; + +static const char * const dbg_out_groups[] = { + "gpio9", +}; + +static const char * const wci22_groups[] = { + "gpio11", "gpio17", +}; + +static const char * const pwm00_groups[] = { + "gpio18", +}; + +static const char * const atest_char0_groups[] = { + "gpio18", +}; + +static const char * const wci23_groups[] = { + "gpio18", "gpio19", +}; + +static const char * const mac11_groups[] = { + "gpio18", "gpio19", +}; + +static const char * const pwm10_groups[] = { + "gpio19", +}; + +static const char * const atest_char1_groups[] = { + "gpio19", +}; + +static const char * const pwm20_groups[] = { + "gpio20", +}; + +static const char * const atest_char2_groups[] = { + "gpio20", +}; + +static const char * const pwm30_groups[] = { + "gpio21", +}; + +static const char * const atest_char3_groups[] = { + "gpio21", +}; + +static const char * const audio_txmclk_groups[] = { + "gpio22", +}; + +static const char * const audio_txmclkin_groups[] = { + "gpio22", +}; + +static const char * const pwm02_groups[] = { + "gpio22", +}; + +static const char * const tx_swrm0_groups[] = { + "gpio22", +}; + +static const char * const qdss_cti_trig_out_b0_groups[] = { + "gpio22", +}; + +static const char * const audio_txbclk_groups[] = { + "gpio23", +}; + +static const char * const pwm12_groups[] = { + "gpio23", +}; + +static const char * const wsa_swrm_groups[] = { + "gpio23", "gpio24", +}; + +static const char * const tx_swrm1_groups[] = { + "gpio23", +}; + +static const char * const qdss_cti_trig_in_b0_groups[] = { + "gpio23", +}; + +static const char * const audio_txfsync_groups[] = { + "gpio24", +}; + +static const char * const pwm22_groups[] = { + "gpio24", +}; + +static const char * const tx_swrm2_groups[] = { + "gpio24", +}; + +static const char * const qdss_cti_trig_out_b1_groups[] = { + "gpio24", +}; + +static const char * const audio0_groups[] = { + "gpio25", "gpio32", +}; + +static const char * const pwm32_groups[] = { + "gpio25", +}; + +static const char * const tx_swrm_groups[] = { + "gpio25", +}; + +static const char * const qdss_cti_trig_in_b1_groups[] = { + "gpio25", +}; + +static const char * const audio1_groups[] = { + "gpio26", "gpio33", +}; + +static const char * const pwm04_groups[] = { + "gpio26", +}; + +static const char * const audio2_groups[] = { + "gpio27", +}; + +static const char * const pwm14_groups[] = { + "gpio27", +}; + +static const char * const audio3_groups[] = { + "gpio28", +}; + +static const char * const pwm24_groups[] = { + "gpio28", +}; + +static const char * const audio_rxmclk_groups[] = { + "gpio29", +}; + +static const char * const audio_rxmclkin_groups[] = { + "gpio29", +}; + +static const char * const pwm03_groups[] = { + "gpio29", +}; + +static const char * const lpass_pdm_groups[] = { + "gpio29", "gpio30", "gpio31", "gpio32", +}; + +static const char * const lpass_aud_groups[] = { + "gpio29", +}; + +static const char * const qdss_cti_trig_in_a1_groups[] = { + "gpio29", +}; + +static const char * const audio_rxbclk_groups[] = { + "gpio30", +}; + +static const char * const pwm13_groups[] = { + "gpio30", +}; + +static const char * const lpass_aud0_groups[] = { + "gpio30", +}; + +static const char * const rx_swrm_groups[] = { + "gpio30", +}; + +static const char * const qdss_cti_trig_out_a1_groups[] = { + "gpio30", +}; + +static const char * const audio_rxfsync_groups[] = { + "gpio31", +}; + +static const char * const pwm23_groups[] = { + "gpio31", +}; + +static const char * const lpass_aud1_groups[] = { + "gpio31", +}; + +static const char * const rx_swrm0_groups[] = { + "gpio31", +}; + +static const char * const qdss_cti_trig_in_a0_groups[] = { + "gpio31", +}; + +static const char * const pwm33_groups[] = { + "gpio32", +}; + +static const char * const lpass_aud2_groups[] = { + "gpio32", +}; + +static const char * const rx_swrm1_groups[] = { + "gpio32", +}; + +static const char * const qdss_cti_trig_out_a0_groups[] = { + "gpio32", +}; + +static const char * const lpass_pcm_groups[] = { + "gpio34", "gpio35", "gpio36", "gpio37", +}; + +static const char * const mac10_groups[] = { + "gpio34", "gpio35", +}; + +static const char * const mac00_groups[] = { + "gpio34", "gpio35", +}; + +static const char * const mac20_groups[] = { + "gpio36", "gpio37", +}; + +static const char * const blsp0_uart_groups[] = { + "gpio38", "gpio39", "gpio40", "gpio41", +}; + +static const char * const blsp0_i2c_groups[] = { + "gpio38", "gpio39", +}; + +static const char * const blsp0_spi_groups[] = { + "gpio38", "gpio39", "gpio40", "gpio41", +}; + +static const char * const blsp2_uart_groups[] = { + "gpio42", "gpio43", "gpio44", "gpio45", +}; + +static const char * const blsp2_i2c_groups[] = { + "gpio42", "gpio43", +}; + +static const char * const blsp2_spi_groups[] = { + "gpio42", "gpio43", "gpio44", "gpio45", +}; + +static const char * const blsp5_i2c_groups[] = { + "gpio46", "gpio47", +}; + +static const char * const blsp5_uart_groups[] = { + "gpio48", "gpio49", +}; + +static const char * const qdss_traceclk_a_groups[] = { + "gpio48", +}; + +static const char * const qdss_tracectl_a_groups[] = { + "gpio49", +}; + +static const char * const pwm01_groups[] = { + "gpio50", +}; + +static const char * const pta1_1_groups[] = { + "gpio51", +}; + +static const char * const pwm11_groups[] = { + "gpio51", +}; + +static const char * const rx1_groups[] = { + "gpio51", +}; + +static const char * const pta1_2_groups[] = { + "gpio52", +}; + +static const char * const pwm21_groups[] = { + "gpio52", +}; + +static const char * const pta1_0_groups[] = { + "gpio53", +}; + +static const char * const pwm31_groups[] = { + "gpio53", +}; + +static const char * const prng_rosc_groups[] = { + "gpio53", +}; + +static const char * const blsp4_uart_groups[] = { + "gpio55", "gpio56", "gpio57", "gpio58", +}; + +static const char * const blsp4_i2c_groups[] = { + "gpio55", "gpio56", +}; + +static const char * const blsp4_spi_groups[] = { + "gpio55", "gpio56", "gpio57", "gpio58", +}; + +static const char * const pcie0_clk_groups[] = { + "gpio59", +}; + +static const char * const cri_trng0_groups[] = { + "gpio59", +}; + +static const char * const pcie0_rst_groups[] = { + "gpio60", +}; + +static const char * const cri_trng1_groups[] = { + "gpio60", +}; + +static const char * const pcie0_wake_groups[] = { + "gpio61", +}; + +static const char * const cri_trng_groups[] = { + "gpio61", +}; + +static const char * const sd_card_groups[] = { + "gpio62", +}; + +static const char * const sd_write_groups[] = { + "gpio63", +}; + +static const char * const rx0_groups[] = { + "gpio63", +}; + +static const char * const tsens_max_groups[] = { + "gpio63", +}; + +static const char * const mdc_groups[] = { + "gpio64", +}; + +static const char * const qdss_tracedata_a_groups[] = { + "gpio64", "gpio65", "gpio66", "gpio67", "gpio68", "gpio69", "gpio70", + "gpio71", "gpio72", "gpio73", "gpio74", "gpio75", "gpio76", "gpio77", + "gpio78", "gpio79", +}; + +static const char * const mdio_groups[] = { + "gpio65", +}; + +static const char * const pta2_0_groups[] = { + "gpio66", +}; + +static const char * const wci21_groups[] = { + "gpio66", "gpio68", +}; + +static const char * const cxc1_groups[] = { + "gpio66", "gpio68", +}; + +static const char * const pta2_1_groups[] = { + "gpio67", +}; + +static const char * const pta2_2_groups[] = { + "gpio68", +}; + +static const char * const blsp1_uart_groups[] = { + "gpio69", "gpio70", "gpio71", "gpio72", +}; + +static const char * const blsp1_i2c_groups[] = { + "gpio69", "gpio70", +}; + +static const char * const blsp1_spi_groups[] = { + "gpio69", "gpio70", "gpio71", "gpio72", +}; + +static const char * const gcc_plltest_groups[] = { + "gpio69", "gpio71", +}; + +static const char * const gcc_tlmm_groups[] = { + "gpio70", +}; + +static const char * const gpio_groups[] = { + "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7", + "gpio8", "gpio9", "gpio10", "gpio11", "gpio12", "gpio13", "gpio14", + "gpio15", "gpio16", "gpio17", "gpio18", "gpio19", "gpio20", "gpio21", + "gpio22", "gpio23", "gpio24", "gpio25", "gpio26", "gpio27", "gpio28", + "gpio29", "gpio30", "gpio31", "gpio32", "gpio33", "gpio34", "gpio35", + "gpio36", "gpio37", "gpio38", "gpio39", "gpio40", "gpio41", "gpio42", + "gpio43", "gpio44", "gpio45", "gpio46", "gpio47", "gpio48", "gpio49", + "gpio50", "gpio51", "gpio52", "gpio53", "gpio54", "gpio55", "gpio56", + "gpio57", "gpio58", "gpio59", "gpio60", "gpio61", "gpio62", "gpio63", + "gpio64", "gpio65", "gpio66", "gpio67", "gpio68", "gpio69", "gpio70", + "gpio71", "gpio72", "gpio73", "gpio74", "gpio75", "gpio76", "gpio77", + "gpio78", "gpio79", +}; + +static const struct pinfunction ipq6018_functions[] = { + MSM_PIN_FUNCTION(atest_char), + MSM_PIN_FUNCTION(atest_char0), + MSM_PIN_FUNCTION(atest_char1), + MSM_PIN_FUNCTION(atest_char2), + MSM_PIN_FUNCTION(atest_char3), + MSM_PIN_FUNCTION(audio0), + MSM_PIN_FUNCTION(audio1), + MSM_PIN_FUNCTION(audio2), + MSM_PIN_FUNCTION(audio3), + MSM_PIN_FUNCTION(audio_rxbclk), + MSM_PIN_FUNCTION(audio_rxfsync), + MSM_PIN_FUNCTION(audio_rxmclk), + MSM_PIN_FUNCTION(audio_rxmclkin), + MSM_PIN_FUNCTION(audio_txbclk), + MSM_PIN_FUNCTION(audio_txfsync), + MSM_PIN_FUNCTION(audio_txmclk), + MSM_PIN_FUNCTION(audio_txmclkin), + MSM_PIN_FUNCTION(blsp0_i2c), + MSM_PIN_FUNCTION(blsp0_spi), + MSM_PIN_FUNCTION(blsp0_uart), + MSM_PIN_FUNCTION(blsp1_i2c), + MSM_PIN_FUNCTION(blsp1_spi), + MSM_PIN_FUNCTION(blsp1_uart), + MSM_PIN_FUNCTION(blsp2_i2c), + MSM_PIN_FUNCTION(blsp2_spi), + MSM_PIN_FUNCTION(blsp2_uart), + MSM_PIN_FUNCTION(blsp3_i2c), + MSM_PIN_FUNCTION(blsp3_spi), + MSM_PIN_FUNCTION(blsp3_uart), + MSM_PIN_FUNCTION(blsp4_i2c), + MSM_PIN_FUNCTION(blsp4_spi), + MSM_PIN_FUNCTION(blsp4_uart), + MSM_PIN_FUNCTION(blsp5_i2c), + MSM_PIN_FUNCTION(blsp5_uart), + MSM_PIN_FUNCTION(burn0), + MSM_PIN_FUNCTION(burn1), + MSM_PIN_FUNCTION(cri_trng), + MSM_PIN_FUNCTION(cri_trng0), + MSM_PIN_FUNCTION(cri_trng1), + MSM_PIN_FUNCTION(cxc0), + MSM_PIN_FUNCTION(cxc1), + MSM_PIN_FUNCTION(dbg_out), + MSM_PIN_FUNCTION(gcc_plltest), + MSM_PIN_FUNCTION(gcc_tlmm), + MSM_PIN_FUNCTION(gpio), + MSM_PIN_FUNCTION(lpass_aud), + MSM_PIN_FUNCTION(lpass_aud0), + MSM_PIN_FUNCTION(lpass_aud1), + MSM_PIN_FUNCTION(lpass_aud2), + MSM_PIN_FUNCTION(lpass_pcm), + MSM_PIN_FUNCTION(lpass_pdm), + MSM_PIN_FUNCTION(mac00), + MSM_PIN_FUNCTION(mac01), + MSM_PIN_FUNCTION(mac10), + MSM_PIN_FUNCTION(mac11), + MSM_PIN_FUNCTION(mac12), + MSM_PIN_FUNCTION(mac13), + MSM_PIN_FUNCTION(mac20), + MSM_PIN_FUNCTION(mac21), + MSM_PIN_FUNCTION(mdc), + MSM_PIN_FUNCTION(mdio), + MSM_PIN_FUNCTION(pcie0_clk), + MSM_PIN_FUNCTION(pcie0_rst), + MSM_PIN_FUNCTION(pcie0_wake), + MSM_PIN_FUNCTION(prng_rosc), + MSM_PIN_FUNCTION(pta1_0), + MSM_PIN_FUNCTION(pta1_1), + MSM_PIN_FUNCTION(pta1_2), + MSM_PIN_FUNCTION(pta2_0), + MSM_PIN_FUNCTION(pta2_1), + MSM_PIN_FUNCTION(pta2_2), + MSM_PIN_FUNCTION(pwm00), + MSM_PIN_FUNCTION(pwm01), + MSM_PIN_FUNCTION(pwm02), + MSM_PIN_FUNCTION(pwm03), + MSM_PIN_FUNCTION(pwm04), + MSM_PIN_FUNCTION(pwm10), + MSM_PIN_FUNCTION(pwm11), + MSM_PIN_FUNCTION(pwm12), + MSM_PIN_FUNCTION(pwm13), + MSM_PIN_FUNCTION(pwm14), + MSM_PIN_FUNCTION(pwm20), + MSM_PIN_FUNCTION(pwm21), + MSM_PIN_FUNCTION(pwm22), + MSM_PIN_FUNCTION(pwm23), + MSM_PIN_FUNCTION(pwm24), + MSM_PIN_FUNCTION(pwm30), + MSM_PIN_FUNCTION(pwm31), + MSM_PIN_FUNCTION(pwm32), + MSM_PIN_FUNCTION(pwm33), + MSM_PIN_FUNCTION(qdss_cti_trig_in_a0), + MSM_PIN_FUNCTION(qdss_cti_trig_in_a1), + MSM_PIN_FUNCTION(qdss_cti_trig_out_a0), + MSM_PIN_FUNCTION(qdss_cti_trig_out_a1), + MSM_PIN_FUNCTION(qdss_cti_trig_in_b0), + MSM_PIN_FUNCTION(qdss_cti_trig_in_b1), + MSM_PIN_FUNCTION(qdss_cti_trig_out_b0), + MSM_PIN_FUNCTION(qdss_cti_trig_out_b1), + MSM_PIN_FUNCTION(qdss_traceclk_a), + MSM_PIN_FUNCTION(qdss_tracectl_a), + MSM_PIN_FUNCTION(qdss_tracedata_a), + MSM_PIN_FUNCTION(qdss_traceclk_b), + MSM_PIN_FUNCTION(qdss_tracectl_b), + MSM_PIN_FUNCTION(qdss_tracedata_b), + MSM_PIN_FUNCTION(qpic_pad), + MSM_PIN_FUNCTION(rx0), + MSM_PIN_FUNCTION(rx1), + MSM_PIN_FUNCTION(rx_swrm), + MSM_PIN_FUNCTION(rx_swrm0), + MSM_PIN_FUNCTION(rx_swrm1), + MSM_PIN_FUNCTION(sd_card), + MSM_PIN_FUNCTION(sd_write), + MSM_PIN_FUNCTION(tsens_max), + MSM_PIN_FUNCTION(tx_swrm), + MSM_PIN_FUNCTION(tx_swrm0), + MSM_PIN_FUNCTION(tx_swrm1), + MSM_PIN_FUNCTION(tx_swrm2), + MSM_PIN_FUNCTION(wci20), + MSM_PIN_FUNCTION(wci21), + MSM_PIN_FUNCTION(wci22), + MSM_PIN_FUNCTION(wci23), + MSM_PIN_FUNCTION(wsa_swrm), +}; + +static const struct msm_pingroup ipq6018_groups[] = { + PINGROUP(0, qpic_pad, wci20, qdss_traceclk_b, _, burn0, _, _, _, _), + PINGROUP(1, qpic_pad, mac12, qdss_tracectl_b, _, burn1, _, _, _, _), + PINGROUP(2, qpic_pad, wci20, qdss_tracedata_b, _, _, _, _, _, _), + PINGROUP(3, qpic_pad, mac01, qdss_tracedata_b, _, _, _, _, _, _), + PINGROUP(4, qpic_pad, mac01, qdss_tracedata_b, _, _, _, _, _, _), + PINGROUP(5, qpic_pad, mac21, qdss_tracedata_b, _, _, _, _, _, _), + PINGROUP(6, qpic_pad, mac21, qdss_tracedata_b, _, _, _, _, _, _), + PINGROUP(7, qpic_pad, qdss_tracedata_b, _, _, _, _, _, _, _), + PINGROUP(8, qpic_pad, qdss_tracedata_b, _, _, _, _, _, _, _), + PINGROUP(9, qpic_pad, atest_char, cxc0, mac13, dbg_out, qdss_tracedata_b, _, _, _), + PINGROUP(10, qpic_pad, qdss_tracedata_b, _, _, _, _, _, _, _), + PINGROUP(11, qpic_pad, wci22, mac12, qdss_tracedata_b, _, _, _, _, _), + PINGROUP(12, qpic_pad, qdss_tracedata_b, _, _, _, _, _, _, _), + PINGROUP(13, qpic_pad, qdss_tracedata_b, _, _, _, _, _, _, _), + PINGROUP(14, qpic_pad, qdss_tracedata_b, _, _, _, _, _, _, _), + PINGROUP(15, qpic_pad, qdss_tracedata_b, _, _, _, _, _, _, _), + PINGROUP(16, qpic_pad, cxc0, mac13, qdss_tracedata_b, _, _, _, _, _), + PINGROUP(17, qpic_pad, qdss_tracedata_b, wci22, _, _, _, _, _, _), + PINGROUP(18, pwm00, atest_char0, wci23, mac11, _, _, _, _, _), + PINGROUP(19, pwm10, atest_char1, wci23, mac11, _, _, _, _, _), + PINGROUP(20, pwm20, atest_char2, _, _, _, _, _, _, _), + PINGROUP(21, pwm30, atest_char3, _, _, _, _, _, _, _), + PINGROUP(22, audio_txmclk, audio_txmclkin, pwm02, tx_swrm0, _, qdss_cti_trig_out_b0, _, _, _), + PINGROUP(23, audio_txbclk, pwm12, wsa_swrm, tx_swrm1, _, qdss_cti_trig_in_b0, _, _, _), + PINGROUP(24, audio_txfsync, pwm22, wsa_swrm, tx_swrm2, _, qdss_cti_trig_out_b1, _, _, _), + PINGROUP(25, audio0, pwm32, tx_swrm, _, qdss_cti_trig_in_b1, _, _, _, _), + PINGROUP(26, audio1, pwm04, _, _, _, _, _, _, _), + PINGROUP(27, audio2, pwm14, _, _, _, _, _, _, _), + PINGROUP(28, audio3, pwm24, _, _, _, _, _, _, _), + PINGROUP(29, audio_rxmclk, audio_rxmclkin, pwm03, lpass_pdm, lpass_aud, qdss_cti_trig_in_a1, _, _, _), + PINGROUP(30, audio_rxbclk, pwm13, lpass_pdm, lpass_aud0, rx_swrm, _, qdss_cti_trig_out_a1, _, _), + PINGROUP(31, audio_rxfsync, pwm23, lpass_pdm, lpass_aud1, rx_swrm0, _, qdss_cti_trig_in_a0, _, _), + PINGROUP(32, audio0, pwm33, lpass_pdm, lpass_aud2, rx_swrm1, _, qdss_cti_trig_out_a0, _, _), + PINGROUP(33, audio1, _, _, _, _, _, _, _, _), + PINGROUP(34, lpass_pcm, mac10, mac00, _, _, _, _, _, _), + PINGROUP(35, lpass_pcm, mac10, mac00, _, _, _, _, _, _), + PINGROUP(36, lpass_pcm, mac20, _, _, _, _, _, _, _), + PINGROUP(37, lpass_pcm, mac20, _, _, _, _, _, _, _), + PINGROUP(38, blsp0_uart, blsp0_i2c, blsp0_spi, _, _, _, _, _, _), + PINGROUP(39, blsp0_uart, blsp0_i2c, blsp0_spi, _, _, _, _, _, _), + PINGROUP(40, blsp0_uart, blsp0_spi, _, _, _, _, _, _, _), + PINGROUP(41, blsp0_uart, blsp0_spi, _, _, _, _, _, _, _), + PINGROUP(42, blsp2_uart, blsp2_i2c, blsp2_spi, _, _, _, _, _, _), + PINGROUP(43, blsp2_uart, blsp2_i2c, blsp2_spi, _, _, _, _, _, _), + PINGROUP(44, blsp2_uart, blsp2_spi, _, _, _, _, _, _, _), + PINGROUP(45, blsp2_uart, blsp2_spi, _, _, _, _, _, _, _), + PINGROUP(46, blsp5_i2c, _, _, _, _, _, _, _, _), + PINGROUP(47, blsp5_i2c, _, _, _, _, _, _, _, _), + PINGROUP(48, blsp5_uart, _, qdss_traceclk_a, _, _, _, _, _, _), + PINGROUP(49, blsp5_uart, _, qdss_tracectl_a, _, _, _, _, _, _), + PINGROUP(50, pwm01, _, _, _, _, _, _, _, _), + PINGROUP(51, pta1_1, pwm11, _, rx1, _, _, _, _, _), + PINGROUP(52, pta1_2, pwm21, _, _, _, _, _, _, _), + PINGROUP(53, pta1_0, pwm31, prng_rosc, _, _, _, _, _, _), + PINGROUP(54, _, _, _, _, _, _, _, _, _), + PINGROUP(55, blsp4_uart, blsp4_i2c, blsp4_spi, _, _, _, _, _, _), + PINGROUP(56, blsp4_uart, blsp4_i2c, blsp4_spi, _, _, _, _, _, _), + PINGROUP(57, blsp4_uart, blsp4_spi, _, _, _, _, _, _, _), + PINGROUP(58, blsp4_uart, blsp4_spi, _, _, _, _, _, _, _), + PINGROUP(59, pcie0_clk, _, _, cri_trng0, _, _, _, _, _), + PINGROUP(60, pcie0_rst, _, _, cri_trng1, _, _, _, _, _), + PINGROUP(61, pcie0_wake, _, _, cri_trng, _, _, _, _, _), + PINGROUP(62, sd_card, _, _, _, _, _, _, _, _), + PINGROUP(63, sd_write, rx0, _, tsens_max, _, _, _, _, _), + PINGROUP(64, mdc, _, qdss_tracedata_a, _, _, _, _, _, _), + PINGROUP(65, mdio, _, qdss_tracedata_a, _, _, _, _, _, _), + PINGROUP(66, pta2_0, wci21, cxc1, qdss_tracedata_a, _, _, _, _, _), + PINGROUP(67, pta2_1, qdss_tracedata_a, _, _, _, _, _, _, _), + PINGROUP(68, pta2_2, wci21, cxc1, qdss_tracedata_a, _, _, _, _, _), + PINGROUP(69, blsp1_uart, blsp1_i2c, blsp1_spi, gcc_plltest, qdss_tracedata_a, _, _, _, _), + PINGROUP(70, blsp1_uart, blsp1_i2c, blsp1_spi, gcc_tlmm, qdss_tracedata_a, _, _, _, _), + PINGROUP(71, blsp1_uart, blsp1_spi, gcc_plltest, qdss_tracedata_a, _, _, _, _, _), + PINGROUP(72, blsp1_uart, blsp1_spi, qdss_tracedata_a, _, _, _, _, _, _), + PINGROUP(73, blsp3_uart, blsp3_i2c, blsp3_spi, _, qdss_tracedata_a, _, _, _, _), + PINGROUP(74, blsp3_uart, blsp3_i2c, blsp3_spi, _, qdss_tracedata_a, _, _, _, _), + PINGROUP(75, blsp3_uart, blsp3_spi, _, qdss_tracedata_a, _, _, _, _, _), + PINGROUP(76, blsp3_uart, blsp3_spi, _, qdss_tracedata_a, _, _, _, _, _), + PINGROUP(77, blsp3_spi, _, qdss_tracedata_a, _, _, _, _, _, _), + PINGROUP(78, blsp3_spi, _, qdss_tracedata_a, _, _, _, _, _, _), + PINGROUP(79, blsp3_spi, _, qdss_tracedata_a, _, _, _, _, _, _), +}; + +static const struct msm_pinctrl_soc_data ipq6018_pinctrl = { + .pins = ipq6018_pins, + .npins = ARRAY_SIZE(ipq6018_pins), + .functions = ipq6018_functions, + .nfunctions = ARRAY_SIZE(ipq6018_functions), + .groups = ipq6018_groups, + .ngroups = ARRAY_SIZE(ipq6018_groups), + .ngpios = 80, +}; + +static int ipq6018_pinctrl_probe(struct platform_device *pdev) +{ + return msm_pinctrl_probe(pdev, &ipq6018_pinctrl); +} + +static const struct of_device_id ipq6018_pinctrl_of_match[] = { + { .compatible = "qcom,ipq6018-pinctrl", }, + { }, +}; + +static struct platform_driver ipq6018_pinctrl_driver = { + .driver = { + .name = "ipq6018-pinctrl", + .of_match_table = ipq6018_pinctrl_of_match, + }, + .probe = ipq6018_pinctrl_probe, + .remove = msm_pinctrl_remove, +}; + +static int __init ipq6018_pinctrl_init(void) +{ + return platform_driver_register(&ipq6018_pinctrl_driver); +} +arch_initcall(ipq6018_pinctrl_init); + +static void __exit ipq6018_pinctrl_exit(void) +{ + platform_driver_unregister(&ipq6018_pinctrl_driver); +} +module_exit(ipq6018_pinctrl_exit); + +MODULE_DESCRIPTION("QTI ipq6018 pinctrl driver"); +MODULE_LICENSE("GPL v2"); +MODULE_DEVICE_TABLE(of, ipq6018_pinctrl_of_match); diff --git a/drivers/pinctrl/qcom/pinctrl-ipq8064.c b/drivers/pinctrl/qcom/pinctrl-ipq8064.c new file mode 100644 index 0000000000..e2bb94e86a --- /dev/null +++ b/drivers/pinctrl/qcom/pinctrl-ipq8064.c @@ -0,0 +1,652 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2014, The Linux Foundation. All rights reserved. + */ + +#include <linux/module.h> +#include <linux/of.h> +#include <linux/platform_device.h> + +#include "pinctrl-msm.h" + +static const struct pinctrl_pin_desc ipq8064_pins[] = { + PINCTRL_PIN(0, "GPIO_0"), + PINCTRL_PIN(1, "GPIO_1"), + PINCTRL_PIN(2, "GPIO_2"), + PINCTRL_PIN(3, "GPIO_3"), + PINCTRL_PIN(4, "GPIO_4"), + PINCTRL_PIN(5, "GPIO_5"), + PINCTRL_PIN(6, "GPIO_6"), + PINCTRL_PIN(7, "GPIO_7"), + PINCTRL_PIN(8, "GPIO_8"), + PINCTRL_PIN(9, "GPIO_9"), + PINCTRL_PIN(10, "GPIO_10"), + PINCTRL_PIN(11, "GPIO_11"), + PINCTRL_PIN(12, "GPIO_12"), + PINCTRL_PIN(13, "GPIO_13"), + PINCTRL_PIN(14, "GPIO_14"), + PINCTRL_PIN(15, "GPIO_15"), + PINCTRL_PIN(16, "GPIO_16"), + PINCTRL_PIN(17, "GPIO_17"), + PINCTRL_PIN(18, "GPIO_18"), + PINCTRL_PIN(19, "GPIO_19"), + PINCTRL_PIN(20, "GPIO_20"), + PINCTRL_PIN(21, "GPIO_21"), + PINCTRL_PIN(22, "GPIO_22"), + PINCTRL_PIN(23, "GPIO_23"), + PINCTRL_PIN(24, "GPIO_24"), + PINCTRL_PIN(25, "GPIO_25"), + PINCTRL_PIN(26, "GPIO_26"), + PINCTRL_PIN(27, "GPIO_27"), + PINCTRL_PIN(28, "GPIO_28"), + PINCTRL_PIN(29, "GPIO_29"), + PINCTRL_PIN(30, "GPIO_30"), + PINCTRL_PIN(31, "GPIO_31"), + PINCTRL_PIN(32, "GPIO_32"), + PINCTRL_PIN(33, "GPIO_33"), + PINCTRL_PIN(34, "GPIO_34"), + PINCTRL_PIN(35, "GPIO_35"), + PINCTRL_PIN(36, "GPIO_36"), + PINCTRL_PIN(37, "GPIO_37"), + PINCTRL_PIN(38, "GPIO_38"), + PINCTRL_PIN(39, "GPIO_39"), + PINCTRL_PIN(40, "GPIO_40"), + PINCTRL_PIN(41, "GPIO_41"), + PINCTRL_PIN(42, "GPIO_42"), + PINCTRL_PIN(43, "GPIO_43"), + PINCTRL_PIN(44, "GPIO_44"), + PINCTRL_PIN(45, "GPIO_45"), + PINCTRL_PIN(46, "GPIO_46"), + PINCTRL_PIN(47, "GPIO_47"), + PINCTRL_PIN(48, "GPIO_48"), + PINCTRL_PIN(49, "GPIO_49"), + PINCTRL_PIN(50, "GPIO_50"), + PINCTRL_PIN(51, "GPIO_51"), + PINCTRL_PIN(52, "GPIO_52"), + PINCTRL_PIN(53, "GPIO_53"), + PINCTRL_PIN(54, "GPIO_54"), + PINCTRL_PIN(55, "GPIO_55"), + PINCTRL_PIN(56, "GPIO_56"), + PINCTRL_PIN(57, "GPIO_57"), + PINCTRL_PIN(58, "GPIO_58"), + PINCTRL_PIN(59, "GPIO_59"), + PINCTRL_PIN(60, "GPIO_60"), + PINCTRL_PIN(61, "GPIO_61"), + PINCTRL_PIN(62, "GPIO_62"), + PINCTRL_PIN(63, "GPIO_63"), + PINCTRL_PIN(64, "GPIO_64"), + PINCTRL_PIN(65, "GPIO_65"), + PINCTRL_PIN(66, "GPIO_66"), + PINCTRL_PIN(67, "GPIO_67"), + PINCTRL_PIN(68, "GPIO_68"), + + PINCTRL_PIN(69, "SDC3_CLK"), + PINCTRL_PIN(70, "SDC3_CMD"), + PINCTRL_PIN(71, "SDC3_DATA"), +}; + +#define DECLARE_IPQ_GPIO_PINS(pin) static const unsigned int gpio##pin##_pins[] = { pin } +DECLARE_IPQ_GPIO_PINS(0); +DECLARE_IPQ_GPIO_PINS(1); +DECLARE_IPQ_GPIO_PINS(2); +DECLARE_IPQ_GPIO_PINS(3); +DECLARE_IPQ_GPIO_PINS(4); +DECLARE_IPQ_GPIO_PINS(5); +DECLARE_IPQ_GPIO_PINS(6); +DECLARE_IPQ_GPIO_PINS(7); +DECLARE_IPQ_GPIO_PINS(8); +DECLARE_IPQ_GPIO_PINS(9); +DECLARE_IPQ_GPIO_PINS(10); +DECLARE_IPQ_GPIO_PINS(11); +DECLARE_IPQ_GPIO_PINS(12); +DECLARE_IPQ_GPIO_PINS(13); +DECLARE_IPQ_GPIO_PINS(14); +DECLARE_IPQ_GPIO_PINS(15); +DECLARE_IPQ_GPIO_PINS(16); +DECLARE_IPQ_GPIO_PINS(17); +DECLARE_IPQ_GPIO_PINS(18); +DECLARE_IPQ_GPIO_PINS(19); +DECLARE_IPQ_GPIO_PINS(20); +DECLARE_IPQ_GPIO_PINS(21); +DECLARE_IPQ_GPIO_PINS(22); +DECLARE_IPQ_GPIO_PINS(23); +DECLARE_IPQ_GPIO_PINS(24); +DECLARE_IPQ_GPIO_PINS(25); +DECLARE_IPQ_GPIO_PINS(26); +DECLARE_IPQ_GPIO_PINS(27); +DECLARE_IPQ_GPIO_PINS(28); +DECLARE_IPQ_GPIO_PINS(29); +DECLARE_IPQ_GPIO_PINS(30); +DECLARE_IPQ_GPIO_PINS(31); +DECLARE_IPQ_GPIO_PINS(32); +DECLARE_IPQ_GPIO_PINS(33); +DECLARE_IPQ_GPIO_PINS(34); +DECLARE_IPQ_GPIO_PINS(35); +DECLARE_IPQ_GPIO_PINS(36); +DECLARE_IPQ_GPIO_PINS(37); +DECLARE_IPQ_GPIO_PINS(38); +DECLARE_IPQ_GPIO_PINS(39); +DECLARE_IPQ_GPIO_PINS(40); +DECLARE_IPQ_GPIO_PINS(41); +DECLARE_IPQ_GPIO_PINS(42); +DECLARE_IPQ_GPIO_PINS(43); +DECLARE_IPQ_GPIO_PINS(44); +DECLARE_IPQ_GPIO_PINS(45); +DECLARE_IPQ_GPIO_PINS(46); +DECLARE_IPQ_GPIO_PINS(47); +DECLARE_IPQ_GPIO_PINS(48); +DECLARE_IPQ_GPIO_PINS(49); +DECLARE_IPQ_GPIO_PINS(50); +DECLARE_IPQ_GPIO_PINS(51); +DECLARE_IPQ_GPIO_PINS(52); +DECLARE_IPQ_GPIO_PINS(53); +DECLARE_IPQ_GPIO_PINS(54); +DECLARE_IPQ_GPIO_PINS(55); +DECLARE_IPQ_GPIO_PINS(56); +DECLARE_IPQ_GPIO_PINS(57); +DECLARE_IPQ_GPIO_PINS(58); +DECLARE_IPQ_GPIO_PINS(59); +DECLARE_IPQ_GPIO_PINS(60); +DECLARE_IPQ_GPIO_PINS(61); +DECLARE_IPQ_GPIO_PINS(62); +DECLARE_IPQ_GPIO_PINS(63); +DECLARE_IPQ_GPIO_PINS(64); +DECLARE_IPQ_GPIO_PINS(65); +DECLARE_IPQ_GPIO_PINS(66); +DECLARE_IPQ_GPIO_PINS(67); +DECLARE_IPQ_GPIO_PINS(68); + +static const unsigned int sdc3_clk_pins[] = { 69 }; +static const unsigned int sdc3_cmd_pins[] = { 70 }; +static const unsigned int sdc3_data_pins[] = { 71 }; + +#define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7, f8, f9, f10) \ + { \ + .grp = PINCTRL_PINGROUP("gpio" #id, \ + gpio##id##_pins, \ + ARRAY_SIZE(gpio##id##_pins)), \ + .funcs = (int[]){ \ + IPQ_MUX_gpio, \ + IPQ_MUX_##f1, \ + IPQ_MUX_##f2, \ + IPQ_MUX_##f3, \ + IPQ_MUX_##f4, \ + IPQ_MUX_##f5, \ + IPQ_MUX_##f6, \ + IPQ_MUX_##f7, \ + IPQ_MUX_##f8, \ + IPQ_MUX_##f9, \ + IPQ_MUX_##f10, \ + }, \ + .nfuncs = 11, \ + .ctl_reg = 0x1000 + 0x10 * id, \ + .io_reg = 0x1004 + 0x10 * id, \ + .intr_cfg_reg = 0x1008 + 0x10 * id, \ + .intr_status_reg = 0x100c + 0x10 * id, \ + .intr_target_reg = 0x400 + 0x4 * id, \ + .mux_bit = 2, \ + .pull_bit = 0, \ + .drv_bit = 6, \ + .oe_bit = 9, \ + .in_bit = 0, \ + .out_bit = 1, \ + .intr_enable_bit = 0, \ + .intr_status_bit = 0, \ + .intr_ack_high = 1, \ + .intr_target_bit = 0, \ + .intr_target_kpss_val = 4, \ + .intr_raw_status_bit = 3, \ + .intr_polarity_bit = 1, \ + .intr_detection_bit = 2, \ + .intr_detection_width = 1, \ + } + +#define SDC_PINGROUP(pg_name, ctl, pull, drv) \ + { \ + .grp = PINCTRL_PINGROUP(#pg_name, \ + pg_name##_pins, \ + ARRAY_SIZE(pg_name##_pins)), \ + .ctl_reg = ctl, \ + .io_reg = 0, \ + .intr_cfg_reg = 0, \ + .intr_status_reg = 0, \ + .intr_target_reg = 0, \ + .mux_bit = -1, \ + .pull_bit = pull, \ + .drv_bit = drv, \ + .oe_bit = -1, \ + .in_bit = -1, \ + .out_bit = -1, \ + .intr_enable_bit = -1, \ + .intr_status_bit = -1, \ + .intr_target_bit = -1, \ + .intr_target_kpss_val = -1, \ + .intr_raw_status_bit = -1, \ + .intr_polarity_bit = -1, \ + .intr_detection_bit = -1, \ + .intr_detection_width = -1, \ + } + +enum ipq8064_functions { + IPQ_MUX_gpio, + IPQ_MUX_mdio, + IPQ_MUX_mi2s, + IPQ_MUX_pdm, + IPQ_MUX_ssbi, + IPQ_MUX_spmi, + IPQ_MUX_audio_pcm, + IPQ_MUX_gsbi1, + IPQ_MUX_gsbi2, + IPQ_MUX_gsbi4, + IPQ_MUX_gsbi5, + IPQ_MUX_gsbi5_spi_cs1, + IPQ_MUX_gsbi5_spi_cs2, + IPQ_MUX_gsbi5_spi_cs3, + IPQ_MUX_gsbi6, + IPQ_MUX_gsbi7, + IPQ_MUX_nss_spi, + IPQ_MUX_sdc1, + IPQ_MUX_spdif, + IPQ_MUX_nand, + IPQ_MUX_tsif1, + IPQ_MUX_tsif2, + IPQ_MUX_usb_fs_n, + IPQ_MUX_usb_fs, + IPQ_MUX_usb2_hsic, + IPQ_MUX_rgmii2, + IPQ_MUX_sata, + IPQ_MUX_pcie1_rst, + IPQ_MUX_pcie1_prsnt, + IPQ_MUX_pcie1_pwrflt, + IPQ_MUX_pcie1_pwren_n, + IPQ_MUX_pcie1_pwren, + IPQ_MUX_pcie1_clk_req, + IPQ_MUX_pcie2_rst, + IPQ_MUX_pcie2_prsnt, + IPQ_MUX_pcie2_pwrflt, + IPQ_MUX_pcie2_pwren_n, + IPQ_MUX_pcie2_pwren, + IPQ_MUX_pcie2_clk_req, + IPQ_MUX_pcie3_rst, + IPQ_MUX_pcie3_prsnt, + IPQ_MUX_pcie3_pwrflt, + IPQ_MUX_pcie3_pwren_n, + IPQ_MUX_pcie3_pwren, + IPQ_MUX_pcie3_clk_req, + IPQ_MUX_ps_hold, + IPQ_MUX_NA, +}; + +static const char * const gpio_groups[] = { + "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7", + "gpio8", "gpio9", "gpio10", "gpio11", "gpio12", "gpio13", "gpio14", + "gpio15", "gpio16", "gpio17", "gpio18", "gpio19", "gpio20", "gpio21", + "gpio22", "gpio23", "gpio24", "gpio25", "gpio26", "gpio27", "gpio28", + "gpio29", "gpio30", "gpio31", "gpio32", "gpio33", "gpio34", "gpio35", + "gpio36", "gpio37", "gpio38", "gpio39", "gpio40", "gpio41", "gpio42", + "gpio43", "gpio44", "gpio45", "gpio46", "gpio47", "gpio48", "gpio49", + "gpio50", "gpio51", "gpio52", "gpio53", "gpio54", "gpio55", "gpio56", + "gpio57", "gpio58", "gpio59", "gpio60", "gpio61", "gpio62", "gpio63", + "gpio64", "gpio65", "gpio66", "gpio67", "gpio68" +}; + +static const char * const mdio_groups[] = { + "gpio0", "gpio1", "gpio2", "gpio10", "gpio11", "gpio66", +}; + +static const char * const mi2s_groups[] = { + "gpio27", "gpio28", "gpio29", "gpio30", "gpio31", "gpio32", + "gpio33", "gpio55", "gpio56", "gpio57", "gpio58", +}; + +static const char * const pdm_groups[] = { + "gpio3", "gpio16", "gpio17", "gpio22", "gpio30", "gpio31", + "gpio34", "gpio35", "gpio52", "gpio55", "gpio56", "gpio58", + "gpio59", +}; + +static const char * const ssbi_groups[] = { + "gpio10", "gpio11", +}; + +static const char * const spmi_groups[] = { + "gpio10", "gpio11", +}; + +static const char * const audio_pcm_groups[] = { + "gpio14", "gpio15", "gpio16", "gpio17", +}; + +static const char * const gsbi1_groups[] = { + "gpio51", "gpio52", "gpio53", "gpio54", +}; + +static const char * const gsbi2_groups[] = { + "gpio22", "gpio23", "gpio24", "gpio25", +}; + +static const char * const gsbi4_groups[] = { + "gpio10", "gpio11", "gpio12", "gpio13", +}; + +static const char * const gsbi5_groups[] = { + "gpio18", "gpio19", "gpio20", "gpio21", +}; + +static const char * const gsbi5_spi_cs1_groups[] = { + "gpio6", "gpio61", +}; + +static const char * const gsbi5_spi_cs2_groups[] = { + "gpio7", "gpio62", +}; + +static const char * const gsbi5_spi_cs3_groups[] = { + "gpio2", +}; + +static const char * const gsbi6_groups[] = { + "gpio27", "gpio28", "gpio29", "gpio30", "gpio55", "gpio56", + "gpio57", "gpio58", +}; + +static const char * const gsbi7_groups[] = { + "gpio6", "gpio7", "gpio8", "gpio9", +}; + +static const char * const nss_spi_groups[] = { + "gpio14", "gpio15", "gpio16", "gpio17", "gpio55", "gpio56", + "gpio57", "gpio58", +}; + +static const char * const sdc1_groups[] = { + "gpio38", "gpio39", "gpio40", "gpio41", "gpio42", "gpio43", + "gpio44", "gpio45", "gpio46", "gpio47", +}; + +static const char * const spdif_groups[] = { + "gpio10", "gpio48", +}; + +static const char * const nand_groups[] = { + "gpio34", "gpio35", "gpio36", "gpio37", "gpio38", "gpio39", + "gpio40", "gpio41", "gpio42", "gpio43", "gpio44", "gpio45", + "gpio46", "gpio47", +}; + +static const char * const tsif1_groups[] = { + "gpio55", "gpio56", "gpio57", "gpio58", +}; + +static const char * const tsif2_groups[] = { + "gpio59", "gpio60", "gpio61", "gpio62", +}; + +static const char * const usb_fs_n_groups[] = { + "gpio6", +}; + +static const char * const usb_fs_groups[] = { + "gpio6", "gpio7", "gpio8", +}; + +static const char * const usb2_hsic_groups[] = { + "gpio67", "gpio68", +}; + +static const char * const rgmii2_groups[] = { + "gpio2", "gpio27", "gpio28", "gpio29", "gpio30", "gpio31", "gpio32", + "gpio51", "gpio52", "gpio59", "gpio60", "gpio61", "gpio62", "gpio66", +}; + +static const char * const sata_groups[] = { + "gpio10", +}; + +static const char * const pcie1_rst_groups[] = { + "gpio3", +}; + +static const char * const pcie1_prsnt_groups[] = { + "gpio3", "gpio11", +}; + +static const char * const pcie1_pwren_n_groups[] = { + "gpio4", "gpio12", +}; + +static const char * const pcie1_pwren_groups[] = { + "gpio4", "gpio12", +}; + +static const char * const pcie1_pwrflt_groups[] = { + "gpio5", "gpio13", +}; + +static const char * const pcie1_clk_req_groups[] = { + "gpio5", +}; + +static const char * const pcie2_rst_groups[] = { + "gpio48", +}; + +static const char * const pcie2_prsnt_groups[] = { + "gpio11", "gpio48", +}; + +static const char * const pcie2_pwren_n_groups[] = { + "gpio12", "gpio49", +}; + +static const char * const pcie2_pwren_groups[] = { + "gpio12", "gpio49", +}; + +static const char * const pcie2_pwrflt_groups[] = { + "gpio13", "gpio50", +}; + +static const char * const pcie2_clk_req_groups[] = { + "gpio50", +}; + +static const char * const pcie3_rst_groups[] = { + "gpio63", +}; + +static const char * const pcie3_prsnt_groups[] = { + "gpio11", +}; + +static const char * const pcie3_pwren_n_groups[] = { + "gpio12", +}; + +static const char * const pcie3_pwren_groups[] = { + "gpio12", +}; + +static const char * const pcie3_pwrflt_groups[] = { + "gpio13", +}; + +static const char * const pcie3_clk_req_groups[] = { + "gpio65", +}; + +static const char * const ps_hold_groups[] = { + "gpio26", +}; + +static const struct pinfunction ipq8064_functions[] = { + IPQ_PIN_FUNCTION(gpio), + IPQ_PIN_FUNCTION(mdio), + IPQ_PIN_FUNCTION(ssbi), + IPQ_PIN_FUNCTION(spmi), + IPQ_PIN_FUNCTION(mi2s), + IPQ_PIN_FUNCTION(pdm), + IPQ_PIN_FUNCTION(audio_pcm), + IPQ_PIN_FUNCTION(gsbi1), + IPQ_PIN_FUNCTION(gsbi2), + IPQ_PIN_FUNCTION(gsbi4), + IPQ_PIN_FUNCTION(gsbi5), + IPQ_PIN_FUNCTION(gsbi5_spi_cs1), + IPQ_PIN_FUNCTION(gsbi5_spi_cs2), + IPQ_PIN_FUNCTION(gsbi5_spi_cs3), + IPQ_PIN_FUNCTION(gsbi6), + IPQ_PIN_FUNCTION(gsbi7), + IPQ_PIN_FUNCTION(nss_spi), + IPQ_PIN_FUNCTION(sdc1), + IPQ_PIN_FUNCTION(spdif), + IPQ_PIN_FUNCTION(nand), + IPQ_PIN_FUNCTION(tsif1), + IPQ_PIN_FUNCTION(tsif2), + IPQ_PIN_FUNCTION(usb_fs_n), + IPQ_PIN_FUNCTION(usb_fs), + IPQ_PIN_FUNCTION(usb2_hsic), + IPQ_PIN_FUNCTION(rgmii2), + IPQ_PIN_FUNCTION(sata), + IPQ_PIN_FUNCTION(pcie1_rst), + IPQ_PIN_FUNCTION(pcie1_prsnt), + IPQ_PIN_FUNCTION(pcie1_pwren_n), + IPQ_PIN_FUNCTION(pcie1_pwren), + IPQ_PIN_FUNCTION(pcie1_pwrflt), + IPQ_PIN_FUNCTION(pcie1_clk_req), + IPQ_PIN_FUNCTION(pcie2_rst), + IPQ_PIN_FUNCTION(pcie2_prsnt), + IPQ_PIN_FUNCTION(pcie2_pwren_n), + IPQ_PIN_FUNCTION(pcie2_pwren), + IPQ_PIN_FUNCTION(pcie2_pwrflt), + IPQ_PIN_FUNCTION(pcie2_clk_req), + IPQ_PIN_FUNCTION(pcie3_rst), + IPQ_PIN_FUNCTION(pcie3_prsnt), + IPQ_PIN_FUNCTION(pcie3_pwren_n), + IPQ_PIN_FUNCTION(pcie3_pwren), + IPQ_PIN_FUNCTION(pcie3_pwrflt), + IPQ_PIN_FUNCTION(pcie3_clk_req), + IPQ_PIN_FUNCTION(ps_hold), +}; + +static const struct msm_pingroup ipq8064_groups[] = { + PINGROUP(0, mdio, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(1, mdio, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(2, gsbi5_spi_cs3, rgmii2, mdio, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(3, pcie1_rst, pcie1_prsnt, pdm, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(4, pcie1_pwren_n, pcie1_pwren, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(5, pcie1_clk_req, pcie1_pwrflt, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(6, gsbi7, usb_fs, gsbi5_spi_cs1, usb_fs_n, NA, NA, NA, NA, NA, NA), + PINGROUP(7, gsbi7, usb_fs, gsbi5_spi_cs2, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(8, gsbi7, usb_fs, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(9, gsbi7, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(10, gsbi4, spdif, sata, ssbi, mdio, spmi, NA, NA, NA, NA), + PINGROUP(11, gsbi4, pcie2_prsnt, pcie1_prsnt, pcie3_prsnt, ssbi, mdio, spmi, NA, NA, NA), + PINGROUP(12, gsbi4, pcie2_pwren_n, pcie1_pwren_n, pcie3_pwren_n, pcie2_pwren, pcie1_pwren, pcie3_pwren, NA, NA, NA), + PINGROUP(13, gsbi4, pcie2_pwrflt, pcie1_pwrflt, pcie3_pwrflt, NA, NA, NA, NA, NA, NA), + PINGROUP(14, audio_pcm, nss_spi, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(15, audio_pcm, nss_spi, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(16, audio_pcm, nss_spi, pdm, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(17, audio_pcm, nss_spi, pdm, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(18, gsbi5, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(19, gsbi5, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(20, gsbi5, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(21, gsbi5, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(22, gsbi2, pdm, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(23, gsbi2, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(24, gsbi2, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(25, gsbi2, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(26, ps_hold, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(27, mi2s, rgmii2, gsbi6, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(28, mi2s, rgmii2, gsbi6, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(29, mi2s, rgmii2, gsbi6, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(30, mi2s, rgmii2, gsbi6, pdm, NA, NA, NA, NA, NA, NA), + PINGROUP(31, mi2s, rgmii2, pdm, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(32, mi2s, rgmii2, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(33, mi2s, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(34, nand, pdm, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(35, nand, pdm, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(36, nand, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(37, nand, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(38, nand, sdc1, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(39, nand, sdc1, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(40, nand, sdc1, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(41, nand, sdc1, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(42, nand, sdc1, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(43, nand, sdc1, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(44, nand, sdc1, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(45, nand, sdc1, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(46, nand, sdc1, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(47, nand, sdc1, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(48, pcie2_rst, spdif, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(49, pcie2_pwren_n, pcie2_pwren, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(50, pcie2_clk_req, pcie2_pwrflt, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(51, gsbi1, rgmii2, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(52, gsbi1, rgmii2, pdm, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(53, gsbi1, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(54, gsbi1, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(55, tsif1, mi2s, gsbi6, pdm, nss_spi, NA, NA, NA, NA, NA), + PINGROUP(56, tsif1, mi2s, gsbi6, pdm, nss_spi, NA, NA, NA, NA, NA), + PINGROUP(57, tsif1, mi2s, gsbi6, nss_spi, NA, NA, NA, NA, NA, NA), + PINGROUP(58, tsif1, mi2s, gsbi6, pdm, nss_spi, NA, NA, NA, NA, NA), + PINGROUP(59, tsif2, rgmii2, pdm, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(60, tsif2, rgmii2, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(61, tsif2, rgmii2, gsbi5_spi_cs1, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(62, tsif2, rgmii2, gsbi5_spi_cs2, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(63, pcie3_rst, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(64, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(65, pcie3_clk_req, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(66, rgmii2, mdio, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(67, usb2_hsic, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(68, usb2_hsic, NA, NA, NA, NA, NA, NA, NA, NA, NA), + SDC_PINGROUP(sdc3_clk, 0x204a, 14, 6), + SDC_PINGROUP(sdc3_cmd, 0x204a, 11, 3), + SDC_PINGROUP(sdc3_data, 0x204a, 9, 0), +}; + +#define NUM_GPIO_PINGROUPS 69 + +static const struct msm_pinctrl_soc_data ipq8064_pinctrl = { + .pins = ipq8064_pins, + .npins = ARRAY_SIZE(ipq8064_pins), + .functions = ipq8064_functions, + .nfunctions = ARRAY_SIZE(ipq8064_functions), + .groups = ipq8064_groups, + .ngroups = ARRAY_SIZE(ipq8064_groups), + .ngpios = NUM_GPIO_PINGROUPS, +}; + +static int ipq8064_pinctrl_probe(struct platform_device *pdev) +{ + return msm_pinctrl_probe(pdev, &ipq8064_pinctrl); +} + +static const struct of_device_id ipq8064_pinctrl_of_match[] = { + { .compatible = "qcom,ipq8064-pinctrl", }, + { }, +}; + +static struct platform_driver ipq8064_pinctrl_driver = { + .driver = { + .name = "ipq8064-pinctrl", + .of_match_table = ipq8064_pinctrl_of_match, + }, + .probe = ipq8064_pinctrl_probe, + .remove = msm_pinctrl_remove, +}; + +static int __init ipq8064_pinctrl_init(void) +{ + return platform_driver_register(&ipq8064_pinctrl_driver); +} +arch_initcall(ipq8064_pinctrl_init); + +static void __exit ipq8064_pinctrl_exit(void) +{ + platform_driver_unregister(&ipq8064_pinctrl_driver); +} +module_exit(ipq8064_pinctrl_exit); + +MODULE_AUTHOR("Andy Gross <agross@codeaurora.org>"); +MODULE_DESCRIPTION("Qualcomm IPQ8064 pinctrl driver"); +MODULE_LICENSE("GPL v2"); +MODULE_DEVICE_TABLE(of, ipq8064_pinctrl_of_match); diff --git a/drivers/pinctrl/qcom/pinctrl-ipq8074.c b/drivers/pinctrl/qcom/pinctrl-ipq8074.c new file mode 100644 index 0000000000..337f3a1c92 --- /dev/null +++ b/drivers/pinctrl/qcom/pinctrl-ipq8074.c @@ -0,0 +1,1061 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2017, The Linux Foundation. All rights reserved. + */ + +#include <linux/module.h> +#include <linux/of.h> +#include <linux/platform_device.h> + +#include "pinctrl-msm.h" + +#define REG_SIZE 0x1000 +#define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7, f8, f9) \ + { \ + .grp = PINCTRL_PINGROUP("gpio" #id, \ + gpio##id##_pins, \ + ARRAY_SIZE(gpio##id##_pins)), \ + .funcs = (int[]){ \ + msm_mux_gpio, /* gpio mode */ \ + msm_mux_##f1, \ + msm_mux_##f2, \ + msm_mux_##f3, \ + msm_mux_##f4, \ + msm_mux_##f5, \ + msm_mux_##f6, \ + msm_mux_##f7, \ + msm_mux_##f8, \ + msm_mux_##f9 \ + }, \ + .nfuncs = 10, \ + .ctl_reg = REG_SIZE * id, \ + .io_reg = 0x4 + REG_SIZE * id, \ + .intr_cfg_reg = 0x8 + REG_SIZE * id, \ + .intr_status_reg = 0xc + REG_SIZE * id, \ + .intr_target_reg = 0x8 + REG_SIZE * id, \ + .mux_bit = 2, \ + .pull_bit = 0, \ + .drv_bit = 6, \ + .oe_bit = 9, \ + .in_bit = 0, \ + .out_bit = 1, \ + .intr_enable_bit = 0, \ + .intr_status_bit = 0, \ + .intr_target_bit = 5, \ + .intr_target_kpss_val = 3, \ + .intr_raw_status_bit = 4, \ + .intr_polarity_bit = 1, \ + .intr_detection_bit = 2, \ + .intr_detection_width = 2, \ + } + +static const struct pinctrl_pin_desc ipq8074_pins[] = { + PINCTRL_PIN(0, "GPIO_0"), + PINCTRL_PIN(1, "GPIO_1"), + PINCTRL_PIN(2, "GPIO_2"), + PINCTRL_PIN(3, "GPIO_3"), + PINCTRL_PIN(4, "GPIO_4"), + PINCTRL_PIN(5, "GPIO_5"), + PINCTRL_PIN(6, "GPIO_6"), + PINCTRL_PIN(7, "GPIO_7"), + PINCTRL_PIN(8, "GPIO_8"), + PINCTRL_PIN(9, "GPIO_9"), + PINCTRL_PIN(10, "GPIO_10"), + PINCTRL_PIN(11, "GPIO_11"), + PINCTRL_PIN(12, "GPIO_12"), + PINCTRL_PIN(13, "GPIO_13"), + PINCTRL_PIN(14, "GPIO_14"), + PINCTRL_PIN(15, "GPIO_15"), + PINCTRL_PIN(16, "GPIO_16"), + PINCTRL_PIN(17, "GPIO_17"), + PINCTRL_PIN(18, "GPIO_18"), + PINCTRL_PIN(19, "GPIO_19"), + PINCTRL_PIN(20, "GPIO_20"), + PINCTRL_PIN(21, "GPIO_21"), + PINCTRL_PIN(22, "GPIO_22"), + PINCTRL_PIN(23, "GPIO_23"), + PINCTRL_PIN(24, "GPIO_24"), + PINCTRL_PIN(25, "GPIO_25"), + PINCTRL_PIN(26, "GPIO_26"), + PINCTRL_PIN(27, "GPIO_27"), + PINCTRL_PIN(28, "GPIO_28"), + PINCTRL_PIN(29, "GPIO_29"), + PINCTRL_PIN(30, "GPIO_30"), + PINCTRL_PIN(31, "GPIO_31"), + PINCTRL_PIN(32, "GPIO_32"), + PINCTRL_PIN(33, "GPIO_33"), + PINCTRL_PIN(34, "GPIO_34"), + PINCTRL_PIN(35, "GPIO_35"), + PINCTRL_PIN(36, "GPIO_36"), + PINCTRL_PIN(37, "GPIO_37"), + PINCTRL_PIN(38, "GPIO_38"), + PINCTRL_PIN(39, "GPIO_39"), + PINCTRL_PIN(40, "GPIO_40"), + PINCTRL_PIN(41, "GPIO_41"), + PINCTRL_PIN(42, "GPIO_42"), + PINCTRL_PIN(43, "GPIO_43"), + PINCTRL_PIN(44, "GPIO_44"), + PINCTRL_PIN(45, "GPIO_45"), + PINCTRL_PIN(46, "GPIO_46"), + PINCTRL_PIN(47, "GPIO_47"), + PINCTRL_PIN(48, "GPIO_48"), + PINCTRL_PIN(49, "GPIO_49"), + PINCTRL_PIN(50, "GPIO_50"), + PINCTRL_PIN(51, "GPIO_51"), + PINCTRL_PIN(52, "GPIO_52"), + PINCTRL_PIN(53, "GPIO_53"), + PINCTRL_PIN(54, "GPIO_54"), + PINCTRL_PIN(55, "GPIO_55"), + PINCTRL_PIN(56, "GPIO_56"), + PINCTRL_PIN(57, "GPIO_57"), + PINCTRL_PIN(58, "GPIO_58"), + PINCTRL_PIN(59, "GPIO_59"), + PINCTRL_PIN(60, "GPIO_60"), + PINCTRL_PIN(61, "GPIO_61"), + PINCTRL_PIN(62, "GPIO_62"), + PINCTRL_PIN(63, "GPIO_63"), + PINCTRL_PIN(64, "GPIO_64"), + PINCTRL_PIN(65, "GPIO_65"), + PINCTRL_PIN(66, "GPIO_66"), + PINCTRL_PIN(67, "GPIO_67"), + PINCTRL_PIN(68, "GPIO_68"), + PINCTRL_PIN(69, "GPIO_69"), +}; + +#define DECLARE_MSM_GPIO_PINS(pin) \ + static const unsigned int gpio##pin##_pins[] = { pin } +DECLARE_MSM_GPIO_PINS(0); +DECLARE_MSM_GPIO_PINS(1); +DECLARE_MSM_GPIO_PINS(2); +DECLARE_MSM_GPIO_PINS(3); +DECLARE_MSM_GPIO_PINS(4); +DECLARE_MSM_GPIO_PINS(5); +DECLARE_MSM_GPIO_PINS(6); +DECLARE_MSM_GPIO_PINS(7); +DECLARE_MSM_GPIO_PINS(8); +DECLARE_MSM_GPIO_PINS(9); +DECLARE_MSM_GPIO_PINS(10); +DECLARE_MSM_GPIO_PINS(11); +DECLARE_MSM_GPIO_PINS(12); +DECLARE_MSM_GPIO_PINS(13); +DECLARE_MSM_GPIO_PINS(14); +DECLARE_MSM_GPIO_PINS(15); +DECLARE_MSM_GPIO_PINS(16); +DECLARE_MSM_GPIO_PINS(17); +DECLARE_MSM_GPIO_PINS(18); +DECLARE_MSM_GPIO_PINS(19); +DECLARE_MSM_GPIO_PINS(20); +DECLARE_MSM_GPIO_PINS(21); +DECLARE_MSM_GPIO_PINS(22); +DECLARE_MSM_GPIO_PINS(23); +DECLARE_MSM_GPIO_PINS(24); +DECLARE_MSM_GPIO_PINS(25); +DECLARE_MSM_GPIO_PINS(26); +DECLARE_MSM_GPIO_PINS(27); +DECLARE_MSM_GPIO_PINS(28); +DECLARE_MSM_GPIO_PINS(29); +DECLARE_MSM_GPIO_PINS(30); +DECLARE_MSM_GPIO_PINS(31); +DECLARE_MSM_GPIO_PINS(32); +DECLARE_MSM_GPIO_PINS(33); +DECLARE_MSM_GPIO_PINS(34); +DECLARE_MSM_GPIO_PINS(35); +DECLARE_MSM_GPIO_PINS(36); +DECLARE_MSM_GPIO_PINS(37); +DECLARE_MSM_GPIO_PINS(38); +DECLARE_MSM_GPIO_PINS(39); +DECLARE_MSM_GPIO_PINS(40); +DECLARE_MSM_GPIO_PINS(41); +DECLARE_MSM_GPIO_PINS(42); +DECLARE_MSM_GPIO_PINS(43); +DECLARE_MSM_GPIO_PINS(44); +DECLARE_MSM_GPIO_PINS(45); +DECLARE_MSM_GPIO_PINS(46); +DECLARE_MSM_GPIO_PINS(47); +DECLARE_MSM_GPIO_PINS(48); +DECLARE_MSM_GPIO_PINS(49); +DECLARE_MSM_GPIO_PINS(50); +DECLARE_MSM_GPIO_PINS(51); +DECLARE_MSM_GPIO_PINS(52); +DECLARE_MSM_GPIO_PINS(53); +DECLARE_MSM_GPIO_PINS(54); +DECLARE_MSM_GPIO_PINS(55); +DECLARE_MSM_GPIO_PINS(56); +DECLARE_MSM_GPIO_PINS(57); +DECLARE_MSM_GPIO_PINS(58); +DECLARE_MSM_GPIO_PINS(59); +DECLARE_MSM_GPIO_PINS(60); +DECLARE_MSM_GPIO_PINS(61); +DECLARE_MSM_GPIO_PINS(62); +DECLARE_MSM_GPIO_PINS(63); +DECLARE_MSM_GPIO_PINS(64); +DECLARE_MSM_GPIO_PINS(65); +DECLARE_MSM_GPIO_PINS(66); +DECLARE_MSM_GPIO_PINS(67); +DECLARE_MSM_GPIO_PINS(68); +DECLARE_MSM_GPIO_PINS(69); + +enum ipq8074_functions { + msm_mux_atest_char, + msm_mux_atest_char0, + msm_mux_atest_char1, + msm_mux_atest_char2, + msm_mux_atest_char3, + msm_mux_audio_rxbclk, + msm_mux_audio_rxd, + msm_mux_audio_rxfsync, + msm_mux_audio_rxmclk, + msm_mux_audio_txbclk, + msm_mux_audio_txd, + msm_mux_audio_txfsync, + msm_mux_audio_txmclk, + msm_mux_blsp0_i2c, + msm_mux_blsp0_spi, + msm_mux_blsp0_uart, + msm_mux_blsp1_i2c, + msm_mux_blsp1_spi, + msm_mux_blsp1_uart, + msm_mux_blsp2_i2c, + msm_mux_blsp2_spi, + msm_mux_blsp2_uart, + msm_mux_blsp3_i2c, + msm_mux_blsp3_spi, + msm_mux_blsp3_spi0, + msm_mux_blsp3_spi1, + msm_mux_blsp3_spi2, + msm_mux_blsp3_spi3, + msm_mux_blsp3_uart, + msm_mux_blsp4_i2c0, + msm_mux_blsp4_i2c1, + msm_mux_blsp4_spi0, + msm_mux_blsp4_spi1, + msm_mux_blsp4_uart0, + msm_mux_blsp4_uart1, + msm_mux_blsp5_i2c, + msm_mux_blsp5_spi, + msm_mux_blsp5_uart, + msm_mux_burn0, + msm_mux_burn1, + msm_mux_cri_trng, + msm_mux_cri_trng0, + msm_mux_cri_trng1, + msm_mux_cxc0, + msm_mux_cxc1, + msm_mux_dbg_out, + msm_mux_gcc_plltest, + msm_mux_gcc_tlmm, + msm_mux_gpio, + msm_mux_ldo_en, + msm_mux_ldo_update, + msm_mux_led0, + msm_mux_led1, + msm_mux_led2, + msm_mux_mac0_sa0, + msm_mux_mac0_sa1, + msm_mux_mac1_sa0, + msm_mux_mac1_sa1, + msm_mux_mac1_sa2, + msm_mux_mac1_sa3, + msm_mux_mac2_sa0, + msm_mux_mac2_sa1, + msm_mux_mdc, + msm_mux_mdio, + msm_mux_pcie0_clk, + msm_mux_pcie0_rst, + msm_mux_pcie0_wake, + msm_mux_pcie1_clk, + msm_mux_pcie1_rst, + msm_mux_pcie1_wake, + msm_mux_pcm_drx, + msm_mux_pcm_dtx, + msm_mux_pcm_fsync, + msm_mux_pcm_pclk, + msm_mux_pcm_zsi0, + msm_mux_pcm_zsi1, + msm_mux_prng_rosc, + msm_mux_pta1_0, + msm_mux_pta1_1, + msm_mux_pta1_2, + msm_mux_pta2_0, + msm_mux_pta2_1, + msm_mux_pta2_2, + msm_mux_pwm0, + msm_mux_pwm1, + msm_mux_pwm2, + msm_mux_pwm3, + msm_mux_qdss_cti_trig_in_a0, + msm_mux_qdss_cti_trig_in_a1, + msm_mux_qdss_cti_trig_in_b0, + msm_mux_qdss_cti_trig_in_b1, + msm_mux_qdss_cti_trig_out_a0, + msm_mux_qdss_cti_trig_out_a1, + msm_mux_qdss_cti_trig_out_b0, + msm_mux_qdss_cti_trig_out_b1, + msm_mux_qdss_traceclk_a, + msm_mux_qdss_traceclk_b, + msm_mux_qdss_tracectl_a, + msm_mux_qdss_tracectl_b, + msm_mux_qdss_tracedata_a, + msm_mux_qdss_tracedata_b, + msm_mux_qpic, + msm_mux_rx0, + msm_mux_rx1, + msm_mux_rx2, + msm_mux_sd_card, + msm_mux_sd_write, + msm_mux_tsens_max, + msm_mux_wci2a, + msm_mux_wci2b, + msm_mux_wci2c, + msm_mux_wci2d, + msm_mux_NA, +}; + +static const char * const qpic_groups[] = { + "gpio0", /* LCD_TE */ + "gpio1", /* BUSY_N */ + "gpio2", /* LCD_RS_N */ + "gpio3", /* WE_N */ + "gpio4", /* OE_N */ + "gpio5", /* DATA[0] */ + "gpio6", /* DATA[1] */ + "gpio7", /* DATA[2] */ + "gpio8", /* DATA[3] */ + "gpio9", /* CS_CSR_LCD */ + "gpio10", /* CLE */ + "gpio11", /* NAND_CS_N */ + "gpio12", /* DATA[4] */ + "gpio13", /* DATA[5] */ + "gpio14", /* DATA[6] */ + "gpio15", /* DATA[7] */ + "gpio16", /* DATA[8] */ + "gpio17", /* ALE */ +}; + +static const char * const blsp5_i2c_groups[] = { + "gpio0", "gpio2", +}; + +static const char * const blsp5_spi_groups[] = { + "gpio0", "gpio2", "gpio9", "gpio16", +}; + +static const char * const wci2a_groups[] = { + "gpio0", "gpio2", +}; + +static const char * const blsp3_spi3_groups[] = { + "gpio0", "gpio2", "gpio9", +}; + +static const char * const burn0_groups[] = { + "gpio0", +}; + +static const char * const pcm_zsi0_groups[] = { + "gpio1", +}; + +static const char * const blsp5_uart_groups[] = { + "gpio0", "gpio2", "gpio9", "gpio16", +}; + +static const char * const mac1_sa2_groups[] = { + "gpio1", "gpio11", +}; + +static const char * const blsp3_spi0_groups[] = { + "gpio1", "gpio3", "gpio4", +}; + +static const char * const burn1_groups[] = { + "gpio1", +}; + +static const char * const mac0_sa1_groups[] = { + "gpio3", "gpio4", +}; + +static const char * const qdss_cti_trig_out_b0_groups[] = { + "gpio3", +}; + +static const char * const qdss_cti_trig_in_b0_groups[] = { + "gpio4", +}; + +static const char * const blsp4_uart0_groups[] = { + "gpio5", "gpio6", "gpio7", "gpio8", +}; + +static const char * const blsp4_i2c0_groups[] = { + "gpio5", "gpio6", +}; + +static const char * const blsp4_spi0_groups[] = { + "gpio5", "gpio6", "gpio7", "gpio8", +}; + +static const char * const mac2_sa1_groups[] = { + "gpio5", "gpio6", +}; + +static const char * const qdss_cti_trig_out_b1_groups[] = { + "gpio5", +}; + +static const char * const qdss_cti_trig_in_b1_groups[] = { + "gpio6", +}; + +static const char * const cxc0_groups[] = { + "gpio9", "gpio16", +}; + +static const char * const mac1_sa3_groups[] = { + "gpio9", "gpio16", +}; + +static const char * const qdss_cti_trig_in_a1_groups[] = { + "gpio9", +}; + +static const char * const qdss_cti_trig_out_a1_groups[] = { + "gpio10", +}; + +static const char * const wci2c_groups[] = { + "gpio11", "gpio17", +}; + +static const char * const qdss_cti_trig_in_a0_groups[] = { + "gpio11", +}; + +static const char * const qdss_cti_trig_out_a0_groups[] = { + "gpio12", +}; + +static const char * const qdss_traceclk_b_groups[] = { + "gpio14", +}; + +static const char * const qdss_tracectl_b_groups[] = { + "gpio15", +}; + +static const char * const pcm_zsi1_groups[] = { + "gpio16", +}; + +static const char * const qdss_tracedata_b_groups[] = { + "gpio16", "gpio17", "gpio18", "gpio19", "gpio20", "gpio21", "gpio22", + "gpio23", "gpio24", "gpio25", "gpio26", "gpio27", "gpio28", "gpio29", + "gpio30", "gpio31", +}; + +static const char * const led0_groups[] = { + "gpio18", +}; + +static const char * const pwm0_groups[] = { + "gpio18", "gpio21", "gpio25", "gpio29", "gpio63", +}; + +static const char * const led1_groups[] = { + "gpio19", +}; + +static const char * const pwm1_groups[] = { + "gpio19", "gpio22", "gpio26", "gpio30", "gpio64", +}; + +static const char * const led2_groups[] = { + "gpio20", +}; + +static const char * const pwm2_groups[] = { + "gpio20", "gpio23", "gpio27", "gpio31", "gpio66", +}; + +static const char * const blsp4_uart1_groups[] = { + "gpio21", "gpio22", "gpio23", "gpio24", +}; + +static const char * const blsp4_i2c1_groups[] = { + "gpio21", "gpio22", +}; + +static const char * const blsp4_spi1_groups[] = { + "gpio21", "gpio22", "gpio23", "gpio24", +}; + +static const char * const wci2d_groups[] = { + "gpio21", "gpio22", +}; + +static const char * const mac1_sa1_groups[] = { + "gpio21", "gpio22", +}; + +static const char * const blsp3_spi2_groups[] = { + "gpio21", "gpio22", "gpio23", +}; + +static const char * const pwm3_groups[] = { + "gpio24", "gpio28", "gpio32", "gpio67", +}; + +static const char * const audio_txmclk_groups[] = { + "gpio25", +}; + +static const char * const audio_txbclk_groups[] = { + "gpio26", +}; + +static const char * const audio_txfsync_groups[] = { + "gpio27", +}; + +static const char * const audio_txd_groups[] = { + "gpio28", +}; + +static const char * const audio_rxmclk_groups[] = { + "gpio29", +}; + +static const char * const atest_char0_groups[] = { + "gpio29", +}; + +static const char * const audio_rxbclk_groups[] = { + "gpio30", +}; + +static const char * const atest_char1_groups[] = { + "gpio30", +}; + +static const char * const audio_rxfsync_groups[] = { + "gpio31", +}; + +static const char * const atest_char2_groups[] = { + "gpio31", +}; + +static const char * const audio_rxd_groups[] = { + "gpio32", +}; + +static const char * const atest_char3_groups[] = { + "gpio32", +}; + +static const char * const pcm_drx_groups[] = { + "gpio33", +}; + +static const char * const mac1_sa0_groups[] = { + "gpio33", "gpio34", +}; + +static const char * const mac0_sa0_groups[] = { + "gpio33", "gpio34", +}; + +static const char * const pcm_dtx_groups[] = { + "gpio34", +}; + +static const char * const pcm_fsync_groups[] = { + "gpio35", +}; + +static const char * const mac2_sa0_groups[] = { + "gpio35", "gpio36", +}; + +static const char * const qdss_traceclk_a_groups[] = { + "gpio35", +}; + +static const char * const pcm_pclk_groups[] = { + "gpio36", +}; + +static const char * const qdss_tracectl_a_groups[] = { + "gpio36", +}; + +static const char * const atest_char_groups[] = { + "gpio37", +}; + +static const char * const qdss_tracedata_a_groups[] = { + "gpio37", "gpio38", "gpio39", "gpio40", "gpio41", "gpio42", "gpio43", + "gpio44", "gpio45", "gpio46", "gpio47", "gpio48", "gpio49", "gpio50", + "gpio51", "gpio52", +}; + +static const char * const blsp0_uart_groups[] = { + "gpio38", "gpio39", "gpio40", "gpio41", +}; + +static const char * const blsp0_i2c_groups[] = { + "gpio38", "gpio39", +}; + +static const char * const blsp0_spi_groups[] = { + "gpio38", "gpio39", "gpio40", "gpio41", +}; + +static const char * const blsp1_uart_groups[] = { + "gpio42", "gpio43", "gpio44", "gpio45", +}; + +static const char * const blsp1_i2c_groups[] = { + "gpio42", "gpio43", +}; + +static const char * const blsp1_spi_groups[] = { + "gpio42", "gpio43", "gpio44", "gpio45", +}; + +static const char * const blsp2_uart_groups[] = { + "gpio46", "gpio47", "gpio48", "gpio49", +}; + +static const char * const blsp2_i2c_groups[] = { + "gpio46", "gpio47", +}; + +static const char * const blsp2_spi_groups[] = { + "gpio46", "gpio47", "gpio48", "gpio49", +}; + +static const char * const blsp3_uart_groups[] = { + "gpio50", "gpio51", "gpio52", "gpio53", +}; + +static const char * const blsp3_i2c_groups[] = { + "gpio50", "gpio51", +}; + +static const char * const blsp3_spi_groups[] = { + "gpio50", "gpio51", "gpio52", "gpio53", +}; + +static const char * const pta2_0_groups[] = { + "gpio54", +}; + +static const char * const wci2b_groups[] = { + "gpio54", "gpio56", +}; + +static const char * const cxc1_groups[] = { + "gpio54", "gpio56", +}; + +static const char * const blsp3_spi1_groups[] = { + "gpio54", "gpio55", "gpio56", +}; + +static const char * const pta2_1_groups[] = { + "gpio55", +}; + +static const char * const pta2_2_groups[] = { + "gpio56", +}; + +static const char * const pcie0_clk_groups[] = { + "gpio57", +}; + +static const char * const dbg_out_groups[] = { + "gpio57", +}; + +static const char * const cri_trng0_groups[] = { + "gpio57", +}; + +static const char * const pcie0_rst_groups[] = { + "gpio58", +}; + +static const char * const cri_trng1_groups[] = { + "gpio58", +}; + +static const char * const pcie0_wake_groups[] = { + "gpio59", +}; + +static const char * const cri_trng_groups[] = { + "gpio59", +}; + +static const char * const pcie1_clk_groups[] = { + "gpio60", +}; + +static const char * const rx2_groups[] = { + "gpio60", +}; + +static const char * const ldo_update_groups[] = { + "gpio60", +}; + +static const char * const pcie1_rst_groups[] = { + "gpio61", +}; + +static const char * const ldo_en_groups[] = { + "gpio61", +}; + +static const char * const pcie1_wake_groups[] = { + "gpio62", +}; + +static const char * const gcc_plltest_groups[] = { + "gpio62", "gpio63", +}; + +static const char * const sd_card_groups[] = { + "gpio63", +}; + +static const char * const pta1_1_groups[] = { + "gpio64", +}; + +static const char * const rx1_groups[] = { + "gpio64", +}; + +static const char * const pta1_2_groups[] = { + "gpio65", +}; + +static const char * const gcc_tlmm_groups[] = { + "gpio65", +}; + +static const char * const pta1_0_groups[] = { + "gpio66", +}; + +static const char * const prng_rosc_groups[] = { + "gpio66", +}; + +static const char * const sd_write_groups[] = { + "gpio67", +}; + +static const char * const rx0_groups[] = { + "gpio67", +}; + +static const char * const tsens_max_groups[] = { + "gpio67", +}; + +static const char * const mdc_groups[] = { + "gpio68", +}; + +static const char * const mdio_groups[] = { + "gpio69", +}; + +static const char * const gpio_groups[] = { + "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7", + "gpio8", "gpio9", "gpio10", "gpio11", "gpio12", "gpio13", "gpio14", + "gpio15", "gpio16", "gpio17", "gpio18", "gpio19", "gpio20", "gpio21", + "gpio22", "gpio23", "gpio24", "gpio25", "gpio26", "gpio27", "gpio28", + "gpio29", "gpio30", "gpio31", "gpio32", "gpio33", "gpio34", "gpio35", + "gpio36", "gpio37", "gpio38", "gpio39", "gpio40", "gpio41", "gpio42", + "gpio43", "gpio44", "gpio45", "gpio46", "gpio47", "gpio48", "gpio49", + "gpio50", "gpio51", "gpio52", "gpio53", "gpio54", "gpio55", "gpio56", + "gpio57", "gpio58", "gpio59", "gpio60", "gpio61", "gpio62", "gpio63", + "gpio64", "gpio65", "gpio66", "gpio67", "gpio68", "gpio69", +}; + +static const struct pinfunction ipq8074_functions[] = { + MSM_PIN_FUNCTION(atest_char), + MSM_PIN_FUNCTION(atest_char0), + MSM_PIN_FUNCTION(atest_char1), + MSM_PIN_FUNCTION(atest_char2), + MSM_PIN_FUNCTION(atest_char3), + MSM_PIN_FUNCTION(audio_rxbclk), + MSM_PIN_FUNCTION(audio_rxd), + MSM_PIN_FUNCTION(audio_rxfsync), + MSM_PIN_FUNCTION(audio_rxmclk), + MSM_PIN_FUNCTION(audio_txbclk), + MSM_PIN_FUNCTION(audio_txd), + MSM_PIN_FUNCTION(audio_txfsync), + MSM_PIN_FUNCTION(audio_txmclk), + MSM_PIN_FUNCTION(blsp0_i2c), + MSM_PIN_FUNCTION(blsp0_spi), + MSM_PIN_FUNCTION(blsp0_uart), + MSM_PIN_FUNCTION(blsp1_i2c), + MSM_PIN_FUNCTION(blsp1_spi), + MSM_PIN_FUNCTION(blsp1_uart), + MSM_PIN_FUNCTION(blsp2_i2c), + MSM_PIN_FUNCTION(blsp2_spi), + MSM_PIN_FUNCTION(blsp2_uart), + MSM_PIN_FUNCTION(blsp3_i2c), + MSM_PIN_FUNCTION(blsp3_spi), + MSM_PIN_FUNCTION(blsp3_spi0), + MSM_PIN_FUNCTION(blsp3_spi1), + MSM_PIN_FUNCTION(blsp3_spi2), + MSM_PIN_FUNCTION(blsp3_spi3), + MSM_PIN_FUNCTION(blsp3_uart), + MSM_PIN_FUNCTION(blsp4_i2c0), + MSM_PIN_FUNCTION(blsp4_i2c1), + MSM_PIN_FUNCTION(blsp4_spi0), + MSM_PIN_FUNCTION(blsp4_spi1), + MSM_PIN_FUNCTION(blsp4_uart0), + MSM_PIN_FUNCTION(blsp4_uart1), + MSM_PIN_FUNCTION(blsp5_i2c), + MSM_PIN_FUNCTION(blsp5_spi), + MSM_PIN_FUNCTION(blsp5_uart), + MSM_PIN_FUNCTION(burn0), + MSM_PIN_FUNCTION(burn1), + MSM_PIN_FUNCTION(cri_trng), + MSM_PIN_FUNCTION(cri_trng0), + MSM_PIN_FUNCTION(cri_trng1), + MSM_PIN_FUNCTION(cxc0), + MSM_PIN_FUNCTION(cxc1), + MSM_PIN_FUNCTION(dbg_out), + MSM_PIN_FUNCTION(gcc_plltest), + MSM_PIN_FUNCTION(gcc_tlmm), + MSM_PIN_FUNCTION(gpio), + MSM_PIN_FUNCTION(ldo_en), + MSM_PIN_FUNCTION(ldo_update), + MSM_PIN_FUNCTION(led0), + MSM_PIN_FUNCTION(led1), + MSM_PIN_FUNCTION(led2), + MSM_PIN_FUNCTION(mac0_sa0), + MSM_PIN_FUNCTION(mac0_sa1), + MSM_PIN_FUNCTION(mac1_sa0), + MSM_PIN_FUNCTION(mac1_sa1), + MSM_PIN_FUNCTION(mac1_sa2), + MSM_PIN_FUNCTION(mac1_sa3), + MSM_PIN_FUNCTION(mac2_sa0), + MSM_PIN_FUNCTION(mac2_sa1), + MSM_PIN_FUNCTION(mdc), + MSM_PIN_FUNCTION(mdio), + MSM_PIN_FUNCTION(pcie0_clk), + MSM_PIN_FUNCTION(pcie0_rst), + MSM_PIN_FUNCTION(pcie0_wake), + MSM_PIN_FUNCTION(pcie1_clk), + MSM_PIN_FUNCTION(pcie1_rst), + MSM_PIN_FUNCTION(pcie1_wake), + MSM_PIN_FUNCTION(pcm_drx), + MSM_PIN_FUNCTION(pcm_dtx), + MSM_PIN_FUNCTION(pcm_fsync), + MSM_PIN_FUNCTION(pcm_pclk), + MSM_PIN_FUNCTION(pcm_zsi0), + MSM_PIN_FUNCTION(pcm_zsi1), + MSM_PIN_FUNCTION(prng_rosc), + MSM_PIN_FUNCTION(pta1_0), + MSM_PIN_FUNCTION(pta1_1), + MSM_PIN_FUNCTION(pta1_2), + MSM_PIN_FUNCTION(pta2_0), + MSM_PIN_FUNCTION(pta2_1), + MSM_PIN_FUNCTION(pta2_2), + MSM_PIN_FUNCTION(pwm0), + MSM_PIN_FUNCTION(pwm1), + MSM_PIN_FUNCTION(pwm2), + MSM_PIN_FUNCTION(pwm3), + MSM_PIN_FUNCTION(qdss_cti_trig_in_a0), + MSM_PIN_FUNCTION(qdss_cti_trig_in_a1), + MSM_PIN_FUNCTION(qdss_cti_trig_in_b0), + MSM_PIN_FUNCTION(qdss_cti_trig_in_b1), + MSM_PIN_FUNCTION(qdss_cti_trig_out_a0), + MSM_PIN_FUNCTION(qdss_cti_trig_out_a1), + MSM_PIN_FUNCTION(qdss_cti_trig_out_b0), + MSM_PIN_FUNCTION(qdss_cti_trig_out_b1), + MSM_PIN_FUNCTION(qdss_traceclk_a), + MSM_PIN_FUNCTION(qdss_traceclk_b), + MSM_PIN_FUNCTION(qdss_tracectl_a), + MSM_PIN_FUNCTION(qdss_tracectl_b), + MSM_PIN_FUNCTION(qdss_tracedata_a), + MSM_PIN_FUNCTION(qdss_tracedata_b), + MSM_PIN_FUNCTION(qpic), + MSM_PIN_FUNCTION(rx0), + MSM_PIN_FUNCTION(rx1), + MSM_PIN_FUNCTION(rx2), + MSM_PIN_FUNCTION(sd_card), + MSM_PIN_FUNCTION(sd_write), + MSM_PIN_FUNCTION(tsens_max), + MSM_PIN_FUNCTION(wci2a), + MSM_PIN_FUNCTION(wci2b), + MSM_PIN_FUNCTION(wci2c), + MSM_PIN_FUNCTION(wci2d), +}; + +static const struct msm_pingroup ipq8074_groups[] = { + PINGROUP(0, qpic, blsp5_uart, blsp5_i2c, blsp5_spi, wci2a, + blsp3_spi3, NA, burn0, NA), + PINGROUP(1, qpic, pcm_zsi0, mac1_sa2, blsp3_spi0, NA, burn1, NA, NA, + NA), + PINGROUP(2, qpic, blsp5_uart, blsp5_i2c, blsp5_spi, wci2a, + blsp3_spi3, NA, NA, NA), + PINGROUP(3, qpic, mac0_sa1, blsp3_spi0, qdss_cti_trig_out_b0, NA, NA, + NA, NA, NA), + PINGROUP(4, qpic, mac0_sa1, blsp3_spi0, qdss_cti_trig_in_b0, NA, NA, + NA, NA, NA), + PINGROUP(5, qpic, blsp4_uart0, blsp4_i2c0, blsp4_spi0, mac2_sa1, + qdss_cti_trig_out_b1, NA, NA, NA), + PINGROUP(6, qpic, blsp4_uart0, blsp4_i2c0, blsp4_spi0, mac2_sa1, + qdss_cti_trig_in_b1, NA, NA, NA), + PINGROUP(7, qpic, blsp4_uart0, blsp4_spi0, NA, NA, NA, NA, NA, NA), + PINGROUP(8, qpic, blsp4_uart0, blsp4_spi0, NA, NA, NA, NA, NA, NA), + PINGROUP(9, qpic, blsp5_uart, blsp5_spi, cxc0, mac1_sa3, blsp3_spi3, + qdss_cti_trig_in_a1, NA, NA), + PINGROUP(10, qpic, qdss_cti_trig_out_a1, NA, NA, NA, NA, NA, NA, + NA), + PINGROUP(11, qpic, wci2c, mac1_sa2, qdss_cti_trig_in_a0, NA, NA, NA, + NA, NA), + PINGROUP(12, qpic, qdss_cti_trig_out_a0, NA, NA, NA, NA, NA, NA, + NA), + PINGROUP(13, qpic, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(14, qpic, qdss_traceclk_b, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(15, qpic, qdss_tracectl_b, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(16, qpic, blsp5_uart, pcm_zsi1, blsp5_spi, cxc0, mac1_sa3, + qdss_tracedata_b, NA, NA), + PINGROUP(17, qpic, wci2c, qdss_tracedata_b, NA, NA, NA, NA, NA, NA), + PINGROUP(18, led0, pwm0, qdss_tracedata_b, NA, NA, NA, NA, NA, NA), + PINGROUP(19, led1, pwm1, NA, qdss_tracedata_b, NA, NA, NA, NA, NA), + PINGROUP(20, led2, pwm2, NA, qdss_tracedata_b, NA, NA, NA, NA, NA), + PINGROUP(21, pwm0, blsp4_uart1, blsp4_i2c1, blsp4_spi1, wci2d, mac1_sa1, + blsp3_spi2, NA, qdss_tracedata_b), + PINGROUP(22, pwm1, blsp4_uart1, blsp4_i2c1, blsp4_spi1, wci2d, mac1_sa1, + blsp3_spi2, NA, qdss_tracedata_b), + PINGROUP(23, pwm2, blsp4_uart1, blsp4_spi1, blsp3_spi2, NA, + qdss_tracedata_b, NA, NA, NA), + PINGROUP(24, pwm3, blsp4_uart1, blsp4_spi1, NA, qdss_tracedata_b, NA, + NA, NA, NA), + PINGROUP(25, audio_txmclk, pwm0, NA, qdss_tracedata_b, NA, NA, NA, NA, + NA), + PINGROUP(26, audio_txbclk, pwm1, NA, qdss_tracedata_b, NA, NA, NA, NA, + NA), + PINGROUP(27, audio_txfsync, pwm2, NA, qdss_tracedata_b, NA, NA, NA, + NA, NA), + PINGROUP(28, audio_txd, pwm3, NA, qdss_tracedata_b, NA, NA, NA, NA, + NA), + PINGROUP(29, audio_rxmclk, pwm0, atest_char0, NA, qdss_tracedata_b, + NA, NA, NA, NA), + PINGROUP(30, audio_rxbclk, pwm1, atest_char1, NA, qdss_tracedata_b, + NA, NA, NA, NA), + PINGROUP(31, audio_rxfsync, pwm2, atest_char2, NA, qdss_tracedata_b, + NA, NA, NA, NA), + PINGROUP(32, audio_rxd, pwm3, atest_char3, NA, NA, NA, NA, NA, NA), + PINGROUP(33, pcm_drx, mac1_sa0, mac0_sa0, NA, NA, NA, NA, NA, NA), + PINGROUP(34, pcm_dtx, mac1_sa0, mac0_sa0, NA, NA, NA, NA, NA, NA), + PINGROUP(35, pcm_fsync, mac2_sa0, qdss_traceclk_a, NA, NA, NA, NA, NA, NA), + PINGROUP(36, pcm_pclk, mac2_sa0, NA, qdss_tracectl_a, NA, NA, NA, NA, NA), + PINGROUP(37, atest_char, NA, qdss_tracedata_a, NA, NA, NA, NA, NA, NA), + PINGROUP(38, blsp0_uart, blsp0_i2c, blsp0_spi, NA, qdss_tracedata_a, + NA, NA, NA, NA), + PINGROUP(39, blsp0_uart, blsp0_i2c, blsp0_spi, NA, qdss_tracedata_a, + NA, NA, NA, NA), + PINGROUP(40, blsp0_uart, blsp0_spi, NA, qdss_tracedata_a, NA, NA, NA, + NA, NA), + PINGROUP(41, blsp0_uart, blsp0_spi, NA, qdss_tracedata_a, NA, NA, NA, + NA, NA), + PINGROUP(42, blsp1_uart, blsp1_i2c, blsp1_spi, NA, qdss_tracedata_a, + NA, NA, NA, NA), + PINGROUP(43, blsp1_uart, blsp1_i2c, blsp1_spi, NA, qdss_tracedata_a, + NA, NA, NA, NA), + PINGROUP(44, blsp1_uart, blsp1_spi, NA, qdss_tracedata_a, NA, NA, NA, + NA, NA), + PINGROUP(45, blsp1_uart, blsp1_spi, qdss_tracedata_a, NA, NA, NA, NA, + NA, NA), + PINGROUP(46, blsp2_uart, blsp2_i2c, blsp2_spi, qdss_tracedata_a, NA, + NA, NA, NA, NA), + PINGROUP(47, blsp2_uart, blsp2_i2c, blsp2_spi, NA, qdss_tracedata_a, + NA, NA, NA, NA), + PINGROUP(48, blsp2_uart, blsp2_spi, NA, qdss_tracedata_a, NA, NA, NA, + NA, NA), + PINGROUP(49, blsp2_uart, blsp2_spi, NA, qdss_tracedata_a, NA, NA, NA, + NA, NA), + PINGROUP(50, blsp3_uart, blsp3_i2c, blsp3_spi, NA, qdss_tracedata_a, + NA, NA, NA, NA), + PINGROUP(51, blsp3_uart, blsp3_i2c, blsp3_spi, NA, qdss_tracedata_a, + NA, NA, NA, NA), + PINGROUP(52, blsp3_uart, blsp3_spi, NA, qdss_tracedata_a, NA, NA, NA, + NA, NA), + PINGROUP(53, blsp3_uart, blsp3_spi, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(54, pta2_0, wci2b, cxc1, blsp3_spi1, NA, NA, NA, NA, NA), + PINGROUP(55, pta2_1, blsp3_spi1, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(56, pta2_2, wci2b, cxc1, blsp3_spi1, NA, NA, NA, NA, NA), + PINGROUP(57, pcie0_clk, NA, dbg_out, cri_trng0, NA, NA, NA, NA, NA), + PINGROUP(58, pcie0_rst, NA, cri_trng1, NA, NA, NA, NA, NA, NA), + PINGROUP(59, pcie0_wake, NA, cri_trng, NA, NA, NA, NA, NA, NA), + PINGROUP(60, pcie1_clk, rx2, ldo_update, NA, NA, NA, NA, NA, NA), + PINGROUP(61, pcie1_rst, ldo_en, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(62, pcie1_wake, gcc_plltest, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(63, sd_card, pwm0, NA, gcc_plltest, NA, NA, NA, NA, NA), + PINGROUP(64, pta1_1, pwm1, NA, rx1, NA, NA, NA, NA, NA), + PINGROUP(65, pta1_2, NA, gcc_tlmm, NA, NA, NA, NA, NA, NA), + PINGROUP(66, pta1_0, pwm2, prng_rosc, NA, NA, NA, NA, NA, NA), + PINGROUP(67, sd_write, pwm3, rx0, tsens_max, NA, NA, NA, NA, NA), + PINGROUP(68, mdc, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(69, mdio, NA, NA, NA, NA, NA, NA, NA, NA), +}; + +static const struct msm_pinctrl_soc_data ipq8074_pinctrl = { + .pins = ipq8074_pins, + .npins = ARRAY_SIZE(ipq8074_pins), + .functions = ipq8074_functions, + .nfunctions = ARRAY_SIZE(ipq8074_functions), + .groups = ipq8074_groups, + .ngroups = ARRAY_SIZE(ipq8074_groups), + .ngpios = 70, +}; + +static int ipq8074_pinctrl_probe(struct platform_device *pdev) +{ + return msm_pinctrl_probe(pdev, &ipq8074_pinctrl); +} + +static const struct of_device_id ipq8074_pinctrl_of_match[] = { + { .compatible = "qcom,ipq8074-pinctrl", }, + { }, +}; + +static struct platform_driver ipq8074_pinctrl_driver = { + .driver = { + .name = "ipq8074-pinctrl", + .of_match_table = ipq8074_pinctrl_of_match, + }, + .probe = ipq8074_pinctrl_probe, + .remove = msm_pinctrl_remove, +}; + +static int __init ipq8074_pinctrl_init(void) +{ + return platform_driver_register(&ipq8074_pinctrl_driver); +} +arch_initcall(ipq8074_pinctrl_init); + +static void __exit ipq8074_pinctrl_exit(void) +{ + platform_driver_unregister(&ipq8074_pinctrl_driver); +} +module_exit(ipq8074_pinctrl_exit); + +MODULE_DESCRIPTION("Qualcomm ipq8074 pinctrl driver"); +MODULE_LICENSE("GPL v2"); +MODULE_DEVICE_TABLE(of, ipq8074_pinctrl_of_match); diff --git a/drivers/pinctrl/qcom/pinctrl-ipq9574.c b/drivers/pinctrl/qcom/pinctrl-ipq9574.c new file mode 100644 index 0000000000..e2491617b2 --- /dev/null +++ b/drivers/pinctrl/qcom/pinctrl-ipq9574.c @@ -0,0 +1,818 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* + * Copyright (c) 2023 The Linux Foundation. All rights reserved. + */ + +#include <linux/module.h> +#include <linux/of.h> +#include <linux/platform_device.h> + +#include "pinctrl-msm.h" + +#define REG_SIZE 0x1000 +#define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7, f8, f9) \ + { \ + .grp = PINCTRL_PINGROUP("gpio" #id, \ + gpio##id##_pins, \ + ARRAY_SIZE(gpio##id##_pins)), \ + .funcs = (int[]){ \ + msm_mux_gpio, /* gpio mode */ \ + msm_mux_##f1, \ + msm_mux_##f2, \ + msm_mux_##f3, \ + msm_mux_##f4, \ + msm_mux_##f5, \ + msm_mux_##f6, \ + msm_mux_##f7, \ + msm_mux_##f8, \ + msm_mux_##f9 \ + }, \ + .nfuncs = 10, \ + .ctl_reg = REG_SIZE * id, \ + .io_reg = 0x4 + REG_SIZE * id, \ + .intr_cfg_reg = 0x8 + REG_SIZE * id, \ + .intr_status_reg = 0xc + REG_SIZE * id, \ + .intr_target_reg = 0x8 + REG_SIZE * id, \ + .mux_bit = 2, \ + .pull_bit = 0, \ + .drv_bit = 6, \ + .oe_bit = 9, \ + .in_bit = 0, \ + .out_bit = 1, \ + .intr_enable_bit = 0, \ + .intr_status_bit = 0, \ + .intr_target_bit = 5, \ + .intr_target_kpss_val = 3, \ + .intr_raw_status_bit = 4, \ + .intr_polarity_bit = 1, \ + .intr_detection_bit = 2, \ + .intr_detection_width = 2, \ + } + +static const struct pinctrl_pin_desc ipq9574_pins[] = { + PINCTRL_PIN(0, "GPIO_0"), + PINCTRL_PIN(1, "GPIO_1"), + PINCTRL_PIN(2, "GPIO_2"), + PINCTRL_PIN(3, "GPIO_3"), + PINCTRL_PIN(4, "GPIO_4"), + PINCTRL_PIN(5, "GPIO_5"), + PINCTRL_PIN(6, "GPIO_6"), + PINCTRL_PIN(7, "GPIO_7"), + PINCTRL_PIN(8, "GPIO_8"), + PINCTRL_PIN(9, "GPIO_9"), + PINCTRL_PIN(10, "GPIO_10"), + PINCTRL_PIN(11, "GPIO_11"), + PINCTRL_PIN(12, "GPIO_12"), + PINCTRL_PIN(13, "GPIO_13"), + PINCTRL_PIN(14, "GPIO_14"), + PINCTRL_PIN(15, "GPIO_15"), + PINCTRL_PIN(16, "GPIO_16"), + PINCTRL_PIN(17, "GPIO_17"), + PINCTRL_PIN(18, "GPIO_18"), + PINCTRL_PIN(19, "GPIO_19"), + PINCTRL_PIN(20, "GPIO_20"), + PINCTRL_PIN(21, "GPIO_21"), + PINCTRL_PIN(22, "GPIO_22"), + PINCTRL_PIN(23, "GPIO_23"), + PINCTRL_PIN(24, "GPIO_24"), + PINCTRL_PIN(25, "GPIO_25"), + PINCTRL_PIN(26, "GPIO_26"), + PINCTRL_PIN(27, "GPIO_27"), + PINCTRL_PIN(28, "GPIO_28"), + PINCTRL_PIN(29, "GPIO_29"), + PINCTRL_PIN(30, "GPIO_30"), + PINCTRL_PIN(31, "GPIO_31"), + PINCTRL_PIN(32, "GPIO_32"), + PINCTRL_PIN(33, "GPIO_33"), + PINCTRL_PIN(34, "GPIO_34"), + PINCTRL_PIN(35, "GPIO_35"), + PINCTRL_PIN(36, "GPIO_36"), + PINCTRL_PIN(37, "GPIO_37"), + PINCTRL_PIN(38, "GPIO_38"), + PINCTRL_PIN(39, "GPIO_39"), + PINCTRL_PIN(40, "GPIO_40"), + PINCTRL_PIN(41, "GPIO_41"), + PINCTRL_PIN(42, "GPIO_42"), + PINCTRL_PIN(43, "GPIO_43"), + PINCTRL_PIN(44, "GPIO_44"), + PINCTRL_PIN(45, "GPIO_45"), + PINCTRL_PIN(46, "GPIO_46"), + PINCTRL_PIN(47, "GPIO_47"), + PINCTRL_PIN(48, "GPIO_48"), + PINCTRL_PIN(49, "GPIO_49"), + PINCTRL_PIN(50, "GPIO_50"), + PINCTRL_PIN(51, "GPIO_51"), + PINCTRL_PIN(52, "GPIO_52"), + PINCTRL_PIN(53, "GPIO_53"), + PINCTRL_PIN(54, "GPIO_54"), + PINCTRL_PIN(55, "GPIO_55"), + PINCTRL_PIN(56, "GPIO_56"), + PINCTRL_PIN(57, "GPIO_57"), + PINCTRL_PIN(58, "GPIO_58"), + PINCTRL_PIN(59, "GPIO_59"), + PINCTRL_PIN(60, "GPIO_60"), + PINCTRL_PIN(61, "GPIO_61"), + PINCTRL_PIN(62, "GPIO_62"), + PINCTRL_PIN(63, "GPIO_63"), + PINCTRL_PIN(64, "GPIO_64"), +}; + +#define DECLARE_MSM_GPIO_PINS(pin) \ + static const unsigned int gpio##pin##_pins[] = { pin } +DECLARE_MSM_GPIO_PINS(0); +DECLARE_MSM_GPIO_PINS(1); +DECLARE_MSM_GPIO_PINS(2); +DECLARE_MSM_GPIO_PINS(3); +DECLARE_MSM_GPIO_PINS(4); +DECLARE_MSM_GPIO_PINS(5); +DECLARE_MSM_GPIO_PINS(6); +DECLARE_MSM_GPIO_PINS(7); +DECLARE_MSM_GPIO_PINS(8); +DECLARE_MSM_GPIO_PINS(9); +DECLARE_MSM_GPIO_PINS(10); +DECLARE_MSM_GPIO_PINS(11); +DECLARE_MSM_GPIO_PINS(12); +DECLARE_MSM_GPIO_PINS(13); +DECLARE_MSM_GPIO_PINS(14); +DECLARE_MSM_GPIO_PINS(15); +DECLARE_MSM_GPIO_PINS(16); +DECLARE_MSM_GPIO_PINS(17); +DECLARE_MSM_GPIO_PINS(18); +DECLARE_MSM_GPIO_PINS(19); +DECLARE_MSM_GPIO_PINS(20); +DECLARE_MSM_GPIO_PINS(21); +DECLARE_MSM_GPIO_PINS(22); +DECLARE_MSM_GPIO_PINS(23); +DECLARE_MSM_GPIO_PINS(24); +DECLARE_MSM_GPIO_PINS(25); +DECLARE_MSM_GPIO_PINS(26); +DECLARE_MSM_GPIO_PINS(27); +DECLARE_MSM_GPIO_PINS(28); +DECLARE_MSM_GPIO_PINS(29); +DECLARE_MSM_GPIO_PINS(30); +DECLARE_MSM_GPIO_PINS(31); +DECLARE_MSM_GPIO_PINS(32); +DECLARE_MSM_GPIO_PINS(33); +DECLARE_MSM_GPIO_PINS(34); +DECLARE_MSM_GPIO_PINS(35); +DECLARE_MSM_GPIO_PINS(36); +DECLARE_MSM_GPIO_PINS(37); +DECLARE_MSM_GPIO_PINS(38); +DECLARE_MSM_GPIO_PINS(39); +DECLARE_MSM_GPIO_PINS(40); +DECLARE_MSM_GPIO_PINS(41); +DECLARE_MSM_GPIO_PINS(42); +DECLARE_MSM_GPIO_PINS(43); +DECLARE_MSM_GPIO_PINS(44); +DECLARE_MSM_GPIO_PINS(45); +DECLARE_MSM_GPIO_PINS(46); +DECLARE_MSM_GPIO_PINS(47); +DECLARE_MSM_GPIO_PINS(48); +DECLARE_MSM_GPIO_PINS(49); +DECLARE_MSM_GPIO_PINS(50); +DECLARE_MSM_GPIO_PINS(51); +DECLARE_MSM_GPIO_PINS(52); +DECLARE_MSM_GPIO_PINS(53); +DECLARE_MSM_GPIO_PINS(54); +DECLARE_MSM_GPIO_PINS(55); +DECLARE_MSM_GPIO_PINS(56); +DECLARE_MSM_GPIO_PINS(57); +DECLARE_MSM_GPIO_PINS(58); +DECLARE_MSM_GPIO_PINS(59); +DECLARE_MSM_GPIO_PINS(60); +DECLARE_MSM_GPIO_PINS(61); +DECLARE_MSM_GPIO_PINS(62); +DECLARE_MSM_GPIO_PINS(63); +DECLARE_MSM_GPIO_PINS(64); + +enum ipq9574_functions { + msm_mux_atest_char, + msm_mux_atest_char0, + msm_mux_atest_char1, + msm_mux_atest_char2, + msm_mux_atest_char3, + msm_mux_audio_pdm0, + msm_mux_audio_pdm1, + msm_mux_audio_pri, + msm_mux_audio_sec, + msm_mux_blsp0_spi, + msm_mux_blsp0_uart, + msm_mux_blsp1_i2c, + msm_mux_blsp1_spi, + msm_mux_blsp1_uart, + msm_mux_blsp2_i2c, + msm_mux_blsp2_spi, + msm_mux_blsp2_uart, + msm_mux_blsp3_i2c, + msm_mux_blsp3_spi, + msm_mux_blsp3_uart, + msm_mux_blsp4_i2c, + msm_mux_blsp4_spi, + msm_mux_blsp4_uart, + msm_mux_blsp5_i2c, + msm_mux_blsp5_uart, + msm_mux_cri_trng0, + msm_mux_cri_trng1, + msm_mux_cri_trng2, + msm_mux_cri_trng3, + msm_mux_cxc0, + msm_mux_cxc1, + msm_mux_dbg_out, + msm_mux_dwc_ddrphy, + msm_mux_gcc_plltest, + msm_mux_gcc_tlmm, + msm_mux_gpio, + msm_mux_mac, + msm_mux_mdc, + msm_mux_mdio, + msm_mux_pcie0_clk, + msm_mux_pcie0_wake, + msm_mux_pcie1_clk, + msm_mux_pcie1_wake, + msm_mux_pcie2_clk, + msm_mux_pcie2_wake, + msm_mux_pcie3_clk, + msm_mux_pcie3_wake, + msm_mux_prng_rosc0, + msm_mux_prng_rosc1, + msm_mux_prng_rosc2, + msm_mux_prng_rosc3, + msm_mux_pta, + msm_mux_pwm, + msm_mux_qdss_cti_trig_in_a0, + msm_mux_qdss_cti_trig_in_a1, + msm_mux_qdss_cti_trig_in_b0, + msm_mux_qdss_cti_trig_in_b1, + msm_mux_qdss_cti_trig_out_a0, + msm_mux_qdss_cti_trig_out_a1, + msm_mux_qdss_cti_trig_out_b0, + msm_mux_qdss_cti_trig_out_b1, + msm_mux_qdss_traceclk_a, + msm_mux_qdss_traceclk_b, + msm_mux_qdss_tracectl_a, + msm_mux_qdss_tracectl_b, + msm_mux_qdss_tracedata_a, + msm_mux_qdss_tracedata_b, + msm_mux_qspi_data, + msm_mux_qspi_clk, + msm_mux_qspi_cs, + msm_mux_rx0, + msm_mux_rx1, + msm_mux_sdc_data, + msm_mux_sdc_clk, + msm_mux_sdc_cmd, + msm_mux_sdc_rclk, + msm_mux_tsens_max, + msm_mux_wci20, + msm_mux_wci21, + msm_mux_wsa_swrm, + msm_mux__, +}; + +static const char * const gpio_groups[] = { + "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7", + "gpio8", "gpio9", "gpio10", "gpio11", "gpio12", "gpio13", "gpio14", + "gpio15", "gpio16", "gpio17", "gpio18", "gpio19", "gpio20", "gpio21", + "gpio22", "gpio23", "gpio24", "gpio25", "gpio26", "gpio27", "gpio28", + "gpio29", "gpio30", "gpio31", "gpio32", "gpio33", "gpio34", "gpio35", + "gpio36", "gpio37", "gpio38", "gpio39", "gpio40", "gpio41", "gpio42", + "gpio43", "gpio44", "gpio45", "gpio46", "gpio47", "gpio48", "gpio49", + "gpio50", "gpio51", "gpio52", "gpio53", "gpio54", "gpio55", "gpio56", + "gpio57", "gpio58", "gpio59", "gpio60", "gpio61", "gpio62", "gpio63", + "gpio64", +}; + +static const char * const sdc_data_groups[] = { + "gpio0", + "gpio1", + "gpio2", + "gpio3", + "gpio6", + "gpio7", + "gpio8", + "gpio9", +}; + +static const char * const qspi_data_groups[] = { + "gpio0", + "gpio1", + "gpio2", + "gpio3", +}; + +static const char * const qdss_traceclk_b_groups[] = { + "gpio0", +}; + +static const char * const qdss_tracectl_b_groups[] = { + "gpio1", +}; + +static const char * const qdss_tracedata_b_groups[] = { + "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7", "gpio8", "gpio9", + "gpio10", "gpio11", "gpio12", "gpio13", "gpio14", "gpio15", "gpio16", + "gpio17", +}; + +static const char * const sdc_cmd_groups[] = { + "gpio4", +}; + +static const char * const qspi_cs_groups[] = { + "gpio4", +}; + +static const char * const sdc_clk_groups[] = { + "gpio5", +}; + +static const char * const qspi_clk_groups[] = { + "gpio5", +}; + +static const char * const sdc_rclk_groups[] = { + "gpio10", +}; + +static const char * const blsp0_spi_groups[] = { + "gpio11", "gpio12", "gpio13", "gpio14", +}; + +static const char * const blsp0_uart_groups[] = { + "gpio11", "gpio12", "gpio13", "gpio14", +}; + +static const char * const blsp3_spi_groups[] = { + "gpio15", "gpio16", "gpio17", "gpio18", "gpio19", "gpio20", "gpio21", +}; + +static const char * const blsp3_i2c_groups[] = { + "gpio15", "gpio16", +}; + +static const char * const blsp3_uart_groups[] = { + "gpio15", "gpio16", "gpio17", "gpio18", +}; + +static const char * const dbg_out_groups[] = { + "gpio17", +}; + +static const char * const cri_trng0_groups[] = { + "gpio20", "gpio38", +}; + +static const char * const cri_trng1_groups[] = { + "gpio21", "gpio34", +}; + +static const char * const pcie0_clk_groups[] = { + "gpio22", +}; + +static const char * const pta_groups[] = { + "gpio22", "gpio23", "gpio24", "gpio54", "gpio55", "gpio56", "gpio61", + "gpio62", "gpio63", +}; + +static const char * const wci21_groups[] = { + "gpio23", "gpio24", +}; + +static const char * const cxc0_groups[] = { + "gpio23", "gpio24", +}; + +static const char * const pcie0_wake_groups[] = { + "gpio24", +}; + +static const char * const qdss_cti_trig_out_b0_groups[] = { + "gpio24", +}; + +static const char * const pcie1_clk_groups[] = { + "gpio25", +}; + +static const char * const qdss_cti_trig_in_b0_groups[] = { + "gpio25", +}; + +static const char * const atest_char0_groups[] = { + "gpio26", +}; + +static const char * const qdss_cti_trig_out_b1_groups[] = { + "gpio26", +}; + +static const char * const pcie1_wake_groups[] = { + "gpio27", +}; + +static const char * const atest_char1_groups[] = { + "gpio27", +}; + +static const char * const qdss_cti_trig_in_b1_groups[] = { + "gpio27", +}; + +static const char * const pcie2_clk_groups[] = { + "gpio28", +}; + +static const char * const atest_char2_groups[] = { + "gpio28", +}; + +static const char * const atest_char3_groups[] = { + "gpio29", +}; + +static const char * const pcie2_wake_groups[] = { + "gpio30", +}; + +static const char * const pwm_groups[] = { + "gpio30", "gpio31", "gpio32", "gpio33", "gpio44", "gpio45", "gpio46", + "gpio47", "gpio50", "gpio51", "gpio52", "gpio53", "gpio54", "gpio55", + "gpio56", "gpio57", "gpio58", "gpio59", "gpio60", +}; + +static const char * const atest_char_groups[] = { + "gpio30", +}; + +static const char * const pcie3_clk_groups[] = { + "gpio31", +}; + +static const char * const qdss_cti_trig_in_a1_groups[] = { + "gpio31", +}; + +static const char * const qdss_cti_trig_out_a1_groups[] = { + "gpio32", +}; + +static const char * const pcie3_wake_groups[] = { + "gpio33", +}; + +static const char * const qdss_cti_trig_in_a0_groups[] = { + "gpio33", +}; + +static const char * const blsp2_uart_groups[] = { + "gpio34", "gpio35", +}; + +static const char * const blsp2_i2c_groups[] = { + "gpio34", "gpio35", +}; + +static const char * const blsp2_spi_groups[] = { + "gpio34", "gpio35", "gpio36", "gpio37", +}; + +static const char * const blsp1_uart_groups[] = { + "gpio34", "gpio35", "gpio36", "gpio37", +}; + +static const char * const qdss_cti_trig_out_a0_groups[] = { + "gpio34", +}; + +static const char * const cri_trng2_groups[] = { + "gpio35", +}; + +static const char * const blsp1_i2c_groups[] = { + "gpio36", "gpio37", +}; + +static const char * const cri_trng3_groups[] = { + "gpio36", +}; + +static const char * const dwc_ddrphy_groups[] = { + "gpio37", +}; + +static const char * const mdc_groups[] = { + "gpio38", +}; + +static const char * const mdio_groups[] = { + "gpio39", +}; + +static const char * const audio_pri_groups[] = { + "gpio40", "gpio41", "gpio42", "gpio43", "gpio61", "gpio61", +}; + +static const char * const audio_pdm0_groups[] = { + "gpio40", "gpio41", "gpio42", "gpio43", +}; + +static const char * const qdss_traceclk_a_groups[] = { + "gpio43", +}; + +static const char * const audio_sec_groups[] = { + "gpio44", "gpio45", "gpio46", "gpio47", "gpio62", "gpio62", +}; + +static const char * const wsa_swrm_groups[] = { + "gpio44", "gpio45", +}; + +static const char * const qdss_tracectl_a_groups[] = { + "gpio44", +}; + +static const char * const qdss_tracedata_a_groups[] = { + "gpio45", "gpio46", "gpio47", "gpio48", "gpio49", "gpio50", "gpio51", + "gpio52", "gpio53", "gpio54", "gpio55", "gpio56", "gpio57", "gpio58", + "gpio59", "gpio60", +}; + +static const char * const rx1_groups[] = { + "gpio46", +}; + +static const char * const mac_groups[] = { + "gpio46", "gpio47", "gpio57", "gpio58", +}; + +static const char * const blsp5_i2c_groups[] = { + "gpio48", "gpio49", +}; + +static const char * const blsp5_uart_groups[] = { + "gpio48", "gpio49", +}; + +static const char * const blsp4_uart_groups[] = { + "gpio50", "gpio51", "gpio52", "gpio53", +}; + +static const char * const blsp4_i2c_groups[] = { + "gpio50", "gpio51", +}; + +static const char * const blsp4_spi_groups[] = { + "gpio50", "gpio51", "gpio52", "gpio53", +}; + +static const char * const wci20_groups[] = { + "gpio57", "gpio58", +}; + +static const char * const cxc1_groups[] = { + "gpio57", "gpio58", +}; + +static const char * const rx0_groups[] = { + "gpio59", +}; + +static const char * const prng_rosc0_groups[] = { + "gpio60", +}; + +static const char * const gcc_plltest_groups[] = { + "gpio60", "gpio62", +}; + +static const char * const blsp1_spi_groups[] = { + "gpio61", "gpio62", "gpio63", "gpio64", +}; + +static const char * const audio_pdm1_groups[] = { + "gpio61", "gpio62", "gpio63", "gpio64", +}; + +static const char * const prng_rosc1_groups[] = { + "gpio61", +}; + +static const char * const gcc_tlmm_groups[] = { + "gpio61", +}; + +static const char * const prng_rosc2_groups[] = { + "gpio62", +}; + +static const char * const prng_rosc3_groups[] = { + "gpio63", +}; + +static const char * const tsens_max_groups[] = { + "gpio64", +}; + +static const struct pinfunction ipq9574_functions[] = { + MSM_PIN_FUNCTION(atest_char), + MSM_PIN_FUNCTION(atest_char0), + MSM_PIN_FUNCTION(atest_char1), + MSM_PIN_FUNCTION(atest_char2), + MSM_PIN_FUNCTION(atest_char3), + MSM_PIN_FUNCTION(audio_pdm0), + MSM_PIN_FUNCTION(audio_pdm1), + MSM_PIN_FUNCTION(audio_pri), + MSM_PIN_FUNCTION(audio_sec), + MSM_PIN_FUNCTION(blsp0_spi), + MSM_PIN_FUNCTION(blsp0_uart), + MSM_PIN_FUNCTION(blsp1_i2c), + MSM_PIN_FUNCTION(blsp1_spi), + MSM_PIN_FUNCTION(blsp1_uart), + MSM_PIN_FUNCTION(blsp2_i2c), + MSM_PIN_FUNCTION(blsp2_spi), + MSM_PIN_FUNCTION(blsp2_uart), + MSM_PIN_FUNCTION(blsp3_i2c), + MSM_PIN_FUNCTION(blsp3_spi), + MSM_PIN_FUNCTION(blsp3_uart), + MSM_PIN_FUNCTION(blsp4_i2c), + MSM_PIN_FUNCTION(blsp4_spi), + MSM_PIN_FUNCTION(blsp4_uart), + MSM_PIN_FUNCTION(blsp5_i2c), + MSM_PIN_FUNCTION(blsp5_uart), + MSM_PIN_FUNCTION(cri_trng0), + MSM_PIN_FUNCTION(cri_trng1), + MSM_PIN_FUNCTION(cri_trng2), + MSM_PIN_FUNCTION(cri_trng3), + MSM_PIN_FUNCTION(cxc0), + MSM_PIN_FUNCTION(cxc1), + MSM_PIN_FUNCTION(dbg_out), + MSM_PIN_FUNCTION(dwc_ddrphy), + MSM_PIN_FUNCTION(gcc_plltest), + MSM_PIN_FUNCTION(gcc_tlmm), + MSM_PIN_FUNCTION(gpio), + MSM_PIN_FUNCTION(mac), + MSM_PIN_FUNCTION(mdc), + MSM_PIN_FUNCTION(mdio), + MSM_PIN_FUNCTION(pcie0_clk), + MSM_PIN_FUNCTION(pcie0_wake), + MSM_PIN_FUNCTION(pcie1_clk), + MSM_PIN_FUNCTION(pcie1_wake), + MSM_PIN_FUNCTION(pcie2_clk), + MSM_PIN_FUNCTION(pcie2_wake), + MSM_PIN_FUNCTION(pcie3_clk), + MSM_PIN_FUNCTION(pcie3_wake), + MSM_PIN_FUNCTION(prng_rosc0), + MSM_PIN_FUNCTION(prng_rosc1), + MSM_PIN_FUNCTION(prng_rosc2), + MSM_PIN_FUNCTION(prng_rosc3), + MSM_PIN_FUNCTION(pta), + MSM_PIN_FUNCTION(pwm), + MSM_PIN_FUNCTION(qdss_cti_trig_in_a0), + MSM_PIN_FUNCTION(qdss_cti_trig_in_a1), + MSM_PIN_FUNCTION(qdss_cti_trig_in_b0), + MSM_PIN_FUNCTION(qdss_cti_trig_in_b1), + MSM_PIN_FUNCTION(qdss_cti_trig_out_a0), + MSM_PIN_FUNCTION(qdss_cti_trig_out_a1), + MSM_PIN_FUNCTION(qdss_cti_trig_out_b0), + MSM_PIN_FUNCTION(qdss_cti_trig_out_b1), + MSM_PIN_FUNCTION(qdss_traceclk_a), + MSM_PIN_FUNCTION(qdss_traceclk_b), + MSM_PIN_FUNCTION(qdss_tracectl_a), + MSM_PIN_FUNCTION(qdss_tracectl_b), + MSM_PIN_FUNCTION(qdss_tracedata_a), + MSM_PIN_FUNCTION(qdss_tracedata_b), + MSM_PIN_FUNCTION(qspi_data), + MSM_PIN_FUNCTION(qspi_clk), + MSM_PIN_FUNCTION(qspi_cs), + MSM_PIN_FUNCTION(rx0), + MSM_PIN_FUNCTION(rx1), + MSM_PIN_FUNCTION(sdc_data), + MSM_PIN_FUNCTION(sdc_clk), + MSM_PIN_FUNCTION(sdc_cmd), + MSM_PIN_FUNCTION(sdc_rclk), + MSM_PIN_FUNCTION(tsens_max), + MSM_PIN_FUNCTION(wci20), + MSM_PIN_FUNCTION(wci21), + MSM_PIN_FUNCTION(wsa_swrm), +}; + +static const struct msm_pingroup ipq9574_groups[] = { + PINGROUP(0, sdc_data, qspi_data, qdss_traceclk_b, _, _, _, _, _, _), + PINGROUP(1, sdc_data, qspi_data, qdss_tracectl_b, _, _, _, _, _, _), + PINGROUP(2, sdc_data, qspi_data, qdss_tracedata_b, _, _, _, _, _, _), + PINGROUP(3, sdc_data, qspi_data, qdss_tracedata_b, _, _, _, _, _, _), + PINGROUP(4, sdc_cmd, qspi_cs, qdss_tracedata_b, _, _, _, _, _, _), + PINGROUP(5, sdc_clk, qspi_clk, qdss_tracedata_b, _, _, _, _, _, _), + PINGROUP(6, sdc_data, qdss_tracedata_b, _, _, _, _, _, _, _), + PINGROUP(7, sdc_data, qdss_tracedata_b, _, _, _, _, _, _, _), + PINGROUP(8, sdc_data, qdss_tracedata_b, _, _, _, _, _, _, _), + PINGROUP(9, sdc_data, qdss_tracedata_b, _, _, _, _, _, _, _), + PINGROUP(10, sdc_rclk, qdss_tracedata_b, _, _, _, _, _, _, _), + PINGROUP(11, blsp0_spi, blsp0_uart, qdss_tracedata_b, _, _, _, _, _, _), + PINGROUP(12, blsp0_spi, blsp0_uart, qdss_tracedata_b, _, _, _, _, _, _), + PINGROUP(13, blsp0_spi, blsp0_uart, qdss_tracedata_b, _, _, _, _, _, _), + PINGROUP(14, blsp0_spi, blsp0_uart, qdss_tracedata_b, _, _, _, _, _, _), + PINGROUP(15, blsp3_spi, blsp3_i2c, blsp3_uart, qdss_tracedata_b, _, _, _, _, _), + PINGROUP(16, blsp3_spi, blsp3_i2c, blsp3_uart, qdss_tracedata_b, _, _, _, _, _), + PINGROUP(17, blsp3_spi, blsp3_uart, dbg_out, qdss_tracedata_b, _, _, _, _, _), + PINGROUP(18, blsp3_spi, blsp3_uart, _, _, _, _, _, _, _), + PINGROUP(19, blsp3_spi, _, _, _, _, _, _, _, _), + PINGROUP(20, blsp3_spi, _, cri_trng0, _, _, _, _, _, _), + PINGROUP(21, blsp3_spi, _, cri_trng1, _, _, _, _, _, _), + PINGROUP(22, pcie0_clk, _, pta, _, _, _, _, _, _), + PINGROUP(23, _, pta, wci21, cxc0, _, _, _, _, _), + PINGROUP(24, pcie0_wake, _, pta, wci21, cxc0, _, qdss_cti_trig_out_b0, _, _), + PINGROUP(25, pcie1_clk, _, _, qdss_cti_trig_in_b0, _, _, _, _, _), + PINGROUP(26, _, atest_char0, _, qdss_cti_trig_out_b1, _, _, _, _, _), + PINGROUP(27, pcie1_wake, _, atest_char1, qdss_cti_trig_in_b1, _, _, _, _, _), + PINGROUP(28, pcie2_clk, atest_char2, _, _, _, _, _, _, _), + PINGROUP(29, atest_char3, _, _, _, _, _, _, _, _), + PINGROUP(30, pcie2_wake, pwm, atest_char, _, _, _, _, _, _), + PINGROUP(31, pcie3_clk, pwm, _, qdss_cti_trig_in_a1, _, _, _, _, _), + PINGROUP(32, pwm, _, qdss_cti_trig_out_a1, _, _, _, _, _, _), + PINGROUP(33, pcie3_wake, pwm, _, qdss_cti_trig_in_a0, _, _, _, _, _), + PINGROUP(34, blsp2_uart, blsp2_i2c, blsp2_spi, blsp1_uart, _, cri_trng1, qdss_cti_trig_out_a0, _, _), + PINGROUP(35, blsp2_uart, blsp2_i2c, blsp2_spi, blsp1_uart, _, cri_trng2, _, _, _), + PINGROUP(36, blsp1_uart, blsp1_i2c, blsp2_spi, _, cri_trng3, _, _, _, _), + PINGROUP(37, blsp1_uart, blsp1_i2c, blsp2_spi, _, dwc_ddrphy, _, _, _, _), + PINGROUP(38, mdc, _, cri_trng0, _, _, _, _, _, _), + PINGROUP(39, mdio, _, _, _, _, _, _, _, _), + PINGROUP(40, audio_pri, audio_pdm0, _, _, _, _, _, _, _), + PINGROUP(41, audio_pri, audio_pdm0, _, _, _, _, _, _, _), + PINGROUP(42, audio_pri, audio_pdm0, _, _, _, _, _, _, _), + PINGROUP(43, audio_pri, audio_pdm0, _, qdss_traceclk_a, _, _, _, _, _), + PINGROUP(44, pwm, audio_sec, wsa_swrm, _, qdss_tracectl_a, _, _, _, _), + PINGROUP(45, pwm, audio_sec, wsa_swrm, _, qdss_tracedata_a, _, _, _, _), + PINGROUP(46, pwm, audio_sec, rx1, mac, _, qdss_tracedata_a, _, _, _), + PINGROUP(47, pwm, audio_sec, mac, _, qdss_tracedata_a, _, _, _, _), + PINGROUP(48, blsp5_i2c, blsp5_uart, _, qdss_tracedata_a, _, _, _, _, _), + PINGROUP(49, blsp5_i2c, blsp5_uart, _, qdss_tracedata_a, _, _, _, _, _), + PINGROUP(50, blsp4_uart, blsp4_i2c, blsp4_spi, pwm, qdss_tracedata_a, _, _, _, _), + PINGROUP(51, blsp4_uart, blsp4_i2c, blsp4_spi, pwm, qdss_tracedata_a, _, _, _, _), + PINGROUP(52, blsp4_uart, blsp4_spi, pwm, qdss_tracedata_a, _, _, _, _, _), + PINGROUP(53, blsp4_uart, blsp4_spi, pwm, qdss_tracedata_a, _, _, _, _, _), + PINGROUP(54, pta, pwm, qdss_tracedata_a, _, _, _, _, _, _), + PINGROUP(55, pta, pwm, qdss_tracedata_a, _, _, _, _, _, _), + PINGROUP(56, pta, pwm, qdss_tracedata_a, _, _, _, _, _, _), + PINGROUP(57, wci20, cxc1, mac, pwm, qdss_tracedata_a, _, _, _, _), + PINGROUP(58, wci20, cxc1, mac, pwm, qdss_tracedata_a, _, _, _, _), + PINGROUP(59, rx0, pwm, qdss_tracedata_a, _, _, _, _, _, _), + PINGROUP(60, pwm, prng_rosc0, qdss_tracedata_a, _, gcc_plltest, _, _, _, _), + PINGROUP(61, blsp1_spi, audio_pri, audio_pdm1, audio_pri, pta, prng_rosc1, gcc_tlmm, _, _), + PINGROUP(62, blsp1_spi, audio_sec, audio_pdm1, audio_sec, pta, prng_rosc2, gcc_plltest, _, _), + PINGROUP(63, blsp1_spi, audio_pdm1, pta, prng_rosc3, _, _, _, _, _), + PINGROUP(64, blsp1_spi, audio_pdm1, tsens_max, _, _, _, _, _, _), +}; + +/* Reserving GPIO59 for controlling the QFPROM LDO regulator */ +static const int ipq9574_reserved_gpios[] = { + 59, -1 +}; + +static const struct msm_pinctrl_soc_data ipq9574_pinctrl = { + .pins = ipq9574_pins, + .npins = ARRAY_SIZE(ipq9574_pins), + .functions = ipq9574_functions, + .nfunctions = ARRAY_SIZE(ipq9574_functions), + .groups = ipq9574_groups, + .ngroups = ARRAY_SIZE(ipq9574_groups), + .reserved_gpios = ipq9574_reserved_gpios, + .ngpios = 65, +}; + +static int ipq9574_pinctrl_probe(struct platform_device *pdev) +{ + return msm_pinctrl_probe(pdev, &ipq9574_pinctrl); +} + +static const struct of_device_id ipq9574_pinctrl_of_match[] = { + { .compatible = "qcom,ipq9574-tlmm", }, + { } +}; +MODULE_DEVICE_TABLE(of, ipq9574_pinctrl_of_match); + +static struct platform_driver ipq9574_pinctrl_driver = { + .driver = { + .name = "ipq9574-tlmm", + .of_match_table = ipq9574_pinctrl_of_match, + }, + .probe = ipq9574_pinctrl_probe, + .remove = msm_pinctrl_remove, +}; + +static int __init ipq9574_pinctrl_init(void) +{ + return platform_driver_register(&ipq9574_pinctrl_driver); +} +arch_initcall(ipq9574_pinctrl_init); + +static void __exit ipq9574_pinctrl_exit(void) +{ + platform_driver_unregister(&ipq9574_pinctrl_driver); +} +module_exit(ipq9574_pinctrl_exit); + +MODULE_DESCRIPTION("QTI IPQ9574 TLMM driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c b/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c new file mode 100644 index 0000000000..0b2839d27f --- /dev/null +++ b/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c @@ -0,0 +1,514 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2016-2019, The Linux Foundation. All rights reserved. + * Copyright (c) 2020 Linaro Ltd. + */ + +#include <linux/bitfield.h> +#include <linux/clk.h> +#include <linux/gpio/driver.h> +#include <linux/module.h> +#include <linux/of.h> +#include <linux/platform_device.h> +#include <linux/seq_file.h> + +#include <linux/pinctrl/pinconf-generic.h> +#include <linux/pinctrl/pinconf.h> +#include <linux/pinctrl/pinmux.h> + +#include "../pinctrl-utils.h" + +#include "pinctrl-lpass-lpi.h" + +#define MAX_NR_GPIO 23 +#define GPIO_FUNC 0 +#define MAX_LPI_NUM_CLKS 2 + +struct lpi_pinctrl { + struct device *dev; + struct pinctrl_dev *ctrl; + struct gpio_chip chip; + struct pinctrl_desc desc; + char __iomem *tlmm_base; + char __iomem *slew_base; + struct clk_bulk_data clks[MAX_LPI_NUM_CLKS]; + /* Protects from concurrent register updates */ + struct mutex lock; + DECLARE_BITMAP(ever_gpio, MAX_NR_GPIO); + const struct lpi_pinctrl_variant_data *data; +}; + +static int lpi_gpio_read(struct lpi_pinctrl *state, unsigned int pin, + unsigned int addr) +{ + return ioread32(state->tlmm_base + LPI_TLMM_REG_OFFSET * pin + addr); +} + +static int lpi_gpio_write(struct lpi_pinctrl *state, unsigned int pin, + unsigned int addr, unsigned int val) +{ + iowrite32(val, state->tlmm_base + LPI_TLMM_REG_OFFSET * pin + addr); + + return 0; +} + +static const struct pinctrl_ops lpi_gpio_pinctrl_ops = { + .get_groups_count = pinctrl_generic_get_group_count, + .get_group_name = pinctrl_generic_get_group_name, + .get_group_pins = pinctrl_generic_get_group_pins, + .dt_node_to_map = pinconf_generic_dt_node_to_map_group, + .dt_free_map = pinctrl_utils_free_map, +}; + +static int lpi_gpio_get_functions_count(struct pinctrl_dev *pctldev) +{ + struct lpi_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); + + return pctrl->data->nfunctions; +} + +static const char *lpi_gpio_get_function_name(struct pinctrl_dev *pctldev, + unsigned int function) +{ + struct lpi_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); + + return pctrl->data->functions[function].name; +} + +static int lpi_gpio_get_function_groups(struct pinctrl_dev *pctldev, + unsigned int function, + const char *const **groups, + unsigned *const num_qgroups) +{ + struct lpi_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); + + *groups = pctrl->data->functions[function].groups; + *num_qgroups = pctrl->data->functions[function].ngroups; + + return 0; +} + +static int lpi_gpio_set_mux(struct pinctrl_dev *pctldev, unsigned int function, + unsigned int group) +{ + struct lpi_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); + const struct lpi_pingroup *g = &pctrl->data->groups[group]; + u32 val; + int i, pin = g->pin; + + for (i = 0; i < g->nfuncs; i++) { + if (g->funcs[i] == function) + break; + } + + if (WARN_ON(i == g->nfuncs)) + return -EINVAL; + + mutex_lock(&pctrl->lock); + val = lpi_gpio_read(pctrl, pin, LPI_GPIO_CFG_REG); + + /* + * If this is the first time muxing to GPIO and the direction is + * output, make sure that we're not going to be glitching the pin + * by reading the current state of the pin and setting it as the + * output. + */ + if (i == GPIO_FUNC && (val & LPI_GPIO_OE_MASK) && + !test_and_set_bit(group, pctrl->ever_gpio)) { + u32 io_val = lpi_gpio_read(pctrl, group, LPI_GPIO_VALUE_REG); + + if (io_val & LPI_GPIO_VALUE_IN_MASK) { + if (!(io_val & LPI_GPIO_VALUE_OUT_MASK)) + lpi_gpio_write(pctrl, group, LPI_GPIO_VALUE_REG, + io_val | LPI_GPIO_VALUE_OUT_MASK); + } else { + if (io_val & LPI_GPIO_VALUE_OUT_MASK) + lpi_gpio_write(pctrl, group, LPI_GPIO_VALUE_REG, + io_val & ~LPI_GPIO_VALUE_OUT_MASK); + } + } + + u32p_replace_bits(&val, i, LPI_GPIO_FUNCTION_MASK); + lpi_gpio_write(pctrl, pin, LPI_GPIO_CFG_REG, val); + mutex_unlock(&pctrl->lock); + + return 0; +} + +static const struct pinmux_ops lpi_gpio_pinmux_ops = { + .get_functions_count = lpi_gpio_get_functions_count, + .get_function_name = lpi_gpio_get_function_name, + .get_function_groups = lpi_gpio_get_function_groups, + .set_mux = lpi_gpio_set_mux, +}; + +static int lpi_config_get(struct pinctrl_dev *pctldev, + unsigned int pin, unsigned long *config) +{ + unsigned int param = pinconf_to_config_param(*config); + struct lpi_pinctrl *state = dev_get_drvdata(pctldev->dev); + unsigned int arg = 0; + int is_out; + int pull; + u32 ctl_reg; + + ctl_reg = lpi_gpio_read(state, pin, LPI_GPIO_CFG_REG); + is_out = ctl_reg & LPI_GPIO_OE_MASK; + pull = FIELD_GET(LPI_GPIO_PULL_MASK, ctl_reg); + + switch (param) { + case PIN_CONFIG_BIAS_DISABLE: + if (pull == LPI_GPIO_BIAS_DISABLE) + arg = 1; + break; + case PIN_CONFIG_BIAS_PULL_DOWN: + if (pull == LPI_GPIO_PULL_DOWN) + arg = 1; + break; + case PIN_CONFIG_BIAS_BUS_HOLD: + if (pull == LPI_GPIO_KEEPER) + arg = 1; + break; + case PIN_CONFIG_BIAS_PULL_UP: + if (pull == LPI_GPIO_PULL_UP) + arg = 1; + break; + case PIN_CONFIG_INPUT_ENABLE: + case PIN_CONFIG_OUTPUT: + if (is_out) + arg = 1; + break; + default: + return -EINVAL; + } + + *config = pinconf_to_config_packed(param, arg); + return 0; +} + +static int lpi_config_set(struct pinctrl_dev *pctldev, unsigned int group, + unsigned long *configs, unsigned int nconfs) +{ + struct lpi_pinctrl *pctrl = dev_get_drvdata(pctldev->dev); + unsigned int param, arg, pullup = LPI_GPIO_BIAS_DISABLE, strength = 2; + bool value, output_enabled = false; + const struct lpi_pingroup *g; + unsigned long sval; + int i, slew_offset; + u32 val; + + g = &pctrl->data->groups[group]; + for (i = 0; i < nconfs; i++) { + param = pinconf_to_config_param(configs[i]); + arg = pinconf_to_config_argument(configs[i]); + + switch (param) { + case PIN_CONFIG_BIAS_DISABLE: + pullup = LPI_GPIO_BIAS_DISABLE; + break; + case PIN_CONFIG_BIAS_PULL_DOWN: + pullup = LPI_GPIO_PULL_DOWN; + break; + case PIN_CONFIG_BIAS_BUS_HOLD: + pullup = LPI_GPIO_KEEPER; + break; + case PIN_CONFIG_BIAS_PULL_UP: + pullup = LPI_GPIO_PULL_UP; + break; + case PIN_CONFIG_INPUT_ENABLE: + output_enabled = false; + break; + case PIN_CONFIG_OUTPUT: + output_enabled = true; + value = arg; + break; + case PIN_CONFIG_DRIVE_STRENGTH: + strength = arg; + break; + case PIN_CONFIG_SLEW_RATE: + if (arg > LPI_SLEW_RATE_MAX) { + dev_err(pctldev->dev, "invalid slew rate %u for pin: %d\n", + arg, group); + return -EINVAL; + } + + slew_offset = g->slew_offset; + if (slew_offset == LPI_NO_SLEW) + break; + + mutex_lock(&pctrl->lock); + + sval = ioread32(pctrl->slew_base + LPI_SLEW_RATE_CTL_REG); + sval &= ~(LPI_SLEW_RATE_MASK << slew_offset); + sval |= arg << slew_offset; + iowrite32(sval, pctrl->slew_base + LPI_SLEW_RATE_CTL_REG); + + mutex_unlock(&pctrl->lock); + break; + default: + return -EINVAL; + } + } + + /* + * As per Hardware Programming Guide, when configuring pin as output, + * set the pin value before setting output-enable (OE). + */ + if (output_enabled) { + val = u32_encode_bits(value ? 1 : 0, LPI_GPIO_VALUE_OUT_MASK); + lpi_gpio_write(pctrl, group, LPI_GPIO_VALUE_REG, val); + } + + mutex_lock(&pctrl->lock); + val = lpi_gpio_read(pctrl, group, LPI_GPIO_CFG_REG); + + u32p_replace_bits(&val, pullup, LPI_GPIO_PULL_MASK); + u32p_replace_bits(&val, LPI_GPIO_DS_TO_VAL(strength), + LPI_GPIO_OUT_STRENGTH_MASK); + u32p_replace_bits(&val, output_enabled, LPI_GPIO_OE_MASK); + + lpi_gpio_write(pctrl, group, LPI_GPIO_CFG_REG, val); + mutex_unlock(&pctrl->lock); + + return 0; +} + +static const struct pinconf_ops lpi_gpio_pinconf_ops = { + .is_generic = true, + .pin_config_group_get = lpi_config_get, + .pin_config_group_set = lpi_config_set, +}; + +static int lpi_gpio_direction_input(struct gpio_chip *chip, unsigned int pin) +{ + struct lpi_pinctrl *state = gpiochip_get_data(chip); + unsigned long config; + + config = pinconf_to_config_packed(PIN_CONFIG_INPUT_ENABLE, 1); + + return lpi_config_set(state->ctrl, pin, &config, 1); +} + +static int lpi_gpio_direction_output(struct gpio_chip *chip, + unsigned int pin, int val) +{ + struct lpi_pinctrl *state = gpiochip_get_data(chip); + unsigned long config; + + config = pinconf_to_config_packed(PIN_CONFIG_OUTPUT, val); + + return lpi_config_set(state->ctrl, pin, &config, 1); +} + +static int lpi_gpio_get(struct gpio_chip *chip, unsigned int pin) +{ + struct lpi_pinctrl *state = gpiochip_get_data(chip); + + return lpi_gpio_read(state, pin, LPI_GPIO_VALUE_REG) & + LPI_GPIO_VALUE_IN_MASK; +} + +static void lpi_gpio_set(struct gpio_chip *chip, unsigned int pin, int value) +{ + struct lpi_pinctrl *state = gpiochip_get_data(chip); + unsigned long config; + + config = pinconf_to_config_packed(PIN_CONFIG_OUTPUT, value); + + lpi_config_set(state->ctrl, pin, &config, 1); +} + +#ifdef CONFIG_DEBUG_FS +#include <linux/seq_file.h> + +static unsigned int lpi_regval_to_drive(u32 val) +{ + return (val + 1) * 2; +} + +static void lpi_gpio_dbg_show_one(struct seq_file *s, + struct pinctrl_dev *pctldev, + struct gpio_chip *chip, + unsigned int offset, + unsigned int gpio) +{ + struct lpi_pinctrl *state = gpiochip_get_data(chip); + struct pinctrl_pin_desc pindesc; + unsigned int func; + int is_out; + int drive; + int pull; + u32 ctl_reg; + + static const char * const pulls[] = { + "no pull", + "pull down", + "keeper", + "pull up" + }; + + pctldev = pctldev ? : state->ctrl; + pindesc = pctldev->desc->pins[offset]; + ctl_reg = lpi_gpio_read(state, offset, LPI_GPIO_CFG_REG); + is_out = ctl_reg & LPI_GPIO_OE_MASK; + + func = FIELD_GET(LPI_GPIO_FUNCTION_MASK, ctl_reg); + drive = FIELD_GET(LPI_GPIO_OUT_STRENGTH_MASK, ctl_reg); + pull = FIELD_GET(LPI_GPIO_PULL_MASK, ctl_reg); + + seq_printf(s, " %-8s: %-3s %d", pindesc.name, is_out ? "out" : "in", func); + seq_printf(s, " %dmA", lpi_regval_to_drive(drive)); + seq_printf(s, " %s", pulls[pull]); +} + +static void lpi_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip) +{ + unsigned int gpio = chip->base; + unsigned int i; + + for (i = 0; i < chip->ngpio; i++, gpio++) { + lpi_gpio_dbg_show_one(s, NULL, chip, i, gpio); + seq_puts(s, "\n"); + } +} + +#else +#define lpi_gpio_dbg_show NULL +#endif + +static const struct gpio_chip lpi_gpio_template = { + .direction_input = lpi_gpio_direction_input, + .direction_output = lpi_gpio_direction_output, + .get = lpi_gpio_get, + .set = lpi_gpio_set, + .request = gpiochip_generic_request, + .free = gpiochip_generic_free, + .dbg_show = lpi_gpio_dbg_show, +}; + +static int lpi_build_pin_desc_groups(struct lpi_pinctrl *pctrl) +{ + int i, ret; + + for (i = 0; i < pctrl->data->npins; i++) { + const struct pinctrl_pin_desc *pin_info = pctrl->desc.pins + i; + + ret = pinctrl_generic_add_group(pctrl->ctrl, pin_info->name, + (int *)&pin_info->number, 1, NULL); + if (ret < 0) + goto err_pinctrl; + } + + return 0; + +err_pinctrl: + for (; i > 0; i--) + pinctrl_generic_remove_group(pctrl->ctrl, i - 1); + + return ret; +} + +int lpi_pinctrl_probe(struct platform_device *pdev) +{ + const struct lpi_pinctrl_variant_data *data; + struct device *dev = &pdev->dev; + struct lpi_pinctrl *pctrl; + int ret; + + pctrl = devm_kzalloc(dev, sizeof(*pctrl), GFP_KERNEL); + if (!pctrl) + return -ENOMEM; + + platform_set_drvdata(pdev, pctrl); + + data = of_device_get_match_data(dev); + if (!data) + return -EINVAL; + + if (WARN_ON(data->npins > MAX_NR_GPIO)) + return -EINVAL; + + pctrl->data = data; + pctrl->dev = &pdev->dev; + + pctrl->clks[0].id = "core"; + pctrl->clks[1].id = "audio"; + + pctrl->tlmm_base = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(pctrl->tlmm_base)) + return dev_err_probe(dev, PTR_ERR(pctrl->tlmm_base), + "TLMM resource not provided\n"); + + pctrl->slew_base = devm_platform_ioremap_resource(pdev, 1); + if (IS_ERR(pctrl->slew_base)) + return dev_err_probe(dev, PTR_ERR(pctrl->slew_base), + "Slew resource not provided\n"); + + ret = devm_clk_bulk_get_optional(dev, MAX_LPI_NUM_CLKS, pctrl->clks); + if (ret) + return ret; + + ret = clk_bulk_prepare_enable(MAX_LPI_NUM_CLKS, pctrl->clks); + if (ret) + return dev_err_probe(dev, ret, "Can't enable clocks\n"); + + pctrl->desc.pctlops = &lpi_gpio_pinctrl_ops; + pctrl->desc.pmxops = &lpi_gpio_pinmux_ops; + pctrl->desc.confops = &lpi_gpio_pinconf_ops; + pctrl->desc.owner = THIS_MODULE; + pctrl->desc.name = dev_name(dev); + pctrl->desc.pins = data->pins; + pctrl->desc.npins = data->npins; + pctrl->chip = lpi_gpio_template; + pctrl->chip.parent = dev; + pctrl->chip.base = -1; + pctrl->chip.ngpio = data->npins; + pctrl->chip.label = dev_name(dev); + pctrl->chip.can_sleep = false; + + mutex_init(&pctrl->lock); + + pctrl->ctrl = devm_pinctrl_register(dev, &pctrl->desc, pctrl); + if (IS_ERR(pctrl->ctrl)) { + ret = PTR_ERR(pctrl->ctrl); + dev_err(dev, "failed to add pin controller\n"); + goto err_pinctrl; + } + + ret = lpi_build_pin_desc_groups(pctrl); + if (ret) + goto err_pinctrl; + + ret = devm_gpiochip_add_data(dev, &pctrl->chip, pctrl); + if (ret) { + dev_err(pctrl->dev, "can't add gpio chip\n"); + goto err_pinctrl; + } + + return 0; + +err_pinctrl: + mutex_destroy(&pctrl->lock); + clk_bulk_disable_unprepare(MAX_LPI_NUM_CLKS, pctrl->clks); + + return ret; +} +EXPORT_SYMBOL_GPL(lpi_pinctrl_probe); + +int lpi_pinctrl_remove(struct platform_device *pdev) +{ + struct lpi_pinctrl *pctrl = platform_get_drvdata(pdev); + int i; + + mutex_destroy(&pctrl->lock); + clk_bulk_disable_unprepare(MAX_LPI_NUM_CLKS, pctrl->clks); + + for (i = 0; i < pctrl->data->npins; i++) + pinctrl_generic_remove_group(pctrl->ctrl, i); + + return 0; +} +EXPORT_SYMBOL_GPL(lpi_pinctrl_remove); + +MODULE_DESCRIPTION("QTI LPI GPIO pin control driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/pinctrl/qcom/pinctrl-lpass-lpi.h b/drivers/pinctrl/qcom/pinctrl-lpass-lpi.h new file mode 100644 index 0000000000..29047bb80b --- /dev/null +++ b/drivers/pinctrl/qcom/pinctrl-lpass-lpi.h @@ -0,0 +1,90 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2016-2019, The Linux Foundation. All rights reserved. + * Copyright (c) 2020 Linaro Ltd. + */ +#ifndef __PINCTRL_LPASS_LPI_H__ +#define __PINCTRL_LPASS_LPI_H__ + +#include <linux/bits.h> +#include <linux/kernel.h> + +#include "../core.h" + +struct platform_device; + +struct pinctrl_pin_desc; + +#define LPI_SLEW_RATE_CTL_REG 0xa000 +#define LPI_TLMM_REG_OFFSET 0x1000 +#define LPI_SLEW_RATE_MAX 0x03 +#define LPI_SLEW_BITS_SIZE 0x02 +#define LPI_SLEW_RATE_MASK GENMASK(1, 0) +#define LPI_GPIO_CFG_REG 0x00 +#define LPI_GPIO_PULL_MASK GENMASK(1, 0) +#define LPI_GPIO_FUNCTION_MASK GENMASK(5, 2) +#define LPI_GPIO_OUT_STRENGTH_MASK GENMASK(8, 6) +#define LPI_GPIO_OE_MASK BIT(9) +#define LPI_GPIO_VALUE_REG 0x04 +#define LPI_GPIO_VALUE_IN_MASK BIT(0) +#define LPI_GPIO_VALUE_OUT_MASK BIT(1) + +#define LPI_GPIO_BIAS_DISABLE 0x0 +#define LPI_GPIO_PULL_DOWN 0x1 +#define LPI_GPIO_KEEPER 0x2 +#define LPI_GPIO_PULL_UP 0x3 +#define LPI_GPIO_DS_TO_VAL(v) (v / 2 - 1) +#define LPI_NO_SLEW -1 + +#define LPI_FUNCTION(fname) \ + [LPI_MUX_##fname] = { \ + .name = #fname, \ + .groups = fname##_groups, \ + .ngroups = ARRAY_SIZE(fname##_groups), \ + } + +#define LPI_PINGROUP(id, soff, f1, f2, f3, f4) \ + { \ + .group.name = "gpio" #id, \ + .group.pins = gpio##id##_pins, \ + .pin = id, \ + .slew_offset = soff, \ + .group.num_pins = ARRAY_SIZE(gpio##id##_pins), \ + .funcs = (int[]){ \ + LPI_MUX_gpio, \ + LPI_MUX_##f1, \ + LPI_MUX_##f2, \ + LPI_MUX_##f3, \ + LPI_MUX_##f4, \ + }, \ + .nfuncs = 5, \ + } + +struct lpi_pingroup { + struct group_desc group; + unsigned int pin; + /* Bit offset in slew register for SoundWire pins only */ + int slew_offset; + unsigned int *funcs; + unsigned int nfuncs; +}; + +struct lpi_function { + const char *name; + const char * const *groups; + unsigned int ngroups; +}; + +struct lpi_pinctrl_variant_data { + const struct pinctrl_pin_desc *pins; + int npins; + const struct lpi_pingroup *groups; + int ngroups; + const struct lpi_function *functions; + int nfunctions; +}; + +int lpi_pinctrl_probe(struct platform_device *pdev); +int lpi_pinctrl_remove(struct platform_device *pdev); + +#endif /*__PINCTRL_LPASS_LPI_H__*/ diff --git a/drivers/pinctrl/qcom/pinctrl-mdm9607.c b/drivers/pinctrl/qcom/pinctrl-mdm9607.c new file mode 100644 index 0000000000..e7cd3ef1cf --- /dev/null +++ b/drivers/pinctrl/qcom/pinctrl-mdm9607.c @@ -0,0 +1,1079 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2021, Konrad Dybcio <konrad.dybcio@somainline.org> + * + * based on pinctrl-msm8916.c + */ + +#include <linux/module.h> +#include <linux/of.h> +#include <linux/platform_device.h> + +#include "pinctrl-msm.h" + +static const struct pinctrl_pin_desc mdm9607_pins[] = { + PINCTRL_PIN(0, "GPIO_0"), + PINCTRL_PIN(1, "GPIO_1"), + PINCTRL_PIN(2, "GPIO_2"), + PINCTRL_PIN(3, "GPIO_3"), + PINCTRL_PIN(4, "GPIO_4"), + PINCTRL_PIN(5, "GPIO_5"), + PINCTRL_PIN(6, "GPIO_6"), + PINCTRL_PIN(7, "GPIO_7"), + PINCTRL_PIN(8, "GPIO_8"), + PINCTRL_PIN(9, "GPIO_9"), + PINCTRL_PIN(10, "GPIO_10"), + PINCTRL_PIN(11, "GPIO_11"), + PINCTRL_PIN(12, "GPIO_12"), + PINCTRL_PIN(13, "GPIO_13"), + PINCTRL_PIN(14, "GPIO_14"), + PINCTRL_PIN(15, "GPIO_15"), + PINCTRL_PIN(16, "GPIO_16"), + PINCTRL_PIN(17, "GPIO_17"), + PINCTRL_PIN(18, "GPIO_18"), + PINCTRL_PIN(19, "GPIO_19"), + PINCTRL_PIN(20, "GPIO_20"), + PINCTRL_PIN(21, "GPIO_21"), + PINCTRL_PIN(22, "GPIO_22"), + PINCTRL_PIN(23, "GPIO_23"), + PINCTRL_PIN(24, "GPIO_24"), + PINCTRL_PIN(25, "GPIO_25"), + PINCTRL_PIN(26, "GPIO_26"), + PINCTRL_PIN(27, "GPIO_27"), + PINCTRL_PIN(28, "GPIO_28"), + PINCTRL_PIN(29, "GPIO_29"), + PINCTRL_PIN(30, "GPIO_30"), + PINCTRL_PIN(31, "GPIO_31"), + PINCTRL_PIN(32, "GPIO_32"), + PINCTRL_PIN(33, "GPIO_33"), + PINCTRL_PIN(34, "GPIO_34"), + PINCTRL_PIN(35, "GPIO_35"), + PINCTRL_PIN(36, "GPIO_36"), + PINCTRL_PIN(37, "GPIO_37"), + PINCTRL_PIN(38, "GPIO_38"), + PINCTRL_PIN(39, "GPIO_39"), + PINCTRL_PIN(40, "GPIO_40"), + PINCTRL_PIN(41, "GPIO_41"), + PINCTRL_PIN(42, "GPIO_42"), + PINCTRL_PIN(43, "GPIO_43"), + PINCTRL_PIN(44, "GPIO_44"), + PINCTRL_PIN(45, "GPIO_45"), + PINCTRL_PIN(46, "GPIO_46"), + PINCTRL_PIN(47, "GPIO_47"), + PINCTRL_PIN(48, "GPIO_48"), + PINCTRL_PIN(49, "GPIO_49"), + PINCTRL_PIN(50, "GPIO_50"), + PINCTRL_PIN(51, "GPIO_51"), + PINCTRL_PIN(52, "GPIO_52"), + PINCTRL_PIN(53, "GPIO_53"), + PINCTRL_PIN(54, "GPIO_54"), + PINCTRL_PIN(55, "GPIO_55"), + PINCTRL_PIN(56, "GPIO_56"), + PINCTRL_PIN(57, "GPIO_57"), + PINCTRL_PIN(58, "GPIO_58"), + PINCTRL_PIN(59, "GPIO_59"), + PINCTRL_PIN(60, "GPIO_60"), + PINCTRL_PIN(61, "GPIO_61"), + PINCTRL_PIN(62, "GPIO_62"), + PINCTRL_PIN(63, "GPIO_63"), + PINCTRL_PIN(64, "GPIO_64"), + PINCTRL_PIN(65, "GPIO_65"), + PINCTRL_PIN(66, "GPIO_66"), + PINCTRL_PIN(67, "GPIO_67"), + PINCTRL_PIN(68, "GPIO_68"), + PINCTRL_PIN(69, "GPIO_69"), + PINCTRL_PIN(70, "GPIO_70"), + PINCTRL_PIN(71, "GPIO_71"), + PINCTRL_PIN(72, "GPIO_72"), + PINCTRL_PIN(73, "GPIO_73"), + PINCTRL_PIN(74, "GPIO_74"), + PINCTRL_PIN(75, "GPIO_75"), + PINCTRL_PIN(76, "GPIO_76"), + PINCTRL_PIN(77, "GPIO_77"), + PINCTRL_PIN(78, "GPIO_78"), + PINCTRL_PIN(79, "GPIO_79"), + PINCTRL_PIN(80, "SDC1_CLK"), + PINCTRL_PIN(81, "SDC1_CMD"), + PINCTRL_PIN(82, "SDC1_DATA"), + PINCTRL_PIN(83, "SDC2_CLK"), + PINCTRL_PIN(84, "SDC2_CMD"), + PINCTRL_PIN(85, "SDC2_DATA"), + PINCTRL_PIN(86, "QDSD_CLK"), + PINCTRL_PIN(87, "QDSD_CMD"), + PINCTRL_PIN(88, "QDSD_DATA0"), + PINCTRL_PIN(89, "QDSD_DATA1"), + PINCTRL_PIN(90, "QDSD_DATA2"), + PINCTRL_PIN(91, "QDSD_DATA3"), +}; + +#define DECLARE_MSM_GPIO_PINS(pin) \ + static const unsigned int gpio##pin##_pins[] = { pin } + +DECLARE_MSM_GPIO_PINS(0); +DECLARE_MSM_GPIO_PINS(1); +DECLARE_MSM_GPIO_PINS(2); +DECLARE_MSM_GPIO_PINS(3); +DECLARE_MSM_GPIO_PINS(4); +DECLARE_MSM_GPIO_PINS(5); +DECLARE_MSM_GPIO_PINS(6); +DECLARE_MSM_GPIO_PINS(7); +DECLARE_MSM_GPIO_PINS(8); +DECLARE_MSM_GPIO_PINS(9); +DECLARE_MSM_GPIO_PINS(10); +DECLARE_MSM_GPIO_PINS(11); +DECLARE_MSM_GPIO_PINS(12); +DECLARE_MSM_GPIO_PINS(13); +DECLARE_MSM_GPIO_PINS(14); +DECLARE_MSM_GPIO_PINS(15); +DECLARE_MSM_GPIO_PINS(16); +DECLARE_MSM_GPIO_PINS(17); +DECLARE_MSM_GPIO_PINS(18); +DECLARE_MSM_GPIO_PINS(19); +DECLARE_MSM_GPIO_PINS(20); +DECLARE_MSM_GPIO_PINS(21); +DECLARE_MSM_GPIO_PINS(22); +DECLARE_MSM_GPIO_PINS(23); +DECLARE_MSM_GPIO_PINS(24); +DECLARE_MSM_GPIO_PINS(25); +DECLARE_MSM_GPIO_PINS(26); +DECLARE_MSM_GPIO_PINS(27); +DECLARE_MSM_GPIO_PINS(28); +DECLARE_MSM_GPIO_PINS(29); +DECLARE_MSM_GPIO_PINS(30); +DECLARE_MSM_GPIO_PINS(31); +DECLARE_MSM_GPIO_PINS(32); +DECLARE_MSM_GPIO_PINS(33); +DECLARE_MSM_GPIO_PINS(34); +DECLARE_MSM_GPIO_PINS(35); +DECLARE_MSM_GPIO_PINS(36); +DECLARE_MSM_GPIO_PINS(37); +DECLARE_MSM_GPIO_PINS(38); +DECLARE_MSM_GPIO_PINS(39); +DECLARE_MSM_GPIO_PINS(40); +DECLARE_MSM_GPIO_PINS(41); +DECLARE_MSM_GPIO_PINS(42); +DECLARE_MSM_GPIO_PINS(43); +DECLARE_MSM_GPIO_PINS(44); +DECLARE_MSM_GPIO_PINS(45); +DECLARE_MSM_GPIO_PINS(46); +DECLARE_MSM_GPIO_PINS(47); +DECLARE_MSM_GPIO_PINS(48); +DECLARE_MSM_GPIO_PINS(49); +DECLARE_MSM_GPIO_PINS(50); +DECLARE_MSM_GPIO_PINS(51); +DECLARE_MSM_GPIO_PINS(52); +DECLARE_MSM_GPIO_PINS(53); +DECLARE_MSM_GPIO_PINS(54); +DECLARE_MSM_GPIO_PINS(55); +DECLARE_MSM_GPIO_PINS(56); +DECLARE_MSM_GPIO_PINS(57); +DECLARE_MSM_GPIO_PINS(58); +DECLARE_MSM_GPIO_PINS(59); +DECLARE_MSM_GPIO_PINS(60); +DECLARE_MSM_GPIO_PINS(61); +DECLARE_MSM_GPIO_PINS(62); +DECLARE_MSM_GPIO_PINS(63); +DECLARE_MSM_GPIO_PINS(64); +DECLARE_MSM_GPIO_PINS(65); +DECLARE_MSM_GPIO_PINS(66); +DECLARE_MSM_GPIO_PINS(67); +DECLARE_MSM_GPIO_PINS(68); +DECLARE_MSM_GPIO_PINS(69); +DECLARE_MSM_GPIO_PINS(70); +DECLARE_MSM_GPIO_PINS(71); +DECLARE_MSM_GPIO_PINS(72); +DECLARE_MSM_GPIO_PINS(73); +DECLARE_MSM_GPIO_PINS(74); +DECLARE_MSM_GPIO_PINS(75); +DECLARE_MSM_GPIO_PINS(76); +DECLARE_MSM_GPIO_PINS(77); +DECLARE_MSM_GPIO_PINS(78); +DECLARE_MSM_GPIO_PINS(79); + +static const unsigned int sdc1_clk_pins[] = { 80 }; +static const unsigned int sdc1_cmd_pins[] = { 81 }; +static const unsigned int sdc1_data_pins[] = { 82 }; +static const unsigned int sdc2_clk_pins[] = { 83 }; +static const unsigned int sdc2_cmd_pins[] = { 84 }; +static const unsigned int sdc2_data_pins[] = { 85 }; +static const unsigned int qdsd_clk_pins[] = { 86 }; +static const unsigned int qdsd_cmd_pins[] = { 87 }; +static const unsigned int qdsd_data0_pins[] = { 88 }; +static const unsigned int qdsd_data1_pins[] = { 89 }; +static const unsigned int qdsd_data2_pins[] = { 90 }; +static const unsigned int qdsd_data3_pins[] = { 91 }; + +#define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7, f8, f9) \ + { \ + .grp = PINCTRL_PINGROUP("gpio" #id, \ + gpio##id##_pins, \ + ARRAY_SIZE(gpio##id##_pins)), \ + .funcs = (int[]){ \ + msm_mux_gpio, \ + msm_mux_##f1, \ + msm_mux_##f2, \ + msm_mux_##f3, \ + msm_mux_##f4, \ + msm_mux_##f5, \ + msm_mux_##f6, \ + msm_mux_##f7, \ + msm_mux_##f8, \ + msm_mux_##f9 \ + }, \ + .nfuncs = 10, \ + .ctl_reg = 0x1000 * id, \ + .io_reg = 0x4 + 0x1000 * id, \ + .intr_cfg_reg = 0x8 + 0x1000 * id, \ + .intr_status_reg = 0xc + 0x1000 * id, \ + .intr_target_reg = 0x8 + 0x1000 * id, \ + .mux_bit = 2, \ + .pull_bit = 0, \ + .drv_bit = 6, \ + .oe_bit = 9, \ + .in_bit = 0, \ + .out_bit = 1, \ + .intr_enable_bit = 0, \ + .intr_status_bit = 0, \ + .intr_target_bit = 5, \ + .intr_target_kpss_val = 4, \ + .intr_raw_status_bit = 4, \ + .intr_polarity_bit = 1, \ + .intr_detection_bit = 2, \ + .intr_detection_width = 2, \ + } + +#define SDC_PINGROUP(pg_name, ctl, pull, drv) \ + { \ + .grp = PINCTRL_PINGROUP(#pg_name, \ + pg_name##_pins, \ + ARRAY_SIZE(pg_name##_pins)), \ + .ctl_reg = ctl, \ + .io_reg = 0, \ + .intr_cfg_reg = 0, \ + .intr_status_reg = 0, \ + .intr_target_reg = 0, \ + .mux_bit = -1, \ + .pull_bit = pull, \ + .drv_bit = drv, \ + .oe_bit = -1, \ + .in_bit = -1, \ + .out_bit = -1, \ + .intr_enable_bit = -1, \ + .intr_status_bit = -1, \ + .intr_target_bit = -1, \ + .intr_target_kpss_val = -1, \ + .intr_raw_status_bit = -1, \ + .intr_polarity_bit = -1, \ + .intr_detection_bit = -1, \ + .intr_detection_width = -1, \ + } + +enum mdm9607_functions { + msm_mux_adsp_ext, + msm_mux_atest_bbrx0, + msm_mux_atest_bbrx1, + msm_mux_atest_char, + msm_mux_atest_char0, + msm_mux_atest_char1, + msm_mux_atest_char2, + msm_mux_atest_char3, + msm_mux_atest_combodac_to_gpio_native, + msm_mux_atest_gpsadc_dtest0_native, + msm_mux_atest_gpsadc_dtest1_native, + msm_mux_atest_tsens, + msm_mux_backlight_en_b, + msm_mux_bimc_dte0, + msm_mux_bimc_dte1, + msm_mux_blsp1_spi, + msm_mux_blsp2_spi, + msm_mux_blsp3_spi, + msm_mux_blsp_i2c1, + msm_mux_blsp_i2c2, + msm_mux_blsp_i2c3, + msm_mux_blsp_i2c4, + msm_mux_blsp_i2c5, + msm_mux_blsp_i2c6, + msm_mux_blsp_spi1, + msm_mux_blsp_spi2, + msm_mux_blsp_spi3, + msm_mux_blsp_spi4, + msm_mux_blsp_spi5, + msm_mux_blsp_spi6, + msm_mux_blsp_uart1, + msm_mux_blsp_uart2, + msm_mux_blsp_uart3, + msm_mux_blsp_uart4, + msm_mux_blsp_uart5, + msm_mux_blsp_uart6, + msm_mux_blsp_uim1, + msm_mux_blsp_uim2, + msm_mux_codec_int, + msm_mux_codec_rst, + msm_mux_coex_uart, + msm_mux_cri_trng, + msm_mux_cri_trng0, + msm_mux_cri_trng1, + msm_mux_dbg_out, + msm_mux_ebi0_wrcdc, + msm_mux_ebi2_a, + msm_mux_ebi2_a_d_8_b, + msm_mux_ebi2_lcd, + msm_mux_ebi2_lcd_cs_n_b, + msm_mux_ebi2_lcd_te_b, + msm_mux_eth_irq, + msm_mux_eth_rst, + msm_mux_gcc_gp1_clk_a, + msm_mux_gcc_gp1_clk_b, + msm_mux_gcc_gp2_clk_a, + msm_mux_gcc_gp2_clk_b, + msm_mux_gcc_gp3_clk_a, + msm_mux_gcc_gp3_clk_b, + msm_mux_gcc_plltest, + msm_mux_gcc_tlmm, + msm_mux_gmac_mdio, + msm_mux_gpio, + msm_mux_gsm0_tx, + msm_mux_lcd_rst, + msm_mux_ldo_en, + msm_mux_ldo_update, + msm_mux_m_voc, + msm_mux_modem_tsync, + msm_mux_nav_ptp_pps_in_a, + msm_mux_nav_ptp_pps_in_b, + msm_mux_nav_tsync_out_a, + msm_mux_nav_tsync_out_b, + msm_mux_pa_indicator, + msm_mux_pbs0, + msm_mux_pbs1, + msm_mux_pbs2, + msm_mux_pri_mi2s_data0_a, + msm_mux_pri_mi2s_data1_a, + msm_mux_pri_mi2s_mclk_a, + msm_mux_pri_mi2s_sck_a, + msm_mux_pri_mi2s_ws_a, + msm_mux_prng_rosc, + msm_mux_ptp_pps_out_a, + msm_mux_ptp_pps_out_b, + msm_mux_pwr_crypto_enabled_a, + msm_mux_pwr_crypto_enabled_b, + msm_mux_pwr_modem_enabled_a, + msm_mux_pwr_modem_enabled_b, + msm_mux_pwr_nav_enabled_a, + msm_mux_pwr_nav_enabled_b, + msm_mux_qdss_cti_trig_in_a0, + msm_mux_qdss_cti_trig_in_a1, + msm_mux_qdss_cti_trig_in_b0, + msm_mux_qdss_cti_trig_in_b1, + msm_mux_qdss_cti_trig_out_a0, + msm_mux_qdss_cti_trig_out_a1, + msm_mux_qdss_cti_trig_out_b0, + msm_mux_qdss_cti_trig_out_b1, + msm_mux_qdss_traceclk_a, + msm_mux_qdss_traceclk_b, + msm_mux_qdss_tracectl_a, + msm_mux_qdss_tracectl_b, + msm_mux_qdss_tracedata_a, + msm_mux_qdss_tracedata_b, + msm_mux_rcm_marker1, + msm_mux_rcm_marker2, + msm_mux_sd_write, + msm_mux_sec_mi2s, + msm_mux_sensor_en, + msm_mux_sensor_int2, + msm_mux_sensor_int3, + msm_mux_sensor_rst, + msm_mux_ssbi1, + msm_mux_ssbi2, + msm_mux_touch_rst, + msm_mux_ts_int, + msm_mux_uim1_clk, + msm_mux_uim1_data, + msm_mux_uim1_present, + msm_mux_uim1_reset, + msm_mux_uim2_clk, + msm_mux_uim2_data, + msm_mux_uim2_present, + msm_mux_uim2_reset, + msm_mux_uim_batt, + msm_mux_wlan_en1, + msm_mux__, +}; + +static const char * const gpio_groups[] = { + "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7", + "gpio8", "gpio9", "gpio10", "gpio11", "gpio12", "gpio13", "gpio14", + "gpio15", "gpio16", "gpio17", "gpio18", "gpio19", "gpio20", "gpio21", + "gpio22", "gpio23", "gpio24", "gpio25", "gpio26", "gpio27", "gpio28", + "gpio29", "gpio30", "gpio31", "gpio32", "gpio33", "gpio34", "gpio35", + "gpio36", "gpio37", "gpio38", "gpio39", "gpio40", "gpio41", "gpio42", + "gpio43", "gpio44", "gpio45", "gpio46", "gpio47", "gpio48", "gpio49", + "gpio50", "gpio51", "gpio52", "gpio53", "gpio54", "gpio55", "gpio56", + "gpio57", "gpio58", "gpio59", "gpio60", "gpio61", "gpio62", "gpio63", + "gpio64", "gpio65", "gpio66", "gpio67", "gpio68", "gpio69", "gpio70", + "gpio71", "gpio72", "gpio73", "gpio74", "gpio75", "gpio76", "gpio77", + "gpio78", "gpio79", +}; +static const char * const blsp_spi3_groups[] = { + "gpio0", "gpio1", "gpio2", "gpio3", +}; +static const char * const blsp_uart3_groups[] = { + "gpio0", "gpio1", "gpio2", "gpio3", +}; +static const char * const qdss_tracedata_a_groups[] = { + "gpio0", "gpio1", "gpio4", "gpio5", "gpio20", "gpio21", "gpio22", + "gpio23", "gpio24", "gpio25", "gpio26", "gpio75", "gpio76", "gpio77", + "gpio78", "gpio79", +}; +static const char * const bimc_dte1_groups[] = { + "gpio1", "gpio24", +}; +static const char * const blsp_i2c3_groups[] = { + "gpio2", "gpio3", +}; +static const char * const qdss_traceclk_a_groups[] = { + "gpio2", +}; +static const char * const bimc_dte0_groups[] = { + "gpio2", "gpio15", +}; +static const char * const qdss_cti_trig_in_a1_groups[] = { + "gpio3", +}; +static const char * const blsp_spi2_groups[] = { + "gpio4", "gpio5", "gpio6", "gpio7", +}; +static const char * const blsp_uart2_groups[] = { + "gpio4", "gpio5", "gpio6", "gpio7", +}; +static const char * const blsp_uim2_groups[] = { + "gpio4", "gpio5", +}; +static const char * const blsp_i2c2_groups[] = { + "gpio6", "gpio7", +}; +static const char * const qdss_tracectl_a_groups[] = { + "gpio6", +}; +static const char * const sensor_int2_groups[] = { + "gpio8", +}; +static const char * const blsp_spi5_groups[] = { + "gpio8", "gpio9", "gpio10", "gpio11", +}; +static const char * const blsp_uart5_groups[] = { + "gpio8", "gpio9", "gpio10", "gpio11", +}; +static const char * const ebi2_lcd_groups[] = { + "gpio8", "gpio11", "gpio74", "gpio78", +}; +static const char * const m_voc_groups[] = { + "gpio8", "gpio78", +}; +static const char * const sensor_int3_groups[] = { + "gpio9", +}; +static const char * const sensor_en_groups[] = { + "gpio10", +}; +static const char * const blsp_i2c5_groups[] = { + "gpio10", "gpio11", +}; +static const char * const ebi2_a_groups[] = { + "gpio10", +}; +static const char * const qdss_tracedata_b_groups[] = { + "gpio10", "gpio39", "gpio40", "gpio41", "gpio42", "gpio43", "gpio46", + "gpio47", "gpio48", "gpio51", "gpio52", "gpio53", "gpio54", "gpio55", + "gpio58", "gpio59", +}; +static const char * const sensor_rst_groups[] = { + "gpio11", +}; +static const char * const blsp2_spi_groups[] = { + "gpio11", "gpio13", "gpio77", +}; +static const char * const blsp_spi1_groups[] = { + "gpio12", "gpio13", "gpio14", "gpio15", +}; +static const char * const blsp_uart1_groups[] = { + "gpio12", "gpio13", "gpio14", "gpio15", +}; +static const char * const blsp_uim1_groups[] = { + "gpio12", "gpio13", +}; +static const char * const blsp3_spi_groups[] = { + "gpio12", "gpio26", "gpio76", +}; +static const char * const gcc_gp2_clk_b_groups[] = { + "gpio12", +}; +static const char * const gcc_gp3_clk_b_groups[] = { + "gpio13", +}; +static const char * const blsp_i2c1_groups[] = { + "gpio14", "gpio15", +}; +static const char * const gcc_gp1_clk_b_groups[] = { + "gpio14", +}; +static const char * const blsp_spi4_groups[] = { + "gpio16", "gpio17", "gpio18", "gpio19", +}; +static const char * const blsp_uart4_groups[] = { + "gpio16", "gpio17", "gpio18", "gpio19", +}; +static const char * const rcm_marker1_groups[] = { + "gpio18", +}; +static const char * const blsp_i2c4_groups[] = { + "gpio18", "gpio19", +}; +static const char * const qdss_cti_trig_out_a1_groups[] = { + "gpio18", +}; +static const char * const rcm_marker2_groups[] = { + "gpio19", +}; +static const char * const qdss_cti_trig_out_a0_groups[] = { + "gpio19", +}; +static const char * const blsp_spi6_groups[] = { + "gpio20", "gpio21", "gpio22", "gpio23", +}; +static const char * const blsp_uart6_groups[] = { + "gpio20", "gpio21", "gpio22", "gpio23", +}; +static const char * const pri_mi2s_ws_a_groups[] = { + "gpio20", +}; +static const char * const ebi2_lcd_te_b_groups[] = { + "gpio20", +}; +static const char * const blsp1_spi_groups[] = { + "gpio20", "gpio21", "gpio78", +}; +static const char * const backlight_en_b_groups[] = { + "gpio21", +}; +static const char * const pri_mi2s_data0_a_groups[] = { + "gpio21", +}; +static const char * const pri_mi2s_data1_a_groups[] = { + "gpio22", +}; +static const char * const blsp_i2c6_groups[] = { + "gpio22", "gpio23", +}; +static const char * const ebi2_a_d_8_b_groups[] = { + "gpio22", +}; +static const char * const pri_mi2s_sck_a_groups[] = { + "gpio23", +}; +static const char * const ebi2_lcd_cs_n_b_groups[] = { + "gpio23", +}; +static const char * const touch_rst_groups[] = { + "gpio24", +}; +static const char * const pri_mi2s_mclk_a_groups[] = { + "gpio24", +}; +static const char * const pwr_nav_enabled_a_groups[] = { + "gpio24", +}; +static const char * const ts_int_groups[] = { + "gpio25", +}; +static const char * const sd_write_groups[] = { + "gpio25", +}; +static const char * const pwr_crypto_enabled_a_groups[] = { + "gpio25", +}; +static const char * const codec_rst_groups[] = { + "gpio26", +}; +static const char * const adsp_ext_groups[] = { + "gpio26", +}; +static const char * const atest_combodac_to_gpio_native_groups[] = { + "gpio26", "gpio27", "gpio28", "gpio29", "gpio30", "gpio31", "gpio32", + "gpio33", "gpio34", "gpio35", "gpio41", "gpio45", "gpio49", "gpio50", + "gpio51", "gpio52", "gpio54", "gpio55", "gpio57", "gpio59", +}; +static const char * const uim2_data_groups[] = { + "gpio27", +}; +static const char * const gmac_mdio_groups[] = { + "gpio27", "gpio28", +}; +static const char * const gcc_gp1_clk_a_groups[] = { + "gpio27", +}; +static const char * const uim2_clk_groups[] = { + "gpio28", +}; +static const char * const gcc_gp2_clk_a_groups[] = { + "gpio28", +}; +static const char * const eth_irq_groups[] = { + "gpio29", +}; +static const char * const uim2_reset_groups[] = { + "gpio29", +}; +static const char * const gcc_gp3_clk_a_groups[] = { + "gpio29", +}; +static const char * const eth_rst_groups[] = { + "gpio30", +}; +static const char * const uim2_present_groups[] = { + "gpio30", +}; +static const char * const prng_rosc_groups[] = { + "gpio30", +}; +static const char * const uim1_data_groups[] = { + "gpio31", +}; +static const char * const uim1_clk_groups[] = { + "gpio32", +}; +static const char * const uim1_reset_groups[] = { + "gpio33", +}; +static const char * const uim1_present_groups[] = { + "gpio34", +}; +static const char * const gcc_plltest_groups[] = { + "gpio34", "gpio35", +}; +static const char * const uim_batt_groups[] = { + "gpio35", +}; +static const char * const coex_uart_groups[] = { + "gpio36", "gpio37", +}; +static const char * const codec_int_groups[] = { + "gpio38", +}; +static const char * const qdss_cti_trig_in_a0_groups[] = { + "gpio38", +}; +static const char * const atest_bbrx1_groups[] = { + "gpio39", +}; +static const char * const cri_trng0_groups[] = { + "gpio40", +}; +static const char * const atest_bbrx0_groups[] = { + "gpio40", +}; +static const char * const cri_trng_groups[] = { + "gpio42", +}; +static const char * const qdss_cti_trig_in_b0_groups[] = { + "gpio44", +}; +static const char * const atest_gpsadc_dtest0_native_groups[] = { + "gpio44", +}; +static const char * const qdss_cti_trig_out_b0_groups[] = { + "gpio45", +}; +static const char * const qdss_tracectl_b_groups[] = { + "gpio49", +}; +static const char * const qdss_traceclk_b_groups[] = { + "gpio50", +}; +static const char * const pa_indicator_groups[] = { + "gpio51", +}; +static const char * const modem_tsync_groups[] = { + "gpio53", +}; +static const char * const nav_tsync_out_a_groups[] = { + "gpio53", +}; +static const char * const nav_ptp_pps_in_a_groups[] = { + "gpio53", +}; +static const char * const ptp_pps_out_a_groups[] = { + "gpio53", +}; +static const char * const gsm0_tx_groups[] = { + "gpio55", +}; +static const char * const qdss_cti_trig_in_b1_groups[] = { + "gpio56", +}; +static const char * const cri_trng1_groups[] = { + "gpio57", +}; +static const char * const qdss_cti_trig_out_b1_groups[] = { + "gpio57", +}; +static const char * const ssbi1_groups[] = { + "gpio58", +}; +static const char * const atest_gpsadc_dtest1_native_groups[] = { + "gpio58", +}; +static const char * const ssbi2_groups[] = { + "gpio59", +}; +static const char * const atest_char3_groups[] = { + "gpio60", +}; +static const char * const atest_char2_groups[] = { + "gpio61", +}; +static const char * const atest_char1_groups[] = { + "gpio62", +}; +static const char * const atest_char0_groups[] = { + "gpio63", +}; +static const char * const atest_char_groups[] = { + "gpio64", +}; +static const char * const ebi0_wrcdc_groups[] = { + "gpio70", +}; +static const char * const ldo_update_groups[] = { + "gpio72", +}; +static const char * const gcc_tlmm_groups[] = { + "gpio72", +}; +static const char * const ldo_en_groups[] = { + "gpio73", +}; +static const char * const dbg_out_groups[] = { + "gpio73", +}; +static const char * const atest_tsens_groups[] = { + "gpio73", +}; +static const char * const lcd_rst_groups[] = { + "gpio74", +}; +static const char * const wlan_en1_groups[] = { + "gpio75", +}; +static const char * const nav_tsync_out_b_groups[] = { + "gpio75", +}; +static const char * const nav_ptp_pps_in_b_groups[] = { + "gpio75", +}; +static const char * const ptp_pps_out_b_groups[] = { + "gpio75", +}; +static const char * const pbs0_groups[] = { + "gpio76", +}; +static const char * const sec_mi2s_groups[] = { + "gpio76", "gpio77", "gpio78", "gpio79", +}; +static const char * const pwr_modem_enabled_a_groups[] = { + "gpio76", +}; +static const char * const pbs1_groups[] = { + "gpio77", +}; +static const char * const pwr_modem_enabled_b_groups[] = { + "gpio77", +}; +static const char * const pbs2_groups[] = { + "gpio78", +}; +static const char * const pwr_nav_enabled_b_groups[] = { + "gpio78", +}; +static const char * const pwr_crypto_enabled_b_groups[] = { + "gpio79", +}; + +static const struct pinfunction mdm9607_functions[] = { + MSM_PIN_FUNCTION(adsp_ext), + MSM_PIN_FUNCTION(atest_bbrx0), + MSM_PIN_FUNCTION(atest_bbrx1), + MSM_PIN_FUNCTION(atest_char), + MSM_PIN_FUNCTION(atest_char0), + MSM_PIN_FUNCTION(atest_char1), + MSM_PIN_FUNCTION(atest_char2), + MSM_PIN_FUNCTION(atest_char3), + MSM_PIN_FUNCTION(atest_combodac_to_gpio_native), + MSM_PIN_FUNCTION(atest_gpsadc_dtest0_native), + MSM_PIN_FUNCTION(atest_gpsadc_dtest1_native), + MSM_PIN_FUNCTION(atest_tsens), + MSM_PIN_FUNCTION(backlight_en_b), + MSM_PIN_FUNCTION(bimc_dte0), + MSM_PIN_FUNCTION(bimc_dte1), + MSM_PIN_FUNCTION(blsp1_spi), + MSM_PIN_FUNCTION(blsp2_spi), + MSM_PIN_FUNCTION(blsp3_spi), + MSM_PIN_FUNCTION(blsp_i2c1), + MSM_PIN_FUNCTION(blsp_i2c2), + MSM_PIN_FUNCTION(blsp_i2c3), + MSM_PIN_FUNCTION(blsp_i2c4), + MSM_PIN_FUNCTION(blsp_i2c5), + MSM_PIN_FUNCTION(blsp_i2c6), + MSM_PIN_FUNCTION(blsp_spi1), + MSM_PIN_FUNCTION(blsp_spi2), + MSM_PIN_FUNCTION(blsp_spi3), + MSM_PIN_FUNCTION(blsp_spi4), + MSM_PIN_FUNCTION(blsp_spi5), + MSM_PIN_FUNCTION(blsp_spi6), + MSM_PIN_FUNCTION(blsp_uart1), + MSM_PIN_FUNCTION(blsp_uart2), + MSM_PIN_FUNCTION(blsp_uart3), + MSM_PIN_FUNCTION(blsp_uart4), + MSM_PIN_FUNCTION(blsp_uart5), + MSM_PIN_FUNCTION(blsp_uart6), + MSM_PIN_FUNCTION(blsp_uim1), + MSM_PIN_FUNCTION(blsp_uim2), + MSM_PIN_FUNCTION(codec_int), + MSM_PIN_FUNCTION(codec_rst), + MSM_PIN_FUNCTION(coex_uart), + MSM_PIN_FUNCTION(cri_trng), + MSM_PIN_FUNCTION(cri_trng0), + MSM_PIN_FUNCTION(cri_trng1), + MSM_PIN_FUNCTION(dbg_out), + MSM_PIN_FUNCTION(ebi0_wrcdc), + MSM_PIN_FUNCTION(ebi2_a), + MSM_PIN_FUNCTION(ebi2_a_d_8_b), + MSM_PIN_FUNCTION(ebi2_lcd), + MSM_PIN_FUNCTION(ebi2_lcd_cs_n_b), + MSM_PIN_FUNCTION(ebi2_lcd_te_b), + MSM_PIN_FUNCTION(eth_irq), + MSM_PIN_FUNCTION(eth_rst), + MSM_PIN_FUNCTION(gcc_gp1_clk_a), + MSM_PIN_FUNCTION(gcc_gp1_clk_b), + MSM_PIN_FUNCTION(gcc_gp2_clk_a), + MSM_PIN_FUNCTION(gcc_gp2_clk_b), + MSM_PIN_FUNCTION(gcc_gp3_clk_a), + MSM_PIN_FUNCTION(gcc_gp3_clk_b), + MSM_PIN_FUNCTION(gcc_plltest), + MSM_PIN_FUNCTION(gcc_tlmm), + MSM_PIN_FUNCTION(gmac_mdio), + MSM_PIN_FUNCTION(gpio), + MSM_PIN_FUNCTION(gsm0_tx), + MSM_PIN_FUNCTION(lcd_rst), + MSM_PIN_FUNCTION(ldo_en), + MSM_PIN_FUNCTION(ldo_update), + MSM_PIN_FUNCTION(m_voc), + MSM_PIN_FUNCTION(modem_tsync), + MSM_PIN_FUNCTION(nav_ptp_pps_in_a), + MSM_PIN_FUNCTION(nav_ptp_pps_in_b), + MSM_PIN_FUNCTION(nav_tsync_out_a), + MSM_PIN_FUNCTION(nav_tsync_out_b), + MSM_PIN_FUNCTION(pa_indicator), + MSM_PIN_FUNCTION(pbs0), + MSM_PIN_FUNCTION(pbs1), + MSM_PIN_FUNCTION(pbs2), + MSM_PIN_FUNCTION(pri_mi2s_data0_a), + MSM_PIN_FUNCTION(pri_mi2s_data1_a), + MSM_PIN_FUNCTION(pri_mi2s_mclk_a), + MSM_PIN_FUNCTION(pri_mi2s_sck_a), + MSM_PIN_FUNCTION(pri_mi2s_ws_a), + MSM_PIN_FUNCTION(prng_rosc), + MSM_PIN_FUNCTION(ptp_pps_out_a), + MSM_PIN_FUNCTION(ptp_pps_out_b), + MSM_PIN_FUNCTION(pwr_crypto_enabled_a), + MSM_PIN_FUNCTION(pwr_crypto_enabled_b), + MSM_PIN_FUNCTION(pwr_modem_enabled_a), + MSM_PIN_FUNCTION(pwr_modem_enabled_b), + MSM_PIN_FUNCTION(pwr_nav_enabled_a), + MSM_PIN_FUNCTION(pwr_nav_enabled_b), + MSM_PIN_FUNCTION(qdss_cti_trig_in_a0), + MSM_PIN_FUNCTION(qdss_cti_trig_in_a1), + MSM_PIN_FUNCTION(qdss_cti_trig_in_b0), + MSM_PIN_FUNCTION(qdss_cti_trig_in_b1), + MSM_PIN_FUNCTION(qdss_cti_trig_out_a0), + MSM_PIN_FUNCTION(qdss_cti_trig_out_a1), + MSM_PIN_FUNCTION(qdss_cti_trig_out_b0), + MSM_PIN_FUNCTION(qdss_cti_trig_out_b1), + MSM_PIN_FUNCTION(qdss_traceclk_a), + MSM_PIN_FUNCTION(qdss_traceclk_b), + MSM_PIN_FUNCTION(qdss_tracectl_a), + MSM_PIN_FUNCTION(qdss_tracectl_b), + MSM_PIN_FUNCTION(qdss_tracedata_a), + MSM_PIN_FUNCTION(qdss_tracedata_b), + MSM_PIN_FUNCTION(rcm_marker1), + MSM_PIN_FUNCTION(rcm_marker2), + MSM_PIN_FUNCTION(sd_write), + MSM_PIN_FUNCTION(sec_mi2s), + MSM_PIN_FUNCTION(sensor_en), + MSM_PIN_FUNCTION(sensor_int2), + MSM_PIN_FUNCTION(sensor_int3), + MSM_PIN_FUNCTION(sensor_rst), + MSM_PIN_FUNCTION(ssbi1), + MSM_PIN_FUNCTION(ssbi2), + MSM_PIN_FUNCTION(touch_rst), + MSM_PIN_FUNCTION(ts_int), + MSM_PIN_FUNCTION(uim1_clk), + MSM_PIN_FUNCTION(uim1_data), + MSM_PIN_FUNCTION(uim1_present), + MSM_PIN_FUNCTION(uim1_reset), + MSM_PIN_FUNCTION(uim2_clk), + MSM_PIN_FUNCTION(uim2_data), + MSM_PIN_FUNCTION(uim2_present), + MSM_PIN_FUNCTION(uim2_reset), + MSM_PIN_FUNCTION(uim_batt), + MSM_PIN_FUNCTION(wlan_en1) +}; + +static const struct msm_pingroup mdm9607_groups[] = { + PINGROUP(0, blsp_uart3, blsp_spi3, _, _, _, _, _, qdss_tracedata_a, _), + PINGROUP(1, blsp_uart3, blsp_spi3, _, _, _, _, _, qdss_tracedata_a, bimc_dte1), + PINGROUP(2, blsp_uart3, blsp_i2c3, blsp_spi3, _, _, _, _, _, qdss_traceclk_a), + PINGROUP(3, blsp_uart3, blsp_i2c3, blsp_spi3, _, _, _, _, _, _), + PINGROUP(4, blsp_spi2, blsp_uart2, blsp_uim2, _, _, _, _, qdss_tracedata_a, _), + PINGROUP(5, blsp_spi2, blsp_uart2, blsp_uim2, _, _, _, _, qdss_tracedata_a, _), + PINGROUP(6, blsp_spi2, blsp_uart2, blsp_i2c2, _, _, _, _, _, _), + PINGROUP(7, blsp_spi2, blsp_uart2, blsp_i2c2, _, _, _, _, _, _), + PINGROUP(8, blsp_spi5, blsp_uart5, ebi2_lcd, m_voc, _, _, _, _, _), + PINGROUP(9, blsp_spi5, blsp_uart5, _, _, _, _, _, _, _), + PINGROUP(10, blsp_spi5, blsp_i2c5, blsp_uart5, ebi2_a, _, _, qdss_tracedata_b, _, _), + PINGROUP(11, blsp_spi5, blsp_i2c5, blsp_uart5, blsp2_spi, ebi2_lcd, _, _, _, _), + PINGROUP(12, blsp_spi1, blsp_uart1, blsp_uim1, blsp3_spi, gcc_gp2_clk_b, _, _, _, _), + PINGROUP(13, blsp_spi1, blsp_uart1, blsp_uim1, blsp2_spi, gcc_gp3_clk_b, _, _, _, _), + PINGROUP(14, blsp_spi1, blsp_uart1, blsp_i2c1, gcc_gp1_clk_b, _, _, _, _, _), + PINGROUP(15, blsp_spi1, blsp_uart1, blsp_i2c1, _, _, _, _, _, _), + PINGROUP(16, blsp_spi4, blsp_uart4, _, _, _, _, _, _, _), + PINGROUP(17, blsp_spi4, blsp_uart4, _, _, _, _, _, _, _), + PINGROUP(18, blsp_spi4, blsp_uart4, blsp_i2c4, _, _, _, _, _, _), + PINGROUP(19, blsp_spi4, blsp_uart4, blsp_i2c4, _, _, _, _, _, _), + PINGROUP(20, blsp_spi6, blsp_uart6, pri_mi2s_ws_a, ebi2_lcd_te_b, blsp1_spi, _, _, _, + qdss_tracedata_a), + PINGROUP(21, blsp_spi6, blsp_uart6, pri_mi2s_data0_a, blsp1_spi, _, _, _, _, _), + PINGROUP(22, blsp_spi6, blsp_uart6, pri_mi2s_data1_a, blsp_i2c6, ebi2_a_d_8_b, _, _, _, _), + PINGROUP(23, blsp_spi6, blsp_uart6, pri_mi2s_sck_a, blsp_i2c6, ebi2_lcd_cs_n_b, _, _, _, _), + PINGROUP(24, pri_mi2s_mclk_a, _, pwr_nav_enabled_a, _, _, _, _, qdss_tracedata_a, + bimc_dte1), + PINGROUP(25, sd_write, _, pwr_crypto_enabled_a, _, _, _, _, qdss_tracedata_a, _), + PINGROUP(26, blsp3_spi, adsp_ext, _, qdss_tracedata_a, _, atest_combodac_to_gpio_native, _, + _, _), + PINGROUP(27, uim2_data, gmac_mdio, gcc_gp1_clk_a, _, _, atest_combodac_to_gpio_native, _, _, + _), + PINGROUP(28, uim2_clk, gmac_mdio, gcc_gp2_clk_a, _, _, atest_combodac_to_gpio_native, _, _, + _), + PINGROUP(29, uim2_reset, gcc_gp3_clk_a, _, _, atest_combodac_to_gpio_native, _, _, _, _), + PINGROUP(30, uim2_present, prng_rosc, _, _, atest_combodac_to_gpio_native, _, _, _, _), + PINGROUP(31, uim1_data, _, _, atest_combodac_to_gpio_native, _, _, _, _, _), + PINGROUP(32, uim1_clk, _, _, atest_combodac_to_gpio_native, _, _, _, _, _), + PINGROUP(33, uim1_reset, _, _, atest_combodac_to_gpio_native, _, _, _, _, _), + PINGROUP(34, uim1_present, gcc_plltest, _, _, atest_combodac_to_gpio_native, _, _, _, _), + PINGROUP(35, uim_batt, gcc_plltest, _, atest_combodac_to_gpio_native, _, _, _, _, _), + PINGROUP(36, coex_uart, _, _, _, _, _, _, _, _), + PINGROUP(37, coex_uart, _, _, _, _, _, _, _, _), + PINGROUP(38, _, _, _, qdss_cti_trig_in_a0, _, _, _, _, _), + PINGROUP(39, _, _, _, qdss_tracedata_b, _, atest_bbrx1, _, _, _), + PINGROUP(40, _, cri_trng0, _, _, _, _, qdss_tracedata_b, _, atest_bbrx0), + PINGROUP(41, _, _, _, _, _, qdss_tracedata_b, _, atest_combodac_to_gpio_native, _), + PINGROUP(42, _, cri_trng, _, _, qdss_tracedata_b, _, _, _, _), + PINGROUP(43, _, _, _, _, qdss_tracedata_b, _, _, _, _), + PINGROUP(44, _, _, qdss_cti_trig_in_b0, _, atest_gpsadc_dtest0_native, _, _, _, _), + PINGROUP(45, _, _, qdss_cti_trig_out_b0, _, atest_combodac_to_gpio_native, _, _, _, _), + PINGROUP(46, _, _, qdss_tracedata_b, _, _, _, _, _, _), + PINGROUP(47, _, _, qdss_tracedata_b, _, _, _, _, _, _), + PINGROUP(48, _, _, qdss_tracedata_b, _, _, _, _, _, _), + PINGROUP(49, _, _, qdss_tracectl_b, _, atest_combodac_to_gpio_native, _, _, _, _), + PINGROUP(50, _, _, qdss_traceclk_b, _, atest_combodac_to_gpio_native, _, _, _, _), + PINGROUP(51, _, pa_indicator, _, qdss_tracedata_b, _, atest_combodac_to_gpio_native, _, _, + _), + PINGROUP(52, _, _, _, qdss_tracedata_b, _, atest_combodac_to_gpio_native, _, _, _), + PINGROUP(53, _, modem_tsync, nav_tsync_out_a, nav_ptp_pps_in_a, ptp_pps_out_a, + qdss_tracedata_b, _, _, _), + PINGROUP(54, _, qdss_tracedata_b, _, atest_combodac_to_gpio_native, _, _, _, _, _), + PINGROUP(55, gsm0_tx, _, qdss_tracedata_b, _, atest_combodac_to_gpio_native, _, _, _, _), + PINGROUP(56, _, _, qdss_cti_trig_in_b1, _, _, _, _, _, _), + PINGROUP(57, _, cri_trng1, _, qdss_cti_trig_out_b1, _, atest_combodac_to_gpio_native, _, _, + _), + PINGROUP(58, _, ssbi1, _, qdss_tracedata_b, _, atest_gpsadc_dtest1_native, _, _, _), + PINGROUP(59, _, ssbi2, _, qdss_tracedata_b, _, atest_combodac_to_gpio_native, _, _, _), + PINGROUP(60, atest_char3, _, _, _, _, _, _, _, _), + PINGROUP(61, atest_char2, _, _, _, _, _, _, _, _), + PINGROUP(62, atest_char1, _, _, _, _, _, _, _, _), + PINGROUP(63, atest_char0, _, _, _, _, _, _, _, _), + PINGROUP(64, atest_char, _, _, _, _, _, _, _, _), + PINGROUP(65, _, _, _, _, _, _, _, _, _), + PINGROUP(66, _, _, _, _, _, _, _, _, _), + PINGROUP(67, _, _, _, _, _, _, _, _, _), + PINGROUP(68, _, _, _, _, _, _, _, _, _), + PINGROUP(69, _, _, _, _, _, _, _, _, _), + PINGROUP(70, _, _, ebi0_wrcdc, _, _, _, _, _, _), + PINGROUP(71, _, _, _, _, _, _, _, _, _), + PINGROUP(72, ldo_update, _, gcc_tlmm, _, _, _, _, _, _), + PINGROUP(73, ldo_en, dbg_out, _, _, _, atest_tsens, _, _, _), + PINGROUP(74, ebi2_lcd, _, _, _, _, _, _, _, _), + PINGROUP(75, nav_tsync_out_b, nav_ptp_pps_in_b, ptp_pps_out_b, _, qdss_tracedata_a, _, _, _, + _), + PINGROUP(76, pbs0, sec_mi2s, blsp3_spi, pwr_modem_enabled_a, _, qdss_tracedata_a, _, _, _), + PINGROUP(77, pbs1, sec_mi2s, blsp2_spi, pwr_modem_enabled_b, _, qdss_tracedata_a, _, _, _), + PINGROUP(78, pbs2, sec_mi2s, blsp1_spi, ebi2_lcd, m_voc, pwr_nav_enabled_b, _, + qdss_tracedata_a, _), + PINGROUP(79, sec_mi2s, _, pwr_crypto_enabled_b, _, qdss_tracedata_a, _, _, _, _), + SDC_PINGROUP(sdc1_clk, 0x10a000, 13, 6), + SDC_PINGROUP(sdc1_cmd, 0x10a000, 11, 3), + SDC_PINGROUP(sdc1_data, 0x10a000, 9, 0), + SDC_PINGROUP(sdc2_clk, 0x109000, 14, 6), + SDC_PINGROUP(sdc2_cmd, 0x109000, 11, 3), + SDC_PINGROUP(sdc2_data, 0x109000, 9, 0), + SDC_PINGROUP(qdsd_clk, 0x19c000, 3, 0), + SDC_PINGROUP(qdsd_cmd, 0x19c000, 8, 5), + SDC_PINGROUP(qdsd_data0, 0x19c000, 13, 10), + SDC_PINGROUP(qdsd_data1, 0x19c000, 18, 15), + SDC_PINGROUP(qdsd_data2, 0x19c000, 23, 20), + SDC_PINGROUP(qdsd_data3, 0x19c000, 28, 25), +}; + +static const struct msm_pinctrl_soc_data mdm9607_pinctrl = { + .pins = mdm9607_pins, + .npins = ARRAY_SIZE(mdm9607_pins), + .functions = mdm9607_functions, + .nfunctions = ARRAY_SIZE(mdm9607_functions), + .groups = mdm9607_groups, + .ngroups = ARRAY_SIZE(mdm9607_groups), + .ngpios = 80, +}; + +static int mdm9607_pinctrl_probe(struct platform_device *pdev) +{ + return msm_pinctrl_probe(pdev, &mdm9607_pinctrl); +} + +static const struct of_device_id mdm9607_pinctrl_of_match[] = { + { .compatible = "qcom,mdm9607-tlmm", }, + { } +}; + +static struct platform_driver mdm9607_pinctrl_driver = { + .driver = { + .name = "mdm9607-pinctrl", + .of_match_table = mdm9607_pinctrl_of_match, + }, + .probe = mdm9607_pinctrl_probe, + .remove = msm_pinctrl_remove, +}; + +static int __init mdm9607_pinctrl_init(void) +{ + return platform_driver_register(&mdm9607_pinctrl_driver); +} +arch_initcall(mdm9607_pinctrl_init); + +static void __exit mdm9607_pinctrl_exit(void) +{ + platform_driver_unregister(&mdm9607_pinctrl_driver); +} +module_exit(mdm9607_pinctrl_exit); + +MODULE_DESCRIPTION("Qualcomm mdm9607 pinctrl driver"); +MODULE_LICENSE("GPL v2"); +MODULE_DEVICE_TABLE(of, mdm9607_pinctrl_of_match); diff --git a/drivers/pinctrl/qcom/pinctrl-mdm9615.c b/drivers/pinctrl/qcom/pinctrl-mdm9615.c new file mode 100644 index 0000000000..0a2ae383d3 --- /dev/null +++ b/drivers/pinctrl/qcom/pinctrl-mdm9615.c @@ -0,0 +1,467 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2014, Sony Mobile Communications AB. + * Copyright (c) 2016 BayLibre, SAS. + * Author : Neil Armstrong <narmstrong@baylibre.com> + */ + +#include <linux/module.h> +#include <linux/of.h> +#include <linux/platform_device.h> +#include <linux/pinctrl/pinmux.h> + +#include "pinctrl-msm.h" + +static const struct pinctrl_pin_desc mdm9615_pins[] = { + PINCTRL_PIN(0, "GPIO_0"), + PINCTRL_PIN(1, "GPIO_1"), + PINCTRL_PIN(2, "GPIO_2"), + PINCTRL_PIN(3, "GPIO_3"), + PINCTRL_PIN(4, "GPIO_4"), + PINCTRL_PIN(5, "GPIO_5"), + PINCTRL_PIN(6, "GPIO_6"), + PINCTRL_PIN(7, "GPIO_7"), + PINCTRL_PIN(8, "GPIO_8"), + PINCTRL_PIN(9, "GPIO_9"), + PINCTRL_PIN(10, "GPIO_10"), + PINCTRL_PIN(11, "GPIO_11"), + PINCTRL_PIN(12, "GPIO_12"), + PINCTRL_PIN(13, "GPIO_13"), + PINCTRL_PIN(14, "GPIO_14"), + PINCTRL_PIN(15, "GPIO_15"), + PINCTRL_PIN(16, "GPIO_16"), + PINCTRL_PIN(17, "GPIO_17"), + PINCTRL_PIN(18, "GPIO_18"), + PINCTRL_PIN(19, "GPIO_19"), + PINCTRL_PIN(20, "GPIO_20"), + PINCTRL_PIN(21, "GPIO_21"), + PINCTRL_PIN(22, "GPIO_22"), + PINCTRL_PIN(23, "GPIO_23"), + PINCTRL_PIN(24, "GPIO_24"), + PINCTRL_PIN(25, "GPIO_25"), + PINCTRL_PIN(26, "GPIO_26"), + PINCTRL_PIN(27, "GPIO_27"), + PINCTRL_PIN(28, "GPIO_28"), + PINCTRL_PIN(29, "GPIO_29"), + PINCTRL_PIN(30, "GPIO_30"), + PINCTRL_PIN(31, "GPIO_31"), + PINCTRL_PIN(32, "GPIO_32"), + PINCTRL_PIN(33, "GPIO_33"), + PINCTRL_PIN(34, "GPIO_34"), + PINCTRL_PIN(35, "GPIO_35"), + PINCTRL_PIN(36, "GPIO_36"), + PINCTRL_PIN(37, "GPIO_37"), + PINCTRL_PIN(38, "GPIO_38"), + PINCTRL_PIN(39, "GPIO_39"), + PINCTRL_PIN(40, "GPIO_40"), + PINCTRL_PIN(41, "GPIO_41"), + PINCTRL_PIN(42, "GPIO_42"), + PINCTRL_PIN(43, "GPIO_43"), + PINCTRL_PIN(44, "GPIO_44"), + PINCTRL_PIN(45, "GPIO_45"), + PINCTRL_PIN(46, "GPIO_46"), + PINCTRL_PIN(47, "GPIO_47"), + PINCTRL_PIN(48, "GPIO_48"), + PINCTRL_PIN(49, "GPIO_49"), + PINCTRL_PIN(50, "GPIO_50"), + PINCTRL_PIN(51, "GPIO_51"), + PINCTRL_PIN(52, "GPIO_52"), + PINCTRL_PIN(53, "GPIO_53"), + PINCTRL_PIN(54, "GPIO_54"), + PINCTRL_PIN(55, "GPIO_55"), + PINCTRL_PIN(56, "GPIO_56"), + PINCTRL_PIN(57, "GPIO_57"), + PINCTRL_PIN(58, "GPIO_58"), + PINCTRL_PIN(59, "GPIO_59"), + PINCTRL_PIN(60, "GPIO_60"), + PINCTRL_PIN(61, "GPIO_61"), + PINCTRL_PIN(62, "GPIO_62"), + PINCTRL_PIN(63, "GPIO_63"), + PINCTRL_PIN(64, "GPIO_64"), + PINCTRL_PIN(65, "GPIO_65"), + PINCTRL_PIN(66, "GPIO_66"), + PINCTRL_PIN(67, "GPIO_67"), + PINCTRL_PIN(68, "GPIO_68"), + PINCTRL_PIN(69, "GPIO_69"), + PINCTRL_PIN(70, "GPIO_70"), + PINCTRL_PIN(71, "GPIO_71"), + PINCTRL_PIN(72, "GPIO_72"), + PINCTRL_PIN(73, "GPIO_73"), + PINCTRL_PIN(74, "GPIO_74"), + PINCTRL_PIN(75, "GPIO_75"), + PINCTRL_PIN(76, "GPIO_76"), + PINCTRL_PIN(77, "GPIO_77"), + PINCTRL_PIN(78, "GPIO_78"), + PINCTRL_PIN(79, "GPIO_79"), + PINCTRL_PIN(80, "GPIO_80"), + PINCTRL_PIN(81, "GPIO_81"), + PINCTRL_PIN(82, "GPIO_82"), + PINCTRL_PIN(83, "GPIO_83"), + PINCTRL_PIN(84, "GPIO_84"), + PINCTRL_PIN(85, "GPIO_85"), + PINCTRL_PIN(86, "GPIO_86"), + PINCTRL_PIN(87, "GPIO_87"), +}; + +#define DECLARE_MSM_GPIO_PINS(pin) \ + static const unsigned int gpio##pin##_pins[] = { pin } +DECLARE_MSM_GPIO_PINS(0); +DECLARE_MSM_GPIO_PINS(1); +DECLARE_MSM_GPIO_PINS(2); +DECLARE_MSM_GPIO_PINS(3); +DECLARE_MSM_GPIO_PINS(4); +DECLARE_MSM_GPIO_PINS(5); +DECLARE_MSM_GPIO_PINS(6); +DECLARE_MSM_GPIO_PINS(7); +DECLARE_MSM_GPIO_PINS(8); +DECLARE_MSM_GPIO_PINS(9); +DECLARE_MSM_GPIO_PINS(10); +DECLARE_MSM_GPIO_PINS(11); +DECLARE_MSM_GPIO_PINS(12); +DECLARE_MSM_GPIO_PINS(13); +DECLARE_MSM_GPIO_PINS(14); +DECLARE_MSM_GPIO_PINS(15); +DECLARE_MSM_GPIO_PINS(16); +DECLARE_MSM_GPIO_PINS(17); +DECLARE_MSM_GPIO_PINS(18); +DECLARE_MSM_GPIO_PINS(19); +DECLARE_MSM_GPIO_PINS(20); +DECLARE_MSM_GPIO_PINS(21); +DECLARE_MSM_GPIO_PINS(22); +DECLARE_MSM_GPIO_PINS(23); +DECLARE_MSM_GPIO_PINS(24); +DECLARE_MSM_GPIO_PINS(25); +DECLARE_MSM_GPIO_PINS(26); +DECLARE_MSM_GPIO_PINS(27); +DECLARE_MSM_GPIO_PINS(28); +DECLARE_MSM_GPIO_PINS(29); +DECLARE_MSM_GPIO_PINS(30); +DECLARE_MSM_GPIO_PINS(31); +DECLARE_MSM_GPIO_PINS(32); +DECLARE_MSM_GPIO_PINS(33); +DECLARE_MSM_GPIO_PINS(34); +DECLARE_MSM_GPIO_PINS(35); +DECLARE_MSM_GPIO_PINS(36); +DECLARE_MSM_GPIO_PINS(37); +DECLARE_MSM_GPIO_PINS(38); +DECLARE_MSM_GPIO_PINS(39); +DECLARE_MSM_GPIO_PINS(40); +DECLARE_MSM_GPIO_PINS(41); +DECLARE_MSM_GPIO_PINS(42); +DECLARE_MSM_GPIO_PINS(43); +DECLARE_MSM_GPIO_PINS(44); +DECLARE_MSM_GPIO_PINS(45); +DECLARE_MSM_GPIO_PINS(46); +DECLARE_MSM_GPIO_PINS(47); +DECLARE_MSM_GPIO_PINS(48); +DECLARE_MSM_GPIO_PINS(49); +DECLARE_MSM_GPIO_PINS(50); +DECLARE_MSM_GPIO_PINS(51); +DECLARE_MSM_GPIO_PINS(52); +DECLARE_MSM_GPIO_PINS(53); +DECLARE_MSM_GPIO_PINS(54); +DECLARE_MSM_GPIO_PINS(55); +DECLARE_MSM_GPIO_PINS(56); +DECLARE_MSM_GPIO_PINS(57); +DECLARE_MSM_GPIO_PINS(58); +DECLARE_MSM_GPIO_PINS(59); +DECLARE_MSM_GPIO_PINS(60); +DECLARE_MSM_GPIO_PINS(61); +DECLARE_MSM_GPIO_PINS(62); +DECLARE_MSM_GPIO_PINS(63); +DECLARE_MSM_GPIO_PINS(64); +DECLARE_MSM_GPIO_PINS(65); +DECLARE_MSM_GPIO_PINS(66); +DECLARE_MSM_GPIO_PINS(67); +DECLARE_MSM_GPIO_PINS(68); +DECLARE_MSM_GPIO_PINS(69); +DECLARE_MSM_GPIO_PINS(70); +DECLARE_MSM_GPIO_PINS(71); +DECLARE_MSM_GPIO_PINS(72); +DECLARE_MSM_GPIO_PINS(73); +DECLARE_MSM_GPIO_PINS(74); +DECLARE_MSM_GPIO_PINS(75); +DECLARE_MSM_GPIO_PINS(76); +DECLARE_MSM_GPIO_PINS(77); +DECLARE_MSM_GPIO_PINS(78); +DECLARE_MSM_GPIO_PINS(79); +DECLARE_MSM_GPIO_PINS(80); +DECLARE_MSM_GPIO_PINS(81); +DECLARE_MSM_GPIO_PINS(82); +DECLARE_MSM_GPIO_PINS(83); +DECLARE_MSM_GPIO_PINS(84); +DECLARE_MSM_GPIO_PINS(85); +DECLARE_MSM_GPIO_PINS(86); +DECLARE_MSM_GPIO_PINS(87); + +#define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7, f8, f9, f10, f11) \ + { \ + .grp = PINCTRL_PINGROUP("gpio" #id, \ + gpio##id##_pins, \ + ARRAY_SIZE(gpio##id##_pins)), \ + .funcs = (int[]){ \ + msm_mux_gpio, \ + msm_mux_##f1, \ + msm_mux_##f2, \ + msm_mux_##f3, \ + msm_mux_##f4, \ + msm_mux_##f5, \ + msm_mux_##f6, \ + msm_mux_##f7, \ + msm_mux_##f8, \ + msm_mux_##f9, \ + msm_mux_##f10, \ + msm_mux_##f11 \ + }, \ + .nfuncs = 12, \ + .ctl_reg = 0x1000 + 0x10 * id, \ + .io_reg = 0x1004 + 0x10 * id, \ + .intr_cfg_reg = 0x1008 + 0x10 * id, \ + .intr_status_reg = 0x100c + 0x10 * id, \ + .intr_target_reg = 0x400 + 0x4 * id, \ + .mux_bit = 2, \ + .pull_bit = 0, \ + .drv_bit = 6, \ + .oe_bit = 9, \ + .in_bit = 0, \ + .out_bit = 1, \ + .intr_enable_bit = 0, \ + .intr_status_bit = 0, \ + .intr_ack_high = 1, \ + .intr_target_bit = 0, \ + .intr_target_kpss_val = 4, \ + .intr_raw_status_bit = 3, \ + .intr_polarity_bit = 1, \ + .intr_detection_bit = 2, \ + .intr_detection_width = 1, \ + } + +enum mdm9615_functions { + msm_mux_gpio, + msm_mux_gsbi2_i2c, + msm_mux_gsbi3, + msm_mux_gsbi4, + msm_mux_gsbi5_i2c, + msm_mux_gsbi5_uart, + msm_mux_sdc2, + msm_mux_ebi2_lcdc, + msm_mux_ps_hold, + msm_mux_prim_audio, + msm_mux_sec_audio, + msm_mux_cdc_mclk, + msm_mux_NA, +}; + +static const char * const gpio_groups[] = { + "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7", + "gpio8", "gpio9", "gpio10", "gpio11", "gpio12", "gpio13", "gpio14", + "gpio15", "gpio16", "gpio17", "gpio18", "gpio19", "gpio20", "gpio21", + "gpio22", "gpio23", "gpio24", "gpio25", "gpio26", "gpio27", "gpio28", + "gpio29", "gpio30", "gpio31", "gpio32", "gpio33", "gpio34", "gpio35", + "gpio36", "gpio37", "gpio38", "gpio39", "gpio40", "gpio41", "gpio42", + "gpio43", "gpio44", "gpio45", "gpio46", "gpio47", "gpio48", "gpio49", + "gpio50", "gpio51", "gpio52", "gpio53", "gpio54", "gpio55", "gpio56", + "gpio57", "gpio58", "gpio59", "gpio60", "gpio61", "gpio62", "gpio63", + "gpio64", "gpio65", "gpio66", "gpio67", "gpio68", "gpio69", "gpio70", + "gpio71", "gpio72", "gpio73", "gpio74", "gpio75", "gpio76", "gpio77", + "gpio78", "gpio79", "gpio80", "gpio81", "gpio82", "gpio83", "gpio84", + "gpio85", "gpio86", "gpio87" +}; + +static const char * const gsbi2_i2c_groups[] = { + "gpio4", "gpio5" +}; + +static const char * const gsbi3_groups[] = { + "gpio8", "gpio9", "gpio10", "gpio11" +}; + +static const char * const gsbi4_groups[] = { + "gpio12", "gpio13", "gpio14", "gpio15" +}; + +static const char * const gsbi5_i2c_groups[] = { + "gpio16", "gpio17" +}; + +static const char * const gsbi5_uart_groups[] = { + "gpio18", "gpio19" +}; + +static const char * const sdc2_groups[] = { + "gpio25", "gpio26", "gpio27", "gpio28", "gpio29", "gpio30", +}; + +static const char * const ebi2_lcdc_groups[] = { + "gpio21", "gpio22", "gpio24", +}; + +static const char * const ps_hold_groups[] = { + "gpio83", +}; + +static const char * const prim_audio_groups[] = { + "gpio20", "gpio21", "gpio22", "gpio23", +}; + +static const char * const sec_audio_groups[] = { + "gpio25", "gpio26", "gpio27", "gpio28", +}; + +static const char * const cdc_mclk_groups[] = { + "gpio24", +}; + +static const struct pinfunction mdm9615_functions[] = { + MSM_PIN_FUNCTION(gpio), + MSM_PIN_FUNCTION(gsbi2_i2c), + MSM_PIN_FUNCTION(gsbi3), + MSM_PIN_FUNCTION(gsbi4), + MSM_PIN_FUNCTION(gsbi5_i2c), + MSM_PIN_FUNCTION(gsbi5_uart), + MSM_PIN_FUNCTION(sdc2), + MSM_PIN_FUNCTION(ebi2_lcdc), + MSM_PIN_FUNCTION(ps_hold), + MSM_PIN_FUNCTION(prim_audio), + MSM_PIN_FUNCTION(sec_audio), + MSM_PIN_FUNCTION(cdc_mclk), +}; + +static const struct msm_pingroup mdm9615_groups[] = { + PINGROUP(0, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(1, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(2, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(3, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(4, gsbi2_i2c, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(5, gsbi2_i2c, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(6, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(7, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(8, gsbi3, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(9, gsbi3, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(10, gsbi3, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(11, gsbi3, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(12, gsbi4, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(13, gsbi4, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(14, gsbi4, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(15, gsbi4, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(16, gsbi5_i2c, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(17, gsbi5_i2c, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(18, gsbi5_uart, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(19, gsbi5_uart, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(20, prim_audio, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(21, prim_audio, ebi2_lcdc, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(22, prim_audio, ebi2_lcdc, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(23, prim_audio, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(24, cdc_mclk, NA, ebi2_lcdc, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(25, sdc2, sec_audio, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(26, sdc2, sec_audio, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(27, sdc2, sec_audio, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(28, sdc2, sec_audio, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(29, sdc2, sec_audio, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(30, sdc2, sec_audio, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(31, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(32, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(33, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(34, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(35, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(36, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(37, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(38, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(39, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(40, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(41, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(42, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(43, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(44, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(45, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(46, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(47, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(48, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(49, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(50, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(51, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(52, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(53, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(54, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(55, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(56, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(57, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(58, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(59, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(60, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(61, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(62, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(63, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(64, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(65, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(66, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(67, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(68, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(69, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(70, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(71, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(72, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(73, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(74, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(75, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(76, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(77, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(78, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(79, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(80, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(81, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(82, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(83, ps_hold, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(84, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(85, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(86, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(87, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), +}; + +#define NUM_GPIO_PINGROUPS 88 + +static const struct msm_pinctrl_soc_data mdm9615_pinctrl = { + .pins = mdm9615_pins, + .npins = ARRAY_SIZE(mdm9615_pins), + .functions = mdm9615_functions, + .nfunctions = ARRAY_SIZE(mdm9615_functions), + .groups = mdm9615_groups, + .ngroups = ARRAY_SIZE(mdm9615_groups), + .ngpios = NUM_GPIO_PINGROUPS, +}; + +static int mdm9615_pinctrl_probe(struct platform_device *pdev) +{ + return msm_pinctrl_probe(pdev, &mdm9615_pinctrl); +} + +static const struct of_device_id mdm9615_pinctrl_of_match[] = { + { .compatible = "qcom,mdm9615-pinctrl", }, + { }, +}; + +static struct platform_driver mdm9615_pinctrl_driver = { + .driver = { + .name = "mdm9615-pinctrl", + .of_match_table = mdm9615_pinctrl_of_match, + }, + .probe = mdm9615_pinctrl_probe, + .remove = msm_pinctrl_remove, +}; + +static int __init mdm9615_pinctrl_init(void) +{ + return platform_driver_register(&mdm9615_pinctrl_driver); +} +arch_initcall(mdm9615_pinctrl_init); + +static void __exit mdm9615_pinctrl_exit(void) +{ + platform_driver_unregister(&mdm9615_pinctrl_driver); +} +module_exit(mdm9615_pinctrl_exit); + +MODULE_AUTHOR("Neil Armstrong <narmstrong@baylibre.com>"); +MODULE_DESCRIPTION("Qualcomm MDM9615 pinctrl driver"); +MODULE_LICENSE("GPL v2"); +MODULE_DEVICE_TABLE(of, mdm9615_pinctrl_of_match); diff --git a/drivers/pinctrl/qcom/pinctrl-msm.c b/drivers/pinctrl/qcom/pinctrl-msm.c new file mode 100644 index 0000000000..115b83e2d8 --- /dev/null +++ b/drivers/pinctrl/qcom/pinctrl-msm.c @@ -0,0 +1,1563 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2013, Sony Mobile Communications AB. + * Copyright (c) 2013, The Linux Foundation. All rights reserved. + */ + +#include <linux/delay.h> +#include <linux/err.h> +#include <linux/gpio/driver.h> +#include <linux/interrupt.h> +#include <linux/io.h> +#include <linux/log2.h> +#include <linux/module.h> +#include <linux/of.h> +#include <linux/platform_device.h> +#include <linux/pm.h> +#include <linux/firmware/qcom/qcom_scm.h> +#include <linux/reboot.h> +#include <linux/seq_file.h> +#include <linux/slab.h> +#include <linux/spinlock.h> + +#include <linux/pinctrl/machine.h> +#include <linux/pinctrl/pinconf-generic.h> +#include <linux/pinctrl/pinconf.h> +#include <linux/pinctrl/pinmux.h> + +#include <linux/soc/qcom/irq.h> + +#include "../core.h" +#include "../pinconf.h" +#include "../pinctrl-utils.h" + +#include "pinctrl-msm.h" + +#define MAX_NR_GPIO 300 +#define MAX_NR_TILES 4 +#define PS_HOLD_OFFSET 0x820 + +/** + * struct msm_pinctrl - state for a pinctrl-msm device + * @dev: device handle. + * @pctrl: pinctrl handle. + * @chip: gpiochip handle. + * @desc: pin controller descriptor + * @restart_nb: restart notifier block. + * @irq: parent irq for the TLMM irq_chip. + * @intr_target_use_scm: route irq to application cpu using scm calls + * @lock: Spinlock to protect register resources as well + * as msm_pinctrl data structures. + * @enabled_irqs: Bitmap of currently enabled irqs. + * @dual_edge_irqs: Bitmap of irqs that need sw emulated dual edge + * detection. + * @skip_wake_irqs: Skip IRQs that are handled by wakeup interrupt controller + * @disabled_for_mux: These IRQs were disabled because we muxed away. + * @ever_gpio: This bit is set the first time we mux a pin to gpio_func. + * @soc: Reference to soc_data of platform specific data. + * @regs: Base addresses for the TLMM tiles. + * @phys_base: Physical base address + */ +struct msm_pinctrl { + struct device *dev; + struct pinctrl_dev *pctrl; + struct gpio_chip chip; + struct pinctrl_desc desc; + struct notifier_block restart_nb; + + int irq; + + bool intr_target_use_scm; + + raw_spinlock_t lock; + + DECLARE_BITMAP(dual_edge_irqs, MAX_NR_GPIO); + DECLARE_BITMAP(enabled_irqs, MAX_NR_GPIO); + DECLARE_BITMAP(skip_wake_irqs, MAX_NR_GPIO); + DECLARE_BITMAP(disabled_for_mux, MAX_NR_GPIO); + DECLARE_BITMAP(ever_gpio, MAX_NR_GPIO); + + const struct msm_pinctrl_soc_data *soc; + void __iomem *regs[MAX_NR_TILES]; + u32 phys_base[MAX_NR_TILES]; +}; + +#define MSM_ACCESSOR(name) \ +static u32 msm_readl_##name(struct msm_pinctrl *pctrl, \ + const struct msm_pingroup *g) \ +{ \ + return readl(pctrl->regs[g->tile] + g->name##_reg); \ +} \ +static void msm_writel_##name(u32 val, struct msm_pinctrl *pctrl, \ + const struct msm_pingroup *g) \ +{ \ + writel(val, pctrl->regs[g->tile] + g->name##_reg); \ +} + +MSM_ACCESSOR(ctl) +MSM_ACCESSOR(io) +MSM_ACCESSOR(intr_cfg) +MSM_ACCESSOR(intr_status) +MSM_ACCESSOR(intr_target) + +static void msm_ack_intr_status(struct msm_pinctrl *pctrl, + const struct msm_pingroup *g) +{ + u32 val = g->intr_ack_high ? BIT(g->intr_status_bit) : 0; + + msm_writel_intr_status(val, pctrl, g); +} + +static int msm_get_groups_count(struct pinctrl_dev *pctldev) +{ + struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); + + return pctrl->soc->ngroups; +} + +static const char *msm_get_group_name(struct pinctrl_dev *pctldev, + unsigned group) +{ + struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); + + return pctrl->soc->groups[group].grp.name; +} + +static int msm_get_group_pins(struct pinctrl_dev *pctldev, + unsigned group, + const unsigned **pins, + unsigned *num_pins) +{ + struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); + + *pins = pctrl->soc->groups[group].grp.pins; + *num_pins = pctrl->soc->groups[group].grp.npins; + return 0; +} + +static const struct pinctrl_ops msm_pinctrl_ops = { + .get_groups_count = msm_get_groups_count, + .get_group_name = msm_get_group_name, + .get_group_pins = msm_get_group_pins, + .dt_node_to_map = pinconf_generic_dt_node_to_map_group, + .dt_free_map = pinctrl_utils_free_map, +}; + +static int msm_pinmux_request(struct pinctrl_dev *pctldev, unsigned offset) +{ + struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); + struct gpio_chip *chip = &pctrl->chip; + + return gpiochip_line_is_valid(chip, offset) ? 0 : -EINVAL; +} + +static int msm_get_functions_count(struct pinctrl_dev *pctldev) +{ + struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); + + return pctrl->soc->nfunctions; +} + +static const char *msm_get_function_name(struct pinctrl_dev *pctldev, + unsigned function) +{ + struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); + + return pctrl->soc->functions[function].name; +} + +static int msm_get_function_groups(struct pinctrl_dev *pctldev, + unsigned function, + const char * const **groups, + unsigned * const num_groups) +{ + struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); + + *groups = pctrl->soc->functions[function].groups; + *num_groups = pctrl->soc->functions[function].ngroups; + return 0; +} + +static int msm_pinmux_set_mux(struct pinctrl_dev *pctldev, + unsigned function, + unsigned group) +{ + struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); + struct gpio_chip *gc = &pctrl->chip; + unsigned int irq = irq_find_mapping(gc->irq.domain, group); + struct irq_data *d = irq_get_irq_data(irq); + unsigned int gpio_func = pctrl->soc->gpio_func; + unsigned int egpio_func = pctrl->soc->egpio_func; + const struct msm_pingroup *g; + unsigned long flags; + u32 val, mask; + int i; + + g = &pctrl->soc->groups[group]; + mask = GENMASK(g->mux_bit + order_base_2(g->nfuncs) - 1, g->mux_bit); + + for (i = 0; i < g->nfuncs; i++) { + if (g->funcs[i] == function) + break; + } + + if (WARN_ON(i == g->nfuncs)) + return -EINVAL; + + /* + * If an GPIO interrupt is setup on this pin then we need special + * handling. Specifically interrupt detection logic will still see + * the pin twiddle even when we're muxed away. + * + * When we see a pin with an interrupt setup on it then we'll disable + * (mask) interrupts on it when we mux away until we mux back. Note + * that disable_irq() refcounts and interrupts are disabled as long as + * at least one disable_irq() has been called. + */ + if (d && i != gpio_func && + !test_and_set_bit(d->hwirq, pctrl->disabled_for_mux)) + disable_irq(irq); + + raw_spin_lock_irqsave(&pctrl->lock, flags); + + val = msm_readl_ctl(pctrl, g); + + /* + * If this is the first time muxing to GPIO and the direction is + * output, make sure that we're not going to be glitching the pin + * by reading the current state of the pin and setting it as the + * output. + */ + if (i == gpio_func && (val & BIT(g->oe_bit)) && + !test_and_set_bit(group, pctrl->ever_gpio)) { + u32 io_val = msm_readl_io(pctrl, g); + + if (io_val & BIT(g->in_bit)) { + if (!(io_val & BIT(g->out_bit))) + msm_writel_io(io_val | BIT(g->out_bit), pctrl, g); + } else { + if (io_val & BIT(g->out_bit)) + msm_writel_io(io_val & ~BIT(g->out_bit), pctrl, g); + } + } + + if (egpio_func && i == egpio_func) { + if (val & BIT(g->egpio_present)) + val &= ~BIT(g->egpio_enable); + } else { + val &= ~mask; + val |= i << g->mux_bit; + /* Claim ownership of pin if egpio capable */ + if (egpio_func && val & BIT(g->egpio_present)) + val |= BIT(g->egpio_enable); + } + + msm_writel_ctl(val, pctrl, g); + + raw_spin_unlock_irqrestore(&pctrl->lock, flags); + + if (d && i == gpio_func && + test_and_clear_bit(d->hwirq, pctrl->disabled_for_mux)) { + /* + * Clear interrupts detected while not GPIO since we only + * masked things. + */ + if (d->parent_data && test_bit(d->hwirq, pctrl->skip_wake_irqs)) + irq_chip_set_parent_state(d, IRQCHIP_STATE_PENDING, false); + else + msm_ack_intr_status(pctrl, g); + + enable_irq(irq); + } + + return 0; +} + +static int msm_pinmux_request_gpio(struct pinctrl_dev *pctldev, + struct pinctrl_gpio_range *range, + unsigned offset) +{ + struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); + const struct msm_pingroup *g = &pctrl->soc->groups[offset]; + + /* No funcs? Probably ACPI so can't do anything here */ + if (!g->nfuncs) + return 0; + + return msm_pinmux_set_mux(pctldev, g->funcs[pctrl->soc->gpio_func], offset); +} + +static const struct pinmux_ops msm_pinmux_ops = { + .request = msm_pinmux_request, + .get_functions_count = msm_get_functions_count, + .get_function_name = msm_get_function_name, + .get_function_groups = msm_get_function_groups, + .gpio_request_enable = msm_pinmux_request_gpio, + .set_mux = msm_pinmux_set_mux, +}; + +static int msm_config_reg(struct msm_pinctrl *pctrl, + const struct msm_pingroup *g, + unsigned param, + unsigned *mask, + unsigned *bit) +{ + switch (param) { + case PIN_CONFIG_BIAS_DISABLE: + case PIN_CONFIG_BIAS_PULL_DOWN: + case PIN_CONFIG_BIAS_BUS_HOLD: + case PIN_CONFIG_BIAS_PULL_UP: + *bit = g->pull_bit; + *mask = 3; + if (g->i2c_pull_bit) + *mask |= BIT(g->i2c_pull_bit) >> *bit; + break; + case PIN_CONFIG_DRIVE_OPEN_DRAIN: + *bit = g->od_bit; + *mask = 1; + break; + case PIN_CONFIG_DRIVE_STRENGTH: + *bit = g->drv_bit; + *mask = 7; + break; + case PIN_CONFIG_OUTPUT: + case PIN_CONFIG_INPUT_ENABLE: + case PIN_CONFIG_OUTPUT_ENABLE: + *bit = g->oe_bit; + *mask = 1; + break; + default: + return -ENOTSUPP; + } + + return 0; +} + +#define MSM_NO_PULL 0 +#define MSM_PULL_DOWN 1 +#define MSM_KEEPER 2 +#define MSM_PULL_UP_NO_KEEPER 2 +#define MSM_PULL_UP 3 +#define MSM_I2C_STRONG_PULL_UP 2200 + +static unsigned msm_regval_to_drive(u32 val) +{ + return (val + 1) * 2; +} + +static int msm_config_group_get(struct pinctrl_dev *pctldev, + unsigned int group, + unsigned long *config) +{ + const struct msm_pingroup *g; + struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); + unsigned param = pinconf_to_config_param(*config); + unsigned mask; + unsigned arg; + unsigned bit; + int ret; + u32 val; + + g = &pctrl->soc->groups[group]; + + ret = msm_config_reg(pctrl, g, param, &mask, &bit); + if (ret < 0) + return ret; + + val = msm_readl_ctl(pctrl, g); + arg = (val >> bit) & mask; + + /* Convert register value to pinconf value */ + switch (param) { + case PIN_CONFIG_BIAS_DISABLE: + if (arg != MSM_NO_PULL) + return -EINVAL; + arg = 1; + break; + case PIN_CONFIG_BIAS_PULL_DOWN: + if (arg != MSM_PULL_DOWN) + return -EINVAL; + arg = 1; + break; + case PIN_CONFIG_BIAS_BUS_HOLD: + if (pctrl->soc->pull_no_keeper) + return -ENOTSUPP; + + if (arg != MSM_KEEPER) + return -EINVAL; + arg = 1; + break; + case PIN_CONFIG_BIAS_PULL_UP: + if (pctrl->soc->pull_no_keeper) + arg = arg == MSM_PULL_UP_NO_KEEPER; + else if (arg & BIT(g->i2c_pull_bit)) + arg = MSM_I2C_STRONG_PULL_UP; + else + arg = arg == MSM_PULL_UP; + if (!arg) + return -EINVAL; + break; + case PIN_CONFIG_DRIVE_OPEN_DRAIN: + /* Pin is not open-drain */ + if (!arg) + return -EINVAL; + arg = 1; + break; + case PIN_CONFIG_DRIVE_STRENGTH: + arg = msm_regval_to_drive(arg); + break; + case PIN_CONFIG_OUTPUT: + /* Pin is not output */ + if (!arg) + return -EINVAL; + + val = msm_readl_io(pctrl, g); + arg = !!(val & BIT(g->in_bit)); + break; + case PIN_CONFIG_OUTPUT_ENABLE: + if (!arg) + return -EINVAL; + break; + default: + return -ENOTSUPP; + } + + *config = pinconf_to_config_packed(param, arg); + + return 0; +} + +static int msm_config_group_set(struct pinctrl_dev *pctldev, + unsigned group, + unsigned long *configs, + unsigned num_configs) +{ + const struct msm_pingroup *g; + struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); + unsigned long flags; + unsigned param; + unsigned mask; + unsigned arg; + unsigned bit; + int ret; + u32 val; + int i; + + g = &pctrl->soc->groups[group]; + + for (i = 0; i < num_configs; i++) { + param = pinconf_to_config_param(configs[i]); + arg = pinconf_to_config_argument(configs[i]); + + ret = msm_config_reg(pctrl, g, param, &mask, &bit); + if (ret < 0) + return ret; + + /* Convert pinconf values to register values */ + switch (param) { + case PIN_CONFIG_BIAS_DISABLE: + arg = MSM_NO_PULL; + break; + case PIN_CONFIG_BIAS_PULL_DOWN: + arg = MSM_PULL_DOWN; + break; + case PIN_CONFIG_BIAS_BUS_HOLD: + if (pctrl->soc->pull_no_keeper) + return -ENOTSUPP; + + arg = MSM_KEEPER; + break; + case PIN_CONFIG_BIAS_PULL_UP: + if (pctrl->soc->pull_no_keeper) + arg = MSM_PULL_UP_NO_KEEPER; + else if (g->i2c_pull_bit && arg == MSM_I2C_STRONG_PULL_UP) + arg = BIT(g->i2c_pull_bit) | MSM_PULL_UP; + else + arg = MSM_PULL_UP; + break; + case PIN_CONFIG_DRIVE_OPEN_DRAIN: + arg = 1; + break; + case PIN_CONFIG_DRIVE_STRENGTH: + /* Check for invalid values */ + if (arg > 16 || arg < 2 || (arg % 2) != 0) + arg = -1; + else + arg = (arg / 2) - 1; + break; + case PIN_CONFIG_OUTPUT: + /* set output value */ + raw_spin_lock_irqsave(&pctrl->lock, flags); + val = msm_readl_io(pctrl, g); + if (arg) + val |= BIT(g->out_bit); + else + val &= ~BIT(g->out_bit); + msm_writel_io(val, pctrl, g); + raw_spin_unlock_irqrestore(&pctrl->lock, flags); + + /* enable output */ + arg = 1; + break; + case PIN_CONFIG_INPUT_ENABLE: + /* + * According to pinctrl documentation this should + * actually be a no-op. + * + * The docs are explicit that "this does not affect + * the pin's ability to drive output" but what we do + * here is to modify the output enable bit. Thus, to + * follow the docs we should remove that. + * + * The docs say that we should enable any relevant + * input buffer, but TLMM there is no input buffer that + * can be enabled/disabled. It's always on. + * + * The points above, explain why this _should_ be a + * no-op. However, for historical reasons and to + * support old device trees, we'll violate the docs + * and still affect the output. + * + * It should further be noted that this old historical + * behavior actually overrides arg to 0. That means + * that "input-enable" and "input-disable" in a device + * tree would _both_ disable the output. We'll + * continue to preserve this behavior as well since + * we have no other use for this attribute. + */ + arg = 0; + break; + case PIN_CONFIG_OUTPUT_ENABLE: + arg = !!arg; + break; + default: + dev_err(pctrl->dev, "Unsupported config parameter: %x\n", + param); + return -EINVAL; + } + + /* Range-check user-supplied value */ + if (arg & ~mask) { + dev_err(pctrl->dev, "config %x: %x is invalid\n", param, arg); + return -EINVAL; + } + + raw_spin_lock_irqsave(&pctrl->lock, flags); + val = msm_readl_ctl(pctrl, g); + val &= ~(mask << bit); + val |= arg << bit; + msm_writel_ctl(val, pctrl, g); + raw_spin_unlock_irqrestore(&pctrl->lock, flags); + } + + return 0; +} + +static const struct pinconf_ops msm_pinconf_ops = { + .is_generic = true, + .pin_config_group_get = msm_config_group_get, + .pin_config_group_set = msm_config_group_set, +}; + +static int msm_gpio_direction_input(struct gpio_chip *chip, unsigned offset) +{ + const struct msm_pingroup *g; + struct msm_pinctrl *pctrl = gpiochip_get_data(chip); + unsigned long flags; + u32 val; + + g = &pctrl->soc->groups[offset]; + + raw_spin_lock_irqsave(&pctrl->lock, flags); + + val = msm_readl_ctl(pctrl, g); + val &= ~BIT(g->oe_bit); + msm_writel_ctl(val, pctrl, g); + + raw_spin_unlock_irqrestore(&pctrl->lock, flags); + + return 0; +} + +static int msm_gpio_direction_output(struct gpio_chip *chip, unsigned offset, int value) +{ + const struct msm_pingroup *g; + struct msm_pinctrl *pctrl = gpiochip_get_data(chip); + unsigned long flags; + u32 val; + + g = &pctrl->soc->groups[offset]; + + raw_spin_lock_irqsave(&pctrl->lock, flags); + + val = msm_readl_io(pctrl, g); + if (value) + val |= BIT(g->out_bit); + else + val &= ~BIT(g->out_bit); + msm_writel_io(val, pctrl, g); + + val = msm_readl_ctl(pctrl, g); + val |= BIT(g->oe_bit); + msm_writel_ctl(val, pctrl, g); + + raw_spin_unlock_irqrestore(&pctrl->lock, flags); + + return 0; +} + +static int msm_gpio_get_direction(struct gpio_chip *chip, unsigned int offset) +{ + struct msm_pinctrl *pctrl = gpiochip_get_data(chip); + const struct msm_pingroup *g; + u32 val; + + g = &pctrl->soc->groups[offset]; + + val = msm_readl_ctl(pctrl, g); + + return val & BIT(g->oe_bit) ? GPIO_LINE_DIRECTION_OUT : + GPIO_LINE_DIRECTION_IN; +} + +static int msm_gpio_get(struct gpio_chip *chip, unsigned offset) +{ + const struct msm_pingroup *g; + struct msm_pinctrl *pctrl = gpiochip_get_data(chip); + u32 val; + + g = &pctrl->soc->groups[offset]; + + val = msm_readl_io(pctrl, g); + return !!(val & BIT(g->in_bit)); +} + +static void msm_gpio_set(struct gpio_chip *chip, unsigned offset, int value) +{ + const struct msm_pingroup *g; + struct msm_pinctrl *pctrl = gpiochip_get_data(chip); + unsigned long flags; + u32 val; + + g = &pctrl->soc->groups[offset]; + + raw_spin_lock_irqsave(&pctrl->lock, flags); + + val = msm_readl_io(pctrl, g); + if (value) + val |= BIT(g->out_bit); + else + val &= ~BIT(g->out_bit); + msm_writel_io(val, pctrl, g); + + raw_spin_unlock_irqrestore(&pctrl->lock, flags); +} + +#ifdef CONFIG_DEBUG_FS + +static void msm_gpio_dbg_show_one(struct seq_file *s, + struct pinctrl_dev *pctldev, + struct gpio_chip *chip, + unsigned offset, + unsigned gpio) +{ + const struct msm_pingroup *g; + struct msm_pinctrl *pctrl = gpiochip_get_data(chip); + unsigned func; + int is_out; + int drive; + int pull; + int val; + int egpio_enable; + u32 ctl_reg, io_reg; + + static const char * const pulls_keeper[] = { + "no pull", + "pull down", + "keeper", + "pull up" + }; + + static const char * const pulls_no_keeper[] = { + "no pull", + "pull down", + "pull up", + }; + + if (!gpiochip_line_is_valid(chip, offset)) + return; + + g = &pctrl->soc->groups[offset]; + ctl_reg = msm_readl_ctl(pctrl, g); + io_reg = msm_readl_io(pctrl, g); + + is_out = !!(ctl_reg & BIT(g->oe_bit)); + func = (ctl_reg >> g->mux_bit) & 7; + drive = (ctl_reg >> g->drv_bit) & 7; + pull = (ctl_reg >> g->pull_bit) & 3; + egpio_enable = 0; + if (pctrl->soc->egpio_func && ctl_reg & BIT(g->egpio_present)) + egpio_enable = !(ctl_reg & BIT(g->egpio_enable)); + + if (is_out) + val = !!(io_reg & BIT(g->out_bit)); + else + val = !!(io_reg & BIT(g->in_bit)); + + if (egpio_enable) { + seq_printf(s, " %-8s: egpio\n", g->grp.name); + return; + } + + seq_printf(s, " %-8s: %-3s", g->grp.name, is_out ? "out" : "in"); + seq_printf(s, " %-4s func%d", val ? "high" : "low", func); + seq_printf(s, " %dmA", msm_regval_to_drive(drive)); + if (pctrl->soc->pull_no_keeper) + seq_printf(s, " %s", pulls_no_keeper[pull]); + else + seq_printf(s, " %s", pulls_keeper[pull]); + seq_puts(s, "\n"); +} + +static void msm_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip) +{ + unsigned gpio = chip->base; + unsigned i; + + for (i = 0; i < chip->ngpio; i++, gpio++) + msm_gpio_dbg_show_one(s, NULL, chip, i, gpio); +} + +#else +#define msm_gpio_dbg_show NULL +#endif + +static int msm_gpio_init_valid_mask(struct gpio_chip *gc, + unsigned long *valid_mask, + unsigned int ngpios) +{ + struct msm_pinctrl *pctrl = gpiochip_get_data(gc); + int ret; + unsigned int len, i; + const int *reserved = pctrl->soc->reserved_gpios; + u16 *tmp; + + /* Remove driver-provided reserved GPIOs from valid_mask */ + if (reserved) { + for (i = 0; reserved[i] >= 0; i++) { + if (i >= ngpios || reserved[i] >= ngpios) { + dev_err(pctrl->dev, "invalid list of reserved GPIOs\n"); + return -EINVAL; + } + clear_bit(reserved[i], valid_mask); + } + + return 0; + } + + /* The number of GPIOs in the ACPI tables */ + len = ret = device_property_count_u16(pctrl->dev, "gpios"); + if (ret < 0) + return 0; + + if (ret > ngpios) + return -EINVAL; + + tmp = kmalloc_array(len, sizeof(*tmp), GFP_KERNEL); + if (!tmp) + return -ENOMEM; + + ret = device_property_read_u16_array(pctrl->dev, "gpios", tmp, len); + if (ret < 0) { + dev_err(pctrl->dev, "could not read list of GPIOs\n"); + goto out; + } + + bitmap_zero(valid_mask, ngpios); + for (i = 0; i < len; i++) + set_bit(tmp[i], valid_mask); + +out: + kfree(tmp); + return ret; +} + +static const struct gpio_chip msm_gpio_template = { + .direction_input = msm_gpio_direction_input, + .direction_output = msm_gpio_direction_output, + .get_direction = msm_gpio_get_direction, + .get = msm_gpio_get, + .set = msm_gpio_set, + .request = gpiochip_generic_request, + .free = gpiochip_generic_free, + .dbg_show = msm_gpio_dbg_show, +}; + +/* For dual-edge interrupts in software, since some hardware has no + * such support: + * + * At appropriate moments, this function may be called to flip the polarity + * settings of both-edge irq lines to try and catch the next edge. + * + * The attempt is considered successful if: + * - the status bit goes high, indicating that an edge was caught, or + * - the input value of the gpio doesn't change during the attempt. + * If the value changes twice during the process, that would cause the first + * test to fail but would force the second, as two opposite + * transitions would cause a detection no matter the polarity setting. + * + * The do-loop tries to sledge-hammer closed the timing hole between + * the initial value-read and the polarity-write - if the line value changes + * during that window, an interrupt is lost, the new polarity setting is + * incorrect, and the first success test will fail, causing a retry. + * + * Algorithm comes from Google's msmgpio driver. + */ +static void msm_gpio_update_dual_edge_pos(struct msm_pinctrl *pctrl, + const struct msm_pingroup *g, + struct irq_data *d) +{ + int loop_limit = 100; + unsigned val, val2, intstat; + unsigned pol; + + do { + val = msm_readl_io(pctrl, g) & BIT(g->in_bit); + + pol = msm_readl_intr_cfg(pctrl, g); + pol ^= BIT(g->intr_polarity_bit); + msm_writel_intr_cfg(pol, pctrl, g); + + val2 = msm_readl_io(pctrl, g) & BIT(g->in_bit); + intstat = msm_readl_intr_status(pctrl, g); + if (intstat || (val == val2)) + return; + } while (loop_limit-- > 0); + dev_err(pctrl->dev, "dual-edge irq failed to stabilize, %#08x != %#08x\n", + val, val2); +} + +static void msm_gpio_irq_mask(struct irq_data *d) +{ + struct gpio_chip *gc = irq_data_get_irq_chip_data(d); + struct msm_pinctrl *pctrl = gpiochip_get_data(gc); + const struct msm_pingroup *g; + unsigned long flags; + u32 val; + + if (d->parent_data) + irq_chip_mask_parent(d); + + if (test_bit(d->hwirq, pctrl->skip_wake_irqs)) + return; + + g = &pctrl->soc->groups[d->hwirq]; + + raw_spin_lock_irqsave(&pctrl->lock, flags); + + val = msm_readl_intr_cfg(pctrl, g); + /* + * There are two bits that control interrupt forwarding to the CPU. The + * RAW_STATUS_EN bit causes the level or edge sensed on the line to be + * latched into the interrupt status register when the hardware detects + * an irq that it's configured for (either edge for edge type or level + * for level type irq). The 'non-raw' status enable bit causes the + * hardware to assert the summary interrupt to the CPU if the latched + * status bit is set. There's a bug though, the edge detection logic + * seems to have a problem where toggling the RAW_STATUS_EN bit may + * cause the status bit to latch spuriously when there isn't any edge + * so we can't touch that bit for edge type irqs and we have to keep + * the bit set anyway so that edges are latched while the line is masked. + * + * To make matters more complicated, leaving the RAW_STATUS_EN bit + * enabled all the time causes level interrupts to re-latch into the + * status register because the level is still present on the line after + * we ack it. We clear the raw status enable bit during mask here and + * set the bit on unmask so the interrupt can't latch into the hardware + * while it's masked. + */ + if (irqd_get_trigger_type(d) & IRQ_TYPE_LEVEL_MASK) + val &= ~BIT(g->intr_raw_status_bit); + + val &= ~BIT(g->intr_enable_bit); + msm_writel_intr_cfg(val, pctrl, g); + + clear_bit(d->hwirq, pctrl->enabled_irqs); + + raw_spin_unlock_irqrestore(&pctrl->lock, flags); +} + +static void msm_gpio_irq_unmask(struct irq_data *d) +{ + struct gpio_chip *gc = irq_data_get_irq_chip_data(d); + struct msm_pinctrl *pctrl = gpiochip_get_data(gc); + const struct msm_pingroup *g; + unsigned long flags; + u32 val; + + if (d->parent_data) + irq_chip_unmask_parent(d); + + if (test_bit(d->hwirq, pctrl->skip_wake_irqs)) + return; + + g = &pctrl->soc->groups[d->hwirq]; + + raw_spin_lock_irqsave(&pctrl->lock, flags); + + val = msm_readl_intr_cfg(pctrl, g); + val |= BIT(g->intr_raw_status_bit); + val |= BIT(g->intr_enable_bit); + msm_writel_intr_cfg(val, pctrl, g); + + set_bit(d->hwirq, pctrl->enabled_irqs); + + raw_spin_unlock_irqrestore(&pctrl->lock, flags); +} + +static void msm_gpio_irq_enable(struct irq_data *d) +{ + struct gpio_chip *gc = irq_data_get_irq_chip_data(d); + struct msm_pinctrl *pctrl = gpiochip_get_data(gc); + + gpiochip_enable_irq(gc, d->hwirq); + + if (d->parent_data) + irq_chip_enable_parent(d); + + if (!test_bit(d->hwirq, pctrl->skip_wake_irqs)) + msm_gpio_irq_unmask(d); +} + +static void msm_gpio_irq_disable(struct irq_data *d) +{ + struct gpio_chip *gc = irq_data_get_irq_chip_data(d); + struct msm_pinctrl *pctrl = gpiochip_get_data(gc); + + if (d->parent_data) + irq_chip_disable_parent(d); + + if (!test_bit(d->hwirq, pctrl->skip_wake_irqs)) + msm_gpio_irq_mask(d); + + gpiochip_disable_irq(gc, d->hwirq); +} + +/** + * msm_gpio_update_dual_edge_parent() - Prime next edge for IRQs handled by parent. + * @d: The irq dta. + * + * This is much like msm_gpio_update_dual_edge_pos() but for IRQs that are + * normally handled by the parent irqchip. The logic here is slightly + * different due to what's easy to do with our parent, but in principle it's + * the same. + */ +static void msm_gpio_update_dual_edge_parent(struct irq_data *d) +{ + struct gpio_chip *gc = irq_data_get_irq_chip_data(d); + struct msm_pinctrl *pctrl = gpiochip_get_data(gc); + const struct msm_pingroup *g = &pctrl->soc->groups[d->hwirq]; + int loop_limit = 100; + unsigned int val; + unsigned int type; + + /* Read the value and make a guess about what edge we need to catch */ + val = msm_readl_io(pctrl, g) & BIT(g->in_bit); + type = val ? IRQ_TYPE_EDGE_FALLING : IRQ_TYPE_EDGE_RISING; + + do { + /* Set the parent to catch the next edge */ + irq_chip_set_type_parent(d, type); + + /* + * Possibly the line changed between when we last read "val" + * (and decided what edge we needed) and when set the edge. + * If the value didn't change (or changed and then changed + * back) then we're done. + */ + val = msm_readl_io(pctrl, g) & BIT(g->in_bit); + if (type == IRQ_TYPE_EDGE_RISING) { + if (!val) + return; + type = IRQ_TYPE_EDGE_FALLING; + } else if (type == IRQ_TYPE_EDGE_FALLING) { + if (val) + return; + type = IRQ_TYPE_EDGE_RISING; + } + } while (loop_limit-- > 0); + dev_warn_once(pctrl->dev, "dual-edge irq failed to stabilize\n"); +} + +static void msm_gpio_irq_ack(struct irq_data *d) +{ + struct gpio_chip *gc = irq_data_get_irq_chip_data(d); + struct msm_pinctrl *pctrl = gpiochip_get_data(gc); + const struct msm_pingroup *g; + unsigned long flags; + + if (test_bit(d->hwirq, pctrl->skip_wake_irqs)) { + if (test_bit(d->hwirq, pctrl->dual_edge_irqs)) + msm_gpio_update_dual_edge_parent(d); + return; + } + + g = &pctrl->soc->groups[d->hwirq]; + + raw_spin_lock_irqsave(&pctrl->lock, flags); + + msm_ack_intr_status(pctrl, g); + + if (test_bit(d->hwirq, pctrl->dual_edge_irqs)) + msm_gpio_update_dual_edge_pos(pctrl, g, d); + + raw_spin_unlock_irqrestore(&pctrl->lock, flags); +} + +static void msm_gpio_irq_eoi(struct irq_data *d) +{ + d = d->parent_data; + + if (d) + d->chip->irq_eoi(d); +} + +static bool msm_gpio_needs_dual_edge_parent_workaround(struct irq_data *d, + unsigned int type) +{ + struct gpio_chip *gc = irq_data_get_irq_chip_data(d); + struct msm_pinctrl *pctrl = gpiochip_get_data(gc); + + return type == IRQ_TYPE_EDGE_BOTH && + pctrl->soc->wakeirq_dual_edge_errata && d->parent_data && + test_bit(d->hwirq, pctrl->skip_wake_irqs); +} + +static int msm_gpio_irq_set_type(struct irq_data *d, unsigned int type) +{ + struct gpio_chip *gc = irq_data_get_irq_chip_data(d); + struct msm_pinctrl *pctrl = gpiochip_get_data(gc); + const struct msm_pingroup *g; + u32 intr_target_mask = GENMASK(2, 0); + unsigned long flags; + bool was_enabled; + u32 val; + + if (msm_gpio_needs_dual_edge_parent_workaround(d, type)) { + set_bit(d->hwirq, pctrl->dual_edge_irqs); + irq_set_handler_locked(d, handle_fasteoi_ack_irq); + msm_gpio_update_dual_edge_parent(d); + return 0; + } + + if (d->parent_data) + irq_chip_set_type_parent(d, type); + + if (test_bit(d->hwirq, pctrl->skip_wake_irqs)) { + clear_bit(d->hwirq, pctrl->dual_edge_irqs); + irq_set_handler_locked(d, handle_fasteoi_irq); + return 0; + } + + g = &pctrl->soc->groups[d->hwirq]; + + raw_spin_lock_irqsave(&pctrl->lock, flags); + + /* + * For hw without possibility of detecting both edges + */ + if (g->intr_detection_width == 1 && type == IRQ_TYPE_EDGE_BOTH) + set_bit(d->hwirq, pctrl->dual_edge_irqs); + else + clear_bit(d->hwirq, pctrl->dual_edge_irqs); + + /* Route interrupts to application cpu. + * With intr_target_use_scm interrupts are routed to + * application cpu using scm calls. + */ + if (g->intr_target_width) + intr_target_mask = GENMASK(g->intr_target_width - 1, 0); + + if (pctrl->intr_target_use_scm) { + u32 addr = pctrl->phys_base[0] + g->intr_target_reg; + int ret; + + qcom_scm_io_readl(addr, &val); + val &= ~(intr_target_mask << g->intr_target_bit); + val |= g->intr_target_kpss_val << g->intr_target_bit; + + ret = qcom_scm_io_writel(addr, val); + if (ret) + dev_err(pctrl->dev, + "Failed routing %lu interrupt to Apps proc", + d->hwirq); + } else { + val = msm_readl_intr_target(pctrl, g); + val &= ~(intr_target_mask << g->intr_target_bit); + val |= g->intr_target_kpss_val << g->intr_target_bit; + msm_writel_intr_target(val, pctrl, g); + } + + /* Update configuration for gpio. + * RAW_STATUS_EN is left on for all gpio irqs. Due to the + * internal circuitry of TLMM, toggling the RAW_STATUS + * could cause the INTR_STATUS to be set for EDGE interrupts. + */ + val = msm_readl_intr_cfg(pctrl, g); + was_enabled = val & BIT(g->intr_raw_status_bit); + val |= BIT(g->intr_raw_status_bit); + if (g->intr_detection_width == 2) { + val &= ~(3 << g->intr_detection_bit); + val &= ~(1 << g->intr_polarity_bit); + switch (type) { + case IRQ_TYPE_EDGE_RISING: + val |= 1 << g->intr_detection_bit; + val |= BIT(g->intr_polarity_bit); + break; + case IRQ_TYPE_EDGE_FALLING: + val |= 2 << g->intr_detection_bit; + val |= BIT(g->intr_polarity_bit); + break; + case IRQ_TYPE_EDGE_BOTH: + val |= 3 << g->intr_detection_bit; + val |= BIT(g->intr_polarity_bit); + break; + case IRQ_TYPE_LEVEL_LOW: + break; + case IRQ_TYPE_LEVEL_HIGH: + val |= BIT(g->intr_polarity_bit); + break; + } + } else if (g->intr_detection_width == 1) { + val &= ~(1 << g->intr_detection_bit); + val &= ~(1 << g->intr_polarity_bit); + switch (type) { + case IRQ_TYPE_EDGE_RISING: + val |= BIT(g->intr_detection_bit); + val |= BIT(g->intr_polarity_bit); + break; + case IRQ_TYPE_EDGE_FALLING: + val |= BIT(g->intr_detection_bit); + break; + case IRQ_TYPE_EDGE_BOTH: + val |= BIT(g->intr_detection_bit); + val |= BIT(g->intr_polarity_bit); + break; + case IRQ_TYPE_LEVEL_LOW: + break; + case IRQ_TYPE_LEVEL_HIGH: + val |= BIT(g->intr_polarity_bit); + break; + } + } else { + BUG(); + } + msm_writel_intr_cfg(val, pctrl, g); + + /* + * The first time we set RAW_STATUS_EN it could trigger an interrupt. + * Clear the interrupt. This is safe because we have + * IRQCHIP_SET_TYPE_MASKED. + */ + if (!was_enabled) + msm_ack_intr_status(pctrl, g); + + if (test_bit(d->hwirq, pctrl->dual_edge_irqs)) + msm_gpio_update_dual_edge_pos(pctrl, g, d); + + raw_spin_unlock_irqrestore(&pctrl->lock, flags); + + if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH)) + irq_set_handler_locked(d, handle_level_irq); + else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING)) + irq_set_handler_locked(d, handle_edge_irq); + + return 0; +} + +static int msm_gpio_irq_set_wake(struct irq_data *d, unsigned int on) +{ + struct gpio_chip *gc = irq_data_get_irq_chip_data(d); + struct msm_pinctrl *pctrl = gpiochip_get_data(gc); + + /* + * While they may not wake up when the TLMM is powered off, + * some GPIOs would like to wakeup the system from suspend + * when TLMM is powered on. To allow that, enable the GPIO + * summary line to be wakeup capable at GIC. + */ + if (d->parent_data && test_bit(d->hwirq, pctrl->skip_wake_irqs)) + return irq_chip_set_wake_parent(d, on); + + return irq_set_irq_wake(pctrl->irq, on); +} + +static int msm_gpio_irq_reqres(struct irq_data *d) +{ + struct gpio_chip *gc = irq_data_get_irq_chip_data(d); + struct msm_pinctrl *pctrl = gpiochip_get_data(gc); + int ret; + + if (!try_module_get(gc->owner)) + return -ENODEV; + + ret = msm_pinmux_request_gpio(pctrl->pctrl, NULL, d->hwirq); + if (ret) + goto out; + msm_gpio_direction_input(gc, d->hwirq); + + if (gpiochip_lock_as_irq(gc, d->hwirq)) { + dev_err(gc->parent, + "unable to lock HW IRQ %lu for IRQ\n", + d->hwirq); + ret = -EINVAL; + goto out; + } + + /* + * The disable / clear-enable workaround we do in msm_pinmux_set_mux() + * only works if disable is not lazy since we only clear any bogus + * interrupt in hardware. Explicitly mark the interrupt as UNLAZY. + */ + irq_set_status_flags(d->irq, IRQ_DISABLE_UNLAZY); + + return 0; +out: + module_put(gc->owner); + return ret; +} + +static void msm_gpio_irq_relres(struct irq_data *d) +{ + struct gpio_chip *gc = irq_data_get_irq_chip_data(d); + + gpiochip_unlock_as_irq(gc, d->hwirq); + module_put(gc->owner); +} + +static int msm_gpio_irq_set_affinity(struct irq_data *d, + const struct cpumask *dest, bool force) +{ + struct gpio_chip *gc = irq_data_get_irq_chip_data(d); + struct msm_pinctrl *pctrl = gpiochip_get_data(gc); + + if (d->parent_data && test_bit(d->hwirq, pctrl->skip_wake_irqs)) + return irq_chip_set_affinity_parent(d, dest, force); + + return -EINVAL; +} + +static int msm_gpio_irq_set_vcpu_affinity(struct irq_data *d, void *vcpu_info) +{ + struct gpio_chip *gc = irq_data_get_irq_chip_data(d); + struct msm_pinctrl *pctrl = gpiochip_get_data(gc); + + if (d->parent_data && test_bit(d->hwirq, pctrl->skip_wake_irqs)) + return irq_chip_set_vcpu_affinity_parent(d, vcpu_info); + + return -EINVAL; +} + +static void msm_gpio_irq_handler(struct irq_desc *desc) +{ + struct gpio_chip *gc = irq_desc_get_handler_data(desc); + const struct msm_pingroup *g; + struct msm_pinctrl *pctrl = gpiochip_get_data(gc); + struct irq_chip *chip = irq_desc_get_chip(desc); + int handled = 0; + u32 val; + int i; + + chained_irq_enter(chip, desc); + + /* + * Each pin has it's own IRQ status register, so use + * enabled_irq bitmap to limit the number of reads. + */ + for_each_set_bit(i, pctrl->enabled_irqs, pctrl->chip.ngpio) { + g = &pctrl->soc->groups[i]; + val = msm_readl_intr_status(pctrl, g); + if (val & BIT(g->intr_status_bit)) { + generic_handle_domain_irq(gc->irq.domain, i); + handled++; + } + } + + /* No interrupts were flagged */ + if (handled == 0) + handle_bad_irq(desc); + + chained_irq_exit(chip, desc); +} + +static int msm_gpio_wakeirq(struct gpio_chip *gc, + unsigned int child, + unsigned int child_type, + unsigned int *parent, + unsigned int *parent_type) +{ + struct msm_pinctrl *pctrl = gpiochip_get_data(gc); + const struct msm_gpio_wakeirq_map *map; + int i; + + *parent = GPIO_NO_WAKE_IRQ; + *parent_type = IRQ_TYPE_EDGE_RISING; + + for (i = 0; i < pctrl->soc->nwakeirq_map; i++) { + map = &pctrl->soc->wakeirq_map[i]; + if (map->gpio == child) { + *parent = map->wakeirq; + break; + } + } + + return 0; +} + +static bool msm_gpio_needs_valid_mask(struct msm_pinctrl *pctrl) +{ + if (pctrl->soc->reserved_gpios) + return true; + + return device_property_count_u16(pctrl->dev, "gpios") > 0; +} + +static const struct irq_chip msm_gpio_irq_chip = { + .name = "msmgpio", + .irq_enable = msm_gpio_irq_enable, + .irq_disable = msm_gpio_irq_disable, + .irq_mask = msm_gpio_irq_mask, + .irq_unmask = msm_gpio_irq_unmask, + .irq_ack = msm_gpio_irq_ack, + .irq_eoi = msm_gpio_irq_eoi, + .irq_set_type = msm_gpio_irq_set_type, + .irq_set_wake = msm_gpio_irq_set_wake, + .irq_request_resources = msm_gpio_irq_reqres, + .irq_release_resources = msm_gpio_irq_relres, + .irq_set_affinity = msm_gpio_irq_set_affinity, + .irq_set_vcpu_affinity = msm_gpio_irq_set_vcpu_affinity, + .flags = (IRQCHIP_MASK_ON_SUSPEND | + IRQCHIP_SET_TYPE_MASKED | + IRQCHIP_ENABLE_WAKEUP_ON_SUSPEND | + IRQCHIP_IMMUTABLE), +}; + +static int msm_gpio_init(struct msm_pinctrl *pctrl) +{ + struct gpio_chip *chip; + struct gpio_irq_chip *girq; + int i, ret; + unsigned gpio, ngpio = pctrl->soc->ngpios; + struct device_node *np; + bool skip; + + if (WARN_ON(ngpio > MAX_NR_GPIO)) + return -EINVAL; + + chip = &pctrl->chip; + chip->base = -1; + chip->ngpio = ngpio; + chip->label = dev_name(pctrl->dev); + chip->parent = pctrl->dev; + chip->owner = THIS_MODULE; + if (msm_gpio_needs_valid_mask(pctrl)) + chip->init_valid_mask = msm_gpio_init_valid_mask; + + np = of_parse_phandle(pctrl->dev->of_node, "wakeup-parent", 0); + if (np) { + chip->irq.parent_domain = irq_find_matching_host(np, + DOMAIN_BUS_WAKEUP); + of_node_put(np); + if (!chip->irq.parent_domain) + return -EPROBE_DEFER; + chip->irq.child_to_parent_hwirq = msm_gpio_wakeirq; + /* + * Let's skip handling the GPIOs, if the parent irqchip + * is handling the direct connect IRQ of the GPIO. + */ + skip = irq_domain_qcom_handle_wakeup(chip->irq.parent_domain); + for (i = 0; skip && i < pctrl->soc->nwakeirq_map; i++) { + gpio = pctrl->soc->wakeirq_map[i].gpio; + set_bit(gpio, pctrl->skip_wake_irqs); + } + } + + girq = &chip->irq; + gpio_irq_chip_set_chip(girq, &msm_gpio_irq_chip); + girq->parent_handler = msm_gpio_irq_handler; + girq->fwnode = dev_fwnode(pctrl->dev); + girq->num_parents = 1; + girq->parents = devm_kcalloc(pctrl->dev, 1, sizeof(*girq->parents), + GFP_KERNEL); + if (!girq->parents) + return -ENOMEM; + girq->default_type = IRQ_TYPE_NONE; + girq->handler = handle_bad_irq; + girq->parents[0] = pctrl->irq; + + ret = gpiochip_add_data(&pctrl->chip, pctrl); + if (ret) { + dev_err(pctrl->dev, "Failed register gpiochip\n"); + return ret; + } + + /* + * For DeviceTree-supported systems, the gpio core checks the + * pinctrl's device node for the "gpio-ranges" property. + * If it is present, it takes care of adding the pin ranges + * for the driver. In this case the driver can skip ahead. + * + * In order to remain compatible with older, existing DeviceTree + * files which don't set the "gpio-ranges" property or systems that + * utilize ACPI the driver has to call gpiochip_add_pin_range(). + */ + if (!of_property_read_bool(pctrl->dev->of_node, "gpio-ranges")) { + ret = gpiochip_add_pin_range(&pctrl->chip, + dev_name(pctrl->dev), 0, 0, chip->ngpio); + if (ret) { + dev_err(pctrl->dev, "Failed to add pin range\n"); + gpiochip_remove(&pctrl->chip); + return ret; + } + } + + return 0; +} + +static int msm_ps_hold_restart(struct notifier_block *nb, unsigned long action, + void *data) +{ + struct msm_pinctrl *pctrl = container_of(nb, struct msm_pinctrl, restart_nb); + + writel(0, pctrl->regs[0] + PS_HOLD_OFFSET); + mdelay(1000); + return NOTIFY_DONE; +} + +static struct msm_pinctrl *poweroff_pctrl; + +static void msm_ps_hold_poweroff(void) +{ + msm_ps_hold_restart(&poweroff_pctrl->restart_nb, 0, NULL); +} + +static void msm_pinctrl_setup_pm_reset(struct msm_pinctrl *pctrl) +{ + int i; + const struct pinfunction *func = pctrl->soc->functions; + + for (i = 0; i < pctrl->soc->nfunctions; i++) + if (!strcmp(func[i].name, "ps_hold")) { + pctrl->restart_nb.notifier_call = msm_ps_hold_restart; + pctrl->restart_nb.priority = 128; + if (register_restart_handler(&pctrl->restart_nb)) + dev_err(pctrl->dev, + "failed to setup restart handler.\n"); + poweroff_pctrl = pctrl; + pm_power_off = msm_ps_hold_poweroff; + break; + } +} + +static __maybe_unused int msm_pinctrl_suspend(struct device *dev) +{ + struct msm_pinctrl *pctrl = dev_get_drvdata(dev); + + return pinctrl_force_sleep(pctrl->pctrl); +} + +static __maybe_unused int msm_pinctrl_resume(struct device *dev) +{ + struct msm_pinctrl *pctrl = dev_get_drvdata(dev); + + return pinctrl_force_default(pctrl->pctrl); +} + +SIMPLE_DEV_PM_OPS(msm_pinctrl_dev_pm_ops, msm_pinctrl_suspend, + msm_pinctrl_resume); + +EXPORT_SYMBOL(msm_pinctrl_dev_pm_ops); + +int msm_pinctrl_probe(struct platform_device *pdev, + const struct msm_pinctrl_soc_data *soc_data) +{ + struct msm_pinctrl *pctrl; + struct resource *res; + int ret; + int i; + + pctrl = devm_kzalloc(&pdev->dev, sizeof(*pctrl), GFP_KERNEL); + if (!pctrl) + return -ENOMEM; + + pctrl->dev = &pdev->dev; + pctrl->soc = soc_data; + pctrl->chip = msm_gpio_template; + pctrl->intr_target_use_scm = of_device_is_compatible( + pctrl->dev->of_node, + "qcom,ipq8064-pinctrl"); + + raw_spin_lock_init(&pctrl->lock); + + if (soc_data->tiles) { + for (i = 0; i < soc_data->ntiles; i++) { + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, + soc_data->tiles[i]); + pctrl->regs[i] = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(pctrl->regs[i])) + return PTR_ERR(pctrl->regs[i]); + } + } else { + pctrl->regs[0] = devm_platform_get_and_ioremap_resource(pdev, 0, &res); + if (IS_ERR(pctrl->regs[0])) + return PTR_ERR(pctrl->regs[0]); + + pctrl->phys_base[0] = res->start; + } + + msm_pinctrl_setup_pm_reset(pctrl); + + pctrl->irq = platform_get_irq(pdev, 0); + if (pctrl->irq < 0) + return pctrl->irq; + + pctrl->desc.owner = THIS_MODULE; + pctrl->desc.pctlops = &msm_pinctrl_ops; + pctrl->desc.pmxops = &msm_pinmux_ops; + pctrl->desc.confops = &msm_pinconf_ops; + pctrl->desc.name = dev_name(&pdev->dev); + pctrl->desc.pins = pctrl->soc->pins; + pctrl->desc.npins = pctrl->soc->npins; + + pctrl->pctrl = devm_pinctrl_register(&pdev->dev, &pctrl->desc, pctrl); + if (IS_ERR(pctrl->pctrl)) { + dev_err(&pdev->dev, "Couldn't register pinctrl driver\n"); + return PTR_ERR(pctrl->pctrl); + } + + ret = msm_gpio_init(pctrl); + if (ret) + return ret; + + platform_set_drvdata(pdev, pctrl); + + dev_dbg(&pdev->dev, "Probed Qualcomm pinctrl driver\n"); + + return 0; +} +EXPORT_SYMBOL(msm_pinctrl_probe); + +int msm_pinctrl_remove(struct platform_device *pdev) +{ + struct msm_pinctrl *pctrl = platform_get_drvdata(pdev); + + gpiochip_remove(&pctrl->chip); + + unregister_restart_handler(&pctrl->restart_nb); + + return 0; +} +EXPORT_SYMBOL(msm_pinctrl_remove); + +MODULE_DESCRIPTION("Qualcomm Technologies, Inc. TLMM driver"); +MODULE_LICENSE("GPL v2"); diff --git a/drivers/pinctrl/qcom/pinctrl-msm.h b/drivers/pinctrl/qcom/pinctrl-msm.h new file mode 100644 index 0000000000..1d2f2e904d --- /dev/null +++ b/drivers/pinctrl/qcom/pinctrl-msm.h @@ -0,0 +1,171 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2013, Sony Mobile Communications AB. + */ +#ifndef __PINCTRL_MSM_H__ +#define __PINCTRL_MSM_H__ + +#include <linux/pm.h> +#include <linux/types.h> + +#include <linux/pinctrl/pinctrl.h> + +struct platform_device; + +struct pinctrl_pin_desc; + +#define APQ_PIN_FUNCTION(fname) \ + [APQ_MUX_##fname] = PINCTRL_PINFUNCTION(#fname, \ + fname##_groups, \ + ARRAY_SIZE(fname##_groups)) + +#define IPQ_PIN_FUNCTION(fname) \ + [IPQ_MUX_##fname] = PINCTRL_PINFUNCTION(#fname, \ + fname##_groups, \ + ARRAY_SIZE(fname##_groups)) + +#define MSM_PIN_FUNCTION(fname) \ + [msm_mux_##fname] = PINCTRL_PINFUNCTION(#fname, \ + fname##_groups, \ + ARRAY_SIZE(fname##_groups)) + +#define QCA_PIN_FUNCTION(fname) \ + [qca_mux_##fname] = PINCTRL_PINFUNCTION(#fname, \ + fname##_groups, \ + ARRAY_SIZE(fname##_groups)) + +/** + * struct msm_pingroup - Qualcomm pingroup definition + * @grp: Generic data of the pin group (name and pins) + * @funcs: A list of pinmux functions that can be selected for + * this group. The index of the selected function is used + * for programming the function selector. + * Entries should be indices into the groups list of the + * struct msm_pinctrl_soc_data. + * @ctl_reg: Offset of the register holding control bits for this group. + * @io_reg: Offset of the register holding input/output bits for this group. + * @intr_cfg_reg: Offset of the register holding interrupt configuration bits. + * @intr_status_reg: Offset of the register holding the status bits for this group. + * @intr_target_reg: Offset of the register specifying routing of the interrupts + * from this group. + * @mux_bit: Offset in @ctl_reg for the pinmux function selection. + * @pull_bit: Offset in @ctl_reg for the bias configuration. + * @drv_bit: Offset in @ctl_reg for the drive strength configuration. + * @od_bit: Offset in @ctl_reg for controlling open drain. + * @oe_bit: Offset in @ctl_reg for controlling output enable. + * @in_bit: Offset in @io_reg for the input bit value. + * @out_bit: Offset in @io_reg for the output bit value. + * @intr_enable_bit: Offset in @intr_cfg_reg for enabling the interrupt for this group. + * @intr_status_bit: Offset in @intr_status_reg for reading and acking the interrupt + * status. + * @intr_target_bit: Offset in @intr_target_reg for configuring the interrupt routing. + * @intr_target_width: Number of bits used for specifying interrupt routing target. + * @intr_target_kpss_val: Value in @intr_target_bit for specifying that the interrupt from + * this gpio should get routed to the KPSS processor. + * @intr_raw_status_bit: Offset in @intr_cfg_reg for the raw status bit. + * @intr_polarity_bit: Offset in @intr_cfg_reg for specifying polarity of the interrupt. + * @intr_detection_bit: Offset in @intr_cfg_reg for specifying interrupt type. + * @intr_detection_width: Number of bits used for specifying interrupt type, + * Should be 2 for SoCs that can detect both edges in hardware, + * otherwise 1. + */ +struct msm_pingroup { + struct pingroup grp; + + unsigned *funcs; + unsigned nfuncs; + + u32 ctl_reg; + u32 io_reg; + u32 intr_cfg_reg; + u32 intr_status_reg; + u32 intr_target_reg; + + unsigned int tile:2; + + unsigned mux_bit:5; + + unsigned pull_bit:5; + unsigned drv_bit:5; + unsigned i2c_pull_bit:5; + + unsigned od_bit:5; + unsigned egpio_enable:5; + unsigned egpio_present:5; + unsigned oe_bit:5; + unsigned in_bit:5; + unsigned out_bit:5; + + unsigned intr_enable_bit:5; + unsigned intr_status_bit:5; + unsigned intr_ack_high:1; + + unsigned intr_target_bit:5; + unsigned intr_target_width:5; + unsigned intr_target_kpss_val:5; + unsigned intr_raw_status_bit:5; + unsigned intr_polarity_bit:5; + unsigned intr_detection_bit:5; + unsigned intr_detection_width:5; +}; + +/** + * struct msm_gpio_wakeirq_map - Map of GPIOs and their wakeup pins + * @gpio: The GPIOs that are wakeup capable + * @wakeirq: The interrupt at the always-on interrupt controller + */ +struct msm_gpio_wakeirq_map { + unsigned int gpio; + unsigned int wakeirq; +}; + +/** + * struct msm_pinctrl_soc_data - Qualcomm pin controller driver configuration + * @pins: An array describing all pins the pin controller affects. + * @npins: The number of entries in @pins. + * @functions: An array describing all mux functions the SoC supports. + * @nfunctions: The number of entries in @functions. + * @groups: An array describing all pin groups the pin SoC supports. + * @ngroups: The numbmer of entries in @groups. + * @ngpio: The number of pingroups the driver should expose as GPIOs. + * @pull_no_keeper: The SoC does not support keeper bias. + * @wakeirq_map: The map of wakeup capable GPIOs and the pin at PDC/MPM + * @nwakeirq_map: The number of entries in @wakeirq_map + * @wakeirq_dual_edge_errata: If true then GPIOs using the wakeirq_map need + * to be aware that their parent can't handle dual + * edge interrupts. + * @gpio_func: Which function number is GPIO (usually 0). + * @egpio_func: If non-zero then this SoC supports eGPIO. Even though in + * hardware this is a mux 1-level above the TLMM, we'll treat + * it as if this is just another mux state of the TLMM. Since + * it doesn't really map to hardware, we'll allocate a virtual + * function number for eGPIO and any time we see that function + * number used we'll treat it as a request to mux away from + * our TLMM towards another owner. + */ +struct msm_pinctrl_soc_data { + const struct pinctrl_pin_desc *pins; + unsigned npins; + const struct pinfunction *functions; + unsigned nfunctions; + const struct msm_pingroup *groups; + unsigned ngroups; + unsigned ngpios; + bool pull_no_keeper; + const char *const *tiles; + unsigned int ntiles; + const int *reserved_gpios; + const struct msm_gpio_wakeirq_map *wakeirq_map; + unsigned int nwakeirq_map; + bool wakeirq_dual_edge_errata; + unsigned int gpio_func; + unsigned int egpio_func; +}; + +extern const struct dev_pm_ops msm_pinctrl_dev_pm_ops; + +int msm_pinctrl_probe(struct platform_device *pdev, + const struct msm_pinctrl_soc_data *soc_data); +int msm_pinctrl_remove(struct platform_device *pdev); + +#endif diff --git a/drivers/pinctrl/qcom/pinctrl-msm8226.c b/drivers/pinctrl/qcom/pinctrl-msm8226.c new file mode 100644 index 0000000000..994619840a --- /dev/null +++ b/drivers/pinctrl/qcom/pinctrl-msm8226.c @@ -0,0 +1,659 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2020, The Linux Foundation. All rights reserved. + */ + +#include <linux/module.h> +#include <linux/of.h> +#include <linux/platform_device.h> + +#include "pinctrl-msm.h" + +static const struct pinctrl_pin_desc msm8226_pins[] = { + PINCTRL_PIN(0, "GPIO_0"), + PINCTRL_PIN(1, "GPIO_1"), + PINCTRL_PIN(2, "GPIO_2"), + PINCTRL_PIN(3, "GPIO_3"), + PINCTRL_PIN(4, "GPIO_4"), + PINCTRL_PIN(5, "GPIO_5"), + PINCTRL_PIN(6, "GPIO_6"), + PINCTRL_PIN(7, "GPIO_7"), + PINCTRL_PIN(8, "GPIO_8"), + PINCTRL_PIN(9, "GPIO_9"), + PINCTRL_PIN(10, "GPIO_10"), + PINCTRL_PIN(11, "GPIO_11"), + PINCTRL_PIN(12, "GPIO_12"), + PINCTRL_PIN(13, "GPIO_13"), + PINCTRL_PIN(14, "GPIO_14"), + PINCTRL_PIN(15, "GPIO_15"), + PINCTRL_PIN(16, "GPIO_16"), + PINCTRL_PIN(17, "GPIO_17"), + PINCTRL_PIN(18, "GPIO_18"), + PINCTRL_PIN(19, "GPIO_19"), + PINCTRL_PIN(20, "GPIO_20"), + PINCTRL_PIN(21, "GPIO_21"), + PINCTRL_PIN(22, "GPIO_22"), + PINCTRL_PIN(23, "GPIO_23"), + PINCTRL_PIN(24, "GPIO_24"), + PINCTRL_PIN(25, "GPIO_25"), + PINCTRL_PIN(26, "GPIO_26"), + PINCTRL_PIN(27, "GPIO_27"), + PINCTRL_PIN(28, "GPIO_28"), + PINCTRL_PIN(29, "GPIO_29"), + PINCTRL_PIN(30, "GPIO_30"), + PINCTRL_PIN(31, "GPIO_31"), + PINCTRL_PIN(32, "GPIO_32"), + PINCTRL_PIN(33, "GPIO_33"), + PINCTRL_PIN(34, "GPIO_34"), + PINCTRL_PIN(35, "GPIO_35"), + PINCTRL_PIN(36, "GPIO_36"), + PINCTRL_PIN(37, "GPIO_37"), + PINCTRL_PIN(38, "GPIO_38"), + PINCTRL_PIN(39, "GPIO_39"), + PINCTRL_PIN(40, "GPIO_40"), + PINCTRL_PIN(41, "GPIO_41"), + PINCTRL_PIN(42, "GPIO_42"), + PINCTRL_PIN(43, "GPIO_43"), + PINCTRL_PIN(44, "GPIO_44"), + PINCTRL_PIN(45, "GPIO_45"), + PINCTRL_PIN(46, "GPIO_46"), + PINCTRL_PIN(47, "GPIO_47"), + PINCTRL_PIN(48, "GPIO_48"), + PINCTRL_PIN(49, "GPIO_49"), + PINCTRL_PIN(50, "GPIO_50"), + PINCTRL_PIN(51, "GPIO_51"), + PINCTRL_PIN(52, "GPIO_52"), + PINCTRL_PIN(53, "GPIO_53"), + PINCTRL_PIN(54, "GPIO_54"), + PINCTRL_PIN(55, "GPIO_55"), + PINCTRL_PIN(56, "GPIO_56"), + PINCTRL_PIN(57, "GPIO_57"), + PINCTRL_PIN(58, "GPIO_58"), + PINCTRL_PIN(59, "GPIO_59"), + PINCTRL_PIN(60, "GPIO_60"), + PINCTRL_PIN(61, "GPIO_61"), + PINCTRL_PIN(62, "GPIO_62"), + PINCTRL_PIN(63, "GPIO_63"), + PINCTRL_PIN(64, "GPIO_64"), + PINCTRL_PIN(65, "GPIO_65"), + PINCTRL_PIN(66, "GPIO_66"), + PINCTRL_PIN(67, "GPIO_67"), + PINCTRL_PIN(68, "GPIO_68"), + PINCTRL_PIN(69, "GPIO_69"), + PINCTRL_PIN(70, "GPIO_70"), + PINCTRL_PIN(71, "GPIO_71"), + PINCTRL_PIN(72, "GPIO_72"), + PINCTRL_PIN(73, "GPIO_73"), + PINCTRL_PIN(74, "GPIO_74"), + PINCTRL_PIN(75, "GPIO_75"), + PINCTRL_PIN(76, "GPIO_76"), + PINCTRL_PIN(77, "GPIO_77"), + PINCTRL_PIN(78, "GPIO_78"), + PINCTRL_PIN(79, "GPIO_79"), + PINCTRL_PIN(80, "GPIO_80"), + PINCTRL_PIN(81, "GPIO_81"), + PINCTRL_PIN(82, "GPIO_82"), + PINCTRL_PIN(83, "GPIO_83"), + PINCTRL_PIN(84, "GPIO_84"), + PINCTRL_PIN(85, "GPIO_85"), + PINCTRL_PIN(86, "GPIO_86"), + PINCTRL_PIN(87, "GPIO_87"), + PINCTRL_PIN(88, "GPIO_88"), + PINCTRL_PIN(89, "GPIO_89"), + PINCTRL_PIN(90, "GPIO_90"), + PINCTRL_PIN(91, "GPIO_91"), + PINCTRL_PIN(92, "GPIO_92"), + PINCTRL_PIN(93, "GPIO_93"), + PINCTRL_PIN(94, "GPIO_94"), + PINCTRL_PIN(95, "GPIO_95"), + PINCTRL_PIN(96, "GPIO_96"), + PINCTRL_PIN(97, "GPIO_97"), + PINCTRL_PIN(98, "GPIO_98"), + PINCTRL_PIN(99, "GPIO_99"), + PINCTRL_PIN(100, "GPIO_100"), + PINCTRL_PIN(101, "GPIO_101"), + PINCTRL_PIN(102, "GPIO_102"), + PINCTRL_PIN(103, "GPIO_103"), + PINCTRL_PIN(104, "GPIO_104"), + PINCTRL_PIN(105, "GPIO_105"), + PINCTRL_PIN(106, "GPIO_106"), + PINCTRL_PIN(107, "GPIO_107"), + PINCTRL_PIN(108, "GPIO_108"), + PINCTRL_PIN(109, "GPIO_109"), + PINCTRL_PIN(110, "GPIO_110"), + PINCTRL_PIN(111, "GPIO_111"), + PINCTRL_PIN(112, "GPIO_112"), + PINCTRL_PIN(113, "GPIO_113"), + PINCTRL_PIN(114, "GPIO_114"), + PINCTRL_PIN(115, "GPIO_115"), + PINCTRL_PIN(116, "GPIO_116"), + + PINCTRL_PIN(117, "SDC1_CLK"), + PINCTRL_PIN(118, "SDC1_CMD"), + PINCTRL_PIN(119, "SDC1_DATA"), + PINCTRL_PIN(120, "SDC2_CLK"), + PINCTRL_PIN(121, "SDC2_CMD"), + PINCTRL_PIN(122, "SDC2_DATA"), +}; + +#define DECLARE_MSM_GPIO_PINS(pin) static const unsigned int gpio##pin##_pins[] = { pin } +DECLARE_MSM_GPIO_PINS(0); +DECLARE_MSM_GPIO_PINS(1); +DECLARE_MSM_GPIO_PINS(2); +DECLARE_MSM_GPIO_PINS(3); +DECLARE_MSM_GPIO_PINS(4); +DECLARE_MSM_GPIO_PINS(5); +DECLARE_MSM_GPIO_PINS(6); +DECLARE_MSM_GPIO_PINS(7); +DECLARE_MSM_GPIO_PINS(8); +DECLARE_MSM_GPIO_PINS(9); +DECLARE_MSM_GPIO_PINS(10); +DECLARE_MSM_GPIO_PINS(11); +DECLARE_MSM_GPIO_PINS(12); +DECLARE_MSM_GPIO_PINS(13); +DECLARE_MSM_GPIO_PINS(14); +DECLARE_MSM_GPIO_PINS(15); +DECLARE_MSM_GPIO_PINS(16); +DECLARE_MSM_GPIO_PINS(17); +DECLARE_MSM_GPIO_PINS(18); +DECLARE_MSM_GPIO_PINS(19); +DECLARE_MSM_GPIO_PINS(20); +DECLARE_MSM_GPIO_PINS(21); +DECLARE_MSM_GPIO_PINS(22); +DECLARE_MSM_GPIO_PINS(23); +DECLARE_MSM_GPIO_PINS(24); +DECLARE_MSM_GPIO_PINS(25); +DECLARE_MSM_GPIO_PINS(26); +DECLARE_MSM_GPIO_PINS(27); +DECLARE_MSM_GPIO_PINS(28); +DECLARE_MSM_GPIO_PINS(29); +DECLARE_MSM_GPIO_PINS(30); +DECLARE_MSM_GPIO_PINS(31); +DECLARE_MSM_GPIO_PINS(32); +DECLARE_MSM_GPIO_PINS(33); +DECLARE_MSM_GPIO_PINS(34); +DECLARE_MSM_GPIO_PINS(35); +DECLARE_MSM_GPIO_PINS(36); +DECLARE_MSM_GPIO_PINS(37); +DECLARE_MSM_GPIO_PINS(38); +DECLARE_MSM_GPIO_PINS(39); +DECLARE_MSM_GPIO_PINS(40); +DECLARE_MSM_GPIO_PINS(41); +DECLARE_MSM_GPIO_PINS(42); +DECLARE_MSM_GPIO_PINS(43); +DECLARE_MSM_GPIO_PINS(44); +DECLARE_MSM_GPIO_PINS(45); +DECLARE_MSM_GPIO_PINS(46); +DECLARE_MSM_GPIO_PINS(47); +DECLARE_MSM_GPIO_PINS(48); +DECLARE_MSM_GPIO_PINS(49); +DECLARE_MSM_GPIO_PINS(50); +DECLARE_MSM_GPIO_PINS(51); +DECLARE_MSM_GPIO_PINS(52); +DECLARE_MSM_GPIO_PINS(53); +DECLARE_MSM_GPIO_PINS(54); +DECLARE_MSM_GPIO_PINS(55); +DECLARE_MSM_GPIO_PINS(56); +DECLARE_MSM_GPIO_PINS(57); +DECLARE_MSM_GPIO_PINS(58); +DECLARE_MSM_GPIO_PINS(59); +DECLARE_MSM_GPIO_PINS(60); +DECLARE_MSM_GPIO_PINS(61); +DECLARE_MSM_GPIO_PINS(62); +DECLARE_MSM_GPIO_PINS(63); +DECLARE_MSM_GPIO_PINS(64); +DECLARE_MSM_GPIO_PINS(65); +DECLARE_MSM_GPIO_PINS(66); +DECLARE_MSM_GPIO_PINS(67); +DECLARE_MSM_GPIO_PINS(68); +DECLARE_MSM_GPIO_PINS(69); +DECLARE_MSM_GPIO_PINS(70); +DECLARE_MSM_GPIO_PINS(71); +DECLARE_MSM_GPIO_PINS(72); +DECLARE_MSM_GPIO_PINS(73); +DECLARE_MSM_GPIO_PINS(74); +DECLARE_MSM_GPIO_PINS(75); +DECLARE_MSM_GPIO_PINS(76); +DECLARE_MSM_GPIO_PINS(77); +DECLARE_MSM_GPIO_PINS(78); +DECLARE_MSM_GPIO_PINS(79); +DECLARE_MSM_GPIO_PINS(80); +DECLARE_MSM_GPIO_PINS(81); +DECLARE_MSM_GPIO_PINS(82); +DECLARE_MSM_GPIO_PINS(83); +DECLARE_MSM_GPIO_PINS(84); +DECLARE_MSM_GPIO_PINS(85); +DECLARE_MSM_GPIO_PINS(86); +DECLARE_MSM_GPIO_PINS(87); +DECLARE_MSM_GPIO_PINS(88); +DECLARE_MSM_GPIO_PINS(89); +DECLARE_MSM_GPIO_PINS(90); +DECLARE_MSM_GPIO_PINS(91); +DECLARE_MSM_GPIO_PINS(92); +DECLARE_MSM_GPIO_PINS(93); +DECLARE_MSM_GPIO_PINS(94); +DECLARE_MSM_GPIO_PINS(95); +DECLARE_MSM_GPIO_PINS(96); +DECLARE_MSM_GPIO_PINS(97); +DECLARE_MSM_GPIO_PINS(98); +DECLARE_MSM_GPIO_PINS(99); +DECLARE_MSM_GPIO_PINS(100); +DECLARE_MSM_GPIO_PINS(101); +DECLARE_MSM_GPIO_PINS(102); +DECLARE_MSM_GPIO_PINS(103); +DECLARE_MSM_GPIO_PINS(104); +DECLARE_MSM_GPIO_PINS(105); +DECLARE_MSM_GPIO_PINS(106); +DECLARE_MSM_GPIO_PINS(107); +DECLARE_MSM_GPIO_PINS(108); +DECLARE_MSM_GPIO_PINS(109); +DECLARE_MSM_GPIO_PINS(110); +DECLARE_MSM_GPIO_PINS(111); +DECLARE_MSM_GPIO_PINS(112); +DECLARE_MSM_GPIO_PINS(113); +DECLARE_MSM_GPIO_PINS(114); +DECLARE_MSM_GPIO_PINS(115); +DECLARE_MSM_GPIO_PINS(116); + +static const unsigned int sdc1_clk_pins[] = { 117 }; +static const unsigned int sdc1_cmd_pins[] = { 118 }; +static const unsigned int sdc1_data_pins[] = { 119 }; +static const unsigned int sdc2_clk_pins[] = { 120 }; +static const unsigned int sdc2_cmd_pins[] = { 121 }; +static const unsigned int sdc2_data_pins[] = { 122 }; + +#define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7) \ + { \ + .grp = PINCTRL_PINGROUP("gpio" #id, \ + gpio##id##_pins, \ + ARRAY_SIZE(gpio##id##_pins)), \ + .funcs = (int[]){ \ + msm_mux_gpio, \ + msm_mux_##f1, \ + msm_mux_##f2, \ + msm_mux_##f3, \ + msm_mux_##f4, \ + msm_mux_##f5, \ + msm_mux_##f6, \ + msm_mux_##f7 \ + }, \ + .nfuncs = 8, \ + .ctl_reg = 0x1000 + 0x10 * id, \ + .io_reg = 0x1004 + 0x10 * id, \ + .intr_cfg_reg = 0x1008 + 0x10 * id, \ + .intr_status_reg = 0x100c + 0x10 * id, \ + .intr_target_reg = 0x1008 + 0x10 * id, \ + .mux_bit = 2, \ + .pull_bit = 0, \ + .drv_bit = 6, \ + .oe_bit = 9, \ + .in_bit = 0, \ + .out_bit = 1, \ + .intr_enable_bit = 0, \ + .intr_status_bit = 0, \ + .intr_target_bit = 5, \ + .intr_target_kpss_val = 4, \ + .intr_raw_status_bit = 4, \ + .intr_polarity_bit = 1, \ + .intr_detection_bit = 2, \ + .intr_detection_width = 2, \ + } + +#define SDC_PINGROUP(pg_name, ctl, pull, drv) \ + { \ + .grp = PINCTRL_PINGROUP(#pg_name, \ + pg_name##_pins, \ + ARRAY_SIZE(pg_name##_pins)), \ + .ctl_reg = ctl, \ + .io_reg = 0, \ + .intr_cfg_reg = 0, \ + .intr_status_reg = 0, \ + .intr_target_reg = 0, \ + .mux_bit = -1, \ + .pull_bit = pull, \ + .drv_bit = drv, \ + .oe_bit = -1, \ + .in_bit = -1, \ + .out_bit = -1, \ + .intr_enable_bit = -1, \ + .intr_status_bit = -1, \ + .intr_target_bit = -1, \ + .intr_target_kpss_val = -1, \ + .intr_raw_status_bit = -1, \ + .intr_polarity_bit = -1, \ + .intr_detection_bit = -1, \ + .intr_detection_width = -1, \ + } + +/* + * TODO: Add the rest of the possible functions and fill out + * the pingroup table below. + */ +enum msm8226_functions { + msm_mux_audio_pcm, + msm_mux_blsp_i2c1, + msm_mux_blsp_i2c2, + msm_mux_blsp_i2c3, + msm_mux_blsp_i2c4, + msm_mux_blsp_i2c5, + msm_mux_blsp_spi1, + msm_mux_blsp_spi2, + msm_mux_blsp_spi3, + msm_mux_blsp_spi4, + msm_mux_blsp_spi5, + msm_mux_blsp_uart1, + msm_mux_blsp_uart2, + msm_mux_blsp_uart3, + msm_mux_blsp_uart4, + msm_mux_blsp_uart5, + msm_mux_blsp_uim1, + msm_mux_blsp_uim2, + msm_mux_blsp_uim3, + msm_mux_blsp_uim4, + msm_mux_blsp_uim5, + msm_mux_cam_mclk0, + msm_mux_cam_mclk1, + msm_mux_cci_i2c0, + msm_mux_gp0_clk, + msm_mux_gp1_clk, + msm_mux_gpio, + msm_mux_sdc3, + msm_mux_wlan, + msm_mux_NA, +}; + +static const char * const gpio_groups[] = { + "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7", + "gpio8", "gpio9", "gpio10", "gpio11", "gpio12", "gpio13", "gpio14", + "gpio15", "gpio16", "gpio17", "gpio18", "gpio19", "gpio20", "gpio21", + "gpio22", "gpio23", "gpio24", "gpio25", "gpio26", "gpio27", "gpio28", + "gpio29", "gpio30", "gpio31", "gpio32", "gpio33", "gpio34", "gpio35", + "gpio36", "gpio37", "gpio38", "gpio39", "gpio40", "gpio41", "gpio42", + "gpio43", "gpio44", "gpio45", "gpio46", "gpio47", "gpio48", "gpio49", + "gpio50", "gpio51", "gpio52", "gpio53", "gpio54", "gpio55", "gpio56", + "gpio57", "gpio58", "gpio59", "gpio60", "gpio61", "gpio62", "gpio63", + "gpio64", "gpio65", "gpio66", "gpio67", "gpio68", "gpio69", "gpio70", + "gpio71", "gpio72", "gpio73", "gpio74", "gpio75", "gpio76", "gpio77", + "gpio78", "gpio79", "gpio80", "gpio81", "gpio82", "gpio83", "gpio84", + "gpio85", "gpio86", "gpio87", "gpio88", "gpio89", "gpio90", "gpio91", + "gpio92", "gpio93", "gpio94", "gpio95", "gpio96", "gpio97", "gpio98", + "gpio99", "gpio100", "gpio101", "gpio102", "gpio103", "gpio104", + "gpio105", "gpio106", "gpio107", "gpio108", "gpio109", "gpio110", + "gpio111", "gpio112", "gpio113", "gpio114", "gpio115", "gpio116", +}; + +static const char * const audio_pcm_groups[] = { + "gpio63", "gpio64", "gpio65", "gpio66" +}; + +static const char * const blsp_uart1_groups[] = { + "gpio0", "gpio1", "gpio2", "gpio3" +}; + +static const char * const blsp_uim1_groups[] = { "gpio0", "gpio1" }; +static const char * const blsp_i2c1_groups[] = { "gpio2", "gpio3" }; +static const char * const blsp_spi1_groups[] = { + "gpio0", "gpio1", "gpio2", "gpio3" +}; + +static const char * const blsp_uart2_groups[] = { + "gpio4", "gpio5", "gpio6", "gpio7" +}; + +static const char * const blsp_uim2_groups[] = { "gpio4", "gpio5" }; +static const char * const blsp_i2c2_groups[] = { "gpio6", "gpio7" }; +static const char * const blsp_spi2_groups[] = { + "gpio4", "gpio5", "gpio6", "gpio7" +}; + +static const char * const blsp_uart3_groups[] = { + "gpio8", "gpio9", "gpio10", "gpio11" +}; + +static const char * const blsp_uim3_groups[] = { "gpio8", "gpio9" }; +static const char * const blsp_i2c3_groups[] = { "gpio10", "gpio11" }; +static const char * const blsp_spi3_groups[] = { + "gpio8", "gpio9", "gpio10", "gpio11" +}; + +static const char * const blsp_uart4_groups[] = { + "gpio12", "gpio13", "gpio14", "gpio15" +}; + +static const char * const blsp_uim4_groups[] = { "gpio12", "gpio13" }; +static const char * const blsp_i2c4_groups[] = { "gpio14", "gpio15" }; +static const char * const blsp_spi4_groups[] = { + "gpio12", "gpio13", "gpio14", "gpio15" +}; + +static const char * const blsp_uart5_groups[] = { + "gpio16", "gpio17", "gpio18", "gpio19" +}; + +static const char * const blsp_uim5_groups[] = { "gpio16", "gpio17" }; +static const char * const blsp_i2c5_groups[] = { "gpio18", "gpio19" }; +static const char * const blsp_spi5_groups[] = { + "gpio16", "gpio17", "gpio18", "gpio19" +}; + +static const char * const cci_i2c0_groups[] = { "gpio29", "gpio30" }; + +static const char * const cam_mclk0_groups[] = { "gpio26" }; +static const char * const cam_mclk1_groups[] = { "gpio27" }; + +static const char * const gp0_clk_groups[] = { "gpio33" }; +static const char * const gp1_clk_groups[] = { "gpio34" }; + +static const char * const sdc3_groups[] = { + "gpio39", "gpio40", "gpio41", "gpio42", "gpio43", "gpio44" +}; + +static const char * const wlan_groups[] = { + "gpio40", "gpio41", "gpio42", "gpio43", "gpio44" +}; + +static const struct pinfunction msm8226_functions[] = { + MSM_PIN_FUNCTION(audio_pcm), + MSM_PIN_FUNCTION(blsp_i2c1), + MSM_PIN_FUNCTION(blsp_i2c2), + MSM_PIN_FUNCTION(blsp_i2c3), + MSM_PIN_FUNCTION(blsp_i2c4), + MSM_PIN_FUNCTION(blsp_i2c5), + MSM_PIN_FUNCTION(blsp_spi1), + MSM_PIN_FUNCTION(blsp_spi2), + MSM_PIN_FUNCTION(blsp_spi3), + MSM_PIN_FUNCTION(blsp_spi4), + MSM_PIN_FUNCTION(blsp_spi5), + MSM_PIN_FUNCTION(blsp_uart1), + MSM_PIN_FUNCTION(blsp_uart2), + MSM_PIN_FUNCTION(blsp_uart3), + MSM_PIN_FUNCTION(blsp_uart4), + MSM_PIN_FUNCTION(blsp_uart5), + MSM_PIN_FUNCTION(blsp_uim1), + MSM_PIN_FUNCTION(blsp_uim2), + MSM_PIN_FUNCTION(blsp_uim3), + MSM_PIN_FUNCTION(blsp_uim4), + MSM_PIN_FUNCTION(blsp_uim5), + MSM_PIN_FUNCTION(cam_mclk0), + MSM_PIN_FUNCTION(cam_mclk1), + MSM_PIN_FUNCTION(cci_i2c0), + MSM_PIN_FUNCTION(gp0_clk), + MSM_PIN_FUNCTION(gp1_clk), + MSM_PIN_FUNCTION(gpio), + MSM_PIN_FUNCTION(sdc3), + MSM_PIN_FUNCTION(wlan), +}; + +static const struct msm_pingroup msm8226_groups[] = { + PINGROUP(0, blsp_spi1, blsp_uart1, blsp_uim1, NA, NA, NA, NA), + PINGROUP(1, blsp_spi1, blsp_uart1, blsp_uim1, NA, NA, NA, NA), + PINGROUP(2, blsp_spi1, blsp_uart1, blsp_i2c1, NA, NA, NA, NA), + PINGROUP(3, blsp_spi1, blsp_uart1, blsp_i2c1, NA, NA, NA, NA), + PINGROUP(4, blsp_spi2, blsp_uart2, blsp_uim2, NA, NA, NA, NA), + PINGROUP(5, blsp_spi2, blsp_uart2, blsp_uim2, NA, NA, NA, NA), + PINGROUP(6, blsp_spi2, blsp_uart2, blsp_i2c2, NA, NA, NA, NA), + PINGROUP(7, blsp_spi2, blsp_uart2, blsp_i2c2, NA, NA, NA, NA), + PINGROUP(8, blsp_spi3, blsp_uart3, blsp_uim3, NA, NA, NA, NA), + PINGROUP(9, blsp_spi3, blsp_uart3, blsp_uim3, NA, NA, NA, NA), + PINGROUP(10, blsp_spi3, blsp_uart3, blsp_i2c3, NA, NA, NA, NA), + PINGROUP(11, blsp_spi3, blsp_uart3, blsp_i2c3, NA, NA, NA, NA), + PINGROUP(12, blsp_spi4, blsp_uart4, blsp_uim4, NA, NA, NA, NA), + PINGROUP(13, blsp_spi4, blsp_uart4, blsp_uim4, NA, NA, NA, NA), + PINGROUP(14, blsp_spi4, blsp_uart4, blsp_i2c4, NA, NA, NA, NA), + PINGROUP(15, blsp_spi4, blsp_uart4, blsp_i2c4, NA, NA, NA, NA), + PINGROUP(16, blsp_spi5, blsp_uart5, blsp_uim5, NA, NA, NA, NA), + PINGROUP(17, blsp_spi5, blsp_uart5, blsp_uim5, NA, NA, NA, NA), + PINGROUP(18, blsp_spi5, blsp_uart5, blsp_i2c5, NA, NA, NA, NA), + PINGROUP(19, blsp_spi5, blsp_uart5, blsp_i2c5, NA, NA, NA, NA), + PINGROUP(20, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(21, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(22, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(23, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(24, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(25, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(26, cam_mclk0, NA, NA, NA, NA, NA, NA), + PINGROUP(27, cam_mclk1, NA, NA, NA, NA, NA, NA), + PINGROUP(28, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(29, cci_i2c0, NA, NA, NA, NA, NA, NA), + PINGROUP(30, cci_i2c0, NA, NA, NA, NA, NA, NA), + PINGROUP(31, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(32, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(33, NA, NA, gp0_clk, NA, NA, NA, NA), + PINGROUP(34, NA, NA, gp1_clk, NA, NA, NA, NA), + PINGROUP(35, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(36, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(37, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(38, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(39, NA, sdc3, NA, NA, NA, NA, NA), + PINGROUP(40, wlan, sdc3, NA, NA, NA, NA, NA), + PINGROUP(41, wlan, sdc3, NA, NA, NA, NA, NA), + PINGROUP(42, wlan, sdc3, NA, NA, NA, NA, NA), + PINGROUP(43, wlan, sdc3, NA, NA, NA, NA, NA), + PINGROUP(44, wlan, sdc3, NA, NA, NA, NA, NA), + PINGROUP(45, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(46, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(47, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(48, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(49, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(50, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(51, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(52, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(53, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(54, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(55, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(56, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(57, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(58, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(59, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(60, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(61, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(62, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(63, audio_pcm, NA, NA, NA, NA, NA, NA), + PINGROUP(64, audio_pcm, NA, NA, NA, NA, NA, NA), + PINGROUP(65, audio_pcm, NA, NA, NA, NA, NA, NA), + PINGROUP(66, audio_pcm, NA, NA, NA, NA, NA, NA), + PINGROUP(67, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(68, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(69, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(70, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(71, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(72, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(73, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(74, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(75, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(76, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(77, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(78, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(79, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(80, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(81, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(82, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(83, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(84, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(85, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(86, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(87, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(88, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(89, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(90, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(91, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(92, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(93, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(94, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(95, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(96, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(97, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(98, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(99, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(100, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(101, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(102, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(103, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(104, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(105, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(106, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(107, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(108, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(109, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(110, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(111, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(112, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(113, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(114, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(115, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(116, NA, NA, NA, NA, NA, NA, NA), + SDC_PINGROUP(sdc1_clk, 0x2044, 13, 6), + SDC_PINGROUP(sdc1_cmd, 0x2044, 11, 3), + SDC_PINGROUP(sdc1_data, 0x2044, 9, 0), + SDC_PINGROUP(sdc2_clk, 0x2048, 14, 6), + SDC_PINGROUP(sdc2_cmd, 0x2048, 11, 3), + SDC_PINGROUP(sdc2_data, 0x2048, 9, 0), +}; + +#define NUM_GPIO_PINGROUPS 117 + +static const struct msm_pinctrl_soc_data msm8226_pinctrl = { + .pins = msm8226_pins, + .npins = ARRAY_SIZE(msm8226_pins), + .functions = msm8226_functions, + .nfunctions = ARRAY_SIZE(msm8226_functions), + .groups = msm8226_groups, + .ngroups = ARRAY_SIZE(msm8226_groups), + .ngpios = NUM_GPIO_PINGROUPS, +}; + +static int msm8226_pinctrl_probe(struct platform_device *pdev) +{ + return msm_pinctrl_probe(pdev, &msm8226_pinctrl); +} + +static const struct of_device_id msm8226_pinctrl_of_match[] = { + { .compatible = "qcom,msm8226-pinctrl", }, + { }, +}; + +static struct platform_driver msm8226_pinctrl_driver = { + .driver = { + .name = "msm8226-pinctrl", + .of_match_table = msm8226_pinctrl_of_match, + }, + .probe = msm8226_pinctrl_probe, + .remove = msm_pinctrl_remove, +}; + +static int __init msm8226_pinctrl_init(void) +{ + return platform_driver_register(&msm8226_pinctrl_driver); +} +arch_initcall(msm8226_pinctrl_init); + +static void __exit msm8226_pinctrl_exit(void) +{ + platform_driver_unregister(&msm8226_pinctrl_driver); +} +module_exit(msm8226_pinctrl_exit); + +MODULE_AUTHOR("Bartosz Dudziak <bartosz.dudziak@snejp.pl>"); +MODULE_DESCRIPTION("Qualcomm MSM8226 pinctrl driver"); +MODULE_LICENSE("GPL v2"); +MODULE_DEVICE_TABLE(of, msm8226_pinctrl_of_match); diff --git a/drivers/pinctrl/qcom/pinctrl-msm8660.c b/drivers/pinctrl/qcom/pinctrl-msm8660.c new file mode 100644 index 0000000000..999a5f867e --- /dev/null +++ b/drivers/pinctrl/qcom/pinctrl-msm8660.c @@ -0,0 +1,1002 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2015, Sony Mobile Communications AB. + */ + +#include <linux/module.h> +#include <linux/of.h> +#include <linux/platform_device.h> + +#include "pinctrl-msm.h" + +static const struct pinctrl_pin_desc msm8660_pins[] = { + PINCTRL_PIN(0, "GPIO_0"), + PINCTRL_PIN(1, "GPIO_1"), + PINCTRL_PIN(2, "GPIO_2"), + PINCTRL_PIN(3, "GPIO_3"), + PINCTRL_PIN(4, "GPIO_4"), + PINCTRL_PIN(5, "GPIO_5"), + PINCTRL_PIN(6, "GPIO_6"), + PINCTRL_PIN(7, "GPIO_7"), + PINCTRL_PIN(8, "GPIO_8"), + PINCTRL_PIN(9, "GPIO_9"), + PINCTRL_PIN(10, "GPIO_10"), + PINCTRL_PIN(11, "GPIO_11"), + PINCTRL_PIN(12, "GPIO_12"), + PINCTRL_PIN(13, "GPIO_13"), + PINCTRL_PIN(14, "GPIO_14"), + PINCTRL_PIN(15, "GPIO_15"), + PINCTRL_PIN(16, "GPIO_16"), + PINCTRL_PIN(17, "GPIO_17"), + PINCTRL_PIN(18, "GPIO_18"), + PINCTRL_PIN(19, "GPIO_19"), + PINCTRL_PIN(20, "GPIO_20"), + PINCTRL_PIN(21, "GPIO_21"), + PINCTRL_PIN(22, "GPIO_22"), + PINCTRL_PIN(23, "GPIO_23"), + PINCTRL_PIN(24, "GPIO_24"), + PINCTRL_PIN(25, "GPIO_25"), + PINCTRL_PIN(26, "GPIO_26"), + PINCTRL_PIN(27, "GPIO_27"), + PINCTRL_PIN(28, "GPIO_28"), + PINCTRL_PIN(29, "GPIO_29"), + PINCTRL_PIN(30, "GPIO_30"), + PINCTRL_PIN(31, "GPIO_31"), + PINCTRL_PIN(32, "GPIO_32"), + PINCTRL_PIN(33, "GPIO_33"), + PINCTRL_PIN(34, "GPIO_34"), + PINCTRL_PIN(35, "GPIO_35"), + PINCTRL_PIN(36, "GPIO_36"), + PINCTRL_PIN(37, "GPIO_37"), + PINCTRL_PIN(38, "GPIO_38"), + PINCTRL_PIN(39, "GPIO_39"), + PINCTRL_PIN(40, "GPIO_40"), + PINCTRL_PIN(41, "GPIO_41"), + PINCTRL_PIN(42, "GPIO_42"), + PINCTRL_PIN(43, "GPIO_43"), + PINCTRL_PIN(44, "GPIO_44"), + PINCTRL_PIN(45, "GPIO_45"), + PINCTRL_PIN(46, "GPIO_46"), + PINCTRL_PIN(47, "GPIO_47"), + PINCTRL_PIN(48, "GPIO_48"), + PINCTRL_PIN(49, "GPIO_49"), + PINCTRL_PIN(50, "GPIO_50"), + PINCTRL_PIN(51, "GPIO_51"), + PINCTRL_PIN(52, "GPIO_52"), + PINCTRL_PIN(53, "GPIO_53"), + PINCTRL_PIN(54, "GPIO_54"), + PINCTRL_PIN(55, "GPIO_55"), + PINCTRL_PIN(56, "GPIO_56"), + PINCTRL_PIN(57, "GPIO_57"), + PINCTRL_PIN(58, "GPIO_58"), + PINCTRL_PIN(59, "GPIO_59"), + PINCTRL_PIN(60, "GPIO_60"), + PINCTRL_PIN(61, "GPIO_61"), + PINCTRL_PIN(62, "GPIO_62"), + PINCTRL_PIN(63, "GPIO_63"), + PINCTRL_PIN(64, "GPIO_64"), + PINCTRL_PIN(65, "GPIO_65"), + PINCTRL_PIN(66, "GPIO_66"), + PINCTRL_PIN(67, "GPIO_67"), + PINCTRL_PIN(68, "GPIO_68"), + PINCTRL_PIN(69, "GPIO_69"), + PINCTRL_PIN(70, "GPIO_70"), + PINCTRL_PIN(71, "GPIO_71"), + PINCTRL_PIN(72, "GPIO_72"), + PINCTRL_PIN(73, "GPIO_73"), + PINCTRL_PIN(74, "GPIO_74"), + PINCTRL_PIN(75, "GPIO_75"), + PINCTRL_PIN(76, "GPIO_76"), + PINCTRL_PIN(77, "GPIO_77"), + PINCTRL_PIN(78, "GPIO_78"), + PINCTRL_PIN(79, "GPIO_79"), + PINCTRL_PIN(80, "GPIO_80"), + PINCTRL_PIN(81, "GPIO_81"), + PINCTRL_PIN(82, "GPIO_82"), + PINCTRL_PIN(83, "GPIO_83"), + PINCTRL_PIN(84, "GPIO_84"), + PINCTRL_PIN(85, "GPIO_85"), + PINCTRL_PIN(86, "GPIO_86"), + PINCTRL_PIN(87, "GPIO_87"), + PINCTRL_PIN(88, "GPIO_88"), + PINCTRL_PIN(89, "GPIO_89"), + PINCTRL_PIN(90, "GPIO_90"), + PINCTRL_PIN(91, "GPIO_91"), + PINCTRL_PIN(92, "GPIO_92"), + PINCTRL_PIN(93, "GPIO_93"), + PINCTRL_PIN(94, "GPIO_94"), + PINCTRL_PIN(95, "GPIO_95"), + PINCTRL_PIN(96, "GPIO_96"), + PINCTRL_PIN(97, "GPIO_97"), + PINCTRL_PIN(98, "GPIO_98"), + PINCTRL_PIN(99, "GPIO_99"), + PINCTRL_PIN(100, "GPIO_100"), + PINCTRL_PIN(101, "GPIO_101"), + PINCTRL_PIN(102, "GPIO_102"), + PINCTRL_PIN(103, "GPIO_103"), + PINCTRL_PIN(104, "GPIO_104"), + PINCTRL_PIN(105, "GPIO_105"), + PINCTRL_PIN(106, "GPIO_106"), + PINCTRL_PIN(107, "GPIO_107"), + PINCTRL_PIN(108, "GPIO_108"), + PINCTRL_PIN(109, "GPIO_109"), + PINCTRL_PIN(110, "GPIO_110"), + PINCTRL_PIN(111, "GPIO_111"), + PINCTRL_PIN(112, "GPIO_112"), + PINCTRL_PIN(113, "GPIO_113"), + PINCTRL_PIN(114, "GPIO_114"), + PINCTRL_PIN(115, "GPIO_115"), + PINCTRL_PIN(116, "GPIO_116"), + PINCTRL_PIN(117, "GPIO_117"), + PINCTRL_PIN(118, "GPIO_118"), + PINCTRL_PIN(119, "GPIO_119"), + PINCTRL_PIN(120, "GPIO_120"), + PINCTRL_PIN(121, "GPIO_121"), + PINCTRL_PIN(122, "GPIO_122"), + PINCTRL_PIN(123, "GPIO_123"), + PINCTRL_PIN(124, "GPIO_124"), + PINCTRL_PIN(125, "GPIO_125"), + PINCTRL_PIN(126, "GPIO_126"), + PINCTRL_PIN(127, "GPIO_127"), + PINCTRL_PIN(128, "GPIO_128"), + PINCTRL_PIN(129, "GPIO_129"), + PINCTRL_PIN(130, "GPIO_130"), + PINCTRL_PIN(131, "GPIO_131"), + PINCTRL_PIN(132, "GPIO_132"), + PINCTRL_PIN(133, "GPIO_133"), + PINCTRL_PIN(134, "GPIO_134"), + PINCTRL_PIN(135, "GPIO_135"), + PINCTRL_PIN(136, "GPIO_136"), + PINCTRL_PIN(137, "GPIO_137"), + PINCTRL_PIN(138, "GPIO_138"), + PINCTRL_PIN(139, "GPIO_139"), + PINCTRL_PIN(140, "GPIO_140"), + PINCTRL_PIN(141, "GPIO_141"), + PINCTRL_PIN(142, "GPIO_142"), + PINCTRL_PIN(143, "GPIO_143"), + PINCTRL_PIN(144, "GPIO_144"), + PINCTRL_PIN(145, "GPIO_145"), + PINCTRL_PIN(146, "GPIO_146"), + PINCTRL_PIN(147, "GPIO_147"), + PINCTRL_PIN(148, "GPIO_148"), + PINCTRL_PIN(149, "GPIO_149"), + PINCTRL_PIN(150, "GPIO_150"), + PINCTRL_PIN(151, "GPIO_151"), + PINCTRL_PIN(152, "GPIO_152"), + PINCTRL_PIN(153, "GPIO_153"), + PINCTRL_PIN(154, "GPIO_154"), + PINCTRL_PIN(155, "GPIO_155"), + PINCTRL_PIN(156, "GPIO_156"), + PINCTRL_PIN(157, "GPIO_157"), + PINCTRL_PIN(158, "GPIO_158"), + PINCTRL_PIN(159, "GPIO_159"), + PINCTRL_PIN(160, "GPIO_160"), + PINCTRL_PIN(161, "GPIO_161"), + PINCTRL_PIN(162, "GPIO_162"), + PINCTRL_PIN(163, "GPIO_163"), + PINCTRL_PIN(164, "GPIO_164"), + PINCTRL_PIN(165, "GPIO_165"), + PINCTRL_PIN(166, "GPIO_166"), + PINCTRL_PIN(167, "GPIO_167"), + PINCTRL_PIN(168, "GPIO_168"), + PINCTRL_PIN(169, "GPIO_169"), + PINCTRL_PIN(170, "GPIO_170"), + PINCTRL_PIN(171, "GPIO_171"), + PINCTRL_PIN(172, "GPIO_172"), + + PINCTRL_PIN(173, "SDC4_CLK"), + PINCTRL_PIN(174, "SDC4_CMD"), + PINCTRL_PIN(175, "SDC4_DATA"), + PINCTRL_PIN(176, "SDC3_CLK"), + PINCTRL_PIN(177, "SDC3_CMD"), + PINCTRL_PIN(178, "SDC3_DATA"), +}; + +#define DECLARE_MSM_GPIO_PIN(pin) static const unsigned int gpio##pin##_pins[] = { pin } +DECLARE_MSM_GPIO_PIN(0); +DECLARE_MSM_GPIO_PIN(1); +DECLARE_MSM_GPIO_PIN(2); +DECLARE_MSM_GPIO_PIN(3); +DECLARE_MSM_GPIO_PIN(4); +DECLARE_MSM_GPIO_PIN(5); +DECLARE_MSM_GPIO_PIN(6); +DECLARE_MSM_GPIO_PIN(7); +DECLARE_MSM_GPIO_PIN(8); +DECLARE_MSM_GPIO_PIN(9); +DECLARE_MSM_GPIO_PIN(10); +DECLARE_MSM_GPIO_PIN(11); +DECLARE_MSM_GPIO_PIN(12); +DECLARE_MSM_GPIO_PIN(13); +DECLARE_MSM_GPIO_PIN(14); +DECLARE_MSM_GPIO_PIN(15); +DECLARE_MSM_GPIO_PIN(16); +DECLARE_MSM_GPIO_PIN(17); +DECLARE_MSM_GPIO_PIN(18); +DECLARE_MSM_GPIO_PIN(19); +DECLARE_MSM_GPIO_PIN(20); +DECLARE_MSM_GPIO_PIN(21); +DECLARE_MSM_GPIO_PIN(22); +DECLARE_MSM_GPIO_PIN(23); +DECLARE_MSM_GPIO_PIN(24); +DECLARE_MSM_GPIO_PIN(25); +DECLARE_MSM_GPIO_PIN(26); +DECLARE_MSM_GPIO_PIN(27); +DECLARE_MSM_GPIO_PIN(28); +DECLARE_MSM_GPIO_PIN(29); +DECLARE_MSM_GPIO_PIN(30); +DECLARE_MSM_GPIO_PIN(31); +DECLARE_MSM_GPIO_PIN(32); +DECLARE_MSM_GPIO_PIN(33); +DECLARE_MSM_GPIO_PIN(34); +DECLARE_MSM_GPIO_PIN(35); +DECLARE_MSM_GPIO_PIN(36); +DECLARE_MSM_GPIO_PIN(37); +DECLARE_MSM_GPIO_PIN(38); +DECLARE_MSM_GPIO_PIN(39); +DECLARE_MSM_GPIO_PIN(40); +DECLARE_MSM_GPIO_PIN(41); +DECLARE_MSM_GPIO_PIN(42); +DECLARE_MSM_GPIO_PIN(43); +DECLARE_MSM_GPIO_PIN(44); +DECLARE_MSM_GPIO_PIN(45); +DECLARE_MSM_GPIO_PIN(46); +DECLARE_MSM_GPIO_PIN(47); +DECLARE_MSM_GPIO_PIN(48); +DECLARE_MSM_GPIO_PIN(49); +DECLARE_MSM_GPIO_PIN(50); +DECLARE_MSM_GPIO_PIN(51); +DECLARE_MSM_GPIO_PIN(52); +DECLARE_MSM_GPIO_PIN(53); +DECLARE_MSM_GPIO_PIN(54); +DECLARE_MSM_GPIO_PIN(55); +DECLARE_MSM_GPIO_PIN(56); +DECLARE_MSM_GPIO_PIN(57); +DECLARE_MSM_GPIO_PIN(58); +DECLARE_MSM_GPIO_PIN(59); +DECLARE_MSM_GPIO_PIN(60); +DECLARE_MSM_GPIO_PIN(61); +DECLARE_MSM_GPIO_PIN(62); +DECLARE_MSM_GPIO_PIN(63); +DECLARE_MSM_GPIO_PIN(64); +DECLARE_MSM_GPIO_PIN(65); +DECLARE_MSM_GPIO_PIN(66); +DECLARE_MSM_GPIO_PIN(67); +DECLARE_MSM_GPIO_PIN(68); +DECLARE_MSM_GPIO_PIN(69); +DECLARE_MSM_GPIO_PIN(70); +DECLARE_MSM_GPIO_PIN(71); +DECLARE_MSM_GPIO_PIN(72); +DECLARE_MSM_GPIO_PIN(73); +DECLARE_MSM_GPIO_PIN(74); +DECLARE_MSM_GPIO_PIN(75); +DECLARE_MSM_GPIO_PIN(76); +DECLARE_MSM_GPIO_PIN(77); +DECLARE_MSM_GPIO_PIN(78); +DECLARE_MSM_GPIO_PIN(79); +DECLARE_MSM_GPIO_PIN(80); +DECLARE_MSM_GPIO_PIN(81); +DECLARE_MSM_GPIO_PIN(82); +DECLARE_MSM_GPIO_PIN(83); +DECLARE_MSM_GPIO_PIN(84); +DECLARE_MSM_GPIO_PIN(85); +DECLARE_MSM_GPIO_PIN(86); +DECLARE_MSM_GPIO_PIN(87); +DECLARE_MSM_GPIO_PIN(88); +DECLARE_MSM_GPIO_PIN(89); +DECLARE_MSM_GPIO_PIN(90); +DECLARE_MSM_GPIO_PIN(91); +DECLARE_MSM_GPIO_PIN(92); +DECLARE_MSM_GPIO_PIN(93); +DECLARE_MSM_GPIO_PIN(94); +DECLARE_MSM_GPIO_PIN(95); +DECLARE_MSM_GPIO_PIN(96); +DECLARE_MSM_GPIO_PIN(97); +DECLARE_MSM_GPIO_PIN(98); +DECLARE_MSM_GPIO_PIN(99); +DECLARE_MSM_GPIO_PIN(100); +DECLARE_MSM_GPIO_PIN(101); +DECLARE_MSM_GPIO_PIN(102); +DECLARE_MSM_GPIO_PIN(103); +DECLARE_MSM_GPIO_PIN(104); +DECLARE_MSM_GPIO_PIN(105); +DECLARE_MSM_GPIO_PIN(106); +DECLARE_MSM_GPIO_PIN(107); +DECLARE_MSM_GPIO_PIN(108); +DECLARE_MSM_GPIO_PIN(109); +DECLARE_MSM_GPIO_PIN(110); +DECLARE_MSM_GPIO_PIN(111); +DECLARE_MSM_GPIO_PIN(112); +DECLARE_MSM_GPIO_PIN(113); +DECLARE_MSM_GPIO_PIN(114); +DECLARE_MSM_GPIO_PIN(115); +DECLARE_MSM_GPIO_PIN(116); +DECLARE_MSM_GPIO_PIN(117); +DECLARE_MSM_GPIO_PIN(118); +DECLARE_MSM_GPIO_PIN(119); +DECLARE_MSM_GPIO_PIN(120); +DECLARE_MSM_GPIO_PIN(121); +DECLARE_MSM_GPIO_PIN(122); +DECLARE_MSM_GPIO_PIN(123); +DECLARE_MSM_GPIO_PIN(124); +DECLARE_MSM_GPIO_PIN(125); +DECLARE_MSM_GPIO_PIN(126); +DECLARE_MSM_GPIO_PIN(127); +DECLARE_MSM_GPIO_PIN(128); +DECLARE_MSM_GPIO_PIN(129); +DECLARE_MSM_GPIO_PIN(130); +DECLARE_MSM_GPIO_PIN(131); +DECLARE_MSM_GPIO_PIN(132); +DECLARE_MSM_GPIO_PIN(133); +DECLARE_MSM_GPIO_PIN(134); +DECLARE_MSM_GPIO_PIN(135); +DECLARE_MSM_GPIO_PIN(136); +DECLARE_MSM_GPIO_PIN(137); +DECLARE_MSM_GPIO_PIN(138); +DECLARE_MSM_GPIO_PIN(139); +DECLARE_MSM_GPIO_PIN(140); +DECLARE_MSM_GPIO_PIN(141); +DECLARE_MSM_GPIO_PIN(142); +DECLARE_MSM_GPIO_PIN(143); +DECLARE_MSM_GPIO_PIN(144); +DECLARE_MSM_GPIO_PIN(145); +DECLARE_MSM_GPIO_PIN(146); +DECLARE_MSM_GPIO_PIN(147); +DECLARE_MSM_GPIO_PIN(148); +DECLARE_MSM_GPIO_PIN(149); +DECLARE_MSM_GPIO_PIN(150); +DECLARE_MSM_GPIO_PIN(151); +DECLARE_MSM_GPIO_PIN(152); +DECLARE_MSM_GPIO_PIN(153); +DECLARE_MSM_GPIO_PIN(154); +DECLARE_MSM_GPIO_PIN(155); +DECLARE_MSM_GPIO_PIN(156); +DECLARE_MSM_GPIO_PIN(157); +DECLARE_MSM_GPIO_PIN(158); +DECLARE_MSM_GPIO_PIN(159); +DECLARE_MSM_GPIO_PIN(160); +DECLARE_MSM_GPIO_PIN(161); +DECLARE_MSM_GPIO_PIN(162); +DECLARE_MSM_GPIO_PIN(163); +DECLARE_MSM_GPIO_PIN(164); +DECLARE_MSM_GPIO_PIN(165); +DECLARE_MSM_GPIO_PIN(166); +DECLARE_MSM_GPIO_PIN(167); +DECLARE_MSM_GPIO_PIN(168); +DECLARE_MSM_GPIO_PIN(169); +DECLARE_MSM_GPIO_PIN(170); +DECLARE_MSM_GPIO_PIN(171); +DECLARE_MSM_GPIO_PIN(172); + +static const unsigned int sdc4_clk_pins[] = { 173 }; +static const unsigned int sdc4_cmd_pins[] = { 174 }; +static const unsigned int sdc4_data_pins[] = { 175 }; +static const unsigned int sdc3_clk_pins[] = { 176 }; +static const unsigned int sdc3_cmd_pins[] = { 177 }; +static const unsigned int sdc3_data_pins[] = { 178 }; + +#define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7) \ + { \ + .grp = PINCTRL_PINGROUP("gpio" #id, \ + gpio##id##_pins, \ + ARRAY_SIZE(gpio##id##_pins)), \ + .funcs = (int[]){ \ + msm_mux_gpio, \ + msm_mux_##f1, \ + msm_mux_##f2, \ + msm_mux_##f3, \ + msm_mux_##f4, \ + msm_mux_##f5, \ + msm_mux_##f6, \ + msm_mux_##f7, \ + }, \ + .nfuncs = 8, \ + .ctl_reg = 0x1000 + 0x10 * id, \ + .io_reg = 0x1004 + 0x10 * id, \ + .intr_cfg_reg = 0x1008 + 0x10 * id, \ + .intr_status_reg = 0x100c + 0x10 * id, \ + .intr_target_reg = 0x400 + 0x4 * id, \ + .mux_bit = 2, \ + .pull_bit = 0, \ + .drv_bit = 6, \ + .oe_bit = 9, \ + .in_bit = 0, \ + .out_bit = 1, \ + .intr_enable_bit = 0, \ + .intr_status_bit = 0, \ + .intr_ack_high = 1, \ + .intr_target_bit = 0, \ + .intr_target_kpss_val = 4, \ + .intr_raw_status_bit = 3, \ + .intr_polarity_bit = 1, \ + .intr_detection_bit = 2, \ + .intr_detection_width = 1, \ + } + +#define SDC_PINGROUP(pg_name, ctl, pull, drv) \ + { \ + .grp = PINCTRL_PINGROUP(#pg_name, \ + pg_name##_pins, \ + ARRAY_SIZE(pg_name##_pins)), \ + .ctl_reg = ctl, \ + .io_reg = 0, \ + .intr_cfg_reg = 0, \ + .intr_status_reg = 0, \ + .intr_target_reg = 0, \ + .mux_bit = -1, \ + .pull_bit = pull, \ + .drv_bit = drv, \ + .oe_bit = -1, \ + .in_bit = -1, \ + .out_bit = -1, \ + .intr_enable_bit = -1, \ + .intr_status_bit = -1, \ + .intr_target_bit = -1, \ + .intr_target_kpss_val = -1, \ + .intr_raw_status_bit = -1, \ + .intr_polarity_bit = -1, \ + .intr_detection_bit = -1, \ + .intr_detection_width = -1, \ + } + +enum msm8660_functions { + msm_mux_gpio, + msm_mux_cam_mclk, + msm_mux_dsub, + msm_mux_ext_gps, + msm_mux_gp_clk_0a, + msm_mux_gp_clk_0b, + msm_mux_gp_clk_1a, + msm_mux_gp_clk_1b, + msm_mux_gp_clk_2a, + msm_mux_gp_clk_2b, + msm_mux_gp_mn, + msm_mux_gsbi1, + msm_mux_gsbi1_spi_cs1_n, + msm_mux_gsbi1_spi_cs2a_n, + msm_mux_gsbi1_spi_cs2b_n, + msm_mux_gsbi1_spi_cs3_n, + msm_mux_gsbi2, + msm_mux_gsbi2_spi_cs1_n, + msm_mux_gsbi2_spi_cs2_n, + msm_mux_gsbi2_spi_cs3_n, + msm_mux_gsbi3, + msm_mux_gsbi3_spi_cs1_n, + msm_mux_gsbi3_spi_cs2_n, + msm_mux_gsbi3_spi_cs3_n, + msm_mux_gsbi4, + msm_mux_gsbi5, + msm_mux_gsbi6, + msm_mux_gsbi7, + msm_mux_gsbi8, + msm_mux_gsbi9, + msm_mux_gsbi10, + msm_mux_gsbi11, + msm_mux_gsbi12, + msm_mux_hdmi, + msm_mux_i2s, + msm_mux_lcdc, + msm_mux_mdp_vsync, + msm_mux_mi2s, + msm_mux_pcm, + msm_mux_ps_hold, + msm_mux_sdc1, + msm_mux_sdc2, + msm_mux_sdc5, + msm_mux_tsif1, + msm_mux_tsif2, + msm_mux_usb_fs1, + msm_mux_usb_fs1_oe_n, + msm_mux_usb_fs2, + msm_mux_usb_fs2_oe_n, + msm_mux_vfe, + msm_mux_vsens_alarm, + msm_mux_ebi2cs, + msm_mux_ebi2, + msm_mux__, +}; + +static const char * const gpio_groups[] = { + "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7", + "gpio8", "gpio9", "gpio10", "gpio11", "gpio12", "gpio13", "gpio14", + "gpio15", "gpio16", "gpio17", "gpio18", "gpio19", "gpio20", "gpio21", + "gpio22", "gpio23", "gpio24", "gpio25", "gpio26", "gpio27", "gpio28", + "gpio29", "gpio30", "gpio31", "gpio32", "gpio33", "gpio34", "gpio35", + "gpio36", "gpio37", "gpio38", "gpio39", "gpio40", "gpio41", "gpio42", + "gpio43", "gpio44", "gpio45", "gpio46", "gpio47", "gpio48", "gpio49", + "gpio50", "gpio51", "gpio52", "gpio53", "gpio54", "gpio55", "gpio56", + "gpio57", "gpio58", "gpio59", "gpio60", "gpio61", "gpio62", "gpio63", + "gpio64", "gpio65", "gpio66", "gpio67", "gpio68", "gpio69", "gpio70", + "gpio71", "gpio72", "gpio73", "gpio74", "gpio75", "gpio76", "gpio77", + "gpio78", "gpio79", "gpio80", "gpio81", "gpio82", "gpio83", "gpio84", + "gpio85", "gpio86", "gpio87", "gpio88", "gpio89", "gpio90", "gpio91", + "gpio92", "gpio93", "gpio94", "gpio95", "gpio96", "gpio97", "gpio98", + "gpio99", "gpio100", "gpio101", "gpio102", "gpio103", "gpio104", + "gpio105", "gpio106", "gpio107", "gpio108", "gpio109", "gpio110", + "gpio111", "gpio112", "gpio113", "gpio114", "gpio115", "gpio116", + "gpio117", "gpio118", "gpio119", "gpio120", "gpio121", "gpio122", + "gpio123", "gpio124", "gpio125", "gpio126", "gpio127", "gpio128", + "gpio129", "gpio130", "gpio131", "gpio132", "gpio133", "gpio134", + "gpio135", "gpio136", "gpio137", "gpio138", "gpio139", "gpio140", + "gpio141", "gpio142", "gpio143", "gpio144", "gpio145", "gpio146", + "gpio147", "gpio148", "gpio149", "gpio150", "gpio151", "gpio152", + "gpio153", "gpio154", "gpio155", "gpio156", "gpio157", "gpio158", + "gpio159", "gpio160", "gpio161", "gpio162", "gpio163", "gpio164", + "gpio165", "gpio166", "gpio167", "gpio168", "gpio169", "gpio170", + "gpio171", "gpio172" +}; + +static const char * const cam_mclk_groups[] = { + "gpio32" +}; +static const char * const dsub_groups[] = { + "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7", + "gpio8", "gpio9", "gpio10", "gpio11", "gpio12", "gpio13", "gpio14", + "gpio15", "gpio16", "gpio17", "gpio18", "gpio19", "gpio20", "gpio21", + "gpio22", "gpio23", "gpio24", "gpio25", "gpio26", "gpio27" +}; +static const char * const ext_gps_groups[] = { + "gpio66", "gpio67", "gpio68", "gpio69" +}; +static const char * const gp_clk_0a_groups[] = { + "gpio30" +}; +static const char * const gp_clk_0b_groups[] = { + "gpio115" +}; +static const char * const gp_clk_1a_groups[] = { + "gpio31" +}; +static const char * const gp_clk_1b_groups[] = { + "gpio122" +}; +static const char * const gp_clk_2a_groups[] = { + "gpio103" +}; +static const char * const gp_clk_2b_groups[] = { + "gpio70" +}; +static const char * const gp_mn_groups[] = { + "gpio29" +}; +static const char * const gsbi1_groups[] = { + "gpio33", "gpio34", "gpio35", "gpio36" +}; +static const char * const gsbi1_spi_cs1_n_groups[] = { +}; +static const char * const gsbi1_spi_cs2a_n_groups[] = { +}; +static const char * const gsbi1_spi_cs2b_n_groups[] = { +}; +static const char * const gsbi1_spi_cs3_n_groups[] = { +}; +static const char * const gsbi2_groups[] = { + "gpio37", "gpio38", "gpio39", "gpio40" +}; +static const char * const gsbi2_spi_cs1_n_groups[] = { + "gpio123" +}; +static const char * const gsbi2_spi_cs2_n_groups[] = { + "gpio124" +}; +static const char * const gsbi2_spi_cs3_n_groups[] = { + "gpio125" +}; +static const char * const gsbi3_groups[] = { + "gpio41", "gpio42", "gpio43", "gpio44" +}; +static const char * const gsbi3_spi_cs1_n_groups[] = { + "gpio62" +}; +static const char * const gsbi3_spi_cs2_n_groups[] = { + "gpio45" +}; +static const char * const gsbi3_spi_cs3_n_groups[] = { + "gpio46" +}; +static const char * const gsbi4_groups[] = { + "gpio45", "gpio56", "gpio47", "gpio48" +}; +static const char * const gsbi5_groups[] = { + "gpio49", "gpio50", "gpio51", "gpio52" +}; +static const char * const gsbi6_groups[] = { + "gpio53", "gpio54", "gpio55", "gpio56" +}; +static const char * const gsbi7_groups[] = { + "gpio57", "gpio58", "gpio59", "gpio60" +}; +static const char * const gsbi8_groups[] = { + "gpio62", "gpio63", "gpio64", "gpio65" +}; +static const char * const gsbi9_groups[] = { + "gpio66", "gpio67", "gpio68", "gpio69" +}; +static const char * const gsbi10_groups[] = { + "gpio70", "gpio71", "gpio72", "gpio73" +}; +static const char * const gsbi11_groups[] = { + "gpio103", "gpio104", "gpio105", "gpio106" +}; +static const char * const gsbi12_groups[] = { + "gpio115", "gpio116", "gpio117", "gpio118" +}; +static const char * const hdmi_groups[] = { + "gpio169", "gpio170", "gpio171", "gpio172" +}; +static const char * const i2s_groups[] = { + "gpio108", "gpio109", "gpio110", "gpio115", "gpio116", "gpio117", + "gpio118", "gpio119", "gpio120", "gpio121", "gpio122" +}; +static const char * const lcdc_groups[] = { + "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7", + "gpio8", "gpio9", "gpio10", "gpio11", "gpio12", "gpio13", "gpio14", + "gpio15", "gpio16", "gpio17", "gpio18", "gpio19", "gpio20", "gpio21", + "gpio22", "gpio23", "gpio24", "gpio25", "gpio26", "gpio27" +}; +static const char * const mdp_vsync_groups[] = { + "gpio28", "gpio39", "gpio41" +}; +static const char * const mi2s_groups[] = { + "gpio101", "gpio102", "gpio103", "gpio104", "gpio105", "gpio106", + "gpio107" +}; +static const char * const pcm_groups[] = { + "gpio111", "gpio112", "gpio113", "gpio114" +}; +static const char * const ps_hold_groups[] = { + "gpio92" +}; +static const char * const sdc1_groups[] = { + "gpio159", "gpio160", "gpio161", "gpio162", "gpio163", "gpio164", + "gpio165", "gpio166", "gpio167", "gpio168" +}; +static const char * const sdc2_groups[] = { + "gpio143", "gpio144", "gpio145", "gpio146", "gpio147", "gpio148", + "gpio149", "gpio150", "gpio151", "gpio152" +}; +static const char * const sdc5_groups[] = { + "gpio95", "gpio96", "gpio97", "gpio98", "gpio99", "gpio100" +}; +static const char * const tsif1_groups[] = { + "gpio93", "gpio94", "gpio95", "gpio96" +}; +static const char * const tsif2_groups[] = { + "gpio97", "gpio98", "gpio99", "gpio100" +}; +static const char * const usb_fs1_groups[] = { + "gpio49", "gpio50", "gpio51" +}; +static const char * const usb_fs1_oe_n_groups[] = { + "gpio51" +}; +static const char * const usb_fs2_groups[] = { + "gpio71", "gpio72", "gpio73" +}; +static const char * const usb_fs2_oe_n_groups[] = { + "gpio73" +}; +static const char * const vfe_groups[] = { + "gpio29", "gpio30", "gpio31", "gpio42", "gpio46", "gpio105", "gpio106", + "gpio117" +}; +static const char * const vsens_alarm_groups[] = { + "gpio127" +}; +static const char * const ebi2cs_groups[] = { + "gpio39", /* CS1A */ + "gpio40", /* CS2A */ + "gpio123", /* CS1B */ + "gpio124", /* CS2B */ + "gpio131", /* CS5 */ + "gpio132", /* CS4 */ + "gpio133", /* CS3 */ + "gpio134", /* CS0 */ +}; +static const char * const ebi2_groups[] = { + /* ADDR9 & ADDR8 */ + "gpio37", "gpio38", + /* ADDR7 - ADDR 0 */ + "gpio123", "gpio124", "gpio125", "gpio126", + "gpio127", "gpio128", "gpio129", "gpio130", + /* (muxed address+data) AD15 - AD0 */ + "gpio135", "gpio136", "gpio137", "gpio138", "gpio139", + "gpio140", "gpio141", "gpio142", "gpio143", "gpio144", + "gpio145", "gpio146", "gpio147", "gpio148", "gpio149", + "gpio150", + "gpio151", /* OE output enable */ + "gpio152", /* clock */ + "gpio153", /* ADV */ + "gpio154", /* WAIT (input) */ + "gpio155", /* UB Upper Byte Enable */ + "gpio156", /* LB Lower Byte Enable */ + "gpio157", /* WE Write Enable */ + "gpio158", /* busy */ +}; + +static const struct pinfunction msm8660_functions[] = { + MSM_PIN_FUNCTION(gpio), + MSM_PIN_FUNCTION(cam_mclk), + MSM_PIN_FUNCTION(dsub), + MSM_PIN_FUNCTION(ext_gps), + MSM_PIN_FUNCTION(gp_clk_0a), + MSM_PIN_FUNCTION(gp_clk_0b), + MSM_PIN_FUNCTION(gp_clk_1a), + MSM_PIN_FUNCTION(gp_clk_1b), + MSM_PIN_FUNCTION(gp_clk_2a), + MSM_PIN_FUNCTION(gp_clk_2b), + MSM_PIN_FUNCTION(gp_mn), + MSM_PIN_FUNCTION(gsbi1), + MSM_PIN_FUNCTION(gsbi1_spi_cs1_n), + MSM_PIN_FUNCTION(gsbi1_spi_cs2a_n), + MSM_PIN_FUNCTION(gsbi1_spi_cs2b_n), + MSM_PIN_FUNCTION(gsbi1_spi_cs3_n), + MSM_PIN_FUNCTION(gsbi2), + MSM_PIN_FUNCTION(gsbi2_spi_cs1_n), + MSM_PIN_FUNCTION(gsbi2_spi_cs2_n), + MSM_PIN_FUNCTION(gsbi2_spi_cs3_n), + MSM_PIN_FUNCTION(gsbi3), + MSM_PIN_FUNCTION(gsbi3_spi_cs1_n), + MSM_PIN_FUNCTION(gsbi3_spi_cs2_n), + MSM_PIN_FUNCTION(gsbi3_spi_cs3_n), + MSM_PIN_FUNCTION(gsbi4), + MSM_PIN_FUNCTION(gsbi5), + MSM_PIN_FUNCTION(gsbi6), + MSM_PIN_FUNCTION(gsbi7), + MSM_PIN_FUNCTION(gsbi8), + MSM_PIN_FUNCTION(gsbi9), + MSM_PIN_FUNCTION(gsbi10), + MSM_PIN_FUNCTION(gsbi11), + MSM_PIN_FUNCTION(gsbi12), + MSM_PIN_FUNCTION(hdmi), + MSM_PIN_FUNCTION(i2s), + MSM_PIN_FUNCTION(lcdc), + MSM_PIN_FUNCTION(mdp_vsync), + MSM_PIN_FUNCTION(mi2s), + MSM_PIN_FUNCTION(pcm), + MSM_PIN_FUNCTION(ps_hold), + MSM_PIN_FUNCTION(sdc1), + MSM_PIN_FUNCTION(sdc2), + MSM_PIN_FUNCTION(sdc5), + MSM_PIN_FUNCTION(tsif1), + MSM_PIN_FUNCTION(tsif2), + MSM_PIN_FUNCTION(usb_fs1), + MSM_PIN_FUNCTION(usb_fs1_oe_n), + MSM_PIN_FUNCTION(usb_fs2), + MSM_PIN_FUNCTION(usb_fs2_oe_n), + MSM_PIN_FUNCTION(vfe), + MSM_PIN_FUNCTION(vsens_alarm), + MSM_PIN_FUNCTION(ebi2cs), /* for EBI2 chip selects */ + MSM_PIN_FUNCTION(ebi2), /* for general EBI2 pins */ +}; + +static const struct msm_pingroup msm8660_groups[] = { + PINGROUP(0, lcdc, dsub, _, _, _, _, _), + PINGROUP(1, lcdc, dsub, _, _, _, _, _), + PINGROUP(2, lcdc, dsub, _, _, _, _, _), + PINGROUP(3, lcdc, dsub, _, _, _, _, _), + PINGROUP(4, lcdc, dsub, _, _, _, _, _), + PINGROUP(5, lcdc, dsub, _, _, _, _, _), + PINGROUP(6, lcdc, dsub, _, _, _, _, _), + PINGROUP(7, lcdc, dsub, _, _, _, _, _), + PINGROUP(8, lcdc, dsub, _, _, _, _, _), + PINGROUP(9, lcdc, dsub, _, _, _, _, _), + PINGROUP(10, lcdc, dsub, _, _, _, _, _), + PINGROUP(11, lcdc, dsub, _, _, _, _, _), + PINGROUP(12, lcdc, dsub, _, _, _, _, _), + PINGROUP(13, lcdc, dsub, _, _, _, _, _), + PINGROUP(14, lcdc, dsub, _, _, _, _, _), + PINGROUP(15, lcdc, dsub, _, _, _, _, _), + PINGROUP(16, lcdc, dsub, _, _, _, _, _), + PINGROUP(17, lcdc, dsub, _, _, _, _, _), + PINGROUP(18, lcdc, dsub, _, _, _, _, _), + PINGROUP(19, lcdc, dsub, _, _, _, _, _), + PINGROUP(20, lcdc, dsub, _, _, _, _, _), + PINGROUP(21, lcdc, dsub, _, _, _, _, _), + PINGROUP(22, lcdc, dsub, _, _, _, _, _), + PINGROUP(23, lcdc, dsub, _, _, _, _, _), + PINGROUP(24, lcdc, dsub, _, _, _, _, _), + PINGROUP(25, lcdc, dsub, _, _, _, _, _), + PINGROUP(26, lcdc, dsub, _, _, _, _, _), + PINGROUP(27, lcdc, dsub, _, _, _, _, _), + PINGROUP(28, mdp_vsync, _, _, _, _, _, _), + PINGROUP(29, vfe, gp_mn, _, _, _, _, _), + PINGROUP(30, vfe, gp_clk_0a, _, _, _, _, _), + PINGROUP(31, vfe, gp_clk_1a, _, _, _, _, _), + PINGROUP(32, cam_mclk, _, _, _, _, _, _), + PINGROUP(33, gsbi1, _, _, _, _, _, _), + PINGROUP(34, gsbi1, _, _, _, _, _, _), + PINGROUP(35, gsbi1, _, _, _, _, _, _), + PINGROUP(36, gsbi1, _, _, _, _, _, _), + PINGROUP(37, gsbi2, ebi2, _, _, _, _, _), + PINGROUP(38, gsbi2, ebi2, _, _, _, _, _), + PINGROUP(39, gsbi2, ebi2cs, mdp_vsync, _, _, _, _), + PINGROUP(40, gsbi2, ebi2cs, _, _, _, _, _), + PINGROUP(41, gsbi3, mdp_vsync, _, _, _, _, _), + PINGROUP(42, gsbi3, vfe, _, _, _, _, _), + PINGROUP(43, gsbi3, _, _, _, _, _, _), + PINGROUP(44, gsbi3, _, _, _, _, _, _), + PINGROUP(45, gsbi4, gsbi3_spi_cs2_n, _, _, _, _, _), + PINGROUP(46, gsbi4, gsbi3_spi_cs3_n, vfe, _, _, _, _), + PINGROUP(47, gsbi4, _, _, _, _, _, _), + PINGROUP(48, gsbi4, _, _, _, _, _, _), + PINGROUP(49, gsbi5, usb_fs1, _, _, _, _, _), + PINGROUP(50, gsbi5, usb_fs1, _, _, _, _, _), + PINGROUP(51, gsbi5, usb_fs1, usb_fs1_oe_n, _, _, _, _), + PINGROUP(52, gsbi5, _, _, _, _, _, _), + PINGROUP(53, gsbi6, _, _, _, _, _, _), + PINGROUP(54, gsbi6, _, _, _, _, _, _), + PINGROUP(55, gsbi6, _, _, _, _, _, _), + PINGROUP(56, gsbi6, _, _, _, _, _, _), + PINGROUP(57, gsbi7, _, _, _, _, _, _), + PINGROUP(58, gsbi7, _, _, _, _, _, _), + PINGROUP(59, gsbi7, _, _, _, _, _, _), + PINGROUP(60, gsbi7, _, _, _, _, _, _), + PINGROUP(61, _, _, _, _, _, _, _), + PINGROUP(62, gsbi8, gsbi3_spi_cs1_n, gsbi1_spi_cs2a_n, _, _, _, _), + PINGROUP(63, gsbi8, gsbi1_spi_cs1_n, _, _, _, _, _), + PINGROUP(64, gsbi8, gsbi1_spi_cs2b_n, _, _, _, _, _), + PINGROUP(65, gsbi8, gsbi1_spi_cs3_n, _, _, _, _, _), + PINGROUP(66, gsbi9, ext_gps, _, _, _, _, _), + PINGROUP(67, gsbi9, ext_gps, _, _, _, _, _), + PINGROUP(68, gsbi9, ext_gps, _, _, _, _, _), + PINGROUP(69, gsbi9, ext_gps, _, _, _, _, _), + PINGROUP(70, gsbi10, gp_clk_2b, _, _, _, _, _), + PINGROUP(71, gsbi10, usb_fs2, _, _, _, _, _), + PINGROUP(72, gsbi10, usb_fs2, _, _, _, _, _), + PINGROUP(73, gsbi10, usb_fs2, usb_fs2_oe_n, _, _, _, _), + PINGROUP(74, _, _, _, _, _, _, _), + PINGROUP(75, _, _, _, _, _, _, _), + PINGROUP(76, _, _, _, _, _, _, _), + PINGROUP(77, _, _, _, _, _, _, _), + PINGROUP(78, _, _, _, _, _, _, _), + PINGROUP(79, _, _, _, _, _, _, _), + PINGROUP(80, _, _, _, _, _, _, _), + PINGROUP(81, _, _, _, _, _, _, _), + PINGROUP(82, _, _, _, _, _, _, _), + PINGROUP(83, _, _, _, _, _, _, _), + PINGROUP(84, _, _, _, _, _, _, _), + PINGROUP(85, _, _, _, _, _, _, _), + PINGROUP(86, _, _, _, _, _, _, _), + PINGROUP(87, _, _, _, _, _, _, _), + PINGROUP(88, _, _, _, _, _, _, _), + PINGROUP(89, _, _, _, _, _, _, _), + PINGROUP(90, _, _, _, _, _, _, _), + PINGROUP(91, _, _, _, _, _, _, _), + PINGROUP(92, ps_hold, _, _, _, _, _, _), + PINGROUP(93, tsif1, _, _, _, _, _, _), + PINGROUP(94, tsif1, _, _, _, _, _, _), + PINGROUP(95, tsif1, sdc5, _, _, _, _, _), + PINGROUP(96, tsif1, sdc5, _, _, _, _, _), + PINGROUP(97, tsif2, sdc5, _, _, _, _, _), + PINGROUP(98, tsif2, sdc5, _, _, _, _, _), + PINGROUP(99, tsif2, sdc5, _, _, _, _, _), + PINGROUP(100, tsif2, sdc5, _, _, _, _, _), + PINGROUP(101, mi2s, _, _, _, _, _, _), + PINGROUP(102, mi2s, _, _, _, _, _, _), + PINGROUP(103, mi2s, gsbi11, gp_clk_2a, _, _, _, _), + PINGROUP(104, mi2s, gsbi11, _, _, _, _, _), + PINGROUP(105, mi2s, gsbi11, vfe, _, _, _, _), + PINGROUP(106, mi2s, gsbi11, vfe, _, _, _, _), + PINGROUP(107, mi2s, _, _, _, _, _, _), + PINGROUP(108, i2s, _, _, _, _, _, _), + PINGROUP(109, i2s, _, _, _, _, _, _), + PINGROUP(110, i2s, _, _, _, _, _, _), + PINGROUP(111, pcm, _, _, _, _, _, _), + PINGROUP(112, pcm, _, _, _, _, _, _), + PINGROUP(113, pcm, _, _, _, _, _, _), + PINGROUP(114, pcm, _, _, _, _, _, _), + PINGROUP(115, i2s, gsbi12, gp_clk_0b, _, _, _, _), + PINGROUP(116, i2s, gsbi12, _, _, _, _, _), + PINGROUP(117, i2s, gsbi12, vfe, _, _, _, _), + PINGROUP(118, i2s, gsbi12, _, _, _, _, _), + PINGROUP(119, i2s, _, _, _, _, _, _), + PINGROUP(120, i2s, _, _, _, _, _, _), + PINGROUP(121, i2s, _, _, _, _, _, _), + PINGROUP(122, i2s, gp_clk_1b, _, _, _, _, _), + PINGROUP(123, ebi2, gsbi2_spi_cs1_n, ebi2cs, _, _, _, _), + PINGROUP(124, ebi2, gsbi2_spi_cs2_n, ebi2cs, _, _, _, _), + PINGROUP(125, ebi2, gsbi2_spi_cs3_n, _, _, _, _, _), + PINGROUP(126, ebi2, _, _, _, _, _, _), + PINGROUP(127, ebi2, vsens_alarm, _, _, _, _, _), + PINGROUP(128, ebi2, _, _, _, _, _, _), + PINGROUP(129, ebi2, _, _, _, _, _, _), + PINGROUP(130, ebi2, _, _, _, _, _, _), + PINGROUP(131, ebi2cs, _, _, _, _, _, _), + PINGROUP(132, ebi2cs, _, _, _, _, _, _), + PINGROUP(133, ebi2cs, _, _, _, _, _, _), + PINGROUP(134, ebi2cs, _, _, _, _, _, _), + PINGROUP(135, ebi2, _, _, _, _, _, _), + PINGROUP(136, ebi2, _, _, _, _, _, _), + PINGROUP(137, ebi2, _, _, _, _, _, _), + PINGROUP(138, ebi2, _, _, _, _, _, _), + PINGROUP(139, ebi2, _, _, _, _, _, _), + PINGROUP(140, ebi2, _, _, _, _, _, _), + PINGROUP(141, ebi2, _, _, _, _, _, _), + PINGROUP(142, ebi2, _, _, _, _, _, _), + PINGROUP(143, ebi2, sdc2, _, _, _, _, _), + PINGROUP(144, ebi2, sdc2, _, _, _, _, _), + PINGROUP(145, ebi2, sdc2, _, _, _, _, _), + PINGROUP(146, ebi2, sdc2, _, _, _, _, _), + PINGROUP(147, ebi2, sdc2, _, _, _, _, _), + PINGROUP(148, ebi2, sdc2, _, _, _, _, _), + PINGROUP(149, ebi2, sdc2, _, _, _, _, _), + PINGROUP(150, ebi2, sdc2, _, _, _, _, _), + PINGROUP(151, ebi2, sdc2, _, _, _, _, _), + PINGROUP(152, ebi2, sdc2, _, _, _, _, _), + PINGROUP(153, ebi2, _, _, _, _, _, _), + PINGROUP(154, ebi2, _, _, _, _, _, _), + PINGROUP(155, ebi2, _, _, _, _, _, _), + PINGROUP(156, ebi2, _, _, _, _, _, _), + PINGROUP(157, ebi2, _, _, _, _, _, _), + PINGROUP(158, ebi2, _, _, _, _, _, _), + PINGROUP(159, sdc1, _, _, _, _, _, _), + PINGROUP(160, sdc1, _, _, _, _, _, _), + PINGROUP(161, sdc1, _, _, _, _, _, _), + PINGROUP(162, sdc1, _, _, _, _, _, _), + PINGROUP(163, sdc1, _, _, _, _, _, _), + PINGROUP(164, sdc1, _, _, _, _, _, _), + PINGROUP(165, sdc1, _, _, _, _, _, _), + PINGROUP(166, sdc1, _, _, _, _, _, _), + PINGROUP(167, sdc1, _, _, _, _, _, _), + PINGROUP(168, sdc1, _, _, _, _, _, _), + PINGROUP(169, hdmi, _, _, _, _, _, _), + PINGROUP(170, hdmi, _, _, _, _, _, _), + PINGROUP(171, hdmi, _, _, _, _, _, _), + PINGROUP(172, hdmi, _, _, _, _, _, _), + + SDC_PINGROUP(sdc4_clk, 0x20a0, -1, 6), + SDC_PINGROUP(sdc4_cmd, 0x20a0, 11, 3), + SDC_PINGROUP(sdc4_data, 0x20a0, 9, 0), + + SDC_PINGROUP(sdc3_clk, 0x20a4, -1, 6), + SDC_PINGROUP(sdc3_cmd, 0x20a4, 11, 3), + SDC_PINGROUP(sdc3_data, 0x20a4, 9, 0), +}; + +#define NUM_GPIO_PINGROUPS 173 + +static const struct msm_pinctrl_soc_data msm8660_pinctrl = { + .pins = msm8660_pins, + .npins = ARRAY_SIZE(msm8660_pins), + .functions = msm8660_functions, + .nfunctions = ARRAY_SIZE(msm8660_functions), + .groups = msm8660_groups, + .ngroups = ARRAY_SIZE(msm8660_groups), + .ngpios = NUM_GPIO_PINGROUPS, +}; + +static int msm8660_pinctrl_probe(struct platform_device *pdev) +{ + return msm_pinctrl_probe(pdev, &msm8660_pinctrl); +} + +static const struct of_device_id msm8660_pinctrl_of_match[] = { + { .compatible = "qcom,msm8660-pinctrl", }, + { }, +}; + +static struct platform_driver msm8660_pinctrl_driver = { + .driver = { + .name = "msm8660-pinctrl", + .of_match_table = msm8660_pinctrl_of_match, + }, + .probe = msm8660_pinctrl_probe, + .remove = msm_pinctrl_remove, +}; + +static int __init msm8660_pinctrl_init(void) +{ + return platform_driver_register(&msm8660_pinctrl_driver); +} +arch_initcall(msm8660_pinctrl_init); + +static void __exit msm8660_pinctrl_exit(void) +{ + platform_driver_unregister(&msm8660_pinctrl_driver); +} +module_exit(msm8660_pinctrl_exit); + +MODULE_AUTHOR("Bjorn Andersson <bjorn.andersson@sonymobile.com>"); +MODULE_DESCRIPTION("Qualcomm MSM8660 pinctrl driver"); +MODULE_LICENSE("GPL v2"); +MODULE_DEVICE_TABLE(of, msm8660_pinctrl_of_match); diff --git a/drivers/pinctrl/qcom/pinctrl-msm8909.c b/drivers/pinctrl/qcom/pinctrl-msm8909.c new file mode 100644 index 0000000000..756856d20d --- /dev/null +++ b/drivers/pinctrl/qcom/pinctrl-msm8909.c @@ -0,0 +1,948 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2016-2018, The Linux Foundation. All rights reserved. + * Copyright (C) 2022, Kernkonzept GmbH. + */ + +#include <linux/module.h> +#include <linux/of.h> +#include <linux/platform_device.h> + +#include "pinctrl-msm.h" + +#define REG_SIZE 0x1000 +#define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7, f8, f9) \ + { \ + .grp = PINCTRL_PINGROUP("gpio" #id, \ + gpio##id##_pins, \ + ARRAY_SIZE(gpio##id##_pins)), \ + .funcs = (int[]){ \ + msm_mux_gpio, \ + msm_mux_##f1, \ + msm_mux_##f2, \ + msm_mux_##f3, \ + msm_mux_##f4, \ + msm_mux_##f5, \ + msm_mux_##f6, \ + msm_mux_##f7, \ + msm_mux_##f8, \ + msm_mux_##f9, \ + }, \ + .nfuncs = 10, \ + .ctl_reg = REG_SIZE * id, \ + .io_reg = 0x4 + REG_SIZE * id, \ + .intr_cfg_reg = 0x8 + REG_SIZE * id, \ + .intr_status_reg = 0xc + REG_SIZE * id, \ + .intr_target_reg = 0x8 + REG_SIZE * id, \ + .mux_bit = 2, \ + .pull_bit = 0, \ + .drv_bit = 6, \ + .oe_bit = 9, \ + .in_bit = 0, \ + .out_bit = 1, \ + .intr_enable_bit = 0, \ + .intr_status_bit = 0, \ + .intr_target_bit = 5, \ + .intr_target_kpss_val = 4, \ + .intr_raw_status_bit = 4, \ + .intr_polarity_bit = 1, \ + .intr_detection_bit = 2, \ + .intr_detection_width = 2, \ + } + +#define SDC_QDSD_PINGROUP(pg_name, ctl, pull, drv) \ + { \ + .grp = PINCTRL_PINGROUP(#pg_name, \ + pg_name##_pins, \ + ARRAY_SIZE(pg_name##_pins)), \ + .ctl_reg = ctl, \ + .io_reg = 0, \ + .intr_cfg_reg = 0, \ + .intr_status_reg = 0, \ + .intr_target_reg = 0, \ + .mux_bit = -1, \ + .pull_bit = pull, \ + .drv_bit = drv, \ + .oe_bit = -1, \ + .in_bit = -1, \ + .out_bit = -1, \ + .intr_enable_bit = -1, \ + .intr_status_bit = -1, \ + .intr_target_bit = -1, \ + .intr_raw_status_bit = -1, \ + .intr_polarity_bit = -1, \ + .intr_detection_bit = -1, \ + .intr_detection_width = -1, \ + } +static const struct pinctrl_pin_desc msm8909_pins[] = { + PINCTRL_PIN(0, "GPIO_0"), + PINCTRL_PIN(1, "GPIO_1"), + PINCTRL_PIN(2, "GPIO_2"), + PINCTRL_PIN(3, "GPIO_3"), + PINCTRL_PIN(4, "GPIO_4"), + PINCTRL_PIN(5, "GPIO_5"), + PINCTRL_PIN(6, "GPIO_6"), + PINCTRL_PIN(7, "GPIO_7"), + PINCTRL_PIN(8, "GPIO_8"), + PINCTRL_PIN(9, "GPIO_9"), + PINCTRL_PIN(10, "GPIO_10"), + PINCTRL_PIN(11, "GPIO_11"), + PINCTRL_PIN(12, "GPIO_12"), + PINCTRL_PIN(13, "GPIO_13"), + PINCTRL_PIN(14, "GPIO_14"), + PINCTRL_PIN(15, "GPIO_15"), + PINCTRL_PIN(16, "GPIO_16"), + PINCTRL_PIN(17, "GPIO_17"), + PINCTRL_PIN(18, "GPIO_18"), + PINCTRL_PIN(19, "GPIO_19"), + PINCTRL_PIN(20, "GPIO_20"), + PINCTRL_PIN(21, "GPIO_21"), + PINCTRL_PIN(22, "GPIO_22"), + PINCTRL_PIN(23, "GPIO_23"), + PINCTRL_PIN(24, "GPIO_24"), + PINCTRL_PIN(25, "GPIO_25"), + PINCTRL_PIN(26, "GPIO_26"), + PINCTRL_PIN(27, "GPIO_27"), + PINCTRL_PIN(28, "GPIO_28"), + PINCTRL_PIN(29, "GPIO_29"), + PINCTRL_PIN(30, "GPIO_30"), + PINCTRL_PIN(31, "GPIO_31"), + PINCTRL_PIN(32, "GPIO_32"), + PINCTRL_PIN(33, "GPIO_33"), + PINCTRL_PIN(34, "GPIO_34"), + PINCTRL_PIN(35, "GPIO_35"), + PINCTRL_PIN(36, "GPIO_36"), + PINCTRL_PIN(37, "GPIO_37"), + PINCTRL_PIN(38, "GPIO_38"), + PINCTRL_PIN(39, "GPIO_39"), + PINCTRL_PIN(40, "GPIO_40"), + PINCTRL_PIN(41, "GPIO_41"), + PINCTRL_PIN(42, "GPIO_42"), + PINCTRL_PIN(43, "GPIO_43"), + PINCTRL_PIN(44, "GPIO_44"), + PINCTRL_PIN(45, "GPIO_45"), + PINCTRL_PIN(46, "GPIO_46"), + PINCTRL_PIN(47, "GPIO_47"), + PINCTRL_PIN(48, "GPIO_48"), + PINCTRL_PIN(49, "GPIO_49"), + PINCTRL_PIN(50, "GPIO_50"), + PINCTRL_PIN(51, "GPIO_51"), + PINCTRL_PIN(52, "GPIO_52"), + PINCTRL_PIN(53, "GPIO_53"), + PINCTRL_PIN(54, "GPIO_54"), + PINCTRL_PIN(55, "GPIO_55"), + PINCTRL_PIN(56, "GPIO_56"), + PINCTRL_PIN(57, "GPIO_57"), + PINCTRL_PIN(58, "GPIO_58"), + PINCTRL_PIN(59, "GPIO_59"), + PINCTRL_PIN(60, "GPIO_60"), + PINCTRL_PIN(61, "GPIO_61"), + PINCTRL_PIN(62, "GPIO_62"), + PINCTRL_PIN(63, "GPIO_63"), + PINCTRL_PIN(64, "GPIO_64"), + PINCTRL_PIN(65, "GPIO_65"), + PINCTRL_PIN(66, "GPIO_66"), + PINCTRL_PIN(67, "GPIO_67"), + PINCTRL_PIN(68, "GPIO_68"), + PINCTRL_PIN(69, "GPIO_69"), + PINCTRL_PIN(70, "GPIO_70"), + PINCTRL_PIN(71, "GPIO_71"), + PINCTRL_PIN(72, "GPIO_72"), + PINCTRL_PIN(73, "GPIO_73"), + PINCTRL_PIN(74, "GPIO_74"), + PINCTRL_PIN(75, "GPIO_75"), + PINCTRL_PIN(76, "GPIO_76"), + PINCTRL_PIN(77, "GPIO_77"), + PINCTRL_PIN(78, "GPIO_78"), + PINCTRL_PIN(79, "GPIO_79"), + PINCTRL_PIN(80, "GPIO_80"), + PINCTRL_PIN(81, "GPIO_81"), + PINCTRL_PIN(82, "GPIO_82"), + PINCTRL_PIN(83, "GPIO_83"), + PINCTRL_PIN(84, "GPIO_84"), + PINCTRL_PIN(85, "GPIO_85"), + PINCTRL_PIN(86, "GPIO_86"), + PINCTRL_PIN(87, "GPIO_87"), + PINCTRL_PIN(88, "GPIO_88"), + PINCTRL_PIN(89, "GPIO_89"), + PINCTRL_PIN(90, "GPIO_90"), + PINCTRL_PIN(91, "GPIO_91"), + PINCTRL_PIN(92, "GPIO_92"), + PINCTRL_PIN(93, "GPIO_93"), + PINCTRL_PIN(94, "GPIO_94"), + PINCTRL_PIN(95, "GPIO_95"), + PINCTRL_PIN(96, "GPIO_96"), + PINCTRL_PIN(97, "GPIO_97"), + PINCTRL_PIN(98, "GPIO_98"), + PINCTRL_PIN(99, "GPIO_99"), + PINCTRL_PIN(100, "GPIO_100"), + PINCTRL_PIN(101, "GPIO_101"), + PINCTRL_PIN(102, "GPIO_102"), + PINCTRL_PIN(103, "GPIO_103"), + PINCTRL_PIN(104, "GPIO_104"), + PINCTRL_PIN(105, "GPIO_105"), + PINCTRL_PIN(106, "GPIO_106"), + PINCTRL_PIN(107, "GPIO_107"), + PINCTRL_PIN(108, "GPIO_108"), + PINCTRL_PIN(109, "GPIO_109"), + PINCTRL_PIN(110, "GPIO_110"), + PINCTRL_PIN(111, "GPIO_111"), + PINCTRL_PIN(112, "GPIO_112"), + PINCTRL_PIN(113, "SDC1_CLK"), + PINCTRL_PIN(114, "SDC1_CMD"), + PINCTRL_PIN(115, "SDC1_DATA"), + PINCTRL_PIN(116, "SDC2_CLK"), + PINCTRL_PIN(117, "SDC2_CMD"), + PINCTRL_PIN(118, "SDC2_DATA"), + PINCTRL_PIN(119, "QDSD_CLK"), + PINCTRL_PIN(120, "QDSD_CMD"), + PINCTRL_PIN(121, "QDSD_DATA0"), + PINCTRL_PIN(122, "QDSD_DATA1"), + PINCTRL_PIN(123, "QDSD_DATA2"), + PINCTRL_PIN(124, "QDSD_DATA3"), +}; + +#define DECLARE_MSM_GPIO_PINS(pin) \ + static const unsigned int gpio##pin##_pins[] = { pin } +DECLARE_MSM_GPIO_PINS(0); +DECLARE_MSM_GPIO_PINS(1); +DECLARE_MSM_GPIO_PINS(2); +DECLARE_MSM_GPIO_PINS(3); +DECLARE_MSM_GPIO_PINS(4); +DECLARE_MSM_GPIO_PINS(5); +DECLARE_MSM_GPIO_PINS(6); +DECLARE_MSM_GPIO_PINS(7); +DECLARE_MSM_GPIO_PINS(8); +DECLARE_MSM_GPIO_PINS(9); +DECLARE_MSM_GPIO_PINS(10); +DECLARE_MSM_GPIO_PINS(11); +DECLARE_MSM_GPIO_PINS(12); +DECLARE_MSM_GPIO_PINS(13); +DECLARE_MSM_GPIO_PINS(14); +DECLARE_MSM_GPIO_PINS(15); +DECLARE_MSM_GPIO_PINS(16); +DECLARE_MSM_GPIO_PINS(17); +DECLARE_MSM_GPIO_PINS(18); +DECLARE_MSM_GPIO_PINS(19); +DECLARE_MSM_GPIO_PINS(20); +DECLARE_MSM_GPIO_PINS(21); +DECLARE_MSM_GPIO_PINS(22); +DECLARE_MSM_GPIO_PINS(23); +DECLARE_MSM_GPIO_PINS(24); +DECLARE_MSM_GPIO_PINS(25); +DECLARE_MSM_GPIO_PINS(26); +DECLARE_MSM_GPIO_PINS(27); +DECLARE_MSM_GPIO_PINS(28); +DECLARE_MSM_GPIO_PINS(29); +DECLARE_MSM_GPIO_PINS(30); +DECLARE_MSM_GPIO_PINS(31); +DECLARE_MSM_GPIO_PINS(32); +DECLARE_MSM_GPIO_PINS(33); +DECLARE_MSM_GPIO_PINS(34); +DECLARE_MSM_GPIO_PINS(35); +DECLARE_MSM_GPIO_PINS(36); +DECLARE_MSM_GPIO_PINS(37); +DECLARE_MSM_GPIO_PINS(38); +DECLARE_MSM_GPIO_PINS(39); +DECLARE_MSM_GPIO_PINS(40); +DECLARE_MSM_GPIO_PINS(41); +DECLARE_MSM_GPIO_PINS(42); +DECLARE_MSM_GPIO_PINS(43); +DECLARE_MSM_GPIO_PINS(44); +DECLARE_MSM_GPIO_PINS(45); +DECLARE_MSM_GPIO_PINS(46); +DECLARE_MSM_GPIO_PINS(47); +DECLARE_MSM_GPIO_PINS(48); +DECLARE_MSM_GPIO_PINS(49); +DECLARE_MSM_GPIO_PINS(50); +DECLARE_MSM_GPIO_PINS(51); +DECLARE_MSM_GPIO_PINS(52); +DECLARE_MSM_GPIO_PINS(53); +DECLARE_MSM_GPIO_PINS(54); +DECLARE_MSM_GPIO_PINS(55); +DECLARE_MSM_GPIO_PINS(56); +DECLARE_MSM_GPIO_PINS(57); +DECLARE_MSM_GPIO_PINS(58); +DECLARE_MSM_GPIO_PINS(59); +DECLARE_MSM_GPIO_PINS(60); +DECLARE_MSM_GPIO_PINS(61); +DECLARE_MSM_GPIO_PINS(62); +DECLARE_MSM_GPIO_PINS(63); +DECLARE_MSM_GPIO_PINS(64); +DECLARE_MSM_GPIO_PINS(65); +DECLARE_MSM_GPIO_PINS(66); +DECLARE_MSM_GPIO_PINS(67); +DECLARE_MSM_GPIO_PINS(68); +DECLARE_MSM_GPIO_PINS(69); +DECLARE_MSM_GPIO_PINS(70); +DECLARE_MSM_GPIO_PINS(71); +DECLARE_MSM_GPIO_PINS(72); +DECLARE_MSM_GPIO_PINS(73); +DECLARE_MSM_GPIO_PINS(74); +DECLARE_MSM_GPIO_PINS(75); +DECLARE_MSM_GPIO_PINS(76); +DECLARE_MSM_GPIO_PINS(77); +DECLARE_MSM_GPIO_PINS(78); +DECLARE_MSM_GPIO_PINS(79); +DECLARE_MSM_GPIO_PINS(80); +DECLARE_MSM_GPIO_PINS(81); +DECLARE_MSM_GPIO_PINS(82); +DECLARE_MSM_GPIO_PINS(83); +DECLARE_MSM_GPIO_PINS(84); +DECLARE_MSM_GPIO_PINS(85); +DECLARE_MSM_GPIO_PINS(86); +DECLARE_MSM_GPIO_PINS(87); +DECLARE_MSM_GPIO_PINS(88); +DECLARE_MSM_GPIO_PINS(89); +DECLARE_MSM_GPIO_PINS(90); +DECLARE_MSM_GPIO_PINS(91); +DECLARE_MSM_GPIO_PINS(92); +DECLARE_MSM_GPIO_PINS(93); +DECLARE_MSM_GPIO_PINS(94); +DECLARE_MSM_GPIO_PINS(95); +DECLARE_MSM_GPIO_PINS(96); +DECLARE_MSM_GPIO_PINS(97); +DECLARE_MSM_GPIO_PINS(98); +DECLARE_MSM_GPIO_PINS(99); +DECLARE_MSM_GPIO_PINS(100); +DECLARE_MSM_GPIO_PINS(101); +DECLARE_MSM_GPIO_PINS(102); +DECLARE_MSM_GPIO_PINS(103); +DECLARE_MSM_GPIO_PINS(104); +DECLARE_MSM_GPIO_PINS(105); +DECLARE_MSM_GPIO_PINS(106); +DECLARE_MSM_GPIO_PINS(107); +DECLARE_MSM_GPIO_PINS(108); +DECLARE_MSM_GPIO_PINS(109); +DECLARE_MSM_GPIO_PINS(110); +DECLARE_MSM_GPIO_PINS(111); +DECLARE_MSM_GPIO_PINS(112); + +static const unsigned int sdc1_clk_pins[] = { 113 }; +static const unsigned int sdc1_cmd_pins[] = { 114 }; +static const unsigned int sdc1_data_pins[] = { 115 }; +static const unsigned int sdc2_clk_pins[] = { 116 }; +static const unsigned int sdc2_cmd_pins[] = { 117 }; +static const unsigned int sdc2_data_pins[] = { 118 }; +static const unsigned int qdsd_clk_pins[] = { 119 }; +static const unsigned int qdsd_cmd_pins[] = { 120 }; +static const unsigned int qdsd_data0_pins[] = { 121 }; +static const unsigned int qdsd_data1_pins[] = { 122 }; +static const unsigned int qdsd_data2_pins[] = { 123 }; +static const unsigned int qdsd_data3_pins[] = { 124 }; + +enum msm8909_functions { + msm_mux_gpio, + msm_mux_adsp_ext, + msm_mux_atest_bbrx0, + msm_mux_atest_bbrx1, + msm_mux_atest_char, + msm_mux_atest_char0, + msm_mux_atest_char1, + msm_mux_atest_char2, + msm_mux_atest_char3, + msm_mux_atest_combodac, + msm_mux_atest_gpsadc0, + msm_mux_atest_gpsadc1, + msm_mux_atest_wlan0, + msm_mux_atest_wlan1, + msm_mux_bimc_dte0, + msm_mux_bimc_dte1, + msm_mux_blsp_i2c1, + msm_mux_blsp_i2c2, + msm_mux_blsp_i2c3, + msm_mux_blsp_i2c4, + msm_mux_blsp_i2c5, + msm_mux_blsp_i2c6, + msm_mux_blsp_spi1, + msm_mux_blsp_spi1_cs1, + msm_mux_blsp_spi1_cs2, + msm_mux_blsp_spi1_cs3, + msm_mux_blsp_spi2, + msm_mux_blsp_spi2_cs1, + msm_mux_blsp_spi2_cs2, + msm_mux_blsp_spi2_cs3, + msm_mux_blsp_spi3, + msm_mux_blsp_spi3_cs1, + msm_mux_blsp_spi3_cs2, + msm_mux_blsp_spi3_cs3, + msm_mux_blsp_spi4, + msm_mux_blsp_spi5, + msm_mux_blsp_spi6, + msm_mux_blsp_uart1, + msm_mux_blsp_uart2, + msm_mux_blsp_uim1, + msm_mux_blsp_uim2, + msm_mux_cam_mclk, + msm_mux_cci_async, + msm_mux_cci_timer0, + msm_mux_cci_timer1, + msm_mux_cci_timer2, + msm_mux_cdc_pdm0, + msm_mux_dbg_out, + msm_mux_dmic0_clk, + msm_mux_dmic0_data, + msm_mux_ebi0_wrcdc, + msm_mux_ebi2_a, + msm_mux_ebi2_lcd, + msm_mux_ext_lpass, + msm_mux_gcc_gp1_clk_a, + msm_mux_gcc_gp1_clk_b, + msm_mux_gcc_gp2_clk_a, + msm_mux_gcc_gp2_clk_b, + msm_mux_gcc_gp3_clk_a, + msm_mux_gcc_gp3_clk_b, + msm_mux_gcc_plltest, + msm_mux_gsm0_tx, + msm_mux_ldo_en, + msm_mux_ldo_update, + msm_mux_m_voc, + msm_mux_mdp_vsync, + msm_mux_modem_tsync, + msm_mux_nav_pps, + msm_mux_nav_tsync, + msm_mux_pa_indicator, + msm_mux_pbs0, + msm_mux_pbs1, + msm_mux_pbs2, + msm_mux_pri_mi2s_data0_a, + msm_mux_pri_mi2s_data0_b, + msm_mux_pri_mi2s_data1_a, + msm_mux_pri_mi2s_data1_b, + msm_mux_pri_mi2s_mclk_a, + msm_mux_pri_mi2s_mclk_b, + msm_mux_pri_mi2s_sck_a, + msm_mux_pri_mi2s_sck_b, + msm_mux_pri_mi2s_ws_a, + msm_mux_pri_mi2s_ws_b, + msm_mux_prng_rosc, + msm_mux_pwr_crypto_enabled_a, + msm_mux_pwr_crypto_enabled_b, + msm_mux_pwr_modem_enabled_a, + msm_mux_pwr_modem_enabled_b, + msm_mux_pwr_nav_enabled_a, + msm_mux_pwr_nav_enabled_b, + msm_mux_qdss_cti_trig_in_a0, + msm_mux_qdss_cti_trig_in_a1, + msm_mux_qdss_cti_trig_in_b0, + msm_mux_qdss_cti_trig_in_b1, + msm_mux_qdss_cti_trig_out_a0, + msm_mux_qdss_cti_trig_out_a1, + msm_mux_qdss_cti_trig_out_b0, + msm_mux_qdss_cti_trig_out_b1, + msm_mux_qdss_traceclk_a, + msm_mux_qdss_tracectl_a, + msm_mux_qdss_tracedata_a, + msm_mux_qdss_tracedata_b, + msm_mux_sd_write, + msm_mux_sec_mi2s, + msm_mux_smb_int, + msm_mux_ssbi0, + msm_mux_ssbi1, + msm_mux_uim1_clk, + msm_mux_uim1_data, + msm_mux_uim1_present, + msm_mux_uim1_reset, + msm_mux_uim2_clk, + msm_mux_uim2_data, + msm_mux_uim2_present, + msm_mux_uim2_reset, + msm_mux_uim3_clk, + msm_mux_uim3_data, + msm_mux_uim3_present, + msm_mux_uim3_reset, + msm_mux_uim_batt, + msm_mux_wcss_bt, + msm_mux_wcss_fm, + msm_mux_wcss_wlan, + msm_mux__, +}; + +static const char * const adsp_ext_groups[] = { "gpio38" }; +static const char * const atest_bbrx0_groups[] = { "gpio37" }; +static const char * const atest_bbrx1_groups[] = { "gpio36" }; +static const char * const atest_char0_groups[] = { "gpio62" }; +static const char * const atest_char1_groups[] = { "gpio61" }; +static const char * const atest_char2_groups[] = { "gpio60" }; +static const char * const atest_char3_groups[] = { "gpio59" }; +static const char * const atest_char_groups[] = { "gpio63" }; +static const char * const atest_combodac_groups[] = { + "gpio32", "gpio38", "gpio39", "gpio40", "gpio41", "gpio42", "gpio43", + "gpio44", "gpio45", "gpio47", "gpio48", "gpio66", "gpio81", "gpio83", + "gpio84", "gpio85", "gpio86", "gpio94", "gpio95", "gpio110" +}; +static const char * const atest_gpsadc0_groups[] = { "gpio65" }; +static const char * const atest_gpsadc1_groups[] = { "gpio79" }; +static const char * const atest_wlan0_groups[] = { "gpio96" }; +static const char * const atest_wlan1_groups[] = { "gpio97" }; +static const char * const bimc_dte0_groups[] = { "gpio6", "gpio59" }; +static const char * const bimc_dte1_groups[] = { "gpio7", "gpio60" }; +static const char * const blsp_i2c1_groups[] = { "gpio6", "gpio7" }; +static const char * const blsp_i2c2_groups[] = { "gpio111", "gpio112" }; +static const char * const blsp_i2c3_groups[] = { "gpio29", "gpio30" }; +static const char * const blsp_i2c4_groups[] = { "gpio14", "gpio15" }; +static const char * const blsp_i2c5_groups[] = { "gpio18", "gpio19" }; +static const char * const blsp_i2c6_groups[] = { "gpio10", "gpio11" }; +static const char * const blsp_spi1_cs1_groups[] = { "gpio97" }; +static const char * const blsp_spi1_cs2_groups[] = { "gpio37" }; +static const char * const blsp_spi1_cs3_groups[] = { "gpio65" }; +static const char * const blsp_spi1_groups[] = { + "gpio4", "gpio5", "gpio6", "gpio7" +}; +static const char * const blsp_spi2_cs1_groups[] = { "gpio98" }; +static const char * const blsp_spi2_cs2_groups[] = { "gpio17" }; +static const char * const blsp_spi2_cs3_groups[] = { "gpio5" }; +static const char * const blsp_spi2_groups[] = { + "gpio20", "gpio21", "gpio111", "gpio112" +}; +static const char * const blsp_spi3_cs1_groups[] = { "gpio95" }; +static const char * const blsp_spi3_cs2_groups[] = { "gpio65" }; +static const char * const blsp_spi3_cs3_groups[] = { "gpio4" }; +static const char * const blsp_spi3_groups[] = { + "gpio0", "gpio1", "gpio2", "gpio3" +}; +static const char * const blsp_spi4_groups[] = { + "gpio12", "gpio13", "gpio14", "gpio15" +}; +static const char * const blsp_spi5_groups[] = { + "gpio16", "gpio17", "gpio18", "gpio19" +}; +static const char * const blsp_spi6_groups[] = { + "gpio8", "gpio9", "gpio10", "gpio11" +}; +static const char * const blsp_uart1_groups[] = { + "gpio4", "gpio5", "gpio6", "gpio7" +}; +static const char * const blsp_uart2_groups[] = { + "gpio20", "gpio21", "gpio111", "gpio112" +}; +static const char * const blsp_uim1_groups[] = { "gpio4", "gpio5" }; +static const char * const blsp_uim2_groups[] = { "gpio20", "gpio21" }; +static const char * const cam_mclk_groups[] = { "gpio26", "gpio27" }; +static const char * const cci_async_groups[] = { "gpio33" }; +static const char * const cci_timer0_groups[] = { "gpio31" }; +static const char * const cci_timer1_groups[] = { "gpio32" }; +static const char * const cci_timer2_groups[] = { "gpio38" }; +static const char * const cdc_pdm0_groups[] = { + "gpio59", "gpio60", "gpio61", "gpio62", "gpio63", "gpio64" +}; +static const char * const dbg_out_groups[] = { "gpio10" }; +static const char * const dmic0_clk_groups[] = { "gpio4" }; +static const char * const dmic0_data_groups[] = { "gpio5" }; +static const char * const ebi0_wrcdc_groups[] = { "gpio64" }; +static const char * const ebi2_a_groups[] = { "gpio99" }; +static const char * const ebi2_lcd_groups[] = { + "gpio24", "gpio24", "gpio25", "gpio95" +}; +static const char * const ext_lpass_groups[] = { "gpio45" }; +static const char * const gcc_gp1_clk_a_groups[] = { "gpio49" }; +static const char * const gcc_gp1_clk_b_groups[] = { "gpio14" }; +static const char * const gcc_gp2_clk_a_groups[] = { "gpio50" }; +static const char * const gcc_gp2_clk_b_groups[] = { "gpio12" }; +static const char * const gcc_gp3_clk_a_groups[] = { "gpio51" }; +static const char * const gcc_gp3_clk_b_groups[] = { "gpio13" }; +static const char * const gcc_plltest_groups[] = { "gpio66", "gpio67" }; +static const char * const gpio_groups[] = { + "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7", + "gpio8", "gpio9", "gpio10", "gpio11", "gpio12", "gpio13", "gpio14", + "gpio15", "gpio16", "gpio17", "gpio18", "gpio19", "gpio20", "gpio21", + "gpio22", "gpio23", "gpio24", "gpio25", "gpio26", "gpio27", "gpio28", + "gpio29", "gpio30", "gpio31", "gpio32", "gpio33", "gpio34", "gpio35", + "gpio36", "gpio37", "gpio38", "gpio39", "gpio40", "gpio41", "gpio42", + "gpio43", "gpio44", "gpio45", "gpio46", "gpio47", "gpio48", "gpio49", + "gpio50", "gpio51", "gpio52", "gpio53", "gpio54", "gpio55", "gpio56", + "gpio57", "gpio58", "gpio59", "gpio60", "gpio61", "gpio62", "gpio63", + "gpio64", "gpio65", "gpio66", "gpio67", "gpio68", "gpio69", "gpio70", + "gpio71", "gpio72", "gpio73", "gpio74", "gpio75", "gpio76", "gpio77", + "gpio78", "gpio79", "gpio80", "gpio81", "gpio82", "gpio83", "gpio84", + "gpio85", "gpio86", "gpio87", "gpio88", "gpio89", "gpio90", "gpio91", + "gpio92", "gpio93", "gpio94", "gpio95", "gpio96", "gpio97", "gpio98", + "gpio99", "gpio100", "gpio101", "gpio102", "gpio103", "gpio104", + "gpio105", "gpio106", "gpio107", "gpio108", "gpio109", "gpio110", + "gpio111", "gpio112" +}; +static const char * const gsm0_tx_groups[] = { "gpio85" }; +static const char * const ldo_en_groups[] = { "gpio99" }; +static const char * const ldo_update_groups[] = { "gpio98" }; +static const char * const m_voc_groups[] = { "gpio8", "gpio95" }; +static const char * const mdp_vsync_groups[] = { "gpio24", "gpio25" }; +static const char * const modem_tsync_groups[] = { "gpio83" }; +static const char * const nav_pps_groups[] = { "gpio83" }; +static const char * const nav_tsync_groups[] = { "gpio83" }; +static const char * const pa_indicator_groups[] = { "gpio82" }; +static const char * const pbs0_groups[] = { "gpio90" }; +static const char * const pbs1_groups[] = { "gpio91" }; +static const char * const pbs2_groups[] = { "gpio92" }; +static const char * const pri_mi2s_data0_a_groups[] = { "gpio62" }; +static const char * const pri_mi2s_data0_b_groups[] = { "gpio95" }; +static const char * const pri_mi2s_data1_a_groups[] = { "gpio63" }; +static const char * const pri_mi2s_data1_b_groups[] = { "gpio96" }; +static const char * const pri_mi2s_mclk_a_groups[] = { "gpio59" }; +static const char * const pri_mi2s_mclk_b_groups[] = { "gpio98" }; +static const char * const pri_mi2s_sck_a_groups[] = { "gpio60" }; +static const char * const pri_mi2s_sck_b_groups[] = { "gpio94" }; +static const char * const pri_mi2s_ws_a_groups[] = { "gpio61" }; +static const char * const pri_mi2s_ws_b_groups[] = { "gpio110" }; +static const char * const prng_rosc_groups[] = { "gpio43" }; +static const char * const pwr_crypto_enabled_a_groups[] = { "gpio35" }; +static const char * const pwr_crypto_enabled_b_groups[] = { "gpio96" }; +static const char * const pwr_modem_enabled_a_groups[] = { "gpio28" }; +static const char * const pwr_modem_enabled_b_groups[] = { "gpio94" }; +static const char * const pwr_nav_enabled_a_groups[] = { "gpio34" }; +static const char * const pwr_nav_enabled_b_groups[] = { "gpio95" }; +static const char * const qdss_cti_trig_in_a0_groups[] = { "gpio20" }; +static const char * const qdss_cti_trig_in_a1_groups[] = { "gpio49" }; +static const char * const qdss_cti_trig_in_b0_groups[] = { "gpio21" }; +static const char * const qdss_cti_trig_in_b1_groups[] = { "gpio50" }; +static const char * const qdss_cti_trig_out_a0_groups[] = { "gpio23" }; +static const char * const qdss_cti_trig_out_a1_groups[] = { "gpio52" }; +static const char * const qdss_cti_trig_out_b0_groups[] = { "gpio22" }; +static const char * const qdss_cti_trig_out_b1_groups[] = { "gpio51" }; +static const char * const qdss_traceclk_a_groups[] = { "gpio46" }; +static const char * const qdss_tracectl_a_groups[] = { "gpio45" }; +static const char * const qdss_tracedata_a_groups[] = { + "gpio8", "gpio9", "gpio10", "gpio39", "gpio40", "gpio41", "gpio42", + "gpio43", "gpio47", "gpio48", "gpio58", "gpio65", "gpio94", "gpio96", + "gpio97" +}; +static const char * const qdss_tracedata_b_groups[] = { + "gpio14", "gpio16", "gpio17", "gpio29", "gpio30", "gpio31", "gpio32", + "gpio33", "gpio34", "gpio35", "gpio36", "gpio37", "gpio93" +}; +static const char * const sd_write_groups[] = { "gpio99" }; +static const char * const sec_mi2s_groups[] = { + "gpio0", "gpio1", "gpio2", "gpio3", "gpio98" +}; +static const char * const smb_int_groups[] = { "gpio58" }; +static const char * const ssbi0_groups[] = { "gpio88" }; +static const char * const ssbi1_groups[] = { "gpio89" }; +static const char * const uim1_clk_groups[] = { "gpio54" }; +static const char * const uim1_data_groups[] = { "gpio53" }; +static const char * const uim1_present_groups[] = { "gpio56" }; +static const char * const uim1_reset_groups[] = { "gpio55" }; +static const char * const uim2_clk_groups[] = { "gpio50" }; +static const char * const uim2_data_groups[] = { "gpio49" }; +static const char * const uim2_present_groups[] = { "gpio52" }; +static const char * const uim2_reset_groups[] = { "gpio51" }; +static const char * const uim3_clk_groups[] = { "gpio23" }; +static const char * const uim3_data_groups[] = { "gpio20" }; +static const char * const uim3_present_groups[] = { "gpio21" }; +static const char * const uim3_reset_groups[] = { "gpio22" }; +static const char * const uim_batt_groups[] = { "gpio57" }; +static const char * const wcss_bt_groups[] = { "gpio39", "gpio47", "gpio48" }; +static const char * const wcss_fm_groups[] = { "gpio45", "gpio46" }; +static const char * const wcss_wlan_groups[] = { + "gpio40", "gpio41", "gpio42", "gpio43", "gpio44" +}; + +static const struct pinfunction msm8909_functions[] = { + MSM_PIN_FUNCTION(adsp_ext), + MSM_PIN_FUNCTION(atest_bbrx0), + MSM_PIN_FUNCTION(atest_bbrx1), + MSM_PIN_FUNCTION(atest_char), + MSM_PIN_FUNCTION(atest_char0), + MSM_PIN_FUNCTION(atest_char1), + MSM_PIN_FUNCTION(atest_char2), + MSM_PIN_FUNCTION(atest_char3), + MSM_PIN_FUNCTION(atest_combodac), + MSM_PIN_FUNCTION(atest_gpsadc0), + MSM_PIN_FUNCTION(atest_gpsadc1), + MSM_PIN_FUNCTION(atest_wlan0), + MSM_PIN_FUNCTION(atest_wlan1), + MSM_PIN_FUNCTION(bimc_dte0), + MSM_PIN_FUNCTION(bimc_dte1), + MSM_PIN_FUNCTION(blsp_i2c1), + MSM_PIN_FUNCTION(blsp_i2c2), + MSM_PIN_FUNCTION(blsp_i2c3), + MSM_PIN_FUNCTION(blsp_i2c4), + MSM_PIN_FUNCTION(blsp_i2c5), + MSM_PIN_FUNCTION(blsp_i2c6), + MSM_PIN_FUNCTION(blsp_spi1), + MSM_PIN_FUNCTION(blsp_spi1_cs1), + MSM_PIN_FUNCTION(blsp_spi1_cs2), + MSM_PIN_FUNCTION(blsp_spi1_cs3), + MSM_PIN_FUNCTION(blsp_spi2), + MSM_PIN_FUNCTION(blsp_spi2_cs1), + MSM_PIN_FUNCTION(blsp_spi2_cs2), + MSM_PIN_FUNCTION(blsp_spi2_cs3), + MSM_PIN_FUNCTION(blsp_spi3), + MSM_PIN_FUNCTION(blsp_spi3_cs1), + MSM_PIN_FUNCTION(blsp_spi3_cs2), + MSM_PIN_FUNCTION(blsp_spi3_cs3), + MSM_PIN_FUNCTION(blsp_spi4), + MSM_PIN_FUNCTION(blsp_spi5), + MSM_PIN_FUNCTION(blsp_spi6), + MSM_PIN_FUNCTION(blsp_uart1), + MSM_PIN_FUNCTION(blsp_uart2), + MSM_PIN_FUNCTION(blsp_uim1), + MSM_PIN_FUNCTION(blsp_uim2), + MSM_PIN_FUNCTION(cam_mclk), + MSM_PIN_FUNCTION(cci_async), + MSM_PIN_FUNCTION(cci_timer0), + MSM_PIN_FUNCTION(cci_timer1), + MSM_PIN_FUNCTION(cci_timer2), + MSM_PIN_FUNCTION(cdc_pdm0), + MSM_PIN_FUNCTION(dbg_out), + MSM_PIN_FUNCTION(dmic0_clk), + MSM_PIN_FUNCTION(dmic0_data), + MSM_PIN_FUNCTION(ebi0_wrcdc), + MSM_PIN_FUNCTION(ebi2_a), + MSM_PIN_FUNCTION(ebi2_lcd), + MSM_PIN_FUNCTION(ext_lpass), + MSM_PIN_FUNCTION(gcc_gp1_clk_a), + MSM_PIN_FUNCTION(gcc_gp1_clk_b), + MSM_PIN_FUNCTION(gcc_gp2_clk_a), + MSM_PIN_FUNCTION(gcc_gp2_clk_b), + MSM_PIN_FUNCTION(gcc_gp3_clk_a), + MSM_PIN_FUNCTION(gcc_gp3_clk_b), + MSM_PIN_FUNCTION(gcc_plltest), + MSM_PIN_FUNCTION(gpio), + MSM_PIN_FUNCTION(gsm0_tx), + MSM_PIN_FUNCTION(ldo_en), + MSM_PIN_FUNCTION(ldo_update), + MSM_PIN_FUNCTION(m_voc), + MSM_PIN_FUNCTION(mdp_vsync), + MSM_PIN_FUNCTION(modem_tsync), + MSM_PIN_FUNCTION(nav_pps), + MSM_PIN_FUNCTION(nav_tsync), + MSM_PIN_FUNCTION(pa_indicator), + MSM_PIN_FUNCTION(pbs0), + MSM_PIN_FUNCTION(pbs1), + MSM_PIN_FUNCTION(pbs2), + MSM_PIN_FUNCTION(pri_mi2s_data0_a), + MSM_PIN_FUNCTION(pri_mi2s_data0_b), + MSM_PIN_FUNCTION(pri_mi2s_data1_a), + MSM_PIN_FUNCTION(pri_mi2s_data1_b), + MSM_PIN_FUNCTION(pri_mi2s_mclk_a), + MSM_PIN_FUNCTION(pri_mi2s_mclk_b), + MSM_PIN_FUNCTION(pri_mi2s_sck_a), + MSM_PIN_FUNCTION(pri_mi2s_sck_b), + MSM_PIN_FUNCTION(pri_mi2s_ws_a), + MSM_PIN_FUNCTION(pri_mi2s_ws_b), + MSM_PIN_FUNCTION(prng_rosc), + MSM_PIN_FUNCTION(pwr_crypto_enabled_a), + MSM_PIN_FUNCTION(pwr_crypto_enabled_b), + MSM_PIN_FUNCTION(pwr_modem_enabled_a), + MSM_PIN_FUNCTION(pwr_modem_enabled_b), + MSM_PIN_FUNCTION(pwr_nav_enabled_a), + MSM_PIN_FUNCTION(pwr_nav_enabled_b), + MSM_PIN_FUNCTION(qdss_cti_trig_in_a0), + MSM_PIN_FUNCTION(qdss_cti_trig_in_a1), + MSM_PIN_FUNCTION(qdss_cti_trig_in_b0), + MSM_PIN_FUNCTION(qdss_cti_trig_in_b1), + MSM_PIN_FUNCTION(qdss_cti_trig_out_a0), + MSM_PIN_FUNCTION(qdss_cti_trig_out_a1), + MSM_PIN_FUNCTION(qdss_cti_trig_out_b0), + MSM_PIN_FUNCTION(qdss_cti_trig_out_b1), + MSM_PIN_FUNCTION(qdss_traceclk_a), + MSM_PIN_FUNCTION(qdss_tracectl_a), + MSM_PIN_FUNCTION(qdss_tracedata_a), + MSM_PIN_FUNCTION(qdss_tracedata_b), + MSM_PIN_FUNCTION(sd_write), + MSM_PIN_FUNCTION(sec_mi2s), + MSM_PIN_FUNCTION(smb_int), + MSM_PIN_FUNCTION(ssbi0), + MSM_PIN_FUNCTION(ssbi1), + MSM_PIN_FUNCTION(uim1_clk), + MSM_PIN_FUNCTION(uim1_data), + MSM_PIN_FUNCTION(uim1_present), + MSM_PIN_FUNCTION(uim1_reset), + MSM_PIN_FUNCTION(uim2_clk), + MSM_PIN_FUNCTION(uim2_data), + MSM_PIN_FUNCTION(uim2_present), + MSM_PIN_FUNCTION(uim2_reset), + MSM_PIN_FUNCTION(uim3_clk), + MSM_PIN_FUNCTION(uim3_data), + MSM_PIN_FUNCTION(uim3_present), + MSM_PIN_FUNCTION(uim3_reset), + MSM_PIN_FUNCTION(uim_batt), + MSM_PIN_FUNCTION(wcss_bt), + MSM_PIN_FUNCTION(wcss_fm), + MSM_PIN_FUNCTION(wcss_wlan), +}; + +static const struct msm_pingroup msm8909_groups[] = { + PINGROUP(0, blsp_spi3, sec_mi2s, _, _, _, _, _, _, _), + PINGROUP(1, blsp_spi3, sec_mi2s, _, _, _, _, _, _, _), + PINGROUP(2, blsp_spi3, sec_mi2s, _, _, _, _, _, _, _), + PINGROUP(3, blsp_spi3, sec_mi2s, _, _, _, _, _, _, _), + PINGROUP(4, blsp_spi1, blsp_uart1, blsp_uim1, blsp_spi3_cs3, dmic0_clk, _, _, _, _), + PINGROUP(5, blsp_spi1, blsp_uart1, blsp_uim1, blsp_spi2_cs3, dmic0_data, _, _, _, _), + PINGROUP(6, blsp_spi1, blsp_uart1, blsp_i2c1, _, _, _, _, _, bimc_dte0), + PINGROUP(7, blsp_spi1, blsp_uart1, blsp_i2c1, _, _, _, _, _, bimc_dte1), + PINGROUP(8, blsp_spi6, m_voc, _, _, _, _, _, qdss_tracedata_a, _), + PINGROUP(9, blsp_spi6, _, _, _, _, _, qdss_tracedata_a, _, _), + PINGROUP(10, blsp_spi6, blsp_i2c6, dbg_out, qdss_tracedata_a, _, _, _, _, _), + PINGROUP(11, blsp_spi6, blsp_i2c6, _, _, _, _, _, _, _), + PINGROUP(12, blsp_spi4, gcc_gp2_clk_b, _, _, _, _, _, _, _), + PINGROUP(13, blsp_spi4, gcc_gp3_clk_b, _, _, _, _, _, _, _), + PINGROUP(14, blsp_spi4, blsp_i2c4, gcc_gp1_clk_b, _, _, _, _, _, qdss_tracedata_b), + PINGROUP(15, blsp_spi4, blsp_i2c4, _, _, _, _, _, _, _), + PINGROUP(16, blsp_spi5, _, _, _, _, _, qdss_tracedata_b, _, _), + PINGROUP(17, blsp_spi5, blsp_spi2_cs2, _, _, _, _, _, qdss_tracedata_b, _), + PINGROUP(18, blsp_spi5, blsp_i2c5, _, _, _, _, _, _, _), + PINGROUP(19, blsp_spi5, blsp_i2c5, _, _, _, _, _, _, _), + PINGROUP(20, uim3_data, blsp_spi2, blsp_uart2, blsp_uim2, _, qdss_cti_trig_in_a0, _, _, _), + PINGROUP(21, uim3_present, blsp_spi2, blsp_uart2, blsp_uim2, _, qdss_cti_trig_in_b0, _, _, _), + PINGROUP(22, uim3_reset, _, qdss_cti_trig_out_b0, _, _, _, _, _, _), + PINGROUP(23, uim3_clk, qdss_cti_trig_out_a0, _, _, _, _, _, _, _), + PINGROUP(24, mdp_vsync, ebi2_lcd, ebi2_lcd, _, _, _, _, _, _), + PINGROUP(25, mdp_vsync, ebi2_lcd, _, _, _, _, _, _, _), + PINGROUP(26, cam_mclk, _, _, _, _, _, _, _, _), + PINGROUP(27, cam_mclk, _, _, _, _, _, _, _, _), + PINGROUP(28, _, pwr_modem_enabled_a, _, _, _, _, _, _, _), + PINGROUP(29, blsp_i2c3, _, _, _, _, _, qdss_tracedata_b, _, _), + PINGROUP(30, blsp_i2c3, _, _, _, _, _, qdss_tracedata_b, _, _), + PINGROUP(31, cci_timer0, _, _, _, _, _, _, qdss_tracedata_b, _), + PINGROUP(32, cci_timer1, _, qdss_tracedata_b, _, atest_combodac, _, _, _, _), + PINGROUP(33, cci_async, qdss_tracedata_b, _, _, _, _, _, _, _), + PINGROUP(34, pwr_nav_enabled_a, qdss_tracedata_b, _, _, _, _, _, _, _), + PINGROUP(35, pwr_crypto_enabled_a, qdss_tracedata_b, _, _, _, _, _, _, _), + PINGROUP(36, qdss_tracedata_b, _, atest_bbrx1, _, _, _, _, _, _), + PINGROUP(37, blsp_spi1_cs2, qdss_tracedata_b, _, atest_bbrx0, _, _, _, _, _), + PINGROUP(38, cci_timer2, adsp_ext, _, atest_combodac, _, _, _, _, _), + PINGROUP(39, wcss_bt, qdss_tracedata_a, _, atest_combodac, _, _, _, _, _), + PINGROUP(40, wcss_wlan, qdss_tracedata_a, _, atest_combodac, _, _, _, _, _), + PINGROUP(41, wcss_wlan, qdss_tracedata_a, _, atest_combodac, _, _, _, _, _), + PINGROUP(42, wcss_wlan, qdss_tracedata_a, _, atest_combodac, _, _, _, _, _), + PINGROUP(43, wcss_wlan, prng_rosc, qdss_tracedata_a, _, atest_combodac, _, _, _, _), + PINGROUP(44, wcss_wlan, _, atest_combodac, _, _, _, _, _, _), + PINGROUP(45, wcss_fm, ext_lpass, qdss_tracectl_a, _, atest_combodac, _, _, _, _), + PINGROUP(46, wcss_fm, qdss_traceclk_a, _, _, _, _, _, _, _), + PINGROUP(47, wcss_bt, qdss_tracedata_a, _, atest_combodac, _, _, _, _, _), + PINGROUP(48, wcss_bt, qdss_tracedata_a, _, atest_combodac, _, _, _, _, _), + PINGROUP(49, uim2_data, gcc_gp1_clk_a, qdss_cti_trig_in_a1, _, _, _, _, _, _), + PINGROUP(50, uim2_clk, gcc_gp2_clk_a, qdss_cti_trig_in_b1, _, _, _, _, _, _), + PINGROUP(51, uim2_reset, gcc_gp3_clk_a, qdss_cti_trig_out_b1, _, _, _, _, _, _), + PINGROUP(52, uim2_present, qdss_cti_trig_out_a1, _, _, _, _, _, _, _), + PINGROUP(53, uim1_data, _, _, _, _, _, _, _, _), + PINGROUP(54, uim1_clk, _, _, _, _, _, _, _, _), + PINGROUP(55, uim1_reset, _, _, _, _, _, _, _, _), + PINGROUP(56, uim1_present, _, _, _, _, _, _, _, _), + PINGROUP(57, uim_batt, _, _, _, _, _, _, _, _), + PINGROUP(58, qdss_tracedata_a, smb_int, _, _, _, _, _, _, _), + PINGROUP(59, cdc_pdm0, pri_mi2s_mclk_a, atest_char3, _, _, _, _, _, bimc_dte0), + PINGROUP(60, cdc_pdm0, pri_mi2s_sck_a, atest_char2, _, _, _, _, _, bimc_dte1), + PINGROUP(61, cdc_pdm0, pri_mi2s_ws_a, atest_char1, _, _, _, _, _, _), + PINGROUP(62, cdc_pdm0, pri_mi2s_data0_a, atest_char0, _, _, _, _, _, _), + PINGROUP(63, cdc_pdm0, pri_mi2s_data1_a, atest_char, _, _, _, _, _, _), + PINGROUP(64, cdc_pdm0, _, _, _, _, _, ebi0_wrcdc, _, _), + PINGROUP(65, blsp_spi3_cs2, blsp_spi1_cs3, qdss_tracedata_a, _, atest_gpsadc0, _, _, _, _), + PINGROUP(66, _, gcc_plltest, _, atest_combodac, _, _, _, _, _), + PINGROUP(67, _, gcc_plltest, _, _, _, _, _, _, _), + PINGROUP(68, _, _, _, _, _, _, _, _, _), + PINGROUP(69, _, _, _, _, _, _, _, _, _), + PINGROUP(70, _, _, _, _, _, _, _, _, _), + PINGROUP(71, _, _, _, _, _, _, _, _, _), + PINGROUP(72, _, _, _, _, _, _, _, _, _), + PINGROUP(73, _, _, _, _, _, _, _, _, _), + PINGROUP(74, _, _, _, _, _, _, _, _, _), + PINGROUP(75, _, _, _, _, _, _, _, _, _), + PINGROUP(76, _, _, _, _, _, _, _, _, _), + PINGROUP(77, _, _, _, _, _, _, _, _, _), + PINGROUP(78, _, _, _, _, _, _, _, _, _), + PINGROUP(79, _, _, atest_gpsadc1, _, _, _, _, _, _), + PINGROUP(80, _, _, _, _, _, _, _, _, _), + PINGROUP(81, _, _, _, atest_combodac, _, _, _, _, _), + PINGROUP(82, _, pa_indicator, _, _, _, _, _, _, _), + PINGROUP(83, _, modem_tsync, nav_tsync, nav_pps, _, atest_combodac, _, _, _), + PINGROUP(84, _, _, atest_combodac, _, _, _, _, _, _), + PINGROUP(85, gsm0_tx, _, _, atest_combodac, _, _, _, _, _), + PINGROUP(86, _, _, atest_combodac, _, _, _, _, _, _), + PINGROUP(87, _, _, _, _, _, _, _, _, _), + PINGROUP(88, _, ssbi0, _, _, _, _, _, _, _), + PINGROUP(89, _, ssbi1, _, _, _, _, _, _, _), + PINGROUP(90, pbs0, _, _, _, _, _, _, _, _), + PINGROUP(91, pbs1, _, _, _, _, _, _, _, _), + PINGROUP(92, pbs2, _, _, _, _, _, _, _, _), + PINGROUP(93, qdss_tracedata_b, _, _, _, _, _, _, _, _), + PINGROUP(94, pri_mi2s_sck_b, pwr_modem_enabled_b, qdss_tracedata_a, _, atest_combodac, _, _, _, _), + PINGROUP(95, blsp_spi3_cs1, pri_mi2s_data0_b, ebi2_lcd, m_voc, pwr_nav_enabled_b, _, atest_combodac, _, _), + PINGROUP(96, pri_mi2s_data1_b, _, pwr_crypto_enabled_b, qdss_tracedata_a, _, atest_wlan0, _, _, _), + PINGROUP(97, blsp_spi1_cs1, qdss_tracedata_a, _, atest_wlan1, _, _, _, _, _), + PINGROUP(98, sec_mi2s, pri_mi2s_mclk_b, blsp_spi2_cs1, ldo_update, _, _, _, _, _), + PINGROUP(99, ebi2_a, sd_write, ldo_en, _, _, _, _, _, _), + PINGROUP(100, _, _, _, _, _, _, _, _, _), + PINGROUP(101, _, _, _, _, _, _, _, _, _), + PINGROUP(102, _, _, _, _, _, _, _, _, _), + PINGROUP(103, _, _, _, _, _, _, _, _, _), + PINGROUP(104, _, _, _, _, _, _, _, _, _), + PINGROUP(105, _, _, _, _, _, _, _, _, _), + PINGROUP(106, _, _, _, _, _, _, _, _, _), + PINGROUP(107, _, _, _, _, _, _, _, _, _), + PINGROUP(108, _, _, _, _, _, _, _, _, _), + PINGROUP(109, _, _, _, _, _, _, _, _, _), + PINGROUP(110, pri_mi2s_ws_b, _, atest_combodac, _, _, _, _, _, _), + PINGROUP(111, blsp_spi2, blsp_uart2, blsp_i2c2, _, _, _, _, _, _), + PINGROUP(112, blsp_spi2, blsp_uart2, blsp_i2c2, _, _, _, _, _, _), + SDC_QDSD_PINGROUP(sdc1_clk, 0x10a000, 13, 6), + SDC_QDSD_PINGROUP(sdc1_cmd, 0x10a000, 11, 3), + SDC_QDSD_PINGROUP(sdc1_data, 0x10a000, 9, 0), + SDC_QDSD_PINGROUP(sdc2_clk, 0x109000, 14, 6), + SDC_QDSD_PINGROUP(sdc2_cmd, 0x109000, 11, 3), + SDC_QDSD_PINGROUP(sdc2_data, 0x109000, 9, 0), + SDC_QDSD_PINGROUP(qdsd_clk, 0x19c000, 3, 0), + SDC_QDSD_PINGROUP(qdsd_cmd, 0x19c000, 8, 5), + SDC_QDSD_PINGROUP(qdsd_data0, 0x19c000, 13, 10), + SDC_QDSD_PINGROUP(qdsd_data1, 0x19c000, 18, 15), + SDC_QDSD_PINGROUP(qdsd_data2, 0x19c000, 23, 20), + SDC_QDSD_PINGROUP(qdsd_data3, 0x19c000, 28, 25), +}; + +static const struct msm_gpio_wakeirq_map msm8909_mpm_map[] = { + { 65, 3 }, { 5, 4 }, { 11, 5 }, { 12, 6 }, { 64, 7 }, { 58, 8 }, + { 50, 9 }, { 13, 10 }, { 49, 11 }, { 20, 12 }, { 21, 13 }, { 25, 14 }, + { 46, 15 }, { 45, 16 }, { 28, 17 }, { 44, 18 }, { 31, 19 }, { 43, 20 }, + { 42, 21 }, { 34, 22 }, { 35, 23 }, { 36, 24 }, { 37, 25 }, { 38, 26 }, + { 39, 27 }, { 40, 28 }, { 41, 29 }, { 90, 30 }, { 91, 32 }, { 92, 33 }, + { 94, 34 }, { 95, 35 }, { 96, 36 }, { 97, 37 }, { 98, 38 }, + { 110, 39 }, { 111, 40 }, { 112, 41 }, { 105, 42 }, { 107, 43 }, + { 47, 50 }, { 48, 51 }, +}; + +static const struct msm_pinctrl_soc_data msm8909_pinctrl = { + .pins = msm8909_pins, + .npins = ARRAY_SIZE(msm8909_pins), + .functions = msm8909_functions, + .nfunctions = ARRAY_SIZE(msm8909_functions), + .groups = msm8909_groups, + .ngroups = ARRAY_SIZE(msm8909_groups), + .ngpios = 113, + .wakeirq_map = msm8909_mpm_map, + .nwakeirq_map = ARRAY_SIZE(msm8909_mpm_map), +}; + +static int msm8909_pinctrl_probe(struct platform_device *pdev) +{ + return msm_pinctrl_probe(pdev, &msm8909_pinctrl); +} + +static const struct of_device_id msm8909_pinctrl_of_match[] = { + { .compatible = "qcom,msm8909-tlmm", }, + { }, +}; +MODULE_DEVICE_TABLE(of, msm8909_pinctrl_of_match); + +static struct platform_driver msm8909_pinctrl_driver = { + .driver = { + .name = "msm8909-pinctrl", + .of_match_table = msm8909_pinctrl_of_match, + }, + .probe = msm8909_pinctrl_probe, + .remove = msm_pinctrl_remove, +}; + +static int __init msm8909_pinctrl_init(void) +{ + return platform_driver_register(&msm8909_pinctrl_driver); +} +arch_initcall(msm8909_pinctrl_init); + +static void __exit msm8909_pinctrl_exit(void) +{ + platform_driver_unregister(&msm8909_pinctrl_driver); +} +module_exit(msm8909_pinctrl_exit); + +MODULE_DESCRIPTION("Qualcomm MSM8909 TLMM pinctrl driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/pinctrl/qcom/pinctrl-msm8916.c b/drivers/pinctrl/qcom/pinctrl-msm8916.c new file mode 100644 index 0000000000..cea5c54f92 --- /dev/null +++ b/drivers/pinctrl/qcom/pinctrl-msm8916.c @@ -0,0 +1,989 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2015, The Linux Foundation. All rights reserved. + */ + +#include <linux/module.h> +#include <linux/of.h> +#include <linux/platform_device.h> + +#include "pinctrl-msm.h" + +static const struct pinctrl_pin_desc msm8916_pins[] = { + PINCTRL_PIN(0, "GPIO_0"), + PINCTRL_PIN(1, "GPIO_1"), + PINCTRL_PIN(2, "GPIO_2"), + PINCTRL_PIN(3, "GPIO_3"), + PINCTRL_PIN(4, "GPIO_4"), + PINCTRL_PIN(5, "GPIO_5"), + PINCTRL_PIN(6, "GPIO_6"), + PINCTRL_PIN(7, "GPIO_7"), + PINCTRL_PIN(8, "GPIO_8"), + PINCTRL_PIN(9, "GPIO_9"), + PINCTRL_PIN(10, "GPIO_10"), + PINCTRL_PIN(11, "GPIO_11"), + PINCTRL_PIN(12, "GPIO_12"), + PINCTRL_PIN(13, "GPIO_13"), + PINCTRL_PIN(14, "GPIO_14"), + PINCTRL_PIN(15, "GPIO_15"), + PINCTRL_PIN(16, "GPIO_16"), + PINCTRL_PIN(17, "GPIO_17"), + PINCTRL_PIN(18, "GPIO_18"), + PINCTRL_PIN(19, "GPIO_19"), + PINCTRL_PIN(20, "GPIO_20"), + PINCTRL_PIN(21, "GPIO_21"), + PINCTRL_PIN(22, "GPIO_22"), + PINCTRL_PIN(23, "GPIO_23"), + PINCTRL_PIN(24, "GPIO_24"), + PINCTRL_PIN(25, "GPIO_25"), + PINCTRL_PIN(26, "GPIO_26"), + PINCTRL_PIN(27, "GPIO_27"), + PINCTRL_PIN(28, "GPIO_28"), + PINCTRL_PIN(29, "GPIO_29"), + PINCTRL_PIN(30, "GPIO_30"), + PINCTRL_PIN(31, "GPIO_31"), + PINCTRL_PIN(32, "GPIO_32"), + PINCTRL_PIN(33, "GPIO_33"), + PINCTRL_PIN(34, "GPIO_34"), + PINCTRL_PIN(35, "GPIO_35"), + PINCTRL_PIN(36, "GPIO_36"), + PINCTRL_PIN(37, "GPIO_37"), + PINCTRL_PIN(38, "GPIO_38"), + PINCTRL_PIN(39, "GPIO_39"), + PINCTRL_PIN(40, "GPIO_40"), + PINCTRL_PIN(41, "GPIO_41"), + PINCTRL_PIN(42, "GPIO_42"), + PINCTRL_PIN(43, "GPIO_43"), + PINCTRL_PIN(44, "GPIO_44"), + PINCTRL_PIN(45, "GPIO_45"), + PINCTRL_PIN(46, "GPIO_46"), + PINCTRL_PIN(47, "GPIO_47"), + PINCTRL_PIN(48, "GPIO_48"), + PINCTRL_PIN(49, "GPIO_49"), + PINCTRL_PIN(50, "GPIO_50"), + PINCTRL_PIN(51, "GPIO_51"), + PINCTRL_PIN(52, "GPIO_52"), + PINCTRL_PIN(53, "GPIO_53"), + PINCTRL_PIN(54, "GPIO_54"), + PINCTRL_PIN(55, "GPIO_55"), + PINCTRL_PIN(56, "GPIO_56"), + PINCTRL_PIN(57, "GPIO_57"), + PINCTRL_PIN(58, "GPIO_58"), + PINCTRL_PIN(59, "GPIO_59"), + PINCTRL_PIN(60, "GPIO_60"), + PINCTRL_PIN(61, "GPIO_61"), + PINCTRL_PIN(62, "GPIO_62"), + PINCTRL_PIN(63, "GPIO_63"), + PINCTRL_PIN(64, "GPIO_64"), + PINCTRL_PIN(65, "GPIO_65"), + PINCTRL_PIN(66, "GPIO_66"), + PINCTRL_PIN(67, "GPIO_67"), + PINCTRL_PIN(68, "GPIO_68"), + PINCTRL_PIN(69, "GPIO_69"), + PINCTRL_PIN(70, "GPIO_70"), + PINCTRL_PIN(71, "GPIO_71"), + PINCTRL_PIN(72, "GPIO_72"), + PINCTRL_PIN(73, "GPIO_73"), + PINCTRL_PIN(74, "GPIO_74"), + PINCTRL_PIN(75, "GPIO_75"), + PINCTRL_PIN(76, "GPIO_76"), + PINCTRL_PIN(77, "GPIO_77"), + PINCTRL_PIN(78, "GPIO_78"), + PINCTRL_PIN(79, "GPIO_79"), + PINCTRL_PIN(80, "GPIO_80"), + PINCTRL_PIN(81, "GPIO_81"), + PINCTRL_PIN(82, "GPIO_82"), + PINCTRL_PIN(83, "GPIO_83"), + PINCTRL_PIN(84, "GPIO_84"), + PINCTRL_PIN(85, "GPIO_85"), + PINCTRL_PIN(86, "GPIO_86"), + PINCTRL_PIN(87, "GPIO_87"), + PINCTRL_PIN(88, "GPIO_88"), + PINCTRL_PIN(89, "GPIO_89"), + PINCTRL_PIN(90, "GPIO_90"), + PINCTRL_PIN(91, "GPIO_91"), + PINCTRL_PIN(92, "GPIO_92"), + PINCTRL_PIN(93, "GPIO_93"), + PINCTRL_PIN(94, "GPIO_94"), + PINCTRL_PIN(95, "GPIO_95"), + PINCTRL_PIN(96, "GPIO_96"), + PINCTRL_PIN(97, "GPIO_97"), + PINCTRL_PIN(98, "GPIO_98"), + PINCTRL_PIN(99, "GPIO_99"), + PINCTRL_PIN(100, "GPIO_100"), + PINCTRL_PIN(101, "GPIO_101"), + PINCTRL_PIN(102, "GPIO_102"), + PINCTRL_PIN(103, "GPIO_103"), + PINCTRL_PIN(104, "GPIO_104"), + PINCTRL_PIN(105, "GPIO_105"), + PINCTRL_PIN(106, "GPIO_106"), + PINCTRL_PIN(107, "GPIO_107"), + PINCTRL_PIN(108, "GPIO_108"), + PINCTRL_PIN(109, "GPIO_109"), + PINCTRL_PIN(110, "GPIO_110"), + PINCTRL_PIN(111, "GPIO_111"), + PINCTRL_PIN(112, "GPIO_112"), + PINCTRL_PIN(113, "GPIO_113"), + PINCTRL_PIN(114, "GPIO_114"), + PINCTRL_PIN(115, "GPIO_115"), + PINCTRL_PIN(116, "GPIO_116"), + PINCTRL_PIN(117, "GPIO_117"), + PINCTRL_PIN(118, "GPIO_118"), + PINCTRL_PIN(119, "GPIO_119"), + PINCTRL_PIN(120, "GPIO_120"), + PINCTRL_PIN(121, "GPIO_121"), + PINCTRL_PIN(122, "SDC1_CLK"), + PINCTRL_PIN(123, "SDC1_CMD"), + PINCTRL_PIN(124, "SDC1_DATA"), + PINCTRL_PIN(125, "SDC2_CLK"), + PINCTRL_PIN(126, "SDC2_CMD"), + PINCTRL_PIN(127, "SDC2_DATA"), + PINCTRL_PIN(128, "QDSD_CLK"), + PINCTRL_PIN(129, "QDSD_CMD"), + PINCTRL_PIN(130, "QDSD_DATA0"), + PINCTRL_PIN(131, "QDSD_DATA1"), + PINCTRL_PIN(132, "QDSD_DATA2"), + PINCTRL_PIN(133, "QDSD_DATA3"), +}; + +#define DECLARE_MSM_GPIO_PINS(pin) \ + static const unsigned int gpio##pin##_pins[] = { pin } + +DECLARE_MSM_GPIO_PINS(0); +DECLARE_MSM_GPIO_PINS(1); +DECLARE_MSM_GPIO_PINS(2); +DECLARE_MSM_GPIO_PINS(3); +DECLARE_MSM_GPIO_PINS(4); +DECLARE_MSM_GPIO_PINS(5); +DECLARE_MSM_GPIO_PINS(6); +DECLARE_MSM_GPIO_PINS(7); +DECLARE_MSM_GPIO_PINS(8); +DECLARE_MSM_GPIO_PINS(9); +DECLARE_MSM_GPIO_PINS(10); +DECLARE_MSM_GPIO_PINS(11); +DECLARE_MSM_GPIO_PINS(12); +DECLARE_MSM_GPIO_PINS(13); +DECLARE_MSM_GPIO_PINS(14); +DECLARE_MSM_GPIO_PINS(15); +DECLARE_MSM_GPIO_PINS(16); +DECLARE_MSM_GPIO_PINS(17); +DECLARE_MSM_GPIO_PINS(18); +DECLARE_MSM_GPIO_PINS(19); +DECLARE_MSM_GPIO_PINS(20); +DECLARE_MSM_GPIO_PINS(21); +DECLARE_MSM_GPIO_PINS(22); +DECLARE_MSM_GPIO_PINS(23); +DECLARE_MSM_GPIO_PINS(24); +DECLARE_MSM_GPIO_PINS(25); +DECLARE_MSM_GPIO_PINS(26); +DECLARE_MSM_GPIO_PINS(27); +DECLARE_MSM_GPIO_PINS(28); +DECLARE_MSM_GPIO_PINS(29); +DECLARE_MSM_GPIO_PINS(30); +DECLARE_MSM_GPIO_PINS(31); +DECLARE_MSM_GPIO_PINS(32); +DECLARE_MSM_GPIO_PINS(33); +DECLARE_MSM_GPIO_PINS(34); +DECLARE_MSM_GPIO_PINS(35); +DECLARE_MSM_GPIO_PINS(36); +DECLARE_MSM_GPIO_PINS(37); +DECLARE_MSM_GPIO_PINS(38); +DECLARE_MSM_GPIO_PINS(39); +DECLARE_MSM_GPIO_PINS(40); +DECLARE_MSM_GPIO_PINS(41); +DECLARE_MSM_GPIO_PINS(42); +DECLARE_MSM_GPIO_PINS(43); +DECLARE_MSM_GPIO_PINS(44); +DECLARE_MSM_GPIO_PINS(45); +DECLARE_MSM_GPIO_PINS(46); +DECLARE_MSM_GPIO_PINS(47); +DECLARE_MSM_GPIO_PINS(48); +DECLARE_MSM_GPIO_PINS(49); +DECLARE_MSM_GPIO_PINS(50); +DECLARE_MSM_GPIO_PINS(51); +DECLARE_MSM_GPIO_PINS(52); +DECLARE_MSM_GPIO_PINS(53); +DECLARE_MSM_GPIO_PINS(54); +DECLARE_MSM_GPIO_PINS(55); +DECLARE_MSM_GPIO_PINS(56); +DECLARE_MSM_GPIO_PINS(57); +DECLARE_MSM_GPIO_PINS(58); +DECLARE_MSM_GPIO_PINS(59); +DECLARE_MSM_GPIO_PINS(60); +DECLARE_MSM_GPIO_PINS(61); +DECLARE_MSM_GPIO_PINS(62); +DECLARE_MSM_GPIO_PINS(63); +DECLARE_MSM_GPIO_PINS(64); +DECLARE_MSM_GPIO_PINS(65); +DECLARE_MSM_GPIO_PINS(66); +DECLARE_MSM_GPIO_PINS(67); +DECLARE_MSM_GPIO_PINS(68); +DECLARE_MSM_GPIO_PINS(69); +DECLARE_MSM_GPIO_PINS(70); +DECLARE_MSM_GPIO_PINS(71); +DECLARE_MSM_GPIO_PINS(72); +DECLARE_MSM_GPIO_PINS(73); +DECLARE_MSM_GPIO_PINS(74); +DECLARE_MSM_GPIO_PINS(75); +DECLARE_MSM_GPIO_PINS(76); +DECLARE_MSM_GPIO_PINS(77); +DECLARE_MSM_GPIO_PINS(78); +DECLARE_MSM_GPIO_PINS(79); +DECLARE_MSM_GPIO_PINS(80); +DECLARE_MSM_GPIO_PINS(81); +DECLARE_MSM_GPIO_PINS(82); +DECLARE_MSM_GPIO_PINS(83); +DECLARE_MSM_GPIO_PINS(84); +DECLARE_MSM_GPIO_PINS(85); +DECLARE_MSM_GPIO_PINS(86); +DECLARE_MSM_GPIO_PINS(87); +DECLARE_MSM_GPIO_PINS(88); +DECLARE_MSM_GPIO_PINS(89); +DECLARE_MSM_GPIO_PINS(90); +DECLARE_MSM_GPIO_PINS(91); +DECLARE_MSM_GPIO_PINS(92); +DECLARE_MSM_GPIO_PINS(93); +DECLARE_MSM_GPIO_PINS(94); +DECLARE_MSM_GPIO_PINS(95); +DECLARE_MSM_GPIO_PINS(96); +DECLARE_MSM_GPIO_PINS(97); +DECLARE_MSM_GPIO_PINS(98); +DECLARE_MSM_GPIO_PINS(99); +DECLARE_MSM_GPIO_PINS(100); +DECLARE_MSM_GPIO_PINS(101); +DECLARE_MSM_GPIO_PINS(102); +DECLARE_MSM_GPIO_PINS(103); +DECLARE_MSM_GPIO_PINS(104); +DECLARE_MSM_GPIO_PINS(105); +DECLARE_MSM_GPIO_PINS(106); +DECLARE_MSM_GPIO_PINS(107); +DECLARE_MSM_GPIO_PINS(108); +DECLARE_MSM_GPIO_PINS(109); +DECLARE_MSM_GPIO_PINS(110); +DECLARE_MSM_GPIO_PINS(111); +DECLARE_MSM_GPIO_PINS(112); +DECLARE_MSM_GPIO_PINS(113); +DECLARE_MSM_GPIO_PINS(114); +DECLARE_MSM_GPIO_PINS(115); +DECLARE_MSM_GPIO_PINS(116); +DECLARE_MSM_GPIO_PINS(117); +DECLARE_MSM_GPIO_PINS(118); +DECLARE_MSM_GPIO_PINS(119); +DECLARE_MSM_GPIO_PINS(120); +DECLARE_MSM_GPIO_PINS(121); + +static const unsigned int sdc1_clk_pins[] = { 122 }; +static const unsigned int sdc1_cmd_pins[] = { 123 }; +static const unsigned int sdc1_data_pins[] = { 124 }; +static const unsigned int sdc2_clk_pins[] = { 125 }; +static const unsigned int sdc2_cmd_pins[] = { 126 }; +static const unsigned int sdc2_data_pins[] = { 127 }; +static const unsigned int qdsd_clk_pins[] = { 128 }; +static const unsigned int qdsd_cmd_pins[] = { 129 }; +static const unsigned int qdsd_data0_pins[] = { 130 }; +static const unsigned int qdsd_data1_pins[] = { 131 }; +static const unsigned int qdsd_data2_pins[] = { 132 }; +static const unsigned int qdsd_data3_pins[] = { 133 }; + +#define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7, f8, f9) \ + { \ + .grp = PINCTRL_PINGROUP("gpio" #id, \ + gpio##id##_pins, \ + ARRAY_SIZE(gpio##id##_pins)), \ + .funcs = (int[]){ \ + msm_mux_gpio, \ + msm_mux_##f1, \ + msm_mux_##f2, \ + msm_mux_##f3, \ + msm_mux_##f4, \ + msm_mux_##f5, \ + msm_mux_##f6, \ + msm_mux_##f7, \ + msm_mux_##f8, \ + msm_mux_##f9 \ + }, \ + .nfuncs = 10, \ + .ctl_reg = 0x1000 * id, \ + .io_reg = 0x4 + 0x1000 * id, \ + .intr_cfg_reg = 0x8 + 0x1000 * id, \ + .intr_status_reg = 0xc + 0x1000 * id, \ + .intr_target_reg = 0x8 + 0x1000 * id, \ + .mux_bit = 2, \ + .pull_bit = 0, \ + .drv_bit = 6, \ + .oe_bit = 9, \ + .in_bit = 0, \ + .out_bit = 1, \ + .intr_enable_bit = 0, \ + .intr_status_bit = 0, \ + .intr_target_bit = 5, \ + .intr_target_kpss_val = 4, \ + .intr_raw_status_bit = 4, \ + .intr_polarity_bit = 1, \ + .intr_detection_bit = 2, \ + .intr_detection_width = 2, \ + } + +#define SDC_PINGROUP(pg_name, ctl, pull, drv) \ + { \ + .grp = PINCTRL_PINGROUP(#pg_name, \ + pg_name##_pins, \ + ARRAY_SIZE(pg_name##_pins)), \ + .ctl_reg = ctl, \ + .io_reg = 0, \ + .intr_cfg_reg = 0, \ + .intr_status_reg = 0, \ + .intr_target_reg = 0, \ + .mux_bit = -1, \ + .pull_bit = pull, \ + .drv_bit = drv, \ + .oe_bit = -1, \ + .in_bit = -1, \ + .out_bit = -1, \ + .intr_enable_bit = -1, \ + .intr_status_bit = -1, \ + .intr_target_bit = -1, \ + .intr_target_kpss_val = -1, \ + .intr_raw_status_bit = -1, \ + .intr_polarity_bit = -1, \ + .intr_detection_bit = -1, \ + .intr_detection_width = -1, \ + } + +enum msm8916_functions { + msm_mux_adsp_ext, + msm_mux_alsp_int, + msm_mux_atest_bbrx0, + msm_mux_atest_bbrx1, + msm_mux_atest_char, + msm_mux_atest_char0, + msm_mux_atest_char1, + msm_mux_atest_char2, + msm_mux_atest_char3, + msm_mux_atest_combodac, + msm_mux_atest_gpsadc0, + msm_mux_atest_gpsadc1, + msm_mux_atest_tsens, + msm_mux_atest_wlan0, + msm_mux_atest_wlan1, + msm_mux_backlight_en, + msm_mux_bimc_dte0, + msm_mux_bimc_dte1, + msm_mux_blsp_i2c1, + msm_mux_blsp_i2c2, + msm_mux_blsp_i2c3, + msm_mux_blsp_i2c4, + msm_mux_blsp_i2c5, + msm_mux_blsp_i2c6, + msm_mux_blsp_spi1, + msm_mux_blsp_spi1_cs1, + msm_mux_blsp_spi1_cs2, + msm_mux_blsp_spi1_cs3, + msm_mux_blsp_spi2, + msm_mux_blsp_spi2_cs1, + msm_mux_blsp_spi2_cs2, + msm_mux_blsp_spi2_cs3, + msm_mux_blsp_spi3, + msm_mux_blsp_spi3_cs1, + msm_mux_blsp_spi3_cs2, + msm_mux_blsp_spi3_cs3, + msm_mux_blsp_spi4, + msm_mux_blsp_spi5, + msm_mux_blsp_spi6, + msm_mux_blsp_uart1, + msm_mux_blsp_uart2, + msm_mux_blsp_uim1, + msm_mux_blsp_uim2, + msm_mux_cam1_rst, + msm_mux_cam1_standby, + msm_mux_cam_mclk0, + msm_mux_cam_mclk1, + msm_mux_cci_async, + msm_mux_cci_i2c, + msm_mux_cci_timer0, + msm_mux_cci_timer1, + msm_mux_cci_timer2, + msm_mux_cdc_pdm0, + msm_mux_codec_mad, + msm_mux_dbg_out, + msm_mux_display_5v, + msm_mux_dmic0_clk, + msm_mux_dmic0_data, + msm_mux_dsi_rst, + msm_mux_ebi0_wrcdc, + msm_mux_euro_us, + msm_mux_ext_lpass, + msm_mux_flash_strobe, + msm_mux_gcc_gp1_clk_a, + msm_mux_gcc_gp1_clk_b, + msm_mux_gcc_gp2_clk_a, + msm_mux_gcc_gp2_clk_b, + msm_mux_gcc_gp3_clk_a, + msm_mux_gcc_gp3_clk_b, + msm_mux_gpio, + msm_mux_gsm0_tx0, + msm_mux_gsm0_tx1, + msm_mux_gsm1_tx0, + msm_mux_gsm1_tx1, + msm_mux_gyro_accl, + msm_mux_kpsns0, + msm_mux_kpsns1, + msm_mux_kpsns2, + msm_mux_ldo_en, + msm_mux_ldo_update, + msm_mux_mag_int, + msm_mux_mdp_vsync, + msm_mux_modem_tsync, + msm_mux_m_voc, + msm_mux_nav_pps, + msm_mux_nav_tsync, + msm_mux_pa_indicator, + msm_mux_pbs0, + msm_mux_pbs1, + msm_mux_pbs2, + msm_mux_pri_mi2s, + msm_mux_pri_mi2s_ws, + msm_mux_prng_rosc, + msm_mux_pwr_crypto_enabled_a, + msm_mux_pwr_crypto_enabled_b, + msm_mux_pwr_modem_enabled_a, + msm_mux_pwr_modem_enabled_b, + msm_mux_pwr_nav_enabled_a, + msm_mux_pwr_nav_enabled_b, + msm_mux_qdss_ctitrig_in_a0, + msm_mux_qdss_ctitrig_in_a1, + msm_mux_qdss_ctitrig_in_b0, + msm_mux_qdss_ctitrig_in_b1, + msm_mux_qdss_ctitrig_out_a0, + msm_mux_qdss_ctitrig_out_a1, + msm_mux_qdss_ctitrig_out_b0, + msm_mux_qdss_ctitrig_out_b1, + msm_mux_qdss_traceclk_a, + msm_mux_qdss_traceclk_b, + msm_mux_qdss_tracectl_a, + msm_mux_qdss_tracectl_b, + msm_mux_qdss_tracedata_a, + msm_mux_qdss_tracedata_b, + msm_mux_reset_n, + msm_mux_sd_card, + msm_mux_sd_write, + msm_mux_sec_mi2s, + msm_mux_smb_int, + msm_mux_ssbi_wtr0, + msm_mux_ssbi_wtr1, + msm_mux_uim1, + msm_mux_uim2, + msm_mux_uim3, + msm_mux_uim_batt, + msm_mux_wcss_bt, + msm_mux_wcss_fm, + msm_mux_wcss_wlan, + msm_mux_webcam1_rst, + msm_mux_NA, +}; + +static const char * const gpio_groups[] = { + "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7", + "gpio8", "gpio9", "gpio10", "gpio11", "gpio12", "gpio13", "gpio14", + "gpio15", "gpio16", "gpio17", "gpio18", "gpio19", "gpio20", "gpio21", + "gpio22", "gpio23", "gpio24", "gpio25", "gpio26", "gpio27", "gpio28", + "gpio29", "gpio30", "gpio31", "gpio32", "gpio33", "gpio34", "gpio35", + "gpio36", "gpio37", "gpio38", "gpio39", "gpio40", "gpio41", "gpio42", + "gpio43", "gpio44", "gpio45", "gpio46", "gpio47", "gpio48", "gpio49", + "gpio50", "gpio51", "gpio52", "gpio53", "gpio54", "gpio55", "gpio56", + "gpio57", "gpio58", "gpio59", "gpio60", "gpio61", "gpio62", "gpio63", + "gpio64", "gpio65", "gpio66", "gpio67", "gpio68", "gpio69", "gpio70", + "gpio71", "gpio72", "gpio73", "gpio74", "gpio75", "gpio76", "gpio77", + "gpio78", "gpio79", "gpio80", "gpio81", "gpio82", "gpio83", "gpio84", + "gpio85", "gpio86", "gpio87", "gpio88", "gpio89", "gpio90", "gpio91", + "gpio92", "gpio93", "gpio94", "gpio95", "gpio96", "gpio97", "gpio98", + "gpio99", "gpio100", "gpio101", "gpio102", "gpio103", "gpio104", + "gpio105", "gpio106", "gpio107", "gpio108", "gpio109", "gpio110", + "gpio111", "gpio112", "gpio113", "gpio114", "gpio115", "gpio116", + "gpio117", "gpio118", "gpio119", "gpio120", "gpio121" +}; +static const char * const adsp_ext_groups[] = { "gpio38" }; +static const char * const alsp_int_groups[] = { "gpio113" }; +static const char * const atest_bbrx0_groups[] = { "gpio17" }; +static const char * const atest_bbrx1_groups[] = { "gpio16" }; +static const char * const atest_char_groups[] = { "gpio62" }; +static const char * const atest_char0_groups[] = { "gpio60" }; +static const char * const atest_char1_groups[] = { "gpio59" }; +static const char * const atest_char2_groups[] = { "gpio58" }; +static const char * const atest_char3_groups[] = { "gpio57" }; +static const char * const atest_combodac_groups[] = { + "gpio4", "gpio12", "gpio13", "gpio20", "gpio21", "gpio28", "gpio29", + "gpio30", "gpio39", "gpio40", "gpio41", "gpio42", "gpio43", "gpio44", + "gpio45", "gpio46", "gpio47", "gpio48", "gpio69", "gpio107" +}; +static const char * const atest_gpsadc0_groups[] = { "gpio7" }; +static const char * const atest_gpsadc1_groups[] = { "gpio18" }; +static const char * const atest_tsens_groups[] = { "gpio112" }; +static const char * const atest_wlan0_groups[] = { "gpio22" }; +static const char * const atest_wlan1_groups[] = { "gpio23" }; +static const char * const backlight_en_groups[] = { "gpio98" }; +static const char * const bimc_dte0_groups[] = { "gpio63", "gpio65" }; +static const char * const bimc_dte1_groups[] = { "gpio64", "gpio66" }; +static const char * const blsp_i2c1_groups[] = { "gpio2", "gpio3" }; +static const char * const blsp_i2c2_groups[] = { "gpio6", "gpio7" }; +static const char * const blsp_i2c3_groups[] = { "gpio10", "gpio11" }; +static const char * const blsp_i2c4_groups[] = { "gpio14", "gpio15" }; +static const char * const blsp_i2c5_groups[] = { "gpio18", "gpio19" }; +static const char * const blsp_i2c6_groups[] = { "gpio22", "gpio23" }; +static const char * const blsp_spi1_groups[] = { + "gpio0", "gpio1", "gpio2", "gpio3" +}; +static const char * const blsp_spi1_cs1_groups[] = { "gpio110" }; +static const char * const blsp_spi1_cs2_groups[] = { "gpio16" }; +static const char * const blsp_spi1_cs3_groups[] = { "gpio4" }; +static const char * const blsp_spi2_groups[] = { + "gpio4", "gpio5", "gpio6", "gpio7" +}; +static const char * const blsp_spi2_cs1_groups[] = { "gpio121" }; +static const char * const blsp_spi2_cs2_groups[] = { "gpio17" }; +static const char * const blsp_spi2_cs3_groups[] = { "gpio5" }; +static const char * const blsp_spi3_groups[] = { + "gpio8", "gpio9", "gpio10", "gpio11" +}; +static const char * const blsp_spi3_cs1_groups[] = { "gpio120" }; +static const char * const blsp_spi3_cs2_groups[] = { "gpio37" }; +static const char * const blsp_spi3_cs3_groups[] = { "gpio69" }; +static const char * const blsp_spi4_groups[] = { + "gpio12", "gpio13", "gpio14", "gpio15" +}; +static const char * const blsp_spi5_groups[] = { + "gpio16", "gpio17", "gpio18", "gpio19" +}; +static const char * const blsp_spi6_groups[] = { + "gpio20", "gpio21", "gpio22", "gpio23" +}; +static const char * const blsp_uart1_groups[] = { + "gpio0", "gpio1", "gpio2", "gpio3" +}; +static const char * const blsp_uart2_groups[] = { + "gpio4", "gpio5", "gpio6", "gpio7" +}; +static const char * const blsp_uim1_groups[] = { "gpio0", "gpio1" }; +static const char * const blsp_uim2_groups[] = { "gpio4", "gpio5" }; +static const char * const cam1_rst_groups[] = { "gpio35" }; +static const char * const cam1_standby_groups[] = { "gpio34" }; +static const char * const cam_mclk0_groups[] = { "gpio26" }; +static const char * const cam_mclk1_groups[] = { "gpio27" }; +static const char * const cci_async_groups[] = { "gpio33" }; +static const char * const cci_i2c_groups[] = { "gpio29", "gpio30" }; +static const char * const cci_timer0_groups[] = { "gpio31" }; +static const char * const cci_timer1_groups[] = { "gpio32" }; +static const char * const cci_timer2_groups[] = { "gpio38" }; +static const char * const cdc_pdm0_groups[] = { + "gpio63", "gpio64", "gpio65", "gpio66", "gpio67", "gpio68" +}; +static const char * const codec_mad_groups[] = { "gpio16" }; +static const char * const dbg_out_groups[] = { "gpio47" }; +static const char * const display_5v_groups[] = { "gpio97" }; +static const char * const dmic0_clk_groups[] = { "gpio0" }; +static const char * const dmic0_data_groups[] = { "gpio1" }; +static const char * const dsi_rst_groups[] = { "gpio25" }; +static const char * const ebi0_wrcdc_groups[] = { "gpio67" }; +static const char * const euro_us_groups[] = { "gpio120" }; +static const char * const ext_lpass_groups[] = { "gpio45" }; +static const char * const flash_strobe_groups[] = { "gpio31", "gpio32" }; +static const char * const gcc_gp1_clk_a_groups[] = { "gpio49" }; +static const char * const gcc_gp1_clk_b_groups[] = { "gpio97" }; +static const char * const gcc_gp2_clk_a_groups[] = { "gpio50" }; +static const char * const gcc_gp2_clk_b_groups[] = { "gpio12" }; +static const char * const gcc_gp3_clk_a_groups[] = { "gpio51" }; +static const char * const gcc_gp3_clk_b_groups[] = { "gpio13" }; +static const char * const gsm0_tx0_groups[] = { "gpio99" }; +static const char * const gsm0_tx1_groups[] = { "gpio100" }; +static const char * const gsm1_tx0_groups[] = { "gpio101" }; +static const char * const gsm1_tx1_groups[] = { "gpio102" }; +static const char * const gyro_accl_groups[] = {"gpio115" }; +static const char * const kpsns0_groups[] = { "gpio107" }; +static const char * const kpsns1_groups[] = { "gpio108" }; +static const char * const kpsns2_groups[] = { "gpio109" }; +static const char * const ldo_en_groups[] = { "gpio121" }; +static const char * const ldo_update_groups[] = { "gpio120" }; +static const char * const mag_int_groups[] = { "gpio69" }; +static const char * const mdp_vsync_groups[] = { "gpio24", "gpio25" }; +static const char * const modem_tsync_groups[] = { "gpio95" }; +static const char * const m_voc_groups[] = { "gpio8", "gpio119" }; +static const char * const nav_pps_groups[] = { "gpio95" }; +static const char * const nav_tsync_groups[] = { "gpio95" }; +static const char * const pa_indicator_groups[] = { "gpio86" }; +static const char * const pbs0_groups[] = { "gpio107" }; +static const char * const pbs1_groups[] = { "gpio108" }; +static const char * const pbs2_groups[] = { "gpio109" }; +static const char * const pri_mi2s_groups[] = { + "gpio113", "gpio114", "gpio115", "gpio116" +}; +static const char * const pri_mi2s_ws_groups[] = { "gpio110" }; +static const char * const prng_rosc_groups[] = { "gpio43" }; +static const char * const pwr_crypto_enabled_a_groups[] = { "gpio35" }; +static const char * const pwr_crypto_enabled_b_groups[] = { "gpio115" }; +static const char * const pwr_modem_enabled_a_groups[] = { "gpio28" }; +static const char * const pwr_modem_enabled_b_groups[] = { "gpio113" }; +static const char * const pwr_nav_enabled_a_groups[] = { "gpio34" }; +static const char * const pwr_nav_enabled_b_groups[] = { "gpio114" }; +static const char * const qdss_ctitrig_in_a0_groups[] = { "gpio20" }; +static const char * const qdss_ctitrig_in_a1_groups[] = { "gpio49" }; +static const char * const qdss_ctitrig_in_b0_groups[] = { "gpio21" }; +static const char * const qdss_ctitrig_in_b1_groups[] = { "gpio50" }; +static const char * const qdss_ctitrig_out_a0_groups[] = { "gpio23" }; +static const char * const qdss_ctitrig_out_a1_groups[] = { "gpio52" }; +static const char * const qdss_ctitrig_out_b0_groups[] = { "gpio22" }; +static const char * const qdss_ctitrig_out_b1_groups[] = { "gpio51" }; +static const char * const qdss_traceclk_a_groups[] = { "gpio46" }; +static const char * const qdss_traceclk_b_groups[] = { "gpio5" }; +static const char * const qdss_tracectl_a_groups[] = { "gpio45" }; +static const char * const qdss_tracectl_b_groups[] = { "gpio4" }; +static const char * const qdss_tracedata_a_groups[] = { + "gpio8", "gpio9", "gpio10", "gpio39", "gpio40", "gpio41", "gpio42", + "gpio43", "gpio47", "gpio48", "gpio62", "gpio69", "gpio112", "gpio113", + "gpio114", "gpio115" +}; +static const char * const qdss_tracedata_b_groups[] = { + "gpio26", "gpio27", "gpio28", "gpio29", "gpio30", "gpio31", "gpio32", + "gpio33", "gpio34", "gpio35", "gpio36", "gpio37", "gpio110", "gpio111", + "gpio120", "gpio121" +}; +static const char * const reset_n_groups[] = { "gpio36" }; +static const char * const sd_card_groups[] = { "gpio38" }; +static const char * const sd_write_groups[] = { "gpio121" }; +static const char * const sec_mi2s_groups[] = { + "gpio112", "gpio117", "gpio118", "gpio119" +}; +static const char * const smb_int_groups[] = { "gpio62" }; +static const char * const ssbi_wtr0_groups[] = { "gpio103", "gpio104" }; +static const char * const ssbi_wtr1_groups[] = { "gpio105", "gpio106" }; +static const char * const uim1_groups[] = { + "gpio57", "gpio58", "gpio59", "gpio60" +}; + +static const char * const uim2_groups[] = { + "gpio53", "gpio54", "gpio55", "gpio56" +}; +static const char * const uim3_groups[] = { + "gpio49", "gpio50", "gpio51", "gpio52" +}; +static const char * const uim_batt_groups[] = { "gpio61" }; +static const char * const wcss_bt_groups[] = { "gpio39", "gpio47", "gpio48" }; +static const char * const wcss_fm_groups[] = { "gpio45", "gpio46" }; +static const char * const wcss_wlan_groups[] = { + "gpio40", "gpio41", "gpio42", "gpio43", "gpio44" +}; +static const char * const webcam1_rst_groups[] = { "gpio28" }; + +static const struct pinfunction msm8916_functions[] = { + MSM_PIN_FUNCTION(adsp_ext), + MSM_PIN_FUNCTION(alsp_int), + MSM_PIN_FUNCTION(atest_bbrx0), + MSM_PIN_FUNCTION(atest_bbrx1), + MSM_PIN_FUNCTION(atest_char), + MSM_PIN_FUNCTION(atest_char0), + MSM_PIN_FUNCTION(atest_char1), + MSM_PIN_FUNCTION(atest_char2), + MSM_PIN_FUNCTION(atest_char3), + MSM_PIN_FUNCTION(atest_combodac), + MSM_PIN_FUNCTION(atest_gpsadc0), + MSM_PIN_FUNCTION(atest_gpsadc1), + MSM_PIN_FUNCTION(atest_tsens), + MSM_PIN_FUNCTION(atest_wlan0), + MSM_PIN_FUNCTION(atest_wlan1), + MSM_PIN_FUNCTION(backlight_en), + MSM_PIN_FUNCTION(bimc_dte0), + MSM_PIN_FUNCTION(bimc_dte1), + MSM_PIN_FUNCTION(blsp_i2c1), + MSM_PIN_FUNCTION(blsp_i2c2), + MSM_PIN_FUNCTION(blsp_i2c3), + MSM_PIN_FUNCTION(blsp_i2c4), + MSM_PIN_FUNCTION(blsp_i2c5), + MSM_PIN_FUNCTION(blsp_i2c6), + MSM_PIN_FUNCTION(blsp_spi1), + MSM_PIN_FUNCTION(blsp_spi1_cs1), + MSM_PIN_FUNCTION(blsp_spi1_cs2), + MSM_PIN_FUNCTION(blsp_spi1_cs3), + MSM_PIN_FUNCTION(blsp_spi2), + MSM_PIN_FUNCTION(blsp_spi2_cs1), + MSM_PIN_FUNCTION(blsp_spi2_cs2), + MSM_PIN_FUNCTION(blsp_spi2_cs3), + MSM_PIN_FUNCTION(blsp_spi3), + MSM_PIN_FUNCTION(blsp_spi3_cs1), + MSM_PIN_FUNCTION(blsp_spi3_cs2), + MSM_PIN_FUNCTION(blsp_spi3_cs3), + MSM_PIN_FUNCTION(blsp_spi4), + MSM_PIN_FUNCTION(blsp_spi5), + MSM_PIN_FUNCTION(blsp_spi6), + MSM_PIN_FUNCTION(blsp_uart1), + MSM_PIN_FUNCTION(blsp_uart2), + MSM_PIN_FUNCTION(blsp_uim1), + MSM_PIN_FUNCTION(blsp_uim2), + MSM_PIN_FUNCTION(cam1_rst), + MSM_PIN_FUNCTION(cam1_standby), + MSM_PIN_FUNCTION(cam_mclk0), + MSM_PIN_FUNCTION(cam_mclk1), + MSM_PIN_FUNCTION(cci_async), + MSM_PIN_FUNCTION(cci_i2c), + MSM_PIN_FUNCTION(cci_timer0), + MSM_PIN_FUNCTION(cci_timer1), + MSM_PIN_FUNCTION(cci_timer2), + MSM_PIN_FUNCTION(cdc_pdm0), + MSM_PIN_FUNCTION(codec_mad), + MSM_PIN_FUNCTION(dbg_out), + MSM_PIN_FUNCTION(display_5v), + MSM_PIN_FUNCTION(dmic0_clk), + MSM_PIN_FUNCTION(dmic0_data), + MSM_PIN_FUNCTION(dsi_rst), + MSM_PIN_FUNCTION(ebi0_wrcdc), + MSM_PIN_FUNCTION(euro_us), + MSM_PIN_FUNCTION(ext_lpass), + MSM_PIN_FUNCTION(flash_strobe), + MSM_PIN_FUNCTION(gcc_gp1_clk_a), + MSM_PIN_FUNCTION(gcc_gp1_clk_b), + MSM_PIN_FUNCTION(gcc_gp2_clk_a), + MSM_PIN_FUNCTION(gcc_gp2_clk_b), + MSM_PIN_FUNCTION(gcc_gp3_clk_a), + MSM_PIN_FUNCTION(gcc_gp3_clk_b), + MSM_PIN_FUNCTION(gpio), + MSM_PIN_FUNCTION(gsm0_tx0), + MSM_PIN_FUNCTION(gsm0_tx1), + MSM_PIN_FUNCTION(gsm1_tx0), + MSM_PIN_FUNCTION(gsm1_tx1), + MSM_PIN_FUNCTION(gyro_accl), + MSM_PIN_FUNCTION(kpsns0), + MSM_PIN_FUNCTION(kpsns1), + MSM_PIN_FUNCTION(kpsns2), + MSM_PIN_FUNCTION(ldo_en), + MSM_PIN_FUNCTION(ldo_update), + MSM_PIN_FUNCTION(mag_int), + MSM_PIN_FUNCTION(mdp_vsync), + MSM_PIN_FUNCTION(modem_tsync), + MSM_PIN_FUNCTION(m_voc), + MSM_PIN_FUNCTION(nav_pps), + MSM_PIN_FUNCTION(nav_tsync), + MSM_PIN_FUNCTION(pa_indicator), + MSM_PIN_FUNCTION(pbs0), + MSM_PIN_FUNCTION(pbs1), + MSM_PIN_FUNCTION(pbs2), + MSM_PIN_FUNCTION(pri_mi2s), + MSM_PIN_FUNCTION(pri_mi2s_ws), + MSM_PIN_FUNCTION(prng_rosc), + MSM_PIN_FUNCTION(pwr_crypto_enabled_a), + MSM_PIN_FUNCTION(pwr_crypto_enabled_b), + MSM_PIN_FUNCTION(pwr_modem_enabled_a), + MSM_PIN_FUNCTION(pwr_modem_enabled_b), + MSM_PIN_FUNCTION(pwr_nav_enabled_a), + MSM_PIN_FUNCTION(pwr_nav_enabled_b), + MSM_PIN_FUNCTION(qdss_ctitrig_in_a0), + MSM_PIN_FUNCTION(qdss_ctitrig_in_a1), + MSM_PIN_FUNCTION(qdss_ctitrig_in_b0), + MSM_PIN_FUNCTION(qdss_ctitrig_in_b1), + MSM_PIN_FUNCTION(qdss_ctitrig_out_a0), + MSM_PIN_FUNCTION(qdss_ctitrig_out_a1), + MSM_PIN_FUNCTION(qdss_ctitrig_out_b0), + MSM_PIN_FUNCTION(qdss_ctitrig_out_b1), + MSM_PIN_FUNCTION(qdss_traceclk_a), + MSM_PIN_FUNCTION(qdss_traceclk_b), + MSM_PIN_FUNCTION(qdss_tracectl_a), + MSM_PIN_FUNCTION(qdss_tracectl_b), + MSM_PIN_FUNCTION(qdss_tracedata_a), + MSM_PIN_FUNCTION(qdss_tracedata_b), + MSM_PIN_FUNCTION(reset_n), + MSM_PIN_FUNCTION(sd_card), + MSM_PIN_FUNCTION(sd_write), + MSM_PIN_FUNCTION(sec_mi2s), + MSM_PIN_FUNCTION(smb_int), + MSM_PIN_FUNCTION(ssbi_wtr0), + MSM_PIN_FUNCTION(ssbi_wtr1), + MSM_PIN_FUNCTION(uim1), + MSM_PIN_FUNCTION(uim2), + MSM_PIN_FUNCTION(uim3), + MSM_PIN_FUNCTION(uim_batt), + MSM_PIN_FUNCTION(wcss_bt), + MSM_PIN_FUNCTION(wcss_fm), + MSM_PIN_FUNCTION(wcss_wlan), + MSM_PIN_FUNCTION(webcam1_rst) +}; + +static const struct msm_pingroup msm8916_groups[] = { + PINGROUP(0, blsp_spi1, blsp_uart1, blsp_uim1, dmic0_clk, NA, NA, NA, NA, NA), + PINGROUP(1, blsp_spi1, blsp_uart1, blsp_uim1, dmic0_data, NA, NA, NA, NA, NA), + PINGROUP(2, blsp_spi1, blsp_uart1, blsp_i2c1, NA, NA, NA, NA, NA, NA), + PINGROUP(3, blsp_spi1, blsp_uart1, blsp_i2c1, NA, NA, NA, NA, NA, NA), + PINGROUP(4, blsp_spi2, blsp_uart2, blsp_uim2, blsp_spi1_cs3, qdss_tracectl_b, NA, atest_combodac, NA, NA), + PINGROUP(5, blsp_spi2, blsp_uart2, blsp_uim2, blsp_spi2_cs3, qdss_traceclk_b, NA, NA, NA, NA), + PINGROUP(6, blsp_spi2, blsp_uart2, blsp_i2c2, NA, NA, NA, NA, NA, NA), + PINGROUP(7, blsp_spi2, blsp_uart2, blsp_i2c2, NA, NA, NA, NA, NA, NA), + PINGROUP(8, blsp_spi3, m_voc, qdss_tracedata_a, NA, NA, NA, NA, NA, NA), + PINGROUP(9, blsp_spi3, qdss_tracedata_a, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(10, blsp_spi3, blsp_i2c3, qdss_tracedata_a, NA, NA, NA, NA, NA, NA), + PINGROUP(11, blsp_spi3, blsp_i2c3, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(12, blsp_spi4, gcc_gp2_clk_b, NA, atest_combodac, NA, NA, NA, NA, NA), + PINGROUP(13, blsp_spi4, gcc_gp3_clk_b, NA, atest_combodac, NA, NA, NA, NA, NA), + PINGROUP(14, blsp_spi4, blsp_i2c4, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(15, blsp_spi4, blsp_i2c4, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(16, blsp_spi5, blsp_spi1_cs2, NA, atest_bbrx1, NA, NA, NA, NA, NA), + PINGROUP(17, blsp_spi5, blsp_spi2_cs2, NA, atest_bbrx0, NA, NA, NA, NA, NA), + PINGROUP(18, blsp_spi5, blsp_i2c5, NA, atest_gpsadc1, NA, NA, NA, NA, NA), + PINGROUP(19, blsp_spi5, blsp_i2c5, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(20, blsp_spi6, NA, NA, NA, NA, NA, NA, qdss_ctitrig_in_a0, NA), + PINGROUP(21, blsp_spi6, NA, NA, NA, NA, NA, NA, qdss_ctitrig_in_b0, NA), + PINGROUP(22, blsp_spi6, blsp_i2c6, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(23, blsp_spi6, blsp_i2c6, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(24, mdp_vsync, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(25, mdp_vsync, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(26, cam_mclk0, NA, NA, NA, NA, NA, qdss_tracedata_b, NA, NA), + PINGROUP(27, cam_mclk1, NA, NA, NA, NA, NA, NA, NA, qdss_tracedata_b), + PINGROUP(28, pwr_modem_enabled_a, NA, NA, NA, NA, NA, qdss_tracedata_b, NA, atest_combodac), + PINGROUP(29, cci_i2c, NA, NA, NA, NA, NA, qdss_tracedata_b, NA, atest_combodac), + PINGROUP(30, cci_i2c, NA, NA, NA, NA, NA, NA, NA, qdss_tracedata_b), + PINGROUP(31, cci_timer0, flash_strobe, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(32, cci_timer1, flash_strobe, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(33, cci_async, NA, NA, NA, NA, NA, NA, NA, qdss_tracedata_b), + PINGROUP(34, pwr_nav_enabled_a, NA, NA, NA, NA, NA, NA, NA, qdss_tracedata_b), + PINGROUP(35, pwr_crypto_enabled_a, NA, NA, NA, NA, NA, NA, NA, qdss_tracedata_b), + PINGROUP(36, NA, NA, NA, NA, NA, NA, NA, qdss_tracedata_b, NA), + PINGROUP(37, blsp_spi3_cs2, NA, NA, NA, NA, NA, qdss_tracedata_b, NA, NA), + PINGROUP(38, cci_timer2, adsp_ext, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(39, wcss_bt, qdss_tracedata_a, NA, atest_combodac, NA, NA, NA, NA, NA), + PINGROUP(40, wcss_wlan, qdss_tracedata_a, NA, atest_combodac, NA, NA, NA, NA, NA), + PINGROUP(41, wcss_wlan, qdss_tracedata_a, NA, atest_combodac, NA, NA, NA, NA, NA), + PINGROUP(42, wcss_wlan, qdss_tracedata_a, NA, atest_combodac, NA, NA, NA, NA, NA), + PINGROUP(43, wcss_wlan, prng_rosc, qdss_tracedata_a, NA, atest_combodac, NA, NA, NA, NA), + PINGROUP(44, wcss_wlan, NA, atest_combodac, NA, NA, NA, NA, NA, NA), + PINGROUP(45, wcss_fm, ext_lpass, qdss_tracectl_a, NA, atest_combodac, NA, NA, NA, NA), + PINGROUP(46, wcss_fm, qdss_traceclk_a, NA, atest_combodac, NA, NA, NA, NA, NA), + PINGROUP(47, wcss_bt, dbg_out, qdss_tracedata_a, NA, atest_combodac, NA, NA, NA, NA), + PINGROUP(48, wcss_bt, qdss_tracedata_a, NA, atest_combodac, NA, NA, NA, NA, NA), + PINGROUP(49, uim3, gcc_gp1_clk_a, qdss_ctitrig_in_a1, NA, NA, NA, NA, NA, NA), + PINGROUP(50, uim3, gcc_gp2_clk_a, qdss_ctitrig_in_b1, NA, NA, NA, NA, NA, NA), + PINGROUP(51, uim3, gcc_gp3_clk_a, qdss_ctitrig_out_b1, NA, NA, NA, NA, NA, NA), + PINGROUP(52, uim3, NA, qdss_ctitrig_out_a1, NA, NA, NA, NA, NA, NA), + PINGROUP(53, uim2, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(54, uim2, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(55, uim2, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(56, uim2, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(57, uim1, atest_char3, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(58, uim1, atest_char2, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(59, uim1, atest_char1, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(60, uim1, atest_char0, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(61, uim_batt, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(62, atest_char, qdss_tracedata_a, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(63, cdc_pdm0, bimc_dte0, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(64, cdc_pdm0, bimc_dte1, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(65, cdc_pdm0, bimc_dte0, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(66, cdc_pdm0, bimc_dte1, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(67, cdc_pdm0, ebi0_wrcdc, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(68, cdc_pdm0, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(69, blsp_spi3_cs3, qdss_tracedata_a, NA, atest_combodac, NA, NA, NA, NA, NA), + PINGROUP(70, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(71, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(72, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(73, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(74, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(75, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(76, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(77, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(78, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(79, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(80, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(81, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(82, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(83, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(84, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(85, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(86, NA, pa_indicator, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(87, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(88, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(89, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(90, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(91, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(92, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(93, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(94, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(95, NA, modem_tsync, nav_tsync, nav_pps, NA, NA, NA, NA, NA), + PINGROUP(96, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(97, gcc_gp1_clk_b, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(98, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(99, gsm0_tx0, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(100, gsm0_tx1, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(101, gsm1_tx0, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(102, gsm1_tx1, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(103, ssbi_wtr0, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(104, ssbi_wtr0, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(105, ssbi_wtr1, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(106, ssbi_wtr1, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(107, pbs0, NA, atest_combodac, NA, NA, NA, NA, NA, NA), + PINGROUP(108, pbs1, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(109, pbs2, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(110, blsp_spi1_cs1, pri_mi2s_ws, NA, qdss_tracedata_b, NA, NA, NA, NA, NA), + PINGROUP(111, qdss_tracedata_b, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(112, sec_mi2s, NA, NA, NA, qdss_tracedata_a, NA, atest_tsens, NA, NA), + PINGROUP(113, pri_mi2s, NA, pwr_modem_enabled_b, NA, NA, NA, NA, NA, qdss_tracedata_a), + PINGROUP(114, pri_mi2s, pwr_nav_enabled_b, NA, NA, NA, NA, NA, qdss_tracedata_a, NA), + PINGROUP(115, pri_mi2s, pwr_crypto_enabled_b, NA, NA, NA, NA, NA, qdss_tracedata_a, NA), + PINGROUP(116, pri_mi2s, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(117, sec_mi2s, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(118, sec_mi2s, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(119, sec_mi2s, m_voc, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(120, blsp_spi3_cs1, ldo_update, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(121, sd_write, blsp_spi2_cs1, ldo_en, NA, NA, NA, NA, NA, NA), + SDC_PINGROUP(sdc1_clk, 0x10a000, 13, 6), + SDC_PINGROUP(sdc1_cmd, 0x10a000, 11, 3), + SDC_PINGROUP(sdc1_data, 0x10a000, 9, 0), + SDC_PINGROUP(sdc2_clk, 0x109000, 14, 6), + SDC_PINGROUP(sdc2_cmd, 0x109000, 11, 3), + SDC_PINGROUP(sdc2_data, 0x109000, 9, 0), + SDC_PINGROUP(qdsd_clk, 0x19c000, 3, 0), + SDC_PINGROUP(qdsd_cmd, 0x19c000, 8, 5), + SDC_PINGROUP(qdsd_data0, 0x19c000, 13, 10), + SDC_PINGROUP(qdsd_data1, 0x19c000, 18, 15), + SDC_PINGROUP(qdsd_data2, 0x19c000, 23, 20), + SDC_PINGROUP(qdsd_data3, 0x19c000, 28, 25), +}; + +#define NUM_GPIO_PINGROUPS 122 + +static const struct msm_pinctrl_soc_data msm8916_pinctrl = { + .pins = msm8916_pins, + .npins = ARRAY_SIZE(msm8916_pins), + .functions = msm8916_functions, + .nfunctions = ARRAY_SIZE(msm8916_functions), + .groups = msm8916_groups, + .ngroups = ARRAY_SIZE(msm8916_groups), + .ngpios = NUM_GPIO_PINGROUPS, +}; + +static int msm8916_pinctrl_probe(struct platform_device *pdev) +{ + return msm_pinctrl_probe(pdev, &msm8916_pinctrl); +} + +static const struct of_device_id msm8916_pinctrl_of_match[] = { + { .compatible = "qcom,msm8916-pinctrl", }, + { }, +}; + +static struct platform_driver msm8916_pinctrl_driver = { + .driver = { + .name = "msm8916-pinctrl", + .of_match_table = msm8916_pinctrl_of_match, + }, + .probe = msm8916_pinctrl_probe, + .remove = msm_pinctrl_remove, +}; + +static int __init msm8916_pinctrl_init(void) +{ + return platform_driver_register(&msm8916_pinctrl_driver); +} +arch_initcall(msm8916_pinctrl_init); + +static void __exit msm8916_pinctrl_exit(void) +{ + platform_driver_unregister(&msm8916_pinctrl_driver); +} +module_exit(msm8916_pinctrl_exit); + +MODULE_DESCRIPTION("Qualcomm msm8916 pinctrl driver"); +MODULE_LICENSE("GPL v2"); +MODULE_DEVICE_TABLE(of, msm8916_pinctrl_of_match); diff --git a/drivers/pinctrl/qcom/pinctrl-msm8953.c b/drivers/pinctrl/qcom/pinctrl-msm8953.c new file mode 100644 index 0000000000..998351bdfe --- /dev/null +++ b/drivers/pinctrl/qcom/pinctrl-msm8953.c @@ -0,0 +1,1836 @@ +// SPDX-License-Identifier: GPL-2.0 +// Copyright (c) 2020, The Linux Foundation. All rights reserved. + +#include <linux/module.h> +#include <linux/of.h> +#include <linux/platform_device.h> + +#include "pinctrl-msm.h" + +#define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7, f8, f9) \ + { \ + .grp = PINCTRL_PINGROUP("gpio" #id, \ + gpio##id##_pins, \ + ARRAY_SIZE(gpio##id##_pins)), \ + .funcs = (int[]){ \ + msm_mux_gpio, /* gpio mode */ \ + msm_mux_##f1, \ + msm_mux_##f2, \ + msm_mux_##f3, \ + msm_mux_##f4, \ + msm_mux_##f5, \ + msm_mux_##f6, \ + msm_mux_##f7, \ + msm_mux_##f8, \ + msm_mux_##f9 \ + }, \ + .nfuncs = 10, \ + .ctl_reg = 0x1000 * id, \ + .io_reg = 0x4 + 0x1000 * id, \ + .intr_cfg_reg = 0x8 + 0x1000 * id, \ + .intr_status_reg = 0xc + 0x1000 * id, \ + .intr_target_reg = 0x8 + 0x1000 * id, \ + .mux_bit = 2, \ + .pull_bit = 0, \ + .drv_bit = 6, \ + .oe_bit = 9, \ + .in_bit = 0, \ + .out_bit = 1, \ + .intr_enable_bit = 0, \ + .intr_status_bit = 0, \ + .intr_target_bit = 5, \ + .intr_target_kpss_val = 4, \ + .intr_raw_status_bit = 4, \ + .intr_polarity_bit = 1, \ + .intr_detection_bit = 2, \ + .intr_detection_width = 2, \ + } + +#define SDC_QDSD_PINGROUP(pg_name, ctl, pull, drv) \ + { \ + .grp = PINCTRL_PINGROUP(#pg_name, \ + pg_name##_pins, \ + ARRAY_SIZE(pg_name##_pins)), \ + .ctl_reg = ctl, \ + .io_reg = 0, \ + .intr_cfg_reg = 0, \ + .intr_status_reg = 0, \ + .intr_target_reg = 0, \ + .mux_bit = -1, \ + .pull_bit = pull, \ + .drv_bit = drv, \ + .oe_bit = -1, \ + .in_bit = -1, \ + .out_bit = -1, \ + .intr_enable_bit = -1, \ + .intr_status_bit = -1, \ + .intr_target_bit = -1, \ + .intr_raw_status_bit = -1, \ + .intr_polarity_bit = -1, \ + .intr_detection_bit = -1, \ + .intr_detection_width = -1, \ + } + +static const struct pinctrl_pin_desc msm8953_pins[] = { + PINCTRL_PIN(0, "GPIO_0"), + PINCTRL_PIN(1, "GPIO_1"), + PINCTRL_PIN(2, "GPIO_2"), + PINCTRL_PIN(3, "GPIO_3"), + PINCTRL_PIN(4, "GPIO_4"), + PINCTRL_PIN(5, "GPIO_5"), + PINCTRL_PIN(6, "GPIO_6"), + PINCTRL_PIN(7, "GPIO_7"), + PINCTRL_PIN(8, "GPIO_8"), + PINCTRL_PIN(9, "GPIO_9"), + PINCTRL_PIN(10, "GPIO_10"), + PINCTRL_PIN(11, "GPIO_11"), + PINCTRL_PIN(12, "GPIO_12"), + PINCTRL_PIN(13, "GPIO_13"), + PINCTRL_PIN(14, "GPIO_14"), + PINCTRL_PIN(15, "GPIO_15"), + PINCTRL_PIN(16, "GPIO_16"), + PINCTRL_PIN(17, "GPIO_17"), + PINCTRL_PIN(18, "GPIO_18"), + PINCTRL_PIN(19, "GPIO_19"), + PINCTRL_PIN(20, "GPIO_20"), + PINCTRL_PIN(21, "GPIO_21"), + PINCTRL_PIN(22, "GPIO_22"), + PINCTRL_PIN(23, "GPIO_23"), + PINCTRL_PIN(24, "GPIO_24"), + PINCTRL_PIN(25, "GPIO_25"), + PINCTRL_PIN(26, "GPIO_26"), + PINCTRL_PIN(27, "GPIO_27"), + PINCTRL_PIN(28, "GPIO_28"), + PINCTRL_PIN(29, "GPIO_29"), + PINCTRL_PIN(30, "GPIO_30"), + PINCTRL_PIN(31, "GPIO_31"), + PINCTRL_PIN(32, "GPIO_32"), + PINCTRL_PIN(33, "GPIO_33"), + PINCTRL_PIN(34, "GPIO_34"), + PINCTRL_PIN(35, "GPIO_35"), + PINCTRL_PIN(36, "GPIO_36"), + PINCTRL_PIN(37, "GPIO_37"), + PINCTRL_PIN(38, "GPIO_38"), + PINCTRL_PIN(39, "GPIO_39"), + PINCTRL_PIN(40, "GPIO_40"), + PINCTRL_PIN(41, "GPIO_41"), + PINCTRL_PIN(42, "GPIO_42"), + PINCTRL_PIN(43, "GPIO_43"), + PINCTRL_PIN(44, "GPIO_44"), + PINCTRL_PIN(45, "GPIO_45"), + PINCTRL_PIN(46, "GPIO_46"), + PINCTRL_PIN(47, "GPIO_47"), + PINCTRL_PIN(48, "GPIO_48"), + PINCTRL_PIN(49, "GPIO_49"), + PINCTRL_PIN(50, "GPIO_50"), + PINCTRL_PIN(51, "GPIO_51"), + PINCTRL_PIN(52, "GPIO_52"), + PINCTRL_PIN(53, "GPIO_53"), + PINCTRL_PIN(54, "GPIO_54"), + PINCTRL_PIN(55, "GPIO_55"), + PINCTRL_PIN(56, "GPIO_56"), + PINCTRL_PIN(57, "GPIO_57"), + PINCTRL_PIN(58, "GPIO_58"), + PINCTRL_PIN(59, "GPIO_59"), + PINCTRL_PIN(60, "GPIO_60"), + PINCTRL_PIN(61, "GPIO_61"), + PINCTRL_PIN(62, "GPIO_62"), + PINCTRL_PIN(63, "GPIO_63"), + PINCTRL_PIN(64, "GPIO_64"), + PINCTRL_PIN(65, "GPIO_65"), + PINCTRL_PIN(66, "GPIO_66"), + PINCTRL_PIN(67, "GPIO_67"), + PINCTRL_PIN(68, "GPIO_68"), + PINCTRL_PIN(69, "GPIO_69"), + PINCTRL_PIN(70, "GPIO_70"), + PINCTRL_PIN(71, "GPIO_71"), + PINCTRL_PIN(72, "GPIO_72"), + PINCTRL_PIN(73, "GPIO_73"), + PINCTRL_PIN(74, "GPIO_74"), + PINCTRL_PIN(75, "GPIO_75"), + PINCTRL_PIN(76, "GPIO_76"), + PINCTRL_PIN(77, "GPIO_77"), + PINCTRL_PIN(78, "GPIO_78"), + PINCTRL_PIN(79, "GPIO_79"), + PINCTRL_PIN(80, "GPIO_80"), + PINCTRL_PIN(81, "GPIO_81"), + PINCTRL_PIN(82, "GPIO_82"), + PINCTRL_PIN(83, "GPIO_83"), + PINCTRL_PIN(84, "GPIO_84"), + PINCTRL_PIN(85, "GPIO_85"), + PINCTRL_PIN(86, "GPIO_86"), + PINCTRL_PIN(87, "GPIO_87"), + PINCTRL_PIN(88, "GPIO_88"), + PINCTRL_PIN(89, "GPIO_89"), + PINCTRL_PIN(90, "GPIO_90"), + PINCTRL_PIN(91, "GPIO_91"), + PINCTRL_PIN(92, "GPIO_92"), + PINCTRL_PIN(93, "GPIO_93"), + PINCTRL_PIN(94, "GPIO_94"), + PINCTRL_PIN(95, "GPIO_95"), + PINCTRL_PIN(96, "GPIO_96"), + PINCTRL_PIN(97, "GPIO_97"), + PINCTRL_PIN(98, "GPIO_98"), + PINCTRL_PIN(99, "GPIO_99"), + PINCTRL_PIN(100, "GPIO_100"), + PINCTRL_PIN(101, "GPIO_101"), + PINCTRL_PIN(102, "GPIO_102"), + PINCTRL_PIN(103, "GPIO_103"), + PINCTRL_PIN(104, "GPIO_104"), + PINCTRL_PIN(105, "GPIO_105"), + PINCTRL_PIN(106, "GPIO_106"), + PINCTRL_PIN(107, "GPIO_107"), + PINCTRL_PIN(108, "GPIO_108"), + PINCTRL_PIN(109, "GPIO_109"), + PINCTRL_PIN(110, "GPIO_110"), + PINCTRL_PIN(111, "GPIO_111"), + PINCTRL_PIN(112, "GPIO_112"), + PINCTRL_PIN(113, "GPIO_113"), + PINCTRL_PIN(114, "GPIO_114"), + PINCTRL_PIN(115, "GPIO_115"), + PINCTRL_PIN(116, "GPIO_116"), + PINCTRL_PIN(117, "GPIO_117"), + PINCTRL_PIN(118, "GPIO_118"), + PINCTRL_PIN(119, "GPIO_119"), + PINCTRL_PIN(120, "GPIO_120"), + PINCTRL_PIN(121, "GPIO_121"), + PINCTRL_PIN(122, "GPIO_122"), + PINCTRL_PIN(123, "GPIO_123"), + PINCTRL_PIN(124, "GPIO_124"), + PINCTRL_PIN(125, "GPIO_125"), + PINCTRL_PIN(126, "GPIO_126"), + PINCTRL_PIN(127, "GPIO_127"), + PINCTRL_PIN(128, "GPIO_128"), + PINCTRL_PIN(129, "GPIO_129"), + PINCTRL_PIN(130, "GPIO_130"), + PINCTRL_PIN(131, "GPIO_131"), + PINCTRL_PIN(132, "GPIO_132"), + PINCTRL_PIN(133, "GPIO_133"), + PINCTRL_PIN(134, "GPIO_134"), + PINCTRL_PIN(135, "GPIO_135"), + PINCTRL_PIN(136, "GPIO_136"), + PINCTRL_PIN(137, "GPIO_137"), + PINCTRL_PIN(138, "GPIO_138"), + PINCTRL_PIN(139, "GPIO_139"), + PINCTRL_PIN(140, "GPIO_140"), + PINCTRL_PIN(141, "GPIO_141"), + PINCTRL_PIN(142, "SDC1_CLK"), + PINCTRL_PIN(143, "SDC1_CMD"), + PINCTRL_PIN(144, "SDC1_DATA"), + PINCTRL_PIN(145, "SDC1_RCLK"), + PINCTRL_PIN(146, "SDC2_CLK"), + PINCTRL_PIN(147, "SDC2_CMD"), + PINCTRL_PIN(148, "SDC2_DATA"), + PINCTRL_PIN(149, "QDSD_CLK"), + PINCTRL_PIN(150, "QDSD_CMD"), + PINCTRL_PIN(151, "QDSD_DATA0"), + PINCTRL_PIN(152, "QDSD_DATA1"), + PINCTRL_PIN(153, "QDSD_DATA2"), + PINCTRL_PIN(154, "QDSD_DATA3"), +}; + +#define DECLARE_MSM_GPIO_PINS(pin) \ + static const unsigned int gpio##pin##_pins[] = { pin } +DECLARE_MSM_GPIO_PINS(0); +DECLARE_MSM_GPIO_PINS(1); +DECLARE_MSM_GPIO_PINS(2); +DECLARE_MSM_GPIO_PINS(3); +DECLARE_MSM_GPIO_PINS(4); +DECLARE_MSM_GPIO_PINS(5); +DECLARE_MSM_GPIO_PINS(6); +DECLARE_MSM_GPIO_PINS(7); +DECLARE_MSM_GPIO_PINS(8); +DECLARE_MSM_GPIO_PINS(9); +DECLARE_MSM_GPIO_PINS(10); +DECLARE_MSM_GPIO_PINS(11); +DECLARE_MSM_GPIO_PINS(12); +DECLARE_MSM_GPIO_PINS(13); +DECLARE_MSM_GPIO_PINS(14); +DECLARE_MSM_GPIO_PINS(15); +DECLARE_MSM_GPIO_PINS(16); +DECLARE_MSM_GPIO_PINS(17); +DECLARE_MSM_GPIO_PINS(18); +DECLARE_MSM_GPIO_PINS(19); +DECLARE_MSM_GPIO_PINS(20); +DECLARE_MSM_GPIO_PINS(21); +DECLARE_MSM_GPIO_PINS(22); +DECLARE_MSM_GPIO_PINS(23); +DECLARE_MSM_GPIO_PINS(24); +DECLARE_MSM_GPIO_PINS(25); +DECLARE_MSM_GPIO_PINS(26); +DECLARE_MSM_GPIO_PINS(27); +DECLARE_MSM_GPIO_PINS(28); +DECLARE_MSM_GPIO_PINS(29); +DECLARE_MSM_GPIO_PINS(30); +DECLARE_MSM_GPIO_PINS(31); +DECLARE_MSM_GPIO_PINS(32); +DECLARE_MSM_GPIO_PINS(33); +DECLARE_MSM_GPIO_PINS(34); +DECLARE_MSM_GPIO_PINS(35); +DECLARE_MSM_GPIO_PINS(36); +DECLARE_MSM_GPIO_PINS(37); +DECLARE_MSM_GPIO_PINS(38); +DECLARE_MSM_GPIO_PINS(39); +DECLARE_MSM_GPIO_PINS(40); +DECLARE_MSM_GPIO_PINS(41); +DECLARE_MSM_GPIO_PINS(42); +DECLARE_MSM_GPIO_PINS(43); +DECLARE_MSM_GPIO_PINS(44); +DECLARE_MSM_GPIO_PINS(45); +DECLARE_MSM_GPIO_PINS(46); +DECLARE_MSM_GPIO_PINS(47); +DECLARE_MSM_GPIO_PINS(48); +DECLARE_MSM_GPIO_PINS(49); +DECLARE_MSM_GPIO_PINS(50); +DECLARE_MSM_GPIO_PINS(51); +DECLARE_MSM_GPIO_PINS(52); +DECLARE_MSM_GPIO_PINS(53); +DECLARE_MSM_GPIO_PINS(54); +DECLARE_MSM_GPIO_PINS(55); +DECLARE_MSM_GPIO_PINS(56); +DECLARE_MSM_GPIO_PINS(57); +DECLARE_MSM_GPIO_PINS(58); +DECLARE_MSM_GPIO_PINS(59); +DECLARE_MSM_GPIO_PINS(60); +DECLARE_MSM_GPIO_PINS(61); +DECLARE_MSM_GPIO_PINS(62); +DECLARE_MSM_GPIO_PINS(63); +DECLARE_MSM_GPIO_PINS(64); +DECLARE_MSM_GPIO_PINS(65); +DECLARE_MSM_GPIO_PINS(66); +DECLARE_MSM_GPIO_PINS(67); +DECLARE_MSM_GPIO_PINS(68); +DECLARE_MSM_GPIO_PINS(69); +DECLARE_MSM_GPIO_PINS(70); +DECLARE_MSM_GPIO_PINS(71); +DECLARE_MSM_GPIO_PINS(72); +DECLARE_MSM_GPIO_PINS(73); +DECLARE_MSM_GPIO_PINS(74); +DECLARE_MSM_GPIO_PINS(75); +DECLARE_MSM_GPIO_PINS(76); +DECLARE_MSM_GPIO_PINS(77); +DECLARE_MSM_GPIO_PINS(78); +DECLARE_MSM_GPIO_PINS(79); +DECLARE_MSM_GPIO_PINS(80); +DECLARE_MSM_GPIO_PINS(81); +DECLARE_MSM_GPIO_PINS(82); +DECLARE_MSM_GPIO_PINS(83); +DECLARE_MSM_GPIO_PINS(84); +DECLARE_MSM_GPIO_PINS(85); +DECLARE_MSM_GPIO_PINS(86); +DECLARE_MSM_GPIO_PINS(87); +DECLARE_MSM_GPIO_PINS(88); +DECLARE_MSM_GPIO_PINS(89); +DECLARE_MSM_GPIO_PINS(90); +DECLARE_MSM_GPIO_PINS(91); +DECLARE_MSM_GPIO_PINS(92); +DECLARE_MSM_GPIO_PINS(93); +DECLARE_MSM_GPIO_PINS(94); +DECLARE_MSM_GPIO_PINS(95); +DECLARE_MSM_GPIO_PINS(96); +DECLARE_MSM_GPIO_PINS(97); +DECLARE_MSM_GPIO_PINS(98); +DECLARE_MSM_GPIO_PINS(99); +DECLARE_MSM_GPIO_PINS(100); +DECLARE_MSM_GPIO_PINS(101); +DECLARE_MSM_GPIO_PINS(102); +DECLARE_MSM_GPIO_PINS(103); +DECLARE_MSM_GPIO_PINS(104); +DECLARE_MSM_GPIO_PINS(105); +DECLARE_MSM_GPIO_PINS(106); +DECLARE_MSM_GPIO_PINS(107); +DECLARE_MSM_GPIO_PINS(108); +DECLARE_MSM_GPIO_PINS(109); +DECLARE_MSM_GPIO_PINS(110); +DECLARE_MSM_GPIO_PINS(111); +DECLARE_MSM_GPIO_PINS(112); +DECLARE_MSM_GPIO_PINS(113); +DECLARE_MSM_GPIO_PINS(114); +DECLARE_MSM_GPIO_PINS(115); +DECLARE_MSM_GPIO_PINS(116); +DECLARE_MSM_GPIO_PINS(117); +DECLARE_MSM_GPIO_PINS(118); +DECLARE_MSM_GPIO_PINS(119); +DECLARE_MSM_GPIO_PINS(120); +DECLARE_MSM_GPIO_PINS(121); +DECLARE_MSM_GPIO_PINS(122); +DECLARE_MSM_GPIO_PINS(123); +DECLARE_MSM_GPIO_PINS(124); +DECLARE_MSM_GPIO_PINS(125); +DECLARE_MSM_GPIO_PINS(126); +DECLARE_MSM_GPIO_PINS(127); +DECLARE_MSM_GPIO_PINS(128); +DECLARE_MSM_GPIO_PINS(129); +DECLARE_MSM_GPIO_PINS(130); +DECLARE_MSM_GPIO_PINS(131); +DECLARE_MSM_GPIO_PINS(132); +DECLARE_MSM_GPIO_PINS(133); +DECLARE_MSM_GPIO_PINS(134); +DECLARE_MSM_GPIO_PINS(135); +DECLARE_MSM_GPIO_PINS(136); +DECLARE_MSM_GPIO_PINS(137); +DECLARE_MSM_GPIO_PINS(138); +DECLARE_MSM_GPIO_PINS(139); +DECLARE_MSM_GPIO_PINS(140); +DECLARE_MSM_GPIO_PINS(141); + +static const unsigned int qdsd_clk_pins[] = { 142 }; +static const unsigned int qdsd_cmd_pins[] = { 143 }; +static const unsigned int qdsd_data0_pins[] = { 144 }; +static const unsigned int qdsd_data1_pins[] = { 145 }; +static const unsigned int qdsd_data2_pins[] = { 146 }; +static const unsigned int qdsd_data3_pins[] = { 147 }; +static const unsigned int sdc1_clk_pins[] = { 148 }; +static const unsigned int sdc1_cmd_pins[] = { 149 }; +static const unsigned int sdc1_data_pins[] = { 150 }; +static const unsigned int sdc1_rclk_pins[] = { 151 }; +static const unsigned int sdc2_clk_pins[] = { 152 }; +static const unsigned int sdc2_cmd_pins[] = { 153 }; +static const unsigned int sdc2_data_pins[] = { 154 }; + +enum msm8953_functions { + msm_mux_accel_int, + msm_mux_adsp_ext, + msm_mux_alsp_int, + msm_mux_atest_bbrx0, + msm_mux_atest_bbrx1, + msm_mux_atest_char, + msm_mux_atest_char0, + msm_mux_atest_char1, + msm_mux_atest_char2, + msm_mux_atest_char3, + msm_mux_atest_gpsadc_dtest0_native, + msm_mux_atest_gpsadc_dtest1_native, + msm_mux_atest_tsens, + msm_mux_atest_wlan0, + msm_mux_atest_wlan1, + msm_mux_bimc_dte0, + msm_mux_bimc_dte1, + msm_mux_blsp1_spi, + msm_mux_blsp3_spi, + msm_mux_blsp6_spi, + msm_mux_blsp7_spi, + msm_mux_blsp_i2c1, + msm_mux_blsp_i2c2, + msm_mux_blsp_i2c3, + msm_mux_blsp_i2c4, + msm_mux_blsp_i2c5, + msm_mux_blsp_i2c6, + msm_mux_blsp_i2c7, + msm_mux_blsp_i2c8, + msm_mux_blsp_spi1, + msm_mux_blsp_spi2, + msm_mux_blsp_spi3, + msm_mux_blsp_spi4, + msm_mux_blsp_spi5, + msm_mux_blsp_spi6, + msm_mux_blsp_spi7, + msm_mux_blsp_spi8, + msm_mux_blsp_uart2, + msm_mux_blsp_uart4, + msm_mux_blsp_uart5, + msm_mux_blsp_uart6, + msm_mux_cam0_ldo, + msm_mux_cam1_ldo, + msm_mux_cam1_rst, + msm_mux_cam1_standby, + msm_mux_cam2_rst, + msm_mux_cam2_standby, + msm_mux_cam3_rst, + msm_mux_cam3_standby, + msm_mux_cam_irq, + msm_mux_cam_mclk, + msm_mux_cap_int, + msm_mux_cci_async, + msm_mux_cci_i2c, + msm_mux_cci_timer0, + msm_mux_cci_timer1, + msm_mux_cci_timer2, + msm_mux_cci_timer3, + msm_mux_cci_timer4, + msm_mux_cdc_pdm0, + msm_mux_codec_int1, + msm_mux_codec_int2, + msm_mux_codec_reset, + msm_mux_cri_trng, + msm_mux_cri_trng0, + msm_mux_cri_trng1, + msm_mux_dac_calib0, + msm_mux_dac_calib1, + msm_mux_dac_calib2, + msm_mux_dac_calib3, + msm_mux_dac_calib4, + msm_mux_dac_calib5, + msm_mux_dac_calib6, + msm_mux_dac_calib7, + msm_mux_dac_calib8, + msm_mux_dac_calib9, + msm_mux_dac_calib10, + msm_mux_dac_calib11, + msm_mux_dac_calib12, + msm_mux_dac_calib13, + msm_mux_dac_calib14, + msm_mux_dac_calib15, + msm_mux_dac_calib16, + msm_mux_dac_calib17, + msm_mux_dac_calib18, + msm_mux_dac_calib19, + msm_mux_dac_calib20, + msm_mux_dac_calib21, + msm_mux_dac_calib22, + msm_mux_dac_calib23, + msm_mux_dac_calib24, + msm_mux_dac_calib25, + msm_mux_dbg_out, + msm_mux_ddr_bist, + msm_mux_dmic0_clk, + msm_mux_dmic0_data, + msm_mux_ebi_cdc, + msm_mux_ebi_ch0, + msm_mux_ext_lpass, + msm_mux_flash_strobe, + msm_mux_fp_int, + msm_mux_gcc_gp1_clk_a, + msm_mux_gcc_gp1_clk_b, + msm_mux_gcc_gp2_clk_a, + msm_mux_gcc_gp2_clk_b, + msm_mux_gcc_gp3_clk_a, + msm_mux_gcc_gp3_clk_b, + msm_mux_gcc_plltest, + msm_mux_gcc_tlmm, + msm_mux_gpio, + msm_mux_gsm0_tx, + msm_mux_gsm1_tx, + msm_mux_gyro_int, + msm_mux_hall_int, + msm_mux_hdmi_int, + msm_mux_key_focus, + msm_mux_key_home, + msm_mux_key_snapshot, + msm_mux_key_volp, + msm_mux_ldo_en, + msm_mux_ldo_update, + msm_mux_lpass_slimbus, + msm_mux_lpass_slimbus0, + msm_mux_lpass_slimbus1, + msm_mux_m_voc, + msm_mux_mag_int, + msm_mux_mdp_vsync, + msm_mux_mipi_dsi0, + msm_mux_modem_tsync, + msm_mux_mss_lte, + msm_mux_nav_pps, + msm_mux_nav_pps_in_a, + msm_mux_nav_pps_in_b, + msm_mux_nav_tsync, + msm_mux_nfc_disable, + msm_mux_nfc_dwl, + msm_mux_nfc_irq, + msm_mux_ois_sync, + msm_mux_pa_indicator, + msm_mux_pbs0, + msm_mux_pbs1, + msm_mux_pbs2, + msm_mux_pressure_int, + msm_mux_pri_mi2s, + msm_mux_pri_mi2s_mclk_a, + msm_mux_pri_mi2s_mclk_b, + msm_mux_pri_mi2s_ws, + msm_mux_prng_rosc, + msm_mux_pwr_crypto_enabled_a, + msm_mux_pwr_crypto_enabled_b, + msm_mux_pwr_down, + msm_mux_pwr_modem_enabled_a, + msm_mux_pwr_modem_enabled_b, + msm_mux_pwr_nav_enabled_a, + msm_mux_pwr_nav_enabled_b, + msm_mux_qdss_cti_trig_in_a0, + msm_mux_qdss_cti_trig_in_a1, + msm_mux_qdss_cti_trig_in_b0, + msm_mux_qdss_cti_trig_in_b1, + msm_mux_qdss_cti_trig_out_a0, + msm_mux_qdss_cti_trig_out_a1, + msm_mux_qdss_cti_trig_out_b0, + msm_mux_qdss_cti_trig_out_b1, + msm_mux_qdss_traceclk_a, + msm_mux_qdss_traceclk_b, + msm_mux_qdss_tracectl_a, + msm_mux_qdss_tracectl_b, + msm_mux_qdss_tracedata_a, + msm_mux_qdss_tracedata_b, + msm_mux_sd_write, + msm_mux_sdcard_det, + msm_mux_sec_mi2s, + msm_mux_sec_mi2s_mclk_a, + msm_mux_sec_mi2s_mclk_b, + msm_mux_smb_int, + msm_mux_ss_switch, + msm_mux_ssbi_wtr1, + msm_mux_ts_resout, + msm_mux_ts_sample, + msm_mux_ts_xvdd, + msm_mux_tsens_max, + msm_mux_uim1_clk, + msm_mux_uim1_data, + msm_mux_uim1_present, + msm_mux_uim1_reset, + msm_mux_uim2_clk, + msm_mux_uim2_data, + msm_mux_uim2_present, + msm_mux_uim2_reset, + msm_mux_uim_batt, + msm_mux_us_emitter, + msm_mux_us_euro, + msm_mux_wcss_bt, + msm_mux_wcss_fm, + msm_mux_wcss_wlan, + msm_mux_wcss_wlan0, + msm_mux_wcss_wlan1, + msm_mux_wcss_wlan2, + msm_mux_wsa_en, + msm_mux_wsa_io, + msm_mux_wsa_irq, + msm_mux__, +}; + +static const char * const accel_int_groups[] = { + "gpio42", +}; + +static const char * const adsp_ext_groups[] = { + "gpio1", +}; + +static const char * const alsp_int_groups[] = { + "gpio43", +}; + +static const char * const atest_bbrx0_groups[] = { + "gpio17", +}; + +static const char * const atest_bbrx1_groups[] = { + "gpio16", +}; + +static const char * const atest_char0_groups[] = { + "gpio68", +}; + +static const char * const atest_char1_groups[] = { + "gpio67", +}; + +static const char * const atest_char2_groups[] = { + "gpio75", +}; + +static const char * const atest_char3_groups[] = { + "gpio63", +}; + +static const char * const atest_char_groups[] = { + "gpio120", +}; + +static const char * const atest_gpsadc_dtest0_native_groups[] = { + "gpio7", +}; + +static const char * const atest_gpsadc_dtest1_native_groups[] = { + "gpio18", +}; + +static const char * const atest_tsens_groups[] = { + "gpio120", +}; + +static const char * const atest_wlan0_groups[] = { + "gpio22", +}; + +static const char * const atest_wlan1_groups[] = { + "gpio23", +}; + +static const char * const bimc_dte0_groups[] = { + "gpio63", "gpio65", +}; + +static const char * const bimc_dte1_groups[] = { + "gpio121", "gpio122", +}; + +static const char * const blsp1_spi_groups[] = { + "gpio35", "gpio36", +}; + +static const char * const blsp3_spi_groups[] = { + "gpio41", "gpio50", +}; + +static const char * const blsp6_spi_groups[] = { + "gpio47", "gpio48", +}; + +static const char * const blsp7_spi_groups[] = { + "gpio89", "gpio90", +}; + +static const char * const blsp_i2c1_groups[] = { + "gpio2", "gpio3", +}; + +static const char * const blsp_i2c2_groups[] = { + "gpio6", "gpio7", +}; + +static const char * const blsp_i2c3_groups[] = { + "gpio10", "gpio11", +}; + +static const char * const blsp_i2c4_groups[] = { + "gpio14", "gpio15", +}; + +static const char * const blsp_i2c5_groups[] = { + "gpio18", "gpio19", +}; + +static const char * const blsp_i2c6_groups[] = { + "gpio22", "gpio23", +}; + +static const char * const blsp_i2c7_groups[] = { + "gpio135", "gpio136", +}; + +static const char * const blsp_i2c8_groups[] = { + "gpio98", "gpio99", +}; + +static const char * const blsp_spi1_groups[] = { + "gpio0", "gpio1", "gpio2", "gpio3", +}; + +static const char * const blsp_spi2_groups[] = { + "gpio4", "gpio5", "gpio6", "gpio7", +}; + +static const char * const blsp_spi3_groups[] = { + "gpio8", "gpio9", "gpio10", "gpio11", +}; + +static const char * const blsp_spi4_groups[] = { + "gpio12", "gpio13", "gpio14", "gpio15", +}; + +static const char * const blsp_spi5_groups[] = { + "gpio16", "gpio17", "gpio18", "gpio19", +}; + +static const char * const blsp_spi6_groups[] = { + "gpio20", "gpio21", "gpio22", "gpio23", +}; + +static const char * const blsp_spi7_groups[] = { + "gpio135", "gpio136", "gpio137", "gpio138", +}; + +static const char * const blsp_spi8_groups[] = { + "gpio96", "gpio97", "gpio98", "gpio99", +}; + +static const char * const blsp_uart2_groups[] = { + "gpio4", "gpio5", "gpio6", "gpio7", +}; + +static const char * const blsp_uart4_groups[] = { + "gpio12", "gpio13", "gpio14", "gpio15", +}; + +static const char * const blsp_uart5_groups[] = { + "gpio16", "gpio17", "gpio18", "gpio19", +}; + +static const char * const blsp_uart6_groups[] = { + "gpio20", "gpio21", "gpio22", "gpio23", +}; + +static const char * const cam0_ldo_groups[] = { + "gpio50", +}; + +static const char * const cam1_ldo_groups[] = { + "gpio134", +}; + +static const char * const cam1_rst_groups[] = { + "gpio40", +}; + +static const char * const cam1_standby_groups[] = { + "gpio39", +}; + +static const char * const cam2_rst_groups[] = { + "gpio129", +}; + +static const char * const cam2_standby_groups[] = { + "gpio130", +}; + +static const char * const cam3_rst_groups[] = { + "gpio131", +}; + +static const char * const cam3_standby_groups[] = { + "gpio132", +}; + +static const char * const cam_irq_groups[] = { + "gpio35", +}; + +static const char * const cam_mclk_groups[] = { + "gpio26", "gpio27", "gpio28", "gpio128", +}; + +static const char * const cap_int_groups[] = { + "gpio13", +}; + +static const char * const cci_async_groups[] = { + "gpio38", +}; + +static const char * const cci_i2c_groups[] = { + "gpio29", "gpio30", "gpio31", "gpio32", +}; + +static const char * const cci_timer0_groups[] = { + "gpio33", +}; + +static const char * const cci_timer1_groups[] = { + "gpio34", +}; + +static const char * const cci_timer2_groups[] = { + "gpio35", +}; + +static const char * const cci_timer3_groups[] = { + "gpio36", +}; + +static const char * const cci_timer4_groups[] = { + "gpio41", +}; + +static const char * const cdc_pdm0_groups[] = { + "gpio67", "gpio68", "gpio69", "gpio70", "gpio71", "gpio72", "gpio73", + "gpio74", +}; + +static const char * const codec_int1_groups[] = { + "gpio73", +}; + +static const char * const codec_int2_groups[] = { + "gpio74", +}; + +static const char * const codec_reset_groups[] = { + "gpio67", +}; + +static const char * const cri_trng0_groups[] = { + "gpio85", +}; + +static const char * const cri_trng1_groups[] = { + "gpio86", +}; + +static const char * const cri_trng_groups[] = { + "gpio87", +}; + +static const char * const dac_calib0_groups[] = { + "gpio4", +}; + +static const char * const dac_calib1_groups[] = { + "gpio12", +}; + +static const char * const dac_calib2_groups[] = { + "gpio13", +}; + +static const char * const dac_calib3_groups[] = { + "gpio28", +}; + +static const char * const dac_calib4_groups[] = { + "gpio29", +}; + +static const char * const dac_calib5_groups[] = { + "gpio39", +}; + +static const char * const dac_calib6_groups[] = { + "gpio40", +}; + +static const char * const dac_calib7_groups[] = { + "gpio41", +}; + +static const char * const dac_calib8_groups[] = { + "gpio42", +}; + +static const char * const dac_calib9_groups[] = { + "gpio43", +}; + +static const char * const dac_calib10_groups[] = { + "gpio44", +}; + +static const char * const dac_calib11_groups[] = { + "gpio45", +}; + +static const char * const dac_calib12_groups[] = { + "gpio46", +}; + +static const char * const dac_calib13_groups[] = { + "gpio47", +}; + +static const char * const dac_calib14_groups[] = { + "gpio48", +}; + +static const char * const dac_calib15_groups[] = { + "gpio20", +}; + +static const char * const dac_calib16_groups[] = { + "gpio21", +}; + +static const char * const dac_calib17_groups[] = { + "gpio67", +}; + +static const char * const dac_calib18_groups[] = { + "gpio115", +}; + +static const char * const dac_calib19_groups[] = { + "gpio30", +}; + +static const char * const dac_calib20_groups[] = { + "gpio128", +}; + +static const char * const dac_calib21_groups[] = { + "gpio129", +}; + +static const char * const dac_calib22_groups[] = { + "gpio130", +}; + +static const char * const dac_calib23_groups[] = { + "gpio131", +}; + +static const char * const dac_calib24_groups[] = { + "gpio132", +}; + +static const char * const dac_calib25_groups[] = { + "gpio133", +}; + +static const char * const dbg_out_groups[] = { + "gpio63", +}; + +static const char * const ddr_bist_groups[] = { + "gpio129", "gpio130", "gpio131", "gpio132", +}; + +static const char * const dmic0_clk_groups[] = { + "gpio89", +}; + +static const char * const dmic0_data_groups[] = { + "gpio90", +}; + +static const char * const ebi_cdc_groups[] = { + "gpio67", "gpio69", "gpio118", "gpio119", "gpio120", "gpio123", +}; + +static const char * const ebi_ch0_groups[] = { + "gpio75", +}; + +static const char * const ext_lpass_groups[] = { + "gpio81", +}; + +static const char * const flash_strobe_groups[] = { + "gpio33", "gpio34", +}; + +static const char * const fp_int_groups[] = { + "gpio48", +}; + +static const char * const gcc_gp1_clk_a_groups[] = { + "gpio42", +}; + +static const char * const gcc_gp1_clk_b_groups[] = { + "gpio6", "gpio41", +}; + +static const char * const gcc_gp2_clk_a_groups[] = { + "gpio43", +}; + +static const char * const gcc_gp2_clk_b_groups[] = { + "gpio10", +}; + +static const char * const gcc_gp3_clk_a_groups[] = { + "gpio44", +}; + +static const char * const gcc_gp3_clk_b_groups[] = { + "gpio11", +}; + +static const char * const gcc_plltest_groups[] = { + "gpio98", "gpio99", +}; + +static const char * const gcc_tlmm_groups[] = { + "gpio87", +}; + +static const char * const gpio_groups[] = { + "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7", + "gpio8", "gpio9", "gpio10", "gpio11", "gpio12", "gpio13", "gpio14", + "gpio15", "gpio16", "gpio17", "gpio18", "gpio19", "gpio20", "gpio21", + "gpio22", "gpio23", "gpio24", "gpio25", "gpio26", "gpio27", "gpio28", + "gpio29", "gpio30", "gpio31", "gpio32", "gpio33", "gpio34", "gpio35", + "gpio36", "gpio37", "gpio38", "gpio39", "gpio40", "gpio41", "gpio42", + "gpio43", "gpio44", "gpio45", "gpio46", "gpio47", "gpio48", "gpio49", + "gpio50", "gpio51", "gpio52", "gpio53", "gpio54", "gpio55", "gpio56", + "gpio57", "gpio58", "gpio59", "gpio60", "gpio61", "gpio62", "gpio63", + "gpio64", "gpio65", "gpio66", "gpio67", "gpio68", "gpio69", "gpio70", + "gpio71", "gpio72", "gpio73", "gpio74", "gpio75", "gpio76", "gpio77", + "gpio78", "gpio79", "gpio80", "gpio81", "gpio82", "gpio83", "gpio84", + "gpio85", "gpio86", "gpio87", "gpio88", "gpio89", "gpio90", "gpio91", + "gpio92", "gpio93", "gpio94", "gpio95", "gpio96", "gpio97", "gpio98", + "gpio99", "gpio100", "gpio101", "gpio102", "gpio103", "gpio104", + "gpio105", "gpio106", "gpio107", "gpio108", "gpio109", "gpio110", + "gpio111", "gpio112", "gpio113", "gpio114", "gpio115", "gpio116", + "gpio117", "gpio118", "gpio119", "gpio120", "gpio121", "gpio122", + "gpio123", "gpio124", "gpio125", "gpio126", "gpio127", "gpio128", + "gpio129", "gpio130", "gpio131", "gpio132", "gpio133", "gpio134", + "gpio135", "gpio136", "gpio137", "gpio138", "gpio139", "gpio140", + "gpio141", +}; + +static const char * const gsm0_tx_groups[] = { + "gpio117", +}; + +static const char * const gsm1_tx_groups[] = { + "gpio115", +}; + +static const char * const gyro_int_groups[] = { + "gpio45", +}; + +static const char * const hall_int_groups[] = { + "gpio12", +}; + +static const char * const hdmi_int_groups[] = { + "gpio90", +}; + +static const char * const key_focus_groups[] = { + "gpio87", +}; + +static const char * const key_home_groups[] = { + "gpio88", +}; + +static const char * const key_snapshot_groups[] = { + "gpio86", +}; + +static const char * const key_volp_groups[] = { + "gpio85", +}; + +static const char * const ldo_en_groups[] = { + "gpio5", +}; + +static const char * const ldo_update_groups[] = { + "gpio4", +}; + +static const char * const lpass_slimbus0_groups[] = { + "gpio71", +}; + +static const char * const lpass_slimbus1_groups[] = { + "gpio72", +}; + +static const char * const lpass_slimbus_groups[] = { + "gpio70", +}; + +static const char * const m_voc_groups[] = { + "gpio17", "gpio21", +}; + +static const char * const mag_int_groups[] = { + "gpio44", +}; + +static const char * const mdp_vsync_groups[] = { + "gpio24", "gpio25", +}; + +static const char * const mipi_dsi0_groups[] = { + "gpio61", +}; + +static const char * const modem_tsync_groups[] = { + "gpio113", +}; + +static const char * const mss_lte_groups[] = { + "gpio82", "gpio83", +}; + +static const char * const nav_pps_groups[] = { + "gpio113", +}; + +static const char * const nav_pps_in_a_groups[] = { + "gpio111", +}; + +static const char * const nav_pps_in_b_groups[] = { + "gpio113", +}; + +static const char * const nav_tsync_groups[] = { + "gpio113", +}; + +static const char * const nfc_disable_groups[] = { + "gpio16", +}; + +static const char * const nfc_dwl_groups[] = { + "gpio62", +}; + +static const char * const nfc_irq_groups[] = { + "gpio17", +}; + +static const char * const ois_sync_groups[] = { + "gpio36", +}; + +static const char * const pa_indicator_groups[] = { + "gpio112", +}; + +static const char * const pbs0_groups[] = { + "gpio85", +}; + +static const char * const pbs1_groups[] = { + "gpio86", +}; + +static const char * const pbs2_groups[] = { + "gpio87", +}; + +static const char * const pressure_int_groups[] = { + "gpio46", +}; + +static const char * const pri_mi2s_groups[] = { + "gpio66", "gpio88", "gpio91", "gpio93", "gpio94", "gpio95", +}; + +static const char * const pri_mi2s_mclk_a_groups[] = { + "gpio25", +}; + +static const char * const pri_mi2s_mclk_b_groups[] = { + "gpio69", +}; + +static const char * const pri_mi2s_ws_groups[] = { + "gpio92", +}; + +static const char * const prng_rosc_groups[] = { + "gpio2", +}; + +static const char * const pwr_crypto_enabled_a_groups[] = { + "gpio36", +}; + +static const char * const pwr_crypto_enabled_b_groups[] = { + "gpio13", +}; + +static const char * const pwr_down_groups[] = { + "gpio89", +}; + +static const char * const pwr_modem_enabled_a_groups[] = { + "gpio29", +}; + +static const char * const pwr_modem_enabled_b_groups[] = { + "gpio9", +}; + +static const char * const pwr_nav_enabled_a_groups[] = { + "gpio35", +}; + +static const char * const pwr_nav_enabled_b_groups[] = { + "gpio12", +}; + +static const char * const qdss_cti_trig_in_a0_groups[] = { + "gpio17", +}; + +static const char * const qdss_cti_trig_in_a1_groups[] = { + "gpio91", +}; + +static const char * const qdss_cti_trig_in_b0_groups[] = { + "gpio21", +}; + +static const char * const qdss_cti_trig_in_b1_groups[] = { + "gpio48", +}; + +static const char * const qdss_cti_trig_out_a0_groups[] = { + "gpio41", +}; + +static const char * const qdss_cti_trig_out_a1_groups[] = { + "gpio3", +}; + +static const char * const qdss_cti_trig_out_b0_groups[] = { + "gpio2", +}; + +static const char * const qdss_cti_trig_out_b1_groups[] = { + "gpio25", +}; + +static const char * const qdss_traceclk_a_groups[] = { + "gpio16", +}; + +static const char * const qdss_traceclk_b_groups[] = { + "gpio22", +}; + +static const char * const qdss_tracectl_a_groups[] = { + "gpio18", +}; + +static const char * const qdss_tracectl_b_groups[] = { + "gpio20", +}; + +static const char * const qdss_tracedata_a_groups[] = { + "gpio19", "gpio26", "gpio27", "gpio28", "gpio29", "gpio30", "gpio31", + "gpio32", "gpio33", "gpio34", "gpio35", "gpio36", "gpio38", "gpio39", + "gpio40", "gpio50", +}; + +static const char * const qdss_tracedata_b_groups[] = { + "gpio8", "gpio9", "gpio12", "gpio13", "gpio23", "gpio42", "gpio43", + "gpio44", "gpio45", "gpio46", "gpio47", "gpio66", "gpio86", "gpio87", + "gpio88", "gpio92", +}; + +static const char * const sd_write_groups[] = { + "gpio50", +}; + +static const char * const sdcard_det_groups[] = { + "gpio133", +}; + +static const char * const sec_mi2s_groups[] = { + "gpio135", "gpio136", "gpio137", "gpio138", +}; + +static const char * const sec_mi2s_mclk_a_groups[] = { + "gpio25", +}; + +static const char * const sec_mi2s_mclk_b_groups[] = { + "gpio66", +}; + +static const char * const smb_int_groups[] = { + "gpio1", +}; + +static const char * const ss_switch_groups[] = { + "gpio139", +}; + +static const char * const ssbi_wtr1_groups[] = { + "gpio114", "gpio123", +}; + +static const char * const ts_resout_groups[] = { + "gpio64", +}; + +static const char * const ts_sample_groups[] = { + "gpio65", +}; + +static const char * const ts_xvdd_groups[] = { + "gpio60", +}; + +static const char * const tsens_max_groups[] = { + "gpio139", +}; + +static const char * const uim1_clk_groups[] = { + "gpio52", +}; + +static const char * const uim1_data_groups[] = { + "gpio51", +}; + +static const char * const uim1_present_groups[] = { + "gpio54", +}; + +static const char * const uim1_reset_groups[] = { + "gpio53", +}; + +static const char * const uim2_clk_groups[] = { + "gpio56", +}; + +static const char * const uim2_data_groups[] = { + "gpio55", +}; + +static const char * const uim2_present_groups[] = { + "gpio58", +}; + +static const char * const uim2_reset_groups[] = { + "gpio57", +}; + +static const char * const uim_batt_groups[] = { + "gpio49", +}; + +static const char * const us_emitter_groups[] = { + "gpio68", +}; + +static const char * const us_euro_groups[] = { + "gpio63", +}; + +static const char * const wcss_bt_groups[] = { + "gpio75", "gpio83", "gpio84", +}; + +static const char * const wcss_fm_groups[] = { + "gpio81", "gpio82", +}; + +static const char * const wcss_wlan0_groups[] = { + "gpio78", +}; + +static const char * const wcss_wlan1_groups[] = { + "gpio77", +}; + +static const char * const wcss_wlan2_groups[] = { + "gpio76", +}; + +static const char * const wcss_wlan_groups[] = { + "gpio79", "gpio80", +}; + +static const char * const wsa_en_groups[] = { + "gpio96", +}; + +static const char * const wsa_io_groups[] = { + "gpio94", "gpio95", +}; + +static const char * const wsa_irq_groups[] = { + "gpio97", +}; + +static const struct pinfunction msm8953_functions[] = { + MSM_PIN_FUNCTION(accel_int), + MSM_PIN_FUNCTION(adsp_ext), + MSM_PIN_FUNCTION(alsp_int), + MSM_PIN_FUNCTION(atest_bbrx0), + MSM_PIN_FUNCTION(atest_bbrx1), + MSM_PIN_FUNCTION(atest_char), + MSM_PIN_FUNCTION(atest_char0), + MSM_PIN_FUNCTION(atest_char1), + MSM_PIN_FUNCTION(atest_char2), + MSM_PIN_FUNCTION(atest_char3), + MSM_PIN_FUNCTION(atest_gpsadc_dtest0_native), + MSM_PIN_FUNCTION(atest_gpsadc_dtest1_native), + MSM_PIN_FUNCTION(atest_tsens), + MSM_PIN_FUNCTION(atest_wlan0), + MSM_PIN_FUNCTION(atest_wlan1), + MSM_PIN_FUNCTION(bimc_dte0), + MSM_PIN_FUNCTION(bimc_dte1), + MSM_PIN_FUNCTION(blsp1_spi), + MSM_PIN_FUNCTION(blsp3_spi), + MSM_PIN_FUNCTION(blsp6_spi), + MSM_PIN_FUNCTION(blsp7_spi), + MSM_PIN_FUNCTION(blsp_i2c1), + MSM_PIN_FUNCTION(blsp_i2c2), + MSM_PIN_FUNCTION(blsp_i2c3), + MSM_PIN_FUNCTION(blsp_i2c4), + MSM_PIN_FUNCTION(blsp_i2c5), + MSM_PIN_FUNCTION(blsp_i2c6), + MSM_PIN_FUNCTION(blsp_i2c7), + MSM_PIN_FUNCTION(blsp_i2c8), + MSM_PIN_FUNCTION(blsp_spi1), + MSM_PIN_FUNCTION(blsp_spi2), + MSM_PIN_FUNCTION(blsp_spi3), + MSM_PIN_FUNCTION(blsp_spi4), + MSM_PIN_FUNCTION(blsp_spi5), + MSM_PIN_FUNCTION(blsp_spi6), + MSM_PIN_FUNCTION(blsp_spi7), + MSM_PIN_FUNCTION(blsp_spi8), + MSM_PIN_FUNCTION(blsp_uart2), + MSM_PIN_FUNCTION(blsp_uart4), + MSM_PIN_FUNCTION(blsp_uart5), + MSM_PIN_FUNCTION(blsp_uart6), + MSM_PIN_FUNCTION(cam0_ldo), + MSM_PIN_FUNCTION(cam1_ldo), + MSM_PIN_FUNCTION(cam1_rst), + MSM_PIN_FUNCTION(cam1_standby), + MSM_PIN_FUNCTION(cam2_rst), + MSM_PIN_FUNCTION(cam2_standby), + MSM_PIN_FUNCTION(cam3_rst), + MSM_PIN_FUNCTION(cam3_standby), + MSM_PIN_FUNCTION(cam_irq), + MSM_PIN_FUNCTION(cam_mclk), + MSM_PIN_FUNCTION(cap_int), + MSM_PIN_FUNCTION(cci_async), + MSM_PIN_FUNCTION(cci_i2c), + MSM_PIN_FUNCTION(cci_timer0), + MSM_PIN_FUNCTION(cci_timer1), + MSM_PIN_FUNCTION(cci_timer2), + MSM_PIN_FUNCTION(cci_timer3), + MSM_PIN_FUNCTION(cci_timer4), + MSM_PIN_FUNCTION(cdc_pdm0), + MSM_PIN_FUNCTION(codec_int1), + MSM_PIN_FUNCTION(codec_int2), + MSM_PIN_FUNCTION(codec_reset), + MSM_PIN_FUNCTION(cri_trng), + MSM_PIN_FUNCTION(cri_trng0), + MSM_PIN_FUNCTION(cri_trng1), + MSM_PIN_FUNCTION(dac_calib0), + MSM_PIN_FUNCTION(dac_calib1), + MSM_PIN_FUNCTION(dac_calib10), + MSM_PIN_FUNCTION(dac_calib11), + MSM_PIN_FUNCTION(dac_calib12), + MSM_PIN_FUNCTION(dac_calib13), + MSM_PIN_FUNCTION(dac_calib14), + MSM_PIN_FUNCTION(dac_calib15), + MSM_PIN_FUNCTION(dac_calib16), + MSM_PIN_FUNCTION(dac_calib17), + MSM_PIN_FUNCTION(dac_calib18), + MSM_PIN_FUNCTION(dac_calib19), + MSM_PIN_FUNCTION(dac_calib2), + MSM_PIN_FUNCTION(dac_calib20), + MSM_PIN_FUNCTION(dac_calib21), + MSM_PIN_FUNCTION(dac_calib22), + MSM_PIN_FUNCTION(dac_calib23), + MSM_PIN_FUNCTION(dac_calib24), + MSM_PIN_FUNCTION(dac_calib25), + MSM_PIN_FUNCTION(dac_calib3), + MSM_PIN_FUNCTION(dac_calib4), + MSM_PIN_FUNCTION(dac_calib5), + MSM_PIN_FUNCTION(dac_calib6), + MSM_PIN_FUNCTION(dac_calib7), + MSM_PIN_FUNCTION(dac_calib8), + MSM_PIN_FUNCTION(dac_calib9), + MSM_PIN_FUNCTION(dbg_out), + MSM_PIN_FUNCTION(ddr_bist), + MSM_PIN_FUNCTION(dmic0_clk), + MSM_PIN_FUNCTION(dmic0_data), + MSM_PIN_FUNCTION(ebi_cdc), + MSM_PIN_FUNCTION(ebi_ch0), + MSM_PIN_FUNCTION(ext_lpass), + MSM_PIN_FUNCTION(flash_strobe), + MSM_PIN_FUNCTION(fp_int), + MSM_PIN_FUNCTION(gcc_gp1_clk_a), + MSM_PIN_FUNCTION(gcc_gp1_clk_b), + MSM_PIN_FUNCTION(gcc_gp2_clk_a), + MSM_PIN_FUNCTION(gcc_gp2_clk_b), + MSM_PIN_FUNCTION(gcc_gp3_clk_a), + MSM_PIN_FUNCTION(gcc_gp3_clk_b), + MSM_PIN_FUNCTION(gcc_plltest), + MSM_PIN_FUNCTION(gcc_tlmm), + MSM_PIN_FUNCTION(gpio), + MSM_PIN_FUNCTION(gsm0_tx), + MSM_PIN_FUNCTION(gsm1_tx), + MSM_PIN_FUNCTION(gyro_int), + MSM_PIN_FUNCTION(hall_int), + MSM_PIN_FUNCTION(hdmi_int), + MSM_PIN_FUNCTION(key_focus), + MSM_PIN_FUNCTION(key_home), + MSM_PIN_FUNCTION(key_snapshot), + MSM_PIN_FUNCTION(key_volp), + MSM_PIN_FUNCTION(ldo_en), + MSM_PIN_FUNCTION(ldo_update), + MSM_PIN_FUNCTION(lpass_slimbus), + MSM_PIN_FUNCTION(lpass_slimbus0), + MSM_PIN_FUNCTION(lpass_slimbus1), + MSM_PIN_FUNCTION(m_voc), + MSM_PIN_FUNCTION(mag_int), + MSM_PIN_FUNCTION(mdp_vsync), + MSM_PIN_FUNCTION(mipi_dsi0), + MSM_PIN_FUNCTION(modem_tsync), + MSM_PIN_FUNCTION(mss_lte), + MSM_PIN_FUNCTION(nav_pps), + MSM_PIN_FUNCTION(nav_pps_in_a), + MSM_PIN_FUNCTION(nav_pps_in_b), + MSM_PIN_FUNCTION(nav_tsync), + MSM_PIN_FUNCTION(nfc_disable), + MSM_PIN_FUNCTION(nfc_dwl), + MSM_PIN_FUNCTION(nfc_irq), + MSM_PIN_FUNCTION(ois_sync), + MSM_PIN_FUNCTION(pa_indicator), + MSM_PIN_FUNCTION(pbs0), + MSM_PIN_FUNCTION(pbs1), + MSM_PIN_FUNCTION(pbs2), + MSM_PIN_FUNCTION(pressure_int), + MSM_PIN_FUNCTION(pri_mi2s), + MSM_PIN_FUNCTION(pri_mi2s_mclk_a), + MSM_PIN_FUNCTION(pri_mi2s_mclk_b), + MSM_PIN_FUNCTION(pri_mi2s_ws), + MSM_PIN_FUNCTION(prng_rosc), + MSM_PIN_FUNCTION(pwr_crypto_enabled_a), + MSM_PIN_FUNCTION(pwr_crypto_enabled_b), + MSM_PIN_FUNCTION(pwr_down), + MSM_PIN_FUNCTION(pwr_modem_enabled_a), + MSM_PIN_FUNCTION(pwr_modem_enabled_b), + MSM_PIN_FUNCTION(pwr_nav_enabled_a), + MSM_PIN_FUNCTION(pwr_nav_enabled_b), + MSM_PIN_FUNCTION(qdss_cti_trig_in_a0), + MSM_PIN_FUNCTION(qdss_cti_trig_in_a1), + MSM_PIN_FUNCTION(qdss_cti_trig_in_b0), + MSM_PIN_FUNCTION(qdss_cti_trig_in_b1), + MSM_PIN_FUNCTION(qdss_cti_trig_out_a0), + MSM_PIN_FUNCTION(qdss_cti_trig_out_a1), + MSM_PIN_FUNCTION(qdss_cti_trig_out_b0), + MSM_PIN_FUNCTION(qdss_cti_trig_out_b1), + MSM_PIN_FUNCTION(qdss_traceclk_a), + MSM_PIN_FUNCTION(qdss_traceclk_b), + MSM_PIN_FUNCTION(qdss_tracectl_a), + MSM_PIN_FUNCTION(qdss_tracectl_b), + MSM_PIN_FUNCTION(qdss_tracedata_a), + MSM_PIN_FUNCTION(qdss_tracedata_b), + MSM_PIN_FUNCTION(sd_write), + MSM_PIN_FUNCTION(sdcard_det), + MSM_PIN_FUNCTION(sec_mi2s), + MSM_PIN_FUNCTION(sec_mi2s_mclk_a), + MSM_PIN_FUNCTION(sec_mi2s_mclk_b), + MSM_PIN_FUNCTION(smb_int), + MSM_PIN_FUNCTION(ss_switch), + MSM_PIN_FUNCTION(ssbi_wtr1), + MSM_PIN_FUNCTION(ts_resout), + MSM_PIN_FUNCTION(ts_sample), + MSM_PIN_FUNCTION(ts_xvdd), + MSM_PIN_FUNCTION(tsens_max), + MSM_PIN_FUNCTION(uim1_clk), + MSM_PIN_FUNCTION(uim1_data), + MSM_PIN_FUNCTION(uim1_present), + MSM_PIN_FUNCTION(uim1_reset), + MSM_PIN_FUNCTION(uim2_clk), + MSM_PIN_FUNCTION(uim2_data), + MSM_PIN_FUNCTION(uim2_present), + MSM_PIN_FUNCTION(uim2_reset), + MSM_PIN_FUNCTION(uim_batt), + MSM_PIN_FUNCTION(us_emitter), + MSM_PIN_FUNCTION(us_euro), + MSM_PIN_FUNCTION(wcss_bt), + MSM_PIN_FUNCTION(wcss_fm), + MSM_PIN_FUNCTION(wcss_wlan), + MSM_PIN_FUNCTION(wcss_wlan0), + MSM_PIN_FUNCTION(wcss_wlan1), + MSM_PIN_FUNCTION(wcss_wlan2), + MSM_PIN_FUNCTION(wsa_en), + MSM_PIN_FUNCTION(wsa_io), + MSM_PIN_FUNCTION(wsa_irq), +}; + +static const struct msm_pingroup msm8953_groups[] = { + PINGROUP(0, blsp_spi1, _, _, _, _, _, _, _, _), + PINGROUP(1, blsp_spi1, adsp_ext, _, _, _, _, _, _, _), + PINGROUP(2, blsp_spi1, blsp_i2c1, prng_rosc, _, _, _, qdss_cti_trig_out_b0, _, _), + PINGROUP(3, blsp_spi1, blsp_i2c1, _, _, _, qdss_cti_trig_out_a1, _, _, _), + PINGROUP(4, blsp_spi2, blsp_uart2, ldo_update, _, dac_calib0, _, _, _, _), + PINGROUP(5, blsp_spi2, blsp_uart2, ldo_en, _, _, _, _, _, _), + PINGROUP(6, blsp_spi2, blsp_uart2, blsp_i2c2, gcc_gp1_clk_b, _, _, _, _, _), + PINGROUP(7, blsp_spi2, blsp_uart2, blsp_i2c2, _, atest_gpsadc_dtest0_native, _, _, _, _), + PINGROUP(8, blsp_spi3, _, _, qdss_tracedata_b, _, _, _, _, _), + PINGROUP(9, blsp_spi3, pwr_modem_enabled_b, _, _, qdss_tracedata_b, _, _, _, _), + PINGROUP(10, blsp_spi3, blsp_i2c3, gcc_gp2_clk_b, _, _, _, _, _, _), + PINGROUP(11, blsp_spi3, blsp_i2c3, gcc_gp3_clk_b, _, _, _, _, _, _), + PINGROUP(12, blsp_spi4, blsp_uart4, pwr_nav_enabled_b, _, _, + qdss_tracedata_b, _, dac_calib1, _), + PINGROUP(13, blsp_spi4, blsp_uart4, pwr_crypto_enabled_b, _, _, _, + qdss_tracedata_b, _, dac_calib2), + PINGROUP(14, blsp_spi4, blsp_uart4, blsp_i2c4, _, _, _, _, _, _), + PINGROUP(15, blsp_spi4, blsp_uart4, blsp_i2c4, _, _, _, _, _, _), + PINGROUP(16, blsp_spi5, blsp_uart5, _, _, qdss_traceclk_a, _, atest_bbrx1, _, _), + PINGROUP(17, blsp_spi5, blsp_uart5, m_voc, qdss_cti_trig_in_a0, _, atest_bbrx0, _, _, _), + PINGROUP(18, blsp_spi5, blsp_uart5, blsp_i2c5, + qdss_tracectl_a, _, atest_gpsadc_dtest1_native, _, _, _), + PINGROUP(19, blsp_spi5, blsp_uart5, blsp_i2c5, qdss_tracedata_a, _, _, _, _, _), + PINGROUP(20, blsp_spi6, blsp_uart6, _, _, _, qdss_tracectl_b, _, dac_calib15, _), + PINGROUP(21, blsp_spi6, blsp_uart6, m_voc, _, _, _, qdss_cti_trig_in_b0, _, dac_calib16), + PINGROUP(22, blsp_spi6, blsp_uart6, blsp_i2c6, qdss_traceclk_b, _, atest_wlan0, _, _, _), + PINGROUP(23, blsp_spi6, blsp_uart6, blsp_i2c6, qdss_tracedata_b, _, atest_wlan1, _, _, _), + PINGROUP(24, mdp_vsync, _, _, _, _, _, _, _, _), + PINGROUP(25, mdp_vsync, pri_mi2s_mclk_a, sec_mi2s_mclk_a, + qdss_cti_trig_out_b1, _, _, _, _, _), + PINGROUP(26, cam_mclk, _, _, _, qdss_tracedata_a, _, _, _, _), + PINGROUP(27, cam_mclk, _, _, _, qdss_tracedata_a, _, _, _, _), + PINGROUP(28, cam_mclk, _, _, _, qdss_tracedata_a, _, dac_calib3, _, _), + PINGROUP(29, cci_i2c, pwr_modem_enabled_a, _, _, _, qdss_tracedata_a, _, dac_calib4, _), + PINGROUP(30, cci_i2c, _, _, _, qdss_tracedata_a, _, dac_calib19, _, _), + PINGROUP(31, cci_i2c, _, _, _, qdss_tracedata_a, _, _, _, _), + PINGROUP(32, cci_i2c, _, _, _, qdss_tracedata_a, _, _, _, _), + PINGROUP(33, cci_timer0, _, _, _, _, qdss_tracedata_a, _, _, _), + PINGROUP(34, cci_timer1, _, _, _, _, qdss_tracedata_a, _, _, _), + PINGROUP(35, cci_timer2, blsp1_spi, pwr_nav_enabled_a, _, _, _, qdss_tracedata_a, _, _), + PINGROUP(36, cci_timer3, blsp1_spi, _, pwr_crypto_enabled_a, _, _, _, qdss_tracedata_a, _), + PINGROUP(37, _, _, _, _, _, _, _, _, _), + PINGROUP(38, cci_async, _, qdss_tracedata_a, _, _, _, _, _, _), + PINGROUP(39, _, _, _, qdss_tracedata_a, _, dac_calib5, _, _, _), + PINGROUP(40, _, _, qdss_tracedata_a, _, dac_calib6, _, _, _, _), + PINGROUP(41, cci_timer4, blsp3_spi, gcc_gp1_clk_b, _, _, + qdss_cti_trig_out_a0, _, dac_calib7, _), + PINGROUP(42, gcc_gp1_clk_a, qdss_tracedata_b, _, dac_calib8, _, _, _, _, _), + PINGROUP(43, gcc_gp2_clk_a, qdss_tracedata_b, _, dac_calib9, _, _, _, _, _), + PINGROUP(44, gcc_gp3_clk_a, qdss_tracedata_b, _, dac_calib10, _, _, _, _, _), + PINGROUP(45, _, qdss_tracedata_b, _, dac_calib11, _, _, _, _, _), + PINGROUP(46, qdss_tracedata_b, _, dac_calib12, _, _, _, _, _, _), + PINGROUP(47, blsp6_spi, qdss_tracedata_b, _, dac_calib13, _, _, _, _, _), + PINGROUP(48, blsp6_spi, _, qdss_cti_trig_in_b1, _, dac_calib14, _, _, _, _), + PINGROUP(49, uim_batt, _, _, _, _, _, _, _, _), + PINGROUP(50, blsp3_spi, sd_write, _, _, _, qdss_tracedata_a, _, _, _), + PINGROUP(51, uim1_data, _, _, _, _, _, _, _, _), + PINGROUP(52, uim1_clk, _, _, _, _, _, _, _, _), + PINGROUP(53, uim1_reset, _, _, _, _, _, _, _, _), + PINGROUP(54, uim1_present, _, _, _, _, _, _, _, _), + PINGROUP(55, uim2_data, _, _, _, _, _, _, _, _), + PINGROUP(56, uim2_clk, _, _, _, _, _, _, _, _), + PINGROUP(57, uim2_reset, _, _, _, _, _, _, _, _), + PINGROUP(58, uim2_present, _, _, _, _, _, _, _, _), + PINGROUP(59, _, _, _, _, _, _, _, _, _), + PINGROUP(60, _, _, _, _, _, _, _, _, _), + PINGROUP(61, _, _, _, _, _, _, _, _, _), + PINGROUP(62, _, _, _, _, _, _, _, _, _), + PINGROUP(63, atest_char3, dbg_out, bimc_dte0, _, _, _, _, _, _), + PINGROUP(64, _, _, _, _, _, _, _, _, _), + PINGROUP(65, bimc_dte0, _, _, _, _, _, _, _, _), + PINGROUP(66, sec_mi2s_mclk_b, pri_mi2s, _, qdss_tracedata_b, _, _, _, _, _), + PINGROUP(67, cdc_pdm0, atest_char1, ebi_cdc, _, dac_calib17, _, _, _, _), + PINGROUP(68, cdc_pdm0, atest_char0, _, _, _, _, _, _, _), + PINGROUP(69, cdc_pdm0, pri_mi2s_mclk_b, ebi_cdc, _, _, _, _, _, _), + PINGROUP(70, lpass_slimbus, cdc_pdm0, _, _, _, _, _, _, _), + PINGROUP(71, lpass_slimbus0, cdc_pdm0, _, _, _, _, _, _, _), + PINGROUP(72, lpass_slimbus1, cdc_pdm0, _, _, _, _, _, _, _), + PINGROUP(73, cdc_pdm0, _, _, _, _, _, _, _, _), + PINGROUP(74, cdc_pdm0, _, _, _, _, _, _, _, _), + PINGROUP(75, wcss_bt, atest_char2, _, ebi_ch0, _, _, _, _, _), + PINGROUP(76, wcss_wlan2, _, _, _, _, _, _, _, _), + PINGROUP(77, wcss_wlan1, _, _, _, _, _, _, _, _), + PINGROUP(78, wcss_wlan0, _, _, _, _, _, _, _, _), + PINGROUP(79, wcss_wlan, _, _, _, _, _, _, _, _), + PINGROUP(80, wcss_wlan, _, _, _, _, _, _, _, _), + PINGROUP(81, wcss_fm, ext_lpass, _, _, _, _, _, _, _), + PINGROUP(82, wcss_fm, mss_lte, _, _, _, _, _, _, _), + PINGROUP(83, wcss_bt, mss_lte, _, _, _, _, _, _, _), + PINGROUP(84, wcss_bt, _, _, _, _, _, _, _, _), + PINGROUP(85, pbs0, cri_trng0, _, _, _, _, _, _, _), + PINGROUP(86, pbs1, cri_trng1, qdss_tracedata_b, _, _, _, _, _, _), + PINGROUP(87, pbs2, cri_trng, qdss_tracedata_b, gcc_tlmm, _, _, _, _, _), + PINGROUP(88, pri_mi2s, _, _, _, qdss_tracedata_b, _, _, _, _), + PINGROUP(89, dmic0_clk, blsp7_spi, _, _, _, _, _, _, _), + PINGROUP(90, dmic0_data, blsp7_spi, _, _, _, _, _, _, _), + PINGROUP(91, pri_mi2s, _, _, _, qdss_cti_trig_in_a1, _, _, _, _), + PINGROUP(92, pri_mi2s_ws, _, _, _, qdss_tracedata_b, _, _, _, _), + PINGROUP(93, pri_mi2s, _, _, _, _, _, _, _, _), + PINGROUP(94, wsa_io, pri_mi2s, _, _, _, _, _, _, _), + PINGROUP(95, wsa_io, pri_mi2s, _, _, _, _, _, _, _), + PINGROUP(96, blsp_spi8, _, _, _, _, _, _, _, _), + PINGROUP(97, blsp_spi8, _, _, _, _, _, _, _, _), + PINGROUP(98, blsp_i2c8, blsp_spi8, gcc_plltest, _, _, _, _, _, _), + PINGROUP(99, blsp_i2c8, blsp_spi8, gcc_plltest, _, _, _, _, _, _), + PINGROUP(100, _, _, _, _, _, _, _, _, _), + PINGROUP(101, _, _, _, _, _, _, _, _, _), + PINGROUP(102, _, _, _, _, _, _, _, _, _), + PINGROUP(103, _, _, _, _, _, _, _, _, _), + PINGROUP(104, _, _, _, _, _, _, _, _, _), + PINGROUP(105, _, _, _, _, _, _, _, _, _), + PINGROUP(106, _, _, _, _, _, _, _, _, _), + PINGROUP(107, _, _, _, _, _, _, _, _, _), + PINGROUP(108, _, _, _, _, _, _, _, _, _), + PINGROUP(109, _, _, _, _, _, _, _, _, _), + PINGROUP(110, _, _, _, _, _, _, _, _, _), + PINGROUP(111, _, _, nav_pps_in_a, _, _, _, _, _, _), + PINGROUP(112, _, pa_indicator, _, _, _, _, _, _, _), + PINGROUP(113, _, nav_pps_in_b, nav_pps, modem_tsync, nav_tsync, _, _, _, _), + PINGROUP(114, _, ssbi_wtr1, _, _, _, _, _, _, _), + PINGROUP(115, _, gsm1_tx, _, dac_calib18, _, _, _, _, _), + PINGROUP(116, _, _, _, _, _, _, _, _, _), + PINGROUP(117, gsm0_tx, _, _, _, _, _, _, _, _), + PINGROUP(118, _, ebi_cdc, _, _, _, _, _, _, _), + PINGROUP(119, _, ebi_cdc, _, _, _, _, _, _, _), + PINGROUP(120, _, atest_char, ebi_cdc, _, atest_tsens, _, _, _, _), + PINGROUP(121, _, _, _, bimc_dte1, _, _, _, _, _), + PINGROUP(122, _, _, _, bimc_dte1, _, _, _, _, _), + PINGROUP(123, _, ssbi_wtr1, ebi_cdc, _, _, _, _, _, _), + PINGROUP(124, _, _, _, _, _, _, _, _, _), + PINGROUP(125, _, _, _, _, _, _, _, _, _), + PINGROUP(126, _, _, _, _, _, _, _, _, _), + PINGROUP(127, _, _, _, _, _, _, _, _, _), + PINGROUP(128, cam_mclk, _, dac_calib20, _, _, _, _, _, _), + PINGROUP(129, ddr_bist, _, dac_calib21, _, _, _, _, _, _), + PINGROUP(130, ddr_bist, _, dac_calib22, _, _, _, _, _, _), + PINGROUP(131, ddr_bist, _, dac_calib23, _, _, _, _, _, _), + PINGROUP(132, ddr_bist, _, dac_calib24, _, _, _, _, _, _), + PINGROUP(133, _, dac_calib25, _, _, _, _, _, _, _), + PINGROUP(134, _, _, _, _, _, _, _, _, _), + PINGROUP(135, sec_mi2s, blsp_spi7, blsp_i2c7, _, _, _, _, _, _), + PINGROUP(136, sec_mi2s, blsp_spi7, blsp_i2c7, _, _, _, _, _, _), + PINGROUP(137, sec_mi2s, blsp_spi7, _, _, _, _, _, _, _), + PINGROUP(138, sec_mi2s, blsp_spi7, _, _, _, _, _, _, _), + PINGROUP(139, tsens_max, _, _, _, _, _, _, _, _), + PINGROUP(140, _, _, _, _, _, _, _, _, _), + PINGROUP(141, _, _, _, _, _, _, _, _, _), + SDC_QDSD_PINGROUP(qdsd_clk, 0x19c000, 3, 0), + SDC_QDSD_PINGROUP(qdsd_cmd, 0x19c000, 8, 5), + SDC_QDSD_PINGROUP(qdsd_data0, 0x19c000, 13, 10), + SDC_QDSD_PINGROUP(qdsd_data1, 0x19c000, 18, 15), + SDC_QDSD_PINGROUP(qdsd_data2, 0x19c000, 23, 20), + SDC_QDSD_PINGROUP(qdsd_data3, 0x19c000, 28, 25), + SDC_QDSD_PINGROUP(sdc1_clk, 0x10a000, 13, 6), + SDC_QDSD_PINGROUP(sdc1_cmd, 0x10a000, 11, 3), + SDC_QDSD_PINGROUP(sdc1_data, 0x10a000, 9, 0), + SDC_QDSD_PINGROUP(sdc1_rclk, 0x10a000, 15, 0), + SDC_QDSD_PINGROUP(sdc2_clk, 0x109000, 14, 6), + SDC_QDSD_PINGROUP(sdc2_cmd, 0x109000, 11, 3), + SDC_QDSD_PINGROUP(sdc2_data, 0x109000, 9, 0), +}; + +static const struct msm_pinctrl_soc_data msm8953_pinctrl = { + .pins = msm8953_pins, + .npins = ARRAY_SIZE(msm8953_pins), + .functions = msm8953_functions, + .nfunctions = ARRAY_SIZE(msm8953_functions), + .groups = msm8953_groups, + .ngroups = ARRAY_SIZE(msm8953_groups), + .ngpios = 142, +}; + +static int msm8953_pinctrl_probe(struct platform_device *pdev) +{ + return msm_pinctrl_probe(pdev, &msm8953_pinctrl); +} + +static const struct of_device_id msm8953_pinctrl_of_match[] = { + { .compatible = "qcom,msm8953-pinctrl", }, + { }, +}; + +static struct platform_driver msm8953_pinctrl_driver = { + .driver = { + .name = "msm8953-pinctrl", + .of_match_table = msm8953_pinctrl_of_match, + }, + .probe = msm8953_pinctrl_probe, + .remove = msm_pinctrl_remove, +}; + +static int __init msm8953_pinctrl_init(void) +{ + return platform_driver_register(&msm8953_pinctrl_driver); +} +arch_initcall(msm8953_pinctrl_init); + +static void __exit msm8953_pinctrl_exit(void) +{ + platform_driver_unregister(&msm8953_pinctrl_driver); +} +module_exit(msm8953_pinctrl_exit); + +MODULE_DESCRIPTION("QTI msm8953 pinctrl driver"); +MODULE_LICENSE("GPL v2"); +MODULE_DEVICE_TABLE(of, msm8953_pinctrl_of_match); diff --git a/drivers/pinctrl/qcom/pinctrl-msm8960.c b/drivers/pinctrl/qcom/pinctrl-msm8960.c new file mode 100644 index 0000000000..ebe230b3b4 --- /dev/null +++ b/drivers/pinctrl/qcom/pinctrl-msm8960.c @@ -0,0 +1,1267 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2014, Sony Mobile Communications AB. + */ + +#include <linux/module.h> +#include <linux/of.h> +#include <linux/platform_device.h> +#include <linux/pinctrl/pinmux.h> + +#include "pinctrl-msm.h" + +static const struct pinctrl_pin_desc msm8960_pins[] = { + PINCTRL_PIN(0, "GPIO_0"), + PINCTRL_PIN(1, "GPIO_1"), + PINCTRL_PIN(2, "GPIO_2"), + PINCTRL_PIN(3, "GPIO_3"), + PINCTRL_PIN(4, "GPIO_4"), + PINCTRL_PIN(5, "GPIO_5"), + PINCTRL_PIN(6, "GPIO_6"), + PINCTRL_PIN(7, "GPIO_7"), + PINCTRL_PIN(8, "GPIO_8"), + PINCTRL_PIN(9, "GPIO_9"), + PINCTRL_PIN(10, "GPIO_10"), + PINCTRL_PIN(11, "GPIO_11"), + PINCTRL_PIN(12, "GPIO_12"), + PINCTRL_PIN(13, "GPIO_13"), + PINCTRL_PIN(14, "GPIO_14"), + PINCTRL_PIN(15, "GPIO_15"), + PINCTRL_PIN(16, "GPIO_16"), + PINCTRL_PIN(17, "GPIO_17"), + PINCTRL_PIN(18, "GPIO_18"), + PINCTRL_PIN(19, "GPIO_19"), + PINCTRL_PIN(20, "GPIO_20"), + PINCTRL_PIN(21, "GPIO_21"), + PINCTRL_PIN(22, "GPIO_22"), + PINCTRL_PIN(23, "GPIO_23"), + PINCTRL_PIN(24, "GPIO_24"), + PINCTRL_PIN(25, "GPIO_25"), + PINCTRL_PIN(26, "GPIO_26"), + PINCTRL_PIN(27, "GPIO_27"), + PINCTRL_PIN(28, "GPIO_28"), + PINCTRL_PIN(29, "GPIO_29"), + PINCTRL_PIN(30, "GPIO_30"), + PINCTRL_PIN(31, "GPIO_31"), + PINCTRL_PIN(32, "GPIO_32"), + PINCTRL_PIN(33, "GPIO_33"), + PINCTRL_PIN(34, "GPIO_34"), + PINCTRL_PIN(35, "GPIO_35"), + PINCTRL_PIN(36, "GPIO_36"), + PINCTRL_PIN(37, "GPIO_37"), + PINCTRL_PIN(38, "GPIO_38"), + PINCTRL_PIN(39, "GPIO_39"), + PINCTRL_PIN(40, "GPIO_40"), + PINCTRL_PIN(41, "GPIO_41"), + PINCTRL_PIN(42, "GPIO_42"), + PINCTRL_PIN(43, "GPIO_43"), + PINCTRL_PIN(44, "GPIO_44"), + PINCTRL_PIN(45, "GPIO_45"), + PINCTRL_PIN(46, "GPIO_46"), + PINCTRL_PIN(47, "GPIO_47"), + PINCTRL_PIN(48, "GPIO_48"), + PINCTRL_PIN(49, "GPIO_49"), + PINCTRL_PIN(50, "GPIO_50"), + PINCTRL_PIN(51, "GPIO_51"), + PINCTRL_PIN(52, "GPIO_52"), + PINCTRL_PIN(53, "GPIO_53"), + PINCTRL_PIN(54, "GPIO_54"), + PINCTRL_PIN(55, "GPIO_55"), + PINCTRL_PIN(56, "GPIO_56"), + PINCTRL_PIN(57, "GPIO_57"), + PINCTRL_PIN(58, "GPIO_58"), + PINCTRL_PIN(59, "GPIO_59"), + PINCTRL_PIN(60, "GPIO_60"), + PINCTRL_PIN(61, "GPIO_61"), + PINCTRL_PIN(62, "GPIO_62"), + PINCTRL_PIN(63, "GPIO_63"), + PINCTRL_PIN(64, "GPIO_64"), + PINCTRL_PIN(65, "GPIO_65"), + PINCTRL_PIN(66, "GPIO_66"), + PINCTRL_PIN(67, "GPIO_67"), + PINCTRL_PIN(68, "GPIO_68"), + PINCTRL_PIN(69, "GPIO_69"), + PINCTRL_PIN(70, "GPIO_70"), + PINCTRL_PIN(71, "GPIO_71"), + PINCTRL_PIN(72, "GPIO_72"), + PINCTRL_PIN(73, "GPIO_73"), + PINCTRL_PIN(74, "GPIO_74"), + PINCTRL_PIN(75, "GPIO_75"), + PINCTRL_PIN(76, "GPIO_76"), + PINCTRL_PIN(77, "GPIO_77"), + PINCTRL_PIN(78, "GPIO_78"), + PINCTRL_PIN(79, "GPIO_79"), + PINCTRL_PIN(80, "GPIO_80"), + PINCTRL_PIN(81, "GPIO_81"), + PINCTRL_PIN(82, "GPIO_82"), + PINCTRL_PIN(83, "GPIO_83"), + PINCTRL_PIN(84, "GPIO_84"), + PINCTRL_PIN(85, "GPIO_85"), + PINCTRL_PIN(86, "GPIO_86"), + PINCTRL_PIN(87, "GPIO_87"), + PINCTRL_PIN(88, "GPIO_88"), + PINCTRL_PIN(89, "GPIO_89"), + PINCTRL_PIN(90, "GPIO_90"), + PINCTRL_PIN(91, "GPIO_91"), + PINCTRL_PIN(92, "GPIO_92"), + PINCTRL_PIN(93, "GPIO_93"), + PINCTRL_PIN(94, "GPIO_94"), + PINCTRL_PIN(95, "GPIO_95"), + PINCTRL_PIN(96, "GPIO_96"), + PINCTRL_PIN(97, "GPIO_97"), + PINCTRL_PIN(98, "GPIO_98"), + PINCTRL_PIN(99, "GPIO_99"), + PINCTRL_PIN(100, "GPIO_100"), + PINCTRL_PIN(101, "GPIO_101"), + PINCTRL_PIN(102, "GPIO_102"), + PINCTRL_PIN(103, "GPIO_103"), + PINCTRL_PIN(104, "GPIO_104"), + PINCTRL_PIN(105, "GPIO_105"), + PINCTRL_PIN(106, "GPIO_106"), + PINCTRL_PIN(107, "GPIO_107"), + PINCTRL_PIN(108, "GPIO_108"), + PINCTRL_PIN(109, "GPIO_109"), + PINCTRL_PIN(110, "GPIO_110"), + PINCTRL_PIN(111, "GPIO_111"), + PINCTRL_PIN(112, "GPIO_112"), + PINCTRL_PIN(113, "GPIO_113"), + PINCTRL_PIN(114, "GPIO_114"), + PINCTRL_PIN(115, "GPIO_115"), + PINCTRL_PIN(116, "GPIO_116"), + PINCTRL_PIN(117, "GPIO_117"), + PINCTRL_PIN(118, "GPIO_118"), + PINCTRL_PIN(119, "GPIO_119"), + PINCTRL_PIN(120, "GPIO_120"), + PINCTRL_PIN(121, "GPIO_121"), + PINCTRL_PIN(122, "GPIO_122"), + PINCTRL_PIN(123, "GPIO_123"), + PINCTRL_PIN(124, "GPIO_124"), + PINCTRL_PIN(125, "GPIO_125"), + PINCTRL_PIN(126, "GPIO_126"), + PINCTRL_PIN(127, "GPIO_127"), + PINCTRL_PIN(128, "GPIO_128"), + PINCTRL_PIN(129, "GPIO_129"), + PINCTRL_PIN(130, "GPIO_130"), + PINCTRL_PIN(131, "GPIO_131"), + PINCTRL_PIN(132, "GPIO_132"), + PINCTRL_PIN(133, "GPIO_133"), + PINCTRL_PIN(134, "GPIO_134"), + PINCTRL_PIN(135, "GPIO_135"), + PINCTRL_PIN(136, "GPIO_136"), + PINCTRL_PIN(137, "GPIO_137"), + PINCTRL_PIN(138, "GPIO_138"), + PINCTRL_PIN(139, "GPIO_139"), + PINCTRL_PIN(140, "GPIO_140"), + PINCTRL_PIN(141, "GPIO_141"), + PINCTRL_PIN(142, "GPIO_142"), + PINCTRL_PIN(143, "GPIO_143"), + PINCTRL_PIN(144, "GPIO_144"), + PINCTRL_PIN(145, "GPIO_145"), + PINCTRL_PIN(146, "GPIO_146"), + PINCTRL_PIN(147, "GPIO_147"), + PINCTRL_PIN(148, "GPIO_148"), + PINCTRL_PIN(149, "GPIO_149"), + PINCTRL_PIN(150, "GPIO_150"), + PINCTRL_PIN(151, "GPIO_151"), + + PINCTRL_PIN(152, "SDC1_CLK"), + PINCTRL_PIN(153, "SDC1_CMD"), + PINCTRL_PIN(154, "SDC1_DATA"), + PINCTRL_PIN(155, "SDC3_CLK"), + PINCTRL_PIN(156, "SDC3_CMD"), + PINCTRL_PIN(157, "SDC3_DATA"), +}; + +#define DECLARE_MSM_GPIO_PINS(pin) static const unsigned int gpio##pin##_pins[] = { pin } +DECLARE_MSM_GPIO_PINS(0); +DECLARE_MSM_GPIO_PINS(1); +DECLARE_MSM_GPIO_PINS(2); +DECLARE_MSM_GPIO_PINS(3); +DECLARE_MSM_GPIO_PINS(4); +DECLARE_MSM_GPIO_PINS(5); +DECLARE_MSM_GPIO_PINS(6); +DECLARE_MSM_GPIO_PINS(7); +DECLARE_MSM_GPIO_PINS(8); +DECLARE_MSM_GPIO_PINS(9); +DECLARE_MSM_GPIO_PINS(10); +DECLARE_MSM_GPIO_PINS(11); +DECLARE_MSM_GPIO_PINS(12); +DECLARE_MSM_GPIO_PINS(13); +DECLARE_MSM_GPIO_PINS(14); +DECLARE_MSM_GPIO_PINS(15); +DECLARE_MSM_GPIO_PINS(16); +DECLARE_MSM_GPIO_PINS(17); +DECLARE_MSM_GPIO_PINS(18); +DECLARE_MSM_GPIO_PINS(19); +DECLARE_MSM_GPIO_PINS(20); +DECLARE_MSM_GPIO_PINS(21); +DECLARE_MSM_GPIO_PINS(22); +DECLARE_MSM_GPIO_PINS(23); +DECLARE_MSM_GPIO_PINS(24); +DECLARE_MSM_GPIO_PINS(25); +DECLARE_MSM_GPIO_PINS(26); +DECLARE_MSM_GPIO_PINS(27); +DECLARE_MSM_GPIO_PINS(28); +DECLARE_MSM_GPIO_PINS(29); +DECLARE_MSM_GPIO_PINS(30); +DECLARE_MSM_GPIO_PINS(31); +DECLARE_MSM_GPIO_PINS(32); +DECLARE_MSM_GPIO_PINS(33); +DECLARE_MSM_GPIO_PINS(34); +DECLARE_MSM_GPIO_PINS(35); +DECLARE_MSM_GPIO_PINS(36); +DECLARE_MSM_GPIO_PINS(37); +DECLARE_MSM_GPIO_PINS(38); +DECLARE_MSM_GPIO_PINS(39); +DECLARE_MSM_GPIO_PINS(40); +DECLARE_MSM_GPIO_PINS(41); +DECLARE_MSM_GPIO_PINS(42); +DECLARE_MSM_GPIO_PINS(43); +DECLARE_MSM_GPIO_PINS(44); +DECLARE_MSM_GPIO_PINS(45); +DECLARE_MSM_GPIO_PINS(46); +DECLARE_MSM_GPIO_PINS(47); +DECLARE_MSM_GPIO_PINS(48); +DECLARE_MSM_GPIO_PINS(49); +DECLARE_MSM_GPIO_PINS(50); +DECLARE_MSM_GPIO_PINS(51); +DECLARE_MSM_GPIO_PINS(52); +DECLARE_MSM_GPIO_PINS(53); +DECLARE_MSM_GPIO_PINS(54); +DECLARE_MSM_GPIO_PINS(55); +DECLARE_MSM_GPIO_PINS(56); +DECLARE_MSM_GPIO_PINS(57); +DECLARE_MSM_GPIO_PINS(58); +DECLARE_MSM_GPIO_PINS(59); +DECLARE_MSM_GPIO_PINS(60); +DECLARE_MSM_GPIO_PINS(61); +DECLARE_MSM_GPIO_PINS(62); +DECLARE_MSM_GPIO_PINS(63); +DECLARE_MSM_GPIO_PINS(64); +DECLARE_MSM_GPIO_PINS(65); +DECLARE_MSM_GPIO_PINS(66); +DECLARE_MSM_GPIO_PINS(67); +DECLARE_MSM_GPIO_PINS(68); +DECLARE_MSM_GPIO_PINS(69); +DECLARE_MSM_GPIO_PINS(70); +DECLARE_MSM_GPIO_PINS(71); +DECLARE_MSM_GPIO_PINS(72); +DECLARE_MSM_GPIO_PINS(73); +DECLARE_MSM_GPIO_PINS(74); +DECLARE_MSM_GPIO_PINS(75); +DECLARE_MSM_GPIO_PINS(76); +DECLARE_MSM_GPIO_PINS(77); +DECLARE_MSM_GPIO_PINS(78); +DECLARE_MSM_GPIO_PINS(79); +DECLARE_MSM_GPIO_PINS(80); +DECLARE_MSM_GPIO_PINS(81); +DECLARE_MSM_GPIO_PINS(82); +DECLARE_MSM_GPIO_PINS(83); +DECLARE_MSM_GPIO_PINS(84); +DECLARE_MSM_GPIO_PINS(85); +DECLARE_MSM_GPIO_PINS(86); +DECLARE_MSM_GPIO_PINS(87); +DECLARE_MSM_GPIO_PINS(88); +DECLARE_MSM_GPIO_PINS(89); +DECLARE_MSM_GPIO_PINS(90); +DECLARE_MSM_GPIO_PINS(91); +DECLARE_MSM_GPIO_PINS(92); +DECLARE_MSM_GPIO_PINS(93); +DECLARE_MSM_GPIO_PINS(94); +DECLARE_MSM_GPIO_PINS(95); +DECLARE_MSM_GPIO_PINS(96); +DECLARE_MSM_GPIO_PINS(97); +DECLARE_MSM_GPIO_PINS(98); +DECLARE_MSM_GPIO_PINS(99); +DECLARE_MSM_GPIO_PINS(100); +DECLARE_MSM_GPIO_PINS(101); +DECLARE_MSM_GPIO_PINS(102); +DECLARE_MSM_GPIO_PINS(103); +DECLARE_MSM_GPIO_PINS(104); +DECLARE_MSM_GPIO_PINS(105); +DECLARE_MSM_GPIO_PINS(106); +DECLARE_MSM_GPIO_PINS(107); +DECLARE_MSM_GPIO_PINS(108); +DECLARE_MSM_GPIO_PINS(109); +DECLARE_MSM_GPIO_PINS(110); +DECLARE_MSM_GPIO_PINS(111); +DECLARE_MSM_GPIO_PINS(112); +DECLARE_MSM_GPIO_PINS(113); +DECLARE_MSM_GPIO_PINS(114); +DECLARE_MSM_GPIO_PINS(115); +DECLARE_MSM_GPIO_PINS(116); +DECLARE_MSM_GPIO_PINS(117); +DECLARE_MSM_GPIO_PINS(118); +DECLARE_MSM_GPIO_PINS(119); +DECLARE_MSM_GPIO_PINS(120); +DECLARE_MSM_GPIO_PINS(121); +DECLARE_MSM_GPIO_PINS(122); +DECLARE_MSM_GPIO_PINS(123); +DECLARE_MSM_GPIO_PINS(124); +DECLARE_MSM_GPIO_PINS(125); +DECLARE_MSM_GPIO_PINS(126); +DECLARE_MSM_GPIO_PINS(127); +DECLARE_MSM_GPIO_PINS(128); +DECLARE_MSM_GPIO_PINS(129); +DECLARE_MSM_GPIO_PINS(130); +DECLARE_MSM_GPIO_PINS(131); +DECLARE_MSM_GPIO_PINS(132); +DECLARE_MSM_GPIO_PINS(133); +DECLARE_MSM_GPIO_PINS(134); +DECLARE_MSM_GPIO_PINS(135); +DECLARE_MSM_GPIO_PINS(136); +DECLARE_MSM_GPIO_PINS(137); +DECLARE_MSM_GPIO_PINS(138); +DECLARE_MSM_GPIO_PINS(139); +DECLARE_MSM_GPIO_PINS(140); +DECLARE_MSM_GPIO_PINS(141); +DECLARE_MSM_GPIO_PINS(142); +DECLARE_MSM_GPIO_PINS(143); +DECLARE_MSM_GPIO_PINS(144); +DECLARE_MSM_GPIO_PINS(145); +DECLARE_MSM_GPIO_PINS(146); +DECLARE_MSM_GPIO_PINS(147); +DECLARE_MSM_GPIO_PINS(148); +DECLARE_MSM_GPIO_PINS(149); +DECLARE_MSM_GPIO_PINS(150); +DECLARE_MSM_GPIO_PINS(151); + +static const unsigned int sdc1_clk_pins[] = { 152 }; +static const unsigned int sdc1_cmd_pins[] = { 153 }; +static const unsigned int sdc1_data_pins[] = { 154 }; +static const unsigned int sdc3_clk_pins[] = { 155 }; +static const unsigned int sdc3_cmd_pins[] = { 156 }; +static const unsigned int sdc3_data_pins[] = { 157 }; + +#define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7, f8, f9, f10, f11) \ + { \ + .grp = PINCTRL_PINGROUP("gpio" #id, \ + gpio##id##_pins, \ + ARRAY_SIZE(gpio##id##_pins)), \ + .funcs = (int[]){ \ + msm_mux_gpio, \ + msm_mux_##f1, \ + msm_mux_##f2, \ + msm_mux_##f3, \ + msm_mux_##f4, \ + msm_mux_##f5, \ + msm_mux_##f6, \ + msm_mux_##f7, \ + msm_mux_##f8, \ + msm_mux_##f9, \ + msm_mux_##f10, \ + msm_mux_##f11 \ + }, \ + .nfuncs = 12, \ + .ctl_reg = 0x1000 + 0x10 * id, \ + .io_reg = 0x1004 + 0x10 * id, \ + .intr_cfg_reg = 0x1008 + 0x10 * id, \ + .intr_status_reg = 0x100c + 0x10 * id, \ + .intr_target_reg = 0x400 + 0x4 * id, \ + .mux_bit = 2, \ + .pull_bit = 0, \ + .drv_bit = 6, \ + .oe_bit = 9, \ + .in_bit = 0, \ + .out_bit = 1, \ + .intr_enable_bit = 0, \ + .intr_status_bit = 0, \ + .intr_ack_high = 1, \ + .intr_target_bit = 0, \ + .intr_target_kpss_val = 4, \ + .intr_raw_status_bit = 3, \ + .intr_polarity_bit = 1, \ + .intr_detection_bit = 2, \ + .intr_detection_width = 1, \ + } + +#define SDC_PINGROUP(pg_name, ctl, pull, drv) \ + { \ + .grp = PINCTRL_PINGROUP(#pg_name, \ + pg_name##_pins, \ + ARRAY_SIZE(pg_name##_pins)), \ + .ctl_reg = ctl, \ + .io_reg = 0, \ + .intr_cfg_reg = 0, \ + .intr_status_reg = 0, \ + .intr_target_reg = 0, \ + .mux_bit = -1, \ + .pull_bit = pull, \ + .drv_bit = drv, \ + .oe_bit = -1, \ + .in_bit = -1, \ + .out_bit = -1, \ + .intr_enable_bit = -1, \ + .intr_status_bit = -1, \ + .intr_target_bit = -1, \ + .intr_target_kpss_val = -1, \ + .intr_raw_status_bit = -1, \ + .intr_polarity_bit = -1, \ + .intr_detection_bit = -1, \ + .intr_detection_width = -1, \ + } + +enum msm8960_functions { + msm_mux_audio_pcm, + msm_mux_bt, + msm_mux_cam_mclk0, + msm_mux_cam_mclk1, + msm_mux_cam_mclk2, + msm_mux_codec_mic_i2s, + msm_mux_codec_spkr_i2s, + msm_mux_ext_gps, + msm_mux_fm, + msm_mux_gps_blanking, + msm_mux_gps_pps_in, + msm_mux_gps_pps_out, + msm_mux_gp_clk_0a, + msm_mux_gp_clk_0b, + msm_mux_gp_clk_1a, + msm_mux_gp_clk_1b, + msm_mux_gp_clk_2a, + msm_mux_gp_clk_2b, + msm_mux_gp_mn, + msm_mux_gp_pdm_0a, + msm_mux_gp_pdm_0b, + msm_mux_gp_pdm_1a, + msm_mux_gp_pdm_1b, + msm_mux_gp_pdm_2a, + msm_mux_gp_pdm_2b, + msm_mux_gpio, + msm_mux_gsbi1, + msm_mux_gsbi1_spi_cs1_n, + msm_mux_gsbi1_spi_cs2a_n, + msm_mux_gsbi1_spi_cs2b_n, + msm_mux_gsbi1_spi_cs3_n, + msm_mux_gsbi2, + msm_mux_gsbi2_spi_cs1_n, + msm_mux_gsbi2_spi_cs2_n, + msm_mux_gsbi2_spi_cs3_n, + msm_mux_gsbi3, + msm_mux_gsbi4, + msm_mux_gsbi4_3d_cam_i2c_l, + msm_mux_gsbi4_3d_cam_i2c_r, + msm_mux_gsbi5, + msm_mux_gsbi5_3d_cam_i2c_l, + msm_mux_gsbi5_3d_cam_i2c_r, + msm_mux_gsbi6, + msm_mux_gsbi7, + msm_mux_gsbi8, + msm_mux_gsbi9, + msm_mux_gsbi10, + msm_mux_gsbi11, + msm_mux_gsbi11_spi_cs1a_n, + msm_mux_gsbi11_spi_cs1b_n, + msm_mux_gsbi11_spi_cs2a_n, + msm_mux_gsbi11_spi_cs2b_n, + msm_mux_gsbi11_spi_cs3_n, + msm_mux_gsbi12, + msm_mux_hdmi_cec, + msm_mux_hdmi_ddc_clock, + msm_mux_hdmi_ddc_data, + msm_mux_hdmi_hot_plug_detect, + msm_mux_hsic, + msm_mux_mdp_vsync, + msm_mux_mi2s, + msm_mux_mic_i2s, + msm_mux_pmb_clk, + msm_mux_pmb_ext_ctrl, + msm_mux_ps_hold, + msm_mux_rpm_wdog, + msm_mux_sdc2, + msm_mux_sdc4, + msm_mux_sdc5, + msm_mux_slimbus1, + msm_mux_slimbus2, + msm_mux_spkr_i2s, + msm_mux_ssbi1, + msm_mux_ssbi2, + msm_mux_ssbi_ext_gps, + msm_mux_ssbi_pmic2, + msm_mux_ssbi_qpa1, + msm_mux_ssbi_ts, + msm_mux_tsif1, + msm_mux_tsif2, + msm_mux_ts_eoc, + msm_mux_usb_fs1, + msm_mux_usb_fs1_oe, + msm_mux_usb_fs1_oe_n, + msm_mux_usb_fs2, + msm_mux_usb_fs2_oe, + msm_mux_usb_fs2_oe_n, + msm_mux_vfe_camif_timer1_a, + msm_mux_vfe_camif_timer1_b, + msm_mux_vfe_camif_timer2, + msm_mux_vfe_camif_timer3_a, + msm_mux_vfe_camif_timer3_b, + msm_mux_vfe_camif_timer4_a, + msm_mux_vfe_camif_timer4_b, + msm_mux_vfe_camif_timer4_c, + msm_mux_vfe_camif_timer5_a, + msm_mux_vfe_camif_timer5_b, + msm_mux_vfe_camif_timer6_a, + msm_mux_vfe_camif_timer6_b, + msm_mux_vfe_camif_timer6_c, + msm_mux_vfe_camif_timer7_a, + msm_mux_vfe_camif_timer7_b, + msm_mux_vfe_camif_timer7_c, + msm_mux_wlan, + msm_mux_NA, +}; + +static const char * const audio_pcm_groups[] = { + "gpio63", "gpio64", "gpio65", "gpio66" +}; + +static const char * const bt_groups[] = { + "gpio28", "gpio29", "gpio83" +}; + +static const char * const cam_mclk0_groups[] = { + "gpio5" +}; + +static const char * const cam_mclk1_groups[] = { + "gpio4" +}; + +static const char * const cam_mclk2_groups[] = { + "gpio2" +}; + +static const char * const codec_mic_i2s_groups[] = { + "gpio54", "gpio55", "gpio56", "gpio57", "gpio58" +}; + +static const char * const codec_spkr_i2s_groups[] = { + "gpio59", "gpio60", "gpio61", "gpio62" +}; + +static const char * const ext_gps_groups[] = { + "gpio22", "gpio23", "gpio24", "gpio25" +}; + +static const char * const fm_groups[] = { + "gpio26", "gpio27" +}; + +static const char * const gps_blanking_groups[] = { + "gpio137" +}; + +static const char * const gps_pps_in_groups[] = { + "gpio37" +}; + +static const char * const gps_pps_out_groups[] = { + "gpio37" +}; + +static const char * const gp_clk_0a_groups[] = { + "gpio3" +}; + +static const char * const gp_clk_0b_groups[] = { + "gpio54" +}; + +static const char * const gp_clk_1a_groups[] = { + "gpio4" +}; + +static const char * const gp_clk_1b_groups[] = { + "gpio70" +}; + +static const char * const gp_clk_2a_groups[] = { + "gpio52" +}; + +static const char * const gp_clk_2b_groups[] = { + "gpio37" +}; + +static const char * const gp_mn_groups[] = { + "gpio2" +}; + +static const char * const gp_pdm_0a_groups[] = { + "gpio58" +}; + +static const char * const gp_pdm_0b_groups[] = { + "gpio39" +}; + +static const char * const gp_pdm_1a_groups[] = { + "gpio94" +}; + +static const char * const gp_pdm_1b_groups[] = { + "gpio64" +}; + +static const char * const gp_pdm_2a_groups[] = { + "gpio69" +}; + +static const char * const gp_pdm_2b_groups[] = { + "gpio53" +}; + +static const char * const gpio_groups[] = { + "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7", + "gpio8", "gpio9", "gpio10", "gpio11", "gpio12", "gpio13", "gpio14", + "gpio15", "gpio16", "gpio17", "gpio18", "gpio19", "gpio20", "gpio21", + "gpio22", "gpio23", "gpio24", "gpio25", "gpio26", "gpio27", "gpio28", + "gpio29", "gpio30", "gpio31", "gpio32", "gpio33", "gpio34", "gpio35", + "gpio36", "gpio37", "gpio38", "gpio39", "gpio40", "gpio41", "gpio42", + "gpio43", "gpio44", "gpio45", "gpio46", "gpio47", "gpio48", "gpio49", + "gpio50", "gpio51", "gpio52", "gpio53", "gpio54", "gpio55", "gpio56", + "gpio57", "gpio58", "gpio59", "gpio60", "gpio61", "gpio62", "gpio63", + "gpio64", "gpio65", "gpio66", "gpio67", "gpio68", "gpio69", "gpio70", + "gpio71", "gpio72", "gpio73", "gpio74", "gpio75", "gpio76", "gpio77", + "gpio78", "gpio79", "gpio80", "gpio81", "gpio82", "gpio83", "gpio84", + "gpio85", "gpio86", "gpio87", "gpio88", "gpio89", "gpio90", "gpio91", + "gpio92", "gpio93", "gpio94", "gpio95", "gpio96", "gpio97", "gpio98", + "gpio99", "gpio100", "gpio101", "gpio102", "gpio103", "gpio104", + "gpio105", "gpio106", "gpio107", "gpio108", "gpio109", "gpio110", + "gpio111", "gpio112", "gpio113", "gpio114", "gpio115", "gpio116", + "gpio117", "gpio118", "gpio119", "gpio120", "gpio121", "gpio122", + "gpio123", "gpio124", "gpio125", "gpio126", "gpio127", "gpio128", + "gpio129", "gpio130", "gpio131", "gpio132", "gpio133", "gpio134", + "gpio135", "gpio136", "gpio137", "gpio138", "gpio139", "gpio140", + "gpio141", "gpio142", "gpio143", "gpio144", "gpio145", "gpio146", + "gpio147", "gpio148", "gpio149", "gpio150", "gpio151" +}; + +static const char * const gsbi1_groups[] = { + "gpio6", "gpio7", "gpio8", "gpio9" +}; + +static const char * const gsbi1_spi_cs1_n_groups[] = { + "gpio14" +}; + +static const char * const gsbi1_spi_cs2a_n_groups[] = { + "gpio15" +}; + +static const char * const gsbi1_spi_cs2b_n_groups[] = { + "gpio17" +}; + +static const char * const gsbi1_spi_cs3_n_groups[] = { + "gpio16" +}; + +static const char * const gsbi2_groups[] = { + "gpio10", "gpio11", "gpio12", "gpio13" +}; + +static const char * const gsbi2_spi_cs1_n_groups[] = { + "gpio52" +}; + +static const char * const gsbi2_spi_cs2_n_groups[] = { + "gpio68" +}; + +static const char * const gsbi2_spi_cs3_n_groups[] = { + "gpio56" +}; + +static const char * const gsbi3_groups[] = { + "gpio14", "gpio15", "gpio16", "gpio17" +}; + +static const char * const gsbi4_groups[] = { + "gpio18", "gpio19", "gpio20", "gpio21" +}; + +static const char * const gsbi4_3d_cam_i2c_l_groups[] = { + "gpio18", "gpio19" +}; + +static const char * const gsbi4_3d_cam_i2c_r_groups[] = { + "gpio20", "gpio21" +}; + +static const char * const gsbi5_groups[] = { + "gpio22", "gpio23", "gpio24", "gpio25" +}; + +static const char * const gsbi5_3d_cam_i2c_l_groups[] = { + "gpio22", "gpio23" +}; + +static const char * const gsbi5_3d_cam_i2c_r_groups[] = { + "gpio24", "gpio25" +}; + +static const char * const gsbi6_groups[] = { + "gpio26", "gpio27", "gpio28", "gpio29" +}; + +static const char * const gsbi7_groups[] = { + "gpio30", "gpio31", "gpio32", "gpio33" +}; + +static const char * const gsbi8_groups[] = { + "gpio34", "gpio35", "gpio36", "gpio37" +}; + +static const char * const gsbi9_groups[] = { + "gpio93", "gpio94", "gpio95", "gpio96" +}; + +static const char * const gsbi10_groups[] = { + "gpio71", "gpio72", "gpio73", "gpio74" +}; + +static const char * const gsbi11_groups[] = { + "gpio38", "gpio39", "gpio40", "gpio41" +}; + +static const char * const gsbi11_spi_cs1a_n_groups[] = { + "gpio36" +}; + +static const char * const gsbi11_spi_cs1b_n_groups[] = { + "gpio18" +}; + +static const char * const gsbi11_spi_cs2a_n_groups[] = { + "gpio37" +}; + +static const char * const gsbi11_spi_cs2b_n_groups[] = { + "gpio19" +}; + +static const char * const gsbi11_spi_cs3_n_groups[] = { + "gpio76" +}; + +static const char * const gsbi12_groups[] = { + "gpio42", "gpio43", "gpio44", "gpio45" +}; + +static const char * const hdmi_cec_groups[] = { + "gpio99" +}; + +static const char * const hdmi_ddc_clock_groups[] = { + "gpio100" +}; + +static const char * const hdmi_ddc_data_groups[] = { + "gpio101" +}; + +static const char * const hdmi_hot_plug_detect_groups[] = { + "gpio102" +}; + +static const char * const hsic_groups[] = { + "gpio150", "gpio151" +}; + +static const char * const mdp_vsync_groups[] = { + "gpio0", "gpio1", "gpio19" +}; + +static const char * const mi2s_groups[] = { + "gpio47", "gpio48", "gpio49", "gpio50", "gpio51", "gpio52", "gpio53" +}; + +static const char * const mic_i2s_groups[] = { + "gpio71", "gpio72", "gpio73", "gpio74" +}; + +static const char * const pmb_clk_groups[] = { + "gpio21", "gpio86", "gpio112" +}; + +static const char * const pmb_ext_ctrl_groups[] = { + "gpio4", "gpio5" +}; + +static const char * const ps_hold_groups[] = { + "gpio108" +}; + +static const char * const rpm_wdog_groups[] = { + "gpio12" +}; + +static const char * const sdc2_groups[] = { + "gpio89", "gpio90", "gpio91", "gpio92", "gpio93", "gpio94", "gpio95", + "gpio96", "gpio97", "gpio98" +}; + +static const char * const sdc4_groups[] = { + "gpio83", "gpio84", "gpio85", "gpio86", "gpio87", "gpio88" +}; + +static const char * const sdc5_groups[] = { + "gpio77", "gpio78", "gpio79", "gpio80", "gpio81", "gpio82" +}; + +static const char * const slimbus1_groups[] = { + "gpio50", "gpio51", "gpio60", "gpio61" +}; + +static const char * const slimbus2_groups[] = { + "gpio42", "gpio43" +}; + +static const char * const spkr_i2s_groups[] = { + "gpio67", "gpio68", "gpio69", "gpio70" +}; + +static const char * const ssbi1_groups[] = { + "gpio141", "gpio143" +}; + +static const char * const ssbi2_groups[] = { + "gpio140", "gpio142" +}; + +static const char * const ssbi_ext_gps_groups[] = { + "gpio23" +}; + +static const char * const ssbi_pmic2_groups[] = { + "gpio149" +}; + +static const char * const ssbi_qpa1_groups[] = { + "gpio131" +}; + +static const char * const ssbi_ts_groups[] = { + "gpio10" +}; + +static const char * const tsif1_groups[] = { + "gpio75", "gpio76", "gpio77", "gpio82" +}; + +static const char * const tsif2_groups[] = { + "gpio78", "gpio79", "gpio80", "gpio81" +}; + +static const char * const ts_eoc_groups[] = { + "gpio11" +}; + +static const char * const usb_fs1_groups[] = { + "gpio32", "gpio33" +}; + +static const char * const usb_fs1_oe_groups[] = { + "gpio31" +}; + +static const char * const usb_fs1_oe_n_groups[] = { + "gpio31" +}; + +static const char * const usb_fs2_groups[] = { + "gpio34", "gpio35" +}; + +static const char * const usb_fs2_oe_groups[] = { + "gpio36" +}; + +static const char * const usb_fs2_oe_n_groups[] = { + "gpio36" +}; + +static const char * const vfe_camif_timer1_a_groups[] = { + "gpio2" +}; + +static const char * const vfe_camif_timer1_b_groups[] = { + "gpio38" +}; + +static const char * const vfe_camif_timer2_groups[] = { + "gpio3" +}; + +static const char * const vfe_camif_timer3_a_groups[] = { + "gpio4" +}; + +static const char * const vfe_camif_timer3_b_groups[] = { + "gpio151" +}; + +static const char * const vfe_camif_timer4_a_groups[] = { + "gpio65" +}; + +static const char * const vfe_camif_timer4_b_groups[] = { + "gpio150" +}; + +static const char * const vfe_camif_timer4_c_groups[] = { + "gpio10" +}; + +static const char * const vfe_camif_timer5_a_groups[] = { + "gpio66" +}; + +static const char * const vfe_camif_timer5_b_groups[] = { + "gpio39" +}; + +static const char * const vfe_camif_timer6_a_groups[] = { + "gpio71" +}; + +static const char * const vfe_camif_timer6_b_groups[] = { + "gpio0" +}; + +static const char * const vfe_camif_timer6_c_groups[] = { + "gpio18" +}; + +static const char * const vfe_camif_timer7_a_groups[] = { + "gpio67" +}; + +static const char * const vfe_camif_timer7_b_groups[] = { + "gpio1" +}; + +static const char * const vfe_camif_timer7_c_groups[] = { + "gpio19" +}; + +static const char * const wlan_groups[] = { + "gpio84", "gpio85", "gpio86", "gpio87", "gpio88" +}; + +static const struct pinfunction msm8960_functions[] = { + MSM_PIN_FUNCTION(audio_pcm), + MSM_PIN_FUNCTION(bt), + MSM_PIN_FUNCTION(cam_mclk0), + MSM_PIN_FUNCTION(cam_mclk1), + MSM_PIN_FUNCTION(cam_mclk2), + MSM_PIN_FUNCTION(codec_mic_i2s), + MSM_PIN_FUNCTION(codec_spkr_i2s), + MSM_PIN_FUNCTION(ext_gps), + MSM_PIN_FUNCTION(fm), + MSM_PIN_FUNCTION(gps_blanking), + MSM_PIN_FUNCTION(gps_pps_in), + MSM_PIN_FUNCTION(gps_pps_out), + MSM_PIN_FUNCTION(gp_clk_0a), + MSM_PIN_FUNCTION(gp_clk_0b), + MSM_PIN_FUNCTION(gp_clk_1a), + MSM_PIN_FUNCTION(gp_clk_1b), + MSM_PIN_FUNCTION(gp_clk_2a), + MSM_PIN_FUNCTION(gp_clk_2b), + MSM_PIN_FUNCTION(gp_mn), + MSM_PIN_FUNCTION(gp_pdm_0a), + MSM_PIN_FUNCTION(gp_pdm_0b), + MSM_PIN_FUNCTION(gp_pdm_1a), + MSM_PIN_FUNCTION(gp_pdm_1b), + MSM_PIN_FUNCTION(gp_pdm_2a), + MSM_PIN_FUNCTION(gp_pdm_2b), + MSM_PIN_FUNCTION(gpio), + MSM_PIN_FUNCTION(gsbi1), + MSM_PIN_FUNCTION(gsbi1_spi_cs1_n), + MSM_PIN_FUNCTION(gsbi1_spi_cs2a_n), + MSM_PIN_FUNCTION(gsbi1_spi_cs2b_n), + MSM_PIN_FUNCTION(gsbi1_spi_cs3_n), + MSM_PIN_FUNCTION(gsbi2), + MSM_PIN_FUNCTION(gsbi2_spi_cs1_n), + MSM_PIN_FUNCTION(gsbi2_spi_cs2_n), + MSM_PIN_FUNCTION(gsbi2_spi_cs3_n), + MSM_PIN_FUNCTION(gsbi3), + MSM_PIN_FUNCTION(gsbi4), + MSM_PIN_FUNCTION(gsbi4_3d_cam_i2c_l), + MSM_PIN_FUNCTION(gsbi4_3d_cam_i2c_r), + MSM_PIN_FUNCTION(gsbi5), + MSM_PIN_FUNCTION(gsbi5_3d_cam_i2c_l), + MSM_PIN_FUNCTION(gsbi5_3d_cam_i2c_r), + MSM_PIN_FUNCTION(gsbi6), + MSM_PIN_FUNCTION(gsbi7), + MSM_PIN_FUNCTION(gsbi8), + MSM_PIN_FUNCTION(gsbi9), + MSM_PIN_FUNCTION(gsbi10), + MSM_PIN_FUNCTION(gsbi11), + MSM_PIN_FUNCTION(gsbi11_spi_cs1a_n), + MSM_PIN_FUNCTION(gsbi11_spi_cs1b_n), + MSM_PIN_FUNCTION(gsbi11_spi_cs2a_n), + MSM_PIN_FUNCTION(gsbi11_spi_cs2b_n), + MSM_PIN_FUNCTION(gsbi11_spi_cs3_n), + MSM_PIN_FUNCTION(gsbi12), + MSM_PIN_FUNCTION(hdmi_cec), + MSM_PIN_FUNCTION(hdmi_ddc_clock), + MSM_PIN_FUNCTION(hdmi_ddc_data), + MSM_PIN_FUNCTION(hdmi_hot_plug_detect), + MSM_PIN_FUNCTION(hsic), + MSM_PIN_FUNCTION(mdp_vsync), + MSM_PIN_FUNCTION(mi2s), + MSM_PIN_FUNCTION(mic_i2s), + MSM_PIN_FUNCTION(pmb_clk), + MSM_PIN_FUNCTION(pmb_ext_ctrl), + MSM_PIN_FUNCTION(ps_hold), + MSM_PIN_FUNCTION(rpm_wdog), + MSM_PIN_FUNCTION(sdc2), + MSM_PIN_FUNCTION(sdc4), + MSM_PIN_FUNCTION(sdc5), + MSM_PIN_FUNCTION(slimbus1), + MSM_PIN_FUNCTION(slimbus2), + MSM_PIN_FUNCTION(spkr_i2s), + MSM_PIN_FUNCTION(ssbi1), + MSM_PIN_FUNCTION(ssbi2), + MSM_PIN_FUNCTION(ssbi_ext_gps), + MSM_PIN_FUNCTION(ssbi_pmic2), + MSM_PIN_FUNCTION(ssbi_qpa1), + MSM_PIN_FUNCTION(ssbi_ts), + MSM_PIN_FUNCTION(tsif1), + MSM_PIN_FUNCTION(tsif2), + MSM_PIN_FUNCTION(ts_eoc), + MSM_PIN_FUNCTION(usb_fs1), + MSM_PIN_FUNCTION(usb_fs1_oe), + MSM_PIN_FUNCTION(usb_fs1_oe_n), + MSM_PIN_FUNCTION(usb_fs2), + MSM_PIN_FUNCTION(usb_fs2_oe), + MSM_PIN_FUNCTION(usb_fs2_oe_n), + MSM_PIN_FUNCTION(vfe_camif_timer1_a), + MSM_PIN_FUNCTION(vfe_camif_timer1_b), + MSM_PIN_FUNCTION(vfe_camif_timer2), + MSM_PIN_FUNCTION(vfe_camif_timer3_a), + MSM_PIN_FUNCTION(vfe_camif_timer3_b), + MSM_PIN_FUNCTION(vfe_camif_timer4_a), + MSM_PIN_FUNCTION(vfe_camif_timer4_b), + MSM_PIN_FUNCTION(vfe_camif_timer4_c), + MSM_PIN_FUNCTION(vfe_camif_timer5_a), + MSM_PIN_FUNCTION(vfe_camif_timer5_b), + MSM_PIN_FUNCTION(vfe_camif_timer6_a), + MSM_PIN_FUNCTION(vfe_camif_timer6_b), + MSM_PIN_FUNCTION(vfe_camif_timer6_c), + MSM_PIN_FUNCTION(vfe_camif_timer7_a), + MSM_PIN_FUNCTION(vfe_camif_timer7_b), + MSM_PIN_FUNCTION(vfe_camif_timer7_c), + MSM_PIN_FUNCTION(wlan), +}; + +static const struct msm_pingroup msm8960_groups[] = { + PINGROUP(0, mdp_vsync, vfe_camif_timer6_b, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(1, mdp_vsync, vfe_camif_timer7_b, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(2, vfe_camif_timer1_a, gp_mn, NA, cam_mclk2, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(3, vfe_camif_timer2, gp_clk_0a, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(4, vfe_camif_timer3_a, cam_mclk1, gp_clk_1a, pmb_ext_ctrl, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(5, cam_mclk0, pmb_ext_ctrl, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(6, gsbi1, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(7, gsbi1, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(8, gsbi1, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(9, gsbi1, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(10, gsbi2, ssbi_ts, NA, vfe_camif_timer4_c, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(11, gsbi2, ts_eoc, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(12, gsbi2, rpm_wdog, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(13, gsbi2, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(14, gsbi3, gsbi1_spi_cs1_n, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(15, gsbi3, gsbi1_spi_cs2a_n, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(16, gsbi3, gsbi1_spi_cs3_n, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(17, gsbi3, gsbi1_spi_cs2b_n, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(18, gsbi4, gsbi11_spi_cs1b_n, NA, NA, gsbi4_3d_cam_i2c_l, vfe_camif_timer6_c, NA, NA, NA, NA, NA), + PINGROUP(19, gsbi4, gsbi11_spi_cs2b_n, NA, mdp_vsync, NA, gsbi4_3d_cam_i2c_l, vfe_camif_timer7_c, NA, NA, NA, NA), + PINGROUP(20, gsbi4, gsbi4_3d_cam_i2c_r, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(21, gsbi4, pmb_clk, gsbi4_3d_cam_i2c_r, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(22, gsbi5, ext_gps, NA, NA, NA, NA, NA, NA, NA, gsbi5_3d_cam_i2c_l, NA), + PINGROUP(23, gsbi5, ssbi_ext_gps, NA, NA, NA, NA, NA, NA, NA, gsbi5_3d_cam_i2c_l, NA), + PINGROUP(24, gsbi5, ext_gps, NA, NA, NA, NA, NA, NA, NA, gsbi5_3d_cam_i2c_r, NA), + PINGROUP(25, gsbi5, ext_gps, NA, NA, NA, NA, NA, NA, NA, gsbi5_3d_cam_i2c_r, NA), + PINGROUP(26, fm, gsbi6, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(27, fm, gsbi6, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(28, bt, gsbi6, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(29, bt, gsbi6, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(30, gsbi7, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(31, gsbi7, usb_fs1_oe, usb_fs1_oe_n, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(32, gsbi7, usb_fs1, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(33, gsbi7, usb_fs1, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(34, gsbi8, usb_fs2, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(35, gsbi8, usb_fs2, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(36, gsbi8, usb_fs2_oe, usb_fs2_oe_n, gsbi11_spi_cs1a_n, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(37, gsbi8, gps_pps_out, gps_pps_in, gsbi11_spi_cs2a_n, gp_clk_2b, NA, NA, NA, NA, NA, NA), + PINGROUP(38, gsbi11, NA, NA, NA, NA, NA, NA, NA, NA, vfe_camif_timer1_b, NA), + PINGROUP(39, gsbi11, gp_pdm_0b, NA, NA, NA, NA, NA, NA, NA, NA, vfe_camif_timer5_b), + PINGROUP(40, gsbi11, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(41, gsbi11, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(42, gsbi12, slimbus2, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(43, gsbi12, slimbus2, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(44, gsbi12, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(45, gsbi12, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(46, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(47, mi2s, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(48, mi2s, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(49, mi2s, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(50, mi2s, slimbus1, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(51, mi2s, slimbus1, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(52, mi2s, gp_clk_2a, gsbi2_spi_cs1_n, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(53, mi2s, gp_pdm_2b, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(54, codec_mic_i2s, gp_clk_0b, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(55, codec_mic_i2s, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(56, codec_mic_i2s, gsbi2_spi_cs3_n, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(57, codec_mic_i2s, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(58, codec_mic_i2s, gp_pdm_0a, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(59, codec_spkr_i2s, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(60, slimbus1, codec_spkr_i2s, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(61, slimbus1, codec_spkr_i2s, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(62, codec_spkr_i2s, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(63, audio_pcm, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(64, audio_pcm, gp_pdm_1b, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(65, audio_pcm, vfe_camif_timer4_a, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(66, audio_pcm, vfe_camif_timer5_a, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(67, spkr_i2s, vfe_camif_timer7_a, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(68, spkr_i2s, gsbi2_spi_cs2_n, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(69, spkr_i2s, gp_pdm_2a, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(70, spkr_i2s, gp_clk_1b, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(71, mic_i2s, gsbi10, vfe_camif_timer6_a, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(72, mic_i2s, gsbi10, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(73, mic_i2s, gsbi10, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(74, mic_i2s, gsbi10, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(75, tsif1, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(76, tsif1, gsbi11_spi_cs3_n, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(77, tsif1, sdc5, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(78, tsif2, sdc5, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(79, tsif2, sdc5, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(80, tsif2, sdc5, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(81, tsif2, sdc5, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(82, tsif1, sdc5, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(83, bt, sdc4, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(84, wlan, sdc4, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(85, wlan, sdc4, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(86, wlan, sdc4, pmb_clk, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(87, wlan, sdc4, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(88, wlan, sdc4, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(89, sdc2, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(90, sdc2, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(91, sdc2, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(92, sdc2, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(93, sdc2, gsbi9, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(94, sdc2, gsbi9, gp_pdm_1a, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(95, sdc2, gsbi9, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(96, sdc2, gsbi9, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(97, sdc2, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(98, sdc2, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(99, hdmi_cec, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(100, hdmi_ddc_clock, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(101, hdmi_ddc_data, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(102, hdmi_hot_plug_detect, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(103, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(104, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(105, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(106, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(107, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(108, ps_hold, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(109, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(110, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(111, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(112, NA, pmb_clk, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(113, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(114, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(115, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(116, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(117, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(118, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(119, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(120, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(121, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(122, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(123, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(124, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(125, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(126, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(127, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(128, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(129, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(130, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(131, NA, ssbi_qpa1, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(132, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(133, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(134, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(135, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(136, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(137, gps_blanking, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(138, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(139, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(140, ssbi2, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(141, ssbi1, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(142, ssbi2, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(143, ssbi1, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(144, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(145, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(146, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(147, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(148, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(149, ssbi_pmic2, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(150, hsic, NA, vfe_camif_timer4_b, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(151, hsic, NA, vfe_camif_timer3_b, NA, NA, NA, NA, NA, NA, NA, NA), + + SDC_PINGROUP(sdc1_clk, 0x20a0, 13, 6), + SDC_PINGROUP(sdc1_cmd, 0x20a0, 11, 3), + SDC_PINGROUP(sdc1_data, 0x20a0, 9, 0), + + SDC_PINGROUP(sdc3_clk, 0x20a4, 14, 6), + SDC_PINGROUP(sdc3_cmd, 0x20a4, 11, 3), + SDC_PINGROUP(sdc3_data, 0x20a4, 9, 0), +}; + +#define NUM_GPIO_PINGROUPS 152 + +static const struct msm_pinctrl_soc_data msm8960_pinctrl = { + .pins = msm8960_pins, + .npins = ARRAY_SIZE(msm8960_pins), + .functions = msm8960_functions, + .nfunctions = ARRAY_SIZE(msm8960_functions), + .groups = msm8960_groups, + .ngroups = ARRAY_SIZE(msm8960_groups), + .ngpios = NUM_GPIO_PINGROUPS, +}; + +static int msm8960_pinctrl_probe(struct platform_device *pdev) +{ + return msm_pinctrl_probe(pdev, &msm8960_pinctrl); +} + +static const struct of_device_id msm8960_pinctrl_of_match[] = { + { .compatible = "qcom,msm8960-pinctrl", }, + { }, +}; + +static struct platform_driver msm8960_pinctrl_driver = { + .driver = { + .name = "msm8960-pinctrl", + .of_match_table = msm8960_pinctrl_of_match, + }, + .probe = msm8960_pinctrl_probe, + .remove = msm_pinctrl_remove, +}; + +static int __init msm8960_pinctrl_init(void) +{ + return platform_driver_register(&msm8960_pinctrl_driver); +} +arch_initcall(msm8960_pinctrl_init); + +static void __exit msm8960_pinctrl_exit(void) +{ + platform_driver_unregister(&msm8960_pinctrl_driver); +} +module_exit(msm8960_pinctrl_exit); + +MODULE_AUTHOR("Bjorn Andersson <bjorn.andersson@sonymobile.com>"); +MODULE_DESCRIPTION("Qualcomm MSM8960 pinctrl driver"); +MODULE_LICENSE("GPL v2"); +MODULE_DEVICE_TABLE(of, msm8960_pinctrl_of_match); diff --git a/drivers/pinctrl/qcom/pinctrl-msm8976.c b/drivers/pinctrl/qcom/pinctrl-msm8976.c new file mode 100644 index 0000000000..c30d80e4e9 --- /dev/null +++ b/drivers/pinctrl/qcom/pinctrl-msm8976.c @@ -0,0 +1,1116 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2015-2016, The Linux Foundation. All rights reserved. + * + * Copyright (c) 2016, AngeloGioacchino Del Regno <kholk11@gmail.com> + */ + +#include <linux/module.h> +#include <linux/of.h> +#include <linux/platform_device.h> + +#include "pinctrl-msm.h" + +#define REG_BASE 0x0 +#define REG_SIZE 0x1000 +#define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7, f8, f9) \ + { \ + .grp = PINCTRL_PINGROUP("gpio" #id, \ + gpio##id##_pins, \ + ARRAY_SIZE(gpio##id##_pins)), \ + .funcs = (int[]){ \ + msm_mux_gpio, /* gpio mode */ \ + msm_mux_##f1, \ + msm_mux_##f2, \ + msm_mux_##f3, \ + msm_mux_##f4, \ + msm_mux_##f5, \ + msm_mux_##f6, \ + msm_mux_##f7, \ + msm_mux_##f8, \ + msm_mux_##f9 \ + }, \ + .nfuncs = 10, \ + .ctl_reg = REG_BASE + REG_SIZE * id, \ + .io_reg = REG_BASE + 0x4 + REG_SIZE * id, \ + .intr_cfg_reg = REG_BASE + 0x8 + REG_SIZE * id, \ + .intr_status_reg = REG_BASE + 0xc + REG_SIZE * id, \ + .intr_target_reg = REG_BASE + 0x8 + REG_SIZE * id, \ + .mux_bit = 2, \ + .pull_bit = 0, \ + .drv_bit = 6, \ + .oe_bit = 9, \ + .in_bit = 0, \ + .out_bit = 1, \ + .intr_enable_bit = 0, \ + .intr_status_bit = 0, \ + .intr_target_bit = 5, \ + .intr_target_kpss_val = 4, \ + .intr_raw_status_bit = 4, \ + .intr_polarity_bit = 1, \ + .intr_detection_bit = 2, \ + .intr_detection_width = 2, \ + } + +#define SDC_QDSD_PINGROUP(pg_name, ctl, pull, drv) \ + { \ + .grp = PINCTRL_PINGROUP(#pg_name, \ + pg_name##_pins, \ + ARRAY_SIZE(pg_name##_pins)), \ + .ctl_reg = ctl, \ + .io_reg = 0, \ + .intr_cfg_reg = 0, \ + .intr_status_reg = 0, \ + .intr_target_reg = 0, \ + .mux_bit = -1, \ + .pull_bit = pull, \ + .drv_bit = drv, \ + .oe_bit = -1, \ + .in_bit = -1, \ + .out_bit = -1, \ + .intr_enable_bit = -1, \ + .intr_status_bit = -1, \ + .intr_target_bit = -1, \ + .intr_raw_status_bit = -1, \ + .intr_polarity_bit = -1, \ + .intr_detection_bit = -1, \ + .intr_detection_width = -1, \ + } +static const struct pinctrl_pin_desc msm8976_pins[] = { + PINCTRL_PIN(0, "GPIO_0"), + PINCTRL_PIN(1, "GPIO_1"), + PINCTRL_PIN(2, "GPIO_2"), + PINCTRL_PIN(3, "GPIO_3"), + PINCTRL_PIN(4, "GPIO_4"), + PINCTRL_PIN(5, "GPIO_5"), + PINCTRL_PIN(6, "GPIO_6"), + PINCTRL_PIN(7, "GPIO_7"), + PINCTRL_PIN(8, "GPIO_8"), + PINCTRL_PIN(9, "GPIO_9"), + PINCTRL_PIN(10, "GPIO_10"), + PINCTRL_PIN(11, "GPIO_11"), + PINCTRL_PIN(12, "GPIO_12"), + PINCTRL_PIN(13, "GPIO_13"), + PINCTRL_PIN(14, "GPIO_14"), + PINCTRL_PIN(15, "GPIO_15"), + PINCTRL_PIN(16, "GPIO_16"), + PINCTRL_PIN(17, "GPIO_17"), + PINCTRL_PIN(18, "GPIO_18"), + PINCTRL_PIN(19, "GPIO_19"), + PINCTRL_PIN(20, "GPIO_20"), + PINCTRL_PIN(21, "GPIO_21"), + PINCTRL_PIN(22, "GPIO_22"), + PINCTRL_PIN(23, "GPIO_23"), + PINCTRL_PIN(24, "GPIO_24"), + PINCTRL_PIN(25, "GPIO_25"), + PINCTRL_PIN(26, "GPIO_26"), + PINCTRL_PIN(27, "GPIO_27"), + PINCTRL_PIN(28, "GPIO_28"), + PINCTRL_PIN(29, "GPIO_29"), + PINCTRL_PIN(30, "GPIO_30"), + PINCTRL_PIN(31, "GPIO_31"), + PINCTRL_PIN(32, "GPIO_32"), + PINCTRL_PIN(33, "GPIO_33"), + PINCTRL_PIN(34, "GPIO_34"), + PINCTRL_PIN(35, "GPIO_35"), + PINCTRL_PIN(36, "GPIO_36"), + PINCTRL_PIN(37, "GPIO_37"), + PINCTRL_PIN(38, "GPIO_38"), + PINCTRL_PIN(39, "GPIO_39"), + PINCTRL_PIN(40, "GPIO_40"), + PINCTRL_PIN(41, "GPIO_41"), + PINCTRL_PIN(42, "GPIO_42"), + PINCTRL_PIN(43, "GPIO_43"), + PINCTRL_PIN(44, "GPIO_44"), + PINCTRL_PIN(45, "GPIO_45"), + PINCTRL_PIN(46, "GPIO_46"), + PINCTRL_PIN(47, "GPIO_47"), + PINCTRL_PIN(48, "GPIO_48"), + PINCTRL_PIN(49, "GPIO_49"), + PINCTRL_PIN(50, "GPIO_50"), + PINCTRL_PIN(51, "GPIO_51"), + PINCTRL_PIN(52, "GPIO_52"), + PINCTRL_PIN(53, "GPIO_53"), + PINCTRL_PIN(54, "GPIO_54"), + PINCTRL_PIN(55, "GPIO_55"), + PINCTRL_PIN(56, "GPIO_56"), + PINCTRL_PIN(57, "GPIO_57"), + PINCTRL_PIN(58, "GPIO_58"), + PINCTRL_PIN(59, "GPIO_59"), + PINCTRL_PIN(60, "GPIO_60"), + PINCTRL_PIN(61, "GPIO_61"), + PINCTRL_PIN(62, "GPIO_62"), + PINCTRL_PIN(63, "GPIO_63"), + PINCTRL_PIN(64, "GPIO_64"), + PINCTRL_PIN(65, "GPIO_65"), + PINCTRL_PIN(66, "GPIO_66"), + PINCTRL_PIN(67, "GPIO_67"), + PINCTRL_PIN(68, "GPIO_68"), + PINCTRL_PIN(69, "GPIO_69"), + PINCTRL_PIN(70, "GPIO_70"), + PINCTRL_PIN(71, "GPIO_71"), + PINCTRL_PIN(72, "GPIO_72"), + PINCTRL_PIN(73, "GPIO_73"), + PINCTRL_PIN(74, "GPIO_74"), + PINCTRL_PIN(75, "GPIO_75"), + PINCTRL_PIN(76, "GPIO_76"), + PINCTRL_PIN(77, "GPIO_77"), + PINCTRL_PIN(78, "GPIO_78"), + PINCTRL_PIN(79, "GPIO_79"), + PINCTRL_PIN(80, "GPIO_80"), + PINCTRL_PIN(81, "GPIO_81"), + PINCTRL_PIN(82, "GPIO_82"), + PINCTRL_PIN(83, "GPIO_83"), + PINCTRL_PIN(84, "GPIO_84"), + PINCTRL_PIN(85, "GPIO_85"), + PINCTRL_PIN(86, "GPIO_86"), + PINCTRL_PIN(87, "GPIO_87"), + PINCTRL_PIN(88, "GPIO_88"), + PINCTRL_PIN(89, "GPIO_89"), + PINCTRL_PIN(90, "GPIO_90"), + PINCTRL_PIN(91, "GPIO_91"), + PINCTRL_PIN(92, "GPIO_92"), + PINCTRL_PIN(93, "GPIO_93"), + PINCTRL_PIN(94, "GPIO_94"), + PINCTRL_PIN(95, "GPIO_95"), + PINCTRL_PIN(96, "GPIO_96"), + PINCTRL_PIN(97, "GPIO_97"), + PINCTRL_PIN(98, "GPIO_98"), + PINCTRL_PIN(99, "GPIO_99"), + PINCTRL_PIN(100, "GPIO_100"), + PINCTRL_PIN(101, "GPIO_101"), + PINCTRL_PIN(102, "GPIO_102"), + PINCTRL_PIN(103, "GPIO_103"), + PINCTRL_PIN(104, "GPIO_104"), + PINCTRL_PIN(105, "GPIO_105"), + PINCTRL_PIN(106, "GPIO_106"), + PINCTRL_PIN(107, "GPIO_107"), + PINCTRL_PIN(108, "GPIO_108"), + PINCTRL_PIN(109, "GPIO_109"), + PINCTRL_PIN(110, "GPIO_110"), + PINCTRL_PIN(111, "GPIO_111"), + PINCTRL_PIN(112, "GPIO_112"), + PINCTRL_PIN(113, "GPIO_113"), + PINCTRL_PIN(114, "GPIO_114"), + PINCTRL_PIN(115, "GPIO_115"), + PINCTRL_PIN(116, "GPIO_116"), + PINCTRL_PIN(117, "GPIO_117"), + PINCTRL_PIN(118, "GPIO_118"), + PINCTRL_PIN(119, "GPIO_119"), + PINCTRL_PIN(120, "GPIO_120"), + PINCTRL_PIN(121, "GPIO_121"), + PINCTRL_PIN(122, "GPIO_122"), + PINCTRL_PIN(123, "GPIO_123"), + PINCTRL_PIN(124, "GPIO_124"), + PINCTRL_PIN(125, "GPIO_125"), + PINCTRL_PIN(126, "GPIO_126"), + PINCTRL_PIN(127, "GPIO_127"), + PINCTRL_PIN(128, "GPIO_128"), + PINCTRL_PIN(129, "GPIO_129"), + PINCTRL_PIN(130, "GPIO_130"), + PINCTRL_PIN(131, "GPIO_131"), + PINCTRL_PIN(132, "GPIO_132"), + PINCTRL_PIN(133, "GPIO_133"), + PINCTRL_PIN(134, "GPIO_134"), + PINCTRL_PIN(135, "GPIO_135"), + PINCTRL_PIN(136, "GPIO_136"), + PINCTRL_PIN(137, "GPIO_137"), + PINCTRL_PIN(138, "GPIO_138"), + PINCTRL_PIN(139, "GPIO_139"), + PINCTRL_PIN(140, "GPIO_140"), + PINCTRL_PIN(141, "GPIO_141"), + PINCTRL_PIN(142, "GPIO_142"), + PINCTRL_PIN(143, "GPIO_143"), + PINCTRL_PIN(144, "GPIO_144"), + PINCTRL_PIN(145, "SDC1_CLK"), + PINCTRL_PIN(146, "SDC1_CMD"), + PINCTRL_PIN(147, "SDC1_DATA"), + PINCTRL_PIN(148, "SDC1_RCLK"), + PINCTRL_PIN(149, "SDC2_CLK"), + PINCTRL_PIN(150, "SDC2_CMD"), + PINCTRL_PIN(151, "SDC2_DATA"), + PINCTRL_PIN(152, "QDSD_CLK"), + PINCTRL_PIN(153, "QDSD_CMD"), + PINCTRL_PIN(154, "QDSD_DATA0"), + PINCTRL_PIN(155, "QDSD_DATA1"), + PINCTRL_PIN(156, "QDSD_DATA2"), + PINCTRL_PIN(157, "QDSD_DATA3"), +}; + +#define DECLARE_MSM_GPIO_PINS(pin) \ + static const unsigned int gpio##pin##_pins[] = { pin } +DECLARE_MSM_GPIO_PINS(0); +DECLARE_MSM_GPIO_PINS(1); +DECLARE_MSM_GPIO_PINS(2); +DECLARE_MSM_GPIO_PINS(3); +DECLARE_MSM_GPIO_PINS(4); +DECLARE_MSM_GPIO_PINS(5); +DECLARE_MSM_GPIO_PINS(6); +DECLARE_MSM_GPIO_PINS(7); +DECLARE_MSM_GPIO_PINS(8); +DECLARE_MSM_GPIO_PINS(9); +DECLARE_MSM_GPIO_PINS(10); +DECLARE_MSM_GPIO_PINS(11); +DECLARE_MSM_GPIO_PINS(12); +DECLARE_MSM_GPIO_PINS(13); +DECLARE_MSM_GPIO_PINS(14); +DECLARE_MSM_GPIO_PINS(15); +DECLARE_MSM_GPIO_PINS(16); +DECLARE_MSM_GPIO_PINS(17); +DECLARE_MSM_GPIO_PINS(18); +DECLARE_MSM_GPIO_PINS(19); +DECLARE_MSM_GPIO_PINS(20); +DECLARE_MSM_GPIO_PINS(21); +DECLARE_MSM_GPIO_PINS(22); +DECLARE_MSM_GPIO_PINS(23); +DECLARE_MSM_GPIO_PINS(24); +DECLARE_MSM_GPIO_PINS(25); +DECLARE_MSM_GPIO_PINS(26); +DECLARE_MSM_GPIO_PINS(27); +DECLARE_MSM_GPIO_PINS(28); +DECLARE_MSM_GPIO_PINS(29); +DECLARE_MSM_GPIO_PINS(30); +DECLARE_MSM_GPIO_PINS(31); +DECLARE_MSM_GPIO_PINS(32); +DECLARE_MSM_GPIO_PINS(33); +DECLARE_MSM_GPIO_PINS(34); +DECLARE_MSM_GPIO_PINS(35); +DECLARE_MSM_GPIO_PINS(36); +DECLARE_MSM_GPIO_PINS(37); +DECLARE_MSM_GPIO_PINS(38); +DECLARE_MSM_GPIO_PINS(39); +DECLARE_MSM_GPIO_PINS(40); +DECLARE_MSM_GPIO_PINS(41); +DECLARE_MSM_GPIO_PINS(42); +DECLARE_MSM_GPIO_PINS(43); +DECLARE_MSM_GPIO_PINS(44); +DECLARE_MSM_GPIO_PINS(45); +DECLARE_MSM_GPIO_PINS(46); +DECLARE_MSM_GPIO_PINS(47); +DECLARE_MSM_GPIO_PINS(48); +DECLARE_MSM_GPIO_PINS(49); +DECLARE_MSM_GPIO_PINS(50); +DECLARE_MSM_GPIO_PINS(51); +DECLARE_MSM_GPIO_PINS(52); +DECLARE_MSM_GPIO_PINS(53); +DECLARE_MSM_GPIO_PINS(54); +DECLARE_MSM_GPIO_PINS(55); +DECLARE_MSM_GPIO_PINS(56); +DECLARE_MSM_GPIO_PINS(57); +DECLARE_MSM_GPIO_PINS(58); +DECLARE_MSM_GPIO_PINS(59); +DECLARE_MSM_GPIO_PINS(60); +DECLARE_MSM_GPIO_PINS(61); +DECLARE_MSM_GPIO_PINS(62); +DECLARE_MSM_GPIO_PINS(63); +DECLARE_MSM_GPIO_PINS(64); +DECLARE_MSM_GPIO_PINS(65); +DECLARE_MSM_GPIO_PINS(66); +DECLARE_MSM_GPIO_PINS(67); +DECLARE_MSM_GPIO_PINS(68); +DECLARE_MSM_GPIO_PINS(69); +DECLARE_MSM_GPIO_PINS(70); +DECLARE_MSM_GPIO_PINS(71); +DECLARE_MSM_GPIO_PINS(72); +DECLARE_MSM_GPIO_PINS(73); +DECLARE_MSM_GPIO_PINS(74); +DECLARE_MSM_GPIO_PINS(75); +DECLARE_MSM_GPIO_PINS(76); +DECLARE_MSM_GPIO_PINS(77); +DECLARE_MSM_GPIO_PINS(78); +DECLARE_MSM_GPIO_PINS(79); +DECLARE_MSM_GPIO_PINS(80); +DECLARE_MSM_GPIO_PINS(81); +DECLARE_MSM_GPIO_PINS(82); +DECLARE_MSM_GPIO_PINS(83); +DECLARE_MSM_GPIO_PINS(84); +DECLARE_MSM_GPIO_PINS(85); +DECLARE_MSM_GPIO_PINS(86); +DECLARE_MSM_GPIO_PINS(87); +DECLARE_MSM_GPIO_PINS(88); +DECLARE_MSM_GPIO_PINS(89); +DECLARE_MSM_GPIO_PINS(90); +DECLARE_MSM_GPIO_PINS(91); +DECLARE_MSM_GPIO_PINS(92); +DECLARE_MSM_GPIO_PINS(93); +DECLARE_MSM_GPIO_PINS(94); +DECLARE_MSM_GPIO_PINS(95); +DECLARE_MSM_GPIO_PINS(96); +DECLARE_MSM_GPIO_PINS(97); +DECLARE_MSM_GPIO_PINS(98); +DECLARE_MSM_GPIO_PINS(99); +DECLARE_MSM_GPIO_PINS(100); +DECLARE_MSM_GPIO_PINS(101); +DECLARE_MSM_GPIO_PINS(102); +DECLARE_MSM_GPIO_PINS(103); +DECLARE_MSM_GPIO_PINS(104); +DECLARE_MSM_GPIO_PINS(105); +DECLARE_MSM_GPIO_PINS(106); +DECLARE_MSM_GPIO_PINS(107); +DECLARE_MSM_GPIO_PINS(108); +DECLARE_MSM_GPIO_PINS(109); +DECLARE_MSM_GPIO_PINS(110); +DECLARE_MSM_GPIO_PINS(111); +DECLARE_MSM_GPIO_PINS(112); +DECLARE_MSM_GPIO_PINS(113); +DECLARE_MSM_GPIO_PINS(114); +DECLARE_MSM_GPIO_PINS(115); +DECLARE_MSM_GPIO_PINS(116); +DECLARE_MSM_GPIO_PINS(117); +DECLARE_MSM_GPIO_PINS(118); +DECLARE_MSM_GPIO_PINS(119); +DECLARE_MSM_GPIO_PINS(120); +DECLARE_MSM_GPIO_PINS(121); +DECLARE_MSM_GPIO_PINS(122); +DECLARE_MSM_GPIO_PINS(123); +DECLARE_MSM_GPIO_PINS(124); +DECLARE_MSM_GPIO_PINS(125); +DECLARE_MSM_GPIO_PINS(126); +DECLARE_MSM_GPIO_PINS(127); +DECLARE_MSM_GPIO_PINS(128); +DECLARE_MSM_GPIO_PINS(129); +DECLARE_MSM_GPIO_PINS(130); +DECLARE_MSM_GPIO_PINS(131); +DECLARE_MSM_GPIO_PINS(132); +DECLARE_MSM_GPIO_PINS(133); +DECLARE_MSM_GPIO_PINS(134); +DECLARE_MSM_GPIO_PINS(135); +DECLARE_MSM_GPIO_PINS(136); +DECLARE_MSM_GPIO_PINS(137); +DECLARE_MSM_GPIO_PINS(138); +DECLARE_MSM_GPIO_PINS(139); +DECLARE_MSM_GPIO_PINS(140); +DECLARE_MSM_GPIO_PINS(141); +DECLARE_MSM_GPIO_PINS(142); +DECLARE_MSM_GPIO_PINS(143); +DECLARE_MSM_GPIO_PINS(144); + +static const unsigned int sdc1_clk_pins[] = { 145 }; +static const unsigned int sdc1_cmd_pins[] = { 146 }; +static const unsigned int sdc1_data_pins[] = { 147 }; +static const unsigned int sdc1_rclk_pins[] = { 148 }; +static const unsigned int sdc2_clk_pins[] = { 149 }; +static const unsigned int sdc2_cmd_pins[] = { 150 }; +static const unsigned int sdc2_data_pins[] = { 151 }; +static const unsigned int qdsd_clk_pins[] = { 152 }; +static const unsigned int qdsd_cmd_pins[] = { 153 }; +static const unsigned int qdsd_data0_pins[] = { 154 }; +static const unsigned int qdsd_data1_pins[] = { 155 }; +static const unsigned int qdsd_data2_pins[] = { 156 }; +static const unsigned int qdsd_data3_pins[] = { 157 }; + +enum msm8976_functions { + msm_mux_gpio, + msm_mux_blsp_uart1, + msm_mux_blsp_spi1, + msm_mux_smb_int, + msm_mux_blsp_i2c1, + msm_mux_blsp_spi2, + msm_mux_blsp_uart2, + msm_mux_blsp_i2c2, + msm_mux_gcc_gp1_clk_b, + msm_mux_blsp_spi3, + msm_mux_qdss_tracedata_b, + msm_mux_blsp_i2c3, + msm_mux_gcc_gp2_clk_b, + msm_mux_gcc_gp3_clk_b, + msm_mux_blsp_spi4, + msm_mux_cap_int, + msm_mux_blsp_i2c4, + msm_mux_blsp_spi5, + msm_mux_blsp_uart5, + msm_mux_qdss_traceclk_a, + msm_mux_m_voc, + msm_mux_blsp_i2c5, + msm_mux_qdss_tracectl_a, + msm_mux_qdss_tracedata_a, + msm_mux_blsp_spi6, + msm_mux_blsp_uart6, + msm_mux_qdss_tracectl_b, + msm_mux_blsp_i2c6, + msm_mux_qdss_traceclk_b, + msm_mux_mdp_vsync, + msm_mux_pri_mi2s_mclk_a, + msm_mux_sec_mi2s_mclk_a, + msm_mux_cam_mclk, + msm_mux_cci0_i2c, + msm_mux_cci1_i2c, + msm_mux_blsp1_spi, + msm_mux_blsp3_spi, + msm_mux_gcc_gp1_clk_a, + msm_mux_gcc_gp2_clk_a, + msm_mux_gcc_gp3_clk_a, + msm_mux_uim_batt, + msm_mux_sd_write, + msm_mux_uim1_data, + msm_mux_uim1_clk, + msm_mux_uim1_reset, + msm_mux_uim1_present, + msm_mux_uim2_data, + msm_mux_uim2_clk, + msm_mux_uim2_reset, + msm_mux_uim2_present, + msm_mux_ts_xvdd, + msm_mux_mipi_dsi0, + msm_mux_us_euro, + msm_mux_ts_resout, + msm_mux_ts_sample, + msm_mux_sec_mi2s_mclk_b, + msm_mux_pri_mi2s, + msm_mux_codec_reset, + msm_mux_cdc_pdm0, + msm_mux_us_emitter, + msm_mux_pri_mi2s_mclk_b, + msm_mux_pri_mi2s_mclk_c, + msm_mux_lpass_slimbus, + msm_mux_lpass_slimbus0, + msm_mux_lpass_slimbus1, + msm_mux_codec_int1, + msm_mux_codec_int2, + msm_mux_wcss_bt, + msm_mux_sdc3, + msm_mux_wcss_wlan2, + msm_mux_wcss_wlan1, + msm_mux_wcss_wlan0, + msm_mux_wcss_wlan, + msm_mux_wcss_fm, + msm_mux_key_volp, + msm_mux_key_snapshot, + msm_mux_key_focus, + msm_mux_key_home, + msm_mux_pwr_down, + msm_mux_dmic0_clk, + msm_mux_hdmi_int, + msm_mux_dmic0_data, + msm_mux_wsa_vi, + msm_mux_wsa_en, + msm_mux_blsp_spi8, + msm_mux_wsa_irq, + msm_mux_blsp_i2c8, + msm_mux_pa_indicator, + msm_mux_modem_tsync, + msm_mux_ssbi_wtr1, + msm_mux_gsm1_tx, + msm_mux_gsm0_tx, + msm_mux_sdcard_det, + msm_mux_sec_mi2s, + msm_mux_ss_switch, + msm_mux_NA, +}; + +static const char * const gpio_groups[] = { + "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7", + "gpio8", "gpio9", "gpio10", "gpio11", "gpio12", "gpio13", "gpio14", + "gpio15", "gpio16", "gpio17", "gpio18", "gpio19", "gpio20", "gpio21", + "gpio22", "gpio23", "gpio24", "gpio25", "gpio26", "gpio27", "gpio28", + "gpio29", "gpio30", "gpio31", "gpio32", "gpio33", "gpio34", "gpio35", + "gpio36", "gpio37", "gpio38", "gpio39", "gpio40", "gpio41", "gpio42", + "gpio43", "gpio44", "gpio45", "gpio46", "gpio47", "gpio48", "gpio49", + "gpio50", "gpio51", "gpio52", "gpio53", "gpio54", "gpio55", "gpio56", + "gpio57", "gpio58", "gpio59", "gpio60", "gpio61", "gpio62", "gpio63", + "gpio64", "gpio65", "gpio66", "gpio67", "gpio68", "gpio69", "gpio70", + "gpio71", "gpio72", "gpio73", "gpio74", "gpio75", "gpio76", "gpio77", + "gpio78", "gpio79", "gpio80", "gpio81", "gpio82", "gpio83", "gpio84", + "gpio85", "gpio86", "gpio87", "gpio88", "gpio89", "gpio90", "gpio91", + "gpio92", "gpio93", "gpio94", "gpio95", "gpio96", "gpio97", "gpio98", + "gpio99", "gpio100", "gpio101", "gpio102", "gpio103", "gpio104", + "gpio105", "gpio106", "gpio107", "gpio108", "gpio109", "gpio110", + "gpio111", "gpio112", "gpio113", "gpio114", "gpio115", "gpio116", + "gpio117", "gpio118", "gpio119", "gpio120", "gpio121", "gpio122", + "gpio123", "gpio124", "gpio125", "gpio126", "gpio127", "gpio128", + "gpio129", "gpio130", "gpio131", "gpio132", "gpio133", "gpio134", + "gpio135", "gpio136", "gpio137", "gpio138", "gpio139", "gpio140", + "gpio141", "gpio142", "gpio143", "gpio144", +}; +static const char * const blsp_uart1_groups[] = { + "gpio0", "gpio1", "gpio2", "gpio3", +}; +static const char * const blsp_spi1_groups[] = { + "gpio0", "gpio1", "gpio2", "gpio3", +}; +static const char * const smb_int_groups[] = { + "gpio1", +}; +static const char * const blsp_i2c1_groups[] = { + "gpio2", "gpio3", +}; +static const char * const blsp_spi2_groups[] = { + "gpio4", "gpio5", "gpio6", "gpio7", +}; +static const char * const blsp_uart2_groups[] = { + "gpio4", "gpio5", "gpio6", "gpio7", +}; +static const char * const blsp_i2c2_groups[] = { + "gpio6", "gpio7", +}; +static const char * const gcc_gp1_clk_b_groups[] = { + "gpio105", +}; +static const char * const blsp_spi3_groups[] = { + "gpio8", "gpio9", "gpio10", "gpio11", +}; +static const char * const qdss_tracedata_b_groups[] = { + "gpio26", "gpio27", "gpio28", "gpio29", "gpio30", + "gpio31", "gpio33", "gpio34", "gpio35", "gpio36", "gpio37", "gpio38", + "gpio116", "gpio126", "gpio128", "gpio129", +}; +static const char * const blsp_i2c3_groups[] = { + "gpio10", "gpio11", +}; +static const char * const gcc_gp2_clk_b_groups[] = { + "gpio12", +}; +static const char * const gcc_gp3_clk_b_groups[] = { + "gpio13", +}; +static const char * const blsp_spi4_groups[] = { + "gpio12", "gpio13", "gpio14", "gpio15", +}; +static const char * const cap_int_groups[] = { + "gpio13", +}; +static const char * const blsp_i2c4_groups[] = { + "gpio14", "gpio15", +}; +static const char * const blsp_spi5_groups[] = { + "gpio134", "gpio135", "gpio136", "gpio137", +}; +static const char * const blsp_uart5_groups[] = { + "gpio134", "gpio135", "gpio136", "gpio137", +}; +static const char * const qdss_traceclk_a_groups[] = { + "gpio46", +}; +static const char * const m_voc_groups[] = { + "gpio123", "gpio124", +}; +static const char * const blsp_i2c5_groups[] = { + "gpio136", "gpio137", +}; +static const char * const qdss_tracectl_a_groups[] = { + "gpio45", +}; +static const char * const qdss_tracedata_a_groups[] = { + "gpio8", "gpio9", "gpio10", "gpio39", "gpio40", "gpio41", "gpio42", + "gpio43", "gpio44", "gpio47", "gpio48", "gpio62", "gpio69", "gpio120", + "gpio121", "gpio130", "gpio131", +}; +static const char * const blsp_spi6_groups[] = { + "gpio20", "gpio21", "gpio22", "gpio23", +}; +static const char * const blsp_uart6_groups[] = { + "gpio20", "gpio21", "gpio22", "gpio23", +}; +static const char * const qdss_tracectl_b_groups[] = { + "gpio5", +}; +static const char * const blsp_i2c6_groups[] = { + "gpio22", "gpio23", +}; +static const char * const qdss_traceclk_b_groups[] = { + "gpio5", +}; +static const char * const mdp_vsync_groups[] = { + "gpio24", "gpio25", +}; +static const char * const pri_mi2s_mclk_a_groups[] = { + "gpio126", +}; +static const char * const sec_mi2s_mclk_a_groups[] = { + "gpio62", +}; +static const char * const cam_mclk_groups[] = { + "gpio26", "gpio27", "gpio28", +}; +static const char * const cci0_i2c_groups[] = { + "gpio30", "gpio29", +}; +static const char * const cci1_i2c_groups[] = { + "gpio104", "gpio103", +}; +static const char * const blsp1_spi_groups[] = { + "gpio101", +}; +static const char * const blsp3_spi_groups[] = { + "gpio106", "gpio107", +}; +static const char * const gcc_gp1_clk_a_groups[] = { + "gpio49", +}; +static const char * const gcc_gp2_clk_a_groups[] = { + "gpio50", +}; +static const char * const gcc_gp3_clk_a_groups[] = { + "gpio51", +}; +static const char * const uim_batt_groups[] = { + "gpio61", +}; +static const char * const sd_write_groups[] = { + "gpio50", +}; +static const char * const uim2_data_groups[] = { + "gpio51", +}; +static const char * const uim2_clk_groups[] = { + "gpio52", +}; +static const char * const uim2_reset_groups[] = { + "gpio53", +}; +static const char * const uim2_present_groups[] = { + "gpio54", +}; +static const char * const uim1_data_groups[] = { + "gpio55", +}; +static const char * const uim1_clk_groups[] = { + "gpio56", +}; +static const char * const uim1_reset_groups[] = { + "gpio57", +}; +static const char * const uim1_present_groups[] = { + "gpio58", +}; +static const char * const ts_xvdd_groups[] = { + "gpio60", +}; +static const char * const mipi_dsi0_groups[] = { + "gpio61", +}; +static const char * const us_euro_groups[] = { + "gpio63", +}; +static const char * const ts_resout_groups[] = { + "gpio64", +}; +static const char * const ts_sample_groups[] = { + "gpio65", +}; +static const char * const sec_mi2s_mclk_b_groups[] = { + "gpio66", +}; +static const char * const pri_mi2s_groups[] = { + "gpio122", "gpio123", "gpio124", "gpio125", "gpio127", +}; +static const char * const codec_reset_groups[] = { + "gpio67", +}; +static const char * const cdc_pdm0_groups[] = { + "gpio116", "gpio117", "gpio118", "gpio119", "gpio120", "gpio121", +}; +static const char * const us_emitter_groups[] = { + "gpio68", +}; +static const char * const pri_mi2s_mclk_b_groups[] = { + "gpio62", +}; +static const char * const pri_mi2s_mclk_c_groups[] = { + "gpio116", +}; +static const char * const lpass_slimbus_groups[] = { + "gpio117", +}; +static const char * const lpass_slimbus0_groups[] = { + "gpio118", +}; +static const char * const lpass_slimbus1_groups[] = { + "gpio119", +}; +static const char * const codec_int1_groups[] = { + "gpio73", +}; +static const char * const codec_int2_groups[] = { + "gpio74", +}; +static const char * const wcss_bt_groups[] = { + "gpio39", "gpio47", "gpio48", +}; +static const char * const sdc3_groups[] = { + "gpio39", "gpio40", "gpio41", + "gpio42", "gpio43", "gpio44", +}; +static const char * const wcss_wlan2_groups[] = { + "gpio40", +}; +static const char * const wcss_wlan1_groups[] = { + "gpio41", +}; +static const char * const wcss_wlan0_groups[] = { + "gpio42", +}; +static const char * const wcss_wlan_groups[] = { + "gpio43", "gpio44", +}; +static const char * const wcss_fm_groups[] = { + "gpio45", "gpio46", +}; +static const char * const key_volp_groups[] = { + "gpio85", +}; +static const char * const key_snapshot_groups[] = { + "gpio86", +}; +static const char * const key_focus_groups[] = { + "gpio87", +}; +static const char * const key_home_groups[] = { + "gpio88", +}; +static const char * const pwr_down_groups[] = { + "gpio89", +}; +static const char * const dmic0_clk_groups[] = { + "gpio66", +}; +static const char * const hdmi_int_groups[] = { + "gpio90", +}; +static const char * const dmic0_data_groups[] = { + "gpio67", +}; +static const char * const wsa_vi_groups[] = { + "gpio108", "gpio109", +}; +static const char * const wsa_en_groups[] = { + "gpio96", +}; +static const char * const blsp_spi8_groups[] = { + "gpio16", "gpio17", "gpio18", "gpio19", +}; +static const char * const wsa_irq_groups[] = { + "gpio97", +}; +static const char * const blsp_i2c8_groups[] = { + "gpio18", "gpio19", +}; +static const char * const pa_indicator_groups[] = { + "gpio92", +}; +static const char * const modem_tsync_groups[] = { + "gpio93", +}; +static const char * const ssbi_wtr1_groups[] = { + "gpio79", "gpio94", +}; +static const char * const gsm1_tx_groups[] = { + "gpio95", +}; +static const char * const gsm0_tx_groups[] = { + "gpio99", +}; +static const char * const sdcard_det_groups[] = { + "gpio133", +}; +static const char * const sec_mi2s_groups[] = { + "gpio102", "gpio105", "gpio134", "gpio135", +}; + +static const char * const ss_switch_groups[] = { + "gpio139", +}; + +static const struct pinfunction msm8976_functions[] = { + MSM_PIN_FUNCTION(gpio), + MSM_PIN_FUNCTION(blsp_spi1), + MSM_PIN_FUNCTION(smb_int), + MSM_PIN_FUNCTION(blsp_i2c1), + MSM_PIN_FUNCTION(blsp_spi2), + MSM_PIN_FUNCTION(blsp_uart1), + MSM_PIN_FUNCTION(blsp_uart2), + MSM_PIN_FUNCTION(blsp_i2c2), + MSM_PIN_FUNCTION(gcc_gp1_clk_b), + MSM_PIN_FUNCTION(blsp_spi3), + MSM_PIN_FUNCTION(qdss_tracedata_b), + MSM_PIN_FUNCTION(blsp_i2c3), + MSM_PIN_FUNCTION(gcc_gp2_clk_b), + MSM_PIN_FUNCTION(gcc_gp3_clk_b), + MSM_PIN_FUNCTION(blsp_spi4), + MSM_PIN_FUNCTION(cap_int), + MSM_PIN_FUNCTION(blsp_i2c4), + MSM_PIN_FUNCTION(blsp_spi5), + MSM_PIN_FUNCTION(blsp_uart5), + MSM_PIN_FUNCTION(qdss_traceclk_a), + MSM_PIN_FUNCTION(m_voc), + MSM_PIN_FUNCTION(blsp_i2c5), + MSM_PIN_FUNCTION(qdss_tracectl_a), + MSM_PIN_FUNCTION(qdss_tracedata_a), + MSM_PIN_FUNCTION(blsp_spi6), + MSM_PIN_FUNCTION(blsp_uart6), + MSM_PIN_FUNCTION(qdss_tracectl_b), + MSM_PIN_FUNCTION(blsp_i2c6), + MSM_PIN_FUNCTION(qdss_traceclk_b), + MSM_PIN_FUNCTION(mdp_vsync), + MSM_PIN_FUNCTION(pri_mi2s_mclk_a), + MSM_PIN_FUNCTION(sec_mi2s_mclk_a), + MSM_PIN_FUNCTION(cam_mclk), + MSM_PIN_FUNCTION(cci0_i2c), + MSM_PIN_FUNCTION(cci1_i2c), + MSM_PIN_FUNCTION(blsp1_spi), + MSM_PIN_FUNCTION(blsp3_spi), + MSM_PIN_FUNCTION(gcc_gp1_clk_a), + MSM_PIN_FUNCTION(gcc_gp2_clk_a), + MSM_PIN_FUNCTION(gcc_gp3_clk_a), + MSM_PIN_FUNCTION(uim_batt), + MSM_PIN_FUNCTION(sd_write), + MSM_PIN_FUNCTION(uim1_data), + MSM_PIN_FUNCTION(uim1_clk), + MSM_PIN_FUNCTION(uim1_reset), + MSM_PIN_FUNCTION(uim1_present), + MSM_PIN_FUNCTION(uim2_data), + MSM_PIN_FUNCTION(uim2_clk), + MSM_PIN_FUNCTION(uim2_reset), + MSM_PIN_FUNCTION(uim2_present), + MSM_PIN_FUNCTION(ts_xvdd), + MSM_PIN_FUNCTION(mipi_dsi0), + MSM_PIN_FUNCTION(us_euro), + MSM_PIN_FUNCTION(ts_resout), + MSM_PIN_FUNCTION(ts_sample), + MSM_PIN_FUNCTION(sec_mi2s_mclk_b), + MSM_PIN_FUNCTION(pri_mi2s), + MSM_PIN_FUNCTION(codec_reset), + MSM_PIN_FUNCTION(cdc_pdm0), + MSM_PIN_FUNCTION(us_emitter), + MSM_PIN_FUNCTION(pri_mi2s_mclk_b), + MSM_PIN_FUNCTION(pri_mi2s_mclk_c), + MSM_PIN_FUNCTION(lpass_slimbus), + MSM_PIN_FUNCTION(lpass_slimbus0), + MSM_PIN_FUNCTION(lpass_slimbus1), + MSM_PIN_FUNCTION(codec_int1), + MSM_PIN_FUNCTION(codec_int2), + MSM_PIN_FUNCTION(wcss_bt), + MSM_PIN_FUNCTION(sdc3), + MSM_PIN_FUNCTION(wcss_wlan2), + MSM_PIN_FUNCTION(wcss_wlan1), + MSM_PIN_FUNCTION(wcss_wlan0), + MSM_PIN_FUNCTION(wcss_wlan), + MSM_PIN_FUNCTION(wcss_fm), + MSM_PIN_FUNCTION(key_volp), + MSM_PIN_FUNCTION(key_snapshot), + MSM_PIN_FUNCTION(key_focus), + MSM_PIN_FUNCTION(key_home), + MSM_PIN_FUNCTION(pwr_down), + MSM_PIN_FUNCTION(dmic0_clk), + MSM_PIN_FUNCTION(hdmi_int), + MSM_PIN_FUNCTION(dmic0_data), + MSM_PIN_FUNCTION(wsa_vi), + MSM_PIN_FUNCTION(wsa_en), + MSM_PIN_FUNCTION(blsp_spi8), + MSM_PIN_FUNCTION(wsa_irq), + MSM_PIN_FUNCTION(blsp_i2c8), + MSM_PIN_FUNCTION(pa_indicator), + MSM_PIN_FUNCTION(modem_tsync), + MSM_PIN_FUNCTION(ssbi_wtr1), + MSM_PIN_FUNCTION(gsm1_tx), + MSM_PIN_FUNCTION(gsm0_tx), + MSM_PIN_FUNCTION(sdcard_det), + MSM_PIN_FUNCTION(sec_mi2s), + MSM_PIN_FUNCTION(ss_switch), +}; + +static const struct msm_pingroup msm8976_groups[] = { + PINGROUP(0, blsp_spi1, blsp_uart1, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(1, blsp_spi1, blsp_uart1, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(2, blsp_spi1, blsp_uart1, blsp_i2c1, NA, NA, NA, NA, NA, NA), + PINGROUP(3, blsp_spi1, blsp_uart1, blsp_i2c1, NA, NA, NA, NA, NA, NA), + PINGROUP(4, blsp_spi2, blsp_uart2, NA, NA, NA, qdss_tracectl_b, NA, NA, NA), + PINGROUP(5, blsp_spi2, blsp_uart2, NA, NA, NA, qdss_traceclk_b, NA, NA, NA), + PINGROUP(6, blsp_spi2, blsp_uart2, blsp_i2c2, NA, NA, NA, NA, NA, NA), + PINGROUP(7, blsp_spi2, blsp_uart2, blsp_i2c2, NA, NA, NA, NA, NA, NA), + PINGROUP(8, blsp_spi3, NA, NA, NA, NA, qdss_tracedata_a, NA, NA, NA), + PINGROUP(9, blsp_spi3, NA, NA, NA, qdss_tracedata_a, NA, NA, NA, NA), + PINGROUP(10, blsp_spi3, NA, blsp_i2c3, NA, NA, qdss_tracedata_a, NA, NA, NA), + PINGROUP(11, blsp_spi3, NA, blsp_i2c3, NA, NA, NA, NA, NA, NA), + PINGROUP(12, blsp_spi4, NA, gcc_gp2_clk_b, NA, NA, NA, NA, NA, NA), + PINGROUP(13, blsp_spi4, NA, gcc_gp3_clk_b, NA, NA, NA, NA, NA, NA), + PINGROUP(14, blsp_spi4, NA, blsp_i2c4, NA, NA, NA, NA, NA, NA), + PINGROUP(15, blsp_spi4, NA, blsp_i2c4, NA, NA, NA, NA, NA, NA), + PINGROUP(16, blsp_spi8, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(17, blsp_spi8, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(18, blsp_spi8, NA, blsp_i2c8, NA, NA, NA, NA, NA, NA), + PINGROUP(19, blsp_spi8, NA, blsp_i2c8, NA, NA, NA, NA, NA, NA), + PINGROUP(20, blsp_spi6, blsp_uart6, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(21, blsp_spi6, blsp_uart6, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(22, blsp_spi6, blsp_uart6, blsp_i2c6, NA, NA, NA, NA, NA, NA), + PINGROUP(23, blsp_spi6, blsp_uart6, blsp_i2c6, NA, NA, NA, NA, NA, NA), + PINGROUP(24, mdp_vsync, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(25, mdp_vsync, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(26, cam_mclk, NA, NA, NA, NA, qdss_tracedata_b, NA, NA, NA), + PINGROUP(27, cam_mclk, NA, NA, NA, NA, NA, qdss_tracedata_b, NA, NA), + PINGROUP(28, cam_mclk, NA, NA, NA, NA, qdss_tracedata_b, NA, NA, NA), + PINGROUP(29, cci0_i2c, NA, NA, NA, NA, qdss_tracedata_b, NA, NA, NA), + PINGROUP(30, cci0_i2c, NA, NA, NA, NA, NA, qdss_tracedata_b, NA, NA), + PINGROUP(31, NA, NA, NA, NA, NA, NA, NA, qdss_tracedata_b, NA), + PINGROUP(32, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(33, NA, NA, NA, NA, NA, NA, qdss_tracedata_b, NA, NA), + PINGROUP(34, NA, NA, NA, NA, NA, NA, NA, NA, qdss_tracedata_b), + PINGROUP(35, NA, NA, NA, NA, NA, NA, NA, NA, qdss_tracedata_b), + PINGROUP(36, NA, NA, NA, NA, NA, NA, qdss_tracedata_b, NA, NA), + PINGROUP(37, NA, NA, NA, qdss_tracedata_b, NA, NA, NA, NA, NA), + PINGROUP(38, NA, NA, NA, NA, NA, NA, NA, qdss_tracedata_b, NA), + PINGROUP(39, wcss_bt, sdc3, NA, qdss_tracedata_a, NA, NA, NA, NA, NA), + PINGROUP(40, wcss_wlan2, sdc3, NA, qdss_tracedata_a, NA, NA, NA, NA, NA), + PINGROUP(41, wcss_wlan1, sdc3, NA, qdss_tracedata_a, NA, NA, NA, NA, NA), + PINGROUP(42, wcss_wlan0, sdc3, NA, qdss_tracedata_a, NA, NA, NA, NA, NA), + PINGROUP(43, wcss_wlan, sdc3, NA, NA, qdss_tracedata_a, NA, NA, NA, NA), + PINGROUP(44, wcss_wlan, sdc3, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(45, wcss_fm, NA, qdss_tracectl_a, NA, NA, NA, NA, NA, NA), + PINGROUP(46, wcss_fm, NA, NA, qdss_traceclk_a, NA, NA, NA, NA, NA), + PINGROUP(47, wcss_bt, NA, qdss_tracedata_a, NA, NA, NA, NA, NA, NA), + PINGROUP(48, wcss_bt, NA, qdss_tracedata_a, NA, NA, NA, NA, NA, NA), + PINGROUP(49, NA, NA, gcc_gp1_clk_a, NA, NA, NA, NA, NA, NA), + PINGROUP(50, NA, sd_write, gcc_gp2_clk_a, NA, NA, NA, NA, NA, NA), + PINGROUP(51, uim2_data, gcc_gp3_clk_a, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(52, uim2_clk, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(53, uim2_reset, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(54, uim2_present, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(55, uim1_data, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(56, uim1_clk, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(57, uim1_reset, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(58, uim1_present, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(59, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(60, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(61, uim_batt, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(62, sec_mi2s_mclk_a, pri_mi2s_mclk_b, qdss_tracedata_a, NA, NA, NA, NA, NA, NA), + PINGROUP(63, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(64, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(65, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(66, dmic0_clk, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(67, dmic0_data, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(68, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(69, qdss_tracedata_a, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(70, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(71, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(72, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(73, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(74, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(75, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(76, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(77, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(78, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(79, NA, ssbi_wtr1, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(80, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(81, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(82, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(83, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(84, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(85, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(86, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(87, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(88, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(89, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(90, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(91, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(92, NA, NA, pa_indicator, NA, NA, NA, NA, NA, NA), + PINGROUP(93, NA, modem_tsync, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(94, NA, ssbi_wtr1, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(95, NA, gsm1_tx, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(96, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(97, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(98, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(99, gsm0_tx, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(100, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(101, blsp1_spi, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(102, sec_mi2s, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(103, cci1_i2c, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(104, cci1_i2c, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(105, sec_mi2s, gcc_gp1_clk_b, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(106, blsp3_spi, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(107, blsp3_spi, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(108, wsa_vi, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(109, wsa_vi, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(110, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(111, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(112, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(113, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(114, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(115, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(116, pri_mi2s_mclk_c, cdc_pdm0, NA, NA, NA, qdss_tracedata_b, NA, NA, NA), + PINGROUP(117, lpass_slimbus, cdc_pdm0, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(118, lpass_slimbus0, cdc_pdm0, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(119, lpass_slimbus1, cdc_pdm0, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(120, cdc_pdm0, NA, NA, NA, NA, NA, NA, qdss_tracedata_a, NA), + PINGROUP(121, cdc_pdm0, NA, NA, NA, NA, NA, NA, qdss_tracedata_a, NA), + PINGROUP(122, pri_mi2s, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(123, pri_mi2s, m_voc, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(124, pri_mi2s, m_voc, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(125, pri_mi2s, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(126, pri_mi2s_mclk_a, sec_mi2s_mclk_b, NA, NA, NA, NA, NA, NA, qdss_tracedata_b), + PINGROUP(127, pri_mi2s, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(128, NA, NA, NA, NA, NA, NA, qdss_tracedata_b, NA, NA), + PINGROUP(129, qdss_tracedata_b, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(130, qdss_tracedata_a, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(131, qdss_tracedata_a, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(132, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(133, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(134, blsp_spi5, blsp_uart5, sec_mi2s, NA, NA, NA, NA, NA, NA), + PINGROUP(135, blsp_spi5, blsp_uart5, sec_mi2s, NA, NA, NA, NA, NA, NA), + PINGROUP(136, blsp_spi5, blsp_uart5, blsp_i2c5, NA, NA, NA, NA, NA, NA), + PINGROUP(137, blsp_spi5, blsp_uart5, blsp_i2c5, NA, NA, NA, NA, NA, NA), + PINGROUP(138, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(139, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(140, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(141, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(142, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(143, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(144, NA, NA, NA, NA, NA, NA, NA, NA, NA), + SDC_QDSD_PINGROUP(sdc1_clk, 0x10a000, 13, 6), + SDC_QDSD_PINGROUP(sdc1_cmd, 0x10a000, 11, 3), + SDC_QDSD_PINGROUP(sdc1_data, 0x10a000, 9, 0), + SDC_QDSD_PINGROUP(sdc1_rclk, 0x10a000, 15, 0), + SDC_QDSD_PINGROUP(sdc2_clk, 0x109000, 14, 6), + SDC_QDSD_PINGROUP(sdc2_cmd, 0x109000, 11, 3), + SDC_QDSD_PINGROUP(sdc2_data, 0x109000, 9, 0), + SDC_QDSD_PINGROUP(qdsd_clk, 0x19c000, 3, 0), + SDC_QDSD_PINGROUP(qdsd_cmd, 0x19c000, 8, 5), + SDC_QDSD_PINGROUP(qdsd_data0, 0x19c000, 13, 10), + SDC_QDSD_PINGROUP(qdsd_data1, 0x19c000, 18, 15), + SDC_QDSD_PINGROUP(qdsd_data2, 0x19c000, 23, 20), + SDC_QDSD_PINGROUP(qdsd_data3, 0x19c000, 28, 25), +}; + +static const struct msm_pinctrl_soc_data msm8976_pinctrl = { + .pins = msm8976_pins, + .npins = ARRAY_SIZE(msm8976_pins), + .functions = msm8976_functions, + .nfunctions = ARRAY_SIZE(msm8976_functions), + .groups = msm8976_groups, + .ngroups = ARRAY_SIZE(msm8976_groups), + .ngpios = 145, +}; + +static int msm8976_pinctrl_probe(struct platform_device *pdev) +{ + return msm_pinctrl_probe(pdev, &msm8976_pinctrl); +} + +static const struct of_device_id msm8976_pinctrl_of_match[] = { + { .compatible = "qcom,msm8976-pinctrl", }, + { }, +}; + +static struct platform_driver msm8976_pinctrl_driver = { + .driver = { + .name = "msm8976-pinctrl", + .of_match_table = msm8976_pinctrl_of_match, + }, + .probe = msm8976_pinctrl_probe, + .remove = msm_pinctrl_remove, +}; + +static int __init msm8976_pinctrl_init(void) +{ + return platform_driver_register(&msm8976_pinctrl_driver); +} +arch_initcall(msm8976_pinctrl_init); + +static void __exit msm8976_pinctrl_exit(void) +{ + platform_driver_unregister(&msm8976_pinctrl_driver); +} +module_exit(msm8976_pinctrl_exit); + +MODULE_DESCRIPTION("Qualcomm msm8976 pinctrl driver"); +MODULE_LICENSE("GPL v2"); +MODULE_DEVICE_TABLE(of, msm8976_pinctrl_of_match); diff --git a/drivers/pinctrl/qcom/pinctrl-msm8994.c b/drivers/pinctrl/qcom/pinctrl-msm8994.c new file mode 100644 index 0000000000..b1a6759ab4 --- /dev/null +++ b/drivers/pinctrl/qcom/pinctrl-msm8994.c @@ -0,0 +1,1363 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2016, The Linux Foundation. All rights reserved. + */ + +#include <linux/module.h> +#include <linux/of.h> +#include <linux/platform_device.h> + +#include "pinctrl-msm.h" + +#define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7, f8, f9, f10, f11) \ + { \ + .grp = PINCTRL_PINGROUP("gpio" #id, \ + gpio##id##_pins, \ + ARRAY_SIZE(gpio##id##_pins)), \ + .funcs = (int[]){ \ + msm_mux_gpio, \ + msm_mux_##f1, \ + msm_mux_##f2, \ + msm_mux_##f3, \ + msm_mux_##f4, \ + msm_mux_##f5, \ + msm_mux_##f6, \ + msm_mux_##f7, \ + msm_mux_##f8, \ + msm_mux_##f9, \ + msm_mux_##f10, \ + msm_mux_##f11 \ + }, \ + .nfuncs = 12, \ + .ctl_reg = 0x1000 + 0x10 * id, \ + .io_reg = 0x1004 + 0x10 * id, \ + .intr_cfg_reg = 0x1008 + 0x10 * id, \ + .intr_status_reg = 0x100c + 0x10 * id, \ + .intr_target_reg = 0x1008 + 0x10 * id, \ + .mux_bit = 2, \ + .pull_bit = 0, \ + .drv_bit = 6, \ + .oe_bit = 9, \ + .in_bit = 0, \ + .out_bit = 1, \ + .intr_enable_bit = 0, \ + .intr_status_bit = 0, \ + .intr_target_bit = 5, \ + .intr_target_kpss_val = 4, \ + .intr_raw_status_bit = 4, \ + .intr_polarity_bit = 1, \ + .intr_detection_bit = 2, \ + .intr_detection_width = 2, \ + } + +#define SDC_PINGROUP(pg_name, ctl, pull, drv) \ + { \ + .grp = PINCTRL_PINGROUP(#pg_name, \ + pg_name##_pins, \ + ARRAY_SIZE(pg_name##_pins)), \ + .ctl_reg = ctl, \ + .io_reg = 0, \ + .intr_cfg_reg = 0, \ + .intr_status_reg = 0, \ + .intr_target_reg = 0, \ + .mux_bit = -1, \ + .pull_bit = pull, \ + .drv_bit = drv, \ + .oe_bit = -1, \ + .in_bit = -1, \ + .out_bit = -1, \ + .intr_enable_bit = -1, \ + .intr_status_bit = -1, \ + .intr_target_bit = -1, \ + .intr_target_kpss_val = -1, \ + .intr_raw_status_bit = -1, \ + .intr_polarity_bit = -1, \ + .intr_detection_bit = -1, \ + .intr_detection_width = -1, \ + } +static const struct pinctrl_pin_desc msm8994_pins[] = { + PINCTRL_PIN(0, "GPIO_0"), + PINCTRL_PIN(1, "GPIO_1"), + PINCTRL_PIN(2, "GPIO_2"), + PINCTRL_PIN(3, "GPIO_3"), + PINCTRL_PIN(4, "GPIO_4"), + PINCTRL_PIN(5, "GPIO_5"), + PINCTRL_PIN(6, "GPIO_6"), + PINCTRL_PIN(7, "GPIO_7"), + PINCTRL_PIN(8, "GPIO_8"), + PINCTRL_PIN(9, "GPIO_9"), + PINCTRL_PIN(10, "GPIO_10"), + PINCTRL_PIN(11, "GPIO_11"), + PINCTRL_PIN(12, "GPIO_12"), + PINCTRL_PIN(13, "GPIO_13"), + PINCTRL_PIN(14, "GPIO_14"), + PINCTRL_PIN(15, "GPIO_15"), + PINCTRL_PIN(16, "GPIO_16"), + PINCTRL_PIN(17, "GPIO_17"), + PINCTRL_PIN(18, "GPIO_18"), + PINCTRL_PIN(19, "GPIO_19"), + PINCTRL_PIN(20, "GPIO_20"), + PINCTRL_PIN(21, "GPIO_21"), + PINCTRL_PIN(22, "GPIO_22"), + PINCTRL_PIN(23, "GPIO_23"), + PINCTRL_PIN(24, "GPIO_24"), + PINCTRL_PIN(25, "GPIO_25"), + PINCTRL_PIN(26, "GPIO_26"), + PINCTRL_PIN(27, "GPIO_27"), + PINCTRL_PIN(28, "GPIO_28"), + PINCTRL_PIN(29, "GPIO_29"), + PINCTRL_PIN(30, "GPIO_30"), + PINCTRL_PIN(31, "GPIO_31"), + PINCTRL_PIN(32, "GPIO_32"), + PINCTRL_PIN(33, "GPIO_33"), + PINCTRL_PIN(34, "GPIO_34"), + PINCTRL_PIN(35, "GPIO_35"), + PINCTRL_PIN(36, "GPIO_36"), + PINCTRL_PIN(37, "GPIO_37"), + PINCTRL_PIN(38, "GPIO_38"), + PINCTRL_PIN(39, "GPIO_39"), + PINCTRL_PIN(40, "GPIO_40"), + PINCTRL_PIN(41, "GPIO_41"), + PINCTRL_PIN(42, "GPIO_42"), + PINCTRL_PIN(43, "GPIO_43"), + PINCTRL_PIN(44, "GPIO_44"), + PINCTRL_PIN(45, "GPIO_45"), + PINCTRL_PIN(46, "GPIO_46"), + PINCTRL_PIN(47, "GPIO_47"), + PINCTRL_PIN(48, "GPIO_48"), + PINCTRL_PIN(49, "GPIO_49"), + PINCTRL_PIN(50, "GPIO_50"), + PINCTRL_PIN(51, "GPIO_51"), + PINCTRL_PIN(52, "GPIO_52"), + PINCTRL_PIN(53, "GPIO_53"), + PINCTRL_PIN(54, "GPIO_54"), + PINCTRL_PIN(55, "GPIO_55"), + PINCTRL_PIN(56, "GPIO_56"), + PINCTRL_PIN(57, "GPIO_57"), + PINCTRL_PIN(58, "GPIO_58"), + PINCTRL_PIN(59, "GPIO_59"), + PINCTRL_PIN(60, "GPIO_60"), + PINCTRL_PIN(61, "GPIO_61"), + PINCTRL_PIN(62, "GPIO_62"), + PINCTRL_PIN(63, "GPIO_63"), + PINCTRL_PIN(64, "GPIO_64"), + PINCTRL_PIN(65, "GPIO_65"), + PINCTRL_PIN(66, "GPIO_66"), + PINCTRL_PIN(67, "GPIO_67"), + PINCTRL_PIN(68, "GPIO_68"), + PINCTRL_PIN(69, "GPIO_69"), + PINCTRL_PIN(70, "GPIO_70"), + PINCTRL_PIN(71, "GPIO_71"), + PINCTRL_PIN(72, "GPIO_72"), + PINCTRL_PIN(73, "GPIO_73"), + PINCTRL_PIN(74, "GPIO_74"), + PINCTRL_PIN(75, "GPIO_75"), + PINCTRL_PIN(76, "GPIO_76"), + PINCTRL_PIN(77, "GPIO_77"), + PINCTRL_PIN(78, "GPIO_78"), + PINCTRL_PIN(79, "GPIO_79"), + PINCTRL_PIN(80, "GPIO_80"), + PINCTRL_PIN(81, "GPIO_81"), + PINCTRL_PIN(82, "GPIO_82"), + PINCTRL_PIN(83, "GPIO_83"), + PINCTRL_PIN(84, "GPIO_84"), + PINCTRL_PIN(85, "GPIO_85"), + PINCTRL_PIN(86, "GPIO_86"), + PINCTRL_PIN(87, "GPIO_87"), + PINCTRL_PIN(88, "GPIO_88"), + PINCTRL_PIN(89, "GPIO_89"), + PINCTRL_PIN(90, "GPIO_90"), + PINCTRL_PIN(91, "GPIO_91"), + PINCTRL_PIN(92, "GPIO_92"), + PINCTRL_PIN(93, "GPIO_93"), + PINCTRL_PIN(94, "GPIO_94"), + PINCTRL_PIN(95, "GPIO_95"), + PINCTRL_PIN(96, "GPIO_96"), + PINCTRL_PIN(97, "GPIO_97"), + PINCTRL_PIN(98, "GPIO_98"), + PINCTRL_PIN(99, "GPIO_99"), + PINCTRL_PIN(100, "GPIO_100"), + PINCTRL_PIN(101, "GPIO_101"), + PINCTRL_PIN(102, "GPIO_102"), + PINCTRL_PIN(103, "GPIO_103"), + PINCTRL_PIN(104, "GPIO_104"), + PINCTRL_PIN(105, "GPIO_105"), + PINCTRL_PIN(106, "GPIO_106"), + PINCTRL_PIN(107, "GPIO_107"), + PINCTRL_PIN(108, "GPIO_108"), + PINCTRL_PIN(109, "GPIO_109"), + PINCTRL_PIN(110, "GPIO_110"), + PINCTRL_PIN(111, "GPIO_111"), + PINCTRL_PIN(112, "GPIO_112"), + PINCTRL_PIN(113, "GPIO_113"), + PINCTRL_PIN(114, "GPIO_114"), + PINCTRL_PIN(115, "GPIO_115"), + PINCTRL_PIN(116, "GPIO_116"), + PINCTRL_PIN(117, "GPIO_117"), + PINCTRL_PIN(118, "GPIO_118"), + PINCTRL_PIN(119, "GPIO_119"), + PINCTRL_PIN(120, "GPIO_120"), + PINCTRL_PIN(121, "GPIO_121"), + PINCTRL_PIN(122, "GPIO_122"), + PINCTRL_PIN(123, "GPIO_123"), + PINCTRL_PIN(124, "GPIO_124"), + PINCTRL_PIN(125, "GPIO_125"), + PINCTRL_PIN(126, "GPIO_126"), + PINCTRL_PIN(127, "GPIO_127"), + PINCTRL_PIN(128, "GPIO_128"), + PINCTRL_PIN(129, "GPIO_129"), + PINCTRL_PIN(130, "GPIO_130"), + PINCTRL_PIN(131, "GPIO_131"), + PINCTRL_PIN(132, "GPIO_132"), + PINCTRL_PIN(133, "GPIO_133"), + PINCTRL_PIN(134, "GPIO_134"), + PINCTRL_PIN(135, "GPIO_135"), + PINCTRL_PIN(136, "GPIO_136"), + PINCTRL_PIN(137, "GPIO_137"), + PINCTRL_PIN(138, "GPIO_138"), + PINCTRL_PIN(139, "GPIO_139"), + PINCTRL_PIN(140, "GPIO_140"), + PINCTRL_PIN(141, "GPIO_141"), + PINCTRL_PIN(142, "GPIO_142"), + PINCTRL_PIN(143, "GPIO_143"), + PINCTRL_PIN(144, "GPIO_144"), + PINCTRL_PIN(145, "GPIO_145"), + PINCTRL_PIN(146, "SDC1_RCLK"), + PINCTRL_PIN(147, "SDC1_CLK"), + PINCTRL_PIN(148, "SDC1_CMD"), + PINCTRL_PIN(149, "SDC1_DATA"), + PINCTRL_PIN(150, "SDC2_CLK"), + PINCTRL_PIN(151, "SDC2_CMD"), + PINCTRL_PIN(152, "SDC2_DATA"), + PINCTRL_PIN(153, "SDC3_CLK"), + PINCTRL_PIN(154, "SDC3_CMD"), + PINCTRL_PIN(155, "SDC3_DATA"), +}; + +#define DECLARE_MSM_GPIO_PINS(pin) \ + static const unsigned int gpio##pin##_pins[] = { pin } +DECLARE_MSM_GPIO_PINS(0); +DECLARE_MSM_GPIO_PINS(1); +DECLARE_MSM_GPIO_PINS(2); +DECLARE_MSM_GPIO_PINS(3); +DECLARE_MSM_GPIO_PINS(4); +DECLARE_MSM_GPIO_PINS(5); +DECLARE_MSM_GPIO_PINS(6); +DECLARE_MSM_GPIO_PINS(7); +DECLARE_MSM_GPIO_PINS(8); +DECLARE_MSM_GPIO_PINS(9); +DECLARE_MSM_GPIO_PINS(10); +DECLARE_MSM_GPIO_PINS(11); +DECLARE_MSM_GPIO_PINS(12); +DECLARE_MSM_GPIO_PINS(13); +DECLARE_MSM_GPIO_PINS(14); +DECLARE_MSM_GPIO_PINS(15); +DECLARE_MSM_GPIO_PINS(16); +DECLARE_MSM_GPIO_PINS(17); +DECLARE_MSM_GPIO_PINS(18); +DECLARE_MSM_GPIO_PINS(19); +DECLARE_MSM_GPIO_PINS(20); +DECLARE_MSM_GPIO_PINS(21); +DECLARE_MSM_GPIO_PINS(22); +DECLARE_MSM_GPIO_PINS(23); +DECLARE_MSM_GPIO_PINS(24); +DECLARE_MSM_GPIO_PINS(25); +DECLARE_MSM_GPIO_PINS(26); +DECLARE_MSM_GPIO_PINS(27); +DECLARE_MSM_GPIO_PINS(28); +DECLARE_MSM_GPIO_PINS(29); +DECLARE_MSM_GPIO_PINS(30); +DECLARE_MSM_GPIO_PINS(31); +DECLARE_MSM_GPIO_PINS(32); +DECLARE_MSM_GPIO_PINS(33); +DECLARE_MSM_GPIO_PINS(34); +DECLARE_MSM_GPIO_PINS(35); +DECLARE_MSM_GPIO_PINS(36); +DECLARE_MSM_GPIO_PINS(37); +DECLARE_MSM_GPIO_PINS(38); +DECLARE_MSM_GPIO_PINS(39); +DECLARE_MSM_GPIO_PINS(40); +DECLARE_MSM_GPIO_PINS(41); +DECLARE_MSM_GPIO_PINS(42); +DECLARE_MSM_GPIO_PINS(43); +DECLARE_MSM_GPIO_PINS(44); +DECLARE_MSM_GPIO_PINS(45); +DECLARE_MSM_GPIO_PINS(46); +DECLARE_MSM_GPIO_PINS(47); +DECLARE_MSM_GPIO_PINS(48); +DECLARE_MSM_GPIO_PINS(49); +DECLARE_MSM_GPIO_PINS(50); +DECLARE_MSM_GPIO_PINS(51); +DECLARE_MSM_GPIO_PINS(52); +DECLARE_MSM_GPIO_PINS(53); +DECLARE_MSM_GPIO_PINS(54); +DECLARE_MSM_GPIO_PINS(55); +DECLARE_MSM_GPIO_PINS(56); +DECLARE_MSM_GPIO_PINS(57); +DECLARE_MSM_GPIO_PINS(58); +DECLARE_MSM_GPIO_PINS(59); +DECLARE_MSM_GPIO_PINS(60); +DECLARE_MSM_GPIO_PINS(61); +DECLARE_MSM_GPIO_PINS(62); +DECLARE_MSM_GPIO_PINS(63); +DECLARE_MSM_GPIO_PINS(64); +DECLARE_MSM_GPIO_PINS(65); +DECLARE_MSM_GPIO_PINS(66); +DECLARE_MSM_GPIO_PINS(67); +DECLARE_MSM_GPIO_PINS(68); +DECLARE_MSM_GPIO_PINS(69); +DECLARE_MSM_GPIO_PINS(70); +DECLARE_MSM_GPIO_PINS(71); +DECLARE_MSM_GPIO_PINS(72); +DECLARE_MSM_GPIO_PINS(73); +DECLARE_MSM_GPIO_PINS(74); +DECLARE_MSM_GPIO_PINS(75); +DECLARE_MSM_GPIO_PINS(76); +DECLARE_MSM_GPIO_PINS(77); +DECLARE_MSM_GPIO_PINS(78); +DECLARE_MSM_GPIO_PINS(79); +DECLARE_MSM_GPIO_PINS(80); +DECLARE_MSM_GPIO_PINS(81); +DECLARE_MSM_GPIO_PINS(82); +DECLARE_MSM_GPIO_PINS(83); +DECLARE_MSM_GPIO_PINS(84); +DECLARE_MSM_GPIO_PINS(85); +DECLARE_MSM_GPIO_PINS(86); +DECLARE_MSM_GPIO_PINS(87); +DECLARE_MSM_GPIO_PINS(88); +DECLARE_MSM_GPIO_PINS(89); +DECLARE_MSM_GPIO_PINS(90); +DECLARE_MSM_GPIO_PINS(91); +DECLARE_MSM_GPIO_PINS(92); +DECLARE_MSM_GPIO_PINS(93); +DECLARE_MSM_GPIO_PINS(94); +DECLARE_MSM_GPIO_PINS(95); +DECLARE_MSM_GPIO_PINS(96); +DECLARE_MSM_GPIO_PINS(97); +DECLARE_MSM_GPIO_PINS(98); +DECLARE_MSM_GPIO_PINS(99); +DECLARE_MSM_GPIO_PINS(100); +DECLARE_MSM_GPIO_PINS(101); +DECLARE_MSM_GPIO_PINS(102); +DECLARE_MSM_GPIO_PINS(103); +DECLARE_MSM_GPIO_PINS(104); +DECLARE_MSM_GPIO_PINS(105); +DECLARE_MSM_GPIO_PINS(106); +DECLARE_MSM_GPIO_PINS(107); +DECLARE_MSM_GPIO_PINS(108); +DECLARE_MSM_GPIO_PINS(109); +DECLARE_MSM_GPIO_PINS(110); +DECLARE_MSM_GPIO_PINS(111); +DECLARE_MSM_GPIO_PINS(112); +DECLARE_MSM_GPIO_PINS(113); +DECLARE_MSM_GPIO_PINS(114); +DECLARE_MSM_GPIO_PINS(115); +DECLARE_MSM_GPIO_PINS(116); +DECLARE_MSM_GPIO_PINS(117); +DECLARE_MSM_GPIO_PINS(118); +DECLARE_MSM_GPIO_PINS(119); +DECLARE_MSM_GPIO_PINS(120); +DECLARE_MSM_GPIO_PINS(121); +DECLARE_MSM_GPIO_PINS(122); +DECLARE_MSM_GPIO_PINS(123); +DECLARE_MSM_GPIO_PINS(124); +DECLARE_MSM_GPIO_PINS(125); +DECLARE_MSM_GPIO_PINS(126); +DECLARE_MSM_GPIO_PINS(127); +DECLARE_MSM_GPIO_PINS(128); +DECLARE_MSM_GPIO_PINS(129); +DECLARE_MSM_GPIO_PINS(130); +DECLARE_MSM_GPIO_PINS(131); +DECLARE_MSM_GPIO_PINS(132); +DECLARE_MSM_GPIO_PINS(133); +DECLARE_MSM_GPIO_PINS(134); +DECLARE_MSM_GPIO_PINS(135); +DECLARE_MSM_GPIO_PINS(136); +DECLARE_MSM_GPIO_PINS(137); +DECLARE_MSM_GPIO_PINS(138); +DECLARE_MSM_GPIO_PINS(139); +DECLARE_MSM_GPIO_PINS(140); +DECLARE_MSM_GPIO_PINS(141); +DECLARE_MSM_GPIO_PINS(142); +DECLARE_MSM_GPIO_PINS(143); +DECLARE_MSM_GPIO_PINS(144); +DECLARE_MSM_GPIO_PINS(145); + +static const unsigned int sdc1_rclk_pins[] = { 146 }; +static const unsigned int sdc1_clk_pins[] = { 147 }; +static const unsigned int sdc1_cmd_pins[] = { 148 }; +static const unsigned int sdc1_data_pins[] = { 149 }; +static const unsigned int sdc2_clk_pins[] = { 150 }; +static const unsigned int sdc2_cmd_pins[] = { 151 }; +static const unsigned int sdc2_data_pins[] = { 152 }; +static const unsigned int sdc3_clk_pins[] = { 153 }; +static const unsigned int sdc3_cmd_pins[] = { 154 }; +static const unsigned int sdc3_data_pins[] = { 155 }; + +enum msm8994_functions { + msm_mux_audio_ref_clk, + msm_mux_blsp_i2c1, + msm_mux_blsp_i2c2, + msm_mux_blsp_i2c3, + msm_mux_blsp_i2c4, + msm_mux_blsp_i2c5, + msm_mux_blsp_i2c6, + msm_mux_blsp_i2c7, + msm_mux_blsp_i2c8, + msm_mux_blsp_i2c9, + msm_mux_blsp_i2c10, + msm_mux_blsp_i2c11, + msm_mux_blsp_i2c12, + msm_mux_blsp_spi1, + msm_mux_blsp_spi1_cs1, + msm_mux_blsp_spi1_cs2, + msm_mux_blsp_spi1_cs3, + msm_mux_blsp_spi2, + msm_mux_blsp_spi2_cs1, + msm_mux_blsp_spi2_cs2, + msm_mux_blsp_spi2_cs3, + msm_mux_blsp_spi3, + msm_mux_blsp_spi4, + msm_mux_blsp_spi5, + msm_mux_blsp_spi6, + msm_mux_blsp_spi7, + msm_mux_blsp_spi8, + msm_mux_blsp_spi9, + msm_mux_blsp_spi10, + msm_mux_blsp_spi10_cs1, + msm_mux_blsp_spi10_cs2, + msm_mux_blsp_spi10_cs3, + msm_mux_blsp_spi11, + msm_mux_blsp_spi12, + msm_mux_blsp_uart1, + msm_mux_blsp_uart2, + msm_mux_blsp_uart3, + msm_mux_blsp_uart4, + msm_mux_blsp_uart5, + msm_mux_blsp_uart6, + msm_mux_blsp_uart7, + msm_mux_blsp_uart8, + msm_mux_blsp_uart9, + msm_mux_blsp_uart10, + msm_mux_blsp_uart11, + msm_mux_blsp_uart12, + msm_mux_blsp_uim1, + msm_mux_blsp_uim2, + msm_mux_blsp_uim3, + msm_mux_blsp_uim4, + msm_mux_blsp_uim5, + msm_mux_blsp_uim6, + msm_mux_blsp_uim7, + msm_mux_blsp_uim8, + msm_mux_blsp_uim9, + msm_mux_blsp_uim10, + msm_mux_blsp_uim11, + msm_mux_blsp_uim12, + msm_mux_blsp11_i2c_scl_b, + msm_mux_blsp11_i2c_sda_b, + msm_mux_blsp11_uart_rx_b, + msm_mux_blsp11_uart_tx_b, + msm_mux_cam_mclk0, + msm_mux_cam_mclk1, + msm_mux_cam_mclk2, + msm_mux_cam_mclk3, + msm_mux_cci_async_in0, + msm_mux_cci_async_in1, + msm_mux_cci_async_in2, + msm_mux_cci_i2c0, + msm_mux_cci_i2c1, + msm_mux_cci_timer0, + msm_mux_cci_timer1, + msm_mux_cci_timer2, + msm_mux_cci_timer3, + msm_mux_cci_timer4, + msm_mux_gcc_gp1_clk_a, + msm_mux_gcc_gp1_clk_b, + msm_mux_gcc_gp2_clk_a, + msm_mux_gcc_gp2_clk_b, + msm_mux_gcc_gp3_clk_a, + msm_mux_gcc_gp3_clk_b, + msm_mux_gp_mn, + msm_mux_gp_pdm0, + msm_mux_gp_pdm1, + msm_mux_gp_pdm2, + msm_mux_gp0_clk, + msm_mux_gp1_clk, + msm_mux_gps_tx, + msm_mux_gsm_tx, + msm_mux_hdmi_cec, + msm_mux_hdmi_ddc, + msm_mux_hdmi_hpd, + msm_mux_hdmi_rcv, + msm_mux_mdp_vsync, + msm_mux_mss_lte, + msm_mux_nav_pps, + msm_mux_nav_tsync, + msm_mux_qdss_cti_trig_in_a, + msm_mux_qdss_cti_trig_in_b, + msm_mux_qdss_cti_trig_in_c, + msm_mux_qdss_cti_trig_in_d, + msm_mux_qdss_cti_trig_out_a, + msm_mux_qdss_cti_trig_out_b, + msm_mux_qdss_cti_trig_out_c, + msm_mux_qdss_cti_trig_out_d, + msm_mux_qdss_traceclk_a, + msm_mux_qdss_traceclk_b, + msm_mux_qdss_tracectl_a, + msm_mux_qdss_tracectl_b, + msm_mux_qdss_tracedata_a, + msm_mux_qdss_tracedata_b, + msm_mux_qua_mi2s, + msm_mux_pci_e0, + msm_mux_pci_e1, + msm_mux_pri_mi2s, + msm_mux_sdc4, + msm_mux_sec_mi2s, + msm_mux_slimbus, + msm_mux_spkr_i2s, + msm_mux_ter_mi2s, + msm_mux_tsif1, + msm_mux_tsif2, + msm_mux_uim1, + msm_mux_uim2, + msm_mux_uim3, + msm_mux_uim4, + msm_mux_uim_batt_alarm, + msm_mux_gpio, + msm_mux_NA, +}; + +static const char * const gpio_groups[] = { + "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7", + "gpio8", "gpio9", "gpio10", "gpio11", "gpio12", "gpio13", "gpio14", + "gpio15", "gpio16", "gpio17", "gpio18", "gpio19", "gpio20", "gpio21", + "gpio22", "gpio23", "gpio24", "gpio25", "gpio26", "gpio27", "gpio28", + "gpio29", "gpio30", "gpio31", "gpio32", "gpio33", "gpio34", "gpio35", + "gpio36", "gpio37", "gpio38", "gpio39", "gpio40", "gpio41", "gpio42", + "gpio43", "gpio44", "gpio45", "gpio46", "gpio47", "gpio48", "gpio49", + "gpio50", "gpio51", "gpio52", "gpio53", "gpio54", "gpio55", "gpio56", + "gpio57", "gpio58", "gpio59", "gpio60", "gpio61", "gpio62", "gpio63", + "gpio64", "gpio65", "gpio66", "gpio67", "gpio68", "gpio69", "gpio70", + "gpio71", "gpio72", "gpio73", "gpio74", "gpio75", "gpio76", "gpio77", + "gpio78", "gpio79", "gpio80", "gpio81", "gpio82", "gpio83", "gpio84", + "gpio85", "gpio86", "gpio87", "gpio88", "gpio89", "gpio90", "gpio91", + "gpio92", "gpio93", "gpio94", "gpio95", "gpio96", "gpio97", "gpio98", + "gpio99", "gpio100", "gpio101", "gpio102", "gpio103", "gpio104", + "gpio105", "gpio106", "gpio107", "gpio108", "gpio109", "gpio110", + "gpio111", "gpio112", "gpio113", "gpio114", "gpio115", "gpio116", + "gpio117", "gpio118", "gpio119", "gpio120", "gpio121", "gpio122", + "gpio123", "gpio124", "gpio125", "gpio126", "gpio127", "gpio128", + "gpio129", "gpio130", "gpio131", "gpio132", "gpio133", "gpio134", + "gpio135", "gpio136", "gpio137", "gpio138", "gpio139", "gpio140", + "gpio141", "gpio142", "gpio143", "gpio144", "gpio145", +}; + +static const char * const blsp_spi1_groups[] = { + "gpio0", "gpio1", "gpio2", "gpio3" +}; +static const char * const blsp_uart1_groups[] = { + "gpio0", "gpio1", "gpio2", "gpio3" +}; +static const char * const blsp_uim1_groups[] = { + "gpio0", "gpio1" +}; +static const char * const hdmi_rcv_groups[] = { + "gpio0" +}; +static const char * const blsp_i2c1_groups[] = { + "gpio2", "gpio3" +}; +static const char * const blsp_spi2_groups[] = { + "gpio4", "gpio5", "gpio6", "gpio7" +}; +static const char * const blsp_uart2_groups[] = { + "gpio4", "gpio5", "gpio6", "gpio7" +}; +static const char * const blsp_uim2_groups[] = { + "gpio4", "gpio5" +}; +static const char * const qdss_cti_trig_out_b_groups[] = { + "gpio4", +}; +static const char * const qdss_cti_trig_in_b_groups[] = { + "gpio5", +}; +static const char * const blsp_i2c2_groups[] = { + "gpio6", "gpio7" +}; +static const char * const blsp_spi3_groups[] = { + "gpio8", "gpio9", "gpio10", "gpio11" +}; +static const char * const blsp_uart3_groups[] = { + "gpio8", "gpio9", "gpio10", "gpio11" +}; +static const char * const blsp_uim3_groups[] = { + "gpio8", "gpio9" +}; +static const char * const blsp_spi1_cs1_groups[] = { + "gpio8" +}; +static const char * const blsp_spi1_cs2_groups[] = { + "gpio9", "gpio11" +}; +static const char * const mdp_vsync_groups[] = { + "gpio10", "gpio11", "gpio12" +}; +static const char * const blsp_i2c3_groups[] = { + "gpio10", "gpio11" +}; +static const char * const blsp_spi1_cs3_groups[] = { + "gpio10" +}; +static const char * const qdss_tracedata_b_groups[] = { + "gpio13", "gpio14", "gpio15", "gpio16", "gpio17", "gpio18", + "gpio19", "gpio21", "gpio22", "gpio23", "gpio25", "gpio26", + "gpio57", "gpio58", "gpio92", "gpio93", +}; +static const char * const cam_mclk0_groups[] = { + "gpio13" +}; +static const char * const cam_mclk1_groups[] = { + "gpio14" +}; +static const char * const cam_mclk2_groups[] = { + "gpio15" +}; +static const char * const cam_mclk3_groups[] = { + "gpio16" +}; +static const char * const cci_i2c0_groups[] = { + "gpio17", "gpio18" +}; +static const char * const blsp_spi4_groups[] = { + "gpio17", "gpio18", "gpio19", "gpio20" +}; +static const char * const blsp_uart4_groups[] = { + "gpio17", "gpio18", "gpio19", "gpio20" +}; +static const char * const blsp_uim4_groups[] = { + "gpio17", "gpio18" +}; +static const char * const cci_i2c1_groups[] = { + "gpio19", "gpio20" +}; +static const char * const blsp_i2c4_groups[] = { + "gpio19", "gpio20" +}; +static const char * const cci_timer0_groups[] = { + "gpio21" +}; +static const char * const blsp_spi5_groups[] = { + "gpio21", "gpio22", "gpio23", "gpio24" +}; +static const char * const blsp_uart5_groups[] = { + "gpio21", "gpio22", "gpio23", "gpio24" +}; +static const char * const blsp_uim5_groups[] = { + "gpio21", "gpio22" +}; +static const char * const cci_timer1_groups[] = { + "gpio22" +}; +static const char * const cci_timer2_groups[] = { + "gpio23" +}; +static const char * const blsp_i2c5_groups[] = { + "gpio23", "gpio24" +}; +static const char * const cci_timer3_groups[] = { + "gpio24" +}; +static const char * const cci_async_in1_groups[] = { + "gpio24" +}; +static const char * const cci_timer4_groups[] = { + "gpio25" +}; +static const char * const cci_async_in2_groups[] = { + "gpio25" +}; +static const char * const blsp_spi6_groups[] = { + "gpio25", "gpio26", "gpio27", "gpio28" +}; +static const char * const blsp_uart6_groups[] = { + "gpio25", "gpio26", "gpio27", "gpio28" +}; +static const char * const blsp_uim6_groups[] = { + "gpio25", "gpio26" +}; +static const char * const cci_async_in0_groups[] = { + "gpio26" +}; +static const char * const gp0_clk_groups[] = { + "gpio26" +}; +static const char * const gp1_clk_groups[] = { + "gpio27", "gpio57", "gpio78" +}; +static const char * const blsp_i2c6_groups[] = { + "gpio27", "gpio28" +}; +static const char * const qdss_tracectl_a_groups[] = { + "gpio27", +}; +static const char * const qdss_traceclk_a_groups[] = { + "gpio28", +}; +static const char * const gp_mn_groups[] = { + "gpio29" +}; +static const char * const hdmi_cec_groups[] = { + "gpio31" +}; +static const char * const hdmi_ddc_groups[] = { + "gpio32", "gpio33" +}; +static const char * const hdmi_hpd_groups[] = { + "gpio34" +}; +static const char * const uim3_groups[] = { + "gpio35", "gpio36", "gpio37", "gpio38" +}; +static const char * const pci_e1_groups[] = { + "gpio35", "gpio36", +}; +static const char * const blsp_spi7_groups[] = { + "gpio41", "gpio42", "gpio43", "gpio44" +}; +static const char * const blsp_uart7_groups[] = { + "gpio41", "gpio42", "gpio43", "gpio44" +}; +static const char * const blsp_uim7_groups[] = { + "gpio41", "gpio42" +}; +static const char * const qdss_cti_trig_out_c_groups[] = { + "gpio41", +}; +static const char * const qdss_cti_trig_in_c_groups[] = { + "gpio42", +}; +static const char * const blsp_i2c7_groups[] = { + "gpio43", "gpio44" +}; +static const char * const blsp_spi8_groups[] = { + "gpio45", "gpio46", "gpio47", "gpio48" +}; +static const char * const blsp_uart8_groups[] = { + "gpio45", "gpio46", "gpio47", "gpio48" +}; +static const char * const blsp_uim8_groups[] = { + "gpio45", "gpio46" +}; +static const char * const blsp_i2c8_groups[] = { + "gpio47", "gpio48" +}; +static const char * const blsp_spi10_cs1_groups[] = { + "gpio47", "gpio67" +}; +static const char * const blsp_spi10_cs2_groups[] = { + "gpio48", "gpio68" +}; +static const char * const uim2_groups[] = { + "gpio49", "gpio50", "gpio51", "gpio52" +}; +static const char * const blsp_spi9_groups[] = { + "gpio49", "gpio50", "gpio51", "gpio52" +}; +static const char * const blsp_uart9_groups[] = { + "gpio49", "gpio50", "gpio51", "gpio52" +}; +static const char * const blsp_uim9_groups[] = { + "gpio49", "gpio50" +}; +static const char * const blsp_i2c9_groups[] = { + "gpio51", "gpio52" +}; +static const char * const pci_e0_groups[] = { + "gpio53", "gpio54", +}; +static const char * const uim4_groups[] = { + "gpio53", "gpio54", "gpio55", "gpio56" +}; +static const char * const blsp_spi10_groups[] = { + "gpio53", "gpio54", "gpio55", "gpio56" +}; +static const char * const blsp_uart10_groups[] = { + "gpio53", "gpio54", "gpio55", "gpio56" +}; +static const char * const blsp_uim10_groups[] = { + "gpio53", "gpio54" +}; +static const char * const qdss_tracedata_a_groups[] = { + "gpio53", "gpio54", "gpio63", "gpio64", "gpio65", + "gpio66", "gpio67", "gpio74", "gpio75", "gpio76", + "gpio77", "gpio85", "gpio86", "gpio87", "gpio89", + "gpio90" +}; +static const char * const gp_pdm0_groups[] = { + "gpio54", "gpio95" +}; +static const char * const blsp_i2c10_groups[] = { + "gpio55", "gpio56" +}; +static const char * const qdss_cti_trig_in_a_groups[] = { + "gpio55", +}; +static const char * const qdss_cti_trig_out_a_groups[] = { + "gpio56", +}; +static const char * const qua_mi2s_groups[] = { + "gpio57", "gpio58", "gpio59", "gpio60", "gpio61", "gpio62", "gpio63", +}; +static const char * const gcc_gp1_clk_a_groups[] = { + "gpio57" +}; +static const char * const gcc_gp2_clk_a_groups[] = { + "gpio58" +}; +static const char * const gcc_gp3_clk_a_groups[] = { + "gpio59" +}; +static const char * const blsp_spi2_cs1_groups[] = { + "gpio62" +}; +static const char * const blsp_spi2_cs2_groups[] = { + "gpio63" +}; +static const char * const gp_pdm2_groups[] = { + "gpio63", "gpio79" +}; +static const char * const pri_mi2s_groups[] = { + "gpio64", "gpio65", "gpio66", "gpio67", "gpio68" +}; +static const char * const blsp_spi2_cs3_groups[] = { + "gpio66" +}; +static const char * const spkr_i2s_groups[] = { + "gpio69", "gpio70", "gpio71", "gpio72" +}; +static const char * const audio_ref_clk_groups[] = { + "gpio69" +}; +static const char * const slimbus_groups[] = { + "gpio70", "gpio71" +}; +static const char * const ter_mi2s_groups[] = { + "gpio73", "gpio74", "gpio75", "gpio76", "gpio77" +}; +static const char * const gp_pdm1_groups[] = { + "gpio74", "gpio86" +}; +static const char * const sec_mi2s_groups[] = { + "gpio78", "gpio79", "gpio80", "gpio81", "gpio82" +}; +static const char * const gcc_gp1_clk_b_groups[] = { + "gpio78" +}; +static const char * const blsp_spi11_groups[] = { + "gpio81", "gpio82", "gpio83", "gpio84" +}; +static const char * const blsp_uart11_groups[] = { + "gpio81", "gpio82", "gpio83", "gpio84" +}; +static const char * const blsp_uim11_groups[] = { + "gpio81", "gpio82" +}; +static const char * const gcc_gp2_clk_b_groups[] = { + "gpio81" +}; +static const char * const gcc_gp3_clk_b_groups[] = { + "gpio82" +}; +static const char * const blsp_i2c11_groups[] = { + "gpio83", "gpio84" +}; +static const char * const blsp_uart12_groups[] = { + "gpio85", "gpio86", "gpio87", "gpio88" +}; +static const char * const blsp_uim12_groups[] = { + "gpio85", "gpio86" +}; +static const char * const blsp_i2c12_groups[] = { + "gpio87", "gpio88" +}; +static const char * const blsp_spi12_groups[] = { + "gpio85", "gpio86", "gpio87", "gpio88" +}; +static const char * const tsif1_groups[] = { + "gpio89", "gpio90", "gpio91", "gpio110", "gpio111" +}; +static const char * const blsp_spi10_cs3_groups[] = { + "gpio90" +}; +static const char * const sdc4_groups[] = { + "gpio91", "gpio92", "gpio93", "gpio94", "gpio95", "gpio96" +}; +static const char * const qdss_traceclk_b_groups[] = { + "gpio91", +}; +static const char * const tsif2_groups[] = { + "gpio92", "gpio93", "gpio94", "gpio95", "gpio96" +}; +static const char * const qdss_tracectl_b_groups[] = { + "gpio94", +}; +static const char * const qdss_cti_trig_out_d_groups[] = { + "gpio95", +}; +static const char * const qdss_cti_trig_in_d_groups[] = { + "gpio96", +}; +static const char * const uim1_groups[] = { + "gpio97", "gpio98", "gpio99", "gpio100" +}; +static const char * const uim_batt_alarm_groups[] = { + "gpio101" +}; +static const char * const blsp11_uart_tx_b_groups[] = { + "gpio111" +}; +static const char * const blsp11_uart_rx_b_groups[] = { + "gpio112" +}; +static const char * const blsp11_i2c_sda_b_groups[] = { + "gpio113" +}; +static const char * const blsp11_i2c_scl_b_groups[] = { + "gpio114" +}; +static const char * const gsm_tx_groups[] = { + "gpio126", "gpio131", "gpio132", "gpio133" +}; +static const char * const nav_tsync_groups[] = { + "gpio127" +}; +static const char * const nav_pps_groups[] = { + "gpio127" +}; +static const char * const gps_tx_groups[] = { + "gpio130" +}; +static const char * const mss_lte_groups[] = { + "gpio134", "gpio135" +}; + +static const struct pinfunction msm8994_functions[] = { + MSM_PIN_FUNCTION(audio_ref_clk), + MSM_PIN_FUNCTION(blsp_i2c1), + MSM_PIN_FUNCTION(blsp_i2c2), + MSM_PIN_FUNCTION(blsp_i2c3), + MSM_PIN_FUNCTION(blsp_i2c4), + MSM_PIN_FUNCTION(blsp_i2c5), + MSM_PIN_FUNCTION(blsp_i2c6), + MSM_PIN_FUNCTION(blsp_i2c7), + MSM_PIN_FUNCTION(blsp_i2c8), + MSM_PIN_FUNCTION(blsp_i2c9), + MSM_PIN_FUNCTION(blsp_i2c10), + MSM_PIN_FUNCTION(blsp_i2c11), + MSM_PIN_FUNCTION(blsp_i2c12), + MSM_PIN_FUNCTION(blsp_spi1), + MSM_PIN_FUNCTION(blsp_spi1_cs1), + MSM_PIN_FUNCTION(blsp_spi1_cs2), + MSM_PIN_FUNCTION(blsp_spi1_cs3), + MSM_PIN_FUNCTION(blsp_spi2), + MSM_PIN_FUNCTION(blsp_spi2_cs1), + MSM_PIN_FUNCTION(blsp_spi2_cs2), + MSM_PIN_FUNCTION(blsp_spi2_cs3), + MSM_PIN_FUNCTION(blsp_spi3), + MSM_PIN_FUNCTION(blsp_spi4), + MSM_PIN_FUNCTION(blsp_spi5), + MSM_PIN_FUNCTION(blsp_spi6), + MSM_PIN_FUNCTION(blsp_spi7), + MSM_PIN_FUNCTION(blsp_spi8), + MSM_PIN_FUNCTION(blsp_spi9), + MSM_PIN_FUNCTION(blsp_spi10), + MSM_PIN_FUNCTION(blsp_spi10_cs1), + MSM_PIN_FUNCTION(blsp_spi10_cs2), + MSM_PIN_FUNCTION(blsp_spi10_cs3), + MSM_PIN_FUNCTION(blsp_spi11), + MSM_PIN_FUNCTION(blsp_spi12), + MSM_PIN_FUNCTION(blsp_uart1), + MSM_PIN_FUNCTION(blsp_uart2), + MSM_PIN_FUNCTION(blsp_uart3), + MSM_PIN_FUNCTION(blsp_uart4), + MSM_PIN_FUNCTION(blsp_uart5), + MSM_PIN_FUNCTION(blsp_uart6), + MSM_PIN_FUNCTION(blsp_uart7), + MSM_PIN_FUNCTION(blsp_uart8), + MSM_PIN_FUNCTION(blsp_uart9), + MSM_PIN_FUNCTION(blsp_uart10), + MSM_PIN_FUNCTION(blsp_uart11), + MSM_PIN_FUNCTION(blsp_uart12), + MSM_PIN_FUNCTION(blsp_uim1), + MSM_PIN_FUNCTION(blsp_uim2), + MSM_PIN_FUNCTION(blsp_uim3), + MSM_PIN_FUNCTION(blsp_uim4), + MSM_PIN_FUNCTION(blsp_uim5), + MSM_PIN_FUNCTION(blsp_uim6), + MSM_PIN_FUNCTION(blsp_uim7), + MSM_PIN_FUNCTION(blsp_uim8), + MSM_PIN_FUNCTION(blsp_uim9), + MSM_PIN_FUNCTION(blsp_uim10), + MSM_PIN_FUNCTION(blsp_uim11), + MSM_PIN_FUNCTION(blsp_uim12), + MSM_PIN_FUNCTION(blsp11_i2c_scl_b), + MSM_PIN_FUNCTION(blsp11_i2c_sda_b), + MSM_PIN_FUNCTION(blsp11_uart_rx_b), + MSM_PIN_FUNCTION(blsp11_uart_tx_b), + MSM_PIN_FUNCTION(cam_mclk0), + MSM_PIN_FUNCTION(cam_mclk1), + MSM_PIN_FUNCTION(cam_mclk2), + MSM_PIN_FUNCTION(cam_mclk3), + MSM_PIN_FUNCTION(cci_async_in0), + MSM_PIN_FUNCTION(cci_async_in1), + MSM_PIN_FUNCTION(cci_async_in2), + MSM_PIN_FUNCTION(cci_i2c0), + MSM_PIN_FUNCTION(cci_i2c1), + MSM_PIN_FUNCTION(cci_timer0), + MSM_PIN_FUNCTION(cci_timer1), + MSM_PIN_FUNCTION(cci_timer2), + MSM_PIN_FUNCTION(cci_timer3), + MSM_PIN_FUNCTION(cci_timer4), + MSM_PIN_FUNCTION(gcc_gp1_clk_a), + MSM_PIN_FUNCTION(gcc_gp1_clk_b), + MSM_PIN_FUNCTION(gcc_gp2_clk_a), + MSM_PIN_FUNCTION(gcc_gp2_clk_b), + MSM_PIN_FUNCTION(gcc_gp3_clk_a), + MSM_PIN_FUNCTION(gcc_gp3_clk_b), + MSM_PIN_FUNCTION(gp_mn), + MSM_PIN_FUNCTION(gp_pdm0), + MSM_PIN_FUNCTION(gp_pdm1), + MSM_PIN_FUNCTION(gp_pdm2), + MSM_PIN_FUNCTION(gp0_clk), + MSM_PIN_FUNCTION(gp1_clk), + MSM_PIN_FUNCTION(gps_tx), + MSM_PIN_FUNCTION(gsm_tx), + MSM_PIN_FUNCTION(hdmi_cec), + MSM_PIN_FUNCTION(hdmi_ddc), + MSM_PIN_FUNCTION(hdmi_hpd), + MSM_PIN_FUNCTION(hdmi_rcv), + MSM_PIN_FUNCTION(mdp_vsync), + MSM_PIN_FUNCTION(mss_lte), + MSM_PIN_FUNCTION(nav_pps), + MSM_PIN_FUNCTION(nav_tsync), + MSM_PIN_FUNCTION(qdss_cti_trig_in_a), + MSM_PIN_FUNCTION(qdss_cti_trig_in_b), + MSM_PIN_FUNCTION(qdss_cti_trig_in_c), + MSM_PIN_FUNCTION(qdss_cti_trig_in_d), + MSM_PIN_FUNCTION(qdss_cti_trig_out_a), + MSM_PIN_FUNCTION(qdss_cti_trig_out_b), + MSM_PIN_FUNCTION(qdss_cti_trig_out_c), + MSM_PIN_FUNCTION(qdss_cti_trig_out_d), + MSM_PIN_FUNCTION(qdss_traceclk_a), + MSM_PIN_FUNCTION(qdss_traceclk_b), + MSM_PIN_FUNCTION(qdss_tracectl_a), + MSM_PIN_FUNCTION(qdss_tracectl_b), + MSM_PIN_FUNCTION(qdss_tracedata_a), + MSM_PIN_FUNCTION(qdss_tracedata_b), + MSM_PIN_FUNCTION(qua_mi2s), + MSM_PIN_FUNCTION(pci_e0), + MSM_PIN_FUNCTION(pci_e1), + MSM_PIN_FUNCTION(pri_mi2s), + MSM_PIN_FUNCTION(sdc4), + MSM_PIN_FUNCTION(sec_mi2s), + MSM_PIN_FUNCTION(slimbus), + MSM_PIN_FUNCTION(spkr_i2s), + MSM_PIN_FUNCTION(ter_mi2s), + MSM_PIN_FUNCTION(tsif1), + MSM_PIN_FUNCTION(tsif2), + MSM_PIN_FUNCTION(uim_batt_alarm), + MSM_PIN_FUNCTION(uim1), + MSM_PIN_FUNCTION(uim2), + MSM_PIN_FUNCTION(uim3), + MSM_PIN_FUNCTION(uim4), + MSM_PIN_FUNCTION(gpio), +}; + +static const struct msm_pingroup msm8994_groups[] = { + PINGROUP(0, blsp_spi1, blsp_uart1, blsp_uim1, hdmi_rcv, NA, NA, NA, + NA, NA, NA, NA), + PINGROUP(1, blsp_spi1, blsp_uart1, blsp_uim1, NA, NA, NA, NA, NA, NA, + NA, NA), + PINGROUP(2, blsp_spi1, blsp_uart1, blsp_i2c1, NA, NA, NA, NA, NA, NA, + NA, NA), + PINGROUP(3, blsp_spi1, blsp_uart1, blsp_i2c1, NA, NA, NA, NA, NA, NA, + NA, NA), + PINGROUP(4, blsp_spi2, blsp_uart2, blsp_uim2, NA, qdss_cti_trig_out_b, + NA, NA, NA, NA, NA, NA), + PINGROUP(5, blsp_spi2, blsp_uart2, blsp_uim2, NA, qdss_cti_trig_in_b, + NA, NA, NA, NA, NA, NA), + PINGROUP(6, blsp_spi2, blsp_uart2, blsp_i2c2, NA, NA, NA, NA, NA, NA, + NA, NA), + PINGROUP(7, blsp_spi2, blsp_uart2, blsp_i2c2, NA, NA, NA, NA, NA, NA, + NA, NA), + PINGROUP(8, blsp_spi3, blsp_uart3, blsp_uim3, blsp_spi1_cs1, NA, NA, + NA, NA, NA, NA, NA), + PINGROUP(9, blsp_spi3, blsp_uart3, blsp_uim3, blsp_spi1_cs2, NA, NA, + NA, NA, NA, NA, NA), + PINGROUP(10, mdp_vsync, blsp_spi3, blsp_uart3, blsp_i2c3, + blsp_spi1_cs3, NA, NA, NA, NA, NA, NA), + PINGROUP(11, mdp_vsync, blsp_spi3, blsp_uart3, blsp_i2c3, + blsp_spi1_cs2, NA, NA, NA, NA, NA, NA), + PINGROUP(12, mdp_vsync, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(13, cam_mclk0, NA, NA, qdss_tracedata_b, NA, NA, NA, NA, NA, + NA, NA), + PINGROUP(14, cam_mclk1, NA, NA, qdss_tracedata_b, NA, NA, NA, NA, NA, + NA, NA), + PINGROUP(15, cam_mclk2, NA, qdss_tracedata_b, NA, NA, NA, NA, NA, NA, + NA, NA), + PINGROUP(16, cam_mclk3, NA, qdss_tracedata_b, NA, NA, NA, NA, NA, NA, + NA, NA), + PINGROUP(17, cci_i2c0, blsp_spi4, blsp_uart4, blsp_uim4, NA, + qdss_tracedata_b, NA, NA, NA, NA, NA), + PINGROUP(18, cci_i2c0, blsp_spi4, blsp_uart4, blsp_uim4, NA, + qdss_tracedata_b, NA, NA, NA, NA, NA), + PINGROUP(19, cci_i2c1, blsp_spi4, blsp_uart4, blsp_i2c4, NA, + qdss_tracedata_b, NA, NA, NA, NA, NA), + PINGROUP(20, cci_i2c1, blsp_spi4, blsp_uart4, blsp_i2c4, NA, NA, NA, + NA, NA, NA, NA), + PINGROUP(21, cci_timer0, blsp_spi5, blsp_uart5, blsp_uim5, NA, + qdss_tracedata_b, NA, NA, NA, NA, NA), + PINGROUP(22, cci_timer1, blsp_spi5, blsp_uart5, blsp_uim5, NA, + qdss_tracedata_b, NA, NA, NA, NA, NA), + PINGROUP(23, cci_timer2, blsp_spi5, blsp_uart5, blsp_i2c5, NA, NA, + qdss_tracedata_b, NA, NA, NA, NA), + PINGROUP(24, cci_timer3, cci_async_in1, blsp_spi5, blsp_uart5, + blsp_i2c5, NA, NA, NA, NA, NA, NA), + PINGROUP(25, cci_timer4, cci_async_in2, blsp_spi6, blsp_uart6, + blsp_uim6, NA, NA, qdss_tracedata_b, NA, NA, NA), + PINGROUP(26, cci_async_in0, blsp_spi6, blsp_uart6, blsp_uim6, gp0_clk, + NA, qdss_tracedata_b, NA, NA, NA, NA), + PINGROUP(27, blsp_spi6, blsp_uart6, blsp_i2c6, gp1_clk, + qdss_tracectl_a, NA, NA, NA, NA, NA, NA), + PINGROUP(28, blsp_spi6, blsp_uart6, blsp_i2c6, qdss_traceclk_a, NA, + NA, NA, NA, NA, NA, NA), + PINGROUP(29, gp_mn, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(30, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(31, hdmi_cec, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(32, hdmi_ddc, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(33, hdmi_ddc, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(34, hdmi_hpd, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(35, uim3, pci_e1, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(36, uim3, pci_e1, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(37, uim3, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(38, uim3, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(39, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(40, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(41, blsp_spi7, blsp_uart7, blsp_uim7, qdss_cti_trig_out_c, + NA, NA, NA, NA, NA, NA, NA), + PINGROUP(42, blsp_spi7, blsp_uart7, blsp_uim7, qdss_cti_trig_in_c, NA, + NA, NA, NA, NA, NA, NA), + PINGROUP(43, blsp_spi7, blsp_uart7, blsp_i2c7, NA, NA, NA, NA, NA, NA, + NA, NA), + PINGROUP(44, blsp_spi7, blsp_uart7, blsp_i2c7, NA, NA, NA, NA, NA, NA, + NA, NA), + PINGROUP(45, blsp_spi8, blsp_uart8, blsp_uim8, NA, NA, NA, NA, NA, NA, + NA, NA), + PINGROUP(46, blsp_spi8, blsp_uart8, blsp_uim8, NA, NA, NA, NA, NA, NA, + NA, NA), + PINGROUP(47, blsp_spi8, blsp_uart8, blsp_i2c8, blsp_spi10_cs1, NA, NA, + NA, NA, NA, NA, NA), + PINGROUP(48, blsp_spi8, blsp_uart8, blsp_i2c8, blsp_spi10_cs2, NA, NA, + NA, NA, NA, NA, NA), + PINGROUP(49, uim2, blsp_spi9, blsp_uart9, blsp_uim9, NA, NA, NA, NA, + NA, NA, NA), + PINGROUP(50, uim2, blsp_spi9, blsp_uart9, blsp_uim9, NA, NA, NA, NA, + NA, NA, NA), + PINGROUP(51, uim2, blsp_spi9, blsp_uart9, blsp_i2c9, NA, NA, NA, NA, + NA, NA, NA), + PINGROUP(52, uim2, blsp_spi9, blsp_uart9, blsp_i2c9, NA, NA, NA, NA, + NA, NA, NA), + PINGROUP(53, uim4, pci_e0, blsp_spi10, blsp_uart10, blsp_uim10, NA, + NA, qdss_tracedata_a, NA, NA, NA), + PINGROUP(54, uim4, pci_e0, blsp_spi10, blsp_uart10, blsp_uim10, + gp_pdm0, NA, NA, qdss_tracedata_a, NA, NA), + PINGROUP(55, uim4, blsp_spi10, blsp_uart10, blsp_i2c10, NA, NA, NA, + qdss_cti_trig_in_a, NA, NA, NA), + PINGROUP(56, uim4, blsp_spi10, blsp_uart10, blsp_i2c10, NA, NA, + qdss_cti_trig_out_a, NA, NA, NA, NA), + PINGROUP(57, qua_mi2s, gcc_gp1_clk_a, NA, NA, qdss_tracedata_b, NA, NA, + NA, NA, NA, NA), + PINGROUP(58, qua_mi2s, gcc_gp2_clk_a, NA, NA, qdss_tracedata_b, NA, NA, + NA, NA, NA, NA), + PINGROUP(59, qua_mi2s, gcc_gp3_clk_a, NA, NA, NA, NA, NA, NA, NA, NA, + NA), + PINGROUP(60, qua_mi2s, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(61, qua_mi2s, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(62, qua_mi2s, blsp_spi2_cs1, NA, NA, NA, NA, NA, NA, NA, NA, + NA), + PINGROUP(63, qua_mi2s, blsp_spi2_cs2, gp_pdm2, NA, NA, NA, NA, NA, + qdss_tracedata_a, NA, NA), + PINGROUP(64, pri_mi2s, NA, NA, NA, qdss_tracedata_a, NA, NA, NA, NA, + NA, NA), + PINGROUP(65, pri_mi2s, NA, NA, NA, qdss_tracedata_a, NA, NA, NA, NA, + NA, NA), + PINGROUP(66, pri_mi2s, blsp_spi2_cs3, NA, NA, NA, qdss_tracedata_a, + NA, NA, NA, NA, NA), + PINGROUP(67, pri_mi2s, blsp_spi10_cs1, NA, NA, NA, qdss_tracedata_a, + NA, NA, NA, NA, NA), + PINGROUP(68, pri_mi2s, blsp_spi10_cs2, NA, NA, NA, NA, NA, NA, NA, NA, + NA), + PINGROUP(69, spkr_i2s, audio_ref_clk, NA, NA, NA, NA, NA, NA, NA, NA, + NA), + PINGROUP(70, slimbus, spkr_i2s, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(71, slimbus, spkr_i2s, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(72, spkr_i2s, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(73, ter_mi2s, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(74, ter_mi2s, gp_pdm1, NA, NA, NA, qdss_tracedata_a, NA, NA, + NA, NA, NA), + PINGROUP(75, ter_mi2s, NA, NA, qdss_tracedata_a, NA, NA, NA, NA, NA, + NA, NA), + PINGROUP(76, ter_mi2s, NA, NA, qdss_tracedata_a, NA, NA, NA, NA, NA, + NA, NA), + PINGROUP(77, ter_mi2s, NA, NA, qdss_tracedata_a, NA, NA, NA, NA, NA, + NA, NA), + PINGROUP(78, sec_mi2s, gcc_gp1_clk_b, NA, NA, NA, NA, NA, NA, NA, NA, + NA), + PINGROUP(79, sec_mi2s, gp_pdm2, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(80, sec_mi2s, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(81, sec_mi2s, blsp_spi11, blsp_uart11, blsp_uim11, + gcc_gp2_clk_b, NA, NA, NA, NA, NA, NA), + PINGROUP(82, sec_mi2s, blsp_spi11, blsp_uart11, blsp_uim11, + gcc_gp3_clk_b, NA, NA, NA, NA, NA, NA), + PINGROUP(83, blsp_spi11, blsp_uart11, blsp_i2c11, NA, NA, NA, NA, NA, + NA, NA, NA), + PINGROUP(84, blsp_spi11, blsp_uart11, blsp_i2c11, NA, NA, NA, NA, NA, + NA, NA, NA), + PINGROUP(85, blsp_spi12, blsp_uart12, blsp_uim12, NA, NA, + qdss_tracedata_a, NA, NA, NA, NA, NA), + PINGROUP(86, blsp_spi12, blsp_uart12, blsp_uim12, gp_pdm1, NA, + qdss_tracedata_a, NA, NA, NA, NA, NA), + PINGROUP(87, blsp_spi12, blsp_uart12, blsp_i2c12, NA, + qdss_tracedata_a, NA, NA, NA, NA, NA, NA), + PINGROUP(88, blsp_spi12, blsp_uart12, blsp_i2c12, NA, NA, NA, NA, NA, + NA, NA, NA), + PINGROUP(89, tsif1, NA, qdss_tracedata_a, NA, NA, NA, NA, NA, NA, NA, + NA), + PINGROUP(90, tsif1, blsp_spi10_cs3, qdss_tracedata_a, NA, NA, NA, NA, + NA, NA, NA, NA), + PINGROUP(91, tsif1, sdc4, NA, NA, NA, NA, qdss_traceclk_b, NA, NA, NA, + NA), + PINGROUP(92, tsif2, sdc4, NA, NA, qdss_tracedata_b, NA, NA, NA, NA, + NA, NA), + PINGROUP(93, tsif2, sdc4, NA, NA, NA, NA, qdss_tracedata_b, NA, NA, + NA, NA), + PINGROUP(94, tsif2, sdc4, NA, NA, NA, NA, qdss_tracectl_b, NA, NA, NA, + NA), + PINGROUP(95, tsif2, sdc4, gp_pdm0, NA, NA, NA, qdss_cti_trig_out_d, + NA, NA, NA, NA), + PINGROUP(96, tsif2, sdc4, qdss_cti_trig_in_d, NA, NA, NA, NA, NA, NA, + NA, NA), + PINGROUP(97, uim1, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(98, uim1, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(99, uim1, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(100, uim1, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(101, uim_batt_alarm, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(102, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(103, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(104, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(105, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(106, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(107, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(108, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(109, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(110, tsif1, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(111, tsif1, blsp11_uart_tx_b, NA, NA, NA, NA, NA, NA, NA, NA, + NA), + PINGROUP(112, blsp11_uart_rx_b, NA, NA, NA, NA, NA, NA, NA, NA, NA, + NA), + PINGROUP(113, blsp11_i2c_sda_b, NA, NA, NA, NA, NA, NA, NA, NA, NA, + NA), + PINGROUP(114, blsp11_i2c_scl_b, NA, NA, NA, NA, NA, NA, NA, NA, NA, + NA), + PINGROUP(115, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(116, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(117, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(118, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(119, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(120, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(121, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(122, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(123, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(124, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(125, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(126, NA, gsm_tx, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(127, NA, nav_tsync, nav_pps, NA, NA, NA, NA, NA, NA, NA, + NA), + PINGROUP(128, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(129, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(130, gps_tx, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(131, gsm_tx, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(132, gsm_tx, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(133, gsm_tx, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(134, mss_lte, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(135, mss_lte, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(136, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(137, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(138, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(139, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(140, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(141, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(142, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(143, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(144, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(145, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + SDC_PINGROUP(sdc1_rclk, 0x2044, 15, 0), + SDC_PINGROUP(sdc1_clk, 0x2044, 13, 6), + SDC_PINGROUP(sdc1_cmd, 0x2044, 11, 3), + SDC_PINGROUP(sdc1_data, 0x2044, 9, 0), + SDC_PINGROUP(sdc2_clk, 0x2048, 14, 6), + SDC_PINGROUP(sdc2_cmd, 0x2048, 11, 3), + SDC_PINGROUP(sdc2_data, 0x2048, 9, 0), + SDC_PINGROUP(sdc3_clk, 0x206c, 14, 6), + SDC_PINGROUP(sdc3_cmd, 0x206c, 11, 3), + SDC_PINGROUP(sdc3_data, 0x206c, 9, 0), +}; + +#define NUM_GPIO_PINGROUPS 146 + +static const struct msm_pinctrl_soc_data msm8994_pinctrl = { + .pins = msm8994_pins, + .npins = ARRAY_SIZE(msm8994_pins), + .functions = msm8994_functions, + .nfunctions = ARRAY_SIZE(msm8994_functions), + .groups = msm8994_groups, + .ngroups = ARRAY_SIZE(msm8994_groups), + .ngpios = NUM_GPIO_PINGROUPS, +}; + +static int msm8994_pinctrl_probe(struct platform_device *pdev) +{ + return msm_pinctrl_probe(pdev, &msm8994_pinctrl); +} + +static const struct of_device_id msm8994_pinctrl_of_match[] = { + { .compatible = "qcom,msm8992-pinctrl", }, + { .compatible = "qcom,msm8994-pinctrl", }, + { } +}; + +static struct platform_driver msm8994_pinctrl_driver = { + .driver = { + .name = "msm8994-pinctrl", + .of_match_table = msm8994_pinctrl_of_match, + }, + .probe = msm8994_pinctrl_probe, + .remove = msm_pinctrl_remove, +}; + +static int __init msm8994_pinctrl_init(void) +{ + return platform_driver_register(&msm8994_pinctrl_driver); +} +arch_initcall(msm8994_pinctrl_init); + +static void __exit msm8994_pinctrl_exit(void) +{ + platform_driver_unregister(&msm8994_pinctrl_driver); +} +module_exit(msm8994_pinctrl_exit); + +MODULE_DESCRIPTION("Qualcomm MSM8994 pinctrl driver"); +MODULE_LICENSE("GPL v2"); +MODULE_DEVICE_TABLE(of, msm8994_pinctrl_of_match); diff --git a/drivers/pinctrl/qcom/pinctrl-msm8996.c b/drivers/pinctrl/qcom/pinctrl-msm8996.c new file mode 100644 index 0000000000..46cc0b49db --- /dev/null +++ b/drivers/pinctrl/qcom/pinctrl-msm8996.c @@ -0,0 +1,1926 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2014-2015, The Linux Foundation. All rights reserved. + */ + +#include <linux/module.h> +#include <linux/of.h> +#include <linux/platform_device.h> + +#include "pinctrl-msm.h" + +#define REG_BASE 0x0 +#define REG_SIZE 0x1000 +#define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7, f8, f9) \ + { \ + .grp = PINCTRL_PINGROUP("gpio" #id, \ + gpio##id##_pins, \ + ARRAY_SIZE(gpio##id##_pins)), \ + .funcs = (int[]){ \ + msm_mux_gpio, /* gpio mode */ \ + msm_mux_##f1, \ + msm_mux_##f2, \ + msm_mux_##f3, \ + msm_mux_##f4, \ + msm_mux_##f5, \ + msm_mux_##f6, \ + msm_mux_##f7, \ + msm_mux_##f8, \ + msm_mux_##f9 \ + }, \ + .nfuncs = 10, \ + .ctl_reg = REG_BASE + REG_SIZE * id, \ + .io_reg = REG_BASE + 0x4 + REG_SIZE * id, \ + .intr_cfg_reg = REG_BASE + 0x8 + REG_SIZE * id, \ + .intr_status_reg = REG_BASE + 0xc + REG_SIZE * id, \ + .intr_target_reg = REG_BASE + 0x8 + REG_SIZE * id, \ + .mux_bit = 2, \ + .pull_bit = 0, \ + .drv_bit = 6, \ + .oe_bit = 9, \ + .in_bit = 0, \ + .out_bit = 1, \ + .intr_enable_bit = 0, \ + .intr_status_bit = 0, \ + .intr_target_bit = 5, \ + .intr_target_kpss_val = 3, \ + .intr_raw_status_bit = 4, \ + .intr_polarity_bit = 1, \ + .intr_detection_bit = 2, \ + .intr_detection_width = 2, \ + } + +#define SDC_QDSD_PINGROUP(pg_name, ctl, pull, drv) \ + { \ + .grp = PINCTRL_PINGROUP(#pg_name, \ + pg_name##_pins, \ + ARRAY_SIZE(pg_name##_pins)), \ + .ctl_reg = ctl, \ + .io_reg = 0, \ + .intr_cfg_reg = 0, \ + .intr_status_reg = 0, \ + .intr_target_reg = 0, \ + .mux_bit = -1, \ + .pull_bit = pull, \ + .drv_bit = drv, \ + .oe_bit = -1, \ + .in_bit = -1, \ + .out_bit = -1, \ + .intr_enable_bit = -1, \ + .intr_status_bit = -1, \ + .intr_target_bit = -1, \ + .intr_raw_status_bit = -1, \ + .intr_polarity_bit = -1, \ + .intr_detection_bit = -1, \ + .intr_detection_width = -1, \ + } +static const struct pinctrl_pin_desc msm8996_pins[] = { + PINCTRL_PIN(0, "GPIO_0"), + PINCTRL_PIN(1, "GPIO_1"), + PINCTRL_PIN(2, "GPIO_2"), + PINCTRL_PIN(3, "GPIO_3"), + PINCTRL_PIN(4, "GPIO_4"), + PINCTRL_PIN(5, "GPIO_5"), + PINCTRL_PIN(6, "GPIO_6"), + PINCTRL_PIN(7, "GPIO_7"), + PINCTRL_PIN(8, "GPIO_8"), + PINCTRL_PIN(9, "GPIO_9"), + PINCTRL_PIN(10, "GPIO_10"), + PINCTRL_PIN(11, "GPIO_11"), + PINCTRL_PIN(12, "GPIO_12"), + PINCTRL_PIN(13, "GPIO_13"), + PINCTRL_PIN(14, "GPIO_14"), + PINCTRL_PIN(15, "GPIO_15"), + PINCTRL_PIN(16, "GPIO_16"), + PINCTRL_PIN(17, "GPIO_17"), + PINCTRL_PIN(18, "GPIO_18"), + PINCTRL_PIN(19, "GPIO_19"), + PINCTRL_PIN(20, "GPIO_20"), + PINCTRL_PIN(21, "GPIO_21"), + PINCTRL_PIN(22, "GPIO_22"), + PINCTRL_PIN(23, "GPIO_23"), + PINCTRL_PIN(24, "GPIO_24"), + PINCTRL_PIN(25, "GPIO_25"), + PINCTRL_PIN(26, "GPIO_26"), + PINCTRL_PIN(27, "GPIO_27"), + PINCTRL_PIN(28, "GPIO_28"), + PINCTRL_PIN(29, "GPIO_29"), + PINCTRL_PIN(30, "GPIO_30"), + PINCTRL_PIN(31, "GPIO_31"), + PINCTRL_PIN(32, "GPIO_32"), + PINCTRL_PIN(33, "GPIO_33"), + PINCTRL_PIN(34, "GPIO_34"), + PINCTRL_PIN(35, "GPIO_35"), + PINCTRL_PIN(36, "GPIO_36"), + PINCTRL_PIN(37, "GPIO_37"), + PINCTRL_PIN(38, "GPIO_38"), + PINCTRL_PIN(39, "GPIO_39"), + PINCTRL_PIN(40, "GPIO_40"), + PINCTRL_PIN(41, "GPIO_41"), + PINCTRL_PIN(42, "GPIO_42"), + PINCTRL_PIN(43, "GPIO_43"), + PINCTRL_PIN(44, "GPIO_44"), + PINCTRL_PIN(45, "GPIO_45"), + PINCTRL_PIN(46, "GPIO_46"), + PINCTRL_PIN(47, "GPIO_47"), + PINCTRL_PIN(48, "GPIO_48"), + PINCTRL_PIN(49, "GPIO_49"), + PINCTRL_PIN(50, "GPIO_50"), + PINCTRL_PIN(51, "GPIO_51"), + PINCTRL_PIN(52, "GPIO_52"), + PINCTRL_PIN(53, "GPIO_53"), + PINCTRL_PIN(54, "GPIO_54"), + PINCTRL_PIN(55, "GPIO_55"), + PINCTRL_PIN(56, "GPIO_56"), + PINCTRL_PIN(57, "GPIO_57"), + PINCTRL_PIN(58, "GPIO_58"), + PINCTRL_PIN(59, "GPIO_59"), + PINCTRL_PIN(60, "GPIO_60"), + PINCTRL_PIN(61, "GPIO_61"), + PINCTRL_PIN(62, "GPIO_62"), + PINCTRL_PIN(63, "GPIO_63"), + PINCTRL_PIN(64, "GPIO_64"), + PINCTRL_PIN(65, "GPIO_65"), + PINCTRL_PIN(66, "GPIO_66"), + PINCTRL_PIN(67, "GPIO_67"), + PINCTRL_PIN(68, "GPIO_68"), + PINCTRL_PIN(69, "GPIO_69"), + PINCTRL_PIN(70, "GPIO_70"), + PINCTRL_PIN(71, "GPIO_71"), + PINCTRL_PIN(72, "GPIO_72"), + PINCTRL_PIN(73, "GPIO_73"), + PINCTRL_PIN(74, "GPIO_74"), + PINCTRL_PIN(75, "GPIO_75"), + PINCTRL_PIN(76, "GPIO_76"), + PINCTRL_PIN(77, "GPIO_77"), + PINCTRL_PIN(78, "GPIO_78"), + PINCTRL_PIN(79, "GPIO_79"), + PINCTRL_PIN(80, "GPIO_80"), + PINCTRL_PIN(81, "GPIO_81"), + PINCTRL_PIN(82, "GPIO_82"), + PINCTRL_PIN(83, "GPIO_83"), + PINCTRL_PIN(84, "GPIO_84"), + PINCTRL_PIN(85, "GPIO_85"), + PINCTRL_PIN(86, "GPIO_86"), + PINCTRL_PIN(87, "GPIO_87"), + PINCTRL_PIN(88, "GPIO_88"), + PINCTRL_PIN(89, "GPIO_89"), + PINCTRL_PIN(90, "GPIO_90"), + PINCTRL_PIN(91, "GPIO_91"), + PINCTRL_PIN(92, "GPIO_92"), + PINCTRL_PIN(93, "GPIO_93"), + PINCTRL_PIN(94, "GPIO_94"), + PINCTRL_PIN(95, "GPIO_95"), + PINCTRL_PIN(96, "GPIO_96"), + PINCTRL_PIN(97, "GPIO_97"), + PINCTRL_PIN(98, "GPIO_98"), + PINCTRL_PIN(99, "GPIO_99"), + PINCTRL_PIN(100, "GPIO_100"), + PINCTRL_PIN(101, "GPIO_101"), + PINCTRL_PIN(102, "GPIO_102"), + PINCTRL_PIN(103, "GPIO_103"), + PINCTRL_PIN(104, "GPIO_104"), + PINCTRL_PIN(105, "GPIO_105"), + PINCTRL_PIN(106, "GPIO_106"), + PINCTRL_PIN(107, "GPIO_107"), + PINCTRL_PIN(108, "GPIO_108"), + PINCTRL_PIN(109, "GPIO_109"), + PINCTRL_PIN(110, "GPIO_110"), + PINCTRL_PIN(111, "GPIO_111"), + PINCTRL_PIN(112, "GPIO_112"), + PINCTRL_PIN(113, "GPIO_113"), + PINCTRL_PIN(114, "GPIO_114"), + PINCTRL_PIN(115, "GPIO_115"), + PINCTRL_PIN(116, "GPIO_116"), + PINCTRL_PIN(117, "GPIO_117"), + PINCTRL_PIN(118, "GPIO_118"), + PINCTRL_PIN(119, "GPIO_119"), + PINCTRL_PIN(120, "GPIO_120"), + PINCTRL_PIN(121, "GPIO_121"), + PINCTRL_PIN(122, "GPIO_122"), + PINCTRL_PIN(123, "GPIO_123"), + PINCTRL_PIN(124, "GPIO_124"), + PINCTRL_PIN(125, "GPIO_125"), + PINCTRL_PIN(126, "GPIO_126"), + PINCTRL_PIN(127, "GPIO_127"), + PINCTRL_PIN(128, "GPIO_128"), + PINCTRL_PIN(129, "GPIO_129"), + PINCTRL_PIN(130, "GPIO_130"), + PINCTRL_PIN(131, "GPIO_131"), + PINCTRL_PIN(132, "GPIO_132"), + PINCTRL_PIN(133, "GPIO_133"), + PINCTRL_PIN(134, "GPIO_134"), + PINCTRL_PIN(135, "GPIO_135"), + PINCTRL_PIN(136, "GPIO_136"), + PINCTRL_PIN(137, "GPIO_137"), + PINCTRL_PIN(138, "GPIO_138"), + PINCTRL_PIN(139, "GPIO_139"), + PINCTRL_PIN(140, "GPIO_140"), + PINCTRL_PIN(141, "GPIO_141"), + PINCTRL_PIN(142, "GPIO_142"), + PINCTRL_PIN(143, "GPIO_143"), + PINCTRL_PIN(144, "GPIO_144"), + PINCTRL_PIN(145, "GPIO_145"), + PINCTRL_PIN(146, "GPIO_146"), + PINCTRL_PIN(147, "GPIO_147"), + PINCTRL_PIN(148, "GPIO_148"), + PINCTRL_PIN(149, "GPIO_149"), + PINCTRL_PIN(150, "SDC1_CLK"), + PINCTRL_PIN(151, "SDC1_CMD"), + PINCTRL_PIN(152, "SDC1_DATA"), + PINCTRL_PIN(153, "SDC2_CLK"), + PINCTRL_PIN(154, "SDC2_CMD"), + PINCTRL_PIN(155, "SDC2_DATA"), + PINCTRL_PIN(156, "SDC1_RCLK"), +}; + +#define DECLARE_MSM_GPIO_PINS(pin) \ + static const unsigned int gpio##pin##_pins[] = { pin } +DECLARE_MSM_GPIO_PINS(0); +DECLARE_MSM_GPIO_PINS(1); +DECLARE_MSM_GPIO_PINS(2); +DECLARE_MSM_GPIO_PINS(3); +DECLARE_MSM_GPIO_PINS(4); +DECLARE_MSM_GPIO_PINS(5); +DECLARE_MSM_GPIO_PINS(6); +DECLARE_MSM_GPIO_PINS(7); +DECLARE_MSM_GPIO_PINS(8); +DECLARE_MSM_GPIO_PINS(9); +DECLARE_MSM_GPIO_PINS(10); +DECLARE_MSM_GPIO_PINS(11); +DECLARE_MSM_GPIO_PINS(12); +DECLARE_MSM_GPIO_PINS(13); +DECLARE_MSM_GPIO_PINS(14); +DECLARE_MSM_GPIO_PINS(15); +DECLARE_MSM_GPIO_PINS(16); +DECLARE_MSM_GPIO_PINS(17); +DECLARE_MSM_GPIO_PINS(18); +DECLARE_MSM_GPIO_PINS(19); +DECLARE_MSM_GPIO_PINS(20); +DECLARE_MSM_GPIO_PINS(21); +DECLARE_MSM_GPIO_PINS(22); +DECLARE_MSM_GPIO_PINS(23); +DECLARE_MSM_GPIO_PINS(24); +DECLARE_MSM_GPIO_PINS(25); +DECLARE_MSM_GPIO_PINS(26); +DECLARE_MSM_GPIO_PINS(27); +DECLARE_MSM_GPIO_PINS(28); +DECLARE_MSM_GPIO_PINS(29); +DECLARE_MSM_GPIO_PINS(30); +DECLARE_MSM_GPIO_PINS(31); +DECLARE_MSM_GPIO_PINS(32); +DECLARE_MSM_GPIO_PINS(33); +DECLARE_MSM_GPIO_PINS(34); +DECLARE_MSM_GPIO_PINS(35); +DECLARE_MSM_GPIO_PINS(36); +DECLARE_MSM_GPIO_PINS(37); +DECLARE_MSM_GPIO_PINS(38); +DECLARE_MSM_GPIO_PINS(39); +DECLARE_MSM_GPIO_PINS(40); +DECLARE_MSM_GPIO_PINS(41); +DECLARE_MSM_GPIO_PINS(42); +DECLARE_MSM_GPIO_PINS(43); +DECLARE_MSM_GPIO_PINS(44); +DECLARE_MSM_GPIO_PINS(45); +DECLARE_MSM_GPIO_PINS(46); +DECLARE_MSM_GPIO_PINS(47); +DECLARE_MSM_GPIO_PINS(48); +DECLARE_MSM_GPIO_PINS(49); +DECLARE_MSM_GPIO_PINS(50); +DECLARE_MSM_GPIO_PINS(51); +DECLARE_MSM_GPIO_PINS(52); +DECLARE_MSM_GPIO_PINS(53); +DECLARE_MSM_GPIO_PINS(54); +DECLARE_MSM_GPIO_PINS(55); +DECLARE_MSM_GPIO_PINS(56); +DECLARE_MSM_GPIO_PINS(57); +DECLARE_MSM_GPIO_PINS(58); +DECLARE_MSM_GPIO_PINS(59); +DECLARE_MSM_GPIO_PINS(60); +DECLARE_MSM_GPIO_PINS(61); +DECLARE_MSM_GPIO_PINS(62); +DECLARE_MSM_GPIO_PINS(63); +DECLARE_MSM_GPIO_PINS(64); +DECLARE_MSM_GPIO_PINS(65); +DECLARE_MSM_GPIO_PINS(66); +DECLARE_MSM_GPIO_PINS(67); +DECLARE_MSM_GPIO_PINS(68); +DECLARE_MSM_GPIO_PINS(69); +DECLARE_MSM_GPIO_PINS(70); +DECLARE_MSM_GPIO_PINS(71); +DECLARE_MSM_GPIO_PINS(72); +DECLARE_MSM_GPIO_PINS(73); +DECLARE_MSM_GPIO_PINS(74); +DECLARE_MSM_GPIO_PINS(75); +DECLARE_MSM_GPIO_PINS(76); +DECLARE_MSM_GPIO_PINS(77); +DECLARE_MSM_GPIO_PINS(78); +DECLARE_MSM_GPIO_PINS(79); +DECLARE_MSM_GPIO_PINS(80); +DECLARE_MSM_GPIO_PINS(81); +DECLARE_MSM_GPIO_PINS(82); +DECLARE_MSM_GPIO_PINS(83); +DECLARE_MSM_GPIO_PINS(84); +DECLARE_MSM_GPIO_PINS(85); +DECLARE_MSM_GPIO_PINS(86); +DECLARE_MSM_GPIO_PINS(87); +DECLARE_MSM_GPIO_PINS(88); +DECLARE_MSM_GPIO_PINS(89); +DECLARE_MSM_GPIO_PINS(90); +DECLARE_MSM_GPIO_PINS(91); +DECLARE_MSM_GPIO_PINS(92); +DECLARE_MSM_GPIO_PINS(93); +DECLARE_MSM_GPIO_PINS(94); +DECLARE_MSM_GPIO_PINS(95); +DECLARE_MSM_GPIO_PINS(96); +DECLARE_MSM_GPIO_PINS(97); +DECLARE_MSM_GPIO_PINS(98); +DECLARE_MSM_GPIO_PINS(99); +DECLARE_MSM_GPIO_PINS(100); +DECLARE_MSM_GPIO_PINS(101); +DECLARE_MSM_GPIO_PINS(102); +DECLARE_MSM_GPIO_PINS(103); +DECLARE_MSM_GPIO_PINS(104); +DECLARE_MSM_GPIO_PINS(105); +DECLARE_MSM_GPIO_PINS(106); +DECLARE_MSM_GPIO_PINS(107); +DECLARE_MSM_GPIO_PINS(108); +DECLARE_MSM_GPIO_PINS(109); +DECLARE_MSM_GPIO_PINS(110); +DECLARE_MSM_GPIO_PINS(111); +DECLARE_MSM_GPIO_PINS(112); +DECLARE_MSM_GPIO_PINS(113); +DECLARE_MSM_GPIO_PINS(114); +DECLARE_MSM_GPIO_PINS(115); +DECLARE_MSM_GPIO_PINS(116); +DECLARE_MSM_GPIO_PINS(117); +DECLARE_MSM_GPIO_PINS(118); +DECLARE_MSM_GPIO_PINS(119); +DECLARE_MSM_GPIO_PINS(120); +DECLARE_MSM_GPIO_PINS(121); +DECLARE_MSM_GPIO_PINS(122); +DECLARE_MSM_GPIO_PINS(123); +DECLARE_MSM_GPIO_PINS(124); +DECLARE_MSM_GPIO_PINS(125); +DECLARE_MSM_GPIO_PINS(126); +DECLARE_MSM_GPIO_PINS(127); +DECLARE_MSM_GPIO_PINS(128); +DECLARE_MSM_GPIO_PINS(129); +DECLARE_MSM_GPIO_PINS(130); +DECLARE_MSM_GPIO_PINS(131); +DECLARE_MSM_GPIO_PINS(132); +DECLARE_MSM_GPIO_PINS(133); +DECLARE_MSM_GPIO_PINS(134); +DECLARE_MSM_GPIO_PINS(135); +DECLARE_MSM_GPIO_PINS(136); +DECLARE_MSM_GPIO_PINS(137); +DECLARE_MSM_GPIO_PINS(138); +DECLARE_MSM_GPIO_PINS(139); +DECLARE_MSM_GPIO_PINS(140); +DECLARE_MSM_GPIO_PINS(141); +DECLARE_MSM_GPIO_PINS(142); +DECLARE_MSM_GPIO_PINS(143); +DECLARE_MSM_GPIO_PINS(144); +DECLARE_MSM_GPIO_PINS(145); +DECLARE_MSM_GPIO_PINS(146); +DECLARE_MSM_GPIO_PINS(147); +DECLARE_MSM_GPIO_PINS(148); +DECLARE_MSM_GPIO_PINS(149); + +static const unsigned int sdc1_clk_pins[] = { 150 }; +static const unsigned int sdc1_cmd_pins[] = { 151 }; +static const unsigned int sdc1_data_pins[] = { 152 }; +static const unsigned int sdc2_clk_pins[] = { 153 }; +static const unsigned int sdc2_cmd_pins[] = { 154 }; +static const unsigned int sdc2_data_pins[] = { 155 }; +static const unsigned int sdc1_rclk_pins[] = { 156 }; + +enum msm8996_functions { + msm_mux_adsp_ext, + msm_mux_atest_bbrx0, + msm_mux_atest_bbrx1, + msm_mux_atest_char, + msm_mux_atest_char0, + msm_mux_atest_char1, + msm_mux_atest_char2, + msm_mux_atest_char3, + msm_mux_atest_gpsadc0, + msm_mux_atest_gpsadc1, + msm_mux_atest_tsens, + msm_mux_atest_tsens2, + msm_mux_atest_usb1, + msm_mux_atest_usb10, + msm_mux_atest_usb11, + msm_mux_atest_usb12, + msm_mux_atest_usb13, + msm_mux_atest_usb2, + msm_mux_atest_usb20, + msm_mux_atest_usb21, + msm_mux_atest_usb22, + msm_mux_atest_usb23, + msm_mux_audio_ref, + msm_mux_bimc_dte0, + msm_mux_bimc_dte1, + msm_mux_blsp10_spi, + msm_mux_blsp11_i2c_scl_b, + msm_mux_blsp11_i2c_sda_b, + msm_mux_blsp11_uart_rx_b, + msm_mux_blsp11_uart_tx_b, + msm_mux_blsp1_spi, + msm_mux_blsp2_spi, + msm_mux_blsp_i2c1, + msm_mux_blsp_i2c10, + msm_mux_blsp_i2c11, + msm_mux_blsp_i2c12, + msm_mux_blsp_i2c2, + msm_mux_blsp_i2c3, + msm_mux_blsp_i2c4, + msm_mux_blsp_i2c5, + msm_mux_blsp_i2c6, + msm_mux_blsp_i2c7, + msm_mux_blsp_i2c8, + msm_mux_blsp_i2c9, + msm_mux_blsp_spi1, + msm_mux_blsp_spi10, + msm_mux_blsp_spi11, + msm_mux_blsp_spi12, + msm_mux_blsp_spi2, + msm_mux_blsp_spi3, + msm_mux_blsp_spi4, + msm_mux_blsp_spi5, + msm_mux_blsp_spi6, + msm_mux_blsp_spi7, + msm_mux_blsp_spi8, + msm_mux_blsp_spi9, + msm_mux_blsp_uart1, + msm_mux_blsp_uart10, + msm_mux_blsp_uart11, + msm_mux_blsp_uart12, + msm_mux_blsp_uart2, + msm_mux_blsp_uart3, + msm_mux_blsp_uart4, + msm_mux_blsp_uart5, + msm_mux_blsp_uart6, + msm_mux_blsp_uart7, + msm_mux_blsp_uart8, + msm_mux_blsp_uart9, + msm_mux_blsp_uim1, + msm_mux_blsp_uim10, + msm_mux_blsp_uim11, + msm_mux_blsp_uim12, + msm_mux_blsp_uim2, + msm_mux_blsp_uim3, + msm_mux_blsp_uim4, + msm_mux_blsp_uim5, + msm_mux_blsp_uim6, + msm_mux_blsp_uim7, + msm_mux_blsp_uim8, + msm_mux_blsp_uim9, + msm_mux_btfm_slimbus, + msm_mux_cam_mclk, + msm_mux_cci_async, + msm_mux_cci_i2c, + msm_mux_cci_timer0, + msm_mux_cci_timer1, + msm_mux_cci_timer2, + msm_mux_cci_timer3, + msm_mux_cci_timer4, + msm_mux_cri_trng, + msm_mux_cri_trng0, + msm_mux_cri_trng1, + msm_mux_dac_calib0, + msm_mux_dac_calib1, + msm_mux_dac_calib10, + msm_mux_dac_calib11, + msm_mux_dac_calib12, + msm_mux_dac_calib13, + msm_mux_dac_calib14, + msm_mux_dac_calib15, + msm_mux_dac_calib16, + msm_mux_dac_calib17, + msm_mux_dac_calib18, + msm_mux_dac_calib19, + msm_mux_dac_calib2, + msm_mux_dac_calib20, + msm_mux_dac_calib21, + msm_mux_dac_calib22, + msm_mux_dac_calib23, + msm_mux_dac_calib24, + msm_mux_dac_calib25, + msm_mux_dac_calib26, + msm_mux_dac_calib3, + msm_mux_dac_calib4, + msm_mux_dac_calib5, + msm_mux_dac_calib6, + msm_mux_dac_calib7, + msm_mux_dac_calib8, + msm_mux_dac_calib9, + msm_mux_dac_gpio, + msm_mux_dbg_out, + msm_mux_ddr_bist, + msm_mux_edp_hot, + msm_mux_edp_lcd, + msm_mux_gcc_gp1_clk_a, + msm_mux_gcc_gp1_clk_b, + msm_mux_gcc_gp2_clk_a, + msm_mux_gcc_gp2_clk_b, + msm_mux_gcc_gp3_clk_a, + msm_mux_gcc_gp3_clk_b, + msm_mux_gsm_tx, + msm_mux_hdmi_cec, + msm_mux_hdmi_ddc, + msm_mux_hdmi_hot, + msm_mux_hdmi_rcv, + msm_mux_isense_dbg, + msm_mux_ldo_en, + msm_mux_ldo_update, + msm_mux_lpass_slimbus, + msm_mux_m_voc, + msm_mux_mdp_vsync, + msm_mux_mdp_vsync_p_b, + msm_mux_mdp_vsync_s_b, + msm_mux_modem_tsync, + msm_mux_mss_lte, + msm_mux_nav_dr, + msm_mux_nav_pps, + msm_mux_pa_indicator, + msm_mux_pci_e0, + msm_mux_pci_e1, + msm_mux_pci_e2, + msm_mux_pll_bypassnl, + msm_mux_pll_reset, + msm_mux_pri_mi2s, + msm_mux_prng_rosc, + msm_mux_pwr_crypto, + msm_mux_pwr_modem, + msm_mux_pwr_nav, + msm_mux_qdss_cti, + msm_mux_qdss_cti_trig_in_a, + msm_mux_qdss_cti_trig_in_b, + msm_mux_qdss_cti_trig_out_a, + msm_mux_qdss_cti_trig_out_b, + msm_mux_qdss_stm0, + msm_mux_qdss_stm1, + msm_mux_qdss_stm10, + msm_mux_qdss_stm11, + msm_mux_qdss_stm12, + msm_mux_qdss_stm13, + msm_mux_qdss_stm14, + msm_mux_qdss_stm15, + msm_mux_qdss_stm16, + msm_mux_qdss_stm17, + msm_mux_qdss_stm18, + msm_mux_qdss_stm19, + msm_mux_qdss_stm2, + msm_mux_qdss_stm20, + msm_mux_qdss_stm21, + msm_mux_qdss_stm22, + msm_mux_qdss_stm23, + msm_mux_qdss_stm24, + msm_mux_qdss_stm25, + msm_mux_qdss_stm26, + msm_mux_qdss_stm27, + msm_mux_qdss_stm28, + msm_mux_qdss_stm29, + msm_mux_qdss_stm3, + msm_mux_qdss_stm30, + msm_mux_qdss_stm31, + msm_mux_qdss_stm4, + msm_mux_qdss_stm5, + msm_mux_qdss_stm6, + msm_mux_qdss_stm7, + msm_mux_qdss_stm8, + msm_mux_qdss_stm9, + msm_mux_qdss_traceclk_a, + msm_mux_qdss_traceclk_b, + msm_mux_qdss_tracectl_a, + msm_mux_qdss_tracectl_b, + msm_mux_qdss_tracedata_11, + msm_mux_qdss_tracedata_12, + msm_mux_qdss_tracedata_a, + msm_mux_qdss_tracedata_b, + msm_mux_qspi0, + msm_mux_qspi1, + msm_mux_qspi2, + msm_mux_qspi3, + msm_mux_qspi_clk, + msm_mux_qspi_cs, + msm_mux_qua_mi2s, + msm_mux_sd_card, + msm_mux_sd_write, + msm_mux_sdc40, + msm_mux_sdc41, + msm_mux_sdc42, + msm_mux_sdc43, + msm_mux_sdc4_clk, + msm_mux_sdc4_cmd, + msm_mux_sec_mi2s, + msm_mux_spkr_i2s, + msm_mux_ssbi1, + msm_mux_ssbi2, + msm_mux_ssc_irq, + msm_mux_ter_mi2s, + msm_mux_tsense_pwm1, + msm_mux_tsense_pwm2, + msm_mux_tsif1_clk, + msm_mux_tsif1_data, + msm_mux_tsif1_en, + msm_mux_tsif1_error, + msm_mux_tsif1_sync, + msm_mux_tsif2_clk, + msm_mux_tsif2_data, + msm_mux_tsif2_en, + msm_mux_tsif2_error, + msm_mux_tsif2_sync, + msm_mux_uim1, + msm_mux_uim2, + msm_mux_uim3, + msm_mux_uim4, + msm_mux_uim_batt, + msm_mux_vfr_1, + msm_mux_gpio, + msm_mux_NA, +}; + +static const char * const gpio_groups[] = { + "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7", + "gpio8", "gpio9", "gpio10", "gpio11", "gpio12", "gpio13", "gpio14", + "gpio15", "gpio16", "gpio17", "gpio18", "gpio19", "gpio20", "gpio21", + "gpio22", "gpio23", "gpio24", "gpio25", "gpio26", "gpio27", "gpio28", + "gpio29", "gpio30", "gpio31", "gpio32", "gpio33", "gpio34", "gpio35", + "gpio36", "gpio37", "gpio38", "gpio39", "gpio40", "gpio41", "gpio42", + "gpio43", "gpio44", "gpio45", "gpio46", "gpio47", "gpio48", "gpio49", + "gpio50", "gpio51", "gpio52", "gpio53", "gpio54", "gpio55", "gpio56", + "gpio57", "gpio58", "gpio59", "gpio60", "gpio61", "gpio62", "gpio63", + "gpio64", "gpio65", "gpio66", "gpio67", "gpio68", "gpio69", "gpio70", + "gpio71", "gpio72", "gpio73", "gpio74", "gpio75", "gpio76", "gpio77", + "gpio78", "gpio79", "gpio80", "gpio81", "gpio82", "gpio83", "gpio84", + "gpio85", "gpio86", "gpio87", "gpio88", "gpio89", "gpio90", "gpio91", + "gpio92", "gpio93", "gpio94", "gpio95", "gpio96", "gpio97", "gpio98", + "gpio99", "gpio100", "gpio101", "gpio102", "gpio103", "gpio104", + "gpio105", "gpio106", "gpio107", "gpio108", "gpio109", "gpio110", + "gpio111", "gpio112", "gpio113", "gpio114", "gpio115", "gpio116", + "gpio117", "gpio118", "gpio119", "gpio120", "gpio121", "gpio122", + "gpio123", "gpio124", "gpio125", "gpio126", "gpio127", "gpio128", + "gpio129", "gpio130", "gpio131", "gpio132", "gpio133", "gpio134", + "gpio135", "gpio136", "gpio137", "gpio138", "gpio139", "gpio140", + "gpio141", "gpio142", "gpio143", "gpio144", "gpio145", "gpio146", + "gpio147", "gpio148", "gpio149" +}; + + +static const char * const blsp_uart1_groups[] = { + "gpio0", "gpio1", "gpio2", "gpio3", +}; +static const char * const blsp_spi1_groups[] = { + "gpio0", "gpio1", "gpio2", "gpio3", +}; +static const char * const blsp_i2c1_groups[] = { + "gpio2", "gpio3", +}; +static const char * const blsp_uim1_groups[] = { + "gpio0", "gpio1", +}; +static const char * const atest_tsens_groups[] = { + "gpio3", +}; +static const char * const bimc_dte1_groups[] = { + "gpio3", "gpio5", +}; +static const char * const blsp_spi8_groups[] = { + "gpio4", "gpio5", "gpio6", "gpio7", +}; +static const char * const blsp_uart8_groups[] = { + "gpio4", "gpio5", "gpio6", "gpio7", +}; +static const char * const blsp_uim8_groups[] = { + "gpio4", "gpio5", +}; +static const char * const qdss_cti_trig_out_b_groups[] = { + "gpio4", +}; +static const char * const dac_calib0_groups[] = { + "gpio4", "gpio41", +}; +static const char * const bimc_dte0_groups[] = { + "gpio4", "gpio6", +}; +static const char * const qdss_cti_trig_in_b_groups[] = { + "gpio5", +}; +static const char * const dac_calib1_groups[] = { + "gpio5", "gpio42", +}; +static const char * const dac_calib2_groups[] = { + "gpio6", "gpio43", +}; +static const char * const atest_tsens2_groups[] = { + "gpio7", +}; +static const char * const blsp_spi10_groups[] = { + "gpio8", "gpio9", "gpio10", "gpio11", +}; +static const char * const blsp_uart10_groups[] = { + "gpio8", "gpio9", "gpio10", "gpio11", +}; +static const char * const blsp_uim10_groups[] = { + "gpio8", "gpio9", +}; +static const char * const atest_bbrx1_groups[] = { + "gpio8", +}; +static const char * const atest_usb12_groups[] = { + "gpio9", +}; +static const char * const mdp_vsync_groups[] = { + "gpio10", "gpio11", "gpio12", +}; +static const char * const edp_lcd_groups[] = { + "gpio10", +}; +static const char * const blsp_i2c10_groups[] = { + "gpio10", "gpio11", +}; +static const char * const atest_usb11_groups[] = { + "gpio10", +}; +static const char * const atest_gpsadc0_groups[] = { + "gpio11", +}; +static const char * const edp_hot_groups[] = { + "gpio11", +}; +static const char * const atest_usb10_groups[] = { + "gpio11", +}; +static const char * const m_voc_groups[] = { + "gpio12", +}; +static const char * const dac_gpio_groups[] = { + "gpio12", +}; +static const char * const atest_char_groups[] = { + "gpio12", +}; +static const char * const cam_mclk_groups[] = { + "gpio13", "gpio14", "gpio15", "gpio16", +}; +static const char * const pll_bypassnl_groups[] = { + "gpio13", +}; +static const char * const qdss_stm7_groups[] = { + "gpio13", +}; +static const char * const blsp_i2c8_groups[] = { + "gpio6", "gpio7", +}; +static const char * const atest_usb1_groups[] = { + "gpio7", +}; +static const char * const atest_usb13_groups[] = { + "gpio8", +}; +static const char * const atest_bbrx0_groups[] = { + "gpio9", +}; +static const char * const atest_gpsadc1_groups[] = { + "gpio10", +}; +static const char * const qdss_tracedata_b_groups[] = { + "gpio13", "gpio14", "gpio15", "gpio16", "gpio17", "gpio18", "gpio19", + "gpio21", "gpio22", "gpio23", "gpio26", "gpio29", "gpio57", "gpio58", + "gpio92", "gpio93", +}; +static const char * const pll_reset_groups[] = { + "gpio14", +}; +static const char * const qdss_stm6_groups[] = { + "gpio14", +}; +static const char * const qdss_stm5_groups[] = { + "gpio15", +}; +static const char * const qdss_stm4_groups[] = { + "gpio16", +}; +static const char * const atest_usb2_groups[] = { + "gpio16", +}; +static const char * const dac_calib3_groups[] = { + "gpio17", "gpio44", +}; +static const char * const cci_i2c_groups[] = { + "gpio17", "gpio18", "gpio19", "gpio20", +}; +static const char * const qdss_stm3_groups[] = { + "gpio17", +}; +static const char * const atest_usb23_groups[] = { + "gpio17", +}; +static const char * const atest_char3_groups[] = { + "gpio17", +}; +static const char * const dac_calib4_groups[] = { + "gpio18", "gpio45", +}; +static const char * const qdss_stm2_groups[] = { + "gpio18", +}; +static const char * const atest_usb22_groups[] = { + "gpio18", +}; +static const char * const atest_char2_groups[] = { + "gpio18", +}; +static const char * const dac_calib5_groups[] = { + "gpio19", "gpio46", +}; +static const char * const qdss_stm1_groups[] = { + "gpio19", +}; +static const char * const atest_usb21_groups[] = { + "gpio19", +}; +static const char * const atest_char1_groups[] = { + "gpio19", +}; +static const char * const dac_calib6_groups[] = { + "gpio20", "gpio47", +}; +static const char * const dbg_out_groups[] = { + "gpio20", +}; +static const char * const qdss_stm0_groups[] = { + "gpio20", +}; +static const char * const atest_usb20_groups[] = { + "gpio20", +}; +static const char * const atest_char0_groups[] = { + "gpio20", +}; +static const char * const dac_calib7_groups[] = { + "gpio21", "gpio48", +}; +static const char * const cci_timer0_groups[] = { + "gpio21", +}; +static const char * const qdss_stm13_groups[] = { + "gpio21", +}; +static const char * const dac_calib8_groups[] = { + "gpio22", "gpio49", +}; +static const char * const cci_timer1_groups[] = { + "gpio22", +}; +static const char * const qdss_stm12_groups[] = { + "gpio22", +}; +static const char * const dac_calib9_groups[] = { + "gpio23", "gpio50", +}; +static const char * const cci_timer2_groups[] = { + "gpio23", +}; +static const char * const qdss_stm11_groups[] = { + "gpio23", +}; +static const char * const dac_calib10_groups[] = { + "gpio24", "gpio51", +}; +static const char * const cci_timer3_groups[] = { + "gpio24", +}; +static const char * const cci_async_groups[] = { + "gpio24", "gpio25", "gpio26", +}; +static const char * const blsp1_spi_groups[] = { + "gpio24", "gpio27", "gpio28", "gpio90", +}; +static const char * const qdss_stm10_groups[] = { + "gpio24", +}; +static const char * const qdss_cti_trig_in_a_groups[] = { + "gpio24", +}; +static const char * const dac_calib11_groups[] = { + "gpio25", "gpio52", +}; +static const char * const cci_timer4_groups[] = { + "gpio25", +}; +static const char * const blsp_spi6_groups[] = { + "gpio25", "gpio26", "gpio27", "gpio28", +}; +static const char * const blsp_uart6_groups[] = { + "gpio25", "gpio26", "gpio27", "gpio28", +}; +static const char * const blsp_uim6_groups[] = { + "gpio25", "gpio26", +}; +static const char * const blsp2_spi_groups[] = { + "gpio25", "gpio29", "gpio30", +}; +static const char * const qdss_stm9_groups[] = { + "gpio25", +}; +static const char * const qdss_cti_trig_out_a_groups[] = { + "gpio25", +}; +static const char * const dac_calib12_groups[] = { + "gpio26", "gpio53", +}; +static const char * const qdss_stm8_groups[] = { + "gpio26", +}; +static const char * const dac_calib13_groups[] = { + "gpio27", "gpio54", +}; +static const char * const blsp_i2c6_groups[] = { + "gpio27", "gpio28", +}; +static const char * const qdss_tracectl_a_groups[] = { + "gpio27", +}; +static const char * const dac_calib14_groups[] = { + "gpio28", "gpio55", +}; +static const char * const qdss_traceclk_a_groups[] = { + "gpio28", +}; +static const char * const dac_calib15_groups[] = { + "gpio29", "gpio56", +}; +static const char * const dac_calib16_groups[] = { + "gpio30", "gpio57", +}; +static const char * const hdmi_rcv_groups[] = { + "gpio30", +}; +static const char * const dac_calib17_groups[] = { + "gpio31", "gpio58", +}; +static const char * const pwr_modem_groups[] = { + "gpio31", +}; +static const char * const hdmi_cec_groups[] = { + "gpio31", +}; +static const char * const pwr_nav_groups[] = { + "gpio32", +}; +static const char * const dac_calib18_groups[] = { + "gpio32", "gpio59", +}; +static const char * const hdmi_ddc_groups[] = { + "gpio32", "gpio33", +}; +static const char * const pwr_crypto_groups[] = { + "gpio33", +}; +static const char * const dac_calib19_groups[] = { + "gpio33", "gpio60", +}; +static const char * const dac_calib20_groups[] = { + "gpio34", "gpio61", +}; +static const char * const hdmi_hot_groups[] = { + "gpio34", +}; +static const char * const dac_calib21_groups[] = { + "gpio35", "gpio62", +}; +static const char * const pci_e0_groups[] = { + "gpio35", "gpio36", +}; +static const char * const dac_calib22_groups[] = { + "gpio36", "gpio63", +}; +static const char * const dac_calib23_groups[] = { + "gpio37", "gpio64", +}; +static const char * const blsp_i2c2_groups[] = { + "gpio43", "gpio44", +}; +static const char * const blsp_spi3_groups[] = { + "gpio45", "gpio46", "gpio47", "gpio48", +}; +static const char * const blsp_uart3_groups[] = { + "gpio45", "gpio46", "gpio47", "gpio48", +}; +static const char * const blsp_uim3_groups[] = { + "gpio45", "gpio46", +}; +static const char * const blsp_i2c3_groups[] = { + "gpio47", "gpio48", +}; +static const char * const dac_calib24_groups[] = { + "gpio38", "gpio65", +}; +static const char * const dac_calib25_groups[] = { + "gpio39", "gpio66", +}; +static const char * const tsif1_sync_groups[] = { + "gpio39", +}; +static const char * const sd_write_groups[] = { + "gpio40", +}; +static const char * const tsif1_error_groups[] = { + "gpio40", +}; +static const char * const blsp_spi2_groups[] = { + "gpio41", "gpio42", "gpio43", "gpio44", +}; +static const char * const blsp_uart2_groups[] = { + "gpio41", "gpio42", "gpio43", "gpio44", +}; +static const char * const blsp_uim2_groups[] = { + "gpio41", "gpio42", +}; +static const char * const qdss_cti_groups[] = { + "gpio41", "gpio42", "gpio100", "gpio101", +}; +static const char * const uim3_groups[] = { + "gpio49", "gpio50", "gpio51", "gpio52", +}; +static const char * const blsp_spi9_groups[] = { + "gpio49", "gpio50", "gpio51", "gpio52", +}; +static const char * const blsp_uart9_groups[] = { + "gpio49", "gpio50", "gpio51", "gpio52", +}; +static const char * const blsp_uim9_groups[] = { + "gpio49", "gpio50", +}; +static const char * const blsp10_spi_groups[] = { + "gpio49", "gpio50", "gpio51", "gpio52", "gpio88", +}; +static const char * const blsp_i2c9_groups[] = { + "gpio51", "gpio52", +}; +static const char * const blsp_spi7_groups[] = { + "gpio53", "gpio54", "gpio55", "gpio56", +}; +static const char * const blsp_uart7_groups[] = { + "gpio53", "gpio54", "gpio55", "gpio56", +}; +static const char * const blsp_uim7_groups[] = { + "gpio53", "gpio54", +}; +static const char * const qdss_tracedata_a_groups[] = { + "gpio53", "gpio54", "gpio63", "gpio64", "gpio65", "gpio66", "gpio67", + "gpio74", "gpio75", "gpio76", "gpio77", "gpio85", "gpio86", "gpio87", + "gpio89", "gpio90", +}; +static const char * const blsp_i2c7_groups[] = { + "gpio55", "gpio56", +}; +static const char * const qua_mi2s_groups[] = { + "gpio57", "gpio58", "gpio59", "gpio60", "gpio61", "gpio62", "gpio63", +}; +static const char * const gcc_gp1_clk_a_groups[] = { + "gpio57", +}; +static const char * const uim4_groups[] = { + "gpio58", "gpio59", "gpio60", "gpio61", +}; +static const char * const blsp_spi11_groups[] = { + "gpio58", "gpio59", "gpio60", "gpio61", +}; +static const char * const blsp_uart11_groups[] = { + "gpio58", "gpio59", "gpio60", "gpio61", +}; +static const char * const blsp_uim11_groups[] = { + "gpio58", "gpio59", +}; +static const char * const gcc_gp2_clk_a_groups[] = { + "gpio58", +}; +static const char * const gcc_gp3_clk_a_groups[] = { + "gpio59", +}; +static const char * const blsp_i2c11_groups[] = { + "gpio60", "gpio61", +}; +static const char * const cri_trng0_groups[] = { + "gpio60", +}; +static const char * const cri_trng1_groups[] = { + "gpio61", +}; +static const char * const cri_trng_groups[] = { + "gpio62", +}; +static const char * const qdss_stm18_groups[] = { + "gpio63", +}; +static const char * const pri_mi2s_groups[] = { + "gpio64", "gpio65", "gpio66", "gpio67", "gpio68", +}; +static const char * const qdss_stm17_groups[] = { + "gpio64", +}; +static const char * const blsp_spi4_groups[] = { + "gpio65", "gpio66", "gpio67", "gpio68", +}; +static const char * const blsp_uart4_groups[] = { + "gpio65", "gpio66", "gpio67", "gpio68", +}; +static const char * const blsp_uim4_groups[] = { + "gpio65", "gpio66", +}; +static const char * const qdss_stm16_groups[] = { + "gpio65", +}; +static const char * const qdss_stm15_groups[] = { + "gpio66", +}; +static const char * const dac_calib26_groups[] = { + "gpio67", +}; +static const char * const blsp_i2c4_groups[] = { + "gpio67", "gpio68", +}; +static const char * const qdss_stm14_groups[] = { + "gpio67", +}; +static const char * const spkr_i2s_groups[] = { + "gpio69", "gpio70", "gpio71", "gpio72", +}; +static const char * const audio_ref_groups[] = { + "gpio69", +}; +static const char * const lpass_slimbus_groups[] = { + "gpio70", "gpio71", "gpio72", +}; +static const char * const isense_dbg_groups[] = { + "gpio70", +}; +static const char * const tsense_pwm1_groups[] = { + "gpio71", +}; +static const char * const tsense_pwm2_groups[] = { + "gpio71", +}; +static const char * const btfm_slimbus_groups[] = { + "gpio73", "gpio74", +}; +static const char * const ter_mi2s_groups[] = { + "gpio74", "gpio75", "gpio76", "gpio77", "gpio78", +}; +static const char * const qdss_stm22_groups[] = { + "gpio74", +}; +static const char * const qdss_stm21_groups[] = { + "gpio75", +}; +static const char * const qdss_stm20_groups[] = { + "gpio76", +}; +static const char * const qdss_stm19_groups[] = { + "gpio77", +}; +static const char * const ssc_irq_groups[] = { + "gpio78", "gpio79", "gpio80", "gpio117", "gpio118", "gpio119", + "gpio120", "gpio121", "gpio122", "gpio123", "gpio124", "gpio125", +}; +static const char * const gcc_gp1_clk_b_groups[] = { + "gpio78", +}; +static const char * const sec_mi2s_groups[] = { + "gpio79", "gpio80", "gpio81", "gpio82", "gpio83", +}; +static const char * const blsp_spi5_groups[] = { + "gpio81", "gpio82", "gpio83", "gpio84", +}; +static const char * const blsp_uart5_groups[] = { + "gpio81", "gpio82", "gpio83", "gpio84", +}; +static const char * const blsp_uim5_groups[] = { + "gpio81", "gpio82", +}; +static const char * const gcc_gp2_clk_b_groups[] = { + "gpio81", +}; +static const char * const gcc_gp3_clk_b_groups[] = { + "gpio82", +}; +static const char * const blsp_i2c5_groups[] = { + "gpio83", "gpio84", +}; +static const char * const blsp_spi12_groups[] = { + "gpio85", "gpio86", "gpio87", "gpio88", +}; +static const char * const blsp_uart12_groups[] = { + "gpio85", "gpio86", "gpio87", "gpio88", +}; +static const char * const blsp_uim12_groups[] = { + "gpio85", "gpio86", +}; +static const char * const qdss_stm25_groups[] = { + "gpio85", +}; +static const char * const qdss_stm31_groups[] = { + "gpio86", +}; +static const char * const blsp_i2c12_groups[] = { + "gpio87", "gpio88", +}; +static const char * const qdss_stm30_groups[] = { + "gpio87", +}; +static const char * const qdss_stm29_groups[] = { + "gpio88", +}; +static const char * const tsif1_clk_groups[] = { + "gpio89", +}; +static const char * const qdss_stm28_groups[] = { + "gpio89", +}; +static const char * const tsif1_en_groups[] = { + "gpio90", +}; +static const char * const tsif1_data_groups[] = { + "gpio91", +}; +static const char * const sdc4_cmd_groups[] = { + "gpio91", +}; +static const char * const qdss_stm27_groups[] = { + "gpio91", +}; +static const char * const qdss_traceclk_b_groups[] = { + "gpio91", +}; +static const char * const tsif2_error_groups[] = { + "gpio92", +}; +static const char * const sdc43_groups[] = { + "gpio92", +}; +static const char * const vfr_1_groups[] = { + "gpio92", +}; +static const char * const qdss_stm26_groups[] = { + "gpio92", +}; +static const char * const tsif2_clk_groups[] = { + "gpio93", +}; +static const char * const sdc4_clk_groups[] = { + "gpio93", +}; +static const char * const qdss_stm24_groups[] = { + "gpio93", +}; +static const char * const tsif2_en_groups[] = { + "gpio94", +}; +static const char * const sdc42_groups[] = { + "gpio94", +}; +static const char * const qdss_stm23_groups[] = { + "gpio94", +}; +static const char * const qdss_tracectl_b_groups[] = { + "gpio94", +}; +static const char * const sd_card_groups[] = { + "gpio95", +}; +static const char * const tsif2_data_groups[] = { + "gpio95", +}; +static const char * const sdc41_groups[] = { + "gpio95", +}; +static const char * const tsif2_sync_groups[] = { + "gpio96", +}; +static const char * const sdc40_groups[] = { + "gpio96", +}; +static const char * const mdp_vsync_p_b_groups[] = { + "gpio97", +}; +static const char * const ldo_en_groups[] = { + "gpio97", +}; +static const char * const mdp_vsync_s_b_groups[] = { + "gpio98", +}; +static const char * const ldo_update_groups[] = { + "gpio98", +}; +static const char * const blsp11_uart_tx_b_groups[] = { + "gpio100", +}; +static const char * const blsp11_uart_rx_b_groups[] = { + "gpio101", +}; +static const char * const blsp11_i2c_sda_b_groups[] = { + "gpio102", +}; +static const char * const prng_rosc_groups[] = { + "gpio102", +}; +static const char * const blsp11_i2c_scl_b_groups[] = { + "gpio103", +}; +static const char * const uim2_groups[] = { + "gpio105", "gpio106", "gpio107", "gpio108", +}; +static const char * const uim1_groups[] = { + "gpio109", "gpio110", "gpio111", "gpio112", +}; +static const char * const uim_batt_groups[] = { + "gpio113", +}; +static const char * const pci_e2_groups[] = { + "gpio114", "gpio115", "gpio116", +}; +static const char * const pa_indicator_groups[] = { + "gpio116", +}; +static const char * const adsp_ext_groups[] = { + "gpio118", +}; +static const char * const ddr_bist_groups[] = { + "gpio121", "gpio122", "gpio123", "gpio124", +}; +static const char * const qdss_tracedata_11_groups[] = { + "gpio123", +}; +static const char * const qdss_tracedata_12_groups[] = { + "gpio124", +}; +static const char * const modem_tsync_groups[] = { + "gpio128", +}; +static const char * const nav_dr_groups[] = { + "gpio128", +}; +static const char * const nav_pps_groups[] = { + "gpio128", +}; +static const char * const pci_e1_groups[] = { + "gpio130", "gpio131", "gpio132", +}; +static const char * const gsm_tx_groups[] = { + "gpio134", "gpio135", +}; +static const char * const qspi_cs_groups[] = { + "gpio138", "gpio141", +}; +static const char * const ssbi2_groups[] = { + "gpio139", +}; +static const char * const ssbi1_groups[] = { + "gpio140", +}; +static const char * const mss_lte_groups[] = { + "gpio144", "gpio145", +}; +static const char * const qspi_clk_groups[] = { + "gpio145", +}; +static const char * const qspi0_groups[] = { + "gpio146", +}; +static const char * const qspi1_groups[] = { + "gpio147", +}; +static const char * const qspi2_groups[] = { + "gpio148", +}; +static const char * const qspi3_groups[] = { + "gpio149", +}; + +static const struct pinfunction msm8996_functions[] = { + MSM_PIN_FUNCTION(adsp_ext), + MSM_PIN_FUNCTION(atest_bbrx0), + MSM_PIN_FUNCTION(atest_bbrx1), + MSM_PIN_FUNCTION(atest_char), + MSM_PIN_FUNCTION(atest_char0), + MSM_PIN_FUNCTION(atest_char1), + MSM_PIN_FUNCTION(atest_char2), + MSM_PIN_FUNCTION(atest_char3), + MSM_PIN_FUNCTION(atest_gpsadc0), + MSM_PIN_FUNCTION(atest_gpsadc1), + MSM_PIN_FUNCTION(atest_tsens), + MSM_PIN_FUNCTION(atest_tsens2), + MSM_PIN_FUNCTION(atest_usb1), + MSM_PIN_FUNCTION(atest_usb10), + MSM_PIN_FUNCTION(atest_usb11), + MSM_PIN_FUNCTION(atest_usb12), + MSM_PIN_FUNCTION(atest_usb13), + MSM_PIN_FUNCTION(atest_usb2), + MSM_PIN_FUNCTION(atest_usb20), + MSM_PIN_FUNCTION(atest_usb21), + MSM_PIN_FUNCTION(atest_usb22), + MSM_PIN_FUNCTION(atest_usb23), + MSM_PIN_FUNCTION(audio_ref), + MSM_PIN_FUNCTION(bimc_dte0), + MSM_PIN_FUNCTION(bimc_dte1), + MSM_PIN_FUNCTION(blsp10_spi), + MSM_PIN_FUNCTION(blsp11_i2c_scl_b), + MSM_PIN_FUNCTION(blsp11_i2c_sda_b), + MSM_PIN_FUNCTION(blsp11_uart_rx_b), + MSM_PIN_FUNCTION(blsp11_uart_tx_b), + MSM_PIN_FUNCTION(blsp1_spi), + MSM_PIN_FUNCTION(blsp2_spi), + MSM_PIN_FUNCTION(blsp_i2c1), + MSM_PIN_FUNCTION(blsp_i2c10), + MSM_PIN_FUNCTION(blsp_i2c11), + MSM_PIN_FUNCTION(blsp_i2c12), + MSM_PIN_FUNCTION(blsp_i2c2), + MSM_PIN_FUNCTION(blsp_i2c3), + MSM_PIN_FUNCTION(blsp_i2c4), + MSM_PIN_FUNCTION(blsp_i2c5), + MSM_PIN_FUNCTION(blsp_i2c6), + MSM_PIN_FUNCTION(blsp_i2c7), + MSM_PIN_FUNCTION(blsp_i2c8), + MSM_PIN_FUNCTION(blsp_i2c9), + MSM_PIN_FUNCTION(blsp_spi1), + MSM_PIN_FUNCTION(blsp_spi10), + MSM_PIN_FUNCTION(blsp_spi11), + MSM_PIN_FUNCTION(blsp_spi12), + MSM_PIN_FUNCTION(blsp_spi2), + MSM_PIN_FUNCTION(blsp_spi3), + MSM_PIN_FUNCTION(blsp_spi4), + MSM_PIN_FUNCTION(blsp_spi5), + MSM_PIN_FUNCTION(blsp_spi6), + MSM_PIN_FUNCTION(blsp_spi7), + MSM_PIN_FUNCTION(blsp_spi8), + MSM_PIN_FUNCTION(blsp_spi9), + MSM_PIN_FUNCTION(blsp_uart1), + MSM_PIN_FUNCTION(blsp_uart10), + MSM_PIN_FUNCTION(blsp_uart11), + MSM_PIN_FUNCTION(blsp_uart12), + MSM_PIN_FUNCTION(blsp_uart2), + MSM_PIN_FUNCTION(blsp_uart3), + MSM_PIN_FUNCTION(blsp_uart4), + MSM_PIN_FUNCTION(blsp_uart5), + MSM_PIN_FUNCTION(blsp_uart6), + MSM_PIN_FUNCTION(blsp_uart7), + MSM_PIN_FUNCTION(blsp_uart8), + MSM_PIN_FUNCTION(blsp_uart9), + MSM_PIN_FUNCTION(blsp_uim1), + MSM_PIN_FUNCTION(blsp_uim10), + MSM_PIN_FUNCTION(blsp_uim11), + MSM_PIN_FUNCTION(blsp_uim12), + MSM_PIN_FUNCTION(blsp_uim2), + MSM_PIN_FUNCTION(blsp_uim3), + MSM_PIN_FUNCTION(blsp_uim4), + MSM_PIN_FUNCTION(blsp_uim5), + MSM_PIN_FUNCTION(blsp_uim6), + MSM_PIN_FUNCTION(blsp_uim7), + MSM_PIN_FUNCTION(blsp_uim8), + MSM_PIN_FUNCTION(blsp_uim9), + MSM_PIN_FUNCTION(btfm_slimbus), + MSM_PIN_FUNCTION(cam_mclk), + MSM_PIN_FUNCTION(cci_async), + MSM_PIN_FUNCTION(cci_i2c), + MSM_PIN_FUNCTION(cci_timer0), + MSM_PIN_FUNCTION(cci_timer1), + MSM_PIN_FUNCTION(cci_timer2), + MSM_PIN_FUNCTION(cci_timer3), + MSM_PIN_FUNCTION(cci_timer4), + MSM_PIN_FUNCTION(cri_trng), + MSM_PIN_FUNCTION(cri_trng0), + MSM_PIN_FUNCTION(cri_trng1), + MSM_PIN_FUNCTION(dac_calib0), + MSM_PIN_FUNCTION(dac_calib1), + MSM_PIN_FUNCTION(dac_calib10), + MSM_PIN_FUNCTION(dac_calib11), + MSM_PIN_FUNCTION(dac_calib12), + MSM_PIN_FUNCTION(dac_calib13), + MSM_PIN_FUNCTION(dac_calib14), + MSM_PIN_FUNCTION(dac_calib15), + MSM_PIN_FUNCTION(dac_calib16), + MSM_PIN_FUNCTION(dac_calib17), + MSM_PIN_FUNCTION(dac_calib18), + MSM_PIN_FUNCTION(dac_calib19), + MSM_PIN_FUNCTION(dac_calib2), + MSM_PIN_FUNCTION(dac_calib20), + MSM_PIN_FUNCTION(dac_calib21), + MSM_PIN_FUNCTION(dac_calib22), + MSM_PIN_FUNCTION(dac_calib23), + MSM_PIN_FUNCTION(dac_calib24), + MSM_PIN_FUNCTION(dac_calib25), + MSM_PIN_FUNCTION(dac_calib26), + MSM_PIN_FUNCTION(dac_calib3), + MSM_PIN_FUNCTION(dac_calib4), + MSM_PIN_FUNCTION(dac_calib5), + MSM_PIN_FUNCTION(dac_calib6), + MSM_PIN_FUNCTION(dac_calib7), + MSM_PIN_FUNCTION(dac_calib8), + MSM_PIN_FUNCTION(dac_calib9), + MSM_PIN_FUNCTION(dac_gpio), + MSM_PIN_FUNCTION(dbg_out), + MSM_PIN_FUNCTION(ddr_bist), + MSM_PIN_FUNCTION(edp_hot), + MSM_PIN_FUNCTION(edp_lcd), + MSM_PIN_FUNCTION(gcc_gp1_clk_a), + MSM_PIN_FUNCTION(gcc_gp1_clk_b), + MSM_PIN_FUNCTION(gcc_gp2_clk_a), + MSM_PIN_FUNCTION(gcc_gp2_clk_b), + MSM_PIN_FUNCTION(gcc_gp3_clk_a), + MSM_PIN_FUNCTION(gcc_gp3_clk_b), + MSM_PIN_FUNCTION(gpio), + MSM_PIN_FUNCTION(gsm_tx), + MSM_PIN_FUNCTION(hdmi_cec), + MSM_PIN_FUNCTION(hdmi_ddc), + MSM_PIN_FUNCTION(hdmi_hot), + MSM_PIN_FUNCTION(hdmi_rcv), + MSM_PIN_FUNCTION(isense_dbg), + MSM_PIN_FUNCTION(ldo_en), + MSM_PIN_FUNCTION(ldo_update), + MSM_PIN_FUNCTION(lpass_slimbus), + MSM_PIN_FUNCTION(m_voc), + MSM_PIN_FUNCTION(mdp_vsync), + MSM_PIN_FUNCTION(mdp_vsync_p_b), + MSM_PIN_FUNCTION(mdp_vsync_s_b), + MSM_PIN_FUNCTION(modem_tsync), + MSM_PIN_FUNCTION(mss_lte), + MSM_PIN_FUNCTION(nav_dr), + MSM_PIN_FUNCTION(nav_pps), + MSM_PIN_FUNCTION(pa_indicator), + MSM_PIN_FUNCTION(pci_e0), + MSM_PIN_FUNCTION(pci_e1), + MSM_PIN_FUNCTION(pci_e2), + MSM_PIN_FUNCTION(pll_bypassnl), + MSM_PIN_FUNCTION(pll_reset), + MSM_PIN_FUNCTION(pri_mi2s), + MSM_PIN_FUNCTION(prng_rosc), + MSM_PIN_FUNCTION(pwr_crypto), + MSM_PIN_FUNCTION(pwr_modem), + MSM_PIN_FUNCTION(pwr_nav), + MSM_PIN_FUNCTION(qdss_cti), + MSM_PIN_FUNCTION(qdss_cti_trig_in_a), + MSM_PIN_FUNCTION(qdss_cti_trig_in_b), + MSM_PIN_FUNCTION(qdss_cti_trig_out_a), + MSM_PIN_FUNCTION(qdss_cti_trig_out_b), + MSM_PIN_FUNCTION(qdss_stm0), + MSM_PIN_FUNCTION(qdss_stm1), + MSM_PIN_FUNCTION(qdss_stm10), + MSM_PIN_FUNCTION(qdss_stm11), + MSM_PIN_FUNCTION(qdss_stm12), + MSM_PIN_FUNCTION(qdss_stm13), + MSM_PIN_FUNCTION(qdss_stm14), + MSM_PIN_FUNCTION(qdss_stm15), + MSM_PIN_FUNCTION(qdss_stm16), + MSM_PIN_FUNCTION(qdss_stm17), + MSM_PIN_FUNCTION(qdss_stm18), + MSM_PIN_FUNCTION(qdss_stm19), + MSM_PIN_FUNCTION(qdss_stm2), + MSM_PIN_FUNCTION(qdss_stm20), + MSM_PIN_FUNCTION(qdss_stm21), + MSM_PIN_FUNCTION(qdss_stm22), + MSM_PIN_FUNCTION(qdss_stm23), + MSM_PIN_FUNCTION(qdss_stm24), + MSM_PIN_FUNCTION(qdss_stm25), + MSM_PIN_FUNCTION(qdss_stm26), + MSM_PIN_FUNCTION(qdss_stm27), + MSM_PIN_FUNCTION(qdss_stm28), + MSM_PIN_FUNCTION(qdss_stm29), + MSM_PIN_FUNCTION(qdss_stm3), + MSM_PIN_FUNCTION(qdss_stm30), + MSM_PIN_FUNCTION(qdss_stm31), + MSM_PIN_FUNCTION(qdss_stm4), + MSM_PIN_FUNCTION(qdss_stm5), + MSM_PIN_FUNCTION(qdss_stm6), + MSM_PIN_FUNCTION(qdss_stm7), + MSM_PIN_FUNCTION(qdss_stm8), + MSM_PIN_FUNCTION(qdss_stm9), + MSM_PIN_FUNCTION(qdss_traceclk_a), + MSM_PIN_FUNCTION(qdss_traceclk_b), + MSM_PIN_FUNCTION(qdss_tracectl_a), + MSM_PIN_FUNCTION(qdss_tracectl_b), + MSM_PIN_FUNCTION(qdss_tracedata_11), + MSM_PIN_FUNCTION(qdss_tracedata_12), + MSM_PIN_FUNCTION(qdss_tracedata_a), + MSM_PIN_FUNCTION(qdss_tracedata_b), + MSM_PIN_FUNCTION(qspi0), + MSM_PIN_FUNCTION(qspi1), + MSM_PIN_FUNCTION(qspi2), + MSM_PIN_FUNCTION(qspi3), + MSM_PIN_FUNCTION(qspi_clk), + MSM_PIN_FUNCTION(qspi_cs), + MSM_PIN_FUNCTION(qua_mi2s), + MSM_PIN_FUNCTION(sd_card), + MSM_PIN_FUNCTION(sd_write), + MSM_PIN_FUNCTION(sdc40), + MSM_PIN_FUNCTION(sdc41), + MSM_PIN_FUNCTION(sdc42), + MSM_PIN_FUNCTION(sdc43), + MSM_PIN_FUNCTION(sdc4_clk), + MSM_PIN_FUNCTION(sdc4_cmd), + MSM_PIN_FUNCTION(sec_mi2s), + MSM_PIN_FUNCTION(spkr_i2s), + MSM_PIN_FUNCTION(ssbi1), + MSM_PIN_FUNCTION(ssbi2), + MSM_PIN_FUNCTION(ssc_irq), + MSM_PIN_FUNCTION(ter_mi2s), + MSM_PIN_FUNCTION(tsense_pwm1), + MSM_PIN_FUNCTION(tsense_pwm2), + MSM_PIN_FUNCTION(tsif1_clk), + MSM_PIN_FUNCTION(tsif1_data), + MSM_PIN_FUNCTION(tsif1_en), + MSM_PIN_FUNCTION(tsif1_error), + MSM_PIN_FUNCTION(tsif1_sync), + MSM_PIN_FUNCTION(tsif2_clk), + MSM_PIN_FUNCTION(tsif2_data), + MSM_PIN_FUNCTION(tsif2_en), + MSM_PIN_FUNCTION(tsif2_error), + MSM_PIN_FUNCTION(tsif2_sync), + MSM_PIN_FUNCTION(uim1), + MSM_PIN_FUNCTION(uim2), + MSM_PIN_FUNCTION(uim3), + MSM_PIN_FUNCTION(uim4), + MSM_PIN_FUNCTION(uim_batt), + MSM_PIN_FUNCTION(vfr_1), +}; + +static const struct msm_pingroup msm8996_groups[] = { + PINGROUP(0, blsp_spi1, blsp_uart1, blsp_uim1, NA, NA, NA, NA, NA, NA), + PINGROUP(1, blsp_spi1, blsp_uart1, blsp_uim1, NA, NA, NA, NA, NA, NA), + PINGROUP(2, blsp_spi1, blsp_uart1, blsp_i2c1, NA, NA, NA, NA, NA, NA), + PINGROUP(3, blsp_spi1, blsp_uart1, blsp_i2c1, NA, atest_tsens, + bimc_dte1, NA, NA, NA), + PINGROUP(4, blsp_spi8, blsp_uart8, blsp_uim8, NA, qdss_cti_trig_out_b, + dac_calib0, bimc_dte0, NA, NA), + PINGROUP(5, blsp_spi8, blsp_uart8, blsp_uim8, NA, qdss_cti_trig_in_b, + dac_calib1, bimc_dte1, NA, NA), + PINGROUP(6, blsp_spi8, blsp_uart8, blsp_i2c8, NA, dac_calib2, + bimc_dte0, NA, NA, NA), + PINGROUP(7, blsp_spi8, blsp_uart8, blsp_i2c8, NA, atest_tsens2, + atest_usb1, NA, NA, NA), + PINGROUP(8, blsp_spi10, blsp_uart10, blsp_uim10, NA, atest_bbrx1, + atest_usb13, NA, NA, NA), + PINGROUP(9, blsp_spi10, blsp_uart10, blsp_uim10, atest_bbrx0, + atest_usb12, NA, NA, NA, NA), + PINGROUP(10, mdp_vsync, blsp_spi10, blsp_uart10, blsp_i2c10, + atest_gpsadc1, atest_usb11, NA, NA, NA), + PINGROUP(11, mdp_vsync, blsp_spi10, blsp_uart10, blsp_i2c10, + atest_gpsadc0, atest_usb10, NA, NA, NA), + PINGROUP(12, mdp_vsync, m_voc, dac_gpio, atest_char, NA, NA, NA, NA, + NA), + PINGROUP(13, cam_mclk, pll_bypassnl, qdss_stm7, qdss_tracedata_b, NA, + NA, NA, NA, NA), + PINGROUP(14, cam_mclk, pll_reset, qdss_stm6, qdss_tracedata_b, NA, NA, + NA, NA, NA), + PINGROUP(15, cam_mclk, qdss_stm5, qdss_tracedata_b, NA, NA, NA, NA, NA, + NA), + PINGROUP(16, cam_mclk, qdss_stm4, qdss_tracedata_b, NA, atest_usb2, NA, + NA, NA, NA), + PINGROUP(17, cci_i2c, qdss_stm3, qdss_tracedata_b, dac_calib3, + atest_usb23, atest_char3, NA, NA, NA), + PINGROUP(18, cci_i2c, qdss_stm2, qdss_tracedata_b, dac_calib4, + atest_usb22, atest_char2, NA, NA, NA), + PINGROUP(19, cci_i2c, qdss_stm1, qdss_tracedata_b, dac_calib5, + atest_usb21, atest_char1, NA, NA, NA), + PINGROUP(20, cci_i2c, dbg_out, qdss_stm0, dac_calib6, atest_usb20, + atest_char0, NA, NA, NA), + PINGROUP(21, cci_timer0, qdss_stm13, qdss_tracedata_b, dac_calib7, NA, + NA, NA, NA, NA), + PINGROUP(22, cci_timer1, qdss_stm12, qdss_tracedata_b, dac_calib8, NA, + NA, NA, NA, NA), + PINGROUP(23, cci_timer2, blsp1_spi, qdss_stm11, qdss_tracedata_b, + dac_calib9, NA, NA, NA, NA), + PINGROUP(24, cci_timer3, cci_async, blsp1_spi, qdss_stm10, + qdss_cti_trig_in_a, dac_calib10, NA, NA, NA), + PINGROUP(25, cci_timer4, cci_async, blsp_spi6, blsp_uart6, blsp_uim6, + blsp2_spi, qdss_stm9, qdss_cti_trig_out_a, dac_calib11), + PINGROUP(26, cci_async, blsp_spi6, blsp_uart6, blsp_uim6, qdss_stm8, + qdss_tracedata_b, dac_calib12, NA, NA), + PINGROUP(27, blsp_spi6, blsp_uart6, blsp_i2c6, blsp1_spi, + qdss_tracectl_a, dac_calib13, NA, NA, NA), + PINGROUP(28, blsp_spi6, blsp_uart6, blsp_i2c6, blsp1_spi, + qdss_traceclk_a, dac_calib14, NA, NA, NA), + PINGROUP(29, blsp2_spi, NA, qdss_tracedata_b, dac_calib15, NA, NA, NA, + NA, NA), + PINGROUP(30, hdmi_rcv, blsp2_spi, dac_calib16, NA, NA, NA, NA, NA, NA), + PINGROUP(31, hdmi_cec, pwr_modem, dac_calib17, NA, NA, NA, NA, NA, NA), + PINGROUP(32, hdmi_ddc, pwr_nav, NA, dac_calib18, NA, NA, NA, NA, NA), + PINGROUP(33, hdmi_ddc, pwr_crypto, NA, dac_calib19, NA, NA, NA, NA, NA), + PINGROUP(34, hdmi_hot, NA, dac_calib20, NA, NA, NA, NA, NA, NA), + PINGROUP(35, pci_e0, NA, dac_calib21, NA, NA, NA, NA, NA, NA), + PINGROUP(36, pci_e0, NA, dac_calib22, NA, NA, NA, NA, NA, NA), + PINGROUP(37, NA, dac_calib23, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(38, NA, dac_calib24, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(39, tsif1_sync, NA, dac_calib25, NA, NA, NA, NA, NA, NA), + PINGROUP(40, sd_write, tsif1_error, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(41, blsp_spi2, blsp_uart2, blsp_uim2, NA, qdss_cti, + dac_calib0, NA, NA, NA), + PINGROUP(42, blsp_spi2, blsp_uart2, blsp_uim2, NA, qdss_cti, + dac_calib1, NA, NA, NA), + PINGROUP(43, blsp_spi2, blsp_uart2, blsp_i2c2, NA, dac_calib2, NA, NA, + NA, NA), + PINGROUP(44, blsp_spi2, blsp_uart2, blsp_i2c2, NA, dac_calib3, NA, NA, + NA, NA), + PINGROUP(45, blsp_spi3, blsp_uart3, blsp_uim3, NA, dac_calib4, NA, NA, + NA, NA), + PINGROUP(46, blsp_spi3, blsp_uart3, blsp_uim3, NA, dac_calib5, NA, NA, + NA, NA), + PINGROUP(47, blsp_spi3, blsp_uart3, blsp_i2c3, dac_calib6, NA, NA, NA, + NA, NA), + PINGROUP(48, blsp_spi3, blsp_uart3, blsp_i2c3, dac_calib7, NA, NA, NA, + NA, NA), + PINGROUP(49, uim3, blsp_spi9, blsp_uart9, blsp_uim9, blsp10_spi, + dac_calib8, NA, NA, NA), + PINGROUP(50, uim3, blsp_spi9, blsp_uart9, blsp_uim9, blsp10_spi, + dac_calib9, NA, NA, NA), + PINGROUP(51, uim3, blsp_spi9, blsp_uart9, blsp_i2c9, blsp10_spi, + dac_calib10, NA, NA, NA), + PINGROUP(52, uim3, blsp_spi9, blsp_uart9, blsp_i2c9, + blsp10_spi, dac_calib11, NA, NA, NA), + PINGROUP(53, blsp_spi7, blsp_uart7, blsp_uim7, NA, qdss_tracedata_a, + dac_calib12, NA, NA, NA), + PINGROUP(54, blsp_spi7, blsp_uart7, blsp_uim7, NA, NA, + qdss_tracedata_a, dac_calib13, NA, NA), + PINGROUP(55, blsp_spi7, blsp_uart7, blsp_i2c7, NA, dac_calib14, NA, NA, + NA, NA), + PINGROUP(56, blsp_spi7, blsp_uart7, blsp_i2c7, NA, dac_calib15, NA, NA, + NA, NA), + PINGROUP(57, qua_mi2s, gcc_gp1_clk_a, NA, qdss_tracedata_b, + dac_calib16, NA, NA, NA, NA), + PINGROUP(58, qua_mi2s, uim4, blsp_spi11, blsp_uart11, blsp_uim11, + gcc_gp2_clk_a, NA, qdss_tracedata_b, dac_calib17), + PINGROUP(59, qua_mi2s, uim4, blsp_spi11, blsp_uart11, blsp_uim11, + gcc_gp3_clk_a, NA, dac_calib18, NA), + PINGROUP(60, qua_mi2s, uim4, blsp_spi11, blsp_uart11, blsp_i2c11, + cri_trng0, NA, dac_calib19, NA), + PINGROUP(61, qua_mi2s, uim4, blsp_spi11, blsp_uart11, + blsp_i2c11, cri_trng1, NA, dac_calib20, NA), + PINGROUP(62, qua_mi2s, cri_trng, NA, dac_calib21, NA, NA, NA, NA, NA), + PINGROUP(63, qua_mi2s, NA, NA, qdss_stm18, qdss_tracedata_a, + dac_calib22, NA, NA, NA), + PINGROUP(64, pri_mi2s, NA, qdss_stm17, qdss_tracedata_a, dac_calib23, + NA, NA, NA, NA), + PINGROUP(65, pri_mi2s, blsp_spi4, blsp_uart4, blsp_uim4, NA, + qdss_stm16, qdss_tracedata_a, dac_calib24, NA), + PINGROUP(66, pri_mi2s, blsp_spi4, blsp_uart4, blsp_uim4, NA, + qdss_stm15, qdss_tracedata_a, dac_calib25, NA), + PINGROUP(67, pri_mi2s, blsp_spi4, blsp_uart4, blsp_i2c4, qdss_stm14, + qdss_tracedata_a, dac_calib26, NA, NA), + PINGROUP(68, pri_mi2s, blsp_spi4, blsp_uart4, blsp_i2c4, NA, NA, NA, + NA, NA), + PINGROUP(69, spkr_i2s, audio_ref, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(70, lpass_slimbus, spkr_i2s, isense_dbg, NA, NA, NA, NA, NA, + NA), + PINGROUP(71, lpass_slimbus, spkr_i2s, tsense_pwm1, tsense_pwm2, NA, NA, + NA, NA, NA), + PINGROUP(72, lpass_slimbus, spkr_i2s, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(73, btfm_slimbus, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(74, btfm_slimbus, ter_mi2s, qdss_stm22, qdss_tracedata_a, NA, + NA, NA, NA, NA), + PINGROUP(75, ter_mi2s, qdss_stm21, qdss_tracedata_a, NA, NA, NA, NA, + NA, NA), + PINGROUP(76, ter_mi2s, qdss_stm20, qdss_tracedata_a, NA, NA, NA, NA, + NA, NA), + PINGROUP(77, ter_mi2s, qdss_stm19, qdss_tracedata_a, NA, NA, NA, NA, + NA, NA), + PINGROUP(78, ter_mi2s, gcc_gp1_clk_b, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(79, sec_mi2s, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(80, sec_mi2s, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(81, sec_mi2s, blsp_spi5, blsp_uart5, blsp_uim5, gcc_gp2_clk_b, + NA, NA, NA, NA), + PINGROUP(82, sec_mi2s, blsp_spi5, blsp_uart5, blsp_uim5, gcc_gp3_clk_b, + NA, NA, NA, NA), + PINGROUP(83, sec_mi2s, blsp_spi5, blsp_uart5, blsp_i2c5, NA, NA, NA, + NA, NA), + PINGROUP(84, blsp_spi5, blsp_uart5, blsp_i2c5, NA, NA, NA, NA, NA, NA), + PINGROUP(85, blsp_spi12, blsp_uart12, blsp_uim12, NA, qdss_stm25, + qdss_tracedata_a, NA, NA, NA), + PINGROUP(86, blsp_spi12, blsp_uart12, blsp_uim12, NA, NA, qdss_stm31, + qdss_tracedata_a, NA, NA), + PINGROUP(87, blsp_spi12, blsp_uart12, blsp_i2c12, NA, qdss_stm30, + qdss_tracedata_a, NA, NA, NA), + PINGROUP(88, blsp_spi12, blsp_uart12, blsp_i2c12, blsp10_spi, NA, + qdss_stm29, NA, NA, NA), + PINGROUP(89, tsif1_clk, qdss_stm28, qdss_tracedata_a, NA, NA, NA, NA, + NA, NA), + PINGROUP(90, tsif1_en, blsp1_spi, qdss_tracedata_a, NA, NA, NA, NA, NA, + NA), + PINGROUP(91, tsif1_data, sdc4_cmd, qdss_stm27, qdss_traceclk_b, NA, NA, + NA, NA, NA), + PINGROUP(92, tsif2_error, sdc43, vfr_1, qdss_stm26, qdss_tracedata_b, + NA, NA, NA, NA), + PINGROUP(93, tsif2_clk, sdc4_clk, NA, qdss_stm24, qdss_tracedata_b, NA, + NA, NA, NA), + PINGROUP(94, tsif2_en, sdc42, NA, qdss_stm23, qdss_tracectl_b, NA, NA, + NA, NA), + PINGROUP(95, tsif2_data, sdc41, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(96, tsif2_sync, sdc40, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(97, NA, NA, mdp_vsync_p_b, ldo_en, NA, NA, NA, NA, NA), + PINGROUP(98, NA, NA, mdp_vsync_s_b, ldo_update, NA, NA, NA, NA, NA), + PINGROUP(99, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(100, NA, NA, blsp11_uart_tx_b, qdss_cti, NA, NA, NA, NA, NA), + PINGROUP(101, NA, blsp11_uart_rx_b, qdss_cti, NA, NA, NA, NA, NA, NA), + PINGROUP(102, NA, blsp11_i2c_sda_b, prng_rosc, NA, NA, NA, NA, NA, NA), + PINGROUP(103, NA, blsp11_i2c_scl_b, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(104, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(105, uim2, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(106, uim2, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(107, uim2, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(108, uim2, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(109, uim1, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(110, uim1, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(111, uim1, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(112, uim1, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(113, uim_batt, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(114, NA, pci_e2, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(115, NA, pci_e2, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(116, NA, pa_indicator, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(117, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(118, adsp_ext, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(119, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(120, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(121, ddr_bist, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(122, ddr_bist, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(123, ddr_bist, qdss_tracedata_11, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(124, ddr_bist, qdss_tracedata_12, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(125, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(126, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(127, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(128, NA, modem_tsync, nav_dr, nav_pps, NA, NA, NA, NA, NA), + PINGROUP(129, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(130, pci_e1, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(131, pci_e1, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(132, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(133, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(134, gsm_tx, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(135, gsm_tx, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(136, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(137, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(138, NA, qspi_cs, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(139, NA, ssbi2, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(140, NA, ssbi1, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(141, NA, qspi_cs, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(142, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(143, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(144, mss_lte, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(145, mss_lte, qspi_clk, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(146, NA, qspi0, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(147, NA, qspi1, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(148, NA, qspi2, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(149, NA, qspi3, NA, NA, NA, NA, NA, NA, NA), + SDC_QDSD_PINGROUP(sdc1_clk, 0x12c000, 13, 6), + SDC_QDSD_PINGROUP(sdc1_cmd, 0x12c000, 11, 3), + SDC_QDSD_PINGROUP(sdc1_data, 0x12c000, 9, 0), + SDC_QDSD_PINGROUP(sdc2_clk, 0x12d000, 14, 6), + SDC_QDSD_PINGROUP(sdc2_cmd, 0x12d000, 11, 3), + SDC_QDSD_PINGROUP(sdc2_data, 0x12d000, 9, 0), + SDC_QDSD_PINGROUP(sdc1_rclk, 0x12c000, 15, 0), +}; + +static const struct msm_pinctrl_soc_data msm8996_pinctrl = { + .pins = msm8996_pins, + .npins = ARRAY_SIZE(msm8996_pins), + .functions = msm8996_functions, + .nfunctions = ARRAY_SIZE(msm8996_functions), + .groups = msm8996_groups, + .ngroups = ARRAY_SIZE(msm8996_groups), + .ngpios = 150, +}; + +static int msm8996_pinctrl_probe(struct platform_device *pdev) +{ + return msm_pinctrl_probe(pdev, &msm8996_pinctrl); +} + +static const struct of_device_id msm8996_pinctrl_of_match[] = { + { .compatible = "qcom,msm8996-pinctrl", }, + { } +}; + +static struct platform_driver msm8996_pinctrl_driver = { + .driver = { + .name = "msm8996-pinctrl", + .of_match_table = msm8996_pinctrl_of_match, + }, + .probe = msm8996_pinctrl_probe, + .remove = msm_pinctrl_remove, +}; + +static int __init msm8996_pinctrl_init(void) +{ + return platform_driver_register(&msm8996_pinctrl_driver); +} +arch_initcall(msm8996_pinctrl_init); + +static void __exit msm8996_pinctrl_exit(void) +{ + platform_driver_unregister(&msm8996_pinctrl_driver); +} +module_exit(msm8996_pinctrl_exit); + +MODULE_DESCRIPTION("Qualcomm msm8996 pinctrl driver"); +MODULE_LICENSE("GPL v2"); +MODULE_DEVICE_TABLE(of, msm8996_pinctrl_of_match); diff --git a/drivers/pinctrl/qcom/pinctrl-msm8998.c b/drivers/pinctrl/qcom/pinctrl-msm8998.c new file mode 100644 index 0000000000..b7cbf32b31 --- /dev/null +++ b/drivers/pinctrl/qcom/pinctrl-msm8998.c @@ -0,0 +1,1555 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2015-2016, The Linux Foundation. All rights reserved. + */ + +#include <linux/module.h> +#include <linux/of.h> +#include <linux/platform_device.h> + +#include "pinctrl-msm.h" + +#define NORTH 0x500000 +#define WEST 0x100000 +#define EAST 0x900000 + +#define PINGROUP(id, base, f1, f2, f3, f4, f5, f6, f7, f8, f9) \ + { \ + .grp = PINCTRL_PINGROUP("gpio" #id, \ + gpio##id##_pins, \ + ARRAY_SIZE(gpio##id##_pins)), \ + .funcs = (int[]){ \ + msm_mux_gpio, /* gpio mode */ \ + msm_mux_##f1, \ + msm_mux_##f2, \ + msm_mux_##f3, \ + msm_mux_##f4, \ + msm_mux_##f5, \ + msm_mux_##f6, \ + msm_mux_##f7, \ + msm_mux_##f8, \ + msm_mux_##f9 \ + }, \ + .nfuncs = 10, \ + .ctl_reg = base + 0x1000 * id, \ + .io_reg = base + 0x4 + 0x1000 * id, \ + .intr_cfg_reg = base + 0x8 + 0x1000 * id, \ + .intr_status_reg = base + 0xc + 0x1000 * id, \ + .intr_target_reg = base + 0x8 + 0x1000 * id, \ + .mux_bit = 2, \ + .pull_bit = 0, \ + .drv_bit = 6, \ + .oe_bit = 9, \ + .in_bit = 0, \ + .out_bit = 1, \ + .intr_enable_bit = 0, \ + .intr_status_bit = 0, \ + .intr_target_bit = 5, \ + .intr_target_kpss_val = 3, \ + .intr_raw_status_bit = 4, \ + .intr_polarity_bit = 1, \ + .intr_detection_bit = 2, \ + .intr_detection_width = 2, \ + } + +#define SDC_QDSD_PINGROUP(pg_name, ctl, pull, drv) \ + { \ + .grp = PINCTRL_PINGROUP(#pg_name, \ + pg_name##_pins, \ + ARRAY_SIZE(pg_name##_pins)), \ + .ctl_reg = ctl, \ + .io_reg = 0, \ + .intr_cfg_reg = 0, \ + .intr_status_reg = 0, \ + .intr_target_reg = 0, \ + .mux_bit = -1, \ + .pull_bit = pull, \ + .drv_bit = drv, \ + .oe_bit = -1, \ + .in_bit = -1, \ + .out_bit = -1, \ + .intr_enable_bit = -1, \ + .intr_status_bit = -1, \ + .intr_target_bit = -1, \ + .intr_raw_status_bit = -1, \ + .intr_polarity_bit = -1, \ + .intr_detection_bit = -1, \ + .intr_detection_width = -1, \ + } + +#define UFS_RESET(pg_name, offset) \ + { \ + .grp = PINCTRL_PINGROUP(#pg_name, \ + pg_name##_pins, \ + ARRAY_SIZE(pg_name##_pins)), \ + .ctl_reg = offset, \ + .io_reg = offset + 0x4, \ + .intr_cfg_reg = 0, \ + .intr_status_reg = 0, \ + .intr_target_reg = 0, \ + .mux_bit = -1, \ + .pull_bit = 3, \ + .drv_bit = 0, \ + .oe_bit = -1, \ + .in_bit = -1, \ + .out_bit = 0, \ + .intr_enable_bit = -1, \ + .intr_status_bit = -1, \ + .intr_target_bit = -1, \ + .intr_raw_status_bit = -1, \ + .intr_polarity_bit = -1, \ + .intr_detection_bit = -1, \ + .intr_detection_width = -1, \ + } + +static const struct pinctrl_pin_desc msm8998_pins[] = { + PINCTRL_PIN(0, "GPIO_0"), + PINCTRL_PIN(1, "GPIO_1"), + PINCTRL_PIN(2, "GPIO_2"), + PINCTRL_PIN(3, "GPIO_3"), + PINCTRL_PIN(4, "GPIO_4"), + PINCTRL_PIN(5, "GPIO_5"), + PINCTRL_PIN(6, "GPIO_6"), + PINCTRL_PIN(7, "GPIO_7"), + PINCTRL_PIN(8, "GPIO_8"), + PINCTRL_PIN(9, "GPIO_9"), + PINCTRL_PIN(10, "GPIO_10"), + PINCTRL_PIN(11, "GPIO_11"), + PINCTRL_PIN(12, "GPIO_12"), + PINCTRL_PIN(13, "GPIO_13"), + PINCTRL_PIN(14, "GPIO_14"), + PINCTRL_PIN(15, "GPIO_15"), + PINCTRL_PIN(16, "GPIO_16"), + PINCTRL_PIN(17, "GPIO_17"), + PINCTRL_PIN(18, "GPIO_18"), + PINCTRL_PIN(19, "GPIO_19"), + PINCTRL_PIN(20, "GPIO_20"), + PINCTRL_PIN(21, "GPIO_21"), + PINCTRL_PIN(22, "GPIO_22"), + PINCTRL_PIN(23, "GPIO_23"), + PINCTRL_PIN(24, "GPIO_24"), + PINCTRL_PIN(25, "GPIO_25"), + PINCTRL_PIN(26, "GPIO_26"), + PINCTRL_PIN(27, "GPIO_27"), + PINCTRL_PIN(28, "GPIO_28"), + PINCTRL_PIN(29, "GPIO_29"), + PINCTRL_PIN(30, "GPIO_30"), + PINCTRL_PIN(31, "GPIO_31"), + PINCTRL_PIN(32, "GPIO_32"), + PINCTRL_PIN(33, "GPIO_33"), + PINCTRL_PIN(34, "GPIO_34"), + PINCTRL_PIN(35, "GPIO_35"), + PINCTRL_PIN(36, "GPIO_36"), + PINCTRL_PIN(37, "GPIO_37"), + PINCTRL_PIN(38, "GPIO_38"), + PINCTRL_PIN(39, "GPIO_39"), + PINCTRL_PIN(40, "GPIO_40"), + PINCTRL_PIN(41, "GPIO_41"), + PINCTRL_PIN(42, "GPIO_42"), + PINCTRL_PIN(43, "GPIO_43"), + PINCTRL_PIN(44, "GPIO_44"), + PINCTRL_PIN(45, "GPIO_45"), + PINCTRL_PIN(46, "GPIO_46"), + PINCTRL_PIN(47, "GPIO_47"), + PINCTRL_PIN(48, "GPIO_48"), + PINCTRL_PIN(49, "GPIO_49"), + PINCTRL_PIN(50, "GPIO_50"), + PINCTRL_PIN(51, "GPIO_51"), + PINCTRL_PIN(52, "GPIO_52"), + PINCTRL_PIN(53, "GPIO_53"), + PINCTRL_PIN(54, "GPIO_54"), + PINCTRL_PIN(55, "GPIO_55"), + PINCTRL_PIN(56, "GPIO_56"), + PINCTRL_PIN(57, "GPIO_57"), + PINCTRL_PIN(58, "GPIO_58"), + PINCTRL_PIN(59, "GPIO_59"), + PINCTRL_PIN(60, "GPIO_60"), + PINCTRL_PIN(61, "GPIO_61"), + PINCTRL_PIN(62, "GPIO_62"), + PINCTRL_PIN(63, "GPIO_63"), + PINCTRL_PIN(64, "GPIO_64"), + PINCTRL_PIN(65, "GPIO_65"), + PINCTRL_PIN(66, "GPIO_66"), + PINCTRL_PIN(67, "GPIO_67"), + PINCTRL_PIN(68, "GPIO_68"), + PINCTRL_PIN(69, "GPIO_69"), + PINCTRL_PIN(70, "GPIO_70"), + PINCTRL_PIN(71, "GPIO_71"), + PINCTRL_PIN(72, "GPIO_72"), + PINCTRL_PIN(73, "GPIO_73"), + PINCTRL_PIN(74, "GPIO_74"), + PINCTRL_PIN(75, "GPIO_75"), + PINCTRL_PIN(76, "GPIO_76"), + PINCTRL_PIN(77, "GPIO_77"), + PINCTRL_PIN(78, "GPIO_78"), + PINCTRL_PIN(79, "GPIO_79"), + PINCTRL_PIN(80, "GPIO_80"), + PINCTRL_PIN(81, "GPIO_81"), + PINCTRL_PIN(82, "GPIO_82"), + PINCTRL_PIN(83, "GPIO_83"), + PINCTRL_PIN(84, "GPIO_84"), + PINCTRL_PIN(85, "GPIO_85"), + PINCTRL_PIN(86, "GPIO_86"), + PINCTRL_PIN(87, "GPIO_87"), + PINCTRL_PIN(88, "GPIO_88"), + PINCTRL_PIN(89, "GPIO_89"), + PINCTRL_PIN(90, "GPIO_90"), + PINCTRL_PIN(91, "GPIO_91"), + PINCTRL_PIN(92, "GPIO_92"), + PINCTRL_PIN(93, "GPIO_93"), + PINCTRL_PIN(94, "GPIO_94"), + PINCTRL_PIN(95, "GPIO_95"), + PINCTRL_PIN(96, "GPIO_96"), + PINCTRL_PIN(97, "GPIO_97"), + PINCTRL_PIN(98, "GPIO_98"), + PINCTRL_PIN(99, "GPIO_99"), + PINCTRL_PIN(100, "GPIO_100"), + PINCTRL_PIN(101, "GPIO_101"), + PINCTRL_PIN(102, "GPIO_102"), + PINCTRL_PIN(103, "GPIO_103"), + PINCTRL_PIN(104, "GPIO_104"), + PINCTRL_PIN(105, "GPIO_105"), + PINCTRL_PIN(106, "GPIO_106"), + PINCTRL_PIN(107, "GPIO_107"), + PINCTRL_PIN(108, "GPIO_108"), + PINCTRL_PIN(109, "GPIO_109"), + PINCTRL_PIN(110, "GPIO_110"), + PINCTRL_PIN(111, "GPIO_111"), + PINCTRL_PIN(112, "GPIO_112"), + PINCTRL_PIN(113, "GPIO_113"), + PINCTRL_PIN(114, "GPIO_114"), + PINCTRL_PIN(115, "GPIO_115"), + PINCTRL_PIN(116, "GPIO_116"), + PINCTRL_PIN(117, "GPIO_117"), + PINCTRL_PIN(118, "GPIO_118"), + PINCTRL_PIN(119, "GPIO_119"), + PINCTRL_PIN(120, "GPIO_120"), + PINCTRL_PIN(121, "GPIO_121"), + PINCTRL_PIN(122, "GPIO_122"), + PINCTRL_PIN(123, "GPIO_123"), + PINCTRL_PIN(124, "GPIO_124"), + PINCTRL_PIN(125, "GPIO_125"), + PINCTRL_PIN(126, "GPIO_126"), + PINCTRL_PIN(127, "GPIO_127"), + PINCTRL_PIN(128, "GPIO_128"), + PINCTRL_PIN(129, "GPIO_129"), + PINCTRL_PIN(130, "GPIO_130"), + PINCTRL_PIN(131, "GPIO_131"), + PINCTRL_PIN(132, "GPIO_132"), + PINCTRL_PIN(133, "GPIO_133"), + PINCTRL_PIN(134, "GPIO_134"), + PINCTRL_PIN(135, "GPIO_135"), + PINCTRL_PIN(136, "GPIO_136"), + PINCTRL_PIN(137, "GPIO_137"), + PINCTRL_PIN(138, "GPIO_138"), + PINCTRL_PIN(139, "GPIO_139"), + PINCTRL_PIN(140, "GPIO_140"), + PINCTRL_PIN(141, "GPIO_141"), + PINCTRL_PIN(142, "GPIO_142"), + PINCTRL_PIN(143, "GPIO_143"), + PINCTRL_PIN(144, "GPIO_144"), + PINCTRL_PIN(145, "GPIO_145"), + PINCTRL_PIN(146, "GPIO_146"), + PINCTRL_PIN(147, "GPIO_147"), + PINCTRL_PIN(148, "GPIO_148"), + PINCTRL_PIN(149, "GPIO_149"), + PINCTRL_PIN(150, "SDC2_CLK"), + PINCTRL_PIN(151, "SDC2_CMD"), + PINCTRL_PIN(152, "SDC2_DATA"), + PINCTRL_PIN(153, "UFS_RESET"), +}; + +#define DECLARE_MSM_GPIO_PINS(pin) \ + static const unsigned int gpio##pin##_pins[] = { pin } +DECLARE_MSM_GPIO_PINS(0); +DECLARE_MSM_GPIO_PINS(1); +DECLARE_MSM_GPIO_PINS(2); +DECLARE_MSM_GPIO_PINS(3); +DECLARE_MSM_GPIO_PINS(4); +DECLARE_MSM_GPIO_PINS(5); +DECLARE_MSM_GPIO_PINS(6); +DECLARE_MSM_GPIO_PINS(7); +DECLARE_MSM_GPIO_PINS(8); +DECLARE_MSM_GPIO_PINS(9); +DECLARE_MSM_GPIO_PINS(10); +DECLARE_MSM_GPIO_PINS(11); +DECLARE_MSM_GPIO_PINS(12); +DECLARE_MSM_GPIO_PINS(13); +DECLARE_MSM_GPIO_PINS(14); +DECLARE_MSM_GPIO_PINS(15); +DECLARE_MSM_GPIO_PINS(16); +DECLARE_MSM_GPIO_PINS(17); +DECLARE_MSM_GPIO_PINS(18); +DECLARE_MSM_GPIO_PINS(19); +DECLARE_MSM_GPIO_PINS(20); +DECLARE_MSM_GPIO_PINS(21); +DECLARE_MSM_GPIO_PINS(22); +DECLARE_MSM_GPIO_PINS(23); +DECLARE_MSM_GPIO_PINS(24); +DECLARE_MSM_GPIO_PINS(25); +DECLARE_MSM_GPIO_PINS(26); +DECLARE_MSM_GPIO_PINS(27); +DECLARE_MSM_GPIO_PINS(28); +DECLARE_MSM_GPIO_PINS(29); +DECLARE_MSM_GPIO_PINS(30); +DECLARE_MSM_GPIO_PINS(31); +DECLARE_MSM_GPIO_PINS(32); +DECLARE_MSM_GPIO_PINS(33); +DECLARE_MSM_GPIO_PINS(34); +DECLARE_MSM_GPIO_PINS(35); +DECLARE_MSM_GPIO_PINS(36); +DECLARE_MSM_GPIO_PINS(37); +DECLARE_MSM_GPIO_PINS(38); +DECLARE_MSM_GPIO_PINS(39); +DECLARE_MSM_GPIO_PINS(40); +DECLARE_MSM_GPIO_PINS(41); +DECLARE_MSM_GPIO_PINS(42); +DECLARE_MSM_GPIO_PINS(43); +DECLARE_MSM_GPIO_PINS(44); +DECLARE_MSM_GPIO_PINS(45); +DECLARE_MSM_GPIO_PINS(46); +DECLARE_MSM_GPIO_PINS(47); +DECLARE_MSM_GPIO_PINS(48); +DECLARE_MSM_GPIO_PINS(49); +DECLARE_MSM_GPIO_PINS(50); +DECLARE_MSM_GPIO_PINS(51); +DECLARE_MSM_GPIO_PINS(52); +DECLARE_MSM_GPIO_PINS(53); +DECLARE_MSM_GPIO_PINS(54); +DECLARE_MSM_GPIO_PINS(55); +DECLARE_MSM_GPIO_PINS(56); +DECLARE_MSM_GPIO_PINS(57); +DECLARE_MSM_GPIO_PINS(58); +DECLARE_MSM_GPIO_PINS(59); +DECLARE_MSM_GPIO_PINS(60); +DECLARE_MSM_GPIO_PINS(61); +DECLARE_MSM_GPIO_PINS(62); +DECLARE_MSM_GPIO_PINS(63); +DECLARE_MSM_GPIO_PINS(64); +DECLARE_MSM_GPIO_PINS(65); +DECLARE_MSM_GPIO_PINS(66); +DECLARE_MSM_GPIO_PINS(67); +DECLARE_MSM_GPIO_PINS(68); +DECLARE_MSM_GPIO_PINS(69); +DECLARE_MSM_GPIO_PINS(70); +DECLARE_MSM_GPIO_PINS(71); +DECLARE_MSM_GPIO_PINS(72); +DECLARE_MSM_GPIO_PINS(73); +DECLARE_MSM_GPIO_PINS(74); +DECLARE_MSM_GPIO_PINS(75); +DECLARE_MSM_GPIO_PINS(76); +DECLARE_MSM_GPIO_PINS(77); +DECLARE_MSM_GPIO_PINS(78); +DECLARE_MSM_GPIO_PINS(79); +DECLARE_MSM_GPIO_PINS(80); +DECLARE_MSM_GPIO_PINS(81); +DECLARE_MSM_GPIO_PINS(82); +DECLARE_MSM_GPIO_PINS(83); +DECLARE_MSM_GPIO_PINS(84); +DECLARE_MSM_GPIO_PINS(85); +DECLARE_MSM_GPIO_PINS(86); +DECLARE_MSM_GPIO_PINS(87); +DECLARE_MSM_GPIO_PINS(88); +DECLARE_MSM_GPIO_PINS(89); +DECLARE_MSM_GPIO_PINS(90); +DECLARE_MSM_GPIO_PINS(91); +DECLARE_MSM_GPIO_PINS(92); +DECLARE_MSM_GPIO_PINS(93); +DECLARE_MSM_GPIO_PINS(94); +DECLARE_MSM_GPIO_PINS(95); +DECLARE_MSM_GPIO_PINS(96); +DECLARE_MSM_GPIO_PINS(97); +DECLARE_MSM_GPIO_PINS(98); +DECLARE_MSM_GPIO_PINS(99); +DECLARE_MSM_GPIO_PINS(100); +DECLARE_MSM_GPIO_PINS(101); +DECLARE_MSM_GPIO_PINS(102); +DECLARE_MSM_GPIO_PINS(103); +DECLARE_MSM_GPIO_PINS(104); +DECLARE_MSM_GPIO_PINS(105); +DECLARE_MSM_GPIO_PINS(106); +DECLARE_MSM_GPIO_PINS(107); +DECLARE_MSM_GPIO_PINS(108); +DECLARE_MSM_GPIO_PINS(109); +DECLARE_MSM_GPIO_PINS(110); +DECLARE_MSM_GPIO_PINS(111); +DECLARE_MSM_GPIO_PINS(112); +DECLARE_MSM_GPIO_PINS(113); +DECLARE_MSM_GPIO_PINS(114); +DECLARE_MSM_GPIO_PINS(115); +DECLARE_MSM_GPIO_PINS(116); +DECLARE_MSM_GPIO_PINS(117); +DECLARE_MSM_GPIO_PINS(118); +DECLARE_MSM_GPIO_PINS(119); +DECLARE_MSM_GPIO_PINS(120); +DECLARE_MSM_GPIO_PINS(121); +DECLARE_MSM_GPIO_PINS(122); +DECLARE_MSM_GPIO_PINS(123); +DECLARE_MSM_GPIO_PINS(124); +DECLARE_MSM_GPIO_PINS(125); +DECLARE_MSM_GPIO_PINS(126); +DECLARE_MSM_GPIO_PINS(127); +DECLARE_MSM_GPIO_PINS(128); +DECLARE_MSM_GPIO_PINS(129); +DECLARE_MSM_GPIO_PINS(130); +DECLARE_MSM_GPIO_PINS(131); +DECLARE_MSM_GPIO_PINS(132); +DECLARE_MSM_GPIO_PINS(133); +DECLARE_MSM_GPIO_PINS(134); +DECLARE_MSM_GPIO_PINS(135); +DECLARE_MSM_GPIO_PINS(136); +DECLARE_MSM_GPIO_PINS(137); +DECLARE_MSM_GPIO_PINS(138); +DECLARE_MSM_GPIO_PINS(139); +DECLARE_MSM_GPIO_PINS(140); +DECLARE_MSM_GPIO_PINS(141); +DECLARE_MSM_GPIO_PINS(142); +DECLARE_MSM_GPIO_PINS(143); +DECLARE_MSM_GPIO_PINS(144); +DECLARE_MSM_GPIO_PINS(145); +DECLARE_MSM_GPIO_PINS(146); +DECLARE_MSM_GPIO_PINS(147); +DECLARE_MSM_GPIO_PINS(148); +DECLARE_MSM_GPIO_PINS(149); + +static const unsigned int sdc2_clk_pins[] = { 150 }; +static const unsigned int sdc2_cmd_pins[] = { 151 }; +static const unsigned int sdc2_data_pins[] = { 152 }; +static const unsigned int ufs_reset_pins[] = { 153 }; + +enum msm8998_functions { + msm_mux_adsp_ext, + msm_mux_agera_pll, + msm_mux_atest_char, + msm_mux_atest_gpsadc0, + msm_mux_atest_gpsadc1, + msm_mux_atest_tsens, + msm_mux_atest_tsens2, + msm_mux_atest_usb1, + msm_mux_atest_usb10, + msm_mux_atest_usb11, + msm_mux_atest_usb12, + msm_mux_atest_usb13, + msm_mux_audio_ref, + msm_mux_bimc_dte0, + msm_mux_bimc_dte1, + msm_mux_blsp10_spi, + msm_mux_blsp10_spi_a, + msm_mux_blsp10_spi_b, + msm_mux_blsp11_i2c, + msm_mux_blsp1_spi, + msm_mux_blsp1_spi_a, + msm_mux_blsp1_spi_b, + msm_mux_blsp2_spi, + msm_mux_blsp9_spi, + msm_mux_blsp_i2c1, + msm_mux_blsp_i2c10, + msm_mux_blsp_i2c11, + msm_mux_blsp_i2c12, + msm_mux_blsp_i2c2, + msm_mux_blsp_i2c3, + msm_mux_blsp_i2c4, + msm_mux_blsp_i2c5, + msm_mux_blsp_i2c6, + msm_mux_blsp_i2c7, + msm_mux_blsp_i2c8, + msm_mux_blsp_i2c9, + msm_mux_blsp_spi1, + msm_mux_blsp_spi10, + msm_mux_blsp_spi11, + msm_mux_blsp_spi12, + msm_mux_blsp_spi2, + msm_mux_blsp_spi3, + msm_mux_blsp_spi4, + msm_mux_blsp_spi5, + msm_mux_blsp_spi6, + msm_mux_blsp_spi7, + msm_mux_blsp_spi8, + msm_mux_blsp_spi9, + msm_mux_blsp_uart1_a, + msm_mux_blsp_uart1_b, + msm_mux_blsp_uart2_a, + msm_mux_blsp_uart2_b, + msm_mux_blsp_uart3_a, + msm_mux_blsp_uart3_b, + msm_mux_blsp_uart7_a, + msm_mux_blsp_uart7_b, + msm_mux_blsp_uart8, + msm_mux_blsp_uart8_a, + msm_mux_blsp_uart8_b, + msm_mux_blsp_uart9_a, + msm_mux_blsp_uart9_b, + msm_mux_blsp_uim1_a, + msm_mux_blsp_uim1_b, + msm_mux_blsp_uim2_a, + msm_mux_blsp_uim2_b, + msm_mux_blsp_uim3_a, + msm_mux_blsp_uim3_b, + msm_mux_blsp_uim7_a, + msm_mux_blsp_uim7_b, + msm_mux_blsp_uim8_a, + msm_mux_blsp_uim8_b, + msm_mux_blsp_uim9_a, + msm_mux_blsp_uim9_b, + msm_mux_bt_reset, + msm_mux_btfm_slimbus, + msm_mux_cam_mclk, + msm_mux_cci_async, + msm_mux_cci_i2c, + msm_mux_cci_timer0, + msm_mux_cci_timer1, + msm_mux_cci_timer2, + msm_mux_cci_timer3, + msm_mux_cci_timer4, + msm_mux_cri_trng, + msm_mux_cri_trng0, + msm_mux_cri_trng1, + msm_mux_dbg_out, + msm_mux_ddr_bist, + msm_mux_edp_hot, + msm_mux_edp_lcd, + msm_mux_gcc_gp1_a, + msm_mux_gcc_gp1_b, + msm_mux_gcc_gp2_a, + msm_mux_gcc_gp2_b, + msm_mux_gcc_gp3_a, + msm_mux_gcc_gp3_b, + msm_mux_gpio, + msm_mux_hdmi_cec, + msm_mux_hdmi_ddc, + msm_mux_hdmi_hot, + msm_mux_hdmi_rcv, + msm_mux_isense_dbg, + msm_mux_jitter_bist, + msm_mux_ldo_en, + msm_mux_ldo_update, + msm_mux_lpass_slimbus, + msm_mux_m_voc, + msm_mux_mdp_vsync, + msm_mux_mdp_vsync0, + msm_mux_mdp_vsync1, + msm_mux_mdp_vsync2, + msm_mux_mdp_vsync3, + msm_mux_mdp_vsync_a, + msm_mux_mdp_vsync_b, + msm_mux_modem_tsync, + msm_mux_mss_lte, + msm_mux_nav_dr, + msm_mux_nav_pps, + msm_mux_pa_indicator, + msm_mux_pci_e0, + msm_mux_phase_flag, + msm_mux_pll_bypassnl, + msm_mux_pll_reset, + msm_mux_pri_mi2s, + msm_mux_pri_mi2s_ws, + msm_mux_prng_rosc, + msm_mux_pwr_crypto, + msm_mux_pwr_modem, + msm_mux_pwr_nav, + msm_mux_qdss_cti0_a, + msm_mux_qdss_cti0_b, + msm_mux_qdss_cti1_a, + msm_mux_qdss_cti1_b, + msm_mux_qdss, + msm_mux_qlink_enable, + msm_mux_qlink_request, + msm_mux_qua_mi2s, + msm_mux_sd_card, + msm_mux_sd_write, + msm_mux_sdc40, + msm_mux_sdc41, + msm_mux_sdc42, + msm_mux_sdc43, + msm_mux_sdc4_clk, + msm_mux_sdc4_cmd, + msm_mux_sec_mi2s, + msm_mux_sp_cmu, + msm_mux_spkr_i2s, + msm_mux_ssbi1, + msm_mux_ssc_irq, + msm_mux_ter_mi2s, + msm_mux_tgu_ch0, + msm_mux_tgu_ch1, + msm_mux_tsense_pwm1, + msm_mux_tsense_pwm2, + msm_mux_tsif0, + msm_mux_tsif1, + msm_mux_uim1_clk, + msm_mux_uim1_data, + msm_mux_uim1_present, + msm_mux_uim1_reset, + msm_mux_uim2_clk, + msm_mux_uim2_data, + msm_mux_uim2_present, + msm_mux_uim2_reset, + msm_mux_uim_batt, + msm_mux_usb_phy, + msm_mux_vfr_1, + msm_mux_vsense_clkout, + msm_mux_vsense_data0, + msm_mux_vsense_data1, + msm_mux_vsense_mode, + msm_mux_wlan1_adc0, + msm_mux_wlan1_adc1, + msm_mux_wlan2_adc0, + msm_mux_wlan2_adc1, + msm_mux__, +}; + +static const char * const gpio_groups[] = { + "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7", + "gpio8", "gpio9", "gpio10", "gpio11", "gpio12", "gpio13", "gpio14", + "gpio15", "gpio16", "gpio17", "gpio18", "gpio19", "gpio20", "gpio21", + "gpio22", "gpio23", "gpio24", "gpio25", "gpio26", "gpio27", "gpio28", + "gpio29", "gpio30", "gpio31", "gpio32", "gpio33", "gpio34", "gpio35", + "gpio36", "gpio37", "gpio38", "gpio39", "gpio40", "gpio41", "gpio42", + "gpio43", "gpio44", "gpio45", "gpio46", "gpio47", "gpio48", "gpio49", + "gpio50", "gpio51", "gpio52", "gpio53", "gpio54", "gpio55", "gpio56", + "gpio57", "gpio58", "gpio59", "gpio60", "gpio61", "gpio62", "gpio63", + "gpio64", "gpio65", "gpio66", "gpio67", "gpio68", "gpio69", "gpio70", + "gpio71", "gpio72", "gpio73", "gpio74", "gpio75", "gpio76", "gpio77", + "gpio78", "gpio79", "gpio80", "gpio81", "gpio82", "gpio83", "gpio84", + "gpio85", "gpio86", "gpio87", "gpio88", "gpio89", "gpio90", "gpio91", + "gpio92", "gpio93", "gpio94", "gpio95", "gpio96", "gpio97", "gpio98", + "gpio99", "gpio100", "gpio101", "gpio102", "gpio103", "gpio104", + "gpio105", "gpio106", "gpio107", "gpio108", "gpio109", "gpio110", + "gpio111", "gpio112", "gpio113", "gpio114", "gpio115", "gpio116", + "gpio117", "gpio118", "gpio119", "gpio120", "gpio121", "gpio122", + "gpio123", "gpio124", "gpio125", "gpio126", "gpio127", "gpio128", + "gpio129", "gpio130", "gpio131", "gpio132", "gpio133", "gpio134", + "gpio135", "gpio136", "gpio137", "gpio138", "gpio139", "gpio140", + "gpio141", "gpio142", "gpio143", "gpio144", "gpio145", "gpio146", + "gpio147", "gpio148", "gpio149", +}; +static const char * const blsp_spi1_groups[] = { + "gpio0", "gpio1", "gpio2", "gpio3", +}; +static const char * const blsp_uim1_a_groups[] = { + "gpio0", "gpio1", +}; +static const char * const blsp_uart1_a_groups[] = { + "gpio0", "gpio1", "gpio2", "gpio3", +}; +static const char * const blsp_i2c1_groups[] = { + "gpio2", "gpio3", +}; +static const char * const blsp_spi8_groups[] = { + "gpio4", "gpio5", "gpio6", "gpio7", +}; +static const char * const blsp_uart8_a_groups[] = { + "gpio4", "gpio5", "gpio6", "gpio7", +}; +static const char * const blsp_uim8_a_groups[] = { + "gpio4", "gpio5", +}; +static const char * const qdss_cti0_b_groups[] = { + "gpio4", "gpio5", +}; +static const char * const blsp_i2c8_groups[] = { + "gpio6", "gpio7", +}; +static const char * const ddr_bist_groups[] = { + "gpio7", "gpio8", "gpio9", "gpio10", +}; +static const char * const atest_tsens2_groups[] = { + "gpio7", +}; +static const char * const atest_usb1_groups[] = { + "gpio7", +}; +static const char * const blsp_spi4_groups[] = { + "gpio8", "gpio9", "gpio10", "gpio11", +}; +static const char * const blsp_uart1_b_groups[] = { + "gpio8", "gpio9", "gpio10", "gpio11", +}; +static const char * const blsp_uim1_b_groups[] = { + "gpio8", "gpio9", +}; +static const char * const wlan1_adc1_groups[] = { + "gpio8", +}; +static const char * const atest_usb13_groups[] = { + "gpio8", +}; +static const char * const bimc_dte1_groups[] = { + "gpio8", "gpio10", +}; +static const char * const wlan1_adc0_groups[] = { + "gpio9", +}; +static const char * const atest_usb12_groups[] = { + "gpio9", +}; +static const char * const bimc_dte0_groups[] = { + "gpio9", "gpio11", +}; +static const char * const mdp_vsync_a_groups[] = { + "gpio10", "gpio11", +}; +static const char * const blsp_i2c4_groups[] = { + "gpio10", "gpio11", +}; +static const char * const atest_gpsadc1_groups[] = { + "gpio10", +}; +static const char * const wlan2_adc1_groups[] = { + "gpio10", +}; +static const char * const atest_usb11_groups[] = { + "gpio10", +}; +static const char * const edp_lcd_groups[] = { + "gpio11", +}; +static const char * const dbg_out_groups[] = { + "gpio11", +}; +static const char * const atest_gpsadc0_groups[] = { + "gpio11", +}; +static const char * const wlan2_adc0_groups[] = { + "gpio11", +}; +static const char * const atest_usb10_groups[] = { + "gpio11", +}; +static const char * const mdp_vsync_groups[] = { + "gpio12", +}; +static const char * const m_voc_groups[] = { + "gpio12", +}; +static const char * const cam_mclk_groups[] = { + "gpio13", "gpio14", "gpio15", "gpio16", +}; +static const char * const pll_bypassnl_groups[] = { + "gpio13", +}; +static const char * const qdss_groups[] = { + "gpio13", "gpio14", "gpio15", "gpio16", "gpio17", "gpio18", "gpio19", + "gpio20", "gpio21", "gpio22", "gpio23", "gpio24", "gpio25", "gpio26", + "gpio27", "gpio28", "gpio29", "gpio30", "gpio41", "gpio42", "gpio43", + "gpio44", "gpio75", "gpio76", "gpio77", "gpio79", "gpio80", "gpio93", + "gpio117", "gpio118", "gpio119", "gpio120", "gpio121", "gpio122", + "gpio123", "gpio124", +}; +static const char * const pll_reset_groups[] = { + "gpio14", +}; +static const char * const cci_i2c_groups[] = { + "gpio17", "gpio18", "gpio19", "gpio20", +}; +static const char * const phase_flag_groups[] = { + "gpio18", "gpio19", "gpio73", "gpio74", "gpio75", "gpio76", "gpio77", + "gpio89", "gpio91", "gpio92", "gpio96", "gpio114", "gpio115", + "gpio116", "gpio117", "gpio118", "gpio119", "gpio120", "gpio121", + "gpio122", "gpio123", "gpio124", "gpio125", "gpio126", "gpio128", + "gpio129", "gpio130", "gpio131", "gpio132", "gpio133", "gpio134", +}; +static const char * const cci_timer4_groups[] = { + "gpio25", +}; +static const char * const blsp2_spi_groups[] = { + "gpio25", "gpio29", "gpio30", +}; +static const char * const cci_timer0_groups[] = { + "gpio21", +}; +static const char * const vsense_data0_groups[] = { + "gpio21", +}; +static const char * const cci_timer1_groups[] = { + "gpio22", +}; +static const char * const vsense_data1_groups[] = { + "gpio22", +}; +static const char * const cci_timer2_groups[] = { + "gpio23", +}; +static const char * const blsp1_spi_b_groups[] = { + "gpio23", "gpio28", +}; +static const char * const vsense_mode_groups[] = { + "gpio23", +}; +static const char * const cci_timer3_groups[] = { + "gpio24", +}; +static const char * const cci_async_groups[] = { + "gpio24", "gpio25", "gpio26", +}; +static const char * const blsp1_spi_a_groups[] = { + "gpio24", "gpio27", +}; +static const char * const vsense_clkout_groups[] = { + "gpio24", +}; +static const char * const hdmi_rcv_groups[] = { + "gpio30", +}; +static const char * const hdmi_cec_groups[] = { + "gpio31", +}; +static const char * const blsp_spi2_groups[] = { + "gpio31", "gpio32", "gpio33", "gpio34", +}; +static const char * const blsp_uart2_a_groups[] = { + "gpio31", "gpio32", "gpio33", "gpio34", +}; +static const char * const blsp_uim2_a_groups[] = { + "gpio31", "gpio34", +}; +static const char * const pwr_modem_groups[] = { + "gpio31", +}; +static const char * const hdmi_ddc_groups[] = { + "gpio32", "gpio33", +}; +static const char * const blsp_i2c2_groups[] = { + "gpio32", "gpio33", +}; +static const char * const pwr_nav_groups[] = { + "gpio32", +}; +static const char * const pwr_crypto_groups[] = { + "gpio33", +}; +static const char * const hdmi_hot_groups[] = { + "gpio34", +}; +static const char * const edp_hot_groups[] = { + "gpio34", +}; +static const char * const pci_e0_groups[] = { + "gpio35", "gpio36", "gpio37", +}; +static const char * const jitter_bist_groups[] = { + "gpio35", +}; +static const char * const agera_pll_groups[] = { + "gpio36", "gpio37", +}; +static const char * const atest_tsens_groups[] = { + "gpio36", +}; +static const char * const usb_phy_groups[] = { + "gpio38", +}; +static const char * const lpass_slimbus_groups[] = { + "gpio39", "gpio70", "gpio71", "gpio72", +}; +static const char * const sd_write_groups[] = { + "gpio40", +}; +static const char * const blsp_spi6_groups[] = { + "gpio41", "gpio42", "gpio43", "gpio44", +}; +static const char * const blsp_uart3_b_groups[] = { + "gpio41", "gpio42", "gpio43", "gpio44", +}; +static const char * const blsp_uim3_b_groups[] = { + "gpio41", "gpio42", +}; +static const char * const blsp_i2c6_groups[] = { + "gpio43", "gpio44", +}; +static const char * const bt_reset_groups[] = { + "gpio45", +}; +static const char * const blsp_spi3_groups[] = { + "gpio45", "gpio46", "gpio47", "gpio48", +}; +static const char * const blsp_uart3_a_groups[] = { + "gpio45", "gpio46", "gpio47", "gpio48", +}; +static const char * const blsp_uim3_a_groups[] = { + "gpio45", "gpio46", +}; +static const char * const blsp_i2c3_groups[] = { + "gpio47", "gpio48", +}; +static const char * const blsp_spi9_groups[] = { + "gpio49", "gpio50", "gpio51", "gpio52", +}; +static const char * const blsp_uart9_a_groups[] = { + "gpio49", "gpio50", "gpio51", "gpio52", +}; +static const char * const blsp_uim9_a_groups[] = { + "gpio49", "gpio50", +}; +static const char * const blsp10_spi_b_groups[] = { + "gpio49", "gpio50", +}; +static const char * const qdss_cti0_a_groups[] = { + "gpio49", "gpio50", +}; +static const char * const blsp_i2c9_groups[] = { + "gpio51", "gpio52", +}; +static const char * const blsp10_spi_a_groups[] = { + "gpio51", "gpio52", +}; +static const char * const blsp_spi7_groups[] = { + "gpio53", "gpio54", "gpio55", "gpio56", +}; +static const char * const blsp_uart7_a_groups[] = { + "gpio53", "gpio54", "gpio55", "gpio56", +}; +static const char * const blsp_uim7_a_groups[] = { + "gpio53", "gpio54", +}; +static const char * const blsp_i2c7_groups[] = { + "gpio55", "gpio56", +}; +static const char * const qua_mi2s_groups[] = { + "gpio57", "gpio58", "gpio59", "gpio60", "gpio61", "gpio62", "gpio63", +}; +static const char * const blsp10_spi_groups[] = { + "gpio57", +}; +static const char * const gcc_gp1_a_groups[] = { + "gpio57", +}; +static const char * const ssc_irq_groups[] = { + "gpio58", "gpio59", "gpio60", "gpio61", "gpio62", "gpio63", "gpio78", + "gpio79", "gpio80", "gpio117", "gpio118", "gpio119", "gpio120", + "gpio121", "gpio122", "gpio123", "gpio124", "gpio125", +}; +static const char * const blsp_spi11_groups[] = { + "gpio58", "gpio59", "gpio60", "gpio61", +}; +static const char * const blsp_uart8_b_groups[] = { + "gpio58", "gpio59", "gpio60", "gpio61", +}; +static const char * const blsp_uim8_b_groups[] = { + "gpio58", "gpio59", +}; +static const char * const gcc_gp2_a_groups[] = { + "gpio58", +}; +static const char * const qdss_cti1_a_groups[] = { + "gpio58", "gpio59", +}; +static const char * const gcc_gp3_a_groups[] = { + "gpio59", +}; +static const char * const blsp_i2c11_groups[] = { + "gpio60", "gpio61", +}; +static const char * const cri_trng0_groups[] = { + "gpio60", +}; +static const char * const cri_trng1_groups[] = { + "gpio61", +}; +static const char * const cri_trng_groups[] = { + "gpio62", +}; +static const char * const pri_mi2s_groups[] = { + "gpio64", "gpio65", "gpio67", "gpio68", +}; +static const char * const sp_cmu_groups[] = { + "gpio64", +}; +static const char * const blsp_spi10_groups[] = { + "gpio65", "gpio66", "gpio67", "gpio68", +}; +static const char * const blsp_uart7_b_groups[] = { + "gpio65", "gpio66", "gpio67", "gpio68", +}; +static const char * const blsp_uim7_b_groups[] = { + "gpio65", "gpio66", +}; +static const char * const pri_mi2s_ws_groups[] = { + "gpio66", +}; +static const char * const blsp_i2c10_groups[] = { + "gpio67", "gpio68", +}; +static const char * const spkr_i2s_groups[] = { + "gpio69", "gpio70", "gpio71", "gpio72", +}; +static const char * const audio_ref_groups[] = { + "gpio69", +}; +static const char * const blsp9_spi_groups[] = { + "gpio70", "gpio71", "gpio72", +}; +static const char * const tsense_pwm1_groups[] = { + "gpio71", +}; +static const char * const tsense_pwm2_groups[] = { + "gpio71", +}; +static const char * const btfm_slimbus_groups[] = { + "gpio73", "gpio74", +}; +static const char * const ter_mi2s_groups[] = { + "gpio74", "gpio75", "gpio76", "gpio77", "gpio78", +}; +static const char * const gcc_gp1_b_groups[] = { + "gpio78", +}; +static const char * const sec_mi2s_groups[] = { + "gpio79", "gpio80", "gpio81", "gpio82", "gpio83", +}; +static const char * const blsp_spi12_groups[] = { + "gpio81", "gpio82", "gpio83", "gpio84", +}; +static const char * const blsp_uart9_b_groups[] = { + "gpio81", "gpio82", "gpio83", "gpio84", +}; +static const char * const blsp_uim9_b_groups[] = { + "gpio81", "gpio82", +}; +static const char * const gcc_gp2_b_groups[] = { + "gpio81", +}; +static const char * const gcc_gp3_b_groups[] = { + "gpio82", +}; +static const char * const blsp_i2c12_groups[] = { + "gpio83", "gpio84", +}; +static const char * const blsp_spi5_groups[] = { + "gpio85", "gpio86", "gpio87", "gpio88", +}; +static const char * const blsp_uart2_b_groups[] = { + "gpio85", "gpio86", "gpio87", "gpio88", +}; +static const char * const blsp_uim2_b_groups[] = { + "gpio85", "gpio86", +}; +static const char * const blsp_i2c5_groups[] = { + "gpio87", "gpio88", +}; +static const char * const tsif0_groups[] = { + "gpio9", "gpio40", "gpio89", "gpio90", "gpio91", +}; +static const char * const mdp_vsync0_groups[] = { + "gpio90", +}; +static const char * const mdp_vsync1_groups[] = { + "gpio90", +}; +static const char * const mdp_vsync2_groups[] = { + "gpio90", +}; +static const char * const mdp_vsync3_groups[] = { + "gpio90", +}; +static const char * const blsp1_spi_groups[] = { + "gpio90", +}; +static const char * const tgu_ch0_groups[] = { + "gpio90", +}; +static const char * const qdss_cti1_b_groups[] = { + "gpio90", "gpio91", +}; +static const char * const sdc4_cmd_groups[] = { + "gpio91", +}; +static const char * const tgu_ch1_groups[] = { + "gpio91", +}; +static const char * const tsif1_groups[] = { + "gpio92", "gpio93", "gpio94", "gpio95", "gpio96", +}; +static const char * const sdc43_groups[] = { + "gpio92", +}; +static const char * const vfr_1_groups[] = { + "gpio92", +}; +static const char * const sdc4_clk_groups[] = { + "gpio93", +}; +static const char * const sdc42_groups[] = { + "gpio94", +}; +static const char * const sd_card_groups[] = { + "gpio95", +}; +static const char * const sdc41_groups[] = { + "gpio95", +}; +static const char * const sdc40_groups[] = { + "gpio96", +}; +static const char * const mdp_vsync_b_groups[] = { + "gpio97", "gpio98", +}; +static const char * const ldo_en_groups[] = { + "gpio97", +}; +static const char * const ldo_update_groups[] = { + "gpio98", +}; +static const char * const blsp_uart8_groups[] = { + "gpio100", "gpio101", +}; +static const char * const blsp11_i2c_groups[] = { + "gpio102", "gpio103", +}; +static const char * const prng_rosc_groups[] = { + "gpio102", +}; +static const char * const uim2_data_groups[] = { + "gpio105", +}; +static const char * const uim2_clk_groups[] = { + "gpio106", +}; +static const char * const uim2_reset_groups[] = { + "gpio107", +}; +static const char * const uim2_present_groups[] = { + "gpio108", +}; +static const char * const uim1_data_groups[] = { + "gpio109", +}; +static const char * const uim1_clk_groups[] = { + "gpio110", +}; +static const char * const uim1_reset_groups[] = { + "gpio111", +}; +static const char * const uim1_present_groups[] = { + "gpio112", +}; +static const char * const uim_batt_groups[] = { + "gpio113", +}; +static const char * const nav_dr_groups[] = { + "gpio115", +}; +static const char * const atest_char_groups[] = { + "gpio117", "gpio118", "gpio119", "gpio120", "gpio121", +}; +static const char * const adsp_ext_groups[] = { + "gpio118", +}; +static const char * const modem_tsync_groups[] = { + "gpio128", +}; +static const char * const nav_pps_groups[] = { + "gpio128", +}; +static const char * const qlink_request_groups[] = { + "gpio130", +}; +static const char * const qlink_enable_groups[] = { + "gpio131", +}; +static const char * const pa_indicator_groups[] = { + "gpio135", +}; +static const char * const ssbi1_groups[] = { + "gpio142", +}; +static const char * const isense_dbg_groups[] = { + "gpio143", +}; +static const char * const mss_lte_groups[] = { + "gpio144", "gpio145", +}; + +static const struct pinfunction msm8998_functions[] = { + MSM_PIN_FUNCTION(gpio), + MSM_PIN_FUNCTION(adsp_ext), + MSM_PIN_FUNCTION(agera_pll), + MSM_PIN_FUNCTION(atest_char), + MSM_PIN_FUNCTION(atest_gpsadc0), + MSM_PIN_FUNCTION(atest_gpsadc1), + MSM_PIN_FUNCTION(atest_tsens), + MSM_PIN_FUNCTION(atest_tsens2), + MSM_PIN_FUNCTION(atest_usb1), + MSM_PIN_FUNCTION(atest_usb10), + MSM_PIN_FUNCTION(atest_usb11), + MSM_PIN_FUNCTION(atest_usb12), + MSM_PIN_FUNCTION(atest_usb13), + MSM_PIN_FUNCTION(audio_ref), + MSM_PIN_FUNCTION(bimc_dte0), + MSM_PIN_FUNCTION(bimc_dte1), + MSM_PIN_FUNCTION(blsp10_spi), + MSM_PIN_FUNCTION(blsp10_spi_a), + MSM_PIN_FUNCTION(blsp10_spi_b), + MSM_PIN_FUNCTION(blsp11_i2c), + MSM_PIN_FUNCTION(blsp1_spi), + MSM_PIN_FUNCTION(blsp1_spi_a), + MSM_PIN_FUNCTION(blsp1_spi_b), + MSM_PIN_FUNCTION(blsp2_spi), + MSM_PIN_FUNCTION(blsp9_spi), + MSM_PIN_FUNCTION(blsp_i2c1), + MSM_PIN_FUNCTION(blsp_i2c2), + MSM_PIN_FUNCTION(blsp_i2c3), + MSM_PIN_FUNCTION(blsp_i2c4), + MSM_PIN_FUNCTION(blsp_i2c5), + MSM_PIN_FUNCTION(blsp_i2c6), + MSM_PIN_FUNCTION(blsp_i2c7), + MSM_PIN_FUNCTION(blsp_i2c8), + MSM_PIN_FUNCTION(blsp_i2c9), + MSM_PIN_FUNCTION(blsp_i2c10), + MSM_PIN_FUNCTION(blsp_i2c11), + MSM_PIN_FUNCTION(blsp_i2c12), + MSM_PIN_FUNCTION(blsp_spi1), + MSM_PIN_FUNCTION(blsp_spi2), + MSM_PIN_FUNCTION(blsp_spi3), + MSM_PIN_FUNCTION(blsp_spi4), + MSM_PIN_FUNCTION(blsp_spi5), + MSM_PIN_FUNCTION(blsp_spi6), + MSM_PIN_FUNCTION(blsp_spi7), + MSM_PIN_FUNCTION(blsp_spi8), + MSM_PIN_FUNCTION(blsp_spi9), + MSM_PIN_FUNCTION(blsp_spi10), + MSM_PIN_FUNCTION(blsp_spi11), + MSM_PIN_FUNCTION(blsp_spi12), + MSM_PIN_FUNCTION(blsp_uart1_a), + MSM_PIN_FUNCTION(blsp_uart1_b), + MSM_PIN_FUNCTION(blsp_uart2_a), + MSM_PIN_FUNCTION(blsp_uart2_b), + MSM_PIN_FUNCTION(blsp_uart3_a), + MSM_PIN_FUNCTION(blsp_uart3_b), + MSM_PIN_FUNCTION(blsp_uart7_a), + MSM_PIN_FUNCTION(blsp_uart7_b), + MSM_PIN_FUNCTION(blsp_uart8), + MSM_PIN_FUNCTION(blsp_uart8_a), + MSM_PIN_FUNCTION(blsp_uart8_b), + MSM_PIN_FUNCTION(blsp_uart9_a), + MSM_PIN_FUNCTION(blsp_uart9_b), + MSM_PIN_FUNCTION(blsp_uim1_a), + MSM_PIN_FUNCTION(blsp_uim1_b), + MSM_PIN_FUNCTION(blsp_uim2_a), + MSM_PIN_FUNCTION(blsp_uim2_b), + MSM_PIN_FUNCTION(blsp_uim3_a), + MSM_PIN_FUNCTION(blsp_uim3_b), + MSM_PIN_FUNCTION(blsp_uim7_a), + MSM_PIN_FUNCTION(blsp_uim7_b), + MSM_PIN_FUNCTION(blsp_uim8_a), + MSM_PIN_FUNCTION(blsp_uim8_b), + MSM_PIN_FUNCTION(blsp_uim9_a), + MSM_PIN_FUNCTION(blsp_uim9_b), + MSM_PIN_FUNCTION(bt_reset), + MSM_PIN_FUNCTION(btfm_slimbus), + MSM_PIN_FUNCTION(cam_mclk), + MSM_PIN_FUNCTION(cci_async), + MSM_PIN_FUNCTION(cci_i2c), + MSM_PIN_FUNCTION(cci_timer0), + MSM_PIN_FUNCTION(cci_timer1), + MSM_PIN_FUNCTION(cci_timer2), + MSM_PIN_FUNCTION(cci_timer3), + MSM_PIN_FUNCTION(cci_timer4), + MSM_PIN_FUNCTION(cri_trng), + MSM_PIN_FUNCTION(cri_trng0), + MSM_PIN_FUNCTION(cri_trng1), + MSM_PIN_FUNCTION(dbg_out), + MSM_PIN_FUNCTION(ddr_bist), + MSM_PIN_FUNCTION(edp_hot), + MSM_PIN_FUNCTION(edp_lcd), + MSM_PIN_FUNCTION(gcc_gp1_a), + MSM_PIN_FUNCTION(gcc_gp1_b), + MSM_PIN_FUNCTION(gcc_gp2_a), + MSM_PIN_FUNCTION(gcc_gp2_b), + MSM_PIN_FUNCTION(gcc_gp3_a), + MSM_PIN_FUNCTION(gcc_gp3_b), + MSM_PIN_FUNCTION(hdmi_cec), + MSM_PIN_FUNCTION(hdmi_ddc), + MSM_PIN_FUNCTION(hdmi_hot), + MSM_PIN_FUNCTION(hdmi_rcv), + MSM_PIN_FUNCTION(isense_dbg), + MSM_PIN_FUNCTION(jitter_bist), + MSM_PIN_FUNCTION(ldo_en), + MSM_PIN_FUNCTION(ldo_update), + MSM_PIN_FUNCTION(lpass_slimbus), + MSM_PIN_FUNCTION(m_voc), + MSM_PIN_FUNCTION(mdp_vsync), + MSM_PIN_FUNCTION(mdp_vsync0), + MSM_PIN_FUNCTION(mdp_vsync1), + MSM_PIN_FUNCTION(mdp_vsync2), + MSM_PIN_FUNCTION(mdp_vsync3), + MSM_PIN_FUNCTION(mdp_vsync_a), + MSM_PIN_FUNCTION(mdp_vsync_b), + MSM_PIN_FUNCTION(modem_tsync), + MSM_PIN_FUNCTION(mss_lte), + MSM_PIN_FUNCTION(nav_dr), + MSM_PIN_FUNCTION(nav_pps), + MSM_PIN_FUNCTION(pa_indicator), + MSM_PIN_FUNCTION(pci_e0), + MSM_PIN_FUNCTION(phase_flag), + MSM_PIN_FUNCTION(pll_bypassnl), + MSM_PIN_FUNCTION(pll_reset), + MSM_PIN_FUNCTION(pri_mi2s), + MSM_PIN_FUNCTION(pri_mi2s_ws), + MSM_PIN_FUNCTION(prng_rosc), + MSM_PIN_FUNCTION(pwr_crypto), + MSM_PIN_FUNCTION(pwr_modem), + MSM_PIN_FUNCTION(pwr_nav), + MSM_PIN_FUNCTION(qdss_cti0_a), + MSM_PIN_FUNCTION(qdss_cti0_b), + MSM_PIN_FUNCTION(qdss_cti1_a), + MSM_PIN_FUNCTION(qdss_cti1_b), + MSM_PIN_FUNCTION(qdss), + MSM_PIN_FUNCTION(qlink_enable), + MSM_PIN_FUNCTION(qlink_request), + MSM_PIN_FUNCTION(qua_mi2s), + MSM_PIN_FUNCTION(sd_card), + MSM_PIN_FUNCTION(sd_write), + MSM_PIN_FUNCTION(sdc40), + MSM_PIN_FUNCTION(sdc41), + MSM_PIN_FUNCTION(sdc42), + MSM_PIN_FUNCTION(sdc43), + MSM_PIN_FUNCTION(sdc4_clk), + MSM_PIN_FUNCTION(sdc4_cmd), + MSM_PIN_FUNCTION(sec_mi2s), + MSM_PIN_FUNCTION(sp_cmu), + MSM_PIN_FUNCTION(spkr_i2s), + MSM_PIN_FUNCTION(ssbi1), + MSM_PIN_FUNCTION(ssc_irq), + MSM_PIN_FUNCTION(ter_mi2s), + MSM_PIN_FUNCTION(tgu_ch0), + MSM_PIN_FUNCTION(tgu_ch1), + MSM_PIN_FUNCTION(tsense_pwm1), + MSM_PIN_FUNCTION(tsense_pwm2), + MSM_PIN_FUNCTION(tsif0), + MSM_PIN_FUNCTION(tsif1), + MSM_PIN_FUNCTION(uim1_clk), + MSM_PIN_FUNCTION(uim1_data), + MSM_PIN_FUNCTION(uim1_present), + MSM_PIN_FUNCTION(uim1_reset), + MSM_PIN_FUNCTION(uim2_clk), + MSM_PIN_FUNCTION(uim2_data), + MSM_PIN_FUNCTION(uim2_present), + MSM_PIN_FUNCTION(uim2_reset), + MSM_PIN_FUNCTION(uim_batt), + MSM_PIN_FUNCTION(usb_phy), + MSM_PIN_FUNCTION(vfr_1), + MSM_PIN_FUNCTION(vsense_clkout), + MSM_PIN_FUNCTION(vsense_data0), + MSM_PIN_FUNCTION(vsense_data1), + MSM_PIN_FUNCTION(vsense_mode), + MSM_PIN_FUNCTION(wlan1_adc0), + MSM_PIN_FUNCTION(wlan1_adc1), + MSM_PIN_FUNCTION(wlan2_adc0), + MSM_PIN_FUNCTION(wlan2_adc1), +}; + +static const struct msm_pingroup msm8998_groups[] = { + PINGROUP(0, EAST, blsp_spi1, blsp_uart1_a, blsp_uim1_a, _, _, _, _, _, _), + PINGROUP(1, EAST, blsp_spi1, blsp_uart1_a, blsp_uim1_a, _, _, _, _, _, _), + PINGROUP(2, EAST, blsp_spi1, blsp_uart1_a, blsp_i2c1, _, _, _, _, _, _), + PINGROUP(3, EAST, blsp_spi1, blsp_uart1_a, blsp_i2c1, _, _, _, _, _, _), + PINGROUP(4, WEST, blsp_spi8, blsp_uart8_a, blsp_uim8_a, _, qdss_cti0_b, _, _, _, _), + PINGROUP(5, WEST, blsp_spi8, blsp_uart8_a, blsp_uim8_a, _, qdss_cti0_b, _, _, _, _), + PINGROUP(6, WEST, blsp_spi8, blsp_uart8_a, blsp_i2c8, _, _, _, _, _, _), + PINGROUP(7, WEST, blsp_spi8, blsp_uart8_a, blsp_i2c8, ddr_bist, _, atest_tsens2, atest_usb1, _, _), + PINGROUP(8, EAST, blsp_spi4, blsp_uart1_b, blsp_uim1_b, _, ddr_bist, _, wlan1_adc1, atest_usb13, bimc_dte1), + PINGROUP(9, EAST, blsp_spi4, blsp_uart1_b, blsp_uim1_b, tsif0, ddr_bist, _, wlan1_adc0, atest_usb12, bimc_dte0), + PINGROUP(10, EAST, mdp_vsync_a, blsp_spi4, blsp_uart1_b, blsp_i2c4, ddr_bist, atest_gpsadc1, wlan2_adc1, atest_usb11, bimc_dte1), + PINGROUP(11, EAST, mdp_vsync_a, edp_lcd, blsp_spi4, blsp_uart1_b, blsp_i2c4, dbg_out, atest_gpsadc0, wlan2_adc0, atest_usb10), + PINGROUP(12, EAST, mdp_vsync, m_voc, _, _, _, _, _, _, _), + PINGROUP(13, EAST, cam_mclk, pll_bypassnl, qdss, _, _, _, _, _, _), + PINGROUP(14, EAST, cam_mclk, pll_reset, qdss, _, _, _, _, _, _), + PINGROUP(15, EAST, cam_mclk, qdss, _, _, _, _, _, _, _), + PINGROUP(16, EAST, cam_mclk, qdss, _, _, _, _, _, _, _), + PINGROUP(17, EAST, cci_i2c, qdss, _, _, _, _, _, _, _), + PINGROUP(18, EAST, cci_i2c, phase_flag, qdss, _, _, _, _, _, _), + PINGROUP(19, EAST, cci_i2c, phase_flag, qdss, _, _, _, _, _, _), + PINGROUP(20, EAST, cci_i2c, qdss, _, _, _, _, _, _, _), + PINGROUP(21, EAST, cci_timer0, _, qdss, vsense_data0, _, _, _, _, _), + PINGROUP(22, EAST, cci_timer1, _, qdss, vsense_data1, _, _, _, _, _), + PINGROUP(23, EAST, cci_timer2, blsp1_spi_b, qdss, vsense_mode, _, _, _, _, _), + PINGROUP(24, EAST, cci_timer3, cci_async, blsp1_spi_a, _, qdss, vsense_clkout, _, _, _), + PINGROUP(25, EAST, cci_timer4, cci_async, blsp2_spi, _, qdss, _, _, _, _), + PINGROUP(26, EAST, cci_async, qdss, _, _, _, _, _, _, _), + PINGROUP(27, EAST, blsp1_spi_a, qdss, _, _, _, _, _, _, _), + PINGROUP(28, EAST, blsp1_spi_b, qdss, _, _, _, _, _, _, _), + PINGROUP(29, EAST, blsp2_spi, _, qdss, _, _, _, _, _, _), + PINGROUP(30, EAST, hdmi_rcv, blsp2_spi, qdss, _, _, _, _, _, _), + PINGROUP(31, EAST, hdmi_cec, blsp_spi2, blsp_uart2_a, blsp_uim2_a, pwr_modem, _, _, _, _), + PINGROUP(32, EAST, hdmi_ddc, blsp_spi2, blsp_uart2_a, blsp_i2c2, pwr_nav, _, _, _, _), + PINGROUP(33, EAST, hdmi_ddc, blsp_spi2, blsp_uart2_a, blsp_i2c2, pwr_crypto, _, _, _, _), + PINGROUP(34, EAST, hdmi_hot, edp_hot, blsp_spi2, blsp_uart2_a, blsp_uim2_a, _, _, _, _), + PINGROUP(35, NORTH, pci_e0, jitter_bist, _, _, _, _, _, _, _), + PINGROUP(36, NORTH, pci_e0, agera_pll, _, atest_tsens, _, _, _, _, _), + PINGROUP(37, NORTH, agera_pll, _, _, _, _, _, _, _, _), + PINGROUP(38, WEST, usb_phy, _, _, _, _, _, _, _, _), + PINGROUP(39, WEST, lpass_slimbus, _, _, _, _, _, _, _, _), + PINGROUP(40, EAST, sd_write, tsif0, _, _, _, _, _, _, _), + PINGROUP(41, EAST, blsp_spi6, blsp_uart3_b, blsp_uim3_b, _, qdss, _, _, _, _), + PINGROUP(42, EAST, blsp_spi6, blsp_uart3_b, blsp_uim3_b, _, qdss, _, _, _, _), + PINGROUP(43, EAST, blsp_spi6, blsp_uart3_b, blsp_i2c6, _, qdss, _, _, _, _), + PINGROUP(44, EAST, blsp_spi6, blsp_uart3_b, blsp_i2c6, _, qdss, _, _, _, _), + PINGROUP(45, EAST, blsp_spi3, blsp_uart3_a, blsp_uim3_a, _, _, _, _, _, _), + PINGROUP(46, EAST, blsp_spi3, blsp_uart3_a, blsp_uim3_a, _, _, _, _, _, _), + PINGROUP(47, EAST, blsp_spi3, blsp_uart3_a, blsp_i2c3, _, _, _, _, _, _), + PINGROUP(48, EAST, blsp_spi3, blsp_uart3_a, blsp_i2c3, _, _, _, _, _, _), + PINGROUP(49, NORTH, blsp_spi9, blsp_uart9_a, blsp_uim9_a, blsp10_spi_b, qdss_cti0_a, _, _, _, _), + PINGROUP(50, NORTH, blsp_spi9, blsp_uart9_a, blsp_uim9_a, blsp10_spi_b, qdss_cti0_a, _, _, _, _), + PINGROUP(51, NORTH, blsp_spi9, blsp_uart9_a, blsp_i2c9, blsp10_spi_a, _, _, _, _, _), + PINGROUP(52, NORTH, blsp_spi9, blsp_uart9_a, blsp_i2c9, blsp10_spi_a, _, _, _, _, _), + PINGROUP(53, WEST, blsp_spi7, blsp_uart7_a, blsp_uim7_a, _, _, _, _, _, _), + PINGROUP(54, WEST, blsp_spi7, blsp_uart7_a, blsp_uim7_a, _, _, _, _, _, _), + PINGROUP(55, WEST, blsp_spi7, blsp_uart7_a, blsp_i2c7, _, _, _, _, _, _), + PINGROUP(56, WEST, blsp_spi7, blsp_uart7_a, blsp_i2c7, _, _, _, _, _, _), + PINGROUP(57, WEST, qua_mi2s, blsp10_spi, gcc_gp1_a, _, _, _, _, _, _), + PINGROUP(58, WEST, qua_mi2s, blsp_spi11, blsp_uart8_b, blsp_uim8_b, gcc_gp2_a, _, qdss_cti1_a, _, _), + PINGROUP(59, WEST, qua_mi2s, blsp_spi11, blsp_uart8_b, blsp_uim8_b, gcc_gp3_a, _, qdss_cti1_a, _, _), + PINGROUP(60, WEST, qua_mi2s, blsp_spi11, blsp_uart8_b, blsp_i2c11, cri_trng0, _, _, _, _), + PINGROUP(61, WEST, qua_mi2s, blsp_spi11, blsp_uart8_b, blsp_i2c11, cri_trng1, _, _, _, _), + PINGROUP(62, WEST, qua_mi2s, cri_trng, _, _, _, _, _, _, _), + PINGROUP(63, WEST, qua_mi2s, _, _, _, _, _, _, _, _), + PINGROUP(64, WEST, pri_mi2s, sp_cmu, _, _, _, _, _, _, _), + PINGROUP(65, WEST, pri_mi2s, blsp_spi10, blsp_uart7_b, blsp_uim7_b, _, _, _, _, _), + PINGROUP(66, WEST, pri_mi2s_ws, blsp_spi10, blsp_uart7_b, blsp_uim7_b, _, _, _, _, _), + PINGROUP(67, WEST, pri_mi2s, blsp_spi10, blsp_uart7_b, blsp_i2c10, _, _, _, _, _), + PINGROUP(68, WEST, pri_mi2s, blsp_spi10, blsp_uart7_b, blsp_i2c10, _, _, _, _, _), + PINGROUP(69, WEST, spkr_i2s, audio_ref, _, _, _, _, _, _, _), + PINGROUP(70, WEST, lpass_slimbus, spkr_i2s, blsp9_spi, _, _, _, _, _, _), + PINGROUP(71, WEST, lpass_slimbus, spkr_i2s, blsp9_spi, tsense_pwm1, tsense_pwm2, _, _, _, _), + PINGROUP(72, WEST, lpass_slimbus, spkr_i2s, blsp9_spi, _, _, _, _, _, _), + PINGROUP(73, WEST, btfm_slimbus, phase_flag, _, _, _, _, _, _, _), + PINGROUP(74, WEST, btfm_slimbus, ter_mi2s, phase_flag, _, _, _, _, _, _), + PINGROUP(75, WEST, ter_mi2s, phase_flag, qdss, _, _, _, _, _, _), + PINGROUP(76, WEST, ter_mi2s, phase_flag, qdss, _, _, _, _, _, _), + PINGROUP(77, WEST, ter_mi2s, phase_flag, qdss, _, _, _, _, _, _), + PINGROUP(78, WEST, ter_mi2s, gcc_gp1_b, _, _, _, _, _, _, _), + PINGROUP(79, WEST, sec_mi2s, _, qdss, _, _, _, _, _, _), + PINGROUP(80, WEST, sec_mi2s, _, qdss, _, _, _, _, _, _), + PINGROUP(81, WEST, sec_mi2s, blsp_spi12, blsp_uart9_b, blsp_uim9_b, gcc_gp2_b, _, _, _, _), + PINGROUP(82, WEST, sec_mi2s, blsp_spi12, blsp_uart9_b, blsp_uim9_b, gcc_gp3_b, _, _, _, _), + PINGROUP(83, WEST, sec_mi2s, blsp_spi12, blsp_uart9_b, blsp_i2c12, _, _, _, _, _), + PINGROUP(84, WEST, blsp_spi12, blsp_uart9_b, blsp_i2c12, _, _, _, _, _, _), + PINGROUP(85, EAST, blsp_spi5, blsp_uart2_b, blsp_uim2_b, _, _, _, _, _, _), + PINGROUP(86, EAST, blsp_spi5, blsp_uart2_b, blsp_uim2_b, _, _, _, _, _, _), + PINGROUP(87, EAST, blsp_spi5, blsp_uart2_b, blsp_i2c5, _, _, _, _, _, _), + PINGROUP(88, EAST, blsp_spi5, blsp_uart2_b, blsp_i2c5, _, _, _, _, _, _), + PINGROUP(89, EAST, tsif0, phase_flag, _, _, _, _, _, _, _), + PINGROUP(90, EAST, tsif0, mdp_vsync0, mdp_vsync1, mdp_vsync2, mdp_vsync3, blsp1_spi, tgu_ch0, qdss_cti1_b, _), + PINGROUP(91, EAST, tsif0, sdc4_cmd, tgu_ch1, phase_flag, qdss_cti1_b, _, _, _, _), + PINGROUP(92, EAST, tsif1, sdc43, vfr_1, phase_flag, _, _, _, _, _), + PINGROUP(93, EAST, tsif1, sdc4_clk, _, qdss, _, _, _, _, _), + PINGROUP(94, EAST, tsif1, sdc42, _, _, _, _, _, _, _), + PINGROUP(95, EAST, tsif1, sdc41, _, _, _, _, _, _, _), + PINGROUP(96, EAST, tsif1, sdc40, phase_flag, _, _, _, _, _, _), + PINGROUP(97, WEST, _, mdp_vsync_b, ldo_en, _, _, _, _, _, _), + PINGROUP(98, WEST, _, mdp_vsync_b, ldo_update, _, _, _, _, _, _), + PINGROUP(99, WEST, _, _, _, _, _, _, _, _, _), + PINGROUP(100, WEST, _, _, blsp_uart8, _, _, _, _, _, _), + PINGROUP(101, WEST, _, blsp_uart8, _, _, _, _, _, _, _), + PINGROUP(102, WEST, _, blsp11_i2c, prng_rosc, _, _, _, _, _, _), + PINGROUP(103, WEST, _, blsp11_i2c, phase_flag, _, _, _, _, _, _), + PINGROUP(104, WEST, _, _, _, _, _, _, _, _, _), + PINGROUP(105, NORTH, uim2_data, _, _, _, _, _, _, _, _), + PINGROUP(106, NORTH, uim2_clk, _, _, _, _, _, _, _, _), + PINGROUP(107, NORTH, uim2_reset, _, _, _, _, _, _, _, _), + PINGROUP(108, NORTH, uim2_present, _, _, _, _, _, _, _, _), + PINGROUP(109, NORTH, uim1_data, _, _, _, _, _, _, _, _), + PINGROUP(110, NORTH, uim1_clk, _, _, _, _, _, _, _, _), + PINGROUP(111, NORTH, uim1_reset, _, _, _, _, _, _, _, _), + PINGROUP(112, NORTH, uim1_present, _, _, _, _, _, _, _, _), + PINGROUP(113, NORTH, uim_batt, _, _, _, _, _, _, _, _), + PINGROUP(114, WEST, _, _, phase_flag, _, _, _, _, _, _), + PINGROUP(115, WEST, _, nav_dr, phase_flag, _, _, _, _, _, _), + PINGROUP(116, WEST, phase_flag, _, _, _, _, _, _, _, _), + PINGROUP(117, EAST, phase_flag, qdss, atest_char, _, _, _, _, _, _), + PINGROUP(118, EAST, adsp_ext, phase_flag, qdss, atest_char, _, _, _, _, _), + PINGROUP(119, EAST, phase_flag, qdss, atest_char, _, _, _, _, _, _), + PINGROUP(120, EAST, phase_flag, qdss, atest_char, _, _, _, _, _, _), + PINGROUP(121, EAST, phase_flag, qdss, atest_char, _, _, _, _, _, _), + PINGROUP(122, EAST, phase_flag, qdss, _, _, _, _, _, _, _), + PINGROUP(123, EAST, phase_flag, qdss, _, _, _, _, _, _, _), + PINGROUP(124, EAST, phase_flag, qdss, _, _, _, _, _, _, _), + PINGROUP(125, EAST, phase_flag, _, _, _, _, _, _, _, _), + PINGROUP(126, EAST, phase_flag, _, _, _, _, _, _, _, _), + PINGROUP(127, WEST, _, _, _, _, _, _, _, _, _), + PINGROUP(128, WEST, modem_tsync, nav_pps, phase_flag, _, _, _, _, _, _), + PINGROUP(129, WEST, phase_flag, _, _, _, _, _, _, _, _), + PINGROUP(130, NORTH, qlink_request, phase_flag, _, _, _, _, _, _, _), + PINGROUP(131, NORTH, qlink_enable, phase_flag, _, _, _, _, _, _, _), + PINGROUP(132, WEST, _, phase_flag, _, _, _, _, _, _, _), + PINGROUP(133, WEST, phase_flag, _, _, _, _, _, _, _, _), + PINGROUP(134, WEST, phase_flag, _, _, _, _, _, _, _, _), + PINGROUP(135, WEST, _, pa_indicator, _, _, _, _, _, _, _), + PINGROUP(136, WEST, _, _, _, _, _, _, _, _, _), + PINGROUP(137, WEST, _, _, _, _, _, _, _, _, _), + PINGROUP(138, WEST, _, _, _, _, _, _, _, _, _), + PINGROUP(139, WEST, _, _, _, _, _, _, _, _, _), + PINGROUP(140, WEST, _, _, _, _, _, _, _, _, _), + PINGROUP(141, WEST, _, _, _, _, _, _, _, _, _), + PINGROUP(142, WEST, _, ssbi1, _, _, _, _, _, _, _), + PINGROUP(143, WEST, isense_dbg, _, _, _, _, _, _, _, _), + PINGROUP(144, WEST, mss_lte, _, _, _, _, _, _, _, _), + PINGROUP(145, WEST, mss_lte, _, _, _, _, _, _, _, _), + PINGROUP(146, WEST, _, _, _, _, _, _, _, _, _), + PINGROUP(147, WEST, _, _, _, _, _, _, _, _, _), + PINGROUP(148, WEST, _, _, _, _, _, _, _, _, _), + PINGROUP(149, WEST, _, _, _, _, _, _, _, _, _), + SDC_QDSD_PINGROUP(sdc2_clk, 0x999000, 14, 6), + SDC_QDSD_PINGROUP(sdc2_cmd, 0x999000, 11, 3), + SDC_QDSD_PINGROUP(sdc2_data, 0x999000, 9, 0), + UFS_RESET(ufs_reset, 0x19d000), +}; + +static const struct msm_gpio_wakeirq_map msm8998_mpm_map[] = { + { 1, 3 }, { 5, 4 }, { 9, 5 }, { 11, 6 }, { 22, 8 }, { 24, 9 }, { 26, 10 }, + { 34, 11 }, { 36, 12 }, { 37, 13 }, { 38, 14 }, { 40, 15 }, { 42, 16 }, { 46, 17 }, + { 50, 18 }, { 53, 19 }, { 54, 20 }, { 56, 21 }, { 57, 22 }, { 58, 23 }, { 59, 24 }, + { 60, 25 }, { 61, 26 }, { 62, 27 }, { 63, 28 }, { 64, 29 }, { 66, 7 }, { 71, 30 }, + { 73, 31 }, { 77, 32 }, { 78, 33 }, { 79, 34 }, { 80, 35 }, { 82, 36 }, { 86, 37 }, + { 91, 38 }, { 92, 39 }, { 95, 40 }, { 97, 41 }, { 101, 42 }, { 104, 43 }, { 106, 44 }, + { 108, 45 }, { 110, 48 }, { 112, 46 }, { 113, 47 }, { 115, 51 }, { 116, 54 }, { 117, 55 }, + { 118, 56 }, { 119, 57 }, { 120, 58 }, { 121, 59 }, { 122, 60 }, { 123, 61 }, { 124, 62 }, + { 125, 63 }, { 126, 64 }, { 127, 50 }, { 129, 65 }, { 131, 66 }, { 132, 67 }, { 133, 68 }, +}; + +static const struct msm_pinctrl_soc_data msm8998_pinctrl = { + .pins = msm8998_pins, + .npins = ARRAY_SIZE(msm8998_pins), + .functions = msm8998_functions, + .nfunctions = ARRAY_SIZE(msm8998_functions), + .groups = msm8998_groups, + .ngroups = ARRAY_SIZE(msm8998_groups), + .ngpios = 150, + .wakeirq_map = msm8998_mpm_map, + .nwakeirq_map = ARRAY_SIZE(msm8998_mpm_map), +}; + +static int msm8998_pinctrl_probe(struct platform_device *pdev) +{ + return msm_pinctrl_probe(pdev, &msm8998_pinctrl); +} + +static const struct of_device_id msm8998_pinctrl_of_match[] = { + { .compatible = "qcom,msm8998-pinctrl", }, + { }, +}; + +static struct platform_driver msm8998_pinctrl_driver = { + .driver = { + .name = "msm8998-pinctrl", + .of_match_table = msm8998_pinctrl_of_match, + }, + .probe = msm8998_pinctrl_probe, + .remove = msm_pinctrl_remove, +}; + +static int __init msm8998_pinctrl_init(void) +{ + return platform_driver_register(&msm8998_pinctrl_driver); +} +arch_initcall(msm8998_pinctrl_init); + +static void __exit msm8998_pinctrl_exit(void) +{ + platform_driver_unregister(&msm8998_pinctrl_driver); +} +module_exit(msm8998_pinctrl_exit); + +MODULE_DESCRIPTION("QTI msm8998 pinctrl driver"); +MODULE_LICENSE("GPL v2"); +MODULE_DEVICE_TABLE(of, msm8998_pinctrl_of_match); diff --git a/drivers/pinctrl/qcom/pinctrl-msm8x74.c b/drivers/pinctrl/qcom/pinctrl-msm8x74.c new file mode 100644 index 0000000000..d5fe629928 --- /dev/null +++ b/drivers/pinctrl/qcom/pinctrl-msm8x74.c @@ -0,0 +1,1093 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2013, Sony Mobile Communications AB. + */ + +#include <linux/module.h> +#include <linux/of.h> +#include <linux/platform_device.h> + +#include "pinctrl-msm.h" + +static const struct pinctrl_pin_desc msm8x74_pins[] = { + PINCTRL_PIN(0, "GPIO_0"), + PINCTRL_PIN(1, "GPIO_1"), + PINCTRL_PIN(2, "GPIO_2"), + PINCTRL_PIN(3, "GPIO_3"), + PINCTRL_PIN(4, "GPIO_4"), + PINCTRL_PIN(5, "GPIO_5"), + PINCTRL_PIN(6, "GPIO_6"), + PINCTRL_PIN(7, "GPIO_7"), + PINCTRL_PIN(8, "GPIO_8"), + PINCTRL_PIN(9, "GPIO_9"), + PINCTRL_PIN(10, "GPIO_10"), + PINCTRL_PIN(11, "GPIO_11"), + PINCTRL_PIN(12, "GPIO_12"), + PINCTRL_PIN(13, "GPIO_13"), + PINCTRL_PIN(14, "GPIO_14"), + PINCTRL_PIN(15, "GPIO_15"), + PINCTRL_PIN(16, "GPIO_16"), + PINCTRL_PIN(17, "GPIO_17"), + PINCTRL_PIN(18, "GPIO_18"), + PINCTRL_PIN(19, "GPIO_19"), + PINCTRL_PIN(20, "GPIO_20"), + PINCTRL_PIN(21, "GPIO_21"), + PINCTRL_PIN(22, "GPIO_22"), + PINCTRL_PIN(23, "GPIO_23"), + PINCTRL_PIN(24, "GPIO_24"), + PINCTRL_PIN(25, "GPIO_25"), + PINCTRL_PIN(26, "GPIO_26"), + PINCTRL_PIN(27, "GPIO_27"), + PINCTRL_PIN(28, "GPIO_28"), + PINCTRL_PIN(29, "GPIO_29"), + PINCTRL_PIN(30, "GPIO_30"), + PINCTRL_PIN(31, "GPIO_31"), + PINCTRL_PIN(32, "GPIO_32"), + PINCTRL_PIN(33, "GPIO_33"), + PINCTRL_PIN(34, "GPIO_34"), + PINCTRL_PIN(35, "GPIO_35"), + PINCTRL_PIN(36, "GPIO_36"), + PINCTRL_PIN(37, "GPIO_37"), + PINCTRL_PIN(38, "GPIO_38"), + PINCTRL_PIN(39, "GPIO_39"), + PINCTRL_PIN(40, "GPIO_40"), + PINCTRL_PIN(41, "GPIO_41"), + PINCTRL_PIN(42, "GPIO_42"), + PINCTRL_PIN(43, "GPIO_43"), + PINCTRL_PIN(44, "GPIO_44"), + PINCTRL_PIN(45, "GPIO_45"), + PINCTRL_PIN(46, "GPIO_46"), + PINCTRL_PIN(47, "GPIO_47"), + PINCTRL_PIN(48, "GPIO_48"), + PINCTRL_PIN(49, "GPIO_49"), + PINCTRL_PIN(50, "GPIO_50"), + PINCTRL_PIN(51, "GPIO_51"), + PINCTRL_PIN(52, "GPIO_52"), + PINCTRL_PIN(53, "GPIO_53"), + PINCTRL_PIN(54, "GPIO_54"), + PINCTRL_PIN(55, "GPIO_55"), + PINCTRL_PIN(56, "GPIO_56"), + PINCTRL_PIN(57, "GPIO_57"), + PINCTRL_PIN(58, "GPIO_58"), + PINCTRL_PIN(59, "GPIO_59"), + PINCTRL_PIN(60, "GPIO_60"), + PINCTRL_PIN(61, "GPIO_61"), + PINCTRL_PIN(62, "GPIO_62"), + PINCTRL_PIN(63, "GPIO_63"), + PINCTRL_PIN(64, "GPIO_64"), + PINCTRL_PIN(65, "GPIO_65"), + PINCTRL_PIN(66, "GPIO_66"), + PINCTRL_PIN(67, "GPIO_67"), + PINCTRL_PIN(68, "GPIO_68"), + PINCTRL_PIN(69, "GPIO_69"), + PINCTRL_PIN(70, "GPIO_70"), + PINCTRL_PIN(71, "GPIO_71"), + PINCTRL_PIN(72, "GPIO_72"), + PINCTRL_PIN(73, "GPIO_73"), + PINCTRL_PIN(74, "GPIO_74"), + PINCTRL_PIN(75, "GPIO_75"), + PINCTRL_PIN(76, "GPIO_76"), + PINCTRL_PIN(77, "GPIO_77"), + PINCTRL_PIN(78, "GPIO_78"), + PINCTRL_PIN(79, "GPIO_79"), + PINCTRL_PIN(80, "GPIO_80"), + PINCTRL_PIN(81, "GPIO_81"), + PINCTRL_PIN(82, "GPIO_82"), + PINCTRL_PIN(83, "GPIO_83"), + PINCTRL_PIN(84, "GPIO_84"), + PINCTRL_PIN(85, "GPIO_85"), + PINCTRL_PIN(86, "GPIO_86"), + PINCTRL_PIN(87, "GPIO_87"), + PINCTRL_PIN(88, "GPIO_88"), + PINCTRL_PIN(89, "GPIO_89"), + PINCTRL_PIN(90, "GPIO_90"), + PINCTRL_PIN(91, "GPIO_91"), + PINCTRL_PIN(92, "GPIO_92"), + PINCTRL_PIN(93, "GPIO_93"), + PINCTRL_PIN(94, "GPIO_94"), + PINCTRL_PIN(95, "GPIO_95"), + PINCTRL_PIN(96, "GPIO_96"), + PINCTRL_PIN(97, "GPIO_97"), + PINCTRL_PIN(98, "GPIO_98"), + PINCTRL_PIN(99, "GPIO_99"), + PINCTRL_PIN(100, "GPIO_100"), + PINCTRL_PIN(101, "GPIO_101"), + PINCTRL_PIN(102, "GPIO_102"), + PINCTRL_PIN(103, "GPIO_103"), + PINCTRL_PIN(104, "GPIO_104"), + PINCTRL_PIN(105, "GPIO_105"), + PINCTRL_PIN(106, "GPIO_106"), + PINCTRL_PIN(107, "GPIO_107"), + PINCTRL_PIN(108, "GPIO_108"), + PINCTRL_PIN(109, "GPIO_109"), + PINCTRL_PIN(110, "GPIO_110"), + PINCTRL_PIN(111, "GPIO_111"), + PINCTRL_PIN(112, "GPIO_112"), + PINCTRL_PIN(113, "GPIO_113"), + PINCTRL_PIN(114, "GPIO_114"), + PINCTRL_PIN(115, "GPIO_115"), + PINCTRL_PIN(116, "GPIO_116"), + PINCTRL_PIN(117, "GPIO_117"), + PINCTRL_PIN(118, "GPIO_118"), + PINCTRL_PIN(119, "GPIO_119"), + PINCTRL_PIN(120, "GPIO_120"), + PINCTRL_PIN(121, "GPIO_121"), + PINCTRL_PIN(122, "GPIO_122"), + PINCTRL_PIN(123, "GPIO_123"), + PINCTRL_PIN(124, "GPIO_124"), + PINCTRL_PIN(125, "GPIO_125"), + PINCTRL_PIN(126, "GPIO_126"), + PINCTRL_PIN(127, "GPIO_127"), + PINCTRL_PIN(128, "GPIO_128"), + PINCTRL_PIN(129, "GPIO_129"), + PINCTRL_PIN(130, "GPIO_130"), + PINCTRL_PIN(131, "GPIO_131"), + PINCTRL_PIN(132, "GPIO_132"), + PINCTRL_PIN(133, "GPIO_133"), + PINCTRL_PIN(134, "GPIO_134"), + PINCTRL_PIN(135, "GPIO_135"), + PINCTRL_PIN(136, "GPIO_136"), + PINCTRL_PIN(137, "GPIO_137"), + PINCTRL_PIN(138, "GPIO_138"), + PINCTRL_PIN(139, "GPIO_139"), + PINCTRL_PIN(140, "GPIO_140"), + PINCTRL_PIN(141, "GPIO_141"), + PINCTRL_PIN(142, "GPIO_142"), + PINCTRL_PIN(143, "GPIO_143"), + PINCTRL_PIN(144, "GPIO_144"), + PINCTRL_PIN(145, "GPIO_145"), + + PINCTRL_PIN(146, "SDC1_CLK"), + PINCTRL_PIN(147, "SDC1_CMD"), + PINCTRL_PIN(148, "SDC1_DATA"), + PINCTRL_PIN(149, "SDC2_CLK"), + PINCTRL_PIN(150, "SDC2_CMD"), + PINCTRL_PIN(151, "SDC2_DATA"), + PINCTRL_PIN(152, "HSIC_STROBE"), + PINCTRL_PIN(153, "HSIC_DATA"), +}; + +#define DECLARE_MSM_GPIO_PINS(pin) static const unsigned int gpio##pin##_pins[] = { pin } +DECLARE_MSM_GPIO_PINS(0); +DECLARE_MSM_GPIO_PINS(1); +DECLARE_MSM_GPIO_PINS(2); +DECLARE_MSM_GPIO_PINS(3); +DECLARE_MSM_GPIO_PINS(4); +DECLARE_MSM_GPIO_PINS(5); +DECLARE_MSM_GPIO_PINS(6); +DECLARE_MSM_GPIO_PINS(7); +DECLARE_MSM_GPIO_PINS(8); +DECLARE_MSM_GPIO_PINS(9); +DECLARE_MSM_GPIO_PINS(10); +DECLARE_MSM_GPIO_PINS(11); +DECLARE_MSM_GPIO_PINS(12); +DECLARE_MSM_GPIO_PINS(13); +DECLARE_MSM_GPIO_PINS(14); +DECLARE_MSM_GPIO_PINS(15); +DECLARE_MSM_GPIO_PINS(16); +DECLARE_MSM_GPIO_PINS(17); +DECLARE_MSM_GPIO_PINS(18); +DECLARE_MSM_GPIO_PINS(19); +DECLARE_MSM_GPIO_PINS(20); +DECLARE_MSM_GPIO_PINS(21); +DECLARE_MSM_GPIO_PINS(22); +DECLARE_MSM_GPIO_PINS(23); +DECLARE_MSM_GPIO_PINS(24); +DECLARE_MSM_GPIO_PINS(25); +DECLARE_MSM_GPIO_PINS(26); +DECLARE_MSM_GPIO_PINS(27); +DECLARE_MSM_GPIO_PINS(28); +DECLARE_MSM_GPIO_PINS(29); +DECLARE_MSM_GPIO_PINS(30); +DECLARE_MSM_GPIO_PINS(31); +DECLARE_MSM_GPIO_PINS(32); +DECLARE_MSM_GPIO_PINS(33); +DECLARE_MSM_GPIO_PINS(34); +DECLARE_MSM_GPIO_PINS(35); +DECLARE_MSM_GPIO_PINS(36); +DECLARE_MSM_GPIO_PINS(37); +DECLARE_MSM_GPIO_PINS(38); +DECLARE_MSM_GPIO_PINS(39); +DECLARE_MSM_GPIO_PINS(40); +DECLARE_MSM_GPIO_PINS(41); +DECLARE_MSM_GPIO_PINS(42); +DECLARE_MSM_GPIO_PINS(43); +DECLARE_MSM_GPIO_PINS(44); +DECLARE_MSM_GPIO_PINS(45); +DECLARE_MSM_GPIO_PINS(46); +DECLARE_MSM_GPIO_PINS(47); +DECLARE_MSM_GPIO_PINS(48); +DECLARE_MSM_GPIO_PINS(49); +DECLARE_MSM_GPIO_PINS(50); +DECLARE_MSM_GPIO_PINS(51); +DECLARE_MSM_GPIO_PINS(52); +DECLARE_MSM_GPIO_PINS(53); +DECLARE_MSM_GPIO_PINS(54); +DECLARE_MSM_GPIO_PINS(55); +DECLARE_MSM_GPIO_PINS(56); +DECLARE_MSM_GPIO_PINS(57); +DECLARE_MSM_GPIO_PINS(58); +DECLARE_MSM_GPIO_PINS(59); +DECLARE_MSM_GPIO_PINS(60); +DECLARE_MSM_GPIO_PINS(61); +DECLARE_MSM_GPIO_PINS(62); +DECLARE_MSM_GPIO_PINS(63); +DECLARE_MSM_GPIO_PINS(64); +DECLARE_MSM_GPIO_PINS(65); +DECLARE_MSM_GPIO_PINS(66); +DECLARE_MSM_GPIO_PINS(67); +DECLARE_MSM_GPIO_PINS(68); +DECLARE_MSM_GPIO_PINS(69); +DECLARE_MSM_GPIO_PINS(70); +DECLARE_MSM_GPIO_PINS(71); +DECLARE_MSM_GPIO_PINS(72); +DECLARE_MSM_GPIO_PINS(73); +DECLARE_MSM_GPIO_PINS(74); +DECLARE_MSM_GPIO_PINS(75); +DECLARE_MSM_GPIO_PINS(76); +DECLARE_MSM_GPIO_PINS(77); +DECLARE_MSM_GPIO_PINS(78); +DECLARE_MSM_GPIO_PINS(79); +DECLARE_MSM_GPIO_PINS(80); +DECLARE_MSM_GPIO_PINS(81); +DECLARE_MSM_GPIO_PINS(82); +DECLARE_MSM_GPIO_PINS(83); +DECLARE_MSM_GPIO_PINS(84); +DECLARE_MSM_GPIO_PINS(85); +DECLARE_MSM_GPIO_PINS(86); +DECLARE_MSM_GPIO_PINS(87); +DECLARE_MSM_GPIO_PINS(88); +DECLARE_MSM_GPIO_PINS(89); +DECLARE_MSM_GPIO_PINS(90); +DECLARE_MSM_GPIO_PINS(91); +DECLARE_MSM_GPIO_PINS(92); +DECLARE_MSM_GPIO_PINS(93); +DECLARE_MSM_GPIO_PINS(94); +DECLARE_MSM_GPIO_PINS(95); +DECLARE_MSM_GPIO_PINS(96); +DECLARE_MSM_GPIO_PINS(97); +DECLARE_MSM_GPIO_PINS(98); +DECLARE_MSM_GPIO_PINS(99); +DECLARE_MSM_GPIO_PINS(100); +DECLARE_MSM_GPIO_PINS(101); +DECLARE_MSM_GPIO_PINS(102); +DECLARE_MSM_GPIO_PINS(103); +DECLARE_MSM_GPIO_PINS(104); +DECLARE_MSM_GPIO_PINS(105); +DECLARE_MSM_GPIO_PINS(106); +DECLARE_MSM_GPIO_PINS(107); +DECLARE_MSM_GPIO_PINS(108); +DECLARE_MSM_GPIO_PINS(109); +DECLARE_MSM_GPIO_PINS(110); +DECLARE_MSM_GPIO_PINS(111); +DECLARE_MSM_GPIO_PINS(112); +DECLARE_MSM_GPIO_PINS(113); +DECLARE_MSM_GPIO_PINS(114); +DECLARE_MSM_GPIO_PINS(115); +DECLARE_MSM_GPIO_PINS(116); +DECLARE_MSM_GPIO_PINS(117); +DECLARE_MSM_GPIO_PINS(118); +DECLARE_MSM_GPIO_PINS(119); +DECLARE_MSM_GPIO_PINS(120); +DECLARE_MSM_GPIO_PINS(121); +DECLARE_MSM_GPIO_PINS(122); +DECLARE_MSM_GPIO_PINS(123); +DECLARE_MSM_GPIO_PINS(124); +DECLARE_MSM_GPIO_PINS(125); +DECLARE_MSM_GPIO_PINS(126); +DECLARE_MSM_GPIO_PINS(127); +DECLARE_MSM_GPIO_PINS(128); +DECLARE_MSM_GPIO_PINS(129); +DECLARE_MSM_GPIO_PINS(130); +DECLARE_MSM_GPIO_PINS(131); +DECLARE_MSM_GPIO_PINS(132); +DECLARE_MSM_GPIO_PINS(133); +DECLARE_MSM_GPIO_PINS(134); +DECLARE_MSM_GPIO_PINS(135); +DECLARE_MSM_GPIO_PINS(136); +DECLARE_MSM_GPIO_PINS(137); +DECLARE_MSM_GPIO_PINS(138); +DECLARE_MSM_GPIO_PINS(139); +DECLARE_MSM_GPIO_PINS(140); +DECLARE_MSM_GPIO_PINS(141); +DECLARE_MSM_GPIO_PINS(142); +DECLARE_MSM_GPIO_PINS(143); +DECLARE_MSM_GPIO_PINS(144); +DECLARE_MSM_GPIO_PINS(145); + +static const unsigned int sdc1_clk_pins[] = { 146 }; +static const unsigned int sdc1_cmd_pins[] = { 147 }; +static const unsigned int sdc1_data_pins[] = { 148 }; +static const unsigned int sdc2_clk_pins[] = { 149 }; +static const unsigned int sdc2_cmd_pins[] = { 150 }; +static const unsigned int sdc2_data_pins[] = { 151 }; +static const unsigned int hsic_strobe_pins[] = { 152 }; +static const unsigned int hsic_data_pins[] = { 153 }; + +#define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7) \ + { \ + .grp = PINCTRL_PINGROUP("gpio" #id, \ + gpio##id##_pins, \ + ARRAY_SIZE(gpio##id##_pins)), \ + .funcs = (int[]){ \ + msm_mux_gpio, \ + msm_mux_##f1, \ + msm_mux_##f2, \ + msm_mux_##f3, \ + msm_mux_##f4, \ + msm_mux_##f5, \ + msm_mux_##f6, \ + msm_mux_##f7 \ + }, \ + .nfuncs = 8, \ + .ctl_reg = 0x1000 + 0x10 * id, \ + .io_reg = 0x1004 + 0x10 * id, \ + .intr_cfg_reg = 0x1008 + 0x10 * id, \ + .intr_status_reg = 0x100c + 0x10 * id, \ + .intr_target_reg = 0x1008 + 0x10 * id, \ + .mux_bit = 2, \ + .pull_bit = 0, \ + .drv_bit = 6, \ + .oe_bit = 9, \ + .in_bit = 0, \ + .out_bit = 1, \ + .intr_enable_bit = 0, \ + .intr_status_bit = 0, \ + .intr_target_bit = 5, \ + .intr_target_kpss_val = 4, \ + .intr_raw_status_bit = 4, \ + .intr_polarity_bit = 1, \ + .intr_detection_bit = 2, \ + .intr_detection_width = 2, \ + } + +#define SDC_PINGROUP(pg_name, ctl, pull, drv) \ + { \ + .grp = PINCTRL_PINGROUP(#pg_name, \ + pg_name##_pins, \ + ARRAY_SIZE(pg_name##_pins)), \ + .ctl_reg = ctl, \ + .io_reg = 0, \ + .intr_cfg_reg = 0, \ + .intr_status_reg = 0, \ + .intr_target_reg = 0, \ + .mux_bit = -1, \ + .pull_bit = pull, \ + .drv_bit = drv, \ + .oe_bit = -1, \ + .in_bit = -1, \ + .out_bit = -1, \ + .intr_enable_bit = -1, \ + .intr_status_bit = -1, \ + .intr_target_bit = -1, \ + .intr_target_kpss_val = -1, \ + .intr_raw_status_bit = -1, \ + .intr_polarity_bit = -1, \ + .intr_detection_bit = -1, \ + .intr_detection_width = -1, \ + } + +#define HSIC_PINGROUP(pg_name, ctl) \ + { \ + .grp = PINCTRL_PINGROUP(#pg_name, \ + pg_name##_pins, \ + ARRAY_SIZE(pg_name##_pins)), \ + .funcs = (int[]){ \ + msm_mux_gpio, \ + msm_mux_hsic_ctl, \ + }, \ + .nfuncs = 2, \ + .ctl_reg = ctl, \ + .io_reg = 0, \ + .intr_cfg_reg = 0, \ + .intr_status_reg = 0, \ + .intr_target_reg = 0, \ + .mux_bit = 25, \ + .pull_bit = -1, \ + .drv_bit = -1, \ + .oe_bit = -1, \ + .in_bit = -1, \ + .out_bit = -1, \ + .intr_enable_bit = -1, \ + .intr_status_bit = -1, \ + .intr_target_bit = -1, \ + .intr_target_kpss_val = -1, \ + .intr_raw_status_bit = -1, \ + .intr_polarity_bit = -1, \ + .intr_detection_bit = -1, \ + .intr_detection_width = -1, \ + } + +/* + * TODO: Add the rest of the possible functions and fill out + * the pingroup table below. + */ +enum msm8x74_functions { + msm_mux_gpio, + msm_mux_cci_i2c0, + msm_mux_cci_i2c1, + msm_mux_blsp_i2c1, + msm_mux_blsp_i2c2, + msm_mux_blsp_i2c3, + msm_mux_blsp_i2c4, + msm_mux_blsp_i2c5, + msm_mux_blsp_i2c6, + msm_mux_blsp_i2c7, + msm_mux_blsp_i2c8, + msm_mux_blsp_i2c9, + msm_mux_blsp_i2c10, + msm_mux_blsp_i2c11, + msm_mux_blsp_i2c12, + msm_mux_blsp_spi1, + msm_mux_blsp_spi1_cs1, + msm_mux_blsp_spi1_cs2, + msm_mux_blsp_spi1_cs3, + msm_mux_blsp_spi2, + msm_mux_blsp_spi2_cs1, + msm_mux_blsp_spi2_cs2, + msm_mux_blsp_spi2_cs3, + msm_mux_blsp_spi3, + msm_mux_blsp_spi4, + msm_mux_blsp_spi5, + msm_mux_blsp_spi6, + msm_mux_blsp_spi7, + msm_mux_blsp_spi8, + msm_mux_blsp_spi9, + msm_mux_blsp_spi10, + msm_mux_blsp_spi10_cs1, + msm_mux_blsp_spi10_cs2, + msm_mux_blsp_spi10_cs3, + msm_mux_blsp_spi11, + msm_mux_blsp_spi12, + msm_mux_blsp_uart1, + msm_mux_blsp_uart2, + msm_mux_blsp_uart3, + msm_mux_blsp_uart4, + msm_mux_blsp_uart5, + msm_mux_blsp_uart6, + msm_mux_blsp_uart7, + msm_mux_blsp_uart8, + msm_mux_blsp_uart9, + msm_mux_blsp_uart10, + msm_mux_blsp_uart11, + msm_mux_blsp_uart12, + msm_mux_blsp_uim1, + msm_mux_blsp_uim2, + msm_mux_blsp_uim3, + msm_mux_blsp_uim4, + msm_mux_blsp_uim5, + msm_mux_blsp_uim6, + msm_mux_blsp_uim7, + msm_mux_blsp_uim8, + msm_mux_blsp_uim9, + msm_mux_blsp_uim10, + msm_mux_blsp_uim11, + msm_mux_blsp_uim12, + msm_mux_uim1, + msm_mux_uim2, + msm_mux_uim_batt_alarm, + msm_mux_sdc3, + msm_mux_sdc4, + msm_mux_gcc_gp_clk1, + msm_mux_gcc_gp_clk2, + msm_mux_gcc_gp_clk3, + msm_mux_qua_mi2s, + msm_mux_pri_mi2s, + msm_mux_spkr_mi2s, + msm_mux_ter_mi2s, + msm_mux_sec_mi2s, + msm_mux_hdmi_cec, + msm_mux_hdmi_ddc, + msm_mux_hdmi_hpd, + msm_mux_edp_hpd, + msm_mux_mdp_vsync, + msm_mux_cam_mclk0, + msm_mux_cam_mclk1, + msm_mux_cam_mclk2, + msm_mux_cam_mclk3, + msm_mux_cci_timer0, + msm_mux_cci_timer1, + msm_mux_cci_timer2, + msm_mux_cci_timer3, + msm_mux_cci_timer4, + msm_mux_cci_async_in0, + msm_mux_cci_async_in1, + msm_mux_cci_async_in2, + msm_mux_gp_pdm0, + msm_mux_gp_pdm1, + msm_mux_gp_pdm2, + msm_mux_gp0_clk, + msm_mux_gp1_clk, + msm_mux_gp_mn, + msm_mux_tsif1, + msm_mux_tsif2, + msm_mux_hsic, + msm_mux_grfc, + msm_mux_audio_ref_clk, + msm_mux_bt, + msm_mux_fm, + msm_mux_wlan, + msm_mux_slimbus, + msm_mux_hsic_ctl, + msm_mux_NA, +}; + +static const char * const gpio_groups[] = { + "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7", + "gpio8", "gpio9", "gpio10", "gpio11", "gpio12", "gpio13", "gpio14", + "gpio15", "gpio16", "gpio17", "gpio18", "gpio19", "gpio20", "gpio21", + "gpio22", "gpio23", "gpio24", "gpio25", "gpio26", "gpio27", "gpio28", + "gpio29", "gpio30", "gpio31", "gpio32", "gpio33", "gpio34", "gpio35", + "gpio36", "gpio37", "gpio38", "gpio39", "gpio40", "gpio41", "gpio42", + "gpio43", "gpio44", "gpio45", "gpio46", "gpio47", "gpio48", "gpio49", + "gpio50", "gpio51", "gpio52", "gpio53", "gpio54", "gpio55", "gpio56", + "gpio57", "gpio58", "gpio59", "gpio60", "gpio61", "gpio62", "gpio63", + "gpio64", "gpio65", "gpio66", "gpio67", "gpio68", "gpio69", "gpio70", + "gpio71", "gpio72", "gpio73", "gpio74", "gpio75", "gpio76", "gpio77", + "gpio78", "gpio79", "gpio80", "gpio81", "gpio82", "gpio83", "gpio84", + "gpio85", "gpio86", "gpio87", "gpio88", "gpio89", "gpio90", "gpio91", + "gpio92", "gpio93", "gpio94", "gpio95", "gpio96", "gpio97", "gpio98", + "gpio99", "gpio100", "gpio101", "gpio102", "gpio103", "gpio104", + "gpio105", "gpio106", "gpio107", "gpio108", "gpio109", "gpio110", + "gpio111", "gpio112", "gpio113", "gpio114", "gpio115", "gpio116", + "gpio117", "gpio118", "gpio119", "gpio120", "gpio121", "gpio122", + "gpio123", "gpio124", "gpio125", "gpio126", "gpio127", "gpio128", + "gpio129", "gpio130", "gpio131", "gpio132", "gpio133", "gpio134", + "gpio135", "gpio136", "gpio137", "gpio138", "gpio139", "gpio140", + "gpio141", "gpio142", "gpio143", "gpio144", "gpio145", "hsic_data", + "hsic_strobe", +}; + +static const char * const blsp_uart1_groups[] = { + "gpio0", "gpio1", "gpio2", "gpio3" +}; +static const char * const blsp_uim1_groups[] = { "gpio0", "gpio1" }; +static const char * const blsp_i2c1_groups[] = { "gpio2", "gpio3" }; +static const char * const blsp_spi1_groups[] = { + "gpio0", "gpio1", "gpio2", "gpio3" +}; +static const char * const blsp_spi1_cs1_groups[] = { "gpio8" }; +static const char * const blsp_spi1_cs2_groups[] = { "gpio9", "gpio11" }; +static const char * const blsp_spi1_cs3_groups[] = { "gpio10" }; + +static const char * const blsp_uart2_groups[] = { + "gpio4", "gpio5", "gpio6", "gpio7" +}; +static const char * const blsp_uim2_groups[] = { "gpio4", "gpio5" }; +static const char * const blsp_i2c2_groups[] = { "gpio6", "gpio7" }; +static const char * const blsp_spi2_groups[] = { + "gpio4", "gpio5", "gpio6", "gpio7" +}; +static const char * const blsp_spi2_cs1_groups[] = { "gpio53", "gpio62" }; +static const char * const blsp_spi2_cs2_groups[] = { "gpio54", "gpio63" }; +static const char * const blsp_spi2_cs3_groups[] = { "gpio66" }; + +static const char * const blsp_uart3_groups[] = { + "gpio8", "gpio9", "gpio10", "gpio11" +}; +static const char * const blsp_uim3_groups[] = { "gpio8", "gpio9" }; +static const char * const blsp_i2c3_groups[] = { "gpio10", "gpio11" }; +static const char * const blsp_spi3_groups[] = { + "gpio8", "gpio9", "gpio10", "gpio11" +}; + +static const char * const cci_i2c0_groups[] = { "gpio19", "gpio20" }; +static const char * const cci_i2c1_groups[] = { "gpio21", "gpio22" }; + +static const char * const blsp_uart4_groups[] = { + "gpio19", "gpio20", "gpio21", "gpio22" +}; +static const char * const blsp_uim4_groups[] = { "gpio19", "gpio20" }; +static const char * const blsp_i2c4_groups[] = { "gpio21", "gpio22" }; +static const char * const blsp_spi4_groups[] = { + "gpio19", "gpio20", "gpio21", "gpio22" +}; + +static const char * const blsp_uart5_groups[] = { + "gpio23", "gpio24", "gpio25", "gpio26" +}; +static const char * const blsp_uim5_groups[] = { "gpio23", "gpio24" }; +static const char * const blsp_i2c5_groups[] = { "gpio25", "gpio26" }; +static const char * const blsp_spi5_groups[] = { + "gpio23", "gpio24", "gpio25", "gpio26" +}; + +static const char * const blsp_uart6_groups[] = { + "gpio27", "gpio28", "gpio29", "gpio30" +}; +static const char * const blsp_uim6_groups[] = { "gpio27", "gpio28" }; +static const char * const blsp_i2c6_groups[] = { "gpio29", "gpio30" }; +static const char * const blsp_spi6_groups[] = { + "gpio27", "gpio28", "gpio29", "gpio30" +}; + +static const char * const blsp_uart7_groups[] = { + "gpio41", "gpio42", "gpio43", "gpio44" +}; +static const char * const blsp_uim7_groups[] = { "gpio41", "gpio42" }; +static const char * const blsp_i2c7_groups[] = { "gpio43", "gpio44" }; +static const char * const blsp_spi7_groups[] = { + "gpio41", "gpio42", "gpio43", "gpio44" +}; + +static const char * const blsp_uart8_groups[] = { + "gpio45", "gpio46", "gpio47", "gpio48" +}; +static const char * const blsp_uim8_groups[] = { "gpio45", "gpio46" }; +static const char * const blsp_i2c8_groups[] = { "gpio47", "gpio48" }; +static const char * const blsp_spi8_groups[] = { + "gpio45", "gpio46", "gpio47", "gpio48" +}; + +static const char * const blsp_uart9_groups[] = { + "gpio49", "gpio50", "gpio51", "gpio52" +}; +static const char * const blsp_uim9_groups[] = { "gpio49", "gpio50" }; +static const char * const blsp_i2c9_groups[] = { "gpio51", "gpio52" }; +static const char * const blsp_spi9_groups[] = { + "gpio49", "gpio50", "gpio51", "gpio52" +}; + +static const char * const blsp_uart10_groups[] = { + "gpio53", "gpio54", "gpio55", "gpio56" +}; +static const char * const blsp_uim10_groups[] = { "gpio53", "gpio54" }; +static const char * const blsp_i2c10_groups[] = { "gpio55", "gpio56" }; +static const char * const blsp_spi10_groups[] = { + "gpio53", "gpio54", "gpio55", "gpio56" +}; +static const char * const blsp_spi10_cs1_groups[] = { "gpio47", "gpio67" }; +static const char * const blsp_spi10_cs2_groups[] = { "gpio48", "gpio68" }; +static const char * const blsp_spi10_cs3_groups[] = { "gpio90" }; + +static const char * const blsp_uart11_groups[] = { + "gpio81", "gpio82", "gpio83", "gpio84" +}; +static const char * const blsp_uim11_groups[] = { "gpio81", "gpio82" }; +static const char * const blsp_i2c11_groups[] = { "gpio83", "gpio84" }; +static const char * const blsp_spi11_groups[] = { + "gpio81", "gpio82", "gpio83", "gpio84" +}; + +static const char * const blsp_uart12_groups[] = { + "gpio85", "gpio86", "gpio87", "gpio88" +}; +static const char * const blsp_uim12_groups[] = { "gpio85", "gpio86" }; +static const char * const blsp_i2c12_groups[] = { "gpio87", "gpio88" }; +static const char * const blsp_spi12_groups[] = { + "gpio85", "gpio86", "gpio87", "gpio88" +}; + +static const char * const uim1_groups[] = { + "gpio97", "gpio98", "gpio99", "gpio100" +}; + +static const char * const uim2_groups[] = { + "gpio49", "gpio50", "gpio51", "gpio52" +}; + +static const char * const uim_batt_alarm_groups[] = { "gpio101" }; + +static const char * const sdc3_groups[] = { + "gpio35", "gpio36", "gpio37", "gpio38", "gpio39", "gpio40" +}; + +static const char * const sdc4_groups[] = { + "gpio91", "gpio92", "gpio93", "gpio94", "gpio95", "gpio96" +}; + +static const char * const gp0_clk_groups[] = { "gpio26" }; +static const char * const gp1_clk_groups[] = { "gpio27", "gpio57", "gpio78" }; +static const char * const gp_mn_groups[] = { "gpio29" }; +static const char * const gcc_gp_clk1_groups[] = { "gpio57", "gpio78" }; +static const char * const gcc_gp_clk2_groups[] = { "gpio58", "gpio81" }; +static const char * const gcc_gp_clk3_groups[] = { "gpio59", "gpio82" }; + +static const char * const qua_mi2s_groups[] = { + "gpio57", "gpio58", "gpio59", "gpio60", "gpio61", "gpio62", "gpio63", +}; + +static const char * const pri_mi2s_groups[] = { + "gpio64", "gpio65", "gpio66", "gpio67", "gpio68" +}; + +static const char * const spkr_mi2s_groups[] = { + "gpio69", "gpio70", "gpio71", "gpio72" +}; + +static const char * const ter_mi2s_groups[] = { + "gpio73", "gpio74", "gpio75", "gpio76", "gpio77" +}; + +static const char * const sec_mi2s_groups[] = { + "gpio78", "gpio79", "gpio80", "gpio81", "gpio82" +}; + +static const char * const hdmi_cec_groups[] = { "gpio31" }; +static const char * const hdmi_ddc_groups[] = { "gpio32", "gpio33" }; +static const char * const hdmi_hpd_groups[] = { "gpio34" }; +static const char * const edp_hpd_groups[] = { "gpio102" }; + +static const char * const mdp_vsync_groups[] = { "gpio12", "gpio13", "gpio14" }; +static const char * const cam_mclk0_groups[] = { "gpio15" }; +static const char * const cam_mclk1_groups[] = { "gpio16" }; +static const char * const cam_mclk2_groups[] = { "gpio17" }; +static const char * const cam_mclk3_groups[] = { "gpio18" }; + +static const char * const cci_timer0_groups[] = { "gpio23" }; +static const char * const cci_timer1_groups[] = { "gpio24" }; +static const char * const cci_timer2_groups[] = { "gpio25" }; +static const char * const cci_timer3_groups[] = { "gpio26" }; +static const char * const cci_timer4_groups[] = { "gpio27" }; +static const char * const cci_async_in0_groups[] = { "gpio28" }; +static const char * const cci_async_in1_groups[] = { "gpio26" }; +static const char * const cci_async_in2_groups[] = { "gpio27" }; + +static const char * const gp_pdm0_groups[] = { "gpio54", "gpio68" }; +static const char * const gp_pdm1_groups[] = { "gpio74", "gpio86" }; +static const char * const gp_pdm2_groups[] = { "gpio63", "gpio79" }; + +static const char * const tsif1_groups[] = { + "gpio89", "gpio90", "gpio91", "gpio92" +}; + +static const char * const tsif2_groups[] = { + "gpio93", "gpio94", "gpio95", "gpio96" +}; + +static const char * const hsic_groups[] = { "gpio144", "gpio145" }; +static const char * const grfc_groups[] = { + "gpio104", "gpio105", "gpio106", "gpio107", "gpio108", "gpio109", + "gpio110", "gpio111", "gpio112", "gpio113", "gpio114", "gpio115", + "gpio116", "gpio117", "gpio118", "gpio119", "gpio120", "gpio121", + "gpio122", "gpio123", "gpio124", "gpio125", "gpio126", "gpio127", + "gpio128", "gpio136", "gpio137", "gpio141", "gpio143" +}; + +static const char * const audio_ref_clk_groups[] = { "gpio69" }; + +static const char * const bt_groups[] = { "gpio35", "gpio43", "gpio44" }; + +static const char * const fm_groups[] = { "gpio41", "gpio42" }; + +static const char * const wlan_groups[] = { + "gpio36", "gpio37", "gpio38", "gpio39", "gpio40" +}; + +static const char * const slimbus_groups[] = { "gpio70", "gpio71" }; +static const char * const hsic_ctl_groups[] = { "hsic_strobe", "hsic_data" }; + +static const struct pinfunction msm8x74_functions[] = { + MSM_PIN_FUNCTION(gpio), + MSM_PIN_FUNCTION(cci_i2c0), + MSM_PIN_FUNCTION(cci_i2c1), + MSM_PIN_FUNCTION(uim1), + MSM_PIN_FUNCTION(uim2), + MSM_PIN_FUNCTION(uim_batt_alarm), + MSM_PIN_FUNCTION(blsp_uim1), + MSM_PIN_FUNCTION(blsp_uim2), + MSM_PIN_FUNCTION(blsp_uim3), + MSM_PIN_FUNCTION(blsp_uim4), + MSM_PIN_FUNCTION(blsp_uim5), + MSM_PIN_FUNCTION(blsp_uim6), + MSM_PIN_FUNCTION(blsp_uim7), + MSM_PIN_FUNCTION(blsp_uim8), + MSM_PIN_FUNCTION(blsp_uim9), + MSM_PIN_FUNCTION(blsp_uim10), + MSM_PIN_FUNCTION(blsp_uim11), + MSM_PIN_FUNCTION(blsp_uim12), + MSM_PIN_FUNCTION(blsp_i2c1), + MSM_PIN_FUNCTION(blsp_i2c2), + MSM_PIN_FUNCTION(blsp_i2c3), + MSM_PIN_FUNCTION(blsp_i2c4), + MSM_PIN_FUNCTION(blsp_i2c5), + MSM_PIN_FUNCTION(blsp_i2c6), + MSM_PIN_FUNCTION(blsp_i2c7), + MSM_PIN_FUNCTION(blsp_i2c8), + MSM_PIN_FUNCTION(blsp_i2c9), + MSM_PIN_FUNCTION(blsp_i2c10), + MSM_PIN_FUNCTION(blsp_i2c11), + MSM_PIN_FUNCTION(blsp_i2c12), + MSM_PIN_FUNCTION(blsp_spi1), + MSM_PIN_FUNCTION(blsp_spi1_cs1), + MSM_PIN_FUNCTION(blsp_spi1_cs2), + MSM_PIN_FUNCTION(blsp_spi1_cs3), + MSM_PIN_FUNCTION(blsp_spi2), + MSM_PIN_FUNCTION(blsp_spi2_cs1), + MSM_PIN_FUNCTION(blsp_spi2_cs2), + MSM_PIN_FUNCTION(blsp_spi2_cs3), + MSM_PIN_FUNCTION(blsp_spi3), + MSM_PIN_FUNCTION(blsp_spi4), + MSM_PIN_FUNCTION(blsp_spi5), + MSM_PIN_FUNCTION(blsp_spi6), + MSM_PIN_FUNCTION(blsp_spi7), + MSM_PIN_FUNCTION(blsp_spi8), + MSM_PIN_FUNCTION(blsp_spi9), + MSM_PIN_FUNCTION(blsp_spi10), + MSM_PIN_FUNCTION(blsp_spi10_cs1), + MSM_PIN_FUNCTION(blsp_spi10_cs2), + MSM_PIN_FUNCTION(blsp_spi10_cs3), + MSM_PIN_FUNCTION(blsp_spi11), + MSM_PIN_FUNCTION(blsp_spi12), + MSM_PIN_FUNCTION(blsp_uart1), + MSM_PIN_FUNCTION(blsp_uart2), + MSM_PIN_FUNCTION(blsp_uart3), + MSM_PIN_FUNCTION(blsp_uart4), + MSM_PIN_FUNCTION(blsp_uart5), + MSM_PIN_FUNCTION(blsp_uart6), + MSM_PIN_FUNCTION(blsp_uart7), + MSM_PIN_FUNCTION(blsp_uart8), + MSM_PIN_FUNCTION(blsp_uart9), + MSM_PIN_FUNCTION(blsp_uart10), + MSM_PIN_FUNCTION(blsp_uart11), + MSM_PIN_FUNCTION(blsp_uart12), + MSM_PIN_FUNCTION(sdc3), + MSM_PIN_FUNCTION(sdc4), + MSM_PIN_FUNCTION(gcc_gp_clk1), + MSM_PIN_FUNCTION(gcc_gp_clk2), + MSM_PIN_FUNCTION(gcc_gp_clk3), + MSM_PIN_FUNCTION(qua_mi2s), + MSM_PIN_FUNCTION(pri_mi2s), + MSM_PIN_FUNCTION(spkr_mi2s), + MSM_PIN_FUNCTION(ter_mi2s), + MSM_PIN_FUNCTION(sec_mi2s), + MSM_PIN_FUNCTION(mdp_vsync), + MSM_PIN_FUNCTION(cam_mclk0), + MSM_PIN_FUNCTION(cam_mclk1), + MSM_PIN_FUNCTION(cam_mclk2), + MSM_PIN_FUNCTION(cam_mclk3), + MSM_PIN_FUNCTION(cci_timer0), + MSM_PIN_FUNCTION(cci_timer1), + MSM_PIN_FUNCTION(cci_timer2), + MSM_PIN_FUNCTION(cci_timer3), + MSM_PIN_FUNCTION(cci_timer4), + MSM_PIN_FUNCTION(cci_async_in0), + MSM_PIN_FUNCTION(cci_async_in1), + MSM_PIN_FUNCTION(cci_async_in2), + MSM_PIN_FUNCTION(hdmi_cec), + MSM_PIN_FUNCTION(hdmi_ddc), + MSM_PIN_FUNCTION(hdmi_hpd), + MSM_PIN_FUNCTION(edp_hpd), + MSM_PIN_FUNCTION(gp_pdm0), + MSM_PIN_FUNCTION(gp_pdm1), + MSM_PIN_FUNCTION(gp_pdm2), + MSM_PIN_FUNCTION(gp0_clk), + MSM_PIN_FUNCTION(gp1_clk), + MSM_PIN_FUNCTION(gp_mn), + MSM_PIN_FUNCTION(tsif1), + MSM_PIN_FUNCTION(tsif2), + MSM_PIN_FUNCTION(hsic), + MSM_PIN_FUNCTION(grfc), + MSM_PIN_FUNCTION(audio_ref_clk), + MSM_PIN_FUNCTION(bt), + MSM_PIN_FUNCTION(fm), + MSM_PIN_FUNCTION(wlan), + MSM_PIN_FUNCTION(slimbus), + MSM_PIN_FUNCTION(hsic_ctl), +}; + +static const struct msm_pingroup msm8x74_groups[] = { + PINGROUP(0, blsp_spi1, blsp_uart1, blsp_uim1, NA, NA, NA, NA), + PINGROUP(1, blsp_spi1, blsp_uart1, blsp_uim1, NA, NA, NA, NA), + PINGROUP(2, blsp_spi1, blsp_uart1, blsp_i2c1, NA, NA, NA, NA), + PINGROUP(3, blsp_spi1, blsp_uart1, blsp_i2c1, NA, NA, NA, NA), + PINGROUP(4, blsp_spi2, blsp_uart2, blsp_uim2, NA, NA, NA, NA), + PINGROUP(5, blsp_spi2, blsp_uart2, blsp_uim2, NA, NA, NA, NA), + PINGROUP(6, blsp_spi2, blsp_uart2, blsp_i2c2, NA, NA, NA, NA), + PINGROUP(7, blsp_spi2, blsp_uart2, blsp_i2c2, NA, NA, NA, NA), + PINGROUP(8, blsp_spi3, blsp_uart3, blsp_uim3, blsp_spi1_cs1, NA, NA, NA), + PINGROUP(9, blsp_spi3, blsp_uart3, blsp_uim3, blsp_spi1_cs2, NA, NA, NA), + PINGROUP(10, blsp_spi3, blsp_uart3, blsp_i2c3, blsp_spi1_cs3, NA, NA, NA), + PINGROUP(11, blsp_spi3, blsp_uart3, blsp_i2c3, blsp_spi1_cs2, NA, NA, NA), + PINGROUP(12, mdp_vsync, NA, NA, NA, NA, NA, NA), + PINGROUP(13, mdp_vsync, NA, NA, NA, NA, NA, NA), + PINGROUP(14, mdp_vsync, NA, NA, NA, NA, NA, NA), + PINGROUP(15, cam_mclk0, NA, NA, NA, NA, NA, NA), + PINGROUP(16, cam_mclk1, NA, NA, NA, NA, NA, NA), + PINGROUP(17, cam_mclk2, NA, NA, NA, NA, NA, NA), + PINGROUP(18, cam_mclk3, NA, NA, NA, NA, NA, NA), + PINGROUP(19, cci_i2c0, blsp_spi4, blsp_uart4, blsp_uim4, NA, NA, NA), + PINGROUP(20, cci_i2c0, blsp_spi4, blsp_uart4, blsp_uim4, NA, NA, NA), + PINGROUP(21, cci_i2c1, blsp_spi4, blsp_uart4, blsp_i2c4, NA, NA, NA), + PINGROUP(22, cci_i2c1, blsp_spi4, blsp_uart4, blsp_i2c4, NA, NA, NA), + PINGROUP(23, cci_timer0, blsp_spi5, blsp_uart5, blsp_uim5, NA, NA, NA), + PINGROUP(24, cci_timer1, blsp_spi5, blsp_uart5, blsp_uim5, NA, NA, NA), + PINGROUP(25, cci_timer2, blsp_spi5, blsp_uart5, blsp_i2c5, NA, NA, NA), + PINGROUP(26, cci_timer3, cci_async_in1, blsp_spi5, blsp_uart5, blsp_i2c5, gp0_clk, NA), + PINGROUP(27, cci_timer4, cci_async_in2, blsp_spi6, blsp_uart6, blsp_i2c6, gp1_clk, NA), + PINGROUP(28, cci_async_in0, blsp_spi6, blsp_uart6, blsp_uim6, NA, NA, NA), + PINGROUP(29, blsp_spi6, blsp_uart6, blsp_i2c6, gp_mn, NA, NA, NA), + PINGROUP(30, blsp_spi6, blsp_uart6, blsp_i2c6, NA, NA, NA, NA), + PINGROUP(31, hdmi_cec, NA, NA, NA, NA, NA, NA), + PINGROUP(32, hdmi_ddc, NA, NA, NA, NA, NA, NA), + PINGROUP(33, hdmi_ddc, NA, NA, NA, NA, NA, NA), + PINGROUP(34, hdmi_hpd, NA, NA, NA, NA, NA, NA), + PINGROUP(35, bt, sdc3, NA, NA, NA, NA, NA), + PINGROUP(36, wlan, sdc3, NA, NA, NA, NA, NA), + PINGROUP(37, wlan, sdc3, NA, NA, NA, NA, NA), + PINGROUP(38, wlan, sdc3, NA, NA, NA, NA, NA), + PINGROUP(39, wlan, sdc3, NA, NA, NA, NA, NA), + PINGROUP(40, wlan, sdc3, NA, NA, NA, NA, NA), + PINGROUP(41, fm, blsp_spi7, blsp_uart7, blsp_uim7, NA, NA, NA), + PINGROUP(42, fm, blsp_spi7, blsp_uart7, blsp_uim7, NA, NA, NA), + PINGROUP(43, bt, blsp_spi7, blsp_uart7, blsp_i2c7, NA, NA, NA), + PINGROUP(44, bt, blsp_spi7, blsp_uart7, blsp_i2c7, NA, NA, NA), + PINGROUP(45, blsp_spi8, blsp_uart8, blsp_uim8, NA, NA, NA, NA), + PINGROUP(46, blsp_spi8, blsp_uart8, blsp_uim8, NA, NA, NA, NA), + PINGROUP(47, blsp_spi8, blsp_uart8, blsp_i2c8, blsp_spi10_cs1, NA, NA, NA), + PINGROUP(48, blsp_spi8, blsp_uart8, blsp_i2c8, blsp_spi10_cs2, NA, NA, NA), + PINGROUP(49, uim2, blsp_spi9, blsp_uart9, blsp_uim9, NA, NA, NA), + PINGROUP(50, uim2, blsp_spi9, blsp_uart9, blsp_uim9, NA, NA, NA), + PINGROUP(51, uim2, blsp_spi9, blsp_uart9, blsp_i2c9, NA, NA, NA), + PINGROUP(52, uim2, blsp_spi9, blsp_uart9, blsp_i2c9, NA, NA, NA), + PINGROUP(53, blsp_spi10, blsp_uart10, blsp_uim10, blsp_spi2_cs1, NA, NA, NA), + PINGROUP(54, blsp_spi10, blsp_uart10, blsp_uim10, blsp_spi2_cs2, gp_pdm0, NA, NA), + PINGROUP(55, blsp_spi10, blsp_uart10, blsp_i2c10, NA, NA, NA, NA), + PINGROUP(56, blsp_spi10, blsp_uart10, blsp_i2c10, NA, NA, NA, NA), + PINGROUP(57, qua_mi2s, gcc_gp_clk1, NA, NA, NA, NA, NA), + PINGROUP(58, qua_mi2s, gcc_gp_clk2, NA, NA, NA, NA, NA), + PINGROUP(59, qua_mi2s, gcc_gp_clk3, NA, NA, NA, NA, NA), + PINGROUP(60, qua_mi2s, NA, NA, NA, NA, NA, NA), + PINGROUP(61, qua_mi2s, NA, NA, NA, NA, NA, NA), + PINGROUP(62, qua_mi2s, blsp_spi2_cs1, NA, NA, NA, NA, NA), + PINGROUP(63, qua_mi2s, blsp_spi2_cs2, gp_pdm2, NA, NA, NA, NA), + PINGROUP(64, pri_mi2s, NA, NA, NA, NA, NA, NA), + PINGROUP(65, pri_mi2s, NA, NA, NA, NA, NA, NA), + PINGROUP(66, pri_mi2s, blsp_spi2_cs3, NA, NA, NA, NA, NA), + PINGROUP(67, pri_mi2s, blsp_spi10_cs1, NA, NA, NA, NA, NA), + PINGROUP(68, pri_mi2s, blsp_spi10_cs2, gp_pdm0, NA, NA, NA, NA), + PINGROUP(69, spkr_mi2s, audio_ref_clk, NA, NA, NA, NA, NA), + PINGROUP(70, slimbus, spkr_mi2s, NA, NA, NA, NA, NA), + PINGROUP(71, slimbus, spkr_mi2s, NA, NA, NA, NA, NA), + PINGROUP(72, spkr_mi2s, NA, NA, NA, NA, NA, NA), + PINGROUP(73, ter_mi2s, NA, NA, NA, NA, NA, NA), + PINGROUP(74, ter_mi2s, gp_pdm1, NA, NA, NA, NA, NA), + PINGROUP(75, ter_mi2s, NA, NA, NA, NA, NA, NA), + PINGROUP(76, ter_mi2s, NA, NA, NA, NA, NA, NA), + PINGROUP(77, ter_mi2s, NA, NA, NA, NA, NA, NA), + PINGROUP(78, sec_mi2s, gcc_gp_clk1, NA, NA, NA, NA, NA), + PINGROUP(79, sec_mi2s, gp_pdm2, NA, NA, NA, NA, NA), + PINGROUP(80, sec_mi2s, NA, NA, NA, NA, NA, NA), + PINGROUP(81, sec_mi2s, blsp_spi11, blsp_uart11, blsp_uim11, gcc_gp_clk2, NA, NA), + PINGROUP(82, sec_mi2s, blsp_spi11, blsp_uart11, blsp_uim11, gcc_gp_clk3, NA, NA), + PINGROUP(83, blsp_spi11, blsp_uart11, blsp_i2c11, NA, NA, NA, NA), + PINGROUP(84, blsp_spi11, blsp_uart11, blsp_i2c11, NA, NA, NA, NA), + PINGROUP(85, blsp_spi12, blsp_uart12, blsp_uim12, NA, NA, NA, NA), + PINGROUP(86, blsp_spi12, blsp_uart12, blsp_uim12, gp_pdm1, NA, NA, NA), + PINGROUP(87, blsp_spi12, blsp_uart12, blsp_i2c12, NA, NA, NA, NA), + PINGROUP(88, blsp_spi12, blsp_uart12, blsp_i2c12, NA, NA, NA, NA), + PINGROUP(89, tsif1, NA, NA, NA, NA, NA, NA), + PINGROUP(90, tsif1, blsp_spi10_cs3, NA, NA, NA, NA, NA), + PINGROUP(91, tsif1, sdc4, NA, NA, NA, NA, NA), + PINGROUP(92, tsif1, sdc4, NA, NA, NA, NA, NA), + PINGROUP(93, tsif2, sdc4, NA, NA, NA, NA, NA), + PINGROUP(94, tsif2, sdc4, NA, NA, NA, NA, NA), + PINGROUP(95, tsif2, sdc4, NA, NA, NA, NA, NA), + PINGROUP(96, tsif2, sdc4, NA, NA, NA, NA, NA), + PINGROUP(97, uim1, NA, NA, NA, NA, NA, NA), + PINGROUP(98, uim1, NA, NA, NA, NA, NA, NA), + PINGROUP(99, uim1, NA, NA, NA, NA, NA, NA), + PINGROUP(100, uim1, NA, NA, NA, NA, NA, NA), + PINGROUP(101, uim_batt_alarm, NA, NA, NA, NA, NA, NA), + PINGROUP(102, edp_hpd, NA, NA, NA, NA, NA, NA), + PINGROUP(103, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(104, grfc, NA, NA, NA, NA, NA, NA), + PINGROUP(105, grfc, NA, NA, NA, NA, NA, NA), + PINGROUP(106, grfc, NA, NA, NA, NA, NA, NA), + PINGROUP(107, grfc, NA, NA, NA, NA, NA, NA), + PINGROUP(108, grfc, NA, NA, NA, NA, NA, NA), + PINGROUP(109, grfc, NA, NA, NA, NA, NA, NA), + PINGROUP(110, grfc, NA, NA, NA, NA, NA, NA), + PINGROUP(111, grfc, NA, NA, NA, NA, NA, NA), + PINGROUP(112, grfc, NA, NA, NA, NA, NA, NA), + PINGROUP(113, grfc, NA, NA, NA, NA, NA, NA), + PINGROUP(114, grfc, NA, NA, NA, NA, NA, NA), + PINGROUP(115, grfc, NA, NA, NA, NA, NA, NA), + PINGROUP(116, grfc, NA, NA, NA, NA, NA, NA), + PINGROUP(117, grfc, NA, NA, NA, NA, NA, NA), + PINGROUP(118, grfc, NA, NA, NA, NA, NA, NA), + PINGROUP(119, grfc, NA, NA, NA, NA, NA, NA), + PINGROUP(120, grfc, NA, NA, NA, NA, NA, NA), + PINGROUP(121, grfc, NA, NA, NA, NA, NA, NA), + PINGROUP(122, grfc, NA, NA, NA, NA, NA, NA), + PINGROUP(123, grfc, NA, NA, NA, NA, NA, NA), + PINGROUP(124, grfc, NA, NA, NA, NA, NA, NA), + PINGROUP(125, grfc, NA, NA, NA, NA, NA, NA), + PINGROUP(126, grfc, NA, NA, NA, NA, NA, NA), + PINGROUP(127, grfc, NA, NA, NA, NA, NA, NA), + PINGROUP(128, NA, grfc, NA, NA, NA, NA, NA), + PINGROUP(129, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(130, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(131, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(132, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(133, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(134, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(135, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(136, NA, grfc, NA, NA, NA, NA, NA), + PINGROUP(137, NA, grfc, NA, NA, NA, NA, NA), + PINGROUP(138, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(139, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(140, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(141, NA, grfc, NA, NA, NA, NA, NA), + PINGROUP(142, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(143, NA, grfc, NA, NA, NA, NA, NA), + PINGROUP(144, hsic, NA, NA, NA, NA, NA, NA), + PINGROUP(145, hsic, NA, NA, NA, NA, NA, NA), + SDC_PINGROUP(sdc1_clk, 0x2044, 13, 6), + SDC_PINGROUP(sdc1_cmd, 0x2044, 11, 3), + SDC_PINGROUP(sdc1_data, 0x2044, 9, 0), + SDC_PINGROUP(sdc2_clk, 0x2048, 14, 6), + SDC_PINGROUP(sdc2_cmd, 0x2048, 11, 3), + SDC_PINGROUP(sdc2_data, 0x2048, 9, 0), + HSIC_PINGROUP(hsic_strobe, 0x2050), + HSIC_PINGROUP(hsic_data, 0x2054), +}; + +#define NUM_GPIO_PINGROUPS 146 + +static const struct msm_pinctrl_soc_data msm8x74_pinctrl = { + .pins = msm8x74_pins, + .npins = ARRAY_SIZE(msm8x74_pins), + .functions = msm8x74_functions, + .nfunctions = ARRAY_SIZE(msm8x74_functions), + .groups = msm8x74_groups, + .ngroups = ARRAY_SIZE(msm8x74_groups), + .ngpios = NUM_GPIO_PINGROUPS, +}; + +static int msm8x74_pinctrl_probe(struct platform_device *pdev) +{ + return msm_pinctrl_probe(pdev, &msm8x74_pinctrl); +} + +static const struct of_device_id msm8x74_pinctrl_of_match[] = { + { .compatible = "qcom,msm8974-pinctrl", }, + { }, +}; + +static struct platform_driver msm8x74_pinctrl_driver = { + .driver = { + .name = "msm8x74-pinctrl", + .of_match_table = msm8x74_pinctrl_of_match, + }, + .probe = msm8x74_pinctrl_probe, + .remove = msm_pinctrl_remove, +}; + +static int __init msm8x74_pinctrl_init(void) +{ + return platform_driver_register(&msm8x74_pinctrl_driver); +} +arch_initcall(msm8x74_pinctrl_init); + +static void __exit msm8x74_pinctrl_exit(void) +{ + platform_driver_unregister(&msm8x74_pinctrl_driver); +} +module_exit(msm8x74_pinctrl_exit); + +MODULE_AUTHOR("Bjorn Andersson <bjorn.andersson@sonymobile.com>"); +MODULE_DESCRIPTION("Qualcomm MSM8x74 pinctrl driver"); +MODULE_LICENSE("GPL v2"); +MODULE_DEVICE_TABLE(of, msm8x74_pinctrl_of_match); + diff --git a/drivers/pinctrl/qcom/pinctrl-qcm2290.c b/drivers/pinctrl/qcom/pinctrl-qcm2290.c new file mode 100644 index 0000000000..ba699eac9e --- /dev/null +++ b/drivers/pinctrl/qcom/pinctrl-qcm2290.c @@ -0,0 +1,1133 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2019-2020, The Linux Foundation. All rights reserved. + */ + +#include <linux/module.h> +#include <linux/of.h> +#include <linux/platform_device.h> + +#include "pinctrl-msm.h" + +#define REG_SIZE 0x1000 + +#define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7, f8, f9) \ + { \ + .grp = PINCTRL_PINGROUP("gpio" #id, \ + gpio##id##_pins, \ + ARRAY_SIZE(gpio##id##_pins)), \ + .funcs = (int[]){ \ + msm_mux_gpio, /* gpio mode */ \ + msm_mux_##f1, \ + msm_mux_##f2, \ + msm_mux_##f3, \ + msm_mux_##f4, \ + msm_mux_##f5, \ + msm_mux_##f6, \ + msm_mux_##f7, \ + msm_mux_##f8, \ + msm_mux_##f9 \ + }, \ + .nfuncs = 10, \ + .ctl_reg = REG_SIZE * id, \ + .io_reg = 0x4 + REG_SIZE * id, \ + .intr_cfg_reg = 0x8 + REG_SIZE * id, \ + .intr_status_reg = 0xc + REG_SIZE * id, \ + .intr_target_reg = 0x8 + REG_SIZE * id, \ + .mux_bit = 2, \ + .pull_bit = 0, \ + .drv_bit = 6, \ + .oe_bit = 9, \ + .in_bit = 0, \ + .out_bit = 1, \ + .intr_enable_bit = 0, \ + .intr_status_bit = 0, \ + .intr_target_bit = 5, \ + .intr_target_kpss_val = 3, \ + .intr_raw_status_bit = 4, \ + .intr_polarity_bit = 1, \ + .intr_detection_bit = 2, \ + .intr_detection_width = 2, \ + } + +#define SDC_QDSD_PINGROUP(pg_name, ctl, pull, drv) \ + { \ + .grp = PINCTRL_PINGROUP(#pg_name, \ + pg_name##_pins, \ + ARRAY_SIZE(pg_name##_pins)), \ + .ctl_reg = ctl, \ + .io_reg = 0, \ + .intr_cfg_reg = 0, \ + .intr_status_reg = 0, \ + .intr_target_reg = 0, \ + .mux_bit = -1, \ + .pull_bit = pull, \ + .drv_bit = drv, \ + .oe_bit = -1, \ + .in_bit = -1, \ + .out_bit = -1, \ + .intr_enable_bit = -1, \ + .intr_status_bit = -1, \ + .intr_target_bit = -1, \ + .intr_raw_status_bit = -1, \ + .intr_polarity_bit = -1, \ + .intr_detection_bit = -1, \ + .intr_detection_width = -1, \ + } + +#define UFS_RESET(pg_name, offset) \ + { \ + .grp = PINCTRL_PINGROUP(#pg_name, \ + pg_name##_pins, \ + ARRAY_SIZE(pg_name##_pins)), \ + .ctl_reg = offset, \ + .io_reg = offset + 0x4, \ + .intr_cfg_reg = 0, \ + .intr_status_reg = 0, \ + .intr_target_reg = 0, \ + .mux_bit = -1, \ + .pull_bit = 3, \ + .drv_bit = 0, \ + .oe_bit = -1, \ + .in_bit = -1, \ + .out_bit = 0, \ + .intr_enable_bit = -1, \ + .intr_status_bit = -1, \ + .intr_target_bit = -1, \ + .intr_raw_status_bit = -1, \ + .intr_polarity_bit = -1, \ + .intr_detection_bit = -1, \ + .intr_detection_width = -1, \ + } +static const struct pinctrl_pin_desc qcm2290_pins[] = { + PINCTRL_PIN(0, "GPIO_0"), + PINCTRL_PIN(1, "GPIO_1"), + PINCTRL_PIN(2, "GPIO_2"), + PINCTRL_PIN(3, "GPIO_3"), + PINCTRL_PIN(4, "GPIO_4"), + PINCTRL_PIN(5, "GPIO_5"), + PINCTRL_PIN(6, "GPIO_6"), + PINCTRL_PIN(7, "GPIO_7"), + PINCTRL_PIN(8, "GPIO_8"), + PINCTRL_PIN(9, "GPIO_9"), + PINCTRL_PIN(10, "GPIO_10"), + PINCTRL_PIN(11, "GPIO_11"), + PINCTRL_PIN(12, "GPIO_12"), + PINCTRL_PIN(13, "GPIO_13"), + PINCTRL_PIN(14, "GPIO_14"), + PINCTRL_PIN(15, "GPIO_15"), + PINCTRL_PIN(16, "GPIO_16"), + PINCTRL_PIN(17, "GPIO_17"), + PINCTRL_PIN(18, "GPIO_18"), + PINCTRL_PIN(19, "GPIO_19"), + PINCTRL_PIN(20, "GPIO_20"), + PINCTRL_PIN(21, "GPIO_21"), + PINCTRL_PIN(22, "GPIO_22"), + PINCTRL_PIN(23, "GPIO_23"), + PINCTRL_PIN(24, "GPIO_24"), + PINCTRL_PIN(25, "GPIO_25"), + PINCTRL_PIN(26, "GPIO_26"), + PINCTRL_PIN(27, "GPIO_27"), + PINCTRL_PIN(28, "GPIO_28"), + PINCTRL_PIN(29, "GPIO_29"), + PINCTRL_PIN(30, "GPIO_30"), + PINCTRL_PIN(31, "GPIO_31"), + PINCTRL_PIN(32, "GPIO_32"), + PINCTRL_PIN(33, "GPIO_33"), + PINCTRL_PIN(34, "GPIO_34"), + PINCTRL_PIN(35, "GPIO_35"), + PINCTRL_PIN(36, "GPIO_36"), + PINCTRL_PIN(37, "GPIO_37"), + PINCTRL_PIN(38, "GPIO_38"), + PINCTRL_PIN(39, "GPIO_39"), + PINCTRL_PIN(40, "GPIO_40"), + PINCTRL_PIN(41, "GPIO_41"), + PINCTRL_PIN(42, "GPIO_42"), + PINCTRL_PIN(43, "GPIO_43"), + PINCTRL_PIN(44, "GPIO_44"), + PINCTRL_PIN(45, "GPIO_45"), + PINCTRL_PIN(46, "GPIO_46"), + PINCTRL_PIN(47, "GPIO_47"), + PINCTRL_PIN(48, "GPIO_48"), + PINCTRL_PIN(49, "GPIO_49"), + PINCTRL_PIN(50, "GPIO_50"), + PINCTRL_PIN(51, "GPIO_51"), + PINCTRL_PIN(52, "GPIO_52"), + PINCTRL_PIN(53, "GPIO_53"), + PINCTRL_PIN(54, "GPIO_54"), + PINCTRL_PIN(55, "GPIO_55"), + PINCTRL_PIN(56, "GPIO_56"), + PINCTRL_PIN(57, "GPIO_57"), + PINCTRL_PIN(58, "GPIO_58"), + PINCTRL_PIN(59, "GPIO_59"), + PINCTRL_PIN(60, "GPIO_60"), + PINCTRL_PIN(61, "GPIO_61"), + PINCTRL_PIN(62, "GPIO_62"), + PINCTRL_PIN(63, "GPIO_63"), + PINCTRL_PIN(64, "GPIO_64"), + PINCTRL_PIN(69, "GPIO_69"), + PINCTRL_PIN(70, "GPIO_70"), + PINCTRL_PIN(71, "GPIO_71"), + PINCTRL_PIN(72, "GPIO_72"), + PINCTRL_PIN(73, "GPIO_73"), + PINCTRL_PIN(74, "GPIO_74"), + PINCTRL_PIN(75, "GPIO_75"), + PINCTRL_PIN(76, "GPIO_76"), + PINCTRL_PIN(77, "GPIO_77"), + PINCTRL_PIN(78, "GPIO_78"), + PINCTRL_PIN(79, "GPIO_79"), + PINCTRL_PIN(80, "GPIO_80"), + PINCTRL_PIN(81, "GPIO_81"), + PINCTRL_PIN(82, "GPIO_82"), + PINCTRL_PIN(86, "GPIO_86"), + PINCTRL_PIN(87, "GPIO_87"), + PINCTRL_PIN(88, "GPIO_88"), + PINCTRL_PIN(89, "GPIO_89"), + PINCTRL_PIN(90, "GPIO_90"), + PINCTRL_PIN(91, "GPIO_91"), + PINCTRL_PIN(94, "GPIO_94"), + PINCTRL_PIN(95, "GPIO_95"), + PINCTRL_PIN(96, "GPIO_96"), + PINCTRL_PIN(97, "GPIO_97"), + PINCTRL_PIN(98, "GPIO_98"), + PINCTRL_PIN(99, "GPIO_99"), + PINCTRL_PIN(100, "GPIO_100"), + PINCTRL_PIN(101, "GPIO_101"), + PINCTRL_PIN(102, "GPIO_102"), + PINCTRL_PIN(103, "GPIO_103"), + PINCTRL_PIN(104, "GPIO_104"), + PINCTRL_PIN(105, "GPIO_105"), + PINCTRL_PIN(106, "GPIO_106"), + PINCTRL_PIN(107, "GPIO_107"), + PINCTRL_PIN(108, "GPIO_108"), + PINCTRL_PIN(109, "GPIO_109"), + PINCTRL_PIN(110, "GPIO_110"), + PINCTRL_PIN(111, "GPIO_111"), + PINCTRL_PIN(112, "GPIO_112"), + PINCTRL_PIN(113, "GPIO_113"), + PINCTRL_PIN(114, "GPIO_114"), + PINCTRL_PIN(115, "GPIO_115"), + PINCTRL_PIN(116, "GPIO_116"), + PINCTRL_PIN(117, "GPIO_117"), + PINCTRL_PIN(118, "GPIO_118"), + PINCTRL_PIN(119, "GPIO_119"), + PINCTRL_PIN(120, "GPIO_120"), + PINCTRL_PIN(121, "GPIO_121"), + PINCTRL_PIN(122, "GPIO_122"), + PINCTRL_PIN(123, "GPIO_123"), + PINCTRL_PIN(124, "GPIO_124"), + PINCTRL_PIN(125, "GPIO_125"), + PINCTRL_PIN(126, "GPIO_126"), + PINCTRL_PIN(127, "SDC1_RCLK"), + PINCTRL_PIN(128, "SDC1_CLK"), + PINCTRL_PIN(129, "SDC1_CMD"), + PINCTRL_PIN(130, "SDC1_DATA"), + PINCTRL_PIN(131, "SDC2_CLK"), + PINCTRL_PIN(132, "SDC2_CMD"), + PINCTRL_PIN(133, "SDC2_DATA"), +}; + +#define DECLARE_MSM_GPIO_PINS(pin) \ + static const unsigned int gpio##pin##_pins[] = { pin } +DECLARE_MSM_GPIO_PINS(0); +DECLARE_MSM_GPIO_PINS(1); +DECLARE_MSM_GPIO_PINS(2); +DECLARE_MSM_GPIO_PINS(3); +DECLARE_MSM_GPIO_PINS(4); +DECLARE_MSM_GPIO_PINS(5); +DECLARE_MSM_GPIO_PINS(6); +DECLARE_MSM_GPIO_PINS(7); +DECLARE_MSM_GPIO_PINS(8); +DECLARE_MSM_GPIO_PINS(9); +DECLARE_MSM_GPIO_PINS(10); +DECLARE_MSM_GPIO_PINS(11); +DECLARE_MSM_GPIO_PINS(12); +DECLARE_MSM_GPIO_PINS(13); +DECLARE_MSM_GPIO_PINS(14); +DECLARE_MSM_GPIO_PINS(15); +DECLARE_MSM_GPIO_PINS(16); +DECLARE_MSM_GPIO_PINS(17); +DECLARE_MSM_GPIO_PINS(18); +DECLARE_MSM_GPIO_PINS(19); +DECLARE_MSM_GPIO_PINS(20); +DECLARE_MSM_GPIO_PINS(21); +DECLARE_MSM_GPIO_PINS(22); +DECLARE_MSM_GPIO_PINS(23); +DECLARE_MSM_GPIO_PINS(24); +DECLARE_MSM_GPIO_PINS(25); +DECLARE_MSM_GPIO_PINS(26); +DECLARE_MSM_GPIO_PINS(27); +DECLARE_MSM_GPIO_PINS(28); +DECLARE_MSM_GPIO_PINS(29); +DECLARE_MSM_GPIO_PINS(30); +DECLARE_MSM_GPIO_PINS(31); +DECLARE_MSM_GPIO_PINS(32); +DECLARE_MSM_GPIO_PINS(33); +DECLARE_MSM_GPIO_PINS(34); +DECLARE_MSM_GPIO_PINS(35); +DECLARE_MSM_GPIO_PINS(36); +DECLARE_MSM_GPIO_PINS(37); +DECLARE_MSM_GPIO_PINS(38); +DECLARE_MSM_GPIO_PINS(39); +DECLARE_MSM_GPIO_PINS(40); +DECLARE_MSM_GPIO_PINS(41); +DECLARE_MSM_GPIO_PINS(42); +DECLARE_MSM_GPIO_PINS(43); +DECLARE_MSM_GPIO_PINS(44); +DECLARE_MSM_GPIO_PINS(45); +DECLARE_MSM_GPIO_PINS(46); +DECLARE_MSM_GPIO_PINS(47); +DECLARE_MSM_GPIO_PINS(48); +DECLARE_MSM_GPIO_PINS(49); +DECLARE_MSM_GPIO_PINS(50); +DECLARE_MSM_GPIO_PINS(51); +DECLARE_MSM_GPIO_PINS(52); +DECLARE_MSM_GPIO_PINS(53); +DECLARE_MSM_GPIO_PINS(54); +DECLARE_MSM_GPIO_PINS(55); +DECLARE_MSM_GPIO_PINS(56); +DECLARE_MSM_GPIO_PINS(57); +DECLARE_MSM_GPIO_PINS(58); +DECLARE_MSM_GPIO_PINS(59); +DECLARE_MSM_GPIO_PINS(60); +DECLARE_MSM_GPIO_PINS(61); +DECLARE_MSM_GPIO_PINS(62); +DECLARE_MSM_GPIO_PINS(63); +DECLARE_MSM_GPIO_PINS(64); +DECLARE_MSM_GPIO_PINS(65); +DECLARE_MSM_GPIO_PINS(66); +DECLARE_MSM_GPIO_PINS(67); +DECLARE_MSM_GPIO_PINS(68); +DECLARE_MSM_GPIO_PINS(69); +DECLARE_MSM_GPIO_PINS(70); +DECLARE_MSM_GPIO_PINS(71); +DECLARE_MSM_GPIO_PINS(72); +DECLARE_MSM_GPIO_PINS(73); +DECLARE_MSM_GPIO_PINS(74); +DECLARE_MSM_GPIO_PINS(75); +DECLARE_MSM_GPIO_PINS(76); +DECLARE_MSM_GPIO_PINS(77); +DECLARE_MSM_GPIO_PINS(78); +DECLARE_MSM_GPIO_PINS(79); +DECLARE_MSM_GPIO_PINS(80); +DECLARE_MSM_GPIO_PINS(81); +DECLARE_MSM_GPIO_PINS(82); +DECLARE_MSM_GPIO_PINS(83); +DECLARE_MSM_GPIO_PINS(84); +DECLARE_MSM_GPIO_PINS(85); +DECLARE_MSM_GPIO_PINS(86); +DECLARE_MSM_GPIO_PINS(87); +DECLARE_MSM_GPIO_PINS(88); +DECLARE_MSM_GPIO_PINS(89); +DECLARE_MSM_GPIO_PINS(90); +DECLARE_MSM_GPIO_PINS(91); +DECLARE_MSM_GPIO_PINS(92); +DECLARE_MSM_GPIO_PINS(93); +DECLARE_MSM_GPIO_PINS(94); +DECLARE_MSM_GPIO_PINS(95); +DECLARE_MSM_GPIO_PINS(96); +DECLARE_MSM_GPIO_PINS(97); +DECLARE_MSM_GPIO_PINS(98); +DECLARE_MSM_GPIO_PINS(99); +DECLARE_MSM_GPIO_PINS(100); +DECLARE_MSM_GPIO_PINS(101); +DECLARE_MSM_GPIO_PINS(102); +DECLARE_MSM_GPIO_PINS(103); +DECLARE_MSM_GPIO_PINS(104); +DECLARE_MSM_GPIO_PINS(105); +DECLARE_MSM_GPIO_PINS(106); +DECLARE_MSM_GPIO_PINS(107); +DECLARE_MSM_GPIO_PINS(108); +DECLARE_MSM_GPIO_PINS(109); +DECLARE_MSM_GPIO_PINS(110); +DECLARE_MSM_GPIO_PINS(111); +DECLARE_MSM_GPIO_PINS(112); +DECLARE_MSM_GPIO_PINS(113); +DECLARE_MSM_GPIO_PINS(114); +DECLARE_MSM_GPIO_PINS(115); +DECLARE_MSM_GPIO_PINS(116); +DECLARE_MSM_GPIO_PINS(117); +DECLARE_MSM_GPIO_PINS(118); +DECLARE_MSM_GPIO_PINS(119); +DECLARE_MSM_GPIO_PINS(120); +DECLARE_MSM_GPIO_PINS(121); +DECLARE_MSM_GPIO_PINS(122); +DECLARE_MSM_GPIO_PINS(123); +DECLARE_MSM_GPIO_PINS(124); +DECLARE_MSM_GPIO_PINS(125); +DECLARE_MSM_GPIO_PINS(126); + +static const unsigned int sdc1_rclk_pins[] = { 127 }; +static const unsigned int sdc1_clk_pins[] = { 128 }; +static const unsigned int sdc1_cmd_pins[] = { 129 }; +static const unsigned int sdc1_data_pins[] = { 130 }; +static const unsigned int sdc2_clk_pins[] = { 131 }; +static const unsigned int sdc2_cmd_pins[] = { 132 }; +static const unsigned int sdc2_data_pins[] = { 133 }; + +enum qcm2290_functions { + msm_mux_adsp_ext, + msm_mux_agera_pll, + msm_mux_atest, + msm_mux_cam_mclk, + msm_mux_cci_async, + msm_mux_cci_i2c, + msm_mux_cci_timer0, + msm_mux_cci_timer1, + msm_mux_cci_timer2, + msm_mux_cci_timer3, + msm_mux_char_exec, + msm_mux_cri_trng, + msm_mux_cri_trng0, + msm_mux_cri_trng1, + msm_mux_dac_calib, + msm_mux_dbg_out, + msm_mux_ddr_bist, + msm_mux_ddr_pxi0, + msm_mux_ddr_pxi1, + msm_mux_ddr_pxi2, + msm_mux_ddr_pxi3, + msm_mux_gcc_gp1, + msm_mux_gcc_gp2, + msm_mux_gcc_gp3, + msm_mux_gpio, + msm_mux_gp_pdm0, + msm_mux_gp_pdm1, + msm_mux_gp_pdm2, + msm_mux_gsm0_tx, + msm_mux_gsm1_tx, + msm_mux_jitter_bist, + msm_mux_mdp_vsync, + msm_mux_mdp_vsync_out_0, + msm_mux_mdp_vsync_out_1, + msm_mux_mpm_pwr, + msm_mux_mss_lte, + msm_mux_m_voc, + msm_mux_nav_gpio, + msm_mux_pa_indicator, + msm_mux_pbs0, + msm_mux_pbs1, + msm_mux_pbs2, + msm_mux_pbs3, + msm_mux_pbs4, + msm_mux_pbs5, + msm_mux_pbs6, + msm_mux_pbs7, + msm_mux_pbs8, + msm_mux_pbs9, + msm_mux_pbs10, + msm_mux_pbs11, + msm_mux_pbs12, + msm_mux_pbs13, + msm_mux_pbs14, + msm_mux_pbs15, + msm_mux_pbs_out, + msm_mux_phase_flag, + msm_mux_pll_bist, + msm_mux_pll_bypassnl, + msm_mux_pll_reset, + msm_mux_prng_rosc, + msm_mux_pwm_0, + msm_mux_pwm_1, + msm_mux_pwm_2, + msm_mux_pwm_3, + msm_mux_pwm_4, + msm_mux_pwm_5, + msm_mux_pwm_6, + msm_mux_pwm_7, + msm_mux_pwm_8, + msm_mux_pwm_9, + msm_mux_qdss_cti, + msm_mux_qdss_gpio, + msm_mux_qup0, + msm_mux_qup1, + msm_mux_qup2, + msm_mux_qup3, + msm_mux_qup4, + msm_mux_qup5, + msm_mux_sdc1_tb, + msm_mux_sdc2_tb, + msm_mux_sd_write, + msm_mux_ssbi_wtr1, + msm_mux_tgu_ch0, + msm_mux_tgu_ch1, + msm_mux_tgu_ch2, + msm_mux_tgu_ch3, + msm_mux_tsense_pwm, + msm_mux_uim1_clk, + msm_mux_uim1_data, + msm_mux_uim1_present, + msm_mux_uim1_reset, + msm_mux_uim2_clk, + msm_mux_uim2_data, + msm_mux_uim2_present, + msm_mux_uim2_reset, + msm_mux_usb_phy, + msm_mux_vfr_1, + msm_mux_vsense_trigger, + msm_mux_wlan1_adc0, + msm_mux_wlan1_adc1, + msm_mux__, +}; + +static const char * const qup0_groups[] = { + "gpio0", "gpio1", "gpio2", "gpio3", "gpio82", "gpio86", +}; +static const char * const gpio_groups[] = { + "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7", + "gpio8", "gpio9", "gpio10", "gpio11", "gpio12", "gpio13", "gpio14", + "gpio15", "gpio16", "gpio17", "gpio18", "gpio19", "gpio20", "gpio21", + "gpio22", "gpio23", "gpio24", "gpio25", "gpio26", "gpio27", "gpio28", + "gpio29", "gpio30", "gpio31", "gpio32", "gpio33", "gpio34", "gpio35", + "gpio36", "gpio37", "gpio38", "gpio39", "gpio40", "gpio41", "gpio42", + "gpio43", "gpio44", "gpio45", "gpio46", "gpio47", "gpio48", "gpio49", + "gpio50", "gpio51", "gpio52", "gpio53", "gpio54", "gpio55", "gpio56", + "gpio57", "gpio58", "gpio59", "gpio60", "gpio61", "gpio62", "gpio63", + "gpio64", "gpio65", "gpio66", "gpio67", "gpio68", "gpio69", "gpio70", + "gpio71", "gpio72", "gpio73", "gpio74", "gpio75", "gpio76", "gpio77", + "gpio78", "gpio79", "gpio80", "gpio81", "gpio82", "gpio83", "gpio84", + "gpio85", "gpio86", "gpio87", "gpio88", "gpio89", "gpio90", "gpio91", + "gpio92", "gpio93", "gpio94", "gpio95", "gpio96", "gpio97", "gpio98", + "gpio99", "gpio100", "gpio101", "gpio102", "gpio103", "gpio104", + "gpio105", "gpio106", "gpio107", "gpio108", "gpio109", "gpio110", + "gpio111", "gpio112", "gpio113", "gpio114", "gpio115", "gpio116", + "gpio117", "gpio118", "gpio119", "gpio120", "gpio121", "gpio122", + "gpio123", "gpio124", "gpio125", "gpio126", +}; +static const char * const ddr_bist_groups[] = { + "gpio0", "gpio1", "gpio2", "gpio3", +}; +static const char * const phase_flag_groups[] = { + "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", + "gpio14", "gpio15", "gpio16", "gpio17", "gpio22", "gpio23", "gpio24", + "gpio25", "gpio26", "gpio29", "gpio30", "gpio31", "gpio32", "gpio33", + "gpio35", "gpio36", "gpio43", "gpio44", "gpio45", "gpio63", "gpio64", + "gpio102", "gpio103", "gpio104", "gpio105", +}; +static const char * const qdss_gpio_groups[] = { + "gpio0", "gpio1", "gpio2", "gpio3", "gpio8", "gpio9", "gpio10", + "gpio11", "gpio14", "gpio15", "gpio16", "gpio17", "gpio18", "gpio19", + "gpio20", "gpio21", "gpio22", "gpio23", "gpio24", "gpio25", "gpio26", + "gpio47", "gpio48", "gpio69", "gpio70", "gpio87", "gpio90", "gpio91", + "gpio94", "gpio95", "gpio104", "gpio105", "gpio106", "gpio107", + "gpio109", "gpio110", +}; +static const char * const atest_groups[] = { + "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", + "gpio22", "gpio23", "gpio24", "gpio25", "gpio26", "gpio29", "gpio30", + "gpio31", "gpio32", "gpio33", "gpio86", "gpio89", "gpio100", "gpio101", +}; +static const char * const mpm_pwr_groups[] = { + "gpio1", +}; +static const char * const m_voc_groups[] = { + "gpio0", +}; +static const char * const dac_calib_groups[] = { + "gpio2", + "gpio3", + "gpio4", + "gpio5", + "gpio6", + "gpio14", + "gpio15", + "gpio16", + "gpio17", + "gpio22", + "gpio23", + "gpio24", + "gpio25", + "gpio26", + "gpio29", + "gpio30", + "gpio31", + "gpio32", + "gpio33", + "gpio80", + "gpio81", + "gpio82", + "gpio102", + "gpio103", + "gpio104", + "gpio105", +}; +static const char * const qup1_groups[] = { + "gpio4", "gpio5", "gpio69", "gpio70", +}; +static const char * const cri_trng0_groups[] = { + "gpio4", +}; +static const char * const cri_trng1_groups[] = { + "gpio5", +}; +static const char * const qup2_groups[] = { + "gpio6", "gpio7", "gpio71", "gpio80", +}; +static const char * const qup3_groups[] = { + "gpio8", "gpio9", "gpio10", "gpio11", +}; +static const char * const pbs_out_groups[] = { + "gpio8", "gpio9", "gpio52", +}; +static const char * const pll_bist_groups[] = { + "gpio8", "gpio9", +}; +static const char * const tsense_pwm_groups[] = { + "gpio8", +}; +static const char * const agera_pll_groups[] = { + "gpio10", "gpio11", +}; +static const char * const pbs0_groups[] = { + "gpio10", +}; +static const char * const pbs1_groups[] = { + "gpio11", +}; +static const char * const qup4_groups[] = { + "gpio12", "gpio13", "gpio96", "gpio97", +}; +static const char * const tgu_ch0_groups[] = { + "gpio12", +}; +static const char * const tgu_ch1_groups[] = { + "gpio13", +}; +static const char * const qup5_groups[] = { + "gpio14", "gpio15", "gpio16", "gpio17", +}; +static const char * const tgu_ch2_groups[] = { + "gpio14", +}; +static const char * const tgu_ch3_groups[] = { + "gpio15", +}; +static const char * const sdc2_tb_groups[] = { + "gpio18", +}; +static const char * const cri_trng_groups[] = { + "gpio18", +}; +static const char * const pbs2_groups[] = { + "gpio18", +}; +static const char * const pwm_0_groups[] = { + "gpio18", +}; +static const char * const sdc1_tb_groups[] = { + "gpio19", +}; +static const char * const pbs3_groups[] = { + "gpio19", +}; +static const char * const cam_mclk_groups[] = { + "gpio20", "gpio21", "gpio27", "gpio28", +}; +static const char * const pbs4_groups[] = { + "gpio20", +}; +static const char * const adsp_ext_groups[] = { + "gpio21", +}; +static const char * const pbs5_groups[] = { + "gpio21", +}; +static const char * const cci_i2c_groups[] = { + "gpio22", "gpio23", "gpio29", "gpio30", +}; +static const char * const prng_rosc_groups[] = { + "gpio22", "gpio23", +}; +static const char * const pbs6_groups[] = { + "gpio22", +}; +static const char * const pbs7_groups[] = { + "gpio23", +}; +static const char * const cci_timer1_groups[] = { + "gpio24", +}; +static const char * const gcc_gp1_groups[] = { + "gpio24", "gpio86", +}; +static const char * const pbs8_groups[] = { + "gpio24", +}; +static const char * const cci_async_groups[] = { + "gpio25", +}; +static const char * const cci_timer0_groups[] = { + "gpio25", +}; +static const char * const pbs9_groups[] = { + "gpio25", +}; +static const char * const pbs10_groups[] = { + "gpio26", +}; +static const char * const vsense_trigger_groups[] = { + "gpio26", +}; +static const char * const qdss_cti_groups[] = { + "gpio27", "gpio28", "gpio72", "gpio73", "gpio96", "gpio97", +}; +static const char * const cci_timer2_groups[] = { + "gpio28", +}; +static const char * const pwm_1_groups[] = { + "gpio28", +}; +static const char * const gp_pdm0_groups[] = { + "gpio31", "gpio95", +}; +static const char * const cci_timer3_groups[] = { + "gpio32", +}; +static const char * const gp_pdm1_groups[] = { + "gpio32", "gpio96", +}; +static const char * const gp_pdm2_groups[] = { + "gpio33", "gpio97", +}; +static const char * const char_exec_groups[] = { + "gpio37", "gpio38", +}; +static const char * const nav_gpio_groups[] = { + "gpio42", "gpio47", "gpio52", "gpio95", "gpio96", "gpio97", "gpio106", + "gpio107", "gpio108", +}; +static const char * const pbs14_groups[] = { + "gpio47", +}; +static const char * const vfr_1_groups[] = { + "gpio48", +}; +static const char * const pbs15_groups[] = { + "gpio48", +}; +static const char * const pa_indicator_groups[] = { + "gpio49", +}; +static const char * const pwm_2_groups[] = { + "gpio51", +}; +static const char * const gsm1_tx_groups[] = { + "gpio53", +}; +static const char * const ssbi_wtr1_groups[] = { + "gpio59", "gpio60", +}; +static const char * const pll_bypassnl_groups[] = { + "gpio62", +}; +static const char * const pll_reset_groups[] = { + "gpio63", +}; +static const char * const ddr_pxi0_groups[] = { + "gpio63", "gpio64", +}; +static const char * const gsm0_tx_groups[] = { + "gpio64", +}; +static const char * const gcc_gp2_groups[] = { + "gpio69", "gpio107", +}; +static const char * const ddr_pxi1_groups[] = { + "gpio69", "gpio70", +}; +static const char * const gcc_gp3_groups[] = { + "gpio70", "gpio106", +}; +static const char * const dbg_out_groups[] = { + "gpio71", +}; +static const char * const uim2_data_groups[] = { + "gpio72", +}; +static const char * const pwm_3_groups[] = { + "gpio72", +}; +static const char * const uim2_clk_groups[] = { + "gpio73", +}; +static const char * const uim2_reset_groups[] = { + "gpio74", +}; +static const char * const pwm_4_groups[] = { + "gpio74", +}; +static const char * const uim2_present_groups[] = { + "gpio75", +}; +static const char * const pwm_5_groups[] = { + "gpio75", +}; +static const char * const uim1_data_groups[] = { + "gpio76", +}; +static const char * const uim1_clk_groups[] = { + "gpio77", +}; +static const char * const uim1_reset_groups[] = { + "gpio78", +}; +static const char * const uim1_present_groups[] = { + "gpio79", +}; +static const char * const mdp_vsync_groups[] = { + "gpio81", "gpio96", "gpio97", +}; +static const char * const mdp_vsync_out_0_groups[] = { + "gpio81", +}; +static const char * const mdp_vsync_out_1_groups[] = { + "gpio81", +}; +static const char * const pwm_6_groups[] = { + "gpio82", +}; +static const char * const pbs11_groups[] = { + "gpio87", +}; +static const char * const usb_phy_groups[] = { + "gpio89", +}; +static const char * const pwm_7_groups[] = { + "gpio89", +}; +static const char * const mss_lte_groups[] = { + "gpio90", "gpio91", +}; +static const char * const pbs12_groups[] = { + "gpio90", +}; +static const char * const pbs13_groups[] = { + "gpio91", +}; +static const char * const wlan1_adc0_groups[] = { + "gpio94", +}; +static const char * const wlan1_adc1_groups[] = { + "gpio95", +}; +static const char * const sd_write_groups[] = { + "gpio96", +}; +static const char * const jitter_bist_groups[] = { + "gpio96", "gpio97", +}; +static const char * const ddr_pxi2_groups[] = { + "gpio102", "gpio103", +}; +static const char * const ddr_pxi3_groups[] = { + "gpio104", "gpio105", +}; +static const char * const pwm_8_groups[] = { + "gpio104", +}; +static const char * const pwm_9_groups[] = { + "gpio115", +}; + +static const struct pinfunction qcm2290_functions[] = { + MSM_PIN_FUNCTION(adsp_ext), + MSM_PIN_FUNCTION(agera_pll), + MSM_PIN_FUNCTION(atest), + MSM_PIN_FUNCTION(cam_mclk), + MSM_PIN_FUNCTION(cci_async), + MSM_PIN_FUNCTION(cci_i2c), + MSM_PIN_FUNCTION(cci_timer0), + MSM_PIN_FUNCTION(cci_timer1), + MSM_PIN_FUNCTION(cci_timer2), + MSM_PIN_FUNCTION(cci_timer3), + MSM_PIN_FUNCTION(char_exec), + MSM_PIN_FUNCTION(cri_trng), + MSM_PIN_FUNCTION(cri_trng0), + MSM_PIN_FUNCTION(cri_trng1), + MSM_PIN_FUNCTION(dac_calib), + MSM_PIN_FUNCTION(dbg_out), + MSM_PIN_FUNCTION(ddr_bist), + MSM_PIN_FUNCTION(ddr_pxi0), + MSM_PIN_FUNCTION(ddr_pxi1), + MSM_PIN_FUNCTION(ddr_pxi2), + MSM_PIN_FUNCTION(ddr_pxi3), + MSM_PIN_FUNCTION(gcc_gp1), + MSM_PIN_FUNCTION(gcc_gp2), + MSM_PIN_FUNCTION(gcc_gp3), + MSM_PIN_FUNCTION(gpio), + MSM_PIN_FUNCTION(gp_pdm0), + MSM_PIN_FUNCTION(gp_pdm1), + MSM_PIN_FUNCTION(gp_pdm2), + MSM_PIN_FUNCTION(gsm0_tx), + MSM_PIN_FUNCTION(gsm1_tx), + MSM_PIN_FUNCTION(jitter_bist), + MSM_PIN_FUNCTION(mdp_vsync), + MSM_PIN_FUNCTION(mdp_vsync_out_0), + MSM_PIN_FUNCTION(mdp_vsync_out_1), + MSM_PIN_FUNCTION(mpm_pwr), + MSM_PIN_FUNCTION(mss_lte), + MSM_PIN_FUNCTION(m_voc), + MSM_PIN_FUNCTION(nav_gpio), + MSM_PIN_FUNCTION(pa_indicator), + MSM_PIN_FUNCTION(pbs0), + MSM_PIN_FUNCTION(pbs1), + MSM_PIN_FUNCTION(pbs2), + MSM_PIN_FUNCTION(pbs3), + MSM_PIN_FUNCTION(pbs4), + MSM_PIN_FUNCTION(pbs5), + MSM_PIN_FUNCTION(pbs6), + MSM_PIN_FUNCTION(pbs7), + MSM_PIN_FUNCTION(pbs8), + MSM_PIN_FUNCTION(pbs9), + MSM_PIN_FUNCTION(pbs10), + MSM_PIN_FUNCTION(pbs11), + MSM_PIN_FUNCTION(pbs12), + MSM_PIN_FUNCTION(pbs13), + MSM_PIN_FUNCTION(pbs14), + MSM_PIN_FUNCTION(pbs15), + MSM_PIN_FUNCTION(pbs_out), + MSM_PIN_FUNCTION(phase_flag), + MSM_PIN_FUNCTION(pll_bist), + MSM_PIN_FUNCTION(pll_bypassnl), + MSM_PIN_FUNCTION(pll_reset), + MSM_PIN_FUNCTION(prng_rosc), + MSM_PIN_FUNCTION(pwm_0), + MSM_PIN_FUNCTION(pwm_1), + MSM_PIN_FUNCTION(pwm_2), + MSM_PIN_FUNCTION(pwm_3), + MSM_PIN_FUNCTION(pwm_4), + MSM_PIN_FUNCTION(pwm_5), + MSM_PIN_FUNCTION(pwm_6), + MSM_PIN_FUNCTION(pwm_7), + MSM_PIN_FUNCTION(pwm_8), + MSM_PIN_FUNCTION(pwm_9), + MSM_PIN_FUNCTION(qdss_cti), + MSM_PIN_FUNCTION(qdss_gpio), + MSM_PIN_FUNCTION(qup0), + MSM_PIN_FUNCTION(qup1), + MSM_PIN_FUNCTION(qup2), + MSM_PIN_FUNCTION(qup3), + MSM_PIN_FUNCTION(qup4), + MSM_PIN_FUNCTION(qup5), + MSM_PIN_FUNCTION(sdc1_tb), + MSM_PIN_FUNCTION(sdc2_tb), + MSM_PIN_FUNCTION(sd_write), + MSM_PIN_FUNCTION(ssbi_wtr1), + MSM_PIN_FUNCTION(tgu_ch0), + MSM_PIN_FUNCTION(tgu_ch1), + MSM_PIN_FUNCTION(tgu_ch2), + MSM_PIN_FUNCTION(tgu_ch3), + MSM_PIN_FUNCTION(tsense_pwm), + MSM_PIN_FUNCTION(uim1_clk), + MSM_PIN_FUNCTION(uim1_data), + MSM_PIN_FUNCTION(uim1_present), + MSM_PIN_FUNCTION(uim1_reset), + MSM_PIN_FUNCTION(uim2_clk), + MSM_PIN_FUNCTION(uim2_data), + MSM_PIN_FUNCTION(uim2_present), + MSM_PIN_FUNCTION(uim2_reset), + MSM_PIN_FUNCTION(usb_phy), + MSM_PIN_FUNCTION(vfr_1), + MSM_PIN_FUNCTION(vsense_trigger), + MSM_PIN_FUNCTION(wlan1_adc0), + MSM_PIN_FUNCTION(wlan1_adc1), +}; + +/* Every pin is maintained as a single group, and missing or non-existing pin + * would be maintained as dummy group to synchronize pin group index with + * pin descriptor registered with pinctrl core. + * Clients would not be able to request these dummy pin groups. + */ +static const struct msm_pingroup qcm2290_groups[] = { + [0] = PINGROUP(0, qup0, m_voc, ddr_bist, _, phase_flag, qdss_gpio, atest, _, _), + [1] = PINGROUP(1, qup0, mpm_pwr, ddr_bist, _, phase_flag, qdss_gpio, atest, _, _), + [2] = PINGROUP(2, qup0, ddr_bist, _, phase_flag, qdss_gpio, dac_calib, atest, _, _), + [3] = PINGROUP(3, qup0, ddr_bist, _, phase_flag, qdss_gpio, dac_calib, atest, _, _), + [4] = PINGROUP(4, qup1, cri_trng0, _, phase_flag, dac_calib, atest, _, _, _), + [5] = PINGROUP(5, qup1, cri_trng1, _, phase_flag, dac_calib, atest, _, _, _), + [6] = PINGROUP(6, qup2, _, phase_flag, dac_calib, atest, _, _, _, _), + [7] = PINGROUP(7, qup2, _, _, _, _, _, _, _, _), + [8] = PINGROUP(8, qup3, pbs_out, pll_bist, _, qdss_gpio, _, tsense_pwm, _, _), + [9] = PINGROUP(9, qup3, pbs_out, pll_bist, _, qdss_gpio, _, _, _, _), + [10] = PINGROUP(10, qup3, agera_pll, _, pbs0, qdss_gpio, _, _, _, _), + [11] = PINGROUP(11, qup3, agera_pll, _, pbs1, qdss_gpio, _, _, _, _), + [12] = PINGROUP(12, qup4, tgu_ch0, _, _, _, _, _, _, _), + [13] = PINGROUP(13, qup4, tgu_ch1, _, _, _, _, _, _, _), + [14] = PINGROUP(14, qup5, tgu_ch2, _, phase_flag, qdss_gpio, dac_calib, _, _, _), + [15] = PINGROUP(15, qup5, tgu_ch3, _, phase_flag, qdss_gpio, dac_calib, _, _, _), + [16] = PINGROUP(16, qup5, _, phase_flag, qdss_gpio, dac_calib, _, _, _, _), + [17] = PINGROUP(17, qup5, _, phase_flag, qdss_gpio, dac_calib, _, _, _, _), + [18] = PINGROUP(18, sdc2_tb, cri_trng, pbs2, qdss_gpio, _, pwm_0, _, _, _), + [19] = PINGROUP(19, sdc1_tb, pbs3, qdss_gpio, _, _, _, _, _, _), + [20] = PINGROUP(20, cam_mclk, pbs4, qdss_gpio, _, _, _, _, _, _), + [21] = PINGROUP(21, cam_mclk, adsp_ext, pbs5, qdss_gpio, _, _, _, _, _), + [22] = PINGROUP(22, cci_i2c, prng_rosc, _, pbs6, phase_flag, qdss_gpio, dac_calib, atest, _), + [23] = PINGROUP(23, cci_i2c, prng_rosc, _, pbs7, phase_flag, qdss_gpio, dac_calib, atest, _), + [24] = PINGROUP(24, cci_timer1, gcc_gp1, _, pbs8, phase_flag, qdss_gpio, dac_calib, atest, _), + [25] = PINGROUP(25, cci_async, cci_timer0, _, pbs9, phase_flag, qdss_gpio, dac_calib, atest, _), + [26] = PINGROUP(26, _, pbs10, phase_flag, qdss_gpio, dac_calib, atest, vsense_trigger, _, _), + [27] = PINGROUP(27, cam_mclk, qdss_cti, _, _, _, _, _, _, _), + [28] = PINGROUP(28, cam_mclk, cci_timer2, qdss_cti, _, pwm_1, _, _, _, _), + [29] = PINGROUP(29, cci_i2c, _, phase_flag, dac_calib, atest, _, _, _, _), + [30] = PINGROUP(30, cci_i2c, _, phase_flag, dac_calib, atest, _, _, _, _), + [31] = PINGROUP(31, gp_pdm0, _, phase_flag, dac_calib, atest, _, _, _, _), + [32] = PINGROUP(32, cci_timer3, gp_pdm1, _, phase_flag, dac_calib, atest, _, _, _), + [33] = PINGROUP(33, gp_pdm2, _, phase_flag, dac_calib, atest, _, _, _, _), + [34] = PINGROUP(34, _, _, _, _, _, _, _, _, _), + [35] = PINGROUP(35, _, phase_flag, _, _, _, _, _, _, _), + [36] = PINGROUP(36, _, phase_flag, _, _, _, _, _, _, _), + [37] = PINGROUP(37, _, _, char_exec, _, _, _, _, _, _), + [38] = PINGROUP(38, _, _, _, char_exec, _, _, _, _, _), + [39] = PINGROUP(39, _, _, _, _, _, _, _, _, _), + [40] = PINGROUP(40, _, _, _, _, _, _, _, _, _), + [41] = PINGROUP(41, _, _, _, _, _, _, _, _, _), + [42] = PINGROUP(42, _, nav_gpio, _, _, _, _, _, _, _), + [43] = PINGROUP(43, _, _, phase_flag, _, _, _, _, _, _), + [44] = PINGROUP(44, _, _, phase_flag, _, _, _, _, _, _), + [45] = PINGROUP(45, _, _, phase_flag, _, _, _, _, _, _), + [46] = PINGROUP(46, _, _, _, _, _, _, _, _, _), + [47] = PINGROUP(47, _, nav_gpio, pbs14, qdss_gpio, _, _, _, _, _), + [48] = PINGROUP(48, _, vfr_1, _, pbs15, qdss_gpio, _, _, _, _), + [49] = PINGROUP(49, _, pa_indicator, _, _, _, _, _, _, _), + [50] = PINGROUP(50, _, _, _, _, _, _, _, _, _), + [51] = PINGROUP(51, _, _, _, pwm_2, _, _, _, _, _), + [52] = PINGROUP(52, _, nav_gpio, pbs_out, _, _, _, _, _, _), + [53] = PINGROUP(53, _, gsm1_tx, _, _, _, _, _, _, _), + [54] = PINGROUP(54, _, _, _, _, _, _, _, _, _), + [55] = PINGROUP(55, _, _, _, _, _, _, _, _, _), + [56] = PINGROUP(56, _, _, _, _, _, _, _, _, _), + [57] = PINGROUP(57, _, _, _, _, _, _, _, _, _), + [58] = PINGROUP(58, _, _, _, _, _, _, _, _, _), + [59] = PINGROUP(59, _, ssbi_wtr1, _, _, _, _, _, _, _), + [60] = PINGROUP(60, _, ssbi_wtr1, _, _, _, _, _, _, _), + [61] = PINGROUP(61, _, _, _, _, _, _, _, _, _), + [62] = PINGROUP(62, _, pll_bypassnl, _, _, _, _, _, _, _), + [63] = PINGROUP(63, pll_reset, _, phase_flag, ddr_pxi0, _, _, _, _, _), + [64] = PINGROUP(64, gsm0_tx, _, phase_flag, ddr_pxi0, _, _, _, _, _), + [65] = PINGROUP(65, _, _, _, _, _, _, _, _, _), + [66] = PINGROUP(66, _, _, _, _, _, _, _, _, _), + [67] = PINGROUP(67, _, _, _, _, _, _, _, _, _), + [68] = PINGROUP(68, _, _, _, _, _, _, _, _, _), + [69] = PINGROUP(69, qup1, gcc_gp2, qdss_gpio, ddr_pxi1, _, _, _, _, _), + [70] = PINGROUP(70, qup1, gcc_gp3, qdss_gpio, ddr_pxi1, _, _, _, _, _), + [71] = PINGROUP(71, qup2, dbg_out, _, _, _, _, _, _, _), + [72] = PINGROUP(72, uim2_data, qdss_cti, _, pwm_3, _, _, _, _, _), + [73] = PINGROUP(73, uim2_clk, _, qdss_cti, _, _, _, _, _, _), + [74] = PINGROUP(74, uim2_reset, _, _, pwm_4, _, _, _, _, _), + [75] = PINGROUP(75, uim2_present, _, _, pwm_5, _, _, _, _, _), + [76] = PINGROUP(76, uim1_data, _, _, _, _, _, _, _, _), + [77] = PINGROUP(77, uim1_clk, _, _, _, _, _, _, _, _), + [78] = PINGROUP(78, uim1_reset, _, _, _, _, _, _, _, _), + [79] = PINGROUP(79, uim1_present, _, _, _, _, _, _, _, _), + [80] = PINGROUP(80, qup2, dac_calib, _, _, _, _, _, _, _), + [81] = PINGROUP(81, mdp_vsync_out_0, mdp_vsync_out_1, mdp_vsync, dac_calib, _, _, _, _, _), + [82] = PINGROUP(82, qup0, dac_calib, _, pwm_6, _, _, _, _, _), + [83] = PINGROUP(83, _, _, _, _, _, _, _, _, _), + [84] = PINGROUP(84, _, _, _, _, _, _, _, _, _), + [85] = PINGROUP(85, _, _, _, _, _, _, _, _, _), + [86] = PINGROUP(86, qup0, gcc_gp1, atest, _, _, _, _, _, _), + [87] = PINGROUP(87, pbs11, qdss_gpio, _, _, _, _, _, _, _), + [88] = PINGROUP(88, _, _, _, _, _, _, _, _, _), + [89] = PINGROUP(89, usb_phy, atest, _, pwm_7, _, _, _, _, _), + [90] = PINGROUP(90, mss_lte, pbs12, qdss_gpio, _, _, _, _, _, _), + [91] = PINGROUP(91, mss_lte, pbs13, qdss_gpio, _, _, _, _, _, _), + [92] = PINGROUP(92, _, _, _, _, _, _, _, _, _), + [93] = PINGROUP(93, _, _, _, _, _, _, _, _, _), + [94] = PINGROUP(94, _, qdss_gpio, wlan1_adc0, _, _, _, _, _, _), + [95] = PINGROUP(95, nav_gpio, gp_pdm0, qdss_gpio, wlan1_adc1, _, _, _, _, _), + [96] = PINGROUP(96, qup4, nav_gpio, mdp_vsync, gp_pdm1, sd_write, jitter_bist, qdss_cti, qdss_cti, _), + [97] = PINGROUP(97, qup4, nav_gpio, mdp_vsync, gp_pdm2, jitter_bist, qdss_cti, qdss_cti, _, _), + [98] = PINGROUP(98, _, _, _, _, _, _, _, _, _), + [99] = PINGROUP(99, _, _, _, _, _, _, _, _, _), + [100] = PINGROUP(100, atest, _, _, _, _, _, _, _, _), + [101] = PINGROUP(101, atest, _, _, _, _, _, _, _, _), + [102] = PINGROUP(102, _, phase_flag, dac_calib, ddr_pxi2, _, _, _, _, _), + [103] = PINGROUP(103, _, phase_flag, dac_calib, ddr_pxi2, _, _, _, _, _), + [104] = PINGROUP(104, _, phase_flag, qdss_gpio, dac_calib, ddr_pxi3, _, pwm_8, _, _), + [105] = PINGROUP(105, _, phase_flag, qdss_gpio, dac_calib, ddr_pxi3, _, _, _, _), + [106] = PINGROUP(106, nav_gpio, gcc_gp3, qdss_gpio, _, _, _, _, _, _), + [107] = PINGROUP(107, nav_gpio, gcc_gp2, qdss_gpio, _, _, _, _, _, _), + [108] = PINGROUP(108, nav_gpio, _, _, _, _, _, _, _, _), + [109] = PINGROUP(109, _, qdss_gpio, _, _, _, _, _, _, _), + [110] = PINGROUP(110, _, qdss_gpio, _, _, _, _, _, _, _), + [111] = PINGROUP(111, _, _, _, _, _, _, _, _, _), + [112] = PINGROUP(112, _, _, _, _, _, _, _, _, _), + [113] = PINGROUP(113, _, _, _, _, _, _, _, _, _), + [114] = PINGROUP(114, _, _, _, _, _, _, _, _, _), + [115] = PINGROUP(115, _, pwm_9, _, _, _, _, _, _, _), + [116] = PINGROUP(116, _, _, _, _, _, _, _, _, _), + [117] = PINGROUP(117, _, _, _, _, _, _, _, _, _), + [118] = PINGROUP(118, _, _, _, _, _, _, _, _, _), + [119] = PINGROUP(119, _, _, _, _, _, _, _, _, _), + [120] = PINGROUP(120, _, _, _, _, _, _, _, _, _), + [121] = PINGROUP(121, _, _, _, _, _, _, _, _, _), + [122] = PINGROUP(122, _, _, _, _, _, _, _, _, _), + [123] = PINGROUP(123, _, _, _, _, _, _, _, _, _), + [124] = PINGROUP(124, _, _, _, _, _, _, _, _, _), + [125] = PINGROUP(125, _, _, _, _, _, _, _, _, _), + [126] = PINGROUP(126, _, _, _, _, _, _, _, _, _), + [127] = SDC_QDSD_PINGROUP(sdc1_rclk, 0x84004, 0, 0), + [128] = SDC_QDSD_PINGROUP(sdc1_clk, 0x84000, 13, 6), + [129] = SDC_QDSD_PINGROUP(sdc1_cmd, 0x84000, 11, 3), + [130] = SDC_QDSD_PINGROUP(sdc1_data, 0x84000, 9, 0), + [131] = SDC_QDSD_PINGROUP(sdc2_clk, 0x86000, 14, 6), + [132] = SDC_QDSD_PINGROUP(sdc2_cmd, 0x86000, 11, 3), + [133] = SDC_QDSD_PINGROUP(sdc2_data, 0x86000, 9, 0), +}; + +static const struct msm_gpio_wakeirq_map qcm2290_mpm_map[] = { + { 0, 84 }, { 3, 75 }, { 4, 16 }, { 6, 59 }, { 8, 63 }, { 11, 17 }, + { 13, 18 }, { 14, 51 }, { 17, 20 }, { 18, 52 }, { 19, 53 }, { 24, 6 }, + { 25, 71 }, { 27, 73 }, { 28, 41 }, { 31, 27 }, { 32, 54 }, { 33, 55 }, + { 34, 56 }, { 35, 57 }, { 36, 58 }, { 39, 28 }, { 46, 29 }, { 62, 60 }, + { 63, 61 }, { 64, 62 }, { 69, 33 }, { 70, 34 }, { 72, 72 }, { 75, 35 }, + { 79, 36 }, { 80, 21 }, { 81, 38 }, { 86, 19 }, { 87, 42 }, { 88, 43 }, + { 89, 45 }, { 91, 74 }, { 94, 47 }, { 95, 48 }, { 96, 49 }, { 97, 50 }, +}; + +static const struct msm_pinctrl_soc_data qcm2290_pinctrl = { + .pins = qcm2290_pins, + .npins = ARRAY_SIZE(qcm2290_pins), + .functions = qcm2290_functions, + .nfunctions = ARRAY_SIZE(qcm2290_functions), + .groups = qcm2290_groups, + .ngroups = ARRAY_SIZE(qcm2290_groups), + .ngpios = 127, + .wakeirq_map = qcm2290_mpm_map, + .nwakeirq_map = ARRAY_SIZE(qcm2290_mpm_map), +}; + +static int qcm2290_pinctrl_probe(struct platform_device *pdev) +{ + return msm_pinctrl_probe(pdev, &qcm2290_pinctrl); +} + +static const struct of_device_id qcm2290_pinctrl_of_match[] = { + { .compatible = "qcom,qcm2290-tlmm", }, + { }, +}; + +static struct platform_driver qcm2290_pinctrl_driver = { + .driver = { + .name = "qcm2290-pinctrl", + .of_match_table = qcm2290_pinctrl_of_match, + }, + .probe = qcm2290_pinctrl_probe, + .remove = msm_pinctrl_remove, +}; + +static int __init qcm2290_pinctrl_init(void) +{ + return platform_driver_register(&qcm2290_pinctrl_driver); +} +arch_initcall(qcm2290_pinctrl_init); + +static void __exit qcm2290_pinctrl_exit(void) +{ + platform_driver_unregister(&qcm2290_pinctrl_driver); +} +module_exit(qcm2290_pinctrl_exit); + +MODULE_DESCRIPTION("QTI QCM2290 pinctrl driver"); +MODULE_LICENSE("GPL v2"); +MODULE_DEVICE_TABLE(of, qcm2290_pinctrl_of_match); diff --git a/drivers/pinctrl/qcom/pinctrl-qcs404.c b/drivers/pinctrl/qcom/pinctrl-qcs404.c new file mode 100644 index 0000000000..ae7224012f --- /dev/null +++ b/drivers/pinctrl/qcom/pinctrl-qcs404.c @@ -0,0 +1,1664 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2018, The Linux Foundation. All rights reserved. + */ + +#include <linux/module.h> +#include <linux/of.h> +#include <linux/platform_device.h> + +#include "pinctrl-msm.h" + +static const char * const qcs404_tiles[] = { + "north", + "south", + "east" +}; + +enum { + NORTH, + SOUTH, + EAST +}; + +#define PINGROUP(id, _tile, f1, f2, f3, f4, f5, f6, f7, f8, f9) \ + { \ + .grp = PINCTRL_PINGROUP("gpio" #id, \ + gpio##id##_pins, \ + ARRAY_SIZE(gpio##id##_pins)), \ + .funcs = (int[]){ \ + msm_mux_gpio, /* gpio mode */ \ + msm_mux_##f1, \ + msm_mux_##f2, \ + msm_mux_##f3, \ + msm_mux_##f4, \ + msm_mux_##f5, \ + msm_mux_##f6, \ + msm_mux_##f7, \ + msm_mux_##f8, \ + msm_mux_##f9 \ + }, \ + .nfuncs = 10, \ + .ctl_reg = 0x1000 * id, \ + .io_reg = 0x1000 * id + 0x4, \ + .intr_cfg_reg = 0x1000 * id + 0x8, \ + .intr_status_reg = 0x1000 * id + 0xc, \ + .intr_target_reg = 0x1000 * id + 0x8, \ + .tile = _tile, \ + .mux_bit = 2, \ + .pull_bit = 0, \ + .drv_bit = 6, \ + .oe_bit = 9, \ + .in_bit = 0, \ + .out_bit = 1, \ + .intr_enable_bit = 0, \ + .intr_status_bit = 0, \ + .intr_target_bit = 5, \ + .intr_target_kpss_val = 4, \ + .intr_raw_status_bit = 4, \ + .intr_polarity_bit = 1, \ + .intr_detection_bit = 2, \ + .intr_detection_width = 2, \ + } + +#define SDC_QDSD_PINGROUP(pg_name, ctl, pull, drv) \ + { \ + .grp = PINCTRL_PINGROUP(#pg_name, \ + pg_name##_pins, \ + ARRAY_SIZE(pg_name##_pins)), \ + .ctl_reg = ctl, \ + .io_reg = 0, \ + .intr_cfg_reg = 0, \ + .intr_status_reg = 0, \ + .intr_target_reg = 0, \ + .tile = SOUTH, \ + .mux_bit = -1, \ + .pull_bit = pull, \ + .drv_bit = drv, \ + .oe_bit = -1, \ + .in_bit = -1, \ + .out_bit = -1, \ + .intr_enable_bit = -1, \ + .intr_status_bit = -1, \ + .intr_target_bit = -1, \ + .intr_raw_status_bit = -1, \ + .intr_polarity_bit = -1, \ + .intr_detection_bit = -1, \ + .intr_detection_width = -1, \ + } + +static const struct pinctrl_pin_desc qcs404_pins[] = { + PINCTRL_PIN(0, "GPIO_0"), + PINCTRL_PIN(1, "GPIO_1"), + PINCTRL_PIN(2, "GPIO_2"), + PINCTRL_PIN(3, "GPIO_3"), + PINCTRL_PIN(4, "GPIO_4"), + PINCTRL_PIN(5, "GPIO_5"), + PINCTRL_PIN(6, "GPIO_6"), + PINCTRL_PIN(7, "GPIO_7"), + PINCTRL_PIN(8, "GPIO_8"), + PINCTRL_PIN(9, "GPIO_9"), + PINCTRL_PIN(10, "GPIO_10"), + PINCTRL_PIN(11, "GPIO_11"), + PINCTRL_PIN(12, "GPIO_12"), + PINCTRL_PIN(13, "GPIO_13"), + PINCTRL_PIN(14, "GPIO_14"), + PINCTRL_PIN(15, "GPIO_15"), + PINCTRL_PIN(16, "GPIO_16"), + PINCTRL_PIN(17, "GPIO_17"), + PINCTRL_PIN(18, "GPIO_18"), + PINCTRL_PIN(19, "GPIO_19"), + PINCTRL_PIN(20, "GPIO_20"), + PINCTRL_PIN(21, "GPIO_21"), + PINCTRL_PIN(22, "GPIO_22"), + PINCTRL_PIN(23, "GPIO_23"), + PINCTRL_PIN(24, "GPIO_24"), + PINCTRL_PIN(25, "GPIO_25"), + PINCTRL_PIN(26, "GPIO_26"), + PINCTRL_PIN(27, "GPIO_27"), + PINCTRL_PIN(28, "GPIO_28"), + PINCTRL_PIN(29, "GPIO_29"), + PINCTRL_PIN(30, "GPIO_30"), + PINCTRL_PIN(31, "GPIO_31"), + PINCTRL_PIN(32, "GPIO_32"), + PINCTRL_PIN(33, "GPIO_33"), + PINCTRL_PIN(34, "GPIO_34"), + PINCTRL_PIN(35, "GPIO_35"), + PINCTRL_PIN(36, "GPIO_36"), + PINCTRL_PIN(37, "GPIO_37"), + PINCTRL_PIN(38, "GPIO_38"), + PINCTRL_PIN(39, "GPIO_39"), + PINCTRL_PIN(40, "GPIO_40"), + PINCTRL_PIN(41, "GPIO_41"), + PINCTRL_PIN(42, "GPIO_42"), + PINCTRL_PIN(43, "GPIO_43"), + PINCTRL_PIN(44, "GPIO_44"), + PINCTRL_PIN(45, "GPIO_45"), + PINCTRL_PIN(46, "GPIO_46"), + PINCTRL_PIN(47, "GPIO_47"), + PINCTRL_PIN(48, "GPIO_48"), + PINCTRL_PIN(49, "GPIO_49"), + PINCTRL_PIN(50, "GPIO_50"), + PINCTRL_PIN(51, "GPIO_51"), + PINCTRL_PIN(52, "GPIO_52"), + PINCTRL_PIN(53, "GPIO_53"), + PINCTRL_PIN(54, "GPIO_54"), + PINCTRL_PIN(55, "GPIO_55"), + PINCTRL_PIN(56, "GPIO_56"), + PINCTRL_PIN(57, "GPIO_57"), + PINCTRL_PIN(58, "GPIO_58"), + PINCTRL_PIN(59, "GPIO_59"), + PINCTRL_PIN(60, "GPIO_60"), + PINCTRL_PIN(61, "GPIO_61"), + PINCTRL_PIN(62, "GPIO_62"), + PINCTRL_PIN(63, "GPIO_63"), + PINCTRL_PIN(64, "GPIO_64"), + PINCTRL_PIN(65, "GPIO_65"), + PINCTRL_PIN(66, "GPIO_66"), + PINCTRL_PIN(67, "GPIO_67"), + PINCTRL_PIN(68, "GPIO_68"), + PINCTRL_PIN(69, "GPIO_69"), + PINCTRL_PIN(70, "GPIO_70"), + PINCTRL_PIN(71, "GPIO_71"), + PINCTRL_PIN(72, "GPIO_72"), + PINCTRL_PIN(73, "GPIO_73"), + PINCTRL_PIN(74, "GPIO_74"), + PINCTRL_PIN(75, "GPIO_75"), + PINCTRL_PIN(76, "GPIO_76"), + PINCTRL_PIN(77, "GPIO_77"), + PINCTRL_PIN(78, "GPIO_78"), + PINCTRL_PIN(79, "GPIO_79"), + PINCTRL_PIN(80, "GPIO_80"), + PINCTRL_PIN(81, "GPIO_81"), + PINCTRL_PIN(82, "GPIO_82"), + PINCTRL_PIN(83, "GPIO_83"), + PINCTRL_PIN(84, "GPIO_84"), + PINCTRL_PIN(85, "GPIO_85"), + PINCTRL_PIN(86, "GPIO_86"), + PINCTRL_PIN(87, "GPIO_87"), + PINCTRL_PIN(88, "GPIO_88"), + PINCTRL_PIN(89, "GPIO_89"), + PINCTRL_PIN(90, "GPIO_90"), + PINCTRL_PIN(91, "GPIO_91"), + PINCTRL_PIN(92, "GPIO_92"), + PINCTRL_PIN(93, "GPIO_93"), + PINCTRL_PIN(94, "GPIO_94"), + PINCTRL_PIN(95, "GPIO_95"), + PINCTRL_PIN(96, "GPIO_96"), + PINCTRL_PIN(97, "GPIO_97"), + PINCTRL_PIN(98, "GPIO_98"), + PINCTRL_PIN(99, "GPIO_99"), + PINCTRL_PIN(100, "GPIO_100"), + PINCTRL_PIN(101, "GPIO_101"), + PINCTRL_PIN(102, "GPIO_102"), + PINCTRL_PIN(103, "GPIO_103"), + PINCTRL_PIN(104, "GPIO_104"), + PINCTRL_PIN(105, "GPIO_105"), + PINCTRL_PIN(106, "GPIO_106"), + PINCTRL_PIN(107, "GPIO_107"), + PINCTRL_PIN(108, "GPIO_108"), + PINCTRL_PIN(109, "GPIO_109"), + PINCTRL_PIN(110, "GPIO_110"), + PINCTRL_PIN(111, "GPIO_111"), + PINCTRL_PIN(112, "GPIO_112"), + PINCTRL_PIN(113, "GPIO_113"), + PINCTRL_PIN(114, "GPIO_114"), + PINCTRL_PIN(115, "GPIO_115"), + PINCTRL_PIN(116, "GPIO_116"), + PINCTRL_PIN(117, "GPIO_117"), + PINCTRL_PIN(118, "GPIO_118"), + PINCTRL_PIN(119, "GPIO_119"), + PINCTRL_PIN(120, "SDC1_RCLK"), + PINCTRL_PIN(121, "SDC1_CLK"), + PINCTRL_PIN(122, "SDC1_CMD"), + PINCTRL_PIN(123, "SDC1_DATA"), + PINCTRL_PIN(124, "SDC2_CLK"), + PINCTRL_PIN(125, "SDC2_CMD"), + PINCTRL_PIN(126, "SDC2_DATA"), +}; + +#define DECLARE_MSM_GPIO_PINS(pin) \ + static const unsigned int gpio##pin##_pins[] = { pin } +DECLARE_MSM_GPIO_PINS(0); +DECLARE_MSM_GPIO_PINS(1); +DECLARE_MSM_GPIO_PINS(2); +DECLARE_MSM_GPIO_PINS(3); +DECLARE_MSM_GPIO_PINS(4); +DECLARE_MSM_GPIO_PINS(5); +DECLARE_MSM_GPIO_PINS(6); +DECLARE_MSM_GPIO_PINS(7); +DECLARE_MSM_GPIO_PINS(8); +DECLARE_MSM_GPIO_PINS(9); +DECLARE_MSM_GPIO_PINS(10); +DECLARE_MSM_GPIO_PINS(11); +DECLARE_MSM_GPIO_PINS(12); +DECLARE_MSM_GPIO_PINS(13); +DECLARE_MSM_GPIO_PINS(14); +DECLARE_MSM_GPIO_PINS(15); +DECLARE_MSM_GPIO_PINS(16); +DECLARE_MSM_GPIO_PINS(17); +DECLARE_MSM_GPIO_PINS(18); +DECLARE_MSM_GPIO_PINS(19); +DECLARE_MSM_GPIO_PINS(20); +DECLARE_MSM_GPIO_PINS(21); +DECLARE_MSM_GPIO_PINS(22); +DECLARE_MSM_GPIO_PINS(23); +DECLARE_MSM_GPIO_PINS(24); +DECLARE_MSM_GPIO_PINS(25); +DECLARE_MSM_GPIO_PINS(26); +DECLARE_MSM_GPIO_PINS(27); +DECLARE_MSM_GPIO_PINS(28); +DECLARE_MSM_GPIO_PINS(29); +DECLARE_MSM_GPIO_PINS(30); +DECLARE_MSM_GPIO_PINS(31); +DECLARE_MSM_GPIO_PINS(32); +DECLARE_MSM_GPIO_PINS(33); +DECLARE_MSM_GPIO_PINS(34); +DECLARE_MSM_GPIO_PINS(35); +DECLARE_MSM_GPIO_PINS(36); +DECLARE_MSM_GPIO_PINS(37); +DECLARE_MSM_GPIO_PINS(38); +DECLARE_MSM_GPIO_PINS(39); +DECLARE_MSM_GPIO_PINS(40); +DECLARE_MSM_GPIO_PINS(41); +DECLARE_MSM_GPIO_PINS(42); +DECLARE_MSM_GPIO_PINS(43); +DECLARE_MSM_GPIO_PINS(44); +DECLARE_MSM_GPIO_PINS(45); +DECLARE_MSM_GPIO_PINS(46); +DECLARE_MSM_GPIO_PINS(47); +DECLARE_MSM_GPIO_PINS(48); +DECLARE_MSM_GPIO_PINS(49); +DECLARE_MSM_GPIO_PINS(50); +DECLARE_MSM_GPIO_PINS(51); +DECLARE_MSM_GPIO_PINS(52); +DECLARE_MSM_GPIO_PINS(53); +DECLARE_MSM_GPIO_PINS(54); +DECLARE_MSM_GPIO_PINS(55); +DECLARE_MSM_GPIO_PINS(56); +DECLARE_MSM_GPIO_PINS(57); +DECLARE_MSM_GPIO_PINS(58); +DECLARE_MSM_GPIO_PINS(59); +DECLARE_MSM_GPIO_PINS(60); +DECLARE_MSM_GPIO_PINS(61); +DECLARE_MSM_GPIO_PINS(62); +DECLARE_MSM_GPIO_PINS(63); +DECLARE_MSM_GPIO_PINS(64); +DECLARE_MSM_GPIO_PINS(65); +DECLARE_MSM_GPIO_PINS(66); +DECLARE_MSM_GPIO_PINS(67); +DECLARE_MSM_GPIO_PINS(68); +DECLARE_MSM_GPIO_PINS(69); +DECLARE_MSM_GPIO_PINS(70); +DECLARE_MSM_GPIO_PINS(71); +DECLARE_MSM_GPIO_PINS(72); +DECLARE_MSM_GPIO_PINS(73); +DECLARE_MSM_GPIO_PINS(74); +DECLARE_MSM_GPIO_PINS(75); +DECLARE_MSM_GPIO_PINS(76); +DECLARE_MSM_GPIO_PINS(77); +DECLARE_MSM_GPIO_PINS(78); +DECLARE_MSM_GPIO_PINS(79); +DECLARE_MSM_GPIO_PINS(80); +DECLARE_MSM_GPIO_PINS(81); +DECLARE_MSM_GPIO_PINS(82); +DECLARE_MSM_GPIO_PINS(83); +DECLARE_MSM_GPIO_PINS(84); +DECLARE_MSM_GPIO_PINS(85); +DECLARE_MSM_GPIO_PINS(86); +DECLARE_MSM_GPIO_PINS(87); +DECLARE_MSM_GPIO_PINS(88); +DECLARE_MSM_GPIO_PINS(89); +DECLARE_MSM_GPIO_PINS(90); +DECLARE_MSM_GPIO_PINS(91); +DECLARE_MSM_GPIO_PINS(92); +DECLARE_MSM_GPIO_PINS(93); +DECLARE_MSM_GPIO_PINS(94); +DECLARE_MSM_GPIO_PINS(95); +DECLARE_MSM_GPIO_PINS(96); +DECLARE_MSM_GPIO_PINS(97); +DECLARE_MSM_GPIO_PINS(98); +DECLARE_MSM_GPIO_PINS(99); +DECLARE_MSM_GPIO_PINS(100); +DECLARE_MSM_GPIO_PINS(101); +DECLARE_MSM_GPIO_PINS(102); +DECLARE_MSM_GPIO_PINS(103); +DECLARE_MSM_GPIO_PINS(104); +DECLARE_MSM_GPIO_PINS(105); +DECLARE_MSM_GPIO_PINS(106); +DECLARE_MSM_GPIO_PINS(107); +DECLARE_MSM_GPIO_PINS(108); +DECLARE_MSM_GPIO_PINS(109); +DECLARE_MSM_GPIO_PINS(110); +DECLARE_MSM_GPIO_PINS(111); +DECLARE_MSM_GPIO_PINS(112); +DECLARE_MSM_GPIO_PINS(113); +DECLARE_MSM_GPIO_PINS(114); +DECLARE_MSM_GPIO_PINS(115); +DECLARE_MSM_GPIO_PINS(116); +DECLARE_MSM_GPIO_PINS(117); +DECLARE_MSM_GPIO_PINS(118); +DECLARE_MSM_GPIO_PINS(119); + +static const unsigned int sdc1_rclk_pins[] = { 120 }; +static const unsigned int sdc1_clk_pins[] = { 121 }; +static const unsigned int sdc1_cmd_pins[] = { 122 }; +static const unsigned int sdc1_data_pins[] = { 123 }; +static const unsigned int sdc2_clk_pins[] = { 124 }; +static const unsigned int sdc2_cmd_pins[] = { 125 }; +static const unsigned int sdc2_data_pins[] = { 126 }; + +enum qcs404_functions { + msm_mux_gpio, + msm_mux_hdmi_tx, + msm_mux_hdmi_ddc, + msm_mux_blsp_uart_tx_a2, + msm_mux_blsp_spi2, + msm_mux_m_voc, + msm_mux_qdss_cti_trig_in_a0, + msm_mux_blsp_uart_rx_a2, + msm_mux_qdss_tracectl_a, + msm_mux_blsp_uart2, + msm_mux_aud_cdc, + msm_mux_blsp_i2c_sda_a2, + msm_mux_qdss_tracedata_a, + msm_mux_blsp_i2c_scl_a2, + msm_mux_qdss_tracectl_b, + msm_mux_qdss_cti_trig_in_b0, + msm_mux_blsp_uart1, + msm_mux_blsp_spi_mosi_a1, + msm_mux_blsp_spi_miso_a1, + msm_mux_qdss_tracedata_b, + msm_mux_blsp_i2c1, + msm_mux_blsp_spi_cs_n_a1, + msm_mux_gcc_plltest, + msm_mux_blsp_spi_clk_a1, + msm_mux_rgb_data0, + msm_mux_blsp_uart5, + msm_mux_blsp_spi5, + msm_mux_adsp_ext, + msm_mux_rgb_data1, + msm_mux_prng_rosc, + msm_mux_rgb_data2, + msm_mux_blsp_i2c5, + msm_mux_gcc_gp1_clk_b, + msm_mux_rgb_data3, + msm_mux_gcc_gp2_clk_b, + msm_mux_blsp_spi0, + msm_mux_blsp_uart0, + msm_mux_gcc_gp3_clk_b, + msm_mux_blsp_i2c0, + msm_mux_qdss_traceclk_b, + msm_mux_pcie_clk, + msm_mux_nfc_irq, + msm_mux_blsp_spi4, + msm_mux_nfc_dwl, + msm_mux_audio_ts, + msm_mux_rgb_data4, + msm_mux_spi_lcd, + msm_mux_blsp_uart_tx_b2, + msm_mux_gcc_gp3_clk_a, + msm_mux_rgb_data5, + msm_mux_blsp_uart_rx_b2, + msm_mux_blsp_i2c_sda_b2, + msm_mux_blsp_i2c_scl_b2, + msm_mux_pwm_led11, + msm_mux_i2s_3_data0_a, + msm_mux_ebi2_lcd, + msm_mux_i2s_3_data1_a, + msm_mux_i2s_3_data2_a, + msm_mux_atest_char, + msm_mux_pwm_led3, + msm_mux_i2s_3_data3_a, + msm_mux_pwm_led4, + msm_mux_i2s_4, + msm_mux_ebi2_a, + msm_mux_dsd_clk_b, + msm_mux_pwm_led5, + msm_mux_pwm_led6, + msm_mux_pwm_led7, + msm_mux_pwm_led8, + msm_mux_pwm_led24, + msm_mux_spkr_dac0, + msm_mux_blsp_i2c4, + msm_mux_pwm_led9, + msm_mux_pwm_led10, + msm_mux_spdifrx_opt, + msm_mux_pwm_led12, + msm_mux_pwm_led13, + msm_mux_pwm_led14, + msm_mux_wlan1_adc1, + msm_mux_rgb_data_b0, + msm_mux_pwm_led15, + msm_mux_blsp_spi_mosi_b1, + msm_mux_wlan1_adc0, + msm_mux_rgb_data_b1, + msm_mux_pwm_led16, + msm_mux_blsp_spi_miso_b1, + msm_mux_qdss_cti_trig_out_b0, + msm_mux_wlan2_adc1, + msm_mux_rgb_data_b2, + msm_mux_pwm_led17, + msm_mux_blsp_spi_cs_n_b1, + msm_mux_wlan2_adc0, + msm_mux_rgb_data_b3, + msm_mux_pwm_led18, + msm_mux_blsp_spi_clk_b1, + msm_mux_rgb_data_b4, + msm_mux_pwm_led19, + msm_mux_ext_mclk1_b, + msm_mux_qdss_traceclk_a, + msm_mux_rgb_data_b5, + msm_mux_pwm_led20, + msm_mux_atest_char3, + msm_mux_i2s_3_sck_b, + msm_mux_ldo_update, + msm_mux_bimc_dte0, + msm_mux_rgb_hsync, + msm_mux_pwm_led21, + msm_mux_i2s_3_ws_b, + msm_mux_dbg_out, + msm_mux_rgb_vsync, + msm_mux_i2s_3_data0_b, + msm_mux_ldo_en, + msm_mux_hdmi_dtest, + msm_mux_rgb_de, + msm_mux_i2s_3_data1_b, + msm_mux_hdmi_lbk9, + msm_mux_rgb_clk, + msm_mux_atest_char1, + msm_mux_i2s_3_data2_b, + msm_mux_ebi_cdc, + msm_mux_hdmi_lbk8, + msm_mux_rgb_mdp, + msm_mux_atest_char0, + msm_mux_i2s_3_data3_b, + msm_mux_hdmi_lbk7, + msm_mux_rgb_data_b6, + msm_mux_rgb_data_b7, + msm_mux_hdmi_lbk6, + msm_mux_rgmii_int, + msm_mux_cri_trng1, + msm_mux_rgmii_wol, + msm_mux_cri_trng0, + msm_mux_gcc_tlmm, + msm_mux_rgmii_ck, + msm_mux_rgmii_tx, + msm_mux_hdmi_lbk5, + msm_mux_hdmi_pixel, + msm_mux_hdmi_rcv, + msm_mux_hdmi_lbk4, + msm_mux_rgmii_ctl, + msm_mux_ext_lpass, + msm_mux_rgmii_rx, + msm_mux_cri_trng, + msm_mux_hdmi_lbk3, + msm_mux_hdmi_lbk2, + msm_mux_qdss_cti_trig_out_b1, + msm_mux_rgmii_mdio, + msm_mux_hdmi_lbk1, + msm_mux_rgmii_mdc, + msm_mux_hdmi_lbk0, + msm_mux_ir_in, + msm_mux_wsa_en, + msm_mux_rgb_data6, + msm_mux_rgb_data7, + msm_mux_atest_char2, + msm_mux_ebi_ch0, + msm_mux_blsp_uart3, + msm_mux_blsp_spi3, + msm_mux_sd_write, + msm_mux_blsp_i2c3, + msm_mux_gcc_gp1_clk_a, + msm_mux_qdss_cti_trig_in_b1, + msm_mux_gcc_gp2_clk_a, + msm_mux_ext_mclk0, + msm_mux_mclk_in1, + msm_mux_i2s_1, + msm_mux_dsd_clk_a, + msm_mux_qdss_cti_trig_in_a1, + msm_mux_rgmi_dll1, + msm_mux_pwm_led22, + msm_mux_pwm_led23, + msm_mux_qdss_cti_trig_out_a0, + msm_mux_rgmi_dll2, + msm_mux_pwm_led1, + msm_mux_qdss_cti_trig_out_a1, + msm_mux_pwm_led2, + msm_mux_i2s_2, + msm_mux_pll_bist, + msm_mux_ext_mclk1_a, + msm_mux_mclk_in2, + msm_mux_bimc_dte1, + msm_mux_i2s_3_sck_a, + msm_mux_i2s_3_ws_a, + msm_mux__, +}; + +static const char * const gpio_groups[] = { + "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7", + "gpio8", "gpio9", "gpio10", "gpio11", "gpio12", "gpio13", "gpio14", + "gpio15", "gpio16", "gpio17", "gpio18", "gpio19", "gpio20", "gpio21", + "gpio21", "gpio21", "gpio22", "gpio22", "gpio23", "gpio23", "gpio24", + "gpio25", "gpio26", "gpio27", "gpio28", "gpio29", "gpio30", "gpio31", + "gpio32", "gpio33", "gpio34", "gpio35", "gpio36", "gpio36", "gpio36", + "gpio36", "gpio37", "gpio37", "gpio37", "gpio38", "gpio38", "gpio38", + "gpio39", "gpio39", "gpio40", "gpio40", "gpio41", "gpio41", "gpio41", + "gpio42", "gpio43", "gpio44", "gpio45", "gpio46", "gpio47", "gpio48", + "gpio49", "gpio50", "gpio51", "gpio52", "gpio53", "gpio54", "gpio55", + "gpio56", "gpio57", "gpio58", "gpio59", "gpio59", "gpio60", "gpio61", + "gpio62", "gpio63", "gpio64", "gpio65", "gpio66", "gpio67", "gpio68", + "gpio69", "gpio70", "gpio71", "gpio72", "gpio73", "gpio74", "gpio75", + "gpio76", "gpio77", "gpio77", "gpio78", "gpio78", "gpio78", "gpio79", + "gpio79", "gpio79", "gpio80", "gpio81", "gpio81", "gpio82", "gpio83", + "gpio84", "gpio85", "gpio86", "gpio87", "gpio88", "gpio89", "gpio90", + "gpio91", "gpio92", "gpio93", "gpio94", "gpio95", "gpio96", "gpio97", + "gpio98", "gpio99", "gpio100", "gpio101", "gpio102", "gpio103", + "gpio104", "gpio105", "gpio106", "gpio107", "gpio108", "gpio108", + "gpio108", "gpio109", "gpio109", "gpio110", "gpio111", "gpio112", + "gpio113", "gpio114", "gpio115", "gpio116", "gpio117", "gpio118", + "gpio119", +}; + +static const char * const hdmi_tx_groups[] = { + "gpio14", +}; + +static const char * const hdmi_ddc_groups[] = { + "gpio15", "gpio16", +}; + +static const char * const blsp_uart_tx_a2_groups[] = { + "gpio17", +}; + +static const char * const blsp_spi2_groups[] = { + "gpio17", "gpio18", "gpio19", "gpio20", +}; + +static const char * const m_voc_groups[] = { + "gpio17", "gpio21", +}; + +static const char * const qdss_cti_trig_in_a0_groups[] = { + "gpio17", +}; + +static const char * const blsp_uart_rx_a2_groups[] = { + "gpio18", +}; + +static const char * const qdss_tracectl_a_groups[] = { + "gpio18", +}; + +static const char * const blsp_uart2_groups[] = { + "gpio19", "gpio20", +}; + +static const char * const aud_cdc_groups[] = { + "gpio19", "gpio20", +}; + +static const char * const blsp_i2c_sda_a2_groups[] = { + "gpio19", +}; + +static const char * const qdss_tracedata_a_groups[] = { + "gpio19", "gpio24", "gpio25", "gpio26", "gpio27", "gpio28", "gpio30", + "gpio31", "gpio32", "gpio36", "gpio38", "gpio39", "gpio42", "gpio43", + "gpio82", "gpio83", +}; + +static const char * const blsp_i2c_scl_a2_groups[] = { + "gpio20", +}; + +static const char * const qdss_tracectl_b_groups[] = { + "gpio20", +}; + +static const char * const qdss_cti_trig_in_b0_groups[] = { + "gpio21", +}; + +static const char * const blsp_uart1_groups[] = { + "gpio22", "gpio23", "gpio24", "gpio25", +}; + +static const char * const blsp_spi_mosi_a1_groups[] = { + "gpio22", +}; + +static const char * const blsp_spi_miso_a1_groups[] = { + "gpio23", +}; + +static const char * const qdss_tracedata_b_groups[] = { + "gpio23", "gpio35", "gpio40", "gpio41", "gpio44", "gpio45", "gpio46", + "gpio47", "gpio49", "gpio50", "gpio55", "gpio61", "gpio62", "gpio85", + "gpio89", "gpio93", +}; + +static const char * const blsp_i2c1_groups[] = { + "gpio24", "gpio25", +}; + +static const char * const blsp_spi_cs_n_a1_groups[] = { + "gpio24", +}; + +static const char * const gcc_plltest_groups[] = { + "gpio24", "gpio25", +}; + +static const char * const blsp_spi_clk_a1_groups[] = { + "gpio25", +}; + +static const char * const rgb_data0_groups[] = { + "gpio26", "gpio41", +}; + +static const char * const blsp_uart5_groups[] = { + "gpio26", "gpio27", "gpio28", "gpio29", +}; + +static const char * const blsp_spi5_groups[] = { + "gpio26", "gpio27", "gpio28", "gpio29", "gpio44", "gpio45", "gpio46", +}; + +static const char * const adsp_ext_groups[] = { + "gpio26", +}; + +static const char * const rgb_data1_groups[] = { + "gpio27", "gpio42", +}; + +static const char * const prng_rosc_groups[] = { + "gpio27", +}; + +static const char * const rgb_data2_groups[] = { + "gpio28", "gpio43", +}; + +static const char * const blsp_i2c5_groups[] = { + "gpio28", "gpio29", +}; + +static const char * const gcc_gp1_clk_b_groups[] = { + "gpio28", +}; + +static const char * const rgb_data3_groups[] = { + "gpio29", "gpio44", +}; + +static const char * const gcc_gp2_clk_b_groups[] = { + "gpio29", +}; + +static const char * const blsp_spi0_groups[] = { + "gpio30", "gpio31", "gpio32", "gpio33", +}; + +static const char * const blsp_uart0_groups[] = { + "gpio30", "gpio31", "gpio32", "gpio33", +}; + +static const char * const gcc_gp3_clk_b_groups[] = { + "gpio30", +}; + +static const char * const blsp_i2c0_groups[] = { + "gpio32", "gpio33", +}; + +static const char * const qdss_traceclk_b_groups[] = { + "gpio34", +}; + +static const char * const pcie_clk_groups[] = { + "gpio35", +}; + +static const char * const nfc_irq_groups[] = { + "gpio37", +}; + +static const char * const blsp_spi4_groups[] = { + "gpio37", "gpio38", "gpio117", "gpio118", +}; + +static const char * const nfc_dwl_groups[] = { + "gpio38", +}; + +static const char * const audio_ts_groups[] = { + "gpio38", +}; + +static const char * const rgb_data4_groups[] = { + "gpio39", "gpio45", +}; + +static const char * const spi_lcd_groups[] = { + "gpio39", "gpio40", +}; + +static const char * const blsp_uart_tx_b2_groups[] = { + "gpio39", +}; + +static const char * const gcc_gp3_clk_a_groups[] = { + "gpio39", +}; + +static const char * const rgb_data5_groups[] = { + "gpio40", "gpio46", +}; + +static const char * const blsp_uart_rx_b2_groups[] = { + "gpio40", +}; + +static const char * const blsp_i2c_sda_b2_groups[] = { + "gpio41", +}; + +static const char * const blsp_i2c_scl_b2_groups[] = { + "gpio42", +}; + +static const char * const pwm_led11_groups[] = { + "gpio43", +}; + +static const char * const i2s_3_data0_a_groups[] = { + "gpio106", +}; + +static const char * const ebi2_lcd_groups[] = { + "gpio106", "gpio107", "gpio108", "gpio109", +}; + +static const char * const i2s_3_data1_a_groups[] = { + "gpio107", +}; + +static const char * const i2s_3_data2_a_groups[] = { + "gpio108", +}; + +static const char * const atest_char_groups[] = { + "gpio108", +}; + +static const char * const pwm_led3_groups[] = { + "gpio108", +}; + +static const char * const i2s_3_data3_a_groups[] = { + "gpio109", +}; + +static const char * const pwm_led4_groups[] = { + "gpio109", +}; + +static const char * const i2s_4_groups[] = { + "gpio110", "gpio111", "gpio111", "gpio112", "gpio112", "gpio113", + "gpio113", "gpio114", "gpio114", "gpio115", "gpio115", "gpio116", +}; + +static const char * const ebi2_a_groups[] = { + "gpio110", +}; + +static const char * const dsd_clk_b_groups[] = { + "gpio110", +}; + +static const char * const pwm_led5_groups[] = { + "gpio110", +}; + +static const char * const pwm_led6_groups[] = { + "gpio111", +}; + +static const char * const pwm_led7_groups[] = { + "gpio112", +}; + +static const char * const pwm_led8_groups[] = { + "gpio113", +}; + +static const char * const pwm_led24_groups[] = { + "gpio114", +}; + +static const char * const spkr_dac0_groups[] = { + "gpio116", +}; + +static const char * const blsp_i2c4_groups[] = { + "gpio117", "gpio118", +}; + +static const char * const pwm_led9_groups[] = { + "gpio117", +}; + +static const char * const pwm_led10_groups[] = { + "gpio118", +}; + +static const char * const spdifrx_opt_groups[] = { + "gpio119", +}; + +static const char * const pwm_led12_groups[] = { + "gpio44", +}; + +static const char * const pwm_led13_groups[] = { + "gpio45", +}; + +static const char * const pwm_led14_groups[] = { + "gpio46", +}; + +static const char * const wlan1_adc1_groups[] = { + "gpio46", +}; + +static const char * const rgb_data_b0_groups[] = { + "gpio47", +}; + +static const char * const pwm_led15_groups[] = { + "gpio47", +}; + +static const char * const blsp_spi_mosi_b1_groups[] = { + "gpio47", +}; + +static const char * const wlan1_adc0_groups[] = { + "gpio47", +}; + +static const char * const rgb_data_b1_groups[] = { + "gpio48", +}; + +static const char * const pwm_led16_groups[] = { + "gpio48", +}; + +static const char * const blsp_spi_miso_b1_groups[] = { + "gpio48", +}; + +static const char * const qdss_cti_trig_out_b0_groups[] = { + "gpio48", +}; + +static const char * const wlan2_adc1_groups[] = { + "gpio48", +}; + +static const char * const rgb_data_b2_groups[] = { + "gpio49", +}; + +static const char * const pwm_led17_groups[] = { + "gpio49", +}; + +static const char * const blsp_spi_cs_n_b1_groups[] = { + "gpio49", +}; + +static const char * const wlan2_adc0_groups[] = { + "gpio49", +}; + +static const char * const rgb_data_b3_groups[] = { + "gpio50", +}; + +static const char * const pwm_led18_groups[] = { + "gpio50", +}; + +static const char * const blsp_spi_clk_b1_groups[] = { + "gpio50", +}; + +static const char * const rgb_data_b4_groups[] = { + "gpio51", +}; + +static const char * const pwm_led19_groups[] = { + "gpio51", +}; + +static const char * const ext_mclk1_b_groups[] = { + "gpio51", +}; + +static const char * const qdss_traceclk_a_groups[] = { + "gpio51", +}; + +static const char * const rgb_data_b5_groups[] = { + "gpio52", +}; + +static const char * const pwm_led20_groups[] = { + "gpio52", +}; + +static const char * const atest_char3_groups[] = { + "gpio52", +}; + +static const char * const i2s_3_sck_b_groups[] = { + "gpio52", +}; + +static const char * const ldo_update_groups[] = { + "gpio52", +}; + +static const char * const bimc_dte0_groups[] = { + "gpio52", "gpio54", +}; + +static const char * const rgb_hsync_groups[] = { + "gpio53", +}; + +static const char * const pwm_led21_groups[] = { + "gpio53", +}; + +static const char * const i2s_3_ws_b_groups[] = { + "gpio53", +}; + +static const char * const dbg_out_groups[] = { + "gpio53", +}; + +static const char * const rgb_vsync_groups[] = { + "gpio54", +}; + +static const char * const i2s_3_data0_b_groups[] = { + "gpio54", +}; + +static const char * const ldo_en_groups[] = { + "gpio54", +}; + +static const char * const hdmi_dtest_groups[] = { + "gpio54", +}; + +static const char * const rgb_de_groups[] = { + "gpio55", +}; + +static const char * const i2s_3_data1_b_groups[] = { + "gpio55", +}; + +static const char * const hdmi_lbk9_groups[] = { + "gpio55", +}; + +static const char * const rgb_clk_groups[] = { + "gpio56", +}; + +static const char * const atest_char1_groups[] = { + "gpio56", +}; + +static const char * const i2s_3_data2_b_groups[] = { + "gpio56", +}; + +static const char * const ebi_cdc_groups[] = { + "gpio56", "gpio58", "gpio106", "gpio107", "gpio108", "gpio111", +}; + +static const char * const hdmi_lbk8_groups[] = { + "gpio56", +}; + +static const char * const rgb_mdp_groups[] = { + "gpio57", +}; + +static const char * const atest_char0_groups[] = { + "gpio57", +}; + +static const char * const i2s_3_data3_b_groups[] = { + "gpio57", +}; + +static const char * const hdmi_lbk7_groups[] = { + "gpio57", +}; + +static const char * const rgb_data_b6_groups[] = { + "gpio58", +}; + +static const char * const rgb_data_b7_groups[] = { + "gpio59", +}; + +static const char * const hdmi_lbk6_groups[] = { + "gpio59", +}; + +static const char * const rgmii_int_groups[] = { + "gpio61", +}; + +static const char * const cri_trng1_groups[] = { + "gpio61", +}; + +static const char * const rgmii_wol_groups[] = { + "gpio62", +}; + +static const char * const cri_trng0_groups[] = { + "gpio62", +}; + +static const char * const gcc_tlmm_groups[] = { + "gpio62", +}; + +static const char * const rgmii_ck_groups[] = { + "gpio63", "gpio69", +}; + +static const char * const rgmii_tx_groups[] = { + "gpio64", "gpio65", "gpio66", "gpio67", +}; + +static const char * const hdmi_lbk5_groups[] = { + "gpio64", +}; + +static const char * const hdmi_pixel_groups[] = { + "gpio65", +}; + +static const char * const hdmi_rcv_groups[] = { + "gpio66", +}; + +static const char * const hdmi_lbk4_groups[] = { + "gpio67", +}; + +static const char * const rgmii_ctl_groups[] = { + "gpio68", "gpio74", +}; + +static const char * const ext_lpass_groups[] = { + "gpio69", +}; + +static const char * const rgmii_rx_groups[] = { + "gpio70", "gpio71", "gpio72", "gpio73", +}; + +static const char * const cri_trng_groups[] = { + "gpio70", +}; + +static const char * const hdmi_lbk3_groups[] = { + "gpio71", +}; + +static const char * const hdmi_lbk2_groups[] = { + "gpio72", +}; + +static const char * const qdss_cti_trig_out_b1_groups[] = { + "gpio73", +}; + +static const char * const rgmii_mdio_groups[] = { + "gpio75", +}; + +static const char * const hdmi_lbk1_groups[] = { + "gpio75", +}; + +static const char * const rgmii_mdc_groups[] = { + "gpio76", +}; + +static const char * const hdmi_lbk0_groups[] = { + "gpio76", +}; + +static const char * const ir_in_groups[] = { + "gpio77", +}; + +static const char * const wsa_en_groups[] = { + "gpio77", +}; + +static const char * const rgb_data6_groups[] = { + "gpio78", "gpio80", +}; + +static const char * const rgb_data7_groups[] = { + "gpio79", "gpio81", +}; + +static const char * const atest_char2_groups[] = { + "gpio80", +}; + +static const char * const ebi_ch0_groups[] = { + "gpio81", +}; + +static const char * const blsp_uart3_groups[] = { + "gpio82", "gpio83", "gpio84", "gpio85", +}; + +static const char * const blsp_spi3_groups[] = { + "gpio82", "gpio83", "gpio84", "gpio85", +}; + +static const char * const sd_write_groups[] = { + "gpio82", +}; + +static const char * const blsp_i2c3_groups[] = { + "gpio84", "gpio85", +}; + +static const char * const gcc_gp1_clk_a_groups[] = { + "gpio84", +}; + +static const char * const qdss_cti_trig_in_b1_groups[] = { + "gpio84", +}; + +static const char * const gcc_gp2_clk_a_groups[] = { + "gpio85", +}; + +static const char * const ext_mclk0_groups[] = { + "gpio86", +}; + +static const char * const mclk_in1_groups[] = { + "gpio86", +}; + +static const char * const i2s_1_groups[] = { + "gpio87", "gpio88", "gpio88", "gpio89", "gpio89", "gpio90", "gpio90", + "gpio91", "gpio91", "gpio92", "gpio92", "gpio93", "gpio93", "gpio94", + "gpio94", "gpio95", "gpio95", "gpio96", +}; + +static const char * const dsd_clk_a_groups[] = { + "gpio87", +}; + +static const char * const qdss_cti_trig_in_a1_groups[] = { + "gpio92", +}; + +static const char * const rgmi_dll1_groups[] = { + "gpio92", +}; + +static const char * const pwm_led22_groups[] = { + "gpio93", +}; + +static const char * const pwm_led23_groups[] = { + "gpio94", +}; + +static const char * const qdss_cti_trig_out_a0_groups[] = { + "gpio94", +}; + +static const char * const rgmi_dll2_groups[] = { + "gpio94", +}; + +static const char * const pwm_led1_groups[] = { + "gpio95", +}; + +static const char * const qdss_cti_trig_out_a1_groups[] = { + "gpio95", +}; + +static const char * const pwm_led2_groups[] = { + "gpio96", +}; + +static const char * const i2s_2_groups[] = { + "gpio97", "gpio98", "gpio99", "gpio100", "gpio101", "gpio102", +}; + +static const char * const pll_bist_groups[] = { + "gpio100", +}; + +static const char * const ext_mclk1_a_groups[] = { + "gpio103", +}; + +static const char * const mclk_in2_groups[] = { + "gpio103", +}; + +static const char * const bimc_dte1_groups[] = { + "gpio103", "gpio109", +}; + +static const char * const i2s_3_sck_a_groups[] = { + "gpio104", +}; + +static const char * const i2s_3_ws_a_groups[] = { + "gpio105", +}; + +static const struct pinfunction qcs404_functions[] = { + MSM_PIN_FUNCTION(gpio), + MSM_PIN_FUNCTION(hdmi_tx), + MSM_PIN_FUNCTION(hdmi_ddc), + MSM_PIN_FUNCTION(blsp_uart_tx_a2), + MSM_PIN_FUNCTION(blsp_spi2), + MSM_PIN_FUNCTION(m_voc), + MSM_PIN_FUNCTION(qdss_cti_trig_in_a0), + MSM_PIN_FUNCTION(blsp_uart_rx_a2), + MSM_PIN_FUNCTION(qdss_tracectl_a), + MSM_PIN_FUNCTION(blsp_uart2), + MSM_PIN_FUNCTION(aud_cdc), + MSM_PIN_FUNCTION(blsp_i2c_sda_a2), + MSM_PIN_FUNCTION(qdss_tracedata_a), + MSM_PIN_FUNCTION(blsp_i2c_scl_a2), + MSM_PIN_FUNCTION(qdss_tracectl_b), + MSM_PIN_FUNCTION(qdss_cti_trig_in_b0), + MSM_PIN_FUNCTION(blsp_uart1), + MSM_PIN_FUNCTION(blsp_spi_mosi_a1), + MSM_PIN_FUNCTION(blsp_spi_miso_a1), + MSM_PIN_FUNCTION(qdss_tracedata_b), + MSM_PIN_FUNCTION(blsp_i2c1), + MSM_PIN_FUNCTION(blsp_spi_cs_n_a1), + MSM_PIN_FUNCTION(gcc_plltest), + MSM_PIN_FUNCTION(blsp_spi_clk_a1), + MSM_PIN_FUNCTION(rgb_data0), + MSM_PIN_FUNCTION(blsp_uart5), + MSM_PIN_FUNCTION(blsp_spi5), + MSM_PIN_FUNCTION(adsp_ext), + MSM_PIN_FUNCTION(rgb_data1), + MSM_PIN_FUNCTION(prng_rosc), + MSM_PIN_FUNCTION(rgb_data2), + MSM_PIN_FUNCTION(blsp_i2c5), + MSM_PIN_FUNCTION(gcc_gp1_clk_b), + MSM_PIN_FUNCTION(rgb_data3), + MSM_PIN_FUNCTION(gcc_gp2_clk_b), + MSM_PIN_FUNCTION(blsp_spi0), + MSM_PIN_FUNCTION(blsp_uart0), + MSM_PIN_FUNCTION(gcc_gp3_clk_b), + MSM_PIN_FUNCTION(blsp_i2c0), + MSM_PIN_FUNCTION(qdss_traceclk_b), + MSM_PIN_FUNCTION(pcie_clk), + MSM_PIN_FUNCTION(nfc_irq), + MSM_PIN_FUNCTION(blsp_spi4), + MSM_PIN_FUNCTION(nfc_dwl), + MSM_PIN_FUNCTION(audio_ts), + MSM_PIN_FUNCTION(rgb_data4), + MSM_PIN_FUNCTION(spi_lcd), + MSM_PIN_FUNCTION(blsp_uart_tx_b2), + MSM_PIN_FUNCTION(gcc_gp3_clk_a), + MSM_PIN_FUNCTION(rgb_data5), + MSM_PIN_FUNCTION(blsp_uart_rx_b2), + MSM_PIN_FUNCTION(blsp_i2c_sda_b2), + MSM_PIN_FUNCTION(blsp_i2c_scl_b2), + MSM_PIN_FUNCTION(pwm_led11), + MSM_PIN_FUNCTION(i2s_3_data0_a), + MSM_PIN_FUNCTION(ebi2_lcd), + MSM_PIN_FUNCTION(i2s_3_data1_a), + MSM_PIN_FUNCTION(i2s_3_data2_a), + MSM_PIN_FUNCTION(atest_char), + MSM_PIN_FUNCTION(pwm_led3), + MSM_PIN_FUNCTION(i2s_3_data3_a), + MSM_PIN_FUNCTION(pwm_led4), + MSM_PIN_FUNCTION(i2s_4), + MSM_PIN_FUNCTION(ebi2_a), + MSM_PIN_FUNCTION(dsd_clk_b), + MSM_PIN_FUNCTION(pwm_led5), + MSM_PIN_FUNCTION(pwm_led6), + MSM_PIN_FUNCTION(pwm_led7), + MSM_PIN_FUNCTION(pwm_led8), + MSM_PIN_FUNCTION(pwm_led24), + MSM_PIN_FUNCTION(spkr_dac0), + MSM_PIN_FUNCTION(blsp_i2c4), + MSM_PIN_FUNCTION(pwm_led9), + MSM_PIN_FUNCTION(pwm_led10), + MSM_PIN_FUNCTION(spdifrx_opt), + MSM_PIN_FUNCTION(pwm_led12), + MSM_PIN_FUNCTION(pwm_led13), + MSM_PIN_FUNCTION(pwm_led14), + MSM_PIN_FUNCTION(wlan1_adc1), + MSM_PIN_FUNCTION(rgb_data_b0), + MSM_PIN_FUNCTION(pwm_led15), + MSM_PIN_FUNCTION(blsp_spi_mosi_b1), + MSM_PIN_FUNCTION(wlan1_adc0), + MSM_PIN_FUNCTION(rgb_data_b1), + MSM_PIN_FUNCTION(pwm_led16), + MSM_PIN_FUNCTION(blsp_spi_miso_b1), + MSM_PIN_FUNCTION(qdss_cti_trig_out_b0), + MSM_PIN_FUNCTION(wlan2_adc1), + MSM_PIN_FUNCTION(rgb_data_b2), + MSM_PIN_FUNCTION(pwm_led17), + MSM_PIN_FUNCTION(blsp_spi_cs_n_b1), + MSM_PIN_FUNCTION(wlan2_adc0), + MSM_PIN_FUNCTION(rgb_data_b3), + MSM_PIN_FUNCTION(pwm_led18), + MSM_PIN_FUNCTION(blsp_spi_clk_b1), + MSM_PIN_FUNCTION(rgb_data_b4), + MSM_PIN_FUNCTION(pwm_led19), + MSM_PIN_FUNCTION(ext_mclk1_b), + MSM_PIN_FUNCTION(qdss_traceclk_a), + MSM_PIN_FUNCTION(rgb_data_b5), + MSM_PIN_FUNCTION(pwm_led20), + MSM_PIN_FUNCTION(atest_char3), + MSM_PIN_FUNCTION(i2s_3_sck_b), + MSM_PIN_FUNCTION(ldo_update), + MSM_PIN_FUNCTION(bimc_dte0), + MSM_PIN_FUNCTION(rgb_hsync), + MSM_PIN_FUNCTION(pwm_led21), + MSM_PIN_FUNCTION(i2s_3_ws_b), + MSM_PIN_FUNCTION(dbg_out), + MSM_PIN_FUNCTION(rgb_vsync), + MSM_PIN_FUNCTION(i2s_3_data0_b), + MSM_PIN_FUNCTION(ldo_en), + MSM_PIN_FUNCTION(hdmi_dtest), + MSM_PIN_FUNCTION(rgb_de), + MSM_PIN_FUNCTION(i2s_3_data1_b), + MSM_PIN_FUNCTION(hdmi_lbk9), + MSM_PIN_FUNCTION(rgb_clk), + MSM_PIN_FUNCTION(atest_char1), + MSM_PIN_FUNCTION(i2s_3_data2_b), + MSM_PIN_FUNCTION(ebi_cdc), + MSM_PIN_FUNCTION(hdmi_lbk8), + MSM_PIN_FUNCTION(rgb_mdp), + MSM_PIN_FUNCTION(atest_char0), + MSM_PIN_FUNCTION(i2s_3_data3_b), + MSM_PIN_FUNCTION(hdmi_lbk7), + MSM_PIN_FUNCTION(rgb_data_b6), + MSM_PIN_FUNCTION(rgb_data_b7), + MSM_PIN_FUNCTION(hdmi_lbk6), + MSM_PIN_FUNCTION(rgmii_int), + MSM_PIN_FUNCTION(cri_trng1), + MSM_PIN_FUNCTION(rgmii_wol), + MSM_PIN_FUNCTION(cri_trng0), + MSM_PIN_FUNCTION(gcc_tlmm), + MSM_PIN_FUNCTION(rgmii_ck), + MSM_PIN_FUNCTION(rgmii_tx), + MSM_PIN_FUNCTION(hdmi_lbk5), + MSM_PIN_FUNCTION(hdmi_pixel), + MSM_PIN_FUNCTION(hdmi_rcv), + MSM_PIN_FUNCTION(hdmi_lbk4), + MSM_PIN_FUNCTION(rgmii_ctl), + MSM_PIN_FUNCTION(ext_lpass), + MSM_PIN_FUNCTION(rgmii_rx), + MSM_PIN_FUNCTION(cri_trng), + MSM_PIN_FUNCTION(hdmi_lbk3), + MSM_PIN_FUNCTION(hdmi_lbk2), + MSM_PIN_FUNCTION(qdss_cti_trig_out_b1), + MSM_PIN_FUNCTION(rgmii_mdio), + MSM_PIN_FUNCTION(hdmi_lbk1), + MSM_PIN_FUNCTION(rgmii_mdc), + MSM_PIN_FUNCTION(hdmi_lbk0), + MSM_PIN_FUNCTION(ir_in), + MSM_PIN_FUNCTION(wsa_en), + MSM_PIN_FUNCTION(rgb_data6), + MSM_PIN_FUNCTION(rgb_data7), + MSM_PIN_FUNCTION(atest_char2), + MSM_PIN_FUNCTION(ebi_ch0), + MSM_PIN_FUNCTION(blsp_uart3), + MSM_PIN_FUNCTION(blsp_spi3), + MSM_PIN_FUNCTION(sd_write), + MSM_PIN_FUNCTION(blsp_i2c3), + MSM_PIN_FUNCTION(gcc_gp1_clk_a), + MSM_PIN_FUNCTION(qdss_cti_trig_in_b1), + MSM_PIN_FUNCTION(gcc_gp2_clk_a), + MSM_PIN_FUNCTION(ext_mclk0), + MSM_PIN_FUNCTION(mclk_in1), + MSM_PIN_FUNCTION(i2s_1), + MSM_PIN_FUNCTION(dsd_clk_a), + MSM_PIN_FUNCTION(qdss_cti_trig_in_a1), + MSM_PIN_FUNCTION(rgmi_dll1), + MSM_PIN_FUNCTION(pwm_led22), + MSM_PIN_FUNCTION(pwm_led23), + MSM_PIN_FUNCTION(qdss_cti_trig_out_a0), + MSM_PIN_FUNCTION(rgmi_dll2), + MSM_PIN_FUNCTION(pwm_led1), + MSM_PIN_FUNCTION(qdss_cti_trig_out_a1), + MSM_PIN_FUNCTION(pwm_led2), + MSM_PIN_FUNCTION(i2s_2), + MSM_PIN_FUNCTION(pll_bist), + MSM_PIN_FUNCTION(ext_mclk1_a), + MSM_PIN_FUNCTION(mclk_in2), + MSM_PIN_FUNCTION(bimc_dte1), + MSM_PIN_FUNCTION(i2s_3_sck_a), + MSM_PIN_FUNCTION(i2s_3_ws_a), +}; + +/* Every pin is maintained as a single group, and missing or non-existing pin + * would be maintained as dummy group to synchronize pin group index with + * pin descriptor registered with pinctrl core. + * Clients would not be able to request these dummy pin groups. + */ +static const struct msm_pingroup qcs404_groups[] = { + [0] = PINGROUP(0, SOUTH, _, _, _, _, _, _, _, _, _), + [1] = PINGROUP(1, SOUTH, _, _, _, _, _, _, _, _, _), + [2] = PINGROUP(2, SOUTH, _, _, _, _, _, _, _, _, _), + [3] = PINGROUP(3, SOUTH, _, _, _, _, _, _, _, _, _), + [4] = PINGROUP(4, SOUTH, _, _, _, _, _, _, _, _, _), + [5] = PINGROUP(5, SOUTH, _, _, _, _, _, _, _, _, _), + [6] = PINGROUP(6, SOUTH, _, _, _, _, _, _, _, _, _), + [7] = PINGROUP(7, SOUTH, _, _, _, _, _, _, _, _, _), + [8] = PINGROUP(8, SOUTH, _, _, _, _, _, _, _, _, _), + [9] = PINGROUP(9, SOUTH, _, _, _, _, _, _, _, _, _), + [10] = PINGROUP(10, SOUTH, _, _, _, _, _, _, _, _, _), + [11] = PINGROUP(11, SOUTH, _, _, _, _, _, _, _, _, _), + [12] = PINGROUP(12, SOUTH, _, _, _, _, _, _, _, _, _), + [13] = PINGROUP(13, SOUTH, _, _, _, _, _, _, _, _, _), + [14] = PINGROUP(14, SOUTH, hdmi_tx, _, _, _, _, _, _, _, _), + [15] = PINGROUP(15, SOUTH, hdmi_ddc, _, _, _, _, _, _, _, _), + [16] = PINGROUP(16, SOUTH, hdmi_ddc, _, _, _, _, _, _, _, _), + [17] = PINGROUP(17, NORTH, blsp_uart_tx_a2, blsp_spi2, m_voc, _, _, _, _, _, _), + [18] = PINGROUP(18, NORTH, blsp_uart_rx_a2, blsp_spi2, _, _, _, _, _, qdss_tracectl_a, _), + [19] = PINGROUP(19, NORTH, blsp_uart2, aud_cdc, blsp_i2c_sda_a2, blsp_spi2, _, qdss_tracedata_a, _, _, _), + [20] = PINGROUP(20, NORTH, blsp_uart2, aud_cdc, blsp_i2c_scl_a2, blsp_spi2, _, _, _, _, _), + [21] = PINGROUP(21, SOUTH, m_voc, _, _, _, _, _, _, _, qdss_cti_trig_in_b0), + [22] = PINGROUP(22, NORTH, blsp_uart1, blsp_spi_mosi_a1, _, _, _, _, _, _, _), + [23] = PINGROUP(23, NORTH, blsp_uart1, blsp_spi_miso_a1, _, _, _, _, _, qdss_tracedata_b, _), + [24] = PINGROUP(24, NORTH, blsp_uart1, blsp_i2c1, blsp_spi_cs_n_a1, gcc_plltest, _, _, _, _, _), + [25] = PINGROUP(25, NORTH, blsp_uart1, blsp_i2c1, blsp_spi_clk_a1, gcc_plltest, _, _, _, _, _), + [26] = PINGROUP(26, EAST, rgb_data0, blsp_uart5, blsp_spi5, adsp_ext, _, _, _, _, _), + [27] = PINGROUP(27, EAST, rgb_data1, blsp_uart5, blsp_spi5, prng_rosc, _, _, _, _, _), + [28] = PINGROUP(28, EAST, rgb_data2, blsp_uart5, blsp_i2c5, blsp_spi5, gcc_gp1_clk_b, _, _, _, _), + [29] = PINGROUP(29, EAST, rgb_data3, blsp_uart5, blsp_i2c5, blsp_spi5, gcc_gp2_clk_b, _, _, _, _), + [30] = PINGROUP(30, NORTH, blsp_spi0, blsp_uart0, gcc_gp3_clk_b, _, _, _, _, _, _), + [31] = PINGROUP(31, NORTH, blsp_spi0, blsp_uart0, _, _, _, _, _, _, _), + [32] = PINGROUP(32, NORTH, blsp_spi0, blsp_uart0, blsp_i2c0, _, _, _, _, _, _), + [33] = PINGROUP(33, NORTH, blsp_spi0, blsp_uart0, blsp_i2c0, _, _, _, _, _, _), + [34] = PINGROUP(34, SOUTH, _, qdss_traceclk_b, _, _, _, _, _, _, _), + [35] = PINGROUP(35, SOUTH, pcie_clk, _, qdss_tracedata_b, _, _, _, _, _, _), + [36] = PINGROUP(36, NORTH, _, _, _, _, _, _, qdss_tracedata_a, _, _), + [37] = PINGROUP(37, NORTH, nfc_irq, blsp_spi4, _, _, _, _, _, _, _), + [38] = PINGROUP(38, NORTH, nfc_dwl, blsp_spi4, audio_ts, _, _, _, _, _, _), + [39] = PINGROUP(39, EAST, rgb_data4, spi_lcd, blsp_uart_tx_b2, gcc_gp3_clk_a, qdss_tracedata_a, _, _, _, _), + [40] = PINGROUP(40, EAST, rgb_data5, spi_lcd, blsp_uart_rx_b2, _, qdss_tracedata_b, _, _, _, _), + [41] = PINGROUP(41, EAST, rgb_data0, blsp_i2c_sda_b2, _, qdss_tracedata_b, _, _, _, _, _), + [42] = PINGROUP(42, EAST, rgb_data1, blsp_i2c_scl_b2, _, _, _, _, _, qdss_tracedata_a, _), + [43] = PINGROUP(43, EAST, rgb_data2, pwm_led11, _, _, _, _, _, _, _), + [44] = PINGROUP(44, EAST, rgb_data3, pwm_led12, blsp_spi5, _, _, _, _, _, _), + [45] = PINGROUP(45, EAST, rgb_data4, pwm_led13, blsp_spi5, qdss_tracedata_b, _, _, _, _, _), + [46] = PINGROUP(46, EAST, rgb_data5, pwm_led14, blsp_spi5, qdss_tracedata_b, _, wlan1_adc1, _, _, _), + [47] = PINGROUP(47, EAST, rgb_data_b0, pwm_led15, blsp_spi_mosi_b1, qdss_tracedata_b, _, wlan1_adc0, _, _, _), + [48] = PINGROUP(48, EAST, rgb_data_b1, pwm_led16, blsp_spi_miso_b1, _, qdss_cti_trig_out_b0, _, wlan2_adc1, _, _), + [49] = PINGROUP(49, EAST, rgb_data_b2, pwm_led17, blsp_spi_cs_n_b1, _, qdss_tracedata_b, _, wlan2_adc0, _, _), + [50] = PINGROUP(50, EAST, rgb_data_b3, pwm_led18, blsp_spi_clk_b1, qdss_tracedata_b, _, _, _, _, _), + [51] = PINGROUP(51, EAST, rgb_data_b4, pwm_led19, ext_mclk1_b, qdss_traceclk_a, _, _, _, _, _), + [52] = PINGROUP(52, EAST, rgb_data_b5, pwm_led20, atest_char3, i2s_3_sck_b, ldo_update, bimc_dte0, _, _, _), + [53] = PINGROUP(53, EAST, rgb_hsync, pwm_led21, i2s_3_ws_b, dbg_out, _, _, _, _, _), + [54] = PINGROUP(54, EAST, rgb_vsync, i2s_3_data0_b, ldo_en, bimc_dte0, _, hdmi_dtest, _, _, _), + [55] = PINGROUP(55, EAST, rgb_de, i2s_3_data1_b, _, qdss_tracedata_b, _, hdmi_lbk9, _, _, _), + [56] = PINGROUP(56, EAST, rgb_clk, atest_char1, i2s_3_data2_b, ebi_cdc, _, hdmi_lbk8, _, _, _), + [57] = PINGROUP(57, EAST, rgb_mdp, atest_char0, i2s_3_data3_b, _, hdmi_lbk7, _, _, _, _), + [58] = PINGROUP(58, EAST, rgb_data_b6, _, ebi_cdc, _, _, _, _, _, _), + [59] = PINGROUP(59, EAST, rgb_data_b7, _, hdmi_lbk6, _, _, _, _, _, _), + [60] = PINGROUP(60, NORTH, _, _, _, _, _, _, _, _, _), + [61] = PINGROUP(61, NORTH, rgmii_int, cri_trng1, qdss_tracedata_b, _, _, _, _, _, _), + [62] = PINGROUP(62, NORTH, rgmii_wol, cri_trng0, qdss_tracedata_b, gcc_tlmm, _, _, _, _, _), + [63] = PINGROUP(63, NORTH, rgmii_ck, _, _, _, _, _, _, _, _), + [64] = PINGROUP(64, NORTH, rgmii_tx, _, hdmi_lbk5, _, _, _, _, _, _), + [65] = PINGROUP(65, NORTH, rgmii_tx, _, hdmi_pixel, _, _, _, _, _, _), + [66] = PINGROUP(66, NORTH, rgmii_tx, _, hdmi_rcv, _, _, _, _, _, _), + [67] = PINGROUP(67, NORTH, rgmii_tx, _, hdmi_lbk4, _, _, _, _, _, _), + [68] = PINGROUP(68, NORTH, rgmii_ctl, _, _, _, _, _, _, _, _), + [69] = PINGROUP(69, NORTH, rgmii_ck, ext_lpass, _, _, _, _, _, _, _), + [70] = PINGROUP(70, NORTH, rgmii_rx, cri_trng, _, _, _, _, _, _, _), + [71] = PINGROUP(71, NORTH, rgmii_rx, _, hdmi_lbk3, _, _, _, _, _, _), + [72] = PINGROUP(72, NORTH, rgmii_rx, _, hdmi_lbk2, _, _, _, _, _, _), + [73] = PINGROUP(73, NORTH, rgmii_rx, _, _, _, _, qdss_cti_trig_out_b1, _, _, _), + [74] = PINGROUP(74, NORTH, rgmii_ctl, _, _, _, _, _, _, _, _), + [75] = PINGROUP(75, NORTH, rgmii_mdio, _, hdmi_lbk1, _, _, _, _, _, _), + [76] = PINGROUP(76, NORTH, rgmii_mdc, _, _, _, _, _, hdmi_lbk0, _, _), + [77] = PINGROUP(77, NORTH, ir_in, wsa_en, _, _, _, _, _, _, _), + [78] = PINGROUP(78, EAST, rgb_data6, _, _, _, _, _, _, _, _), + [79] = PINGROUP(79, EAST, rgb_data7, _, _, _, _, _, _, _, _), + [80] = PINGROUP(80, EAST, rgb_data6, atest_char2, _, _, _, _, _, _, _), + [81] = PINGROUP(81, EAST, rgb_data7, ebi_ch0, _, _, _, _, _, _, _), + [82] = PINGROUP(82, NORTH, blsp_uart3, blsp_spi3, sd_write, _, _, _, _, _, qdss_tracedata_a), + [83] = PINGROUP(83, NORTH, blsp_uart3, blsp_spi3, _, _, _, _, qdss_tracedata_a, _, _), + [84] = PINGROUP(84, NORTH, blsp_uart3, blsp_i2c3, blsp_spi3, gcc_gp1_clk_a, qdss_cti_trig_in_b1, _, _, _, _), + [85] = PINGROUP(85, NORTH, blsp_uart3, blsp_i2c3, blsp_spi3, gcc_gp2_clk_a, qdss_tracedata_b, _, _, _, _), + [86] = PINGROUP(86, EAST, ext_mclk0, mclk_in1, _, _, _, _, _, _, _), + [87] = PINGROUP(87, EAST, i2s_1, dsd_clk_a, _, _, _, _, _, _, _), + [88] = PINGROUP(88, EAST, i2s_1, i2s_1, _, _, _, _, _, _, _), + [89] = PINGROUP(89, EAST, i2s_1, i2s_1, _, _, _, _, _, _, qdss_tracedata_b), + [90] = PINGROUP(90, EAST, i2s_1, i2s_1, _, _, _, _, _, _, _), + [91] = PINGROUP(91, EAST, i2s_1, i2s_1, _, _, _, _, _, _, _), + [92] = PINGROUP(92, EAST, i2s_1, i2s_1, _, _, _, _, _, qdss_cti_trig_in_a1, _), + [93] = PINGROUP(93, EAST, i2s_1, pwm_led22, i2s_1, _, _, _, _, _, qdss_tracedata_b), + [94] = PINGROUP(94, EAST, i2s_1, pwm_led23, i2s_1, _, qdss_cti_trig_out_a0, _, rgmi_dll2, _, _), + [95] = PINGROUP(95, EAST, i2s_1, pwm_led1, i2s_1, _, qdss_cti_trig_out_a1, _, _, _, _), + [96] = PINGROUP(96, EAST, i2s_1, pwm_led2, _, _, _, _, _, _, _), + [97] = PINGROUP(97, EAST, i2s_2, _, _, _, _, _, _, _, _), + [98] = PINGROUP(98, EAST, i2s_2, _, _, _, _, _, _, _, _), + [99] = PINGROUP(99, EAST, i2s_2, _, _, _, _, _, _, _, _), + [100] = PINGROUP(100, EAST, i2s_2, pll_bist, _, _, _, _, _, _, _), + [101] = PINGROUP(101, EAST, i2s_2, _, _, _, _, _, _, _, _), + [102] = PINGROUP(102, EAST, i2s_2, _, _, _, _, _, _, _, _), + [103] = PINGROUP(103, EAST, ext_mclk1_a, mclk_in2, bimc_dte1, _, _, _, _, _, _), + [104] = PINGROUP(104, EAST, i2s_3_sck_a, _, _, _, _, _, _, _, _), + [105] = PINGROUP(105, EAST, i2s_3_ws_a, _, _, _, _, _, _, _, _), + [106] = PINGROUP(106, EAST, i2s_3_data0_a, ebi2_lcd, _, _, ebi_cdc, _, _, _, _), + [107] = PINGROUP(107, EAST, i2s_3_data1_a, ebi2_lcd, _, _, ebi_cdc, _, _, _, _), + [108] = PINGROUP(108, EAST, i2s_3_data2_a, ebi2_lcd, atest_char, pwm_led3, ebi_cdc, _, _, _, _), + [109] = PINGROUP(109, EAST, i2s_3_data3_a, ebi2_lcd, pwm_led4, bimc_dte1, _, _, _, _, _), + [110] = PINGROUP(110, EAST, i2s_4, ebi2_a, dsd_clk_b, pwm_led5, _, _, _, _, _), + [111] = PINGROUP(111, EAST, i2s_4, i2s_4, pwm_led6, ebi_cdc, _, _, _, _, _), + [112] = PINGROUP(112, EAST, i2s_4, i2s_4, pwm_led7, _, _, _, _, _, _), + [113] = PINGROUP(113, EAST, i2s_4, i2s_4, pwm_led8, _, _, _, _, _, _), + [114] = PINGROUP(114, EAST, i2s_4, i2s_4, pwm_led24, _, _, _, _, _, _), + [115] = PINGROUP(115, EAST, i2s_4, i2s_4, _, _, _, _, _, _, _), + [116] = PINGROUP(116, EAST, i2s_4, spkr_dac0, _, _, _, _, _, _, _), + [117] = PINGROUP(117, NORTH, blsp_i2c4, blsp_spi4, pwm_led9, _, _, _, _, _, _), + [118] = PINGROUP(118, NORTH, blsp_i2c4, blsp_spi4, pwm_led10, _, _, _, _, _, _), + [119] = PINGROUP(119, EAST, spdifrx_opt, _, _, _, _, _, _, _, _), + [120] = SDC_QDSD_PINGROUP(sdc1_rclk, 0xc2000, 15, 0), + [121] = SDC_QDSD_PINGROUP(sdc1_clk, 0xc2000, 13, 6), + [122] = SDC_QDSD_PINGROUP(sdc1_cmd, 0xc2000, 11, 3), + [123] = SDC_QDSD_PINGROUP(sdc1_data, 0xc2000, 9, 0), + [124] = SDC_QDSD_PINGROUP(sdc2_clk, 0xc3000, 14, 6), + [125] = SDC_QDSD_PINGROUP(sdc2_cmd, 0xc3000, 11, 3), + [126] = SDC_QDSD_PINGROUP(sdc2_data, 0xc3000, 9, 0), +}; + +static const struct msm_pinctrl_soc_data qcs404_pinctrl = { + .pins = qcs404_pins, + .npins = ARRAY_SIZE(qcs404_pins), + .functions = qcs404_functions, + .nfunctions = ARRAY_SIZE(qcs404_functions), + .groups = qcs404_groups, + .ngroups = ARRAY_SIZE(qcs404_groups), + .ngpios = 120, + .tiles = qcs404_tiles, + .ntiles = ARRAY_SIZE(qcs404_tiles), +}; + +static int qcs404_pinctrl_probe(struct platform_device *pdev) +{ + return msm_pinctrl_probe(pdev, &qcs404_pinctrl); +} + +static const struct of_device_id qcs404_pinctrl_of_match[] = { + { .compatible = "qcom,qcs404-pinctrl", }, + { }, +}; + +static struct platform_driver qcs404_pinctrl_driver = { + .driver = { + .name = "qcs404-pinctrl", + .of_match_table = qcs404_pinctrl_of_match, + }, + .probe = qcs404_pinctrl_probe, + .remove = msm_pinctrl_remove, +}; + +static int __init qcs404_pinctrl_init(void) +{ + return platform_driver_register(&qcs404_pinctrl_driver); +} +arch_initcall(qcs404_pinctrl_init); + +static void __exit qcs404_pinctrl_exit(void) +{ + platform_driver_unregister(&qcs404_pinctrl_driver); +} +module_exit(qcs404_pinctrl_exit); + +MODULE_DESCRIPTION("Qualcomm QCS404 pinctrl driver"); +MODULE_LICENSE("GPL v2"); +MODULE_DEVICE_TABLE(of, qcs404_pinctrl_of_match); diff --git a/drivers/pinctrl/qcom/pinctrl-qdf2xxx.c b/drivers/pinctrl/qcom/pinctrl-qdf2xxx.c new file mode 100644 index 0000000000..b5808fcfb1 --- /dev/null +++ b/drivers/pinctrl/qcom/pinctrl-qdf2xxx.c @@ -0,0 +1,164 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2015, The Linux Foundation. All rights reserved. + * + * GPIO and pin control functions on this SOC are handled by the "TLMM" + * device. The driver which controls this device is pinctrl-msm.c. Each + * SOC with a TLMM is expected to create a client driver that registers + * with pinctrl-msm.c. This means that all TLMM drivers are pin control + * drivers. + * + * This pin control driver is intended to be used only an ACPI-enabled + * system. As such, UEFI will handle all pin control configuration, so + * this driver does not provide pin control functions. It is effectively + * a GPIO-only driver. The alternative is to duplicate the GPIO code of + * pinctrl-msm.c into another driver. + */ + +#include <linux/module.h> +#include <linux/platform_device.h> +#include <linux/pinctrl/pinctrl.h> +#include <linux/acpi.h> + +#include "pinctrl-msm.h" + +/* A maximum of 256 allows us to use a u8 array to hold the GPIO numbers */ +#define MAX_GPIOS 256 + +/* maximum size of each gpio name (enough room for "gpioXXX" + null) */ +#define NAME_SIZE 8 + +static int qdf2xxx_pinctrl_probe(struct platform_device *pdev) +{ + struct msm_pinctrl_soc_data *pinctrl; + struct pinctrl_pin_desc *pins; + struct msm_pingroup *groups; + char (*names)[NAME_SIZE]; + unsigned int i; + u32 num_gpios; + unsigned int avail_gpios; /* The number of GPIOs we support */ + u8 gpios[MAX_GPIOS]; /* An array of supported GPIOs */ + int ret; + + /* Query the number of GPIOs from ACPI */ + ret = device_property_read_u32(&pdev->dev, "num-gpios", &num_gpios); + if (ret < 0) { + dev_err(&pdev->dev, "missing 'num-gpios' property\n"); + return ret; + } + if (!num_gpios || num_gpios > MAX_GPIOS) { + dev_err(&pdev->dev, "invalid 'num-gpios' property\n"); + return -ENODEV; + } + + /* The number of GPIOs in the approved list */ + ret = device_property_count_u8(&pdev->dev, "gpios"); + if (ret < 0) { + dev_err(&pdev->dev, "missing 'gpios' property\n"); + return ret; + } + /* + * The number of available GPIOs should be non-zero, and no + * more than the total number of GPIOS. + */ + if (!ret || ret > num_gpios) { + dev_err(&pdev->dev, "invalid 'gpios' property\n"); + return -ENODEV; + } + avail_gpios = ret; + + ret = device_property_read_u8_array(&pdev->dev, "gpios", gpios, + avail_gpios); + if (ret < 0) { + dev_err(&pdev->dev, "could not read list of GPIOs\n"); + return ret; + } + + pinctrl = devm_kzalloc(&pdev->dev, sizeof(*pinctrl), GFP_KERNEL); + pins = devm_kcalloc(&pdev->dev, num_gpios, + sizeof(struct pinctrl_pin_desc), GFP_KERNEL); + groups = devm_kcalloc(&pdev->dev, num_gpios, + sizeof(struct msm_pingroup), GFP_KERNEL); + names = devm_kcalloc(&pdev->dev, avail_gpios, NAME_SIZE, GFP_KERNEL); + + if (!pinctrl || !pins || !groups || !names) + return -ENOMEM; + + /* + * Initialize the array. GPIOs not listed in the 'gpios' array + * still need a number, but nothing else. + */ + for (i = 0; i < num_gpios; i++) { + pins[i].number = i; + groups[i].grp.pins = &pins[i].number; + } + + /* Populate the entries that are meant to be exposed as GPIOs. */ + for (i = 0; i < avail_gpios; i++) { + unsigned int gpio = gpios[i]; + + groups[gpio].grp.npins = 1; + snprintf(names[i], NAME_SIZE, "gpio%u", gpio); + pins[gpio].name = names[i]; + groups[gpio].grp.name = names[i]; + + groups[gpio].ctl_reg = 0x10000 * gpio; + groups[gpio].io_reg = 0x04 + 0x10000 * gpio; + groups[gpio].intr_cfg_reg = 0x08 + 0x10000 * gpio; + groups[gpio].intr_status_reg = 0x0c + 0x10000 * gpio; + groups[gpio].intr_target_reg = 0x08 + 0x10000 * gpio; + + groups[gpio].mux_bit = 2; + groups[gpio].pull_bit = 0; + groups[gpio].drv_bit = 6; + groups[gpio].oe_bit = 9; + groups[gpio].in_bit = 0; + groups[gpio].out_bit = 1; + groups[gpio].intr_enable_bit = 0; + groups[gpio].intr_status_bit = 0; + groups[gpio].intr_target_bit = 5; + groups[gpio].intr_target_kpss_val = 1; + groups[gpio].intr_raw_status_bit = 4; + groups[gpio].intr_polarity_bit = 1; + groups[gpio].intr_detection_bit = 2; + groups[gpio].intr_detection_width = 2; + } + + pinctrl->pins = pins; + pinctrl->groups = groups; + pinctrl->npins = num_gpios; + pinctrl->ngroups = num_gpios; + pinctrl->ngpios = num_gpios; + + return msm_pinctrl_probe(pdev, pinctrl); +} + +static const struct acpi_device_id qdf2xxx_acpi_ids[] = { + {"QCOM8002"}, + {}, +}; +MODULE_DEVICE_TABLE(acpi, qdf2xxx_acpi_ids); + +static struct platform_driver qdf2xxx_pinctrl_driver = { + .driver = { + .name = "qdf2xxx-pinctrl", + .acpi_match_table = qdf2xxx_acpi_ids, + }, + .probe = qdf2xxx_pinctrl_probe, + .remove = msm_pinctrl_remove, +}; + +static int __init qdf2xxx_pinctrl_init(void) +{ + return platform_driver_register(&qdf2xxx_pinctrl_driver); +} +arch_initcall(qdf2xxx_pinctrl_init); + +static void __exit qdf2xxx_pinctrl_exit(void) +{ + platform_driver_unregister(&qdf2xxx_pinctrl_driver); +} +module_exit(qdf2xxx_pinctrl_exit); + +MODULE_DESCRIPTION("Qualcomm Technologies QDF2xxx pin control driver"); +MODULE_LICENSE("GPL v2"); diff --git a/drivers/pinctrl/qcom/pinctrl-qdu1000.c b/drivers/pinctrl/qcom/pinctrl-qdu1000.c new file mode 100644 index 0000000000..47bc529ef5 --- /dev/null +++ b/drivers/pinctrl/qcom/pinctrl-qdu1000.c @@ -0,0 +1,1267 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2021, The Linux Foundation. All rights reserved. + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include <linux/module.h> +#include <linux/of.h> +#include <linux/platform_device.h> + +#include "pinctrl-msm.h" + +#define REG_BASE 0x100000 +#define REG_SIZE 0x1000 + +#define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7, f8, f9) \ + { \ + .grp = PINCTRL_PINGROUP("gpio" #id, \ + gpio##id##_pins, \ + ARRAY_SIZE(gpio##id##_pins)), \ + .funcs = (int[]){ \ + msm_mux_gpio, /* gpio mode */ \ + msm_mux_##f1, \ + msm_mux_##f2, \ + msm_mux_##f3, \ + msm_mux_##f4, \ + msm_mux_##f5, \ + msm_mux_##f6, \ + msm_mux_##f7, \ + msm_mux_##f8, \ + msm_mux_##f9 \ + }, \ + .nfuncs = 10, \ + .ctl_reg = REG_BASE + REG_SIZE * id, \ + .io_reg = REG_BASE + 0x4 + REG_SIZE * id, \ + .intr_cfg_reg = REG_BASE + 0x8 + REG_SIZE * id, \ + .intr_status_reg = REG_BASE + 0xc + REG_SIZE * id, \ + .intr_target_reg = REG_BASE + 0x8 + REG_SIZE * id, \ + .mux_bit = 2, \ + .pull_bit = 0, \ + .drv_bit = 6, \ + .oe_bit = 9, \ + .in_bit = 0, \ + .out_bit = 1, \ + .intr_enable_bit = 0, \ + .intr_status_bit = 0, \ + .intr_target_bit = 5, \ + .intr_target_kpss_val = 3, \ + .intr_raw_status_bit = 4, \ + .intr_polarity_bit = 1, \ + .intr_detection_bit = 2, \ + .intr_detection_width = 2, \ + } + +#define SDC_QDSD_PINGROUP(pg_name, ctl, pull, drv) \ + { \ + .grp = PINCTRL_PINGROUP(#pg_name, \ + pg_name##_pins, \ + ARRAY_SIZE(pg_name##_pins)), \ + .ctl_reg = REG_BASE + ctl, \ + .io_reg = 0, \ + .intr_cfg_reg = 0, \ + .intr_status_reg = 0, \ + .intr_target_reg = 0, \ + .mux_bit = -1, \ + .pull_bit = pull, \ + .drv_bit = drv, \ + .oe_bit = -1, \ + .in_bit = -1, \ + .out_bit = -1, \ + .intr_enable_bit = -1, \ + .intr_status_bit = -1, \ + .intr_target_bit = -1, \ + .intr_raw_status_bit = -1, \ + .intr_polarity_bit = -1, \ + .intr_detection_bit = -1, \ + .intr_detection_width = -1, \ + } + +#define UFS_RESET(pg_name, offset) \ + { \ + .grp = PINCTRL_PINGROUP(#pg_name, \ + pg_name##_pins, \ + ARRAY_SIZE(pg_name##_pins)), \ + .ctl_reg = offset, \ + .io_reg = offset + 0x4, \ + .intr_cfg_reg = 0, \ + .intr_status_reg = 0, \ + .intr_target_reg = 0, \ + .mux_bit = -1, \ + .pull_bit = 3, \ + .drv_bit = 0, \ + .oe_bit = -1, \ + .in_bit = -1, \ + .out_bit = 0, \ + .intr_enable_bit = -1, \ + .intr_status_bit = -1, \ + .intr_target_bit = -1, \ + .intr_raw_status_bit = -1, \ + .intr_polarity_bit = -1, \ + .intr_detection_bit = -1, \ + .intr_detection_width = -1, \ + } + +#define QUP_I3C(qup_mode, qup_offset) \ + { \ + .mode = qup_mode, \ + .offset = qup_offset, \ + } + +static const struct pinctrl_pin_desc qdu1000_pins[] = { + PINCTRL_PIN(0, "GPIO_0"), + PINCTRL_PIN(1, "GPIO_1"), + PINCTRL_PIN(2, "GPIO_2"), + PINCTRL_PIN(3, "GPIO_3"), + PINCTRL_PIN(4, "GPIO_4"), + PINCTRL_PIN(5, "GPIO_5"), + PINCTRL_PIN(6, "GPIO_6"), + PINCTRL_PIN(7, "GPIO_7"), + PINCTRL_PIN(8, "GPIO_8"), + PINCTRL_PIN(9, "GPIO_9"), + PINCTRL_PIN(10, "GPIO_10"), + PINCTRL_PIN(11, "GPIO_11"), + PINCTRL_PIN(12, "GPIO_12"), + PINCTRL_PIN(13, "GPIO_13"), + PINCTRL_PIN(14, "GPIO_14"), + PINCTRL_PIN(15, "GPIO_15"), + PINCTRL_PIN(16, "GPIO_16"), + PINCTRL_PIN(17, "GPIO_17"), + PINCTRL_PIN(18, "GPIO_18"), + PINCTRL_PIN(19, "GPIO_19"), + PINCTRL_PIN(20, "GPIO_20"), + PINCTRL_PIN(21, "GPIO_21"), + PINCTRL_PIN(22, "GPIO_22"), + PINCTRL_PIN(23, "GPIO_23"), + PINCTRL_PIN(24, "GPIO_24"), + PINCTRL_PIN(25, "GPIO_25"), + PINCTRL_PIN(26, "GPIO_26"), + PINCTRL_PIN(27, "GPIO_27"), + PINCTRL_PIN(28, "GPIO_28"), + PINCTRL_PIN(29, "GPIO_29"), + PINCTRL_PIN(30, "GPIO_30"), + PINCTRL_PIN(31, "GPIO_31"), + PINCTRL_PIN(32, "GPIO_32"), + PINCTRL_PIN(33, "GPIO_33"), + PINCTRL_PIN(34, "GPIO_34"), + PINCTRL_PIN(35, "GPIO_35"), + PINCTRL_PIN(36, "GPIO_36"), + PINCTRL_PIN(37, "GPIO_37"), + PINCTRL_PIN(38, "GPIO_38"), + PINCTRL_PIN(39, "GPIO_39"), + PINCTRL_PIN(40, "GPIO_40"), + PINCTRL_PIN(41, "GPIO_41"), + PINCTRL_PIN(42, "GPIO_42"), + PINCTRL_PIN(43, "GPIO_43"), + PINCTRL_PIN(44, "GPIO_44"), + PINCTRL_PIN(45, "GPIO_45"), + PINCTRL_PIN(46, "GPIO_46"), + PINCTRL_PIN(47, "GPIO_47"), + PINCTRL_PIN(48, "GPIO_48"), + PINCTRL_PIN(49, "GPIO_49"), + PINCTRL_PIN(50, "GPIO_50"), + PINCTRL_PIN(51, "GPIO_51"), + PINCTRL_PIN(52, "GPIO_52"), + PINCTRL_PIN(53, "GPIO_53"), + PINCTRL_PIN(54, "GPIO_54"), + PINCTRL_PIN(55, "GPIO_55"), + PINCTRL_PIN(56, "GPIO_56"), + PINCTRL_PIN(57, "GPIO_57"), + PINCTRL_PIN(58, "GPIO_58"), + PINCTRL_PIN(59, "GPIO_59"), + PINCTRL_PIN(60, "GPIO_60"), + PINCTRL_PIN(61, "GPIO_61"), + PINCTRL_PIN(62, "GPIO_62"), + PINCTRL_PIN(63, "GPIO_63"), + PINCTRL_PIN(64, "GPIO_64"), + PINCTRL_PIN(65, "GPIO_65"), + PINCTRL_PIN(66, "GPIO_66"), + PINCTRL_PIN(67, "GPIO_67"), + PINCTRL_PIN(68, "GPIO_68"), + PINCTRL_PIN(69, "GPIO_69"), + PINCTRL_PIN(70, "GPIO_70"), + PINCTRL_PIN(71, "GPIO_71"), + PINCTRL_PIN(72, "GPIO_72"), + PINCTRL_PIN(73, "GPIO_73"), + PINCTRL_PIN(74, "GPIO_74"), + PINCTRL_PIN(75, "GPIO_75"), + PINCTRL_PIN(76, "GPIO_76"), + PINCTRL_PIN(77, "GPIO_77"), + PINCTRL_PIN(78, "GPIO_78"), + PINCTRL_PIN(79, "GPIO_79"), + PINCTRL_PIN(80, "GPIO_80"), + PINCTRL_PIN(81, "GPIO_81"), + PINCTRL_PIN(82, "GPIO_82"), + PINCTRL_PIN(83, "GPIO_83"), + PINCTRL_PIN(84, "GPIO_84"), + PINCTRL_PIN(85, "GPIO_85"), + PINCTRL_PIN(86, "GPIO_86"), + PINCTRL_PIN(87, "GPIO_87"), + PINCTRL_PIN(88, "GPIO_88"), + PINCTRL_PIN(89, "GPIO_89"), + PINCTRL_PIN(90, "GPIO_90"), + PINCTRL_PIN(91, "GPIO_91"), + PINCTRL_PIN(92, "GPIO_92"), + PINCTRL_PIN(93, "GPIO_93"), + PINCTRL_PIN(94, "GPIO_94"), + PINCTRL_PIN(95, "GPIO_95"), + PINCTRL_PIN(96, "GPIO_96"), + PINCTRL_PIN(97, "GPIO_97"), + PINCTRL_PIN(98, "GPIO_98"), + PINCTRL_PIN(99, "GPIO_99"), + PINCTRL_PIN(100, "GPIO_100"), + PINCTRL_PIN(101, "GPIO_101"), + PINCTRL_PIN(102, "GPIO_102"), + PINCTRL_PIN(103, "GPIO_103"), + PINCTRL_PIN(104, "GPIO_104"), + PINCTRL_PIN(105, "GPIO_105"), + PINCTRL_PIN(106, "GPIO_106"), + PINCTRL_PIN(107, "GPIO_107"), + PINCTRL_PIN(108, "GPIO_108"), + PINCTRL_PIN(109, "GPIO_109"), + PINCTRL_PIN(110, "GPIO_110"), + PINCTRL_PIN(111, "GPIO_111"), + PINCTRL_PIN(112, "GPIO_112"), + PINCTRL_PIN(113, "GPIO_113"), + PINCTRL_PIN(114, "GPIO_114"), + PINCTRL_PIN(115, "GPIO_115"), + PINCTRL_PIN(116, "GPIO_116"), + PINCTRL_PIN(117, "GPIO_117"), + PINCTRL_PIN(118, "GPIO_118"), + PINCTRL_PIN(119, "GPIO_119"), + PINCTRL_PIN(120, "GPIO_120"), + PINCTRL_PIN(121, "GPIO_121"), + PINCTRL_PIN(122, "GPIO_122"), + PINCTRL_PIN(123, "GPIO_123"), + PINCTRL_PIN(124, "GPIO_124"), + PINCTRL_PIN(125, "GPIO_125"), + PINCTRL_PIN(126, "GPIO_126"), + PINCTRL_PIN(127, "GPIO_127"), + PINCTRL_PIN(128, "GPIO_128"), + PINCTRL_PIN(129, "GPIO_129"), + PINCTRL_PIN(130, "GPIO_130"), + PINCTRL_PIN(131, "GPIO_131"), + PINCTRL_PIN(132, "GPIO_132"), + PINCTRL_PIN(133, "GPIO_133"), + PINCTRL_PIN(134, "GPIO_134"), + PINCTRL_PIN(135, "GPIO_135"), + PINCTRL_PIN(136, "GPIO_136"), + PINCTRL_PIN(137, "GPIO_137"), + PINCTRL_PIN(138, "GPIO_138"), + PINCTRL_PIN(139, "GPIO_139"), + PINCTRL_PIN(140, "GPIO_140"), + PINCTRL_PIN(141, "GPIO_141"), + PINCTRL_PIN(142, "GPIO_142"), + PINCTRL_PIN(143, "GPIO_143"), + PINCTRL_PIN(144, "GPIO_144"), + PINCTRL_PIN(145, "GPIO_145"), + PINCTRL_PIN(146, "GPIO_146"), + PINCTRL_PIN(147, "GPIO_147"), + PINCTRL_PIN(148, "GPIO_148"), + PINCTRL_PIN(149, "GPIO_149"), + PINCTRL_PIN(150, "GPIO_150"), + PINCTRL_PIN(151, "SDC1_RCLK"), + PINCTRL_PIN(152, "SDC1_CLK"), + PINCTRL_PIN(153, "SDC1_CMD"), + PINCTRL_PIN(154, "SDC1_DATA"), +}; + +#define DECLARE_MSM_GPIO_PINS(pin) \ + static const unsigned int gpio##pin##_pins[] = { pin } +DECLARE_MSM_GPIO_PINS(0); +DECLARE_MSM_GPIO_PINS(1); +DECLARE_MSM_GPIO_PINS(2); +DECLARE_MSM_GPIO_PINS(3); +DECLARE_MSM_GPIO_PINS(4); +DECLARE_MSM_GPIO_PINS(5); +DECLARE_MSM_GPIO_PINS(6); +DECLARE_MSM_GPIO_PINS(7); +DECLARE_MSM_GPIO_PINS(8); +DECLARE_MSM_GPIO_PINS(9); +DECLARE_MSM_GPIO_PINS(10); +DECLARE_MSM_GPIO_PINS(11); +DECLARE_MSM_GPIO_PINS(12); +DECLARE_MSM_GPIO_PINS(13); +DECLARE_MSM_GPIO_PINS(14); +DECLARE_MSM_GPIO_PINS(15); +DECLARE_MSM_GPIO_PINS(16); +DECLARE_MSM_GPIO_PINS(17); +DECLARE_MSM_GPIO_PINS(18); +DECLARE_MSM_GPIO_PINS(19); +DECLARE_MSM_GPIO_PINS(20); +DECLARE_MSM_GPIO_PINS(21); +DECLARE_MSM_GPIO_PINS(22); +DECLARE_MSM_GPIO_PINS(23); +DECLARE_MSM_GPIO_PINS(24); +DECLARE_MSM_GPIO_PINS(25); +DECLARE_MSM_GPIO_PINS(26); +DECLARE_MSM_GPIO_PINS(27); +DECLARE_MSM_GPIO_PINS(28); +DECLARE_MSM_GPIO_PINS(29); +DECLARE_MSM_GPIO_PINS(30); +DECLARE_MSM_GPIO_PINS(31); +DECLARE_MSM_GPIO_PINS(32); +DECLARE_MSM_GPIO_PINS(33); +DECLARE_MSM_GPIO_PINS(34); +DECLARE_MSM_GPIO_PINS(35); +DECLARE_MSM_GPIO_PINS(36); +DECLARE_MSM_GPIO_PINS(37); +DECLARE_MSM_GPIO_PINS(38); +DECLARE_MSM_GPIO_PINS(39); +DECLARE_MSM_GPIO_PINS(40); +DECLARE_MSM_GPIO_PINS(41); +DECLARE_MSM_GPIO_PINS(42); +DECLARE_MSM_GPIO_PINS(43); +DECLARE_MSM_GPIO_PINS(44); +DECLARE_MSM_GPIO_PINS(45); +DECLARE_MSM_GPIO_PINS(46); +DECLARE_MSM_GPIO_PINS(47); +DECLARE_MSM_GPIO_PINS(48); +DECLARE_MSM_GPIO_PINS(49); +DECLARE_MSM_GPIO_PINS(50); +DECLARE_MSM_GPIO_PINS(51); +DECLARE_MSM_GPIO_PINS(52); +DECLARE_MSM_GPIO_PINS(53); +DECLARE_MSM_GPIO_PINS(54); +DECLARE_MSM_GPIO_PINS(55); +DECLARE_MSM_GPIO_PINS(56); +DECLARE_MSM_GPIO_PINS(57); +DECLARE_MSM_GPIO_PINS(58); +DECLARE_MSM_GPIO_PINS(59); +DECLARE_MSM_GPIO_PINS(60); +DECLARE_MSM_GPIO_PINS(61); +DECLARE_MSM_GPIO_PINS(62); +DECLARE_MSM_GPIO_PINS(63); +DECLARE_MSM_GPIO_PINS(64); +DECLARE_MSM_GPIO_PINS(65); +DECLARE_MSM_GPIO_PINS(66); +DECLARE_MSM_GPIO_PINS(67); +DECLARE_MSM_GPIO_PINS(68); +DECLARE_MSM_GPIO_PINS(69); +DECLARE_MSM_GPIO_PINS(70); +DECLARE_MSM_GPIO_PINS(71); +DECLARE_MSM_GPIO_PINS(72); +DECLARE_MSM_GPIO_PINS(73); +DECLARE_MSM_GPIO_PINS(74); +DECLARE_MSM_GPIO_PINS(75); +DECLARE_MSM_GPIO_PINS(76); +DECLARE_MSM_GPIO_PINS(77); +DECLARE_MSM_GPIO_PINS(78); +DECLARE_MSM_GPIO_PINS(79); +DECLARE_MSM_GPIO_PINS(80); +DECLARE_MSM_GPIO_PINS(81); +DECLARE_MSM_GPIO_PINS(82); +DECLARE_MSM_GPIO_PINS(83); +DECLARE_MSM_GPIO_PINS(84); +DECLARE_MSM_GPIO_PINS(85); +DECLARE_MSM_GPIO_PINS(86); +DECLARE_MSM_GPIO_PINS(87); +DECLARE_MSM_GPIO_PINS(88); +DECLARE_MSM_GPIO_PINS(89); +DECLARE_MSM_GPIO_PINS(90); +DECLARE_MSM_GPIO_PINS(91); +DECLARE_MSM_GPIO_PINS(92); +DECLARE_MSM_GPIO_PINS(93); +DECLARE_MSM_GPIO_PINS(94); +DECLARE_MSM_GPIO_PINS(95); +DECLARE_MSM_GPIO_PINS(96); +DECLARE_MSM_GPIO_PINS(97); +DECLARE_MSM_GPIO_PINS(98); +DECLARE_MSM_GPIO_PINS(99); +DECLARE_MSM_GPIO_PINS(100); +DECLARE_MSM_GPIO_PINS(101); +DECLARE_MSM_GPIO_PINS(102); +DECLARE_MSM_GPIO_PINS(103); +DECLARE_MSM_GPIO_PINS(104); +DECLARE_MSM_GPIO_PINS(105); +DECLARE_MSM_GPIO_PINS(106); +DECLARE_MSM_GPIO_PINS(107); +DECLARE_MSM_GPIO_PINS(108); +DECLARE_MSM_GPIO_PINS(109); +DECLARE_MSM_GPIO_PINS(110); +DECLARE_MSM_GPIO_PINS(111); +DECLARE_MSM_GPIO_PINS(112); +DECLARE_MSM_GPIO_PINS(113); +DECLARE_MSM_GPIO_PINS(114); +DECLARE_MSM_GPIO_PINS(115); +DECLARE_MSM_GPIO_PINS(116); +DECLARE_MSM_GPIO_PINS(117); +DECLARE_MSM_GPIO_PINS(118); +DECLARE_MSM_GPIO_PINS(119); +DECLARE_MSM_GPIO_PINS(120); +DECLARE_MSM_GPIO_PINS(121); +DECLARE_MSM_GPIO_PINS(122); +DECLARE_MSM_GPIO_PINS(123); +DECLARE_MSM_GPIO_PINS(124); +DECLARE_MSM_GPIO_PINS(125); +DECLARE_MSM_GPIO_PINS(126); +DECLARE_MSM_GPIO_PINS(127); +DECLARE_MSM_GPIO_PINS(128); +DECLARE_MSM_GPIO_PINS(129); +DECLARE_MSM_GPIO_PINS(130); +DECLARE_MSM_GPIO_PINS(131); +DECLARE_MSM_GPIO_PINS(132); +DECLARE_MSM_GPIO_PINS(133); +DECLARE_MSM_GPIO_PINS(134); +DECLARE_MSM_GPIO_PINS(135); +DECLARE_MSM_GPIO_PINS(136); +DECLARE_MSM_GPIO_PINS(137); +DECLARE_MSM_GPIO_PINS(138); +DECLARE_MSM_GPIO_PINS(139); +DECLARE_MSM_GPIO_PINS(140); +DECLARE_MSM_GPIO_PINS(141); +DECLARE_MSM_GPIO_PINS(142); +DECLARE_MSM_GPIO_PINS(143); +DECLARE_MSM_GPIO_PINS(144); +DECLARE_MSM_GPIO_PINS(145); +DECLARE_MSM_GPIO_PINS(146); +DECLARE_MSM_GPIO_PINS(147); +DECLARE_MSM_GPIO_PINS(148); +DECLARE_MSM_GPIO_PINS(149); +DECLARE_MSM_GPIO_PINS(150); + +static const unsigned int sdc1_rclk_pins[] = { 151 }; +static const unsigned int sdc1_clk_pins[] = { 152 }; +static const unsigned int sdc1_cmd_pins[] = { 153 }; +static const unsigned int sdc1_data_pins[] = { 154 }; + +enum qdu1000_functions { + msm_mux_gpio, + msm_mux_cmo_pri, + msm_mux_si5518_int, + msm_mux_atest_char, + msm_mux_atest_usb, + msm_mux_char_exec, + msm_mux_cmu_rng, + msm_mux_dbg_out_clk, + msm_mux_ddr_bist, + msm_mux_ddr_pxi0, + msm_mux_ddr_pxi1, + msm_mux_ddr_pxi2, + msm_mux_ddr_pxi3, + msm_mux_ddr_pxi4, + msm_mux_ddr_pxi5, + msm_mux_ddr_pxi6, + msm_mux_ddr_pxi7, + msm_mux_eth012_int_n, + msm_mux_eth345_int_n, + msm_mux_eth6_int_n, + msm_mux_gcc_gp1, + msm_mux_gcc_gp2, + msm_mux_gcc_gp3, + msm_mux_gps_pps_in, + msm_mux_hardsync_pps_in, + msm_mux_intr_c, + msm_mux_jitter_bist_ref, + msm_mux_pcie_clkreqn, + msm_mux_phase_flag, + msm_mux_pll_bist, + msm_mux_pll_clk, + msm_mux_prng_rosc, + msm_mux_qdss_cti, + msm_mux_qdss_gpio, + msm_mux_qlink0_enable, + msm_mux_qlink0_request, + msm_mux_qlink0_wmss, + msm_mux_qlink1_enable, + msm_mux_qlink1_request, + msm_mux_qlink1_wmss, + msm_mux_qlink2_enable, + msm_mux_qlink2_request, + msm_mux_qlink2_wmss, + msm_mux_qlink3_enable, + msm_mux_qlink3_request, + msm_mux_qlink3_wmss, + msm_mux_qlink4_enable, + msm_mux_qlink4_request, + msm_mux_qlink4_wmss, + msm_mux_qlink5_enable, + msm_mux_qlink5_request, + msm_mux_qlink5_wmss, + msm_mux_qlink6_enable, + msm_mux_qlink6_request, + msm_mux_qlink6_wmss, + msm_mux_qlink7_enable, + msm_mux_qlink7_request, + msm_mux_qlink7_wmss, + msm_mux_qspi_clk, + msm_mux_qspi_cs, + msm_mux_qspi0, + msm_mux_qspi1, + msm_mux_qspi2, + msm_mux_qspi3, + msm_mux_qup00, + msm_mux_qup01, + msm_mux_qup02, + msm_mux_qup03, + msm_mux_qup04, + msm_mux_qup05, + msm_mux_qup06, + msm_mux_qup07, + msm_mux_qup08, + msm_mux_qup10, + msm_mux_qup11, + msm_mux_qup12, + msm_mux_qup13, + msm_mux_qup14, + msm_mux_qup15, + msm_mux_qup16, + msm_mux_qup17, + msm_mux_qup20, + msm_mux_qup21, + msm_mux_qup22, + msm_mux_smb_alert, + msm_mux_smb_clk, + msm_mux_smb_dat, + msm_mux_tb_trig, + msm_mux_tgu_ch0, + msm_mux_tgu_ch1, + msm_mux_tgu_ch2, + msm_mux_tgu_ch3, + msm_mux_tgu_ch4, + msm_mux_tgu_ch5, + msm_mux_tgu_ch6, + msm_mux_tgu_ch7, + msm_mux_tmess_prng0, + msm_mux_tmess_prng1, + msm_mux_tmess_prng2, + msm_mux_tmess_prng3, + msm_mux_tod_pps_in, + msm_mux_tsense_pwm1, + msm_mux_tsense_pwm2, + msm_mux_usb2phy_ac, + msm_mux_usb_con_det, + msm_mux_usb_dfp_en, + msm_mux_usb_phy, + msm_mux_vfr_0, + msm_mux_vfr_1, + msm_mux_vsense_trigger, + msm_mux__, +}; + +static const char * const gpio_groups[] = { + "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7", + "gpio8", "gpio9", "gpio10", "gpio11", "gpio12", "gpio13", "gpio14", + "gpio15", "gpio16", "gpio17", "gpio18", "gpio19", "gpio20", "gpio21", + "gpio22", "gpio23", "gpio24", "gpio25", "gpio26", "gpio27", "gpio28", + "gpio29", "gpio30", "gpio31", "gpio32", "gpio33", "gpio34", "gpio35", + "gpio36", "gpio37", "gpio38", "gpio39", "gpio40", "gpio41", "gpio42", + "gpio43", "gpio44", "gpio45", "gpio46", "gpio47", "gpio48", "gpio49", + "gpio50", "gpio51", "gpio52", "gpio53", "gpio54", "gpio55", "gpio56", + "gpio57", "gpio58", "gpio59", "gpio60", "gpio61", "gpio62", "gpio63", + "gpio64", "gpio65", "gpio66", "gpio67", "gpio68", "gpio69", "gpio70", + "gpio71", "gpio72", "gpio73", "gpio74", "gpio75", "gpio76", "gpio77", + "gpio78", "gpio79", "gpio80", "gpio81", "gpio82", "gpio83", "gpio84", + "gpio85", "gpio86", "gpio87", "gpio88", "gpio89", "gpio90", "gpio91", + "gpio92", "gpio93", "gpio94", "gpio95", "gpio96", "gpio97", "gpio98", + "gpio99", "gpio100", "gpio101", "gpio102", "gpio103", "gpio104", + "gpio105", "gpio106", "gpio107", "gpio108", "gpio109", "gpio110", + "gpio111", "gpio112", "gpio113", "gpio114", "gpio115", "gpio116", + "gpio117", "gpio118", "gpio119", "gpio120", "gpio121", "gpio122", + "gpio123", "gpio124", "gpio125", "gpio126", "gpio127", "gpio128", + "gpio129", "gpio130", "gpio131", "gpio132", "gpio133", "gpio134", + "gpio135", "gpio136", "gpio137", "gpio138", "gpio139", "gpio140", + "gpio141", "gpio142", "gpio143", "gpio144", "gpio145", "gpio146", + "gpio147", "gpio148", "gpio149", "gpio150", +}; +static const char * const cmo_pri_groups[] = { + "gpio103", +}; +static const char * const si5518_int_groups[] = { + "gpio44", +}; +static const char * const atest_char_groups[] = { + "gpio89", "gpio90", "gpio91", "gpio92", "gpio95", +}; +static const char * const atest_usb_groups[] = { + "gpio114", "gpio115", "gpio116", "gpio117", "gpio118", +}; +static const char * const char_exec_groups[] = { + "gpio99", "gpio100", +}; +static const char * const cmu_rng_groups[] = { + "gpio89", "gpio90", "gpio91", "gpio92", +}; +static const char * const dbg_out_clk_groups[] = { + "gpio136", +}; +static const char * const ddr_bist_groups[] = { + "gpio0", "gpio1", "gpio2", "gpio3", +}; +static const char * const ddr_pxi0_groups[] = { + "gpio114", "gpio115", +}; +static const char * const ddr_pxi1_groups[] = { + "gpio116", "gpio117", +}; +static const char * const ddr_pxi2_groups[] = { + "gpio118", "gpio119", +}; +static const char * const ddr_pxi3_groups[] = { + "gpio120", "gpio121", +}; +static const char * const ddr_pxi4_groups[] = { + "gpio122", "gpio123", +}; +static const char * const ddr_pxi5_groups[] = { + "gpio124", "gpio125", +}; +static const char * const ddr_pxi6_groups[] = { + "gpio126", "gpio127", +}; +static const char * const ddr_pxi7_groups[] = { + "gpio128", "gpio129", +}; +static const char * const eth012_int_n_groups[] = { + "gpio86", +}; +static const char * const eth345_int_n_groups[] = { + "gpio87", +}; +static const char * const eth6_int_n_groups[] = { + "gpio88", +}; +static const char * const gcc_gp1_groups[] = { + "gpio86", "gpio134", +}; +static const char * const gcc_gp2_groups[] = { + "gpio87", "gpio135", +}; +static const char * const gcc_gp3_groups[] = { + "gpio88", "gpio136", +}; +static const char * const gps_pps_in_groups[] = { + "gpio49", +}; +static const char * const hardsync_pps_in_groups[] = { + "gpio47", +}; +static const char * const intr_c_groups[] = { + "gpio26", "gpio27", "gpio28", "gpio141", "gpio142", "gpio143", +}; +static const char * const jitter_bist_ref_groups[] = { + "gpio130", +}; +static const char * const pcie_clkreqn_groups[] = { + "gpio98", "gpio99", "gpio100", +}; +static const char * const phase_flag_groups[] = { + "gpio6", "gpio7", "gpio8", "gpio9", "gpio16", "gpio17", "gpio18", + "gpio19", "gpio20", "gpio22", "gpio21", "gpio23", "gpio24", "gpio25", + "gpio26", "gpio27", "gpio28", "gpio29", "gpio30", "gpio31", "gpio32", + "gpio33", "gpio42", "gpio43", "gpio89", "gpio90", "gpio91", "gpio92", + "gpio95", "gpio96", "gpio97", "gpio102", +}; +static const char * const pll_bist_groups[] = { + "gpio20", +}; +static const char * const pll_clk_groups[] = { + "gpio98", +}; +static const char * const prng_rosc_groups[] = { + "gpio18", "gpio19", "gpio20", "gpio21", +}; +static const char * const qdss_cti_groups[] = { + "gpio36", "gpio37", "gpio38", "gpio39", "gpio40", "gpio41", "gpio48", + "gpio49", "gpio86", "gpio87", "gpio93", "gpio94", "gpio130", "gpio131", + "gpio132", "gpio133", "gpio134", "gpio135", "gpio144", "gpio145", +}; +static const char * const qdss_gpio_groups[] = { + "gpio6", "gpio7", "gpio8", "gpio9", "gpio16", "gpio17", "gpio18", + "gpio19", "gpio20", "gpio21", "gpio22", "gpio23", "gpio25", "gpio26", + "gpio27", "gpio28", "gpio24", "gpio29", "gpio30", "gpio31", "gpio32", + "gpio33", "gpio34", "gpio35", "gpio42", "gpio43", "gpio88", "gpio89", + "gpio90", "gpio91", "gpio92", "gpio95", "gpio96", "gpio97", "gpio102", + "gpio103", +}; +static const char * const qlink0_enable_groups[] = { + "gpio67", +}; +static const char * const qlink0_request_groups[] = { + "gpio66", +}; +static const char * const qlink0_wmss_groups[] = { + "gpio82", +}; +static const char * const qlink1_enable_groups[] = { + "gpio69", +}; +static const char * const qlink1_request_groups[] = { + "gpio68", +}; +static const char * const qlink1_wmss_groups[] = { + "gpio83", +}; +static const char * const qlink2_enable_groups[] = { + "gpio71", +}; +static const char * const qlink2_request_groups[] = { + "gpio70", +}; +static const char * const qlink2_wmss_groups[] = { + "gpio138", +}; +static const char * const qlink3_enable_groups[] = { + "gpio73", +}; +static const char * const qlink3_request_groups[] = { + "gpio72", +}; +static const char * const qlink3_wmss_groups[] = { + "gpio139", +}; +static const char * const qlink4_enable_groups[] = { + "gpio75", +}; +static const char * const qlink4_request_groups[] = { + "gpio74", +}; +static const char * const qlink4_wmss_groups[] = { + "gpio84", +}; +static const char * const qlink5_enable_groups[] = { + "gpio77", +}; +static const char * const qlink5_request_groups[] = { + "gpio76", +}; +static const char * const qlink5_wmss_groups[] = { + "gpio85", +}; +static const char * const qlink6_enable_groups[] = { + "gpio79", +}; +static const char * const qlink6_request_groups[] = { + "gpio78", +}; +static const char * const qlink6_wmss_groups[] = { + "gpio56", +}; +static const char * const qlink7_enable_groups[] = { + "gpio81", +}; +static const char * const qlink7_request_groups[] = { + "gpio80", +}; +static const char * const qlink7_wmss_groups[] = { + "gpio57", +}; +static const char * const qspi0_groups[] = { + "gpio114", +}; +static const char * const qspi1_groups[] = { + "gpio115", +}; +static const char * const qspi2_groups[] = { + "gpio116", +}; +static const char * const qspi3_groups[] = { + "gpio117", +}; +static const char * const qspi_clk_groups[] = { + "gpio126", +}; +static const char * const qspi_cs_groups[] = { + "gpio125", +}; +static const char * const qup00_groups[] = { + "gpio6", "gpio7", "gpio8", "gpio9", +}; +static const char * const qup01_groups[] = { + "gpio10", "gpio11", "gpio12", "gpio13", +}; +static const char * const qup02_groups[] = { + "gpio10", "gpio11", "gpio12", "gpio13", +}; +static const char * const qup03_groups[] = { + "gpio14", "gpio15", "gpio16", "gpio17", +}; +static const char * const qup04_groups[] = { + "gpio14", "gpio15", "gpio16", "gpio17", +}; +static const char * const qup05_groups[] = { + "gpio130", "gpio131", "gpio132", "gpio133", +}; +static const char * const qup06_groups[] = { + "gpio130", "gpio131", "gpio132", "gpio133", +}; +static const char * const qup07_groups[] = { + "gpio134", "gpio135", +}; +static const char * const qup08_groups[] = { + "gpio134", "gpio135", +}; +static const char * const qup10_groups[] = { + "gpio18", "gpio19", "gpio20", "gpio21", +}; +static const char * const qup11_groups[] = { + "gpio22", "gpio23", "gpio24", "gpio25", +}; +static const char * const qup12_groups[] = { + "gpio22", "gpio23", "gpio24", "gpio25", +}; +static const char * const qup13_groups[] = { + "gpio26", "gpio27", "gpio28", "gpio29", +}; +static const char * const qup14_groups[] = { + "gpio26", "gpio27", "gpio28", "gpio29", +}; +static const char * const qup15_groups[] = { + "gpio30", "gpio31", "gpio32", "gpio33", +}; +static const char * const qup16_groups[] = { + "gpio29", "gpio34", "gpio35", "gpio36", "gpio37", "gpio38", "gpio39", +}; +static const char * const qup17_groups[] = { + "gpio12", "gpio13", "gpio14", "gpio30", "gpio31", "gpio40", "gpio41", +}; +static const char * const qup20_groups[] = { + "gpio0", "gpio1", "gpio2", "gpio3", +}; +static const char * const qup21_groups[] = { + "gpio0", "gpio1", "gpio2", "gpio3", +}; +static const char * const qup22_groups[] = { + "gpio4", "gpio5", "gpio128", "gpio129", +}; +static const char * const smb_alert_groups[] = { + "gpio88", "gpio101", +}; +static const char * const smb_clk_groups[] = { + "gpio133", +}; +static const char * const smb_dat_groups[] = { + "gpio132", +}; +static const char * const tb_trig_groups[] = { + "gpio114", +}; +static const char * const tgu_ch0_groups[] = { + "gpio6", +}; +static const char * const tgu_ch1_groups[] = { + "gpio7", +}; +static const char * const tgu_ch2_groups[] = { + "gpio8", +}; +static const char * const tgu_ch3_groups[] = { + "gpio9", +}; +static const char * const tgu_ch4_groups[] = { + "gpio44", +}; +static const char * const tgu_ch5_groups[] = { + "gpio45", +}; +static const char * const tgu_ch6_groups[] = { + "gpio46", +}; +static const char * const tgu_ch7_groups[] = { + "gpio47", +}; +static const char * const tmess_prng0_groups[] = { + "gpio33", +}; +static const char * const tmess_prng1_groups[] = { + "gpio32", +}; +static const char * const tmess_prng2_groups[] = { + "gpio31", +}; +static const char * const tmess_prng3_groups[] = { + "gpio30", +}; +static const char * const tod_pps_in_groups[] = { + "gpio48", +}; +static const char * const tsense_pwm1_groups[] = { + "gpio2", +}; +static const char * const tsense_pwm2_groups[] = { + "gpio3", +}; +static const char * const usb2phy_ac_groups[] = { + "gpio90", +}; +static const char * const usb_con_det_groups[] = { + "gpio42", +}; +static const char * const usb_dfp_en_groups[] = { + "gpio43", +}; +static const char * const usb_phy_groups[] = { + "gpio91", +}; +static const char * const vfr_0_groups[] = { + "gpio93", +}; +static const char * const vfr_1_groups[] = { + "gpio94", +}; +static const char * const vsense_trigger_groups[] = { + "gpio135", +}; + +static const struct pinfunction qdu1000_functions[] = { + MSM_PIN_FUNCTION(gpio), + MSM_PIN_FUNCTION(cmo_pri), + MSM_PIN_FUNCTION(si5518_int), + MSM_PIN_FUNCTION(atest_char), + MSM_PIN_FUNCTION(atest_usb), + MSM_PIN_FUNCTION(char_exec), + MSM_PIN_FUNCTION(cmu_rng), + MSM_PIN_FUNCTION(dbg_out_clk), + MSM_PIN_FUNCTION(ddr_bist), + MSM_PIN_FUNCTION(ddr_pxi0), + MSM_PIN_FUNCTION(ddr_pxi1), + MSM_PIN_FUNCTION(ddr_pxi2), + MSM_PIN_FUNCTION(ddr_pxi3), + MSM_PIN_FUNCTION(ddr_pxi4), + MSM_PIN_FUNCTION(ddr_pxi5), + MSM_PIN_FUNCTION(ddr_pxi6), + MSM_PIN_FUNCTION(ddr_pxi7), + MSM_PIN_FUNCTION(eth012_int_n), + MSM_PIN_FUNCTION(eth345_int_n), + MSM_PIN_FUNCTION(eth6_int_n), + MSM_PIN_FUNCTION(gcc_gp1), + MSM_PIN_FUNCTION(gcc_gp2), + MSM_PIN_FUNCTION(gcc_gp3), + MSM_PIN_FUNCTION(gps_pps_in), + MSM_PIN_FUNCTION(hardsync_pps_in), + MSM_PIN_FUNCTION(intr_c), + MSM_PIN_FUNCTION(jitter_bist_ref), + MSM_PIN_FUNCTION(pcie_clkreqn), + MSM_PIN_FUNCTION(phase_flag), + MSM_PIN_FUNCTION(pll_bist), + MSM_PIN_FUNCTION(pll_clk), + MSM_PIN_FUNCTION(prng_rosc), + MSM_PIN_FUNCTION(qdss_cti), + MSM_PIN_FUNCTION(qdss_gpio), + MSM_PIN_FUNCTION(qlink0_enable), + MSM_PIN_FUNCTION(qlink0_request), + MSM_PIN_FUNCTION(qlink0_wmss), + MSM_PIN_FUNCTION(qlink1_enable), + MSM_PIN_FUNCTION(qlink1_request), + MSM_PIN_FUNCTION(qlink1_wmss), + MSM_PIN_FUNCTION(qlink2_enable), + MSM_PIN_FUNCTION(qlink2_request), + MSM_PIN_FUNCTION(qlink2_wmss), + MSM_PIN_FUNCTION(qlink3_enable), + MSM_PIN_FUNCTION(qlink3_request), + MSM_PIN_FUNCTION(qlink3_wmss), + MSM_PIN_FUNCTION(qlink4_enable), + MSM_PIN_FUNCTION(qlink4_request), + MSM_PIN_FUNCTION(qlink4_wmss), + MSM_PIN_FUNCTION(qlink5_enable), + MSM_PIN_FUNCTION(qlink5_request), + MSM_PIN_FUNCTION(qlink5_wmss), + MSM_PIN_FUNCTION(qlink6_enable), + MSM_PIN_FUNCTION(qlink6_request), + MSM_PIN_FUNCTION(qlink6_wmss), + MSM_PIN_FUNCTION(qlink7_enable), + MSM_PIN_FUNCTION(qlink7_request), + MSM_PIN_FUNCTION(qlink7_wmss), + MSM_PIN_FUNCTION(qspi0), + MSM_PIN_FUNCTION(qspi1), + MSM_PIN_FUNCTION(qspi2), + MSM_PIN_FUNCTION(qspi3), + MSM_PIN_FUNCTION(qspi_clk), + MSM_PIN_FUNCTION(qspi_cs), + MSM_PIN_FUNCTION(qup00), + MSM_PIN_FUNCTION(qup01), + MSM_PIN_FUNCTION(qup02), + MSM_PIN_FUNCTION(qup03), + MSM_PIN_FUNCTION(qup04), + MSM_PIN_FUNCTION(qup05), + MSM_PIN_FUNCTION(qup06), + MSM_PIN_FUNCTION(qup07), + MSM_PIN_FUNCTION(qup08), + MSM_PIN_FUNCTION(qup10), + MSM_PIN_FUNCTION(qup11), + MSM_PIN_FUNCTION(qup12), + MSM_PIN_FUNCTION(qup13), + MSM_PIN_FUNCTION(qup14), + MSM_PIN_FUNCTION(qup15), + MSM_PIN_FUNCTION(qup16), + MSM_PIN_FUNCTION(qup17), + MSM_PIN_FUNCTION(qup20), + MSM_PIN_FUNCTION(qup21), + MSM_PIN_FUNCTION(qup22), + MSM_PIN_FUNCTION(smb_alert), + MSM_PIN_FUNCTION(smb_clk), + MSM_PIN_FUNCTION(smb_dat), + MSM_PIN_FUNCTION(tb_trig), + MSM_PIN_FUNCTION(tgu_ch0), + MSM_PIN_FUNCTION(tgu_ch1), + MSM_PIN_FUNCTION(tgu_ch2), + MSM_PIN_FUNCTION(tgu_ch3), + MSM_PIN_FUNCTION(tgu_ch4), + MSM_PIN_FUNCTION(tgu_ch5), + MSM_PIN_FUNCTION(tgu_ch6), + MSM_PIN_FUNCTION(tgu_ch7), + MSM_PIN_FUNCTION(tmess_prng0), + MSM_PIN_FUNCTION(tmess_prng1), + MSM_PIN_FUNCTION(tmess_prng2), + MSM_PIN_FUNCTION(tmess_prng3), + MSM_PIN_FUNCTION(tod_pps_in), + MSM_PIN_FUNCTION(tsense_pwm1), + MSM_PIN_FUNCTION(tsense_pwm2), + MSM_PIN_FUNCTION(usb2phy_ac), + MSM_PIN_FUNCTION(usb_con_det), + MSM_PIN_FUNCTION(usb_dfp_en), + MSM_PIN_FUNCTION(usb_phy), + MSM_PIN_FUNCTION(vfr_0), + MSM_PIN_FUNCTION(vfr_1), + MSM_PIN_FUNCTION(vsense_trigger), +}; + +/* + * Every pin is maintained as a single group, and missing or non-existing pin + * would be maintained as dummy group to synchronize pin group index with + * pin descriptor registered with pinctrl core. + * Clients would not be able to request these dummy pin groups. + */ +static const struct msm_pingroup qdu1000_groups[] = { + [0] = PINGROUP(0, qup20, qup21, ddr_bist, _, _, _, _, _, _), + [1] = PINGROUP(1, qup20, qup21, ddr_bist, _, _, _, _, _, _), + [2] = PINGROUP(2, qup21, qup20, ddr_bist, _, + tsense_pwm1, _, _, _, _), + [3] = PINGROUP(3, qup21, qup20, ddr_bist, _, + tsense_pwm2, _, _, _, _), + [4] = PINGROUP(4, qup22, _, _, _, _, _, _, _, _), + [5] = PINGROUP(5, qup22, _, _, _, _, _, _, _, _), + [6] = PINGROUP(6, qup00, tgu_ch0, phase_flag, _, + qdss_gpio, _, _, _, _), + [7] = PINGROUP(7, qup00, tgu_ch1, phase_flag, _, + qdss_gpio, _, _, _, _), + [8] = PINGROUP(8, qup00, tgu_ch2, phase_flag, _, + qdss_gpio, _, _, _, _), + [9] = PINGROUP(9, qup00, tgu_ch3, phase_flag, _, + qdss_gpio, _, _, _, _), + [10] = PINGROUP(10, qup01, qup02, _, _, _, _, _, _, _), + [11] = PINGROUP(11, qup01, qup02, _, _, _, _, _, _, _), + [12] = PINGROUP(12, qup02, qup01, qup17, _, _, _, _, _, _), + [13] = PINGROUP(13, qup02, qup01, qup17, _, _, _, _, _, _), + [14] = PINGROUP(14, qup03, qup04, qup17, _, _, _, _, _, _), + [15] = PINGROUP(15, qup03, qup04, _, _, _, _, _, _, _), + [16] = PINGROUP(16, qup04, qup03, phase_flag, _, + qdss_gpio, _, _, _, _), + [17] = PINGROUP(17, qup04, qup03, phase_flag, _, + qdss_gpio, _, _, _, _), + [18] = PINGROUP(18, qup10, prng_rosc, phase_flag, + _, qdss_gpio, _, _, _, _), + [19] = PINGROUP(19, qup10, prng_rosc, phase_flag, + _, qdss_gpio, _, _, _, _), + [20] = PINGROUP(20, qup10, prng_rosc, pll_bist, + phase_flag, _, qdss_gpio, _, _, _), + [21] = PINGROUP(21, qup10, prng_rosc, phase_flag, + _, qdss_gpio, _, _, _, _), + [22] = PINGROUP(22, qup11, qup12, phase_flag, _, + qdss_gpio, _, _, _, _), + [23] = PINGROUP(23, qup11, qup12, phase_flag, _, + qdss_gpio, _, _, _, _), + [24] = PINGROUP(24, qup12, qup11, phase_flag, _, + qdss_gpio, _, _, _, _), + [25] = PINGROUP(25, qup12, qup11, phase_flag, _, + qdss_gpio, _, _, _, _), + [26] = PINGROUP(26, qup13, qup14, intr_c, + phase_flag, _, qdss_gpio, _, _, _), + [27] = PINGROUP(27, qup13, qup14, intr_c, + phase_flag, _, qdss_gpio, _, _, _), + [28] = PINGROUP(28, qup14, qup13, intr_c, + phase_flag, _, qdss_gpio, _, _, _), + [29] = PINGROUP(29, qup14, qup13, qup16, + phase_flag, _, qdss_gpio, _, _, _), + [30] = PINGROUP(30, qup17, qup15, tmess_prng3, + phase_flag, _, qdss_gpio, _, _, _), + [31] = PINGROUP(31, qup17, qup15, tmess_prng2, + phase_flag, _, qdss_gpio, _, _, _), + [32] = PINGROUP(32, qup15, tmess_prng1, phase_flag, + _, qdss_gpio, _, _, _, _), + [33] = PINGROUP(33, qup15, tmess_prng0, phase_flag, + _, qdss_gpio, _, _, _, _), + [34] = PINGROUP(34, qup16, qdss_gpio, _, _, _, _, _, _, _), + [35] = PINGROUP(35, qup16, qdss_gpio, _, _, _, _, _, _, _), + [36] = PINGROUP(36, qup16, qdss_cti, _, _, _, _, _, _, _), + [37] = PINGROUP(37, qup16, qdss_cti, _, _, _, _, _, _, _), + [38] = PINGROUP(38, qup16, qdss_cti, _, _, _, _, _, _, _), + [39] = PINGROUP(39, qup16, qdss_cti, _, _, _, _, _, _, _), + [40] = PINGROUP(40, qup17, qdss_cti, _, _, _, _, _, _, _), + [41] = PINGROUP(41, qup17, qdss_cti, _, _, _, _, _, _, _), + [42] = PINGROUP(42, usb_con_det, phase_flag, _, + qdss_gpio, _, _, _, _, _), + [43] = PINGROUP(43, usb_dfp_en, phase_flag, _, + qdss_gpio, _, _, _, _, _), + [44] = PINGROUP(44, si5518_int, tgu_ch4, _, _, _, _, _, _, _), + [45] = PINGROUP(45, tgu_ch5, _, _, _, _, _, _, _, _), + [46] = PINGROUP(46, tgu_ch6, _, _, _, _, _, _, _, _), + [47] = PINGROUP(47, hardsync_pps_in, tgu_ch7, _, _, _, _, _, _, _), + [48] = PINGROUP(48, tod_pps_in, qdss_cti, _, _, _, _, _, _, _), + [49] = PINGROUP(49, gps_pps_in, qdss_cti, _, _, _, _, _, _, _), + [50] = PINGROUP(50, _, _, _, _, _, _, _, _, _), + [51] = PINGROUP(51, _, _, _, _, _, _, _, _, _), + [52] = PINGROUP(52, _, _, _, _, _, _, _, _, _), + [53] = PINGROUP(53, _, _, _, _, _, _, _, _, _), + [54] = PINGROUP(54, _, _, _, _, _, _, _, _, _), + [55] = PINGROUP(55, _, _, _, _, _, _, _, _, _), + [56] = PINGROUP(56, _, qlink6_wmss, _, _, _, _, _, _, _), + [57] = PINGROUP(57, _, qlink7_wmss, _, _, _, _, _, _, _), + [58] = PINGROUP(58, _, _, _, _, _, _, _, _, _), + [59] = PINGROUP(59, _, _, _, _, _, _, _, _, _), + [60] = PINGROUP(60, _, _, _, _, _, _, _, _, _), + [61] = PINGROUP(61, _, _, _, _, _, _, _, _, _), + [62] = PINGROUP(62, _, _, _, _, _, _, _, _, _), + [63] = PINGROUP(63, _, _, _, _, _, _, _, _, _), + [64] = PINGROUP(64, _, _, _, _, _, _, _, _, _), + [65] = PINGROUP(65, _, _, _, _, _, _, _, _, _), + [66] = PINGROUP(66, qlink0_request, _, _, _, _, _, _, _, _), + [67] = PINGROUP(67, qlink0_enable, _, _, _, _, _, _, _, _), + [68] = PINGROUP(68, qlink1_request, _, _, _, _, _, _, _, _), + [69] = PINGROUP(69, qlink1_enable, _, _, _, _, _, _, _, _), + [70] = PINGROUP(70, qlink2_request, _, _, _, _, _, _, _, _), + [71] = PINGROUP(71, qlink2_enable, _, _, _, _, _, _, _, _), + [72] = PINGROUP(72, qlink3_request, _, _, _, _, _, _, _, _), + [73] = PINGROUP(73, qlink3_enable, _, _, _, _, _, _, _, _), + [74] = PINGROUP(74, qlink4_request, _, _, _, _, _, _, _, _), + [75] = PINGROUP(75, qlink4_enable, _, _, _, _, _, _, _, _), + [76] = PINGROUP(76, qlink5_request, _, _, _, _, _, _, _, _), + [77] = PINGROUP(77, qlink5_enable, _, _, _, _, _, _, _, _), + [78] = PINGROUP(78, qlink6_request, _, _, _, _, _, _, _, _), + [79] = PINGROUP(79, qlink6_enable, _, _, _, _, _, _, _, _), + [80] = PINGROUP(80, qlink7_request, _, _, _, _, _, _, _, _), + [81] = PINGROUP(81, qlink7_enable, _, _, _, _, _, _, _, _), + [82] = PINGROUP(82, qlink0_wmss, _, _, _, _, _, _, _, _), + [83] = PINGROUP(83, qlink1_wmss, _, _, _, _, _, _, _, _), + [84] = PINGROUP(84, qlink4_wmss, _, _, _, _, _, _, _, _), + [85] = PINGROUP(85, qlink5_wmss, _, _, _, _, _, _, _, _), + [86] = PINGROUP(86, eth012_int_n, gcc_gp1, _, qdss_cti, _, _, _, _, _), + [87] = PINGROUP(87, eth345_int_n, gcc_gp2, _, qdss_cti, _, _, _, _, _), + [88] = PINGROUP(88, eth6_int_n, smb_alert, gcc_gp3, _, + qdss_gpio, _, _, _, _), + [89] = PINGROUP(89, phase_flag, cmu_rng, _, + qdss_gpio, atest_char, _, _, _, _), + [90] = PINGROUP(90, usb2phy_ac, phase_flag, + cmu_rng, _, qdss_gpio, + atest_char, _, _, _), + [91] = PINGROUP(91, usb_phy, phase_flag, cmu_rng, + _, qdss_gpio, atest_char, _, _, _), + [92] = PINGROUP(92, phase_flag, cmu_rng, _, + qdss_gpio, atest_char, _, _, _, _), + [93] = PINGROUP(93, vfr_0, qdss_cti, _, _, _, _, _, _, _), + [94] = PINGROUP(94, vfr_1, qdss_cti, _, _, _, _, _, _, _), + [95] = PINGROUP(95, phase_flag, _, qdss_gpio, + atest_char, _, _, _, _, _), + [96] = PINGROUP(96, phase_flag, _, qdss_gpio, _, _, _, _, _, _), + [97] = PINGROUP(97, phase_flag, _, qdss_gpio, _, _, _, _, _, _), + [98] = PINGROUP(98, pll_clk, _, _, _, _, _, _, _, _), + [99] = PINGROUP(99, pcie_clkreqn, char_exec, _, _, _, _, _, _, _), + [100] = PINGROUP(100, char_exec, _, _, _, _, _, _, _, _), + [101] = PINGROUP(101, smb_alert, _, _, _, _, _, _, _, _), + [102] = PINGROUP(102, phase_flag, _, qdss_gpio, _, _, _, _, _, _), + [103] = PINGROUP(103, cmo_pri, qdss_gpio, _, _, _, _, _, _, _), + [104] = PINGROUP(104, _, _, _, _, _, _, _, _, _), + [105] = PINGROUP(105, _, _, _, _, _, _, _, _, _), + [106] = PINGROUP(106, _, _, _, _, _, _, _, _, _), + [107] = PINGROUP(107, _, _, _, _, _, _, _, _, _), + [108] = PINGROUP(108, _, _, _, _, _, _, _, _, _), + [109] = PINGROUP(109, _, _, _, _, _, _, _, _, _), + [110] = PINGROUP(110, _, _, _, _, _, _, _, _, _), + [111] = PINGROUP(111, _, _, _, _, _, _, _, _, _), + [112] = PINGROUP(112, _, _, _, _, _, _, _, _, _), + [113] = PINGROUP(113, _, _, _, _, _, _, _, _, _), + [114] = PINGROUP(114, qspi0, tb_trig, _, + atest_usb, ddr_pxi0, _, _, _, _), + [115] = PINGROUP(115, qspi1, _, atest_usb, + ddr_pxi0, _, _, _, _, _), + [116] = PINGROUP(116, qspi2, _, atest_usb, + ddr_pxi1, _, _, _, _, _), + [117] = PINGROUP(117, qspi3, _, atest_usb, + ddr_pxi1, _, _, _, _, _), + [118] = PINGROUP(118, _, atest_usb, ddr_pxi2, _, _, _, _, _, _), + [119] = PINGROUP(119, _, _, ddr_pxi2, _, _, _, _, _, _), + [120] = PINGROUP(120, _, _, ddr_pxi3, _, _, _, _, _, _), + [121] = PINGROUP(121, _, ddr_pxi3, _, _, _, _, _, _, _), + [122] = PINGROUP(122, _, ddr_pxi4, _, _, _, _, _, _, _), + [123] = PINGROUP(123, _, ddr_pxi4, _, _, _, _, _, _, _), + [124] = PINGROUP(124, _, ddr_pxi5, _, _, _, _, _, _, _), + [125] = PINGROUP(125, qspi_cs, _, ddr_pxi5, _, _, _, _, _, _), + [126] = PINGROUP(126, qspi_clk, _, ddr_pxi6, _, _, _, _, _, _), + [127] = PINGROUP(127, _, ddr_pxi6, _, _, _, _, _, _, _), + [128] = PINGROUP(128, qup22, _, ddr_pxi7, _, _, _, _, _, _), + [129] = PINGROUP(129, qup22, ddr_pxi7, _, _, _, _, _, _, _), + [130] = PINGROUP(130, qup05, qup06, jitter_bist_ref, + qdss_cti, _, _, _, _, _), + [131] = PINGROUP(131, qup05, qup06, qdss_cti, _, _, _, _, _, _), + [132] = PINGROUP(132, qup06, qup05, smb_dat, + qdss_cti, _, _, _, _, _), + [133] = PINGROUP(133, qup06, qup05, smb_clk, + qdss_cti, _, _, _, _, _), + [134] = PINGROUP(134, qup08, qup07, gcc_gp1, _, + qdss_cti, _, _, _, _), + [135] = PINGROUP(135, qup08, qup07, gcc_gp2, _, + qdss_cti, vsense_trigger, _, _, _), + [136] = PINGROUP(136, gcc_gp3, dbg_out_clk, _, _, _, _, _, _, _), + [137] = PINGROUP(137, _, _, _, _, _, _, _, _, _), + [138] = PINGROUP(138, qlink2_wmss, _, _, _, _, _, _, _, _), + [139] = PINGROUP(139, qlink3_wmss, _, _, _, _, _, _, _, _), + [140] = PINGROUP(140, _, _, _, _, _, _, _, _, _), + [141] = PINGROUP(141, intr_c, _, _, _, _, _, _, _, _), + [142] = PINGROUP(142, intr_c, _, _, _, _, _, _, _, _), + [143] = PINGROUP(143, intr_c, _, _, _, _, _, _, _, _), + [144] = PINGROUP(144, qdss_cti, _, _, _, _, _, _, _, _), + [145] = PINGROUP(145, qdss_cti, _, _, _, _, _, _, _, _), + [146] = PINGROUP(146, _, _, _, _, _, _, _, _, _), + [147] = PINGROUP(147, _, _, _, _, _, _, _, _, _), + [148] = PINGROUP(148, _, _, _, _, _, _, _, _, _), + [149] = PINGROUP(149, _, _, _, _, _, _, _, _, _), + [150] = PINGROUP(150, _, _, _, _, _, _, _, _, _), + [151] = SDC_QDSD_PINGROUP(sdc1_rclk, 0x9e000, 0, 0), + [152] = SDC_QDSD_PINGROUP(sdc1_clk, 0x9d000, 13, 6), + [153] = SDC_QDSD_PINGROUP(sdc1_cmd, 0x9d000, 11, 3), + [154] = SDC_QDSD_PINGROUP(sdc1_data, 0x9d000, 9, 0), +}; +static const struct msm_pinctrl_soc_data qdu1000_tlmm = { + .pins = qdu1000_pins, + .npins = ARRAY_SIZE(qdu1000_pins), + .functions = qdu1000_functions, + .nfunctions = ARRAY_SIZE(qdu1000_functions), + .groups = qdu1000_groups, + .ngroups = ARRAY_SIZE(qdu1000_groups), + .ngpios = 151, +}; + +static int qdu1000_tlmm_probe(struct platform_device *pdev) +{ + return msm_pinctrl_probe(pdev, &qdu1000_tlmm); +} + +static const struct of_device_id qdu1000_tlmm_of_match[] = { + { .compatible = "qcom,qdu1000-tlmm", }, + { }, +}; +MODULE_DEVICE_TABLE(of, qdu1000_tlmm_of_match); + +static struct platform_driver qdu1000_tlmm_driver = { + .driver = { + .name = "qdu1000-tlmm", + .of_match_table = qdu1000_tlmm_of_match, + }, + .probe = qdu1000_tlmm_probe, + .remove = msm_pinctrl_remove, +}; + +static int __init qdu1000_tlmm_init(void) +{ + return platform_driver_register(&qdu1000_tlmm_driver); +} +arch_initcall(qdu1000_tlmm_init); + +static void __exit qdu1000_tlmm_exit(void) +{ + platform_driver_unregister(&qdu1000_tlmm_driver); +} +module_exit(qdu1000_tlmm_exit); + +MODULE_DESCRIPTION("QTI QDU1000 TLMM driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/pinctrl/qcom/pinctrl-sa8775p.c b/drivers/pinctrl/qcom/pinctrl-sa8775p.c new file mode 100644 index 0000000000..8fdea25d8d --- /dev/null +++ b/drivers/pinctrl/qcom/pinctrl-sa8775p.c @@ -0,0 +1,1549 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2023, Linaro Limited + */ + +#include <linux/module.h> +#include <linux/of.h> +#include <linux/platform_device.h> + +#include "pinctrl-msm.h" + +#define REG_BASE 0x100000 +#define REG_SIZE 0x1000 +#define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7, f8, f9)\ + { \ + .grp = PINCTRL_PINGROUP("gpio" #id, \ + gpio##id##_pins, \ + ARRAY_SIZE(gpio##id##_pins)), \ + .funcs = (int[]){ \ + msm_mux_gpio, /* gpio mode */ \ + msm_mux_##f1, \ + msm_mux_##f2, \ + msm_mux_##f3, \ + msm_mux_##f4, \ + msm_mux_##f5, \ + msm_mux_##f6, \ + msm_mux_##f7, \ + msm_mux_##f8, \ + msm_mux_##f9 \ + }, \ + .nfuncs = 10, \ + .ctl_reg = REG_BASE + REG_SIZE * id, \ + .io_reg = REG_BASE + 0x4 + REG_SIZE * id, \ + .intr_cfg_reg = REG_BASE + 0x8 + REG_SIZE * id, \ + .intr_status_reg = REG_BASE + 0xc + REG_SIZE * id, \ + .intr_target_reg = REG_BASE + 0x8 + REG_SIZE * id, \ + .mux_bit = 2, \ + .pull_bit = 0, \ + .drv_bit = 6, \ + .egpio_enable = 12, \ + .egpio_present = 11, \ + .oe_bit = 9, \ + .in_bit = 0, \ + .out_bit = 1, \ + .intr_enable_bit = 0, \ + .intr_status_bit = 0, \ + .intr_target_bit = 5, \ + .intr_target_width = 4, \ + .intr_target_kpss_val = 3, \ + .intr_raw_status_bit = 4, \ + .intr_polarity_bit = 1, \ + .intr_detection_bit = 2, \ + .intr_detection_width = 2, \ + } + +#define SDC_QDSD_PINGROUP(pg_name, ctl, pull, drv) \ + { \ + .grp = PINCTRL_PINGROUP(#pg_name, \ + pg_name##_pins, \ + ARRAY_SIZE(pg_name##_pins)), \ + .ctl_reg = ctl, \ + .io_reg = 0, \ + .intr_cfg_reg = 0, \ + .intr_status_reg = 0, \ + .intr_target_reg = 0, \ + .mux_bit = -1, \ + .pull_bit = pull, \ + .drv_bit = drv, \ + .oe_bit = -1, \ + .in_bit = -1, \ + .out_bit = -1, \ + .intr_enable_bit = -1, \ + .intr_status_bit = -1, \ + .intr_target_bit = -1, \ + .intr_raw_status_bit = -1, \ + .intr_polarity_bit = -1, \ + .intr_detection_bit = -1, \ + .intr_detection_width = -1, \ + } + +#define UFS_RESET(pg_name, offset) \ + { \ + .grp = PINCTRL_PINGROUP(#pg_name, \ + pg_name##_pins, \ + ARRAY_SIZE(pg_name##_pins)), \ + .ctl_reg = offset, \ + .io_reg = offset + 0x4, \ + .intr_cfg_reg = 0, \ + .intr_status_reg = 0, \ + .intr_target_reg = 0, \ + .mux_bit = -1, \ + .pull_bit = 3, \ + .drv_bit = 0, \ + .oe_bit = -1, \ + .in_bit = -1, \ + .out_bit = 0, \ + .intr_enable_bit = -1, \ + .intr_status_bit = -1, \ + .intr_target_bit = -1, \ + .intr_raw_status_bit = -1, \ + .intr_polarity_bit = -1, \ + .intr_detection_bit = -1, \ + .intr_detection_width = -1, \ + } + +#define QUP_I3C(qup_mode, qup_offset) \ + { \ + .mode = qup_mode, \ + .offset = qup_offset, \ + } + +#define QUP_I3C_6_MODE_OFFSET 0xAF000 +#define QUP_I3C_7_MODE_OFFSET 0xB0000 +#define QUP_I3C_13_MODE_OFFSET 0xB1000 +#define QUP_I3C_14_MODE_OFFSET 0xB2000 + +static const struct pinctrl_pin_desc sa8775p_pins[] = { + PINCTRL_PIN(0, "GPIO_0"), + PINCTRL_PIN(1, "GPIO_1"), + PINCTRL_PIN(2, "GPIO_2"), + PINCTRL_PIN(3, "GPIO_3"), + PINCTRL_PIN(4, "GPIO_4"), + PINCTRL_PIN(5, "GPIO_5"), + PINCTRL_PIN(6, "GPIO_6"), + PINCTRL_PIN(7, "GPIO_7"), + PINCTRL_PIN(8, "GPIO_8"), + PINCTRL_PIN(9, "GPIO_9"), + PINCTRL_PIN(10, "GPIO_10"), + PINCTRL_PIN(11, "GPIO_11"), + PINCTRL_PIN(12, "GPIO_12"), + PINCTRL_PIN(13, "GPIO_13"), + PINCTRL_PIN(14, "GPIO_14"), + PINCTRL_PIN(15, "GPIO_15"), + PINCTRL_PIN(16, "GPIO_16"), + PINCTRL_PIN(17, "GPIO_17"), + PINCTRL_PIN(18, "GPIO_18"), + PINCTRL_PIN(19, "GPIO_19"), + PINCTRL_PIN(20, "GPIO_20"), + PINCTRL_PIN(21, "GPIO_21"), + PINCTRL_PIN(22, "GPIO_22"), + PINCTRL_PIN(23, "GPIO_23"), + PINCTRL_PIN(24, "GPIO_24"), + PINCTRL_PIN(25, "GPIO_25"), + PINCTRL_PIN(26, "GPIO_26"), + PINCTRL_PIN(27, "GPIO_27"), + PINCTRL_PIN(28, "GPIO_28"), + PINCTRL_PIN(29, "GPIO_29"), + PINCTRL_PIN(30, "GPIO_30"), + PINCTRL_PIN(31, "GPIO_31"), + PINCTRL_PIN(32, "GPIO_32"), + PINCTRL_PIN(33, "GPIO_33"), + PINCTRL_PIN(34, "GPIO_34"), + PINCTRL_PIN(35, "GPIO_35"), + PINCTRL_PIN(36, "GPIO_36"), + PINCTRL_PIN(37, "GPIO_37"), + PINCTRL_PIN(38, "GPIO_38"), + PINCTRL_PIN(39, "GPIO_39"), + PINCTRL_PIN(40, "GPIO_40"), + PINCTRL_PIN(41, "GPIO_41"), + PINCTRL_PIN(42, "GPIO_42"), + PINCTRL_PIN(43, "GPIO_43"), + PINCTRL_PIN(44, "GPIO_44"), + PINCTRL_PIN(45, "GPIO_45"), + PINCTRL_PIN(46, "GPIO_46"), + PINCTRL_PIN(47, "GPIO_47"), + PINCTRL_PIN(48, "GPIO_48"), + PINCTRL_PIN(49, "GPIO_49"), + PINCTRL_PIN(50, "GPIO_50"), + PINCTRL_PIN(51, "GPIO_51"), + PINCTRL_PIN(52, "GPIO_52"), + PINCTRL_PIN(53, "GPIO_53"), + PINCTRL_PIN(54, "GPIO_54"), + PINCTRL_PIN(55, "GPIO_55"), + PINCTRL_PIN(56, "GPIO_56"), + PINCTRL_PIN(57, "GPIO_57"), + PINCTRL_PIN(58, "GPIO_58"), + PINCTRL_PIN(59, "GPIO_59"), + PINCTRL_PIN(60, "GPIO_60"), + PINCTRL_PIN(61, "GPIO_61"), + PINCTRL_PIN(62, "GPIO_62"), + PINCTRL_PIN(63, "GPIO_63"), + PINCTRL_PIN(64, "GPIO_64"), + PINCTRL_PIN(65, "GPIO_65"), + PINCTRL_PIN(66, "GPIO_66"), + PINCTRL_PIN(67, "GPIO_67"), + PINCTRL_PIN(68, "GPIO_68"), + PINCTRL_PIN(69, "GPIO_69"), + PINCTRL_PIN(70, "GPIO_70"), + PINCTRL_PIN(71, "GPIO_71"), + PINCTRL_PIN(72, "GPIO_72"), + PINCTRL_PIN(73, "GPIO_73"), + PINCTRL_PIN(74, "GPIO_74"), + PINCTRL_PIN(75, "GPIO_75"), + PINCTRL_PIN(76, "GPIO_76"), + PINCTRL_PIN(77, "GPIO_77"), + PINCTRL_PIN(78, "GPIO_78"), + PINCTRL_PIN(79, "GPIO_79"), + PINCTRL_PIN(80, "GPIO_80"), + PINCTRL_PIN(81, "GPIO_81"), + PINCTRL_PIN(82, "GPIO_82"), + PINCTRL_PIN(83, "GPIO_83"), + PINCTRL_PIN(84, "GPIO_84"), + PINCTRL_PIN(85, "GPIO_85"), + PINCTRL_PIN(86, "GPIO_86"), + PINCTRL_PIN(87, "GPIO_87"), + PINCTRL_PIN(88, "GPIO_88"), + PINCTRL_PIN(89, "GPIO_89"), + PINCTRL_PIN(90, "GPIO_90"), + PINCTRL_PIN(91, "GPIO_91"), + PINCTRL_PIN(92, "GPIO_92"), + PINCTRL_PIN(93, "GPIO_93"), + PINCTRL_PIN(94, "GPIO_94"), + PINCTRL_PIN(95, "GPIO_95"), + PINCTRL_PIN(96, "GPIO_96"), + PINCTRL_PIN(97, "GPIO_97"), + PINCTRL_PIN(98, "GPIO_98"), + PINCTRL_PIN(99, "GPIO_99"), + PINCTRL_PIN(100, "GPIO_100"), + PINCTRL_PIN(101, "GPIO_101"), + PINCTRL_PIN(102, "GPIO_102"), + PINCTRL_PIN(103, "GPIO_103"), + PINCTRL_PIN(104, "GPIO_104"), + PINCTRL_PIN(105, "GPIO_105"), + PINCTRL_PIN(106, "GPIO_106"), + PINCTRL_PIN(107, "GPIO_107"), + PINCTRL_PIN(108, "GPIO_108"), + PINCTRL_PIN(109, "GPIO_109"), + PINCTRL_PIN(110, "GPIO_110"), + PINCTRL_PIN(111, "GPIO_111"), + PINCTRL_PIN(112, "GPIO_112"), + PINCTRL_PIN(113, "GPIO_113"), + PINCTRL_PIN(114, "GPIO_114"), + PINCTRL_PIN(115, "GPIO_115"), + PINCTRL_PIN(116, "GPIO_116"), + PINCTRL_PIN(117, "GPIO_117"), + PINCTRL_PIN(118, "GPIO_118"), + PINCTRL_PIN(119, "GPIO_119"), + PINCTRL_PIN(120, "GPIO_120"), + PINCTRL_PIN(121, "GPIO_121"), + PINCTRL_PIN(122, "GPIO_122"), + PINCTRL_PIN(123, "GPIO_123"), + PINCTRL_PIN(124, "GPIO_124"), + PINCTRL_PIN(125, "GPIO_125"), + PINCTRL_PIN(126, "GPIO_126"), + PINCTRL_PIN(127, "GPIO_127"), + PINCTRL_PIN(128, "GPIO_128"), + PINCTRL_PIN(129, "GPIO_129"), + PINCTRL_PIN(130, "GPIO_130"), + PINCTRL_PIN(131, "GPIO_131"), + PINCTRL_PIN(132, "GPIO_132"), + PINCTRL_PIN(133, "GPIO_133"), + PINCTRL_PIN(134, "GPIO_134"), + PINCTRL_PIN(135, "GPIO_135"), + PINCTRL_PIN(136, "GPIO_136"), + PINCTRL_PIN(137, "GPIO_137"), + PINCTRL_PIN(138, "GPIO_138"), + PINCTRL_PIN(139, "GPIO_139"), + PINCTRL_PIN(140, "GPIO_140"), + PINCTRL_PIN(141, "GPIO_141"), + PINCTRL_PIN(142, "GPIO_142"), + PINCTRL_PIN(143, "GPIO_143"), + PINCTRL_PIN(144, "GPIO_144"), + PINCTRL_PIN(145, "GPIO_145"), + PINCTRL_PIN(146, "GPIO_146"), + PINCTRL_PIN(147, "GPIO_147"), + PINCTRL_PIN(148, "GPIO_148"), + PINCTRL_PIN(149, "UFS_RESET"), + PINCTRL_PIN(150, "SDC1_RCLK"), + PINCTRL_PIN(151, "SDC1_CLK"), + PINCTRL_PIN(152, "SDC1_CMD"), + PINCTRL_PIN(153, "SDC1_DATA"), +}; + +#define DECLARE_MSM_GPIO_PINS(pin) \ + static const unsigned int gpio##pin##_pins[] = { pin } +DECLARE_MSM_GPIO_PINS(0); +DECLARE_MSM_GPIO_PINS(1); +DECLARE_MSM_GPIO_PINS(2); +DECLARE_MSM_GPIO_PINS(3); +DECLARE_MSM_GPIO_PINS(4); +DECLARE_MSM_GPIO_PINS(5); +DECLARE_MSM_GPIO_PINS(6); +DECLARE_MSM_GPIO_PINS(7); +DECLARE_MSM_GPIO_PINS(8); +DECLARE_MSM_GPIO_PINS(9); +DECLARE_MSM_GPIO_PINS(10); +DECLARE_MSM_GPIO_PINS(11); +DECLARE_MSM_GPIO_PINS(12); +DECLARE_MSM_GPIO_PINS(13); +DECLARE_MSM_GPIO_PINS(14); +DECLARE_MSM_GPIO_PINS(15); +DECLARE_MSM_GPIO_PINS(16); +DECLARE_MSM_GPIO_PINS(17); +DECLARE_MSM_GPIO_PINS(18); +DECLARE_MSM_GPIO_PINS(19); +DECLARE_MSM_GPIO_PINS(20); +DECLARE_MSM_GPIO_PINS(21); +DECLARE_MSM_GPIO_PINS(22); +DECLARE_MSM_GPIO_PINS(23); +DECLARE_MSM_GPIO_PINS(24); +DECLARE_MSM_GPIO_PINS(25); +DECLARE_MSM_GPIO_PINS(26); +DECLARE_MSM_GPIO_PINS(27); +DECLARE_MSM_GPIO_PINS(28); +DECLARE_MSM_GPIO_PINS(29); +DECLARE_MSM_GPIO_PINS(30); +DECLARE_MSM_GPIO_PINS(31); +DECLARE_MSM_GPIO_PINS(32); +DECLARE_MSM_GPIO_PINS(33); +DECLARE_MSM_GPIO_PINS(34); +DECLARE_MSM_GPIO_PINS(35); +DECLARE_MSM_GPIO_PINS(36); +DECLARE_MSM_GPIO_PINS(37); +DECLARE_MSM_GPIO_PINS(38); +DECLARE_MSM_GPIO_PINS(39); +DECLARE_MSM_GPIO_PINS(40); +DECLARE_MSM_GPIO_PINS(41); +DECLARE_MSM_GPIO_PINS(42); +DECLARE_MSM_GPIO_PINS(43); +DECLARE_MSM_GPIO_PINS(44); +DECLARE_MSM_GPIO_PINS(45); +DECLARE_MSM_GPIO_PINS(46); +DECLARE_MSM_GPIO_PINS(47); +DECLARE_MSM_GPIO_PINS(48); +DECLARE_MSM_GPIO_PINS(49); +DECLARE_MSM_GPIO_PINS(50); +DECLARE_MSM_GPIO_PINS(51); +DECLARE_MSM_GPIO_PINS(52); +DECLARE_MSM_GPIO_PINS(53); +DECLARE_MSM_GPIO_PINS(54); +DECLARE_MSM_GPIO_PINS(55); +DECLARE_MSM_GPIO_PINS(56); +DECLARE_MSM_GPIO_PINS(57); +DECLARE_MSM_GPIO_PINS(58); +DECLARE_MSM_GPIO_PINS(59); +DECLARE_MSM_GPIO_PINS(60); +DECLARE_MSM_GPIO_PINS(61); +DECLARE_MSM_GPIO_PINS(62); +DECLARE_MSM_GPIO_PINS(63); +DECLARE_MSM_GPIO_PINS(64); +DECLARE_MSM_GPIO_PINS(65); +DECLARE_MSM_GPIO_PINS(66); +DECLARE_MSM_GPIO_PINS(67); +DECLARE_MSM_GPIO_PINS(68); +DECLARE_MSM_GPIO_PINS(69); +DECLARE_MSM_GPIO_PINS(70); +DECLARE_MSM_GPIO_PINS(71); +DECLARE_MSM_GPIO_PINS(72); +DECLARE_MSM_GPIO_PINS(73); +DECLARE_MSM_GPIO_PINS(74); +DECLARE_MSM_GPIO_PINS(75); +DECLARE_MSM_GPIO_PINS(76); +DECLARE_MSM_GPIO_PINS(77); +DECLARE_MSM_GPIO_PINS(78); +DECLARE_MSM_GPIO_PINS(79); +DECLARE_MSM_GPIO_PINS(80); +DECLARE_MSM_GPIO_PINS(81); +DECLARE_MSM_GPIO_PINS(82); +DECLARE_MSM_GPIO_PINS(83); +DECLARE_MSM_GPIO_PINS(84); +DECLARE_MSM_GPIO_PINS(85); +DECLARE_MSM_GPIO_PINS(86); +DECLARE_MSM_GPIO_PINS(87); +DECLARE_MSM_GPIO_PINS(88); +DECLARE_MSM_GPIO_PINS(89); +DECLARE_MSM_GPIO_PINS(90); +DECLARE_MSM_GPIO_PINS(91); +DECLARE_MSM_GPIO_PINS(92); +DECLARE_MSM_GPIO_PINS(93); +DECLARE_MSM_GPIO_PINS(94); +DECLARE_MSM_GPIO_PINS(95); +DECLARE_MSM_GPIO_PINS(96); +DECLARE_MSM_GPIO_PINS(97); +DECLARE_MSM_GPIO_PINS(98); +DECLARE_MSM_GPIO_PINS(99); +DECLARE_MSM_GPIO_PINS(100); +DECLARE_MSM_GPIO_PINS(101); +DECLARE_MSM_GPIO_PINS(102); +DECLARE_MSM_GPIO_PINS(103); +DECLARE_MSM_GPIO_PINS(104); +DECLARE_MSM_GPIO_PINS(105); +DECLARE_MSM_GPIO_PINS(106); +DECLARE_MSM_GPIO_PINS(107); +DECLARE_MSM_GPIO_PINS(108); +DECLARE_MSM_GPIO_PINS(109); +DECLARE_MSM_GPIO_PINS(110); +DECLARE_MSM_GPIO_PINS(111); +DECLARE_MSM_GPIO_PINS(112); +DECLARE_MSM_GPIO_PINS(113); +DECLARE_MSM_GPIO_PINS(114); +DECLARE_MSM_GPIO_PINS(115); +DECLARE_MSM_GPIO_PINS(116); +DECLARE_MSM_GPIO_PINS(117); +DECLARE_MSM_GPIO_PINS(118); +DECLARE_MSM_GPIO_PINS(119); +DECLARE_MSM_GPIO_PINS(120); +DECLARE_MSM_GPIO_PINS(121); +DECLARE_MSM_GPIO_PINS(122); +DECLARE_MSM_GPIO_PINS(123); +DECLARE_MSM_GPIO_PINS(124); +DECLARE_MSM_GPIO_PINS(125); +DECLARE_MSM_GPIO_PINS(126); +DECLARE_MSM_GPIO_PINS(127); +DECLARE_MSM_GPIO_PINS(128); +DECLARE_MSM_GPIO_PINS(129); +DECLARE_MSM_GPIO_PINS(130); +DECLARE_MSM_GPIO_PINS(131); +DECLARE_MSM_GPIO_PINS(132); +DECLARE_MSM_GPIO_PINS(133); +DECLARE_MSM_GPIO_PINS(134); +DECLARE_MSM_GPIO_PINS(135); +DECLARE_MSM_GPIO_PINS(136); +DECLARE_MSM_GPIO_PINS(137); +DECLARE_MSM_GPIO_PINS(138); +DECLARE_MSM_GPIO_PINS(139); +DECLARE_MSM_GPIO_PINS(140); +DECLARE_MSM_GPIO_PINS(141); +DECLARE_MSM_GPIO_PINS(142); +DECLARE_MSM_GPIO_PINS(143); +DECLARE_MSM_GPIO_PINS(144); +DECLARE_MSM_GPIO_PINS(145); +DECLARE_MSM_GPIO_PINS(146); +DECLARE_MSM_GPIO_PINS(147); +DECLARE_MSM_GPIO_PINS(148); + +static const unsigned int ufs_reset_pins[] = { 149 }; +static const unsigned int sdc1_rclk_pins[] = { 150 }; +static const unsigned int sdc1_clk_pins[] = { 151 }; +static const unsigned int sdc1_cmd_pins[] = { 152 }; +static const unsigned int sdc1_data_pins[] = { 153 }; + +enum sa8775p_functions { + msm_mux_gpio, + msm_mux_atest_char, + msm_mux_atest_usb2, + msm_mux_audio_ref, + msm_mux_cam_mclk, + msm_mux_cci_async, + msm_mux_cci_i2c, + msm_mux_cci_timer0, + msm_mux_cci_timer1, + msm_mux_cci_timer2, + msm_mux_cci_timer3, + msm_mux_cci_timer4, + msm_mux_cci_timer5, + msm_mux_cci_timer6, + msm_mux_cci_timer7, + msm_mux_cci_timer8, + msm_mux_cci_timer9, + msm_mux_cri_trng, + msm_mux_cri_trng0, + msm_mux_cri_trng1, + msm_mux_dbg_out, + msm_mux_ddr_bist, + msm_mux_ddr_pxi0, + msm_mux_ddr_pxi1, + msm_mux_ddr_pxi2, + msm_mux_ddr_pxi3, + msm_mux_ddr_pxi4, + msm_mux_ddr_pxi5, + msm_mux_edp0_hot, + msm_mux_edp0_lcd, + msm_mux_edp1_hot, + msm_mux_edp1_lcd, + msm_mux_edp2_hot, + msm_mux_edp2_lcd, + msm_mux_edp3_hot, + msm_mux_edp3_lcd, + msm_mux_emac0_mcg0, + msm_mux_emac0_mcg1, + msm_mux_emac0_mcg2, + msm_mux_emac0_mcg3, + msm_mux_emac0_mdc, + msm_mux_emac0_mdio, + msm_mux_emac0_ptp_aux, + msm_mux_emac0_ptp_pps, + msm_mux_emac1_mcg0, + msm_mux_emac1_mcg1, + msm_mux_emac1_mcg2, + msm_mux_emac1_mcg3, + msm_mux_emac1_mdc, + msm_mux_emac1_mdio, + msm_mux_emac1_ptp_aux, + msm_mux_emac1_ptp_pps, + msm_mux_gcc_gp1, + msm_mux_gcc_gp2, + msm_mux_gcc_gp3, + msm_mux_gcc_gp4, + msm_mux_gcc_gp5, + msm_mux_hs0_mi2s, + msm_mux_hs1_mi2s, + msm_mux_hs2_mi2s, + msm_mux_ibi_i3c, + msm_mux_jitter_bist, + msm_mux_mdp0_vsync0, + msm_mux_mdp0_vsync1, + msm_mux_mdp0_vsync2, + msm_mux_mdp0_vsync3, + msm_mux_mdp0_vsync4, + msm_mux_mdp0_vsync5, + msm_mux_mdp0_vsync6, + msm_mux_mdp0_vsync7, + msm_mux_mdp0_vsync8, + msm_mux_mdp1_vsync0, + msm_mux_mdp1_vsync1, + msm_mux_mdp1_vsync2, + msm_mux_mdp1_vsync3, + msm_mux_mdp1_vsync4, + msm_mux_mdp1_vsync5, + msm_mux_mdp1_vsync6, + msm_mux_mdp1_vsync7, + msm_mux_mdp1_vsync8, + msm_mux_mdp_vsync, + msm_mux_mi2s1_data0, + msm_mux_mi2s1_data1, + msm_mux_mi2s1_sck, + msm_mux_mi2s1_ws, + msm_mux_mi2s2_data0, + msm_mux_mi2s2_data1, + msm_mux_mi2s2_sck, + msm_mux_mi2s2_ws, + msm_mux_mi2s_mclk0, + msm_mux_mi2s_mclk1, + msm_mux_pcie0_clkreq, + msm_mux_pcie1_clkreq, + msm_mux_phase_flag, + msm_mux_pll_bist, + msm_mux_pll_clk, + msm_mux_prng_rosc0, + msm_mux_prng_rosc1, + msm_mux_prng_rosc2, + msm_mux_prng_rosc3, + msm_mux_qdss_cti, + msm_mux_qdss_gpio, + msm_mux_qup0_se0, + msm_mux_qup0_se1, + msm_mux_qup0_se2, + msm_mux_qup0_se3, + msm_mux_qup0_se4, + msm_mux_qup0_se5, + msm_mux_qup1_se0, + msm_mux_qup1_se1, + msm_mux_qup1_se2, + msm_mux_qup1_se3, + msm_mux_qup1_se4, + msm_mux_qup1_se5, + msm_mux_qup1_se6, + msm_mux_qup2_se0, + msm_mux_qup2_se1, + msm_mux_qup2_se2, + msm_mux_qup2_se3, + msm_mux_qup2_se4, + msm_mux_qup2_se5, + msm_mux_qup2_se6, + msm_mux_qup3_se0, + msm_mux_sail_top, + msm_mux_sailss_emac0, + msm_mux_sailss_ospi, + msm_mux_sgmii_phy, + msm_mux_tb_trig, + msm_mux_tgu_ch0, + msm_mux_tgu_ch1, + msm_mux_tgu_ch2, + msm_mux_tgu_ch3, + msm_mux_tgu_ch4, + msm_mux_tgu_ch5, + msm_mux_tsense_pwm1, + msm_mux_tsense_pwm2, + msm_mux_tsense_pwm3, + msm_mux_tsense_pwm4, + msm_mux_usb2phy_ac, + msm_mux_vsense_trigger, + msm_mux__, +}; + +static const char * const gpio_groups[] = { + "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7", + "gpio8", "gpio9", "gpio10", "gpio11", "gpio12", "gpio13", "gpio14", + "gpio15", "gpio16", "gpio17", "gpio18", "gpio19", "gpio20", "gpio21", + "gpio22", "gpio23", "gpio24", "gpio25", "gpio26", "gpio27", "gpio28", + "gpio29", "gpio30", "gpio31", "gpio32", "gpio33", "gpio34", "gpio35", + "gpio36", "gpio37", "gpio38", "gpio39", "gpio40", "gpio41", "gpio42", + "gpio43", "gpio44", "gpio45", "gpio46", "gpio47", "gpio48", "gpio49", + "gpio50", "gpio51", "gpio52", "gpio53", "gpio54", "gpio55", "gpio56", + "gpio57", "gpio58", "gpio59", "gpio60", "gpio61", "gpio62", "gpio63", + "gpio64", "gpio65", "gpio66", "gpio67", "gpio68", "gpio69", "gpio70", + "gpio71", "gpio72", "gpio73", "gpio74", "gpio75", "gpio76", "gpio77", + "gpio78", "gpio79", "gpio80", "gpio81", "gpio82", "gpio83", "gpio84", + "gpio85", "gpio86", "gpio87", "gpio88", "gpio89", "gpio90", "gpio91", + "gpio92", "gpio93", "gpio94", "gpio95", "gpio96", "gpio97", "gpio98", + "gpio99", "gpio100", "gpio101", "gpio102", "gpio103", "gpio104", + "gpio105", "gpio106", "gpio107", "gpio108", "gpio109", "gpio110", + "gpio111", "gpio112", "gpio113", "gpio114", "gpio115", "gpio116", + "gpio117", "gpio118", "gpio119", "gpio120", "gpio121", "gpio122", + "gpio123", "gpio124", "gpio125", "gpio126", "gpio127", "gpio128", + "gpio129", "gpio130", "gpio131", "gpio132", "gpio133", "gpio134", + "gpio135", "gpio136", "gpio137", "gpio138", "gpio139", "gpio140", + "gpio141", "gpio142", "gpio143", "gpio144", "gpio145", "gpio146", + "gpio147", "gpio148", +}; + +static const char * const atest_char_groups[] = { + "gpio27", "gpio58", "gpio59", "gpio89", "gpio90", +}; + +static const char * const atest_usb2_groups[] = { + "gpio58", "gpio59", "gpio86", "gpio87", "gpio88", "gpio89", "gpio90", + "gpio91", "gpio92", "gpio93", "gpio94", "gpio95", "gpio96", "gpio97", + "gpio105", +}; + +static const char * const audio_ref_groups[] = { + "gpio113", +}; + +static const char * const cam_mclk_groups[] = { + "gpio72", "gpio73", "gpio74", "gpio75", +}; + +static const char * const cci_async_groups[] = { + "gpio50", "gpio66", "gpio68", "gpio69", "gpio70", "gpio71", +}; + +static const char * const cci_i2c_groups[] = { + "gpio52", "gpio53", "gpio54", "gpio55", "gpio56", "gpio57", "gpio58", + "gpio59", "gpio60", "gpio61", "gpio62", "gpio63", "gpio64", "gpio65", + "gpio66", "gpio67", +}; + +static const char * const cci_timer0_groups[] = { + "gpio68", +}; + +static const char * const cci_timer1_groups[] = { + "gpio69", +}; + +static const char * const cci_timer2_groups[] = { + "gpio70", +}; + +static const char * const cci_timer3_groups[] = { + "gpio71", +}; + +static const char * const cci_timer4_groups[] = { + "gpio52", +}; + +static const char * const cci_timer5_groups[] = { + "gpio53", +}; + +static const char * const cci_timer6_groups[] = { + "gpio54", +}; + +static const char * const cci_timer7_groups[] = { + "gpio55", +}; + +static const char * const cci_timer8_groups[] = { + "gpio56", +}; + +static const char * const cci_timer9_groups[] = { + "gpio57", +}; + +static const char * const cri_trng_groups[] = { + "gpio99", +}; + +static const char * const cri_trng0_groups[] = { + "gpio97", +}; + +static const char * const cri_trng1_groups[] = { + "gpio98", +}; + +static const char * const dbg_out_groups[] = { + "gpio144", +}; + +static const char * const ddr_bist_groups[] = { + "gpio56", "gpio57", "gpio58", "gpio59", +}; + +static const char * const ddr_pxi0_groups[] = { + "gpio33", "gpio34", +}; + +static const char * const ddr_pxi1_groups[] = { + "gpio52", "gpio53", +}; + +static const char * const ddr_pxi2_groups[] = { + "gpio55", "gpio86", +}; + +static const char * const ddr_pxi3_groups[] = { + "gpio87", "gpio88", +}; + +static const char * const ddr_pxi4_groups[] = { + "gpio89", "gpio90", +}; + +static const char * const ddr_pxi5_groups[] = { + "gpio118", "gpio119", +}; + +static const char * const edp0_hot_groups[] = { + "gpio101", +}; + +static const char * const edp0_lcd_groups[] = { + "gpio44", +}; + +static const char * const edp1_hot_groups[] = { + "gpio102", +}; + +static const char * const edp1_lcd_groups[] = { + "gpio45", +}; + +static const char * const edp2_hot_groups[] = { + "gpio104", +}; + +static const char * const edp2_lcd_groups[] = { + "gpio48", +}; + +static const char * const edp3_hot_groups[] = { + "gpio103", +}; + +static const char * const edp3_lcd_groups[] = { + "gpio49", +}; + +static const char * const emac0_mcg0_groups[] = { + "gpio12", +}; + +static const char * const emac0_mcg1_groups[] = { + "gpio13", +}; + +static const char * const emac0_mcg2_groups[] = { + "gpio14", +}; + +static const char * const emac0_mcg3_groups[] = { + "gpio15", +}; + +static const char * const emac0_mdc_groups[] = { + "gpio8", +}; + +static const char * const emac0_mdio_groups[] = { + "gpio9", +}; + +static const char * const emac0_ptp_aux_groups[] = { + "gpio6", "gpio10", "gpio11", "gpio12", +}; + +static const char * const emac0_ptp_pps_groups[] = { + "gpio6", "gpio10", "gpio11", "gpio12", +}; + +static const char * const emac1_mcg0_groups[] = { + "gpio16", + +}; + +static const char * const emac1_mcg1_groups[] = { + "gpio17", +}; + +static const char * const emac1_mcg2_groups[] = { + "gpio18", +}; + +static const char * const emac1_mcg3_groups[] = { + "gpio19", +}; + +static const char * const emac1_mdc_groups[] = { + "gpio20", +}; + +static const char * const emac1_mdio_groups[] = { + "gpio21", +}; + +static const char * const emac1_ptp_aux_groups[] = { + "gpio6", "gpio10", "gpio11", "gpio12", +}; + +static const char * const emac1_ptp_pps_groups[] = { + "gpio6", "gpio10", "gpio11", "gpio12", +}; + +static const char * const gcc_gp1_groups[] = { + "gpio51", "gpio82", +}; + +static const char * const gcc_gp2_groups[] = { + "gpio52", "gpio83", +}; + +static const char * const gcc_gp3_groups[] = { + "gpio53", "gpio84", +}; + +static const char * const gcc_gp4_groups[] = { + "gpio33", "gpio55", +}; + +static const char * const gcc_gp5_groups[] = { + "gpio34", "gpio42", +}; + +static const char * const hs0_mi2s_groups[] = { + "gpio114", "gpio115", "gpio116", "gpio117", +}; + +static const char * const hs1_mi2s_groups[] = { + "gpio118", "gpio119", "gpio120", "gpio121", +}; + +static const char * const hs2_mi2s_groups[] = { + "gpio122", "gpio123", "gpio124", "gpio125", +}; + +static const char * const ibi_i3c_groups[] = { + "gpio40", "gpio41", "gpio42", "gpio43", "gpio80", "gpio81", "gpio84", + "gpio85", +}; + +static const char * const jitter_bist_groups[] = { + "gpio86", +}; + +static const char * const mdp0_vsync0_groups[] = { + "gpio57", +}; + +static const char * const mdp0_vsync1_groups[] = { + "gpio58", +}; + +static const char * const mdp0_vsync2_groups[] = { + "gpio59", +}; + +static const char * const mdp0_vsync3_groups[] = { + "gpio80", +}; + +static const char * const mdp0_vsync4_groups[] = { + "gpio81", +}; + +static const char * const mdp0_vsync5_groups[] = { + "gpio91", +}; + +static const char * const mdp0_vsync6_groups[] = { + "gpio92", +}; + +static const char * const mdp0_vsync7_groups[] = { + "gpio93", +}; + +static const char * const mdp0_vsync8_groups[] = { + "gpio94", +}; + +static const char * const mdp1_vsync0_groups[] = { + "gpio40", +}; + +static const char * const mdp1_vsync1_groups[] = { + "gpio41", +}; + +static const char * const mdp1_vsync2_groups[] = { + "gpio42", +}; + +static const char * const mdp1_vsync3_groups[] = { + "gpio43", +}; + +static const char * const mdp1_vsync4_groups[] = { + "gpio46", +}; + +static const char * const mdp1_vsync5_groups[] = { + "gpio47", +}; + +static const char * const mdp1_vsync6_groups[] = { + "gpio51", +}; + +static const char * const mdp1_vsync7_groups[] = { + "gpio52", +}; + +static const char * const mdp1_vsync8_groups[] = { + "gpio50", +}; + +static const char * const mdp_vsync_groups[] = { + "gpio82", "gpio83", "gpio84", +}; + +static const char * const mi2s1_data0_groups[] = { + "gpio108", +}; + +static const char * const mi2s1_data1_groups[] = { + "gpio109", +}; + +static const char * const mi2s1_sck_groups[] = { + "gpio106", +}; + +static const char * const mi2s1_ws_groups[] = { + "gpio107", +}; + +static const char * const mi2s2_data0_groups[] = { + "gpio112", +}; + +static const char * const mi2s2_data1_groups[] = { + "gpio113", +}; + +static const char * const mi2s2_sck_groups[] = { + "gpio110", +}; + +static const char * const mi2s2_ws_groups[] = { + "gpio111", +}; + +static const char * const mi2s_mclk0_groups[] = { + "gpio105", +}; + +static const char * const mi2s_mclk1_groups[] = { + "gpio117", +}; + +static const char * const pcie0_clkreq_groups[] = { + "gpio1", +}; + +static const char * const pcie1_clkreq_groups[] = { + "gpio3", +}; + +static const char * const phase_flag_groups[] = { + "gpio25", "gpio26", "gpio27", "gpio28", "gpio29", "gpio30", "gpio31", + "gpio32", "gpio35", "gpio36", "gpio37", "gpio38", "gpio39", "gpio56", + "gpio57", "gpio98", "gpio99", "gpio106", "gpio107", "gpio108", + "gpio109", "gpio110", "gpio111", "gpio112", "gpio113", "gpio114", + "gpio120", "gpio121", "gpio122", "gpio123", "gpio124", "gpio125", +}; + +static const char * const pll_bist_groups[] = { + "gpio114", +}; + +static const char * const pll_clk_groups[] = { + "gpio87", +}; + +static const char * const prng_rosc0_groups[] = { + "gpio101", +}; + +static const char * const prng_rosc1_groups[] = { + "gpio102", +}; + +static const char * const prng_rosc2_groups[] = { + "gpio103", +}; + +static const char * const prng_rosc3_groups[] = { + "gpio104", +}; + +static const char * const qdss_cti_groups[] = { + "gpio26", "gpio27", "gpio38", "gpio39", "gpio48", "gpio49", "gpio50", + "gpio51", +}; + +static const char * const qdss_gpio_groups[] = { + "gpio20", "gpio21", "gpio22", "gpio23", "gpio24", "gpio25", "gpio28", + "gpio29", "gpio30", "gpio31", "gpio60", "gpio61", "gpio62", "gpio63", + "gpio64", "gpio65", "gpio66", "gpio67", "gpio105", "gpio106", "gpio107", + "gpio108", "gpio109", "gpio110", "gpio111", "gpio112", "gpio113", + "gpio114", "gpio115", "gpio116", "gpio117", "gpio118", "gpio119", + "gpio120", "gpio121", "gpio122", +}; + +static const char * const qup0_se0_groups[] = { + "gpio20", "gpio21", "gpio22", "gpio23", +}; + +static const char * const qup0_se1_groups[] = { + "gpio24", "gpio25", "gpio26", "gpio27", +}; + +static const char * const qup0_se2_groups[] = { + "gpio36", "gpio37", "gpio38", "gpio39", +}; + +static const char * const qup0_se3_groups[] = { + "gpio28", "gpio29", "gpio30", "gpio31", +}; + +static const char * const qup0_se4_groups[] = { + "gpio32", "gpio33", "gpio34", "gpio35", +}; + +static const char * const qup0_se5_groups[] = { + "gpio36", "gpio37", "gpio38", "gpio39", +}; + +static const char * const qup1_se0_groups[] = { + "gpio40", "gpio41", "gpio42", "gpio43", +}; + +static const char * const qup1_se1_groups[] = { + "gpio40", "gpio41", "gpio42", "gpio43", +}; + +static const char * const qup1_se2_groups[] = { + "gpio44", "gpio45", "gpio46", "gpio47", +}; + +static const char * const qup1_se3_groups[] = { + "gpio44", "gpio45", "gpio46", "gpio47", +}; + +static const char * const qup1_se4_groups[] = { + "gpio48", "gpio49", "gpio50", "gpio51", +}; + +static const char * const qup1_se5_groups[] = { + "gpio52", "gpio53", "gpio54", "gpio55", +}; + +static const char * const qup1_se6_groups[] = { + "gpio56", "gpio56", "gpio57", "gpio57", +}; + +static const char * const qup2_se0_groups[] = { + "gpio80", "gpio81", "gpio82", "gpio83", +}; + +static const char * const qup2_se1_groups[] = { + "gpio84", "gpio85", "gpio99", "gpio100", +}; + +static const char * const qup2_se2_groups[] = { + "gpio86", "gpio87", "gpio88", "gpio89", "gpio90", +}; + +static const char * const qup2_se3_groups[] = { + "gpio91", "gpio92", "gpio93", "gpio94", +}; + +static const char * const qup2_se4_groups[] = { + "gpio95", "gpio96", "gpio97", "gpio98", +}; + +static const char * const qup2_se5_groups[] = { + "gpio84", "gpio85", "gpio99", "gpio100", +}; + +static const char * const qup2_se6_groups[] = { + "gpio95", "gpio96", "gpio97", "gpio98", +}; + +static const char * const qup3_se0_groups[] = { + "gpio13", "gpio14", "gpio15", "gpio16", "gpio17", "gpio18", "gpio19", +}; + +static const char * const sail_top_groups[] = { + "gpio13", "gpio14", "gpio15", "gpio16", +}; + +static const char * const sailss_emac0_groups[] = { + "gpio18", "gpio19", +}; + +static const char * const sailss_ospi_groups[] = { + "gpio18", "gpio19", +}; + +static const char * const sgmii_phy_groups[] = { + "gpio7", "gpio26", +}; + +static const char * const tb_trig_groups[] = { + "gpio17", "gpio17", +}; + +static const char * const tgu_ch0_groups[] = { + "gpio46", +}; + +static const char * const tgu_ch1_groups[] = { + "gpio47", +}; + +static const char * const tgu_ch2_groups[] = { + "gpio36", +}; + +static const char * const tgu_ch3_groups[] = { + "gpio37", +}; + +static const char * const tgu_ch4_groups[] = { + "gpio38", +}; + +static const char * const tgu_ch5_groups[] = { + "gpio39", +}; + +static const char * const tsense_pwm1_groups[] = { + "gpio104", +}; + +static const char * const tsense_pwm2_groups[] = { + "gpio103", +}; + +static const char * const tsense_pwm3_groups[] = { + "gpio102", +}; + +static const char * const tsense_pwm4_groups[] = { + "gpio101", +}; + +static const char * const usb2phy_ac_groups[] = { + "gpio10", "gpio11", "gpio12", +}; + +static const char * const vsense_trigger_groups[] = { + "gpio111", +}; + +static const struct pinfunction sa8775p_functions[] = { + MSM_PIN_FUNCTION(gpio), + MSM_PIN_FUNCTION(atest_char), + MSM_PIN_FUNCTION(atest_usb2), + MSM_PIN_FUNCTION(audio_ref), + MSM_PIN_FUNCTION(cam_mclk), + MSM_PIN_FUNCTION(cci_async), + MSM_PIN_FUNCTION(cci_i2c), + MSM_PIN_FUNCTION(cci_timer0), + MSM_PIN_FUNCTION(cci_timer1), + MSM_PIN_FUNCTION(cci_timer2), + MSM_PIN_FUNCTION(cci_timer3), + MSM_PIN_FUNCTION(cci_timer4), + MSM_PIN_FUNCTION(cci_timer5), + MSM_PIN_FUNCTION(cci_timer6), + MSM_PIN_FUNCTION(cci_timer7), + MSM_PIN_FUNCTION(cci_timer8), + MSM_PIN_FUNCTION(cci_timer9), + MSM_PIN_FUNCTION(cri_trng), + MSM_PIN_FUNCTION(cri_trng0), + MSM_PIN_FUNCTION(cri_trng1), + MSM_PIN_FUNCTION(dbg_out), + MSM_PIN_FUNCTION(ddr_bist), + MSM_PIN_FUNCTION(ddr_pxi0), + MSM_PIN_FUNCTION(ddr_pxi1), + MSM_PIN_FUNCTION(ddr_pxi2), + MSM_PIN_FUNCTION(ddr_pxi3), + MSM_PIN_FUNCTION(ddr_pxi4), + MSM_PIN_FUNCTION(ddr_pxi5), + MSM_PIN_FUNCTION(edp0_hot), + MSM_PIN_FUNCTION(edp0_lcd), + MSM_PIN_FUNCTION(edp1_hot), + MSM_PIN_FUNCTION(edp1_lcd), + MSM_PIN_FUNCTION(edp2_hot), + MSM_PIN_FUNCTION(edp2_lcd), + MSM_PIN_FUNCTION(edp3_hot), + MSM_PIN_FUNCTION(edp3_lcd), + MSM_PIN_FUNCTION(emac0_mcg0), + MSM_PIN_FUNCTION(emac0_mcg1), + MSM_PIN_FUNCTION(emac0_mcg2), + MSM_PIN_FUNCTION(emac0_mcg3), + MSM_PIN_FUNCTION(emac0_mdc), + MSM_PIN_FUNCTION(emac0_mdio), + MSM_PIN_FUNCTION(emac0_ptp_aux), + MSM_PIN_FUNCTION(emac0_ptp_pps), + MSM_PIN_FUNCTION(emac1_mcg0), + MSM_PIN_FUNCTION(emac1_mcg1), + MSM_PIN_FUNCTION(emac1_mcg2), + MSM_PIN_FUNCTION(emac1_mcg3), + MSM_PIN_FUNCTION(emac1_mdc), + MSM_PIN_FUNCTION(emac1_mdio), + MSM_PIN_FUNCTION(emac1_ptp_aux), + MSM_PIN_FUNCTION(emac1_ptp_pps), + MSM_PIN_FUNCTION(gcc_gp1), + MSM_PIN_FUNCTION(gcc_gp2), + MSM_PIN_FUNCTION(gcc_gp3), + MSM_PIN_FUNCTION(gcc_gp4), + MSM_PIN_FUNCTION(gcc_gp5), + MSM_PIN_FUNCTION(hs0_mi2s), + MSM_PIN_FUNCTION(hs1_mi2s), + MSM_PIN_FUNCTION(hs2_mi2s), + MSM_PIN_FUNCTION(ibi_i3c), + MSM_PIN_FUNCTION(jitter_bist), + MSM_PIN_FUNCTION(mdp0_vsync0), + MSM_PIN_FUNCTION(mdp0_vsync1), + MSM_PIN_FUNCTION(mdp0_vsync2), + MSM_PIN_FUNCTION(mdp0_vsync3), + MSM_PIN_FUNCTION(mdp0_vsync4), + MSM_PIN_FUNCTION(mdp0_vsync5), + MSM_PIN_FUNCTION(mdp0_vsync6), + MSM_PIN_FUNCTION(mdp0_vsync7), + MSM_PIN_FUNCTION(mdp0_vsync8), + MSM_PIN_FUNCTION(mdp1_vsync0), + MSM_PIN_FUNCTION(mdp1_vsync1), + MSM_PIN_FUNCTION(mdp1_vsync2), + MSM_PIN_FUNCTION(mdp1_vsync3), + MSM_PIN_FUNCTION(mdp1_vsync4), + MSM_PIN_FUNCTION(mdp1_vsync5), + MSM_PIN_FUNCTION(mdp1_vsync6), + MSM_PIN_FUNCTION(mdp1_vsync7), + MSM_PIN_FUNCTION(mdp1_vsync8), + MSM_PIN_FUNCTION(mdp_vsync), + MSM_PIN_FUNCTION(mi2s1_data0), + MSM_PIN_FUNCTION(mi2s1_data1), + MSM_PIN_FUNCTION(mi2s1_sck), + MSM_PIN_FUNCTION(mi2s1_ws), + MSM_PIN_FUNCTION(mi2s2_data0), + MSM_PIN_FUNCTION(mi2s2_data1), + MSM_PIN_FUNCTION(mi2s2_sck), + MSM_PIN_FUNCTION(mi2s2_ws), + MSM_PIN_FUNCTION(mi2s_mclk0), + MSM_PIN_FUNCTION(mi2s_mclk1), + MSM_PIN_FUNCTION(pcie0_clkreq), + MSM_PIN_FUNCTION(pcie1_clkreq), + MSM_PIN_FUNCTION(phase_flag), + MSM_PIN_FUNCTION(pll_bist), + MSM_PIN_FUNCTION(pll_clk), + MSM_PIN_FUNCTION(prng_rosc0), + MSM_PIN_FUNCTION(prng_rosc1), + MSM_PIN_FUNCTION(prng_rosc2), + MSM_PIN_FUNCTION(prng_rosc3), + MSM_PIN_FUNCTION(qdss_cti), + MSM_PIN_FUNCTION(qdss_gpio), + MSM_PIN_FUNCTION(qup0_se0), + MSM_PIN_FUNCTION(qup0_se1), + MSM_PIN_FUNCTION(qup0_se2), + MSM_PIN_FUNCTION(qup0_se3), + MSM_PIN_FUNCTION(qup0_se4), + MSM_PIN_FUNCTION(qup0_se5), + MSM_PIN_FUNCTION(qup1_se0), + MSM_PIN_FUNCTION(qup1_se1), + MSM_PIN_FUNCTION(qup1_se2), + MSM_PIN_FUNCTION(qup1_se3), + MSM_PIN_FUNCTION(qup1_se4), + MSM_PIN_FUNCTION(qup1_se5), + MSM_PIN_FUNCTION(qup1_se6), + MSM_PIN_FUNCTION(qup2_se0), + MSM_PIN_FUNCTION(qup2_se1), + MSM_PIN_FUNCTION(qup2_se2), + MSM_PIN_FUNCTION(qup2_se3), + MSM_PIN_FUNCTION(qup2_se4), + MSM_PIN_FUNCTION(qup2_se5), + MSM_PIN_FUNCTION(qup2_se6), + MSM_PIN_FUNCTION(qup3_se0), + MSM_PIN_FUNCTION(sail_top), + MSM_PIN_FUNCTION(sailss_emac0), + MSM_PIN_FUNCTION(sailss_ospi), + MSM_PIN_FUNCTION(sgmii_phy), + MSM_PIN_FUNCTION(tb_trig), + MSM_PIN_FUNCTION(tgu_ch0), + MSM_PIN_FUNCTION(tgu_ch1), + MSM_PIN_FUNCTION(tgu_ch2), + MSM_PIN_FUNCTION(tgu_ch3), + MSM_PIN_FUNCTION(tgu_ch4), + MSM_PIN_FUNCTION(tgu_ch5), + MSM_PIN_FUNCTION(tsense_pwm1), + MSM_PIN_FUNCTION(tsense_pwm2), + MSM_PIN_FUNCTION(tsense_pwm3), + MSM_PIN_FUNCTION(tsense_pwm4), + MSM_PIN_FUNCTION(usb2phy_ac), + MSM_PIN_FUNCTION(vsense_trigger), +}; + +/* + * Every pin is maintained as a single group, and missing or non-existing pin + * would be maintained as dummy group to synchronize pin group index with + * pin descriptor registered with pinctrl core. + * Clients would not be able to request these dummy pin groups. + */ +static const struct msm_pingroup sa8775p_groups[] = { + [0] = PINGROUP(0, _, _, _, _, _, _, _, _, _), + [1] = PINGROUP(1, pcie0_clkreq, _, _, _, _, _, _, _, _), + [2] = PINGROUP(2, _, _, _, _, _, _, _, _, _), + [3] = PINGROUP(3, pcie1_clkreq, _, _, _, _, _, _, _, _), + [4] = PINGROUP(4, _, _, _, _, _, _, _, _, _), + [5] = PINGROUP(5, _, _, _, _, _, _, _, _, _), + [6] = PINGROUP(6, emac0_ptp_aux, emac0_ptp_pps, emac1_ptp_aux, emac1_ptp_pps, + _, _, _, _, _), + [7] = PINGROUP(7, sgmii_phy, _, _, _, _, _, _, _, _), + [8] = PINGROUP(8, emac0_mdc, _, _, _, _, _, _, _, _), + [9] = PINGROUP(9, emac0_mdio, _, _, _, _, _, _, _, _), + [10] = PINGROUP(10, usb2phy_ac, emac0_ptp_aux, emac0_ptp_pps, emac1_ptp_aux, emac1_ptp_pps, + _, _, _, _), + [11] = PINGROUP(11, usb2phy_ac, emac0_ptp_aux, emac0_ptp_pps, emac1_ptp_aux, emac1_ptp_pps, + _, _, _, _), + [12] = PINGROUP(12, usb2phy_ac, emac0_ptp_aux, emac0_ptp_pps, emac1_ptp_aux, emac1_ptp_pps, + emac0_mcg0, _, _, _), + [13] = PINGROUP(13, qup3_se0, emac0_mcg1, _, _, sail_top, _, _, _, _), + [14] = PINGROUP(14, qup3_se0, emac0_mcg2, _, _, sail_top, _, _, _, _), + [15] = PINGROUP(15, qup3_se0, emac0_mcg3, _, _, sail_top, _, _, _, _), + [16] = PINGROUP(16, qup3_se0, emac1_mcg0, _, _, sail_top, _, _, _, _), + [17] = PINGROUP(17, qup3_se0, tb_trig, tb_trig, emac1_mcg1, _, _, _, _, _), + [18] = PINGROUP(18, qup3_se0, emac1_mcg2, _, _, sailss_ospi, sailss_emac0, _, _, _), + [19] = PINGROUP(19, qup3_se0, emac1_mcg3, _, _, sailss_ospi, sailss_emac0, _, _, _), + [20] = PINGROUP(20, qup0_se0, emac1_mdc, qdss_gpio, _, _, _, _, _, _), + [21] = PINGROUP(21, qup0_se0, emac1_mdio, qdss_gpio, _, _, _, _, _, _), + [22] = PINGROUP(22, qup0_se0, qdss_gpio, _, _, _, _, _, _, _), + [23] = PINGROUP(23, qup0_se0, qdss_gpio, _, _, _, _, _, _, _), + [24] = PINGROUP(24, qup0_se1, qdss_gpio, _, _, _, _, _, _, _), + [25] = PINGROUP(25, qup0_se1, phase_flag, _, qdss_gpio, _, _, _, _, _), + [26] = PINGROUP(26, sgmii_phy, qup0_se1, qdss_cti, phase_flag, _, _, _, _, _), + [27] = PINGROUP(27, qup0_se1, qdss_cti, phase_flag, _, atest_char, _, _, _, _), + [28] = PINGROUP(28, qup0_se3, phase_flag, _, qdss_gpio, _, _, _, _, _), + [29] = PINGROUP(29, qup0_se3, phase_flag, _, qdss_gpio, _, _, _, _, _), + [30] = PINGROUP(30, qup0_se3, phase_flag, _, qdss_gpio, _, _, _, _, _), + [31] = PINGROUP(31, qup0_se3, phase_flag, _, qdss_gpio, _, _, _, _, _), + [32] = PINGROUP(32, qup0_se4, phase_flag, _, _, _, _, _, _, _), + [33] = PINGROUP(33, qup0_se4, gcc_gp4, _, ddr_pxi0, _, _, _, _, _), + [34] = PINGROUP(34, qup0_se4, gcc_gp5, _, ddr_pxi0, _, _, _, _, _), + [35] = PINGROUP(35, qup0_se4, phase_flag, _, _, _, _, _, _, _), + [36] = PINGROUP(36, qup0_se2, qup0_se5, phase_flag, tgu_ch2, _, _, _, _, _), + [37] = PINGROUP(37, qup0_se2, qup0_se5, phase_flag, tgu_ch3, _, _, _, _, _), + [38] = PINGROUP(38, qup0_se5, qup0_se2, qdss_cti, phase_flag, tgu_ch4, _, _, _, _), + [39] = PINGROUP(39, qup0_se5, qup0_se2, qdss_cti, phase_flag, tgu_ch5, _, _, _, _), + [40] = PINGROUP(40, qup1_se0, qup1_se1, ibi_i3c, mdp1_vsync0, _, _, _, _, _), + [41] = PINGROUP(41, qup1_se0, qup1_se1, ibi_i3c, mdp1_vsync1, _, _, _, _, _), + [42] = PINGROUP(42, qup1_se1, qup1_se0, ibi_i3c, mdp1_vsync2, gcc_gp5, _, _, _, _), + [43] = PINGROUP(43, qup1_se1, qup1_se0, ibi_i3c, mdp1_vsync3, _, _, _, _, _), + [44] = PINGROUP(44, qup1_se2, qup1_se3, edp0_lcd, _, _, _, _, _, _), + [45] = PINGROUP(45, qup1_se2, qup1_se3, edp1_lcd, _, _, _, _, _, _), + [46] = PINGROUP(46, qup1_se3, qup1_se2, mdp1_vsync4, tgu_ch0, _, _, _, _, _), + [47] = PINGROUP(47, qup1_se3, qup1_se2, mdp1_vsync5, tgu_ch1, _, _, _, _, _), + [48] = PINGROUP(48, qup1_se4, qdss_cti, edp2_lcd, _, _, _, _, _, _), + [49] = PINGROUP(49, qup1_se4, qdss_cti, edp3_lcd, _, _, _, _, _, _), + [50] = PINGROUP(50, qup1_se4, cci_async, qdss_cti, mdp1_vsync8, _, _, _, _, _), + [51] = PINGROUP(51, qup1_se4, qdss_cti, mdp1_vsync6, gcc_gp1, _, _, _, _, _), + [52] = PINGROUP(52, qup1_se5, cci_timer4, cci_i2c, mdp1_vsync7, gcc_gp2, _, ddr_pxi1, _, _), + [53] = PINGROUP(53, qup1_se5, cci_timer5, cci_i2c, gcc_gp3, _, ddr_pxi1, _, _, _), + [54] = PINGROUP(54, qup1_se5, cci_timer6, cci_i2c, _, _, _, _, _, _), + [55] = PINGROUP(55, qup1_se5, cci_timer7, cci_i2c, gcc_gp4, _, ddr_pxi2, _, _, _), + [56] = PINGROUP(56, qup1_se6, qup1_se6, cci_timer8, cci_i2c, phase_flag, + ddr_bist, _, _, _), + [57] = PINGROUP(57, qup1_se6, qup1_se6, cci_timer9, cci_i2c, mdp0_vsync0, + phase_flag, ddr_bist, _, _), + [58] = PINGROUP(58, cci_i2c, mdp0_vsync1, ddr_bist, _, atest_usb2, atest_char, _, _, _), + [59] = PINGROUP(59, cci_i2c, mdp0_vsync2, ddr_bist, _, atest_usb2, atest_char, _, _, _), + [60] = PINGROUP(60, cci_i2c, qdss_gpio, _, _, _, _, _, _, _), + [61] = PINGROUP(61, cci_i2c, qdss_gpio, _, _, _, _, _, _, _), + [62] = PINGROUP(62, cci_i2c, qdss_gpio, _, _, _, _, _, _, _), + [63] = PINGROUP(63, cci_i2c, qdss_gpio, _, _, _, _, _, _, _), + [64] = PINGROUP(64, cci_i2c, qdss_gpio, _, _, _, _, _, _, _), + [65] = PINGROUP(65, cci_i2c, qdss_gpio, _, _, _, _, _, _, _), + [66] = PINGROUP(66, cci_i2c, cci_async, qdss_gpio, _, _, _, _, _, _), + [67] = PINGROUP(67, cci_i2c, qdss_gpio, _, _, _, _, _, _, _), + [68] = PINGROUP(68, cci_timer0, cci_async, _, _, _, _, _, _, _), + [69] = PINGROUP(69, cci_timer1, cci_async, _, _, _, _, _, _, _), + [70] = PINGROUP(70, cci_timer2, cci_async, _, _, _, _, _, _, _), + [71] = PINGROUP(71, cci_timer3, cci_async, _, _, _, _, _, _, _), + [72] = PINGROUP(72, cam_mclk, _, _, _, _, _, _, _, _), + [73] = PINGROUP(73, cam_mclk, _, _, _, _, _, _, _, _), + [74] = PINGROUP(74, cam_mclk, _, _, _, _, _, _, _, _), + [75] = PINGROUP(75, cam_mclk, _, _, _, _, _, _, _, _), + [76] = PINGROUP(76, _, _, _, _, _, _, _, _, _), + [77] = PINGROUP(77, _, _, _, _, _, _, _, _, _), + [78] = PINGROUP(78, _, _, _, _, _, _, _, _, _), + [79] = PINGROUP(79, _, _, _, _, _, _, _, _, _), + [80] = PINGROUP(80, qup2_se0, ibi_i3c, mdp0_vsync3, _, _, _, _, _, _), + [81] = PINGROUP(81, qup2_se0, ibi_i3c, mdp0_vsync4, _, _, _, _, _, _), + [82] = PINGROUP(82, qup2_se0, mdp_vsync, gcc_gp1, _, _, _, _, _, _), + [83] = PINGROUP(83, qup2_se0, mdp_vsync, gcc_gp2, _, _, _, _, _, _), + [84] = PINGROUP(84, qup2_se1, qup2_se5, ibi_i3c, mdp_vsync, gcc_gp3, _, _, _, _), + [85] = PINGROUP(85, qup2_se1, qup2_se5, ibi_i3c, _, _, _, _, _, _), + [86] = PINGROUP(86, qup2_se2, jitter_bist, atest_usb2, ddr_pxi2, _, _, _, _, _), + [87] = PINGROUP(87, qup2_se2, pll_clk, atest_usb2, ddr_pxi3, _, _, _, _, _), + [88] = PINGROUP(88, qup2_se2, _, atest_usb2, ddr_pxi3, _, _, _, _, _), + [89] = PINGROUP(89, qup2_se2, _, atest_usb2, ddr_pxi4, atest_char, _, _, _, _), + [90] = PINGROUP(90, qup2_se2, _, atest_usb2, ddr_pxi4, atest_char, _, _, _, _), + [91] = PINGROUP(91, qup2_se3, mdp0_vsync5, _, atest_usb2, _, _, _, _, _), + [92] = PINGROUP(92, qup2_se3, mdp0_vsync6, _, atest_usb2, _, _, _, _, _), + [93] = PINGROUP(93, qup2_se3, mdp0_vsync7, _, atest_usb2, _, _, _, _, _), + [94] = PINGROUP(94, qup2_se3, mdp0_vsync8, _, atest_usb2, _, _, _, _, _), + [95] = PINGROUP(95, qup2_se4, qup2_se6, _, atest_usb2, _, _, _, _, _), + [96] = PINGROUP(96, qup2_se4, qup2_se6, _, atest_usb2, _, _, _, _, _), + [97] = PINGROUP(97, qup2_se6, qup2_se4, cri_trng0, _, atest_usb2, _, _, _, _), + [98] = PINGROUP(98, qup2_se6, qup2_se4, phase_flag, cri_trng1, _, _, _, _, _), + [99] = PINGROUP(99, qup2_se5, qup2_se1, phase_flag, cri_trng, _, _, _, _, _), + [100] = PINGROUP(100, qup2_se5, qup2_se1, _, _, _, _, _, _, _), + [101] = PINGROUP(101, edp0_hot, prng_rosc0, tsense_pwm4, _, _, _, _, _, _), + [102] = PINGROUP(102, edp1_hot, prng_rosc1, tsense_pwm3, _, _, _, _, _, _), + [103] = PINGROUP(103, edp3_hot, prng_rosc2, tsense_pwm2, _, _, _, _, _, _), + [104] = PINGROUP(104, edp2_hot, prng_rosc3, tsense_pwm1, _, _, _, _, _, _), + [105] = PINGROUP(105, mi2s_mclk0, _, qdss_gpio, atest_usb2, _, _, _, _, _), + [106] = PINGROUP(106, mi2s1_sck, phase_flag, _, qdss_gpio, _, _, _, _, _), + [107] = PINGROUP(107, mi2s1_ws, phase_flag, _, qdss_gpio, _, _, _, _, _), + [108] = PINGROUP(108, mi2s1_data0, phase_flag, _, qdss_gpio, _, _, _, _, _), + [109] = PINGROUP(109, mi2s1_data1, phase_flag, _, qdss_gpio, _, _, _, _, _), + [110] = PINGROUP(110, mi2s2_sck, phase_flag, _, qdss_gpio, _, _, _, _, _), + [111] = PINGROUP(111, mi2s2_ws, phase_flag, _, qdss_gpio, vsense_trigger, _, _, _, _), + [112] = PINGROUP(112, mi2s2_data0, phase_flag, _, qdss_gpio, _, _, _, _, _), + [113] = PINGROUP(113, mi2s2_data1, audio_ref, phase_flag, _, qdss_gpio, _, _, _, _), + [114] = PINGROUP(114, hs0_mi2s, pll_bist, phase_flag, _, qdss_gpio, _, _, _, _), + [115] = PINGROUP(115, hs0_mi2s, _, qdss_gpio, _, _, _, _, _, _), + [116] = PINGROUP(116, hs0_mi2s, _, qdss_gpio, _, _, _, _, _, _), + [117] = PINGROUP(117, hs0_mi2s, mi2s_mclk1, _, qdss_gpio, _, _, _, _, _), + [118] = PINGROUP(118, hs1_mi2s, _, qdss_gpio, ddr_pxi5, _, _, _, _, _), + [119] = PINGROUP(119, hs1_mi2s, _, qdss_gpio, ddr_pxi5, _, _, _, _, _), + [120] = PINGROUP(120, hs1_mi2s, phase_flag, _, qdss_gpio, _, _, _, _, _), + [121] = PINGROUP(121, hs1_mi2s, phase_flag, _, qdss_gpio, _, _, _, _, _), + [122] = PINGROUP(122, hs2_mi2s, phase_flag, _, qdss_gpio, _, _, _, _, _), + [123] = PINGROUP(123, hs2_mi2s, phase_flag, _, _, _, _, _, _, _), + [124] = PINGROUP(124, hs2_mi2s, phase_flag, _, _, _, _, _, _, _), + [125] = PINGROUP(125, hs2_mi2s, phase_flag, _, _, _, _, _, _, _), + [126] = PINGROUP(126, _, _, _, _, _, _, _, _, _), + [127] = PINGROUP(127, _, _, _, _, _, _, _, _, _), + [128] = PINGROUP(128, _, _, _, _, _, _, _, _, _), + [129] = PINGROUP(129, _, _, _, _, _, _, _, _, _), + [130] = PINGROUP(130, _, _, _, _, _, _, _, _, _), + [131] = PINGROUP(131, _, _, _, _, _, _, _, _, _), + [132] = PINGROUP(132, _, _, _, _, _, _, _, _, _), + [133] = PINGROUP(133, _, _, _, _, _, _, _, _, _), + [134] = PINGROUP(134, _, _, _, _, _, _, _, _, _), + [135] = PINGROUP(135, _, _, _, _, _, _, _, _, _), + [136] = PINGROUP(136, _, _, _, _, _, _, _, _, _), + [137] = PINGROUP(137, _, _, _, _, _, _, _, _, _), + [138] = PINGROUP(138, _, _, _, _, _, _, _, _, _), + [139] = PINGROUP(139, _, _, _, _, _, _, _, _, _), + [140] = PINGROUP(140, _, _, _, _, _, _, _, _, _), + [141] = PINGROUP(141, _, _, _, _, _, _, _, _, _), + [142] = PINGROUP(142, _, _, _, _, _, _, _, _, _), + [143] = PINGROUP(143, _, _, _, _, _, _, _, _, _), + [144] = PINGROUP(144, dbg_out, _, _, _, _, _, _, _, _), + [145] = PINGROUP(145, _, _, _, _, _, _, _, _, _), + [146] = PINGROUP(146, _, _, _, _, _, _, _, _, _), + [147] = PINGROUP(147, _, _, _, _, _, _, _, _, _), + [148] = PINGROUP(148, _, _, _, _, _, _, _, _, _), + [149] = UFS_RESET(ufs_reset, 0x1a2000), + [150] = SDC_QDSD_PINGROUP(sdc1_rclk, 0x199000, 15, 0), + [151] = SDC_QDSD_PINGROUP(sdc1_clk, 0x199000, 13, 6), + [152] = SDC_QDSD_PINGROUP(sdc1_cmd, 0x199000, 11, 3), + [153] = SDC_QDSD_PINGROUP(sdc1_data, 0x199000, 9, 0), +}; + +static const struct msm_gpio_wakeirq_map sa8775p_pdc_map[] = { + { 0, 169 }, { 1, 174 }, { 2, 170 }, { 3, 175 }, { 4, 171 }, { 5, 173 }, + { 6, 172 }, { 7, 182 }, { 10, 220 }, { 11, 213 }, { 12, 221 }, + { 16, 230 }, { 19, 231 }, { 20, 232 }, { 23, 233 }, { 24, 234 }, + { 26, 223 }, { 27, 235 }, { 28, 209 }, { 29, 176 }, { 30, 200 }, + { 31, 201 }, { 32, 212 }, { 35, 177 }, { 36, 178 }, { 39, 184 }, + { 40, 185 }, { 41, 227 }, { 42, 186 }, { 43, 228 }, { 45, 187 }, + { 47, 188 }, { 48, 194 }, { 51, 195 }, { 52, 196 }, { 55, 197 }, + { 56, 198 }, { 57, 236 }, { 58, 192 }, { 59, 193 }, { 72, 179 }, + { 73, 180 }, { 74, 181 }, { 75, 202 }, { 76, 183 }, { 77, 189 }, + { 78, 190 }, { 79, 191 }, { 80, 199 }, { 83, 204 }, { 84, 205 }, + { 85, 229 }, { 86, 206 }, { 89, 207 }, { 91, 208 }, { 94, 214 }, + { 95, 215 }, { 96, 237 }, { 97, 216 }, { 98, 238 }, { 99, 217 }, + { 100, 239 }, { 105, 219 }, { 106, 210 }, { 107, 211 }, { 108, 222 }, + { 109, 203 }, { 145, 225 }, { 146, 226 }, +}; + +static const struct msm_pinctrl_soc_data sa8775p_pinctrl = { + .pins = sa8775p_pins, + .npins = ARRAY_SIZE(sa8775p_pins), + .functions = sa8775p_functions, + .nfunctions = ARRAY_SIZE(sa8775p_functions), + .groups = sa8775p_groups, + .ngroups = ARRAY_SIZE(sa8775p_groups), + .ngpios = 150, + .wakeirq_map = sa8775p_pdc_map, + .nwakeirq_map = ARRAY_SIZE(sa8775p_pdc_map), +}; + +static int sa8775p_pinctrl_probe(struct platform_device *pdev) +{ + return msm_pinctrl_probe(pdev, &sa8775p_pinctrl); +} + +static const struct of_device_id sa8775p_pinctrl_of_match[] = { + { .compatible = "qcom,sa8775p-tlmm", }, + { }, +}; +MODULE_DEVICE_TABLE(of, sa8775p_pinctrl_of_match); + +static struct platform_driver sa8775p_pinctrl_driver = { + .driver = { + .name = "sa8775p-tlmm", + .of_match_table = sa8775p_pinctrl_of_match, + }, + .probe = sa8775p_pinctrl_probe, + .remove = msm_pinctrl_remove, +}; + +static int __init sa8775p_pinctrl_init(void) +{ + return platform_driver_register(&sa8775p_pinctrl_driver); +} +arch_initcall(sa8775p_pinctrl_init); + +static void __exit sa8775p_pinctrl_exit(void) +{ + platform_driver_unregister(&sa8775p_pinctrl_driver); +} +module_exit(sa8775p_pinctrl_exit); + +MODULE_DESCRIPTION("QTI SA8775P pinctrl driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/pinctrl/qcom/pinctrl-sc7180.c b/drivers/pinctrl/qcom/pinctrl-sc7180.c new file mode 100644 index 0000000000..6eb0c73791 --- /dev/null +++ b/drivers/pinctrl/qcom/pinctrl-sc7180.c @@ -0,0 +1,1179 @@ +// SPDX-License-Identifier: GPL-2.0 +// Copyright (c) 2019, The Linux Foundation. All rights reserved. + +#include <linux/module.h> +#include <linux/of.h> +#include <linux/platform_device.h> + +#include "pinctrl-msm.h" + +static const char * const sc7180_tiles[] = { + "north", + "south", + "west", +}; + +enum { + NORTH, + SOUTH, + WEST +}; + +#define PINGROUP(id, _tile, f1, f2, f3, f4, f5, f6, f7, f8, f9) \ + { \ + .grp = PINCTRL_PINGROUP("gpio" #id, \ + gpio##id##_pins, \ + ARRAY_SIZE(gpio##id##_pins)), \ + .funcs = (int[]){ \ + msm_mux_gpio, /* gpio mode */ \ + msm_mux_##f1, \ + msm_mux_##f2, \ + msm_mux_##f3, \ + msm_mux_##f4, \ + msm_mux_##f5, \ + msm_mux_##f6, \ + msm_mux_##f7, \ + msm_mux_##f8, \ + msm_mux_##f9 \ + }, \ + .nfuncs = 10, \ + .ctl_reg = 0x1000 * id, \ + .io_reg = 0x1000 * id + 0x4, \ + .intr_cfg_reg = 0x1000 * id + 0x8, \ + .intr_status_reg = 0x1000 * id + 0xc, \ + .intr_target_reg = 0x1000 * id + 0x8, \ + .tile = _tile, \ + .mux_bit = 2, \ + .pull_bit = 0, \ + .drv_bit = 6, \ + .oe_bit = 9, \ + .in_bit = 0, \ + .out_bit = 1, \ + .intr_enable_bit = 0, \ + .intr_status_bit = 0, \ + .intr_target_bit = 5, \ + .intr_target_kpss_val = 3, \ + .intr_raw_status_bit = 4, \ + .intr_polarity_bit = 1, \ + .intr_detection_bit = 2, \ + .intr_detection_width = 2, \ + } + +#define SDC_QDSD_PINGROUP(pg_name, ctl, pull, drv) \ + { \ + .grp = PINCTRL_PINGROUP(#pg_name, \ + pg_name##_pins, \ + ARRAY_SIZE(pg_name##_pins)), \ + .ctl_reg = ctl, \ + .io_reg = 0, \ + .intr_cfg_reg = 0, \ + .intr_status_reg = 0, \ + .intr_target_reg = 0, \ + .tile = SOUTH, \ + .mux_bit = -1, \ + .pull_bit = pull, \ + .drv_bit = drv, \ + .oe_bit = -1, \ + .in_bit = -1, \ + .out_bit = -1, \ + .intr_enable_bit = -1, \ + .intr_status_bit = -1, \ + .intr_target_bit = -1, \ + .intr_raw_status_bit = -1, \ + .intr_polarity_bit = -1, \ + .intr_detection_bit = -1, \ + .intr_detection_width = -1, \ + } + +#define UFS_RESET(pg_name, offset) \ + { \ + .grp = PINCTRL_PINGROUP(#pg_name, \ + pg_name##_pins, \ + ARRAY_SIZE(pg_name##_pins)), \ + .ctl_reg = offset, \ + .io_reg = offset + 0x4, \ + .intr_cfg_reg = 0, \ + .intr_status_reg = 0, \ + .intr_target_reg = 0, \ + .tile = SOUTH, \ + .mux_bit = -1, \ + .pull_bit = 3, \ + .drv_bit = 0, \ + .oe_bit = -1, \ + .in_bit = -1, \ + .out_bit = 0, \ + .intr_enable_bit = -1, \ + .intr_status_bit = -1, \ + .intr_target_bit = -1, \ + .intr_raw_status_bit = -1, \ + .intr_polarity_bit = -1, \ + .intr_detection_bit = -1, \ + .intr_detection_width = -1, \ + } +static const struct pinctrl_pin_desc sc7180_pins[] = { + PINCTRL_PIN(0, "GPIO_0"), + PINCTRL_PIN(1, "GPIO_1"), + PINCTRL_PIN(2, "GPIO_2"), + PINCTRL_PIN(3, "GPIO_3"), + PINCTRL_PIN(4, "GPIO_4"), + PINCTRL_PIN(5, "GPIO_5"), + PINCTRL_PIN(6, "GPIO_6"), + PINCTRL_PIN(7, "GPIO_7"), + PINCTRL_PIN(8, "GPIO_8"), + PINCTRL_PIN(9, "GPIO_9"), + PINCTRL_PIN(10, "GPIO_10"), + PINCTRL_PIN(11, "GPIO_11"), + PINCTRL_PIN(12, "GPIO_12"), + PINCTRL_PIN(13, "GPIO_13"), + PINCTRL_PIN(14, "GPIO_14"), + PINCTRL_PIN(15, "GPIO_15"), + PINCTRL_PIN(16, "GPIO_16"), + PINCTRL_PIN(17, "GPIO_17"), + PINCTRL_PIN(18, "GPIO_18"), + PINCTRL_PIN(19, "GPIO_19"), + PINCTRL_PIN(20, "GPIO_20"), + PINCTRL_PIN(21, "GPIO_21"), + PINCTRL_PIN(22, "GPIO_22"), + PINCTRL_PIN(23, "GPIO_23"), + PINCTRL_PIN(24, "GPIO_24"), + PINCTRL_PIN(25, "GPIO_25"), + PINCTRL_PIN(26, "GPIO_26"), + PINCTRL_PIN(27, "GPIO_27"), + PINCTRL_PIN(28, "GPIO_28"), + PINCTRL_PIN(29, "GPIO_29"), + PINCTRL_PIN(30, "GPIO_30"), + PINCTRL_PIN(31, "GPIO_31"), + PINCTRL_PIN(32, "GPIO_32"), + PINCTRL_PIN(33, "GPIO_33"), + PINCTRL_PIN(34, "GPIO_34"), + PINCTRL_PIN(35, "GPIO_35"), + PINCTRL_PIN(36, "GPIO_36"), + PINCTRL_PIN(37, "GPIO_37"), + PINCTRL_PIN(38, "GPIO_38"), + PINCTRL_PIN(39, "GPIO_39"), + PINCTRL_PIN(40, "GPIO_40"), + PINCTRL_PIN(41, "GPIO_41"), + PINCTRL_PIN(42, "GPIO_42"), + PINCTRL_PIN(43, "GPIO_43"), + PINCTRL_PIN(44, "GPIO_44"), + PINCTRL_PIN(45, "GPIO_45"), + PINCTRL_PIN(46, "GPIO_46"), + PINCTRL_PIN(47, "GPIO_47"), + PINCTRL_PIN(48, "GPIO_48"), + PINCTRL_PIN(49, "GPIO_49"), + PINCTRL_PIN(50, "GPIO_50"), + PINCTRL_PIN(51, "GPIO_51"), + PINCTRL_PIN(52, "GPIO_52"), + PINCTRL_PIN(53, "GPIO_53"), + PINCTRL_PIN(54, "GPIO_54"), + PINCTRL_PIN(55, "GPIO_55"), + PINCTRL_PIN(56, "GPIO_56"), + PINCTRL_PIN(57, "GPIO_57"), + PINCTRL_PIN(58, "GPIO_58"), + PINCTRL_PIN(59, "GPIO_59"), + PINCTRL_PIN(60, "GPIO_60"), + PINCTRL_PIN(61, "GPIO_61"), + PINCTRL_PIN(62, "GPIO_62"), + PINCTRL_PIN(63, "GPIO_63"), + PINCTRL_PIN(64, "GPIO_64"), + PINCTRL_PIN(65, "GPIO_65"), + PINCTRL_PIN(66, "GPIO_66"), + PINCTRL_PIN(67, "GPIO_67"), + PINCTRL_PIN(68, "GPIO_68"), + PINCTRL_PIN(69, "GPIO_69"), + PINCTRL_PIN(70, "GPIO_70"), + PINCTRL_PIN(71, "GPIO_71"), + PINCTRL_PIN(72, "GPIO_72"), + PINCTRL_PIN(73, "GPIO_73"), + PINCTRL_PIN(74, "GPIO_74"), + PINCTRL_PIN(75, "GPIO_75"), + PINCTRL_PIN(76, "GPIO_76"), + PINCTRL_PIN(77, "GPIO_77"), + PINCTRL_PIN(78, "GPIO_78"), + PINCTRL_PIN(79, "GPIO_79"), + PINCTRL_PIN(80, "GPIO_80"), + PINCTRL_PIN(81, "GPIO_81"), + PINCTRL_PIN(82, "GPIO_82"), + PINCTRL_PIN(83, "GPIO_83"), + PINCTRL_PIN(84, "GPIO_84"), + PINCTRL_PIN(85, "GPIO_85"), + PINCTRL_PIN(86, "GPIO_86"), + PINCTRL_PIN(87, "GPIO_87"), + PINCTRL_PIN(88, "GPIO_88"), + PINCTRL_PIN(89, "GPIO_89"), + PINCTRL_PIN(90, "GPIO_90"), + PINCTRL_PIN(91, "GPIO_91"), + PINCTRL_PIN(92, "GPIO_92"), + PINCTRL_PIN(93, "GPIO_93"), + PINCTRL_PIN(94, "GPIO_94"), + PINCTRL_PIN(95, "GPIO_95"), + PINCTRL_PIN(96, "GPIO_96"), + PINCTRL_PIN(97, "GPIO_97"), + PINCTRL_PIN(98, "GPIO_98"), + PINCTRL_PIN(99, "GPIO_99"), + PINCTRL_PIN(100, "GPIO_100"), + PINCTRL_PIN(101, "GPIO_101"), + PINCTRL_PIN(102, "GPIO_102"), + PINCTRL_PIN(103, "GPIO_103"), + PINCTRL_PIN(104, "GPIO_104"), + PINCTRL_PIN(105, "GPIO_105"), + PINCTRL_PIN(106, "GPIO_106"), + PINCTRL_PIN(107, "GPIO_107"), + PINCTRL_PIN(108, "GPIO_108"), + PINCTRL_PIN(109, "GPIO_109"), + PINCTRL_PIN(110, "GPIO_110"), + PINCTRL_PIN(111, "GPIO_111"), + PINCTRL_PIN(112, "GPIO_112"), + PINCTRL_PIN(113, "GPIO_113"), + PINCTRL_PIN(114, "GPIO_114"), + PINCTRL_PIN(115, "GPIO_115"), + PINCTRL_PIN(116, "GPIO_116"), + PINCTRL_PIN(117, "GPIO_117"), + PINCTRL_PIN(118, "GPIO_118"), + PINCTRL_PIN(119, "UFS_RESET"), + PINCTRL_PIN(120, "SDC1_RCLK"), + PINCTRL_PIN(121, "SDC1_CLK"), + PINCTRL_PIN(122, "SDC1_CMD"), + PINCTRL_PIN(123, "SDC1_DATA"), + PINCTRL_PIN(124, "SDC2_CLK"), + PINCTRL_PIN(125, "SDC2_CMD"), + PINCTRL_PIN(126, "SDC2_DATA"), +}; + +#define DECLARE_MSM_GPIO_PINS(pin) \ + static const unsigned int gpio##pin##_pins[] = { pin } +DECLARE_MSM_GPIO_PINS(0); +DECLARE_MSM_GPIO_PINS(1); +DECLARE_MSM_GPIO_PINS(2); +DECLARE_MSM_GPIO_PINS(3); +DECLARE_MSM_GPIO_PINS(4); +DECLARE_MSM_GPIO_PINS(5); +DECLARE_MSM_GPIO_PINS(6); +DECLARE_MSM_GPIO_PINS(7); +DECLARE_MSM_GPIO_PINS(8); +DECLARE_MSM_GPIO_PINS(9); +DECLARE_MSM_GPIO_PINS(10); +DECLARE_MSM_GPIO_PINS(11); +DECLARE_MSM_GPIO_PINS(12); +DECLARE_MSM_GPIO_PINS(13); +DECLARE_MSM_GPIO_PINS(14); +DECLARE_MSM_GPIO_PINS(15); +DECLARE_MSM_GPIO_PINS(16); +DECLARE_MSM_GPIO_PINS(17); +DECLARE_MSM_GPIO_PINS(18); +DECLARE_MSM_GPIO_PINS(19); +DECLARE_MSM_GPIO_PINS(20); +DECLARE_MSM_GPIO_PINS(21); +DECLARE_MSM_GPIO_PINS(22); +DECLARE_MSM_GPIO_PINS(23); +DECLARE_MSM_GPIO_PINS(24); +DECLARE_MSM_GPIO_PINS(25); +DECLARE_MSM_GPIO_PINS(26); +DECLARE_MSM_GPIO_PINS(27); +DECLARE_MSM_GPIO_PINS(28); +DECLARE_MSM_GPIO_PINS(29); +DECLARE_MSM_GPIO_PINS(30); +DECLARE_MSM_GPIO_PINS(31); +DECLARE_MSM_GPIO_PINS(32); +DECLARE_MSM_GPIO_PINS(33); +DECLARE_MSM_GPIO_PINS(34); +DECLARE_MSM_GPIO_PINS(35); +DECLARE_MSM_GPIO_PINS(36); +DECLARE_MSM_GPIO_PINS(37); +DECLARE_MSM_GPIO_PINS(38); +DECLARE_MSM_GPIO_PINS(39); +DECLARE_MSM_GPIO_PINS(40); +DECLARE_MSM_GPIO_PINS(41); +DECLARE_MSM_GPIO_PINS(42); +DECLARE_MSM_GPIO_PINS(43); +DECLARE_MSM_GPIO_PINS(44); +DECLARE_MSM_GPIO_PINS(45); +DECLARE_MSM_GPIO_PINS(46); +DECLARE_MSM_GPIO_PINS(47); +DECLARE_MSM_GPIO_PINS(48); +DECLARE_MSM_GPIO_PINS(49); +DECLARE_MSM_GPIO_PINS(50); +DECLARE_MSM_GPIO_PINS(51); +DECLARE_MSM_GPIO_PINS(52); +DECLARE_MSM_GPIO_PINS(53); +DECLARE_MSM_GPIO_PINS(54); +DECLARE_MSM_GPIO_PINS(55); +DECLARE_MSM_GPIO_PINS(56); +DECLARE_MSM_GPIO_PINS(57); +DECLARE_MSM_GPIO_PINS(58); +DECLARE_MSM_GPIO_PINS(59); +DECLARE_MSM_GPIO_PINS(60); +DECLARE_MSM_GPIO_PINS(61); +DECLARE_MSM_GPIO_PINS(62); +DECLARE_MSM_GPIO_PINS(63); +DECLARE_MSM_GPIO_PINS(64); +DECLARE_MSM_GPIO_PINS(65); +DECLARE_MSM_GPIO_PINS(66); +DECLARE_MSM_GPIO_PINS(67); +DECLARE_MSM_GPIO_PINS(68); +DECLARE_MSM_GPIO_PINS(69); +DECLARE_MSM_GPIO_PINS(70); +DECLARE_MSM_GPIO_PINS(71); +DECLARE_MSM_GPIO_PINS(72); +DECLARE_MSM_GPIO_PINS(73); +DECLARE_MSM_GPIO_PINS(74); +DECLARE_MSM_GPIO_PINS(75); +DECLARE_MSM_GPIO_PINS(76); +DECLARE_MSM_GPIO_PINS(77); +DECLARE_MSM_GPIO_PINS(78); +DECLARE_MSM_GPIO_PINS(79); +DECLARE_MSM_GPIO_PINS(80); +DECLARE_MSM_GPIO_PINS(81); +DECLARE_MSM_GPIO_PINS(82); +DECLARE_MSM_GPIO_PINS(83); +DECLARE_MSM_GPIO_PINS(84); +DECLARE_MSM_GPIO_PINS(85); +DECLARE_MSM_GPIO_PINS(86); +DECLARE_MSM_GPIO_PINS(87); +DECLARE_MSM_GPIO_PINS(88); +DECLARE_MSM_GPIO_PINS(89); +DECLARE_MSM_GPIO_PINS(90); +DECLARE_MSM_GPIO_PINS(91); +DECLARE_MSM_GPIO_PINS(92); +DECLARE_MSM_GPIO_PINS(93); +DECLARE_MSM_GPIO_PINS(94); +DECLARE_MSM_GPIO_PINS(95); +DECLARE_MSM_GPIO_PINS(96); +DECLARE_MSM_GPIO_PINS(97); +DECLARE_MSM_GPIO_PINS(98); +DECLARE_MSM_GPIO_PINS(99); +DECLARE_MSM_GPIO_PINS(100); +DECLARE_MSM_GPIO_PINS(101); +DECLARE_MSM_GPIO_PINS(102); +DECLARE_MSM_GPIO_PINS(103); +DECLARE_MSM_GPIO_PINS(104); +DECLARE_MSM_GPIO_PINS(105); +DECLARE_MSM_GPIO_PINS(106); +DECLARE_MSM_GPIO_PINS(107); +DECLARE_MSM_GPIO_PINS(108); +DECLARE_MSM_GPIO_PINS(109); +DECLARE_MSM_GPIO_PINS(110); +DECLARE_MSM_GPIO_PINS(111); +DECLARE_MSM_GPIO_PINS(112); +DECLARE_MSM_GPIO_PINS(113); +DECLARE_MSM_GPIO_PINS(114); +DECLARE_MSM_GPIO_PINS(115); +DECLARE_MSM_GPIO_PINS(116); +DECLARE_MSM_GPIO_PINS(117); +DECLARE_MSM_GPIO_PINS(118); + +static const unsigned int ufs_reset_pins[] = { 119 }; +static const unsigned int sdc1_rclk_pins[] = { 120 }; +static const unsigned int sdc1_clk_pins[] = { 121 }; +static const unsigned int sdc1_cmd_pins[] = { 122 }; +static const unsigned int sdc1_data_pins[] = { 123 }; +static const unsigned int sdc2_clk_pins[] = { 124 }; +static const unsigned int sdc2_cmd_pins[] = { 125 }; +static const unsigned int sdc2_data_pins[] = { 126 }; + +enum sc7180_functions { + msm_mux_adsp_ext, + msm_mux_agera_pll, + msm_mux_aoss_cti, + msm_mux_atest_char, + msm_mux_atest_char0, + msm_mux_atest_char1, + msm_mux_atest_char2, + msm_mux_atest_char3, + msm_mux_atest_tsens, + msm_mux_atest_tsens2, + msm_mux_atest_usb1, + msm_mux_atest_usb2, + msm_mux_atest_usb10, + msm_mux_atest_usb11, + msm_mux_atest_usb12, + msm_mux_atest_usb13, + msm_mux_atest_usb20, + msm_mux_atest_usb21, + msm_mux_atest_usb22, + msm_mux_atest_usb23, + msm_mux_audio_ref, + msm_mux_btfm_slimbus, + msm_mux_cam_mclk, + msm_mux_cci_async, + msm_mux_cci_i2c, + msm_mux_cci_timer0, + msm_mux_cci_timer1, + msm_mux_cci_timer2, + msm_mux_cci_timer3, + msm_mux_cci_timer4, + msm_mux_cri_trng, + msm_mux_dbg_out, + msm_mux_ddr_bist, + msm_mux_ddr_pxi0, + msm_mux_ddr_pxi1, + msm_mux_ddr_pxi2, + msm_mux_ddr_pxi3, + msm_mux_dp_hot, + msm_mux_edp_lcd, + msm_mux_gcc_gp1, + msm_mux_gcc_gp2, + msm_mux_gcc_gp3, + msm_mux_gpio, + msm_mux_gp_pdm0, + msm_mux_gp_pdm1, + msm_mux_gp_pdm2, + msm_mux_gps_tx, + msm_mux_jitter_bist, + msm_mux_ldo_en, + msm_mux_ldo_update, + msm_mux_lpass_ext, + msm_mux_mdp_vsync, + msm_mux_mdp_vsync0, + msm_mux_mdp_vsync1, + msm_mux_mdp_vsync2, + msm_mux_mdp_vsync3, + msm_mux_mi2s_1, + msm_mux_mi2s_0, + msm_mux_mi2s_2, + msm_mux_mss_lte, + msm_mux_m_voc, + msm_mux_pa_indicator, + msm_mux_phase_flag, + msm_mux_PLL_BIST, + msm_mux_pll_bypassnl, + msm_mux_pll_reset, + msm_mux_prng_rosc, + msm_mux_qdss, + msm_mux_qdss_cti, + msm_mux_qlink_enable, + msm_mux_qlink_request, + msm_mux_qspi_clk, + msm_mux_qspi_cs, + msm_mux_qspi_data, + msm_mux_qup00, + msm_mux_qup01, + msm_mux_qup02_i2c, + msm_mux_qup02_uart, + msm_mux_qup03, + msm_mux_qup04_i2c, + msm_mux_qup04_uart, + msm_mux_qup05, + msm_mux_qup10, + msm_mux_qup11_i2c, + msm_mux_qup11_uart, + msm_mux_qup12, + msm_mux_qup13_i2c, + msm_mux_qup13_uart, + msm_mux_qup14, + msm_mux_qup15, + msm_mux_sdc1_tb, + msm_mux_sdc2_tb, + msm_mux_sd_write, + msm_mux_sp_cmu, + msm_mux_tgu_ch0, + msm_mux_tgu_ch1, + msm_mux_tgu_ch2, + msm_mux_tgu_ch3, + msm_mux_tsense_pwm1, + msm_mux_tsense_pwm2, + msm_mux_uim1, + msm_mux_uim2, + msm_mux_uim_batt, + msm_mux_usb_phy, + msm_mux_vfr_1, + msm_mux__V_GPIO, + msm_mux__V_PPS_IN, + msm_mux__V_PPS_OUT, + msm_mux_vsense_trigger, + msm_mux_wlan1_adc0, + msm_mux_wlan1_adc1, + msm_mux_wlan2_adc0, + msm_mux_wlan2_adc1, + msm_mux__, +}; + +static const char * const qup01_groups[] = { + "gpio0", "gpio1", "gpio2", "gpio3", "gpio12", "gpio94", +}; +static const char * const gpio_groups[] = { + "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7", + "gpio8", "gpio9", "gpio10", "gpio11", "gpio12", "gpio13", "gpio14", + "gpio15", "gpio16", "gpio17", "gpio18", "gpio19", "gpio20", "gpio21", + "gpio22", "gpio23", "gpio24", "gpio25", "gpio26", "gpio27", "gpio28", + "gpio29", "gpio30", "gpio31", "gpio32", "gpio33", "gpio34", "gpio35", + "gpio36", "gpio37", "gpio38", "gpio39", "gpio40", "gpio41", "gpio42", + "gpio43", "gpio44", "gpio45", "gpio46", "gpio47", "gpio48", "gpio49", + "gpio50", "gpio51", "gpio52", "gpio53", "gpio54", "gpio55", "gpio56", + "gpio57", "gpio58", "gpio59", "gpio60", "gpio61", "gpio62", "gpio63", + "gpio64", "gpio65", "gpio66", "gpio67", "gpio68", "gpio69", "gpio70", + "gpio71", "gpio72", "gpio73", "gpio74", "gpio75", "gpio76", "gpio77", + "gpio78", "gpio79", "gpio80", "gpio81", "gpio82", "gpio83", "gpio84", + "gpio85", "gpio86", "gpio87", "gpio88", "gpio89", "gpio90", "gpio91", + "gpio92", "gpio93", "gpio94", "gpio95", "gpio96", "gpio97", "gpio98", + "gpio99", "gpio100", "gpio101", "gpio102", "gpio103", "gpio104", + "gpio105", "gpio106", "gpio107", "gpio108", "gpio109", "gpio110", + "gpio111", "gpio112", "gpio113", "gpio114", "gpio115", "gpio116", + "gpio117", "gpio118", +}; +static const char * const phase_flag_groups[] = { + "gpio0", "gpio1", "gpio2", "gpio8", "gpio9", + "gpio11", "gpio12", "gpio17", "gpio18", "gpio19", + "gpio20", "gpio25", "gpio26", "gpio27", "gpio28", + "gpio32", "gpio33", "gpio34", "gpio35", "gpio36", + "gpio37", "gpio38", "gpio39", "gpio42", "gpio44", + "gpio56", "gpio57", "gpio58", "gpio63", "gpio64", + "gpio108", "gpio109", +}; +static const char * const cri_trng_groups[] = { + "gpio0", "gpio1", "gpio2", +}; +static const char * const sp_cmu_groups[] = { + "gpio3", +}; +static const char * const dbg_out_groups[] = { + "gpio3", +}; +static const char * const qdss_cti_groups[] = { + "gpio3", "gpio4", "gpio8", "gpio9", "gpio33", "gpio44", "gpio45", + "gpio72", +}; +static const char * const sdc1_tb_groups[] = { + "gpio4", +}; +static const char * const sdc2_tb_groups[] = { + "gpio5", +}; +static const char * const qup11_i2c_groups[] = { + "gpio6", "gpio7", +}; +static const char * const qup11_uart_groups[] = { + "gpio6", "gpio7", +}; +static const char * const ddr_bist_groups[] = { + "gpio7", "gpio8", "gpio9", "gpio10", +}; +static const char * const gp_pdm1_groups[] = { + "gpio8", "gpio50", +}; +static const char * const mdp_vsync_groups[] = { + "gpio10", "gpio11", "gpio12", "gpio70", "gpio71", +}; +static const char * const edp_lcd_groups[] = { + "gpio11", +}; +static const char * const ddr_pxi2_groups[] = { + "gpio11", "gpio26", +}; +static const char * const m_voc_groups[] = { + "gpio12", +}; +static const char * const wlan2_adc0_groups[] = { + "gpio12", +}; +static const char * const atest_usb10_groups[] = { + "gpio12", +}; +static const char * const ddr_pxi3_groups[] = { + "gpio12", "gpio108", +}; +static const char * const cam_mclk_groups[] = { + "gpio13", "gpio14", "gpio15", "gpio16", "gpio23", +}; +static const char * const pll_bypassnl_groups[] = { + "gpio13", +}; +static const char * const qdss_groups[] = { + "gpio13", "gpio86", "gpio14", "gpio87", + "gpio15", "gpio88", "gpio16", "gpio89", + "gpio17", "gpio90", "gpio18", "gpio91", + "gpio19", "gpio21", "gpio20", "gpio22", + "gpio23", "gpio54", "gpio24", "gpio36", + "gpio25", "gpio57", "gpio26", "gpio31", + "gpio27", "gpio56", "gpio28", "gpio29", + "gpio30", "gpio35", "gpio93", "gpio104", + "gpio34", "gpio53", "gpio37", "gpio55", +}; +static const char * const pll_reset_groups[] = { + "gpio14", +}; +static const char * const qup02_i2c_groups[] = { + "gpio15", "gpio16", +}; +static const char * const qup02_uart_groups[] = { + "gpio15", "gpio16", +}; +static const char * const cci_i2c_groups[] = { + "gpio17", "gpio18", "gpio19", "gpio20", "gpio27", "gpio28", +}; +static const char * const wlan1_adc0_groups[] = { + "gpio17", +}; +static const char * const atest_usb12_groups[] = { + "gpio17", +}; +static const char * const ddr_pxi1_groups[] = { + "gpio17", "gpio44", +}; +static const char * const atest_char_groups[] = { + "gpio17", +}; +static const char * const agera_pll_groups[] = { + "gpio18", +}; +static const char * const vsense_trigger_groups[] = { + "gpio18", +}; +static const char * const ddr_pxi0_groups[] = { + "gpio18", "gpio27", +}; +static const char * const atest_char3_groups[] = { + "gpio18", +}; +static const char * const atest_char2_groups[] = { + "gpio19", +}; +static const char * const atest_char1_groups[] = { + "gpio20", +}; +static const char * const cci_timer0_groups[] = { + "gpio21", +}; +static const char * const gcc_gp2_groups[] = { + "gpio21", +}; +static const char * const atest_char0_groups[] = { + "gpio21", +}; +static const char * const cci_timer1_groups[] = { + "gpio22", +}; +static const char * const gcc_gp3_groups[] = { + "gpio22", +}; +static const char * const cci_timer2_groups[] = { + "gpio23", +}; +static const char * const cci_timer3_groups[] = { + "gpio24", +}; +static const char * const cci_async_groups[] = { + "gpio24", "gpio25", "gpio26", +}; +static const char * const cci_timer4_groups[] = { + "gpio25", +}; +static const char * const qup05_groups[] = { + "gpio25", "gpio26", "gpio27", "gpio28", +}; +static const char * const atest_tsens_groups[] = { + "gpio26", +}; +static const char * const atest_usb11_groups[] = { + "gpio26", +}; +static const char * const PLL_BIST_groups[] = { + "gpio27", +}; +static const char * const sd_write_groups[] = { + "gpio33", +}; +static const char * const qup00_groups[] = { + "gpio34", "gpio35", "gpio36", "gpio37", +}; +static const char * const gp_pdm0_groups[] = { + "gpio37", "gpio68", +}; +static const char * const qup03_groups[] = { + "gpio38", "gpio39", "gpio40", "gpio41", +}; +static const char * const atest_tsens2_groups[] = { + "gpio39", +}; +static const char * const wlan2_adc1_groups[] = { + "gpio39", +}; +static const char * const atest_usb1_groups[] = { + "gpio39", +}; +static const char * const qup12_groups[] = { + "gpio42", "gpio43", "gpio44", "gpio45", +}; +static const char * const wlan1_adc1_groups[] = { + "gpio44", +}; +static const char * const atest_usb13_groups[] = { + "gpio44", +}; +static const char * const qup13_i2c_groups[] = { + "gpio46", "gpio47", +}; +static const char * const qup13_uart_groups[] = { + "gpio46", "gpio47", +}; +static const char * const gcc_gp1_groups[] = { + "gpio48", "gpio56", +}; +static const char * const mi2s_1_groups[] = { + "gpio49", "gpio50", "gpio51", "gpio52", +}; +static const char * const btfm_slimbus_groups[] = { + "gpio49", "gpio50", "gpio51", "gpio52", +}; +static const char * const atest_usb2_groups[] = { + "gpio51", +}; +static const char * const atest_usb23_groups[] = { + "gpio52", +}; +static const char * const mi2s_0_groups[] = { + "gpio53", "gpio54", "gpio55", "gpio56", +}; +static const char * const qup15_groups[] = { + "gpio53", "gpio54", "gpio55", "gpio56", +}; +static const char * const atest_usb22_groups[] = { + "gpio53", +}; +static const char * const atest_usb21_groups[] = { + "gpio54", +}; +static const char * const atest_usb20_groups[] = { + "gpio55", +}; +static const char * const lpass_ext_groups[] = { + "gpio57", "gpio58", +}; +static const char * const audio_ref_groups[] = { + "gpio57", +}; +static const char * const jitter_bist_groups[] = { + "gpio57", +}; +static const char * const gp_pdm2_groups[] = { + "gpio57", +}; +static const char * const qup10_groups[] = { + "gpio59", "gpio60", "gpio61", "gpio62", "gpio68", "gpio72", +}; +static const char * const tgu_ch3_groups[] = { + "gpio62", +}; +static const char * const qspi_clk_groups[] = { + "gpio63", +}; +static const char * const mdp_vsync0_groups[] = { + "gpio63", +}; +static const char * const mi2s_2_groups[] = { + "gpio63", "gpio64", "gpio65", "gpio66", +}; +static const char * const mdp_vsync1_groups[] = { + "gpio63", +}; +static const char * const mdp_vsync2_groups[] = { + "gpio63", +}; +static const char * const mdp_vsync3_groups[] = { + "gpio63", +}; +static const char * const tgu_ch0_groups[] = { + "gpio63", +}; +static const char * const qspi_data_groups[] = { + "gpio64", "gpio65", "gpio66", "gpio67", +}; +static const char * const tgu_ch1_groups[] = { + "gpio64", +}; +static const char * const vfr_1_groups[] = { + "gpio65", +}; +static const char * const tgu_ch2_groups[] = { + "gpio65", +}; +static const char * const qspi_cs_groups[] = { + "gpio68", "gpio72", +}; +static const char * const ldo_en_groups[] = { + "gpio70", +}; +static const char * const ldo_update_groups[] = { + "gpio71", +}; +static const char * const prng_rosc_groups[] = { + "gpio72", +}; +static const char * const uim2_groups[] = { + "gpio75", "gpio76", "gpio77", "gpio78", +}; +static const char * const uim1_groups[] = { + "gpio79", "gpio80", "gpio81", "gpio82", +}; +static const char * const _V_GPIO_groups[] = { + "gpio83", "gpio84", "gpio107", +}; +static const char * const _V_PPS_IN_groups[] = { + "gpio83", "gpio84", "gpio107", +}; +static const char * const _V_PPS_OUT_groups[] = { + "gpio83", "gpio84", "gpio107", +}; +static const char * const gps_tx_groups[] = { + "gpio83", "gpio84", "gpio107", "gpio109", +}; +static const char * const uim_batt_groups[] = { + "gpio85", +}; +static const char * const dp_hot_groups[] = { + "gpio85", "gpio117", +}; +static const char * const aoss_cti_groups[] = { + "gpio85", +}; +static const char * const qup14_groups[] = { + "gpio86", "gpio87", "gpio88", "gpio89", "gpio90", "gpio91", +}; +static const char * const adsp_ext_groups[] = { + "gpio87", +}; +static const char * const tsense_pwm1_groups[] = { + "gpio88", +}; +static const char * const tsense_pwm2_groups[] = { + "gpio88", +}; +static const char * const qlink_request_groups[] = { + "gpio96", +}; +static const char * const qlink_enable_groups[] = { + "gpio97", +}; +static const char * const pa_indicator_groups[] = { + "gpio99", +}; +static const char * const usb_phy_groups[] = { + "gpio104", +}; +static const char * const mss_lte_groups[] = { + "gpio108", "gpio109", +}; +static const char * const qup04_i2c_groups[] = { + "gpio115", "gpio116", +}; +static const char * const qup04_uart_groups[] = { + "gpio115", "gpio116", +}; + +static const struct pinfunction sc7180_functions[] = { + MSM_PIN_FUNCTION(adsp_ext), + MSM_PIN_FUNCTION(agera_pll), + MSM_PIN_FUNCTION(aoss_cti), + MSM_PIN_FUNCTION(atest_char), + MSM_PIN_FUNCTION(atest_char0), + MSM_PIN_FUNCTION(atest_char1), + MSM_PIN_FUNCTION(atest_char2), + MSM_PIN_FUNCTION(atest_char3), + MSM_PIN_FUNCTION(atest_tsens), + MSM_PIN_FUNCTION(atest_tsens2), + MSM_PIN_FUNCTION(atest_usb1), + MSM_PIN_FUNCTION(atest_usb2), + MSM_PIN_FUNCTION(atest_usb10), + MSM_PIN_FUNCTION(atest_usb11), + MSM_PIN_FUNCTION(atest_usb12), + MSM_PIN_FUNCTION(atest_usb13), + MSM_PIN_FUNCTION(atest_usb20), + MSM_PIN_FUNCTION(atest_usb21), + MSM_PIN_FUNCTION(atest_usb22), + MSM_PIN_FUNCTION(atest_usb23), + MSM_PIN_FUNCTION(audio_ref), + MSM_PIN_FUNCTION(btfm_slimbus), + MSM_PIN_FUNCTION(cam_mclk), + MSM_PIN_FUNCTION(cci_async), + MSM_PIN_FUNCTION(cci_i2c), + MSM_PIN_FUNCTION(cci_timer0), + MSM_PIN_FUNCTION(cci_timer1), + MSM_PIN_FUNCTION(cci_timer2), + MSM_PIN_FUNCTION(cci_timer3), + MSM_PIN_FUNCTION(cci_timer4), + MSM_PIN_FUNCTION(cri_trng), + MSM_PIN_FUNCTION(dbg_out), + MSM_PIN_FUNCTION(ddr_bist), + MSM_PIN_FUNCTION(ddr_pxi0), + MSM_PIN_FUNCTION(ddr_pxi1), + MSM_PIN_FUNCTION(ddr_pxi2), + MSM_PIN_FUNCTION(ddr_pxi3), + MSM_PIN_FUNCTION(dp_hot), + MSM_PIN_FUNCTION(edp_lcd), + MSM_PIN_FUNCTION(gcc_gp1), + MSM_PIN_FUNCTION(gcc_gp2), + MSM_PIN_FUNCTION(gcc_gp3), + MSM_PIN_FUNCTION(gpio), + MSM_PIN_FUNCTION(gp_pdm0), + MSM_PIN_FUNCTION(gp_pdm1), + MSM_PIN_FUNCTION(gp_pdm2), + MSM_PIN_FUNCTION(gps_tx), + MSM_PIN_FUNCTION(jitter_bist), + MSM_PIN_FUNCTION(ldo_en), + MSM_PIN_FUNCTION(ldo_update), + MSM_PIN_FUNCTION(lpass_ext), + MSM_PIN_FUNCTION(mdp_vsync), + MSM_PIN_FUNCTION(mdp_vsync0), + MSM_PIN_FUNCTION(mdp_vsync1), + MSM_PIN_FUNCTION(mdp_vsync2), + MSM_PIN_FUNCTION(mdp_vsync3), + MSM_PIN_FUNCTION(mi2s_0), + MSM_PIN_FUNCTION(mi2s_1), + MSM_PIN_FUNCTION(mi2s_2), + MSM_PIN_FUNCTION(mss_lte), + MSM_PIN_FUNCTION(m_voc), + MSM_PIN_FUNCTION(pa_indicator), + MSM_PIN_FUNCTION(phase_flag), + MSM_PIN_FUNCTION(PLL_BIST), + MSM_PIN_FUNCTION(pll_bypassnl), + MSM_PIN_FUNCTION(pll_reset), + MSM_PIN_FUNCTION(prng_rosc), + MSM_PIN_FUNCTION(qdss), + MSM_PIN_FUNCTION(qdss_cti), + MSM_PIN_FUNCTION(qlink_enable), + MSM_PIN_FUNCTION(qlink_request), + MSM_PIN_FUNCTION(qspi_clk), + MSM_PIN_FUNCTION(qspi_cs), + MSM_PIN_FUNCTION(qspi_data), + MSM_PIN_FUNCTION(qup00), + MSM_PIN_FUNCTION(qup01), + MSM_PIN_FUNCTION(qup02_i2c), + MSM_PIN_FUNCTION(qup02_uart), + MSM_PIN_FUNCTION(qup03), + MSM_PIN_FUNCTION(qup04_i2c), + MSM_PIN_FUNCTION(qup04_uart), + MSM_PIN_FUNCTION(qup05), + MSM_PIN_FUNCTION(qup10), + MSM_PIN_FUNCTION(qup11_i2c), + MSM_PIN_FUNCTION(qup11_uart), + MSM_PIN_FUNCTION(qup12), + MSM_PIN_FUNCTION(qup13_i2c), + MSM_PIN_FUNCTION(qup13_uart), + MSM_PIN_FUNCTION(qup14), + MSM_PIN_FUNCTION(qup15), + MSM_PIN_FUNCTION(sdc1_tb), + MSM_PIN_FUNCTION(sdc2_tb), + MSM_PIN_FUNCTION(sd_write), + MSM_PIN_FUNCTION(sp_cmu), + MSM_PIN_FUNCTION(tgu_ch0), + MSM_PIN_FUNCTION(tgu_ch1), + MSM_PIN_FUNCTION(tgu_ch2), + MSM_PIN_FUNCTION(tgu_ch3), + MSM_PIN_FUNCTION(tsense_pwm1), + MSM_PIN_FUNCTION(tsense_pwm2), + MSM_PIN_FUNCTION(uim1), + MSM_PIN_FUNCTION(uim2), + MSM_PIN_FUNCTION(uim_batt), + MSM_PIN_FUNCTION(usb_phy), + MSM_PIN_FUNCTION(vfr_1), + MSM_PIN_FUNCTION(_V_GPIO), + MSM_PIN_FUNCTION(_V_PPS_IN), + MSM_PIN_FUNCTION(_V_PPS_OUT), + MSM_PIN_FUNCTION(vsense_trigger), + MSM_PIN_FUNCTION(wlan1_adc0), + MSM_PIN_FUNCTION(wlan1_adc1), + MSM_PIN_FUNCTION(wlan2_adc0), + MSM_PIN_FUNCTION(wlan2_adc1), +}; + +/* Every pin is maintained as a single group, and missing or non-existing pin + * would be maintained as dummy group to synchronize pin group index with + * pin descriptor registered with pinctrl core. + * Clients would not be able to request these dummy pin groups. + */ +static const struct msm_pingroup sc7180_groups[] = { + [0] = PINGROUP(0, SOUTH, qup01, cri_trng, _, phase_flag, _, _, _, _, _), + [1] = PINGROUP(1, SOUTH, qup01, cri_trng, _, phase_flag, _, _, _, _, _), + [2] = PINGROUP(2, SOUTH, qup01, cri_trng, _, phase_flag, _, _, _, _, _), + [3] = PINGROUP(3, SOUTH, qup01, sp_cmu, dbg_out, qdss_cti, _, _, _, _, _), + [4] = PINGROUP(4, NORTH, sdc1_tb, _, qdss_cti, _, _, _, _, _, _), + [5] = PINGROUP(5, NORTH, sdc2_tb, _, _, _, _, _, _, _, _), + [6] = PINGROUP(6, NORTH, qup11_i2c, qup11_uart, _, _, _, _, _, _, _), + [7] = PINGROUP(7, NORTH, qup11_i2c, qup11_uart, ddr_bist, _, _, _, _, _, _), + [8] = PINGROUP(8, NORTH, gp_pdm1, ddr_bist, _, phase_flag, qdss_cti, _, _, _, _), + [9] = PINGROUP(9, NORTH, ddr_bist, _, phase_flag, qdss_cti, _, _, _, _, _), + [10] = PINGROUP(10, NORTH, mdp_vsync, ddr_bist, _, _, _, _, _, _, _), + [11] = PINGROUP(11, NORTH, mdp_vsync, edp_lcd, _, phase_flag, ddr_pxi2, _, _, _, _), + [12] = PINGROUP(12, SOUTH, mdp_vsync, m_voc, qup01, _, phase_flag, wlan2_adc0, atest_usb10, ddr_pxi3, _), + [13] = PINGROUP(13, SOUTH, cam_mclk, pll_bypassnl, qdss, _, _, _, _, _, _), + [14] = PINGROUP(14, SOUTH, cam_mclk, pll_reset, qdss, _, _, _, _, _, _), + [15] = PINGROUP(15, SOUTH, cam_mclk, qup02_i2c, qup02_uart, qdss, _, _, _, _, _), + [16] = PINGROUP(16, SOUTH, cam_mclk, qup02_i2c, qup02_uart, qdss, _, _, _, _, _), + [17] = PINGROUP(17, SOUTH, cci_i2c, _, phase_flag, qdss, _, wlan1_adc0, atest_usb12, ddr_pxi1, atest_char), + [18] = PINGROUP(18, SOUTH, cci_i2c, agera_pll, _, phase_flag, qdss, vsense_trigger, ddr_pxi0, atest_char3, _), + [19] = PINGROUP(19, SOUTH, cci_i2c, _, phase_flag, qdss, atest_char2, _, _, _, _), + [20] = PINGROUP(20, SOUTH, cci_i2c, _, phase_flag, qdss, atest_char1, _, _, _, _), + [21] = PINGROUP(21, NORTH, cci_timer0, gcc_gp2, _, qdss, atest_char0, _, _, _, _), + [22] = PINGROUP(22, NORTH, cci_timer1, gcc_gp3, _, qdss, _, _, _, _, _), + [23] = PINGROUP(23, SOUTH, cci_timer2, cam_mclk, qdss, _, _, _, _, _, _), + [24] = PINGROUP(24, SOUTH, cci_timer3, cci_async, qdss, _, _, _, _, _, _), + [25] = PINGROUP(25, SOUTH, cci_timer4, cci_async, qup05, _, phase_flag, qdss, _, _, _), + [26] = PINGROUP(26, SOUTH, cci_async, qup05, _, phase_flag, qdss, atest_tsens, atest_usb11, ddr_pxi2, _), + [27] = PINGROUP(27, SOUTH, cci_i2c, qup05, PLL_BIST, _, phase_flag, qdss, ddr_pxi0, _, _), + [28] = PINGROUP(28, SOUTH, cci_i2c, qup05, _, phase_flag, qdss, _, _, _, _), + [29] = PINGROUP(29, NORTH, _, qdss, _, _, _, _, _, _, _), + [30] = PINGROUP(30, SOUTH, qdss, _, _, _, _, _, _, _, _), + [31] = PINGROUP(31, NORTH, _, qdss, _, _, _, _, _, _, _), + [32] = PINGROUP(32, NORTH, _, phase_flag, _, _, _, _, _, _, _), + [33] = PINGROUP(33, NORTH, sd_write, _, phase_flag, qdss_cti, _, _, _, _, _), + [34] = PINGROUP(34, SOUTH, qup00, _, phase_flag, qdss, _, _, _, _, _), + [35] = PINGROUP(35, SOUTH, qup00, _, phase_flag, qdss, _, _, _, _, _), + [36] = PINGROUP(36, SOUTH, qup00, _, phase_flag, qdss, _, _, _, _, _), + [37] = PINGROUP(37, SOUTH, qup00, gp_pdm0, _, phase_flag, qdss, _, _, _, _), + [38] = PINGROUP(38, SOUTH, qup03, _, phase_flag, _, _, _, _, _, _), + [39] = PINGROUP(39, SOUTH, qup03, _, phase_flag, atest_tsens2, wlan2_adc1, atest_usb1, _, _, _), + [40] = PINGROUP(40, SOUTH, qup03, _, _, _, _, _, _, _, _), + [41] = PINGROUP(41, SOUTH, qup03, _, _, _, _, _, _, _, _), + [42] = PINGROUP(42, NORTH, qup12, _, phase_flag, _, _, _, _, _, _), + [43] = PINGROUP(43, NORTH, qup12, _, _, _, _, _, _, _, _), + [44] = PINGROUP(44, NORTH, qup12, _, phase_flag, qdss_cti, wlan1_adc1, atest_usb13, ddr_pxi1, _, _), + [45] = PINGROUP(45, NORTH, qup12, qdss_cti, _, _, _, _, _, _, _), + [46] = PINGROUP(46, NORTH, qup13_i2c, qup13_uart, _, _, _, _, _, _, _), + [47] = PINGROUP(47, NORTH, qup13_i2c, qup13_uart, _, _, _, _, _, _, _), + [48] = PINGROUP(48, NORTH, gcc_gp1, _, _, _, _, _, _, _, _), + [49] = PINGROUP(49, WEST, mi2s_1, btfm_slimbus, _, _, _, _, _, _, _), + [50] = PINGROUP(50, WEST, mi2s_1, btfm_slimbus, gp_pdm1, _, _, _, _, _, _), + [51] = PINGROUP(51, WEST, mi2s_1, btfm_slimbus, atest_usb2, _, _, _, _, _, _), + [52] = PINGROUP(52, WEST, mi2s_1, btfm_slimbus, atest_usb23, _, _, _, _, _, _), + [53] = PINGROUP(53, WEST, mi2s_0, qup15, qdss, atest_usb22, _, _, _, _, _), + [54] = PINGROUP(54, WEST, mi2s_0, qup15, qdss, atest_usb21, _, _, _, _, _), + [55] = PINGROUP(55, WEST, mi2s_0, qup15, qdss, atest_usb20, _, _, _, _, _), + [56] = PINGROUP(56, WEST, mi2s_0, qup15, gcc_gp1, _, phase_flag, qdss, _, _, _), + [57] = PINGROUP(57, WEST, lpass_ext, audio_ref, jitter_bist, gp_pdm2, _, phase_flag, qdss, _, _), + [58] = PINGROUP(58, WEST, lpass_ext, _, phase_flag, _, _, _, _, _, _), + [59] = PINGROUP(59, NORTH, qup10, _, _, _, _, _, _, _, _), + [60] = PINGROUP(60, NORTH, qup10, _, _, _, _, _, _, _, _), + [61] = PINGROUP(61, NORTH, qup10, _, _, _, _, _, _, _, _), + [62] = PINGROUP(62, NORTH, qup10, tgu_ch3, _, _, _, _, _, _, _), + [63] = PINGROUP(63, NORTH, qspi_clk, mdp_vsync0, mi2s_2, mdp_vsync1, mdp_vsync2, mdp_vsync3, tgu_ch0, _, phase_flag), + [64] = PINGROUP(64, NORTH, qspi_data, mi2s_2, tgu_ch1, _, phase_flag, _, _, _, _), + [65] = PINGROUP(65, NORTH, qspi_data, mi2s_2, vfr_1, tgu_ch2, _, _, _, _, _), + [66] = PINGROUP(66, NORTH, qspi_data, mi2s_2, _, _, _, _, _, _, _), + [67] = PINGROUP(67, NORTH, qspi_data, _, _, _, _, _, _, _, _), + [68] = PINGROUP(68, NORTH, qspi_cs, qup10, gp_pdm0, _, _, _, _, _, _), + [69] = PINGROUP(69, WEST, _, _, _, _, _, _, _, _, _), + [70] = PINGROUP(70, NORTH, _, _, mdp_vsync, ldo_en, _, _, _, _, _), + [71] = PINGROUP(71, NORTH, _, mdp_vsync, ldo_update, _, _, _, _, _, _), + [72] = PINGROUP(72, NORTH, qspi_cs, qup10, prng_rosc, _, qdss_cti, _, _, _, _), + [73] = PINGROUP(73, WEST, _, _, _, _, _, _, _, _, _), + [74] = PINGROUP(74, WEST, _, _, _, _, _, _, _, _, _), + [75] = PINGROUP(75, WEST, uim2, _, _, _, _, _, _, _, _), + [76] = PINGROUP(76, WEST, uim2, _, _, _, _, _, _, _, _), + [77] = PINGROUP(77, WEST, uim2, _, _, _, _, _, _, _, _), + [78] = PINGROUP(78, WEST, uim2, _, _, _, _, _, _, _, _), + [79] = PINGROUP(79, WEST, uim1, _, _, _, _, _, _, _, _), + [80] = PINGROUP(80, WEST, uim1, _, _, _, _, _, _, _, _), + [81] = PINGROUP(81, WEST, uim1, _, _, _, _, _, _, _, _), + [82] = PINGROUP(82, WEST, uim1, _, _, _, _, _, _, _, _), + [83] = PINGROUP(83, WEST, _, _V_GPIO, _V_PPS_IN, _V_PPS_OUT, gps_tx, _, _, _, _), + [84] = PINGROUP(84, WEST, _, _V_GPIO, _V_PPS_IN, _V_PPS_OUT, gps_tx, _, _, _, _), + [85] = PINGROUP(85, WEST, uim_batt, dp_hot, aoss_cti, _, _, _, _, _, _), + [86] = PINGROUP(86, NORTH, qup14, qdss, _, _, _, _, _, _, _), + [87] = PINGROUP(87, NORTH, qup14, adsp_ext, qdss, _, _, _, _, _, _), + [88] = PINGROUP(88, NORTH, qup14, qdss, tsense_pwm1, tsense_pwm2, _, _, _, _, _), + [89] = PINGROUP(89, NORTH, qup14, qdss, _, _, _, _, _, _, _), + [90] = PINGROUP(90, NORTH, qup14, qdss, _, _, _, _, _, _, _), + [91] = PINGROUP(91, NORTH, qup14, qdss, _, _, _, _, _, _, _), + [92] = PINGROUP(92, NORTH, _, _, _, _, _, _, _, _, _), + [93] = PINGROUP(93, NORTH, qdss, _, _, _, _, _, _, _, _), + [94] = PINGROUP(94, SOUTH, qup01, _, _, _, _, _, _, _, _), + [95] = PINGROUP(95, WEST, _, _, _, _, _, _, _, _, _), + [96] = PINGROUP(96, WEST, qlink_request, _, _, _, _, _, _, _, _), + [97] = PINGROUP(97, WEST, qlink_enable, _, _, _, _, _, _, _, _), + [98] = PINGROUP(98, WEST, _, _, _, _, _, _, _, _, _), + [99] = PINGROUP(99, WEST, _, pa_indicator, _, _, _, _, _, _, _), + [100] = PINGROUP(100, WEST, _, _, _, _, _, _, _, _, _), + [101] = PINGROUP(101, NORTH, _, _, _, _, _, _, _, _, _), + [102] = PINGROUP(102, NORTH, _, _, _, _, _, _, _, _, _), + [103] = PINGROUP(103, NORTH, _, _, _, _, _, _, _, _, _), + [104] = PINGROUP(104, WEST, usb_phy, _, qdss, _, _, _, _, _, _), + [105] = PINGROUP(105, NORTH, _, _, _, _, _, _, _, _, _), + [106] = PINGROUP(106, NORTH, _, _, _, _, _, _, _, _, _), + [107] = PINGROUP(107, WEST, _, _V_GPIO, _V_PPS_IN, _V_PPS_OUT, gps_tx, _, _, _, _), + [108] = PINGROUP(108, SOUTH, mss_lte, _, phase_flag, ddr_pxi3, _, _, _, _, _), + [109] = PINGROUP(109, SOUTH, mss_lte, gps_tx, _, phase_flag, _, _, _, _, _), + [110] = PINGROUP(110, NORTH, _, _, _, _, _, _, _, _, _), + [111] = PINGROUP(111, NORTH, _, _, _, _, _, _, _, _, _), + [112] = PINGROUP(112, NORTH, _, _, _, _, _, _, _, _, _), + [113] = PINGROUP(113, NORTH, _, _, _, _, _, _, _, _, _), + [114] = PINGROUP(114, NORTH, _, _, _, _, _, _, _, _, _), + [115] = PINGROUP(115, WEST, qup04_i2c, qup04_uart, _, _, _, _, _, _, _), + [116] = PINGROUP(116, WEST, qup04_i2c, qup04_uart, _, _, _, _, _, _, _), + [117] = PINGROUP(117, WEST, dp_hot, _, _, _, _, _, _, _, _), + [118] = PINGROUP(118, WEST, _, _, _, _, _, _, _, _, _), + [119] = UFS_RESET(ufs_reset, 0x7f000), + [120] = SDC_QDSD_PINGROUP(sdc1_rclk, 0x7a000, 15, 0), + [121] = SDC_QDSD_PINGROUP(sdc1_clk, 0x7a000, 13, 6), + [122] = SDC_QDSD_PINGROUP(sdc1_cmd, 0x7a000, 11, 3), + [123] = SDC_QDSD_PINGROUP(sdc1_data, 0x7a000, 9, 0), + [124] = SDC_QDSD_PINGROUP(sdc2_clk, 0x7b000, 14, 6), + [125] = SDC_QDSD_PINGROUP(sdc2_cmd, 0x7b000, 11, 3), + [126] = SDC_QDSD_PINGROUP(sdc2_data, 0x7b000, 9, 0), +}; + +static const struct msm_gpio_wakeirq_map sc7180_pdc_map[] = { + {0, 40}, {3, 50}, {4, 42}, {5, 70}, {6, 41}, {9, 35}, + {10, 80}, {11, 51}, {16, 20}, {21, 55}, {22, 90}, {23, 21}, + {24, 61}, {26, 52}, {28, 36}, {30, 100}, {31, 33}, {32, 81}, + {33, 62}, {34, 43}, {36, 91}, {37, 53}, {38, 63}, {39, 72}, + {41, 101}, {42, 7}, {43, 34}, {45, 73}, {47, 82}, {49, 17}, + {52, 109}, {53, 102}, {55, 92}, {56, 56}, {57, 57}, {58, 83}, + {59, 37}, {62, 110}, {63, 111}, {64, 74}, {65, 44}, {66, 93}, + {67, 58}, {68, 112}, {69, 32}, {70, 54}, {72, 59}, {73, 64}, + {74, 71}, {78, 31}, {82, 30}, {85, 103}, {86, 38}, {87, 39}, + {88, 45}, {89, 46}, {90, 47}, {91, 48}, {92, 60}, {93, 49}, + {94, 84}, {95, 94}, {98, 65}, {101, 66}, {104, 67}, {109, 104}, + {110, 68}, {113, 69}, {114, 113}, {115, 108}, {116, 121}, + {117, 114}, {118, 119}, +}; + +static const struct msm_pinctrl_soc_data sc7180_pinctrl = { + .pins = sc7180_pins, + .npins = ARRAY_SIZE(sc7180_pins), + .functions = sc7180_functions, + .nfunctions = ARRAY_SIZE(sc7180_functions), + .groups = sc7180_groups, + .ngroups = ARRAY_SIZE(sc7180_groups), + .ngpios = 120, + .tiles = sc7180_tiles, + .ntiles = ARRAY_SIZE(sc7180_tiles), + .wakeirq_map = sc7180_pdc_map, + .nwakeirq_map = ARRAY_SIZE(sc7180_pdc_map), + .wakeirq_dual_edge_errata = true, +}; + +static int sc7180_pinctrl_probe(struct platform_device *pdev) +{ + return msm_pinctrl_probe(pdev, &sc7180_pinctrl); +} + +static const struct of_device_id sc7180_pinctrl_of_match[] = { + { .compatible = "qcom,sc7180-pinctrl", }, + { }, +}; + +static struct platform_driver sc7180_pinctrl_driver = { + .driver = { + .name = "sc7180-pinctrl", + .pm = &msm_pinctrl_dev_pm_ops, + .of_match_table = sc7180_pinctrl_of_match, + }, + .probe = sc7180_pinctrl_probe, + .remove = msm_pinctrl_remove, +}; + +static int __init sc7180_pinctrl_init(void) +{ + return platform_driver_register(&sc7180_pinctrl_driver); +} +arch_initcall(sc7180_pinctrl_init); + +static void __exit sc7180_pinctrl_exit(void) +{ + platform_driver_unregister(&sc7180_pinctrl_driver); +} +module_exit(sc7180_pinctrl_exit); + +MODULE_DESCRIPTION("QTI sc7180 pinctrl driver"); +MODULE_LICENSE("GPL v2"); +MODULE_DEVICE_TABLE(of, sc7180_pinctrl_of_match); diff --git a/drivers/pinctrl/qcom/pinctrl-sc7280-lpass-lpi.c b/drivers/pinctrl/qcom/pinctrl-sc7280-lpass-lpi.c new file mode 100644 index 0000000000..d615b6c55b --- /dev/null +++ b/drivers/pinctrl/qcom/pinctrl-sc7280-lpass-lpi.c @@ -0,0 +1,166 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved. + * ALSA SoC platform-machine driver for QTi LPASS + */ + +#include <linux/gpio/driver.h> +#include <linux/module.h> +#include <linux/platform_device.h> + +#include "pinctrl-lpass-lpi.h" + +enum lpass_lpi_functions { + LPI_MUX_dmic1_clk, + LPI_MUX_dmic1_data, + LPI_MUX_dmic2_clk, + LPI_MUX_dmic2_data, + LPI_MUX_dmic3_clk, + LPI_MUX_dmic3_data, + LPI_MUX_i2s1_clk, + LPI_MUX_i2s1_data, + LPI_MUX_i2s1_ws, + LPI_MUX_i2s2_clk, + LPI_MUX_i2s2_data, + LPI_MUX_i2s2_ws, + LPI_MUX_qua_mi2s_data, + LPI_MUX_qua_mi2s_sclk, + LPI_MUX_qua_mi2s_ws, + LPI_MUX_swr_rx_clk, + LPI_MUX_swr_rx_data, + LPI_MUX_swr_tx_clk, + LPI_MUX_swr_tx_data, + LPI_MUX_wsa_swr_clk, + LPI_MUX_wsa_swr_data, + LPI_MUX_gpio, + LPI_MUX__, +}; + +static int gpio0_pins[] = { 0 }; +static int gpio1_pins[] = { 1 }; +static int gpio2_pins[] = { 2 }; +static int gpio3_pins[] = { 3 }; +static int gpio4_pins[] = { 4 }; +static int gpio5_pins[] = { 5 }; +static int gpio6_pins[] = { 6 }; +static int gpio7_pins[] = { 7 }; +static int gpio8_pins[] = { 8 }; +static int gpio9_pins[] = { 9 }; +static int gpio10_pins[] = { 10 }; +static int gpio11_pins[] = { 11 }; +static int gpio12_pins[] = { 12 }; +static int gpio13_pins[] = { 13 }; +static int gpio14_pins[] = { 14 }; + +static const struct pinctrl_pin_desc sc7280_lpi_pins[] = { + PINCTRL_PIN(0, "gpio0"), + PINCTRL_PIN(1, "gpio1"), + PINCTRL_PIN(2, "gpio2"), + PINCTRL_PIN(3, "gpio3"), + PINCTRL_PIN(4, "gpio4"), + PINCTRL_PIN(5, "gpio5"), + PINCTRL_PIN(6, "gpio6"), + PINCTRL_PIN(7, "gpio7"), + PINCTRL_PIN(8, "gpio8"), + PINCTRL_PIN(9, "gpio9"), + PINCTRL_PIN(10, "gpio10"), + PINCTRL_PIN(11, "gpio11"), + PINCTRL_PIN(12, "gpio12"), + PINCTRL_PIN(13, "gpio13"), + PINCTRL_PIN(14, "gpio14"), +}; + +static const char * const swr_tx_clk_groups[] = { "gpio0" }; +static const char * const swr_tx_data_groups[] = { "gpio1", "gpio2", "gpio14" }; +static const char * const swr_rx_clk_groups[] = { "gpio3" }; +static const char * const swr_rx_data_groups[] = { "gpio4", "gpio5" }; +static const char * const dmic1_clk_groups[] = { "gpio6" }; +static const char * const dmic1_data_groups[] = { "gpio7" }; +static const char * const dmic2_clk_groups[] = { "gpio8" }; +static const char * const dmic2_data_groups[] = { "gpio9" }; +static const char * const i2s2_clk_groups[] = { "gpio10" }; +static const char * const i2s2_ws_groups[] = { "gpio11" }; +static const char * const dmic3_clk_groups[] = { "gpio12" }; +static const char * const dmic3_data_groups[] = { "gpio13" }; +static const char * const qua_mi2s_sclk_groups[] = { "gpio0" }; +static const char * const qua_mi2s_ws_groups[] = { "gpio1" }; +static const char * const qua_mi2s_data_groups[] = { "gpio2", "gpio3", "gpio4" }; +static const char * const i2s1_clk_groups[] = { "gpio6" }; +static const char * const i2s1_ws_groups[] = { "gpio7" }; +static const char * const i2s1_data_groups[] = { "gpio8", "gpio9" }; +static const char * const wsa_swr_clk_groups[] = { "gpio10" }; +static const char * const wsa_swr_data_groups[] = { "gpio11" }; +static const char * const i2s2_data_groups[] = { "gpio12", "gpio13" }; + +static const struct lpi_pingroup sc7280_groups[] = { + LPI_PINGROUP(0, 0, swr_tx_clk, qua_mi2s_sclk, _, _), + LPI_PINGROUP(1, 2, swr_tx_data, qua_mi2s_ws, _, _), + LPI_PINGROUP(2, 4, swr_tx_data, qua_mi2s_data, _, _), + LPI_PINGROUP(3, 8, swr_rx_clk, qua_mi2s_data, _, _), + LPI_PINGROUP(4, 10, swr_rx_data, qua_mi2s_data, _, _), + LPI_PINGROUP(5, 12, swr_rx_data, _, _, _), + LPI_PINGROUP(6, LPI_NO_SLEW, dmic1_clk, i2s1_clk, _, _), + LPI_PINGROUP(7, LPI_NO_SLEW, dmic1_data, i2s1_ws, _, _), + LPI_PINGROUP(8, LPI_NO_SLEW, dmic2_clk, i2s1_data, _, _), + LPI_PINGROUP(9, LPI_NO_SLEW, dmic2_data, i2s1_data, _, _), + LPI_PINGROUP(10, 16, i2s2_clk, wsa_swr_clk, _, _), + LPI_PINGROUP(11, 18, i2s2_ws, wsa_swr_data, _, _), + LPI_PINGROUP(12, LPI_NO_SLEW, dmic3_clk, i2s2_data, _, _), + LPI_PINGROUP(13, LPI_NO_SLEW, dmic3_data, i2s2_data, _, _), + LPI_PINGROUP(14, 6, swr_tx_data, _, _, _), +}; + +static const struct lpi_function sc7280_functions[] = { + LPI_FUNCTION(dmic1_clk), + LPI_FUNCTION(dmic1_data), + LPI_FUNCTION(dmic2_clk), + LPI_FUNCTION(dmic2_data), + LPI_FUNCTION(dmic3_clk), + LPI_FUNCTION(dmic3_data), + LPI_FUNCTION(i2s1_clk), + LPI_FUNCTION(i2s1_data), + LPI_FUNCTION(i2s1_ws), + LPI_FUNCTION(i2s2_clk), + LPI_FUNCTION(i2s2_data), + LPI_FUNCTION(i2s2_ws), + LPI_FUNCTION(qua_mi2s_data), + LPI_FUNCTION(qua_mi2s_sclk), + LPI_FUNCTION(qua_mi2s_ws), + LPI_FUNCTION(swr_rx_clk), + LPI_FUNCTION(swr_rx_data), + LPI_FUNCTION(swr_tx_clk), + LPI_FUNCTION(swr_tx_data), + LPI_FUNCTION(wsa_swr_clk), + LPI_FUNCTION(wsa_swr_data), +}; + +static const struct lpi_pinctrl_variant_data sc7280_lpi_data = { + .pins = sc7280_lpi_pins, + .npins = ARRAY_SIZE(sc7280_lpi_pins), + .groups = sc7280_groups, + .ngroups = ARRAY_SIZE(sc7280_groups), + .functions = sc7280_functions, + .nfunctions = ARRAY_SIZE(sc7280_functions), +}; + +static const struct of_device_id lpi_pinctrl_of_match[] = { + { + .compatible = "qcom,sc7280-lpass-lpi-pinctrl", + .data = &sc7280_lpi_data, + }, + { } +}; +MODULE_DEVICE_TABLE(of, lpi_pinctrl_of_match); + +static struct platform_driver lpi_pinctrl_driver = { + .driver = { + .name = "qcom-sc7280-lpass-lpi-pinctrl", + .of_match_table = lpi_pinctrl_of_match, + }, + .probe = lpi_pinctrl_probe, + .remove = lpi_pinctrl_remove, +}; + +module_platform_driver(lpi_pinctrl_driver); +MODULE_DESCRIPTION("QTI SC7280 LPI GPIO pin control driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/pinctrl/qcom/pinctrl-sc7280.c b/drivers/pinctrl/qcom/pinctrl-sc7280.c new file mode 100644 index 0000000000..0c10eeb60b --- /dev/null +++ b/drivers/pinctrl/qcom/pinctrl-sc7280.c @@ -0,0 +1,1525 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2020, The Linux Foundation. All rights reserved. + */ + +#include <linux/module.h> +#include <linux/of.h> +#include <linux/platform_device.h> + +#include "pinctrl-msm.h" + +#define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7, f8, f9) \ + { \ + .grp = PINCTRL_PINGROUP("gpio" #id, \ + gpio##id##_pins, \ + ARRAY_SIZE(gpio##id##_pins)), \ + .funcs = (int[]){ \ + msm_mux_gpio, /* gpio mode */ \ + msm_mux_##f1, \ + msm_mux_##f2, \ + msm_mux_##f3, \ + msm_mux_##f4, \ + msm_mux_##f5, \ + msm_mux_##f6, \ + msm_mux_##f7, \ + msm_mux_##f8, \ + msm_mux_##f9 \ + }, \ + .nfuncs = 10, \ + .ctl_reg = 0x1000 * id, \ + .io_reg = 0x1000 * id + 0x4, \ + .intr_cfg_reg = 0x1000 * id + 0x8, \ + .intr_status_reg = 0x1000 * id + 0xc, \ + .intr_target_reg = 0x1000 * id + 0x8, \ + .mux_bit = 2, \ + .pull_bit = 0, \ + .drv_bit = 6, \ + .egpio_enable = 12, \ + .egpio_present = 11, \ + .oe_bit = 9, \ + .in_bit = 0, \ + .out_bit = 1, \ + .intr_enable_bit = 0, \ + .intr_status_bit = 0, \ + .intr_target_bit = 5, \ + .intr_target_kpss_val = 3, \ + .intr_raw_status_bit = 4, \ + .intr_polarity_bit = 1, \ + .intr_detection_bit = 2, \ + .intr_detection_width = 2, \ + } + +#define SDC_QDSD_PINGROUP(pg_name, ctl, pull, drv) \ + { \ + .grp = PINCTRL_PINGROUP(#pg_name, \ + pg_name##_pins, \ + ARRAY_SIZE(pg_name##_pins)), \ + .ctl_reg = ctl, \ + .io_reg = 0, \ + .intr_cfg_reg = 0, \ + .intr_status_reg = 0, \ + .intr_target_reg = 0, \ + .mux_bit = -1, \ + .pull_bit = pull, \ + .drv_bit = drv, \ + .oe_bit = -1, \ + .in_bit = -1, \ + .out_bit = -1, \ + .intr_enable_bit = -1, \ + .intr_status_bit = -1, \ + .intr_target_bit = -1, \ + .intr_raw_status_bit = -1, \ + .intr_polarity_bit = -1, \ + .intr_detection_bit = -1, \ + .intr_detection_width = -1, \ + } + +#define UFS_RESET(pg_name, offset) \ + { \ + .grp = PINCTRL_PINGROUP(#pg_name, \ + pg_name##_pins, \ + ARRAY_SIZE(pg_name##_pins)), \ + .ctl_reg = offset, \ + .io_reg = offset + 0x4, \ + .intr_cfg_reg = 0, \ + .intr_status_reg = 0, \ + .intr_target_reg = 0, \ + .mux_bit = -1, \ + .pull_bit = 3, \ + .drv_bit = 0, \ + .oe_bit = -1, \ + .in_bit = -1, \ + .out_bit = 0, \ + .intr_enable_bit = -1, \ + .intr_status_bit = -1, \ + .intr_target_bit = -1, \ + .intr_raw_status_bit = -1, \ + .intr_polarity_bit = -1, \ + .intr_detection_bit = -1, \ + .intr_detection_width = -1, \ + } + +static const struct pinctrl_pin_desc sc7280_pins[] = { + PINCTRL_PIN(0, "GPIO_0"), + PINCTRL_PIN(1, "GPIO_1"), + PINCTRL_PIN(2, "GPIO_2"), + PINCTRL_PIN(3, "GPIO_3"), + PINCTRL_PIN(4, "GPIO_4"), + PINCTRL_PIN(5, "GPIO_5"), + PINCTRL_PIN(6, "GPIO_6"), + PINCTRL_PIN(7, "GPIO_7"), + PINCTRL_PIN(8, "GPIO_8"), + PINCTRL_PIN(9, "GPIO_9"), + PINCTRL_PIN(10, "GPIO_10"), + PINCTRL_PIN(11, "GPIO_11"), + PINCTRL_PIN(12, "GPIO_12"), + PINCTRL_PIN(13, "GPIO_13"), + PINCTRL_PIN(14, "GPIO_14"), + PINCTRL_PIN(15, "GPIO_15"), + PINCTRL_PIN(16, "GPIO_16"), + PINCTRL_PIN(17, "GPIO_17"), + PINCTRL_PIN(18, "GPIO_18"), + PINCTRL_PIN(19, "GPIO_19"), + PINCTRL_PIN(20, "GPIO_20"), + PINCTRL_PIN(21, "GPIO_21"), + PINCTRL_PIN(22, "GPIO_22"), + PINCTRL_PIN(23, "GPIO_23"), + PINCTRL_PIN(24, "GPIO_24"), + PINCTRL_PIN(25, "GPIO_25"), + PINCTRL_PIN(26, "GPIO_26"), + PINCTRL_PIN(27, "GPIO_27"), + PINCTRL_PIN(28, "GPIO_28"), + PINCTRL_PIN(29, "GPIO_29"), + PINCTRL_PIN(30, "GPIO_30"), + PINCTRL_PIN(31, "GPIO_31"), + PINCTRL_PIN(32, "GPIO_32"), + PINCTRL_PIN(33, "GPIO_33"), + PINCTRL_PIN(34, "GPIO_34"), + PINCTRL_PIN(35, "GPIO_35"), + PINCTRL_PIN(36, "GPIO_36"), + PINCTRL_PIN(37, "GPIO_37"), + PINCTRL_PIN(38, "GPIO_38"), + PINCTRL_PIN(39, "GPIO_39"), + PINCTRL_PIN(40, "GPIO_40"), + PINCTRL_PIN(41, "GPIO_41"), + PINCTRL_PIN(42, "GPIO_42"), + PINCTRL_PIN(43, "GPIO_43"), + PINCTRL_PIN(44, "GPIO_44"), + PINCTRL_PIN(45, "GPIO_45"), + PINCTRL_PIN(46, "GPIO_46"), + PINCTRL_PIN(47, "GPIO_47"), + PINCTRL_PIN(48, "GPIO_48"), + PINCTRL_PIN(49, "GPIO_49"), + PINCTRL_PIN(50, "GPIO_50"), + PINCTRL_PIN(51, "GPIO_51"), + PINCTRL_PIN(52, "GPIO_52"), + PINCTRL_PIN(53, "GPIO_53"), + PINCTRL_PIN(54, "GPIO_54"), + PINCTRL_PIN(55, "GPIO_55"), + PINCTRL_PIN(56, "GPIO_56"), + PINCTRL_PIN(57, "GPIO_57"), + PINCTRL_PIN(58, "GPIO_58"), + PINCTRL_PIN(59, "GPIO_59"), + PINCTRL_PIN(60, "GPIO_60"), + PINCTRL_PIN(61, "GPIO_61"), + PINCTRL_PIN(62, "GPIO_62"), + PINCTRL_PIN(63, "GPIO_63"), + PINCTRL_PIN(64, "GPIO_64"), + PINCTRL_PIN(65, "GPIO_65"), + PINCTRL_PIN(66, "GPIO_66"), + PINCTRL_PIN(67, "GPIO_67"), + PINCTRL_PIN(68, "GPIO_68"), + PINCTRL_PIN(69, "GPIO_69"), + PINCTRL_PIN(70, "GPIO_70"), + PINCTRL_PIN(71, "GPIO_71"), + PINCTRL_PIN(72, "GPIO_72"), + PINCTRL_PIN(73, "GPIO_73"), + PINCTRL_PIN(74, "GPIO_74"), + PINCTRL_PIN(75, "GPIO_75"), + PINCTRL_PIN(76, "GPIO_76"), + PINCTRL_PIN(77, "GPIO_77"), + PINCTRL_PIN(78, "GPIO_78"), + PINCTRL_PIN(79, "GPIO_79"), + PINCTRL_PIN(80, "GPIO_80"), + PINCTRL_PIN(81, "GPIO_81"), + PINCTRL_PIN(82, "GPIO_82"), + PINCTRL_PIN(83, "GPIO_83"), + PINCTRL_PIN(84, "GPIO_84"), + PINCTRL_PIN(85, "GPIO_85"), + PINCTRL_PIN(86, "GPIO_86"), + PINCTRL_PIN(87, "GPIO_87"), + PINCTRL_PIN(88, "GPIO_88"), + PINCTRL_PIN(89, "GPIO_89"), + PINCTRL_PIN(90, "GPIO_90"), + PINCTRL_PIN(91, "GPIO_91"), + PINCTRL_PIN(92, "GPIO_92"), + PINCTRL_PIN(93, "GPIO_93"), + PINCTRL_PIN(94, "GPIO_94"), + PINCTRL_PIN(95, "GPIO_95"), + PINCTRL_PIN(96, "GPIO_96"), + PINCTRL_PIN(97, "GPIO_97"), + PINCTRL_PIN(98, "GPIO_98"), + PINCTRL_PIN(99, "GPIO_99"), + PINCTRL_PIN(100, "GPIO_100"), + PINCTRL_PIN(101, "GPIO_101"), + PINCTRL_PIN(102, "GPIO_102"), + PINCTRL_PIN(103, "GPIO_103"), + PINCTRL_PIN(104, "GPIO_104"), + PINCTRL_PIN(105, "GPIO_105"), + PINCTRL_PIN(106, "GPIO_106"), + PINCTRL_PIN(107, "GPIO_107"), + PINCTRL_PIN(108, "GPIO_108"), + PINCTRL_PIN(109, "GPIO_109"), + PINCTRL_PIN(110, "GPIO_110"), + PINCTRL_PIN(111, "GPIO_111"), + PINCTRL_PIN(112, "GPIO_112"), + PINCTRL_PIN(113, "GPIO_113"), + PINCTRL_PIN(114, "GPIO_114"), + PINCTRL_PIN(115, "GPIO_115"), + PINCTRL_PIN(116, "GPIO_116"), + PINCTRL_PIN(117, "GPIO_117"), + PINCTRL_PIN(118, "GPIO_118"), + PINCTRL_PIN(119, "GPIO_119"), + PINCTRL_PIN(120, "GPIO_120"), + PINCTRL_PIN(121, "GPIO_121"), + PINCTRL_PIN(122, "GPIO_122"), + PINCTRL_PIN(123, "GPIO_123"), + PINCTRL_PIN(124, "GPIO_124"), + PINCTRL_PIN(125, "GPIO_125"), + PINCTRL_PIN(126, "GPIO_126"), + PINCTRL_PIN(127, "GPIO_127"), + PINCTRL_PIN(128, "GPIO_128"), + PINCTRL_PIN(129, "GPIO_129"), + PINCTRL_PIN(130, "GPIO_130"), + PINCTRL_PIN(131, "GPIO_131"), + PINCTRL_PIN(132, "GPIO_132"), + PINCTRL_PIN(133, "GPIO_133"), + PINCTRL_PIN(134, "GPIO_134"), + PINCTRL_PIN(135, "GPIO_135"), + PINCTRL_PIN(136, "GPIO_136"), + PINCTRL_PIN(137, "GPIO_137"), + PINCTRL_PIN(138, "GPIO_138"), + PINCTRL_PIN(139, "GPIO_139"), + PINCTRL_PIN(140, "GPIO_140"), + PINCTRL_PIN(141, "GPIO_141"), + PINCTRL_PIN(142, "GPIO_142"), + PINCTRL_PIN(143, "GPIO_143"), + PINCTRL_PIN(144, "GPIO_144"), + PINCTRL_PIN(145, "GPIO_145"), + PINCTRL_PIN(146, "GPIO_146"), + PINCTRL_PIN(147, "GPIO_147"), + PINCTRL_PIN(148, "GPIO_148"), + PINCTRL_PIN(149, "GPIO_149"), + PINCTRL_PIN(150, "GPIO_150"), + PINCTRL_PIN(151, "GPIO_151"), + PINCTRL_PIN(152, "GPIO_152"), + PINCTRL_PIN(153, "GPIO_153"), + PINCTRL_PIN(154, "GPIO_154"), + PINCTRL_PIN(155, "GPIO_155"), + PINCTRL_PIN(156, "GPIO_156"), + PINCTRL_PIN(157, "GPIO_157"), + PINCTRL_PIN(158, "GPIO_158"), + PINCTRL_PIN(159, "GPIO_159"), + PINCTRL_PIN(160, "GPIO_160"), + PINCTRL_PIN(161, "GPIO_161"), + PINCTRL_PIN(162, "GPIO_162"), + PINCTRL_PIN(163, "GPIO_163"), + PINCTRL_PIN(164, "GPIO_164"), + PINCTRL_PIN(165, "GPIO_165"), + PINCTRL_PIN(166, "GPIO_166"), + PINCTRL_PIN(167, "GPIO_167"), + PINCTRL_PIN(168, "GPIO_168"), + PINCTRL_PIN(169, "GPIO_169"), + PINCTRL_PIN(170, "GPIO_170"), + PINCTRL_PIN(171, "GPIO_171"), + PINCTRL_PIN(172, "GPIO_172"), + PINCTRL_PIN(173, "GPIO_173"), + PINCTRL_PIN(174, "GPIO_174"), + PINCTRL_PIN(175, "UFS_RESET"), + PINCTRL_PIN(176, "SDC1_RCLK"), + PINCTRL_PIN(177, "SDC1_CLK"), + PINCTRL_PIN(178, "SDC1_CMD"), + PINCTRL_PIN(179, "SDC1_DATA"), + PINCTRL_PIN(180, "SDC2_CLK"), + PINCTRL_PIN(181, "SDC2_CMD"), + PINCTRL_PIN(182, "SDC2_DATA"), +}; + +#define DECLARE_MSM_GPIO_PINS(pin) \ + static const unsigned int gpio##pin##_pins[] = { pin } +DECLARE_MSM_GPIO_PINS(0); +DECLARE_MSM_GPIO_PINS(1); +DECLARE_MSM_GPIO_PINS(2); +DECLARE_MSM_GPIO_PINS(3); +DECLARE_MSM_GPIO_PINS(4); +DECLARE_MSM_GPIO_PINS(5); +DECLARE_MSM_GPIO_PINS(6); +DECLARE_MSM_GPIO_PINS(7); +DECLARE_MSM_GPIO_PINS(8); +DECLARE_MSM_GPIO_PINS(9); +DECLARE_MSM_GPIO_PINS(10); +DECLARE_MSM_GPIO_PINS(11); +DECLARE_MSM_GPIO_PINS(12); +DECLARE_MSM_GPIO_PINS(13); +DECLARE_MSM_GPIO_PINS(14); +DECLARE_MSM_GPIO_PINS(15); +DECLARE_MSM_GPIO_PINS(16); +DECLARE_MSM_GPIO_PINS(17); +DECLARE_MSM_GPIO_PINS(18); +DECLARE_MSM_GPIO_PINS(19); +DECLARE_MSM_GPIO_PINS(20); +DECLARE_MSM_GPIO_PINS(21); +DECLARE_MSM_GPIO_PINS(22); +DECLARE_MSM_GPIO_PINS(23); +DECLARE_MSM_GPIO_PINS(24); +DECLARE_MSM_GPIO_PINS(25); +DECLARE_MSM_GPIO_PINS(26); +DECLARE_MSM_GPIO_PINS(27); +DECLARE_MSM_GPIO_PINS(28); +DECLARE_MSM_GPIO_PINS(29); +DECLARE_MSM_GPIO_PINS(30); +DECLARE_MSM_GPIO_PINS(31); +DECLARE_MSM_GPIO_PINS(32); +DECLARE_MSM_GPIO_PINS(33); +DECLARE_MSM_GPIO_PINS(34); +DECLARE_MSM_GPIO_PINS(35); +DECLARE_MSM_GPIO_PINS(36); +DECLARE_MSM_GPIO_PINS(37); +DECLARE_MSM_GPIO_PINS(38); +DECLARE_MSM_GPIO_PINS(39); +DECLARE_MSM_GPIO_PINS(40); +DECLARE_MSM_GPIO_PINS(41); +DECLARE_MSM_GPIO_PINS(42); +DECLARE_MSM_GPIO_PINS(43); +DECLARE_MSM_GPIO_PINS(44); +DECLARE_MSM_GPIO_PINS(45); +DECLARE_MSM_GPIO_PINS(46); +DECLARE_MSM_GPIO_PINS(47); +DECLARE_MSM_GPIO_PINS(48); +DECLARE_MSM_GPIO_PINS(49); +DECLARE_MSM_GPIO_PINS(50); +DECLARE_MSM_GPIO_PINS(51); +DECLARE_MSM_GPIO_PINS(52); +DECLARE_MSM_GPIO_PINS(53); +DECLARE_MSM_GPIO_PINS(54); +DECLARE_MSM_GPIO_PINS(55); +DECLARE_MSM_GPIO_PINS(56); +DECLARE_MSM_GPIO_PINS(57); +DECLARE_MSM_GPIO_PINS(58); +DECLARE_MSM_GPIO_PINS(59); +DECLARE_MSM_GPIO_PINS(60); +DECLARE_MSM_GPIO_PINS(61); +DECLARE_MSM_GPIO_PINS(62); +DECLARE_MSM_GPIO_PINS(63); +DECLARE_MSM_GPIO_PINS(64); +DECLARE_MSM_GPIO_PINS(65); +DECLARE_MSM_GPIO_PINS(66); +DECLARE_MSM_GPIO_PINS(67); +DECLARE_MSM_GPIO_PINS(68); +DECLARE_MSM_GPIO_PINS(69); +DECLARE_MSM_GPIO_PINS(70); +DECLARE_MSM_GPIO_PINS(71); +DECLARE_MSM_GPIO_PINS(72); +DECLARE_MSM_GPIO_PINS(73); +DECLARE_MSM_GPIO_PINS(74); +DECLARE_MSM_GPIO_PINS(75); +DECLARE_MSM_GPIO_PINS(76); +DECLARE_MSM_GPIO_PINS(77); +DECLARE_MSM_GPIO_PINS(78); +DECLARE_MSM_GPIO_PINS(79); +DECLARE_MSM_GPIO_PINS(80); +DECLARE_MSM_GPIO_PINS(81); +DECLARE_MSM_GPIO_PINS(82); +DECLARE_MSM_GPIO_PINS(83); +DECLARE_MSM_GPIO_PINS(84); +DECLARE_MSM_GPIO_PINS(85); +DECLARE_MSM_GPIO_PINS(86); +DECLARE_MSM_GPIO_PINS(87); +DECLARE_MSM_GPIO_PINS(88); +DECLARE_MSM_GPIO_PINS(89); +DECLARE_MSM_GPIO_PINS(90); +DECLARE_MSM_GPIO_PINS(91); +DECLARE_MSM_GPIO_PINS(92); +DECLARE_MSM_GPIO_PINS(93); +DECLARE_MSM_GPIO_PINS(94); +DECLARE_MSM_GPIO_PINS(95); +DECLARE_MSM_GPIO_PINS(96); +DECLARE_MSM_GPIO_PINS(97); +DECLARE_MSM_GPIO_PINS(98); +DECLARE_MSM_GPIO_PINS(99); +DECLARE_MSM_GPIO_PINS(100); +DECLARE_MSM_GPIO_PINS(101); +DECLARE_MSM_GPIO_PINS(102); +DECLARE_MSM_GPIO_PINS(103); +DECLARE_MSM_GPIO_PINS(104); +DECLARE_MSM_GPIO_PINS(105); +DECLARE_MSM_GPIO_PINS(106); +DECLARE_MSM_GPIO_PINS(107); +DECLARE_MSM_GPIO_PINS(108); +DECLARE_MSM_GPIO_PINS(109); +DECLARE_MSM_GPIO_PINS(110); +DECLARE_MSM_GPIO_PINS(111); +DECLARE_MSM_GPIO_PINS(112); +DECLARE_MSM_GPIO_PINS(113); +DECLARE_MSM_GPIO_PINS(114); +DECLARE_MSM_GPIO_PINS(115); +DECLARE_MSM_GPIO_PINS(116); +DECLARE_MSM_GPIO_PINS(117); +DECLARE_MSM_GPIO_PINS(118); +DECLARE_MSM_GPIO_PINS(119); +DECLARE_MSM_GPIO_PINS(120); +DECLARE_MSM_GPIO_PINS(121); +DECLARE_MSM_GPIO_PINS(122); +DECLARE_MSM_GPIO_PINS(123); +DECLARE_MSM_GPIO_PINS(124); +DECLARE_MSM_GPIO_PINS(125); +DECLARE_MSM_GPIO_PINS(126); +DECLARE_MSM_GPIO_PINS(127); +DECLARE_MSM_GPIO_PINS(128); +DECLARE_MSM_GPIO_PINS(129); +DECLARE_MSM_GPIO_PINS(130); +DECLARE_MSM_GPIO_PINS(131); +DECLARE_MSM_GPIO_PINS(132); +DECLARE_MSM_GPIO_PINS(133); +DECLARE_MSM_GPIO_PINS(134); +DECLARE_MSM_GPIO_PINS(135); +DECLARE_MSM_GPIO_PINS(136); +DECLARE_MSM_GPIO_PINS(137); +DECLARE_MSM_GPIO_PINS(138); +DECLARE_MSM_GPIO_PINS(139); +DECLARE_MSM_GPIO_PINS(140); +DECLARE_MSM_GPIO_PINS(141); +DECLARE_MSM_GPIO_PINS(142); +DECLARE_MSM_GPIO_PINS(143); +DECLARE_MSM_GPIO_PINS(144); +DECLARE_MSM_GPIO_PINS(145); +DECLARE_MSM_GPIO_PINS(146); +DECLARE_MSM_GPIO_PINS(147); +DECLARE_MSM_GPIO_PINS(148); +DECLARE_MSM_GPIO_PINS(149); +DECLARE_MSM_GPIO_PINS(150); +DECLARE_MSM_GPIO_PINS(151); +DECLARE_MSM_GPIO_PINS(152); +DECLARE_MSM_GPIO_PINS(153); +DECLARE_MSM_GPIO_PINS(154); +DECLARE_MSM_GPIO_PINS(155); +DECLARE_MSM_GPIO_PINS(156); +DECLARE_MSM_GPIO_PINS(157); +DECLARE_MSM_GPIO_PINS(158); +DECLARE_MSM_GPIO_PINS(159); +DECLARE_MSM_GPIO_PINS(160); +DECLARE_MSM_GPIO_PINS(161); +DECLARE_MSM_GPIO_PINS(162); +DECLARE_MSM_GPIO_PINS(163); +DECLARE_MSM_GPIO_PINS(164); +DECLARE_MSM_GPIO_PINS(165); +DECLARE_MSM_GPIO_PINS(166); +DECLARE_MSM_GPIO_PINS(167); +DECLARE_MSM_GPIO_PINS(168); +DECLARE_MSM_GPIO_PINS(169); +DECLARE_MSM_GPIO_PINS(170); +DECLARE_MSM_GPIO_PINS(171); +DECLARE_MSM_GPIO_PINS(172); +DECLARE_MSM_GPIO_PINS(173); +DECLARE_MSM_GPIO_PINS(174); + +static const unsigned int ufs_reset_pins[] = { 175 }; +static const unsigned int sdc1_rclk_pins[] = { 176 }; +static const unsigned int sdc1_clk_pins[] = { 177 }; +static const unsigned int sdc1_cmd_pins[] = { 178 }; +static const unsigned int sdc1_data_pins[] = { 179 }; +static const unsigned int sdc2_clk_pins[] = { 180 }; +static const unsigned int sdc2_cmd_pins[] = { 181 }; +static const unsigned int sdc2_data_pins[] = { 182 }; + +enum sc7280_functions { + msm_mux_atest_char, + msm_mux_atest_char0, + msm_mux_atest_char1, + msm_mux_atest_char2, + msm_mux_atest_char3, + msm_mux_atest_usb0, + msm_mux_atest_usb00, + msm_mux_atest_usb01, + msm_mux_atest_usb02, + msm_mux_atest_usb03, + msm_mux_atest_usb1, + msm_mux_atest_usb10, + msm_mux_atest_usb11, + msm_mux_atest_usb12, + msm_mux_atest_usb13, + msm_mux_audio_ref, + msm_mux_cam_mclk, + msm_mux_cci_async, + msm_mux_cci_i2c, + msm_mux_cci_timer0, + msm_mux_cci_timer1, + msm_mux_cci_timer2, + msm_mux_cci_timer3, + msm_mux_cci_timer4, + msm_mux_cmu_rng0, + msm_mux_cmu_rng1, + msm_mux_cmu_rng2, + msm_mux_cmu_rng3, + msm_mux_coex_uart1, + msm_mux_cri_trng, + msm_mux_cri_trng0, + msm_mux_cri_trng1, + msm_mux_dbg_out, + msm_mux_ddr_bist, + msm_mux_ddr_pxi0, + msm_mux_ddr_pxi1, + msm_mux_dp_hot, + msm_mux_dp_lcd, + msm_mux_edp_hot, + msm_mux_edp_lcd, + msm_mux_egpio, + msm_mux_gcc_gp1, + msm_mux_gcc_gp2, + msm_mux_gcc_gp3, + msm_mux_gpio, + msm_mux_host2wlan_sol, + msm_mux_ibi_i3c, + msm_mux_jitter_bist, + msm_mux_lpass_slimbus, + msm_mux_mdp_vsync, + msm_mux_mdp_vsync0, + msm_mux_mdp_vsync1, + msm_mux_mdp_vsync2, + msm_mux_mdp_vsync3, + msm_mux_mdp_vsync4, + msm_mux_mdp_vsync5, + msm_mux_mi2s0_data0, + msm_mux_mi2s0_data1, + msm_mux_mi2s0_sck, + msm_mux_mi2s0_ws, + msm_mux_mi2s1_data0, + msm_mux_mi2s1_data1, + msm_mux_mi2s1_sck, + msm_mux_mi2s1_ws, + msm_mux_mi2s2_data0, + msm_mux_mi2s2_data1, + msm_mux_mi2s2_sck, + msm_mux_mi2s2_ws, + msm_mux_mss_grfc0, + msm_mux_mss_grfc1, + msm_mux_mss_grfc10, + msm_mux_mss_grfc11, + msm_mux_mss_grfc12, + msm_mux_mss_grfc2, + msm_mux_mss_grfc3, + msm_mux_mss_grfc4, + msm_mux_mss_grfc5, + msm_mux_mss_grfc6, + msm_mux_mss_grfc7, + msm_mux_mss_grfc8, + msm_mux_mss_grfc9, + msm_mux_nav_gpio0, + msm_mux_nav_gpio1, + msm_mux_nav_gpio2, + msm_mux_pa_indicator, + msm_mux_pcie0_clkreqn, + msm_mux_pcie1_clkreqn, + msm_mux_phase_flag, + msm_mux_pll_bist, + msm_mux_pll_bypassnl, + msm_mux_pll_clk, + msm_mux_pll_reset, + msm_mux_pri_mi2s, + msm_mux_prng_rosc, + msm_mux_qdss, + msm_mux_qdss_cti, + msm_mux_qlink0_enable, + msm_mux_qlink0_request, + msm_mux_qlink0_wmss, + msm_mux_qlink1_enable, + msm_mux_qlink1_request, + msm_mux_qlink1_wmss, + msm_mux_qspi_clk, + msm_mux_qspi_cs, + msm_mux_qspi_data, + msm_mux_qup00, + msm_mux_qup01, + msm_mux_qup02, + msm_mux_qup03, + msm_mux_qup04, + msm_mux_qup05, + msm_mux_qup06, + msm_mux_qup07, + msm_mux_qup10, + msm_mux_qup11, + msm_mux_qup12, + msm_mux_qup13, + msm_mux_qup14, + msm_mux_qup15, + msm_mux_qup16, + msm_mux_qup17, + msm_mux_sd_write, + msm_mux_sdc40, + msm_mux_sdc41, + msm_mux_sdc42, + msm_mux_sdc43, + msm_mux_sdc4_clk, + msm_mux_sdc4_cmd, + msm_mux_sec_mi2s, + msm_mux_tb_trig, + msm_mux_tgu_ch0, + msm_mux_tgu_ch1, + msm_mux_tsense_pwm1, + msm_mux_tsense_pwm2, + msm_mux_uim0_clk, + msm_mux_uim0_data, + msm_mux_uim0_present, + msm_mux_uim0_reset, + msm_mux_uim1_clk, + msm_mux_uim1_data, + msm_mux_uim1_present, + msm_mux_uim1_reset, + msm_mux_usb2phy_ac, + msm_mux_usb_phy, + msm_mux_vfr_0, + msm_mux_vfr_1, + msm_mux_vsense_trigger, + msm_mux__, +}; + +static const char * const gpio_groups[] = { + "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7", + "gpio8", "gpio9", "gpio10", "gpio11", "gpio12", "gpio13", "gpio14", + "gpio15", "gpio16", "gpio17", "gpio18", "gpio19", "gpio20", "gpio21", + "gpio22", "gpio23", "gpio24", "gpio25", "gpio26", "gpio27", "gpio28", + "gpio29", "gpio30", "gpio31", "gpio32", "gpio33", "gpio34", "gpio35", + "gpio36", "gpio37", "gpio38", "gpio39", "gpio40", "gpio41", "gpio42", + "gpio43", "gpio44", "gpio45", "gpio46", "gpio47", "gpio48", "gpio49", + "gpio50", "gpio51", "gpio52", "gpio53", "gpio54", "gpio55", "gpio56", + "gpio57", "gpio58", "gpio59", "gpio60", "gpio61", "gpio62", "gpio63", + "gpio64", "gpio65", "gpio66", "gpio67", "gpio68", "gpio69", "gpio70", + "gpio71", "gpio72", "gpio73", "gpio74", "gpio75", "gpio76", "gpio77", + "gpio78", "gpio79", "gpio80", "gpio81", "gpio82", "gpio83", "gpio84", + "gpio85", "gpio86", "gpio87", "gpio88", "gpio89", "gpio90", "gpio91", + "gpio92", "gpio93", "gpio94", "gpio95", "gpio96", "gpio97", "gpio98", + "gpio99", "gpio100", "gpio101", "gpio102", "gpio103", "gpio104", + "gpio105", "gpio106", "gpio107", "gpio108", "gpio109", "gpio110", + "gpio111", "gpio112", "gpio113", "gpio114", "gpio115", "gpio116", + "gpio117", "gpio118", "gpio119", "gpio120", "gpio121", "gpio122", + "gpio123", "gpio124", "gpio125", "gpio126", "gpio127", "gpio128", + "gpio129", "gpio130", "gpio131", "gpio132", "gpio133", "gpio134", + "gpio135", "gpio136", "gpio137", "gpio138", "gpio139", "gpio140", + "gpio141", "gpio142", "gpio143", "gpio144", "gpio145", "gpio146", + "gpio147", "gpio148", "gpio149", "gpio150", "gpio151", "gpio152", + "gpio153", "gpio154", "gpio155", "gpio156", "gpio157", "gpio158", + "gpio159", "gpio160", "gpio161", "gpio162", "gpio163", "gpio164", + "gpio165", "gpio166", "gpio167", "gpio168", "gpio169", "gpio170", + "gpio171", "gpio172", "gpio173", "gpio174", +}; +static const char * const egpio_groups[] = { + "gpio144", "gpio145", "gpio146", "gpio147", "gpio148", "gpio149", + "gpio150", "gpio151", "gpio152", "gpio153", "gpio154", "gpio155", + "gpio156", "gpio157", "gpio158", "gpio159", "gpio160", "gpio161", + "gpio162", "gpio163", "gpio164", "gpio165", "gpio166", "gpio167", + "gpio168", "gpio169", "gpio170", "gpio171", "gpio172", "gpio173", + "gpio174", +}; +static const char * const atest_char_groups[] = { + "gpio81", +}; +static const char * const atest_char0_groups[] = { + "gpio77", +}; +static const char * const atest_char1_groups[] = { + "gpio78", +}; +static const char * const atest_char2_groups[] = { + "gpio79", +}; +static const char * const atest_char3_groups[] = { + "gpio80", +}; +static const char * const atest_usb0_groups[] = { + "gpio107", +}; +static const char * const atest_usb00_groups[] = { + "gpio106", +}; +static const char * const atest_usb01_groups[] = { + "gpio105", +}; +static const char * const atest_usb02_groups[] = { + "gpio104", +}; +static const char * const atest_usb03_groups[] = { + "gpio103", +}; +static const char * const atest_usb1_groups[] = { + "gpio81", +}; +static const char * const atest_usb10_groups[] = { + "gpio80", +}; +static const char * const atest_usb11_groups[] = { + "gpio79", +}; +static const char * const atest_usb12_groups[] = { + "gpio78", +}; +static const char * const atest_usb13_groups[] = { + "gpio77", +}; +static const char * const audio_ref_groups[] = { + "gpio105", +}; +static const char * const cam_mclk_groups[] = { + "gpio64", "gpio65", "gpio66", "gpio67", "gpio68", "gpio93", +}; +static const char * const cci_async_groups[] = { + "gpio78", "gpio79", "gpio93", +}; +static const char * const cci_i2c_groups[] = { + "gpio69", "gpio70", "gpio71", "gpio72", "gpio73", "gpio74", "gpio75", + "gpio76", +}; +static const char * const cci_timer0_groups[] = { + "gpio20", +}; +static const char * const cci_timer1_groups[] = { + "gpio21", +}; +static const char * const cci_timer2_groups[] = { + "gpio77", +}; +static const char * const cci_timer3_groups[] = { + "gpio78", +}; +static const char * const cci_timer4_groups[] = { + "gpio79", +}; +static const char * const cmu_rng0_groups[] = { + "gpio120", +}; +static const char * const cmu_rng1_groups[] = { + "gpio119", +}; +static const char * const cmu_rng2_groups[] = { + "gpio118", +}; +static const char * const cmu_rng3_groups[] = { + "gpio117", +}; +static const char * const coex_uart1_groups[] = { + "gpio127", "gpio128", +}; +static const char * const cri_trng_groups[] = { + "gpio124", +}; +static const char * const cri_trng0_groups[] = { + "gpio121", +}; +static const char * const cri_trng1_groups[] = { + "gpio122", +}; +static const char * const dbg_out_groups[] = { + "gpio38", +}; +static const char * const ddr_bist_groups[] = { + "gpio56", "gpio57", "gpio58", "gpio59", +}; +static const char * const ddr_pxi0_groups[] = { + "gpio14", "gpio15", +}; +static const char * const ddr_pxi1_groups[] = { + "gpio12", "gpio13", +}; +static const char * const dp_hot_groups[] = { + "gpio47", +}; +static const char * const dp_lcd_groups[] = { + "gpio81", +}; +static const char * const edp_hot_groups[] = { + "gpio60", +}; +static const char * const edp_lcd_groups[] = { + "gpio46", +}; +static const char * const gcc_gp1_groups[] = { + "gpio76", "gpio105", +}; +static const char * const gcc_gp2_groups[] = { + "gpio77", "gpio106", +}; +static const char * const gcc_gp3_groups[] = { + "gpio78", "gpio107", +}; +static const char * const host2wlan_sol_groups[] = { + "gpio26", +}; +static const char * const ibi_i3c_groups[] = { + "gpio0", "gpio1", "gpio4", "gpio5", "gpio36", "gpio37", +}; +static const char * const jitter_bist_groups[] = { + "gpio79", +}; +static const char * const lpass_slimbus_groups[] = { + "gpio94", "gpio95", +}; +static const char * const mdp_vsync_groups[] = { + "gpio14", "gpio16", "gpio79", "gpio80", "gpio81", +}; +static const char * const mdp_vsync0_groups[] = { + "gpio80", +}; +static const char * const mdp_vsync1_groups[] = { + "gpio80", +}; +static const char * const mdp_vsync2_groups[] = { + "gpio81", +}; +static const char * const mdp_vsync3_groups[] = { + "gpio81", +}; +static const char * const mdp_vsync4_groups[] = { + "gpio80", +}; +static const char * const mdp_vsync5_groups[] = { + "gpio81", +}; +static const char * const mi2s0_data0_groups[] = { + "gpio98", +}; +static const char * const mi2s0_data1_groups[] = { + "gpio99", +}; +static const char * const mi2s0_sck_groups[] = { + "gpio97", +}; +static const char * const mi2s0_ws_groups[] = { + "gpio100", +}; +static const char * const mi2s1_data0_groups[] = { + "gpio107", +}; +static const char * const mi2s1_data1_groups[] = { + "gpio105", +}; +static const char * const mi2s1_sck_groups[] = { + "gpio106", +}; +static const char * const mi2s1_ws_groups[] = { + "gpio108", +}; +static const char * const mi2s2_data0_groups[] = { + "gpio102", +}; +static const char * const mi2s2_data1_groups[] = { + "gpio104", +}; +static const char * const mi2s2_sck_groups[] = { + "gpio101", +}; +static const char * const mi2s2_ws_groups[] = { + "gpio103", +}; +static const char * const mss_grfc0_groups[] = { + "gpio117", "gpio132", +}; +static const char * const mss_grfc1_groups[] = { + "gpio118", +}; +static const char * const mss_grfc10_groups[] = { + "gpio127", +}; +static const char * const mss_grfc11_groups[] = { + "gpio128", +}; +static const char * const mss_grfc12_groups[] = { + "gpio131", +}; +static const char * const mss_grfc2_groups[] = { + "gpio119", +}; +static const char * const mss_grfc3_groups[] = { + "gpio120", +}; +static const char * const mss_grfc4_groups[] = { + "gpio121", +}; +static const char * const mss_grfc5_groups[] = { + "gpio122", +}; +static const char * const mss_grfc6_groups[] = { + "gpio123", +}; +static const char * const mss_grfc7_groups[] = { + "gpio124", +}; +static const char * const mss_grfc8_groups[] = { + "gpio125", +}; +static const char * const mss_grfc9_groups[] = { + "gpio126", +}; +static const char * const nav_gpio0_groups[] = { + "gpio129", +}; +static const char * const nav_gpio1_groups[] = { + "gpio130", +}; +static const char * const nav_gpio2_groups[] = { + "gpio131", +}; +static const char * const pa_indicator_groups[] = { + "gpio131", +}; +static const char * const pcie0_clkreqn_groups[] = { + "gpio88", +}; +static const char * const pcie1_clkreqn_groups[] = { + "gpio79", +}; +static const char * const phase_flag_groups[] = { + "gpio12", "gpio13", "gpio14", "gpio15", "gpio16", + "gpio17", "gpio18", "gpio19", "gpio56", "gpio57", + "gpio58", "gpio59", "gpio60", "gpio61", "gpio62", + "gpio63", "gpio117", "gpio118", "gpio119", "gpio120", + "gpio121", "gpio122", "gpio123", "gpio124", "gpio125", + "gpio126", "gpio127", "gpio128", "gpio129", "gpio130", + "gpio131", "gpio132", +}; +static const char * const pll_bist_groups[] = { + "gpio80", +}; +static const char * const pll_bypassnl_groups[] = { + "gpio66", +}; +static const char * const pll_clk_groups[] = { + "gpio140", +}; +static const char * const pll_reset_groups[] = { + "gpio67", +}; +static const char * const pri_mi2s_groups[] = { + "gpio96", +}; +static const char * const prng_rosc_groups[] = { + "gpio123", +}; +static const char * const qdss_groups[] = { + "gpio2", "gpio3", "gpio8", "gpio9", "gpio10", + "gpio11", "gpio12", "gpio13", "gpio20", "gpio21", + "gpio22", "gpio23", "gpio24", "gpio25", "gpio26", + "gpio27", "gpio28", "gpio29", "gpio58", "gpio59", + "gpio101", "gpio102", "gpio103", "gpio104", "gpio105", + "gpio106", "gpio107", "gpio108", "gpio150", "gpio151", + "gpio152", "gpio153", "gpio171", "gpio172", "gpio173", + "gpio174", +}; +static const char * const qdss_cti_groups[] = { + "gpio15", "gpio16", "gpio18", "gpio19", "gpio156", "gpio157", + "gpio165", "gpio166", +}; +static const char * const qlink0_enable_groups[] = { + "gpio134", +}; +static const char * const qlink0_request_groups[] = { + "gpio133", +}; +static const char * const qlink0_wmss_groups[] = { + "gpio135", +}; +static const char * const qlink1_enable_groups[] = { + "gpio137", +}; +static const char * const qlink1_request_groups[] = { + "gpio136", +}; +static const char * const qlink1_wmss_groups[] = { + "gpio138", +}; +static const char * const qspi_clk_groups[] = { + "gpio14", +}; +static const char * const qspi_cs_groups[] = { + "gpio15", "gpio19", +}; +static const char * const qspi_data_groups[] = { + "gpio12", "gpio13", "gpio16", "gpio17", +}; +static const char * const qup00_groups[] = { + "gpio0", "gpio1", "gpio2", "gpio3", +}; +static const char * const qup01_groups[] = { + "gpio4", "gpio5", "gpio6", "gpio7", +}; +static const char * const qup02_groups[] = { + "gpio8", "gpio9", "gpio10", "gpio11", +}; +static const char * const qup03_groups[] = { + "gpio12", "gpio13", "gpio14", "gpio15", +}; +static const char * const qup04_groups[] = { + "gpio16", "gpio17", "gpio18", "gpio19", +}; +static const char * const qup05_groups[] = { + "gpio20", "gpio21", "gpio22", "gpio23", +}; +static const char * const qup06_groups[] = { + "gpio24", "gpio25", "gpio26", "gpio27", +}; +static const char * const qup07_groups[] = { + "gpio2", "gpio3", "gpio6", "gpio28", "gpio29", "gpio30", "gpio31", +}; +static const char * const qup10_groups[] = { + "gpio32", "gpio33", "gpio34", "gpio35", +}; +static const char * const qup11_groups[] = { + "gpio36", "gpio37", "gpio38", "gpio39", +}; +static const char * const qup12_groups[] = { + "gpio40", "gpio41", "gpio42", "gpio43", +}; +static const char * const qup13_groups[] = { + "gpio44", "gpio45", "gpio46", "gpio47", +}; +static const char * const qup14_groups[] = { + "gpio38", "gpio48", "gpio49", "gpio50", "gpio51", "gpio54", "gpio55", +}; +static const char * const qup15_groups[] = { + "gpio52", "gpio53", "gpio54", "gpio55", +}; +static const char * const qup16_groups[] = { + "gpio50", "gpio56", "gpio57", "gpio58", "gpio59", "gpio62", "gpio63", +}; +static const char * const qup17_groups[] = { + "gpio60", "gpio61", "gpio62", "gpio63", +}; +static const char * const sd_write_groups[] = { + "gpio61", +}; +static const char * const sdc40_groups[] = { + "gpio12", +}; +static const char * const sdc41_groups[] = { + "gpio13", +}; +static const char * const sdc42_groups[] = { + "gpio16", +}; +static const char * const sdc43_groups[] = { + "gpio17", +}; +static const char * const sdc4_clk_groups[] = { + "gpio14", +}; +static const char * const sdc4_cmd_groups[] = { + "gpio19", +}; +static const char * const sec_mi2s_groups[] = { + "gpio105", +}; +static const char * const tb_trig_groups[] = { + "gpio12", "gpio13", "gpio15", +}; +static const char * const tgu_ch0_groups[] = { + "gpio65", +}; +static const char * const tgu_ch1_groups[] = { + "gpio66", +}; +static const char * const tsense_pwm1_groups[] = { + "gpio61", +}; +static const char * const tsense_pwm2_groups[] = { + "gpio61", +}; +static const char * const uim0_clk_groups[] = { + "gpio114", +}; +static const char * const uim0_data_groups[] = { + "gpio113", +}; +static const char * const uim0_present_groups[] = { + "gpio116", +}; +static const char * const uim0_reset_groups[] = { + "gpio115", +}; +static const char * const uim1_clk_groups[] = { + "gpio110", +}; +static const char * const uim1_data_groups[] = { + "gpio109", +}; +static const char * const uim1_present_groups[] = { + "gpio112", +}; +static const char * const uim1_reset_groups[] = { + "gpio111", +}; +static const char * const usb2phy_ac_groups[] = { + "gpio84", "gpio85", +}; +static const char * const usb_phy_groups[] = { + "gpio140", +}; +static const char * const vfr_0_groups[] = { + "gpio80", +}; +static const char * const vfr_1_groups[] = { + "gpio103", +}; +static const char * const vsense_trigger_groups[] = { + "gpio100", +}; + +static const struct pinfunction sc7280_functions[] = { + MSM_PIN_FUNCTION(atest_char), + MSM_PIN_FUNCTION(atest_char0), + MSM_PIN_FUNCTION(atest_char1), + MSM_PIN_FUNCTION(atest_char2), + MSM_PIN_FUNCTION(atest_char3), + MSM_PIN_FUNCTION(atest_usb0), + MSM_PIN_FUNCTION(atest_usb00), + MSM_PIN_FUNCTION(atest_usb01), + MSM_PIN_FUNCTION(atest_usb02), + MSM_PIN_FUNCTION(atest_usb03), + MSM_PIN_FUNCTION(atest_usb1), + MSM_PIN_FUNCTION(atest_usb10), + MSM_PIN_FUNCTION(atest_usb11), + MSM_PIN_FUNCTION(atest_usb12), + MSM_PIN_FUNCTION(atest_usb13), + MSM_PIN_FUNCTION(audio_ref), + MSM_PIN_FUNCTION(cam_mclk), + MSM_PIN_FUNCTION(cci_async), + MSM_PIN_FUNCTION(cci_i2c), + MSM_PIN_FUNCTION(cci_timer0), + MSM_PIN_FUNCTION(cci_timer1), + MSM_PIN_FUNCTION(cci_timer2), + MSM_PIN_FUNCTION(cci_timer3), + MSM_PIN_FUNCTION(cci_timer4), + MSM_PIN_FUNCTION(cmu_rng0), + MSM_PIN_FUNCTION(cmu_rng1), + MSM_PIN_FUNCTION(cmu_rng2), + MSM_PIN_FUNCTION(cmu_rng3), + MSM_PIN_FUNCTION(coex_uart1), + MSM_PIN_FUNCTION(cri_trng), + MSM_PIN_FUNCTION(cri_trng0), + MSM_PIN_FUNCTION(cri_trng1), + MSM_PIN_FUNCTION(dbg_out), + MSM_PIN_FUNCTION(ddr_bist), + MSM_PIN_FUNCTION(ddr_pxi0), + MSM_PIN_FUNCTION(ddr_pxi1), + MSM_PIN_FUNCTION(dp_hot), + MSM_PIN_FUNCTION(dp_lcd), + MSM_PIN_FUNCTION(edp_hot), + MSM_PIN_FUNCTION(edp_lcd), + MSM_PIN_FUNCTION(egpio), + MSM_PIN_FUNCTION(gcc_gp1), + MSM_PIN_FUNCTION(gcc_gp2), + MSM_PIN_FUNCTION(gcc_gp3), + MSM_PIN_FUNCTION(gpio), + MSM_PIN_FUNCTION(host2wlan_sol), + MSM_PIN_FUNCTION(ibi_i3c), + MSM_PIN_FUNCTION(jitter_bist), + MSM_PIN_FUNCTION(lpass_slimbus), + MSM_PIN_FUNCTION(mdp_vsync), + MSM_PIN_FUNCTION(mdp_vsync0), + MSM_PIN_FUNCTION(mdp_vsync1), + MSM_PIN_FUNCTION(mdp_vsync2), + MSM_PIN_FUNCTION(mdp_vsync3), + MSM_PIN_FUNCTION(mdp_vsync4), + MSM_PIN_FUNCTION(mdp_vsync5), + MSM_PIN_FUNCTION(mi2s0_data0), + MSM_PIN_FUNCTION(mi2s0_data1), + MSM_PIN_FUNCTION(mi2s0_sck), + MSM_PIN_FUNCTION(mi2s0_ws), + MSM_PIN_FUNCTION(mi2s1_data0), + MSM_PIN_FUNCTION(mi2s1_data1), + MSM_PIN_FUNCTION(mi2s1_sck), + MSM_PIN_FUNCTION(mi2s1_ws), + MSM_PIN_FUNCTION(mi2s2_data0), + MSM_PIN_FUNCTION(mi2s2_data1), + MSM_PIN_FUNCTION(mi2s2_sck), + MSM_PIN_FUNCTION(mi2s2_ws), + MSM_PIN_FUNCTION(mss_grfc0), + MSM_PIN_FUNCTION(mss_grfc1), + MSM_PIN_FUNCTION(mss_grfc10), + MSM_PIN_FUNCTION(mss_grfc11), + MSM_PIN_FUNCTION(mss_grfc12), + MSM_PIN_FUNCTION(mss_grfc2), + MSM_PIN_FUNCTION(mss_grfc3), + MSM_PIN_FUNCTION(mss_grfc4), + MSM_PIN_FUNCTION(mss_grfc5), + MSM_PIN_FUNCTION(mss_grfc6), + MSM_PIN_FUNCTION(mss_grfc7), + MSM_PIN_FUNCTION(mss_grfc8), + MSM_PIN_FUNCTION(mss_grfc9), + MSM_PIN_FUNCTION(nav_gpio0), + MSM_PIN_FUNCTION(nav_gpio1), + MSM_PIN_FUNCTION(nav_gpio2), + MSM_PIN_FUNCTION(pa_indicator), + MSM_PIN_FUNCTION(pcie0_clkreqn), + MSM_PIN_FUNCTION(pcie1_clkreqn), + MSM_PIN_FUNCTION(phase_flag), + MSM_PIN_FUNCTION(pll_bist), + MSM_PIN_FUNCTION(pll_bypassnl), + MSM_PIN_FUNCTION(pll_clk), + MSM_PIN_FUNCTION(pll_reset), + MSM_PIN_FUNCTION(pri_mi2s), + MSM_PIN_FUNCTION(prng_rosc), + MSM_PIN_FUNCTION(qdss), + MSM_PIN_FUNCTION(qdss_cti), + MSM_PIN_FUNCTION(qlink0_enable), + MSM_PIN_FUNCTION(qlink0_request), + MSM_PIN_FUNCTION(qlink0_wmss), + MSM_PIN_FUNCTION(qlink1_enable), + MSM_PIN_FUNCTION(qlink1_request), + MSM_PIN_FUNCTION(qlink1_wmss), + MSM_PIN_FUNCTION(qspi_clk), + MSM_PIN_FUNCTION(qspi_cs), + MSM_PIN_FUNCTION(qspi_data), + MSM_PIN_FUNCTION(qup00), + MSM_PIN_FUNCTION(qup01), + MSM_PIN_FUNCTION(qup02), + MSM_PIN_FUNCTION(qup03), + MSM_PIN_FUNCTION(qup04), + MSM_PIN_FUNCTION(qup05), + MSM_PIN_FUNCTION(qup06), + MSM_PIN_FUNCTION(qup07), + MSM_PIN_FUNCTION(qup10), + MSM_PIN_FUNCTION(qup11), + MSM_PIN_FUNCTION(qup12), + MSM_PIN_FUNCTION(qup13), + MSM_PIN_FUNCTION(qup14), + MSM_PIN_FUNCTION(qup15), + MSM_PIN_FUNCTION(qup16), + MSM_PIN_FUNCTION(qup17), + MSM_PIN_FUNCTION(sdc40), + MSM_PIN_FUNCTION(sdc41), + MSM_PIN_FUNCTION(sdc42), + MSM_PIN_FUNCTION(sdc43), + MSM_PIN_FUNCTION(sdc4_clk), + MSM_PIN_FUNCTION(sdc4_cmd), + MSM_PIN_FUNCTION(sd_write), + MSM_PIN_FUNCTION(sec_mi2s), + MSM_PIN_FUNCTION(tb_trig), + MSM_PIN_FUNCTION(tgu_ch0), + MSM_PIN_FUNCTION(tgu_ch1), + MSM_PIN_FUNCTION(tsense_pwm1), + MSM_PIN_FUNCTION(tsense_pwm2), + MSM_PIN_FUNCTION(uim0_clk), + MSM_PIN_FUNCTION(uim0_data), + MSM_PIN_FUNCTION(uim0_present), + MSM_PIN_FUNCTION(uim0_reset), + MSM_PIN_FUNCTION(uim1_clk), + MSM_PIN_FUNCTION(uim1_data), + MSM_PIN_FUNCTION(uim1_present), + MSM_PIN_FUNCTION(uim1_reset), + MSM_PIN_FUNCTION(usb2phy_ac), + MSM_PIN_FUNCTION(usb_phy), + MSM_PIN_FUNCTION(vfr_0), + MSM_PIN_FUNCTION(vfr_1), + MSM_PIN_FUNCTION(vsense_trigger), +}; + +/* Every pin is maintained as a single group, and missing or non-existing pin + * would be maintained as dummy group to synchronize pin group index with + * pin descriptor registered with pinctrl core. + * Clients would not be able to request these dummy pin groups. + */ +static const struct msm_pingroup sc7280_groups[] = { + [0] = PINGROUP(0, qup00, ibi_i3c, _, _, _, _, _, _, _), + [1] = PINGROUP(1, qup00, ibi_i3c, _, _, _, _, _, _, _), + [2] = PINGROUP(2, qup00, qup07, _, qdss, _, _, _, _, _), + [3] = PINGROUP(3, qup00, qup07, _, qdss, _, _, _, _, _), + [4] = PINGROUP(4, qup01, ibi_i3c, _, _, _, _, _, _, _), + [5] = PINGROUP(5, qup01, ibi_i3c, _, _, _, _, _, _, _), + [6] = PINGROUP(6, qup01, qup07, _, _, _, _, _, _, _), + [7] = PINGROUP(7, qup01, _, _, _, _, _, _, _, _), + [8] = PINGROUP(8, qup02, _, qdss, _, _, _, _, _, _), + [9] = PINGROUP(9, qup02, _, qdss, _, _, _, _, _, _), + [10] = PINGROUP(10, qup02, _, qdss, _, _, _, _, _, _), + [11] = PINGROUP(11, qup02, _, qdss, _, _, _, _, _, _), + [12] = PINGROUP(12, qup03, qspi_data, sdc40, tb_trig, phase_flag, qdss, ddr_pxi1, _, _), + [13] = PINGROUP(13, qup03, qspi_data, sdc41, tb_trig, phase_flag, qdss, ddr_pxi1, _, _), + [14] = PINGROUP(14, qup03, qspi_clk, sdc4_clk, mdp_vsync, phase_flag, ddr_pxi0, _, _, _), + [15] = PINGROUP(15, qup03, qspi_cs, tb_trig, phase_flag, qdss_cti, ddr_pxi0, _, _, _), + [16] = PINGROUP(16, qup04, qspi_data, sdc42, mdp_vsync, phase_flag, qdss_cti, _, _, _), + [17] = PINGROUP(17, qup04, qspi_data, sdc43, _, phase_flag, _, _, _, _), + [18] = PINGROUP(18, qup04, _, phase_flag, qdss_cti, _, _, _, _, _), + [19] = PINGROUP(19, qup04, qspi_cs, sdc4_cmd, _, phase_flag, qdss_cti, _, _, _), + [20] = PINGROUP(20, qup05, cci_timer0, _, qdss, _, _, _, _, _), + [21] = PINGROUP(21, qup05, cci_timer1, _, qdss, _, _, _, _, _), + [22] = PINGROUP(22, qup05, _, qdss, _, _, _, _, _, _), + [23] = PINGROUP(23, qup05, _, qdss, _, _, _, _, _, _), + [24] = PINGROUP(24, qup06, _, qdss, _, _, _, _, _, _), + [25] = PINGROUP(25, qup06, _, qdss, _, _, _, _, _, _), + [26] = PINGROUP(26, qup06, host2wlan_sol, _, qdss, _, _, _, _, _), + [27] = PINGROUP(27, qup06, _, qdss, _, _, _, _, _, _), + [28] = PINGROUP(28, qup07, _, qdss, _, _, _, _, _, _), + [29] = PINGROUP(29, qup07, qdss, _, _, _, _, _, _, _), + [30] = PINGROUP(30, qup07, _, _, _, _, _, _, _, _), + [31] = PINGROUP(31, qup07, _, _, _, _, _, _, _, _), + [32] = PINGROUP(32, qup10, _, _, _, _, _, _, _, _), + [33] = PINGROUP(33, qup10, _, _, _, _, _, _, _, _), + [34] = PINGROUP(34, qup10, _, _, _, _, _, _, _, _), + [35] = PINGROUP(35, qup10, _, _, _, _, _, _, _, _), + [36] = PINGROUP(36, qup11, ibi_i3c, _, _, _, _, _, _, _), + [37] = PINGROUP(37, qup11, ibi_i3c, _, _, _, _, _, _, _), + [38] = PINGROUP(38, qup11, qup14, dbg_out, _, _, _, _, _, _), + [39] = PINGROUP(39, qup11, _, _, _, _, _, _, _, _), + [40] = PINGROUP(40, qup12, _, _, _, _, _, _, _, _), + [41] = PINGROUP(41, qup12, _, _, _, _, _, _, _, _), + [42] = PINGROUP(42, qup12, _, _, _, _, _, _, _, _), + [43] = PINGROUP(43, qup12, _, _, _, _, _, _, _, _), + [44] = PINGROUP(44, qup13, _, _, _, _, _, _, _, _), + [45] = PINGROUP(45, qup13, _, _, _, _, _, _, _, _), + [46] = PINGROUP(46, qup13, edp_lcd, _, _, _, _, _, _, _), + [47] = PINGROUP(47, qup13, dp_hot, _, _, _, _, _, _, _), + [48] = PINGROUP(48, qup14, _, _, _, _, _, _, _, _), + [49] = PINGROUP(49, qup14, _, _, _, _, _, _, _, _), + [50] = PINGROUP(50, qup14, qup16, _, _, _, _, _, _, _), + [51] = PINGROUP(51, qup14, _, _, _, _, _, _, _, _), + [52] = PINGROUP(52, qup15, _, _, _, _, _, _, _, _), + [53] = PINGROUP(53, qup15, _, _, _, _, _, _, _, _), + [54] = PINGROUP(54, qup15, qup14, _, _, _, _, _, _, _), + [55] = PINGROUP(55, qup15, qup14, _, _, _, _, _, _, _), + [56] = PINGROUP(56, qup16, ddr_bist, phase_flag, _, _, _, _, _, _), + [57] = PINGROUP(57, qup16, ddr_bist, phase_flag, _, _, _, _, _, _), + [58] = PINGROUP(58, qup16, ddr_bist, phase_flag, qdss, _, _, _, _, _), + [59] = PINGROUP(59, qup16, ddr_bist, phase_flag, qdss, _, _, _, _, _), + [60] = PINGROUP(60, qup17, edp_hot, _, phase_flag, _, _, _, _, _), + [61] = PINGROUP(61, qup17, sd_write, phase_flag, tsense_pwm1, tsense_pwm2, _, _, _, _), + [62] = PINGROUP(62, qup17, qup16, phase_flag, _, _, _, _, _, _), + [63] = PINGROUP(63, qup17, qup16, phase_flag, _, _, _, _, _, _), + [64] = PINGROUP(64, cam_mclk, _, _, _, _, _, _, _, _), + [65] = PINGROUP(65, cam_mclk, tgu_ch0, _, _, _, _, _, _, _), + [66] = PINGROUP(66, cam_mclk, pll_bypassnl, tgu_ch1, _, _, _, _, _, _), + [67] = PINGROUP(67, cam_mclk, pll_reset, _, _, _, _, _, _, _), + [68] = PINGROUP(68, cam_mclk, _, _, _, _, _, _, _, _), + [69] = PINGROUP(69, cci_i2c, _, _, _, _, _, _, _, _), + [70] = PINGROUP(70, cci_i2c, _, _, _, _, _, _, _, _), + [71] = PINGROUP(71, cci_i2c, _, _, _, _, _, _, _, _), + [72] = PINGROUP(72, cci_i2c, _, _, _, _, _, _, _, _), + [73] = PINGROUP(73, cci_i2c, _, _, _, _, _, _, _, _), + [74] = PINGROUP(74, cci_i2c, _, _, _, _, _, _, _, _), + [75] = PINGROUP(75, cci_i2c, _, _, _, _, _, _, _, _), + [76] = PINGROUP(76, cci_i2c, gcc_gp1, _, _, _, _, _, _, _), + [77] = PINGROUP(77, cci_timer2, gcc_gp2, _, atest_usb13, atest_char0, _, _, _, _), + [78] = PINGROUP(78, cci_timer3, cci_async, gcc_gp3, _, atest_usb12, atest_char1, _, _, _), + [79] = PINGROUP(79, cci_timer4, cci_async, pcie1_clkreqn, mdp_vsync, jitter_bist, atest_usb11, atest_char2, _, _), + [80] = PINGROUP(80, mdp_vsync, vfr_0, mdp_vsync0, mdp_vsync1, mdp_vsync4, pll_bist, atest_usb10, atest_char3, _), + [81] = PINGROUP(81, mdp_vsync, dp_lcd, mdp_vsync2, mdp_vsync3, mdp_vsync5, atest_usb1, atest_char, _, _), + [82] = PINGROUP(82, _, _, _, _, _, _, _, _, _), + [83] = PINGROUP(83, _, _, _, _, _, _, _, _, _), + [84] = PINGROUP(84, usb2phy_ac, _, _, _, _, _, _, _, _), + [85] = PINGROUP(85, usb2phy_ac, _, _, _, _, _, _, _, _), + [86] = PINGROUP(86, _, _, _, _, _, _, _, _, _), + [87] = PINGROUP(87, _, _, _, _, _, _, _, _, _), + [88] = PINGROUP(88, pcie0_clkreqn, _, _, _, _, _, _, _, _), + [89] = PINGROUP(89, _, _, _, _, _, _, _, _, _), + [90] = PINGROUP(90, _, _, _, _, _, _, _, _, _), + [91] = PINGROUP(91, _, _, _, _, _, _, _, _, _), + [92] = PINGROUP(92, _, _, _, _, _, _, _, _, _), + [93] = PINGROUP(93, cam_mclk, cci_async, _, _, _, _, _, _, _), + [94] = PINGROUP(94, lpass_slimbus, _, _, _, _, _, _, _, _), + [95] = PINGROUP(95, lpass_slimbus, _, _, _, _, _, _, _, _), + [96] = PINGROUP(96, pri_mi2s, _, _, _, _, _, _, _, _), + [97] = PINGROUP(97, mi2s0_sck, _, _, _, _, _, _, _, _), + [98] = PINGROUP(98, mi2s0_data0, _, _, _, _, _, _, _, _), + [99] = PINGROUP(99, mi2s0_data1, _, _, _, _, _, _, _, _), + [100] = PINGROUP(100, mi2s0_ws, _, vsense_trigger, _, _, _, _, _, _), + [101] = PINGROUP(101, mi2s2_sck, _, qdss, _, _, _, _, _, _), + [102] = PINGROUP(102, mi2s2_data0, _, _, qdss, _, _, _, _, _), + [103] = PINGROUP(103, mi2s2_ws, vfr_1, _, _, qdss, _, atest_usb03, _, _), + [104] = PINGROUP(104, mi2s2_data1, _, _, qdss, _, atest_usb02, _, _, _), + [105] = PINGROUP(105, sec_mi2s, mi2s1_data1, audio_ref, gcc_gp1, _, qdss, atest_usb01, _, _), + [106] = PINGROUP(106, mi2s1_sck, gcc_gp2, _, qdss, atest_usb00, _, _, _, _), + [107] = PINGROUP(107, mi2s1_data0, gcc_gp3, _, qdss, atest_usb0, _, _, _, _), + [108] = PINGROUP(108, mi2s1_ws, _, qdss, _, _, _, _, _, _), + [109] = PINGROUP(109, uim1_data, _, _, _, _, _, _, _, _), + [110] = PINGROUP(110, uim1_clk, _, _, _, _, _, _, _, _), + [111] = PINGROUP(111, uim1_reset, _, _, _, _, _, _, _, _), + [112] = PINGROUP(112, uim1_present, _, _, _, _, _, _, _, _), + [113] = PINGROUP(113, uim0_data, _, _, _, _, _, _, _, _), + [114] = PINGROUP(114, uim0_clk, _, _, _, _, _, _, _, _), + [115] = PINGROUP(115, uim0_reset, _, _, _, _, _, _, _, _), + [116] = PINGROUP(116, uim0_present, _, _, _, _, _, _, _, _), + [117] = PINGROUP(117, _, mss_grfc0, cmu_rng3, phase_flag, _, _, _, _, _), + [118] = PINGROUP(118, _, mss_grfc1, cmu_rng2, phase_flag, _, _, _, _, _), + [119] = PINGROUP(119, _, mss_grfc2, cmu_rng1, phase_flag, _, _, _, _, _), + [120] = PINGROUP(120, _, mss_grfc3, cmu_rng0, phase_flag, _, _, _, _, _), + [121] = PINGROUP(121, _, mss_grfc4, cri_trng0, phase_flag, _, _, _, _, _), + [122] = PINGROUP(122, _, mss_grfc5, cri_trng1, phase_flag, _, _, _, _, _), + [123] = PINGROUP(123, _, mss_grfc6, prng_rosc, phase_flag, _, _, _, _, _), + [124] = PINGROUP(124, _, mss_grfc7, cri_trng, phase_flag, _, _, _, _, _), + [125] = PINGROUP(125, _, mss_grfc8, phase_flag, _, _, _, _, _, _), + [126] = PINGROUP(126, _, mss_grfc9, phase_flag, _, _, _, _, _, _), + [127] = PINGROUP(127, coex_uart1, mss_grfc10, phase_flag, _, _, _, _, _, _), + [128] = PINGROUP(128, coex_uart1, mss_grfc11, phase_flag, _, _, _, _, _, _), + [129] = PINGROUP(129, nav_gpio0, phase_flag, _, _, _, _, _, _, _), + [130] = PINGROUP(130, nav_gpio1, phase_flag, _, _, _, _, _, _, _), + [131] = PINGROUP(131, mss_grfc12, nav_gpio2, pa_indicator, phase_flag, _, _, _, _, _), + [132] = PINGROUP(132, mss_grfc0, phase_flag, _, _, _, _, _, _, _), + [133] = PINGROUP(133, qlink0_request, _, _, _, _, _, _, _, _), + [134] = PINGROUP(134, qlink0_enable, _, _, _, _, _, _, _, _), + [135] = PINGROUP(135, qlink0_wmss, _, _, _, _, _, _, _, _), + [136] = PINGROUP(136, qlink1_request, _, _, _, _, _, _, _, _), + [137] = PINGROUP(137, qlink1_enable, _, _, _, _, _, _, _, _), + [138] = PINGROUP(138, qlink1_wmss, _, _, _, _, _, _, _, _), + [139] = PINGROUP(139, _, _, _, _, _, _, _, _, _), + [140] = PINGROUP(140, usb_phy, pll_clk, _, _, _, _, _, _, _), + [141] = PINGROUP(141, _, _, _, _, _, _, _, _, _), + [142] = PINGROUP(142, _, _, _, _, _, _, _, _, _), + [143] = PINGROUP(143, _, _, _, _, _, _, _, _, _), + [144] = PINGROUP(144, _, _, _, _, _, _, _, _, egpio), + [145] = PINGROUP(145, _, _, _, _, _, _, _, _, egpio), + [146] = PINGROUP(146, _, _, _, _, _, _, _, _, egpio), + [147] = PINGROUP(147, _, _, _, _, _, _, _, _, egpio), + [148] = PINGROUP(148, _, _, _, _, _, _, _, _, egpio), + [149] = PINGROUP(149, _, _, _, _, _, _, _, _, egpio), + [150] = PINGROUP(150, qdss, _, _, _, _, _, _, _, egpio), + [151] = PINGROUP(151, qdss, _, _, _, _, _, _, _, egpio), + [152] = PINGROUP(152, qdss, _, _, _, _, _, _, _, egpio), + [153] = PINGROUP(153, qdss, _, _, _, _, _, _, _, egpio), + [154] = PINGROUP(154, _, _, _, _, _, _, _, _, egpio), + [155] = PINGROUP(155, _, _, _, _, _, _, _, _, egpio), + [156] = PINGROUP(156, qdss_cti, _, _, _, _, _, _, _, egpio), + [157] = PINGROUP(157, qdss_cti, _, _, _, _, _, _, _, egpio), + [158] = PINGROUP(158, _, _, _, _, _, _, _, _, egpio), + [159] = PINGROUP(159, _, _, _, _, _, _, _, _, egpio), + [160] = PINGROUP(160, _, _, _, _, _, _, _, _, egpio), + [161] = PINGROUP(161, _, _, _, _, _, _, _, _, egpio), + [162] = PINGROUP(162, _, _, _, _, _, _, _, _, egpio), + [163] = PINGROUP(163, _, _, _, _, _, _, _, _, egpio), + [164] = PINGROUP(164, _, _, _, _, _, _, _, _, egpio), + [165] = PINGROUP(165, qdss_cti, _, _, _, _, _, _, _, egpio), + [166] = PINGROUP(166, qdss_cti, _, _, _, _, _, _, _, egpio), + [167] = PINGROUP(167, _, _, _, _, _, _, _, _, egpio), + [168] = PINGROUP(168, _, _, _, _, _, _, _, _, egpio), + [169] = PINGROUP(169, _, _, _, _, _, _, _, _, egpio), + [170] = PINGROUP(170, _, _, _, _, _, _, _, _, egpio), + [171] = PINGROUP(171, qdss, _, _, _, _, _, _, _, egpio), + [172] = PINGROUP(172, qdss, _, _, _, _, _, _, _, egpio), + [173] = PINGROUP(173, qdss, _, _, _, _, _, _, _, egpio), + [174] = PINGROUP(174, qdss, _, _, _, _, _, _, _, egpio), + [175] = UFS_RESET(ufs_reset, 0xbe000), + [176] = SDC_QDSD_PINGROUP(sdc1_rclk, 0xb3004, 0, 6), + [177] = SDC_QDSD_PINGROUP(sdc1_clk, 0xb3000, 13, 6), + [178] = SDC_QDSD_PINGROUP(sdc1_cmd, 0xb3000, 11, 3), + [179] = SDC_QDSD_PINGROUP(sdc1_data, 0xb3000, 9, 0), + [180] = SDC_QDSD_PINGROUP(sdc2_clk, 0xb4000, 14, 6), + [181] = SDC_QDSD_PINGROUP(sdc2_cmd, 0xb4000, 11, 3), + [182] = SDC_QDSD_PINGROUP(sdc2_data, 0xb4000, 9, 0), +}; + +static const struct msm_gpio_wakeirq_map sc7280_pdc_map[] = { + { 0, 134 }, { 3, 131 }, { 4, 121 }, { 7, 103 }, { 8, 155 }, + { 11, 93 }, { 12, 78 }, { 15, 79 }, { 16, 80 }, { 18, 81 }, + { 19, 107 }, { 20, 82 }, { 21, 83 }, { 23, 99 }, { 24, 86 }, + { 25, 95 }, { 27, 158 }, { 28, 159 }, { 31, 90 }, { 32, 144 }, + { 34, 77 }, { 35, 92 }, { 36, 157 }, { 39, 73 }, { 40, 97 }, + { 41, 98 }, { 43, 85 }, { 44, 100 }, { 45, 101 }, { 47, 102 }, + { 48, 74 }, { 51, 112 }, { 52, 156 }, { 54, 117 }, { 55, 84 }, + { 56, 108 }, { 59, 110 }, { 60, 111 }, { 61, 123 }, { 63, 104 }, + { 68, 127 }, { 72, 150 }, { 75, 133 }, { 77, 125 }, { 78, 105 }, + { 79, 106 }, { 80, 118 }, { 81, 119 }, { 82, 162 }, { 83, 122 }, + { 86, 75 }, { 88, 154 }, { 89, 124 }, { 90, 149 }, { 91, 76 }, + { 93, 128 }, { 95, 160 }, { 101, 126 }, { 102, 96 }, { 103, 116 }, + { 104, 114 }, { 112, 72 }, { 116, 135 }, { 117, 163 }, { 119, 137 }, + { 121, 138 }, { 123, 139 }, { 125, 140 }, { 127, 141 }, { 128, 165 }, + { 129, 143 }, { 130, 94 }, { 131, 145 }, { 133, 146 }, { 136, 147 }, + { 140, 148 }, { 141, 115 }, { 142, 113 }, { 145, 130 }, { 148, 132 }, + { 150, 87 }, { 151, 88 }, { 153, 89 }, { 155, 164 }, { 156, 129 }, + { 157, 161 }, { 158, 120 }, { 161, 136 }, { 163, 142 }, { 172, 166 }, + { 174, 167 }, +}; + +static const struct msm_pinctrl_soc_data sc7280_pinctrl = { + .pins = sc7280_pins, + .npins = ARRAY_SIZE(sc7280_pins), + .functions = sc7280_functions, + .nfunctions = ARRAY_SIZE(sc7280_functions), + .groups = sc7280_groups, + .ngroups = ARRAY_SIZE(sc7280_groups), + .ngpios = 176, + .wakeirq_map = sc7280_pdc_map, + .nwakeirq_map = ARRAY_SIZE(sc7280_pdc_map), + .egpio_func = 9, +}; + +static int sc7280_pinctrl_probe(struct platform_device *pdev) +{ + return msm_pinctrl_probe(pdev, &sc7280_pinctrl); +} + +static const struct of_device_id sc7280_pinctrl_of_match[] = { + { .compatible = "qcom,sc7280-pinctrl", }, + { }, +}; + +static struct platform_driver sc7280_pinctrl_driver = { + .driver = { + .name = "sc7280-pinctrl", + .pm = &msm_pinctrl_dev_pm_ops, + .of_match_table = sc7280_pinctrl_of_match, + }, + .probe = sc7280_pinctrl_probe, + .remove = msm_pinctrl_remove, +}; + +static int __init sc7280_pinctrl_init(void) +{ + return platform_driver_register(&sc7280_pinctrl_driver); +} +arch_initcall(sc7280_pinctrl_init); + +static void __exit sc7280_pinctrl_exit(void) +{ + platform_driver_unregister(&sc7280_pinctrl_driver); +} +module_exit(sc7280_pinctrl_exit); + +MODULE_DESCRIPTION("QTI sc7280 pinctrl driver"); +MODULE_LICENSE("GPL v2"); +MODULE_DEVICE_TABLE(of, sc7280_pinctrl_of_match); diff --git a/drivers/pinctrl/qcom/pinctrl-sc8180x.c b/drivers/pinctrl/qcom/pinctrl-sc8180x.c new file mode 100644 index 0000000000..d6a79ad41a --- /dev/null +++ b/drivers/pinctrl/qcom/pinctrl-sc8180x.c @@ -0,0 +1,1739 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. + * Copyright (c) 2020-2021, Linaro Ltd. + */ + +#include <linux/module.h> +#include <linux/of.h> +#include <linux/platform_device.h> + +#include "pinctrl-msm.h" + +static const char * const sc8180x_tiles[] = { + "south", + "east", + "west" +}; + +enum { + SOUTH, + EAST, + WEST +}; + +/* + * ACPI DSDT has one single memory resource for TLMM. The offsets below are + * used to locate different tiles for ACPI probe. + */ +struct tile_info { + u32 offset; + u32 size; +}; + +static const struct tile_info sc8180x_tile_info[] = { + { 0x00d00000, 0x00300000, }, + { 0x00500000, 0x00700000, }, + { 0x00100000, 0x00300000, }, +}; + +#define REG_SIZE 0x1000 +#define PINGROUP_OFFSET(id, _tile, offset, f1, f2, f3, f4, f5, f6, f7, f8, f9) \ + { \ + .grp = PINCTRL_PINGROUP("gpio" #id, \ + gpio##id##_pins, \ + ARRAY_SIZE(gpio##id##_pins)), \ + .funcs = (int[]){ \ + msm_mux_gpio, /* gpio mode */ \ + msm_mux_##f1, \ + msm_mux_##f2, \ + msm_mux_##f3, \ + msm_mux_##f4, \ + msm_mux_##f5, \ + msm_mux_##f6, \ + msm_mux_##f7, \ + msm_mux_##f8, \ + msm_mux_##f9 \ + }, \ + .nfuncs = 10, \ + .ctl_reg = REG_SIZE * id + offset, \ + .io_reg = REG_SIZE * id + 0x4 + offset, \ + .intr_cfg_reg = REG_SIZE * id + 0x8 + offset, \ + .intr_status_reg = REG_SIZE * id + 0xc + offset,\ + .intr_target_reg = REG_SIZE * id + 0x8 + offset,\ + .tile = _tile, \ + .mux_bit = 2, \ + .pull_bit = 0, \ + .drv_bit = 6, \ + .oe_bit = 9, \ + .in_bit = 0, \ + .out_bit = 1, \ + .intr_enable_bit = 0, \ + .intr_status_bit = 0, \ + .intr_target_bit = 5, \ + .intr_target_kpss_val = 3, \ + .intr_raw_status_bit = 4, \ + .intr_polarity_bit = 1, \ + .intr_detection_bit = 2, \ + .intr_detection_width = 2, \ + } + +#define PINGROUP(id, _tile, f1, f2, f3, f4, f5, f6, f7, f8, f9) \ + PINGROUP_OFFSET(id, _tile, 0x0, f1, f2, f3, f4, f5, f6, f7, f8, f9) + +#define SDC_QDSD_PINGROUP(pg_name, ctl, pull, drv) \ + { \ + .grp = PINCTRL_PINGROUP(#pg_name, \ + pg_name##_pins, \ + ARRAY_SIZE(pg_name##_pins)), \ + .ctl_reg = ctl, \ + .io_reg = 0, \ + .intr_cfg_reg = 0, \ + .intr_status_reg = 0, \ + .intr_target_reg = 0, \ + .tile = EAST, \ + .mux_bit = -1, \ + .pull_bit = pull, \ + .drv_bit = drv, \ + .oe_bit = -1, \ + .in_bit = -1, \ + .out_bit = -1, \ + .intr_enable_bit = -1, \ + .intr_status_bit = -1, \ + .intr_target_bit = -1, \ + .intr_raw_status_bit = -1, \ + .intr_polarity_bit = -1, \ + .intr_detection_bit = -1, \ + .intr_detection_width = -1, \ + } + +#define UFS_RESET(pg_name) \ + { \ + .grp = PINCTRL_PINGROUP(#pg_name, \ + pg_name##_pins, \ + ARRAY_SIZE(pg_name##_pins)), \ + .ctl_reg = 0xb6000, \ + .io_reg = 0xb6004, \ + .intr_cfg_reg = 0, \ + .intr_status_reg = 0, \ + .intr_target_reg = 0, \ + .tile = SOUTH, \ + .mux_bit = -1, \ + .pull_bit = 3, \ + .drv_bit = 0, \ + .oe_bit = -1, \ + .in_bit = -1, \ + .out_bit = 0, \ + .intr_enable_bit = -1, \ + .intr_status_bit = -1, \ + .intr_target_bit = -1, \ + .intr_raw_status_bit = -1, \ + .intr_polarity_bit = -1, \ + .intr_detection_bit = -1, \ + .intr_detection_width = -1, \ + } +static const struct pinctrl_pin_desc sc8180x_pins[] = { + PINCTRL_PIN(0, "GPIO_0"), + PINCTRL_PIN(1, "GPIO_1"), + PINCTRL_PIN(2, "GPIO_2"), + PINCTRL_PIN(3, "GPIO_3"), + PINCTRL_PIN(4, "GPIO_4"), + PINCTRL_PIN(5, "GPIO_5"), + PINCTRL_PIN(6, "GPIO_6"), + PINCTRL_PIN(7, "GPIO_7"), + PINCTRL_PIN(8, "GPIO_8"), + PINCTRL_PIN(9, "GPIO_9"), + PINCTRL_PIN(10, "GPIO_10"), + PINCTRL_PIN(11, "GPIO_11"), + PINCTRL_PIN(12, "GPIO_12"), + PINCTRL_PIN(13, "GPIO_13"), + PINCTRL_PIN(14, "GPIO_14"), + PINCTRL_PIN(15, "GPIO_15"), + PINCTRL_PIN(16, "GPIO_16"), + PINCTRL_PIN(17, "GPIO_17"), + PINCTRL_PIN(18, "GPIO_18"), + PINCTRL_PIN(19, "GPIO_19"), + PINCTRL_PIN(20, "GPIO_20"), + PINCTRL_PIN(21, "GPIO_21"), + PINCTRL_PIN(22, "GPIO_22"), + PINCTRL_PIN(23, "GPIO_23"), + PINCTRL_PIN(24, "GPIO_24"), + PINCTRL_PIN(25, "GPIO_25"), + PINCTRL_PIN(26, "GPIO_26"), + PINCTRL_PIN(27, "GPIO_27"), + PINCTRL_PIN(28, "GPIO_28"), + PINCTRL_PIN(29, "GPIO_29"), + PINCTRL_PIN(30, "GPIO_30"), + PINCTRL_PIN(31, "GPIO_31"), + PINCTRL_PIN(32, "GPIO_32"), + PINCTRL_PIN(33, "GPIO_33"), + PINCTRL_PIN(34, "GPIO_34"), + PINCTRL_PIN(35, "GPIO_35"), + PINCTRL_PIN(36, "GPIO_36"), + PINCTRL_PIN(37, "GPIO_37"), + PINCTRL_PIN(38, "GPIO_38"), + PINCTRL_PIN(39, "GPIO_39"), + PINCTRL_PIN(40, "GPIO_40"), + PINCTRL_PIN(41, "GPIO_41"), + PINCTRL_PIN(42, "GPIO_42"), + PINCTRL_PIN(43, "GPIO_43"), + PINCTRL_PIN(44, "GPIO_44"), + PINCTRL_PIN(45, "GPIO_45"), + PINCTRL_PIN(46, "GPIO_46"), + PINCTRL_PIN(47, "GPIO_47"), + PINCTRL_PIN(48, "GPIO_48"), + PINCTRL_PIN(49, "GPIO_49"), + PINCTRL_PIN(50, "GPIO_50"), + PINCTRL_PIN(51, "GPIO_51"), + PINCTRL_PIN(52, "GPIO_52"), + PINCTRL_PIN(53, "GPIO_53"), + PINCTRL_PIN(54, "GPIO_54"), + PINCTRL_PIN(55, "GPIO_55"), + PINCTRL_PIN(56, "GPIO_56"), + PINCTRL_PIN(57, "GPIO_57"), + PINCTRL_PIN(58, "GPIO_58"), + PINCTRL_PIN(59, "GPIO_59"), + PINCTRL_PIN(60, "GPIO_60"), + PINCTRL_PIN(61, "GPIO_61"), + PINCTRL_PIN(62, "GPIO_62"), + PINCTRL_PIN(63, "GPIO_63"), + PINCTRL_PIN(64, "GPIO_64"), + PINCTRL_PIN(65, "GPIO_65"), + PINCTRL_PIN(66, "GPIO_66"), + PINCTRL_PIN(67, "GPIO_67"), + PINCTRL_PIN(68, "GPIO_68"), + PINCTRL_PIN(69, "GPIO_69"), + PINCTRL_PIN(70, "GPIO_70"), + PINCTRL_PIN(71, "GPIO_71"), + PINCTRL_PIN(72, "GPIO_72"), + PINCTRL_PIN(73, "GPIO_73"), + PINCTRL_PIN(74, "GPIO_74"), + PINCTRL_PIN(75, "GPIO_75"), + PINCTRL_PIN(76, "GPIO_76"), + PINCTRL_PIN(77, "GPIO_77"), + PINCTRL_PIN(78, "GPIO_78"), + PINCTRL_PIN(79, "GPIO_79"), + PINCTRL_PIN(80, "GPIO_80"), + PINCTRL_PIN(81, "GPIO_81"), + PINCTRL_PIN(82, "GPIO_82"), + PINCTRL_PIN(83, "GPIO_83"), + PINCTRL_PIN(84, "GPIO_84"), + PINCTRL_PIN(85, "GPIO_85"), + PINCTRL_PIN(86, "GPIO_86"), + PINCTRL_PIN(87, "GPIO_87"), + PINCTRL_PIN(88, "GPIO_88"), + PINCTRL_PIN(89, "GPIO_89"), + PINCTRL_PIN(90, "GPIO_90"), + PINCTRL_PIN(91, "GPIO_91"), + PINCTRL_PIN(92, "GPIO_92"), + PINCTRL_PIN(93, "GPIO_93"), + PINCTRL_PIN(94, "GPIO_94"), + PINCTRL_PIN(95, "GPIO_95"), + PINCTRL_PIN(96, "GPIO_96"), + PINCTRL_PIN(97, "GPIO_97"), + PINCTRL_PIN(98, "GPIO_98"), + PINCTRL_PIN(99, "GPIO_99"), + PINCTRL_PIN(100, "GPIO_100"), + PINCTRL_PIN(101, "GPIO_101"), + PINCTRL_PIN(102, "GPIO_102"), + PINCTRL_PIN(103, "GPIO_103"), + PINCTRL_PIN(104, "GPIO_104"), + PINCTRL_PIN(105, "GPIO_105"), + PINCTRL_PIN(106, "GPIO_106"), + PINCTRL_PIN(107, "GPIO_107"), + PINCTRL_PIN(108, "GPIO_108"), + PINCTRL_PIN(109, "GPIO_109"), + PINCTRL_PIN(110, "GPIO_110"), + PINCTRL_PIN(111, "GPIO_111"), + PINCTRL_PIN(112, "GPIO_112"), + PINCTRL_PIN(113, "GPIO_113"), + PINCTRL_PIN(114, "GPIO_114"), + PINCTRL_PIN(115, "GPIO_115"), + PINCTRL_PIN(116, "GPIO_116"), + PINCTRL_PIN(117, "GPIO_117"), + PINCTRL_PIN(118, "GPIO_118"), + PINCTRL_PIN(119, "GPIO_119"), + PINCTRL_PIN(120, "GPIO_120"), + PINCTRL_PIN(121, "GPIO_121"), + PINCTRL_PIN(122, "GPIO_122"), + PINCTRL_PIN(123, "GPIO_123"), + PINCTRL_PIN(124, "GPIO_124"), + PINCTRL_PIN(125, "GPIO_125"), + PINCTRL_PIN(126, "GPIO_126"), + PINCTRL_PIN(127, "GPIO_127"), + PINCTRL_PIN(128, "GPIO_128"), + PINCTRL_PIN(129, "GPIO_129"), + PINCTRL_PIN(130, "GPIO_130"), + PINCTRL_PIN(131, "GPIO_131"), + PINCTRL_PIN(132, "GPIO_132"), + PINCTRL_PIN(133, "GPIO_133"), + PINCTRL_PIN(134, "GPIO_134"), + PINCTRL_PIN(135, "GPIO_135"), + PINCTRL_PIN(136, "GPIO_136"), + PINCTRL_PIN(137, "GPIO_137"), + PINCTRL_PIN(138, "GPIO_138"), + PINCTRL_PIN(139, "GPIO_139"), + PINCTRL_PIN(140, "GPIO_140"), + PINCTRL_PIN(141, "GPIO_141"), + PINCTRL_PIN(142, "GPIO_142"), + PINCTRL_PIN(143, "GPIO_143"), + PINCTRL_PIN(144, "GPIO_144"), + PINCTRL_PIN(145, "GPIO_145"), + PINCTRL_PIN(146, "GPIO_146"), + PINCTRL_PIN(147, "GPIO_147"), + PINCTRL_PIN(148, "GPIO_148"), + PINCTRL_PIN(149, "GPIO_149"), + PINCTRL_PIN(150, "GPIO_150"), + PINCTRL_PIN(151, "GPIO_151"), + PINCTRL_PIN(152, "GPIO_152"), + PINCTRL_PIN(153, "GPIO_153"), + PINCTRL_PIN(154, "GPIO_154"), + PINCTRL_PIN(155, "GPIO_155"), + PINCTRL_PIN(156, "GPIO_156"), + PINCTRL_PIN(157, "GPIO_157"), + PINCTRL_PIN(158, "GPIO_158"), + PINCTRL_PIN(159, "GPIO_159"), + PINCTRL_PIN(160, "GPIO_160"), + PINCTRL_PIN(161, "GPIO_161"), + PINCTRL_PIN(162, "GPIO_162"), + PINCTRL_PIN(163, "GPIO_163"), + PINCTRL_PIN(164, "GPIO_164"), + PINCTRL_PIN(165, "GPIO_165"), + PINCTRL_PIN(166, "GPIO_166"), + PINCTRL_PIN(167, "GPIO_167"), + PINCTRL_PIN(168, "GPIO_168"), + PINCTRL_PIN(169, "GPIO_169"), + PINCTRL_PIN(170, "GPIO_170"), + PINCTRL_PIN(171, "GPIO_171"), + PINCTRL_PIN(172, "GPIO_172"), + PINCTRL_PIN(173, "GPIO_173"), + PINCTRL_PIN(174, "GPIO_174"), + PINCTRL_PIN(175, "GPIO_175"), + PINCTRL_PIN(176, "GPIO_176"), + PINCTRL_PIN(177, "GPIO_177"), + PINCTRL_PIN(178, "GPIO_178"), + PINCTRL_PIN(179, "GPIO_179"), + PINCTRL_PIN(180, "GPIO_180"), + PINCTRL_PIN(181, "GPIO_181"), + PINCTRL_PIN(182, "GPIO_182"), + PINCTRL_PIN(183, "GPIO_183"), + PINCTRL_PIN(184, "GPIO_184"), + PINCTRL_PIN(185, "GPIO_185"), + PINCTRL_PIN(186, "GPIO_186"), + PINCTRL_PIN(187, "GPIO_187"), + PINCTRL_PIN(188, "GPIO_188"), + PINCTRL_PIN(189, "GPIO_189"), + PINCTRL_PIN(190, "UFS_RESET"), + PINCTRL_PIN(191, "SDC2_CLK"), + PINCTRL_PIN(192, "SDC2_CMD"), + PINCTRL_PIN(193, "SDC2_DATA"), +}; + +#define DECLARE_MSM_GPIO_PINS(pin) \ + static const unsigned int gpio##pin##_pins[] = { pin } +DECLARE_MSM_GPIO_PINS(0); +DECLARE_MSM_GPIO_PINS(1); +DECLARE_MSM_GPIO_PINS(2); +DECLARE_MSM_GPIO_PINS(3); +DECLARE_MSM_GPIO_PINS(4); +DECLARE_MSM_GPIO_PINS(5); +DECLARE_MSM_GPIO_PINS(6); +DECLARE_MSM_GPIO_PINS(7); +DECLARE_MSM_GPIO_PINS(8); +DECLARE_MSM_GPIO_PINS(9); +DECLARE_MSM_GPIO_PINS(10); +DECLARE_MSM_GPIO_PINS(11); +DECLARE_MSM_GPIO_PINS(12); +DECLARE_MSM_GPIO_PINS(13); +DECLARE_MSM_GPIO_PINS(14); +DECLARE_MSM_GPIO_PINS(15); +DECLARE_MSM_GPIO_PINS(16); +DECLARE_MSM_GPIO_PINS(17); +DECLARE_MSM_GPIO_PINS(18); +DECLARE_MSM_GPIO_PINS(19); +DECLARE_MSM_GPIO_PINS(20); +DECLARE_MSM_GPIO_PINS(21); +DECLARE_MSM_GPIO_PINS(22); +DECLARE_MSM_GPIO_PINS(23); +DECLARE_MSM_GPIO_PINS(24); +DECLARE_MSM_GPIO_PINS(25); +DECLARE_MSM_GPIO_PINS(26); +DECLARE_MSM_GPIO_PINS(27); +DECLARE_MSM_GPIO_PINS(28); +DECLARE_MSM_GPIO_PINS(29); +DECLARE_MSM_GPIO_PINS(30); +DECLARE_MSM_GPIO_PINS(31); +DECLARE_MSM_GPIO_PINS(32); +DECLARE_MSM_GPIO_PINS(33); +DECLARE_MSM_GPIO_PINS(34); +DECLARE_MSM_GPIO_PINS(35); +DECLARE_MSM_GPIO_PINS(36); +DECLARE_MSM_GPIO_PINS(37); +DECLARE_MSM_GPIO_PINS(38); +DECLARE_MSM_GPIO_PINS(39); +DECLARE_MSM_GPIO_PINS(40); +DECLARE_MSM_GPIO_PINS(41); +DECLARE_MSM_GPIO_PINS(42); +DECLARE_MSM_GPIO_PINS(43); +DECLARE_MSM_GPIO_PINS(44); +DECLARE_MSM_GPIO_PINS(45); +DECLARE_MSM_GPIO_PINS(46); +DECLARE_MSM_GPIO_PINS(47); +DECLARE_MSM_GPIO_PINS(48); +DECLARE_MSM_GPIO_PINS(49); +DECLARE_MSM_GPIO_PINS(50); +DECLARE_MSM_GPIO_PINS(51); +DECLARE_MSM_GPIO_PINS(52); +DECLARE_MSM_GPIO_PINS(53); +DECLARE_MSM_GPIO_PINS(54); +DECLARE_MSM_GPIO_PINS(55); +DECLARE_MSM_GPIO_PINS(56); +DECLARE_MSM_GPIO_PINS(57); +DECLARE_MSM_GPIO_PINS(58); +DECLARE_MSM_GPIO_PINS(59); +DECLARE_MSM_GPIO_PINS(60); +DECLARE_MSM_GPIO_PINS(61); +DECLARE_MSM_GPIO_PINS(62); +DECLARE_MSM_GPIO_PINS(63); +DECLARE_MSM_GPIO_PINS(64); +DECLARE_MSM_GPIO_PINS(65); +DECLARE_MSM_GPIO_PINS(66); +DECLARE_MSM_GPIO_PINS(67); +DECLARE_MSM_GPIO_PINS(68); +DECLARE_MSM_GPIO_PINS(69); +DECLARE_MSM_GPIO_PINS(70); +DECLARE_MSM_GPIO_PINS(71); +DECLARE_MSM_GPIO_PINS(72); +DECLARE_MSM_GPIO_PINS(73); +DECLARE_MSM_GPIO_PINS(74); +DECLARE_MSM_GPIO_PINS(75); +DECLARE_MSM_GPIO_PINS(76); +DECLARE_MSM_GPIO_PINS(77); +DECLARE_MSM_GPIO_PINS(78); +DECLARE_MSM_GPIO_PINS(79); +DECLARE_MSM_GPIO_PINS(80); +DECLARE_MSM_GPIO_PINS(81); +DECLARE_MSM_GPIO_PINS(82); +DECLARE_MSM_GPIO_PINS(83); +DECLARE_MSM_GPIO_PINS(84); +DECLARE_MSM_GPIO_PINS(85); +DECLARE_MSM_GPIO_PINS(86); +DECLARE_MSM_GPIO_PINS(87); +DECLARE_MSM_GPIO_PINS(88); +DECLARE_MSM_GPIO_PINS(89); +DECLARE_MSM_GPIO_PINS(90); +DECLARE_MSM_GPIO_PINS(91); +DECLARE_MSM_GPIO_PINS(92); +DECLARE_MSM_GPIO_PINS(93); +DECLARE_MSM_GPIO_PINS(94); +DECLARE_MSM_GPIO_PINS(95); +DECLARE_MSM_GPIO_PINS(96); +DECLARE_MSM_GPIO_PINS(97); +DECLARE_MSM_GPIO_PINS(98); +DECLARE_MSM_GPIO_PINS(99); +DECLARE_MSM_GPIO_PINS(100); +DECLARE_MSM_GPIO_PINS(101); +DECLARE_MSM_GPIO_PINS(102); +DECLARE_MSM_GPIO_PINS(103); +DECLARE_MSM_GPIO_PINS(104); +DECLARE_MSM_GPIO_PINS(105); +DECLARE_MSM_GPIO_PINS(106); +DECLARE_MSM_GPIO_PINS(107); +DECLARE_MSM_GPIO_PINS(108); +DECLARE_MSM_GPIO_PINS(109); +DECLARE_MSM_GPIO_PINS(110); +DECLARE_MSM_GPIO_PINS(111); +DECLARE_MSM_GPIO_PINS(112); +DECLARE_MSM_GPIO_PINS(113); +DECLARE_MSM_GPIO_PINS(114); +DECLARE_MSM_GPIO_PINS(115); +DECLARE_MSM_GPIO_PINS(116); +DECLARE_MSM_GPIO_PINS(117); +DECLARE_MSM_GPIO_PINS(118); +DECLARE_MSM_GPIO_PINS(119); +DECLARE_MSM_GPIO_PINS(120); +DECLARE_MSM_GPIO_PINS(121); +DECLARE_MSM_GPIO_PINS(122); +DECLARE_MSM_GPIO_PINS(123); +DECLARE_MSM_GPIO_PINS(124); +DECLARE_MSM_GPIO_PINS(125); +DECLARE_MSM_GPIO_PINS(126); +DECLARE_MSM_GPIO_PINS(127); +DECLARE_MSM_GPIO_PINS(128); +DECLARE_MSM_GPIO_PINS(129); +DECLARE_MSM_GPIO_PINS(130); +DECLARE_MSM_GPIO_PINS(131); +DECLARE_MSM_GPIO_PINS(132); +DECLARE_MSM_GPIO_PINS(133); +DECLARE_MSM_GPIO_PINS(134); +DECLARE_MSM_GPIO_PINS(135); +DECLARE_MSM_GPIO_PINS(136); +DECLARE_MSM_GPIO_PINS(137); +DECLARE_MSM_GPIO_PINS(138); +DECLARE_MSM_GPIO_PINS(139); +DECLARE_MSM_GPIO_PINS(140); +DECLARE_MSM_GPIO_PINS(141); +DECLARE_MSM_GPIO_PINS(142); +DECLARE_MSM_GPIO_PINS(143); +DECLARE_MSM_GPIO_PINS(144); +DECLARE_MSM_GPIO_PINS(145); +DECLARE_MSM_GPIO_PINS(146); +DECLARE_MSM_GPIO_PINS(147); +DECLARE_MSM_GPIO_PINS(148); +DECLARE_MSM_GPIO_PINS(149); +DECLARE_MSM_GPIO_PINS(150); +DECLARE_MSM_GPIO_PINS(151); +DECLARE_MSM_GPIO_PINS(152); +DECLARE_MSM_GPIO_PINS(153); +DECLARE_MSM_GPIO_PINS(154); +DECLARE_MSM_GPIO_PINS(155); +DECLARE_MSM_GPIO_PINS(156); +DECLARE_MSM_GPIO_PINS(157); +DECLARE_MSM_GPIO_PINS(158); +DECLARE_MSM_GPIO_PINS(159); +DECLARE_MSM_GPIO_PINS(160); +DECLARE_MSM_GPIO_PINS(161); +DECLARE_MSM_GPIO_PINS(162); +DECLARE_MSM_GPIO_PINS(163); +DECLARE_MSM_GPIO_PINS(164); +DECLARE_MSM_GPIO_PINS(165); +DECLARE_MSM_GPIO_PINS(166); +DECLARE_MSM_GPIO_PINS(167); +DECLARE_MSM_GPIO_PINS(168); +DECLARE_MSM_GPIO_PINS(169); +DECLARE_MSM_GPIO_PINS(170); +DECLARE_MSM_GPIO_PINS(171); +DECLARE_MSM_GPIO_PINS(172); +DECLARE_MSM_GPIO_PINS(173); +DECLARE_MSM_GPIO_PINS(174); +DECLARE_MSM_GPIO_PINS(175); +DECLARE_MSM_GPIO_PINS(176); +DECLARE_MSM_GPIO_PINS(177); +DECLARE_MSM_GPIO_PINS(178); +DECLARE_MSM_GPIO_PINS(179); +DECLARE_MSM_GPIO_PINS(180); +DECLARE_MSM_GPIO_PINS(181); +DECLARE_MSM_GPIO_PINS(182); +DECLARE_MSM_GPIO_PINS(183); +DECLARE_MSM_GPIO_PINS(184); +DECLARE_MSM_GPIO_PINS(185); +DECLARE_MSM_GPIO_PINS(186); +DECLARE_MSM_GPIO_PINS(187); +DECLARE_MSM_GPIO_PINS(188); +DECLARE_MSM_GPIO_PINS(189); + +static const unsigned int ufs_reset_pins[] = { 190 }; +static const unsigned int sdc2_clk_pins[] = { 191 }; +static const unsigned int sdc2_cmd_pins[] = { 192 }; +static const unsigned int sdc2_data_pins[] = { 193 }; + +enum sc8180x_functions { + msm_mux_adsp_ext, + msm_mux_agera_pll, + msm_mux_aoss_cti, + msm_mux_atest_char, + msm_mux_atest_tsens, + msm_mux_atest_tsens2, + msm_mux_atest_usb0, + msm_mux_atest_usb1, + msm_mux_atest_usb2, + msm_mux_atest_usb3, + msm_mux_atest_usb4, + msm_mux_audio_ref, + msm_mux_btfm_slimbus, + msm_mux_cam_mclk, + msm_mux_cci_async, + msm_mux_cci_i2c, + msm_mux_cci_timer0, + msm_mux_cci_timer1, + msm_mux_cci_timer2, + msm_mux_cci_timer3, + msm_mux_cci_timer4, + msm_mux_cci_timer5, + msm_mux_cci_timer6, + msm_mux_cci_timer7, + msm_mux_cci_timer8, + msm_mux_cci_timer9, + msm_mux_cri_trng, + msm_mux_dbg_out, + msm_mux_ddr_bist, + msm_mux_ddr_pxi, + msm_mux_debug_hot, + msm_mux_dp_hot, + msm_mux_edp_hot, + msm_mux_edp_lcd, + msm_mux_emac_phy, + msm_mux_emac_pps, + msm_mux_gcc_gp1, + msm_mux_gcc_gp2, + msm_mux_gcc_gp3, + msm_mux_gcc_gp4, + msm_mux_gcc_gp5, + msm_mux_gpio, + msm_mux_gps, + msm_mux_grfc, + msm_mux_hs1_mi2s, + msm_mux_hs2_mi2s, + msm_mux_hs3_mi2s, + msm_mux_jitter_bist, + msm_mux_lpass_slimbus, + msm_mux_m_voc, + msm_mux_mdp_vsync, + msm_mux_mdp_vsync0, + msm_mux_mdp_vsync1, + msm_mux_mdp_vsync2, + msm_mux_mdp_vsync3, + msm_mux_mdp_vsync4, + msm_mux_mdp_vsync5, + msm_mux_mss_lte, + msm_mux_nav_pps, + msm_mux_pa_indicator, + msm_mux_pci_e0, + msm_mux_pci_e1, + msm_mux_pci_e2, + msm_mux_pci_e3, + msm_mux_phase_flag, + msm_mux_pll_bist, + msm_mux_pll_bypassnl, + msm_mux_pll_reset, + msm_mux_pri_mi2s, + msm_mux_pri_mi2s_ws, + msm_mux_prng_rosc, + msm_mux_qdss_cti, + msm_mux_qdss_gpio, + msm_mux_qlink, + msm_mux_qspi0, + msm_mux_qspi0_clk, + msm_mux_qspi0_cs, + msm_mux_qspi1, + msm_mux_qspi1_clk, + msm_mux_qspi1_cs, + msm_mux_qua_mi2s, + msm_mux_qup0, + msm_mux_qup1, + msm_mux_qup2, + msm_mux_qup3, + msm_mux_qup4, + msm_mux_qup5, + msm_mux_qup6, + msm_mux_qup7, + msm_mux_qup8, + msm_mux_qup9, + msm_mux_qup10, + msm_mux_qup11, + msm_mux_qup12, + msm_mux_qup13, + msm_mux_qup14, + msm_mux_qup15, + msm_mux_qup16, + msm_mux_qup17, + msm_mux_qup18, + msm_mux_qup19, + msm_mux_qup_l4, + msm_mux_qup_l5, + msm_mux_qup_l6, + msm_mux_rgmii, + msm_mux_sd_write, + msm_mux_sdc4, + msm_mux_sdc4_clk, + msm_mux_sdc4_cmd, + msm_mux_sec_mi2s, + msm_mux_sp_cmu, + msm_mux_spkr_i2s, + msm_mux_ter_mi2s, + msm_mux_tgu, + msm_mux_tsense_pwm1, + msm_mux_tsense_pwm2, + msm_mux_tsif1, + msm_mux_tsif2, + msm_mux_uim1, + msm_mux_uim2, + msm_mux_uim_batt, + msm_mux_usb0_phy, + msm_mux_usb1_phy, + msm_mux_usb2phy_ac, + msm_mux_vfr_1, + msm_mux_vsense_trigger, + msm_mux_wlan1_adc, + msm_mux_wlan2_adc, + msm_mux_wmss_reset, + msm_mux__, +}; + +static const char * const adsp_ext_groups[] = { + "gpio115", +}; + +static const char * const agera_pll_groups[] = { + "gpio37", +}; + +static const char * const aoss_cti_groups[] = { + "gpio113", +}; + +static const char * const atest_char_groups[] = { + "gpio133", "gpio134", "gpio135", "gpio140", "gpio142", +}; + +static const char * const atest_tsens2_groups[] = { + "gpio62", +}; + +static const char * const atest_tsens_groups[] = { + "gpio93", +}; + +static const char * const atest_usb0_groups[] = { + "gpio90", "gpio91", "gpio92", "gpio93", "gpio94", +}; + +static const char * const atest_usb1_groups[] = { + "gpio60", "gpio62", "gpio63", "gpio64", "gpio65", +}; + +static const char * const atest_usb2_groups[] = { + "gpio34", "gpio95", "gpio102", "gpio121", "gpio122", +}; + +static const char * const atest_usb3_groups[] = { + "gpio68", "gpio71", "gpio72", "gpio73", "gpio74", +}; + +static const char * const atest_usb4_groups[] = { + "gpio75", "gpio76", "gpio77", "gpio78", "gpio88", +}; + +static const char * const audio_ref_groups[] = { + "gpio148", +}; + +static const char * const btfm_slimbus_groups[] = { + "gpio153", "gpio154", +}; + +static const char * const cam_mclk_groups[] = { + "gpio13", "gpio14", "gpio15", "gpio16", "gpio25", "gpio179", "gpio180", + "gpio181", +}; + +static const char * const cci_async_groups[] = { + "gpio24", "gpio25", "gpio26", "gpio176", "gpio185", "gpio186", +}; + +static const char * const cci_i2c_groups[] = { + "gpio0", "gpio1", "gpio2", "gpio3", "gpio17", "gpio18", "gpio19", + "gpio20", "gpio31", "gpio32", "gpio33", "gpio34", "gpio39", "gpio40", + "gpio41", "gpio42", +}; + +static const char * const cci_timer0_groups[] = { + "gpio21", +}; + +static const char * const cci_timer1_groups[] = { + "gpio22", +}; + +static const char * const cci_timer2_groups[] = { + "gpio23", +}; + +static const char * const cci_timer3_groups[] = { + "gpio24", +}; + +static const char * const cci_timer4_groups[] = { + "gpio178", +}; + +static const char * const cci_timer5_groups[] = { + "gpio182", +}; + +static const char * const cci_timer6_groups[] = { + "gpio183", +}; + +static const char * const cci_timer7_groups[] = { + "gpio184", +}; + +static const char * const cci_timer8_groups[] = { + "gpio185", +}; + +static const char * const cci_timer9_groups[] = { + "gpio186", +}; + +static const char * const cri_trng_groups[] = { + "gpio159", + "gpio160", + "gpio161", +}; + +static const char * const dbg_out_groups[] = { + "gpio34", +}; + +static const char * const ddr_bist_groups[] = { + "gpio98", "gpio99", "gpio145", "gpio146", +}; + +static const char * const ddr_pxi_groups[] = { + "gpio60", "gpio62", "gpio63", "gpio64", "gpio65", "gpio68", "gpio71", + "gpio72", "gpio73", "gpio74", "gpio75", "gpio76", "gpio77", "gpio78", + "gpio88", "gpio90", +}; + +static const char * const debug_hot_groups[] = { + "gpio7", +}; + +static const char * const dp_hot_groups[] = { + "gpio189", +}; + +static const char * const edp_hot_groups[] = { + "gpio10", +}; + +static const char * const edp_lcd_groups[] = { + "gpio11", +}; + +static const char * const emac_phy_groups[] = { + "gpio124", +}; + +static const char * const emac_pps_groups[] = { + "gpio81", +}; + +static const char * const gcc_gp1_groups[] = { + "gpio131", "gpio136", +}; + +static const char * const gcc_gp2_groups[] = { + "gpio21", "gpio137", +}; + +static const char * const gcc_gp3_groups[] = { + "gpio22", "gpio138", +}; + +static const char * const gcc_gp4_groups[] = { + "gpio139", "gpio182", +}; + +static const char * const gcc_gp5_groups[] = { + "gpio140", "gpio183", +}; + +static const char * const gpio_groups[] = { + "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7", + "gpio8", "gpio9", "gpio10", "gpio11", "gpio12", "gpio12", "gpio13", + "gpio14", "gpio15", "gpio16", "gpio17", "gpio18", "gpio19", "gpio20", + "gpio21", "gpio22", "gpio23", "gpio24", "gpio25", "gpio26", "gpio27", + "gpio28", "gpio29", "gpio30", "gpio31", "gpio32", "gpio33", "gpio34", + "gpio35", "gpio36", "gpio37", "gpio38", "gpio39", "gpio40", "gpio41", + "gpio42", "gpio43", "gpio44", "gpio45", "gpio46", "gpio47", "gpio48", + "gpio49", "gpio50", "gpio51", "gpio52", "gpio53", "gpio54", "gpio55", + "gpio56", "gpio57", "gpio58", "gpio59", "gpio60", "gpio61", "gpio62", + "gpio63", "gpio64", "gpio65", "gpio66", "gpio67", "gpio68", "gpio69", + "gpio70", "gpio71", "gpio72", "gpio73", "gpio74", "gpio75", "gpio76", + "gpio77", "gpio78", "gpio79", "gpio80", "gpio81", "gpio82", "gpio83", + "gpio84", "gpio85", "gpio86", "gpio87", "gpio88", "gpio89", "gpio90", + "gpio91", "gpio92", "gpio93", "gpio94", "gpio95", "gpio96", "gpio97", + "gpio98", "gpio99", "gpio100", "gpio101", "gpio102", "gpio103", + "gpio104", "gpio105", "gpio106", "gpio107", "gpio108", "gpio109", + "gpio110", "gpio111", "gpio112", "gpio113", "gpio114", "gpio115", + "gpio116", "gpio117", "gpio118", "gpio119", "gpio120", "gpio121", + "gpio122", "gpio123", "gpio124", "gpio125", "gpio126", "gpio127", + "gpio128", "gpio129", "gpio130", "gpio131", "gpio132", "gpio133", + "gpio134", "gpio135", "gpio136", "gpio137", "gpio138", "gpio139", + "gpio140", "gpio141", "gpio142", "gpio143", "gpio144", "gpio145", + "gpio146", "gpio147", "gpio148", "gpio149", "gpio150", "gpio151", + "gpio152", "gpio153", "gpio154", "gpio155", "gpio156", "gpio157", + "gpio158", "gpio159", "gpio160", "gpio161", "gpio162", "gpio163", + "gpio164", "gpio165", "gpio166", "gpio167", "gpio168", "gpio169", + "gpio170", "gpio171", "gpio172", "gpio173", "gpio174", "gpio175", + "gpio176", "gpio177", "gpio177", "gpio178", "gpio179", "gpio180", + "gpio181", "gpio182", "gpio183", "gpio184", "gpio185", "gpio186", + "gpio186", "gpio187", "gpio187", "gpio188", "gpio188", "gpio189", +}; + +static const char * const gps_groups[] = { + "gpio60", "gpio76", "gpio77", "gpio81", "gpio82", +}; + +static const char * const grfc_groups[] = { + "gpio64", "gpio65", "gpio66", "gpio67", "gpio68", "gpio71", "gpio72", + "gpio73", "gpio74", "gpio75", "gpio76", "gpio77", "gpio78", "gpio79", + "gpio80", "gpio81", "gpio82", +}; + +static const char * const hs1_mi2s_groups[] = { + "gpio155", "gpio156", "gpio157", "gpio158", "gpio159", +}; + +static const char * const hs2_mi2s_groups[] = { + "gpio160", "gpio161", "gpio162", "gpio163", "gpio164", +}; + +static const char * const hs3_mi2s_groups[] = { + "gpio125", "gpio165", "gpio166", "gpio167", "gpio168", +}; + +static const char * const jitter_bist_groups[] = { + "gpio129", +}; + +static const char * const lpass_slimbus_groups[] = { + "gpio149", "gpio150", "gpio151", "gpio152", +}; + +static const char * const m_voc_groups[] = { + "gpio10", +}; + +static const char * const mdp_vsync0_groups[] = { + "gpio89", +}; + +static const char * const mdp_vsync1_groups[] = { + "gpio89", +}; + +static const char * const mdp_vsync2_groups[] = { + "gpio89", +}; + +static const char * const mdp_vsync3_groups[] = { + "gpio89", +}; + +static const char * const mdp_vsync4_groups[] = { + "gpio89", +}; + +static const char * const mdp_vsync5_groups[] = { + "gpio89", +}; + +static const char * const mdp_vsync_groups[] = { + "gpio8", "gpio9", "gpio10", "gpio60", "gpio82", +}; + +static const char * const mss_lte_groups[] = { + "gpio69", "gpio70", +}; + +static const char * const nav_pps_groups[] = { + "gpio60", "gpio60", "gpio76", "gpio76", "gpio77", "gpio77", "gpio81", + "gpio81", "gpio82", "gpio82", +}; + +static const char * const pa_indicator_groups[] = { + "gpio68", +}; + +static const char * const pci_e0_groups[] = { + "gpio35", "gpio36", +}; + +static const char * const pci_e1_groups[] = { + "gpio102", "gpio103", +}; + +static const char * const pci_e2_groups[] = { + "gpio175", "gpio176", +}; + +static const char * const pci_e3_groups[] = { + "gpio178", "gpio179", +}; + +static const char * const phase_flag_groups[] = { + "gpio4", "gpio5", "gpio6", "gpio7", "gpio33", "gpio53", "gpio54", + "gpio102", "gpio120", "gpio121", "gpio122", "gpio123", "gpio125", + "gpio148", "gpio149", "gpio150", "gpio151", "gpio152", "gpio155", + "gpio156", "gpio157", "gpio158", "gpio159", "gpio160", "gpio161", + "gpio162", "gpio163", "gpio164", "gpio165", "gpio166", "gpio167", + "gpio168", +}; + +static const char * const pll_bist_groups[] = { + "gpio130", +}; + +static const char * const pll_bypassnl_groups[] = { + "gpio100", +}; + +static const char * const pll_reset_groups[] = { + "gpio101", +}; + +static const char * const pri_mi2s_groups[] = { + "gpio143", "gpio144", "gpio146", "gpio147", +}; + +static const char * const pri_mi2s_ws_groups[] = { + "gpio145", +}; + +static const char * const prng_rosc_groups[] = { + "gpio163", +}; + +static const char * const qdss_cti_groups[] = { + "gpio49", "gpio50", "gpio81", "gpio82", "gpio89", "gpio90", "gpio141", + "gpio142", +}; + +static const char * const qdss_gpio_groups[] = { + "gpio13", "gpio14", "gpio15", "gpio16", "gpio17", "gpio18", "gpio19", + "gpio20", "gpio21", "gpio22", "gpio23", "gpio24", "gpio25", "gpio26", + "gpio27", "gpio28", "gpio29", "gpio30", "gpio39", "gpio40", "gpio41", + "gpio42", "gpio92", "gpio114", "gpio115", "gpio116", "gpio117", + "gpio118", "gpio119", "gpio120", "gpio121", "gpio130", "gpio132", + "gpio133", "gpio134", "gpio135", +}; + +static const char * const qlink_groups[] = { + "gpio61", "gpio62", +}; + +static const char * const qspi0_groups[] = { + "gpio89", "gpio90", "gpio91", "gpio93", +}; + +static const char * const qspi0_clk_groups[] = { + "gpio92", +}; + +static const char * const qspi0_cs_groups[] = { + "gpio88", "gpio94", +}; + +static const char * const qspi1_groups[] = { + "gpio56", "gpio57", "gpio161", "gpio162", +}; + +static const char * const qspi1_clk_groups[] = { + "gpio163", +}; + +static const char * const qspi1_cs_groups[] = { + "gpio55", "gpio164", +}; + +static const char * const qua_mi2s_groups[] = { + "gpio136", "gpio137", "gpio138", "gpio139", "gpio140", "gpio141", + "gpio142", +}; + +static const char * const qup0_groups[] = { + "gpio0", "gpio1", "gpio2", "gpio3", +}; + +static const char * const qup10_groups[] = { + "gpio9", "gpio10", "gpio11", "gpio12", +}; + +static const char * const qup11_groups[] = { + "gpio92", "gpio93", "gpio94", "gpio95", +}; + +static const char * const qup12_groups[] = { + "gpio83", "gpio84", "gpio85", "gpio86", +}; + +static const char * const qup13_groups[] = { + "gpio43", "gpio44", "gpio45", "gpio46", +}; + +static const char * const qup14_groups[] = { + "gpio47", "gpio48", "gpio49", "gpio50", +}; + +static const char * const qup15_groups[] = { + "gpio27", "gpio28", "gpio29", "gpio30", +}; + +static const char * const qup16_groups[] = { + "gpio83", "gpio84", "gpio85", "gpio86", +}; + +static const char * const qup17_groups[] = { + "gpio55", "gpio56", "gpio57", "gpio58", +}; + +static const char * const qup18_groups[] = { + "gpio23", "gpio24", "gpio25", "gpio26", +}; + +static const char * const qup19_groups[] = { + "gpio181", "gpio182", "gpio183", "gpio184", +}; + +static const char * const qup1_groups[] = { + "gpio114", "gpio115", "gpio116", "gpio117", +}; + +static const char * const qup2_groups[] = { + "gpio126", "gpio127", "gpio128", "gpio129", +}; + +static const char * const qup3_groups[] = { + "gpio144", "gpio145", "gpio146", "gpio147", +}; + +static const char * const qup4_groups[] = { + "gpio51", "gpio52", "gpio53", "gpio54", +}; + +static const char * const qup5_groups[] = { + "gpio119", "gpio120", "gpio121", "gpio122", +}; + +static const char * const qup6_groups[] = { + "gpio4", "gpio5", "gpio6", "gpio7", +}; + +static const char * const qup7_groups[] = { + "gpio98", "gpio99", "gpio100", "gpio101", +}; + +static const char * const qup8_groups[] = { + "gpio88", "gpio89", "gpio90", "gpio91", +}; + +static const char * const qup9_groups[] = { + "gpio39", "gpio40", "gpio41", "gpio42", +}; + +static const char * const qup_l4_groups[] = { + "gpio35", "gpio59", "gpio60", "gpio95", +}; + +static const char * const qup_l5_groups[] = { + "gpio7", "gpio33", "gpio36", "gpio96", +}; + +static const char * const qup_l6_groups[] = { + "gpio6", "gpio34", "gpio37", "gpio97", +}; + +static const char * const rgmii_groups[] = { + "gpio4", "gpio5", "gpio6", "gpio7", "gpio59", "gpio114", "gpio115", + "gpio116", "gpio117", "gpio118", "gpio119", "gpio120", "gpio121", + "gpio122", +}; + +static const char * const sd_write_groups[] = { + "gpio97", +}; + +static const char * const sdc4_groups[] = { + "gpio91", "gpio93", "gpio94", "gpio95", +}; + +static const char * const sdc4_clk_groups[] = { + "gpio92", +}; + +static const char * const sdc4_cmd_groups[] = { + "gpio90", +}; + +static const char * const sec_mi2s_groups[] = { + "gpio126", "gpio127", "gpio128", "gpio129", "gpio130", +}; + +static const char * const sp_cmu_groups[] = { + "gpio162", +}; + +static const char * const spkr_i2s_groups[] = { + "gpio148", "gpio149", "gpio150", "gpio151", "gpio152", +}; + +static const char * const ter_mi2s_groups[] = { + "gpio131", "gpio132", "gpio133", "gpio134", "gpio135", +}; + +static const char * const tgu_groups[] = { + "gpio89", "gpio90", "gpio91", "gpio88", "gpio74", "gpio77", "gpio76", + "gpio75", +}; + +static const char * const tsense_pwm1_groups[] = { + "gpio150", +}; + +static const char * const tsense_pwm2_groups[] = { + "gpio150", +}; + +static const char * const tsif1_groups[] = { + "gpio88", "gpio89", "gpio90", "gpio91", "gpio97", +}; + +static const char * const tsif2_groups[] = { + "gpio92", "gpio93", "gpio94", "gpio95", "gpio96", +}; + +static const char * const uim1_groups[] = { + "gpio109", "gpio110", "gpio111", "gpio112", +}; + +static const char * const uim2_groups[] = { + "gpio105", "gpio106", "gpio107", "gpio108", +}; + +static const char * const uim_batt_groups[] = { + "gpio113", +}; + +static const char * const usb0_phy_groups[] = { + "gpio38", +}; + +static const char * const usb1_phy_groups[] = { + "gpio58", +}; + +static const char * const usb2phy_ac_groups[] = { + "gpio47", "gpio48", "gpio113", "gpio123", +}; + +static const char * const vfr_1_groups[] = { + "gpio91", +}; + +static const char * const vsense_trigger_groups[] = { + "gpio62", +}; + +static const char * const wlan1_adc_groups[] = { + "gpio64", "gpio63", +}; + +static const char * const wlan2_adc_groups[] = { + "gpio68", "gpio65", +}; + +static const char * const wmss_reset_groups[] = { + "gpio63", +}; + +static const struct pinfunction sc8180x_functions[] = { + MSM_PIN_FUNCTION(adsp_ext), + MSM_PIN_FUNCTION(agera_pll), + MSM_PIN_FUNCTION(aoss_cti), + MSM_PIN_FUNCTION(atest_char), + MSM_PIN_FUNCTION(atest_tsens), + MSM_PIN_FUNCTION(atest_tsens2), + MSM_PIN_FUNCTION(atest_usb0), + MSM_PIN_FUNCTION(atest_usb1), + MSM_PIN_FUNCTION(atest_usb2), + MSM_PIN_FUNCTION(atest_usb3), + MSM_PIN_FUNCTION(atest_usb4), + MSM_PIN_FUNCTION(audio_ref), + MSM_PIN_FUNCTION(btfm_slimbus), + MSM_PIN_FUNCTION(cam_mclk), + MSM_PIN_FUNCTION(cci_async), + MSM_PIN_FUNCTION(cci_i2c), + MSM_PIN_FUNCTION(cci_timer0), + MSM_PIN_FUNCTION(cci_timer1), + MSM_PIN_FUNCTION(cci_timer2), + MSM_PIN_FUNCTION(cci_timer3), + MSM_PIN_FUNCTION(cci_timer4), + MSM_PIN_FUNCTION(cci_timer5), + MSM_PIN_FUNCTION(cci_timer6), + MSM_PIN_FUNCTION(cci_timer7), + MSM_PIN_FUNCTION(cci_timer8), + MSM_PIN_FUNCTION(cci_timer9), + MSM_PIN_FUNCTION(cri_trng), + MSM_PIN_FUNCTION(dbg_out), + MSM_PIN_FUNCTION(ddr_bist), + MSM_PIN_FUNCTION(ddr_pxi), + MSM_PIN_FUNCTION(debug_hot), + MSM_PIN_FUNCTION(dp_hot), + MSM_PIN_FUNCTION(edp_hot), + MSM_PIN_FUNCTION(edp_lcd), + MSM_PIN_FUNCTION(emac_phy), + MSM_PIN_FUNCTION(emac_pps), + MSM_PIN_FUNCTION(gcc_gp1), + MSM_PIN_FUNCTION(gcc_gp2), + MSM_PIN_FUNCTION(gcc_gp3), + MSM_PIN_FUNCTION(gcc_gp4), + MSM_PIN_FUNCTION(gcc_gp5), + MSM_PIN_FUNCTION(gpio), + MSM_PIN_FUNCTION(gps), + MSM_PIN_FUNCTION(grfc), + MSM_PIN_FUNCTION(hs1_mi2s), + MSM_PIN_FUNCTION(hs2_mi2s), + MSM_PIN_FUNCTION(hs3_mi2s), + MSM_PIN_FUNCTION(jitter_bist), + MSM_PIN_FUNCTION(lpass_slimbus), + MSM_PIN_FUNCTION(m_voc), + MSM_PIN_FUNCTION(mdp_vsync), + MSM_PIN_FUNCTION(mdp_vsync0), + MSM_PIN_FUNCTION(mdp_vsync1), + MSM_PIN_FUNCTION(mdp_vsync2), + MSM_PIN_FUNCTION(mdp_vsync3), + MSM_PIN_FUNCTION(mdp_vsync4), + MSM_PIN_FUNCTION(mdp_vsync5), + MSM_PIN_FUNCTION(mss_lte), + MSM_PIN_FUNCTION(nav_pps), + MSM_PIN_FUNCTION(pa_indicator), + MSM_PIN_FUNCTION(pci_e0), + MSM_PIN_FUNCTION(pci_e1), + MSM_PIN_FUNCTION(pci_e2), + MSM_PIN_FUNCTION(pci_e3), + MSM_PIN_FUNCTION(phase_flag), + MSM_PIN_FUNCTION(pll_bist), + MSM_PIN_FUNCTION(pll_bypassnl), + MSM_PIN_FUNCTION(pll_reset), + MSM_PIN_FUNCTION(pri_mi2s), + MSM_PIN_FUNCTION(pri_mi2s_ws), + MSM_PIN_FUNCTION(prng_rosc), + MSM_PIN_FUNCTION(qdss_cti), + MSM_PIN_FUNCTION(qdss_gpio), + MSM_PIN_FUNCTION(qlink), + MSM_PIN_FUNCTION(qspi0), + MSM_PIN_FUNCTION(qspi0_clk), + MSM_PIN_FUNCTION(qspi0_cs), + MSM_PIN_FUNCTION(qspi1), + MSM_PIN_FUNCTION(qspi1_clk), + MSM_PIN_FUNCTION(qspi1_cs), + MSM_PIN_FUNCTION(qua_mi2s), + MSM_PIN_FUNCTION(qup0), + MSM_PIN_FUNCTION(qup1), + MSM_PIN_FUNCTION(qup2), + MSM_PIN_FUNCTION(qup3), + MSM_PIN_FUNCTION(qup4), + MSM_PIN_FUNCTION(qup5), + MSM_PIN_FUNCTION(qup6), + MSM_PIN_FUNCTION(qup7), + MSM_PIN_FUNCTION(qup8), + MSM_PIN_FUNCTION(qup9), + MSM_PIN_FUNCTION(qup10), + MSM_PIN_FUNCTION(qup11), + MSM_PIN_FUNCTION(qup12), + MSM_PIN_FUNCTION(qup13), + MSM_PIN_FUNCTION(qup14), + MSM_PIN_FUNCTION(qup15), + MSM_PIN_FUNCTION(qup16), + MSM_PIN_FUNCTION(qup17), + MSM_PIN_FUNCTION(qup18), + MSM_PIN_FUNCTION(qup19), + MSM_PIN_FUNCTION(qup_l4), + MSM_PIN_FUNCTION(qup_l5), + MSM_PIN_FUNCTION(qup_l6), + MSM_PIN_FUNCTION(rgmii), + MSM_PIN_FUNCTION(sd_write), + MSM_PIN_FUNCTION(sdc4), + MSM_PIN_FUNCTION(sdc4_clk), + MSM_PIN_FUNCTION(sdc4_cmd), + MSM_PIN_FUNCTION(sec_mi2s), + MSM_PIN_FUNCTION(sp_cmu), + MSM_PIN_FUNCTION(spkr_i2s), + MSM_PIN_FUNCTION(ter_mi2s), + MSM_PIN_FUNCTION(tgu), + MSM_PIN_FUNCTION(tsense_pwm1), + MSM_PIN_FUNCTION(tsense_pwm2), + MSM_PIN_FUNCTION(tsif1), + MSM_PIN_FUNCTION(tsif2), + MSM_PIN_FUNCTION(uim1), + MSM_PIN_FUNCTION(uim2), + MSM_PIN_FUNCTION(uim_batt), + MSM_PIN_FUNCTION(usb0_phy), + MSM_PIN_FUNCTION(usb1_phy), + MSM_PIN_FUNCTION(usb2phy_ac), + MSM_PIN_FUNCTION(vfr_1), + MSM_PIN_FUNCTION(vsense_trigger), + MSM_PIN_FUNCTION(wlan1_adc), + MSM_PIN_FUNCTION(wlan2_adc), + MSM_PIN_FUNCTION(wmss_reset), +}; + +/* Every pin is maintained as a single group, and missing or non-existing pin + * would be maintained as dummy group to synchronize pin group index with + * pin descriptor registered with pinctrl core. + * Clients would not be able to request these dummy pin groups. + */ +static const struct msm_pingroup sc8180x_groups[] = { + [0] = PINGROUP(0, WEST, qup0, cci_i2c, _, _, _, _, _, _, _), + [1] = PINGROUP(1, WEST, qup0, cci_i2c, _, _, _, _, _, _, _), + [2] = PINGROUP(2, WEST, qup0, cci_i2c, _, _, _, _, _, _, _), + [3] = PINGROUP(3, WEST, qup0, cci_i2c, _, _, _, _, _, _, _), + [4] = PINGROUP(4, WEST, qup6, rgmii, _, phase_flag, _, _, _, _, _), + [5] = PINGROUP(5, WEST, qup6, rgmii, _, phase_flag, _, _, _, _, _), + [6] = PINGROUP(6, WEST, qup6, rgmii, qup_l6, _, phase_flag, _, _, _, _), + [7] = PINGROUP(7, WEST, qup6, debug_hot, rgmii, qup_l5, _, phase_flag, _, _, _), + [8] = PINGROUP(8, EAST, mdp_vsync, _, _, _, _, _, _, _, _), + [9] = PINGROUP(9, EAST, mdp_vsync, qup10, _, _, _, _, _, _, _), + [10] = PINGROUP(10, EAST, edp_hot, m_voc, mdp_vsync, qup10, _, _, _, _, _), + [11] = PINGROUP(11, EAST, edp_lcd, qup10, _, _, _, _, _, _, _), + [12] = PINGROUP(12, EAST, qup10, _, _, _, _, _, _, _, _), + [13] = PINGROUP(13, EAST, cam_mclk, qdss_gpio, _, _, _, _, _, _, _), + [14] = PINGROUP(14, EAST, cam_mclk, qdss_gpio, _, _, _, _, _, _, _), + [15] = PINGROUP(15, EAST, cam_mclk, qdss_gpio, _, _, _, _, _, _, _), + [16] = PINGROUP(16, EAST, cam_mclk, qdss_gpio, _, _, _, _, _, _, _), + [17] = PINGROUP(17, EAST, cci_i2c, qdss_gpio, _, _, _, _, _, _, _), + [18] = PINGROUP(18, EAST, cci_i2c, qdss_gpio, _, _, _, _, _, _, _), + [19] = PINGROUP(19, EAST, cci_i2c, qdss_gpio, _, _, _, _, _, _, _), + [20] = PINGROUP(20, EAST, cci_i2c, qdss_gpio, _, _, _, _, _, _, _), + [21] = PINGROUP(21, EAST, cci_timer0, gcc_gp2, qdss_gpio, _, _, _, _, _, _), + [22] = PINGROUP(22, EAST, cci_timer1, gcc_gp3, qdss_gpio, _, _, _, _, _, _), + [23] = PINGROUP(23, EAST, cci_timer2, qup18, qdss_gpio, _, _, _, _, _, _), + [24] = PINGROUP(24, EAST, cci_timer3, cci_async, qup18, qdss_gpio, _, _, _, _, _), + [25] = PINGROUP(25, EAST, cam_mclk, cci_async, qup18, qdss_gpio, _, _, _, _, _), + [26] = PINGROUP(26, EAST, cci_async, qup18, qdss_gpio, _, _, _, _, _, _), + [27] = PINGROUP(27, EAST, qup15, _, qdss_gpio, _, _, _, _, _, _), + [28] = PINGROUP(28, EAST, qup15, qdss_gpio, _, _, _, _, _, _, _), + [29] = PINGROUP(29, EAST, qup15, qdss_gpio, _, _, _, _, _, _, _), + [30] = PINGROUP(30, EAST, qup15, qdss_gpio, _, _, _, _, _, _, _), + [31] = PINGROUP(31, EAST, cci_i2c, _, _, _, _, _, _, _, _), + [32] = PINGROUP(32, EAST, cci_i2c, _, _, _, _, _, _, _, _), + [33] = PINGROUP(33, EAST, cci_i2c, qup_l5, _, phase_flag, _, _, _, _, _), + [34] = PINGROUP(34, EAST, cci_i2c, qup_l6, dbg_out, atest_usb2, _, _, _, _, _), + [35] = PINGROUP(35, SOUTH, pci_e0, qup_l4, _, _, _, _, _, _, _), + [36] = PINGROUP(36, SOUTH, pci_e0, qup_l5, _, _, _, _, _, _, _), + [37] = PINGROUP(37, SOUTH, qup_l6, agera_pll, _, _, _, _, _, _, _), + [38] = PINGROUP(38, SOUTH, usb0_phy, _, _, _, _, _, _, _, _), + [39] = PINGROUP(39, EAST, qup9, cci_i2c, qdss_gpio, _, _, _, _, _, _), + [40] = PINGROUP(40, EAST, qup9, cci_i2c, qdss_gpio, _, _, _, _, _, _), + [41] = PINGROUP(41, EAST, qup9, cci_i2c, qdss_gpio, _, _, _, _, _, _), + [42] = PINGROUP(42, EAST, qup9, cci_i2c, qdss_gpio, _, _, _, _, _, _), + [43] = PINGROUP(43, EAST, qup13, _, _, _, _, _, _, _, _), + [44] = PINGROUP(44, EAST, qup13, _, _, _, _, _, _, _, _), + [45] = PINGROUP(45, EAST, qup13, _, _, _, _, _, _, _, _), + [46] = PINGROUP(46, EAST, qup13, _, _, _, _, _, _, _, _), + [47] = PINGROUP(47, EAST, qup14, usb2phy_ac, _, _, _, _, _, _, _), + [48] = PINGROUP(48, EAST, qup14, usb2phy_ac, _, _, _, _, _, _, _), + [49] = PINGROUP(49, EAST, qup14, qdss_cti, _, _, _, _, _, _, _), + [50] = PINGROUP(50, EAST, qup14, qdss_cti, _, _, _, _, _, _, _), + [51] = PINGROUP(51, WEST, qup4, _, _, _, _, _, _, _, _), + [52] = PINGROUP(52, WEST, qup4, _, _, _, _, _, _, _, _), + [53] = PINGROUP(53, WEST, qup4, _, phase_flag, _, _, _, _, _, _), + [54] = PINGROUP(54, WEST, qup4, _, _, phase_flag, _, _, _, _, _), + [55] = PINGROUP(55, WEST, qup17, qspi1_cs, _, _, _, _, _, _, _), + [56] = PINGROUP(56, WEST, qup17, qspi1, _, _, _, _, _, _, _), + [57] = PINGROUP(57, WEST, qup17, qspi1, _, _, _, _, _, _, _), + [58] = PINGROUP(58, WEST, usb1_phy, qup17, _, _, _, _, _, _, _), + [59] = PINGROUP(59, WEST, rgmii, qup_l4, _, _, _, _, _, _, _), + [60] = PINGROUP(60, EAST, gps, nav_pps, nav_pps, qup_l4, mdp_vsync, atest_usb1, ddr_pxi, _, _), + [61] = PINGROUP(61, EAST, qlink, _, _, _, _, _, _, _, _), + [62] = PINGROUP(62, EAST, qlink, atest_tsens2, atest_usb1, ddr_pxi, vsense_trigger, _, _, _, _), + [63] = PINGROUP(63, EAST, wmss_reset, _, atest_usb1, ddr_pxi, wlan1_adc, _, _, _, _), + [64] = PINGROUP(64, EAST, grfc, _, atest_usb1, ddr_pxi, wlan1_adc, _, _, _, _), + [65] = PINGROUP(65, EAST, grfc, atest_usb1, ddr_pxi, wlan2_adc, _, _, _, _, _), + [66] = PINGROUP(66, EAST, grfc, _, _, _, _, _, _, _, _), + [67] = PINGROUP(67, EAST, grfc, _, _, _, _, _, _, _, _), + [68] = PINGROUP(68, EAST, grfc, pa_indicator, atest_usb3, ddr_pxi, wlan2_adc, _, _, _, _), + [69] = PINGROUP(69, EAST, mss_lte, _, _, _, _, _, _, _, _), + [70] = PINGROUP(70, EAST, mss_lte, _, _, _, _, _, _, _, _), + [71] = PINGROUP(71, EAST, _, grfc, atest_usb3, ddr_pxi, _, _, _, _, _), + [72] = PINGROUP(72, EAST, _, grfc, atest_usb3, ddr_pxi, _, _, _, _, _), + [73] = PINGROUP(73, EAST, _, grfc, atest_usb3, ddr_pxi, _, _, _, _, _), + [74] = PINGROUP(74, EAST, _, grfc, tgu, atest_usb3, ddr_pxi, _, _, _, _), + [75] = PINGROUP(75, EAST, _, grfc, tgu, atest_usb4, ddr_pxi, _, _, _, _), + [76] = PINGROUP(76, EAST, _, grfc, gps, nav_pps, nav_pps, tgu, atest_usb4, ddr_pxi, _), + [77] = PINGROUP(77, EAST, _, grfc, gps, nav_pps, nav_pps, tgu, atest_usb4, ddr_pxi, _), + [78] = PINGROUP(78, EAST, _, grfc, _, atest_usb4, ddr_pxi, _, _, _, _), + [79] = PINGROUP(79, EAST, _, grfc, _, _, _, _, _, _, _), + [80] = PINGROUP(80, EAST, _, grfc, _, _, _, _, _, _, _), + [81] = PINGROUP(81, EAST, _, grfc, gps, nav_pps, nav_pps, qdss_cti, _, emac_pps, _), + [82] = PINGROUP(82, EAST, _, grfc, gps, nav_pps, nav_pps, mdp_vsync, qdss_cti, _, _), + [83] = PINGROUP(83, EAST, qup12, qup16, _, _, _, _, _, _, _), + [84] = PINGROUP(84, EAST, qup12, qup16, _, _, _, _, _, _, _), + [85] = PINGROUP(85, EAST, qup12, qup16, _, _, _, _, _, _, _), + [86] = PINGROUP(86, EAST, qup12, qup16, _, _, _, _, _, _, _), + [87] = PINGROUP(87, SOUTH, _, _, _, _, _, _, _, _, _), + [88] = PINGROUP(88, EAST, tsif1, qup8, qspi0_cs, tgu, atest_usb4, ddr_pxi, _, _, _), + [89] = PINGROUP(89, EAST, tsif1, qup8, qspi0, mdp_vsync0, mdp_vsync1, mdp_vsync2, mdp_vsync3, mdp_vsync4, mdp_vsync5), + [90] = PINGROUP(90, EAST, tsif1, qup8, qspi0, sdc4_cmd, tgu, qdss_cti, atest_usb0, ddr_pxi, _), + [91] = PINGROUP(91, EAST, tsif1, qup8, qspi0, sdc4, vfr_1, tgu, atest_usb0, _, _), + [92] = PINGROUP(92, EAST, tsif2, qup11, qspi0_clk, sdc4_clk, qdss_gpio, atest_usb0, _, _, _), + [93] = PINGROUP(93, EAST, tsif2, qup11, qspi0, sdc4, atest_tsens, atest_usb0, _, _, _), + [94] = PINGROUP(94, EAST, tsif2, qup11, qspi0_cs, sdc4, _, atest_usb0, _, _, _), + [95] = PINGROUP(95, EAST, tsif2, qup11, sdc4, qup_l4, atest_usb2, _, _, _, _), + [96] = PINGROUP(96, WEST, tsif2, qup_l5, _, _, _, _, _, _, _), + [97] = PINGROUP(97, WEST, sd_write, tsif1, qup_l6, _, _, _, _, _, _), + [98] = PINGROUP(98, WEST, qup7, ddr_bist, _, _, _, _, _, _, _), + [99] = PINGROUP(99, WEST, qup7, ddr_bist, _, _, _, _, _, _, _), + [100] = PINGROUP(100, WEST, qup7, pll_bypassnl, _, _, _, _, _, _, _), + [101] = PINGROUP(101, WEST, qup7, pll_reset, _, _, _, _, _, _, _), + [102] = PINGROUP(102, SOUTH, pci_e1, _, phase_flag, atest_usb2, _, _, _, _, _), + [103] = PINGROUP(103, SOUTH, pci_e1, _, _, _, _, _, _, _, _), + [104] = PINGROUP(104, SOUTH, _, _, _, _, _, _, _, _, _), + [105] = PINGROUP(105, WEST, uim2, _, _, _, _, _, _, _, _), + [106] = PINGROUP(106, WEST, uim2, _, _, _, _, _, _, _, _), + [107] = PINGROUP(107, WEST, uim2, _, _, _, _, _, _, _, _), + [108] = PINGROUP(108, WEST, uim2, _, _, _, _, _, _, _, _), + [109] = PINGROUP(109, WEST, uim1, _, _, _, _, _, _, _, _), + [110] = PINGROUP(110, WEST, uim1, _, _, _, _, _, _, _, _), + [111] = PINGROUP(111, WEST, uim1, _, _, _, _, _, _, _, _), + [112] = PINGROUP(112, WEST, uim1, _, _, _, _, _, _, _, _), + [113] = PINGROUP(113, WEST, uim_batt, usb2phy_ac, aoss_cti, _, _, _, _, _, _), + [114] = PINGROUP(114, WEST, qup1, rgmii, _, qdss_gpio, _, _, _, _, _), + [115] = PINGROUP(115, WEST, qup1, rgmii, adsp_ext, _, qdss_gpio, _, _, _, _), + [116] = PINGROUP(116, WEST, qup1, rgmii, _, qdss_gpio, _, _, _, _, _), + [117] = PINGROUP(117, WEST, qup1, rgmii, _, qdss_gpio, _, _, _, _, _), + [118] = PINGROUP(118, WEST, rgmii, _, qdss_gpio, _, _, _, _, _, _), + [119] = PINGROUP(119, WEST, qup5, rgmii, _, qdss_gpio, _, _, _, _, _), + [120] = PINGROUP(120, WEST, qup5, rgmii, _, phase_flag, qdss_gpio, _, _, _, _), + [121] = PINGROUP(121, WEST, qup5, rgmii, _, phase_flag, qdss_gpio, atest_usb2, _, _, _), + [122] = PINGROUP(122, WEST, qup5, rgmii, _, phase_flag, atest_usb2, _, _, _, _), + [123] = PINGROUP(123, SOUTH, usb2phy_ac, _, phase_flag, _, _, _, _, _, _), + [124] = PINGROUP(124, SOUTH, emac_phy, _, _, _, _, _, _, _, _), + [125] = PINGROUP(125, WEST, hs3_mi2s, _, phase_flag, _, _, _, _, _, _), + [126] = PINGROUP(126, WEST, sec_mi2s, qup2, _, _, _, _, _, _, _), + [127] = PINGROUP(127, WEST, sec_mi2s, qup2, _, _, _, _, _, _, _), + [128] = PINGROUP(128, WEST, sec_mi2s, qup2, _, _, _, _, _, _, _), + [129] = PINGROUP(129, WEST, sec_mi2s, qup2, jitter_bist, _, _, _, _, _, _), + [130] = PINGROUP(130, WEST, sec_mi2s, pll_bist, _, qdss_gpio, _, _, _, _, _), + [131] = PINGROUP(131, WEST, ter_mi2s, gcc_gp1, _, _, _, _, _, _, _), + [132] = PINGROUP(132, WEST, ter_mi2s, _, qdss_gpio, _, _, _, _, _, _), + [133] = PINGROUP(133, WEST, ter_mi2s, _, qdss_gpio, atest_char, _, _, _, _, _), + [134] = PINGROUP(134, WEST, ter_mi2s, _, qdss_gpio, atest_char, _, _, _, _, _), + [135] = PINGROUP(135, WEST, ter_mi2s, _, qdss_gpio, atest_char, _, _, _, _, _), + [136] = PINGROUP(136, WEST, qua_mi2s, gcc_gp1, _, _, _, _, _, _, _), + [137] = PINGROUP(137, WEST, qua_mi2s, gcc_gp2, _, _, _, _, _, _, _), + [138] = PINGROUP(138, WEST, qua_mi2s, gcc_gp3, _, _, _, _, _, _, _), + [139] = PINGROUP(139, WEST, qua_mi2s, gcc_gp4, _, _, _, _, _, _, _), + [140] = PINGROUP(140, WEST, qua_mi2s, gcc_gp5, _, atest_char, _, _, _, _, _), + [141] = PINGROUP(141, WEST, qua_mi2s, qdss_cti, _, _, _, _, _, _, _), + [142] = PINGROUP(142, WEST, qua_mi2s, _, _, qdss_cti, atest_char, _, _, _, _), + [143] = PINGROUP(143, WEST, pri_mi2s, _, _, _, _, _, _, _, _), + [144] = PINGROUP(144, WEST, pri_mi2s, qup3, _, _, _, _, _, _, _), + [145] = PINGROUP(145, WEST, pri_mi2s_ws, qup3, ddr_bist, _, _, _, _, _, _), + [146] = PINGROUP(146, WEST, pri_mi2s, qup3, ddr_bist, _, _, _, _, _, _), + [147] = PINGROUP(147, WEST, pri_mi2s, qup3, _, _, _, _, _, _, _), + [148] = PINGROUP(148, WEST, spkr_i2s, audio_ref, _, phase_flag, _, _, _, _, _), + [149] = PINGROUP(149, WEST, lpass_slimbus, spkr_i2s, _, phase_flag, _, _, _, _, _), + [150] = PINGROUP(150, WEST, lpass_slimbus, spkr_i2s, _, phase_flag, tsense_pwm1, tsense_pwm2, _, _, _), + [151] = PINGROUP(151, WEST, lpass_slimbus, spkr_i2s, _, phase_flag, _, _, _, _, _), + [152] = PINGROUP(152, WEST, lpass_slimbus, spkr_i2s, _, phase_flag, _, _, _, _, _), + [153] = PINGROUP(153, WEST, btfm_slimbus, _, _, _, _, _, _, _, _), + [154] = PINGROUP(154, WEST, btfm_slimbus, _, _, _, _, _, _, _, _), + [155] = PINGROUP(155, WEST, hs1_mi2s, _, phase_flag, _, _, _, _, _, _), + [156] = PINGROUP(156, WEST, hs1_mi2s, _, phase_flag, _, _, _, _, _, _), + [157] = PINGROUP(157, WEST, hs1_mi2s, _, phase_flag, _, _, _, _, _, _), + [158] = PINGROUP(158, WEST, hs1_mi2s, _, phase_flag, _, _, _, _, _, _), + [159] = PINGROUP(159, WEST, hs1_mi2s, cri_trng, _, phase_flag, _, _, _, _, _), + [160] = PINGROUP(160, WEST, hs2_mi2s, cri_trng, _, phase_flag, _, _, _, _, _), + [161] = PINGROUP(161, WEST, hs2_mi2s, qspi1, cri_trng, _, phase_flag, _, _, _, _), + [162] = PINGROUP(162, WEST, hs2_mi2s, qspi1, sp_cmu, _, phase_flag, _, _, _, _), + [163] = PINGROUP(163, WEST, hs2_mi2s, qspi1_clk, prng_rosc, _, phase_flag, _, _, _, _), + [164] = PINGROUP(164, WEST, hs2_mi2s, qspi1_cs, _, phase_flag, _, _, _, _, _), + [165] = PINGROUP(165, WEST, hs3_mi2s, _, phase_flag, _, _, _, _, _, _), + [166] = PINGROUP(166, WEST, hs3_mi2s, _, phase_flag, _, _, _, _, _, _), + [167] = PINGROUP(167, WEST, hs3_mi2s, _, phase_flag, _, _, _, _, _, _), + [168] = PINGROUP(168, WEST, hs3_mi2s, _, phase_flag, _, _, _, _, _, _), + [169] = PINGROUP(169, SOUTH, _, _, _, _, _, _, _, _, _), + [170] = PINGROUP(170, SOUTH, _, _, _, _, _, _, _, _, _), + [171] = PINGROUP(171, SOUTH, _, _, _, _, _, _, _, _, _), + [172] = PINGROUP(172, SOUTH, _, _, _, _, _, _, _, _, _), + [173] = PINGROUP(173, SOUTH, _, _, _, _, _, _, _, _, _), + [174] = PINGROUP(174, SOUTH, _, _, _, _, _, _, _, _, _), + [175] = PINGROUP(175, SOUTH, pci_e2, _, _, _, _, _, _, _, _), + [176] = PINGROUP(176, SOUTH, pci_e2, cci_async, _, _, _, _, _, _, _), + [177] = PINGROUP_OFFSET(177, SOUTH, 0x1e000, _, _, _, _, _, _, _, _, _), + [178] = PINGROUP_OFFSET(178, SOUTH, 0x1e000, pci_e3, cci_timer4, _, _, _, _, _, _, _), + [179] = PINGROUP_OFFSET(179, SOUTH, 0x1e000, pci_e3, cam_mclk, _, _, _, _, _, _, _), + [180] = PINGROUP_OFFSET(180, SOUTH, 0x1e000, cam_mclk, _, _, _, _, _, _, _, _), + [181] = PINGROUP_OFFSET(181, SOUTH, 0x1e000, qup19, cam_mclk, _, _, _, _, _, _, _), + [182] = PINGROUP_OFFSET(182, SOUTH, 0x1e000, qup19, cci_timer5, gcc_gp4, _, _, _, _, _, _), + [183] = PINGROUP_OFFSET(183, SOUTH, 0x1e000, qup19, cci_timer6, gcc_gp5, _, _, _, _, _, _), + [184] = PINGROUP_OFFSET(184, SOUTH, 0x1e000, qup19, cci_timer7, _, _, _, _, _, _, _), + [185] = PINGROUP_OFFSET(185, SOUTH, 0x1e000, cci_timer8, cci_async, _, _, _, _, _, _, _), + [186] = PINGROUP_OFFSET(186, SOUTH, 0x1e000, cci_timer9, cci_async, _, _, _, _, _, _, _), + [187] = PINGROUP_OFFSET(187, SOUTH, 0x1e000, _, _, _, _, _, _, _, _, _), + [188] = PINGROUP_OFFSET(188, SOUTH, 0x1e000, _, _, _, _, _, _, _, _, _), + [189] = PINGROUP_OFFSET(189, SOUTH, 0x1e000, dp_hot, _, _, _, _, _, _, _, _), + [190] = UFS_RESET(ufs_reset), + [191] = SDC_QDSD_PINGROUP(sdc2_clk, 0x4b2000, 14, 6), + [192] = SDC_QDSD_PINGROUP(sdc2_cmd, 0x4b2000, 11, 3), + [193] = SDC_QDSD_PINGROUP(sdc2_data, 0x4b2000, 9, 0), +}; + +static const int sc8180x_acpi_reserved_gpios[] = { + 0, 1, 2, 3, + 47, 48, 49, 50, + 126, 127, 128, 129, + -1 /* terminator */ +}; + +static const struct msm_gpio_wakeirq_map sc8180x_pdc_map[] = { + { 3, 31 }, { 5, 32 }, { 8, 33 }, { 9, 34 }, { 10, 100 }, { 12, 104 }, + { 24, 37 }, { 26, 38 }, { 27, 41 }, { 28, 42 }, { 30, 39 }, { 36, 43 }, + { 37, 44 }, { 38, 45 }, { 39, 118 }, { 39, 125 }, { 41, 47 }, + { 42, 48 }, { 46, 50 }, { 47, 49 }, { 48, 51 }, { 49, 53 }, { 50, 52 }, + { 51, 116 }, { 51, 123 }, { 53, 54 }, { 54, 55 }, { 55, 56 }, + { 56, 57 }, { 58, 58 }, { 60, 60 }, { 68, 62 }, { 70, 63 }, { 76, 86 }, + { 77, 36 }, { 81, 64 }, { 83, 65 }, { 86, 67 }, { 87, 84 }, { 88, 117 }, + { 88, 124 }, { 90, 69 }, { 91, 70 }, { 93, 75 }, { 95, 72 }, { 97, 74 }, + { 101, 76 }, { 103, 77 }, { 104, 78 }, { 114, 82 }, { 117, 85 }, + { 118, 101 }, { 119, 87 }, { 120, 88 }, { 121, 89 }, { 122, 90 }, + { 123, 91 }, { 124, 92 }, { 125, 93 }, { 129, 94 }, { 132, 105 }, + { 133, 35 }, { 134, 36 }, { 136, 97 }, { 142, 103 }, { 144, 115 }, + { 144, 122 }, { 147, 106 }, { 150, 107 }, { 152, 108 }, { 153, 109 }, + { 177, 111 }, { 180, 112 }, { 184, 113 }, { 189, 114 } +}; + +static struct msm_pinctrl_soc_data sc8180x_pinctrl = { + .tiles = sc8180x_tiles, + .ntiles = ARRAY_SIZE(sc8180x_tiles), + .pins = sc8180x_pins, + .npins = ARRAY_SIZE(sc8180x_pins), + .functions = sc8180x_functions, + .nfunctions = ARRAY_SIZE(sc8180x_functions), + .groups = sc8180x_groups, + .ngroups = ARRAY_SIZE(sc8180x_groups), + .ngpios = 191, + .wakeirq_map = sc8180x_pdc_map, + .nwakeirq_map = ARRAY_SIZE(sc8180x_pdc_map), +}; + +static const struct msm_pinctrl_soc_data sc8180x_acpi_pinctrl = { + .tiles = sc8180x_tiles, + .ntiles = ARRAY_SIZE(sc8180x_tiles), + .pins = sc8180x_pins, + .npins = ARRAY_SIZE(sc8180x_pins), + .groups = sc8180x_groups, + .ngroups = ARRAY_SIZE(sc8180x_groups), + .reserved_gpios = sc8180x_acpi_reserved_gpios, + .ngpios = 190, +}; + +/* + * ACPI DSDT has one single memory resource for TLMM, which violates the + * hardware layout of 3 separate tiles. Let's split the memory resource into + * 3 named ones, so that msm_pinctrl_probe() can map memory for ACPI in the + * same way as for DT probe. + */ +static int sc8180x_pinctrl_add_tile_resources(struct platform_device *pdev) +{ + int nres_num = pdev->num_resources + ARRAY_SIZE(sc8180x_tiles) - 1; + struct resource *mres = NULL; + struct resource *nres, *res; + int i, ret; + + /* + * DT already has tiles defined properly, so nothing needs to be done + * for DT probe. + */ + if (pdev->dev.of_node) + return 0; + + /* Allocate for new resources */ + nres = devm_kzalloc(&pdev->dev, sizeof(*nres) * nres_num, GFP_KERNEL); + if (!nres) + return -ENOMEM; + + res = nres; + + for (i = 0; i < pdev->num_resources; i++) { + struct resource *r = &pdev->resource[i]; + + /* Save memory resource and copy others */ + if (resource_type(r) == IORESOURCE_MEM) + mres = r; + else + *res++ = *r; + } + + if (!mres) + return -EINVAL; + + /* Append tile memory resources */ + for (i = 0; i < ARRAY_SIZE(sc8180x_tiles); i++, res++) { + const struct tile_info *info = &sc8180x_tile_info[i]; + + res->start = mres->start + info->offset; + res->end = mres->start + info->offset + info->size - 1; + res->flags = mres->flags; + res->name = sc8180x_tiles[i]; + + /* Add new MEM to resource tree */ + insert_resource(mres->parent, res); + } + + /* Remove old MEM from resource tree */ + remove_resource(mres); + + /* Free old resources and install new ones */ + ret = platform_device_add_resources(pdev, nres, nres_num); + if (ret) { + dev_err(&pdev->dev, "failed to add new resources: %d\n", ret); + return ret; + } + + return 0; +} + +static int sc8180x_pinctrl_probe(struct platform_device *pdev) +{ + const struct msm_pinctrl_soc_data *soc_data; + int ret; + + soc_data = device_get_match_data(&pdev->dev); + if (!soc_data) + return -EINVAL; + + ret = sc8180x_pinctrl_add_tile_resources(pdev); + if (ret) + return ret; + + return msm_pinctrl_probe(pdev, soc_data); +} + +static const struct acpi_device_id sc8180x_pinctrl_acpi_match[] = { + { + .id = "QCOM040D", + .driver_data = (kernel_ulong_t) &sc8180x_acpi_pinctrl, + }, + { } +}; +MODULE_DEVICE_TABLE(acpi, sc8180x_pinctrl_acpi_match); + +static const struct of_device_id sc8180x_pinctrl_of_match[] = { + { + .compatible = "qcom,sc8180x-tlmm", + .data = &sc8180x_pinctrl, + }, + { }, +}; +MODULE_DEVICE_TABLE(of, sc8180x_pinctrl_of_match); + +static struct platform_driver sc8180x_pinctrl_driver = { + .driver = { + .name = "sc8180x-pinctrl", + .of_match_table = sc8180x_pinctrl_of_match, + .acpi_match_table = sc8180x_pinctrl_acpi_match, + }, + .probe = sc8180x_pinctrl_probe, + .remove = msm_pinctrl_remove, +}; + +static int __init sc8180x_pinctrl_init(void) +{ + return platform_driver_register(&sc8180x_pinctrl_driver); +} +arch_initcall(sc8180x_pinctrl_init); + +static void __exit sc8180x_pinctrl_exit(void) +{ + platform_driver_unregister(&sc8180x_pinctrl_driver); +} +module_exit(sc8180x_pinctrl_exit); + +MODULE_DESCRIPTION("QTI SC8180x pinctrl driver"); +MODULE_LICENSE("GPL v2"); diff --git a/drivers/pinctrl/qcom/pinctrl-sc8280xp-lpass-lpi.c b/drivers/pinctrl/qcom/pinctrl-sc8280xp-lpass-lpi.c new file mode 100644 index 0000000000..4b9c0beac3 --- /dev/null +++ b/drivers/pinctrl/qcom/pinctrl-sc8280xp-lpass-lpi.c @@ -0,0 +1,207 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2022 Linaro Ltd. + */ + +#include <linux/gpio/driver.h> +#include <linux/module.h> +#include <linux/platform_device.h> + +#include "pinctrl-lpass-lpi.h" + +enum lpass_lpi_functions { + LPI_MUX_dmic1_clk, + LPI_MUX_dmic1_data, + LPI_MUX_dmic2_clk, + LPI_MUX_dmic2_data, + LPI_MUX_dmic3_clk, + LPI_MUX_dmic3_data, + LPI_MUX_dmic4_clk, + LPI_MUX_dmic4_data, + LPI_MUX_i2s1_clk, + LPI_MUX_i2s1_data, + LPI_MUX_i2s1_ws, + LPI_MUX_i2s2_clk, + LPI_MUX_i2s2_data, + LPI_MUX_i2s2_ws, + LPI_MUX_i2s3_clk, + LPI_MUX_i2s3_data, + LPI_MUX_i2s3_ws, + LPI_MUX_qua_mi2s_data, + LPI_MUX_qua_mi2s_sclk, + LPI_MUX_qua_mi2s_ws, + LPI_MUX_swr_rx_clk, + LPI_MUX_swr_rx_data, + LPI_MUX_swr_tx_clk, + LPI_MUX_swr_tx_data, + LPI_MUX_wsa_swr_clk, + LPI_MUX_wsa_swr_data, + LPI_MUX_wsa2_swr_clk, + LPI_MUX_wsa2_swr_data, + LPI_MUX_ext_mclk1_a, + LPI_MUX_ext_mclk1_b, + LPI_MUX_ext_mclk1_c, + LPI_MUX_gpio, + LPI_MUX__, +}; + +static int gpio0_pins[] = { 0 }; +static int gpio1_pins[] = { 1 }; +static int gpio2_pins[] = { 2 }; +static int gpio3_pins[] = { 3 }; +static int gpio4_pins[] = { 4 }; +static int gpio5_pins[] = { 5 }; +static int gpio6_pins[] = { 6 }; +static int gpio7_pins[] = { 7 }; +static int gpio8_pins[] = { 8 }; +static int gpio9_pins[] = { 9 }; +static int gpio10_pins[] = { 10 }; +static int gpio11_pins[] = { 11 }; +static int gpio12_pins[] = { 12 }; +static int gpio13_pins[] = { 13 }; +static int gpio14_pins[] = { 14 }; +static int gpio15_pins[] = { 15 }; +static int gpio16_pins[] = { 16 }; +static int gpio17_pins[] = { 17 }; +static int gpio18_pins[] = { 18 }; + +static const struct pinctrl_pin_desc sc8280xp_lpi_pins[] = { + PINCTRL_PIN(0, "gpio0"), + PINCTRL_PIN(1, "gpio1"), + PINCTRL_PIN(2, "gpio2"), + PINCTRL_PIN(3, "gpio3"), + PINCTRL_PIN(4, "gpio4"), + PINCTRL_PIN(5, "gpio5"), + PINCTRL_PIN(6, "gpio6"), + PINCTRL_PIN(7, "gpio7"), + PINCTRL_PIN(8, "gpio8"), + PINCTRL_PIN(9, "gpio9"), + PINCTRL_PIN(10, "gpio10"), + PINCTRL_PIN(11, "gpio11"), + PINCTRL_PIN(12, "gpio12"), + PINCTRL_PIN(13, "gpio13"), + PINCTRL_PIN(14, "gpio14"), + PINCTRL_PIN(15, "gpio15"), + PINCTRL_PIN(16, "gpio16"), + PINCTRL_PIN(17, "gpio17"), + PINCTRL_PIN(18, "gpio18"), +}; + +static const char * const swr_tx_clk_groups[] = { "gpio0" }; +static const char * const swr_tx_data_groups[] = { "gpio1", "gpio2", "gpio14" }; +static const char * const swr_rx_clk_groups[] = { "gpio3" }; +static const char * const swr_rx_data_groups[] = { "gpio4", "gpio5" }; +static const char * const dmic1_clk_groups[] = { "gpio6" }; +static const char * const dmic1_data_groups[] = { "gpio7" }; +static const char * const dmic2_clk_groups[] = { "gpio8" }; +static const char * const dmic2_data_groups[] = { "gpio9" }; +static const char * const dmic4_clk_groups[] = { "gpio17" }; +static const char * const dmic4_data_groups[] = { "gpio18" }; +static const char * const i2s2_clk_groups[] = { "gpio10" }; +static const char * const i2s2_ws_groups[] = { "gpio11" }; +static const char * const dmic3_clk_groups[] = { "gpio12" }; +static const char * const dmic3_data_groups[] = { "gpio13" }; +static const char * const qua_mi2s_sclk_groups[] = { "gpio0" }; +static const char * const qua_mi2s_ws_groups[] = { "gpio1" }; +static const char * const qua_mi2s_data_groups[] = { "gpio2", "gpio3", "gpio4", "gpio5" }; +static const char * const i2s1_clk_groups[] = { "gpio6" }; +static const char * const i2s1_ws_groups[] = { "gpio7" }; +static const char * const i2s1_data_groups[] = { "gpio8", "gpio9" }; +static const char * const wsa_swr_clk_groups[] = { "gpio10" }; +static const char * const wsa_swr_data_groups[] = { "gpio11" }; +static const char * const wsa2_swr_clk_groups[] = { "gpio15" }; +static const char * const wsa2_swr_data_groups[] = { "gpio16" }; +static const char * const i2s2_data_groups[] = { "gpio15", "gpio16" }; +static const char * const i2s3_clk_groups[] = { "gpio12"}; +static const char * const i2s3_ws_groups[] = { "gpio13"}; +static const char * const i2s3_data_groups[] = { "gpio17", "gpio18"}; +static const char * const ext_mclk1_c_groups[] = { "gpio5" }; +static const char * const ext_mclk1_b_groups[] = { "gpio9" }; +static const char * const ext_mclk1_a_groups[] = { "gpio13" }; + +static const struct lpi_pingroup sc8280xp_groups[] = { + LPI_PINGROUP(0, 0, swr_tx_clk, qua_mi2s_sclk, _, _), + LPI_PINGROUP(1, 2, swr_tx_data, qua_mi2s_ws, _, _), + LPI_PINGROUP(2, 4, swr_tx_data, qua_mi2s_data, _, _), + LPI_PINGROUP(3, 8, swr_rx_clk, qua_mi2s_data, _, _), + LPI_PINGROUP(4, 10, swr_rx_data, qua_mi2s_data, _, _), + LPI_PINGROUP(5, 12, swr_rx_data, ext_mclk1_c, qua_mi2s_data, _), + LPI_PINGROUP(6, LPI_NO_SLEW, dmic1_clk, i2s1_clk, _, _), + LPI_PINGROUP(7, LPI_NO_SLEW, dmic1_data, i2s1_ws, _, _), + LPI_PINGROUP(8, LPI_NO_SLEW, dmic2_clk, i2s1_data, _, _), + LPI_PINGROUP(9, LPI_NO_SLEW, dmic2_data, i2s1_data, ext_mclk1_b, _), + LPI_PINGROUP(10, 16, i2s2_clk, wsa_swr_clk, _, _), + LPI_PINGROUP(11, 18, i2s2_ws, wsa_swr_data, _, _), + LPI_PINGROUP(12, LPI_NO_SLEW, dmic3_clk, i2s3_clk, _, _), + LPI_PINGROUP(13, LPI_NO_SLEW, dmic3_data, i2s3_ws, ext_mclk1_a, _), + LPI_PINGROUP(14, 6, swr_tx_data, _, _, _), + LPI_PINGROUP(15, 20, i2s2_data, wsa2_swr_clk, _, _), + LPI_PINGROUP(16, 22, i2s2_data, wsa2_swr_data, _, _), + LPI_PINGROUP(17, LPI_NO_SLEW, dmic4_clk, i2s3_data, _, _), + LPI_PINGROUP(18, LPI_NO_SLEW, dmic4_data, i2s3_data, _, _), +}; + +static const struct lpi_function sc8280xp_functions[] = { + LPI_FUNCTION(dmic1_clk), + LPI_FUNCTION(dmic1_data), + LPI_FUNCTION(dmic2_clk), + LPI_FUNCTION(dmic2_data), + LPI_FUNCTION(dmic3_clk), + LPI_FUNCTION(dmic3_data), + LPI_FUNCTION(dmic4_clk), + LPI_FUNCTION(dmic4_data), + LPI_FUNCTION(i2s1_clk), + LPI_FUNCTION(i2s1_data), + LPI_FUNCTION(i2s1_ws), + LPI_FUNCTION(i2s2_clk), + LPI_FUNCTION(i2s2_data), + LPI_FUNCTION(i2s2_ws), + LPI_FUNCTION(i2s3_clk), + LPI_FUNCTION(i2s3_data), + LPI_FUNCTION(i2s3_ws), + LPI_FUNCTION(qua_mi2s_data), + LPI_FUNCTION(qua_mi2s_sclk), + LPI_FUNCTION(qua_mi2s_ws), + LPI_FUNCTION(swr_rx_clk), + LPI_FUNCTION(swr_rx_data), + LPI_FUNCTION(swr_tx_clk), + LPI_FUNCTION(swr_tx_data), + LPI_FUNCTION(wsa_swr_clk), + LPI_FUNCTION(wsa_swr_data), + LPI_FUNCTION(wsa2_swr_clk), + LPI_FUNCTION(wsa2_swr_data), + LPI_FUNCTION(ext_mclk1_a), + LPI_FUNCTION(ext_mclk1_b), + LPI_FUNCTION(ext_mclk1_c), +}; + +static const struct lpi_pinctrl_variant_data sc8280xp_lpi_data = { + .pins = sc8280xp_lpi_pins, + .npins = ARRAY_SIZE(sc8280xp_lpi_pins), + .groups = sc8280xp_groups, + .ngroups = ARRAY_SIZE(sc8280xp_groups), + .functions = sc8280xp_functions, + .nfunctions = ARRAY_SIZE(sc8280xp_functions), +}; + +static const struct of_device_id lpi_pinctrl_of_match[] = { + { + .compatible = "qcom,sc8280xp-lpass-lpi-pinctrl", + .data = &sc8280xp_lpi_data, + }, + { } +}; +MODULE_DEVICE_TABLE(of, lpi_pinctrl_of_match); + +static struct platform_driver lpi_pinctrl_driver = { + .driver = { + .name = "qcom-sc8280xp-lpass-lpi-pinctrl", + .of_match_table = lpi_pinctrl_of_match, + }, + .probe = lpi_pinctrl_probe, + .remove = lpi_pinctrl_remove, +}; + +module_platform_driver(lpi_pinctrl_driver); +MODULE_DESCRIPTION("QTI SC8280XP LPI GPIO pin control driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/pinctrl/qcom/pinctrl-sc8280xp.c b/drivers/pinctrl/qcom/pinctrl-sc8280xp.c new file mode 100644 index 0000000000..96f4fb5a5d --- /dev/null +++ b/drivers/pinctrl/qcom/pinctrl-sc8280xp.c @@ -0,0 +1,1945 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved. + * Copyright (c) 2022, Linaro Ltd. + */ + +#include <linux/module.h> +#include <linux/of.h> +#include <linux/platform_device.h> + +#include "pinctrl-msm.h" + +#define REG_SIZE 0x1000 +#define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7) \ + { \ + .grp = PINCTRL_PINGROUP("gpio" #id, \ + gpio##id##_pins, \ + ARRAY_SIZE(gpio##id##_pins)), \ + .funcs = (int[]){ \ + msm_mux_gpio, /* gpio mode */ \ + msm_mux_##f1, \ + msm_mux_##f2, \ + msm_mux_##f3, \ + msm_mux_##f4, \ + msm_mux_##f5, \ + msm_mux_##f6, \ + msm_mux_##f7, \ + }, \ + .nfuncs = 8, \ + .ctl_reg = REG_SIZE * id, \ + .io_reg = 0x4 + REG_SIZE * id, \ + .intr_cfg_reg = 0x8 + REG_SIZE * id, \ + .intr_status_reg = 0xc + REG_SIZE * id, \ + .intr_target_reg = 0x8 + REG_SIZE * id, \ + .mux_bit = 2, \ + .pull_bit = 0, \ + .drv_bit = 6, \ + .oe_bit = 9, \ + .in_bit = 0, \ + .out_bit = 1, \ + .egpio_enable = 12, \ + .egpio_present = 11, \ + .intr_enable_bit = 0, \ + .intr_status_bit = 0, \ + .intr_target_bit = 5, \ + .intr_target_kpss_val = 3, \ + .intr_raw_status_bit = 4, \ + .intr_polarity_bit = 1, \ + .intr_detection_bit = 2, \ + .intr_detection_width = 2, \ + } + +#define SDC_QDSD_PINGROUP(pg_name, ctl, pull, drv) \ + { \ + .grp = PINCTRL_PINGROUP(#pg_name, \ + pg_name##_pins, \ + ARRAY_SIZE(pg_name##_pins)), \ + .ctl_reg = ctl, \ + .io_reg = 0, \ + .intr_cfg_reg = 0, \ + .intr_status_reg = 0, \ + .intr_target_reg = 0, \ + .mux_bit = -1, \ + .pull_bit = pull, \ + .drv_bit = drv, \ + .oe_bit = -1, \ + .in_bit = -1, \ + .out_bit = -1, \ + .intr_enable_bit = -1, \ + .intr_status_bit = -1, \ + .intr_target_bit = -1, \ + .intr_raw_status_bit = -1, \ + .intr_polarity_bit = -1, \ + .intr_detection_bit = -1, \ + .intr_detection_width = -1, \ + } + +#define UFS_RESET(pg_name, offset) \ + { \ + .grp = PINCTRL_PINGROUP(#pg_name, \ + pg_name##_pins, \ + ARRAY_SIZE(pg_name##_pins)), \ + .ctl_reg = offset, \ + .io_reg = offset + 0x4, \ + .intr_cfg_reg = 0, \ + .intr_status_reg = 0, \ + .intr_target_reg = 0, \ + .mux_bit = -1, \ + .pull_bit = 3, \ + .drv_bit = 0, \ + .oe_bit = -1, \ + .in_bit = -1, \ + .out_bit = 0, \ + .intr_enable_bit = -1, \ + .intr_status_bit = -1, \ + .intr_target_bit = -1, \ + .intr_raw_status_bit = -1, \ + .intr_polarity_bit = -1, \ + .intr_detection_bit = -1, \ + .intr_detection_width = -1, \ + } +static const struct pinctrl_pin_desc sc8280xp_pins[] = { + PINCTRL_PIN(0, "GPIO_0"), + PINCTRL_PIN(1, "GPIO_1"), + PINCTRL_PIN(2, "GPIO_2"), + PINCTRL_PIN(3, "GPIO_3"), + PINCTRL_PIN(4, "GPIO_4"), + PINCTRL_PIN(5, "GPIO_5"), + PINCTRL_PIN(6, "GPIO_6"), + PINCTRL_PIN(7, "GPIO_7"), + PINCTRL_PIN(8, "GPIO_8"), + PINCTRL_PIN(9, "GPIO_9"), + PINCTRL_PIN(10, "GPIO_10"), + PINCTRL_PIN(11, "GPIO_11"), + PINCTRL_PIN(12, "GPIO_12"), + PINCTRL_PIN(13, "GPIO_13"), + PINCTRL_PIN(14, "GPIO_14"), + PINCTRL_PIN(15, "GPIO_15"), + PINCTRL_PIN(16, "GPIO_16"), + PINCTRL_PIN(17, "GPIO_17"), + PINCTRL_PIN(18, "GPIO_18"), + PINCTRL_PIN(19, "GPIO_19"), + PINCTRL_PIN(20, "GPIO_20"), + PINCTRL_PIN(21, "GPIO_21"), + PINCTRL_PIN(22, "GPIO_22"), + PINCTRL_PIN(23, "GPIO_23"), + PINCTRL_PIN(24, "GPIO_24"), + PINCTRL_PIN(25, "GPIO_25"), + PINCTRL_PIN(26, "GPIO_26"), + PINCTRL_PIN(27, "GPIO_27"), + PINCTRL_PIN(28, "GPIO_28"), + PINCTRL_PIN(29, "GPIO_29"), + PINCTRL_PIN(30, "GPIO_30"), + PINCTRL_PIN(31, "GPIO_31"), + PINCTRL_PIN(32, "GPIO_32"), + PINCTRL_PIN(33, "GPIO_33"), + PINCTRL_PIN(34, "GPIO_34"), + PINCTRL_PIN(35, "GPIO_35"), + PINCTRL_PIN(36, "GPIO_36"), + PINCTRL_PIN(37, "GPIO_37"), + PINCTRL_PIN(38, "GPIO_38"), + PINCTRL_PIN(39, "GPIO_39"), + PINCTRL_PIN(40, "GPIO_40"), + PINCTRL_PIN(41, "GPIO_41"), + PINCTRL_PIN(42, "GPIO_42"), + PINCTRL_PIN(43, "GPIO_43"), + PINCTRL_PIN(44, "GPIO_44"), + PINCTRL_PIN(45, "GPIO_45"), + PINCTRL_PIN(46, "GPIO_46"), + PINCTRL_PIN(47, "GPIO_47"), + PINCTRL_PIN(48, "GPIO_48"), + PINCTRL_PIN(49, "GPIO_49"), + PINCTRL_PIN(50, "GPIO_50"), + PINCTRL_PIN(51, "GPIO_51"), + PINCTRL_PIN(52, "GPIO_52"), + PINCTRL_PIN(53, "GPIO_53"), + PINCTRL_PIN(54, "GPIO_54"), + PINCTRL_PIN(55, "GPIO_55"), + PINCTRL_PIN(56, "GPIO_56"), + PINCTRL_PIN(57, "GPIO_57"), + PINCTRL_PIN(58, "GPIO_58"), + PINCTRL_PIN(59, "GPIO_59"), + PINCTRL_PIN(60, "GPIO_60"), + PINCTRL_PIN(61, "GPIO_61"), + PINCTRL_PIN(62, "GPIO_62"), + PINCTRL_PIN(63, "GPIO_63"), + PINCTRL_PIN(64, "GPIO_64"), + PINCTRL_PIN(65, "GPIO_65"), + PINCTRL_PIN(66, "GPIO_66"), + PINCTRL_PIN(67, "GPIO_67"), + PINCTRL_PIN(68, "GPIO_68"), + PINCTRL_PIN(69, "GPIO_69"), + PINCTRL_PIN(70, "GPIO_70"), + PINCTRL_PIN(71, "GPIO_71"), + PINCTRL_PIN(72, "GPIO_72"), + PINCTRL_PIN(73, "GPIO_73"), + PINCTRL_PIN(74, "GPIO_74"), + PINCTRL_PIN(75, "GPIO_75"), + PINCTRL_PIN(76, "GPIO_76"), + PINCTRL_PIN(77, "GPIO_77"), + PINCTRL_PIN(78, "GPIO_78"), + PINCTRL_PIN(79, "GPIO_79"), + PINCTRL_PIN(80, "GPIO_80"), + PINCTRL_PIN(81, "GPIO_81"), + PINCTRL_PIN(82, "GPIO_82"), + PINCTRL_PIN(83, "GPIO_83"), + PINCTRL_PIN(84, "GPIO_84"), + PINCTRL_PIN(85, "GPIO_85"), + PINCTRL_PIN(86, "GPIO_86"), + PINCTRL_PIN(87, "GPIO_87"), + PINCTRL_PIN(88, "GPIO_88"), + PINCTRL_PIN(89, "GPIO_89"), + PINCTRL_PIN(90, "GPIO_90"), + PINCTRL_PIN(91, "GPIO_91"), + PINCTRL_PIN(92, "GPIO_92"), + PINCTRL_PIN(93, "GPIO_93"), + PINCTRL_PIN(94, "GPIO_94"), + PINCTRL_PIN(95, "GPIO_95"), + PINCTRL_PIN(96, "GPIO_96"), + PINCTRL_PIN(97, "GPIO_97"), + PINCTRL_PIN(98, "GPIO_98"), + PINCTRL_PIN(99, "GPIO_99"), + PINCTRL_PIN(100, "GPIO_100"), + PINCTRL_PIN(101, "GPIO_101"), + PINCTRL_PIN(102, "GPIO_102"), + PINCTRL_PIN(103, "GPIO_103"), + PINCTRL_PIN(104, "GPIO_104"), + PINCTRL_PIN(105, "GPIO_105"), + PINCTRL_PIN(106, "GPIO_106"), + PINCTRL_PIN(107, "GPIO_107"), + PINCTRL_PIN(108, "GPIO_108"), + PINCTRL_PIN(109, "GPIO_109"), + PINCTRL_PIN(110, "GPIO_110"), + PINCTRL_PIN(111, "GPIO_111"), + PINCTRL_PIN(112, "GPIO_112"), + PINCTRL_PIN(113, "GPIO_113"), + PINCTRL_PIN(114, "GPIO_114"), + PINCTRL_PIN(115, "GPIO_115"), + PINCTRL_PIN(116, "GPIO_116"), + PINCTRL_PIN(117, "GPIO_117"), + PINCTRL_PIN(118, "GPIO_118"), + PINCTRL_PIN(119, "GPIO_119"), + PINCTRL_PIN(120, "GPIO_120"), + PINCTRL_PIN(121, "GPIO_121"), + PINCTRL_PIN(122, "GPIO_122"), + PINCTRL_PIN(123, "GPIO_123"), + PINCTRL_PIN(124, "GPIO_124"), + PINCTRL_PIN(125, "GPIO_125"), + PINCTRL_PIN(126, "GPIO_126"), + PINCTRL_PIN(127, "GPIO_127"), + PINCTRL_PIN(128, "GPIO_128"), + PINCTRL_PIN(129, "GPIO_129"), + PINCTRL_PIN(130, "GPIO_130"), + PINCTRL_PIN(131, "GPIO_131"), + PINCTRL_PIN(132, "GPIO_132"), + PINCTRL_PIN(133, "GPIO_133"), + PINCTRL_PIN(134, "GPIO_134"), + PINCTRL_PIN(135, "GPIO_135"), + PINCTRL_PIN(136, "GPIO_136"), + PINCTRL_PIN(137, "GPIO_137"), + PINCTRL_PIN(138, "GPIO_138"), + PINCTRL_PIN(139, "GPIO_139"), + PINCTRL_PIN(140, "GPIO_140"), + PINCTRL_PIN(141, "GPIO_141"), + PINCTRL_PIN(142, "GPIO_142"), + PINCTRL_PIN(143, "GPIO_143"), + PINCTRL_PIN(144, "GPIO_144"), + PINCTRL_PIN(145, "GPIO_145"), + PINCTRL_PIN(146, "GPIO_146"), + PINCTRL_PIN(147, "GPIO_147"), + PINCTRL_PIN(148, "GPIO_148"), + PINCTRL_PIN(149, "GPIO_149"), + PINCTRL_PIN(150, "GPIO_150"), + PINCTRL_PIN(151, "GPIO_151"), + PINCTRL_PIN(152, "GPIO_152"), + PINCTRL_PIN(153, "GPIO_153"), + PINCTRL_PIN(154, "GPIO_154"), + PINCTRL_PIN(155, "GPIO_155"), + PINCTRL_PIN(156, "GPIO_156"), + PINCTRL_PIN(157, "GPIO_157"), + PINCTRL_PIN(158, "GPIO_158"), + PINCTRL_PIN(159, "GPIO_159"), + PINCTRL_PIN(160, "GPIO_160"), + PINCTRL_PIN(161, "GPIO_161"), + PINCTRL_PIN(162, "GPIO_162"), + PINCTRL_PIN(163, "GPIO_163"), + PINCTRL_PIN(164, "GPIO_164"), + PINCTRL_PIN(165, "GPIO_165"), + PINCTRL_PIN(166, "GPIO_166"), + PINCTRL_PIN(167, "GPIO_167"), + PINCTRL_PIN(168, "GPIO_168"), + PINCTRL_PIN(169, "GPIO_169"), + PINCTRL_PIN(170, "GPIO_170"), + PINCTRL_PIN(171, "GPIO_171"), + PINCTRL_PIN(172, "GPIO_172"), + PINCTRL_PIN(173, "GPIO_173"), + PINCTRL_PIN(174, "GPIO_174"), + PINCTRL_PIN(175, "GPIO_175"), + PINCTRL_PIN(176, "GPIO_176"), + PINCTRL_PIN(177, "GPIO_177"), + PINCTRL_PIN(178, "GPIO_178"), + PINCTRL_PIN(179, "GPIO_179"), + PINCTRL_PIN(180, "GPIO_180"), + PINCTRL_PIN(181, "GPIO_181"), + PINCTRL_PIN(182, "GPIO_182"), + PINCTRL_PIN(183, "GPIO_183"), + PINCTRL_PIN(184, "GPIO_184"), + PINCTRL_PIN(185, "GPIO_185"), + PINCTRL_PIN(186, "GPIO_186"), + PINCTRL_PIN(187, "GPIO_187"), + PINCTRL_PIN(188, "GPIO_188"), + PINCTRL_PIN(189, "GPIO_189"), + PINCTRL_PIN(190, "GPIO_190"), + PINCTRL_PIN(191, "GPIO_191"), + PINCTRL_PIN(192, "GPIO_192"), + PINCTRL_PIN(193, "GPIO_193"), + PINCTRL_PIN(194, "GPIO_194"), + PINCTRL_PIN(195, "GPIO_195"), + PINCTRL_PIN(196, "GPIO_196"), + PINCTRL_PIN(197, "GPIO_197"), + PINCTRL_PIN(198, "GPIO_198"), + PINCTRL_PIN(199, "GPIO_199"), + PINCTRL_PIN(200, "GPIO_200"), + PINCTRL_PIN(201, "GPIO_201"), + PINCTRL_PIN(202, "GPIO_202"), + PINCTRL_PIN(203, "GPIO_203"), + PINCTRL_PIN(204, "GPIO_204"), + PINCTRL_PIN(205, "GPIO_205"), + PINCTRL_PIN(206, "GPIO_206"), + PINCTRL_PIN(207, "GPIO_207"), + PINCTRL_PIN(208, "GPIO_208"), + PINCTRL_PIN(209, "GPIO_209"), + PINCTRL_PIN(210, "GPIO_210"), + PINCTRL_PIN(211, "GPIO_211"), + PINCTRL_PIN(212, "GPIO_212"), + PINCTRL_PIN(213, "GPIO_213"), + PINCTRL_PIN(214, "GPIO_214"), + PINCTRL_PIN(215, "GPIO_215"), + PINCTRL_PIN(216, "GPIO_216"), + PINCTRL_PIN(217, "GPIO_217"), + PINCTRL_PIN(218, "GPIO_218"), + PINCTRL_PIN(219, "GPIO_219"), + PINCTRL_PIN(220, "GPIO_220"), + PINCTRL_PIN(221, "GPIO_221"), + PINCTRL_PIN(222, "GPIO_222"), + PINCTRL_PIN(223, "GPIO_223"), + PINCTRL_PIN(224, "GPIO_224"), + PINCTRL_PIN(225, "GPIO_225"), + PINCTRL_PIN(226, "GPIO_226"), + PINCTRL_PIN(227, "GPIO_227"), + PINCTRL_PIN(228, "UFS_RESET"), + PINCTRL_PIN(229, "UFS1_RESET"), + PINCTRL_PIN(230, "SDC2_CLK"), + PINCTRL_PIN(231, "SDC2_CMD"), + PINCTRL_PIN(232, "SDC2_DATA"), +}; + +#define DECLARE_MSM_GPIO_PINS(pin) \ + static const unsigned int gpio##pin##_pins[] = { pin } +DECLARE_MSM_GPIO_PINS(0); +DECLARE_MSM_GPIO_PINS(1); +DECLARE_MSM_GPIO_PINS(2); +DECLARE_MSM_GPIO_PINS(3); +DECLARE_MSM_GPIO_PINS(4); +DECLARE_MSM_GPIO_PINS(5); +DECLARE_MSM_GPIO_PINS(6); +DECLARE_MSM_GPIO_PINS(7); +DECLARE_MSM_GPIO_PINS(8); +DECLARE_MSM_GPIO_PINS(9); +DECLARE_MSM_GPIO_PINS(10); +DECLARE_MSM_GPIO_PINS(11); +DECLARE_MSM_GPIO_PINS(12); +DECLARE_MSM_GPIO_PINS(13); +DECLARE_MSM_GPIO_PINS(14); +DECLARE_MSM_GPIO_PINS(15); +DECLARE_MSM_GPIO_PINS(16); +DECLARE_MSM_GPIO_PINS(17); +DECLARE_MSM_GPIO_PINS(18); +DECLARE_MSM_GPIO_PINS(19); +DECLARE_MSM_GPIO_PINS(20); +DECLARE_MSM_GPIO_PINS(21); +DECLARE_MSM_GPIO_PINS(22); +DECLARE_MSM_GPIO_PINS(23); +DECLARE_MSM_GPIO_PINS(24); +DECLARE_MSM_GPIO_PINS(25); +DECLARE_MSM_GPIO_PINS(26); +DECLARE_MSM_GPIO_PINS(27); +DECLARE_MSM_GPIO_PINS(28); +DECLARE_MSM_GPIO_PINS(29); +DECLARE_MSM_GPIO_PINS(30); +DECLARE_MSM_GPIO_PINS(31); +DECLARE_MSM_GPIO_PINS(32); +DECLARE_MSM_GPIO_PINS(33); +DECLARE_MSM_GPIO_PINS(34); +DECLARE_MSM_GPIO_PINS(35); +DECLARE_MSM_GPIO_PINS(36); +DECLARE_MSM_GPIO_PINS(37); +DECLARE_MSM_GPIO_PINS(38); +DECLARE_MSM_GPIO_PINS(39); +DECLARE_MSM_GPIO_PINS(40); +DECLARE_MSM_GPIO_PINS(41); +DECLARE_MSM_GPIO_PINS(42); +DECLARE_MSM_GPIO_PINS(43); +DECLARE_MSM_GPIO_PINS(44); +DECLARE_MSM_GPIO_PINS(45); +DECLARE_MSM_GPIO_PINS(46); +DECLARE_MSM_GPIO_PINS(47); +DECLARE_MSM_GPIO_PINS(48); +DECLARE_MSM_GPIO_PINS(49); +DECLARE_MSM_GPIO_PINS(50); +DECLARE_MSM_GPIO_PINS(51); +DECLARE_MSM_GPIO_PINS(52); +DECLARE_MSM_GPIO_PINS(53); +DECLARE_MSM_GPIO_PINS(54); +DECLARE_MSM_GPIO_PINS(55); +DECLARE_MSM_GPIO_PINS(56); +DECLARE_MSM_GPIO_PINS(57); +DECLARE_MSM_GPIO_PINS(58); +DECLARE_MSM_GPIO_PINS(59); +DECLARE_MSM_GPIO_PINS(60); +DECLARE_MSM_GPIO_PINS(61); +DECLARE_MSM_GPIO_PINS(62); +DECLARE_MSM_GPIO_PINS(63); +DECLARE_MSM_GPIO_PINS(64); +DECLARE_MSM_GPIO_PINS(65); +DECLARE_MSM_GPIO_PINS(66); +DECLARE_MSM_GPIO_PINS(67); +DECLARE_MSM_GPIO_PINS(68); +DECLARE_MSM_GPIO_PINS(69); +DECLARE_MSM_GPIO_PINS(70); +DECLARE_MSM_GPIO_PINS(71); +DECLARE_MSM_GPIO_PINS(72); +DECLARE_MSM_GPIO_PINS(73); +DECLARE_MSM_GPIO_PINS(74); +DECLARE_MSM_GPIO_PINS(75); +DECLARE_MSM_GPIO_PINS(76); +DECLARE_MSM_GPIO_PINS(77); +DECLARE_MSM_GPIO_PINS(78); +DECLARE_MSM_GPIO_PINS(79); +DECLARE_MSM_GPIO_PINS(80); +DECLARE_MSM_GPIO_PINS(81); +DECLARE_MSM_GPIO_PINS(82); +DECLARE_MSM_GPIO_PINS(83); +DECLARE_MSM_GPIO_PINS(84); +DECLARE_MSM_GPIO_PINS(85); +DECLARE_MSM_GPIO_PINS(86); +DECLARE_MSM_GPIO_PINS(87); +DECLARE_MSM_GPIO_PINS(88); +DECLARE_MSM_GPIO_PINS(89); +DECLARE_MSM_GPIO_PINS(90); +DECLARE_MSM_GPIO_PINS(91); +DECLARE_MSM_GPIO_PINS(92); +DECLARE_MSM_GPIO_PINS(93); +DECLARE_MSM_GPIO_PINS(94); +DECLARE_MSM_GPIO_PINS(95); +DECLARE_MSM_GPIO_PINS(96); +DECLARE_MSM_GPIO_PINS(97); +DECLARE_MSM_GPIO_PINS(98); +DECLARE_MSM_GPIO_PINS(99); +DECLARE_MSM_GPIO_PINS(100); +DECLARE_MSM_GPIO_PINS(101); +DECLARE_MSM_GPIO_PINS(102); +DECLARE_MSM_GPIO_PINS(103); +DECLARE_MSM_GPIO_PINS(104); +DECLARE_MSM_GPIO_PINS(105); +DECLARE_MSM_GPIO_PINS(106); +DECLARE_MSM_GPIO_PINS(107); +DECLARE_MSM_GPIO_PINS(108); +DECLARE_MSM_GPIO_PINS(109); +DECLARE_MSM_GPIO_PINS(110); +DECLARE_MSM_GPIO_PINS(111); +DECLARE_MSM_GPIO_PINS(112); +DECLARE_MSM_GPIO_PINS(113); +DECLARE_MSM_GPIO_PINS(114); +DECLARE_MSM_GPIO_PINS(115); +DECLARE_MSM_GPIO_PINS(116); +DECLARE_MSM_GPIO_PINS(117); +DECLARE_MSM_GPIO_PINS(118); +DECLARE_MSM_GPIO_PINS(119); +DECLARE_MSM_GPIO_PINS(120); +DECLARE_MSM_GPIO_PINS(121); +DECLARE_MSM_GPIO_PINS(122); +DECLARE_MSM_GPIO_PINS(123); +DECLARE_MSM_GPIO_PINS(124); +DECLARE_MSM_GPIO_PINS(125); +DECLARE_MSM_GPIO_PINS(126); +DECLARE_MSM_GPIO_PINS(127); +DECLARE_MSM_GPIO_PINS(128); +DECLARE_MSM_GPIO_PINS(129); +DECLARE_MSM_GPIO_PINS(130); +DECLARE_MSM_GPIO_PINS(131); +DECLARE_MSM_GPIO_PINS(132); +DECLARE_MSM_GPIO_PINS(133); +DECLARE_MSM_GPIO_PINS(134); +DECLARE_MSM_GPIO_PINS(135); +DECLARE_MSM_GPIO_PINS(136); +DECLARE_MSM_GPIO_PINS(137); +DECLARE_MSM_GPIO_PINS(138); +DECLARE_MSM_GPIO_PINS(139); +DECLARE_MSM_GPIO_PINS(140); +DECLARE_MSM_GPIO_PINS(141); +DECLARE_MSM_GPIO_PINS(142); +DECLARE_MSM_GPIO_PINS(143); +DECLARE_MSM_GPIO_PINS(144); +DECLARE_MSM_GPIO_PINS(145); +DECLARE_MSM_GPIO_PINS(146); +DECLARE_MSM_GPIO_PINS(147); +DECLARE_MSM_GPIO_PINS(148); +DECLARE_MSM_GPIO_PINS(149); +DECLARE_MSM_GPIO_PINS(150); +DECLARE_MSM_GPIO_PINS(151); +DECLARE_MSM_GPIO_PINS(152); +DECLARE_MSM_GPIO_PINS(153); +DECLARE_MSM_GPIO_PINS(154); +DECLARE_MSM_GPIO_PINS(155); +DECLARE_MSM_GPIO_PINS(156); +DECLARE_MSM_GPIO_PINS(157); +DECLARE_MSM_GPIO_PINS(158); +DECLARE_MSM_GPIO_PINS(159); +DECLARE_MSM_GPIO_PINS(160); +DECLARE_MSM_GPIO_PINS(161); +DECLARE_MSM_GPIO_PINS(162); +DECLARE_MSM_GPIO_PINS(163); +DECLARE_MSM_GPIO_PINS(164); +DECLARE_MSM_GPIO_PINS(165); +DECLARE_MSM_GPIO_PINS(166); +DECLARE_MSM_GPIO_PINS(167); +DECLARE_MSM_GPIO_PINS(168); +DECLARE_MSM_GPIO_PINS(169); +DECLARE_MSM_GPIO_PINS(170); +DECLARE_MSM_GPIO_PINS(171); +DECLARE_MSM_GPIO_PINS(172); +DECLARE_MSM_GPIO_PINS(173); +DECLARE_MSM_GPIO_PINS(174); +DECLARE_MSM_GPIO_PINS(175); +DECLARE_MSM_GPIO_PINS(176); +DECLARE_MSM_GPIO_PINS(177); +DECLARE_MSM_GPIO_PINS(178); +DECLARE_MSM_GPIO_PINS(179); +DECLARE_MSM_GPIO_PINS(180); +DECLARE_MSM_GPIO_PINS(181); +DECLARE_MSM_GPIO_PINS(182); +DECLARE_MSM_GPIO_PINS(183); +DECLARE_MSM_GPIO_PINS(184); +DECLARE_MSM_GPIO_PINS(185); +DECLARE_MSM_GPIO_PINS(186); +DECLARE_MSM_GPIO_PINS(187); +DECLARE_MSM_GPIO_PINS(188); +DECLARE_MSM_GPIO_PINS(189); +DECLARE_MSM_GPIO_PINS(190); +DECLARE_MSM_GPIO_PINS(191); +DECLARE_MSM_GPIO_PINS(192); +DECLARE_MSM_GPIO_PINS(193); +DECLARE_MSM_GPIO_PINS(194); +DECLARE_MSM_GPIO_PINS(195); +DECLARE_MSM_GPIO_PINS(196); +DECLARE_MSM_GPIO_PINS(197); +DECLARE_MSM_GPIO_PINS(198); +DECLARE_MSM_GPIO_PINS(199); +DECLARE_MSM_GPIO_PINS(200); +DECLARE_MSM_GPIO_PINS(201); +DECLARE_MSM_GPIO_PINS(202); +DECLARE_MSM_GPIO_PINS(203); +DECLARE_MSM_GPIO_PINS(204); +DECLARE_MSM_GPIO_PINS(205); +DECLARE_MSM_GPIO_PINS(206); +DECLARE_MSM_GPIO_PINS(207); +DECLARE_MSM_GPIO_PINS(208); +DECLARE_MSM_GPIO_PINS(209); +DECLARE_MSM_GPIO_PINS(210); +DECLARE_MSM_GPIO_PINS(211); +DECLARE_MSM_GPIO_PINS(212); +DECLARE_MSM_GPIO_PINS(213); +DECLARE_MSM_GPIO_PINS(214); +DECLARE_MSM_GPIO_PINS(215); +DECLARE_MSM_GPIO_PINS(216); +DECLARE_MSM_GPIO_PINS(217); +DECLARE_MSM_GPIO_PINS(218); +DECLARE_MSM_GPIO_PINS(219); +DECLARE_MSM_GPIO_PINS(220); +DECLARE_MSM_GPIO_PINS(221); +DECLARE_MSM_GPIO_PINS(222); +DECLARE_MSM_GPIO_PINS(223); +DECLARE_MSM_GPIO_PINS(224); +DECLARE_MSM_GPIO_PINS(225); +DECLARE_MSM_GPIO_PINS(226); +DECLARE_MSM_GPIO_PINS(227); + +static const unsigned int ufs_reset_pins[] = { 228 }; +static const unsigned int ufs1_reset_pins[] = { 229 }; +static const unsigned int sdc2_clk_pins[] = { 230 }; +static const unsigned int sdc2_cmd_pins[] = { 231 }; +static const unsigned int sdc2_data_pins[] = { 232 }; + +enum sc8280xp_functions { + msm_mux_atest_char, + msm_mux_atest_usb, + msm_mux_audio_ref, + msm_mux_cam_mclk, + msm_mux_cci_async, + msm_mux_cci_i2c, + msm_mux_cci_timer0, + msm_mux_cci_timer1, + msm_mux_cci_timer2, + msm_mux_cci_timer3, + msm_mux_cci_timer4, + msm_mux_cci_timer5, + msm_mux_cci_timer6, + msm_mux_cci_timer7, + msm_mux_cci_timer8, + msm_mux_cci_timer9, + msm_mux_cmu_rng, + msm_mux_cri_trng, + msm_mux_cri_trng0, + msm_mux_cri_trng1, + msm_mux_dbg_out, + msm_mux_ddr_bist, + msm_mux_ddr_pxi0, + msm_mux_ddr_pxi1, + msm_mux_ddr_pxi2, + msm_mux_ddr_pxi3, + msm_mux_ddr_pxi4, + msm_mux_ddr_pxi5, + msm_mux_ddr_pxi6, + msm_mux_ddr_pxi7, + msm_mux_dp2_hot, + msm_mux_dp3_hot, + msm_mux_edp0_lcd, + msm_mux_edp1_lcd, + msm_mux_edp2_lcd, + msm_mux_edp3_lcd, + msm_mux_edp_hot, + msm_mux_egpio, + msm_mux_emac0_dll, + msm_mux_emac0_mcg0, + msm_mux_emac0_mcg1, + msm_mux_emac0_mcg2, + msm_mux_emac0_mcg3, + msm_mux_emac0_phy, + msm_mux_emac0_ptp, + msm_mux_emac1_dll0, + msm_mux_emac1_dll1, + msm_mux_emac1_mcg0, + msm_mux_emac1_mcg1, + msm_mux_emac1_mcg2, + msm_mux_emac1_mcg3, + msm_mux_emac1_phy, + msm_mux_emac1_ptp, + msm_mux_gcc_gp1, + msm_mux_gcc_gp2, + msm_mux_gcc_gp3, + msm_mux_gcc_gp4, + msm_mux_gcc_gp5, + msm_mux_gpio, + msm_mux_hs1_mi2s, + msm_mux_hs2_mi2s, + msm_mux_hs3_mi2s, + msm_mux_ibi_i3c, + msm_mux_jitter_bist, + msm_mux_lpass_slimbus, + msm_mux_mdp0_vsync0, + msm_mux_mdp0_vsync1, + msm_mux_mdp0_vsync2, + msm_mux_mdp0_vsync3, + msm_mux_mdp0_vsync4, + msm_mux_mdp0_vsync5, + msm_mux_mdp0_vsync6, + msm_mux_mdp0_vsync7, + msm_mux_mdp0_vsync8, + msm_mux_mdp1_vsync0, + msm_mux_mdp1_vsync1, + msm_mux_mdp1_vsync2, + msm_mux_mdp1_vsync3, + msm_mux_mdp1_vsync4, + msm_mux_mdp1_vsync5, + msm_mux_mdp1_vsync6, + msm_mux_mdp1_vsync7, + msm_mux_mdp1_vsync8, + msm_mux_mdp_vsync, + msm_mux_mi2s0_data0, + msm_mux_mi2s0_data1, + msm_mux_mi2s0_sck, + msm_mux_mi2s0_ws, + msm_mux_mi2s1_data0, + msm_mux_mi2s1_data1, + msm_mux_mi2s1_sck, + msm_mux_mi2s1_ws, + msm_mux_mi2s2_data0, + msm_mux_mi2s2_data1, + msm_mux_mi2s2_sck, + msm_mux_mi2s2_ws, + msm_mux_mi2s_mclk1, + msm_mux_mi2s_mclk2, + msm_mux_pcie2a_clkreq, + msm_mux_pcie2b_clkreq, + msm_mux_pcie3a_clkreq, + msm_mux_pcie3b_clkreq, + msm_mux_pcie4_clkreq, + msm_mux_phase_flag, + msm_mux_pll_bist, + msm_mux_pll_clk, + msm_mux_prng_rosc0, + msm_mux_prng_rosc1, + msm_mux_prng_rosc2, + msm_mux_prng_rosc3, + msm_mux_qdss_cti, + msm_mux_qdss_gpio, + msm_mux_qspi, + msm_mux_qspi_clk, + msm_mux_qspi_cs, + msm_mux_qup0, + msm_mux_qup1, + msm_mux_qup10, + msm_mux_qup11, + msm_mux_qup12, + msm_mux_qup13, + msm_mux_qup14, + msm_mux_qup15, + msm_mux_qup16, + msm_mux_qup17, + msm_mux_qup18, + msm_mux_qup19, + msm_mux_qup2, + msm_mux_qup20, + msm_mux_qup21, + msm_mux_qup22, + msm_mux_qup23, + msm_mux_qup3, + msm_mux_qup4, + msm_mux_qup5, + msm_mux_qup6, + msm_mux_qup7, + msm_mux_qup8, + msm_mux_qup9, + msm_mux_rgmii_0, + msm_mux_rgmii_1, + msm_mux_sd_write, + msm_mux_sdc40, + msm_mux_sdc42, + msm_mux_sdc43, + msm_mux_sdc4_clk, + msm_mux_sdc4_cmd, + msm_mux_tb_trig, + msm_mux_tgu, + msm_mux_tsense_pwm1, + msm_mux_tsense_pwm2, + msm_mux_tsense_pwm3, + msm_mux_tsense_pwm4, + msm_mux_usb0_dp, + msm_mux_usb0_phy, + msm_mux_usb0_sbrx, + msm_mux_usb0_sbtx, + msm_mux_usb0_usb4, + msm_mux_usb1_dp, + msm_mux_usb1_phy, + msm_mux_usb1_sbrx, + msm_mux_usb1_sbtx, + msm_mux_usb1_usb4, + msm_mux_usb2phy_ac, + msm_mux_vsense_trigger, + msm_mux__, +}; + +static const char * const gpio_groups[] = { + "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7", + "gpio8", "gpio9", "gpio10", "gpio11", "gpio12", "gpio13", "gpio14", + "gpio15", "gpio16", "gpio17", "gpio18", "gpio19", "gpio20", "gpio21", + "gpio22", "gpio23", "gpio24", "gpio25", "gpio26", "gpio27", "gpio28", + "gpio29", "gpio30", "gpio31", "gpio32", "gpio33", "gpio34", "gpio35", + "gpio36", "gpio37", "gpio38", "gpio39", "gpio40", "gpio41", "gpio42", + "gpio43", "gpio44", "gpio45", "gpio46", "gpio47", "gpio48", "gpio49", + "gpio50", "gpio51", "gpio52", "gpio53", "gpio54", "gpio55", "gpio56", + "gpio57", "gpio58", "gpio59", "gpio60", "gpio61", "gpio62", "gpio63", + "gpio64", "gpio65", "gpio66", "gpio67", "gpio68", "gpio69", "gpio70", + "gpio71", "gpio72", "gpio73", "gpio74", "gpio75", "gpio76", "gpio78", + "gpio79", "gpio80", "gpio81", "gpio82", "gpio83", "gpio84", "gpio85", + "gpio86", "gpio87", "gpio88", "gpio89", "gpio90", "gpio91", "gpio92", + "gpio93", "gpio94", "gpio95", "gpio96", "gpio97", "gpio98", "gpio99", + "gpio100", "gpio101", "gpio102", "gpio103", "gpio104", "gpio105", + "gpio106", "gpio107", "gpio108", "gpio109", "gpio110", "gpio111", + "gpio112", "gpio113", "gpio114", "gpio115", "gpio116", "gpio117", + "gpio118", "gpio119", "gpio120", "gpio121", "gpio122", "gpio123", + "gpio124", "gpio125", "gpio126", "gpio127", "gpio128", "gpio129", + "gpio130", "gpio131", "gpio132", "gpio133", "gpio134", "gpio135", + "gpio136", "gpio137", "gpio138", "gpio139", "gpio140", "gpio141", + "gpio142", "gpio143", "gpio144", "gpio145", "gpio146", "gpio147", + "gpio148", "gpio149", "gpio150", "gpio151", "gpio152", "gpio153", + "gpio154", "gpio155", "gpio156", "gpio157", "gpio158", "gpio159", + "gpio160", "gpio161", "gpio162", "gpio163", "gpio164", "gpio165", + "gpio166", "gpio167", "gpio168", "gpio169", "gpio170", "gpio171", + "gpio172", "gpio173", "gpio174", "gpio175", "gpio176", "gpio177", + "gpio178", "gpio179", "gpio180", "gpio181", "gpio182", "gpio183", + "gpio184", "gpio185", "gpio186", "gpio187", "gpio188", "gpio189", + "gpio190", "gpio191", "gpio192", "gpio193", "gpio194", "gpio195", + "gpio196", "gpio197", "gpio198", "gpio199", "gpio200", "gpio201", + "gpio202", "gpio203", "gpio204", "gpio205", "gpio206", "gpio207", + "gpio208", "gpio209", "gpio210", "gpio211", "gpio212", "gpio213", + "gpio214", "gpio215", "gpio216", "gpio217", "gpio218", "gpio219", + "gpio220", "gpio221", "gpio222", "gpio223", "gpio224", "gpio225", + "gpio226", "gpio227", +}; + +static const char * const atest_char_groups[] = { + "gpio134", "gpio139", "gpio140", "gpio142", "gpio143", +}; + +static const char * const atest_usb_groups[] = { + "gpio71", "gpio72", "gpio73", "gpio74", "gpio75", "gpio76", "gpio78", + "gpio79", "gpio97", "gpio98", "gpio101", "gpio102", "gpio103", + "gpio104", "gpio105", "gpio110", "gpio111", "gpio112", "gpio113", + "gpio114", "gpio121", "gpio122", "gpio130", "gpio131", "gpio135", + "gpio137", "gpio138", "gpio148", "gpio149", +}; + +static const char * const audio_ref_groups[] = { + "gpio80", +}; + +static const char * const cam_mclk_groups[] = { + "gpio6", "gpio7", "gpio16", "gpio17", "gpio33", "gpio34", "gpio119", + "gpio120", +}; + +static const char * const cci_async_groups[] = { + "gpio15", "gpio119", "gpio120", "gpio160", "gpio161", "gpio167", +}; + +static const char * const cci_i2c_groups[] = { + "gpio10", "gpio11", "gpio12", "gpio13", "gpio113", "gpio114", + "gpio115", "gpio116", "gpio117", "gpio118", "gpio123", "gpio124", + "gpio145", "gpio146", "gpio164", "gpio165", +}; + +static const char * const cci_timer0_groups[] = { + "gpio119", +}; + +static const char * const cci_timer1_groups[] = { + "gpio120", +}; + +static const char * const cci_timer2_groups[] = { + "gpio14", +}; + +static const char * const cci_timer3_groups[] = { + "gpio15", +}; + +static const char * const cci_timer4_groups[] = { + "gpio161", +}; + +static const char * const cci_timer5_groups[] = { + "gpio139", +}; + +static const char * const cci_timer6_groups[] = { + "gpio162", +}; + +static const char * const cci_timer7_groups[] = { + "gpio163", +}; + +static const char * const cci_timer8_groups[] = { + "gpio167", +}; + +static const char * const cci_timer9_groups[] = { + "gpio160", +}; + +static const char * const cmu_rng_groups[] = { + "gpio123", "gpio124", "gpio126", "gpio136", +}; + +static const char * const cri_trng0_groups[] = { + "gpio187", +}; + +static const char * const cri_trng1_groups[] = { + "gpio188", +}; + +static const char * const cri_trng_groups[] = { + "gpio190", +}; + +static const char * const dbg_out_groups[] = { + "gpio125", +}; + +static const char * const ddr_bist_groups[] = { + "gpio42", "gpio45", "gpio46", "gpio47", +}; + +static const char * const ddr_pxi0_groups[] = { + "gpio121", "gpio126", +}; + +static const char * const ddr_pxi1_groups[] = { + "gpio124", "gpio125", +}; + +static const char * const ddr_pxi2_groups[] = { + "gpio123", "gpio138", +}; + +static const char * const ddr_pxi3_groups[] = { + "gpio120", "gpio137", +}; + +static const char * const ddr_pxi4_groups[] = { + "gpio216", "gpio217", +}; + +static const char * const ddr_pxi5_groups[] = { + "gpio214", "gpio215", +}; + +static const char * const ddr_pxi6_groups[] = { + "gpio79", "gpio218", +}; + +static const char * const ddr_pxi7_groups[] = { + "gpio135", "gpio136", +}; + +static const char * const dp2_hot_groups[] = { + "gpio20", +}; + +static const char * const dp3_hot_groups[] = { + "gpio45", +}; + +static const char * const edp0_lcd_groups[] = { + "gpio26", +}; + +static const char * const edp1_lcd_groups[] = { + "gpio27", +}; + +static const char * const edp2_lcd_groups[] = { + "gpio28", +}; + +static const char * const edp3_lcd_groups[] = { + "gpio29", +}; + +static const char * const edp_hot_groups[] = { + "gpio2", "gpio3", "gpio6", "gpio7", +}; + +static const char * const egpio_groups[] = { + "gpio189", "gpio190", "gpio191", "gpio192", "gpio193", "gpio194", + "gpio195", "gpio196", "gpio197", "gpio198", "gpio199", "gpio200", + "gpio201", "gpio202", "gpio203", "gpio204", "gpio205", "gpio206", + "gpio207", "gpio208", "gpio209", "gpio210", "gpio211", "gpio212", + "gpio213", "gpio214", "gpio215", "gpio216", "gpio217", "gpio218", + "gpio219", "gpio220", "gpio221", "gpio222", "gpio223", "gpio224", + "gpio225", "gpio226", "gpio227", +}; + +static const char * const emac0_dll_groups[] = { + "gpio216", "gpio217", +}; + +static const char * const emac0_mcg0_groups[] = { + "gpio160", +}; + +static const char * const emac0_mcg1_groups[] = { + "gpio161", +}; + +static const char * const emac0_mcg2_groups[] = { + "gpio162", +}; + +static const char * const emac0_mcg3_groups[] = { + "gpio163", +}; + +static const char * const emac0_phy_groups[] = { + "gpio127", +}; + +static const char * const emac0_ptp_groups[] = { + "gpio130", "gpio130", "gpio131", "gpio131", "gpio156", "gpio156", + "gpio157", "gpio157", "gpio158", "gpio158", "gpio159", "gpio159", +}; + +static const char * const emac1_dll0_groups[] = { + "gpio215", +}; + +static const char * const emac1_dll1_groups[] = { + "gpio218", +}; + +static const char * const emac1_mcg0_groups[] = { + "gpio57", +}; + +static const char * const emac1_mcg1_groups[] = { + "gpio58", +}; + +static const char * const emac1_mcg2_groups[] = { + "gpio68", +}; + +static const char * const emac1_mcg3_groups[] = { + "gpio69", +}; + +static const char * const emac1_phy_groups[] = { + "gpio54", +}; + +static const char * const emac1_ptp_groups[] = { + "gpio55", "gpio55", "gpio56", "gpio56", "gpio93", "gpio93", "gpio94", + "gpio94", "gpio95", "gpio95", "gpio96", "gpio96", +}; + +static const char * const gcc_gp1_groups[] = { + "gpio119", "gpio149", +}; + +static const char * const gcc_gp2_groups[] = { + "gpio114", "gpio120", +}; + +static const char * const gcc_gp3_groups[] = { + "gpio115", "gpio139", +}; + +static const char * const gcc_gp4_groups[] = { + "gpio160", "gpio162", +}; + +static const char * const gcc_gp5_groups[] = { + "gpio167", "gpio168", +}; + +static const char * const hs1_mi2s_groups[] = { + "gpio208", "gpio209", "gpio210", "gpio211", +}; + +static const char * const hs2_mi2s_groups[] = { + "gpio91", "gpio92", "gpio218", "gpio219", +}; + +static const char * const hs3_mi2s_groups[] = { + "gpio224", "gpio225", "gpio226", "gpio227", +}; + +static const char * const ibi_i3c_groups[] = { + "gpio4", "gpio5", "gpio36", "gpio37", "gpio128", "gpio129", "gpio154", + "gpio155", +}; + +static const char * const jitter_bist_groups[] = { + "gpio140", +}; + +static const char * const lpass_slimbus_groups[] = { + "gpio220", "gpio221", +}; + +static const char * const mdp0_vsync0_groups[] = { + "gpio1", +}; + +static const char * const mdp0_vsync1_groups[] = { + "gpio2", +}; + +static const char * const mdp0_vsync2_groups[] = { + "gpio8", +}; + +static const char * const mdp0_vsync3_groups[] = { + "gpio9", +}; + +static const char * const mdp0_vsync4_groups[] = { + "gpio10", +}; + +static const char * const mdp0_vsync5_groups[] = { + "gpio11", +}; + +static const char * const mdp0_vsync6_groups[] = { + "gpio12", +}; + +static const char * const mdp0_vsync7_groups[] = { + "gpio13", +}; + +static const char * const mdp0_vsync8_groups[] = { + "gpio16", +}; + +static const char * const mdp1_vsync0_groups[] = { + "gpio17", +}; + +static const char * const mdp1_vsync1_groups[] = { + "gpio18", +}; + +static const char * const mdp1_vsync2_groups[] = { + "gpio19", +}; + +static const char * const mdp1_vsync3_groups[] = { + "gpio20", +}; + +static const char * const mdp1_vsync4_groups[] = { + "gpio36", +}; + +static const char * const mdp1_vsync5_groups[] = { + "gpio37", +}; + +static const char * const mdp1_vsync6_groups[] = { + "gpio38", +}; + +static const char * const mdp1_vsync7_groups[] = { + "gpio39", +}; + +static const char * const mdp1_vsync8_groups[] = { + "gpio40", +}; + +static const char * const mdp_vsync_groups[] = { + "gpio8", "gpio100", "gpio101", +}; + +static const char * const mi2s0_data0_groups[] = { + "gpio95", +}; + +static const char * const mi2s0_data1_groups[] = { + "gpio96", +}; + +static const char * const mi2s0_sck_groups[] = { + "gpio93", +}; + +static const char * const mi2s0_ws_groups[] = { + "gpio94", +}; + +static const char * const mi2s1_data0_groups[] = { + "gpio222", +}; + +static const char * const mi2s1_data1_groups[] = { + "gpio223", +}; + +static const char * const mi2s1_sck_groups[] = { + "gpio220", +}; + +static const char * const mi2s1_ws_groups[] = { + "gpio221", +}; + +static const char * const mi2s2_data0_groups[] = { + "gpio214", +}; + +static const char * const mi2s2_data1_groups[] = { + "gpio215", +}; + +static const char * const mi2s2_sck_groups[] = { + "gpio212", +}; + +static const char * const mi2s2_ws_groups[] = { + "gpio213", +}; + +static const char * const mi2s_mclk1_groups[] = { + "gpio80", "gpio216", +}; + +static const char * const mi2s_mclk2_groups[] = { + "gpio217", +}; + +static const char * const pcie2a_clkreq_groups[] = { + "gpio142", +}; + +static const char * const pcie2b_clkreq_groups[] = { + "gpio144", +}; + +static const char * const pcie3a_clkreq_groups[] = { + "gpio150", +}; + +static const char * const pcie3b_clkreq_groups[] = { + "gpio152", +}; + +static const char * const pcie4_clkreq_groups[] = { + "gpio140", +}; + +static const char * const phase_flag_groups[] = { + "gpio80", "gpio81", "gpio82", "gpio83", "gpio87", "gpio88", "gpio89", + "gpio90", "gpio91", "gpio92", "gpio93", "gpio94", "gpio95", "gpio132", + "gpio144", "gpio145", "gpio146", "gpio147", "gpio195", "gpio196", + "gpio197", "gpio198", "gpio202", "gpio219", "gpio220", "gpio221", + "gpio222", "gpio223", "gpio224", "gpio225", "gpio226", "gpio227", +}; + +static const char * const pll_bist_groups[] = { + "gpio84", +}; + +static const char * const pll_clk_groups[] = { + "gpio84", "gpio86", +}; + +static const char * const prng_rosc0_groups[] = { + "gpio189", +}; + +static const char * const prng_rosc1_groups[] = { + "gpio191", +}; + +static const char * const prng_rosc2_groups[] = { + "gpio193", +}; + +static const char * const prng_rosc3_groups[] = { + "gpio194", +}; + +static const char * const qdss_cti_groups[] = { + "gpio3", "gpio4", "gpio7", "gpio21", "gpio30", "gpio30", "gpio31", + "gpio31", +}; + +static const char * const qdss_gpio_groups[] = { + "gpio10", "gpio11", "gpio12", "gpio13", "gpio14", "gpio15", "gpio16", + "gpio17", "gpio80", "gpio96", "gpio115", "gpio116", "gpio117", + "gpio118", "gpio119", "gpio120", "gpio121", "gpio122", "gpio161", + "gpio162", "gpio195", "gpio196", "gpio197", "gpio198", "gpio201", + "gpio202", "gpio206", "gpio207", "gpio212", "gpio213", "gpio214", + "gpio215", "gpio216", "gpio217", "gpio222", "gpio223", +}; + +static const char * const qspi_clk_groups[] = { + "gpio74", +}; + +static const char * const qspi_cs_groups[] = { + "gpio75", "gpio81", +}; + +static const char * const qspi_groups[] = { + "gpio76", "gpio78", "gpio79", +}; + +static const char * const qup0_groups[] = { + "gpio135", "gpio136", "gpio137", "gpio138", +}; + +static const char * const qup10_groups[] = { + "gpio22", "gpio23", "gpio24", "gpio25", +}; + +static const char * const qup11_groups[] = { + "gpio18", "gpio19", "gpio20", "gpio21", +}; + +static const char * const qup12_groups[] = { + "gpio0", "gpio1", "gpio2", "gpio3", +}; + +static const char * const qup13_groups[] = { + "gpio26", "gpio27", "gpio28", "gpio29", +}; + +static const char * const qup14_groups[] = { + "gpio4", "gpio5", "gpio6", "gpio7", +}; + +static const char * const qup15_groups[] = { + "gpio36", "gpio37", "gpio38", "gpio39", +}; + +static const char * const qup16_groups[] = { + "gpio70", "gpio71", "gpio72", "gpio73", +}; + +static const char * const qup17_groups[] = { + "gpio61", "gpio62", "gpio63", "gpio64", +}; + +static const char * const qup18_groups[] = { + "gpio66", "gpio67", "gpio68", "gpio69", +}; + +static const char * const qup19_groups[] = { + "gpio55", "gpio56", "gpio57", "gpio58", +}; + +static const char * const qup1_groups[] = { + "gpio158", "gpio159", "gpio160", "gpio161", +}; + +static const char * const qup20_groups[] = { + "gpio87", "gpio88", "gpio89", "gpio90", "gpio91", "gpio92", "gpio110", +}; + +static const char * const qup21_groups[] = { + "gpio81", "gpio82", "gpio83", "gpio84", +}; + +static const char * const qup22_groups[] = { + "gpio83", "gpio84", "gpio85", "gpio86", +}; + +static const char * const qup23_groups[] = { + "gpio59", "gpio60", "gpio61", "gpio62", +}; + +static const char * const qup2_groups[] = { + "gpio121", "gpio122", "gpio123", "gpio124", +}; + +static const char * const qup3_groups[] = { + "gpio135", "gpio136", "gpio137", "gpio138", +}; + +static const char * const qup4_groups[] = { + "gpio111", "gpio112", "gpio171", "gpio172", "gpio173", "gpio174", + "gpio175", +}; + +static const char * const qup5_groups[] = { + "gpio111", "gpio112", "gpio145", "gpio146", +}; + +static const char * const qup6_groups[] = { + "gpio154", "gpio155", "gpio156", "gpio157", +}; + +static const char * const qup7_groups[] = { + "gpio125", "gpio126", "gpio128", "gpio129", +}; + +static const char * const qup8_groups[] = { + "gpio43", "gpio44", "gpio45", "gpio46", +}; + +static const char * const qup9_groups[] = { + "gpio41", "gpio42", "gpio43", "gpio44", +}; + +static const char * const rgmii_0_groups[] = { + "gpio175", "gpio176", "gpio177", "gpio178", "gpio179", "gpio180", + "gpio181", "gpio182", "gpio183", "gpio184", "gpio185", "gpio186", + "gpio187", "gpio188", +}; + +static const char * const rgmii_1_groups[] = { + "gpio97", "gpio98", "gpio99", "gpio100", "gpio101", "gpio102", + "gpio103", "gpio104", "gpio105", "gpio106", "gpio107", "gpio108", + "gpio109", "gpio110", +}; + +static const char * const sd_write_groups[] = { + "gpio130", +}; + +static const char * const sdc40_groups[] = { + "gpio76", +}; + +static const char * const sdc42_groups[] = { + "gpio78", +}; + +static const char * const sdc43_groups[] = { + "gpio79", +}; + +static const char * const sdc4_clk_groups[] = { + "gpio74", +}; + +static const char * const sdc4_cmd_groups[] = { + "gpio75", +}; + +static const char * const tb_trig_groups[] = { + "gpio153", "gpio157", +}; + +static const char * const tgu_groups[] = { + "gpio101", "gpio102", "gpio103", "gpio104", "gpio105", "gpio106", + "gpio107", "gpio108", +}; + +static const char * const tsense_pwm1_groups[] = { + "gpio70", +}; + +static const char * const tsense_pwm2_groups[] = { + "gpio69", +}; + +static const char * const tsense_pwm3_groups[] = { + "gpio67", +}; + +static const char * const tsense_pwm4_groups[] = { + "gpio65", +}; + +static const char * const usb0_dp_groups[] = { + "gpio21", +}; + +static const char * const usb0_phy_groups[] = { + "gpio166", +}; + +static const char * const usb0_sbrx_groups[] = { + "gpio170", +}; + +static const char * const usb0_sbtx_groups[] = { + "gpio168", "gpio169", +}; + +static const char * const usb0_usb4_groups[] = { + "gpio132", +}; + +static const char * const usb1_dp_groups[] = { + "gpio9", +}; + +static const char * const usb1_phy_groups[] = { + "gpio49", +}; + +static const char * const usb1_sbrx_groups[] = { + "gpio53", +}; + +static const char * const usb1_sbtx_groups[] = { + "gpio51", "gpio52", +}; + +static const char * const usb1_usb4_groups[] = { + "gpio32", +}; + +static const char * const usb2phy_ac_groups[] = { + "gpio24", "gpio25", "gpio133", "gpio134", "gpio148", "gpio149", +}; + +static const char * const vsense_trigger_groups[] = { + "gpio81", +}; + +static const struct pinfunction sc8280xp_functions[] = { + MSM_PIN_FUNCTION(atest_char), + MSM_PIN_FUNCTION(atest_usb), + MSM_PIN_FUNCTION(audio_ref), + MSM_PIN_FUNCTION(cam_mclk), + MSM_PIN_FUNCTION(cci_async), + MSM_PIN_FUNCTION(cci_i2c), + MSM_PIN_FUNCTION(cci_timer0), + MSM_PIN_FUNCTION(cci_timer1), + MSM_PIN_FUNCTION(cci_timer2), + MSM_PIN_FUNCTION(cci_timer3), + MSM_PIN_FUNCTION(cci_timer4), + MSM_PIN_FUNCTION(cci_timer5), + MSM_PIN_FUNCTION(cci_timer6), + MSM_PIN_FUNCTION(cci_timer7), + MSM_PIN_FUNCTION(cci_timer8), + MSM_PIN_FUNCTION(cci_timer9), + MSM_PIN_FUNCTION(cmu_rng), + MSM_PIN_FUNCTION(cri_trng), + MSM_PIN_FUNCTION(cri_trng0), + MSM_PIN_FUNCTION(cri_trng1), + MSM_PIN_FUNCTION(dbg_out), + MSM_PIN_FUNCTION(ddr_bist), + MSM_PIN_FUNCTION(ddr_pxi0), + MSM_PIN_FUNCTION(ddr_pxi1), + MSM_PIN_FUNCTION(ddr_pxi2), + MSM_PIN_FUNCTION(ddr_pxi3), + MSM_PIN_FUNCTION(ddr_pxi4), + MSM_PIN_FUNCTION(ddr_pxi5), + MSM_PIN_FUNCTION(ddr_pxi6), + MSM_PIN_FUNCTION(ddr_pxi7), + MSM_PIN_FUNCTION(dp2_hot), + MSM_PIN_FUNCTION(dp3_hot), + MSM_PIN_FUNCTION(edp0_lcd), + MSM_PIN_FUNCTION(edp1_lcd), + MSM_PIN_FUNCTION(edp2_lcd), + MSM_PIN_FUNCTION(edp3_lcd), + MSM_PIN_FUNCTION(edp_hot), + MSM_PIN_FUNCTION(egpio), + MSM_PIN_FUNCTION(emac0_dll), + MSM_PIN_FUNCTION(emac0_mcg0), + MSM_PIN_FUNCTION(emac0_mcg1), + MSM_PIN_FUNCTION(emac0_mcg2), + MSM_PIN_FUNCTION(emac0_mcg3), + MSM_PIN_FUNCTION(emac0_phy), + MSM_PIN_FUNCTION(emac0_ptp), + MSM_PIN_FUNCTION(emac1_dll0), + MSM_PIN_FUNCTION(emac1_dll1), + MSM_PIN_FUNCTION(emac1_mcg0), + MSM_PIN_FUNCTION(emac1_mcg1), + MSM_PIN_FUNCTION(emac1_mcg2), + MSM_PIN_FUNCTION(emac1_mcg3), + MSM_PIN_FUNCTION(emac1_phy), + MSM_PIN_FUNCTION(emac1_ptp), + MSM_PIN_FUNCTION(gcc_gp1), + MSM_PIN_FUNCTION(gcc_gp2), + MSM_PIN_FUNCTION(gcc_gp3), + MSM_PIN_FUNCTION(gcc_gp4), + MSM_PIN_FUNCTION(gcc_gp5), + MSM_PIN_FUNCTION(gpio), + MSM_PIN_FUNCTION(hs1_mi2s), + MSM_PIN_FUNCTION(hs2_mi2s), + MSM_PIN_FUNCTION(hs3_mi2s), + MSM_PIN_FUNCTION(ibi_i3c), + MSM_PIN_FUNCTION(jitter_bist), + MSM_PIN_FUNCTION(lpass_slimbus), + MSM_PIN_FUNCTION(mdp0_vsync0), + MSM_PIN_FUNCTION(mdp0_vsync1), + MSM_PIN_FUNCTION(mdp0_vsync2), + MSM_PIN_FUNCTION(mdp0_vsync3), + MSM_PIN_FUNCTION(mdp0_vsync4), + MSM_PIN_FUNCTION(mdp0_vsync5), + MSM_PIN_FUNCTION(mdp0_vsync6), + MSM_PIN_FUNCTION(mdp0_vsync7), + MSM_PIN_FUNCTION(mdp0_vsync8), + MSM_PIN_FUNCTION(mdp1_vsync0), + MSM_PIN_FUNCTION(mdp1_vsync1), + MSM_PIN_FUNCTION(mdp1_vsync2), + MSM_PIN_FUNCTION(mdp1_vsync3), + MSM_PIN_FUNCTION(mdp1_vsync4), + MSM_PIN_FUNCTION(mdp1_vsync5), + MSM_PIN_FUNCTION(mdp1_vsync6), + MSM_PIN_FUNCTION(mdp1_vsync7), + MSM_PIN_FUNCTION(mdp1_vsync8), + MSM_PIN_FUNCTION(mdp_vsync), + MSM_PIN_FUNCTION(mi2s0_data0), + MSM_PIN_FUNCTION(mi2s0_data1), + MSM_PIN_FUNCTION(mi2s0_sck), + MSM_PIN_FUNCTION(mi2s0_ws), + MSM_PIN_FUNCTION(mi2s1_data0), + MSM_PIN_FUNCTION(mi2s1_data1), + MSM_PIN_FUNCTION(mi2s1_sck), + MSM_PIN_FUNCTION(mi2s1_ws), + MSM_PIN_FUNCTION(mi2s2_data0), + MSM_PIN_FUNCTION(mi2s2_data1), + MSM_PIN_FUNCTION(mi2s2_sck), + MSM_PIN_FUNCTION(mi2s2_ws), + MSM_PIN_FUNCTION(mi2s_mclk1), + MSM_PIN_FUNCTION(mi2s_mclk2), + MSM_PIN_FUNCTION(pcie2a_clkreq), + MSM_PIN_FUNCTION(pcie2b_clkreq), + MSM_PIN_FUNCTION(pcie3a_clkreq), + MSM_PIN_FUNCTION(pcie3b_clkreq), + MSM_PIN_FUNCTION(pcie4_clkreq), + MSM_PIN_FUNCTION(phase_flag), + MSM_PIN_FUNCTION(pll_bist), + MSM_PIN_FUNCTION(pll_clk), + MSM_PIN_FUNCTION(prng_rosc0), + MSM_PIN_FUNCTION(prng_rosc1), + MSM_PIN_FUNCTION(prng_rosc2), + MSM_PIN_FUNCTION(prng_rosc3), + MSM_PIN_FUNCTION(qdss_cti), + MSM_PIN_FUNCTION(qdss_gpio), + MSM_PIN_FUNCTION(qspi), + MSM_PIN_FUNCTION(qspi_clk), + MSM_PIN_FUNCTION(qspi_cs), + MSM_PIN_FUNCTION(qup0), + MSM_PIN_FUNCTION(qup1), + MSM_PIN_FUNCTION(qup2), + MSM_PIN_FUNCTION(qup3), + MSM_PIN_FUNCTION(qup4), + MSM_PIN_FUNCTION(qup5), + MSM_PIN_FUNCTION(qup6), + MSM_PIN_FUNCTION(qup7), + MSM_PIN_FUNCTION(qup8), + MSM_PIN_FUNCTION(qup9), + MSM_PIN_FUNCTION(qup10), + MSM_PIN_FUNCTION(qup11), + MSM_PIN_FUNCTION(qup12), + MSM_PIN_FUNCTION(qup13), + MSM_PIN_FUNCTION(qup14), + MSM_PIN_FUNCTION(qup15), + MSM_PIN_FUNCTION(qup16), + MSM_PIN_FUNCTION(qup17), + MSM_PIN_FUNCTION(qup18), + MSM_PIN_FUNCTION(qup19), + MSM_PIN_FUNCTION(qup20), + MSM_PIN_FUNCTION(qup21), + MSM_PIN_FUNCTION(qup22), + MSM_PIN_FUNCTION(qup23), + MSM_PIN_FUNCTION(rgmii_0), + MSM_PIN_FUNCTION(rgmii_1), + MSM_PIN_FUNCTION(sd_write), + MSM_PIN_FUNCTION(sdc40), + MSM_PIN_FUNCTION(sdc42), + MSM_PIN_FUNCTION(sdc43), + MSM_PIN_FUNCTION(sdc4_clk), + MSM_PIN_FUNCTION(sdc4_cmd), + MSM_PIN_FUNCTION(tb_trig), + MSM_PIN_FUNCTION(tgu), + MSM_PIN_FUNCTION(tsense_pwm1), + MSM_PIN_FUNCTION(tsense_pwm2), + MSM_PIN_FUNCTION(tsense_pwm3), + MSM_PIN_FUNCTION(tsense_pwm4), + MSM_PIN_FUNCTION(usb0_dp), + MSM_PIN_FUNCTION(usb0_phy), + MSM_PIN_FUNCTION(usb0_sbrx), + MSM_PIN_FUNCTION(usb0_sbtx), + MSM_PIN_FUNCTION(usb0_usb4), + MSM_PIN_FUNCTION(usb1_dp), + MSM_PIN_FUNCTION(usb1_phy), + MSM_PIN_FUNCTION(usb1_sbrx), + MSM_PIN_FUNCTION(usb1_sbtx), + MSM_PIN_FUNCTION(usb1_usb4), + MSM_PIN_FUNCTION(usb2phy_ac), + MSM_PIN_FUNCTION(vsense_trigger), +}; + +static const struct msm_pingroup sc8280xp_groups[] = { + [0] = PINGROUP(0, qup12, _, _, _, _, _, _), + [1] = PINGROUP(1, qup12, mdp0_vsync0, _, _, _, _, _), + [2] = PINGROUP(2, edp_hot, qup12, mdp0_vsync1, _, _, _, _), + [3] = PINGROUP(3, edp_hot, qup12, qdss_cti, _, _, _, _), + [4] = PINGROUP(4, qup14, ibi_i3c, qdss_cti, _, _, _, _), + [5] = PINGROUP(5, qup14, ibi_i3c, _, _, _, _, _), + [6] = PINGROUP(6, edp_hot, qup14, cam_mclk, _, _, _, _), + [7] = PINGROUP(7, edp_hot, qup14, qdss_cti, cam_mclk, _, _, _), + [8] = PINGROUP(8, mdp_vsync, mdp0_vsync2, _, _, _, _, _), + [9] = PINGROUP(9, usb1_dp, mdp0_vsync3, _, _, _, _, _), + [10] = PINGROUP(10, cci_i2c, mdp0_vsync4, _, qdss_gpio, _, _, _), + [11] = PINGROUP(11, cci_i2c, mdp0_vsync5, _, qdss_gpio, _, _, _), + [12] = PINGROUP(12, cci_i2c, mdp0_vsync6, _, qdss_gpio, _, _, _), + [13] = PINGROUP(13, cci_i2c, mdp0_vsync7, _, qdss_gpio, _, _, _), + [14] = PINGROUP(14, cci_timer2, qdss_gpio, _, _, _, _, _), + [15] = PINGROUP(15, cci_timer3, cci_async, _, qdss_gpio, _, _, _), + [16] = PINGROUP(16, cam_mclk, mdp0_vsync8, _, qdss_gpio, _, _, _), + [17] = PINGROUP(17, cam_mclk, mdp1_vsync0, _, qdss_gpio, _, _, _), + [18] = PINGROUP(18, qup11, mdp1_vsync1, _, _, _, _, _), + [19] = PINGROUP(19, qup11, mdp1_vsync2, _, _, _, _, _), + [20] = PINGROUP(20, qup11, dp2_hot, mdp1_vsync3, _, _, _, _), + [21] = PINGROUP(21, qup11, usb0_dp, qdss_cti, _, _, _, _), + [22] = PINGROUP(22, qup10, _, _, _, _, _, _), + [23] = PINGROUP(23, qup10, _, _, _, _, _, _), + [24] = PINGROUP(24, qup10, usb2phy_ac, _, _, _, _, _), + [25] = PINGROUP(25, qup10, usb2phy_ac, _, _, _, _, _), + [26] = PINGROUP(26, qup13, edp0_lcd, _, _, _, _, _), + [27] = PINGROUP(27, qup13, edp1_lcd, _, _, _, _, _), + [28] = PINGROUP(28, qup13, edp2_lcd, _, _, _, _, _), + [29] = PINGROUP(29, qup13, edp3_lcd, _, _, _, _, _), + [30] = PINGROUP(30, qdss_cti, qdss_cti, _, _, _, _, _), + [31] = PINGROUP(31, qdss_cti, qdss_cti, _, _, _, _, _), + [32] = PINGROUP(32, usb1_usb4, _, _, _, _, _, _), + [33] = PINGROUP(33, cam_mclk, _, _, _, _, _, _), + [34] = PINGROUP(34, cam_mclk, _, _, _, _, _, _), + [35] = PINGROUP(35, _, _, _, _, _, _, _), + [36] = PINGROUP(36, qup15, ibi_i3c, mdp1_vsync4, _, _, _, _), + [37] = PINGROUP(37, qup15, ibi_i3c, mdp1_vsync5, _, _, _, _), + [38] = PINGROUP(38, qup15, mdp1_vsync6, _, _, _, _, _), + [39] = PINGROUP(39, qup15, mdp1_vsync7, _, _, _, _, _), + [40] = PINGROUP(40, mdp1_vsync8, _, _, _, _, _, _), + [41] = PINGROUP(41, qup9, _, _, _, _, _, _), + [42] = PINGROUP(42, qup9, ddr_bist, _, _, _, _, _), + [43] = PINGROUP(43, qup8, qup9, _, _, _, _, _), + [44] = PINGROUP(44, qup8, qup9, _, _, _, _, _), + [45] = PINGROUP(45, qup8, dp3_hot, ddr_bist, _, _, _, _), + [46] = PINGROUP(46, qup8, ddr_bist, _, _, _, _, _), + [47] = PINGROUP(47, ddr_bist, _, _, _, _, _, _), + [48] = PINGROUP(48, _, _, _, _, _, _, _), + [49] = PINGROUP(49, usb1_phy, _, _, _, _, _, _), + [50] = PINGROUP(50, _, _, _, _, _, _, _), + [51] = PINGROUP(51, usb1_sbtx, _, _, _, _, _, _), + [52] = PINGROUP(52, usb1_sbtx, _, _, _, _, _, _), + [53] = PINGROUP(53, usb1_sbrx, _, _, _, _, _, _), + [54] = PINGROUP(54, emac1_phy, _, _, _, _, _, _), + [55] = PINGROUP(55, emac1_ptp, emac1_ptp, qup19, _, _, _, _), + [56] = PINGROUP(56, emac1_ptp, emac1_ptp, qup19, _, _, _, _), + [57] = PINGROUP(57, qup19, emac1_mcg0, _, _, _, _, _), + [58] = PINGROUP(58, qup19, emac1_mcg1, _, _, _, _, _), + [59] = PINGROUP(59, qup23, _, _, _, _, _, _), + [60] = PINGROUP(60, qup23, _, _, _, _, _, _), + [61] = PINGROUP(61, qup23, qup17, _, _, _, _, _), + [62] = PINGROUP(62, qup23, qup17, _, _, _, _, _), + [63] = PINGROUP(63, qup17, _, _, _, _, _, _), + [64] = PINGROUP(64, qup17, _, _, _, _, _, _), + [65] = PINGROUP(65, tsense_pwm4, _, _, _, _, _, _), + [66] = PINGROUP(66, qup18, _, _, _, _, _, _), + [67] = PINGROUP(67, qup18, tsense_pwm3, _, _, _, _, _), + [68] = PINGROUP(68, qup18, emac1_mcg2, _, _, _, _, _), + [69] = PINGROUP(69, qup18, emac1_mcg3, tsense_pwm2, _, _, _, _), + [70] = PINGROUP(70, qup16, tsense_pwm1, _, _, _, _, _), + [71] = PINGROUP(71, qup16, atest_usb, _, _, _, _, _), + [72] = PINGROUP(72, qup16, atest_usb, _, _, _, _, _), + [73] = PINGROUP(73, qup16, atest_usb, _, _, _, _, _), + [74] = PINGROUP(74, qspi_clk, sdc4_clk, atest_usb, _, _, _, _), + [75] = PINGROUP(75, qspi_cs, sdc4_cmd, atest_usb, _, _, _, _), + [76] = PINGROUP(76, qspi, sdc40, atest_usb, _, _, _, _), + [77] = PINGROUP(77, _, _, _, _, _, _, _), + [78] = PINGROUP(78, qspi, sdc42, atest_usb, _, _, _, _), + [79] = PINGROUP(79, qspi, sdc43, atest_usb, ddr_pxi6, _, _, _), + [80] = PINGROUP(80, mi2s_mclk1, audio_ref, phase_flag, _, qdss_gpio, _, _), + [81] = PINGROUP(81, qup21, qspi_cs, phase_flag, _, vsense_trigger, _, _), + [82] = PINGROUP(82, qup21, phase_flag, _, _, _, _, _), + [83] = PINGROUP(83, qup21, qup22, phase_flag, _, _, _, _), + [84] = PINGROUP(84, qup21, qup22, pll_bist, pll_clk, _, _, _), + [85] = PINGROUP(85, qup22, _, _, _, _, _, _), + [86] = PINGROUP(86, qup22, _, pll_clk, _, _, _, _), + [87] = PINGROUP(87, qup20, phase_flag, _, _, _, _, _), + [88] = PINGROUP(88, qup20, phase_flag, _, _, _, _, _), + [89] = PINGROUP(89, qup20, phase_flag, _, _, _, _, _), + [90] = PINGROUP(90, qup20, phase_flag, _, _, _, _, _), + [91] = PINGROUP(91, qup20, hs2_mi2s, phase_flag, _, _, _, _), + [92] = PINGROUP(92, qup20, hs2_mi2s, phase_flag, _, _, _, _), + [93] = PINGROUP(93, mi2s0_sck, emac1_ptp, emac1_ptp, phase_flag, _, _, _), + [94] = PINGROUP(94, mi2s0_ws, emac1_ptp, emac1_ptp, phase_flag, _, _, _), + [95] = PINGROUP(95, mi2s0_data0, emac1_ptp, emac1_ptp, phase_flag, _, _, _), + [96] = PINGROUP(96, mi2s0_data1, emac1_ptp, emac1_ptp, qdss_gpio, _, _, _), + [97] = PINGROUP(97, rgmii_1, atest_usb, _, _, _, _, _), + [98] = PINGROUP(98, rgmii_1, atest_usb, _, _, _, _, _), + [99] = PINGROUP(99, rgmii_1, _, _, _, _, _, _), + [100] = PINGROUP(100, mdp_vsync, rgmii_1, _, _, _, _, _), + [101] = PINGROUP(101, mdp_vsync, rgmii_1, tgu, atest_usb, _, _, _), + [102] = PINGROUP(102, rgmii_1, tgu, atest_usb, _, _, _, _), + [103] = PINGROUP(103, rgmii_1, tgu, atest_usb, _, _, _, _), + [104] = PINGROUP(104, rgmii_1, tgu, atest_usb, _, _, _, _), + [105] = PINGROUP(105, rgmii_1, tgu, atest_usb, _, _, _, _), + [106] = PINGROUP(106, rgmii_1, tgu, _, _, _, _, _), + [107] = PINGROUP(107, rgmii_1, tgu, _, _, _, _, _), + [108] = PINGROUP(108, rgmii_1, tgu, _, _, _, _, _), + [109] = PINGROUP(109, rgmii_1, _, _, _, _, _, _), + [110] = PINGROUP(110, qup20, rgmii_1, atest_usb, _, _, _, _), + [111] = PINGROUP(111, qup4, qup5, atest_usb, _, _, _, _), + [112] = PINGROUP(112, qup4, qup5, atest_usb, _, _, _, _), + [113] = PINGROUP(113, cci_i2c, atest_usb, _, _, _, _, _), + [114] = PINGROUP(114, cci_i2c, gcc_gp2, atest_usb, _, _, _, _), + [115] = PINGROUP(115, cci_i2c, gcc_gp3, qdss_gpio, _, _, _, _), + [116] = PINGROUP(116, cci_i2c, qdss_gpio, _, _, _, _, _), + [117] = PINGROUP(117, cci_i2c, _, qdss_gpio, _, _, _, _), + [118] = PINGROUP(118, cci_i2c, _, qdss_gpio, _, _, _, _), + [119] = PINGROUP(119, cam_mclk, cci_timer0, cci_async, gcc_gp1, qdss_gpio, _, _), + [120] = PINGROUP(120, cam_mclk, cci_timer1, cci_async, gcc_gp2, qdss_gpio, ddr_pxi3, _), + [121] = PINGROUP(121, qup2, qdss_gpio, _, atest_usb, ddr_pxi0, _, _), + [122] = PINGROUP(122, qup2, qdss_gpio, atest_usb, _, _, _, _), + [123] = PINGROUP(123, qup2, cci_i2c, cmu_rng, ddr_pxi2, _, _, _), + [124] = PINGROUP(124, qup2, cci_i2c, cmu_rng, ddr_pxi1, _, _, _), + [125] = PINGROUP(125, qup7, dbg_out, ddr_pxi1, _, _, _, _), + [126] = PINGROUP(126, qup7, cmu_rng, ddr_pxi0, _, _, _, _), + [127] = PINGROUP(127, emac0_phy, _, _, _, _, _, _), + [128] = PINGROUP(128, qup7, ibi_i3c, _, _, _, _, _), + [129] = PINGROUP(129, qup7, ibi_i3c, _, _, _, _, _), + [130] = PINGROUP(130, emac0_ptp, emac0_ptp, sd_write, atest_usb, _, _, _), + [131] = PINGROUP(131, emac0_ptp, emac0_ptp, atest_usb, _, _, _, _), + [132] = PINGROUP(132, usb0_usb4, phase_flag, _, _, _, _, _), + [133] = PINGROUP(133, usb2phy_ac, _, _, _, _, _, _), + [134] = PINGROUP(134, usb2phy_ac, atest_char, _, _, _, _, _), + [135] = PINGROUP(135, qup0, qup3, _, atest_usb, ddr_pxi7, _, _), + [136] = PINGROUP(136, qup0, qup3, cmu_rng, ddr_pxi7, _, _, _), + [137] = PINGROUP(137, qup3, qup0, _, atest_usb, ddr_pxi3, _, _), + [138] = PINGROUP(138, qup3, qup0, _, atest_usb, ddr_pxi2, _, _), + [139] = PINGROUP(139, cci_timer5, gcc_gp3, atest_char, _, _, _, _), + [140] = PINGROUP(140, pcie4_clkreq, jitter_bist, atest_char, _, _, _, _), + [141] = PINGROUP(141, _, _, _, _, _, _, _), + [142] = PINGROUP(142, pcie2a_clkreq, atest_char, _, _, _, _, _), + [143] = PINGROUP(143, _, atest_char, _, _, _, _, _), + [144] = PINGROUP(144, pcie2b_clkreq, phase_flag, _, _, _, _, _), + [145] = PINGROUP(145, qup5, cci_i2c, phase_flag, _, _, _, _), + [146] = PINGROUP(146, qup5, cci_i2c, phase_flag, _, _, _, _), + [147] = PINGROUP(147, _, phase_flag, _, _, _, _, _), + [148] = PINGROUP(148, usb2phy_ac, _, atest_usb, _, _, _, _), + [149] = PINGROUP(149, usb2phy_ac, gcc_gp1, atest_usb, _, _, _, _), + [150] = PINGROUP(150, pcie3a_clkreq, _, _, _, _, _, _), + [151] = PINGROUP(151, _, _, _, _, _, _, _), + [152] = PINGROUP(152, pcie3b_clkreq, _, _, _, _, _, _), + [153] = PINGROUP(153, _, tb_trig, _, _, _, _, _), + [154] = PINGROUP(154, qup6, ibi_i3c, _, _, _, _, _), + [155] = PINGROUP(155, qup6, ibi_i3c, _, _, _, _, _), + [156] = PINGROUP(156, qup6, emac0_ptp, emac0_ptp, _, _, _, _), + [157] = PINGROUP(157, qup6, emac0_ptp, emac0_ptp, tb_trig, _, _, _), + [158] = PINGROUP(158, qup1, emac0_ptp, emac0_ptp, _, _, _, _), + [159] = PINGROUP(159, qup1, emac0_ptp, emac0_ptp, _, _, _, _), + [160] = PINGROUP(160, cci_timer9, qup1, cci_async, emac0_mcg0, gcc_gp4, _, _), + [161] = PINGROUP(161, cci_timer4, cci_async, qup1, emac0_mcg1, qdss_gpio, _, _), + [162] = PINGROUP(162, cci_timer6, emac0_mcg2, gcc_gp4, qdss_gpio, _, _, _), + [163] = PINGROUP(163, cci_timer7, emac0_mcg3, _, _, _, _, _), + [164] = PINGROUP(164, cci_i2c, _, _, _, _, _, _), + [165] = PINGROUP(165, cci_i2c, _, _, _, _, _, _), + [166] = PINGROUP(166, usb0_phy, _, _, _, _, _, _), + [167] = PINGROUP(167, cci_timer8, cci_async, gcc_gp5, _, _, _, _), + [168] = PINGROUP(168, usb0_sbtx, gcc_gp5, _, _, _, _, _), + [169] = PINGROUP(169, usb0_sbtx, _, _, _, _, _, _), + [170] = PINGROUP(170, usb0_sbrx, _, _, _, _, _, _), + [171] = PINGROUP(171, qup4, _, _, _, _, _, _), + [172] = PINGROUP(172, qup4, _, _, _, _, _, _), + [173] = PINGROUP(173, qup4, _, _, _, _, _, _), + [174] = PINGROUP(174, qup4, _, _, _, _, _, _), + [175] = PINGROUP(175, qup4, rgmii_0, _, _, _, _, _), + [176] = PINGROUP(176, rgmii_0, _, _, _, _, _, _), + [177] = PINGROUP(177, rgmii_0, _, _, _, _, _, _), + [178] = PINGROUP(178, rgmii_0, _, _, _, _, _, _), + [179] = PINGROUP(179, rgmii_0, _, _, _, _, _, _), + [180] = PINGROUP(180, rgmii_0, _, _, _, _, _, _), + [181] = PINGROUP(181, rgmii_0, _, _, _, _, _, _), + [182] = PINGROUP(182, rgmii_0, _, _, _, _, _, _), + [183] = PINGROUP(183, rgmii_0, _, _, _, _, _, _), + [184] = PINGROUP(184, rgmii_0, _, _, _, _, _, _), + [185] = PINGROUP(185, rgmii_0, _, _, _, _, _, _), + [186] = PINGROUP(186, rgmii_0, _, _, _, _, _, _), + [187] = PINGROUP(187, rgmii_0, cri_trng0, _, _, _, _, _), + [188] = PINGROUP(188, rgmii_0, cri_trng1, _, _, _, _, _), + [189] = PINGROUP(189, prng_rosc0, _, _, _, _, _, egpio), + [190] = PINGROUP(190, cri_trng, _, _, _, _, _, egpio), + [191] = PINGROUP(191, prng_rosc1, _, _, _, _, _, egpio), + [192] = PINGROUP(192, _, _, _, _, _, _, egpio), + [193] = PINGROUP(193, prng_rosc2, _, _, _, _, _, egpio), + [194] = PINGROUP(194, prng_rosc3, _, _, _, _, _, egpio), + [195] = PINGROUP(195, phase_flag, _, qdss_gpio, _, _, _, egpio), + [196] = PINGROUP(196, phase_flag, _, qdss_gpio, _, _, _, egpio), + [197] = PINGROUP(197, phase_flag, _, qdss_gpio, _, _, _, egpio), + [198] = PINGROUP(198, phase_flag, _, qdss_gpio, _, _, _, egpio), + [199] = PINGROUP(199, _, _, _, _, _, _, egpio), + [200] = PINGROUP(200, _, _, _, _, _, _, egpio), + [201] = PINGROUP(201, qdss_gpio, _, _, _, _, _, egpio), + [202] = PINGROUP(202, phase_flag, _, qdss_gpio, _, _, _, egpio), + [203] = PINGROUP(203, _, _, _, _, _, _, egpio), + [204] = PINGROUP(204, _, _, _, _, _, _, egpio), + [205] = PINGROUP(205, _, _, _, _, _, _, egpio), + [206] = PINGROUP(206, qdss_gpio, _, _, _, _, _, egpio), + [207] = PINGROUP(207, qdss_gpio, _, _, _, _, _, egpio), + [208] = PINGROUP(208, hs1_mi2s, _, _, _, _, _, egpio), + [209] = PINGROUP(209, hs1_mi2s, _, _, _, _, _, egpio), + [210] = PINGROUP(210, hs1_mi2s, _, _, _, _, _, egpio), + [211] = PINGROUP(211, hs1_mi2s, _, _, _, _, _, egpio), + [212] = PINGROUP(212, mi2s2_sck, qdss_gpio, _, _, _, _, egpio), + [213] = PINGROUP(213, mi2s2_ws, qdss_gpio, _, _, _, _, egpio), + [214] = PINGROUP(214, mi2s2_data0, qdss_gpio, ddr_pxi5, _, _, _, egpio), + [215] = PINGROUP(215, mi2s2_data1, qdss_gpio, emac1_dll0, ddr_pxi5, _, _, egpio), + [216] = PINGROUP(216, mi2s_mclk1, qdss_gpio, emac0_dll, ddr_pxi4, _, _, egpio), + [217] = PINGROUP(217, mi2s_mclk2, qdss_gpio, emac0_dll, ddr_pxi4, _, _, egpio), + [218] = PINGROUP(218, hs2_mi2s, emac1_dll1, ddr_pxi6, _, _, _, egpio), + [219] = PINGROUP(219, hs2_mi2s, phase_flag, _, _, _, _, egpio), + [220] = PINGROUP(220, lpass_slimbus, mi2s1_sck, phase_flag, _, _, _, egpio), + [221] = PINGROUP(221, lpass_slimbus, mi2s1_ws, phase_flag, _, _, _, egpio), + [222] = PINGROUP(222, mi2s1_data0, phase_flag, _, qdss_gpio, _, _, egpio), + [223] = PINGROUP(223, mi2s1_data1, phase_flag, _, qdss_gpio, _, _, egpio), + [224] = PINGROUP(224, hs3_mi2s, phase_flag, _, _, _, _, egpio), + [225] = PINGROUP(225, hs3_mi2s, phase_flag, _, _, _, _, egpio), + [226] = PINGROUP(226, hs3_mi2s, phase_flag, _, _, _, _, egpio), + [227] = PINGROUP(227, hs3_mi2s, phase_flag, _, _, _, _, egpio), + [228] = UFS_RESET(ufs_reset, 0xf1000), + [229] = UFS_RESET(ufs1_reset, 0xf3000), + [230] = SDC_QDSD_PINGROUP(sdc2_clk, 0xe8000, 14, 6), + [231] = SDC_QDSD_PINGROUP(sdc2_cmd, 0xe8000, 11, 3), + [232] = SDC_QDSD_PINGROUP(sdc2_data, 0xe8000, 9, 0), +}; + +static const struct msm_gpio_wakeirq_map sc8280xp_pdc_map[] = { + { 3, 245 }, { 4, 263 }, { 7, 254 }, { 21, 220 }, { 25, 244 }, + { 26, 211 }, { 27, 172 }, { 29, 203 }, { 30, 169 }, { 31, 180 }, + { 32, 181 }, { 33, 182 }, { 36, 206 }, { 39, 246 }, { 40, 183 }, + { 42, 179 }, { 46, 247 }, { 53, 248 }, { 54, 190 }, { 55, 249 }, + { 56, 250 }, { 58, 251 }, { 59, 207 }, { 62, 252 }, { 63, 191 }, + { 64, 192 }, { 65, 193 }, { 69, 253 }, { 73, 255 }, { 84, 256 }, + { 85, 208 }, { 90, 257 }, { 102, 214 }, { 103, 215 }, { 104, 216 }, + { 107, 217 }, { 110, 218 }, { 124, 224 }, { 125, 189 }, + { 126, 200 }, { 127, 225 }, { 128, 262 }, { 129, 201 }, + { 130, 209 }, { 131, 173 }, { 132, 202 }, { 136, 210 }, + { 138, 171 }, { 139, 226 }, { 140, 227 }, { 142, 228 }, + { 144, 229 }, { 145, 230 }, { 146, 231 }, { 148, 232 }, + { 149, 233 }, { 150, 234 }, { 152, 235 }, { 154, 212 }, + { 157, 213 }, { 161, 219 }, { 170, 236 }, { 171, 221 }, + { 174, 222 }, { 175, 237 }, { 176, 223 }, { 177, 170 }, + { 180, 238 }, { 181, 239 }, { 182, 240 }, { 183, 241 }, + { 184, 242 }, { 185, 243 }, { 190, 178 }, { 193, 184 }, + { 196, 185 }, { 198, 186 }, { 200, 174 }, { 201, 175 }, + { 205, 176 }, { 206, 177 }, { 208, 187 }, { 210, 198 }, + { 211, 199 }, { 212, 204 }, { 215, 205 }, { 220, 188 }, + { 221, 194 }, { 223, 195 }, { 225, 196 }, { 227, 197 }, +}; + +static struct msm_pinctrl_soc_data sc8280xp_pinctrl = { + .pins = sc8280xp_pins, + .npins = ARRAY_SIZE(sc8280xp_pins), + .functions = sc8280xp_functions, + .nfunctions = ARRAY_SIZE(sc8280xp_functions), + .groups = sc8280xp_groups, + .ngroups = ARRAY_SIZE(sc8280xp_groups), + .ngpios = 230, + .wakeirq_map = sc8280xp_pdc_map, + .nwakeirq_map = ARRAY_SIZE(sc8280xp_pdc_map), + .egpio_func = 7, +}; + +static int sc8280xp_pinctrl_probe(struct platform_device *pdev) +{ + return msm_pinctrl_probe(pdev, &sc8280xp_pinctrl); +} + +static const struct of_device_id sc8280xp_pinctrl_of_match[] = { + { .compatible = "qcom,sc8280xp-tlmm", }, + { }, +}; +MODULE_DEVICE_TABLE(of, sc8280xp_pinctrl_of_match); + +static struct platform_driver sc8280xp_pinctrl_driver = { + .driver = { + .name = "sc8280xp-tlmm", + .of_match_table = sc8280xp_pinctrl_of_match, + }, + .probe = sc8280xp_pinctrl_probe, + .remove = msm_pinctrl_remove, +}; + +static int __init sc8280xp_pinctrl_init(void) +{ + return platform_driver_register(&sc8280xp_pinctrl_driver); +} +arch_initcall(sc8280xp_pinctrl_init); + +static void __exit sc8280xp_pinctrl_exit(void) +{ + platform_driver_unregister(&sc8280xp_pinctrl_driver); +} +module_exit(sc8280xp_pinctrl_exit); + +MODULE_DESCRIPTION("Qualcomm SC8280XP TLMM pinctrl driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/pinctrl/qcom/pinctrl-sdm660.c b/drivers/pinctrl/qcom/pinctrl-sdm660.c new file mode 100644 index 0000000000..c2e0d5c034 --- /dev/null +++ b/drivers/pinctrl/qcom/pinctrl-sdm660.c @@ -0,0 +1,1448 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2016, The Linux Foundation. All rights reserved. + * Copyright (c) 2018, Craig Tatlor. + */ + +#include <linux/module.h> +#include <linux/of.h> +#include <linux/platform_device.h> + +#include "pinctrl-msm.h" + +static const char * const sdm660_tiles[] = { + "north", + "center", + "south" +}; + +enum { + NORTH, + CENTER, + SOUTH +}; + +#define REG_SIZE 0x1000 + +#define PINGROUP(id, _tile, f1, f2, f3, f4, f5, f6, f7, f8, f9) \ + { \ + .grp = PINCTRL_PINGROUP("gpio" #id, \ + gpio##id##_pins, \ + ARRAY_SIZE(gpio##id##_pins)), \ + .funcs = (int[]){ \ + msm_mux_gpio, /* gpio mode */ \ + msm_mux_##f1, \ + msm_mux_##f2, \ + msm_mux_##f3, \ + msm_mux_##f4, \ + msm_mux_##f5, \ + msm_mux_##f6, \ + msm_mux_##f7, \ + msm_mux_##f8, \ + msm_mux_##f9 \ + }, \ + .nfuncs = 10, \ + .ctl_reg = REG_SIZE * id, \ + .io_reg = 0x4 + REG_SIZE * id, \ + .intr_cfg_reg = 0x8 + REG_SIZE * id, \ + .intr_status_reg = 0xc + REG_SIZE * id, \ + .intr_target_reg = 0x8 + REG_SIZE * id, \ + .tile = _tile, \ + .mux_bit = 2, \ + .pull_bit = 0, \ + .drv_bit = 6, \ + .oe_bit = 9, \ + .in_bit = 0, \ + .out_bit = 1, \ + .intr_enable_bit = 0, \ + .intr_status_bit = 0, \ + .intr_target_bit = 5, \ + .intr_target_kpss_val = 3, \ + .intr_raw_status_bit = 4, \ + .intr_polarity_bit = 1, \ + .intr_detection_bit = 2, \ + .intr_detection_width = 2, \ + } + +#define SDC_QDSD_PINGROUP(pg_name, ctl, pull, drv) \ + { \ + .grp = PINCTRL_PINGROUP(#pg_name, \ + pg_name##_pins, \ + ARRAY_SIZE(pg_name##_pins)), \ + .ctl_reg = ctl, \ + .io_reg = 0, \ + .intr_cfg_reg = 0, \ + .intr_status_reg = 0, \ + .intr_target_reg = 0, \ + .tile = NORTH, \ + .mux_bit = -1, \ + .pull_bit = pull, \ + .drv_bit = drv, \ + .oe_bit = -1, \ + .in_bit = -1, \ + .out_bit = -1, \ + .intr_enable_bit = -1, \ + .intr_status_bit = -1, \ + .intr_target_bit = -1, \ + .intr_raw_status_bit = -1, \ + .intr_polarity_bit = -1, \ + .intr_detection_bit = -1, \ + .intr_detection_width = -1, \ + } + +static const struct pinctrl_pin_desc sdm660_pins[] = { + PINCTRL_PIN(0, "GPIO_0"), + PINCTRL_PIN(1, "GPIO_1"), + PINCTRL_PIN(2, "GPIO_2"), + PINCTRL_PIN(3, "GPIO_3"), + PINCTRL_PIN(4, "GPIO_4"), + PINCTRL_PIN(5, "GPIO_5"), + PINCTRL_PIN(6, "GPIO_6"), + PINCTRL_PIN(7, "GPIO_7"), + PINCTRL_PIN(8, "GPIO_8"), + PINCTRL_PIN(9, "GPIO_9"), + PINCTRL_PIN(10, "GPIO_10"), + PINCTRL_PIN(11, "GPIO_11"), + PINCTRL_PIN(12, "GPIO_12"), + PINCTRL_PIN(13, "GPIO_13"), + PINCTRL_PIN(14, "GPIO_14"), + PINCTRL_PIN(15, "GPIO_15"), + PINCTRL_PIN(16, "GPIO_16"), + PINCTRL_PIN(17, "GPIO_17"), + PINCTRL_PIN(18, "GPIO_18"), + PINCTRL_PIN(19, "GPIO_19"), + PINCTRL_PIN(20, "GPIO_20"), + PINCTRL_PIN(21, "GPIO_21"), + PINCTRL_PIN(22, "GPIO_22"), + PINCTRL_PIN(23, "GPIO_23"), + PINCTRL_PIN(24, "GPIO_24"), + PINCTRL_PIN(25, "GPIO_25"), + PINCTRL_PIN(26, "GPIO_26"), + PINCTRL_PIN(27, "GPIO_27"), + PINCTRL_PIN(28, "GPIO_28"), + PINCTRL_PIN(29, "GPIO_29"), + PINCTRL_PIN(30, "GPIO_30"), + PINCTRL_PIN(31, "GPIO_31"), + PINCTRL_PIN(32, "GPIO_32"), + PINCTRL_PIN(33, "GPIO_33"), + PINCTRL_PIN(34, "GPIO_34"), + PINCTRL_PIN(35, "GPIO_35"), + PINCTRL_PIN(36, "GPIO_36"), + PINCTRL_PIN(37, "GPIO_37"), + PINCTRL_PIN(38, "GPIO_38"), + PINCTRL_PIN(39, "GPIO_39"), + PINCTRL_PIN(40, "GPIO_40"), + PINCTRL_PIN(41, "GPIO_41"), + PINCTRL_PIN(42, "GPIO_42"), + PINCTRL_PIN(43, "GPIO_43"), + PINCTRL_PIN(44, "GPIO_44"), + PINCTRL_PIN(45, "GPIO_45"), + PINCTRL_PIN(46, "GPIO_46"), + PINCTRL_PIN(47, "GPIO_47"), + PINCTRL_PIN(48, "GPIO_48"), + PINCTRL_PIN(49, "GPIO_49"), + PINCTRL_PIN(50, "GPIO_50"), + PINCTRL_PIN(51, "GPIO_51"), + PINCTRL_PIN(52, "GPIO_52"), + PINCTRL_PIN(53, "GPIO_53"), + PINCTRL_PIN(54, "GPIO_54"), + PINCTRL_PIN(55, "GPIO_55"), + PINCTRL_PIN(56, "GPIO_56"), + PINCTRL_PIN(57, "GPIO_57"), + PINCTRL_PIN(58, "GPIO_58"), + PINCTRL_PIN(59, "GPIO_59"), + PINCTRL_PIN(60, "GPIO_60"), + PINCTRL_PIN(61, "GPIO_61"), + PINCTRL_PIN(62, "GPIO_62"), + PINCTRL_PIN(63, "GPIO_63"), + PINCTRL_PIN(64, "GPIO_64"), + PINCTRL_PIN(65, "GPIO_65"), + PINCTRL_PIN(66, "GPIO_66"), + PINCTRL_PIN(67, "GPIO_67"), + PINCTRL_PIN(68, "GPIO_68"), + PINCTRL_PIN(69, "GPIO_69"), + PINCTRL_PIN(70, "GPIO_70"), + PINCTRL_PIN(71, "GPIO_71"), + PINCTRL_PIN(72, "GPIO_72"), + PINCTRL_PIN(73, "GPIO_73"), + PINCTRL_PIN(74, "GPIO_74"), + PINCTRL_PIN(75, "GPIO_75"), + PINCTRL_PIN(76, "GPIO_76"), + PINCTRL_PIN(77, "GPIO_77"), + PINCTRL_PIN(78, "GPIO_78"), + PINCTRL_PIN(79, "GPIO_79"), + PINCTRL_PIN(80, "GPIO_80"), + PINCTRL_PIN(81, "GPIO_81"), + PINCTRL_PIN(82, "GPIO_82"), + PINCTRL_PIN(83, "GPIO_83"), + PINCTRL_PIN(84, "GPIO_84"), + PINCTRL_PIN(85, "GPIO_85"), + PINCTRL_PIN(86, "GPIO_86"), + PINCTRL_PIN(87, "GPIO_87"), + PINCTRL_PIN(88, "GPIO_88"), + PINCTRL_PIN(89, "GPIO_89"), + PINCTRL_PIN(90, "GPIO_90"), + PINCTRL_PIN(91, "GPIO_91"), + PINCTRL_PIN(92, "GPIO_92"), + PINCTRL_PIN(93, "GPIO_93"), + PINCTRL_PIN(94, "GPIO_94"), + PINCTRL_PIN(95, "GPIO_95"), + PINCTRL_PIN(96, "GPIO_96"), + PINCTRL_PIN(97, "GPIO_97"), + PINCTRL_PIN(98, "GPIO_98"), + PINCTRL_PIN(99, "GPIO_99"), + PINCTRL_PIN(100, "GPIO_100"), + PINCTRL_PIN(101, "GPIO_101"), + PINCTRL_PIN(102, "GPIO_102"), + PINCTRL_PIN(103, "GPIO_103"), + PINCTRL_PIN(104, "GPIO_104"), + PINCTRL_PIN(105, "GPIO_105"), + PINCTRL_PIN(106, "GPIO_106"), + PINCTRL_PIN(107, "GPIO_107"), + PINCTRL_PIN(108, "GPIO_108"), + PINCTRL_PIN(109, "GPIO_109"), + PINCTRL_PIN(110, "GPIO_110"), + PINCTRL_PIN(111, "GPIO_111"), + PINCTRL_PIN(112, "GPIO_112"), + PINCTRL_PIN(113, "GPIO_113"), + PINCTRL_PIN(114, "SDC1_CLK"), + PINCTRL_PIN(115, "SDC1_CMD"), + PINCTRL_PIN(116, "SDC1_DATA"), + PINCTRL_PIN(117, "SDC2_CLK"), + PINCTRL_PIN(118, "SDC2_CMD"), + PINCTRL_PIN(119, "SDC2_DATA"), + PINCTRL_PIN(120, "SDC1_RCLK"), +}; + +#define DECLARE_MSM_GPIO_PINS(pin) \ + static const unsigned int gpio##pin##_pins[] = { pin } +DECLARE_MSM_GPIO_PINS(0); +DECLARE_MSM_GPIO_PINS(1); +DECLARE_MSM_GPIO_PINS(2); +DECLARE_MSM_GPIO_PINS(3); +DECLARE_MSM_GPIO_PINS(4); +DECLARE_MSM_GPIO_PINS(5); +DECLARE_MSM_GPIO_PINS(6); +DECLARE_MSM_GPIO_PINS(7); +DECLARE_MSM_GPIO_PINS(8); +DECLARE_MSM_GPIO_PINS(9); +DECLARE_MSM_GPIO_PINS(10); +DECLARE_MSM_GPIO_PINS(11); +DECLARE_MSM_GPIO_PINS(12); +DECLARE_MSM_GPIO_PINS(13); +DECLARE_MSM_GPIO_PINS(14); +DECLARE_MSM_GPIO_PINS(15); +DECLARE_MSM_GPIO_PINS(16); +DECLARE_MSM_GPIO_PINS(17); +DECLARE_MSM_GPIO_PINS(18); +DECLARE_MSM_GPIO_PINS(19); +DECLARE_MSM_GPIO_PINS(20); +DECLARE_MSM_GPIO_PINS(21); +DECLARE_MSM_GPIO_PINS(22); +DECLARE_MSM_GPIO_PINS(23); +DECLARE_MSM_GPIO_PINS(24); +DECLARE_MSM_GPIO_PINS(25); +DECLARE_MSM_GPIO_PINS(26); +DECLARE_MSM_GPIO_PINS(27); +DECLARE_MSM_GPIO_PINS(28); +DECLARE_MSM_GPIO_PINS(29); +DECLARE_MSM_GPIO_PINS(30); +DECLARE_MSM_GPIO_PINS(31); +DECLARE_MSM_GPIO_PINS(32); +DECLARE_MSM_GPIO_PINS(33); +DECLARE_MSM_GPIO_PINS(34); +DECLARE_MSM_GPIO_PINS(35); +DECLARE_MSM_GPIO_PINS(36); +DECLARE_MSM_GPIO_PINS(37); +DECLARE_MSM_GPIO_PINS(38); +DECLARE_MSM_GPIO_PINS(39); +DECLARE_MSM_GPIO_PINS(40); +DECLARE_MSM_GPIO_PINS(41); +DECLARE_MSM_GPIO_PINS(42); +DECLARE_MSM_GPIO_PINS(43); +DECLARE_MSM_GPIO_PINS(44); +DECLARE_MSM_GPIO_PINS(45); +DECLARE_MSM_GPIO_PINS(46); +DECLARE_MSM_GPIO_PINS(47); +DECLARE_MSM_GPIO_PINS(48); +DECLARE_MSM_GPIO_PINS(49); +DECLARE_MSM_GPIO_PINS(50); +DECLARE_MSM_GPIO_PINS(51); +DECLARE_MSM_GPIO_PINS(52); +DECLARE_MSM_GPIO_PINS(53); +DECLARE_MSM_GPIO_PINS(54); +DECLARE_MSM_GPIO_PINS(55); +DECLARE_MSM_GPIO_PINS(56); +DECLARE_MSM_GPIO_PINS(57); +DECLARE_MSM_GPIO_PINS(58); +DECLARE_MSM_GPIO_PINS(59); +DECLARE_MSM_GPIO_PINS(60); +DECLARE_MSM_GPIO_PINS(61); +DECLARE_MSM_GPIO_PINS(62); +DECLARE_MSM_GPIO_PINS(63); +DECLARE_MSM_GPIO_PINS(64); +DECLARE_MSM_GPIO_PINS(65); +DECLARE_MSM_GPIO_PINS(66); +DECLARE_MSM_GPIO_PINS(67); +DECLARE_MSM_GPIO_PINS(68); +DECLARE_MSM_GPIO_PINS(69); +DECLARE_MSM_GPIO_PINS(70); +DECLARE_MSM_GPIO_PINS(71); +DECLARE_MSM_GPIO_PINS(72); +DECLARE_MSM_GPIO_PINS(73); +DECLARE_MSM_GPIO_PINS(74); +DECLARE_MSM_GPIO_PINS(75); +DECLARE_MSM_GPIO_PINS(76); +DECLARE_MSM_GPIO_PINS(77); +DECLARE_MSM_GPIO_PINS(78); +DECLARE_MSM_GPIO_PINS(79); +DECLARE_MSM_GPIO_PINS(80); +DECLARE_MSM_GPIO_PINS(81); +DECLARE_MSM_GPIO_PINS(82); +DECLARE_MSM_GPIO_PINS(83); +DECLARE_MSM_GPIO_PINS(84); +DECLARE_MSM_GPIO_PINS(85); +DECLARE_MSM_GPIO_PINS(86); +DECLARE_MSM_GPIO_PINS(87); +DECLARE_MSM_GPIO_PINS(88); +DECLARE_MSM_GPIO_PINS(89); +DECLARE_MSM_GPIO_PINS(90); +DECLARE_MSM_GPIO_PINS(91); +DECLARE_MSM_GPIO_PINS(92); +DECLARE_MSM_GPIO_PINS(93); +DECLARE_MSM_GPIO_PINS(94); +DECLARE_MSM_GPIO_PINS(95); +DECLARE_MSM_GPIO_PINS(96); +DECLARE_MSM_GPIO_PINS(97); +DECLARE_MSM_GPIO_PINS(98); +DECLARE_MSM_GPIO_PINS(99); +DECLARE_MSM_GPIO_PINS(100); +DECLARE_MSM_GPIO_PINS(101); +DECLARE_MSM_GPIO_PINS(102); +DECLARE_MSM_GPIO_PINS(103); +DECLARE_MSM_GPIO_PINS(104); +DECLARE_MSM_GPIO_PINS(105); +DECLARE_MSM_GPIO_PINS(106); +DECLARE_MSM_GPIO_PINS(107); +DECLARE_MSM_GPIO_PINS(108); +DECLARE_MSM_GPIO_PINS(109); +DECLARE_MSM_GPIO_PINS(110); +DECLARE_MSM_GPIO_PINS(111); +DECLARE_MSM_GPIO_PINS(112); +DECLARE_MSM_GPIO_PINS(113); + +static const unsigned int sdc1_clk_pins[] = { 114 }; +static const unsigned int sdc1_cmd_pins[] = { 115 }; +static const unsigned int sdc1_data_pins[] = { 116 }; +static const unsigned int sdc1_rclk_pins[] = { 120 }; +static const unsigned int sdc2_clk_pins[] = { 117 }; +static const unsigned int sdc2_cmd_pins[] = { 118 }; +static const unsigned int sdc2_data_pins[] = { 119 }; + +enum sdm660_functions { + msm_mux_adsp_ext, + msm_mux_agera_pll, + msm_mux_atest_char, + msm_mux_atest_char0, + msm_mux_atest_char1, + msm_mux_atest_char2, + msm_mux_atest_char3, + msm_mux_atest_gpsadc0, + msm_mux_atest_gpsadc1, + msm_mux_atest_tsens, + msm_mux_atest_tsens2, + msm_mux_atest_usb1, + msm_mux_atest_usb10, + msm_mux_atest_usb11, + msm_mux_atest_usb12, + msm_mux_atest_usb13, + msm_mux_atest_usb2, + msm_mux_atest_usb20, + msm_mux_atest_usb21, + msm_mux_atest_usb22, + msm_mux_atest_usb23, + msm_mux_audio_ref, + msm_mux_bimc_dte0, + msm_mux_bimc_dte1, + msm_mux_blsp_i2c1, + msm_mux_blsp_i2c2, + msm_mux_blsp_i2c3, + msm_mux_blsp_i2c4, + msm_mux_blsp_i2c5, + msm_mux_blsp_i2c6, + msm_mux_blsp_i2c7, + msm_mux_blsp_i2c8_a, + msm_mux_blsp_i2c8_b, + msm_mux_blsp_spi1, + msm_mux_blsp_spi2, + msm_mux_blsp_spi3, + msm_mux_blsp_spi3_cs1, + msm_mux_blsp_spi3_cs2, + msm_mux_blsp_spi4, + msm_mux_blsp_spi5, + msm_mux_blsp_spi6, + msm_mux_blsp_spi7, + msm_mux_blsp_spi8_a, + msm_mux_blsp_spi8_b, + msm_mux_blsp_spi8_cs1, + msm_mux_blsp_spi8_cs2, + msm_mux_blsp_uart1, + msm_mux_blsp_uart2, + msm_mux_blsp_uart5, + msm_mux_blsp_uart6_a, + msm_mux_blsp_uart6_b, + msm_mux_blsp_uim1, + msm_mux_blsp_uim2, + msm_mux_blsp_uim5, + msm_mux_blsp_uim6, + msm_mux_cam_mclk, + msm_mux_cci_async, + msm_mux_cci_i2c, + msm_mux_cri_trng, + msm_mux_cri_trng0, + msm_mux_cri_trng1, + msm_mux_dbg_out, + msm_mux_ddr_bist, + msm_mux_gcc_gp1, + msm_mux_gcc_gp2, + msm_mux_gcc_gp3, + msm_mux_gpio, + msm_mux_gps_tx_a, + msm_mux_gps_tx_b, + msm_mux_gps_tx_c, + msm_mux_isense_dbg, + msm_mux_jitter_bist, + msm_mux_ldo_en, + msm_mux_ldo_update, + msm_mux_m_voc, + msm_mux_mdp_vsync, + msm_mux_mdss_vsync0, + msm_mux_mdss_vsync1, + msm_mux_mdss_vsync2, + msm_mux_mdss_vsync3, + msm_mux_mss_lte, + msm_mux_nav_pps_a, + msm_mux_nav_pps_b, + msm_mux_nav_pps_c, + msm_mux_pa_indicator, + msm_mux_phase_flag0, + msm_mux_phase_flag1, + msm_mux_phase_flag2, + msm_mux_phase_flag3, + msm_mux_phase_flag4, + msm_mux_phase_flag5, + msm_mux_phase_flag6, + msm_mux_phase_flag7, + msm_mux_phase_flag8, + msm_mux_phase_flag9, + msm_mux_phase_flag10, + msm_mux_phase_flag11, + msm_mux_phase_flag12, + msm_mux_phase_flag13, + msm_mux_phase_flag14, + msm_mux_phase_flag15, + msm_mux_phase_flag16, + msm_mux_phase_flag17, + msm_mux_phase_flag18, + msm_mux_phase_flag19, + msm_mux_phase_flag20, + msm_mux_phase_flag21, + msm_mux_phase_flag22, + msm_mux_phase_flag23, + msm_mux_phase_flag24, + msm_mux_phase_flag25, + msm_mux_phase_flag26, + msm_mux_phase_flag27, + msm_mux_phase_flag28, + msm_mux_phase_flag29, + msm_mux_phase_flag30, + msm_mux_phase_flag31, + msm_mux_pll_bypassnl, + msm_mux_pll_reset, + msm_mux_pri_mi2s, + msm_mux_pri_mi2s_ws, + msm_mux_prng_rosc, + msm_mux_pwr_crypto, + msm_mux_pwr_modem, + msm_mux_pwr_nav, + msm_mux_qdss_cti0_a, + msm_mux_qdss_cti0_b, + msm_mux_qdss_cti1_a, + msm_mux_qdss_cti1_b, + msm_mux_qdss_gpio, + msm_mux_qdss_gpio0, + msm_mux_qdss_gpio1, + msm_mux_qdss_gpio10, + msm_mux_qdss_gpio11, + msm_mux_qdss_gpio12, + msm_mux_qdss_gpio13, + msm_mux_qdss_gpio14, + msm_mux_qdss_gpio15, + msm_mux_qdss_gpio2, + msm_mux_qdss_gpio3, + msm_mux_qdss_gpio4, + msm_mux_qdss_gpio5, + msm_mux_qdss_gpio6, + msm_mux_qdss_gpio7, + msm_mux_qdss_gpio8, + msm_mux_qdss_gpio9, + msm_mux_qlink_enable, + msm_mux_qlink_request, + msm_mux_qspi_clk, + msm_mux_qspi_cs, + msm_mux_qspi_data0, + msm_mux_qspi_data1, + msm_mux_qspi_data2, + msm_mux_qspi_data3, + msm_mux_qspi_resetn, + msm_mux_sec_mi2s, + msm_mux_sndwire_clk, + msm_mux_sndwire_data, + msm_mux_sp_cmu, + msm_mux_ssc_irq, + msm_mux_tgu_ch0, + msm_mux_tgu_ch1, + msm_mux_tsense_pwm1, + msm_mux_tsense_pwm2, + msm_mux_uim1_clk, + msm_mux_uim1_data, + msm_mux_uim1_present, + msm_mux_uim1_reset, + msm_mux_uim2_clk, + msm_mux_uim2_data, + msm_mux_uim2_present, + msm_mux_uim2_reset, + msm_mux_uim_batt, + msm_mux_vfr_1, + msm_mux_vsense_clkout, + msm_mux_vsense_data0, + msm_mux_vsense_data1, + msm_mux_vsense_mode, + msm_mux_wlan1_adc0, + msm_mux_wlan1_adc1, + msm_mux_wlan2_adc0, + msm_mux_wlan2_adc1, + msm_mux__, +}; + +static const char * const gpio_groups[] = { + "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7", + "gpio8", "gpio9", "gpio10", "gpio11", "gpio12", "gpio13", "gpio14", + "gpio15", "gpio16", "gpio17", "gpio18", "gpio19", "gpio20", "gpio21", + "gpio22", "gpio23", "gpio24", "gpio25", "gpio26", "gpio27", "gpio28", + "gpio29", "gpio30", "gpio31", "gpio32", "gpio33", "gpio34", "gpio35", + "gpio36", "gpio37", "gpio38", "gpio39", "gpio40", "gpio41", "gpio42", + "gpio43", "gpio44", "gpio45", "gpio46", "gpio47", "gpio48", "gpio49", + "gpio50", "gpio51", "gpio52", "gpio53", "gpio54", "gpio55", "gpio56", + "gpio57", "gpio58", "gpio59", "gpio60", "gpio61", "gpio62", "gpio63", + "gpio64", "gpio65", "gpio66", "gpio67", "gpio68", "gpio69", "gpio70", + "gpio71", "gpio72", "gpio73", "gpio74", "gpio75", "gpio76", "gpio77", + "gpio78", "gpio79", "gpio80", "gpio81", "gpio82", "gpio83", "gpio84", + "gpio85", "gpio86", "gpio87", "gpio88", "gpio89", "gpio90", "gpio91", + "gpio92", "gpio93", "gpio94", "gpio95", "gpio96", "gpio97", "gpio98", + "gpio99", "gpio100", "gpio101", "gpio102", "gpio103", "gpio104", + "gpio105", "gpio106", "gpio107", "gpio108", "gpio109", "gpio110", + "gpio111", "gpio112", "gpio113", +}; + +static const char * const adsp_ext_groups[] = { + "gpio65", +}; +static const char * const agera_pll_groups[] = { + "gpio34", "gpio36", +}; +static const char * const atest_char0_groups[] = { + "gpio62", +}; +static const char * const atest_char1_groups[] = { + "gpio61", +}; +static const char * const atest_char2_groups[] = { + "gpio60", +}; +static const char * const atest_char3_groups[] = { + "gpio59", +}; +static const char * const atest_char_groups[] = { + "gpio58", +}; +static const char * const atest_gpsadc0_groups[] = { + "gpio1", +}; +static const char * const atest_gpsadc1_groups[] = { + "gpio0", +}; +static const char * const atest_tsens2_groups[] = { + "gpio3", +}; +static const char * const atest_tsens_groups[] = { + "gpio36", +}; +static const char * const atest_usb10_groups[] = { + "gpio11", +}; +static const char * const atest_usb11_groups[] = { + "gpio10", +}; +static const char * const atest_usb12_groups[] = { + "gpio9", +}; +static const char * const atest_usb13_groups[] = { + "gpio8", +}; +static const char * const atest_usb1_groups[] = { + "gpio3", +}; +static const char * const atest_usb20_groups[] = { + "gpio56", +}; +static const char * const atest_usb21_groups[] = { + "gpio36", +}; +static const char * const atest_usb22_groups[] = { + "gpio57", +}; +static const char * const atest_usb23_groups[] = { + "gpio37", +}; +static const char * const atest_usb2_groups[] = { + "gpio35", +}; +static const char * const audio_ref_groups[] = { + "gpio62", +}; +static const char * const bimc_dte0_groups[] = { + "gpio9", "gpio11", +}; +static const char * const bimc_dte1_groups[] = { + "gpio8", "gpio10", +}; +static const char * const blsp_i2c1_groups[] = { + "gpio2", "gpio3", +}; +static const char * const blsp_i2c2_groups[] = { + "gpio6", "gpio7", +}; +static const char * const blsp_i2c3_groups[] = { + "gpio10", "gpio11", +}; +static const char * const blsp_i2c4_groups[] = { + "gpio14", "gpio15", +}; +static const char * const blsp_i2c5_groups[] = { + "gpio18", "gpio19", +}; +static const char * const blsp_i2c6_groups[] = { + "gpio22", "gpio23", +}; +static const char * const blsp_i2c7_groups[] = { + "gpio26", "gpio27", +}; +static const char * const blsp_i2c8_a_groups[] = { + "gpio30", "gpio31", +}; +static const char * const blsp_i2c8_b_groups[] = { + "gpio44", "gpio52", +}; +static const char * const blsp_spi1_groups[] = { + "gpio0", "gpio1", "gpio2", "gpio3", "gpio46", +}; +static const char * const blsp_spi2_groups[] = { + "gpio4", "gpio5", "gpio6", "gpio7", +}; +static const char * const blsp_spi3_cs1_groups[] = { + "gpio30", +}; +static const char * const blsp_spi3_cs2_groups[] = { + "gpio65", +}; +static const char * const blsp_spi3_groups[] = { + "gpio8", "gpio9", "gpio10", "gpio11", +}; +static const char * const blsp_spi4_groups[] = { + "gpio12", "gpio13", "gpio14", "gpio15", +}; +static const char * const blsp_spi5_groups[] = { + "gpio16", "gpio17", "gpio18", "gpio19", +}; +static const char * const blsp_spi6_groups[] = { + "gpio49", "gpio52", "gpio22", "gpio23", +}; +static const char * const blsp_spi7_groups[] = { + "gpio24", "gpio25", "gpio26", "gpio27", +}; +static const char * const blsp_spi8_a_groups[] = { + "gpio28", "gpio29", "gpio30", "gpio31", +}; +static const char * const blsp_spi8_b_groups[] = { + "gpio40", "gpio41", "gpio44", "gpio52", +}; +static const char * const blsp_spi8_cs1_groups[] = { + "gpio64", +}; +static const char * const blsp_spi8_cs2_groups[] = { + "gpio76", +}; +static const char * const blsp_uart1_groups[] = { + "gpio0", "gpio1", "gpio2", "gpio3", +}; +static const char * const blsp_uart2_groups[] = { + "gpio4", "gpio5", "gpio6", "gpio7", +}; +static const char * const blsp_uart5_groups[] = { + "gpio16", "gpio17", "gpio18", "gpio19", +}; +static const char * const blsp_uart6_a_groups[] = { + "gpio24", "gpio25", "gpio26", "gpio27", +}; +static const char * const blsp_uart6_b_groups[] = { + "gpio28", "gpio29", "gpio30", "gpio31", +}; +static const char * const blsp_uim1_groups[] = { + "gpio0", "gpio1", +}; +static const char * const blsp_uim2_groups[] = { + "gpio4", "gpio5", +}; +static const char * const blsp_uim5_groups[] = { + "gpio16", "gpio17", +}; +static const char * const blsp_uim6_groups[] = { + "gpio20", "gpio21", +}; +static const char * const cam_mclk_groups[] = { + "gpio32", "gpio33", "gpio34", "gpio35", +}; +static const char * const cci_async_groups[] = { + "gpio45", +}; +static const char * const cci_i2c_groups[] = { + "gpio36", "gpio37", "gpio38", "gpio39", +}; +static const char * const cri_trng0_groups[] = { + "gpio60", +}; +static const char * const cri_trng1_groups[] = { + "gpio61", +}; +static const char * const cri_trng_groups[] = { + "gpio62", +}; +static const char * const dbg_out_groups[] = { + "gpio11", +}; +static const char * const ddr_bist_groups[] = { + "gpio3", "gpio8", "gpio9", "gpio10", +}; +static const char * const gcc_gp1_groups[] = { + "gpio57", "gpio78", +}; +static const char * const gcc_gp2_groups[] = { + "gpio58", "gpio81", +}; +static const char * const gcc_gp3_groups[] = { + "gpio59", "gpio82", +}; +static const char * const gps_tx_a_groups[] = { + "gpio65", +}; +static const char * const gps_tx_b_groups[] = { + "gpio98", +}; +static const char * const gps_tx_c_groups[] = { + "gpio80", +}; +static const char * const isense_dbg_groups[] = { + "gpio68", +}; +static const char * const jitter_bist_groups[] = { + "gpio35", +}; +static const char * const ldo_en_groups[] = { + "gpio97", +}; +static const char * const ldo_update_groups[] = { + "gpio98", +}; +static const char * const m_voc_groups[] = { + "gpio28", +}; +static const char * const mdp_vsync_groups[] = { + "gpio59", "gpio74", +}; +static const char * const mdss_vsync0_groups[] = { + "gpio42", +}; +static const char * const mdss_vsync1_groups[] = { + "gpio42", +}; +static const char * const mdss_vsync2_groups[] = { + "gpio42", +}; +static const char * const mdss_vsync3_groups[] = { + "gpio42", +}; +static const char * const mss_lte_groups[] = { + "gpio81", "gpio82", +}; +static const char * const nav_pps_a_groups[] = { + "gpio65", +}; +static const char * const nav_pps_b_groups[] = { + "gpio98", +}; +static const char * const nav_pps_c_groups[] = { + "gpio80", +}; +static const char * const pa_indicator_groups[] = { + "gpio92", +}; +static const char * const phase_flag0_groups[] = { + "gpio68", +}; +static const char * const phase_flag1_groups[] = { + "gpio48", +}; +static const char * const phase_flag2_groups[] = { + "gpio49", +}; +static const char * const phase_flag3_groups[] = { + "gpio4", +}; +static const char * const phase_flag4_groups[] = { + "gpio57", +}; +static const char * const phase_flag5_groups[] = { + "gpio17", +}; +static const char * const phase_flag6_groups[] = { + "gpio53", +}; +static const char * const phase_flag7_groups[] = { + "gpio69", +}; +static const char * const phase_flag8_groups[] = { + "gpio70", +}; +static const char * const phase_flag9_groups[] = { + "gpio50", +}; +static const char * const phase_flag10_groups[] = { + "gpio56", +}; +static const char * const phase_flag11_groups[] = { + "gpio21", +}; +static const char * const phase_flag12_groups[] = { + "gpio22", +}; +static const char * const phase_flag13_groups[] = { + "gpio23", +}; +static const char * const phase_flag14_groups[] = { + "gpio5", +}; +static const char * const phase_flag15_groups[] = { + "gpio51", +}; +static const char * const phase_flag16_groups[] = { + "gpio52", +}; +static const char * const phase_flag17_groups[] = { + "gpio24", +}; +static const char * const phase_flag18_groups[] = { + "gpio25", +}; +static const char * const phase_flag19_groups[] = { + "gpio26", +}; +static const char * const phase_flag20_groups[] = { + "gpio27", +}; +static const char * const phase_flag21_groups[] = { + "gpio28", +}; +static const char * const phase_flag22_groups[] = { + "gpio29", +}; +static const char * const phase_flag23_groups[] = { + "gpio30", +}; +static const char * const phase_flag24_groups[] = { + "gpio31", +}; +static const char * const phase_flag25_groups[] = { + "gpio55", +}; +static const char * const phase_flag26_groups[] = { + "gpio12", +}; +static const char * const phase_flag27_groups[] = { + "gpio13", +}; +static const char * const phase_flag28_groups[] = { + "gpio14", +}; +static const char * const phase_flag29_groups[] = { + "gpio54", +}; +static const char * const phase_flag30_groups[] = { + "gpio47", +}; +static const char * const phase_flag31_groups[] = { + "gpio6", +}; +static const char * const pll_bypassnl_groups[] = { + "gpio36", +}; +static const char * const pll_reset_groups[] = { + "gpio37", +}; +static const char * const pri_mi2s_groups[] = { + "gpio12", "gpio14", "gpio15", "gpio61", +}; +static const char * const pri_mi2s_ws_groups[] = { + "gpio13", +}; +static const char * const prng_rosc_groups[] = { + "gpio102", +}; +static const char * const pwr_crypto_groups[] = { + "gpio33", +}; +static const char * const pwr_modem_groups[] = { + "gpio31", +}; +static const char * const pwr_nav_groups[] = { + "gpio32", +}; +static const char * const qdss_cti0_a_groups[] = { + "gpio49", "gpio50", +}; +static const char * const qdss_cti0_b_groups[] = { + "gpio13", "gpio21", +}; +static const char * const qdss_cti1_a_groups[] = { + "gpio53", "gpio55", +}; +static const char * const qdss_cti1_b_groups[] = { + "gpio12", "gpio66", +}; +static const char * const qdss_gpio0_groups[] = { + "gpio32", "gpio67", +}; +static const char * const qdss_gpio10_groups[] = { + "gpio43", "gpio77", +}; +static const char * const qdss_gpio11_groups[] = { + "gpio44", "gpio79", +}; +static const char * const qdss_gpio12_groups[] = { + "gpio45", "gpio80", +}; +static const char * const qdss_gpio13_groups[] = { + "gpio46", "gpio78", +}; +static const char * const qdss_gpio14_groups[] = { + "gpio47", "gpio72", +}; +static const char * const qdss_gpio15_groups[] = { + "gpio48", "gpio73", +}; +static const char * const qdss_gpio1_groups[] = { + "gpio33", "gpio63", +}; +static const char * const qdss_gpio2_groups[] = { + "gpio34", "gpio64", +}; +static const char * const qdss_gpio3_groups[] = { + "gpio35", "gpio56", +}; +static const char * const qdss_gpio4_groups[] = { + "gpio0", "gpio36", +}; +static const char * const qdss_gpio5_groups[] = { + "gpio1", "gpio37", +}; +static const char * const qdss_gpio6_groups[] = { + "gpio38", "gpio70", +}; +static const char * const qdss_gpio7_groups[] = { + "gpio39", "gpio71", +}; +static const char * const qdss_gpio8_groups[] = { + "gpio51", "gpio75", +}; +static const char * const qdss_gpio9_groups[] = { + "gpio42", "gpio76", +}; +static const char * const qdss_gpio_groups[] = { + "gpio31", "gpio52", "gpio68", "gpio69", +}; +static const char * const qlink_enable_groups[] = { + "gpio100", +}; +static const char * const qlink_request_groups[] = { + "gpio99", +}; +static const char * const qspi_clk_groups[] = { + "gpio47", +}; +static const char * const qspi_cs_groups[] = { + "gpio43", "gpio50", +}; +static const char * const qspi_data0_groups[] = { + "gpio33", +}; +static const char * const qspi_data1_groups[] = { + "gpio34", +}; +static const char * const qspi_data2_groups[] = { + "gpio35", +}; +static const char * const qspi_data3_groups[] = { + "gpio51", +}; +static const char * const qspi_resetn_groups[] = { + "gpio48", +}; +static const char * const sec_mi2s_groups[] = { + "gpio24", "gpio25", "gpio26", "gpio27", "gpio62", +}; +static const char * const sndwire_clk_groups[] = { + "gpio24", +}; +static const char * const sndwire_data_groups[] = { + "gpio25", +}; +static const char * const sp_cmu_groups[] = { + "gpio64", +}; +static const char * const ssc_irq_groups[] = { + "gpio67", "gpio68", "gpio69", "gpio70", "gpio71", "gpio72", "gpio74", + "gpio75", "gpio76", +}; +static const char * const tgu_ch0_groups[] = { + "gpio0", +}; +static const char * const tgu_ch1_groups[] = { + "gpio1", +}; +static const char * const tsense_pwm1_groups[] = { + "gpio71", +}; +static const char * const tsense_pwm2_groups[] = { + "gpio71", +}; +static const char * const uim1_clk_groups[] = { + "gpio88", +}; +static const char * const uim1_data_groups[] = { + "gpio87", +}; +static const char * const uim1_present_groups[] = { + "gpio90", +}; +static const char * const uim1_reset_groups[] = { + "gpio89", +}; +static const char * const uim2_clk_groups[] = { + "gpio84", +}; +static const char * const uim2_data_groups[] = { + "gpio83", +}; +static const char * const uim2_present_groups[] = { + "gpio86", +}; +static const char * const uim2_reset_groups[] = { + "gpio85", +}; +static const char * const uim_batt_groups[] = { + "gpio91", +}; +static const char * const vfr_1_groups[] = { + "gpio27", +}; +static const char * const vsense_clkout_groups[] = { + "gpio24", +}; +static const char * const vsense_data0_groups[] = { + "gpio21", +}; +static const char * const vsense_data1_groups[] = { + "gpio22", +}; +static const char * const vsense_mode_groups[] = { + "gpio23", +}; +static const char * const wlan1_adc0_groups[] = { + "gpio9", +}; +static const char * const wlan1_adc1_groups[] = { + "gpio8", +}; +static const char * const wlan2_adc0_groups[] = { + "gpio11", +}; +static const char * const wlan2_adc1_groups[] = { + "gpio10", +}; + +static const struct pinfunction sdm660_functions[] = { + MSM_PIN_FUNCTION(adsp_ext), + MSM_PIN_FUNCTION(agera_pll), + MSM_PIN_FUNCTION(atest_char), + MSM_PIN_FUNCTION(atest_char0), + MSM_PIN_FUNCTION(atest_char1), + MSM_PIN_FUNCTION(atest_char2), + MSM_PIN_FUNCTION(atest_char3), + MSM_PIN_FUNCTION(atest_gpsadc0), + MSM_PIN_FUNCTION(atest_gpsadc1), + MSM_PIN_FUNCTION(atest_tsens), + MSM_PIN_FUNCTION(atest_tsens2), + MSM_PIN_FUNCTION(atest_usb1), + MSM_PIN_FUNCTION(atest_usb10), + MSM_PIN_FUNCTION(atest_usb11), + MSM_PIN_FUNCTION(atest_usb12), + MSM_PIN_FUNCTION(atest_usb13), + MSM_PIN_FUNCTION(atest_usb2), + MSM_PIN_FUNCTION(atest_usb20), + MSM_PIN_FUNCTION(atest_usb21), + MSM_PIN_FUNCTION(atest_usb22), + MSM_PIN_FUNCTION(atest_usb23), + MSM_PIN_FUNCTION(audio_ref), + MSM_PIN_FUNCTION(bimc_dte0), + MSM_PIN_FUNCTION(bimc_dte1), + MSM_PIN_FUNCTION(blsp_i2c1), + MSM_PIN_FUNCTION(blsp_i2c2), + MSM_PIN_FUNCTION(blsp_i2c3), + MSM_PIN_FUNCTION(blsp_i2c4), + MSM_PIN_FUNCTION(blsp_i2c5), + MSM_PIN_FUNCTION(blsp_i2c6), + MSM_PIN_FUNCTION(blsp_i2c7), + MSM_PIN_FUNCTION(blsp_i2c8_a), + MSM_PIN_FUNCTION(blsp_i2c8_b), + MSM_PIN_FUNCTION(blsp_spi1), + MSM_PIN_FUNCTION(blsp_spi2), + MSM_PIN_FUNCTION(blsp_spi3), + MSM_PIN_FUNCTION(blsp_spi3_cs1), + MSM_PIN_FUNCTION(blsp_spi3_cs2), + MSM_PIN_FUNCTION(blsp_spi4), + MSM_PIN_FUNCTION(blsp_spi5), + MSM_PIN_FUNCTION(blsp_spi6), + MSM_PIN_FUNCTION(blsp_spi7), + MSM_PIN_FUNCTION(blsp_spi8_a), + MSM_PIN_FUNCTION(blsp_spi8_b), + MSM_PIN_FUNCTION(blsp_spi8_cs1), + MSM_PIN_FUNCTION(blsp_spi8_cs2), + MSM_PIN_FUNCTION(blsp_uart1), + MSM_PIN_FUNCTION(blsp_uart2), + MSM_PIN_FUNCTION(blsp_uart5), + MSM_PIN_FUNCTION(blsp_uart6_a), + MSM_PIN_FUNCTION(blsp_uart6_b), + MSM_PIN_FUNCTION(blsp_uim1), + MSM_PIN_FUNCTION(blsp_uim2), + MSM_PIN_FUNCTION(blsp_uim5), + MSM_PIN_FUNCTION(blsp_uim6), + MSM_PIN_FUNCTION(cam_mclk), + MSM_PIN_FUNCTION(cci_async), + MSM_PIN_FUNCTION(cci_i2c), + MSM_PIN_FUNCTION(cri_trng), + MSM_PIN_FUNCTION(cri_trng0), + MSM_PIN_FUNCTION(cri_trng1), + MSM_PIN_FUNCTION(dbg_out), + MSM_PIN_FUNCTION(ddr_bist), + MSM_PIN_FUNCTION(gcc_gp1), + MSM_PIN_FUNCTION(gcc_gp2), + MSM_PIN_FUNCTION(gcc_gp3), + MSM_PIN_FUNCTION(gpio), + MSM_PIN_FUNCTION(gps_tx_a), + MSM_PIN_FUNCTION(gps_tx_b), + MSM_PIN_FUNCTION(gps_tx_c), + MSM_PIN_FUNCTION(isense_dbg), + MSM_PIN_FUNCTION(jitter_bist), + MSM_PIN_FUNCTION(ldo_en), + MSM_PIN_FUNCTION(ldo_update), + MSM_PIN_FUNCTION(m_voc), + MSM_PIN_FUNCTION(mdp_vsync), + MSM_PIN_FUNCTION(mdss_vsync0), + MSM_PIN_FUNCTION(mdss_vsync1), + MSM_PIN_FUNCTION(mdss_vsync2), + MSM_PIN_FUNCTION(mdss_vsync3), + MSM_PIN_FUNCTION(mss_lte), + MSM_PIN_FUNCTION(nav_pps_a), + MSM_PIN_FUNCTION(nav_pps_b), + MSM_PIN_FUNCTION(nav_pps_c), + MSM_PIN_FUNCTION(pa_indicator), + MSM_PIN_FUNCTION(phase_flag0), + MSM_PIN_FUNCTION(phase_flag1), + MSM_PIN_FUNCTION(phase_flag2), + MSM_PIN_FUNCTION(phase_flag3), + MSM_PIN_FUNCTION(phase_flag4), + MSM_PIN_FUNCTION(phase_flag5), + MSM_PIN_FUNCTION(phase_flag6), + MSM_PIN_FUNCTION(phase_flag7), + MSM_PIN_FUNCTION(phase_flag8), + MSM_PIN_FUNCTION(phase_flag9), + MSM_PIN_FUNCTION(phase_flag10), + MSM_PIN_FUNCTION(phase_flag11), + MSM_PIN_FUNCTION(phase_flag12), + MSM_PIN_FUNCTION(phase_flag13), + MSM_PIN_FUNCTION(phase_flag14), + MSM_PIN_FUNCTION(phase_flag15), + MSM_PIN_FUNCTION(phase_flag16), + MSM_PIN_FUNCTION(phase_flag17), + MSM_PIN_FUNCTION(phase_flag18), + MSM_PIN_FUNCTION(phase_flag19), + MSM_PIN_FUNCTION(phase_flag20), + MSM_PIN_FUNCTION(phase_flag21), + MSM_PIN_FUNCTION(phase_flag22), + MSM_PIN_FUNCTION(phase_flag23), + MSM_PIN_FUNCTION(phase_flag24), + MSM_PIN_FUNCTION(phase_flag25), + MSM_PIN_FUNCTION(phase_flag26), + MSM_PIN_FUNCTION(phase_flag27), + MSM_PIN_FUNCTION(phase_flag28), + MSM_PIN_FUNCTION(phase_flag29), + MSM_PIN_FUNCTION(phase_flag30), + MSM_PIN_FUNCTION(phase_flag31), + MSM_PIN_FUNCTION(pll_bypassnl), + MSM_PIN_FUNCTION(pll_reset), + MSM_PIN_FUNCTION(pri_mi2s), + MSM_PIN_FUNCTION(pri_mi2s_ws), + MSM_PIN_FUNCTION(prng_rosc), + MSM_PIN_FUNCTION(pwr_crypto), + MSM_PIN_FUNCTION(pwr_modem), + MSM_PIN_FUNCTION(pwr_nav), + MSM_PIN_FUNCTION(qdss_cti0_a), + MSM_PIN_FUNCTION(qdss_cti0_b), + MSM_PIN_FUNCTION(qdss_cti1_a), + MSM_PIN_FUNCTION(qdss_cti1_b), + MSM_PIN_FUNCTION(qdss_gpio), + MSM_PIN_FUNCTION(qdss_gpio0), + MSM_PIN_FUNCTION(qdss_gpio1), + MSM_PIN_FUNCTION(qdss_gpio10), + MSM_PIN_FUNCTION(qdss_gpio11), + MSM_PIN_FUNCTION(qdss_gpio12), + MSM_PIN_FUNCTION(qdss_gpio13), + MSM_PIN_FUNCTION(qdss_gpio14), + MSM_PIN_FUNCTION(qdss_gpio15), + MSM_PIN_FUNCTION(qdss_gpio2), + MSM_PIN_FUNCTION(qdss_gpio3), + MSM_PIN_FUNCTION(qdss_gpio4), + MSM_PIN_FUNCTION(qdss_gpio5), + MSM_PIN_FUNCTION(qdss_gpio6), + MSM_PIN_FUNCTION(qdss_gpio7), + MSM_PIN_FUNCTION(qdss_gpio8), + MSM_PIN_FUNCTION(qdss_gpio9), + MSM_PIN_FUNCTION(qlink_enable), + MSM_PIN_FUNCTION(qlink_request), + MSM_PIN_FUNCTION(qspi_clk), + MSM_PIN_FUNCTION(qspi_cs), + MSM_PIN_FUNCTION(qspi_data0), + MSM_PIN_FUNCTION(qspi_data1), + MSM_PIN_FUNCTION(qspi_data2), + MSM_PIN_FUNCTION(qspi_data3), + MSM_PIN_FUNCTION(qspi_resetn), + MSM_PIN_FUNCTION(sec_mi2s), + MSM_PIN_FUNCTION(sndwire_clk), + MSM_PIN_FUNCTION(sndwire_data), + MSM_PIN_FUNCTION(sp_cmu), + MSM_PIN_FUNCTION(ssc_irq), + MSM_PIN_FUNCTION(tgu_ch0), + MSM_PIN_FUNCTION(tgu_ch1), + MSM_PIN_FUNCTION(tsense_pwm1), + MSM_PIN_FUNCTION(tsense_pwm2), + MSM_PIN_FUNCTION(uim1_clk), + MSM_PIN_FUNCTION(uim1_data), + MSM_PIN_FUNCTION(uim1_present), + MSM_PIN_FUNCTION(uim1_reset), + MSM_PIN_FUNCTION(uim2_clk), + MSM_PIN_FUNCTION(uim2_data), + MSM_PIN_FUNCTION(uim2_present), + MSM_PIN_FUNCTION(uim2_reset), + MSM_PIN_FUNCTION(uim_batt), + MSM_PIN_FUNCTION(vfr_1), + MSM_PIN_FUNCTION(vsense_clkout), + MSM_PIN_FUNCTION(vsense_data0), + MSM_PIN_FUNCTION(vsense_data1), + MSM_PIN_FUNCTION(vsense_mode), + MSM_PIN_FUNCTION(wlan1_adc0), + MSM_PIN_FUNCTION(wlan1_adc1), + MSM_PIN_FUNCTION(wlan2_adc0), + MSM_PIN_FUNCTION(wlan2_adc1), +}; + +static const struct msm_pingroup sdm660_groups[] = { + PINGROUP(0, SOUTH, blsp_spi1, blsp_uart1, blsp_uim1, tgu_ch0, _, _, qdss_gpio4, atest_gpsadc1, _), + PINGROUP(1, SOUTH, blsp_spi1, blsp_uart1, blsp_uim1, tgu_ch1, _, _, qdss_gpio5, atest_gpsadc0, _), + PINGROUP(2, SOUTH, blsp_spi1, blsp_uart1, blsp_i2c1, _, _, _, _, _, _), + PINGROUP(3, SOUTH, blsp_spi1, blsp_uart1, blsp_i2c1, ddr_bist, _, _, atest_tsens2, atest_usb1, _), + PINGROUP(4, NORTH, blsp_spi2, blsp_uim2, blsp_uart2, phase_flag3, _, _, _, _, _), + PINGROUP(5, SOUTH, blsp_spi2, blsp_uim2, blsp_uart2, phase_flag14, _, _, _, _, _), + PINGROUP(6, SOUTH, blsp_spi2, blsp_i2c2, blsp_uart2, phase_flag31, _, _, _, _, _), + PINGROUP(7, SOUTH, blsp_spi2, blsp_i2c2, blsp_uart2, _, _, _, _, _, _), + PINGROUP(8, NORTH, blsp_spi3, ddr_bist, _, _, _, wlan1_adc1, atest_usb13, bimc_dte1, _), + PINGROUP(9, NORTH, blsp_spi3, ddr_bist, _, _, _, wlan1_adc0, atest_usb12, bimc_dte0, _), + PINGROUP(10, NORTH, blsp_spi3, blsp_i2c3, ddr_bist, _, _, wlan2_adc1, atest_usb11, bimc_dte1, _), + PINGROUP(11, NORTH, blsp_spi3, blsp_i2c3, _, dbg_out, wlan2_adc0, atest_usb10, bimc_dte0, _, _), + PINGROUP(12, NORTH, blsp_spi4, pri_mi2s, _, phase_flag26, qdss_cti1_b, _, _, _, _), + PINGROUP(13, NORTH, blsp_spi4, _, pri_mi2s_ws, _, _, phase_flag27, qdss_cti0_b, _, _), + PINGROUP(14, NORTH, blsp_spi4, blsp_i2c4, pri_mi2s, _, phase_flag28, _, _, _, _), + PINGROUP(15, NORTH, blsp_spi4, blsp_i2c4, pri_mi2s, _, _, _, _, _, _), + PINGROUP(16, CENTER, blsp_uart5, blsp_spi5, blsp_uim5, _, _, _, _, _, _), + PINGROUP(17, CENTER, blsp_uart5, blsp_spi5, blsp_uim5, _, phase_flag5, _, _, _, _), + PINGROUP(18, CENTER, blsp_uart5, blsp_spi5, blsp_i2c5, _, _, _, _, _, _), + PINGROUP(19, CENTER, blsp_uart5, blsp_spi5, blsp_i2c5, _, _, _, _, _, _), + PINGROUP(20, SOUTH, _, _, blsp_uim6, _, _, _, _, _, _), + PINGROUP(21, SOUTH, _, _, blsp_uim6, _, phase_flag11, qdss_cti0_b, vsense_data0, _, _), + PINGROUP(22, CENTER, blsp_spi6, _, blsp_i2c6, _, phase_flag12, vsense_data1, _, _, _), + PINGROUP(23, CENTER, blsp_spi6, _, blsp_i2c6, _, phase_flag13, vsense_mode, _, _, _), + PINGROUP(24, NORTH, blsp_spi7, blsp_uart6_a, sec_mi2s, sndwire_clk, _, _, phase_flag17, vsense_clkout, _), + PINGROUP(25, NORTH, blsp_spi7, blsp_uart6_a, sec_mi2s, sndwire_data, _, _, phase_flag18, _, _), + PINGROUP(26, NORTH, blsp_spi7, blsp_uart6_a, blsp_i2c7, sec_mi2s, _, phase_flag19, _, _, _), + PINGROUP(27, NORTH, blsp_spi7, blsp_uart6_a, blsp_i2c7, vfr_1, sec_mi2s, _, phase_flag20, _, _), + PINGROUP(28, CENTER, blsp_spi8_a, blsp_uart6_b, m_voc, _, phase_flag21, _, _, _, _), + PINGROUP(29, CENTER, blsp_spi8_a, blsp_uart6_b, _, _, phase_flag22, _, _, _, _), + PINGROUP(30, CENTER, blsp_spi8_a, blsp_uart6_b, blsp_i2c8_a, blsp_spi3_cs1, _, phase_flag23, _, _, _), + PINGROUP(31, CENTER, blsp_spi8_a, blsp_uart6_b, blsp_i2c8_a, pwr_modem, _, phase_flag24, qdss_gpio, _, _), + PINGROUP(32, SOUTH, cam_mclk, pwr_nav, _, _, qdss_gpio0, _, _, _, _), + PINGROUP(33, SOUTH, cam_mclk, qspi_data0, pwr_crypto, _, _, qdss_gpio1, _, _, _), + PINGROUP(34, SOUTH, cam_mclk, qspi_data1, agera_pll, _, _, qdss_gpio2, _, _, _), + PINGROUP(35, SOUTH, cam_mclk, qspi_data2, jitter_bist, _, _, qdss_gpio3, _, atest_usb2, _), + PINGROUP(36, SOUTH, cci_i2c, pll_bypassnl, agera_pll, _, _, qdss_gpio4, atest_tsens, atest_usb21, _), + PINGROUP(37, SOUTH, cci_i2c, pll_reset, _, _, qdss_gpio5, atest_usb23, _, _, _), + PINGROUP(38, SOUTH, cci_i2c, _, _, qdss_gpio6, _, _, _, _, _), + PINGROUP(39, SOUTH, cci_i2c, _, _, qdss_gpio7, _, _, _, _, _), + PINGROUP(40, SOUTH, _, _, blsp_spi8_b, _, _, _, _, _, _), + PINGROUP(41, SOUTH, _, _, blsp_spi8_b, _, _, _, _, _, _), + PINGROUP(42, SOUTH, mdss_vsync0, mdss_vsync1, mdss_vsync2, mdss_vsync3, _, _, qdss_gpio9, _, _), + PINGROUP(43, SOUTH, _, _, qspi_cs, _, _, qdss_gpio10, _, _, _), + PINGROUP(44, SOUTH, _, _, blsp_spi8_b, blsp_i2c8_b, _, _, qdss_gpio11, _, _), + PINGROUP(45, SOUTH, cci_async, _, _, qdss_gpio12, _, _, _, _, _), + PINGROUP(46, SOUTH, blsp_spi1, _, _, qdss_gpio13, _, _, _, _, _), + PINGROUP(47, SOUTH, qspi_clk, _, phase_flag30, qdss_gpio14, _, _, _, _, _), + PINGROUP(48, SOUTH, _, phase_flag1, qdss_gpio15, _, _, _, _, _, _), + PINGROUP(49, SOUTH, blsp_spi6, phase_flag2, qdss_cti0_a, _, _, _, _, _, _), + PINGROUP(50, SOUTH, qspi_cs, _, phase_flag9, qdss_cti0_a, _, _, _, _, _), + PINGROUP(51, SOUTH, qspi_data3, _, phase_flag15, qdss_gpio8, _, _, _, _, _), + PINGROUP(52, SOUTH, _, blsp_spi8_b, blsp_i2c8_b, blsp_spi6, phase_flag16, qdss_gpio, _, _, _), + PINGROUP(53, NORTH, _, phase_flag6, qdss_cti1_a, _, _, _, _, _, _), + PINGROUP(54, NORTH, _, _, phase_flag29, _, _, _, _, _, _), + PINGROUP(55, SOUTH, _, phase_flag25, qdss_cti1_a, _, _, _, _, _, _), + PINGROUP(56, SOUTH, _, phase_flag10, qdss_gpio3, _, atest_usb20, _, _, _, _), + PINGROUP(57, SOUTH, gcc_gp1, _, phase_flag4, atest_usb22, _, _, _, _, _), + PINGROUP(58, SOUTH, _, gcc_gp2, _, _, atest_char, _, _, _, _), + PINGROUP(59, NORTH, mdp_vsync, gcc_gp3, _, _, atest_char3, _, _, _, _), + PINGROUP(60, NORTH, cri_trng0, _, _, atest_char2, _, _, _, _, _), + PINGROUP(61, NORTH, pri_mi2s, cri_trng1, _, _, atest_char1, _, _, _, _), + PINGROUP(62, NORTH, sec_mi2s, audio_ref, _, cri_trng, _, _, atest_char0, _, _), + PINGROUP(63, NORTH, _, _, _, qdss_gpio1, _, _, _, _, _), + PINGROUP(64, SOUTH, blsp_spi8_cs1, sp_cmu, _, _, qdss_gpio2, _, _, _, _), + PINGROUP(65, SOUTH, _, nav_pps_a, nav_pps_a, gps_tx_a, blsp_spi3_cs2, adsp_ext, _, _, _), + PINGROUP(66, NORTH, _, _, qdss_cti1_b, _, _, _, _, _, _), + PINGROUP(67, NORTH, _, _, qdss_gpio0, _, _, _, _, _, _), + PINGROUP(68, NORTH, isense_dbg, _, phase_flag0, qdss_gpio, _, _, _, _, _), + PINGROUP(69, NORTH, _, phase_flag7, qdss_gpio, _, _, _, _, _, _), + PINGROUP(70, NORTH, _, phase_flag8, qdss_gpio6, _, _, _, _, _, _), + PINGROUP(71, NORTH, _, _, qdss_gpio7, tsense_pwm1, tsense_pwm2, _, _, _, _), + PINGROUP(72, NORTH, _, qdss_gpio14, _, _, _, _, _, _, _), + PINGROUP(73, NORTH, _, _, qdss_gpio15, _, _, _, _, _, _), + PINGROUP(74, NORTH, mdp_vsync, _, _, _, _, _, _, _, _), + PINGROUP(75, NORTH, _, _, qdss_gpio8, _, _, _, _, _, _), + PINGROUP(76, NORTH, blsp_spi8_cs2, _, _, _, qdss_gpio9, _, _, _, _), + PINGROUP(77, NORTH, _, _, qdss_gpio10, _, _, _, _, _, _), + PINGROUP(78, NORTH, gcc_gp1, _, qdss_gpio13, _, _, _, _, _, _), + PINGROUP(79, SOUTH, _, _, qdss_gpio11, _, _, _, _, _, _), + PINGROUP(80, SOUTH, nav_pps_b, nav_pps_b, gps_tx_c, _, _, qdss_gpio12, _, _, _), + PINGROUP(81, CENTER, mss_lte, gcc_gp2, _, _, _, _, _, _, _), + PINGROUP(82, CENTER, mss_lte, gcc_gp3, _, _, _, _, _, _, _), + PINGROUP(83, SOUTH, uim2_data, _, _, _, _, _, _, _, _), + PINGROUP(84, SOUTH, uim2_clk, _, _, _, _, _, _, _, _), + PINGROUP(85, SOUTH, uim2_reset, _, _, _, _, _, _, _, _), + PINGROUP(86, SOUTH, uim2_present, _, _, _, _, _, _, _, _), + PINGROUP(87, SOUTH, uim1_data, _, _, _, _, _, _, _, _), + PINGROUP(88, SOUTH, uim1_clk, _, _, _, _, _, _, _, _), + PINGROUP(89, SOUTH, uim1_reset, _, _, _, _, _, _, _, _), + PINGROUP(90, SOUTH, uim1_present, _, _, _, _, _, _, _, _), + PINGROUP(91, SOUTH, uim_batt, _, _, _, _, _, _, _, _), + PINGROUP(92, SOUTH, _, _, pa_indicator, _, _, _, _, _, _), + PINGROUP(93, SOUTH, _, _, _, _, _, _, _, _, _), + PINGROUP(94, SOUTH, _, _, _, _, _, _, _, _, _), + PINGROUP(95, SOUTH, _, _, _, _, _, _, _, _, _), + PINGROUP(96, SOUTH, _, _, _, _, _, _, _, _, _), + PINGROUP(97, SOUTH, _, ldo_en, _, _, _, _, _, _, _), + PINGROUP(98, SOUTH, _, nav_pps_c, nav_pps_c, gps_tx_b, ldo_update, _, _, _, _), + PINGROUP(99, SOUTH, qlink_request, _, _, _, _, _, _, _, _), + PINGROUP(100, SOUTH, qlink_enable, _, _, _, _, _, _, _, _), + PINGROUP(101, SOUTH, _, _, _, _, _, _, _, _, _), + PINGROUP(102, SOUTH, _, prng_rosc, _, _, _, _, _, _, _), + PINGROUP(103, SOUTH, _, _, _, _, _, _, _, _, _), + PINGROUP(104, SOUTH, _, _, _, _, _, _, _, _, _), + PINGROUP(105, SOUTH, _, _, _, _, _, _, _, _, _), + PINGROUP(106, SOUTH, _, _, _, _, _, _, _, _, _), + PINGROUP(107, SOUTH, _, _, _, _, _, _, _, _, _), + PINGROUP(108, SOUTH, _, _, _, _, _, _, _, _, _), + PINGROUP(109, SOUTH, _, _, _, _, _, _, _, _, _), + PINGROUP(110, SOUTH, _, _, _, _, _, _, _, _, _), + PINGROUP(111, SOUTH, _, _, _, _, _, _, _, _, _), + PINGROUP(112, SOUTH, _, _, _, _, _, _, _, _, _), + PINGROUP(113, SOUTH, _, _, _, _, _, _, _, _, _), + SDC_QDSD_PINGROUP(sdc1_clk, 0x9a000, 13, 6), + SDC_QDSD_PINGROUP(sdc1_cmd, 0x9a000, 11, 3), + SDC_QDSD_PINGROUP(sdc1_data, 0x9a000, 9, 0), + SDC_QDSD_PINGROUP(sdc2_clk, 0x9b000, 14, 6), + SDC_QDSD_PINGROUP(sdc2_cmd, 0x9b000, 11, 3), + SDC_QDSD_PINGROUP(sdc2_data, 0x9b000, 9, 0), + SDC_QDSD_PINGROUP(sdc1_rclk, 0x9a000, 15, 0), +}; + +static const struct msm_pinctrl_soc_data sdm660_pinctrl = { + .pins = sdm660_pins, + .npins = ARRAY_SIZE(sdm660_pins), + .functions = sdm660_functions, + .nfunctions = ARRAY_SIZE(sdm660_functions), + .groups = sdm660_groups, + .ngroups = ARRAY_SIZE(sdm660_groups), + .ngpios = 114, + .tiles = sdm660_tiles, + .ntiles = ARRAY_SIZE(sdm660_tiles), +}; + +static int sdm660_pinctrl_probe(struct platform_device *pdev) +{ + return msm_pinctrl_probe(pdev, &sdm660_pinctrl); +} + +static const struct of_device_id sdm660_pinctrl_of_match[] = { + { .compatible = "qcom,sdm660-pinctrl", }, + { .compatible = "qcom,sdm630-pinctrl", }, + { }, +}; + +static struct platform_driver sdm660_pinctrl_driver = { + .driver = { + .name = "sdm660-pinctrl", + .of_match_table = sdm660_pinctrl_of_match, + }, + .probe = sdm660_pinctrl_probe, + .remove = msm_pinctrl_remove, +}; + +static int __init sdm660_pinctrl_init(void) +{ + return platform_driver_register(&sdm660_pinctrl_driver); +} +arch_initcall(sdm660_pinctrl_init); + +static void __exit sdm660_pinctrl_exit(void) +{ + platform_driver_unregister(&sdm660_pinctrl_driver); +} +module_exit(sdm660_pinctrl_exit); + +MODULE_DESCRIPTION("QTI sdm660 pinctrl driver"); +MODULE_LICENSE("GPL v2"); +MODULE_DEVICE_TABLE(of, sdm660_pinctrl_of_match); diff --git a/drivers/pinctrl/qcom/pinctrl-sdm670.c b/drivers/pinctrl/qcom/pinctrl-sdm670.c new file mode 100644 index 0000000000..cc3cce077d --- /dev/null +++ b/drivers/pinctrl/qcom/pinctrl-sdm670.c @@ -0,0 +1,1337 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2017-2018, The Linux Foundation. All rights reserved. + * Copyright (c) 2022, Richard Acayan. All rights reserved. + */ + +#include <linux/module.h> +#include <linux/of.h> +#include <linux/platform_device.h> + +#include "pinctrl-msm.h" + +#define NORTH 0x00500000 +#define SOUTH 0x00900000 +#define WEST 0x00100000 + +#define REG_SIZE 0x1000 +#define PINGROUP(id, base, f1, f2, f3, f4, f5, f6, f7, f8, f9) \ + { \ + .grp = PINCTRL_PINGROUP("gpio" #id, \ + gpio##id##_pins, \ + ARRAY_SIZE(gpio##id##_pins)), \ + .funcs = (int[]){ \ + msm_mux_gpio, /* gpio mode */ \ + msm_mux_##f1, \ + msm_mux_##f2, \ + msm_mux_##f3, \ + msm_mux_##f4, \ + msm_mux_##f5, \ + msm_mux_##f6, \ + msm_mux_##f7, \ + msm_mux_##f8, \ + msm_mux_##f9 \ + }, \ + .nfuncs = 10, \ + .ctl_reg = base + REG_SIZE * id, \ + .io_reg = base + 0x4 + REG_SIZE * id, \ + .intr_cfg_reg = base + 0x8 + REG_SIZE * id, \ + .intr_status_reg = base + 0xc + REG_SIZE * id, \ + .intr_target_reg = base + 0x8 + REG_SIZE * id, \ + .mux_bit = 2, \ + .pull_bit = 0, \ + .drv_bit = 6, \ + .oe_bit = 9, \ + .in_bit = 0, \ + .out_bit = 1, \ + .intr_enable_bit = 0, \ + .intr_status_bit = 0, \ + .intr_target_bit = 5, \ + .intr_target_kpss_val = 3, \ + .intr_raw_status_bit = 4, \ + .intr_polarity_bit = 1, \ + .intr_detection_bit = 2, \ + .intr_detection_width = 2, \ + } + +/* + * A dummy pingroup is a pin group that cannot be assigned a function and has + * no registers to control or monitor it. + */ +#define PINGROUP_DUMMY(id) \ + { \ + .grp = PINCTRL_PINGROUP("gpio" #id, \ + gpio##id##_pins, \ + ARRAY_SIZE(gpio##id##_pins)), \ + .ctl_reg = 0, \ + .io_reg = 0, \ + .intr_cfg_reg = 0, \ + .intr_status_reg = 0, \ + .intr_target_reg = 0, \ + .mux_bit = -1, \ + .pull_bit = -1, \ + .drv_bit = -1, \ + .oe_bit = -1, \ + .in_bit = -1, \ + .out_bit = -1, \ + .intr_enable_bit = -1, \ + .intr_status_bit = -1, \ + .intr_target_bit = -1, \ + .intr_raw_status_bit = -1, \ + .intr_polarity_bit = -1, \ + .intr_detection_bit = -1, \ + .intr_detection_width = -1, \ + } + +#define SDC_QDSD_PINGROUP(pg_name, ctl, pull, drv) \ + { \ + .grp = PINCTRL_PINGROUP(#pg_name, \ + pg_name##_pins, \ + ARRAY_SIZE(pg_name##_pins)), \ + .ctl_reg = ctl, \ + .io_reg = 0, \ + .intr_cfg_reg = 0, \ + .intr_status_reg = 0, \ + .intr_target_reg = 0, \ + .mux_bit = -1, \ + .pull_bit = pull, \ + .drv_bit = drv, \ + .oe_bit = -1, \ + .in_bit = -1, \ + .out_bit = -1, \ + .intr_enable_bit = -1, \ + .intr_status_bit = -1, \ + .intr_target_bit = -1, \ + .intr_raw_status_bit = -1, \ + .intr_polarity_bit = -1, \ + .intr_detection_bit = -1, \ + .intr_detection_width = -1, \ + } + +#define UFS_RESET(pg_name, offset) \ + { \ + .grp = PINCTRL_PINGROUP(#pg_name, \ + pg_name##_pins, \ + ARRAY_SIZE(pg_name##_pins)), \ + .ctl_reg = offset, \ + .io_reg = offset + 0x4, \ + .intr_cfg_reg = 0, \ + .intr_status_reg = 0, \ + .intr_target_reg = 0, \ + .mux_bit = -1, \ + .pull_bit = 3, \ + .drv_bit = 0, \ + .oe_bit = -1, \ + .in_bit = -1, \ + .out_bit = 0, \ + .intr_enable_bit = -1, \ + .intr_status_bit = -1, \ + .intr_target_bit = -1, \ + .intr_raw_status_bit = -1, \ + .intr_polarity_bit = -1, \ + .intr_detection_bit = -1, \ + .intr_detection_width = -1, \ + } + +static const struct pinctrl_pin_desc sdm670_pins[] = { + PINCTRL_PIN(0, "GPIO_0"), + PINCTRL_PIN(1, "GPIO_1"), + PINCTRL_PIN(2, "GPIO_2"), + PINCTRL_PIN(3, "GPIO_3"), + PINCTRL_PIN(4, "GPIO_4"), + PINCTRL_PIN(5, "GPIO_5"), + PINCTRL_PIN(6, "GPIO_6"), + PINCTRL_PIN(7, "GPIO_7"), + PINCTRL_PIN(8, "GPIO_8"), + PINCTRL_PIN(9, "GPIO_9"), + PINCTRL_PIN(10, "GPIO_10"), + PINCTRL_PIN(11, "GPIO_11"), + PINCTRL_PIN(12, "GPIO_12"), + PINCTRL_PIN(13, "GPIO_13"), + PINCTRL_PIN(14, "GPIO_14"), + PINCTRL_PIN(15, "GPIO_15"), + PINCTRL_PIN(16, "GPIO_16"), + PINCTRL_PIN(17, "GPIO_17"), + PINCTRL_PIN(18, "GPIO_18"), + PINCTRL_PIN(19, "GPIO_19"), + PINCTRL_PIN(20, "GPIO_20"), + PINCTRL_PIN(21, "GPIO_21"), + PINCTRL_PIN(22, "GPIO_22"), + PINCTRL_PIN(23, "GPIO_23"), + PINCTRL_PIN(24, "GPIO_24"), + PINCTRL_PIN(25, "GPIO_25"), + PINCTRL_PIN(26, "GPIO_26"), + PINCTRL_PIN(27, "GPIO_27"), + PINCTRL_PIN(28, "GPIO_28"), + PINCTRL_PIN(29, "GPIO_29"), + PINCTRL_PIN(30, "GPIO_30"), + PINCTRL_PIN(31, "GPIO_31"), + PINCTRL_PIN(32, "GPIO_32"), + PINCTRL_PIN(33, "GPIO_33"), + PINCTRL_PIN(34, "GPIO_34"), + PINCTRL_PIN(35, "GPIO_35"), + PINCTRL_PIN(36, "GPIO_36"), + PINCTRL_PIN(37, "GPIO_37"), + PINCTRL_PIN(38, "GPIO_38"), + PINCTRL_PIN(39, "GPIO_39"), + PINCTRL_PIN(40, "GPIO_40"), + PINCTRL_PIN(41, "GPIO_41"), + PINCTRL_PIN(42, "GPIO_42"), + PINCTRL_PIN(43, "GPIO_43"), + PINCTRL_PIN(44, "GPIO_44"), + PINCTRL_PIN(45, "GPIO_45"), + PINCTRL_PIN(46, "GPIO_46"), + PINCTRL_PIN(47, "GPIO_47"), + PINCTRL_PIN(48, "GPIO_48"), + PINCTRL_PIN(49, "GPIO_49"), + PINCTRL_PIN(50, "GPIO_50"), + PINCTRL_PIN(51, "GPIO_51"), + PINCTRL_PIN(52, "GPIO_52"), + PINCTRL_PIN(53, "GPIO_53"), + PINCTRL_PIN(54, "GPIO_54"), + PINCTRL_PIN(55, "GPIO_55"), + PINCTRL_PIN(56, "GPIO_56"), + PINCTRL_PIN(57, "GPIO_57"), + PINCTRL_PIN(58, "GPIO_58"), + PINCTRL_PIN(59, "GPIO_59"), + PINCTRL_PIN(60, "GPIO_60"), + PINCTRL_PIN(61, "GPIO_61"), + PINCTRL_PIN(62, "GPIO_62"), + PINCTRL_PIN(63, "GPIO_63"), + PINCTRL_PIN(64, "GPIO_64"), + PINCTRL_PIN(65, "GPIO_65"), + PINCTRL_PIN(66, "GPIO_66"), + PINCTRL_PIN(67, "GPIO_67"), + PINCTRL_PIN(68, "GPIO_68"), + PINCTRL_PIN(69, "GPIO_69"), + PINCTRL_PIN(70, "GPIO_70"), + PINCTRL_PIN(71, "GPIO_71"), + PINCTRL_PIN(72, "GPIO_72"), + PINCTRL_PIN(73, "GPIO_73"), + PINCTRL_PIN(74, "GPIO_74"), + PINCTRL_PIN(75, "GPIO_75"), + PINCTRL_PIN(76, "GPIO_76"), + PINCTRL_PIN(77, "GPIO_77"), + PINCTRL_PIN(78, "GPIO_78"), + PINCTRL_PIN(79, "GPIO_79"), + PINCTRL_PIN(80, "GPIO_80"), + PINCTRL_PIN(81, "GPIO_81"), + PINCTRL_PIN(82, "GPIO_82"), + PINCTRL_PIN(83, "GPIO_83"), + PINCTRL_PIN(84, "GPIO_84"), + PINCTRL_PIN(85, "GPIO_85"), + PINCTRL_PIN(86, "GPIO_86"), + PINCTRL_PIN(87, "GPIO_87"), + PINCTRL_PIN(88, "GPIO_88"), + PINCTRL_PIN(89, "GPIO_89"), + PINCTRL_PIN(90, "GPIO_90"), + PINCTRL_PIN(91, "GPIO_91"), + PINCTRL_PIN(92, "GPIO_92"), + PINCTRL_PIN(93, "GPIO_93"), + PINCTRL_PIN(94, "GPIO_94"), + PINCTRL_PIN(95, "GPIO_95"), + PINCTRL_PIN(96, "GPIO_96"), + PINCTRL_PIN(97, "GPIO_97"), + PINCTRL_PIN(98, "GPIO_98"), + PINCTRL_PIN(99, "GPIO_99"), + PINCTRL_PIN(100, "GPIO_100"), + PINCTRL_PIN(101, "GPIO_101"), + PINCTRL_PIN(102, "GPIO_102"), + PINCTRL_PIN(103, "GPIO_103"), + PINCTRL_PIN(104, "GPIO_104"), + PINCTRL_PIN(105, "GPIO_105"), + PINCTRL_PIN(106, "GPIO_106"), + PINCTRL_PIN(107, "GPIO_107"), + PINCTRL_PIN(108, "GPIO_108"), + PINCTRL_PIN(109, "GPIO_109"), + PINCTRL_PIN(110, "GPIO_110"), + PINCTRL_PIN(111, "GPIO_111"), + PINCTRL_PIN(112, "GPIO_112"), + PINCTRL_PIN(113, "GPIO_113"), + PINCTRL_PIN(114, "GPIO_114"), + PINCTRL_PIN(115, "GPIO_115"), + PINCTRL_PIN(116, "GPIO_116"), + PINCTRL_PIN(117, "GPIO_117"), + PINCTRL_PIN(118, "GPIO_118"), + PINCTRL_PIN(119, "GPIO_119"), + PINCTRL_PIN(120, "GPIO_120"), + PINCTRL_PIN(121, "GPIO_121"), + PINCTRL_PIN(122, "GPIO_122"), + PINCTRL_PIN(123, "GPIO_123"), + PINCTRL_PIN(124, "GPIO_124"), + PINCTRL_PIN(125, "GPIO_125"), + PINCTRL_PIN(126, "GPIO_126"), + PINCTRL_PIN(127, "GPIO_127"), + PINCTRL_PIN(128, "GPIO_128"), + PINCTRL_PIN(129, "GPIO_129"), + PINCTRL_PIN(130, "GPIO_130"), + PINCTRL_PIN(131, "GPIO_131"), + PINCTRL_PIN(132, "GPIO_132"), + PINCTRL_PIN(133, "GPIO_133"), + PINCTRL_PIN(134, "GPIO_134"), + PINCTRL_PIN(135, "GPIO_135"), + PINCTRL_PIN(136, "GPIO_136"), + PINCTRL_PIN(137, "GPIO_137"), + PINCTRL_PIN(138, "GPIO_138"), + PINCTRL_PIN(139, "GPIO_139"), + PINCTRL_PIN(140, "GPIO_140"), + PINCTRL_PIN(141, "GPIO_141"), + PINCTRL_PIN(142, "GPIO_142"), + PINCTRL_PIN(143, "GPIO_143"), + PINCTRL_PIN(144, "GPIO_144"), + PINCTRL_PIN(145, "GPIO_145"), + PINCTRL_PIN(146, "GPIO_146"), + PINCTRL_PIN(147, "GPIO_147"), + PINCTRL_PIN(148, "GPIO_148"), + PINCTRL_PIN(149, "GPIO_149"), + PINCTRL_PIN(150, "UFS_RESET"), + PINCTRL_PIN(151, "SDC1_RCLK"), + PINCTRL_PIN(152, "SDC1_CLK"), + PINCTRL_PIN(153, "SDC1_CMD"), + PINCTRL_PIN(154, "SDC1_DATA"), + PINCTRL_PIN(155, "SDC2_CLK"), + PINCTRL_PIN(156, "SDC2_CMD"), + PINCTRL_PIN(157, "SDC2_DATA"), +}; + +#define DECLARE_MSM_GPIO_PINS(pin) \ + static const unsigned int gpio##pin##_pins[] = { pin } +DECLARE_MSM_GPIO_PINS(0); +DECLARE_MSM_GPIO_PINS(1); +DECLARE_MSM_GPIO_PINS(2); +DECLARE_MSM_GPIO_PINS(3); +DECLARE_MSM_GPIO_PINS(4); +DECLARE_MSM_GPIO_PINS(5); +DECLARE_MSM_GPIO_PINS(6); +DECLARE_MSM_GPIO_PINS(7); +DECLARE_MSM_GPIO_PINS(8); +DECLARE_MSM_GPIO_PINS(9); +DECLARE_MSM_GPIO_PINS(10); +DECLARE_MSM_GPIO_PINS(11); +DECLARE_MSM_GPIO_PINS(12); +DECLARE_MSM_GPIO_PINS(13); +DECLARE_MSM_GPIO_PINS(14); +DECLARE_MSM_GPIO_PINS(15); +DECLARE_MSM_GPIO_PINS(16); +DECLARE_MSM_GPIO_PINS(17); +DECLARE_MSM_GPIO_PINS(18); +DECLARE_MSM_GPIO_PINS(19); +DECLARE_MSM_GPIO_PINS(20); +DECLARE_MSM_GPIO_PINS(21); +DECLARE_MSM_GPIO_PINS(22); +DECLARE_MSM_GPIO_PINS(23); +DECLARE_MSM_GPIO_PINS(24); +DECLARE_MSM_GPIO_PINS(25); +DECLARE_MSM_GPIO_PINS(26); +DECLARE_MSM_GPIO_PINS(27); +DECLARE_MSM_GPIO_PINS(28); +DECLARE_MSM_GPIO_PINS(29); +DECLARE_MSM_GPIO_PINS(30); +DECLARE_MSM_GPIO_PINS(31); +DECLARE_MSM_GPIO_PINS(32); +DECLARE_MSM_GPIO_PINS(33); +DECLARE_MSM_GPIO_PINS(34); +DECLARE_MSM_GPIO_PINS(35); +DECLARE_MSM_GPIO_PINS(36); +DECLARE_MSM_GPIO_PINS(37); +DECLARE_MSM_GPIO_PINS(38); +DECLARE_MSM_GPIO_PINS(39); +DECLARE_MSM_GPIO_PINS(40); +DECLARE_MSM_GPIO_PINS(41); +DECLARE_MSM_GPIO_PINS(42); +DECLARE_MSM_GPIO_PINS(43); +DECLARE_MSM_GPIO_PINS(44); +DECLARE_MSM_GPIO_PINS(45); +DECLARE_MSM_GPIO_PINS(46); +DECLARE_MSM_GPIO_PINS(47); +DECLARE_MSM_GPIO_PINS(48); +DECLARE_MSM_GPIO_PINS(49); +DECLARE_MSM_GPIO_PINS(50); +DECLARE_MSM_GPIO_PINS(51); +DECLARE_MSM_GPIO_PINS(52); +DECLARE_MSM_GPIO_PINS(53); +DECLARE_MSM_GPIO_PINS(54); +DECLARE_MSM_GPIO_PINS(55); +DECLARE_MSM_GPIO_PINS(56); +DECLARE_MSM_GPIO_PINS(57); +DECLARE_MSM_GPIO_PINS(58); +DECLARE_MSM_GPIO_PINS(59); +DECLARE_MSM_GPIO_PINS(60); +DECLARE_MSM_GPIO_PINS(61); +DECLARE_MSM_GPIO_PINS(62); +DECLARE_MSM_GPIO_PINS(63); +DECLARE_MSM_GPIO_PINS(64); +DECLARE_MSM_GPIO_PINS(65); +DECLARE_MSM_GPIO_PINS(66); +DECLARE_MSM_GPIO_PINS(67); +DECLARE_MSM_GPIO_PINS(68); +DECLARE_MSM_GPIO_PINS(69); +DECLARE_MSM_GPIO_PINS(70); +DECLARE_MSM_GPIO_PINS(71); +DECLARE_MSM_GPIO_PINS(72); +DECLARE_MSM_GPIO_PINS(73); +DECLARE_MSM_GPIO_PINS(74); +DECLARE_MSM_GPIO_PINS(75); +DECLARE_MSM_GPIO_PINS(76); +DECLARE_MSM_GPIO_PINS(77); +DECLARE_MSM_GPIO_PINS(78); +DECLARE_MSM_GPIO_PINS(79); +DECLARE_MSM_GPIO_PINS(80); +DECLARE_MSM_GPIO_PINS(81); +DECLARE_MSM_GPIO_PINS(82); +DECLARE_MSM_GPIO_PINS(83); +DECLARE_MSM_GPIO_PINS(84); +DECLARE_MSM_GPIO_PINS(85); +DECLARE_MSM_GPIO_PINS(86); +DECLARE_MSM_GPIO_PINS(87); +DECLARE_MSM_GPIO_PINS(88); +DECLARE_MSM_GPIO_PINS(89); +DECLARE_MSM_GPIO_PINS(90); +DECLARE_MSM_GPIO_PINS(91); +DECLARE_MSM_GPIO_PINS(92); +DECLARE_MSM_GPIO_PINS(93); +DECLARE_MSM_GPIO_PINS(94); +DECLARE_MSM_GPIO_PINS(95); +DECLARE_MSM_GPIO_PINS(96); +DECLARE_MSM_GPIO_PINS(97); +DECLARE_MSM_GPIO_PINS(98); +DECLARE_MSM_GPIO_PINS(99); +DECLARE_MSM_GPIO_PINS(100); +DECLARE_MSM_GPIO_PINS(101); +DECLARE_MSM_GPIO_PINS(102); +DECLARE_MSM_GPIO_PINS(103); +DECLARE_MSM_GPIO_PINS(104); +DECLARE_MSM_GPIO_PINS(105); +DECLARE_MSM_GPIO_PINS(106); +DECLARE_MSM_GPIO_PINS(107); +DECLARE_MSM_GPIO_PINS(108); +DECLARE_MSM_GPIO_PINS(109); +DECLARE_MSM_GPIO_PINS(110); +DECLARE_MSM_GPIO_PINS(111); +DECLARE_MSM_GPIO_PINS(112); +DECLARE_MSM_GPIO_PINS(113); +DECLARE_MSM_GPIO_PINS(114); +DECLARE_MSM_GPIO_PINS(115); +DECLARE_MSM_GPIO_PINS(116); +DECLARE_MSM_GPIO_PINS(117); +DECLARE_MSM_GPIO_PINS(118); +DECLARE_MSM_GPIO_PINS(119); +DECLARE_MSM_GPIO_PINS(120); +DECLARE_MSM_GPIO_PINS(121); +DECLARE_MSM_GPIO_PINS(122); +DECLARE_MSM_GPIO_PINS(123); +DECLARE_MSM_GPIO_PINS(124); +DECLARE_MSM_GPIO_PINS(125); +DECLARE_MSM_GPIO_PINS(126); +DECLARE_MSM_GPIO_PINS(127); +DECLARE_MSM_GPIO_PINS(128); +DECLARE_MSM_GPIO_PINS(129); +DECLARE_MSM_GPIO_PINS(130); +DECLARE_MSM_GPIO_PINS(131); +DECLARE_MSM_GPIO_PINS(132); +DECLARE_MSM_GPIO_PINS(133); +DECLARE_MSM_GPIO_PINS(134); +DECLARE_MSM_GPIO_PINS(135); +DECLARE_MSM_GPIO_PINS(136); +DECLARE_MSM_GPIO_PINS(137); +DECLARE_MSM_GPIO_PINS(138); +DECLARE_MSM_GPIO_PINS(139); +DECLARE_MSM_GPIO_PINS(140); +DECLARE_MSM_GPIO_PINS(141); +DECLARE_MSM_GPIO_PINS(142); +DECLARE_MSM_GPIO_PINS(143); +DECLARE_MSM_GPIO_PINS(144); +DECLARE_MSM_GPIO_PINS(145); +DECLARE_MSM_GPIO_PINS(146); +DECLARE_MSM_GPIO_PINS(147); +DECLARE_MSM_GPIO_PINS(148); +DECLARE_MSM_GPIO_PINS(149); + +static const unsigned int ufs_reset_pins[] = { 150 }; +static const unsigned int sdc1_rclk_pins[] = { 151 }; +static const unsigned int sdc1_clk_pins[] = { 152 }; +static const unsigned int sdc1_cmd_pins[] = { 153 }; +static const unsigned int sdc1_data_pins[] = { 154 }; +static const unsigned int sdc2_clk_pins[] = { 155 }; +static const unsigned int sdc2_cmd_pins[] = { 156 }; +static const unsigned int sdc2_data_pins[] = { 157 }; + +enum sdm670_functions { + msm_mux_gpio, + msm_mux_adsp_ext, + msm_mux_agera_pll, + msm_mux_atest_char, + msm_mux_atest_tsens, + msm_mux_atest_tsens2, + msm_mux_atest_usb1, + msm_mux_atest_usb10, + msm_mux_atest_usb11, + msm_mux_atest_usb12, + msm_mux_atest_usb13, + msm_mux_atest_usb2, + msm_mux_atest_usb20, + msm_mux_atest_usb21, + msm_mux_atest_usb22, + msm_mux_atest_usb23, + msm_mux_cam_mclk, + msm_mux_cci_async, + msm_mux_cci_i2c, + msm_mux_cci_timer0, + msm_mux_cci_timer1, + msm_mux_cci_timer2, + msm_mux_cci_timer3, + msm_mux_cci_timer4, + msm_mux_copy_gp, + msm_mux_copy_phase, + msm_mux_dbg_out, + msm_mux_ddr_bist, + msm_mux_ddr_pxi0, + msm_mux_ddr_pxi1, + msm_mux_ddr_pxi2, + msm_mux_ddr_pxi3, + msm_mux_edp_hot, + msm_mux_edp_lcd, + msm_mux_gcc_gp1, + msm_mux_gcc_gp2, + msm_mux_gcc_gp3, + msm_mux_gp_pdm0, + msm_mux_gp_pdm1, + msm_mux_gp_pdm2, + msm_mux_gps_tx, + msm_mux_jitter_bist, + msm_mux_ldo_en, + msm_mux_ldo_update, + msm_mux_lpass_slimbus, + msm_mux_m_voc, + msm_mux_mdp_vsync, + msm_mux_mdp_vsync0, + msm_mux_mdp_vsync1, + msm_mux_mdp_vsync2, + msm_mux_mdp_vsync3, + msm_mux_mss_lte, + msm_mux_nav_pps, + msm_mux_pa_indicator, + msm_mux_pci_e0, + msm_mux_pci_e1, + msm_mux_phase_flag, + msm_mux_pll_bist, + msm_mux_pll_bypassnl, + msm_mux_pll_reset, + msm_mux_pri_mi2s, + msm_mux_pri_mi2s_ws, + msm_mux_prng_rosc, + msm_mux_qdss_cti, + msm_mux_qdss, + msm_mux_qlink_enable, + msm_mux_qlink_request, + msm_mux_qua_mi2s, + msm_mux_qup0, + msm_mux_qup1, + msm_mux_qup10, + msm_mux_qup11, + msm_mux_qup12, + msm_mux_qup13, + msm_mux_qup14, + msm_mux_qup15, + msm_mux_qup2, + msm_mux_qup3, + msm_mux_qup4, + msm_mux_qup5, + msm_mux_qup6, + msm_mux_qup7, + msm_mux_qup8, + msm_mux_qup9, + msm_mux_qup_l4, + msm_mux_qup_l5, + msm_mux_qup_l6, + msm_mux_sd_write, + msm_mux_sdc4_clk, + msm_mux_sdc4_cmd, + msm_mux_sdc4_data, + msm_mux_sec_mi2s, + msm_mux_ter_mi2s, + msm_mux_tgu_ch0, + msm_mux_tgu_ch1, + msm_mux_tgu_ch2, + msm_mux_tgu_ch3, + msm_mux_tsif1_clk, + msm_mux_tsif1_data, + msm_mux_tsif1_en, + msm_mux_tsif1_error, + msm_mux_tsif1_sync, + msm_mux_tsif2_clk, + msm_mux_tsif2_data, + msm_mux_tsif2_en, + msm_mux_tsif2_error, + msm_mux_tsif2_sync, + msm_mux_uim1_clk, + msm_mux_uim1_data, + msm_mux_uim1_present, + msm_mux_uim1_reset, + msm_mux_uim2_clk, + msm_mux_uim2_data, + msm_mux_uim2_present, + msm_mux_uim2_reset, + msm_mux_uim_batt, + msm_mux_usb_phy, + msm_mux_vfr_1, + msm_mux_vsense_trigger, + msm_mux_wlan1_adc0, + msm_mux_wlan1_adc1, + msm_mux_wlan2_adc0, + msm_mux_wlan2_adc1, + msm_mux_wsa_clk, + msm_mux_wsa_data, + msm_mux__, +}; + +static const char * const gpio_groups[] = { + "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7", + "gpio8", "gpio9", "gpio10", "gpio11", "gpio12", "gpio13", "gpio14", + "gpio15", "gpio16", "gpio17", "gpio18", "gpio19", "gpio20", "gpio21", + "gpio22", "gpio23", "gpio24", "gpio25", "gpio26", "gpio27", "gpio28", + "gpio29", "gpio30", "gpio31", "gpio32", "gpio33", "gpio34", "gpio35", + "gpio36", "gpio37", "gpio38", "gpio39", "gpio40", "gpio41", "gpio42", + "gpio43", "gpio44", "gpio45", "gpio46", "gpio47", "gpio48", "gpio49", + "gpio50", "gpio51", "gpio52", "gpio53", "gpio54", "gpio55", "gpio56", + "gpio57", "gpio65", "gpio66", "gpio67", "gpio68", "gpio75", "gpio76", + "gpio77", "gpio78", "gpio79", "gpio80", "gpio81", "gpio82", "gpio83", + "gpio84", "gpio85", "gpio86", "gpio87", "gpio88", "gpio89", "gpio90", + "gpio91", "gpio92", "gpio93", "gpio94", "gpio95", "gpio96", "gpio97", + "gpio98", "gpio99", "gpio100", "gpio101", "gpio102", "gpio103", + "gpio105", "gpio106", "gpio107", "gpio108", "gpio109", "gpio110", + "gpio111", "gpio112", "gpio113", "gpio114", "gpio115", "gpio116", + "gpio117", "gpio118", "gpio119", "gpio120", "gpio121", "gpio122", + "gpio123", "gpio124", "gpio125", "gpio126", "gpio127", "gpio128", + "gpio129", "gpio130", "gpio131", "gpio132", "gpio133", "gpio134", + "gpio135", "gpio136", "gpio137", "gpio138", "gpio139", "gpio140", + "gpio141", "gpio142", "gpio143", "gpio144", "gpio145", "gpio146", + "gpio147", "gpio148", "gpio149", +}; +static const char * const qup0_groups[] = { + "gpio0", "gpio1", "gpio2", "gpio3", +}; +static const char * const qup9_groups[] = { + "gpio4", "gpio5", "gpio6", "gpio7", +}; +static const char * const qdss_cti_groups[] = { + "gpio4", "gpio5", "gpio51", "gpio52", "gpio90", "gpio91", +}; +static const char * const ddr_pxi0_groups[] = { + "gpio6", "gpio7", +}; +static const char * const ddr_bist_groups[] = { + "gpio7", "gpio8", "gpio9", "gpio10", +}; +static const char * const atest_tsens2_groups[] = { + "gpio7", +}; +static const char * const vsense_trigger_groups[] = { + "gpio7", +}; +static const char * const atest_usb1_groups[] = { + "gpio7", +}; +static const char * const qup_l4_groups[] = { + "gpio8", "gpio35", "gpio75", "gpio105", "gpio123", +}; +static const char * const gp_pdm1_groups[] = { + "gpio8", "gpio66", +}; +static const char * const qup_l5_groups[] = { + "gpio9", "gpio36", "gpio76", "gpio106", "gpio124", +}; +static const char * const mdp_vsync_groups[] = { + "gpio10", "gpio11", "gpio12", "gpio97", "gpio98", +}; +static const char * const qup_l6_groups[] = { + "gpio10", "gpio37", "gpio77", "gpio107", "gpio125", +}; +static const char * const wlan2_adc1_groups[] = { + "gpio10", +}; +static const char * const atest_usb11_groups[] = { + "gpio10", +}; +static const char * const ddr_pxi2_groups[] = { + "gpio10", "gpio11", +}; +static const char * const edp_lcd_groups[] = { + "gpio11", +}; +static const char * const dbg_out_groups[] = { + "gpio11", +}; +static const char * const wlan2_adc0_groups[] = { + "gpio11", +}; +static const char * const atest_usb10_groups[] = { + "gpio11", +}; +static const char * const m_voc_groups[] = { + "gpio12", +}; +static const char * const tsif1_sync_groups[] = { + "gpio12", +}; +static const char * const ddr_pxi3_groups[] = { + "gpio12", "gpio13", +}; +static const char * const cam_mclk_groups[] = { + "gpio13", "gpio14", "gpio15", "gpio16", +}; +static const char * const pll_bypassnl_groups[] = { + "gpio13", +}; +static const char * const qdss_groups[] = { + "gpio13", "gpio14", "gpio15", "gpio16", "gpio17", "gpio18", "gpio19", + "gpio20", "gpio21", "gpio22", "gpio23", "gpio24", "gpio25", "gpio26", + "gpio27", "gpio28", "gpio29", "gpio30", "gpio41", "gpio42", "gpio43", + "gpio44", "gpio75", "gpio76", "gpio77", "gpio79", "gpio80", "gpio93", + "gpio117", "gpio118", "gpio119", "gpio120", "gpio121", "gpio122", + "gpio123", "gpio124", +}; +static const char * const pll_reset_groups[] = { + "gpio14", +}; +static const char * const cci_i2c_groups[] = { + "gpio17", "gpio18", "gpio19", "gpio20", +}; +static const char * const qup1_groups[] = { + "gpio17", "gpio18", "gpio19", "gpio20", +}; +static const char * const cci_timer0_groups[] = { + "gpio21", +}; +static const char * const gcc_gp2_groups[] = { + "gpio21", +}; +static const char * const cci_timer1_groups[] = { + "gpio22", +}; +static const char * const gcc_gp3_groups[] = { + "gpio22", +}; +static const char * const cci_timer2_groups[] = { + "gpio23", +}; +static const char * const cci_timer3_groups[] = { + "gpio24", +}; +static const char * const cci_async_groups[] = { + "gpio24", "gpio25", "gpio26", +}; +static const char * const cci_timer4_groups[] = { + "gpio25", +}; +static const char * const jitter_bist_groups[] = { + "gpio26", "gpio35", +}; +static const char * const qup2_groups[] = { + "gpio27", "gpio28", "gpio29", "gpio30", +}; +static const char * const pll_bist_groups[] = { + "gpio27", "gpio36", +}; +static const char * const agera_pll_groups[] = { + "gpio28", "gpio37", +}; +static const char * const atest_tsens_groups[] = { + "gpio29", +}; +static const char * const phase_flag_groups[] = { + "gpio29", "gpio30", "gpio52", "gpio53", "gpio54", "gpio55", "gpio56", + "gpio57", "gpio75", "gpio76", "gpio77", "gpio89", "gpio90", "gpio96", + "gpio99", "gpio100", "gpio101", "gpio137", "gpio138", "gpio139", + "gpio140", "gpio141", "gpio142", "gpio143", +}; +static const char * const qup11_groups[] = { + "gpio31", "gpio32", "gpio33", "gpio34", +}; +static const char * const qup14_groups[] = { + "gpio31", "gpio32", "gpio33", "gpio34", +}; +static const char * const pci_e0_groups[] = { + "gpio35", "gpio36", +}; +static const char * const usb_phy_groups[] = { + "gpio38", +}; +static const char * const lpass_slimbus_groups[] = { + "gpio39", +}; +static const char * const sd_write_groups[] = { + "gpio40", +}; +static const char * const tsif1_error_groups[] = { + "gpio40", +}; +static const char * const qup3_groups[] = { + "gpio41", "gpio42", "gpio43", "gpio44", +}; +static const char * const qup6_groups[] = { + "gpio45", "gpio46", "gpio47", "gpio48", +}; +static const char * const qup12_groups[] = { + "gpio49", "gpio50", "gpio51", "gpio52", +}; +static const char * const qup10_groups[] = { + "gpio53", "gpio54", "gpio55", "gpio56", +}; +static const char * const gp_pdm0_groups[] = { + "gpio54", "gpio95", +}; +static const char * const wlan1_adc1_groups[] = { + "gpio54", +}; +static const char * const atest_usb13_groups[] = { + "gpio54", +}; +static const char * const ddr_pxi1_groups[] = { + "gpio54", "gpio55", +}; +static const char * const wlan1_adc0_groups[] = { + "gpio55", +}; +static const char * const atest_usb12_groups[] = { + "gpio55", +}; +static const char * const qua_mi2s_groups[] = { + "gpio57", +}; +static const char * const gcc_gp1_groups[] = { + "gpio57", "gpio78", +}; +static const char * const pri_mi2s_groups[] = { + "gpio65", "gpio67", "gpio68", +}; +static const char * const qup8_groups[] = { + "gpio65", "gpio66", "gpio67", "gpio68", +}; +static const char * const wsa_clk_groups[] = { + "gpio65", +}; +static const char * const pri_mi2s_ws_groups[] = { + "gpio66", +}; +static const char * const wsa_data_groups[] = { + "gpio66", +}; +static const char * const atest_usb2_groups[] = { + "gpio67", +}; +static const char * const atest_usb23_groups[] = { + "gpio68", +}; +static const char * const ter_mi2s_groups[] = { + "gpio75", "gpio76", "gpio77", "gpio78", +}; +static const char * const atest_usb22_groups[] = { + "gpio75", +}; +static const char * const atest_usb21_groups[] = { + "gpio76", +}; +static const char * const atest_usb20_groups[] = { + "gpio77", +}; +static const char * const sec_mi2s_groups[] = { + "gpio79", "gpio80", "gpio81", "gpio82", "gpio83", +}; +static const char * const gp_pdm2_groups[] = { + "gpio79", +}; +static const char * const qup15_groups[] = { + "gpio81", "gpio82", "gpio83", "gpio84", +}; +static const char * const qup5_groups[] = { + "gpio85", "gpio86", "gpio87", "gpio88", +}; +static const char * const copy_gp_groups[] = { + "gpio86", +}; +static const char * const tsif1_clk_groups[] = { + "gpio89", +}; +static const char * const qup4_groups[] = { + "gpio89", "gpio90", "gpio91", "gpio92", +}; +static const char * const tgu_ch3_groups[] = { + "gpio89", +}; +static const char * const tsif1_en_groups[] = { + "gpio90", +}; +static const char * const mdp_vsync0_groups[] = { + "gpio90", +}; +static const char * const mdp_vsync1_groups[] = { + "gpio90", +}; +static const char * const mdp_vsync2_groups[] = { + "gpio90", +}; +static const char * const mdp_vsync3_groups[] = { + "gpio90", +}; +static const char * const tgu_ch0_groups[] = { + "gpio90", +}; +static const char * const tsif1_data_groups[] = { + "gpio91", +}; +static const char * const sdc4_cmd_groups[] = { + "gpio91", +}; +static const char * const tgu_ch1_groups[] = { + "gpio91", +}; +static const char * const tsif2_error_groups[] = { + "gpio92", +}; +static const char * const vfr_1_groups[] = { + "gpio92", +}; +static const char * const tgu_ch2_groups[] = { + "gpio92", +}; +static const char * const sdc4_data_groups[] = { + "gpio92", "gpio94", "gpio95", "gpio96", +}; +static const char * const tsif2_clk_groups[] = { + "gpio93", +}; +static const char * const sdc4_clk_groups[] = { + "gpio93", +}; +static const char * const qup7_groups[] = { + "gpio93", "gpio94", "gpio95", "gpio96", +}; +static const char * const tsif2_en_groups[] = { + "gpio94", +}; +static const char * const tsif2_data_groups[] = { + "gpio95", +}; +static const char * const tsif2_sync_groups[] = { + "gpio96", +}; +static const char * const ldo_en_groups[] = { + "gpio97", +}; +static const char * const ldo_update_groups[] = { + "gpio98", +}; +static const char * const prng_rosc_groups[] = { + "gpio99", "gpio102", +}; +static const char * const pci_e1_groups[] = { + "gpio102", "gpio103", +}; +static const char * const copy_phase_groups[] = { + "gpio103", +}; +static const char * const uim2_data_groups[] = { + "gpio105", +}; +static const char * const qup13_groups[] = { + "gpio105", "gpio106", "gpio107", "gpio108", +}; +static const char * const uim2_clk_groups[] = { + "gpio106", +}; +static const char * const uim2_reset_groups[] = { + "gpio107", +}; +static const char * const uim2_present_groups[] = { + "gpio108", +}; +static const char * const uim1_data_groups[] = { + "gpio109", +}; +static const char * const uim1_clk_groups[] = { + "gpio110", +}; +static const char * const uim1_reset_groups[] = { + "gpio111", +}; +static const char * const uim1_present_groups[] = { + "gpio112", +}; +static const char * const uim_batt_groups[] = { + "gpio113", +}; +static const char * const edp_hot_groups[] = { + "gpio113", +}; +static const char * const nav_pps_groups[] = { + "gpio114", "gpio114", "gpio115", "gpio115", "gpio128", "gpio128", + "gpio129", "gpio129", "gpio143", "gpio143", +}; +static const char * const gps_tx_groups[] = { + "gpio114", "gpio115", "gpio128", "gpio129", "gpio143", "gpio145", +}; +static const char * const atest_char_groups[] = { + "gpio117", "gpio118", "gpio119", "gpio120", "gpio121", +}; +static const char * const adsp_ext_groups[] = { + "gpio118", +}; +static const char * const qlink_request_groups[] = { + "gpio130", +}; +static const char * const qlink_enable_groups[] = { + "gpio131", +}; +static const char * const pa_indicator_groups[] = { + "gpio135", +}; +static const char * const mss_lte_groups[] = { + "gpio144", "gpio145", +}; + +static const struct pinfunction sdm670_functions[] = { + MSM_PIN_FUNCTION(gpio), + MSM_PIN_FUNCTION(adsp_ext), + MSM_PIN_FUNCTION(agera_pll), + MSM_PIN_FUNCTION(atest_char), + MSM_PIN_FUNCTION(atest_tsens), + MSM_PIN_FUNCTION(atest_tsens2), + MSM_PIN_FUNCTION(atest_usb1), + MSM_PIN_FUNCTION(atest_usb10), + MSM_PIN_FUNCTION(atest_usb11), + MSM_PIN_FUNCTION(atest_usb12), + MSM_PIN_FUNCTION(atest_usb13), + MSM_PIN_FUNCTION(atest_usb2), + MSM_PIN_FUNCTION(atest_usb20), + MSM_PIN_FUNCTION(atest_usb21), + MSM_PIN_FUNCTION(atest_usb22), + MSM_PIN_FUNCTION(atest_usb23), + MSM_PIN_FUNCTION(cam_mclk), + MSM_PIN_FUNCTION(cci_async), + MSM_PIN_FUNCTION(cci_i2c), + MSM_PIN_FUNCTION(cci_timer0), + MSM_PIN_FUNCTION(cci_timer1), + MSM_PIN_FUNCTION(cci_timer2), + MSM_PIN_FUNCTION(cci_timer3), + MSM_PIN_FUNCTION(cci_timer4), + MSM_PIN_FUNCTION(copy_gp), + MSM_PIN_FUNCTION(copy_phase), + MSM_PIN_FUNCTION(dbg_out), + MSM_PIN_FUNCTION(ddr_bist), + MSM_PIN_FUNCTION(ddr_pxi0), + MSM_PIN_FUNCTION(ddr_pxi1), + MSM_PIN_FUNCTION(ddr_pxi2), + MSM_PIN_FUNCTION(ddr_pxi3), + MSM_PIN_FUNCTION(edp_hot), + MSM_PIN_FUNCTION(edp_lcd), + MSM_PIN_FUNCTION(gcc_gp1), + MSM_PIN_FUNCTION(gcc_gp2), + MSM_PIN_FUNCTION(gcc_gp3), + MSM_PIN_FUNCTION(gp_pdm0), + MSM_PIN_FUNCTION(gp_pdm1), + MSM_PIN_FUNCTION(gp_pdm2), + MSM_PIN_FUNCTION(gps_tx), + MSM_PIN_FUNCTION(jitter_bist), + MSM_PIN_FUNCTION(ldo_en), + MSM_PIN_FUNCTION(ldo_update), + MSM_PIN_FUNCTION(lpass_slimbus), + MSM_PIN_FUNCTION(m_voc), + MSM_PIN_FUNCTION(mdp_vsync), + MSM_PIN_FUNCTION(mdp_vsync0), + MSM_PIN_FUNCTION(mdp_vsync1), + MSM_PIN_FUNCTION(mdp_vsync2), + MSM_PIN_FUNCTION(mdp_vsync3), + MSM_PIN_FUNCTION(mss_lte), + MSM_PIN_FUNCTION(nav_pps), + MSM_PIN_FUNCTION(pa_indicator), + MSM_PIN_FUNCTION(pci_e0), + MSM_PIN_FUNCTION(pci_e1), + MSM_PIN_FUNCTION(phase_flag), + MSM_PIN_FUNCTION(pll_bist), + MSM_PIN_FUNCTION(pll_bypassnl), + MSM_PIN_FUNCTION(pll_reset), + MSM_PIN_FUNCTION(pri_mi2s), + MSM_PIN_FUNCTION(pri_mi2s_ws), + MSM_PIN_FUNCTION(prng_rosc), + MSM_PIN_FUNCTION(qdss_cti), + MSM_PIN_FUNCTION(qdss), + MSM_PIN_FUNCTION(qlink_enable), + MSM_PIN_FUNCTION(qlink_request), + MSM_PIN_FUNCTION(qua_mi2s), + MSM_PIN_FUNCTION(qup0), + MSM_PIN_FUNCTION(qup1), + MSM_PIN_FUNCTION(qup10), + MSM_PIN_FUNCTION(qup11), + MSM_PIN_FUNCTION(qup12), + MSM_PIN_FUNCTION(qup13), + MSM_PIN_FUNCTION(qup14), + MSM_PIN_FUNCTION(qup15), + MSM_PIN_FUNCTION(qup2), + MSM_PIN_FUNCTION(qup3), + MSM_PIN_FUNCTION(qup4), + MSM_PIN_FUNCTION(qup5), + MSM_PIN_FUNCTION(qup6), + MSM_PIN_FUNCTION(qup7), + MSM_PIN_FUNCTION(qup8), + MSM_PIN_FUNCTION(qup9), + MSM_PIN_FUNCTION(qup_l4), + MSM_PIN_FUNCTION(qup_l5), + MSM_PIN_FUNCTION(qup_l6), + MSM_PIN_FUNCTION(sdc4_clk), + MSM_PIN_FUNCTION(sdc4_cmd), + MSM_PIN_FUNCTION(sdc4_data), + MSM_PIN_FUNCTION(sd_write), + MSM_PIN_FUNCTION(sec_mi2s), + MSM_PIN_FUNCTION(ter_mi2s), + MSM_PIN_FUNCTION(tgu_ch0), + MSM_PIN_FUNCTION(tgu_ch1), + MSM_PIN_FUNCTION(tgu_ch2), + MSM_PIN_FUNCTION(tgu_ch3), + MSM_PIN_FUNCTION(tsif1_clk), + MSM_PIN_FUNCTION(tsif1_data), + MSM_PIN_FUNCTION(tsif1_en), + MSM_PIN_FUNCTION(tsif1_error), + MSM_PIN_FUNCTION(tsif1_sync), + MSM_PIN_FUNCTION(tsif2_clk), + MSM_PIN_FUNCTION(tsif2_data), + MSM_PIN_FUNCTION(tsif2_en), + MSM_PIN_FUNCTION(tsif2_error), + MSM_PIN_FUNCTION(tsif2_sync), + MSM_PIN_FUNCTION(uim1_clk), + MSM_PIN_FUNCTION(uim1_data), + MSM_PIN_FUNCTION(uim1_present), + MSM_PIN_FUNCTION(uim1_reset), + MSM_PIN_FUNCTION(uim2_clk), + MSM_PIN_FUNCTION(uim2_data), + MSM_PIN_FUNCTION(uim2_present), + MSM_PIN_FUNCTION(uim2_reset), + MSM_PIN_FUNCTION(uim_batt), + MSM_PIN_FUNCTION(usb_phy), + MSM_PIN_FUNCTION(vfr_1), + MSM_PIN_FUNCTION(vsense_trigger), + MSM_PIN_FUNCTION(wlan1_adc0), + MSM_PIN_FUNCTION(wlan1_adc1), + MSM_PIN_FUNCTION(wlan2_adc0), + MSM_PIN_FUNCTION(wlan2_adc1), + MSM_PIN_FUNCTION(wsa_clk), + MSM_PIN_FUNCTION(wsa_data), +}; + +/* + * Each pin is individually controlled by its own group and gpios that cannot + * be requested are represented by the PINGROUP_DUMMY macro so that the group + * numbers and names correspond to their respective gpio. These dummy pins do + * not have a valid set of pinfuncs or a valid ctl_reg and should not be + * requested. + */ +static const struct msm_pingroup sdm670_groups[] = { + PINGROUP(0, SOUTH, qup0, _, _, _, _, _, _, _, _), + PINGROUP(1, SOUTH, qup0, _, _, _, _, _, _, _, _), + PINGROUP(2, SOUTH, qup0, _, _, _, _, _, _, _, _), + PINGROUP(3, SOUTH, qup0, _, _, _, _, _, _, _, _), + PINGROUP(4, NORTH, qup9, qdss_cti, _, _, _, _, _, _, _), + PINGROUP(5, NORTH, qup9, qdss_cti, _, _, _, _, _, _, _), + PINGROUP(6, NORTH, qup9, _, ddr_pxi0, _, _, _, _, _, _), + PINGROUP(7, NORTH, qup9, ddr_bist, _, atest_tsens2, vsense_trigger, atest_usb1, ddr_pxi0, _, _), + PINGROUP(8, WEST, qup_l4, gp_pdm1, ddr_bist, _, _, _, _, _, _), + PINGROUP(9, WEST, qup_l5, ddr_bist, _, _, _, _, _, _, _), + PINGROUP(10, NORTH, mdp_vsync, qup_l6, ddr_bist, wlan2_adc1, atest_usb11, ddr_pxi2, _, _, _), + PINGROUP(11, NORTH, mdp_vsync, edp_lcd, dbg_out, wlan2_adc0, atest_usb10, ddr_pxi2, _, _, _), + PINGROUP(12, SOUTH, mdp_vsync, m_voc, tsif1_sync, ddr_pxi3, _, _, _, _, _), + PINGROUP(13, WEST, cam_mclk, pll_bypassnl, qdss, ddr_pxi3, _, _, _, _, _), + PINGROUP(14, WEST, cam_mclk, pll_reset, qdss, _, _, _, _, _, _), + PINGROUP(15, WEST, cam_mclk, qdss, _, _, _, _, _, _, _), + PINGROUP(16, WEST, cam_mclk, qdss, _, _, _, _, _, _, _), + PINGROUP(17, WEST, cci_i2c, qup1, qdss, _, _, _, _, _, _), + PINGROUP(18, WEST, cci_i2c, qup1, _, qdss, _, _, _, _, _), + PINGROUP(19, WEST, cci_i2c, qup1, _, qdss, _, _, _, _, _), + PINGROUP(20, WEST, cci_i2c, qup1, _, qdss, _, _, _, _, _), + PINGROUP(21, WEST, cci_timer0, gcc_gp2, qdss, _, _, _, _, _, _), + PINGROUP(22, WEST, cci_timer1, gcc_gp3, qdss, _, _, _, _, _, _), + PINGROUP(23, WEST, cci_timer2, qdss, _, _, _, _, _, _, _), + PINGROUP(24, WEST, cci_timer3, cci_async, qdss, _, _, _, _, _, _), + PINGROUP(25, WEST, cci_timer4, cci_async, qdss, _, _, _, _, _, _), + PINGROUP(26, WEST, cci_async, qdss, jitter_bist, _, _, _, _, _, _), + PINGROUP(27, WEST, qup2, qdss, pll_bist, _, _, _, _, _, _), + PINGROUP(28, WEST, qup2, qdss, agera_pll, _, _, _, _, _, _), + PINGROUP(29, WEST, qup2, _, phase_flag, qdss, atest_tsens, _, _, _, _), + PINGROUP(30, WEST, qup2, phase_flag, qdss, _, _, _, _, _, _), + PINGROUP(31, WEST, qup11, qup14, _, _, _, _, _, _, _), + PINGROUP(32, WEST, qup11, qup14, _, _, _, _, _, _, _), + PINGROUP(33, WEST, qup11, qup14, _, _, _, _, _, _, _), + PINGROUP(34, WEST, qup11, qup14, _, _, _, _, _, _, _), + PINGROUP(35, NORTH, pci_e0, qup_l4, jitter_bist, _, _, _, _, _, _), + PINGROUP(36, NORTH, pci_e0, qup_l5, pll_bist, _, _, _, _, _, _), + PINGROUP(37, NORTH, qup_l6, agera_pll, _, _, _, _, _, _, _), + PINGROUP(38, NORTH, usb_phy, _, _, _, _, _, _, _, _), + PINGROUP(39, NORTH, lpass_slimbus, _, _, _, _, _, _, _, _), + PINGROUP(40, NORTH, sd_write, tsif1_error, _, _, _, _, _, _, _), + PINGROUP(41, SOUTH, qup3, _, qdss, _, _, _, _, _, _), + PINGROUP(42, SOUTH, qup3, _, qdss, _, _, _, _, _, _), + PINGROUP(43, SOUTH, qup3, _, qdss, _, _, _, _, _, _), + PINGROUP(44, SOUTH, qup3, _, qdss, _, _, _, _, _, _), + PINGROUP(45, SOUTH, qup6, _, _, _, _, _, _, _, _), + PINGROUP(46, SOUTH, qup6, _, _, _, _, _, _, _, _), + PINGROUP(47, SOUTH, qup6, _, _, _, _, _, _, _, _), + PINGROUP(48, SOUTH, qup6, _, _, _, _, _, _, _, _), + PINGROUP(49, NORTH, qup12, _, _, _, _, _, _, _, _), + PINGROUP(50, NORTH, qup12, _, _, _, _, _, _, _, _), + PINGROUP(51, NORTH, qup12, qdss_cti, _, _, _, _, _, _, _), + PINGROUP(52, NORTH, qup12, phase_flag, qdss_cti, _, _, _, _, _, _), + PINGROUP(53, NORTH, qup10, phase_flag, _, _, _, _, _, _, _), + PINGROUP(54, NORTH, qup10, gp_pdm0, phase_flag, _, wlan1_adc1, atest_usb13, ddr_pxi1, _, _), + PINGROUP(55, NORTH, qup10, phase_flag, _, wlan1_adc0, atest_usb12, ddr_pxi1, _, _, _), + PINGROUP(56, NORTH, qup10, phase_flag, _, _, _, _, _, _, _), + PINGROUP(57, NORTH, qua_mi2s, gcc_gp1, phase_flag, _, _, _, _, _, _), + PINGROUP_DUMMY(58), + PINGROUP_DUMMY(59), + PINGROUP_DUMMY(60), + PINGROUP_DUMMY(61), + PINGROUP_DUMMY(62), + PINGROUP_DUMMY(63), + PINGROUP_DUMMY(64), + PINGROUP(65, NORTH, pri_mi2s, qup8, wsa_clk, _, _, _, _, _, _), + PINGROUP(66, NORTH, pri_mi2s_ws, qup8, wsa_data, gp_pdm1, _, _, _, _, _), + PINGROUP(67, NORTH, pri_mi2s, qup8, _, atest_usb2, _, _, _, _, _), + PINGROUP(68, NORTH, pri_mi2s, qup8, _, atest_usb23, _, _, _, _, _), + PINGROUP_DUMMY(69), + PINGROUP_DUMMY(70), + PINGROUP_DUMMY(71), + PINGROUP_DUMMY(72), + PINGROUP_DUMMY(73), + PINGROUP_DUMMY(74), + PINGROUP(75, NORTH, ter_mi2s, phase_flag, qdss, atest_usb22, qup_l4, _, _, _, _), + PINGROUP(76, NORTH, ter_mi2s, phase_flag, qdss, atest_usb21, qup_l5, _, _, _, _), + PINGROUP(77, NORTH, ter_mi2s, phase_flag, qdss, atest_usb20, qup_l6, _, _, _, _), + PINGROUP(78, NORTH, ter_mi2s, gcc_gp1, _, _, _, _, _, _, _), + PINGROUP(79, NORTH, sec_mi2s, gp_pdm2, _, qdss, _, _, _, _, _), + PINGROUP(80, NORTH, sec_mi2s, _, qdss, _, _, _, _, _, _), + PINGROUP(81, NORTH, sec_mi2s, qup15, _, _, _, _, _, _, _), + PINGROUP(82, NORTH, sec_mi2s, qup15, _, _, _, _, _, _, _), + PINGROUP(83, NORTH, sec_mi2s, qup15, _, _, _, _, _, _, _), + PINGROUP(84, NORTH, qup15, _, _, _, _, _, _, _, _), + PINGROUP(85, SOUTH, qup5, _, _, _, _, _, _, _, _), + PINGROUP(86, SOUTH, qup5, copy_gp, _, _, _, _, _, _, _), + PINGROUP(87, SOUTH, qup5, _, _, _, _, _, _, _, _), + PINGROUP(88, SOUTH, qup5, _, _, _, _, _, _, _, _), + PINGROUP(89, SOUTH, tsif1_clk, qup4, tgu_ch3, phase_flag, _, _, _, _, _), + PINGROUP(90, SOUTH, tsif1_en, mdp_vsync0, qup4, mdp_vsync1, mdp_vsync2, mdp_vsync3, tgu_ch0, phase_flag, qdss_cti), + PINGROUP(91, SOUTH, tsif1_data, sdc4_cmd, qup4, tgu_ch1, _, qdss_cti, _, _, _), + PINGROUP(92, SOUTH, tsif2_error, sdc4_data, qup4, vfr_1, tgu_ch2, _, _, _, _), + PINGROUP(93, SOUTH, tsif2_clk, sdc4_clk, qup7, _, qdss, _, _, _, _), + PINGROUP(94, SOUTH, tsif2_en, sdc4_data, qup7, _, _, _, _, _, _), + PINGROUP(95, SOUTH, tsif2_data, sdc4_data, qup7, gp_pdm0, _, _, _, _, _), + PINGROUP(96, SOUTH, tsif2_sync, sdc4_data, qup7, phase_flag, _, _, _, _, _), + PINGROUP(97, WEST, _, _, mdp_vsync, ldo_en, _, _, _, _, _), + PINGROUP(98, WEST, _, mdp_vsync, ldo_update, _, _, _, _, _, _), + PINGROUP(99, NORTH, phase_flag, prng_rosc, _, _, _, _, _, _, _), + PINGROUP(100, WEST, phase_flag, _, _, _, _, _, _, _, _), + PINGROUP(101, WEST, _, phase_flag, _, _, _, _, _, _, _), + PINGROUP(102, WEST, pci_e1, prng_rosc, _, _, _, _, _, _, _), + PINGROUP(103, WEST, pci_e1, copy_phase, _, _, _, _, _, _, _), + PINGROUP_DUMMY(104), + PINGROUP(105, NORTH, uim2_data, qup13, qup_l4, _, _, _, _, _, _), + PINGROUP(106, NORTH, uim2_clk, qup13, qup_l5, _, _, _, _, _, _), + PINGROUP(107, NORTH, uim2_reset, qup13, qup_l6, _, _, _, _, _, _), + PINGROUP(108, NORTH, uim2_present, qup13, _, _, _, _, _, _, _), + PINGROUP(109, NORTH, uim1_data, _, _, _, _, _, _, _, _), + PINGROUP(110, NORTH, uim1_clk, _, _, _, _, _, _, _, _), + PINGROUP(111, NORTH, uim1_reset, _, _, _, _, _, _, _, _), + PINGROUP(112, NORTH, uim1_present, _, _, _, _, _, _, _, _), + PINGROUP(113, NORTH, uim_batt, edp_hot, _, _, _, _, _, _, _), + PINGROUP(114, WEST, _, nav_pps, nav_pps, gps_tx, _, _, _, _, _), + PINGROUP(115, WEST, _, nav_pps, nav_pps, gps_tx, _, _, _, _, _), + PINGROUP(116, SOUTH, _, _, _, _, _, _, _, _, _), + PINGROUP(117, NORTH, _, qdss, atest_char, _, _, _, _, _, _), + PINGROUP(118, NORTH, adsp_ext, _, qdss, atest_char, _, _, _, _, _), + PINGROUP(119, NORTH, _, qdss, atest_char, _, _, _, _, _, _), + PINGROUP(120, NORTH, _, qdss, atest_char, _, _, _, _, _, _), + PINGROUP(121, NORTH, _, qdss, atest_char, _, _, _, _, _, _), + PINGROUP(122, NORTH, _, qdss, _, _, _, _, _, _, _), + PINGROUP(123, NORTH, qup_l4, _, qdss, _, _, _, _, _, _), + PINGROUP(124, NORTH, qup_l5, _, qdss, _, _, _, _, _, _), + PINGROUP(125, NORTH, qup_l6, _, _, _, _, _, _, _, _), + PINGROUP(126, NORTH, _, _, _, _, _, _, _, _, _), + PINGROUP(127, WEST, _, _, _, _, _, _, _, _, _), + PINGROUP(128, WEST, nav_pps, nav_pps, gps_tx, _, _, _, _, _, _), + PINGROUP(129, WEST, nav_pps, nav_pps, gps_tx, _, _, _, _, _, _), + PINGROUP(130, WEST, qlink_request, _, _, _, _, _, _, _, _), + PINGROUP(131, WEST, qlink_enable, _, _, _, _, _, _, _, _), + PINGROUP(132, WEST, _, _, _, _, _, _, _, _, _), + PINGROUP(133, NORTH, _, _, _, _, _, _, _, _, _), + PINGROUP(134, NORTH, _, _, _, _, _, _, _, _, _), + PINGROUP(135, WEST, _, pa_indicator, _, _, _, _, _, _, _), + PINGROUP(136, WEST, _, _, _, _, _, _, _, _, _), + PINGROUP(137, WEST, _, _, phase_flag, _, _, _, _, _, _), + PINGROUP(138, WEST, _, _, phase_flag, _, _, _, _, _, _), + PINGROUP(139, WEST, _, phase_flag, _, _, _, _, _, _, _), + PINGROUP(140, WEST, _, _, phase_flag, _, _, _, _, _, _), + PINGROUP(141, WEST, _, phase_flag, _, _, _, _, _, _, _), + PINGROUP(142, WEST, _, phase_flag, _, _, _, _, _, _, _), + PINGROUP(143, WEST, _, nav_pps, nav_pps, gps_tx, phase_flag, _, _, _, _), + PINGROUP(144, SOUTH, mss_lte, _, _, _, _, _, _, _, _), + PINGROUP(145, SOUTH, mss_lte, gps_tx, _, _, _, _, _, _, _), + PINGROUP(146, WEST, _, _, _, _, _, _, _, _, _), + PINGROUP(147, WEST, _, _, _, _, _, _, _, _, _), + PINGROUP(148, WEST, _, _, _, _, _, _, _, _, _), + PINGROUP(149, WEST, _, _, _, _, _, _, _, _, _), + UFS_RESET(ufs_reset, 0x99d000), + SDC_QDSD_PINGROUP(sdc1_rclk, 0x99000, 15, 0), + SDC_QDSD_PINGROUP(sdc1_clk, 0x99000, 13, 6), + SDC_QDSD_PINGROUP(sdc1_cmd, 0x99000, 11, 3), + SDC_QDSD_PINGROUP(sdc1_data, 0x99000, 9, 0), + SDC_QDSD_PINGROUP(sdc2_clk, 0x9a000, 14, 6), + SDC_QDSD_PINGROUP(sdc2_cmd, 0x9a000, 11, 3), + SDC_QDSD_PINGROUP(sdc2_data, 0x9a000, 9, 0), +}; + +static const int sdm670_reserved_gpios[] = { + 58, 59, 60, 61, 62, 63, 64, 69, 70, 71, 72, 73, 74, 104, -1 +}; + +static const struct msm_pinctrl_soc_data sdm670_pinctrl = { + .pins = sdm670_pins, + .npins = ARRAY_SIZE(sdm670_pins), + .functions = sdm670_functions, + .nfunctions = ARRAY_SIZE(sdm670_functions), + .groups = sdm670_groups, + .ngroups = ARRAY_SIZE(sdm670_groups), + .ngpios = 151, + .reserved_gpios = sdm670_reserved_gpios, +}; + +static int sdm670_pinctrl_probe(struct platform_device *pdev) +{ + return msm_pinctrl_probe(pdev, &sdm670_pinctrl); +} + +static const struct of_device_id sdm670_pinctrl_of_match[] = { + { .compatible = "qcom,sdm670-tlmm", }, + { }, +}; +MODULE_DEVICE_TABLE(of, sdm670_pinctrl_of_match); + +static struct platform_driver sdm670_pinctrl_driver = { + .driver = { + .name = "sdm670-pinctrl", + .of_match_table = sdm670_pinctrl_of_match, + }, + .probe = sdm670_pinctrl_probe, + .remove = msm_pinctrl_remove, +}; + +static int __init sdm670_pinctrl_init(void) +{ + return platform_driver_register(&sdm670_pinctrl_driver); +} +arch_initcall(sdm670_pinctrl_init); + +static void __exit sdm670_pinctrl_exit(void) +{ + platform_driver_unregister(&sdm670_pinctrl_driver); +} +module_exit(sdm670_pinctrl_exit); + +MODULE_DESCRIPTION("Qualcomm SDM670 TLMM pinctrl driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/pinctrl/qcom/pinctrl-sdm845.c b/drivers/pinctrl/qcom/pinctrl-sdm845.c new file mode 100644 index 0000000000..cc05c415ed --- /dev/null +++ b/drivers/pinctrl/qcom/pinctrl-sdm845.c @@ -0,0 +1,1371 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2016-2019, The Linux Foundation. All rights reserved. + */ + +#include <linux/acpi.h> +#include <linux/module.h> +#include <linux/of.h> +#include <linux/platform_device.h> + +#include "pinctrl-msm.h" + +#define NORTH 0x00500000 +#define SOUTH 0x00900000 +#define EAST 0x00100000 +#define REG_SIZE 0x1000 +#define PINGROUP(id, base, f1, f2, f3, f4, f5, f6, f7, f8, f9, f10) \ + { \ + .grp = PINCTRL_PINGROUP("gpio" #id, \ + gpio##id##_pins, \ + ARRAY_SIZE(gpio##id##_pins)), \ + .funcs = (int[]){ \ + msm_mux_gpio, /* gpio mode */ \ + msm_mux_##f1, \ + msm_mux_##f2, \ + msm_mux_##f3, \ + msm_mux_##f4, \ + msm_mux_##f5, \ + msm_mux_##f6, \ + msm_mux_##f7, \ + msm_mux_##f8, \ + msm_mux_##f9, \ + msm_mux_##f10 \ + }, \ + .nfuncs = 11, \ + .ctl_reg = base + REG_SIZE * id, \ + .io_reg = base + 0x4 + REG_SIZE * id, \ + .intr_cfg_reg = base + 0x8 + REG_SIZE * id, \ + .intr_status_reg = base + 0xc + REG_SIZE * id, \ + .intr_target_reg = base + 0x8 + REG_SIZE * id, \ + .mux_bit = 2, \ + .pull_bit = 0, \ + .drv_bit = 6, \ + .oe_bit = 9, \ + .in_bit = 0, \ + .out_bit = 1, \ + .intr_enable_bit = 0, \ + .intr_status_bit = 0, \ + .intr_target_bit = 5, \ + .intr_target_kpss_val = 3, \ + .intr_raw_status_bit = 4, \ + .intr_polarity_bit = 1, \ + .intr_detection_bit = 2, \ + .intr_detection_width = 2, \ + } + +#define SDC_QDSD_PINGROUP(pg_name, ctl, pull, drv) \ + { \ + .grp = PINCTRL_PINGROUP(#pg_name, \ + pg_name##_pins, \ + ARRAY_SIZE(pg_name##_pins)), \ + .ctl_reg = ctl, \ + .io_reg = 0, \ + .intr_cfg_reg = 0, \ + .intr_status_reg = 0, \ + .intr_target_reg = 0, \ + .mux_bit = -1, \ + .pull_bit = pull, \ + .drv_bit = drv, \ + .oe_bit = -1, \ + .in_bit = -1, \ + .out_bit = -1, \ + .intr_enable_bit = -1, \ + .intr_status_bit = -1, \ + .intr_target_bit = -1, \ + .intr_raw_status_bit = -1, \ + .intr_polarity_bit = -1, \ + .intr_detection_bit = -1, \ + .intr_detection_width = -1, \ + } + +#define UFS_RESET(pg_name, offset) \ + { \ + .grp = PINCTRL_PINGROUP(#pg_name, \ + pg_name##_pins, \ + ARRAY_SIZE(pg_name##_pins)), \ + .ctl_reg = offset, \ + .io_reg = offset + 0x4, \ + .intr_cfg_reg = 0, \ + .intr_status_reg = 0, \ + .intr_target_reg = 0, \ + .mux_bit = -1, \ + .pull_bit = 3, \ + .drv_bit = 0, \ + .oe_bit = -1, \ + .in_bit = -1, \ + .out_bit = 0, \ + .intr_enable_bit = -1, \ + .intr_status_bit = -1, \ + .intr_target_bit = -1, \ + .intr_raw_status_bit = -1, \ + .intr_polarity_bit = -1, \ + .intr_detection_bit = -1, \ + .intr_detection_width = -1, \ + } +static const struct pinctrl_pin_desc sdm845_pins[] = { + PINCTRL_PIN(0, "GPIO_0"), + PINCTRL_PIN(1, "GPIO_1"), + PINCTRL_PIN(2, "GPIO_2"), + PINCTRL_PIN(3, "GPIO_3"), + PINCTRL_PIN(4, "GPIO_4"), + PINCTRL_PIN(5, "GPIO_5"), + PINCTRL_PIN(6, "GPIO_6"), + PINCTRL_PIN(7, "GPIO_7"), + PINCTRL_PIN(8, "GPIO_8"), + PINCTRL_PIN(9, "GPIO_9"), + PINCTRL_PIN(10, "GPIO_10"), + PINCTRL_PIN(11, "GPIO_11"), + PINCTRL_PIN(12, "GPIO_12"), + PINCTRL_PIN(13, "GPIO_13"), + PINCTRL_PIN(14, "GPIO_14"), + PINCTRL_PIN(15, "GPIO_15"), + PINCTRL_PIN(16, "GPIO_16"), + PINCTRL_PIN(17, "GPIO_17"), + PINCTRL_PIN(18, "GPIO_18"), + PINCTRL_PIN(19, "GPIO_19"), + PINCTRL_PIN(20, "GPIO_20"), + PINCTRL_PIN(21, "GPIO_21"), + PINCTRL_PIN(22, "GPIO_22"), + PINCTRL_PIN(23, "GPIO_23"), + PINCTRL_PIN(24, "GPIO_24"), + PINCTRL_PIN(25, "GPIO_25"), + PINCTRL_PIN(26, "GPIO_26"), + PINCTRL_PIN(27, "GPIO_27"), + PINCTRL_PIN(28, "GPIO_28"), + PINCTRL_PIN(29, "GPIO_29"), + PINCTRL_PIN(30, "GPIO_30"), + PINCTRL_PIN(31, "GPIO_31"), + PINCTRL_PIN(32, "GPIO_32"), + PINCTRL_PIN(33, "GPIO_33"), + PINCTRL_PIN(34, "GPIO_34"), + PINCTRL_PIN(35, "GPIO_35"), + PINCTRL_PIN(36, "GPIO_36"), + PINCTRL_PIN(37, "GPIO_37"), + PINCTRL_PIN(38, "GPIO_38"), + PINCTRL_PIN(39, "GPIO_39"), + PINCTRL_PIN(40, "GPIO_40"), + PINCTRL_PIN(41, "GPIO_41"), + PINCTRL_PIN(42, "GPIO_42"), + PINCTRL_PIN(43, "GPIO_43"), + PINCTRL_PIN(44, "GPIO_44"), + PINCTRL_PIN(45, "GPIO_45"), + PINCTRL_PIN(46, "GPIO_46"), + PINCTRL_PIN(47, "GPIO_47"), + PINCTRL_PIN(48, "GPIO_48"), + PINCTRL_PIN(49, "GPIO_49"), + PINCTRL_PIN(50, "GPIO_50"), + PINCTRL_PIN(51, "GPIO_51"), + PINCTRL_PIN(52, "GPIO_52"), + PINCTRL_PIN(53, "GPIO_53"), + PINCTRL_PIN(54, "GPIO_54"), + PINCTRL_PIN(55, "GPIO_55"), + PINCTRL_PIN(56, "GPIO_56"), + PINCTRL_PIN(57, "GPIO_57"), + PINCTRL_PIN(58, "GPIO_58"), + PINCTRL_PIN(59, "GPIO_59"), + PINCTRL_PIN(60, "GPIO_60"), + PINCTRL_PIN(61, "GPIO_61"), + PINCTRL_PIN(62, "GPIO_62"), + PINCTRL_PIN(63, "GPIO_63"), + PINCTRL_PIN(64, "GPIO_64"), + PINCTRL_PIN(65, "GPIO_65"), + PINCTRL_PIN(66, "GPIO_66"), + PINCTRL_PIN(67, "GPIO_67"), + PINCTRL_PIN(68, "GPIO_68"), + PINCTRL_PIN(69, "GPIO_69"), + PINCTRL_PIN(70, "GPIO_70"), + PINCTRL_PIN(71, "GPIO_71"), + PINCTRL_PIN(72, "GPIO_72"), + PINCTRL_PIN(73, "GPIO_73"), + PINCTRL_PIN(74, "GPIO_74"), + PINCTRL_PIN(75, "GPIO_75"), + PINCTRL_PIN(76, "GPIO_76"), + PINCTRL_PIN(77, "GPIO_77"), + PINCTRL_PIN(78, "GPIO_78"), + PINCTRL_PIN(79, "GPIO_79"), + PINCTRL_PIN(80, "GPIO_80"), + PINCTRL_PIN(81, "GPIO_81"), + PINCTRL_PIN(82, "GPIO_82"), + PINCTRL_PIN(83, "GPIO_83"), + PINCTRL_PIN(84, "GPIO_84"), + PINCTRL_PIN(85, "GPIO_85"), + PINCTRL_PIN(86, "GPIO_86"), + PINCTRL_PIN(87, "GPIO_87"), + PINCTRL_PIN(88, "GPIO_88"), + PINCTRL_PIN(89, "GPIO_89"), + PINCTRL_PIN(90, "GPIO_90"), + PINCTRL_PIN(91, "GPIO_91"), + PINCTRL_PIN(92, "GPIO_92"), + PINCTRL_PIN(93, "GPIO_93"), + PINCTRL_PIN(94, "GPIO_94"), + PINCTRL_PIN(95, "GPIO_95"), + PINCTRL_PIN(96, "GPIO_96"), + PINCTRL_PIN(97, "GPIO_97"), + PINCTRL_PIN(98, "GPIO_98"), + PINCTRL_PIN(99, "GPIO_99"), + PINCTRL_PIN(100, "GPIO_100"), + PINCTRL_PIN(101, "GPIO_101"), + PINCTRL_PIN(102, "GPIO_102"), + PINCTRL_PIN(103, "GPIO_103"), + PINCTRL_PIN(104, "GPIO_104"), + PINCTRL_PIN(105, "GPIO_105"), + PINCTRL_PIN(106, "GPIO_106"), + PINCTRL_PIN(107, "GPIO_107"), + PINCTRL_PIN(108, "GPIO_108"), + PINCTRL_PIN(109, "GPIO_109"), + PINCTRL_PIN(110, "GPIO_110"), + PINCTRL_PIN(111, "GPIO_111"), + PINCTRL_PIN(112, "GPIO_112"), + PINCTRL_PIN(113, "GPIO_113"), + PINCTRL_PIN(114, "GPIO_114"), + PINCTRL_PIN(115, "GPIO_115"), + PINCTRL_PIN(116, "GPIO_116"), + PINCTRL_PIN(117, "GPIO_117"), + PINCTRL_PIN(118, "GPIO_118"), + PINCTRL_PIN(119, "GPIO_119"), + PINCTRL_PIN(120, "GPIO_120"), + PINCTRL_PIN(121, "GPIO_121"), + PINCTRL_PIN(122, "GPIO_122"), + PINCTRL_PIN(123, "GPIO_123"), + PINCTRL_PIN(124, "GPIO_124"), + PINCTRL_PIN(125, "GPIO_125"), + PINCTRL_PIN(126, "GPIO_126"), + PINCTRL_PIN(127, "GPIO_127"), + PINCTRL_PIN(128, "GPIO_128"), + PINCTRL_PIN(129, "GPIO_129"), + PINCTRL_PIN(130, "GPIO_130"), + PINCTRL_PIN(131, "GPIO_131"), + PINCTRL_PIN(132, "GPIO_132"), + PINCTRL_PIN(133, "GPIO_133"), + PINCTRL_PIN(134, "GPIO_134"), + PINCTRL_PIN(135, "GPIO_135"), + PINCTRL_PIN(136, "GPIO_136"), + PINCTRL_PIN(137, "GPIO_137"), + PINCTRL_PIN(138, "GPIO_138"), + PINCTRL_PIN(139, "GPIO_139"), + PINCTRL_PIN(140, "GPIO_140"), + PINCTRL_PIN(141, "GPIO_141"), + PINCTRL_PIN(142, "GPIO_142"), + PINCTRL_PIN(143, "GPIO_143"), + PINCTRL_PIN(144, "GPIO_144"), + PINCTRL_PIN(145, "GPIO_145"), + PINCTRL_PIN(146, "GPIO_146"), + PINCTRL_PIN(147, "GPIO_147"), + PINCTRL_PIN(148, "GPIO_148"), + PINCTRL_PIN(149, "GPIO_149"), + PINCTRL_PIN(150, "UFS_RESET"), + PINCTRL_PIN(151, "SDC2_CLK"), + PINCTRL_PIN(152, "SDC2_CMD"), + PINCTRL_PIN(153, "SDC2_DATA"), +}; + +#define DECLARE_MSM_GPIO_PINS(pin) \ + static const unsigned int gpio##pin##_pins[] = { pin } +DECLARE_MSM_GPIO_PINS(0); +DECLARE_MSM_GPIO_PINS(1); +DECLARE_MSM_GPIO_PINS(2); +DECLARE_MSM_GPIO_PINS(3); +DECLARE_MSM_GPIO_PINS(4); +DECLARE_MSM_GPIO_PINS(5); +DECLARE_MSM_GPIO_PINS(6); +DECLARE_MSM_GPIO_PINS(7); +DECLARE_MSM_GPIO_PINS(8); +DECLARE_MSM_GPIO_PINS(9); +DECLARE_MSM_GPIO_PINS(10); +DECLARE_MSM_GPIO_PINS(11); +DECLARE_MSM_GPIO_PINS(12); +DECLARE_MSM_GPIO_PINS(13); +DECLARE_MSM_GPIO_PINS(14); +DECLARE_MSM_GPIO_PINS(15); +DECLARE_MSM_GPIO_PINS(16); +DECLARE_MSM_GPIO_PINS(17); +DECLARE_MSM_GPIO_PINS(18); +DECLARE_MSM_GPIO_PINS(19); +DECLARE_MSM_GPIO_PINS(20); +DECLARE_MSM_GPIO_PINS(21); +DECLARE_MSM_GPIO_PINS(22); +DECLARE_MSM_GPIO_PINS(23); +DECLARE_MSM_GPIO_PINS(24); +DECLARE_MSM_GPIO_PINS(25); +DECLARE_MSM_GPIO_PINS(26); +DECLARE_MSM_GPIO_PINS(27); +DECLARE_MSM_GPIO_PINS(28); +DECLARE_MSM_GPIO_PINS(29); +DECLARE_MSM_GPIO_PINS(30); +DECLARE_MSM_GPIO_PINS(31); +DECLARE_MSM_GPIO_PINS(32); +DECLARE_MSM_GPIO_PINS(33); +DECLARE_MSM_GPIO_PINS(34); +DECLARE_MSM_GPIO_PINS(35); +DECLARE_MSM_GPIO_PINS(36); +DECLARE_MSM_GPIO_PINS(37); +DECLARE_MSM_GPIO_PINS(38); +DECLARE_MSM_GPIO_PINS(39); +DECLARE_MSM_GPIO_PINS(40); +DECLARE_MSM_GPIO_PINS(41); +DECLARE_MSM_GPIO_PINS(42); +DECLARE_MSM_GPIO_PINS(43); +DECLARE_MSM_GPIO_PINS(44); +DECLARE_MSM_GPIO_PINS(45); +DECLARE_MSM_GPIO_PINS(46); +DECLARE_MSM_GPIO_PINS(47); +DECLARE_MSM_GPIO_PINS(48); +DECLARE_MSM_GPIO_PINS(49); +DECLARE_MSM_GPIO_PINS(50); +DECLARE_MSM_GPIO_PINS(51); +DECLARE_MSM_GPIO_PINS(52); +DECLARE_MSM_GPIO_PINS(53); +DECLARE_MSM_GPIO_PINS(54); +DECLARE_MSM_GPIO_PINS(55); +DECLARE_MSM_GPIO_PINS(56); +DECLARE_MSM_GPIO_PINS(57); +DECLARE_MSM_GPIO_PINS(58); +DECLARE_MSM_GPIO_PINS(59); +DECLARE_MSM_GPIO_PINS(60); +DECLARE_MSM_GPIO_PINS(61); +DECLARE_MSM_GPIO_PINS(62); +DECLARE_MSM_GPIO_PINS(63); +DECLARE_MSM_GPIO_PINS(64); +DECLARE_MSM_GPIO_PINS(65); +DECLARE_MSM_GPIO_PINS(66); +DECLARE_MSM_GPIO_PINS(67); +DECLARE_MSM_GPIO_PINS(68); +DECLARE_MSM_GPIO_PINS(69); +DECLARE_MSM_GPIO_PINS(70); +DECLARE_MSM_GPIO_PINS(71); +DECLARE_MSM_GPIO_PINS(72); +DECLARE_MSM_GPIO_PINS(73); +DECLARE_MSM_GPIO_PINS(74); +DECLARE_MSM_GPIO_PINS(75); +DECLARE_MSM_GPIO_PINS(76); +DECLARE_MSM_GPIO_PINS(77); +DECLARE_MSM_GPIO_PINS(78); +DECLARE_MSM_GPIO_PINS(79); +DECLARE_MSM_GPIO_PINS(80); +DECLARE_MSM_GPIO_PINS(81); +DECLARE_MSM_GPIO_PINS(82); +DECLARE_MSM_GPIO_PINS(83); +DECLARE_MSM_GPIO_PINS(84); +DECLARE_MSM_GPIO_PINS(85); +DECLARE_MSM_GPIO_PINS(86); +DECLARE_MSM_GPIO_PINS(87); +DECLARE_MSM_GPIO_PINS(88); +DECLARE_MSM_GPIO_PINS(89); +DECLARE_MSM_GPIO_PINS(90); +DECLARE_MSM_GPIO_PINS(91); +DECLARE_MSM_GPIO_PINS(92); +DECLARE_MSM_GPIO_PINS(93); +DECLARE_MSM_GPIO_PINS(94); +DECLARE_MSM_GPIO_PINS(95); +DECLARE_MSM_GPIO_PINS(96); +DECLARE_MSM_GPIO_PINS(97); +DECLARE_MSM_GPIO_PINS(98); +DECLARE_MSM_GPIO_PINS(99); +DECLARE_MSM_GPIO_PINS(100); +DECLARE_MSM_GPIO_PINS(101); +DECLARE_MSM_GPIO_PINS(102); +DECLARE_MSM_GPIO_PINS(103); +DECLARE_MSM_GPIO_PINS(104); +DECLARE_MSM_GPIO_PINS(105); +DECLARE_MSM_GPIO_PINS(106); +DECLARE_MSM_GPIO_PINS(107); +DECLARE_MSM_GPIO_PINS(108); +DECLARE_MSM_GPIO_PINS(109); +DECLARE_MSM_GPIO_PINS(110); +DECLARE_MSM_GPIO_PINS(111); +DECLARE_MSM_GPIO_PINS(112); +DECLARE_MSM_GPIO_PINS(113); +DECLARE_MSM_GPIO_PINS(114); +DECLARE_MSM_GPIO_PINS(115); +DECLARE_MSM_GPIO_PINS(116); +DECLARE_MSM_GPIO_PINS(117); +DECLARE_MSM_GPIO_PINS(118); +DECLARE_MSM_GPIO_PINS(119); +DECLARE_MSM_GPIO_PINS(120); +DECLARE_MSM_GPIO_PINS(121); +DECLARE_MSM_GPIO_PINS(122); +DECLARE_MSM_GPIO_PINS(123); +DECLARE_MSM_GPIO_PINS(124); +DECLARE_MSM_GPIO_PINS(125); +DECLARE_MSM_GPIO_PINS(126); +DECLARE_MSM_GPIO_PINS(127); +DECLARE_MSM_GPIO_PINS(128); +DECLARE_MSM_GPIO_PINS(129); +DECLARE_MSM_GPIO_PINS(130); +DECLARE_MSM_GPIO_PINS(131); +DECLARE_MSM_GPIO_PINS(132); +DECLARE_MSM_GPIO_PINS(133); +DECLARE_MSM_GPIO_PINS(134); +DECLARE_MSM_GPIO_PINS(135); +DECLARE_MSM_GPIO_PINS(136); +DECLARE_MSM_GPIO_PINS(137); +DECLARE_MSM_GPIO_PINS(138); +DECLARE_MSM_GPIO_PINS(139); +DECLARE_MSM_GPIO_PINS(140); +DECLARE_MSM_GPIO_PINS(141); +DECLARE_MSM_GPIO_PINS(142); +DECLARE_MSM_GPIO_PINS(143); +DECLARE_MSM_GPIO_PINS(144); +DECLARE_MSM_GPIO_PINS(145); +DECLARE_MSM_GPIO_PINS(146); +DECLARE_MSM_GPIO_PINS(147); +DECLARE_MSM_GPIO_PINS(148); +DECLARE_MSM_GPIO_PINS(149); + +static const unsigned int ufs_reset_pins[] = { 150 }; +static const unsigned int sdc2_clk_pins[] = { 151 }; +static const unsigned int sdc2_cmd_pins[] = { 152 }; +static const unsigned int sdc2_data_pins[] = { 153 }; + +enum sdm845_functions { + msm_mux_gpio, + msm_mux_adsp_ext, + msm_mux_agera_pll, + msm_mux_atest_char, + msm_mux_atest_tsens, + msm_mux_atest_tsens2, + msm_mux_atest_usb1, + msm_mux_atest_usb10, + msm_mux_atest_usb11, + msm_mux_atest_usb12, + msm_mux_atest_usb13, + msm_mux_atest_usb2, + msm_mux_atest_usb20, + msm_mux_atest_usb21, + msm_mux_atest_usb22, + msm_mux_atest_usb23, + msm_mux_audio_ref, + msm_mux_btfm_slimbus, + msm_mux_cam_mclk, + msm_mux_cci_async, + msm_mux_cci_i2c, + msm_mux_cci_timer0, + msm_mux_cci_timer1, + msm_mux_cci_timer2, + msm_mux_cci_timer3, + msm_mux_cci_timer4, + msm_mux_cri_trng, + msm_mux_cri_trng0, + msm_mux_cri_trng1, + msm_mux_dbg_out, + msm_mux_ddr_bist, + msm_mux_ddr_pxi0, + msm_mux_ddr_pxi1, + msm_mux_ddr_pxi2, + msm_mux_ddr_pxi3, + msm_mux_edp_hot, + msm_mux_edp_lcd, + msm_mux_gcc_gp1, + msm_mux_gcc_gp2, + msm_mux_gcc_gp3, + msm_mux_jitter_bist, + msm_mux_ldo_en, + msm_mux_ldo_update, + msm_mux_lpass_slimbus, + msm_mux_m_voc, + msm_mux_mdp_vsync, + msm_mux_mdp_vsync0, + msm_mux_mdp_vsync1, + msm_mux_mdp_vsync2, + msm_mux_mdp_vsync3, + msm_mux_mss_lte, + msm_mux_nav_pps, + msm_mux_pa_indicator, + msm_mux_pci_e0, + msm_mux_pci_e1, + msm_mux_phase_flag, + msm_mux_pll_bist, + msm_mux_pll_bypassnl, + msm_mux_pll_reset, + msm_mux_pri_mi2s, + msm_mux_pri_mi2s_ws, + msm_mux_prng_rosc, + msm_mux_qdss_cti, + msm_mux_qdss, + msm_mux_qlink_enable, + msm_mux_qlink_request, + msm_mux_qspi_clk, + msm_mux_qspi_cs, + msm_mux_qspi_data, + msm_mux_qua_mi2s, + msm_mux_qup0, + msm_mux_qup1, + msm_mux_qup10, + msm_mux_qup11, + msm_mux_qup12, + msm_mux_qup13, + msm_mux_qup14, + msm_mux_qup15, + msm_mux_qup2, + msm_mux_qup3, + msm_mux_qup4, + msm_mux_qup5, + msm_mux_qup6, + msm_mux_qup7, + msm_mux_qup8, + msm_mux_qup9, + msm_mux_qup_l4, + msm_mux_qup_l5, + msm_mux_qup_l6, + msm_mux_sd_write, + msm_mux_sdc4_clk, + msm_mux_sdc4_cmd, + msm_mux_sdc4_data, + msm_mux_sec_mi2s, + msm_mux_sp_cmu, + msm_mux_spkr_i2s, + msm_mux_ter_mi2s, + msm_mux_tgu_ch0, + msm_mux_tgu_ch1, + msm_mux_tgu_ch2, + msm_mux_tgu_ch3, + msm_mux_tsense_pwm1, + msm_mux_tsense_pwm2, + msm_mux_tsif1_clk, + msm_mux_tsif1_data, + msm_mux_tsif1_en, + msm_mux_tsif1_error, + msm_mux_tsif1_sync, + msm_mux_tsif2_clk, + msm_mux_tsif2_data, + msm_mux_tsif2_en, + msm_mux_tsif2_error, + msm_mux_tsif2_sync, + msm_mux_uim1_clk, + msm_mux_uim1_data, + msm_mux_uim1_present, + msm_mux_uim1_reset, + msm_mux_uim2_clk, + msm_mux_uim2_data, + msm_mux_uim2_present, + msm_mux_uim2_reset, + msm_mux_uim_batt, + msm_mux_usb_phy, + msm_mux_vfr_1, + msm_mux_vsense_trigger, + msm_mux_wlan1_adc0, + msm_mux_wlan1_adc1, + msm_mux_wlan2_adc0, + msm_mux_wlan2_adc1, + msm_mux__, +}; + +static const char * const ddr_pxi3_groups[] = { + "gpio12", "gpio13", +}; +static const char * const cam_mclk_groups[] = { + "gpio13", "gpio14", "gpio15", "gpio16", +}; +static const char * const pll_bypassnl_groups[] = { + "gpio13", +}; +static const char * const qdss_groups[] = { + "gpio13", "gpio14", "gpio15", "gpio16", "gpio17", "gpio18", "gpio19", + "gpio20", "gpio21", "gpio22", "gpio23", "gpio24", "gpio25", "gpio26", + "gpio27", "gpio28", "gpio29", "gpio30", "gpio41", "gpio42", "gpio43", + "gpio44", "gpio75", "gpio76", "gpio77", "gpio79", "gpio80", "gpio93", + "gpio117", "gpio118", "gpio119", "gpio120", "gpio121", "gpio122", + "gpio123", "gpio124", +}; +static const char * const pll_reset_groups[] = { + "gpio14", +}; +static const char * const cci_i2c_groups[] = { + "gpio17", "gpio18", "gpio19", "gpio20", +}; +static const char * const qup1_groups[] = { + "gpio17", "gpio18", "gpio19", "gpio20", +}; +static const char * const cci_timer0_groups[] = { + "gpio21", +}; +static const char * const gcc_gp2_groups[] = { + "gpio21", "gpio58", +}; +static const char * const cci_timer1_groups[] = { + "gpio22", +}; +static const char * const gcc_gp3_groups[] = { + "gpio22", "gpio59", +}; +static const char * const cci_timer2_groups[] = { + "gpio23", +}; +static const char * const cci_timer3_groups[] = { + "gpio24", +}; +static const char * const cci_async_groups[] = { + "gpio24", "gpio25", "gpio26", +}; +static const char * const cci_timer4_groups[] = { + "gpio25", +}; +static const char * const qup2_groups[] = { + "gpio27", "gpio28", "gpio29", "gpio30", +}; +static const char * const phase_flag_groups[] = { + "gpio29", "gpio30", "gpio52", "gpio53", "gpio54", "gpio55", "gpio56", + "gpio57", "gpio58", "gpio59", "gpio60", "gpio61", "gpio62", "gpio63", + "gpio64", "gpio74", "gpio75", "gpio76", "gpio77", "gpio89", "gpio90", + "gpio96", "gpio99", "gpio100", "gpio103", "gpio137", "gpio138", + "gpio139", "gpio140", "gpio141", "gpio142", "gpio143", +}; +static const char * const qup11_groups[] = { + "gpio31", "gpio32", "gpio33", "gpio34", +}; +static const char * const qup14_groups[] = { + "gpio31", "gpio32", "gpio33", "gpio34", +}; +static const char * const pci_e0_groups[] = { + "gpio35", "gpio36", +}; +static const char * const jitter_bist_groups[] = { + "gpio35", +}; +static const char * const pll_bist_groups[] = { + "gpio36", +}; +static const char * const atest_tsens_groups[] = { + "gpio36", +}; +static const char * const agera_pll_groups[] = { + "gpio37", +}; +static const char * const usb_phy_groups[] = { + "gpio38", +}; +static const char * const lpass_slimbus_groups[] = { + "gpio39", "gpio70", "gpio71", "gpio72", +}; +static const char * const sd_write_groups[] = { + "gpio40", +}; +static const char * const tsif1_error_groups[] = { + "gpio40", +}; +static const char * const qup3_groups[] = { + "gpio41", "gpio42", "gpio43", "gpio44", +}; +static const char * const qup6_groups[] = { + "gpio45", "gpio46", "gpio47", "gpio48", +}; +static const char * const qup12_groups[] = { + "gpio49", "gpio50", "gpio51", "gpio52", +}; +static const char * const qup10_groups[] = { + "gpio53", "gpio54", "gpio55", "gpio56", +}; +static const char * const qua_mi2s_groups[] = { + "gpio57", "gpio58", "gpio59", "gpio60", "gpio61", "gpio62", "gpio63", +}; +static const char * const gcc_gp1_groups[] = { + "gpio57", "gpio78", +}; +static const char * const cri_trng0_groups[] = { + "gpio60", +}; +static const char * const cri_trng1_groups[] = { + "gpio61", +}; +static const char * const cri_trng_groups[] = { + "gpio62", +}; +static const char * const pri_mi2s_groups[] = { + "gpio64", "gpio65", "gpio67", "gpio68", +}; +static const char * const sp_cmu_groups[] = { + "gpio64", +}; +static const char * const qup8_groups[] = { + "gpio65", "gpio66", "gpio67", "gpio68", +}; +static const char * const pri_mi2s_ws_groups[] = { + "gpio66", +}; +static const char * const spkr_i2s_groups[] = { + "gpio69", "gpio70", "gpio71", "gpio72", +}; +static const char * const audio_ref_groups[] = { + "gpio69", +}; +static const char * const tsense_pwm1_groups[] = { + "gpio71", +}; +static const char * const tsense_pwm2_groups[] = { + "gpio71", +}; +static const char * const btfm_slimbus_groups[] = { + "gpio73", "gpio74", +}; +static const char * const atest_usb2_groups[] = { + "gpio73", +}; +static const char * const ter_mi2s_groups[] = { + "gpio74", "gpio75", "gpio76", "gpio77", "gpio78", +}; +static const char * const atest_usb23_groups[] = { + "gpio74", +}; +static const char * const atest_usb22_groups[] = { + "gpio75", +}; +static const char * const atest_usb21_groups[] = { + "gpio76", +}; +static const char * const atest_usb20_groups[] = { + "gpio77", +}; +static const char * const sec_mi2s_groups[] = { + "gpio79", "gpio80", "gpio81", "gpio82", "gpio83", +}; +static const char * const qup15_groups[] = { + "gpio81", "gpio82", "gpio83", "gpio84", +}; +static const char * const qup5_groups[] = { + "gpio85", "gpio86", "gpio87", "gpio88", +}; +static const char * const tsif1_clk_groups[] = { + "gpio89", +}; +static const char * const qup4_groups[] = { + "gpio89", "gpio90", "gpio91", "gpio92", +}; +static const char * const qspi_cs_groups[] = { + "gpio89", "gpio90", +}; +static const char * const tgu_ch3_groups[] = { + "gpio89", +}; +static const char * const tsif1_en_groups[] = { + "gpio90", +}; +static const char * const mdp_vsync0_groups[] = { + "gpio90", +}; +static const char * const mdp_vsync1_groups[] = { + "gpio90", +}; +static const char * const mdp_vsync2_groups[] = { + "gpio90", +}; +static const char * const mdp_vsync3_groups[] = { + "gpio90", +}; +static const char * const tgu_ch0_groups[] = { + "gpio90", +}; +static const char * const tsif1_data_groups[] = { + "gpio91", +}; +static const char * const sdc4_cmd_groups[] = { + "gpio91", +}; +static const char * const qspi_data_groups[] = { + "gpio91", "gpio92", "gpio93", "gpio94", +}; +static const char * const tgu_ch1_groups[] = { + "gpio91", +}; +static const char * const tsif2_error_groups[] = { + "gpio92", +}; +static const char * const sdc4_data_groups[] = { + "gpio92", + "gpio94", + "gpio95", + "gpio96", +}; +static const char * const vfr_1_groups[] = { + "gpio92", +}; +static const char * const tgu_ch2_groups[] = { + "gpio92", +}; +static const char * const tsif2_clk_groups[] = { + "gpio93", +}; +static const char * const sdc4_clk_groups[] = { + "gpio93", +}; +static const char * const qup7_groups[] = { + "gpio93", "gpio94", "gpio95", "gpio96", +}; +static const char * const tsif2_en_groups[] = { + "gpio94", +}; +static const char * const tsif2_data_groups[] = { + "gpio95", +}; +static const char * const qspi_clk_groups[] = { + "gpio95", +}; +static const char * const tsif2_sync_groups[] = { + "gpio96", +}; +static const char * const ldo_en_groups[] = { + "gpio97", +}; +static const char * const ldo_update_groups[] = { + "gpio98", +}; +static const char * const pci_e1_groups[] = { + "gpio102", "gpio103", +}; +static const char * const prng_rosc_groups[] = { + "gpio102", +}; +static const char * const uim2_data_groups[] = { + "gpio105", +}; +static const char * const qup13_groups[] = { + "gpio105", "gpio106", "gpio107", "gpio108", +}; +static const char * const uim2_clk_groups[] = { + "gpio106", +}; +static const char * const uim2_reset_groups[] = { + "gpio107", +}; +static const char * const uim2_present_groups[] = { + "gpio108", +}; +static const char * const uim1_data_groups[] = { + "gpio109", +}; +static const char * const uim1_clk_groups[] = { + "gpio110", +}; +static const char * const uim1_reset_groups[] = { + "gpio111", +}; +static const char * const uim1_present_groups[] = { + "gpio112", +}; +static const char * const uim_batt_groups[] = { + "gpio113", +}; +static const char * const edp_hot_groups[] = { + "gpio113", +}; +static const char * const nav_pps_groups[] = { + "gpio114", "gpio114", "gpio115", "gpio115", "gpio128", "gpio128", + "gpio129", "gpio129", "gpio143", "gpio143", +}; +static const char * const atest_char_groups[] = { + "gpio117", "gpio118", "gpio119", "gpio120", "gpio121", +}; +static const char * const adsp_ext_groups[] = { + "gpio118", +}; +static const char * const qlink_request_groups[] = { + "gpio130", +}; +static const char * const qlink_enable_groups[] = { + "gpio131", +}; +static const char * const pa_indicator_groups[] = { + "gpio135", +}; +static const char * const mss_lte_groups[] = { + "gpio144", "gpio145", +}; +static const char * const qup0_groups[] = { + "gpio0", "gpio1", "gpio2", "gpio3", +}; +static const char * const gpio_groups[] = { + "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7", + "gpio8", "gpio9", "gpio10", "gpio11", "gpio12", "gpio13", "gpio14", + "gpio15", "gpio16", "gpio17", "gpio18", "gpio19", "gpio20", "gpio21", + "gpio22", "gpio23", "gpio24", "gpio25", "gpio26", "gpio27", "gpio28", + "gpio29", "gpio30", "gpio31", "gpio32", "gpio33", "gpio34", "gpio35", + "gpio36", "gpio37", "gpio38", "gpio39", "gpio40", "gpio41", "gpio42", + "gpio43", "gpio44", "gpio45", "gpio46", "gpio47", "gpio48", "gpio49", + "gpio50", "gpio51", "gpio52", "gpio53", "gpio54", "gpio55", "gpio56", + "gpio57", "gpio58", "gpio59", "gpio60", "gpio61", "gpio62", "gpio63", + "gpio64", "gpio65", "gpio66", "gpio67", "gpio68", "gpio69", "gpio70", + "gpio71", "gpio72", "gpio73", "gpio74", "gpio75", "gpio76", "gpio77", + "gpio78", "gpio79", "gpio80", "gpio81", "gpio82", "gpio83", "gpio84", + "gpio85", "gpio86", "gpio87", "gpio88", "gpio89", "gpio90", "gpio91", + "gpio92", "gpio93", "gpio94", "gpio95", "gpio96", "gpio97", "gpio98", + "gpio99", "gpio100", "gpio101", "gpio102", "gpio103", "gpio104", + "gpio105", "gpio106", "gpio107", "gpio108", "gpio109", "gpio110", + "gpio111", "gpio112", "gpio113", "gpio114", "gpio115", "gpio116", + "gpio117", "gpio118", "gpio119", "gpio120", "gpio121", "gpio122", + "gpio123", "gpio124", "gpio125", "gpio126", "gpio127", "gpio128", + "gpio129", "gpio130", "gpio131", "gpio132", "gpio133", "gpio134", + "gpio135", "gpio136", "gpio137", "gpio138", "gpio139", "gpio140", + "gpio141", "gpio142", "gpio143", "gpio144", "gpio145", "gpio146", + "gpio147", "gpio148", "gpio149", +}; +static const char * const qup9_groups[] = { + "gpio4", "gpio5", "gpio6", "gpio7", +}; +static const char * const qdss_cti_groups[] = { + "gpio4", "gpio5", "gpio51", "gpio52", "gpio62", "gpio63", "gpio90", + "gpio91", +}; +static const char * const ddr_pxi0_groups[] = { + "gpio6", "gpio7", +}; +static const char * const ddr_bist_groups[] = { + "gpio7", "gpio8", "gpio9", "gpio10", +}; +static const char * const atest_tsens2_groups[] = { + "gpio7", +}; +static const char * const vsense_trigger_groups[] = { + "gpio7", +}; +static const char * const atest_usb1_groups[] = { + "gpio7", +}; +static const char * const qup_l4_groups[] = { + "gpio8", "gpio35", "gpio105", "gpio123", +}; +static const char * const wlan1_adc1_groups[] = { + "gpio8", +}; +static const char * const atest_usb13_groups[] = { + "gpio8", +}; +static const char * const ddr_pxi1_groups[] = { + "gpio8", "gpio9", +}; +static const char * const qup_l5_groups[] = { + "gpio9", "gpio36", "gpio106", "gpio124", +}; +static const char * const wlan1_adc0_groups[] = { + "gpio9", +}; +static const char * const atest_usb12_groups[] = { + "gpio9", +}; +static const char * const mdp_vsync_groups[] = { + "gpio10", "gpio11", "gpio12", "gpio97", "gpio98", +}; +static const char * const qup_l6_groups[] = { + "gpio10", "gpio37", "gpio107", "gpio125", +}; +static const char * const wlan2_adc1_groups[] = { + "gpio10", +}; +static const char * const atest_usb11_groups[] = { + "gpio10", +}; +static const char * const ddr_pxi2_groups[] = { + "gpio10", "gpio11", +}; +static const char * const edp_lcd_groups[] = { + "gpio11", +}; +static const char * const dbg_out_groups[] = { + "gpio11", +}; +static const char * const wlan2_adc0_groups[] = { + "gpio11", +}; +static const char * const atest_usb10_groups[] = { + "gpio11", +}; +static const char * const m_voc_groups[] = { + "gpio12", +}; +static const char * const tsif1_sync_groups[] = { + "gpio12", +}; + +static const struct pinfunction sdm845_functions[] = { + MSM_PIN_FUNCTION(gpio), + MSM_PIN_FUNCTION(adsp_ext), + MSM_PIN_FUNCTION(agera_pll), + MSM_PIN_FUNCTION(atest_char), + MSM_PIN_FUNCTION(atest_tsens), + MSM_PIN_FUNCTION(atest_tsens2), + MSM_PIN_FUNCTION(atest_usb1), + MSM_PIN_FUNCTION(atest_usb10), + MSM_PIN_FUNCTION(atest_usb11), + MSM_PIN_FUNCTION(atest_usb12), + MSM_PIN_FUNCTION(atest_usb13), + MSM_PIN_FUNCTION(atest_usb2), + MSM_PIN_FUNCTION(atest_usb20), + MSM_PIN_FUNCTION(atest_usb21), + MSM_PIN_FUNCTION(atest_usb22), + MSM_PIN_FUNCTION(atest_usb23), + MSM_PIN_FUNCTION(audio_ref), + MSM_PIN_FUNCTION(btfm_slimbus), + MSM_PIN_FUNCTION(cam_mclk), + MSM_PIN_FUNCTION(cci_async), + MSM_PIN_FUNCTION(cci_i2c), + MSM_PIN_FUNCTION(cci_timer0), + MSM_PIN_FUNCTION(cci_timer1), + MSM_PIN_FUNCTION(cci_timer2), + MSM_PIN_FUNCTION(cci_timer3), + MSM_PIN_FUNCTION(cci_timer4), + MSM_PIN_FUNCTION(cri_trng), + MSM_PIN_FUNCTION(cri_trng0), + MSM_PIN_FUNCTION(cri_trng1), + MSM_PIN_FUNCTION(dbg_out), + MSM_PIN_FUNCTION(ddr_bist), + MSM_PIN_FUNCTION(ddr_pxi0), + MSM_PIN_FUNCTION(ddr_pxi1), + MSM_PIN_FUNCTION(ddr_pxi2), + MSM_PIN_FUNCTION(ddr_pxi3), + MSM_PIN_FUNCTION(edp_hot), + MSM_PIN_FUNCTION(edp_lcd), + MSM_PIN_FUNCTION(gcc_gp1), + MSM_PIN_FUNCTION(gcc_gp2), + MSM_PIN_FUNCTION(gcc_gp3), + MSM_PIN_FUNCTION(jitter_bist), + MSM_PIN_FUNCTION(ldo_en), + MSM_PIN_FUNCTION(ldo_update), + MSM_PIN_FUNCTION(lpass_slimbus), + MSM_PIN_FUNCTION(m_voc), + MSM_PIN_FUNCTION(mdp_vsync), + MSM_PIN_FUNCTION(mdp_vsync0), + MSM_PIN_FUNCTION(mdp_vsync1), + MSM_PIN_FUNCTION(mdp_vsync2), + MSM_PIN_FUNCTION(mdp_vsync3), + MSM_PIN_FUNCTION(mss_lte), + MSM_PIN_FUNCTION(nav_pps), + MSM_PIN_FUNCTION(pa_indicator), + MSM_PIN_FUNCTION(pci_e0), + MSM_PIN_FUNCTION(pci_e1), + MSM_PIN_FUNCTION(phase_flag), + MSM_PIN_FUNCTION(pll_bist), + MSM_PIN_FUNCTION(pll_bypassnl), + MSM_PIN_FUNCTION(pll_reset), + MSM_PIN_FUNCTION(pri_mi2s), + MSM_PIN_FUNCTION(pri_mi2s_ws), + MSM_PIN_FUNCTION(prng_rosc), + MSM_PIN_FUNCTION(qdss_cti), + MSM_PIN_FUNCTION(qdss), + MSM_PIN_FUNCTION(qlink_enable), + MSM_PIN_FUNCTION(qlink_request), + MSM_PIN_FUNCTION(qspi_clk), + MSM_PIN_FUNCTION(qspi_cs), + MSM_PIN_FUNCTION(qspi_data), + MSM_PIN_FUNCTION(qua_mi2s), + MSM_PIN_FUNCTION(qup0), + MSM_PIN_FUNCTION(qup1), + MSM_PIN_FUNCTION(qup10), + MSM_PIN_FUNCTION(qup11), + MSM_PIN_FUNCTION(qup12), + MSM_PIN_FUNCTION(qup13), + MSM_PIN_FUNCTION(qup14), + MSM_PIN_FUNCTION(qup15), + MSM_PIN_FUNCTION(qup2), + MSM_PIN_FUNCTION(qup3), + MSM_PIN_FUNCTION(qup4), + MSM_PIN_FUNCTION(qup5), + MSM_PIN_FUNCTION(qup6), + MSM_PIN_FUNCTION(qup7), + MSM_PIN_FUNCTION(qup8), + MSM_PIN_FUNCTION(qup9), + MSM_PIN_FUNCTION(qup_l4), + MSM_PIN_FUNCTION(qup_l5), + MSM_PIN_FUNCTION(qup_l6), + MSM_PIN_FUNCTION(sd_write), + MSM_PIN_FUNCTION(sdc4_clk), + MSM_PIN_FUNCTION(sdc4_cmd), + MSM_PIN_FUNCTION(sdc4_data), + MSM_PIN_FUNCTION(sec_mi2s), + MSM_PIN_FUNCTION(sp_cmu), + MSM_PIN_FUNCTION(spkr_i2s), + MSM_PIN_FUNCTION(ter_mi2s), + MSM_PIN_FUNCTION(tgu_ch0), + MSM_PIN_FUNCTION(tgu_ch1), + MSM_PIN_FUNCTION(tgu_ch2), + MSM_PIN_FUNCTION(tgu_ch3), + MSM_PIN_FUNCTION(tsense_pwm1), + MSM_PIN_FUNCTION(tsense_pwm2), + MSM_PIN_FUNCTION(tsif1_clk), + MSM_PIN_FUNCTION(tsif1_data), + MSM_PIN_FUNCTION(tsif1_en), + MSM_PIN_FUNCTION(tsif1_error), + MSM_PIN_FUNCTION(tsif1_sync), + MSM_PIN_FUNCTION(tsif2_clk), + MSM_PIN_FUNCTION(tsif2_data), + MSM_PIN_FUNCTION(tsif2_en), + MSM_PIN_FUNCTION(tsif2_error), + MSM_PIN_FUNCTION(tsif2_sync), + MSM_PIN_FUNCTION(uim1_clk), + MSM_PIN_FUNCTION(uim1_data), + MSM_PIN_FUNCTION(uim1_present), + MSM_PIN_FUNCTION(uim1_reset), + MSM_PIN_FUNCTION(uim2_clk), + MSM_PIN_FUNCTION(uim2_data), + MSM_PIN_FUNCTION(uim2_present), + MSM_PIN_FUNCTION(uim2_reset), + MSM_PIN_FUNCTION(uim_batt), + MSM_PIN_FUNCTION(usb_phy), + MSM_PIN_FUNCTION(vfr_1), + MSM_PIN_FUNCTION(vsense_trigger), + MSM_PIN_FUNCTION(wlan1_adc0), + MSM_PIN_FUNCTION(wlan1_adc1), + MSM_PIN_FUNCTION(wlan2_adc0), + MSM_PIN_FUNCTION(wlan2_adc1), +}; + +/* Every pin is maintained as a single group, and missing or non-existing pin + * would be maintained as dummy group to synchronize pin group index with + * pin descriptor registered with pinctrl core. + * Clients would not be able to request these dummy pin groups. + */ +static const struct msm_pingroup sdm845_groups[] = { + PINGROUP(0, EAST, qup0, _, _, _, _, _, _, _, _, _), + PINGROUP(1, EAST, qup0, _, _, _, _, _, _, _, _, _), + PINGROUP(2, EAST, qup0, _, _, _, _, _, _, _, _, _), + PINGROUP(3, EAST, qup0, _, _, _, _, _, _, _, _, _), + PINGROUP(4, NORTH, qup9, qdss_cti, _, _, _, _, _, _, _, _), + PINGROUP(5, NORTH, qup9, qdss_cti, _, _, _, _, _, _, _, _), + PINGROUP(6, NORTH, qup9, _, ddr_pxi0, _, _, _, _, _, _, _), + PINGROUP(7, NORTH, qup9, ddr_bist, _, atest_tsens2, vsense_trigger, atest_usb1, ddr_pxi0, _, _, _), + PINGROUP(8, EAST, qup_l4, _, ddr_bist, _, _, wlan1_adc1, atest_usb13, ddr_pxi1, _, _), + PINGROUP(9, EAST, qup_l5, ddr_bist, _, wlan1_adc0, atest_usb12, ddr_pxi1, _, _, _, _), + PINGROUP(10, EAST, mdp_vsync, qup_l6, ddr_bist, wlan2_adc1, atest_usb11, ddr_pxi2, _, _, _, _), + PINGROUP(11, EAST, mdp_vsync, edp_lcd, dbg_out, wlan2_adc0, atest_usb10, ddr_pxi2, _, _, _, _), + PINGROUP(12, SOUTH, mdp_vsync, m_voc, tsif1_sync, ddr_pxi3, _, _, _, _, _, _), + PINGROUP(13, SOUTH, cam_mclk, pll_bypassnl, qdss, ddr_pxi3, _, _, _, _, _, _), + PINGROUP(14, SOUTH, cam_mclk, pll_reset, qdss, _, _, _, _, _, _, _), + PINGROUP(15, SOUTH, cam_mclk, qdss, _, _, _, _, _, _, _, _), + PINGROUP(16, SOUTH, cam_mclk, qdss, _, _, _, _, _, _, _, _), + PINGROUP(17, SOUTH, cci_i2c, qup1, qdss, _, _, _, _, _, _, _), + PINGROUP(18, SOUTH, cci_i2c, qup1, _, qdss, _, _, _, _, _, _), + PINGROUP(19, SOUTH, cci_i2c, qup1, _, qdss, _, _, _, _, _, _), + PINGROUP(20, SOUTH, cci_i2c, qup1, _, qdss, _, _, _, _, _, _), + PINGROUP(21, SOUTH, cci_timer0, gcc_gp2, qdss, _, _, _, _, _, _, _), + PINGROUP(22, SOUTH, cci_timer1, gcc_gp3, qdss, _, _, _, _, _, _, _), + PINGROUP(23, SOUTH, cci_timer2, qdss, _, _, _, _, _, _, _, _), + PINGROUP(24, SOUTH, cci_timer3, cci_async, qdss, _, _, _, _, _, _, _), + PINGROUP(25, SOUTH, cci_timer4, cci_async, qdss, _, _, _, _, _, _, _), + PINGROUP(26, SOUTH, cci_async, qdss, _, _, _, _, _, _, _, _), + PINGROUP(27, EAST, qup2, qdss, _, _, _, _, _, _, _, _), + PINGROUP(28, EAST, qup2, qdss, _, _, _, _, _, _, _, _), + PINGROUP(29, EAST, qup2, _, phase_flag, qdss, _, _, _, _, _, _), + PINGROUP(30, EAST, qup2, phase_flag, qdss, _, _, _, _, _, _, _), + PINGROUP(31, NORTH, qup11, qup14, _, _, _, _, _, _, _, _), + PINGROUP(32, NORTH, qup11, qup14, _, _, _, _, _, _, _, _), + PINGROUP(33, NORTH, qup11, qup14, _, _, _, _, _, _, _, _), + PINGROUP(34, NORTH, qup11, qup14, _, _, _, _, _, _, _, _), + PINGROUP(35, SOUTH, pci_e0, qup_l4, jitter_bist, _, _, _, _, _, _, _), + PINGROUP(36, SOUTH, pci_e0, qup_l5, pll_bist, _, atest_tsens, _, _, _, _, _), + PINGROUP(37, SOUTH, qup_l6, agera_pll, _, _, _, _, _, _, _, _), + PINGROUP(38, NORTH, usb_phy, _, _, _, _, _, _, _, _, _), + PINGROUP(39, EAST, lpass_slimbus, _, _, _, _, _, _, _, _, _), + PINGROUP(40, SOUTH, sd_write, tsif1_error, _, _, _, _, _, _, _, _), + PINGROUP(41, EAST, qup3, _, qdss, _, _, _, _, _, _, _), + PINGROUP(42, EAST, qup3, _, qdss, _, _, _, _, _, _, _), + PINGROUP(43, EAST, qup3, _, qdss, _, _, _, _, _, _, _), + PINGROUP(44, EAST, qup3, _, qdss, _, _, _, _, _, _, _), + PINGROUP(45, EAST, qup6, _, _, _, _, _, _, _, _, _), + PINGROUP(46, EAST, qup6, _, _, _, _, _, _, _, _, _), + PINGROUP(47, EAST, qup6, _, _, _, _, _, _, _, _, _), + PINGROUP(48, EAST, qup6, _, _, _, _, _, _, _, _, _), + PINGROUP(49, NORTH, qup12, _, _, _, _, _, _, _, _, _), + PINGROUP(50, NORTH, qup12, _, _, _, _, _, _, _, _, _), + PINGROUP(51, NORTH, qup12, qdss_cti, _, _, _, _, _, _, _, _), + PINGROUP(52, NORTH, qup12, phase_flag, qdss_cti, _, _, _, _, _, _, _), + PINGROUP(53, NORTH, qup10, phase_flag, _, _, _, _, _, _, _, _), + PINGROUP(54, NORTH, qup10, _, phase_flag, _, _, _, _, _, _, _), + PINGROUP(55, NORTH, qup10, phase_flag, _, _, _, _, _, _, _, _), + PINGROUP(56, NORTH, qup10, phase_flag, _, _, _, _, _, _, _, _), + PINGROUP(57, NORTH, qua_mi2s, gcc_gp1, phase_flag, _, _, _, _, _, _, _), + PINGROUP(58, NORTH, qua_mi2s, gcc_gp2, phase_flag, _, _, _, _, _, _, _), + PINGROUP(59, NORTH, qua_mi2s, gcc_gp3, phase_flag, _, _, _, _, _, _, _), + PINGROUP(60, NORTH, qua_mi2s, cri_trng0, phase_flag, _, _, _, _, _, _, _), + PINGROUP(61, NORTH, qua_mi2s, cri_trng1, phase_flag, _, _, _, _, _, _, _), + PINGROUP(62, NORTH, qua_mi2s, cri_trng, phase_flag, qdss_cti, _, _, _, _, _, _), + PINGROUP(63, NORTH, qua_mi2s, _, phase_flag, qdss_cti, _, _, _, _, _, _), + PINGROUP(64, NORTH, pri_mi2s, sp_cmu, phase_flag, _, _, _, _, _, _, _), + PINGROUP(65, NORTH, pri_mi2s, qup8, _, _, _, _, _, _, _, _), + PINGROUP(66, NORTH, pri_mi2s_ws, qup8, _, _, _, _, _, _, _, _), + PINGROUP(67, NORTH, pri_mi2s, qup8, _, _, _, _, _, _, _, _), + PINGROUP(68, NORTH, pri_mi2s, qup8, _, _, _, _, _, _, _, _), + PINGROUP(69, EAST, spkr_i2s, audio_ref, _, _, _, _, _, _, _, _), + PINGROUP(70, EAST, lpass_slimbus, spkr_i2s, _, _, _, _, _, _, _, _), + PINGROUP(71, EAST, lpass_slimbus, spkr_i2s, tsense_pwm1, tsense_pwm2, _, _, _, _, _, _), + PINGROUP(72, EAST, lpass_slimbus, spkr_i2s, _, _, _, _, _, _, _, _), + PINGROUP(73, EAST, btfm_slimbus, atest_usb2, _, _, _, _, _, _, _, _), + PINGROUP(74, EAST, btfm_slimbus, ter_mi2s, phase_flag, atest_usb23, _, _, _, _, _, _), + PINGROUP(75, EAST, ter_mi2s, phase_flag, qdss, atest_usb22, _, _, _, _, _, _), + PINGROUP(76, EAST, ter_mi2s, phase_flag, qdss, atest_usb21, _, _, _, _, _, _), + PINGROUP(77, EAST, ter_mi2s, phase_flag, qdss, atest_usb20, _, _, _, _, _, _), + PINGROUP(78, EAST, ter_mi2s, gcc_gp1, _, _, _, _, _, _, _, _), + PINGROUP(79, NORTH, sec_mi2s, _, _, qdss, _, _, _, _, _, _), + PINGROUP(80, NORTH, sec_mi2s, _, qdss, _, _, _, _, _, _, _), + PINGROUP(81, NORTH, sec_mi2s, qup15, _, _, _, _, _, _, _, _), + PINGROUP(82, NORTH, sec_mi2s, qup15, _, _, _, _, _, _, _, _), + PINGROUP(83, NORTH, sec_mi2s, qup15, _, _, _, _, _, _, _, _), + PINGROUP(84, NORTH, qup15, _, _, _, _, _, _, _, _, _), + PINGROUP(85, EAST, qup5, _, _, _, _, _, _, _, _, _), + PINGROUP(86, EAST, qup5, _, _, _, _, _, _, _, _, _), + PINGROUP(87, EAST, qup5, _, _, _, _, _, _, _, _, _), + PINGROUP(88, EAST, qup5, _, _, _, _, _, _, _, _, _), + PINGROUP(89, SOUTH, tsif1_clk, qup4, qspi_cs, tgu_ch3, phase_flag, _, _, _, _, _), + PINGROUP(90, SOUTH, tsif1_en, mdp_vsync0, qup4, qspi_cs, mdp_vsync1, + mdp_vsync2, mdp_vsync3, tgu_ch0, phase_flag, qdss_cti), + PINGROUP(91, SOUTH, tsif1_data, sdc4_cmd, qup4, qspi_data, tgu_ch1, _, qdss_cti, _, _, _), + PINGROUP(92, SOUTH, tsif2_error, sdc4_data, qup4, qspi_data, vfr_1, tgu_ch2, _, _, _, _), + PINGROUP(93, SOUTH, tsif2_clk, sdc4_clk, qup7, qspi_data, _, qdss, _, _, _, _), + PINGROUP(94, SOUTH, tsif2_en, sdc4_data, qup7, qspi_data, _, _, _, _, _, _), + PINGROUP(95, SOUTH, tsif2_data, sdc4_data, qup7, qspi_clk, _, _, _, _, _, _), + PINGROUP(96, SOUTH, tsif2_sync, sdc4_data, qup7, phase_flag, _, _, _, _, _, _), + PINGROUP(97, NORTH, _, _, mdp_vsync, ldo_en, _, _, _, _, _, _), + PINGROUP(98, NORTH, _, mdp_vsync, ldo_update, _, _, _, _, _, _, _), + PINGROUP(99, NORTH, phase_flag, _, _, _, _, _, _, _, _, _), + PINGROUP(100, NORTH, phase_flag, _, _, _, _, _, _, _, _, _), + PINGROUP(101, NORTH, _, _, _, _, _, _, _, _, _, _), + PINGROUP(102, NORTH, pci_e1, prng_rosc, _, _, _, _, _, _, _, _), + PINGROUP(103, NORTH, pci_e1, phase_flag, _, _, _, _, _, _, _, _), + PINGROUP(104, NORTH, _, _, _, _, _, _, _, _, _, _), + PINGROUP(105, NORTH, uim2_data, qup13, qup_l4, _, _, _, _, _, _, _), + PINGROUP(106, NORTH, uim2_clk, qup13, qup_l5, _, _, _, _, _, _, _), + PINGROUP(107, NORTH, uim2_reset, qup13, qup_l6, _, _, _, _, _, _, _), + PINGROUP(108, NORTH, uim2_present, qup13, _, _, _, _, _, _, _, _), + PINGROUP(109, NORTH, uim1_data, _, _, _, _, _, _, _, _, _), + PINGROUP(110, NORTH, uim1_clk, _, _, _, _, _, _, _, _, _), + PINGROUP(111, NORTH, uim1_reset, _, _, _, _, _, _, _, _, _), + PINGROUP(112, NORTH, uim1_present, _, _, _, _, _, _, _, _, _), + PINGROUP(113, NORTH, uim_batt, edp_hot, _, _, _, _, _, _, _, _), + PINGROUP(114, NORTH, _, nav_pps, nav_pps, _, _, _, _, _, _, _), + PINGROUP(115, NORTH, _, nav_pps, nav_pps, _, _, _, _, _, _, _), + PINGROUP(116, NORTH, _, _, _, _, _, _, _, _, _, _), + PINGROUP(117, NORTH, _, qdss, atest_char, _, _, _, _, _, _, _), + PINGROUP(118, NORTH, adsp_ext, _, qdss, atest_char, _, _, _, _, _, _), + PINGROUP(119, NORTH, _, qdss, atest_char, _, _, _, _, _, _, _), + PINGROUP(120, NORTH, _, qdss, atest_char, _, _, _, _, _, _, _), + PINGROUP(121, NORTH, _, qdss, atest_char, _, _, _, _, _, _, _), + PINGROUP(122, EAST, _, qdss, _, _, _, _, _, _, _, _), + PINGROUP(123, EAST, qup_l4, _, qdss, _, _, _, _, _, _, _), + PINGROUP(124, EAST, qup_l5, _, qdss, _, _, _, _, _, _, _), + PINGROUP(125, EAST, qup_l6, _, _, _, _, _, _, _, _, _), + PINGROUP(126, EAST, _, _, _, _, _, _, _, _, _, _), + PINGROUP(127, NORTH, _, _, _, _, _, _, _, _, _, _), + PINGROUP(128, NORTH, nav_pps, nav_pps, _, _, _, _, _, _, _, _), + PINGROUP(129, NORTH, nav_pps, nav_pps, _, _, _, _, _, _, _, _), + PINGROUP(130, NORTH, qlink_request, _, _, _, _, _, _, _, _, _), + PINGROUP(131, NORTH, qlink_enable, _, _, _, _, _, _, _, _, _), + PINGROUP(132, NORTH, _, _, _, _, _, _, _, _, _, _), + PINGROUP(133, NORTH, _, _, _, _, _, _, _, _, _, _), + PINGROUP(134, NORTH, _, _, _, _, _, _, _, _, _, _), + PINGROUP(135, NORTH, _, pa_indicator, _, _, _, _, _, _, _, _), + PINGROUP(136, NORTH, _, _, _, _, _, _, _, _, _, _), + PINGROUP(137, NORTH, _, _, phase_flag, _, _, _, _, _, _, _), + PINGROUP(138, NORTH, _, _, phase_flag, _, _, _, _, _, _, _), + PINGROUP(139, NORTH, _, phase_flag, _, _, _, _, _, _, _, _), + PINGROUP(140, NORTH, _, _, phase_flag, _, _, _, _, _, _, _), + PINGROUP(141, NORTH, _, phase_flag, _, _, _, _, _, _, _, _), + PINGROUP(142, NORTH, _, phase_flag, _, _, _, _, _, _, _, _), + PINGROUP(143, NORTH, _, nav_pps, nav_pps, _, phase_flag, _, _, _, _, _), + PINGROUP(144, NORTH, mss_lte, _, _, _, _, _, _, _, _, _), + PINGROUP(145, NORTH, mss_lte, _, _, _, _, _, _, _, _, _), + PINGROUP(146, NORTH, _, _, _, _, _, _, _, _, _, _), + PINGROUP(147, NORTH, _, _, _, _, _, _, _, _, _, _), + PINGROUP(148, NORTH, _, _, _, _, _, _, _, _, _, _), + PINGROUP(149, NORTH, _, _, _, _, _, _, _, _, _, _), + UFS_RESET(ufs_reset, 0x99f000), + SDC_QDSD_PINGROUP(sdc2_clk, 0x99a000, 14, 6), + SDC_QDSD_PINGROUP(sdc2_cmd, 0x99a000, 11, 3), + SDC_QDSD_PINGROUP(sdc2_data, 0x99a000, 9, 0), +}; + +static const int sdm845_acpi_reserved_gpios[] = { + 0, 1, 2, 3, 81, 82, 83, 84, -1 +}; + +static const struct msm_gpio_wakeirq_map sdm845_pdc_map[] = { + { 1, 30 }, { 3, 31 }, { 5, 32 }, { 10, 33 }, { 11, 34 }, + { 20, 35 }, { 22, 36 }, { 24, 37 }, { 26, 38 }, { 30, 39 }, + { 31, 117 }, { 32, 41 }, { 34, 42 }, { 36, 43 }, { 37, 44 }, + { 38, 45 }, { 39, 46 }, { 40, 47 }, { 41, 115 }, { 43, 49 }, + { 44, 50 }, { 46, 51 }, { 48, 52 }, { 49, 118 }, { 52, 54 }, + { 53, 55 }, { 54, 56 }, { 56, 57 }, { 57, 58 }, { 58, 59 }, + { 59, 60 }, { 60, 61 }, { 61, 62 }, { 62, 63 }, { 63, 64 }, + { 64, 65 }, { 66, 66 }, { 68, 67 }, { 71, 68 }, { 73, 69 }, + { 77, 70 }, { 78, 71 }, { 79, 72 }, { 80, 73 }, { 84, 74 }, + { 85, 75 }, { 86, 76 }, { 88, 77 }, { 89, 116 }, { 91, 79 }, + { 92, 80 }, { 95, 81 }, { 96, 82 }, { 97, 83 }, { 101, 84 }, + { 103, 85 }, { 104, 86 }, { 115, 90 }, { 116, 91 }, { 117, 92 }, + { 118, 93 }, { 119, 94 }, { 120, 95 }, { 121, 96 }, { 122, 97 }, + { 123, 98 }, { 124, 99 }, { 125, 100 }, { 127, 102 }, { 128, 103 }, + { 129, 104 }, { 130, 105 }, { 132, 106 }, { 133, 107 }, { 145, 108 }, +}; + +static const struct msm_pinctrl_soc_data sdm845_pinctrl = { + .pins = sdm845_pins, + .npins = ARRAY_SIZE(sdm845_pins), + .functions = sdm845_functions, + .nfunctions = ARRAY_SIZE(sdm845_functions), + .groups = sdm845_groups, + .ngroups = ARRAY_SIZE(sdm845_groups), + .ngpios = 151, + .wakeirq_map = sdm845_pdc_map, + .nwakeirq_map = ARRAY_SIZE(sdm845_pdc_map), + .wakeirq_dual_edge_errata = true, +}; + +static const struct msm_pinctrl_soc_data sdm845_acpi_pinctrl = { + .pins = sdm845_pins, + .npins = ARRAY_SIZE(sdm845_pins), + .groups = sdm845_groups, + .ngroups = ARRAY_SIZE(sdm845_groups), + .reserved_gpios = sdm845_acpi_reserved_gpios, + .ngpios = 150, +}; + +static int sdm845_pinctrl_probe(struct platform_device *pdev) +{ + int ret; + + if (pdev->dev.of_node) { + ret = msm_pinctrl_probe(pdev, &sdm845_pinctrl); + } else if (has_acpi_companion(&pdev->dev)) { + ret = msm_pinctrl_probe(pdev, &sdm845_acpi_pinctrl); + } else { + dev_err(&pdev->dev, "DT and ACPI disabled\n"); + return -EINVAL; + } + + return ret; +} + +#ifdef CONFIG_ACPI +static const struct acpi_device_id sdm845_pinctrl_acpi_match[] = { + { "QCOM0217"}, + { }, +}; +MODULE_DEVICE_TABLE(acpi, sdm845_pinctrl_acpi_match); +#endif + +static const struct of_device_id sdm845_pinctrl_of_match[] = { + { .compatible = "qcom,sdm845-pinctrl", }, + { }, +}; + +static struct platform_driver sdm845_pinctrl_driver = { + .driver = { + .name = "sdm845-pinctrl", + .pm = &msm_pinctrl_dev_pm_ops, + .of_match_table = sdm845_pinctrl_of_match, + .acpi_match_table = ACPI_PTR(sdm845_pinctrl_acpi_match), + }, + .probe = sdm845_pinctrl_probe, + .remove = msm_pinctrl_remove, +}; + +static int __init sdm845_pinctrl_init(void) +{ + return platform_driver_register(&sdm845_pinctrl_driver); +} +arch_initcall(sdm845_pinctrl_init); + +static void __exit sdm845_pinctrl_exit(void) +{ + platform_driver_unregister(&sdm845_pinctrl_driver); +} +module_exit(sdm845_pinctrl_exit); + +MODULE_DESCRIPTION("QTI sdm845 pinctrl driver"); +MODULE_LICENSE("GPL v2"); +MODULE_DEVICE_TABLE(of, sdm845_pinctrl_of_match); diff --git a/drivers/pinctrl/qcom/pinctrl-sdx55.c b/drivers/pinctrl/qcom/pinctrl-sdx55.c new file mode 100644 index 0000000000..8826db9d21 --- /dev/null +++ b/drivers/pinctrl/qcom/pinctrl-sdx55.c @@ -0,0 +1,1010 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2018-2020, The Linux Foundation. All rights reserved. + */ + +#include <linux/module.h> +#include <linux/of.h> +#include <linux/platform_device.h> + +#include "pinctrl-msm.h" + +#define REG_SIZE 0x1000 + +#define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7, f8, f9) \ + { \ + .grp = PINCTRL_PINGROUP("gpio" #id, \ + gpio##id##_pins, \ + ARRAY_SIZE(gpio##id##_pins)), \ + .funcs = (int[]){ \ + msm_mux_gpio, /* gpio mode */ \ + msm_mux_##f1, \ + msm_mux_##f2, \ + msm_mux_##f3, \ + msm_mux_##f4, \ + msm_mux_##f5, \ + msm_mux_##f6, \ + msm_mux_##f7, \ + msm_mux_##f8, \ + msm_mux_##f9 \ + }, \ + .nfuncs = 10, \ + .ctl_reg = REG_SIZE * id, \ + .io_reg = 0x4 + REG_SIZE * id, \ + .intr_cfg_reg = 0x8 + REG_SIZE * id, \ + .intr_status_reg = 0xc + REG_SIZE * id, \ + .intr_target_reg = 0x8 + REG_SIZE * id, \ + .mux_bit = 2, \ + .pull_bit = 0, \ + .drv_bit = 6, \ + .oe_bit = 9, \ + .in_bit = 0, \ + .out_bit = 1, \ + .intr_enable_bit = 0, \ + .intr_status_bit = 0, \ + .intr_target_bit = 5, \ + .intr_target_kpss_val = 3, \ + .intr_raw_status_bit = 4, \ + .intr_polarity_bit = 1, \ + .intr_detection_bit = 2, \ + .intr_detection_width = 2, \ + } + +#define SDC_PINGROUP(pg_name, ctl, pull, drv) \ + { \ + .grp = PINCTRL_PINGROUP(#pg_name, \ + pg_name##_pins, \ + ARRAY_SIZE(pg_name##_pins)), \ + .ctl_reg = ctl, \ + .io_reg = 0, \ + .intr_cfg_reg = 0, \ + .intr_status_reg = 0, \ + .intr_target_reg = 0, \ + .mux_bit = -1, \ + .pull_bit = pull, \ + .drv_bit = drv, \ + .oe_bit = -1, \ + .in_bit = -1, \ + .out_bit = -1, \ + .intr_enable_bit = -1, \ + .intr_status_bit = -1, \ + .intr_target_bit = -1, \ + .intr_raw_status_bit = -1, \ + .intr_polarity_bit = -1, \ + .intr_detection_bit = -1, \ + .intr_detection_width = -1, \ + } + +static const struct pinctrl_pin_desc sdx55_pins[] = { + PINCTRL_PIN(0, "GPIO_0"), + PINCTRL_PIN(1, "GPIO_1"), + PINCTRL_PIN(2, "GPIO_2"), + PINCTRL_PIN(3, "GPIO_3"), + PINCTRL_PIN(4, "GPIO_4"), + PINCTRL_PIN(5, "GPIO_5"), + PINCTRL_PIN(6, "GPIO_6"), + PINCTRL_PIN(7, "GPIO_7"), + PINCTRL_PIN(8, "GPIO_8"), + PINCTRL_PIN(9, "GPIO_9"), + PINCTRL_PIN(10, "GPIO_10"), + PINCTRL_PIN(11, "GPIO_11"), + PINCTRL_PIN(12, "GPIO_12"), + PINCTRL_PIN(13, "GPIO_13"), + PINCTRL_PIN(14, "GPIO_14"), + PINCTRL_PIN(15, "GPIO_15"), + PINCTRL_PIN(16, "GPIO_16"), + PINCTRL_PIN(17, "GPIO_17"), + PINCTRL_PIN(18, "GPIO_18"), + PINCTRL_PIN(19, "GPIO_19"), + PINCTRL_PIN(20, "GPIO_20"), + PINCTRL_PIN(21, "GPIO_21"), + PINCTRL_PIN(22, "GPIO_22"), + PINCTRL_PIN(23, "GPIO_23"), + PINCTRL_PIN(24, "GPIO_24"), + PINCTRL_PIN(25, "GPIO_25"), + PINCTRL_PIN(26, "GPIO_26"), + PINCTRL_PIN(27, "GPIO_27"), + PINCTRL_PIN(28, "GPIO_28"), + PINCTRL_PIN(29, "GPIO_29"), + PINCTRL_PIN(30, "GPIO_30"), + PINCTRL_PIN(31, "GPIO_31"), + PINCTRL_PIN(32, "GPIO_32"), + PINCTRL_PIN(33, "GPIO_33"), + PINCTRL_PIN(34, "GPIO_34"), + PINCTRL_PIN(35, "GPIO_35"), + PINCTRL_PIN(36, "GPIO_36"), + PINCTRL_PIN(37, "GPIO_37"), + PINCTRL_PIN(38, "GPIO_38"), + PINCTRL_PIN(39, "GPIO_39"), + PINCTRL_PIN(40, "GPIO_40"), + PINCTRL_PIN(41, "GPIO_41"), + PINCTRL_PIN(42, "GPIO_42"), + PINCTRL_PIN(43, "GPIO_43"), + PINCTRL_PIN(44, "GPIO_44"), + PINCTRL_PIN(45, "GPIO_45"), + PINCTRL_PIN(46, "GPIO_46"), + PINCTRL_PIN(47, "GPIO_47"), + PINCTRL_PIN(48, "GPIO_48"), + PINCTRL_PIN(49, "GPIO_49"), + PINCTRL_PIN(50, "GPIO_50"), + PINCTRL_PIN(51, "GPIO_51"), + PINCTRL_PIN(52, "GPIO_52"), + PINCTRL_PIN(53, "GPIO_53"), + PINCTRL_PIN(54, "GPIO_54"), + PINCTRL_PIN(55, "GPIO_55"), + PINCTRL_PIN(56, "GPIO_56"), + PINCTRL_PIN(57, "GPIO_57"), + PINCTRL_PIN(58, "GPIO_58"), + PINCTRL_PIN(59, "GPIO_59"), + PINCTRL_PIN(60, "GPIO_60"), + PINCTRL_PIN(61, "GPIO_61"), + PINCTRL_PIN(62, "GPIO_62"), + PINCTRL_PIN(63, "GPIO_63"), + PINCTRL_PIN(64, "GPIO_64"), + PINCTRL_PIN(65, "GPIO_65"), + PINCTRL_PIN(66, "GPIO_66"), + PINCTRL_PIN(67, "GPIO_67"), + PINCTRL_PIN(68, "GPIO_68"), + PINCTRL_PIN(69, "GPIO_69"), + PINCTRL_PIN(70, "GPIO_70"), + PINCTRL_PIN(71, "GPIO_71"), + PINCTRL_PIN(72, "GPIO_72"), + PINCTRL_PIN(73, "GPIO_73"), + PINCTRL_PIN(74, "GPIO_74"), + PINCTRL_PIN(75, "GPIO_75"), + PINCTRL_PIN(76, "GPIO_76"), + PINCTRL_PIN(77, "GPIO_77"), + PINCTRL_PIN(78, "GPIO_78"), + PINCTRL_PIN(79, "GPIO_79"), + PINCTRL_PIN(80, "GPIO_80"), + PINCTRL_PIN(81, "GPIO_81"), + PINCTRL_PIN(82, "GPIO_82"), + PINCTRL_PIN(83, "GPIO_83"), + PINCTRL_PIN(84, "GPIO_84"), + PINCTRL_PIN(85, "GPIO_85"), + PINCTRL_PIN(86, "GPIO_86"), + PINCTRL_PIN(87, "GPIO_87"), + PINCTRL_PIN(88, "GPIO_88"), + PINCTRL_PIN(89, "GPIO_89"), + PINCTRL_PIN(90, "GPIO_90"), + PINCTRL_PIN(91, "GPIO_91"), + PINCTRL_PIN(92, "GPIO_92"), + PINCTRL_PIN(93, "GPIO_93"), + PINCTRL_PIN(94, "GPIO_94"), + PINCTRL_PIN(95, "GPIO_95"), + PINCTRL_PIN(96, "GPIO_96"), + PINCTRL_PIN(97, "GPIO_97"), + PINCTRL_PIN(98, "GPIO_98"), + PINCTRL_PIN(99, "GPIO_99"), + PINCTRL_PIN(100, "GPIO_100"), + PINCTRL_PIN(101, "GPIO_101"), + PINCTRL_PIN(102, "GPIO_102"), + PINCTRL_PIN(103, "GPIO_103"), + PINCTRL_PIN(104, "GPIO_104"), + PINCTRL_PIN(105, "GPIO_105"), + PINCTRL_PIN(106, "GPIO_106"), + PINCTRL_PIN(107, "GPIO_107"), + PINCTRL_PIN(108, "SDC1_RCLK"), + PINCTRL_PIN(109, "SDC1_CLK"), + PINCTRL_PIN(110, "SDC1_CMD"), + PINCTRL_PIN(111, "SDC1_DATA"), +}; + +#define DECLARE_MSM_GPIO_PINS(pin) \ + static const unsigned int gpio##pin##_pins[] = { pin } +DECLARE_MSM_GPIO_PINS(0); +DECLARE_MSM_GPIO_PINS(1); +DECLARE_MSM_GPIO_PINS(2); +DECLARE_MSM_GPIO_PINS(3); +DECLARE_MSM_GPIO_PINS(4); +DECLARE_MSM_GPIO_PINS(5); +DECLARE_MSM_GPIO_PINS(6); +DECLARE_MSM_GPIO_PINS(7); +DECLARE_MSM_GPIO_PINS(8); +DECLARE_MSM_GPIO_PINS(9); +DECLARE_MSM_GPIO_PINS(10); +DECLARE_MSM_GPIO_PINS(11); +DECLARE_MSM_GPIO_PINS(12); +DECLARE_MSM_GPIO_PINS(13); +DECLARE_MSM_GPIO_PINS(14); +DECLARE_MSM_GPIO_PINS(15); +DECLARE_MSM_GPIO_PINS(16); +DECLARE_MSM_GPIO_PINS(17); +DECLARE_MSM_GPIO_PINS(18); +DECLARE_MSM_GPIO_PINS(19); +DECLARE_MSM_GPIO_PINS(20); +DECLARE_MSM_GPIO_PINS(21); +DECLARE_MSM_GPIO_PINS(22); +DECLARE_MSM_GPIO_PINS(23); +DECLARE_MSM_GPIO_PINS(24); +DECLARE_MSM_GPIO_PINS(25); +DECLARE_MSM_GPIO_PINS(26); +DECLARE_MSM_GPIO_PINS(27); +DECLARE_MSM_GPIO_PINS(28); +DECLARE_MSM_GPIO_PINS(29); +DECLARE_MSM_GPIO_PINS(30); +DECLARE_MSM_GPIO_PINS(31); +DECLARE_MSM_GPIO_PINS(32); +DECLARE_MSM_GPIO_PINS(33); +DECLARE_MSM_GPIO_PINS(34); +DECLARE_MSM_GPIO_PINS(35); +DECLARE_MSM_GPIO_PINS(36); +DECLARE_MSM_GPIO_PINS(37); +DECLARE_MSM_GPIO_PINS(38); +DECLARE_MSM_GPIO_PINS(39); +DECLARE_MSM_GPIO_PINS(40); +DECLARE_MSM_GPIO_PINS(41); +DECLARE_MSM_GPIO_PINS(42); +DECLARE_MSM_GPIO_PINS(43); +DECLARE_MSM_GPIO_PINS(44); +DECLARE_MSM_GPIO_PINS(45); +DECLARE_MSM_GPIO_PINS(46); +DECLARE_MSM_GPIO_PINS(47); +DECLARE_MSM_GPIO_PINS(48); +DECLARE_MSM_GPIO_PINS(49); +DECLARE_MSM_GPIO_PINS(50); +DECLARE_MSM_GPIO_PINS(51); +DECLARE_MSM_GPIO_PINS(52); +DECLARE_MSM_GPIO_PINS(53); +DECLARE_MSM_GPIO_PINS(54); +DECLARE_MSM_GPIO_PINS(55); +DECLARE_MSM_GPIO_PINS(56); +DECLARE_MSM_GPIO_PINS(57); +DECLARE_MSM_GPIO_PINS(58); +DECLARE_MSM_GPIO_PINS(59); +DECLARE_MSM_GPIO_PINS(60); +DECLARE_MSM_GPIO_PINS(61); +DECLARE_MSM_GPIO_PINS(62); +DECLARE_MSM_GPIO_PINS(63); +DECLARE_MSM_GPIO_PINS(64); +DECLARE_MSM_GPIO_PINS(65); +DECLARE_MSM_GPIO_PINS(66); +DECLARE_MSM_GPIO_PINS(67); +DECLARE_MSM_GPIO_PINS(68); +DECLARE_MSM_GPIO_PINS(69); +DECLARE_MSM_GPIO_PINS(70); +DECLARE_MSM_GPIO_PINS(71); +DECLARE_MSM_GPIO_PINS(72); +DECLARE_MSM_GPIO_PINS(73); +DECLARE_MSM_GPIO_PINS(74); +DECLARE_MSM_GPIO_PINS(75); +DECLARE_MSM_GPIO_PINS(76); +DECLARE_MSM_GPIO_PINS(77); +DECLARE_MSM_GPIO_PINS(78); +DECLARE_MSM_GPIO_PINS(79); +DECLARE_MSM_GPIO_PINS(80); +DECLARE_MSM_GPIO_PINS(81); +DECLARE_MSM_GPIO_PINS(82); +DECLARE_MSM_GPIO_PINS(83); +DECLARE_MSM_GPIO_PINS(84); +DECLARE_MSM_GPIO_PINS(85); +DECLARE_MSM_GPIO_PINS(86); +DECLARE_MSM_GPIO_PINS(87); +DECLARE_MSM_GPIO_PINS(88); +DECLARE_MSM_GPIO_PINS(89); +DECLARE_MSM_GPIO_PINS(90); +DECLARE_MSM_GPIO_PINS(91); +DECLARE_MSM_GPIO_PINS(92); +DECLARE_MSM_GPIO_PINS(93); +DECLARE_MSM_GPIO_PINS(94); +DECLARE_MSM_GPIO_PINS(95); +DECLARE_MSM_GPIO_PINS(96); +DECLARE_MSM_GPIO_PINS(97); +DECLARE_MSM_GPIO_PINS(98); +DECLARE_MSM_GPIO_PINS(99); +DECLARE_MSM_GPIO_PINS(100); +DECLARE_MSM_GPIO_PINS(101); +DECLARE_MSM_GPIO_PINS(102); +DECLARE_MSM_GPIO_PINS(103); +DECLARE_MSM_GPIO_PINS(104); +DECLARE_MSM_GPIO_PINS(105); +DECLARE_MSM_GPIO_PINS(106); +DECLARE_MSM_GPIO_PINS(107); + +static const unsigned int sdc1_rclk_pins[] = { 108 }; +static const unsigned int sdc1_clk_pins[] = { 109 }; +static const unsigned int sdc1_cmd_pins[] = { 110 }; +static const unsigned int sdc1_data_pins[] = { 111 }; + +enum sdx55_functions { + msm_mux_adsp_ext, + msm_mux_atest, + msm_mux_audio_ref, + msm_mux_bimc_dte0, + msm_mux_bimc_dte1, + msm_mux_blsp_i2c1, + msm_mux_blsp_i2c2, + msm_mux_blsp_i2c3, + msm_mux_blsp_i2c4, + msm_mux_blsp_spi1, + msm_mux_blsp_spi2, + msm_mux_blsp_spi3, + msm_mux_blsp_spi4, + msm_mux_blsp_uart1, + msm_mux_blsp_uart2, + msm_mux_blsp_uart3, + msm_mux_blsp_uart4, + msm_mux_char_exec, + msm_mux_coex_uart, + msm_mux_coex_uart2, + msm_mux_cri_trng, + msm_mux_cri_trng0, + msm_mux_cri_trng1, + msm_mux_dbg_out, + msm_mux_ddr_bist, + msm_mux_ddr_pxi0, + msm_mux_ebi0_wrcdc, + msm_mux_ebi2_a, + msm_mux_ebi2_lcd, + msm_mux_emac_gcc0, + msm_mux_emac_gcc1, + msm_mux_emac_pps0, + msm_mux_emac_pps1, + msm_mux_ext_dbg, + msm_mux_gcc_gp1, + msm_mux_gcc_gp2, + msm_mux_gcc_gp3, + msm_mux_gcc_plltest, + msm_mux_gpio, + msm_mux_i2s_mclk, + msm_mux_jitter_bist, + msm_mux_ldo_en, + msm_mux_ldo_update, + msm_mux_mgpi_clk, + msm_mux_m_voc, + msm_mux_native_char, + msm_mux_native_char0, + msm_mux_native_char1, + msm_mux_native_char2, + msm_mux_native_char3, + msm_mux_native_tsens, + msm_mux_native_tsense, + msm_mux_nav_gpio, + msm_mux_pa_indicator, + msm_mux_pcie_clkreq, + msm_mux_pci_e, + msm_mux_pll_bist, + msm_mux_pll_ref, + msm_mux_pll_test, + msm_mux_pri_mi2s, + msm_mux_prng_rosc, + msm_mux_qdss_cti, + msm_mux_qdss_gpio, + msm_mux_qdss_stm, + msm_mux_qlink0_en, + msm_mux_qlink0_req, + msm_mux_qlink0_wmss, + msm_mux_qlink1_en, + msm_mux_qlink1_req, + msm_mux_qlink1_wmss, + msm_mux_spmi_coex, + msm_mux_sec_mi2s, + msm_mux_spmi_vgi, + msm_mux_tgu_ch0, + msm_mux_uim1_clk, + msm_mux_uim1_data, + msm_mux_uim1_present, + msm_mux_uim1_reset, + msm_mux_uim2_clk, + msm_mux_uim2_data, + msm_mux_uim2_present, + msm_mux_uim2_reset, + msm_mux_usb2phy_ac, + msm_mux_vsense_trigger, + msm_mux__, +}; + +static const char * const gpio_groups[] = { + "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7", + "gpio8", "gpio9", "gpio10", "gpio11", "gpio12", "gpio13", "gpio14", + "gpio15", "gpio16", "gpio17", "gpio18", "gpio19", "gpio20", "gpio21", + "gpio22", "gpio23", "gpio24", "gpio25", "gpio26", "gpio27", "gpio28", + "gpio29", "gpio30", "gpio31", "gpio32", "gpio33", "gpio34", "gpio35", + "gpio36", "gpio37", "gpio38", "gpio39", "gpio40", "gpio41", "gpio42", + "gpio43", "gpio44", "gpio45", "gpio46", "gpio47", "gpio48", "gpio49", + "gpio50", "gpio51", "gpio52", "gpio53", "gpio54", "gpio55", "gpio56", + "gpio57", "gpio58", "gpio59", "gpio60", "gpio61", "gpio62", "gpio63", + "gpio64", "gpio65", "gpio66", "gpio67", "gpio68", "gpio69", "gpio70", + "gpio71", "gpio72", "gpio73", "gpio74", "gpio75", "gpio76", "gpio77", + "gpio78", "gpio79", "gpio80", "gpio81", "gpio82", "gpio83", "gpio84", + "gpio85", "gpio86", "gpio87", "gpio88", "gpio89", "gpio90", "gpio91", + "gpio92", "gpio93", "gpio94", "gpio95", "gpio96", "gpio97", "gpio98", + "gpio99", "gpio100", "gpio101", "gpio102", "gpio103", "gpio104", + "gpio105", "gpio106", "gpio107", +}; + +static const char * const qdss_stm_groups[] = { + "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7", "gpio12", "gpio13", + "gpio14", "gpio15", "gpio16", "gpio17", "gpio18", "gpio19", "gpio20", "gpio21", "gpio22", + "gpio23", "gpio44", "gpio45", "gpio52", "gpio53", "gpio56", "gpio57", "gpio61", "gpio62", + "gpio63", "gpio64", "gpio65", "gpio66", +}; + +static const char * const ddr_pxi0_groups[] = { + "gpio45", "gpio46", +}; + +static const char * const m_voc_groups[] = { + "gpio46", "gpio48", "gpio49", "gpio59", "gpio60", +}; + +static const char * const ddr_bist_groups[] = { + "gpio46", "gpio47", "gpio48", "gpio49", +}; + +static const char * const blsp_spi1_groups[] = { + "gpio52", "gpio62", "gpio71", "gpio80", "gpio81", "gpio82", "gpio83", +}; + +static const char * const pci_e_groups[] = { + "gpio53", +}; + +static const char * const tgu_ch0_groups[] = { + "gpio55", +}; + +static const char * const pcie_clkreq_groups[] = { + "gpio56", +}; + +static const char * const mgpi_clk_groups[] = { + "gpio61", "gpio71", +}; + +static const char * const i2s_mclk_groups[] = { + "gpio62", +}; + +static const char * const audio_ref_groups[] = { + "gpio62", +}; + +static const char * const ldo_update_groups[] = { + "gpio62", +}; + +static const char * const atest_groups[] = { + "gpio63", "gpio64", "gpio65", "gpio66", "gpio67", +}; + +static const char * const uim1_data_groups[] = { + "gpio67", +}; + +static const char * const uim1_present_groups[] = { + "gpio68", +}; + +static const char * const uim1_reset_groups[] = { + "gpio69", +}; + +static const char * const uim1_clk_groups[] = { + "gpio70", +}; + +static const char * const qlink1_en_groups[] = { + "gpio72", +}; + +static const char * const qlink1_req_groups[] = { + "gpio73", +}; + +static const char * const qlink1_wmss_groups[] = { + "gpio74", +}; + +static const char * const coex_uart2_groups[] = { + "gpio75", "gpio76", +}; + +static const char * const spmi_vgi_groups[] = { + "gpio78", "gpio79", +}; + +static const char * const gcc_plltest_groups[] = { + "gpio81", "gpio82", +}; + +static const char * const usb2phy_ac_groups[] = { + "gpio93", +}; + +static const char * const emac_pps1_groups[] = { + "gpio95", +}; + +static const char * const emac_pps0_groups[] = { + "gpio106", +}; + +static const char * const uim2_data_groups[] = { + "gpio0", +}; + +static const char * const ebi0_wrcdc_groups[] = { + "gpio0", "gpio2", +}; + +static const char * const uim2_present_groups[] = { + "gpio1", +}; + +static const char * const blsp_uart1_groups[] = { + "gpio0", "gpio1", "gpio2", "gpio3", "gpio20", "gpio21", "gpio22", + "gpio23", +}; + +static const char * const uim2_reset_groups[] = { + "gpio2", +}; + +static const char * const blsp_i2c1_groups[] = { + "gpio2", "gpio3", "gpio82", "gpio83", +}; + +static const char * const uim2_clk_groups[] = { + "gpio3", +}; + +static const char * const blsp_spi2_groups[] = { + "gpio4", "gpio5", "gpio6", "gpio7", "gpio52", "gpio62", "gpio71", +}; + +static const char * const blsp_uart2_groups[] = { + "gpio4", "gpio5", "gpio6", "gpio7", "gpio63", "gpio64", "gpio65", + "gpio66", +}; + +static const char * const blsp_i2c2_groups[] = { + "gpio6", "gpio7", "gpio65", "gpio66", +}; + +static const char * const char_exec_groups[] = { + "gpio6", "gpio7", +}; + +static const char * const pri_mi2s_groups[] = { + "gpio8", "gpio9", "gpio10", "gpio11", "gpio12", "gpio13", "gpio14", + "gpio15", +}; + +static const char * const blsp_spi3_groups[] = { + "gpio8", "gpio9", "gpio10", "gpio11", "gpio52", "gpio62", "gpio71", +}; + +static const char * const blsp_uart3_groups[] = { + "gpio8", "gpio9", "gpio10", "gpio11", +}; + +static const char * const ext_dbg_groups[] = { + "gpio8", "gpio9", "gpio10", "gpio11", +}; + +static const char * const ldo_en_groups[] = { + "gpio8", +}; + +static const char * const blsp_i2c3_groups[] = { + "gpio10", "gpio11", +}; + +static const char * const gcc_gp3_groups[] = { + "gpio11", +}; + +static const char * const emac_gcc1_groups[] = { + "gpio14", +}; + +static const char * const bimc_dte0_groups[] = { + "gpio14", "gpio59", +}; + +static const char * const native_tsens_groups[] = { + "gpio14", +}; + +static const char * const vsense_trigger_groups[] = { + "gpio14", +}; + +static const char * const emac_gcc0_groups[] = { + "gpio15", +}; + +static const char * const bimc_dte1_groups[] = { + "gpio15", "gpio61", +}; + +static const char * const sec_mi2s_groups[] = { + "gpio16", "gpio17", "gpio18", "gpio19", "gpio20", "gpio21", "gpio22", + "gpio23", +}; + +static const char * const blsp_spi4_groups[] = { + "gpio16", "gpio17", "gpio18", "gpio19", "gpio52", "gpio62", "gpio71", +}; + +static const char * const blsp_uart4_groups[] = { + "gpio16", "gpio17", "gpio18", "gpio19", "gpio20", "gpio21", "gpio22", + "gpio23", +}; + +static const char * const qdss_cti_groups[] = { + "gpio16", "gpio16", "gpio17", "gpio17", "gpio22", "gpio22", "gpio23", + "gpio23", "gpio54", "gpio54", "gpio55", "gpio55", "gpio59", "gpio60", + "gpio94", "gpio94", "gpio95", "gpio95", +}; + +static const char * const blsp_i2c4_groups[] = { + "gpio18", "gpio19", "gpio78", "gpio79", +}; + +static const char * const gcc_gp1_groups[] = { + "gpio18", +}; + +static const char * const jitter_bist_groups[] = { + "gpio19", +}; + +static const char * const gcc_gp2_groups[] = { + "gpio19", +}; + +static const char * const ebi2_a_groups[] = { + "gpio20", +}; + +static const char * const ebi2_lcd_groups[] = { + "gpio21", "gpio22", "gpio23", +}; + +static const char * const pll_bist_groups[] = { + "gpio22", +}; + +static const char * const adsp_ext_groups[] = { + "gpio24", "gpio25", +}; + +static const char * const native_char_groups[] = { + "gpio26", +}; + +static const char * const qlink0_wmss_groups[] = { + "gpio28", +}; + +static const char * const native_char3_groups[] = { + "gpio28", +}; + +static const char * const native_char2_groups[] = { + "gpio29", +}; + +static const char * const native_tsense_groups[] = { + "gpio29", +}; + +static const char * const nav_gpio_groups[] = { + "gpio31", "gpio32", "gpio76", +}; + +static const char * const pll_ref_groups[] = { + "gpio32", +}; + +static const char * const pa_indicator_groups[] = { + "gpio33", +}; + +static const char * const native_char0_groups[] = { + "gpio33", +}; + +static const char * const qlink0_en_groups[] = { + "gpio34", +}; + +static const char * const qlink0_req_groups[] = { + "gpio35", +}; + +static const char * const pll_test_groups[] = { + "gpio35", +}; + +static const char * const cri_trng_groups[] = { + "gpio36", +}; + +static const char * const dbg_out_groups[] = { + "gpio36", +}; + +static const char * const prng_rosc_groups[] = { + "gpio38", +}; + +static const char * const cri_trng0_groups[] = { + "gpio40", +}; + +static const char * const cri_trng1_groups[] = { + "gpio41", +}; + +static const char * const qdss_gpio_groups[] = { + "gpio4", "gpio5", "gpio6", "gpio7", + "gpio12", "gpio13", "gpio14", "gpio15", "gpio16", "gpio17", "gpio18", "gpio19", + "gpio42", "gpio61", "gpio63", "gpio64", "gpio65", "gpio66", +}; + +static const char * const native_char1_groups[] = { + "gpio42", +}; + +static const char * const coex_uart_groups[] = { + "gpio44", "gpio45", +}; + +static const char * const spmi_coex_groups[] = { + "gpio44", "gpio45", +}; + +static const struct pinfunction sdx55_functions[] = { + MSM_PIN_FUNCTION(adsp_ext), + MSM_PIN_FUNCTION(atest), + MSM_PIN_FUNCTION(audio_ref), + MSM_PIN_FUNCTION(bimc_dte0), + MSM_PIN_FUNCTION(bimc_dte1), + MSM_PIN_FUNCTION(blsp_i2c1), + MSM_PIN_FUNCTION(blsp_i2c2), + MSM_PIN_FUNCTION(blsp_i2c3), + MSM_PIN_FUNCTION(blsp_i2c4), + MSM_PIN_FUNCTION(blsp_spi1), + MSM_PIN_FUNCTION(blsp_spi2), + MSM_PIN_FUNCTION(blsp_spi3), + MSM_PIN_FUNCTION(blsp_spi4), + MSM_PIN_FUNCTION(blsp_uart1), + MSM_PIN_FUNCTION(blsp_uart2), + MSM_PIN_FUNCTION(blsp_uart3), + MSM_PIN_FUNCTION(blsp_uart4), + MSM_PIN_FUNCTION(char_exec), + MSM_PIN_FUNCTION(coex_uart), + MSM_PIN_FUNCTION(coex_uart2), + MSM_PIN_FUNCTION(cri_trng), + MSM_PIN_FUNCTION(cri_trng0), + MSM_PIN_FUNCTION(cri_trng1), + MSM_PIN_FUNCTION(dbg_out), + MSM_PIN_FUNCTION(ddr_bist), + MSM_PIN_FUNCTION(ddr_pxi0), + MSM_PIN_FUNCTION(ebi0_wrcdc), + MSM_PIN_FUNCTION(ebi2_a), + MSM_PIN_FUNCTION(ebi2_lcd), + MSM_PIN_FUNCTION(emac_gcc0), + MSM_PIN_FUNCTION(emac_gcc1), + MSM_PIN_FUNCTION(emac_pps0), + MSM_PIN_FUNCTION(emac_pps1), + MSM_PIN_FUNCTION(ext_dbg), + MSM_PIN_FUNCTION(gcc_gp1), + MSM_PIN_FUNCTION(gcc_gp2), + MSM_PIN_FUNCTION(gcc_gp3), + MSM_PIN_FUNCTION(gcc_plltest), + MSM_PIN_FUNCTION(gpio), + MSM_PIN_FUNCTION(i2s_mclk), + MSM_PIN_FUNCTION(jitter_bist), + MSM_PIN_FUNCTION(ldo_en), + MSM_PIN_FUNCTION(ldo_update), + MSM_PIN_FUNCTION(mgpi_clk), + MSM_PIN_FUNCTION(m_voc), + MSM_PIN_FUNCTION(native_char), + MSM_PIN_FUNCTION(native_char0), + MSM_PIN_FUNCTION(native_char1), + MSM_PIN_FUNCTION(native_char2), + MSM_PIN_FUNCTION(native_char3), + MSM_PIN_FUNCTION(native_tsens), + MSM_PIN_FUNCTION(native_tsense), + MSM_PIN_FUNCTION(nav_gpio), + MSM_PIN_FUNCTION(pa_indicator), + MSM_PIN_FUNCTION(pcie_clkreq), + MSM_PIN_FUNCTION(pci_e), + MSM_PIN_FUNCTION(pll_bist), + MSM_PIN_FUNCTION(pll_ref), + MSM_PIN_FUNCTION(pll_test), + MSM_PIN_FUNCTION(pri_mi2s), + MSM_PIN_FUNCTION(prng_rosc), + MSM_PIN_FUNCTION(qdss_cti), + MSM_PIN_FUNCTION(qdss_gpio), + MSM_PIN_FUNCTION(qdss_stm), + MSM_PIN_FUNCTION(qlink0_en), + MSM_PIN_FUNCTION(qlink0_req), + MSM_PIN_FUNCTION(qlink0_wmss), + MSM_PIN_FUNCTION(qlink1_en), + MSM_PIN_FUNCTION(qlink1_req), + MSM_PIN_FUNCTION(qlink1_wmss), + MSM_PIN_FUNCTION(spmi_coex), + MSM_PIN_FUNCTION(sec_mi2s), + MSM_PIN_FUNCTION(spmi_vgi), + MSM_PIN_FUNCTION(tgu_ch0), + MSM_PIN_FUNCTION(uim1_clk), + MSM_PIN_FUNCTION(uim1_data), + MSM_PIN_FUNCTION(uim1_present), + MSM_PIN_FUNCTION(uim1_reset), + MSM_PIN_FUNCTION(uim2_clk), + MSM_PIN_FUNCTION(uim2_data), + MSM_PIN_FUNCTION(uim2_present), + MSM_PIN_FUNCTION(uim2_reset), + MSM_PIN_FUNCTION(usb2phy_ac), + MSM_PIN_FUNCTION(vsense_trigger), +}; + +/* Every pin is maintained as a single group, and missing or non-existing pin + * would be maintained as dummy group to synchronize pin group index with + * pin descriptor registered with pinctrl core. + * Clients would not be able to request these dummy pin groups. + */ +static const struct msm_pingroup sdx55_groups[] = { + [0] = PINGROUP(0, uim2_data, blsp_uart1, qdss_stm, ebi0_wrcdc, _, _, _, _, _), + [1] = PINGROUP(1, uim2_present, blsp_uart1, qdss_stm, _, _, _, _, _, _), + [2] = PINGROUP(2, uim2_reset, blsp_uart1, blsp_i2c1, qdss_stm, ebi0_wrcdc, _, _, _, _), + [3] = PINGROUP(3, uim2_clk, blsp_uart1, blsp_i2c1, qdss_stm, _, _, _, _, _), + [4] = PINGROUP(4, blsp_spi2, blsp_uart2, _, qdss_stm, qdss_gpio, _, _, _, _), + [5] = PINGROUP(5, blsp_spi2, blsp_uart2, _, qdss_stm, qdss_gpio, _, _, _, _), + [6] = PINGROUP(6, blsp_spi2, blsp_uart2, blsp_i2c2, char_exec, _, qdss_stm, qdss_gpio, _, _), + [7] = PINGROUP(7, blsp_spi2, blsp_uart2, blsp_i2c2, char_exec, _, qdss_stm, qdss_gpio, _, _), + [8] = PINGROUP(8, pri_mi2s, blsp_spi3, blsp_uart3, ext_dbg, ldo_en, _, _, _, _), + [9] = PINGROUP(9, pri_mi2s, blsp_spi3, blsp_uart3, ext_dbg, _, _, _, _, _), + [10] = PINGROUP(10, pri_mi2s, blsp_spi3, blsp_uart3, blsp_i2c3, ext_dbg, _, _, _, _), + [11] = PINGROUP(11, pri_mi2s, blsp_spi3, blsp_uart3, blsp_i2c3, ext_dbg, gcc_gp3, _, _, _), + [12] = PINGROUP(12, pri_mi2s, _, qdss_stm, qdss_gpio, _, _, _, _, _), + [13] = PINGROUP(13, pri_mi2s, _, qdss_stm, qdss_gpio, _, _, _, _, _), + [14] = PINGROUP(14, pri_mi2s, emac_gcc1, _, _, qdss_stm, qdss_gpio, bimc_dte0, native_tsens, vsense_trigger), + [15] = PINGROUP(15, pri_mi2s, emac_gcc0, _, _, qdss_stm, qdss_gpio, bimc_dte1, _, _), + [16] = PINGROUP(16, sec_mi2s, blsp_spi4, blsp_uart4, qdss_cti, qdss_cti, _, _, qdss_stm, qdss_gpio), + [17] = PINGROUP(17, sec_mi2s, blsp_spi4, blsp_uart4, qdss_cti, qdss_cti, _, qdss_stm, qdss_gpio, _), + [18] = PINGROUP(18, sec_mi2s, blsp_spi4, blsp_uart4, blsp_i2c4, gcc_gp1, qdss_stm, qdss_gpio, _, _), + [19] = PINGROUP(19, sec_mi2s, blsp_spi4, blsp_uart4, blsp_i2c4, jitter_bist, gcc_gp2, _, qdss_stm, qdss_gpio), + [20] = PINGROUP(20, sec_mi2s, ebi2_a, blsp_uart1, blsp_uart4, qdss_stm, _, _, _, _), + [21] = PINGROUP(21, sec_mi2s, ebi2_lcd, blsp_uart1, blsp_uart4, _, qdss_stm, _, _, _), + [22] = PINGROUP(22, sec_mi2s, ebi2_lcd, blsp_uart1, qdss_cti, qdss_cti, blsp_uart4, pll_bist, _, qdss_stm), + [23] = PINGROUP(23, sec_mi2s, ebi2_lcd, qdss_cti, qdss_cti, blsp_uart1, blsp_uart4, qdss_stm, _, _), + [24] = PINGROUP(24, adsp_ext, _, _, _, _, _, _, _, _), + [25] = PINGROUP(25, adsp_ext, _, _, _, _, _, _, _, _), + [26] = PINGROUP(26, _, _, _, native_char, _, _, _, _, _), + [27] = PINGROUP(27, _, _, _, _, _, _, _, _, _), + [28] = PINGROUP(28, qlink0_wmss, _, native_char3, _, _, _, _, _, _), + [29] = PINGROUP(29, _, _, _, native_char2, native_tsense, _, _, _, _), + [30] = PINGROUP(30, _, _, _, _, _, _, _, _, _), + [31] = PINGROUP(31, nav_gpio, _, _, _, _, _, _, _, _), + [32] = PINGROUP(32, nav_gpio, pll_ref, _, _, _, _, _, _, _), + [33] = PINGROUP(33, _, pa_indicator, native_char0, _, _, _, _, _, _), + [34] = PINGROUP(34, qlink0_en, _, _, _, _, _, _, _, _), + [35] = PINGROUP(35, qlink0_req, pll_test, _, _, _, _, _, _, _), + [36] = PINGROUP(36, _, _, cri_trng, dbg_out, _, _, _, _, _), + [37] = PINGROUP(37, _, _, _, _, _, _, _, _, _), + [38] = PINGROUP(38, _, _, prng_rosc, _, _, _, _, _, _), + [39] = PINGROUP(39, _, _, _, _, _, _, _, _, _), + [40] = PINGROUP(40, _, _, cri_trng0, _, _, _, _, _, _), + [41] = PINGROUP(41, _, _, cri_trng1, _, _, _, _, _, _), + [42] = PINGROUP(42, _, qdss_gpio, native_char1, _, _, _, _, _, _), + [43] = PINGROUP(43, _, _, _, _, _, _, _, _, _), + [44] = PINGROUP(44, coex_uart, spmi_coex, _, qdss_stm, _, _, _, _, _), + [45] = PINGROUP(45, coex_uart, spmi_coex, qdss_stm, ddr_pxi0, _, _, _, _, _), + [46] = PINGROUP(46, m_voc, ddr_bist, ddr_pxi0, _, _, _, _, _, _), + [47] = PINGROUP(47, ddr_bist, _, _, _, _, _, _, _, _), + [48] = PINGROUP(48, m_voc, ddr_bist, _, _, _, _, _, _, _), + [49] = PINGROUP(49, m_voc, ddr_bist, _, _, _, _, _, _, _), + [50] = PINGROUP(50, _, _, _, _, _, _, _, _, _), + [51] = PINGROUP(51, _, _, _, _, _, _, _, _, _), + [52] = PINGROUP(52, blsp_spi2, blsp_spi1, blsp_spi3, blsp_spi4, _, _, qdss_stm, _, _), + [53] = PINGROUP(53, pci_e, _, _, qdss_stm, _, _, _, _, _), + [54] = PINGROUP(54, qdss_cti, qdss_cti, _, _, _, _, _, _, _), + [55] = PINGROUP(55, qdss_cti, qdss_cti, tgu_ch0, _, _, _, _, _, _), + [56] = PINGROUP(56, pcie_clkreq, _, qdss_stm, _, _, _, _, _, _), + [57] = PINGROUP(57, _, qdss_stm, _, _, _, _, _, _, _), + [58] = PINGROUP(58, _, _, _, _, _, _, _, _, _), + [59] = PINGROUP(59, qdss_cti, m_voc, bimc_dte0, _, _, _, _, _, _), + [60] = PINGROUP(60, qdss_cti, _, m_voc, _, _, _, _, _, _), + [61] = PINGROUP(61, mgpi_clk, qdss_stm, qdss_gpio, bimc_dte1, _, _, _, _, _), + [62] = PINGROUP(62, i2s_mclk, audio_ref, blsp_spi1, blsp_spi2, blsp_spi3, blsp_spi4, ldo_update, qdss_stm, _), + [63] = PINGROUP(63, blsp_uart2, _, qdss_stm, qdss_gpio, atest, _, _, _, _), + [64] = PINGROUP(64, blsp_uart2, qdss_stm, qdss_gpio, atest, _, _, _, _, _), + [65] = PINGROUP(65, blsp_uart2, blsp_i2c2, _, qdss_stm, qdss_gpio, atest, _, _, _), + [66] = PINGROUP(66, blsp_uart2, blsp_i2c2, qdss_stm, qdss_gpio, atest, _, _, _, _), + [67] = PINGROUP(67, uim1_data, atest, _, _, _, _, _, _, _), + [68] = PINGROUP(68, uim1_present, _, _, _, _, _, _, _, _), + [69] = PINGROUP(69, uim1_reset, _, _, _, _, _, _, _, _), + [70] = PINGROUP(70, uim1_clk, _, _, _, _, _, _, _, _), + [71] = PINGROUP(71, mgpi_clk, blsp_spi1, blsp_spi2, blsp_spi3, blsp_spi4, _, _, _, _), + [72] = PINGROUP(72, qlink1_en, _, _, _, _, _, _, _, _), + [73] = PINGROUP(73, qlink1_req, _, _, _, _, _, _, _, _), + [74] = PINGROUP(74, qlink1_wmss, _, _, _, _, _, _, _, _), + [75] = PINGROUP(75, coex_uart2, _, _, _, _, _, _, _, _), + [76] = PINGROUP(76, coex_uart2, nav_gpio, _, _, _, _, _, _, _), + [77] = PINGROUP(77, _, _, _, _, _, _, _, _, _), + [78] = PINGROUP(78, spmi_vgi, blsp_i2c4, _, _, _, _, _, _, _), + [79] = PINGROUP(79, spmi_vgi, blsp_i2c4, _, _, _, _, _, _, _), + [80] = PINGROUP(80, _, blsp_spi1, _, _, _, _, _, _, _), + [81] = PINGROUP(81, _, blsp_spi1, _, gcc_plltest, _, _, _, _, _), + [82] = PINGROUP(82, _, blsp_spi1, _, blsp_i2c1, gcc_plltest, _, _, _, _), + [83] = PINGROUP(83, _, blsp_spi1, _, blsp_i2c1, _, _, _, _, _), + [84] = PINGROUP(84, _, _, _, _, _, _, _, _, _), + [85] = PINGROUP(85, _, _, _, _, _, _, _, _, _), + [86] = PINGROUP(86, _, _, _, _, _, _, _, _, _), + [87] = PINGROUP(87, _, _, _, _, _, _, _, _, _), + [88] = PINGROUP(88, _, _, _, _, _, _, _, _, _), + [89] = PINGROUP(89, _, _, _, _, _, _, _, _, _), + [90] = PINGROUP(90, _, _, _, _, _, _, _, _, _), + [91] = PINGROUP(91, _, _, _, _, _, _, _, _, _), + [92] = PINGROUP(92, _, _, _, _, _, _, _, _, _), + [93] = PINGROUP(93, _, _, usb2phy_ac, _, _, _, _, _, _), + [94] = PINGROUP(94, qdss_cti, qdss_cti, _, _, _, _, _, _, _), + [95] = PINGROUP(95, qdss_cti, qdss_cti, emac_pps1, _, _, _, _, _, _), + [96] = PINGROUP(96, _, _, _, _, _, _, _, _, _), + [97] = PINGROUP(97, _, _, _, _, _, _, _, _, _), + [98] = PINGROUP(98, _, _, _, _, _, _, _, _, _), + [99] = PINGROUP(99, _, _, _, _, _, _, _, _, _), + [100] = PINGROUP(100, _, _, _, _, _, _, _, _, _), + [101] = PINGROUP(101, _, _, _, _, _, _, _, _, _), + [102] = PINGROUP(102, _, _, _, _, _, _, _, _, _), + [103] = PINGROUP(103, _, _, _, _, _, _, _, _, _), + [104] = PINGROUP(104, _, _, _, _, _, _, _, _, _), + [105] = PINGROUP(105, _, _, _, _, _, _, _, _, _), + [106] = PINGROUP(106, emac_pps0, _, _, _, _, _, _, _, _), + [107] = PINGROUP(107, _, _, _, _, _, _, _, _, _), + [109] = SDC_PINGROUP(sdc1_rclk, 0x9a000, 15, 0), + [110] = SDC_PINGROUP(sdc1_clk, 0x9a000, 13, 6), + [111] = SDC_PINGROUP(sdc1_cmd, 0x9a000, 11, 3), + [112] = SDC_PINGROUP(sdc1_data, 0x9a000, 9, 0), +}; + +static const struct msm_pinctrl_soc_data sdx55_pinctrl = { + .pins = sdx55_pins, + .npins = ARRAY_SIZE(sdx55_pins), + .functions = sdx55_functions, + .nfunctions = ARRAY_SIZE(sdx55_functions), + .groups = sdx55_groups, + .ngroups = ARRAY_SIZE(sdx55_groups), + .ngpios = 108, +}; + +static int sdx55_pinctrl_probe(struct platform_device *pdev) +{ + return msm_pinctrl_probe(pdev, &sdx55_pinctrl); +} + +static const struct of_device_id sdx55_pinctrl_of_match[] = { + { .compatible = "qcom,sdx55-pinctrl", }, + { }, +}; + +static struct platform_driver sdx55_pinctrl_driver = { + .driver = { + .name = "sdx55-pinctrl", + .of_match_table = sdx55_pinctrl_of_match, + }, + .probe = sdx55_pinctrl_probe, + .remove = msm_pinctrl_remove, +}; + +static int __init sdx55_pinctrl_init(void) +{ + return platform_driver_register(&sdx55_pinctrl_driver); +} +arch_initcall(sdx55_pinctrl_init); + +static void __exit sdx55_pinctrl_exit(void) +{ + platform_driver_unregister(&sdx55_pinctrl_driver); +} +module_exit(sdx55_pinctrl_exit); + +MODULE_DESCRIPTION("QTI sdx55 pinctrl driver"); +MODULE_LICENSE("GPL v2"); +MODULE_DEVICE_TABLE(of, sdx55_pinctrl_of_match); diff --git a/drivers/pinctrl/qcom/pinctrl-sdx65.c b/drivers/pinctrl/qcom/pinctrl-sdx65.c new file mode 100644 index 0000000000..f6f319c997 --- /dev/null +++ b/drivers/pinctrl/qcom/pinctrl-sdx65.c @@ -0,0 +1,959 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2021 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include <linux/module.h> +#include <linux/of.h> +#include <linux/platform_device.h> + +#include "pinctrl-msm.h" + +#define REG_BASE 0x0 +#define REG_SIZE 0x1000 +#define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7, f8, f9) \ + { \ + .grp = PINCTRL_PINGROUP("gpio" #id, \ + gpio##id##_pins, \ + ARRAY_SIZE(gpio##id##_pins)), \ + .funcs = (int[]){ \ + msm_mux_gpio, /* gpio mode */ \ + msm_mux_##f1, \ + msm_mux_##f2, \ + msm_mux_##f3, \ + msm_mux_##f4, \ + msm_mux_##f5, \ + msm_mux_##f6, \ + msm_mux_##f7, \ + msm_mux_##f8, \ + msm_mux_##f9 \ + }, \ + .nfuncs = 10, \ + .ctl_reg = REG_BASE + REG_SIZE * id, \ + .io_reg = REG_BASE + 0x4 + REG_SIZE * id, \ + .intr_cfg_reg = REG_BASE + 0x8 + REG_SIZE * id, \ + .intr_status_reg = REG_BASE + 0xc + REG_SIZE * id, \ + .intr_target_reg = REG_BASE + 0x8 + REG_SIZE * id, \ + .mux_bit = 2, \ + .pull_bit = 0, \ + .drv_bit = 6, \ + .oe_bit = 9, \ + .in_bit = 0, \ + .out_bit = 1, \ + .intr_enable_bit = 0, \ + .intr_status_bit = 0, \ + .intr_target_bit = 5, \ + .intr_target_kpss_val = 3, \ + .intr_raw_status_bit = 4, \ + .intr_polarity_bit = 1, \ + .intr_detection_bit = 2, \ + .intr_detection_width = 2, \ + } + +#define SDC_QDSD_PINGROUP(pg_name, ctl, pull, drv) \ + { \ + .grp = PINCTRL_PINGROUP(#pg_name, \ + pg_name##_pins, \ + ARRAY_SIZE(pg_name##_pins)), \ + .ctl_reg = ctl, \ + .io_reg = 0, \ + .intr_cfg_reg = 0, \ + .intr_status_reg = 0, \ + .intr_target_reg = 0, \ + .mux_bit = -1, \ + .pull_bit = pull, \ + .drv_bit = drv, \ + .oe_bit = -1, \ + .in_bit = -1, \ + .out_bit = -1, \ + .intr_enable_bit = -1, \ + .intr_status_bit = -1, \ + .intr_target_bit = -1, \ + .intr_raw_status_bit = -1, \ + .intr_polarity_bit = -1, \ + .intr_detection_bit = -1, \ + .intr_detection_width = -1, \ + } + +#define UFS_RESET(pg_name, offset) \ + { \ + .grp = PINCTRL_PINGROUP(#pg_name, \ + pg_name##_pins, \ + ARRAY_SIZE(pg_name##_pins)), \ + .ctl_reg = offset, \ + .io_reg = offset + 0x4, \ + .intr_cfg_reg = 0, \ + .intr_status_reg = 0, \ + .intr_target_reg = 0, \ + .mux_bit = -1, \ + .pull_bit = 3, \ + .drv_bit = 0, \ + .oe_bit = -1, \ + .in_bit = -1, \ + .out_bit = 0, \ + .intr_enable_bit = -1, \ + .intr_status_bit = -1, \ + .intr_target_bit = -1, \ + .intr_raw_status_bit = -1, \ + .intr_polarity_bit = -1, \ + .intr_detection_bit = -1, \ + .intr_detection_width = -1, \ + } + +static const struct pinctrl_pin_desc sdx65_pins[] = { + PINCTRL_PIN(0, "GPIO_0"), + PINCTRL_PIN(1, "GPIO_1"), + PINCTRL_PIN(2, "GPIO_2"), + PINCTRL_PIN(3, "GPIO_3"), + PINCTRL_PIN(4, "GPIO_4"), + PINCTRL_PIN(5, "GPIO_5"), + PINCTRL_PIN(6, "GPIO_6"), + PINCTRL_PIN(7, "GPIO_7"), + PINCTRL_PIN(8, "GPIO_8"), + PINCTRL_PIN(9, "GPIO_9"), + PINCTRL_PIN(10, "GPIO_10"), + PINCTRL_PIN(11, "GPIO_11"), + PINCTRL_PIN(12, "GPIO_12"), + PINCTRL_PIN(13, "GPIO_13"), + PINCTRL_PIN(14, "GPIO_14"), + PINCTRL_PIN(15, "GPIO_15"), + PINCTRL_PIN(16, "GPIO_16"), + PINCTRL_PIN(17, "GPIO_17"), + PINCTRL_PIN(18, "GPIO_18"), + PINCTRL_PIN(19, "GPIO_19"), + PINCTRL_PIN(20, "GPIO_20"), + PINCTRL_PIN(21, "GPIO_21"), + PINCTRL_PIN(22, "GPIO_22"), + PINCTRL_PIN(23, "GPIO_23"), + PINCTRL_PIN(24, "GPIO_24"), + PINCTRL_PIN(25, "GPIO_25"), + PINCTRL_PIN(26, "GPIO_26"), + PINCTRL_PIN(27, "GPIO_27"), + PINCTRL_PIN(28, "GPIO_28"), + PINCTRL_PIN(29, "GPIO_29"), + PINCTRL_PIN(30, "GPIO_30"), + PINCTRL_PIN(31, "GPIO_31"), + PINCTRL_PIN(32, "GPIO_32"), + PINCTRL_PIN(33, "GPIO_33"), + PINCTRL_PIN(34, "GPIO_34"), + PINCTRL_PIN(35, "GPIO_35"), + PINCTRL_PIN(36, "GPIO_36"), + PINCTRL_PIN(37, "GPIO_37"), + PINCTRL_PIN(38, "GPIO_38"), + PINCTRL_PIN(39, "GPIO_39"), + PINCTRL_PIN(40, "GPIO_40"), + PINCTRL_PIN(41, "GPIO_41"), + PINCTRL_PIN(42, "GPIO_42"), + PINCTRL_PIN(43, "GPIO_43"), + PINCTRL_PIN(44, "GPIO_44"), + PINCTRL_PIN(45, "GPIO_45"), + PINCTRL_PIN(46, "GPIO_46"), + PINCTRL_PIN(47, "GPIO_47"), + PINCTRL_PIN(48, "GPIO_48"), + PINCTRL_PIN(49, "GPIO_49"), + PINCTRL_PIN(50, "GPIO_50"), + PINCTRL_PIN(51, "GPIO_51"), + PINCTRL_PIN(52, "GPIO_52"), + PINCTRL_PIN(53, "GPIO_53"), + PINCTRL_PIN(54, "GPIO_54"), + PINCTRL_PIN(55, "GPIO_55"), + PINCTRL_PIN(56, "GPIO_56"), + PINCTRL_PIN(57, "GPIO_57"), + PINCTRL_PIN(58, "GPIO_58"), + PINCTRL_PIN(59, "GPIO_59"), + PINCTRL_PIN(60, "GPIO_60"), + PINCTRL_PIN(61, "GPIO_61"), + PINCTRL_PIN(62, "GPIO_62"), + PINCTRL_PIN(63, "GPIO_63"), + PINCTRL_PIN(64, "GPIO_64"), + PINCTRL_PIN(65, "GPIO_65"), + PINCTRL_PIN(66, "GPIO_66"), + PINCTRL_PIN(67, "GPIO_67"), + PINCTRL_PIN(68, "GPIO_68"), + PINCTRL_PIN(69, "GPIO_69"), + PINCTRL_PIN(70, "GPIO_70"), + PINCTRL_PIN(71, "GPIO_71"), + PINCTRL_PIN(72, "GPIO_72"), + PINCTRL_PIN(73, "GPIO_73"), + PINCTRL_PIN(74, "GPIO_74"), + PINCTRL_PIN(75, "GPIO_75"), + PINCTRL_PIN(76, "GPIO_76"), + PINCTRL_PIN(77, "GPIO_77"), + PINCTRL_PIN(78, "GPIO_78"), + PINCTRL_PIN(79, "GPIO_79"), + PINCTRL_PIN(80, "GPIO_80"), + PINCTRL_PIN(81, "GPIO_81"), + PINCTRL_PIN(82, "GPIO_82"), + PINCTRL_PIN(83, "GPIO_83"), + PINCTRL_PIN(84, "GPIO_84"), + PINCTRL_PIN(85, "GPIO_85"), + PINCTRL_PIN(86, "GPIO_86"), + PINCTRL_PIN(87, "GPIO_87"), + PINCTRL_PIN(88, "GPIO_88"), + PINCTRL_PIN(89, "GPIO_89"), + PINCTRL_PIN(90, "GPIO_90"), + PINCTRL_PIN(91, "GPIO_91"), + PINCTRL_PIN(92, "GPIO_92"), + PINCTRL_PIN(93, "GPIO_93"), + PINCTRL_PIN(94, "GPIO_94"), + PINCTRL_PIN(95, "GPIO_95"), + PINCTRL_PIN(96, "GPIO_96"), + PINCTRL_PIN(97, "GPIO_97"), + PINCTRL_PIN(98, "GPIO_98"), + PINCTRL_PIN(99, "GPIO_99"), + PINCTRL_PIN(100, "GPIO_100"), + PINCTRL_PIN(101, "GPIO_101"), + PINCTRL_PIN(102, "GPIO_102"), + PINCTRL_PIN(103, "GPIO_103"), + PINCTRL_PIN(104, "GPIO_104"), + PINCTRL_PIN(105, "GPIO_105"), + PINCTRL_PIN(106, "GPIO_106"), + PINCTRL_PIN(107, "GPIO_107"), + PINCTRL_PIN(108, "UFS_RESET"), + PINCTRL_PIN(109, "SDC1_RCLK"), + PINCTRL_PIN(110, "SDC1_CLK"), + PINCTRL_PIN(111, "SDC1_CMD"), + PINCTRL_PIN(112, "SDC1_DATA"), +}; + +#define DECLARE_MSM_GPIO_PINS(pin) \ + static const unsigned int gpio##pin##_pins[] = { pin } +DECLARE_MSM_GPIO_PINS(0); +DECLARE_MSM_GPIO_PINS(1); +DECLARE_MSM_GPIO_PINS(2); +DECLARE_MSM_GPIO_PINS(3); +DECLARE_MSM_GPIO_PINS(4); +DECLARE_MSM_GPIO_PINS(5); +DECLARE_MSM_GPIO_PINS(6); +DECLARE_MSM_GPIO_PINS(7); +DECLARE_MSM_GPIO_PINS(8); +DECLARE_MSM_GPIO_PINS(9); +DECLARE_MSM_GPIO_PINS(10); +DECLARE_MSM_GPIO_PINS(11); +DECLARE_MSM_GPIO_PINS(12); +DECLARE_MSM_GPIO_PINS(13); +DECLARE_MSM_GPIO_PINS(14); +DECLARE_MSM_GPIO_PINS(15); +DECLARE_MSM_GPIO_PINS(16); +DECLARE_MSM_GPIO_PINS(17); +DECLARE_MSM_GPIO_PINS(18); +DECLARE_MSM_GPIO_PINS(19); +DECLARE_MSM_GPIO_PINS(20); +DECLARE_MSM_GPIO_PINS(21); +DECLARE_MSM_GPIO_PINS(22); +DECLARE_MSM_GPIO_PINS(23); +DECLARE_MSM_GPIO_PINS(24); +DECLARE_MSM_GPIO_PINS(25); +DECLARE_MSM_GPIO_PINS(26); +DECLARE_MSM_GPIO_PINS(27); +DECLARE_MSM_GPIO_PINS(28); +DECLARE_MSM_GPIO_PINS(29); +DECLARE_MSM_GPIO_PINS(30); +DECLARE_MSM_GPIO_PINS(31); +DECLARE_MSM_GPIO_PINS(32); +DECLARE_MSM_GPIO_PINS(33); +DECLARE_MSM_GPIO_PINS(34); +DECLARE_MSM_GPIO_PINS(35); +DECLARE_MSM_GPIO_PINS(36); +DECLARE_MSM_GPIO_PINS(37); +DECLARE_MSM_GPIO_PINS(38); +DECLARE_MSM_GPIO_PINS(39); +DECLARE_MSM_GPIO_PINS(40); +DECLARE_MSM_GPIO_PINS(41); +DECLARE_MSM_GPIO_PINS(42); +DECLARE_MSM_GPIO_PINS(43); +DECLARE_MSM_GPIO_PINS(44); +DECLARE_MSM_GPIO_PINS(45); +DECLARE_MSM_GPIO_PINS(46); +DECLARE_MSM_GPIO_PINS(47); +DECLARE_MSM_GPIO_PINS(48); +DECLARE_MSM_GPIO_PINS(49); +DECLARE_MSM_GPIO_PINS(50); +DECLARE_MSM_GPIO_PINS(51); +DECLARE_MSM_GPIO_PINS(52); +DECLARE_MSM_GPIO_PINS(53); +DECLARE_MSM_GPIO_PINS(54); +DECLARE_MSM_GPIO_PINS(55); +DECLARE_MSM_GPIO_PINS(56); +DECLARE_MSM_GPIO_PINS(57); +DECLARE_MSM_GPIO_PINS(58); +DECLARE_MSM_GPIO_PINS(59); +DECLARE_MSM_GPIO_PINS(60); +DECLARE_MSM_GPIO_PINS(61); +DECLARE_MSM_GPIO_PINS(62); +DECLARE_MSM_GPIO_PINS(63); +DECLARE_MSM_GPIO_PINS(64); +DECLARE_MSM_GPIO_PINS(65); +DECLARE_MSM_GPIO_PINS(66); +DECLARE_MSM_GPIO_PINS(67); +DECLARE_MSM_GPIO_PINS(68); +DECLARE_MSM_GPIO_PINS(69); +DECLARE_MSM_GPIO_PINS(70); +DECLARE_MSM_GPIO_PINS(71); +DECLARE_MSM_GPIO_PINS(72); +DECLARE_MSM_GPIO_PINS(73); +DECLARE_MSM_GPIO_PINS(74); +DECLARE_MSM_GPIO_PINS(75); +DECLARE_MSM_GPIO_PINS(76); +DECLARE_MSM_GPIO_PINS(77); +DECLARE_MSM_GPIO_PINS(78); +DECLARE_MSM_GPIO_PINS(79); +DECLARE_MSM_GPIO_PINS(80); +DECLARE_MSM_GPIO_PINS(81); +DECLARE_MSM_GPIO_PINS(82); +DECLARE_MSM_GPIO_PINS(83); +DECLARE_MSM_GPIO_PINS(84); +DECLARE_MSM_GPIO_PINS(85); +DECLARE_MSM_GPIO_PINS(86); +DECLARE_MSM_GPIO_PINS(87); +DECLARE_MSM_GPIO_PINS(88); +DECLARE_MSM_GPIO_PINS(89); +DECLARE_MSM_GPIO_PINS(90); +DECLARE_MSM_GPIO_PINS(91); +DECLARE_MSM_GPIO_PINS(92); +DECLARE_MSM_GPIO_PINS(93); +DECLARE_MSM_GPIO_PINS(94); +DECLARE_MSM_GPIO_PINS(95); +DECLARE_MSM_GPIO_PINS(96); +DECLARE_MSM_GPIO_PINS(97); +DECLARE_MSM_GPIO_PINS(98); +DECLARE_MSM_GPIO_PINS(99); +DECLARE_MSM_GPIO_PINS(100); +DECLARE_MSM_GPIO_PINS(101); +DECLARE_MSM_GPIO_PINS(102); +DECLARE_MSM_GPIO_PINS(103); +DECLARE_MSM_GPIO_PINS(104); +DECLARE_MSM_GPIO_PINS(105); +DECLARE_MSM_GPIO_PINS(106); +DECLARE_MSM_GPIO_PINS(107); + +static const unsigned int ufs_reset_pins[] = { 108 }; +static const unsigned int sdc1_rclk_pins[] = { 109 }; +static const unsigned int sdc1_clk_pins[] = { 110 }; +static const unsigned int sdc1_cmd_pins[] = { 111 }; +static const unsigned int sdc1_data_pins[] = { 112 }; + +enum sdx65_functions { + msm_mux_qlink0_wmss, + msm_mux_adsp_ext, + msm_mux_atest_char, + msm_mux_atest_char0, + msm_mux_atest_char1, + msm_mux_atest_char2, + msm_mux_atest_char3, + msm_mux_audio_ref, + msm_mux_bimc_dte0, + msm_mux_bimc_dte1, + msm_mux_blsp_i2c1, + msm_mux_blsp_i2c2, + msm_mux_blsp_i2c3, + msm_mux_blsp_i2c4, + msm_mux_blsp_spi1, + msm_mux_blsp_spi2, + msm_mux_blsp_spi3, + msm_mux_blsp_spi4, + msm_mux_blsp_uart1, + msm_mux_blsp_uart2, + msm_mux_blsp_uart3, + msm_mux_blsp_uart4, + msm_mux_char_exec, + msm_mux_coex_uart, + msm_mux_coex_uart2, + msm_mux_cri_trng, + msm_mux_cri_trng0, + msm_mux_cri_trng1, + msm_mux_dbg_out, + msm_mux_ddr_bist, + msm_mux_ddr_pxi0, + msm_mux_ebi0_wrcdc, + msm_mux_ebi2_a, + msm_mux_ebi2_lcd, + msm_mux_ext_dbg, + msm_mux_gcc_gp1, + msm_mux_gcc_gp2, + msm_mux_gcc_gp3, + msm_mux_gcc_plltest, + msm_mux_gpio, + msm_mux_i2s_mclk, + msm_mux_jitter_bist, + msm_mux_ldo_en, + msm_mux_ldo_update, + msm_mux_m_voc, + msm_mux_mgpi_clk, + msm_mux_native_char, + msm_mux_native_tsens, + msm_mux_native_tsense, + msm_mux_nav_gpio, + msm_mux_pa_indicator, + msm_mux_pci_e, + msm_mux_pcie_clkreq, + msm_mux_pll_bist, + msm_mux_pll_ref, + msm_mux_pri_mi2s, + msm_mux_pri_mi2s_ws, + msm_mux_prng_rosc, + msm_mux_qdss_cti, + msm_mux_qdss_gpio, + msm_mux_qlink0_en, + msm_mux_qlink0_req, + msm_mux_qlink1_en, + msm_mux_qlink1_req, + msm_mux_qlink1_wmss, + msm_mux_qlink2_en, + msm_mux_qlink2_req, + msm_mux_qlink2_wmss, + msm_mux_sdc1_tb, + msm_mux_sec_mi2s, + msm_mux_spmi_coex, + msm_mux_spmi_vgi, + msm_mux_tgu_ch0, + msm_mux_uim1_clk, + msm_mux_uim1_data, + msm_mux_uim1_present, + msm_mux_uim1_reset, + msm_mux_uim2_clk, + msm_mux_uim2_data, + msm_mux_uim2_present, + msm_mux_uim2_reset, + msm_mux_usb2phy_ac, + msm_mux_vsense_trigger, + msm_mux__, +}; + +static const char * const gpio_groups[] = { + "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7", + "gpio8", "gpio9", "gpio10", "gpio11", "gpio12", "gpio13", "gpio14", + "gpio15", "gpio16", "gpio17", "gpio18", "gpio19", "gpio20", "gpio21", + "gpio22", "gpio23", "gpio24", "gpio25", "gpio26", "gpio27", "gpio28", + "gpio29", "gpio30", "gpio31", "gpio32", "gpio33", "gpio34", "gpio35", + "gpio36", "gpio37", "gpio38", "gpio39", "gpio40", "gpio41", "gpio42", + "gpio43", "gpio44", "gpio45", "gpio46", "gpio47", "gpio48", "gpio49", + "gpio50", "gpio51", "gpio52", "gpio53", "gpio54", "gpio55", "gpio56", + "gpio57", "gpio58", "gpio59", "gpio60", "gpio61", "gpio62", "gpio63", + "gpio64", "gpio65", "gpio66", "gpio67", "gpio68", "gpio69", "gpio70", + "gpio71", "gpio72", "gpio73", "gpio74", "gpio75", "gpio76", "gpio77", + "gpio78", "gpio79", "gpio80", "gpio81", "gpio82", "gpio83", "gpio84", + "gpio85", "gpio86", "gpio87", "gpio88", "gpio89", "gpio90", "gpio91", + "gpio92", "gpio93", "gpio94", "gpio95", "gpio96", "gpio97", "gpio98", + "gpio99", "gpio100", "gpio101", "gpio102", "gpio103", "gpio104", + "gpio105", "gpio106", "gpio107", +}; +static const char * const uim2_data_groups[] = { + "gpio0", +}; +static const char * const blsp_uart1_groups[] = { + "gpio0", "gpio1", "gpio2", "gpio3", "gpio48", "gpio49", "gpio80", + "gpio81", +}; +static const char * const ebi0_wrcdc_groups[] = { + "gpio0", "gpio2", +}; +static const char * const uim2_present_groups[] = { + "gpio1", +}; +static const char * const uim2_reset_groups[] = { + "gpio2", +}; +static const char * const blsp_i2c1_groups[] = { + "gpio2", "gpio3", "gpio82", "gpio83", +}; +static const char * const uim2_clk_groups[] = { + "gpio3", +}; +static const char * const blsp_spi2_groups[] = { + "gpio4", "gpio5", "gpio6", "gpio7", "gpio23", "gpio47", "gpio62", +}; +static const char * const blsp_uart2_groups[] = { + "gpio4", "gpio5", "gpio6", "gpio7", "gpio63", "gpio64", "gpio65", + "gpio66", +}; +static const char * const blsp_i2c2_groups[] = { + "gpio6", "gpio7", "gpio65", "gpio66", +}; +static const char * const char_exec_groups[] = { + "gpio6", "gpio7", +}; +static const char * const qdss_gpio_groups[] = { + "gpio4", "gpio5", "gpio6", "gpio7", "gpio12", "gpio13", + "gpio14", "gpio15", "gpio16", "gpio17", "gpio18", "gpio19", + "gpio33", "gpio42", "gpio63", "gpio64", "gpio65", "gpio66", +}; +static const char * const blsp_spi3_groups[] = { + "gpio8", "gpio9", "gpio10", "gpio11", "gpio23", "gpio47", "gpio62", +}; +static const char * const blsp_uart3_groups[] = { + "gpio8", "gpio9", "gpio10", "gpio11", +}; +static const char * const ext_dbg_groups[] = { + "gpio8", "gpio9", "gpio10", "gpio11", +}; +static const char * const ldo_en_groups[] = { + "gpio8", +}; +static const char * const blsp_i2c3_groups[] = { + "gpio10", "gpio11", +}; +static const char * const gcc_gp3_groups[] = { + "gpio11", +}; +static const char * const pri_mi2s_ws_groups[] = { + "gpio12", +}; +static const char * const pri_mi2s_groups[] = { + "gpio13", "gpio14", "gpio15", +}; +static const char * const vsense_trigger_groups[] = { + "gpio13", +}; +static const char * const native_tsens_groups[] = { + "gpio14", +}; +static const char * const bimc_dte0_groups[] = { + "gpio14", "gpio59", +}; +static const char * const bimc_dte1_groups[] = { + "gpio15", "gpio61", +}; +static const char * const sec_mi2s_groups[] = { + "gpio16", "gpio17", "gpio18", "gpio19", +}; +static const char * const blsp_spi4_groups[] = { + "gpio16", "gpio17", "gpio18", "gpio19", "gpio23", "gpio47", "gpio62", +}; +static const char * const blsp_uart4_groups[] = { + "gpio16", "gpio17", "gpio18", "gpio19", "gpio22", "gpio23", "gpio48", + "gpio49", +}; +static const char * const qdss_cti_groups[] = { + "gpio16", "gpio16", "gpio17", "gpio17", "gpio54", "gpio54", "gpio55", + "gpio55", "gpio59", "gpio60", "gpio65", "gpio65", "gpio66", "gpio66", + "gpio94", "gpio94", "gpio95", "gpio95", +}; +static const char * const blsp_i2c4_groups[] = { + "gpio18", "gpio19", "gpio84", "gpio85", +}; +static const char * const gcc_gp1_groups[] = { + "gpio18", +}; +static const char * const jitter_bist_groups[] = { + "gpio19", +}; +static const char * const gcc_gp2_groups[] = { + "gpio19", +}; +static const char * const pll_bist_groups[] = { + "gpio22", +}; +static const char * const blsp_spi1_groups[] = { + "gpio23", "gpio47", "gpio62", "gpio80", "gpio81", "gpio82", "gpio83", +}; +static const char * const adsp_ext_groups[] = { + "gpio24", "gpio25", +}; +static const char * const qlink0_wmss_groups[] = { + "gpio28", +}; +static const char * const native_tsense_groups[] = { + "gpio29", "gpio72", +}; +static const char * const nav_gpio_groups[] = { + "gpio31", "gpio32", +}; +static const char * const pll_ref_groups[] = { + "gpio32", +}; +static const char * const pa_indicator_groups[] = { + "gpio33", +}; +static const char * const qlink0_en_groups[] = { + "gpio34", +}; +static const char * const qlink0_req_groups[] = { + "gpio35", +}; +static const char * const dbg_out_groups[] = { + "gpio35", +}; +static const char * const cri_trng_groups[] = { + "gpio36", +}; +static const char * const prng_rosc_groups[] = { + "gpio38", +}; +static const char * const cri_trng0_groups[] = { + "gpio40", +}; +static const char * const cri_trng1_groups[] = { + "gpio41", +}; +static const char * const coex_uart_groups[] = { + "gpio44", "gpio45", +}; +static const char * const ddr_pxi0_groups[] = { + "gpio45", "gpio46", +}; +static const char * const m_voc_groups[] = { + "gpio46", "gpio48", "gpio49", "gpio59", "gpio60", +}; +static const char * const ddr_bist_groups[] = { + "gpio46", "gpio47", "gpio48", "gpio49", +}; +static const char * const pci_e_groups[] = { + "gpio53", +}; +static const char * const tgu_ch0_groups[] = { + "gpio55", +}; +static const char * const pcie_clkreq_groups[] = { + "gpio56", +}; +static const char * const native_char_groups[] = { + "gpio26", "gpio29", "gpio33", "gpio42", "gpio57", +}; +static const char * const mgpi_clk_groups[] = { + "gpio61", "gpio71", +}; +static const char * const qlink2_wmss_groups[] = { + "gpio61", +}; +static const char * const i2s_mclk_groups[] = { + "gpio62", +}; +static const char * const audio_ref_groups[] = { + "gpio62", +}; +static const char * const ldo_update_groups[] = { + "gpio62", +}; +static const char * const atest_char_groups[] = { + "gpio63", +}; +static const char * const atest_char3_groups[] = { + "gpio64", +}; +static const char * const atest_char2_groups[] = { + "gpio65", +}; +static const char * const atest_char1_groups[] = { + "gpio66", +}; +static const char * const uim1_data_groups[] = { + "gpio67", +}; +static const char * const atest_char0_groups[] = { + "gpio67", +}; +static const char * const uim1_present_groups[] = { + "gpio68", +}; +static const char * const uim1_reset_groups[] = { + "gpio69", +}; +static const char * const uim1_clk_groups[] = { + "gpio70", +}; +static const char * const qlink2_en_groups[] = { + "gpio71", +}; +static const char * const qlink1_en_groups[] = { + "gpio72", +}; +static const char * const qlink1_req_groups[] = { + "gpio73", +}; +static const char * const qlink1_wmss_groups[] = { + "gpio74", +}; +static const char * const coex_uart2_groups[] = { + "gpio75", "gpio76", "gpio102", "gpio103", +}; +static const char * const spmi_coex_groups[] = { + "gpio75", "gpio76", +}; +static const char * const qlink2_req_groups[] = { + "gpio77", +}; +static const char * const spmi_vgi_groups[] = { + "gpio78", "gpio79", +}; +static const char * const gcc_plltest_groups[] = { + "gpio81", "gpio82", +}; +static const char * const ebi2_lcd_groups[] = { + "gpio84", "gpio85", "gpio90", +}; +static const char * const ebi2_a_groups[] = { + "gpio89", +}; +static const char * const usb2phy_ac_groups[] = { + "gpio93", +}; +static const char * const sdc1_tb_groups[] = { + "gpio106", +}; + +static const struct pinfunction sdx65_functions[] = { + MSM_PIN_FUNCTION(qlink0_wmss), + MSM_PIN_FUNCTION(adsp_ext), + MSM_PIN_FUNCTION(atest_char), + MSM_PIN_FUNCTION(atest_char0), + MSM_PIN_FUNCTION(atest_char1), + MSM_PIN_FUNCTION(atest_char2), + MSM_PIN_FUNCTION(atest_char3), + MSM_PIN_FUNCTION(audio_ref), + MSM_PIN_FUNCTION(bimc_dte0), + MSM_PIN_FUNCTION(bimc_dte1), + MSM_PIN_FUNCTION(blsp_i2c1), + MSM_PIN_FUNCTION(blsp_i2c2), + MSM_PIN_FUNCTION(blsp_i2c3), + MSM_PIN_FUNCTION(blsp_i2c4), + MSM_PIN_FUNCTION(blsp_spi1), + MSM_PIN_FUNCTION(blsp_spi2), + MSM_PIN_FUNCTION(blsp_spi3), + MSM_PIN_FUNCTION(blsp_spi4), + MSM_PIN_FUNCTION(blsp_uart1), + MSM_PIN_FUNCTION(blsp_uart2), + MSM_PIN_FUNCTION(blsp_uart3), + MSM_PIN_FUNCTION(blsp_uart4), + MSM_PIN_FUNCTION(char_exec), + MSM_PIN_FUNCTION(coex_uart), + MSM_PIN_FUNCTION(coex_uart2), + MSM_PIN_FUNCTION(cri_trng), + MSM_PIN_FUNCTION(cri_trng0), + MSM_PIN_FUNCTION(cri_trng1), + MSM_PIN_FUNCTION(dbg_out), + MSM_PIN_FUNCTION(ddr_bist), + MSM_PIN_FUNCTION(ddr_pxi0), + MSM_PIN_FUNCTION(ebi0_wrcdc), + MSM_PIN_FUNCTION(ebi2_a), + MSM_PIN_FUNCTION(ebi2_lcd), + MSM_PIN_FUNCTION(ext_dbg), + MSM_PIN_FUNCTION(gcc_gp1), + MSM_PIN_FUNCTION(gcc_gp2), + MSM_PIN_FUNCTION(gcc_gp3), + MSM_PIN_FUNCTION(gcc_plltest), + MSM_PIN_FUNCTION(gpio), + MSM_PIN_FUNCTION(i2s_mclk), + MSM_PIN_FUNCTION(jitter_bist), + MSM_PIN_FUNCTION(ldo_en), + MSM_PIN_FUNCTION(ldo_update), + MSM_PIN_FUNCTION(m_voc), + MSM_PIN_FUNCTION(mgpi_clk), + MSM_PIN_FUNCTION(native_char), + MSM_PIN_FUNCTION(native_tsens), + MSM_PIN_FUNCTION(native_tsense), + MSM_PIN_FUNCTION(nav_gpio), + MSM_PIN_FUNCTION(pa_indicator), + MSM_PIN_FUNCTION(pci_e), + MSM_PIN_FUNCTION(pcie_clkreq), + MSM_PIN_FUNCTION(pll_bist), + MSM_PIN_FUNCTION(pll_ref), + MSM_PIN_FUNCTION(pri_mi2s), + MSM_PIN_FUNCTION(pri_mi2s_ws), + MSM_PIN_FUNCTION(prng_rosc), + MSM_PIN_FUNCTION(qdss_cti), + MSM_PIN_FUNCTION(qdss_gpio), + MSM_PIN_FUNCTION(qlink0_en), + MSM_PIN_FUNCTION(qlink0_req), + MSM_PIN_FUNCTION(qlink1_en), + MSM_PIN_FUNCTION(qlink1_req), + MSM_PIN_FUNCTION(qlink1_wmss), + MSM_PIN_FUNCTION(qlink2_en), + MSM_PIN_FUNCTION(qlink2_req), + MSM_PIN_FUNCTION(qlink2_wmss), + MSM_PIN_FUNCTION(sdc1_tb), + MSM_PIN_FUNCTION(sec_mi2s), + MSM_PIN_FUNCTION(spmi_coex), + MSM_PIN_FUNCTION(spmi_vgi), + MSM_PIN_FUNCTION(tgu_ch0), + MSM_PIN_FUNCTION(uim1_clk), + MSM_PIN_FUNCTION(uim1_data), + MSM_PIN_FUNCTION(uim1_present), + MSM_PIN_FUNCTION(uim1_reset), + MSM_PIN_FUNCTION(uim2_clk), + MSM_PIN_FUNCTION(uim2_data), + MSM_PIN_FUNCTION(uim2_present), + MSM_PIN_FUNCTION(uim2_reset), + MSM_PIN_FUNCTION(usb2phy_ac), + MSM_PIN_FUNCTION(vsense_trigger), +}; + +/* Every pin is maintained as a single group, and missing or non-existing pin + * would be maintained as dummy group to synchronize pin group index with + * pin descriptor registered with pinctrl core. + * Clients would not be able to request these dummy pin groups. + */ +static const struct msm_pingroup sdx65_groups[] = { + [0] = PINGROUP(0, uim2_data, blsp_uart1, ebi0_wrcdc, _, _, _, _, _, _), + [1] = PINGROUP(1, uim2_present, blsp_uart1, _, _, _, _, _, _, _), + [2] = PINGROUP(2, uim2_reset, blsp_uart1, blsp_i2c1, ebi0_wrcdc, _, _, _, _, _), + [3] = PINGROUP(3, uim2_clk, blsp_uart1, blsp_i2c1, _, _, _, _, _, _), + [4] = PINGROUP(4, blsp_spi2, blsp_uart2, _, qdss_gpio, _, _, _, _, _), + [5] = PINGROUP(5, blsp_spi2, blsp_uart2, _, qdss_gpio, _, _, _, _, _), + [6] = PINGROUP(6, blsp_spi2, blsp_uart2, blsp_i2c2, char_exec, _, qdss_gpio, _, _, _), + [7] = PINGROUP(7, blsp_spi2, blsp_uart2, blsp_i2c2, char_exec, _, qdss_gpio, _, _, _), + [8] = PINGROUP(8, blsp_spi3, blsp_uart3, ext_dbg, ldo_en, _, _, _, _, _), + [9] = PINGROUP(9, blsp_spi3, blsp_uart3, ext_dbg, _, _, _, _, _, _), + [10] = PINGROUP(10, blsp_spi3, blsp_uart3, blsp_i2c3, ext_dbg, _, _, _, _, _), + [11] = PINGROUP(11, blsp_spi3, blsp_uart3, blsp_i2c3, ext_dbg, gcc_gp3, _, _, _, _), + [12] = PINGROUP(12, pri_mi2s_ws, _, qdss_gpio, _, _, _, _, _, _), + [13] = PINGROUP(13, pri_mi2s, _, qdss_gpio, vsense_trigger, _, _, _, _, _), + [14] = PINGROUP(14, pri_mi2s, _, _, qdss_gpio, native_tsens, bimc_dte0, _, _, _), + [15] = PINGROUP(15, pri_mi2s, _, _, qdss_gpio, bimc_dte1, _, _, _, _), + [16] = PINGROUP(16, sec_mi2s, blsp_spi4, blsp_uart4, qdss_cti, qdss_cti, _, _, qdss_gpio, _), + [17] = PINGROUP(17, sec_mi2s, blsp_spi4, blsp_uart4, qdss_cti, qdss_cti, _, qdss_gpio, _, _), + [18] = PINGROUP(18, sec_mi2s, blsp_spi4, blsp_uart4, blsp_i2c4, gcc_gp1, qdss_gpio, _, _, _), + [19] = PINGROUP(19, sec_mi2s, blsp_spi4, blsp_uart4, blsp_i2c4, jitter_bist, gcc_gp2, _, qdss_gpio, _), + [20] = PINGROUP(20, _, _, _, _, _, _, _, _, _), + [21] = PINGROUP(21, _, _, _, _, _, _, _, _, _), + [22] = PINGROUP(22, blsp_uart4, pll_bist, _, _, _, _, _, _, _), + [23] = PINGROUP(23, blsp_uart4, blsp_spi2, blsp_spi1, blsp_spi3, blsp_spi4, _, _, _, _), + [24] = PINGROUP(24, adsp_ext, _, _, _, _, _, _, _, _), + [25] = PINGROUP(25, adsp_ext, _, _, _, _, _, _, _, _), + [26] = PINGROUP(26, _, _, _, native_char, _, _, _, _, _), + [27] = PINGROUP(27, _, _, _, _, _, _, _, _, _), + [28] = PINGROUP(28, qlink0_wmss, _, _, _, _, _, _, _, _), + [29] = PINGROUP(29, _, _, _, native_tsense, native_char, _, _, _, _), + [30] = PINGROUP(30, _, _, _, _, _, _, _, _, _), + [31] = PINGROUP(31, nav_gpio, _, _, _, _, _, _, _, _), + [32] = PINGROUP(32, nav_gpio, pll_ref, _, _, _, _, _, _, _), + [33] = PINGROUP(33, _, pa_indicator, qdss_gpio, native_char, _, _, _, _, _), + [34] = PINGROUP(34, qlink0_en, _, _, _, _, _, _, _, _), + [35] = PINGROUP(35, qlink0_req, dbg_out, _, _, _, _, _, _, _), + [36] = PINGROUP(36, _, _, cri_trng, _, _, _, _, _, _), + [37] = PINGROUP(37, _, _, _, _, _, _, _, _, _), + [38] = PINGROUP(38, _, _, prng_rosc, _, _, _, _, _, _), + [39] = PINGROUP(39, _, _, _, _, _, _, _, _, _), + [40] = PINGROUP(40, _, _, cri_trng0, _, _, _, _, _, _), + [41] = PINGROUP(41, _, _, cri_trng1, _, _, _, _, _, _), + [42] = PINGROUP(42, _, qdss_gpio, native_char, _, _, _, _, _, _), + [43] = PINGROUP(43, _, _, _, _, _, _, _, _, _), + [44] = PINGROUP(44, coex_uart, _, _, _, _, _, _, _, _), + [45] = PINGROUP(45, coex_uart, ddr_pxi0, _, _, _, _, _, _, _), + [46] = PINGROUP(46, m_voc, ddr_bist, ddr_pxi0, _, _, _, _, _, _), + [47] = PINGROUP(47, ddr_bist, blsp_spi1, blsp_spi2, blsp_spi3, blsp_spi4, _, _, _, _), + [48] = PINGROUP(48, m_voc, blsp_uart1, blsp_uart4, ddr_bist, _, _, _, _, _), + [49] = PINGROUP(49, m_voc, blsp_uart1, blsp_uart4, ddr_bist, _, _, _, _, _), + [50] = PINGROUP(50, _, _, _, _, _, _, _, _, _), + [51] = PINGROUP(51, _, _, _, _, _, _, _, _, _), + [52] = PINGROUP(52, _, _, _, _, _, _, _, _, _), + [53] = PINGROUP(53, pci_e, _, _, _, _, _, _, _, _), + [54] = PINGROUP(54, qdss_cti, qdss_cti, _, _, _, _, _, _, _), + [55] = PINGROUP(55, qdss_cti, qdss_cti, tgu_ch0, _, _, _, _, _, _), + [56] = PINGROUP(56, pcie_clkreq, _, _, _, _, _, _, _, _), + [57] = PINGROUP(57, _, native_char, _, _, _, _, _, _, _), + [58] = PINGROUP(58, _, _, _, _, _, _, _, _, _), + [59] = PINGROUP(59, qdss_cti, m_voc, bimc_dte0, _, _, _, _, _, _), + [60] = PINGROUP(60, qdss_cti, _, m_voc, _, _, _, _, _, _), + [61] = PINGROUP(61, mgpi_clk, qlink2_wmss, bimc_dte1, _, _, _, _, _, _), + [62] = PINGROUP(62, i2s_mclk, audio_ref, blsp_spi1, blsp_spi2, blsp_spi3, blsp_spi4, ldo_update, _, _), + [63] = PINGROUP(63, blsp_uart2, _, qdss_gpio, atest_char, _, _, _, _, _), + [64] = PINGROUP(64, blsp_uart2, qdss_gpio, atest_char3, _, _, _, _, _, _), + [65] = PINGROUP(65, blsp_uart2, blsp_i2c2, qdss_cti, qdss_cti, _, qdss_gpio, atest_char2, _, _), + [66] = PINGROUP(66, blsp_uart2, blsp_i2c2, qdss_cti, qdss_cti, qdss_gpio, atest_char1, _, _, _), + [67] = PINGROUP(67, uim1_data, atest_char0, _, _, _, _, _, _, _), + [68] = PINGROUP(68, uim1_present, _, _, _, _, _, _, _, _), + [69] = PINGROUP(69, uim1_reset, _, _, _, _, _, _, _, _), + [70] = PINGROUP(70, uim1_clk, _, _, _, _, _, _, _, _), + [71] = PINGROUP(71, mgpi_clk, qlink2_en, _, _, _, _, _, _, _), + [72] = PINGROUP(72, qlink1_en, _, native_tsense, _, _, _, _, _, _), + [73] = PINGROUP(73, qlink1_req, _, _, _, _, _, _, _, _), + [74] = PINGROUP(74, qlink1_wmss, _, _, _, _, _, _, _, _), + [75] = PINGROUP(75, coex_uart2, spmi_coex, _, _, _, _, _, _, _), + [76] = PINGROUP(76, coex_uart2, spmi_coex, _, _, _, _, _, _, _), + [77] = PINGROUP(77, _, qlink2_req, _, _, _, _, _, _, _), + [78] = PINGROUP(78, spmi_vgi, _, _, _, _, _, _, _, _), + [79] = PINGROUP(79, spmi_vgi, _, _, _, _, _, _, _, _), + [80] = PINGROUP(80, _, blsp_spi1, _, blsp_uart1, _, _, _, _, _), + [81] = PINGROUP(81, _, blsp_spi1, _, blsp_uart1, gcc_plltest, _, _, _, _), + [82] = PINGROUP(82, _, blsp_spi1, _, blsp_i2c1, gcc_plltest, _, _, _, _), + [83] = PINGROUP(83, _, blsp_spi1, _, blsp_i2c1, _, _, _, _, _), + [84] = PINGROUP(84, _, ebi2_lcd, _, blsp_i2c4, _, _, _, _, _), + [85] = PINGROUP(85, _, ebi2_lcd, _, blsp_i2c4, _, _, _, _, _), + [86] = PINGROUP(86, _, _, _, _, _, _, _, _, _), + [87] = PINGROUP(87, _, _, _, _, _, _, _, _, _), + [88] = PINGROUP(88, _, _, _, _, _, _, _, _, _), + [89] = PINGROUP(89, _, _, _, _, ebi2_a, _, _, _, _), + [90] = PINGROUP(90, _, _, _, _, ebi2_lcd, _, _, _, _), + [91] = PINGROUP(91, _, _, _, _, _, _, _, _, _), + [92] = PINGROUP(92, _, _, _, _, _, _, _, _, _), + [93] = PINGROUP(93, _, _, usb2phy_ac, _, _, _, _, _, _), + [94] = PINGROUP(94, qdss_cti, qdss_cti, _, _, _, _, _, _, _), + [95] = PINGROUP(95, qdss_cti, qdss_cti, _, _, _, _, _, _, _), + [96] = PINGROUP(96, _, _, _, _, _, _, _, _, _), + [97] = PINGROUP(97, _, _, _, _, _, _, _, _, _), + [98] = PINGROUP(98, _, _, _, _, _, _, _, _, _), + [99] = PINGROUP(99, _, _, _, _, _, _, _, _, _), + [100] = PINGROUP(100, _, _, _, _, _, _, _, _, _), + [101] = PINGROUP(101, _, _, _, _, _, _, _, _, _), + [102] = PINGROUP(102, _, _, coex_uart2, _, _, _, _, _, _), + [103] = PINGROUP(103, _, _, coex_uart2, _, _, _, _, _, _), + [104] = PINGROUP(104, _, _, _, _, _, _, _, _, _), + [105] = PINGROUP(105, _, _, _, _, _, _, _, _, _), + [106] = PINGROUP(106, sdc1_tb, _, _, _, _, _, _, _, _), + [107] = PINGROUP(107, _, _, _, _, _, _, _, _, _), + [108] = UFS_RESET(ufs_reset, 0x0), + [109] = SDC_QDSD_PINGROUP(sdc1_rclk, 0x9a000, 15, 0), + [110] = SDC_QDSD_PINGROUP(sdc1_clk, 0x9a000, 13, 6), + [111] = SDC_QDSD_PINGROUP(sdc1_cmd, 0x9a000, 11, 3), + [112] = SDC_QDSD_PINGROUP(sdc1_data, 0x9a000, 9, 0), +}; + +static const struct msm_gpio_wakeirq_map sdx65_pdc_map[] = { + {1, 20}, {2, 21}, {5, 22}, {6, 23}, {9, 24}, {10, 25}, + {11, 26}, {12, 27}, {13, 28}, {14, 29}, {15, 30}, {16, 31}, + {17, 32}, {18, 33}, {19, 34}, {21, 35}, {22, 36}, {23, 70}, + {24, 37}, {25, 38}, {35, 40}, {43, 41}, {46, 44}, {48, 45}, + {49, 57}, {50, 46}, {52, 47}, {54, 49}, {55, 50}, {60, 53}, + {61, 54}, {64, 55}, {65, 81}, {68, 56}, {71, 58}, {73, 59}, + {77, 77}, {81, 65}, {83, 63}, {84, 64}, {86, 66}, {88, 67}, + {89, 68}, {90, 69}, {93, 71}, {94, 72}, {95, 73}, {96, 74}, + {99, 75}, {103, 78}, {104, 79} +}; + +static const struct msm_pinctrl_soc_data sdx65_pinctrl = { + .pins = sdx65_pins, + .npins = ARRAY_SIZE(sdx65_pins), + .functions = sdx65_functions, + .nfunctions = ARRAY_SIZE(sdx65_functions), + .groups = sdx65_groups, + .ngroups = ARRAY_SIZE(sdx65_groups), + .ngpios = 109, + .wakeirq_map = sdx65_pdc_map, + .nwakeirq_map = ARRAY_SIZE(sdx65_pdc_map), +}; + +static int sdx65_pinctrl_probe(struct platform_device *pdev) +{ + return msm_pinctrl_probe(pdev, &sdx65_pinctrl); +} + +static const struct of_device_id sdx65_pinctrl_of_match[] = { + { .compatible = "qcom,sdx65-tlmm", }, + { }, +}; + +static struct platform_driver sdx65_pinctrl_driver = { + .driver = { + .name = "sdx65-tlmm", + .of_match_table = sdx65_pinctrl_of_match, + }, + .probe = sdx65_pinctrl_probe, + .remove = msm_pinctrl_remove, +}; + +static int __init sdx65_pinctrl_init(void) +{ + return platform_driver_register(&sdx65_pinctrl_driver); +} +arch_initcall(sdx65_pinctrl_init); + +static void __exit sdx65_pinctrl_exit(void) +{ + platform_driver_unregister(&sdx65_pinctrl_driver); +} +module_exit(sdx65_pinctrl_exit); + +MODULE_DESCRIPTION("QTI sdx65 pinctrl driver"); +MODULE_LICENSE("GPL v2"); +MODULE_DEVICE_TABLE(of, sdx65_pinctrl_of_match); diff --git a/drivers/pinctrl/qcom/pinctrl-sdx75.c b/drivers/pinctrl/qcom/pinctrl-sdx75.c new file mode 100644 index 0000000000..3cfe8c7f04 --- /dev/null +++ b/drivers/pinctrl/qcom/pinctrl-sdx75.c @@ -0,0 +1,1143 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include <linux/module.h> +#include <linux/of.h> +#include <linux/platform_device.h> +#include "pinctrl-msm.h" + +#define REG_BASE 0x100000 +#define REG_SIZE 0x1000 + +#define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7, f8, f9, f10) \ + { \ + .grp = PINCTRL_PINGROUP("gpio"#id, gpio##id##_pins, \ + (unsigned int)ARRAY_SIZE(gpio##id##_pins)), \ + .ctl_reg = REG_BASE + REG_SIZE * id, \ + .io_reg = REG_BASE + 0x4 + REG_SIZE * id, \ + .intr_cfg_reg = REG_BASE + 0x8 + REG_SIZE * id, \ + .intr_status_reg = REG_BASE + 0xc + REG_SIZE * id, \ + .intr_target_reg = REG_BASE + 0x8 + REG_SIZE * id, \ + .mux_bit = 2, \ + .pull_bit = 0, \ + .drv_bit = 6, \ + .egpio_enable = 12, \ + .egpio_present = 11, \ + .oe_bit = 9, \ + .in_bit = 0, \ + .out_bit = 1, \ + .intr_enable_bit = 0, \ + .intr_status_bit = 0, \ + .intr_target_bit = 5, \ + .intr_target_kpss_val = 3, \ + .intr_raw_status_bit = 4, \ + .intr_polarity_bit = 1, \ + .intr_detection_bit = 2, \ + .intr_detection_width = 2, \ + .funcs = (int[]){ \ + msm_mux_gpio, /* gpio mode */ \ + msm_mux_##f1, \ + msm_mux_##f2, \ + msm_mux_##f3, \ + msm_mux_##f4, \ + msm_mux_##f5, \ + msm_mux_##f6, \ + msm_mux_##f7, \ + msm_mux_##f8, \ + msm_mux_##f9, \ + msm_mux_##f10 \ + }, \ + .nfuncs = 11, \ + } + +#define SDC_QDSD_PINGROUP(pg_name, ctl, pull, drv) \ + { \ + .grp = PINCTRL_PINGROUP(#pg_name, pg_name##_pins, \ + (unsigned int)ARRAY_SIZE(pg_name##_pins)), \ + .ctl_reg = ctl, \ + .io_reg = 0, \ + .intr_cfg_reg = 0, \ + .intr_status_reg = 0, \ + .intr_target_reg = 0, \ + .mux_bit = -1, \ + .pull_bit = pull, \ + .drv_bit = drv, \ + .oe_bit = -1, \ + .in_bit = -1, \ + .out_bit = -1, \ + .intr_enable_bit = -1, \ + .intr_status_bit = -1, \ + .intr_target_bit = -1, \ + .intr_raw_status_bit = -1, \ + .intr_polarity_bit = -1, \ + .intr_detection_bit = -1, \ + .intr_detection_width = -1, \ + } + +static const struct pinctrl_pin_desc sdx75_pins[] = { + PINCTRL_PIN(0, "GPIO_0"), + PINCTRL_PIN(1, "GPIO_1"), + PINCTRL_PIN(2, "GPIO_2"), + PINCTRL_PIN(3, "GPIO_3"), + PINCTRL_PIN(4, "GPIO_4"), + PINCTRL_PIN(5, "GPIO_5"), + PINCTRL_PIN(6, "GPIO_6"), + PINCTRL_PIN(7, "GPIO_7"), + PINCTRL_PIN(8, "GPIO_8"), + PINCTRL_PIN(9, "GPIO_9"), + PINCTRL_PIN(10, "GPIO_10"), + PINCTRL_PIN(11, "GPIO_11"), + PINCTRL_PIN(12, "GPIO_12"), + PINCTRL_PIN(13, "GPIO_13"), + PINCTRL_PIN(14, "GPIO_14"), + PINCTRL_PIN(15, "GPIO_15"), + PINCTRL_PIN(16, "GPIO_16"), + PINCTRL_PIN(17, "GPIO_17"), + PINCTRL_PIN(18, "GPIO_18"), + PINCTRL_PIN(19, "GPIO_19"), + PINCTRL_PIN(20, "GPIO_20"), + PINCTRL_PIN(21, "GPIO_21"), + PINCTRL_PIN(22, "GPIO_22"), + PINCTRL_PIN(23, "GPIO_23"), + PINCTRL_PIN(24, "GPIO_24"), + PINCTRL_PIN(25, "GPIO_25"), + PINCTRL_PIN(26, "GPIO_26"), + PINCTRL_PIN(27, "GPIO_27"), + PINCTRL_PIN(28, "GPIO_28"), + PINCTRL_PIN(29, "GPIO_29"), + PINCTRL_PIN(30, "GPIO_30"), + PINCTRL_PIN(31, "GPIO_31"), + PINCTRL_PIN(32, "GPIO_32"), + PINCTRL_PIN(33, "GPIO_33"), + PINCTRL_PIN(34, "GPIO_34"), + PINCTRL_PIN(35, "GPIO_35"), + PINCTRL_PIN(36, "GPIO_36"), + PINCTRL_PIN(37, "GPIO_37"), + PINCTRL_PIN(38, "GPIO_38"), + PINCTRL_PIN(39, "GPIO_39"), + PINCTRL_PIN(40, "GPIO_40"), + PINCTRL_PIN(41, "GPIO_41"), + PINCTRL_PIN(42, "GPIO_42"), + PINCTRL_PIN(43, "GPIO_43"), + PINCTRL_PIN(44, "GPIO_44"), + PINCTRL_PIN(45, "GPIO_45"), + PINCTRL_PIN(46, "GPIO_46"), + PINCTRL_PIN(47, "GPIO_47"), + PINCTRL_PIN(48, "GPIO_48"), + PINCTRL_PIN(49, "GPIO_49"), + PINCTRL_PIN(50, "GPIO_50"), + PINCTRL_PIN(51, "GPIO_51"), + PINCTRL_PIN(52, "GPIO_52"), + PINCTRL_PIN(53, "GPIO_53"), + PINCTRL_PIN(54, "GPIO_54"), + PINCTRL_PIN(55, "GPIO_55"), + PINCTRL_PIN(56, "GPIO_56"), + PINCTRL_PIN(57, "GPIO_57"), + PINCTRL_PIN(58, "GPIO_58"), + PINCTRL_PIN(59, "GPIO_59"), + PINCTRL_PIN(60, "GPIO_60"), + PINCTRL_PIN(61, "GPIO_61"), + PINCTRL_PIN(62, "GPIO_62"), + PINCTRL_PIN(63, "GPIO_63"), + PINCTRL_PIN(64, "GPIO_64"), + PINCTRL_PIN(65, "GPIO_65"), + PINCTRL_PIN(66, "GPIO_66"), + PINCTRL_PIN(67, "GPIO_67"), + PINCTRL_PIN(68, "GPIO_68"), + PINCTRL_PIN(69, "GPIO_69"), + PINCTRL_PIN(70, "GPIO_70"), + PINCTRL_PIN(71, "GPIO_71"), + PINCTRL_PIN(72, "GPIO_72"), + PINCTRL_PIN(73, "GPIO_73"), + PINCTRL_PIN(74, "GPIO_74"), + PINCTRL_PIN(75, "GPIO_75"), + PINCTRL_PIN(76, "GPIO_76"), + PINCTRL_PIN(77, "GPIO_77"), + PINCTRL_PIN(78, "GPIO_78"), + PINCTRL_PIN(79, "GPIO_79"), + PINCTRL_PIN(80, "GPIO_80"), + PINCTRL_PIN(81, "GPIO_81"), + PINCTRL_PIN(82, "GPIO_82"), + PINCTRL_PIN(83, "GPIO_83"), + PINCTRL_PIN(84, "GPIO_84"), + PINCTRL_PIN(85, "GPIO_85"), + PINCTRL_PIN(86, "GPIO_86"), + PINCTRL_PIN(87, "GPIO_87"), + PINCTRL_PIN(88, "GPIO_88"), + PINCTRL_PIN(89, "GPIO_89"), + PINCTRL_PIN(90, "GPIO_90"), + PINCTRL_PIN(91, "GPIO_91"), + PINCTRL_PIN(92, "GPIO_92"), + PINCTRL_PIN(93, "GPIO_93"), + PINCTRL_PIN(94, "GPIO_94"), + PINCTRL_PIN(95, "GPIO_95"), + PINCTRL_PIN(96, "GPIO_96"), + PINCTRL_PIN(97, "GPIO_97"), + PINCTRL_PIN(98, "GPIO_98"), + PINCTRL_PIN(99, "GPIO_99"), + PINCTRL_PIN(100, "GPIO_100"), + PINCTRL_PIN(101, "GPIO_101"), + PINCTRL_PIN(102, "GPIO_102"), + PINCTRL_PIN(103, "GPIO_103"), + PINCTRL_PIN(104, "GPIO_104"), + PINCTRL_PIN(105, "GPIO_105"), + PINCTRL_PIN(106, "GPIO_106"), + PINCTRL_PIN(107, "GPIO_107"), + PINCTRL_PIN(108, "GPIO_108"), + PINCTRL_PIN(109, "GPIO_109"), + PINCTRL_PIN(110, "GPIO_110"), + PINCTRL_PIN(111, "GPIO_111"), + PINCTRL_PIN(112, "GPIO_112"), + PINCTRL_PIN(113, "GPIO_113"), + PINCTRL_PIN(114, "GPIO_114"), + PINCTRL_PIN(115, "GPIO_115"), + PINCTRL_PIN(116, "GPIO_116"), + PINCTRL_PIN(117, "GPIO_117"), + PINCTRL_PIN(118, "GPIO_118"), + PINCTRL_PIN(119, "GPIO_119"), + PINCTRL_PIN(120, "GPIO_120"), + PINCTRL_PIN(121, "GPIO_121"), + PINCTRL_PIN(122, "GPIO_122"), + PINCTRL_PIN(123, "GPIO_123"), + PINCTRL_PIN(124, "GPIO_124"), + PINCTRL_PIN(125, "GPIO_125"), + PINCTRL_PIN(126, "GPIO_126"), + PINCTRL_PIN(127, "GPIO_127"), + PINCTRL_PIN(128, "GPIO_128"), + PINCTRL_PIN(129, "GPIO_129"), + PINCTRL_PIN(130, "GPIO_130"), + PINCTRL_PIN(131, "GPIO_131"), + PINCTRL_PIN(132, "GPIO_132"), + PINCTRL_PIN(133, "SDC1_RCLK"), + PINCTRL_PIN(134, "SDC1_CLK"), + PINCTRL_PIN(135, "SDC1_CMD"), + PINCTRL_PIN(136, "SDC1_DATA"), + PINCTRL_PIN(137, "SDC2_CLK"), + PINCTRL_PIN(138, "SDC2_CMD"), + PINCTRL_PIN(139, "SDC2_DATA"), +}; + +#define DECLARE_MSM_GPIO_PINS(pin) \ + static const unsigned int gpio##pin##_pins[] = {pin} +DECLARE_MSM_GPIO_PINS(0); +DECLARE_MSM_GPIO_PINS(1); +DECLARE_MSM_GPIO_PINS(2); +DECLARE_MSM_GPIO_PINS(3); +DECLARE_MSM_GPIO_PINS(4); +DECLARE_MSM_GPIO_PINS(5); +DECLARE_MSM_GPIO_PINS(6); +DECLARE_MSM_GPIO_PINS(7); +DECLARE_MSM_GPIO_PINS(8); +DECLARE_MSM_GPIO_PINS(9); +DECLARE_MSM_GPIO_PINS(10); +DECLARE_MSM_GPIO_PINS(11); +DECLARE_MSM_GPIO_PINS(12); +DECLARE_MSM_GPIO_PINS(13); +DECLARE_MSM_GPIO_PINS(14); +DECLARE_MSM_GPIO_PINS(15); +DECLARE_MSM_GPIO_PINS(16); +DECLARE_MSM_GPIO_PINS(17); +DECLARE_MSM_GPIO_PINS(18); +DECLARE_MSM_GPIO_PINS(19); +DECLARE_MSM_GPIO_PINS(20); +DECLARE_MSM_GPIO_PINS(21); +DECLARE_MSM_GPIO_PINS(22); +DECLARE_MSM_GPIO_PINS(23); +DECLARE_MSM_GPIO_PINS(24); +DECLARE_MSM_GPIO_PINS(25); +DECLARE_MSM_GPIO_PINS(26); +DECLARE_MSM_GPIO_PINS(27); +DECLARE_MSM_GPIO_PINS(28); +DECLARE_MSM_GPIO_PINS(29); +DECLARE_MSM_GPIO_PINS(30); +DECLARE_MSM_GPIO_PINS(31); +DECLARE_MSM_GPIO_PINS(32); +DECLARE_MSM_GPIO_PINS(33); +DECLARE_MSM_GPIO_PINS(34); +DECLARE_MSM_GPIO_PINS(35); +DECLARE_MSM_GPIO_PINS(36); +DECLARE_MSM_GPIO_PINS(37); +DECLARE_MSM_GPIO_PINS(38); +DECLARE_MSM_GPIO_PINS(39); +DECLARE_MSM_GPIO_PINS(40); +DECLARE_MSM_GPIO_PINS(41); +DECLARE_MSM_GPIO_PINS(42); +DECLARE_MSM_GPIO_PINS(43); +DECLARE_MSM_GPIO_PINS(44); +DECLARE_MSM_GPIO_PINS(45); +DECLARE_MSM_GPIO_PINS(46); +DECLARE_MSM_GPIO_PINS(47); +DECLARE_MSM_GPIO_PINS(48); +DECLARE_MSM_GPIO_PINS(49); +DECLARE_MSM_GPIO_PINS(50); +DECLARE_MSM_GPIO_PINS(51); +DECLARE_MSM_GPIO_PINS(52); +DECLARE_MSM_GPIO_PINS(53); +DECLARE_MSM_GPIO_PINS(54); +DECLARE_MSM_GPIO_PINS(55); +DECLARE_MSM_GPIO_PINS(56); +DECLARE_MSM_GPIO_PINS(57); +DECLARE_MSM_GPIO_PINS(58); +DECLARE_MSM_GPIO_PINS(59); +DECLARE_MSM_GPIO_PINS(60); +DECLARE_MSM_GPIO_PINS(61); +DECLARE_MSM_GPIO_PINS(62); +DECLARE_MSM_GPIO_PINS(63); +DECLARE_MSM_GPIO_PINS(64); +DECLARE_MSM_GPIO_PINS(65); +DECLARE_MSM_GPIO_PINS(66); +DECLARE_MSM_GPIO_PINS(67); +DECLARE_MSM_GPIO_PINS(68); +DECLARE_MSM_GPIO_PINS(69); +DECLARE_MSM_GPIO_PINS(70); +DECLARE_MSM_GPIO_PINS(71); +DECLARE_MSM_GPIO_PINS(72); +DECLARE_MSM_GPIO_PINS(73); +DECLARE_MSM_GPIO_PINS(74); +DECLARE_MSM_GPIO_PINS(75); +DECLARE_MSM_GPIO_PINS(76); +DECLARE_MSM_GPIO_PINS(77); +DECLARE_MSM_GPIO_PINS(78); +DECLARE_MSM_GPIO_PINS(79); +DECLARE_MSM_GPIO_PINS(80); +DECLARE_MSM_GPIO_PINS(81); +DECLARE_MSM_GPIO_PINS(82); +DECLARE_MSM_GPIO_PINS(83); +DECLARE_MSM_GPIO_PINS(84); +DECLARE_MSM_GPIO_PINS(85); +DECLARE_MSM_GPIO_PINS(86); +DECLARE_MSM_GPIO_PINS(87); +DECLARE_MSM_GPIO_PINS(88); +DECLARE_MSM_GPIO_PINS(89); +DECLARE_MSM_GPIO_PINS(90); +DECLARE_MSM_GPIO_PINS(91); +DECLARE_MSM_GPIO_PINS(92); +DECLARE_MSM_GPIO_PINS(93); +DECLARE_MSM_GPIO_PINS(94); +DECLARE_MSM_GPIO_PINS(95); +DECLARE_MSM_GPIO_PINS(96); +DECLARE_MSM_GPIO_PINS(97); +DECLARE_MSM_GPIO_PINS(98); +DECLARE_MSM_GPIO_PINS(99); +DECLARE_MSM_GPIO_PINS(100); +DECLARE_MSM_GPIO_PINS(101); +DECLARE_MSM_GPIO_PINS(102); +DECLARE_MSM_GPIO_PINS(103); +DECLARE_MSM_GPIO_PINS(104); +DECLARE_MSM_GPIO_PINS(105); +DECLARE_MSM_GPIO_PINS(106); +DECLARE_MSM_GPIO_PINS(107); +DECLARE_MSM_GPIO_PINS(108); +DECLARE_MSM_GPIO_PINS(109); +DECLARE_MSM_GPIO_PINS(110); +DECLARE_MSM_GPIO_PINS(111); +DECLARE_MSM_GPIO_PINS(112); +DECLARE_MSM_GPIO_PINS(113); +DECLARE_MSM_GPIO_PINS(114); +DECLARE_MSM_GPIO_PINS(115); +DECLARE_MSM_GPIO_PINS(116); +DECLARE_MSM_GPIO_PINS(117); +DECLARE_MSM_GPIO_PINS(118); +DECLARE_MSM_GPIO_PINS(119); +DECLARE_MSM_GPIO_PINS(120); +DECLARE_MSM_GPIO_PINS(121); +DECLARE_MSM_GPIO_PINS(122); +DECLARE_MSM_GPIO_PINS(123); +DECLARE_MSM_GPIO_PINS(124); +DECLARE_MSM_GPIO_PINS(125); +DECLARE_MSM_GPIO_PINS(126); +DECLARE_MSM_GPIO_PINS(127); +DECLARE_MSM_GPIO_PINS(128); +DECLARE_MSM_GPIO_PINS(129); +DECLARE_MSM_GPIO_PINS(130); +DECLARE_MSM_GPIO_PINS(131); +DECLARE_MSM_GPIO_PINS(132); + +static const unsigned int sdc1_rclk_pins[] = {133}; +static const unsigned int sdc1_clk_pins[] = {134}; +static const unsigned int sdc1_cmd_pins[] = {135}; +static const unsigned int sdc1_data_pins[] = {136}; +static const unsigned int sdc2_clk_pins[] = {137}; +static const unsigned int sdc2_cmd_pins[] = {138}; +static const unsigned int sdc2_data_pins[] = {139}; + +enum sdx75_functions { + msm_mux_adsp_ext, + msm_mux_atest_char, + msm_mux_audio_ref_clk, + msm_mux_bimc_dte, + msm_mux_char_exec, + msm_mux_coex_uart2, + msm_mux_coex_uart, + msm_mux_cri_trng, + msm_mux_cri_trng0, + msm_mux_cri_trng1, + msm_mux_dbg_out_clk, + msm_mux_ddr_bist, + msm_mux_ddr_pxi0, + msm_mux_ebi0_wrcdc, + msm_mux_ebi2_a, + msm_mux_ebi2_lcd, + msm_mux_ebi2_lcd_te, + msm_mux_emac0_mcg, + msm_mux_emac0_ptp, + msm_mux_emac1_mcg, + msm_mux_emac1_ptp, + msm_mux_emac_cdc, + msm_mux_emac_pps_in, + msm_mux_eth0_mdc, + msm_mux_eth0_mdio, + msm_mux_eth1_mdc, + msm_mux_eth1_mdio, + msm_mux_ext_dbg, + msm_mux_gcc_125_clk, + msm_mux_gcc_gp1_clk, + msm_mux_gcc_gp2_clk, + msm_mux_gcc_gp3_clk, + msm_mux_gcc_plltest, + msm_mux_gpio, + msm_mux_i2s_mclk, + msm_mux_jitter_bist, + msm_mux_ldo_en, + msm_mux_ldo_update, + msm_mux_m_voc, + msm_mux_mgpi_clk, + msm_mux_native_char, + msm_mux_native_tsens, + msm_mux_native_tsense, + msm_mux_nav_dr_sync, + msm_mux_nav_gpio, + msm_mux_pa_indicator, + msm_mux_pci_e, + msm_mux_pcie0_clkreq_n, + msm_mux_pcie1_clkreq_n, + msm_mux_pcie2_clkreq_n, + msm_mux_pll_bist_sync, + msm_mux_pll_clk_aux, + msm_mux_pll_ref_clk, + msm_mux_pri_mi2s, + msm_mux_prng_rosc, + msm_mux_qdss_cti, + msm_mux_qdss_gpio, + msm_mux_qlink0_b_en, + msm_mux_qlink0_b_req, + msm_mux_qlink0_l_en, + msm_mux_qlink0_l_req, + msm_mux_qlink0_wmss, + msm_mux_qlink1_l_en, + msm_mux_qlink1_l_req, + msm_mux_qlink1_wmss, + msm_mux_qup_se0, + msm_mux_qup_se1_l2_mira, + msm_mux_qup_se1_l2_mirb, + msm_mux_qup_se1_l3_mira, + msm_mux_qup_se1_l3_mirb, + msm_mux_qup_se2, + msm_mux_qup_se3, + msm_mux_qup_se4, + msm_mux_qup_se5, + msm_mux_qup_se6, + msm_mux_qup_se7, + msm_mux_qup_se8, + msm_mux_rgmii_rx_ctl, + msm_mux_rgmii_rxc, + msm_mux_rgmii_rxd, + msm_mux_rgmii_tx_ctl, + msm_mux_rgmii_txc, + msm_mux_rgmii_txd, + msm_mux_sd_card, + msm_mux_sdc1_tb, + msm_mux_sdc2_tb_trig, + msm_mux_sec_mi2s, + msm_mux_sgmii_phy_intr0_n, + msm_mux_sgmii_phy_intr1_n, + msm_mux_spmi_coex, + msm_mux_spmi_vgi, + msm_mux_tgu_ch0_trigout, + msm_mux_tmess_prng0, + msm_mux_tmess_prng1, + msm_mux_tmess_prng2, + msm_mux_tmess_prng3, + msm_mux_tri_mi2s, + msm_mux_uim1_clk, + msm_mux_uim1_data, + msm_mux_uim1_present, + msm_mux_uim1_reset, + msm_mux_uim2_clk, + msm_mux_uim2_data, + msm_mux_uim2_present, + msm_mux_uim2_reset, + msm_mux_usb2phy_ac_en, + msm_mux_vsense_trigger_mirnat, + msm_mux__, +}; + +static const char *const gpio_groups[] = { + "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", + "gpio7", "gpio8", "gpio9", "gpio10", "gpio11", "gpio12", "gpio13", + "gpio14", "gpio15", "gpio16", "gpio17", "gpio18", "gpio19", "gpio20", + "gpio21", "gpio22", "gpio23", "gpio24", "gpio25", "gpio26", "gpio27", + "gpio28", "gpio29", "gpio30", "gpio31", "gpio32", "gpio33", "gpio34", + "gpio35", "gpio36", "gpio37", "gpio38", "gpio39", "gpio40", "gpio41", + "gpio42", "gpio43", "gpio44", "gpio45", "gpio46", "gpio47", "gpio48", + "gpio49", "gpio50", "gpio51", "gpio52", "gpio53", "gpio54", "gpio55", + "gpio56", "gpio57", "gpio58", "gpio59", "gpio60", "gpio61", "gpio62", + "gpio63", "gpio64", "gpio65", "gpio66", "gpio67", "gpio68", "gpio69", + "gpio70", "gpio71", "gpio72", "gpio73", "gpio74", "gpio75", "gpio76", + "gpio77", "gpio78", "gpio79", "gpio80", "gpio81", "gpio82", "gpio83", + "gpio84", "gpio85", "gpio86", "gpio87", "gpio88", "gpio89", "gpio90", + "gpio91", "gpio92", "gpio93", "gpio94", "gpio95", "gpio96", "gpio97", + "gpio98", "gpio99", "gpio100", "gpio101", "gpio102", "gpio103", "gpio104", + "gpio105", "gpio106", "gpio107", "gpio108", "gpio109", "gpio110", "gpio111", + "gpio112", "gpio113", "gpio114", "gpio115", "gpio116", "gpio117", "gpio118", + "gpio119", "gpio120", "gpio121", "gpio122", "gpio123", "gpio124", "gpio125", + "gpio126", "gpio127", "gpio128", "gpio129", "gpio130", "gpio131", "gpio132", +}; +static const char *const adsp_ext_groups[] = { + "gpio59", "gpio68", +}; +static const char *const atest_char_groups[] = { + "gpio24", "gpio25", "gpio26", "gpio41", "gpio63", +}; +static const char *const audio_ref_clk_groups[] = { + "gpio126", +}; +static const char *const bimc_dte_groups[] = { + "gpio14", "gpio15", "gpio61", "gpio59", +}; +static const char *const char_exec_groups[] = { + "gpio6", "gpio7", +}; +static const char *const coex_uart2_groups[] = { + "gpio48", "gpio49", "gpio90", "gpio91", +}; +static const char *const coex_uart_groups[] = { + "gpio46", "gpio47", +}; +static const char *const cri_trng_groups[] = { + "gpio36", +}; +static const char *const cri_trng0_groups[] = { + "gpio31", +}; +static const char *const cri_trng1_groups[] = { + "gpio32", +}; +static const char *const dbg_out_clk_groups[] = { + "gpio26", +}; +static const char *const ddr_bist_groups[] = { + "gpio46", "gpio47", "gpio48", "gpio49", +}; +static const char *const ddr_pxi0_groups[] = { + "gpio45", "gpio46", +}; +static const char *const ebi0_wrcdc_groups[] = { + "gpio0", "gpio2", +}; +static const char *const ebi2_a_groups[] = { + "gpio100", +}; +static const char *const ebi2_lcd_groups[] = { + "gpio99", "gpio101", +}; +static const char *const ebi2_lcd_te_groups[] = { + "gpio98", +}; +static const char *const emac0_mcg_groups[] = { + "gpio83", "gpio84", "gpio85", "gpio89", +}; +static const char *const emac0_ptp_groups[] = { + "gpio35", "gpio83", "gpio84", "gpio85", "gpio89", "gpio119", "gpio123", +}; +static const char *const emac1_mcg_groups[] = { + "gpio90", "gpio92", "gpio93", "gpio122", +}; +static const char *const emac1_ptp_groups[] = { + "gpio112", "gpio113", "gpio114", "gpio115", +}; +static const char *const emac_cdc_groups[] = { + "gpio38", "gpio39", +}; +static const char *const emac_pps_in_groups[] = { + "gpio127", +}; +static const char *const eth0_mdc_groups[] = { + "gpio94", +}; +static const char *const eth0_mdio_groups[] = { + "gpio95", +}; +static const char *const eth1_mdc_groups[] = { + "gpio106", +}; +static const char *const eth1_mdio_groups[] = { + "gpio107", +}; +static const char *const ext_dbg_groups[] = { + "gpio12", "gpio13", "gpio14", "gpio15", +}; +static const char *const gcc_125_clk_groups[] = { + "gpio25", +}; +static const char *const gcc_gp1_clk_groups[] = { + "gpio39", +}; +static const char *const gcc_gp2_clk_groups[] = { + "gpio40", +}; +static const char *const gcc_gp3_clk_groups[] = { + "gpio41", +}; +static const char *const gcc_plltest_groups[] = { + "gpio81", "gpio82", +}; +static const char *const i2s_mclk_groups[] = { + "gpio74", +}; +static const char *const jitter_bist_groups[] = { + "gpio41", +}; +static const char *const ldo_en_groups[] = { + "gpio8", +}; +static const char *const ldo_update_groups[] = { + "gpio62", +}; +static const char *const m_voc_groups[] = { + "gpio62", "gpio63", "gpio64", "gpio65", "gpio71", +}; +static const char *const mgpi_clk_groups[] = { + "gpio39", "gpio40", +}; +static const char *const native_char_groups[] = { + "gpio29", "gpio33", "gpio57", "gpio66", "gpio67", +}; +static const char *const native_tsens_groups[] = { + "gpio38", +}; +static const char *const native_tsense_groups[] = { + "gpio64", "gpio76", +}; +static const char *const nav_dr_sync_groups[] = { + "gpio36", +}; +static const char *const nav_gpio_groups[] = { + "gpio35", "gpio36", "gpio104", +}; +static const char *const pa_indicator_groups[] = { + "gpio58", +}; +static const char *const pci_e_groups[] = { + "gpio42", +}; +static const char *const pcie0_clkreq_n_groups[] = { + "gpio43", +}; +static const char *const pcie1_clkreq_n_groups[] = { + "gpio124", +}; +static const char *const pcie2_clkreq_n_groups[] = { + "gpio121", +}; +static const char *const pll_bist_sync_groups[] = { + "gpio38", +}; +static const char *const pll_clk_aux_groups[] = { + "gpio40", +}; +static const char *const pll_ref_clk_groups[] = { + "gpio37", +}; +static const char *const pri_mi2s_groups[] = { + "gpio16", "gpio17", "gpio18", "gpio19", +}; +static const char *const prng_rosc_groups[] = { + "gpio27", "gpio36", "gpio37", "gpio38", +}; +static const char *const qdss_cti_groups[] = { + "gpio16", "gpio17", "gpio52", "gpio53", "gpio56", + "gpio57", "gpio59", "gpio60", "gpio78", "gpio79", +}; +static const char *const qdss_gpio_groups[] = { + "gpio82", "gpio83", "gpio84", "gpio85", "gpio94", + "gpio95", "gpio96", "gpio97", "gpio110", "gpio111", + "gpio112", "gpio113", "gpio114", "gpio115", "gpio116", + "gpio117", "gpio118", "gpio119", +}; +static const char *const qlink0_b_en_groups[] = { + "gpio40", +}; +static const char *const qlink0_b_req_groups[] = { + "gpio41", +}; +static const char *const qlink0_l_en_groups[] = { + "gpio37", +}; +static const char *const qlink0_l_req_groups[] = { + "gpio38", +}; +static const char *const qlink0_wmss_groups[] = { + "gpio39", +}; +static const char *const qlink1_l_en_groups[] = { + "gpio26", +}; +static const char *const qlink1_l_req_groups[] = { + "gpio27", +}; +static const char *const qlink1_wmss_groups[] = { + "gpio28", +}; +static const char *const qup_se0_groups[] = { + "gpio8", "gpio9", "gpio10", "gpio11", +}; +static const char *const qup_se1_l2_mira_groups[] = { + "gpio12", +}; +static const char *const qup_se1_l2_mirb_groups[] = { + "gpio16", +}; +static const char *const qup_se1_l3_mira_groups[] = { + "gpio13", +}; +static const char *const qup_se1_l3_mirb_groups[] = { + "gpio17", +}; +static const char *const qup_se2_groups[] = { + "gpio14", "gpio15", "gpio16", "gpio17", +}; +static const char *const qup_se3_groups[] = { + "gpio52", "gpio53", "gpio54", "gpio55", +}; +static const char *const qup_se4_groups[] = { + "gpio64", "gpio65", +}; +static const char *const qup_se5_groups[] = { + "gpio110", "gpio111", +}; +static const char *const qup_se6_groups[] = { + "gpio112", "gpio113", "gpio114", "gpio115", +}; +static const char *const qup_se7_groups[] = { + "gpio116", "gpio117", "gpio118", "gpio119", +}; +static const char *const qup_se8_groups[] = { + "gpio124", "gpio125", +}; +static const char *const rgmii_rx_ctl_groups[] = { + "gpio93", +}; +static const char *const rgmii_rxc_groups[] = { + "gpio88", +}; +static const char *const rgmii_rxd_groups[] = { + "gpio89", "gpio90", "gpio91", "gpio92", +}; +static const char *const rgmii_tx_ctl_groups[] = { + "gpio87", +}; +static const char *const rgmii_txc_groups[] = { + "gpio82", +}; +static const char *const rgmii_txd_groups[] = { + "gpio83", "gpio84", "gpio85", "gpio86", +}; +static const char *const sd_card_groups[] = { + "gpio105", +}; +static const char *const sdc1_tb_groups[] = { + "gpio84", "gpio130", +}; +static const char *const sdc2_tb_trig_groups[] = { + "gpio129", +}; +static const char *const sec_mi2s_groups[] = { + "gpio20", "gpio21", "gpio22", "gpio23", +}; +static const char *const sgmii_phy_intr0_n_groups[] = { + "gpio97", +}; +static const char *const sgmii_phy_intr1_n_groups[] = { + "gpio109", +}; +static const char *const spmi_coex_groups[] = { + "gpio48", "gpio49", +}; +static const char *const spmi_vgi_groups[] = { + "gpio50", "gpio51", +}; +static const char *const tgu_ch0_trigout_groups[] = { + "gpio55", +}; +static const char *const tmess_prng0_groups[] = { + "gpio28", +}; +static const char *const tmess_prng1_groups[] = { + "gpio29", +}; +static const char *const tmess_prng2_groups[] = { + "gpio30", +}; +static const char *const tmess_prng3_groups[] = { + "gpio31", +}; +static const char *const tri_mi2s_groups[] = { + "gpio98", "gpio99", "gpio100", "gpio101", +}; +static const char *const uim1_clk_groups[] = { + "gpio7", +}; +static const char *const uim1_data_groups[] = { + "gpio4", +}; +static const char *const uim1_present_groups[] = { + "gpio5", +}; +static const char *const uim1_reset_groups[] = { + "gpio6", +}; +static const char *const uim2_clk_groups[] = { + "gpio3", +}; +static const char *const uim2_data_groups[] = { + "gpio0", +}; +static const char *const uim2_present_groups[] = { + "gpio1", +}; +static const char *const uim2_reset_groups[] = { + "gpio2", +}; +static const char *const usb2phy_ac_en_groups[] = { + "gpio80", +}; +static const char *const vsense_trigger_mirnat_groups[] = { + "gpio37", +}; + +static const struct pinfunction sdx75_functions[] = { + MSM_PIN_FUNCTION(adsp_ext), + MSM_PIN_FUNCTION(atest_char), + MSM_PIN_FUNCTION(audio_ref_clk), + MSM_PIN_FUNCTION(bimc_dte), + MSM_PIN_FUNCTION(char_exec), + MSM_PIN_FUNCTION(coex_uart2), + MSM_PIN_FUNCTION(coex_uart), + MSM_PIN_FUNCTION(cri_trng), + MSM_PIN_FUNCTION(cri_trng0), + MSM_PIN_FUNCTION(cri_trng1), + MSM_PIN_FUNCTION(dbg_out_clk), + MSM_PIN_FUNCTION(ddr_bist), + MSM_PIN_FUNCTION(ddr_pxi0), + MSM_PIN_FUNCTION(ebi0_wrcdc), + MSM_PIN_FUNCTION(ebi2_a), + MSM_PIN_FUNCTION(ebi2_lcd), + MSM_PIN_FUNCTION(ebi2_lcd_te), + MSM_PIN_FUNCTION(emac0_mcg), + MSM_PIN_FUNCTION(emac0_ptp), + MSM_PIN_FUNCTION(emac1_mcg), + MSM_PIN_FUNCTION(emac1_ptp), + MSM_PIN_FUNCTION(emac_cdc), + MSM_PIN_FUNCTION(emac_pps_in), + MSM_PIN_FUNCTION(eth0_mdc), + MSM_PIN_FUNCTION(eth0_mdio), + MSM_PIN_FUNCTION(eth1_mdc), + MSM_PIN_FUNCTION(eth1_mdio), + MSM_PIN_FUNCTION(ext_dbg), + MSM_PIN_FUNCTION(gcc_125_clk), + MSM_PIN_FUNCTION(gcc_gp1_clk), + MSM_PIN_FUNCTION(gcc_gp2_clk), + MSM_PIN_FUNCTION(gcc_gp3_clk), + MSM_PIN_FUNCTION(gcc_plltest), + MSM_PIN_FUNCTION(gpio), + MSM_PIN_FUNCTION(i2s_mclk), + MSM_PIN_FUNCTION(jitter_bist), + MSM_PIN_FUNCTION(ldo_en), + MSM_PIN_FUNCTION(ldo_update), + MSM_PIN_FUNCTION(m_voc), + MSM_PIN_FUNCTION(mgpi_clk), + MSM_PIN_FUNCTION(native_char), + MSM_PIN_FUNCTION(native_tsens), + MSM_PIN_FUNCTION(native_tsense), + MSM_PIN_FUNCTION(nav_dr_sync), + MSM_PIN_FUNCTION(nav_gpio), + MSM_PIN_FUNCTION(pa_indicator), + MSM_PIN_FUNCTION(pci_e), + MSM_PIN_FUNCTION(pcie0_clkreq_n), + MSM_PIN_FUNCTION(pcie1_clkreq_n), + MSM_PIN_FUNCTION(pcie2_clkreq_n), + MSM_PIN_FUNCTION(pll_bist_sync), + MSM_PIN_FUNCTION(pll_clk_aux), + MSM_PIN_FUNCTION(pll_ref_clk), + MSM_PIN_FUNCTION(pri_mi2s), + MSM_PIN_FUNCTION(prng_rosc), + MSM_PIN_FUNCTION(qdss_cti), + MSM_PIN_FUNCTION(qdss_gpio), + MSM_PIN_FUNCTION(qlink0_b_en), + MSM_PIN_FUNCTION(qlink0_b_req), + MSM_PIN_FUNCTION(qlink0_l_en), + MSM_PIN_FUNCTION(qlink0_l_req), + MSM_PIN_FUNCTION(qlink1_l_en), + MSM_PIN_FUNCTION(qlink1_l_req), + MSM_PIN_FUNCTION(qlink0_wmss), + MSM_PIN_FUNCTION(qlink1_wmss), + MSM_PIN_FUNCTION(qup_se0), + MSM_PIN_FUNCTION(qup_se1_l2_mira), + MSM_PIN_FUNCTION(qup_se1_l2_mirb), + MSM_PIN_FUNCTION(qup_se1_l3_mira), + MSM_PIN_FUNCTION(qup_se1_l3_mirb), + MSM_PIN_FUNCTION(qup_se2), + MSM_PIN_FUNCTION(qup_se3), + MSM_PIN_FUNCTION(qup_se4), + MSM_PIN_FUNCTION(qup_se5), + MSM_PIN_FUNCTION(qup_se6), + MSM_PIN_FUNCTION(qup_se7), + MSM_PIN_FUNCTION(qup_se8), + MSM_PIN_FUNCTION(rgmii_rx_ctl), + MSM_PIN_FUNCTION(rgmii_rxc), + MSM_PIN_FUNCTION(rgmii_rxd), + MSM_PIN_FUNCTION(rgmii_tx_ctl), + MSM_PIN_FUNCTION(rgmii_txc), + MSM_PIN_FUNCTION(rgmii_txd), + MSM_PIN_FUNCTION(sd_card), + MSM_PIN_FUNCTION(sdc1_tb), + MSM_PIN_FUNCTION(sdc2_tb_trig), + MSM_PIN_FUNCTION(sec_mi2s), + MSM_PIN_FUNCTION(sgmii_phy_intr0_n), + MSM_PIN_FUNCTION(sgmii_phy_intr1_n), + MSM_PIN_FUNCTION(spmi_coex), + MSM_PIN_FUNCTION(spmi_vgi), + MSM_PIN_FUNCTION(tgu_ch0_trigout), + MSM_PIN_FUNCTION(tmess_prng0), + MSM_PIN_FUNCTION(tmess_prng1), + MSM_PIN_FUNCTION(tmess_prng2), + MSM_PIN_FUNCTION(tmess_prng3), + MSM_PIN_FUNCTION(tri_mi2s), + MSM_PIN_FUNCTION(uim1_clk), + MSM_PIN_FUNCTION(uim1_data), + MSM_PIN_FUNCTION(uim1_present), + MSM_PIN_FUNCTION(uim1_reset), + MSM_PIN_FUNCTION(uim2_clk), + MSM_PIN_FUNCTION(uim2_data), + MSM_PIN_FUNCTION(uim2_present), + MSM_PIN_FUNCTION(uim2_reset), + MSM_PIN_FUNCTION(usb2phy_ac_en), + MSM_PIN_FUNCTION(vsense_trigger_mirnat), +}; + +static const struct msm_pingroup sdx75_groups[] = { + [0] = PINGROUP(0, uim2_data, ebi0_wrcdc, _, _, _, _, _, _, _, _), + [1] = PINGROUP(1, uim2_present, _, _, _, _, _, _, _, _, _), + [2] = PINGROUP(2, uim2_reset, ebi0_wrcdc, _, _, _, _, _, _, _, _), + [3] = PINGROUP(3, uim2_clk, _, _, _, _, _, _, _, _, _), + [4] = PINGROUP(4, uim1_data, _, _, _, _, _, _, _, _, _), + [5] = PINGROUP(5, uim1_present, _, _, _, _, _, _, _, _, _), + [6] = PINGROUP(6, uim1_reset, char_exec, _, _, _, _, _, _, _, _), + [7] = PINGROUP(7, uim1_clk, char_exec, _, _, _, _, _, _, _, _), + [8] = PINGROUP(8, qup_se0, ldo_en, _, _, _, _, _, _, _, _), + [9] = PINGROUP(9, qup_se0, _, _, _, _, _, _, _, _, _), + [10] = PINGROUP(10, qup_se0, _, _, _, _, _, _, _, _, _), + [11] = PINGROUP(11, qup_se0, _, _, _, _, _, _, _, _, _), + [12] = PINGROUP(12, qup_se1_l2_mira, ext_dbg, _, _, _, _, _, _, _, _), + [13] = PINGROUP(13, qup_se1_l3_mira, ext_dbg, _, _, _, _, _, _, _, _), + [14] = PINGROUP(14, qup_se2, ext_dbg, bimc_dte, _, _, _, _, _, _, _), + [15] = PINGROUP(15, qup_se2, ext_dbg, bimc_dte, _, _, _, _, _, _, _), + [16] = PINGROUP(16, pri_mi2s, qup_se2, qup_se1_l2_mirb, qdss_cti, qdss_cti, _, _, _, _, _), + [17] = PINGROUP(17, pri_mi2s, qup_se2, qup_se1_l3_mirb, qdss_cti, qdss_cti, _, _, _, _, _), + [18] = PINGROUP(18, pri_mi2s, _, _, _, _, _, _, _, _, _), + [19] = PINGROUP(19, pri_mi2s, _, _, _, _, _, _, _, _, _), + [20] = PINGROUP(20, sec_mi2s, _, _, _, _, _, _, _, _, _), + [21] = PINGROUP(21, sec_mi2s, _, _, _, _, _, _, _, _, _), + [22] = PINGROUP(22, sec_mi2s, _, _, _, _, _, _, _, _, _), + [23] = PINGROUP(23, sec_mi2s, _, _, _, _, _, _, _, _, _), + [24] = PINGROUP(24, _, atest_char, _, _, _, _, _, _, _, _), + [25] = PINGROUP(25, gcc_125_clk, _, atest_char, _, _, _, _, _, _, _), + [26] = PINGROUP(26, _, _, qlink1_l_en, dbg_out_clk, atest_char, _, _, _, _, _), + [27] = PINGROUP(27, _, _, qlink1_l_req, prng_rosc, _, _, _, _, _, _), + [28] = PINGROUP(28, _, qlink1_wmss, tmess_prng0, _, _, _, _, _, _, _), + [29] = PINGROUP(29, _, _, _, native_char, tmess_prng1, _, _, _, _, _), + [30] = PINGROUP(30, _, _, _, tmess_prng2, _, _, _, _, _, _), + [31] = PINGROUP(31, _, _, cri_trng0, _, tmess_prng3, _, _, _, _, _), + [32] = PINGROUP(32, _, _, cri_trng1, _, _, _, _, _, _, _), + [33] = PINGROUP(33, _, _, native_char, _, _, _, _, _, _, _), + [34] = PINGROUP(34, _, _, _, _, _, _, _, _, _, _), + [35] = PINGROUP(35, nav_gpio, emac0_ptp, emac0_ptp, _, _, _, _, _, _, _), + [36] = PINGROUP(36, nav_gpio, nav_dr_sync, nav_gpio, cri_trng, prng_rosc, _, _, _, _, _), + [37] = PINGROUP(37, qlink0_l_en, _, pll_ref_clk, prng_rosc, vsense_trigger_mirnat, _, _, _, _, _), + [38] = PINGROUP(38, qlink0_l_req, _, pll_bist_sync, prng_rosc, _, emac_cdc, _, native_tsens, _, _), + [39] = PINGROUP(39, qlink0_wmss, _, mgpi_clk, gcc_gp1_clk, _, emac_cdc, _, _, _, _), + [40] = PINGROUP(40, qlink0_b_en, _, mgpi_clk, pll_clk_aux, gcc_gp2_clk, _, _, _, _, _), + [41] = PINGROUP(41, qlink0_b_req, _, jitter_bist, gcc_gp3_clk, _, _, atest_char, _, _, _), + [42] = PINGROUP(42, pci_e, _, _, _, _, _, _, _, _, _), + [43] = PINGROUP(43, pcie0_clkreq_n, _, _, _, _, _, _, _, _, _), + [44] = PINGROUP(44, _, _, _, _, _, _, _, _, _, _), + [45] = PINGROUP(45, ddr_pxi0, _, _, _, _, _, _, _, _, _), + [46] = PINGROUP(46, coex_uart, ddr_bist, ddr_pxi0, _, _, _, _, _, _, _), + [47] = PINGROUP(47, coex_uart, ddr_bist, _, _, _, _, _, _, _, _), + [48] = PINGROUP(48, coex_uart2, spmi_coex, ddr_bist, _, _, _, _, _, _, _), + [49] = PINGROUP(49, coex_uart2, spmi_coex, ddr_bist, _, _, _, _, _, _, _), + [50] = PINGROUP(50, spmi_vgi, _, _, _, _, _, _, _, _, _), + [51] = PINGROUP(51, spmi_vgi, _, _, _, _, _, _, _, _, _), + [52] = PINGROUP(52, qup_se3, qdss_cti, qdss_cti, _, _, _, _, _, _, _), + [53] = PINGROUP(53, qup_se3, qdss_cti, qdss_cti, _, _, _, _, _, _, _), + [54] = PINGROUP(54, qup_se3, _, _, _, _, _, _, _, _, _), + [55] = PINGROUP(55, qup_se3, tgu_ch0_trigout, _, _, _, _, _, _, _, _), + [56] = PINGROUP(56, qdss_cti, qdss_cti, _, _, _, _, _, _, _, _), + [57] = PINGROUP(57, qdss_cti, qdss_cti, _, native_char, _, _, _, _, _, _), + [58] = PINGROUP(58, _, pa_indicator, _, _, _, _, _, _, _, _), + [59] = PINGROUP(59, adsp_ext, qdss_cti, _, bimc_dte, _, _, _, _, _, _), + [60] = PINGROUP(60, qdss_cti, _, _, _, _, _, _, _, _, _), + [61] = PINGROUP(61, _, bimc_dte, _, _, _, _, _, _, _, _), + [62] = PINGROUP(62, m_voc, ldo_update, _, _, _, _, _, _, _, _), + [63] = PINGROUP(63, m_voc, _, atest_char, _, _, _, _, _, _, _), + [64] = PINGROUP(64, qup_se4, m_voc, _, native_tsense, _, _, _, _, _, _), + [65] = PINGROUP(65, qup_se4, m_voc, _, _, _, _, _, _, _, _), + [66] = PINGROUP(66, _, native_char, _, _, _, _, _, _, _, _), + [67] = PINGROUP(67, _, native_char, _, _, _, _, _, _, _, _), + [68] = PINGROUP(68, adsp_ext, _, _, _, _, _, _, _, _, _), + [69] = PINGROUP(69, _, _, _, _, _, _, _, _, _, _), + [70] = PINGROUP(70, _, _, _, _, _, _, _, _, _, _), + [71] = PINGROUP(71, m_voc, _, _, _, _, _, _, _, _, _), + [72] = PINGROUP(72, _, _, _, _, _, _, _, _, _, _), + [73] = PINGROUP(73, _, _, _, _, _, _, _, _, _, _), + [74] = PINGROUP(74, i2s_mclk, _, _, _, _, _, _, _, _, _), + [75] = PINGROUP(75, _, _, _, _, _, _, _, _, _, _), + [76] = PINGROUP(76, native_tsense, _, _, _, _, _, _, _, _, _), + [77] = PINGROUP(77, _, _, _, _, _, _, _, _, _, _), + [78] = PINGROUP(78, qdss_cti, qdss_cti, _, _, _, _, _, _, _, _), + [79] = PINGROUP(79, qdss_cti, qdss_cti, _, _, _, _, _, _, _, _), + [80] = PINGROUP(80, usb2phy_ac_en, _, _, _, _, _, _, _, _, _), + [81] = PINGROUP(81, gcc_plltest, _, _, _, _, _, _, _, _, _), + [82] = PINGROUP(82, rgmii_txc, gcc_plltest, qdss_gpio, _, _, _, _, _, _, _), + [83] = PINGROUP(83, rgmii_txd, emac0_ptp, emac0_ptp, emac0_mcg, qdss_gpio, _, _, _, _, _), + [84] = PINGROUP(84, rgmii_txd, emac0_ptp, emac0_mcg, qdss_gpio, _, sdc1_tb, _, _, _, _), + [85] = PINGROUP(85, rgmii_txd, emac0_ptp, emac0_mcg, qdss_gpio, _, _, _, _, _, _), + [86] = PINGROUP(86, rgmii_txd, _, _, _, _, _, _, _, _, _), + [87] = PINGROUP(87, rgmii_tx_ctl, _, _, _, _, _, _, _, _, _), + [88] = PINGROUP(88, rgmii_rxc, _, _, _, _, _, _, _, _, _), + [89] = PINGROUP(89, rgmii_rxd, emac0_ptp, emac0_ptp, emac0_mcg, _, _, _, _, _, _), + [90] = PINGROUP(90, rgmii_rxd, coex_uart2, emac1_mcg, _, _, _, _, _, _, _), + [91] = PINGROUP(91, rgmii_rxd, coex_uart2, _, _, _, _, _, _, _, _), + [92] = PINGROUP(92, rgmii_rxd, emac1_mcg, _, _, _, _, _, _, _, _), + [93] = PINGROUP(93, rgmii_rx_ctl, emac1_mcg, _, _, _, _, _, _, _, _), + [94] = PINGROUP(94, eth0_mdc, qdss_gpio, _, _, _, _, _, _, _, _), + [95] = PINGROUP(95, eth0_mdio, qdss_gpio, _, _, _, _, _, _, _, _), + [96] = PINGROUP(96, qdss_gpio, _, _, _, _, _, _, _, _, _), + [97] = PINGROUP(97, sgmii_phy_intr0_n, _, qdss_gpio, _, _, _, _, _, _, _), + [98] = PINGROUP(98, tri_mi2s, ebi2_lcd_te, _, _, _, _, _, _, _, _), + [99] = PINGROUP(99, tri_mi2s, ebi2_lcd, _, _, _, _, _, _, _, _), + [100] = PINGROUP(100, tri_mi2s, ebi2_a, _, _, _, _, _, _, _, _), + [101] = PINGROUP(101, tri_mi2s, ebi2_lcd, _, _, _, _, _, _, _, _), + [102] = PINGROUP(102, _, _, _, _, _, _, _, _, _, _), + [103] = PINGROUP(103, _, _, _, _, _, _, _, _, _, _), + [104] = PINGROUP(104, nav_gpio, _, _, _, _, _, _, _, _, _), + [105] = PINGROUP(105, sd_card, _, _, _, _, _, _, _, _, _), + [106] = PINGROUP(106, eth1_mdc, _, _, _, _, _, _, _, _, _), + [107] = PINGROUP(107, eth1_mdio, _, _, _, _, _, _, _, _, _), + [108] = PINGROUP(108, _, _, _, _, _, _, _, _, _, _), + [109] = PINGROUP(109, sgmii_phy_intr1_n, _, _, _, _, _, _, _, _, _), + [110] = PINGROUP(110, qup_se5, qdss_gpio, _, _, _, _, _, _, _, _), + [111] = PINGROUP(111, qup_se5, qdss_gpio, _, _, _, _, _, _, _, _), + [112] = PINGROUP(112, qup_se6, emac1_ptp, emac1_ptp, qdss_gpio, _, _, _, _, _, _), + [113] = PINGROUP(113, qup_se6, emac1_ptp, emac1_ptp, qdss_gpio, _, _, _, _, _, _), + [114] = PINGROUP(114, qup_se6, emac1_ptp, emac1_ptp, qdss_gpio, _, _, _, _, _, _), + [115] = PINGROUP(115, qup_se6, emac1_ptp, emac1_ptp, qdss_gpio, _, _, _, _, _, _), + [116] = PINGROUP(116, qup_se7, qdss_gpio, _, _, _, _, _, _, _, _), + [117] = PINGROUP(117, qup_se7, qdss_gpio, _, _, _, _, _, _, _, _), + [118] = PINGROUP(118, qup_se7, qdss_gpio, _, _, _, _, _, _, _, _), + [119] = PINGROUP(119, qup_se7, emac0_ptp, qdss_gpio, _, _, _, _, _, _, _), + [120] = PINGROUP(120, _, _, _, _, _, _, _, _, _, _), + [121] = PINGROUP(121, pcie2_clkreq_n, _, _, _, _, _, _, _, _, _), + [122] = PINGROUP(122, emac1_mcg, _, _, _, _, _, _, _, _, _), + [123] = PINGROUP(123, emac0_ptp, emac0_ptp, emac0_ptp, emac0_ptp, _, _, _, _, _, _), + [124] = PINGROUP(124, pcie1_clkreq_n, qup_se8, _, _, _, _, _, _, _, _), + [125] = PINGROUP(125, qup_se8, _, _, _, _, _, _, _, _, _), + [126] = PINGROUP(126, audio_ref_clk, _, _, _, _, _, _, _, _, _), + [127] = PINGROUP(127, emac_pps_in, _, _, _, _, _, _, _, _, _), + [128] = PINGROUP(128, _, _, _, _, _, _, _, _, _, _), + [129] = PINGROUP(129, sdc2_tb_trig, _, _, _, _, _, _, _, _, _), + [130] = PINGROUP(130, sdc1_tb, _, _, _, _, _, _, _, _, _), + [131] = PINGROUP(131, _, _, _, _, _, _, _, _, _, _), + [132] = PINGROUP(132, _, _, _, _, _, _, _, _, _, _), + [133] = SDC_QDSD_PINGROUP(sdc1_rclk, 0x19a000, 16, 0), + [134] = SDC_QDSD_PINGROUP(sdc1_clk, 0x19a000, 14, 6), + [135] = SDC_QDSD_PINGROUP(sdc1_cmd, 0x19a000, 11, 3), + [136] = SDC_QDSD_PINGROUP(sdc1_data, 0x19a000, 9, 0), + [137] = SDC_QDSD_PINGROUP(sdc2_clk, 0x19b000, 14, 6), + [138] = SDC_QDSD_PINGROUP(sdc2_cmd, 0x19b000, 11, 3), + [139] = SDC_QDSD_PINGROUP(sdc2_data, 0x19b000, 9, 0), +}; + +static const struct msm_gpio_wakeirq_map sdx75_pdc_map[] = { + { 1, 57 }, { 2, 91 }, {5, 52 }, { 6, 109 }, { 9, 129 }, { 11, 62 }, + { 13, 84 }, { 15, 87 }, { 17, 88 }, { 18, 89 }, { 19, 90 }, { 20, 92 }, + { 21, 93 }, { 22, 94 }, { 23, 95 }, { 25, 96 }, { 27, 97 }, { 35, 58 }, + { 36, 53 }, { 38, 98 }, { 39, 99 }, { 40, 100 }, { 41, 101 }, { 42, 54 }, + { 43, 56 }, { 44, 71 }, { 46, 60 }, { 47, 61 }, { 49, 47 }, { 50, 126 }, + { 51, 55 }, { 52, 102 }, { 53, 141 }, { 54, 104 }, { 55, 105 }, { 56, 106 }, + { 57, 107 }, { 59, 108 }, { 60, 110 }, { 62, 111 }, { 63, 112 }, { 64, 113 }, + { 65, 114 }, { 67, 115 }, { 68, 116 }, { 69, 117 }, { 70, 118 }, { 71, 119 }, + { 72, 120 }, { 75, 121 }, { 76, 122 }, { 78, 123 }, { 79, 124 }, { 80, 125 }, + { 81, 50 }, { 85, 127 }, { 87, 128 }, { 91, 130 }, { 92, 131 }, { 93, 132 }, + { 94, 133 }, { 95, 134 }, { 97, 135 }, { 98, 136 }, { 101, 64 }, { 103, 51 }, + { 105, 65 }, { 106, 66 }, { 107, 67 }, { 108, 68 }, { 109, 69 }, { 111, 70 }, + { 113, 59 }, { 115, 72 }, { 116, 73 }, { 117, 74 }, { 118, 75 }, { 119, 76 }, + { 120, 77 }, { 121, 78 }, { 123, 79 }, { 124, 80 }, { 125, 63 }, { 127, 81 }, + { 128, 82 }, { 129, 83 }, { 130, 85 }, { 132, 86 }, +}; + +static const struct msm_pinctrl_soc_data sdx75_pinctrl = { + .pins = sdx75_pins, + .npins = ARRAY_SIZE(sdx75_pins), + .functions = sdx75_functions, + .nfunctions = ARRAY_SIZE(sdx75_functions), + .groups = sdx75_groups, + .ngroups = ARRAY_SIZE(sdx75_groups), + .ngpios = 133, + .wakeirq_map = sdx75_pdc_map, + .nwakeirq_map = ARRAY_SIZE(sdx75_pdc_map), +}; + +static const struct of_device_id sdx75_pinctrl_of_match[] = { + { .compatible = "qcom,sdx75-tlmm", .data = &sdx75_pinctrl }, + { } +}; +MODULE_DEVICE_TABLE(of, sdx75_pinctrl_of_match); + +static int sdx75_pinctrl_probe(struct platform_device *pdev) +{ + const struct msm_pinctrl_soc_data *pinctrl_data; + + pinctrl_data = of_device_get_match_data(&pdev->dev); + if (!pinctrl_data) + return -EINVAL; + + return msm_pinctrl_probe(pdev, pinctrl_data); +} + +static struct platform_driver sdx75_pinctrl_driver = { + .driver = { + .name = "sdx75-tlmm", + .of_match_table = sdx75_pinctrl_of_match, + }, + .probe = sdx75_pinctrl_probe, + .remove = msm_pinctrl_remove, +}; + +static int __init sdx75_pinctrl_init(void) +{ + return platform_driver_register(&sdx75_pinctrl_driver); +} +arch_initcall(sdx75_pinctrl_init); + +static void __exit sdx75_pinctrl_exit(void) +{ + platform_driver_unregister(&sdx75_pinctrl_driver); +} +module_exit(sdx75_pinctrl_exit); + +MODULE_DESCRIPTION("QTI sdx75 pinctrl driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/pinctrl/qcom/pinctrl-sm6115-lpass-lpi.c b/drivers/pinctrl/qcom/pinctrl-sm6115-lpass-lpi.c new file mode 100644 index 0000000000..2b09bf171a --- /dev/null +++ b/drivers/pinctrl/qcom/pinctrl-sm6115-lpass-lpi.c @@ -0,0 +1,175 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2016-2019, The Linux Foundation. All rights reserved. + * Copyright (c) 2020, 2023 Linaro Ltd. + */ + +#include <linux/gpio/driver.h> +#include <linux/module.h> +#include <linux/platform_device.h> + +#include "pinctrl-lpass-lpi.h" + +enum lpass_lpi_functions { + LPI_MUX_dmic01_clk, + LPI_MUX_dmic01_data, + LPI_MUX_dmic23_clk, + LPI_MUX_dmic23_data, + LPI_MUX_i2s1_clk, + LPI_MUX_i2s1_data, + LPI_MUX_i2s1_ws, + LPI_MUX_i2s2_clk, + LPI_MUX_i2s2_data, + LPI_MUX_i2s2_ws, + LPI_MUX_i2s3_clk, + LPI_MUX_i2s3_data, + LPI_MUX_i2s3_ws, + LPI_MUX_qua_mi2s_data, + LPI_MUX_qua_mi2s_sclk, + LPI_MUX_qua_mi2s_ws, + LPI_MUX_swr_rx_clk, + LPI_MUX_swr_rx_data, + LPI_MUX_swr_tx_clk, + LPI_MUX_swr_tx_data, + LPI_MUX_wsa_mclk, + LPI_MUX_gpio, + LPI_MUX__, +}; + +static int gpio0_pins[] = { 0 }; +static int gpio1_pins[] = { 1 }; +static int gpio2_pins[] = { 2 }; +static int gpio3_pins[] = { 3 }; +static int gpio4_pins[] = { 4 }; +static int gpio5_pins[] = { 5 }; +static int gpio6_pins[] = { 6 }; +static int gpio7_pins[] = { 7 }; +static int gpio8_pins[] = { 8 }; +static int gpio9_pins[] = { 9 }; +static int gpio10_pins[] = { 10 }; +static int gpio11_pins[] = { 11 }; +static int gpio12_pins[] = { 12 }; +static int gpio13_pins[] = { 13 }; +static int gpio14_pins[] = { 14 }; +static int gpio15_pins[] = { 15 }; +static int gpio16_pins[] = { 16 }; +static int gpio17_pins[] = { 17 }; +static int gpio18_pins[] = { 18 }; + +static const struct pinctrl_pin_desc sm6115_lpi_pins[] = { + PINCTRL_PIN(0, "gpio0"), + PINCTRL_PIN(1, "gpio1"), + PINCTRL_PIN(2, "gpio2"), + PINCTRL_PIN(3, "gpio3"), + PINCTRL_PIN(4, "gpio4"), + PINCTRL_PIN(5, "gpio5"), + PINCTRL_PIN(6, "gpio6"), + PINCTRL_PIN(7, "gpio7"), + PINCTRL_PIN(8, "gpio8"), + PINCTRL_PIN(9, "gpio9"), + PINCTRL_PIN(10, "gpio10"), + PINCTRL_PIN(11, "gpio11"), + PINCTRL_PIN(12, "gpio12"), + PINCTRL_PIN(13, "gpio13"), + PINCTRL_PIN(14, "gpio14"), + PINCTRL_PIN(15, "gpio15"), + PINCTRL_PIN(16, "gpio16"), + PINCTRL_PIN(17, "gpio17"), + PINCTRL_PIN(18, "gpio18"), +}; + +static const char * const dmic01_clk_groups[] = { "gpio6" }; +static const char * const dmic01_data_groups[] = { "gpio7" }; +static const char * const dmic23_clk_groups[] = { "gpio8" }; +static const char * const dmic23_data_groups[] = { "gpio9" }; +static const char * const i2s1_clk_groups[] = { "gpio6" }; +static const char * const i2s1_data_groups[] = { "gpio8", "gpio9" }; +static const char * const i2s1_ws_groups[] = { "gpio7" }; +static const char * const i2s2_clk_groups[] = { "gpio10" }; +static const char * const i2s2_data_groups[] = { "gpio12", "gpio13" }; +static const char * const i2s2_ws_groups[] = { "gpio11" }; +static const char * const i2s3_clk_groups[] = { "gpio14" }; +static const char * const i2s3_data_groups[] = { "gpio16", "gpio17" }; +static const char * const i2s3_ws_groups[] = { "gpio15" }; +static const char * const qua_mi2s_data_groups[] = { "gpio2", "gpio3", "gpio4", "gpio5" }; +static const char * const qua_mi2s_sclk_groups[] = { "gpio0" }; +static const char * const qua_mi2s_ws_groups[] = { "gpio1" }; +static const char * const swr_rx_clk_groups[] = { "gpio3" }; +static const char * const swr_rx_data_groups[] = { "gpio4", "gpio5" }; +static const char * const swr_tx_clk_groups[] = { "gpio0" }; +static const char * const swr_tx_data_groups[] = { "gpio1", "gpio2" }; +static const char * const wsa_mclk_groups[] = { "gpio18" }; + +static const struct lpi_pingroup sm6115_groups[] = { + LPI_PINGROUP(0, 0, swr_tx_clk, qua_mi2s_sclk, _, _), + LPI_PINGROUP(1, 2, swr_tx_data, qua_mi2s_ws, _, _), + LPI_PINGROUP(2, 4, swr_tx_data, qua_mi2s_data, _, _), + LPI_PINGROUP(3, 8, swr_rx_clk, qua_mi2s_data, _, _), + LPI_PINGROUP(4, 10, swr_rx_data, qua_mi2s_data, _, _), + LPI_PINGROUP(5, 12, swr_rx_data, _, qua_mi2s_data, _), + LPI_PINGROUP(6, LPI_NO_SLEW, dmic01_clk, i2s1_clk, _, _), + LPI_PINGROUP(7, LPI_NO_SLEW, dmic01_data, i2s1_ws, _, _), + LPI_PINGROUP(8, LPI_NO_SLEW, dmic23_clk, i2s1_data, _, _), + LPI_PINGROUP(9, LPI_NO_SLEW, dmic23_data, i2s1_data, _, _), + LPI_PINGROUP(10, LPI_NO_SLEW, i2s2_clk, _, _, _), + LPI_PINGROUP(11, LPI_NO_SLEW, i2s2_ws, _, _, _), + LPI_PINGROUP(12, LPI_NO_SLEW, _, i2s2_data, _, _), + LPI_PINGROUP(13, LPI_NO_SLEW, _, i2s2_data, _, _), + LPI_PINGROUP(14, LPI_NO_SLEW, i2s3_clk, _, _, _), + LPI_PINGROUP(15, LPI_NO_SLEW, i2s3_ws, _, _, _), + LPI_PINGROUP(16, LPI_NO_SLEW, i2s3_data, _, _, _), + LPI_PINGROUP(17, LPI_NO_SLEW, i2s3_data, _, _, _), + LPI_PINGROUP(18, 14, wsa_mclk, _, _, _), +}; + +static const struct lpi_function sm6115_functions[] = { + LPI_FUNCTION(dmic01_clk), + LPI_FUNCTION(dmic01_data), + LPI_FUNCTION(dmic23_clk), + LPI_FUNCTION(dmic23_data), + LPI_FUNCTION(i2s1_clk), + LPI_FUNCTION(i2s1_data), + LPI_FUNCTION(i2s1_ws), + LPI_FUNCTION(i2s2_clk), + LPI_FUNCTION(i2s2_data), + LPI_FUNCTION(i2s2_ws), + LPI_FUNCTION(i2s3_clk), + LPI_FUNCTION(i2s3_data), + LPI_FUNCTION(i2s3_ws), + LPI_FUNCTION(qua_mi2s_data), + LPI_FUNCTION(qua_mi2s_sclk), + LPI_FUNCTION(qua_mi2s_ws), + LPI_FUNCTION(swr_rx_clk), + LPI_FUNCTION(swr_rx_data), + LPI_FUNCTION(swr_tx_clk), + LPI_FUNCTION(swr_tx_data), + LPI_FUNCTION(wsa_mclk), +}; + +static const struct lpi_pinctrl_variant_data sm6115_lpi_data = { + .pins = sm6115_lpi_pins, + .npins = ARRAY_SIZE(sm6115_lpi_pins), + .groups = sm6115_groups, + .ngroups = ARRAY_SIZE(sm6115_groups), + .functions = sm6115_functions, + .nfunctions = ARRAY_SIZE(sm6115_functions), +}; + +static const struct of_device_id lpi_pinctrl_of_match[] = { + { .compatible = "qcom,sm6115-lpass-lpi-pinctrl", .data = &sm6115_lpi_data }, + { } +}; +MODULE_DEVICE_TABLE(of, lpi_pinctrl_of_match); + +static struct platform_driver lpi_pinctrl_driver = { + .driver = { + .name = "qcom-sm6115-lpass-lpi-pinctrl", + .of_match_table = lpi_pinctrl_of_match, + }, + .probe = lpi_pinctrl_probe, + .remove = lpi_pinctrl_remove, +}; + +module_platform_driver(lpi_pinctrl_driver); +MODULE_DESCRIPTION("QTI SM6115 LPI GPIO pin control driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/pinctrl/qcom/pinctrl-sm6115.c b/drivers/pinctrl/qcom/pinctrl-sm6115.c new file mode 100644 index 0000000000..2a06025f48 --- /dev/null +++ b/drivers/pinctrl/qcom/pinctrl-sm6115.c @@ -0,0 +1,915 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2019, The Linux Foundation. All rights reserved. + */ + +#include <linux/module.h> +#include <linux/of.h> +#include <linux/platform_device.h> + +#include "pinctrl-msm.h" + +static const char * const sm6115_tiles[] = { + "south", + "east", + "west" +}; + +enum { + SOUTH, + EAST, + WEST +}; + +#define PINGROUP(id, _tile, f1, f2, f3, f4, f5, f6, f7, f8, f9) \ + { \ + .grp = PINCTRL_PINGROUP("gpio" #id, \ + gpio##id##_pins, \ + ARRAY_SIZE(gpio##id##_pins)), \ + .funcs = (int[]){ \ + msm_mux_gpio, /* gpio mode */ \ + msm_mux_##f1, \ + msm_mux_##f2, \ + msm_mux_##f3, \ + msm_mux_##f4, \ + msm_mux_##f5, \ + msm_mux_##f6, \ + msm_mux_##f7, \ + msm_mux_##f8, \ + msm_mux_##f9 \ + }, \ + .nfuncs = 10, \ + .ctl_reg = 0x1000 * id, \ + .io_reg = 0x4 + 0x1000 * id, \ + .intr_cfg_reg = 0x8 + 0x1000 * id, \ + .intr_status_reg = 0xc + 0x1000 * id, \ + .intr_target_reg = 0x8 + 0x1000 * id, \ + .tile = _tile, \ + .mux_bit = 2, \ + .pull_bit = 0, \ + .drv_bit = 6, \ + .oe_bit = 9, \ + .in_bit = 0, \ + .out_bit = 1, \ + .intr_enable_bit = 0, \ + .intr_status_bit = 0, \ + .intr_target_bit = 5, \ + .intr_target_kpss_val = 3, \ + .intr_raw_status_bit = 4, \ + .intr_polarity_bit = 1, \ + .intr_detection_bit = 2, \ + .intr_detection_width = 2, \ + } + +#define SDC_QDSD_PINGROUP(pg_name, _tile, ctl, pull, drv) \ + { \ + .grp = PINCTRL_PINGROUP(#pg_name, \ + pg_name##_pins, \ + ARRAY_SIZE(pg_name##_pins)), \ + .ctl_reg = ctl, \ + .io_reg = 0, \ + .intr_cfg_reg = 0, \ + .intr_status_reg = 0, \ + .intr_target_reg = 0, \ + .tile = _tile, \ + .mux_bit = -1, \ + .pull_bit = pull, \ + .drv_bit = drv, \ + .oe_bit = -1, \ + .in_bit = -1, \ + .out_bit = -1, \ + .intr_enable_bit = -1, \ + .intr_status_bit = -1, \ + .intr_target_bit = -1, \ + .intr_raw_status_bit = -1, \ + .intr_polarity_bit = -1, \ + .intr_detection_bit = -1, \ + .intr_detection_width = -1, \ + } + +#define UFS_RESET(pg_name, offset) \ + { \ + .grp = PINCTRL_PINGROUP(#pg_name, \ + pg_name##_pins, \ + ARRAY_SIZE(pg_name##_pins)), \ + .ctl_reg = offset, \ + .io_reg = offset + 0x4, \ + .intr_cfg_reg = 0, \ + .intr_status_reg = 0, \ + .intr_target_reg = 0, \ + .tile = WEST, \ + .mux_bit = -1, \ + .pull_bit = 3, \ + .drv_bit = 0, \ + .oe_bit = -1, \ + .in_bit = -1, \ + .out_bit = 0, \ + .intr_enable_bit = -1, \ + .intr_status_bit = -1, \ + .intr_target_bit = -1, \ + .intr_raw_status_bit = -1, \ + .intr_polarity_bit = -1, \ + .intr_detection_bit = -1, \ + .intr_detection_width = -1, \ + } +static const struct pinctrl_pin_desc sm6115_pins[] = { + PINCTRL_PIN(0, "GPIO_0"), + PINCTRL_PIN(1, "GPIO_1"), + PINCTRL_PIN(2, "GPIO_2"), + PINCTRL_PIN(3, "GPIO_3"), + PINCTRL_PIN(4, "GPIO_4"), + PINCTRL_PIN(5, "GPIO_5"), + PINCTRL_PIN(6, "GPIO_6"), + PINCTRL_PIN(7, "GPIO_7"), + PINCTRL_PIN(8, "GPIO_8"), + PINCTRL_PIN(9, "GPIO_9"), + PINCTRL_PIN(10, "GPIO_10"), + PINCTRL_PIN(11, "GPIO_11"), + PINCTRL_PIN(12, "GPIO_12"), + PINCTRL_PIN(13, "GPIO_13"), + PINCTRL_PIN(14, "GPIO_14"), + PINCTRL_PIN(15, "GPIO_15"), + PINCTRL_PIN(16, "GPIO_16"), + PINCTRL_PIN(17, "GPIO_17"), + PINCTRL_PIN(18, "GPIO_18"), + PINCTRL_PIN(19, "GPIO_19"), + PINCTRL_PIN(20, "GPIO_20"), + PINCTRL_PIN(21, "GPIO_21"), + PINCTRL_PIN(22, "GPIO_22"), + PINCTRL_PIN(23, "GPIO_23"), + PINCTRL_PIN(24, "GPIO_24"), + PINCTRL_PIN(25, "GPIO_25"), + PINCTRL_PIN(26, "GPIO_26"), + PINCTRL_PIN(27, "GPIO_27"), + PINCTRL_PIN(28, "GPIO_28"), + PINCTRL_PIN(29, "GPIO_29"), + PINCTRL_PIN(30, "GPIO_30"), + PINCTRL_PIN(31, "GPIO_31"), + PINCTRL_PIN(32, "GPIO_32"), + PINCTRL_PIN(33, "GPIO_33"), + PINCTRL_PIN(34, "GPIO_34"), + PINCTRL_PIN(35, "GPIO_35"), + PINCTRL_PIN(36, "GPIO_36"), + PINCTRL_PIN(37, "GPIO_37"), + PINCTRL_PIN(38, "GPIO_38"), + PINCTRL_PIN(39, "GPIO_39"), + PINCTRL_PIN(40, "GPIO_40"), + PINCTRL_PIN(41, "GPIO_41"), + PINCTRL_PIN(42, "GPIO_42"), + PINCTRL_PIN(43, "GPIO_43"), + PINCTRL_PIN(44, "GPIO_44"), + PINCTRL_PIN(45, "GPIO_45"), + PINCTRL_PIN(46, "GPIO_46"), + PINCTRL_PIN(47, "GPIO_47"), + PINCTRL_PIN(48, "GPIO_48"), + PINCTRL_PIN(49, "GPIO_49"), + PINCTRL_PIN(50, "GPIO_50"), + PINCTRL_PIN(51, "GPIO_51"), + PINCTRL_PIN(52, "GPIO_52"), + PINCTRL_PIN(53, "GPIO_53"), + PINCTRL_PIN(54, "GPIO_54"), + PINCTRL_PIN(55, "GPIO_55"), + PINCTRL_PIN(56, "GPIO_56"), + PINCTRL_PIN(57, "GPIO_57"), + PINCTRL_PIN(58, "GPIO_58"), + PINCTRL_PIN(59, "GPIO_59"), + PINCTRL_PIN(60, "GPIO_60"), + PINCTRL_PIN(61, "GPIO_61"), + PINCTRL_PIN(62, "GPIO_62"), + PINCTRL_PIN(63, "GPIO_63"), + PINCTRL_PIN(64, "GPIO_64"), + PINCTRL_PIN(65, "GPIO_65"), + PINCTRL_PIN(66, "GPIO_66"), + PINCTRL_PIN(67, "GPIO_67"), + PINCTRL_PIN(68, "GPIO_68"), + PINCTRL_PIN(69, "GPIO_69"), + PINCTRL_PIN(70, "GPIO_70"), + PINCTRL_PIN(71, "GPIO_71"), + PINCTRL_PIN(72, "GPIO_72"), + PINCTRL_PIN(73, "GPIO_73"), + PINCTRL_PIN(74, "GPIO_74"), + PINCTRL_PIN(75, "GPIO_75"), + PINCTRL_PIN(76, "GPIO_76"), + PINCTRL_PIN(77, "GPIO_77"), + PINCTRL_PIN(78, "GPIO_78"), + PINCTRL_PIN(79, "GPIO_79"), + PINCTRL_PIN(80, "GPIO_80"), + PINCTRL_PIN(81, "GPIO_81"), + PINCTRL_PIN(82, "GPIO_82"), + PINCTRL_PIN(83, "GPIO_83"), + PINCTRL_PIN(84, "GPIO_84"), + PINCTRL_PIN(85, "GPIO_85"), + PINCTRL_PIN(86, "GPIO_86"), + PINCTRL_PIN(87, "GPIO_87"), + PINCTRL_PIN(88, "GPIO_88"), + PINCTRL_PIN(89, "GPIO_89"), + PINCTRL_PIN(90, "GPIO_90"), + PINCTRL_PIN(91, "GPIO_91"), + PINCTRL_PIN(92, "GPIO_92"), + PINCTRL_PIN(93, "GPIO_93"), + PINCTRL_PIN(94, "GPIO_94"), + PINCTRL_PIN(95, "GPIO_95"), + PINCTRL_PIN(96, "GPIO_96"), + PINCTRL_PIN(97, "GPIO_97"), + PINCTRL_PIN(98, "GPIO_98"), + PINCTRL_PIN(99, "GPIO_99"), + PINCTRL_PIN(100, "GPIO_100"), + PINCTRL_PIN(101, "GPIO_101"), + PINCTRL_PIN(102, "GPIO_102"), + PINCTRL_PIN(103, "GPIO_103"), + PINCTRL_PIN(104, "GPIO_104"), + PINCTRL_PIN(105, "GPIO_105"), + PINCTRL_PIN(106, "GPIO_106"), + PINCTRL_PIN(107, "GPIO_107"), + PINCTRL_PIN(108, "GPIO_108"), + PINCTRL_PIN(109, "GPIO_109"), + PINCTRL_PIN(110, "GPIO_110"), + PINCTRL_PIN(111, "GPIO_111"), + PINCTRL_PIN(112, "GPIO_112"), + PINCTRL_PIN(113, "UFS_RESET"), + PINCTRL_PIN(114, "SDC1_RCLK"), + PINCTRL_PIN(115, "SDC1_CLK"), + PINCTRL_PIN(116, "SDC1_CMD"), + PINCTRL_PIN(117, "SDC1_DATA"), + PINCTRL_PIN(118, "SDC2_CLK"), + PINCTRL_PIN(119, "SDC2_CMD"), + PINCTRL_PIN(120, "SDC2_DATA"), +}; + +#define DECLARE_MSM_GPIO_PINS(pin) \ + static const unsigned int gpio##pin##_pins[] = { pin } +DECLARE_MSM_GPIO_PINS(0); +DECLARE_MSM_GPIO_PINS(1); +DECLARE_MSM_GPIO_PINS(2); +DECLARE_MSM_GPIO_PINS(3); +DECLARE_MSM_GPIO_PINS(4); +DECLARE_MSM_GPIO_PINS(5); +DECLARE_MSM_GPIO_PINS(6); +DECLARE_MSM_GPIO_PINS(7); +DECLARE_MSM_GPIO_PINS(8); +DECLARE_MSM_GPIO_PINS(9); +DECLARE_MSM_GPIO_PINS(10); +DECLARE_MSM_GPIO_PINS(11); +DECLARE_MSM_GPIO_PINS(12); +DECLARE_MSM_GPIO_PINS(13); +DECLARE_MSM_GPIO_PINS(14); +DECLARE_MSM_GPIO_PINS(15); +DECLARE_MSM_GPIO_PINS(16); +DECLARE_MSM_GPIO_PINS(17); +DECLARE_MSM_GPIO_PINS(18); +DECLARE_MSM_GPIO_PINS(19); +DECLARE_MSM_GPIO_PINS(20); +DECLARE_MSM_GPIO_PINS(21); +DECLARE_MSM_GPIO_PINS(22); +DECLARE_MSM_GPIO_PINS(23); +DECLARE_MSM_GPIO_PINS(24); +DECLARE_MSM_GPIO_PINS(25); +DECLARE_MSM_GPIO_PINS(26); +DECLARE_MSM_GPIO_PINS(27); +DECLARE_MSM_GPIO_PINS(28); +DECLARE_MSM_GPIO_PINS(29); +DECLARE_MSM_GPIO_PINS(30); +DECLARE_MSM_GPIO_PINS(31); +DECLARE_MSM_GPIO_PINS(32); +DECLARE_MSM_GPIO_PINS(33); +DECLARE_MSM_GPIO_PINS(34); +DECLARE_MSM_GPIO_PINS(35); +DECLARE_MSM_GPIO_PINS(36); +DECLARE_MSM_GPIO_PINS(37); +DECLARE_MSM_GPIO_PINS(38); +DECLARE_MSM_GPIO_PINS(39); +DECLARE_MSM_GPIO_PINS(40); +DECLARE_MSM_GPIO_PINS(41); +DECLARE_MSM_GPIO_PINS(42); +DECLARE_MSM_GPIO_PINS(43); +DECLARE_MSM_GPIO_PINS(44); +DECLARE_MSM_GPIO_PINS(45); +DECLARE_MSM_GPIO_PINS(46); +DECLARE_MSM_GPIO_PINS(47); +DECLARE_MSM_GPIO_PINS(48); +DECLARE_MSM_GPIO_PINS(49); +DECLARE_MSM_GPIO_PINS(50); +DECLARE_MSM_GPIO_PINS(51); +DECLARE_MSM_GPIO_PINS(52); +DECLARE_MSM_GPIO_PINS(53); +DECLARE_MSM_GPIO_PINS(54); +DECLARE_MSM_GPIO_PINS(55); +DECLARE_MSM_GPIO_PINS(56); +DECLARE_MSM_GPIO_PINS(57); +DECLARE_MSM_GPIO_PINS(58); +DECLARE_MSM_GPIO_PINS(59); +DECLARE_MSM_GPIO_PINS(60); +DECLARE_MSM_GPIO_PINS(61); +DECLARE_MSM_GPIO_PINS(62); +DECLARE_MSM_GPIO_PINS(63); +DECLARE_MSM_GPIO_PINS(64); +DECLARE_MSM_GPIO_PINS(65); +DECLARE_MSM_GPIO_PINS(66); +DECLARE_MSM_GPIO_PINS(67); +DECLARE_MSM_GPIO_PINS(68); +DECLARE_MSM_GPIO_PINS(69); +DECLARE_MSM_GPIO_PINS(70); +DECLARE_MSM_GPIO_PINS(71); +DECLARE_MSM_GPIO_PINS(72); +DECLARE_MSM_GPIO_PINS(73); +DECLARE_MSM_GPIO_PINS(74); +DECLARE_MSM_GPIO_PINS(75); +DECLARE_MSM_GPIO_PINS(76); +DECLARE_MSM_GPIO_PINS(77); +DECLARE_MSM_GPIO_PINS(78); +DECLARE_MSM_GPIO_PINS(79); +DECLARE_MSM_GPIO_PINS(80); +DECLARE_MSM_GPIO_PINS(81); +DECLARE_MSM_GPIO_PINS(82); +DECLARE_MSM_GPIO_PINS(83); +DECLARE_MSM_GPIO_PINS(84); +DECLARE_MSM_GPIO_PINS(85); +DECLARE_MSM_GPIO_PINS(86); +DECLARE_MSM_GPIO_PINS(87); +DECLARE_MSM_GPIO_PINS(88); +DECLARE_MSM_GPIO_PINS(89); +DECLARE_MSM_GPIO_PINS(90); +DECLARE_MSM_GPIO_PINS(91); +DECLARE_MSM_GPIO_PINS(92); +DECLARE_MSM_GPIO_PINS(93); +DECLARE_MSM_GPIO_PINS(94); +DECLARE_MSM_GPIO_PINS(95); +DECLARE_MSM_GPIO_PINS(96); +DECLARE_MSM_GPIO_PINS(97); +DECLARE_MSM_GPIO_PINS(98); +DECLARE_MSM_GPIO_PINS(99); +DECLARE_MSM_GPIO_PINS(100); +DECLARE_MSM_GPIO_PINS(101); +DECLARE_MSM_GPIO_PINS(102); +DECLARE_MSM_GPIO_PINS(103); +DECLARE_MSM_GPIO_PINS(104); +DECLARE_MSM_GPIO_PINS(105); +DECLARE_MSM_GPIO_PINS(106); +DECLARE_MSM_GPIO_PINS(107); +DECLARE_MSM_GPIO_PINS(108); +DECLARE_MSM_GPIO_PINS(109); +DECLARE_MSM_GPIO_PINS(110); +DECLARE_MSM_GPIO_PINS(111); +DECLARE_MSM_GPIO_PINS(112); + +static const unsigned int ufs_reset_pins[] = { 113 }; +static const unsigned int sdc1_rclk_pins[] = { 114 }; +static const unsigned int sdc1_clk_pins[] = { 115 }; +static const unsigned int sdc1_cmd_pins[] = { 116 }; +static const unsigned int sdc1_data_pins[] = { 117 }; +static const unsigned int sdc2_clk_pins[] = { 118 }; +static const unsigned int sdc2_cmd_pins[] = { 119 }; +static const unsigned int sdc2_data_pins[] = { 120 }; + +enum sm6115_functions { + msm_mux_adsp_ext, + msm_mux_agera_pll, + msm_mux_atest, + msm_mux_cam_mclk, + msm_mux_cci_async, + msm_mux_cci_i2c, + msm_mux_cci_timer, + msm_mux_cri_trng, + msm_mux_dac_calib, + msm_mux_dbg_out, + msm_mux_ddr_bist, + msm_mux_ddr_pxi0, + msm_mux_ddr_pxi1, + msm_mux_ddr_pxi2, + msm_mux_ddr_pxi3, + msm_mux_gcc_gp1, + msm_mux_gcc_gp2, + msm_mux_gcc_gp3, + msm_mux_gpio, + msm_mux_gp_pdm0, + msm_mux_gp_pdm1, + msm_mux_gp_pdm2, + msm_mux_gsm0_tx, + msm_mux_gsm1_tx, + msm_mux_jitter_bist, + msm_mux_mdp_vsync, + msm_mux_mdp_vsync_out_0, + msm_mux_mdp_vsync_out_1, + msm_mux_mpm_pwr, + msm_mux_mss_lte, + msm_mux_m_voc, + msm_mux_nav_gpio, + msm_mux_pa_indicator, + msm_mux_pbs, + msm_mux_pbs_out, + msm_mux_phase_flag, + msm_mux_pll_bist, + msm_mux_pll_bypassnl, + msm_mux_pll_reset, + msm_mux_prng_rosc, + msm_mux_qdss_cti, + msm_mux_qdss_gpio, + msm_mux_qup0, + msm_mux_qup1, + msm_mux_qup2, + msm_mux_qup3, + msm_mux_qup4, + msm_mux_qup5, + msm_mux_sdc1_tb, + msm_mux_sdc2_tb, + msm_mux_sd_write, + msm_mux_ssbi_wtr1, + msm_mux_tgu, + msm_mux_tsense_pwm, + msm_mux_uim1_clk, + msm_mux_uim1_data, + msm_mux_uim1_present, + msm_mux_uim1_reset, + msm_mux_uim2_clk, + msm_mux_uim2_data, + msm_mux_uim2_present, + msm_mux_uim2_reset, + msm_mux_usb_phy, + msm_mux_vfr_1, + msm_mux_vsense_trigger, + msm_mux_wlan1_adc0, + msm_mux_wlan1_adc1, + msm_mux__, +}; + +static const char * const qup0_groups[] = { + "gpio0", "gpio1", "gpio2", "gpio3", "gpio82", "gpio86", +}; +static const char * const gpio_groups[] = { + "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7", + "gpio8", "gpio9", "gpio10", "gpio11", "gpio12", "gpio13", "gpio14", + "gpio15", "gpio16", "gpio17", "gpio18", "gpio19", "gpio20", "gpio21", + "gpio22", "gpio23", "gpio24", "gpio25", "gpio26", "gpio27", "gpio28", + "gpio29", "gpio30", "gpio31", "gpio32", "gpio33", "gpio34", "gpio35", + "gpio36", "gpio37", "gpio38", "gpio39", "gpio40", "gpio41", "gpio42", + "gpio43", "gpio44", "gpio45", "gpio46", "gpio47", "gpio48", "gpio49", + "gpio50", "gpio51", "gpio52", "gpio53", "gpio54", "gpio55", "gpio56", + "gpio57", "gpio58", "gpio59", "gpio60", "gpio61", "gpio62", "gpio63", + "gpio64", "gpio65", "gpio66", "gpio67", "gpio68", "gpio69", "gpio70", + "gpio71", "gpio72", "gpio73", "gpio74", "gpio75", "gpio76", "gpio77", + "gpio78", "gpio79", "gpio80", "gpio81", "gpio82", "gpio83", "gpio84", + "gpio85", "gpio86", "gpio87", "gpio88", "gpio89", "gpio90", "gpio91", + "gpio92", "gpio93", "gpio94", "gpio95", "gpio96", "gpio97", "gpio98", + "gpio99", "gpio100", "gpio101", "gpio102", "gpio103", "gpio104", + "gpio105", "gpio106", "gpio107", "gpio108", "gpio109", "gpio110", + "gpio111", "gpio112", +}; +static const char * const ddr_bist_groups[] = { + "gpio0", "gpio1", "gpio2", "gpio3", +}; +static const char * const phase_flag_groups[] = { + "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", + "gpio14", "gpio15", "gpio16", "gpio17", "gpio22", "gpio23", "gpio24", + "gpio25", "gpio26", "gpio29", "gpio30", "gpio31", "gpio32", "gpio33", + "gpio35", "gpio36", "gpio43", "gpio44", "gpio45", "gpio63", "gpio64", + "gpio102", "gpio103", "gpio104", "gpio105", +}; +static const char * const qdss_gpio_groups[] = { + "gpio0", "gpio1", "gpio2", "gpio3", "gpio8", "gpio9", "gpio10", + "gpio11", "gpio14", "gpio15", "gpio16", "gpio17", "gpio18", "gpio19", + "gpio20", "gpio21", "gpio22", "gpio23", "gpio24", "gpio25", "gpio26", + "gpio47", "gpio48", "gpio69", "gpio70", "gpio87", "gpio90", "gpio91", + "gpio94", "gpio95", "gpio104", "gpio105", "gpio106", "gpio107", + "gpio109", "gpio110", +}; +static const char * const atest_groups[] = { + "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", + "gpio22", "gpio23", "gpio24", "gpio25", "gpio26", "gpio29", "gpio30", + "gpio31", "gpio32", "gpio33", "gpio86", "gpio87", "gpio88", "gpio89", + "gpio100", "gpio101", +}; +static const char * const mpm_pwr_groups[] = { + "gpio1", +}; +static const char * const m_voc_groups[] = { + "gpio0", +}; +static const char * const dac_calib_groups[] = { + "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio14", "gpio15", + "gpio16", "gpio17", "gpio22", "gpio23", "gpio24", "gpio25", "gpio26", + "gpio29", "gpio30", "gpio31", "gpio32", "gpio33", "gpio80", "gpio81", + "gpio82", "gpio102", "gpio103", "gpio104", "gpio105" +}; +static const char * const qup1_groups[] = { + "gpio4", "gpio5", "gpio69", "gpio70", +}; +static const char * const cri_trng_groups[] = { + "gpio4", "gpio5", "gpio18", +}; +static const char * const qup2_groups[] = { + "gpio6", "gpio7", "gpio71", "gpio80", +}; +static const char * const qup3_groups[] = { + "gpio8", "gpio9", "gpio10", "gpio11", +}; +static const char * const pbs_out_groups[] = { + "gpio8", "gpio9", "gpio52", +}; +static const char * const pll_bist_groups[] = { + "gpio8", "gpio9", +}; +static const char * const tsense_pwm_groups[] = { + "gpio8", +}; +static const char * const agera_pll_groups[] = { + "gpio10", "gpio11", +}; +static const char * const pbs_groups[] = { + "gpio10", "gpio11", "gpio18", "gpio19", "gpio20", "gpio21", "gpio22", + "gpio23", "gpio24", "gpio25", "gpio26", "gpio47", "gpio48", "gpio87", + "gpio90", "gpio91", +}; +static const char * const qup4_groups[] = { + "gpio12", "gpio13", "gpio96", "gpio97", +}; +static const char * const tgu_groups[] = { + "gpio12", "gpio13", "gpio14", "gpio15", +}; +static const char * const qup5_groups[] = { + "gpio14", "gpio15", "gpio16", "gpio17", +}; +static const char * const sdc2_tb_groups[] = { + "gpio18", +}; +static const char * const sdc1_tb_groups[] = { + "gpio19", +}; +static const char * const cam_mclk_groups[] = { + "gpio20", "gpio21", "gpio27", "gpio28", +}; +static const char * const adsp_ext_groups[] = { + "gpio21", +}; +static const char * const cci_i2c_groups[] = { + "gpio22", "gpio23", "gpio29", "gpio30", +}; +static const char * const prng_rosc_groups[] = { + "gpio22", "gpio23", +}; +static const char * const cci_timer_groups[] = { + "gpio24", "gpio25", "gpio28", "gpio32", +}; +static const char * const gcc_gp1_groups[] = { + "gpio24", "gpio86", +}; +static const char * const cci_async_groups[] = { + "gpio25", +}; +static const char * const vsense_trigger_groups[] = { + "gpio26", +}; +static const char * const qdss_cti_groups[] = { + "gpio27", "gpio28", "gpio72", "gpio73", "gpio96", "gpio97", +}; +static const char * const gp_pdm0_groups[] = { + "gpio31", "gpio95", +}; +static const char * const gp_pdm1_groups[] = { + "gpio32", "gpio96", +}; +static const char * const gp_pdm2_groups[] = { + "gpio33", "gpio97", +}; +static const char * const nav_gpio_groups[] = { + "gpio42", "gpio47", "gpio52", "gpio95", "gpio96", "gpio97", "gpio106", + "gpio107", "gpio108", +}; +static const char * const vfr_1_groups[] = { + "gpio48", +}; +static const char * const pa_indicator_groups[] = { + "gpio49", +}; +static const char * const gsm1_tx_groups[] = { + "gpio53", +}; +static const char * const ssbi_wtr1_groups[] = { + "gpio59", "gpio60", +}; +static const char * const pll_bypassnl_groups[] = { + "gpio62", +}; +static const char * const pll_reset_groups[] = { + "gpio63", +}; +static const char * const ddr_pxi0_groups[] = { + "gpio63", "gpio64", +}; +static const char * const gsm0_tx_groups[] = { + "gpio64", +}; +static const char * const gcc_gp2_groups[] = { + "gpio69", "gpio107", +}; +static const char * const ddr_pxi1_groups[] = { + "gpio69", "gpio70", +}; +static const char * const gcc_gp3_groups[] = { + "gpio70", "gpio106", +}; +static const char * const dbg_out_groups[] = { + "gpio71", +}; +static const char * const uim2_data_groups[] = { + "gpio72", +}; +static const char * const uim2_clk_groups[] = { + "gpio73", +}; +static const char * const uim2_reset_groups[] = { + "gpio74", +}; +static const char * const uim2_present_groups[] = { + "gpio75", +}; +static const char * const uim1_data_groups[] = { + "gpio76", +}; +static const char * const uim1_clk_groups[] = { + "gpio77", +}; +static const char * const uim1_reset_groups[] = { + "gpio78", +}; +static const char * const uim1_present_groups[] = { + "gpio79", +}; +static const char * const mdp_vsync_groups[] = { + "gpio81", "gpio96", "gpio97", +}; +static const char * const mdp_vsync_out_0_groups[] = { + "gpio81", +}; +static const char * const mdp_vsync_out_1_groups[] = { + "gpio81", +}; +static const char * const usb_phy_groups[] = { + "gpio89", +}; +static const char * const mss_lte_groups[] = { + "gpio90", "gpio91", +}; +static const char * const wlan1_adc0_groups[] = { + "gpio94", +}; +static const char * const wlan1_adc1_groups[] = { + "gpio95", +}; +static const char * const sd_write_groups[] = { + "gpio96", +}; +static const char * const jitter_bist_groups[] = { + "gpio96", "gpio97", +}; +static const char * const ddr_pxi2_groups[] = { + "gpio102", "gpio103", +}; +static const char * const ddr_pxi3_groups[] = { + "gpio104", "gpio105", +}; + +static const struct pinfunction sm6115_functions[] = { + MSM_PIN_FUNCTION(adsp_ext), + MSM_PIN_FUNCTION(agera_pll), + MSM_PIN_FUNCTION(atest), + MSM_PIN_FUNCTION(cam_mclk), + MSM_PIN_FUNCTION(cci_async), + MSM_PIN_FUNCTION(cci_i2c), + MSM_PIN_FUNCTION(cci_timer), + MSM_PIN_FUNCTION(cri_trng), + MSM_PIN_FUNCTION(dac_calib), + MSM_PIN_FUNCTION(dbg_out), + MSM_PIN_FUNCTION(ddr_bist), + MSM_PIN_FUNCTION(ddr_pxi0), + MSM_PIN_FUNCTION(ddr_pxi1), + MSM_PIN_FUNCTION(ddr_pxi2), + MSM_PIN_FUNCTION(ddr_pxi3), + MSM_PIN_FUNCTION(gcc_gp1), + MSM_PIN_FUNCTION(gcc_gp2), + MSM_PIN_FUNCTION(gcc_gp3), + MSM_PIN_FUNCTION(gpio), + MSM_PIN_FUNCTION(gp_pdm0), + MSM_PIN_FUNCTION(gp_pdm1), + MSM_PIN_FUNCTION(gp_pdm2), + MSM_PIN_FUNCTION(gsm0_tx), + MSM_PIN_FUNCTION(gsm1_tx), + MSM_PIN_FUNCTION(jitter_bist), + MSM_PIN_FUNCTION(mdp_vsync), + MSM_PIN_FUNCTION(mdp_vsync_out_0), + MSM_PIN_FUNCTION(mdp_vsync_out_1), + MSM_PIN_FUNCTION(mpm_pwr), + MSM_PIN_FUNCTION(mss_lte), + MSM_PIN_FUNCTION(m_voc), + MSM_PIN_FUNCTION(nav_gpio), + MSM_PIN_FUNCTION(pa_indicator), + MSM_PIN_FUNCTION(pbs), + MSM_PIN_FUNCTION(pbs_out), + MSM_PIN_FUNCTION(phase_flag), + MSM_PIN_FUNCTION(pll_bist), + MSM_PIN_FUNCTION(pll_bypassnl), + MSM_PIN_FUNCTION(pll_reset), + MSM_PIN_FUNCTION(prng_rosc), + MSM_PIN_FUNCTION(qdss_cti), + MSM_PIN_FUNCTION(qdss_gpio), + MSM_PIN_FUNCTION(qup0), + MSM_PIN_FUNCTION(qup1), + MSM_PIN_FUNCTION(qup2), + MSM_PIN_FUNCTION(qup3), + MSM_PIN_FUNCTION(qup4), + MSM_PIN_FUNCTION(qup5), + MSM_PIN_FUNCTION(sdc1_tb), + MSM_PIN_FUNCTION(sdc2_tb), + MSM_PIN_FUNCTION(sd_write), + MSM_PIN_FUNCTION(ssbi_wtr1), + MSM_PIN_FUNCTION(tgu), + MSM_PIN_FUNCTION(tsense_pwm), + MSM_PIN_FUNCTION(uim1_clk), + MSM_PIN_FUNCTION(uim1_data), + MSM_PIN_FUNCTION(uim1_present), + MSM_PIN_FUNCTION(uim1_reset), + MSM_PIN_FUNCTION(uim2_clk), + MSM_PIN_FUNCTION(uim2_data), + MSM_PIN_FUNCTION(uim2_present), + MSM_PIN_FUNCTION(uim2_reset), + MSM_PIN_FUNCTION(usb_phy), + MSM_PIN_FUNCTION(vfr_1), + MSM_PIN_FUNCTION(vsense_trigger), + MSM_PIN_FUNCTION(wlan1_adc0), + MSM_PIN_FUNCTION(wlan1_adc1), +}; + +/* Every pin is maintained as a single group, and missing or non-existing pin + * would be maintained as dummy group to synchronize pin group index with + * pin descriptor registered with pinctrl core. + * Clients would not be able to request these dummy pin groups. + */ +static const struct msm_pingroup sm6115_groups[] = { + [0] = PINGROUP(0, WEST, qup0, m_voc, ddr_bist, _, phase_flag, qdss_gpio, atest, _, _), + [1] = PINGROUP(1, WEST, qup0, mpm_pwr, ddr_bist, _, phase_flag, qdss_gpio, atest, _, _), + [2] = PINGROUP(2, WEST, qup0, ddr_bist, _, phase_flag, qdss_gpio, dac_calib, atest, _, _), + [3] = PINGROUP(3, WEST, qup0, ddr_bist, _, phase_flag, qdss_gpio, dac_calib, atest, _, _), + [4] = PINGROUP(4, WEST, qup1, cri_trng, _, phase_flag, dac_calib, atest, _, _, _), + [5] = PINGROUP(5, WEST, qup1, cri_trng, _, phase_flag, dac_calib, atest, _, _, _), + [6] = PINGROUP(6, WEST, qup2, _, phase_flag, dac_calib, atest, _, _, _, _), + [7] = PINGROUP(7, WEST, qup2, _, _, _, _, _, _, _, _), + [8] = PINGROUP(8, EAST, qup3, pbs_out, pll_bist, _, qdss_gpio, _, tsense_pwm, _, _), + [9] = PINGROUP(9, EAST, qup3, pbs_out, pll_bist, _, qdss_gpio, _, _, _, _), + [10] = PINGROUP(10, EAST, qup3, agera_pll, _, pbs, qdss_gpio, _, _, _, _), + [11] = PINGROUP(11, EAST, qup3, agera_pll, _, pbs, qdss_gpio, _, _, _, _), + [12] = PINGROUP(12, WEST, qup4, tgu, _, _, _, _, _, _, _), + [13] = PINGROUP(13, WEST, qup4, tgu, _, _, _, _, _, _, _), + [14] = PINGROUP(14, WEST, qup5, tgu, _, phase_flag, qdss_gpio, dac_calib, _, _, _), + [15] = PINGROUP(15, WEST, qup5, tgu, _, phase_flag, qdss_gpio, dac_calib, _, _, _), + [16] = PINGROUP(16, WEST, qup5, _, phase_flag, qdss_gpio, dac_calib, _, _, _, _), + [17] = PINGROUP(17, WEST, qup5, _, phase_flag, qdss_gpio, dac_calib, _, _, _, _), + [18] = PINGROUP(18, EAST, sdc2_tb, cri_trng, pbs, qdss_gpio, _, _, _, _, _), + [19] = PINGROUP(19, EAST, sdc1_tb, pbs, qdss_gpio, _, _, _, _, _, _), + [20] = PINGROUP(20, EAST, cam_mclk, pbs, qdss_gpio, _, _, _, _, _, _), + [21] = PINGROUP(21, EAST, cam_mclk, adsp_ext, pbs, qdss_gpio, _, _, _, _, _), + [22] = PINGROUP(22, EAST, cci_i2c, prng_rosc, _, pbs, phase_flag, qdss_gpio, dac_calib, atest, _), + [23] = PINGROUP(23, EAST, cci_i2c, prng_rosc, _, pbs, phase_flag, qdss_gpio, dac_calib, atest, _), + [24] = PINGROUP(24, EAST, cci_timer, gcc_gp1, _, pbs, phase_flag, qdss_gpio, dac_calib, atest, _), + [25] = PINGROUP(25, EAST, cci_async, cci_timer, _, pbs, phase_flag, qdss_gpio, dac_calib, atest, _), + [26] = PINGROUP(26, EAST, _, pbs, phase_flag, qdss_gpio, dac_calib, atest, vsense_trigger, _, _), + [27] = PINGROUP(27, EAST, cam_mclk, qdss_cti, _, _, _, _, _, _, _), + [28] = PINGROUP(28, EAST, cam_mclk, cci_timer, qdss_cti, _, _, _, _, _, _), + [29] = PINGROUP(29, EAST, cci_i2c, _, phase_flag, dac_calib, atest, _, _, _, _), + [30] = PINGROUP(30, EAST, cci_i2c, _, phase_flag, dac_calib, atest, _, _, _, _), + [31] = PINGROUP(31, EAST, gp_pdm0, _, phase_flag, dac_calib, atest, _, _, _, _), + [32] = PINGROUP(32, EAST, cci_timer, gp_pdm1, _, phase_flag, dac_calib, atest, _, _, _), + [33] = PINGROUP(33, EAST, gp_pdm2, _, phase_flag, dac_calib, atest, _, _, _, _), + [34] = PINGROUP(34, EAST, _, _, _, _, _, _, _, _, _), + [35] = PINGROUP(35, EAST, _, phase_flag, _, _, _, _, _, _, _), + [36] = PINGROUP(36, EAST, _, phase_flag, _, _, _, _, _, _, _), + [37] = PINGROUP(37, EAST, _, _, _, _, _, _, _, _, _), + [38] = PINGROUP(38, EAST, _, _, _, _, _, _, _, _, _), + [39] = PINGROUP(39, EAST, _, _, _, _, _, _, _, _, _), + [40] = PINGROUP(40, EAST, _, _, _, _, _, _, _, _, _), + [41] = PINGROUP(41, EAST, _, _, _, _, _, _, _, _, _), + [42] = PINGROUP(42, EAST, _, nav_gpio, _, _, _, _, _, _, _), + [43] = PINGROUP(43, EAST, _, _, phase_flag, _, _, _, _, _, _), + [44] = PINGROUP(44, EAST, _, _, phase_flag, _, _, _, _, _, _), + [45] = PINGROUP(45, EAST, _, _, phase_flag, _, _, _, _, _, _), + [46] = PINGROUP(46, EAST, _, _, _, _, _, _, _, _, _), + [47] = PINGROUP(47, EAST, _, nav_gpio, pbs, qdss_gpio, _, _, _, _, _), + [48] = PINGROUP(48, EAST, _, vfr_1, _, pbs, qdss_gpio, _, _, _, _), + [49] = PINGROUP(49, EAST, _, pa_indicator, _, _, _, _, _, _, _), + [50] = PINGROUP(50, EAST, _, _, _, _, _, _, _, _, _), + [51] = PINGROUP(51, EAST, _, _, _, _, _, _, _, _, _), + [52] = PINGROUP(52, EAST, _, nav_gpio, pbs_out, _, _, _, _, _, _), + [53] = PINGROUP(53, EAST, _, gsm1_tx, _, _, _, _, _, _, _), + [54] = PINGROUP(54, EAST, _, _, _, _, _, _, _, _, _), + [55] = PINGROUP(55, EAST, _, _, _, _, _, _, _, _, _), + [56] = PINGROUP(56, EAST, _, _, _, _, _, _, _, _, _), + [57] = PINGROUP(57, EAST, _, _, _, _, _, _, _, _, _), + [58] = PINGROUP(58, EAST, _, _, _, _, _, _, _, _, _), + [59] = PINGROUP(59, EAST, _, ssbi_wtr1, _, _, _, _, _, _, _), + [60] = PINGROUP(60, EAST, _, ssbi_wtr1, _, _, _, _, _, _, _), + [61] = PINGROUP(61, EAST, _, _, _, _, _, _, _, _, _), + [62] = PINGROUP(62, EAST, _, pll_bypassnl, _, _, _, _, _, _, _), + [63] = PINGROUP(63, EAST, pll_reset, _, phase_flag, ddr_pxi0, _, _, _, _, _), + [64] = PINGROUP(64, EAST, gsm0_tx, _, phase_flag, ddr_pxi0, _, _, _, _, _), + [65] = PINGROUP(65, WEST, _, _, _, _, _, _, _, _, _), + [66] = PINGROUP(66, WEST, _, _, _, _, _, _, _, _, _), + [67] = PINGROUP(67, WEST, _, _, _, _, _, _, _, _, _), + [68] = PINGROUP(68, WEST, _, _, _, _, _, _, _, _, _), + [69] = PINGROUP(69, WEST, qup1, gcc_gp2, qdss_gpio, ddr_pxi1, _, _, _, _, _), + [70] = PINGROUP(70, WEST, qup1, gcc_gp3, qdss_gpio, ddr_pxi1, _, _, _, _, _), + [71] = PINGROUP(71, WEST, qup2, dbg_out, _, _, _, _, _, _, _), + [72] = PINGROUP(72, SOUTH, uim2_data, qdss_cti, _, _, _, _, _, _, _), + [73] = PINGROUP(73, SOUTH, uim2_clk, _, qdss_cti, _, _, _, _, _, _), + [74] = PINGROUP(74, SOUTH, uim2_reset, _, _, _, _, _, _, _, _), + [75] = PINGROUP(75, SOUTH, uim2_present, _, _, _, _, _, _, _, _), + [76] = PINGROUP(76, SOUTH, uim1_data, _, _, _, _, _, _, _, _), + [77] = PINGROUP(77, SOUTH, uim1_clk, _, _, _, _, _, _, _, _), + [78] = PINGROUP(78, SOUTH, uim1_reset, _, _, _, _, _, _, _, _), + [79] = PINGROUP(79, SOUTH, uim1_present, _, _, _, _, _, _, _, _), + [80] = PINGROUP(80, WEST, qup2, dac_calib, _, _, _, _, _, _, _), + [81] = PINGROUP(81, WEST, mdp_vsync_out_0, mdp_vsync_out_1, mdp_vsync, dac_calib, _, _, _, _, _), + [82] = PINGROUP(82, WEST, qup0, dac_calib, _, _, _, _, _, _, _), + [83] = PINGROUP(83, WEST, _, _, _, _, _, _, _, _, _), + [84] = PINGROUP(84, WEST, _, _, _, _, _, _, _, _, _), + [85] = PINGROUP(85, WEST, _, _, _, _, _, _, _, _, _), + [86] = PINGROUP(86, WEST, qup0, gcc_gp1, atest, _, _, _, _, _, _), + [87] = PINGROUP(87, EAST, pbs, qdss_gpio, _, _, _, _, _, _, _), + [88] = PINGROUP(88, EAST, _, _, _, _, _, _, _, _, _), + [89] = PINGROUP(89, WEST, usb_phy, atest, _, _, _, _, _, _, _), + [90] = PINGROUP(90, EAST, mss_lte, pbs, qdss_gpio, _, _, _, _, _, _), + [91] = PINGROUP(91, EAST, mss_lte, pbs, qdss_gpio, _, _, _, _, _, _), + [92] = PINGROUP(92, WEST, _, _, _, _, _, _, _, _, _), + [93] = PINGROUP(93, WEST, _, _, _, _, _, _, _, _, _), + [94] = PINGROUP(94, WEST, _, qdss_gpio, wlan1_adc0, _, _, _, _, _, _), + [95] = PINGROUP(95, WEST, nav_gpio, gp_pdm0, qdss_gpio, wlan1_adc1, _, _, _, _, _), + [96] = PINGROUP(96, WEST, qup4, nav_gpio, mdp_vsync, gp_pdm1, sd_write, jitter_bist, qdss_cti, qdss_cti, _), + [97] = PINGROUP(97, WEST, qup4, nav_gpio, mdp_vsync, gp_pdm2, jitter_bist, qdss_cti, qdss_cti, _, _), + [98] = PINGROUP(98, SOUTH, _, _, _, _, _, _, _, _, _), + [99] = PINGROUP(99, SOUTH, _, _, _, _, _, _, _, _, _), + [100] = PINGROUP(100, SOUTH, atest, _, _, _, _, _, _, _, _), + [101] = PINGROUP(101, SOUTH, atest, _, _, _, _, _, _, _, _), + [102] = PINGROUP(102, SOUTH, _, phase_flag, dac_calib, ddr_pxi2, _, _, _, _, _), + [103] = PINGROUP(103, SOUTH, _, phase_flag, dac_calib, ddr_pxi2, _, _, _, _, _), + [104] = PINGROUP(104, SOUTH, _, phase_flag, qdss_gpio, dac_calib, ddr_pxi3, _, _, _, _), + [105] = PINGROUP(105, SOUTH, _, phase_flag, qdss_gpio, dac_calib, ddr_pxi3, _, _, _, _), + [106] = PINGROUP(106, SOUTH, nav_gpio, gcc_gp3, qdss_gpio, _, _, _, _, _, _), + [107] = PINGROUP(107, SOUTH, nav_gpio, gcc_gp2, qdss_gpio, _, _, _, _, _, _), + [108] = PINGROUP(108, SOUTH, nav_gpio, _, _, _, _, _, _, _, _), + [109] = PINGROUP(109, SOUTH, _, qdss_gpio, _, _, _, _, _, _, _), + [110] = PINGROUP(110, SOUTH, _, qdss_gpio, _, _, _, _, _, _, _), + [111] = PINGROUP(111, SOUTH, _, _, _, _, _, _, _, _, _), + [112] = PINGROUP(112, SOUTH, _, _, _, _, _, _, _, _, _), + [113] = UFS_RESET(ufs_reset, 0x78000), + [114] = SDC_QDSD_PINGROUP(sdc1_rclk, WEST, 0x75000, 15, 0), + [115] = SDC_QDSD_PINGROUP(sdc1_clk, WEST, 0x75000, 13, 6), + [116] = SDC_QDSD_PINGROUP(sdc1_cmd, WEST, 0x75000, 11, 3), + [117] = SDC_QDSD_PINGROUP(sdc1_data, WEST, 0x75000, 9, 0), + [118] = SDC_QDSD_PINGROUP(sdc2_clk, SOUTH, 0x73000, 14, 6), + [119] = SDC_QDSD_PINGROUP(sdc2_cmd, SOUTH, 0x73000, 11, 3), + [120] = SDC_QDSD_PINGROUP(sdc2_data, SOUTH, 0x73000, 9, 0), +}; + +static const struct msm_pinctrl_soc_data sm6115_tlmm = { + .pins = sm6115_pins, + .npins = ARRAY_SIZE(sm6115_pins), + .functions = sm6115_functions, + .nfunctions = ARRAY_SIZE(sm6115_functions), + .groups = sm6115_groups, + .ngroups = ARRAY_SIZE(sm6115_groups), + .ngpios = 114, + .tiles = sm6115_tiles, + .ntiles = ARRAY_SIZE(sm6115_tiles), +}; + +static int sm6115_tlmm_probe(struct platform_device *pdev) +{ + return msm_pinctrl_probe(pdev, &sm6115_tlmm); +} + +static const struct of_device_id sm6115_tlmm_of_match[] = { + { .compatible = "qcom,sm6115-tlmm", }, + { } +}; + +static struct platform_driver sm6115_tlmm_driver = { + .driver = { + .name = "sm6115-tlmm", + .of_match_table = sm6115_tlmm_of_match, + }, + .probe = sm6115_tlmm_probe, + .remove = msm_pinctrl_remove, +}; + +static int __init sm6115_tlmm_init(void) +{ + return platform_driver_register(&sm6115_tlmm_driver); +} +arch_initcall(sm6115_tlmm_init); + +static void __exit sm6115_tlmm_exit(void) +{ + platform_driver_unregister(&sm6115_tlmm_driver); +} +module_exit(sm6115_tlmm_exit); + +MODULE_DESCRIPTION("QTI sm6115 tlmm driver"); +MODULE_LICENSE("GPL v2"); +MODULE_DEVICE_TABLE(of, sm6115_tlmm_of_match); diff --git a/drivers/pinctrl/qcom/pinctrl-sm6125.c b/drivers/pinctrl/qcom/pinctrl-sm6125.c new file mode 100644 index 0000000000..d5e2b89695 --- /dev/null +++ b/drivers/pinctrl/qcom/pinctrl-sm6125.c @@ -0,0 +1,1269 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) + +#include <linux/module.h> +#include <linux/of.h> +#include <linux/platform_device.h> + +#include "pinctrl-msm.h" + +static const char * const sm6125_tiles[] = { + "south", + "east", + "west" +}; + +enum { + SOUTH, + EAST, + WEST +}; + +#define PINGROUP(id, _tile, f1, f2, f3, f4, f5, f6, f7, f8, f9) \ + { \ + .grp = PINCTRL_PINGROUP("gpio" #id, \ + gpio##id##_pins, \ + ARRAY_SIZE(gpio##id##_pins)), \ + .funcs = (int[]){ \ + msm_mux_gpio, /* gpio mode */ \ + msm_mux_##f1, \ + msm_mux_##f2, \ + msm_mux_##f3, \ + msm_mux_##f4, \ + msm_mux_##f5, \ + msm_mux_##f6, \ + msm_mux_##f7, \ + msm_mux_##f8, \ + msm_mux_##f9 \ + }, \ + .nfuncs = 10, \ + .ctl_reg = 0x1000 * id, \ + .io_reg = 0x4 + 0x1000 * id, \ + .intr_cfg_reg = 0x8 + 0x1000 * id, \ + .intr_status_reg = 0xc + 0x1000 * id, \ + .intr_target_reg = 0x8 + 0x1000 * id, \ + .tile = _tile, \ + .mux_bit = 2, \ + .pull_bit = 0, \ + .drv_bit = 6, \ + .oe_bit = 9, \ + .in_bit = 0, \ + .out_bit = 1, \ + .intr_enable_bit = 0, \ + .intr_status_bit = 0, \ + .intr_target_bit = 5, \ + .intr_target_kpss_val = 3, \ + .intr_raw_status_bit = 4, \ + .intr_polarity_bit = 1, \ + .intr_detection_bit = 2, \ + .intr_detection_width = 2, \ + } + +#define SDC_QDSD_PINGROUP(pg_name, _tile, ctl, pull, drv) \ + { \ + .grp = PINCTRL_PINGROUP(#pg_name, \ + pg_name##_pins, \ + ARRAY_SIZE(pg_name##_pins)), \ + .ctl_reg = ctl, \ + .io_reg = 0, \ + .intr_cfg_reg = 0, \ + .intr_status_reg = 0, \ + .intr_target_reg = 0, \ + .tile = _tile, \ + .mux_bit = -1, \ + .pull_bit = pull, \ + .drv_bit = drv, \ + .oe_bit = -1, \ + .in_bit = -1, \ + .out_bit = -1, \ + .intr_enable_bit = -1, \ + .intr_status_bit = -1, \ + .intr_target_bit = -1, \ + .intr_raw_status_bit = -1, \ + .intr_polarity_bit = -1, \ + .intr_detection_bit = -1, \ + .intr_detection_width = -1, \ + } + +#define UFS_RESET(pg_name, offset) \ + { \ + .grp = PINCTRL_PINGROUP(#pg_name, \ + pg_name##_pins, \ + ARRAY_SIZE(pg_name##_pins)), \ + .ctl_reg = offset, \ + .io_reg = offset + 0x4, \ + .intr_cfg_reg = 0, \ + .intr_status_reg = 0, \ + .intr_target_reg = 0, \ + .tile = WEST, \ + .mux_bit = -1, \ + .pull_bit = 3, \ + .drv_bit = 0, \ + .oe_bit = -1, \ + .in_bit = -1, \ + .out_bit = 0, \ + .intr_enable_bit = -1, \ + .intr_status_bit = -1, \ + .intr_target_bit = -1, \ + .intr_raw_status_bit = -1, \ + .intr_polarity_bit = -1, \ + .intr_detection_bit = -1, \ + .intr_detection_width = -1, \ + } +static const struct pinctrl_pin_desc sm6125_pins[] = { + PINCTRL_PIN(0, "GPIO_0"), + PINCTRL_PIN(1, "GPIO_1"), + PINCTRL_PIN(2, "GPIO_2"), + PINCTRL_PIN(3, "GPIO_3"), + PINCTRL_PIN(4, "GPIO_4"), + PINCTRL_PIN(5, "GPIO_5"), + PINCTRL_PIN(6, "GPIO_6"), + PINCTRL_PIN(7, "GPIO_7"), + PINCTRL_PIN(8, "GPIO_8"), + PINCTRL_PIN(9, "GPIO_9"), + PINCTRL_PIN(10, "GPIO_10"), + PINCTRL_PIN(11, "GPIO_11"), + PINCTRL_PIN(12, "GPIO_12"), + PINCTRL_PIN(13, "GPIO_13"), + PINCTRL_PIN(14, "GPIO_14"), + PINCTRL_PIN(15, "GPIO_15"), + PINCTRL_PIN(16, "GPIO_16"), + PINCTRL_PIN(17, "GPIO_17"), + PINCTRL_PIN(18, "GPIO_18"), + PINCTRL_PIN(19, "GPIO_19"), + PINCTRL_PIN(20, "GPIO_20"), + PINCTRL_PIN(21, "GPIO_21"), + PINCTRL_PIN(22, "GPIO_22"), + PINCTRL_PIN(23, "GPIO_23"), + PINCTRL_PIN(24, "GPIO_24"), + PINCTRL_PIN(25, "GPIO_25"), + PINCTRL_PIN(26, "GPIO_26"), + PINCTRL_PIN(27, "GPIO_27"), + PINCTRL_PIN(28, "GPIO_28"), + PINCTRL_PIN(29, "GPIO_29"), + PINCTRL_PIN(30, "GPIO_30"), + PINCTRL_PIN(31, "GPIO_31"), + PINCTRL_PIN(32, "GPIO_32"), + PINCTRL_PIN(33, "GPIO_33"), + PINCTRL_PIN(34, "GPIO_34"), + PINCTRL_PIN(35, "GPIO_35"), + PINCTRL_PIN(36, "GPIO_36"), + PINCTRL_PIN(37, "GPIO_37"), + PINCTRL_PIN(38, "GPIO_38"), + PINCTRL_PIN(39, "GPIO_39"), + PINCTRL_PIN(40, "GPIO_40"), + PINCTRL_PIN(41, "GPIO_41"), + PINCTRL_PIN(42, "GPIO_42"), + PINCTRL_PIN(43, "GPIO_43"), + PINCTRL_PIN(44, "GPIO_44"), + PINCTRL_PIN(45, "GPIO_45"), + PINCTRL_PIN(46, "GPIO_46"), + PINCTRL_PIN(47, "GPIO_47"), + PINCTRL_PIN(48, "GPIO_48"), + PINCTRL_PIN(49, "GPIO_49"), + PINCTRL_PIN(50, "GPIO_50"), + PINCTRL_PIN(51, "GPIO_51"), + PINCTRL_PIN(52, "GPIO_52"), + PINCTRL_PIN(53, "GPIO_53"), + PINCTRL_PIN(54, "GPIO_54"), + PINCTRL_PIN(55, "GPIO_55"), + PINCTRL_PIN(56, "GPIO_56"), + PINCTRL_PIN(57, "GPIO_57"), + PINCTRL_PIN(58, "GPIO_58"), + PINCTRL_PIN(59, "GPIO_59"), + PINCTRL_PIN(60, "GPIO_60"), + PINCTRL_PIN(61, "GPIO_61"), + PINCTRL_PIN(62, "GPIO_62"), + PINCTRL_PIN(63, "GPIO_63"), + PINCTRL_PIN(64, "GPIO_64"), + PINCTRL_PIN(65, "GPIO_65"), + PINCTRL_PIN(66, "GPIO_66"), + PINCTRL_PIN(67, "GPIO_67"), + PINCTRL_PIN(68, "GPIO_68"), + PINCTRL_PIN(69, "GPIO_69"), + PINCTRL_PIN(70, "GPIO_70"), + PINCTRL_PIN(71, "GPIO_71"), + PINCTRL_PIN(72, "GPIO_72"), + PINCTRL_PIN(73, "GPIO_73"), + PINCTRL_PIN(74, "GPIO_74"), + PINCTRL_PIN(75, "GPIO_75"), + PINCTRL_PIN(76, "GPIO_76"), + PINCTRL_PIN(77, "GPIO_77"), + PINCTRL_PIN(78, "GPIO_78"), + PINCTRL_PIN(79, "GPIO_79"), + PINCTRL_PIN(80, "GPIO_80"), + PINCTRL_PIN(81, "GPIO_81"), + PINCTRL_PIN(82, "GPIO_82"), + PINCTRL_PIN(83, "GPIO_83"), + PINCTRL_PIN(84, "GPIO_84"), + PINCTRL_PIN(85, "GPIO_85"), + PINCTRL_PIN(86, "GPIO_86"), + PINCTRL_PIN(87, "GPIO_87"), + PINCTRL_PIN(88, "GPIO_88"), + PINCTRL_PIN(89, "GPIO_89"), + PINCTRL_PIN(90, "GPIO_90"), + PINCTRL_PIN(91, "GPIO_91"), + PINCTRL_PIN(92, "GPIO_92"), + PINCTRL_PIN(93, "GPIO_93"), + PINCTRL_PIN(94, "GPIO_94"), + PINCTRL_PIN(95, "GPIO_95"), + PINCTRL_PIN(96, "GPIO_96"), + PINCTRL_PIN(97, "GPIO_97"), + PINCTRL_PIN(98, "GPIO_98"), + PINCTRL_PIN(99, "GPIO_99"), + PINCTRL_PIN(100, "GPIO_100"), + PINCTRL_PIN(101, "GPIO_101"), + PINCTRL_PIN(102, "GPIO_102"), + PINCTRL_PIN(103, "GPIO_103"), + PINCTRL_PIN(104, "GPIO_104"), + PINCTRL_PIN(105, "GPIO_105"), + PINCTRL_PIN(106, "GPIO_106"), + PINCTRL_PIN(107, "GPIO_107"), + PINCTRL_PIN(108, "GPIO_108"), + PINCTRL_PIN(109, "GPIO_109"), + PINCTRL_PIN(110, "GPIO_110"), + PINCTRL_PIN(111, "GPIO_111"), + PINCTRL_PIN(112, "GPIO_112"), + PINCTRL_PIN(113, "GPIO_113"), + PINCTRL_PIN(114, "GPIO_114"), + PINCTRL_PIN(115, "GPIO_115"), + PINCTRL_PIN(116, "GPIO_116"), + PINCTRL_PIN(117, "GPIO_117"), + PINCTRL_PIN(118, "GPIO_118"), + PINCTRL_PIN(119, "GPIO_119"), + PINCTRL_PIN(120, "GPIO_120"), + PINCTRL_PIN(121, "GPIO_121"), + PINCTRL_PIN(122, "GPIO_122"), + PINCTRL_PIN(123, "GPIO_123"), + PINCTRL_PIN(124, "GPIO_124"), + PINCTRL_PIN(125, "GPIO_125"), + PINCTRL_PIN(126, "GPIO_126"), + PINCTRL_PIN(127, "GPIO_127"), + PINCTRL_PIN(128, "GPIO_128"), + PINCTRL_PIN(129, "GPIO_129"), + PINCTRL_PIN(130, "GPIO_130"), + PINCTRL_PIN(131, "GPIO_131"), + PINCTRL_PIN(132, "GPIO_132"), + PINCTRL_PIN(133, "UFS_RESET"), + PINCTRL_PIN(134, "SDC1_RCLK"), + PINCTRL_PIN(135, "SDC1_CLK"), + PINCTRL_PIN(136, "SDC1_CMD"), + PINCTRL_PIN(137, "SDC1_DATA"), + PINCTRL_PIN(138, "SDC2_CLK"), + PINCTRL_PIN(139, "SDC2_CMD"), + PINCTRL_PIN(140, "SDC2_DATA"), +}; + +#define DECLARE_MSM_GPIO_PINS(pin) \ + static const unsigned int gpio##pin##_pins[] = { pin } +DECLARE_MSM_GPIO_PINS(0); +DECLARE_MSM_GPIO_PINS(1); +DECLARE_MSM_GPIO_PINS(2); +DECLARE_MSM_GPIO_PINS(3); +DECLARE_MSM_GPIO_PINS(4); +DECLARE_MSM_GPIO_PINS(5); +DECLARE_MSM_GPIO_PINS(6); +DECLARE_MSM_GPIO_PINS(7); +DECLARE_MSM_GPIO_PINS(8); +DECLARE_MSM_GPIO_PINS(9); +DECLARE_MSM_GPIO_PINS(10); +DECLARE_MSM_GPIO_PINS(11); +DECLARE_MSM_GPIO_PINS(12); +DECLARE_MSM_GPIO_PINS(13); +DECLARE_MSM_GPIO_PINS(14); +DECLARE_MSM_GPIO_PINS(15); +DECLARE_MSM_GPIO_PINS(16); +DECLARE_MSM_GPIO_PINS(17); +DECLARE_MSM_GPIO_PINS(18); +DECLARE_MSM_GPIO_PINS(19); +DECLARE_MSM_GPIO_PINS(20); +DECLARE_MSM_GPIO_PINS(21); +DECLARE_MSM_GPIO_PINS(22); +DECLARE_MSM_GPIO_PINS(23); +DECLARE_MSM_GPIO_PINS(24); +DECLARE_MSM_GPIO_PINS(25); +DECLARE_MSM_GPIO_PINS(26); +DECLARE_MSM_GPIO_PINS(27); +DECLARE_MSM_GPIO_PINS(28); +DECLARE_MSM_GPIO_PINS(29); +DECLARE_MSM_GPIO_PINS(30); +DECLARE_MSM_GPIO_PINS(31); +DECLARE_MSM_GPIO_PINS(32); +DECLARE_MSM_GPIO_PINS(33); +DECLARE_MSM_GPIO_PINS(34); +DECLARE_MSM_GPIO_PINS(35); +DECLARE_MSM_GPIO_PINS(36); +DECLARE_MSM_GPIO_PINS(37); +DECLARE_MSM_GPIO_PINS(38); +DECLARE_MSM_GPIO_PINS(39); +DECLARE_MSM_GPIO_PINS(40); +DECLARE_MSM_GPIO_PINS(41); +DECLARE_MSM_GPIO_PINS(42); +DECLARE_MSM_GPIO_PINS(43); +DECLARE_MSM_GPIO_PINS(44); +DECLARE_MSM_GPIO_PINS(45); +DECLARE_MSM_GPIO_PINS(46); +DECLARE_MSM_GPIO_PINS(47); +DECLARE_MSM_GPIO_PINS(48); +DECLARE_MSM_GPIO_PINS(49); +DECLARE_MSM_GPIO_PINS(50); +DECLARE_MSM_GPIO_PINS(51); +DECLARE_MSM_GPIO_PINS(52); +DECLARE_MSM_GPIO_PINS(53); +DECLARE_MSM_GPIO_PINS(54); +DECLARE_MSM_GPIO_PINS(55); +DECLARE_MSM_GPIO_PINS(56); +DECLARE_MSM_GPIO_PINS(57); +DECLARE_MSM_GPIO_PINS(58); +DECLARE_MSM_GPIO_PINS(59); +DECLARE_MSM_GPIO_PINS(60); +DECLARE_MSM_GPIO_PINS(61); +DECLARE_MSM_GPIO_PINS(62); +DECLARE_MSM_GPIO_PINS(63); +DECLARE_MSM_GPIO_PINS(64); +DECLARE_MSM_GPIO_PINS(65); +DECLARE_MSM_GPIO_PINS(66); +DECLARE_MSM_GPIO_PINS(67); +DECLARE_MSM_GPIO_PINS(68); +DECLARE_MSM_GPIO_PINS(69); +DECLARE_MSM_GPIO_PINS(70); +DECLARE_MSM_GPIO_PINS(71); +DECLARE_MSM_GPIO_PINS(72); +DECLARE_MSM_GPIO_PINS(73); +DECLARE_MSM_GPIO_PINS(74); +DECLARE_MSM_GPIO_PINS(75); +DECLARE_MSM_GPIO_PINS(76); +DECLARE_MSM_GPIO_PINS(77); +DECLARE_MSM_GPIO_PINS(78); +DECLARE_MSM_GPIO_PINS(79); +DECLARE_MSM_GPIO_PINS(80); +DECLARE_MSM_GPIO_PINS(81); +DECLARE_MSM_GPIO_PINS(82); +DECLARE_MSM_GPIO_PINS(83); +DECLARE_MSM_GPIO_PINS(84); +DECLARE_MSM_GPIO_PINS(85); +DECLARE_MSM_GPIO_PINS(86); +DECLARE_MSM_GPIO_PINS(87); +DECLARE_MSM_GPIO_PINS(88); +DECLARE_MSM_GPIO_PINS(89); +DECLARE_MSM_GPIO_PINS(90); +DECLARE_MSM_GPIO_PINS(91); +DECLARE_MSM_GPIO_PINS(92); +DECLARE_MSM_GPIO_PINS(93); +DECLARE_MSM_GPIO_PINS(94); +DECLARE_MSM_GPIO_PINS(95); +DECLARE_MSM_GPIO_PINS(96); +DECLARE_MSM_GPIO_PINS(97); +DECLARE_MSM_GPIO_PINS(98); +DECLARE_MSM_GPIO_PINS(99); +DECLARE_MSM_GPIO_PINS(100); +DECLARE_MSM_GPIO_PINS(101); +DECLARE_MSM_GPIO_PINS(102); +DECLARE_MSM_GPIO_PINS(103); +DECLARE_MSM_GPIO_PINS(104); +DECLARE_MSM_GPIO_PINS(105); +DECLARE_MSM_GPIO_PINS(106); +DECLARE_MSM_GPIO_PINS(107); +DECLARE_MSM_GPIO_PINS(108); +DECLARE_MSM_GPIO_PINS(109); +DECLARE_MSM_GPIO_PINS(110); +DECLARE_MSM_GPIO_PINS(111); +DECLARE_MSM_GPIO_PINS(112); +DECLARE_MSM_GPIO_PINS(113); +DECLARE_MSM_GPIO_PINS(114); +DECLARE_MSM_GPIO_PINS(115); +DECLARE_MSM_GPIO_PINS(116); +DECLARE_MSM_GPIO_PINS(117); +DECLARE_MSM_GPIO_PINS(118); +DECLARE_MSM_GPIO_PINS(119); +DECLARE_MSM_GPIO_PINS(120); +DECLARE_MSM_GPIO_PINS(121); +DECLARE_MSM_GPIO_PINS(122); +DECLARE_MSM_GPIO_PINS(123); +DECLARE_MSM_GPIO_PINS(124); +DECLARE_MSM_GPIO_PINS(125); +DECLARE_MSM_GPIO_PINS(126); +DECLARE_MSM_GPIO_PINS(127); +DECLARE_MSM_GPIO_PINS(128); +DECLARE_MSM_GPIO_PINS(129); +DECLARE_MSM_GPIO_PINS(130); +DECLARE_MSM_GPIO_PINS(131); +DECLARE_MSM_GPIO_PINS(132); + +static const unsigned int ufs_reset_pins[] = { 133 }; +static const unsigned int sdc1_rclk_pins[] = { 134 }; +static const unsigned int sdc1_clk_pins[] = { 135 }; +static const unsigned int sdc1_cmd_pins[] = { 136 }; +static const unsigned int sdc1_data_pins[] = { 137 }; +static const unsigned int sdc2_clk_pins[] = { 138 }; +static const unsigned int sdc2_cmd_pins[] = { 139 }; +static const unsigned int sdc2_data_pins[] = { 140 }; + + +enum sm6125_functions { + msm_mux_qup00, + msm_mux_gpio, + msm_mux_qdss, + msm_mux_qup01, + msm_mux_qup02, + msm_mux_ddr_pxi0, + msm_mux_ddr_bist, + msm_mux_atest_tsens2, + msm_mux_vsense_trigger, + msm_mux_atest_usb1, + msm_mux_gp_pdm1, + msm_mux_phase_flag, + msm_mux_dbg_out, + msm_mux_qup14, + msm_mux_atest_usb11, + msm_mux_ddr_pxi2, + msm_mux_atest_usb10, + msm_mux_jitter_bist, + msm_mux_ddr_pxi3, + msm_mux_pll_bypassnl, + msm_mux_pll_bist, + msm_mux_qup03, + msm_mux_pll_reset, + msm_mux_agera_pll, + msm_mux_qdss_cti, + msm_mux_qup04, + msm_mux_wlan2_adc1, + msm_mux_wlan2_adc0, + msm_mux_wsa_clk, + msm_mux_qup13, + msm_mux_ter_mi2s, + msm_mux_wsa_data, + msm_mux_qup10, + msm_mux_gcc_gp3, + msm_mux_qup12, + msm_mux_sd_write, + msm_mux_qup11, + msm_mux_cam_mclk, + msm_mux_atest_tsens, + msm_mux_cci_i2c, + msm_mux_cci_timer2, + msm_mux_cci_timer1, + msm_mux_gcc_gp2, + msm_mux_cci_async, + msm_mux_cci_timer4, + msm_mux_cci_timer0, + msm_mux_gcc_gp1, + msm_mux_cci_timer3, + msm_mux_wlan1_adc1, + msm_mux_wlan1_adc0, + msm_mux_qlink_request, + msm_mux_qlink_enable, + msm_mux_pa_indicator, + msm_mux_nav_pps, + msm_mux_gps_tx, + msm_mux_gp_pdm0, + msm_mux_atest_usb13, + msm_mux_ddr_pxi1, + msm_mux_atest_usb12, + msm_mux_cri_trng0, + msm_mux_cri_trng, + msm_mux_cri_trng1, + msm_mux_gp_pdm2, + msm_mux_sp_cmu, + msm_mux_atest_usb2, + msm_mux_atest_usb23, + msm_mux_uim2_data, + msm_mux_uim2_clk, + msm_mux_uim2_reset, + msm_mux_atest_usb22, + msm_mux_uim2_present, + msm_mux_atest_usb21, + msm_mux_uim1_data, + msm_mux_atest_usb20, + msm_mux_uim1_clk, + msm_mux_uim1_reset, + msm_mux_uim1_present, + msm_mux_mdp_vsync, + msm_mux_copy_gp, + msm_mux_tsense_pwm, + msm_mux_mpm_pwr, + msm_mux_tgu_ch3, + msm_mux_mdp_vsync0, + msm_mux_mdp_vsync1, + msm_mux_mdp_vsync2, + msm_mux_mdp_vsync3, + msm_mux_mdp_vsync4, + msm_mux_mdp_vsync5, + msm_mux_tgu_ch0, + msm_mux_tgu_ch1, + msm_mux_atest_char1, + msm_mux_vfr_1, + msm_mux_tgu_ch2, + msm_mux_atest_char0, + msm_mux_atest_char2, + msm_mux_atest_char3, + msm_mux_ldo_en, + msm_mux_ldo_update, + msm_mux_prng_rosc, + msm_mux_dp_hot, + msm_mux_debug_hot, + msm_mux_copy_phase, + msm_mux_usb_phy, + msm_mux_atest_char, + msm_mux_unused1, + msm_mux_qua_mi2s, + msm_mux_mss_lte, + msm_mux_swr_tx, + msm_mux_aud_sb, + msm_mux_unused2, + msm_mux_swr_rx, + msm_mux_edp_hot, + msm_mux_audio_ref, + msm_mux_pri_mi2s, + msm_mux_pri_mi2s_ws, + msm_mux_adsp_ext, + msm_mux_edp_lcd, + msm_mux_mclk2, + msm_mux_m_voc, + msm_mux_mclk1, + msm_mux_qca_sb, + msm_mux_qui_mi2s, + msm_mux_dmic0_clk, + msm_mux_sec_mi2s, + msm_mux_dmic0_data, + msm_mux_dmic1_clk, + msm_mux_dmic1_data, + msm_mux__, +}; + +static const char * const qup00_groups[] = { + "gpio0", "gpio1", "gpio2", "gpio3", +}; +static const char * const gpio_groups[] = { + "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7", + "gpio8", "gpio9", "gpio10", "gpio11", "gpio12", "gpio13", "gpio14", + "gpio15", "gpio16", "gpio17", "gpio18", "gpio19", "gpio20", "gpio21", + "gpio22", "gpio23", "gpio24", "gpio25", "gpio26", "gpio27", "gpio28", + "gpio29", "gpio30", "gpio31", "gpio32", "gpio33", "gpio34", "gpio35", + "gpio36", "gpio37", "gpio38", "gpio39", "gpio40", "gpio41", "gpio42", + "gpio43", "gpio44", "gpio45", "gpio46", "gpio47", "gpio48", "gpio49", + "gpio50", "gpio51", "gpio52", "gpio53", "gpio54", "gpio55", "gpio56", + "gpio57", "gpio58", "gpio59", "gpio60", "gpio61", "gpio62", "gpio63", + "gpio64", "gpio65", "gpio66", "gpio67", "gpio68", "gpio69", "gpio70", + "gpio71", "gpio72", "gpio73", "gpio74", "gpio75", "gpio76", "gpio77", + "gpio78", "gpio79", "gpio80", "gpio81", "gpio82", "gpio83", "gpio84", + "gpio85", "gpio86", "gpio87", "gpio88", "gpio89", "gpio90", "gpio91", + "gpio92", "gpio93", "gpio94", "gpio95", "gpio96", "gpio97", "gpio98", + "gpio99", "gpio100", "gpio101", "gpio102", "gpio103", "gpio104", + "gpio105", "gpio106", "gpio107", "gpio108", "gpio109", "gpio110", + "gpio111", "gpio112", "gpio113", "gpio114", "gpio115", "gpio116", + "gpio117", "gpio118", "gpio119", "gpio120", "gpio121", "gpio122", + "gpio123", "gpio124", "gpio125", "gpio126", "gpio127", "gpio128", + "gpio129", "gpio130", "gpio131", "gpio132", +}; +static const char * const qdss_groups[] = { + "gpio0", "gpio1", "gpio2", "gpio3", "gpio20", "gpio21", "gpio34", "gpio35", + "gpio36", "gpio42", "gpio41", "gpio43", "gpio44", "gpio45", "gpio46", + "gpio47", "gpio48", "gpio49", "gpio80", "gpio81", "gpio82", "gpio83", + "gpio84", "gpio85", "gpio86", "gpio91", "gpio92", "gpio94", "gpio96", + "gpio100", "gpio102", "gpio114", "gpio115", "gpio116", "gpio117", "gpio118", +}; +static const char * const qup01_groups[] = { + "gpio4", "gpio5", +}; +static const char * const qup02_groups[] = { + "gpio6", "gpio7", "gpio8", "gpio9", +}; +static const char * const ddr_pxi0_groups[] = { + "gpio6", "gpio7", +}; +static const char * const ddr_bist_groups[] = { + "gpio7", "gpio8", "gpio9", "gpio10", +}; +static const char * const atest_tsens2_groups[] = { + "gpio7", +}; +static const char * const vsense_trigger_groups[] = { + "gpio7", +}; +static const char * const atest_usb1_groups[] = { + "gpio7", +}; +static const char * const gp_pdm1_groups[] = { + "gpio8", "gpio65", +}; +static const char * const phase_flag_groups[] = { + "gpio8", "gpio9", "gpio23", "gpio24", "gpio25", "gpio26", "gpio28", + "gpio29", "gpio30", "gpio53", "gpio54", "gpio55", "gpio56", "gpio57", + "gpio58", "gpio59", "gpio60", "gpio61", "gpio62", "gpio80", "gpio81", + "gpio82", "gpio83", "gpio84", "gpio88", "gpio89", "gpio91", "gpio93", + "gpio98", "gpio129", "gpio130", "gpio131", +}; +static const char * const dbg_out_groups[] = { + "gpio9", +}; +static const char * const qup14_groups[] = { + "gpio10", "gpio11", "gpio12", "gpio13", +}; +static const char * const atest_usb11_groups[] = { + "gpio10", +}; +static const char * const ddr_pxi2_groups[] = { + "gpio10", "gpio11", +}; +static const char * const atest_usb10_groups[] = { + "gpio11", +}; +static const char * const jitter_bist_groups[] = { + "gpio12", "gpio31", +}; +static const char * const ddr_pxi3_groups[] = { + "gpio12", "gpio13", +}; +static const char * const pll_bypassnl_groups[] = { + "gpio13", +}; +static const char * const pll_bist_groups[] = { + "gpio13", "gpio32", +}; +static const char * const qup03_groups[] = { + "gpio14", "gpio15", +}; +static const char * const pll_reset_groups[] = { + "gpio14", +}; +static const char * const agera_pll_groups[] = { + "gpio14", "gpio33", +}; +static const char * const qdss_cti_groups[] = { + "gpio14", "gpio15", "gpio95", "gpio101", "gpio106", "gpio107", + "gpio110", "gpio111", +}; +static const char * const qup04_groups[] = { + "gpio16", "gpio17", +}; +static const char * const wlan2_adc1_groups[] = { + "gpio16", +}; +static const char * const wlan2_adc0_groups[] = { + "gpio17", +}; +static const char * const wsa_clk_groups[] = { + "gpio18", +}; +static const char * const qup13_groups[] = { + "gpio18", "gpio19", "gpio20", "gpio21", +}; +static const char * const ter_mi2s_groups[] = { + "gpio18", "gpio19", "gpio20", "gpio21", +}; +static const char * const wsa_data_groups[] = { + "gpio19", +}; +static const char * const qup10_groups[] = { + "gpio22", "gpio23", "gpio24", "gpio25", "gpio26", "gpio27", +}; +static const char * const gcc_gp3_groups[] = { + "gpio22", "gpio58", +}; +static const char * const qup12_groups[] = { + "gpio28", "gpio29", +}; +static const char * const sd_write_groups[] = { + "gpio29", +}; +static const char * const qup11_groups[] = { + "gpio30", "gpio31", "gpio32", "gpio33", +}; +static const char * const cam_mclk_groups[] = { + "gpio34", "gpio35", "gpio36", "gpio44", +}; +static const char * const atest_tsens_groups[] = { + "gpio34", +}; +static const char * const cci_i2c_groups[] = { + "gpio37", "gpio38", "gpio39", "gpio40", +}; +static const char * const cci_timer2_groups[] = { + "gpio42", +}; +static const char * const cci_timer1_groups[] = { + "gpio43", +}; +static const char * const gcc_gp2_groups[] = { + "gpio43", "gpio44", +}; +static const char * const cci_async_groups[] = { + "gpio44", "gpio47", "gpio48", +}; +static const char * const cci_timer4_groups[] = { + "gpio44", +}; +static const char * const cci_timer0_groups[] = { + "gpio45", +}; +static const char * const gcc_gp1_groups[] = { + "gpio45", "gpio46", +}; +static const char * const cci_timer3_groups[] = { + "gpio46", +}; +static const char * const wlan1_adc1_groups[] = { + "gpio47", +}; +static const char * const wlan1_adc0_groups[] = { + "gpio48", +}; +static const char * const qlink_request_groups[] = { + "gpio50", +}; +static const char * const qlink_enable_groups[] = { + "gpio51", +}; +static const char * const pa_indicator_groups[] = { + "gpio52", +}; +static const char * const nav_pps_groups[] = { + "gpio52", "gpio55", "gpio56", "gpio58", + "gpio59", +}; +static const char * const gps_tx_groups[] = { + "gpio52", "gpio53", "gpio55", "gpio56", "gpio58", "gpio59", +}; +static const char * const gp_pdm0_groups[] = { + "gpio53", "gpio94", +}; +static const char * const atest_usb13_groups[] = { + "gpio53", +}; +static const char * const ddr_pxi1_groups[] = { + "gpio53", "gpio54", +}; +static const char * const atest_usb12_groups[] = { + "gpio54", +}; +static const char * const cri_trng0_groups[] = { + "gpio59", +}; +static const char * const cri_trng_groups[] = { + "gpio60", +}; +static const char * const cri_trng1_groups[] = { + "gpio61", +}; +static const char * const gp_pdm2_groups[] = { + "gpio62", "gpio78", +}; +static const char * const sp_cmu_groups[] = { + "gpio63", +}; +static const char * const atest_usb2_groups[] = { + "gpio66", +}; +static const char * const atest_usb23_groups[] = { + "gpio67", +}; +static const char * const uim2_data_groups[] = { + "gpio72", +}; +static const char * const uim2_clk_groups[] = { + "gpio73", +}; +static const char * const uim2_reset_groups[] = { + "gpio74", +}; +static const char * const atest_usb22_groups[] = { + "gpio74", +}; +static const char * const uim2_present_groups[] = { + "gpio75", +}; +static const char * const atest_usb21_groups[] = { + "gpio75", +}; +static const char * const uim1_data_groups[] = { + "gpio76", +}; +static const char * const atest_usb20_groups[] = { + "gpio76", +}; +static const char * const uim1_clk_groups[] = { + "gpio77", +}; +static const char * const uim1_reset_groups[] = { + "gpio78", +}; +static const char * const uim1_present_groups[] = { + "gpio79", +}; +static const char * const mdp_vsync_groups[] = { + "gpio80", "gpio81", "gpio82", "gpio89", "gpio96", "gpio97", +}; +static const char * const copy_gp_groups[] = { + "gpio85", +}; +static const char * const tsense_pwm_groups[] = { + "gpio87", +}; +static const char * const mpm_pwr_groups[] = { + "gpio88", +}; +static const char * const tgu_ch3_groups[] = { + "gpio88", +}; +static const char * const mdp_vsync0_groups[] = { + "gpio89", +}; +static const char * const mdp_vsync1_groups[] = { + "gpio89", +}; +static const char * const mdp_vsync2_groups[] = { + "gpio89", +}; +static const char * const mdp_vsync3_groups[] = { + "gpio89", +}; +static const char * const mdp_vsync4_groups[] = { + "gpio89", +}; +static const char * const mdp_vsync5_groups[] = { + "gpio89", +}; +static const char * const tgu_ch0_groups[] = { + "gpio89", +}; +static const char * const tgu_ch1_groups[] = { + "gpio90", +}; +static const char * const atest_char1_groups[] = { + "gpio90", +}; +static const char * const vfr_1_groups[] = { + "gpio91", +}; +static const char * const tgu_ch2_groups[] = { + "gpio91", +}; +static const char * const atest_char0_groups[] = { + "gpio92", +}; +static const char * const atest_char2_groups[] = { + "gpio93", +}; +static const char * const atest_char3_groups[] = { + "gpio94", +}; +static const char * const ldo_en_groups[] = { + "gpio96", +}; +static const char * const ldo_update_groups[] = { + "gpio97", +}; +static const char * const prng_rosc_groups[] = { + "gpio98", "gpio100", +}; +static const char * const dp_hot_groups[] = { + "gpio100", +}; +static const char * const debug_hot_groups[] = { + "gpio101", +}; +static const char * const copy_phase_groups[] = { + "gpio101", +}; +static const char * const usb_phy_groups[] = { + "gpio102", +}; +static const char * const atest_char_groups[] = { + "gpio102", +}; +static const char * const unused1_groups[] = { + "gpio104", +}; +static const char * const qua_mi2s_groups[] = { + "gpio104", "gpio106", "gpio107", "gpio108", "gpio110", "gpio111", +}; +static const char * const mss_lte_groups[] = { + "gpio105", "gpio109", +}; +static const char * const swr_tx_groups[] = { + "gpio106", "gpio107", "gpio108", "gpio109", +}; +static const char * const aud_sb_groups[] = { + "gpio106", "gpio107", "gpio108", "gpio109", +}; +static const char * const unused2_groups[] = { + "gpio109", +}; +static const char * const swr_rx_groups[] = { + "gpio110", "gpio111", "gpio112", +}; +static const char * const edp_hot_groups[] = { + "gpio111", +}; +static const char * const audio_ref_groups[] = { + "gpio112", +}; +static const char * const pri_mi2s_groups[] = { + "gpio113", "gpio115", "gpio116", +}; +static const char * const pri_mi2s_ws_groups[] = { + "gpio114", +}; +static const char * const adsp_ext_groups[] = { + "gpio116", +}; +static const char * const edp_lcd_groups[] = { + "gpio117", +}; +static const char * const mclk2_groups[] = { + "gpio118", +}; +static const char * const m_voc_groups[] = { + "gpio118", +}; +static const char * const mclk1_groups[] = { + "gpio119", +}; +static const char * const qca_sb_groups[] = { + "gpio121", "gpio122", +}; +static const char * const qui_mi2s_groups[] = { + "gpio121", "gpio122", "gpio123", "gpio124", +}; +static const char * const dmic0_clk_groups[] = { + "gpio125", +}; +static const char * const sec_mi2s_groups[] = { + "gpio125", "gpio126", "gpio127", "gpio128", +}; +static const char * const dmic0_data_groups[] = { + "gpio126", +}; +static const char * const dmic1_clk_groups[] = { + "gpio127", +}; +static const char * const dmic1_data_groups[] = { + "gpio128", +}; + +static const struct pinfunction sm6125_functions[] = { + MSM_PIN_FUNCTION(qup00), + MSM_PIN_FUNCTION(gpio), + MSM_PIN_FUNCTION(qdss), + MSM_PIN_FUNCTION(qup01), + MSM_PIN_FUNCTION(qup02), + MSM_PIN_FUNCTION(ddr_pxi0), + MSM_PIN_FUNCTION(ddr_bist), + MSM_PIN_FUNCTION(atest_tsens2), + MSM_PIN_FUNCTION(vsense_trigger), + MSM_PIN_FUNCTION(atest_usb1), + MSM_PIN_FUNCTION(gp_pdm1), + MSM_PIN_FUNCTION(phase_flag), + MSM_PIN_FUNCTION(dbg_out), + MSM_PIN_FUNCTION(qup14), + MSM_PIN_FUNCTION(atest_usb11), + MSM_PIN_FUNCTION(ddr_pxi2), + MSM_PIN_FUNCTION(atest_usb10), + MSM_PIN_FUNCTION(jitter_bist), + MSM_PIN_FUNCTION(ddr_pxi3), + MSM_PIN_FUNCTION(pll_bypassnl), + MSM_PIN_FUNCTION(pll_bist), + MSM_PIN_FUNCTION(qup03), + MSM_PIN_FUNCTION(pll_reset), + MSM_PIN_FUNCTION(agera_pll), + MSM_PIN_FUNCTION(qdss_cti), + MSM_PIN_FUNCTION(qup04), + MSM_PIN_FUNCTION(wlan2_adc1), + MSM_PIN_FUNCTION(wlan2_adc0), + MSM_PIN_FUNCTION(wsa_clk), + MSM_PIN_FUNCTION(qup13), + MSM_PIN_FUNCTION(ter_mi2s), + MSM_PIN_FUNCTION(wsa_data), + MSM_PIN_FUNCTION(qup10), + MSM_PIN_FUNCTION(gcc_gp3), + MSM_PIN_FUNCTION(qup12), + MSM_PIN_FUNCTION(sd_write), + MSM_PIN_FUNCTION(qup11), + MSM_PIN_FUNCTION(cam_mclk), + MSM_PIN_FUNCTION(atest_tsens), + MSM_PIN_FUNCTION(cci_i2c), + MSM_PIN_FUNCTION(cci_timer2), + MSM_PIN_FUNCTION(cci_timer1), + MSM_PIN_FUNCTION(gcc_gp2), + MSM_PIN_FUNCTION(cci_async), + MSM_PIN_FUNCTION(cci_timer4), + MSM_PIN_FUNCTION(cci_timer0), + MSM_PIN_FUNCTION(gcc_gp1), + MSM_PIN_FUNCTION(cci_timer3), + MSM_PIN_FUNCTION(wlan1_adc1), + MSM_PIN_FUNCTION(wlan1_adc0), + MSM_PIN_FUNCTION(qlink_request), + MSM_PIN_FUNCTION(qlink_enable), + MSM_PIN_FUNCTION(pa_indicator), + MSM_PIN_FUNCTION(nav_pps), + MSM_PIN_FUNCTION(gps_tx), + MSM_PIN_FUNCTION(gp_pdm0), + MSM_PIN_FUNCTION(atest_usb13), + MSM_PIN_FUNCTION(ddr_pxi1), + MSM_PIN_FUNCTION(atest_usb12), + MSM_PIN_FUNCTION(cri_trng0), + MSM_PIN_FUNCTION(cri_trng), + MSM_PIN_FUNCTION(cri_trng1), + MSM_PIN_FUNCTION(gp_pdm2), + MSM_PIN_FUNCTION(sp_cmu), + MSM_PIN_FUNCTION(atest_usb2), + MSM_PIN_FUNCTION(atest_usb23), + MSM_PIN_FUNCTION(uim2_data), + MSM_PIN_FUNCTION(uim2_clk), + MSM_PIN_FUNCTION(uim2_reset), + MSM_PIN_FUNCTION(atest_usb22), + MSM_PIN_FUNCTION(uim2_present), + MSM_PIN_FUNCTION(atest_usb21), + MSM_PIN_FUNCTION(uim1_data), + MSM_PIN_FUNCTION(atest_usb20), + MSM_PIN_FUNCTION(uim1_clk), + MSM_PIN_FUNCTION(uim1_reset), + MSM_PIN_FUNCTION(uim1_present), + MSM_PIN_FUNCTION(mdp_vsync), + MSM_PIN_FUNCTION(copy_gp), + MSM_PIN_FUNCTION(tsense_pwm), + MSM_PIN_FUNCTION(mpm_pwr), + MSM_PIN_FUNCTION(tgu_ch3), + MSM_PIN_FUNCTION(mdp_vsync0), + MSM_PIN_FUNCTION(mdp_vsync1), + MSM_PIN_FUNCTION(mdp_vsync2), + MSM_PIN_FUNCTION(mdp_vsync3), + MSM_PIN_FUNCTION(mdp_vsync4), + MSM_PIN_FUNCTION(mdp_vsync5), + MSM_PIN_FUNCTION(tgu_ch0), + MSM_PIN_FUNCTION(tgu_ch1), + MSM_PIN_FUNCTION(atest_char1), + MSM_PIN_FUNCTION(vfr_1), + MSM_PIN_FUNCTION(tgu_ch2), + MSM_PIN_FUNCTION(atest_char0), + MSM_PIN_FUNCTION(atest_char2), + MSM_PIN_FUNCTION(atest_char3), + MSM_PIN_FUNCTION(ldo_en), + MSM_PIN_FUNCTION(ldo_update), + MSM_PIN_FUNCTION(prng_rosc), + MSM_PIN_FUNCTION(dp_hot), + MSM_PIN_FUNCTION(debug_hot), + MSM_PIN_FUNCTION(copy_phase), + MSM_PIN_FUNCTION(usb_phy), + MSM_PIN_FUNCTION(atest_char), + MSM_PIN_FUNCTION(unused1), + MSM_PIN_FUNCTION(qua_mi2s), + MSM_PIN_FUNCTION(mss_lte), + MSM_PIN_FUNCTION(swr_tx), + MSM_PIN_FUNCTION(aud_sb), + MSM_PIN_FUNCTION(unused2), + MSM_PIN_FUNCTION(swr_rx), + MSM_PIN_FUNCTION(edp_hot), + MSM_PIN_FUNCTION(audio_ref), + MSM_PIN_FUNCTION(pri_mi2s), + MSM_PIN_FUNCTION(pri_mi2s_ws), + MSM_PIN_FUNCTION(adsp_ext), + MSM_PIN_FUNCTION(edp_lcd), + MSM_PIN_FUNCTION(mclk2), + MSM_PIN_FUNCTION(m_voc), + MSM_PIN_FUNCTION(mclk1), + MSM_PIN_FUNCTION(qca_sb), + MSM_PIN_FUNCTION(qui_mi2s), + MSM_PIN_FUNCTION(dmic0_clk), + MSM_PIN_FUNCTION(sec_mi2s), + MSM_PIN_FUNCTION(dmic0_data), + MSM_PIN_FUNCTION(dmic1_clk), + MSM_PIN_FUNCTION(dmic1_data), +}; + + /* + * Every pin is maintained as a single group, and missing or non-existing pin + * would be maintained as dummy group to synchronize pin group index with + * pin descriptor registered with pinctrl core. + * Clients would not be able to request these dummy pin groups. + */ +static const struct msm_pingroup sm6125_groups[] = { + [0] = PINGROUP(0, WEST, qup00, _, qdss, _, _, _, _, _, _), + [1] = PINGROUP(1, WEST, qup00, _, qdss, _, _, _, _, _, _), + [2] = PINGROUP(2, WEST, qup00, _, qdss, _, _, _, _, _, _), + [3] = PINGROUP(3, WEST, qup00, _, qdss, _, _, _, _, _, _), + [4] = PINGROUP(4, WEST, qup01, _, _, _, _, _, _, _, _), + [5] = PINGROUP(5, WEST, qup01, _, _, _, _, _, _, _, _), + [6] = PINGROUP(6, WEST, qup02, ddr_pxi0, _, _, _, _, _, _, _), + [7] = PINGROUP(7, WEST, qup02, ddr_bist, atest_tsens2, vsense_trigger, atest_usb1, ddr_pxi0, _, _, _), + [8] = PINGROUP(8, WEST, qup02, gp_pdm1, ddr_bist, _, phase_flag, _, _, _, _), + [9] = PINGROUP(9, WEST, qup02, ddr_bist, dbg_out, phase_flag, _, _, _, _, _), + [10] = PINGROUP(10, EAST, qup14, ddr_bist, atest_usb11, ddr_pxi2, _, _, _, _, _), + [11] = PINGROUP(11, EAST, qup14, atest_usb10, ddr_pxi2, _, _, _, _, _, _), + [12] = PINGROUP(12, EAST, qup14, jitter_bist, ddr_pxi3, _, _, _, _, _, _), + [13] = PINGROUP(13, EAST, qup14, pll_bypassnl, pll_bist, _, ddr_pxi3, _, _, _, _), + [14] = PINGROUP(14, WEST, qup03, qup03, pll_reset, agera_pll, _, qdss_cti, _, _, _), + [15] = PINGROUP(15, WEST, qup03, qup03, qdss_cti, _, _, _, _, _, _), + [16] = PINGROUP(16, WEST, qup04, qup04, _, wlan2_adc1, _, _, _, _, _), + [17] = PINGROUP(17, WEST, qup04, qup04, _, wlan2_adc0, _, _, _, _, _), + [18] = PINGROUP(18, EAST, wsa_clk, qup13, ter_mi2s, _, _, _, _, _, _), + [19] = PINGROUP(19, EAST, wsa_data, qup13, ter_mi2s, _, _, _, _, _, _), + [20] = PINGROUP(20, EAST, qup13, ter_mi2s, qdss, _, _, _, _, _, _), + [21] = PINGROUP(21, EAST, qup13, ter_mi2s, _, qdss, _, _, _, _, _), + [22] = PINGROUP(22, WEST, qup10, gcc_gp3, _, _, _, _, _, _, _), + [23] = PINGROUP(23, WEST, qup10, _, phase_flag, _, _, _, _, _, _), + [24] = PINGROUP(24, WEST, qup10, _, phase_flag, _, _, _, _, _, _), + [25] = PINGROUP(25, WEST, qup10, _, phase_flag, _, _, _, _, _, _), + [26] = PINGROUP(26, WEST, qup10, _, phase_flag, _, _, _, _, _, _), + [27] = PINGROUP(27, WEST, qup10, _, _, _, _, _, _, _, _), + [28] = PINGROUP(28, WEST, qup12, _, phase_flag, _, _, _, _, _, _), + [29] = PINGROUP(29, WEST, qup12, sd_write, _, phase_flag, _, _, _, _, _), + [30] = PINGROUP(30, WEST, qup11, _, phase_flag, _, _, _, _, _, _), + [31] = PINGROUP(31, WEST, qup11, jitter_bist, _, _, _, _, _, _, _), + [32] = PINGROUP(32, WEST, qup11, pll_bist, _, _, _, _, _, _, _), + [33] = PINGROUP(33, WEST, qup11, agera_pll, _, _, _, _, _, _, _), + [34] = PINGROUP(34, SOUTH, cam_mclk, _, qdss, atest_tsens, _, _, _, _, _), + [35] = PINGROUP(35, SOUTH, cam_mclk, _, qdss, _, _, _, _, _, _), + [36] = PINGROUP(36, SOUTH, cam_mclk, _, qdss, _, _, _, _, _, _), + [37] = PINGROUP(37, SOUTH, cci_i2c, _, _, _, _, _, _, _, _), + [38] = PINGROUP(38, EAST, cci_i2c, _, _, _, _, _, _, _, _), + [39] = PINGROUP(39, EAST, cci_i2c, _, _, _, _, _, _, _, _), + [40] = PINGROUP(40, EAST, cci_i2c, _, _, _, _, _, _, _, _), + [41] = PINGROUP(41, EAST, _, qdss, _, _, _, _, _, _, _), + [42] = PINGROUP(42, EAST, cci_timer2, _, qdss, _, _, _, _, _, _), + [43] = PINGROUP(43, EAST, cci_timer1, _, gcc_gp2, _, qdss, _, _, _, _), + [44] = PINGROUP(44, SOUTH, cci_async, cci_timer4, _, gcc_gp2, _, qdss, cam_mclk, _, _), + [45] = PINGROUP(45, SOUTH, cci_timer0, _, gcc_gp1, qdss, _, _, _, _, _), + [46] = PINGROUP(46, SOUTH, cci_timer3, _, gcc_gp1, _, qdss, _, _, _, _), + [47] = PINGROUP(47, SOUTH, cci_async, _, qdss, wlan1_adc1, _, _, _, _, _), + [48] = PINGROUP(48, SOUTH, cci_async, _, qdss, wlan1_adc0, _, _, _, _, _), + [49] = PINGROUP(49, SOUTH, qdss, _, _, _, _, _, _, _, _), + [50] = PINGROUP(50, SOUTH, qlink_request, _, _, _, _, _, _, _, _), + [51] = PINGROUP(51, SOUTH, qlink_enable, _, _, _, _, _, _, _, _), + [52] = PINGROUP(52, SOUTH, pa_indicator, nav_pps, nav_pps, gps_tx, _, _, _, _, _), + [53] = PINGROUP(53, SOUTH, _, gps_tx, gp_pdm0, _, phase_flag, atest_usb13, ddr_pxi1, _, _), + [54] = PINGROUP(54, SOUTH, _, _, phase_flag, atest_usb12, ddr_pxi1, _, _, _, _), + [55] = PINGROUP(55, SOUTH, _, nav_pps, nav_pps, gps_tx, _, phase_flag, _, _, _), + [56] = PINGROUP(56, SOUTH, _, nav_pps, gps_tx, nav_pps, phase_flag, _, _, _, _), + [57] = PINGROUP(57, SOUTH, _, phase_flag, _, _, _, _, _, _, _), + [58] = PINGROUP(58, SOUTH, _, nav_pps, nav_pps, gps_tx, gcc_gp3, _, phase_flag, _, _), + [59] = PINGROUP(59, SOUTH, _, nav_pps, nav_pps, gps_tx, cri_trng0, _, phase_flag, _, _), + [60] = PINGROUP(60, SOUTH, _, cri_trng, _, phase_flag, _, _, _, _, _), + [61] = PINGROUP(61, SOUTH, _, cri_trng1, _, phase_flag, _, _, _, _, _), + [62] = PINGROUP(62, SOUTH, _, _, gp_pdm2, _, phase_flag, _, _, _, _), + [63] = PINGROUP(63, SOUTH, _, sp_cmu, _, _, _, _, _, _, _), + [64] = PINGROUP(64, SOUTH, _, _, _, _, _, _, _, _, _), + [65] = PINGROUP(65, SOUTH, _, gp_pdm1, _, _, _, _, _, _, _), + [66] = PINGROUP(66, SOUTH, _, _, atest_usb2, _, _, _, _, _, _), + [67] = PINGROUP(67, SOUTH, _, _, atest_usb23, _, _, _, _, _, _), + [68] = PINGROUP(68, SOUTH, _, _, _, _, _, _, _, _, _), + [69] = PINGROUP(69, SOUTH, _, _, _, _, _, _, _, _, _), + [70] = PINGROUP(70, SOUTH, _, _, _, _, _, _, _, _, _), + [71] = PINGROUP(71, SOUTH, _, _, _, _, _, _, _, _, _), + [72] = PINGROUP(72, SOUTH, uim2_data, _, _, _, _, _, _, _, _), + [73] = PINGROUP(73, SOUTH, uim2_clk, _, _, _, _, _, _, _, _), + [74] = PINGROUP(74, SOUTH, uim2_reset, _, atest_usb22, _, _, _, _, _, _), + [75] = PINGROUP(75, SOUTH, uim2_present, _, atest_usb21, _, _, _, _, _, _), + [76] = PINGROUP(76, SOUTH, uim1_data, _, atest_usb20, _, _, _, _, _, _), + [77] = PINGROUP(77, SOUTH, uim1_clk, _, _, _, _, _, _, _, _), + [78] = PINGROUP(78, SOUTH, uim1_reset, gp_pdm2, _, _, _, _, _, _, _), + [79] = PINGROUP(79, SOUTH, uim1_present, _, _, _, _, _, _, _, _), + [80] = PINGROUP(80, SOUTH, mdp_vsync, _, phase_flag, qdss, _, _, _, _, _), + [81] = PINGROUP(81, SOUTH, mdp_vsync, _, phase_flag, qdss, _, _, _, _, _), + [82] = PINGROUP(82, SOUTH, mdp_vsync, _, phase_flag, qdss, _, _, _, _, _), + [83] = PINGROUP(83, SOUTH, _, phase_flag, qdss, _, _, _, _, _, _), + [84] = PINGROUP(84, SOUTH, _, phase_flag, qdss, _, _, _, _, _, _), + [85] = PINGROUP(85, SOUTH, copy_gp, _, qdss, _, _, _, _, _, _), + [86] = PINGROUP(86, SOUTH, _, qdss, _, _, _, _, _, _, _), + [87] = PINGROUP(87, WEST, tsense_pwm, _, _, _, _, _, _, _, _), + [88] = PINGROUP(88, WEST, mpm_pwr, tgu_ch3, _, phase_flag, _, _, _, _, _), + [89] = PINGROUP(89, WEST, mdp_vsync, mdp_vsync0, mdp_vsync1, mdp_vsync2, mdp_vsync3, mdp_vsync4, mdp_vsync5, tgu_ch0, _), + [90] = PINGROUP(90, WEST, tgu_ch1, atest_char1, _, _, _, _, _, _, _), + [91] = PINGROUP(91, WEST, vfr_1, tgu_ch2, _, phase_flag, qdss, _, _, _, _), + [92] = PINGROUP(92, WEST, qdss, atest_char0, _, _, _, _, _, _, _), + [93] = PINGROUP(93, WEST, _, phase_flag, atest_char2, _, _, _, _, _, _), + [94] = PINGROUP(94, SOUTH, gp_pdm0, _, qdss, atest_char3, _, _, _, _, _), + [95] = PINGROUP(95, SOUTH, qdss_cti, _, _, _, _, _, _, _, _), + [96] = PINGROUP(96, SOUTH, mdp_vsync, ldo_en, qdss, _, _, _, _, _, _), + [97] = PINGROUP(97, SOUTH, mdp_vsync, ldo_update, _, _, _, _, _, _, _), + [98] = PINGROUP(98, SOUTH, _, phase_flag, prng_rosc, _, _, _, _, _, _), + [99] = PINGROUP(99, SOUTH, _, _, _, _, _, _, _, _, _), + [100] = PINGROUP(100, SOUTH, dp_hot, prng_rosc, qdss, _, _, _, _, _, _), + [101] = PINGROUP(101, SOUTH, debug_hot, copy_phase, qdss_cti, _, _, _, _, _, _), + [102] = PINGROUP(102, SOUTH, usb_phy, _, qdss, atest_char, _, _, _, _, _), + [103] = PINGROUP(103, SOUTH, _, _, _, _, _, _, _, _, _), + [104] = PINGROUP(104, EAST, unused1, _, qua_mi2s, _, _, _, _, _, _), + [105] = PINGROUP(105, EAST, mss_lte, _, _, _, _, _, _, _, _), + [106] = PINGROUP(106, EAST, swr_tx, aud_sb, qua_mi2s, _, qdss_cti, _, _, _, _), + [107] = PINGROUP(107, EAST, swr_tx, aud_sb, qua_mi2s, _, qdss_cti, _, _, _, _), + [108] = PINGROUP(108, EAST, swr_tx, aud_sb, qua_mi2s, _, _, _, _, _, _), + [109] = PINGROUP(109, EAST, swr_tx, aud_sb, unused2, _, mss_lte, _, _, _, _), + [110] = PINGROUP(110, EAST, swr_rx, qua_mi2s, _, qdss_cti, _, _, _, _, _), + [111] = PINGROUP(111, EAST, swr_rx, qua_mi2s, edp_hot, _, qdss_cti, _, _, _, _), + [112] = PINGROUP(112, EAST, swr_rx, audio_ref, _, _, _, _, _, _, _), + [113] = PINGROUP(113, EAST, pri_mi2s, _, _, _, _, _, _, _, _), + [114] = PINGROUP(114, EAST, pri_mi2s_ws, qdss, _, _, _, _, _, _, _), + [115] = PINGROUP(115, EAST, pri_mi2s, qdss, _, _, _, _, _, _, _), + [116] = PINGROUP(116, EAST, pri_mi2s, adsp_ext, qdss, _, _, _, _, _, _), + [117] = PINGROUP(117, SOUTH, edp_lcd, qdss, _, _, _, _, _, _, _), + [118] = PINGROUP(118, SOUTH, mclk2, m_voc, qdss, _, _, _, _, _, _), + [119] = PINGROUP(119, SOUTH, mclk1, _, _, _, _, _, _, _, _), + [120] = PINGROUP(120, SOUTH, _, _, _, _, _, _, _, _, _), + [121] = PINGROUP(121, EAST, qca_sb, qui_mi2s, _, _, _, _, _, _, _), + [122] = PINGROUP(122, EAST, qca_sb, qui_mi2s, _, _, _, _, _, _, _), + [123] = PINGROUP(123, EAST, qui_mi2s, _, _, _, _, _, _, _, _), + [124] = PINGROUP(124, EAST, qui_mi2s, _, _, _, _, _, _, _, _), + [125] = PINGROUP(125, EAST, dmic0_clk, sec_mi2s, _, _, _, _, _, _, _), + [126] = PINGROUP(126, EAST, dmic0_data, sec_mi2s, _, _, _, _, _, _, _), + [127] = PINGROUP(127, EAST, dmic1_clk, sec_mi2s, _, _, _, _, _, _, _), + [128] = PINGROUP(128, EAST, dmic1_data, sec_mi2s, _, _, _, _, _, _, _), + [129] = PINGROUP(129, SOUTH, _, phase_flag, _, _, _, _, _, _, _), + [130] = PINGROUP(130, SOUTH, phase_flag, _, _, _, _, _, _, _, _), + [131] = PINGROUP(131, SOUTH, phase_flag, _, _, _, _, _, _, _, _), + [132] = PINGROUP(132, SOUTH, _, _, _, _, _, _, _, _, _), + [133] = UFS_RESET(ufs_reset, 0x190000), + [134] = SDC_QDSD_PINGROUP(sdc1_rclk, WEST, 0x18d000, 15, 0), + [135] = SDC_QDSD_PINGROUP(sdc1_clk, WEST, 0x18d000, 13, 6), + [136] = SDC_QDSD_PINGROUP(sdc1_cmd, WEST, 0x18d000, 11, 3), + [137] = SDC_QDSD_PINGROUP(sdc1_data, WEST, 0x18d000, 9, 0), + [138] = SDC_QDSD_PINGROUP(sdc2_clk, SOUTH, 0x58b000, 14, 6), + [139] = SDC_QDSD_PINGROUP(sdc2_cmd, SOUTH, 0x58b000, 11, 3), + [140] = SDC_QDSD_PINGROUP(sdc2_data, SOUTH, 0x58b000, 9, 0), +}; + +static const struct msm_pinctrl_soc_data sm6125_tlmm = { + .pins = sm6125_pins, + .npins = ARRAY_SIZE(sm6125_pins), + .functions = sm6125_functions, + .nfunctions = ARRAY_SIZE(sm6125_functions), + .groups = sm6125_groups, + .ngroups = ARRAY_SIZE(sm6125_groups), + .ngpios = 134, + .tiles = sm6125_tiles, + .ntiles = ARRAY_SIZE(sm6125_tiles), +}; + +static int sm6125_tlmm_probe(struct platform_device *pdev) +{ + return msm_pinctrl_probe(pdev, &sm6125_tlmm); +} + +static const struct of_device_id sm6125_tlmm_of_match[] = { + { .compatible = "qcom,sm6125-tlmm", }, + { }, +}; + +static struct platform_driver sm6125_tlmm_driver = { + .driver = { + .name = "sm6125-tlmm", + .of_match_table = sm6125_tlmm_of_match, + }, + .probe = sm6125_tlmm_probe, + .remove = msm_pinctrl_remove, +}; + +static int __init sm6125_tlmm_init(void) +{ + return platform_driver_register(&sm6125_tlmm_driver); +} +arch_initcall(sm6125_tlmm_init); + +static void __exit sm6125_tlmm_exit(void) +{ + platform_driver_unregister(&sm6125_tlmm_driver); +} +module_exit(sm6125_tlmm_exit); + +MODULE_DESCRIPTION("QTI sm6125 TLMM driver"); +MODULE_LICENSE("GPL v2"); +MODULE_DEVICE_TABLE(of, sm6125_tlmm_of_match); diff --git a/drivers/pinctrl/qcom/pinctrl-sm6350.c b/drivers/pinctrl/qcom/pinctrl-sm6350.c new file mode 100644 index 0000000000..f3828c07b1 --- /dev/null +++ b/drivers/pinctrl/qcom/pinctrl-sm6350.c @@ -0,0 +1,1393 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2021, The Linux Foundation. All rights reserved. + * Copyright (c) 2021, Konrad Dybcio <konrad.dybcio@somainline.org> + */ + +#include <linux/module.h> +#include <linux/of.h> +#include <linux/platform_device.h> + +#include "pinctrl-msm.h" + +#define REG_SIZE 0x1000 +#define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7, f8, f9) \ + { \ + .grp = PINCTRL_PINGROUP("gpio" #id, \ + gpio##id##_pins, \ + ARRAY_SIZE(gpio##id##_pins)), \ + .funcs = (int[]){ \ + msm_mux_gpio, /* gpio mode */ \ + msm_mux_##f1, \ + msm_mux_##f2, \ + msm_mux_##f3, \ + msm_mux_##f4, \ + msm_mux_##f5, \ + msm_mux_##f6, \ + msm_mux_##f7, \ + msm_mux_##f8, \ + msm_mux_##f9 \ + }, \ + .nfuncs = 10, \ + .ctl_reg = REG_SIZE * id, \ + .io_reg = 0x4 + REG_SIZE * id, \ + .intr_cfg_reg = 0x8 + REG_SIZE * id, \ + .intr_status_reg = 0xc + REG_SIZE * id, \ + .intr_target_reg = 0x8 + REG_SIZE * id, \ + .mux_bit = 2, \ + .pull_bit = 0, \ + .drv_bit = 6, \ + .oe_bit = 9, \ + .in_bit = 0, \ + .out_bit = 1, \ + .intr_enable_bit = 0, \ + .intr_status_bit = 0, \ + .intr_target_bit = 5, \ + .intr_target_kpss_val = 3, \ + .intr_raw_status_bit = 4, \ + .intr_polarity_bit = 1, \ + .intr_detection_bit = 2, \ + .intr_detection_width = 2, \ + } + +#define SDC_PINGROUP(pg_name, ctl, pull, drv) \ + { \ + .grp = PINCTRL_PINGROUP(#pg_name, \ + pg_name##_pins, \ + ARRAY_SIZE(pg_name##_pins)), \ + .ctl_reg = ctl, \ + .io_reg = 0, \ + .intr_cfg_reg = 0, \ + .intr_status_reg = 0, \ + .intr_target_reg = 0, \ + .mux_bit = -1, \ + .pull_bit = pull, \ + .drv_bit = drv, \ + .oe_bit = -1, \ + .in_bit = -1, \ + .out_bit = -1, \ + .intr_enable_bit = -1, \ + .intr_status_bit = -1, \ + .intr_target_bit = -1, \ + .intr_raw_status_bit = -1, \ + .intr_polarity_bit = -1, \ + .intr_detection_bit = -1, \ + .intr_detection_width = -1, \ + } + +#define UFS_RESET(pg_name, offset) \ + { \ + .grp = PINCTRL_PINGROUP(#pg_name, \ + pg_name##_pins, \ + ARRAY_SIZE(pg_name##_pins)), \ + .ctl_reg = offset, \ + .io_reg = offset + 0x4, \ + .intr_cfg_reg = 0, \ + .intr_status_reg = 0, \ + .intr_target_reg = 0, \ + .mux_bit = -1, \ + .pull_bit = 3, \ + .drv_bit = 0, \ + .oe_bit = -1, \ + .in_bit = -1, \ + .out_bit = 0, \ + .intr_enable_bit = -1, \ + .intr_status_bit = -1, \ + .intr_target_bit = -1, \ + .intr_raw_status_bit = -1, \ + .intr_polarity_bit = -1, \ + .intr_detection_bit = -1, \ + .intr_detection_width = -1, \ + } +static const struct pinctrl_pin_desc sm6350_pins[] = { + PINCTRL_PIN(0, "GPIO_0"), + PINCTRL_PIN(1, "GPIO_1"), + PINCTRL_PIN(2, "GPIO_2"), + PINCTRL_PIN(3, "GPIO_3"), + PINCTRL_PIN(4, "GPIO_4"), + PINCTRL_PIN(5, "GPIO_5"), + PINCTRL_PIN(6, "GPIO_6"), + PINCTRL_PIN(7, "GPIO_7"), + PINCTRL_PIN(8, "GPIO_8"), + PINCTRL_PIN(9, "GPIO_9"), + PINCTRL_PIN(10, "GPIO_10"), + PINCTRL_PIN(11, "GPIO_11"), + PINCTRL_PIN(12, "GPIO_12"), + PINCTRL_PIN(13, "GPIO_13"), + PINCTRL_PIN(14, "GPIO_14"), + PINCTRL_PIN(15, "GPIO_15"), + PINCTRL_PIN(16, "GPIO_16"), + PINCTRL_PIN(17, "GPIO_17"), + PINCTRL_PIN(18, "GPIO_18"), + PINCTRL_PIN(19, "GPIO_19"), + PINCTRL_PIN(20, "GPIO_20"), + PINCTRL_PIN(21, "GPIO_21"), + PINCTRL_PIN(22, "GPIO_22"), + PINCTRL_PIN(23, "GPIO_23"), + PINCTRL_PIN(24, "GPIO_24"), + PINCTRL_PIN(25, "GPIO_25"), + PINCTRL_PIN(26, "GPIO_26"), + PINCTRL_PIN(27, "GPIO_27"), + PINCTRL_PIN(28, "GPIO_28"), + PINCTRL_PIN(29, "GPIO_29"), + PINCTRL_PIN(30, "GPIO_30"), + PINCTRL_PIN(31, "GPIO_31"), + PINCTRL_PIN(32, "GPIO_32"), + PINCTRL_PIN(33, "GPIO_33"), + PINCTRL_PIN(34, "GPIO_34"), + PINCTRL_PIN(35, "GPIO_35"), + PINCTRL_PIN(36, "GPIO_36"), + PINCTRL_PIN(37, "GPIO_37"), + PINCTRL_PIN(38, "GPIO_38"), + PINCTRL_PIN(39, "GPIO_39"), + PINCTRL_PIN(40, "GPIO_40"), + PINCTRL_PIN(41, "GPIO_41"), + PINCTRL_PIN(42, "GPIO_42"), + PINCTRL_PIN(43, "GPIO_43"), + PINCTRL_PIN(44, "GPIO_44"), + PINCTRL_PIN(45, "GPIO_45"), + PINCTRL_PIN(46, "GPIO_46"), + PINCTRL_PIN(47, "GPIO_47"), + PINCTRL_PIN(48, "GPIO_48"), + PINCTRL_PIN(49, "GPIO_49"), + PINCTRL_PIN(50, "GPIO_50"), + PINCTRL_PIN(51, "GPIO_51"), + PINCTRL_PIN(52, "GPIO_52"), + PINCTRL_PIN(53, "GPIO_53"), + PINCTRL_PIN(54, "GPIO_54"), + PINCTRL_PIN(55, "GPIO_55"), + PINCTRL_PIN(56, "GPIO_56"), + PINCTRL_PIN(57, "GPIO_57"), + PINCTRL_PIN(58, "GPIO_58"), + PINCTRL_PIN(59, "GPIO_59"), + PINCTRL_PIN(60, "GPIO_60"), + PINCTRL_PIN(61, "GPIO_61"), + PINCTRL_PIN(62, "GPIO_62"), + PINCTRL_PIN(63, "GPIO_63"), + PINCTRL_PIN(64, "GPIO_64"), + PINCTRL_PIN(65, "GPIO_65"), + PINCTRL_PIN(66, "GPIO_66"), + PINCTRL_PIN(67, "GPIO_67"), + PINCTRL_PIN(68, "GPIO_68"), + PINCTRL_PIN(69, "GPIO_69"), + PINCTRL_PIN(70, "GPIO_70"), + PINCTRL_PIN(71, "GPIO_71"), + PINCTRL_PIN(72, "GPIO_72"), + PINCTRL_PIN(73, "GPIO_73"), + PINCTRL_PIN(74, "GPIO_74"), + PINCTRL_PIN(75, "GPIO_75"), + PINCTRL_PIN(76, "GPIO_76"), + PINCTRL_PIN(77, "GPIO_77"), + PINCTRL_PIN(78, "GPIO_78"), + PINCTRL_PIN(79, "GPIO_79"), + PINCTRL_PIN(80, "GPIO_80"), + PINCTRL_PIN(81, "GPIO_81"), + PINCTRL_PIN(82, "GPIO_82"), + PINCTRL_PIN(83, "GPIO_83"), + PINCTRL_PIN(84, "GPIO_84"), + PINCTRL_PIN(85, "GPIO_85"), + PINCTRL_PIN(86, "GPIO_86"), + PINCTRL_PIN(87, "GPIO_87"), + PINCTRL_PIN(88, "GPIO_88"), + PINCTRL_PIN(89, "GPIO_89"), + PINCTRL_PIN(90, "GPIO_90"), + PINCTRL_PIN(91, "GPIO_91"), + PINCTRL_PIN(92, "GPIO_92"), + PINCTRL_PIN(93, "GPIO_93"), + PINCTRL_PIN(94, "GPIO_94"), + PINCTRL_PIN(95, "GPIO_95"), + PINCTRL_PIN(96, "GPIO_96"), + PINCTRL_PIN(97, "GPIO_97"), + PINCTRL_PIN(98, "GPIO_98"), + PINCTRL_PIN(99, "GPIO_99"), + PINCTRL_PIN(100, "GPIO_100"), + PINCTRL_PIN(101, "GPIO_101"), + PINCTRL_PIN(102, "GPIO_102"), + PINCTRL_PIN(103, "GPIO_103"), + PINCTRL_PIN(104, "GPIO_104"), + PINCTRL_PIN(105, "GPIO_105"), + PINCTRL_PIN(106, "GPIO_106"), + PINCTRL_PIN(107, "GPIO_107"), + PINCTRL_PIN(108, "GPIO_108"), + PINCTRL_PIN(109, "GPIO_109"), + PINCTRL_PIN(110, "GPIO_110"), + PINCTRL_PIN(111, "GPIO_111"), + PINCTRL_PIN(112, "GPIO_112"), + PINCTRL_PIN(113, "GPIO_113"), + PINCTRL_PIN(114, "GPIO_114"), + PINCTRL_PIN(115, "GPIO_115"), + PINCTRL_PIN(116, "GPIO_116"), + PINCTRL_PIN(117, "GPIO_117"), + PINCTRL_PIN(118, "GPIO_118"), + PINCTRL_PIN(119, "GPIO_119"), + PINCTRL_PIN(120, "GPIO_120"), + PINCTRL_PIN(121, "GPIO_121"), + PINCTRL_PIN(122, "GPIO_122"), + PINCTRL_PIN(123, "GPIO_123"), + PINCTRL_PIN(124, "GPIO_124"), + PINCTRL_PIN(125, "GPIO_125"), + PINCTRL_PIN(126, "GPIO_126"), + PINCTRL_PIN(127, "GPIO_127"), + PINCTRL_PIN(128, "GPIO_128"), + PINCTRL_PIN(129, "GPIO_129"), + PINCTRL_PIN(130, "GPIO_130"), + PINCTRL_PIN(131, "GPIO_131"), + PINCTRL_PIN(132, "GPIO_132"), + PINCTRL_PIN(133, "GPIO_133"), + PINCTRL_PIN(134, "GPIO_134"), + PINCTRL_PIN(135, "GPIO_135"), + PINCTRL_PIN(136, "GPIO_136"), + PINCTRL_PIN(137, "GPIO_137"), + PINCTRL_PIN(138, "GPIO_138"), + PINCTRL_PIN(139, "GPIO_139"), + PINCTRL_PIN(140, "GPIO_140"), + PINCTRL_PIN(141, "GPIO_141"), + PINCTRL_PIN(142, "GPIO_142"), + PINCTRL_PIN(143, "GPIO_143"), + PINCTRL_PIN(144, "GPIO_144"), + PINCTRL_PIN(145, "GPIO_145"), + PINCTRL_PIN(146, "GPIO_146"), + PINCTRL_PIN(147, "GPIO_147"), + PINCTRL_PIN(148, "GPIO_148"), + PINCTRL_PIN(149, "GPIO_149"), + PINCTRL_PIN(150, "GPIO_150"), + PINCTRL_PIN(151, "GPIO_151"), + PINCTRL_PIN(152, "GPIO_152"), + PINCTRL_PIN(153, "GPIO_153"), + PINCTRL_PIN(154, "GPIO_154"), + PINCTRL_PIN(155, "GPIO_155"), + PINCTRL_PIN(156, "UFS_RESET"), + PINCTRL_PIN(157, "SDC1_RCLK"), + PINCTRL_PIN(158, "SDC1_CLK"), + PINCTRL_PIN(159, "SDC1_CMD"), + PINCTRL_PIN(160, "SDC1_DATA"), + PINCTRL_PIN(161, "SDC2_CLK"), + PINCTRL_PIN(162, "SDC2_CMD"), + PINCTRL_PIN(163, "SDC2_DATA"), +}; + +#define DECLARE_MSM_GPIO_PINS(pin) \ + static const unsigned int gpio##pin##_pins[] = { pin } +DECLARE_MSM_GPIO_PINS(0); +DECLARE_MSM_GPIO_PINS(1); +DECLARE_MSM_GPIO_PINS(2); +DECLARE_MSM_GPIO_PINS(3); +DECLARE_MSM_GPIO_PINS(4); +DECLARE_MSM_GPIO_PINS(5); +DECLARE_MSM_GPIO_PINS(6); +DECLARE_MSM_GPIO_PINS(7); +DECLARE_MSM_GPIO_PINS(8); +DECLARE_MSM_GPIO_PINS(9); +DECLARE_MSM_GPIO_PINS(10); +DECLARE_MSM_GPIO_PINS(11); +DECLARE_MSM_GPIO_PINS(12); +DECLARE_MSM_GPIO_PINS(13); +DECLARE_MSM_GPIO_PINS(14); +DECLARE_MSM_GPIO_PINS(15); +DECLARE_MSM_GPIO_PINS(16); +DECLARE_MSM_GPIO_PINS(17); +DECLARE_MSM_GPIO_PINS(18); +DECLARE_MSM_GPIO_PINS(19); +DECLARE_MSM_GPIO_PINS(20); +DECLARE_MSM_GPIO_PINS(21); +DECLARE_MSM_GPIO_PINS(22); +DECLARE_MSM_GPIO_PINS(23); +DECLARE_MSM_GPIO_PINS(24); +DECLARE_MSM_GPIO_PINS(25); +DECLARE_MSM_GPIO_PINS(26); +DECLARE_MSM_GPIO_PINS(27); +DECLARE_MSM_GPIO_PINS(28); +DECLARE_MSM_GPIO_PINS(29); +DECLARE_MSM_GPIO_PINS(30); +DECLARE_MSM_GPIO_PINS(31); +DECLARE_MSM_GPIO_PINS(32); +DECLARE_MSM_GPIO_PINS(33); +DECLARE_MSM_GPIO_PINS(34); +DECLARE_MSM_GPIO_PINS(35); +DECLARE_MSM_GPIO_PINS(36); +DECLARE_MSM_GPIO_PINS(37); +DECLARE_MSM_GPIO_PINS(38); +DECLARE_MSM_GPIO_PINS(39); +DECLARE_MSM_GPIO_PINS(40); +DECLARE_MSM_GPIO_PINS(41); +DECLARE_MSM_GPIO_PINS(42); +DECLARE_MSM_GPIO_PINS(43); +DECLARE_MSM_GPIO_PINS(44); +DECLARE_MSM_GPIO_PINS(45); +DECLARE_MSM_GPIO_PINS(46); +DECLARE_MSM_GPIO_PINS(47); +DECLARE_MSM_GPIO_PINS(48); +DECLARE_MSM_GPIO_PINS(49); +DECLARE_MSM_GPIO_PINS(50); +DECLARE_MSM_GPIO_PINS(51); +DECLARE_MSM_GPIO_PINS(52); +DECLARE_MSM_GPIO_PINS(53); +DECLARE_MSM_GPIO_PINS(54); +DECLARE_MSM_GPIO_PINS(55); +DECLARE_MSM_GPIO_PINS(56); +DECLARE_MSM_GPIO_PINS(57); +DECLARE_MSM_GPIO_PINS(58); +DECLARE_MSM_GPIO_PINS(59); +DECLARE_MSM_GPIO_PINS(60); +DECLARE_MSM_GPIO_PINS(61); +DECLARE_MSM_GPIO_PINS(62); +DECLARE_MSM_GPIO_PINS(63); +DECLARE_MSM_GPIO_PINS(64); +DECLARE_MSM_GPIO_PINS(65); +DECLARE_MSM_GPIO_PINS(66); +DECLARE_MSM_GPIO_PINS(67); +DECLARE_MSM_GPIO_PINS(68); +DECLARE_MSM_GPIO_PINS(69); +DECLARE_MSM_GPIO_PINS(70); +DECLARE_MSM_GPIO_PINS(71); +DECLARE_MSM_GPIO_PINS(72); +DECLARE_MSM_GPIO_PINS(73); +DECLARE_MSM_GPIO_PINS(74); +DECLARE_MSM_GPIO_PINS(75); +DECLARE_MSM_GPIO_PINS(76); +DECLARE_MSM_GPIO_PINS(77); +DECLARE_MSM_GPIO_PINS(78); +DECLARE_MSM_GPIO_PINS(79); +DECLARE_MSM_GPIO_PINS(80); +DECLARE_MSM_GPIO_PINS(81); +DECLARE_MSM_GPIO_PINS(82); +DECLARE_MSM_GPIO_PINS(83); +DECLARE_MSM_GPIO_PINS(84); +DECLARE_MSM_GPIO_PINS(85); +DECLARE_MSM_GPIO_PINS(86); +DECLARE_MSM_GPIO_PINS(87); +DECLARE_MSM_GPIO_PINS(88); +DECLARE_MSM_GPIO_PINS(89); +DECLARE_MSM_GPIO_PINS(90); +DECLARE_MSM_GPIO_PINS(91); +DECLARE_MSM_GPIO_PINS(92); +DECLARE_MSM_GPIO_PINS(93); +DECLARE_MSM_GPIO_PINS(94); +DECLARE_MSM_GPIO_PINS(95); +DECLARE_MSM_GPIO_PINS(96); +DECLARE_MSM_GPIO_PINS(97); +DECLARE_MSM_GPIO_PINS(98); +DECLARE_MSM_GPIO_PINS(99); +DECLARE_MSM_GPIO_PINS(100); +DECLARE_MSM_GPIO_PINS(101); +DECLARE_MSM_GPIO_PINS(102); +DECLARE_MSM_GPIO_PINS(103); +DECLARE_MSM_GPIO_PINS(104); +DECLARE_MSM_GPIO_PINS(105); +DECLARE_MSM_GPIO_PINS(106); +DECLARE_MSM_GPIO_PINS(107); +DECLARE_MSM_GPIO_PINS(108); +DECLARE_MSM_GPIO_PINS(109); +DECLARE_MSM_GPIO_PINS(110); +DECLARE_MSM_GPIO_PINS(111); +DECLARE_MSM_GPIO_PINS(112); +DECLARE_MSM_GPIO_PINS(113); +DECLARE_MSM_GPIO_PINS(114); +DECLARE_MSM_GPIO_PINS(115); +DECLARE_MSM_GPIO_PINS(116); +DECLARE_MSM_GPIO_PINS(117); +DECLARE_MSM_GPIO_PINS(118); +DECLARE_MSM_GPIO_PINS(119); +DECLARE_MSM_GPIO_PINS(120); +DECLARE_MSM_GPIO_PINS(121); +DECLARE_MSM_GPIO_PINS(122); +DECLARE_MSM_GPIO_PINS(123); +DECLARE_MSM_GPIO_PINS(124); +DECLARE_MSM_GPIO_PINS(125); +DECLARE_MSM_GPIO_PINS(126); +DECLARE_MSM_GPIO_PINS(127); +DECLARE_MSM_GPIO_PINS(128); +DECLARE_MSM_GPIO_PINS(129); +DECLARE_MSM_GPIO_PINS(130); +DECLARE_MSM_GPIO_PINS(131); +DECLARE_MSM_GPIO_PINS(132); +DECLARE_MSM_GPIO_PINS(133); +DECLARE_MSM_GPIO_PINS(134); +DECLARE_MSM_GPIO_PINS(135); +DECLARE_MSM_GPIO_PINS(136); +DECLARE_MSM_GPIO_PINS(137); +DECLARE_MSM_GPIO_PINS(138); +DECLARE_MSM_GPIO_PINS(139); +DECLARE_MSM_GPIO_PINS(140); +DECLARE_MSM_GPIO_PINS(141); +DECLARE_MSM_GPIO_PINS(142); +DECLARE_MSM_GPIO_PINS(143); +DECLARE_MSM_GPIO_PINS(144); +DECLARE_MSM_GPIO_PINS(145); +DECLARE_MSM_GPIO_PINS(146); +DECLARE_MSM_GPIO_PINS(147); +DECLARE_MSM_GPIO_PINS(148); +DECLARE_MSM_GPIO_PINS(149); +DECLARE_MSM_GPIO_PINS(150); +DECLARE_MSM_GPIO_PINS(151); +DECLARE_MSM_GPIO_PINS(152); +DECLARE_MSM_GPIO_PINS(153); +DECLARE_MSM_GPIO_PINS(154); +DECLARE_MSM_GPIO_PINS(155); + +static const unsigned int ufs_reset_pins[] = { 156 }; +static const unsigned int sdc1_rclk_pins[] = { 157 }; +static const unsigned int sdc1_clk_pins[] = { 158 }; +static const unsigned int sdc1_cmd_pins[] = { 159 }; +static const unsigned int sdc1_data_pins[] = { 160 }; +static const unsigned int sdc2_clk_pins[] = { 161 }; +static const unsigned int sdc2_cmd_pins[] = { 162 }; +static const unsigned int sdc2_data_pins[] = { 163 }; + +enum sm6350_functions { + msm_mux_adsp_ext, + msm_mux_agera_pll, + msm_mux_atest_char, + msm_mux_atest_char0, + msm_mux_atest_char1, + msm_mux_atest_char2, + msm_mux_atest_char3, + msm_mux_atest_tsens, + msm_mux_atest_tsens2, + msm_mux_atest_usb, + msm_mux_audio_ref, + msm_mux_btfm_slimbus, + msm_mux_cam_mclk0, + msm_mux_cam_mclk1, + msm_mux_cam_mclk2, + msm_mux_cam_mclk3, + msm_mux_cam_mclk4, + msm_mux_cci_async, + msm_mux_cci_i2c, + msm_mux_cci_timer0, + msm_mux_cci_timer1, + msm_mux_cci_timer2, + msm_mux_cci_timer3, + msm_mux_cci_timer4, + msm_mux_cri_trng, + msm_mux_dbg_out, + msm_mux_ddr_bist, + msm_mux_ddr_pxi0, + msm_mux_ddr_pxi1, + msm_mux_ddr_pxi2, + msm_mux_ddr_pxi3, + msm_mux_dp_hot, + msm_mux_edp_lcd, + msm_mux_gcc_gp1, + msm_mux_gcc_gp2, + msm_mux_gcc_gp3, + msm_mux_gp_pdm0, + msm_mux_gp_pdm1, + msm_mux_gp_pdm2, + msm_mux_gpio, + msm_mux_gps_tx, + msm_mux_ibi_i3c, + msm_mux_jitter_bist, + msm_mux_ldo_en, + msm_mux_ldo_update, + msm_mux_lpass_ext, + msm_mux_m_voc, + msm_mux_mclk, + msm_mux_mdp_vsync, + msm_mux_mdp_vsync0, + msm_mux_mdp_vsync1, + msm_mux_mdp_vsync2, + msm_mux_mdp_vsync3, + msm_mux_mi2s_0, + msm_mux_mi2s_1, + msm_mux_mi2s_2, + msm_mux_mss_lte, + msm_mux_nav_gpio, + msm_mux_nav_pps, + msm_mux_pa_indicator, + msm_mux_pcie0_clk, + msm_mux_phase_flag, + msm_mux_pll_bist, + msm_mux_pll_bypassnl, + msm_mux_pll_reset, + msm_mux_prng_rosc, + msm_mux_qdss_cti, + msm_mux_qdss_gpio, + msm_mux_qdss_gpio0, + msm_mux_qdss_gpio1, + msm_mux_qdss_gpio10, + msm_mux_qdss_gpio11, + msm_mux_qdss_gpio12, + msm_mux_qdss_gpio13, + msm_mux_qdss_gpio14, + msm_mux_qdss_gpio15, + msm_mux_qdss_gpio2, + msm_mux_qdss_gpio3, + msm_mux_qdss_gpio4, + msm_mux_qdss_gpio5, + msm_mux_qdss_gpio6, + msm_mux_qdss_gpio7, + msm_mux_qdss_gpio8, + msm_mux_qdss_gpio9, + msm_mux_qlink0_enable, + msm_mux_qlink0_request, + msm_mux_qlink0_wmss, + msm_mux_qlink1_enable, + msm_mux_qlink1_request, + msm_mux_qlink1_wmss, + msm_mux_qup00, + msm_mux_qup01, + msm_mux_qup02, + msm_mux_qup10, + msm_mux_qup11, + msm_mux_qup12, + msm_mux_qup13_f1, + msm_mux_qup13_f2, + msm_mux_qup14, + msm_mux_rffe0_clk, + msm_mux_rffe0_data, + msm_mux_rffe1_clk, + msm_mux_rffe1_data, + msm_mux_rffe2_clk, + msm_mux_rffe2_data, + msm_mux_rffe3_clk, + msm_mux_rffe3_data, + msm_mux_rffe4_clk, + msm_mux_rffe4_data, + msm_mux_sd_write, + msm_mux_sdc1_tb, + msm_mux_sdc2_tb, + msm_mux_sp_cmu, + msm_mux_tgu_ch0, + msm_mux_tgu_ch1, + msm_mux_tgu_ch2, + msm_mux_tgu_ch3, + msm_mux_tsense_pwm1, + msm_mux_tsense_pwm2, + msm_mux_uim1_clk, + msm_mux_uim1_data, + msm_mux_uim1_present, + msm_mux_uim1_reset, + msm_mux_uim2_clk, + msm_mux_uim2_data, + msm_mux_uim2_present, + msm_mux_uim2_reset, + msm_mux_usb_phy, + msm_mux_vfr_1, + msm_mux_vsense_trigger, + msm_mux_wlan1_adc0, + msm_mux_wlan1_adc1, + msm_mux_wlan2_adc0, + msm_mux_wlan2_adc1, + msm_mux__, +}; + +static const char * const ibi_i3c_groups[] = { + "gpio0", "gpio1", +}; +static const char * const gpio_groups[] = { + "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7", + "gpio8", "gpio9", "gpio10", "gpio11", "gpio12", "gpio13", "gpio14", + "gpio15", "gpio16", "gpio17", "gpio18", "gpio19", "gpio20", "gpio21", + "gpio22", "gpio23", "gpio24", "gpio25", "gpio26", "gpio27", "gpio28", + "gpio29", "gpio30", "gpio31", "gpio32", "gpio33", "gpio34", "gpio35", + "gpio36", "gpio37", "gpio38", "gpio39", "gpio40", "gpio41", "gpio42", + "gpio43", "gpio44", "gpio45", "gpio46", "gpio47", "gpio48", "gpio49", + "gpio50", "gpio51", "gpio52", "gpio53", "gpio54", "gpio55", "gpio56", + "gpio57", "gpio58", "gpio59", "gpio60", "gpio61", "gpio62", "gpio63", + "gpio64", "gpio65", "gpio66", "gpio67", "gpio68", "gpio69", "gpio70", + "gpio71", "gpio72", "gpio73", "gpio74", "gpio75", "gpio76", "gpio77", + "gpio78", "gpio79", "gpio80", "gpio81", "gpio82", "gpio83", "gpio84", + "gpio85", "gpio86", "gpio87", "gpio88", "gpio89", "gpio90", "gpio91", + "gpio92", "gpio93", "gpio94", "gpio95", "gpio96", "gpio97", "gpio98", + "gpio99", "gpio100", "gpio101", "gpio102", "gpio103", "gpio104", + "gpio105", "gpio106", "gpio107", "gpio108", "gpio109", "gpio110", + "gpio111", "gpio112", "gpio113", "gpio114", "gpio115", "gpio116", + "gpio117", "gpio118", "gpio119", "gpio120", "gpio121", "gpio122", + "gpio123", "gpio124", "gpio125", "gpio126", "gpio127", "gpio128", + "gpio129", "gpio130", "gpio131", "gpio132", "gpio133", "gpio134", + "gpio135", "gpio136", "gpio137", "gpio138", "gpio139", "gpio140", + "gpio141", "gpio142", "gpio143", "gpio144", "gpio145", "gpio146", + "gpio147", "gpio148", "gpio149", "gpio150", "gpio151", "gpio152", + "gpio153", "gpio154", "gpio155", +}; +static const char * const cri_trng_groups[] = { + "gpio0", "gpio1", "gpio2", +}; +static const char * const qup00_groups[] = { + "gpio0", "gpio1", "gpio2", "gpio3", +}; +static const char * const cci_i2c_groups[] = { + "gpio2", "gpio3", "gpio39", "gpio40", "gpio41", "gpio42", "gpio43", + "gpio44", +}; +static const char * const qdss_cti_groups[] = { + "gpio2", "gpio3", "gpio6", "gpio7", "gpio61", "gpio62", "gpio86", + "gpio87", +}; +static const char * const sp_cmu_groups[] = { + "gpio3", +}; +static const char * const dbg_out_groups[] = { + "gpio3", +}; +static const char * const qup14_groups[] = { + "gpio4", "gpio4", "gpio5", "gpio5", +}; +static const char * const sdc1_tb_groups[] = { + "gpio4", +}; +static const char * const sdc2_tb_groups[] = { + "gpio5", +}; +static const char * const mdp_vsync_groups[] = { + "gpio6", "gpio23", "gpio24", "gpio27", "gpio28", +}; +static const char * const gp_pdm1_groups[] = { + "gpio8", "gpio52", +}; +static const char * const qdss_gpio_groups[] = { + "gpio8", "gpio9", "gpio63", "gpio64", +}; +static const char * const m_voc_groups[] = { + "gpio12", +}; +static const char * const dp_hot_groups[] = { + "gpio12", "gpio118", +}; +static const char * const phase_flag_groups[] = { + "gpio12", "gpio17", "gpio18", "gpio34", "gpio35", + "gpio36", "gpio37", "gpio38", "gpio39", "gpio40", + "gpio41", "gpio42", "gpio43", "gpio44", "gpio45", + "gpio46", "gpio47", "gpio48", "gpio49", "gpio50", + "gpio51", "gpio52", "gpio53", "gpio56", "gpio57", + "gpio60", "gpio61", "gpio62", "gpio63", "gpio64", + "gpio67", "gpio68", +}; +static const char * const qup10_groups[] = { + "gpio13", "gpio14", "gpio15", "gpio16", "gpio17", +}; +static const char * const pll_bypassnl_groups[] = { + "gpio13", +}; +static const char * const pll_reset_groups[] = { + "gpio14", +}; +static const char * const qup12_groups[] = { + "gpio19", "gpio19", "gpio20", "gpio20", +}; +static const char * const ddr_bist_groups[] = { + "gpio19", "gpio20", "gpio21", "gpio22", +}; +static const char * const gcc_gp2_groups[] = { + "gpio21", +}; +static const char * const gcc_gp3_groups[] = { + "gpio22", +}; +static const char * const edp_lcd_groups[] = { + "gpio23", +}; +static const char * const qup13_f1_groups[] = { + "gpio25", "gpio26", +}; +static const char * const qup13_f2_groups[] = { + "gpio25", "gpio26", +}; +static const char * const qup11_groups[] = { + "gpio27", "gpio27", "gpio28", "gpio28", +}; +static const char * const pll_bist_groups[] = { + "gpio27", +}; +static const char * const qdss_gpio14_groups[] = { + "gpio27", "gpio36", +}; +static const char * const qdss_gpio15_groups[] = { + "gpio28", "gpio37", +}; +static const char * const cam_mclk0_groups[] = { + "gpio29", +}; +static const char * const cam_mclk1_groups[] = { + "gpio30", +}; +static const char * const cam_mclk2_groups[] = { + "gpio31", +}; +static const char * const cam_mclk3_groups[] = { + "gpio32", +}; +static const char * const cam_mclk4_groups[] = { + "gpio33", +}; +static const char * const cci_timer0_groups[] = { + "gpio34", +}; +static const char * const qdss_gpio12_groups[] = { + "gpio34", "gpio52", +}; +static const char * const cci_timer1_groups[] = { + "gpio35", +}; +static const char * const cci_async_groups[] = { + "gpio35", "gpio36", "gpio48", "gpio52", "gpio53", +}; +static const char * const qdss_gpio13_groups[] = { + "gpio35", "gpio53", +}; +static const char * const cci_timer2_groups[] = { + "gpio36", +}; +static const char * const cci_timer3_groups[] = { + "gpio37", +}; +static const char * const gp_pdm0_groups[] = { + "gpio37", "gpio68", +}; +static const char * const cci_timer4_groups[] = { + "gpio38", +}; +static const char * const qdss_gpio2_groups[] = { + "gpio38", "gpio41", +}; +static const char * const qdss_gpio0_groups[] = { + "gpio39", "gpio65", +}; +static const char * const qdss_gpio1_groups[] = { + "gpio40", "gpio66", +}; +static const char * const qdss_gpio3_groups[] = { + "gpio42", "gpio47", +}; +static const char * const qdss_gpio4_groups[] = { + "gpio43", "gpio88", +}; +static const char * const qdss_gpio5_groups[] = { + "gpio44", "gpio89", +}; +static const char * const qup02_groups[] = { + "gpio45", "gpio46", "gpio48", "gpio56", "gpio57", +}; +static const char * const qdss_gpio6_groups[] = { + "gpio45", "gpio90", +}; +static const char * const qdss_gpio7_groups[] = { + "gpio46", "gpio91", +}; +static const char * const mdp_vsync0_groups[] = { + "gpio47", +}; +static const char * const mdp_vsync1_groups[] = { + "gpio48", +}; +static const char * const gcc_gp1_groups[] = { + "gpio48", "gpio58", +}; +static const char * const qdss_gpio8_groups[] = { + "gpio48", "gpio92", +}; +static const char * const vfr_1_groups[] = { + "gpio49", +}; +static const char * const qdss_gpio9_groups[] = { + "gpio49", "gpio93", +}; +static const char * const qdss_gpio10_groups[] = { + "gpio50", "gpio56", +}; +static const char * const qdss_gpio11_groups[] = { + "gpio51", "gpio57", +}; +static const char * const mdp_vsync2_groups[] = { + "gpio56", +}; +static const char * const mdp_vsync3_groups[] = { + "gpio57", +}; +static const char * const gp_pdm2_groups[] = { + "gpio57", +}; +static const char * const audio_ref_groups[] = { + "gpio60", +}; +static const char * const lpass_ext_groups[] = { + "gpio60", "gpio93", +}; +static const char * const mi2s_2_groups[] = { + "gpio60", "gpio72", "gpio73", "gpio74", +}; +static const char * const qup01_groups[] = { + "gpio61", "gpio62", "gpio63", "gpio64", +}; +static const char * const tgu_ch0_groups[] = { + "gpio61", +}; +static const char * const tgu_ch1_groups[] = { + "gpio62", +}; +static const char * const tgu_ch2_groups[] = { + "gpio63", +}; +static const char * const tgu_ch3_groups[] = { + "gpio64", +}; +static const char * const mss_lte_groups[] = { + "gpio65", "gpio66", +}; +static const char * const btfm_slimbus_groups[] = { + "gpio67", "gpio68", "gpio86", "gpio87", +}; +static const char * const mi2s_1_groups[] = { + "gpio67", "gpio68", "gpio86", "gpio87", +}; +static const char * const uim2_data_groups[] = { + "gpio75", +}; +static const char * const uim2_clk_groups[] = { + "gpio76", +}; +static const char * const uim2_reset_groups[] = { + "gpio77", +}; +static const char * const uim2_present_groups[] = { + "gpio78", +}; +static const char * const uim1_data_groups[] = { + "gpio79", +}; +static const char * const uim1_clk_groups[] = { + "gpio80", +}; +static const char * const uim1_reset_groups[] = { + "gpio81", +}; +static const char * const uim1_present_groups[] = { + "gpio82", +}; +static const char * const atest_usb_groups[] = { + "gpio83", "gpio84", "gpio85", "gpio86", + "gpio87", "gpio88", "gpio89", "gpio90", + "gpio91", "gpio92", +}; +static const char * const sd_write_groups[] = { + "gpio85", +}; +static const char * const ddr_pxi0_groups[] = { + "gpio86", "gpio90", +}; +static const char * const adsp_ext_groups[] = { + "gpio87", +}; +static const char * const ddr_pxi1_groups[] = { + "gpio87", "gpio91", +}; +static const char * const mi2s_0_groups[] = { + "gpio88", "gpio89", "gpio90", "gpio91", +}; +static const char * const ddr_pxi2_groups[] = { + "gpio88", "gpio92", +}; +static const char * const tsense_pwm1_groups[] = { + "gpio88", +}; +static const char * const tsense_pwm2_groups[] = { + "gpio88", +}; +static const char * const agera_pll_groups[] = { + "gpio89", +}; +static const char * const vsense_trigger_groups[] = { + "gpio89", +}; +static const char * const ddr_pxi3_groups[] = { + "gpio89", "gpio93", +}; +static const char * const jitter_bist_groups[] = { + "gpio90", +}; +static const char * const wlan1_adc0_groups[] = { + "gpio90", +}; +static const char * const wlan2_adc0_groups[] = { + "gpio91", +}; +static const char * const atest_tsens_groups[] = { + "gpio92", +}; +static const char * const wlan1_adc1_groups[] = { + "gpio92", +}; +static const char * const mclk_groups[] = { + "gpio93", +}; +static const char * const atest_tsens2_groups[] = { + "gpio93", +}; +static const char * const wlan2_adc1_groups[] = { + "gpio93", +}; +static const char * const ldo_en_groups[] = { + "gpio95", +}; +static const char * const atest_char_groups[] = { + "gpio95", +}; +static const char * const ldo_update_groups[] = { + "gpio96", +}; +static const char * const atest_char0_groups[] = { + "gpio96", +}; +static const char * const prng_rosc_groups[] = { + "gpio97", +}; +static const char * const atest_char1_groups[] = { + "gpio97", +}; +static const char * const atest_char2_groups[] = { + "gpio98", +}; +static const char * const atest_char3_groups[] = { + "gpio99", +}; +static const char * const nav_gpio_groups[] = { + "gpio101", "gpio102", +}; +static const char * const nav_pps_groups[] = { + "gpio101", "gpio101", "gpio102", "gpio102", +}; +static const char * const gps_tx_groups[] = { + "gpio101", "gpio102", "gpio107", "gpio108", +}; +static const char * const qlink0_wmss_groups[] = { + "gpio103", +}; +static const char * const qlink0_request_groups[] = { + "gpio104", +}; +static const char * const qlink0_enable_groups[] = { + "gpio105", +}; +static const char * const qlink1_wmss_groups[] = { + "gpio106", +}; +static const char * const qlink1_request_groups[] = { + "gpio107", +}; +static const char * const qlink1_enable_groups[] = { + "gpio108", +}; +static const char * const rffe0_data_groups[] = { + "gpio109", +}; +static const char * const rffe0_clk_groups[] = { + "gpio110", +}; +static const char * const rffe1_data_groups[] = { + "gpio111", +}; +static const char * const rffe1_clk_groups[] = { + "gpio112", +}; +static const char * const rffe2_data_groups[] = { + "gpio113", +}; +static const char * const rffe2_clk_groups[] = { + "gpio114", +}; +static const char * const rffe3_data_groups[] = { + "gpio115", +}; +static const char * const rffe3_clk_groups[] = { + "gpio116", +}; +static const char * const rffe4_data_groups[] = { + "gpio117", +}; +static const char * const rffe4_clk_groups[] = { + "gpio118", +}; +static const char * const pa_indicator_groups[] = { + "gpio118", +}; +static const char * const pcie0_clk_groups[] = { + "gpio122", +}; +static const char * const usb_phy_groups[] = { + "gpio124", +}; + +static const struct pinfunction sm6350_functions[] = { + MSM_PIN_FUNCTION(adsp_ext), + MSM_PIN_FUNCTION(agera_pll), + MSM_PIN_FUNCTION(atest_char), + MSM_PIN_FUNCTION(atest_char0), + MSM_PIN_FUNCTION(atest_char1), + MSM_PIN_FUNCTION(atest_char2), + MSM_PIN_FUNCTION(atest_char3), + MSM_PIN_FUNCTION(atest_tsens), + MSM_PIN_FUNCTION(atest_tsens2), + MSM_PIN_FUNCTION(atest_usb), + MSM_PIN_FUNCTION(audio_ref), + MSM_PIN_FUNCTION(btfm_slimbus), + MSM_PIN_FUNCTION(cam_mclk0), + MSM_PIN_FUNCTION(cam_mclk1), + MSM_PIN_FUNCTION(cam_mclk2), + MSM_PIN_FUNCTION(cam_mclk3), + MSM_PIN_FUNCTION(cam_mclk4), + MSM_PIN_FUNCTION(cci_async), + MSM_PIN_FUNCTION(cci_i2c), + MSM_PIN_FUNCTION(cci_timer0), + MSM_PIN_FUNCTION(cci_timer1), + MSM_PIN_FUNCTION(cci_timer2), + MSM_PIN_FUNCTION(cci_timer3), + MSM_PIN_FUNCTION(cci_timer4), + MSM_PIN_FUNCTION(cri_trng), + MSM_PIN_FUNCTION(dbg_out), + MSM_PIN_FUNCTION(ddr_bist), + MSM_PIN_FUNCTION(ddr_pxi0), + MSM_PIN_FUNCTION(ddr_pxi1), + MSM_PIN_FUNCTION(ddr_pxi2), + MSM_PIN_FUNCTION(ddr_pxi3), + MSM_PIN_FUNCTION(dp_hot), + MSM_PIN_FUNCTION(edp_lcd), + MSM_PIN_FUNCTION(gcc_gp1), + MSM_PIN_FUNCTION(gcc_gp2), + MSM_PIN_FUNCTION(gcc_gp3), + MSM_PIN_FUNCTION(gp_pdm0), + MSM_PIN_FUNCTION(gp_pdm1), + MSM_PIN_FUNCTION(gp_pdm2), + MSM_PIN_FUNCTION(gpio), + MSM_PIN_FUNCTION(gps_tx), + MSM_PIN_FUNCTION(ibi_i3c), + MSM_PIN_FUNCTION(jitter_bist), + MSM_PIN_FUNCTION(ldo_en), + MSM_PIN_FUNCTION(ldo_update), + MSM_PIN_FUNCTION(lpass_ext), + MSM_PIN_FUNCTION(m_voc), + MSM_PIN_FUNCTION(mclk), + MSM_PIN_FUNCTION(mdp_vsync), + MSM_PIN_FUNCTION(mdp_vsync0), + MSM_PIN_FUNCTION(mdp_vsync1), + MSM_PIN_FUNCTION(mdp_vsync2), + MSM_PIN_FUNCTION(mdp_vsync3), + MSM_PIN_FUNCTION(mi2s_0), + MSM_PIN_FUNCTION(mi2s_1), + MSM_PIN_FUNCTION(mi2s_2), + MSM_PIN_FUNCTION(mss_lte), + MSM_PIN_FUNCTION(nav_gpio), + MSM_PIN_FUNCTION(nav_pps), + MSM_PIN_FUNCTION(pa_indicator), + MSM_PIN_FUNCTION(pcie0_clk), + MSM_PIN_FUNCTION(phase_flag), + MSM_PIN_FUNCTION(pll_bist), + MSM_PIN_FUNCTION(pll_bypassnl), + MSM_PIN_FUNCTION(pll_reset), + MSM_PIN_FUNCTION(prng_rosc), + MSM_PIN_FUNCTION(qdss_cti), + MSM_PIN_FUNCTION(qdss_gpio), + MSM_PIN_FUNCTION(qdss_gpio0), + MSM_PIN_FUNCTION(qdss_gpio1), + MSM_PIN_FUNCTION(qdss_gpio10), + MSM_PIN_FUNCTION(qdss_gpio11), + MSM_PIN_FUNCTION(qdss_gpio12), + MSM_PIN_FUNCTION(qdss_gpio13), + MSM_PIN_FUNCTION(qdss_gpio14), + MSM_PIN_FUNCTION(qdss_gpio15), + MSM_PIN_FUNCTION(qdss_gpio2), + MSM_PIN_FUNCTION(qdss_gpio3), + MSM_PIN_FUNCTION(qdss_gpio4), + MSM_PIN_FUNCTION(qdss_gpio5), + MSM_PIN_FUNCTION(qdss_gpio6), + MSM_PIN_FUNCTION(qdss_gpio7), + MSM_PIN_FUNCTION(qdss_gpio8), + MSM_PIN_FUNCTION(qdss_gpio9), + MSM_PIN_FUNCTION(qlink0_enable), + MSM_PIN_FUNCTION(qlink0_request), + MSM_PIN_FUNCTION(qlink0_wmss), + MSM_PIN_FUNCTION(qlink1_enable), + MSM_PIN_FUNCTION(qlink1_request), + MSM_PIN_FUNCTION(qlink1_wmss), + MSM_PIN_FUNCTION(qup00), + MSM_PIN_FUNCTION(qup01), + MSM_PIN_FUNCTION(qup02), + MSM_PIN_FUNCTION(qup10), + MSM_PIN_FUNCTION(qup11), + MSM_PIN_FUNCTION(qup12), + MSM_PIN_FUNCTION(qup13_f1), + MSM_PIN_FUNCTION(qup13_f2), + MSM_PIN_FUNCTION(qup14), + MSM_PIN_FUNCTION(rffe0_clk), + MSM_PIN_FUNCTION(rffe0_data), + MSM_PIN_FUNCTION(rffe1_clk), + MSM_PIN_FUNCTION(rffe1_data), + MSM_PIN_FUNCTION(rffe2_clk), + MSM_PIN_FUNCTION(rffe2_data), + MSM_PIN_FUNCTION(rffe3_clk), + MSM_PIN_FUNCTION(rffe3_data), + MSM_PIN_FUNCTION(rffe4_clk), + MSM_PIN_FUNCTION(rffe4_data), + MSM_PIN_FUNCTION(sd_write), + MSM_PIN_FUNCTION(sdc1_tb), + MSM_PIN_FUNCTION(sdc2_tb), + MSM_PIN_FUNCTION(sp_cmu), + MSM_PIN_FUNCTION(tgu_ch0), + MSM_PIN_FUNCTION(tgu_ch1), + MSM_PIN_FUNCTION(tgu_ch2), + MSM_PIN_FUNCTION(tgu_ch3), + MSM_PIN_FUNCTION(tsense_pwm1), + MSM_PIN_FUNCTION(tsense_pwm2), + MSM_PIN_FUNCTION(uim1_clk), + MSM_PIN_FUNCTION(uim1_data), + MSM_PIN_FUNCTION(uim1_present), + MSM_PIN_FUNCTION(uim1_reset), + MSM_PIN_FUNCTION(uim2_clk), + MSM_PIN_FUNCTION(uim2_data), + MSM_PIN_FUNCTION(uim2_present), + MSM_PIN_FUNCTION(uim2_reset), + MSM_PIN_FUNCTION(usb_phy), + MSM_PIN_FUNCTION(vfr_1), + MSM_PIN_FUNCTION(vsense_trigger), + MSM_PIN_FUNCTION(wlan1_adc0), + MSM_PIN_FUNCTION(wlan1_adc1), + MSM_PIN_FUNCTION(wlan2_adc0), + MSM_PIN_FUNCTION(wlan2_adc1), +}; + +/* + * Every pin is maintained as a single group, and missing or non-existing pin + * would be maintained as dummy group to synchronize pin group index with + * pin descriptor registered with pinctrl core. + * Clients would not be able to request these dummy pin groups. + */ +static const struct msm_pingroup sm6350_groups[] = { + [0] = PINGROUP(0, ibi_i3c, qup00, cri_trng, _, _, _, _, _, _), + [1] = PINGROUP(1, ibi_i3c, qup00, cri_trng, _, _, _, _, _, _), + [2] = PINGROUP(2, qup00, cci_i2c, cri_trng, qdss_cti, _, _, _, _, _), + [3] = PINGROUP(3, qup00, cci_i2c, sp_cmu, dbg_out, qdss_cti, _, _, _, _), + [4] = PINGROUP(4, qup14, qup14, sdc1_tb, _, _, _, _, _, _), + [5] = PINGROUP(5, qup14, qup14, sdc2_tb, _, _, _, _, _, _), + [6] = PINGROUP(6, mdp_vsync, qdss_cti, _, _, _, _, _, _, _), + [7] = PINGROUP(7, qdss_cti, _, _, _, _, _, _, _, _), + [8] = PINGROUP(8, gp_pdm1, qdss_gpio, _, _, _, _, _, _, _), + [9] = PINGROUP(9, qdss_gpio, _, _, _, _, _, _, _, _), + [10] = PINGROUP(10, _, _, _, _, _, _, _, _, _), + [11] = PINGROUP(11, _, _, _, _, _, _, _, _, _), + [12] = PINGROUP(12, m_voc, dp_hot, _, phase_flag, _, _, _, _, _), + [13] = PINGROUP(13, qup10, pll_bypassnl, _, _, _, _, _, _, _), + [14] = PINGROUP(14, qup10, pll_reset, _, _, _, _, _, _, _), + [15] = PINGROUP(15, qup10, _, _, _, _, _, _, _, _), + [16] = PINGROUP(16, qup10, _, _, _, _, _, _, _, _), + [17] = PINGROUP(17, _, phase_flag, qup10, _, _, _, _, _, _), + [18] = PINGROUP(18, _, phase_flag, _, _, _, _, _, _, _), + [19] = PINGROUP(19, qup12, qup12, ddr_bist, _, _, _, _, _, _), + [20] = PINGROUP(20, qup12, qup12, ddr_bist, _, _, _, _, _, _), + [21] = PINGROUP(21, gcc_gp2, ddr_bist, _, _, _, _, _, _, _), + [22] = PINGROUP(22, gcc_gp3, ddr_bist, _, _, _, _, _, _, _), + [23] = PINGROUP(23, mdp_vsync, edp_lcd, _, _, _, _, _, _, _), + [24] = PINGROUP(24, mdp_vsync, _, _, _, _, _, _, _, _), + [25] = PINGROUP(25, qup13_f1, qup13_f2, _, _, _, _, _, _, _), + [26] = PINGROUP(26, qup13_f1, qup13_f2, _, _, _, _, _, _, _), + [27] = PINGROUP(27, qup11, qup11, mdp_vsync, pll_bist, _, qdss_gpio14, _, _, _), + [28] = PINGROUP(28, qup11, qup11, mdp_vsync, _, qdss_gpio15, _, _, _, _), + [29] = PINGROUP(29, cam_mclk0, _, _, _, _, _, _, _, _), + [30] = PINGROUP(30, cam_mclk1, _, _, _, _, _, _, _, _), + [31] = PINGROUP(31, cam_mclk2, _, _, _, _, _, _, _, _), + [32] = PINGROUP(32, cam_mclk3, _, _, _, _, _, _, _, _), + [33] = PINGROUP(33, cam_mclk4, _, _, _, _, _, _, _, _), + [34] = PINGROUP(34, cci_timer0, _, phase_flag, qdss_gpio12, _, _, _, _, _), + [35] = PINGROUP(35, cci_timer1, cci_async, _, phase_flag, qdss_gpio13, _, _, _, _), + [36] = PINGROUP(36, cci_timer2, cci_async, _, phase_flag, qdss_gpio14, _, _, _, _), + [37] = PINGROUP(37, cci_timer3, gp_pdm0, _, phase_flag, qdss_gpio15, _, _, _, _), + [38] = PINGROUP(38, cci_timer4, _, phase_flag, qdss_gpio2, _, _, _, _, _), + [39] = PINGROUP(39, cci_i2c, _, phase_flag, qdss_gpio0, _, _, _, _, _), + [40] = PINGROUP(40, cci_i2c, _, phase_flag, qdss_gpio1, _, _, _, _, _), + [41] = PINGROUP(41, cci_i2c, _, phase_flag, qdss_gpio2, _, _, _, _, _), + [42] = PINGROUP(42, cci_i2c, _, phase_flag, qdss_gpio3, _, _, _, _, _), + [43] = PINGROUP(43, cci_i2c, _, phase_flag, qdss_gpio4, _, _, _, _, _), + [44] = PINGROUP(44, cci_i2c, _, phase_flag, qdss_gpio5, _, _, _, _, _), + [45] = PINGROUP(45, qup02, _, phase_flag, qdss_gpio6, _, _, _, _, _), + [46] = PINGROUP(46, qup02, _, phase_flag, qdss_gpio7, _, _, _, _, _), + [47] = PINGROUP(47, mdp_vsync0, _, phase_flag, qdss_gpio3, _, _, _, _, _), + [48] = PINGROUP(48, cci_async, mdp_vsync1, gcc_gp1, _, phase_flag, qdss_gpio8, qup02, _, _), + [49] = PINGROUP(49, vfr_1, _, phase_flag, qdss_gpio9, _, _, _, _, _), + [50] = PINGROUP(50, _, phase_flag, qdss_gpio10, _, _, _, _, _, _), + [51] = PINGROUP(51, _, phase_flag, qdss_gpio11, _, _, _, _, _, _), + [52] = PINGROUP(52, cci_async, gp_pdm1, _, phase_flag, qdss_gpio12, _, _, _, _), + [53] = PINGROUP(53, cci_async, _, phase_flag, qdss_gpio13, _, _, _, _, _), + [54] = PINGROUP(54, _, _, _, _, _, _, _, _, _), + [55] = PINGROUP(55, _, _, _, _, _, _, _, _, _), + [56] = PINGROUP(56, qup02, mdp_vsync2, _, phase_flag, qdss_gpio10, _, _, _, _), + [57] = PINGROUP(57, qup02, mdp_vsync3, gp_pdm2, _, phase_flag, qdss_gpio11, _, _, _), + [58] = PINGROUP(58, gcc_gp1, _, _, _, _, _, _, _, _), + [59] = PINGROUP(59, _, _, _, _, _, _, _, _, _), + [60] = PINGROUP(60, audio_ref, lpass_ext, mi2s_2, _, phase_flag, _, _, _, _), + [61] = PINGROUP(61, qup01, tgu_ch0, _, phase_flag, qdss_cti, _, _, _, _), + [62] = PINGROUP(62, qup01, tgu_ch1, _, phase_flag, qdss_cti, _, _, _, _), + [63] = PINGROUP(63, qup01, tgu_ch2, _, phase_flag, qdss_gpio, _, _, _, _), + [64] = PINGROUP(64, qup01, tgu_ch3, _, phase_flag, qdss_gpio, _, _, _, _), + [65] = PINGROUP(65, mss_lte, _, qdss_gpio0, _, _, _, _, _, _), + [66] = PINGROUP(66, mss_lte, _, qdss_gpio1, _, _, _, _, _, _), + [67] = PINGROUP(67, btfm_slimbus, mi2s_1, _, phase_flag, _, _, _, _, _), + [68] = PINGROUP(68, btfm_slimbus, mi2s_1, gp_pdm0, _, phase_flag, _, _, _, _), + [69] = PINGROUP(69, _, _, _, _, _, _, _, _, _), + [70] = PINGROUP(70, _, _, _, _, _, _, _, _, _), + [71] = PINGROUP(71, _, _, _, _, _, _, _, _, _), + [72] = PINGROUP(72, mi2s_2, _, _, _, _, _, _, _, _), + [73] = PINGROUP(73, mi2s_2, _, _, _, _, _, _, _, _), + [74] = PINGROUP(74, mi2s_2, _, _, _, _, _, _, _, _), + [75] = PINGROUP(75, uim2_data, _, _, _, _, _, _, _, _), + [76] = PINGROUP(76, uim2_clk, _, _, _, _, _, _, _, _), + [77] = PINGROUP(77, uim2_reset, _, _, _, _, _, _, _, _), + [78] = PINGROUP(78, uim2_present, _, _, _, _, _, _, _, _), + [79] = PINGROUP(79, uim1_data, _, _, _, _, _, _, _, _), + [80] = PINGROUP(80, uim1_clk, _, _, _, _, _, _, _, _), + [81] = PINGROUP(81, uim1_reset, _, _, _, _, _, _, _, _), + [82] = PINGROUP(82, uim1_present, _, _, _, _, _, _, _, _), + [83] = PINGROUP(83, atest_usb, _, _, _, _, _, _, _, _), + [84] = PINGROUP(84, _, atest_usb, _, _, _, _, _, _, _), + [85] = PINGROUP(85, sd_write, _, atest_usb, _, _, _, _, _, _), + [86] = PINGROUP(86, btfm_slimbus, mi2s_1, _, qdss_cti, atest_usb, ddr_pxi0, _, _, _), + [87] = PINGROUP(87, btfm_slimbus, mi2s_1, adsp_ext, _, qdss_cti, atest_usb, ddr_pxi1, _, _), + [88] = PINGROUP(88, mi2s_0, _, qdss_gpio4, _, atest_usb, ddr_pxi2, + tsense_pwm1, tsense_pwm2, _), + [89] = PINGROUP(89, mi2s_0, agera_pll, _, qdss_gpio5, _, + vsense_trigger, atest_usb, ddr_pxi3, _), + [90] = PINGROUP(90, mi2s_0, jitter_bist, _, qdss_gpio6, _, + wlan1_adc0, atest_usb, ddr_pxi0, _), + [91] = PINGROUP(91, mi2s_0, _, qdss_gpio7, _, wlan2_adc0, + atest_usb, ddr_pxi1, _, _), + [92] = PINGROUP(92, _, qdss_gpio8, atest_tsens, wlan1_adc1, + atest_usb, ddr_pxi2, _, _, _), + [93] = PINGROUP(93, mclk, lpass_ext, _, qdss_gpio9, atest_tsens2, + wlan2_adc1, ddr_pxi3, _, _), + [94] = PINGROUP(94, _, _, _, _, _, _, _, _, _), + [95] = PINGROUP(95, ldo_en, _, atest_char, _, _, _, _, _, _), + [96] = PINGROUP(96, ldo_update, _, atest_char0, _, _, _, _, _, _), + [97] = PINGROUP(97, prng_rosc, _, atest_char1, _, _, _, _, _, _), + [98] = PINGROUP(98, _, atest_char2, _, _, _, _, _, _, _), + [99] = PINGROUP(99, _, atest_char3, _, _, _, _, _, _, _), + [100] = PINGROUP(100, _, _, _, _, _, _, _, _, _), + [101] = PINGROUP(101, nav_gpio, nav_pps, nav_pps, gps_tx, _, _, _, _, _), + [102] = PINGROUP(102, nav_gpio, nav_pps, nav_pps, gps_tx, _, _, _, _, _), + [103] = PINGROUP(103, qlink0_wmss, _, _, _, _, _, _, _, _), + [104] = PINGROUP(104, qlink0_request, _, _, _, _, _, _, _, _), + [105] = PINGROUP(105, qlink0_enable, _, _, _, _, _, _, _, _), + [106] = PINGROUP(106, qlink1_wmss, _, _, _, _, _, _, _, _), + [107] = PINGROUP(107, qlink1_request, gps_tx, _, _, _, _, _, _, _), + [108] = PINGROUP(108, qlink1_enable, gps_tx, _, _, _, _, _, _, _), + [109] = PINGROUP(109, rffe0_data, _, _, _, _, _, _, _, _), + [110] = PINGROUP(110, rffe0_clk, _, _, _, _, _, _, _, _), + [111] = PINGROUP(111, rffe1_data, _, _, _, _, _, _, _, _), + [112] = PINGROUP(112, rffe1_clk, _, _, _, _, _, _, _, _), + [113] = PINGROUP(113, rffe2_data, _, _, _, _, _, _, _, _), + [114] = PINGROUP(114, rffe2_clk, _, _, _, _, _, _, _, _), + [115] = PINGROUP(115, rffe3_data, _, _, _, _, _, _, _, _), + [116] = PINGROUP(116, rffe3_clk, _, _, _, _, _, _, _, _), + [117] = PINGROUP(117, rffe4_data, _, _, _, _, _, _, _, _), + [118] = PINGROUP(118, rffe4_clk, _, pa_indicator, dp_hot, _, _, _, _, _), + [119] = PINGROUP(119, _, _, _, _, _, _, _, _, _), + [120] = PINGROUP(120, _, _, _, _, _, _, _, _, _), + [121] = PINGROUP(121, _, _, _, _, _, _, _, _, _), + [122] = PINGROUP(122, pcie0_clk, _, _, _, _, _, _, _, _), + [123] = PINGROUP(123, _, _, _, _, _, _, _, _, _), + [124] = PINGROUP(124, usb_phy, _, _, _, _, _, _, _, _), + [125] = PINGROUP(125, _, _, _, _, _, _, _, _, _), + [126] = PINGROUP(126, _, _, _, _, _, _, _, _, _), + [127] = PINGROUP(127, _, _, _, _, _, _, _, _, _), + [128] = PINGROUP(128, _, _, _, _, _, _, _, _, _), + [129] = PINGROUP(129, _, _, _, _, _, _, _, _, _), + [130] = PINGROUP(130, _, _, _, _, _, _, _, _, _), + [131] = PINGROUP(131, _, _, _, _, _, _, _, _, _), + [132] = PINGROUP(132, _, _, _, _, _, _, _, _, _), + [133] = PINGROUP(133, _, _, _, _, _, _, _, _, _), + [134] = PINGROUP(134, _, _, _, _, _, _, _, _, _), + [135] = PINGROUP(135, _, _, _, _, _, _, _, _, _), + [136] = PINGROUP(136, _, _, _, _, _, _, _, _, _), + [137] = PINGROUP(137, _, _, _, _, _, _, _, _, _), + [138] = PINGROUP(138, _, _, _, _, _, _, _, _, _), + [139] = PINGROUP(139, _, _, _, _, _, _, _, _, _), + [140] = PINGROUP(140, _, _, _, _, _, _, _, _, _), + [141] = PINGROUP(141, _, _, _, _, _, _, _, _, _), + [142] = PINGROUP(142, _, _, _, _, _, _, _, _, _), + [143] = PINGROUP(143, _, _, _, _, _, _, _, _, _), + [144] = PINGROUP(144, _, _, _, _, _, _, _, _, _), + [145] = PINGROUP(145, _, _, _, _, _, _, _, _, _), + [146] = PINGROUP(146, _, _, _, _, _, _, _, _, _), + [147] = PINGROUP(147, _, _, _, _, _, _, _, _, _), + [148] = PINGROUP(148, _, _, _, _, _, _, _, _, _), + [149] = PINGROUP(149, _, _, _, _, _, _, _, _, _), + [150] = PINGROUP(150, _, _, _, _, _, _, _, _, _), + [151] = PINGROUP(151, _, _, _, _, _, _, _, _, _), + [152] = PINGROUP(152, _, _, _, _, _, _, _, _, _), + [153] = PINGROUP(153, _, _, _, _, _, _, _, _, _), + [154] = PINGROUP(154, _, _, _, _, _, _, _, _, _), + [155] = PINGROUP(155, _, _, _, _, _, _, _, _, _), + [156] = UFS_RESET(ufs_reset, 0xae000), + [157] = SDC_PINGROUP(sdc1_rclk, 0xa1000, 15, 0), + [158] = SDC_PINGROUP(sdc1_clk, 0xa0000, 13, 6), + [159] = SDC_PINGROUP(sdc1_cmd, 0xa0000, 11, 3), + [160] = SDC_PINGROUP(sdc1_data, 0xa0000, 9, 0), + [161] = SDC_PINGROUP(sdc2_clk, 0xa2000, 14, 6), + [162] = SDC_PINGROUP(sdc2_cmd, 0xa2000, 11, 3), + [163] = SDC_PINGROUP(sdc2_data, 0xa2000, 9, 0), +}; + +static const struct msm_gpio_wakeirq_map sm6350_pdc_map[] = { + { 3, 126 }, { 4, 151 }, { 7, 58 }, { 8, 113 }, { 9, 66 }, { 11, 106 }, + { 12, 59 }, { 13, 112 }, { 16, 73 }, { 17, 74 }, { 18, 75 }, { 19, 76 }, + { 21, 130 }, { 22, 96 }, { 23, 146 }, { 24, 114 }, { 25, 83 }, + { 27, 84 }, { 28, 85 }, { 34, 147 }, { 35, 92 }, { 36, 93 }, { 37, 94 }, + { 38, 68 }, { 48, 100 }, { 50, 57 }, { 51, 81 }, { 52, 80 }, { 53, 69 }, + { 54, 71 }, { 55, 70 }, { 57, 152 }, { 58, 115 }, { 59, 116 }, { 60, 117 }, + { 61, 118 }, { 62, 119 }, { 64, 121 }, { 66, 127 }, { 67, 128 }, + { 69, 60 }, { 73, 78 }, { 78, 135 }, { 82, 138 }, { 83, 140 }, + { 84, 141 }, { 85, 98 }, { 87, 88 }, { 88, 107 }, { 89, 109 }, + { 90, 110 }, { 91, 111 }, { 92, 149 }, { 93, 101 }, { 94, 61 }, + { 95, 65 }, { 96, 95 }, { 97, 72 }, { 98, 145 }, { 99, 150 }, + { 100, 108 }, { 104, 129 }, { 107, 131 }, { 110, 132 }, { 112, 133 }, + { 114, 134 }, { 116, 136 }, { 118, 137 }, { 122, 97 }, { 123, 99 }, + { 124, 148 }, { 125, 82 }, { 128, 144 }, { 129, 86 }, { 131, 87 }, + { 133, 142 }, { 134, 143 }, { 136, 102 }, { 137, 91 }, { 138, 77 }, + { 139, 79 }, { 140, 90 }, { 142, 103 }, { 144, 105 }, { 147, 104 }, + { 153, 120 }, { 155, 67 } +}; + +static const struct msm_pinctrl_soc_data sm6350_tlmm = { + .pins = sm6350_pins, + .npins = ARRAY_SIZE(sm6350_pins), + .functions = sm6350_functions, + .nfunctions = ARRAY_SIZE(sm6350_functions), + .groups = sm6350_groups, + .ngroups = ARRAY_SIZE(sm6350_groups), + .ngpios = 157, + .wakeirq_map = sm6350_pdc_map, + .nwakeirq_map = ARRAY_SIZE(sm6350_pdc_map), + .wakeirq_dual_edge_errata = true, +}; + +static int sm6350_tlmm_probe(struct platform_device *pdev) +{ + return msm_pinctrl_probe(pdev, &sm6350_tlmm); +} + +static const struct of_device_id sm6350_tlmm_of_match[] = { + { .compatible = "qcom,sm6350-tlmm" }, + { }, +}; + +static struct platform_driver sm6350_tlmm_driver = { + .driver = { + .name = "sm6350-tlmm", + .of_match_table = sm6350_tlmm_of_match, + }, + .probe = sm6350_tlmm_probe, + .remove = msm_pinctrl_remove, +}; + +static int __init sm6350_tlmm_init(void) +{ + return platform_driver_register(&sm6350_tlmm_driver); +} +arch_initcall(sm6350_tlmm_init); + +static void __exit sm6350_tlmm_exit(void) +{ + platform_driver_unregister(&sm6350_tlmm_driver); +} +module_exit(sm6350_tlmm_exit); + +MODULE_DESCRIPTION("QTI SM6350 TLMM driver"); +MODULE_LICENSE("GPL v2"); +MODULE_DEVICE_TABLE(of, sm6350_tlmm_of_match); diff --git a/drivers/pinctrl/qcom/pinctrl-sm6375.c b/drivers/pinctrl/qcom/pinctrl-sm6375.c new file mode 100644 index 0000000000..c82c851693 --- /dev/null +++ b/drivers/pinctrl/qcom/pinctrl-sm6375.c @@ -0,0 +1,1536 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2021, The Linux Foundation. All rights reserved. + * Copyright (c) 2022, Konrad Dybcio <konrad.dybcio@somainline.org> + */ + +#include <linux/module.h> +#include <linux/of.h> +#include <linux/platform_device.h> + +#include "pinctrl-msm.h" + +#define REG_BASE 0x100000 +#define REG_SIZE 0x1000 +#define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7, f8, f9) \ + { \ + .grp = PINCTRL_PINGROUP("gpio" #id, \ + gpio##id##_pins, \ + ARRAY_SIZE(gpio##id##_pins)), \ + .funcs = (int[]){ \ + msm_mux_gpio, /* gpio mode */ \ + msm_mux_##f1, \ + msm_mux_##f2, \ + msm_mux_##f3, \ + msm_mux_##f4, \ + msm_mux_##f5, \ + msm_mux_##f6, \ + msm_mux_##f7, \ + msm_mux_##f8, \ + msm_mux_##f9 \ + }, \ + .nfuncs = 10, \ + .ctl_reg = REG_SIZE * id, \ + .io_reg = REG_SIZE * id + 0x4, \ + .intr_cfg_reg = REG_SIZE * id + 0x8, \ + .intr_status_reg = REG_SIZE * id + 0xc, \ + .intr_target_reg = REG_SIZE * id + 0x8, \ + .mux_bit = 2, \ + .pull_bit = 0, \ + .drv_bit = 6, \ + .egpio_enable = 12, \ + .egpio_present = 11, \ + .oe_bit = 9, \ + .in_bit = 0, \ + .out_bit = 1, \ + .intr_enable_bit = 0, \ + .intr_status_bit = 0, \ + .intr_target_bit = 5, \ + .intr_target_kpss_val = 3, \ + .intr_raw_status_bit = 4, \ + .intr_polarity_bit = 1, \ + .intr_detection_bit = 2, \ + .intr_detection_width = 2, \ + } + +#define SDC_PINGROUP(pg_name, ctl, pull, drv) \ + { \ + .grp = PINCTRL_PINGROUP(#pg_name, \ + pg_name##_pins, \ + ARRAY_SIZE(pg_name##_pins)), \ + .ctl_reg = ctl, \ + .io_reg = 0, \ + .intr_cfg_reg = 0, \ + .intr_status_reg = 0, \ + .intr_target_reg = 0, \ + .mux_bit = -1, \ + .pull_bit = pull, \ + .drv_bit = drv, \ + .oe_bit = -1, \ + .in_bit = -1, \ + .out_bit = -1, \ + .intr_enable_bit = -1, \ + .intr_status_bit = -1, \ + .intr_target_bit = -1, \ + .intr_raw_status_bit = -1, \ + .intr_polarity_bit = -1, \ + .intr_detection_bit = -1, \ + .intr_detection_width = -1, \ + } + +#define UFS_RESET(pg_name, offset) \ + { \ + .grp = PINCTRL_PINGROUP(#pg_name, \ + pg_name##_pins, \ + ARRAY_SIZE(pg_name##_pins)), \ + .ctl_reg = offset, \ + .io_reg = offset + 0x4, \ + .intr_cfg_reg = 0, \ + .intr_status_reg = 0, \ + .intr_target_reg = 0, \ + .mux_bit = -1, \ + .pull_bit = 3, \ + .drv_bit = 0, \ + .oe_bit = -1, \ + .in_bit = -1, \ + .out_bit = 0, \ + .intr_enable_bit = -1, \ + .intr_status_bit = -1, \ + .intr_target_bit = -1, \ + .intr_raw_status_bit = -1, \ + .intr_polarity_bit = -1, \ + .intr_detection_bit = -1, \ + .intr_detection_width = -1, \ + } + +static const struct pinctrl_pin_desc sm6375_pins[] = { + PINCTRL_PIN(0, "GPIO_0"), + PINCTRL_PIN(1, "GPIO_1"), + PINCTRL_PIN(2, "GPIO_2"), + PINCTRL_PIN(3, "GPIO_3"), + PINCTRL_PIN(4, "GPIO_4"), + PINCTRL_PIN(5, "GPIO_5"), + PINCTRL_PIN(6, "GPIO_6"), + PINCTRL_PIN(7, "GPIO_7"), + PINCTRL_PIN(8, "GPIO_8"), + PINCTRL_PIN(9, "GPIO_9"), + PINCTRL_PIN(10, "GPIO_10"), + PINCTRL_PIN(11, "GPIO_11"), + PINCTRL_PIN(12, "GPIO_12"), + PINCTRL_PIN(13, "GPIO_13"), + PINCTRL_PIN(14, "GPIO_14"), + PINCTRL_PIN(15, "GPIO_15"), + PINCTRL_PIN(16, "GPIO_16"), + PINCTRL_PIN(17, "GPIO_17"), + PINCTRL_PIN(18, "GPIO_18"), + PINCTRL_PIN(19, "GPIO_19"), + PINCTRL_PIN(20, "GPIO_20"), + PINCTRL_PIN(21, "GPIO_21"), + PINCTRL_PIN(22, "GPIO_22"), + PINCTRL_PIN(23, "GPIO_23"), + PINCTRL_PIN(24, "GPIO_24"), + PINCTRL_PIN(25, "GPIO_25"), + PINCTRL_PIN(26, "GPIO_26"), + PINCTRL_PIN(27, "GPIO_27"), + PINCTRL_PIN(28, "GPIO_28"), + PINCTRL_PIN(29, "GPIO_29"), + PINCTRL_PIN(30, "GPIO_30"), + PINCTRL_PIN(31, "GPIO_31"), + PINCTRL_PIN(32, "GPIO_32"), + PINCTRL_PIN(33, "GPIO_33"), + PINCTRL_PIN(34, "GPIO_34"), + PINCTRL_PIN(35, "GPIO_35"), + PINCTRL_PIN(36, "GPIO_36"), + PINCTRL_PIN(37, "GPIO_37"), + PINCTRL_PIN(38, "GPIO_38"), + PINCTRL_PIN(39, "GPIO_39"), + PINCTRL_PIN(40, "GPIO_40"), + PINCTRL_PIN(41, "GPIO_41"), + PINCTRL_PIN(42, "GPIO_42"), + PINCTRL_PIN(43, "GPIO_43"), + PINCTRL_PIN(44, "GPIO_44"), + PINCTRL_PIN(45, "GPIO_45"), + PINCTRL_PIN(46, "GPIO_46"), + PINCTRL_PIN(47, "GPIO_47"), + PINCTRL_PIN(48, "GPIO_48"), + PINCTRL_PIN(49, "GPIO_49"), + PINCTRL_PIN(50, "GPIO_50"), + PINCTRL_PIN(51, "GPIO_51"), + PINCTRL_PIN(52, "GPIO_52"), + PINCTRL_PIN(53, "GPIO_53"), + PINCTRL_PIN(54, "GPIO_54"), + PINCTRL_PIN(55, "GPIO_55"), + PINCTRL_PIN(56, "GPIO_56"), + PINCTRL_PIN(57, "GPIO_57"), + PINCTRL_PIN(58, "GPIO_58"), + PINCTRL_PIN(59, "GPIO_59"), + PINCTRL_PIN(60, "GPIO_60"), + PINCTRL_PIN(61, "GPIO_61"), + PINCTRL_PIN(62, "GPIO_62"), + PINCTRL_PIN(63, "GPIO_63"), + PINCTRL_PIN(64, "GPIO_64"), + PINCTRL_PIN(65, "GPIO_65"), + PINCTRL_PIN(66, "GPIO_66"), + PINCTRL_PIN(67, "GPIO_67"), + PINCTRL_PIN(68, "GPIO_68"), + PINCTRL_PIN(69, "GPIO_69"), + PINCTRL_PIN(70, "GPIO_70"), + PINCTRL_PIN(71, "GPIO_71"), + PINCTRL_PIN(72, "GPIO_72"), + PINCTRL_PIN(73, "GPIO_73"), + PINCTRL_PIN(74, "GPIO_74"), + PINCTRL_PIN(75, "GPIO_75"), + PINCTRL_PIN(76, "GPIO_76"), + PINCTRL_PIN(77, "GPIO_77"), + PINCTRL_PIN(78, "GPIO_78"), + PINCTRL_PIN(79, "GPIO_79"), + PINCTRL_PIN(80, "GPIO_80"), + PINCTRL_PIN(81, "GPIO_81"), + PINCTRL_PIN(82, "GPIO_82"), + PINCTRL_PIN(83, "GPIO_83"), + PINCTRL_PIN(84, "GPIO_84"), + PINCTRL_PIN(85, "GPIO_85"), + PINCTRL_PIN(86, "GPIO_86"), + PINCTRL_PIN(87, "GPIO_87"), + PINCTRL_PIN(88, "GPIO_88"), + PINCTRL_PIN(89, "GPIO_89"), + PINCTRL_PIN(90, "GPIO_90"), + PINCTRL_PIN(91, "GPIO_91"), + PINCTRL_PIN(92, "GPIO_92"), + PINCTRL_PIN(93, "GPIO_93"), + PINCTRL_PIN(94, "GPIO_94"), + PINCTRL_PIN(95, "GPIO_95"), + PINCTRL_PIN(96, "GPIO_96"), + PINCTRL_PIN(97, "GPIO_97"), + PINCTRL_PIN(98, "GPIO_98"), + PINCTRL_PIN(99, "GPIO_99"), + PINCTRL_PIN(100, "GPIO_100"), + PINCTRL_PIN(101, "GPIO_101"), + PINCTRL_PIN(102, "GPIO_102"), + PINCTRL_PIN(103, "GPIO_103"), + PINCTRL_PIN(104, "GPIO_104"), + PINCTRL_PIN(105, "GPIO_105"), + PINCTRL_PIN(106, "GPIO_106"), + PINCTRL_PIN(107, "GPIO_107"), + PINCTRL_PIN(108, "GPIO_108"), + PINCTRL_PIN(109, "GPIO_109"), + PINCTRL_PIN(110, "GPIO_110"), + PINCTRL_PIN(111, "GPIO_111"), + PINCTRL_PIN(112, "GPIO_112"), + PINCTRL_PIN(113, "GPIO_113"), + PINCTRL_PIN(114, "GPIO_114"), + PINCTRL_PIN(115, "GPIO_115"), + PINCTRL_PIN(116, "GPIO_116"), + PINCTRL_PIN(117, "GPIO_117"), + PINCTRL_PIN(118, "GPIO_118"), + PINCTRL_PIN(119, "GPIO_119"), + PINCTRL_PIN(120, "GPIO_120"), + PINCTRL_PIN(121, "GPIO_121"), + PINCTRL_PIN(122, "GPIO_122"), + PINCTRL_PIN(123, "GPIO_123"), + PINCTRL_PIN(124, "GPIO_124"), + PINCTRL_PIN(125, "GPIO_125"), + PINCTRL_PIN(126, "GPIO_126"), + PINCTRL_PIN(127, "GPIO_127"), + PINCTRL_PIN(128, "GPIO_128"), + PINCTRL_PIN(129, "GPIO_129"), + PINCTRL_PIN(130, "GPIO_130"), + PINCTRL_PIN(131, "GPIO_131"), + PINCTRL_PIN(132, "GPIO_132"), + PINCTRL_PIN(133, "GPIO_133"), + PINCTRL_PIN(134, "GPIO_134"), + PINCTRL_PIN(135, "GPIO_135"), + PINCTRL_PIN(136, "GPIO_136"), + PINCTRL_PIN(137, "GPIO_137"), + PINCTRL_PIN(138, "GPIO_138"), + PINCTRL_PIN(139, "GPIO_139"), + PINCTRL_PIN(140, "GPIO_140"), + PINCTRL_PIN(141, "GPIO_141"), + PINCTRL_PIN(142, "GPIO_142"), + PINCTRL_PIN(143, "GPIO_143"), + PINCTRL_PIN(144, "GPIO_144"), + PINCTRL_PIN(145, "GPIO_145"), + PINCTRL_PIN(146, "GPIO_146"), + PINCTRL_PIN(147, "GPIO_147"), + PINCTRL_PIN(148, "GPIO_148"), + PINCTRL_PIN(149, "GPIO_149"), + PINCTRL_PIN(150, "GPIO_150"), + PINCTRL_PIN(151, "GPIO_151"), + PINCTRL_PIN(152, "GPIO_152"), + PINCTRL_PIN(153, "GPIO_153"), + PINCTRL_PIN(154, "GPIO_154"), + PINCTRL_PIN(155, "GPIO_155"), + PINCTRL_PIN(156, "UFS_RESET"), + PINCTRL_PIN(157, "SDC1_RCLK"), + PINCTRL_PIN(158, "SDC1_CLK"), + PINCTRL_PIN(159, "SDC1_CMD"), + PINCTRL_PIN(160, "SDC1_DATA"), + PINCTRL_PIN(161, "SDC2_CLK"), + PINCTRL_PIN(162, "SDC2_CMD"), + PINCTRL_PIN(163, "SDC2_DATA"), +}; + +#define DECLARE_MSM_GPIO_PINS(pin) \ + static const unsigned int gpio##pin##_pins[] = { pin } +DECLARE_MSM_GPIO_PINS(0); +DECLARE_MSM_GPIO_PINS(1); +DECLARE_MSM_GPIO_PINS(2); +DECLARE_MSM_GPIO_PINS(3); +DECLARE_MSM_GPIO_PINS(4); +DECLARE_MSM_GPIO_PINS(5); +DECLARE_MSM_GPIO_PINS(6); +DECLARE_MSM_GPIO_PINS(7); +DECLARE_MSM_GPIO_PINS(8); +DECLARE_MSM_GPIO_PINS(9); +DECLARE_MSM_GPIO_PINS(10); +DECLARE_MSM_GPIO_PINS(11); +DECLARE_MSM_GPIO_PINS(12); +DECLARE_MSM_GPIO_PINS(13); +DECLARE_MSM_GPIO_PINS(14); +DECLARE_MSM_GPIO_PINS(15); +DECLARE_MSM_GPIO_PINS(16); +DECLARE_MSM_GPIO_PINS(17); +DECLARE_MSM_GPIO_PINS(18); +DECLARE_MSM_GPIO_PINS(19); +DECLARE_MSM_GPIO_PINS(20); +DECLARE_MSM_GPIO_PINS(21); +DECLARE_MSM_GPIO_PINS(22); +DECLARE_MSM_GPIO_PINS(23); +DECLARE_MSM_GPIO_PINS(24); +DECLARE_MSM_GPIO_PINS(25); +DECLARE_MSM_GPIO_PINS(26); +DECLARE_MSM_GPIO_PINS(27); +DECLARE_MSM_GPIO_PINS(28); +DECLARE_MSM_GPIO_PINS(29); +DECLARE_MSM_GPIO_PINS(30); +DECLARE_MSM_GPIO_PINS(31); +DECLARE_MSM_GPIO_PINS(32); +DECLARE_MSM_GPIO_PINS(33); +DECLARE_MSM_GPIO_PINS(34); +DECLARE_MSM_GPIO_PINS(35); +DECLARE_MSM_GPIO_PINS(36); +DECLARE_MSM_GPIO_PINS(37); +DECLARE_MSM_GPIO_PINS(38); +DECLARE_MSM_GPIO_PINS(39); +DECLARE_MSM_GPIO_PINS(40); +DECLARE_MSM_GPIO_PINS(41); +DECLARE_MSM_GPIO_PINS(42); +DECLARE_MSM_GPIO_PINS(43); +DECLARE_MSM_GPIO_PINS(44); +DECLARE_MSM_GPIO_PINS(45); +DECLARE_MSM_GPIO_PINS(46); +DECLARE_MSM_GPIO_PINS(47); +DECLARE_MSM_GPIO_PINS(48); +DECLARE_MSM_GPIO_PINS(49); +DECLARE_MSM_GPIO_PINS(50); +DECLARE_MSM_GPIO_PINS(51); +DECLARE_MSM_GPIO_PINS(52); +DECLARE_MSM_GPIO_PINS(53); +DECLARE_MSM_GPIO_PINS(54); +DECLARE_MSM_GPIO_PINS(55); +DECLARE_MSM_GPIO_PINS(56); +DECLARE_MSM_GPIO_PINS(57); +DECLARE_MSM_GPIO_PINS(58); +DECLARE_MSM_GPIO_PINS(59); +DECLARE_MSM_GPIO_PINS(60); +DECLARE_MSM_GPIO_PINS(61); +DECLARE_MSM_GPIO_PINS(62); +DECLARE_MSM_GPIO_PINS(63); +DECLARE_MSM_GPIO_PINS(64); +DECLARE_MSM_GPIO_PINS(65); +DECLARE_MSM_GPIO_PINS(66); +DECLARE_MSM_GPIO_PINS(67); +DECLARE_MSM_GPIO_PINS(68); +DECLARE_MSM_GPIO_PINS(69); +DECLARE_MSM_GPIO_PINS(70); +DECLARE_MSM_GPIO_PINS(71); +DECLARE_MSM_GPIO_PINS(72); +DECLARE_MSM_GPIO_PINS(73); +DECLARE_MSM_GPIO_PINS(74); +DECLARE_MSM_GPIO_PINS(75); +DECLARE_MSM_GPIO_PINS(76); +DECLARE_MSM_GPIO_PINS(77); +DECLARE_MSM_GPIO_PINS(78); +DECLARE_MSM_GPIO_PINS(79); +DECLARE_MSM_GPIO_PINS(80); +DECLARE_MSM_GPIO_PINS(81); +DECLARE_MSM_GPIO_PINS(82); +DECLARE_MSM_GPIO_PINS(83); +DECLARE_MSM_GPIO_PINS(84); +DECLARE_MSM_GPIO_PINS(85); +DECLARE_MSM_GPIO_PINS(86); +DECLARE_MSM_GPIO_PINS(87); +DECLARE_MSM_GPIO_PINS(88); +DECLARE_MSM_GPIO_PINS(89); +DECLARE_MSM_GPIO_PINS(90); +DECLARE_MSM_GPIO_PINS(91); +DECLARE_MSM_GPIO_PINS(92); +DECLARE_MSM_GPIO_PINS(93); +DECLARE_MSM_GPIO_PINS(94); +DECLARE_MSM_GPIO_PINS(95); +DECLARE_MSM_GPIO_PINS(96); +DECLARE_MSM_GPIO_PINS(97); +DECLARE_MSM_GPIO_PINS(98); +DECLARE_MSM_GPIO_PINS(99); +DECLARE_MSM_GPIO_PINS(100); +DECLARE_MSM_GPIO_PINS(101); +DECLARE_MSM_GPIO_PINS(102); +DECLARE_MSM_GPIO_PINS(103); +DECLARE_MSM_GPIO_PINS(104); +DECLARE_MSM_GPIO_PINS(105); +DECLARE_MSM_GPIO_PINS(106); +DECLARE_MSM_GPIO_PINS(107); +DECLARE_MSM_GPIO_PINS(108); +DECLARE_MSM_GPIO_PINS(109); +DECLARE_MSM_GPIO_PINS(110); +DECLARE_MSM_GPIO_PINS(111); +DECLARE_MSM_GPIO_PINS(112); +DECLARE_MSM_GPIO_PINS(113); +DECLARE_MSM_GPIO_PINS(114); +DECLARE_MSM_GPIO_PINS(115); +DECLARE_MSM_GPIO_PINS(116); +DECLARE_MSM_GPIO_PINS(117); +DECLARE_MSM_GPIO_PINS(118); +DECLARE_MSM_GPIO_PINS(119); +DECLARE_MSM_GPIO_PINS(120); +DECLARE_MSM_GPIO_PINS(121); +DECLARE_MSM_GPIO_PINS(122); +DECLARE_MSM_GPIO_PINS(123); +DECLARE_MSM_GPIO_PINS(124); +DECLARE_MSM_GPIO_PINS(125); +DECLARE_MSM_GPIO_PINS(126); +DECLARE_MSM_GPIO_PINS(127); +DECLARE_MSM_GPIO_PINS(128); +DECLARE_MSM_GPIO_PINS(129); +DECLARE_MSM_GPIO_PINS(130); +DECLARE_MSM_GPIO_PINS(131); +DECLARE_MSM_GPIO_PINS(132); +DECLARE_MSM_GPIO_PINS(133); +DECLARE_MSM_GPIO_PINS(134); +DECLARE_MSM_GPIO_PINS(135); +DECLARE_MSM_GPIO_PINS(136); +DECLARE_MSM_GPIO_PINS(137); +DECLARE_MSM_GPIO_PINS(138); +DECLARE_MSM_GPIO_PINS(139); +DECLARE_MSM_GPIO_PINS(140); +DECLARE_MSM_GPIO_PINS(141); +DECLARE_MSM_GPIO_PINS(142); +DECLARE_MSM_GPIO_PINS(143); +DECLARE_MSM_GPIO_PINS(144); +DECLARE_MSM_GPIO_PINS(145); +DECLARE_MSM_GPIO_PINS(146); +DECLARE_MSM_GPIO_PINS(147); +DECLARE_MSM_GPIO_PINS(148); +DECLARE_MSM_GPIO_PINS(149); +DECLARE_MSM_GPIO_PINS(150); +DECLARE_MSM_GPIO_PINS(151); +DECLARE_MSM_GPIO_PINS(152); +DECLARE_MSM_GPIO_PINS(153); +DECLARE_MSM_GPIO_PINS(154); +DECLARE_MSM_GPIO_PINS(155); + + +static const unsigned int sdc1_rclk_pins[] = { 157 }; +static const unsigned int sdc1_clk_pins[] = { 158 }; +static const unsigned int sdc1_cmd_pins[] = { 159 }; +static const unsigned int sdc1_data_pins[] = { 160 }; +static const unsigned int sdc2_clk_pins[] = { 161 }; +static const unsigned int sdc2_cmd_pins[] = { 162 }; +static const unsigned int sdc2_data_pins[] = { 163 }; +static const unsigned int ufs_reset_pins[] = { 156 }; + +enum sm6375_functions { + msm_mux_adsp_ext, + msm_mux_agera_pll, + msm_mux_atest_char, + msm_mux_atest_char0, + msm_mux_atest_char1, + msm_mux_atest_char2, + msm_mux_atest_char3, + msm_mux_atest_tsens, + msm_mux_atest_tsens2, + msm_mux_atest_usb1, + msm_mux_atest_usb10, + msm_mux_atest_usb11, + msm_mux_atest_usb12, + msm_mux_atest_usb13, + msm_mux_atest_usb2, + msm_mux_atest_usb20, + msm_mux_atest_usb21, + msm_mux_atest_usb22, + msm_mux_atest_usb23, + msm_mux_audio_ref, + msm_mux_btfm_slimbus, + msm_mux_cam_mclk, + msm_mux_cci_async, + msm_mux_cci_i2c, + msm_mux_cci_timer0, + msm_mux_cci_timer1, + msm_mux_cci_timer2, + msm_mux_cci_timer3, + msm_mux_cci_timer4, + msm_mux_cri_trng, + msm_mux_dbg_out, + msm_mux_ddr_bist, + msm_mux_ddr_pxi0, + msm_mux_ddr_pxi1, + msm_mux_ddr_pxi2, + msm_mux_ddr_pxi3, + msm_mux_dp_hot, + msm_mux_edp_lcd, + msm_mux_gcc_gp1, + msm_mux_gcc_gp2, + msm_mux_gcc_gp3, + msm_mux_gp_pdm0, + msm_mux_gp_pdm1, + msm_mux_gp_pdm2, + msm_mux_gpio, + msm_mux_gps_tx, + msm_mux_ibi_i3c, + msm_mux_jitter_bist, + msm_mux_ldo_en, + msm_mux_ldo_update, + msm_mux_lpass_ext, + msm_mux_m_voc, + msm_mux_mclk, + msm_mux_mdp_vsync, + msm_mux_mdp_vsync0, + msm_mux_mdp_vsync1, + msm_mux_mdp_vsync2, + msm_mux_mdp_vsync3, + msm_mux_mi2s_0, + msm_mux_mi2s_1, + msm_mux_mi2s_2, + msm_mux_mss_lte, + msm_mux_nav_gpio, + msm_mux_nav_pps, + msm_mux_pa_indicator, + msm_mux_phase_flag0, + msm_mux_phase_flag1, + msm_mux_phase_flag10, + msm_mux_phase_flag11, + msm_mux_phase_flag12, + msm_mux_phase_flag13, + msm_mux_phase_flag14, + msm_mux_phase_flag15, + msm_mux_phase_flag16, + msm_mux_phase_flag17, + msm_mux_phase_flag18, + msm_mux_phase_flag19, + msm_mux_phase_flag2, + msm_mux_phase_flag20, + msm_mux_phase_flag21, + msm_mux_phase_flag22, + msm_mux_phase_flag23, + msm_mux_phase_flag24, + msm_mux_phase_flag25, + msm_mux_phase_flag26, + msm_mux_phase_flag27, + msm_mux_phase_flag28, + msm_mux_phase_flag29, + msm_mux_phase_flag3, + msm_mux_phase_flag30, + msm_mux_phase_flag31, + msm_mux_phase_flag4, + msm_mux_phase_flag5, + msm_mux_phase_flag6, + msm_mux_phase_flag7, + msm_mux_phase_flag8, + msm_mux_phase_flag9, + msm_mux_pll_bist, + msm_mux_pll_bypassnl, + msm_mux_pll_clk, + msm_mux_pll_reset, + msm_mux_prng_rosc0, + msm_mux_prng_rosc1, + msm_mux_prng_rosc2, + msm_mux_prng_rosc3, + msm_mux_qdss_cti, + msm_mux_qdss_gpio, + msm_mux_qdss_gpio0, + msm_mux_qdss_gpio1, + msm_mux_qdss_gpio10, + msm_mux_qdss_gpio11, + msm_mux_qdss_gpio12, + msm_mux_qdss_gpio13, + msm_mux_qdss_gpio14, + msm_mux_qdss_gpio15, + msm_mux_qdss_gpio2, + msm_mux_qdss_gpio3, + msm_mux_qdss_gpio4, + msm_mux_qdss_gpio5, + msm_mux_qdss_gpio6, + msm_mux_qdss_gpio7, + msm_mux_qdss_gpio8, + msm_mux_qdss_gpio9, + msm_mux_qlink0_enable, + msm_mux_qlink0_request, + msm_mux_qlink0_wmss, + msm_mux_qlink1_enable, + msm_mux_qlink1_request, + msm_mux_qlink1_wmss, + msm_mux_qup00, + msm_mux_qup01, + msm_mux_qup02, + msm_mux_qup10, + msm_mux_qup11_f1, + msm_mux_qup11_f2, + msm_mux_qup12, + msm_mux_qup13_f1, + msm_mux_qup13_f2, + msm_mux_qup14, + msm_mux_sd_write, + msm_mux_sdc1_tb, + msm_mux_sdc2_tb, + msm_mux_sp_cmu, + msm_mux_tgu_ch0, + msm_mux_tgu_ch1, + msm_mux_tgu_ch2, + msm_mux_tgu_ch3, + msm_mux_tsense_pwm1, + msm_mux_tsense_pwm2, + msm_mux_uim1_clk, + msm_mux_uim1_data, + msm_mux_uim1_present, + msm_mux_uim1_reset, + msm_mux_uim2_clk, + msm_mux_uim2_data, + msm_mux_uim2_present, + msm_mux_uim2_reset, + msm_mux_usb2phy_ac, + msm_mux_usb_phy, + msm_mux_vfr_1, + msm_mux_vsense_trigger, + msm_mux_wlan1_adc0, + msm_mux_wlan1_adc1, + msm_mux_wlan2_adc0, + msm_mux_wlan2_adc1, + msm_mux__, +}; + +static const char * const gpio_groups[] = { + "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7", + "gpio8", "gpio9", "gpio11", "gpio12", "gpio13", "gpio14", "gpio15", + "gpio16", "gpio17", "gpio18", "gpio19", "gpio20", "gpio21", "gpio22", + "gpio23", "gpio24", "gpio25", "gpio26", "gpio27", "gpio28", "gpio29", + "gpio30", "gpio31", "gpio32", "gpio33", "gpio34", "gpio35", "gpio36", + "gpio37", "gpio38", "gpio39", "gpio40", "gpio41", "gpio42", "gpio43", + "gpio44", "gpio45", "gpio46", "gpio47", "gpio48", "gpio49", "gpio50", + "gpio51", "gpio52", "gpio53", "gpio56", "gpio57", "gpio58", "gpio59", + "gpio60", "gpio61", "gpio62", "gpio63", "gpio64", "gpio65", "gpio66", + "gpio67", "gpio68", "gpio69", "gpio75", "gpio76", "gpio77", "gpio78", + "gpio79", "gpio80", "gpio81", "gpio82", "gpio83", "gpio84", "gpio85", + "gpio86", "gpio87", "gpio88", "gpio89", "gpio90", "gpio91", "gpio92", + "gpio93", "gpio94", "gpio95", "gpio96", "gpio97", "gpio98", "gpio99", + "gpio100", "gpio101", "gpio102", "gpio103", "gpio104", "gpio105", + "gpio106", "gpio107", "gpio108", "gpio109", "gpio110", "gpio111", + "gpio112", "gpio113", "gpio114", "gpio115", "gpio116", "gpio117", + "gpio118", "gpio119", "gpio120", "gpio124", "gpio125", "gpio126", + "gpio127", "gpio128", "gpio129", "gpio130", "gpio131", "gpio132", + "gpio133", "gpio134", "gpio135", "gpio136", "gpio141", "gpio142", + "gpio143", "gpio150", "gpio151", "gpio152", "gpio153", "gpio154", + "gpio155", +}; +static const char * const agera_pll_groups[] = { + "gpio89", +}; +static const char * const cci_async_groups[] = { + "gpio35", "gpio36", "gpio48", "gpio52", "gpio53", +}; +static const char * const cci_i2c_groups[] = { + "gpio2", "gpio3", "gpio39", "gpio40", "gpio41", "gpio42", "gpio43", + "gpio44", +}; +static const char * const gps_tx_groups[] = { + "gpio101", "gpio102", "gpio107", "gpio108", +}; +static const char * const gp_pdm0_groups[] = { + "gpio37", "gpio68", +}; +static const char * const gp_pdm1_groups[] = { + "gpio8", "gpio52", +}; +static const char * const gp_pdm2_groups[] = { + "gpio57", +}; +static const char * const jitter_bist_groups[] = { + "gpio90", +}; +static const char * const mclk_groups[] = { + "gpio93", +}; +static const char * const mdp_vsync_groups[] = { + "gpio6", "gpio23", "gpio24", "gpio27", "gpio28", +}; +static const char * const mss_lte_groups[] = { + "gpio65", "gpio66", +}; +static const char * const nav_pps_groups[] = { + "gpio101", "gpio101", "gpio102", "gpio102", +}; +static const char * const pll_bist_groups[] = { + "gpio27", +}; +static const char * const qlink0_wmss_groups[] = { + "gpio103", +}; +static const char * const qlink1_wmss_groups[] = { + "gpio106", +}; +static const char * const usb_phy_groups[] = { + "gpio124", +}; +static const char * const adsp_ext_groups[] = { + "gpio87", +}; +static const char * const atest_char_groups[] = { + "gpio95", +}; +static const char * const atest_char0_groups[] = { + "gpio96", +}; +static const char * const atest_char1_groups[] = { + "gpio97", +}; +static const char * const atest_char2_groups[] = { + "gpio98", +}; +static const char * const atest_char3_groups[] = { + "gpio99", +}; +static const char * const atest_tsens_groups[] = { + "gpio92", +}; +static const char * const atest_tsens2_groups[] = { + "gpio93", +}; +static const char * const atest_usb1_groups[] = { + "gpio83", +}; +static const char * const atest_usb10_groups[] = { + "gpio84", +}; +static const char * const atest_usb11_groups[] = { + "gpio85", +}; +static const char * const atest_usb12_groups[] = { + "gpio86", +}; +static const char * const atest_usb13_groups[] = { + "gpio87", +}; +static const char * const atest_usb2_groups[] = { + "gpio88", +}; +static const char * const atest_usb20_groups[] = { + "gpio89", +}; +static const char * const atest_usb21_groups[] = { + "gpio90", +}; +static const char * const atest_usb22_groups[] = { + "gpio91", +}; +static const char * const atest_usb23_groups[] = { + "gpio92", +}; +static const char * const audio_ref_groups[] = { + "gpio60", +}; +static const char * const btfm_slimbus_groups[] = { + "gpio67", "gpio68", "gpio86", "gpio87", +}; +static const char * const cam_mclk_groups[] = { + "gpio29", "gpio30", "gpio31", "gpio32", "gpio33", +}; +static const char * const cci_timer0_groups[] = { + "gpio34", +}; +static const char * const cci_timer1_groups[] = { + "gpio35", +}; +static const char * const cci_timer2_groups[] = { + "gpio36", +}; +static const char * const cci_timer3_groups[] = { + "gpio37", +}; +static const char * const cci_timer4_groups[] = { + "gpio38", +}; +static const char * const cri_trng_groups[] = { + "gpio0", "gpio1", "gpio2", +}; +static const char * const dbg_out_groups[] = { + "gpio3", +}; +static const char * const ddr_bist_groups[] = { + "gpio19", "gpio20", "gpio21", "gpio22", +}; +static const char * const ddr_pxi0_groups[] = { + "gpio86", "gpio90", +}; +static const char * const ddr_pxi1_groups[] = { + "gpio87", "gpio91", +}; +static const char * const ddr_pxi2_groups[] = { + "gpio88", "gpio92", +}; +static const char * const ddr_pxi3_groups[] = { + "gpio89", "gpio93", +}; +static const char * const dp_hot_groups[] = { + "gpio12", "gpio118", +}; +static const char * const edp_lcd_groups[] = { + "gpio23", +}; +static const char * const gcc_gp1_groups[] = { + "gpio48", "gpio58", +}; +static const char * const gcc_gp2_groups[] = { + "gpio21", +}; +static const char * const gcc_gp3_groups[] = { + "gpio22", +}; +static const char * const ibi_i3c_groups[] = { + "gpio0", "gpio1", +}; +static const char * const ldo_en_groups[] = { + "gpio95", +}; +static const char * const ldo_update_groups[] = { + "gpio96", +}; +static const char * const lpass_ext_groups[] = { + "gpio60", "gpio93", +}; +static const char * const m_voc_groups[] = { + "gpio12", +}; +static const char * const mdp_vsync0_groups[] = { + "gpio47", +}; +static const char * const mdp_vsync1_groups[] = { + "gpio48", +}; +static const char * const mdp_vsync2_groups[] = { + "gpio56", +}; +static const char * const mdp_vsync3_groups[] = { + "gpio57", +}; +static const char * const mi2s_0_groups[] = { + "gpio88", "gpio89", "gpio90", "gpio91", +}; +static const char * const mi2s_1_groups[] = { + "gpio67", "gpio68", "gpio86", "gpio87", +}; +static const char * const mi2s_2_groups[] = { + "gpio60", +}; +static const char * const nav_gpio_groups[] = { + "gpio101", "gpio102", +}; +static const char * const pa_indicator_groups[] = { + "gpio118", +}; +static const char * const phase_flag0_groups[] = { + "gpio12", +}; +static const char * const phase_flag1_groups[] = { + "gpio17", +}; +static const char * const phase_flag10_groups[] = { + "gpio41", +}; +static const char * const phase_flag11_groups[] = { + "gpio42", +}; +static const char * const phase_flag12_groups[] = { + "gpio43", +}; +static const char * const phase_flag13_groups[] = { + "gpio44", +}; +static const char * const phase_flag14_groups[] = { + "gpio45", +}; +static const char * const phase_flag15_groups[] = { + "gpio46", +}; +static const char * const phase_flag16_groups[] = { + "gpio47", +}; +static const char * const phase_flag17_groups[] = { + "gpio48", +}; +static const char * const phase_flag18_groups[] = { + "gpio49", +}; +static const char * const phase_flag19_groups[] = { + "gpio50", +}; +static const char * const phase_flag2_groups[] = { + "gpio18", +}; +static const char * const phase_flag20_groups[] = { + "gpio51", +}; +static const char * const phase_flag21_groups[] = { + "gpio52", +}; +static const char * const phase_flag22_groups[] = { + "gpio53", +}; +static const char * const phase_flag23_groups[] = { + "gpio56", +}; +static const char * const phase_flag24_groups[] = { + "gpio57", +}; +static const char * const phase_flag25_groups[] = { + "gpio60", +}; +static const char * const phase_flag26_groups[] = { + "gpio61", +}; +static const char * const phase_flag27_groups[] = { + "gpio62", +}; +static const char * const phase_flag28_groups[] = { + "gpio63", +}; +static const char * const phase_flag29_groups[] = { + "gpio64", +}; +static const char * const phase_flag3_groups[] = { + "gpio34", +}; +static const char * const phase_flag30_groups[] = { + "gpio67", +}; +static const char * const phase_flag31_groups[] = { + "gpio68", +}; +static const char * const phase_flag4_groups[] = { + "gpio35", +}; +static const char * const phase_flag5_groups[] = { + "gpio36", +}; +static const char * const phase_flag6_groups[] = { + "gpio37", +}; +static const char * const phase_flag7_groups[] = { + "gpio38", +}; +static const char * const phase_flag8_groups[] = { + "gpio39", +}; +static const char * const phase_flag9_groups[] = { + "gpio40", +}; +static const char * const pll_bypassnl_groups[] = { + "gpio13", +}; +static const char * const pll_clk_groups[] = { + "gpio98", +}; +static const char * const pll_reset_groups[] = { + "gpio14", +}; +static const char * const prng_rosc0_groups[] = { + "gpio97", +}; +static const char * const prng_rosc1_groups[] = { + "gpio98", +}; +static const char * const prng_rosc2_groups[] = { + "gpio99", +}; +static const char * const prng_rosc3_groups[] = { + "gpio100", +}; +static const char * const qdss_cti_groups[] = { + "gpio2", "gpio3", "gpio6", "gpio7", "gpio61", "gpio62", "gpio86", + "gpio87", +}; +static const char * const qdss_gpio_groups[] = { + "gpio8", "gpio9", "gpio63", "gpio64", +}; +static const char * const qdss_gpio0_groups[] = { + "gpio39", "gpio65", +}; +static const char * const qdss_gpio1_groups[] = { + "gpio40", "gpio66", +}; +static const char * const qdss_gpio10_groups[] = { + "gpio50", "gpio56", +}; +static const char * const qdss_gpio11_groups[] = { + "gpio51", "gpio57", +}; +static const char * const qdss_gpio12_groups[] = { + "gpio34", "gpio52", +}; +static const char * const qdss_gpio13_groups[] = { + "gpio35", "gpio53", +}; +static const char * const qdss_gpio14_groups[] = { + "gpio27", "gpio36", +}; +static const char * const qdss_gpio15_groups[] = { + "gpio28", "gpio37", +}; +static const char * const qdss_gpio2_groups[] = { + "gpio38", "gpio41", +}; +static const char * const qdss_gpio3_groups[] = { + "gpio42", "gpio47", +}; +static const char * const qdss_gpio4_groups[] = { + "gpio43", "gpio88", +}; +static const char * const qdss_gpio5_groups[] = { + "gpio44", "gpio89", +}; +static const char * const qdss_gpio6_groups[] = { + "gpio45", "gpio90", +}; +static const char * const qdss_gpio7_groups[] = { + "gpio46", "gpio91", +}; +static const char * const qdss_gpio8_groups[] = { + "gpio48", "gpio92", +}; +static const char * const qdss_gpio9_groups[] = { + "gpio49", "gpio93", +}; +static const char * const qlink0_enable_groups[] = { + "gpio105", +}; +static const char * const qlink0_request_groups[] = { + "gpio104", +}; +static const char * const qlink1_enable_groups[] = { + "gpio108", +}; +static const char * const qlink1_request_groups[] = { + "gpio107", +}; +static const char * const qup00_groups[] = { + "gpio0", "gpio1", "gpio2", "gpio3", +}; +static const char * const qup01_groups[] = { + "gpio61", "gpio62", "gpio63", "gpio64", +}; +static const char * const qup02_groups[] = { + "gpio45", "gpio46", "gpio48", "gpio56", "gpio57", +}; +static const char * const qup10_groups[] = { + "gpio13", "gpio14", "gpio15", "gpio16", "gpio17", +}; +static const char * const qup11_f1_groups[] = { + "gpio27", "gpio28", +}; +static const char * const qup11_f2_groups[] = { + "gpio27", "gpio28", +}; + +static const char * const qup12_groups[] = { + "gpio19", "gpio19", "gpio20", "gpio20", +}; +static const char * const qup13_f1_groups[] = { + "gpio25", "gpio26", +}; +static const char * const qup13_f2_groups[] = { + "gpio25", "gpio26", +}; +static const char * const qup14_groups[] = { + "gpio4", "gpio4", "gpio5", "gpio5", +}; +static const char * const sd_write_groups[] = { + "gpio85", +}; +static const char * const sdc1_tb_groups[] = { + "gpio4", +}; +static const char * const sdc2_tb_groups[] = { + "gpio5", +}; +static const char * const sp_cmu_groups[] = { + "gpio3", +}; +static const char * const tgu_ch0_groups[] = { + "gpio61", +}; +static const char * const tgu_ch1_groups[] = { + "gpio62", +}; +static const char * const tgu_ch2_groups[] = { + "gpio63", +}; +static const char * const tgu_ch3_groups[] = { + "gpio64", +}; +static const char * const tsense_pwm1_groups[] = { + "gpio88", +}; +static const char * const tsense_pwm2_groups[] = { + "gpio88", +}; +static const char * const uim1_clk_groups[] = { + "gpio80", +}; +static const char * const uim1_data_groups[] = { + "gpio79", +}; +static const char * const uim1_present_groups[] = { + "gpio82", +}; +static const char * const uim1_reset_groups[] = { + "gpio81", +}; +static const char * const uim2_clk_groups[] = { + "gpio76", +}; +static const char * const uim2_data_groups[] = { + "gpio75", +}; +static const char * const uim2_present_groups[] = { + "gpio78", +}; +static const char * const uim2_reset_groups[] = { + "gpio77", +}; +static const char * const usb2phy_ac_groups[] = { + "gpio47", +}; +static const char * const vfr_1_groups[] = { + "gpio49", +}; +static const char * const vsense_trigger_groups[] = { + "gpio89", +}; +static const char * const wlan1_adc0_groups[] = { + "gpio90", +}; +static const char * const wlan1_adc1_groups[] = { + "gpio92", +}; +static const char * const wlan2_adc0_groups[] = { + "gpio91", +}; +static const char * const wlan2_adc1_groups[] = { + "gpio93", +}; + +static const struct pinfunction sm6375_functions[] = { + MSM_PIN_FUNCTION(adsp_ext), + MSM_PIN_FUNCTION(agera_pll), + MSM_PIN_FUNCTION(atest_char), + MSM_PIN_FUNCTION(atest_char0), + MSM_PIN_FUNCTION(atest_char1), + MSM_PIN_FUNCTION(atest_char2), + MSM_PIN_FUNCTION(atest_char3), + MSM_PIN_FUNCTION(atest_tsens), + MSM_PIN_FUNCTION(atest_tsens2), + MSM_PIN_FUNCTION(atest_usb1), + MSM_PIN_FUNCTION(atest_usb10), + MSM_PIN_FUNCTION(atest_usb11), + MSM_PIN_FUNCTION(atest_usb12), + MSM_PIN_FUNCTION(atest_usb13), + MSM_PIN_FUNCTION(atest_usb2), + MSM_PIN_FUNCTION(atest_usb20), + MSM_PIN_FUNCTION(atest_usb21), + MSM_PIN_FUNCTION(atest_usb22), + MSM_PIN_FUNCTION(atest_usb23), + MSM_PIN_FUNCTION(audio_ref), + MSM_PIN_FUNCTION(btfm_slimbus), + MSM_PIN_FUNCTION(cam_mclk), + MSM_PIN_FUNCTION(cci_async), + MSM_PIN_FUNCTION(cci_i2c), + MSM_PIN_FUNCTION(cci_timer0), + MSM_PIN_FUNCTION(cci_timer1), + MSM_PIN_FUNCTION(cci_timer2), + MSM_PIN_FUNCTION(cci_timer3), + MSM_PIN_FUNCTION(cci_timer4), + MSM_PIN_FUNCTION(cri_trng), + MSM_PIN_FUNCTION(dbg_out), + MSM_PIN_FUNCTION(ddr_bist), + MSM_PIN_FUNCTION(ddr_pxi0), + MSM_PIN_FUNCTION(ddr_pxi1), + MSM_PIN_FUNCTION(ddr_pxi2), + MSM_PIN_FUNCTION(ddr_pxi3), + MSM_PIN_FUNCTION(dp_hot), + MSM_PIN_FUNCTION(edp_lcd), + MSM_PIN_FUNCTION(gcc_gp1), + MSM_PIN_FUNCTION(gcc_gp2), + MSM_PIN_FUNCTION(gcc_gp3), + MSM_PIN_FUNCTION(gp_pdm0), + MSM_PIN_FUNCTION(gp_pdm1), + MSM_PIN_FUNCTION(gp_pdm2), + MSM_PIN_FUNCTION(gpio), + MSM_PIN_FUNCTION(gps_tx), + MSM_PIN_FUNCTION(ibi_i3c), + MSM_PIN_FUNCTION(jitter_bist), + MSM_PIN_FUNCTION(ldo_en), + MSM_PIN_FUNCTION(ldo_update), + MSM_PIN_FUNCTION(lpass_ext), + MSM_PIN_FUNCTION(m_voc), + MSM_PIN_FUNCTION(mclk), + MSM_PIN_FUNCTION(mdp_vsync), + MSM_PIN_FUNCTION(mdp_vsync0), + MSM_PIN_FUNCTION(mdp_vsync1), + MSM_PIN_FUNCTION(mdp_vsync2), + MSM_PIN_FUNCTION(mdp_vsync3), + MSM_PIN_FUNCTION(mi2s_0), + MSM_PIN_FUNCTION(mi2s_1), + MSM_PIN_FUNCTION(mi2s_2), + MSM_PIN_FUNCTION(mss_lte), + MSM_PIN_FUNCTION(nav_gpio), + MSM_PIN_FUNCTION(nav_pps), + MSM_PIN_FUNCTION(pa_indicator), + MSM_PIN_FUNCTION(phase_flag0), + MSM_PIN_FUNCTION(phase_flag1), + MSM_PIN_FUNCTION(phase_flag10), + MSM_PIN_FUNCTION(phase_flag11), + MSM_PIN_FUNCTION(phase_flag12), + MSM_PIN_FUNCTION(phase_flag13), + MSM_PIN_FUNCTION(phase_flag14), + MSM_PIN_FUNCTION(phase_flag15), + MSM_PIN_FUNCTION(phase_flag16), + MSM_PIN_FUNCTION(phase_flag17), + MSM_PIN_FUNCTION(phase_flag18), + MSM_PIN_FUNCTION(phase_flag19), + MSM_PIN_FUNCTION(phase_flag2), + MSM_PIN_FUNCTION(phase_flag20), + MSM_PIN_FUNCTION(phase_flag21), + MSM_PIN_FUNCTION(phase_flag22), + MSM_PIN_FUNCTION(phase_flag23), + MSM_PIN_FUNCTION(phase_flag24), + MSM_PIN_FUNCTION(phase_flag25), + MSM_PIN_FUNCTION(phase_flag26), + MSM_PIN_FUNCTION(phase_flag27), + MSM_PIN_FUNCTION(phase_flag28), + MSM_PIN_FUNCTION(phase_flag29), + MSM_PIN_FUNCTION(phase_flag3), + MSM_PIN_FUNCTION(phase_flag30), + MSM_PIN_FUNCTION(phase_flag31), + MSM_PIN_FUNCTION(phase_flag4), + MSM_PIN_FUNCTION(phase_flag5), + MSM_PIN_FUNCTION(phase_flag6), + MSM_PIN_FUNCTION(phase_flag7), + MSM_PIN_FUNCTION(phase_flag8), + MSM_PIN_FUNCTION(phase_flag9), + MSM_PIN_FUNCTION(pll_bist), + MSM_PIN_FUNCTION(pll_bypassnl), + MSM_PIN_FUNCTION(pll_clk), + MSM_PIN_FUNCTION(pll_reset), + MSM_PIN_FUNCTION(prng_rosc0), + MSM_PIN_FUNCTION(prng_rosc1), + MSM_PIN_FUNCTION(prng_rosc2), + MSM_PIN_FUNCTION(prng_rosc3), + MSM_PIN_FUNCTION(qdss_cti), + MSM_PIN_FUNCTION(qdss_gpio), + MSM_PIN_FUNCTION(qdss_gpio0), + MSM_PIN_FUNCTION(qdss_gpio1), + MSM_PIN_FUNCTION(qdss_gpio10), + MSM_PIN_FUNCTION(qdss_gpio11), + MSM_PIN_FUNCTION(qdss_gpio12), + MSM_PIN_FUNCTION(qdss_gpio13), + MSM_PIN_FUNCTION(qdss_gpio14), + MSM_PIN_FUNCTION(qdss_gpio15), + MSM_PIN_FUNCTION(qdss_gpio2), + MSM_PIN_FUNCTION(qdss_gpio3), + MSM_PIN_FUNCTION(qdss_gpio4), + MSM_PIN_FUNCTION(qdss_gpio5), + MSM_PIN_FUNCTION(qdss_gpio6), + MSM_PIN_FUNCTION(qdss_gpio7), + MSM_PIN_FUNCTION(qdss_gpio8), + MSM_PIN_FUNCTION(qdss_gpio9), + MSM_PIN_FUNCTION(qlink0_enable), + MSM_PIN_FUNCTION(qlink0_request), + MSM_PIN_FUNCTION(qlink0_wmss), + MSM_PIN_FUNCTION(qlink1_enable), + MSM_PIN_FUNCTION(qlink1_request), + MSM_PIN_FUNCTION(qlink1_wmss), + MSM_PIN_FUNCTION(qup00), + MSM_PIN_FUNCTION(qup01), + MSM_PIN_FUNCTION(qup02), + MSM_PIN_FUNCTION(qup10), + MSM_PIN_FUNCTION(qup11_f1), + MSM_PIN_FUNCTION(qup11_f2), + MSM_PIN_FUNCTION(qup12), + MSM_PIN_FUNCTION(qup13_f1), + MSM_PIN_FUNCTION(qup13_f2), + MSM_PIN_FUNCTION(qup14), + MSM_PIN_FUNCTION(sd_write), + MSM_PIN_FUNCTION(sdc1_tb), + MSM_PIN_FUNCTION(sdc2_tb), + MSM_PIN_FUNCTION(sp_cmu), + MSM_PIN_FUNCTION(tgu_ch0), + MSM_PIN_FUNCTION(tgu_ch1), + MSM_PIN_FUNCTION(tgu_ch2), + MSM_PIN_FUNCTION(tgu_ch3), + MSM_PIN_FUNCTION(tsense_pwm1), + MSM_PIN_FUNCTION(tsense_pwm2), + MSM_PIN_FUNCTION(uim1_clk), + MSM_PIN_FUNCTION(uim1_data), + MSM_PIN_FUNCTION(uim1_present), + MSM_PIN_FUNCTION(uim1_reset), + MSM_PIN_FUNCTION(uim2_clk), + MSM_PIN_FUNCTION(uim2_data), + MSM_PIN_FUNCTION(uim2_present), + MSM_PIN_FUNCTION(uim2_reset), + MSM_PIN_FUNCTION(usb2phy_ac), + MSM_PIN_FUNCTION(usb_phy), + MSM_PIN_FUNCTION(vfr_1), + MSM_PIN_FUNCTION(vsense_trigger), + MSM_PIN_FUNCTION(wlan1_adc0), + MSM_PIN_FUNCTION(wlan1_adc1), + MSM_PIN_FUNCTION(wlan2_adc0), + MSM_PIN_FUNCTION(wlan2_adc1), +}; + +/* + * Every pin is maintained as a single group, and missing or non-existing pin + * would be maintained as dummy group to synchronize pin group index with + * pin descriptor registered with pinctrl core. + * Clients would not be able to request these dummy pin groups. + */ +static const struct msm_pingroup sm6375_groups[] = { + [0] = PINGROUP(0, ibi_i3c, qup00, cri_trng, _, _, _, _, _, _), + [1] = PINGROUP(1, ibi_i3c, qup00, cri_trng, _, _, _, _, _, _), + [2] = PINGROUP(2, qup00, cci_i2c, cri_trng, qdss_cti, _, _, _, _, _), + [3] = PINGROUP(3, qup00, cci_i2c, sp_cmu, dbg_out, qdss_cti, _, _, _, _), + [4] = PINGROUP(4, qup14, qup14, sdc1_tb, _, _, _, _, _, _), + [5] = PINGROUP(5, qup14, qup14, sdc2_tb, _, _, _, _, _, _), + [6] = PINGROUP(6, mdp_vsync, qdss_cti, _, _, _, _, _, _, _), + [7] = PINGROUP(7, qdss_cti, _, _, _, _, _, _, _, _), + [8] = PINGROUP(8, gp_pdm1, qdss_gpio, _, _, _, _, _, _, _), + [9] = PINGROUP(9, qdss_gpio, _, _, _, _, _, _, _, _), + [10] = PINGROUP(10, _, _, _, _, _, _, _, _, _), + [11] = PINGROUP(11, _, _, _, _, _, _, _, _, _), + [12] = PINGROUP(12, m_voc, dp_hot, _, phase_flag0, _, _, _, _, _), + [13] = PINGROUP(13, qup10, pll_bypassnl, _, _, _, _, _, _, _), + [14] = PINGROUP(14, qup10, pll_reset, _, _, _, _, _, _, _), + [15] = PINGROUP(15, qup10, _, _, _, _, _, _, _, _), + [16] = PINGROUP(16, qup10, _, _, _, _, _, _, _, _), + [17] = PINGROUP(17, _, phase_flag1, qup10, _, _, _, _, _, _), + [18] = PINGROUP(18, _, phase_flag2, _, _, _, _, _, _, _), + [19] = PINGROUP(19, qup12, qup12, ddr_bist, _, _, _, _, _, _), + [20] = PINGROUP(20, qup12, qup12, ddr_bist, _, _, _, _, _, _), + [21] = PINGROUP(21, gcc_gp2, ddr_bist, _, _, _, _, _, _, _), + [22] = PINGROUP(22, gcc_gp3, ddr_bist, _, _, _, _, _, _, _), + [23] = PINGROUP(23, mdp_vsync, edp_lcd, _, _, _, _, _, _, _), + [24] = PINGROUP(24, mdp_vsync, _, _, _, _, _, _, _, _), + [25] = PINGROUP(25, qup13_f1, qup13_f2, _, _, _, _, _, _, _), + [26] = PINGROUP(26, qup13_f1, qup13_f2, _, _, _, _, _, _, _), + [27] = PINGROUP(27, qup11_f1, qup11_f2, mdp_vsync, pll_bist, _, qdss_gpio14, _, _, _), + [28] = PINGROUP(28, qup11_f1, qup11_f2, mdp_vsync, _, qdss_gpio15, _, _, _, _), + [29] = PINGROUP(29, cam_mclk, _, _, _, _, _, _, _, _), + [30] = PINGROUP(30, cam_mclk, _, _, _, _, _, _, _, _), + [31] = PINGROUP(31, cam_mclk, _, _, _, _, _, _, _, _), + [32] = PINGROUP(32, cam_mclk, _, _, _, _, _, _, _, _), + [33] = PINGROUP(33, cam_mclk, _, _, _, _, _, _, _, _), + [34] = PINGROUP(34, cci_timer0, _, phase_flag3, qdss_gpio12, _, _, _, _, _), + [35] = PINGROUP(35, cci_timer1, cci_async, _, phase_flag4, qdss_gpio13, _, _, _, _), + [36] = PINGROUP(36, cci_timer2, cci_async, _, phase_flag5, qdss_gpio14, _, _, _, _), + [37] = PINGROUP(37, cci_timer3, gp_pdm0, _, phase_flag6, qdss_gpio15, _, _, _, _), + [38] = PINGROUP(38, cci_timer4, _, phase_flag7, qdss_gpio2, _, _, _, _, _), + [39] = PINGROUP(39, cci_i2c, _, phase_flag8, qdss_gpio0, _, _, _, _, _), + [40] = PINGROUP(40, cci_i2c, _, phase_flag9, qdss_gpio1, _, _, _, _, _), + [41] = PINGROUP(41, cci_i2c, _, phase_flag10, qdss_gpio2, _, _, _, _, _), + [42] = PINGROUP(42, cci_i2c, _, phase_flag11, qdss_gpio3, _, _, _, _, _), + [43] = PINGROUP(43, cci_i2c, _, phase_flag12, qdss_gpio4, _, _, _, _, _), + [44] = PINGROUP(44, cci_i2c, _, phase_flag13, qdss_gpio5, _, _, _, _, _), + [45] = PINGROUP(45, qup02, _, phase_flag14, qdss_gpio6, _, _, _, _, _), + [46] = PINGROUP(46, qup02, _, phase_flag15, qdss_gpio7, _, _, _, _, _), + [47] = PINGROUP(47, mdp_vsync0, _, phase_flag16, qdss_gpio3, _, _, usb2phy_ac, _, _), + [48] = PINGROUP(48, cci_async, mdp_vsync1, gcc_gp1, _, phase_flag17, qdss_gpio8, qup02, + _, _), + [49] = PINGROUP(49, vfr_1, _, phase_flag18, qdss_gpio9, _, _, _, _, _), + [50] = PINGROUP(50, _, phase_flag19, qdss_gpio10, _, _, _, _, _, _), + [51] = PINGROUP(51, _, phase_flag20, qdss_gpio11, _, _, _, _, _, _), + [52] = PINGROUP(52, cci_async, gp_pdm1, _, phase_flag21, qdss_gpio12, _, _, _, _), + [53] = PINGROUP(53, cci_async, _, phase_flag22, qdss_gpio13, _, _, _, _, _), + [54] = PINGROUP(54, _, _, _, _, _, _, _, _, _), + [55] = PINGROUP(55, _, _, _, _, _, _, _, _, _), + [56] = PINGROUP(56, qup02, mdp_vsync2, _, phase_flag23, qdss_gpio10, _, _, _, _), + [57] = PINGROUP(57, qup02, mdp_vsync3, gp_pdm2, _, phase_flag24, qdss_gpio11, _, _, _), + [58] = PINGROUP(58, gcc_gp1, _, _, _, _, _, _, _, _), + [59] = PINGROUP(59, _, _, _, _, _, _, _, _, _), + [60] = PINGROUP(60, audio_ref, lpass_ext, mi2s_2, _, phase_flag25, _, _, _, _), + [61] = PINGROUP(61, qup01, tgu_ch0, _, phase_flag26, qdss_cti, _, _, _, _), + [62] = PINGROUP(62, qup01, tgu_ch1, _, phase_flag27, qdss_cti, _, _, _, _), + [63] = PINGROUP(63, qup01, tgu_ch2, _, phase_flag28, qdss_gpio, _, _, _, _), + [64] = PINGROUP(64, qup01, tgu_ch3, _, phase_flag29, qdss_gpio, _, _, _, _), + [65] = PINGROUP(65, mss_lte, _, qdss_gpio0, _, _, _, _, _, _), + [66] = PINGROUP(66, mss_lte, _, qdss_gpio1, _, _, _, _, _, _), + [67] = PINGROUP(67, btfm_slimbus, mi2s_1, _, phase_flag30, _, _, _, _, _), + [68] = PINGROUP(68, btfm_slimbus, mi2s_1, gp_pdm0, _, phase_flag31, _, _, _, _), + [69] = PINGROUP(69, _, _, _, _, _, _, _, _, _), + [70] = PINGROUP(70, _, _, _, _, _, _, _, _, _), + [71] = PINGROUP(71, _, _, _, _, _, _, _, _, _), + [72] = PINGROUP(72, _, _, _, _, _, _, _, _, _), + [73] = PINGROUP(73, _, _, _, _, _, _, _, _, _), + [74] = PINGROUP(74, _, _, _, _, _, _, _, _, _), + [75] = PINGROUP(75, uim2_data, _, _, _, _, _, _, _, _), + [76] = PINGROUP(76, uim2_clk, _, _, _, _, _, _, _, _), + [77] = PINGROUP(77, uim2_reset, _, _, _, _, _, _, _, _), + [78] = PINGROUP(78, uim2_present, _, _, _, _, _, _, _, _), + [79] = PINGROUP(79, uim1_data, _, _, _, _, _, _, _, _), + [80] = PINGROUP(80, uim1_clk, _, _, _, _, _, _, _, _), + [81] = PINGROUP(81, uim1_reset, _, _, _, _, _, _, _, _), + [82] = PINGROUP(82, uim1_present, _, _, _, _, _, _, _, _), + [83] = PINGROUP(83, atest_usb1, _, _, _, _, _, _, _, _), + [84] = PINGROUP(84, _, atest_usb10, _, _, _, _, _, _, _), + [85] = PINGROUP(85, sd_write, _, atest_usb11, _, _, _, _, _, _), + [86] = PINGROUP(86, btfm_slimbus, mi2s_1, _, qdss_cti, atest_usb12, ddr_pxi0, _, _, _), + [87] = PINGROUP(87, btfm_slimbus, mi2s_1, adsp_ext, _, qdss_cti, atest_usb13, ddr_pxi1, _, + _), + [88] = PINGROUP(88, mi2s_0, _, qdss_gpio4, _, atest_usb2, ddr_pxi2, tsense_pwm1, + tsense_pwm2, _), + [89] = PINGROUP(89, mi2s_0, agera_pll, _, qdss_gpio5, _, vsense_trigger, atest_usb20, + ddr_pxi3, _), + [90] = PINGROUP(90, mi2s_0, jitter_bist, _, qdss_gpio6, _, wlan1_adc0, atest_usb21, + ddr_pxi0, _), + [91] = PINGROUP(91, mi2s_0, _, qdss_gpio7, _, wlan2_adc0, atest_usb22, ddr_pxi1, _, _), + [92] = PINGROUP(92, _, qdss_gpio8, atest_tsens, wlan1_adc1, atest_usb23, ddr_pxi2, _, _, + _), + [93] = PINGROUP(93, mclk, lpass_ext, _, qdss_gpio9, atest_tsens2, wlan2_adc1, ddr_pxi3, + _, _), + [94] = PINGROUP(94, _, _, _, _, _, _, _, _, _), + [95] = PINGROUP(95, ldo_en, _, atest_char, _, _, _, _, _, _), + [96] = PINGROUP(96, ldo_update, _, atest_char0, _, _, _, _, _, _), + [97] = PINGROUP(97, prng_rosc0, _, atest_char1, _, _, _, _, _, _), + [98] = PINGROUP(98, _, atest_char2, _, _, prng_rosc1, pll_clk, _, _, _), + [99] = PINGROUP(99, _, atest_char3, _, _, prng_rosc2, _, _, _, _), + [100] = PINGROUP(100, _, _, prng_rosc3, _, _, _, _, _, _), + [101] = PINGROUP(101, nav_gpio, nav_pps, nav_pps, gps_tx, _, _, _, _, _), + [102] = PINGROUP(102, nav_gpio, nav_pps, nav_pps, gps_tx, _, _, _, _, _), + [103] = PINGROUP(103, qlink0_wmss, _, _, _, _, _, _, _, _), + [104] = PINGROUP(104, qlink0_request, _, _, _, _, _, _, _, _), + [105] = PINGROUP(105, qlink0_enable, _, _, _, _, _, _, _, _), + [106] = PINGROUP(106, qlink1_wmss, _, _, _, _, _, _, _, _), + [107] = PINGROUP(107, qlink1_request, gps_tx, _, _, _, _, _, _, _), + [108] = PINGROUP(108, qlink1_enable, gps_tx, _, _, _, _, _, _, _), + [109] = PINGROUP(109, _, _, _, _, _, _, _, _, _), + [110] = PINGROUP(110, _, _, _, _, _, _, _, _, _), + [111] = PINGROUP(111, _, _, _, _, _, _, _, _, _), + [112] = PINGROUP(112, _, _, _, _, _, _, _, _, _), + [113] = PINGROUP(113, _, _, _, _, _, _, _, _, _), + [114] = PINGROUP(114, _, _, _, _, _, _, _, _, _), + [115] = PINGROUP(115, _, _, _, _, _, _, _, _, _), + [116] = PINGROUP(116, _, _, _, _, _, _, _, _, _), + [117] = PINGROUP(117, _, _, _, _, _, _, _, _, _), + [118] = PINGROUP(118, _, _, pa_indicator, dp_hot, _, _, _, _, _), + [119] = PINGROUP(119, _, _, _, _, _, _, _, _, _), + [120] = PINGROUP(120, _, _, _, _, _, _, _, _, _), + [121] = PINGROUP(121, _, _, _, _, _, _, _, _, _), + [122] = PINGROUP(122, _, _, _, _, _, _, _, _, _), + [123] = PINGROUP(123, _, _, _, _, _, _, _, _, _), + [124] = PINGROUP(124, usb_phy, _, _, _, _, _, _, _, _), + [125] = PINGROUP(125, _, _, _, _, _, _, _, _, _), + [126] = PINGROUP(126, _, _, _, _, _, _, _, _, _), + [127] = PINGROUP(127, _, _, _, _, _, _, _, _, _), + [128] = PINGROUP(128, _, _, _, _, _, _, _, _, _), + [129] = PINGROUP(129, _, _, _, _, _, _, _, _, _), + [130] = PINGROUP(130, _, _, _, _, _, _, _, _, _), + [131] = PINGROUP(131, _, _, _, _, _, _, _, _, _), + [132] = PINGROUP(132, _, _, _, _, _, _, _, _, _), + [133] = PINGROUP(133, _, _, _, _, _, _, _, _, _), + [134] = PINGROUP(134, _, _, _, _, _, _, _, _, _), + [135] = PINGROUP(135, _, _, _, _, _, _, _, _, _), + [136] = PINGROUP(136, _, _, _, _, _, _, _, _, _), + [137] = PINGROUP(137, _, _, _, _, _, _, _, _, _), + [138] = PINGROUP(138, _, _, _, _, _, _, _, _, _), + [139] = PINGROUP(139, _, _, _, _, _, _, _, _, _), + [140] = PINGROUP(140, _, _, _, _, _, _, _, _, _), + [141] = PINGROUP(141, _, _, _, _, _, _, _, _, _), + [142] = PINGROUP(142, _, _, _, _, _, _, _, _, _), + [143] = PINGROUP(143, _, _, _, _, _, _, _, _, _), + [144] = PINGROUP(144, _, _, _, _, _, _, _, _, _), + [145] = PINGROUP(145, _, _, _, _, _, _, _, _, _), + [146] = PINGROUP(146, _, _, _, _, _, _, _, _, _), + [147] = PINGROUP(147, _, _, _, _, _, _, _, _, _), + [148] = PINGROUP(148, _, _, _, _, _, _, _, _, _), + [149] = PINGROUP(149, _, _, _, _, _, _, _, _, _), + [150] = PINGROUP(150, _, _, _, _, _, _, _, _, _), + [151] = PINGROUP(151, _, _, _, _, _, _, _, _, _), + [152] = PINGROUP(152, _, _, _, _, _, _, _, _, _), + [153] = PINGROUP(153, _, _, _, _, _, _, _, _, _), + [154] = PINGROUP(154, _, _, _, _, _, _, _, _, _), + [155] = PINGROUP(155, _, _, _, _, _, _, _, _, _), + [156] = UFS_RESET(ufs_reset, 0x1ae000), + [157] = SDC_PINGROUP(sdc1_rclk, 0x1a1000, 0, 0), + [158] = SDC_PINGROUP(sdc1_clk, 0x1a0000, 13, 6), + [159] = SDC_PINGROUP(sdc1_cmd, 0x1a0000, 11, 3), + [160] = SDC_PINGROUP(sdc1_data, 0x1a0000, 9, 0), + [161] = SDC_PINGROUP(sdc2_clk, 0x1a2000, 14, 6), + [162] = SDC_PINGROUP(sdc2_cmd, 0x1a2000, 11, 3), + [163] = SDC_PINGROUP(sdc2_data, 0x1a2000, 9, 0), +}; + +static const struct msm_gpio_wakeirq_map sm6375_mpm_map[] = { + { 0, 84 }, { 3, 6 }, { 4, 7 }, { 7, 8 }, { 8, 9 }, { 9, 10 }, { 11, 11 }, { 12, 13 }, + { 13, 14 }, { 16, 16 }, { 17, 17 }, { 18, 18 }, { 19, 19 }, { 21, 20 }, { 22, 21 }, + { 23, 23 }, { 24, 24 }, { 25, 25 }, { 27, 26 }, { 28, 27 }, { 37, 28 }, { 38, 29 }, + { 48, 30 }, { 50, 31 }, { 51, 32 }, { 52, 33 }, { 57, 34 }, { 59, 35 }, { 60, 37 }, + { 61, 38 }, { 62, 39 }, { 64, 40 }, { 66, 41 }, { 67, 42 }, { 68, 43 }, { 69, 44 }, + { 78, 45 }, { 82, 36 }, { 83, 47 }, { 84, 48 }, { 85, 49 }, { 87, 50 }, { 88, 51 }, + { 91, 52 }, { 94, 53 }, { 95, 54 }, { 96, 55 }, { 97, 56 }, { 98, 57 }, { 99, 58 }, + { 100, 59 }, { 104, 60 }, { 107, 61 }, { 118, 62 }, { 124, 63 }, { 125, 64 }, { 126, 65 }, + { 128, 66 }, { 129, 67 }, { 131, 69 }, { 133, 70 }, { 134, 71 }, { 136, 73 }, { 142, 74 }, + { 150, 75 }, { 153, 76 }, { 155, 77 }, +}; + +static const struct msm_pinctrl_soc_data sm6375_tlmm = { + .pins = sm6375_pins, + .npins = ARRAY_SIZE(sm6375_pins), + .functions = sm6375_functions, + .nfunctions = ARRAY_SIZE(sm6375_functions), + .groups = sm6375_groups, + .ngroups = ARRAY_SIZE(sm6375_groups), + .ngpios = 157, + .wakeirq_map = sm6375_mpm_map, + .nwakeirq_map = ARRAY_SIZE(sm6375_mpm_map), +}; + +static int sm6375_tlmm_probe(struct platform_device *pdev) +{ + return msm_pinctrl_probe(pdev, &sm6375_tlmm); +} + +static const struct of_device_id sm6375_tlmm_of_match[] = { + { .compatible = "qcom,sm6375-tlmm", }, + { }, +}; + +static struct platform_driver sm6375_tlmm_driver = { + .driver = { + .name = "sm6375-tlmm", + .of_match_table = sm6375_tlmm_of_match, + }, + .probe = sm6375_tlmm_probe, + .remove = msm_pinctrl_remove, +}; + +static int __init sm6375_tlmm_init(void) +{ + return platform_driver_register(&sm6375_tlmm_driver); +} +arch_initcall(sm6375_tlmm_init); + +static void __exit sm6375_tlmm_exit(void) +{ + platform_driver_unregister(&sm6375_tlmm_driver); +} +module_exit(sm6375_tlmm_exit); + +MODULE_DESCRIPTION("QTI SM6375 TLMM driver"); +MODULE_LICENSE("GPL"); +MODULE_DEVICE_TABLE(of, sm6375_tlmm_of_match); diff --git a/drivers/pinctrl/qcom/pinctrl-sm7150.c b/drivers/pinctrl/qcom/pinctrl-sm7150.c new file mode 100644 index 0000000000..33657cf98f --- /dev/null +++ b/drivers/pinctrl/qcom/pinctrl-sm7150.c @@ -0,0 +1,1273 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2018, The Linux Foundation. All rights reserved. + * Copyright (c) 2023, Danila Tikhonov <danila@jiaxyga.com> + */ + +#include <linux/module.h> +#include <linux/of.h> +#include <linux/platform_device.h> +#include <linux/pinctrl/pinctrl.h> + +#include "pinctrl-msm.h" + +static const char * const sm7150_tiles[] = { + "north", + "south", + "west", +}; + +enum { + NORTH, + SOUTH, + WEST +}; + +#define REG_SIZE 0x1000 + +#define PINGROUP(id, _tile, f1, f2, f3, f4, f5, f6, f7, f8, f9) \ + { \ + .grp = PINCTRL_PINGROUP("gpio" #id, \ + gpio##id##_pins, \ + ARRAY_SIZE(gpio##id##_pins)), \ + .funcs = (int[]){ \ + msm_mux_gpio, /* gpio mode */ \ + msm_mux_##f1, \ + msm_mux_##f2, \ + msm_mux_##f3, \ + msm_mux_##f4, \ + msm_mux_##f5, \ + msm_mux_##f6, \ + msm_mux_##f7, \ + msm_mux_##f8, \ + msm_mux_##f9 \ + }, \ + .nfuncs = 10, \ + .ctl_reg = REG_SIZE * id, \ + .io_reg = 0x4 + REG_SIZE * id, \ + .intr_cfg_reg = 0x8 + REG_SIZE * id, \ + .intr_status_reg = 0xc + REG_SIZE * id, \ + .intr_target_reg = 0x8 + REG_SIZE * id, \ + .tile = _tile, \ + .mux_bit = 2, \ + .pull_bit = 0, \ + .drv_bit = 6, \ + .oe_bit = 9, \ + .in_bit = 0, \ + .out_bit = 1, \ + .intr_enable_bit = 0, \ + .intr_status_bit = 0, \ + .intr_target_bit = 5, \ + .intr_target_kpss_val = 3, \ + .intr_raw_status_bit = 4, \ + .intr_polarity_bit = 1, \ + .intr_detection_bit = 2, \ + .intr_detection_width = 2, \ + } + +#define SDC_QDSD_PINGROUP(pg_name, ctl, pull, drv) \ + { \ + .grp = PINCTRL_PINGROUP(#pg_name, \ + pg_name##_pins, \ + ARRAY_SIZE(pg_name##_pins)), \ + .ctl_reg = ctl, \ + .io_reg = 0, \ + .intr_cfg_reg = 0, \ + .intr_status_reg = 0, \ + .intr_target_reg = 0, \ + .tile = SOUTH, \ + .mux_bit = -1, \ + .pull_bit = pull, \ + .drv_bit = drv, \ + .oe_bit = -1, \ + .in_bit = -1, \ + .out_bit = -1, \ + .intr_enable_bit = -1, \ + .intr_status_bit = -1, \ + .intr_target_bit = -1, \ + .intr_raw_status_bit = -1, \ + .intr_polarity_bit = -1, \ + .intr_detection_bit = -1, \ + .intr_detection_width = -1, \ + } + +#define UFS_RESET(pg_name, offset) \ + { \ + .grp = PINCTRL_PINGROUP(#pg_name, \ + pg_name##_pins, \ + ARRAY_SIZE(pg_name##_pins)), \ + .ctl_reg = offset, \ + .io_reg = offset + 0x4, \ + .intr_cfg_reg = 0, \ + .intr_status_reg = 0, \ + .intr_target_reg = 0, \ + .tile = SOUTH, \ + .mux_bit = -1, \ + .pull_bit = 3, \ + .drv_bit = 0, \ + .oe_bit = -1, \ + .in_bit = -1, \ + .out_bit = 0, \ + .intr_enable_bit = -1, \ + .intr_status_bit = -1, \ + .intr_target_bit = -1, \ + .intr_raw_status_bit = -1, \ + .intr_polarity_bit = -1, \ + .intr_detection_bit = -1, \ + .intr_detection_width = -1, \ + } + +static const struct pinctrl_pin_desc sm7150_pins[] = { + PINCTRL_PIN(0, "GPIO_0"), + PINCTRL_PIN(1, "GPIO_1"), + PINCTRL_PIN(2, "GPIO_2"), + PINCTRL_PIN(3, "GPIO_3"), + PINCTRL_PIN(4, "GPIO_4"), + PINCTRL_PIN(5, "GPIO_5"), + PINCTRL_PIN(6, "GPIO_6"), + PINCTRL_PIN(7, "GPIO_7"), + PINCTRL_PIN(8, "GPIO_8"), + PINCTRL_PIN(9, "GPIO_9"), + PINCTRL_PIN(10, "GPIO_10"), + PINCTRL_PIN(11, "GPIO_11"), + PINCTRL_PIN(12, "GPIO_12"), + PINCTRL_PIN(13, "GPIO_13"), + PINCTRL_PIN(14, "GPIO_14"), + PINCTRL_PIN(15, "GPIO_15"), + PINCTRL_PIN(16, "GPIO_16"), + PINCTRL_PIN(17, "GPIO_17"), + PINCTRL_PIN(18, "GPIO_18"), + PINCTRL_PIN(19, "GPIO_19"), + PINCTRL_PIN(20, "GPIO_20"), + PINCTRL_PIN(21, "GPIO_21"), + PINCTRL_PIN(22, "GPIO_22"), + PINCTRL_PIN(23, "GPIO_23"), + PINCTRL_PIN(24, "GPIO_24"), + PINCTRL_PIN(25, "GPIO_25"), + PINCTRL_PIN(26, "GPIO_26"), + PINCTRL_PIN(27, "GPIO_27"), + PINCTRL_PIN(28, "GPIO_28"), + PINCTRL_PIN(29, "GPIO_29"), + PINCTRL_PIN(30, "GPIO_30"), + PINCTRL_PIN(31, "GPIO_31"), + PINCTRL_PIN(32, "GPIO_32"), + PINCTRL_PIN(33, "GPIO_33"), + PINCTRL_PIN(34, "GPIO_34"), + PINCTRL_PIN(35, "GPIO_35"), + PINCTRL_PIN(36, "GPIO_36"), + PINCTRL_PIN(37, "GPIO_37"), + PINCTRL_PIN(38, "GPIO_38"), + PINCTRL_PIN(39, "GPIO_39"), + PINCTRL_PIN(40, "GPIO_40"), + PINCTRL_PIN(41, "GPIO_41"), + PINCTRL_PIN(42, "GPIO_42"), + PINCTRL_PIN(43, "GPIO_43"), + PINCTRL_PIN(44, "GPIO_44"), + PINCTRL_PIN(45, "GPIO_45"), + PINCTRL_PIN(46, "GPIO_46"), + PINCTRL_PIN(47, "GPIO_47"), + PINCTRL_PIN(48, "GPIO_48"), + PINCTRL_PIN(49, "GPIO_49"), + PINCTRL_PIN(50, "GPIO_50"), + PINCTRL_PIN(51, "GPIO_51"), + PINCTRL_PIN(52, "GPIO_52"), + PINCTRL_PIN(53, "GPIO_53"), + PINCTRL_PIN(54, "GPIO_54"), + PINCTRL_PIN(55, "GPIO_55"), + PINCTRL_PIN(56, "GPIO_56"), + PINCTRL_PIN(57, "GPIO_57"), + PINCTRL_PIN(58, "GPIO_58"), + PINCTRL_PIN(59, "GPIO_59"), + PINCTRL_PIN(60, "GPIO_60"), + PINCTRL_PIN(61, "GPIO_61"), + PINCTRL_PIN(62, "GPIO_62"), + PINCTRL_PIN(63, "GPIO_63"), + PINCTRL_PIN(64, "GPIO_64"), + PINCTRL_PIN(65, "GPIO_65"), + PINCTRL_PIN(66, "GPIO_66"), + PINCTRL_PIN(67, "GPIO_67"), + PINCTRL_PIN(68, "GPIO_68"), + PINCTRL_PIN(69, "GPIO_69"), + PINCTRL_PIN(70, "GPIO_70"), + PINCTRL_PIN(71, "GPIO_71"), + PINCTRL_PIN(72, "GPIO_72"), + PINCTRL_PIN(73, "GPIO_73"), + PINCTRL_PIN(74, "GPIO_74"), + PINCTRL_PIN(75, "GPIO_75"), + PINCTRL_PIN(76, "GPIO_76"), + PINCTRL_PIN(77, "GPIO_77"), + PINCTRL_PIN(78, "GPIO_78"), + PINCTRL_PIN(79, "GPIO_79"), + PINCTRL_PIN(80, "GPIO_80"), + PINCTRL_PIN(81, "GPIO_81"), + PINCTRL_PIN(82, "GPIO_82"), + PINCTRL_PIN(83, "GPIO_83"), + PINCTRL_PIN(84, "GPIO_84"), + PINCTRL_PIN(85, "GPIO_85"), + PINCTRL_PIN(86, "GPIO_86"), + PINCTRL_PIN(87, "GPIO_87"), + PINCTRL_PIN(88, "GPIO_88"), + PINCTRL_PIN(89, "GPIO_89"), + PINCTRL_PIN(90, "GPIO_90"), + PINCTRL_PIN(91, "GPIO_91"), + PINCTRL_PIN(92, "GPIO_92"), + PINCTRL_PIN(93, "GPIO_93"), + PINCTRL_PIN(94, "GPIO_94"), + PINCTRL_PIN(95, "GPIO_95"), + PINCTRL_PIN(96, "GPIO_96"), + PINCTRL_PIN(97, "GPIO_97"), + PINCTRL_PIN(98, "GPIO_98"), + PINCTRL_PIN(99, "GPIO_99"), + PINCTRL_PIN(100, "GPIO_100"), + PINCTRL_PIN(101, "GPIO_101"), + PINCTRL_PIN(102, "GPIO_102"), + PINCTRL_PIN(103, "GPIO_103"), + PINCTRL_PIN(104, "GPIO_104"), + PINCTRL_PIN(105, "GPIO_105"), + PINCTRL_PIN(106, "GPIO_106"), + PINCTRL_PIN(107, "GPIO_107"), + PINCTRL_PIN(108, "GPIO_108"), + PINCTRL_PIN(109, "GPIO_109"), + PINCTRL_PIN(110, "GPIO_110"), + PINCTRL_PIN(111, "GPIO_111"), + PINCTRL_PIN(112, "GPIO_112"), + PINCTRL_PIN(113, "GPIO_113"), + PINCTRL_PIN(114, "GPIO_114"), + PINCTRL_PIN(115, "GPIO_115"), + PINCTRL_PIN(116, "GPIO_116"), + PINCTRL_PIN(117, "GPIO_117"), + PINCTRL_PIN(118, "GPIO_118"), + PINCTRL_PIN(119, "UFS_RESET"), + PINCTRL_PIN(120, "SDC1_RCLK"), + PINCTRL_PIN(121, "SDC1_CLK"), + PINCTRL_PIN(122, "SDC1_CMD"), + PINCTRL_PIN(123, "SDC1_DATA"), + PINCTRL_PIN(124, "SDC2_CLK"), + PINCTRL_PIN(125, "SDC2_CMD"), + PINCTRL_PIN(126, "SDC2_DATA"), + +}; + +#define DECLARE_MSM_GPIO_PINS(pin) \ + static const unsigned int gpio##pin##_pins[] = { pin } +DECLARE_MSM_GPIO_PINS(0); +DECLARE_MSM_GPIO_PINS(1); +DECLARE_MSM_GPIO_PINS(2); +DECLARE_MSM_GPIO_PINS(3); +DECLARE_MSM_GPIO_PINS(4); +DECLARE_MSM_GPIO_PINS(5); +DECLARE_MSM_GPIO_PINS(6); +DECLARE_MSM_GPIO_PINS(7); +DECLARE_MSM_GPIO_PINS(8); +DECLARE_MSM_GPIO_PINS(9); +DECLARE_MSM_GPIO_PINS(10); +DECLARE_MSM_GPIO_PINS(11); +DECLARE_MSM_GPIO_PINS(12); +DECLARE_MSM_GPIO_PINS(13); +DECLARE_MSM_GPIO_PINS(14); +DECLARE_MSM_GPIO_PINS(15); +DECLARE_MSM_GPIO_PINS(16); +DECLARE_MSM_GPIO_PINS(17); +DECLARE_MSM_GPIO_PINS(18); +DECLARE_MSM_GPIO_PINS(19); +DECLARE_MSM_GPIO_PINS(20); +DECLARE_MSM_GPIO_PINS(21); +DECLARE_MSM_GPIO_PINS(22); +DECLARE_MSM_GPIO_PINS(23); +DECLARE_MSM_GPIO_PINS(24); +DECLARE_MSM_GPIO_PINS(25); +DECLARE_MSM_GPIO_PINS(26); +DECLARE_MSM_GPIO_PINS(27); +DECLARE_MSM_GPIO_PINS(28); +DECLARE_MSM_GPIO_PINS(29); +DECLARE_MSM_GPIO_PINS(30); +DECLARE_MSM_GPIO_PINS(31); +DECLARE_MSM_GPIO_PINS(32); +DECLARE_MSM_GPIO_PINS(33); +DECLARE_MSM_GPIO_PINS(34); +DECLARE_MSM_GPIO_PINS(35); +DECLARE_MSM_GPIO_PINS(36); +DECLARE_MSM_GPIO_PINS(37); +DECLARE_MSM_GPIO_PINS(38); +DECLARE_MSM_GPIO_PINS(39); +DECLARE_MSM_GPIO_PINS(40); +DECLARE_MSM_GPIO_PINS(41); +DECLARE_MSM_GPIO_PINS(42); +DECLARE_MSM_GPIO_PINS(43); +DECLARE_MSM_GPIO_PINS(44); +DECLARE_MSM_GPIO_PINS(45); +DECLARE_MSM_GPIO_PINS(46); +DECLARE_MSM_GPIO_PINS(47); +DECLARE_MSM_GPIO_PINS(48); +DECLARE_MSM_GPIO_PINS(49); +DECLARE_MSM_GPIO_PINS(50); +DECLARE_MSM_GPIO_PINS(51); +DECLARE_MSM_GPIO_PINS(52); +DECLARE_MSM_GPIO_PINS(53); +DECLARE_MSM_GPIO_PINS(54); +DECLARE_MSM_GPIO_PINS(55); +DECLARE_MSM_GPIO_PINS(56); +DECLARE_MSM_GPIO_PINS(57); +DECLARE_MSM_GPIO_PINS(58); +DECLARE_MSM_GPIO_PINS(59); +DECLARE_MSM_GPIO_PINS(60); +DECLARE_MSM_GPIO_PINS(61); +DECLARE_MSM_GPIO_PINS(62); +DECLARE_MSM_GPIO_PINS(63); +DECLARE_MSM_GPIO_PINS(64); +DECLARE_MSM_GPIO_PINS(65); +DECLARE_MSM_GPIO_PINS(66); +DECLARE_MSM_GPIO_PINS(67); +DECLARE_MSM_GPIO_PINS(68); +DECLARE_MSM_GPIO_PINS(69); +DECLARE_MSM_GPIO_PINS(70); +DECLARE_MSM_GPIO_PINS(71); +DECLARE_MSM_GPIO_PINS(72); +DECLARE_MSM_GPIO_PINS(73); +DECLARE_MSM_GPIO_PINS(74); +DECLARE_MSM_GPIO_PINS(75); +DECLARE_MSM_GPIO_PINS(76); +DECLARE_MSM_GPIO_PINS(77); +DECLARE_MSM_GPIO_PINS(78); +DECLARE_MSM_GPIO_PINS(79); +DECLARE_MSM_GPIO_PINS(80); +DECLARE_MSM_GPIO_PINS(81); +DECLARE_MSM_GPIO_PINS(82); +DECLARE_MSM_GPIO_PINS(83); +DECLARE_MSM_GPIO_PINS(84); +DECLARE_MSM_GPIO_PINS(85); +DECLARE_MSM_GPIO_PINS(86); +DECLARE_MSM_GPIO_PINS(87); +DECLARE_MSM_GPIO_PINS(88); +DECLARE_MSM_GPIO_PINS(89); +DECLARE_MSM_GPIO_PINS(90); +DECLARE_MSM_GPIO_PINS(91); +DECLARE_MSM_GPIO_PINS(92); +DECLARE_MSM_GPIO_PINS(93); +DECLARE_MSM_GPIO_PINS(94); +DECLARE_MSM_GPIO_PINS(95); +DECLARE_MSM_GPIO_PINS(96); +DECLARE_MSM_GPIO_PINS(97); +DECLARE_MSM_GPIO_PINS(98); +DECLARE_MSM_GPIO_PINS(99); +DECLARE_MSM_GPIO_PINS(100); +DECLARE_MSM_GPIO_PINS(101); +DECLARE_MSM_GPIO_PINS(102); +DECLARE_MSM_GPIO_PINS(103); +DECLARE_MSM_GPIO_PINS(104); +DECLARE_MSM_GPIO_PINS(105); +DECLARE_MSM_GPIO_PINS(106); +DECLARE_MSM_GPIO_PINS(107); +DECLARE_MSM_GPIO_PINS(108); +DECLARE_MSM_GPIO_PINS(109); +DECLARE_MSM_GPIO_PINS(110); +DECLARE_MSM_GPIO_PINS(111); +DECLARE_MSM_GPIO_PINS(112); +DECLARE_MSM_GPIO_PINS(113); +DECLARE_MSM_GPIO_PINS(114); +DECLARE_MSM_GPIO_PINS(115); +DECLARE_MSM_GPIO_PINS(116); +DECLARE_MSM_GPIO_PINS(117); +DECLARE_MSM_GPIO_PINS(118); + +static const unsigned int ufs_reset_pins[] = { 119 }; +static const unsigned int sdc1_rclk_pins[] = { 120 }; +static const unsigned int sdc1_clk_pins[] = { 121 }; +static const unsigned int sdc1_cmd_pins[] = { 122 }; +static const unsigned int sdc1_data_pins[] = { 123 }; +static const unsigned int sdc2_clk_pins[] = { 124 }; +static const unsigned int sdc2_cmd_pins[] = { 125 }; +static const unsigned int sdc2_data_pins[] = { 126 }; + +enum sm7150_functions { + msm_mux_gpio, + msm_mux_adsp_ext, + msm_mux_agera_pll, + msm_mux_aoss_cti, + msm_mux_atest_char, + msm_mux_atest_tsens, + msm_mux_atest_tsens2, + msm_mux_atest_usb1, + msm_mux_atest_usb2, + msm_mux_cam_mclk, + msm_mux_cci_async, + msm_mux_cci_i2c, + msm_mux_cci_timer0, + msm_mux_cci_timer1, + msm_mux_cci_timer2, + msm_mux_cci_timer3, + msm_mux_cci_timer4, + msm_mux_dbg_out, + msm_mux_ddr_bist, + msm_mux_ddr_pxi0, + msm_mux_ddr_pxi1, + msm_mux_ddr_pxi2, + msm_mux_ddr_pxi3, + msm_mux_edp_hot, + msm_mux_edp_lcd, + msm_mux_gcc_gp1, + msm_mux_gcc_gp2, + msm_mux_gcc_gp3, + msm_mux_gp_pdm0, + msm_mux_gp_pdm1, + msm_mux_gp_pdm2, + msm_mux_gps_tx, + msm_mux_jitter_bist, + msm_mux_ldo_en, + msm_mux_ldo_update, + msm_mux_m_voc, + msm_mux_mdp_vsync, + msm_mux_mdp_vsync0, + msm_mux_mdp_vsync1, + msm_mux_mdp_vsync2, + msm_mux_mdp_vsync3, + msm_mux_mss_lte, + msm_mux_nav_pps_in, + msm_mux_nav_pps_out, + msm_mux_pa_indicator, + msm_mux_pci_e, + msm_mux_phase_flag, + msm_mux_pll_bist, + msm_mux_pll_bypassnl, + msm_mux_pll_reset, + msm_mux_pri_mi2s, + msm_mux_pri_mi2s_ws, + msm_mux_prng_rosc, + msm_mux_qdss, + msm_mux_qdss_cti, + msm_mux_qlink_enable, + msm_mux_qlink_request, + msm_mux_qua_mi2s, + msm_mux_qup00, + msm_mux_qup01, + msm_mux_qup02, + msm_mux_qup03, + msm_mux_qup04, + msm_mux_qup10, + msm_mux_qup11, + msm_mux_qup12, + msm_mux_qup13, + msm_mux_qup14, + msm_mux_qup15, + msm_mux_sd_write, + msm_mux_sdc40, + msm_mux_sdc41, + msm_mux_sdc42, + msm_mux_sdc43, + msm_mux_sdc4_clk, + msm_mux_sdc4_cmd, + msm_mux_sec_mi2s, + msm_mux_ter_mi2s, + msm_mux_tgu_ch0, + msm_mux_tgu_ch1, + msm_mux_tgu_ch2, + msm_mux_tgu_ch3, + msm_mux_tsif1_clk, + msm_mux_tsif1_data, + msm_mux_tsif1_en, + msm_mux_tsif1_error, + msm_mux_tsif1_sync, + msm_mux_tsif2_clk, + msm_mux_tsif2_data, + msm_mux_tsif2_en, + msm_mux_tsif2_error, + msm_mux_tsif2_sync, + msm_mux_uim1_clk, + msm_mux_uim1_data, + msm_mux_uim1_present, + msm_mux_uim1_reset, + msm_mux_uim2_clk, + msm_mux_uim2_data, + msm_mux_uim2_present, + msm_mux_uim2_reset, + msm_mux_uim_batt, + msm_mux_usb_phy, + msm_mux_vfr_1, + msm_mux_vsense_trigger, + msm_mux_wlan1_adc0, + msm_mux_wlan1_adc1, + msm_mux_wlan2_adc0, + msm_mux_wlan2_adc1, + msm_mux_wsa_clk, + msm_mux_wsa_data, + msm_mux__, +}; + +static const char * const gpio_groups[] = { + "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7", + "gpio8", "gpio9", "gpio10", "gpio11", "gpio12", "gpio13", "gpio14", + "gpio15", "gpio16", "gpio17", "gpio18", "gpio19", "gpio20", "gpio21", + "gpio22", "gpio23", "gpio24", "gpio25", "gpio26", "gpio27", "gpio28", + "gpio29", "gpio30", "gpio31", "gpio32", "gpio33", "gpio34", "gpio35", + "gpio36", "gpio37", "gpio38", "gpio39", "gpio40", "gpio41", "gpio42", + "gpio43", "gpio44", "gpio45", "gpio46", "gpio47", "gpio48", "gpio49", + "gpio50", "gpio51", "gpio52", "gpio53", "gpio54", "gpio55", "gpio56", + "gpio57", "gpio58", "gpio59", "gpio60", "gpio61", "gpio62", "gpio63", + "gpio64", "gpio65", "gpio66", "gpio67", "gpio68", "gpio69", "gpio70", + "gpio71", "gpio72", "gpio73", "gpio74", "gpio75", "gpio76", "gpio77", + "gpio78", "gpio79", "gpio80", "gpio81", "gpio82", "gpio83", "gpio84", + "gpio85", "gpio86", "gpio87", "gpio88", "gpio89", "gpio90", "gpio91", + "gpio92", "gpio93", "gpio94", "gpio95", "gpio96", "gpio97", "gpio98", + "gpio99", "gpio100", "gpio101", "gpio102", "gpio103", "gpio104", + "gpio105", "gpio106", "gpio107", "gpio108", "gpio109", "gpio110", + "gpio111", "gpio112", "gpio113", "gpio114", "gpio115", "gpio116", + "gpio117", "gpio118", +}; + +static const char * const adsp_ext_groups[] = { + "gpio87", +}; + +static const char * const agera_pll_groups[] = { + "gpio28", +}; + +static const char * const aoss_cti_groups[] = { + "gpio85", +}; + +static const char * const atest_char_groups[] = { + "gpio86", "gpio87", "gpio88", "gpio89", "gpio90", +}; + +static const char * const atest_tsens_groups[] = { + "gpio29", +}; + +static const char * const atest_tsens2_groups[] = { + "gpio7", +}; + +static const char * const atest_usb1_groups[] = { + "gpio7", "gpio10", "gpio11", "gpio39", "gpio44", +}; + +static const char * const atest_usb2_groups[] = { + "gpio51", "gpio52", "gpio53", "gpio54", "gpio55" +}; + +static const char * const cam_mclk_groups[] = { + "gpio13", "gpio14", "gpio15", "gpio16", +}; + +static const char * const cci_async_groups[] = { + "gpio24", "gpio25", "gpio26", +}; + +static const char * const cci_i2c_groups[] = { + "gpio17", "gpio18", "gpio19", "gpio20", "gpio27", "gpio28", +}; + +static const char * const cci_timer0_groups[] = { + "gpio21", +}; + +static const char * const cci_timer1_groups[] = { + "gpio22", +}; + +static const char * const cci_timer2_groups[] = { + "gpio23", +}; + +static const char * const cci_timer3_groups[] = { + "gpio24", +}; + +static const char * const cci_timer4_groups[] = { + "gpio25", +}; + +static const char * const dbg_out_groups[] = { + "gpio3", +}; + +static const char * const ddr_bist_groups[] = { + "gpio7", "gpio8", "gpio9", "gpio10", +}; + +static const char * const ddr_pxi0_groups[] = { + "gpio6", "gpio7", +}; + +static const char * const ddr_pxi1_groups[] = { + "gpio39", "gpio44", +}; + +static const char * const ddr_pxi2_groups[] = { + "gpio10", "gpio11", +}; + +static const char * const ddr_pxi3_groups[] = { + "gpio12", "gpio13", +}; + +static const char * const edp_hot_groups[] = { + "gpio85", +}; + +static const char * const edp_lcd_groups[] = { + "gpio11", +}; + +static const char * const gcc_gp1_groups[] = { + "gpio48", "gpio56", +}; + +static const char * const gcc_gp2_groups[] = { + "gpio21", +}; + +static const char * const gcc_gp3_groups[] = { + "gpio22", +}; + +static const char * const gp_pdm0_groups[] = { + "gpio37", "gpio68", +}; + +static const char * const gp_pdm1_groups[] = { + "gpio8", "gpio50", +}; + +static const char * const gp_pdm2_groups[] = { + "gpio57", +}; + +static const char * const gps_tx_groups[] = { + "gpio83", "gpio84", "gpio107", "gpio109", +}; + +static const char * const jitter_bist_groups[] = { + "gpio26", +}; + +static const char * const ldo_en_groups[] = { + "gpio70", +}; + +static const char * const ldo_update_groups[] = { + "gpio71", +}; + +static const char * const m_voc_groups[] = { + "gpio12", +}; + +static const char * const mdp_vsync_groups[] = { + "gpio10", "gpio11", "gpio12", "gpio70", "gpio71", +}; + +static const char * const mdp_vsync0_groups[] = { + "gpio63", +}; + +static const char * const mdp_vsync1_groups[] = { + "gpio63", +}; + +static const char * const mdp_vsync2_groups[] = { + "gpio63", +}; + +static const char * const mdp_vsync3_groups[] = { + "gpio63", +}; + +static const char * const mss_lte_groups[] = { + "gpio108", "gpio109", +}; + +static const char * const nav_pps_in_groups[] = { + "gpio83", "gpio84", "gpio107", +}; + +static const char * const nav_pps_out_groups[] = { + "gpio83", "gpio84", "gpio107", +}; + +static const char * const pa_indicator_groups[] = { + "gpio99", +}; + +static const char * const pci_e_groups[] = { + "gpio66", "gpio67", "gpio68", +}; + +static const char * const phase_flag_groups[] = { + "gpio0", "gpio1", "gpio2", "gpio6", "gpio7", "gpio10", "gpio11", + "gpio12", "gpio13", "gpio14", "gpio15", "gpio16", "gpio17", "gpio24", + "gpio25", "gpio26", "gpio27", "gpio28", "gpio29", "gpio30", "gpio35", + "gpio36", "gpio37", "gpio38", "gpio39", "gpio43", "gpio44", "gpio56", + "gpio57", "gpio60", "gpio61", "gpio62", +}; + +static const char * const pll_bist_groups[] = { + "gpio27", +}; + +static const char * const pll_bypassnl_groups[] = { + "gpio13", +}; + +static const char * const pll_reset_groups[] = { + "gpio14", +}; + +static const char * const pri_mi2s_groups[] = { + "gpio49", "gpio51", "gpio52", +}; + +static const char * const pri_mi2s_ws_groups[] = { + "gpio50", +}; + +static const char * const prng_rosc_groups[] = { + "gpio72", +}; + +static const char * const qdss_groups[] = { + "gpio13", "gpio86", "gpio14", "gpio87", "gpio15", "gpio88", "gpio16", + "gpio89", "gpio17", "gpio90", "gpio18", "gpio91", "gpio19", "gpio34", + "gpio20", "gpio35", "gpio21", "gpio53", "gpio22", "gpio30", "gpio23", + "gpio54", "gpio24", "gpio55", "gpio25", "gpio57", "gpio26", "gpio31", + "gpio27", "gpio56", "gpio28", "gpio36", "gpio29", "gpio37", "gpio93", + "gpio104", +}; + +static const char * const qdss_cti_groups[] = { + "gpio4", "gpio5", "gpio32", "gpio44", "gpio45", "gpio63", +}; + +static const char * const qlink_enable_groups[] = { + "gpio97", +}; + +static const char * const qlink_request_groups[] = { + "gpio96", +}; + +static const char * const qua_mi2s_groups[] = { + "gpio58", +}; + +static const char * const qup00_groups[] = { + "gpio49", "gpio50", "gpio51", "gpio52", "gpio57", "gpio58", +}; + +static const char * const qup01_groups[] = { + "gpio0", "gpio1", "gpio2", "gpio3", "gpio12", "gpio37", +}; + +static const char * const qup02_groups[] = { + "gpio34", "gpio35", +}; + +static const char * const qup03_groups[] = { + "gpio38", "gpio39", "gpio40", "gpio41", +}; + +static const char * const qup04_groups[] = { + "gpio53", "gpio54", "gpio55", "gpio56", +}; + +static const char * const qup10_groups[] = { + "gpio59", "gpio60", "gpio61", "gpio62", "gpio63", "gpio64", "gpio65", +}; + +static const char * const qup11_groups[] = { + "gpio6", "gpio7", "gpio8", "gpio9", +}; + +static const char * const qup12_groups[] = { + "gpio42", "gpio43", "gpio44", "gpio45", +}; + +static const char * const qup13_groups[] = { + "gpio46", "gpio47", +}; + +static const char * const qup14_groups[] = { + "gpio110", "gpio111", "gpio112", "gpio113", +}; + +static const char * const qup15_groups[] = { + "gpio92", "gpio101", "gpio102", "gpio103", +}; + +static const char * const sd_write_groups[] = { + "gpio33", +}; + +static const char * const sdc40_groups[] = { + "gpio69", +}; + +static const char * const sdc41_groups[] = { + "gpio68", +}; + +static const char * const sdc42_groups[] = { + "gpio67", +}; + +static const char * const sdc43_groups[] = { + "gpio65", +}; + +static const char * const sdc4_clk_groups[] = { + "gpio66", +}; + +static const char * const sdc4_cmd_groups[] = { + "gpio64", +}; + +static const char * const sec_mi2s_groups[] = { + "gpio57", +}; + +static const char * const ter_mi2s_groups[] = { + "gpio53", "gpio54", "gpio55", "gpio56", +}; + +static const char * const tgu_ch0_groups[] = { + "gpio63", +}; + +static const char * const tgu_ch1_groups[] = { + "gpio64", +}; + +static const char * const tgu_ch2_groups[] = { + "gpio65", +}; + +static const char * const tgu_ch3_groups[] = { + "gpio62", +}; + +static const char * const tsif1_clk_groups[] = { + "gpio62", +}; + +static const char * const tsif1_data_groups[] = { + "gpio64", +}; + +static const char * const tsif1_en_groups[] = { + "gpio63", +}; + +static const char * const tsif1_error_groups[] = { + "gpio60", +}; + +static const char * const tsif1_sync_groups[] = { + "gpio61", +}; + +static const char * const tsif2_clk_groups[] = { + "gpio66", +}; + +static const char * const tsif2_data_groups[] = { + "gpio68", +}; + +static const char * const tsif2_en_groups[] = { + "gpio67", +}; + +static const char * const tsif2_error_groups[] = { + "gpio65", +}; + +static const char * const tsif2_sync_groups[] = { + "gpio69", +}; + +static const char * const uim1_clk_groups[] = { + "gpio80", +}; + +static const char * const uim1_data_groups[] = { + "gpio79", +}; + +static const char * const uim1_present_groups[] = { + "gpio82", +}; + +static const char * const uim1_reset_groups[] = { + "gpio81", +}; + +static const char * const uim2_clk_groups[] = { + "gpio76", +}; + +static const char * const uim2_data_groups[] = { + "gpio75", +}; + +static const char * const uim2_present_groups[] = { + "gpio78", +}; + +static const char * const uim2_reset_groups[] = { + "gpio77", +}; + +static const char * const uim_batt_groups[] = { + "gpio85", +}; + +static const char * const usb_phy_groups[] = { + "gpio104", +}; + +static const char * const vfr_1_groups[] = { + "gpio65", +}; + +static const char * const vsense_trigger_groups[] = { + "gpio7", +}; + +static const char * const wlan1_adc0_groups[] = { + "gpio39", +}; + +static const char * const wlan1_adc1_groups[] = { + "gpio44", +}; + +static const char * const wlan2_adc0_groups[] = { + "gpio11", +}; + +static const char * const wlan2_adc1_groups[] = { + "gpio10", +}; + +static const char * const wsa_clk_groups[] = { + "gpio49", +}; + +static const char * const wsa_data_groups[] = { + "gpio50", +}; + +static const struct pinfunction sm7150_functions[] = { + MSM_PIN_FUNCTION(gpio), + MSM_PIN_FUNCTION(adsp_ext), + MSM_PIN_FUNCTION(agera_pll), + MSM_PIN_FUNCTION(aoss_cti), + MSM_PIN_FUNCTION(atest_char), + MSM_PIN_FUNCTION(atest_tsens), + MSM_PIN_FUNCTION(atest_tsens2), + MSM_PIN_FUNCTION(atest_usb1), + MSM_PIN_FUNCTION(atest_usb2), + MSM_PIN_FUNCTION(cam_mclk), + MSM_PIN_FUNCTION(cci_async), + MSM_PIN_FUNCTION(cci_i2c), + MSM_PIN_FUNCTION(cci_timer0), + MSM_PIN_FUNCTION(cci_timer1), + MSM_PIN_FUNCTION(cci_timer2), + MSM_PIN_FUNCTION(cci_timer3), + MSM_PIN_FUNCTION(cci_timer4), + MSM_PIN_FUNCTION(dbg_out), + MSM_PIN_FUNCTION(ddr_bist), + MSM_PIN_FUNCTION(ddr_pxi0), + MSM_PIN_FUNCTION(ddr_pxi1), + MSM_PIN_FUNCTION(ddr_pxi2), + MSM_PIN_FUNCTION(ddr_pxi3), + MSM_PIN_FUNCTION(edp_hot), + MSM_PIN_FUNCTION(edp_lcd), + MSM_PIN_FUNCTION(gcc_gp1), + MSM_PIN_FUNCTION(gcc_gp2), + MSM_PIN_FUNCTION(gcc_gp3), + MSM_PIN_FUNCTION(gp_pdm0), + MSM_PIN_FUNCTION(gp_pdm1), + MSM_PIN_FUNCTION(gp_pdm2), + MSM_PIN_FUNCTION(gps_tx), + MSM_PIN_FUNCTION(jitter_bist), + MSM_PIN_FUNCTION(ldo_en), + MSM_PIN_FUNCTION(ldo_update), + MSM_PIN_FUNCTION(m_voc), + MSM_PIN_FUNCTION(mdp_vsync), + MSM_PIN_FUNCTION(mdp_vsync0), + MSM_PIN_FUNCTION(mdp_vsync1), + MSM_PIN_FUNCTION(mdp_vsync2), + MSM_PIN_FUNCTION(mdp_vsync3), + MSM_PIN_FUNCTION(mss_lte), + MSM_PIN_FUNCTION(nav_pps_in), + MSM_PIN_FUNCTION(nav_pps_out), + MSM_PIN_FUNCTION(pa_indicator), + MSM_PIN_FUNCTION(pci_e), + MSM_PIN_FUNCTION(phase_flag), + MSM_PIN_FUNCTION(pll_bist), + MSM_PIN_FUNCTION(pll_bypassnl), + MSM_PIN_FUNCTION(pll_reset), + MSM_PIN_FUNCTION(pri_mi2s), + MSM_PIN_FUNCTION(pri_mi2s_ws), + MSM_PIN_FUNCTION(prng_rosc), + MSM_PIN_FUNCTION(qdss_cti), + MSM_PIN_FUNCTION(qdss), + MSM_PIN_FUNCTION(qlink_enable), + MSM_PIN_FUNCTION(qlink_request), + MSM_PIN_FUNCTION(qua_mi2s), + MSM_PIN_FUNCTION(qup00), + MSM_PIN_FUNCTION(qup01), + MSM_PIN_FUNCTION(qup02), + MSM_PIN_FUNCTION(qup03), + MSM_PIN_FUNCTION(qup04), + MSM_PIN_FUNCTION(qup10), + MSM_PIN_FUNCTION(qup11), + MSM_PIN_FUNCTION(qup12), + MSM_PIN_FUNCTION(qup13), + MSM_PIN_FUNCTION(qup14), + MSM_PIN_FUNCTION(qup15), + MSM_PIN_FUNCTION(sd_write), + MSM_PIN_FUNCTION(sdc40), + MSM_PIN_FUNCTION(sdc41), + MSM_PIN_FUNCTION(sdc42), + MSM_PIN_FUNCTION(sdc43), + MSM_PIN_FUNCTION(sdc4_clk), + MSM_PIN_FUNCTION(sdc4_cmd), + MSM_PIN_FUNCTION(sec_mi2s), + MSM_PIN_FUNCTION(ter_mi2s), + MSM_PIN_FUNCTION(tgu_ch0), + MSM_PIN_FUNCTION(tgu_ch1), + MSM_PIN_FUNCTION(tgu_ch2), + MSM_PIN_FUNCTION(tgu_ch3), + MSM_PIN_FUNCTION(tsif1_clk), + MSM_PIN_FUNCTION(tsif1_data), + MSM_PIN_FUNCTION(tsif1_en), + MSM_PIN_FUNCTION(tsif1_error), + MSM_PIN_FUNCTION(tsif1_sync), + MSM_PIN_FUNCTION(tsif2_clk), + MSM_PIN_FUNCTION(tsif2_data), + MSM_PIN_FUNCTION(tsif2_en), + MSM_PIN_FUNCTION(tsif2_error), + MSM_PIN_FUNCTION(tsif2_sync), + MSM_PIN_FUNCTION(uim1_clk), + MSM_PIN_FUNCTION(uim1_data), + MSM_PIN_FUNCTION(uim1_present), + MSM_PIN_FUNCTION(uim1_reset), + MSM_PIN_FUNCTION(uim2_clk), + MSM_PIN_FUNCTION(uim2_data), + MSM_PIN_FUNCTION(uim2_present), + MSM_PIN_FUNCTION(uim2_reset), + MSM_PIN_FUNCTION(uim_batt), + MSM_PIN_FUNCTION(usb_phy), + MSM_PIN_FUNCTION(vfr_1), + MSM_PIN_FUNCTION(vsense_trigger), + MSM_PIN_FUNCTION(wlan1_adc0), + MSM_PIN_FUNCTION(wlan1_adc1), + MSM_PIN_FUNCTION(wlan2_adc0), + MSM_PIN_FUNCTION(wlan2_adc1), + MSM_PIN_FUNCTION(wsa_clk), + MSM_PIN_FUNCTION(wsa_data), +}; + +/* + * Every pin is maintained as a single group, and missing or non-existing pin + * would be maintained as dummy group to synchronize pin group index with + * pin descriptor registered with pinctrl core. + * Clients would not be able to request these dummy pin groups. + */ +static const struct msm_pingroup sm7150_groups[] = { + [0] = PINGROUP(0, SOUTH, qup01, _, phase_flag, _, _, _, _, _, _), + [1] = PINGROUP(1, SOUTH, qup01, _, phase_flag, _, _, _, _, _, _), + [2] = PINGROUP(2, SOUTH, qup01, _, phase_flag, _, _, _, _, _, _), + [3] = PINGROUP(3, SOUTH, qup01, dbg_out, _, _, _, _, _, _, _), + [4] = PINGROUP(4, NORTH, _, qdss_cti, _, _, _, _, _, _, _), + [5] = PINGROUP(5, NORTH, _, qdss_cti, _, _, _, _, _, _, _), + [6] = PINGROUP(6, NORTH, qup11, _, phase_flag, ddr_pxi0, _, _, _, _, _), + [7] = PINGROUP(7, NORTH, qup11, ddr_bist, _, phase_flag, atest_tsens2, vsense_trigger, atest_usb1, ddr_pxi0, _), + [8] = PINGROUP(8, NORTH, qup11, gp_pdm1, ddr_bist, _, _, _, _, _, _), + [9] = PINGROUP(9, NORTH, qup11, ddr_bist, _, _, _, _, _, _, _), + [10] = PINGROUP(10, NORTH, mdp_vsync, ddr_bist, _, phase_flag, wlan2_adc1, atest_usb1, ddr_pxi2, _, _), + [11] = PINGROUP(11, NORTH, mdp_vsync, edp_lcd, _, phase_flag, wlan2_adc0, atest_usb1, ddr_pxi2, _, _), + [12] = PINGROUP(12, SOUTH, mdp_vsync, m_voc, qup01, _, phase_flag, ddr_pxi3, _, _, _), + [13] = PINGROUP(13, SOUTH, cam_mclk, pll_bypassnl, _, phase_flag, qdss, ddr_pxi3, _, _, _), + [14] = PINGROUP(14, SOUTH, cam_mclk, pll_reset, _, phase_flag, qdss, _, _, _, _), + [15] = PINGROUP(15, SOUTH, cam_mclk, _, phase_flag, qdss, _, _, _, _, _), + [16] = PINGROUP(16, SOUTH, cam_mclk, _, phase_flag, qdss, _, _, _, _, _), + [17] = PINGROUP(17, SOUTH, cci_i2c, _, phase_flag, qdss, _, _, _, _, _), + [18] = PINGROUP(18, SOUTH, cci_i2c, qdss, _, _, _, _, _, _, _), + [19] = PINGROUP(19, SOUTH, cci_i2c, qdss, _, _, _, _, _, _, _), + [20] = PINGROUP(20, SOUTH, cci_i2c, qdss, _, _, _, _, _, _, _), + [21] = PINGROUP(21, SOUTH, cci_timer0, gcc_gp2, _, qdss, _, _, _, _, _), + [22] = PINGROUP(22, SOUTH, cci_timer1, gcc_gp3, _, qdss, _, _, _, _, _), + [23] = PINGROUP(23, SOUTH, cci_timer2, qdss, _, _, _, _, _, _, _), + [24] = PINGROUP(24, SOUTH, cci_timer3, cci_async, _, phase_flag, qdss, _, _, _, _), + [25] = PINGROUP(25, SOUTH, cci_timer4, cci_async, _, phase_flag, qdss, _, _, _, _), + [26] = PINGROUP(26, SOUTH, cci_async, jitter_bist, _, phase_flag, qdss, _, _, _, _), + [27] = PINGROUP(27, SOUTH, cci_i2c, pll_bist, _, phase_flag, qdss, _, _, _, _), + [28] = PINGROUP(28, SOUTH, cci_i2c, agera_pll, _, phase_flag, qdss, _, _, _, _), + [29] = PINGROUP(29, NORTH, _, _, phase_flag, qdss, atest_tsens, _, _, _, _), + [30] = PINGROUP(30, SOUTH, _, phase_flag, qdss, _, _, _, _, _, _), + [31] = PINGROUP(31, WEST, _, qdss, _, _, _, _, _, _, _), + [32] = PINGROUP(32, NORTH, qdss_cti, _, _, _, _, _, _, _, _), + [33] = PINGROUP(33, NORTH, sd_write, _, _, _, _, _, _, _, _), + [34] = PINGROUP(34, SOUTH, qup02, qdss, _, _, _, _, _, _, _), + [35] = PINGROUP(35, SOUTH, qup02, _, phase_flag, qdss, _, _, _, _, _), + [36] = PINGROUP(36, SOUTH, _, phase_flag, qdss, _, _, _, _, _, _), + [37] = PINGROUP(37, SOUTH, qup01, gp_pdm0, _, phase_flag, qdss, _, _, _, _), + [38] = PINGROUP(38, SOUTH, qup03, _, phase_flag, _, _, _, _, _, _), + [39] = PINGROUP(39, SOUTH, qup03, _, phase_flag, _, wlan1_adc0, atest_usb1, ddr_pxi1, _, _), + [40] = PINGROUP(40, SOUTH, qup03, _, _, _, _, _, _, _, _), + [41] = PINGROUP(41, SOUTH, qup03, _, _, _, _, _, _, _, _), + [42] = PINGROUP(42, NORTH, qup12, _, _, _, _, _, _, _, _), + [43] = PINGROUP(43, NORTH, qup12, _, phase_flag, _, _, _, _, _, _), + [44] = PINGROUP(44, NORTH, qup12, _, phase_flag, qdss_cti, _, wlan1_adc1, atest_usb1, ddr_pxi1, _), + [45] = PINGROUP(45, NORTH, qup12, qdss_cti, _, _, _, _, _, _, _), + [46] = PINGROUP(46, NORTH, qup13, _, _, _, _, _, _, _, _), + [47] = PINGROUP(47, NORTH, qup13, _, _, _, _, _, _, _, _), + [48] = PINGROUP(48, WEST, gcc_gp1, _, _, _, _, _, _, _, _), + [49] = PINGROUP(49, WEST, pri_mi2s, qup00, wsa_clk, _, _, _, _, _, _), + [50] = PINGROUP(50, WEST, pri_mi2s_ws, qup00, wsa_data, gp_pdm1, _, _, _, _, _), + [51] = PINGROUP(51, WEST, pri_mi2s, qup00, atest_usb2, _, _, _, _, _, _), + [52] = PINGROUP(52, WEST, pri_mi2s, qup00, atest_usb2, _, _, _, _, _, _), + [53] = PINGROUP(53, WEST, ter_mi2s, qup04, qdss, atest_usb2, _, _, _, _, _), + [54] = PINGROUP(54, WEST, ter_mi2s, qup04, qdss, atest_usb2, _, _, _, _, _), + [55] = PINGROUP(55, WEST, ter_mi2s, qup04, qdss, atest_usb2, _, _, _, _, _), + [56] = PINGROUP(56, WEST, ter_mi2s, qup04, gcc_gp1, _, phase_flag, qdss, _, _, _), + [57] = PINGROUP(57, WEST, sec_mi2s, qup00, gp_pdm2, _, phase_flag, qdss, _, _, _), + [58] = PINGROUP(58, WEST, qua_mi2s, qup00, _, _, _, _, _, _, _), + [59] = PINGROUP(59, NORTH, qup10, _, _, _, _, _, _, _, _), + [60] = PINGROUP(60, NORTH, qup10, tsif1_error, _, phase_flag, _, _, _, _, _), + [61] = PINGROUP(61, NORTH, qup10, tsif1_sync, _, phase_flag, _, _, _, _, _), + [62] = PINGROUP(62, NORTH, qup10, tsif1_clk, tgu_ch3, _, phase_flag, _, _, _, _), + [63] = PINGROUP(63, NORTH, tsif1_en, mdp_vsync0, qup10, mdp_vsync1, mdp_vsync2, mdp_vsync3, tgu_ch0, qdss_cti, _), + [64] = PINGROUP(64, NORTH, tsif1_data, sdc4_cmd, qup10, tgu_ch1, _, _, _, _, _), + [65] = PINGROUP(65, NORTH, tsif2_error, sdc43, qup10, vfr_1, tgu_ch2, _, _, _, _), + [66] = PINGROUP(66, NORTH, tsif2_clk, sdc4_clk, pci_e, _, _, _, _, _, _), + [67] = PINGROUP(67, NORTH, tsif2_en, sdc42, pci_e, _, _, _, _, _, _), + [68] = PINGROUP(68, NORTH, tsif2_data, sdc41, pci_e, gp_pdm0, _, _, _, _, _), + [69] = PINGROUP(69, NORTH, tsif2_sync, sdc40, _, _, _, _, _, _, _), + [70] = PINGROUP(70, NORTH, _, _, mdp_vsync, ldo_en, _, _, _, _, _), + [71] = PINGROUP(71, NORTH, _, mdp_vsync, ldo_update, _, _, _, _, _, _), + [72] = PINGROUP(72, NORTH, prng_rosc, _, _, _, _, _, _, _, _), + [73] = PINGROUP(73, NORTH, _, _, _, _, _, _, _, _, _), + [74] = PINGROUP(74, WEST, _, _, _, _, _, _, _, _, _), + [75] = PINGROUP(75, WEST, uim2_data, _, _, _, _, _, _, _, _), + [76] = PINGROUP(76, WEST, uim2_clk, _, _, _, _, _, _, _, _), + [77] = PINGROUP(77, WEST, uim2_reset, _, _, _, _, _, _, _, _), + [78] = PINGROUP(78, WEST, uim2_present, _, _, _, _, _, _, _, _), + [79] = PINGROUP(79, WEST, uim1_data, _, _, _, _, _, _, _, _), + [80] = PINGROUP(80, WEST, uim1_clk, _, _, _, _, _, _, _, _), + [81] = PINGROUP(81, WEST, uim1_reset, _, _, _, _, _, _, _, _), + [82] = PINGROUP(82, WEST, uim1_present, _, _, _, _, _, _, _, _), + [83] = PINGROUP(83, WEST, _, nav_pps_in, nav_pps_out, gps_tx, _, _, _, _, _), + [84] = PINGROUP(84, WEST, _, nav_pps_in, nav_pps_out, gps_tx, _, _, _, _, _), + [85] = PINGROUP(85, WEST, uim_batt, edp_hot, aoss_cti, _, _, _, _, _, _), + [86] = PINGROUP(86, NORTH, qdss, atest_char, _, _, _, _, _, _, _), + [87] = PINGROUP(87, NORTH, adsp_ext, qdss, atest_char, _, _, _, _, _, _), + [88] = PINGROUP(88, NORTH, qdss, atest_char, _, _, _, _, _, _, _), + [89] = PINGROUP(89, NORTH, qdss, atest_char, _, _, _, _, _, _, _), + [90] = PINGROUP(90, NORTH, qdss, atest_char, _, _, _, _, _, _, _), + [91] = PINGROUP(91, NORTH, qdss, _, _, _, _, _, _, _, _), + [92] = PINGROUP(92, NORTH, _, _, qup15, _, _, _, _, _, _), + [93] = PINGROUP(93, NORTH, qdss, _, _, _, _, _, _, _, _), + [94] = PINGROUP(94, SOUTH, _, _, _, _, _, _, _, _, _), + [95] = PINGROUP(95, WEST, _, _, _, _, _, _, _, _, _), + [96] = PINGROUP(96, WEST, qlink_request, _, _, _, _, _, _, _, _), + [97] = PINGROUP(97, WEST, qlink_enable, _, _, _, _, _, _, _, _), + [98] = PINGROUP(98, WEST, _, _, _, _, _, _, _, _, _), + [99] = PINGROUP(99, WEST, _, pa_indicator, _, _, _, _, _, _, _), + [100] = PINGROUP(100, WEST, _, _, _, _, _, _, _, _, _), + [101] = PINGROUP(101, NORTH, _, _, qup15, _, _, _, _, _, _), + [102] = PINGROUP(102, NORTH, _, _, qup15, _, _, _, _, _, _), + [103] = PINGROUP(103, NORTH, _, qup15, _, _, _, _, _, _, _), + [104] = PINGROUP(104, WEST, usb_phy, _, qdss, _, _, _, _, _, _), + [105] = PINGROUP(105, NORTH, _, _, _, _, _, _, _, _, _), + [106] = PINGROUP(106, NORTH, _, _, _, _, _, _, _, _, _), + [107] = PINGROUP(107, WEST, _, nav_pps_in, nav_pps_out, gps_tx, _, _, _, _, _), + [108] = PINGROUP(108, SOUTH, mss_lte, _, _, _, _, _, _, _, _), + [109] = PINGROUP(109, SOUTH, mss_lte, gps_tx, _, _, _, _, _, _, _), + [110] = PINGROUP(110, NORTH, _, _, qup14, _, _, _, _, _, _), + [111] = PINGROUP(111, NORTH, _, _, qup14, _, _, _, _, _, _), + [112] = PINGROUP(112, NORTH, _, qup14, _, _, _, _, _, _, _), + [113] = PINGROUP(113, NORTH, _, qup14, _, _, _, _, _, _, _), + [114] = PINGROUP(114, NORTH, _, _, _, _, _, _, _, _, _), + [115] = PINGROUP(115, NORTH, _, _, _, _, _, _, _, _, _), + [116] = PINGROUP(116, NORTH, _, _, _, _, _, _, _, _, _), + [117] = PINGROUP(117, NORTH, _, _, _, _, _, _, _, _, _), + [118] = PINGROUP(118, NORTH, _, _, _, _, _, _, _, _, _), + [119] = UFS_RESET(ufs_reset, 0x9f000), + [120] = SDC_QDSD_PINGROUP(sdc1_rclk, 0x9a000, 15, 0), + [121] = SDC_QDSD_PINGROUP(sdc1_clk, 0x9a000, 13, 6), + [122] = SDC_QDSD_PINGROUP(sdc1_cmd, 0x9a000, 11, 3), + [123] = SDC_QDSD_PINGROUP(sdc1_data, 0x9a000, 9, 0), + [124] = SDC_QDSD_PINGROUP(sdc2_clk, 0x98000, 14, 6), + [125] = SDC_QDSD_PINGROUP(sdc2_cmd, 0x98000, 11, 3), + [126] = SDC_QDSD_PINGROUP(sdc2_data, 0x98000, 9, 0), +}; + +static const struct msm_gpio_wakeirq_map sm7150_pdc_map[] = { + {0, 40}, {3, 50}, {4, 42}, {5, 70}, {6, 41}, {9, 57}, + {10, 80}, {11, 51}, {22, 90}, {24, 61}, {26, 52}, {30, 56}, + {31, 33}, {32, 81}, {33, 62}, {34, 43}, {36, 91}, {37, 53}, + {38, 63}, {39, 72}, {41, 101}, {42, 35}, {43, 34}, {45, 73}, + {47, 82}, {48, 36}, {49, 37}, {50, 38}, {52, 39}, {53, 102}, + {55, 92}, {56, 45}, {57, 46}, {58, 83}, {59, 47}, {62, 48}, + {64, 74}, {65, 44}, {66, 93}, {67, 49}, {68, 55}, {69, 32}, + {70, 54}, {73, 64}, {74, 71}, {78, 31}, {82, 30}, {84, 58}, + {85, 103}, {86, 59}, {87, 60}, {88, 65}, {89, 66}, {90, 67}, + {91, 68}, {92, 69}, {93, 75}, {94, 84}, {95, 94}, {96, 76}, + {98, 77}, {101, 78}, {104, 99}, {109, 104}, {110, 79}, {113, 85}, +}; + +static const struct msm_pinctrl_soc_data sm7150_tlmm = { + .pins = sm7150_pins, + .npins = ARRAY_SIZE(sm7150_pins), + .functions = sm7150_functions, + .nfunctions = ARRAY_SIZE(sm7150_functions), + .groups = sm7150_groups, + .ngroups = ARRAY_SIZE(sm7150_groups), + .ngpios = 120, + .tiles = sm7150_tiles, + .ntiles = ARRAY_SIZE(sm7150_tiles), + .wakeirq_map = sm7150_pdc_map, + .nwakeirq_map = ARRAY_SIZE(sm7150_pdc_map), + .wakeirq_dual_edge_errata = true, +}; + +static int sm7150_tlmm_probe(struct platform_device *pdev) +{ + return msm_pinctrl_probe(pdev, &sm7150_tlmm); +} + +static const struct of_device_id sm7150_tlmm_of_match[] = { + { .compatible = "qcom,sm7150-tlmm", }, + { }, +}; + +static struct platform_driver sm7150_tlmm_driver = { + .driver = { + .name = "sm7150-tlmm", + .pm = &msm_pinctrl_dev_pm_ops, + .of_match_table = sm7150_tlmm_of_match, + }, + .probe = sm7150_tlmm_probe, + .remove = msm_pinctrl_remove, +}; + +static int __init sm7150_tlmm_init(void) +{ + return platform_driver_register(&sm7150_tlmm_driver); +} +arch_initcall(sm7150_tlmm_init); + +static void __exit sm7150_tlmm_exit(void) +{ + platform_driver_unregister(&sm7150_tlmm_driver); +} +module_exit(sm7150_tlmm_exit); + +MODULE_DESCRIPTION("Qualcomm SM7150 TLMM driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/pinctrl/qcom/pinctrl-sm8150.c b/drivers/pinctrl/qcom/pinctrl-sm8150.c new file mode 100644 index 0000000000..01aea9c70b --- /dev/null +++ b/drivers/pinctrl/qcom/pinctrl-sm8150.c @@ -0,0 +1,1562 @@ +// SPDX-License-Identifier: GPL-2.0 +// Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. + +#include <linux/module.h> +#include <linux/of.h> +#include <linux/platform_device.h> + +#include "pinctrl-msm.h" + +static const char * const sm8150_tiles[] = { + "north", + "south", + "east", + "west" +}; + +enum { + NORTH, + SOUTH, + EAST, + WEST +}; + +#define PINGROUP(id, _tile, f1, f2, f3, f4, f5, f6, f7, f8, f9) \ + { \ + .grp = PINCTRL_PINGROUP("gpio" #id, \ + gpio##id##_pins, \ + ARRAY_SIZE(gpio##id##_pins)), \ + .funcs = (int[]){ \ + msm_mux_gpio, /* gpio mode */ \ + msm_mux_##f1, \ + msm_mux_##f2, \ + msm_mux_##f3, \ + msm_mux_##f4, \ + msm_mux_##f5, \ + msm_mux_##f6, \ + msm_mux_##f7, \ + msm_mux_##f8, \ + msm_mux_##f9 \ + }, \ + .nfuncs = 10, \ + .ctl_reg = 0x1000 * id, \ + .io_reg = 0x1000 * id + 0x4, \ + .intr_cfg_reg = 0x1000 * id + 0x8, \ + .intr_status_reg = 0x1000 * id + 0xc, \ + .intr_target_reg = 0x1000 * id + 0x8, \ + .tile = _tile, \ + .mux_bit = 2, \ + .pull_bit = 0, \ + .drv_bit = 6, \ + .oe_bit = 9, \ + .in_bit = 0, \ + .out_bit = 1, \ + .intr_enable_bit = 0, \ + .intr_status_bit = 0, \ + .intr_target_bit = 5, \ + .intr_target_kpss_val = 3, \ + .intr_raw_status_bit = 4, \ + .intr_polarity_bit = 1, \ + .intr_detection_bit = 2, \ + .intr_detection_width = 2, \ + } + +#define SDC_QDSD_PINGROUP(pg_name, ctl, pull, drv) \ + { \ + .grp = PINCTRL_PINGROUP(#pg_name, \ + pg_name##_pins, \ + ARRAY_SIZE(pg_name##_pins)), \ + .ctl_reg = ctl, \ + .io_reg = 0, \ + .intr_cfg_reg = 0, \ + .intr_status_reg = 0, \ + .intr_target_reg = 0, \ + .tile = NORTH, \ + .mux_bit = -1, \ + .pull_bit = pull, \ + .drv_bit = drv, \ + .oe_bit = -1, \ + .in_bit = -1, \ + .out_bit = -1, \ + .intr_enable_bit = -1, \ + .intr_status_bit = -1, \ + .intr_target_bit = -1, \ + .intr_raw_status_bit = -1, \ + .intr_polarity_bit = -1, \ + .intr_detection_bit = -1, \ + .intr_detection_width = -1, \ + } + +#define UFS_RESET(pg_name, offset) \ + { \ + .grp = PINCTRL_PINGROUP(#pg_name, \ + pg_name##_pins, \ + ARRAY_SIZE(pg_name##_pins)), \ + .ctl_reg = offset, \ + .io_reg = offset + 0x4, \ + .intr_cfg_reg = 0, \ + .intr_status_reg = 0, \ + .intr_target_reg = 0, \ + .tile = SOUTH, \ + .mux_bit = -1, \ + .pull_bit = 3, \ + .drv_bit = 0, \ + .oe_bit = -1, \ + .in_bit = -1, \ + .out_bit = 0, \ + .intr_enable_bit = -1, \ + .intr_status_bit = -1, \ + .intr_target_bit = -1, \ + .intr_raw_status_bit = -1, \ + .intr_polarity_bit = -1, \ + .intr_detection_bit = -1, \ + .intr_detection_width = -1, \ + } + +static const struct pinctrl_pin_desc sm8150_pins[] = { + PINCTRL_PIN(0, "GPIO_0"), + PINCTRL_PIN(1, "GPIO_1"), + PINCTRL_PIN(2, "GPIO_2"), + PINCTRL_PIN(3, "GPIO_3"), + PINCTRL_PIN(4, "GPIO_4"), + PINCTRL_PIN(5, "GPIO_5"), + PINCTRL_PIN(6, "GPIO_6"), + PINCTRL_PIN(7, "GPIO_7"), + PINCTRL_PIN(8, "GPIO_8"), + PINCTRL_PIN(9, "GPIO_9"), + PINCTRL_PIN(10, "GPIO_10"), + PINCTRL_PIN(11, "GPIO_11"), + PINCTRL_PIN(12, "GPIO_12"), + PINCTRL_PIN(13, "GPIO_13"), + PINCTRL_PIN(14, "GPIO_14"), + PINCTRL_PIN(15, "GPIO_15"), + PINCTRL_PIN(16, "GPIO_16"), + PINCTRL_PIN(17, "GPIO_17"), + PINCTRL_PIN(18, "GPIO_18"), + PINCTRL_PIN(19, "GPIO_19"), + PINCTRL_PIN(20, "GPIO_20"), + PINCTRL_PIN(21, "GPIO_21"), + PINCTRL_PIN(22, "GPIO_22"), + PINCTRL_PIN(23, "GPIO_23"), + PINCTRL_PIN(24, "GPIO_24"), + PINCTRL_PIN(25, "GPIO_25"), + PINCTRL_PIN(26, "GPIO_26"), + PINCTRL_PIN(27, "GPIO_27"), + PINCTRL_PIN(28, "GPIO_28"), + PINCTRL_PIN(29, "GPIO_29"), + PINCTRL_PIN(30, "GPIO_30"), + PINCTRL_PIN(31, "GPIO_31"), + PINCTRL_PIN(32, "GPIO_32"), + PINCTRL_PIN(33, "GPIO_33"), + PINCTRL_PIN(34, "GPIO_34"), + PINCTRL_PIN(35, "GPIO_35"), + PINCTRL_PIN(36, "GPIO_36"), + PINCTRL_PIN(37, "GPIO_37"), + PINCTRL_PIN(38, "GPIO_38"), + PINCTRL_PIN(39, "GPIO_39"), + PINCTRL_PIN(40, "GPIO_40"), + PINCTRL_PIN(41, "GPIO_41"), + PINCTRL_PIN(42, "GPIO_42"), + PINCTRL_PIN(43, "GPIO_43"), + PINCTRL_PIN(44, "GPIO_44"), + PINCTRL_PIN(45, "GPIO_45"), + PINCTRL_PIN(46, "GPIO_46"), + PINCTRL_PIN(47, "GPIO_47"), + PINCTRL_PIN(48, "GPIO_48"), + PINCTRL_PIN(49, "GPIO_49"), + PINCTRL_PIN(50, "GPIO_50"), + PINCTRL_PIN(51, "GPIO_51"), + PINCTRL_PIN(52, "GPIO_52"), + PINCTRL_PIN(53, "GPIO_53"), + PINCTRL_PIN(54, "GPIO_54"), + PINCTRL_PIN(55, "GPIO_55"), + PINCTRL_PIN(56, "GPIO_56"), + PINCTRL_PIN(57, "GPIO_57"), + PINCTRL_PIN(58, "GPIO_58"), + PINCTRL_PIN(59, "GPIO_59"), + PINCTRL_PIN(60, "GPIO_60"), + PINCTRL_PIN(61, "GPIO_61"), + PINCTRL_PIN(62, "GPIO_62"), + PINCTRL_PIN(63, "GPIO_63"), + PINCTRL_PIN(64, "GPIO_64"), + PINCTRL_PIN(65, "GPIO_65"), + PINCTRL_PIN(66, "GPIO_66"), + PINCTRL_PIN(67, "GPIO_67"), + PINCTRL_PIN(68, "GPIO_68"), + PINCTRL_PIN(69, "GPIO_69"), + PINCTRL_PIN(70, "GPIO_70"), + PINCTRL_PIN(71, "GPIO_71"), + PINCTRL_PIN(72, "GPIO_72"), + PINCTRL_PIN(73, "GPIO_73"), + PINCTRL_PIN(74, "GPIO_74"), + PINCTRL_PIN(75, "GPIO_75"), + PINCTRL_PIN(76, "GPIO_76"), + PINCTRL_PIN(77, "GPIO_77"), + PINCTRL_PIN(78, "GPIO_78"), + PINCTRL_PIN(79, "GPIO_79"), + PINCTRL_PIN(80, "GPIO_80"), + PINCTRL_PIN(81, "GPIO_81"), + PINCTRL_PIN(82, "GPIO_82"), + PINCTRL_PIN(83, "GPIO_83"), + PINCTRL_PIN(84, "GPIO_84"), + PINCTRL_PIN(85, "GPIO_85"), + PINCTRL_PIN(86, "GPIO_86"), + PINCTRL_PIN(87, "GPIO_87"), + PINCTRL_PIN(88, "GPIO_88"), + PINCTRL_PIN(89, "GPIO_89"), + PINCTRL_PIN(90, "GPIO_90"), + PINCTRL_PIN(91, "GPIO_91"), + PINCTRL_PIN(92, "GPIO_92"), + PINCTRL_PIN(93, "GPIO_93"), + PINCTRL_PIN(94, "GPIO_94"), + PINCTRL_PIN(95, "GPIO_95"), + PINCTRL_PIN(96, "GPIO_96"), + PINCTRL_PIN(97, "GPIO_97"), + PINCTRL_PIN(98, "GPIO_98"), + PINCTRL_PIN(99, "GPIO_99"), + PINCTRL_PIN(100, "GPIO_100"), + PINCTRL_PIN(101, "GPIO_101"), + PINCTRL_PIN(102, "GPIO_102"), + PINCTRL_PIN(103, "GPIO_103"), + PINCTRL_PIN(104, "GPIO_104"), + PINCTRL_PIN(105, "GPIO_105"), + PINCTRL_PIN(106, "GPIO_106"), + PINCTRL_PIN(107, "GPIO_107"), + PINCTRL_PIN(108, "GPIO_108"), + PINCTRL_PIN(109, "GPIO_109"), + PINCTRL_PIN(110, "GPIO_110"), + PINCTRL_PIN(111, "GPIO_111"), + PINCTRL_PIN(112, "GPIO_112"), + PINCTRL_PIN(113, "GPIO_113"), + PINCTRL_PIN(114, "GPIO_114"), + PINCTRL_PIN(115, "GPIO_115"), + PINCTRL_PIN(116, "GPIO_116"), + PINCTRL_PIN(117, "GPIO_117"), + PINCTRL_PIN(118, "GPIO_118"), + PINCTRL_PIN(119, "GPIO_119"), + PINCTRL_PIN(120, "GPIO_120"), + PINCTRL_PIN(121, "GPIO_121"), + PINCTRL_PIN(122, "GPIO_122"), + PINCTRL_PIN(123, "GPIO_123"), + PINCTRL_PIN(124, "GPIO_124"), + PINCTRL_PIN(125, "GPIO_125"), + PINCTRL_PIN(126, "GPIO_126"), + PINCTRL_PIN(127, "GPIO_127"), + PINCTRL_PIN(128, "GPIO_128"), + PINCTRL_PIN(129, "GPIO_129"), + PINCTRL_PIN(130, "GPIO_130"), + PINCTRL_PIN(131, "GPIO_131"), + PINCTRL_PIN(132, "GPIO_132"), + PINCTRL_PIN(133, "GPIO_133"), + PINCTRL_PIN(134, "GPIO_134"), + PINCTRL_PIN(135, "GPIO_135"), + PINCTRL_PIN(136, "GPIO_136"), + PINCTRL_PIN(137, "GPIO_137"), + PINCTRL_PIN(138, "GPIO_138"), + PINCTRL_PIN(139, "GPIO_139"), + PINCTRL_PIN(140, "GPIO_140"), + PINCTRL_PIN(141, "GPIO_141"), + PINCTRL_PIN(142, "GPIO_142"), + PINCTRL_PIN(143, "GPIO_143"), + PINCTRL_PIN(144, "GPIO_144"), + PINCTRL_PIN(145, "GPIO_145"), + PINCTRL_PIN(146, "GPIO_146"), + PINCTRL_PIN(147, "GPIO_147"), + PINCTRL_PIN(148, "GPIO_148"), + PINCTRL_PIN(149, "GPIO_149"), + PINCTRL_PIN(150, "GPIO_150"), + PINCTRL_PIN(151, "GPIO_151"), + PINCTRL_PIN(152, "GPIO_152"), + PINCTRL_PIN(153, "GPIO_153"), + PINCTRL_PIN(154, "GPIO_154"), + PINCTRL_PIN(155, "GPIO_155"), + PINCTRL_PIN(156, "GPIO_156"), + PINCTRL_PIN(157, "GPIO_157"), + PINCTRL_PIN(158, "GPIO_158"), + PINCTRL_PIN(159, "GPIO_159"), + PINCTRL_PIN(160, "GPIO_160"), + PINCTRL_PIN(161, "GPIO_161"), + PINCTRL_PIN(162, "GPIO_162"), + PINCTRL_PIN(163, "GPIO_163"), + PINCTRL_PIN(164, "GPIO_164"), + PINCTRL_PIN(165, "GPIO_165"), + PINCTRL_PIN(166, "GPIO_166"), + PINCTRL_PIN(167, "GPIO_167"), + PINCTRL_PIN(168, "GPIO_168"), + PINCTRL_PIN(169, "GPIO_169"), + PINCTRL_PIN(170, "GPIO_170"), + PINCTRL_PIN(171, "GPIO_171"), + PINCTRL_PIN(172, "GPIO_172"), + PINCTRL_PIN(173, "GPIO_173"), + PINCTRL_PIN(174, "GPIO_174"), + PINCTRL_PIN(175, "UFS_RESET"), + PINCTRL_PIN(176, "SDC2_CLK"), + PINCTRL_PIN(177, "SDC2_CMD"), + PINCTRL_PIN(178, "SDC2_DATA"), +}; + +#define DECLARE_MSM_GPIO_PINS(pin) \ + static const unsigned int gpio##pin##_pins[] = { pin } +DECLARE_MSM_GPIO_PINS(0); +DECLARE_MSM_GPIO_PINS(1); +DECLARE_MSM_GPIO_PINS(2); +DECLARE_MSM_GPIO_PINS(3); +DECLARE_MSM_GPIO_PINS(4); +DECLARE_MSM_GPIO_PINS(5); +DECLARE_MSM_GPIO_PINS(6); +DECLARE_MSM_GPIO_PINS(7); +DECLARE_MSM_GPIO_PINS(8); +DECLARE_MSM_GPIO_PINS(9); +DECLARE_MSM_GPIO_PINS(10); +DECLARE_MSM_GPIO_PINS(11); +DECLARE_MSM_GPIO_PINS(12); +DECLARE_MSM_GPIO_PINS(13); +DECLARE_MSM_GPIO_PINS(14); +DECLARE_MSM_GPIO_PINS(15); +DECLARE_MSM_GPIO_PINS(16); +DECLARE_MSM_GPIO_PINS(17); +DECLARE_MSM_GPIO_PINS(18); +DECLARE_MSM_GPIO_PINS(19); +DECLARE_MSM_GPIO_PINS(20); +DECLARE_MSM_GPIO_PINS(21); +DECLARE_MSM_GPIO_PINS(22); +DECLARE_MSM_GPIO_PINS(23); +DECLARE_MSM_GPIO_PINS(24); +DECLARE_MSM_GPIO_PINS(25); +DECLARE_MSM_GPIO_PINS(26); +DECLARE_MSM_GPIO_PINS(27); +DECLARE_MSM_GPIO_PINS(28); +DECLARE_MSM_GPIO_PINS(29); +DECLARE_MSM_GPIO_PINS(30); +DECLARE_MSM_GPIO_PINS(31); +DECLARE_MSM_GPIO_PINS(32); +DECLARE_MSM_GPIO_PINS(33); +DECLARE_MSM_GPIO_PINS(34); +DECLARE_MSM_GPIO_PINS(35); +DECLARE_MSM_GPIO_PINS(36); +DECLARE_MSM_GPIO_PINS(37); +DECLARE_MSM_GPIO_PINS(38); +DECLARE_MSM_GPIO_PINS(39); +DECLARE_MSM_GPIO_PINS(40); +DECLARE_MSM_GPIO_PINS(41); +DECLARE_MSM_GPIO_PINS(42); +DECLARE_MSM_GPIO_PINS(43); +DECLARE_MSM_GPIO_PINS(44); +DECLARE_MSM_GPIO_PINS(45); +DECLARE_MSM_GPIO_PINS(46); +DECLARE_MSM_GPIO_PINS(47); +DECLARE_MSM_GPIO_PINS(48); +DECLARE_MSM_GPIO_PINS(49); +DECLARE_MSM_GPIO_PINS(50); +DECLARE_MSM_GPIO_PINS(51); +DECLARE_MSM_GPIO_PINS(52); +DECLARE_MSM_GPIO_PINS(53); +DECLARE_MSM_GPIO_PINS(54); +DECLARE_MSM_GPIO_PINS(55); +DECLARE_MSM_GPIO_PINS(56); +DECLARE_MSM_GPIO_PINS(57); +DECLARE_MSM_GPIO_PINS(58); +DECLARE_MSM_GPIO_PINS(59); +DECLARE_MSM_GPIO_PINS(60); +DECLARE_MSM_GPIO_PINS(61); +DECLARE_MSM_GPIO_PINS(62); +DECLARE_MSM_GPIO_PINS(63); +DECLARE_MSM_GPIO_PINS(64); +DECLARE_MSM_GPIO_PINS(65); +DECLARE_MSM_GPIO_PINS(66); +DECLARE_MSM_GPIO_PINS(67); +DECLARE_MSM_GPIO_PINS(68); +DECLARE_MSM_GPIO_PINS(69); +DECLARE_MSM_GPIO_PINS(70); +DECLARE_MSM_GPIO_PINS(71); +DECLARE_MSM_GPIO_PINS(72); +DECLARE_MSM_GPIO_PINS(73); +DECLARE_MSM_GPIO_PINS(74); +DECLARE_MSM_GPIO_PINS(75); +DECLARE_MSM_GPIO_PINS(76); +DECLARE_MSM_GPIO_PINS(77); +DECLARE_MSM_GPIO_PINS(78); +DECLARE_MSM_GPIO_PINS(79); +DECLARE_MSM_GPIO_PINS(80); +DECLARE_MSM_GPIO_PINS(81); +DECLARE_MSM_GPIO_PINS(82); +DECLARE_MSM_GPIO_PINS(83); +DECLARE_MSM_GPIO_PINS(84); +DECLARE_MSM_GPIO_PINS(85); +DECLARE_MSM_GPIO_PINS(86); +DECLARE_MSM_GPIO_PINS(87); +DECLARE_MSM_GPIO_PINS(88); +DECLARE_MSM_GPIO_PINS(89); +DECLARE_MSM_GPIO_PINS(90); +DECLARE_MSM_GPIO_PINS(91); +DECLARE_MSM_GPIO_PINS(92); +DECLARE_MSM_GPIO_PINS(93); +DECLARE_MSM_GPIO_PINS(94); +DECLARE_MSM_GPIO_PINS(95); +DECLARE_MSM_GPIO_PINS(96); +DECLARE_MSM_GPIO_PINS(97); +DECLARE_MSM_GPIO_PINS(98); +DECLARE_MSM_GPIO_PINS(99); +DECLARE_MSM_GPIO_PINS(100); +DECLARE_MSM_GPIO_PINS(101); +DECLARE_MSM_GPIO_PINS(102); +DECLARE_MSM_GPIO_PINS(103); +DECLARE_MSM_GPIO_PINS(104); +DECLARE_MSM_GPIO_PINS(105); +DECLARE_MSM_GPIO_PINS(106); +DECLARE_MSM_GPIO_PINS(107); +DECLARE_MSM_GPIO_PINS(108); +DECLARE_MSM_GPIO_PINS(109); +DECLARE_MSM_GPIO_PINS(110); +DECLARE_MSM_GPIO_PINS(111); +DECLARE_MSM_GPIO_PINS(112); +DECLARE_MSM_GPIO_PINS(113); +DECLARE_MSM_GPIO_PINS(114); +DECLARE_MSM_GPIO_PINS(115); +DECLARE_MSM_GPIO_PINS(116); +DECLARE_MSM_GPIO_PINS(117); +DECLARE_MSM_GPIO_PINS(118); +DECLARE_MSM_GPIO_PINS(119); +DECLARE_MSM_GPIO_PINS(120); +DECLARE_MSM_GPIO_PINS(121); +DECLARE_MSM_GPIO_PINS(122); +DECLARE_MSM_GPIO_PINS(123); +DECLARE_MSM_GPIO_PINS(124); +DECLARE_MSM_GPIO_PINS(125); +DECLARE_MSM_GPIO_PINS(126); +DECLARE_MSM_GPIO_PINS(127); +DECLARE_MSM_GPIO_PINS(128); +DECLARE_MSM_GPIO_PINS(129); +DECLARE_MSM_GPIO_PINS(130); +DECLARE_MSM_GPIO_PINS(131); +DECLARE_MSM_GPIO_PINS(132); +DECLARE_MSM_GPIO_PINS(133); +DECLARE_MSM_GPIO_PINS(134); +DECLARE_MSM_GPIO_PINS(135); +DECLARE_MSM_GPIO_PINS(136); +DECLARE_MSM_GPIO_PINS(137); +DECLARE_MSM_GPIO_PINS(138); +DECLARE_MSM_GPIO_PINS(139); +DECLARE_MSM_GPIO_PINS(140); +DECLARE_MSM_GPIO_PINS(141); +DECLARE_MSM_GPIO_PINS(142); +DECLARE_MSM_GPIO_PINS(143); +DECLARE_MSM_GPIO_PINS(144); +DECLARE_MSM_GPIO_PINS(145); +DECLARE_MSM_GPIO_PINS(146); +DECLARE_MSM_GPIO_PINS(147); +DECLARE_MSM_GPIO_PINS(148); +DECLARE_MSM_GPIO_PINS(149); +DECLARE_MSM_GPIO_PINS(150); +DECLARE_MSM_GPIO_PINS(151); +DECLARE_MSM_GPIO_PINS(152); +DECLARE_MSM_GPIO_PINS(153); +DECLARE_MSM_GPIO_PINS(154); +DECLARE_MSM_GPIO_PINS(155); +DECLARE_MSM_GPIO_PINS(156); +DECLARE_MSM_GPIO_PINS(157); +DECLARE_MSM_GPIO_PINS(158); +DECLARE_MSM_GPIO_PINS(159); +DECLARE_MSM_GPIO_PINS(160); +DECLARE_MSM_GPIO_PINS(161); +DECLARE_MSM_GPIO_PINS(162); +DECLARE_MSM_GPIO_PINS(163); +DECLARE_MSM_GPIO_PINS(164); +DECLARE_MSM_GPIO_PINS(165); +DECLARE_MSM_GPIO_PINS(166); +DECLARE_MSM_GPIO_PINS(167); +DECLARE_MSM_GPIO_PINS(168); +DECLARE_MSM_GPIO_PINS(169); +DECLARE_MSM_GPIO_PINS(170); +DECLARE_MSM_GPIO_PINS(171); +DECLARE_MSM_GPIO_PINS(172); +DECLARE_MSM_GPIO_PINS(173); +DECLARE_MSM_GPIO_PINS(174); + +static const unsigned int ufs_reset_pins[] = { 175 }; +static const unsigned int sdc2_clk_pins[] = { 176 }; +static const unsigned int sdc2_cmd_pins[] = { 177 }; +static const unsigned int sdc2_data_pins[] = { 178 }; + +enum sm8150_functions { + msm_mux_adsp_ext, + msm_mux_agera_pll, + msm_mux_aoss_cti, + msm_mux_atest_char, + msm_mux_atest_char0, + msm_mux_atest_char1, + msm_mux_atest_char2, + msm_mux_atest_char3, + msm_mux_atest_usb1, + msm_mux_atest_usb2, + msm_mux_atest_usb10, + msm_mux_atest_usb11, + msm_mux_atest_usb12, + msm_mux_atest_usb13, + msm_mux_atest_usb20, + msm_mux_atest_usb21, + msm_mux_atest_usb22, + msm_mux_atest_usb23, + msm_mux_audio_ref, + msm_mux_btfm_slimbus, + msm_mux_cam_mclk, + msm_mux_cci_async, + msm_mux_cci_i2c, + msm_mux_cci_timer0, + msm_mux_cci_timer1, + msm_mux_cci_timer2, + msm_mux_cci_timer3, + msm_mux_cci_timer4, + msm_mux_cri_trng, + msm_mux_cri_trng0, + msm_mux_cri_trng1, + msm_mux_dbg_out, + msm_mux_ddr_bist, + msm_mux_ddr_pxi0, + msm_mux_ddr_pxi1, + msm_mux_ddr_pxi2, + msm_mux_ddr_pxi3, + msm_mux_edp_hot, + msm_mux_edp_lcd, + msm_mux_emac_phy, + msm_mux_emac_pps, + msm_mux_gcc_gp1, + msm_mux_gcc_gp2, + msm_mux_gcc_gp3, + msm_mux_gpio, + msm_mux_jitter_bist, + msm_mux_hs1_mi2s, + msm_mux_hs2_mi2s, + msm_mux_hs3_mi2s, + msm_mux_lpass_slimbus, + msm_mux_mdp_vsync, + msm_mux_mdp_vsync0, + msm_mux_mdp_vsync1, + msm_mux_mdp_vsync2, + msm_mux_mdp_vsync3, + msm_mux_mss_lte, + msm_mux_m_voc, + msm_mux_nav_pps, + msm_mux_pa_indicator, + msm_mux_pci_e0, + msm_mux_pci_e1, + msm_mux_phase_flag, + msm_mux_pll_bist, + msm_mux_pll_bypassnl, + msm_mux_pll_reset, + msm_mux_pri_mi2s, + msm_mux_pri_mi2s_ws, + msm_mux_prng_rosc, + msm_mux_qdss, + msm_mux_qdss_cti, + msm_mux_qlink_enable, + msm_mux_qlink_request, + msm_mux_qspi0, + msm_mux_qspi1, + msm_mux_qspi2, + msm_mux_qspi3, + msm_mux_qspi_clk, + msm_mux_qspi_cs, + msm_mux_qua_mi2s, + msm_mux_qup0, + msm_mux_qup1, + msm_mux_qup2, + msm_mux_qup3, + msm_mux_qup4, + msm_mux_qup5, + msm_mux_qup6, + msm_mux_qup7, + msm_mux_qup8, + msm_mux_qup9, + msm_mux_qup10, + msm_mux_qup11, + msm_mux_qup12, + msm_mux_qup13, + msm_mux_qup14, + msm_mux_qup15, + msm_mux_qup16, + msm_mux_qup17, + msm_mux_qup18, + msm_mux_qup19, + msm_mux_qup_l4, + msm_mux_qup_l5, + msm_mux_qup_l6, + msm_mux_rgmii, + msm_mux_sdc4, + msm_mux_sd_write, + msm_mux_sec_mi2s, + msm_mux_spkr_i2s, + msm_mux_sp_cmu, + msm_mux_ter_mi2s, + msm_mux_tgu_ch0, + msm_mux_tgu_ch2, + msm_mux_tgu_ch1, + msm_mux_tgu_ch3, + msm_mux_tsense_pwm1, + msm_mux_tsense_pwm2, + msm_mux_tsif1, + msm_mux_tsif2, + msm_mux_uim1, + msm_mux_uim2, + msm_mux_uim_batt, + msm_mux_usb2phy_ac, + msm_mux_usb_phy, + msm_mux_vfr_1, + msm_mux_vsense_trigger, + msm_mux_wlan1_adc1, + msm_mux_wlan1_adc0, + msm_mux_wlan2_adc1, + msm_mux_wlan2_adc0, + msm_mux_wmss_reset, + msm_mux__, +}; + +static const char * const phase_flag_groups[] = { + "gpio18", "gpio19", "gpio20", "gpio55", "gpio56", + "gpio57", "gpio59", "gpio64", "gpio68", "gpio76", + "gpio79", "gpio80", "gpio90", "gpio91", "gpio92", + "gpio93", "gpio94", "gpio96", "gpio114", "gpio115", + "gpio116", "gpio117", "gpio118", "gpio119", "gpio120", + "gpio121", "gpio122", "gpio126", "gpio127", "gpio128", + "gpio144", "gpio145", +}; + +static const char * const emac_pps_groups[] = { + "gpio81", +}; + +static const char * const qup12_groups[] = { + "gpio83", "gpio84", "gpio85", "gpio86", +}; + +static const char * const qup16_groups[] = { + "gpio83", "gpio84", "gpio85", "gpio86", +}; + +static const char * const tsif1_groups[] = { + "gpio88", "gpio89", "gpio90", "gpio91", "gpio97", +}; + +static const char * const qup8_groups[] = { + "gpio88", "gpio89", "gpio90", "gpio91", +}; + +static const char * const qspi_cs_groups[] = { + "gpio88", "gpio94", +}; + +static const char * const tgu_ch3_groups[] = { + "gpio88", +}; + +static const char * const qspi0_groups[] = { + "gpio89", +}; + +static const char * const mdp_vsync0_groups[] = { + "gpio89", +}; + +static const char * const mdp_vsync1_groups[] = { + "gpio89", +}; + +static const char * const mdp_vsync2_groups[] = { + "gpio89", +}; + +static const char * const mdp_vsync3_groups[] = { + "gpio89", +}; + +static const char * const tgu_ch0_groups[] = { + "gpio89", +}; + +static const char * const qspi1_groups[] = { + "gpio90", +}; + +static const char * const sdc4_groups[] = { + "gpio90", "gpio91", "gpio92", "gpio93", "gpio94", "gpio95", +}; + +static const char * const tgu_ch1_groups[] = { + "gpio90", +}; + +static const char * const wlan1_adc1_groups[] = { + "gpio90", +}; + +static const char * const qspi2_groups[] = { + "gpio91", +}; + +static const char * const vfr_1_groups[] = { + "gpio91", +}; + +static const char * const tgu_ch2_groups[] = { + "gpio91", +}; + +static const char * const wlan1_adc0_groups[] = { + "gpio91", +}; + +static const char * const tsif2_groups[] = { + "gpio92", "gpio93", "gpio94", "gpio95", "gpio96", +}; + +static const char * const qup11_groups[] = { + "gpio92", "gpio93", "gpio94", "gpio95", +}; + +static const char * const qspi_clk_groups[] = { + "gpio92", +}; + +static const char * const wlan2_adc1_groups[] = { + "gpio92", +}; + +static const char * const qspi3_groups[] = { + "gpio93", +}; + +static const char * const wlan2_adc0_groups[] = { + "gpio93", +}; + +static const char * const sd_write_groups[] = { + "gpio97", +}; + +static const char * const qup7_groups[] = { + "gpio98", "gpio99", "gpio100", "gpio101", +}; + +static const char * const ddr_bist_groups[] = { + "gpio98", "gpio99", "gpio145", "gpio146", +}; + +static const char * const ddr_pxi3_groups[] = { + "gpio98", "gpio101", +}; + +static const char * const atest_usb13_groups[] = { + "gpio99", +}; + +static const char * const ddr_pxi1_groups[] = { + "gpio99", "gpio100", +}; + +static const char * const pll_bypassnl_groups[] = { + "gpio100", +}; + +static const char * const atest_usb12_groups[] = { + "gpio100", +}; + +static const char * const pll_reset_groups[] = { + "gpio101", +}; + +static const char * const pci_e1_groups[] = { + "gpio102", "gpio103", +}; + +static const char * const uim2_groups[] = { + "gpio105", "gpio106", "gpio107", "gpio108", +}; + +static const char * const uim1_groups[] = { + "gpio109", "gpio110", "gpio111", "gpio112", +}; + +static const char * const uim_batt_groups[] = { + "gpio113", +}; + +static const char * const usb2phy_ac_groups[] = { + "gpio113", "gpio123", +}; + +static const char * const aoss_cti_groups[] = { + "gpio113", +}; + +static const char * const qup1_groups[] = { + "gpio114", "gpio115", "gpio116", "gpio117", +}; + +static const char * const rgmii_groups[] = { + "gpio4", "gpio5", "gpio6", "gpio7", "gpio59", + "gpio114", "gpio115", "gpio116", "gpio117", + "gpio118", "gpio119", "gpio120", "gpio121", "gpio122", +}; + +static const char * const adsp_ext_groups[] = { + "gpio115", +}; + +static const char * const qup5_groups[] = { + "gpio119", "gpio120", "gpio121", "gpio122", +}; + +static const char * const atest_usb22_groups[] = { + "gpio123", +}; + +static const char * const emac_phy_groups[] = { + "gpio124", +}; + +static const char * const hs3_mi2s_groups[] = { + "gpio125", "gpio165", "gpio166", "gpio167", "gpio168", +}; + +static const char * const sec_mi2s_groups[] = { + "gpio126", "gpio127", "gpio128", "gpio129", "gpio130", +}; + +static const char * const qup2_groups[] = { + "gpio126", "gpio127", "gpio128", "gpio129", +}; + +static const char * const jitter_bist_groups[] = { + "gpio129", +}; + +static const char * const atest_usb21_groups[] = { + "gpio129", +}; + +static const char * const pll_bist_groups[] = { + "gpio130", +}; + +static const char * const atest_usb20_groups[] = { + "gpio130", +}; + +static const char * const atest_char0_groups[] = { + "gpio130", +}; + +static const char * const ter_mi2s_groups[] = { + "gpio131", "gpio132", "gpio133", "gpio134", "gpio135", +}; + +static const char * const gcc_gp1_groups[] = { + "gpio131", "gpio136", +}; + +static const char * const atest_char1_groups[] = { + "gpio133", +}; + +static const char * const atest_char2_groups[] = { + "gpio134", +}; + +static const char * const atest_char3_groups[] = { + "gpio135", +}; + +static const char * const qua_mi2s_groups[] = { + "gpio136", "gpio137", "gpio138", "gpio139", "gpio140", "gpio141", + "gpio142", +}; + +static const char * const pri_mi2s_groups[] = { + "gpio143", "gpio144", "gpio146", "gpio147", +}; + +static const char * const qup3_groups[] = { + "gpio144", "gpio145", "gpio146", "gpio147", +}; + +static const char * const ddr_pxi0_groups[] = { + "gpio144", "gpio145", +}; + +static const char * const pri_mi2s_ws_groups[] = { + "gpio145", +}; + +static const char * const vsense_trigger_groups[] = { + "gpio145", +}; + +static const char * const atest_usb1_groups[] = { + "gpio145", +}; + +static const char * const atest_usb11_groups[] = { + "gpio146", +}; + +static const char * const ddr_pxi2_groups[] = { + "gpio146", "gpio147", +}; + +static const char * const dbg_out_groups[] = { + "gpio147", +}; + +static const char * const atest_usb10_groups[] = { + "gpio147", +}; + +static const char * const spkr_i2s_groups[] = { + "gpio148", "gpio149", "gpio150", "gpio151", "gpio152", +}; + +static const char * const audio_ref_groups[] = { + "gpio148", +}; + +static const char * const lpass_slimbus_groups[] = { + "gpio149", "gpio150", "gpio151", "gpio152", +}; + +static const char * const tsense_pwm1_groups[] = { + "gpio150", +}; + +static const char * const tsense_pwm2_groups[] = { + "gpio150", +}; + +static const char * const btfm_slimbus_groups[] = { + "gpio153", "gpio154", +}; + +static const char * const hs1_mi2s_groups[] = { + "gpio155", "gpio156", "gpio157", "gpio158", "gpio159", +}; + +static const char * const cri_trng0_groups[] = { + "gpio159", +}; + +static const char * const hs2_mi2s_groups[] = { + "gpio160", "gpio161", "gpio162", "gpio163", "gpio164", +}; + +static const char * const cri_trng1_groups[] = { + "gpio160", +}; + +static const char * const cri_trng_groups[] = { + "gpio161", +}; + +static const char * const sp_cmu_groups[] = { + "gpio162", +}; + +static const char * const prng_rosc_groups[] = { + "gpio163", +}; + +static const char * const qup0_groups[] = { + "gpio0", "gpio1", "gpio2", "gpio3", +}; + +static const char * const gpio_groups[] = { + "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7", + "gpio8", "gpio9", "gpio10", "gpio11", "gpio12", "gpio13", "gpio14", + "gpio15", "gpio16", "gpio17", "gpio18", "gpio19", "gpio20", "gpio21", + "gpio22", "gpio23", "gpio24", "gpio25", "gpio26", "gpio27", "gpio28", + "gpio29", "gpio30", "gpio31", "gpio32", "gpio33", "gpio34", "gpio35", + "gpio36", "gpio37", "gpio38", "gpio39", "gpio40", "gpio41", "gpio42", + "gpio43", "gpio44", "gpio45", "gpio46", "gpio47", "gpio48", "gpio49", + "gpio50", "gpio51", "gpio52", "gpio53", "gpio54", "gpio55", "gpio56", + "gpio57", "gpio58", "gpio59", "gpio60", "gpio61", "gpio62", "gpio63", + "gpio64", "gpio65", "gpio66", "gpio67", "gpio68", "gpio69", "gpio70", + "gpio71", "gpio72", "gpio73", "gpio74", "gpio75", "gpio76", "gpio77", + "gpio78", "gpio79", "gpio80", "gpio81", "gpio82", "gpio83", "gpio84", + "gpio85", "gpio86", "gpio87", "gpio88", "gpio89", "gpio90", "gpio91", + "gpio92", "gpio93", "gpio94", "gpio95", "gpio96", "gpio97", "gpio98", + "gpio99", "gpio100", "gpio101", "gpio102", "gpio103", "gpio104", + "gpio105", "gpio106", "gpio107", "gpio108", "gpio109", "gpio110", + "gpio111", "gpio112", "gpio113", "gpio114", "gpio115", "gpio116", + "gpio117", "gpio118", "gpio119", "gpio120", "gpio121", "gpio122", + "gpio123", "gpio124", "gpio125", "gpio126", "gpio127", "gpio128", + "gpio129", "gpio130", "gpio131", "gpio132", "gpio133", "gpio134", + "gpio135", "gpio136", "gpio137", "gpio138", "gpio139", "gpio140", + "gpio141", "gpio142", "gpio143", "gpio144", "gpio145", "gpio146", + "gpio147", "gpio148", "gpio149", "gpio150", "gpio151", "gpio152", + "gpio153", "gpio154", "gpio155", "gpio156", "gpio157", "gpio158", + "gpio159", "gpio160", "gpio161", "gpio162", "gpio163", "gpio164", + "gpio165", "gpio166", "gpio167", "gpio168", "gpio169", "gpio170", + "gpio171", "gpio172", "gpio173", "gpio174", +}; + +static const char * const qup6_groups[] = { + "gpio4", "gpio5", "gpio6", "gpio7", +}; + +static const char * const qup_l6_groups[] = { + "gpio6", "gpio34", "gpio97", "gpio123", +}; + +static const char * const qup_l5_groups[] = { + "gpio7", "gpio33", "gpio82", "gpio96", +}; + +static const char * const mdp_vsync_groups[] = { + "gpio8", "gpio9", "gpio10", "gpio81", "gpio82", +}; + +static const char * const edp_lcd_groups[] = { + "gpio9", +}; + +static const char * const qup10_groups[] = { + "gpio9", "gpio10", "gpio11", "gpio12", +}; + +static const char * const m_voc_groups[] = { + "gpio10", +}; + +static const char * const edp_hot_groups[] = { + "gpio10", +}; + +static const char * const cam_mclk_groups[] = { + "gpio13", "gpio14", "gpio15", "gpio16", +}; + +static const char * const qdss_groups[] = { + "gpio13", "gpio14", "gpio15", "gpio16", "gpio17", + "gpio18", "gpio19", "gpio20", "gpio21", "gpio22", + "gpio23", "gpio24", "gpio25", "gpio26", "gpio27", + "gpio28", "gpio29", "gpio30", "gpio31", "gpio32", + "gpio33", "gpio39", "gpio40", "gpio41", "gpio42", + "gpio47", "gpio48", "gpio83", "gpio117", "gpio118", + "gpio119", "gpio120", "gpio121", "gpio132", + "gpio133", "gpio134", +}; + +static const char * const cci_i2c_groups[] = { + "gpio17", "gpio18", "gpio19", "gpio20", "gpio31", "gpio32", "gpio33", + "gpio34", +}; + +static const char * const cci_timer0_groups[] = { + "gpio21", +}; + +static const char * const gcc_gp2_groups[] = { + "gpio21", "gpio137", +}; + +static const char * const cci_timer1_groups[] = { + "gpio22", +}; + +static const char * const gcc_gp3_groups[] = { + "gpio22", "gpio138", +}; + +static const char * const cci_timer2_groups[] = { + "gpio23", +}; + +static const char * const qup18_groups[] = { + "gpio23", "gpio24", "gpio25", "gpio26", +}; + +static const char * const cci_timer3_groups[] = { + "gpio24", +}; + +static const char * const cci_async_groups[] = { + "gpio24", "gpio25", "gpio26", +}; + +static const char * const cci_timer4_groups[] = { + "gpio25", +}; + +static const char * const qup15_groups[] = { + "gpio27", "gpio28", "gpio29", "gpio30", +}; + +static const char * const pci_e0_groups[] = { + "gpio35", "gpio36", +}; + +static const char * const qup_l4_groups[] = { + "gpio37", "gpio59", "gpio81", "gpio95", +}; + +static const char * const agera_pll_groups[] = { + "gpio37", +}; + +static const char * const usb_phy_groups[] = { + "gpio38", +}; + +static const char * const qup9_groups[] = { + "gpio39", "gpio40", "gpio41", "gpio42", +}; + +static const char * const qup13_groups[] = { + "gpio43", "gpio44", "gpio45", "gpio46", +}; + +static const char * const qdss_cti_groups[] = { + "gpio45", "gpio46", "gpio49", "gpio50", "gpio56", "gpio57", "gpio58", + "gpio58", +}; + +static const char * const qup14_groups[] = { + "gpio47", "gpio48", "gpio49", "gpio50", +}; + +static const char * const qup4_groups[] = { + "gpio51", "gpio52", "gpio53", "gpio54", +}; + +static const char * const qup17_groups[] = { + "gpio55", "gpio56", "gpio57", "gpio58", +}; + +static const char * const qup19_groups[] = { + "gpio55", "gpio56", "gpio57", "gpio58", +}; + +static const char * const atest_char_groups[] = { + "gpio59", +}; + +static const char * const nav_pps_groups[] = { + "gpio60", "gpio60", "gpio76", "gpio76", "gpio77", "gpio77", "gpio81", + "gpio81", "gpio82", "gpio82", +}; + +static const char * const atest_usb2_groups[] = { + "gpio60", +}; + +static const char * const qlink_request_groups[] = { + "gpio61", +}; + +static const char * const qlink_enable_groups[] = { + "gpio62", +}; + +static const char * const wmss_reset_groups[] = { + "gpio63", +}; + +static const char * const atest_usb23_groups[] = { + "gpio63", +}; + +static const char * const pa_indicator_groups[] = { + "gpio68", +}; + +static const char * const mss_lte_groups[] = { + "gpio69", "gpio70", +}; + +static const struct pinfunction sm8150_functions[] = { + MSM_PIN_FUNCTION(adsp_ext), + MSM_PIN_FUNCTION(agera_pll), + MSM_PIN_FUNCTION(aoss_cti), + MSM_PIN_FUNCTION(ddr_pxi2), + MSM_PIN_FUNCTION(atest_char), + MSM_PIN_FUNCTION(atest_char0), + MSM_PIN_FUNCTION(atest_char1), + MSM_PIN_FUNCTION(atest_char2), + MSM_PIN_FUNCTION(atest_char3), + MSM_PIN_FUNCTION(audio_ref), + MSM_PIN_FUNCTION(atest_usb1), + MSM_PIN_FUNCTION(atest_usb2), + MSM_PIN_FUNCTION(atest_usb10), + MSM_PIN_FUNCTION(atest_usb11), + MSM_PIN_FUNCTION(atest_usb12), + MSM_PIN_FUNCTION(atest_usb13), + MSM_PIN_FUNCTION(atest_usb20), + MSM_PIN_FUNCTION(atest_usb21), + MSM_PIN_FUNCTION(atest_usb22), + MSM_PIN_FUNCTION(atest_usb23), + MSM_PIN_FUNCTION(btfm_slimbus), + MSM_PIN_FUNCTION(cam_mclk), + MSM_PIN_FUNCTION(cci_async), + MSM_PIN_FUNCTION(cci_i2c), + MSM_PIN_FUNCTION(cci_timer0), + MSM_PIN_FUNCTION(cci_timer1), + MSM_PIN_FUNCTION(cci_timer2), + MSM_PIN_FUNCTION(cci_timer3), + MSM_PIN_FUNCTION(cci_timer4), + MSM_PIN_FUNCTION(cri_trng), + MSM_PIN_FUNCTION(cri_trng0), + MSM_PIN_FUNCTION(cri_trng1), + MSM_PIN_FUNCTION(dbg_out), + MSM_PIN_FUNCTION(ddr_bist), + MSM_PIN_FUNCTION(ddr_pxi0), + MSM_PIN_FUNCTION(ddr_pxi1), + MSM_PIN_FUNCTION(ddr_pxi3), + MSM_PIN_FUNCTION(edp_hot), + MSM_PIN_FUNCTION(edp_lcd), + MSM_PIN_FUNCTION(emac_phy), + MSM_PIN_FUNCTION(emac_pps), + MSM_PIN_FUNCTION(gcc_gp1), + MSM_PIN_FUNCTION(gcc_gp2), + MSM_PIN_FUNCTION(gcc_gp3), + MSM_PIN_FUNCTION(gpio), + MSM_PIN_FUNCTION(hs1_mi2s), + MSM_PIN_FUNCTION(hs2_mi2s), + MSM_PIN_FUNCTION(hs3_mi2s), + MSM_PIN_FUNCTION(jitter_bist), + MSM_PIN_FUNCTION(lpass_slimbus), + MSM_PIN_FUNCTION(mdp_vsync), + MSM_PIN_FUNCTION(mdp_vsync0), + MSM_PIN_FUNCTION(mdp_vsync1), + MSM_PIN_FUNCTION(mdp_vsync2), + MSM_PIN_FUNCTION(mdp_vsync3), + MSM_PIN_FUNCTION(mss_lte), + MSM_PIN_FUNCTION(m_voc), + MSM_PIN_FUNCTION(nav_pps), + MSM_PIN_FUNCTION(pa_indicator), + MSM_PIN_FUNCTION(pci_e0), + MSM_PIN_FUNCTION(phase_flag), + MSM_PIN_FUNCTION(pll_bypassnl), + MSM_PIN_FUNCTION(pll_bist), + MSM_PIN_FUNCTION(pci_e1), + MSM_PIN_FUNCTION(pll_reset), + MSM_PIN_FUNCTION(pri_mi2s), + MSM_PIN_FUNCTION(pri_mi2s_ws), + MSM_PIN_FUNCTION(prng_rosc), + MSM_PIN_FUNCTION(qdss), + MSM_PIN_FUNCTION(qdss_cti), + MSM_PIN_FUNCTION(qlink_request), + MSM_PIN_FUNCTION(qlink_enable), + MSM_PIN_FUNCTION(qspi0), + MSM_PIN_FUNCTION(qspi1), + MSM_PIN_FUNCTION(qspi2), + MSM_PIN_FUNCTION(qspi3), + MSM_PIN_FUNCTION(qspi_clk), + MSM_PIN_FUNCTION(qspi_cs), + MSM_PIN_FUNCTION(qua_mi2s), + MSM_PIN_FUNCTION(qup0), + MSM_PIN_FUNCTION(qup1), + MSM_PIN_FUNCTION(qup2), + MSM_PIN_FUNCTION(qup3), + MSM_PIN_FUNCTION(qup4), + MSM_PIN_FUNCTION(qup5), + MSM_PIN_FUNCTION(qup6), + MSM_PIN_FUNCTION(qup7), + MSM_PIN_FUNCTION(qup8), + MSM_PIN_FUNCTION(qup9), + MSM_PIN_FUNCTION(qup10), + MSM_PIN_FUNCTION(qup11), + MSM_PIN_FUNCTION(qup12), + MSM_PIN_FUNCTION(qup13), + MSM_PIN_FUNCTION(qup14), + MSM_PIN_FUNCTION(qup15), + MSM_PIN_FUNCTION(qup16), + MSM_PIN_FUNCTION(qup17), + MSM_PIN_FUNCTION(qup18), + MSM_PIN_FUNCTION(qup19), + MSM_PIN_FUNCTION(qup_l4), + MSM_PIN_FUNCTION(qup_l5), + MSM_PIN_FUNCTION(qup_l6), + MSM_PIN_FUNCTION(rgmii), + MSM_PIN_FUNCTION(sdc4), + MSM_PIN_FUNCTION(sd_write), + MSM_PIN_FUNCTION(sec_mi2s), + MSM_PIN_FUNCTION(spkr_i2s), + MSM_PIN_FUNCTION(sp_cmu), + MSM_PIN_FUNCTION(ter_mi2s), + MSM_PIN_FUNCTION(tgu_ch0), + MSM_PIN_FUNCTION(tgu_ch1), + MSM_PIN_FUNCTION(tgu_ch2), + MSM_PIN_FUNCTION(tgu_ch3), + MSM_PIN_FUNCTION(tsense_pwm1), + MSM_PIN_FUNCTION(tsense_pwm2), + MSM_PIN_FUNCTION(tsif1), + MSM_PIN_FUNCTION(tsif2), + MSM_PIN_FUNCTION(uim1), + MSM_PIN_FUNCTION(uim2), + MSM_PIN_FUNCTION(uim_batt), + MSM_PIN_FUNCTION(usb2phy_ac), + MSM_PIN_FUNCTION(usb_phy), + MSM_PIN_FUNCTION(vfr_1), + MSM_PIN_FUNCTION(vsense_trigger), + MSM_PIN_FUNCTION(wlan1_adc0), + MSM_PIN_FUNCTION(wlan1_adc1), + MSM_PIN_FUNCTION(wlan2_adc0), + MSM_PIN_FUNCTION(wlan2_adc1), + MSM_PIN_FUNCTION(wmss_reset), +}; + +/* + * Every pin is maintained as a single group, and missing or non-existing pin + * would be maintained as dummy group to synchronize pin group index with + * pin descriptor registered with pinctrl core. + * Clients would not be able to request these dummy pin groups. + */ +static const struct msm_pingroup sm8150_groups[] = { + [0] = PINGROUP(0, SOUTH, qup0, _, _, _, _, _, _, _, _), + [1] = PINGROUP(1, SOUTH, qup0, _, _, _, _, _, _, _, _), + [2] = PINGROUP(2, SOUTH, qup0, _, _, _, _, _, _, _, _), + [3] = PINGROUP(3, SOUTH, qup0, _, _, _, _, _, _, _, _), + [4] = PINGROUP(4, SOUTH, qup6, rgmii, _, _, _, _, _, _, _), + [5] = PINGROUP(5, SOUTH, qup6, rgmii, _, _, _, _, _, _, _), + [6] = PINGROUP(6, SOUTH, qup6, rgmii, qup_l6, _, _, _, _, _, _), + [7] = PINGROUP(7, SOUTH, qup6, rgmii, qup_l5, _, _, _, _, _, _), + [8] = PINGROUP(8, NORTH, mdp_vsync, _, _, _, _, _, _, _, _), + [9] = PINGROUP(9, NORTH, mdp_vsync, edp_lcd, qup10, _, _, _, _, _, _), + [10] = PINGROUP(10, NORTH, mdp_vsync, m_voc, edp_hot, qup10, _, _, _, _, _), + [11] = PINGROUP(11, NORTH, qup10, _, _, _, _, _, _, _, _), + [12] = PINGROUP(12, NORTH, qup10, _, _, _, _, _, _, _, _), + [13] = PINGROUP(13, NORTH, cam_mclk, qdss, _, _, _, _, _, _, _), + [14] = PINGROUP(14, NORTH, cam_mclk, qdss, _, _, _, _, _, _, _), + [15] = PINGROUP(15, NORTH, cam_mclk, qdss, _, _, _, _, _, _, _), + [16] = PINGROUP(16, NORTH, cam_mclk, qdss, _, _, _, _, _, _, _), + [17] = PINGROUP(17, NORTH, cci_i2c, qdss, _, _, _, _, _, _, _), + [18] = PINGROUP(18, NORTH, cci_i2c, phase_flag, _, qdss, _, _, _, _, _), + [19] = PINGROUP(19, NORTH, cci_i2c, phase_flag, _, qdss, _, _, _, _, _), + [20] = PINGROUP(20, NORTH, cci_i2c, phase_flag, _, qdss, _, _, _, _, _), + [21] = PINGROUP(21, EAST, cci_timer0, gcc_gp2, qdss, _, _, _, _, _, _), + [22] = PINGROUP(22, EAST, cci_timer1, gcc_gp3, qdss, _, _, _, _, _, _), + [23] = PINGROUP(23, EAST, cci_timer2, qup18, qdss, _, _, _, _, _, _), + [24] = PINGROUP(24, EAST, cci_timer3, cci_async, qup18, qdss, _, _, _, _, _), + [25] = PINGROUP(25, EAST, cci_timer4, cci_async, qup18, qdss, _, _, _, _, _), + [26] = PINGROUP(26, EAST, cci_async, qup18, qdss, _, _, _, _, _, _), + [27] = PINGROUP(27, EAST, qup15, _, qdss, _, _, _, _, _, _), + [28] = PINGROUP(28, EAST, qup15, qdss, _, _, _, _, _, _, _), + [29] = PINGROUP(29, EAST, qup15, qdss, _, _, _, _, _, _, _), + [30] = PINGROUP(30, EAST, qup15, qdss, _, _, _, _, _, _, _), + [31] = PINGROUP(31, NORTH, cci_i2c, qdss, _, _, _, _, _, _, _), + [32] = PINGROUP(32, NORTH, cci_i2c, qdss, _, _, _, _, _, _, _), + [33] = PINGROUP(33, NORTH, cci_i2c, qup_l5, qdss, _, _, _, _, _, _), + [34] = PINGROUP(34, NORTH, cci_i2c, qup_l6, _, _, _, _, _, _, _), + [35] = PINGROUP(35, NORTH, pci_e0, _, _, _, _, _, _, _, _), + [36] = PINGROUP(36, NORTH, pci_e0, _, _, _, _, _, _, _, _), + [37] = PINGROUP(37, NORTH, qup_l4, agera_pll, _, _, _, _, _, _, _), + [38] = PINGROUP(38, SOUTH, usb_phy, _, _, _, _, _, _, _, _), + [39] = PINGROUP(39, NORTH, qup9, qdss, _, _, _, _, _, _, _), + [40] = PINGROUP(40, NORTH, qup9, qdss, _, _, _, _, _, _, _), + [41] = PINGROUP(41, NORTH, qup9, qdss, _, _, _, _, _, _, _), + [42] = PINGROUP(42, NORTH, qup9, qdss, _, _, _, _, _, _, _), + [43] = PINGROUP(43, EAST, qup13, _, _, _, _, _, _, _, _), + [44] = PINGROUP(44, EAST, qup13, _, _, _, _, _, _, _, _), + [45] = PINGROUP(45, EAST, qup13, qdss_cti, _, _, _, _, _, _, _), + [46] = PINGROUP(46, EAST, qup13, qdss_cti, _, _, _, _, _, _, _), + [47] = PINGROUP(47, EAST, qup14, qdss, _, _, _, _, _, _, _), + [48] = PINGROUP(48, EAST, qup14, qdss, _, _, _, _, _, _, _), + [49] = PINGROUP(49, EAST, qup14, _, qdss_cti, _, _, _, _, _, _), + [50] = PINGROUP(50, EAST, qup14, qdss_cti, _, _, _, _, _, _, _), + [51] = PINGROUP(51, SOUTH, qup4, _, _, _, _, _, _, _, _), + [52] = PINGROUP(52, SOUTH, qup4, _, _, _, _, _, _, _, _), + [53] = PINGROUP(53, SOUTH, qup4, _, _, _, _, _, _, _, _), + [54] = PINGROUP(54, SOUTH, qup4, _, _, _, _, _, _, _, _), + [55] = PINGROUP(55, SOUTH, qup17, qup19, phase_flag, _, _, _, _, _, _), + [56] = PINGROUP(56, SOUTH, qup17, qup19, qdss_cti, phase_flag, _, _, _, _, _), + [57] = PINGROUP(57, SOUTH, qup17, qup19, qdss_cti, phase_flag, _, _, _, _, _), + [58] = PINGROUP(58, SOUTH, qup17, qup19, qdss_cti, phase_flag, _, _, _, _, _), + [59] = PINGROUP(59, SOUTH, rgmii, qup_l4, phase_flag, _, atest_char, _, _, _, _), + [60] = PINGROUP(60, SOUTH, _, nav_pps, nav_pps, atest_usb2, _, _, _, _, _), + [61] = PINGROUP(61, SOUTH, qlink_request, _, _, _, _, _, _, _, _), + [62] = PINGROUP(62, SOUTH, qlink_enable, _, _, _, _, _, _, _, _), + [63] = PINGROUP(63, SOUTH, wmss_reset, atest_usb23, _, _, _, _, _, _, _), + [64] = PINGROUP(64, SOUTH, _, phase_flag, _, _, _, _, _, _, _), + [65] = PINGROUP(65, SOUTH, _, _, _, _, _, _, _, _, _), + [66] = PINGROUP(66, SOUTH, _, _, _, _, _, _, _, _, _), + [67] = PINGROUP(67, SOUTH, _, _, _, _, _, _, _, _, _), + [68] = PINGROUP(68, SOUTH, _, pa_indicator, phase_flag, _, _, _, _, _, _), + [69] = PINGROUP(69, SOUTH, mss_lte, _, _, _, _, _, _, _, _), + [70] = PINGROUP(70, SOUTH, mss_lte, _, _, _, _, _, _, _, _), + [71] = PINGROUP(71, SOUTH, _, _, _, _, _, _, _, _, _), + [72] = PINGROUP(72, SOUTH, _, _, _, _, _, _, _, _, _), + [73] = PINGROUP(73, SOUTH, _, _, _, _, _, _, _, _, _), + [74] = PINGROUP(74, SOUTH, _, _, _, _, _, _, _, _, _), + [75] = PINGROUP(75, SOUTH, _, _, _, _, _, _, _, _, _), + [76] = PINGROUP(76, SOUTH, _, _, _, nav_pps, nav_pps, phase_flag, _, _, _), + [77] = PINGROUP(77, SOUTH, _, _, _, nav_pps, nav_pps, _, _, _, _), + [78] = PINGROUP(78, SOUTH, _, _, _, _, _, _, _, _, _), + [79] = PINGROUP(79, SOUTH, _, _, phase_flag, _, _, _, _, _, _), + [80] = PINGROUP(80, SOUTH, _, _, phase_flag, _, _, _, _, _, _), + [81] = PINGROUP(81, SOUTH, _, _, _, nav_pps, nav_pps, qup_l4, mdp_vsync, emac_pps, _), + [82] = PINGROUP(82, SOUTH, _, _, _, nav_pps, nav_pps, qup_l5, mdp_vsync, _, _), + [83] = PINGROUP(83, NORTH, qup12, qup16, _, qdss, _, _, _, _, _), + [84] = PINGROUP(84, NORTH, qup12, qup16, _, _, _, _, _, _, _), + [85] = PINGROUP(85, NORTH, qup12, qup16, _, _, _, _, _, _, _), + [86] = PINGROUP(86, NORTH, qup12, qup16, _, _, _, _, _, _, _), + [87] = PINGROUP(87, EAST, _, _, _, _, _, _, _, _, _), + [88] = PINGROUP(88, NORTH, tsif1, qup8, qspi_cs, tgu_ch3, _, _, _, _, _), + [89] = PINGROUP(89, NORTH, tsif1, qup8, qspi0, mdp_vsync0, mdp_vsync1, mdp_vsync2, mdp_vsync3, tgu_ch0, _), + [90] = PINGROUP(90, NORTH, tsif1, qup8, qspi1, sdc4, phase_flag, tgu_ch1, _, _, wlan1_adc1), + [91] = PINGROUP(91, NORTH, tsif1, qup8, qspi2, sdc4, vfr_1, phase_flag, tgu_ch2, _, _), + [92] = PINGROUP(92, NORTH, tsif2, qup11, qspi_clk, sdc4, phase_flag, _, wlan2_adc1, _, _), + [93] = PINGROUP(93, NORTH, tsif2, qup11, qspi3, sdc4, phase_flag, _, wlan2_adc0, _, _), + [94] = PINGROUP(94, NORTH, tsif2, qup11, qspi_cs, sdc4, phase_flag, _, _, _, _), + [95] = PINGROUP(95, NORTH, tsif2, qup11, sdc4, qup_l4, _, _, _, _, _), + [96] = PINGROUP(96, NORTH, tsif2, qup_l5, phase_flag, _, _, _, _, _, _), + [97] = PINGROUP(97, NORTH, sd_write, tsif1, qup_l6, _, _, _, _, _, _), + [98] = PINGROUP(98, SOUTH, qup7, ddr_bist, ddr_pxi3, _, _, _, _, _, _), + [99] = PINGROUP(99, SOUTH, qup7, ddr_bist, atest_usb13, ddr_pxi1, _, _, _, _, _), + [100] = PINGROUP(100, SOUTH, qup7, pll_bypassnl, atest_usb12, ddr_pxi1, _, _, _, _, _), + [101] = PINGROUP(101, SOUTH, qup7, pll_reset, ddr_pxi3, _, _, _, _, _, _), + [102] = PINGROUP(102, NORTH, pci_e1, _, _, _, _, _, _, _, _), + [103] = PINGROUP(103, NORTH, pci_e1, _, _, _, _, _, _, _, _), + [104] = PINGROUP(104, NORTH, _, _, _, _, _, _, _, _, _), + [105] = PINGROUP(105, WEST, uim2, _, _, _, _, _, _, _, _), + [106] = PINGROUP(106, WEST, uim2, _, _, _, _, _, _, _, _), + [107] = PINGROUP(107, WEST, uim2, _, _, _, _, _, _, _, _), + [108] = PINGROUP(108, WEST, uim2, _, _, _, _, _, _, _, _), + [109] = PINGROUP(109, WEST, uim1, _, _, _, _, _, _, _, _), + [110] = PINGROUP(110, WEST, uim1, _, _, _, _, _, _, _, _), + [111] = PINGROUP(111, WEST, uim1, _, _, _, _, _, _, _, _), + [112] = PINGROUP(112, WEST, uim1, _, _, _, _, _, _, _, _), + [113] = PINGROUP(113, WEST, uim_batt, usb2phy_ac, aoss_cti, _, _, _, _, _, _), + [114] = PINGROUP(114, SOUTH, qup1, rgmii, phase_flag, _, _, _, _, _, _), + [115] = PINGROUP(115, SOUTH, qup1, rgmii, phase_flag, adsp_ext, _, _, _, _, _), + [116] = PINGROUP(116, SOUTH, qup1, rgmii, phase_flag, _, _, _, _, _, _), + [117] = PINGROUP(117, SOUTH, qup1, rgmii, phase_flag, _, qdss, _, _, _, _), + [118] = PINGROUP(118, SOUTH, rgmii, phase_flag, _, qdss, _, _, _, _, _), + [119] = PINGROUP(119, SOUTH, qup5, rgmii, phase_flag, _, qdss, _, _, _, _), + [120] = PINGROUP(120, SOUTH, qup5, rgmii, phase_flag, _, qdss, _, _, _, _), + [121] = PINGROUP(121, SOUTH, qup5, rgmii, phase_flag, _, qdss, _, _, _, _), + [122] = PINGROUP(122, SOUTH, qup5, rgmii, phase_flag, _, _, _, _, _, _), + [123] = PINGROUP(123, SOUTH, usb2phy_ac, qup_l6, atest_usb22, _, _, _, _, _, _), + [124] = PINGROUP(124, SOUTH, emac_phy, _, _, _, _, _, _, _, _), + [125] = PINGROUP(125, WEST, hs3_mi2s, _, _, _, _, _, _, _, _), + [126] = PINGROUP(126, SOUTH, sec_mi2s, qup2, phase_flag, _, _, _, _, _, _), + [127] = PINGROUP(127, SOUTH, sec_mi2s, qup2, phase_flag, _, _, _, _, _, _), + [128] = PINGROUP(128, SOUTH, sec_mi2s, qup2, phase_flag, _, _, _, _, _, _), + [129] = PINGROUP(129, SOUTH, sec_mi2s, qup2, jitter_bist, atest_usb21, _, _, _, _, _), + [130] = PINGROUP(130, SOUTH, sec_mi2s, pll_bist, atest_usb20, atest_char0, _, _, _, _, _), + [131] = PINGROUP(131, SOUTH, ter_mi2s, gcc_gp1, _, _, _, _, _, _, _), + [132] = PINGROUP(132, SOUTH, ter_mi2s, _, qdss, _, _, _, _, _, _), + [133] = PINGROUP(133, SOUTH, ter_mi2s, qdss, atest_char1, _, _, _, _, _, _), + [134] = PINGROUP(134, SOUTH, ter_mi2s, qdss, atest_char2, _, _, _, _, _, _), + [135] = PINGROUP(135, SOUTH, ter_mi2s, atest_char3, _, _, _, _, _, _, _), + [136] = PINGROUP(136, SOUTH, qua_mi2s, gcc_gp1, _, _, _, _, _, _, _), + [137] = PINGROUP(137, SOUTH, qua_mi2s, gcc_gp2, _, _, _, _, _, _, _), + [138] = PINGROUP(138, SOUTH, qua_mi2s, gcc_gp3, _, _, _, _, _, _, _), + [139] = PINGROUP(139, SOUTH, qua_mi2s, _, _, _, _, _, _, _, _), + [140] = PINGROUP(140, SOUTH, qua_mi2s, _, _, _, _, _, _, _, _), + [141] = PINGROUP(141, SOUTH, qua_mi2s, _, _, _, _, _, _, _, _), + [142] = PINGROUP(142, SOUTH, qua_mi2s, _, _, _, _, _, _, _, _), + [143] = PINGROUP(143, SOUTH, pri_mi2s, _, _, _, _, _, _, _, _), + [144] = PINGROUP(144, SOUTH, pri_mi2s, qup3, phase_flag, _, ddr_pxi0, _, _, _, _), + [145] = PINGROUP(145, SOUTH, pri_mi2s_ws, qup3, phase_flag, ddr_bist, _, vsense_trigger, atest_usb1, ddr_pxi0, _), + [146] = PINGROUP(146, SOUTH, pri_mi2s, qup3, ddr_bist, atest_usb11, ddr_pxi2, _, _, _, _), + [147] = PINGROUP(147, SOUTH, pri_mi2s, qup3, dbg_out, atest_usb10, ddr_pxi2, _, _, _, _), + [148] = PINGROUP(148, SOUTH, spkr_i2s, audio_ref, _, _, _, _, _, _, _), + [149] = PINGROUP(149, SOUTH, lpass_slimbus, spkr_i2s, _, _, _, _, _, _, _), + [150] = PINGROUP(150, SOUTH, lpass_slimbus, spkr_i2s, tsense_pwm1, tsense_pwm2, _, _, _, _, _), + [151] = PINGROUP(151, SOUTH, lpass_slimbus, spkr_i2s, _, _, _, _, _, _, _), + [152] = PINGROUP(152, SOUTH, lpass_slimbus, spkr_i2s, _, _, _, _, _, _, _), + [153] = PINGROUP(153, SOUTH, btfm_slimbus, _, _, _, _, _, _, _, _), + [154] = PINGROUP(154, SOUTH, btfm_slimbus, _, _, _, _, _, _, _, _), + [155] = PINGROUP(155, WEST, hs1_mi2s, _, _, _, _, _, _, _, _), + [156] = PINGROUP(156, WEST, hs1_mi2s, _, _, _, _, _, _, _, _), + [157] = PINGROUP(157, WEST, hs1_mi2s, _, _, _, _, _, _, _, _), + [158] = PINGROUP(158, WEST, hs1_mi2s, _, _, _, _, _, _, _, _), + [159] = PINGROUP(159, WEST, hs1_mi2s, cri_trng0, _, _, _, _, _, _, _), + [160] = PINGROUP(160, WEST, hs2_mi2s, cri_trng1, _, _, _, _, _, _, _), + [161] = PINGROUP(161, WEST, hs2_mi2s, cri_trng, _, _, _, _, _, _, _), + [162] = PINGROUP(162, WEST, hs2_mi2s, sp_cmu, _, _, _, _, _, _, _), + [163] = PINGROUP(163, WEST, hs2_mi2s, prng_rosc, _, _, _, _, _, _, _), + [164] = PINGROUP(164, WEST, hs2_mi2s, _, _, _, _, _, _, _, _), + [165] = PINGROUP(165, WEST, hs3_mi2s, _, _, _, _, _, _, _, _), + [166] = PINGROUP(166, WEST, hs3_mi2s, _, _, _, _, _, _, _, _), + [167] = PINGROUP(167, WEST, hs3_mi2s, _, _, _, _, _, _, _, _), + [168] = PINGROUP(168, WEST, hs3_mi2s, _, _, _, _, _, _, _, _), + [169] = PINGROUP(169, NORTH, _, _, _, _, _, _, _, _, _), + [170] = PINGROUP(170, NORTH, _, _, _, _, _, _, _, _, _), + [171] = PINGROUP(171, NORTH, _, _, _, _, _, _, _, _, _), + [172] = PINGROUP(172, NORTH, _, _, _, _, _, _, _, _, _), + [173] = PINGROUP(173, NORTH, _, _, _, _, _, _, _, _, _), + [174] = PINGROUP(174, NORTH, _, _, _, _, _, _, _, _, _), + [175] = UFS_RESET(ufs_reset, 0xB6000), + [176] = SDC_QDSD_PINGROUP(sdc2_clk, 0xB2000, 14, 6), + [177] = SDC_QDSD_PINGROUP(sdc2_cmd, 0xB2000, 11, 3), + [178] = SDC_QDSD_PINGROUP(sdc2_data, 0xB2000, 9, 0), +}; + +static const struct msm_gpio_wakeirq_map sm8150_pdc_map[] = { + { 3, 31 }, { 5, 32 }, { 8, 33 }, { 9, 34 }, { 10, 100 }, + { 12, 104 }, { 24, 37 }, { 26, 38 }, { 27, 41 }, { 28, 42 }, + { 30, 39 }, { 36, 43 }, { 37, 44 }, { 38, 30 }, { 39, 118 }, + { 39, 125 }, { 41, 47 }, { 42, 48 }, { 46, 50 }, { 47, 49 }, + { 48, 51 }, { 49, 53 }, { 50, 52 }, { 51, 116 }, { 51, 123 }, + { 53, 54 }, { 54, 55 }, { 55, 56 }, { 56, 57 }, { 58, 58 }, + { 60, 60 }, { 61, 61 }, { 68, 62 }, { 70, 63 }, { 76, 71 }, + { 77, 66 }, { 81, 64 }, { 83, 65 }, { 86, 67 }, { 87, 84 }, + { 88, 117 }, { 88, 124 }, { 90, 69 }, { 91, 70 }, { 93, 75 }, + { 95, 72 }, { 96, 73 }, { 97, 74 }, { 101, 40 }, { 103, 77 }, + { 104, 78 }, { 108, 79 }, { 112, 80 }, { 113, 81 }, { 114, 82 }, + { 117, 85 }, { 118, 101 }, { 119, 87 }, { 120, 88 }, { 121, 89 }, + { 122, 90 }, { 123, 91 }, { 124, 92 }, { 125, 93 }, { 129, 94 }, + { 132, 105 }, { 133, 83 }, { 134, 36 }, { 136, 97 }, { 142, 103 }, + { 144, 115 }, { 144, 122 }, { 147, 102 }, { 150, 107 }, + { 152, 108 }, { 153, 109 } +}; + +static const struct msm_pinctrl_soc_data sm8150_pinctrl = { + .pins = sm8150_pins, + .npins = ARRAY_SIZE(sm8150_pins), + .functions = sm8150_functions, + .nfunctions = ARRAY_SIZE(sm8150_functions), + .groups = sm8150_groups, + .ngroups = ARRAY_SIZE(sm8150_groups), + .ngpios = 176, + .tiles = sm8150_tiles, + .ntiles = ARRAY_SIZE(sm8150_tiles), + .wakeirq_map = sm8150_pdc_map, + .nwakeirq_map = ARRAY_SIZE(sm8150_pdc_map), + .wakeirq_dual_edge_errata = true, +}; + +static int sm8150_pinctrl_probe(struct platform_device *pdev) +{ + return msm_pinctrl_probe(pdev, &sm8150_pinctrl); +} + +static const struct of_device_id sm8150_pinctrl_of_match[] = { + { .compatible = "qcom,sm8150-pinctrl", }, + { }, +}; + +static struct platform_driver sm8150_pinctrl_driver = { + .driver = { + .name = "sm8150-pinctrl", + .of_match_table = sm8150_pinctrl_of_match, + }, + .probe = sm8150_pinctrl_probe, + .remove = msm_pinctrl_remove, +}; + +static int __init sm8150_pinctrl_init(void) +{ + return platform_driver_register(&sm8150_pinctrl_driver); +} +arch_initcall(sm8150_pinctrl_init); + +static void __exit sm8150_pinctrl_exit(void) +{ + platform_driver_unregister(&sm8150_pinctrl_driver); +} +module_exit(sm8150_pinctrl_exit); + +MODULE_DESCRIPTION("QTI sm8150 pinctrl driver"); +MODULE_LICENSE("GPL v2"); +MODULE_DEVICE_TABLE(of, sm8150_pinctrl_of_match); diff --git a/drivers/pinctrl/qcom/pinctrl-sm8250-lpass-lpi.c b/drivers/pinctrl/qcom/pinctrl-sm8250-lpass-lpi.c new file mode 100644 index 0000000000..ddbc6317f2 --- /dev/null +++ b/drivers/pinctrl/qcom/pinctrl-sm8250-lpass-lpi.c @@ -0,0 +1,163 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2016-2019, The Linux Foundation. All rights reserved. + * Copyright (c) 2020 Linaro Ltd. + */ + +#include <linux/gpio/driver.h> +#include <linux/module.h> +#include <linux/platform_device.h> + +#include "pinctrl-lpass-lpi.h" + +enum lpass_lpi_functions { + LPI_MUX_dmic1_clk, + LPI_MUX_dmic1_data, + LPI_MUX_dmic2_clk, + LPI_MUX_dmic2_data, + LPI_MUX_dmic3_clk, + LPI_MUX_dmic3_data, + LPI_MUX_i2s1_clk, + LPI_MUX_i2s1_data, + LPI_MUX_i2s1_ws, + LPI_MUX_i2s2_clk, + LPI_MUX_i2s2_data, + LPI_MUX_i2s2_ws, + LPI_MUX_qua_mi2s_data, + LPI_MUX_qua_mi2s_sclk, + LPI_MUX_qua_mi2s_ws, + LPI_MUX_swr_rx_clk, + LPI_MUX_swr_rx_data, + LPI_MUX_swr_tx_clk, + LPI_MUX_swr_tx_data, + LPI_MUX_wsa_swr_clk, + LPI_MUX_wsa_swr_data, + LPI_MUX_gpio, + LPI_MUX__, +}; + +static int gpio0_pins[] = { 0 }; +static int gpio1_pins[] = { 1 }; +static int gpio2_pins[] = { 2 }; +static int gpio3_pins[] = { 3 }; +static int gpio4_pins[] = { 4 }; +static int gpio5_pins[] = { 5 }; +static int gpio6_pins[] = { 6 }; +static int gpio7_pins[] = { 7 }; +static int gpio8_pins[] = { 8 }; +static int gpio9_pins[] = { 9 }; +static int gpio10_pins[] = { 10 }; +static int gpio11_pins[] = { 11 }; +static int gpio12_pins[] = { 12 }; +static int gpio13_pins[] = { 13 }; + +static const struct pinctrl_pin_desc sm8250_lpi_pins[] = { + PINCTRL_PIN(0, "gpio0"), + PINCTRL_PIN(1, "gpio1"), + PINCTRL_PIN(2, "gpio2"), + PINCTRL_PIN(3, "gpio3"), + PINCTRL_PIN(4, "gpio4"), + PINCTRL_PIN(5, "gpio5"), + PINCTRL_PIN(6, "gpio6"), + PINCTRL_PIN(7, "gpio7"), + PINCTRL_PIN(8, "gpio8"), + PINCTRL_PIN(9, "gpio9"), + PINCTRL_PIN(10, "gpio10"), + PINCTRL_PIN(11, "gpio11"), + PINCTRL_PIN(12, "gpio12"), + PINCTRL_PIN(13, "gpio13"), +}; + +static const char * const swr_tx_clk_groups[] = { "gpio0" }; +static const char * const swr_tx_data_groups[] = { "gpio1", "gpio2", "gpio5" }; +static const char * const swr_rx_clk_groups[] = { "gpio3" }; +static const char * const swr_rx_data_groups[] = { "gpio4", "gpio5" }; +static const char * const dmic1_clk_groups[] = { "gpio6" }; +static const char * const dmic1_data_groups[] = { "gpio7" }; +static const char * const dmic2_clk_groups[] = { "gpio8" }; +static const char * const dmic2_data_groups[] = { "gpio9" }; +static const char * const i2s2_clk_groups[] = { "gpio10" }; +static const char * const i2s2_ws_groups[] = { "gpio11" }; +static const char * const dmic3_clk_groups[] = { "gpio12" }; +static const char * const dmic3_data_groups[] = { "gpio13" }; +static const char * const qua_mi2s_sclk_groups[] = { "gpio0" }; +static const char * const qua_mi2s_ws_groups[] = { "gpio1" }; +static const char * const qua_mi2s_data_groups[] = { "gpio2", "gpio3", "gpio4" }; +static const char * const i2s1_clk_groups[] = { "gpio6" }; +static const char * const i2s1_ws_groups[] = { "gpio7" }; +static const char * const i2s1_data_groups[] = { "gpio8", "gpio9" }; +static const char * const wsa_swr_clk_groups[] = { "gpio10" }; +static const char * const wsa_swr_data_groups[] = { "gpio11" }; +static const char * const i2s2_data_groups[] = { "gpio12", "gpio12" }; + +static const struct lpi_pingroup sm8250_groups[] = { + LPI_PINGROUP(0, 0, swr_tx_clk, qua_mi2s_sclk, _, _), + LPI_PINGROUP(1, 2, swr_tx_data, qua_mi2s_ws, _, _), + LPI_PINGROUP(2, 4, swr_tx_data, qua_mi2s_data, _, _), + LPI_PINGROUP(3, 8, swr_rx_clk, qua_mi2s_data, _, _), + LPI_PINGROUP(4, 10, swr_rx_data, qua_mi2s_data, _, _), + LPI_PINGROUP(5, 12, swr_tx_data, swr_rx_data, _, _), + LPI_PINGROUP(6, LPI_NO_SLEW, dmic1_clk, i2s1_clk, _, _), + LPI_PINGROUP(7, LPI_NO_SLEW, dmic1_data, i2s1_ws, _, _), + LPI_PINGROUP(8, LPI_NO_SLEW, dmic2_clk, i2s1_data, _, _), + LPI_PINGROUP(9, LPI_NO_SLEW, dmic2_data, i2s1_data, _, _), + LPI_PINGROUP(10, 16, i2s2_clk, wsa_swr_clk, _, _), + LPI_PINGROUP(11, 18, i2s2_ws, wsa_swr_data, _, _), + LPI_PINGROUP(12, LPI_NO_SLEW, dmic3_clk, i2s2_data, _, _), + LPI_PINGROUP(13, LPI_NO_SLEW, dmic3_data, i2s2_data, _, _), +}; + +static const struct lpi_function sm8250_functions[] = { + LPI_FUNCTION(dmic1_clk), + LPI_FUNCTION(dmic1_data), + LPI_FUNCTION(dmic2_clk), + LPI_FUNCTION(dmic2_data), + LPI_FUNCTION(dmic3_clk), + LPI_FUNCTION(dmic3_data), + LPI_FUNCTION(i2s1_clk), + LPI_FUNCTION(i2s1_data), + LPI_FUNCTION(i2s1_ws), + LPI_FUNCTION(i2s2_clk), + LPI_FUNCTION(i2s2_data), + LPI_FUNCTION(i2s2_ws), + LPI_FUNCTION(qua_mi2s_data), + LPI_FUNCTION(qua_mi2s_sclk), + LPI_FUNCTION(qua_mi2s_ws), + LPI_FUNCTION(swr_rx_clk), + LPI_FUNCTION(swr_rx_data), + LPI_FUNCTION(swr_tx_clk), + LPI_FUNCTION(swr_tx_data), + LPI_FUNCTION(wsa_swr_clk), + LPI_FUNCTION(wsa_swr_data), +}; + +static const struct lpi_pinctrl_variant_data sm8250_lpi_data = { + .pins = sm8250_lpi_pins, + .npins = ARRAY_SIZE(sm8250_lpi_pins), + .groups = sm8250_groups, + .ngroups = ARRAY_SIZE(sm8250_groups), + .functions = sm8250_functions, + .nfunctions = ARRAY_SIZE(sm8250_functions), +}; + +static const struct of_device_id lpi_pinctrl_of_match[] = { + { + .compatible = "qcom,sm8250-lpass-lpi-pinctrl", + .data = &sm8250_lpi_data, + }, + { } +}; +MODULE_DEVICE_TABLE(of, lpi_pinctrl_of_match); + +static struct platform_driver lpi_pinctrl_driver = { + .driver = { + .name = "qcom-sm8250-lpass-lpi-pinctrl", + .of_match_table = lpi_pinctrl_of_match, + }, + .probe = lpi_pinctrl_probe, + .remove = lpi_pinctrl_remove, +}; + +module_platform_driver(lpi_pinctrl_driver); +MODULE_DESCRIPTION("QTI SM8250 LPI GPIO pin control driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/pinctrl/qcom/pinctrl-sm8250.c b/drivers/pinctrl/qcom/pinctrl-sm8250.c new file mode 100644 index 0000000000..e9961a49ff --- /dev/null +++ b/drivers/pinctrl/qcom/pinctrl-sm8250.c @@ -0,0 +1,1371 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. + */ + +#include <linux/module.h> +#include <linux/of.h> +#include <linux/platform_device.h> + +#include "pinctrl-msm.h" + +static const char * const sm8250_tiles[] = { + "west", + "south", + "north", +}; + +enum { + WEST, + SOUTH, + NORTH, +}; + +#define REG_SIZE 0x1000 +#define PINGROUP(id, _tile, f1, f2, f3, f4, f5, f6, f7, f8, f9) \ + { \ + .grp = PINCTRL_PINGROUP("gpio" #id, \ + gpio##id##_pins, \ + ARRAY_SIZE(gpio##id##_pins)), \ + .funcs = (int[]){ \ + msm_mux_gpio, /* gpio mode */ \ + msm_mux_##f1, \ + msm_mux_##f2, \ + msm_mux_##f3, \ + msm_mux_##f4, \ + msm_mux_##f5, \ + msm_mux_##f6, \ + msm_mux_##f7, \ + msm_mux_##f8, \ + msm_mux_##f9 \ + }, \ + .nfuncs = 10, \ + .ctl_reg = REG_SIZE * id, \ + .io_reg = REG_SIZE * id + 0x4, \ + .intr_cfg_reg = REG_SIZE * id + 0x8, \ + .intr_status_reg = REG_SIZE * id + 0xc, \ + .intr_target_reg = REG_SIZE * id + 0x8, \ + .tile = _tile, \ + .mux_bit = 2, \ + .pull_bit = 0, \ + .drv_bit = 6, \ + .oe_bit = 9, \ + .in_bit = 0, \ + .out_bit = 1, \ + .intr_enable_bit = 0, \ + .intr_status_bit = 0, \ + .intr_target_bit = 5, \ + .intr_target_kpss_val = 3, \ + .intr_raw_status_bit = 4, \ + .intr_polarity_bit = 1, \ + .intr_detection_bit = 2, \ + .intr_detection_width = 2, \ + } + +#define SDC_PINGROUP(pg_name, ctl, pull, drv) \ + { \ + .grp = PINCTRL_PINGROUP(#pg_name, \ + pg_name##_pins, \ + ARRAY_SIZE(pg_name##_pins)), \ + .ctl_reg = ctl, \ + .io_reg = 0, \ + .intr_cfg_reg = 0, \ + .intr_status_reg = 0, \ + .intr_target_reg = 0, \ + .tile = NORTH, \ + .mux_bit = -1, \ + .pull_bit = pull, \ + .drv_bit = drv, \ + .oe_bit = -1, \ + .in_bit = -1, \ + .out_bit = -1, \ + .intr_enable_bit = -1, \ + .intr_status_bit = -1, \ + .intr_target_bit = -1, \ + .intr_raw_status_bit = -1, \ + .intr_polarity_bit = -1, \ + .intr_detection_bit = -1, \ + .intr_detection_width = -1, \ + } + +#define UFS_RESET(pg_name, offset) \ + { \ + .grp = PINCTRL_PINGROUP(#pg_name, \ + pg_name##_pins, \ + ARRAY_SIZE(pg_name##_pins)), \ + .ctl_reg = offset, \ + .io_reg = offset + 0x4, \ + .intr_cfg_reg = 0, \ + .intr_status_reg = 0, \ + .intr_target_reg = 0, \ + .tile = SOUTH, \ + .mux_bit = -1, \ + .pull_bit = 3, \ + .drv_bit = 0, \ + .oe_bit = -1, \ + .in_bit = -1, \ + .out_bit = 0, \ + .intr_enable_bit = -1, \ + .intr_status_bit = -1, \ + .intr_target_bit = -1, \ + .intr_raw_status_bit = -1, \ + .intr_polarity_bit = -1, \ + .intr_detection_bit = -1, \ + .intr_detection_width = -1, \ + } + +static const struct pinctrl_pin_desc sm8250_pins[] = { + PINCTRL_PIN(0, "GPIO_0"), + PINCTRL_PIN(1, "GPIO_1"), + PINCTRL_PIN(2, "GPIO_2"), + PINCTRL_PIN(3, "GPIO_3"), + PINCTRL_PIN(4, "GPIO_4"), + PINCTRL_PIN(5, "GPIO_5"), + PINCTRL_PIN(6, "GPIO_6"), + PINCTRL_PIN(7, "GPIO_7"), + PINCTRL_PIN(8, "GPIO_8"), + PINCTRL_PIN(9, "GPIO_9"), + PINCTRL_PIN(10, "GPIO_10"), + PINCTRL_PIN(11, "GPIO_11"), + PINCTRL_PIN(12, "GPIO_12"), + PINCTRL_PIN(13, "GPIO_13"), + PINCTRL_PIN(14, "GPIO_14"), + PINCTRL_PIN(15, "GPIO_15"), + PINCTRL_PIN(16, "GPIO_16"), + PINCTRL_PIN(17, "GPIO_17"), + PINCTRL_PIN(18, "GPIO_18"), + PINCTRL_PIN(19, "GPIO_19"), + PINCTRL_PIN(20, "GPIO_20"), + PINCTRL_PIN(21, "GPIO_21"), + PINCTRL_PIN(22, "GPIO_22"), + PINCTRL_PIN(23, "GPIO_23"), + PINCTRL_PIN(24, "GPIO_24"), + PINCTRL_PIN(25, "GPIO_25"), + PINCTRL_PIN(26, "GPIO_26"), + PINCTRL_PIN(27, "GPIO_27"), + PINCTRL_PIN(28, "GPIO_28"), + PINCTRL_PIN(29, "GPIO_29"), + PINCTRL_PIN(30, "GPIO_30"), + PINCTRL_PIN(31, "GPIO_31"), + PINCTRL_PIN(32, "GPIO_32"), + PINCTRL_PIN(33, "GPIO_33"), + PINCTRL_PIN(34, "GPIO_34"), + PINCTRL_PIN(35, "GPIO_35"), + PINCTRL_PIN(36, "GPIO_36"), + PINCTRL_PIN(37, "GPIO_37"), + PINCTRL_PIN(38, "GPIO_38"), + PINCTRL_PIN(39, "GPIO_39"), + PINCTRL_PIN(40, "GPIO_40"), + PINCTRL_PIN(41, "GPIO_41"), + PINCTRL_PIN(42, "GPIO_42"), + PINCTRL_PIN(43, "GPIO_43"), + PINCTRL_PIN(44, "GPIO_44"), + PINCTRL_PIN(45, "GPIO_45"), + PINCTRL_PIN(46, "GPIO_46"), + PINCTRL_PIN(47, "GPIO_47"), + PINCTRL_PIN(48, "GPIO_48"), + PINCTRL_PIN(49, "GPIO_49"), + PINCTRL_PIN(50, "GPIO_50"), + PINCTRL_PIN(51, "GPIO_51"), + PINCTRL_PIN(52, "GPIO_52"), + PINCTRL_PIN(53, "GPIO_53"), + PINCTRL_PIN(54, "GPIO_54"), + PINCTRL_PIN(55, "GPIO_55"), + PINCTRL_PIN(56, "GPIO_56"), + PINCTRL_PIN(57, "GPIO_57"), + PINCTRL_PIN(58, "GPIO_58"), + PINCTRL_PIN(59, "GPIO_59"), + PINCTRL_PIN(60, "GPIO_60"), + PINCTRL_PIN(61, "GPIO_61"), + PINCTRL_PIN(62, "GPIO_62"), + PINCTRL_PIN(63, "GPIO_63"), + PINCTRL_PIN(64, "GPIO_64"), + PINCTRL_PIN(65, "GPIO_65"), + PINCTRL_PIN(66, "GPIO_66"), + PINCTRL_PIN(67, "GPIO_67"), + PINCTRL_PIN(68, "GPIO_68"), + PINCTRL_PIN(69, "GPIO_69"), + PINCTRL_PIN(70, "GPIO_70"), + PINCTRL_PIN(71, "GPIO_71"), + PINCTRL_PIN(72, "GPIO_72"), + PINCTRL_PIN(73, "GPIO_73"), + PINCTRL_PIN(74, "GPIO_74"), + PINCTRL_PIN(75, "GPIO_75"), + PINCTRL_PIN(76, "GPIO_76"), + PINCTRL_PIN(77, "GPIO_77"), + PINCTRL_PIN(78, "GPIO_78"), + PINCTRL_PIN(79, "GPIO_79"), + PINCTRL_PIN(80, "GPIO_80"), + PINCTRL_PIN(81, "GPIO_81"), + PINCTRL_PIN(82, "GPIO_82"), + PINCTRL_PIN(83, "GPIO_83"), + PINCTRL_PIN(84, "GPIO_84"), + PINCTRL_PIN(85, "GPIO_85"), + PINCTRL_PIN(86, "GPIO_86"), + PINCTRL_PIN(87, "GPIO_87"), + PINCTRL_PIN(88, "GPIO_88"), + PINCTRL_PIN(89, "GPIO_89"), + PINCTRL_PIN(90, "GPIO_90"), + PINCTRL_PIN(91, "GPIO_91"), + PINCTRL_PIN(92, "GPIO_92"), + PINCTRL_PIN(93, "GPIO_93"), + PINCTRL_PIN(94, "GPIO_94"), + PINCTRL_PIN(95, "GPIO_95"), + PINCTRL_PIN(96, "GPIO_96"), + PINCTRL_PIN(97, "GPIO_97"), + PINCTRL_PIN(98, "GPIO_98"), + PINCTRL_PIN(99, "GPIO_99"), + PINCTRL_PIN(100, "GPIO_100"), + PINCTRL_PIN(101, "GPIO_101"), + PINCTRL_PIN(102, "GPIO_102"), + PINCTRL_PIN(103, "GPIO_103"), + PINCTRL_PIN(104, "GPIO_104"), + PINCTRL_PIN(105, "GPIO_105"), + PINCTRL_PIN(106, "GPIO_106"), + PINCTRL_PIN(107, "GPIO_107"), + PINCTRL_PIN(108, "GPIO_108"), + PINCTRL_PIN(109, "GPIO_109"), + PINCTRL_PIN(110, "GPIO_110"), + PINCTRL_PIN(111, "GPIO_111"), + PINCTRL_PIN(112, "GPIO_112"), + PINCTRL_PIN(113, "GPIO_113"), + PINCTRL_PIN(114, "GPIO_114"), + PINCTRL_PIN(115, "GPIO_115"), + PINCTRL_PIN(116, "GPIO_116"), + PINCTRL_PIN(117, "GPIO_117"), + PINCTRL_PIN(118, "GPIO_118"), + PINCTRL_PIN(119, "GPIO_119"), + PINCTRL_PIN(120, "GPIO_120"), + PINCTRL_PIN(121, "GPIO_121"), + PINCTRL_PIN(122, "GPIO_122"), + PINCTRL_PIN(123, "GPIO_123"), + PINCTRL_PIN(124, "GPIO_124"), + PINCTRL_PIN(125, "GPIO_125"), + PINCTRL_PIN(126, "GPIO_126"), + PINCTRL_PIN(127, "GPIO_127"), + PINCTRL_PIN(128, "GPIO_128"), + PINCTRL_PIN(129, "GPIO_129"), + PINCTRL_PIN(130, "GPIO_130"), + PINCTRL_PIN(131, "GPIO_131"), + PINCTRL_PIN(132, "GPIO_132"), + PINCTRL_PIN(133, "GPIO_133"), + PINCTRL_PIN(134, "GPIO_134"), + PINCTRL_PIN(135, "GPIO_135"), + PINCTRL_PIN(136, "GPIO_136"), + PINCTRL_PIN(137, "GPIO_137"), + PINCTRL_PIN(138, "GPIO_138"), + PINCTRL_PIN(139, "GPIO_139"), + PINCTRL_PIN(140, "GPIO_140"), + PINCTRL_PIN(141, "GPIO_141"), + PINCTRL_PIN(142, "GPIO_142"), + PINCTRL_PIN(143, "GPIO_143"), + PINCTRL_PIN(144, "GPIO_144"), + PINCTRL_PIN(145, "GPIO_145"), + PINCTRL_PIN(146, "GPIO_146"), + PINCTRL_PIN(147, "GPIO_147"), + PINCTRL_PIN(148, "GPIO_148"), + PINCTRL_PIN(149, "GPIO_149"), + PINCTRL_PIN(150, "GPIO_150"), + PINCTRL_PIN(151, "GPIO_151"), + PINCTRL_PIN(152, "GPIO_152"), + PINCTRL_PIN(153, "GPIO_153"), + PINCTRL_PIN(154, "GPIO_154"), + PINCTRL_PIN(155, "GPIO_155"), + PINCTRL_PIN(156, "GPIO_156"), + PINCTRL_PIN(157, "GPIO_157"), + PINCTRL_PIN(158, "GPIO_158"), + PINCTRL_PIN(159, "GPIO_159"), + PINCTRL_PIN(160, "GPIO_160"), + PINCTRL_PIN(161, "GPIO_161"), + PINCTRL_PIN(162, "GPIO_162"), + PINCTRL_PIN(163, "GPIO_163"), + PINCTRL_PIN(164, "GPIO_164"), + PINCTRL_PIN(165, "GPIO_165"), + PINCTRL_PIN(166, "GPIO_166"), + PINCTRL_PIN(167, "GPIO_167"), + PINCTRL_PIN(168, "GPIO_168"), + PINCTRL_PIN(169, "GPIO_169"), + PINCTRL_PIN(170, "GPIO_170"), + PINCTRL_PIN(171, "GPIO_171"), + PINCTRL_PIN(172, "GPIO_172"), + PINCTRL_PIN(173, "GPIO_173"), + PINCTRL_PIN(174, "GPIO_174"), + PINCTRL_PIN(175, "GPIO_175"), + PINCTRL_PIN(176, "GPIO_176"), + PINCTRL_PIN(177, "GPIO_177"), + PINCTRL_PIN(178, "GPIO_178"), + PINCTRL_PIN(179, "GPIO_179"), + PINCTRL_PIN(180, "SDC2_CLK"), + PINCTRL_PIN(181, "SDC2_CMD"), + PINCTRL_PIN(182, "SDC2_DATA"), + PINCTRL_PIN(183, "UFS_RESET"), +}; + +#define DECLARE_MSM_GPIO_PINS(pin) \ + static const unsigned int gpio##pin##_pins[] = { pin } +DECLARE_MSM_GPIO_PINS(0); +DECLARE_MSM_GPIO_PINS(1); +DECLARE_MSM_GPIO_PINS(2); +DECLARE_MSM_GPIO_PINS(3); +DECLARE_MSM_GPIO_PINS(4); +DECLARE_MSM_GPIO_PINS(5); +DECLARE_MSM_GPIO_PINS(6); +DECLARE_MSM_GPIO_PINS(7); +DECLARE_MSM_GPIO_PINS(8); +DECLARE_MSM_GPIO_PINS(9); +DECLARE_MSM_GPIO_PINS(10); +DECLARE_MSM_GPIO_PINS(11); +DECLARE_MSM_GPIO_PINS(12); +DECLARE_MSM_GPIO_PINS(13); +DECLARE_MSM_GPIO_PINS(14); +DECLARE_MSM_GPIO_PINS(15); +DECLARE_MSM_GPIO_PINS(16); +DECLARE_MSM_GPIO_PINS(17); +DECLARE_MSM_GPIO_PINS(18); +DECLARE_MSM_GPIO_PINS(19); +DECLARE_MSM_GPIO_PINS(20); +DECLARE_MSM_GPIO_PINS(21); +DECLARE_MSM_GPIO_PINS(22); +DECLARE_MSM_GPIO_PINS(23); +DECLARE_MSM_GPIO_PINS(24); +DECLARE_MSM_GPIO_PINS(25); +DECLARE_MSM_GPIO_PINS(26); +DECLARE_MSM_GPIO_PINS(27); +DECLARE_MSM_GPIO_PINS(28); +DECLARE_MSM_GPIO_PINS(29); +DECLARE_MSM_GPIO_PINS(30); +DECLARE_MSM_GPIO_PINS(31); +DECLARE_MSM_GPIO_PINS(32); +DECLARE_MSM_GPIO_PINS(33); +DECLARE_MSM_GPIO_PINS(34); +DECLARE_MSM_GPIO_PINS(35); +DECLARE_MSM_GPIO_PINS(36); +DECLARE_MSM_GPIO_PINS(37); +DECLARE_MSM_GPIO_PINS(38); +DECLARE_MSM_GPIO_PINS(39); +DECLARE_MSM_GPIO_PINS(40); +DECLARE_MSM_GPIO_PINS(41); +DECLARE_MSM_GPIO_PINS(42); +DECLARE_MSM_GPIO_PINS(43); +DECLARE_MSM_GPIO_PINS(44); +DECLARE_MSM_GPIO_PINS(45); +DECLARE_MSM_GPIO_PINS(46); +DECLARE_MSM_GPIO_PINS(47); +DECLARE_MSM_GPIO_PINS(48); +DECLARE_MSM_GPIO_PINS(49); +DECLARE_MSM_GPIO_PINS(50); +DECLARE_MSM_GPIO_PINS(51); +DECLARE_MSM_GPIO_PINS(52); +DECLARE_MSM_GPIO_PINS(53); +DECLARE_MSM_GPIO_PINS(54); +DECLARE_MSM_GPIO_PINS(55); +DECLARE_MSM_GPIO_PINS(56); +DECLARE_MSM_GPIO_PINS(57); +DECLARE_MSM_GPIO_PINS(58); +DECLARE_MSM_GPIO_PINS(59); +DECLARE_MSM_GPIO_PINS(60); +DECLARE_MSM_GPIO_PINS(61); +DECLARE_MSM_GPIO_PINS(62); +DECLARE_MSM_GPIO_PINS(63); +DECLARE_MSM_GPIO_PINS(64); +DECLARE_MSM_GPIO_PINS(65); +DECLARE_MSM_GPIO_PINS(66); +DECLARE_MSM_GPIO_PINS(67); +DECLARE_MSM_GPIO_PINS(68); +DECLARE_MSM_GPIO_PINS(69); +DECLARE_MSM_GPIO_PINS(70); +DECLARE_MSM_GPIO_PINS(71); +DECLARE_MSM_GPIO_PINS(72); +DECLARE_MSM_GPIO_PINS(73); +DECLARE_MSM_GPIO_PINS(74); +DECLARE_MSM_GPIO_PINS(75); +DECLARE_MSM_GPIO_PINS(76); +DECLARE_MSM_GPIO_PINS(77); +DECLARE_MSM_GPIO_PINS(78); +DECLARE_MSM_GPIO_PINS(79); +DECLARE_MSM_GPIO_PINS(80); +DECLARE_MSM_GPIO_PINS(81); +DECLARE_MSM_GPIO_PINS(82); +DECLARE_MSM_GPIO_PINS(83); +DECLARE_MSM_GPIO_PINS(84); +DECLARE_MSM_GPIO_PINS(85); +DECLARE_MSM_GPIO_PINS(86); +DECLARE_MSM_GPIO_PINS(87); +DECLARE_MSM_GPIO_PINS(88); +DECLARE_MSM_GPIO_PINS(89); +DECLARE_MSM_GPIO_PINS(90); +DECLARE_MSM_GPIO_PINS(91); +DECLARE_MSM_GPIO_PINS(92); +DECLARE_MSM_GPIO_PINS(93); +DECLARE_MSM_GPIO_PINS(94); +DECLARE_MSM_GPIO_PINS(95); +DECLARE_MSM_GPIO_PINS(96); +DECLARE_MSM_GPIO_PINS(97); +DECLARE_MSM_GPIO_PINS(98); +DECLARE_MSM_GPIO_PINS(99); +DECLARE_MSM_GPIO_PINS(100); +DECLARE_MSM_GPIO_PINS(101); +DECLARE_MSM_GPIO_PINS(102); +DECLARE_MSM_GPIO_PINS(103); +DECLARE_MSM_GPIO_PINS(104); +DECLARE_MSM_GPIO_PINS(105); +DECLARE_MSM_GPIO_PINS(106); +DECLARE_MSM_GPIO_PINS(107); +DECLARE_MSM_GPIO_PINS(108); +DECLARE_MSM_GPIO_PINS(109); +DECLARE_MSM_GPIO_PINS(110); +DECLARE_MSM_GPIO_PINS(111); +DECLARE_MSM_GPIO_PINS(112); +DECLARE_MSM_GPIO_PINS(113); +DECLARE_MSM_GPIO_PINS(114); +DECLARE_MSM_GPIO_PINS(115); +DECLARE_MSM_GPIO_PINS(116); +DECLARE_MSM_GPIO_PINS(117); +DECLARE_MSM_GPIO_PINS(118); +DECLARE_MSM_GPIO_PINS(119); +DECLARE_MSM_GPIO_PINS(120); +DECLARE_MSM_GPIO_PINS(121); +DECLARE_MSM_GPIO_PINS(122); +DECLARE_MSM_GPIO_PINS(123); +DECLARE_MSM_GPIO_PINS(124); +DECLARE_MSM_GPIO_PINS(125); +DECLARE_MSM_GPIO_PINS(126); +DECLARE_MSM_GPIO_PINS(127); +DECLARE_MSM_GPIO_PINS(128); +DECLARE_MSM_GPIO_PINS(129); +DECLARE_MSM_GPIO_PINS(130); +DECLARE_MSM_GPIO_PINS(131); +DECLARE_MSM_GPIO_PINS(132); +DECLARE_MSM_GPIO_PINS(133); +DECLARE_MSM_GPIO_PINS(134); +DECLARE_MSM_GPIO_PINS(135); +DECLARE_MSM_GPIO_PINS(136); +DECLARE_MSM_GPIO_PINS(137); +DECLARE_MSM_GPIO_PINS(138); +DECLARE_MSM_GPIO_PINS(139); +DECLARE_MSM_GPIO_PINS(140); +DECLARE_MSM_GPIO_PINS(141); +DECLARE_MSM_GPIO_PINS(142); +DECLARE_MSM_GPIO_PINS(143); +DECLARE_MSM_GPIO_PINS(144); +DECLARE_MSM_GPIO_PINS(145); +DECLARE_MSM_GPIO_PINS(146); +DECLARE_MSM_GPIO_PINS(147); +DECLARE_MSM_GPIO_PINS(148); +DECLARE_MSM_GPIO_PINS(149); +DECLARE_MSM_GPIO_PINS(150); +DECLARE_MSM_GPIO_PINS(151); +DECLARE_MSM_GPIO_PINS(152); +DECLARE_MSM_GPIO_PINS(153); +DECLARE_MSM_GPIO_PINS(154); +DECLARE_MSM_GPIO_PINS(155); +DECLARE_MSM_GPIO_PINS(156); +DECLARE_MSM_GPIO_PINS(157); +DECLARE_MSM_GPIO_PINS(158); +DECLARE_MSM_GPIO_PINS(159); +DECLARE_MSM_GPIO_PINS(160); +DECLARE_MSM_GPIO_PINS(161); +DECLARE_MSM_GPIO_PINS(162); +DECLARE_MSM_GPIO_PINS(163); +DECLARE_MSM_GPIO_PINS(164); +DECLARE_MSM_GPIO_PINS(165); +DECLARE_MSM_GPIO_PINS(166); +DECLARE_MSM_GPIO_PINS(167); +DECLARE_MSM_GPIO_PINS(168); +DECLARE_MSM_GPIO_PINS(169); +DECLARE_MSM_GPIO_PINS(170); +DECLARE_MSM_GPIO_PINS(171); +DECLARE_MSM_GPIO_PINS(172); +DECLARE_MSM_GPIO_PINS(173); +DECLARE_MSM_GPIO_PINS(174); +DECLARE_MSM_GPIO_PINS(175); +DECLARE_MSM_GPIO_PINS(176); +DECLARE_MSM_GPIO_PINS(177); +DECLARE_MSM_GPIO_PINS(178); +DECLARE_MSM_GPIO_PINS(179); + +static const unsigned int ufs_reset_pins[] = { 180 }; +static const unsigned int sdc2_clk_pins[] = { 181 }; +static const unsigned int sdc2_cmd_pins[] = { 182 }; +static const unsigned int sdc2_data_pins[] = { 183 }; + +enum sm8250_functions { + msm_mux_aoss_cti, + msm_mux_atest, + msm_mux_audio_ref, + msm_mux_cam_mclk, + msm_mux_cci_async, + msm_mux_cci_i2c, + msm_mux_cci_timer0, + msm_mux_cci_timer1, + msm_mux_cci_timer2, + msm_mux_cci_timer3, + msm_mux_cci_timer4, + msm_mux_cri_trng, + msm_mux_cri_trng0, + msm_mux_cri_trng1, + msm_mux_dbg_out, + msm_mux_ddr_bist, + msm_mux_ddr_pxi0, + msm_mux_ddr_pxi1, + msm_mux_ddr_pxi2, + msm_mux_ddr_pxi3, + msm_mux_dp_hot, + msm_mux_dp_lcd, + msm_mux_gcc_gp1, + msm_mux_gcc_gp2, + msm_mux_gcc_gp3, + msm_mux_gpio, + msm_mux_ibi_i3c, + msm_mux_jitter_bist, + msm_mux_lpass_slimbus, + msm_mux_mdp_vsync, + msm_mux_mdp_vsync0, + msm_mux_mdp_vsync1, + msm_mux_mdp_vsync2, + msm_mux_mdp_vsync3, + msm_mux_mi2s0_data0, + msm_mux_mi2s0_data1, + msm_mux_mi2s0_sck, + msm_mux_mi2s0_ws, + msm_mux_mi2s1_data0, + msm_mux_mi2s1_data1, + msm_mux_mi2s1_sck, + msm_mux_mi2s1_ws, + msm_mux_mi2s2_data0, + msm_mux_mi2s2_data1, + msm_mux_mi2s2_sck, + msm_mux_mi2s2_ws, + msm_mux_pci_e0, + msm_mux_pci_e1, + msm_mux_pci_e2, + msm_mux_phase_flag, + msm_mux_pll_bist, + msm_mux_pll_bypassnl, + msm_mux_pll_clk, + msm_mux_pll_reset, + msm_mux_pri_mi2s, + msm_mux_prng_rosc, + msm_mux_qdss_cti, + msm_mux_qdss_gpio, + msm_mux_qspi0, + msm_mux_qspi1, + msm_mux_qspi2, + msm_mux_qspi3, + msm_mux_qspi_clk, + msm_mux_qspi_cs, + msm_mux_qup0, + msm_mux_qup1, + msm_mux_qup10, + msm_mux_qup11, + msm_mux_qup12, + msm_mux_qup13, + msm_mux_qup14, + msm_mux_qup15, + msm_mux_qup16, + msm_mux_qup17, + msm_mux_qup18, + msm_mux_qup19, + msm_mux_qup2, + msm_mux_qup3, + msm_mux_qup4, + msm_mux_qup5, + msm_mux_qup6, + msm_mux_qup7, + msm_mux_qup8, + msm_mux_qup9, + msm_mux_qup_l4, + msm_mux_qup_l5, + msm_mux_qup_l6, + msm_mux_sd_write, + msm_mux_sdc40, + msm_mux_sdc41, + msm_mux_sdc42, + msm_mux_sdc43, + msm_mux_sdc4_clk, + msm_mux_sdc4_cmd, + msm_mux_sec_mi2s, + msm_mux_sp_cmu, + msm_mux_tgu_ch0, + msm_mux_tgu_ch1, + msm_mux_tgu_ch2, + msm_mux_tgu_ch3, + msm_mux_tsense_pwm1, + msm_mux_tsense_pwm2, + msm_mux_tsif0_clk, + msm_mux_tsif0_data, + msm_mux_tsif0_en, + msm_mux_tsif0_error, + msm_mux_tsif0_sync, + msm_mux_tsif1_clk, + msm_mux_tsif1_data, + msm_mux_tsif1_en, + msm_mux_tsif1_error, + msm_mux_tsif1_sync, + msm_mux_usb2phy_ac, + msm_mux_usb_phy, + msm_mux_vsense_trigger, + msm_mux__, +}; + +static const char * const tsif1_data_groups[] = { + "gpio75", +}; +static const char * const sdc41_groups[] = { + "gpio75", +}; +static const char * const tsif1_sync_groups[] = { + "gpio76", +}; +static const char * const sdc40_groups[] = { + "gpio76", +}; +static const char * const aoss_cti_groups[] = { + "gpio77", +}; +static const char * const phase_flag_groups[] = { + "gpio45", "gpio46", "gpio47", "gpio48", "gpio49", "gpio50", "gpio51", + "gpio69", "gpio70", "gpio71", "gpio72", "gpio73", "gpio74", "gpio77", + "gpio78", "gpio79", "gpio80", "gpio81", "gpio82", "gpio83", "gpio84", + "gpio103", "gpio104", "gpio115", "gpio116", "gpio117", "gpio118", + "gpio119", "gpio120", "gpio122", "gpio124", "gpio125", +}; +static const char * const sd_write_groups[] = { + "gpio78", +}; +static const char * const pci_e0_groups[] = { + "gpio79", "gpio80", +}; +static const char * const pci_e1_groups[] = { + "gpio82", "gpio83", +}; +static const char * const pci_e2_groups[] = { + "gpio85", "gpio86", +}; +static const char * const tgu_ch0_groups[] = { + "gpio85", +}; +static const char * const atest_groups[] = { + "gpio24", "gpio25", "gpio26", "gpio27", "gpio32", "gpio33", "gpio34", + "gpio35", "gpio36", "gpio37", "gpio85", "gpio86", "gpio87", "gpio88", + "gpio89", +}; +static const char * const tgu_ch3_groups[] = { + "gpio86", +}; +static const char * const tsif1_error_groups[] = { + "gpio90", +}; +static const char * const tgu_ch1_groups[] = { + "gpio90", +}; +static const char * const tsif0_error_groups[] = { + "gpio91", +}; +static const char * const tgu_ch2_groups[] = { + "gpio91", +}; +static const char * const cam_mclk_groups[] = { + "gpio94", "gpio95", "gpio96", "gpio97", "gpio98", "gpio99", "gpio100", +}; +static const char * const ddr_bist_groups[] = { + "gpio94", "gpio95", "gpio143", "gpio144", +}; +static const char * const pll_bypassnl_groups[] = { + "gpio96", +}; +static const char * const pll_reset_groups[] = { + "gpio97", +}; +static const char * const cci_i2c_groups[] = { + "gpio101", "gpio102", "gpio103", "gpio104", "gpio105", "gpio106", + "gpio107", "gpio108", +}; +static const char * const qdss_gpio_groups[] = { + "gpio94", "gpio95", "gpio96", "gpio97", "gpio98", "gpio99", "gpio100", + "gpio101", "gpio102", "gpio103", "gpio104", "gpio105", "gpio106", + "gpio107", "gpio108", "gpio109", "gpio110", "gpio111", "gpio160", + "gpio161", "gpio162", "gpio163", "gpio164", "gpio165", "gpio166", + "gpio167", "gpio168", "gpio169", "gpio170", "gpio171", "gpio172", + "gpio173", "gpio174", "gpio175", "gpio176", "gpio177", +}; +static const char * const gcc_gp1_groups[] = { + "gpio106", "gpio136", +}; +static const char * const gcc_gp2_groups[] = { + "gpio107", "gpio137", +}; +static const char * const gcc_gp3_groups[] = { + "gpio108", "gpio138", +}; +static const char * const cci_timer0_groups[] = { + "gpio109", +}; +static const char * const cci_timer1_groups[] = { + "gpio110", +}; +static const char * const cci_timer2_groups[] = { + "gpio111", +}; +static const char * const cci_timer3_groups[] = { + "gpio112", +}; +static const char * const cci_async_groups[] = { + "gpio112", "gpio113", "gpio114", +}; +static const char * const cci_timer4_groups[] = { + "gpio113", +}; +static const char * const qup2_groups[] = { + "gpio115", "gpio116", "gpio117", "gpio118", +}; +static const char * const qup3_groups[] = { + "gpio119", "gpio120", "gpio121", "gpio122", +}; +static const char * const tsense_pwm1_groups[] = { + "gpio123", +}; +static const char * const tsense_pwm2_groups[] = { + "gpio123", +}; +static const char * const qup9_groups[] = { + "gpio125", "gpio126", "gpio127", "gpio128", +}; +static const char * const qup10_groups[] = { + "gpio129", "gpio130", "gpio131", "gpio132", +}; +static const char * const mi2s2_sck_groups[] = { + "gpio133", +}; +static const char * const mi2s2_data0_groups[] = { + "gpio134", +}; +static const char * const mi2s2_ws_groups[] = { + "gpio135", +}; +static const char * const pri_mi2s_groups[] = { + "gpio136", +}; +static const char * const sec_mi2s_groups[] = { + "gpio137", +}; +static const char * const audio_ref_groups[] = { + "gpio137", +}; +static const char * const mi2s2_data1_groups[] = { + "gpio137", +}; +static const char * const mi2s0_sck_groups[] = { + "gpio138", +}; +static const char * const mi2s0_data0_groups[] = { + "gpio139", +}; +static const char * const mi2s0_data1_groups[] = { + "gpio140", +}; +static const char * const mi2s0_ws_groups[] = { + "gpio141", +}; +static const char * const lpass_slimbus_groups[] = { + "gpio142", "gpio143", "gpio144", "gpio145", +}; +static const char * const mi2s1_sck_groups[] = { + "gpio142", +}; +static const char * const mi2s1_data0_groups[] = { + "gpio143", +}; +static const char * const mi2s1_data1_groups[] = { + "gpio144", +}; +static const char * const mi2s1_ws_groups[] = { + "gpio145", +}; +static const char * const cri_trng0_groups[] = { + "gpio159", +}; +static const char * const cri_trng1_groups[] = { + "gpio160", +}; +static const char * const cri_trng_groups[] = { + "gpio161", +}; +static const char * const sp_cmu_groups[] = { + "gpio162", +}; +static const char * const prng_rosc_groups[] = { + "gpio163", +}; +static const char * const qup19_groups[] = { + "gpio0", "gpio1", "gpio2", "gpio3", +}; +static const char * const gpio_groups[] = { + "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7", + "gpio8", "gpio9", "gpio10", "gpio11", "gpio12", "gpio13", "gpio14", + "gpio15", "gpio16", "gpio17", "gpio18", "gpio19", "gpio20", "gpio21", + "gpio22", "gpio23", "gpio24", "gpio25", "gpio26", "gpio27", "gpio28", + "gpio29", "gpio30", "gpio31", "gpio32", "gpio33", "gpio34", "gpio35", + "gpio36", "gpio37", "gpio38", "gpio39", "gpio40", "gpio41", "gpio42", + "gpio43", "gpio44", "gpio45", "gpio46", "gpio47", "gpio48", "gpio49", + "gpio50", "gpio51", "gpio52", "gpio53", "gpio54", "gpio55", "gpio56", + "gpio57", "gpio58", "gpio59", "gpio60", "gpio61", "gpio62", "gpio63", + "gpio64", "gpio65", "gpio66", "gpio67", "gpio68", "gpio69", "gpio70", + "gpio71", "gpio72", "gpio73", "gpio74", "gpio75", "gpio76", "gpio77", + "gpio78", "gpio79", "gpio80", "gpio81", "gpio82", "gpio83", "gpio84", + "gpio85", "gpio86", "gpio87", "gpio88", "gpio89", "gpio90", "gpio91", + "gpio92", "gpio93", "gpio94", "gpio95", "gpio96", "gpio97", "gpio98", + "gpio99", "gpio100", "gpio101", "gpio102", "gpio103", "gpio104", + "gpio105", "gpio106", "gpio107", "gpio108", "gpio109", "gpio110", + "gpio111", "gpio112", "gpio113", "gpio114", "gpio115", "gpio116", + "gpio117", "gpio118", "gpio119", "gpio120", "gpio121", "gpio122", + "gpio123", "gpio124", "gpio125", "gpio126", "gpio127", "gpio128", + "gpio129", "gpio130", "gpio131", "gpio132", "gpio133", "gpio134", + "gpio135", "gpio136", "gpio137", "gpio138", "gpio139", "gpio140", + "gpio141", "gpio142", "gpio143", "gpio144", "gpio145", "gpio146", + "gpio147", "gpio148", "gpio149", "gpio150", "gpio151", "gpio152", + "gpio153", "gpio154", "gpio155", "gpio156", "gpio157", "gpio158", + "gpio159", "gpio160", "gpio161", "gpio162", "gpio163", "gpio164", + "gpio165", "gpio166", "gpio167", "gpio168", "gpio169", "gpio170", + "gpio171", "gpio172", "gpio173", "gpio174", "gpio175", "gpio176", + "gpio177", "gpio178", "gpio179", +}; +static const char * const qdss_cti_groups[] = { + "gpio0", "gpio2", "gpio2", "gpio44", "gpio45", "gpio46", "gpio92", + "gpio93", +}; +static const char * const qup1_groups[] = { + "gpio4", "gpio5", "gpio6", "gpio7", +}; +static const char * const ibi_i3c_groups[] = { + "gpio4", "gpio5", "gpio24", "gpio25", "gpio28", "gpio29", "gpio40", + "gpio41", +}; +static const char * const qup_l4_groups[] = { + "gpio6", "gpio14", "gpio46", "gpio123", +}; +static const char * const qup_l5_groups[] = { + "gpio7", "gpio15", "gpio47", "gpio124", +}; +static const char * const qup4_groups[] = { + "gpio8", "gpio9", "gpio10", "gpio11", +}; +static const char * const qup5_groups[] = { + "gpio12", "gpio13", "gpio14", "gpio15", +}; +static const char * const qup6_groups[] = { + "gpio16", "gpio17", "gpio18", "gpio19", +}; +static const char * const qup7_groups[] = { + "gpio20", "gpio21", "gpio22", "gpio23", +}; +static const char * const qup8_groups[] = { + "gpio24", "gpio25", "gpio26", "gpio27", +}; +static const char * const qup0_groups[] = { + "gpio28", "gpio29", "gpio30", "gpio31", +}; +static const char * const qup12_groups[] = { + "gpio32", "gpio33", "gpio34", "gpio35", +}; +static const char * const qup13_groups[] = { + "gpio36", "gpio37", "gpio38", "gpio39", +}; +static const char * const qup14_groups[] = { + "gpio40", "gpio41", "gpio42", "gpio43", +}; +static const char * const ddr_pxi3_groups[] = { + "gpio40", "gpio43", +}; +static const char * const ddr_pxi1_groups[] = { + "gpio41", "gpio42", +}; +static const char * const vsense_trigger_groups[] = { + "gpio42", +}; +static const char * const qup15_groups[] = { + "gpio44", "gpio45", "gpio46", "gpio47", +}; +static const char * const dbg_out_groups[] = { + "gpio44", +}; +static const char * const qup16_groups[] = { + "gpio48", "gpio49", "gpio50", "gpio51", +}; +static const char * const qup17_groups[] = { + "gpio52", "gpio53", "gpio54", "gpio55", +}; +static const char * const ddr_pxi0_groups[] = { + "gpio52", "gpio53", +}; +static const char * const jitter_bist_groups[] = { + "gpio54", +}; +static const char * const pll_bist_groups[] = { + "gpio55", +}; +static const char * const ddr_pxi2_groups[] = { + "gpio55", "gpio56", +}; +static const char * const qup18_groups[] = { + "gpio56", "gpio57", "gpio58", "gpio59", +}; +static const char * const qup11_groups[] = { + "gpio60", "gpio61", "gpio62", "gpio63", +}; +static const char * const usb2phy_ac_groups[] = { + "gpio64", "gpio90", +}; +static const char * const qup_l6_groups[] = { + "gpio64", "gpio77", "gpio92", "gpio93", +}; +static const char * const usb_phy_groups[] = { + "gpio65", +}; +static const char * const pll_clk_groups[] = { + "gpio65", +}; +static const char * const mdp_vsync_groups[] = { + "gpio66", "gpio67", "gpio68", "gpio122", "gpio124", +}; +static const char * const dp_lcd_groups[] = { + "gpio67", +}; +static const char * const dp_hot_groups[] = { + "gpio68", +}; +static const char * const qspi_cs_groups[] = { + "gpio69", "gpio75", +}; +static const char * const tsif0_clk_groups[] = { + "gpio69", +}; +static const char * const qspi0_groups[] = { + "gpio70", +}; +static const char * const tsif0_en_groups[] = { + "gpio70", +}; +static const char * const mdp_vsync0_groups[] = { + "gpio70", +}; +static const char * const mdp_vsync1_groups[] = { + "gpio70", +}; +static const char * const mdp_vsync2_groups[] = { + "gpio70", +}; +static const char * const mdp_vsync3_groups[] = { + "gpio70", +}; +static const char * const qspi1_groups[] = { + "gpio71", +}; +static const char * const tsif0_data_groups[] = { + "gpio71", +}; +static const char * const sdc4_cmd_groups[] = { + "gpio71", +}; +static const char * const qspi2_groups[] = { + "gpio72", +}; +static const char * const tsif0_sync_groups[] = { + "gpio72", +}; +static const char * const sdc43_groups[] = { + "gpio72", +}; +static const char * const qspi_clk_groups[] = { + "gpio73", +}; +static const char * const tsif1_clk_groups[] = { + "gpio73", +}; +static const char * const sdc4_clk_groups[] = { + "gpio73", +}; +static const char * const qspi3_groups[] = { + "gpio74", +}; +static const char * const tsif1_en_groups[] = { + "gpio74", +}; +static const char * const sdc42_groups[] = { + "gpio74", +}; + +static const struct pinfunction sm8250_functions[] = { + MSM_PIN_FUNCTION(aoss_cti), + MSM_PIN_FUNCTION(atest), + MSM_PIN_FUNCTION(audio_ref), + MSM_PIN_FUNCTION(cam_mclk), + MSM_PIN_FUNCTION(cci_async), + MSM_PIN_FUNCTION(cci_i2c), + MSM_PIN_FUNCTION(cci_timer0), + MSM_PIN_FUNCTION(cci_timer1), + MSM_PIN_FUNCTION(cci_timer2), + MSM_PIN_FUNCTION(cci_timer3), + MSM_PIN_FUNCTION(cci_timer4), + MSM_PIN_FUNCTION(cri_trng), + MSM_PIN_FUNCTION(cri_trng0), + MSM_PIN_FUNCTION(cri_trng1), + MSM_PIN_FUNCTION(dbg_out), + MSM_PIN_FUNCTION(ddr_bist), + MSM_PIN_FUNCTION(ddr_pxi0), + MSM_PIN_FUNCTION(ddr_pxi1), + MSM_PIN_FUNCTION(ddr_pxi2), + MSM_PIN_FUNCTION(ddr_pxi3), + MSM_PIN_FUNCTION(dp_hot), + MSM_PIN_FUNCTION(dp_lcd), + MSM_PIN_FUNCTION(gcc_gp1), + MSM_PIN_FUNCTION(gcc_gp2), + MSM_PIN_FUNCTION(gcc_gp3), + MSM_PIN_FUNCTION(gpio), + MSM_PIN_FUNCTION(ibi_i3c), + MSM_PIN_FUNCTION(jitter_bist), + MSM_PIN_FUNCTION(lpass_slimbus), + MSM_PIN_FUNCTION(mdp_vsync), + MSM_PIN_FUNCTION(mdp_vsync0), + MSM_PIN_FUNCTION(mdp_vsync1), + MSM_PIN_FUNCTION(mdp_vsync2), + MSM_PIN_FUNCTION(mdp_vsync3), + MSM_PIN_FUNCTION(mi2s0_data0), + MSM_PIN_FUNCTION(mi2s0_data1), + MSM_PIN_FUNCTION(mi2s0_sck), + MSM_PIN_FUNCTION(mi2s0_ws), + MSM_PIN_FUNCTION(mi2s1_data0), + MSM_PIN_FUNCTION(mi2s1_data1), + MSM_PIN_FUNCTION(mi2s1_sck), + MSM_PIN_FUNCTION(mi2s1_ws), + MSM_PIN_FUNCTION(mi2s2_data0), + MSM_PIN_FUNCTION(mi2s2_data1), + MSM_PIN_FUNCTION(mi2s2_sck), + MSM_PIN_FUNCTION(mi2s2_ws), + MSM_PIN_FUNCTION(pci_e0), + MSM_PIN_FUNCTION(pci_e1), + MSM_PIN_FUNCTION(pci_e2), + MSM_PIN_FUNCTION(phase_flag), + MSM_PIN_FUNCTION(pll_bist), + MSM_PIN_FUNCTION(pll_bypassnl), + MSM_PIN_FUNCTION(pll_clk), + MSM_PIN_FUNCTION(pll_reset), + MSM_PIN_FUNCTION(pri_mi2s), + MSM_PIN_FUNCTION(prng_rosc), + MSM_PIN_FUNCTION(qdss_cti), + MSM_PIN_FUNCTION(qdss_gpio), + MSM_PIN_FUNCTION(qspi0), + MSM_PIN_FUNCTION(qspi1), + MSM_PIN_FUNCTION(qspi2), + MSM_PIN_FUNCTION(qspi3), + MSM_PIN_FUNCTION(qspi_clk), + MSM_PIN_FUNCTION(qspi_cs), + MSM_PIN_FUNCTION(qup0), + MSM_PIN_FUNCTION(qup1), + MSM_PIN_FUNCTION(qup10), + MSM_PIN_FUNCTION(qup11), + MSM_PIN_FUNCTION(qup12), + MSM_PIN_FUNCTION(qup13), + MSM_PIN_FUNCTION(qup14), + MSM_PIN_FUNCTION(qup15), + MSM_PIN_FUNCTION(qup16), + MSM_PIN_FUNCTION(qup17), + MSM_PIN_FUNCTION(qup18), + MSM_PIN_FUNCTION(qup19), + MSM_PIN_FUNCTION(qup2), + MSM_PIN_FUNCTION(qup3), + MSM_PIN_FUNCTION(qup4), + MSM_PIN_FUNCTION(qup5), + MSM_PIN_FUNCTION(qup6), + MSM_PIN_FUNCTION(qup7), + MSM_PIN_FUNCTION(qup8), + MSM_PIN_FUNCTION(qup9), + MSM_PIN_FUNCTION(qup_l4), + MSM_PIN_FUNCTION(qup_l5), + MSM_PIN_FUNCTION(qup_l6), + MSM_PIN_FUNCTION(sd_write), + MSM_PIN_FUNCTION(sdc40), + MSM_PIN_FUNCTION(sdc41), + MSM_PIN_FUNCTION(sdc42), + MSM_PIN_FUNCTION(sdc43), + MSM_PIN_FUNCTION(sdc4_clk), + MSM_PIN_FUNCTION(sdc4_cmd), + MSM_PIN_FUNCTION(sec_mi2s), + MSM_PIN_FUNCTION(sp_cmu), + MSM_PIN_FUNCTION(tgu_ch0), + MSM_PIN_FUNCTION(tgu_ch1), + MSM_PIN_FUNCTION(tgu_ch2), + MSM_PIN_FUNCTION(tgu_ch3), + MSM_PIN_FUNCTION(tsense_pwm1), + MSM_PIN_FUNCTION(tsense_pwm2), + MSM_PIN_FUNCTION(tsif0_clk), + MSM_PIN_FUNCTION(tsif0_data), + MSM_PIN_FUNCTION(tsif0_en), + MSM_PIN_FUNCTION(tsif0_error), + MSM_PIN_FUNCTION(tsif0_sync), + MSM_PIN_FUNCTION(tsif1_clk), + MSM_PIN_FUNCTION(tsif1_data), + MSM_PIN_FUNCTION(tsif1_en), + MSM_PIN_FUNCTION(tsif1_error), + MSM_PIN_FUNCTION(tsif1_sync), + MSM_PIN_FUNCTION(usb2phy_ac), + MSM_PIN_FUNCTION(usb_phy), + MSM_PIN_FUNCTION(vsense_trigger), +}; + +/* Every pin is maintained as a single group, and missing or non-existing pin + * would be maintained as dummy group to synchronize pin group index with + * pin descriptor registered with pinctrl core. + * Clients would not be able to request these dummy pin groups. + */ +static const struct msm_pingroup sm8250_groups[] = { + [0] = PINGROUP(0, SOUTH, qup19, qdss_cti, _, _, _, _, _, _, _), + [1] = PINGROUP(1, SOUTH, qup19, _, _, _, _, _, _, _, _), + [2] = PINGROUP(2, SOUTH, qup19, qdss_cti, qdss_cti, _, _, _, _, _, _), + [3] = PINGROUP(3, SOUTH, qup19, _, _, _, _, _, _, _, _), + [4] = PINGROUP(4, NORTH, qup1, ibi_i3c, _, _, _, _, _, _, _), + [5] = PINGROUP(5, NORTH, qup1, ibi_i3c, _, _, _, _, _, _, _), + [6] = PINGROUP(6, NORTH, qup1, qup_l4, _, _, _, _, _, _, _), + [7] = PINGROUP(7, NORTH, qup1, qup_l5, _, _, _, _, _, _, _), + [8] = PINGROUP(8, NORTH, qup4, _, _, _, _, _, _, _, _), + [9] = PINGROUP(9, NORTH, qup4, _, _, _, _, _, _, _, _), + [10] = PINGROUP(10, NORTH, qup4, _, _, _, _, _, _, _, _), + [11] = PINGROUP(11, NORTH, qup4, _, _, _, _, _, _, _, _), + [12] = PINGROUP(12, NORTH, qup5, _, _, _, _, _, _, _, _), + [13] = PINGROUP(13, NORTH, qup5, _, _, _, _, _, _, _, _), + [14] = PINGROUP(14, NORTH, qup5, qup_l4, _, _, _, _, _, _, _), + [15] = PINGROUP(15, NORTH, qup5, qup_l5, _, _, _, _, _, _, _), + [16] = PINGROUP(16, NORTH, qup6, _, _, _, _, _, _, _, _), + [17] = PINGROUP(17, NORTH, qup6, _, _, _, _, _, _, _, _), + [18] = PINGROUP(18, NORTH, qup6, _, _, _, _, _, _, _, _), + [19] = PINGROUP(19, NORTH, qup6, _, _, _, _, _, _, _, _), + [20] = PINGROUP(20, NORTH, qup7, _, _, _, _, _, _, _, _), + [21] = PINGROUP(21, NORTH, qup7, _, _, _, _, _, _, _, _), + [22] = PINGROUP(22, NORTH, qup7, _, _, _, _, _, _, _, _), + [23] = PINGROUP(23, NORTH, qup7, _, _, _, _, _, _, _, _), + [24] = PINGROUP(24, SOUTH, qup8, ibi_i3c, atest, _, _, _, _, _, _), + [25] = PINGROUP(25, SOUTH, qup8, ibi_i3c, atest, _, _, _, _, _, _), + [26] = PINGROUP(26, SOUTH, qup8, atest, _, _, _, _, _, _, _), + [27] = PINGROUP(27, SOUTH, qup8, atest, _, _, _, _, _, _, _), + [28] = PINGROUP(28, NORTH, qup0, ibi_i3c, _, _, _, _, _, _, _), + [29] = PINGROUP(29, NORTH, qup0, ibi_i3c, _, _, _, _, _, _, _), + [30] = PINGROUP(30, NORTH, qup0, _, _, _, _, _, _, _, _), + [31] = PINGROUP(31, NORTH, qup0, _, _, _, _, _, _, _, _), + [32] = PINGROUP(32, SOUTH, qup12, _, atest, _, _, _, _, _, _), + [33] = PINGROUP(33, SOUTH, qup12, atest, _, _, _, _, _, _, _), + [34] = PINGROUP(34, SOUTH, qup12, atest, _, _, _, _, _, _, _), + [35] = PINGROUP(35, SOUTH, qup12, atest, _, _, _, _, _, _, _), + [36] = PINGROUP(36, SOUTH, qup13, atest, _, _, _, _, _, _, _), + [37] = PINGROUP(37, SOUTH, qup13, atest, _, _, _, _, _, _, _), + [38] = PINGROUP(38, SOUTH, qup13, _, _, _, _, _, _, _, _), + [39] = PINGROUP(39, SOUTH, qup13, _, _, _, _, _, _, _, _), + [40] = PINGROUP(40, SOUTH, qup14, ibi_i3c, _, ddr_pxi3, _, _, _, _, _), + [41] = PINGROUP(41, SOUTH, qup14, ibi_i3c, _, ddr_pxi1, _, _, _, _, _), + [42] = PINGROUP(42, SOUTH, qup14, vsense_trigger, ddr_pxi1, _, _, _, _, _, _), + [43] = PINGROUP(43, SOUTH, qup14, ddr_pxi3, _, _, _, _, _, _, _), + [44] = PINGROUP(44, SOUTH, qup15, qdss_cti, dbg_out, _, _, _, _, _, _), + [45] = PINGROUP(45, SOUTH, qup15, qdss_cti, phase_flag, _, _, _, _, _, _), + [46] = PINGROUP(46, SOUTH, qup15, qup_l4, qdss_cti, phase_flag, _, _, _, _, _), + [47] = PINGROUP(47, SOUTH, qup15, qup_l5, phase_flag, _, _, _, _, _, _), + [48] = PINGROUP(48, SOUTH, qup16, phase_flag, _, _, _, _, _, _, _), + [49] = PINGROUP(49, SOUTH, qup16, phase_flag, _, _, _, _, _, _, _), + [50] = PINGROUP(50, SOUTH, qup16, phase_flag, _, _, _, _, _, _, _), + [51] = PINGROUP(51, SOUTH, qup16, phase_flag, _, _, _, _, _, _, _), + [52] = PINGROUP(52, SOUTH, qup17, ddr_pxi0, _, _, _, _, _, _, _), + [53] = PINGROUP(53, SOUTH, qup17, ddr_pxi0, _, _, _, _, _, _, _), + [54] = PINGROUP(54, SOUTH, qup17, jitter_bist, _, _, _, _, _, _, _), + [55] = PINGROUP(55, SOUTH, qup17, pll_bist, ddr_pxi2, _, _, _, _, _, _), + [56] = PINGROUP(56, SOUTH, qup18, ddr_pxi2, _, _, _, _, _, _, _), + [57] = PINGROUP(57, SOUTH, qup18, _, _, _, _, _, _, _, _), + [58] = PINGROUP(58, SOUTH, qup18, _, _, _, _, _, _, _, _), + [59] = PINGROUP(59, SOUTH, qup18, _, _, _, _, _, _, _, _), + [60] = PINGROUP(60, SOUTH, qup11, _, _, _, _, _, _, _, _), + [61] = PINGROUP(61, SOUTH, qup11, _, _, _, _, _, _, _, _), + [62] = PINGROUP(62, SOUTH, qup11, _, _, _, _, _, _, _, _), + [63] = PINGROUP(63, SOUTH, qup11, _, _, _, _, _, _, _, _), + [64] = PINGROUP(64, SOUTH, usb2phy_ac, qup_l6, _, _, _, _, _, _, _), + [65] = PINGROUP(65, SOUTH, usb_phy, pll_clk, _, _, _, _, _, _, _), + [66] = PINGROUP(66, NORTH, mdp_vsync, _, _, _, _, _, _, _, _), + [67] = PINGROUP(67, NORTH, mdp_vsync, dp_lcd, _, _, _, _, _, _, _), + [68] = PINGROUP(68, NORTH, mdp_vsync, dp_hot, _, _, _, _, _, _, _), + [69] = PINGROUP(69, SOUTH, qspi_cs, tsif0_clk, phase_flag, _, _, _, _, _, _), + [70] = PINGROUP(70, SOUTH, qspi0, tsif0_en, mdp_vsync0, mdp_vsync1, mdp_vsync2, mdp_vsync3, phase_flag, _, _), + [71] = PINGROUP(71, SOUTH, qspi1, tsif0_data, sdc4_cmd, phase_flag, _, _, _, _, _), + [72] = PINGROUP(72, SOUTH, qspi2, tsif0_sync, sdc43, phase_flag, _, _, _, _, _), + [73] = PINGROUP(73, SOUTH, qspi_clk, tsif1_clk, sdc4_clk, phase_flag, _, _, _, _, _), + [74] = PINGROUP(74, SOUTH, qspi3, tsif1_en, sdc42, phase_flag, _, _, _, _, _), + [75] = PINGROUP(75, SOUTH, qspi_cs, tsif1_data, sdc41, _, _, _, _, _, _), + [76] = PINGROUP(76, SOUTH, tsif1_sync, sdc40, _, _, _, _, _, _, _), + [77] = PINGROUP(77, NORTH, qup_l6, aoss_cti, phase_flag, _, _, _, _, _, _), + [78] = PINGROUP(78, NORTH, sd_write, phase_flag, _, _, _, _, _, _, _), + [79] = PINGROUP(79, NORTH, pci_e0, phase_flag, _, _, _, _, _, _, _), + [80] = PINGROUP(80, NORTH, pci_e0, phase_flag, _, _, _, _, _, _, _), + [81] = PINGROUP(81, NORTH, phase_flag, _, _, _, _, _, _, _, _), + [82] = PINGROUP(82, NORTH, pci_e1, phase_flag, _, _, _, _, _, _, _), + [83] = PINGROUP(83, NORTH, pci_e1, phase_flag, _, _, _, _, _, _, _), + [84] = PINGROUP(84, NORTH, phase_flag, _, _, _, _, _, _, _, _), + [85] = PINGROUP(85, SOUTH, pci_e2, tgu_ch0, atest, _, _, _, _, _, _), + [86] = PINGROUP(86, SOUTH, pci_e2, tgu_ch3, atest, _, _, _, _, _, _), + [87] = PINGROUP(87, SOUTH, atest, _, _, _, _, _, _, _, _), + [88] = PINGROUP(88, SOUTH, _, atest, _, _, _, _, _, _, _), + [89] = PINGROUP(89, SOUTH, _, atest, _, _, _, _, _, _, _), + [90] = PINGROUP(90, SOUTH, tsif1_error, usb2phy_ac, tgu_ch1, _, _, _, _, _, _), + [91] = PINGROUP(91, SOUTH, tsif0_error, tgu_ch2, _, _, _, _, _, _, _), + [92] = PINGROUP(92, NORTH, qup_l6, qdss_cti, _, _, _, _, _, _, _), + [93] = PINGROUP(93, NORTH, qup_l6, qdss_cti, _, _, _, _, _, _, _), + [94] = PINGROUP(94, NORTH, cam_mclk, ddr_bist, qdss_gpio, _, _, _, _, _, _), + [95] = PINGROUP(95, NORTH, cam_mclk, ddr_bist, qdss_gpio, _, _, _, _, _, _), + [96] = PINGROUP(96, NORTH, cam_mclk, pll_bypassnl, qdss_gpio, _, _, _, _, _, _), + [97] = PINGROUP(97, NORTH, cam_mclk, pll_reset, qdss_gpio, _, _, _, _, _, _), + [98] = PINGROUP(98, NORTH, cam_mclk, qdss_gpio, _, _, _, _, _, _, _), + [99] = PINGROUP(99, NORTH, cam_mclk, qdss_gpio, _, _, _, _, _, _, _), + [100] = PINGROUP(100, NORTH, cam_mclk, qdss_gpio, _, _, _, _, _, _, _), + [101] = PINGROUP(101, NORTH, cci_i2c, qdss_gpio, _, _, _, _, _, _, _), + [102] = PINGROUP(102, NORTH, cci_i2c, qdss_gpio, _, _, _, _, _, _, _), + [103] = PINGROUP(103, NORTH, cci_i2c, phase_flag, _, qdss_gpio, _, _, _, _, _), + [104] = PINGROUP(104, NORTH, cci_i2c, phase_flag, _, qdss_gpio, _, _, _, _, _), + [105] = PINGROUP(105, NORTH, cci_i2c, qdss_gpio, _, _, _, _, _, _, _), + [106] = PINGROUP(106, NORTH, cci_i2c, gcc_gp1, qdss_gpio, _, _, _, _, _, _), + [107] = PINGROUP(107, NORTH, cci_i2c, gcc_gp2, qdss_gpio, _, _, _, _, _, _), + [108] = PINGROUP(108, NORTH, cci_i2c, gcc_gp3, qdss_gpio, _, _, _, _, _, _), + [109] = PINGROUP(109, NORTH, cci_timer0, qdss_gpio, _, _, _, _, _, _, _), + [110] = PINGROUP(110, NORTH, cci_timer1, qdss_gpio, _, _, _, _, _, _, _), + [111] = PINGROUP(111, NORTH, cci_timer2, qdss_gpio, _, _, _, _, _, _, _), + [112] = PINGROUP(112, NORTH, cci_timer3, cci_async, _, _, _, _, _, _, _), + [113] = PINGROUP(113, NORTH, cci_timer4, cci_async, _, _, _, _, _, _, _), + [114] = PINGROUP(114, NORTH, cci_async, _, _, _, _, _, _, _, _), + [115] = PINGROUP(115, NORTH, qup2, phase_flag, _, _, _, _, _, _, _), + [116] = PINGROUP(116, NORTH, qup2, phase_flag, _, _, _, _, _, _, _), + [117] = PINGROUP(117, NORTH, qup2, phase_flag, _, _, _, _, _, _, _), + [118] = PINGROUP(118, NORTH, qup2, phase_flag, _, _, _, _, _, _, _), + [119] = PINGROUP(119, NORTH, qup3, phase_flag, _, _, _, _, _, _, _), + [120] = PINGROUP(120, NORTH, qup3, phase_flag, _, _, _, _, _, _, _), + [121] = PINGROUP(121, NORTH, qup3, _, _, _, _, _, _, _, _), + [122] = PINGROUP(122, NORTH, qup3, mdp_vsync, phase_flag, _, _, _, _, _, _), + [123] = PINGROUP(123, NORTH, qup_l4, tsense_pwm1, tsense_pwm2, _, _, _, _, _, _), + [124] = PINGROUP(124, NORTH, qup_l5, mdp_vsync, phase_flag, _, _, _, _, _, _), + [125] = PINGROUP(125, SOUTH, qup9, phase_flag, _, _, _, _, _, _, _), + [126] = PINGROUP(126, SOUTH, qup9, _, _, _, _, _, _, _, _), + [127] = PINGROUP(127, SOUTH, qup9, _, _, _, _, _, _, _, _), + [128] = PINGROUP(128, SOUTH, qup9, _, _, _, _, _, _, _, _), + [129] = PINGROUP(129, SOUTH, qup10, _, _, _, _, _, _, _, _), + [130] = PINGROUP(130, SOUTH, qup10, _, _, _, _, _, _, _, _), + [131] = PINGROUP(131, SOUTH, qup10, _, _, _, _, _, _, _, _), + [132] = PINGROUP(132, SOUTH, qup10, _, _, _, _, _, _, _, _), + [133] = PINGROUP(133, WEST, mi2s2_sck, _, _, _, _, _, _, _, _), + [134] = PINGROUP(134, WEST, mi2s2_data0, _, _, _, _, _, _, _, _), + [135] = PINGROUP(135, WEST, mi2s2_ws, _, _, _, _, _, _, _, _), + [136] = PINGROUP(136, WEST, pri_mi2s, gcc_gp1, _, _, _, _, _, _, _), + [137] = PINGROUP(137, WEST, sec_mi2s, audio_ref, mi2s2_data1, gcc_gp2, _, _, _, _, _), + [138] = PINGROUP(138, WEST, mi2s0_sck, gcc_gp3, _, _, _, _, _, _, _), + [139] = PINGROUP(139, WEST, mi2s0_data0, _, _, _, _, _, _, _, _), + [140] = PINGROUP(140, WEST, mi2s0_data1, _, _, _, _, _, _, _, _), + [141] = PINGROUP(141, WEST, mi2s0_ws, _, _, _, _, _, _, _, _), + [142] = PINGROUP(142, WEST, lpass_slimbus, mi2s1_sck, _, _, _, _, _, _, _), + [143] = PINGROUP(143, WEST, lpass_slimbus, mi2s1_data0, ddr_bist, _, _, _, _, _, _), + [144] = PINGROUP(144, WEST, lpass_slimbus, mi2s1_data1, ddr_bist, _, _, _, _, _, _), + [145] = PINGROUP(145, WEST, lpass_slimbus, mi2s1_ws, _, _, _, _, _, _, _), + [146] = PINGROUP(146, WEST, _, _, _, _, _, _, _, _, _), + [147] = PINGROUP(147, WEST, _, _, _, _, _, _, _, _, _), + [148] = PINGROUP(148, WEST, _, _, _, _, _, _, _, _, _), + [149] = PINGROUP(149, WEST, _, _, _, _, _, _, _, _, _), + [150] = PINGROUP(150, WEST, _, _, _, _, _, _, _, _, _), + [151] = PINGROUP(151, WEST, _, _, _, _, _, _, _, _, _), + [152] = PINGROUP(152, WEST, _, _, _, _, _, _, _, _, _), + [153] = PINGROUP(153, WEST, _, _, _, _, _, _, _, _, _), + [154] = PINGROUP(154, WEST, _, _, _, _, _, _, _, _, _), + [155] = PINGROUP(155, WEST, _, _, _, _, _, _, _, _, _), + [156] = PINGROUP(156, WEST, _, _, _, _, _, _, _, _, _), + [157] = PINGROUP(157, WEST, _, _, _, _, _, _, _, _, _), + [158] = PINGROUP(158, WEST, _, _, _, _, _, _, _, _, _), + [159] = PINGROUP(159, WEST, cri_trng0, _, _, _, _, _, _, _, _), + [160] = PINGROUP(160, WEST, cri_trng1, qdss_gpio, _, _, _, _, _, _, _), + [161] = PINGROUP(161, WEST, cri_trng, qdss_gpio, _, _, _, _, _, _, _), + [162] = PINGROUP(162, WEST, sp_cmu, qdss_gpio, _, _, _, _, _, _, _), + [163] = PINGROUP(163, WEST, prng_rosc, qdss_gpio, _, _, _, _, _, _, _), + [164] = PINGROUP(164, WEST, qdss_gpio, _, _, _, _, _, _, _, _), + [165] = PINGROUP(165, WEST, qdss_gpio, _, _, _, _, _, _, _, _), + [166] = PINGROUP(166, WEST, qdss_gpio, _, _, _, _, _, _, _, _), + [167] = PINGROUP(167, WEST, qdss_gpio, _, _, _, _, _, _, _, _), + [168] = PINGROUP(168, WEST, qdss_gpio, _, _, _, _, _, _, _, _), + [169] = PINGROUP(169, WEST, qdss_gpio, _, _, _, _, _, _, _, _), + [170] = PINGROUP(170, WEST, qdss_gpio, _, _, _, _, _, _, _, _), + [171] = PINGROUP(171, WEST, qdss_gpio, _, _, _, _, _, _, _, _), + [172] = PINGROUP(172, WEST, qdss_gpio, _, _, _, _, _, _, _, _), + [173] = PINGROUP(173, WEST, qdss_gpio, _, _, _, _, _, _, _, _), + [174] = PINGROUP(174, WEST, qdss_gpio, _, _, _, _, _, _, _, _), + [175] = PINGROUP(175, WEST, qdss_gpio, _, _, _, _, _, _, _, _), + [176] = PINGROUP(176, WEST, qdss_gpio, _, _, _, _, _, _, _, _), + [177] = PINGROUP(177, WEST, qdss_gpio, _, _, _, _, _, _, _, _), + [178] = PINGROUP(178, WEST, _, _, _, _, _, _, _, _, _), + [179] = PINGROUP(179, WEST, _, _, _, _, _, _, _, _, _), + [180] = UFS_RESET(ufs_reset, 0xb8000), + [181] = SDC_PINGROUP(sdc2_clk, 0xb7000, 14, 6), + [182] = SDC_PINGROUP(sdc2_cmd, 0xb7000, 11, 3), + [183] = SDC_PINGROUP(sdc2_data, 0xb7000, 9, 0), +}; + +static const struct msm_gpio_wakeirq_map sm8250_pdc_map[] = { + { 0, 79 }, { 1, 84 }, { 2, 80 }, { 3, 82 }, { 4, 107 }, { 7, 43 }, + { 11, 42 }, { 14, 44 }, { 15, 52 }, { 19, 67 }, { 23, 68 }, { 24, 105 }, + { 27, 92 }, { 28, 106 }, { 31, 69 }, { 35, 70 }, { 39, 73 }, + { 40, 108 }, { 43, 71 }, { 45, 72 }, { 47, 83 }, { 51, 74 }, { 55, 77 }, + { 59, 78 }, { 63, 75 }, { 64, 81 }, { 65, 87 }, { 66, 88 }, { 67, 89 }, + { 68, 54 }, { 70, 85 }, { 77, 46 }, { 80, 90 }, { 81, 91 }, { 83, 97 }, + { 84, 98 }, { 86, 99 }, { 87, 100 }, { 88, 101 }, { 89, 102 }, + { 92, 103 }, { 93, 104 }, { 100, 53 }, { 103, 47 }, { 104, 48 }, + { 108, 49 }, { 109, 94 }, { 110, 95 }, { 111, 96 }, { 112, 55 }, + { 113, 56 }, { 118, 50 }, { 121, 51 }, { 122, 57 }, { 123, 58 }, + { 124, 45 }, { 126, 59 }, { 128, 76 }, { 129, 86 }, { 132, 93 }, + { 133, 65 }, { 134, 66 }, { 136, 62 }, { 137, 63 }, { 138, 64 }, + { 142, 60 }, { 143, 61 } +}; + +static const struct msm_pinctrl_soc_data sm8250_pinctrl = { + .pins = sm8250_pins, + .npins = ARRAY_SIZE(sm8250_pins), + .functions = sm8250_functions, + .nfunctions = ARRAY_SIZE(sm8250_functions), + .groups = sm8250_groups, + .ngroups = ARRAY_SIZE(sm8250_groups), + .ngpios = 181, + .tiles = sm8250_tiles, + .ntiles = ARRAY_SIZE(sm8250_tiles), + .wakeirq_map = sm8250_pdc_map, + .nwakeirq_map = ARRAY_SIZE(sm8250_pdc_map), +}; + +static int sm8250_pinctrl_probe(struct platform_device *pdev) +{ + return msm_pinctrl_probe(pdev, &sm8250_pinctrl); +} + +static const struct of_device_id sm8250_pinctrl_of_match[] = { + { .compatible = "qcom,sm8250-pinctrl", }, + { }, +}; + +static struct platform_driver sm8250_pinctrl_driver = { + .driver = { + .name = "sm8250-pinctrl", + .of_match_table = sm8250_pinctrl_of_match, + }, + .probe = sm8250_pinctrl_probe, + .remove = msm_pinctrl_remove, +}; + +static int __init sm8250_pinctrl_init(void) +{ + return platform_driver_register(&sm8250_pinctrl_driver); +} +arch_initcall(sm8250_pinctrl_init); + +static void __exit sm8250_pinctrl_exit(void) +{ + platform_driver_unregister(&sm8250_pinctrl_driver); +} +module_exit(sm8250_pinctrl_exit); + +MODULE_DESCRIPTION("QTI sm8250 pinctrl driver"); +MODULE_LICENSE("GPL v2"); +MODULE_DEVICE_TABLE(of, sm8250_pinctrl_of_match); diff --git a/drivers/pinctrl/qcom/pinctrl-sm8350-lpass-lpi.c b/drivers/pinctrl/qcom/pinctrl-sm8350-lpass-lpi.c new file mode 100644 index 0000000000..f889c779bc --- /dev/null +++ b/drivers/pinctrl/qcom/pinctrl-sm8350-lpass-lpi.c @@ -0,0 +1,167 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2016-2019, The Linux Foundation. All rights reserved. + * Copyright (c) 2020-2023 Linaro Ltd. + */ + +#include <linux/gpio/driver.h> +#include <linux/module.h> +#include <linux/platform_device.h> + +#include "pinctrl-lpass-lpi.h" + +enum lpass_lpi_functions { + LPI_MUX_dmic1_clk, + LPI_MUX_dmic1_data, + LPI_MUX_dmic2_clk, + LPI_MUX_dmic2_data, + LPI_MUX_dmic3_clk, + LPI_MUX_dmic3_data, + LPI_MUX_i2s1_clk, + LPI_MUX_i2s1_data, + LPI_MUX_i2s1_ws, + LPI_MUX_i2s2_clk, + LPI_MUX_i2s2_data, + LPI_MUX_i2s2_ws, + LPI_MUX_qua_mi2s_data, + LPI_MUX_qua_mi2s_sclk, + LPI_MUX_qua_mi2s_ws, + LPI_MUX_swr_rx_clk, + LPI_MUX_swr_rx_data, + LPI_MUX_swr_tx_clk, + LPI_MUX_swr_tx_data, + LPI_MUX_wsa_swr_clk, + LPI_MUX_wsa_swr_data, + LPI_MUX_gpio, + LPI_MUX__, +}; + +static int gpio0_pins[] = { 0 }; +static int gpio1_pins[] = { 1 }; +static int gpio2_pins[] = { 2 }; +static int gpio3_pins[] = { 3 }; +static int gpio4_pins[] = { 4 }; +static int gpio5_pins[] = { 5 }; +static int gpio6_pins[] = { 6 }; +static int gpio7_pins[] = { 7 }; +static int gpio8_pins[] = { 8 }; +static int gpio9_pins[] = { 9 }; +static int gpio10_pins[] = { 10 }; +static int gpio11_pins[] = { 11 }; +static int gpio12_pins[] = { 12 }; +static int gpio13_pins[] = { 13 }; +static int gpio14_pins[] = { 14 }; + +static const struct pinctrl_pin_desc sm8350_lpi_pins[] = { + PINCTRL_PIN(0, "gpio0"), + PINCTRL_PIN(1, "gpio1"), + PINCTRL_PIN(2, "gpio2"), + PINCTRL_PIN(3, "gpio3"), + PINCTRL_PIN(4, "gpio4"), + PINCTRL_PIN(5, "gpio5"), + PINCTRL_PIN(6, "gpio6"), + PINCTRL_PIN(7, "gpio7"), + PINCTRL_PIN(8, "gpio8"), + PINCTRL_PIN(9, "gpio9"), + PINCTRL_PIN(10, "gpio10"), + PINCTRL_PIN(11, "gpio11"), + PINCTRL_PIN(12, "gpio12"), + PINCTRL_PIN(13, "gpio13"), + PINCTRL_PIN(14, "gpio14"), +}; + +static const char * const swr_tx_clk_groups[] = { "gpio0" }; +static const char * const swr_tx_data_groups[] = { "gpio1", "gpio2", "gpio5", "gpio14" }; +static const char * const swr_rx_clk_groups[] = { "gpio3" }; +static const char * const swr_rx_data_groups[] = { "gpio4", "gpio5" }; +static const char * const dmic1_clk_groups[] = { "gpio6" }; +static const char * const dmic1_data_groups[] = { "gpio7" }; +static const char * const dmic2_clk_groups[] = { "gpio8" }; +static const char * const dmic2_data_groups[] = { "gpio9" }; +static const char * const i2s2_clk_groups[] = { "gpio10" }; +static const char * const i2s2_ws_groups[] = { "gpio11" }; +static const char * const dmic3_clk_groups[] = { "gpio12" }; +static const char * const dmic3_data_groups[] = { "gpio13" }; +static const char * const qua_mi2s_sclk_groups[] = { "gpio0" }; +static const char * const qua_mi2s_ws_groups[] = { "gpio1" }; +static const char * const qua_mi2s_data_groups[] = { "gpio2", "gpio3", "gpio4" }; +static const char * const i2s1_clk_groups[] = { "gpio6" }; +static const char * const i2s1_ws_groups[] = { "gpio7" }; +static const char * const i2s1_data_groups[] = { "gpio8", "gpio9" }; +static const char * const wsa_swr_clk_groups[] = { "gpio10" }; +static const char * const wsa_swr_data_groups[] = { "gpio11" }; +static const char * const i2s2_data_groups[] = { "gpio12", "gpio12" }; + +static const struct lpi_pingroup sm8350_groups[] = { + LPI_PINGROUP(0, 0, swr_tx_clk, qua_mi2s_sclk, _, _), + LPI_PINGROUP(1, 2, swr_tx_data, qua_mi2s_ws, _, _), + LPI_PINGROUP(2, 4, swr_tx_data, qua_mi2s_data, _, _), + LPI_PINGROUP(3, 8, swr_rx_clk, qua_mi2s_data, _, _), + LPI_PINGROUP(4, 10, swr_rx_data, qua_mi2s_data, _, _), + LPI_PINGROUP(5, 12, swr_tx_data, swr_rx_data, _, _), + LPI_PINGROUP(6, LPI_NO_SLEW, dmic1_clk, i2s1_clk, _, _), + LPI_PINGROUP(7, LPI_NO_SLEW, dmic1_data, i2s1_ws, _, _), + LPI_PINGROUP(8, LPI_NO_SLEW, dmic2_clk, i2s1_data, _, _), + LPI_PINGROUP(9, LPI_NO_SLEW, dmic2_data, i2s1_data, _, _), + LPI_PINGROUP(10, 16, i2s2_clk, wsa_swr_clk, _, _), + LPI_PINGROUP(11, 18, i2s2_ws, wsa_swr_data, _, _), + LPI_PINGROUP(12, LPI_NO_SLEW, dmic3_clk, i2s2_data, _, _), + LPI_PINGROUP(13, LPI_NO_SLEW, dmic3_data, i2s2_data, _, _), + LPI_PINGROUP(14, 6, swr_tx_data, _, _, _), +}; + +static const struct lpi_function sm8350_functions[] = { + LPI_FUNCTION(dmic1_clk), + LPI_FUNCTION(dmic1_data), + LPI_FUNCTION(dmic2_clk), + LPI_FUNCTION(dmic2_data), + LPI_FUNCTION(dmic3_clk), + LPI_FUNCTION(dmic3_data), + LPI_FUNCTION(i2s1_clk), + LPI_FUNCTION(i2s1_data), + LPI_FUNCTION(i2s1_ws), + LPI_FUNCTION(i2s2_clk), + LPI_FUNCTION(i2s2_data), + LPI_FUNCTION(i2s2_ws), + LPI_FUNCTION(qua_mi2s_data), + LPI_FUNCTION(qua_mi2s_sclk), + LPI_FUNCTION(qua_mi2s_ws), + LPI_FUNCTION(swr_rx_clk), + LPI_FUNCTION(swr_rx_data), + LPI_FUNCTION(swr_tx_clk), + LPI_FUNCTION(swr_tx_data), + LPI_FUNCTION(wsa_swr_clk), + LPI_FUNCTION(wsa_swr_data), +}; + +static const struct lpi_pinctrl_variant_data sm8350_lpi_data = { + .pins = sm8350_lpi_pins, + .npins = ARRAY_SIZE(sm8350_lpi_pins), + .groups = sm8350_groups, + .ngroups = ARRAY_SIZE(sm8350_groups), + .functions = sm8350_functions, + .nfunctions = ARRAY_SIZE(sm8350_functions), +}; + +static const struct of_device_id lpi_pinctrl_of_match[] = { + { + .compatible = "qcom,sm8350-lpass-lpi-pinctrl", + .data = &sm8350_lpi_data, + }, + { } +}; +MODULE_DEVICE_TABLE(of, lpi_pinctrl_of_match); + +static struct platform_driver lpi_pinctrl_driver = { + .driver = { + .name = "qcom-sm8350-lpass-lpi-pinctrl", + .of_match_table = lpi_pinctrl_of_match, + }, + .probe = lpi_pinctrl_probe, + .remove = lpi_pinctrl_remove, +}; +module_platform_driver(lpi_pinctrl_driver); + +MODULE_AUTHOR("Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>"); +MODULE_DESCRIPTION("QTI SM8350 LPI GPIO pin control driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/pinctrl/qcom/pinctrl-sm8350.c b/drivers/pinctrl/qcom/pinctrl-sm8350.c new file mode 100644 index 0000000000..9c69458bd9 --- /dev/null +++ b/drivers/pinctrl/qcom/pinctrl-sm8350.c @@ -0,0 +1,1662 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2019-2020, The Linux Foundation. All rights reserved. + * Copyright (c) 2020-2021, Linaro Limited + */ + +#include <linux/module.h> +#include <linux/of.h> +#include <linux/platform_device.h> + +#include "pinctrl-msm.h" + +#define REG_SIZE 0x1000 + +#define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7, f8, f9) \ + { \ + .grp = PINCTRL_PINGROUP("gpio" #id, \ + gpio##id##_pins, \ + ARRAY_SIZE(gpio##id##_pins)), \ + .funcs = (int[]){ \ + msm_mux_gpio, /* gpio mode */ \ + msm_mux_##f1, \ + msm_mux_##f2, \ + msm_mux_##f3, \ + msm_mux_##f4, \ + msm_mux_##f5, \ + msm_mux_##f6, \ + msm_mux_##f7, \ + msm_mux_##f8, \ + msm_mux_##f9 \ + }, \ + .nfuncs = 10, \ + .ctl_reg = REG_SIZE * id, \ + .io_reg = REG_SIZE * id + 0x4, \ + .intr_cfg_reg = REG_SIZE * id + 0x8, \ + .intr_status_reg = REG_SIZE * id + 0xc, \ + .intr_target_reg = REG_SIZE * id + 0x8, \ + .mux_bit = 2, \ + .pull_bit = 0, \ + .drv_bit = 6, \ + .oe_bit = 9, \ + .in_bit = 0, \ + .out_bit = 1, \ + .intr_enable_bit = 0, \ + .intr_status_bit = 0, \ + .intr_target_bit = 5, \ + .intr_target_kpss_val = 3, \ + .intr_raw_status_bit = 4, \ + .intr_polarity_bit = 1, \ + .intr_detection_bit = 2, \ + .intr_detection_width = 2, \ + } + +#define SDC_PINGROUP(pg_name, ctl, pull, drv) \ + { \ + .grp = PINCTRL_PINGROUP(#pg_name, \ + pg_name##_pins, \ + ARRAY_SIZE(pg_name##_pins)), \ + .ctl_reg = ctl, \ + .io_reg = 0, \ + .intr_cfg_reg = 0, \ + .intr_status_reg = 0, \ + .intr_target_reg = 0, \ + .mux_bit = -1, \ + .pull_bit = pull, \ + .drv_bit = drv, \ + .oe_bit = -1, \ + .in_bit = -1, \ + .out_bit = -1, \ + .intr_enable_bit = -1, \ + .intr_status_bit = -1, \ + .intr_target_bit = -1, \ + .intr_raw_status_bit = -1, \ + .intr_polarity_bit = -1, \ + .intr_detection_bit = -1, \ + .intr_detection_width = -1, \ + } + +#define UFS_RESET(pg_name, offset) \ + { \ + .grp = PINCTRL_PINGROUP(#pg_name, \ + pg_name##_pins, \ + ARRAY_SIZE(pg_name##_pins)), \ + .ctl_reg = offset, \ + .io_reg = offset + 0x4, \ + .intr_cfg_reg = 0, \ + .intr_status_reg = 0, \ + .intr_target_reg = 0, \ + .mux_bit = -1, \ + .pull_bit = 3, \ + .drv_bit = 0, \ + .oe_bit = -1, \ + .in_bit = -1, \ + .out_bit = 0, \ + .intr_enable_bit = -1, \ + .intr_status_bit = -1, \ + .intr_target_bit = -1, \ + .intr_raw_status_bit = -1, \ + .intr_polarity_bit = -1, \ + .intr_detection_bit = -1, \ + .intr_detection_width = -1, \ + } + +static const struct pinctrl_pin_desc sm8350_pins[] = { + PINCTRL_PIN(0, "GPIO_0"), + PINCTRL_PIN(1, "GPIO_1"), + PINCTRL_PIN(2, "GPIO_2"), + PINCTRL_PIN(3, "GPIO_3"), + PINCTRL_PIN(4, "GPIO_4"), + PINCTRL_PIN(5, "GPIO_5"), + PINCTRL_PIN(6, "GPIO_6"), + PINCTRL_PIN(7, "GPIO_7"), + PINCTRL_PIN(8, "GPIO_8"), + PINCTRL_PIN(9, "GPIO_9"), + PINCTRL_PIN(10, "GPIO_10"), + PINCTRL_PIN(11, "GPIO_11"), + PINCTRL_PIN(12, "GPIO_12"), + PINCTRL_PIN(13, "GPIO_13"), + PINCTRL_PIN(14, "GPIO_14"), + PINCTRL_PIN(15, "GPIO_15"), + PINCTRL_PIN(16, "GPIO_16"), + PINCTRL_PIN(17, "GPIO_17"), + PINCTRL_PIN(18, "GPIO_18"), + PINCTRL_PIN(19, "GPIO_19"), + PINCTRL_PIN(20, "GPIO_20"), + PINCTRL_PIN(21, "GPIO_21"), + PINCTRL_PIN(22, "GPIO_22"), + PINCTRL_PIN(23, "GPIO_23"), + PINCTRL_PIN(24, "GPIO_24"), + PINCTRL_PIN(25, "GPIO_25"), + PINCTRL_PIN(26, "GPIO_26"), + PINCTRL_PIN(27, "GPIO_27"), + PINCTRL_PIN(28, "GPIO_28"), + PINCTRL_PIN(29, "GPIO_29"), + PINCTRL_PIN(30, "GPIO_30"), + PINCTRL_PIN(31, "GPIO_31"), + PINCTRL_PIN(32, "GPIO_32"), + PINCTRL_PIN(33, "GPIO_33"), + PINCTRL_PIN(34, "GPIO_34"), + PINCTRL_PIN(35, "GPIO_35"), + PINCTRL_PIN(36, "GPIO_36"), + PINCTRL_PIN(37, "GPIO_37"), + PINCTRL_PIN(38, "GPIO_38"), + PINCTRL_PIN(39, "GPIO_39"), + PINCTRL_PIN(40, "GPIO_40"), + PINCTRL_PIN(41, "GPIO_41"), + PINCTRL_PIN(42, "GPIO_42"), + PINCTRL_PIN(43, "GPIO_43"), + PINCTRL_PIN(44, "GPIO_44"), + PINCTRL_PIN(45, "GPIO_45"), + PINCTRL_PIN(46, "GPIO_46"), + PINCTRL_PIN(47, "GPIO_47"), + PINCTRL_PIN(48, "GPIO_48"), + PINCTRL_PIN(49, "GPIO_49"), + PINCTRL_PIN(50, "GPIO_50"), + PINCTRL_PIN(51, "GPIO_51"), + PINCTRL_PIN(52, "GPIO_52"), + PINCTRL_PIN(53, "GPIO_53"), + PINCTRL_PIN(54, "GPIO_54"), + PINCTRL_PIN(55, "GPIO_55"), + PINCTRL_PIN(56, "GPIO_56"), + PINCTRL_PIN(57, "GPIO_57"), + PINCTRL_PIN(58, "GPIO_58"), + PINCTRL_PIN(59, "GPIO_59"), + PINCTRL_PIN(60, "GPIO_60"), + PINCTRL_PIN(61, "GPIO_61"), + PINCTRL_PIN(62, "GPIO_62"), + PINCTRL_PIN(63, "GPIO_63"), + PINCTRL_PIN(64, "GPIO_64"), + PINCTRL_PIN(65, "GPIO_65"), + PINCTRL_PIN(66, "GPIO_66"), + PINCTRL_PIN(67, "GPIO_67"), + PINCTRL_PIN(68, "GPIO_68"), + PINCTRL_PIN(69, "GPIO_69"), + PINCTRL_PIN(70, "GPIO_70"), + PINCTRL_PIN(71, "GPIO_71"), + PINCTRL_PIN(72, "GPIO_72"), + PINCTRL_PIN(73, "GPIO_73"), + PINCTRL_PIN(74, "GPIO_74"), + PINCTRL_PIN(75, "GPIO_75"), + PINCTRL_PIN(76, "GPIO_76"), + PINCTRL_PIN(77, "GPIO_77"), + PINCTRL_PIN(78, "GPIO_78"), + PINCTRL_PIN(79, "GPIO_79"), + PINCTRL_PIN(80, "GPIO_80"), + PINCTRL_PIN(81, "GPIO_81"), + PINCTRL_PIN(82, "GPIO_82"), + PINCTRL_PIN(83, "GPIO_83"), + PINCTRL_PIN(84, "GPIO_84"), + PINCTRL_PIN(85, "GPIO_85"), + PINCTRL_PIN(86, "GPIO_86"), + PINCTRL_PIN(87, "GPIO_87"), + PINCTRL_PIN(88, "GPIO_88"), + PINCTRL_PIN(89, "GPIO_89"), + PINCTRL_PIN(90, "GPIO_90"), + PINCTRL_PIN(91, "GPIO_91"), + PINCTRL_PIN(92, "GPIO_92"), + PINCTRL_PIN(93, "GPIO_93"), + PINCTRL_PIN(94, "GPIO_94"), + PINCTRL_PIN(95, "GPIO_95"), + PINCTRL_PIN(96, "GPIO_96"), + PINCTRL_PIN(97, "GPIO_97"), + PINCTRL_PIN(98, "GPIO_98"), + PINCTRL_PIN(99, "GPIO_99"), + PINCTRL_PIN(100, "GPIO_100"), + PINCTRL_PIN(101, "GPIO_101"), + PINCTRL_PIN(102, "GPIO_102"), + PINCTRL_PIN(103, "GPIO_103"), + PINCTRL_PIN(104, "GPIO_104"), + PINCTRL_PIN(105, "GPIO_105"), + PINCTRL_PIN(106, "GPIO_106"), + PINCTRL_PIN(107, "GPIO_107"), + PINCTRL_PIN(108, "GPIO_108"), + PINCTRL_PIN(109, "GPIO_109"), + PINCTRL_PIN(110, "GPIO_110"), + PINCTRL_PIN(111, "GPIO_111"), + PINCTRL_PIN(112, "GPIO_112"), + PINCTRL_PIN(113, "GPIO_113"), + PINCTRL_PIN(114, "GPIO_114"), + PINCTRL_PIN(115, "GPIO_115"), + PINCTRL_PIN(116, "GPIO_116"), + PINCTRL_PIN(117, "GPIO_117"), + PINCTRL_PIN(118, "GPIO_118"), + PINCTRL_PIN(119, "GPIO_119"), + PINCTRL_PIN(120, "GPIO_120"), + PINCTRL_PIN(121, "GPIO_121"), + PINCTRL_PIN(122, "GPIO_122"), + PINCTRL_PIN(123, "GPIO_123"), + PINCTRL_PIN(124, "GPIO_124"), + PINCTRL_PIN(125, "GPIO_125"), + PINCTRL_PIN(126, "GPIO_126"), + PINCTRL_PIN(127, "GPIO_127"), + PINCTRL_PIN(128, "GPIO_128"), + PINCTRL_PIN(129, "GPIO_129"), + PINCTRL_PIN(130, "GPIO_130"), + PINCTRL_PIN(131, "GPIO_131"), + PINCTRL_PIN(132, "GPIO_132"), + PINCTRL_PIN(133, "GPIO_133"), + PINCTRL_PIN(134, "GPIO_134"), + PINCTRL_PIN(135, "GPIO_135"), + PINCTRL_PIN(136, "GPIO_136"), + PINCTRL_PIN(137, "GPIO_137"), + PINCTRL_PIN(138, "GPIO_138"), + PINCTRL_PIN(139, "GPIO_139"), + PINCTRL_PIN(140, "GPIO_140"), + PINCTRL_PIN(141, "GPIO_141"), + PINCTRL_PIN(142, "GPIO_142"), + PINCTRL_PIN(143, "GPIO_143"), + PINCTRL_PIN(144, "GPIO_144"), + PINCTRL_PIN(145, "GPIO_145"), + PINCTRL_PIN(146, "GPIO_146"), + PINCTRL_PIN(147, "GPIO_147"), + PINCTRL_PIN(148, "GPIO_148"), + PINCTRL_PIN(149, "GPIO_149"), + PINCTRL_PIN(150, "GPIO_150"), + PINCTRL_PIN(151, "GPIO_151"), + PINCTRL_PIN(152, "GPIO_152"), + PINCTRL_PIN(153, "GPIO_153"), + PINCTRL_PIN(154, "GPIO_154"), + PINCTRL_PIN(155, "GPIO_155"), + PINCTRL_PIN(156, "GPIO_156"), + PINCTRL_PIN(157, "GPIO_157"), + PINCTRL_PIN(158, "GPIO_158"), + PINCTRL_PIN(159, "GPIO_159"), + PINCTRL_PIN(160, "GPIO_160"), + PINCTRL_PIN(161, "GPIO_161"), + PINCTRL_PIN(162, "GPIO_162"), + PINCTRL_PIN(163, "GPIO_163"), + PINCTRL_PIN(164, "GPIO_164"), + PINCTRL_PIN(165, "GPIO_165"), + PINCTRL_PIN(166, "GPIO_166"), + PINCTRL_PIN(167, "GPIO_167"), + PINCTRL_PIN(168, "GPIO_168"), + PINCTRL_PIN(169, "GPIO_169"), + PINCTRL_PIN(170, "GPIO_170"), + PINCTRL_PIN(171, "GPIO_171"), + PINCTRL_PIN(172, "GPIO_172"), + PINCTRL_PIN(173, "GPIO_173"), + PINCTRL_PIN(174, "GPIO_174"), + PINCTRL_PIN(175, "GPIO_175"), + PINCTRL_PIN(176, "GPIO_176"), + PINCTRL_PIN(177, "GPIO_177"), + PINCTRL_PIN(178, "GPIO_178"), + PINCTRL_PIN(179, "GPIO_179"), + PINCTRL_PIN(180, "GPIO_180"), + PINCTRL_PIN(181, "GPIO_181"), + PINCTRL_PIN(182, "GPIO_182"), + PINCTRL_PIN(183, "GPIO_183"), + PINCTRL_PIN(184, "GPIO_184"), + PINCTRL_PIN(185, "GPIO_185"), + PINCTRL_PIN(186, "GPIO_186"), + PINCTRL_PIN(187, "GPIO_187"), + PINCTRL_PIN(188, "GPIO_188"), + PINCTRL_PIN(189, "GPIO_189"), + PINCTRL_PIN(190, "GPIO_190"), + PINCTRL_PIN(191, "GPIO_191"), + PINCTRL_PIN(192, "GPIO_192"), + PINCTRL_PIN(193, "GPIO_193"), + PINCTRL_PIN(194, "GPIO_194"), + PINCTRL_PIN(195, "GPIO_195"), + PINCTRL_PIN(196, "GPIO_196"), + PINCTRL_PIN(197, "GPIO_197"), + PINCTRL_PIN(198, "GPIO_198"), + PINCTRL_PIN(199, "GPIO_199"), + PINCTRL_PIN(200, "GPIO_200"), + PINCTRL_PIN(201, "GPIO_201"), + PINCTRL_PIN(202, "GPIO_202"), + PINCTRL_PIN(203, "UFS_RESET"), + PINCTRL_PIN(204, "SDC2_CLK"), + PINCTRL_PIN(205, "SDC2_CMD"), + PINCTRL_PIN(206, "SDC2_DATA"), +}; + +#define DECLARE_MSM_GPIO_PINS(pin) \ + static const unsigned int gpio##pin##_pins[] = { pin } +DECLARE_MSM_GPIO_PINS(0); +DECLARE_MSM_GPIO_PINS(1); +DECLARE_MSM_GPIO_PINS(2); +DECLARE_MSM_GPIO_PINS(3); +DECLARE_MSM_GPIO_PINS(4); +DECLARE_MSM_GPIO_PINS(5); +DECLARE_MSM_GPIO_PINS(6); +DECLARE_MSM_GPIO_PINS(7); +DECLARE_MSM_GPIO_PINS(8); +DECLARE_MSM_GPIO_PINS(9); +DECLARE_MSM_GPIO_PINS(10); +DECLARE_MSM_GPIO_PINS(11); +DECLARE_MSM_GPIO_PINS(12); +DECLARE_MSM_GPIO_PINS(13); +DECLARE_MSM_GPIO_PINS(14); +DECLARE_MSM_GPIO_PINS(15); +DECLARE_MSM_GPIO_PINS(16); +DECLARE_MSM_GPIO_PINS(17); +DECLARE_MSM_GPIO_PINS(18); +DECLARE_MSM_GPIO_PINS(19); +DECLARE_MSM_GPIO_PINS(20); +DECLARE_MSM_GPIO_PINS(21); +DECLARE_MSM_GPIO_PINS(22); +DECLARE_MSM_GPIO_PINS(23); +DECLARE_MSM_GPIO_PINS(24); +DECLARE_MSM_GPIO_PINS(25); +DECLARE_MSM_GPIO_PINS(26); +DECLARE_MSM_GPIO_PINS(27); +DECLARE_MSM_GPIO_PINS(28); +DECLARE_MSM_GPIO_PINS(29); +DECLARE_MSM_GPIO_PINS(30); +DECLARE_MSM_GPIO_PINS(31); +DECLARE_MSM_GPIO_PINS(32); +DECLARE_MSM_GPIO_PINS(33); +DECLARE_MSM_GPIO_PINS(34); +DECLARE_MSM_GPIO_PINS(35); +DECLARE_MSM_GPIO_PINS(36); +DECLARE_MSM_GPIO_PINS(37); +DECLARE_MSM_GPIO_PINS(38); +DECLARE_MSM_GPIO_PINS(39); +DECLARE_MSM_GPIO_PINS(40); +DECLARE_MSM_GPIO_PINS(41); +DECLARE_MSM_GPIO_PINS(42); +DECLARE_MSM_GPIO_PINS(43); +DECLARE_MSM_GPIO_PINS(44); +DECLARE_MSM_GPIO_PINS(45); +DECLARE_MSM_GPIO_PINS(46); +DECLARE_MSM_GPIO_PINS(47); +DECLARE_MSM_GPIO_PINS(48); +DECLARE_MSM_GPIO_PINS(49); +DECLARE_MSM_GPIO_PINS(50); +DECLARE_MSM_GPIO_PINS(51); +DECLARE_MSM_GPIO_PINS(52); +DECLARE_MSM_GPIO_PINS(53); +DECLARE_MSM_GPIO_PINS(54); +DECLARE_MSM_GPIO_PINS(55); +DECLARE_MSM_GPIO_PINS(56); +DECLARE_MSM_GPIO_PINS(57); +DECLARE_MSM_GPIO_PINS(58); +DECLARE_MSM_GPIO_PINS(59); +DECLARE_MSM_GPIO_PINS(60); +DECLARE_MSM_GPIO_PINS(61); +DECLARE_MSM_GPIO_PINS(62); +DECLARE_MSM_GPIO_PINS(63); +DECLARE_MSM_GPIO_PINS(64); +DECLARE_MSM_GPIO_PINS(65); +DECLARE_MSM_GPIO_PINS(66); +DECLARE_MSM_GPIO_PINS(67); +DECLARE_MSM_GPIO_PINS(68); +DECLARE_MSM_GPIO_PINS(69); +DECLARE_MSM_GPIO_PINS(70); +DECLARE_MSM_GPIO_PINS(71); +DECLARE_MSM_GPIO_PINS(72); +DECLARE_MSM_GPIO_PINS(73); +DECLARE_MSM_GPIO_PINS(74); +DECLARE_MSM_GPIO_PINS(75); +DECLARE_MSM_GPIO_PINS(76); +DECLARE_MSM_GPIO_PINS(77); +DECLARE_MSM_GPIO_PINS(78); +DECLARE_MSM_GPIO_PINS(79); +DECLARE_MSM_GPIO_PINS(80); +DECLARE_MSM_GPIO_PINS(81); +DECLARE_MSM_GPIO_PINS(82); +DECLARE_MSM_GPIO_PINS(83); +DECLARE_MSM_GPIO_PINS(84); +DECLARE_MSM_GPIO_PINS(85); +DECLARE_MSM_GPIO_PINS(86); +DECLARE_MSM_GPIO_PINS(87); +DECLARE_MSM_GPIO_PINS(88); +DECLARE_MSM_GPIO_PINS(89); +DECLARE_MSM_GPIO_PINS(90); +DECLARE_MSM_GPIO_PINS(91); +DECLARE_MSM_GPIO_PINS(92); +DECLARE_MSM_GPIO_PINS(93); +DECLARE_MSM_GPIO_PINS(94); +DECLARE_MSM_GPIO_PINS(95); +DECLARE_MSM_GPIO_PINS(96); +DECLARE_MSM_GPIO_PINS(97); +DECLARE_MSM_GPIO_PINS(98); +DECLARE_MSM_GPIO_PINS(99); +DECLARE_MSM_GPIO_PINS(100); +DECLARE_MSM_GPIO_PINS(101); +DECLARE_MSM_GPIO_PINS(102); +DECLARE_MSM_GPIO_PINS(103); +DECLARE_MSM_GPIO_PINS(104); +DECLARE_MSM_GPIO_PINS(105); +DECLARE_MSM_GPIO_PINS(106); +DECLARE_MSM_GPIO_PINS(107); +DECLARE_MSM_GPIO_PINS(108); +DECLARE_MSM_GPIO_PINS(109); +DECLARE_MSM_GPIO_PINS(110); +DECLARE_MSM_GPIO_PINS(111); +DECLARE_MSM_GPIO_PINS(112); +DECLARE_MSM_GPIO_PINS(113); +DECLARE_MSM_GPIO_PINS(114); +DECLARE_MSM_GPIO_PINS(115); +DECLARE_MSM_GPIO_PINS(116); +DECLARE_MSM_GPIO_PINS(117); +DECLARE_MSM_GPIO_PINS(118); +DECLARE_MSM_GPIO_PINS(119); +DECLARE_MSM_GPIO_PINS(120); +DECLARE_MSM_GPIO_PINS(121); +DECLARE_MSM_GPIO_PINS(122); +DECLARE_MSM_GPIO_PINS(123); +DECLARE_MSM_GPIO_PINS(124); +DECLARE_MSM_GPIO_PINS(125); +DECLARE_MSM_GPIO_PINS(126); +DECLARE_MSM_GPIO_PINS(127); +DECLARE_MSM_GPIO_PINS(128); +DECLARE_MSM_GPIO_PINS(129); +DECLARE_MSM_GPIO_PINS(130); +DECLARE_MSM_GPIO_PINS(131); +DECLARE_MSM_GPIO_PINS(132); +DECLARE_MSM_GPIO_PINS(133); +DECLARE_MSM_GPIO_PINS(134); +DECLARE_MSM_GPIO_PINS(135); +DECLARE_MSM_GPIO_PINS(136); +DECLARE_MSM_GPIO_PINS(137); +DECLARE_MSM_GPIO_PINS(138); +DECLARE_MSM_GPIO_PINS(139); +DECLARE_MSM_GPIO_PINS(140); +DECLARE_MSM_GPIO_PINS(141); +DECLARE_MSM_GPIO_PINS(142); +DECLARE_MSM_GPIO_PINS(143); +DECLARE_MSM_GPIO_PINS(144); +DECLARE_MSM_GPIO_PINS(145); +DECLARE_MSM_GPIO_PINS(146); +DECLARE_MSM_GPIO_PINS(147); +DECLARE_MSM_GPIO_PINS(148); +DECLARE_MSM_GPIO_PINS(149); +DECLARE_MSM_GPIO_PINS(150); +DECLARE_MSM_GPIO_PINS(151); +DECLARE_MSM_GPIO_PINS(152); +DECLARE_MSM_GPIO_PINS(153); +DECLARE_MSM_GPIO_PINS(154); +DECLARE_MSM_GPIO_PINS(155); +DECLARE_MSM_GPIO_PINS(156); +DECLARE_MSM_GPIO_PINS(157); +DECLARE_MSM_GPIO_PINS(158); +DECLARE_MSM_GPIO_PINS(159); +DECLARE_MSM_GPIO_PINS(160); +DECLARE_MSM_GPIO_PINS(161); +DECLARE_MSM_GPIO_PINS(162); +DECLARE_MSM_GPIO_PINS(163); +DECLARE_MSM_GPIO_PINS(164); +DECLARE_MSM_GPIO_PINS(165); +DECLARE_MSM_GPIO_PINS(166); +DECLARE_MSM_GPIO_PINS(167); +DECLARE_MSM_GPIO_PINS(168); +DECLARE_MSM_GPIO_PINS(169); +DECLARE_MSM_GPIO_PINS(170); +DECLARE_MSM_GPIO_PINS(171); +DECLARE_MSM_GPIO_PINS(172); +DECLARE_MSM_GPIO_PINS(173); +DECLARE_MSM_GPIO_PINS(174); +DECLARE_MSM_GPIO_PINS(175); +DECLARE_MSM_GPIO_PINS(176); +DECLARE_MSM_GPIO_PINS(177); +DECLARE_MSM_GPIO_PINS(178); +DECLARE_MSM_GPIO_PINS(179); +DECLARE_MSM_GPIO_PINS(180); +DECLARE_MSM_GPIO_PINS(181); +DECLARE_MSM_GPIO_PINS(182); +DECLARE_MSM_GPIO_PINS(183); +DECLARE_MSM_GPIO_PINS(184); +DECLARE_MSM_GPIO_PINS(185); +DECLARE_MSM_GPIO_PINS(186); +DECLARE_MSM_GPIO_PINS(187); +DECLARE_MSM_GPIO_PINS(188); +DECLARE_MSM_GPIO_PINS(189); +DECLARE_MSM_GPIO_PINS(190); +DECLARE_MSM_GPIO_PINS(191); +DECLARE_MSM_GPIO_PINS(192); +DECLARE_MSM_GPIO_PINS(193); +DECLARE_MSM_GPIO_PINS(194); +DECLARE_MSM_GPIO_PINS(195); +DECLARE_MSM_GPIO_PINS(196); +DECLARE_MSM_GPIO_PINS(197); +DECLARE_MSM_GPIO_PINS(198); +DECLARE_MSM_GPIO_PINS(199); +DECLARE_MSM_GPIO_PINS(200); +DECLARE_MSM_GPIO_PINS(201); +DECLARE_MSM_GPIO_PINS(202); + +static const unsigned int ufs_reset_pins[] = { 203 }; +static const unsigned int sdc2_clk_pins[] = { 204 }; +static const unsigned int sdc2_cmd_pins[] = { 205 }; +static const unsigned int sdc2_data_pins[] = { 206 }; + +enum sm8350_functions { + msm_mux_atest_char, + msm_mux_atest_usb, + msm_mux_audio_ref, + msm_mux_cam_mclk, + msm_mux_cci_async, + msm_mux_cci_i2c, + msm_mux_cci_timer, + msm_mux_cmu_rng, + msm_mux_coex_uart1, + msm_mux_coex_uart2, + msm_mux_cri_trng, + msm_mux_cri_trng0, + msm_mux_cri_trng1, + msm_mux_dbg_out, + msm_mux_ddr_bist, + msm_mux_ddr_pxi0, + msm_mux_ddr_pxi1, + msm_mux_ddr_pxi2, + msm_mux_ddr_pxi3, + msm_mux_dp_hot, + msm_mux_dp_lcd, + msm_mux_gcc_gp1, + msm_mux_gcc_gp2, + msm_mux_gcc_gp3, + msm_mux_gpio, + msm_mux_ibi_i3c, + msm_mux_jitter_bist, + msm_mux_lpass_slimbus, + msm_mux_mdp_vsync, + msm_mux_mdp_vsync0, + msm_mux_mdp_vsync1, + msm_mux_mdp_vsync2, + msm_mux_mdp_vsync3, + msm_mux_mi2s0_data0, + msm_mux_mi2s0_data1, + msm_mux_mi2s0_sck, + msm_mux_mi2s0_ws, + msm_mux_mi2s1_data0, + msm_mux_mi2s1_data1, + msm_mux_mi2s1_sck, + msm_mux_mi2s1_ws, + msm_mux_mi2s2_data0, + msm_mux_mi2s2_data1, + msm_mux_mi2s2_sck, + msm_mux_mi2s2_ws, + msm_mux_mss_grfc0, + msm_mux_mss_grfc1, + msm_mux_mss_grfc10, + msm_mux_mss_grfc11, + msm_mux_mss_grfc12, + msm_mux_mss_grfc2, + msm_mux_mss_grfc3, + msm_mux_mss_grfc4, + msm_mux_mss_grfc5, + msm_mux_mss_grfc6, + msm_mux_mss_grfc7, + msm_mux_mss_grfc8, + msm_mux_mss_grfc9, + msm_mux_nav_gpio, + msm_mux_pa_indicator, + msm_mux_pcie0_clkreqn, + msm_mux_pcie1_clkreqn, + msm_mux_phase_flag, + msm_mux_pll_bist, + msm_mux_pll_clk, + msm_mux_pri_mi2s, + msm_mux_prng_rosc, + msm_mux_qdss_cti, + msm_mux_qdss_gpio, + msm_mux_qlink0_enable, + msm_mux_qlink0_request, + msm_mux_qlink0_wmss, + msm_mux_qlink1_enable, + msm_mux_qlink1_request, + msm_mux_qlink1_wmss, + msm_mux_qlink2_enable, + msm_mux_qlink2_request, + msm_mux_qlink2_wmss, + msm_mux_qspi0, + msm_mux_qspi1, + msm_mux_qspi2, + msm_mux_qspi3, + msm_mux_qspi_clk, + msm_mux_qspi_cs, + msm_mux_qup0, + msm_mux_qup1, + msm_mux_qup10, + msm_mux_qup11, + msm_mux_qup12, + msm_mux_qup13, + msm_mux_qup14, + msm_mux_qup15, + msm_mux_qup16, + msm_mux_qup17, + msm_mux_qup18, + msm_mux_qup19, + msm_mux_qup2, + msm_mux_qup3, + msm_mux_qup4, + msm_mux_qup5, + msm_mux_qup6, + msm_mux_qup7, + msm_mux_qup8, + msm_mux_qup9, + msm_mux_qup_l4, + msm_mux_qup_l5, + msm_mux_qup_l6, + msm_mux_sd_write, + msm_mux_sdc40, + msm_mux_sdc41, + msm_mux_sdc42, + msm_mux_sdc43, + msm_mux_sdc4_clk, + msm_mux_sdc4_cmd, + msm_mux_sec_mi2s, + msm_mux_tb_trig, + msm_mux_tgu_ch0, + msm_mux_tgu_ch1, + msm_mux_tgu_ch2, + msm_mux_tgu_ch3, + msm_mux_tsense_pwm1, + msm_mux_tsense_pwm2, + msm_mux_uim0_clk, + msm_mux_uim0_data, + msm_mux_uim0_present, + msm_mux_uim0_reset, + msm_mux_uim1_clk, + msm_mux_uim1_data, + msm_mux_uim1_present, + msm_mux_uim1_reset, + msm_mux_usb2phy_ac, + msm_mux_usb_phy, + msm_mux_vfr_0, + msm_mux_vfr_1, + msm_mux_vsense_trigger, + msm_mux__, +}; + +static const char * const gpio_groups[] = { + "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7", + "gpio8", "gpio9", "gpio10", "gpio11", "gpio12", "gpio13", "gpio14", + "gpio15", "gpio16", "gpio17", "gpio18", "gpio19", "gpio20", "gpio21", + "gpio22", "gpio23", "gpio24", "gpio25", "gpio26", "gpio27", "gpio28", + "gpio29", "gpio30", "gpio31", "gpio32", "gpio33", "gpio34", "gpio35", + "gpio36", "gpio37", "gpio38", "gpio39", "gpio40", "gpio41", "gpio42", + "gpio43", "gpio44", "gpio45", "gpio46", "gpio47", "gpio48", "gpio49", + "gpio50", "gpio51", "gpio52", "gpio53", "gpio54", "gpio55", "gpio56", + "gpio57", "gpio58", "gpio59", "gpio60", "gpio61", "gpio62", "gpio63", + "gpio64", "gpio65", "gpio66", "gpio67", "gpio68", "gpio69", "gpio70", + "gpio71", "gpio72", "gpio73", "gpio74", "gpio75", "gpio76", "gpio77", + "gpio78", "gpio79", "gpio80", "gpio81", "gpio82", "gpio83", "gpio84", + "gpio85", "gpio86", "gpio87", "gpio88", "gpio89", "gpio90", "gpio91", + "gpio92", "gpio93", "gpio94", "gpio95", "gpio96", "gpio97", "gpio98", + "gpio99", "gpio100", "gpio101", "gpio102", "gpio103", "gpio104", + "gpio105", "gpio106", "gpio107", "gpio108", "gpio109", "gpio110", + "gpio111", "gpio112", "gpio113", "gpio114", "gpio115", "gpio116", + "gpio117", "gpio118", "gpio119", "gpio120", "gpio121", "gpio122", + "gpio123", "gpio124", "gpio125", "gpio126", "gpio127", "gpio128", + "gpio129", "gpio130", "gpio131", "gpio132", "gpio133", "gpio134", + "gpio135", "gpio136", "gpio137", "gpio138", "gpio139", "gpio140", + "gpio141", "gpio142", "gpio143", "gpio144", "gpio145", "gpio146", + "gpio147", "gpio148", "gpio149", "gpio150", "gpio151", "gpio152", + "gpio153", "gpio154", "gpio155", "gpio156", "gpio157", "gpio158", + "gpio159", "gpio160", "gpio161", "gpio162", "gpio163", "gpio164", + "gpio165", "gpio166", "gpio167", "gpio168", "gpio169", "gpio170", + "gpio171", "gpio172", "gpio173", "gpio174", "gpio175", "gpio176", + "gpio177", "gpio178", "gpio179", "gpio180", "gpio181", "gpio182", + "gpio183", "gpio184", "gpio185", "gpio186", "gpio187", "gpio188", + "gpio189", "gpio190", "gpio191", "gpio192", "gpio193", "gpio194", + "gpio195", "gpio196", "gpio197", "gpio198", "gpio199", "gpio200", + "gpio201", "gpio202", +}; + +static const char * const atest_char_groups[] = { + "gpio85", "gpio86", "gpio87", "gpio115", "gpio117", +}; + +static const char * const atest_usb_groups[] = { + "gpio55", "gpio80", "gpio81", "gpio151", "gpio152", + "gpio153", "gpio154", "gpio158", "gpio159", "gpio161", +}; + +static const char * const audio_ref_groups[] = { + "gpio124", +}; + +static const char * const cam_mclk_groups[] = { + "gpio100", "gpio101", "gpio102", "gpio103", "gpio104", "gpio105", +}; + +static const char * const cci_async_groups[] = { + "gpio106", "gpio118", "gpio119", +}; + +static const char * const cci_i2c_groups[] = { + "gpio107", "gpio108", "gpio109", "gpio110", "gpio111", "gpio112", + "gpio113", "gpio114", +}; + +static const char * const cci_timer_groups[] = { + "gpio115", "gpio116", "gpio117", "gpio118", "gpio119", +}; + +static const char * const cmu_rng_groups[] = { + "gpio174", "gpio175", "gpio176", "gpio177", +}; + +static const char * const coex_uart1_groups[] = { + "gpio151", "gpio152", +}; + +static const char * const coex_uart2_groups[] = { + "gpio153", "gpio154", +}; + +static const char * const cri_trng_groups[] = { + "gpio186", +}; + +static const char * const cri_trng0_groups[] = { + "gpio183", +}; + +static const char * const cri_trng1_groups[] = { + "gpio184", +}; + +static const char * const dbg_out_groups[] = { + "gpio14", +}; + +static const char * const ddr_bist_groups[] = { + "gpio36", "gpio37", "gpio40", "gpio41", +}; + +static const char * const ddr_pxi0_groups[] = { + "gpio51", "gpio52", +}; + +static const char * const ddr_pxi1_groups[] = { + "gpio48", "gpio49", +}; + +static const char * const ddr_pxi2_groups[] = { + "gpio45", "gpio47", +}; + +static const char * const ddr_pxi3_groups[] = { + "gpio43", "gpio44", +}; + +static const char * const dp_hot_groups[] = { + "gpio87", +}; + +static const char * const dp_lcd_groups[] = { + "gpio83", +}; + +static const char * const gcc_gp1_groups[] = { + "gpio115", "gpio129", +}; + +static const char * const gcc_gp2_groups[] = { + "gpio116", "gpio130", +}; + +static const char * const gcc_gp3_groups[] = { + "gpio117", "gpio131", +}; + +static const char * const ibi_i3c_groups[] = { + "gpio36", "gpio37", "gpio56", "gpio57", "gpio60", "gpio61", +}; + +static const char * const jitter_bist_groups[] = { + "gpio80", +}; + +static const char * const lpass_slimbus_groups[] = { + "gpio129", "gpio130", +}; + +static const char * const mdp_vsync_groups[] = { + "gpio15", "gpio26", "gpio82", "gpio83", "gpio84", +}; + +static const char * const mdp_vsync0_groups[] = { + "gpio86", +}; + +static const char * const mdp_vsync1_groups[] = { + "gpio86", +}; + +static const char * const mdp_vsync2_groups[] = { + "gpio87", +}; + +static const char * const mdp_vsync3_groups[] = { + "gpio87", +}; + +static const char * const mi2s0_data0_groups[] = { + "gpio126", +}; + +static const char * const mi2s0_data1_groups[] = { + "gpio127", +}; + +static const char * const mi2s0_sck_groups[] = { + "gpio125", +}; + +static const char * const mi2s0_ws_groups[] = { + "gpio128", +}; + +static const char * const mi2s1_data0_groups[] = { + "gpio130", +}; + +static const char * const mi2s1_data1_groups[] = { + "gpio131", +}; + +static const char * const mi2s1_sck_groups[] = { + "gpio129", +}; + +static const char * const mi2s1_ws_groups[] = { + "gpio132", +}; + +static const char * const mi2s2_data0_groups[] = { + "gpio121", +}; + +static const char * const mi2s2_data1_groups[] = { + "gpio124", +}; + +static const char * const mi2s2_sck_groups[] = { + "gpio120", +}; + +static const char * const mi2s2_ws_groups[] = { + "gpio122", +}; + +static const char * const mss_grfc0_groups[] = { + "gpio141", "gpio158", +}; + +static const char * const mss_grfc1_groups[] = { + "gpio142", +}; + +static const char * const mss_grfc10_groups[] = { + "gpio153", +}; + +static const char * const mss_grfc11_groups[] = { + "gpio154", +}; + +static const char * const mss_grfc12_groups[] = { + "gpio157", +}; + +static const char * const mss_grfc2_groups[] = { + "gpio143", +}; + +static const char * const mss_grfc3_groups[] = { + "gpio144", +}; + +static const char * const mss_grfc4_groups[] = { + "gpio145", +}; + +static const char * const mss_grfc5_groups[] = { + "gpio146", +}; + +static const char * const mss_grfc6_groups[] = { + "gpio147", +}; + +static const char * const mss_grfc7_groups[] = { + "gpio148", +}; + +static const char * const mss_grfc8_groups[] = { + "gpio149", +}; + +static const char * const mss_grfc9_groups[] = { + "gpio150", +}; + +static const char * const nav_gpio_groups[] = { + "gpio155", "gpio156", "gpio157", +}; + +static const char * const pa_indicator_groups[] = { + "gpio157", +}; + +static const char * const pcie0_clkreqn_groups[] = { + "gpio95", +}; + +static const char * const pcie1_clkreqn_groups[] = { + "gpio98", +}; + +static const char * const phase_flag_groups[] = { + "gpio12", "gpio13", "gpio16", "gpio17", "gpio28", "gpio29", "gpio30", + "gpio31", "gpio32", "gpio33", "gpio34", "gpio35", "gpio72", "gpio73", + "gpio74", "gpio75", "gpio76", "gpio77", "gpio78", "gpio79", "gpio103", + "gpio104", "gpio105", "gpio106", "gpio107", "gpio108", "gpio109", + "gpio110", "gpio111", "gpio112", "gpio113", "gpio114", +}; + +static const char * const pll_bist_groups[] = { + "gpio81", +}; + +static const char * const pll_clk_groups[] = { + "gpio81", +}; + +static const char * const pri_mi2s_groups[] = { + "gpio123", +}; + +static const char * const prng_rosc_groups[] = { + "gpio185", +}; + +static const char * const qdss_cti_groups[] = { + "gpio14", "gpio27", "gpio87", "gpio88", "gpio89", "gpio90", "gpio91", "gpio92", +}; + +static const char * const qdss_gpio_groups[] = { + "gpio100", "gpio101", "gpio102", "gpio103", "gpio104", "gpio105", "gpio106", "gpio107", + "gpio108", "gpio109", "gpio110", "gpio111", "gpio112", "gpio113", "gpio114", "gpio115", + "gpio116", "gpio117", "gpio183", "gpio184", "gpio185", "gpio186", "gpio187", "gpio188", + "gpio189", "gpio190", "gpio191", "gpio192", "gpio193", "gpio194", "gpio195", "gpio196", + "gpio197", "gpio198", "gpio199", "gpio200", +}; + +static const char * const qlink0_enable_groups[] = { + "gpio160", +}; + +static const char * const qlink0_request_groups[] = { + "gpio159", +}; + +static const char * const qlink0_wmss_groups[] = { + "gpio161", +}; + +static const char * const qlink1_enable_groups[] = { + "gpio163", +}; + +static const char * const qlink1_request_groups[] = { + "gpio162", +}; + +static const char * const qlink1_wmss_groups[] = { + "gpio164", +}; + +static const char * const qlink2_enable_groups[] = { + "gpio166", +}; + +static const char * const qlink2_request_groups[] = { + "gpio165", +}; + +static const char * const qlink2_wmss_groups[] = { + "gpio167", +}; + +static const char * const qspi0_groups[] = { + "gpio44", +}; + +static const char * const qspi1_groups[] = { + "gpio45", +}; + +static const char * const qspi2_groups[] = { + "gpio48", +}; + +static const char * const qspi3_groups[] = { + "gpio49", +}; + +static const char * const qspi_clk_groups[] = { + "gpio50", +}; + +static const char * const qspi_cs_groups[] = { + "gpio47", "gpio51", +}; + +static const char * const qup0_groups[] = { + "gpio4", "gpio5", "gpio6", "gpio7", +}; + +static const char * const qup1_groups[] = { + "gpio8", "gpio9", "gpio10", "gpio11", +}; + +static const char * const qup10_groups[] = { + "gpio44", "gpio45", "gpio46", "gpio47", +}; + +static const char * const qup11_groups[] = { + "gpio48", "gpio49", "gpio50", "gpio51", +}; + +static const char * const qup12_groups[] = { + "gpio52", "gpio53", "gpio54", "gpio55", +}; + +static const char * const qup13_groups[] = { + "gpio0", "gpio1", "gpio2", "gpio3", +}; + +static const char * const qup14_groups[] = { + "gpio56", "gpio57", "gpio58", "gpio59", +}; + +static const char * const qup15_groups[] = { + "gpio60", "gpio61", "gpio62", "gpio63", +}; + +static const char * const qup16_groups[] = { + "gpio64", "gpio65", "gpio66", "gpio67", +}; + +static const char * const qup17_groups[] = { + "gpio72", "gpio73", "gpio74", "gpio75", +}; + +static const char * const qup18_groups[] = { + "gpio68", "gpio69", "gpio70", "gpio71", +}; + +static const char * const qup19_groups[] = { + "gpio76", "gpio77", "gpio78", "gpio79", +}; + +static const char * const qup2_groups[] = { + "gpio12", "gpio13", "gpio14", "gpio15", +}; + +static const char * const qup3_groups[] = { + "gpio16", "gpio17", "gpio18", "gpio19", +}; + +static const char * const qup4_groups[] = { + "gpio20", "gpio21", "gpio22", "gpio23", +}; + +static const char * const qup5_groups[] = { + "gpio24", "gpio25", "gpio26", "gpio27", +}; + +static const char * const qup6_groups[] = { + "gpio28", "gpio29", "gpio30", "gpio31", +}; + +static const char * const qup7_groups[] = { + "gpio32", "gpio33", "gpio34", "gpio35", +}; + +static const char * const qup8_groups[] = { + "gpio36", "gpio37", "gpio38", "gpio39", +}; + +static const char * const qup9_groups[] = { + "gpio40", "gpio41", "gpio42", "gpio43", +}; + +static const char * const qup_l4_groups[] = { + "gpio2", "gpio6", "gpio58", "gpio63", +}; + +static const char * const qup_l5_groups[] = { + "gpio3", "gpio7", "gpio59", "gpio66", +}; + +static const char * const qup_l6_groups[] = { + "gpio10", "gpio42", "gpio62", "gpio67", +}; + +static const char * const sd_write_groups[] = { + "gpio93", +}; + +static const char * const sdc40_groups[] = { + "gpio44", +}; + +static const char * const sdc41_groups[] = { + "gpio45", +}; + +static const char * const sdc42_groups[] = { + "gpio48", +}; + +static const char * const sdc43_groups[] = { + "gpio49", +}; + +static const char * const sdc4_clk_groups[] = { + "gpio50", +}; + +static const char * const sdc4_cmd_groups[] = { + "gpio51", +}; + +static const char * const sec_mi2s_groups[] = { + "gpio124", +}; + +static const char * const tb_trig_groups[] = { + "gpio64", "gpio136", +}; + +static const char * const tgu_ch0_groups[] = { + "gpio99", +}; + +static const char * const tgu_ch1_groups[] = { + "gpio100", +}; + +static const char * const tgu_ch2_groups[] = { + "gpio101", +}; + +static const char * const tgu_ch3_groups[] = { + "gpio102", +}; + +static const char * const tsense_pwm1_groups[] = { + "gpio88", +}; + +static const char * const tsense_pwm2_groups[] = { + "gpio88", +}; + +static const char * const uim0_clk_groups[] = { + "gpio138", +}; + +static const char * const uim0_data_groups[] = { + "gpio137", +}; + +static const char * const uim0_present_groups[] = { + "gpio140", +}; + +static const char * const uim0_reset_groups[] = { + "gpio139", +}; + +static const char * const uim1_clk_groups[] = { + "gpio134", +}; + +static const char * const uim1_data_groups[] = { + "gpio133", +}; + +static const char * const uim1_present_groups[] = { + "gpio136", +}; + +static const char * const uim1_reset_groups[] = { + "gpio135", +}; + +static const char * const usb2phy_ac_groups[] = { + "gpio39", "gpio80", +}; + +static const char * const usb_phy_groups[] = { + "gpio81", +}; + +static const char * const vfr_0_groups[] = { + "gpio84", +}; + +static const char * const vfr_1_groups[] = { + "gpio90", +}; + +static const char * const vsense_trigger_groups[] = { + "gpio78", +}; + +static const struct pinfunction sm8350_functions[] = { + MSM_PIN_FUNCTION(atest_char), + MSM_PIN_FUNCTION(atest_usb), + MSM_PIN_FUNCTION(audio_ref), + MSM_PIN_FUNCTION(cam_mclk), + MSM_PIN_FUNCTION(cci_async), + MSM_PIN_FUNCTION(cci_i2c), + MSM_PIN_FUNCTION(cci_timer), + MSM_PIN_FUNCTION(cmu_rng), + MSM_PIN_FUNCTION(coex_uart1), + MSM_PIN_FUNCTION(coex_uart2), + MSM_PIN_FUNCTION(cri_trng), + MSM_PIN_FUNCTION(cri_trng0), + MSM_PIN_FUNCTION(cri_trng1), + MSM_PIN_FUNCTION(dbg_out), + MSM_PIN_FUNCTION(ddr_bist), + MSM_PIN_FUNCTION(ddr_pxi0), + MSM_PIN_FUNCTION(ddr_pxi1), + MSM_PIN_FUNCTION(ddr_pxi2), + MSM_PIN_FUNCTION(ddr_pxi3), + MSM_PIN_FUNCTION(dp_hot), + MSM_PIN_FUNCTION(dp_lcd), + MSM_PIN_FUNCTION(gcc_gp1), + MSM_PIN_FUNCTION(gcc_gp2), + MSM_PIN_FUNCTION(gcc_gp3), + MSM_PIN_FUNCTION(gpio), + MSM_PIN_FUNCTION(ibi_i3c), + MSM_PIN_FUNCTION(jitter_bist), + MSM_PIN_FUNCTION(lpass_slimbus), + MSM_PIN_FUNCTION(mdp_vsync), + MSM_PIN_FUNCTION(mdp_vsync0), + MSM_PIN_FUNCTION(mdp_vsync1), + MSM_PIN_FUNCTION(mdp_vsync2), + MSM_PIN_FUNCTION(mdp_vsync3), + MSM_PIN_FUNCTION(mi2s0_data0), + MSM_PIN_FUNCTION(mi2s0_data1), + MSM_PIN_FUNCTION(mi2s0_sck), + MSM_PIN_FUNCTION(mi2s0_ws), + MSM_PIN_FUNCTION(mi2s1_data0), + MSM_PIN_FUNCTION(mi2s1_data1), + MSM_PIN_FUNCTION(mi2s1_sck), + MSM_PIN_FUNCTION(mi2s1_ws), + MSM_PIN_FUNCTION(mi2s2_data0), + MSM_PIN_FUNCTION(mi2s2_data1), + MSM_PIN_FUNCTION(mi2s2_sck), + MSM_PIN_FUNCTION(mi2s2_ws), + MSM_PIN_FUNCTION(mss_grfc0), + MSM_PIN_FUNCTION(mss_grfc1), + MSM_PIN_FUNCTION(mss_grfc10), + MSM_PIN_FUNCTION(mss_grfc11), + MSM_PIN_FUNCTION(mss_grfc12), + MSM_PIN_FUNCTION(mss_grfc2), + MSM_PIN_FUNCTION(mss_grfc3), + MSM_PIN_FUNCTION(mss_grfc4), + MSM_PIN_FUNCTION(mss_grfc5), + MSM_PIN_FUNCTION(mss_grfc6), + MSM_PIN_FUNCTION(mss_grfc7), + MSM_PIN_FUNCTION(mss_grfc8), + MSM_PIN_FUNCTION(mss_grfc9), + MSM_PIN_FUNCTION(nav_gpio), + MSM_PIN_FUNCTION(pa_indicator), + MSM_PIN_FUNCTION(pcie0_clkreqn), + MSM_PIN_FUNCTION(pcie1_clkreqn), + MSM_PIN_FUNCTION(phase_flag), + MSM_PIN_FUNCTION(pll_bist), + MSM_PIN_FUNCTION(pll_clk), + MSM_PIN_FUNCTION(pri_mi2s), + MSM_PIN_FUNCTION(prng_rosc), + MSM_PIN_FUNCTION(qdss_cti), + MSM_PIN_FUNCTION(qdss_gpio), + MSM_PIN_FUNCTION(qlink0_enable), + MSM_PIN_FUNCTION(qlink0_request), + MSM_PIN_FUNCTION(qlink0_wmss), + MSM_PIN_FUNCTION(qlink1_enable), + MSM_PIN_FUNCTION(qlink1_request), + MSM_PIN_FUNCTION(qlink1_wmss), + MSM_PIN_FUNCTION(qlink2_enable), + MSM_PIN_FUNCTION(qlink2_request), + MSM_PIN_FUNCTION(qlink2_wmss), + MSM_PIN_FUNCTION(qspi0), + MSM_PIN_FUNCTION(qspi1), + MSM_PIN_FUNCTION(qspi2), + MSM_PIN_FUNCTION(qspi3), + MSM_PIN_FUNCTION(qspi_clk), + MSM_PIN_FUNCTION(qspi_cs), + MSM_PIN_FUNCTION(qup0), + MSM_PIN_FUNCTION(qup1), + MSM_PIN_FUNCTION(qup10), + MSM_PIN_FUNCTION(qup11), + MSM_PIN_FUNCTION(qup12), + MSM_PIN_FUNCTION(qup13), + MSM_PIN_FUNCTION(qup14), + MSM_PIN_FUNCTION(qup15), + MSM_PIN_FUNCTION(qup16), + MSM_PIN_FUNCTION(qup17), + MSM_PIN_FUNCTION(qup18), + MSM_PIN_FUNCTION(qup19), + MSM_PIN_FUNCTION(qup2), + MSM_PIN_FUNCTION(qup3), + MSM_PIN_FUNCTION(qup4), + MSM_PIN_FUNCTION(qup5), + MSM_PIN_FUNCTION(qup6), + MSM_PIN_FUNCTION(qup7), + MSM_PIN_FUNCTION(qup8), + MSM_PIN_FUNCTION(qup9), + MSM_PIN_FUNCTION(qup_l4), + MSM_PIN_FUNCTION(qup_l5), + MSM_PIN_FUNCTION(qup_l6), + MSM_PIN_FUNCTION(sd_write), + MSM_PIN_FUNCTION(sdc40), + MSM_PIN_FUNCTION(sdc41), + MSM_PIN_FUNCTION(sdc42), + MSM_PIN_FUNCTION(sdc43), + MSM_PIN_FUNCTION(sdc4_clk), + MSM_PIN_FUNCTION(sdc4_cmd), + MSM_PIN_FUNCTION(sec_mi2s), + MSM_PIN_FUNCTION(tb_trig), + MSM_PIN_FUNCTION(tgu_ch0), + MSM_PIN_FUNCTION(tgu_ch1), + MSM_PIN_FUNCTION(tgu_ch2), + MSM_PIN_FUNCTION(tgu_ch3), + MSM_PIN_FUNCTION(tsense_pwm1), + MSM_PIN_FUNCTION(tsense_pwm2), + MSM_PIN_FUNCTION(uim0_clk), + MSM_PIN_FUNCTION(uim0_data), + MSM_PIN_FUNCTION(uim0_present), + MSM_PIN_FUNCTION(uim0_reset), + MSM_PIN_FUNCTION(uim1_clk), + MSM_PIN_FUNCTION(uim1_data), + MSM_PIN_FUNCTION(uim1_present), + MSM_PIN_FUNCTION(uim1_reset), + MSM_PIN_FUNCTION(usb2phy_ac), + MSM_PIN_FUNCTION(usb_phy), + MSM_PIN_FUNCTION(vfr_0), + MSM_PIN_FUNCTION(vfr_1), + MSM_PIN_FUNCTION(vsense_trigger), +}; + +/* Every pin is maintained as a single group, and missing or non-existing pin + * would be maintained as dummy group to synchronize pin group index with + * pin descriptor registered with pinctrl core. + * Clients would not be able to request these dummy pin groups. + */ +static const struct msm_pingroup sm8350_groups[] = { + [0] = PINGROUP(0, qup13, _, _, _, _, _, _, _, _), + [1] = PINGROUP(1, qup13, _, _, _, _, _, _, _, _), + [2] = PINGROUP(2, qup13, qup_l4, _, _, _, _, _, _, _), + [3] = PINGROUP(3, qup13, qup_l5, _, _, _, _, _, _, _), + [4] = PINGROUP(4, qup0, _, _, _, _, _, _, _, _), + [5] = PINGROUP(5, qup0, _, _, _, _, _, _, _, _), + [6] = PINGROUP(6, qup0, qup_l4, _, _, _, _, _, _, _), + [7] = PINGROUP(7, qup0, qup_l5, _, _, _, _, _, _, _), + [8] = PINGROUP(8, qup1, _, _, _, _, _, _, _, _), + [9] = PINGROUP(9, qup1, _, _, _, _, _, _, _, _), + [10] = PINGROUP(10, qup1, qup_l6, _, _, _, _, _, _, _), + [11] = PINGROUP(11, qup1, _, _, _, _, _, _, _, _), + [12] = PINGROUP(12, qup2, phase_flag, _, _, _, _, _, _, _), + [13] = PINGROUP(13, qup2, phase_flag, _, _, _, _, _, _, _), + [14] = PINGROUP(14, qup2, qdss_cti, dbg_out, _, _, _, _, _, _), + [15] = PINGROUP(15, qup2, mdp_vsync, _, _, _, _, _, _, _), + [16] = PINGROUP(16, qup3, phase_flag, _, _, _, _, _, _, _), + [17] = PINGROUP(17, qup3, phase_flag, _, _, _, _, _, _, _), + [18] = PINGROUP(18, qup3, _, _, _, _, _, _, _, _), + [19] = PINGROUP(19, qup3, _, _, _, _, _, _, _, _), + [20] = PINGROUP(20, qup4, _, _, _, _, _, _, _, _), + [21] = PINGROUP(21, qup4, _, _, _, _, _, _, _, _), + [22] = PINGROUP(22, qup4, _, _, _, _, _, _, _, _), + [23] = PINGROUP(23, qup4, _, _, _, _, _, _, _, _), + [24] = PINGROUP(24, qup5, _, _, _, _, _, _, _, _), + [25] = PINGROUP(25, qup5, _, _, _, _, _, _, _, _), + [26] = PINGROUP(26, qup5, mdp_vsync, _, _, _, _, _, _, _), + [27] = PINGROUP(27, qup5, qdss_cti, _, _, _, _, _, _, _), + [28] = PINGROUP(28, qup6, phase_flag, _, _, _, _, _, _, _), + [29] = PINGROUP(29, qup6, phase_flag, _, _, _, _, _, _, _), + [30] = PINGROUP(30, qup6, phase_flag, _, _, _, _, _, _, _), + [31] = PINGROUP(31, qup6, phase_flag, _, _, _, _, _, _, _), + [32] = PINGROUP(32, qup7, phase_flag, _, _, _, _, _, _, _), + [33] = PINGROUP(33, qup7, phase_flag, _, _, _, _, _, _, _), + [34] = PINGROUP(34, qup7, phase_flag, _, _, _, _, _, _, _), + [35] = PINGROUP(35, qup7, phase_flag, _, _, _, _, _, _, _), + [36] = PINGROUP(36, qup8, ibi_i3c, ddr_bist, _, _, _, _, _, _), + [37] = PINGROUP(37, qup8, ibi_i3c, ddr_bist, _, _, _, _, _, _), + [38] = PINGROUP(38, qup8, _, _, _, _, _, _, _, _), + [39] = PINGROUP(39, qup8, usb2phy_ac, _, _, _, _, _, _, _), + [40] = PINGROUP(40, qup9, ddr_bist, _, _, _, _, _, _, _), + [41] = PINGROUP(41, qup9, ddr_bist, _, _, _, _, _, _, _), + [42] = PINGROUP(42, qup9, qup_l6, _, _, _, _, _, _, _), + [43] = PINGROUP(43, qup9, ddr_pxi3, _, _, _, _, _, _, _), + [44] = PINGROUP(44, qup10, qspi0, sdc40, ddr_pxi3, _, _, _, _, _), + [45] = PINGROUP(45, qup10, qspi1, sdc41, ddr_pxi2, _, _, _, _, _), + [46] = PINGROUP(46, qup10, _, _, _, _, _, _, _, _), + [47] = PINGROUP(47, qup10, qspi_cs, ddr_pxi2, _, _, _, _, _, _), + [48] = PINGROUP(48, qup11, qspi2, sdc42, ddr_pxi1, _, _, _, _, _), + [49] = PINGROUP(49, qup11, qspi3, sdc43, ddr_pxi1, _, _, _, _, _), + [50] = PINGROUP(50, qup11, qspi_clk, sdc4_clk, _, _, _, _, _, _), + [51] = PINGROUP(51, qup11, qspi_cs, sdc4_cmd, ddr_pxi0, _, _, _, _, _), + [52] = PINGROUP(52, qup12, ddr_pxi0, _, _, _, _, _, _, _), + [53] = PINGROUP(53, qup12, _, _, _, _, _, _, _, _), + [54] = PINGROUP(54, qup12, _, _, _, _, _, _, _, _), + [55] = PINGROUP(55, qup12, atest_usb, _, _, _, _, _, _, _), + [56] = PINGROUP(56, qup14, ibi_i3c, _, _, _, _, _, _, _), + [57] = PINGROUP(57, qup14, ibi_i3c, _, _, _, _, _, _, _), + [58] = PINGROUP(58, qup14, qup_l4, _, _, _, _, _, _, _), + [59] = PINGROUP(59, qup14, qup_l5, _, _, _, _, _, _, _), + [60] = PINGROUP(60, qup15, ibi_i3c, _, _, _, _, _, _, _), + [61] = PINGROUP(61, qup15, ibi_i3c, _, _, _, _, _, _, _), + [62] = PINGROUP(62, qup15, qup_l6, _, _, _, _, _, _, _), + [63] = PINGROUP(63, qup15, qup_l4, _, _, _, _, _, _, _), + [64] = PINGROUP(64, qup16, tb_trig, _, _, _, _, _, _, _), + [65] = PINGROUP(65, qup16, _, _, _, _, _, _, _, _), + [66] = PINGROUP(66, qup16, qup_l5, _, _, _, _, _, _, _), + [67] = PINGROUP(67, qup16, qup_l6, _, _, _, _, _, _, _), + [68] = PINGROUP(68, qup18, _, _, _, _, _, _, _, _), + [69] = PINGROUP(69, qup18, _, _, _, _, _, _, _, _), + [70] = PINGROUP(70, qup18, _, _, _, _, _, _, _, _), + [71] = PINGROUP(71, qup18, _, _, _, _, _, _, _, _), + [72] = PINGROUP(72, qup17, phase_flag, _, _, _, _, _, _, _), + [73] = PINGROUP(73, qup17, phase_flag, _, _, _, _, _, _, _), + [74] = PINGROUP(74, qup17, phase_flag, _, _, _, _, _, _, _), + [75] = PINGROUP(75, qup17, phase_flag, _, _, _, _, _, _, _), + [76] = PINGROUP(76, qup19, phase_flag, _, _, _, _, _, _, _), + [77] = PINGROUP(77, qup19, phase_flag, _, _, _, _, _, _, _), + [78] = PINGROUP(78, qup19, phase_flag, _, vsense_trigger, _, _, _, _, _), + [79] = PINGROUP(79, qup19, phase_flag, _, _, _, _, _, _, _), + [80] = PINGROUP(80, usb2phy_ac, jitter_bist, atest_usb, _, _, _, _, _, _), + [81] = PINGROUP(81, usb_phy, pll_bist, pll_clk, atest_usb, _, _, _, _, _), + [82] = PINGROUP(82, mdp_vsync, _, _, _, _, _, _, _, _), + [83] = PINGROUP(83, mdp_vsync, dp_lcd, _, _, _, _, _, _, _), + [84] = PINGROUP(84, mdp_vsync, vfr_0, _, _, _, _, _, _, _), + [85] = PINGROUP(85, atest_char, _, _, _, _, _, _, _, _), + [86] = PINGROUP(86, mdp_vsync0, mdp_vsync1, atest_char, _, _, _, _, _, _), + [87] = PINGROUP(87, dp_hot, mdp_vsync2, mdp_vsync3, qdss_cti, atest_char, _, _, _, _), + [88] = PINGROUP(88, qdss_cti, tsense_pwm1, tsense_pwm2, _, _, _, _, _, _), + [89] = PINGROUP(89, qdss_cti, _, _, _, _, _, _, _, _), + [90] = PINGROUP(90, vfr_1, qdss_cti, _, _, _, _, _, _, _), + [91] = PINGROUP(91, qdss_cti, _, _, _, _, _, _, _, _), + [92] = PINGROUP(92, qdss_cti, _, _, _, _, _, _, _, _), + [93] = PINGROUP(93, sd_write, _, _, _, _, _, _, _, _), + [94] = PINGROUP(94, _, _, _, _, _, _, _, _, _), + [95] = PINGROUP(95, pcie0_clkreqn, _, _, _, _, _, _, _, _), + [96] = PINGROUP(96, _, _, _, _, _, _, _, _, _), + [97] = PINGROUP(97, _, _, _, _, _, _, _, _, _), + [98] = PINGROUP(98, pcie1_clkreqn, _, _, _, _, _, _, _, _), + [99] = PINGROUP(99, tgu_ch0, _, _, _, _, _, _, _, _), + [100] = PINGROUP(100, cam_mclk, tgu_ch1, qdss_gpio, _, _, _, _, _, _), + [101] = PINGROUP(101, cam_mclk, tgu_ch2, qdss_gpio, _, _, _, _, _, _), + [102] = PINGROUP(102, cam_mclk, tgu_ch3, qdss_gpio, _, _, _, _, _, _), + [103] = PINGROUP(103, cam_mclk, phase_flag, _, qdss_gpio, _, _, _, _, _), + [104] = PINGROUP(104, cam_mclk, phase_flag, _, qdss_gpio, _, _, _, _, _), + [105] = PINGROUP(105, cam_mclk, phase_flag, _, qdss_gpio, _, _, _, _, _), + [106] = PINGROUP(106, cci_async, phase_flag, _, qdss_gpio, _, _, _, _, _), + [107] = PINGROUP(107, cci_i2c, phase_flag, _, qdss_gpio, _, _, _, _, _), + [108] = PINGROUP(108, cci_i2c, phase_flag, _, qdss_gpio, _, _, _, _, _), + [109] = PINGROUP(109, cci_i2c, phase_flag, _, qdss_gpio, _, _, _, _, _), + [110] = PINGROUP(110, cci_i2c, phase_flag, _, qdss_gpio, _, _, _, _, _), + [111] = PINGROUP(111, cci_i2c, phase_flag, _, qdss_gpio, _, _, _, _, _), + [112] = PINGROUP(112, cci_i2c, phase_flag, _, qdss_gpio, _, _, _, _, _), + [113] = PINGROUP(113, cci_i2c, phase_flag, _, qdss_gpio, _, _, _, _, _), + [114] = PINGROUP(114, cci_i2c, phase_flag, _, qdss_gpio, _, _, _, _, _), + [115] = PINGROUP(115, cci_timer, gcc_gp1, qdss_gpio, atest_char, _, _, _, _, _), + [116] = PINGROUP(116, cci_timer, gcc_gp2, qdss_gpio, _, _, _, _, _, _), + [117] = PINGROUP(117, cci_timer, gcc_gp3, qdss_gpio, atest_char, _, _, _, _, _), + [118] = PINGROUP(118, cci_timer, cci_async, _, _, _, _, _, _, _), + [119] = PINGROUP(119, cci_timer, cci_async, _, _, _, _, _, _, _), + [120] = PINGROUP(120, mi2s2_sck, _, _, _, _, _, _, _, _), + [121] = PINGROUP(121, mi2s2_data0, _, _, _, _, _, _, _, _), + [122] = PINGROUP(122, mi2s2_ws, _, _, _, _, _, _, _, _), + [123] = PINGROUP(123, pri_mi2s, _, _, _, _, _, _, _, _), + [124] = PINGROUP(124, sec_mi2s, audio_ref, mi2s2_data1, _, _, _, _, _, _), + [125] = PINGROUP(125, mi2s0_sck, _, _, _, _, _, _, _, _), + [126] = PINGROUP(126, mi2s0_data0, _, _, _, _, _, _, _, _), + [127] = PINGROUP(127, mi2s0_data1, _, _, _, _, _, _, _, _), + [128] = PINGROUP(128, mi2s0_ws, _, _, _, _, _, _, _, _), + [129] = PINGROUP(129, lpass_slimbus, mi2s1_sck, gcc_gp1, _, _, _, _, _, _), + [130] = PINGROUP(130, lpass_slimbus, mi2s1_data0, gcc_gp2, _, _, _, _, _, _), + [131] = PINGROUP(131, mi2s1_data1, gcc_gp3, _, _, _, _, _, _, _), + [132] = PINGROUP(132, mi2s1_ws, _, _, _, _, _, _, _, _), + [133] = PINGROUP(133, uim1_data, _, _, _, _, _, _, _, _), + [134] = PINGROUP(134, uim1_clk, _, _, _, _, _, _, _, _), + [135] = PINGROUP(135, uim1_reset, _, _, _, _, _, _, _, _), + [136] = PINGROUP(136, uim1_present, tb_trig, _, _, _, _, _, _, _), + [137] = PINGROUP(137, uim0_data, _, _, _, _, _, _, _, _), + [138] = PINGROUP(138, uim0_clk, _, _, _, _, _, _, _, _), + [139] = PINGROUP(139, uim0_reset, _, _, _, _, _, _, _, _), + [140] = PINGROUP(140, uim0_present, _, _, _, _, _, _, _, _), + [141] = PINGROUP(141, _, mss_grfc0, _, _, _, _, _, _, _), + [142] = PINGROUP(142, _, mss_grfc1, _, _, _, _, _, _, _), + [143] = PINGROUP(143, _, mss_grfc2, _, _, _, _, _, _, _), + [144] = PINGROUP(144, _, mss_grfc3, _, _, _, _, _, _, _), + [145] = PINGROUP(145, _, mss_grfc4, _, _, _, _, _, _, _), + [146] = PINGROUP(146, _, mss_grfc5, _, _, _, _, _, _, _), + [147] = PINGROUP(147, _, mss_grfc6, _, _, _, _, _, _, _), + [148] = PINGROUP(148, _, mss_grfc7, _, _, _, _, _, _, _), + [149] = PINGROUP(149, _, mss_grfc8, _, _, _, _, _, _, _), + [150] = PINGROUP(150, _, mss_grfc9, _, _, _, _, _, _, _), + [151] = PINGROUP(151, coex_uart1, atest_usb, _, _, _, _, _, _, _), + [152] = PINGROUP(152, coex_uart1, atest_usb, _, _, _, _, _, _, _), + [153] = PINGROUP(153, coex_uart2, mss_grfc10, atest_usb, _, _, _, _, _, _), + [154] = PINGROUP(154, coex_uart2, mss_grfc11, atest_usb, _, _, _, _, _, _), + [155] = PINGROUP(155, nav_gpio, _, _, _, _, _, _, _, _), + [156] = PINGROUP(156, nav_gpio, _, _, _, _, _, _, _, _), + [157] = PINGROUP(157, mss_grfc12, pa_indicator, nav_gpio, _, _, _, _, _, _), + [158] = PINGROUP(158, mss_grfc0, atest_usb, _, _, _, _, _, _, _), + [159] = PINGROUP(159, qlink0_request, atest_usb, _, _, _, _, _, _, _), + [160] = PINGROUP(160, qlink0_enable, _, _, _, _, _, _, _, _), + [161] = PINGROUP(161, qlink0_wmss, atest_usb, _, _, _, _, _, _, _), + [162] = PINGROUP(162, qlink1_request, _, _, _, _, _, _, _, _), + [163] = PINGROUP(163, qlink1_enable, _, _, _, _, _, _, _, _), + [164] = PINGROUP(164, qlink1_wmss, _, _, _, _, _, _, _, _), + [165] = PINGROUP(165, qlink2_request, _, _, _, _, _, _, _, _), + [166] = PINGROUP(166, qlink2_enable, _, _, _, _, _, _, _, _), + [167] = PINGROUP(167, qlink2_wmss, _, _, _, _, _, _, _, _), + [168] = PINGROUP(168, _, _, _, _, _, _, _, _, _), + [169] = PINGROUP(169, _, _, _, _, _, _, _, _, _), + [170] = PINGROUP(170, _, _, _, _, _, _, _, _, _), + [171] = PINGROUP(171, _, _, _, _, _, _, _, _, _), + [172] = PINGROUP(172, _, _, _, _, _, _, _, _, _), + [173] = PINGROUP(173, _, _, _, _, _, _, _, _, _), + [174] = PINGROUP(174, cmu_rng, _, _, _, _, _, _, _, _), + [175] = PINGROUP(175, cmu_rng, _, _, _, _, _, _, _, _), + [176] = PINGROUP(176, cmu_rng, _, _, _, _, _, _, _, _), + [177] = PINGROUP(177, cmu_rng, _, _, _, _, _, _, _, _), + [178] = PINGROUP(178, _, _, _, _, _, _, _, _, _), + [179] = PINGROUP(179, _, _, _, _, _, _, _, _, _), + [180] = PINGROUP(180, _, _, _, _, _, _, _, _, _), + [181] = PINGROUP(181, _, _, _, _, _, _, _, _, _), + [182] = PINGROUP(182, _, _, _, _, _, _, _, _, _), + [183] = PINGROUP(183, cri_trng0, qdss_gpio, _, _, _, _, _, _, _), + [184] = PINGROUP(184, cri_trng1, qdss_gpio, _, _, _, _, _, _, _), + [185] = PINGROUP(185, prng_rosc, qdss_gpio, _, _, _, _, _, _, _), + [186] = PINGROUP(186, cri_trng, qdss_gpio, _, _, _, _, _, _, _), + [187] = PINGROUP(187, qdss_gpio, _, _, _, _, _, _, _, _), + [188] = PINGROUP(188, qdss_gpio, _, _, _, _, _, _, _, _), + [189] = PINGROUP(189, qdss_gpio, _, _, _, _, _, _, _, _), + [190] = PINGROUP(190, qdss_gpio, _, _, _, _, _, _, _, _), + [191] = PINGROUP(191, qdss_gpio, _, _, _, _, _, _, _, _), + [192] = PINGROUP(192, qdss_gpio, _, _, _, _, _, _, _, _), + [193] = PINGROUP(193, qdss_gpio, _, _, _, _, _, _, _, _), + [194] = PINGROUP(194, qdss_gpio, _, _, _, _, _, _, _, _), + [195] = PINGROUP(195, qdss_gpio, _, _, _, _, _, _, _, _), + [196] = PINGROUP(196, qdss_gpio, _, _, _, _, _, _, _, _), + [197] = PINGROUP(197, qdss_gpio, _, _, _, _, _, _, _, _), + [198] = PINGROUP(198, qdss_gpio, _, _, _, _, _, _, _, _), + [199] = PINGROUP(199, qdss_gpio, _, _, _, _, _, _, _, _), + [200] = PINGROUP(200, qdss_gpio, _, _, _, _, _, _, _, _), + [201] = PINGROUP(201, _, _, _, _, _, _, _, _, _), + [202] = PINGROUP(202, _, _, _, _, _, _, _, _, _), + [203] = UFS_RESET(ufs_reset, 0xd8000), + [204] = SDC_PINGROUP(sdc2_clk, 0xcf000, 14, 6), + [205] = SDC_PINGROUP(sdc2_cmd, 0xcf000, 11, 3), + [206] = SDC_PINGROUP(sdc2_data, 0xcf000, 9, 0), +}; + +static const struct msm_gpio_wakeirq_map sm8350_pdc_map[] = { + { 2, 117 }, { 7, 82 }, { 11, 83 }, { 14, 80 }, { 15, 146 }, + { 19, 121 }, { 23, 84 }, { 26, 86 }, { 27, 75 }, { 31, 85 }, + { 32, 97 }, { 34, 98 }, { 35, 131 }, { 36, 79 }, { 38, 99 }, + { 39, 92 }, { 40, 101 }, { 43, 137 }, { 44, 102 }, { 46, 96 }, + { 47, 93 }, { 50, 108 }, { 51, 127 }, { 55, 128 }, { 56, 81 }, + { 59, 112 }, { 60, 119 }, { 63, 73 }, { 67, 74 }, { 71, 134 }, + { 75, 103 }, { 79, 104 }, { 80, 126 }, { 81, 139 }, { 82, 140 }, + { 83, 141 }, { 84, 124 }, { 85, 109 }, { 86, 143 }, { 87, 138 }, + { 88, 122 }, { 89, 113 }, { 90, 114 }, { 91, 115 }, { 92, 76 }, + { 95, 147 }, { 96, 148 }, { 98, 149 }, { 99, 150 }, { 115, 125 }, + { 116, 106 }, { 117, 105 }, { 118, 116 }, { 119, 123 }, { 130, 145 }, + { 136, 72 }, { 140, 100 }, { 151, 110 }, { 153, 95 }, { 155, 107 }, + { 156, 94 }, { 157, 111 }, { 159, 118 }, { 162, 77 }, { 165, 78 }, + { 169, 70 }, { 172, 132 }, { 174, 87 }, { 175, 88 }, { 177, 89 }, + { 179, 120 }, { 180, 129 }, { 183, 90 }, { 185, 136 }, { 187, 142 }, + { 190, 144 }, { 198, 91 }, { 200, 133 }, { 202, 135 }, +}; + +static const struct msm_pinctrl_soc_data sm8350_tlmm = { + .pins = sm8350_pins, + .npins = ARRAY_SIZE(sm8350_pins), + .functions = sm8350_functions, + .nfunctions = ARRAY_SIZE(sm8350_functions), + .groups = sm8350_groups, + .ngroups = ARRAY_SIZE(sm8350_groups), + .ngpios = 204, + .wakeirq_map = sm8350_pdc_map, + .nwakeirq_map = ARRAY_SIZE(sm8350_pdc_map), +}; + +static int sm8350_tlmm_probe(struct platform_device *pdev) +{ + return msm_pinctrl_probe(pdev, &sm8350_tlmm); +} + +static const struct of_device_id sm8350_tlmm_of_match[] = { + { .compatible = "qcom,sm8350-tlmm", }, + { }, +}; + +static struct platform_driver sm8350_tlmm_driver = { + .driver = { + .name = "sm8350-tlmm", + .of_match_table = sm8350_tlmm_of_match, + }, + .probe = sm8350_tlmm_probe, + .remove = msm_pinctrl_remove, +}; + +static int __init sm8350_tlmm_init(void) +{ + return platform_driver_register(&sm8350_tlmm_driver); +} +arch_initcall(sm8350_tlmm_init); + +static void __exit sm8350_tlmm_exit(void) +{ + platform_driver_unregister(&sm8350_tlmm_driver); +} +module_exit(sm8350_tlmm_exit); + +MODULE_DESCRIPTION("QTI SM8350 TLMM driver"); +MODULE_LICENSE("GPL v2"); +MODULE_DEVICE_TABLE(of, sm8350_tlmm_of_match); diff --git a/drivers/pinctrl/qcom/pinctrl-sm8450-lpass-lpi.c b/drivers/pinctrl/qcom/pinctrl-sm8450-lpass-lpi.c new file mode 100644 index 0000000000..e22d03ce29 --- /dev/null +++ b/drivers/pinctrl/qcom/pinctrl-sm8450-lpass-lpi.c @@ -0,0 +1,240 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2022 Linaro Ltd. + */ + +#include <linux/gpio/driver.h> +#include <linux/module.h> +#include <linux/platform_device.h> + +#include "pinctrl-lpass-lpi.h" + +enum lpass_lpi_functions { + LPI_MUX_dmic1_clk, + LPI_MUX_dmic1_data, + LPI_MUX_dmic2_clk, + LPI_MUX_dmic2_data, + LPI_MUX_dmic3_clk, + LPI_MUX_dmic3_data, + LPI_MUX_dmic4_clk, + LPI_MUX_dmic4_data, + LPI_MUX_i2s1_clk, + LPI_MUX_i2s1_data, + LPI_MUX_i2s1_ws, + LPI_MUX_i2s2_clk, + LPI_MUX_i2s2_data, + LPI_MUX_i2s2_ws, + LPI_MUX_i2s3_clk, + LPI_MUX_i2s3_data, + LPI_MUX_i2s3_ws, + LPI_MUX_i2s4_clk, + LPI_MUX_i2s4_data, + LPI_MUX_i2s4_ws, + LPI_MUX_qua_mi2s_data, + LPI_MUX_qua_mi2s_sclk, + LPI_MUX_qua_mi2s_ws, + LPI_MUX_swr_rx_clk, + LPI_MUX_swr_rx_data, + LPI_MUX_swr_tx_clk, + LPI_MUX_swr_tx_data, + LPI_MUX_wsa_swr_clk, + LPI_MUX_wsa_swr_data, + LPI_MUX_wsa2_swr_clk, + LPI_MUX_wsa2_swr_data, + LPI_MUX_slimbus_clk, + LPI_MUX_slimbus_data, + LPI_MUX_ext_mclk1_a, + LPI_MUX_ext_mclk1_b, + LPI_MUX_ext_mclk1_c, + LPI_MUX_ext_mclk1_d, + LPI_MUX_ext_mclk1_e, + LPI_MUX_gpio, + LPI_MUX__, +}; + +static int gpio0_pins[] = { 0 }; +static int gpio1_pins[] = { 1 }; +static int gpio2_pins[] = { 2 }; +static int gpio3_pins[] = { 3 }; +static int gpio4_pins[] = { 4 }; +static int gpio5_pins[] = { 5 }; +static int gpio6_pins[] = { 6 }; +static int gpio7_pins[] = { 7 }; +static int gpio8_pins[] = { 8 }; +static int gpio9_pins[] = { 9 }; +static int gpio10_pins[] = { 10 }; +static int gpio11_pins[] = { 11 }; +static int gpio12_pins[] = { 12 }; +static int gpio13_pins[] = { 13 }; +static int gpio14_pins[] = { 14 }; +static int gpio15_pins[] = { 15 }; +static int gpio16_pins[] = { 16 }; +static int gpio17_pins[] = { 17 }; +static int gpio18_pins[] = { 18 }; +static int gpio19_pins[] = { 19 }; +static int gpio20_pins[] = { 20 }; +static int gpio21_pins[] = { 21 }; +static int gpio22_pins[] = { 22 }; + +static const struct pinctrl_pin_desc sm8450_lpi_pins[] = { + PINCTRL_PIN(0, "gpio0"), + PINCTRL_PIN(1, "gpio1"), + PINCTRL_PIN(2, "gpio2"), + PINCTRL_PIN(3, "gpio3"), + PINCTRL_PIN(4, "gpio4"), + PINCTRL_PIN(5, "gpio5"), + PINCTRL_PIN(6, "gpio6"), + PINCTRL_PIN(7, "gpio7"), + PINCTRL_PIN(8, "gpio8"), + PINCTRL_PIN(9, "gpio9"), + PINCTRL_PIN(10, "gpio10"), + PINCTRL_PIN(11, "gpio11"), + PINCTRL_PIN(12, "gpio12"), + PINCTRL_PIN(13, "gpio13"), + PINCTRL_PIN(14, "gpio14"), + PINCTRL_PIN(15, "gpio15"), + PINCTRL_PIN(16, "gpio16"), + PINCTRL_PIN(17, "gpio17"), + PINCTRL_PIN(18, "gpio18"), + PINCTRL_PIN(19, "gpio19"), + PINCTRL_PIN(20, "gpio20"), + PINCTRL_PIN(21, "gpio21"), + PINCTRL_PIN(22, "gpio22"), +}; + +static const char * const swr_tx_clk_groups[] = { "gpio0" }; +static const char * const swr_tx_data_groups[] = { "gpio1", "gpio2", "gpio14" }; +static const char * const swr_rx_clk_groups[] = { "gpio3" }; +static const char * const swr_rx_data_groups[] = { "gpio4", "gpio5" }; +static const char * const dmic1_clk_groups[] = { "gpio6" }; +static const char * const dmic1_data_groups[] = { "gpio7" }; +static const char * const dmic2_clk_groups[] = { "gpio8" }; +static const char * const dmic2_data_groups[] = { "gpio9" }; +static const char * const dmic4_clk_groups[] = { "gpio17" }; +static const char * const dmic4_data_groups[] = { "gpio18" }; +static const char * const i2s2_clk_groups[] = { "gpio10" }; +static const char * const i2s2_ws_groups[] = { "gpio11" }; +static const char * const dmic3_clk_groups[] = { "gpio12" }; +static const char * const dmic3_data_groups[] = { "gpio13" }; +static const char * const qua_mi2s_sclk_groups[] = { "gpio0" }; +static const char * const qua_mi2s_ws_groups[] = { "gpio1" }; +static const char * const qua_mi2s_data_groups[] = { "gpio2", "gpio3", "gpio4", "gpio5" }; +static const char * const i2s1_clk_groups[] = { "gpio6" }; +static const char * const i2s1_ws_groups[] = { "gpio7" }; +static const char * const i2s1_data_groups[] = { "gpio8", "gpio9" }; +static const char * const wsa_swr_clk_groups[] = { "gpio10" }; +static const char * const wsa_swr_data_groups[] = { "gpio11" }; +static const char * const wsa2_swr_clk_groups[] = { "gpio15" }; +static const char * const wsa2_swr_data_groups[] = { "gpio16" }; +static const char * const i2s2_data_groups[] = { "gpio15", "gpio16" }; +static const char * const i2s4_ws_groups[] = { "gpio13" }; +static const char * const i2s4_clk_groups[] = { "gpio12" }; +static const char * const i2s4_data_groups[] = { "gpio17", "gpio18" }; +static const char * const slimbus_clk_groups[] = { "gpio19"}; +static const char * const i2s3_clk_groups[] = { "gpio19"}; +static const char * const i2s3_ws_groups[] = { "gpio20"}; +static const char * const i2s3_data_groups[] = { "gpio21", "gpio22"}; +static const char * const slimbus_data_groups[] = { "gpio20"}; +static const char * const ext_mclk1_c_groups[] = { "gpio5" }; +static const char * const ext_mclk1_b_groups[] = { "gpio9" }; +static const char * const ext_mclk1_a_groups[] = { "gpio13" }; +static const char * const ext_mclk1_d_groups[] = { "gpio14" }; +static const char * const ext_mclk1_e_groups[] = { "gpio22" }; + +static const struct lpi_pingroup sm8450_groups[] = { + LPI_PINGROUP(0, 0, swr_tx_clk, qua_mi2s_sclk, _, _), + LPI_PINGROUP(1, 2, swr_tx_data, qua_mi2s_ws, _, _), + LPI_PINGROUP(2, 4, swr_tx_data, qua_mi2s_data, _, _), + LPI_PINGROUP(3, 8, swr_rx_clk, qua_mi2s_data, _, _), + LPI_PINGROUP(4, 10, swr_rx_data, qua_mi2s_data, _, _), + LPI_PINGROUP(5, 12, swr_rx_data, ext_mclk1_c, qua_mi2s_data, _), + LPI_PINGROUP(6, LPI_NO_SLEW, dmic1_clk, i2s1_clk, _, _), + LPI_PINGROUP(7, LPI_NO_SLEW, dmic1_data, i2s1_ws, _, _), + LPI_PINGROUP(8, LPI_NO_SLEW, dmic2_clk, i2s1_data, _, _), + LPI_PINGROUP(9, LPI_NO_SLEW, dmic2_data, i2s1_data, ext_mclk1_b, _), + LPI_PINGROUP(10, 16, i2s2_clk, wsa_swr_clk, _, _), + LPI_PINGROUP(11, 18, i2s2_ws, wsa_swr_data, _, _), + LPI_PINGROUP(12, LPI_NO_SLEW, dmic3_clk, i2s4_clk, _, _), + LPI_PINGROUP(13, LPI_NO_SLEW, dmic3_data, i2s4_ws, ext_mclk1_a, _), + LPI_PINGROUP(14, 6, swr_tx_data, ext_mclk1_d, _, _), + LPI_PINGROUP(15, 20, i2s2_data, wsa2_swr_clk, _, _), + LPI_PINGROUP(16, 22, i2s2_data, wsa2_swr_data, _, _), + LPI_PINGROUP(17, LPI_NO_SLEW, dmic4_clk, i2s4_data, _, _), + LPI_PINGROUP(18, LPI_NO_SLEW, dmic4_data, i2s4_data, _, _), + LPI_PINGROUP(19, LPI_NO_SLEW, i2s3_clk, slimbus_clk, _, _), + LPI_PINGROUP(20, LPI_NO_SLEW, i2s3_ws, slimbus_data, _, _), + LPI_PINGROUP(21, LPI_NO_SLEW, i2s3_data, _, _, _), + LPI_PINGROUP(22, LPI_NO_SLEW, i2s3_data, ext_mclk1_e, _, _), +}; + +static const struct lpi_function sm8450_functions[] = { + LPI_FUNCTION(dmic1_clk), + LPI_FUNCTION(dmic1_data), + LPI_FUNCTION(dmic2_clk), + LPI_FUNCTION(dmic2_data), + LPI_FUNCTION(dmic3_clk), + LPI_FUNCTION(dmic3_data), + LPI_FUNCTION(dmic4_clk), + LPI_FUNCTION(dmic4_data), + LPI_FUNCTION(i2s1_clk), + LPI_FUNCTION(i2s1_data), + LPI_FUNCTION(i2s1_ws), + LPI_FUNCTION(i2s2_clk), + LPI_FUNCTION(i2s2_data), + LPI_FUNCTION(i2s2_ws), + LPI_FUNCTION(i2s3_clk), + LPI_FUNCTION(i2s3_data), + LPI_FUNCTION(i2s3_ws), + LPI_FUNCTION(i2s4_clk), + LPI_FUNCTION(i2s4_data), + LPI_FUNCTION(i2s4_ws), + LPI_FUNCTION(qua_mi2s_data), + LPI_FUNCTION(qua_mi2s_sclk), + LPI_FUNCTION(qua_mi2s_ws), + LPI_FUNCTION(swr_rx_clk), + LPI_FUNCTION(swr_rx_data), + LPI_FUNCTION(swr_tx_clk), + LPI_FUNCTION(swr_tx_data), + LPI_FUNCTION(slimbus_clk), + LPI_FUNCTION(slimbus_data), + LPI_FUNCTION(wsa_swr_clk), + LPI_FUNCTION(wsa_swr_data), + LPI_FUNCTION(wsa2_swr_clk), + LPI_FUNCTION(wsa2_swr_data), + LPI_FUNCTION(ext_mclk1_a), + LPI_FUNCTION(ext_mclk1_b), + LPI_FUNCTION(ext_mclk1_c), + LPI_FUNCTION(ext_mclk1_d), + LPI_FUNCTION(ext_mclk1_e), +}; + +static const struct lpi_pinctrl_variant_data sm8450_lpi_data = { + .pins = sm8450_lpi_pins, + .npins = ARRAY_SIZE(sm8450_lpi_pins), + .groups = sm8450_groups, + .ngroups = ARRAY_SIZE(sm8450_groups), + .functions = sm8450_functions, + .nfunctions = ARRAY_SIZE(sm8450_functions), +}; + +static const struct of_device_id lpi_pinctrl_of_match[] = { + { + .compatible = "qcom,sm8450-lpass-lpi-pinctrl", + .data = &sm8450_lpi_data, + }, + { } +}; +MODULE_DEVICE_TABLE(of, lpi_pinctrl_of_match); + +static struct platform_driver lpi_pinctrl_driver = { + .driver = { + .name = "qcom-sm8450-lpass-lpi-pinctrl", + .of_match_table = lpi_pinctrl_of_match, + }, + .probe = lpi_pinctrl_probe, + .remove = lpi_pinctrl_remove, +}; + +module_platform_driver(lpi_pinctrl_driver); +MODULE_DESCRIPTION("QTI SM8450 LPI GPIO pin control driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/pinctrl/qcom/pinctrl-sm8450.c b/drivers/pinctrl/qcom/pinctrl-sm8450.c new file mode 100644 index 0000000000..d11bb1ee9e --- /dev/null +++ b/drivers/pinctrl/qcom/pinctrl-sm8450.c @@ -0,0 +1,1697 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved. + * Copyright (c) 2021, Linaro Limited + */ + +#include <linux/module.h> +#include <linux/of.h> +#include <linux/platform_device.h> + +#include "pinctrl-msm.h" + +#define REG_SIZE 0x1000 + +#define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7, f8, f9) \ + { \ + .grp = PINCTRL_PINGROUP("gpio" #id, \ + gpio##id##_pins, \ + ARRAY_SIZE(gpio##id##_pins)), \ + .funcs = (int[]){ \ + msm_mux_gpio, /* gpio mode */ \ + msm_mux_##f1, \ + msm_mux_##f2, \ + msm_mux_##f3, \ + msm_mux_##f4, \ + msm_mux_##f5, \ + msm_mux_##f6, \ + msm_mux_##f7, \ + msm_mux_##f8, \ + msm_mux_##f9 \ + }, \ + .nfuncs = 10, \ + .ctl_reg = REG_SIZE * id, \ + .io_reg = 0x4 + REG_SIZE * id, \ + .intr_cfg_reg = 0x8 + REG_SIZE * id, \ + .intr_status_reg = 0xc + REG_SIZE * id, \ + .intr_target_reg = 0x8 + REG_SIZE * id, \ + .mux_bit = 2, \ + .pull_bit = 0, \ + .drv_bit = 6, \ + .egpio_enable = 12, \ + .egpio_present = 11, \ + .oe_bit = 9, \ + .in_bit = 0, \ + .out_bit = 1, \ + .intr_enable_bit = 0, \ + .intr_status_bit = 0, \ + .intr_target_bit = 5, \ + .intr_target_kpss_val = 3, \ + .intr_raw_status_bit = 4, \ + .intr_polarity_bit = 1, \ + .intr_detection_bit = 2, \ + .intr_detection_width = 2, \ + } + +#define SDC_QDSD_PINGROUP(pg_name, ctl, pull, drv) \ + { \ + .grp = PINCTRL_PINGROUP(#pg_name, \ + pg_name##_pins, \ + ARRAY_SIZE(pg_name##_pins)), \ + .ctl_reg = ctl, \ + .io_reg = 0, \ + .intr_cfg_reg = 0, \ + .intr_status_reg = 0, \ + .intr_target_reg = 0, \ + .mux_bit = -1, \ + .pull_bit = pull, \ + .drv_bit = drv, \ + .oe_bit = -1, \ + .in_bit = -1, \ + .out_bit = -1, \ + .intr_enable_bit = -1, \ + .intr_status_bit = -1, \ + .intr_target_bit = -1, \ + .intr_raw_status_bit = -1, \ + .intr_polarity_bit = -1, \ + .intr_detection_bit = -1, \ + .intr_detection_width = -1, \ + } + +#define UFS_RESET(pg_name, offset) \ + { \ + .grp = PINCTRL_PINGROUP(#pg_name, \ + pg_name##_pins, \ + ARRAY_SIZE(pg_name##_pins)), \ + .ctl_reg = offset, \ + .io_reg = offset + 0x4, \ + .intr_cfg_reg = 0, \ + .intr_status_reg = 0, \ + .intr_target_reg = 0, \ + .mux_bit = -1, \ + .pull_bit = 3, \ + .drv_bit = 0, \ + .oe_bit = -1, \ + .in_bit = -1, \ + .out_bit = 0, \ + .intr_enable_bit = -1, \ + .intr_status_bit = -1, \ + .intr_target_bit = -1, \ + .intr_raw_status_bit = -1, \ + .intr_polarity_bit = -1, \ + .intr_detection_bit = -1, \ + .intr_detection_width = -1, \ + } + +static const struct pinctrl_pin_desc sm8450_pins[] = { + PINCTRL_PIN(0, "GPIO_0"), + PINCTRL_PIN(1, "GPIO_1"), + PINCTRL_PIN(2, "GPIO_2"), + PINCTRL_PIN(3, "GPIO_3"), + PINCTRL_PIN(4, "GPIO_4"), + PINCTRL_PIN(5, "GPIO_5"), + PINCTRL_PIN(6, "GPIO_6"), + PINCTRL_PIN(7, "GPIO_7"), + PINCTRL_PIN(8, "GPIO_8"), + PINCTRL_PIN(9, "GPIO_9"), + PINCTRL_PIN(10, "GPIO_10"), + PINCTRL_PIN(11, "GPIO_11"), + PINCTRL_PIN(12, "GPIO_12"), + PINCTRL_PIN(13, "GPIO_13"), + PINCTRL_PIN(14, "GPIO_14"), + PINCTRL_PIN(15, "GPIO_15"), + PINCTRL_PIN(16, "GPIO_16"), + PINCTRL_PIN(17, "GPIO_17"), + PINCTRL_PIN(18, "GPIO_18"), + PINCTRL_PIN(19, "GPIO_19"), + PINCTRL_PIN(20, "GPIO_20"), + PINCTRL_PIN(21, "GPIO_21"), + PINCTRL_PIN(22, "GPIO_22"), + PINCTRL_PIN(23, "GPIO_23"), + PINCTRL_PIN(24, "GPIO_24"), + PINCTRL_PIN(25, "GPIO_25"), + PINCTRL_PIN(26, "GPIO_26"), + PINCTRL_PIN(27, "GPIO_27"), + PINCTRL_PIN(28, "GPIO_28"), + PINCTRL_PIN(29, "GPIO_29"), + PINCTRL_PIN(30, "GPIO_30"), + PINCTRL_PIN(31, "GPIO_31"), + PINCTRL_PIN(32, "GPIO_32"), + PINCTRL_PIN(33, "GPIO_33"), + PINCTRL_PIN(34, "GPIO_34"), + PINCTRL_PIN(35, "GPIO_35"), + PINCTRL_PIN(36, "GPIO_36"), + PINCTRL_PIN(37, "GPIO_37"), + PINCTRL_PIN(38, "GPIO_38"), + PINCTRL_PIN(39, "GPIO_39"), + PINCTRL_PIN(40, "GPIO_40"), + PINCTRL_PIN(41, "GPIO_41"), + PINCTRL_PIN(42, "GPIO_42"), + PINCTRL_PIN(43, "GPIO_43"), + PINCTRL_PIN(44, "GPIO_44"), + PINCTRL_PIN(45, "GPIO_45"), + PINCTRL_PIN(46, "GPIO_46"), + PINCTRL_PIN(47, "GPIO_47"), + PINCTRL_PIN(48, "GPIO_48"), + PINCTRL_PIN(49, "GPIO_49"), + PINCTRL_PIN(50, "GPIO_50"), + PINCTRL_PIN(51, "GPIO_51"), + PINCTRL_PIN(52, "GPIO_52"), + PINCTRL_PIN(53, "GPIO_53"), + PINCTRL_PIN(54, "GPIO_54"), + PINCTRL_PIN(55, "GPIO_55"), + PINCTRL_PIN(56, "GPIO_56"), + PINCTRL_PIN(57, "GPIO_57"), + PINCTRL_PIN(58, "GPIO_58"), + PINCTRL_PIN(59, "GPIO_59"), + PINCTRL_PIN(60, "GPIO_60"), + PINCTRL_PIN(61, "GPIO_61"), + PINCTRL_PIN(62, "GPIO_62"), + PINCTRL_PIN(63, "GPIO_63"), + PINCTRL_PIN(64, "GPIO_64"), + PINCTRL_PIN(65, "GPIO_65"), + PINCTRL_PIN(66, "GPIO_66"), + PINCTRL_PIN(67, "GPIO_67"), + PINCTRL_PIN(68, "GPIO_68"), + PINCTRL_PIN(69, "GPIO_69"), + PINCTRL_PIN(70, "GPIO_70"), + PINCTRL_PIN(71, "GPIO_71"), + PINCTRL_PIN(72, "GPIO_72"), + PINCTRL_PIN(73, "GPIO_73"), + PINCTRL_PIN(74, "GPIO_74"), + PINCTRL_PIN(75, "GPIO_75"), + PINCTRL_PIN(76, "GPIO_76"), + PINCTRL_PIN(77, "GPIO_77"), + PINCTRL_PIN(78, "GPIO_78"), + PINCTRL_PIN(79, "GPIO_79"), + PINCTRL_PIN(80, "GPIO_80"), + PINCTRL_PIN(81, "GPIO_81"), + PINCTRL_PIN(82, "GPIO_82"), + PINCTRL_PIN(83, "GPIO_83"), + PINCTRL_PIN(84, "GPIO_84"), + PINCTRL_PIN(85, "GPIO_85"), + PINCTRL_PIN(86, "GPIO_86"), + PINCTRL_PIN(87, "GPIO_87"), + PINCTRL_PIN(88, "GPIO_88"), + PINCTRL_PIN(89, "GPIO_89"), + PINCTRL_PIN(90, "GPIO_90"), + PINCTRL_PIN(91, "GPIO_91"), + PINCTRL_PIN(92, "GPIO_92"), + PINCTRL_PIN(93, "GPIO_93"), + PINCTRL_PIN(94, "GPIO_94"), + PINCTRL_PIN(95, "GPIO_95"), + PINCTRL_PIN(96, "GPIO_96"), + PINCTRL_PIN(97, "GPIO_97"), + PINCTRL_PIN(98, "GPIO_98"), + PINCTRL_PIN(99, "GPIO_99"), + PINCTRL_PIN(100, "GPIO_100"), + PINCTRL_PIN(101, "GPIO_101"), + PINCTRL_PIN(102, "GPIO_102"), + PINCTRL_PIN(103, "GPIO_103"), + PINCTRL_PIN(104, "GPIO_104"), + PINCTRL_PIN(105, "GPIO_105"), + PINCTRL_PIN(106, "GPIO_106"), + PINCTRL_PIN(107, "GPIO_107"), + PINCTRL_PIN(108, "GPIO_108"), + PINCTRL_PIN(109, "GPIO_109"), + PINCTRL_PIN(110, "GPIO_110"), + PINCTRL_PIN(111, "GPIO_111"), + PINCTRL_PIN(112, "GPIO_112"), + PINCTRL_PIN(113, "GPIO_113"), + PINCTRL_PIN(114, "GPIO_114"), + PINCTRL_PIN(115, "GPIO_115"), + PINCTRL_PIN(116, "GPIO_116"), + PINCTRL_PIN(117, "GPIO_117"), + PINCTRL_PIN(118, "GPIO_118"), + PINCTRL_PIN(119, "GPIO_119"), + PINCTRL_PIN(120, "GPIO_120"), + PINCTRL_PIN(121, "GPIO_121"), + PINCTRL_PIN(122, "GPIO_122"), + PINCTRL_PIN(123, "GPIO_123"), + PINCTRL_PIN(124, "GPIO_124"), + PINCTRL_PIN(125, "GPIO_125"), + PINCTRL_PIN(126, "GPIO_126"), + PINCTRL_PIN(127, "GPIO_127"), + PINCTRL_PIN(128, "GPIO_128"), + PINCTRL_PIN(129, "GPIO_129"), + PINCTRL_PIN(130, "GPIO_130"), + PINCTRL_PIN(131, "GPIO_131"), + PINCTRL_PIN(132, "GPIO_132"), + PINCTRL_PIN(133, "GPIO_133"), + PINCTRL_PIN(134, "GPIO_134"), + PINCTRL_PIN(135, "GPIO_135"), + PINCTRL_PIN(136, "GPIO_136"), + PINCTRL_PIN(137, "GPIO_137"), + PINCTRL_PIN(138, "GPIO_138"), + PINCTRL_PIN(139, "GPIO_139"), + PINCTRL_PIN(140, "GPIO_140"), + PINCTRL_PIN(141, "GPIO_141"), + PINCTRL_PIN(142, "GPIO_142"), + PINCTRL_PIN(143, "GPIO_143"), + PINCTRL_PIN(144, "GPIO_144"), + PINCTRL_PIN(145, "GPIO_145"), + PINCTRL_PIN(146, "GPIO_146"), + PINCTRL_PIN(147, "GPIO_147"), + PINCTRL_PIN(148, "GPIO_148"), + PINCTRL_PIN(149, "GPIO_149"), + PINCTRL_PIN(150, "GPIO_150"), + PINCTRL_PIN(151, "GPIO_151"), + PINCTRL_PIN(152, "GPIO_152"), + PINCTRL_PIN(153, "GPIO_153"), + PINCTRL_PIN(154, "GPIO_154"), + PINCTRL_PIN(155, "GPIO_155"), + PINCTRL_PIN(156, "GPIO_156"), + PINCTRL_PIN(157, "GPIO_157"), + PINCTRL_PIN(158, "GPIO_158"), + PINCTRL_PIN(159, "GPIO_159"), + PINCTRL_PIN(160, "GPIO_160"), + PINCTRL_PIN(161, "GPIO_161"), + PINCTRL_PIN(162, "GPIO_162"), + PINCTRL_PIN(163, "GPIO_163"), + PINCTRL_PIN(164, "GPIO_164"), + PINCTRL_PIN(165, "GPIO_165"), + PINCTRL_PIN(166, "GPIO_166"), + PINCTRL_PIN(167, "GPIO_167"), + PINCTRL_PIN(168, "GPIO_168"), + PINCTRL_PIN(169, "GPIO_169"), + PINCTRL_PIN(170, "GPIO_170"), + PINCTRL_PIN(171, "GPIO_171"), + PINCTRL_PIN(172, "GPIO_172"), + PINCTRL_PIN(173, "GPIO_173"), + PINCTRL_PIN(174, "GPIO_174"), + PINCTRL_PIN(175, "GPIO_175"), + PINCTRL_PIN(176, "GPIO_176"), + PINCTRL_PIN(177, "GPIO_177"), + PINCTRL_PIN(178, "GPIO_178"), + PINCTRL_PIN(179, "GPIO_179"), + PINCTRL_PIN(180, "GPIO_180"), + PINCTRL_PIN(181, "GPIO_181"), + PINCTRL_PIN(182, "GPIO_182"), + PINCTRL_PIN(183, "GPIO_183"), + PINCTRL_PIN(184, "GPIO_184"), + PINCTRL_PIN(185, "GPIO_185"), + PINCTRL_PIN(186, "GPIO_186"), + PINCTRL_PIN(187, "GPIO_187"), + PINCTRL_PIN(188, "GPIO_188"), + PINCTRL_PIN(189, "GPIO_189"), + PINCTRL_PIN(190, "GPIO_190"), + PINCTRL_PIN(191, "GPIO_191"), + PINCTRL_PIN(192, "GPIO_192"), + PINCTRL_PIN(193, "GPIO_193"), + PINCTRL_PIN(194, "GPIO_194"), + PINCTRL_PIN(195, "GPIO_195"), + PINCTRL_PIN(196, "GPIO_196"), + PINCTRL_PIN(197, "GPIO_197"), + PINCTRL_PIN(198, "GPIO_198"), + PINCTRL_PIN(199, "GPIO_199"), + PINCTRL_PIN(200, "GPIO_200"), + PINCTRL_PIN(201, "GPIO_201"), + PINCTRL_PIN(202, "GPIO_202"), + PINCTRL_PIN(203, "GPIO_203"), + PINCTRL_PIN(204, "GPIO_204"), + PINCTRL_PIN(205, "GPIO_205"), + PINCTRL_PIN(206, "GPIO_206"), + PINCTRL_PIN(207, "GPIO_207"), + PINCTRL_PIN(208, "GPIO_208"), + PINCTRL_PIN(209, "GPIO_209"), + PINCTRL_PIN(210, "UFS_RESET"), + PINCTRL_PIN(211, "SDC2_CLK"), + PINCTRL_PIN(212, "SDC2_CMD"), + PINCTRL_PIN(213, "SDC2_DATA"), +}; + +#define DECLARE_MSM_GPIO_PINS(pin) \ + static const unsigned int gpio##pin##_pins[] = { pin } +DECLARE_MSM_GPIO_PINS(0); +DECLARE_MSM_GPIO_PINS(1); +DECLARE_MSM_GPIO_PINS(2); +DECLARE_MSM_GPIO_PINS(3); +DECLARE_MSM_GPIO_PINS(4); +DECLARE_MSM_GPIO_PINS(5); +DECLARE_MSM_GPIO_PINS(6); +DECLARE_MSM_GPIO_PINS(7); +DECLARE_MSM_GPIO_PINS(8); +DECLARE_MSM_GPIO_PINS(9); +DECLARE_MSM_GPIO_PINS(10); +DECLARE_MSM_GPIO_PINS(11); +DECLARE_MSM_GPIO_PINS(12); +DECLARE_MSM_GPIO_PINS(13); +DECLARE_MSM_GPIO_PINS(14); +DECLARE_MSM_GPIO_PINS(15); +DECLARE_MSM_GPIO_PINS(16); +DECLARE_MSM_GPIO_PINS(17); +DECLARE_MSM_GPIO_PINS(18); +DECLARE_MSM_GPIO_PINS(19); +DECLARE_MSM_GPIO_PINS(20); +DECLARE_MSM_GPIO_PINS(21); +DECLARE_MSM_GPIO_PINS(22); +DECLARE_MSM_GPIO_PINS(23); +DECLARE_MSM_GPIO_PINS(24); +DECLARE_MSM_GPIO_PINS(25); +DECLARE_MSM_GPIO_PINS(26); +DECLARE_MSM_GPIO_PINS(27); +DECLARE_MSM_GPIO_PINS(28); +DECLARE_MSM_GPIO_PINS(29); +DECLARE_MSM_GPIO_PINS(30); +DECLARE_MSM_GPIO_PINS(31); +DECLARE_MSM_GPIO_PINS(32); +DECLARE_MSM_GPIO_PINS(33); +DECLARE_MSM_GPIO_PINS(34); +DECLARE_MSM_GPIO_PINS(35); +DECLARE_MSM_GPIO_PINS(36); +DECLARE_MSM_GPIO_PINS(37); +DECLARE_MSM_GPIO_PINS(38); +DECLARE_MSM_GPIO_PINS(39); +DECLARE_MSM_GPIO_PINS(40); +DECLARE_MSM_GPIO_PINS(41); +DECLARE_MSM_GPIO_PINS(42); +DECLARE_MSM_GPIO_PINS(43); +DECLARE_MSM_GPIO_PINS(44); +DECLARE_MSM_GPIO_PINS(45); +DECLARE_MSM_GPIO_PINS(46); +DECLARE_MSM_GPIO_PINS(47); +DECLARE_MSM_GPIO_PINS(48); +DECLARE_MSM_GPIO_PINS(49); +DECLARE_MSM_GPIO_PINS(50); +DECLARE_MSM_GPIO_PINS(51); +DECLARE_MSM_GPIO_PINS(52); +DECLARE_MSM_GPIO_PINS(53); +DECLARE_MSM_GPIO_PINS(54); +DECLARE_MSM_GPIO_PINS(55); +DECLARE_MSM_GPIO_PINS(56); +DECLARE_MSM_GPIO_PINS(57); +DECLARE_MSM_GPIO_PINS(58); +DECLARE_MSM_GPIO_PINS(59); +DECLARE_MSM_GPIO_PINS(60); +DECLARE_MSM_GPIO_PINS(61); +DECLARE_MSM_GPIO_PINS(62); +DECLARE_MSM_GPIO_PINS(63); +DECLARE_MSM_GPIO_PINS(64); +DECLARE_MSM_GPIO_PINS(65); +DECLARE_MSM_GPIO_PINS(66); +DECLARE_MSM_GPIO_PINS(67); +DECLARE_MSM_GPIO_PINS(68); +DECLARE_MSM_GPIO_PINS(69); +DECLARE_MSM_GPIO_PINS(70); +DECLARE_MSM_GPIO_PINS(71); +DECLARE_MSM_GPIO_PINS(72); +DECLARE_MSM_GPIO_PINS(73); +DECLARE_MSM_GPIO_PINS(74); +DECLARE_MSM_GPIO_PINS(75); +DECLARE_MSM_GPIO_PINS(76); +DECLARE_MSM_GPIO_PINS(77); +DECLARE_MSM_GPIO_PINS(78); +DECLARE_MSM_GPIO_PINS(79); +DECLARE_MSM_GPIO_PINS(80); +DECLARE_MSM_GPIO_PINS(81); +DECLARE_MSM_GPIO_PINS(82); +DECLARE_MSM_GPIO_PINS(83); +DECLARE_MSM_GPIO_PINS(84); +DECLARE_MSM_GPIO_PINS(85); +DECLARE_MSM_GPIO_PINS(86); +DECLARE_MSM_GPIO_PINS(87); +DECLARE_MSM_GPIO_PINS(88); +DECLARE_MSM_GPIO_PINS(89); +DECLARE_MSM_GPIO_PINS(90); +DECLARE_MSM_GPIO_PINS(91); +DECLARE_MSM_GPIO_PINS(92); +DECLARE_MSM_GPIO_PINS(93); +DECLARE_MSM_GPIO_PINS(94); +DECLARE_MSM_GPIO_PINS(95); +DECLARE_MSM_GPIO_PINS(96); +DECLARE_MSM_GPIO_PINS(97); +DECLARE_MSM_GPIO_PINS(98); +DECLARE_MSM_GPIO_PINS(99); +DECLARE_MSM_GPIO_PINS(100); +DECLARE_MSM_GPIO_PINS(101); +DECLARE_MSM_GPIO_PINS(102); +DECLARE_MSM_GPIO_PINS(103); +DECLARE_MSM_GPIO_PINS(104); +DECLARE_MSM_GPIO_PINS(105); +DECLARE_MSM_GPIO_PINS(106); +DECLARE_MSM_GPIO_PINS(107); +DECLARE_MSM_GPIO_PINS(108); +DECLARE_MSM_GPIO_PINS(109); +DECLARE_MSM_GPIO_PINS(110); +DECLARE_MSM_GPIO_PINS(111); +DECLARE_MSM_GPIO_PINS(112); +DECLARE_MSM_GPIO_PINS(113); +DECLARE_MSM_GPIO_PINS(114); +DECLARE_MSM_GPIO_PINS(115); +DECLARE_MSM_GPIO_PINS(116); +DECLARE_MSM_GPIO_PINS(117); +DECLARE_MSM_GPIO_PINS(118); +DECLARE_MSM_GPIO_PINS(119); +DECLARE_MSM_GPIO_PINS(120); +DECLARE_MSM_GPIO_PINS(121); +DECLARE_MSM_GPIO_PINS(122); +DECLARE_MSM_GPIO_PINS(123); +DECLARE_MSM_GPIO_PINS(124); +DECLARE_MSM_GPIO_PINS(125); +DECLARE_MSM_GPIO_PINS(126); +DECLARE_MSM_GPIO_PINS(127); +DECLARE_MSM_GPIO_PINS(128); +DECLARE_MSM_GPIO_PINS(129); +DECLARE_MSM_GPIO_PINS(130); +DECLARE_MSM_GPIO_PINS(131); +DECLARE_MSM_GPIO_PINS(132); +DECLARE_MSM_GPIO_PINS(133); +DECLARE_MSM_GPIO_PINS(134); +DECLARE_MSM_GPIO_PINS(135); +DECLARE_MSM_GPIO_PINS(136); +DECLARE_MSM_GPIO_PINS(137); +DECLARE_MSM_GPIO_PINS(138); +DECLARE_MSM_GPIO_PINS(139); +DECLARE_MSM_GPIO_PINS(140); +DECLARE_MSM_GPIO_PINS(141); +DECLARE_MSM_GPIO_PINS(142); +DECLARE_MSM_GPIO_PINS(143); +DECLARE_MSM_GPIO_PINS(144); +DECLARE_MSM_GPIO_PINS(145); +DECLARE_MSM_GPIO_PINS(146); +DECLARE_MSM_GPIO_PINS(147); +DECLARE_MSM_GPIO_PINS(148); +DECLARE_MSM_GPIO_PINS(149); +DECLARE_MSM_GPIO_PINS(150); +DECLARE_MSM_GPIO_PINS(151); +DECLARE_MSM_GPIO_PINS(152); +DECLARE_MSM_GPIO_PINS(153); +DECLARE_MSM_GPIO_PINS(154); +DECLARE_MSM_GPIO_PINS(155); +DECLARE_MSM_GPIO_PINS(156); +DECLARE_MSM_GPIO_PINS(157); +DECLARE_MSM_GPIO_PINS(158); +DECLARE_MSM_GPIO_PINS(159); +DECLARE_MSM_GPIO_PINS(160); +DECLARE_MSM_GPIO_PINS(161); +DECLARE_MSM_GPIO_PINS(162); +DECLARE_MSM_GPIO_PINS(163); +DECLARE_MSM_GPIO_PINS(164); +DECLARE_MSM_GPIO_PINS(165); +DECLARE_MSM_GPIO_PINS(166); +DECLARE_MSM_GPIO_PINS(167); +DECLARE_MSM_GPIO_PINS(168); +DECLARE_MSM_GPIO_PINS(169); +DECLARE_MSM_GPIO_PINS(170); +DECLARE_MSM_GPIO_PINS(171); +DECLARE_MSM_GPIO_PINS(172); +DECLARE_MSM_GPIO_PINS(173); +DECLARE_MSM_GPIO_PINS(174); +DECLARE_MSM_GPIO_PINS(175); +DECLARE_MSM_GPIO_PINS(176); +DECLARE_MSM_GPIO_PINS(177); +DECLARE_MSM_GPIO_PINS(178); +DECLARE_MSM_GPIO_PINS(179); +DECLARE_MSM_GPIO_PINS(180); +DECLARE_MSM_GPIO_PINS(181); +DECLARE_MSM_GPIO_PINS(182); +DECLARE_MSM_GPIO_PINS(183); +DECLARE_MSM_GPIO_PINS(184); +DECLARE_MSM_GPIO_PINS(185); +DECLARE_MSM_GPIO_PINS(186); +DECLARE_MSM_GPIO_PINS(187); +DECLARE_MSM_GPIO_PINS(188); +DECLARE_MSM_GPIO_PINS(189); +DECLARE_MSM_GPIO_PINS(190); +DECLARE_MSM_GPIO_PINS(191); +DECLARE_MSM_GPIO_PINS(192); +DECLARE_MSM_GPIO_PINS(193); +DECLARE_MSM_GPIO_PINS(194); +DECLARE_MSM_GPIO_PINS(195); +DECLARE_MSM_GPIO_PINS(196); +DECLARE_MSM_GPIO_PINS(197); +DECLARE_MSM_GPIO_PINS(198); +DECLARE_MSM_GPIO_PINS(199); +DECLARE_MSM_GPIO_PINS(200); +DECLARE_MSM_GPIO_PINS(201); +DECLARE_MSM_GPIO_PINS(202); +DECLARE_MSM_GPIO_PINS(203); +DECLARE_MSM_GPIO_PINS(204); +DECLARE_MSM_GPIO_PINS(205); +DECLARE_MSM_GPIO_PINS(206); +DECLARE_MSM_GPIO_PINS(207); +DECLARE_MSM_GPIO_PINS(208); +DECLARE_MSM_GPIO_PINS(209); + +static const unsigned int ufs_reset_pins[] = { 210 }; +static const unsigned int sdc2_clk_pins[] = { 211 }; +static const unsigned int sdc2_cmd_pins[] = { 212 }; +static const unsigned int sdc2_data_pins[] = { 213 }; + +enum sm8450_functions { + msm_mux_gpio, + msm_mux_aon_cam, + msm_mux_atest_char, + msm_mux_atest_usb, + msm_mux_audio_ref, + msm_mux_cam_mclk, + msm_mux_cci_async, + msm_mux_cci_i2c, + msm_mux_cci_timer, + msm_mux_cmu_rng, + msm_mux_coex_uart1, + msm_mux_coex_uart2, + msm_mux_cri_trng, + msm_mux_cri_trng0, + msm_mux_cri_trng1, + msm_mux_dbg_out, + msm_mux_ddr_bist, + msm_mux_ddr_pxi0, + msm_mux_ddr_pxi1, + msm_mux_ddr_pxi2, + msm_mux_ddr_pxi3, + msm_mux_dp_hot, + msm_mux_egpio, + msm_mux_gcc_gp1, + msm_mux_gcc_gp2, + msm_mux_gcc_gp3, + msm_mux_ibi_i3c, + msm_mux_jitter_bist, + msm_mux_mdp_vsync, + msm_mux_mdp_vsync0, + msm_mux_mdp_vsync1, + msm_mux_mdp_vsync2, + msm_mux_mdp_vsync3, + msm_mux_mi2s0_data0, + msm_mux_mi2s0_data1, + msm_mux_mi2s0_sck, + msm_mux_mi2s0_ws, + msm_mux_mi2s2_data0, + msm_mux_mi2s2_data1, + msm_mux_mi2s2_sck, + msm_mux_mi2s2_ws, + msm_mux_mss_grfc0, + msm_mux_mss_grfc1, + msm_mux_mss_grfc10, + msm_mux_mss_grfc11, + msm_mux_mss_grfc12, + msm_mux_mss_grfc2, + msm_mux_mss_grfc3, + msm_mux_mss_grfc4, + msm_mux_mss_grfc5, + msm_mux_mss_grfc6, + msm_mux_mss_grfc7, + msm_mux_mss_grfc8, + msm_mux_mss_grfc9, + msm_mux_nav, + msm_mux_pcie0_clkreqn, + msm_mux_pcie1_clkreqn, + msm_mux_phase_flag, + msm_mux_pll_bist, + msm_mux_pll_clk, + msm_mux_pri_mi2s, + msm_mux_prng_rosc, + msm_mux_qdss_cti, + msm_mux_qdss_gpio, + msm_mux_qlink0_enable, + msm_mux_qlink0_request, + msm_mux_qlink0_wmss, + msm_mux_qlink1_enable, + msm_mux_qlink1_request, + msm_mux_qlink1_wmss, + msm_mux_qlink2_enable, + msm_mux_qlink2_request, + msm_mux_qlink2_wmss, + msm_mux_qspi0, + msm_mux_qspi1, + msm_mux_qspi2, + msm_mux_qspi3, + msm_mux_qspi_clk, + msm_mux_qspi_cs, + msm_mux_qup0, + msm_mux_qup1, + msm_mux_qup10, + msm_mux_qup11, + msm_mux_qup12, + msm_mux_qup13, + msm_mux_qup14, + msm_mux_qup15, + msm_mux_qup16, + msm_mux_qup17, + msm_mux_qup18, + msm_mux_qup19, + msm_mux_qup2, + msm_mux_qup20, + msm_mux_qup21, + msm_mux_qup3, + msm_mux_qup4, + msm_mux_qup5, + msm_mux_qup6, + msm_mux_qup7, + msm_mux_qup8, + msm_mux_qup9, + msm_mux_qup_l4, + msm_mux_qup_l5, + msm_mux_qup_l6, + msm_mux_sd_write, + msm_mux_sdc40, + msm_mux_sdc41, + msm_mux_sdc42, + msm_mux_sdc43, + msm_mux_sdc4_clk, + msm_mux_sdc4_cmd, + msm_mux_sec_mi2s, + msm_mux_tb_trig, + msm_mux_tgu_ch0, + msm_mux_tgu_ch1, + msm_mux_tgu_ch2, + msm_mux_tgu_ch3, + msm_mux_tmess_prng0, + msm_mux_tmess_prng1, + msm_mux_tmess_prng2, + msm_mux_tmess_prng3, + msm_mux_tsense_pwm1, + msm_mux_tsense_pwm2, + msm_mux_uim0_clk, + msm_mux_uim0_data, + msm_mux_uim0_present, + msm_mux_uim0_reset, + msm_mux_uim1_clk, + msm_mux_uim1_data, + msm_mux_uim1_present, + msm_mux_uim1_reset, + msm_mux_usb2phy_ac, + msm_mux_usb_phy, + msm_mux_vfr_0, + msm_mux_vfr_1, + msm_mux_vsense_trigger, + msm_mux__, +}; + +static const char * const gpio_groups[] = { + "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7", + "gpio8", "gpio9", "gpio10", "gpio11", "gpio12", "gpio13", "gpio14", + "gpio15", "gpio16", "gpio17", "gpio18", "gpio19", "gpio20", "gpio21", + "gpio22", "gpio23", "gpio24", "gpio25", "gpio26", "gpio27", "gpio28", + "gpio29", "gpio30", "gpio31", "gpio32", "gpio33", "gpio34", "gpio35", + "gpio36", "gpio37", "gpio38", "gpio39", "gpio40", "gpio41", "gpio42", + "gpio43", "gpio44", "gpio45", "gpio46", "gpio47", "gpio48", "gpio49", + "gpio50", "gpio51", "gpio52", "gpio53", "gpio54", "gpio55", "gpio56", + "gpio57", "gpio58", "gpio59", "gpio60", "gpio61", "gpio62", "gpio63", + "gpio64", "gpio65", "gpio66", "gpio67", "gpio68", "gpio69", "gpio70", + "gpio71", "gpio72", "gpio73", "gpio74", "gpio75", "gpio76", "gpio77", + "gpio78", "gpio79", "gpio80", "gpio81", "gpio82", "gpio83", "gpio84", + "gpio85", "gpio86", "gpio87", "gpio88", "gpio89", "gpio90", "gpio91", + "gpio92", "gpio93", "gpio94", "gpio95", "gpio96", "gpio97", "gpio98", + "gpio99", "gpio100", "gpio101", "gpio102", "gpio103", "gpio104", + "gpio105", "gpio106", "gpio107", "gpio108", "gpio109", "gpio110", + "gpio111", "gpio112", "gpio113", "gpio114", "gpio115", "gpio116", + "gpio117", "gpio118", "gpio119", "gpio120", "gpio121", "gpio122", + "gpio123", "gpio124", "gpio125", "gpio126", "gpio127", "gpio128", + "gpio129", "gpio130", "gpio131", "gpio132", "gpio133", "gpio134", + "gpio135", "gpio136", "gpio137", "gpio138", "gpio139", "gpio140", + "gpio141", "gpio142", "gpio143", "gpio144", "gpio145", "gpio146", + "gpio147", "gpio148", "gpio149", "gpio150", "gpio151", "gpio152", + "gpio153", "gpio154", "gpio155", "gpio156", "gpio157", "gpio158", + "gpio159", "gpio160", "gpio161", "gpio162", "gpio163", "gpio164", + "gpio165", "gpio166", "gpio167", "gpio168", "gpio169", "gpio170", + "gpio171", "gpio172", "gpio173", "gpio174", "gpio175", "gpio176", + "gpio177", "gpio178", "gpio179", "gpio180", "gpio181", "gpio182", + "gpio183", "gpio184", "gpio185", "gpio186", "gpio187", "gpio188", + "gpio189", "gpio190", "gpio191", "gpio192", "gpio193", "gpio194", + "gpio195", "gpio196", "gpio197", "gpio198", "gpio199", "gpio200", + "gpio201", "gpio202", "gpio203", "gpio204", "gpio205", "gpio206", + "gpio207", "gpio208", "gpio209", +}; + +static const char * const egpio_groups[] = { + "gpio165", "gpio166", "gpio167", "gpio168", "gpio169", "gpio170", + "gpio171", "gpio172", "gpio173", "gpio174", "gpio175", "gpio176", + "gpio177", "gpio178", "gpio179", "gpio180", "gpio181", "gpio182", + "gpio183", "gpio184", "gpio185", "gpio186", "gpio187", "gpio188", + "gpio189", "gpio190", "gpio191", "gpio192", "gpio193", "gpio194", + "gpio195", "gpio196", "gpio197", "gpio198", "gpio199", "gpio200", + "gpio201", "gpio202", "gpio203", "gpio204", "gpio205", "gpio206", + "gpio207", "gpio208", "gpio209", +}; + +static const char * const aon_cam_groups[] = { + "gpio108", +}; + +static const char * const atest_char_groups[] = { + "gpio86", "gpio87", "gpio88", "gpio89", "gpio90", +}; + +static const char * const atest_usb_groups[] = { + "gpio37", "gpio39", "gpio55", "gpio148", "gpio149", +}; + +static const char * const audio_ref_groups[] = { + "gpio124", +}; + +static const char * const cam_mclk_groups[] = { + "gpio100", "gpio101", "gpio102", "gpio103", "gpio104", "gpio105", "gpio106", "gpio107", +}; + +static const char * const cci_async_groups[] = { + "gpio109", "gpio119", "gpio120", +}; + +static const char * const cci_i2c_groups[] = { + "gpio110", "gpio111", "gpio112", "gpio113", "gpio114", "gpio115", "gpio208", "gpio209", +}; + +static const char * const cci_timer_groups[] = { + "gpio116", "gpio117", "gpio118", "gpio119", "gpio120", +}; + +static const char * const cmu_rng_groups[] = { + "gpio94", "gpio95", "gpio96", "gpio97", +}; + +static const char * const coex_uart1_groups[] = { + "gpio148", "gpio149", +}; + +static const char * const coex_uart2_groups[] = { + "gpio150", "gpio151", +}; + +static const char * const cri_trng_groups[] = { + "gpio99", +}; + +static const char * const cri_trng0_groups[] = { + "gpio71", +}; + +static const char * const cri_trng1_groups[] = { + "gpio72", +}; + +static const char * const dbg_out_groups[] = { + "gpio9", +}; + +static const char * const ddr_bist_groups[] = { + "gpio36", "gpio37", "gpio40", "gpio41", +}; + +static const char * const ddr_pxi0_groups[] = { + "gpio51", "gpio52", +}; + +static const char * const ddr_pxi1_groups[] = { + "gpio40", "gpio41", +}; + +static const char * const ddr_pxi2_groups[] = { + "gpio45", "gpio47", +}; + +static const char * const ddr_pxi3_groups[] = { + "gpio43", "gpio44", +}; + +static const char * const dp_hot_groups[] = { + "gpio47", +}; + +static const char * const gcc_gp1_groups[] = { + "gpio86", "gpio134", +}; + +static const char * const gcc_gp2_groups[] = { + "gpio87", "gpio135", +}; + +static const char * const gcc_gp3_groups[] = { + "gpio88", "gpio136", +}; + +static const char * const ibi_i3c_groups[] = { + "gpio28", "gpio29", "gpio32", "gpio33", "gpio56", "gpio57", "gpio60", "gpio61", +}; + +static const char * const jitter_bist_groups[] = { + "gpio24", +}; + +static const char * const mdp_vsync_groups[] = { + "gpio46", "gpio47", "gpio86", "gpio87", "gpio88", +}; + +static const char * const mdp_vsync0_groups[] = { + "gpio86", +}; + +static const char * const mdp_vsync1_groups[] = { + "gpio86", +}; + +static const char * const mdp_vsync2_groups[] = { + "gpio87", +}; + +static const char * const mdp_vsync3_groups[] = { + "gpio87", +}; + +static const char * const mi2s0_data0_groups[] = { + "gpio127", +}; + +static const char * const mi2s0_data1_groups[] = { + "gpio128", +}; + +static const char * const mi2s0_sck_groups[] = { + "gpio126", +}; + +static const char * const mi2s0_ws_groups[] = { + "gpio129", +}; + +static const char * const mi2s2_data0_groups[] = { + "gpio122", +}; + +static const char * const mi2s2_data1_groups[] = { + "gpio124", +}; + +static const char * const mi2s2_sck_groups[] = { + "gpio121", +}; + +static const char * const mi2s2_ws_groups[] = { + "gpio123", +}; + +static const char * const mss_grfc0_groups[] = { + "gpio138", "gpio153", +}; + +static const char * const mss_grfc1_groups[] = { + "gpio139", +}; + +static const char * const mss_grfc10_groups[] = { + "gpio150", +}; + +static const char * const mss_grfc11_groups[] = { + "gpio151", +}; + +static const char * const mss_grfc12_groups[] = { + "gpio152", +}; + +static const char * const mss_grfc2_groups[] = { + "gpio140", +}; + +static const char * const mss_grfc3_groups[] = { + "gpio141", +}; + +static const char * const mss_grfc4_groups[] = { + "gpio142", +}; + +static const char * const mss_grfc5_groups[] = { + "gpio143", +}; + +static const char * const mss_grfc6_groups[] = { + "gpio144", +}; + +static const char * const mss_grfc7_groups[] = { + "gpio145", +}; + +static const char * const mss_grfc8_groups[] = { + "gpio146", +}; + +static const char * const mss_grfc9_groups[] = { + "gpio147", +}; + +static const char * const nav_groups[] = { + "gpio153", "gpio154", "gpio155", +}; + +static const char * const pcie0_clkreqn_groups[] = { + "gpio95", +}; + +static const char * const pcie1_clkreqn_groups[] = { + "gpio98", +}; + +static const char * const phase_flag_groups[] = { + "gpio4", "gpio5", "gpio6", "gpio7", "gpio10", "gpio11", "gpio12", "gpio13", + "gpio14", "gpio15", "gpio16", "gpio17", "gpio18", "gpio19", "gpio25", "gpio26", + "gpio76", "gpio77", "gpio78", "gpio79", "gpio81", "gpio82", "gpio83", "gpio92", + "gpio93", "gpio94", "gpio95", "gpio96", "gpio97", "gpio98", "gpio99", +}; + +static const char * const pll_bist_groups[] = { + "gpio20", +}; + +static const char * const pll_clk_groups[] = { + "gpio107", +}; + +static const char * const pri_mi2s_groups[] = { + "gpio125", +}; + +static const char * const prng_rosc_groups[] = { + "gpio73", "gpio75", "gpio81", "gpio83", "gpio81", +}; + +static const char * const qdss_cti_groups[] = { + "gpio2", "gpio80", "gpio81", "gpio82", "gpio83", "gpio84", "gpio85", "gpio93", +}; + +static const char * const qdss_gpio_groups[] = { + "gpio100", "gpio101", "gpio102", "gpio103", "gpio104", "gpio105", "gpio106", "gpio107", + "gpio110", "gpio111", "gpio112", "gpio113", "gpio114", "gpio115", "gpio117", "gpio118", + "gpio119", "gpio120", "gpio188", "gpio189", "gpio190", "gpio191", "gpio192", "gpio193", + "gpio194", "gpio195", "gpio196", "gpio197", "gpio198", "gpio199", "gpio200", "gpio201", + "gpio202", "gpio203", "gpio204", "gpio205", +}; + +static const char * const qlink0_enable_groups[] = { + "gpio157", +}; + +static const char * const qlink0_request_groups[] = { + "gpio156", +}; + +static const char * const qlink0_wmss_groups[] = { + "gpio158", +}; + +static const char * const qlink1_enable_groups[] = { + "gpio160", +}; + +static const char * const qlink1_request_groups[] = { + "gpio159", +}; + +static const char * const qlink1_wmss_groups[] = { + "gpio161", +}; + +static const char * const qlink2_enable_groups[] = { + "gpio163", +}; + +static const char * const qlink2_request_groups[] = { + "gpio162", +}; + +static const char * const qlink2_wmss_groups[] = { + "gpio164", +}; + +static const char * const qspi0_groups[] = { + "gpio52", +}; + +static const char * const qspi1_groups[] = { + "gpio53", +}; + +static const char * const qspi2_groups[] = { + "gpio48", +}; + +static const char * const qspi3_groups[] = { + "gpio49", +}; + +static const char * const qspi_clk_groups[] = { + "gpio50", +}; + +static const char * const qspi_cs_groups[] = { + "gpio51", "gpio54", +}; + +static const char * const qup0_groups[] = { + "gpio0", "gpio1", "gpio2", "gpio3", +}; + +static const char * const qup1_groups[] = { + "gpio4", "gpio5", "gpio6", "gpio7", +}; + +static const char * const qup10_groups[] = { + "gpio36", "gpio37", "gpio38", "gpio39", +}; + +static const char * const qup11_groups[] = { + "gpio40", "gpio41", "gpio42", "gpio43", +}; + +static const char * const qup12_groups[] = { + "gpio44", "gpio45", "gpio46", "gpio47", +}; + +static const char * const qup13_groups[] = { + "gpio48", "gpio49", "gpio50", "gpio51", +}; + +static const char * const qup14_groups[] = { + "gpio52", "gpio53", "gpio54", "gpio55", +}; + +static const char * const qup15_groups[] = { + "gpio56", "gpio57", "gpio58", "gpio59", +}; + +static const char * const qup16_groups[] = { + "gpio60", "gpio61", "gpio62", "gpio63", +}; + +static const char * const qup17_groups[] = { + "gpio64", "gpio65", "gpio66", "gpio67", +}; + +static const char * const qup18_groups[] = { + "gpio68", "gpio69", "gpio70", "gpio71", +}; + +static const char * const qup19_groups[] = { + "gpio72", "gpio73", "gpio74", "gpio75", +}; + +static const char * const qup2_groups[] = { + "gpio8", "gpio9", "gpio10", "gpio11", +}; + +static const char * const qup20_groups[] = { + "gpio76", "gpio77", "gpio78", "gpio79", +}; + +static const char * const qup21_groups[] = { + "gpio80", "gpio81", "gpio82", "gpio83", +}; + +static const char * const qup3_groups[] = { + "gpio12", "gpio13", "gpio14", "gpio15", +}; + +static const char * const qup4_groups[] = { + "gpio16", "gpio17", "gpio18", "gpio19", +}; + +static const char * const qup5_groups[] = { + "gpio84", "gpio85", "gpio206", "gpio207", +}; + +static const char * const qup6_groups[] = { + "gpio20", "gpio21", "gpio22", "gpio23", +}; + +static const char * const qup7_groups[] = { + "gpio24", "gpio25", "gpio26", "gpio27", +}; + +static const char * const qup8_groups[] = { + "gpio28", "gpio29", "gpio30", "gpio31", +}; + +static const char * const qup9_groups[] = { + "gpio32", "gpio33", "gpio34", "gpio35", +}; + +static const char * const qup_l4_groups[] = { + "gpio24", "gpio40", "gpio58", "gpio63", +}; + +static const char * const qup_l5_groups[] = { + "gpio25", "gpio41", "gpio59", "gpio66", +}; + +static const char * const qup_l6_groups[] = { + "gpio26", "gpio42", "gpio62", "gpio67", +}; + +static const char * const sd_write_groups[] = { + "gpio93", +}; + +static const char * const sdc40_groups[] = { + "gpio52", +}; + +static const char * const sdc41_groups[] = { + "gpio53", +}; + +static const char * const sdc42_groups[] = { + "gpio48", +}; + +static const char * const sdc43_groups[] = { + "gpio49", +}; + +static const char * const sdc4_clk_groups[] = { + "gpio50", +}; + +static const char * const sdc4_cmd_groups[] = { + "gpio51", +}; + +static const char * const sec_mi2s_groups[] = { + "gpio124", +}; + +static const char * const tb_trig_groups[] = { + "gpio64", "gpio137", +}; + +static const char * const tgu_ch0_groups[] = { + "gpio64", +}; + +static const char * const tgu_ch1_groups[] = { + "gpio65", +}; + +static const char * const tgu_ch2_groups[] = { + "gpio66", +}; + +static const char * const tgu_ch3_groups[] = { + "gpio67", +}; + +static const char * const tmess_prng0_groups[] = { + "gpio80", +}; + +static const char * const tmess_prng1_groups[] = { + "gpio79", +}; + +static const char * const tmess_prng2_groups[] = { + "gpio77", +}; + +static const char * const tmess_prng3_groups[] = { + "gpio76", +}; + +static const char * const tsense_pwm1_groups[] = { + "gpio91", +}; + +static const char * const tsense_pwm2_groups[] = { + "gpio91", +}; + +static const char * const uim0_clk_groups[] = { + "gpio131", +}; + +static const char * const uim0_data_groups[] = { + "gpio130", +}; + +static const char * const uim0_present_groups[] = { + "gpio133", +}; + +static const char * const uim0_reset_groups[] = { + "gpio132", +}; + +static const char * const uim1_clk_groups[] = { + "gpio135", +}; + +static const char * const uim1_data_groups[] = { + "gpio134", +}; + +static const char * const uim1_present_groups[] = { + "gpio137", +}; + +static const char * const uim1_reset_groups[] = { + "gpio136", +}; + +static const char * const usb2phy_ac_groups[] = { + "gpio90", +}; + +static const char * const usb_phy_groups[] = { + "gpio91", +}; + +static const char * const vfr_0_groups[] = { + "gpio89", +}; + +static const char * const vfr_1_groups[] = { + "gpio155", +}; + +static const char * const vsense_trigger_groups[] = { + "gpio18", +}; + +static const struct pinfunction sm8450_functions[] = { + MSM_PIN_FUNCTION(gpio), + MSM_PIN_FUNCTION(aon_cam), + MSM_PIN_FUNCTION(atest_char), + MSM_PIN_FUNCTION(atest_usb), + MSM_PIN_FUNCTION(audio_ref), + MSM_PIN_FUNCTION(cam_mclk), + MSM_PIN_FUNCTION(cci_async), + MSM_PIN_FUNCTION(cci_i2c), + MSM_PIN_FUNCTION(cci_timer), + MSM_PIN_FUNCTION(cmu_rng), + MSM_PIN_FUNCTION(coex_uart1), + MSM_PIN_FUNCTION(coex_uart2), + MSM_PIN_FUNCTION(cri_trng), + MSM_PIN_FUNCTION(cri_trng0), + MSM_PIN_FUNCTION(cri_trng1), + MSM_PIN_FUNCTION(dbg_out), + MSM_PIN_FUNCTION(ddr_bist), + MSM_PIN_FUNCTION(ddr_pxi0), + MSM_PIN_FUNCTION(ddr_pxi1), + MSM_PIN_FUNCTION(ddr_pxi2), + MSM_PIN_FUNCTION(ddr_pxi3), + MSM_PIN_FUNCTION(dp_hot), + MSM_PIN_FUNCTION(egpio), + MSM_PIN_FUNCTION(gcc_gp1), + MSM_PIN_FUNCTION(gcc_gp2), + MSM_PIN_FUNCTION(gcc_gp3), + MSM_PIN_FUNCTION(ibi_i3c), + MSM_PIN_FUNCTION(jitter_bist), + MSM_PIN_FUNCTION(mdp_vsync), + MSM_PIN_FUNCTION(mdp_vsync0), + MSM_PIN_FUNCTION(mdp_vsync1), + MSM_PIN_FUNCTION(mdp_vsync2), + MSM_PIN_FUNCTION(mdp_vsync3), + MSM_PIN_FUNCTION(mi2s0_data0), + MSM_PIN_FUNCTION(mi2s0_data1), + MSM_PIN_FUNCTION(mi2s0_sck), + MSM_PIN_FUNCTION(mi2s0_ws), + MSM_PIN_FUNCTION(mi2s2_data0), + MSM_PIN_FUNCTION(mi2s2_data1), + MSM_PIN_FUNCTION(mi2s2_sck), + MSM_PIN_FUNCTION(mi2s2_ws), + MSM_PIN_FUNCTION(mss_grfc0), + MSM_PIN_FUNCTION(mss_grfc1), + MSM_PIN_FUNCTION(mss_grfc10), + MSM_PIN_FUNCTION(mss_grfc11), + MSM_PIN_FUNCTION(mss_grfc12), + MSM_PIN_FUNCTION(mss_grfc2), + MSM_PIN_FUNCTION(mss_grfc3), + MSM_PIN_FUNCTION(mss_grfc4), + MSM_PIN_FUNCTION(mss_grfc5), + MSM_PIN_FUNCTION(mss_grfc6), + MSM_PIN_FUNCTION(mss_grfc7), + MSM_PIN_FUNCTION(mss_grfc8), + MSM_PIN_FUNCTION(mss_grfc9), + MSM_PIN_FUNCTION(nav), + MSM_PIN_FUNCTION(pcie0_clkreqn), + MSM_PIN_FUNCTION(pcie1_clkreqn), + MSM_PIN_FUNCTION(phase_flag), + MSM_PIN_FUNCTION(pll_bist), + MSM_PIN_FUNCTION(pll_clk), + MSM_PIN_FUNCTION(pri_mi2s), + MSM_PIN_FUNCTION(prng_rosc), + MSM_PIN_FUNCTION(qdss_cti), + MSM_PIN_FUNCTION(qdss_gpio), + MSM_PIN_FUNCTION(qlink0_enable), + MSM_PIN_FUNCTION(qlink0_request), + MSM_PIN_FUNCTION(qlink0_wmss), + MSM_PIN_FUNCTION(qlink1_enable), + MSM_PIN_FUNCTION(qlink1_request), + MSM_PIN_FUNCTION(qlink1_wmss), + MSM_PIN_FUNCTION(qlink2_enable), + MSM_PIN_FUNCTION(qlink2_request), + MSM_PIN_FUNCTION(qlink2_wmss), + MSM_PIN_FUNCTION(qspi0), + MSM_PIN_FUNCTION(qspi1), + MSM_PIN_FUNCTION(qspi2), + MSM_PIN_FUNCTION(qspi3), + MSM_PIN_FUNCTION(qspi_clk), + MSM_PIN_FUNCTION(qspi_cs), + MSM_PIN_FUNCTION(qup0), + MSM_PIN_FUNCTION(qup1), + MSM_PIN_FUNCTION(qup10), + MSM_PIN_FUNCTION(qup11), + MSM_PIN_FUNCTION(qup12), + MSM_PIN_FUNCTION(qup13), + MSM_PIN_FUNCTION(qup14), + MSM_PIN_FUNCTION(qup15), + MSM_PIN_FUNCTION(qup16), + MSM_PIN_FUNCTION(qup17), + MSM_PIN_FUNCTION(qup18), + MSM_PIN_FUNCTION(qup19), + MSM_PIN_FUNCTION(qup2), + MSM_PIN_FUNCTION(qup20), + MSM_PIN_FUNCTION(qup21), + MSM_PIN_FUNCTION(qup3), + MSM_PIN_FUNCTION(qup4), + MSM_PIN_FUNCTION(qup5), + MSM_PIN_FUNCTION(qup6), + MSM_PIN_FUNCTION(qup7), + MSM_PIN_FUNCTION(qup8), + MSM_PIN_FUNCTION(qup9), + MSM_PIN_FUNCTION(qup_l4), + MSM_PIN_FUNCTION(qup_l5), + MSM_PIN_FUNCTION(qup_l6), + MSM_PIN_FUNCTION(sd_write), + MSM_PIN_FUNCTION(sdc40), + MSM_PIN_FUNCTION(sdc41), + MSM_PIN_FUNCTION(sdc42), + MSM_PIN_FUNCTION(sdc43), + MSM_PIN_FUNCTION(sdc4_clk), + MSM_PIN_FUNCTION(sdc4_cmd), + MSM_PIN_FUNCTION(sec_mi2s), + MSM_PIN_FUNCTION(tb_trig), + MSM_PIN_FUNCTION(tgu_ch0), + MSM_PIN_FUNCTION(tgu_ch1), + MSM_PIN_FUNCTION(tgu_ch2), + MSM_PIN_FUNCTION(tgu_ch3), + MSM_PIN_FUNCTION(tmess_prng0), + MSM_PIN_FUNCTION(tmess_prng1), + MSM_PIN_FUNCTION(tmess_prng2), + MSM_PIN_FUNCTION(tmess_prng3), + MSM_PIN_FUNCTION(tsense_pwm1), + MSM_PIN_FUNCTION(tsense_pwm2), + MSM_PIN_FUNCTION(uim0_clk), + MSM_PIN_FUNCTION(uim0_data), + MSM_PIN_FUNCTION(uim0_present), + MSM_PIN_FUNCTION(uim0_reset), + MSM_PIN_FUNCTION(uim1_clk), + MSM_PIN_FUNCTION(uim1_data), + MSM_PIN_FUNCTION(uim1_present), + MSM_PIN_FUNCTION(uim1_reset), + MSM_PIN_FUNCTION(usb2phy_ac), + MSM_PIN_FUNCTION(usb_phy), + MSM_PIN_FUNCTION(vfr_0), + MSM_PIN_FUNCTION(vfr_1), + MSM_PIN_FUNCTION(vsense_trigger), +}; + +/* Every pin is maintained as a single group, and missing or non-existing pin + * would be maintained as dummy group to synchronize pin group index with + * pin descriptor registered with pinctrl core. + * Clients would not be able to request these dummy pin groups. + */ +static const struct msm_pingroup sm8450_groups[] = { + [0] = PINGROUP(0, qup0, _, _, _, _, _, _, _, _), + [1] = PINGROUP(1, qup0, _, _, _, _, _, _, _, _), + [2] = PINGROUP(2, qup0, qdss_cti, _, _, _, _, _, _, _), + [3] = PINGROUP(3, qup0, _, _, _, _, _, _, _, _), + [4] = PINGROUP(4, qup1, phase_flag, _, _, _, _, _, _, _), + [5] = PINGROUP(5, qup1, phase_flag, _, _, _, _, _, _, _), + [6] = PINGROUP(6, qup1, phase_flag, _, _, _, _, _, _, _), + [7] = PINGROUP(7, qup1, phase_flag, _, _, _, _, _, _, _), + [8] = PINGROUP(8, qup2, _, _, _, _, _, _, _, _), + [9] = PINGROUP(9, qup2, dbg_out, _, _, _, _, _, _, _), + [10] = PINGROUP(10, qup2, phase_flag, _, _, _, _, _, _, _), + [11] = PINGROUP(11, qup2, phase_flag, _, _, _, _, _, _, _), + [12] = PINGROUP(12, qup3, phase_flag, _, _, _, _, _, _, _), + [13] = PINGROUP(13, qup3, phase_flag, _, _, _, _, _, _, _), + [14] = PINGROUP(14, qup3, phase_flag, _, _, _, _, _, _, _), + [15] = PINGROUP(15, qup3, phase_flag, _, _, _, _, _, _, _), + [16] = PINGROUP(16, qup4, phase_flag, _, _, _, _, _, _, _), + [17] = PINGROUP(17, qup4, phase_flag, _, _, _, _, _, _, _), + [18] = PINGROUP(18, qup4, phase_flag, _, vsense_trigger, _, _, _, _, _), + [19] = PINGROUP(19, qup4, phase_flag, _, _, _, _, _, _, _), + [20] = PINGROUP(20, qup6, pll_bist, _, _, _, _, _, _, _), + [21] = PINGROUP(21, qup6, _, _, _, _, _, _, _, _), + [22] = PINGROUP(22, qup6, _, _, _, _, _, _, _, _), + [23] = PINGROUP(23, qup6, _, _, _, _, _, _, _, _), + [24] = PINGROUP(24, qup7, qup_l4, jitter_bist, _, _, _, _, _, _), + [25] = PINGROUP(25, qup7, qup_l5, phase_flag, _, _, _, _, _, _), + [26] = PINGROUP(26, qup7, qup_l6, phase_flag, _, _, _, _, _, _), + [27] = PINGROUP(27, qup7, _, _, _, _, _, _, _, _), + [28] = PINGROUP(28, qup8, ibi_i3c, _, _, _, _, _, _, _), + [29] = PINGROUP(29, qup8, ibi_i3c, _, _, _, _, _, _, _), + [30] = PINGROUP(30, qup8, _, _, _, _, _, _, _, _), + [31] = PINGROUP(31, qup8, _, _, _, _, _, _, _, _), + [32] = PINGROUP(32, qup9, ibi_i3c, _, _, _, _, _, _, _), + [33] = PINGROUP(33, qup9, ibi_i3c, _, _, _, _, _, _, _), + [34] = PINGROUP(34, qup9, _, _, _, _, _, _, _, _), + [35] = PINGROUP(35, qup9, _, _, _, _, _, _, _, _), + [36] = PINGROUP(36, qup10, ddr_bist, _, _, _, _, _, _, _), + [37] = PINGROUP(37, qup10, ddr_bist, atest_usb, _, _, _, _, _, _), + [38] = PINGROUP(38, qup10, _, _, _, _, _, _, _, _), + [39] = PINGROUP(39, qup10, atest_usb, _, _, _, _, _, _, _), + [40] = PINGROUP(40, qup11, qup_l4, ddr_bist, ddr_pxi1, _, _, _, _, _), + [41] = PINGROUP(41, qup11, qup_l5, ddr_bist, ddr_pxi1, _, _, _, _, _), + [42] = PINGROUP(42, qup11, qup_l6, _, _, _, _, _, _, _), + [43] = PINGROUP(43, qup11, ddr_pxi3, _, _, _, _, _, _, _), + [44] = PINGROUP(44, qup12, ddr_pxi3, _, _, _, _, _, _, _), + [45] = PINGROUP(45, qup12, ddr_pxi2, _, _, _, _, _, _, _), + [46] = PINGROUP(46, qup12, mdp_vsync, _, _, _, _, _, _, _), + [47] = PINGROUP(47, qup12, dp_hot, mdp_vsync, ddr_pxi2, _, _, _, _, _), + [48] = PINGROUP(48, qup13, qspi2, sdc42, _, _, _, _, _, _), + [49] = PINGROUP(49, qup13, qspi3, sdc43, _, _, _, _, _, _), + [50] = PINGROUP(50, qup13, qspi_clk, sdc4_clk, _, _, _, _, _, _), + [51] = PINGROUP(51, qup13, qspi_cs, sdc4_cmd, ddr_pxi0, _, _, _, _, _), + [52] = PINGROUP(52, qup14, qspi0, sdc40, ddr_pxi0, _, _, _, _, _), + [53] = PINGROUP(53, qup14, qspi1, sdc41, _, _, _, _, _, _), + [54] = PINGROUP(54, qup14, qspi_cs, _, _, _, _, _, _, _), + [55] = PINGROUP(55, qup14, atest_usb, _, _, _, _, _, _, _), + [56] = PINGROUP(56, qup15, ibi_i3c, _, _, _, _, _, _, _), + [57] = PINGROUP(57, qup15, ibi_i3c, _, _, _, _, _, _, _), + [58] = PINGROUP(58, qup15, qup_l4, _, _, _, _, _, _, _), + [59] = PINGROUP(59, qup15, qup_l5, _, _, _, _, _, _, _), + [60] = PINGROUP(60, qup16, ibi_i3c, _, _, _, _, _, _, _), + [61] = PINGROUP(61, qup16, ibi_i3c, _, _, _, _, _, _, _), + [62] = PINGROUP(62, qup16, qup_l6, _, _, _, _, _, _, _), + [63] = PINGROUP(63, qup16, qup_l4, _, _, _, _, _, _, _), + [64] = PINGROUP(64, qup17, tb_trig, tgu_ch0, _, _, _, _, _, _), + [65] = PINGROUP(65, qup17, tgu_ch1, _, _, _, _, _, _, _), + [66] = PINGROUP(66, qup17, qup_l5, tgu_ch2, _, _, _, _, _, _), + [67] = PINGROUP(67, qup17, qup_l6, tgu_ch3, _, _, _, _, _, _), + [68] = PINGROUP(68, qup18, _, _, _, _, _, _, _, _), + [69] = PINGROUP(69, qup18, _, _, _, _, _, _, _, _), + [70] = PINGROUP(70, qup18, _, _, _, _, _, _, _, _), + [71] = PINGROUP(71, qup18, cri_trng0, _, _, _, _, _, _, _), + [72] = PINGROUP(72, qup19, cri_trng1, _, _, _, _, _, _, _), + [73] = PINGROUP(73, qup19, prng_rosc, _, _, _, _, _, _, _), + [74] = PINGROUP(74, qup19, _, _, _, _, _, _, _, _), + [75] = PINGROUP(75, qup19, prng_rosc, _, _, _, _, _, _, _), + [76] = PINGROUP(76, qup20, phase_flag, tmess_prng3, _, _, _, _, _, _), + [77] = PINGROUP(77, qup20, phase_flag, tmess_prng2, _, _, _, _, _, _), + [78] = PINGROUP(78, qup20, phase_flag, _, _, _, _, _, _, _), + [79] = PINGROUP(79, qup20, phase_flag, tmess_prng1, _, _, _, _, _, _), + [80] = PINGROUP(80, qup21, qdss_cti, phase_flag, tmess_prng0, _, _, _, _, _), + [81] = PINGROUP(81, qup21, qdss_cti, phase_flag, prng_rosc, _, _, _, _, _), + [82] = PINGROUP(82, qup21, qdss_cti, phase_flag, _, _, _, _, _, _), + [83] = PINGROUP(83, qup21, qdss_cti, phase_flag, prng_rosc, _, _, _, _, _), + [84] = PINGROUP(84, qup5, qdss_cti, _, _, _, _, _, _, _), + [85] = PINGROUP(85, qup5, qdss_cti, _, _, _, _, _, _, _), + [86] = PINGROUP(86, mdp_vsync, mdp_vsync0, mdp_vsync1, gcc_gp1, atest_char, _, _, _, _), + [87] = PINGROUP(87, mdp_vsync, mdp_vsync2, mdp_vsync3, gcc_gp2, atest_char, _, _, _, _), + [88] = PINGROUP(88, mdp_vsync, gcc_gp3, atest_char, _, _, _, _, _, _), + [89] = PINGROUP(89, vfr_0, atest_char, _, _, _, _, _, _, _), + [90] = PINGROUP(90, usb2phy_ac, atest_char, _, _, _, _, _, _, _), + [91] = PINGROUP(91, usb_phy, tsense_pwm1, tsense_pwm2, _, _, _, _, _, _), + [92] = PINGROUP(92, phase_flag, _, _, _, _, _, _, _, _), + [93] = PINGROUP(93, sd_write, qdss_cti, phase_flag, _, _, _, _, _, _), + [94] = PINGROUP(94, cmu_rng, phase_flag, _, _, _, _, _, _, _), + [95] = PINGROUP(95, pcie0_clkreqn, cmu_rng, phase_flag, _, _, _, _, _, _), + [96] = PINGROUP(96, cmu_rng, phase_flag, _, _, _, _, _, _, _), + [97] = PINGROUP(97, cmu_rng, phase_flag, _, _, _, _, _, _, _), + [98] = PINGROUP(98, pcie1_clkreqn, phase_flag, _, _, _, _, _, _, _), + [99] = PINGROUP(99, phase_flag, cri_trng, _, _, _, _, _, _, _), + [100] = PINGROUP(100, cam_mclk, qdss_gpio, _, _, _, _, _, _, _), + [101] = PINGROUP(101, cam_mclk, qdss_gpio, _, _, _, _, _, _, _), + [102] = PINGROUP(102, cam_mclk, qdss_gpio, _, _, _, _, _, _, _), + [103] = PINGROUP(103, cam_mclk, qdss_gpio, _, _, _, _, _, _, _), + [104] = PINGROUP(104, cam_mclk, qdss_gpio, _, _, _, _, _, _, _), + [105] = PINGROUP(105, cam_mclk, qdss_gpio, _, _, _, _, _, _, _), + [106] = PINGROUP(106, cam_mclk, qdss_gpio, _, _, _, _, _, _, _), + [107] = PINGROUP(107, cam_mclk, qdss_gpio, pll_clk, _, _, _, _, _, _), + [108] = PINGROUP(108, aon_cam, _, _, _, _, _, _, _, _), + [109] = PINGROUP(109, cci_async, _, _, _, _, _, _, _, _), + [110] = PINGROUP(110, cci_i2c, qdss_gpio, _, _, _, _, _, _, _), + [111] = PINGROUP(111, cci_i2c, qdss_gpio, _, _, _, _, _, _, _), + [112] = PINGROUP(112, cci_i2c, qdss_gpio, _, _, _, _, _, _, _), + [113] = PINGROUP(113, cci_i2c, qdss_gpio, _, _, _, _, _, _, _), + [114] = PINGROUP(114, cci_i2c, qdss_gpio, _, _, _, _, _, _, _), + [115] = PINGROUP(115, cci_i2c, qdss_gpio, _, _, _, _, _, _, _), + [116] = PINGROUP(116, cci_timer, _, _, _, _, _, _, _, _), + [117] = PINGROUP(117, cci_timer, qdss_gpio, _, _, _, _, _, _, _), + [118] = PINGROUP(118, cci_timer, qdss_gpio, _, _, _, _, _, _, _), + [119] = PINGROUP(119, cci_timer, cci_async, qdss_gpio, _, _, _, _, _, _), + [120] = PINGROUP(120, cci_timer, cci_async, qdss_gpio, _, _, _, _, _, _), + [121] = PINGROUP(121, mi2s2_sck, _, _, _, _, _, _, _, _), + [122] = PINGROUP(122, mi2s2_data0, _, _, _, _, _, _, _, _), + [123] = PINGROUP(123, mi2s2_ws, _, _, _, _, _, _, _, _), + [124] = PINGROUP(124, mi2s2_data1, sec_mi2s, audio_ref, _, _, _, _, _, _), + [125] = PINGROUP(125, pri_mi2s, _, _, _, _, _, _, _, _), + [126] = PINGROUP(126, mi2s0_sck, _, _, _, _, _, _, _, _), + [127] = PINGROUP(127, mi2s0_data0, _, _, _, _, _, _, _, _), + [128] = PINGROUP(128, mi2s0_data1, _, _, _, _, _, _, _, _), + [129] = PINGROUP(129, mi2s0_ws, _, _, _, _, _, _, _, _), + [130] = PINGROUP(130, uim0_data, _, _, _, _, _, _, _, _), + [131] = PINGROUP(131, uim0_clk, _, _, _, _, _, _, _, _), + [132] = PINGROUP(132, uim0_reset, _, _, _, _, _, _, _, _), + [133] = PINGROUP(133, uim0_present, _, _, _, _, _, _, _, _), + [134] = PINGROUP(134, uim1_data, gcc_gp1, _, _, _, _, _, _, _), + [135] = PINGROUP(135, uim1_clk, gcc_gp2, _, _, _, _, _, _, _), + [136] = PINGROUP(136, uim1_reset, gcc_gp3, _, _, _, _, _, _, _), + [137] = PINGROUP(137, uim1_present, tb_trig, _, _, _, _, _, _, _), + [138] = PINGROUP(138, _, mss_grfc0, _, _, _, _, _, _, _), + [139] = PINGROUP(139, _, mss_grfc1, _, _, _, _, _, _, _), + [140] = PINGROUP(140, _, mss_grfc2, _, _, _, _, _, _, _), + [141] = PINGROUP(141, _, mss_grfc3, _, _, _, _, _, _, _), + [142] = PINGROUP(142, _, mss_grfc4, _, _, _, _, _, _, _), + [143] = PINGROUP(143, _, mss_grfc5, _, _, _, _, _, _, _), + [144] = PINGROUP(144, _, mss_grfc6, _, _, _, _, _, _, _), + [145] = PINGROUP(145, _, mss_grfc7, _, _, _, _, _, _, _), + [146] = PINGROUP(146, _, mss_grfc8, _, _, _, _, _, _, _), + [147] = PINGROUP(147, _, mss_grfc9, _, _, _, _, _, _, _), + [148] = PINGROUP(148, coex_uart1, atest_usb, _, _, _, _, _, _, _), + [149] = PINGROUP(149, coex_uart1, atest_usb, _, _, _, _, _, _, _), + [150] = PINGROUP(150, coex_uart2, mss_grfc10, _, _, _, _, _, _, _), + [151] = PINGROUP(151, coex_uart2, mss_grfc11, _, _, _, _, _, _, _), + [152] = PINGROUP(152, mss_grfc12, _, _, _, _, _, _, _, _), + [153] = PINGROUP(153, mss_grfc0, nav, _, _, _, _, _, _, _), + [154] = PINGROUP(154, nav, _, _, _, _, _, _, _, _), + [155] = PINGROUP(155, nav, vfr_1, _, _, _, _, _, _, _), + [156] = PINGROUP(156, qlink0_request, _, _, _, _, _, _, _, _), + [157] = PINGROUP(157, qlink0_enable, _, _, _, _, _, _, _, _), + [158] = PINGROUP(158, qlink0_wmss, _, _, _, _, _, _, _, _), + [159] = PINGROUP(159, qlink1_request, _, _, _, _, _, _, _, _), + [160] = PINGROUP(160, qlink1_enable, _, _, _, _, _, _, _, _), + [161] = PINGROUP(161, qlink1_wmss, _, _, _, _, _, _, _, _), + [162] = PINGROUP(162, qlink2_request, _, _, _, _, _, _, _, _), + [163] = PINGROUP(163, qlink2_enable, _, _, _, _, _, _, _, _), + [164] = PINGROUP(164, qlink2_wmss, _, _, _, _, _, _, _, _), + [165] = PINGROUP(165, _, _, _, _, _, _, _, _, egpio), + [166] = PINGROUP(166, _, _, _, _, _, _, _, _, egpio), + [167] = PINGROUP(167, _, _, _, _, _, _, _, _, egpio), + [168] = PINGROUP(168, _, _, _, _, _, _, _, _, egpio), + [169] = PINGROUP(169, _, _, _, _, _, _, _, _, egpio), + [170] = PINGROUP(170, _, _, _, _, _, _, _, _, egpio), + [171] = PINGROUP(171, _, _, _, _, _, _, _, _, egpio), + [172] = PINGROUP(172, _, _, _, _, _, _, _, _, egpio), + [173] = PINGROUP(173, _, _, _, _, _, _, _, _, egpio), + [174] = PINGROUP(174, _, _, _, _, _, _, _, _, egpio), + [175] = PINGROUP(175, _, _, _, _, _, _, _, _, egpio), + [176] = PINGROUP(176, _, _, _, _, _, _, _, _, egpio), + [177] = PINGROUP(177, _, _, _, _, _, _, _, _, egpio), + [178] = PINGROUP(178, _, _, _, _, _, _, _, _, egpio), + [179] = PINGROUP(179, _, _, _, _, _, _, _, _, egpio), + [180] = PINGROUP(180, _, _, _, _, _, _, _, _, egpio), + [181] = PINGROUP(181, _, _, _, _, _, _, _, _, egpio), + [182] = PINGROUP(182, _, _, _, _, _, _, _, _, egpio), + [183] = PINGROUP(183, _, _, _, _, _, _, _, _, egpio), + [184] = PINGROUP(184, _, _, _, _, _, _, _, _, egpio), + [185] = PINGROUP(185, _, _, _, _, _, _, _, _, egpio), + [186] = PINGROUP(186, _, _, _, _, _, _, _, _, egpio), + [187] = PINGROUP(187, _, _, _, _, _, _, _, _, egpio), + [188] = PINGROUP(188, _, qdss_gpio, _, _, _, _, _, _, egpio), + [189] = PINGROUP(189, _, qdss_gpio, _, _, _, _, _, _, egpio), + [190] = PINGROUP(190, qdss_gpio, _, _, _, _, _, _, _, egpio), + [191] = PINGROUP(191, qdss_gpio, _, _, _, _, _, _, _, egpio), + [192] = PINGROUP(192, _, qdss_gpio, _, _, _, _, _, _, egpio), + [193] = PINGROUP(193, _, qdss_gpio, _, _, _, _, _, _, egpio), + [194] = PINGROUP(194, _, qdss_gpio, _, _, _, _, _, _, egpio), + [195] = PINGROUP(195, _, qdss_gpio, _, _, _, _, _, _, egpio), + [196] = PINGROUP(196, _, qdss_gpio, _, _, _, _, _, _, egpio), + [197] = PINGROUP(197, _, qdss_gpio, _, _, _, _, _, _, egpio), + [198] = PINGROUP(198, _, qdss_gpio, _, _, _, _, _, _, egpio), + [199] = PINGROUP(199, _, qdss_gpio, _, _, _, _, _, _, egpio), + [200] = PINGROUP(200, _, qdss_gpio, _, _, _, _, _, _, egpio), + [201] = PINGROUP(201, _, qdss_gpio, _, _, _, _, _, _, egpio), + [202] = PINGROUP(202, qdss_gpio, _, _, _, _, _, _, _, egpio), + [203] = PINGROUP(203, qdss_gpio, _, _, _, _, _, _, _, egpio), + [204] = PINGROUP(204, qdss_gpio, _, _, _, _, _, _, _, egpio), + [205] = PINGROUP(205, qdss_gpio, _, _, _, _, _, _, _, egpio), + [206] = PINGROUP(206, qup5, _, _, _, _, _, _, _, egpio), + [207] = PINGROUP(207, qup5, _, _, _, _, _, _, _, egpio), + [208] = PINGROUP(208, cci_i2c, _, _, _, _, _, _, _, egpio), + [209] = PINGROUP(209, cci_i2c, _, _, _, _, _, _, _, egpio), + [210] = UFS_RESET(ufs_reset, 0xde000), + [211] = SDC_QDSD_PINGROUP(sdc2_clk, 0xd6000, 14, 6), + [212] = SDC_QDSD_PINGROUP(sdc2_cmd, 0xd6000, 11, 3), + [213] = SDC_QDSD_PINGROUP(sdc2_data, 0xd6000, 9, 0), +}; + +static const struct msm_gpio_wakeirq_map sm8450_pdc_map[] = { + { 2, 70 }, { 3, 77 }, { 7, 52 }, { 8, 108 }, { 10, 128 }, { 11, 53 }, + { 12, 129 }, { 13, 130 }, { 14, 131 }, { 15, 67 }, { 19, 69 }, { 21, 132 }, + { 23, 54 }, { 26, 56 }, { 27, 71 }, { 28, 57 }, { 31, 55 }, { 32, 58 }, + { 34, 72 }, { 35, 43 }, { 36, 78 }, { 38, 79 }, { 39, 62 }, { 40, 80 }, + { 41, 133 }, { 43, 81 }, { 44, 87 }, { 45, 134 }, { 46, 66 }, { 47, 63 }, + { 50, 88 }, { 51, 89 }, { 55, 90 }, { 56, 59 }, { 59, 82 }, { 60, 60 }, + { 62, 135 }, { 63, 91 }, { 66, 136 }, { 67, 44 }, { 69, 137 }, { 71, 97 }, + { 75, 73 }, { 79, 74 }, { 80, 96 }, { 81, 98 }, { 82, 45 }, { 83, 99 }, + { 84, 94 }, { 85, 100 }, { 86, 101 }, { 87, 102 }, { 88, 92 }, { 89, 83 }, + { 90, 84 }, { 91, 85 }, { 92, 46 }, { 95, 103 }, { 96, 104 }, { 98, 105 }, + { 99, 106 }, { 115, 95 }, { 116, 76 }, { 117, 75 }, { 118, 86 }, { 119, 93 }, + { 133, 47 }, { 137, 42 }, { 148, 61 }, { 150, 68 }, { 153, 65 }, { 154, 48 }, + { 155, 49 }, { 156, 64 }, { 159, 50 }, { 162, 51 }, { 166, 111 }, { 169, 114 }, + { 171, 115 }, { 172, 116 }, { 174, 117 }, { 176, 107 }, { 181, 109 }, + { 182, 110 }, { 185, 112 }, { 187, 113 }, { 188, 118 }, { 190, 122 }, + { 192, 123 }, { 195, 124 }, { 201, 119 }, { 203, 120 }, { 205, 121 }, +}; + +static const struct msm_pinctrl_soc_data sm8450_tlmm = { + .pins = sm8450_pins, + .npins = ARRAY_SIZE(sm8450_pins), + .functions = sm8450_functions, + .nfunctions = ARRAY_SIZE(sm8450_functions), + .groups = sm8450_groups, + .ngroups = ARRAY_SIZE(sm8450_groups), + .ngpios = 211, + .wakeirq_map = sm8450_pdc_map, + .nwakeirq_map = ARRAY_SIZE(sm8450_pdc_map), + .egpio_func = 9, +}; + +static int sm8450_tlmm_probe(struct platform_device *pdev) +{ + return msm_pinctrl_probe(pdev, &sm8450_tlmm); +} + +static const struct of_device_id sm8450_tlmm_of_match[] = { + { .compatible = "qcom,sm8450-tlmm", }, + { }, +}; + +static struct platform_driver sm8450_tlmm_driver = { + .driver = { + .name = "sm8450-tlmm", + .of_match_table = sm8450_tlmm_of_match, + }, + .probe = sm8450_tlmm_probe, + .remove = msm_pinctrl_remove, +}; + +static int __init sm8450_tlmm_init(void) +{ + return platform_driver_register(&sm8450_tlmm_driver); +} +arch_initcall(sm8450_tlmm_init); + +static void __exit sm8450_tlmm_exit(void) +{ + platform_driver_unregister(&sm8450_tlmm_driver); +} +module_exit(sm8450_tlmm_exit); + +MODULE_DESCRIPTION("QTI SM8450 TLMM driver"); +MODULE_LICENSE("GPL v2"); +MODULE_DEVICE_TABLE(of, sm8450_tlmm_of_match); diff --git a/drivers/pinctrl/qcom/pinctrl-sm8550-lpass-lpi.c b/drivers/pinctrl/qcom/pinctrl-sm8550-lpass-lpi.c new file mode 100644 index 0000000000..db1a46fee9 --- /dev/null +++ b/drivers/pinctrl/qcom/pinctrl-sm8550-lpass-lpi.c @@ -0,0 +1,248 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2022-2023 Linaro Ltd. + */ + +#include <linux/gpio/driver.h> +#include <linux/module.h> +#include <linux/platform_device.h> + +#include "pinctrl-lpass-lpi.h" + +enum lpass_lpi_functions { + LPI_MUX_dmic1_clk, + LPI_MUX_dmic1_data, + LPI_MUX_dmic2_clk, + LPI_MUX_dmic2_data, + LPI_MUX_dmic3_clk, + LPI_MUX_dmic3_data, + LPI_MUX_dmic4_clk, + LPI_MUX_dmic4_data, + LPI_MUX_i2s0_clk, + LPI_MUX_i2s0_data, + LPI_MUX_i2s0_ws, + LPI_MUX_i2s1_clk, + LPI_MUX_i2s1_data, + LPI_MUX_i2s1_ws, + LPI_MUX_i2s2_clk, + LPI_MUX_i2s2_data, + LPI_MUX_i2s2_ws, + LPI_MUX_i2s3_clk, + LPI_MUX_i2s3_data, + LPI_MUX_i2s3_ws, + LPI_MUX_i2s4_clk, + LPI_MUX_i2s4_data, + LPI_MUX_i2s4_ws, + LPI_MUX_slimbus_clk, + LPI_MUX_slimbus_data, + LPI_MUX_swr_rx_clk, + LPI_MUX_swr_rx_data, + LPI_MUX_swr_tx_clk, + LPI_MUX_swr_tx_data, + LPI_MUX_wsa_swr_clk, + LPI_MUX_wsa_swr_data, + LPI_MUX_wsa2_swr_clk, + LPI_MUX_wsa2_swr_data, + LPI_MUX_ext_mclk1_a, + LPI_MUX_ext_mclk1_b, + LPI_MUX_ext_mclk1_c, + LPI_MUX_ext_mclk1_d, + LPI_MUX_ext_mclk1_e, + LPI_MUX_gpio, + LPI_MUX__, +}; + +static int gpio0_pins[] = { 0 }; +static int gpio1_pins[] = { 1 }; +static int gpio2_pins[] = { 2 }; +static int gpio3_pins[] = { 3 }; +static int gpio4_pins[] = { 4 }; +static int gpio5_pins[] = { 5 }; +static int gpio6_pins[] = { 6 }; +static int gpio7_pins[] = { 7 }; +static int gpio8_pins[] = { 8 }; +static int gpio9_pins[] = { 9 }; +static int gpio10_pins[] = { 10 }; +static int gpio11_pins[] = { 11 }; +static int gpio12_pins[] = { 12 }; +static int gpio13_pins[] = { 13 }; +static int gpio14_pins[] = { 14 }; +static int gpio15_pins[] = { 15 }; +static int gpio16_pins[] = { 16 }; +static int gpio17_pins[] = { 17 }; +static int gpio18_pins[] = { 18 }; +static int gpio19_pins[] = { 19 }; +static int gpio20_pins[] = { 20 }; +static int gpio21_pins[] = { 21 }; +static int gpio22_pins[] = { 22 }; + +static const struct pinctrl_pin_desc sm8550_lpi_pins[] = { + PINCTRL_PIN(0, "gpio0"), + PINCTRL_PIN(1, "gpio1"), + PINCTRL_PIN(2, "gpio2"), + PINCTRL_PIN(3, "gpio3"), + PINCTRL_PIN(4, "gpio4"), + PINCTRL_PIN(5, "gpio5"), + PINCTRL_PIN(6, "gpio6"), + PINCTRL_PIN(7, "gpio7"), + PINCTRL_PIN(8, "gpio8"), + PINCTRL_PIN(9, "gpio9"), + PINCTRL_PIN(10, "gpio10"), + PINCTRL_PIN(11, "gpio11"), + PINCTRL_PIN(12, "gpio12"), + PINCTRL_PIN(13, "gpio13"), + PINCTRL_PIN(14, "gpio14"), + PINCTRL_PIN(15, "gpio15"), + PINCTRL_PIN(16, "gpio16"), + PINCTRL_PIN(17, "gpio17"), + PINCTRL_PIN(18, "gpio18"), + PINCTRL_PIN(19, "gpio19"), + PINCTRL_PIN(20, "gpio20"), + PINCTRL_PIN(21, "gpio21"), + PINCTRL_PIN(22, "gpio22"), +}; + +static const char * const gpio_groups[] = { + "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7", + "gpio8", "gpio9", "gpio10", "gpio11", "gpio12", "gpio13", "gpio14", + "gpio15", "gpio16", "gpio17", "gpio18", "gpio19", "gpio20", "gpio21", + "gpio22", +}; + +static const char * const dmic1_clk_groups[] = { "gpio6" }; +static const char * const dmic1_data_groups[] = { "gpio7" }; +static const char * const dmic2_clk_groups[] = { "gpio8" }; +static const char * const dmic2_data_groups[] = { "gpio9" }; +static const char * const dmic3_clk_groups[] = { "gpio12" }; +static const char * const dmic3_data_groups[] = { "gpio13" }; +static const char * const dmic4_clk_groups[] = { "gpio17" }; +static const char * const dmic4_data_groups[] = { "gpio18" }; +static const char * const i2s0_clk_groups[] = { "gpio0" }; +static const char * const i2s0_ws_groups[] = { "gpio1" }; +static const char * const i2s0_data_groups[] = { "gpio2", "gpio3", "gpio4", "gpio5" }; +static const char * const i2s1_clk_groups[] = { "gpio6" }; +static const char * const i2s1_ws_groups[] = { "gpio7" }; +static const char * const i2s1_data_groups[] = { "gpio8", "gpio9" }; +static const char * const i2s2_clk_groups[] = { "gpio10" }; +static const char * const i2s2_ws_groups[] = { "gpio11" }; +static const char * const i2s2_data_groups[] = { "gpio15", "gpio16" }; +static const char * const i2s3_clk_groups[] = { "gpio12" }; +static const char * const i2s3_ws_groups[] = { "gpio13" }; +static const char * const i2s3_data_groups[] = { "gpio17", "gpio18" }; +static const char * const i2s4_clk_groups[] = { "gpio19"}; +static const char * const i2s4_ws_groups[] = { "gpio20"}; +static const char * const i2s4_data_groups[] = { "gpio21", "gpio22"}; +static const char * const slimbus_clk_groups[] = { "gpio19"}; +static const char * const slimbus_data_groups[] = { "gpio20"}; +static const char * const swr_tx_clk_groups[] = { "gpio0" }; +static const char * const swr_tx_data_groups[] = { "gpio1", "gpio2", "gpio14" }; +static const char * const swr_rx_clk_groups[] = { "gpio3" }; +static const char * const swr_rx_data_groups[] = { "gpio4", "gpio5", "gpio15" }; +static const char * const wsa_swr_clk_groups[] = { "gpio10" }; +static const char * const wsa_swr_data_groups[] = { "gpio11" }; +static const char * const wsa2_swr_clk_groups[] = { "gpio15" }; +static const char * const wsa2_swr_data_groups[] = { "gpio16" }; +static const char * const ext_mclk1_c_groups[] = { "gpio5" }; +static const char * const ext_mclk1_b_groups[] = { "gpio9" }; +static const char * const ext_mclk1_a_groups[] = { "gpio13" }; +static const char * const ext_mclk1_d_groups[] = { "gpio14" }; +static const char * const ext_mclk1_e_groups[] = { "gpio22" }; + +static const struct lpi_pingroup sm8550_groups[] = { + LPI_PINGROUP(0, 0, swr_tx_clk, i2s0_clk, _, _), + LPI_PINGROUP(1, 2, swr_tx_data, i2s0_ws, _, _), + LPI_PINGROUP(2, 4, swr_tx_data, i2s0_data, _, _), + LPI_PINGROUP(3, 8, swr_rx_clk, i2s0_data, _, _), + LPI_PINGROUP(4, 10, swr_rx_data, i2s0_data, _, _), + LPI_PINGROUP(5, 12, swr_rx_data, ext_mclk1_c, i2s0_data, _), + LPI_PINGROUP(6, LPI_NO_SLEW, dmic1_clk, i2s1_clk, _, _), + LPI_PINGROUP(7, LPI_NO_SLEW, dmic1_data, i2s1_ws, _, _), + LPI_PINGROUP(8, LPI_NO_SLEW, dmic2_clk, i2s1_data, _, _), + LPI_PINGROUP(9, LPI_NO_SLEW, dmic2_data, i2s1_data, ext_mclk1_b, _), + LPI_PINGROUP(10, 16, i2s2_clk, wsa_swr_clk, _, _), + LPI_PINGROUP(11, 18, i2s2_ws, wsa_swr_data, _, _), + LPI_PINGROUP(12, LPI_NO_SLEW, dmic3_clk, i2s3_clk, _, _), + LPI_PINGROUP(13, LPI_NO_SLEW, dmic3_data, i2s3_ws, ext_mclk1_a, _), + LPI_PINGROUP(14, 6, swr_tx_data, ext_mclk1_d, _, _), + LPI_PINGROUP(15, 20, i2s2_data, wsa2_swr_clk, _, _), + LPI_PINGROUP(16, 22, i2s2_data, wsa2_swr_data, _, _), + LPI_PINGROUP(17, LPI_NO_SLEW, dmic4_clk, i2s3_data, _, _), + LPI_PINGROUP(18, LPI_NO_SLEW, dmic4_data, i2s3_data, _, _), + LPI_PINGROUP(19, LPI_NO_SLEW, i2s4_clk, slimbus_clk, _, _), + LPI_PINGROUP(20, LPI_NO_SLEW, i2s4_ws, slimbus_data, _, _), + LPI_PINGROUP(21, LPI_NO_SLEW, i2s4_data, _, _, _), + LPI_PINGROUP(22, LPI_NO_SLEW, i2s4_data, ext_mclk1_e, _, _), +}; + +static const struct lpi_function sm8550_functions[] = { + LPI_FUNCTION(gpio), + LPI_FUNCTION(dmic1_clk), + LPI_FUNCTION(dmic1_data), + LPI_FUNCTION(dmic2_clk), + LPI_FUNCTION(dmic2_data), + LPI_FUNCTION(dmic3_clk), + LPI_FUNCTION(dmic3_data), + LPI_FUNCTION(dmic4_clk), + LPI_FUNCTION(dmic4_data), + LPI_FUNCTION(i2s0_clk), + LPI_FUNCTION(i2s0_data), + LPI_FUNCTION(i2s0_ws), + LPI_FUNCTION(i2s1_clk), + LPI_FUNCTION(i2s1_data), + LPI_FUNCTION(i2s1_ws), + LPI_FUNCTION(i2s2_clk), + LPI_FUNCTION(i2s2_data), + LPI_FUNCTION(i2s2_ws), + LPI_FUNCTION(i2s3_clk), + LPI_FUNCTION(i2s3_data), + LPI_FUNCTION(i2s3_ws), + LPI_FUNCTION(i2s4_clk), + LPI_FUNCTION(i2s4_data), + LPI_FUNCTION(i2s4_ws), + LPI_FUNCTION(slimbus_clk), + LPI_FUNCTION(slimbus_data), + LPI_FUNCTION(swr_rx_clk), + LPI_FUNCTION(swr_rx_data), + LPI_FUNCTION(swr_tx_clk), + LPI_FUNCTION(swr_tx_data), + LPI_FUNCTION(wsa_swr_clk), + LPI_FUNCTION(wsa_swr_data), + LPI_FUNCTION(wsa2_swr_clk), + LPI_FUNCTION(wsa2_swr_data), + LPI_FUNCTION(ext_mclk1_a), + LPI_FUNCTION(ext_mclk1_b), + LPI_FUNCTION(ext_mclk1_c), + LPI_FUNCTION(ext_mclk1_d), + LPI_FUNCTION(ext_mclk1_e), +}; + +static const struct lpi_pinctrl_variant_data sm8550_lpi_data = { + .pins = sm8550_lpi_pins, + .npins = ARRAY_SIZE(sm8550_lpi_pins), + .groups = sm8550_groups, + .ngroups = ARRAY_SIZE(sm8550_groups), + .functions = sm8550_functions, + .nfunctions = ARRAY_SIZE(sm8550_functions), +}; + +static const struct of_device_id lpi_pinctrl_of_match[] = { + { + .compatible = "qcom,sm8550-lpass-lpi-pinctrl", + .data = &sm8550_lpi_data, + }, + { } +}; +MODULE_DEVICE_TABLE(of, lpi_pinctrl_of_match); + +static struct platform_driver lpi_pinctrl_driver = { + .driver = { + .name = "qcom-sm8550-lpass-lpi-pinctrl", + .of_match_table = lpi_pinctrl_of_match, + }, + .probe = lpi_pinctrl_probe, + .remove = lpi_pinctrl_remove, +}; + +module_platform_driver(lpi_pinctrl_driver); +MODULE_DESCRIPTION("Qualcomm SM8550 LPI GPIO pin control driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/pinctrl/qcom/pinctrl-sm8550.c b/drivers/pinctrl/qcom/pinctrl-sm8550.c new file mode 100644 index 0000000000..3c847d9cb5 --- /dev/null +++ b/drivers/pinctrl/qcom/pinctrl-sm8550.c @@ -0,0 +1,1782 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2021, The Linux Foundation. All rights reserved. + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2022, Linaro Limited + */ + +#include <linux/module.h> +#include <linux/of.h> +#include <linux/platform_device.h> + +#include "pinctrl-msm.h" + +#define REG_SIZE 0x1000 + +#define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7, f8, f9) \ + { \ + .grp = PINCTRL_PINGROUP("gpio" #id, \ + gpio##id##_pins, \ + ARRAY_SIZE(gpio##id##_pins)), \ + .funcs = (int[]){ \ + msm_mux_gpio, /* gpio mode */ \ + msm_mux_##f1, \ + msm_mux_##f2, \ + msm_mux_##f3, \ + msm_mux_##f4, \ + msm_mux_##f5, \ + msm_mux_##f6, \ + msm_mux_##f7, \ + msm_mux_##f8, \ + msm_mux_##f9 \ + }, \ + .nfuncs = 10, \ + .ctl_reg = REG_SIZE * id, \ + .io_reg = 0x4 + REG_SIZE * id, \ + .intr_cfg_reg = 0x8 + REG_SIZE * id, \ + .intr_status_reg = 0xc + REG_SIZE * id, \ + .intr_target_reg = 0x8 + REG_SIZE * id, \ + .mux_bit = 2, \ + .pull_bit = 0, \ + .drv_bit = 6, \ + .i2c_pull_bit = 13, \ + .egpio_enable = 12, \ + .egpio_present = 11, \ + .oe_bit = 9, \ + .in_bit = 0, \ + .out_bit = 1, \ + .intr_enable_bit = 0, \ + .intr_status_bit = 0, \ + .intr_target_bit = 5, \ + .intr_target_kpss_val = 3, \ + .intr_raw_status_bit = 4, \ + .intr_polarity_bit = 1, \ + .intr_detection_bit = 2, \ + .intr_detection_width = 2, \ + } + +#define SDC_QDSD_PINGROUP(pg_name, ctl, pull, drv) \ + { \ + .grp = PINCTRL_PINGROUP(#pg_name, \ + pg_name##_pins, \ + ARRAY_SIZE(pg_name##_pins)), \ + .ctl_reg = ctl, \ + .io_reg = 0, \ + .intr_cfg_reg = 0, \ + .intr_status_reg = 0, \ + .intr_target_reg = 0, \ + .mux_bit = -1, \ + .pull_bit = pull, \ + .drv_bit = drv, \ + .oe_bit = -1, \ + .in_bit = -1, \ + .out_bit = -1, \ + .intr_enable_bit = -1, \ + .intr_status_bit = -1, \ + .intr_target_bit = -1, \ + .intr_raw_status_bit = -1, \ + .intr_polarity_bit = -1, \ + .intr_detection_bit = -1, \ + .intr_detection_width = -1, \ + } + +#define UFS_RESET(pg_name, offset) \ + { \ + .grp = PINCTRL_PINGROUP(#pg_name, \ + pg_name##_pins, \ + ARRAY_SIZE(pg_name##_pins)), \ + .ctl_reg = offset, \ + .io_reg = offset + 0x4, \ + .intr_cfg_reg = 0, \ + .intr_status_reg = 0, \ + .intr_target_reg = 0, \ + .mux_bit = -1, \ + .pull_bit = 3, \ + .drv_bit = 0, \ + .oe_bit = -1, \ + .in_bit = -1, \ + .out_bit = 0, \ + .intr_enable_bit = -1, \ + .intr_status_bit = -1, \ + .intr_target_bit = -1, \ + .intr_raw_status_bit = -1, \ + .intr_polarity_bit = -1, \ + .intr_detection_bit = -1, \ + .intr_detection_width = -1, \ + } + +static const struct pinctrl_pin_desc sm8550_pins[] = { + PINCTRL_PIN(0, "GPIO_0"), + PINCTRL_PIN(1, "GPIO_1"), + PINCTRL_PIN(2, "GPIO_2"), + PINCTRL_PIN(3, "GPIO_3"), + PINCTRL_PIN(4, "GPIO_4"), + PINCTRL_PIN(5, "GPIO_5"), + PINCTRL_PIN(6, "GPIO_6"), + PINCTRL_PIN(7, "GPIO_7"), + PINCTRL_PIN(8, "GPIO_8"), + PINCTRL_PIN(9, "GPIO_9"), + PINCTRL_PIN(10, "GPIO_10"), + PINCTRL_PIN(11, "GPIO_11"), + PINCTRL_PIN(12, "GPIO_12"), + PINCTRL_PIN(13, "GPIO_13"), + PINCTRL_PIN(14, "GPIO_14"), + PINCTRL_PIN(15, "GPIO_15"), + PINCTRL_PIN(16, "GPIO_16"), + PINCTRL_PIN(17, "GPIO_17"), + PINCTRL_PIN(18, "GPIO_18"), + PINCTRL_PIN(19, "GPIO_19"), + PINCTRL_PIN(20, "GPIO_20"), + PINCTRL_PIN(21, "GPIO_21"), + PINCTRL_PIN(22, "GPIO_22"), + PINCTRL_PIN(23, "GPIO_23"), + PINCTRL_PIN(24, "GPIO_24"), + PINCTRL_PIN(25, "GPIO_25"), + PINCTRL_PIN(26, "GPIO_26"), + PINCTRL_PIN(27, "GPIO_27"), + PINCTRL_PIN(28, "GPIO_28"), + PINCTRL_PIN(29, "GPIO_29"), + PINCTRL_PIN(30, "GPIO_30"), + PINCTRL_PIN(31, "GPIO_31"), + PINCTRL_PIN(32, "GPIO_32"), + PINCTRL_PIN(33, "GPIO_33"), + PINCTRL_PIN(34, "GPIO_34"), + PINCTRL_PIN(35, "GPIO_35"), + PINCTRL_PIN(36, "GPIO_36"), + PINCTRL_PIN(37, "GPIO_37"), + PINCTRL_PIN(38, "GPIO_38"), + PINCTRL_PIN(39, "GPIO_39"), + PINCTRL_PIN(40, "GPIO_40"), + PINCTRL_PIN(41, "GPIO_41"), + PINCTRL_PIN(42, "GPIO_42"), + PINCTRL_PIN(43, "GPIO_43"), + PINCTRL_PIN(44, "GPIO_44"), + PINCTRL_PIN(45, "GPIO_45"), + PINCTRL_PIN(46, "GPIO_46"), + PINCTRL_PIN(47, "GPIO_47"), + PINCTRL_PIN(48, "GPIO_48"), + PINCTRL_PIN(49, "GPIO_49"), + PINCTRL_PIN(50, "GPIO_50"), + PINCTRL_PIN(51, "GPIO_51"), + PINCTRL_PIN(52, "GPIO_52"), + PINCTRL_PIN(53, "GPIO_53"), + PINCTRL_PIN(54, "GPIO_54"), + PINCTRL_PIN(55, "GPIO_55"), + PINCTRL_PIN(56, "GPIO_56"), + PINCTRL_PIN(57, "GPIO_57"), + PINCTRL_PIN(58, "GPIO_58"), + PINCTRL_PIN(59, "GPIO_59"), + PINCTRL_PIN(60, "GPIO_60"), + PINCTRL_PIN(61, "GPIO_61"), + PINCTRL_PIN(62, "GPIO_62"), + PINCTRL_PIN(63, "GPIO_63"), + PINCTRL_PIN(64, "GPIO_64"), + PINCTRL_PIN(65, "GPIO_65"), + PINCTRL_PIN(66, "GPIO_66"), + PINCTRL_PIN(67, "GPIO_67"), + PINCTRL_PIN(68, "GPIO_68"), + PINCTRL_PIN(69, "GPIO_69"), + PINCTRL_PIN(70, "GPIO_70"), + PINCTRL_PIN(71, "GPIO_71"), + PINCTRL_PIN(72, "GPIO_72"), + PINCTRL_PIN(73, "GPIO_73"), + PINCTRL_PIN(74, "GPIO_74"), + PINCTRL_PIN(75, "GPIO_75"), + PINCTRL_PIN(76, "GPIO_76"), + PINCTRL_PIN(77, "GPIO_77"), + PINCTRL_PIN(78, "GPIO_78"), + PINCTRL_PIN(79, "GPIO_79"), + PINCTRL_PIN(80, "GPIO_80"), + PINCTRL_PIN(81, "GPIO_81"), + PINCTRL_PIN(82, "GPIO_82"), + PINCTRL_PIN(83, "GPIO_83"), + PINCTRL_PIN(84, "GPIO_84"), + PINCTRL_PIN(85, "GPIO_85"), + PINCTRL_PIN(86, "GPIO_86"), + PINCTRL_PIN(87, "GPIO_87"), + PINCTRL_PIN(88, "GPIO_88"), + PINCTRL_PIN(89, "GPIO_89"), + PINCTRL_PIN(90, "GPIO_90"), + PINCTRL_PIN(91, "GPIO_91"), + PINCTRL_PIN(92, "GPIO_92"), + PINCTRL_PIN(93, "GPIO_93"), + PINCTRL_PIN(94, "GPIO_94"), + PINCTRL_PIN(95, "GPIO_95"), + PINCTRL_PIN(96, "GPIO_96"), + PINCTRL_PIN(97, "GPIO_97"), + PINCTRL_PIN(98, "GPIO_98"), + PINCTRL_PIN(99, "GPIO_99"), + PINCTRL_PIN(100, "GPIO_100"), + PINCTRL_PIN(101, "GPIO_101"), + PINCTRL_PIN(102, "GPIO_102"), + PINCTRL_PIN(103, "GPIO_103"), + PINCTRL_PIN(104, "GPIO_104"), + PINCTRL_PIN(105, "GPIO_105"), + PINCTRL_PIN(106, "GPIO_106"), + PINCTRL_PIN(107, "GPIO_107"), + PINCTRL_PIN(108, "GPIO_108"), + PINCTRL_PIN(109, "GPIO_109"), + PINCTRL_PIN(110, "GPIO_110"), + PINCTRL_PIN(111, "GPIO_111"), + PINCTRL_PIN(112, "GPIO_112"), + PINCTRL_PIN(113, "GPIO_113"), + PINCTRL_PIN(114, "GPIO_114"), + PINCTRL_PIN(115, "GPIO_115"), + PINCTRL_PIN(116, "GPIO_116"), + PINCTRL_PIN(117, "GPIO_117"), + PINCTRL_PIN(118, "GPIO_118"), + PINCTRL_PIN(119, "GPIO_119"), + PINCTRL_PIN(120, "GPIO_120"), + PINCTRL_PIN(121, "GPIO_121"), + PINCTRL_PIN(122, "GPIO_122"), + PINCTRL_PIN(123, "GPIO_123"), + PINCTRL_PIN(124, "GPIO_124"), + PINCTRL_PIN(125, "GPIO_125"), + PINCTRL_PIN(126, "GPIO_126"), + PINCTRL_PIN(127, "GPIO_127"), + PINCTRL_PIN(128, "GPIO_128"), + PINCTRL_PIN(129, "GPIO_129"), + PINCTRL_PIN(130, "GPIO_130"), + PINCTRL_PIN(131, "GPIO_131"), + PINCTRL_PIN(132, "GPIO_132"), + PINCTRL_PIN(133, "GPIO_133"), + PINCTRL_PIN(134, "GPIO_134"), + PINCTRL_PIN(135, "GPIO_135"), + PINCTRL_PIN(136, "GPIO_136"), + PINCTRL_PIN(137, "GPIO_137"), + PINCTRL_PIN(138, "GPIO_138"), + PINCTRL_PIN(139, "GPIO_139"), + PINCTRL_PIN(140, "GPIO_140"), + PINCTRL_PIN(141, "GPIO_141"), + PINCTRL_PIN(142, "GPIO_142"), + PINCTRL_PIN(143, "GPIO_143"), + PINCTRL_PIN(144, "GPIO_144"), + PINCTRL_PIN(145, "GPIO_145"), + PINCTRL_PIN(146, "GPIO_146"), + PINCTRL_PIN(147, "GPIO_147"), + PINCTRL_PIN(148, "GPIO_148"), + PINCTRL_PIN(149, "GPIO_149"), + PINCTRL_PIN(150, "GPIO_150"), + PINCTRL_PIN(151, "GPIO_151"), + PINCTRL_PIN(152, "GPIO_152"), + PINCTRL_PIN(153, "GPIO_153"), + PINCTRL_PIN(154, "GPIO_154"), + PINCTRL_PIN(155, "GPIO_155"), + PINCTRL_PIN(156, "GPIO_156"), + PINCTRL_PIN(157, "GPIO_157"), + PINCTRL_PIN(158, "GPIO_158"), + PINCTRL_PIN(159, "GPIO_159"), + PINCTRL_PIN(160, "GPIO_160"), + PINCTRL_PIN(161, "GPIO_161"), + PINCTRL_PIN(162, "GPIO_162"), + PINCTRL_PIN(163, "GPIO_163"), + PINCTRL_PIN(164, "GPIO_164"), + PINCTRL_PIN(165, "GPIO_165"), + PINCTRL_PIN(166, "GPIO_166"), + PINCTRL_PIN(167, "GPIO_167"), + PINCTRL_PIN(168, "GPIO_168"), + PINCTRL_PIN(169, "GPIO_169"), + PINCTRL_PIN(170, "GPIO_170"), + PINCTRL_PIN(171, "GPIO_171"), + PINCTRL_PIN(172, "GPIO_172"), + PINCTRL_PIN(173, "GPIO_173"), + PINCTRL_PIN(174, "GPIO_174"), + PINCTRL_PIN(175, "GPIO_175"), + PINCTRL_PIN(176, "GPIO_176"), + PINCTRL_PIN(177, "GPIO_177"), + PINCTRL_PIN(178, "GPIO_178"), + PINCTRL_PIN(179, "GPIO_179"), + PINCTRL_PIN(180, "GPIO_180"), + PINCTRL_PIN(181, "GPIO_181"), + PINCTRL_PIN(182, "GPIO_182"), + PINCTRL_PIN(183, "GPIO_183"), + PINCTRL_PIN(184, "GPIO_184"), + PINCTRL_PIN(185, "GPIO_185"), + PINCTRL_PIN(186, "GPIO_186"), + PINCTRL_PIN(187, "GPIO_187"), + PINCTRL_PIN(188, "GPIO_188"), + PINCTRL_PIN(189, "GPIO_189"), + PINCTRL_PIN(190, "GPIO_190"), + PINCTRL_PIN(191, "GPIO_191"), + PINCTRL_PIN(192, "GPIO_192"), + PINCTRL_PIN(193, "GPIO_193"), + PINCTRL_PIN(194, "GPIO_194"), + PINCTRL_PIN(195, "GPIO_195"), + PINCTRL_PIN(196, "GPIO_196"), + PINCTRL_PIN(197, "GPIO_197"), + PINCTRL_PIN(198, "GPIO_198"), + PINCTRL_PIN(199, "GPIO_199"), + PINCTRL_PIN(200, "GPIO_200"), + PINCTRL_PIN(201, "GPIO_201"), + PINCTRL_PIN(202, "GPIO_202"), + PINCTRL_PIN(203, "GPIO_203"), + PINCTRL_PIN(204, "GPIO_204"), + PINCTRL_PIN(205, "GPIO_205"), + PINCTRL_PIN(206, "GPIO_206"), + PINCTRL_PIN(207, "GPIO_207"), + PINCTRL_PIN(208, "GPIO_208"), + PINCTRL_PIN(209, "GPIO_209"), + PINCTRL_PIN(210, "UFS_RESET"), + PINCTRL_PIN(211, "SDC2_CLK"), + PINCTRL_PIN(212, "SDC2_CMD"), + PINCTRL_PIN(213, "SDC2_DATA"), +}; + +#define DECLARE_MSM_GPIO_PINS(pin) \ + static const unsigned int gpio##pin##_pins[] = { pin } +DECLARE_MSM_GPIO_PINS(0); +DECLARE_MSM_GPIO_PINS(1); +DECLARE_MSM_GPIO_PINS(2); +DECLARE_MSM_GPIO_PINS(3); +DECLARE_MSM_GPIO_PINS(4); +DECLARE_MSM_GPIO_PINS(5); +DECLARE_MSM_GPIO_PINS(6); +DECLARE_MSM_GPIO_PINS(7); +DECLARE_MSM_GPIO_PINS(8); +DECLARE_MSM_GPIO_PINS(9); +DECLARE_MSM_GPIO_PINS(10); +DECLARE_MSM_GPIO_PINS(11); +DECLARE_MSM_GPIO_PINS(12); +DECLARE_MSM_GPIO_PINS(13); +DECLARE_MSM_GPIO_PINS(14); +DECLARE_MSM_GPIO_PINS(15); +DECLARE_MSM_GPIO_PINS(16); +DECLARE_MSM_GPIO_PINS(17); +DECLARE_MSM_GPIO_PINS(18); +DECLARE_MSM_GPIO_PINS(19); +DECLARE_MSM_GPIO_PINS(20); +DECLARE_MSM_GPIO_PINS(21); +DECLARE_MSM_GPIO_PINS(22); +DECLARE_MSM_GPIO_PINS(23); +DECLARE_MSM_GPIO_PINS(24); +DECLARE_MSM_GPIO_PINS(25); +DECLARE_MSM_GPIO_PINS(26); +DECLARE_MSM_GPIO_PINS(27); +DECLARE_MSM_GPIO_PINS(28); +DECLARE_MSM_GPIO_PINS(29); +DECLARE_MSM_GPIO_PINS(30); +DECLARE_MSM_GPIO_PINS(31); +DECLARE_MSM_GPIO_PINS(32); +DECLARE_MSM_GPIO_PINS(33); +DECLARE_MSM_GPIO_PINS(34); +DECLARE_MSM_GPIO_PINS(35); +DECLARE_MSM_GPIO_PINS(36); +DECLARE_MSM_GPIO_PINS(37); +DECLARE_MSM_GPIO_PINS(38); +DECLARE_MSM_GPIO_PINS(39); +DECLARE_MSM_GPIO_PINS(40); +DECLARE_MSM_GPIO_PINS(41); +DECLARE_MSM_GPIO_PINS(42); +DECLARE_MSM_GPIO_PINS(43); +DECLARE_MSM_GPIO_PINS(44); +DECLARE_MSM_GPIO_PINS(45); +DECLARE_MSM_GPIO_PINS(46); +DECLARE_MSM_GPIO_PINS(47); +DECLARE_MSM_GPIO_PINS(48); +DECLARE_MSM_GPIO_PINS(49); +DECLARE_MSM_GPIO_PINS(50); +DECLARE_MSM_GPIO_PINS(51); +DECLARE_MSM_GPIO_PINS(52); +DECLARE_MSM_GPIO_PINS(53); +DECLARE_MSM_GPIO_PINS(54); +DECLARE_MSM_GPIO_PINS(55); +DECLARE_MSM_GPIO_PINS(56); +DECLARE_MSM_GPIO_PINS(57); +DECLARE_MSM_GPIO_PINS(58); +DECLARE_MSM_GPIO_PINS(59); +DECLARE_MSM_GPIO_PINS(60); +DECLARE_MSM_GPIO_PINS(61); +DECLARE_MSM_GPIO_PINS(62); +DECLARE_MSM_GPIO_PINS(63); +DECLARE_MSM_GPIO_PINS(64); +DECLARE_MSM_GPIO_PINS(65); +DECLARE_MSM_GPIO_PINS(66); +DECLARE_MSM_GPIO_PINS(67); +DECLARE_MSM_GPIO_PINS(68); +DECLARE_MSM_GPIO_PINS(69); +DECLARE_MSM_GPIO_PINS(70); +DECLARE_MSM_GPIO_PINS(71); +DECLARE_MSM_GPIO_PINS(72); +DECLARE_MSM_GPIO_PINS(73); +DECLARE_MSM_GPIO_PINS(74); +DECLARE_MSM_GPIO_PINS(75); +DECLARE_MSM_GPIO_PINS(76); +DECLARE_MSM_GPIO_PINS(77); +DECLARE_MSM_GPIO_PINS(78); +DECLARE_MSM_GPIO_PINS(79); +DECLARE_MSM_GPIO_PINS(80); +DECLARE_MSM_GPIO_PINS(81); +DECLARE_MSM_GPIO_PINS(82); +DECLARE_MSM_GPIO_PINS(83); +DECLARE_MSM_GPIO_PINS(84); +DECLARE_MSM_GPIO_PINS(85); +DECLARE_MSM_GPIO_PINS(86); +DECLARE_MSM_GPIO_PINS(87); +DECLARE_MSM_GPIO_PINS(88); +DECLARE_MSM_GPIO_PINS(89); +DECLARE_MSM_GPIO_PINS(90); +DECLARE_MSM_GPIO_PINS(91); +DECLARE_MSM_GPIO_PINS(92); +DECLARE_MSM_GPIO_PINS(93); +DECLARE_MSM_GPIO_PINS(94); +DECLARE_MSM_GPIO_PINS(95); +DECLARE_MSM_GPIO_PINS(96); +DECLARE_MSM_GPIO_PINS(97); +DECLARE_MSM_GPIO_PINS(98); +DECLARE_MSM_GPIO_PINS(99); +DECLARE_MSM_GPIO_PINS(100); +DECLARE_MSM_GPIO_PINS(101); +DECLARE_MSM_GPIO_PINS(102); +DECLARE_MSM_GPIO_PINS(103); +DECLARE_MSM_GPIO_PINS(104); +DECLARE_MSM_GPIO_PINS(105); +DECLARE_MSM_GPIO_PINS(106); +DECLARE_MSM_GPIO_PINS(107); +DECLARE_MSM_GPIO_PINS(108); +DECLARE_MSM_GPIO_PINS(109); +DECLARE_MSM_GPIO_PINS(110); +DECLARE_MSM_GPIO_PINS(111); +DECLARE_MSM_GPIO_PINS(112); +DECLARE_MSM_GPIO_PINS(113); +DECLARE_MSM_GPIO_PINS(114); +DECLARE_MSM_GPIO_PINS(115); +DECLARE_MSM_GPIO_PINS(116); +DECLARE_MSM_GPIO_PINS(117); +DECLARE_MSM_GPIO_PINS(118); +DECLARE_MSM_GPIO_PINS(119); +DECLARE_MSM_GPIO_PINS(120); +DECLARE_MSM_GPIO_PINS(121); +DECLARE_MSM_GPIO_PINS(122); +DECLARE_MSM_GPIO_PINS(123); +DECLARE_MSM_GPIO_PINS(124); +DECLARE_MSM_GPIO_PINS(125); +DECLARE_MSM_GPIO_PINS(126); +DECLARE_MSM_GPIO_PINS(127); +DECLARE_MSM_GPIO_PINS(128); +DECLARE_MSM_GPIO_PINS(129); +DECLARE_MSM_GPIO_PINS(130); +DECLARE_MSM_GPIO_PINS(131); +DECLARE_MSM_GPIO_PINS(132); +DECLARE_MSM_GPIO_PINS(133); +DECLARE_MSM_GPIO_PINS(134); +DECLARE_MSM_GPIO_PINS(135); +DECLARE_MSM_GPIO_PINS(136); +DECLARE_MSM_GPIO_PINS(137); +DECLARE_MSM_GPIO_PINS(138); +DECLARE_MSM_GPIO_PINS(139); +DECLARE_MSM_GPIO_PINS(140); +DECLARE_MSM_GPIO_PINS(141); +DECLARE_MSM_GPIO_PINS(142); +DECLARE_MSM_GPIO_PINS(143); +DECLARE_MSM_GPIO_PINS(144); +DECLARE_MSM_GPIO_PINS(145); +DECLARE_MSM_GPIO_PINS(146); +DECLARE_MSM_GPIO_PINS(147); +DECLARE_MSM_GPIO_PINS(148); +DECLARE_MSM_GPIO_PINS(149); +DECLARE_MSM_GPIO_PINS(150); +DECLARE_MSM_GPIO_PINS(151); +DECLARE_MSM_GPIO_PINS(152); +DECLARE_MSM_GPIO_PINS(153); +DECLARE_MSM_GPIO_PINS(154); +DECLARE_MSM_GPIO_PINS(155); +DECLARE_MSM_GPIO_PINS(156); +DECLARE_MSM_GPIO_PINS(157); +DECLARE_MSM_GPIO_PINS(158); +DECLARE_MSM_GPIO_PINS(159); +DECLARE_MSM_GPIO_PINS(160); +DECLARE_MSM_GPIO_PINS(161); +DECLARE_MSM_GPIO_PINS(162); +DECLARE_MSM_GPIO_PINS(163); +DECLARE_MSM_GPIO_PINS(164); +DECLARE_MSM_GPIO_PINS(165); +DECLARE_MSM_GPIO_PINS(166); +DECLARE_MSM_GPIO_PINS(167); +DECLARE_MSM_GPIO_PINS(168); +DECLARE_MSM_GPIO_PINS(169); +DECLARE_MSM_GPIO_PINS(170); +DECLARE_MSM_GPIO_PINS(171); +DECLARE_MSM_GPIO_PINS(172); +DECLARE_MSM_GPIO_PINS(173); +DECLARE_MSM_GPIO_PINS(174); +DECLARE_MSM_GPIO_PINS(175); +DECLARE_MSM_GPIO_PINS(176); +DECLARE_MSM_GPIO_PINS(177); +DECLARE_MSM_GPIO_PINS(178); +DECLARE_MSM_GPIO_PINS(179); +DECLARE_MSM_GPIO_PINS(180); +DECLARE_MSM_GPIO_PINS(181); +DECLARE_MSM_GPIO_PINS(182); +DECLARE_MSM_GPIO_PINS(183); +DECLARE_MSM_GPIO_PINS(184); +DECLARE_MSM_GPIO_PINS(185); +DECLARE_MSM_GPIO_PINS(186); +DECLARE_MSM_GPIO_PINS(187); +DECLARE_MSM_GPIO_PINS(188); +DECLARE_MSM_GPIO_PINS(189); +DECLARE_MSM_GPIO_PINS(190); +DECLARE_MSM_GPIO_PINS(191); +DECLARE_MSM_GPIO_PINS(192); +DECLARE_MSM_GPIO_PINS(193); +DECLARE_MSM_GPIO_PINS(194); +DECLARE_MSM_GPIO_PINS(195); +DECLARE_MSM_GPIO_PINS(196); +DECLARE_MSM_GPIO_PINS(197); +DECLARE_MSM_GPIO_PINS(198); +DECLARE_MSM_GPIO_PINS(199); +DECLARE_MSM_GPIO_PINS(200); +DECLARE_MSM_GPIO_PINS(201); +DECLARE_MSM_GPIO_PINS(202); +DECLARE_MSM_GPIO_PINS(203); +DECLARE_MSM_GPIO_PINS(204); +DECLARE_MSM_GPIO_PINS(205); +DECLARE_MSM_GPIO_PINS(206); +DECLARE_MSM_GPIO_PINS(207); +DECLARE_MSM_GPIO_PINS(208); +DECLARE_MSM_GPIO_PINS(209); + +static const unsigned int ufs_reset_pins[] = { 210 }; +static const unsigned int sdc2_clk_pins[] = { 211 }; +static const unsigned int sdc2_cmd_pins[] = { 212 }; +static const unsigned int sdc2_data_pins[] = { 213 }; + +enum sm8550_functions { + msm_mux_gpio, + msm_mux_aon_cci, + msm_mux_aoss_cti, + msm_mux_atest_char, + msm_mux_atest_usb, + msm_mux_audio_ext_mclk0, + msm_mux_audio_ext_mclk1, + msm_mux_audio_ref_clk, + msm_mux_cam_aon_mclk4, + msm_mux_cam_mclk, + msm_mux_cci_async_in, + msm_mux_cci_i2c_scl, + msm_mux_cci_i2c_sda, + msm_mux_cci_timer, + msm_mux_cmu_rng, + msm_mux_coex_uart1_rx, + msm_mux_coex_uart1_tx, + msm_mux_coex_uart2_rx, + msm_mux_coex_uart2_tx, + msm_mux_cri_trng, + msm_mux_dbg_out_clk, + msm_mux_ddr_bist_complete, + msm_mux_ddr_bist_fail, + msm_mux_ddr_bist_start, + msm_mux_ddr_bist_stop, + msm_mux_ddr_pxi0, + msm_mux_ddr_pxi1, + msm_mux_ddr_pxi2, + msm_mux_ddr_pxi3, + msm_mux_dp_hot, + msm_mux_gcc_gp1, + msm_mux_gcc_gp2, + msm_mux_gcc_gp3, + msm_mux_i2chub0_se0, + msm_mux_i2chub0_se1, + msm_mux_i2chub0_se2, + msm_mux_i2chub0_se3, + msm_mux_i2chub0_se4, + msm_mux_i2chub0_se5, + msm_mux_i2chub0_se6, + msm_mux_i2chub0_se7, + msm_mux_i2chub0_se8, + msm_mux_i2chub0_se9, + msm_mux_i2s0_data0, + msm_mux_i2s0_data1, + msm_mux_i2s0_sck, + msm_mux_i2s0_ws, + msm_mux_i2s1_data0, + msm_mux_i2s1_data1, + msm_mux_i2s1_sck, + msm_mux_i2s1_ws, + msm_mux_ibi_i3c, + msm_mux_jitter_bist, + msm_mux_mdp_vsync, + msm_mux_mdp_vsync0_out, + msm_mux_mdp_vsync1_out, + msm_mux_mdp_vsync2_out, + msm_mux_mdp_vsync3_out, + msm_mux_mdp_vsync_e, + msm_mux_nav_gpio0, + msm_mux_nav_gpio1, + msm_mux_nav_gpio2, + msm_mux_pcie0_clk_req_n, + msm_mux_pcie1_clk_req_n, + msm_mux_phase_flag, + msm_mux_pll_bist_sync, + msm_mux_pll_clk_aux, + msm_mux_prng_rosc0, + msm_mux_prng_rosc1, + msm_mux_prng_rosc2, + msm_mux_prng_rosc3, + msm_mux_qdss_cti, + msm_mux_qdss_gpio, + msm_mux_qlink0_enable, + msm_mux_qlink0_request, + msm_mux_qlink0_wmss, + msm_mux_qlink1_enable, + msm_mux_qlink1_request, + msm_mux_qlink1_wmss, + msm_mux_qlink2_enable, + msm_mux_qlink2_request, + msm_mux_qlink2_wmss, + msm_mux_qspi0, + msm_mux_qspi1, + msm_mux_qspi2, + msm_mux_qspi3, + msm_mux_qspi_clk, + msm_mux_qspi_cs, + msm_mux_qup1_se0, + msm_mux_qup1_se1, + msm_mux_qup1_se2, + msm_mux_qup1_se3, + msm_mux_qup1_se4, + msm_mux_qup1_se5, + msm_mux_qup1_se6, + msm_mux_qup1_se7, + msm_mux_qup2_se0, + msm_mux_qup2_se0_l0_mira, + msm_mux_qup2_se0_l0_mirb, + msm_mux_qup2_se0_l1_mira, + msm_mux_qup2_se0_l1_mirb, + msm_mux_qup2_se0_l2_mira, + msm_mux_qup2_se0_l2_mirb, + msm_mux_qup2_se0_l3_mira, + msm_mux_qup2_se0_l3_mirb, + msm_mux_qup2_se1, + msm_mux_qup2_se2, + msm_mux_qup2_se3, + msm_mux_qup2_se4, + msm_mux_qup2_se5, + msm_mux_qup2_se6, + msm_mux_qup2_se7, + msm_mux_resout_n, + msm_mux_sd_write_protect, + msm_mux_sdc40, + msm_mux_sdc41, + msm_mux_sdc42, + msm_mux_sdc43, + msm_mux_sdc4_clk, + msm_mux_sdc4_cmd, + msm_mux_tb_trig_sdc2, + msm_mux_tb_trig_sdc4, + msm_mux_tgu_ch0_trigout, + msm_mux_tgu_ch1_trigout, + msm_mux_tgu_ch2_trigout, + msm_mux_tgu_ch3_trigout, + msm_mux_tmess_prng0, + msm_mux_tmess_prng1, + msm_mux_tmess_prng2, + msm_mux_tmess_prng3, + msm_mux_tsense_pwm1, + msm_mux_tsense_pwm2, + msm_mux_tsense_pwm3, + msm_mux_uim0_clk, + msm_mux_uim0_data, + msm_mux_uim0_present, + msm_mux_uim0_reset, + msm_mux_uim1_clk, + msm_mux_uim1_data, + msm_mux_uim1_present, + msm_mux_uim1_reset, + msm_mux_usb1_hs, + msm_mux_usb_phy, + msm_mux_vfr_0, + msm_mux_vfr_1, + msm_mux_vsense_trigger_mirnat, + msm_mux__, +}; + +static const char * const gpio_groups[] = { + "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7", + "gpio8", "gpio9", "gpio10", "gpio11", "gpio12", "gpio13", "gpio14", + "gpio15", "gpio16", "gpio17", "gpio18", "gpio19", "gpio20", "gpio21", + "gpio22", "gpio23", "gpio24", "gpio25", "gpio26", "gpio27", "gpio28", + "gpio29", "gpio30", "gpio31", "gpio32", "gpio33", "gpio34", "gpio35", + "gpio36", "gpio37", "gpio38", "gpio39", "gpio40", "gpio41", "gpio42", + "gpio43", "gpio44", "gpio45", "gpio46", "gpio47", "gpio48", "gpio49", + "gpio50", "gpio51", "gpio52", "gpio53", "gpio54", "gpio55", "gpio56", + "gpio57", "gpio58", "gpio59", "gpio60", "gpio61", "gpio62", "gpio63", + "gpio64", "gpio65", "gpio66", "gpio67", "gpio68", "gpio69", "gpio70", + "gpio71", "gpio72", "gpio73", "gpio74", "gpio75", "gpio76", "gpio77", + "gpio78", "gpio79", "gpio80", "gpio81", "gpio82", "gpio83", "gpio84", + "gpio85", "gpio86", "gpio87", "gpio88", "gpio89", "gpio90", "gpio91", + "gpio92", "gpio93", "gpio94", "gpio95", "gpio96", "gpio97", "gpio98", + "gpio99", "gpio100", "gpio101", "gpio102", "gpio103", "gpio104", + "gpio105", "gpio106", "gpio107", "gpio108", "gpio109", "gpio110", + "gpio111", "gpio112", "gpio113", "gpio114", "gpio115", "gpio116", + "gpio117", "gpio118", "gpio119", "gpio120", "gpio121", "gpio122", + "gpio123", "gpio124", "gpio125", "gpio126", "gpio127", "gpio128", + "gpio129", "gpio130", "gpio131", "gpio132", "gpio133", "gpio134", + "gpio135", "gpio136", "gpio137", "gpio138", "gpio139", "gpio140", + "gpio141", "gpio142", "gpio143", "gpio144", "gpio145", "gpio146", + "gpio147", "gpio148", "gpio149", "gpio150", "gpio151", "gpio152", + "gpio153", "gpio154", "gpio155", "gpio156", "gpio157", "gpio158", + "gpio159", "gpio160", "gpio161", "gpio162", "gpio163", "gpio164", + "gpio165", "gpio166", "gpio167", "gpio168", "gpio169", "gpio170", + "gpio171", "gpio172", "gpio173", "gpio174", "gpio175", "gpio176", + "gpio177", "gpio178", "gpio179", "gpio180", "gpio181", "gpio182", + "gpio183", "gpio184", "gpio185", "gpio186", "gpio187", "gpio188", + "gpio189", "gpio190", "gpio191", "gpio192", "gpio193", "gpio194", + "gpio195", "gpio196", "gpio197", "gpio198", "gpio199", "gpio200", + "gpio201", "gpio202", "gpio203", "gpio204", "gpio205", "gpio206", + "gpio207", "gpio208", "gpio209", +}; + +static const char * const aon_cci_groups[] = { + "gpio208", "gpio209", +}; + +static const char * const aoss_cti_groups[] = { + "gpio44", "gpio45", "gpio46", "gpio47", +}; + +static const char *const atest_char_groups[] = { + "gpio130", "gpio132", "gpio133", "gpio134", "gpio135", +}; + +static const char *const atest_usb_groups[] = { + "gpio37", "gpio39", "gpio55", "gpio149", "gpio148", +}; + +static const char *const audio_ext_mclk0_groups[] = { + "gpio125", +}; + +static const char *const audio_ext_mclk1_groups[] = { + "gpio124", +}; + +static const char *const audio_ref_clk_groups[] = { + "gpio124", +}; + +static const char *const cam_aon_mclk4_groups[] = { + "gpio104", +}; + +static const char *const cam_mclk_groups[] = { + "gpio100", "gpio101", "gpio102", "gpio103", + "gpio105", "gpio106", "gpio107", +}; + +static const char *const cci_async_in_groups[] = { + "gpio71", "gpio72", "gpio109", +}; + +static const char *const cci_i2c_scl_groups[] = { + "gpio111", "gpio113", "gpio115", "gpio75", "gpio1", +}; + +static const char *const cci_i2c_sda_groups[] = { + "gpio110", "gpio112", "gpio114", "gpio74", "gpio0", +}; + +static const char *const cci_timer_groups[] = { + "gpio116", "gpio117", "gpio118", "gpio119", "gpio120", +}; + +static const char *const cmu_rng_groups[] = { + "gpio129", "gpio128", "gpio127", "gpio122", +}; + +static const char *const coex_uart1_rx_groups[] = { + "gpio148", +}; + +static const char *const coex_uart1_tx_groups[] = { + "gpio149", +}; + +static const char *const coex_uart2_rx_groups[] = { + "gpio150", +}; + +static const char *const coex_uart2_tx_groups[] = { + "gpio151", +}; + +static const char *const cri_trng_groups[] = { + "gpio187", +}; + +static const char *const dbg_out_clk_groups[] = { + "gpio89", +}; + +static const char *const ddr_bist_complete_groups[] = { + "gpio40", +}; + +static const char *const ddr_bist_fail_groups[] = { + "gpio36", +}; + +static const char *const ddr_bist_start_groups[] = { + "gpio37", +}; + +static const char *const ddr_bist_stop_groups[] = { + "gpio41", +}; + +static const char *const ddr_pxi0_groups[] = { + "gpio51", + "gpio52", +}; + +static const char *const ddr_pxi1_groups[] = { + "gpio40", + "gpio41", +}; + +static const char *const ddr_pxi2_groups[] = { + "gpio45", + "gpio47", +}; + +static const char *const ddr_pxi3_groups[] = { + "gpio43", + "gpio44", +}; + +static const char *const dp_hot_groups[] = { + "gpio47", +}; + +static const char *const gcc_gp1_groups[] = { + "gpio86", + "gpio134", +}; + +static const char *const gcc_gp2_groups[] = { + "gpio87", + "gpio135", +}; + +static const char *const gcc_gp3_groups[] = { + "gpio88", + "gpio136", +}; + +static const char *const i2chub0_se0_groups[] = { + "gpio16", + "gpio17", +}; + +static const char *const i2chub0_se1_groups[] = { + "gpio18", + "gpio19", +}; + +static const char *const i2chub0_se2_groups[] = { + "gpio20", + "gpio21", +}; + +static const char *const i2chub0_se3_groups[] = { + "gpio22", + "gpio23", +}; + +static const char *const i2chub0_se4_groups[] = { + "gpio4", + "gpio5", +}; + +static const char *const i2chub0_se5_groups[] = { + "gpio6", + "gpio7", +}; + +static const char *const i2chub0_se6_groups[] = { + "gpio8", + "gpio9", +}; + +static const char *const i2chub0_se7_groups[] = { + "gpio10", + "gpio11", +}; + +static const char *const i2chub0_se8_groups[] = { + "gpio206", + "gpio207", +}; + +static const char *const i2chub0_se9_groups[] = { + "gpio84", + "gpio85", +}; + +static const char *const i2s0_data0_groups[] = { + "gpio127", +}; + +static const char *const i2s0_data1_groups[] = { + "gpio128", +}; + +static const char *const i2s0_sck_groups[] = { + "gpio126", +}; + +static const char *const i2s0_ws_groups[] = { + "gpio129", +}; + +static const char *const i2s1_data0_groups[] = { + "gpio122", +}; + +static const char *const i2s1_data1_groups[] = { + "gpio124", +}; + +static const char *const i2s1_sck_groups[] = { + "gpio121", +}; + +static const char *const i2s1_ws_groups[] = { + "gpio123", +}; + +static const char *const ibi_i3c_groups[] = { + "gpio0", "gpio1", "gpio28", "gpio29", "gpio32", + "gpio33", "gpio56", "gpio57", "gpio60", "gpio61", +}; + +static const char *const jitter_bist_groups[] = { + "gpio43", +}; + +static const char *const mdp_vsync_groups[] = { + "gpio86", + "gpio87", + "gpio133", + "gpio137", +}; + +static const char *const mdp_vsync0_out_groups[] = { + "gpio86", +}; + +static const char *const mdp_vsync1_out_groups[] = { + "gpio86", +}; + +static const char *const mdp_vsync2_out_groups[] = { + "gpio87", +}; + +static const char *const mdp_vsync3_out_groups[] = { + "gpio87", +}; + +static const char *const mdp_vsync_e_groups[] = { + "gpio88", +}; + +static const char *const nav_gpio0_groups[] = { + "gpio154", +}; + +static const char *const nav_gpio1_groups[] = { + "gpio155", +}; + +static const char *const nav_gpio2_groups[] = { + "gpio153", +}; + +static const char *const pcie0_clk_req_n_groups[] = { + "gpio95", +}; + +static const char *const pcie1_clk_req_n_groups[] = { + "gpio98", +}; + +static const char *const phase_flag_groups[] = { + "gpio0", "gpio2", "gpio3", "gpio10", "gpio11", "gpio12", "gpio13", "gpio59", + "gpio63", "gpio64", "gpio65", "gpio67", "gpio68", "gpio69", "gpio75", "gpio76", + "gpio77", "gpio79", "gpio80", "gpio81", "gpio92", "gpio83", "gpio94", "gpio95", + "gpio96", "gpio97", "gpio98", "gpio99", "gpio116", "gpio117", "gpio119", "gpio120", +}; + +static const char *const pll_bist_sync_groups[] = { + "gpio20", +}; + +static const char *const pll_clk_aux_groups[] = { + "gpio107", +}; + +static const char *const prng_rosc0_groups[] = { + "gpio186", +}; + +static const char *const prng_rosc1_groups[] = { + "gpio183", +}; + +static const char *const prng_rosc2_groups[] = { + "gpio182", +}; + +static const char *const prng_rosc3_groups[] = { + "gpio181", +}; + +static const char *const qdss_cti_groups[] = { + "gpio10", "gpio11", "gpio75", "gpio79", + "gpio159", "gpio160", "gpio161", "gpio162", +}; + +static const char *const qdss_gpio_groups[] = { + "gpio59", "gpio64", "gpio73", "gpio100", "gpio101", "gpio102", "gpio103", + "gpio104", "gpio105", "gpio110", "gpio111", "gpio112", "gpio113", "gpio114", + "gpio115", "gpio116", "gpio117", "gpio120", "gpio138", "gpio139", "gpio140", + "gpio141", "gpio142", "gpio143", "gpio144", "gpio145", "gpio148", "gpio149", + "gpio150", "gpio151", "gpio152", "gpio153", "gpio154", "gpio155", "gpio156", + "gpio157", +}; + +static const char *const qlink0_enable_groups[] = { + "gpio157", +}; + +static const char *const qlink0_request_groups[] = { + "gpio156", +}; + +static const char *const qlink0_wmss_groups[] = { + "gpio158", +}; + +static const char *const qlink1_enable_groups[] = { + "gpio160", +}; + +static const char *const qlink1_request_groups[] = { + "gpio159", +}; + +static const char *const qlink1_wmss_groups[] = { + "gpio161", +}; + +static const char *const qlink2_enable_groups[] = { + "gpio163", +}; + +static const char *const qlink2_request_groups[] = { + "gpio162", +}; + +static const char *const qlink2_wmss_groups[] = { + "gpio164", +}; + +static const char *const qspi0_groups[] = { + "gpio89", +}; + +static const char *const qspi1_groups[] = { + "gpio90", +}; + +static const char *const qspi2_groups[] = { + "gpio48", +}; + +static const char *const qspi3_groups[] = { + "gpio49", +}; + +static const char *const qspi_clk_groups[] = { + "gpio50", +}; + +static const char *const qspi_cs_groups[] = { + "gpio51", "gpio91", +}; + +static const char *const qup1_se0_groups[] = { + "gpio28", "gpio29", "gpio30", "gpio31", +}; + +static const char *const qup1_se1_groups[] = { + "gpio32", "gpio33", "gpio34", "gpio35", +}; + +static const char *const qup1_se2_groups[] = { + "gpio40", "gpio41", "gpio42", "gpio36", + "gpio37", "gpio38", "gpio39", +}; + +static const char *const qup1_se3_groups[] = { + "gpio40", "gpio41", "gpio42", "gpio43", +}; + +static const char *const qup1_se4_groups[] = { + "gpio44", "gpio45", "gpio46", "gpio47", +}; + +static const char *const qup1_se5_groups[] = { + "gpio52", "gpio53", "gpio54", "gpio55", +}; + +static const char *const qup1_se6_groups[] = { + "gpio48", "gpio49", "gpio50", "gpio51", +}; + +static const char *const qup1_se7_groups[] = { + "gpio24", "gpio25", "gpio26", "gpio27", +}; + +static const char *const qup2_se0_groups[] = { + "gpio63", "gpio66", "gpio67", +}; + +static const char *const qup2_se0_l0_mira_groups[] = { + "gpio56", +}; + +static const char *const qup2_se0_l0_mirb_groups[] = { + "gpio0", +}; + +static const char *const qup2_se0_l1_mira_groups[] = { + "gpio57", +}; + +static const char *const qup2_se0_l1_mirb_groups[] = { + "gpio1", +}; + +static const char *const qup2_se0_l2_mira_groups[] = { + "gpio58", +}; + +static const char *const qup2_se0_l2_mirb_groups[] = { + "gpio109", +}; + +static const char *const qup2_se0_l3_mira_groups[] = { + "gpio59", +}; + +static const char *const qup2_se0_l3_mirb_groups[] = { + "gpio107", +}; + +static const char *const qup2_se1_groups[] = { + "gpio60", "gpio61", "gpio62", "gpio63", +}; + +static const char *const qup2_se2_groups[] = { + "gpio64", "gpio65", "gpio66", "gpio67", +}; + +static const char *const qup2_se3_groups[] = { + "gpio68", "gpio69", "gpio70", "gpio71", +}; + +static const char *const qup2_se4_groups[] = { + "gpio2", "gpio3", "gpio118", "gpio119", +}; + +static const char *const qup2_se5_groups[] = { + "gpio80", "gpio81", "gpio82", "gpio83", +}; + +static const char *const qup2_se6_groups[] = { + "gpio76", "gpio77", "gpio78", "gpio79", +}; + +static const char *const qup2_se7_groups[] = { + "gpio72", "gpio106", "gpio74", "gpio75", +}; + +static const char * const resout_n_groups[] = { + "gpio92", +}; + +static const char *const sd_write_protect_groups[] = { + "gpio93", +}; + +static const char *const sdc40_groups[] = { + "gpio89", +}; + +static const char *const sdc41_groups[] = { + "gpio90", +}; + +static const char *const sdc42_groups[] = { + "gpio48", +}; + +static const char *const sdc43_groups[] = { + "gpio49", +}; + +static const char *const sdc4_clk_groups[] = { + "gpio50", +}; + +static const char *const sdc4_cmd_groups[] = { + "gpio51", +}; + +static const char * const tb_trig_sdc2_groups[] = { + "gpio64", +}; + +static const char * const tb_trig_sdc4_groups[] = { + "gpio91", +}; + +static const char * const tgu_ch0_trigout_groups[] = { + "gpio64", +}; + +static const char * const tgu_ch1_trigout_groups[] = { + "gpio65", +}; + +static const char * const tgu_ch2_trigout_groups[] = { + "gpio66", +}; + +static const char * const tgu_ch3_trigout_groups[] = { + "gpio67", +}; + +static const char *const tmess_prng0_groups[] = { + "gpio92", +}; + +static const char *const tmess_prng1_groups[] = { + "gpio94", +}; + +static const char *const tmess_prng2_groups[] = { + "gpio95", +}; + +static const char *const tmess_prng3_groups[] = { + "gpio96", +}; + +static const char *const tsense_pwm1_groups[] = { + "gpio50", +}; + +static const char *const tsense_pwm2_groups[] = { + "gpio50", +}; + +static const char *const tsense_pwm3_groups[] = { + "gpio50", +}; + +static const char *const uim0_clk_groups[] = { + "gpio131", +}; + +static const char *const uim0_data_groups[] = { + "gpio130", +}; + +static const char *const uim0_present_groups[] = { + "gpio27", +}; + +static const char *const uim0_reset_groups[] = { + "gpio132", +}; + +static const char *const uim1_clk_groups[] = { + "gpio135", +}; + +static const char *const uim1_data_groups[] = { + "gpio134", +}; + +static const char *const uim1_present_groups[] = { + "gpio26", +}; + +static const char *const uim1_reset_groups[] = { + "gpio136", +}; + +static const char *const usb1_hs_groups[] = { + "gpio90", +}; + +static const char *const usb_phy_groups[] = { + "gpio11", + "gpio48", +}; + +static const char *const vfr_0_groups[] = { + "gpio150", +}; + +static const char *const vfr_1_groups[] = { + "gpio155", +}; + +static const char *const vsense_trigger_mirnat_groups[] = { + "gpio24", +}; + +static const struct pinfunction sm8550_functions[] = { + MSM_PIN_FUNCTION(gpio), + MSM_PIN_FUNCTION(aon_cci), + MSM_PIN_FUNCTION(aoss_cti), + MSM_PIN_FUNCTION(atest_char), + MSM_PIN_FUNCTION(atest_usb), + MSM_PIN_FUNCTION(audio_ext_mclk0), + MSM_PIN_FUNCTION(audio_ext_mclk1), + MSM_PIN_FUNCTION(audio_ref_clk), + MSM_PIN_FUNCTION(cam_aon_mclk4), + MSM_PIN_FUNCTION(cam_mclk), + MSM_PIN_FUNCTION(cci_async_in), + MSM_PIN_FUNCTION(cci_i2c_scl), + MSM_PIN_FUNCTION(cci_i2c_sda), + MSM_PIN_FUNCTION(cci_timer), + MSM_PIN_FUNCTION(cmu_rng), + MSM_PIN_FUNCTION(coex_uart1_rx), + MSM_PIN_FUNCTION(coex_uart1_tx), + MSM_PIN_FUNCTION(coex_uart2_rx), + MSM_PIN_FUNCTION(coex_uart2_tx), + MSM_PIN_FUNCTION(cri_trng), + MSM_PIN_FUNCTION(dbg_out_clk), + MSM_PIN_FUNCTION(ddr_bist_complete), + MSM_PIN_FUNCTION(ddr_bist_fail), + MSM_PIN_FUNCTION(ddr_bist_start), + MSM_PIN_FUNCTION(ddr_bist_stop), + MSM_PIN_FUNCTION(ddr_pxi0), + MSM_PIN_FUNCTION(ddr_pxi1), + MSM_PIN_FUNCTION(ddr_pxi2), + MSM_PIN_FUNCTION(ddr_pxi3), + MSM_PIN_FUNCTION(dp_hot), + MSM_PIN_FUNCTION(gcc_gp1), + MSM_PIN_FUNCTION(gcc_gp2), + MSM_PIN_FUNCTION(gcc_gp3), + MSM_PIN_FUNCTION(i2chub0_se0), + MSM_PIN_FUNCTION(i2chub0_se1), + MSM_PIN_FUNCTION(i2chub0_se2), + MSM_PIN_FUNCTION(i2chub0_se3), + MSM_PIN_FUNCTION(i2chub0_se4), + MSM_PIN_FUNCTION(i2chub0_se5), + MSM_PIN_FUNCTION(i2chub0_se6), + MSM_PIN_FUNCTION(i2chub0_se7), + MSM_PIN_FUNCTION(i2chub0_se8), + MSM_PIN_FUNCTION(i2chub0_se9), + MSM_PIN_FUNCTION(i2s0_data0), + MSM_PIN_FUNCTION(i2s0_data1), + MSM_PIN_FUNCTION(i2s0_sck), + MSM_PIN_FUNCTION(i2s0_ws), + MSM_PIN_FUNCTION(i2s1_data0), + MSM_PIN_FUNCTION(i2s1_data1), + MSM_PIN_FUNCTION(i2s1_sck), + MSM_PIN_FUNCTION(i2s1_ws), + MSM_PIN_FUNCTION(ibi_i3c), + MSM_PIN_FUNCTION(jitter_bist), + MSM_PIN_FUNCTION(mdp_vsync), + MSM_PIN_FUNCTION(mdp_vsync0_out), + MSM_PIN_FUNCTION(mdp_vsync1_out), + MSM_PIN_FUNCTION(mdp_vsync2_out), + MSM_PIN_FUNCTION(mdp_vsync3_out), + MSM_PIN_FUNCTION(mdp_vsync_e), + MSM_PIN_FUNCTION(nav_gpio0), + MSM_PIN_FUNCTION(nav_gpio1), + MSM_PIN_FUNCTION(nav_gpio2), + MSM_PIN_FUNCTION(pcie0_clk_req_n), + MSM_PIN_FUNCTION(pcie1_clk_req_n), + MSM_PIN_FUNCTION(phase_flag), + MSM_PIN_FUNCTION(pll_bist_sync), + MSM_PIN_FUNCTION(pll_clk_aux), + MSM_PIN_FUNCTION(prng_rosc0), + MSM_PIN_FUNCTION(prng_rosc1), + MSM_PIN_FUNCTION(prng_rosc2), + MSM_PIN_FUNCTION(prng_rosc3), + MSM_PIN_FUNCTION(qdss_cti), + MSM_PIN_FUNCTION(qdss_gpio), + MSM_PIN_FUNCTION(qlink0_enable), + MSM_PIN_FUNCTION(qlink0_request), + MSM_PIN_FUNCTION(qlink0_wmss), + MSM_PIN_FUNCTION(qlink1_enable), + MSM_PIN_FUNCTION(qlink1_request), + MSM_PIN_FUNCTION(qlink1_wmss), + MSM_PIN_FUNCTION(qlink2_enable), + MSM_PIN_FUNCTION(qlink2_request), + MSM_PIN_FUNCTION(qlink2_wmss), + MSM_PIN_FUNCTION(qspi0), + MSM_PIN_FUNCTION(qspi1), + MSM_PIN_FUNCTION(qspi2), + MSM_PIN_FUNCTION(qspi3), + MSM_PIN_FUNCTION(qspi_clk), + MSM_PIN_FUNCTION(qspi_cs), + MSM_PIN_FUNCTION(qup1_se0), + MSM_PIN_FUNCTION(qup1_se1), + MSM_PIN_FUNCTION(qup1_se2), + MSM_PIN_FUNCTION(qup1_se3), + MSM_PIN_FUNCTION(qup1_se4), + MSM_PIN_FUNCTION(qup1_se5), + MSM_PIN_FUNCTION(qup1_se6), + MSM_PIN_FUNCTION(qup1_se7), + MSM_PIN_FUNCTION(qup2_se0), + MSM_PIN_FUNCTION(qup2_se0_l0_mira), + MSM_PIN_FUNCTION(qup2_se0_l0_mirb), + MSM_PIN_FUNCTION(qup2_se0_l1_mira), + MSM_PIN_FUNCTION(qup2_se0_l1_mirb), + MSM_PIN_FUNCTION(qup2_se0_l2_mira), + MSM_PIN_FUNCTION(qup2_se0_l2_mirb), + MSM_PIN_FUNCTION(qup2_se0_l3_mira), + MSM_PIN_FUNCTION(qup2_se0_l3_mirb), + MSM_PIN_FUNCTION(qup2_se1), + MSM_PIN_FUNCTION(qup2_se2), + MSM_PIN_FUNCTION(qup2_se3), + MSM_PIN_FUNCTION(qup2_se4), + MSM_PIN_FUNCTION(qup2_se5), + MSM_PIN_FUNCTION(qup2_se6), + MSM_PIN_FUNCTION(qup2_se7), + MSM_PIN_FUNCTION(resout_n), + MSM_PIN_FUNCTION(sd_write_protect), + MSM_PIN_FUNCTION(sdc40), + MSM_PIN_FUNCTION(sdc41), + MSM_PIN_FUNCTION(sdc42), + MSM_PIN_FUNCTION(sdc43), + MSM_PIN_FUNCTION(sdc4_clk), + MSM_PIN_FUNCTION(sdc4_cmd), + MSM_PIN_FUNCTION(tb_trig_sdc2), + MSM_PIN_FUNCTION(tb_trig_sdc4), + MSM_PIN_FUNCTION(tgu_ch0_trigout), + MSM_PIN_FUNCTION(tgu_ch1_trigout), + MSM_PIN_FUNCTION(tgu_ch2_trigout), + MSM_PIN_FUNCTION(tgu_ch3_trigout), + MSM_PIN_FUNCTION(tmess_prng0), + MSM_PIN_FUNCTION(tmess_prng1), + MSM_PIN_FUNCTION(tmess_prng2), + MSM_PIN_FUNCTION(tmess_prng3), + MSM_PIN_FUNCTION(tsense_pwm1), + MSM_PIN_FUNCTION(tsense_pwm2), + MSM_PIN_FUNCTION(tsense_pwm3), + MSM_PIN_FUNCTION(uim0_clk), + MSM_PIN_FUNCTION(uim0_data), + MSM_PIN_FUNCTION(uim0_present), + MSM_PIN_FUNCTION(uim0_reset), + MSM_PIN_FUNCTION(uim1_clk), + MSM_PIN_FUNCTION(uim1_data), + MSM_PIN_FUNCTION(uim1_present), + MSM_PIN_FUNCTION(uim1_reset), + MSM_PIN_FUNCTION(usb1_hs), + MSM_PIN_FUNCTION(usb_phy), + MSM_PIN_FUNCTION(vfr_0), + MSM_PIN_FUNCTION(vfr_1), + MSM_PIN_FUNCTION(vsense_trigger_mirnat), +}; + +/* + * Every pin is maintained as a single group, and missing or non-existing pin + * would be maintained as dummy group to synchronize pin group index with + * pin descriptor registered with pinctrl core. + * Clients would not be able to request these dummy pin groups. + */ +static const struct msm_pingroup sm8550_groups[] = { + [0] = PINGROUP(0, cci_i2c_sda, qup2_se0_l0_mirb, ibi_i3c, phase_flag, _, _, _, _, _), + [1] = PINGROUP(1, cci_i2c_scl, qup2_se0_l1_mirb, ibi_i3c, _, _, _, _, _, _), + [2] = PINGROUP(2, qup2_se4, phase_flag, _, _, _, _, _, _, _), + [3] = PINGROUP(3, qup2_se4, phase_flag, _, _, _, _, _, _, _), + [4] = PINGROUP(4, i2chub0_se4, _, _, _, _, _, _, _, _), + [5] = PINGROUP(5, i2chub0_se4, _, _, _, _, _, _, _, _), + [6] = PINGROUP(6, i2chub0_se5, _, _, _, _, _, _, _, _), + [7] = PINGROUP(7, i2chub0_se5, _, _, _, _, _, _, _, _), + [8] = PINGROUP(8, i2chub0_se6, _, _, _, _, _, _, _, _), + [9] = PINGROUP(9, i2chub0_se6, _, _, _, _, _, _, _, _), + [10] = PINGROUP(10, i2chub0_se7, qdss_cti, phase_flag, _, _, _, _, _, _), + [11] = PINGROUP(11, i2chub0_se7, usb_phy, qdss_cti, phase_flag, _, _, _, _, _), + [12] = PINGROUP(12, phase_flag, _, _, _, _, _, _, _, _), + [13] = PINGROUP(13, phase_flag, _, _, _, _, _, _, _, _), + [14] = PINGROUP(14, _, _, _, _, _, _, _, _, _), + [15] = PINGROUP(15, _, _, _, _, _, _, _, _, _), + [16] = PINGROUP(16, i2chub0_se0, _, _, _, _, _, _, _, _), + [17] = PINGROUP(17, i2chub0_se0, _, _, _, _, _, _, _, _), + [18] = PINGROUP(18, i2chub0_se1, _, _, _, _, _, _, _, _), + [19] = PINGROUP(19, i2chub0_se1, _, _, _, _, _, _, _, _), + [20] = PINGROUP(20, i2chub0_se2, pll_bist_sync, _, _, _, _, _, _, _), + [21] = PINGROUP(21, i2chub0_se2, _, _, _, _, _, _, _, _), + [22] = PINGROUP(22, i2chub0_se3, _, _, _, _, _, _, _, _), + [23] = PINGROUP(23, i2chub0_se3, _, _, _, _, _, _, _, _), + [24] = PINGROUP(24, qup1_se7, vsense_trigger_mirnat, _, _, _, _, _, _, _), + [25] = PINGROUP(25, qup1_se7, _, _, _, _, _, _, _, _), + [26] = PINGROUP(26, qup1_se7, uim1_present, _, _, _, _, _, _, _), + [27] = PINGROUP(27, qup1_se7, uim0_present, _, _, _, _, _, _, _), + [28] = PINGROUP(28, qup1_se0, ibi_i3c, _, _, _, _, _, _, _), + [29] = PINGROUP(29, qup1_se0, ibi_i3c, _, _, _, _, _, _, _), + [30] = PINGROUP(30, qup1_se0, _, _, _, _, _, _, _, _), + [31] = PINGROUP(31, qup1_se0, _, _, _, _, _, _, _, _), + [32] = PINGROUP(32, qup1_se1, ibi_i3c, _, _, _, _, _, _, _), + [33] = PINGROUP(33, qup1_se1, ibi_i3c, _, _, _, _, _, _, _), + [34] = PINGROUP(34, qup1_se1, _, _, _, _, _, _, _, _), + [35] = PINGROUP(35, qup1_se1, _, _, _, _, _, _, _, _), + [36] = PINGROUP(36, qup1_se2, ddr_bist_fail, _, _, _, _, _, _, _), + [37] = PINGROUP(37, qup1_se2, ddr_bist_start, _, atest_usb, _, _, _, _, _), + [38] = PINGROUP(38, qup1_se2, _, _, _, _, _, _, _, _), + [39] = PINGROUP(39, qup1_se2, _, atest_usb, _, _, _, _, _, _), + [40] = PINGROUP(40, qup1_se3, qup1_se2, ddr_bist_complete, _, ddr_pxi1, _, _, _, _), + [41] = PINGROUP(41, qup1_se3, qup1_se2, ddr_bist_stop, _, ddr_pxi1, _, _, _, _), + [42] = PINGROUP(42, qup1_se3, qup1_se2, _, _, _, _, _, _, _), + [43] = PINGROUP(43, qup1_se3, jitter_bist, ddr_pxi3, _, _, _, _, _, _), + [44] = PINGROUP(44, qup1_se4, aoss_cti, ddr_pxi3, _, _, _, _, _, _), + [45] = PINGROUP(45, qup1_se4, aoss_cti, ddr_pxi2, _, _, _, _, _, _), + [46] = PINGROUP(46, qup1_se4, aoss_cti, _, _, _, _, _, _, _), + [47] = PINGROUP(47, qup1_se4, aoss_cti, dp_hot, ddr_pxi2, _, _, _, _, _), + [48] = PINGROUP(48, usb_phy, qup1_se6, qspi2, sdc42, _, _, _, _, _), + [49] = PINGROUP(49, qup1_se6, qspi3, sdc43, _, _, _, _, _, _), + [50] = PINGROUP(50, qup1_se6, qspi_clk, sdc4_clk, tsense_pwm1, tsense_pwm2, tsense_pwm3, _, _, _), + [51] = PINGROUP(51, qup1_se6, qspi_cs, sdc4_cmd, ddr_pxi0, _, _, _, _, _), + [52] = PINGROUP(52, _, qup1_se5, ddr_pxi0, _, _, _, _, _, _), + [53] = PINGROUP(53, _, qup1_se5, _, _, _, _, _, _, _), + [54] = PINGROUP(54, _, qup1_se5, _, _, _, _, _, _, _), + [55] = PINGROUP(55, qup1_se5, atest_usb, _, _, _, _, _, _, _), + [56] = PINGROUP(56, qup2_se0_l0_mira, ibi_i3c, _, _, _, _, _, _, _), + [57] = PINGROUP(57, qup2_se0_l1_mira, ibi_i3c, _, _, _, _, _, _, _), + [58] = PINGROUP(58, qup2_se0_l2_mira, _, _, _, _, _, _, _, _), + [59] = PINGROUP(59, qup2_se0_l3_mira, phase_flag, _, qdss_gpio, _, _, _, _, _), + [60] = PINGROUP(60, qup2_se1, ibi_i3c, _, _, _, _, _, _, _), + [61] = PINGROUP(61, qup2_se1, ibi_i3c, _, _, _, _, _, _, _), + [62] = PINGROUP(62, qup2_se1, _, _, _, _, _, _, _, _), + [63] = PINGROUP(63, qup2_se1, qup2_se0, phase_flag, _, _, _, _, _, _), + [64] = PINGROUP(64, qup2_se2, tb_trig_sdc2, phase_flag, tgu_ch0_trigout, _, qdss_gpio, _, _, _), + [65] = PINGROUP(65, qup2_se2, phase_flag, tgu_ch1_trigout, _, _, _, _, _, _), + [66] = PINGROUP(66, qup2_se2, qup2_se0, tgu_ch2_trigout, _, _, _, _, _, _), + [67] = PINGROUP(67, qup2_se2, qup2_se0, phase_flag, tgu_ch3_trigout, _, _, _, _, _), + [68] = PINGROUP(68, qup2_se3, phase_flag, _, _, _, _, _, _, _), + [69] = PINGROUP(69, qup2_se3, phase_flag, _, _, _, _, _, _, _), + [70] = PINGROUP(70, qup2_se3, _, _, _, _, _, _, _, _), + [71] = PINGROUP(71, cci_async_in, qup2_se3, _, _, _, _, _, _, _), + [72] = PINGROUP(72, cci_async_in, qup2_se7, _, _, _, _, _, _, _), + [73] = PINGROUP(73, qdss_gpio, _, _, _, _, _, _, _, _), + [74] = PINGROUP(74, cci_i2c_sda, qup2_se7, _, _, _, _, _, _, _), + [75] = PINGROUP(75, cci_i2c_scl, qup2_se7, qdss_cti, phase_flag, _, _, _, _, _), + [76] = PINGROUP(76, qup2_se6, phase_flag, _, _, _, _, _, _, _), + [77] = PINGROUP(77, qup2_se6, phase_flag, _, _, _, _, _, _, _), + [78] = PINGROUP(78, qup2_se6, _, _, _, _, _, _, _, _), + [79] = PINGROUP(79, qup2_se6, qdss_cti, phase_flag, _, _, _, _, _, _), + [80] = PINGROUP(80, qup2_se5, phase_flag, _, _, _, _, _, _, _), + [81] = PINGROUP(81, qup2_se5, phase_flag, _, _, _, _, _, _, _), + [82] = PINGROUP(82, qup2_se5, _, _, _, _, _, _, _, _), + [83] = PINGROUP(83, qup2_se5, phase_flag, _, _, _, _, _, _, _), + [84] = PINGROUP(84, i2chub0_se9, _, _, _, _, _, _, _, _), + [85] = PINGROUP(85, i2chub0_se9, _, _, _, _, _, _, _, _), + [86] = PINGROUP(86, mdp_vsync, mdp_vsync0_out, mdp_vsync1_out, gcc_gp1, _, _, _, _, _), + [87] = PINGROUP(87, mdp_vsync, mdp_vsync2_out, mdp_vsync3_out, gcc_gp2, _, _, _, _, _), + [88] = PINGROUP(88, mdp_vsync_e, gcc_gp3, _, _, _, _, _, _, _), + [89] = PINGROUP(89, qspi0, sdc40, dbg_out_clk, _, _, _, _, _, _), + [90] = PINGROUP(90, usb1_hs, qspi1, sdc41, _, _, _, _, _, _), + [91] = PINGROUP(91, qspi_cs, tb_trig_sdc4, _, _, _, _, _, _, _), + [92] = PINGROUP(92, resout_n, phase_flag, tmess_prng0, _, _, _, _, _, _), + [93] = PINGROUP(93, sd_write_protect, _, _, _, _, _, _, _, _), + [94] = PINGROUP(94, phase_flag, tmess_prng1, _, _, _, _, _, _, _), + [95] = PINGROUP(95, pcie0_clk_req_n, phase_flag, tmess_prng2, _, _, _, _, _, _), + [96] = PINGROUP(96, phase_flag, tmess_prng3, _, _, _, _, _, _, _), + [97] = PINGROUP(97, phase_flag, _, _, _, _, _, _, _, _), + [98] = PINGROUP(98, pcie1_clk_req_n, phase_flag, _, _, _, _, _, _, _), + [99] = PINGROUP(99, phase_flag, _, _, _, _, _, _, _, _), + [100] = PINGROUP(100, cam_mclk, qdss_gpio, _, _, _, _, _, _, _), + [101] = PINGROUP(101, cam_mclk, qdss_gpio, _, _, _, _, _, _, _), + [102] = PINGROUP(102, cam_mclk, qdss_gpio, _, _, _, _, _, _, _), + [103] = PINGROUP(103, cam_mclk, qdss_gpio, _, _, _, _, _, _, _), + [104] = PINGROUP(104, cam_aon_mclk4, qdss_gpio, _, _, _, _, _, _, _), + [105] = PINGROUP(105, cam_mclk, qdss_gpio, _, _, _, _, _, _, _), + [106] = PINGROUP(106, cam_mclk, qup2_se7, _, _, _, _, _, _, _), + [107] = PINGROUP(107, cam_mclk, qup2_se0_l3_mirb, pll_clk_aux, _, _, _, _, _, _), + [108] = PINGROUP(108, _, _, _, _, _, _, _, _, _), + [109] = PINGROUP(109, cci_async_in, qup2_se0_l2_mirb, _, _, _, _, _, _, _), + [110] = PINGROUP(110, cci_i2c_sda, qdss_gpio, _, _, _, _, _, _, _), + [111] = PINGROUP(111, cci_i2c_scl, qdss_gpio, _, _, _, _, _, _, _), + [112] = PINGROUP(112, cci_i2c_sda, qdss_gpio, _, _, _, _, _, _, _), + [113] = PINGROUP(113, cci_i2c_scl, qdss_gpio, _, _, _, _, _, _, _), + [114] = PINGROUP(114, cci_i2c_sda, qdss_gpio, _, _, _, _, _, _, _), + [115] = PINGROUP(115, cci_i2c_scl, qdss_gpio, _, _, _, _, _, _, _), + [116] = PINGROUP(116, cci_timer, phase_flag, _, qdss_gpio, _, _, _, _, _), + [117] = PINGROUP(117, cci_timer, phase_flag, _, qdss_gpio, _, _, _, _, _), + [118] = PINGROUP(118, qup2_se4, cci_timer, _, _, _, _, _, _, _), + [119] = PINGROUP(119, qup2_se4, cci_timer, phase_flag, _, _, _, _, _, _), + [120] = PINGROUP(120, cci_timer, phase_flag, _, qdss_gpio, _, _, _, _, _), + [121] = PINGROUP(121, i2s1_sck, _, _, _, _, _, _, _, _), + [122] = PINGROUP(122, i2s1_data0, cmu_rng, _, _, _, _, _, _, _), + [123] = PINGROUP(123, i2s1_ws, _, _, _, _, _, _, _, _), + [124] = PINGROUP(124, i2s1_data1, audio_ext_mclk1, audio_ref_clk, _, _, _, _, _, _), + [125] = PINGROUP(125, audio_ext_mclk0, _, _, _, _, _, _, _, _), + [126] = PINGROUP(126, i2s0_sck, _, _, _, _, _, _, _, _), + [127] = PINGROUP(127, i2s0_data0, cmu_rng, _, _, _, _, _, _, _), + [128] = PINGROUP(128, i2s0_data1, cmu_rng, _, _, _, _, _, _, _), + [129] = PINGROUP(129, i2s0_ws, cmu_rng, _, _, _, _, _, _, _), + [130] = PINGROUP(130, uim0_data, atest_char, _, _, _, _, _, _, _), + [131] = PINGROUP(131, uim0_clk, _, _, _, _, _, _, _, _), + [132] = PINGROUP(132, uim0_reset, atest_char, _, _, _, _, _, _, _), + [133] = PINGROUP(133, mdp_vsync, atest_char, _, _, _, _, _, _, _), + [134] = PINGROUP(134, uim1_data, gcc_gp1, atest_char, _, _, _, _, _, _), + [135] = PINGROUP(135, uim1_clk, gcc_gp2, atest_char, _, _, _, _, _, _), + [136] = PINGROUP(136, uim1_reset, gcc_gp3, _, _, _, _, _, _, _), + [137] = PINGROUP(137, mdp_vsync, _, _, _, _, _, _, _, _), + [138] = PINGROUP(138, _, _, qdss_gpio, _, _, _, _, _, _), + [139] = PINGROUP(139, _, _, qdss_gpio, _, _, _, _, _, _), + [140] = PINGROUP(140, _, _, qdss_gpio, _, _, _, _, _, _), + [141] = PINGROUP(141, _, _, qdss_gpio, _, _, _, _, _, _), + [142] = PINGROUP(142, _, _, qdss_gpio, _, _, _, _, _, _), + [143] = PINGROUP(143, _, _, qdss_gpio, _, _, _, _, _, _), + [144] = PINGROUP(144, _, _, qdss_gpio, _, _, _, _, _, _), + [145] = PINGROUP(145, _, _, qdss_gpio, _, _, _, _, _, _), + [146] = PINGROUP(146, _, _, _, _, _, _, _, _, _), + [147] = PINGROUP(147, _, _, _, _, _, _, _, _, _), + [148] = PINGROUP(148, coex_uart1_rx, qdss_gpio, atest_usb, _, _, _, _, _, _), + [149] = PINGROUP(149, coex_uart1_tx, qdss_gpio, atest_usb, _, _, _, _, _, _), + [150] = PINGROUP(150, coex_uart2_rx, _, vfr_0, qdss_gpio, _, _, _, _, _), + [151] = PINGROUP(151, coex_uart2_tx, _, qdss_gpio, _, _, _, _, _, _), + [152] = PINGROUP(152, _, qdss_gpio, _, _, _, _, _, _, _), + [153] = PINGROUP(153, _, nav_gpio2, qdss_gpio, _, _, _, _, _, _), + [154] = PINGROUP(154, nav_gpio0, qdss_gpio, _, _, _, _, _, _, _), + [155] = PINGROUP(155, nav_gpio1, vfr_1, qdss_gpio, _, _, _, _, _, _), + [156] = PINGROUP(156, qlink0_request, qdss_gpio, _, _, _, _, _, _, _), + [157] = PINGROUP(157, qlink0_enable, qdss_gpio, _, _, _, _, _, _, _), + [158] = PINGROUP(158, qlink0_wmss, _, _, _, _, _, _, _, _), + [159] = PINGROUP(159, qlink1_request, qdss_cti, _, _, _, _, _, _, _), + [160] = PINGROUP(160, qlink1_enable, qdss_cti, _, _, _, _, _, _, _), + [161] = PINGROUP(161, qlink1_wmss, qdss_cti, _, _, _, _, _, _, _), + [162] = PINGROUP(162, qlink2_request, qdss_cti, _, _, _, _, _, _, _), + [163] = PINGROUP(163, qlink2_enable, _, _, _, _, _, _, _, _), + [164] = PINGROUP(164, qlink2_wmss, _, _, _, _, _, _, _, _), + [165] = PINGROUP(165, _, _, _, _, _, _, _, _, _), + [166] = PINGROUP(166, _, _, _, _, _, _, _, _, _), + [167] = PINGROUP(167, _, _, _, _, _, _, _, _, _), + [168] = PINGROUP(168, _, _, _, _, _, _, _, _, _), + [169] = PINGROUP(169, _, _, _, _, _, _, _, _, _), + [170] = PINGROUP(170, _, _, _, _, _, _, _, _, _), + [171] = PINGROUP(171, _, _, _, _, _, _, _, _, _), + [172] = PINGROUP(172, _, _, _, _, _, _, _, _, _), + [173] = PINGROUP(173, _, _, _, _, _, _, _, _, _), + [174] = PINGROUP(174, _, _, _, _, _, _, _, _, _), + [175] = PINGROUP(175, _, _, _, _, _, _, _, _, _), + [176] = PINGROUP(176, _, _, _, _, _, _, _, _, _), + [177] = PINGROUP(177, _, _, _, _, _, _, _, _, _), + [178] = PINGROUP(178, _, _, _, _, _, _, _, _, _), + [179] = PINGROUP(179, _, _, _, _, _, _, _, _, _), + [180] = PINGROUP(180, _, _, _, _, _, _, _, _, _), + [181] = PINGROUP(181, prng_rosc3, _, _, _, _, _, _, _, _), + [182] = PINGROUP(182, prng_rosc2, _, _, _, _, _, _, _, _), + [183] = PINGROUP(183, prng_rosc1, _, _, _, _, _, _, _, _), + [184] = PINGROUP(184, _, _, _, _, _, _, _, _, _), + [185] = PINGROUP(185, _, _, _, _, _, _, _, _, _), + [186] = PINGROUP(186, prng_rosc0, _, _, _, _, _, _, _, _), + [187] = PINGROUP(187, cri_trng, _, _, _, _, _, _, _, _), + [188] = PINGROUP(188, _, _, _, _, _, _, _, _, _), + [189] = PINGROUP(189, _, _, _, _, _, _, _, _, _), + [190] = PINGROUP(190, _, _, _, _, _, _, _, _, _), + [191] = PINGROUP(191, _, _, _, _, _, _, _, _, _), + [192] = PINGROUP(192, _, _, _, _, _, _, _, _, _), + [193] = PINGROUP(193, _, _, _, _, _, _, _, _, _), + [194] = PINGROUP(194, _, _, _, _, _, _, _, _, _), + [195] = PINGROUP(195, _, _, _, _, _, _, _, _, _), + [196] = PINGROUP(196, _, _, _, _, _, _, _, _, _), + [197] = PINGROUP(197, _, _, _, _, _, _, _, _, _), + [198] = PINGROUP(198, _, _, _, _, _, _, _, _, _), + [199] = PINGROUP(199, _, _, _, _, _, _, _, _, _), + [200] = PINGROUP(200, _, _, _, _, _, _, _, _, _), + [201] = PINGROUP(201, _, _, _, _, _, _, _, _, _), + [202] = PINGROUP(202, _, _, _, _, _, _, _, _, _), + [203] = PINGROUP(203, _, _, _, _, _, _, _, _, _), + [204] = PINGROUP(204, _, _, _, _, _, _, _, _, _), + [205] = PINGROUP(205, _, _, _, _, _, _, _, _, _), + [206] = PINGROUP(206, i2chub0_se8, _, _, _, _, _, _, _, _), + [207] = PINGROUP(207, i2chub0_se8, _, _, _, _, _, _, _, _), + [208] = PINGROUP(208, aon_cci, _, _, _, _, _, _, _, _), + [209] = PINGROUP(209, aon_cci, _, _, _, _, _, _, _, _), + [210] = UFS_RESET(ufs_reset, 0xde000), + [211] = SDC_QDSD_PINGROUP(sdc2_clk, 0xd6000, 14, 6), + [212] = SDC_QDSD_PINGROUP(sdc2_cmd, 0xd6000, 11, 3), + [213] = SDC_QDSD_PINGROUP(sdc2_data, 0xd6000, 9, 0), +}; + +static const struct msm_gpio_wakeirq_map sm8550_pdc_map[] = { + { 0, 118 }, { 2, 90 }, { 3, 101 }, { 8, 60 }, { 9, 67 }, + { 11, 103 }, { 14, 136 }, { 15, 78 }, { 16, 138 }, { 17, 80 }, + { 18, 71 }, { 19, 59 }, { 25, 57 }, { 26, 74 }, { 27, 76 }, + { 28, 62 }, { 31, 88 }, { 32, 63 }, { 35, 124 }, { 39, 92 }, + { 40, 77 }, { 41, 83 }, { 43, 86 }, { 44, 75 }, { 45, 93 }, + { 46, 96 }, { 47, 64 }, { 48, 110 }, { 51, 89 }, { 55, 95 }, + { 56, 68 }, { 59, 87 }, { 60, 65 }, { 62, 100 }, { 63, 81 }, + { 67, 79 }, { 71, 102 }, { 73, 82 }, { 75, 72 }, { 79, 140 }, + { 82, 105 }, { 83, 104 }, { 84, 126 }, { 85, 142 }, { 86, 106 }, + { 87, 107 }, { 88, 61 }, { 89, 111 }, { 95, 108 }, { 96, 109 }, + { 98, 97 }, { 99, 58 }, { 107, 139 }, { 119, 94 }, { 120, 135 }, + { 133, 52 }, { 137, 84 }, { 148, 66 }, { 150, 73 }, { 153, 70 }, + { 154, 53 }, { 155, 69 }, { 156, 54 }, { 159, 55 }, { 162, 56 }, + { 166, 116 }, { 169, 119 }, { 171, 120 }, { 172, 85 }, { 174, 98 }, + { 176, 112 }, { 177, 51 }, { 181, 114 }, { 182, 115 }, { 185, 117 }, + { 187, 91 }, { 188, 123 }, { 190, 127 }, { 191, 113 }, { 192, 128 }, + { 193, 129 }, { 196, 133 }, { 197, 134 }, { 198, 50 }, { 199, 99 }, + { 200, 49 }, { 201, 48 }, { 203, 125 }, { 205, 141 }, { 206, 137 }, + { 207, 47 }, { 208, 121 }, { 209, 122 }, +}; + +static const struct msm_pinctrl_soc_data sm8550_tlmm = { + .pins = sm8550_pins, + .npins = ARRAY_SIZE(sm8550_pins), + .functions = sm8550_functions, + .nfunctions = ARRAY_SIZE(sm8550_functions), + .groups = sm8550_groups, + .ngroups = ARRAY_SIZE(sm8550_groups), + .ngpios = 211, + .wakeirq_map = sm8550_pdc_map, + .nwakeirq_map = ARRAY_SIZE(sm8550_pdc_map), + .egpio_func = 9, +}; + +static int sm8550_tlmm_probe(struct platform_device *pdev) +{ + return msm_pinctrl_probe(pdev, &sm8550_tlmm); +} + +static const struct of_device_id sm8550_tlmm_of_match[] = { + { .compatible = "qcom,sm8550-tlmm", }, + {}, +}; + +static struct platform_driver sm8550_tlmm_driver = { + .driver = { + .name = "sm8550-tlmm", + .of_match_table = sm8550_tlmm_of_match, + }, + .probe = sm8550_tlmm_probe, + .remove = msm_pinctrl_remove, +}; + +static int __init sm8550_tlmm_init(void) +{ + return platform_driver_register(&sm8550_tlmm_driver); +} +arch_initcall(sm8550_tlmm_init); + +static void __exit sm8550_tlmm_exit(void) +{ + platform_driver_unregister(&sm8550_tlmm_driver); +} +module_exit(sm8550_tlmm_exit); + +MODULE_DESCRIPTION("QTI SM8550 TLMM driver"); +MODULE_LICENSE("GPL"); +MODULE_DEVICE_TABLE(of, sm8550_tlmm_of_match); diff --git a/drivers/pinctrl/qcom/pinctrl-spmi-gpio.c b/drivers/pinctrl/qcom/pinctrl-spmi-gpio.c new file mode 100644 index 0000000000..deded9c6fd --- /dev/null +++ b/drivers/pinctrl/qcom/pinctrl-spmi-gpio.c @@ -0,0 +1,1276 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2012-2014, 2016-2021 The Linux Foundation. All rights reserved. + * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include <linux/gpio/driver.h> +#include <linux/interrupt.h> +#include <linux/module.h> +#include <linux/of.h> +#include <linux/of_irq.h> +#include <linux/platform_device.h> +#include <linux/regmap.h> +#include <linux/seq_file.h> +#include <linux/slab.h> +#include <linux/spmi.h> +#include <linux/types.h> + +#include <linux/pinctrl/pinconf-generic.h> +#include <linux/pinctrl/pinconf.h> +#include <linux/pinctrl/pinmux.h> + +#include <dt-bindings/pinctrl/qcom,pmic-gpio.h> + +#include "../core.h" +#include "../pinctrl-utils.h" + +#define PMIC_GPIO_ADDRESS_RANGE 0x100 + +/* type and subtype registers base address offsets */ +#define PMIC_GPIO_REG_TYPE 0x4 +#define PMIC_GPIO_REG_SUBTYPE 0x5 + +/* GPIO peripheral type and subtype out_values */ +#define PMIC_GPIO_TYPE 0x10 +#define PMIC_GPIO_SUBTYPE_GPIO_4CH 0x1 +#define PMIC_GPIO_SUBTYPE_GPIOC_4CH 0x5 +#define PMIC_GPIO_SUBTYPE_GPIO_8CH 0x9 +#define PMIC_GPIO_SUBTYPE_GPIOC_8CH 0xd +#define PMIC_GPIO_SUBTYPE_GPIO_LV 0x10 +#define PMIC_GPIO_SUBTYPE_GPIO_MV 0x11 +#define PMIC_GPIO_SUBTYPE_GPIO_LV_VIN2 0x12 +#define PMIC_GPIO_SUBTYPE_GPIO_MV_VIN3 0x13 + +#define PMIC_MPP_REG_RT_STS 0x10 +#define PMIC_MPP_REG_RT_STS_VAL_MASK 0x1 + +/* control register base address offsets */ +#define PMIC_GPIO_REG_MODE_CTL 0x40 +#define PMIC_GPIO_REG_DIG_VIN_CTL 0x41 +#define PMIC_GPIO_REG_DIG_PULL_CTL 0x42 +#define PMIC_GPIO_REG_LV_MV_DIG_OUT_SOURCE_CTL 0x44 +#define PMIC_GPIO_REG_DIG_IN_CTL 0x43 +#define PMIC_GPIO_REG_DIG_OUT_CTL 0x45 +#define PMIC_GPIO_REG_EN_CTL 0x46 +#define PMIC_GPIO_REG_LV_MV_ANA_PASS_THRU_SEL 0x4A + +/* PMIC_GPIO_REG_MODE_CTL */ +#define PMIC_GPIO_REG_MODE_VALUE_SHIFT 0x1 +#define PMIC_GPIO_REG_MODE_FUNCTION_SHIFT 1 +#define PMIC_GPIO_REG_MODE_FUNCTION_MASK 0x7 +#define PMIC_GPIO_REG_MODE_DIR_SHIFT 4 +#define PMIC_GPIO_REG_MODE_DIR_MASK 0x7 + +#define PMIC_GPIO_MODE_DIGITAL_INPUT 0 +#define PMIC_GPIO_MODE_DIGITAL_OUTPUT 1 +#define PMIC_GPIO_MODE_DIGITAL_INPUT_OUTPUT 2 +#define PMIC_GPIO_MODE_ANALOG_PASS_THRU 3 +#define PMIC_GPIO_REG_LV_MV_MODE_DIR_MASK 0x3 + +/* PMIC_GPIO_REG_DIG_VIN_CTL */ +#define PMIC_GPIO_REG_VIN_SHIFT 0 +#define PMIC_GPIO_REG_VIN_MASK 0x7 + +/* PMIC_GPIO_REG_DIG_PULL_CTL */ +#define PMIC_GPIO_REG_PULL_SHIFT 0 +#define PMIC_GPIO_REG_PULL_MASK 0x7 + +#define PMIC_GPIO_PULL_DOWN 4 +#define PMIC_GPIO_PULL_DISABLE 5 + +/* PMIC_GPIO_REG_LV_MV_DIG_OUT_SOURCE_CTL for LV/MV */ +#define PMIC_GPIO_LV_MV_OUTPUT_INVERT 0x80 +#define PMIC_GPIO_LV_MV_OUTPUT_INVERT_SHIFT 7 +#define PMIC_GPIO_LV_MV_OUTPUT_SOURCE_SEL_MASK 0xF + +/* PMIC_GPIO_REG_DIG_IN_CTL */ +#define PMIC_GPIO_LV_MV_DIG_IN_DTEST_EN 0x80 +#define PMIC_GPIO_LV_MV_DIG_IN_DTEST_SEL_MASK 0x7 +#define PMIC_GPIO_DIG_IN_DTEST_SEL_MASK 0xf + +/* PMIC_GPIO_REG_DIG_OUT_CTL */ +#define PMIC_GPIO_REG_OUT_STRENGTH_SHIFT 0 +#define PMIC_GPIO_REG_OUT_STRENGTH_MASK 0x3 +#define PMIC_GPIO_REG_OUT_TYPE_SHIFT 4 +#define PMIC_GPIO_REG_OUT_TYPE_MASK 0x3 + +/* + * Output type - indicates pin should be configured as push-pull, + * open drain or open source. + */ +#define PMIC_GPIO_OUT_BUF_CMOS 0 +#define PMIC_GPIO_OUT_BUF_OPEN_DRAIN_NMOS 1 +#define PMIC_GPIO_OUT_BUF_OPEN_DRAIN_PMOS 2 + +#define PMIC_GPIO_OUT_STRENGTH_LOW 1 +#define PMIC_GPIO_OUT_STRENGTH_HIGH 3 + +/* PMIC_GPIO_REG_EN_CTL */ +#define PMIC_GPIO_REG_MASTER_EN_SHIFT 7 + +#define PMIC_GPIO_PHYSICAL_OFFSET 1 + +/* PMIC_GPIO_REG_LV_MV_ANA_PASS_THRU_SEL */ +#define PMIC_GPIO_LV_MV_ANA_MUX_SEL_MASK 0x3 + +/* Qualcomm specific pin configurations */ +#define PMIC_GPIO_CONF_PULL_UP (PIN_CONFIG_END + 1) +#define PMIC_GPIO_CONF_STRENGTH (PIN_CONFIG_END + 2) +#define PMIC_GPIO_CONF_ATEST (PIN_CONFIG_END + 3) +#define PMIC_GPIO_CONF_ANALOG_PASS (PIN_CONFIG_END + 4) +#define PMIC_GPIO_CONF_DTEST_BUFFER (PIN_CONFIG_END + 5) + +/* The index of each function in pmic_gpio_functions[] array */ +enum pmic_gpio_func_index { + PMIC_GPIO_FUNC_INDEX_NORMAL, + PMIC_GPIO_FUNC_INDEX_PAIRED, + PMIC_GPIO_FUNC_INDEX_FUNC1, + PMIC_GPIO_FUNC_INDEX_FUNC2, + PMIC_GPIO_FUNC_INDEX_FUNC3, + PMIC_GPIO_FUNC_INDEX_FUNC4, + PMIC_GPIO_FUNC_INDEX_DTEST1, + PMIC_GPIO_FUNC_INDEX_DTEST2, + PMIC_GPIO_FUNC_INDEX_DTEST3, + PMIC_GPIO_FUNC_INDEX_DTEST4, +}; + +/** + * struct pmic_gpio_pad - keep current GPIO settings + * @base: Address base in SPMI device. + * @is_enabled: Set to false when GPIO should be put in high Z state. + * @out_value: Cached pin output value + * @have_buffer: Set to true if GPIO output could be configured in push-pull, + * open-drain or open-source mode. + * @output_enabled: Set to true if GPIO output logic is enabled. + * @input_enabled: Set to true if GPIO input buffer logic is enabled. + * @analog_pass: Set to true if GPIO is in analog-pass-through mode. + * @lv_mv_type: Set to true if GPIO subtype is GPIO_LV(0x10) or GPIO_MV(0x11). + * @num_sources: Number of power-sources supported by this GPIO. + * @power_source: Current power-source used. + * @buffer_type: Push-pull, open-drain or open-source. + * @pullup: Constant current which flow trough GPIO output buffer. + * @strength: No, Low, Medium, High + * @function: See pmic_gpio_functions[] + * @atest: the ATEST selection for GPIO analog-pass-through mode + * @dtest_buffer: the DTEST buffer selection for digital input mode. + */ +struct pmic_gpio_pad { + u16 base; + bool is_enabled; + bool out_value; + bool have_buffer; + bool output_enabled; + bool input_enabled; + bool analog_pass; + bool lv_mv_type; + unsigned int num_sources; + unsigned int power_source; + unsigned int buffer_type; + unsigned int pullup; + unsigned int strength; + unsigned int function; + unsigned int atest; + unsigned int dtest_buffer; +}; + +struct pmic_gpio_state { + struct device *dev; + struct regmap *map; + struct pinctrl_dev *ctrl; + struct gpio_chip chip; + u8 usid; + u8 pid_base; +}; + +static const struct pinconf_generic_params pmic_gpio_bindings[] = { + {"qcom,pull-up-strength", PMIC_GPIO_CONF_PULL_UP, 0}, + {"qcom,drive-strength", PMIC_GPIO_CONF_STRENGTH, 0}, + {"qcom,atest", PMIC_GPIO_CONF_ATEST, 0}, + {"qcom,analog-pass", PMIC_GPIO_CONF_ANALOG_PASS, 0}, + {"qcom,dtest-buffer", PMIC_GPIO_CONF_DTEST_BUFFER, 0}, +}; + +#ifdef CONFIG_DEBUG_FS +static const struct pin_config_item pmic_conf_items[ARRAY_SIZE(pmic_gpio_bindings)] = { + PCONFDUMP(PMIC_GPIO_CONF_PULL_UP, "pull up strength", NULL, true), + PCONFDUMP(PMIC_GPIO_CONF_STRENGTH, "drive-strength", NULL, true), + PCONFDUMP(PMIC_GPIO_CONF_ATEST, "atest", NULL, true), + PCONFDUMP(PMIC_GPIO_CONF_ANALOG_PASS, "analog-pass", NULL, true), + PCONFDUMP(PMIC_GPIO_CONF_DTEST_BUFFER, "dtest-buffer", NULL, true), +}; +#endif + +static const char *const pmic_gpio_groups[] = { + "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7", "gpio8", + "gpio9", "gpio10", "gpio11", "gpio12", "gpio13", "gpio14", "gpio15", + "gpio16", "gpio17", "gpio18", "gpio19", "gpio20", "gpio21", "gpio22", + "gpio23", "gpio24", "gpio25", "gpio26", "gpio27", "gpio28", "gpio29", + "gpio30", "gpio31", "gpio32", "gpio33", "gpio34", "gpio35", "gpio36", +}; + +static const char *const pmic_gpio_functions[] = { + [PMIC_GPIO_FUNC_INDEX_NORMAL] = PMIC_GPIO_FUNC_NORMAL, + [PMIC_GPIO_FUNC_INDEX_PAIRED] = PMIC_GPIO_FUNC_PAIRED, + [PMIC_GPIO_FUNC_INDEX_FUNC1] = PMIC_GPIO_FUNC_FUNC1, + [PMIC_GPIO_FUNC_INDEX_FUNC2] = PMIC_GPIO_FUNC_FUNC2, + [PMIC_GPIO_FUNC_INDEX_FUNC3] = PMIC_GPIO_FUNC_FUNC3, + [PMIC_GPIO_FUNC_INDEX_FUNC4] = PMIC_GPIO_FUNC_FUNC4, + [PMIC_GPIO_FUNC_INDEX_DTEST1] = PMIC_GPIO_FUNC_DTEST1, + [PMIC_GPIO_FUNC_INDEX_DTEST2] = PMIC_GPIO_FUNC_DTEST2, + [PMIC_GPIO_FUNC_INDEX_DTEST3] = PMIC_GPIO_FUNC_DTEST3, + [PMIC_GPIO_FUNC_INDEX_DTEST4] = PMIC_GPIO_FUNC_DTEST4, +}; + +static int pmic_gpio_read(struct pmic_gpio_state *state, + struct pmic_gpio_pad *pad, unsigned int addr) +{ + unsigned int val; + int ret; + + ret = regmap_read(state->map, pad->base + addr, &val); + if (ret < 0) + dev_err(state->dev, "read 0x%x failed\n", addr); + else + ret = val; + + return ret; +} + +static int pmic_gpio_write(struct pmic_gpio_state *state, + struct pmic_gpio_pad *pad, unsigned int addr, + unsigned int val) +{ + int ret; + + ret = regmap_write(state->map, pad->base + addr, val); + if (ret < 0) + dev_err(state->dev, "write 0x%x failed\n", addr); + + return ret; +} + +static int pmic_gpio_get_groups_count(struct pinctrl_dev *pctldev) +{ + /* Every PIN is a group */ + return pctldev->desc->npins; +} + +static const char *pmic_gpio_get_group_name(struct pinctrl_dev *pctldev, + unsigned pin) +{ + return pctldev->desc->pins[pin].name; +} + +static int pmic_gpio_get_group_pins(struct pinctrl_dev *pctldev, unsigned pin, + const unsigned **pins, unsigned *num_pins) +{ + *pins = &pctldev->desc->pins[pin].number; + *num_pins = 1; + return 0; +} + +static const struct pinctrl_ops pmic_gpio_pinctrl_ops = { + .get_groups_count = pmic_gpio_get_groups_count, + .get_group_name = pmic_gpio_get_group_name, + .get_group_pins = pmic_gpio_get_group_pins, + .dt_node_to_map = pinconf_generic_dt_node_to_map_group, + .dt_free_map = pinctrl_utils_free_map, +}; + +static int pmic_gpio_get_functions_count(struct pinctrl_dev *pctldev) +{ + return ARRAY_SIZE(pmic_gpio_functions); +} + +static const char *pmic_gpio_get_function_name(struct pinctrl_dev *pctldev, + unsigned function) +{ + return pmic_gpio_functions[function]; +} + +static int pmic_gpio_get_function_groups(struct pinctrl_dev *pctldev, + unsigned function, + const char *const **groups, + unsigned *const num_qgroups) +{ + *groups = pmic_gpio_groups; + *num_qgroups = pctldev->desc->npins; + return 0; +} + +static int pmic_gpio_set_mux(struct pinctrl_dev *pctldev, unsigned function, + unsigned pin) +{ + struct pmic_gpio_state *state = pinctrl_dev_get_drvdata(pctldev); + struct pmic_gpio_pad *pad; + unsigned int val; + int ret; + + if (function > PMIC_GPIO_FUNC_INDEX_DTEST4) { + pr_err("function: %d is not defined\n", function); + return -EINVAL; + } + + pad = pctldev->desc->pins[pin].drv_data; + /* + * Non-LV/MV subtypes only support 2 special functions, + * offsetting the dtestx function values by 2 + */ + if (!pad->lv_mv_type) { + if (function == PMIC_GPIO_FUNC_INDEX_FUNC3 || + function == PMIC_GPIO_FUNC_INDEX_FUNC4) { + pr_err("LV/MV subtype doesn't have func3/func4\n"); + return -EINVAL; + } + if (function >= PMIC_GPIO_FUNC_INDEX_DTEST1) + function -= (PMIC_GPIO_FUNC_INDEX_DTEST1 - + PMIC_GPIO_FUNC_INDEX_FUNC3); + } + + pad->function = function; + + if (pad->analog_pass) + val = PMIC_GPIO_MODE_ANALOG_PASS_THRU; + else if (pad->output_enabled && pad->input_enabled) + val = PMIC_GPIO_MODE_DIGITAL_INPUT_OUTPUT; + else if (pad->output_enabled) + val = PMIC_GPIO_MODE_DIGITAL_OUTPUT; + else + val = PMIC_GPIO_MODE_DIGITAL_INPUT; + + if (pad->lv_mv_type) { + ret = pmic_gpio_write(state, pad, + PMIC_GPIO_REG_MODE_CTL, val); + if (ret < 0) + return ret; + + val = pad->atest - 1; + ret = pmic_gpio_write(state, pad, + PMIC_GPIO_REG_LV_MV_ANA_PASS_THRU_SEL, val); + if (ret < 0) + return ret; + + val = pad->out_value + << PMIC_GPIO_LV_MV_OUTPUT_INVERT_SHIFT; + val |= pad->function + & PMIC_GPIO_LV_MV_OUTPUT_SOURCE_SEL_MASK; + ret = pmic_gpio_write(state, pad, + PMIC_GPIO_REG_LV_MV_DIG_OUT_SOURCE_CTL, val); + if (ret < 0) + return ret; + } else { + val = val << PMIC_GPIO_REG_MODE_DIR_SHIFT; + val |= pad->function << PMIC_GPIO_REG_MODE_FUNCTION_SHIFT; + val |= pad->out_value & PMIC_GPIO_REG_MODE_VALUE_SHIFT; + + ret = pmic_gpio_write(state, pad, PMIC_GPIO_REG_MODE_CTL, val); + if (ret < 0) + return ret; + } + + val = pad->is_enabled << PMIC_GPIO_REG_MASTER_EN_SHIFT; + + return pmic_gpio_write(state, pad, PMIC_GPIO_REG_EN_CTL, val); +} + +static const struct pinmux_ops pmic_gpio_pinmux_ops = { + .get_functions_count = pmic_gpio_get_functions_count, + .get_function_name = pmic_gpio_get_function_name, + .get_function_groups = pmic_gpio_get_function_groups, + .set_mux = pmic_gpio_set_mux, +}; + +static int pmic_gpio_config_get(struct pinctrl_dev *pctldev, + unsigned int pin, unsigned long *config) +{ + unsigned param = pinconf_to_config_param(*config); + struct pmic_gpio_pad *pad; + unsigned arg; + + pad = pctldev->desc->pins[pin].drv_data; + + switch (param) { + case PIN_CONFIG_DRIVE_PUSH_PULL: + if (pad->buffer_type != PMIC_GPIO_OUT_BUF_CMOS) + return -EINVAL; + arg = 1; + break; + case PIN_CONFIG_DRIVE_OPEN_DRAIN: + if (pad->buffer_type != PMIC_GPIO_OUT_BUF_OPEN_DRAIN_NMOS) + return -EINVAL; + arg = 1; + break; + case PIN_CONFIG_DRIVE_OPEN_SOURCE: + if (pad->buffer_type != PMIC_GPIO_OUT_BUF_OPEN_DRAIN_PMOS) + return -EINVAL; + arg = 1; + break; + case PIN_CONFIG_BIAS_PULL_DOWN: + if (pad->pullup != PMIC_GPIO_PULL_DOWN) + return -EINVAL; + arg = 1; + break; + case PIN_CONFIG_BIAS_DISABLE: + if (pad->pullup != PMIC_GPIO_PULL_DISABLE) + return -EINVAL; + arg = 1; + break; + case PIN_CONFIG_BIAS_PULL_UP: + if (pad->pullup != PMIC_GPIO_PULL_UP_30) + return -EINVAL; + arg = 1; + break; + case PIN_CONFIG_BIAS_HIGH_IMPEDANCE: + if (pad->is_enabled) + return -EINVAL; + arg = 1; + break; + case PIN_CONFIG_POWER_SOURCE: + arg = pad->power_source; + break; + case PIN_CONFIG_INPUT_ENABLE: + if (!pad->input_enabled) + return -EINVAL; + arg = 1; + break; + case PIN_CONFIG_OUTPUT_ENABLE: + arg = pad->output_enabled; + break; + case PIN_CONFIG_OUTPUT: + arg = pad->out_value; + break; + case PMIC_GPIO_CONF_PULL_UP: + arg = pad->pullup; + break; + case PMIC_GPIO_CONF_STRENGTH: + switch (pad->strength) { + case PMIC_GPIO_OUT_STRENGTH_HIGH: + arg = PMIC_GPIO_STRENGTH_HIGH; + break; + case PMIC_GPIO_OUT_STRENGTH_LOW: + arg = PMIC_GPIO_STRENGTH_LOW; + break; + default: + arg = pad->strength; + break; + } + break; + case PMIC_GPIO_CONF_ATEST: + arg = pad->atest; + break; + case PMIC_GPIO_CONF_ANALOG_PASS: + arg = pad->analog_pass; + break; + case PMIC_GPIO_CONF_DTEST_BUFFER: + arg = pad->dtest_buffer; + break; + default: + return -EINVAL; + } + + *config = pinconf_to_config_packed(param, arg); + return 0; +} + +static int pmic_gpio_config_set(struct pinctrl_dev *pctldev, unsigned int pin, + unsigned long *configs, unsigned nconfs) +{ + struct pmic_gpio_state *state = pinctrl_dev_get_drvdata(pctldev); + struct pmic_gpio_pad *pad; + unsigned param, arg; + unsigned int val; + int i, ret; + + pad = pctldev->desc->pins[pin].drv_data; + + pad->is_enabled = true; + for (i = 0; i < nconfs; i++) { + param = pinconf_to_config_param(configs[i]); + arg = pinconf_to_config_argument(configs[i]); + + switch (param) { + case PIN_CONFIG_DRIVE_PUSH_PULL: + pad->buffer_type = PMIC_GPIO_OUT_BUF_CMOS; + break; + case PIN_CONFIG_DRIVE_OPEN_DRAIN: + if (!pad->have_buffer) + return -EINVAL; + pad->buffer_type = PMIC_GPIO_OUT_BUF_OPEN_DRAIN_NMOS; + break; + case PIN_CONFIG_DRIVE_OPEN_SOURCE: + if (!pad->have_buffer) + return -EINVAL; + pad->buffer_type = PMIC_GPIO_OUT_BUF_OPEN_DRAIN_PMOS; + break; + case PIN_CONFIG_BIAS_DISABLE: + pad->pullup = PMIC_GPIO_PULL_DISABLE; + break; + case PIN_CONFIG_BIAS_PULL_UP: + pad->pullup = PMIC_GPIO_PULL_UP_30; + break; + case PIN_CONFIG_BIAS_PULL_DOWN: + if (arg) + pad->pullup = PMIC_GPIO_PULL_DOWN; + else + pad->pullup = PMIC_GPIO_PULL_DISABLE; + break; + case PIN_CONFIG_BIAS_HIGH_IMPEDANCE: + pad->is_enabled = false; + break; + case PIN_CONFIG_POWER_SOURCE: + if (arg >= pad->num_sources) + return -EINVAL; + pad->power_source = arg; + break; + case PIN_CONFIG_INPUT_ENABLE: + pad->input_enabled = arg ? true : false; + break; + case PIN_CONFIG_OUTPUT_ENABLE: + pad->output_enabled = arg ? true : false; + break; + case PIN_CONFIG_OUTPUT: + pad->output_enabled = true; + pad->out_value = arg; + break; + case PMIC_GPIO_CONF_PULL_UP: + if (arg > PMIC_GPIO_PULL_UP_1P5_30) + return -EINVAL; + pad->pullup = arg; + break; + case PMIC_GPIO_CONF_STRENGTH: + if (arg > PMIC_GPIO_STRENGTH_LOW) + return -EINVAL; + switch (arg) { + case PMIC_GPIO_STRENGTH_HIGH: + pad->strength = PMIC_GPIO_OUT_STRENGTH_HIGH; + break; + case PMIC_GPIO_STRENGTH_LOW: + pad->strength = PMIC_GPIO_OUT_STRENGTH_LOW; + break; + default: + pad->strength = arg; + break; + } + break; + case PMIC_GPIO_CONF_ATEST: + if (!pad->lv_mv_type || arg > 4) + return -EINVAL; + pad->atest = arg; + break; + case PMIC_GPIO_CONF_ANALOG_PASS: + if (!pad->lv_mv_type) + return -EINVAL; + pad->analog_pass = true; + break; + case PMIC_GPIO_CONF_DTEST_BUFFER: + if (arg > 4) + return -EINVAL; + pad->dtest_buffer = arg; + break; + default: + return -EINVAL; + } + } + + val = pad->power_source << PMIC_GPIO_REG_VIN_SHIFT; + + ret = pmic_gpio_write(state, pad, PMIC_GPIO_REG_DIG_VIN_CTL, val); + if (ret < 0) + return ret; + + val = pad->pullup << PMIC_GPIO_REG_PULL_SHIFT; + + ret = pmic_gpio_write(state, pad, PMIC_GPIO_REG_DIG_PULL_CTL, val); + if (ret < 0) + return ret; + + val = pad->buffer_type << PMIC_GPIO_REG_OUT_TYPE_SHIFT; + val |= pad->strength << PMIC_GPIO_REG_OUT_STRENGTH_SHIFT; + + ret = pmic_gpio_write(state, pad, PMIC_GPIO_REG_DIG_OUT_CTL, val); + if (ret < 0) + return ret; + + if (pad->dtest_buffer == 0) { + val = 0; + } else { + if (pad->lv_mv_type) { + val = pad->dtest_buffer - 1; + val |= PMIC_GPIO_LV_MV_DIG_IN_DTEST_EN; + } else { + val = BIT(pad->dtest_buffer - 1); + } + } + ret = pmic_gpio_write(state, pad, PMIC_GPIO_REG_DIG_IN_CTL, val); + if (ret < 0) + return ret; + + if (pad->analog_pass) + val = PMIC_GPIO_MODE_ANALOG_PASS_THRU; + else if (pad->output_enabled && pad->input_enabled) + val = PMIC_GPIO_MODE_DIGITAL_INPUT_OUTPUT; + else if (pad->output_enabled) + val = PMIC_GPIO_MODE_DIGITAL_OUTPUT; + else + val = PMIC_GPIO_MODE_DIGITAL_INPUT; + + if (pad->lv_mv_type) { + ret = pmic_gpio_write(state, pad, + PMIC_GPIO_REG_MODE_CTL, val); + if (ret < 0) + return ret; + + val = pad->atest - 1; + ret = pmic_gpio_write(state, pad, + PMIC_GPIO_REG_LV_MV_ANA_PASS_THRU_SEL, val); + if (ret < 0) + return ret; + + val = pad->out_value + << PMIC_GPIO_LV_MV_OUTPUT_INVERT_SHIFT; + val |= pad->function + & PMIC_GPIO_LV_MV_OUTPUT_SOURCE_SEL_MASK; + ret = pmic_gpio_write(state, pad, + PMIC_GPIO_REG_LV_MV_DIG_OUT_SOURCE_CTL, val); + if (ret < 0) + return ret; + } else { + val = val << PMIC_GPIO_REG_MODE_DIR_SHIFT; + val |= pad->function << PMIC_GPIO_REG_MODE_FUNCTION_SHIFT; + val |= pad->out_value & PMIC_GPIO_REG_MODE_VALUE_SHIFT; + + ret = pmic_gpio_write(state, pad, PMIC_GPIO_REG_MODE_CTL, val); + if (ret < 0) + return ret; + } + + val = pad->is_enabled << PMIC_GPIO_REG_MASTER_EN_SHIFT; + + ret = pmic_gpio_write(state, pad, PMIC_GPIO_REG_EN_CTL, val); + + return ret; +} + +static void pmic_gpio_config_dbg_show(struct pinctrl_dev *pctldev, + struct seq_file *s, unsigned pin) +{ + struct pmic_gpio_state *state = pinctrl_dev_get_drvdata(pctldev); + struct pmic_gpio_pad *pad; + int ret, val, function; + + static const char *const biases[] = { + "pull-up 30uA", "pull-up 1.5uA", "pull-up 31.5uA", + "pull-up 1.5uA + 30uA boost", "pull-down 10uA", "no pull" + }; + static const char *const buffer_types[] = { + "push-pull", "open-drain", "open-source" + }; + static const char *const strengths[] = { + "no", "high", "medium", "low" + }; + + pad = pctldev->desc->pins[pin].drv_data; + + seq_printf(s, " gpio%-2d:", pin + PMIC_GPIO_PHYSICAL_OFFSET); + + val = pmic_gpio_read(state, pad, PMIC_GPIO_REG_EN_CTL); + + if (val < 0 || !(val >> PMIC_GPIO_REG_MASTER_EN_SHIFT)) { + seq_puts(s, " ---"); + } else { + if (pad->input_enabled) { + ret = pmic_gpio_read(state, pad, PMIC_MPP_REG_RT_STS); + if (ret < 0) + return; + + ret &= PMIC_MPP_REG_RT_STS_VAL_MASK; + pad->out_value = ret; + } + /* + * For the non-LV/MV subtypes only 2 special functions are + * available, offsetting the dtest function values by 2. + */ + function = pad->function; + if (!pad->lv_mv_type && + pad->function >= PMIC_GPIO_FUNC_INDEX_FUNC3) + function += PMIC_GPIO_FUNC_INDEX_DTEST1 - + PMIC_GPIO_FUNC_INDEX_FUNC3; + + if (pad->analog_pass) + seq_puts(s, " analog-pass"); + else + seq_printf(s, " %-4s", + pad->output_enabled ? "out" : "in"); + seq_printf(s, " %-4s", pad->out_value ? "high" : "low"); + seq_printf(s, " %-7s", pmic_gpio_functions[function]); + seq_printf(s, " vin-%d", pad->power_source); + seq_printf(s, " %-27s", biases[pad->pullup]); + seq_printf(s, " %-10s", buffer_types[pad->buffer_type]); + seq_printf(s, " %-7s", strengths[pad->strength]); + seq_printf(s, " atest-%d", pad->atest); + seq_printf(s, " dtest-%d", pad->dtest_buffer); + } +} + +static const struct pinconf_ops pmic_gpio_pinconf_ops = { + .is_generic = true, + .pin_config_group_get = pmic_gpio_config_get, + .pin_config_group_set = pmic_gpio_config_set, + .pin_config_group_dbg_show = pmic_gpio_config_dbg_show, +}; + +static int pmic_gpio_direction_input(struct gpio_chip *chip, unsigned pin) +{ + struct pmic_gpio_state *state = gpiochip_get_data(chip); + unsigned long config; + + config = pinconf_to_config_packed(PIN_CONFIG_INPUT_ENABLE, 1); + + return pmic_gpio_config_set(state->ctrl, pin, &config, 1); +} + +static int pmic_gpio_direction_output(struct gpio_chip *chip, + unsigned pin, int val) +{ + struct pmic_gpio_state *state = gpiochip_get_data(chip); + unsigned long config; + + config = pinconf_to_config_packed(PIN_CONFIG_OUTPUT, val); + + return pmic_gpio_config_set(state->ctrl, pin, &config, 1); +} + +static int pmic_gpio_get(struct gpio_chip *chip, unsigned pin) +{ + struct pmic_gpio_state *state = gpiochip_get_data(chip); + struct pmic_gpio_pad *pad; + int ret; + + pad = state->ctrl->desc->pins[pin].drv_data; + + if (!pad->is_enabled) + return -EINVAL; + + if (pad->input_enabled) { + ret = pmic_gpio_read(state, pad, PMIC_MPP_REG_RT_STS); + if (ret < 0) + return ret; + + pad->out_value = ret & PMIC_MPP_REG_RT_STS_VAL_MASK; + } + + return !!pad->out_value; +} + +static void pmic_gpio_set(struct gpio_chip *chip, unsigned pin, int value) +{ + struct pmic_gpio_state *state = gpiochip_get_data(chip); + unsigned long config; + + config = pinconf_to_config_packed(PIN_CONFIG_OUTPUT, value); + + pmic_gpio_config_set(state->ctrl, pin, &config, 1); +} + +static int pmic_gpio_of_xlate(struct gpio_chip *chip, + const struct of_phandle_args *gpio_desc, + u32 *flags) +{ + if (chip->of_gpio_n_cells < 2) + return -EINVAL; + + if (flags) + *flags = gpio_desc->args[1]; + + return gpio_desc->args[0] - PMIC_GPIO_PHYSICAL_OFFSET; +} + +static void pmic_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip) +{ + struct pmic_gpio_state *state = gpiochip_get_data(chip); + unsigned i; + + for (i = 0; i < chip->ngpio; i++) { + pmic_gpio_config_dbg_show(state->ctrl, s, i); + seq_puts(s, "\n"); + } +} + +static const struct gpio_chip pmic_gpio_gpio_template = { + .direction_input = pmic_gpio_direction_input, + .direction_output = pmic_gpio_direction_output, + .get = pmic_gpio_get, + .set = pmic_gpio_set, + .request = gpiochip_generic_request, + .free = gpiochip_generic_free, + .of_xlate = pmic_gpio_of_xlate, + .dbg_show = pmic_gpio_dbg_show, +}; + +static int pmic_gpio_populate(struct pmic_gpio_state *state, + struct pmic_gpio_pad *pad) +{ + int type, subtype, val, dir; + + type = pmic_gpio_read(state, pad, PMIC_GPIO_REG_TYPE); + if (type < 0) + return type; + + if (type != PMIC_GPIO_TYPE) { + dev_err(state->dev, "incorrect block type 0x%x at 0x%x\n", + type, pad->base); + return -ENODEV; + } + + subtype = pmic_gpio_read(state, pad, PMIC_GPIO_REG_SUBTYPE); + if (subtype < 0) + return subtype; + + switch (subtype) { + case PMIC_GPIO_SUBTYPE_GPIO_4CH: + pad->have_buffer = true; + fallthrough; + case PMIC_GPIO_SUBTYPE_GPIOC_4CH: + pad->num_sources = 4; + break; + case PMIC_GPIO_SUBTYPE_GPIO_8CH: + pad->have_buffer = true; + fallthrough; + case PMIC_GPIO_SUBTYPE_GPIOC_8CH: + pad->num_sources = 8; + break; + case PMIC_GPIO_SUBTYPE_GPIO_LV: + pad->num_sources = 1; + pad->have_buffer = true; + pad->lv_mv_type = true; + break; + case PMIC_GPIO_SUBTYPE_GPIO_MV: + pad->num_sources = 2; + pad->have_buffer = true; + pad->lv_mv_type = true; + break; + case PMIC_GPIO_SUBTYPE_GPIO_LV_VIN2: + pad->num_sources = 2; + pad->have_buffer = true; + pad->lv_mv_type = true; + break; + case PMIC_GPIO_SUBTYPE_GPIO_MV_VIN3: + pad->num_sources = 3; + pad->have_buffer = true; + pad->lv_mv_type = true; + break; + default: + dev_err(state->dev, "unknown GPIO type 0x%x\n", subtype); + return -ENODEV; + } + + if (pad->lv_mv_type) { + val = pmic_gpio_read(state, pad, + PMIC_GPIO_REG_LV_MV_DIG_OUT_SOURCE_CTL); + if (val < 0) + return val; + + pad->out_value = !!(val & PMIC_GPIO_LV_MV_OUTPUT_INVERT); + pad->function = val & PMIC_GPIO_LV_MV_OUTPUT_SOURCE_SEL_MASK; + + val = pmic_gpio_read(state, pad, PMIC_GPIO_REG_MODE_CTL); + if (val < 0) + return val; + + dir = val & PMIC_GPIO_REG_LV_MV_MODE_DIR_MASK; + } else { + val = pmic_gpio_read(state, pad, PMIC_GPIO_REG_MODE_CTL); + if (val < 0) + return val; + + pad->out_value = val & PMIC_GPIO_REG_MODE_VALUE_SHIFT; + + dir = val >> PMIC_GPIO_REG_MODE_DIR_SHIFT; + dir &= PMIC_GPIO_REG_MODE_DIR_MASK; + pad->function = val >> PMIC_GPIO_REG_MODE_FUNCTION_SHIFT; + pad->function &= PMIC_GPIO_REG_MODE_FUNCTION_MASK; + } + + switch (dir) { + case PMIC_GPIO_MODE_DIGITAL_INPUT: + pad->input_enabled = true; + pad->output_enabled = false; + break; + case PMIC_GPIO_MODE_DIGITAL_OUTPUT: + pad->input_enabled = false; + pad->output_enabled = true; + break; + case PMIC_GPIO_MODE_DIGITAL_INPUT_OUTPUT: + pad->input_enabled = true; + pad->output_enabled = true; + break; + case PMIC_GPIO_MODE_ANALOG_PASS_THRU: + if (!pad->lv_mv_type) + return -ENODEV; + pad->analog_pass = true; + break; + default: + dev_err(state->dev, "unknown GPIO direction\n"); + return -ENODEV; + } + + val = pmic_gpio_read(state, pad, PMIC_GPIO_REG_DIG_VIN_CTL); + if (val < 0) + return val; + + pad->power_source = val >> PMIC_GPIO_REG_VIN_SHIFT; + pad->power_source &= PMIC_GPIO_REG_VIN_MASK; + + val = pmic_gpio_read(state, pad, PMIC_GPIO_REG_DIG_PULL_CTL); + if (val < 0) + return val; + + pad->pullup = val >> PMIC_GPIO_REG_PULL_SHIFT; + pad->pullup &= PMIC_GPIO_REG_PULL_MASK; + + val = pmic_gpio_read(state, pad, PMIC_GPIO_REG_DIG_IN_CTL); + if (val < 0) + return val; + + if (pad->lv_mv_type && (val & PMIC_GPIO_LV_MV_DIG_IN_DTEST_EN)) + pad->dtest_buffer = + (val & PMIC_GPIO_LV_MV_DIG_IN_DTEST_SEL_MASK) + 1; + else if (!pad->lv_mv_type) + pad->dtest_buffer = ffs(val); + else + pad->dtest_buffer = 0; + + val = pmic_gpio_read(state, pad, PMIC_GPIO_REG_DIG_OUT_CTL); + if (val < 0) + return val; + + pad->strength = val >> PMIC_GPIO_REG_OUT_STRENGTH_SHIFT; + pad->strength &= PMIC_GPIO_REG_OUT_STRENGTH_MASK; + + pad->buffer_type = val >> PMIC_GPIO_REG_OUT_TYPE_SHIFT; + pad->buffer_type &= PMIC_GPIO_REG_OUT_TYPE_MASK; + + if (pad->lv_mv_type) { + val = pmic_gpio_read(state, pad, + PMIC_GPIO_REG_LV_MV_ANA_PASS_THRU_SEL); + if (val < 0) + return val; + pad->atest = (val & PMIC_GPIO_LV_MV_ANA_MUX_SEL_MASK) + 1; + } + + /* Pin could be disabled with PIN_CONFIG_BIAS_HIGH_IMPEDANCE */ + pad->is_enabled = true; + return 0; +} + +static int pmic_gpio_domain_translate(struct irq_domain *domain, + struct irq_fwspec *fwspec, + unsigned long *hwirq, + unsigned int *type) +{ + struct pmic_gpio_state *state = container_of(domain->host_data, + struct pmic_gpio_state, + chip); + + if (fwspec->param_count != 2 || + fwspec->param[0] < 1 || fwspec->param[0] > state->chip.ngpio) + return -EINVAL; + + *hwirq = fwspec->param[0] - PMIC_GPIO_PHYSICAL_OFFSET; + *type = fwspec->param[1]; + + return 0; +} + +static unsigned int pmic_gpio_child_offset_to_irq(struct gpio_chip *chip, + unsigned int offset) +{ + return offset + PMIC_GPIO_PHYSICAL_OFFSET; +} + +static int pmic_gpio_child_to_parent_hwirq(struct gpio_chip *chip, + unsigned int child_hwirq, + unsigned int child_type, + unsigned int *parent_hwirq, + unsigned int *parent_type) +{ + struct pmic_gpio_state *state = gpiochip_get_data(chip); + + *parent_hwirq = child_hwirq + state->pid_base; + *parent_type = child_type; + + return 0; +} + +static int pmic_gpio_populate_parent_fwspec(struct gpio_chip *chip, + union gpio_irq_fwspec *gfwspec, + unsigned int parent_hwirq, + unsigned int parent_type) +{ + struct pmic_gpio_state *state = gpiochip_get_data(chip); + struct irq_fwspec *fwspec = &gfwspec->fwspec; + + fwspec->fwnode = chip->irq.parent_domain->fwnode; + + fwspec->param_count = 4; + fwspec->param[0] = state->usid; + fwspec->param[1] = parent_hwirq; + /* param[2] must be left as 0 */ + fwspec->param[3] = parent_type; + + return 0; +} + +static void pmic_gpio_irq_mask(struct irq_data *data) +{ + struct gpio_chip *gc = irq_data_get_irq_chip_data(data); + + irq_chip_mask_parent(data); + gpiochip_disable_irq(gc, data->hwirq); +} + +static void pmic_gpio_irq_unmask(struct irq_data *data) +{ + struct gpio_chip *gc = irq_data_get_irq_chip_data(data); + + gpiochip_enable_irq(gc, data->hwirq); + irq_chip_unmask_parent(data); +} + +static const struct irq_chip spmi_gpio_irq_chip = { + .name = "spmi-gpio", + .irq_ack = irq_chip_ack_parent, + .irq_mask = pmic_gpio_irq_mask, + .irq_unmask = pmic_gpio_irq_unmask, + .irq_set_type = irq_chip_set_type_parent, + .irq_set_wake = irq_chip_set_wake_parent, + .flags = IRQCHIP_IMMUTABLE | IRQCHIP_MASK_ON_SUSPEND, + GPIOCHIP_IRQ_RESOURCE_HELPERS, +}; + +static int pmic_gpio_probe(struct platform_device *pdev) +{ + struct irq_domain *parent_domain; + struct device_node *parent_node; + struct device *dev = &pdev->dev; + struct pinctrl_pin_desc *pindesc; + struct pinctrl_desc *pctrldesc; + struct pmic_gpio_pad *pad, *pads; + struct pmic_gpio_state *state; + struct gpio_irq_chip *girq; + const struct spmi_device *parent_spmi_dev; + int ret, npins, i; + u32 reg; + + ret = of_property_read_u32(dev->of_node, "reg", ®); + if (ret < 0) { + dev_err(dev, "missing base address"); + return ret; + } + + npins = (uintptr_t) device_get_match_data(&pdev->dev); + + state = devm_kzalloc(dev, sizeof(*state), GFP_KERNEL); + if (!state) + return -ENOMEM; + + platform_set_drvdata(pdev, state); + + state->dev = &pdev->dev; + state->map = dev_get_regmap(dev->parent, NULL); + parent_spmi_dev = to_spmi_device(dev->parent); + state->usid = parent_spmi_dev->usid; + state->pid_base = reg >> 8; + + pindesc = devm_kcalloc(dev, npins, sizeof(*pindesc), GFP_KERNEL); + if (!pindesc) + return -ENOMEM; + + pads = devm_kcalloc(dev, npins, sizeof(*pads), GFP_KERNEL); + if (!pads) + return -ENOMEM; + + pctrldesc = devm_kzalloc(dev, sizeof(*pctrldesc), GFP_KERNEL); + if (!pctrldesc) + return -ENOMEM; + + pctrldesc->pctlops = &pmic_gpio_pinctrl_ops; + pctrldesc->pmxops = &pmic_gpio_pinmux_ops; + pctrldesc->confops = &pmic_gpio_pinconf_ops; + pctrldesc->owner = THIS_MODULE; + pctrldesc->name = dev_name(dev); + pctrldesc->pins = pindesc; + pctrldesc->npins = npins; + pctrldesc->num_custom_params = ARRAY_SIZE(pmic_gpio_bindings); + pctrldesc->custom_params = pmic_gpio_bindings; +#ifdef CONFIG_DEBUG_FS + pctrldesc->custom_conf_items = pmic_conf_items; +#endif + + for (i = 0; i < npins; i++, pindesc++) { + pad = &pads[i]; + pindesc->drv_data = pad; + pindesc->number = i; + pindesc->name = pmic_gpio_groups[i]; + + pad->base = reg + i * PMIC_GPIO_ADDRESS_RANGE; + + ret = pmic_gpio_populate(state, pad); + if (ret < 0) + return ret; + } + + state->chip = pmic_gpio_gpio_template; + state->chip.parent = dev; + state->chip.base = -1; + state->chip.ngpio = npins; + state->chip.label = dev_name(dev); + state->chip.of_gpio_n_cells = 2; + state->chip.can_sleep = false; + + state->ctrl = devm_pinctrl_register(dev, pctrldesc, state); + if (IS_ERR(state->ctrl)) + return PTR_ERR(state->ctrl); + + parent_node = of_irq_find_parent(state->dev->of_node); + if (!parent_node) + return -ENXIO; + + parent_domain = irq_find_host(parent_node); + of_node_put(parent_node); + if (!parent_domain) + return -ENXIO; + + girq = &state->chip.irq; + gpio_irq_chip_set_chip(girq, &spmi_gpio_irq_chip); + girq->default_type = IRQ_TYPE_NONE; + girq->handler = handle_level_irq; + girq->fwnode = dev_fwnode(state->dev); + girq->parent_domain = parent_domain; + girq->child_to_parent_hwirq = pmic_gpio_child_to_parent_hwirq; + girq->populate_parent_alloc_arg = pmic_gpio_populate_parent_fwspec; + girq->child_offset_to_irq = pmic_gpio_child_offset_to_irq; + girq->child_irq_domain_ops.translate = pmic_gpio_domain_translate; + + ret = gpiochip_add_data(&state->chip, state); + if (ret) { + dev_err(state->dev, "can't add gpio chip\n"); + return ret; + } + + /* + * For DeviceTree-supported systems, the gpio core checks the + * pinctrl's device node for the "gpio-ranges" property. + * If it is present, it takes care of adding the pin ranges + * for the driver. In this case the driver can skip ahead. + * + * In order to remain compatible with older, existing DeviceTree + * files which don't set the "gpio-ranges" property or systems that + * utilize ACPI the driver has to call gpiochip_add_pin_range(). + */ + if (!of_property_read_bool(dev->of_node, "gpio-ranges")) { + ret = gpiochip_add_pin_range(&state->chip, dev_name(dev), 0, 0, + npins); + if (ret) { + dev_err(dev, "failed to add pin range\n"); + goto err_range; + } + } + + return 0; + +err_range: + gpiochip_remove(&state->chip); + return ret; +} + +static int pmic_gpio_remove(struct platform_device *pdev) +{ + struct pmic_gpio_state *state = platform_get_drvdata(pdev); + + gpiochip_remove(&state->chip); + return 0; +} + +static const struct of_device_id pmic_gpio_of_match[] = { + { .compatible = "qcom,pm2250-gpio", .data = (void *) 10 }, + /* pm660 has 13 GPIOs with holes on 1, 5, 6, 7, 8 and 10 */ + { .compatible = "qcom,pm660-gpio", .data = (void *) 13 }, + /* pm660l has 12 GPIOs with holes on 1, 2, 10, 11 and 12 */ + { .compatible = "qcom,pm660l-gpio", .data = (void *) 12 }, + { .compatible = "qcom,pm6125-gpio", .data = (void *) 9 }, + { .compatible = "qcom,pm6150-gpio", .data = (void *) 10 }, + { .compatible = "qcom,pm6150l-gpio", .data = (void *) 12 }, + { .compatible = "qcom,pm6350-gpio", .data = (void *) 9 }, + { .compatible = "qcom,pm7250b-gpio", .data = (void *) 12 }, + { .compatible = "qcom,pm7325-gpio", .data = (void *) 10 }, + { .compatible = "qcom,pm7550ba-gpio", .data = (void *) 8}, + { .compatible = "qcom,pm8005-gpio", .data = (void *) 4 }, + { .compatible = "qcom,pm8008-gpio", .data = (void *) 2 }, + { .compatible = "qcom,pm8019-gpio", .data = (void *) 6 }, + /* pm8150 has 10 GPIOs with holes on 2, 5, 7 and 8 */ + { .compatible = "qcom,pm8150-gpio", .data = (void *) 10 }, + { .compatible = "qcom,pmc8180-gpio", .data = (void *) 10 }, + /* pm8150b has 12 GPIOs with holes on 3, r and 7 */ + { .compatible = "qcom,pm8150b-gpio", .data = (void *) 12 }, + /* pm8150l has 12 GPIOs with holes on 7 */ + { .compatible = "qcom,pm8150l-gpio", .data = (void *) 12 }, + { .compatible = "qcom,pmc8180c-gpio", .data = (void *) 12 }, + { .compatible = "qcom,pm8226-gpio", .data = (void *) 8 }, + { .compatible = "qcom,pm8350-gpio", .data = (void *) 10 }, + { .compatible = "qcom,pm8350b-gpio", .data = (void *) 8 }, + { .compatible = "qcom,pm8350c-gpio", .data = (void *) 9 }, + { .compatible = "qcom,pm8450-gpio", .data = (void *) 4 }, + { .compatible = "qcom,pm8550-gpio", .data = (void *) 12 }, + { .compatible = "qcom,pm8550b-gpio", .data = (void *) 12 }, + { .compatible = "qcom,pm8550ve-gpio", .data = (void *) 8 }, + { .compatible = "qcom,pm8550vs-gpio", .data = (void *) 6 }, + { .compatible = "qcom,pm8916-gpio", .data = (void *) 4 }, + { .compatible = "qcom,pm8941-gpio", .data = (void *) 36 }, + /* pm8950 has 8 GPIOs with holes on 3 */ + { .compatible = "qcom,pm8950-gpio", .data = (void *) 8 }, + /* pm8953 has 8 GPIOs with holes on 3 and 6 */ + { .compatible = "qcom,pm8953-gpio", .data = (void *) 8 }, + { .compatible = "qcom,pm8994-gpio", .data = (void *) 22 }, + { .compatible = "qcom,pm8998-gpio", .data = (void *) 26 }, + { .compatible = "qcom,pma8084-gpio", .data = (void *) 22 }, + { .compatible = "qcom,pmi632-gpio", .data = (void *) 8 }, + { .compatible = "qcom,pmi8950-gpio", .data = (void *) 2 }, + { .compatible = "qcom,pmi8994-gpio", .data = (void *) 10 }, + { .compatible = "qcom,pmi8998-gpio", .data = (void *) 14 }, + { .compatible = "qcom,pmk8350-gpio", .data = (void *) 4 }, + { .compatible = "qcom,pmk8550-gpio", .data = (void *) 6 }, + { .compatible = "qcom,pmm8155au-gpio", .data = (void *) 10 }, + { .compatible = "qcom,pmm8654au-gpio", .data = (void *) 12 }, + /* pmp8074 has 12 GPIOs with holes on 1 and 12 */ + { .compatible = "qcom,pmp8074-gpio", .data = (void *) 12 }, + { .compatible = "qcom,pmr735a-gpio", .data = (void *) 4 }, + { .compatible = "qcom,pmr735b-gpio", .data = (void *) 4 }, + { .compatible = "qcom,pmr735d-gpio", .data = (void *) 2 }, + /* pms405 has 12 GPIOs with holes on 1, 9, and 10 */ + { .compatible = "qcom,pms405-gpio", .data = (void *) 12 }, + /* pmx55 has 11 GPIOs with holes on 3, 7, 10, 11 */ + { .compatible = "qcom,pmx55-gpio", .data = (void *) 11 }, + { .compatible = "qcom,pmx65-gpio", .data = (void *) 16 }, + { .compatible = "qcom,pmx75-gpio", .data = (void *) 16 }, + { }, +}; + +MODULE_DEVICE_TABLE(of, pmic_gpio_of_match); + +static struct platform_driver pmic_gpio_driver = { + .driver = { + .name = "qcom-spmi-gpio", + .of_match_table = pmic_gpio_of_match, + }, + .probe = pmic_gpio_probe, + .remove = pmic_gpio_remove, +}; + +module_platform_driver(pmic_gpio_driver); + +MODULE_AUTHOR("Ivan T. Ivanov <iivanov@mm-sol.com>"); +MODULE_DESCRIPTION("Qualcomm SPMI PMIC GPIO pin control driver"); +MODULE_ALIAS("platform:qcom-spmi-gpio"); +MODULE_LICENSE("GPL v2"); diff --git a/drivers/pinctrl/qcom/pinctrl-spmi-mpp.c b/drivers/pinctrl/qcom/pinctrl-spmi-mpp.c new file mode 100644 index 0000000000..fe0393829c --- /dev/null +++ b/drivers/pinctrl/qcom/pinctrl-spmi-mpp.c @@ -0,0 +1,1012 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2012-2014, The Linux Foundation. All rights reserved. + */ + +#include <linux/gpio/driver.h> +#include <linux/module.h> +#include <linux/of.h> +#include <linux/of_irq.h> +#include <linux/platform_device.h> +#include <linux/regmap.h> +#include <linux/seq_file.h> +#include <linux/slab.h> +#include <linux/types.h> + +#include <linux/pinctrl/pinconf-generic.h> +#include <linux/pinctrl/pinconf.h> +#include <linux/pinctrl/pinmux.h> + +#include <dt-bindings/pinctrl/qcom,pmic-mpp.h> + +#include "../core.h" +#include "../pinctrl-utils.h" + +#define PMIC_MPP_ADDRESS_RANGE 0x100 + +/* + * Pull Up Values - it indicates whether a pull-up should be + * applied for bidirectional mode only. The hardware ignores the + * configuration when operating in other modes. + */ +#define PMIC_MPP_PULL_UP_0P6KOHM 0 +#define PMIC_MPP_PULL_UP_10KOHM 1 +#define PMIC_MPP_PULL_UP_30KOHM 2 +#define PMIC_MPP_PULL_UP_OPEN 3 + +/* type registers base address bases */ +#define PMIC_MPP_REG_TYPE 0x4 +#define PMIC_MPP_REG_SUBTYPE 0x5 + +/* mpp peripheral type and subtype values */ +#define PMIC_MPP_TYPE 0x11 +#define PMIC_MPP_SUBTYPE_4CH_NO_ANA_OUT 0x3 +#define PMIC_MPP_SUBTYPE_ULT_4CH_NO_ANA_OUT 0x4 +#define PMIC_MPP_SUBTYPE_4CH_NO_SINK 0x5 +#define PMIC_MPP_SUBTYPE_ULT_4CH_NO_SINK 0x6 +#define PMIC_MPP_SUBTYPE_4CH_FULL_FUNC 0x7 +#define PMIC_MPP_SUBTYPE_8CH_FULL_FUNC 0xf + +#define PMIC_MPP_REG_RT_STS 0x10 +#define PMIC_MPP_REG_RT_STS_VAL_MASK 0x1 + +/* control register base address bases */ +#define PMIC_MPP_REG_MODE_CTL 0x40 +#define PMIC_MPP_REG_DIG_VIN_CTL 0x41 +#define PMIC_MPP_REG_DIG_PULL_CTL 0x42 +#define PMIC_MPP_REG_DIG_IN_CTL 0x43 +#define PMIC_MPP_REG_EN_CTL 0x46 +#define PMIC_MPP_REG_AOUT_CTL 0x48 +#define PMIC_MPP_REG_AIN_CTL 0x4a +#define PMIC_MPP_REG_SINK_CTL 0x4c + +/* PMIC_MPP_REG_MODE_CTL */ +#define PMIC_MPP_REG_MODE_VALUE_MASK 0x1 +#define PMIC_MPP_REG_MODE_FUNCTION_SHIFT 1 +#define PMIC_MPP_REG_MODE_FUNCTION_MASK 0x7 +#define PMIC_MPP_REG_MODE_DIR_SHIFT 4 +#define PMIC_MPP_REG_MODE_DIR_MASK 0x7 + +/* PMIC_MPP_REG_DIG_VIN_CTL */ +#define PMIC_MPP_REG_VIN_SHIFT 0 +#define PMIC_MPP_REG_VIN_MASK 0x7 + +/* PMIC_MPP_REG_DIG_PULL_CTL */ +#define PMIC_MPP_REG_PULL_SHIFT 0 +#define PMIC_MPP_REG_PULL_MASK 0x7 + +/* PMIC_MPP_REG_EN_CTL */ +#define PMIC_MPP_REG_MASTER_EN_SHIFT 7 + +/* PMIC_MPP_REG_AIN_CTL */ +#define PMIC_MPP_REG_AIN_ROUTE_SHIFT 0 +#define PMIC_MPP_REG_AIN_ROUTE_MASK 0x7 + +#define PMIC_MPP_MODE_DIGITAL_INPUT 0 +#define PMIC_MPP_MODE_DIGITAL_OUTPUT 1 +#define PMIC_MPP_MODE_DIGITAL_BIDIR 2 +#define PMIC_MPP_MODE_ANALOG_BIDIR 3 +#define PMIC_MPP_MODE_ANALOG_INPUT 4 +#define PMIC_MPP_MODE_ANALOG_OUTPUT 5 +#define PMIC_MPP_MODE_CURRENT_SINK 6 + +#define PMIC_MPP_SELECTOR_NORMAL 0 +#define PMIC_MPP_SELECTOR_PAIRED 1 +#define PMIC_MPP_SELECTOR_DTEST_FIRST 4 + +#define PMIC_MPP_PHYSICAL_OFFSET 1 + +/* Qualcomm specific pin configurations */ +#define PMIC_MPP_CONF_AMUX_ROUTE (PIN_CONFIG_END + 1) +#define PMIC_MPP_CONF_ANALOG_LEVEL (PIN_CONFIG_END + 2) +#define PMIC_MPP_CONF_DTEST_SELECTOR (PIN_CONFIG_END + 3) +#define PMIC_MPP_CONF_PAIRED (PIN_CONFIG_END + 4) + +/** + * struct pmic_mpp_pad - keep current MPP settings + * @base: Address base in SPMI device. + * @is_enabled: Set to false when MPP should be put in high Z state. + * @out_value: Cached pin output value. + * @output_enabled: Set to true if MPP output logic is enabled. + * @input_enabled: Set to true if MPP input buffer logic is enabled. + * @paired: Pin operates in paired mode + * @has_pullup: Pin has support to configure pullup + * @num_sources: Number of power-sources supported by this MPP. + * @power_source: Current power-source used. + * @amux_input: Set the source for analog input. + * @aout_level: Analog output level + * @pullup: Pullup resistor value. Valid in Bidirectional mode only. + * @function: See pmic_mpp_functions[]. + * @drive_strength: Amount of current in sink mode + * @dtest: DTEST route selector + */ +struct pmic_mpp_pad { + u16 base; + bool is_enabled; + bool out_value; + bool output_enabled; + bool input_enabled; + bool paired; + bool has_pullup; + unsigned int num_sources; + unsigned int power_source; + unsigned int amux_input; + unsigned int aout_level; + unsigned int pullup; + unsigned int function; + unsigned int drive_strength; + unsigned int dtest; +}; + +struct pmic_mpp_state { + struct device *dev; + struct regmap *map; + struct pinctrl_dev *ctrl; + struct gpio_chip chip; +}; + +static const struct pinconf_generic_params pmic_mpp_bindings[] = { + {"qcom,amux-route", PMIC_MPP_CONF_AMUX_ROUTE, 0}, + {"qcom,analog-level", PMIC_MPP_CONF_ANALOG_LEVEL, 0}, + {"qcom,dtest", PMIC_MPP_CONF_DTEST_SELECTOR, 0}, + {"qcom,paired", PMIC_MPP_CONF_PAIRED, 0}, +}; + +#ifdef CONFIG_DEBUG_FS +static const struct pin_config_item pmic_conf_items[] = { + PCONFDUMP(PMIC_MPP_CONF_AMUX_ROUTE, "analog mux", NULL, true), + PCONFDUMP(PMIC_MPP_CONF_ANALOG_LEVEL, "analog level", NULL, true), + PCONFDUMP(PMIC_MPP_CONF_DTEST_SELECTOR, "dtest", NULL, true), + PCONFDUMP(PMIC_MPP_CONF_PAIRED, "paired", NULL, false), +}; +#endif + +static const char *const pmic_mpp_groups[] = { + "mpp1", "mpp2", "mpp3", "mpp4", "mpp5", "mpp6", "mpp7", "mpp8", +}; + +#define PMIC_MPP_DIGITAL 0 +#define PMIC_MPP_ANALOG 1 +#define PMIC_MPP_SINK 2 + +static const char *const pmic_mpp_functions[] = { + "digital", "analog", "sink" +}; + +static int pmic_mpp_read(struct pmic_mpp_state *state, + struct pmic_mpp_pad *pad, unsigned int addr) +{ + unsigned int val; + int ret; + + ret = regmap_read(state->map, pad->base + addr, &val); + if (ret < 0) + dev_err(state->dev, "read 0x%x failed\n", addr); + else + ret = val; + + return ret; +} + +static int pmic_mpp_write(struct pmic_mpp_state *state, + struct pmic_mpp_pad *pad, unsigned int addr, + unsigned int val) +{ + int ret; + + ret = regmap_write(state->map, pad->base + addr, val); + if (ret < 0) + dev_err(state->dev, "write 0x%x failed\n", addr); + + return ret; +} + +static int pmic_mpp_get_groups_count(struct pinctrl_dev *pctldev) +{ + /* Every PIN is a group */ + return pctldev->desc->npins; +} + +static const char *pmic_mpp_get_group_name(struct pinctrl_dev *pctldev, + unsigned pin) +{ + return pctldev->desc->pins[pin].name; +} + +static int pmic_mpp_get_group_pins(struct pinctrl_dev *pctldev, + unsigned pin, + const unsigned **pins, unsigned *num_pins) +{ + *pins = &pctldev->desc->pins[pin].number; + *num_pins = 1; + return 0; +} + +static const struct pinctrl_ops pmic_mpp_pinctrl_ops = { + .get_groups_count = pmic_mpp_get_groups_count, + .get_group_name = pmic_mpp_get_group_name, + .get_group_pins = pmic_mpp_get_group_pins, + .dt_node_to_map = pinconf_generic_dt_node_to_map_group, + .dt_free_map = pinctrl_utils_free_map, +}; + +static int pmic_mpp_get_functions_count(struct pinctrl_dev *pctldev) +{ + return ARRAY_SIZE(pmic_mpp_functions); +} + +static const char *pmic_mpp_get_function_name(struct pinctrl_dev *pctldev, + unsigned function) +{ + return pmic_mpp_functions[function]; +} + +static int pmic_mpp_get_function_groups(struct pinctrl_dev *pctldev, + unsigned function, + const char *const **groups, + unsigned *const num_qgroups) +{ + *groups = pmic_mpp_groups; + *num_qgroups = pctldev->desc->npins; + return 0; +} + +static int pmic_mpp_write_mode_ctl(struct pmic_mpp_state *state, + struct pmic_mpp_pad *pad) +{ + unsigned int mode; + unsigned int sel; + unsigned int val; + unsigned int en; + + switch (pad->function) { + case PMIC_MPP_ANALOG: + if (pad->input_enabled && pad->output_enabled) + mode = PMIC_MPP_MODE_ANALOG_BIDIR; + else if (pad->input_enabled) + mode = PMIC_MPP_MODE_ANALOG_INPUT; + else + mode = PMIC_MPP_MODE_ANALOG_OUTPUT; + break; + case PMIC_MPP_DIGITAL: + if (pad->input_enabled && pad->output_enabled) + mode = PMIC_MPP_MODE_DIGITAL_BIDIR; + else if (pad->input_enabled) + mode = PMIC_MPP_MODE_DIGITAL_INPUT; + else + mode = PMIC_MPP_MODE_DIGITAL_OUTPUT; + break; + case PMIC_MPP_SINK: + default: + mode = PMIC_MPP_MODE_CURRENT_SINK; + break; + } + + if (pad->dtest) + sel = PMIC_MPP_SELECTOR_DTEST_FIRST + pad->dtest - 1; + else if (pad->paired) + sel = PMIC_MPP_SELECTOR_PAIRED; + else + sel = PMIC_MPP_SELECTOR_NORMAL; + + en = !!pad->out_value; + + val = mode << PMIC_MPP_REG_MODE_DIR_SHIFT | + sel << PMIC_MPP_REG_MODE_FUNCTION_SHIFT | + en; + + return pmic_mpp_write(state, pad, PMIC_MPP_REG_MODE_CTL, val); +} + +static int pmic_mpp_set_mux(struct pinctrl_dev *pctldev, unsigned function, + unsigned pin) +{ + struct pmic_mpp_state *state = pinctrl_dev_get_drvdata(pctldev); + struct pmic_mpp_pad *pad; + unsigned int val; + int ret; + + pad = pctldev->desc->pins[pin].drv_data; + + pad->function = function; + + ret = pmic_mpp_write_mode_ctl(state, pad); + if (ret < 0) + return ret; + + val = pad->is_enabled << PMIC_MPP_REG_MASTER_EN_SHIFT; + + return pmic_mpp_write(state, pad, PMIC_MPP_REG_EN_CTL, val); +} + +static const struct pinmux_ops pmic_mpp_pinmux_ops = { + .get_functions_count = pmic_mpp_get_functions_count, + .get_function_name = pmic_mpp_get_function_name, + .get_function_groups = pmic_mpp_get_function_groups, + .set_mux = pmic_mpp_set_mux, +}; + +static int pmic_mpp_config_get(struct pinctrl_dev *pctldev, + unsigned int pin, unsigned long *config) +{ + unsigned param = pinconf_to_config_param(*config); + struct pmic_mpp_pad *pad; + unsigned arg = 0; + + pad = pctldev->desc->pins[pin].drv_data; + + switch (param) { + case PIN_CONFIG_BIAS_DISABLE: + if (pad->pullup != PMIC_MPP_PULL_UP_OPEN) + return -EINVAL; + arg = 1; + break; + case PIN_CONFIG_BIAS_PULL_UP: + switch (pad->pullup) { + case PMIC_MPP_PULL_UP_0P6KOHM: + arg = 600; + break; + case PMIC_MPP_PULL_UP_10KOHM: + arg = 10000; + break; + case PMIC_MPP_PULL_UP_30KOHM: + arg = 30000; + break; + default: + return -EINVAL; + } + break; + case PIN_CONFIG_BIAS_HIGH_IMPEDANCE: + if (pad->is_enabled) + return -EINVAL; + arg = 1; + break; + case PIN_CONFIG_POWER_SOURCE: + arg = pad->power_source; + break; + case PIN_CONFIG_INPUT_ENABLE: + if (!pad->input_enabled) + return -EINVAL; + arg = 1; + break; + case PIN_CONFIG_OUTPUT: + arg = pad->out_value; + break; + case PMIC_MPP_CONF_DTEST_SELECTOR: + arg = pad->dtest; + break; + case PMIC_MPP_CONF_AMUX_ROUTE: + arg = pad->amux_input; + break; + case PMIC_MPP_CONF_PAIRED: + if (!pad->paired) + return -EINVAL; + arg = 1; + break; + case PIN_CONFIG_DRIVE_STRENGTH: + arg = pad->drive_strength; + break; + case PMIC_MPP_CONF_ANALOG_LEVEL: + arg = pad->aout_level; + break; + default: + return -EINVAL; + } + + /* Convert register value to pinconf value */ + *config = pinconf_to_config_packed(param, arg); + return 0; +} + +static int pmic_mpp_config_set(struct pinctrl_dev *pctldev, unsigned int pin, + unsigned long *configs, unsigned nconfs) +{ + struct pmic_mpp_state *state = pinctrl_dev_get_drvdata(pctldev); + struct pmic_mpp_pad *pad; + unsigned param, arg; + unsigned int val; + int i, ret; + + pad = pctldev->desc->pins[pin].drv_data; + + /* Make it possible to enable the pin, by not setting high impedance */ + pad->is_enabled = true; + + for (i = 0; i < nconfs; i++) { + param = pinconf_to_config_param(configs[i]); + arg = pinconf_to_config_argument(configs[i]); + + switch (param) { + case PIN_CONFIG_BIAS_DISABLE: + pad->pullup = PMIC_MPP_PULL_UP_OPEN; + break; + case PIN_CONFIG_BIAS_PULL_UP: + switch (arg) { + case 600: + pad->pullup = PMIC_MPP_PULL_UP_0P6KOHM; + break; + case 10000: + pad->pullup = PMIC_MPP_PULL_UP_10KOHM; + break; + case 30000: + pad->pullup = PMIC_MPP_PULL_UP_30KOHM; + break; + default: + return -EINVAL; + } + break; + case PIN_CONFIG_BIAS_HIGH_IMPEDANCE: + pad->is_enabled = false; + break; + case PIN_CONFIG_POWER_SOURCE: + if (arg >= pad->num_sources) + return -EINVAL; + pad->power_source = arg; + break; + case PIN_CONFIG_INPUT_ENABLE: + pad->input_enabled = arg ? true : false; + break; + case PIN_CONFIG_OUTPUT: + pad->output_enabled = true; + pad->out_value = arg; + break; + case PMIC_MPP_CONF_DTEST_SELECTOR: + pad->dtest = arg; + break; + case PIN_CONFIG_DRIVE_STRENGTH: + pad->drive_strength = arg; + break; + case PMIC_MPP_CONF_AMUX_ROUTE: + if (arg >= PMIC_MPP_AMUX_ROUTE_ABUS4) + return -EINVAL; + pad->amux_input = arg; + break; + case PMIC_MPP_CONF_ANALOG_LEVEL: + pad->aout_level = arg; + break; + case PMIC_MPP_CONF_PAIRED: + pad->paired = !!arg; + break; + default: + return -EINVAL; + } + } + + val = pad->power_source << PMIC_MPP_REG_VIN_SHIFT; + + ret = pmic_mpp_write(state, pad, PMIC_MPP_REG_DIG_VIN_CTL, val); + if (ret < 0) + return ret; + + if (pad->has_pullup) { + val = pad->pullup << PMIC_MPP_REG_PULL_SHIFT; + + ret = pmic_mpp_write(state, pad, PMIC_MPP_REG_DIG_PULL_CTL, + val); + if (ret < 0) + return ret; + } + + val = pad->amux_input & PMIC_MPP_REG_AIN_ROUTE_MASK; + + ret = pmic_mpp_write(state, pad, PMIC_MPP_REG_AIN_CTL, val); + if (ret < 0) + return ret; + + ret = pmic_mpp_write(state, pad, PMIC_MPP_REG_AOUT_CTL, pad->aout_level); + if (ret < 0) + return ret; + + ret = pmic_mpp_write_mode_ctl(state, pad); + if (ret < 0) + return ret; + + ret = pmic_mpp_write(state, pad, PMIC_MPP_REG_SINK_CTL, pad->drive_strength); + if (ret < 0) + return ret; + + val = pad->is_enabled << PMIC_MPP_REG_MASTER_EN_SHIFT; + + return pmic_mpp_write(state, pad, PMIC_MPP_REG_EN_CTL, val); +} + +static void pmic_mpp_config_dbg_show(struct pinctrl_dev *pctldev, + struct seq_file *s, unsigned pin) +{ + struct pmic_mpp_state *state = pinctrl_dev_get_drvdata(pctldev); + struct pmic_mpp_pad *pad; + int ret; + + static const char *const biases[] = { + "0.6kOhm", "10kOhm", "30kOhm", "Disabled" + }; + + pad = pctldev->desc->pins[pin].drv_data; + + seq_printf(s, " mpp%-2d:", pin + PMIC_MPP_PHYSICAL_OFFSET); + + if (!pad->is_enabled) { + seq_puts(s, " ---"); + } else { + + if (pad->input_enabled) { + ret = pmic_mpp_read(state, pad, PMIC_MPP_REG_RT_STS); + if (ret < 0) + return; + + ret &= PMIC_MPP_REG_RT_STS_VAL_MASK; + pad->out_value = ret; + } + + seq_printf(s, " %-4s", pad->output_enabled ? "out" : "in"); + seq_printf(s, " %-7s", pmic_mpp_functions[pad->function]); + seq_printf(s, " vin-%d", pad->power_source); + seq_printf(s, " %d", pad->aout_level); + if (pad->has_pullup) + seq_printf(s, " %-8s", biases[pad->pullup]); + seq_printf(s, " %-4s", pad->out_value ? "high" : "low"); + if (pad->dtest) + seq_printf(s, " dtest%d", pad->dtest); + if (pad->paired) + seq_puts(s, " paired"); + } +} + +static const struct pinconf_ops pmic_mpp_pinconf_ops = { + .is_generic = true, + .pin_config_group_get = pmic_mpp_config_get, + .pin_config_group_set = pmic_mpp_config_set, + .pin_config_group_dbg_show = pmic_mpp_config_dbg_show, +}; + +static int pmic_mpp_direction_input(struct gpio_chip *chip, unsigned pin) +{ + struct pmic_mpp_state *state = gpiochip_get_data(chip); + unsigned long config; + + config = pinconf_to_config_packed(PIN_CONFIG_INPUT_ENABLE, 1); + + return pmic_mpp_config_set(state->ctrl, pin, &config, 1); +} + +static int pmic_mpp_direction_output(struct gpio_chip *chip, + unsigned pin, int val) +{ + struct pmic_mpp_state *state = gpiochip_get_data(chip); + unsigned long config; + + config = pinconf_to_config_packed(PIN_CONFIG_OUTPUT, val); + + return pmic_mpp_config_set(state->ctrl, pin, &config, 1); +} + +static int pmic_mpp_get(struct gpio_chip *chip, unsigned pin) +{ + struct pmic_mpp_state *state = gpiochip_get_data(chip); + struct pmic_mpp_pad *pad; + int ret; + + pad = state->ctrl->desc->pins[pin].drv_data; + + if (pad->input_enabled) { + ret = pmic_mpp_read(state, pad, PMIC_MPP_REG_RT_STS); + if (ret < 0) + return ret; + + pad->out_value = ret & PMIC_MPP_REG_RT_STS_VAL_MASK; + } + + return !!pad->out_value; +} + +static void pmic_mpp_set(struct gpio_chip *chip, unsigned pin, int value) +{ + struct pmic_mpp_state *state = gpiochip_get_data(chip); + unsigned long config; + + config = pinconf_to_config_packed(PIN_CONFIG_OUTPUT, value); + + pmic_mpp_config_set(state->ctrl, pin, &config, 1); +} + +static int pmic_mpp_of_xlate(struct gpio_chip *chip, + const struct of_phandle_args *gpio_desc, + u32 *flags) +{ + if (chip->of_gpio_n_cells < 2) + return -EINVAL; + + if (flags) + *flags = gpio_desc->args[1]; + + return gpio_desc->args[0] - PMIC_MPP_PHYSICAL_OFFSET; +} + +static void pmic_mpp_dbg_show(struct seq_file *s, struct gpio_chip *chip) +{ + struct pmic_mpp_state *state = gpiochip_get_data(chip); + unsigned i; + + for (i = 0; i < chip->ngpio; i++) { + pmic_mpp_config_dbg_show(state->ctrl, s, i); + seq_puts(s, "\n"); + } +} + +static const struct gpio_chip pmic_mpp_gpio_template = { + .direction_input = pmic_mpp_direction_input, + .direction_output = pmic_mpp_direction_output, + .get = pmic_mpp_get, + .set = pmic_mpp_set, + .request = gpiochip_generic_request, + .free = gpiochip_generic_free, + .of_xlate = pmic_mpp_of_xlate, + .dbg_show = pmic_mpp_dbg_show, +}; + +static int pmic_mpp_populate(struct pmic_mpp_state *state, + struct pmic_mpp_pad *pad) +{ + int type, subtype, val, dir; + unsigned int sel; + + type = pmic_mpp_read(state, pad, PMIC_MPP_REG_TYPE); + if (type < 0) + return type; + + if (type != PMIC_MPP_TYPE) { + dev_err(state->dev, "incorrect block type 0x%x at 0x%x\n", + type, pad->base); + return -ENODEV; + } + + subtype = pmic_mpp_read(state, pad, PMIC_MPP_REG_SUBTYPE); + if (subtype < 0) + return subtype; + + switch (subtype) { + case PMIC_MPP_SUBTYPE_4CH_NO_ANA_OUT: + case PMIC_MPP_SUBTYPE_ULT_4CH_NO_ANA_OUT: + case PMIC_MPP_SUBTYPE_4CH_NO_SINK: + case PMIC_MPP_SUBTYPE_ULT_4CH_NO_SINK: + case PMIC_MPP_SUBTYPE_4CH_FULL_FUNC: + pad->num_sources = 4; + break; + case PMIC_MPP_SUBTYPE_8CH_FULL_FUNC: + pad->num_sources = 8; + break; + default: + dev_err(state->dev, "unknown MPP type 0x%x at 0x%x\n", + subtype, pad->base); + return -ENODEV; + } + + val = pmic_mpp_read(state, pad, PMIC_MPP_REG_MODE_CTL); + if (val < 0) + return val; + + pad->out_value = val & PMIC_MPP_REG_MODE_VALUE_MASK; + + dir = val >> PMIC_MPP_REG_MODE_DIR_SHIFT; + dir &= PMIC_MPP_REG_MODE_DIR_MASK; + + switch (dir) { + case PMIC_MPP_MODE_DIGITAL_INPUT: + pad->input_enabled = true; + pad->output_enabled = false; + pad->function = PMIC_MPP_DIGITAL; + break; + case PMIC_MPP_MODE_DIGITAL_OUTPUT: + pad->input_enabled = false; + pad->output_enabled = true; + pad->function = PMIC_MPP_DIGITAL; + break; + case PMIC_MPP_MODE_DIGITAL_BIDIR: + pad->input_enabled = true; + pad->output_enabled = true; + pad->function = PMIC_MPP_DIGITAL; + break; + case PMIC_MPP_MODE_ANALOG_BIDIR: + pad->input_enabled = true; + pad->output_enabled = true; + pad->function = PMIC_MPP_ANALOG; + break; + case PMIC_MPP_MODE_ANALOG_INPUT: + pad->input_enabled = true; + pad->output_enabled = false; + pad->function = PMIC_MPP_ANALOG; + break; + case PMIC_MPP_MODE_ANALOG_OUTPUT: + pad->input_enabled = false; + pad->output_enabled = true; + pad->function = PMIC_MPP_ANALOG; + break; + case PMIC_MPP_MODE_CURRENT_SINK: + pad->input_enabled = false; + pad->output_enabled = true; + pad->function = PMIC_MPP_SINK; + break; + default: + dev_err(state->dev, "unknown MPP direction\n"); + return -ENODEV; + } + + sel = val >> PMIC_MPP_REG_MODE_FUNCTION_SHIFT; + sel &= PMIC_MPP_REG_MODE_FUNCTION_MASK; + + if (sel >= PMIC_MPP_SELECTOR_DTEST_FIRST) + pad->dtest = sel + 1; + else if (sel == PMIC_MPP_SELECTOR_PAIRED) + pad->paired = true; + + val = pmic_mpp_read(state, pad, PMIC_MPP_REG_DIG_VIN_CTL); + if (val < 0) + return val; + + pad->power_source = val >> PMIC_MPP_REG_VIN_SHIFT; + pad->power_source &= PMIC_MPP_REG_VIN_MASK; + + if (subtype != PMIC_MPP_SUBTYPE_ULT_4CH_NO_ANA_OUT && + subtype != PMIC_MPP_SUBTYPE_ULT_4CH_NO_SINK) { + val = pmic_mpp_read(state, pad, PMIC_MPP_REG_DIG_PULL_CTL); + if (val < 0) + return val; + + pad->pullup = val >> PMIC_MPP_REG_PULL_SHIFT; + pad->pullup &= PMIC_MPP_REG_PULL_MASK; + pad->has_pullup = true; + } + + val = pmic_mpp_read(state, pad, PMIC_MPP_REG_AIN_CTL); + if (val < 0) + return val; + + pad->amux_input = val >> PMIC_MPP_REG_AIN_ROUTE_SHIFT; + pad->amux_input &= PMIC_MPP_REG_AIN_ROUTE_MASK; + + val = pmic_mpp_read(state, pad, PMIC_MPP_REG_SINK_CTL); + if (val < 0) + return val; + + pad->drive_strength = val; + + val = pmic_mpp_read(state, pad, PMIC_MPP_REG_AOUT_CTL); + if (val < 0) + return val; + + pad->aout_level = val; + + val = pmic_mpp_read(state, pad, PMIC_MPP_REG_EN_CTL); + if (val < 0) + return val; + + pad->is_enabled = !!val; + + return 0; +} + +static int pmic_mpp_domain_translate(struct irq_domain *domain, + struct irq_fwspec *fwspec, + unsigned long *hwirq, + unsigned int *type) +{ + struct pmic_mpp_state *state = container_of(domain->host_data, + struct pmic_mpp_state, + chip); + + if (fwspec->param_count != 2 || + fwspec->param[0] < 1 || fwspec->param[0] > state->chip.ngpio) + return -EINVAL; + + *hwirq = fwspec->param[0] - PMIC_MPP_PHYSICAL_OFFSET; + *type = fwspec->param[1]; + + return 0; +} + +static unsigned int pmic_mpp_child_offset_to_irq(struct gpio_chip *chip, + unsigned int offset) +{ + return offset + PMIC_MPP_PHYSICAL_OFFSET; +} + +static int pmic_mpp_child_to_parent_hwirq(struct gpio_chip *chip, + unsigned int child_hwirq, + unsigned int child_type, + unsigned int *parent_hwirq, + unsigned int *parent_type) +{ + *parent_hwirq = child_hwirq + 0xc0; + *parent_type = child_type; + + return 0; +} + +static void pmic_mpp_irq_mask(struct irq_data *d) +{ + struct gpio_chip *gc = irq_data_get_irq_chip_data(d); + + irq_chip_mask_parent(d); + gpiochip_disable_irq(gc, irqd_to_hwirq(d)); +} + +static void pmic_mpp_irq_unmask(struct irq_data *d) +{ + struct gpio_chip *gc = irq_data_get_irq_chip_data(d); + + gpiochip_enable_irq(gc, irqd_to_hwirq(d)); + irq_chip_unmask_parent(d); +} + +static const struct irq_chip pmic_mpp_irq_chip = { + .name = "spmi-mpp", + .irq_ack = irq_chip_ack_parent, + .irq_mask = pmic_mpp_irq_mask, + .irq_unmask = pmic_mpp_irq_unmask, + .irq_set_type = irq_chip_set_type_parent, + .irq_set_wake = irq_chip_set_wake_parent, + .flags = IRQCHIP_MASK_ON_SUSPEND | IRQCHIP_IMMUTABLE, + GPIOCHIP_IRQ_RESOURCE_HELPERS, +}; + +static int pmic_mpp_probe(struct platform_device *pdev) +{ + struct irq_domain *parent_domain; + struct device_node *parent_node; + struct device *dev = &pdev->dev; + struct pinctrl_pin_desc *pindesc; + struct pinctrl_desc *pctrldesc; + struct pmic_mpp_pad *pad, *pads; + struct pmic_mpp_state *state; + struct gpio_irq_chip *girq; + int ret, npins, i; + u32 reg; + + ret = of_property_read_u32(dev->of_node, "reg", ®); + if (ret < 0) { + dev_err(dev, "missing base address"); + return ret; + } + + npins = (uintptr_t) device_get_match_data(&pdev->dev); + + BUG_ON(npins > ARRAY_SIZE(pmic_mpp_groups)); + + state = devm_kzalloc(dev, sizeof(*state), GFP_KERNEL); + if (!state) + return -ENOMEM; + + platform_set_drvdata(pdev, state); + + state->dev = &pdev->dev; + state->map = dev_get_regmap(dev->parent, NULL); + + pindesc = devm_kcalloc(dev, npins, sizeof(*pindesc), GFP_KERNEL); + if (!pindesc) + return -ENOMEM; + + pads = devm_kcalloc(dev, npins, sizeof(*pads), GFP_KERNEL); + if (!pads) + return -ENOMEM; + + pctrldesc = devm_kzalloc(dev, sizeof(*pctrldesc), GFP_KERNEL); + if (!pctrldesc) + return -ENOMEM; + + pctrldesc->pctlops = &pmic_mpp_pinctrl_ops; + pctrldesc->pmxops = &pmic_mpp_pinmux_ops; + pctrldesc->confops = &pmic_mpp_pinconf_ops; + pctrldesc->owner = THIS_MODULE; + pctrldesc->name = dev_name(dev); + pctrldesc->pins = pindesc; + pctrldesc->npins = npins; + + pctrldesc->num_custom_params = ARRAY_SIZE(pmic_mpp_bindings); + pctrldesc->custom_params = pmic_mpp_bindings; +#ifdef CONFIG_DEBUG_FS + pctrldesc->custom_conf_items = pmic_conf_items; +#endif + + for (i = 0; i < npins; i++, pindesc++) { + pad = &pads[i]; + pindesc->drv_data = pad; + pindesc->number = i; + pindesc->name = pmic_mpp_groups[i]; + + pad->base = reg + i * PMIC_MPP_ADDRESS_RANGE; + + ret = pmic_mpp_populate(state, pad); + if (ret < 0) + return ret; + } + + state->chip = pmic_mpp_gpio_template; + state->chip.parent = dev; + state->chip.base = -1; + state->chip.ngpio = npins; + state->chip.label = dev_name(dev); + state->chip.of_gpio_n_cells = 2; + state->chip.can_sleep = false; + + state->ctrl = devm_pinctrl_register(dev, pctrldesc, state); + if (IS_ERR(state->ctrl)) + return PTR_ERR(state->ctrl); + + parent_node = of_irq_find_parent(state->dev->of_node); + if (!parent_node) + return -ENXIO; + + parent_domain = irq_find_host(parent_node); + of_node_put(parent_node); + if (!parent_domain) + return -ENXIO; + + girq = &state->chip.irq; + gpio_irq_chip_set_chip(girq, &pmic_mpp_irq_chip); + girq->default_type = IRQ_TYPE_NONE; + girq->handler = handle_level_irq; + girq->fwnode = dev_fwnode(state->dev); + girq->parent_domain = parent_domain; + girq->child_to_parent_hwirq = pmic_mpp_child_to_parent_hwirq; + girq->populate_parent_alloc_arg = gpiochip_populate_parent_fwspec_fourcell; + girq->child_offset_to_irq = pmic_mpp_child_offset_to_irq; + girq->child_irq_domain_ops.translate = pmic_mpp_domain_translate; + + ret = gpiochip_add_data(&state->chip, state); + if (ret) { + dev_err(state->dev, "can't add gpio chip\n"); + return ret; + } + + ret = gpiochip_add_pin_range(&state->chip, dev_name(dev), 0, 0, npins); + if (ret) { + dev_err(dev, "failed to add pin range\n"); + goto err_range; + } + + return 0; + +err_range: + gpiochip_remove(&state->chip); + return ret; +} + +static int pmic_mpp_remove(struct platform_device *pdev) +{ + struct pmic_mpp_state *state = platform_get_drvdata(pdev); + + gpiochip_remove(&state->chip); + return 0; +} + +static const struct of_device_id pmic_mpp_of_match[] = { + { .compatible = "qcom,pm8019-mpp", .data = (void *) 6 }, + { .compatible = "qcom,pm8226-mpp", .data = (void *) 8 }, + { .compatible = "qcom,pm8841-mpp", .data = (void *) 4 }, + { .compatible = "qcom,pm8916-mpp", .data = (void *) 4 }, + { .compatible = "qcom,pm8941-mpp", .data = (void *) 8 }, + { .compatible = "qcom,pm8950-mpp", .data = (void *) 4 }, + { .compatible = "qcom,pmi8950-mpp", .data = (void *) 4 }, + { .compatible = "qcom,pm8994-mpp", .data = (void *) 8 }, + { .compatible = "qcom,pma8084-mpp", .data = (void *) 8 }, + { .compatible = "qcom,pmi8994-mpp", .data = (void *) 4 }, + { }, +}; + +MODULE_DEVICE_TABLE(of, pmic_mpp_of_match); + +static struct platform_driver pmic_mpp_driver = { + .driver = { + .name = "qcom-spmi-mpp", + .of_match_table = pmic_mpp_of_match, + }, + .probe = pmic_mpp_probe, + .remove = pmic_mpp_remove, +}; + +module_platform_driver(pmic_mpp_driver); + +MODULE_AUTHOR("Ivan T. Ivanov <iivanov@mm-sol.com>"); +MODULE_DESCRIPTION("Qualcomm SPMI PMIC MPP pin control driver"); +MODULE_ALIAS("platform:qcom-spmi-mpp"); +MODULE_LICENSE("GPL v2"); diff --git a/drivers/pinctrl/qcom/pinctrl-ssbi-gpio.c b/drivers/pinctrl/qcom/pinctrl-ssbi-gpio.c new file mode 100644 index 0000000000..e0d43d076c --- /dev/null +++ b/drivers/pinctrl/qcom/pinctrl-ssbi-gpio.c @@ -0,0 +1,878 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2015, Sony Mobile Communications AB. + * Copyright (c) 2013, The Linux Foundation. All rights reserved. + */ + +#include <linux/gpio/driver.h> +#include <linux/interrupt.h> +#include <linux/module.h> +#include <linux/of.h> +#include <linux/of_irq.h> +#include <linux/platform_device.h> +#include <linux/regmap.h> +#include <linux/seq_file.h> +#include <linux/slab.h> + +#include <linux/pinctrl/pinconf-generic.h> +#include <linux/pinctrl/pinconf.h> +#include <linux/pinctrl/pinctrl.h> +#include <linux/pinctrl/pinmux.h> + +#include <dt-bindings/pinctrl/qcom,pmic-gpio.h> + +#include "../core.h" +#include "../pinctrl-utils.h" + +/* mode */ +#define PM8XXX_GPIO_MODE_ENABLED BIT(0) +#define PM8XXX_GPIO_MODE_INPUT 0 +#define PM8XXX_GPIO_MODE_OUTPUT 2 + +/* output buffer */ +#define PM8XXX_GPIO_PUSH_PULL 0 +#define PM8XXX_GPIO_OPEN_DRAIN 1 + +/* bias */ +#define PM8XXX_GPIO_BIAS_PU_30 0 +#define PM8XXX_GPIO_BIAS_PU_1P5 1 +#define PM8XXX_GPIO_BIAS_PU_31P5 2 +#define PM8XXX_GPIO_BIAS_PU_1P5_30 3 +#define PM8XXX_GPIO_BIAS_PD 4 +#define PM8XXX_GPIO_BIAS_NP 5 + +/* GPIO registers */ +#define SSBI_REG_ADDR_GPIO_BASE 0x150 +#define SSBI_REG_ADDR_GPIO(n) (SSBI_REG_ADDR_GPIO_BASE + n) + +#define PM8XXX_BANK_WRITE BIT(7) + +#define PM8XXX_MAX_GPIOS 44 + +#define PM8XXX_GPIO_PHYSICAL_OFFSET 1 + +/* custom pinconf parameters */ +#define PM8XXX_QCOM_DRIVE_STRENGH (PIN_CONFIG_END + 1) +#define PM8XXX_QCOM_PULL_UP_STRENGTH (PIN_CONFIG_END + 2) + +/** + * struct pm8xxx_pin_data - dynamic configuration for a pin + * @reg: address of the control register + * @power_source: logical selected voltage source, mapping in static data + * is used translate to register values + * @mode: operating mode for the pin (input/output) + * @open_drain: output buffer configured as open-drain (vs push-pull) + * @output_value: configured output value + * @bias: register view of configured bias + * @pull_up_strength: placeholder for selected pull up strength + * only used to configure bias when pull up is selected + * @output_strength: selector of output-strength + * @disable: pin disabled / configured as tristate + * @function: pinmux selector + * @inverted: pin logic is inverted + */ +struct pm8xxx_pin_data { + unsigned reg; + u8 power_source; + u8 mode; + bool open_drain; + bool output_value; + u8 bias; + u8 pull_up_strength; + u8 output_strength; + bool disable; + u8 function; + bool inverted; +}; + +struct pm8xxx_gpio { + struct device *dev; + struct regmap *regmap; + struct pinctrl_dev *pctrl; + struct gpio_chip chip; + + struct pinctrl_desc desc; + unsigned npins; +}; + +static const struct pinconf_generic_params pm8xxx_gpio_bindings[] = { + {"qcom,drive-strength", PM8XXX_QCOM_DRIVE_STRENGH, 0}, + {"qcom,pull-up-strength", PM8XXX_QCOM_PULL_UP_STRENGTH, 0}, +}; + +#ifdef CONFIG_DEBUG_FS +static const struct pin_config_item pm8xxx_conf_items[ARRAY_SIZE(pm8xxx_gpio_bindings)] = { + PCONFDUMP(PM8XXX_QCOM_DRIVE_STRENGH, "drive-strength", NULL, true), + PCONFDUMP(PM8XXX_QCOM_PULL_UP_STRENGTH, "pull up strength", NULL, true), +}; +#endif + +static const char * const pm8xxx_groups[PM8XXX_MAX_GPIOS] = { + "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7", "gpio8", + "gpio9", "gpio10", "gpio11", "gpio12", "gpio13", "gpio14", "gpio15", + "gpio16", "gpio17", "gpio18", "gpio19", "gpio20", "gpio21", "gpio22", + "gpio23", "gpio24", "gpio25", "gpio26", "gpio27", "gpio28", "gpio29", + "gpio30", "gpio31", "gpio32", "gpio33", "gpio34", "gpio35", "gpio36", + "gpio37", "gpio38", "gpio39", "gpio40", "gpio41", "gpio42", "gpio43", + "gpio44", +}; + +static const char * const pm8xxx_gpio_functions[] = { + PMIC_GPIO_FUNC_NORMAL, PMIC_GPIO_FUNC_PAIRED, + PMIC_GPIO_FUNC_FUNC1, PMIC_GPIO_FUNC_FUNC2, + PMIC_GPIO_FUNC_DTEST1, PMIC_GPIO_FUNC_DTEST2, + PMIC_GPIO_FUNC_DTEST3, PMIC_GPIO_FUNC_DTEST4, +}; + +static int pm8xxx_read_bank(struct pm8xxx_gpio *pctrl, + struct pm8xxx_pin_data *pin, int bank) +{ + unsigned int val = bank << 4; + int ret; + + ret = regmap_write(pctrl->regmap, pin->reg, val); + if (ret) { + dev_err(pctrl->dev, "failed to select bank %d\n", bank); + return ret; + } + + ret = regmap_read(pctrl->regmap, pin->reg, &val); + if (ret) { + dev_err(pctrl->dev, "failed to read register %d\n", bank); + return ret; + } + + return val; +} + +static int pm8xxx_write_bank(struct pm8xxx_gpio *pctrl, + struct pm8xxx_pin_data *pin, + int bank, + u8 val) +{ + int ret; + + val |= PM8XXX_BANK_WRITE; + val |= bank << 4; + + ret = regmap_write(pctrl->regmap, pin->reg, val); + if (ret) + dev_err(pctrl->dev, "failed to write register\n"); + + return ret; +} + +static int pm8xxx_get_groups_count(struct pinctrl_dev *pctldev) +{ + struct pm8xxx_gpio *pctrl = pinctrl_dev_get_drvdata(pctldev); + + return pctrl->npins; +} + +static const char *pm8xxx_get_group_name(struct pinctrl_dev *pctldev, + unsigned group) +{ + return pm8xxx_groups[group]; +} + + +static int pm8xxx_get_group_pins(struct pinctrl_dev *pctldev, + unsigned group, + const unsigned **pins, + unsigned *num_pins) +{ + struct pm8xxx_gpio *pctrl = pinctrl_dev_get_drvdata(pctldev); + + *pins = &pctrl->desc.pins[group].number; + *num_pins = 1; + + return 0; +} + +static const struct pinctrl_ops pm8xxx_pinctrl_ops = { + .get_groups_count = pm8xxx_get_groups_count, + .get_group_name = pm8xxx_get_group_name, + .get_group_pins = pm8xxx_get_group_pins, + .dt_node_to_map = pinconf_generic_dt_node_to_map_group, + .dt_free_map = pinctrl_utils_free_map, +}; + +static int pm8xxx_get_functions_count(struct pinctrl_dev *pctldev) +{ + return ARRAY_SIZE(pm8xxx_gpio_functions); +} + +static const char *pm8xxx_get_function_name(struct pinctrl_dev *pctldev, + unsigned function) +{ + return pm8xxx_gpio_functions[function]; +} + +static int pm8xxx_get_function_groups(struct pinctrl_dev *pctldev, + unsigned function, + const char * const **groups, + unsigned * const num_groups) +{ + struct pm8xxx_gpio *pctrl = pinctrl_dev_get_drvdata(pctldev); + + *groups = pm8xxx_groups; + *num_groups = pctrl->npins; + return 0; +} + +static int pm8xxx_pinmux_set_mux(struct pinctrl_dev *pctldev, + unsigned function, + unsigned group) +{ + struct pm8xxx_gpio *pctrl = pinctrl_dev_get_drvdata(pctldev); + struct pm8xxx_pin_data *pin = pctrl->desc.pins[group].drv_data; + u8 val; + + pin->function = function; + val = pin->function << 1; + + pm8xxx_write_bank(pctrl, pin, 4, val); + + return 0; +} + +static const struct pinmux_ops pm8xxx_pinmux_ops = { + .get_functions_count = pm8xxx_get_functions_count, + .get_function_name = pm8xxx_get_function_name, + .get_function_groups = pm8xxx_get_function_groups, + .set_mux = pm8xxx_pinmux_set_mux, +}; + +static int pm8xxx_pin_config_get(struct pinctrl_dev *pctldev, + unsigned int offset, + unsigned long *config) +{ + struct pm8xxx_gpio *pctrl = pinctrl_dev_get_drvdata(pctldev); + struct pm8xxx_pin_data *pin = pctrl->desc.pins[offset].drv_data; + unsigned param = pinconf_to_config_param(*config); + unsigned arg; + + switch (param) { + case PIN_CONFIG_BIAS_DISABLE: + if (pin->bias != PM8XXX_GPIO_BIAS_NP) + return -EINVAL; + arg = 1; + break; + case PIN_CONFIG_BIAS_PULL_DOWN: + if (pin->bias != PM8XXX_GPIO_BIAS_PD) + return -EINVAL; + arg = 1; + break; + case PIN_CONFIG_BIAS_PULL_UP: + if (pin->bias > PM8XXX_GPIO_BIAS_PU_1P5_30) + return -EINVAL; + arg = 1; + break; + case PM8XXX_QCOM_PULL_UP_STRENGTH: + arg = pin->pull_up_strength; + break; + case PIN_CONFIG_BIAS_HIGH_IMPEDANCE: + if (!pin->disable) + return -EINVAL; + arg = 1; + break; + case PIN_CONFIG_INPUT_ENABLE: + if (pin->mode != PM8XXX_GPIO_MODE_INPUT) + return -EINVAL; + arg = 1; + break; + case PIN_CONFIG_OUTPUT: + if (pin->mode & PM8XXX_GPIO_MODE_OUTPUT) + arg = pin->output_value; + else + arg = 0; + break; + case PIN_CONFIG_POWER_SOURCE: + arg = pin->power_source; + break; + case PM8XXX_QCOM_DRIVE_STRENGH: + arg = pin->output_strength; + break; + case PIN_CONFIG_DRIVE_PUSH_PULL: + if (pin->open_drain) + return -EINVAL; + arg = 1; + break; + case PIN_CONFIG_DRIVE_OPEN_DRAIN: + if (!pin->open_drain) + return -EINVAL; + arg = 1; + break; + default: + return -EINVAL; + } + + *config = pinconf_to_config_packed(param, arg); + + return 0; +} + +static int pm8xxx_pin_config_set(struct pinctrl_dev *pctldev, + unsigned int offset, + unsigned long *configs, + unsigned num_configs) +{ + struct pm8xxx_gpio *pctrl = pinctrl_dev_get_drvdata(pctldev); + struct pm8xxx_pin_data *pin = pctrl->desc.pins[offset].drv_data; + unsigned param; + unsigned arg; + unsigned i; + u8 banks = 0; + u8 val; + + for (i = 0; i < num_configs; i++) { + param = pinconf_to_config_param(configs[i]); + arg = pinconf_to_config_argument(configs[i]); + + switch (param) { + case PIN_CONFIG_BIAS_DISABLE: + pin->bias = PM8XXX_GPIO_BIAS_NP; + banks |= BIT(2); + pin->disable = 0; + banks |= BIT(3); + break; + case PIN_CONFIG_BIAS_PULL_DOWN: + pin->bias = PM8XXX_GPIO_BIAS_PD; + banks |= BIT(2); + pin->disable = 0; + banks |= BIT(3); + break; + case PM8XXX_QCOM_PULL_UP_STRENGTH: + if (arg > PM8XXX_GPIO_BIAS_PU_1P5_30) { + dev_err(pctrl->dev, "invalid pull-up strength\n"); + return -EINVAL; + } + pin->pull_up_strength = arg; + fallthrough; + case PIN_CONFIG_BIAS_PULL_UP: + pin->bias = pin->pull_up_strength; + banks |= BIT(2); + pin->disable = 0; + banks |= BIT(3); + break; + case PIN_CONFIG_BIAS_HIGH_IMPEDANCE: + pin->disable = 1; + banks |= BIT(3); + break; + case PIN_CONFIG_INPUT_ENABLE: + pin->mode = PM8XXX_GPIO_MODE_INPUT; + banks |= BIT(0) | BIT(1); + break; + case PIN_CONFIG_OUTPUT: + pin->mode = PM8XXX_GPIO_MODE_OUTPUT; + pin->output_value = !!arg; + banks |= BIT(0) | BIT(1); + break; + case PIN_CONFIG_POWER_SOURCE: + pin->power_source = arg; + banks |= BIT(0); + break; + case PM8XXX_QCOM_DRIVE_STRENGH: + if (arg > PMIC_GPIO_STRENGTH_LOW) { + dev_err(pctrl->dev, "invalid drive strength\n"); + return -EINVAL; + } + pin->output_strength = arg; + banks |= BIT(3); + break; + case PIN_CONFIG_DRIVE_PUSH_PULL: + pin->open_drain = 0; + banks |= BIT(1); + break; + case PIN_CONFIG_DRIVE_OPEN_DRAIN: + pin->open_drain = 1; + banks |= BIT(1); + break; + default: + dev_err(pctrl->dev, + "unsupported config parameter: %x\n", + param); + return -EINVAL; + } + } + + if (banks & BIT(0)) { + val = pin->power_source << 1; + val |= PM8XXX_GPIO_MODE_ENABLED; + pm8xxx_write_bank(pctrl, pin, 0, val); + } + + if (banks & BIT(1)) { + val = pin->mode << 2; + val |= pin->open_drain << 1; + val |= pin->output_value; + pm8xxx_write_bank(pctrl, pin, 1, val); + } + + if (banks & BIT(2)) { + val = pin->bias << 1; + pm8xxx_write_bank(pctrl, pin, 2, val); + } + + if (banks & BIT(3)) { + val = pin->output_strength << 2; + val |= pin->disable; + pm8xxx_write_bank(pctrl, pin, 3, val); + } + + if (banks & BIT(4)) { + val = pin->function << 1; + pm8xxx_write_bank(pctrl, pin, 4, val); + } + + if (banks & BIT(5)) { + val = 0; + if (!pin->inverted) + val |= BIT(3); + pm8xxx_write_bank(pctrl, pin, 5, val); + } + + return 0; +} + +static const struct pinconf_ops pm8xxx_pinconf_ops = { + .is_generic = true, + .pin_config_group_get = pm8xxx_pin_config_get, + .pin_config_group_set = pm8xxx_pin_config_set, +}; + +static const struct pinctrl_desc pm8xxx_pinctrl_desc = { + .name = "pm8xxx_gpio", + .pctlops = &pm8xxx_pinctrl_ops, + .pmxops = &pm8xxx_pinmux_ops, + .confops = &pm8xxx_pinconf_ops, + .owner = THIS_MODULE, +}; + +static int pm8xxx_gpio_direction_input(struct gpio_chip *chip, + unsigned offset) +{ + struct pm8xxx_gpio *pctrl = gpiochip_get_data(chip); + struct pm8xxx_pin_data *pin = pctrl->desc.pins[offset].drv_data; + u8 val; + + pin->mode = PM8XXX_GPIO_MODE_INPUT; + val = pin->mode << 2; + + pm8xxx_write_bank(pctrl, pin, 1, val); + + return 0; +} + +static int pm8xxx_gpio_direction_output(struct gpio_chip *chip, + unsigned offset, + int value) +{ + struct pm8xxx_gpio *pctrl = gpiochip_get_data(chip); + struct pm8xxx_pin_data *pin = pctrl->desc.pins[offset].drv_data; + u8 val; + + pin->mode = PM8XXX_GPIO_MODE_OUTPUT; + pin->output_value = !!value; + + val = pin->mode << 2; + val |= pin->open_drain << 1; + val |= pin->output_value; + + pm8xxx_write_bank(pctrl, pin, 1, val); + + return 0; +} + +static int pm8xxx_gpio_get(struct gpio_chip *chip, unsigned offset) +{ + struct pm8xxx_gpio *pctrl = gpiochip_get_data(chip); + struct pm8xxx_pin_data *pin = pctrl->desc.pins[offset].drv_data; + int ret, irq; + bool state; + + if (pin->mode == PM8XXX_GPIO_MODE_OUTPUT) + return pin->output_value; + + irq = chip->to_irq(chip, offset); + if (irq >= 0) { + ret = irq_get_irqchip_state(irq, IRQCHIP_STATE_LINE_LEVEL, + &state); + if (!ret) + ret = !!state; + } else + ret = -EINVAL; + + return ret; +} + +static void pm8xxx_gpio_set(struct gpio_chip *chip, unsigned offset, int value) +{ + struct pm8xxx_gpio *pctrl = gpiochip_get_data(chip); + struct pm8xxx_pin_data *pin = pctrl->desc.pins[offset].drv_data; + u8 val; + + pin->output_value = !!value; + + val = pin->mode << 2; + val |= pin->open_drain << 1; + val |= pin->output_value; + + pm8xxx_write_bank(pctrl, pin, 1, val); +} + +static int pm8xxx_gpio_of_xlate(struct gpio_chip *chip, + const struct of_phandle_args *gpio_desc, + u32 *flags) +{ + if (chip->of_gpio_n_cells < 2) + return -EINVAL; + + if (flags) + *flags = gpio_desc->args[1]; + + return gpio_desc->args[0] - PM8XXX_GPIO_PHYSICAL_OFFSET; +} + + +#ifdef CONFIG_DEBUG_FS + +static void pm8xxx_gpio_dbg_show_one(struct seq_file *s, + struct pinctrl_dev *pctldev, + struct gpio_chip *chip, + unsigned offset, + unsigned gpio) +{ + struct pm8xxx_gpio *pctrl = gpiochip_get_data(chip); + struct pm8xxx_pin_data *pin = pctrl->desc.pins[offset].drv_data; + + static const char * const modes[] = { + "in", "both", "out", "off" + }; + static const char * const biases[] = { + "pull-up 30uA", "pull-up 1.5uA", "pull-up 31.5uA", + "pull-up 1.5uA + 30uA boost", "pull-down 10uA", "no pull" + }; + static const char * const buffer_types[] = { + "push-pull", "open-drain" + }; + static const char * const strengths[] = { + "no", "high", "medium", "low" + }; + + seq_printf(s, " gpio%-2d:", offset + PM8XXX_GPIO_PHYSICAL_OFFSET); + if (pin->disable) { + seq_puts(s, " ---"); + } else { + seq_printf(s, " %-4s", modes[pin->mode]); + seq_printf(s, " %-7s", pm8xxx_gpio_functions[pin->function]); + seq_printf(s, " VIN%d", pin->power_source); + seq_printf(s, " %-27s", biases[pin->bias]); + seq_printf(s, " %-10s", buffer_types[pin->open_drain]); + seq_printf(s, " %-4s", pin->output_value ? "high" : "low"); + seq_printf(s, " %-7s", strengths[pin->output_strength]); + if (pin->inverted) + seq_puts(s, " inverted"); + } +} + +static void pm8xxx_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip) +{ + unsigned gpio = chip->base; + unsigned i; + + for (i = 0; i < chip->ngpio; i++, gpio++) { + pm8xxx_gpio_dbg_show_one(s, NULL, chip, i, gpio); + seq_puts(s, "\n"); + } +} + +#else +#define pm8xxx_gpio_dbg_show NULL +#endif + +static const struct gpio_chip pm8xxx_gpio_template = { + .direction_input = pm8xxx_gpio_direction_input, + .direction_output = pm8xxx_gpio_direction_output, + .get = pm8xxx_gpio_get, + .set = pm8xxx_gpio_set, + .of_xlate = pm8xxx_gpio_of_xlate, + .dbg_show = pm8xxx_gpio_dbg_show, + .owner = THIS_MODULE, +}; + +static int pm8xxx_pin_populate(struct pm8xxx_gpio *pctrl, + struct pm8xxx_pin_data *pin) +{ + int val; + + val = pm8xxx_read_bank(pctrl, pin, 0); + if (val < 0) + return val; + + pin->power_source = (val >> 1) & 0x7; + + val = pm8xxx_read_bank(pctrl, pin, 1); + if (val < 0) + return val; + + pin->mode = (val >> 2) & 0x3; + pin->open_drain = !!(val & BIT(1)); + pin->output_value = val & BIT(0); + + val = pm8xxx_read_bank(pctrl, pin, 2); + if (val < 0) + return val; + + pin->bias = (val >> 1) & 0x7; + if (pin->bias <= PM8XXX_GPIO_BIAS_PU_1P5_30) + pin->pull_up_strength = pin->bias; + else + pin->pull_up_strength = PM8XXX_GPIO_BIAS_PU_30; + + val = pm8xxx_read_bank(pctrl, pin, 3); + if (val < 0) + return val; + + pin->output_strength = (val >> 2) & 0x3; + pin->disable = val & BIT(0); + + val = pm8xxx_read_bank(pctrl, pin, 4); + if (val < 0) + return val; + + pin->function = (val >> 1) & 0x7; + + val = pm8xxx_read_bank(pctrl, pin, 5); + if (val < 0) + return val; + + pin->inverted = !(val & BIT(3)); + + return 0; +} + +static void pm8xxx_irq_disable(struct irq_data *d) +{ + struct gpio_chip *gc = irq_data_get_irq_chip_data(d); + + gpiochip_disable_irq(gc, irqd_to_hwirq(d)); +} + +static void pm8xxx_irq_enable(struct irq_data *d) +{ + struct gpio_chip *gc = irq_data_get_irq_chip_data(d); + + gpiochip_enable_irq(gc, irqd_to_hwirq(d)); +} + +static const struct irq_chip pm8xxx_irq_chip = { + .name = "ssbi-gpio", + .irq_mask_ack = irq_chip_mask_ack_parent, + .irq_unmask = irq_chip_unmask_parent, + .irq_disable = pm8xxx_irq_disable, + .irq_enable = pm8xxx_irq_enable, + .irq_set_type = irq_chip_set_type_parent, + .flags = IRQCHIP_MASK_ON_SUSPEND | IRQCHIP_SKIP_SET_WAKE | + IRQCHIP_IMMUTABLE, + GPIOCHIP_IRQ_RESOURCE_HELPERS, +}; + +static int pm8xxx_domain_translate(struct irq_domain *domain, + struct irq_fwspec *fwspec, + unsigned long *hwirq, + unsigned int *type) +{ + struct pm8xxx_gpio *pctrl = container_of(domain->host_data, + struct pm8xxx_gpio, chip); + + if (fwspec->param_count != 2 || fwspec->param[0] < 1 || + fwspec->param[0] > pctrl->chip.ngpio) + return -EINVAL; + + *hwirq = fwspec->param[0] - PM8XXX_GPIO_PHYSICAL_OFFSET; + *type = fwspec->param[1]; + + return 0; +} + +static unsigned int pm8xxx_child_offset_to_irq(struct gpio_chip *chip, + unsigned int offset) +{ + return offset + PM8XXX_GPIO_PHYSICAL_OFFSET; +} + +static int pm8xxx_child_to_parent_hwirq(struct gpio_chip *chip, + unsigned int child_hwirq, + unsigned int child_type, + unsigned int *parent_hwirq, + unsigned int *parent_type) +{ + *parent_hwirq = child_hwirq + 0xc0; + *parent_type = child_type; + + return 0; +} + +static const struct of_device_id pm8xxx_gpio_of_match[] = { + { .compatible = "qcom,pm8018-gpio", .data = (void *) 6 }, + { .compatible = "qcom,pm8038-gpio", .data = (void *) 12 }, + { .compatible = "qcom,pm8058-gpio", .data = (void *) 44 }, + { .compatible = "qcom,pm8917-gpio", .data = (void *) 38 }, + { .compatible = "qcom,pm8921-gpio", .data = (void *) 44 }, + { }, +}; +MODULE_DEVICE_TABLE(of, pm8xxx_gpio_of_match); + +static int pm8xxx_gpio_probe(struct platform_device *pdev) +{ + struct pm8xxx_pin_data *pin_data; + struct irq_domain *parent_domain; + struct device_node *parent_node; + struct pinctrl_pin_desc *pins; + struct gpio_irq_chip *girq; + struct pm8xxx_gpio *pctrl; + int ret, i; + + pctrl = devm_kzalloc(&pdev->dev, sizeof(*pctrl), GFP_KERNEL); + if (!pctrl) + return -ENOMEM; + + pctrl->dev = &pdev->dev; + pctrl->npins = (uintptr_t) device_get_match_data(&pdev->dev); + + pctrl->regmap = dev_get_regmap(pdev->dev.parent, NULL); + if (!pctrl->regmap) { + dev_err(&pdev->dev, "parent regmap unavailable\n"); + return -ENXIO; + } + + pctrl->desc = pm8xxx_pinctrl_desc; + pctrl->desc.npins = pctrl->npins; + + pins = devm_kcalloc(&pdev->dev, + pctrl->desc.npins, + sizeof(struct pinctrl_pin_desc), + GFP_KERNEL); + if (!pins) + return -ENOMEM; + + pin_data = devm_kcalloc(&pdev->dev, + pctrl->desc.npins, + sizeof(struct pm8xxx_pin_data), + GFP_KERNEL); + if (!pin_data) + return -ENOMEM; + + for (i = 0; i < pctrl->desc.npins; i++) { + pin_data[i].reg = SSBI_REG_ADDR_GPIO(i); + + ret = pm8xxx_pin_populate(pctrl, &pin_data[i]); + if (ret) + return ret; + + pins[i].number = i; + pins[i].name = pm8xxx_groups[i]; + pins[i].drv_data = &pin_data[i]; + } + pctrl->desc.pins = pins; + + pctrl->desc.num_custom_params = ARRAY_SIZE(pm8xxx_gpio_bindings); + pctrl->desc.custom_params = pm8xxx_gpio_bindings; +#ifdef CONFIG_DEBUG_FS + pctrl->desc.custom_conf_items = pm8xxx_conf_items; +#endif + + pctrl->pctrl = devm_pinctrl_register(&pdev->dev, &pctrl->desc, pctrl); + if (IS_ERR(pctrl->pctrl)) { + dev_err(&pdev->dev, "couldn't register pm8xxx gpio driver\n"); + return PTR_ERR(pctrl->pctrl); + } + + pctrl->chip = pm8xxx_gpio_template; + pctrl->chip.base = -1; + pctrl->chip.parent = &pdev->dev; + pctrl->chip.of_gpio_n_cells = 2; + pctrl->chip.label = dev_name(pctrl->dev); + pctrl->chip.ngpio = pctrl->npins; + + parent_node = of_irq_find_parent(pctrl->dev->of_node); + if (!parent_node) + return -ENXIO; + + parent_domain = irq_find_host(parent_node); + of_node_put(parent_node); + if (!parent_domain) + return -ENXIO; + + girq = &pctrl->chip.irq; + gpio_irq_chip_set_chip(girq, &pm8xxx_irq_chip); + girq->default_type = IRQ_TYPE_NONE; + girq->handler = handle_level_irq; + girq->fwnode = dev_fwnode(pctrl->dev); + girq->parent_domain = parent_domain; + girq->child_to_parent_hwirq = pm8xxx_child_to_parent_hwirq; + girq->populate_parent_alloc_arg = gpiochip_populate_parent_fwspec_twocell; + girq->child_offset_to_irq = pm8xxx_child_offset_to_irq; + girq->child_irq_domain_ops.translate = pm8xxx_domain_translate; + + ret = gpiochip_add_data(&pctrl->chip, pctrl); + if (ret) { + dev_err(&pdev->dev, "failed register gpiochip\n"); + return ret; + } + + /* + * For DeviceTree-supported systems, the gpio core checks the + * pinctrl's device node for the "gpio-ranges" property. + * If it is present, it takes care of adding the pin ranges + * for the driver. In this case the driver can skip ahead. + * + * In order to remain compatible with older, existing DeviceTree + * files which don't set the "gpio-ranges" property or systems that + * utilize ACPI the driver has to call gpiochip_add_pin_range(). + */ + if (!of_property_read_bool(pctrl->dev->of_node, "gpio-ranges")) { + ret = gpiochip_add_pin_range(&pctrl->chip, dev_name(pctrl->dev), + 0, 0, pctrl->chip.ngpio); + if (ret) { + dev_err(pctrl->dev, "failed to add pin range\n"); + goto unregister_gpiochip; + } + } + + platform_set_drvdata(pdev, pctrl); + + dev_dbg(&pdev->dev, "Qualcomm pm8xxx gpio driver probed\n"); + + return 0; + +unregister_gpiochip: + gpiochip_remove(&pctrl->chip); + + return ret; +} + +static int pm8xxx_gpio_remove(struct platform_device *pdev) +{ + struct pm8xxx_gpio *pctrl = platform_get_drvdata(pdev); + + gpiochip_remove(&pctrl->chip); + + return 0; +} + +static struct platform_driver pm8xxx_gpio_driver = { + .driver = { + .name = "qcom-ssbi-gpio", + .of_match_table = pm8xxx_gpio_of_match, + }, + .probe = pm8xxx_gpio_probe, + .remove = pm8xxx_gpio_remove, +}; + +module_platform_driver(pm8xxx_gpio_driver); + +MODULE_AUTHOR("Bjorn Andersson <bjorn.andersson@sonymobile.com>"); +MODULE_DESCRIPTION("Qualcomm PM8xxx GPIO driver"); +MODULE_LICENSE("GPL v2"); diff --git a/drivers/pinctrl/qcom/pinctrl-ssbi-mpp.c b/drivers/pinctrl/qcom/pinctrl-ssbi-mpp.c new file mode 100644 index 0000000000..985d1a0ee8 --- /dev/null +++ b/drivers/pinctrl/qcom/pinctrl-ssbi-mpp.c @@ -0,0 +1,961 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2015, Sony Mobile Communications AB. + * Copyright (c) 2013, The Linux Foundation. All rights reserved. + */ + +#include <linux/gpio/driver.h> +#include <linux/interrupt.h> +#include <linux/module.h> +#include <linux/of.h> +#include <linux/of_irq.h> +#include <linux/platform_device.h> +#include <linux/regmap.h> +#include <linux/seq_file.h> +#include <linux/slab.h> + +#include <linux/pinctrl/pinconf-generic.h> +#include <linux/pinctrl/pinconf.h> +#include <linux/pinctrl/pinctrl.h> +#include <linux/pinctrl/pinmux.h> + +#include <dt-bindings/pinctrl/qcom,pmic-mpp.h> + +#include "../core.h" +#include "../pinctrl-utils.h" + +/* MPP registers */ +#define SSBI_REG_ADDR_MPP_BASE 0x50 +#define SSBI_REG_ADDR_MPP(n) (SSBI_REG_ADDR_MPP_BASE + n) + +/* MPP Type: type */ +#define PM8XXX_MPP_TYPE_D_INPUT 0 +#define PM8XXX_MPP_TYPE_D_OUTPUT 1 +#define PM8XXX_MPP_TYPE_D_BI_DIR 2 +#define PM8XXX_MPP_TYPE_A_INPUT 3 +#define PM8XXX_MPP_TYPE_A_OUTPUT 4 +#define PM8XXX_MPP_TYPE_SINK 5 +#define PM8XXX_MPP_TYPE_DTEST_SINK 6 +#define PM8XXX_MPP_TYPE_DTEST_OUTPUT 7 + +/* Digital Input: control */ +#define PM8XXX_MPP_DIN_TO_INT 0 +#define PM8XXX_MPP_DIN_TO_DBUS1 1 +#define PM8XXX_MPP_DIN_TO_DBUS2 2 +#define PM8XXX_MPP_DIN_TO_DBUS3 3 + +/* Digital Output: control */ +#define PM8XXX_MPP_DOUT_CTRL_LOW 0 +#define PM8XXX_MPP_DOUT_CTRL_HIGH 1 +#define PM8XXX_MPP_DOUT_CTRL_MPP 2 +#define PM8XXX_MPP_DOUT_CTRL_INV_MPP 3 + +/* Bidirectional: control */ +#define PM8XXX_MPP_BI_PULLUP_1KOHM 0 +#define PM8XXX_MPP_BI_PULLUP_OPEN 1 +#define PM8XXX_MPP_BI_PULLUP_10KOHM 2 +#define PM8XXX_MPP_BI_PULLUP_30KOHM 3 + +/* Analog Output: control */ +#define PM8XXX_MPP_AOUT_CTRL_DISABLE 0 +#define PM8XXX_MPP_AOUT_CTRL_ENABLE 1 +#define PM8XXX_MPP_AOUT_CTRL_MPP_HIGH_EN 2 +#define PM8XXX_MPP_AOUT_CTRL_MPP_LOW_EN 3 + +/* Current Sink: control */ +#define PM8XXX_MPP_CS_CTRL_DISABLE 0 +#define PM8XXX_MPP_CS_CTRL_ENABLE 1 +#define PM8XXX_MPP_CS_CTRL_MPP_HIGH_EN 2 +#define PM8XXX_MPP_CS_CTRL_MPP_LOW_EN 3 + +/* DTEST Current Sink: control */ +#define PM8XXX_MPP_DTEST_CS_CTRL_EN1 0 +#define PM8XXX_MPP_DTEST_CS_CTRL_EN2 1 +#define PM8XXX_MPP_DTEST_CS_CTRL_EN3 2 +#define PM8XXX_MPP_DTEST_CS_CTRL_EN4 3 + +/* DTEST Digital Output: control */ +#define PM8XXX_MPP_DTEST_DBUS1 0 +#define PM8XXX_MPP_DTEST_DBUS2 1 +#define PM8XXX_MPP_DTEST_DBUS3 2 +#define PM8XXX_MPP_DTEST_DBUS4 3 + +/* custom pinconf parameters */ +#define PM8XXX_CONFIG_AMUX (PIN_CONFIG_END + 1) +#define PM8XXX_CONFIG_DTEST_SELECTOR (PIN_CONFIG_END + 2) +#define PM8XXX_CONFIG_ALEVEL (PIN_CONFIG_END + 3) +#define PM8XXX_CONFIG_PAIRED (PIN_CONFIG_END + 4) + +/** + * struct pm8xxx_pin_data - dynamic configuration for a pin + * @reg: address of the control register + * @mode: operating mode for the pin (digital, analog or current sink) + * @input: pin is input + * @output: pin is output + * @high_z: pin is floating + * @paired: mpp operates in paired mode + * @output_value: logical output value of the mpp + * @power_source: selected power source + * @dtest: DTEST route selector + * @amux: input muxing in analog mode + * @aout_level: selector of the output in analog mode + * @drive_strength: drive strength of the current sink + * @pullup: pull up value, when in digital bidirectional mode + */ +struct pm8xxx_pin_data { + unsigned reg; + + u8 mode; + + bool input; + bool output; + bool high_z; + bool paired; + bool output_value; + + u8 power_source; + u8 dtest; + u8 amux; + u8 aout_level; + u8 drive_strength; + unsigned pullup; +}; + +struct pm8xxx_mpp { + struct device *dev; + struct regmap *regmap; + struct pinctrl_dev *pctrl; + struct gpio_chip chip; + + struct pinctrl_desc desc; + unsigned npins; +}; + +static const struct pinconf_generic_params pm8xxx_mpp_bindings[] = { + {"qcom,amux-route", PM8XXX_CONFIG_AMUX, 0}, + {"qcom,analog-level", PM8XXX_CONFIG_ALEVEL, 0}, + {"qcom,dtest", PM8XXX_CONFIG_DTEST_SELECTOR, 0}, + {"qcom,paired", PM8XXX_CONFIG_PAIRED, 0}, +}; + +#ifdef CONFIG_DEBUG_FS +static const struct pin_config_item pm8xxx_conf_items[] = { + PCONFDUMP(PM8XXX_CONFIG_AMUX, "analog mux", NULL, true), + PCONFDUMP(PM8XXX_CONFIG_ALEVEL, "analog level", NULL, true), + PCONFDUMP(PM8XXX_CONFIG_DTEST_SELECTOR, "dtest", NULL, true), + PCONFDUMP(PM8XXX_CONFIG_PAIRED, "paired", NULL, false), +}; +#endif + +#define PM8XXX_MAX_MPPS 12 +#define PM8XXX_MPP_PHYSICAL_OFFSET 1 + +static const char * const pm8xxx_groups[PM8XXX_MAX_MPPS] = { + "mpp1", "mpp2", "mpp3", "mpp4", "mpp5", "mpp6", "mpp7", "mpp8", + "mpp9", "mpp10", "mpp11", "mpp12", +}; + +#define PM8XXX_MPP_DIGITAL 0 +#define PM8XXX_MPP_ANALOG 1 +#define PM8XXX_MPP_SINK 2 + +static const char * const pm8xxx_mpp_functions[] = { + "digital", "analog", "sink", +}; + +static int pm8xxx_mpp_update(struct pm8xxx_mpp *pctrl, + struct pm8xxx_pin_data *pin) +{ + unsigned level; + unsigned ctrl; + unsigned type; + int ret; + u8 val; + + switch (pin->mode) { + case PM8XXX_MPP_DIGITAL: + if (pin->dtest) { + type = PM8XXX_MPP_TYPE_DTEST_OUTPUT; + ctrl = pin->dtest - 1; + } else if (pin->input && pin->output) { + type = PM8XXX_MPP_TYPE_D_BI_DIR; + if (pin->high_z) + ctrl = PM8XXX_MPP_BI_PULLUP_OPEN; + else if (pin->pullup == 600) + ctrl = PM8XXX_MPP_BI_PULLUP_1KOHM; + else if (pin->pullup == 10000) + ctrl = PM8XXX_MPP_BI_PULLUP_10KOHM; + else + ctrl = PM8XXX_MPP_BI_PULLUP_30KOHM; + } else if (pin->input) { + type = PM8XXX_MPP_TYPE_D_INPUT; + if (pin->dtest) + ctrl = pin->dtest; + else + ctrl = PM8XXX_MPP_DIN_TO_INT; + } else { + type = PM8XXX_MPP_TYPE_D_OUTPUT; + ctrl = !!pin->output_value; + if (pin->paired) + ctrl |= BIT(1); + } + + level = pin->power_source; + break; + case PM8XXX_MPP_ANALOG: + if (pin->output) { + type = PM8XXX_MPP_TYPE_A_OUTPUT; + level = pin->aout_level; + ctrl = pin->output_value; + if (pin->paired) + ctrl |= BIT(1); + } else { + type = PM8XXX_MPP_TYPE_A_INPUT; + level = pin->amux; + ctrl = 0; + } + break; + case PM8XXX_MPP_SINK: + level = (pin->drive_strength / 5) - 1; + if (pin->dtest) { + type = PM8XXX_MPP_TYPE_DTEST_SINK; + ctrl = pin->dtest - 1; + } else { + type = PM8XXX_MPP_TYPE_SINK; + ctrl = pin->output_value; + if (pin->paired) + ctrl |= BIT(1); + } + break; + default: + return -EINVAL; + } + + val = type << 5 | level << 2 | ctrl; + ret = regmap_write(pctrl->regmap, pin->reg, val); + if (ret) + dev_err(pctrl->dev, "failed to write register\n"); + + return ret; +} + +static int pm8xxx_get_groups_count(struct pinctrl_dev *pctldev) +{ + struct pm8xxx_mpp *pctrl = pinctrl_dev_get_drvdata(pctldev); + + return pctrl->npins; +} + +static const char *pm8xxx_get_group_name(struct pinctrl_dev *pctldev, + unsigned group) +{ + return pm8xxx_groups[group]; +} + + +static int pm8xxx_get_group_pins(struct pinctrl_dev *pctldev, + unsigned group, + const unsigned **pins, + unsigned *num_pins) +{ + struct pm8xxx_mpp *pctrl = pinctrl_dev_get_drvdata(pctldev); + + *pins = &pctrl->desc.pins[group].number; + *num_pins = 1; + + return 0; +} + +static const struct pinctrl_ops pm8xxx_pinctrl_ops = { + .get_groups_count = pm8xxx_get_groups_count, + .get_group_name = pm8xxx_get_group_name, + .get_group_pins = pm8xxx_get_group_pins, + .dt_node_to_map = pinconf_generic_dt_node_to_map_group, + .dt_free_map = pinctrl_utils_free_map, +}; + +static int pm8xxx_get_functions_count(struct pinctrl_dev *pctldev) +{ + return ARRAY_SIZE(pm8xxx_mpp_functions); +} + +static const char *pm8xxx_get_function_name(struct pinctrl_dev *pctldev, + unsigned function) +{ + return pm8xxx_mpp_functions[function]; +} + +static int pm8xxx_get_function_groups(struct pinctrl_dev *pctldev, + unsigned function, + const char * const **groups, + unsigned * const num_groups) +{ + struct pm8xxx_mpp *pctrl = pinctrl_dev_get_drvdata(pctldev); + + *groups = pm8xxx_groups; + *num_groups = pctrl->npins; + return 0; +} + +static int pm8xxx_pinmux_set_mux(struct pinctrl_dev *pctldev, + unsigned function, + unsigned group) +{ + struct pm8xxx_mpp *pctrl = pinctrl_dev_get_drvdata(pctldev); + struct pm8xxx_pin_data *pin = pctrl->desc.pins[group].drv_data; + + pin->mode = function; + pm8xxx_mpp_update(pctrl, pin); + + return 0; +} + +static const struct pinmux_ops pm8xxx_pinmux_ops = { + .get_functions_count = pm8xxx_get_functions_count, + .get_function_name = pm8xxx_get_function_name, + .get_function_groups = pm8xxx_get_function_groups, + .set_mux = pm8xxx_pinmux_set_mux, +}; + +static int pm8xxx_pin_config_get(struct pinctrl_dev *pctldev, + unsigned int offset, + unsigned long *config) +{ + struct pm8xxx_mpp *pctrl = pinctrl_dev_get_drvdata(pctldev); + struct pm8xxx_pin_data *pin = pctrl->desc.pins[offset].drv_data; + unsigned param = pinconf_to_config_param(*config); + unsigned arg; + + switch (param) { + case PIN_CONFIG_BIAS_PULL_UP: + arg = pin->pullup; + break; + case PIN_CONFIG_BIAS_HIGH_IMPEDANCE: + arg = pin->high_z; + break; + case PIN_CONFIG_INPUT_ENABLE: + arg = pin->input; + break; + case PIN_CONFIG_OUTPUT: + arg = pin->output_value; + break; + case PIN_CONFIG_POWER_SOURCE: + arg = pin->power_source; + break; + case PIN_CONFIG_DRIVE_STRENGTH: + arg = pin->drive_strength; + break; + case PM8XXX_CONFIG_DTEST_SELECTOR: + arg = pin->dtest; + break; + case PM8XXX_CONFIG_AMUX: + arg = pin->amux; + break; + case PM8XXX_CONFIG_ALEVEL: + arg = pin->aout_level; + break; + case PM8XXX_CONFIG_PAIRED: + arg = pin->paired; + break; + default: + return -EINVAL; + } + + *config = pinconf_to_config_packed(param, arg); + + return 0; +} + +static int pm8xxx_pin_config_set(struct pinctrl_dev *pctldev, + unsigned int offset, + unsigned long *configs, + unsigned num_configs) +{ + struct pm8xxx_mpp *pctrl = pinctrl_dev_get_drvdata(pctldev); + struct pm8xxx_pin_data *pin = pctrl->desc.pins[offset].drv_data; + unsigned param; + unsigned arg; + unsigned i; + + for (i = 0; i < num_configs; i++) { + param = pinconf_to_config_param(configs[i]); + arg = pinconf_to_config_argument(configs[i]); + + switch (param) { + case PIN_CONFIG_BIAS_PULL_UP: + pin->pullup = arg; + break; + case PIN_CONFIG_BIAS_HIGH_IMPEDANCE: + pin->high_z = true; + break; + case PIN_CONFIG_INPUT_ENABLE: + pin->input = true; + break; + case PIN_CONFIG_OUTPUT: + pin->output = true; + pin->output_value = !!arg; + break; + case PIN_CONFIG_POWER_SOURCE: + pin->power_source = arg; + break; + case PIN_CONFIG_DRIVE_STRENGTH: + pin->drive_strength = arg; + break; + case PM8XXX_CONFIG_DTEST_SELECTOR: + pin->dtest = arg; + break; + case PM8XXX_CONFIG_AMUX: + pin->amux = arg; + break; + case PM8XXX_CONFIG_ALEVEL: + pin->aout_level = arg; + break; + case PM8XXX_CONFIG_PAIRED: + pin->paired = !!arg; + break; + default: + dev_err(pctrl->dev, + "unsupported config parameter: %x\n", + param); + return -EINVAL; + } + } + + pm8xxx_mpp_update(pctrl, pin); + + return 0; +} + +static const struct pinconf_ops pm8xxx_pinconf_ops = { + .is_generic = true, + .pin_config_group_get = pm8xxx_pin_config_get, + .pin_config_group_set = pm8xxx_pin_config_set, +}; + +static const struct pinctrl_desc pm8xxx_pinctrl_desc = { + .name = "pm8xxx_mpp", + .pctlops = &pm8xxx_pinctrl_ops, + .pmxops = &pm8xxx_pinmux_ops, + .confops = &pm8xxx_pinconf_ops, + .owner = THIS_MODULE, +}; + +static int pm8xxx_mpp_direction_input(struct gpio_chip *chip, + unsigned offset) +{ + struct pm8xxx_mpp *pctrl = gpiochip_get_data(chip); + struct pm8xxx_pin_data *pin = pctrl->desc.pins[offset].drv_data; + + switch (pin->mode) { + case PM8XXX_MPP_DIGITAL: + pin->input = true; + break; + case PM8XXX_MPP_ANALOG: + pin->input = true; + pin->output = true; + break; + case PM8XXX_MPP_SINK: + return -EINVAL; + } + + pm8xxx_mpp_update(pctrl, pin); + + return 0; +} + +static int pm8xxx_mpp_direction_output(struct gpio_chip *chip, + unsigned offset, + int value) +{ + struct pm8xxx_mpp *pctrl = gpiochip_get_data(chip); + struct pm8xxx_pin_data *pin = pctrl->desc.pins[offset].drv_data; + + switch (pin->mode) { + case PM8XXX_MPP_DIGITAL: + pin->output = true; + break; + case PM8XXX_MPP_ANALOG: + pin->input = false; + pin->output = true; + break; + case PM8XXX_MPP_SINK: + pin->input = false; + pin->output = true; + break; + } + + pm8xxx_mpp_update(pctrl, pin); + + return 0; +} + +static int pm8xxx_mpp_get(struct gpio_chip *chip, unsigned offset) +{ + struct pm8xxx_mpp *pctrl = gpiochip_get_data(chip); + struct pm8xxx_pin_data *pin = pctrl->desc.pins[offset].drv_data; + bool state; + int ret, irq; + + if (!pin->input) + return !!pin->output_value; + + irq = chip->to_irq(chip, offset); + if (irq < 0) + return irq; + + ret = irq_get_irqchip_state(irq, IRQCHIP_STATE_LINE_LEVEL, &state); + if (!ret) + ret = !!state; + + return ret; +} + +static void pm8xxx_mpp_set(struct gpio_chip *chip, unsigned offset, int value) +{ + struct pm8xxx_mpp *pctrl = gpiochip_get_data(chip); + struct pm8xxx_pin_data *pin = pctrl->desc.pins[offset].drv_data; + + pin->output_value = !!value; + + pm8xxx_mpp_update(pctrl, pin); +} + +static int pm8xxx_mpp_of_xlate(struct gpio_chip *chip, + const struct of_phandle_args *gpio_desc, + u32 *flags) +{ + if (chip->of_gpio_n_cells < 2) + return -EINVAL; + + if (flags) + *flags = gpio_desc->args[1]; + + return gpio_desc->args[0] - PM8XXX_MPP_PHYSICAL_OFFSET; +} + + +#ifdef CONFIG_DEBUG_FS + +static void pm8xxx_mpp_dbg_show_one(struct seq_file *s, + struct pinctrl_dev *pctldev, + struct gpio_chip *chip, + unsigned offset, + unsigned gpio) +{ + struct pm8xxx_mpp *pctrl = gpiochip_get_data(chip); + struct pm8xxx_pin_data *pin = pctrl->desc.pins[offset].drv_data; + + static const char * const aout_lvls[] = { + "1v25", "1v25_2", "0v625", "0v3125", "mpp", "abus1", "abus2", + "abus3" + }; + + static const char * const amuxs[] = { + "amux5", "amux6", "amux7", "amux8", "amux9", "abus1", "abus2", + "abus3", + }; + + seq_printf(s, " mpp%-2d:", offset + PM8XXX_MPP_PHYSICAL_OFFSET); + + switch (pin->mode) { + case PM8XXX_MPP_DIGITAL: + seq_puts(s, " digital "); + if (pin->dtest) { + seq_printf(s, "dtest%d\n", pin->dtest); + } else if (pin->input && pin->output) { + if (pin->high_z) + seq_puts(s, "bi-dir high-z"); + else + seq_printf(s, "bi-dir %dOhm", pin->pullup); + } else if (pin->input) { + if (pin->dtest) + seq_printf(s, "in dtest%d", pin->dtest); + else + seq_puts(s, "in gpio"); + } else if (pin->output) { + seq_puts(s, "out "); + + if (!pin->paired) { + seq_puts(s, pin->output_value ? + "high" : "low"); + } else { + seq_puts(s, pin->output_value ? + "inverted" : "follow"); + } + } + break; + case PM8XXX_MPP_ANALOG: + seq_puts(s, " analog "); + if (pin->output) { + seq_printf(s, "out %s ", aout_lvls[pin->aout_level]); + if (!pin->paired) { + seq_puts(s, pin->output_value ? + "high" : "low"); + } else { + seq_puts(s, pin->output_value ? + "inverted" : "follow"); + } + } else { + seq_printf(s, "input mux %s", amuxs[pin->amux]); + } + break; + case PM8XXX_MPP_SINK: + seq_printf(s, " sink %dmA ", pin->drive_strength); + if (pin->dtest) { + seq_printf(s, "dtest%d", pin->dtest); + } else { + if (!pin->paired) { + seq_puts(s, pin->output_value ? + "high" : "low"); + } else { + seq_puts(s, pin->output_value ? + "inverted" : "follow"); + } + } + break; + } +} + +static void pm8xxx_mpp_dbg_show(struct seq_file *s, struct gpio_chip *chip) +{ + unsigned gpio = chip->base; + unsigned i; + + for (i = 0; i < chip->ngpio; i++, gpio++) { + pm8xxx_mpp_dbg_show_one(s, NULL, chip, i, gpio); + seq_puts(s, "\n"); + } +} + +#else +#define pm8xxx_mpp_dbg_show NULL +#endif + +static const struct gpio_chip pm8xxx_mpp_template = { + .direction_input = pm8xxx_mpp_direction_input, + .direction_output = pm8xxx_mpp_direction_output, + .get = pm8xxx_mpp_get, + .set = pm8xxx_mpp_set, + .of_xlate = pm8xxx_mpp_of_xlate, + .dbg_show = pm8xxx_mpp_dbg_show, + .owner = THIS_MODULE, +}; + +static int pm8xxx_pin_populate(struct pm8xxx_mpp *pctrl, + struct pm8xxx_pin_data *pin) +{ + unsigned int val; + unsigned level; + unsigned ctrl; + unsigned type; + int ret; + + ret = regmap_read(pctrl->regmap, pin->reg, &val); + if (ret) { + dev_err(pctrl->dev, "failed to read register\n"); + return ret; + } + + type = (val >> 5) & 7; + level = (val >> 2) & 7; + ctrl = (val) & 3; + + switch (type) { + case PM8XXX_MPP_TYPE_D_INPUT: + pin->mode = PM8XXX_MPP_DIGITAL; + pin->input = true; + pin->power_source = level; + pin->dtest = ctrl; + break; + case PM8XXX_MPP_TYPE_D_OUTPUT: + pin->mode = PM8XXX_MPP_DIGITAL; + pin->output = true; + pin->power_source = level; + pin->output_value = !!(ctrl & BIT(0)); + pin->paired = !!(ctrl & BIT(1)); + break; + case PM8XXX_MPP_TYPE_D_BI_DIR: + pin->mode = PM8XXX_MPP_DIGITAL; + pin->input = true; + pin->output = true; + pin->power_source = level; + switch (ctrl) { + case PM8XXX_MPP_BI_PULLUP_1KOHM: + pin->pullup = 600; + break; + case PM8XXX_MPP_BI_PULLUP_OPEN: + pin->high_z = true; + break; + case PM8XXX_MPP_BI_PULLUP_10KOHM: + pin->pullup = 10000; + break; + case PM8XXX_MPP_BI_PULLUP_30KOHM: + pin->pullup = 30000; + break; + } + break; + case PM8XXX_MPP_TYPE_A_INPUT: + pin->mode = PM8XXX_MPP_ANALOG; + pin->input = true; + pin->amux = level; + break; + case PM8XXX_MPP_TYPE_A_OUTPUT: + pin->mode = PM8XXX_MPP_ANALOG; + pin->output = true; + pin->aout_level = level; + pin->output_value = !!(ctrl & BIT(0)); + pin->paired = !!(ctrl & BIT(1)); + break; + case PM8XXX_MPP_TYPE_SINK: + pin->mode = PM8XXX_MPP_SINK; + pin->drive_strength = 5 * (level + 1); + pin->output_value = !!(ctrl & BIT(0)); + pin->paired = !!(ctrl & BIT(1)); + break; + case PM8XXX_MPP_TYPE_DTEST_SINK: + pin->mode = PM8XXX_MPP_SINK; + pin->dtest = ctrl + 1; + pin->drive_strength = 5 * (level + 1); + break; + case PM8XXX_MPP_TYPE_DTEST_OUTPUT: + pin->mode = PM8XXX_MPP_DIGITAL; + pin->power_source = level; + if (ctrl >= 1) + pin->dtest = ctrl; + break; + } + + return 0; +} + +static int pm8xxx_mpp_domain_translate(struct irq_domain *domain, + struct irq_fwspec *fwspec, + unsigned long *hwirq, + unsigned int *type) +{ + struct pm8xxx_mpp *pctrl = container_of(domain->host_data, + struct pm8xxx_mpp, chip); + + if (fwspec->param_count != 2 || + fwspec->param[0] < PM8XXX_MPP_PHYSICAL_OFFSET || + fwspec->param[0] > pctrl->chip.ngpio) + return -EINVAL; + + *hwirq = fwspec->param[0] - PM8XXX_MPP_PHYSICAL_OFFSET; + *type = fwspec->param[1]; + + return 0; +} + +static unsigned int pm8xxx_mpp_child_offset_to_irq(struct gpio_chip *chip, + unsigned int offset) +{ + return offset + PM8XXX_MPP_PHYSICAL_OFFSET; +} + +static int pm8821_mpp_child_to_parent_hwirq(struct gpio_chip *chip, + unsigned int child_hwirq, + unsigned int child_type, + unsigned int *parent_hwirq, + unsigned int *parent_type) +{ + *parent_hwirq = child_hwirq + 24; + *parent_type = child_type; + + return 0; +} + +static int pm8xxx_mpp_child_to_parent_hwirq(struct gpio_chip *chip, + unsigned int child_hwirq, + unsigned int child_type, + unsigned int *parent_hwirq, + unsigned int *parent_type) +{ + *parent_hwirq = child_hwirq + 0x80; + *parent_type = child_type; + + return 0; +} + +static void pm8xxx_mpp_irq_disable(struct irq_data *d) +{ + struct gpio_chip *gc = irq_data_get_irq_chip_data(d); + + gpiochip_disable_irq(gc, irqd_to_hwirq(d)); +} + +static void pm8xxx_mpp_irq_enable(struct irq_data *d) +{ + struct gpio_chip *gc = irq_data_get_irq_chip_data(d); + + gpiochip_enable_irq(gc, irqd_to_hwirq(d)); +} + +static const struct irq_chip pm8xxx_mpp_irq_chip = { + .name = "ssbi-mpp", + .irq_mask_ack = irq_chip_mask_ack_parent, + .irq_unmask = irq_chip_unmask_parent, + .irq_disable = pm8xxx_mpp_irq_disable, + .irq_enable = pm8xxx_mpp_irq_enable, + .irq_set_type = irq_chip_set_type_parent, + .flags = IRQCHIP_MASK_ON_SUSPEND | IRQCHIP_SKIP_SET_WAKE | + IRQCHIP_IMMUTABLE, + GPIOCHIP_IRQ_RESOURCE_HELPERS, +}; + +static const struct of_device_id pm8xxx_mpp_of_match[] = { + { .compatible = "qcom,pm8018-mpp", .data = (void *) 6 }, + { .compatible = "qcom,pm8038-mpp", .data = (void *) 6 }, + { .compatible = "qcom,pm8058-mpp", .data = (void *) 12 }, + { .compatible = "qcom,pm8821-mpp", .data = (void *) 4 }, + { .compatible = "qcom,pm8917-mpp", .data = (void *) 10 }, + { .compatible = "qcom,pm8921-mpp", .data = (void *) 12 }, + { }, +}; +MODULE_DEVICE_TABLE(of, pm8xxx_mpp_of_match); + +static int pm8xxx_mpp_probe(struct platform_device *pdev) +{ + struct pm8xxx_pin_data *pin_data; + struct irq_domain *parent_domain; + struct device_node *parent_node; + struct pinctrl_pin_desc *pins; + struct gpio_irq_chip *girq; + struct pm8xxx_mpp *pctrl; + int ret; + int i; + + pctrl = devm_kzalloc(&pdev->dev, sizeof(*pctrl), GFP_KERNEL); + if (!pctrl) + return -ENOMEM; + + pctrl->dev = &pdev->dev; + pctrl->npins = (uintptr_t) device_get_match_data(&pdev->dev); + + pctrl->regmap = dev_get_regmap(pdev->dev.parent, NULL); + if (!pctrl->regmap) { + dev_err(&pdev->dev, "parent regmap unavailable\n"); + return -ENXIO; + } + + pctrl->desc = pm8xxx_pinctrl_desc; + pctrl->desc.npins = pctrl->npins; + + pins = devm_kcalloc(&pdev->dev, + pctrl->desc.npins, + sizeof(struct pinctrl_pin_desc), + GFP_KERNEL); + if (!pins) + return -ENOMEM; + + pin_data = devm_kcalloc(&pdev->dev, + pctrl->desc.npins, + sizeof(struct pm8xxx_pin_data), + GFP_KERNEL); + if (!pin_data) + return -ENOMEM; + + for (i = 0; i < pctrl->desc.npins; i++) { + pin_data[i].reg = SSBI_REG_ADDR_MPP(i); + + ret = pm8xxx_pin_populate(pctrl, &pin_data[i]); + if (ret) + return ret; + + pins[i].number = i; + pins[i].name = pm8xxx_groups[i]; + pins[i].drv_data = &pin_data[i]; + } + pctrl->desc.pins = pins; + + pctrl->desc.num_custom_params = ARRAY_SIZE(pm8xxx_mpp_bindings); + pctrl->desc.custom_params = pm8xxx_mpp_bindings; +#ifdef CONFIG_DEBUG_FS + pctrl->desc.custom_conf_items = pm8xxx_conf_items; +#endif + + pctrl->pctrl = devm_pinctrl_register(&pdev->dev, &pctrl->desc, pctrl); + if (IS_ERR(pctrl->pctrl)) { + dev_err(&pdev->dev, "couldn't register pm8xxx mpp driver\n"); + return PTR_ERR(pctrl->pctrl); + } + + pctrl->chip = pm8xxx_mpp_template; + pctrl->chip.base = -1; + pctrl->chip.parent = &pdev->dev; + pctrl->chip.of_gpio_n_cells = 2; + pctrl->chip.label = dev_name(pctrl->dev); + pctrl->chip.ngpio = pctrl->npins; + + parent_node = of_irq_find_parent(pctrl->dev->of_node); + if (!parent_node) + return -ENXIO; + + parent_domain = irq_find_host(parent_node); + of_node_put(parent_node); + if (!parent_domain) + return -ENXIO; + + girq = &pctrl->chip.irq; + gpio_irq_chip_set_chip(girq, &pm8xxx_mpp_irq_chip); + girq->default_type = IRQ_TYPE_NONE; + girq->handler = handle_level_irq; + girq->fwnode = dev_fwnode(pctrl->dev); + girq->parent_domain = parent_domain; + if (of_device_is_compatible(pdev->dev.of_node, "qcom,pm8821-mpp")) + girq->child_to_parent_hwirq = pm8821_mpp_child_to_parent_hwirq; + else + girq->child_to_parent_hwirq = pm8xxx_mpp_child_to_parent_hwirq; + girq->populate_parent_alloc_arg = gpiochip_populate_parent_fwspec_twocell; + girq->child_offset_to_irq = pm8xxx_mpp_child_offset_to_irq; + girq->child_irq_domain_ops.translate = pm8xxx_mpp_domain_translate; + + ret = gpiochip_add_data(&pctrl->chip, pctrl); + if (ret) { + dev_err(&pdev->dev, "failed register gpiochip\n"); + return ret; + } + + ret = gpiochip_add_pin_range(&pctrl->chip, + dev_name(pctrl->dev), + 0, 0, pctrl->chip.ngpio); + if (ret) { + dev_err(pctrl->dev, "failed to add pin range\n"); + goto unregister_gpiochip; + } + + platform_set_drvdata(pdev, pctrl); + + dev_dbg(&pdev->dev, "Qualcomm pm8xxx mpp driver probed\n"); + + return 0; + +unregister_gpiochip: + gpiochip_remove(&pctrl->chip); + + return ret; +} + +static int pm8xxx_mpp_remove(struct platform_device *pdev) +{ + struct pm8xxx_mpp *pctrl = platform_get_drvdata(pdev); + + gpiochip_remove(&pctrl->chip); + + return 0; +} + +static struct platform_driver pm8xxx_mpp_driver = { + .driver = { + .name = "qcom-ssbi-mpp", + .of_match_table = pm8xxx_mpp_of_match, + }, + .probe = pm8xxx_mpp_probe, + .remove = pm8xxx_mpp_remove, +}; + +module_platform_driver(pm8xxx_mpp_driver); + +MODULE_AUTHOR("Bjorn Andersson <bjorn.andersson@sonymobile.com>"); +MODULE_DESCRIPTION("Qualcomm PM8xxx MPP driver"); +MODULE_LICENSE("GPL v2"); |