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authorDaniel Baumann <daniel.baumann@progress-linux.org>2024-05-18 17:39:57 +0000
committerDaniel Baumann <daniel.baumann@progress-linux.org>2024-05-18 17:39:57 +0000
commitdc50eab76b709d68175a358d6e23a5a3890764d3 (patch)
treec754d0390db060af0213ff994f0ac310e4cfd6e9 /drivers/pinctrl
parentAdding debian version 6.6.15-2. (diff)
downloadlinux-dc50eab76b709d68175a358d6e23a5a3890764d3.tar.xz
linux-dc50eab76b709d68175a358d6e23a5a3890764d3.zip
Merging upstream version 6.7.7.
Signed-off-by: Daniel Baumann <daniel.baumann@progress-linux.org>
Diffstat (limited to 'drivers/pinctrl')
-rw-r--r--drivers/pinctrl/Kconfig1
-rw-r--r--drivers/pinctrl/Makefile1
-rw-r--r--drivers/pinctrl/aspeed/pinctrl-aspeed-g4.c19
-rw-r--r--drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c19
-rw-r--r--drivers/pinctrl/aspeed/pinctrl-aspeed-g6.c7
-rw-r--r--drivers/pinctrl/bcm/pinctrl-iproc-gpio.c6
-rw-r--r--drivers/pinctrl/bcm/pinctrl-ns.c8
-rw-r--r--drivers/pinctrl/berlin/berlin-bg2.c8
-rw-r--r--drivers/pinctrl/berlin/berlin-bg2cd.c8
-rw-r--r--drivers/pinctrl/berlin/berlin-bg2q.c8
-rw-r--r--drivers/pinctrl/berlin/berlin-bg4ct.c9
-rw-r--r--drivers/pinctrl/berlin/berlin.c8
-rw-r--r--drivers/pinctrl/berlin/pinctrl-as370.c9
-rw-r--r--drivers/pinctrl/cirrus/pinctrl-cs42l43.c9
-rw-r--r--drivers/pinctrl/cirrus/pinctrl-lochnagar.c2
-rw-r--r--drivers/pinctrl/cirrus/pinctrl-madera-core.c6
-rw-r--r--drivers/pinctrl/core.c139
-rw-r--r--drivers/pinctrl/freescale/pinctrl-mxs.c13
-rw-r--r--drivers/pinctrl/intel/pinctrl-baytrail.c24
-rw-r--r--drivers/pinctrl/intel/pinctrl-broxton.c3
-rw-r--r--drivers/pinctrl/intel/pinctrl-cherryview.c161
-rw-r--r--drivers/pinctrl/intel/pinctrl-denverton.c7
-rw-r--r--drivers/pinctrl/intel/pinctrl-intel.c200
-rw-r--r--drivers/pinctrl/intel/pinctrl-intel.h2
-rw-r--r--drivers/pinctrl/intel/pinctrl-lynxpoint.c38
-rw-r--r--drivers/pinctrl/intel/pinctrl-merrifield.c2
-rw-r--r--drivers/pinctrl/intel/pinctrl-moorefield.c2
-rw-r--r--drivers/pinctrl/mediatek/pinctrl-moore.c18
-rw-r--r--drivers/pinctrl/mediatek/pinctrl-mt7981.c16
-rw-r--r--drivers/pinctrl/mediatek/pinctrl-mtk-common.c10
-rw-r--r--drivers/pinctrl/mediatek/pinctrl-paris.c8
-rw-r--r--drivers/pinctrl/meson/Kconfig6
-rw-r--r--drivers/pinctrl/meson/Makefile1
-rw-r--r--drivers/pinctrl/meson/pinctrl-amlogic-t7.c1611
-rw-r--r--drivers/pinctrl/mvebu/pinctrl-armada-38x.c9
-rw-r--r--drivers/pinctrl/mvebu/pinctrl-armada-39x.c9
-rw-r--r--drivers/pinctrl/mvebu/pinctrl-armada-ap806.c5
-rw-r--r--drivers/pinctrl/mvebu/pinctrl-armada-cp110.c6
-rw-r--r--drivers/pinctrl/mvebu/pinctrl-armada-xp.c9
-rw-r--r--drivers/pinctrl/mvebu/pinctrl-dove.c6
-rw-r--r--drivers/pinctrl/mvebu/pinctrl-kirkwood.c7
-rw-r--r--drivers/pinctrl/mvebu/pinctrl-orion.c7
-rw-r--r--drivers/pinctrl/nomadik/pinctrl-abx500.c14
-rw-r--r--drivers/pinctrl/nomadik/pinctrl-nomadik.c10
-rw-r--r--drivers/pinctrl/nuvoton/Kconfig17
-rw-r--r--drivers/pinctrl/nuvoton/Makefile1
-rw-r--r--drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c29
-rw-r--r--drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c2486
-rw-r--r--drivers/pinctrl/nuvoton/pinctrl-wpcm450.c12
-rw-r--r--drivers/pinctrl/pinconf-generic.c16
-rw-r--r--drivers/pinctrl/pinconf.c14
-rw-r--r--drivers/pinctrl/pinctrl-amd.c6
-rw-r--r--drivers/pinctrl/pinctrl-artpec6.c6
-rw-r--r--drivers/pinctrl/pinctrl-as3722.c14
-rw-r--r--drivers/pinctrl/pinctrl-at91.c11
-rw-r--r--drivers/pinctrl/pinctrl-axp209.c7
-rw-r--r--drivers/pinctrl/pinctrl-cy8c95x0.c9
-rw-r--r--drivers/pinctrl/pinctrl-da9062.c7
-rw-r--r--drivers/pinctrl/pinctrl-ingenic.c19
-rw-r--r--drivers/pinctrl/pinctrl-mcp23s08.h8
-rw-r--r--drivers/pinctrl/pinctrl-mcp23s08_i2c.c93
-rw-r--r--drivers/pinctrl/pinctrl-mcp23s08_spi.c97
-rw-r--r--drivers/pinctrl/pinctrl-ocelot.c10
-rw-r--r--drivers/pinctrl/pinctrl-rk805.c10
-rw-r--r--drivers/pinctrl/pinctrl-rockchip.c6
-rw-r--r--drivers/pinctrl/pinctrl-single.c21
-rw-r--r--drivers/pinctrl/pinctrl-st.c13
-rw-r--r--drivers/pinctrl/pinctrl-stmfx.c16
-rw-r--r--drivers/pinctrl/pinctrl-sx150x.c7
-rw-r--r--drivers/pinctrl/pinctrl-tb10x.c6
-rw-r--r--drivers/pinctrl/pinctrl-utils.c6
-rw-r--r--drivers/pinctrl/pinctrl-xway.c11
-rw-r--r--drivers/pinctrl/pinmux.c6
-rw-r--r--drivers/pinctrl/qcom/pinctrl-apq8064.c2
-rw-r--r--drivers/pinctrl/qcom/pinctrl-apq8084.c2
-rw-r--r--drivers/pinctrl/qcom/pinctrl-ipq4019.c2
-rw-r--r--drivers/pinctrl/qcom/pinctrl-ipq5018.c2
-rw-r--r--drivers/pinctrl/qcom/pinctrl-ipq5332.c2
-rw-r--r--drivers/pinctrl/qcom/pinctrl-ipq6018.c2
-rw-r--r--drivers/pinctrl/qcom/pinctrl-ipq8064.c2
-rw-r--r--drivers/pinctrl/qcom/pinctrl-ipq8074.c2
-rw-r--r--drivers/pinctrl/qcom/pinctrl-ipq9574.c2
-rw-r--r--drivers/pinctrl/qcom/pinctrl-lpass-lpi.c4
-rw-r--r--drivers/pinctrl/qcom/pinctrl-lpass-lpi.h2
-rw-r--r--drivers/pinctrl/qcom/pinctrl-mdm9607.c2
-rw-r--r--drivers/pinctrl/qcom/pinctrl-mdm9615.c2
-rw-r--r--drivers/pinctrl/qcom/pinctrl-msm.c4
-rw-r--r--drivers/pinctrl/qcom/pinctrl-msm.h2
-rw-r--r--drivers/pinctrl/qcom/pinctrl-msm8226.c22
-rw-r--r--drivers/pinctrl/qcom/pinctrl-msm8660.c2
-rw-r--r--drivers/pinctrl/qcom/pinctrl-msm8909.c2
-rw-r--r--drivers/pinctrl/qcom/pinctrl-msm8916.c2
-rw-r--r--drivers/pinctrl/qcom/pinctrl-msm8953.c2
-rw-r--r--drivers/pinctrl/qcom/pinctrl-msm8960.c2
-rw-r--r--drivers/pinctrl/qcom/pinctrl-msm8976.c2
-rw-r--r--drivers/pinctrl/qcom/pinctrl-msm8994.c2
-rw-r--r--drivers/pinctrl/qcom/pinctrl-msm8996.c16
-rw-r--r--drivers/pinctrl/qcom/pinctrl-msm8998.c2
-rw-r--r--drivers/pinctrl/qcom/pinctrl-msm8x74.c14
-rw-r--r--drivers/pinctrl/qcom/pinctrl-qcm2290.c2
-rw-r--r--drivers/pinctrl/qcom/pinctrl-qcs404.c2
-rw-r--r--drivers/pinctrl/qcom/pinctrl-qdf2xxx.c2
-rw-r--r--drivers/pinctrl/qcom/pinctrl-qdu1000.c2
-rw-r--r--drivers/pinctrl/qcom/pinctrl-sa8775p.c2
-rw-r--r--drivers/pinctrl/qcom/pinctrl-sc7180.c2
-rw-r--r--drivers/pinctrl/qcom/pinctrl-sc7280-lpass-lpi.c2
-rw-r--r--drivers/pinctrl/qcom/pinctrl-sc7280.c2
-rw-r--r--drivers/pinctrl/qcom/pinctrl-sc8180x.c2
-rw-r--r--drivers/pinctrl/qcom/pinctrl-sc8280xp-lpass-lpi.c2
-rw-r--r--drivers/pinctrl/qcom/pinctrl-sc8280xp.c2
-rw-r--r--drivers/pinctrl/qcom/pinctrl-sdm660.c16
-rw-r--r--drivers/pinctrl/qcom/pinctrl-sdm670.c2
-rw-r--r--drivers/pinctrl/qcom/pinctrl-sdm845.c2
-rw-r--r--drivers/pinctrl/qcom/pinctrl-sdx55.c2
-rw-r--r--drivers/pinctrl/qcom/pinctrl-sdx65.c2
-rw-r--r--drivers/pinctrl/qcom/pinctrl-sdx75.c2
-rw-r--r--drivers/pinctrl/qcom/pinctrl-sm6115-lpass-lpi.c2
-rw-r--r--drivers/pinctrl/qcom/pinctrl-sm6115.c14
-rw-r--r--drivers/pinctrl/qcom/pinctrl-sm6125.c19
-rw-r--r--drivers/pinctrl/qcom/pinctrl-sm6350.c2
-rw-r--r--drivers/pinctrl/qcom/pinctrl-sm6375.c2
-rw-r--r--drivers/pinctrl/qcom/pinctrl-sm7150.c2
-rw-r--r--drivers/pinctrl/qcom/pinctrl-sm8150.c2
-rw-r--r--drivers/pinctrl/qcom/pinctrl-sm8250-lpass-lpi.c2
-rw-r--r--drivers/pinctrl/qcom/pinctrl-sm8250.c2
-rw-r--r--drivers/pinctrl/qcom/pinctrl-sm8350-lpass-lpi.c2
-rw-r--r--drivers/pinctrl/qcom/pinctrl-sm8350.c2
-rw-r--r--drivers/pinctrl/qcom/pinctrl-sm8450-lpass-lpi.c2
-rw-r--r--drivers/pinctrl/qcom/pinctrl-sm8450.c2
-rw-r--r--drivers/pinctrl/qcom/pinctrl-sm8550-lpass-lpi.c2
-rw-r--r--drivers/pinctrl/qcom/pinctrl-sm8550.c2
-rw-r--r--drivers/pinctrl/qcom/pinctrl-spmi-gpio.c5
-rw-r--r--drivers/pinctrl/qcom/pinctrl-spmi-mpp.c5
-rw-r--r--drivers/pinctrl/qcom/pinctrl-ssbi-gpio.c6
-rw-r--r--drivers/pinctrl/qcom/pinctrl-ssbi-mpp.c6
-rw-r--r--drivers/pinctrl/realtek/Kconfig23
-rw-r--r--drivers/pinctrl/realtek/Makefile6
-rw-r--r--drivers/pinctrl/realtek/pinctrl-rtd.c596
-rw-r--r--drivers/pinctrl/realtek/pinctrl-rtd.h124
-rw-r--r--drivers/pinctrl/realtek/pinctrl-rtd1315e.c1440
-rw-r--r--drivers/pinctrl/realtek/pinctrl-rtd1319d.c1610
-rw-r--r--drivers/pinctrl/realtek/pinctrl-rtd1619b.c1601
-rw-r--r--drivers/pinctrl/renesas/gpio.c8
-rw-r--r--drivers/pinctrl/renesas/pfc-r8a7778.c38
-rw-r--r--drivers/pinctrl/renesas/pfc-r8a7779.c2
-rw-r--r--drivers/pinctrl/renesas/pinctrl-rzg2l.c718
-rw-r--r--drivers/pinctrl/renesas/pinctrl-rzn1.c6
-rw-r--r--drivers/pinctrl/renesas/pinctrl-rzv2m.c4
-rw-r--r--drivers/pinctrl/samsung/pinctrl-exynos.c2
-rw-r--r--drivers/pinctrl/samsung/pinctrl-exynos.h2
-rw-r--r--drivers/pinctrl/samsung/pinctrl-samsung.c56
-rw-r--r--drivers/pinctrl/samsung/pinctrl-samsung.h4
-rw-r--r--drivers/pinctrl/spear/pinctrl-plgpio.c8
-rw-r--r--drivers/pinctrl/sprd/pinctrl-sprd-sc9860.c2
-rw-r--r--drivers/pinctrl/sprd/pinctrl-sprd.c3
-rw-r--r--drivers/pinctrl/sprd/pinctrl-sprd.h2
-rw-r--r--drivers/pinctrl/starfive/pinctrl-starfive-jh7100.c14
-rw-r--r--drivers/pinctrl/starfive/pinctrl-starfive-jh7110.c14
-rw-r--r--drivers/pinctrl/stm32/pinctrl-stm32.c20
-rw-r--r--drivers/pinctrl/sunxi/pinctrl-sun50i-h616.c380
-rw-r--r--drivers/pinctrl/tegra/pinctrl-tegra.c8
-rw-r--r--drivers/pinctrl/ti/pinctrl-ti-iodelay.c29
-rw-r--r--drivers/pinctrl/uniphier/pinctrl-uniphier-core.c2
-rw-r--r--drivers/pinctrl/vt8500/pinctrl-wmt.c9
164 files changed, 11258 insertions, 1139 deletions
diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig
index 7dfb719058..1de4e1eded 100644
--- a/drivers/pinctrl/Kconfig
+++ b/drivers/pinctrl/Kconfig
@@ -520,6 +520,7 @@ source "drivers/pinctrl/nuvoton/Kconfig"
source "drivers/pinctrl/nxp/Kconfig"
source "drivers/pinctrl/pxa/Kconfig"
source "drivers/pinctrl/qcom/Kconfig"
+source "drivers/pinctrl/realtek/Kconfig"
source "drivers/pinctrl/renesas/Kconfig"
source "drivers/pinctrl/samsung/Kconfig"
source "drivers/pinctrl/spear/Kconfig"
diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile
index dd6cda2702..37575deb7a 100644
--- a/drivers/pinctrl/Makefile
+++ b/drivers/pinctrl/Makefile
@@ -66,6 +66,7 @@ obj-y += nuvoton/
obj-y += nxp/
obj-$(CONFIG_PINCTRL_PXA) += pxa/
obj-y += qcom/
+obj-$(CONFIG_ARCH_REALTEK) += realtek/
obj-$(CONFIG_PINCTRL_RENESAS) += renesas/
obj-$(CONFIG_PINCTRL_SAMSUNG) += samsung/
obj-$(CONFIG_PINCTRL_SPEAR) += spear/
diff --git a/drivers/pinctrl/aspeed/pinctrl-aspeed-g4.c b/drivers/pinctrl/aspeed/pinctrl-aspeed-g4.c
index bfed0e2746..774f8d0514 100644
--- a/drivers/pinctrl/aspeed/pinctrl-aspeed-g4.c
+++ b/drivers/pinctrl/aspeed/pinctrl-aspeed-g4.c
@@ -2563,15 +2563,20 @@ static int aspeed_g4_sig_expr_set(struct aspeed_pinmux_data *ctx,
* deconfigured and is the reason we re-evaluate after writing
* all descriptor bits.
*
- * Port D and port E GPIO loopback modes are the only exception
- * as those are commonly used with front-panel buttons to allow
- * normal operation of the host when the BMC is powered off or
- * fails to boot. Once the BMC has booted, the loopback mode
- * must be disabled for the BMC to control host power-on and
- * reset.
+ * We make two exceptions to the read-only rule:
+ *
+ * - The passthrough mode of GPIO ports D and E are commonly
+ * used with front-panel buttons to allow normal operation
+ * of the host if the BMC is powered off or fails to boot.
+ * Once the BMC has booted, the loopback mode must be
+ * disabled for the BMC to control host power-on and reset.
+ *
+ * - The operating mode of the SPI1 interface is simply
+ * strapped incorrectly on some systems and requires a
+ * software fixup, which we allow to be done via pinctrl.
*/
if (desc->ip == ASPEED_IP_SCU && desc->reg == HW_STRAP1 &&
- !(desc->mask & (BIT(21) | BIT(22))))
+ !(desc->mask & (BIT(22) | BIT(21) | BIT(13) | BIT(12))))
continue;
if (desc->ip == ASPEED_IP_SCU && desc->reg == HW_STRAP2)
diff --git a/drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c b/drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c
index 4c0d26606b..5bb8fd0d1e 100644
--- a/drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c
+++ b/drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c
@@ -2742,15 +2742,20 @@ static int aspeed_g5_sig_expr_set(struct aspeed_pinmux_data *ctx,
* deconfigured and is the reason we re-evaluate after writing
* all descriptor bits.
*
- * Port D and port E GPIO loopback modes are the only exception
- * as those are commonly used with front-panel buttons to allow
- * normal operation of the host when the BMC is powered off or
- * fails to boot. Once the BMC has booted, the loopback mode
- * must be disabled for the BMC to control host power-on and
- * reset.
+ * We make two exceptions to the read-only rule:
+ *
+ * - The passthrough mode of GPIO ports D and E are commonly
+ * used with front-panel buttons to allow normal operation
+ * of the host if the BMC is powered off or fails to boot.
+ * Once the BMC has booted, the loopback mode must be
+ * disabled for the BMC to control host power-on and reset.
+ *
+ * - The operating mode of the SPI1 interface is simply
+ * strapped incorrectly on some systems and requires a
+ * software fixup, which we allow to be done via pinctrl.
*/
if (desc->ip == ASPEED_IP_SCU && desc->reg == HW_STRAP1 &&
- !(desc->mask & (BIT(21) | BIT(22))))
+ !(desc->mask & (BIT(22) | BIT(21) | BIT(13) | BIT(12))))
continue;
if (desc->ip == ASPEED_IP_SCU && desc->reg == HW_STRAP2)
diff --git a/drivers/pinctrl/aspeed/pinctrl-aspeed-g6.c b/drivers/pinctrl/aspeed/pinctrl-aspeed-g6.c
index 80838dc54b..d376fa7114 100644
--- a/drivers/pinctrl/aspeed/pinctrl-aspeed-g6.c
+++ b/drivers/pinctrl/aspeed/pinctrl-aspeed-g6.c
@@ -1592,9 +1592,10 @@ SIG_EXPR_LIST_DECL_SEMG(A4, USB2ADPDP, USBA, USB2ADP, USB2ADP_DESC,
SIG_DESC_SET(SCUC20, 16));
SIG_EXPR_LIST_DECL_SEMG(A4, USB2ADDP, USBA, USB2AD, USB2AD_DESC);
SIG_EXPR_LIST_DECL_SEMG(A4, USB2AHDP, USBA, USB2AH, USB2AH_DESC);
-SIG_EXPR_LIST_DECL_SEMG(A4, USB2AHPDP, USBA, USB2AHP, USB2AHP_DESC);
+SIG_EXPR_LIST_DECL_SEMG(A4, USB2AHPDP, USBA, USB2AHP, USB2AHP_DESC,
+ SIG_DESC_SET(SCUC20, 16));
PIN_DECL_(A4, SIG_EXPR_LIST_PTR(A4, USB2ADPDP), SIG_EXPR_LIST_PTR(A4, USB2ADDP),
- SIG_EXPR_LIST_PTR(A4, USB2AHDP));
+ SIG_EXPR_LIST_PTR(A4, USB2AHDP), SIG_EXPR_LIST_PTR(A4, USB2AHPDP));
#define B4 253
SIG_EXPR_LIST_DECL_SEMG(B4, USB2ADPDN, USBA, USB2ADP, USB2ADP_DESC);
@@ -1602,7 +1603,7 @@ SIG_EXPR_LIST_DECL_SEMG(B4, USB2ADDN, USBA, USB2AD, USB2AD_DESC);
SIG_EXPR_LIST_DECL_SEMG(B4, USB2AHDN, USBA, USB2AH, USB2AH_DESC);
SIG_EXPR_LIST_DECL_SEMG(B4, USB2AHPDN, USBA, USB2AHP, USB2AHP_DESC);
PIN_DECL_(B4, SIG_EXPR_LIST_PTR(B4, USB2ADPDN), SIG_EXPR_LIST_PTR(B4, USB2ADDN),
- SIG_EXPR_LIST_PTR(B4, USB2AHDN));
+ SIG_EXPR_LIST_PTR(B4, USB2AHDN), SIG_EXPR_LIST_PTR(B4, USB2AHPDN));
GROUP_DECL(USBA, A4, B4);
diff --git a/drivers/pinctrl/bcm/pinctrl-iproc-gpio.c b/drivers/pinctrl/bcm/pinctrl-iproc-gpio.c
index bc7bb9876e..fd5ce52d05 100644
--- a/drivers/pinctrl/bcm/pinctrl-iproc-gpio.c
+++ b/drivers/pinctrl/bcm/pinctrl-iproc-gpio.c
@@ -330,24 +330,22 @@ static const struct irq_chip iproc_gpio_irq_chip = {
static int iproc_gpio_request(struct gpio_chip *gc, unsigned offset)
{
struct iproc_gpio *chip = gpiochip_get_data(gc);
- unsigned gpio = gc->base + offset;
/* not all Iproc GPIO pins can be muxed individually */
if (!chip->pinmux_is_supported)
return 0;
- return pinctrl_gpio_request(gpio);
+ return pinctrl_gpio_request(gc, offset);
}
static void iproc_gpio_free(struct gpio_chip *gc, unsigned offset)
{
struct iproc_gpio *chip = gpiochip_get_data(gc);
- unsigned gpio = gc->base + offset;
if (!chip->pinmux_is_supported)
return;
- pinctrl_gpio_free(gpio);
+ pinctrl_gpio_free(gc, offset);
}
static int iproc_gpio_direction_input(struct gpio_chip *gc, unsigned gpio)
diff --git a/drivers/pinctrl/bcm/pinctrl-ns.c b/drivers/pinctrl/bcm/pinctrl-ns.c
index f80630a74d..d099a7f25f 100644
--- a/drivers/pinctrl/bcm/pinctrl-ns.c
+++ b/drivers/pinctrl/bcm/pinctrl-ns.c
@@ -7,11 +7,11 @@
#include <linux/io.h>
#include <linux/module.h>
#include <linux/of.h>
-#include <linux/of_device.h>
#include <linux/pinctrl/pinconf-generic.h>
#include <linux/pinctrl/pinctrl.h>
#include <linux/pinctrl/pinmux.h>
#include <linux/platform_device.h>
+#include <linux/property.h>
#include <linux/slab.h>
#include "../core.h"
@@ -208,7 +208,6 @@ static const struct of_device_id ns_pinctrl_of_match_table[] = {
static int ns_pinctrl_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
- const struct of_device_id *of_id;
struct ns_pinctrl *ns_pinctrl;
struct pinctrl_desc *pctldesc;
struct pinctrl_pin_desc *pin;
@@ -225,10 +224,7 @@ static int ns_pinctrl_probe(struct platform_device *pdev)
ns_pinctrl->dev = dev;
- of_id = of_match_device(ns_pinctrl_of_match_table, dev);
- if (!of_id)
- return -EINVAL;
- ns_pinctrl->chipset_flag = (uintptr_t)of_id->data;
+ ns_pinctrl->chipset_flag = (uintptr_t)device_get_match_data(dev);
res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
"cru_gpio_control");
diff --git a/drivers/pinctrl/berlin/berlin-bg2.c b/drivers/pinctrl/berlin/berlin-bg2.c
index acbd413340..15aed44676 100644
--- a/drivers/pinctrl/berlin/berlin-bg2.c
+++ b/drivers/pinctrl/berlin/berlin-bg2.c
@@ -8,8 +8,9 @@
*/
#include <linux/init.h>
-#include <linux/of_device.h>
+#include <linux/of.h>
#include <linux/platform_device.h>
+#include <linux/property.h>
#include <linux/regmap.h>
#include "berlin.h"
@@ -227,10 +228,7 @@ static const struct of_device_id berlin2_pinctrl_match[] = {
static int berlin2_pinctrl_probe(struct platform_device *pdev)
{
- const struct of_device_id *match =
- of_match_device(berlin2_pinctrl_match, &pdev->dev);
-
- return berlin_pinctrl_probe(pdev, match->data);
+ return berlin_pinctrl_probe(pdev, device_get_match_data(&pdev->dev));
}
static struct platform_driver berlin2_pinctrl_driver = {
diff --git a/drivers/pinctrl/berlin/berlin-bg2cd.c b/drivers/pinctrl/berlin/berlin-bg2cd.c
index c0f5d86d5d..73a1d8c230 100644
--- a/drivers/pinctrl/berlin/berlin-bg2cd.c
+++ b/drivers/pinctrl/berlin/berlin-bg2cd.c
@@ -8,8 +8,9 @@
*/
#include <linux/init.h>
-#include <linux/of_device.h>
+#include <linux/of.h>
#include <linux/platform_device.h>
+#include <linux/property.h>
#include <linux/regmap.h>
#include "berlin.h"
@@ -172,10 +173,7 @@ static const struct of_device_id berlin2cd_pinctrl_match[] = {
static int berlin2cd_pinctrl_probe(struct platform_device *pdev)
{
- const struct of_device_id *match =
- of_match_device(berlin2cd_pinctrl_match, &pdev->dev);
-
- return berlin_pinctrl_probe(pdev, match->data);
+ return berlin_pinctrl_probe(pdev, device_get_match_data(&pdev->dev));
}
static struct platform_driver berlin2cd_pinctrl_driver = {
diff --git a/drivers/pinctrl/berlin/berlin-bg2q.c b/drivers/pinctrl/berlin/berlin-bg2q.c
index 20a3216ede..a5dbc8f279 100644
--- a/drivers/pinctrl/berlin/berlin-bg2q.c
+++ b/drivers/pinctrl/berlin/berlin-bg2q.c
@@ -8,8 +8,9 @@
*/
#include <linux/init.h>
-#include <linux/of_device.h>
+#include <linux/of.h>
#include <linux/platform_device.h>
+#include <linux/property.h>
#include <linux/regmap.h>
#include "berlin.h"
@@ -389,10 +390,7 @@ static const struct of_device_id berlin2q_pinctrl_match[] = {
static int berlin2q_pinctrl_probe(struct platform_device *pdev)
{
- const struct of_device_id *match =
- of_match_device(berlin2q_pinctrl_match, &pdev->dev);
-
- return berlin_pinctrl_probe(pdev, match->data);
+ return berlin_pinctrl_probe(pdev, device_get_match_data(&pdev->dev));
}
static struct platform_driver berlin2q_pinctrl_driver = {
diff --git a/drivers/pinctrl/berlin/berlin-bg4ct.c b/drivers/pinctrl/berlin/berlin-bg4ct.c
index 3026a3b3da..9bf0a54f27 100644
--- a/drivers/pinctrl/berlin/berlin-bg4ct.c
+++ b/drivers/pinctrl/berlin/berlin-bg4ct.c
@@ -8,8 +8,9 @@
*/
#include <linux/init.h>
-#include <linux/of_device.h>
+#include <linux/of.h>
#include <linux/platform_device.h>
+#include <linux/property.h>
#include <linux/regmap.h>
#include "berlin.h"
@@ -449,8 +450,8 @@ static const struct of_device_id berlin4ct_pinctrl_match[] = {
static int berlin4ct_pinctrl_probe(struct platform_device *pdev)
{
- const struct of_device_id *match =
- of_match_device(berlin4ct_pinctrl_match, &pdev->dev);
+ const struct berlin_pinctrl_desc *desc =
+ device_get_match_data(&pdev->dev);
struct regmap_config *rmconfig;
struct regmap *regmap;
struct resource *res;
@@ -473,7 +474,7 @@ static int berlin4ct_pinctrl_probe(struct platform_device *pdev)
if (IS_ERR(regmap))
return PTR_ERR(regmap);
- return berlin_pinctrl_probe_regmap(pdev, match->data, regmap);
+ return berlin_pinctrl_probe_regmap(pdev, desc, regmap);
}
static struct platform_driver berlin4ct_pinctrl_driver = {
diff --git a/drivers/pinctrl/berlin/berlin.c b/drivers/pinctrl/berlin/berlin.c
index 1e427ea4d3..9550cc8095 100644
--- a/drivers/pinctrl/berlin/berlin.c
+++ b/drivers/pinctrl/berlin/berlin.c
@@ -96,10 +96,10 @@ static int berlin_pinctrl_dt_node_to_map(struct pinctrl_dev *pctrl_dev,
}
static const struct pinctrl_ops berlin_pinctrl_ops = {
- .get_groups_count = &berlin_pinctrl_get_group_count,
- .get_group_name = &berlin_pinctrl_get_group_name,
- .dt_node_to_map = &berlin_pinctrl_dt_node_to_map,
- .dt_free_map = &pinctrl_utils_free_map,
+ .get_groups_count = berlin_pinctrl_get_group_count,
+ .get_group_name = berlin_pinctrl_get_group_name,
+ .dt_node_to_map = berlin_pinctrl_dt_node_to_map,
+ .dt_free_map = pinctrl_utils_free_map,
};
static int berlin_pinmux_get_functions_count(struct pinctrl_dev *pctrl_dev)
diff --git a/drivers/pinctrl/berlin/pinctrl-as370.c b/drivers/pinctrl/berlin/pinctrl-as370.c
index b631c14813..fc0daec94e 100644
--- a/drivers/pinctrl/berlin/pinctrl-as370.c
+++ b/drivers/pinctrl/berlin/pinctrl-as370.c
@@ -8,8 +8,9 @@
*/
#include <linux/init.h>
-#include <linux/of_device.h>
+#include <linux/of.h>
#include <linux/platform_device.h>
+#include <linux/property.h>
#include <linux/regmap.h>
#include "berlin.h"
@@ -330,8 +331,8 @@ static const struct of_device_id as370_pinctrl_match[] = {
static int as370_pinctrl_probe(struct platform_device *pdev)
{
- const struct of_device_id *match =
- of_match_device(as370_pinctrl_match, &pdev->dev);
+ const struct berlin_pinctrl_desc *desc =
+ device_get_match_data(&pdev->dev);
struct regmap_config *rmconfig;
struct regmap *regmap;
struct resource *res;
@@ -354,7 +355,7 @@ static int as370_pinctrl_probe(struct platform_device *pdev)
if (IS_ERR(regmap))
return PTR_ERR(regmap);
- return berlin_pinctrl_probe_regmap(pdev, match->data, regmap);
+ return berlin_pinctrl_probe_regmap(pdev, desc, regmap);
}
static struct platform_driver as370_pinctrl_driver = {
diff --git a/drivers/pinctrl/cirrus/pinctrl-cs42l43.c b/drivers/pinctrl/cirrus/pinctrl-cs42l43.c
index c096463184..012b0a3bad 100644
--- a/drivers/pinctrl/cirrus/pinctrl-cs42l43.c
+++ b/drivers/pinctrl/cirrus/pinctrl-cs42l43.c
@@ -506,17 +506,12 @@ static void cs42l43_gpio_set(struct gpio_chip *chip, unsigned int offset, int va
pm_runtime_put(priv->dev);
}
-static int cs42l43_gpio_direction_in(struct gpio_chip *chip, unsigned int offset)
-{
- return pinctrl_gpio_direction_input(chip->base + offset);
-}
-
static int cs42l43_gpio_direction_out(struct gpio_chip *chip,
unsigned int offset, int value)
{
cs42l43_gpio_set(chip, offset, value);
- return pinctrl_gpio_direction_output(chip->base + offset);
+ return pinctrl_gpio_direction_output(chip, offset);
}
static int cs42l43_gpio_add_pin_ranges(struct gpio_chip *chip)
@@ -551,7 +546,7 @@ static int cs42l43_pin_probe(struct platform_device *pdev)
priv->gpio_chip.request = gpiochip_generic_request;
priv->gpio_chip.free = gpiochip_generic_free;
- priv->gpio_chip.direction_input = cs42l43_gpio_direction_in;
+ priv->gpio_chip.direction_input = pinctrl_gpio_direction_input;
priv->gpio_chip.direction_output = cs42l43_gpio_direction_out;
priv->gpio_chip.add_pin_ranges = cs42l43_gpio_add_pin_ranges;
priv->gpio_chip.get = cs42l43_gpio_get;
diff --git a/drivers/pinctrl/cirrus/pinctrl-lochnagar.c b/drivers/pinctrl/cirrus/pinctrl-lochnagar.c
index 0b78cf611a..014297a3fb 100644
--- a/drivers/pinctrl/cirrus/pinctrl-lochnagar.c
+++ b/drivers/pinctrl/cirrus/pinctrl-lochnagar.c
@@ -1098,7 +1098,7 @@ static int lochnagar_gpio_direction_out(struct gpio_chip *chip,
{
lochnagar_gpio_set(chip, offset, value);
- return pinctrl_gpio_direction_output(chip->base + offset);
+ return pinctrl_gpio_direction_output(chip, offset);
}
static int lochnagar_fill_func_groups(struct lochnagar_pin_priv *priv)
diff --git a/drivers/pinctrl/cirrus/pinctrl-madera-core.c b/drivers/pinctrl/cirrus/pinctrl-madera-core.c
index bb589922d8..898b197c37 100644
--- a/drivers/pinctrl/cirrus/pinctrl-madera-core.c
+++ b/drivers/pinctrl/cirrus/pinctrl-madera-core.c
@@ -1084,19 +1084,17 @@ static int madera_pin_probe(struct platform_device *pdev)
return 0;
}
-static int madera_pin_remove(struct platform_device *pdev)
+static void madera_pin_remove(struct platform_device *pdev)
{
struct madera_pin_private *priv = platform_get_drvdata(pdev);
if (priv->madera->pdata.gpio_configs)
pinctrl_unregister_mappings(priv->madera->pdata.gpio_configs);
-
- return 0;
}
static struct platform_driver madera_pin_driver = {
.probe = madera_pin_probe,
- .remove = madera_pin_remove,
+ .remove_new = madera_pin_remove,
.driver = {
.name = "madera-pinctrl",
},
diff --git a/drivers/pinctrl/core.c b/drivers/pinctrl/core.c
index 184ec92241..f2977eb655 100644
--- a/drivers/pinctrl/core.c
+++ b/drivers/pinctrl/core.c
@@ -12,17 +12,19 @@
*/
#define pr_fmt(fmt) "pinctrl core: " fmt
+#include <linux/array_size.h>
#include <linux/debugfs.h>
#include <linux/device.h>
#include <linux/err.h>
#include <linux/export.h>
#include <linux/init.h>
-#include <linux/kernel.h>
#include <linux/kref.h>
#include <linux/list.h>
#include <linux/seq_file.h>
#include <linux/slab.h>
+#include <linux/gpio/driver.h>
+
#include <linux/pinctrl/consumer.h>
#include <linux/pinctrl/devinfo.h>
#include <linux/pinctrl/machine.h>
@@ -267,7 +269,8 @@ static int pinctrl_register_pins(struct pinctrl_dev *pctldev,
/**
* gpio_to_pin() - GPIO range GPIO number to pin number translation
* @range: GPIO range used for the translation
- * @gpio: gpio pin to translate to a pin number
+ * @gc: GPIO chip structure from the GPIO subsystem
+ * @offset: hardware offset of the GPIO relative to the controller
*
* Finds the pin number for a given GPIO using the specified GPIO range
* as a base for translation. The distinction between linear GPIO ranges
@@ -278,25 +281,27 @@ static int pinctrl_register_pins(struct pinctrl_dev *pctldev,
* result of successful pinctrl_get_device_gpio_range calls)!
*/
static inline int gpio_to_pin(struct pinctrl_gpio_range *range,
- unsigned int gpio)
+ struct gpio_chip *gc, unsigned int offset)
{
- unsigned int offset = gpio - range->base;
+ unsigned int pin = gc->base + offset - range->base;
if (range->pins)
- return range->pins[offset];
+ return range->pins[pin];
else
- return range->pin_base + offset;
+ return range->pin_base + pin;
}
/**
* pinctrl_match_gpio_range() - check if a certain GPIO pin is in range
* @pctldev: pin controller device to check
- * @gpio: gpio pin to check taken from the global GPIO pin space
+ * @gc: GPIO chip structure from the GPIO subsystem
+ * @offset: hardware offset of the GPIO relative to the controller
*
* Tries to match a GPIO pin number to the ranges handled by a certain pin
* controller, return the range or NULL
*/
static struct pinctrl_gpio_range *
-pinctrl_match_gpio_range(struct pinctrl_dev *pctldev, unsigned gpio)
+pinctrl_match_gpio_range(struct pinctrl_dev *pctldev, struct gpio_chip *gc,
+ unsigned int offset)
{
struct pinctrl_gpio_range *range;
@@ -304,8 +309,8 @@ pinctrl_match_gpio_range(struct pinctrl_dev *pctldev, unsigned gpio)
/* Loop over the ranges */
list_for_each_entry(range, &pctldev->gpio_ranges, node) {
/* Check if we're in the valid range */
- if (gpio >= range->base &&
- gpio < range->base + range->npins) {
+ if ((gc->base + offset) >= range->base &&
+ (gc->base + offset) < range->base + range->npins) {
mutex_unlock(&pctldev->mutex);
return range;
}
@@ -317,7 +322,8 @@ pinctrl_match_gpio_range(struct pinctrl_dev *pctldev, unsigned gpio)
/**
* pinctrl_ready_for_gpio_range() - check if other GPIO pins of
* the same GPIO chip are in range
- * @gpio: gpio pin to check taken from the global GPIO pin space
+ * @gc: GPIO chip structure from the GPIO subsystem
+ * @offset: hardware offset of the GPIO relative to the controller
*
* This function is complement of pinctrl_match_gpio_range(). If the return
* value of pinctrl_match_gpio_range() is NULL, this function could be used
@@ -328,19 +334,11 @@ pinctrl_match_gpio_range(struct pinctrl_dev *pctldev, unsigned gpio)
* is false, it means that pinctrl device may not be ready.
*/
#ifdef CONFIG_GPIOLIB
-static bool pinctrl_ready_for_gpio_range(unsigned gpio)
+static bool pinctrl_ready_for_gpio_range(struct gpio_chip *gc,
+ unsigned int offset)
{
struct pinctrl_dev *pctldev;
struct pinctrl_gpio_range *range = NULL;
- /*
- * FIXME: "gpio" here is a number in the global GPIO numberspace.
- * get rid of this from the ranges eventually and get the GPIO
- * descriptor from the gpio_chip.
- */
- struct gpio_chip *chip = gpiod_to_chip(gpio_to_desc(gpio));
-
- if (WARN(!chip, "no gpio_chip for gpio%i?", gpio))
- return false;
mutex_lock(&pinctrldev_list_mutex);
@@ -350,8 +348,8 @@ static bool pinctrl_ready_for_gpio_range(unsigned gpio)
mutex_lock(&pctldev->mutex);
list_for_each_entry(range, &pctldev->gpio_ranges, node) {
/* Check if any gpio range overlapped with gpio chip */
- if (range->base + range->npins - 1 < chip->base ||
- range->base > chip->base + chip->ngpio - 1)
+ if (range->base + range->npins - 1 < gc->base ||
+ range->base > gc->base + gc->ngpio - 1)
continue;
mutex_unlock(&pctldev->mutex);
mutex_unlock(&pinctrldev_list_mutex);
@@ -365,12 +363,17 @@ static bool pinctrl_ready_for_gpio_range(unsigned gpio)
return false;
}
#else
-static bool pinctrl_ready_for_gpio_range(unsigned gpio) { return true; }
+static inline bool
+pinctrl_ready_for_gpio_range(struct gpio_chip *gc, unsigned int offset)
+{
+ return true;
+}
#endif
/**
* pinctrl_get_device_gpio_range() - find device for GPIO range
- * @gpio: the pin to locate the pin controller for
+ * @gc: GPIO chip structure from the GPIO subsystem
+ * @offset: hardware offset of the GPIO relative to the controller
* @outdev: the pin control device if found
* @outrange: the GPIO range if found
*
@@ -379,7 +382,8 @@ static bool pinctrl_ready_for_gpio_range(unsigned gpio) { return true; }
* -EPROBE_DEFER if the GPIO range could not be found in any device since it
* may still have not been registered.
*/
-static int pinctrl_get_device_gpio_range(unsigned gpio,
+static int pinctrl_get_device_gpio_range(struct gpio_chip *gc,
+ unsigned int offset,
struct pinctrl_dev **outdev,
struct pinctrl_gpio_range **outrange)
{
@@ -391,7 +395,7 @@ static int pinctrl_get_device_gpio_range(unsigned gpio,
list_for_each_entry(pctldev, &pinctrldev_list, node) {
struct pinctrl_gpio_range *range;
- range = pinctrl_match_gpio_range(pctldev, gpio);
+ range = pinctrl_match_gpio_range(pctldev, gc, offset);
if (range) {
*outdev = pctldev;
*outrange = range;
@@ -445,9 +449,9 @@ struct pinctrl_dev *pinctrl_find_and_add_gpio_range(const char *devname,
* it has not probed yet, so the driver trying to register this
* range need to defer probing.
*/
- if (!pctldev) {
+ if (!pctldev)
return ERR_PTR(-EPROBE_DEFER);
- }
+
pinctrl_add_gpio_range(pctldev, range);
return pctldev;
@@ -753,7 +757,7 @@ int pinctrl_get_group_selector(struct pinctrl_dev *pctldev,
return -EINVAL;
}
-bool pinctrl_gpio_can_use_line(unsigned gpio)
+bool pinctrl_gpio_can_use_line(struct gpio_chip *gc, unsigned int offset)
{
struct pinctrl_dev *pctldev;
struct pinctrl_gpio_range *range;
@@ -765,13 +769,13 @@ bool pinctrl_gpio_can_use_line(unsigned gpio)
* we're probably dealing with GPIO driver
* without a backing pin controller - bail out.
*/
- if (pinctrl_get_device_gpio_range(gpio, &pctldev, &range))
+ if (pinctrl_get_device_gpio_range(gc, offset, &pctldev, &range))
return true;
mutex_lock(&pctldev->mutex);
/* Convert to the pin controllers number space */
- pin = gpio_to_pin(range, gpio);
+ pin = gpio_to_pin(range, gc, offset);
result = pinmux_can_be_used_for_gpio(pctldev, pin);
@@ -783,22 +787,22 @@ EXPORT_SYMBOL_GPL(pinctrl_gpio_can_use_line);
/**
* pinctrl_gpio_request() - request a single pin to be used as GPIO
- * @gpio: the GPIO pin number from the GPIO subsystem number space
+ * @gc: GPIO chip structure from the GPIO subsystem
+ * @offset: hardware offset of the GPIO relative to the controller
*
* This function should *ONLY* be used from gpiolib-based GPIO drivers,
* as part of their gpio_request() semantics, platforms and individual drivers
* shall *NOT* request GPIO pins to be muxed in.
*/
-int pinctrl_gpio_request(unsigned gpio)
+int pinctrl_gpio_request(struct gpio_chip *gc, unsigned int offset)
{
- struct pinctrl_dev *pctldev;
struct pinctrl_gpio_range *range;
- int ret;
- int pin;
+ struct pinctrl_dev *pctldev;
+ int ret, pin;
- ret = pinctrl_get_device_gpio_range(gpio, &pctldev, &range);
+ ret = pinctrl_get_device_gpio_range(gc, offset, &pctldev, &range);
if (ret) {
- if (pinctrl_ready_for_gpio_range(gpio))
+ if (pinctrl_ready_for_gpio_range(gc, offset))
ret = 0;
return ret;
}
@@ -806,9 +810,9 @@ int pinctrl_gpio_request(unsigned gpio)
mutex_lock(&pctldev->mutex);
/* Convert to the pin controllers number space */
- pin = gpio_to_pin(range, gpio);
+ pin = gpio_to_pin(range, gc, offset);
- ret = pinmux_request_gpio(pctldev, range, pin, gpio);
+ ret = pinmux_request_gpio(pctldev, range, pin, gc->base + offset);
mutex_unlock(&pctldev->mutex);
@@ -818,27 +822,27 @@ EXPORT_SYMBOL_GPL(pinctrl_gpio_request);
/**
* pinctrl_gpio_free() - free control on a single pin, currently used as GPIO
- * @gpio: the GPIO pin number from the GPIO subsystem number space
+ * @gc: GPIO chip structure from the GPIO subsystem
+ * @offset: hardware offset of the GPIO relative to the controller
*
* This function should *ONLY* be used from gpiolib-based GPIO drivers,
- * as part of their gpio_free() semantics, platforms and individual drivers
- * shall *NOT* request GPIO pins to be muxed out.
+ * as part of their gpio_request() semantics, platforms and individual drivers
+ * shall *NOT* request GPIO pins to be muxed in.
*/
-void pinctrl_gpio_free(unsigned gpio)
+void pinctrl_gpio_free(struct gpio_chip *gc, unsigned int offset)
{
- struct pinctrl_dev *pctldev;
struct pinctrl_gpio_range *range;
- int ret;
- int pin;
+ struct pinctrl_dev *pctldev;
+ int ret, pin;
- ret = pinctrl_get_device_gpio_range(gpio, &pctldev, &range);
- if (ret) {
+ ret = pinctrl_get_device_gpio_range(gc, offset, &pctldev, &range);
+ if (ret)
return;
- }
+
mutex_lock(&pctldev->mutex);
/* Convert to the pin controllers number space */
- pin = gpio_to_pin(range, gpio);
+ pin = gpio_to_pin(range, gc, offset);
pinmux_free_gpio(pctldev, pin, range);
@@ -846,14 +850,15 @@ void pinctrl_gpio_free(unsigned gpio)
}
EXPORT_SYMBOL_GPL(pinctrl_gpio_free);
-static int pinctrl_gpio_direction(unsigned gpio, bool input)
+static int pinctrl_gpio_direction(struct gpio_chip *gc, unsigned int offset,
+ bool input)
{
struct pinctrl_dev *pctldev;
struct pinctrl_gpio_range *range;
int ret;
int pin;
- ret = pinctrl_get_device_gpio_range(gpio, &pctldev, &range);
+ ret = pinctrl_get_device_gpio_range(gc, offset, &pctldev, &range);
if (ret) {
return ret;
}
@@ -861,7 +866,7 @@ static int pinctrl_gpio_direction(unsigned gpio, bool input)
mutex_lock(&pctldev->mutex);
/* Convert to the pin controllers number space */
- pin = gpio_to_pin(range, gpio);
+ pin = gpio_to_pin(range, gc, offset);
ret = pinmux_gpio_direction(pctldev, range, pin, input);
mutex_unlock(&pctldev->mutex);
@@ -871,54 +876,58 @@ static int pinctrl_gpio_direction(unsigned gpio, bool input)
/**
* pinctrl_gpio_direction_input() - request a GPIO pin to go into input mode
- * @gpio: the GPIO pin number from the GPIO subsystem number space
+ * @gc: GPIO chip structure from the GPIO subsystem
+ * @offset: hardware offset of the GPIO relative to the controller
*
* This function should *ONLY* be used from gpiolib-based GPIO drivers,
* as part of their gpio_direction_input() semantics, platforms and individual
* drivers shall *NOT* touch pin control GPIO calls.
*/
-int pinctrl_gpio_direction_input(unsigned gpio)
+int pinctrl_gpio_direction_input(struct gpio_chip *gc, unsigned int offset)
{
- return pinctrl_gpio_direction(gpio, true);
+ return pinctrl_gpio_direction(gc, offset, true);
}
EXPORT_SYMBOL_GPL(pinctrl_gpio_direction_input);
/**
* pinctrl_gpio_direction_output() - request a GPIO pin to go into output mode
- * @gpio: the GPIO pin number from the GPIO subsystem number space
+ * @gc: GPIO chip structure from the GPIO subsystem
+ * @offset: hardware offset of the GPIO relative to the controller
*
* This function should *ONLY* be used from gpiolib-based GPIO drivers,
* as part of their gpio_direction_output() semantics, platforms and individual
* drivers shall *NOT* touch pin control GPIO calls.
*/
-int pinctrl_gpio_direction_output(unsigned gpio)
+int pinctrl_gpio_direction_output(struct gpio_chip *gc, unsigned int offset)
{
- return pinctrl_gpio_direction(gpio, false);
+ return pinctrl_gpio_direction(gc, offset, false);
}
EXPORT_SYMBOL_GPL(pinctrl_gpio_direction_output);
/**
* pinctrl_gpio_set_config() - Apply config to given GPIO pin
- * @gpio: the GPIO pin number from the GPIO subsystem number space
+ * @gc: GPIO chip structure from the GPIO subsystem
+ * @offset: hardware offset of the GPIO relative to the controller
* @config: the configuration to apply to the GPIO
*
* This function should *ONLY* be used from gpiolib-based GPIO drivers, if
* they need to call the underlying pin controller to change GPIO config
* (for example set debounce time).
*/
-int pinctrl_gpio_set_config(unsigned gpio, unsigned long config)
+int pinctrl_gpio_set_config(struct gpio_chip *gc, unsigned int offset,
+ unsigned long config)
{
unsigned long configs[] = { config };
struct pinctrl_gpio_range *range;
struct pinctrl_dev *pctldev;
int ret, pin;
- ret = pinctrl_get_device_gpio_range(gpio, &pctldev, &range);
+ ret = pinctrl_get_device_gpio_range(gc, offset, &pctldev, &range);
if (ret)
return ret;
mutex_lock(&pctldev->mutex);
- pin = gpio_to_pin(range, gpio);
+ pin = gpio_to_pin(range, gc, offset);
ret = pinconf_set_config(pctldev, pin, configs, ARRAY_SIZE(configs));
mutex_unlock(&pctldev->mutex);
diff --git a/drivers/pinctrl/freescale/pinctrl-mxs.c b/drivers/pinctrl/freescale/pinctrl-mxs.c
index cf3f4d2e0c..e77311f262 100644
--- a/drivers/pinctrl/freescale/pinctrl-mxs.c
+++ b/drivers/pinctrl/freescale/pinctrl-mxs.c
@@ -395,6 +395,12 @@ static int mxs_pinctrl_parse_group(struct platform_device *pdev,
return 0;
}
+static bool is_mxs_gpio(struct device_node *child)
+{
+ return of_device_is_compatible(child, "fsl,imx23-gpio") ||
+ of_device_is_compatible(child, "fsl,imx28-gpio");
+}
+
static int mxs_pinctrl_probe_dt(struct platform_device *pdev,
struct mxs_pinctrl_data *d)
{
@@ -402,7 +408,6 @@ static int mxs_pinctrl_probe_dt(struct platform_device *pdev,
struct device_node *np = pdev->dev.of_node;
struct device_node *child;
struct mxs_function *f;
- const char *gpio_compat = "fsl,mxs-gpio";
const char *fn, *fnull = "";
int i = 0, idxf = 0, idxg = 0;
int ret;
@@ -417,7 +422,7 @@ static int mxs_pinctrl_probe_dt(struct platform_device *pdev,
/* Count total functions and groups */
fn = fnull;
for_each_child_of_node(np, child) {
- if (of_device_is_compatible(child, gpio_compat))
+ if (is_mxs_gpio(child))
continue;
soc->ngroups++;
/* Skip pure pinconf node */
@@ -446,7 +451,7 @@ static int mxs_pinctrl_probe_dt(struct platform_device *pdev,
fn = fnull;
f = &soc->functions[idxf];
for_each_child_of_node(np, child) {
- if (of_device_is_compatible(child, gpio_compat))
+ if (is_mxs_gpio(child))
continue;
if (of_property_read_u32(child, "reg", &val))
continue;
@@ -486,7 +491,7 @@ static int mxs_pinctrl_probe_dt(struct platform_device *pdev,
idxf = 0;
fn = fnull;
for_each_child_of_node(np, child) {
- if (of_device_is_compatible(child, gpio_compat))
+ if (is_mxs_gpio(child))
continue;
if (of_property_read_u32(child, "reg", &val)) {
ret = mxs_pinctrl_parse_group(pdev, child,
diff --git a/drivers/pinctrl/intel/pinctrl-baytrail.c b/drivers/pinctrl/intel/pinctrl-baytrail.c
index ec76e43527..f1af21dbd5 100644
--- a/drivers/pinctrl/intel/pinctrl-baytrail.c
+++ b/drivers/pinctrl/intel/pinctrl-baytrail.c
@@ -7,16 +7,16 @@
*/
#include <linux/acpi.h>
+#include <linux/array_size.h>
#include <linux/bitops.h>
#include <linux/gpio/driver.h>
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/io.h>
-#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/types.h>
#include <linux/platform_device.h>
-#include <linux/pm_runtime.h>
+#include <linux/pm.h>
#include <linux/property.h>
#include <linux/seq_file.h>
#include <linux/string_helpers.h>
@@ -722,8 +722,6 @@ static int byt_gpio_request_enable(struct pinctrl_dev *pctl_dev,
raw_spin_unlock_irqrestore(&byt_lock, flags);
- pm_runtime_get(vg->dev);
-
return 0;
}
@@ -734,7 +732,6 @@ static void byt_gpio_disable_free(struct pinctrl_dev *pctl_dev,
struct intel_pinctrl *vg = pinctrl_dev_get_drvdata(pctl_dev);
byt_gpio_clear_triggering(vg, offset);
- pm_runtime_put(vg->dev);
}
static void byt_gpio_direct_irq_check(struct intel_pinctrl *vg,
@@ -921,13 +918,14 @@ static int byt_pin_config_set(struct pinctrl_dev *pctl_dev,
unsigned int num_configs)
{
struct intel_pinctrl *vg = pinctrl_dev_get_drvdata(pctl_dev);
- unsigned int param, arg;
void __iomem *conf_reg = byt_gpio_reg(vg, offset, BYT_CONF0_REG);
void __iomem *val_reg = byt_gpio_reg(vg, offset, BYT_VAL_REG);
void __iomem *db_reg = byt_gpio_reg(vg, offset, BYT_DEBOUNCE_REG);
u32 conf, val, db_pulse, debounce;
+ enum pin_config_param param;
unsigned long flags;
int i, ret = 0;
+ u32 arg;
raw_spin_lock_irqsave(&byt_lock, flags);
@@ -1661,7 +1659,6 @@ static int byt_pinctrl_probe(struct platform_device *pdev)
return ret;
platform_set_drvdata(pdev, vg);
- pm_runtime_enable(dev);
return 0;
}
@@ -1750,26 +1747,15 @@ static int byt_gpio_resume(struct device *dev)
return 0;
}
-static int byt_gpio_runtime_suspend(struct device *dev)
-{
- return 0;
-}
-
-static int byt_gpio_runtime_resume(struct device *dev)
-{
- return 0;
-}
-
static const struct dev_pm_ops byt_gpio_pm_ops = {
LATE_SYSTEM_SLEEP_PM_OPS(byt_gpio_suspend, byt_gpio_resume)
- RUNTIME_PM_OPS(byt_gpio_runtime_suspend, byt_gpio_runtime_resume, NULL)
};
static struct platform_driver byt_gpio_driver = {
.probe = byt_pinctrl_probe,
.driver = {
.name = "byt_gpio",
- .pm = pm_ptr(&byt_gpio_pm_ops),
+ .pm = pm_sleep_ptr(&byt_gpio_pm_ops),
.acpi_match_table = byt_gpio_acpi_match,
.suppress_bind_attrs = true,
},
diff --git a/drivers/pinctrl/intel/pinctrl-broxton.c b/drivers/pinctrl/intel/pinctrl-broxton.c
index 4d5ddb2979..3118c7c884 100644
--- a/drivers/pinctrl/intel/pinctrl-broxton.c
+++ b/drivers/pinctrl/intel/pinctrl-broxton.c
@@ -998,6 +998,7 @@ static const struct platform_device_id bxt_pinctrl_platform_ids[] = {
{ "broxton-pinctrl", (kernel_ulong_t)bxt_pinctrl_soc_data },
{ }
};
+MODULE_DEVICE_TABLE(platform, bxt_pinctrl_platform_ids);
static INTEL_PINCTRL_PM_OPS(bxt_pinctrl_pm_ops);
@@ -1026,6 +1027,4 @@ module_exit(bxt_pinctrl_exit);
MODULE_AUTHOR("Mika Westerberg <mika.westerberg@linux.intel.com>");
MODULE_DESCRIPTION("Intel Broxton SoC pinctrl/GPIO driver");
MODULE_LICENSE("GPL v2");
-MODULE_ALIAS("platform:apollolake-pinctrl");
-MODULE_ALIAS("platform:broxton-pinctrl");
MODULE_IMPORT_NS(PINCTRL_INTEL);
diff --git a/drivers/pinctrl/intel/pinctrl-cherryview.c b/drivers/pinctrl/intel/pinctrl-cherryview.c
index 81ee949b94..067b0d344f 100644
--- a/drivers/pinctrl/intel/pinctrl-cherryview.c
+++ b/drivers/pinctrl/intel/pinctrl-cherryview.c
@@ -11,9 +11,10 @@
*/
#include <linux/acpi.h>
+#include <linux/array_size.h>
+#include <linux/cleanup.h>
#include <linux/dmi.h>
#include <linux/gpio/driver.h>
-#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/seq_file.h>
@@ -612,26 +613,26 @@ static void chv_writel(struct intel_pinctrl *pctrl, unsigned int pin, unsigned i
}
/* When Pad Cfg is locked, driver can only change GPIOTXState or GPIORXState */
+static bool chv_pad_is_locked(u32 ctrl1)
+{
+ return ctrl1 & CHV_PADCTRL1_CFGLOCK;
+}
+
static bool chv_pad_locked(struct intel_pinctrl *pctrl, unsigned int offset)
{
- return chv_readl(pctrl, offset, CHV_PADCTRL1) & CHV_PADCTRL1_CFGLOCK;
+ return chv_pad_is_locked(chv_readl(pctrl, offset, CHV_PADCTRL1));
}
static void chv_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
unsigned int offset)
{
struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
- unsigned long flags;
u32 ctrl0, ctrl1;
- bool locked;
-
- raw_spin_lock_irqsave(&chv_lock, flags);
-
- ctrl0 = chv_readl(pctrl, offset, CHV_PADCTRL0);
- ctrl1 = chv_readl(pctrl, offset, CHV_PADCTRL1);
- locked = chv_pad_locked(pctrl, offset);
- raw_spin_unlock_irqrestore(&chv_lock, flags);
+ scoped_guard(raw_spinlock_irqsave, &chv_lock) {
+ ctrl0 = chv_readl(pctrl, offset, CHV_PADCTRL0);
+ ctrl1 = chv_readl(pctrl, offset, CHV_PADCTRL1);
+ }
if (ctrl0 & CHV_PADCTRL0_GPIOEN) {
seq_puts(s, "GPIO ");
@@ -646,7 +647,7 @@ static void chv_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
seq_printf(s, "0x%08x 0x%08x", ctrl0, ctrl1);
- if (locked)
+ if (chv_pad_is_locked(ctrl1))
seq_puts(s, " [LOCKED]");
}
@@ -663,17 +664,15 @@ static int chv_pinmux_set_mux(struct pinctrl_dev *pctldev,
struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
struct device *dev = pctrl->dev;
const struct intel_pingroup *grp;
- unsigned long flags;
int i;
grp = &pctrl->soc->groups[group];
- raw_spin_lock_irqsave(&chv_lock, flags);
+ guard(raw_spinlock_irqsave)(&chv_lock);
/* Check first that the pad is not locked */
for (i = 0; i < grp->grp.npins; i++) {
if (chv_pad_locked(pctrl, grp->grp.pins[i])) {
- raw_spin_unlock_irqrestore(&chv_lock, flags);
dev_warn(dev, "unable to set mode for locked pin %u\n", grp->grp.pins[i]);
return -EBUSY;
}
@@ -713,8 +712,6 @@ static int chv_pinmux_set_mux(struct pinctrl_dev *pctldev,
invert_oe ? "" : "not ");
}
- raw_spin_unlock_irqrestore(&chv_lock, flags);
-
return 0;
}
@@ -745,16 +742,14 @@ static int chv_gpio_request_enable(struct pinctrl_dev *pctldev,
unsigned int offset)
{
struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
- unsigned long flags;
u32 value;
- raw_spin_lock_irqsave(&chv_lock, flags);
+ guard(raw_spinlock_irqsave)(&chv_lock);
if (chv_pad_locked(pctrl, offset)) {
value = chv_readl(pctrl, offset, CHV_PADCTRL0);
if (!(value & CHV_PADCTRL0_GPIOEN)) {
/* Locked so cannot enable */
- raw_spin_unlock_irqrestore(&chv_lock, flags);
return -EBUSY;
}
} else {
@@ -789,8 +784,6 @@ static int chv_gpio_request_enable(struct pinctrl_dev *pctldev,
chv_writel(pctrl, offset, CHV_PADCTRL0, value);
}
- raw_spin_unlock_irqrestore(&chv_lock, flags);
-
return 0;
}
@@ -799,14 +792,13 @@ static void chv_gpio_disable_free(struct pinctrl_dev *pctldev,
unsigned int offset)
{
struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
- unsigned long flags;
- raw_spin_lock_irqsave(&chv_lock, flags);
+ guard(raw_spinlock_irqsave)(&chv_lock);
- if (!chv_pad_locked(pctrl, offset))
- chv_gpio_clear_triggering(pctrl, offset);
+ if (chv_pad_locked(pctrl, offset))
+ return;
- raw_spin_unlock_irqrestore(&chv_lock, flags);
+ chv_gpio_clear_triggering(pctrl, offset);
}
static int chv_gpio_set_direction(struct pinctrl_dev *pctldev,
@@ -814,10 +806,9 @@ static int chv_gpio_set_direction(struct pinctrl_dev *pctldev,
unsigned int offset, bool input)
{
struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
- unsigned long flags;
u32 ctrl0;
- raw_spin_lock_irqsave(&chv_lock, flags);
+ guard(raw_spinlock_irqsave)(&chv_lock);
ctrl0 = chv_readl(pctrl, offset, CHV_PADCTRL0) & ~CHV_PADCTRL0_GPIOCFG_MASK;
if (input)
@@ -826,8 +817,6 @@ static int chv_gpio_set_direction(struct pinctrl_dev *pctldev,
ctrl0 |= CHV_PADCTRL0_GPIOCFG_GPO << CHV_PADCTRL0_GPIOCFG_SHIFT;
chv_writel(pctrl, offset, CHV_PADCTRL0, ctrl0);
- raw_spin_unlock_irqrestore(&chv_lock, flags);
-
return 0;
}
@@ -846,15 +835,14 @@ static int chv_config_get(struct pinctrl_dev *pctldev, unsigned int pin,
{
struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
enum pin_config_param param = pinconf_to_config_param(*config);
- unsigned long flags;
u32 ctrl0, ctrl1;
u16 arg = 0;
u32 term;
- raw_spin_lock_irqsave(&chv_lock, flags);
- ctrl0 = chv_readl(pctrl, pin, CHV_PADCTRL0);
- ctrl1 = chv_readl(pctrl, pin, CHV_PADCTRL1);
- raw_spin_unlock_irqrestore(&chv_lock, flags);
+ scoped_guard(raw_spinlock_irqsave, &chv_lock) {
+ ctrl0 = chv_readl(pctrl, pin, CHV_PADCTRL0);
+ ctrl1 = chv_readl(pctrl, pin, CHV_PADCTRL1);
+ }
term = (ctrl0 & CHV_PADCTRL0_TERM_MASK) >> CHV_PADCTRL0_TERM_SHIFT;
@@ -906,6 +894,7 @@ static int chv_config_get(struct pinctrl_dev *pctldev, unsigned int pin,
return -EINVAL;
break;
+ }
case PIN_CONFIG_DRIVE_PUSH_PULL:
if (ctrl1 & CHV_PADCTRL1_ODEN)
@@ -916,7 +905,6 @@ static int chv_config_get(struct pinctrl_dev *pctldev, unsigned int pin,
if (!(ctrl1 & CHV_PADCTRL1_ODEN))
return -EINVAL;
break;
- }
default:
return -ENOTSUPP;
@@ -929,10 +917,10 @@ static int chv_config_get(struct pinctrl_dev *pctldev, unsigned int pin,
static int chv_config_set_pull(struct intel_pinctrl *pctrl, unsigned int pin,
enum pin_config_param param, u32 arg)
{
- unsigned long flags;
u32 ctrl0, pull;
- raw_spin_lock_irqsave(&chv_lock, flags);
+ guard(raw_spinlock_irqsave)(&chv_lock);
+
ctrl0 = chv_readl(pctrl, pin, CHV_PADCTRL0);
switch (param) {
@@ -955,7 +943,6 @@ static int chv_config_set_pull(struct intel_pinctrl *pctrl, unsigned int pin,
pull = CHV_PADCTRL0_TERM_20K << CHV_PADCTRL0_TERM_SHIFT;
break;
default:
- raw_spin_unlock_irqrestore(&chv_lock, flags);
return -EINVAL;
}
@@ -973,7 +960,6 @@ static int chv_config_set_pull(struct intel_pinctrl *pctrl, unsigned int pin,
pull = CHV_PADCTRL0_TERM_20K << CHV_PADCTRL0_TERM_SHIFT;
break;
default:
- raw_spin_unlock_irqrestore(&chv_lock, flags);
return -EINVAL;
}
@@ -981,12 +967,10 @@ static int chv_config_set_pull(struct intel_pinctrl *pctrl, unsigned int pin,
break;
default:
- raw_spin_unlock_irqrestore(&chv_lock, flags);
return -EINVAL;
}
chv_writel(pctrl, pin, CHV_PADCTRL0, ctrl0);
- raw_spin_unlock_irqrestore(&chv_lock, flags);
return 0;
}
@@ -994,10 +978,10 @@ static int chv_config_set_pull(struct intel_pinctrl *pctrl, unsigned int pin,
static int chv_config_set_oden(struct intel_pinctrl *pctrl, unsigned int pin,
bool enable)
{
- unsigned long flags;
u32 ctrl1;
- raw_spin_lock_irqsave(&chv_lock, flags);
+ guard(raw_spinlock_irqsave)(&chv_lock);
+
ctrl1 = chv_readl(pctrl, pin, CHV_PADCTRL1);
if (enable)
@@ -1006,7 +990,6 @@ static int chv_config_set_oden(struct intel_pinctrl *pctrl, unsigned int pin,
ctrl1 &= ~CHV_PADCTRL1_ODEN;
chv_writel(pctrl, pin, CHV_PADCTRL1, ctrl1);
- raw_spin_unlock_irqrestore(&chv_lock, flags);
return 0;
}
@@ -1116,12 +1099,10 @@ static struct pinctrl_desc chv_pinctrl_desc = {
static int chv_gpio_get(struct gpio_chip *chip, unsigned int offset)
{
struct intel_pinctrl *pctrl = gpiochip_get_data(chip);
- unsigned long flags;
u32 ctrl0, cfg;
- raw_spin_lock_irqsave(&chv_lock, flags);
- ctrl0 = chv_readl(pctrl, offset, CHV_PADCTRL0);
- raw_spin_unlock_irqrestore(&chv_lock, flags);
+ scoped_guard(raw_spinlock_irqsave, &chv_lock)
+ ctrl0 = chv_readl(pctrl, offset, CHV_PADCTRL0);
cfg = ctrl0 & CHV_PADCTRL0_GPIOCFG_MASK;
cfg >>= CHV_PADCTRL0_GPIOCFG_SHIFT;
@@ -1134,10 +1115,9 @@ static int chv_gpio_get(struct gpio_chip *chip, unsigned int offset)
static void chv_gpio_set(struct gpio_chip *chip, unsigned int offset, int value)
{
struct intel_pinctrl *pctrl = gpiochip_get_data(chip);
- unsigned long flags;
u32 ctrl0;
- raw_spin_lock_irqsave(&chv_lock, flags);
+ guard(raw_spinlock_irqsave)(&chv_lock);
ctrl0 = chv_readl(pctrl, offset, CHV_PADCTRL0);
@@ -1147,19 +1127,15 @@ static void chv_gpio_set(struct gpio_chip *chip, unsigned int offset, int value)
ctrl0 &= ~CHV_PADCTRL0_GPIOTXSTATE;
chv_writel(pctrl, offset, CHV_PADCTRL0, ctrl0);
-
- raw_spin_unlock_irqrestore(&chv_lock, flags);
}
static int chv_gpio_get_direction(struct gpio_chip *chip, unsigned int offset)
{
struct intel_pinctrl *pctrl = gpiochip_get_data(chip);
u32 ctrl0, direction;
- unsigned long flags;
- raw_spin_lock_irqsave(&chv_lock, flags);
- ctrl0 = chv_readl(pctrl, offset, CHV_PADCTRL0);
- raw_spin_unlock_irqrestore(&chv_lock, flags);
+ scoped_guard(raw_spinlock_irqsave, &chv_lock)
+ ctrl0 = chv_readl(pctrl, offset, CHV_PADCTRL0);
direction = ctrl0 & CHV_PADCTRL0_GPIOCFG_MASK;
direction >>= CHV_PADCTRL0_GPIOCFG_SHIFT;
@@ -1172,14 +1148,14 @@ static int chv_gpio_get_direction(struct gpio_chip *chip, unsigned int offset)
static int chv_gpio_direction_input(struct gpio_chip *chip, unsigned int offset)
{
- return pinctrl_gpio_direction_input(chip->base + offset);
+ return pinctrl_gpio_direction_input(chip, offset);
}
static int chv_gpio_direction_output(struct gpio_chip *chip, unsigned int offset,
int value)
{
chv_gpio_set(chip, offset, value);
- return pinctrl_gpio_direction_output(chip->base + offset);
+ return pinctrl_gpio_direction_output(chip, offset);
}
static const struct gpio_chip chv_gpio_chip = {
@@ -1200,23 +1176,20 @@ static void chv_gpio_irq_ack(struct irq_data *d)
irq_hw_number_t hwirq = irqd_to_hwirq(d);
u32 intr_line;
- raw_spin_lock(&chv_lock);
+ guard(raw_spinlock)(&chv_lock);
intr_line = chv_readl(pctrl, hwirq, CHV_PADCTRL0);
intr_line &= CHV_PADCTRL0_INTSEL_MASK;
intr_line >>= CHV_PADCTRL0_INTSEL_SHIFT;
chv_pctrl_writel(pctrl, CHV_INTSTAT, BIT(intr_line));
-
- raw_spin_unlock(&chv_lock);
}
static void chv_gpio_irq_mask_unmask(struct gpio_chip *gc, irq_hw_number_t hwirq, bool mask)
{
struct intel_pinctrl *pctrl = gpiochip_get_data(gc);
u32 value, intr_line;
- unsigned long flags;
- raw_spin_lock_irqsave(&chv_lock, flags);
+ guard(raw_spinlock_irqsave)(&chv_lock);
intr_line = chv_readl(pctrl, hwirq, CHV_PADCTRL0);
intr_line &= CHV_PADCTRL0_INTSEL_MASK;
@@ -1228,8 +1201,6 @@ static void chv_gpio_irq_mask_unmask(struct gpio_chip *gc, irq_hw_number_t hwirq
else
value |= BIT(intr_line);
chv_pctrl_writel(pctrl, CHV_INTMASK, value);
-
- raw_spin_unlock_irqrestore(&chv_lock, flags);
}
static void chv_gpio_irq_mask(struct irq_data *d)
@@ -1254,7 +1225,15 @@ static unsigned chv_gpio_irq_startup(struct irq_data *d)
{
/*
* Check if the interrupt has been requested with 0 as triggering
- * type. In that case it is assumed that the current values
+ * type. If not, bail out, ...
+ */
+ if (irqd_get_trigger_type(d) != IRQ_TYPE_NONE) {
+ chv_gpio_irq_unmask(d);
+ return 0;
+ }
+
+ /*
+ * ...otherwise it is assumed that the current values
* programmed to the hardware are used (e.g BIOS configured
* defaults).
*
@@ -1262,17 +1241,15 @@ static unsigned chv_gpio_irq_startup(struct irq_data *d)
* read back the values from hardware now, set correct flow handler
* and update mappings before the interrupt is being used.
*/
- if (irqd_get_trigger_type(d) == IRQ_TYPE_NONE) {
+ scoped_guard(raw_spinlock_irqsave, &chv_lock) {
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
struct intel_pinctrl *pctrl = gpiochip_get_data(gc);
struct device *dev = pctrl->dev;
struct intel_community_context *cctx = &pctrl->context.communities[0];
irq_hw_number_t hwirq = irqd_to_hwirq(d);
irq_flow_handler_t handler;
- unsigned long flags;
u32 intsel, value;
- raw_spin_lock_irqsave(&chv_lock, flags);
intsel = chv_readl(pctrl, hwirq, CHV_PADCTRL0);
intsel &= CHV_PADCTRL0_INTSEL_MASK;
intsel >>= CHV_PADCTRL0_INTSEL_SHIFT;
@@ -1289,7 +1266,6 @@ static unsigned chv_gpio_irq_startup(struct irq_data *d)
intsel, hwirq);
cctx->intr_lines[intsel] = hwirq;
}
- raw_spin_unlock_irqrestore(&chv_lock, flags);
}
chv_gpio_irq_unmask(d);
@@ -1354,17 +1330,14 @@ static int chv_gpio_irq_type(struct irq_data *d, unsigned int type)
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
struct intel_pinctrl *pctrl = gpiochip_get_data(gc);
irq_hw_number_t hwirq = irqd_to_hwirq(d);
- unsigned long flags;
u32 value;
int ret;
- raw_spin_lock_irqsave(&chv_lock, flags);
+ guard(raw_spinlock_irqsave)(&chv_lock);
ret = chv_gpio_set_intr_line(pctrl, hwirq);
- if (ret) {
- raw_spin_unlock_irqrestore(&chv_lock, flags);
+ if (ret)
return ret;
- }
/*
* Pins which can be used as shared interrupt are configured in
@@ -1405,8 +1378,6 @@ static int chv_gpio_irq_type(struct irq_data *d, unsigned int type)
else if (type & IRQ_TYPE_LEVEL_MASK)
irq_set_handler_locked(d, handle_level_irq);
- raw_spin_unlock_irqrestore(&chv_lock, flags);
-
return 0;
}
@@ -1430,14 +1401,12 @@ static void chv_gpio_irq_handler(struct irq_desc *desc)
struct intel_community_context *cctx = &pctrl->context.communities[0];
struct irq_chip *chip = irq_desc_get_chip(desc);
unsigned long pending;
- unsigned long flags;
u32 intr_line;
chained_irq_enter(chip, desc);
- raw_spin_lock_irqsave(&chv_lock, flags);
- pending = chv_pctrl_readl(pctrl, CHV_INTSTAT);
- raw_spin_unlock_irqrestore(&chv_lock, flags);
+ scoped_guard(raw_spinlock_irqsave, &chv_lock)
+ pending = chv_pctrl_readl(pctrl, CHV_INTSTAT);
for_each_set_bit(intr_line, &pending, community->nirqs) {
unsigned int offset;
@@ -1626,21 +1595,17 @@ static acpi_status chv_pinctrl_mmio_access_handler(u32 function,
void *handler_context, void *region_context)
{
struct intel_pinctrl *pctrl = region_context;
- unsigned long flags;
- acpi_status ret = AE_OK;
- raw_spin_lock_irqsave(&chv_lock, flags);
+ guard(raw_spinlock_irqsave)(&chv_lock);
if (function == ACPI_WRITE)
chv_pctrl_writel(pctrl, address, *value);
else if (function == ACPI_READ)
*value = chv_pctrl_readl(pctrl, address);
else
- ret = AE_BAD_PARAMETER;
-
- raw_spin_unlock_irqrestore(&chv_lock, flags);
+ return AE_BAD_PARAMETER;
- return ret;
+ return AE_OK;
}
static int chv_pinctrl_probe(struct platform_device *pdev)
@@ -1728,7 +1693,7 @@ static int chv_pinctrl_probe(struct platform_device *pdev)
return 0;
}
-static int chv_pinctrl_remove(struct platform_device *pdev)
+static void chv_pinctrl_remove(struct platform_device *pdev)
{
struct intel_pinctrl *pctrl = platform_get_drvdata(pdev);
const struct intel_community *community = &pctrl->communities[0];
@@ -1736,18 +1701,15 @@ static int chv_pinctrl_remove(struct platform_device *pdev)
acpi_remove_address_space_handler(ACPI_HANDLE(&pdev->dev),
community->acpi_space_id,
chv_pinctrl_mmio_access_handler);
-
- return 0;
}
static int chv_pinctrl_suspend_noirq(struct device *dev)
{
struct intel_pinctrl *pctrl = dev_get_drvdata(dev);
struct intel_community_context *cctx = &pctrl->context.communities[0];
- unsigned long flags;
int i;
- raw_spin_lock_irqsave(&chv_lock, flags);
+ guard(raw_spinlock_irqsave)(&chv_lock);
cctx->saved_intmask = chv_pctrl_readl(pctrl, CHV_INTMASK);
@@ -1765,8 +1727,6 @@ static int chv_pinctrl_suspend_noirq(struct device *dev)
ctx->padctrl1 = chv_readl(pctrl, desc->number, CHV_PADCTRL1);
}
- raw_spin_unlock_irqrestore(&chv_lock, flags);
-
return 0;
}
@@ -1774,10 +1734,9 @@ static int chv_pinctrl_resume_noirq(struct device *dev)
{
struct intel_pinctrl *pctrl = dev_get_drvdata(dev);
struct intel_community_context *cctx = &pctrl->context.communities[0];
- unsigned long flags;
int i;
- raw_spin_lock_irqsave(&chv_lock, flags);
+ guard(raw_spinlock_irqsave)(&chv_lock);
/*
* Mask all interrupts before restoring per-pin configuration
@@ -1819,8 +1778,6 @@ static int chv_pinctrl_resume_noirq(struct device *dev)
chv_pctrl_writel(pctrl, CHV_INTSTAT, 0xffff);
chv_pctrl_writel(pctrl, CHV_INTMASK, cctx->saved_intmask);
- raw_spin_unlock_irqrestore(&chv_lock, flags);
-
return 0;
}
@@ -1835,7 +1792,7 @@ MODULE_DEVICE_TABLE(acpi, chv_pinctrl_acpi_match);
static struct platform_driver chv_pinctrl_driver = {
.probe = chv_pinctrl_probe,
- .remove = chv_pinctrl_remove,
+ .remove_new = chv_pinctrl_remove,
.driver = {
.name = "cherryview-pinctrl",
.pm = pm_sleep_ptr(&chv_pinctrl_pm_ops),
diff --git a/drivers/pinctrl/intel/pinctrl-denverton.c b/drivers/pinctrl/intel/pinctrl-denverton.c
index 0c4694cfa5..562a4f9188 100644
--- a/drivers/pinctrl/intel/pinctrl-denverton.c
+++ b/drivers/pinctrl/intel/pinctrl-denverton.c
@@ -257,6 +257,12 @@ static const struct acpi_device_id dnv_pinctrl_acpi_match[] = {
};
MODULE_DEVICE_TABLE(acpi, dnv_pinctrl_acpi_match);
+static const struct platform_device_id dnv_pinctrl_platform_ids[] = {
+ { "denverton-pinctrl", (kernel_ulong_t)&dnv_soc_data },
+ { }
+};
+MODULE_DEVICE_TABLE(platform, dnv_pinctrl_platform_ids);
+
static struct platform_driver dnv_pinctrl_driver = {
.probe = intel_pinctrl_probe_by_hid,
.driver = {
@@ -264,6 +270,7 @@ static struct platform_driver dnv_pinctrl_driver = {
.acpi_match_table = dnv_pinctrl_acpi_match,
.pm = &dnv_pinctrl_pm_ops,
},
+ .id_table = dnv_pinctrl_platform_ids,
};
static int __init dnv_pinctrl_init(void)
diff --git a/drivers/pinctrl/intel/pinctrl-intel.c b/drivers/pinctrl/intel/pinctrl-intel.c
index 3be04ab760..652ba451f8 100644
--- a/drivers/pinctrl/intel/pinctrl-intel.c
+++ b/drivers/pinctrl/intel/pinctrl-intel.c
@@ -8,6 +8,7 @@
*/
#include <linux/acpi.h>
+#include <linux/cleanup.h>
#include <linux/gpio/driver.h>
#include <linux/interrupt.h>
#include <linux/log2.h>
@@ -393,20 +394,17 @@ static int intel_pinmux_set_mux(struct pinctrl_dev *pctldev,
{
struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
const struct intel_pingroup *grp = &pctrl->soc->groups[group];
- unsigned long flags;
int i;
- raw_spin_lock_irqsave(&pctrl->lock, flags);
+ guard(raw_spinlock_irqsave)(&pctrl->lock);
/*
* All pins in the groups needs to be accessible and writable
* before we can enable the mux for this group.
*/
for (i = 0; i < grp->grp.npins; i++) {
- if (!intel_pad_usable(pctrl, grp->grp.pins[i])) {
- raw_spin_unlock_irqrestore(&pctrl->lock, flags);
+ if (!intel_pad_usable(pctrl, grp->grp.pins[i]))
return -EBUSY;
- }
}
/* Now enable the mux setting for each pin in the group */
@@ -428,8 +426,6 @@ static int intel_pinmux_set_mux(struct pinctrl_dev *pctldev,
writel(value, padcfg0);
}
- raw_spin_unlock_irqrestore(&pctrl->lock, flags);
-
return 0;
}
@@ -485,21 +481,16 @@ static int intel_gpio_request_enable(struct pinctrl_dev *pctldev,
{
struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
void __iomem *padcfg0;
- unsigned long flags;
padcfg0 = intel_get_padcfg(pctrl, pin, PADCFG0);
- raw_spin_lock_irqsave(&pctrl->lock, flags);
+ guard(raw_spinlock_irqsave)(&pctrl->lock);
- if (!intel_pad_owned_by_host(pctrl, pin)) {
- raw_spin_unlock_irqrestore(&pctrl->lock, flags);
+ if (!intel_pad_owned_by_host(pctrl, pin))
return -EBUSY;
- }
- if (!intel_pad_is_unlocked(pctrl, pin)) {
- raw_spin_unlock_irqrestore(&pctrl->lock, flags);
+ if (!intel_pad_is_unlocked(pctrl, pin))
return 0;
- }
/*
* If pin is already configured in GPIO mode, we assume that
@@ -507,15 +498,11 @@ static int intel_gpio_request_enable(struct pinctrl_dev *pctldev,
* potential glitches on the pin. Otherwise, for the pin in
* alternative mode, consumer has to supply respective flags.
*/
- if (intel_gpio_get_gpio_mode(padcfg0) == PADCFG0_PMODE_GPIO) {
- raw_spin_unlock_irqrestore(&pctrl->lock, flags);
+ if (intel_gpio_get_gpio_mode(padcfg0) == PADCFG0_PMODE_GPIO)
return 0;
- }
intel_gpio_set_gpio_mode(padcfg0);
- raw_spin_unlock_irqrestore(&pctrl->lock, flags);
-
return 0;
}
@@ -525,13 +512,12 @@ static int intel_gpio_set_direction(struct pinctrl_dev *pctldev,
{
struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
void __iomem *padcfg0;
- unsigned long flags;
padcfg0 = intel_get_padcfg(pctrl, pin, PADCFG0);
- raw_spin_lock_irqsave(&pctrl->lock, flags);
+ guard(raw_spinlock_irqsave)(&pctrl->lock);
+
__intel_gpio_set_direction(padcfg0, input);
- raw_spin_unlock_irqrestore(&pctrl->lock, flags);
return 0;
}
@@ -548,17 +534,13 @@ static const struct pinmux_ops intel_pinmux_ops = {
static int intel_config_get_pull(struct intel_pinctrl *pctrl, unsigned int pin,
enum pin_config_param param, u32 *arg)
{
- const struct intel_community *community;
void __iomem *padcfg1;
- unsigned long flags;
u32 value, term;
- community = intel_get_community(pctrl, pin);
padcfg1 = intel_get_padcfg(pctrl, pin, PADCFG1);
- raw_spin_lock_irqsave(&pctrl->lock, flags);
- value = readl(padcfg1);
- raw_spin_unlock_irqrestore(&pctrl->lock, flags);
+ scoped_guard(raw_spinlock_irqsave, &pctrl->lock)
+ value = readl(padcfg1);
term = (value & PADCFG1_TERM_MASK) >> PADCFG1_TERM_SHIFT;
@@ -592,7 +574,9 @@ static int intel_config_get_pull(struct intel_pinctrl *pctrl, unsigned int pin,
break;
- case PIN_CONFIG_BIAS_PULL_DOWN:
+ case PIN_CONFIG_BIAS_PULL_DOWN: {
+ const struct intel_community *community = intel_get_community(pctrl, pin);
+
if (!term || value & PADCFG1_TERM_UP)
return -EINVAL;
@@ -619,6 +603,7 @@ static int intel_config_get_pull(struct intel_pinctrl *pctrl, unsigned int pin,
}
break;
+ }
default:
return -EINVAL;
@@ -631,7 +616,6 @@ static int intel_config_get_debounce(struct intel_pinctrl *pctrl, unsigned int p
enum pin_config_param param, u32 *arg)
{
void __iomem *padcfg2;
- unsigned long flags;
unsigned long v;
u32 value2;
@@ -639,9 +623,9 @@ static int intel_config_get_debounce(struct intel_pinctrl *pctrl, unsigned int p
if (!padcfg2)
return -ENOTSUPP;
- raw_spin_lock_irqsave(&pctrl->lock, flags);
- value2 = readl(padcfg2);
- raw_spin_unlock_irqrestore(&pctrl->lock, flags);
+ scoped_guard(raw_spinlock_irqsave, &pctrl->lock)
+ value2 = readl(padcfg2);
+
if (!(value2 & PADCFG2_DEBEN))
return -EINVAL;
@@ -690,19 +674,8 @@ static int intel_config_set_pull(struct intel_pinctrl *pctrl, unsigned int pin,
{
unsigned int param = pinconf_to_config_param(config);
unsigned int arg = pinconf_to_config_argument(config);
- const struct intel_community *community;
+ u32 term = 0, up = 0, value;
void __iomem *padcfg1;
- unsigned long flags;
- int ret = 0;
- u32 value;
-
- community = intel_get_community(pctrl, pin);
- padcfg1 = intel_get_padcfg(pctrl, pin, PADCFG1);
-
- raw_spin_lock_irqsave(&pctrl->lock, flags);
-
- value = readl(padcfg1);
- value &= ~(PADCFG1_TERM_MASK | PADCFG1_TERM_UP);
/* Set default strength value in case none is given */
if (arg == 1)
@@ -715,78 +688,77 @@ static int intel_config_set_pull(struct intel_pinctrl *pctrl, unsigned int pin,
case PIN_CONFIG_BIAS_PULL_UP:
switch (arg) {
case 20000:
- value |= PADCFG1_TERM_20K << PADCFG1_TERM_SHIFT;
+ term = PADCFG1_TERM_20K;
break;
case 5000:
- value |= PADCFG1_TERM_5K << PADCFG1_TERM_SHIFT;
+ term = PADCFG1_TERM_5K;
break;
case 4000:
- value |= PADCFG1_TERM_4K << PADCFG1_TERM_SHIFT;
+ term = PADCFG1_TERM_4K;
break;
case 1000:
- value |= PADCFG1_TERM_1K << PADCFG1_TERM_SHIFT;
+ term = PADCFG1_TERM_1K;
break;
case 833:
- value |= PADCFG1_TERM_833 << PADCFG1_TERM_SHIFT;
+ term = PADCFG1_TERM_833;
break;
default:
- ret = -EINVAL;
- break;
+ return -EINVAL;
}
- value |= PADCFG1_TERM_UP;
+ up = PADCFG1_TERM_UP;
break;
- case PIN_CONFIG_BIAS_PULL_DOWN:
+ case PIN_CONFIG_BIAS_PULL_DOWN: {
+ const struct intel_community *community = intel_get_community(pctrl, pin);
+
switch (arg) {
case 20000:
- value |= PADCFG1_TERM_20K << PADCFG1_TERM_SHIFT;
+ term = PADCFG1_TERM_20K;
break;
case 5000:
- value |= PADCFG1_TERM_5K << PADCFG1_TERM_SHIFT;
+ term = PADCFG1_TERM_5K;
break;
case 4000:
- value |= PADCFG1_TERM_4K << PADCFG1_TERM_SHIFT;
+ term = PADCFG1_TERM_4K;
break;
case 1000:
- if (!(community->features & PINCTRL_FEATURE_1K_PD)) {
- ret = -EINVAL;
- break;
- }
- value |= PADCFG1_TERM_1K << PADCFG1_TERM_SHIFT;
+ if (!(community->features & PINCTRL_FEATURE_1K_PD))
+ return -EINVAL;
+ term = PADCFG1_TERM_1K;
break;
case 833:
- if (!(community->features & PINCTRL_FEATURE_1K_PD)) {
- ret = -EINVAL;
- break;
- }
- value |= PADCFG1_TERM_833 << PADCFG1_TERM_SHIFT;
+ if (!(community->features & PINCTRL_FEATURE_1K_PD))
+ return -EINVAL;
+ term = PADCFG1_TERM_833;
break;
default:
- ret = -EINVAL;
- break;
+ return -EINVAL;
}
break;
+ }
default:
- ret = -EINVAL;
- break;
+ return -EINVAL;
}
- if (!ret)
- writel(value, padcfg1);
+ padcfg1 = intel_get_padcfg(pctrl, pin, PADCFG1);
- raw_spin_unlock_irqrestore(&pctrl->lock, flags);
+ guard(raw_spinlock_irqsave)(&pctrl->lock);
- return ret;
+ value = readl(padcfg1);
+ value = (value & ~PADCFG1_TERM_MASK) | (term << PADCFG1_TERM_SHIFT);
+ value = (value & ~PADCFG1_TERM_UP) | up;
+ writel(value, padcfg1);
+
+ return 0;
}
static int intel_config_set_debounce(struct intel_pinctrl *pctrl,
unsigned int pin, unsigned int debounce)
{
void __iomem *padcfg0, *padcfg2;
- unsigned long flags;
u32 value0, value2;
padcfg2 = intel_get_padcfg(pctrl, pin, PADCFG2);
@@ -795,7 +767,7 @@ static int intel_config_set_debounce(struct intel_pinctrl *pctrl,
padcfg0 = intel_get_padcfg(pctrl, pin, PADCFG0);
- raw_spin_lock_irqsave(&pctrl->lock, flags);
+ guard(raw_spinlock_irqsave)(&pctrl->lock);
value0 = readl(padcfg0);
value2 = readl(padcfg2);
@@ -808,10 +780,8 @@ static int intel_config_set_debounce(struct intel_pinctrl *pctrl,
unsigned long v;
v = order_base_2(debounce * NSEC_PER_USEC / DEBOUNCE_PERIOD_NSEC);
- if (v < 3 || v > 15) {
- raw_spin_unlock_irqrestore(&pctrl->lock, flags);
+ if (v < 3 || v > 15)
return -EINVAL;
- }
/* Enable glitch filter and debouncer */
value0 |= PADCFG0_PREGFRXSEL;
@@ -822,8 +792,6 @@ static int intel_config_set_debounce(struct intel_pinctrl *pctrl,
writel(value0, padcfg0);
writel(value2, padcfg2);
- raw_spin_unlock_irqrestore(&pctrl->lock, flags);
-
return 0;
}
@@ -973,7 +941,6 @@ static void intel_gpio_set(struct gpio_chip *chip, unsigned int offset,
int value)
{
struct intel_pinctrl *pctrl = gpiochip_get_data(chip);
- unsigned long flags;
void __iomem *reg;
u32 padcfg0;
int pin;
@@ -986,20 +953,19 @@ static void intel_gpio_set(struct gpio_chip *chip, unsigned int offset,
if (!reg)
return;
- raw_spin_lock_irqsave(&pctrl->lock, flags);
+ guard(raw_spinlock_irqsave)(&pctrl->lock);
+
padcfg0 = readl(reg);
if (value)
padcfg0 |= PADCFG0_GPIOTXSTATE;
else
padcfg0 &= ~PADCFG0_GPIOTXSTATE;
writel(padcfg0, reg);
- raw_spin_unlock_irqrestore(&pctrl->lock, flags);
}
static int intel_gpio_get_direction(struct gpio_chip *chip, unsigned int offset)
{
struct intel_pinctrl *pctrl = gpiochip_get_data(chip);
- unsigned long flags;
void __iomem *reg;
u32 padcfg0;
int pin;
@@ -1012,9 +978,9 @@ static int intel_gpio_get_direction(struct gpio_chip *chip, unsigned int offset)
if (!reg)
return -EINVAL;
- raw_spin_lock_irqsave(&pctrl->lock, flags);
- padcfg0 = readl(reg);
- raw_spin_unlock_irqrestore(&pctrl->lock, flags);
+ scoped_guard(raw_spinlock_irqsave, &pctrl->lock)
+ padcfg0 = readl(reg);
+
if (padcfg0 & PADCFG0_PMODE_MASK)
return -EINVAL;
@@ -1026,14 +992,14 @@ static int intel_gpio_get_direction(struct gpio_chip *chip, unsigned int offset)
static int intel_gpio_direction_input(struct gpio_chip *chip, unsigned int offset)
{
- return pinctrl_gpio_direction_input(chip->base + offset);
+ return pinctrl_gpio_direction_input(chip, offset);
}
static int intel_gpio_direction_output(struct gpio_chip *chip, unsigned int offset,
int value)
{
intel_gpio_set(chip, offset, value);
- return pinctrl_gpio_direction_output(chip->base + offset);
+ return pinctrl_gpio_direction_output(chip, offset);
}
static const struct gpio_chip intel_gpio_chip = {
@@ -1058,15 +1024,17 @@ static void intel_gpio_irq_ack(struct irq_data *d)
pin = intel_gpio_to_pin(pctrl, irqd_to_hwirq(d), &community, &padgrp);
if (pin >= 0) {
- unsigned int gpp, gpp_offset, is_offset;
+ unsigned int gpp, gpp_offset;
+ void __iomem *is;
gpp = padgrp->reg_num;
gpp_offset = padgroup_offset(padgrp, pin);
- is_offset = community->is_offset + gpp * 4;
- raw_spin_lock(&pctrl->lock);
- writel(BIT(gpp_offset), community->regs + is_offset);
- raw_spin_unlock(&pctrl->lock);
+ is = community->regs + community->is_offset + gpp * 4;
+
+ guard(raw_spinlock)(&pctrl->lock);
+
+ writel(BIT(gpp_offset), is);
}
}
@@ -1080,7 +1048,6 @@ static void intel_gpio_irq_mask_unmask(struct gpio_chip *gc, irq_hw_number_t hwi
pin = intel_gpio_to_pin(pctrl, hwirq, &community, &padgrp);
if (pin >= 0) {
unsigned int gpp, gpp_offset;
- unsigned long flags;
void __iomem *reg, *is;
u32 value;
@@ -1090,7 +1057,7 @@ static void intel_gpio_irq_mask_unmask(struct gpio_chip *gc, irq_hw_number_t hwi
reg = community->regs + community->ie_offset + gpp * 4;
is = community->regs + community->is_offset + gpp * 4;
- raw_spin_lock_irqsave(&pctrl->lock, flags);
+ guard(raw_spinlock_irqsave)(&pctrl->lock);
/* Clear interrupt status first to avoid unexpected interrupt */
writel(BIT(gpp_offset), is);
@@ -1101,7 +1068,6 @@ static void intel_gpio_irq_mask_unmask(struct gpio_chip *gc, irq_hw_number_t hwi
else
value |= BIT(gpp_offset);
writel(value, reg);
- raw_spin_unlock_irqrestore(&pctrl->lock, flags);
}
}
@@ -1129,7 +1095,6 @@ static int intel_gpio_irq_type(struct irq_data *d, unsigned int type)
struct intel_pinctrl *pctrl = gpiochip_get_data(gc);
unsigned int pin = intel_gpio_to_pin(pctrl, irqd_to_hwirq(d), NULL, NULL);
u32 rxevcfg, rxinv, value;
- unsigned long flags;
void __iomem *reg;
reg = intel_get_padcfg(pctrl, pin, PADCFG0);
@@ -1163,7 +1128,7 @@ static int intel_gpio_irq_type(struct irq_data *d, unsigned int type)
else
rxinv = 0;
- raw_spin_lock_irqsave(&pctrl->lock, flags);
+ guard(raw_spinlock_irqsave)(&pctrl->lock);
intel_gpio_set_gpio_mode(reg);
@@ -1179,8 +1144,6 @@ static int intel_gpio_irq_type(struct irq_data *d, unsigned int type)
else if (type & IRQ_TYPE_LEVEL_MASK)
irq_set_handler_locked(d, handle_level_irq);
- raw_spin_unlock_irqrestore(&pctrl->lock, flags);
-
return 0;
}
@@ -1219,16 +1182,19 @@ static int intel_gpio_community_irq_handler(struct intel_pinctrl *pctrl,
for (gpp = 0; gpp < community->ngpps; gpp++) {
const struct intel_padgroup *padgrp = &community->gpps[gpp];
- unsigned long pending, enabled, gpp_offset;
+ unsigned long pending, enabled;
+ unsigned int gpp, gpp_offset;
+ void __iomem *reg, *is;
- raw_spin_lock(&pctrl->lock);
+ gpp = padgrp->reg_num;
- pending = readl(community->regs + community->is_offset +
- padgrp->reg_num * 4);
- enabled = readl(community->regs + community->ie_offset +
- padgrp->reg_num * 4);
+ reg = community->regs + community->ie_offset + gpp * 4;
+ is = community->regs + community->is_offset + gpp * 4;
- raw_spin_unlock(&pctrl->lock);
+ scoped_guard(raw_spinlock, &pctrl->lock) {
+ pending = readl(is);
+ enabled = readl(reg);
+ }
/* Only interrupts that are enabled */
pending &= enabled;
@@ -1264,16 +1230,18 @@ static void intel_gpio_irq_init(struct intel_pinctrl *pctrl)
for (i = 0; i < pctrl->ncommunities; i++) {
const struct intel_community *community;
- void __iomem *base;
+ void __iomem *reg, *is;
unsigned int gpp;
community = &pctrl->communities[i];
- base = community->regs;
for (gpp = 0; gpp < community->ngpps; gpp++) {
+ reg = community->regs + community->ie_offset + gpp * 4;
+ is = community->regs + community->is_offset + gpp * 4;
+
/* Mask and clear all interrupts */
- writel(0, base + community->ie_offset + gpp * 4);
- writel(0xffff, base + community->is_offset + gpp * 4);
+ writel(0, reg);
+ writel(0xffff, is);
}
}
}
@@ -1694,7 +1662,7 @@ const struct intel_pinctrl_soc_data *intel_pinctrl_get_soc_data(struct platform_
unsigned int i;
for (i = 0; table[i]; i++) {
- if (!strcmp(adev->pnp.unique_id, table[i]->uid)) {
+ if (acpi_dev_uid_match(adev, table[i]->uid)) {
data = table[i];
break;
}
diff --git a/drivers/pinctrl/intel/pinctrl-intel.h b/drivers/pinctrl/intel/pinctrl-intel.h
index cee512f97b..2bb553598e 100644
--- a/drivers/pinctrl/intel/pinctrl-intel.h
+++ b/drivers/pinctrl/intel/pinctrl-intel.h
@@ -10,11 +10,11 @@
#ifndef PINCTRL_INTEL_H
#define PINCTRL_INTEL_H
+#include <linux/array_size.h>
#include <linux/bits.h>
#include <linux/compiler_types.h>
#include <linux/gpio/driver.h>
#include <linux/irq.h>
-#include <linux/kernel.h>
#include <linux/pm.h>
#include <linux/pinctrl/pinctrl.h>
#include <linux/spinlock_types.h>
diff --git a/drivers/pinctrl/intel/pinctrl-lynxpoint.c b/drivers/pinctrl/intel/pinctrl-lynxpoint.c
index c3732a9f06..e6878e4cf2 100644
--- a/drivers/pinctrl/intel/pinctrl-lynxpoint.c
+++ b/drivers/pinctrl/intel/pinctrl-lynxpoint.c
@@ -8,14 +8,14 @@
*/
#include <linux/acpi.h>
+#include <linux/array_size.h>
#include <linux/bitops.h>
#include <linux/gpio/driver.h>
#include <linux/interrupt.h>
#include <linux/io.h>
-#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/platform_device.h>
-#include <linux/pm_runtime.h>
+#include <linux/pm.h>
#include <linux/seq_file.h>
#include <linux/slab.h>
#include <linux/types.h>
@@ -337,8 +337,6 @@ static int lp_gpio_request_enable(struct pinctrl_dev *pctldev,
unsigned long flags;
u32 value;
- pm_runtime_get(lg->dev);
-
raw_spin_lock_irqsave(&lg->lock, flags);
/*
@@ -373,8 +371,6 @@ static void lp_gpio_disable_free(struct pinctrl_dev *pctldev,
lp_gpio_disable_input(conf2);
raw_spin_unlock_irqrestore(&lg->lock, flags);
-
- pm_runtime_put(lg->dev);
}
static int lp_gpio_set_direction(struct pinctrl_dev *pctldev,
@@ -545,7 +541,7 @@ static void lp_gpio_set(struct gpio_chip *chip, unsigned int offset, int value)
static int lp_gpio_direction_input(struct gpio_chip *chip, unsigned int offset)
{
- return pinctrl_gpio_direction_input(chip->base + offset);
+ return pinctrl_gpio_direction_input(chip, offset);
}
static int lp_gpio_direction_output(struct gpio_chip *chip, unsigned int offset,
@@ -553,7 +549,7 @@ static int lp_gpio_direction_output(struct gpio_chip *chip, unsigned int offset,
{
lp_gpio_set(chip, offset, value);
- return pinctrl_gpio_direction_output(chip->base + offset);
+ return pinctrl_gpio_direction_output(chip, offset);
}
static int lp_gpio_get_direction(struct gpio_chip *chip, unsigned int offset)
@@ -841,24 +837,6 @@ static int lp_gpio_probe(struct platform_device *pdev)
return ret;
}
- pm_runtime_enable(dev);
-
- return 0;
-}
-
-static int lp_gpio_remove(struct platform_device *pdev)
-{
- pm_runtime_disable(&pdev->dev);
- return 0;
-}
-
-static int lp_gpio_runtime_suspend(struct device *dev)
-{
- return 0;
-}
-
-static int lp_gpio_runtime_resume(struct device *dev)
-{
return 0;
}
@@ -876,10 +854,7 @@ static int lp_gpio_resume(struct device *dev)
return 0;
}
-static const struct dev_pm_ops lp_gpio_pm_ops = {
- SYSTEM_SLEEP_PM_OPS(NULL, lp_gpio_resume)
- RUNTIME_PM_OPS(lp_gpio_runtime_suspend, lp_gpio_runtime_resume, NULL)
-};
+static DEFINE_SIMPLE_DEV_PM_OPS(lp_gpio_pm_ops, NULL, lp_gpio_resume);
static const struct acpi_device_id lynxpoint_gpio_acpi_match[] = {
{ "INT33C7", (kernel_ulong_t)&lptlp_soc_data },
@@ -890,10 +865,9 @@ MODULE_DEVICE_TABLE(acpi, lynxpoint_gpio_acpi_match);
static struct platform_driver lp_gpio_driver = {
.probe = lp_gpio_probe,
- .remove = lp_gpio_remove,
.driver = {
.name = "lp_gpio",
- .pm = pm_ptr(&lp_gpio_pm_ops),
+ .pm = pm_sleep_ptr(&lp_gpio_pm_ops),
.acpi_match_table = lynxpoint_gpio_acpi_match,
},
};
diff --git a/drivers/pinctrl/intel/pinctrl-merrifield.c b/drivers/pinctrl/intel/pinctrl-merrifield.c
index d809680a09..1a556f5822 100644
--- a/drivers/pinctrl/intel/pinctrl-merrifield.c
+++ b/drivers/pinctrl/intel/pinctrl-merrifield.c
@@ -6,8 +6,8 @@
* Author: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
*/
+#include <linux/array_size.h>
#include <linux/init.h>
-#include <linux/kernel.h>
#include <linux/mod_devicetable.h>
#include <linux/module.h>
#include <linux/platform_device.h>
diff --git a/drivers/pinctrl/intel/pinctrl-moorefield.c b/drivers/pinctrl/intel/pinctrl-moorefield.c
index 807a694b81..7b995fbf5c 100644
--- a/drivers/pinctrl/intel/pinctrl-moorefield.c
+++ b/drivers/pinctrl/intel/pinctrl-moorefield.c
@@ -6,8 +6,8 @@
* Author: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
*/
+#include <linux/array_size.h>
#include <linux/init.h>
-#include <linux/kernel.h>
#include <linux/mod_devicetable.h>
#include <linux/module.h>
#include <linux/platform_device.h>
diff --git a/drivers/pinctrl/mediatek/pinctrl-moore.c b/drivers/pinctrl/mediatek/pinctrl-moore.c
index 8649a2f9d3..c3d59eddd9 100644
--- a/drivers/pinctrl/mediatek/pinctrl-moore.c
+++ b/drivers/pinctrl/mediatek/pinctrl-moore.c
@@ -45,7 +45,7 @@ static int mtk_pinmux_set_mux(struct pinctrl_dev *pctldev,
struct mtk_pinctrl *hw = pinctrl_dev_get_drvdata(pctldev);
struct function_desc *func;
struct group_desc *grp;
- int i;
+ int i, err;
func = pinmux_generic_get_function(pctldev, selector);
if (!func)
@@ -67,8 +67,11 @@ static int mtk_pinmux_set_mux(struct pinctrl_dev *pctldev,
if (!desc->name)
return -ENOTSUPP;
- mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_MODE,
- pin_modes[i]);
+ err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_MODE,
+ pin_modes[i]);
+
+ if (err)
+ return err;
}
return 0;
@@ -507,17 +510,12 @@ static void mtk_gpio_set(struct gpio_chip *chip, unsigned int gpio, int value)
mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DO, !!value);
}
-static int mtk_gpio_direction_input(struct gpio_chip *chip, unsigned int gpio)
-{
- return pinctrl_gpio_direction_input(chip->base + gpio);
-}
-
static int mtk_gpio_direction_output(struct gpio_chip *chip, unsigned int gpio,
int value)
{
mtk_gpio_set(chip, gpio, value);
- return pinctrl_gpio_direction_output(chip->base + gpio);
+ return pinctrl_gpio_direction_output(chip, gpio);
}
static int mtk_gpio_to_irq(struct gpio_chip *chip, unsigned int offset)
@@ -566,7 +564,7 @@ static int mtk_build_gpiochip(struct mtk_pinctrl *hw)
chip->parent = hw->dev;
chip->request = gpiochip_generic_request;
chip->free = gpiochip_generic_free;
- chip->direction_input = mtk_gpio_direction_input;
+ chip->direction_input = pinctrl_gpio_direction_input;
chip->direction_output = mtk_gpio_direction_output;
chip->get = mtk_gpio_get;
chip->set = mtk_gpio_set;
diff --git a/drivers/pinctrl/mediatek/pinctrl-mt7981.c b/drivers/pinctrl/mediatek/pinctrl-mt7981.c
index 0fd2c0c451..7e59a44078 100644
--- a/drivers/pinctrl/mediatek/pinctrl-mt7981.c
+++ b/drivers/pinctrl/mediatek/pinctrl-mt7981.c
@@ -611,6 +611,9 @@ static int mt7981_wo0_jtag_1_funcs[] = { 5, 5, 5, 5, 5, };
static int mt7981_uart2_0_pins[] = { 4, 5, 6, 7, };
static int mt7981_uart2_0_funcs[] = { 3, 3, 3, 3, };
+static int mt7981_uart2_0_tx_rx_pins[] = { 4, 5, };
+static int mt7981_uart2_0_tx_rx_funcs[] = { 3, 3, };
+
/* GBE_LED0 */
static int mt7981_gbe_led0_pins[] = { 8, };
static int mt7981_gbe_led0_funcs[] = { 3, };
@@ -731,6 +734,9 @@ static int mt7981_uart1_0_funcs[] = { 4, 4, 4, 4, };
static int mt7981_uart1_1_pins[] = { 26, 27, 28, 29, };
static int mt7981_uart1_1_funcs[] = { 2, 2, 2, 2, };
+static int mt7981_uart1_2_pins[] = { 9, 10, };
+static int mt7981_uart1_2_funcs[] = { 2, 2, };
+
/* UART2 */
static int mt7981_uart2_1_pins[] = { 22, 23, 24, 25, };
static int mt7981_uart2_1_funcs[] = { 3, 3, 3, 3, };
@@ -805,6 +811,8 @@ static const struct group_desc mt7981_groups[] = {
PINCTRL_PIN_GROUP("wo0_jtag_0", mt7981_wo0_jtag_0),
/* @GPIO(4,7) WM_JTAG(3) */
PINCTRL_PIN_GROUP("uart2_0", mt7981_uart2_0),
+ /* @GPIO(4,5) WM_JTAG(4) */
+ PINCTRL_PIN_GROUP("uart2_0_tx_rx", mt7981_uart2_0_tx_rx),
/* @GPIO(8) GBE_LED0(3) */
PINCTRL_PIN_GROUP("gbe_led0", mt7981_gbe_led0),
/* @GPIO(4,6) PTA_EXT(4) */
@@ -861,6 +869,8 @@ static const struct group_desc mt7981_groups[] = {
PINCTRL_PIN_GROUP("uart1_0", mt7981_uart1_0),
/* @GPIO(26,29): UART1(2) */
PINCTRL_PIN_GROUP("uart1_1", mt7981_uart1_1),
+ /* @GPIO(9,10): UART1(2) */
+ PINCTRL_PIN_GROUP("uart1_2", mt7981_uart1_2),
/* @GPIO(22,25): UART1(3) */
PINCTRL_PIN_GROUP("uart2_1", mt7981_uart2_1),
/* @GPIO(22,24) PTA_EXT(4) */
@@ -922,9 +932,9 @@ static const struct group_desc mt7981_groups[] = {
*/
static const char *mt7981_wa_aice_groups[] = { "wa_aice1", "wa_aice2", "wm_aice1_1",
"wa_aice3", "wm_aice1_2", };
-static const char *mt7981_uart_groups[] = { "wm_uart_0", "uart2_0",
- "net_wo0_uart_txd_0", "net_wo0_uart_txd_1", "net_wo0_uart_txd_2",
- "uart1_0", "uart1_1", "uart2_1", "wm_aurt_1", "wm_aurt_2", "uart0", };
+static const char *mt7981_uart_groups[] = { "net_wo0_uart_txd_0", "net_wo0_uart_txd_1",
+ "net_wo0_uart_txd_2", "uart0", "uart1_0", "uart1_1", "uart1_2", "uart2_0",
+ "uart2_0_tx_rx", "uart2_1", "wm_uart_0", "wm_aurt_1", "wm_aurt_2", };
static const char *mt7981_dfd_groups[] = { "dfd", "dfd_ntrst", };
static const char *mt7981_wdt_groups[] = { "watchdog", "watchdog1", };
static const char *mt7981_pcie_groups[] = { "pcie_pereset", "pcie_clk", "pcie_wake", };
diff --git a/drivers/pinctrl/mediatek/pinctrl-mtk-common.c b/drivers/pinctrl/mediatek/pinctrl-mtk-common.c
index 74b15952b7..e79d66a041 100644
--- a/drivers/pinctrl/mediatek/pinctrl-mtk-common.c
+++ b/drivers/pinctrl/mediatek/pinctrl-mtk-common.c
@@ -808,17 +808,11 @@ static const struct pinmux_ops mtk_pmx_ops = {
.gpio_request_enable = mtk_pmx_gpio_request_enable,
};
-static int mtk_gpio_direction_input(struct gpio_chip *chip,
- unsigned offset)
-{
- return pinctrl_gpio_direction_input(chip->base + offset);
-}
-
static int mtk_gpio_direction_output(struct gpio_chip *chip,
unsigned offset, int value)
{
mtk_gpio_set(chip, offset, value);
- return pinctrl_gpio_direction_output(chip->base + offset);
+ return pinctrl_gpio_direction_output(chip, offset);
}
static int mtk_gpio_get_direction(struct gpio_chip *chip, unsigned offset)
@@ -898,7 +892,7 @@ static const struct gpio_chip mtk_gpio_chip = {
.request = gpiochip_generic_request,
.free = gpiochip_generic_free,
.get_direction = mtk_gpio_get_direction,
- .direction_input = mtk_gpio_direction_input,
+ .direction_input = pinctrl_gpio_direction_input,
.direction_output = mtk_gpio_direction_output,
.get = mtk_gpio_get,
.set = mtk_gpio_set,
diff --git a/drivers/pinctrl/mediatek/pinctrl-paris.c b/drivers/pinctrl/mediatek/pinctrl-paris.c
index 33d6c3fb79..6392f1e05d 100644
--- a/drivers/pinctrl/mediatek/pinctrl-paris.c
+++ b/drivers/pinctrl/mediatek/pinctrl-paris.c
@@ -779,9 +779,7 @@ static int mtk_pmx_set_mux(struct pinctrl_dev *pctldev,
return -EINVAL;
desc = (const struct mtk_pin_desc *)&hw->soc->pins[grp->pin];
- mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_MODE, desc_func->muxval);
-
- return 0;
+ return mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_MODE, desc_func->muxval);
}
static const struct pinmux_ops mtk_pmxops = {
@@ -918,7 +916,7 @@ static int mtk_gpio_direction_input(struct gpio_chip *chip, unsigned int gpio)
if (gpio >= hw->soc->npins)
return -EINVAL;
- return pinctrl_gpio_direction_input(chip->base + gpio);
+ return pinctrl_gpio_direction_input(chip, gpio);
}
static int mtk_gpio_direction_output(struct gpio_chip *chip, unsigned int gpio,
@@ -931,7 +929,7 @@ static int mtk_gpio_direction_output(struct gpio_chip *chip, unsigned int gpio,
mtk_gpio_set(chip, gpio, value);
- return pinctrl_gpio_direction_output(chip->base + gpio);
+ return pinctrl_gpio_direction_output(chip, gpio);
}
static int mtk_gpio_to_irq(struct gpio_chip *chip, unsigned int offset)
diff --git a/drivers/pinctrl/meson/Kconfig b/drivers/pinctrl/meson/Kconfig
index 71fa7431df..cc39789676 100644
--- a/drivers/pinctrl/meson/Kconfig
+++ b/drivers/pinctrl/meson/Kconfig
@@ -73,4 +73,10 @@ config PINCTRL_AMLOGIC_C3
select PINCTRL_MESON_AXG_PMX
default y
+config PINCTRL_AMLOGIC_T7
+ tristate "Amlogic T7 SoC pinctrl driver"
+ depends on ARM64
+ select PINCTRL_MESON_AXG_PMX
+ default y
+
endif
diff --git a/drivers/pinctrl/meson/Makefile b/drivers/pinctrl/meson/Makefile
index 7ecddf7f68..9e538b9ffb 100644
--- a/drivers/pinctrl/meson/Makefile
+++ b/drivers/pinctrl/meson/Makefile
@@ -11,3 +11,4 @@ obj-$(CONFIG_PINCTRL_MESON_G12A) += pinctrl-meson-g12a.o
obj-$(CONFIG_PINCTRL_MESON_A1) += pinctrl-meson-a1.o
obj-$(CONFIG_PINCTRL_MESON_S4) += pinctrl-meson-s4.o
obj-$(CONFIG_PINCTRL_AMLOGIC_C3) += pinctrl-amlogic-c3.o
+obj-$(CONFIG_PINCTRL_AMLOGIC_T7) += pinctrl-amlogic-t7.o
diff --git a/drivers/pinctrl/meson/pinctrl-amlogic-t7.c b/drivers/pinctrl/meson/pinctrl-amlogic-t7.c
new file mode 100644
index 0000000000..0aed5de3f0
--- /dev/null
+++ b/drivers/pinctrl/meson/pinctrl-amlogic-t7.c
@@ -0,0 +1,1611 @@
+// SPDX-License-Identifier: (GPL-2.0-only OR MIT)
+/*
+ * Pin controller and GPIO driver for Amlogic T7 SoC.
+ *
+ * Copyright (c) 2023 Amlogic, Inc. All rights reserved.
+ * Author: Huqiang Qin <huqiang.qin@amlogic.com>
+ */
+
+#include <dt-bindings/gpio/amlogic,t7-periphs-pinctrl.h>
+#include "pinctrl-meson.h"
+#include "pinctrl-meson-axg-pmx.h"
+
+static const struct pinctrl_pin_desc t7_periphs_pins[] = {
+ MESON_PIN(GPIOB_0),
+ MESON_PIN(GPIOB_1),
+ MESON_PIN(GPIOB_2),
+ MESON_PIN(GPIOB_3),
+ MESON_PIN(GPIOB_4),
+ MESON_PIN(GPIOB_5),
+ MESON_PIN(GPIOB_6),
+ MESON_PIN(GPIOB_7),
+ MESON_PIN(GPIOB_8),
+ MESON_PIN(GPIOB_9),
+ MESON_PIN(GPIOB_10),
+ MESON_PIN(GPIOB_11),
+ MESON_PIN(GPIOB_12),
+
+ MESON_PIN(GPIOC_0),
+ MESON_PIN(GPIOC_1),
+ MESON_PIN(GPIOC_2),
+ MESON_PIN(GPIOC_3),
+ MESON_PIN(GPIOC_4),
+ MESON_PIN(GPIOC_5),
+ MESON_PIN(GPIOC_6),
+
+ MESON_PIN(GPIOX_0),
+ MESON_PIN(GPIOX_1),
+ MESON_PIN(GPIOX_2),
+ MESON_PIN(GPIOX_3),
+ MESON_PIN(GPIOX_4),
+ MESON_PIN(GPIOX_5),
+ MESON_PIN(GPIOX_6),
+ MESON_PIN(GPIOX_7),
+ MESON_PIN(GPIOX_8),
+ MESON_PIN(GPIOX_9),
+ MESON_PIN(GPIOX_10),
+ MESON_PIN(GPIOX_11),
+ MESON_PIN(GPIOX_12),
+ MESON_PIN(GPIOX_13),
+ MESON_PIN(GPIOX_14),
+ MESON_PIN(GPIOX_15),
+ MESON_PIN(GPIOX_16),
+ MESON_PIN(GPIOX_17),
+ MESON_PIN(GPIOX_18),
+ MESON_PIN(GPIOX_19),
+
+ MESON_PIN(GPIOW_0),
+ MESON_PIN(GPIOW_1),
+ MESON_PIN(GPIOW_2),
+ MESON_PIN(GPIOW_3),
+ MESON_PIN(GPIOW_4),
+ MESON_PIN(GPIOW_5),
+ MESON_PIN(GPIOW_6),
+ MESON_PIN(GPIOW_7),
+ MESON_PIN(GPIOW_8),
+ MESON_PIN(GPIOW_9),
+ MESON_PIN(GPIOW_10),
+ MESON_PIN(GPIOW_11),
+ MESON_PIN(GPIOW_12),
+ MESON_PIN(GPIOW_13),
+ MESON_PIN(GPIOW_14),
+ MESON_PIN(GPIOW_15),
+ MESON_PIN(GPIOW_16),
+
+ MESON_PIN(GPIOD_0),
+ MESON_PIN(GPIOD_1),
+ MESON_PIN(GPIOD_2),
+ MESON_PIN(GPIOD_3),
+ MESON_PIN(GPIOD_4),
+ MESON_PIN(GPIOD_5),
+ MESON_PIN(GPIOD_6),
+ MESON_PIN(GPIOD_7),
+ MESON_PIN(GPIOD_8),
+ MESON_PIN(GPIOD_9),
+ MESON_PIN(GPIOD_10),
+ MESON_PIN(GPIOD_11),
+ MESON_PIN(GPIOD_12),
+
+ MESON_PIN(GPIOE_0),
+ MESON_PIN(GPIOE_1),
+ MESON_PIN(GPIOE_2),
+ MESON_PIN(GPIOE_3),
+ MESON_PIN(GPIOE_4),
+ MESON_PIN(GPIOE_5),
+ MESON_PIN(GPIOE_6),
+
+ MESON_PIN(GPIOZ_0),
+ MESON_PIN(GPIOZ_1),
+ MESON_PIN(GPIOZ_2),
+ MESON_PIN(GPIOZ_3),
+ MESON_PIN(GPIOZ_4),
+ MESON_PIN(GPIOZ_5),
+ MESON_PIN(GPIOZ_6),
+ MESON_PIN(GPIOZ_7),
+ MESON_PIN(GPIOZ_8),
+ MESON_PIN(GPIOZ_9),
+ MESON_PIN(GPIOZ_10),
+ MESON_PIN(GPIOZ_11),
+ MESON_PIN(GPIOZ_12),
+ MESON_PIN(GPIOZ_13),
+
+ MESON_PIN(GPIOT_0),
+ MESON_PIN(GPIOT_1),
+ MESON_PIN(GPIOT_2),
+ MESON_PIN(GPIOT_3),
+ MESON_PIN(GPIOT_4),
+ MESON_PIN(GPIOT_5),
+ MESON_PIN(GPIOT_6),
+ MESON_PIN(GPIOT_7),
+ MESON_PIN(GPIOT_8),
+ MESON_PIN(GPIOT_9),
+ MESON_PIN(GPIOT_10),
+ MESON_PIN(GPIOT_11),
+ MESON_PIN(GPIOT_12),
+ MESON_PIN(GPIOT_13),
+ MESON_PIN(GPIOT_14),
+ MESON_PIN(GPIOT_15),
+ MESON_PIN(GPIOT_16),
+ MESON_PIN(GPIOT_17),
+ MESON_PIN(GPIOT_18),
+ MESON_PIN(GPIOT_19),
+ MESON_PIN(GPIOT_20),
+ MESON_PIN(GPIOT_21),
+ MESON_PIN(GPIOT_22),
+ MESON_PIN(GPIOT_23),
+
+ MESON_PIN(GPIOM_0),
+ MESON_PIN(GPIOM_1),
+ MESON_PIN(GPIOM_2),
+ MESON_PIN(GPIOM_3),
+ MESON_PIN(GPIOM_4),
+ MESON_PIN(GPIOM_5),
+ MESON_PIN(GPIOM_6),
+ MESON_PIN(GPIOM_7),
+ MESON_PIN(GPIOM_8),
+ MESON_PIN(GPIOM_9),
+ MESON_PIN(GPIOM_10),
+ MESON_PIN(GPIOM_11),
+ MESON_PIN(GPIOM_12),
+ MESON_PIN(GPIOM_13),
+
+ MESON_PIN(GPIOY_0),
+ MESON_PIN(GPIOY_1),
+ MESON_PIN(GPIOY_2),
+ MESON_PIN(GPIOY_3),
+ MESON_PIN(GPIOY_4),
+ MESON_PIN(GPIOY_5),
+ MESON_PIN(GPIOY_6),
+ MESON_PIN(GPIOY_7),
+ MESON_PIN(GPIOY_8),
+ MESON_PIN(GPIOY_9),
+ MESON_PIN(GPIOY_10),
+ MESON_PIN(GPIOY_11),
+ MESON_PIN(GPIOY_12),
+ MESON_PIN(GPIOY_13),
+ MESON_PIN(GPIOY_14),
+ MESON_PIN(GPIOY_15),
+ MESON_PIN(GPIOY_16),
+ MESON_PIN(GPIOY_17),
+ MESON_PIN(GPIOY_18),
+
+ MESON_PIN(GPIOH_0),
+ MESON_PIN(GPIOH_1),
+ MESON_PIN(GPIOH_2),
+ MESON_PIN(GPIOH_3),
+ MESON_PIN(GPIOH_4),
+ MESON_PIN(GPIOH_5),
+ MESON_PIN(GPIOH_6),
+ MESON_PIN(GPIOH_7),
+
+ MESON_PIN(GPIO_TEST_N),
+};
+
+/* Bank B func1 */
+static const unsigned int emmc_nand_d0_pins[] = { GPIOB_0 };
+static const unsigned int emmc_nand_d1_pins[] = { GPIOB_1 };
+static const unsigned int emmc_nand_d2_pins[] = { GPIOB_2 };
+static const unsigned int emmc_nand_d3_pins[] = { GPIOB_3 };
+static const unsigned int emmc_nand_d4_pins[] = { GPIOB_4 };
+static const unsigned int emmc_nand_d5_pins[] = { GPIOB_5 };
+static const unsigned int emmc_nand_d6_pins[] = { GPIOB_6 };
+static const unsigned int emmc_nand_d7_pins[] = { GPIOB_7 };
+static const unsigned int emmc_clk_pins[] = { GPIOB_8 };
+static const unsigned int emmc_cmd_pins[] = { GPIOB_10 };
+static const unsigned int emmc_nand_ds_pins[] = { GPIOB_11 };
+
+/* Bank B func2 */
+static const unsigned int nor_hold_pins[] = { GPIOB_3 };
+static const unsigned int nor_d_pins[] = { GPIOB_4 };
+static const unsigned int nor_q_pins[] = { GPIOB_5 };
+static const unsigned int nor_c_pins[] = { GPIOB_6 };
+static const unsigned int nor_wp_pins[] = { GPIOB_7 };
+static const unsigned int nor_cs_pins[] = { GPIOB_12 };
+
+/* Bank C func1 */
+static const unsigned int sdcard_d0_pins[] = { GPIOC_0 };
+static const unsigned int sdcard_d1_pins[] = { GPIOC_1 };
+static const unsigned int sdcard_d2_pins[] = { GPIOC_2 };
+static const unsigned int sdcard_d3_pins[] = { GPIOC_3 };
+static const unsigned int sdcard_clk_pins[] = { GPIOC_4 };
+static const unsigned int sdcard_cmd_pins[] = { GPIOC_5 };
+static const unsigned int gen_clk_out_c_pins[] = { GPIOC_6 };
+
+/* Bank C func2 */
+static const unsigned int jtag_b_tdo_pins[] = { GPIOC_0 };
+static const unsigned int jtag_b_tdi_pins[] = { GPIOC_1 };
+static const unsigned int uart_ao_a_rx_c_pins[] = { GPIOC_2 };
+static const unsigned int uart_ao_a_tx_c_pins[] = { GPIOC_3 };
+static const unsigned int jtag_b_clk_pins[] = { GPIOC_4 };
+static const unsigned int jtag_b_tms_pins[] = { GPIOC_5 };
+
+/* Bank C func3 */
+static const unsigned int spi1_mosi_c_pins[] = { GPIOC_0 };
+static const unsigned int spi1_miso_c_pins[] = { GPIOC_1 };
+static const unsigned int spi1_sclk_c_pins[] = { GPIOC_2 };
+static const unsigned int spi1_ss0_c_pins[] = { GPIOC_3 };
+
+/* Bank X func1 */
+static const unsigned int sdio_d0_pins[] = { GPIOX_0 };
+static const unsigned int sdio_d1_pins[] = { GPIOX_1 };
+static const unsigned int sdio_d2_pins[] = { GPIOX_2 };
+static const unsigned int sdio_d3_pins[] = { GPIOX_3 };
+static const unsigned int sdio_clk_pins[] = { GPIOX_4 };
+static const unsigned int sdio_cmd_pins[] = { GPIOX_5 };
+static const unsigned int pwm_b_pins[] = { GPIOX_6 };
+static const unsigned int pwm_c_pins[] = { GPIOX_7 };
+static const unsigned int tdm_d0_pins[] = { GPIOX_8 };
+static const unsigned int tdm_d1_pins[] = { GPIOX_9 };
+static const unsigned int tdm_fs0_pins[] = { GPIOX_10 };
+static const unsigned int tdm_sclk0_pins[] = { GPIOX_11 };
+static const unsigned int uart_c_tx_pins[] = { GPIOX_12 };
+static const unsigned int uart_c_rx_pins[] = { GPIOX_13 };
+static const unsigned int uart_c_cts_pins[] = { GPIOX_14 };
+static const unsigned int uart_c_rts_pins[] = { GPIOX_15 };
+static const unsigned int pwm_a_pins[] = { GPIOX_16 };
+static const unsigned int i2c2_sda_x_pins[] = { GPIOX_17 };
+static const unsigned int i2c2_sck_x_pins[] = { GPIOX_18 };
+static const unsigned int pwm_d_pins[] = { GPIOX_19 };
+
+/* Bank X func2 */
+static const unsigned int clk12_24_x_pins[] = { GPIOX_14 };
+
+/* Bank W func1 */
+static const unsigned int hdmirx_a_hpd_pins[] = { GPIOW_0 };
+static const unsigned int hdmirx_a_det_pins[] = { GPIOW_1 };
+static const unsigned int hdmirx_a_sda_pins[] = { GPIOW_2 };
+static const unsigned int hdmirx_a_sck_pins[] = { GPIOW_3 };
+static const unsigned int hdmirx_c_hpd_pins[] = { GPIOW_4 };
+static const unsigned int hdmirx_c_det_pins[] = { GPIOW_5 };
+static const unsigned int hdmirx_c_sda_pins[] = { GPIOW_6 };
+static const unsigned int hdmirx_c_sck_pins[] = { GPIOW_7 };
+static const unsigned int hdmirx_b_hpd_pins[] = { GPIOW_8 };
+static const unsigned int hdmirx_b_det_pins[] = { GPIOW_9 };
+static const unsigned int hdmirx_b_sda_pins[] = { GPIOW_10 };
+static const unsigned int hdmirx_b_sck_pins[] = { GPIOW_11 };
+static const unsigned int cec_a_pins[] = { GPIOW_12 };
+static const unsigned int hdmitx_sda_w13_pins[] = { GPIOW_13 };
+static const unsigned int hdmitx_sck_w14_pins[] = { GPIOW_14 };
+static const unsigned int hdmitx_hpd_in_pins[] = { GPIOW_15 };
+static const unsigned int cec_b_pins[] = { GPIOW_16 };
+
+/* Bank W func2 */
+static const unsigned int uart_ao_a_tx_w2_pins[] = { GPIOW_2 };
+static const unsigned int uart_ao_a_rx_w3_pins[] = { GPIOW_3 };
+static const unsigned int uart_ao_a_tx_w6_pins[] = { GPIOW_6 };
+static const unsigned int uart_ao_a_rx_w7_pins[] = { GPIOW_7 };
+static const unsigned int uart_ao_a_tx_w10_pins[] = { GPIOW_10 };
+static const unsigned int uart_ao_a_rx_w11_pins[] = { GPIOW_11 };
+
+/* Bank W func3 */
+static const unsigned int hdmitx_sda_w2_pins[] = { GPIOW_2 };
+static const unsigned int hdmitx_sck_w3_pins[] = { GPIOW_3 };
+
+/* Bank D func1 */
+static const unsigned int uart_ao_a_tx_d0_pins[] = { GPIOD_0 };
+static const unsigned int uart_ao_a_rx_d1_pins[] = { GPIOD_1 };
+static const unsigned int i2c0_ao_sck_d_pins[] = { GPIOD_2 };
+static const unsigned int i2c0_ao_sda_d_pins[] = { GPIOD_3 };
+static const unsigned int remote_out_d4_pins[] = { GPIOD_4 };
+static const unsigned int remote_in_pins[] = { GPIOD_5 };
+static const unsigned int jtag_a_clk_pins[] = { GPIOD_6 };
+static const unsigned int jtag_a_tms_pins[] = { GPIOD_7 };
+static const unsigned int jtag_a_tdi_pins[] = { GPIOD_8 };
+static const unsigned int jtag_a_tdo_pins[] = { GPIOD_9 };
+static const unsigned int gen_clk_out_d_pins[] = { GPIOD_10 };
+static const unsigned int pwm_ao_g_d11_pins[] = { GPIOD_11 };
+static const unsigned int wd_rsto_pins[] = { GPIOD_12 };
+
+/* Bank D func2 */
+static const unsigned int i2c0_slave_ao_sck_pins[] = { GPIOD_2 };
+static const unsigned int i2c0_slave_ao_sda_pins[] = { GPIOD_3 };
+static const unsigned int rtc_clk_in_pins[] = { GPIOD_4 };
+static const unsigned int pwm_ao_h_d5_pins[] = { GPIOD_5 };
+static const unsigned int pwm_ao_c_d_pins[] = { GPIOD_6 };
+static const unsigned int pwm_ao_g_d7_pins[] = { GPIOD_7 };
+static const unsigned int spdif_out_d_pins[] = { GPIOD_8 };
+static const unsigned int spdif_in_d_pins[] = { GPIOD_9 };
+static const unsigned int pwm_ao_h_d10_pins[] = { GPIOD_10 };
+
+/* Bank D func3 */
+static const unsigned int uart_ao_b_tx_pins[] = { GPIOD_2 };
+static const unsigned int uart_ao_b_rx_pins[] = { GPIOD_3 };
+static const unsigned int uart_ao_b_cts_pins[] = { GPIOD_4 };
+static const unsigned int pwm_ao_c_hiz_pins[] = { GPIOD_6 };
+static const unsigned int pwm_ao_g_hiz_pins[] = { GPIOD_7 };
+static const unsigned int uart_ao_b_rts_pins[] = { GPIOD_10 };
+
+/* Bank D func4 */
+static const unsigned int remote_out_d6_pins[] = { GPIOD_6 };
+
+/* Bank E func1 */
+static const unsigned int pwm_ao_a_pins[] = { GPIOE_0 };
+static const unsigned int pwm_ao_b_pins[] = { GPIOE_1 };
+static const unsigned int pwm_ao_c_e_pins[] = { GPIOE_2 };
+static const unsigned int pwm_ao_d_pins[] = { GPIOE_3 };
+static const unsigned int pwm_ao_e_pins[] = { GPIOE_4 };
+static const unsigned int pwm_ao_f_pins[] = { GPIOE_5 };
+static const unsigned int pwm_ao_g_e_pins[] = { GPIOE_6 };
+
+/* Bank E func2 */
+static const unsigned int i2c0_ao_sck_e_pins[] = { GPIOE_0 };
+static const unsigned int i2c0_ao_sda_e_pins[] = { GPIOE_1 };
+static const unsigned int clk25m_pins[] = { GPIOE_2 };
+static const unsigned int i2c1_ao_sck_pins[] = { GPIOE_3 };
+static const unsigned int i2c1_ao_sda_pins[] = { GPIOE_4 };
+static const unsigned int rtc_clk_out_pins[] = { GPIOD_5 };
+
+/* Bank E func3 */
+static const unsigned int clk12_24_e_pins[] = { GPIOE_4 };
+
+/* Bank Z func1 */
+static const unsigned int eth_mdio_pins[] = { GPIOZ_0 };
+static const unsigned int eth_mdc_pins[] = { GPIOZ_1 };
+static const unsigned int eth_rgmii_rx_clk_pins[] = { GPIOZ_2 };
+static const unsigned int eth_rx_dv_pins[] = { GPIOZ_3 };
+static const unsigned int eth_rxd0_pins[] = { GPIOZ_4 };
+static const unsigned int eth_rxd1_pins[] = { GPIOZ_5 };
+static const unsigned int eth_rxd2_rgmii_pins[] = { GPIOZ_6 };
+static const unsigned int eth_rxd3_rgmii_pins[] = { GPIOZ_7 };
+static const unsigned int eth_rgmii_tx_clk_pins[] = { GPIOZ_8 };
+static const unsigned int eth_txen_pins[] = { GPIOZ_9 };
+static const unsigned int eth_txd0_pins[] = { GPIOZ_10 };
+static const unsigned int eth_txd1_pins[] = { GPIOZ_11 };
+static const unsigned int eth_txd2_rgmii_pins[] = { GPIOZ_12 };
+static const unsigned int eth_txd3_rgmii_pins[] = { GPIOZ_13 };
+
+/* Bank Z func2 */
+static const unsigned int iso7816_clk_z_pins[] = { GPIOZ_0 };
+static const unsigned int iso7816_data_z_pins[] = { GPIOZ_1 };
+static const unsigned int tsin_b_valid_pins[] = { GPIOZ_2 };
+static const unsigned int tsin_b_sop_pins[] = { GPIOZ_3 };
+static const unsigned int tsin_b_din0_pins[] = { GPIOZ_4 };
+static const unsigned int tsin_b_clk_pins[] = { GPIOZ_5 };
+static const unsigned int tsin_b_fail_pins[] = { GPIOZ_6 };
+static const unsigned int tsin_b_din1_pins[] = { GPIOZ_7 };
+static const unsigned int tsin_b_din2_pins[] = { GPIOZ_8 };
+static const unsigned int tsin_b_din3_pins[] = { GPIOZ_9 };
+static const unsigned int tsin_b_din4_pins[] = { GPIOZ_10 };
+static const unsigned int tsin_b_din5_pins[] = { GPIOZ_11 };
+static const unsigned int tsin_b_din6_pins[] = { GPIOZ_12 };
+static const unsigned int tsin_b_din7_pins[] = { GPIOZ_13 };
+
+/* Bank Z func3 */
+static const unsigned int tsin_c_z_valid_pins[] = { GPIOZ_6 };
+static const unsigned int tsin_c_z_sop_pins[] = { GPIOZ_7 };
+static const unsigned int tsin_c_z_din0_pins[] = { GPIOZ_8 };
+static const unsigned int tsin_c_z_clk_pins[] = { GPIOZ_9 };
+static const unsigned int tsin_d_z_valid_pins[] = { GPIOZ_10 };
+static const unsigned int tsin_d_z_sop_pins[] = { GPIOZ_11 };
+static const unsigned int tsin_d_z_din0_pins[] = { GPIOZ_12 };
+static const unsigned int tsin_d_z_clk_pins[] = { GPIOZ_13 };
+
+/* Bank Z func4 */
+static const unsigned int spi4_mosi_pins[] = { GPIOZ_0 };
+static const unsigned int spi4_miso_pins[] = { GPIOZ_1 };
+static const unsigned int spi4_sclk_pins[] = { GPIOZ_2 };
+static const unsigned int spi4_ss0_pins[] = { GPIOZ_3 };
+static const unsigned int spi5_mosi_pins[] = { GPIOZ_4 };
+static const unsigned int spi5_miso_pins[] = { GPIOZ_5 };
+static const unsigned int spi5_sclk_pins[] = { GPIOZ_6 };
+static const unsigned int spi5_ss0_pins[] = { GPIOZ_7 };
+
+/* Bank T func1 */
+static const unsigned int mclk1_pins[] = { GPIOT_0 };
+static const unsigned int tdm_sclk1_pins[] = { GPIOT_1 };
+static const unsigned int tdm_fs1_pins[] = { GPIOT_2 };
+static const unsigned int tdm_d2_pins[] = { GPIOT_3 };
+static const unsigned int tdm_d3_pins[] = { GPIOT_4 };
+static const unsigned int tdm_d4_pins[] = { GPIOT_5 };
+static const unsigned int tdm_d5_pins[] = { GPIOT_6 };
+static const unsigned int tdm_d6_pins[] = { GPIOT_7 };
+static const unsigned int tdm_d7_pins[] = { GPIOT_8 };
+static const unsigned int tdm_d8_pins[] = { GPIOT_9 };
+static const unsigned int tdm_d9_pins[] = { GPIOT_10 };
+static const unsigned int tdm_d10_pins[] = { GPIOT_11 };
+static const unsigned int tdm_d11_pins[] = { GPIOT_12 };
+static const unsigned int mclk2_pins[] = { GPIOT_13 };
+static const unsigned int tdm_sclk2_pins[] = { GPIOT_14 };
+static const unsigned int tdm_fs2_pins[] = { GPIOT_15 };
+static const unsigned int i2c1_sck_pins[] = { GPIOT_16 };
+static const unsigned int i2c1_sda_pins[] = { GPIOT_17 };
+static const unsigned int spi0_mosi_pins[] = { GPIOT_18 };
+static const unsigned int spi0_miso_pins[] = { GPIOT_19 };
+static const unsigned int spi0_sclk_pins[] = { GPIOT_20 };
+static const unsigned int spi0_ss0_pins[] = { GPIOT_21 };
+static const unsigned int spi0_ss1_pins[] = { GPIOT_22 };
+static const unsigned int spi0_ss2_pins[] = { GPIOT_23 };
+
+/* Bank T func2 */
+static const unsigned int spdif_in_t_pins[] = { GPIOT_3 };
+static const unsigned int spdif_out_t_pins[] = { GPIOT_4 };
+static const unsigned int iso7816_clk_t_pins[] = { GPIOT_5 };
+static const unsigned int iso7816_data_t_pins[] = { GPIOT_6 };
+static const unsigned int tsin_a_sop_t_pins[] = { GPIOT_7 };
+static const unsigned int tsin_a_din0_t_pins[] = { GPIOT_8 };
+static const unsigned int tsin_a_clk_t_pins[] = { GPIOT_9 };
+static const unsigned int tsin_a_valid_t_pins[] = { GPIOT_10 };
+static const unsigned int i2c0_sck_t_pins[] = { GPIOT_20 };
+static const unsigned int i2c0_sda_t_pins[] = { GPIOT_21 };
+static const unsigned int i2c2_sck_t_pins[] = { GPIOT_22 };
+static const unsigned int i2c2_sda_t_pins[] = { GPIOT_23 };
+
+/* Bank T func3 */
+static const unsigned int spi3_mosi_pins[] = { GPIOT_6 };
+static const unsigned int spi3_miso_pins[] = { GPIOT_7 };
+static const unsigned int spi3_sclk_pins[] = { GPIOT_8 };
+static const unsigned int spi3_ss0_pins[] = { GPIOT_9 };
+
+/* Bank M func1 */
+static const unsigned int tdm_d12_pins[] = { GPIOM_0 };
+static const unsigned int tdm_d13_pins[] = { GPIOM_1 };
+static const unsigned int tdm_d14_pins[] = { GPIOM_2 };
+static const unsigned int tdm_d15_pins[] = { GPIOM_3 };
+static const unsigned int tdm_sclk3_pins[] = { GPIOM_4 };
+static const unsigned int tdm_fs3_pins[] = { GPIOM_5 };
+static const unsigned int i2c3_sda_m_pins[] = { GPIOM_6 };
+static const unsigned int i2c3_sck_m_pins[] = { GPIOM_7 };
+static const unsigned int spi1_mosi_m_pins[] = { GPIOM_8 };
+static const unsigned int spi1_miso_m_pins[] = { GPIOM_9 };
+static const unsigned int spi1_sclk_m_pins[] = { GPIOM_10 };
+static const unsigned int spi1_ss0_m_pins[] = { GPIOM_11 };
+static const unsigned int spi1_ss1_m_pins[] = { GPIOM_12 };
+static const unsigned int spi1_ss2_m_pins[] = { GPIOM_13 };
+
+/* Bank M func2 */
+static const unsigned int pdm_din1_m0_pins[] = { GPIOM_0 };
+static const unsigned int pdm_din2_pins[] = { GPIOM_1 };
+static const unsigned int pdm_din3_pins[] = { GPIOM_2 };
+static const unsigned int pdm_dclk_pins[] = { GPIOM_3 };
+static const unsigned int pdm_din0_pins[] = { GPIOM_4 };
+static const unsigned int pdm_din1_m5_pins[] = { GPIOM_5 };
+static const unsigned int uart_d_tx_m_pins[] = { GPIOM_8 };
+static const unsigned int uart_d_rx_m_pins[] = { GPIOM_9 };
+static const unsigned int uart_d_cts_m_pins[] = { GPIOM_10 };
+static const unsigned int uart_d_rts_m_pins[] = { GPIOM_11 };
+static const unsigned int i2c2_sda_m_pins[] = { GPIOM_12 };
+static const unsigned int i2c2_sck_m_pins[] = { GPIOM_13 };
+
+/* Bank Y func1 */
+static const unsigned int spi2_mosi_pins[] = { GPIOY_0 };
+static const unsigned int spi2_miso_pins[] = { GPIOY_1 };
+static const unsigned int spi2_sclk_pins[] = { GPIOY_2 };
+static const unsigned int spi2_ss0_pins[] = { GPIOY_3 };
+static const unsigned int spi2_ss1_pins[] = { GPIOY_4 };
+static const unsigned int spi2_ss2_pins[] = { GPIOY_5 };
+static const unsigned int uart_e_tx_pins[] = { GPIOY_6 };
+static const unsigned int uart_e_rx_pins[] = { GPIOY_7 };
+static const unsigned int uart_e_cts_pins[] = { GPIOY_8 };
+static const unsigned int uart_e_rts_pins[] = { GPIOY_9 };
+static const unsigned int uart_d_cts_y_pins[] = { GPIOY_10 };
+static const unsigned int uart_d_rts_y_pins[] = { GPIOY_11 };
+static const unsigned int uart_d_tx_y_pins[] = { GPIOY_12 };
+static const unsigned int uart_d_rx_y_pins[] = { GPIOY_13 };
+static const unsigned int i2c4_sck_y_pins[] = { GPIOY_15 };
+static const unsigned int i2c4_sda_y_pins[] = { GPIOY_16 };
+static const unsigned int i2c5_sck_pins[] = { GPIOY_17 };
+static const unsigned int i2c5_sda_pins[] = { GPIOY_18 };
+
+/* Bank Y func2 */
+static const unsigned int tsin_c_y_sop_pins[] = { GPIOY_4 };
+static const unsigned int tsin_c_y_din0_pins[] = { GPIOY_5 };
+static const unsigned int tsin_c_y_clk_pins[] = { GPIOY_6 };
+static const unsigned int tsin_c_y_valid_pins[] = { GPIOY_7 };
+static const unsigned int tsin_d_y_sop_pins[] = { GPIOY_8 };
+static const unsigned int tsin_d_y_din0_pins[] = { GPIOY_9 };
+static const unsigned int tsin_d_y_clk_pins[] = { GPIOY_10 };
+static const unsigned int tsin_d_y_valid_pins[] = { GPIOY_11 };
+static const unsigned int pcieck_reqn_y_pins[] = { GPIOY_18 };
+
+/* Bank Y func3 */
+static const unsigned int pwm_e_pins[] = { GPIOY_1 };
+static const unsigned int hsync_pins[] = { GPIOY_4 };
+static const unsigned int vsync_pins[] = { GPIOY_5 };
+static const unsigned int pwm_f_pins[] = { GPIOY_8 };
+static const unsigned int sync_3d_out_pins[] = { GPIOY_9 };
+static const unsigned int vx1_a_htpdn_pins[] = { GPIOY_10 };
+static const unsigned int vx1_b_htpdn_pins[] = { GPIOY_11 };
+static const unsigned int vx1_a_lockn_pins[] = { GPIOY_12 };
+static const unsigned int vx1_b_lockn_pins[] = { GPIOY_13 };
+static const unsigned int pwm_vs_y_pins[] = { GPIOY_14 };
+
+/* Bank Y func4 */
+static const unsigned int edp_a_hpd_pins[] = { GPIOY_10 };
+static const unsigned int edp_b_hpd_pins[] = { GPIOY_11 };
+
+/* Bank H func1 */
+static const unsigned int mic_mute_key_pins[] = { GPIOH_0 };
+static const unsigned int mic_mute_led_pins[] = { GPIOH_1 };
+static const unsigned int i2c3_sck_h_pins[] = { GPIOH_2 };
+static const unsigned int i2c3_sda_h_pins[] = { GPIOH_3 };
+static const unsigned int i2c4_sck_h_pins[] = { GPIOH_4 };
+static const unsigned int i2c4_sda_h_pins[] = { GPIOH_5 };
+static const unsigned int eth_link_led_pins[] = { GPIOH_6 };
+static const unsigned int eth_act_led_pins[] = { GPIOH_7 };
+
+/* Bank H func2 */
+static const unsigned int pwm_vs_h_pins[] = { GPIOH_1 };
+static const unsigned int uart_f_tx_pins[] = { GPIOH_2 };
+static const unsigned int uart_f_rx_pins[] = { GPIOH_3 };
+static const unsigned int uart_f_cts_pins[] = { GPIOH_4 };
+static const unsigned int uart_f_rts_pins[] = { GPIOH_5 };
+static const unsigned int i2c0_sda_h_pins[] = { GPIOH_6 };
+static const unsigned int i2c0_sck_h_pins[] = { GPIOH_7 };
+
+/* Bank H func3 */
+static const unsigned int pcieck_reqn_h_pins[] = { GPIOH_2 };
+
+static struct meson_pmx_group t7_periphs_groups[] = {
+ GPIO_GROUP(GPIOB_0),
+ GPIO_GROUP(GPIOB_1),
+ GPIO_GROUP(GPIOB_2),
+ GPIO_GROUP(GPIOB_3),
+ GPIO_GROUP(GPIOB_4),
+ GPIO_GROUP(GPIOB_5),
+ GPIO_GROUP(GPIOB_6),
+ GPIO_GROUP(GPIOB_7),
+ GPIO_GROUP(GPIOB_8),
+ GPIO_GROUP(GPIOB_9),
+ GPIO_GROUP(GPIOB_10),
+ GPIO_GROUP(GPIOB_11),
+ GPIO_GROUP(GPIOB_12),
+
+ GPIO_GROUP(GPIOC_0),
+ GPIO_GROUP(GPIOC_1),
+ GPIO_GROUP(GPIOC_2),
+ GPIO_GROUP(GPIOC_3),
+ GPIO_GROUP(GPIOC_4),
+ GPIO_GROUP(GPIOC_5),
+ GPIO_GROUP(GPIOC_6),
+
+ GPIO_GROUP(GPIOX_0),
+ GPIO_GROUP(GPIOX_1),
+ GPIO_GROUP(GPIOX_2),
+ GPIO_GROUP(GPIOX_3),
+ GPIO_GROUP(GPIOX_4),
+ GPIO_GROUP(GPIOX_5),
+ GPIO_GROUP(GPIOX_6),
+ GPIO_GROUP(GPIOX_7),
+ GPIO_GROUP(GPIOX_8),
+ GPIO_GROUP(GPIOX_9),
+ GPIO_GROUP(GPIOX_10),
+ GPIO_GROUP(GPIOX_11),
+ GPIO_GROUP(GPIOX_12),
+ GPIO_GROUP(GPIOX_13),
+ GPIO_GROUP(GPIOX_14),
+ GPIO_GROUP(GPIOX_15),
+ GPIO_GROUP(GPIOX_16),
+ GPIO_GROUP(GPIOX_17),
+ GPIO_GROUP(GPIOX_18),
+ GPIO_GROUP(GPIOX_19),
+
+ GPIO_GROUP(GPIOW_0),
+ GPIO_GROUP(GPIOW_1),
+ GPIO_GROUP(GPIOW_2),
+ GPIO_GROUP(GPIOW_3),
+ GPIO_GROUP(GPIOW_4),
+ GPIO_GROUP(GPIOW_5),
+ GPIO_GROUP(GPIOW_6),
+ GPIO_GROUP(GPIOW_7),
+ GPIO_GROUP(GPIOW_8),
+ GPIO_GROUP(GPIOW_9),
+ GPIO_GROUP(GPIOW_10),
+ GPIO_GROUP(GPIOW_11),
+ GPIO_GROUP(GPIOW_12),
+ GPIO_GROUP(GPIOW_13),
+ GPIO_GROUP(GPIOW_14),
+ GPIO_GROUP(GPIOW_15),
+ GPIO_GROUP(GPIOW_16),
+
+ GPIO_GROUP(GPIOD_0),
+ GPIO_GROUP(GPIOD_1),
+ GPIO_GROUP(GPIOD_2),
+ GPIO_GROUP(GPIOD_3),
+ GPIO_GROUP(GPIOD_4),
+ GPIO_GROUP(GPIOD_5),
+ GPIO_GROUP(GPIOD_6),
+ GPIO_GROUP(GPIOD_7),
+ GPIO_GROUP(GPIOD_8),
+ GPIO_GROUP(GPIOD_9),
+ GPIO_GROUP(GPIOD_10),
+ GPIO_GROUP(GPIOD_11),
+ GPIO_GROUP(GPIOD_12),
+
+ GPIO_GROUP(GPIOE_0),
+ GPIO_GROUP(GPIOE_1),
+ GPIO_GROUP(GPIOE_2),
+ GPIO_GROUP(GPIOE_3),
+ GPIO_GROUP(GPIOE_4),
+ GPIO_GROUP(GPIOE_5),
+ GPIO_GROUP(GPIOE_6),
+
+ GPIO_GROUP(GPIOZ_0),
+ GPIO_GROUP(GPIOZ_1),
+ GPIO_GROUP(GPIOZ_2),
+ GPIO_GROUP(GPIOZ_3),
+ GPIO_GROUP(GPIOZ_4),
+ GPIO_GROUP(GPIOZ_5),
+ GPIO_GROUP(GPIOZ_6),
+ GPIO_GROUP(GPIOZ_7),
+ GPIO_GROUP(GPIOZ_8),
+ GPIO_GROUP(GPIOZ_9),
+ GPIO_GROUP(GPIOZ_10),
+ GPIO_GROUP(GPIOZ_11),
+ GPIO_GROUP(GPIOZ_12),
+ GPIO_GROUP(GPIOZ_13),
+
+ GPIO_GROUP(GPIOT_0),
+ GPIO_GROUP(GPIOT_1),
+ GPIO_GROUP(GPIOT_2),
+ GPIO_GROUP(GPIOT_3),
+ GPIO_GROUP(GPIOT_4),
+ GPIO_GROUP(GPIOT_5),
+ GPIO_GROUP(GPIOT_6),
+ GPIO_GROUP(GPIOT_7),
+ GPIO_GROUP(GPIOT_8),
+ GPIO_GROUP(GPIOT_9),
+ GPIO_GROUP(GPIOT_10),
+ GPIO_GROUP(GPIOT_11),
+ GPIO_GROUP(GPIOT_12),
+ GPIO_GROUP(GPIOT_13),
+ GPIO_GROUP(GPIOT_14),
+ GPIO_GROUP(GPIOT_15),
+ GPIO_GROUP(GPIOT_16),
+ GPIO_GROUP(GPIOT_17),
+ GPIO_GROUP(GPIOT_18),
+ GPIO_GROUP(GPIOT_19),
+ GPIO_GROUP(GPIOT_20),
+ GPIO_GROUP(GPIOT_21),
+ GPIO_GROUP(GPIOT_22),
+ GPIO_GROUP(GPIOT_23),
+
+ GPIO_GROUP(GPIOM_0),
+ GPIO_GROUP(GPIOM_1),
+ GPIO_GROUP(GPIOM_2),
+ GPIO_GROUP(GPIOM_3),
+ GPIO_GROUP(GPIOM_4),
+ GPIO_GROUP(GPIOM_5),
+ GPIO_GROUP(GPIOM_6),
+ GPIO_GROUP(GPIOM_7),
+ GPIO_GROUP(GPIOM_8),
+ GPIO_GROUP(GPIOM_9),
+ GPIO_GROUP(GPIOM_10),
+ GPIO_GROUP(GPIOM_11),
+ GPIO_GROUP(GPIOM_12),
+ GPIO_GROUP(GPIOM_13),
+
+ GPIO_GROUP(GPIOY_0),
+ GPIO_GROUP(GPIOY_1),
+ GPIO_GROUP(GPIOY_2),
+ GPIO_GROUP(GPIOY_3),
+ GPIO_GROUP(GPIOY_4),
+ GPIO_GROUP(GPIOY_5),
+ GPIO_GROUP(GPIOY_6),
+ GPIO_GROUP(GPIOY_7),
+ GPIO_GROUP(GPIOY_8),
+ GPIO_GROUP(GPIOY_9),
+ GPIO_GROUP(GPIOY_10),
+ GPIO_GROUP(GPIOY_11),
+ GPIO_GROUP(GPIOY_12),
+ GPIO_GROUP(GPIOY_13),
+ GPIO_GROUP(GPIOY_14),
+ GPIO_GROUP(GPIOY_15),
+ GPIO_GROUP(GPIOY_16),
+ GPIO_GROUP(GPIOY_17),
+ GPIO_GROUP(GPIOY_18),
+
+ GPIO_GROUP(GPIOH_0),
+ GPIO_GROUP(GPIOH_1),
+ GPIO_GROUP(GPIOH_2),
+ GPIO_GROUP(GPIOH_3),
+ GPIO_GROUP(GPIOH_4),
+ GPIO_GROUP(GPIOH_5),
+ GPIO_GROUP(GPIOH_6),
+ GPIO_GROUP(GPIOH_7),
+ GPIO_GROUP(GPIO_TEST_N),
+
+ /* Bank B func1 */
+ GROUP(emmc_nand_d0, 1),
+ GROUP(emmc_nand_d1, 1),
+ GROUP(emmc_nand_d2, 1),
+ GROUP(emmc_nand_d3, 1),
+ GROUP(emmc_nand_d4, 1),
+ GROUP(emmc_nand_d5, 1),
+ GROUP(emmc_nand_d6, 1),
+ GROUP(emmc_nand_d7, 1),
+ GROUP(emmc_clk, 1),
+ GROUP(emmc_cmd, 1),
+ GROUP(emmc_nand_ds, 1),
+
+ /* Bank B func1 */
+ GROUP(nor_hold, 2),
+ GROUP(nor_d, 2),
+ GROUP(nor_q, 2),
+ GROUP(nor_c, 2),
+ GROUP(nor_wp, 2),
+ GROUP(nor_cs, 2),
+
+ /* Bank C func1 */
+ GROUP(sdcard_d0, 1),
+ GROUP(sdcard_d1, 1),
+ GROUP(sdcard_d2, 1),
+ GROUP(sdcard_d3, 1),
+ GROUP(sdcard_clk, 1),
+ GROUP(sdcard_cmd, 1),
+ GROUP(gen_clk_out_c, 1),
+
+ /* Bank C func2 */
+ GROUP(jtag_b_tdo, 2),
+ GROUP(jtag_b_tdi, 2),
+ GROUP(uart_ao_a_rx_c, 2),
+ GROUP(uart_ao_a_tx_c, 2),
+ GROUP(jtag_b_clk, 2),
+ GROUP(jtag_b_tms, 2),
+
+ /* Bank C func3 */
+ GROUP(spi1_mosi_c, 3),
+ GROUP(spi1_miso_c, 3),
+ GROUP(spi1_sclk_c, 3),
+ GROUP(spi1_ss0_c, 3),
+
+ /* Bank X func1 */
+ GROUP(sdio_d0, 1),
+ GROUP(sdio_d1, 1),
+ GROUP(sdio_d2, 1),
+ GROUP(sdio_d3, 1),
+ GROUP(sdio_clk, 1),
+ GROUP(sdio_cmd, 1),
+ GROUP(pwm_b, 1),
+ GROUP(pwm_c, 1),
+ GROUP(tdm_d0, 1),
+ GROUP(tdm_d1, 1),
+ GROUP(tdm_fs0, 1),
+ GROUP(tdm_sclk0, 1),
+ GROUP(uart_c_tx, 1),
+ GROUP(uart_c_rx, 1),
+ GROUP(uart_c_cts, 1),
+ GROUP(uart_c_rts, 1),
+ GROUP(pwm_a, 1),
+ GROUP(i2c2_sda_x, 1),
+ GROUP(i2c2_sck_x, 1),
+ GROUP(pwm_d, 1),
+
+ /* Bank X func2 */
+ GROUP(clk12_24_x, 2),
+
+ /* Bank W func1 */
+ GROUP(hdmirx_a_hpd, 1),
+ GROUP(hdmirx_a_det, 1),
+ GROUP(hdmirx_a_sda, 1),
+ GROUP(hdmirx_a_sck, 1),
+ GROUP(hdmirx_c_hpd, 1),
+ GROUP(hdmirx_c_det, 1),
+ GROUP(hdmirx_c_sda, 1),
+ GROUP(hdmirx_c_sck, 1),
+ GROUP(hdmirx_b_hpd, 1),
+ GROUP(hdmirx_b_det, 1),
+ GROUP(hdmirx_b_sda, 1),
+ GROUP(hdmirx_b_sck, 1),
+ GROUP(cec_a, 1),
+ GROUP(hdmitx_sda_w13, 1),
+ GROUP(hdmitx_sck_w14, 1),
+ GROUP(hdmitx_hpd_in, 1),
+ GROUP(cec_b, 1),
+
+ /* Bank W func2 */
+ GROUP(uart_ao_a_tx_w2, 2),
+ GROUP(uart_ao_a_rx_w3, 2),
+ GROUP(uart_ao_a_tx_w6, 2),
+ GROUP(uart_ao_a_rx_w7, 2),
+ GROUP(uart_ao_a_tx_w10, 2),
+ GROUP(uart_ao_a_rx_w11, 2),
+
+ /* Bank W func3 */
+ GROUP(hdmitx_sda_w2, 3),
+ GROUP(hdmitx_sck_w3, 3),
+
+ /* Bank D func1 */
+ GROUP(uart_ao_a_tx_d0, 1),
+ GROUP(uart_ao_a_rx_d1, 1),
+ GROUP(i2c0_ao_sck_d, 1),
+ GROUP(i2c0_ao_sda_d, 1),
+ GROUP(remote_out_d4, 1),
+ GROUP(remote_in, 1),
+ GROUP(jtag_a_clk, 1),
+ GROUP(jtag_a_tms, 1),
+ GROUP(jtag_a_tdi, 1),
+ GROUP(jtag_a_tdo, 1),
+ GROUP(gen_clk_out_d, 1),
+ GROUP(pwm_ao_g_d11, 1),
+ GROUP(wd_rsto, 1),
+
+ /* Bank D func2 */
+ GROUP(i2c0_slave_ao_sck, 2),
+ GROUP(i2c0_slave_ao_sda, 2),
+ GROUP(rtc_clk_in, 2),
+ GROUP(pwm_ao_h_d5, 2),
+ GROUP(pwm_ao_c_d, 2),
+ GROUP(pwm_ao_g_d7, 2),
+ GROUP(spdif_out_d, 2),
+ GROUP(spdif_in_d, 2),
+ GROUP(pwm_ao_h_d10, 2),
+
+ /* Bank D func3 */
+ GROUP(uart_ao_b_tx, 3),
+ GROUP(uart_ao_b_rx, 3),
+ GROUP(uart_ao_b_cts, 3),
+ GROUP(pwm_ao_c_hiz, 3),
+ GROUP(pwm_ao_g_hiz, 3),
+ GROUP(uart_ao_b_rts, 3),
+
+ /* Bank D func4 */
+ GROUP(remote_out_d6, 4),
+
+ /* Bank E func1 */
+ GROUP(pwm_ao_a, 1),
+ GROUP(pwm_ao_b, 1),
+ GROUP(pwm_ao_c_e, 1),
+ GROUP(pwm_ao_d, 1),
+ GROUP(pwm_ao_e, 1),
+ GROUP(pwm_ao_f, 1),
+ GROUP(pwm_ao_g_e, 1),
+
+ /* Bank E func2 */
+ GROUP(i2c0_ao_sck_e, 2),
+ GROUP(i2c0_ao_sda_e, 2),
+ GROUP(clk25m, 2),
+ GROUP(i2c1_ao_sck, 2),
+ GROUP(i2c1_ao_sda, 2),
+ GROUP(rtc_clk_out, 2),
+
+ /* Bank E func3 */
+ GROUP(clk12_24_e, 3),
+
+ /* Bank Z func1 */
+ GROUP(eth_mdio, 1),
+ GROUP(eth_mdc, 1),
+ GROUP(eth_rgmii_rx_clk, 1),
+ GROUP(eth_rx_dv, 1),
+ GROUP(eth_rxd0, 1),
+ GROUP(eth_rxd1, 1),
+ GROUP(eth_rxd2_rgmii, 1),
+ GROUP(eth_rxd3_rgmii, 1),
+ GROUP(eth_rgmii_tx_clk, 1),
+ GROUP(eth_txen, 1),
+ GROUP(eth_txd0, 1),
+ GROUP(eth_txd1, 1),
+ GROUP(eth_txd2_rgmii, 1),
+ GROUP(eth_txd3_rgmii, 1),
+
+ /* Bank Z func2 */
+ GROUP(iso7816_clk_z, 2),
+ GROUP(iso7816_data_z, 2),
+ GROUP(tsin_b_valid, 2),
+ GROUP(tsin_b_sop, 2),
+ GROUP(tsin_b_din0, 2),
+ GROUP(tsin_b_clk, 2),
+ GROUP(tsin_b_fail, 2),
+ GROUP(tsin_b_din1, 2),
+ GROUP(tsin_b_din2, 2),
+ GROUP(tsin_b_din3, 2),
+ GROUP(tsin_b_din4, 2),
+ GROUP(tsin_b_din5, 2),
+ GROUP(tsin_b_din6, 2),
+ GROUP(tsin_b_din7, 2),
+
+ /* Bank Z func3 */
+ GROUP(tsin_c_z_valid, 3),
+ GROUP(tsin_c_z_sop, 3),
+ GROUP(tsin_c_z_din0, 3),
+ GROUP(tsin_c_z_clk, 3),
+ GROUP(tsin_d_z_valid, 3),
+ GROUP(tsin_d_z_sop, 3),
+ GROUP(tsin_d_z_din0, 3),
+ GROUP(tsin_d_z_clk, 3),
+
+ /* Bank Z func4 */
+ GROUP(spi4_mosi, 4),
+ GROUP(spi4_miso, 4),
+ GROUP(spi4_sclk, 4),
+ GROUP(spi4_ss0, 4),
+ GROUP(spi5_mosi, 4),
+ GROUP(spi5_miso, 4),
+ GROUP(spi5_sclk, 4),
+ GROUP(spi5_ss0, 4),
+
+ /* Bank T func1 */
+ GROUP(mclk1, 1),
+ GROUP(tdm_sclk1, 1),
+ GROUP(tdm_fs1, 1),
+ GROUP(tdm_d2, 1),
+ GROUP(tdm_d3, 1),
+ GROUP(tdm_d4, 1),
+ GROUP(tdm_d5, 1),
+ GROUP(tdm_d6, 1),
+ GROUP(tdm_d7, 1),
+ GROUP(tdm_d8, 1),
+ GROUP(tdm_d9, 1),
+ GROUP(tdm_d10, 1),
+ GROUP(tdm_d11, 1),
+ GROUP(mclk2, 1),
+ GROUP(tdm_sclk2, 1),
+ GROUP(tdm_fs2, 1),
+ GROUP(i2c1_sck, 1),
+ GROUP(i2c1_sda, 1),
+ GROUP(spi0_mosi, 1),
+ GROUP(spi0_miso, 1),
+ GROUP(spi0_sclk, 1),
+ GROUP(spi0_ss0, 1),
+ GROUP(spi0_ss1, 1),
+ GROUP(spi0_ss2, 1),
+
+ /* Bank T func2 */
+ GROUP(spdif_in_t, 2),
+ GROUP(spdif_out_t, 2),
+ GROUP(iso7816_clk_t, 2),
+ GROUP(iso7816_data_t, 2),
+ GROUP(tsin_a_sop_t, 2),
+ GROUP(tsin_a_din0_t, 2),
+ GROUP(tsin_a_clk_t, 2),
+ GROUP(tsin_a_valid_t, 2),
+ GROUP(i2c0_sck_t, 2),
+ GROUP(i2c0_sda_t, 2),
+ GROUP(i2c2_sck_t, 2),
+ GROUP(i2c2_sda_t, 2),
+
+ /* Bank T func3 */
+ GROUP(spi3_mosi, 3),
+ GROUP(spi3_miso, 3),
+ GROUP(spi3_sclk, 3),
+ GROUP(spi3_ss0, 3),
+
+ /* Bank M func1 */
+ GROUP(tdm_d12, 1),
+ GROUP(tdm_d13, 1),
+ GROUP(tdm_d14, 1),
+ GROUP(tdm_d15, 1),
+ GROUP(tdm_sclk3, 1),
+ GROUP(tdm_fs3, 1),
+ GROUP(i2c3_sda_m, 1),
+ GROUP(i2c3_sck_m, 1),
+ GROUP(spi1_mosi_m, 1),
+ GROUP(spi1_miso_m, 1),
+ GROUP(spi1_sclk_m, 1),
+ GROUP(spi1_ss0_m, 1),
+ GROUP(spi1_ss1_m, 1),
+ GROUP(spi1_ss2_m, 1),
+
+ /* Bank M func2 */
+ GROUP(pdm_din1_m0, 2),
+ GROUP(pdm_din2, 2),
+ GROUP(pdm_din3, 2),
+ GROUP(pdm_dclk, 2),
+ GROUP(pdm_din0, 2),
+ GROUP(pdm_din1_m5, 2),
+ GROUP(uart_d_tx_m, 2),
+ GROUP(uart_d_rx_m, 2),
+ GROUP(uart_d_cts_m, 2),
+ GROUP(uart_d_rts_m, 2),
+ GROUP(i2c2_sda_m, 2),
+ GROUP(i2c2_sck_m, 2),
+
+ /* Bank Y func1 */
+ GROUP(spi2_mosi, 1),
+ GROUP(spi2_miso, 1),
+ GROUP(spi2_sclk, 1),
+ GROUP(spi2_ss0, 1),
+ GROUP(spi2_ss1, 1),
+ GROUP(spi2_ss2, 1),
+ GROUP(uart_e_tx, 1),
+ GROUP(uart_e_rx, 1),
+ GROUP(uart_e_cts, 1),
+ GROUP(uart_e_rts, 1),
+ GROUP(uart_d_cts_y, 1),
+ GROUP(uart_d_rts_y, 1),
+ GROUP(uart_d_tx_y, 1),
+ GROUP(uart_d_rx_y, 1),
+ GROUP(i2c4_sck_y, 1),
+ GROUP(i2c4_sda_y, 1),
+ GROUP(i2c5_sck, 1),
+ GROUP(i2c5_sda, 1),
+
+ /* Bank Y func2 */
+ GROUP(tsin_c_y_sop, 2),
+ GROUP(tsin_c_y_din0, 2),
+ GROUP(tsin_c_y_clk, 2),
+ GROUP(tsin_c_y_valid, 2),
+ GROUP(tsin_d_y_sop, 2),
+ GROUP(tsin_d_y_din0, 2),
+ GROUP(tsin_d_y_clk, 2),
+ GROUP(tsin_d_y_valid, 2),
+ GROUP(pcieck_reqn_y, 2),
+
+ /* Bank Y func3 */
+ GROUP(pwm_e, 3),
+ GROUP(hsync, 3),
+ GROUP(vsync, 3),
+ GROUP(pwm_f, 3),
+ GROUP(sync_3d_out, 3),
+ GROUP(vx1_a_htpdn, 3),
+ GROUP(vx1_b_htpdn, 3),
+ GROUP(vx1_a_lockn, 3),
+ GROUP(vx1_b_lockn, 3),
+ GROUP(pwm_vs_y, 3),
+
+ /* Bank Y func4 */
+ GROUP(edp_a_hpd, 4),
+ GROUP(edp_b_hpd, 4),
+
+ /* Bank H func1 */
+ GROUP(mic_mute_key, 1),
+ GROUP(mic_mute_led, 1),
+ GROUP(i2c3_sck_h, 1),
+ GROUP(i2c3_sda_h, 1),
+ GROUP(i2c4_sck_h, 1),
+ GROUP(i2c4_sda_h, 1),
+ GROUP(eth_link_led, 1),
+ GROUP(eth_act_led, 1),
+
+ /* Bank H func2 */
+ GROUP(pwm_vs_h, 2),
+ GROUP(uart_f_tx, 2),
+ GROUP(uart_f_rx, 2),
+ GROUP(uart_f_cts, 2),
+ GROUP(uart_f_rts, 2),
+ GROUP(i2c0_sda_h, 2),
+ GROUP(i2c0_sck_h, 2),
+
+ /* Bank H func3 */
+ GROUP(pcieck_reqn_h, 3),
+};
+
+static const char * const gpio_periphs_groups[] = {
+ "GPIOB_0", "GPIOB_1", "GPIOB_2", "GPIOB_3", "GPIOB_4", "GPIOB_5",
+ "GPIOB_6", "GPIOB_7", "GPIOB_8", "GPIOB_9", "GPIOB_10",
+ "GPIOB_11", "GPIOB_12",
+
+ "GPIOC_0", "GPIOC_1", "GPIOC_2", "GPIOC_3", "GPIOC_4", "GPIOC_5",
+ "GPIOC_6",
+
+ "GPIOX_0", "GPIOX_1", "GPIOX_2", "GPIOX_3", "GPIOX_4", "GPIOX_5",
+ "GPIOX_6", "GPIOX_7", "GPIOX_8", "GPIOX_9", "GPIOX_10", "GPIOX_11",
+ "GPIOX_12", "GPIOX_13", "GPIOX_14", "GPIOX_15", "GPIOX_16", "GPIOX_17",
+ "GPIOX_18", "GPIOX_19",
+
+ "GPIOW_0", "GPIOW_1", "GPIOW_2", "GPIOW_3", "GPIOW_4", "GPIOW_5",
+ "GPIOW_6", "GPIOW_7", "GPIOW_8", "GPIOW_9", "GPIOW_10", "GPIOW_11",
+ "GPIOW_12", "GPIOW_13", "GPIOW_14", "GPIOW_15", "GPIOW_16",
+
+ "GPIOD_0", "GPIOD_1", "GPIOD_2", "GPIOD_3", "GPIOD_4", "GPIOD_5",
+ "GPIOD_6", "GPIOD_7", "GPIOD_8", "GPIOD_9", "GPIOD_10", "GPIOD_11",
+ "GPIOD_12",
+
+ "GPIOE_0", "GPIOE_1", "GPIOE_2", "GPIOE_3", "GPIOE_4", "GPIOE_5",
+ "GPIOE_6",
+
+ "GPIOZ_0", "GPIOZ_1", "GPIOZ_2", "GPIOZ_3", "GPIOZ_4", "GPIOZ_5",
+ "GPIOZ_6", "GPIOZ_7", "GPIOZ_8", "GPIOZ_9", "GPIOZ_10", "GPIOZ_11",
+ "GPIOZ_12", "GPIOZ_13",
+
+ "GPIOT_0", "GPIOT_1", "GPIOT_2", "GPIOT_3", "GPIOT_4", "GPIOT_5",
+ "GPIOT_6", "GPIOT_7", "GPIOT_8", "GPIOT_9", "GPIOT_10", "GPIOT_11",
+ "GPIOT_12", "GPIOT_13", "GPIOT_14", "GPIOT_15", "GPIOT_16",
+ "GPIOT_17", "GPIOT_18", "GPIOT_19", "GPIOT_20", "GPIOT_21",
+ "GPIOT_22", "GPIOT_23",
+
+ "GPIOM_0", "GPIOM_1", "GPIOM_2", "GPIOM_3", "GPIOM_4", "GPIOM_5",
+ "GPIOM_6", "GPIOM_7", "GPIOM_8", "GPIOM_9", "GPIOM_10", "GPIOM_11",
+ "GPIOM_12", "GPIOM_13",
+
+ "GPIOY_0", "GPIOY_1", "GPIOY_2", "GPIOY_3", "GPIOY_4", "GPIOY_5",
+ "GPIOY_6", "GPIOY_7", "GPIOY_8", "GPIOY_9", "GPIOY_10", "GPIOY_11",
+ "GPIOY_12", "GPIOY_13", "GPIOY_14", "GPIOY_15", "GPIOY_16",
+ "GPIOY_17", "GPIOY_18",
+
+ "GPIOH_0", "GPIOH_1", "GPIOH_2", "GPIOH_3", "GPIOH_4", "GPIOH_5",
+ "GPIOH_6", "GPIOH_7",
+
+ "GPIO_TEST_N",
+};
+
+static const char * const emmc_groups[] = {
+ "emmc_nand_d0", "emmc_nand_d1", "emmc_nand_d2", "emmc_nand_d3",
+ "emmc_nand_d4", "emmc_nand_d5", "emmc_nand_d6", "emmc_nand_d7",
+ "emmc_clk", "emmc_cmd", "emmc_nand_ds",
+};
+
+static const char * const nor_groups[] = {
+ "nor_hold", "nor_d", "nor_q", "nor_c", "nor_wp", "nor_cs",
+};
+
+static const char * const sdcard_groups[] = {
+ "sdcard_d0", "sdcard_d1", "sdcard_d2", "sdcard_d3", "sdcard_clk",
+ "sdcard_cmd",
+};
+
+static const char * const sdio_groups[] = {
+ "sdio_d0", "sdio_d1", "sdio_d2", "sdio_d3", "sdio_clk", "sdio_cmd",
+};
+
+static const char * const gen_clk_groups[] = {
+ "gen_clk_out_c", "gen_clk_out_d",
+};
+
+static const char * const jtag_a_groups[] = {
+ "jtag_a_clk", "jtag_a_tms", "jtag_a_tdi", "jtag_a_tdo",
+};
+
+static const char * const jtag_b_groups[] = {
+ "jtag_b_tdo", "jtag_b_tdi", "jtag_b_clk", "jtag_b_tms",
+};
+
+static const char * const uart_c_groups[] = {
+ "uart_c_tx", "uart_c_rx", "uart_c_cts", "uart_c_rts",
+};
+
+static const char * const uart_d_groups[] = {
+ "uart_d_tx_m", "uart_d_rx_m", "uart_d_cts_m", "uart_d_rts_m",
+ "uart_d_rts_y", "uart_d_tx_y", "uart_d_rx_y", "uart_d_cts_y",
+};
+
+static const char * const uart_e_groups[] = {
+ "uart_e_tx", "uart_e_rx", "uart_e_cts", "uart_e_rts",
+};
+
+static const char * const uart_f_groups[] = {
+ "uart_f_tx", "uart_f_rx", "uart_f_cts", "uart_f_rts",
+};
+
+static const char * const uart_ao_a_groups[] = {
+ "uart_ao_a_rx_c", "uart_ao_a_tx_c", "uart_ao_a_tx_w2",
+ "uart_ao_a_rx_w3", "uart_ao_a_tx_w6", "uart_ao_a_rx_w7",
+ "uart_ao_a_tx_w10", "uart_ao_a_rx_w11", "uart_ao_a_tx_d0",
+ "uart_ao_a_rx_d1",
+};
+
+static const char * const uart_ao_b_groups[] = {
+ "uart_ao_b_tx", "uart_ao_b_rx", "uart_ao_b_cts", "uart_ao_b_rts",
+};
+
+static const char * const spi0_groups[] = {
+ "spi0_mosi", "spi0_miso", "spi0_sclk", "spi0_ss0", "spi0_ss1",
+ "spi0_ss2",
+};
+
+static const char * const spi1_groups[] = {
+ "spi1_mosi_c", "spi1_miso_c", "spi1_sclk_c", "spi1_ss0_c",
+ "spi1_mosi_m", "spi1_miso_m", "spi1_sclk_m", "spi1_ss0_m",
+ "spi1_ss1_m", "spi1_ss2_m",
+};
+
+static const char * const spi2_groups[] = {
+ "spi2_mosi", "spi2_miso", "spi2_sclk", "spi2_ss0", "spi2_ss1",
+ "spi2_ss2",
+};
+
+static const char * const spi3_groups[] = {
+ "spi3_mosi", "spi3_miso", "spi3_sclk", "spi3_ss0",
+};
+
+static const char * const spi4_groups[] = {
+ "spi4_mosi", "spi4_miso", "spi4_sclk", "spi4_ss0",
+};
+
+static const char * const spi5_groups[] = {
+ "spi5_mosi", "spi5_miso", "spi5_sclk", "spi5_ss0",
+};
+
+static const char * const pwm_a_groups[] = {
+ "pwm_a",
+};
+
+static const char * const pwm_b_groups[] = {
+ "pwm_b",
+};
+
+static const char * const pwm_c_groups[] = {
+ "pwm_c",
+};
+
+static const char * const pwm_d_groups[] = {
+ "pwm_d",
+};
+
+static const char * const pwm_e_groups[] = {
+ "pwm_e",
+};
+
+static const char * const pwm_f_groups[] = {
+ "pwm_f",
+};
+
+static const char * const pwm_ao_c_hiz_groups[] = {
+ "pwm_ao_c_hiz",
+};
+
+static const char * const pwm_ao_g_hiz_groups[] = {
+ "pwm_ao_g_hiz",
+};
+
+static const char * const pwm_ao_a_groups[] = {
+ "pwm_ao_a",
+};
+
+static const char * const pwm_ao_b_groups[] = {
+ "pwm_ao_b",
+};
+
+static const char * const pwm_ao_c_groups[] = {
+ "pwm_ao_c_d", "pwm_ao_c_e",
+};
+
+static const char * const pwm_ao_d_groups[] = {
+ "pwm_ao_d",
+};
+
+static const char * const pwm_ao_e_groups[] = {
+ "pwm_ao_e",
+};
+
+static const char * const pwm_ao_f_groups[] = {
+ "pwm_ao_f",
+};
+
+static const char * const pwm_ao_h_groups[] = {
+ "pwm_ao_h_d5", "pwm_ao_h_d10",
+};
+
+static const char * const pwm_ao_g_groups[] = {
+ "pwm_ao_g_d11", "pwm_ao_g_d7", "pwm_ao_g_e",
+};
+
+static const char * const pwm_vs_groups[] = {
+ "pwm_vs_y", "pwm_vs_h",
+};
+
+static const char * const tdm_groups[] = {
+ "tdm_d0", "tdm_d1", "tdm_fs0", "tdm_sclk0", "tdm_sclk1", "tdm_fs1",
+ "tdm_d2", "tdm_d3", "tdm_d4", "tdm_d5", "tdm_d6", "tdm_d7",
+ "tdm_d8", "tdm_d9", "tdm_d10", "tdm_d11", "tdm_sclk2", "tdm_fs2",
+ "tdm_d12", "tdm_d13", "tdm_d14", "tdm_d15", "tdm_sclk3", "tdm_fs3",
+};
+
+static const char * const i2c0_slave_ao_groups[] = {
+ "i2c0_slave_ao_sck", "i2c0_slave_ao_sda",
+};
+
+static const char * const i2c0_ao_groups[] = {
+ "i2c0_ao_sck_d", "i2c0_ao_sda_d",
+ "i2c0_ao_sck_e", "i2c0_ao_sda_e",
+};
+
+static const char * const i2c1_ao_groups[] = {
+ "i2c1_ao_sck", "i2c1_ao_sda",
+};
+
+static const char * const i2c0_groups[] = {
+ "i2c0_sck_t", "i2c0_sda_t", "i2c0_sck_h", "i2c0_sda_h",
+};
+
+static const char * const i2c1_groups[] = {
+ "i2c1_sck", "i2c1_sda",
+};
+
+static const char * const i2c2_groups[] = {
+ "i2c2_sda_x", "i2c2_sck_x",
+ "i2c2_sda_t", "i2c2_sck_t",
+ "i2c2_sda_m", "i2c2_sck_m",
+};
+
+static const char * const i2c3_groups[] = {
+ "i2c3_sda_m", "i2c3_sck_m", "i2c3_sck_h", "i2c3_sda_h",
+};
+
+static const char * const i2c4_groups[] = {
+ "i2c4_sck_y", "i2c4_sda_y", "i2c4_sck_h", "i2c4_sda_h",
+};
+
+static const char * const i2c5_groups[] = {
+ "i2c5_sck", "i2c5_sda",
+};
+
+static const char * const clk12_24_groups[] = {
+ "clk12_24_x", "clk12_24_e",
+};
+
+static const char * const hdmirx_a_groups[] = {
+ "hdmirx_a_hpd", "hdmirx_a_det", "hdmirx_a_sda", "hdmirx_a_sck",
+};
+
+static const char * const hdmirx_b_groups[] = {
+ "hdmirx_b_hpd", "hdmirx_b_det", "hdmirx_b_sda", "hdmirx_b_sck",
+};
+
+static const char * const hdmirx_c_groups[] = {
+ "hdmirx_c_hpd", "hdmirx_c_det", "hdmirx_c_sda", "hdmirx_c_sck",
+};
+
+static const char * const cec_a_groups[] = {
+ "cec_a",
+};
+
+static const char * const cec_b_groups[] = {
+ "cec_b",
+};
+
+static const char * const hdmitx_groups[] = {
+ "hdmitx_sda_w13", "hdmitx_sck_w14", "hdmitx_hpd_in",
+ "hdmitx_sda_w2", "hdmitx_sck_w3",
+};
+
+static const char * const remote_out_groups[] = {
+ "remote_out_d4", "remote_out_d6",
+};
+
+static const char * const remote_in_groups[] = {
+ "remote_in",
+};
+
+static const char * const wd_rsto_groups[] = {
+ "wd_rsto",
+};
+
+static const char * const rtc_clk_groups[] = {
+ "rtc_clk_in", "rtc_clk_out",
+};
+
+static const char * const spdif_out_groups[] = {
+ "spdif_out_d", "spdif_out_t",
+};
+
+static const char * const spdif_in_groups[] = {
+ "spdif_in_d", "spdif_in_t",
+};
+
+static const char * const clk25m_groups[] = {
+ "clk25m",
+};
+
+static const char * const eth_groups[] = {
+ "eth_mdio", "eth_mdc", "eth_rgmii_rx_clk", "eth_rx_dv", "eth_rxd0",
+ "eth_rxd1", "eth_rxd2_rgmii", "eth_rxd3_rgmii", "eth_rgmii_tx_clk",
+ "eth_txen", "eth_txd0", "eth_txd1", "eth_txd2_rgmii",
+ "eth_txd3_rgmii", "eth_link_led", "eth_act_led",
+};
+
+static const char * const iso7816_groups[] = {
+ "iso7816_clk_z", "iso7816_data_z",
+ "iso7816_clk_t", "iso7816_data_t",
+};
+
+static const char * const tsin_a_groups[] = {
+ "tsin_a_sop_t", "tsin_a_din0_t", "tsin_a_clk_t", "tsin_a_valid_t",
+};
+
+static const char * const tsin_b_groups[] = {
+ "tsin_b_valid", "tsin_b_sop", "tsin_b_din0", "tsin_b_clk",
+ "tsin_b_fail", "tsin_b_din1", "tsin_b_din2", "tsin_b_din3",
+ "tsin_b_din4", "tsin_b_din5", "tsin_b_din6", "tsin_b_din7",
+};
+
+static const char * const tsin_c_groups[] = {
+ "tsin_c_z_valid", "tsin_c_z_sop", "tsin_c_z_din0", "tsin_c_z_clk",
+ "tsin_c_y_sop", "tsin_c_y_din0", "tsin_c_y_clk", "tsin_c_y_valid",
+};
+
+static const char * const tsin_d_groups[] = {
+ "tsin_d_z_valid", "tsin_d_z_sop", "tsin_d_z_din0", "tsin_d_z_clk",
+ "tsin_d_y_sop", "tsin_d_y_din0", "tsin_d_y_clk", "tsin_d_y_valid",
+};
+
+static const char * const mclk_groups[] = {
+ "mclk1", "mclk2",
+};
+
+static const char * const pdm_groups[] = {
+ "pdm_din1_m0", "pdm_din2", "pdm_din3", "pdm_dclk", "pdm_din0",
+ "pdm_din1_m5",
+};
+
+static const char * const pcieck_groups[] = {
+ "pcieck_reqn_y", "pcieck_reqn_h",
+};
+
+static const char * const hsync_groups[] = {
+ "hsync",
+};
+
+static const char * const vsync_groups[] = {
+ "vsync",
+};
+
+static const char * const sync_3d_groups[] = {
+ "sync_3d_out",
+};
+
+static const char * const vx1_a_groups[] = {
+ "vx1_a_htpdn", "vx1_a_lockn",
+};
+
+static const char * const vx1_b_groups[] = {
+ "vx1_b_htpdn", "vx1_b_lockn",
+};
+
+static const char * const edp_a_groups[] = {
+ "edp_a_hpd",
+};
+
+static const char * const edp_b_groups[] = {
+ "edp_b_hpd",
+};
+
+static const char * const mic_mute_groups[] = {
+ "mic_mute_key", "mic_mute_led",
+};
+
+static struct meson_pmx_func t7_periphs_functions[] = {
+ FUNCTION(gpio_periphs),
+ FUNCTION(emmc),
+ FUNCTION(nor),
+ FUNCTION(sdcard),
+ FUNCTION(sdio),
+ FUNCTION(gen_clk),
+ FUNCTION(jtag_a),
+ FUNCTION(jtag_b),
+ FUNCTION(uart_c),
+ FUNCTION(uart_d),
+ FUNCTION(uart_e),
+ FUNCTION(uart_f),
+ FUNCTION(uart_ao_a),
+ FUNCTION(uart_ao_b),
+ FUNCTION(spi0),
+ FUNCTION(spi1),
+ FUNCTION(spi2),
+ FUNCTION(spi3),
+ FUNCTION(spi4),
+ FUNCTION(spi5),
+ FUNCTION(pwm_a),
+ FUNCTION(pwm_b),
+ FUNCTION(pwm_c),
+ FUNCTION(pwm_d),
+ FUNCTION(pwm_e),
+ FUNCTION(pwm_f),
+ FUNCTION(pwm_ao_c_hiz),
+ FUNCTION(pwm_ao_g_hiz),
+ FUNCTION(pwm_ao_a),
+ FUNCTION(pwm_ao_b),
+ FUNCTION(pwm_ao_c),
+ FUNCTION(pwm_ao_d),
+ FUNCTION(pwm_ao_e),
+ FUNCTION(pwm_ao_f),
+ FUNCTION(pwm_ao_h),
+ FUNCTION(pwm_ao_g),
+ FUNCTION(pwm_vs),
+ FUNCTION(tdm),
+ FUNCTION(i2c0_slave_ao),
+ FUNCTION(i2c0_ao),
+ FUNCTION(i2c1_ao),
+ FUNCTION(i2c0),
+ FUNCTION(i2c1),
+ FUNCTION(i2c2),
+ FUNCTION(i2c3),
+ FUNCTION(i2c4),
+ FUNCTION(i2c5),
+ FUNCTION(clk12_24),
+ FUNCTION(hdmirx_a),
+ FUNCTION(hdmirx_b),
+ FUNCTION(hdmirx_c),
+ FUNCTION(cec_a),
+ FUNCTION(cec_b),
+ FUNCTION(hdmitx),
+ FUNCTION(remote_out),
+ FUNCTION(remote_in),
+ FUNCTION(wd_rsto),
+ FUNCTION(rtc_clk),
+ FUNCTION(spdif_out),
+ FUNCTION(spdif_in),
+ FUNCTION(clk25m),
+ FUNCTION(eth),
+ FUNCTION(iso7816),
+ FUNCTION(tsin_a),
+ FUNCTION(tsin_b),
+ FUNCTION(tsin_c),
+ FUNCTION(tsin_d),
+ FUNCTION(mclk),
+ FUNCTION(pdm),
+ FUNCTION(pcieck),
+ FUNCTION(hsync),
+ FUNCTION(vsync),
+ FUNCTION(sync_3d),
+ FUNCTION(vx1_a),
+ FUNCTION(vx1_b),
+ FUNCTION(edp_a),
+ FUNCTION(edp_b),
+ FUNCTION(mic_mute),
+};
+
+static struct meson_bank t7_periphs_banks[] = {
+ /* name first last irq pullen pull dir out in ds */
+ BANK_DS("D", GPIOD_0, GPIOD_12, 57, 69,
+ 0x03, 0, 0x04, 0, 0x02, 0, 0x01, 0, 0x00, 0, 0x07, 0),
+ BANK_DS("E", GPIOE_0, GPIOE_6, 70, 76,
+ 0x0b, 0, 0x0c, 0, 0x0a, 0, 0x09, 0, 0x08, 0, 0x0f, 0),
+ BANK_DS("Z", GPIOZ_0, GPIOZ_13, 77, 90,
+ 0x13, 0, 0x14, 0, 0x12, 0, 0x11, 0, 0x10, 0, 0x17, 0),
+ BANK_DS("H", GPIOH_0, GPIOH_7, 148, 155,
+ 0x1b, 0, 0x1c, 0, 0x1a, 0, 0x19, 0, 0x18, 0, 0x1f, 0),
+ BANK_DS("C", GPIOC_0, GPIOC_6, 13, 19,
+ 0x23, 0, 0x24, 0, 0x22, 0, 0x21, 0, 0x20, 0, 0x27, 0),
+ BANK_DS("B", GPIOB_0, GPIOB_12, 0, 12,
+ 0x2b, 0, 0x2c, 0, 0x2a, 0, 0x29, 0, 0x28, 0, 0x2f, 0),
+ BANK_DS("X", GPIOX_0, GPIOX_19, 20, 39,
+ 0x33, 0, 0x34, 0, 0x32, 0, 0x31, 0, 0x30, 0, 0x37, 0),
+ BANK_DS("T", GPIOT_0, GPIOT_23, 91, 114,
+ 0x43, 0, 0x44, 0, 0x42, 0, 0x41, 0, 0x40, 0, 0x47, 0),
+ BANK_DS("Y", GPIOY_0, GPIOY_18, 129, 147,
+ 0x53, 0, 0x54, 0, 0x52, 0, 0x51, 0, 0x50, 0, 0x57, 0),
+ BANK_DS("W", GPIOW_0, GPIOW_16, 40, 56,
+ 0x63, 0, 0x64, 0, 0x62, 0, 0x61, 0, 0x60, 0, 0x67, 0),
+ BANK_DS("M", GPIOM_0, GPIOM_13, 115, 128,
+ 0x73, 0, 0x74, 0, 0x72, 0, 0x71, 0, 0x70, 0, 0x77, 0),
+ BANK_DS("TEST_N", GPIO_TEST_N, GPIO_TEST_N, 156, 156,
+ 0x83, 0, 0x84, 0, 0x82, 0, 0x81, 0, 0x80, 0, 0x87, 0),
+};
+
+static struct meson_pmx_bank t7_periphs_pmx_banks[] = {
+ /* name first last reg offset */
+ BANK_PMX("D", GPIOD_0, GPIOD_12, 0x0a, 0),
+ BANK_PMX("E", GPIOE_0, GPIOE_6, 0x0c, 0),
+ BANK_PMX("Z", GPIOZ_0, GPIOZ_13, 0x05, 0),
+ BANK_PMX("H", GPIOH_0, GPIOH_7, 0x08, 0),
+ BANK_PMX("C", GPIOC_0, GPIOC_6, 0x07, 0),
+ BANK_PMX("B", GPIOB_0, GPIOB_12, 0x00, 0),
+ BANK_PMX("X", GPIOX_0, GPIOX_19, 0x02, 0),
+ BANK_PMX("T", GPIOT_0, GPIOT_23, 0x0f, 0),
+ BANK_PMX("Y", GPIOY_0, GPIOY_18, 0x13, 0),
+ BANK_PMX("W", GPIOW_0, GPIOW_16, 0x16, 0),
+ BANK_PMX("M", GPIOM_0, GPIOM_13, 0x0d, 0),
+ BANK_PMX("TEST_N", GPIO_TEST_N, GPIO_TEST_N, 0x09, 0),
+};
+
+static struct meson_axg_pmx_data t7_periphs_pmx_banks_data = {
+ .pmx_banks = t7_periphs_pmx_banks,
+ .num_pmx_banks = ARRAY_SIZE(t7_periphs_pmx_banks),
+};
+
+static struct meson_pinctrl_data t7_periphs_pinctrl_data = {
+ .name = "periphs-banks",
+ .pins = t7_periphs_pins,
+ .groups = t7_periphs_groups,
+ .funcs = t7_periphs_functions,
+ .banks = t7_periphs_banks,
+ .num_pins = ARRAY_SIZE(t7_periphs_pins),
+ .num_groups = ARRAY_SIZE(t7_periphs_groups),
+ .num_funcs = ARRAY_SIZE(t7_periphs_functions),
+ .num_banks = ARRAY_SIZE(t7_periphs_banks),
+ .pmx_ops = &meson_axg_pmx_ops,
+ .pmx_data = &t7_periphs_pmx_banks_data,
+ .parse_dt = &meson_a1_parse_dt_extra,
+};
+
+static const struct of_device_id t7_pinctrl_dt_match[] = {
+ {
+ .compatible = "amlogic,t7-periphs-pinctrl",
+ .data = &t7_periphs_pinctrl_data,
+ },
+ { }
+};
+MODULE_DEVICE_TABLE(of, t7_pinctrl_dt_match);
+
+static struct platform_driver t7_pinctrl_driver = {
+ .probe = meson_pinctrl_probe,
+ .driver = {
+ .name = "amlogic-t7-pinctrl",
+ .of_match_table = t7_pinctrl_dt_match,
+ },
+};
+module_platform_driver(t7_pinctrl_driver);
+
+MODULE_AUTHOR("Huqiang Qin <huqiang.qin@amlogic.com>");
+MODULE_DESCRIPTION("Pin controller and GPIO driver for Amlogic T7 SoC");
+MODULE_LICENSE("Dual BSD/GPL");
diff --git a/drivers/pinctrl/mvebu/pinctrl-armada-38x.c b/drivers/pinctrl/mvebu/pinctrl-armada-38x.c
index 040e418dbf..162dfc2136 100644
--- a/drivers/pinctrl/mvebu/pinctrl-armada-38x.c
+++ b/drivers/pinctrl/mvebu/pinctrl-armada-38x.c
@@ -12,8 +12,8 @@
#include <linux/io.h>
#include <linux/platform_device.h>
#include <linux/of.h>
-#include <linux/of_device.h>
#include <linux/pinctrl/pinctrl.h>
+#include <linux/property.h>
#include "pinctrl-mvebu.h"
@@ -404,13 +404,8 @@ static struct pinctrl_gpio_range armada_38x_mpp_gpio_ranges[] = {
static int armada_38x_pinctrl_probe(struct platform_device *pdev)
{
struct mvebu_pinctrl_soc_info *soc = &armada_38x_pinctrl_info;
- const struct of_device_id *match =
- of_match_device(armada_38x_pinctrl_of_match, &pdev->dev);
- if (!match)
- return -ENODEV;
-
- soc->variant = (unsigned) match->data & 0xff;
+ soc->variant = (unsigned)device_get_match_data(&pdev->dev) & 0xff;
soc->controls = armada_38x_mpp_controls;
soc->ncontrols = ARRAY_SIZE(armada_38x_mpp_controls);
soc->gpioranges = armada_38x_mpp_gpio_ranges;
diff --git a/drivers/pinctrl/mvebu/pinctrl-armada-39x.c b/drivers/pinctrl/mvebu/pinctrl-armada-39x.c
index c33f1cbaf6..d9c98faa7b 100644
--- a/drivers/pinctrl/mvebu/pinctrl-armada-39x.c
+++ b/drivers/pinctrl/mvebu/pinctrl-armada-39x.c
@@ -12,8 +12,8 @@
#include <linux/io.h>
#include <linux/platform_device.h>
#include <linux/of.h>
-#include <linux/of_device.h>
#include <linux/pinctrl/pinctrl.h>
+#include <linux/property.h>
#include "pinctrl-mvebu.h"
@@ -386,13 +386,8 @@ static struct pinctrl_gpio_range armada_39x_mpp_gpio_ranges[] = {
static int armada_39x_pinctrl_probe(struct platform_device *pdev)
{
struct mvebu_pinctrl_soc_info *soc = &armada_39x_pinctrl_info;
- const struct of_device_id *match =
- of_match_device(armada_39x_pinctrl_of_match, &pdev->dev);
- if (!match)
- return -ENODEV;
-
- soc->variant = (unsigned) match->data & 0xff;
+ soc->variant = (unsigned)device_get_match_data(&pdev->dev) & 0xff;
soc->controls = armada_39x_mpp_controls;
soc->ncontrols = ARRAY_SIZE(armada_39x_mpp_controls);
soc->gpioranges = armada_39x_mpp_gpio_ranges;
diff --git a/drivers/pinctrl/mvebu/pinctrl-armada-ap806.c b/drivers/pinctrl/mvebu/pinctrl-armada-ap806.c
index 89bab53671..7becf2781a 100644
--- a/drivers/pinctrl/mvebu/pinctrl-armada-ap806.c
+++ b/drivers/pinctrl/mvebu/pinctrl-armada-ap806.c
@@ -13,7 +13,6 @@
#include <linux/io.h>
#include <linux/platform_device.h>
#include <linux/of.h>
-#include <linux/of_device.h>
#include <linux/pinctrl/pinctrl.h>
#include "pinctrl-mvebu.h"
@@ -106,10 +105,8 @@ static struct pinctrl_gpio_range armada_ap806_mpp_gpio_ranges[] = {
static int armada_ap806_pinctrl_probe(struct platform_device *pdev)
{
struct mvebu_pinctrl_soc_info *soc = &armada_ap806_pinctrl_info;
- const struct of_device_id *match =
- of_match_device(armada_ap806_pinctrl_of_match, &pdev->dev);
- if (!match || !pdev->dev.parent)
+ if (!pdev->dev.parent)
return -ENODEV;
soc->variant = 0; /* no variants for Armada AP806 */
diff --git a/drivers/pinctrl/mvebu/pinctrl-armada-cp110.c b/drivers/pinctrl/mvebu/pinctrl-armada-cp110.c
index 8ba8f3e912..9a250c491f 100644
--- a/drivers/pinctrl/mvebu/pinctrl-armada-cp110.c
+++ b/drivers/pinctrl/mvebu/pinctrl-armada-cp110.c
@@ -12,9 +12,9 @@
#include <linux/io.h>
#include <linux/mfd/syscon.h>
#include <linux/of.h>
-#include <linux/of_device.h>
#include <linux/pinctrl/pinctrl.h>
#include <linux/platform_device.h>
+#include <linux/property.h>
#include "pinctrl-mvebu.h"
@@ -638,8 +638,6 @@ static void mvebu_pinctrl_assign_variant(struct mvebu_mpp_mode *m,
static int armada_cp110_pinctrl_probe(struct platform_device *pdev)
{
struct mvebu_pinctrl_soc_info *soc;
- const struct of_device_id *match =
- of_match_device(armada_cp110_pinctrl_of_match, &pdev->dev);
int i;
if (!pdev->dev.parent)
@@ -650,7 +648,7 @@ static int armada_cp110_pinctrl_probe(struct platform_device *pdev)
if (!soc)
return -ENOMEM;
- soc->variant = (unsigned long) match->data & 0xff;
+ soc->variant = (unsigned long)device_get_match_data(&pdev->dev) & 0xff;
soc->controls = armada_cp110_mpp_controls;
soc->ncontrols = ARRAY_SIZE(armada_cp110_mpp_controls);
soc->modes = armada_cp110_mpp_modes;
diff --git a/drivers/pinctrl/mvebu/pinctrl-armada-xp.c b/drivers/pinctrl/mvebu/pinctrl-armada-xp.c
index 48e2a6c56a..487825bfd1 100644
--- a/drivers/pinctrl/mvebu/pinctrl-armada-xp.c
+++ b/drivers/pinctrl/mvebu/pinctrl-armada-xp.c
@@ -19,8 +19,8 @@
#include <linux/platform_device.h>
#include <linux/clk.h>
#include <linux/of.h>
-#include <linux/of_device.h>
#include <linux/pinctrl/pinctrl.h>
+#include <linux/property.h>
#include <linux/bitops.h>
#include "pinctrl-mvebu.h"
@@ -568,14 +568,9 @@ static int armada_xp_pinctrl_resume(struct platform_device *pdev)
static int armada_xp_pinctrl_probe(struct platform_device *pdev)
{
struct mvebu_pinctrl_soc_info *soc = &armada_xp_pinctrl_info;
- const struct of_device_id *match =
- of_match_device(armada_xp_pinctrl_of_match, &pdev->dev);
int nregs;
- if (!match)
- return -ENODEV;
-
- soc->variant = (unsigned) match->data & 0xff;
+ soc->variant = (unsigned)device_get_match_data(&pdev->dev) & 0xff;
switch (soc->variant) {
case V_MV78230:
diff --git a/drivers/pinctrl/mvebu/pinctrl-dove.c b/drivers/pinctrl/mvebu/pinctrl-dove.c
index bd74daa9ed..1947da73e5 100644
--- a/drivers/pinctrl/mvebu/pinctrl-dove.c
+++ b/drivers/pinctrl/mvebu/pinctrl-dove.c
@@ -12,9 +12,9 @@
#include <linux/platform_device.h>
#include <linux/clk.h>
#include <linux/of.h>
-#include <linux/of_device.h>
#include <linux/mfd/syscon.h>
#include <linux/pinctrl/pinctrl.h>
+#include <linux/property.h>
#include <linux/regmap.h>
#include "pinctrl-mvebu.h"
@@ -765,13 +765,11 @@ static int dove_pinctrl_probe(struct platform_device *pdev)
{
struct resource *res, *mpp_res;
struct resource fb_res;
- const struct of_device_id *match =
- of_match_device(dove_pinctrl_of_match, &pdev->dev);
struct mvebu_mpp_ctrl_data *mpp_data;
void __iomem *base;
int i;
- pdev->dev.platform_data = (void *)match->data;
+ pdev->dev.platform_data = (void *)device_get_match_data(&pdev->dev);
/*
* General MPP Configuration Register is part of pdma registers.
diff --git a/drivers/pinctrl/mvebu/pinctrl-kirkwood.c b/drivers/pinctrl/mvebu/pinctrl-kirkwood.c
index d45c31f281..4789d7442f 100644
--- a/drivers/pinctrl/mvebu/pinctrl-kirkwood.c
+++ b/drivers/pinctrl/mvebu/pinctrl-kirkwood.c
@@ -11,8 +11,8 @@
#include <linux/platform_device.h>
#include <linux/clk.h>
#include <linux/of.h>
-#include <linux/of_device.h>
#include <linux/pinctrl/pinctrl.h>
+#include <linux/property.h>
#include "pinctrl-mvebu.h"
@@ -470,10 +470,7 @@ static const struct of_device_id kirkwood_pinctrl_of_match[] = {
static int kirkwood_pinctrl_probe(struct platform_device *pdev)
{
- const struct of_device_id *match =
- of_match_device(kirkwood_pinctrl_of_match, &pdev->dev);
-
- pdev->dev.platform_data = (void *)match->data;
+ pdev->dev.platform_data = (void *)device_get_match_data(&pdev->dev);
return mvebu_pinctrl_simple_mmio_probe(pdev);
}
diff --git a/drivers/pinctrl/mvebu/pinctrl-orion.c b/drivers/pinctrl/mvebu/pinctrl-orion.c
index cc97d270be..2b6ab7f2af 100644
--- a/drivers/pinctrl/mvebu/pinctrl-orion.c
+++ b/drivers/pinctrl/mvebu/pinctrl-orion.c
@@ -19,8 +19,8 @@
#include <linux/platform_device.h>
#include <linux/clk.h>
#include <linux/of.h>
-#include <linux/of_device.h>
#include <linux/pinctrl/pinctrl.h>
+#include <linux/property.h>
#include "pinctrl-mvebu.h"
@@ -218,10 +218,7 @@ static const struct of_device_id orion_pinctrl_of_match[] = {
static int orion_pinctrl_probe(struct platform_device *pdev)
{
- const struct of_device_id *match =
- of_match_device(orion_pinctrl_of_match, &pdev->dev);
-
- pdev->dev.platform_data = (void*)match->data;
+ pdev->dev.platform_data = (void*)device_get_match_data(&pdev->dev);
mpp_base = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(mpp_base))
diff --git a/drivers/pinctrl/nomadik/pinctrl-abx500.c b/drivers/pinctrl/nomadik/pinctrl-abx500.c
index 6b90051af2..d3c32d809b 100644
--- a/drivers/pinctrl/nomadik/pinctrl-abx500.c
+++ b/drivers/pinctrl/nomadik/pinctrl-abx500.c
@@ -17,6 +17,7 @@
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/platform_device.h>
+#include <linux/property.h>
#include <linux/seq_file.h>
#include <linux/slab.h>
#include <linux/types.h>
@@ -985,7 +986,6 @@ static const struct of_device_id abx500_gpio_match[] = {
static int abx500_gpio_probe(struct platform_device *pdev)
{
struct device_node *np = pdev->dev.of_node;
- const struct of_device_id *match;
struct abx500_pinctrl *pct;
unsigned int id = -1;
int ret;
@@ -1006,12 +1006,7 @@ static int abx500_gpio_probe(struct platform_device *pdev)
pct->chip.parent = &pdev->dev;
pct->chip.base = -1; /* Dynamic allocation */
- match = of_match_device(abx500_gpio_match, &pdev->dev);
- if (!match) {
- dev_err(&pdev->dev, "gpio dt not matching\n");
- return -ENODEV;
- }
- id = (unsigned long)match->data;
+ id = (unsigned long)device_get_match_data(&pdev->dev);
/* Poke in other ASIC variants here */
switch (id) {
@@ -1079,12 +1074,11 @@ out_rem_chip:
* abx500_gpio_remove() - remove Ab8500-gpio driver
* @pdev: Platform device registered
*/
-static int abx500_gpio_remove(struct platform_device *pdev)
+static void abx500_gpio_remove(struct platform_device *pdev)
{
struct abx500_pinctrl *pct = platform_get_drvdata(pdev);
gpiochip_remove(&pct->chip);
- return 0;
}
static struct platform_driver abx500_gpio_driver = {
@@ -1093,7 +1087,7 @@ static struct platform_driver abx500_gpio_driver = {
.of_match_table = abx500_gpio_match,
},
.probe = abx500_gpio_probe,
- .remove = abx500_gpio_remove,
+ .remove_new = abx500_gpio_remove,
};
static int __init abx500_gpio_init(void)
diff --git a/drivers/pinctrl/nomadik/pinctrl-nomadik.c b/drivers/pinctrl/nomadik/pinctrl-nomadik.c
index 86a638077a..863732287b 100644
--- a/drivers/pinctrl/nomadik/pinctrl-nomadik.c
+++ b/drivers/pinctrl/nomadik/pinctrl-nomadik.c
@@ -16,9 +16,11 @@
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/kernel.h>
+#include <linux/of.h>
#include <linux/of_address.h>
-#include <linux/of_device.h>
+#include <linux/of_platform.h>
#include <linux/platform_device.h>
+#include <linux/property.h>
#include <linux/seq_file.h>
#include <linux/slab.h>
#include <linux/spinlock.h>
@@ -1838,7 +1840,6 @@ static int nmk_pinctrl_resume(struct device *dev)
static int nmk_pinctrl_probe(struct platform_device *pdev)
{
- const struct of_device_id *match;
struct device_node *np = pdev->dev.of_node;
struct device_node *prcm_np;
struct nmk_pinctrl *npct;
@@ -1849,10 +1850,7 @@ static int nmk_pinctrl_probe(struct platform_device *pdev)
if (!npct)
return -ENOMEM;
- match = of_match_device(nmk_pinctrl_match, &pdev->dev);
- if (!match)
- return -ENODEV;
- version = (unsigned int) match->data;
+ version = (unsigned int)device_get_match_data(&pdev->dev);
/* Poke in other ASIC variants here */
if (version == PINCTRL_NMK_STN8815)
diff --git a/drivers/pinctrl/nuvoton/Kconfig b/drivers/pinctrl/nuvoton/Kconfig
index 8fe61b3481..2abbfcec1f 100644
--- a/drivers/pinctrl/nuvoton/Kconfig
+++ b/drivers/pinctrl/nuvoton/Kconfig
@@ -2,8 +2,7 @@
config PINCTRL_WPCM450
tristate "Pinctrl and GPIO driver for Nuvoton WPCM450"
- depends on ARCH_WPCM450 || COMPILE_TEST
- depends on OF
+ depends on (ARCH_WPCM450 || COMPILE_TEST) && OF
select PINMUX
select PINCONF
select GENERIC_PINCONF
@@ -32,3 +31,17 @@ config PINCTRL_NPCM7XX
help
Say Y here to enable pin controller and GPIO support
for Nuvoton NPCM750/730/715/705 SoCs.
+
+config PINCTRL_NPCM8XX
+ tristate "Pinctrl and GPIO driver for Nuvoton NPCM8XX"
+ depends on (ARCH_NPCM || COMPILE_TEST) && OF
+ select PINMUX
+ select PINCONF
+ select GENERIC_PINCONF
+ select GPIOLIB
+ select GPIO_GENERIC
+ select GPIOLIB_IRQCHIP
+ help
+ Say Y or M here to enable pin controller and GPIO support for
+ the Nuvoton NPCM8XX SoC. This is strongly recommended when
+ building a kernel that will run on this chip.
diff --git a/drivers/pinctrl/nuvoton/Makefile b/drivers/pinctrl/nuvoton/Makefile
index 9e66f5dc74..08031eab0a 100644
--- a/drivers/pinctrl/nuvoton/Makefile
+++ b/drivers/pinctrl/nuvoton/Makefile
@@ -3,3 +3,4 @@
obj-$(CONFIG_PINCTRL_WPCM450) += pinctrl-wpcm450.o
obj-$(CONFIG_PINCTRL_NPCM7XX) += pinctrl-npcm7xx.o
+obj-$(CONFIG_PINCTRL_NPCM8XX) += pinctrl-npcm8xx.o
diff --git a/drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c b/drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c
index 843ffcd968..1e658721aa 100644
--- a/drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c
+++ b/drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c
@@ -171,7 +171,7 @@ static int npcmgpio_direction_input(struct gpio_chip *chip, unsigned int offset)
struct npcm7xx_gpio *bank = gpiochip_get_data(chip);
int ret;
- ret = pinctrl_gpio_direction_input(offset + chip->base);
+ ret = pinctrl_gpio_direction_input(chip, offset);
if (ret)
return ret;
@@ -188,7 +188,7 @@ static int npcmgpio_direction_output(struct gpio_chip *chip,
dev_dbg(chip->parent, "gpio_direction_output: offset%d = %x\n", offset,
value);
- ret = pinctrl_gpio_direction_output(offset + chip->base);
+ ret = pinctrl_gpio_direction_output(chip, offset);
if (ret)
return ret;
@@ -201,19 +201,13 @@ static int npcmgpio_gpio_request(struct gpio_chip *chip, unsigned int offset)
int ret;
dev_dbg(chip->parent, "gpio_request: offset%d\n", offset);
- ret = pinctrl_gpio_request(offset + chip->base);
+ ret = pinctrl_gpio_request(chip, offset);
if (ret)
return ret;
return bank->request(chip, offset);
}
-static void npcmgpio_gpio_free(struct gpio_chip *chip, unsigned int offset)
-{
- dev_dbg(chip->parent, "gpio_free: offset%d\n", offset);
- pinctrl_gpio_free(offset + chip->base);
-}
-
static void npcmgpio_irq_handler(struct irq_desc *desc)
{
struct gpio_chip *gc;
@@ -1588,19 +1582,6 @@ static int npcm7xx_get_group_pins(struct pinctrl_dev *pctldev,
return 0;
}
-static int npcm7xx_dt_node_to_map(struct pinctrl_dev *pctldev,
- struct device_node *np_config,
- struct pinctrl_map **map,
- u32 *num_maps)
-{
- struct npcm7xx_pinctrl *npcm = pinctrl_dev_get_drvdata(pctldev);
-
- dev_dbg(npcm->dev, "dt_node_to_map: %s\n", np_config->name);
- return pinconf_generic_dt_node_to_map(pctldev, np_config,
- map, num_maps,
- PIN_MAP_TYPE_INVALID);
-}
-
static void npcm7xx_dt_free_map(struct pinctrl_dev *pctldev,
struct pinctrl_map *map, u32 num_maps)
{
@@ -1612,7 +1593,7 @@ static const struct pinctrl_ops npcm7xx_pinctrl_ops = {
.get_group_name = npcm7xx_get_group_name,
.get_group_pins = npcm7xx_get_group_pins,
.pin_dbg_show = npcm7xx_pin_dbg_show,
- .dt_node_to_map = npcm7xx_dt_node_to_map,
+ .dt_node_to_map = pinconf_generic_dt_node_to_map_all,
.dt_free_map = npcm7xx_dt_free_map,
};
@@ -1929,7 +1910,7 @@ static int npcm7xx_gpio_of(struct npcm7xx_pinctrl *pctrl)
pctrl->gpio_bank[id].gc.direction_output = npcmgpio_direction_output;
pctrl->gpio_bank[id].request = pctrl->gpio_bank[id].gc.request;
pctrl->gpio_bank[id].gc.request = npcmgpio_gpio_request;
- pctrl->gpio_bank[id].gc.free = npcmgpio_gpio_free;
+ pctrl->gpio_bank[id].gc.free = pinctrl_gpio_free;
id++;
}
diff --git a/drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c b/drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c
new file mode 100644
index 0000000000..a377d36b0e
--- /dev/null
+++ b/drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c
@@ -0,0 +1,2486 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (c) 2020 Nuvoton Technology corporation.
+
+#include <linux/bits.h>
+#include <linux/device.h>
+#include <linux/gpio/driver.h>
+#include <linux/interrupt.h>
+#include <linux/irq.h>
+#include <linux/mfd/syscon.h>
+#include <linux/module.h>
+#include <linux/debugfs.h>
+#include <linux/seq_file.h>
+#include <linux/mod_devicetable.h>
+#include <linux/pinctrl/machine.h>
+#include <linux/pinctrl/pinconf.h>
+#include <linux/pinctrl/pinconf-generic.h>
+#include <linux/pinctrl/pinctrl.h>
+#include <linux/pinctrl/pinmux.h>
+#include <linux/pinctrl/consumer.h>
+#include <linux/platform_device.h>
+#include <linux/property.h>
+#include <linux/regmap.h>
+
+/* GCR registers */
+#define NPCM8XX_GCR_SRCNT 0x068
+#define NPCM8XX_GCR_FLOCKR1 0x074
+#define NPCM8XX_GCR_DSCNT 0x078
+#define NPCM8XX_GCR_I2CSEGSEL 0x0e0
+#define NPCM8XX_GCR_MFSEL1 0x260
+#define NPCM8XX_GCR_MFSEL2 0x264
+#define NPCM8XX_GCR_MFSEL3 0x268
+#define NPCM8XX_GCR_MFSEL4 0x26c
+#define NPCM8XX_GCR_MFSEL5 0x270
+#define NPCM8XX_GCR_MFSEL6 0x274
+#define NPCM8XX_GCR_MFSEL7 0x278
+
+#define SRCNT_ESPI BIT(3)
+
+/* GPIO registers */
+#define NPCM8XX_GP_N_TLOCK1 0x00
+#define NPCM8XX_GP_N_DIN 0x04
+#define NPCM8XX_GP_N_POL 0x08
+#define NPCM8XX_GP_N_DOUT 0x0c
+#define NPCM8XX_GP_N_OE 0x10
+#define NPCM8XX_GP_N_OTYP 0x14
+#define NPCM8XX_GP_N_MP 0x18
+#define NPCM8XX_GP_N_PU 0x1c
+#define NPCM8XX_GP_N_PD 0x20
+#define NPCM8XX_GP_N_DBNC 0x24
+#define NPCM8XX_GP_N_EVTYP 0x28
+#define NPCM8XX_GP_N_EVBE 0x2c
+#define NPCM8XX_GP_N_OBL0 0x30
+#define NPCM8XX_GP_N_OBL1 0x34
+#define NPCM8XX_GP_N_OBL2 0x38
+#define NPCM8XX_GP_N_OBL3 0x3c
+#define NPCM8XX_GP_N_EVEN 0x40
+#define NPCM8XX_GP_N_EVENS 0x44
+#define NPCM8XX_GP_N_EVENC 0x48
+#define NPCM8XX_GP_N_EVST 0x4c
+#define NPCM8XX_GP_N_SPLCK 0x50
+#define NPCM8XX_GP_N_MPLCK 0x54
+#define NPCM8XX_GP_N_IEM 0x58
+#define NPCM8XX_GP_N_OSRC 0x5c
+#define NPCM8XX_GP_N_ODSC 0x60
+#define NPCM8XX_GP_N_DOS 0x68
+#define NPCM8XX_GP_N_DOC 0x6c
+#define NPCM8XX_GP_N_OES 0x70
+#define NPCM8XX_GP_N_OEC 0x74
+#define NPCM8XX_GP_N_DBNCS0 0x80
+#define NPCM8XX_GP_N_DBNCS1 0x84
+#define NPCM8XX_GP_N_DBNCP0 0x88
+#define NPCM8XX_GP_N_DBNCP1 0x8c
+#define NPCM8XX_GP_N_DBNCP2 0x90
+#define NPCM8XX_GP_N_DBNCP3 0x94
+#define NPCM8XX_GP_N_TLOCK2 0xac
+
+#define NPCM8XX_GPIO_PER_BANK 32
+#define NPCM8XX_GPIO_BANK_NUM 8
+#define NPCM8XX_GCR_NONE 0
+
+#define NPCM8XX_DEBOUNCE_MAX 4
+#define NPCM8XX_DEBOUNCE_NSEC 40
+#define NPCM8XX_DEBOUNCE_VAL_MASK GENMASK(23, 4)
+#define NPCM8XX_DEBOUNCE_MAX_VAL 0xFFFFF7
+
+/* Structure for register banks */
+struct debounce_time {
+ bool set_val[NPCM8XX_DEBOUNCE_MAX];
+ u32 nanosec_val[NPCM8XX_DEBOUNCE_MAX];
+};
+
+struct npcm8xx_gpio {
+ struct gpio_chip gc;
+ void __iomem *base;
+ struct debounce_time debounce;
+ int irqbase;
+ int irq;
+ struct irq_chip irq_chip;
+ u32 pinctrl_id;
+ int (*direction_input)(struct gpio_chip *chip, unsigned int offset);
+ int (*direction_output)(struct gpio_chip *chip, unsigned int offset,
+ int value);
+ int (*request)(struct gpio_chip *chip, unsigned int offset);
+ void (*free)(struct gpio_chip *chip, unsigned int offset);
+};
+
+struct npcm8xx_pinctrl {
+ struct pinctrl_dev *pctldev;
+ struct device *dev;
+ struct npcm8xx_gpio gpio_bank[NPCM8XX_GPIO_BANK_NUM];
+ struct irq_domain *domain;
+ struct regmap *gcr_regmap;
+ void __iomem *regs;
+ u32 bank_num;
+};
+
+/* GPIO handling in the pinctrl driver */
+static void npcm_gpio_set(struct gpio_chip *gc, void __iomem *reg,
+ unsigned int pinmask)
+{
+ unsigned long flags;
+
+ raw_spin_lock_irqsave(&gc->bgpio_lock, flags);
+ iowrite32(ioread32(reg) | pinmask, reg);
+ raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags);
+}
+
+static void npcm_gpio_clr(struct gpio_chip *gc, void __iomem *reg,
+ unsigned int pinmask)
+{
+ unsigned long flags;
+
+ raw_spin_lock_irqsave(&gc->bgpio_lock, flags);
+ iowrite32(ioread32(reg) & ~pinmask, reg);
+ raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags);
+}
+
+static void npcmgpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
+{
+ struct npcm8xx_gpio *bank = gpiochip_get_data(chip);
+
+ seq_printf(s, "DIN :%.8x DOUT:%.8x IE :%.8x OE :%.8x\n",
+ ioread32(bank->base + NPCM8XX_GP_N_DIN),
+ ioread32(bank->base + NPCM8XX_GP_N_DOUT),
+ ioread32(bank->base + NPCM8XX_GP_N_IEM),
+ ioread32(bank->base + NPCM8XX_GP_N_OE));
+ seq_printf(s, "PU :%.8x PD :%.8x DB :%.8x POL :%.8x\n",
+ ioread32(bank->base + NPCM8XX_GP_N_PU),
+ ioread32(bank->base + NPCM8XX_GP_N_PD),
+ ioread32(bank->base + NPCM8XX_GP_N_DBNC),
+ ioread32(bank->base + NPCM8XX_GP_N_POL));
+ seq_printf(s, "ETYP:%.8x EVBE:%.8x EVEN:%.8x EVST:%.8x\n",
+ ioread32(bank->base + NPCM8XX_GP_N_EVTYP),
+ ioread32(bank->base + NPCM8XX_GP_N_EVBE),
+ ioread32(bank->base + NPCM8XX_GP_N_EVEN),
+ ioread32(bank->base + NPCM8XX_GP_N_EVST));
+ seq_printf(s, "OTYP:%.8x OSRC:%.8x ODSC:%.8x\n",
+ ioread32(bank->base + NPCM8XX_GP_N_OTYP),
+ ioread32(bank->base + NPCM8XX_GP_N_OSRC),
+ ioread32(bank->base + NPCM8XX_GP_N_ODSC));
+ seq_printf(s, "OBL0:%.8x OBL1:%.8x OBL2:%.8x OBL3:%.8x\n",
+ ioread32(bank->base + NPCM8XX_GP_N_OBL0),
+ ioread32(bank->base + NPCM8XX_GP_N_OBL1),
+ ioread32(bank->base + NPCM8XX_GP_N_OBL2),
+ ioread32(bank->base + NPCM8XX_GP_N_OBL3));
+ seq_printf(s, "SLCK:%.8x MLCK:%.8x\n",
+ ioread32(bank->base + NPCM8XX_GP_N_SPLCK),
+ ioread32(bank->base + NPCM8XX_GP_N_MPLCK));
+}
+
+static int npcmgpio_direction_input(struct gpio_chip *chip, unsigned int offset)
+{
+ struct npcm8xx_gpio *bank = gpiochip_get_data(chip);
+ int ret;
+
+ ret = pinctrl_gpio_direction_input(chip, offset);
+ if (ret)
+ return ret;
+
+ return bank->direction_input(chip, offset);
+}
+
+static int npcmgpio_direction_output(struct gpio_chip *chip,
+ unsigned int offset, int value)
+{
+ struct npcm8xx_gpio *bank = gpiochip_get_data(chip);
+ int ret;
+
+ ret = pinctrl_gpio_direction_output(chip, offset);
+ if (ret)
+ return ret;
+
+ return bank->direction_output(chip, offset, value);
+}
+
+static int npcmgpio_gpio_request(struct gpio_chip *chip, unsigned int offset)
+{
+ struct npcm8xx_gpio *bank = gpiochip_get_data(chip);
+ int ret;
+
+ ret = pinctrl_gpio_request(chip, offset);
+ if (ret)
+ return ret;
+
+ return bank->request(chip, offset);
+}
+
+static void npcmgpio_irq_handler(struct irq_desc *desc)
+{
+ unsigned long sts, en, bit;
+ struct npcm8xx_gpio *bank;
+ struct irq_chip *chip;
+ struct gpio_chip *gc;
+
+ gc = irq_desc_get_handler_data(desc);
+ bank = gpiochip_get_data(gc);
+ chip = irq_desc_get_chip(desc);
+
+ chained_irq_enter(chip, desc);
+ sts = ioread32(bank->base + NPCM8XX_GP_N_EVST);
+ en = ioread32(bank->base + NPCM8XX_GP_N_EVEN);
+ sts &= en;
+ for_each_set_bit(bit, &sts, NPCM8XX_GPIO_PER_BANK)
+ generic_handle_domain_irq(gc->irq.domain, bit);
+ chained_irq_exit(chip, desc);
+}
+
+static int npcmgpio_set_irq_type(struct irq_data *d, unsigned int type)
+{
+ struct npcm8xx_gpio *bank =
+ gpiochip_get_data(irq_data_get_irq_chip_data(d));
+ unsigned int gpio = BIT(irqd_to_hwirq(d));
+
+ switch (type) {
+ case IRQ_TYPE_EDGE_RISING:
+ npcm_gpio_clr(&bank->gc, bank->base + NPCM8XX_GP_N_EVBE, gpio);
+ npcm_gpio_clr(&bank->gc, bank->base + NPCM8XX_GP_N_POL, gpio);
+ break;
+ case IRQ_TYPE_EDGE_FALLING:
+ npcm_gpio_clr(&bank->gc, bank->base + NPCM8XX_GP_N_EVBE, gpio);
+ npcm_gpio_set(&bank->gc, bank->base + NPCM8XX_GP_N_POL, gpio);
+ break;
+ case IRQ_TYPE_EDGE_BOTH:
+ npcm_gpio_set(&bank->gc, bank->base + NPCM8XX_GP_N_EVBE, gpio);
+ break;
+ case IRQ_TYPE_LEVEL_LOW:
+ npcm_gpio_set(&bank->gc, bank->base + NPCM8XX_GP_N_POL, gpio);
+ break;
+ case IRQ_TYPE_LEVEL_HIGH:
+ npcm_gpio_clr(&bank->gc, bank->base + NPCM8XX_GP_N_POL, gpio);
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ if (type & IRQ_TYPE_LEVEL_MASK) {
+ npcm_gpio_clr(&bank->gc, bank->base + NPCM8XX_GP_N_EVTYP, gpio);
+ irq_set_handler_locked(d, handle_level_irq);
+ } else if (type & IRQ_TYPE_EDGE_BOTH) {
+ npcm_gpio_set(&bank->gc, bank->base + NPCM8XX_GP_N_EVTYP, gpio);
+ irq_set_handler_locked(d, handle_edge_irq);
+ }
+
+ return 0;
+}
+
+static void npcmgpio_irq_ack(struct irq_data *d)
+{
+ struct npcm8xx_gpio *bank =
+ gpiochip_get_data(irq_data_get_irq_chip_data(d));
+ unsigned int gpio = irqd_to_hwirq(d);
+
+ iowrite32(BIT(gpio), bank->base + NPCM8XX_GP_N_EVST);
+}
+
+static void npcmgpio_irq_mask(struct irq_data *d)
+{
+ struct npcm8xx_gpio *bank =
+ gpiochip_get_data(irq_data_get_irq_chip_data(d));
+ unsigned int gpio = irqd_to_hwirq(d);
+
+ iowrite32(BIT(gpio), bank->base + NPCM8XX_GP_N_EVENC);
+}
+
+static void npcmgpio_irq_unmask(struct irq_data *d)
+{
+ struct npcm8xx_gpio *bank =
+ gpiochip_get_data(irq_data_get_irq_chip_data(d));
+ unsigned int gpio = irqd_to_hwirq(d);
+
+ iowrite32(BIT(gpio), bank->base + NPCM8XX_GP_N_EVENS);
+}
+
+static unsigned int npcmgpio_irq_startup(struct irq_data *d)
+{
+ struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
+ unsigned int gpio = irqd_to_hwirq(d);
+
+ /* active-high, input, clear interrupt, enable interrupt */
+ npcmgpio_direction_input(gc, gpio);
+ npcmgpio_irq_ack(d);
+ npcmgpio_irq_unmask(d);
+
+ return 0;
+}
+
+static struct irq_chip npcmgpio_irqchip = {
+ .name = "NPCM8XX-GPIO-IRQ",
+ .irq_ack = npcmgpio_irq_ack,
+ .irq_unmask = npcmgpio_irq_unmask,
+ .irq_mask = npcmgpio_irq_mask,
+ .irq_set_type = npcmgpio_set_irq_type,
+ .irq_startup = npcmgpio_irq_startup,
+ .flags = IRQCHIP_MASK_ON_SUSPEND | IRQCHIP_IMMUTABLE,
+ GPIOCHIP_IRQ_RESOURCE_HELPERS,
+};
+
+static const int gpi36_pins[] = { 58 };
+static const int gpi35_pins[] = { 58 };
+
+static const int tp_jtag3_pins[] = { 44, 62, 45, 46 };
+static const int tp_uart_pins[] = { 50, 51 };
+
+static const int tp_smb2_pins[] = { 24, 25 };
+static const int tp_smb1_pins[] = { 142, 143 };
+
+static const int tp_gpio7_pins[] = { 96 };
+static const int tp_gpio6_pins[] = { 97 };
+static const int tp_gpio5_pins[] = { 98 };
+static const int tp_gpio4_pins[] = { 99 };
+static const int tp_gpio3_pins[] = { 100 };
+static const int tp_gpio2_pins[] = { 16 };
+static const int tp_gpio1_pins[] = { 9 };
+static const int tp_gpio0_pins[] = { 8 };
+
+static const int tp_gpio2b_pins[] = { 101 };
+static const int tp_gpio1b_pins[] = { 92 };
+static const int tp_gpio0b_pins[] = { 91 };
+
+static const int vgadig_pins[] = { 102, 103, 104, 105 };
+
+static const int nbu1crts_pins[] = { 44, 62 };
+
+static const int fm2_pins[] = { 224, 225, 226, 227, 228, 229, 230 };
+static const int fm1_pins[] = { 175, 176, 177, 203, 191, 192, 233 };
+static const int fm0_pins[] = { 194, 195, 196, 202, 199, 198, 197 };
+
+static const int gpio1836_pins[] = { 183, 184, 185, 186 };
+static const int gpio1889_pins[] = { 188, 189 };
+static const int gpo187_pins[] = { 187 };
+
+static const int cp1urxd_pins[] = { 41 };
+static const int r3rxer_pins[] = { 212 };
+
+static const int cp1gpio2c_pins[] = { 101 };
+static const int cp1gpio3c_pins[] = { 100 };
+
+static const int cp1gpio0b_pins[] = { 127 };
+static const int cp1gpio1b_pins[] = { 126 };
+static const int cp1gpio2b_pins[] = { 125 };
+static const int cp1gpio3b_pins[] = { 124 };
+static const int cp1gpio4b_pins[] = { 99 };
+static const int cp1gpio5b_pins[] = { 98 };
+static const int cp1gpio6b_pins[] = { 97 };
+static const int cp1gpio7b_pins[] = { 96 };
+
+static const int cp1gpio0_pins[] = { };
+static const int cp1gpio1_pins[] = { };
+static const int cp1gpio2_pins[] = { };
+static const int cp1gpio3_pins[] = { };
+static const int cp1gpio4_pins[] = { };
+static const int cp1gpio5_pins[] = { 17 };
+static const int cp1gpio6_pins[] = { 91 };
+static const int cp1gpio7_pins[] = { 92 };
+
+static const int cp1utxd_pins[] = { 42 };
+
+static const int spi1cs3_pins[] = { 192 };
+static const int spi1cs2_pins[] = { 191 };
+static const int spi1cs1_pins[] = { 233 };
+static const int spi1cs0_pins[] = { 203 };
+
+static const int spi1d23_pins[] = { 191, 192 };
+
+static const int j2j3_pins[] = { 44, 62, 45, 46 };
+
+static const int r3oen_pins[] = { 213 };
+static const int r2oen_pins[] = { 90 };
+static const int r1oen_pins[] = { 56 };
+static const int bu4b_pins[] = { 98, 99 };
+static const int bu4_pins[] = { 54, 55 };
+static const int bu5b_pins[] = { 100, 101 };
+static const int bu5_pins[] = { 52, 53 };
+static const int bu6_pins[] = { 50, 51 };
+static const int rmii3_pins[] = { 110, 111, 209, 211, 210, 214, 215 };
+
+static const int jm1_pins[] = { 136, 137, 138, 139, 140 };
+static const int jm2_pins[] = { 251 };
+
+static const int tpgpio5b_pins[] = { 58 };
+static const int tpgpio4b_pins[] = { 57 };
+
+static const int clkrun_pins[] = { 162 };
+
+static const int i3c5_pins[] = { 106, 107 };
+static const int i3c4_pins[] = { 33, 34 };
+static const int i3c3_pins[] = { 246, 247 };
+static const int i3c2_pins[] = { 244, 245 };
+static const int i3c1_pins[] = { 242, 243 };
+static const int i3c0_pins[] = { 240, 241 };
+
+static const int hsi1a_pins[] = { 43, 63 };
+static const int hsi2a_pins[] = { 48, 49 };
+static const int hsi1b_pins[] = { 44, 62 };
+static const int hsi2b_pins[] = { 50, 51 };
+static const int hsi1c_pins[] = { 45, 46, 47, 61 };
+static const int hsi2c_pins[] = { 45, 46, 47, 61 };
+
+static const int smb0_pins[] = { 115, 114 };
+static const int smb0b_pins[] = { 195, 194 };
+static const int smb0c_pins[] = { 202, 196 };
+static const int smb0d_pins[] = { 198, 199 };
+static const int smb0den_pins[] = { 197 };
+static const int smb1_pins[] = { 117, 116 };
+static const int smb1b_pins[] = { 126, 127 };
+static const int smb1c_pins[] = { 124, 125 };
+static const int smb1d_pins[] = { 4, 5 };
+static const int smb2_pins[] = { 119, 118 };
+static const int smb2b_pins[] = { 122, 123 };
+static const int smb2c_pins[] = { 120, 121 };
+static const int smb2d_pins[] = { 6, 7 };
+static const int smb3_pins[] = { 30, 31 };
+static const int smb3b_pins[] = { 39, 40 };
+static const int smb3c_pins[] = { 37, 38 };
+static const int smb3d_pins[] = { 59, 60 };
+static const int smb4_pins[] = { 28, 29 };
+static const int smb4b_pins[] = { 18, 19 };
+static const int smb4c_pins[] = { 20, 21 };
+static const int smb4d_pins[] = { 22, 23 };
+static const int smb4den_pins[] = { 17 };
+static const int smb5_pins[] = { 26, 27 };
+static const int smb5b_pins[] = { 13, 12 };
+static const int smb5c_pins[] = { 15, 14 };
+static const int smb5d_pins[] = { 94, 93 };
+static const int ga20kbc_pins[] = { 94, 93 };
+
+static const int smb6_pins[] = { 172, 171 };
+static const int smb6b_pins[] = { 2, 3 };
+static const int smb6c_pins[] = { 0, 1 };
+static const int smb6d_pins[] = { 10, 11 };
+static const int smb7_pins[] = { 174, 173 };
+static const int smb7b_pins[] = { 16, 141 };
+static const int smb7c_pins[] = { 24, 25 };
+static const int smb7d_pins[] = { 142, 143 };
+static const int smb8_pins[] = { 129, 128 };
+static const int smb9_pins[] = { 131, 130 };
+static const int smb10_pins[] = { 133, 132 };
+static const int smb11_pins[] = { 135, 134 };
+static const int smb12_pins[] = { 221, 220 };
+static const int smb13_pins[] = { 223, 222 };
+static const int smb14_pins[] = { 22, 23 };
+static const int smb14b_pins[] = { 32, 187 };
+static const int smb15_pins[] = { 20, 21 };
+static const int smb15b_pins[] = { 192, 191 };
+
+static const int smb16_pins[] = { 10, 11 };
+static const int smb16b_pins[] = { 218, 219 };
+static const int smb17_pins[] = { 3, 2 };
+static const int smb18_pins[] = { 0, 1 };
+static const int smb19_pins[] = { 60, 59 };
+static const int smb20_pins[] = { 234, 235 };
+static const int smb21_pins[] = { 169, 170 };
+static const int smb22_pins[] = { 40, 39 };
+static const int smb23_pins[] = { 38, 37 };
+static const int smb23b_pins[] = { 134, 135 };
+
+static const int fanin0_pins[] = { 64 };
+static const int fanin1_pins[] = { 65 };
+static const int fanin2_pins[] = { 66 };
+static const int fanin3_pins[] = { 67 };
+static const int fanin4_pins[] = { 68 };
+static const int fanin5_pins[] = { 69 };
+static const int fanin6_pins[] = { 70 };
+static const int fanin7_pins[] = { 71 };
+static const int fanin8_pins[] = { 72 };
+static const int fanin9_pins[] = { 73 };
+static const int fanin10_pins[] = { 74 };
+static const int fanin11_pins[] = { 75 };
+static const int fanin12_pins[] = { 76 };
+static const int fanin13_pins[] = { 77 };
+static const int fanin14_pins[] = { 78 };
+static const int fanin15_pins[] = { 79 };
+static const int faninx_pins[] = { 175, 176, 177, 203 };
+
+static const int pwm0_pins[] = { 80 };
+static const int pwm1_pins[] = { 81 };
+static const int pwm2_pins[] = { 82 };
+static const int pwm3_pins[] = { 83 };
+static const int pwm4_pins[] = { 144 };
+static const int pwm5_pins[] = { 145 };
+static const int pwm6_pins[] = { 146 };
+static const int pwm7_pins[] = { 147 };
+static const int pwm8_pins[] = { 220 };
+static const int pwm9_pins[] = { 221 };
+static const int pwm10_pins[] = { 234 };
+static const int pwm11_pins[] = { 235 };
+
+static const int uart1_pins[] = { 43, 45, 46, 47, 61, 62, 63 };
+static const int uart2_pins[] = { 48, 49, 50, 51, 52, 53, 54, 55 };
+
+static const int sg1mdio_pins[] = { 108, 109 };
+
+static const int rg2_pins[] = { 110, 111, 112, 113, 208, 209, 210, 211, 212,
+ 213, 214, 215 };
+static const int rg2mdio_pins[] = { 216, 217 };
+
+static const int ddr_pins[] = { 110, 111, 112, 113, 208, 209, 210, 211, 212,
+ 213, 214, 215, 216, 217 };
+
+static const int iox1_pins[] = { 0, 1, 2, 3 };
+static const int iox2_pins[] = { 4, 5, 6, 7 };
+static const int ioxh_pins[] = { 10, 11, 24, 25 };
+
+static const int mmc_pins[] = { 152, 154, 156, 157, 158, 159 };
+static const int mmcwp_pins[] = { 153 };
+static const int mmccd_pins[] = { 155 };
+static const int mmcrst_pins[] = { 155 };
+static const int mmc8_pins[] = { 148, 149, 150, 151 };
+
+static const int r1_pins[] = { 178, 179, 180, 181, 182, 193, 201 };
+static const int r1err_pins[] = { 56 };
+static const int r1md_pins[] = { 57, 58 };
+static const int r2_pins[] = { 84, 85, 86, 87, 88, 89, 200 };
+static const int r2err_pins[] = { 90 };
+static const int r2md_pins[] = { 91, 92 };
+static const int sd1_pins[] = { 136, 137, 138, 139, 140, 141, 142, 143 };
+static const int sd1pwr_pins[] = { 143 };
+
+static const int wdog1_pins[] = { 218 };
+static const int wdog2_pins[] = { 219 };
+
+static const int bmcuart0a_pins[] = { 41, 42 };
+static const int bmcuart0b_pins[] = { 48, 49 };
+static const int bmcuart1_pins[] = { 43, 44, 62, 63 };
+
+static const int scipme_pins[] = { 169 };
+static const int smi_pins[] = { 170 };
+static const int serirq_pins[] = { 168 };
+
+static const int clkout_pins[] = { 160 };
+static const int clkreq_pins[] = { 231 };
+
+static const int jtag2_pins[] = { 43, 44, 45, 46, 47 };
+static const int gspi_pins[] = { 12, 13, 14, 15 };
+
+static const int spix_pins[] = { 224, 225, 226, 227, 229, 230 };
+static const int spixcs1_pins[] = { 228 };
+
+static const int spi1_pins[] = { 175, 176, 177 };
+static const int pspi_pins[] = { 17, 18, 19 };
+
+static const int spi0cs1_pins[] = { 32 };
+
+static const int spi3_pins[] = { 183, 184, 185, 186 };
+static const int spi3cs1_pins[] = { 187 };
+static const int spi3quad_pins[] = { 188, 189 };
+static const int spi3cs2_pins[] = { 188 };
+static const int spi3cs3_pins[] = { 189 };
+
+static const int ddc_pins[] = { 204, 205, 206, 207 };
+
+static const int lpc_pins[] = { 95, 161, 163, 164, 165, 166, 167 };
+static const int lpcclk_pins[] = { 168 };
+static const int espi_pins[] = { 95, 161, 163, 164, 165, 166, 167, 168 };
+
+static const int lkgpo0_pins[] = { 16 };
+static const int lkgpo1_pins[] = { 8 };
+static const int lkgpo2_pins[] = { 9 };
+
+static const int nprd_smi_pins[] = { 190 };
+
+static const int hgpio0_pins[] = { 20 };
+static const int hgpio1_pins[] = { 21 };
+static const int hgpio2_pins[] = { 22 };
+static const int hgpio3_pins[] = { 23 };
+static const int hgpio4_pins[] = { 24 };
+static const int hgpio5_pins[] = { 25 };
+static const int hgpio6_pins[] = { 59 };
+static const int hgpio7_pins[] = { 60 };
+
+/*
+ * pin: name, number
+ * group: name, npins, pins
+ * function: name, ngroups, groups
+ */
+struct npcm8xx_pingroup {
+ const char *name;
+ const unsigned int *pins;
+ int npins;
+};
+
+#define NPCM8XX_GRPS \
+ NPCM8XX_GRP(gpi36), \
+ NPCM8XX_GRP(gpi35), \
+ NPCM8XX_GRP(tp_jtag3), \
+ NPCM8XX_GRP(tp_uart), \
+ NPCM8XX_GRP(tp_smb2), \
+ NPCM8XX_GRP(tp_smb1), \
+ NPCM8XX_GRP(tp_gpio7), \
+ NPCM8XX_GRP(tp_gpio6), \
+ NPCM8XX_GRP(tp_gpio5), \
+ NPCM8XX_GRP(tp_gpio4), \
+ NPCM8XX_GRP(tp_gpio3), \
+ NPCM8XX_GRP(tp_gpio2), \
+ NPCM8XX_GRP(tp_gpio1), \
+ NPCM8XX_GRP(tp_gpio0), \
+ NPCM8XX_GRP(tp_gpio2b), \
+ NPCM8XX_GRP(tp_gpio1b), \
+ NPCM8XX_GRP(tp_gpio0b), \
+ NPCM8XX_GRP(vgadig), \
+ NPCM8XX_GRP(nbu1crts), \
+ NPCM8XX_GRP(fm2), \
+ NPCM8XX_GRP(fm1), \
+ NPCM8XX_GRP(fm0), \
+ NPCM8XX_GRP(gpio1836), \
+ NPCM8XX_GRP(gpio1889), \
+ NPCM8XX_GRP(gpo187), \
+ NPCM8XX_GRP(cp1urxd), \
+ NPCM8XX_GRP(r3rxer), \
+ NPCM8XX_GRP(cp1gpio2c), \
+ NPCM8XX_GRP(cp1gpio3c), \
+ NPCM8XX_GRP(cp1gpio0b), \
+ NPCM8XX_GRP(cp1gpio1b), \
+ NPCM8XX_GRP(cp1gpio2b), \
+ NPCM8XX_GRP(cp1gpio3b), \
+ NPCM8XX_GRP(cp1gpio4b), \
+ NPCM8XX_GRP(cp1gpio5b), \
+ NPCM8XX_GRP(cp1gpio6b), \
+ NPCM8XX_GRP(cp1gpio7b), \
+ NPCM8XX_GRP(cp1gpio0), \
+ NPCM8XX_GRP(cp1gpio1), \
+ NPCM8XX_GRP(cp1gpio2), \
+ NPCM8XX_GRP(cp1gpio3), \
+ NPCM8XX_GRP(cp1gpio4), \
+ NPCM8XX_GRP(cp1gpio5), \
+ NPCM8XX_GRP(cp1gpio6), \
+ NPCM8XX_GRP(cp1gpio7), \
+ NPCM8XX_GRP(cp1utxd), \
+ NPCM8XX_GRP(spi1cs3), \
+ NPCM8XX_GRP(spi1cs2), \
+ NPCM8XX_GRP(spi1cs1), \
+ NPCM8XX_GRP(spi1cs0), \
+ NPCM8XX_GRP(spi1d23), \
+ NPCM8XX_GRP(j2j3), \
+ NPCM8XX_GRP(r3oen), \
+ NPCM8XX_GRP(r2oen), \
+ NPCM8XX_GRP(r1oen), \
+ NPCM8XX_GRP(bu4b), \
+ NPCM8XX_GRP(bu4), \
+ NPCM8XX_GRP(bu5b), \
+ NPCM8XX_GRP(bu5), \
+ NPCM8XX_GRP(bu6), \
+ NPCM8XX_GRP(rmii3), \
+ NPCM8XX_GRP(jm1), \
+ NPCM8XX_GRP(jm2), \
+ NPCM8XX_GRP(tpgpio5b), \
+ NPCM8XX_GRP(tpgpio4b), \
+ NPCM8XX_GRP(clkrun), \
+ NPCM8XX_GRP(i3c5), \
+ NPCM8XX_GRP(i3c4), \
+ NPCM8XX_GRP(i3c3), \
+ NPCM8XX_GRP(i3c2), \
+ NPCM8XX_GRP(i3c1), \
+ NPCM8XX_GRP(i3c0), \
+ NPCM8XX_GRP(hsi1a), \
+ NPCM8XX_GRP(hsi2a), \
+ NPCM8XX_GRP(hsi1b), \
+ NPCM8XX_GRP(hsi2b), \
+ NPCM8XX_GRP(hsi1c), \
+ NPCM8XX_GRP(hsi2c), \
+ NPCM8XX_GRP(smb0), \
+ NPCM8XX_GRP(smb0b), \
+ NPCM8XX_GRP(smb0c), \
+ NPCM8XX_GRP(smb0d), \
+ NPCM8XX_GRP(smb0den), \
+ NPCM8XX_GRP(smb1), \
+ NPCM8XX_GRP(smb1b), \
+ NPCM8XX_GRP(smb1c), \
+ NPCM8XX_GRP(smb1d), \
+ NPCM8XX_GRP(smb2), \
+ NPCM8XX_GRP(smb2b), \
+ NPCM8XX_GRP(smb2c), \
+ NPCM8XX_GRP(smb2d), \
+ NPCM8XX_GRP(smb3), \
+ NPCM8XX_GRP(smb3b), \
+ NPCM8XX_GRP(smb3c), \
+ NPCM8XX_GRP(smb3d), \
+ NPCM8XX_GRP(smb4), \
+ NPCM8XX_GRP(smb4b), \
+ NPCM8XX_GRP(smb4c), \
+ NPCM8XX_GRP(smb4d), \
+ NPCM8XX_GRP(smb4den), \
+ NPCM8XX_GRP(smb5), \
+ NPCM8XX_GRP(smb5b), \
+ NPCM8XX_GRP(smb5c), \
+ NPCM8XX_GRP(smb5d), \
+ NPCM8XX_GRP(ga20kbc), \
+ NPCM8XX_GRP(smb6), \
+ NPCM8XX_GRP(smb6b), \
+ NPCM8XX_GRP(smb6c), \
+ NPCM8XX_GRP(smb6d), \
+ NPCM8XX_GRP(smb7), \
+ NPCM8XX_GRP(smb7b), \
+ NPCM8XX_GRP(smb7c), \
+ NPCM8XX_GRP(smb7d), \
+ NPCM8XX_GRP(smb8), \
+ NPCM8XX_GRP(smb9), \
+ NPCM8XX_GRP(smb10), \
+ NPCM8XX_GRP(smb11), \
+ NPCM8XX_GRP(smb12), \
+ NPCM8XX_GRP(smb13), \
+ NPCM8XX_GRP(smb14), \
+ NPCM8XX_GRP(smb14b), \
+ NPCM8XX_GRP(smb15), \
+ NPCM8XX_GRP(smb15b), \
+ NPCM8XX_GRP(smb16), \
+ NPCM8XX_GRP(smb16b), \
+ NPCM8XX_GRP(smb17), \
+ NPCM8XX_GRP(smb18), \
+ NPCM8XX_GRP(smb19), \
+ NPCM8XX_GRP(smb20), \
+ NPCM8XX_GRP(smb21), \
+ NPCM8XX_GRP(smb22), \
+ NPCM8XX_GRP(smb23), \
+ NPCM8XX_GRP(smb23b), \
+ NPCM8XX_GRP(fanin0), \
+ NPCM8XX_GRP(fanin1), \
+ NPCM8XX_GRP(fanin2), \
+ NPCM8XX_GRP(fanin3), \
+ NPCM8XX_GRP(fanin4), \
+ NPCM8XX_GRP(fanin5), \
+ NPCM8XX_GRP(fanin6), \
+ NPCM8XX_GRP(fanin7), \
+ NPCM8XX_GRP(fanin8), \
+ NPCM8XX_GRP(fanin9), \
+ NPCM8XX_GRP(fanin10), \
+ NPCM8XX_GRP(fanin11), \
+ NPCM8XX_GRP(fanin12), \
+ NPCM8XX_GRP(fanin13), \
+ NPCM8XX_GRP(fanin14), \
+ NPCM8XX_GRP(fanin15), \
+ NPCM8XX_GRP(faninx), \
+ NPCM8XX_GRP(pwm0), \
+ NPCM8XX_GRP(pwm1), \
+ NPCM8XX_GRP(pwm2), \
+ NPCM8XX_GRP(pwm3), \
+ NPCM8XX_GRP(pwm4), \
+ NPCM8XX_GRP(pwm5), \
+ NPCM8XX_GRP(pwm6), \
+ NPCM8XX_GRP(pwm7), \
+ NPCM8XX_GRP(pwm8), \
+ NPCM8XX_GRP(pwm9), \
+ NPCM8XX_GRP(pwm10), \
+ NPCM8XX_GRP(pwm11), \
+ NPCM8XX_GRP(sg1mdio), \
+ NPCM8XX_GRP(rg2), \
+ NPCM8XX_GRP(rg2mdio), \
+ NPCM8XX_GRP(ddr), \
+ NPCM8XX_GRP(uart1), \
+ NPCM8XX_GRP(uart2), \
+ NPCM8XX_GRP(bmcuart0a), \
+ NPCM8XX_GRP(bmcuart0b), \
+ NPCM8XX_GRP(bmcuart1), \
+ NPCM8XX_GRP(iox1), \
+ NPCM8XX_GRP(iox2), \
+ NPCM8XX_GRP(ioxh), \
+ NPCM8XX_GRP(gspi), \
+ NPCM8XX_GRP(mmc), \
+ NPCM8XX_GRP(mmcwp), \
+ NPCM8XX_GRP(mmccd), \
+ NPCM8XX_GRP(mmcrst), \
+ NPCM8XX_GRP(mmc8), \
+ NPCM8XX_GRP(r1), \
+ NPCM8XX_GRP(r1err), \
+ NPCM8XX_GRP(r1md), \
+ NPCM8XX_GRP(r2), \
+ NPCM8XX_GRP(r2err), \
+ NPCM8XX_GRP(r2md), \
+ NPCM8XX_GRP(sd1), \
+ NPCM8XX_GRP(sd1pwr), \
+ NPCM8XX_GRP(wdog1), \
+ NPCM8XX_GRP(wdog2), \
+ NPCM8XX_GRP(scipme), \
+ NPCM8XX_GRP(smi), \
+ NPCM8XX_GRP(serirq), \
+ NPCM8XX_GRP(jtag2), \
+ NPCM8XX_GRP(spix), \
+ NPCM8XX_GRP(spixcs1), \
+ NPCM8XX_GRP(spi1), \
+ NPCM8XX_GRP(pspi), \
+ NPCM8XX_GRP(ddc), \
+ NPCM8XX_GRP(clkreq), \
+ NPCM8XX_GRP(clkout), \
+ NPCM8XX_GRP(spi3), \
+ NPCM8XX_GRP(spi3cs1), \
+ NPCM8XX_GRP(spi3quad), \
+ NPCM8XX_GRP(spi3cs2), \
+ NPCM8XX_GRP(spi3cs3), \
+ NPCM8XX_GRP(spi0cs1), \
+ NPCM8XX_GRP(lpc), \
+ NPCM8XX_GRP(lpcclk), \
+ NPCM8XX_GRP(espi), \
+ NPCM8XX_GRP(lkgpo0), \
+ NPCM8XX_GRP(lkgpo1), \
+ NPCM8XX_GRP(lkgpo2), \
+ NPCM8XX_GRP(nprd_smi), \
+ NPCM8XX_GRP(hgpio0), \
+ NPCM8XX_GRP(hgpio1), \
+ NPCM8XX_GRP(hgpio2), \
+ NPCM8XX_GRP(hgpio3), \
+ NPCM8XX_GRP(hgpio4), \
+ NPCM8XX_GRP(hgpio5), \
+ NPCM8XX_GRP(hgpio6), \
+ NPCM8XX_GRP(hgpio7), \
+ \
+
+enum {
+#define NPCM8XX_GRP(x) fn_ ## x
+ NPCM8XX_GRPS
+ NPCM8XX_GRP(none),
+ NPCM8XX_GRP(gpio),
+#undef NPCM8XX_GRP
+};
+
+static struct npcm8xx_pingroup npcm8xx_pingroups[] = {
+#define NPCM8XX_GRP(x) { .name = #x, .pins = x ## _pins, \
+ .npins = ARRAY_SIZE(x ## _pins) }
+ NPCM8XX_GRPS
+#undef NPCM8XX_GRP
+};
+
+#define NPCM8XX_SFUNC(a) NPCM8XX_FUNC(a, #a)
+#define NPCM8XX_FUNC(a, b...) static const char *a ## _grp[] = { b }
+#define NPCM8XX_MKFUNC(nm) { .name = #nm, .ngroups = ARRAY_SIZE(nm ## _grp), \
+ .groups = nm ## _grp }
+struct npcm8xx_func {
+ const char *name;
+ const unsigned int ngroups;
+ const char *const *groups;
+};
+
+NPCM8XX_SFUNC(gpi36);
+NPCM8XX_SFUNC(gpi35);
+NPCM8XX_SFUNC(tp_jtag3);
+NPCM8XX_SFUNC(tp_uart);
+NPCM8XX_SFUNC(tp_smb2);
+NPCM8XX_SFUNC(tp_smb1);
+NPCM8XX_SFUNC(tp_gpio7);
+NPCM8XX_SFUNC(tp_gpio6);
+NPCM8XX_SFUNC(tp_gpio5);
+NPCM8XX_SFUNC(tp_gpio4);
+NPCM8XX_SFUNC(tp_gpio3);
+NPCM8XX_SFUNC(tp_gpio2);
+NPCM8XX_SFUNC(tp_gpio1);
+NPCM8XX_SFUNC(tp_gpio0);
+NPCM8XX_SFUNC(tp_gpio2b);
+NPCM8XX_SFUNC(tp_gpio1b);
+NPCM8XX_SFUNC(tp_gpio0b);
+NPCM8XX_SFUNC(vgadig);
+NPCM8XX_SFUNC(nbu1crts);
+NPCM8XX_SFUNC(fm2);
+NPCM8XX_SFUNC(fm1);
+NPCM8XX_SFUNC(fm0);
+NPCM8XX_SFUNC(gpio1836);
+NPCM8XX_SFUNC(gpio1889);
+NPCM8XX_SFUNC(gpo187);
+NPCM8XX_SFUNC(cp1urxd);
+NPCM8XX_SFUNC(r3rxer);
+NPCM8XX_SFUNC(cp1gpio2c);
+NPCM8XX_SFUNC(cp1gpio3c);
+NPCM8XX_SFUNC(cp1gpio0b);
+NPCM8XX_SFUNC(cp1gpio1b);
+NPCM8XX_SFUNC(cp1gpio2b);
+NPCM8XX_SFUNC(cp1gpio3b);
+NPCM8XX_SFUNC(cp1gpio4b);
+NPCM8XX_SFUNC(cp1gpio5b);
+NPCM8XX_SFUNC(cp1gpio6b);
+NPCM8XX_SFUNC(cp1gpio7b);
+NPCM8XX_SFUNC(cp1gpio0);
+NPCM8XX_SFUNC(cp1gpio1);
+NPCM8XX_SFUNC(cp1gpio2);
+NPCM8XX_SFUNC(cp1gpio3);
+NPCM8XX_SFUNC(cp1gpio4);
+NPCM8XX_SFUNC(cp1gpio5);
+NPCM8XX_SFUNC(cp1gpio6);
+NPCM8XX_SFUNC(cp1gpio7);
+NPCM8XX_SFUNC(cp1utxd);
+NPCM8XX_SFUNC(spi1cs3);
+NPCM8XX_SFUNC(spi1cs2);
+NPCM8XX_SFUNC(spi1cs1);
+NPCM8XX_SFUNC(spi1cs0);
+NPCM8XX_SFUNC(spi1d23);
+NPCM8XX_SFUNC(j2j3);
+NPCM8XX_SFUNC(r3oen);
+NPCM8XX_SFUNC(r2oen);
+NPCM8XX_SFUNC(r1oen);
+NPCM8XX_SFUNC(bu4b);
+NPCM8XX_SFUNC(bu4);
+NPCM8XX_SFUNC(bu5b);
+NPCM8XX_SFUNC(bu5);
+NPCM8XX_SFUNC(bu6);
+NPCM8XX_SFUNC(rmii3);
+NPCM8XX_SFUNC(jm1);
+NPCM8XX_SFUNC(jm2);
+NPCM8XX_SFUNC(tpgpio5b);
+NPCM8XX_SFUNC(tpgpio4b);
+NPCM8XX_SFUNC(clkrun);
+NPCM8XX_SFUNC(i3c5);
+NPCM8XX_SFUNC(i3c4);
+NPCM8XX_SFUNC(i3c3);
+NPCM8XX_SFUNC(i3c2);
+NPCM8XX_SFUNC(i3c1);
+NPCM8XX_SFUNC(i3c0);
+NPCM8XX_SFUNC(hsi1a);
+NPCM8XX_SFUNC(hsi2a);
+NPCM8XX_SFUNC(hsi1b);
+NPCM8XX_SFUNC(hsi2b);
+NPCM8XX_SFUNC(hsi1c);
+NPCM8XX_SFUNC(hsi2c);
+NPCM8XX_SFUNC(smb0);
+NPCM8XX_SFUNC(smb0b);
+NPCM8XX_SFUNC(smb0c);
+NPCM8XX_SFUNC(smb0d);
+NPCM8XX_SFUNC(smb0den);
+NPCM8XX_SFUNC(smb1);
+NPCM8XX_SFUNC(smb1b);
+NPCM8XX_SFUNC(smb1c);
+NPCM8XX_SFUNC(smb1d);
+NPCM8XX_SFUNC(smb2);
+NPCM8XX_SFUNC(smb2b);
+NPCM8XX_SFUNC(smb2c);
+NPCM8XX_SFUNC(smb2d);
+NPCM8XX_SFUNC(smb3);
+NPCM8XX_SFUNC(smb3b);
+NPCM8XX_SFUNC(smb3c);
+NPCM8XX_SFUNC(smb3d);
+NPCM8XX_SFUNC(smb4);
+NPCM8XX_SFUNC(smb4b);
+NPCM8XX_SFUNC(smb4c);
+NPCM8XX_SFUNC(smb4d);
+NPCM8XX_SFUNC(smb4den);
+NPCM8XX_SFUNC(smb5);
+NPCM8XX_SFUNC(smb5b);
+NPCM8XX_SFUNC(smb5c);
+NPCM8XX_SFUNC(smb5d);
+NPCM8XX_SFUNC(ga20kbc);
+NPCM8XX_SFUNC(smb6);
+NPCM8XX_SFUNC(smb6b);
+NPCM8XX_SFUNC(smb6c);
+NPCM8XX_SFUNC(smb6d);
+NPCM8XX_SFUNC(smb7);
+NPCM8XX_SFUNC(smb7b);
+NPCM8XX_SFUNC(smb7c);
+NPCM8XX_SFUNC(smb7d);
+NPCM8XX_SFUNC(smb8);
+NPCM8XX_SFUNC(smb9);
+NPCM8XX_SFUNC(smb10);
+NPCM8XX_SFUNC(smb11);
+NPCM8XX_SFUNC(smb12);
+NPCM8XX_SFUNC(smb13);
+NPCM8XX_SFUNC(smb14);
+NPCM8XX_SFUNC(smb14b);
+NPCM8XX_SFUNC(smb15);
+NPCM8XX_SFUNC(smb16);
+NPCM8XX_SFUNC(smb16b);
+NPCM8XX_SFUNC(smb17);
+NPCM8XX_SFUNC(smb18);
+NPCM8XX_SFUNC(smb19);
+NPCM8XX_SFUNC(smb20);
+NPCM8XX_SFUNC(smb21);
+NPCM8XX_SFUNC(smb22);
+NPCM8XX_SFUNC(smb23);
+NPCM8XX_SFUNC(smb23b);
+NPCM8XX_SFUNC(fanin0);
+NPCM8XX_SFUNC(fanin1);
+NPCM8XX_SFUNC(fanin2);
+NPCM8XX_SFUNC(fanin3);
+NPCM8XX_SFUNC(fanin4);
+NPCM8XX_SFUNC(fanin5);
+NPCM8XX_SFUNC(fanin6);
+NPCM8XX_SFUNC(fanin7);
+NPCM8XX_SFUNC(fanin8);
+NPCM8XX_SFUNC(fanin9);
+NPCM8XX_SFUNC(fanin10);
+NPCM8XX_SFUNC(fanin11);
+NPCM8XX_SFUNC(fanin12);
+NPCM8XX_SFUNC(fanin13);
+NPCM8XX_SFUNC(fanin14);
+NPCM8XX_SFUNC(fanin15);
+NPCM8XX_SFUNC(faninx);
+NPCM8XX_SFUNC(pwm0);
+NPCM8XX_SFUNC(pwm1);
+NPCM8XX_SFUNC(pwm2);
+NPCM8XX_SFUNC(pwm3);
+NPCM8XX_SFUNC(pwm4);
+NPCM8XX_SFUNC(pwm5);
+NPCM8XX_SFUNC(pwm6);
+NPCM8XX_SFUNC(pwm7);
+NPCM8XX_SFUNC(pwm8);
+NPCM8XX_SFUNC(pwm9);
+NPCM8XX_SFUNC(pwm10);
+NPCM8XX_SFUNC(pwm11);
+NPCM8XX_SFUNC(sg1mdio);
+NPCM8XX_SFUNC(rg2);
+NPCM8XX_SFUNC(rg2mdio);
+NPCM8XX_SFUNC(ddr);
+NPCM8XX_SFUNC(uart1);
+NPCM8XX_SFUNC(uart2);
+NPCM8XX_SFUNC(bmcuart0a);
+NPCM8XX_SFUNC(bmcuart0b);
+NPCM8XX_SFUNC(bmcuart1);
+NPCM8XX_SFUNC(iox1);
+NPCM8XX_SFUNC(iox2);
+NPCM8XX_SFUNC(ioxh);
+NPCM8XX_SFUNC(gspi);
+NPCM8XX_SFUNC(mmc);
+NPCM8XX_SFUNC(mmcwp);
+NPCM8XX_SFUNC(mmccd);
+NPCM8XX_SFUNC(mmcrst);
+NPCM8XX_SFUNC(mmc8);
+NPCM8XX_SFUNC(r1);
+NPCM8XX_SFUNC(r1err);
+NPCM8XX_SFUNC(r1md);
+NPCM8XX_SFUNC(r2);
+NPCM8XX_SFUNC(r2err);
+NPCM8XX_SFUNC(r2md);
+NPCM8XX_SFUNC(sd1);
+NPCM8XX_SFUNC(sd1pwr);
+NPCM8XX_SFUNC(wdog1);
+NPCM8XX_SFUNC(wdog2);
+NPCM8XX_SFUNC(scipme);
+NPCM8XX_SFUNC(smi);
+NPCM8XX_SFUNC(serirq);
+NPCM8XX_SFUNC(jtag2);
+NPCM8XX_SFUNC(spix);
+NPCM8XX_SFUNC(spixcs1);
+NPCM8XX_SFUNC(spi1);
+NPCM8XX_SFUNC(pspi);
+NPCM8XX_SFUNC(ddc);
+NPCM8XX_SFUNC(clkreq);
+NPCM8XX_SFUNC(clkout);
+NPCM8XX_SFUNC(spi3);
+NPCM8XX_SFUNC(spi3cs1);
+NPCM8XX_SFUNC(spi3quad);
+NPCM8XX_SFUNC(spi3cs2);
+NPCM8XX_SFUNC(spi3cs3);
+NPCM8XX_SFUNC(spi0cs1);
+NPCM8XX_SFUNC(lpc);
+NPCM8XX_SFUNC(lpcclk);
+NPCM8XX_SFUNC(espi);
+NPCM8XX_SFUNC(lkgpo0);
+NPCM8XX_SFUNC(lkgpo1);
+NPCM8XX_SFUNC(lkgpo2);
+NPCM8XX_SFUNC(nprd_smi);
+NPCM8XX_SFUNC(hgpio0);
+NPCM8XX_SFUNC(hgpio1);
+NPCM8XX_SFUNC(hgpio2);
+NPCM8XX_SFUNC(hgpio3);
+NPCM8XX_SFUNC(hgpio4);
+NPCM8XX_SFUNC(hgpio5);
+NPCM8XX_SFUNC(hgpio6);
+NPCM8XX_SFUNC(hgpio7);
+
+/* Function names */
+static struct npcm8xx_func npcm8xx_funcs[] = {
+ NPCM8XX_MKFUNC(gpi36),
+ NPCM8XX_MKFUNC(gpi35),
+ NPCM8XX_MKFUNC(tp_jtag3),
+ NPCM8XX_MKFUNC(tp_uart),
+ NPCM8XX_MKFUNC(tp_smb2),
+ NPCM8XX_MKFUNC(tp_smb1),
+ NPCM8XX_MKFUNC(tp_gpio7),
+ NPCM8XX_MKFUNC(tp_gpio6),
+ NPCM8XX_MKFUNC(tp_gpio5),
+ NPCM8XX_MKFUNC(tp_gpio4),
+ NPCM8XX_MKFUNC(tp_gpio3),
+ NPCM8XX_MKFUNC(tp_gpio2),
+ NPCM8XX_MKFUNC(tp_gpio1),
+ NPCM8XX_MKFUNC(tp_gpio0),
+ NPCM8XX_MKFUNC(tp_gpio2b),
+ NPCM8XX_MKFUNC(tp_gpio1b),
+ NPCM8XX_MKFUNC(tp_gpio0b),
+ NPCM8XX_MKFUNC(vgadig),
+ NPCM8XX_MKFUNC(nbu1crts),
+ NPCM8XX_MKFUNC(fm2),
+ NPCM8XX_MKFUNC(fm1),
+ NPCM8XX_MKFUNC(fm0),
+ NPCM8XX_MKFUNC(gpio1836),
+ NPCM8XX_MKFUNC(gpio1889),
+ NPCM8XX_MKFUNC(gpo187),
+ NPCM8XX_MKFUNC(cp1urxd),
+ NPCM8XX_MKFUNC(r3rxer),
+ NPCM8XX_MKFUNC(cp1gpio2c),
+ NPCM8XX_MKFUNC(cp1gpio3c),
+ NPCM8XX_MKFUNC(cp1gpio0b),
+ NPCM8XX_MKFUNC(cp1gpio1b),
+ NPCM8XX_MKFUNC(cp1gpio2b),
+ NPCM8XX_MKFUNC(cp1gpio3b),
+ NPCM8XX_MKFUNC(cp1gpio4b),
+ NPCM8XX_MKFUNC(cp1gpio5b),
+ NPCM8XX_MKFUNC(cp1gpio6b),
+ NPCM8XX_MKFUNC(cp1gpio7b),
+ NPCM8XX_MKFUNC(cp1gpio0),
+ NPCM8XX_MKFUNC(cp1gpio1),
+ NPCM8XX_MKFUNC(cp1gpio2),
+ NPCM8XX_MKFUNC(cp1gpio3),
+ NPCM8XX_MKFUNC(cp1gpio4),
+ NPCM8XX_MKFUNC(cp1gpio5),
+ NPCM8XX_MKFUNC(cp1gpio6),
+ NPCM8XX_MKFUNC(cp1gpio7),
+ NPCM8XX_MKFUNC(cp1utxd),
+ NPCM8XX_MKFUNC(spi1cs3),
+ NPCM8XX_MKFUNC(spi1cs2),
+ NPCM8XX_MKFUNC(spi1cs1),
+ NPCM8XX_MKFUNC(spi1cs0),
+ NPCM8XX_MKFUNC(spi1d23),
+ NPCM8XX_MKFUNC(j2j3),
+ NPCM8XX_MKFUNC(r3oen),
+ NPCM8XX_MKFUNC(r2oen),
+ NPCM8XX_MKFUNC(r1oen),
+ NPCM8XX_MKFUNC(bu4b),
+ NPCM8XX_MKFUNC(bu4),
+ NPCM8XX_MKFUNC(bu5b),
+ NPCM8XX_MKFUNC(bu5),
+ NPCM8XX_MKFUNC(bu6),
+ NPCM8XX_MKFUNC(rmii3),
+ NPCM8XX_MKFUNC(jm1),
+ NPCM8XX_MKFUNC(jm2),
+ NPCM8XX_MKFUNC(tpgpio5b),
+ NPCM8XX_MKFUNC(tpgpio4b),
+ NPCM8XX_MKFUNC(clkrun),
+ NPCM8XX_MKFUNC(i3c5),
+ NPCM8XX_MKFUNC(i3c4),
+ NPCM8XX_MKFUNC(i3c3),
+ NPCM8XX_MKFUNC(i3c2),
+ NPCM8XX_MKFUNC(i3c1),
+ NPCM8XX_MKFUNC(i3c0),
+ NPCM8XX_MKFUNC(hsi1a),
+ NPCM8XX_MKFUNC(hsi2a),
+ NPCM8XX_MKFUNC(hsi1b),
+ NPCM8XX_MKFUNC(hsi2b),
+ NPCM8XX_MKFUNC(hsi1c),
+ NPCM8XX_MKFUNC(hsi2c),
+ NPCM8XX_MKFUNC(smb0),
+ NPCM8XX_MKFUNC(smb0b),
+ NPCM8XX_MKFUNC(smb0c),
+ NPCM8XX_MKFUNC(smb0d),
+ NPCM8XX_MKFUNC(smb0den),
+ NPCM8XX_MKFUNC(smb1),
+ NPCM8XX_MKFUNC(smb1b),
+ NPCM8XX_MKFUNC(smb1c),
+ NPCM8XX_MKFUNC(smb1d),
+ NPCM8XX_MKFUNC(smb2),
+ NPCM8XX_MKFUNC(smb2b),
+ NPCM8XX_MKFUNC(smb2c),
+ NPCM8XX_MKFUNC(smb2d),
+ NPCM8XX_MKFUNC(smb3),
+ NPCM8XX_MKFUNC(smb3b),
+ NPCM8XX_MKFUNC(smb3c),
+ NPCM8XX_MKFUNC(smb3d),
+ NPCM8XX_MKFUNC(smb4),
+ NPCM8XX_MKFUNC(smb4b),
+ NPCM8XX_MKFUNC(smb4c),
+ NPCM8XX_MKFUNC(smb4d),
+ NPCM8XX_MKFUNC(smb4den),
+ NPCM8XX_MKFUNC(smb5),
+ NPCM8XX_MKFUNC(smb5b),
+ NPCM8XX_MKFUNC(smb5c),
+ NPCM8XX_MKFUNC(smb5d),
+ NPCM8XX_MKFUNC(ga20kbc),
+ NPCM8XX_MKFUNC(smb6),
+ NPCM8XX_MKFUNC(smb6b),
+ NPCM8XX_MKFUNC(smb6c),
+ NPCM8XX_MKFUNC(smb6d),
+ NPCM8XX_MKFUNC(smb7),
+ NPCM8XX_MKFUNC(smb7b),
+ NPCM8XX_MKFUNC(smb7c),
+ NPCM8XX_MKFUNC(smb7d),
+ NPCM8XX_MKFUNC(smb8),
+ NPCM8XX_MKFUNC(smb9),
+ NPCM8XX_MKFUNC(smb10),
+ NPCM8XX_MKFUNC(smb11),
+ NPCM8XX_MKFUNC(smb12),
+ NPCM8XX_MKFUNC(smb13),
+ NPCM8XX_MKFUNC(smb14),
+ NPCM8XX_MKFUNC(smb14b),
+ NPCM8XX_MKFUNC(smb15),
+ NPCM8XX_MKFUNC(smb16),
+ NPCM8XX_MKFUNC(smb16b),
+ NPCM8XX_MKFUNC(smb17),
+ NPCM8XX_MKFUNC(smb18),
+ NPCM8XX_MKFUNC(smb19),
+ NPCM8XX_MKFUNC(smb20),
+ NPCM8XX_MKFUNC(smb21),
+ NPCM8XX_MKFUNC(smb22),
+ NPCM8XX_MKFUNC(smb23),
+ NPCM8XX_MKFUNC(smb23b),
+ NPCM8XX_MKFUNC(fanin0),
+ NPCM8XX_MKFUNC(fanin1),
+ NPCM8XX_MKFUNC(fanin2),
+ NPCM8XX_MKFUNC(fanin3),
+ NPCM8XX_MKFUNC(fanin4),
+ NPCM8XX_MKFUNC(fanin5),
+ NPCM8XX_MKFUNC(fanin6),
+ NPCM8XX_MKFUNC(fanin7),
+ NPCM8XX_MKFUNC(fanin8),
+ NPCM8XX_MKFUNC(fanin9),
+ NPCM8XX_MKFUNC(fanin10),
+ NPCM8XX_MKFUNC(fanin11),
+ NPCM8XX_MKFUNC(fanin12),
+ NPCM8XX_MKFUNC(fanin13),
+ NPCM8XX_MKFUNC(fanin14),
+ NPCM8XX_MKFUNC(fanin15),
+ NPCM8XX_MKFUNC(faninx),
+ NPCM8XX_MKFUNC(pwm0),
+ NPCM8XX_MKFUNC(pwm1),
+ NPCM8XX_MKFUNC(pwm2),
+ NPCM8XX_MKFUNC(pwm3),
+ NPCM8XX_MKFUNC(pwm4),
+ NPCM8XX_MKFUNC(pwm5),
+ NPCM8XX_MKFUNC(pwm6),
+ NPCM8XX_MKFUNC(pwm7),
+ NPCM8XX_MKFUNC(pwm8),
+ NPCM8XX_MKFUNC(pwm9),
+ NPCM8XX_MKFUNC(pwm10),
+ NPCM8XX_MKFUNC(pwm11),
+ NPCM8XX_MKFUNC(sg1mdio),
+ NPCM8XX_MKFUNC(rg2),
+ NPCM8XX_MKFUNC(rg2mdio),
+ NPCM8XX_MKFUNC(ddr),
+ NPCM8XX_MKFUNC(uart1),
+ NPCM8XX_MKFUNC(uart2),
+ NPCM8XX_MKFUNC(bmcuart0a),
+ NPCM8XX_MKFUNC(bmcuart0b),
+ NPCM8XX_MKFUNC(bmcuart1),
+ NPCM8XX_MKFUNC(iox1),
+ NPCM8XX_MKFUNC(iox2),
+ NPCM8XX_MKFUNC(ioxh),
+ NPCM8XX_MKFUNC(gspi),
+ NPCM8XX_MKFUNC(mmc),
+ NPCM8XX_MKFUNC(mmcwp),
+ NPCM8XX_MKFUNC(mmccd),
+ NPCM8XX_MKFUNC(mmcrst),
+ NPCM8XX_MKFUNC(mmc8),
+ NPCM8XX_MKFUNC(r1),
+ NPCM8XX_MKFUNC(r1err),
+ NPCM8XX_MKFUNC(r1md),
+ NPCM8XX_MKFUNC(r2),
+ NPCM8XX_MKFUNC(r2err),
+ NPCM8XX_MKFUNC(r2md),
+ NPCM8XX_MKFUNC(sd1),
+ NPCM8XX_MKFUNC(sd1pwr),
+ NPCM8XX_MKFUNC(wdog1),
+ NPCM8XX_MKFUNC(wdog2),
+ NPCM8XX_MKFUNC(scipme),
+ NPCM8XX_MKFUNC(smi),
+ NPCM8XX_MKFUNC(serirq),
+ NPCM8XX_MKFUNC(jtag2),
+ NPCM8XX_MKFUNC(spix),
+ NPCM8XX_MKFUNC(spixcs1),
+ NPCM8XX_MKFUNC(spi1),
+ NPCM8XX_MKFUNC(pspi),
+ NPCM8XX_MKFUNC(ddc),
+ NPCM8XX_MKFUNC(clkreq),
+ NPCM8XX_MKFUNC(clkout),
+ NPCM8XX_MKFUNC(spi3),
+ NPCM8XX_MKFUNC(spi3cs1),
+ NPCM8XX_MKFUNC(spi3quad),
+ NPCM8XX_MKFUNC(spi3cs2),
+ NPCM8XX_MKFUNC(spi3cs3),
+ NPCM8XX_MKFUNC(spi0cs1),
+ NPCM8XX_MKFUNC(lpc),
+ NPCM8XX_MKFUNC(lpcclk),
+ NPCM8XX_MKFUNC(espi),
+ NPCM8XX_MKFUNC(lkgpo0),
+ NPCM8XX_MKFUNC(lkgpo1),
+ NPCM8XX_MKFUNC(lkgpo2),
+ NPCM8XX_MKFUNC(nprd_smi),
+ NPCM8XX_MKFUNC(hgpio0),
+ NPCM8XX_MKFUNC(hgpio1),
+ NPCM8XX_MKFUNC(hgpio2),
+ NPCM8XX_MKFUNC(hgpio3),
+ NPCM8XX_MKFUNC(hgpio4),
+ NPCM8XX_MKFUNC(hgpio5),
+ NPCM8XX_MKFUNC(hgpio6),
+ NPCM8XX_MKFUNC(hgpio7),
+};
+
+#define NPCM8XX_PINCFG(a, b, c, d, e, f, g, h, i, j, k, l, m, n, o, p, q) \
+ [a] { .fn0 = fn_ ## b, .reg0 = NPCM8XX_GCR_ ## c, .bit0 = d, \
+ .fn1 = fn_ ## e, .reg1 = NPCM8XX_GCR_ ## f, .bit1 = g, \
+ .fn2 = fn_ ## h, .reg2 = NPCM8XX_GCR_ ## i, .bit2 = j, \
+ .fn3 = fn_ ## k, .reg3 = NPCM8XX_GCR_ ## l, .bit3 = m, \
+ .fn4 = fn_ ## n, .reg4 = NPCM8XX_GCR_ ## o, .bit4 = p, \
+ .flag = q }
+
+/* Drive strength controlled by NPCM8XX_GP_N_ODSC */
+#define DRIVE_STRENGTH_LO_SHIFT 8
+#define DRIVE_STRENGTH_HI_SHIFT 12
+#define DRIVE_STRENGTH_MASK GENMASK(15, 8)
+
+#define DSTR(lo, hi) (((lo) << DRIVE_STRENGTH_LO_SHIFT) | \
+ ((hi) << DRIVE_STRENGTH_HI_SHIFT))
+#define DSLO(x) (((x) >> DRIVE_STRENGTH_LO_SHIFT) & GENMASK(3, 0))
+#define DSHI(x) (((x) >> DRIVE_STRENGTH_HI_SHIFT) & GENMASK(3, 0))
+
+#define GPI BIT(0) /* Not GPO */
+#define GPO BIT(1) /* Not GPI */
+#define SLEW BIT(2) /* Has Slew Control, NPCM8XX_GP_N_OSRC */
+#define SLEWLPC BIT(3) /* Has Slew Control, SRCNT.3 */
+
+struct npcm8xx_pincfg {
+ int flag;
+ int fn0, reg0, bit0;
+ int fn1, reg1, bit1;
+ int fn2, reg2, bit2;
+ int fn3, reg3, bit3;
+ int fn4, reg4, bit4;
+};
+
+static const struct npcm8xx_pincfg pincfg[] = {
+ /* PIN FUNCTION 1 FUNCTION 2 FUNCTION 3 FUNCTION 4 FUNCTION 5 FLAGS */
+ NPCM8XX_PINCFG(0, iox1, MFSEL1, 30, smb6c, I2CSEGSEL, 25, smb18, MFSEL5, 26, none, NONE, 0, none, NONE, 0, SLEW),
+ NPCM8XX_PINCFG(1, iox1, MFSEL1, 30, smb6c, I2CSEGSEL, 25, smb18, MFSEL5, 26, none, NONE, 0, none, NONE, 0, SLEW),
+ NPCM8XX_PINCFG(2, iox1, MFSEL1, 30, smb6b, I2CSEGSEL, 24, smb17, MFSEL5, 25, none, NONE, 0, none, NONE, 0, SLEW),
+ NPCM8XX_PINCFG(3, iox1, MFSEL1, 30, smb6b, I2CSEGSEL, 24, smb17, MFSEL5, 25, none, NONE, 0, none, NONE, 0, SLEW),
+ NPCM8XX_PINCFG(4, iox2, MFSEL3, 14, smb1d, I2CSEGSEL, 7, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW),
+ NPCM8XX_PINCFG(5, iox2, MFSEL3, 14, smb1d, I2CSEGSEL, 7, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW),
+ NPCM8XX_PINCFG(6, iox2, MFSEL3, 14, smb2d, I2CSEGSEL, 10, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW),
+ NPCM8XX_PINCFG(7, iox2, MFSEL3, 14, smb2d, I2CSEGSEL, 10, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW),
+ NPCM8XX_PINCFG(8, lkgpo1, FLOCKR1, 4, tp_gpio0b, MFSEL7, 8, none, NONE, 0, none, NONE, 0, none, NONE, 0, DSTR(8, 12)),
+ NPCM8XX_PINCFG(9, lkgpo2, FLOCKR1, 8, tp_gpio1b, MFSEL7, 9, none, NONE, 0, none, NONE, 0, none, NONE, 0, DSTR(8, 12)),
+ NPCM8XX_PINCFG(10, ioxh, MFSEL3, 18, smb6d, I2CSEGSEL, 26, smb16, MFSEL5, 24, none, NONE, 0, none, NONE, 0, SLEW),
+ NPCM8XX_PINCFG(11, ioxh, MFSEL3, 18, smb6d, I2CSEGSEL, 26, smb16, MFSEL5, 24, none, NONE, 0, none, NONE, 0, SLEW),
+ NPCM8XX_PINCFG(12, gspi, MFSEL1, 24, smb5b, I2CSEGSEL, 19, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW),
+ NPCM8XX_PINCFG(13, gspi, MFSEL1, 24, smb5b, I2CSEGSEL, 19, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW),
+ NPCM8XX_PINCFG(14, gspi, MFSEL1, 24, smb5c, I2CSEGSEL, 20, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW),
+ NPCM8XX_PINCFG(15, gspi, MFSEL1, 24, smb5c, I2CSEGSEL, 20, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW),
+ NPCM8XX_PINCFG(16, lkgpo0, FLOCKR1, 0, smb7b, I2CSEGSEL, 27, tp_gpio2b, MFSEL7, 10, none, NONE, 0, none, NONE, 0, SLEW),
+ NPCM8XX_PINCFG(17, pspi, MFSEL3, 13, cp1gpio5, MFSEL6, 7, smb4den, I2CSEGSEL, 23, none, NONE, 0, none, NONE, 0, SLEW),
+ NPCM8XX_PINCFG(18, pspi, MFSEL3, 13, smb4b, I2CSEGSEL, 14, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW),
+ NPCM8XX_PINCFG(19, pspi, MFSEL3, 13, smb4b, I2CSEGSEL, 14, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW),
+ NPCM8XX_PINCFG(20, hgpio0, MFSEL2, 24, smb15, MFSEL3, 8, smb4c, I2CSEGSEL, 15, none, NONE, 0, none, NONE, 0, SLEW),
+ NPCM8XX_PINCFG(21, hgpio1, MFSEL2, 25, smb15, MFSEL3, 8, smb4c, I2CSEGSEL, 15, none, NONE, 0, none, NONE, 0, SLEW),
+ NPCM8XX_PINCFG(22, hgpio2, MFSEL2, 26, smb14, MFSEL3, 7, smb4d, I2CSEGSEL, 16, none, NONE, 0, none, NONE, 0, SLEW),
+ NPCM8XX_PINCFG(23, hgpio3, MFSEL2, 27, smb14, MFSEL3, 7, smb4d, I2CSEGSEL, 16, none, NONE, 0, none, NONE, 0, SLEW),
+ NPCM8XX_PINCFG(24, hgpio4, MFSEL2, 28, ioxh, MFSEL3, 18, smb7c, I2CSEGSEL, 28, tp_smb2, MFSEL7, 28, none, NONE, 0, SLEW),
+ NPCM8XX_PINCFG(25, hgpio5, MFSEL2, 29, ioxh, MFSEL3, 18, smb7c, I2CSEGSEL, 28, tp_smb2, MFSEL7, 28, none, NONE, 0, SLEW),
+ NPCM8XX_PINCFG(26, smb5, MFSEL1, 2, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, 0),
+ NPCM8XX_PINCFG(27, smb5, MFSEL1, 2, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, 0),
+ NPCM8XX_PINCFG(28, smb4, MFSEL1, 1, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, 0),
+ NPCM8XX_PINCFG(29, smb4, MFSEL1, 1, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, 0),
+ NPCM8XX_PINCFG(30, smb3, MFSEL1, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, 0),
+ NPCM8XX_PINCFG(31, smb3, MFSEL1, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, 0),
+ NPCM8XX_PINCFG(32, spi0cs1, MFSEL1, 3, smb14b, MFSEL7, 26, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW),
+ NPCM8XX_PINCFG(33, i3c4, MFSEL6, 10, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW),
+ NPCM8XX_PINCFG(34, i3c4, MFSEL6, 10, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW),
+ NPCM8XX_PINCFG(37, smb3c, I2CSEGSEL, 12, smb23, MFSEL5, 31, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW),
+ NPCM8XX_PINCFG(38, smb3c, I2CSEGSEL, 12, smb23, MFSEL5, 31, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW),
+ NPCM8XX_PINCFG(39, smb3b, I2CSEGSEL, 11, smb22, MFSEL5, 30, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW),
+ NPCM8XX_PINCFG(40, smb3b, I2CSEGSEL, 11, smb22, MFSEL5, 30, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW),
+ NPCM8XX_PINCFG(41, bmcuart0a, MFSEL1, 9, cp1urxd, MFSEL6, 31, none, NONE, 0, none, NONE, 0, none, NONE, 0, 0),
+ NPCM8XX_PINCFG(42, bmcuart0a, MFSEL1, 9, cp1utxd, MFSEL6, 1, none, NONE, 0, none, NONE, 0, none, NONE, 0, DSTR(2, 4) | GPO),
+ NPCM8XX_PINCFG(43, uart1, MFSEL1, 10, bmcuart1, MFSEL3, 24, none, NONE, 0, none, NONE, 0, none, NONE, 0, GPO),
+ NPCM8XX_PINCFG(44, hsi1b, MFSEL1, 28, nbu1crts, MFSEL6, 15, jtag2, MFSEL4, 0, tp_jtag3, MFSEL7, 13, j2j3, MFSEL5, 2, GPO),
+ NPCM8XX_PINCFG(45, hsi1c, MFSEL1, 4, jtag2, MFSEL4, 0, j2j3, MFSEL5, 2, tp_jtag3, MFSEL7, 13, none, NONE, 0, GPO),
+ NPCM8XX_PINCFG(46, hsi1c, MFSEL1, 4, jtag2, MFSEL4, 0, j2j3, MFSEL5, 2, tp_jtag3, MFSEL7, 13, none, NONE, 0, GPO),
+ NPCM8XX_PINCFG(47, hsi1c, MFSEL1, 4, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, DSTR(2, 8)),
+ NPCM8XX_PINCFG(48, hsi2a, MFSEL1, 11, bmcuart0b, MFSEL4, 1, none, NONE, 0, none, NONE, 0, none, NONE, 0, GPO),
+ NPCM8XX_PINCFG(49, hsi2a, MFSEL1, 11, bmcuart0b, MFSEL4, 1, none, NONE, 0, none, NONE, 0, none, NONE, 0, GPO),
+ NPCM8XX_PINCFG(50, hsi2b, MFSEL1, 29, bu6, MFSEL5, 6, tp_uart, MFSEL7, 12, none, NONE, 0, none, NONE, 0, GPO),
+ NPCM8XX_PINCFG(51, hsi2b, MFSEL1, 29, bu6, MFSEL5, 6, tp_uart, MFSEL7, 12, none, NONE, 0, none, NONE, 0, GPO),
+ NPCM8XX_PINCFG(52, hsi2c, MFSEL1, 5, bu5, MFSEL5, 7, none, NONE, 0, none, NONE, 0, none, NONE, 0, GPO),
+ NPCM8XX_PINCFG(53, hsi2c, MFSEL1, 5, bu5, MFSEL5, 7, none, NONE, 0, none, NONE, 0, none, NONE, 0, GPO),
+ NPCM8XX_PINCFG(54, hsi2c, MFSEL1, 5, bu4, MFSEL5, 8, none, NONE, 0, none, NONE, 0, none, NONE, 0, GPO),
+ NPCM8XX_PINCFG(55, hsi2c, MFSEL1, 5, bu4, MFSEL5, 8, none, NONE, 0, none, NONE, 0, none, NONE, 0, GPO),
+ NPCM8XX_PINCFG(56, r1err, MFSEL1, 12, r1oen, MFSEL5, 9, none, NONE, 0, none, NONE, 0, none, NONE, 0, GPO),
+ NPCM8XX_PINCFG(57, r1md, MFSEL1, 13, tpgpio4b, MFSEL5, 20, none, NONE, 0, none, NONE, 0, none, NONE, 0, DSTR(2, 4)),
+ NPCM8XX_PINCFG(58, r1md, MFSEL1, 13, tpgpio5b, MFSEL5, 22, none, NONE, 0, none, NONE, 0, none, NONE, 0, DSTR(2, 4)),
+ NPCM8XX_PINCFG(59, hgpio6, MFSEL2, 30, smb3d, I2CSEGSEL, 13, smb19, MFSEL5, 27, none, NONE, 0, none, NONE, 0, 0),
+ NPCM8XX_PINCFG(60, hgpio7, MFSEL2, 31, smb3d, I2CSEGSEL, 13, smb19, MFSEL5, 27, none, NONE, 0, none, NONE, 0, 0),
+ NPCM8XX_PINCFG(61, hsi1c, MFSEL1, 4, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, GPO),
+ NPCM8XX_PINCFG(62, hsi1b, MFSEL1, 28, jtag2, MFSEL4, 0, j2j3, MFSEL5, 2, nbu1crts, MFSEL6, 15, tp_jtag3, MFSEL7, 13, GPO),
+ NPCM8XX_PINCFG(63, hsi1a, MFSEL1, 10, bmcuart1, MFSEL3, 24, none, NONE, 0, none, NONE, 0, none, NONE, 0, GPO),
+ NPCM8XX_PINCFG(64, fanin0, MFSEL2, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, GPO),
+ NPCM8XX_PINCFG(65, fanin1, MFSEL2, 1, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, GPO),
+ NPCM8XX_PINCFG(66, fanin2, MFSEL2, 2, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, GPO),
+ NPCM8XX_PINCFG(67, fanin3, MFSEL2, 3, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, GPO),
+ NPCM8XX_PINCFG(68, fanin4, MFSEL2, 4, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, GPO),
+ NPCM8XX_PINCFG(69, fanin5, MFSEL2, 5, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, GPO),
+ NPCM8XX_PINCFG(70, fanin6, MFSEL2, 6, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, GPO),
+ NPCM8XX_PINCFG(71, fanin7, MFSEL2, 7, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, GPO),
+ NPCM8XX_PINCFG(72, fanin8, MFSEL2, 8, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, GPO),
+ NPCM8XX_PINCFG(73, fanin9, MFSEL2, 9, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, GPO),
+ NPCM8XX_PINCFG(74, fanin10, MFSEL2, 10, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, GPO),
+ NPCM8XX_PINCFG(75, fanin11, MFSEL2, 11, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, GPO),
+ NPCM8XX_PINCFG(76, fanin12, MFSEL2, 12, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, GPO),
+ NPCM8XX_PINCFG(77, fanin13, MFSEL2, 13, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, GPO),
+ NPCM8XX_PINCFG(78, fanin14, MFSEL2, 14, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, GPO),
+ NPCM8XX_PINCFG(79, fanin15, MFSEL2, 15, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, GPO),
+ NPCM8XX_PINCFG(80, pwm0, MFSEL2, 16, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, DSTR(4, 8)),
+ NPCM8XX_PINCFG(81, pwm1, MFSEL2, 17, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, DSTR(4, 8)),
+ NPCM8XX_PINCFG(82, pwm2, MFSEL2, 18, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, DSTR(4, 8)),
+ NPCM8XX_PINCFG(83, pwm3, MFSEL2, 19, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, DSTR(4, 8)),
+ NPCM8XX_PINCFG(84, r2, MFSEL1, 14, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW),
+ NPCM8XX_PINCFG(85, r2, MFSEL1, 14, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW),
+ NPCM8XX_PINCFG(86, r2, MFSEL1, 14, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW),
+ NPCM8XX_PINCFG(87, r2, MFSEL1, 14, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, GPO),
+ NPCM8XX_PINCFG(88, r2, MFSEL1, 14, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, GPO),
+ NPCM8XX_PINCFG(89, r2, MFSEL1, 14, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, GPO),
+ NPCM8XX_PINCFG(90, r2err, MFSEL1, 15, r2oen, MFSEL5, 10, none, NONE, 0, none, NONE, 0, none, NONE, 0, GPO),
+ NPCM8XX_PINCFG(91, r2md, MFSEL1, 16, cp1gpio6, MFSEL6, 8, tp_gpio0, MFSEL7, 0, none, NONE, 0, none, NONE, 0, DSTR(2, 4)),
+ NPCM8XX_PINCFG(92, r2md, MFSEL1, 16, cp1gpio7, MFSEL6, 9, tp_gpio1, MFSEL7, 1, none, NONE, 0, none, NONE, 0, DSTR(2, 4)),
+ NPCM8XX_PINCFG(93, ga20kbc, MFSEL1, 17, smb5d, I2CSEGSEL, 21, none, NONE, 0, none, NONE, 0, none, NONE, 0, 0),
+ NPCM8XX_PINCFG(94, ga20kbc, MFSEL1, 17, smb5d, I2CSEGSEL, 21, none, NONE, 0, none, NONE, 0, none, NONE, 0, 0),
+ NPCM8XX_PINCFG(95, lpc, MFSEL1, 26, espi, MFSEL4, 8, none, NONE, 0, none, NONE, 0, none, NONE, 0, 0),
+ NPCM8XX_PINCFG(96, cp1gpio7b, MFSEL6, 24, tp_gpio7, MFSEL7, 7, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW),
+ NPCM8XX_PINCFG(97, cp1gpio6b, MFSEL6, 25, tp_gpio6, MFSEL7, 6, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW),
+ NPCM8XX_PINCFG(98, bu4b, MFSEL5, 13, cp1gpio5b, MFSEL6, 26, tp_gpio5, MFSEL7, 5, none, NONE, 0, none, NONE, 0, SLEW),
+ NPCM8XX_PINCFG(99, bu4b, MFSEL5, 13, cp1gpio4b, MFSEL6, 27, tp_gpio4, MFSEL7, 4, none, NONE, 0, none, NONE, 0, SLEW),
+ NPCM8XX_PINCFG(100, bu5b, MFSEL5, 12, cp1gpio3c, MFSEL6, 28, tp_gpio3, MFSEL7, 3, none, NONE, 0, none, NONE, 0, SLEW),
+ NPCM8XX_PINCFG(101, bu5b, MFSEL5, 12, cp1gpio2c, MFSEL6, 29, tp_gpio2, MFSEL7, 2, none, NONE, 0, none, NONE, 0, SLEW),
+ NPCM8XX_PINCFG(102, vgadig, MFSEL7, 29, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, DSTR(4, 8)),
+ NPCM8XX_PINCFG(103, vgadig, MFSEL7, 29, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, DSTR(4, 8)),
+ NPCM8XX_PINCFG(104, vgadig, MFSEL7, 29, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, 0),
+ NPCM8XX_PINCFG(105, vgadig, MFSEL7, 29, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, 0),
+ NPCM8XX_PINCFG(106, i3c5, MFSEL3, 22, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW),
+ NPCM8XX_PINCFG(107, i3c5, MFSEL3, 22, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW),
+ NPCM8XX_PINCFG(108, sg1mdio, MFSEL4, 21, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW),
+ NPCM8XX_PINCFG(109, sg1mdio, MFSEL4, 21, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW),
+ NPCM8XX_PINCFG(110, rg2, MFSEL4, 24, ddr, MFSEL3, 26, rmii3, MFSEL5, 11, none, NONE, 0, none, NONE, 0, 0),
+ NPCM8XX_PINCFG(111, rg2, MFSEL4, 24, ddr, MFSEL3, 26, rmii3, MFSEL5, 11, none, NONE, 0, none, NONE, 0, 0),
+ NPCM8XX_PINCFG(112, rg2, MFSEL4, 24, ddr, MFSEL3, 26, none, NONE, 0, none, NONE, 0, none, NONE, 0, 0),
+ NPCM8XX_PINCFG(113, rg2, MFSEL4, 24, ddr, MFSEL3, 26, none, NONE, 0, none, NONE, 0, none, NONE, 0, 0),
+ NPCM8XX_PINCFG(114, smb0, MFSEL1, 6, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, 0),
+ NPCM8XX_PINCFG(115, smb0, MFSEL1, 6, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, 0),
+ NPCM8XX_PINCFG(116, smb1, MFSEL1, 7, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, 0),
+ NPCM8XX_PINCFG(117, smb1, MFSEL1, 7, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, 0),
+ NPCM8XX_PINCFG(118, smb2, MFSEL1, 8, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, 0),
+ NPCM8XX_PINCFG(119, smb2, MFSEL1, 8, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, 0),
+ NPCM8XX_PINCFG(120, smb2c, I2CSEGSEL, 9, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW),
+ NPCM8XX_PINCFG(121, smb2c, I2CSEGSEL, 9, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW),
+ NPCM8XX_PINCFG(122, smb2b, I2CSEGSEL, 8, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW),
+ NPCM8XX_PINCFG(123, smb2b, I2CSEGSEL, 8, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW),
+ NPCM8XX_PINCFG(124, smb1c, I2CSEGSEL, 6, cp1gpio3b, MFSEL6, 23, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW),
+ NPCM8XX_PINCFG(125, smb1c, I2CSEGSEL, 6, cp1gpio2b, MFSEL6, 22, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW),
+ NPCM8XX_PINCFG(126, smb1b, I2CSEGSEL, 5, cp1gpio1b, MFSEL6, 21, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW),
+ NPCM8XX_PINCFG(127, smb1b, I2CSEGSEL, 5, cp1gpio0b, MFSEL6, 20, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW),
+ NPCM8XX_PINCFG(128, smb8, MFSEL4, 11, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, 0),
+ NPCM8XX_PINCFG(129, smb8, MFSEL4, 11, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, 0),
+ NPCM8XX_PINCFG(130, smb9, MFSEL4, 12, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, 0),
+ NPCM8XX_PINCFG(131, smb9, MFSEL4, 12, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, 0),
+ NPCM8XX_PINCFG(132, smb10, MFSEL4, 13, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, 0),
+ NPCM8XX_PINCFG(133, smb10, MFSEL4, 13, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, 0),
+ NPCM8XX_PINCFG(134, smb11, MFSEL4, 14, smb23b, MFSEL6, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, 0),
+ NPCM8XX_PINCFG(135, smb11, MFSEL4, 14, smb23b, MFSEL6, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, 0),
+ NPCM8XX_PINCFG(136, jm1, MFSEL5, 15, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW),
+ NPCM8XX_PINCFG(137, jm1, MFSEL5, 15, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW),
+ NPCM8XX_PINCFG(138, jm1, MFSEL5, 15, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW),
+ NPCM8XX_PINCFG(139, jm1, MFSEL5, 15, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW),
+ NPCM8XX_PINCFG(140, jm1, MFSEL5, 15, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW),
+ NPCM8XX_PINCFG(141, smb7b, I2CSEGSEL, 27, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, 0),
+ NPCM8XX_PINCFG(142, smb7d, I2CSEGSEL, 29, tp_smb1, MFSEL7, 11, none, NONE, 0, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW),
+ NPCM8XX_PINCFG(143, smb7d, I2CSEGSEL, 29, tp_smb1, MFSEL7, 11, none, NONE, 0, none, NONE, 0, none, NONE, 0, 0),
+ NPCM8XX_PINCFG(144, pwm4, MFSEL2, 20, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, DSTR(4, 8)),
+ NPCM8XX_PINCFG(145, pwm5, MFSEL2, 21, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, DSTR(4, 8)),
+ NPCM8XX_PINCFG(146, pwm6, MFSEL2, 22, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, DSTR(4, 8)),
+ NPCM8XX_PINCFG(147, pwm7, MFSEL2, 23, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, DSTR(4, 8)),
+ NPCM8XX_PINCFG(148, mmc8, MFSEL3, 11, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW),
+ NPCM8XX_PINCFG(149, mmc8, MFSEL3, 11, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW),
+ NPCM8XX_PINCFG(150, mmc8, MFSEL3, 11, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW),
+ NPCM8XX_PINCFG(151, mmc8, MFSEL3, 11, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW),
+ NPCM8XX_PINCFG(152, mmc, MFSEL3, 10, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW),
+ NPCM8XX_PINCFG(153, mmcwp, FLOCKR1, 24, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, 0),
+ NPCM8XX_PINCFG(154, mmc, MFSEL3, 10, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW),
+ NPCM8XX_PINCFG(155, mmccd, MFSEL3, 25, mmcrst, MFSEL4, 6, none, NONE, 0, none, NONE, 0, none, NONE, 0, 0),
+ NPCM8XX_PINCFG(156, mmc, MFSEL3, 10, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW),
+ NPCM8XX_PINCFG(157, mmc, MFSEL3, 10, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW),
+ NPCM8XX_PINCFG(158, mmc, MFSEL3, 10, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW),
+ NPCM8XX_PINCFG(159, mmc, MFSEL3, 10, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW),
+ NPCM8XX_PINCFG(160, clkout, MFSEL1, 21, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW),
+ NPCM8XX_PINCFG(161, lpc, MFSEL1, 26, espi, MFSEL4, 8, none, NONE, 0, none, NONE, 0, none, NONE, 0, 0),
+ NPCM8XX_PINCFG(162, serirq, MFSEL1, 31, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, DSTR(8, 12)),
+ NPCM8XX_PINCFG(163, lpc, MFSEL1, 26, espi, MFSEL4, 8, none, NONE, 0, none, NONE, 0, none, NONE, 0, 0),
+ NPCM8XX_PINCFG(164, lpc, MFSEL1, 26, espi, MFSEL4, 8, none, NONE, 0, none, NONE, 0, none, NONE, 0, 0),
+ NPCM8XX_PINCFG(165, lpc, MFSEL1, 26, espi, MFSEL4, 8, none, NONE, 0, none, NONE, 0, none, NONE, 0, 0),
+ NPCM8XX_PINCFG(166, lpc, MFSEL1, 26, espi, MFSEL4, 8, none, NONE, 0, none, NONE, 0, none, NONE, 0, 0),
+ NPCM8XX_PINCFG(167, lpc, MFSEL1, 26, espi, MFSEL4, 8, none, NONE, 0, none, NONE, 0, none, NONE, 0, 0),
+ NPCM8XX_PINCFG(168, lpcclk, MFSEL1, 31, espi, MFSEL4, 8, none, NONE, 0, none, NONE, 0, none, NONE, 0, 0),
+ NPCM8XX_PINCFG(169, scipme, MFSEL3, 0, smb21, MFSEL5, 29, none, NONE, 0, none, NONE, 0, none, NONE, 0, 0),
+ NPCM8XX_PINCFG(170, smi, MFSEL1, 22, smb21, MFSEL5, 29, none, NONE, 0, none, NONE, 0, none, NONE, 0, 0),
+ NPCM8XX_PINCFG(171, smb6, MFSEL3, 1, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, 0),
+ NPCM8XX_PINCFG(172, smb6, MFSEL3, 1, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, 0),
+ NPCM8XX_PINCFG(173, smb7, MFSEL3, 2, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, 0),
+ NPCM8XX_PINCFG(174, smb7, MFSEL3, 2, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, 0),
+ NPCM8XX_PINCFG(175, spi1, MFSEL3, 4, faninx, MFSEL3, 3, fm1, MFSEL6, 17, none, NONE, 0, none, NONE, 0, DSTR(8, 12)),
+ NPCM8XX_PINCFG(176, spi1, MFSEL3, 4, faninx, MFSEL3, 3, fm1, MFSEL6, 17, none, NONE, 0, none, NONE, 0, DSTR(8, 12)),
+ NPCM8XX_PINCFG(177, spi1, MFSEL3, 4, faninx, MFSEL3, 3, fm1, MFSEL6, 17, none, NONE, 0, none, NONE, 0, DSTR(8, 12)),
+ NPCM8XX_PINCFG(178, r1, MFSEL3, 9, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW),
+ NPCM8XX_PINCFG(179, r1, MFSEL3, 9, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW),
+ NPCM8XX_PINCFG(180, r1, MFSEL3, 9, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW),
+ NPCM8XX_PINCFG(181, r1, MFSEL3, 9, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, GPO),
+ NPCM8XX_PINCFG(182, r1, MFSEL3, 9, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, GPO),
+ NPCM8XX_PINCFG(183, gpio1836, MFSEL6, 19, spi3, MFSEL4, 16, none, NONE, 0, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW),
+ NPCM8XX_PINCFG(184, gpio1836, MFSEL6, 19, spi3, MFSEL4, 16, none, NONE, 0, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW),
+ NPCM8XX_PINCFG(185, gpio1836, MFSEL6, 19, spi3, MFSEL4, 16, none, NONE, 0, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW),
+ NPCM8XX_PINCFG(186, gpio1836, MFSEL6, 19, spi3, MFSEL4, 16, none, NONE, 0, none, NONE, 0, none, NONE, 0, DSTR(8, 12)),
+ NPCM8XX_PINCFG(187, gpo187, MFSEL7, 24, smb14b, MFSEL7, 26, spi3cs1, MFSEL4, 17, none, NONE, 0, none, NONE, 0, 0),
+ NPCM8XX_PINCFG(188, gpio1889, MFSEL7, 25, spi3cs2, MFSEL4, 18, spi3quad, MFSEL4, 20, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW),
+ NPCM8XX_PINCFG(189, gpio1889, MFSEL7, 25, spi3cs3, MFSEL4, 19, spi3quad, MFSEL4, 20, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW),
+ NPCM8XX_PINCFG(190, nprd_smi, FLOCKR1, 20, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, DSTR(2, 4)),
+ NPCM8XX_PINCFG(191, spi1d23, MFSEL5, 3, spi1cs2, MFSEL5, 4, fm1, MFSEL6, 17, smb15, MFSEL7, 27, none, NONE, 0, DSTR(0, 2)), /* XX */
+ NPCM8XX_PINCFG(192, spi1d23, MFSEL5, 3, spi1cs3, MFSEL5, 5, fm1, MFSEL6, 17, smb15, MFSEL7, 27, none, NONE, 0, DSTR(0, 2)), /* XX */
+ NPCM8XX_PINCFG(193, r1, MFSEL3, 9, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, 0),
+ NPCM8XX_PINCFG(194, smb0b, I2CSEGSEL, 0, fm0, MFSEL6, 16, none, NONE, 0, none, NONE, 0, none, NONE, 0, DSTR(0, 1)),
+ NPCM8XX_PINCFG(195, smb0b, I2CSEGSEL, 0, fm0, MFSEL6, 16, none, NONE, 0, none, NONE, 0, none, NONE, 0, DSTR(0, 1)),
+ NPCM8XX_PINCFG(196, smb0c, I2CSEGSEL, 1, fm0, MFSEL6, 16, none, NONE, 0, none, NONE, 0, none, NONE, 0, DSTR(0, 1)),
+ NPCM8XX_PINCFG(197, smb0den, I2CSEGSEL, 22, fm0, MFSEL6, 16, none, NONE, 0, none, NONE, 0, none, NONE, 0, DSTR(0, 1)),
+ NPCM8XX_PINCFG(198, smb0d, I2CSEGSEL, 2, fm0, MFSEL6, 16, none, NONE, 0, none, NONE, 0, none, NONE, 0, DSTR(0, 1)),
+ NPCM8XX_PINCFG(199, smb0d, I2CSEGSEL, 2, fm0, MFSEL6, 16, none, NONE, 0, none, NONE, 0, none, NONE, 0, DSTR(0, 1)),
+ NPCM8XX_PINCFG(200, r2, MFSEL1, 14, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, GPO),
+ NPCM8XX_PINCFG(201, r1, MFSEL3, 9, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, GPO),
+ NPCM8XX_PINCFG(202, smb0c, I2CSEGSEL, 1, fm0, MFSEL6, 16, none, NONE, 0, none, NONE, 0, none, NONE, 0, DSTR(0, 1)),
+ NPCM8XX_PINCFG(203, faninx, MFSEL3, 3, spi1cs0, MFSEL3, 4, fm1, MFSEL6, 17, none, NONE, 0, none, NONE, 0, DSTR(8, 12)),
+ NPCM8XX_PINCFG(208, rg2, MFSEL4, 24, ddr, MFSEL3, 26, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW), /* DSCNT */
+ NPCM8XX_PINCFG(209, rg2, MFSEL4, 24, ddr, MFSEL3, 26, rmii3, MFSEL5, 11, none, NONE, 0, none, NONE, 0, SLEW), /* DSCNT */
+ NPCM8XX_PINCFG(210, rg2, MFSEL4, 24, ddr, MFSEL3, 26, rmii3, MFSEL5, 11, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW),
+ NPCM8XX_PINCFG(211, rg2, MFSEL4, 24, ddr, MFSEL3, 26, rmii3, MFSEL5, 11, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW),
+ NPCM8XX_PINCFG(212, rg2, MFSEL4, 24, ddr, MFSEL3, 26, r3rxer, MFSEL6, 30, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW),
+ NPCM8XX_PINCFG(213, rg2, MFSEL4, 24, ddr, MFSEL3, 26, r3oen, MFSEL5, 14, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW),
+ NPCM8XX_PINCFG(214, rg2, MFSEL4, 24, ddr, MFSEL3, 26, rmii3, MFSEL5, 11, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW),
+ NPCM8XX_PINCFG(215, rg2, MFSEL4, 24, ddr, MFSEL3, 26, rmii3, MFSEL5, 11, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW),
+ NPCM8XX_PINCFG(216, rg2mdio, MFSEL4, 23, ddr, MFSEL3, 26, none, NONE, 0, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW),
+ NPCM8XX_PINCFG(217, rg2mdio, MFSEL4, 23, ddr, MFSEL3, 26, none, NONE, 0, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW),
+ NPCM8XX_PINCFG(218, wdog1, MFSEL3, 19, smb16b, MFSEL7, 30, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW),
+ NPCM8XX_PINCFG(219, wdog2, MFSEL3, 20, smb16b, MFSEL7, 30, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW),
+ NPCM8XX_PINCFG(220, smb12, MFSEL3, 5, pwm8, MFSEL6, 11, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW),
+ NPCM8XX_PINCFG(221, smb12, MFSEL3, 5, pwm9, MFSEL6, 12, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW),
+ NPCM8XX_PINCFG(222, smb13, MFSEL3, 6, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW),
+ NPCM8XX_PINCFG(223, smb13, MFSEL3, 6, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW),
+ NPCM8XX_PINCFG(224, spix, MFSEL4, 27, fm2, MFSEL6, 18, none, NONE, 0, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW),
+ NPCM8XX_PINCFG(225, spix, MFSEL4, 27, fm2, MFSEL6, 18, none, NONE, 0, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW),
+ NPCM8XX_PINCFG(226, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, GPO | DSTR(8, 12) | SLEW),
+ NPCM8XX_PINCFG(227, spix, MFSEL4, 27, fm2, MFSEL6, 18, none, NONE, 0, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW),
+ NPCM8XX_PINCFG(228, spixcs1, MFSEL4, 28, fm2, MFSEL6, 18, none, NONE, 0, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW),
+ NPCM8XX_PINCFG(229, spix, MFSEL4, 27, fm2, MFSEL6, 18, none, NONE, 0, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW),
+ NPCM8XX_PINCFG(230, spix, MFSEL4, 27, fm2, MFSEL6, 18, none, NONE, 0, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW),
+ NPCM8XX_PINCFG(231, clkreq, MFSEL4, 9, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, DSTR(4, 12) | SLEW),
+ NPCM8XX_PINCFG(233, spi1cs1, MFSEL5, 0, fm1, MFSEL6, 17, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEWLPC), /* slewlpc ? */
+ NPCM8XX_PINCFG(234, pwm10, MFSEL6, 13, smb20, MFSEL5, 28, none, NONE, 0, none, NONE, 0, none, NONE, 0, 0),
+ NPCM8XX_PINCFG(235, pwm11, MFSEL6, 14, smb20, MFSEL5, 28, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW),
+ NPCM8XX_PINCFG(240, i3c0, MFSEL5, 17, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW),
+ NPCM8XX_PINCFG(241, i3c0, MFSEL5, 17, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW),
+ NPCM8XX_PINCFG(242, i3c1, MFSEL5, 19, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW),
+ NPCM8XX_PINCFG(243, i3c1, MFSEL5, 19, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW),
+ NPCM8XX_PINCFG(244, i3c2, MFSEL5, 21, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW),
+ NPCM8XX_PINCFG(245, i3c2, MFSEL5, 21, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW),
+ NPCM8XX_PINCFG(246, i3c3, MFSEL5, 23, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW),
+ NPCM8XX_PINCFG(247, i3c3, MFSEL5, 23, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW),
+ NPCM8XX_PINCFG(251, jm2, MFSEL5, 1, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW),
+ NPCM8XX_PINCFG(253, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, GPI), /* SDHC1 power */
+ NPCM8XX_PINCFG(254, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, GPI), /* SDHC2 power */
+ NPCM8XX_PINCFG(255, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, GPI), /* DACOSEL */
+};
+
+/* number, name, drv_data */
+static const struct pinctrl_pin_desc npcm8xx_pins[] = {
+ PINCTRL_PIN(0, "GPIO0/IOX1_DI/SMB6C_SDA/SMB18_SDA"),
+ PINCTRL_PIN(1, "GPIO1/IOX1_LD/SMB6C_SCL/SMB18_SCL"),
+ PINCTRL_PIN(2, "GPIO2/IOX1_CK/SMB6B_SDA/SMB17_SDA"),
+ PINCTRL_PIN(3, "GPIO3/IOX1_DO/SMB6B_SCL/SMB17_SCL"),
+ PINCTRL_PIN(4, "GPIO4/IOX2_DI/SMB1D_SDA"),
+ PINCTRL_PIN(5, "GPIO5/IOX2_LD/SMB1D_SCL"),
+ PINCTRL_PIN(6, "GPIO6/IOX2_CK/SMB2D_SDA"),
+ PINCTRL_PIN(7, "GPIO7/IOX2_D0/SMB2D_SCL"),
+ PINCTRL_PIN(8, "GPIO8/LKGPO1/TP_GPIO0"),
+ PINCTRL_PIN(9, "GPIO9/LKGPO2/TP_GPIO1"),
+ PINCTRL_PIN(10, "GPIO10/IOXH_LD/SMB6D_SCL/SMB16_SCL"),
+ PINCTRL_PIN(11, "GPIO11/IOXH_CK/SMB6D_SDA/SMB16_SDA"),
+ PINCTRL_PIN(12, "GPIO12/GSPI_CK/SMB5B_SCL"),
+ PINCTRL_PIN(13, "GPIO13/GSPI_DO/SMB5B_SDA"),
+ PINCTRL_PIN(14, "GPIO14/GSPI_DI/SMB5C_SCL"),
+ PINCTRL_PIN(15, "GPIO15/GSPI_CS/SMB5C_SDA"),
+ PINCTRL_PIN(16, "GPIO16/SMB7B_SDA/LKGPO0/TP_GPIO2"),
+ PINCTRL_PIN(17, "GPIO17/PSPI_DI/CP1_GPIO5"),
+ PINCTRL_PIN(18, "GPIO18/PSPI_D0/SMB4B_SDA"),
+ PINCTRL_PIN(19, "GPIO19/PSPI_CK/SMB4B_SCL"),
+ PINCTRL_PIN(20, "GPIO20/H_GPIO0/SMB4C_SDA/SMB15_SDA"),
+ PINCTRL_PIN(21, "GPIO21/H_GPIO1/SMB4C_SCL/SMB15_SCL"),
+ PINCTRL_PIN(22, "GPIO22/H_GPIO2/SMB4D_SDA/SMB14_SDA"),
+ PINCTRL_PIN(23, "GPIO23/H_GPIO3/SMB4D_SCL/SMB14_SCL"),
+ PINCTRL_PIN(24, "GPIO24/IOXH_DO/H_GPIO4/SMB7C_SCL/TP_SMB2_SCL"),
+ PINCTRL_PIN(25, "GPIO25/IOXH_DI/H_GPIO4/SMB7C_SDA/TP_SMB2_SDA"),
+ PINCTRL_PIN(26, "GPIO26/SMB5_SDA"),
+ PINCTRL_PIN(27, "GPIO27/SMB5_SCL"),
+ PINCTRL_PIN(28, "GPIO28/SMB4_SDA"),
+ PINCTRL_PIN(29, "GPIO29/SMB4_SCL"),
+ PINCTRL_PIN(30, "GPIO30/SMB3_SDA"),
+ PINCTRL_PIN(31, "GPIO31/SMB3_SCL"),
+ PINCTRL_PIN(32, "GPIO32/SMB14B_SCL/SPI0_nCS1"),
+ PINCTRL_PIN(33, "GPIO33/I3C4_SCL"),
+ PINCTRL_PIN(34, "GPIO34/I3C4_SDA"),
+ PINCTRL_PIN(37, "GPIO37/SMB3C_SDA/SMB23_SDA"),
+ PINCTRL_PIN(38, "GPIO38/SMB3C_SCL/SMB23_SCL"),
+ PINCTRL_PIN(39, "GPIO39/SMB3B_SDA/SMB22_SDA"),
+ PINCTRL_PIN(40, "GPIO40/SMB3B_SCL/SMB22_SCL"),
+ PINCTRL_PIN(41, "GPIO41/BU0_RXD/CP1U_RXD"),
+ PINCTRL_PIN(42, "GPIO42/BU0_TXD/CP1U_TXD"),
+ PINCTRL_PIN(43, "GPIO43/SI1_RXD/BU1_RXD"),
+ PINCTRL_PIN(44, "GPIO44/SI1_nCTS/BU1_nCTS/CP_TDI/TP_TDI/CP_TP_TDI"),
+ PINCTRL_PIN(45, "GPIO45/SI1_nDCD/CP_TMS_SWIO/TP_TMS_SWIO/CP_TP_TMS_SWIO"),
+ PINCTRL_PIN(46, "GPIO46/SI1_nDSR/CP_TCK_SWCLK/TP_TCK_SWCLK/CP_TP_TCK_SWCLK"),
+ PINCTRL_PIN(47, "GPIO47/SI1n_RI1"),
+ PINCTRL_PIN(48, "GPIO48/SI2_TXD/BU0_TXD/STRAP5"),
+ PINCTRL_PIN(49, "GPIO49/SI2_RXD/BU0_RXD"),
+ PINCTRL_PIN(50, "GPIO50/SI2_nCTS/BU6_TXD/TPU_TXD"),
+ PINCTRL_PIN(51, "GPIO51/SI2_nRTS/BU6_RXD/TPU_RXD"),
+ PINCTRL_PIN(52, "GPIO52/SI2_nDCD/BU5_RXD"),
+ PINCTRL_PIN(53, "GPIO53/SI2_nDTR_BOUT2/BU5_TXD"),
+ PINCTRL_PIN(54, "GPIO54/SI2_nDSR/BU4_TXD"),
+ PINCTRL_PIN(55, "GPIO55/SI2_RI2/BU4_RXD"),
+ PINCTRL_PIN(56, "GPIO56/R1_RXERR/R1_OEN"),
+ PINCTRL_PIN(57, "GPIO57/R1_MDC/TP_GPIO4"),
+ PINCTRL_PIN(58, "GPIO58/R1_MDIO/TP_GPIO5"),
+ PINCTRL_PIN(59, "GPIO59/H_GPIO06/SMB3D_SDA/SMB19_SDA"),
+ PINCTRL_PIN(60, "GPIO60/H_GPIO07/SMB3D_SCL/SMB19_SCL"),
+ PINCTRL_PIN(61, "GPIO61/SI1_nDTR_BOUT"),
+ PINCTRL_PIN(62, "GPIO62/SI1_nRTS/BU1_nRTS/CP_TDO_SWO/TP_TDO_SWO/CP_TP_TDO_SWO"),
+ PINCTRL_PIN(63, "GPIO63/BU1_TXD1/SI1_TXD"),
+ PINCTRL_PIN(64, "GPIO64/FANIN0"),
+ PINCTRL_PIN(65, "GPIO65/FANIN1"),
+ PINCTRL_PIN(66, "GPIO66/FANIN2"),
+ PINCTRL_PIN(67, "GPIO67/FANIN3"),
+ PINCTRL_PIN(68, "GPIO68/FANIN4"),
+ PINCTRL_PIN(69, "GPIO69/FANIN5"),
+ PINCTRL_PIN(70, "GPIO70/FANIN6"),
+ PINCTRL_PIN(71, "GPIO71/FANIN7"),
+ PINCTRL_PIN(72, "GPIO72/FANIN8"),
+ PINCTRL_PIN(73, "GPIO73/FANIN9"),
+ PINCTRL_PIN(74, "GPIO74/FANIN10"),
+ PINCTRL_PIN(75, "GPIO75/FANIN11"),
+ PINCTRL_PIN(76, "GPIO76/FANIN12"),
+ PINCTRL_PIN(77, "GPIO77/FANIN13"),
+ PINCTRL_PIN(78, "GPIO78/FANIN14"),
+ PINCTRL_PIN(79, "GPIO79/FANIN15"),
+ PINCTRL_PIN(80, "GPIO80/PWM0"),
+ PINCTRL_PIN(81, "GPIO81/PWM1"),
+ PINCTRL_PIN(82, "GPIO82/PWM2"),
+ PINCTRL_PIN(83, "GPIO83/PWM3"),
+ PINCTRL_PIN(84, "GPIO84/R2_TXD0"),
+ PINCTRL_PIN(85, "GPIO85/R2_TXD1"),
+ PINCTRL_PIN(86, "GPIO86/R2_TXEN"),
+ PINCTRL_PIN(87, "GPIO87/R2_RXD0"),
+ PINCTRL_PIN(88, "GPIO88/R2_RXD1"),
+ PINCTRL_PIN(89, "GPIO89/R2_CRSDV"),
+ PINCTRL_PIN(90, "GPIO90/R2_RXERR/R2_OEN"),
+ PINCTRL_PIN(91, "GPIO91/R2_MDC/CP1_GPIO6/TP_GPIO0"),
+ PINCTRL_PIN(92, "GPIO92/R2_MDIO/CP1_GPIO7/TP_GPIO1"),
+ PINCTRL_PIN(93, "GPIO93/GA20/SMB5D_SCL"),
+ PINCTRL_PIN(94, "GPIO94/nKBRST/SMB5D_SDA"),
+ PINCTRL_PIN(95, "GPIO95/nESPIRST/LPC_nLRESET"),
+ PINCTRL_PIN(96, "GPIO96/CP1_GPIO7/BU2_TXD/TP_GPIO7"),
+ PINCTRL_PIN(97, "GPIO97/CP1_GPIO6/BU2_RXD/TP_GPIO6"),
+ PINCTRL_PIN(98, "GPIO98/CP1_GPIO5/BU4_TXD/TP_GPIO5"),
+ PINCTRL_PIN(99, "GPIO99/CP1_GPIO4/BU4_RXD/TP_GPIO4"),
+ PINCTRL_PIN(100, "GPIO100/CP1_GPIO3/BU5_TXD/TP_GPIO3"),
+ PINCTRL_PIN(101, "GPIO101/CP1_GPIO2/BU5_RXD/TP_GPIO2"),
+ PINCTRL_PIN(102, "GPIO102/HSYNC"),
+ PINCTRL_PIN(103, "GPIO103/VSYNC"),
+ PINCTRL_PIN(104, "GPIO104/DDC_SCL"),
+ PINCTRL_PIN(105, "GPIO105/DDC_SDA"),
+ PINCTRL_PIN(106, "GPIO106/I3C5_SCL"),
+ PINCTRL_PIN(107, "GPIO107/I3C5_SDA"),
+ PINCTRL_PIN(108, "GPIO108/SG1_MDC"),
+ PINCTRL_PIN(109, "GPIO109/SG1_MDIO"),
+ PINCTRL_PIN(110, "GPIO110/RG2_TXD0/DDRV0/R3_TXD0"),
+ PINCTRL_PIN(111, "GPIO111/RG2_TXD1/DDRV1/R3_TXD1"),
+ PINCTRL_PIN(112, "GPIO112/RG2_TXD2/DDRV2"),
+ PINCTRL_PIN(113, "GPIO113/RG2_TXD3/DDRV3"),
+ PINCTRL_PIN(114, "GPIO114/SMB0_SCL"),
+ PINCTRL_PIN(115, "GPIO115/SMB0_SDA"),
+ PINCTRL_PIN(116, "GPIO116/SMB1_SCL"),
+ PINCTRL_PIN(117, "GPIO117/SMB1_SDA"),
+ PINCTRL_PIN(118, "GPIO118/SMB2_SCL"),
+ PINCTRL_PIN(119, "GPIO119/SMB2_SDA"),
+ PINCTRL_PIN(120, "GPIO120/SMB2C_SDA"),
+ PINCTRL_PIN(121, "GPIO121/SMB2C_SCL"),
+ PINCTRL_PIN(122, "GPIO122/SMB2B_SDA"),
+ PINCTRL_PIN(123, "GPIO123/SMB2B_SCL"),
+ PINCTRL_PIN(124, "GPIO124/SMB1C_SDA/CP1_GPIO3"),
+ PINCTRL_PIN(125, "GPIO125/SMB1C_SCL/CP1_GPIO2"),
+ PINCTRL_PIN(126, "GPIO126/SMB1B_SDA/CP1_GPIO1"),
+ PINCTRL_PIN(127, "GPIO127/SMB1B_SCL/CP1_GPIO0"),
+ PINCTRL_PIN(128, "GPIO128/SMB824_SCL"),
+ PINCTRL_PIN(129, "GPIO129/SMB824_SDA"),
+ PINCTRL_PIN(130, "GPIO130/SMB925_SCL"),
+ PINCTRL_PIN(131, "GPIO131/SMB925_SDA"),
+ PINCTRL_PIN(132, "GPIO132/SMB1026_SCL"),
+ PINCTRL_PIN(133, "GPIO133/SMB1026_SDA"),
+ PINCTRL_PIN(134, "GPIO134/SMB11_SCL/SMB23B_SCL"),
+ PINCTRL_PIN(135, "GPIO135/SMB11_SDA/SMB23B_SDA"),
+ PINCTRL_PIN(136, "GPIO136/JM1_TCK"),
+ PINCTRL_PIN(137, "GPIO137/JM1_TDO"),
+ PINCTRL_PIN(138, "GPIO138/JM1_TMS"),
+ PINCTRL_PIN(139, "GPIO139/JM1_TDI"),
+ PINCTRL_PIN(140, "GPIO140/JM1_nTRST"),
+ PINCTRL_PIN(141, "GPIO141/SMB7B_SCL"),
+ PINCTRL_PIN(142, "GPIO142/SMB7D_SCL/TPSMB1_SCL"),
+ PINCTRL_PIN(143, "GPIO143/SMB7D_SDA/TPSMB1_SDA"),
+ PINCTRL_PIN(144, "GPIO144/PWM4"),
+ PINCTRL_PIN(145, "GPIO145/PWM5"),
+ PINCTRL_PIN(146, "GPIO146/PWM6"),
+ PINCTRL_PIN(147, "GPIO147/PWM7"),
+ PINCTRL_PIN(148, "GPIO148/MMC_DT4"),
+ PINCTRL_PIN(149, "GPIO149/MMC_DT5"),
+ PINCTRL_PIN(150, "GPIO150/MMC_DT6"),
+ PINCTRL_PIN(151, "GPIO151/MMC_DT7"),
+ PINCTRL_PIN(152, "GPIO152/MMC_CLK"),
+ PINCTRL_PIN(153, "GPIO153/MMC_WP"),
+ PINCTRL_PIN(154, "GPIO154/MMC_CMD"),
+ PINCTRL_PIN(155, "GPIO155/MMC_nCD/MMC_nRSTLK"),
+ PINCTRL_PIN(156, "GPIO156/MMC_DT0"),
+ PINCTRL_PIN(157, "GPIO157/MMC_DT1"),
+ PINCTRL_PIN(158, "GPIO158/MMC_DT2"),
+ PINCTRL_PIN(159, "GPIO159/MMC_DT3"),
+ PINCTRL_PIN(160, "GPIO160/CLKOUT/RNGOSCOUT/GFXBYPCK"),
+ PINCTRL_PIN(161, "GPIO161/ESPI_nCS/LPC_nLFRAME"),
+ PINCTRL_PIN(162, "GPIO162/SERIRQ"),
+ PINCTRL_PIN(163, "GPIO163/ESPI_CK/LPC_LCLK"),
+ PINCTRL_PIN(164, "GPIO164/ESPI_IO0/LPC_LAD0"),
+ PINCTRL_PIN(165, "GPIO165/ESPI_IO1/LPC_LAD1"),
+ PINCTRL_PIN(166, "GPIO166/ESPI_IO2/LPC_LAD2"),
+ PINCTRL_PIN(167, "GPIO167/ESPI_IO3/LPC_LAD3"),
+ PINCTRL_PIN(168, "GPIO168/ESPI_nALERT/LPC_nCLKRUN"),
+ PINCTRL_PIN(169, "GPIO169/nSCIPME/SMB21_SCL"),
+ PINCTRL_PIN(170, "GPIO170/nSMI/SMB21_SDA"),
+ PINCTRL_PIN(171, "GPIO171/SMB6_SCL"),
+ PINCTRL_PIN(172, "GPIO172/SMB6_SDA"),
+ PINCTRL_PIN(173, "GPIO173/SMB7_SCL"),
+ PINCTRL_PIN(174, "GPIO174/SMB7_SDA"),
+ PINCTRL_PIN(175, "GPIO175/SPI1_CK/FANIN19/FM1_CK"),
+ PINCTRL_PIN(176, "GPIO176/SPI1_DO/FANIN18/FM1_DO/STRAP9"),
+ PINCTRL_PIN(177, "GPIO177/SPI1_DI/FANIN17/FM1_D1/STRAP10"),
+ PINCTRL_PIN(178, "GPIO178/R1_TXD0"),
+ PINCTRL_PIN(179, "GPIO179/R1_TXD1"),
+ PINCTRL_PIN(180, "GPIO180/R1_TXEN"),
+ PINCTRL_PIN(181, "GPIO181/R1_RXD0"),
+ PINCTRL_PIN(182, "GPIO182/R1_RXD1"),
+ PINCTRL_PIN(183, "GPIO183/SPI3_SEL"),
+ PINCTRL_PIN(184, "GPIO184/SPI3_D0/STRAP13"),
+ PINCTRL_PIN(185, "GPIO185/SPI3_D1"),
+ PINCTRL_PIN(186, "GPIO186/SPI3_nCS0"),
+ PINCTRL_PIN(187, "GPO187/SPI3_nCS1_SMB14B_SDA"),
+ PINCTRL_PIN(188, "GPIO188/SPI3_D2/SPI3_nCS2"),
+ PINCTRL_PIN(189, "GPIO189/SPI3_D3/SPI3_nCS3"),
+ PINCTRL_PIN(190, "GPIO190/nPRD_SMI"),
+ PINCTRL_PIN(191, "GPIO191/SPI1_D1/FANIN17/FM1_D1/STRAP10"),
+ PINCTRL_PIN(192, "GPIO192/SPI1_D3/SPI_nCS3/FM1_D3/SMB15_SCL"),
+ PINCTRL_PIN(193, "GPIO193/R1_CRSDV"),
+ PINCTRL_PIN(194, "GPIO194/SMB0B_SCL/FM0_CK"),
+ PINCTRL_PIN(195, "GPIO195/SMB0B_SDA/FM0_D0"),
+ PINCTRL_PIN(196, "GPIO196/SMB0C_SCL/FM0_D1"),
+ PINCTRL_PIN(197, "GPIO197/SMB0DEN/FM0_D3"),
+ PINCTRL_PIN(198, "GPIO198/SMB0D_SDA/FM0_D2"),
+ PINCTRL_PIN(199, "GPIO199/SMB0D_SCL/FM0_CSO"),
+ PINCTRL_PIN(200, "GPIO200/R2_CK"),
+ PINCTRL_PIN(201, "GPIO201/R1_CK"),
+ PINCTRL_PIN(202, "GPIO202/SMB0C_SDA/FM0_CSI"),
+ PINCTRL_PIN(203, "GPIO203/SPI1_nCS0/FANIN16/FM1_CSI"),
+ PINCTRL_PIN(208, "GPIO208/RG2_TXC/DVCK"),
+ PINCTRL_PIN(209, "GPIO209/RG2_TXCTL/DDRV4/R3_TXEN"),
+ PINCTRL_PIN(210, "GPIO210/RG2_RXD0/DDRV5/R3_RXD0"),
+ PINCTRL_PIN(211, "GPIO211/RG2_RXD1/DDRV6/R3_RXD1"),
+ PINCTRL_PIN(212, "GPIO212/RG2_RXD2/DDRV7/R3_RXD2"),
+ PINCTRL_PIN(213, "GPIO213/RG2_RXD3/DDRV8/R3_OEN"),
+ PINCTRL_PIN(214, "GPIO214/RG2_RXC/DDRV9/R3_CK"),
+ PINCTRL_PIN(215, "GPIO215/RG2_RXCTL/DDRV10/R3_CRSDV"),
+ PINCTRL_PIN(216, "GPIO216/RG2_MDC/DDRV11"),
+ PINCTRL_PIN(217, "GPIO217/RG2_MDIO/DVHSYNC"),
+ PINCTRL_PIN(218, "GPIO218/nWDO1/SMB16_SCL"),
+ PINCTRL_PIN(219, "GPIO219/nWDO2/SMB16_SDA"),
+ PINCTRL_PIN(220, "GPIO220/SMB12_SCL/PWM8"),
+ PINCTRL_PIN(221, "GPIO221/SMB12_SDA/PWM9"),
+ PINCTRL_PIN(222, "GPIO222/SMB13_SCL"),
+ PINCTRL_PIN(223, "GPIO223/SMB13_SDA"),
+ PINCTRL_PIN(224, "GPIO224/SPIX_CK/FM2_CK"),
+ PINCTRL_PIN(225, "GPO225/SPIX_D0/FM2_D0/STRAP1"),
+ PINCTRL_PIN(226, "GPO226/SPIX_D1/FM2_D1/STRAP2"),
+ PINCTRL_PIN(227, "GPIO227/SPIX_nCS0/FM2_CSI"),
+ PINCTRL_PIN(228, "GPIO228/SPIX_nCS1/FM2_CSO"),
+ PINCTRL_PIN(229, "GPO229/SPIX_D2/FM2_D2/STRAP3"),
+ PINCTRL_PIN(230, "GPO230/SPIX_D3/FM2_D3/STRAP6"),
+ PINCTRL_PIN(231, "GPIO231/EP_nCLKREQ"),
+ PINCTRL_PIN(233, "GPIO233/SPI1_nCS1/FM1_CSO"),
+ PINCTRL_PIN(234, "GPIO234/PWM10/SMB20_SCL"),
+ PINCTRL_PIN(235, "GPIO235/PWM11/SMB20_SDA"),
+ PINCTRL_PIN(240, "GPIO240/I3C0_SCL"),
+ PINCTRL_PIN(241, "GPIO241/I3C0_SDA"),
+ PINCTRL_PIN(242, "GPIO242/I3C1_SCL"),
+ PINCTRL_PIN(243, "GPIO243/I3C1_SDA"),
+ PINCTRL_PIN(244, "GPIO244/I3C2_SCL"),
+ PINCTRL_PIN(245, "GPIO245/I3C2_SDA"),
+ PINCTRL_PIN(246, "GPIO246/I3C3_SCL"),
+ PINCTRL_PIN(247, "GPIO247/I3C3_SDA"),
+ PINCTRL_PIN(250, "GPIO250/RG2_REFCK/DVVSYNC"),
+ PINCTRL_PIN(251, "JM2/CP1_GPIO"),
+ };
+
+/* Enable mode in pin group */
+static void npcm8xx_setfunc(struct regmap *gcr_regmap, const unsigned int *pin,
+ int pin_number, int mode)
+{
+ const struct npcm8xx_pincfg *cfg;
+ int i;
+
+ for (i = 0 ; i < pin_number ; i++) {
+ cfg = &pincfg[pin[i]];
+ if (mode == fn_gpio || cfg->fn0 == mode || cfg->fn1 == mode ||
+ cfg->fn2 == mode || cfg->fn3 == mode || cfg->fn4 == mode) {
+ if (cfg->reg0)
+ regmap_update_bits(gcr_regmap, cfg->reg0,
+ BIT(cfg->bit0),
+ (cfg->fn0 == mode) ?
+ BIT(cfg->bit0) : 0);
+ if (cfg->reg1)
+ regmap_update_bits(gcr_regmap, cfg->reg1,
+ BIT(cfg->bit1),
+ (cfg->fn1 == mode) ?
+ BIT(cfg->bit1) : 0);
+ if (cfg->reg2)
+ regmap_update_bits(gcr_regmap, cfg->reg2,
+ BIT(cfg->bit2),
+ (cfg->fn2 == mode) ?
+ BIT(cfg->bit2) : 0);
+ if (cfg->reg3)
+ regmap_update_bits(gcr_regmap, cfg->reg3,
+ BIT(cfg->bit3),
+ (cfg->fn3 == mode) ?
+ BIT(cfg->bit3) : 0);
+ if (cfg->reg4)
+ regmap_update_bits(gcr_regmap, cfg->reg4,
+ BIT(cfg->bit4),
+ (cfg->fn4 == mode) ?
+ BIT(cfg->bit4) : 0);
+ }
+ }
+}
+
+static int npcm8xx_get_slew_rate(struct npcm8xx_gpio *bank,
+ struct regmap *gcr_regmap, unsigned int pin)
+{
+ int gpio = pin % bank->gc.ngpio;
+ unsigned long pinmask = BIT(gpio);
+ u32 val;
+
+ if (pincfg[pin].flag & SLEW)
+ return ioread32(bank->base + NPCM8XX_GP_N_OSRC) & pinmask;
+ /* LPC Slew rate in SRCNT register */
+ if (pincfg[pin].flag & SLEWLPC) {
+ regmap_read(gcr_regmap, NPCM8XX_GCR_SRCNT, &val);
+ return !!(val & SRCNT_ESPI);
+ }
+
+ return -EINVAL;
+}
+
+static int npcm8xx_set_slew_rate(struct npcm8xx_gpio *bank,
+ struct regmap *gcr_regmap, unsigned int pin,
+ int arg)
+{
+ void __iomem *OSRC_Offset = bank->base + NPCM8XX_GP_N_OSRC;
+ int gpio = BIT(pin % bank->gc.ngpio);
+
+ if (pincfg[pin].flag & SLEW) {
+ switch (arg) {
+ case 0:
+ npcm_gpio_clr(&bank->gc, OSRC_Offset, gpio);
+ return 0;
+ case 1:
+ npcm_gpio_set(&bank->gc, OSRC_Offset, gpio);
+ return 0;
+ default:
+ return -EINVAL;
+ }
+ }
+
+ if (!(pincfg[pin].flag & SLEWLPC))
+ return -EINVAL;
+
+ switch (arg) {
+ case 0:
+ regmap_update_bits(gcr_regmap, NPCM8XX_GCR_SRCNT,
+ SRCNT_ESPI, 0);
+ break;
+ case 1:
+ regmap_update_bits(gcr_regmap, NPCM8XX_GCR_SRCNT,
+ SRCNT_ESPI, SRCNT_ESPI);
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+static int npcm8xx_get_drive_strength(struct pinctrl_dev *pctldev,
+ unsigned int pin)
+{
+ struct npcm8xx_pinctrl *npcm = pinctrl_dev_get_drvdata(pctldev);
+ struct npcm8xx_gpio *bank =
+ &npcm->gpio_bank[pin / NPCM8XX_GPIO_PER_BANK];
+ int gpio = pin % bank->gc.ngpio;
+ unsigned long pinmask = BIT(gpio);
+ int flg, val;
+ u32 ds = 0;
+
+ flg = pincfg[pin].flag;
+ if (!(flg & DRIVE_STRENGTH_MASK))
+ return -EINVAL;
+
+ val = ioread32(bank->base + NPCM8XX_GP_N_ODSC) & pinmask;
+ ds = val ? DSHI(flg) : DSLO(flg);
+ dev_dbg(bank->gc.parent, "pin %d strength %d = %d\n", pin, val, ds);
+
+ return ds;
+}
+
+static int npcm8xx_set_drive_strength(struct npcm8xx_pinctrl *npcm,
+ unsigned int pin, int nval)
+{
+ struct npcm8xx_gpio *bank =
+ &npcm->gpio_bank[pin / NPCM8XX_GPIO_PER_BANK];
+ int gpio = BIT(pin % bank->gc.ngpio);
+ int v;
+
+ v = pincfg[pin].flag & DRIVE_STRENGTH_MASK;
+
+ if (DSLO(v) == nval)
+ npcm_gpio_clr(&bank->gc, bank->base + NPCM8XX_GP_N_ODSC, gpio);
+ else if (DSHI(v) == nval)
+ npcm_gpio_set(&bank->gc, bank->base + NPCM8XX_GP_N_ODSC, gpio);
+ else
+ return -ENOTSUPP;
+
+ return 0;
+}
+
+/* pinctrl_ops */
+static int npcm8xx_get_groups_count(struct pinctrl_dev *pctldev)
+{
+ return ARRAY_SIZE(npcm8xx_pingroups);
+}
+
+static const char *npcm8xx_get_group_name(struct pinctrl_dev *pctldev,
+ unsigned int selector)
+{
+ return npcm8xx_pingroups[selector].name;
+}
+
+static int npcm8xx_get_group_pins(struct pinctrl_dev *pctldev,
+ unsigned int selector,
+ const unsigned int **pins,
+ unsigned int *npins)
+{
+ *npins = npcm8xx_pingroups[selector].npins;
+ *pins = npcm8xx_pingroups[selector].pins;
+
+ return 0;
+}
+
+static int npcm8xx_dt_node_to_map(struct pinctrl_dev *pctldev,
+ struct device_node *np_config,
+ struct pinctrl_map **map,
+ u32 *num_maps)
+{
+ return pinconf_generic_dt_node_to_map(pctldev, np_config,
+ map, num_maps,
+ PIN_MAP_TYPE_INVALID);
+}
+
+static void npcm8xx_dt_free_map(struct pinctrl_dev *pctldev,
+ struct pinctrl_map *map, u32 num_maps)
+{
+ kfree(map);
+}
+
+static const struct pinctrl_ops npcm8xx_pinctrl_ops = {
+ .get_groups_count = npcm8xx_get_groups_count,
+ .get_group_name = npcm8xx_get_group_name,
+ .get_group_pins = npcm8xx_get_group_pins,
+ .dt_node_to_map = npcm8xx_dt_node_to_map,
+ .dt_free_map = npcm8xx_dt_free_map,
+};
+
+static int npcm8xx_get_functions_count(struct pinctrl_dev *pctldev)
+{
+ return ARRAY_SIZE(npcm8xx_funcs);
+}
+
+static const char *npcm8xx_get_function_name(struct pinctrl_dev *pctldev,
+ unsigned int function)
+{
+ return npcm8xx_funcs[function].name;
+}
+
+static int npcm8xx_get_function_groups(struct pinctrl_dev *pctldev,
+ unsigned int function,
+ const char * const **groups,
+ unsigned int * const ngroups)
+{
+ *ngroups = npcm8xx_funcs[function].ngroups;
+ *groups = npcm8xx_funcs[function].groups;
+
+ return 0;
+}
+
+static int npcm8xx_pinmux_set_mux(struct pinctrl_dev *pctldev,
+ unsigned int function,
+ unsigned int group)
+{
+ struct npcm8xx_pinctrl *npcm = pinctrl_dev_get_drvdata(pctldev);
+
+ npcm8xx_setfunc(npcm->gcr_regmap, npcm8xx_pingroups[group].pins,
+ npcm8xx_pingroups[group].npins, group);
+
+ return 0;
+}
+
+static int npcm8xx_gpio_request_enable(struct pinctrl_dev *pctldev,
+ struct pinctrl_gpio_range *range,
+ unsigned int offset)
+{
+ struct npcm8xx_pinctrl *npcm = pinctrl_dev_get_drvdata(pctldev);
+ const unsigned int *pin = &offset;
+ int mode = fn_gpio;
+
+ if (pin[0] >= 183 && pin[0] <= 189)
+ mode = pincfg[pin[0]].fn0;
+
+ npcm8xx_setfunc(npcm->gcr_regmap, &offset, 1, mode);
+
+ return 0;
+}
+
+static void npcm8xx_gpio_request_free(struct pinctrl_dev *pctldev,
+ struct pinctrl_gpio_range *range,
+ unsigned int offset)
+{
+ struct npcm8xx_pinctrl *npcm = pinctrl_dev_get_drvdata(pctldev);
+ int virq;
+
+ virq = irq_find_mapping(npcm->domain, offset);
+ if (virq)
+ irq_dispose_mapping(virq);
+}
+
+static int npcm_gpio_set_direction(struct pinctrl_dev *pctldev,
+ struct pinctrl_gpio_range *range,
+ unsigned int offset, bool input)
+{
+ struct npcm8xx_pinctrl *npcm = pinctrl_dev_get_drvdata(pctldev);
+ struct npcm8xx_gpio *bank =
+ &npcm->gpio_bank[offset / NPCM8XX_GPIO_PER_BANK];
+ int gpio = BIT(offset % bank->gc.ngpio);
+
+ if (input)
+ iowrite32(gpio, bank->base + NPCM8XX_GP_N_OEC);
+ else
+ iowrite32(gpio, bank->base + NPCM8XX_GP_N_OES);
+
+ return 0;
+}
+
+static const struct pinmux_ops npcm8xx_pinmux_ops = {
+ .get_functions_count = npcm8xx_get_functions_count,
+ .get_function_name = npcm8xx_get_function_name,
+ .get_function_groups = npcm8xx_get_function_groups,
+ .set_mux = npcm8xx_pinmux_set_mux,
+ .gpio_request_enable = npcm8xx_gpio_request_enable,
+ .gpio_disable_free = npcm8xx_gpio_request_free,
+ .gpio_set_direction = npcm_gpio_set_direction,
+};
+
+static int debounce_timing_setting(struct npcm8xx_gpio *bank, u32 gpio,
+ u32 nanosecs)
+{
+ void __iomem *DBNCS_offset = bank->base + NPCM8XX_GP_N_DBNCS0 + (gpio / 4);
+ int gpio_debounce = (gpio % 16) * 2, debounce_select, i;
+ u32 dbncp_val, dbncp_val_mod;
+
+ for (i = 0 ; i < NPCM8XX_DEBOUNCE_MAX ; i++) {
+ if (bank->debounce.set_val[i]) {
+ if (bank->debounce.nanosec_val[i] == nanosecs) {
+ debounce_select = i << gpio_debounce;
+ npcm_gpio_set(&bank->gc, DBNCS_offset,
+ debounce_select);
+ break;
+ }
+ } else {
+ bank->debounce.set_val[i] = true;
+ bank->debounce.nanosec_val[i] = nanosecs;
+ debounce_select = i << gpio_debounce;
+ npcm_gpio_set(&bank->gc, DBNCS_offset, debounce_select);
+ switch (nanosecs) {
+ case 1 ... 1040:
+ iowrite32(0, bank->base + NPCM8XX_GP_N_DBNCP0 + (i * 4));
+ break;
+ case 1041 ... 1640:
+ iowrite32(0x10, bank->base + NPCM8XX_GP_N_DBNCP0 + (i * 4));
+ break;
+ case 1641 ... 2280:
+ iowrite32(0x20, bank->base + NPCM8XX_GP_N_DBNCP0 + (i * 4));
+ break;
+ case 2281 ... 2700:
+ iowrite32(0x30, bank->base + NPCM8XX_GP_N_DBNCP0 + (i * 4));
+ break;
+ case 2701 ... 2856:
+ iowrite32(0x40, bank->base + NPCM8XX_GP_N_DBNCP0 + (i * 4));
+ break;
+ case 2857 ... 3496:
+ iowrite32(0x50, bank->base + NPCM8XX_GP_N_DBNCP0 + (i * 4));
+ break;
+ case 3497 ... 4136:
+ iowrite32(0x60, bank->base + NPCM8XX_GP_N_DBNCP0 + (i * 4));
+ break;
+ case 4137 ... 5025:
+ iowrite32(0x70, bank->base + NPCM8XX_GP_N_DBNCP0 + (i * 4));
+ break;
+ default:
+ dbncp_val = DIV_ROUND_CLOSEST(nanosecs, NPCM8XX_DEBOUNCE_NSEC);
+ if (dbncp_val > NPCM8XX_DEBOUNCE_MAX_VAL)
+ return -ENOTSUPP;
+ dbncp_val_mod = dbncp_val & GENMASK(3, 0);
+ if (dbncp_val_mod > GENMASK(2, 0))
+ dbncp_val += 0x10;
+ iowrite32(dbncp_val & NPCM8XX_DEBOUNCE_VAL_MASK,
+ bank->base + NPCM8XX_GP_N_DBNCP0 + (i * 4));
+ break;
+ }
+ break;
+ }
+ }
+
+ if (i == 4)
+ return -ENOTSUPP;
+
+ return 0;
+}
+
+static int npcm_set_debounce(struct npcm8xx_pinctrl *npcm, unsigned int pin,
+ u32 nanosecs)
+{
+ struct npcm8xx_gpio *bank =
+ &npcm->gpio_bank[pin / NPCM8XX_GPIO_PER_BANK];
+ int gpio = BIT(pin % bank->gc.ngpio);
+ int ret;
+
+ if (nanosecs) {
+ ret = debounce_timing_setting(bank, pin % bank->gc.ngpio,
+ nanosecs);
+ if (ret)
+ dev_err(npcm->dev, "Pin %d, All four debounce timing values are used, please use one of exist debounce values\n", pin);
+ else
+ npcm_gpio_set(&bank->gc, bank->base + NPCM8XX_GP_N_DBNC,
+ gpio);
+ return ret;
+ }
+
+ npcm_gpio_clr(&bank->gc, bank->base + NPCM8XX_GP_N_DBNC, gpio);
+
+ return 0;
+}
+
+/* pinconf_ops */
+static int npcm8xx_config_get(struct pinctrl_dev *pctldev, unsigned int pin,
+ unsigned long *config)
+{
+ enum pin_config_param param = pinconf_to_config_param(*config);
+ struct npcm8xx_pinctrl *npcm = pinctrl_dev_get_drvdata(pctldev);
+ struct npcm8xx_gpio *bank =
+ &npcm->gpio_bank[pin / NPCM8XX_GPIO_PER_BANK];
+ int gpio = pin % bank->gc.ngpio;
+ unsigned long pinmask = BIT(gpio);
+ u32 ie, oe, pu, pd;
+ int rc = 0;
+
+ switch (param) {
+ case PIN_CONFIG_BIAS_DISABLE:
+ case PIN_CONFIG_BIAS_PULL_UP:
+ case PIN_CONFIG_BIAS_PULL_DOWN:
+ pu = ioread32(bank->base + NPCM8XX_GP_N_PU) & pinmask;
+ pd = ioread32(bank->base + NPCM8XX_GP_N_PD) & pinmask;
+ if (param == PIN_CONFIG_BIAS_DISABLE)
+ rc = !pu && !pd;
+ else if (param == PIN_CONFIG_BIAS_PULL_UP)
+ rc = pu && !pd;
+ else if (param == PIN_CONFIG_BIAS_PULL_DOWN)
+ rc = !pu && pd;
+ break;
+ case PIN_CONFIG_OUTPUT:
+ case PIN_CONFIG_INPUT_ENABLE:
+ ie = ioread32(bank->base + NPCM8XX_GP_N_IEM) & pinmask;
+ oe = ioread32(bank->base + NPCM8XX_GP_N_OE) & pinmask;
+ if (param == PIN_CONFIG_INPUT_ENABLE)
+ rc = (ie && !oe);
+ else if (param == PIN_CONFIG_OUTPUT)
+ rc = (!ie && oe);
+ break;
+ case PIN_CONFIG_DRIVE_PUSH_PULL:
+ rc = !(ioread32(bank->base + NPCM8XX_GP_N_OTYP) & pinmask);
+ break;
+ case PIN_CONFIG_DRIVE_OPEN_DRAIN:
+ rc = ioread32(bank->base + NPCM8XX_GP_N_OTYP) & pinmask;
+ break;
+ case PIN_CONFIG_INPUT_DEBOUNCE:
+ rc = ioread32(bank->base + NPCM8XX_GP_N_DBNC) & pinmask;
+ break;
+ case PIN_CONFIG_DRIVE_STRENGTH:
+ rc = npcm8xx_get_drive_strength(pctldev, pin);
+ if (rc)
+ *config = pinconf_to_config_packed(param, rc);
+ break;
+ case PIN_CONFIG_SLEW_RATE:
+ rc = npcm8xx_get_slew_rate(bank, npcm->gcr_regmap, pin);
+ if (rc >= 0)
+ *config = pinconf_to_config_packed(param, rc);
+ break;
+ default:
+ return -ENOTSUPP;
+ }
+
+ if (!rc)
+ return -EINVAL;
+
+ return 0;
+}
+
+static int npcm8xx_config_set_one(struct npcm8xx_pinctrl *npcm,
+ unsigned int pin, unsigned long config)
+{
+ enum pin_config_param param = pinconf_to_config_param(config);
+ struct npcm8xx_gpio *bank =
+ &npcm->gpio_bank[pin / NPCM8XX_GPIO_PER_BANK];
+ u32 arg = pinconf_to_config_argument(config);
+ int gpio = BIT(pin % bank->gc.ngpio);
+
+ switch (param) {
+ case PIN_CONFIG_BIAS_DISABLE:
+ npcm_gpio_clr(&bank->gc, bank->base + NPCM8XX_GP_N_PU, gpio);
+ npcm_gpio_clr(&bank->gc, bank->base + NPCM8XX_GP_N_PD, gpio);
+ break;
+ case PIN_CONFIG_BIAS_PULL_DOWN:
+ npcm_gpio_clr(&bank->gc, bank->base + NPCM8XX_GP_N_PU, gpio);
+ npcm_gpio_set(&bank->gc, bank->base + NPCM8XX_GP_N_PD, gpio);
+ break;
+ case PIN_CONFIG_BIAS_PULL_UP:
+ npcm_gpio_clr(&bank->gc, bank->base + NPCM8XX_GP_N_PD, gpio);
+ npcm_gpio_set(&bank->gc, bank->base + NPCM8XX_GP_N_PU, gpio);
+ break;
+ case PIN_CONFIG_INPUT_ENABLE:
+ iowrite32(gpio, bank->base + NPCM8XX_GP_N_OEC);
+ bank->direction_input(&bank->gc, pin % bank->gc.ngpio);
+ break;
+ case PIN_CONFIG_OUTPUT:
+ bank->direction_output(&bank->gc, pin % bank->gc.ngpio, arg);
+ iowrite32(gpio, bank->base + NPCM8XX_GP_N_OES);
+ break;
+ case PIN_CONFIG_DRIVE_PUSH_PULL:
+ npcm_gpio_clr(&bank->gc, bank->base + NPCM8XX_GP_N_OTYP, gpio);
+ break;
+ case PIN_CONFIG_DRIVE_OPEN_DRAIN:
+ npcm_gpio_set(&bank->gc, bank->base + NPCM8XX_GP_N_OTYP, gpio);
+ break;
+ case PIN_CONFIG_INPUT_DEBOUNCE:
+ return npcm_set_debounce(npcm, pin, arg * 1000);
+ case PIN_CONFIG_SLEW_RATE:
+ return npcm8xx_set_slew_rate(bank, npcm->gcr_regmap, pin, arg);
+ case PIN_CONFIG_DRIVE_STRENGTH:
+ return npcm8xx_set_drive_strength(npcm, pin, arg);
+ default:
+ return -ENOTSUPP;
+ }
+
+ return 0;
+}
+
+static int npcm8xx_config_set(struct pinctrl_dev *pctldev, unsigned int pin,
+ unsigned long *configs, unsigned int num_configs)
+{
+ struct npcm8xx_pinctrl *npcm = pinctrl_dev_get_drvdata(pctldev);
+ int rc;
+
+ while (num_configs--) {
+ rc = npcm8xx_config_set_one(npcm, pin, *configs++);
+ if (rc)
+ return rc;
+ }
+
+ return 0;
+}
+
+static const struct pinconf_ops npcm8xx_pinconf_ops = {
+ .is_generic = true,
+ .pin_config_get = npcm8xx_config_get,
+ .pin_config_set = npcm8xx_config_set,
+};
+
+/* pinctrl_desc */
+static struct pinctrl_desc npcm8xx_pinctrl_desc = {
+ .name = "npcm8xx-pinctrl",
+ .pins = npcm8xx_pins,
+ .npins = ARRAY_SIZE(npcm8xx_pins),
+ .pctlops = &npcm8xx_pinctrl_ops,
+ .pmxops = &npcm8xx_pinmux_ops,
+ .confops = &npcm8xx_pinconf_ops,
+ .owner = THIS_MODULE,
+};
+
+static int npcmgpio_add_pin_ranges(struct gpio_chip *chip)
+{
+ struct npcm8xx_gpio *bank = gpiochip_get_data(chip);
+
+ return gpiochip_add_pin_range(&bank->gc, dev_name(chip->parent),
+ bank->pinctrl_id, bank->gc.base,
+ bank->gc.ngpio);
+}
+
+static int npcm8xx_gpio_fw(struct npcm8xx_pinctrl *pctrl)
+{
+ struct fwnode_reference_args args;
+ struct device *dev = pctrl->dev;
+ struct fwnode_handle *child;
+ int ret = -ENXIO;
+ int id = 0, i;
+
+ for_each_gpiochip_node(dev, child) {
+ pctrl->gpio_bank[id].base = fwnode_iomap(child, 0);
+ if (!pctrl->gpio_bank[id].base)
+ return dev_err_probe(dev, -ENXIO, "fwnode_iomap id %d failed\n", id);
+
+ ret = bgpio_init(&pctrl->gpio_bank[id].gc, dev, 4,
+ pctrl->gpio_bank[id].base + NPCM8XX_GP_N_DIN,
+ pctrl->gpio_bank[id].base + NPCM8XX_GP_N_DOUT,
+ NULL,
+ NULL,
+ pctrl->gpio_bank[id].base + NPCM8XX_GP_N_IEM,
+ BGPIOF_READ_OUTPUT_REG_SET);
+ if (ret)
+ return dev_err_probe(dev, ret, "bgpio_init() failed\n");
+
+ ret = fwnode_property_get_reference_args(child, "gpio-ranges", NULL, 3, 0, &args);
+ if (ret < 0)
+ return dev_err_probe(dev, ret, "gpio-ranges fail for GPIO bank %u\n", id);
+
+ ret = fwnode_irq_get(child, 0);
+ if (!ret)
+ return dev_err_probe(dev, ret, "No IRQ for GPIO bank %u\n", id);
+
+ pctrl->gpio_bank[id].irq = ret;
+ pctrl->gpio_bank[id].irq_chip = npcmgpio_irqchip;
+ pctrl->gpio_bank[id].irqbase = id * NPCM8XX_GPIO_PER_BANK;
+ pctrl->gpio_bank[id].pinctrl_id = args.args[0];
+ pctrl->gpio_bank[id].gc.base = -1;
+ pctrl->gpio_bank[id].gc.ngpio = args.args[2];
+ pctrl->gpio_bank[id].gc.owner = THIS_MODULE;
+ pctrl->gpio_bank[id].gc.parent = dev;
+ pctrl->gpio_bank[id].gc.fwnode = child;
+ pctrl->gpio_bank[id].gc.label = devm_kasprintf(dev, GFP_KERNEL, "%pfw", child);
+ pctrl->gpio_bank[id].gc.dbg_show = npcmgpio_dbg_show;
+ pctrl->gpio_bank[id].direction_input = pctrl->gpio_bank[id].gc.direction_input;
+ pctrl->gpio_bank[id].gc.direction_input = npcmgpio_direction_input;
+ pctrl->gpio_bank[id].direction_output = pctrl->gpio_bank[id].gc.direction_output;
+ pctrl->gpio_bank[id].gc.direction_output = npcmgpio_direction_output;
+ pctrl->gpio_bank[id].request = pctrl->gpio_bank[id].gc.request;
+ pctrl->gpio_bank[id].gc.request = npcmgpio_gpio_request;
+ pctrl->gpio_bank[id].gc.free = pinctrl_gpio_free;
+ for (i = 0 ; i < NPCM8XX_DEBOUNCE_MAX ; i++)
+ pctrl->gpio_bank[id].debounce.set_val[i] = false;
+ pctrl->gpio_bank[id].gc.add_pin_ranges = npcmgpio_add_pin_ranges;
+ id++;
+ }
+
+ pctrl->bank_num = id;
+ return ret;
+}
+
+static int npcm8xx_gpio_register(struct npcm8xx_pinctrl *pctrl)
+{
+ int ret, id;
+
+ for (id = 0 ; id < pctrl->bank_num ; id++) {
+ struct gpio_irq_chip *girq;
+
+ girq = &pctrl->gpio_bank[id].gc.irq;
+ girq->chip = &pctrl->gpio_bank[id].irq_chip;
+ girq->parent_handler = npcmgpio_irq_handler;
+ girq->num_parents = 1;
+ girq->parents = devm_kcalloc(pctrl->dev, girq->num_parents,
+ sizeof(*girq->parents),
+ GFP_KERNEL);
+ if (!girq->parents)
+ return -ENOMEM;
+
+ girq->parents[0] = pctrl->gpio_bank[id].irq;
+ girq->default_type = IRQ_TYPE_NONE;
+ girq->handler = handle_level_irq;
+ ret = devm_gpiochip_add_data(pctrl->dev,
+ &pctrl->gpio_bank[id].gc,
+ &pctrl->gpio_bank[id]);
+ if (ret)
+ return dev_err_probe(pctrl->dev, ret, "Failed to add GPIO chip %u\n", id);
+ }
+
+ return 0;
+}
+
+static int npcm8xx_pinctrl_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct npcm8xx_pinctrl *pctrl;
+ int ret;
+
+ pctrl = devm_kzalloc(dev, sizeof(*pctrl), GFP_KERNEL);
+ if (!pctrl)
+ return -ENOMEM;
+
+ pctrl->dev = dev;
+ platform_set_drvdata(pdev, pctrl);
+
+ pctrl->gcr_regmap =
+ syscon_regmap_lookup_by_phandle(dev->of_node, "nuvoton,sysgcr");
+ if (IS_ERR(pctrl->gcr_regmap))
+ return dev_err_probe(dev, PTR_ERR(pctrl->gcr_regmap),
+ "Failed to find nuvoton,sysgcr property\n");
+
+ ret = npcm8xx_gpio_fw(pctrl);
+ if (ret < 0)
+ return dev_err_probe(dev, ret,
+ "Failed to gpio dt-binding\n");
+
+ pctrl->pctldev = devm_pinctrl_register(dev, &npcm8xx_pinctrl_desc, pctrl);
+ if (IS_ERR(pctrl->pctldev))
+ return dev_err_probe(dev, PTR_ERR(pctrl->pctldev),
+ "Failed to register pinctrl device\n");
+
+ ret = npcm8xx_gpio_register(pctrl);
+ if (ret < 0)
+ dev_err_probe(dev, ret, "Failed to register gpio\n");
+
+ return 0;
+}
+
+static const struct of_device_id npcm8xx_pinctrl_match[] = {
+ { .compatible = "nuvoton,npcm845-pinctrl" },
+ { }
+};
+MODULE_DEVICE_TABLE(of, npcm8xx_pinctrl_match);
+
+static struct platform_driver npcm8xx_pinctrl_driver = {
+ .probe = npcm8xx_pinctrl_probe,
+ .driver = {
+ .name = "npcm8xx-pinctrl",
+ .of_match_table = npcm8xx_pinctrl_match,
+ .suppress_bind_attrs = true,
+ },
+};
+
+static int __init npcm8xx_pinctrl_register(void)
+{
+ return platform_driver_register(&npcm8xx_pinctrl_driver);
+}
+arch_initcall(npcm8xx_pinctrl_register);
+
+MODULE_LICENSE("GPL v2");
+MODULE_AUTHOR("tomer.maimon@nuvoton.com");
+MODULE_DESCRIPTION("Nuvoton NPCM8XX Pinctrl and GPIO driver");
diff --git a/drivers/pinctrl/nuvoton/pinctrl-wpcm450.c b/drivers/pinctrl/nuvoton/pinctrl-wpcm450.c
index 8a9961ac87..0cff44b07b 100644
--- a/drivers/pinctrl/nuvoton/pinctrl-wpcm450.c
+++ b/drivers/pinctrl/nuvoton/pinctrl-wpcm450.c
@@ -858,16 +858,6 @@ static int wpcm450_get_group_pins(struct pinctrl_dev *pctldev,
return 0;
}
-static int wpcm450_dt_node_to_map(struct pinctrl_dev *pctldev,
- struct device_node *np_config,
- struct pinctrl_map **map,
- u32 *num_maps)
-{
- return pinconf_generic_dt_node_to_map(pctldev, np_config,
- map, num_maps,
- PIN_MAP_TYPE_INVALID);
-}
-
static void wpcm450_dt_free_map(struct pinctrl_dev *pctldev,
struct pinctrl_map *map, u32 num_maps)
{
@@ -878,7 +868,7 @@ static const struct pinctrl_ops wpcm450_pinctrl_ops = {
.get_groups_count = wpcm450_get_groups_count,
.get_group_name = wpcm450_get_group_name,
.get_group_pins = wpcm450_get_group_pins,
- .dt_node_to_map = wpcm450_dt_node_to_map,
+ .dt_node_to_map = pinconf_generic_dt_node_to_map_all,
.dt_free_map = wpcm450_dt_free_map,
};
diff --git a/drivers/pinctrl/pinconf-generic.c b/drivers/pinctrl/pinconf-generic.c
index 365c4b0ca4..8313cb5f3b 100644
--- a/drivers/pinctrl/pinconf-generic.c
+++ b/drivers/pinctrl/pinconf-generic.c
@@ -10,17 +10,19 @@
#define pr_fmt(fmt) "generic pinconfig core: " fmt
-#include <linux/kernel.h>
-#include <linux/module.h>
-#include <linux/init.h>
+#include <linux/array_size.h>
+#include <linux/debugfs.h>
#include <linux/device.h>
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/of.h>
#include <linux/slab.h>
-#include <linux/debugfs.h>
#include <linux/seq_file.h>
-#include <linux/pinctrl/pinctrl.h>
-#include <linux/pinctrl/pinconf.h>
+
#include <linux/pinctrl/pinconf-generic.h>
-#include <linux/of.h>
+#include <linux/pinctrl/pinconf.h>
+#include <linux/pinctrl/pinctrl.h>
+
#include "core.h"
#include "pinconf.h"
#include "pinctrl-utils.h"
diff --git a/drivers/pinctrl/pinconf.c b/drivers/pinctrl/pinconf.c
index d9d5406547..96d853a8f3 100644
--- a/drivers/pinctrl/pinconf.c
+++ b/drivers/pinctrl/pinconf.c
@@ -9,16 +9,18 @@
*/
#define pr_fmt(fmt) "pinconfig core: " fmt
-#include <linux/kernel.h>
-#include <linux/module.h>
-#include <linux/init.h>
-#include <linux/device.h>
-#include <linux/slab.h>
+#include <linux/array_size.h>
#include <linux/debugfs.h>
+#include <linux/device.h>
+#include <linux/init.h>
+#include <linux/module.h>
#include <linux/seq_file.h>
+#include <linux/slab.h>
+
#include <linux/pinctrl/machine.h>
-#include <linux/pinctrl/pinctrl.h>
#include <linux/pinctrl/pinconf.h>
+#include <linux/pinctrl/pinctrl.h>
+
#include "core.h"
#include "pinconf.h"
diff --git a/drivers/pinctrl/pinctrl-amd.c b/drivers/pinctrl/pinctrl-amd.c
index 86034c457c..03ecb3d1aa 100644
--- a/drivers/pinctrl/pinctrl-amd.c
+++ b/drivers/pinctrl/pinctrl-amd.c
@@ -1175,7 +1175,7 @@ out2:
return ret;
}
-static int amd_gpio_remove(struct platform_device *pdev)
+static void amd_gpio_remove(struct platform_device *pdev)
{
struct amd_gpio *gpio_dev;
@@ -1183,8 +1183,6 @@ static int amd_gpio_remove(struct platform_device *pdev)
gpiochip_remove(&gpio_dev->gc);
acpi_unregister_wakeup_handler(amd_gpio_check_wake, gpio_dev);
-
- return 0;
}
#ifdef CONFIG_ACPI
@@ -1206,7 +1204,7 @@ static struct platform_driver amd_gpio_driver = {
#endif
},
.probe = amd_gpio_probe,
- .remove = amd_gpio_remove,
+ .remove_new = amd_gpio_remove,
};
module_platform_driver(amd_gpio_driver);
diff --git a/drivers/pinctrl/pinctrl-artpec6.c b/drivers/pinctrl/pinctrl-artpec6.c
index d6c9f9dcff..dd93f124e0 100644
--- a/drivers/pinctrl/pinctrl-artpec6.c
+++ b/drivers/pinctrl/pinctrl-artpec6.c
@@ -970,13 +970,11 @@ static int artpec6_pmx_probe(struct platform_device *pdev)
return 0;
}
-static int artpec6_pmx_remove(struct platform_device *pdev)
+static void artpec6_pmx_remove(struct platform_device *pdev)
{
struct artpec6_pmx *pmx = platform_get_drvdata(pdev);
pinctrl_unregister(pmx->pctl);
-
- return 0;
}
static const struct of_device_id artpec6_pinctrl_match[] = {
@@ -990,7 +988,7 @@ static struct platform_driver artpec6_pmx_driver = {
.of_match_table = artpec6_pinctrl_match,
},
.probe = artpec6_pmx_probe,
- .remove = artpec6_pmx_remove,
+ .remove_new = artpec6_pmx_remove,
};
static int __init artpec6_pmx_init(void)
diff --git a/drivers/pinctrl/pinctrl-as3722.c b/drivers/pinctrl/pinctrl-as3722.c
index f0e5d87ac5..6a5f23cf7a 100644
--- a/drivers/pinctrl/pinctrl-as3722.c
+++ b/drivers/pinctrl/pinctrl-as3722.c
@@ -500,16 +500,11 @@ static void as3722_gpio_set(struct gpio_chip *chip, unsigned offset,
"GPIO_SIGNAL_OUT_REG update failed: %d\n", ret);
}
-static int as3722_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
-{
- return pinctrl_gpio_direction_input(chip->base + offset);
-}
-
static int as3722_gpio_direction_output(struct gpio_chip *chip,
unsigned offset, int value)
{
as3722_gpio_set(chip, offset, value);
- return pinctrl_gpio_direction_output(chip->base + offset);
+ return pinctrl_gpio_direction_output(chip, offset);
}
static int as3722_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
@@ -526,7 +521,7 @@ static const struct gpio_chip as3722_gpio_chip = {
.free = gpiochip_generic_free,
.get = as3722_gpio_get,
.set = as3722_gpio_set,
- .direction_input = as3722_gpio_direction_input,
+ .direction_input = pinctrl_gpio_direction_input,
.direction_output = as3722_gpio_direction_output,
.to_irq = as3722_gpio_to_irq,
.can_sleep = true,
@@ -587,12 +582,11 @@ fail_range_add:
return ret;
}
-static int as3722_pinctrl_remove(struct platform_device *pdev)
+static void as3722_pinctrl_remove(struct platform_device *pdev)
{
struct as3722_pctrl_info *as_pci = platform_get_drvdata(pdev);
gpiochip_remove(&as_pci->gpio_chip);
- return 0;
}
static const struct of_device_id as3722_pinctrl_of_match[] = {
@@ -607,7 +601,7 @@ static struct platform_driver as3722_pinctrl_driver = {
.of_match_table = as3722_pinctrl_of_match,
},
.probe = as3722_pinctrl_probe,
- .remove = as3722_pinctrl_remove,
+ .remove_new = as3722_pinctrl_remove,
};
module_platform_driver(as3722_pinctrl_driver);
diff --git a/drivers/pinctrl/pinctrl-at91.c b/drivers/pinctrl/pinctrl-at91.c
index 608f55c5ba..5aa9d5c533 100644
--- a/drivers/pinctrl/pinctrl-at91.c
+++ b/drivers/pinctrl/pinctrl-at91.c
@@ -12,10 +12,9 @@
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/of.h>
-#include <linux/of_address.h>
-#include <linux/of_device.h>
-#include <linux/of_irq.h>
+#include <linux/platform_device.h>
#include <linux/pm.h>
+#include <linux/property.h>
#include <linux/seq_file.h>
#include <linux/slab.h>
#include <linux/string_helpers.h>
@@ -1302,8 +1301,8 @@ static int at91_pinctrl_probe_dt(struct platform_device *pdev,
if (!np)
return -ENODEV;
- info->dev = dev;
- info->ops = of_device_get_match_data(dev);
+ info->dev = &pdev->dev;
+ info->ops = device_get_match_data(&pdev->dev);
at91_pinctrl_child_count(info, np);
/*
@@ -1845,7 +1844,7 @@ static int at91_gpio_probe(struct platform_device *pdev)
if (IS_ERR(at91_chip->regbase))
return PTR_ERR(at91_chip->regbase);
- at91_chip->ops = of_device_get_match_data(dev);
+ at91_chip->ops = device_get_match_data(dev);
at91_chip->pioc_virq = irq;
at91_chip->clock = devm_clk_get_enabled(dev, NULL);
diff --git a/drivers/pinctrl/pinctrl-axp209.c b/drivers/pinctrl/pinctrl-axp209.c
index 9f5b3ab8e1..2b4805e74e 100644
--- a/drivers/pinctrl/pinctrl-axp209.c
+++ b/drivers/pinctrl/pinctrl-axp209.c
@@ -124,11 +124,6 @@ static int axp20x_gpio_get_reg(unsigned int offset)
return -EINVAL;
}
-static int axp20x_gpio_input(struct gpio_chip *chip, unsigned int offset)
-{
- return pinctrl_gpio_direction_input(chip->base + offset);
-}
-
static int axp20x_gpio_get(struct gpio_chip *chip, unsigned int offset)
{
struct axp20x_pctl *pctl = gpiochip_get_data(chip);
@@ -474,7 +469,7 @@ static int axp20x_pctl_probe(struct platform_device *pdev)
pctl->chip.get = axp20x_gpio_get;
pctl->chip.get_direction = axp20x_gpio_get_direction;
pctl->chip.set = axp20x_gpio_set;
- pctl->chip.direction_input = axp20x_gpio_input;
+ pctl->chip.direction_input = pinctrl_gpio_direction_input;
pctl->chip.direction_output = axp20x_gpio_output;
pctl->desc = of_device_get_match_data(dev);
diff --git a/drivers/pinctrl/pinctrl-cy8c95x0.c b/drivers/pinctrl/pinctrl-cy8c95x0.c
index f2b9db66fd..fe9545c630 100644
--- a/drivers/pinctrl/pinctrl-cy8c95x0.c
+++ b/drivers/pinctrl/pinctrl-cy8c95x0.c
@@ -143,6 +143,7 @@ static const struct dmi_system_id cy8c95x0_dmi_acpi_irq_info[] = {
* @pinctrl_desc: pin controller description
* @name: Chip controller name
* @tpin: Total number of pins
+ * @gpio_reset: GPIO line handler that can reset the IC
*/
struct cy8c95x0_pinctrl {
struct regmap *regmap;
@@ -557,7 +558,7 @@ out:
static int cy8c95x0_gpio_direction_input(struct gpio_chip *gc, unsigned int off)
{
- return pinctrl_gpio_direction_input(gc->base + off);
+ return pinctrl_gpio_direction_input(gc, off);
}
static int cy8c95x0_gpio_direction_output(struct gpio_chip *gc,
@@ -574,7 +575,7 @@ static int cy8c95x0_gpio_direction_output(struct gpio_chip *gc,
if (ret)
return ret;
- return pinctrl_gpio_direction_output(gc->base + off);
+ return pinctrl_gpio_direction_output(gc, off);
}
static int cy8c95x0_gpio_get_value(struct gpio_chip *gc, unsigned int off)
@@ -1358,9 +1359,7 @@ static int cy8c95x0_probe(struct i2c_client *client)
chip->dev = &client->dev;
/* Set the device type */
- chip->driver_data = (unsigned long)device_get_match_data(&client->dev);
- if (!chip->driver_data)
- chip->driver_data = i2c_match_id(cy8c95x0_id, client)->driver_data;
+ chip->driver_data = (uintptr_t)i2c_get_match_data(client);
if (!chip->driver_data)
return -ENODEV;
diff --git a/drivers/pinctrl/pinctrl-da9062.c b/drivers/pinctrl/pinctrl-da9062.c
index 0e0ac3f3ff..3998b27cbe 100644
--- a/drivers/pinctrl/pinctrl-da9062.c
+++ b/drivers/pinctrl/pinctrl-da9062.c
@@ -17,17 +17,12 @@
#include <linux/property.h>
#include <linux/regmap.h>
+#include <linux/gpio/consumer.h>
#include <linux/gpio/driver.h>
#include <linux/mfd/da9062/core.h>
#include <linux/mfd/da9062/registers.h>
-/*
- * We need this get the gpio_desc from a <gpio_chip,offset> tuple to decide if
- * the gpio is active low without a vendor specific dt-binding.
- */
-#include "../gpio/gpiolib.h"
-
#define DA9062_TYPE(offset) (4 * (offset % 2))
#define DA9062_PIN_SHIFT(offset) (4 * (offset % 2))
#define DA9062_PIN_ALTERNATE 0x00 /* gpio alternate mode */
diff --git a/drivers/pinctrl/pinctrl-ingenic.c b/drivers/pinctrl/pinctrl-ingenic.c
index 2f220a47b7..ee718f6e25 100644
--- a/drivers/pinctrl/pinctrl-ingenic.c
+++ b/drivers/pinctrl/pinctrl-ingenic.c
@@ -133,6 +133,8 @@ struct ingenic_pinctrl {
struct pinctrl_pin_desc *pdesc;
const struct ingenic_chip_info *info;
+
+ struct gpio_chip *gc;
};
struct ingenic_gpio_chip {
@@ -3558,17 +3560,11 @@ static int ingenic_gpio_get(struct gpio_chip *gc, unsigned int offset)
return (int) ingenic_gpio_get_value(jzgc, offset);
}
-static int ingenic_gpio_direction_input(struct gpio_chip *gc,
- unsigned int offset)
-{
- return pinctrl_gpio_direction_input(gc->base + offset);
-}
-
static int ingenic_gpio_direction_output(struct gpio_chip *gc,
unsigned int offset, int value)
{
ingenic_gpio_set(gc, offset, value);
- return pinctrl_gpio_direction_output(gc->base + offset);
+ return pinctrl_gpio_direction_output(gc, offset);
}
static inline void ingenic_config_pin(struct ingenic_pinctrl *jzpc,
@@ -3678,7 +3674,7 @@ static int ingenic_gpio_irq_request(struct irq_data *data)
irq_hw_number_t irq = irqd_to_hwirq(data);
int ret;
- ret = ingenic_gpio_direction_input(gpio_chip, irq);
+ ret = pinctrl_gpio_direction_input(gpio_chip, irq);
if (ret)
return ret;
@@ -4052,7 +4048,8 @@ static int ingenic_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
break;
case PIN_CONFIG_OUTPUT:
- ret = pinctrl_gpio_direction_output(pin);
+ ret = pinctrl_gpio_direction_output(jzpc->gc,
+ pin - jzpc->gc->base);
if (ret)
return ret;
@@ -4172,6 +4169,8 @@ static int __init ingenic_gpio_probe(struct ingenic_pinctrl *jzpc,
if (!jzgc)
return -ENOMEM;
+ jzpc->gc = &jzgc->gc;
+
jzgc->jzpc = jzpc;
jzgc->reg_base = bank * jzpc->info->reg_offset;
@@ -4192,7 +4191,7 @@ static int __init ingenic_gpio_probe(struct ingenic_pinctrl *jzpc,
jzgc->gc.set = ingenic_gpio_set;
jzgc->gc.get = ingenic_gpio_get;
- jzgc->gc.direction_input = ingenic_gpio_direction_input;
+ jzgc->gc.direction_input = pinctrl_gpio_direction_input;
jzgc->gc.direction_output = ingenic_gpio_direction_output;
jzgc->gc.get_direction = ingenic_gpio_get_direction;
jzgc->gc.request = gpiochip_generic_request;
diff --git a/drivers/pinctrl/pinctrl-mcp23s08.h b/drivers/pinctrl/pinctrl-mcp23s08.h
index b15516af77..105bce9e0f 100644
--- a/drivers/pinctrl/pinctrl-mcp23s08.h
+++ b/drivers/pinctrl/pinctrl-mcp23s08.h
@@ -22,6 +22,14 @@ struct regmap;
struct pinctrl_dev;
+struct mcp23s08_info {
+ const struct regmap_config *regmap;
+ const char *label;
+ unsigned int type;
+ u16 ngpio;
+ bool reg_shift;
+};
+
struct mcp23s08 {
u8 addr;
bool irq_active_high;
diff --git a/drivers/pinctrl/pinctrl-mcp23s08_i2c.c b/drivers/pinctrl/pinctrl-mcp23s08_i2c.c
index 3dd1bd8e73..04e8e7d079 100644
--- a/drivers/pinctrl/pinctrl-mcp23s08_i2c.c
+++ b/drivers/pinctrl/pinctrl-mcp23s08_i2c.c
@@ -10,9 +10,8 @@
static int mcp230xx_probe(struct i2c_client *client)
{
- const struct i2c_device_id *id = i2c_client_get_device_id(client);
+ const struct mcp23s08_info *info;
struct device *dev = &client->dev;
- unsigned int type = id->driver_data;
struct mcp23s08 *mcp;
int ret;
@@ -20,40 +19,21 @@ static int mcp230xx_probe(struct i2c_client *client)
if (!mcp)
return -ENOMEM;
- switch (type) {
- case MCP_TYPE_008:
- mcp->regmap = devm_regmap_init_i2c(client, &mcp23x08_regmap);
- mcp->reg_shift = 0;
- mcp->chip.ngpio = 8;
- mcp->chip.label = "mcp23008";
- break;
-
- case MCP_TYPE_017:
- mcp->regmap = devm_regmap_init_i2c(client, &mcp23x17_regmap);
- mcp->reg_shift = 1;
- mcp->chip.ngpio = 16;
- mcp->chip.label = "mcp23017";
- break;
-
- case MCP_TYPE_018:
- mcp->regmap = devm_regmap_init_i2c(client, &mcp23x17_regmap);
- mcp->reg_shift = 1;
- mcp->chip.ngpio = 16;
- mcp->chip.label = "mcp23018";
- break;
-
- default:
- dev_err(dev, "invalid device type (%d)\n", type);
- return -EINVAL;
- }
+ info = i2c_get_match_data(client);
+ if (!info)
+ return dev_err_probe(dev, -EINVAL, "invalid device type\n");
+ mcp->reg_shift = info->reg_shift;
+ mcp->chip.ngpio = info->ngpio;
+ mcp->chip.label = info->label;
+ mcp->regmap = devm_regmap_init_i2c(client, info->regmap);
if (IS_ERR(mcp->regmap))
return PTR_ERR(mcp->regmap);
mcp->irq = client->irq;
mcp->pinctrl_desc.name = "mcp23xxx-pinctrl";
- ret = mcp23s08_probe_one(mcp, dev, client->addr, type, -1);
+ ret = mcp23s08_probe_one(mcp, dev, client->addr, info->type, -1);
if (ret)
return ret;
@@ -62,36 +42,45 @@ static int mcp230xx_probe(struct i2c_client *client)
return 0;
}
+static const struct mcp23s08_info mcp23008_i2c = {
+ .regmap = &mcp23x08_regmap,
+ .label = "mcp23008",
+ .type = MCP_TYPE_008,
+ .ngpio = 8,
+ .reg_shift = 0,
+};
+
+static const struct mcp23s08_info mcp23017_i2c = {
+ .regmap = &mcp23x17_regmap,
+ .label = "mcp23017",
+ .type = MCP_TYPE_017,
+ .ngpio = 16,
+ .reg_shift = 1,
+};
+
+static const struct mcp23s08_info mcp23018_i2c = {
+ .regmap = &mcp23x17_regmap,
+ .label = "mcp23018",
+ .type = MCP_TYPE_018,
+ .ngpio = 16,
+ .reg_shift = 1,
+};
+
static const struct i2c_device_id mcp230xx_id[] = {
- { "mcp23008", MCP_TYPE_008 },
- { "mcp23017", MCP_TYPE_017 },
- { "mcp23018", MCP_TYPE_018 },
+ { "mcp23008", (kernel_ulong_t)&mcp23008_i2c },
+ { "mcp23017", (kernel_ulong_t)&mcp23017_i2c },
+ { "mcp23018", (kernel_ulong_t)&mcp23018_i2c },
{ }
};
MODULE_DEVICE_TABLE(i2c, mcp230xx_id);
static const struct of_device_id mcp23s08_i2c_of_match[] = {
- {
- .compatible = "microchip,mcp23008",
- .data = (void *) MCP_TYPE_008,
- },
- {
- .compatible = "microchip,mcp23017",
- .data = (void *) MCP_TYPE_017,
- },
- {
- .compatible = "microchip,mcp23018",
- .data = (void *) MCP_TYPE_018,
- },
+ { .compatible = "microchip,mcp23008", .data = &mcp23008_i2c },
+ { .compatible = "microchip,mcp23017", .data = &mcp23017_i2c },
+ { .compatible = "microchip,mcp23018", .data = &mcp23018_i2c },
/* NOTE: The use of the mcp prefix is deprecated and will be removed. */
- {
- .compatible = "mcp,mcp23008",
- .data = (void *) MCP_TYPE_008,
- },
- {
- .compatible = "mcp,mcp23017",
- .data = (void *) MCP_TYPE_017,
- },
+ { .compatible = "mcp,mcp23008", .data = &mcp23008_i2c },
+ { .compatible = "mcp,mcp23017", .data = &mcp23017_i2c },
{ }
};
MODULE_DEVICE_TABLE(of, mcp23s08_i2c_of_match);
diff --git a/drivers/pinctrl/pinctrl-mcp23s08_spi.c b/drivers/pinctrl/pinctrl-mcp23s08_spi.c
index ea059b9c55..4a872fff5f 100644
--- a/drivers/pinctrl/pinctrl-mcp23s08_spi.c
+++ b/drivers/pinctrl/pinctrl-mcp23s08_spi.c
@@ -80,21 +80,18 @@ static const struct regmap_bus mcp23sxx_spi_regmap = {
};
static int mcp23s08_spi_regmap_init(struct mcp23s08 *mcp, struct device *dev,
- unsigned int addr, unsigned int type)
+ unsigned int addr,
+ const struct mcp23s08_info *info)
{
- const struct regmap_config *config;
struct regmap_config *copy;
const char *name;
- switch (type) {
+ switch (info->type) {
case MCP_TYPE_S08:
- mcp->reg_shift = 0;
- mcp->chip.ngpio = 8;
mcp->chip.label = devm_kasprintf(dev, GFP_KERNEL, "mcp23s08.%d", addr);
if (!mcp->chip.label)
return -ENOMEM;
- config = &mcp23x08_regmap;
name = devm_kasprintf(dev, GFP_KERNEL, "%d", addr);
if (!name)
return -ENOMEM;
@@ -102,13 +99,10 @@ static int mcp23s08_spi_regmap_init(struct mcp23s08 *mcp, struct device *dev,
break;
case MCP_TYPE_S17:
- mcp->reg_shift = 1;
- mcp->chip.ngpio = 16;
mcp->chip.label = devm_kasprintf(dev, GFP_KERNEL, "mcp23s17.%d", addr);
if (!mcp->chip.label)
return -ENOMEM;
- config = &mcp23x17_regmap;
name = devm_kasprintf(dev, GFP_KERNEL, "%d", addr);
if (!name)
return -ENOMEM;
@@ -116,20 +110,18 @@ static int mcp23s08_spi_regmap_init(struct mcp23s08 *mcp, struct device *dev,
break;
case MCP_TYPE_S18:
- mcp->reg_shift = 1;
- mcp->chip.ngpio = 16;
- mcp->chip.label = "mcp23s18";
-
- config = &mcp23x17_regmap;
- name = config->name;
+ mcp->chip.label = info->label;
+ name = info->regmap->name;
break;
default:
- dev_err(dev, "invalid device type (%d)\n", type);
+ dev_err(dev, "invalid device type (%d)\n", info->type);
return -EINVAL;
}
- copy = devm_kmemdup(dev, config, sizeof(*config), GFP_KERNEL);
+ mcp->reg_shift = info->reg_shift;
+ mcp->chip.ngpio = info->ngpio;
+ copy = devm_kmemdup(dev, info->regmap, sizeof(*info->regmap), GFP_KERNEL);
if (!copy)
return -ENOMEM;
@@ -143,22 +135,17 @@ static int mcp23s08_spi_regmap_init(struct mcp23s08 *mcp, struct device *dev,
static int mcp23s08_probe(struct spi_device *spi)
{
- struct device *dev = &spi->dev;
struct mcp23s08_driver_data *data;
+ const struct mcp23s08_info *info;
+ struct device *dev = &spi->dev;
unsigned long spi_present_mask;
- const void *match;
- unsigned int addr;
unsigned int ngpio = 0;
+ unsigned int addr;
int chips;
- int type;
int ret;
u32 v;
- match = device_get_match_data(dev);
- if (match)
- type = (int)(uintptr_t)match;
- else
- type = spi_get_device_id(spi)->driver_data;
+ info = spi_get_device_match_data(spi);
ret = device_property_read_u32(dev, "microchip,spi-present-mask", &v);
if (ret) {
@@ -187,7 +174,7 @@ static int mcp23s08_probe(struct spi_device *spi)
data->mcp[addr] = &data->chip[--chips];
data->mcp[addr]->irq = spi->irq;
- ret = mcp23s08_spi_regmap_init(data->mcp[addr], dev, addr, type);
+ ret = mcp23s08_spi_regmap_init(data->mcp[addr], dev, addr, info);
if (ret)
return ret;
@@ -197,7 +184,8 @@ static int mcp23s08_probe(struct spi_device *spi)
if (!data->mcp[addr]->pinctrl_desc.name)
return -ENOMEM;
- ret = mcp23s08_probe_one(data->mcp[addr], dev, 0x40 | (addr << 1), type, -1);
+ ret = mcp23s08_probe_one(data->mcp[addr], dev, 0x40 | (addr << 1),
+ info->type, -1);
if (ret < 0)
return ret;
@@ -208,36 +196,43 @@ static int mcp23s08_probe(struct spi_device *spi)
return 0;
}
+static const struct mcp23s08_info mcp23s08_spi = {
+ .regmap = &mcp23x08_regmap,
+ .type = MCP_TYPE_S08,
+ .ngpio = 8,
+ .reg_shift = 0,
+};
+
+static const struct mcp23s08_info mcp23s17_spi = {
+ .regmap = &mcp23x17_regmap,
+ .type = MCP_TYPE_S17,
+ .ngpio = 16,
+ .reg_shift = 1,
+};
+
+static const struct mcp23s08_info mcp23s18_spi = {
+ .regmap = &mcp23x17_regmap,
+ .label = "mcp23s18",
+ .type = MCP_TYPE_S18,
+ .ngpio = 16,
+ .reg_shift = 1,
+};
+
static const struct spi_device_id mcp23s08_ids[] = {
- { "mcp23s08", MCP_TYPE_S08 },
- { "mcp23s17", MCP_TYPE_S17 },
- { "mcp23s18", MCP_TYPE_S18 },
+ { "mcp23s08", (kernel_ulong_t)&mcp23s08_spi },
+ { "mcp23s17", (kernel_ulong_t)&mcp23s17_spi },
+ { "mcp23s18", (kernel_ulong_t)&mcp23s18_spi },
{ }
};
MODULE_DEVICE_TABLE(spi, mcp23s08_ids);
static const struct of_device_id mcp23s08_spi_of_match[] = {
- {
- .compatible = "microchip,mcp23s08",
- .data = (void *) MCP_TYPE_S08,
- },
- {
- .compatible = "microchip,mcp23s17",
- .data = (void *) MCP_TYPE_S17,
- },
- {
- .compatible = "microchip,mcp23s18",
- .data = (void *) MCP_TYPE_S18,
- },
+ { .compatible = "microchip,mcp23s08", .data = &mcp23s08_spi },
+ { .compatible = "microchip,mcp23s17", .data = &mcp23s17_spi },
+ { .compatible = "microchip,mcp23s18", .data = &mcp23s18_spi },
/* NOTE: The use of the mcp prefix is deprecated and will be removed. */
- {
- .compatible = "mcp,mcp23s08",
- .data = (void *) MCP_TYPE_S08,
- },
- {
- .compatible = "mcp,mcp23s17",
- .data = (void *) MCP_TYPE_S17,
- },
+ { .compatible = "mcp,mcp23s08", .data = &mcp23s08_spi },
+ { .compatible = "mcp,mcp23s17", .data = &mcp23s17_spi },
{ }
};
MODULE_DEVICE_TABLE(of, mcp23s08_spi_of_match);
diff --git a/drivers/pinctrl/pinctrl-ocelot.c b/drivers/pinctrl/pinctrl-ocelot.c
index f8ae2e9742..52aadd6d72 100644
--- a/drivers/pinctrl/pinctrl-ocelot.c
+++ b/drivers/pinctrl/pinctrl-ocelot.c
@@ -1776,12 +1776,6 @@ static int ocelot_gpio_get_direction(struct gpio_chip *chip,
return GPIO_LINE_DIRECTION_IN;
}
-static int ocelot_gpio_direction_input(struct gpio_chip *chip,
- unsigned int offset)
-{
- return pinctrl_gpio_direction_input(chip->base + offset);
-}
-
static int ocelot_gpio_direction_output(struct gpio_chip *chip,
unsigned int offset, int value)
{
@@ -1795,7 +1789,7 @@ static int ocelot_gpio_direction_output(struct gpio_chip *chip,
regmap_write(info->map, REG(OCELOT_GPIO_OUT_CLR, info, offset),
pin);
- return pinctrl_gpio_direction_output(chip->base + offset);
+ return pinctrl_gpio_direction_output(chip, offset);
}
static const struct gpio_chip ocelot_gpiolib_chip = {
@@ -1804,7 +1798,7 @@ static const struct gpio_chip ocelot_gpiolib_chip = {
.set = ocelot_gpio_set,
.get = ocelot_gpio_get,
.get_direction = ocelot_gpio_get_direction,
- .direction_input = ocelot_gpio_direction_input,
+ .direction_input = pinctrl_gpio_direction_input,
.direction_output = ocelot_gpio_direction_output,
.owner = THIS_MODULE,
};
diff --git a/drivers/pinctrl/pinctrl-rk805.c b/drivers/pinctrl/pinctrl-rk805.c
index 2639a9ee82..56d916f2ce 100644
--- a/drivers/pinctrl/pinctrl-rk805.c
+++ b/drivers/pinctrl/pinctrl-rk805.c
@@ -286,17 +286,11 @@ static void rk805_gpio_set(struct gpio_chip *chip,
offset, value);
}
-static int rk805_gpio_direction_input(struct gpio_chip *chip,
- unsigned int offset)
-{
- return pinctrl_gpio_direction_input(chip->base + offset);
-}
-
static int rk805_gpio_direction_output(struct gpio_chip *chip,
unsigned int offset, int value)
{
rk805_gpio_set(chip, offset, value);
- return pinctrl_gpio_direction_output(chip->base + offset);
+ return pinctrl_gpio_direction_output(chip, offset);
}
static int rk805_gpio_get_direction(struct gpio_chip *chip, unsigned int offset)
@@ -330,7 +324,7 @@ static const struct gpio_chip rk805_gpio_chip = {
.get_direction = rk805_gpio_get_direction,
.get = rk805_gpio_get,
.set = rk805_gpio_set,
- .direction_input = rk805_gpio_direction_input,
+ .direction_input = pinctrl_gpio_direction_input,
.direction_output = rk805_gpio_direction_output,
.can_sleep = true,
.base = -1,
diff --git a/drivers/pinctrl/pinctrl-rockchip.c b/drivers/pinctrl/pinctrl-rockchip.c
index 45e416f68e..3bedf36a00 100644
--- a/drivers/pinctrl/pinctrl-rockchip.c
+++ b/drivers/pinctrl/pinctrl-rockchip.c
@@ -3429,7 +3429,7 @@ static int rockchip_pinctrl_probe(struct platform_device *pdev)
return 0;
}
-static int rockchip_pinctrl_remove(struct platform_device *pdev)
+static void rockchip_pinctrl_remove(struct platform_device *pdev)
{
struct rockchip_pinctrl *info = platform_get_drvdata(pdev);
struct rockchip_pin_bank *bank;
@@ -3450,8 +3450,6 @@ static int rockchip_pinctrl_remove(struct platform_device *pdev)
}
mutex_unlock(&bank->deferred_lock);
}
-
- return 0;
}
static struct rockchip_pin_bank px30_pin_banks[] = {
@@ -3982,7 +3980,7 @@ static const struct of_device_id rockchip_pinctrl_dt_match[] = {
static struct platform_driver rockchip_pinctrl_driver = {
.probe = rockchip_pinctrl_probe,
- .remove = rockchip_pinctrl_remove,
+ .remove_new = rockchip_pinctrl_remove,
.driver = {
.name = "rockchip-pinctrl",
.pm = &rockchip_pinctrl_dev_pm_ops,
diff --git a/drivers/pinctrl/pinctrl-single.c b/drivers/pinctrl/pinctrl-single.c
index 461a7c02d4..8267be7696 100644
--- a/drivers/pinctrl/pinctrl-single.c
+++ b/drivers/pinctrl/pinctrl-single.c
@@ -239,32 +239,32 @@ static struct lock_class_key pcs_request_class;
* does not help in this case.
*/
-static unsigned __maybe_unused pcs_readb(void __iomem *reg)
+static unsigned int pcs_readb(void __iomem *reg)
{
return readb(reg);
}
-static unsigned __maybe_unused pcs_readw(void __iomem *reg)
+static unsigned int pcs_readw(void __iomem *reg)
{
return readw(reg);
}
-static unsigned __maybe_unused pcs_readl(void __iomem *reg)
+static unsigned int pcs_readl(void __iomem *reg)
{
return readl(reg);
}
-static void __maybe_unused pcs_writeb(unsigned val, void __iomem *reg)
+static void pcs_writeb(unsigned int val, void __iomem *reg)
{
writeb(val, reg);
}
-static void __maybe_unused pcs_writew(unsigned val, void __iomem *reg)
+static void pcs_writew(unsigned int val, void __iomem *reg)
{
writew(val, reg);
}
-static void __maybe_unused pcs_writel(unsigned val, void __iomem *reg)
+static void pcs_writel(unsigned int val, void __iomem *reg)
{
writel(val, reg);
}
@@ -1925,16 +1925,11 @@ free:
return ret;
}
-static int pcs_remove(struct platform_device *pdev)
+static void pcs_remove(struct platform_device *pdev)
{
struct pcs_device *pcs = platform_get_drvdata(pdev);
- if (!pcs)
- return 0;
-
pcs_free_resources(pcs);
-
- return 0;
}
static const struct pcs_soc_data pinctrl_single_omap_wkup = {
@@ -1982,7 +1977,7 @@ MODULE_DEVICE_TABLE(of, pcs_of_match);
static struct platform_driver pcs_driver = {
.probe = pcs_probe,
- .remove = pcs_remove,
+ .remove_new = pcs_remove,
.driver = {
.name = DRIVER_NAME,
.of_match_table = pcs_of_match,
diff --git a/drivers/pinctrl/pinctrl-st.c b/drivers/pinctrl/pinctrl-st.c
index c1f36b164e..1485573b52 100644
--- a/drivers/pinctrl/pinctrl-st.c
+++ b/drivers/pinctrl/pinctrl-st.c
@@ -717,20 +717,13 @@ static void st_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
__st_gpio_set(bank, offset, value);
}
-static int st_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
-{
- pinctrl_gpio_direction_input(chip->base + offset);
-
- return 0;
-}
-
static int st_gpio_direction_output(struct gpio_chip *chip,
unsigned offset, int value)
{
struct st_gpio_bank *bank = gpiochip_get_data(chip);
__st_gpio_set(bank, offset, value);
- pinctrl_gpio_direction_output(chip->base + offset);
+ pinctrl_gpio_direction_output(chip, offset);
return 0;
}
@@ -1330,7 +1323,7 @@ static int st_gpio_irq_request_resources(struct irq_data *d)
{
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
- st_gpio_direction_input(gc, d->hwirq);
+ pinctrl_gpio_direction_input(gc, d->hwirq);
return gpiochip_reqres_irq(gc, d->hwirq);
}
@@ -1488,7 +1481,7 @@ static const struct gpio_chip st_gpio_template = {
.free = gpiochip_generic_free,
.get = st_gpio_get,
.set = st_gpio_set,
- .direction_input = st_gpio_direction_input,
+ .direction_input = pinctrl_gpio_direction_input,
.direction_output = st_gpio_direction_output,
.get_direction = st_gpio_get_direction,
.ngpio = ST_GPIO_PINS_PER_BANK,
diff --git a/drivers/pinctrl/pinctrl-stmfx.c b/drivers/pinctrl/pinctrl-stmfx.c
index 0974bbf57b..6313be370e 100644
--- a/drivers/pinctrl/pinctrl-stmfx.c
+++ b/drivers/pinctrl/pinctrl-stmfx.c
@@ -734,14 +734,18 @@ static int stmfx_pinctrl_probe(struct platform_device *pdev)
return 0;
}
-static int stmfx_pinctrl_remove(struct platform_device *pdev)
+static void stmfx_pinctrl_remove(struct platform_device *pdev)
{
struct stmfx *stmfx = dev_get_drvdata(pdev->dev.parent);
+ int ret;
- return stmfx_function_disable(stmfx,
- STMFX_FUNC_GPIO |
- STMFX_FUNC_ALTGPIO_LOW |
- STMFX_FUNC_ALTGPIO_HIGH);
+ ret = stmfx_function_disable(stmfx,
+ STMFX_FUNC_GPIO |
+ STMFX_FUNC_ALTGPIO_LOW |
+ STMFX_FUNC_ALTGPIO_HIGH);
+ if (ret)
+ dev_err(&pdev->dev, "Failed to disable pins (%pe)\n",
+ ERR_PTR(ret));
}
#ifdef CONFIG_PM_SLEEP
@@ -850,7 +854,7 @@ static struct platform_driver stmfx_pinctrl_driver = {
.pm = &stmfx_pinctrl_dev_pm_ops,
},
.probe = stmfx_pinctrl_probe,
- .remove = stmfx_pinctrl_remove,
+ .remove_new = stmfx_pinctrl_remove,
};
module_platform_driver(stmfx_pinctrl_driver);
diff --git a/drivers/pinctrl/pinctrl-sx150x.c b/drivers/pinctrl/pinctrl-sx150x.c
index fef1ee7b79..fd0331a87c 100644
--- a/drivers/pinctrl/pinctrl-sx150x.c
+++ b/drivers/pinctrl/pinctrl-sx150x.c
@@ -1116,7 +1116,6 @@ static const struct regmap_config sx150x_regmap_config = {
static int sx150x_probe(struct i2c_client *client)
{
- const struct i2c_device_id *id = i2c_client_get_device_id(client);
static const u32 i2c_funcs = I2C_FUNC_SMBUS_BYTE_DATA |
I2C_FUNC_SMBUS_WRITE_WORD_DATA;
struct device *dev = &client->dev;
@@ -1135,11 +1134,7 @@ static int sx150x_probe(struct i2c_client *client)
pctl->dev = dev;
pctl->client = client;
- if (dev->of_node)
- pctl->data = of_device_get_match_data(dev);
- else
- pctl->data = (struct sx150x_device_data *)id->driver_data;
-
+ pctl->data = i2c_get_match_data(client);
if (!pctl->data)
return -EINVAL;
diff --git a/drivers/pinctrl/pinctrl-tb10x.c b/drivers/pinctrl/pinctrl-tb10x.c
index ab49bd7089..c3b76e6511 100644
--- a/drivers/pinctrl/pinctrl-tb10x.c
+++ b/drivers/pinctrl/pinctrl-tb10x.c
@@ -804,13 +804,11 @@ fail:
return ret;
}
-static int tb10x_pinctrl_remove(struct platform_device *pdev)
+static void tb10x_pinctrl_remove(struct platform_device *pdev)
{
struct tb10x_pinctrl *state = platform_get_drvdata(pdev);
mutex_destroy(&state->mutex);
-
- return 0;
}
@@ -822,7 +820,7 @@ MODULE_DEVICE_TABLE(of, tb10x_pinctrl_dt_ids);
static struct platform_driver tb10x_pinctrl_pdrv = {
.probe = tb10x_pinctrl_probe,
- .remove = tb10x_pinctrl_remove,
+ .remove_new = tb10x_pinctrl_remove,
.driver = {
.name = "tb10x_pinctrl",
.of_match_table = of_match_ptr(tb10x_pinctrl_dt_ids),
diff --git a/drivers/pinctrl/pinctrl-utils.c b/drivers/pinctrl/pinctrl-utils.c
index 3580e0fd94..40862f7bd6 100644
--- a/drivers/pinctrl/pinctrl-utils.c
+++ b/drivers/pinctrl/pinctrl-utils.c
@@ -6,12 +6,14 @@
*
* Author: Laxman Dewangan <ldewangan@nvidia.com>
*/
+#include <linux/array_size.h>
#include <linux/device.h>
#include <linux/export.h>
-#include <linux/kernel.h>
-#include <linux/pinctrl/pinctrl.h>
#include <linux/of.h>
#include <linux/slab.h>
+
+#include <linux/pinctrl/pinctrl.h>
+
#include "core.h"
#include "pinctrl-utils.h"
diff --git a/drivers/pinctrl/pinctrl-xway.c b/drivers/pinctrl/pinctrl-xway.c
index cf0383f575..f4256a9181 100644
--- a/drivers/pinctrl/pinctrl-xway.c
+++ b/drivers/pinctrl/pinctrl-xway.c
@@ -11,12 +11,12 @@
#include <linux/gpio/driver.h>
#include <linux/slab.h>
#include <linux/module.h>
-#include <linux/of_platform.h>
-#include <linux/of_address.h>
+#include <linux/of.h>
#include <linux/ioport.h>
#include <linux/io.h>
#include <linux/device.h>
#include <linux/platform_device.h>
+#include <linux/property.h>
#include "pinctrl-lantiq.h"
@@ -1451,7 +1451,6 @@ MODULE_DEVICE_TABLE(of, xway_match);
static int pinmux_xway_probe(struct platform_device *pdev)
{
- const struct of_device_id *match;
const struct pinctrl_xway_soc *xway_soc;
int ret, i;
@@ -1460,10 +1459,8 @@ static int pinmux_xway_probe(struct platform_device *pdev)
if (IS_ERR(xway_info.membase[0]))
return PTR_ERR(xway_info.membase[0]);
- match = of_match_device(xway_match, &pdev->dev);
- if (match)
- xway_soc = (const struct pinctrl_xway_soc *) match->data;
- else
+ xway_soc = device_get_match_data(&pdev->dev);
+ if (!xway_soc)
xway_soc = &danube_pinctrl;
/* find out how many pads we have */
diff --git a/drivers/pinctrl/pinmux.c b/drivers/pinctrl/pinmux.c
index 2a180a5d64..23d2da0b99 100644
--- a/drivers/pinctrl/pinmux.c
+++ b/drivers/pinctrl/pinmux.c
@@ -12,12 +12,12 @@
*/
#define pr_fmt(fmt) "pinmux core: " fmt
+#include <linux/array_size.h>
#include <linux/ctype.h>
#include <linux/debugfs.h>
#include <linux/device.h>
#include <linux/err.h>
#include <linux/init.h>
-#include <linux/kernel.h>
#include <linux/list.h>
#include <linux/module.h>
#include <linux/radix-tree.h>
@@ -173,10 +173,8 @@ static int pin_request(struct pinctrl_dev *pctldev,
else
status = 0;
- if (status) {
- dev_err(pctldev->dev, "request() failed for pin %d\n", pin);
+ if (status)
module_put(pctldev->owner);
- }
out_free_pin:
if (status) {
diff --git a/drivers/pinctrl/qcom/pinctrl-apq8064.c b/drivers/pinctrl/qcom/pinctrl-apq8064.c
index 20c3b90250..a18df41622 100644
--- a/drivers/pinctrl/qcom/pinctrl-apq8064.c
+++ b/drivers/pinctrl/qcom/pinctrl-apq8064.c
@@ -629,7 +629,7 @@ static struct platform_driver apq8064_pinctrl_driver = {
.of_match_table = apq8064_pinctrl_of_match,
},
.probe = apq8064_pinctrl_probe,
- .remove = msm_pinctrl_remove,
+ .remove_new = msm_pinctrl_remove,
};
static int __init apq8064_pinctrl_init(void)
diff --git a/drivers/pinctrl/qcom/pinctrl-apq8084.c b/drivers/pinctrl/qcom/pinctrl-apq8084.c
index 3fc0a40762..afada80e52 100644
--- a/drivers/pinctrl/qcom/pinctrl-apq8084.c
+++ b/drivers/pinctrl/qcom/pinctrl-apq8084.c
@@ -1207,7 +1207,7 @@ static struct platform_driver apq8084_pinctrl_driver = {
.of_match_table = apq8084_pinctrl_of_match,
},
.probe = apq8084_pinctrl_probe,
- .remove = msm_pinctrl_remove,
+ .remove_new = msm_pinctrl_remove,
};
static int __init apq8084_pinctrl_init(void)
diff --git a/drivers/pinctrl/qcom/pinctrl-ipq4019.c b/drivers/pinctrl/qcom/pinctrl-ipq4019.c
index 1f7944dd82..cb13576ad6 100644
--- a/drivers/pinctrl/qcom/pinctrl-ipq4019.c
+++ b/drivers/pinctrl/qcom/pinctrl-ipq4019.c
@@ -710,7 +710,7 @@ static struct platform_driver ipq4019_pinctrl_driver = {
.of_match_table = ipq4019_pinctrl_of_match,
},
.probe = ipq4019_pinctrl_probe,
- .remove = msm_pinctrl_remove,
+ .remove_new = msm_pinctrl_remove,
};
static int __init ipq4019_pinctrl_init(void)
diff --git a/drivers/pinctrl/qcom/pinctrl-ipq5018.c b/drivers/pinctrl/qcom/pinctrl-ipq5018.c
index e2951f81c3..68f65b5700 100644
--- a/drivers/pinctrl/qcom/pinctrl-ipq5018.c
+++ b/drivers/pinctrl/qcom/pinctrl-ipq5018.c
@@ -754,7 +754,7 @@ static struct platform_driver ipq5018_pinctrl_driver = {
.of_match_table = ipq5018_pinctrl_of_match,
},
.probe = ipq5018_pinctrl_probe,
- .remove = msm_pinctrl_remove,
+ .remove_new = msm_pinctrl_remove,
};
static int __init ipq5018_pinctrl_init(void)
diff --git a/drivers/pinctrl/qcom/pinctrl-ipq5332.c b/drivers/pinctrl/qcom/pinctrl-ipq5332.c
index 625f801405..8821751189 100644
--- a/drivers/pinctrl/qcom/pinctrl-ipq5332.c
+++ b/drivers/pinctrl/qcom/pinctrl-ipq5332.c
@@ -834,7 +834,7 @@ static struct platform_driver ipq5332_pinctrl_driver = {
.of_match_table = ipq5332_pinctrl_of_match,
},
.probe = ipq5332_pinctrl_probe,
- .remove = msm_pinctrl_remove,
+ .remove_new = msm_pinctrl_remove,
};
static int __init ipq5332_pinctrl_init(void)
diff --git a/drivers/pinctrl/qcom/pinctrl-ipq6018.c b/drivers/pinctrl/qcom/pinctrl-ipq6018.c
index 0ad08647db..ac330d8712 100644
--- a/drivers/pinctrl/qcom/pinctrl-ipq6018.c
+++ b/drivers/pinctrl/qcom/pinctrl-ipq6018.c
@@ -1080,7 +1080,7 @@ static struct platform_driver ipq6018_pinctrl_driver = {
.of_match_table = ipq6018_pinctrl_of_match,
},
.probe = ipq6018_pinctrl_probe,
- .remove = msm_pinctrl_remove,
+ .remove_new = msm_pinctrl_remove,
};
static int __init ipq6018_pinctrl_init(void)
diff --git a/drivers/pinctrl/qcom/pinctrl-ipq8064.c b/drivers/pinctrl/qcom/pinctrl-ipq8064.c
index e2bb94e86a..e10e1bc4c9 100644
--- a/drivers/pinctrl/qcom/pinctrl-ipq8064.c
+++ b/drivers/pinctrl/qcom/pinctrl-ipq8064.c
@@ -631,7 +631,7 @@ static struct platform_driver ipq8064_pinctrl_driver = {
.of_match_table = ipq8064_pinctrl_of_match,
},
.probe = ipq8064_pinctrl_probe,
- .remove = msm_pinctrl_remove,
+ .remove_new = msm_pinctrl_remove,
};
static int __init ipq8064_pinctrl_init(void)
diff --git a/drivers/pinctrl/qcom/pinctrl-ipq8074.c b/drivers/pinctrl/qcom/pinctrl-ipq8074.c
index 337f3a1c92..fee32c1d1d 100644
--- a/drivers/pinctrl/qcom/pinctrl-ipq8074.c
+++ b/drivers/pinctrl/qcom/pinctrl-ipq8074.c
@@ -1041,7 +1041,7 @@ static struct platform_driver ipq8074_pinctrl_driver = {
.of_match_table = ipq8074_pinctrl_of_match,
},
.probe = ipq8074_pinctrl_probe,
- .remove = msm_pinctrl_remove,
+ .remove_new = msm_pinctrl_remove,
};
static int __init ipq8074_pinctrl_init(void)
diff --git a/drivers/pinctrl/qcom/pinctrl-ipq9574.c b/drivers/pinctrl/qcom/pinctrl-ipq9574.c
index e2491617b2..20ab59cb62 100644
--- a/drivers/pinctrl/qcom/pinctrl-ipq9574.c
+++ b/drivers/pinctrl/qcom/pinctrl-ipq9574.c
@@ -799,7 +799,7 @@ static struct platform_driver ipq9574_pinctrl_driver = {
.of_match_table = ipq9574_pinctrl_of_match,
},
.probe = ipq9574_pinctrl_probe,
- .remove = msm_pinctrl_remove,
+ .remove_new = msm_pinctrl_remove,
};
static int __init ipq9574_pinctrl_init(void)
diff --git a/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c b/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c
index 0b2839d27f..9651aed048 100644
--- a/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c
+++ b/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c
@@ -495,7 +495,7 @@ err_pinctrl:
}
EXPORT_SYMBOL_GPL(lpi_pinctrl_probe);
-int lpi_pinctrl_remove(struct platform_device *pdev)
+void lpi_pinctrl_remove(struct platform_device *pdev)
{
struct lpi_pinctrl *pctrl = platform_get_drvdata(pdev);
int i;
@@ -505,8 +505,6 @@ int lpi_pinctrl_remove(struct platform_device *pdev)
for (i = 0; i < pctrl->data->npins; i++)
pinctrl_generic_remove_group(pctrl->ctrl, i);
-
- return 0;
}
EXPORT_SYMBOL_GPL(lpi_pinctrl_remove);
diff --git a/drivers/pinctrl/qcom/pinctrl-lpass-lpi.h b/drivers/pinctrl/qcom/pinctrl-lpass-lpi.h
index 29047bb80b..387d83ee95 100644
--- a/drivers/pinctrl/qcom/pinctrl-lpass-lpi.h
+++ b/drivers/pinctrl/qcom/pinctrl-lpass-lpi.h
@@ -85,6 +85,6 @@ struct lpi_pinctrl_variant_data {
};
int lpi_pinctrl_probe(struct platform_device *pdev);
-int lpi_pinctrl_remove(struct platform_device *pdev);
+void lpi_pinctrl_remove(struct platform_device *pdev);
#endif /*__PINCTRL_LPASS_LPI_H__*/
diff --git a/drivers/pinctrl/qcom/pinctrl-mdm9607.c b/drivers/pinctrl/qcom/pinctrl-mdm9607.c
index e7cd3ef1cf..415d24e162 100644
--- a/drivers/pinctrl/qcom/pinctrl-mdm9607.c
+++ b/drivers/pinctrl/qcom/pinctrl-mdm9607.c
@@ -1059,7 +1059,7 @@ static struct platform_driver mdm9607_pinctrl_driver = {
.of_match_table = mdm9607_pinctrl_of_match,
},
.probe = mdm9607_pinctrl_probe,
- .remove = msm_pinctrl_remove,
+ .remove_new = msm_pinctrl_remove,
};
static int __init mdm9607_pinctrl_init(void)
diff --git a/drivers/pinctrl/qcom/pinctrl-mdm9615.c b/drivers/pinctrl/qcom/pinctrl-mdm9615.c
index 0a2ae383d3..3f2eafea0b 100644
--- a/drivers/pinctrl/qcom/pinctrl-mdm9615.c
+++ b/drivers/pinctrl/qcom/pinctrl-mdm9615.c
@@ -446,7 +446,7 @@ static struct platform_driver mdm9615_pinctrl_driver = {
.of_match_table = mdm9615_pinctrl_of_match,
},
.probe = mdm9615_pinctrl_probe,
- .remove = msm_pinctrl_remove,
+ .remove_new = msm_pinctrl_remove,
};
static int __init mdm9615_pinctrl_init(void)
diff --git a/drivers/pinctrl/qcom/pinctrl-msm.c b/drivers/pinctrl/qcom/pinctrl-msm.c
index 115b83e2d8..395040346d 100644
--- a/drivers/pinctrl/qcom/pinctrl-msm.c
+++ b/drivers/pinctrl/qcom/pinctrl-msm.c
@@ -1547,15 +1547,13 @@ int msm_pinctrl_probe(struct platform_device *pdev,
}
EXPORT_SYMBOL(msm_pinctrl_probe);
-int msm_pinctrl_remove(struct platform_device *pdev)
+void msm_pinctrl_remove(struct platform_device *pdev)
{
struct msm_pinctrl *pctrl = platform_get_drvdata(pdev);
gpiochip_remove(&pctrl->chip);
unregister_restart_handler(&pctrl->restart_nb);
-
- return 0;
}
EXPORT_SYMBOL(msm_pinctrl_remove);
diff --git a/drivers/pinctrl/qcom/pinctrl-msm.h b/drivers/pinctrl/qcom/pinctrl-msm.h
index 1d2f2e904d..4968d08a38 100644
--- a/drivers/pinctrl/qcom/pinctrl-msm.h
+++ b/drivers/pinctrl/qcom/pinctrl-msm.h
@@ -166,6 +166,6 @@ extern const struct dev_pm_ops msm_pinctrl_dev_pm_ops;
int msm_pinctrl_probe(struct platform_device *pdev,
const struct msm_pinctrl_soc_data *soc_data);
-int msm_pinctrl_remove(struct platform_device *pdev);
+void msm_pinctrl_remove(struct platform_device *pdev);
#endif
diff --git a/drivers/pinctrl/qcom/pinctrl-msm8226.c b/drivers/pinctrl/qcom/pinctrl-msm8226.c
index 994619840a..40806c0650 100644
--- a/drivers/pinctrl/qcom/pinctrl-msm8226.c
+++ b/drivers/pinctrl/qcom/pinctrl-msm8226.c
@@ -336,6 +336,7 @@ enum msm8226_functions {
msm_mux_blsp_i2c3,
msm_mux_blsp_i2c4,
msm_mux_blsp_i2c5,
+ msm_mux_blsp_i2c6,
msm_mux_blsp_spi1,
msm_mux_blsp_spi2,
msm_mux_blsp_spi3,
@@ -436,6 +437,8 @@ static const char * const blsp_spi5_groups[] = {
"gpio16", "gpio17", "gpio18", "gpio19"
};
+static const char * const blsp_i2c6_groups[] = { "gpio22", "gpio23" };
+
static const char * const cci_i2c0_groups[] = { "gpio29", "gpio30" };
static const char * const cam_mclk0_groups[] = { "gpio26" };
@@ -459,6 +462,7 @@ static const struct pinfunction msm8226_functions[] = {
MSM_PIN_FUNCTION(blsp_i2c3),
MSM_PIN_FUNCTION(blsp_i2c4),
MSM_PIN_FUNCTION(blsp_i2c5),
+ MSM_PIN_FUNCTION(blsp_i2c6),
MSM_PIN_FUNCTION(blsp_spi1),
MSM_PIN_FUNCTION(blsp_spi2),
MSM_PIN_FUNCTION(blsp_spi3),
@@ -507,8 +511,8 @@ static const struct msm_pingroup msm8226_groups[] = {
PINGROUP(19, blsp_spi5, blsp_uart5, blsp_i2c5, NA, NA, NA, NA),
PINGROUP(20, NA, NA, NA, NA, NA, NA, NA),
PINGROUP(21, NA, NA, NA, NA, NA, NA, NA),
- PINGROUP(22, NA, NA, NA, NA, NA, NA, NA),
- PINGROUP(23, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(22, NA, NA, blsp_i2c6, NA, NA, NA, NA),
+ PINGROUP(23, NA, NA, blsp_i2c6, NA, NA, NA, NA),
PINGROUP(24, NA, NA, NA, NA, NA, NA, NA),
PINGROUP(25, NA, NA, NA, NA, NA, NA, NA),
PINGROUP(26, cam_mclk0, NA, NA, NA, NA, NA, NA),
@@ -612,6 +616,16 @@ static const struct msm_pingroup msm8226_groups[] = {
#define NUM_GPIO_PINGROUPS 117
+static const struct msm_gpio_wakeirq_map msm8226_mpm_map[] = {
+ { 1, 3 }, { 4, 4 }, { 5, 5 }, { 9, 6 }, { 13, 7 }, { 17, 8 },
+ { 21, 9 }, { 27, 10 }, { 29, 11 }, { 31, 12 }, { 33, 13 }, { 35, 14 },
+ { 37, 15 }, { 38, 16 }, { 39, 17 }, { 41, 18 }, { 46, 19 }, { 48, 20 },
+ { 49, 21 }, { 50, 22 }, { 51, 23 }, { 52, 24 }, { 54, 25 }, { 62, 26 },
+ { 63, 27 }, { 64, 28 }, { 65, 29 }, { 66, 30 }, { 67, 31 }, { 68, 32 },
+ { 69, 33 }, { 71, 34 }, { 72, 35 }, { 106, 36 }, { 107, 37 }, { 108, 38 },
+ { 109, 39 }, { 110, 40 }, { 111, 54 }, { 113, 55 }, { 115, 41 },
+};
+
static const struct msm_pinctrl_soc_data msm8226_pinctrl = {
.pins = msm8226_pins,
.npins = ARRAY_SIZE(msm8226_pins),
@@ -620,6 +634,8 @@ static const struct msm_pinctrl_soc_data msm8226_pinctrl = {
.groups = msm8226_groups,
.ngroups = ARRAY_SIZE(msm8226_groups),
.ngpios = NUM_GPIO_PINGROUPS,
+ .wakeirq_map = msm8226_mpm_map,
+ .nwakeirq_map = ARRAY_SIZE(msm8226_mpm_map),
};
static int msm8226_pinctrl_probe(struct platform_device *pdev)
@@ -638,7 +654,7 @@ static struct platform_driver msm8226_pinctrl_driver = {
.of_match_table = msm8226_pinctrl_of_match,
},
.probe = msm8226_pinctrl_probe,
- .remove = msm_pinctrl_remove,
+ .remove_new = msm_pinctrl_remove,
};
static int __init msm8226_pinctrl_init(void)
diff --git a/drivers/pinctrl/qcom/pinctrl-msm8660.c b/drivers/pinctrl/qcom/pinctrl-msm8660.c
index 999a5f867e..dba6d531b4 100644
--- a/drivers/pinctrl/qcom/pinctrl-msm8660.c
+++ b/drivers/pinctrl/qcom/pinctrl-msm8660.c
@@ -981,7 +981,7 @@ static struct platform_driver msm8660_pinctrl_driver = {
.of_match_table = msm8660_pinctrl_of_match,
},
.probe = msm8660_pinctrl_probe,
- .remove = msm_pinctrl_remove,
+ .remove_new = msm_pinctrl_remove,
};
static int __init msm8660_pinctrl_init(void)
diff --git a/drivers/pinctrl/qcom/pinctrl-msm8909.c b/drivers/pinctrl/qcom/pinctrl-msm8909.c
index 756856d20d..14b17ba9f9 100644
--- a/drivers/pinctrl/qcom/pinctrl-msm8909.c
+++ b/drivers/pinctrl/qcom/pinctrl-msm8909.c
@@ -929,7 +929,7 @@ static struct platform_driver msm8909_pinctrl_driver = {
.of_match_table = msm8909_pinctrl_of_match,
},
.probe = msm8909_pinctrl_probe,
- .remove = msm_pinctrl_remove,
+ .remove_new = msm_pinctrl_remove,
};
static int __init msm8909_pinctrl_init(void)
diff --git a/drivers/pinctrl/qcom/pinctrl-msm8916.c b/drivers/pinctrl/qcom/pinctrl-msm8916.c
index cea5c54f92..184dcf8422 100644
--- a/drivers/pinctrl/qcom/pinctrl-msm8916.c
+++ b/drivers/pinctrl/qcom/pinctrl-msm8916.c
@@ -969,7 +969,7 @@ static struct platform_driver msm8916_pinctrl_driver = {
.of_match_table = msm8916_pinctrl_of_match,
},
.probe = msm8916_pinctrl_probe,
- .remove = msm_pinctrl_remove,
+ .remove_new = msm_pinctrl_remove,
};
static int __init msm8916_pinctrl_init(void)
diff --git a/drivers/pinctrl/qcom/pinctrl-msm8953.c b/drivers/pinctrl/qcom/pinctrl-msm8953.c
index 998351bdfe..c2253821ae 100644
--- a/drivers/pinctrl/qcom/pinctrl-msm8953.c
+++ b/drivers/pinctrl/qcom/pinctrl-msm8953.c
@@ -1816,7 +1816,7 @@ static struct platform_driver msm8953_pinctrl_driver = {
.of_match_table = msm8953_pinctrl_of_match,
},
.probe = msm8953_pinctrl_probe,
- .remove = msm_pinctrl_remove,
+ .remove_new = msm_pinctrl_remove,
};
static int __init msm8953_pinctrl_init(void)
diff --git a/drivers/pinctrl/qcom/pinctrl-msm8960.c b/drivers/pinctrl/qcom/pinctrl-msm8960.c
index ebe230b3b4..6b9148d226 100644
--- a/drivers/pinctrl/qcom/pinctrl-msm8960.c
+++ b/drivers/pinctrl/qcom/pinctrl-msm8960.c
@@ -1246,7 +1246,7 @@ static struct platform_driver msm8960_pinctrl_driver = {
.of_match_table = msm8960_pinctrl_of_match,
},
.probe = msm8960_pinctrl_probe,
- .remove = msm_pinctrl_remove,
+ .remove_new = msm_pinctrl_remove,
};
static int __init msm8960_pinctrl_init(void)
diff --git a/drivers/pinctrl/qcom/pinctrl-msm8976.c b/drivers/pinctrl/qcom/pinctrl-msm8976.c
index c30d80e4e9..9a951888e8 100644
--- a/drivers/pinctrl/qcom/pinctrl-msm8976.c
+++ b/drivers/pinctrl/qcom/pinctrl-msm8976.c
@@ -1096,7 +1096,7 @@ static struct platform_driver msm8976_pinctrl_driver = {
.of_match_table = msm8976_pinctrl_of_match,
},
.probe = msm8976_pinctrl_probe,
- .remove = msm_pinctrl_remove,
+ .remove_new = msm_pinctrl_remove,
};
static int __init msm8976_pinctrl_init(void)
diff --git a/drivers/pinctrl/qcom/pinctrl-msm8994.c b/drivers/pinctrl/qcom/pinctrl-msm8994.c
index b1a6759ab4..1ed1dd32d6 100644
--- a/drivers/pinctrl/qcom/pinctrl-msm8994.c
+++ b/drivers/pinctrl/qcom/pinctrl-msm8994.c
@@ -1343,7 +1343,7 @@ static struct platform_driver msm8994_pinctrl_driver = {
.of_match_table = msm8994_pinctrl_of_match,
},
.probe = msm8994_pinctrl_probe,
- .remove = msm_pinctrl_remove,
+ .remove_new = msm_pinctrl_remove,
};
static int __init msm8994_pinctrl_init(void)
diff --git a/drivers/pinctrl/qcom/pinctrl-msm8996.c b/drivers/pinctrl/qcom/pinctrl-msm8996.c
index 46cc0b49db..777c2a7403 100644
--- a/drivers/pinctrl/qcom/pinctrl-msm8996.c
+++ b/drivers/pinctrl/qcom/pinctrl-msm8996.c
@@ -1880,6 +1880,18 @@ static const struct msm_pingroup msm8996_groups[] = {
SDC_QDSD_PINGROUP(sdc1_rclk, 0x12c000, 15, 0),
};
+static const struct msm_gpio_wakeirq_map msm8996_mpm_map[] = {
+ { 1, 3 }, { 5, 4 }, { 9, 5 }, { 11, 6 }, { 66, 7 }, { 22, 8 }, { 24, 9 }, { 26, 10 },
+ { 34, 11 }, { 36, 12 }, { 37, 13 }, { 38, 14 }, { 40, 15 }, { 42, 16 }, { 46, 17 },
+ { 50, 18 }, { 53, 19 }, { 54, 20 }, { 56, 21 }, { 57, 22 }, { 58, 23 }, { 59, 24 },
+ { 60, 25 }, { 61, 26 }, { 62, 27 }, { 63, 28 }, { 64, 29 }, { 71, 30 }, { 73, 31 },
+ { 77, 32 }, { 78, 33 }, { 79, 34 }, { 80, 35 }, { 82, 36 }, { 86, 37 }, { 91, 38 },
+ { 92, 39 }, { 95, 40 }, { 97, 41 }, { 101, 42 }, { 104, 43 }, { 106, 44 }, { 108, 45 },
+ { 112, 46 }, { 113, 47 }, { 110, 48 }, { 127, 50 }, { 115, 51 }, { 116, 54 }, { 117, 55 },
+ { 118, 56 }, { 119, 57 }, { 120, 58 }, { 121, 59 }, { 122, 60 }, { 123, 61 }, { 124, 62 },
+ { 125, 63 }, { 126, 64 }, { 129, 65 }, { 131, 66 }, { 132, 67 }, { 133, 68 }, { 145, 69 },
+};
+
static const struct msm_pinctrl_soc_data msm8996_pinctrl = {
.pins = msm8996_pins,
.npins = ARRAY_SIZE(msm8996_pins),
@@ -1888,6 +1900,8 @@ static const struct msm_pinctrl_soc_data msm8996_pinctrl = {
.groups = msm8996_groups,
.ngroups = ARRAY_SIZE(msm8996_groups),
.ngpios = 150,
+ .wakeirq_map = msm8996_mpm_map,
+ .nwakeirq_map = ARRAY_SIZE(msm8996_mpm_map),
};
static int msm8996_pinctrl_probe(struct platform_device *pdev)
@@ -1906,7 +1920,7 @@ static struct platform_driver msm8996_pinctrl_driver = {
.of_match_table = msm8996_pinctrl_of_match,
},
.probe = msm8996_pinctrl_probe,
- .remove = msm_pinctrl_remove,
+ .remove_new = msm_pinctrl_remove,
};
static int __init msm8996_pinctrl_init(void)
diff --git a/drivers/pinctrl/qcom/pinctrl-msm8998.c b/drivers/pinctrl/qcom/pinctrl-msm8998.c
index b7cbf32b31..4aaf45e54f 100644
--- a/drivers/pinctrl/qcom/pinctrl-msm8998.c
+++ b/drivers/pinctrl/qcom/pinctrl-msm8998.c
@@ -1535,7 +1535,7 @@ static struct platform_driver msm8998_pinctrl_driver = {
.of_match_table = msm8998_pinctrl_of_match,
},
.probe = msm8998_pinctrl_probe,
- .remove = msm_pinctrl_remove,
+ .remove_new = msm_pinctrl_remove,
};
static int __init msm8998_pinctrl_init(void)
diff --git a/drivers/pinctrl/qcom/pinctrl-msm8x74.c b/drivers/pinctrl/qcom/pinctrl-msm8x74.c
index d5fe629928..750a8272de 100644
--- a/drivers/pinctrl/qcom/pinctrl-msm8x74.c
+++ b/drivers/pinctrl/qcom/pinctrl-msm8x74.c
@@ -1045,6 +1045,16 @@ static const struct msm_pingroup msm8x74_groups[] = {
#define NUM_GPIO_PINGROUPS 146
+static const struct msm_gpio_wakeirq_map msm8x74_mpm_map[] = {
+ { 1, 4 }, { 5, 5 }, { 9, 6 }, { 18, 7 }, { 20, 8 }, { 24, 9 },
+ { 27, 10 }, { 28, 11 }, { 34, 12 }, { 35, 13 }, { 37, 14 }, { 42, 15 },
+ { 44, 16 }, { 46, 17 }, { 50, 18 }, { 54, 19 }, { 59, 20 }, { 61, 21 },
+ { 62, 22 }, { 64, 23 }, { 65, 24 }, { 66, 25 }, { 67, 26 }, { 68, 27 },
+ { 71, 28 }, { 72, 29 }, { 73, 30 }, { 74, 31 }, { 75, 32 }, { 77, 33 },
+ { 79, 34 }, { 80, 35 }, { 82, 36 }, { 86, 37 }, { 92, 38 }, { 93, 39 },
+ { 95, 40 }, { 102, 3 }, { 144, 41 },
+};
+
static const struct msm_pinctrl_soc_data msm8x74_pinctrl = {
.pins = msm8x74_pins,
.npins = ARRAY_SIZE(msm8x74_pins),
@@ -1053,6 +1063,8 @@ static const struct msm_pinctrl_soc_data msm8x74_pinctrl = {
.groups = msm8x74_groups,
.ngroups = ARRAY_SIZE(msm8x74_groups),
.ngpios = NUM_GPIO_PINGROUPS,
+ .wakeirq_map = msm8x74_mpm_map,
+ .nwakeirq_map = ARRAY_SIZE(msm8x74_mpm_map),
};
static int msm8x74_pinctrl_probe(struct platform_device *pdev)
@@ -1071,7 +1083,7 @@ static struct platform_driver msm8x74_pinctrl_driver = {
.of_match_table = msm8x74_pinctrl_of_match,
},
.probe = msm8x74_pinctrl_probe,
- .remove = msm_pinctrl_remove,
+ .remove_new = msm_pinctrl_remove,
};
static int __init msm8x74_pinctrl_init(void)
diff --git a/drivers/pinctrl/qcom/pinctrl-qcm2290.c b/drivers/pinctrl/qcom/pinctrl-qcm2290.c
index ba699eac9e..f5c1c427b4 100644
--- a/drivers/pinctrl/qcom/pinctrl-qcm2290.c
+++ b/drivers/pinctrl/qcom/pinctrl-qcm2290.c
@@ -1113,7 +1113,7 @@ static struct platform_driver qcm2290_pinctrl_driver = {
.of_match_table = qcm2290_pinctrl_of_match,
},
.probe = qcm2290_pinctrl_probe,
- .remove = msm_pinctrl_remove,
+ .remove_new = msm_pinctrl_remove,
};
static int __init qcm2290_pinctrl_init(void)
diff --git a/drivers/pinctrl/qcom/pinctrl-qcs404.c b/drivers/pinctrl/qcom/pinctrl-qcs404.c
index ae7224012f..9a875b7dc9 100644
--- a/drivers/pinctrl/qcom/pinctrl-qcs404.c
+++ b/drivers/pinctrl/qcom/pinctrl-qcs404.c
@@ -1644,7 +1644,7 @@ static struct platform_driver qcs404_pinctrl_driver = {
.of_match_table = qcs404_pinctrl_of_match,
},
.probe = qcs404_pinctrl_probe,
- .remove = msm_pinctrl_remove,
+ .remove_new = msm_pinctrl_remove,
};
static int __init qcs404_pinctrl_init(void)
diff --git a/drivers/pinctrl/qcom/pinctrl-qdf2xxx.c b/drivers/pinctrl/qcom/pinctrl-qdf2xxx.c
index b5808fcfb1..4d2f6f4951 100644
--- a/drivers/pinctrl/qcom/pinctrl-qdf2xxx.c
+++ b/drivers/pinctrl/qcom/pinctrl-qdf2xxx.c
@@ -145,7 +145,7 @@ static struct platform_driver qdf2xxx_pinctrl_driver = {
.acpi_match_table = qdf2xxx_acpi_ids,
},
.probe = qdf2xxx_pinctrl_probe,
- .remove = msm_pinctrl_remove,
+ .remove_new = msm_pinctrl_remove,
};
static int __init qdf2xxx_pinctrl_init(void)
diff --git a/drivers/pinctrl/qcom/pinctrl-qdu1000.c b/drivers/pinctrl/qcom/pinctrl-qdu1000.c
index 47bc529ef5..da4f940bc8 100644
--- a/drivers/pinctrl/qcom/pinctrl-qdu1000.c
+++ b/drivers/pinctrl/qcom/pinctrl-qdu1000.c
@@ -1248,7 +1248,7 @@ static struct platform_driver qdu1000_tlmm_driver = {
.of_match_table = qdu1000_tlmm_of_match,
},
.probe = qdu1000_tlmm_probe,
- .remove = msm_pinctrl_remove,
+ .remove_new = msm_pinctrl_remove,
};
static int __init qdu1000_tlmm_init(void)
diff --git a/drivers/pinctrl/qcom/pinctrl-sa8775p.c b/drivers/pinctrl/qcom/pinctrl-sa8775p.c
index 8fdea25d8d..5459c0c681 100644
--- a/drivers/pinctrl/qcom/pinctrl-sa8775p.c
+++ b/drivers/pinctrl/qcom/pinctrl-sa8775p.c
@@ -1530,7 +1530,7 @@ static struct platform_driver sa8775p_pinctrl_driver = {
.of_match_table = sa8775p_pinctrl_of_match,
},
.probe = sa8775p_pinctrl_probe,
- .remove = msm_pinctrl_remove,
+ .remove_new = msm_pinctrl_remove,
};
static int __init sa8775p_pinctrl_init(void)
diff --git a/drivers/pinctrl/qcom/pinctrl-sc7180.c b/drivers/pinctrl/qcom/pinctrl-sc7180.c
index 6eb0c73791..c27aaa599b 100644
--- a/drivers/pinctrl/qcom/pinctrl-sc7180.c
+++ b/drivers/pinctrl/qcom/pinctrl-sc7180.c
@@ -1159,7 +1159,7 @@ static struct platform_driver sc7180_pinctrl_driver = {
.of_match_table = sc7180_pinctrl_of_match,
},
.probe = sc7180_pinctrl_probe,
- .remove = msm_pinctrl_remove,
+ .remove_new = msm_pinctrl_remove,
};
static int __init sc7180_pinctrl_init(void)
diff --git a/drivers/pinctrl/qcom/pinctrl-sc7280-lpass-lpi.c b/drivers/pinctrl/qcom/pinctrl-sc7280-lpass-lpi.c
index d615b6c55b..99156217c6 100644
--- a/drivers/pinctrl/qcom/pinctrl-sc7280-lpass-lpi.c
+++ b/drivers/pinctrl/qcom/pinctrl-sc7280-lpass-lpi.c
@@ -158,7 +158,7 @@ static struct platform_driver lpi_pinctrl_driver = {
.of_match_table = lpi_pinctrl_of_match,
},
.probe = lpi_pinctrl_probe,
- .remove = lpi_pinctrl_remove,
+ .remove_new = lpi_pinctrl_remove,
};
module_platform_driver(lpi_pinctrl_driver);
diff --git a/drivers/pinctrl/qcom/pinctrl-sc7280.c b/drivers/pinctrl/qcom/pinctrl-sc7280.c
index 0c10eeb60b..c2db663e39 100644
--- a/drivers/pinctrl/qcom/pinctrl-sc7280.c
+++ b/drivers/pinctrl/qcom/pinctrl-sc7280.c
@@ -1505,7 +1505,7 @@ static struct platform_driver sc7280_pinctrl_driver = {
.of_match_table = sc7280_pinctrl_of_match,
},
.probe = sc7280_pinctrl_probe,
- .remove = msm_pinctrl_remove,
+ .remove_new = msm_pinctrl_remove,
};
static int __init sc7280_pinctrl_init(void)
diff --git a/drivers/pinctrl/qcom/pinctrl-sc8180x.c b/drivers/pinctrl/qcom/pinctrl-sc8180x.c
index d6a79ad41a..cfa7c8be97 100644
--- a/drivers/pinctrl/qcom/pinctrl-sc8180x.c
+++ b/drivers/pinctrl/qcom/pinctrl-sc8180x.c
@@ -1720,7 +1720,7 @@ static struct platform_driver sc8180x_pinctrl_driver = {
.acpi_match_table = sc8180x_pinctrl_acpi_match,
},
.probe = sc8180x_pinctrl_probe,
- .remove = msm_pinctrl_remove,
+ .remove_new = msm_pinctrl_remove,
};
static int __init sc8180x_pinctrl_init(void)
diff --git a/drivers/pinctrl/qcom/pinctrl-sc8280xp-lpass-lpi.c b/drivers/pinctrl/qcom/pinctrl-sc8280xp-lpass-lpi.c
index 4b9c0beac3..b33483056f 100644
--- a/drivers/pinctrl/qcom/pinctrl-sc8280xp-lpass-lpi.c
+++ b/drivers/pinctrl/qcom/pinctrl-sc8280xp-lpass-lpi.c
@@ -199,7 +199,7 @@ static struct platform_driver lpi_pinctrl_driver = {
.of_match_table = lpi_pinctrl_of_match,
},
.probe = lpi_pinctrl_probe,
- .remove = lpi_pinctrl_remove,
+ .remove_new = lpi_pinctrl_remove,
};
module_platform_driver(lpi_pinctrl_driver);
diff --git a/drivers/pinctrl/qcom/pinctrl-sc8280xp.c b/drivers/pinctrl/qcom/pinctrl-sc8280xp.c
index 96f4fb5a5d..4b1c496976 100644
--- a/drivers/pinctrl/qcom/pinctrl-sc8280xp.c
+++ b/drivers/pinctrl/qcom/pinctrl-sc8280xp.c
@@ -1926,7 +1926,7 @@ static struct platform_driver sc8280xp_pinctrl_driver = {
.of_match_table = sc8280xp_pinctrl_of_match,
},
.probe = sc8280xp_pinctrl_probe,
- .remove = msm_pinctrl_remove,
+ .remove_new = msm_pinctrl_remove,
};
static int __init sc8280xp_pinctrl_init(void)
diff --git a/drivers/pinctrl/qcom/pinctrl-sdm660.c b/drivers/pinctrl/qcom/pinctrl-sdm660.c
index c2e0d5c034..b93837c009 100644
--- a/drivers/pinctrl/qcom/pinctrl-sdm660.c
+++ b/drivers/pinctrl/qcom/pinctrl-sdm660.c
@@ -1399,6 +1399,18 @@ static const struct msm_pingroup sdm660_groups[] = {
SDC_QDSD_PINGROUP(sdc1_rclk, 0x9a000, 15, 0),
};
+static const struct msm_gpio_wakeirq_map sdm660_mpm_map[] = {
+ { 1, 3 }, { 5, 4 }, { 9, 5 }, { 10, 6 }, { 66, 7 }, { 22, 8 }, { 25, 9 }, { 28, 10 },
+ { 58, 11 }, { 41, 13 }, { 43, 14 }, { 40, 15 }, { 42, 16 }, { 46, 17 }, { 50, 18 },
+ { 44, 19 }, { 56, 21 }, { 45, 22 }, { 68, 23 }, { 69, 24 }, { 70, 25 }, { 71, 26 },
+ { 72, 27 }, { 73, 28 }, { 64, 29 }, { 2, 30 }, { 13, 31 }, { 111, 32 }, { 74, 33 },
+ { 75, 34 }, { 76, 35 }, { 82, 36 }, { 17, 37 }, { 77, 38 }, { 47, 39 }, { 54, 40 },
+ { 48, 41 }, { 101, 42 }, { 49, 43 }, { 51, 44 }, { 86, 45 }, { 90, 46 }, { 91, 47 },
+ { 52, 48 }, { 55, 50 }, { 6, 51 }, { 65, 53 }, { 67, 55 }, { 83, 56 }, { 84, 57 },
+ { 85, 58 }, { 87, 59 }, { 21, 63 }, { 78, 64 }, { 113, 65 }, { 60, 66 }, { 98, 67 },
+ { 30, 68 }, { 31, 70 }, { 29, 71 }, { 107, 76 }, { 109, 83 }, { 103, 84 }, { 105, 85 },
+};
+
static const struct msm_pinctrl_soc_data sdm660_pinctrl = {
.pins = sdm660_pins,
.npins = ARRAY_SIZE(sdm660_pins),
@@ -1409,6 +1421,8 @@ static const struct msm_pinctrl_soc_data sdm660_pinctrl = {
.ngpios = 114,
.tiles = sdm660_tiles,
.ntiles = ARRAY_SIZE(sdm660_tiles),
+ .wakeirq_map = sdm660_mpm_map,
+ .nwakeirq_map = ARRAY_SIZE(sdm660_mpm_map),
};
static int sdm660_pinctrl_probe(struct platform_device *pdev)
@@ -1428,7 +1442,7 @@ static struct platform_driver sdm660_pinctrl_driver = {
.of_match_table = sdm660_pinctrl_of_match,
},
.probe = sdm660_pinctrl_probe,
- .remove = msm_pinctrl_remove,
+ .remove_new = msm_pinctrl_remove,
};
static int __init sdm660_pinctrl_init(void)
diff --git a/drivers/pinctrl/qcom/pinctrl-sdm670.c b/drivers/pinctrl/qcom/pinctrl-sdm670.c
index cc3cce077d..1e694a9669 100644
--- a/drivers/pinctrl/qcom/pinctrl-sdm670.c
+++ b/drivers/pinctrl/qcom/pinctrl-sdm670.c
@@ -1318,7 +1318,7 @@ static struct platform_driver sdm670_pinctrl_driver = {
.of_match_table = sdm670_pinctrl_of_match,
},
.probe = sdm670_pinctrl_probe,
- .remove = msm_pinctrl_remove,
+ .remove_new = msm_pinctrl_remove,
};
static int __init sdm670_pinctrl_init(void)
diff --git a/drivers/pinctrl/qcom/pinctrl-sdm845.c b/drivers/pinctrl/qcom/pinctrl-sdm845.c
index cc05c415ed..3f3265e001 100644
--- a/drivers/pinctrl/qcom/pinctrl-sdm845.c
+++ b/drivers/pinctrl/qcom/pinctrl-sdm845.c
@@ -1351,7 +1351,7 @@ static struct platform_driver sdm845_pinctrl_driver = {
.acpi_match_table = ACPI_PTR(sdm845_pinctrl_acpi_match),
},
.probe = sdm845_pinctrl_probe,
- .remove = msm_pinctrl_remove,
+ .remove_new = msm_pinctrl_remove,
};
static int __init sdm845_pinctrl_init(void)
diff --git a/drivers/pinctrl/qcom/pinctrl-sdx55.c b/drivers/pinctrl/qcom/pinctrl-sdx55.c
index 8826db9d21..c88b8bfcac 100644
--- a/drivers/pinctrl/qcom/pinctrl-sdx55.c
+++ b/drivers/pinctrl/qcom/pinctrl-sdx55.c
@@ -990,7 +990,7 @@ static struct platform_driver sdx55_pinctrl_driver = {
.of_match_table = sdx55_pinctrl_of_match,
},
.probe = sdx55_pinctrl_probe,
- .remove = msm_pinctrl_remove,
+ .remove_new = msm_pinctrl_remove,
};
static int __init sdx55_pinctrl_init(void)
diff --git a/drivers/pinctrl/qcom/pinctrl-sdx65.c b/drivers/pinctrl/qcom/pinctrl-sdx65.c
index f6f319c997..bd44ec0fca 100644
--- a/drivers/pinctrl/qcom/pinctrl-sdx65.c
+++ b/drivers/pinctrl/qcom/pinctrl-sdx65.c
@@ -939,7 +939,7 @@ static struct platform_driver sdx65_pinctrl_driver = {
.of_match_table = sdx65_pinctrl_of_match,
},
.probe = sdx65_pinctrl_probe,
- .remove = msm_pinctrl_remove,
+ .remove_new = msm_pinctrl_remove,
};
static int __init sdx65_pinctrl_init(void)
diff --git a/drivers/pinctrl/qcom/pinctrl-sdx75.c b/drivers/pinctrl/qcom/pinctrl-sdx75.c
index 3cfe8c7f04..396f6fc779 100644
--- a/drivers/pinctrl/qcom/pinctrl-sdx75.c
+++ b/drivers/pinctrl/qcom/pinctrl-sdx75.c
@@ -1124,7 +1124,7 @@ static struct platform_driver sdx75_pinctrl_driver = {
.of_match_table = sdx75_pinctrl_of_match,
},
.probe = sdx75_pinctrl_probe,
- .remove = msm_pinctrl_remove,
+ .remove_new = msm_pinctrl_remove,
};
static int __init sdx75_pinctrl_init(void)
diff --git a/drivers/pinctrl/qcom/pinctrl-sm6115-lpass-lpi.c b/drivers/pinctrl/qcom/pinctrl-sm6115-lpass-lpi.c
index 2b09bf171a..e8a6f6f6af 100644
--- a/drivers/pinctrl/qcom/pinctrl-sm6115-lpass-lpi.c
+++ b/drivers/pinctrl/qcom/pinctrl-sm6115-lpass-lpi.c
@@ -167,7 +167,7 @@ static struct platform_driver lpi_pinctrl_driver = {
.of_match_table = lpi_pinctrl_of_match,
},
.probe = lpi_pinctrl_probe,
- .remove = lpi_pinctrl_remove,
+ .remove_new = lpi_pinctrl_remove,
};
module_platform_driver(lpi_pinctrl_driver);
diff --git a/drivers/pinctrl/qcom/pinctrl-sm6115.c b/drivers/pinctrl/qcom/pinctrl-sm6115.c
index 2a06025f48..7ce04144b6 100644
--- a/drivers/pinctrl/qcom/pinctrl-sm6115.c
+++ b/drivers/pinctrl/qcom/pinctrl-sm6115.c
@@ -867,6 +867,16 @@ static const struct msm_pingroup sm6115_groups[] = {
[120] = SDC_QDSD_PINGROUP(sdc2_data, SOUTH, 0x73000, 9, 0),
};
+static const struct msm_gpio_wakeirq_map sm6115_mpm_map[] = {
+ { 0, 84 }, { 3, 75 }, { 4, 16 }, { 6, 59 }, { 8, 63 }, { 11, 17 }, { 13, 18 },
+ { 14, 51 }, { 17, 20 }, { 18, 52 }, { 19, 53 }, { 24, 6 }, { 25, 71 }, { 27, 73 },
+ { 28, 41 }, { 31, 27 }, { 32, 54 }, { 33, 55 }, { 34, 56 }, { 35, 57 }, { 36, 58 },
+ { 39, 28 }, { 46, 29 }, { 62, 60 }, { 63, 61 }, { 64, 62 }, { 65, 30 }, { 66, 31 },
+ { 67, 32 }, { 69, 33 }, { 70, 34 }, { 72, 72 }, { 75, 35 }, { 79, 36 }, { 80, 21 },
+ { 81, 38 }, { 83, 9 }, { 84, 39 }, { 85, 40 }, { 86, 19 }, { 87, 42 }, { 88, 43 },
+ { 89, 45 }, { 91, 74 }, { 93, 46 }, { 94, 47 }, { 95, 48 }, { 96, 49 }, { 97, 50 },
+};
+
static const struct msm_pinctrl_soc_data sm6115_tlmm = {
.pins = sm6115_pins,
.npins = ARRAY_SIZE(sm6115_pins),
@@ -877,6 +887,8 @@ static const struct msm_pinctrl_soc_data sm6115_tlmm = {
.ngpios = 114,
.tiles = sm6115_tiles,
.ntiles = ARRAY_SIZE(sm6115_tiles),
+ .wakeirq_map = sm6115_mpm_map,
+ .nwakeirq_map = ARRAY_SIZE(sm6115_mpm_map),
};
static int sm6115_tlmm_probe(struct platform_device *pdev)
@@ -895,7 +907,7 @@ static struct platform_driver sm6115_tlmm_driver = {
.of_match_table = sm6115_tlmm_of_match,
},
.probe = sm6115_tlmm_probe,
- .remove = msm_pinctrl_remove,
+ .remove_new = msm_pinctrl_remove,
};
static int __init sm6115_tlmm_init(void)
diff --git a/drivers/pinctrl/qcom/pinctrl-sm6125.c b/drivers/pinctrl/qcom/pinctrl-sm6125.c
index d5e2b89695..65de34c307 100644
--- a/drivers/pinctrl/qcom/pinctrl-sm6125.c
+++ b/drivers/pinctrl/qcom/pinctrl-sm6125.c
@@ -1221,6 +1221,21 @@ static const struct msm_pingroup sm6125_groups[] = {
[140] = SDC_QDSD_PINGROUP(sdc2_data, SOUTH, 0x58b000, 9, 0),
};
+static const struct msm_gpio_wakeirq_map sm6125_mpm_map[] = {
+ { 1, 14 }, { 3, 15 }, { 4, 16 }, { 9, 17 }, { 13, 18 }, { 14, 23 },
+ { 15, 19 }, { 17, 20 }, { 19, 21 }, { 21, 22 }, { 22, 84 }, { 25, 24 },
+ { 26, 25 }, { 27, 26 }, { 29, 27 }, { 33, 28 }, { 36, 29 }, { 42, 30 },
+ { 43, 5 }, { 44, 31 }, { 45, 6 }, { 47, 32 }, { 50, 33 }, { 59, 7 },
+ { 70, 34 }, { 72, 8 }, { 75, 35 }, { 79, 36 }, { 80, 37 }, { 81, 38 },
+ { 82, 39 }, { 83, 9 }, { 85, 40 }, { 86, 41 }, { 88, 42 }, { 89, 43 },
+ { 91, 44 }, { 92, 45 }, { 93, 46 }, { 94, 47 }, { 95, 48 }, { 96, 49 },
+ { 97, 70 }, { 98, 50 }, { 99, 51 }, { 100, 64 }, { 101, 52 },
+ { 102, 53 }, { 105, 54 }, { 107, 55 }, { 110, 56 }, { 111, 57 },
+ { 112, 58 }, { 118, 59 }, { 120, 71 }, { 122, 60 }, { 123, 61 },
+ { 124, 13 }, { 126, 62 }, { 128, 63 }, { 130, 65 }, { 131, 66 },
+ { 132, 67 },
+};
+
static const struct msm_pinctrl_soc_data sm6125_tlmm = {
.pins = sm6125_pins,
.npins = ARRAY_SIZE(sm6125_pins),
@@ -1231,6 +1246,8 @@ static const struct msm_pinctrl_soc_data sm6125_tlmm = {
.ngpios = 134,
.tiles = sm6125_tiles,
.ntiles = ARRAY_SIZE(sm6125_tiles),
+ .wakeirq_map = sm6125_mpm_map,
+ .nwakeirq_map = ARRAY_SIZE(sm6125_mpm_map),
};
static int sm6125_tlmm_probe(struct platform_device *pdev)
@@ -1249,7 +1266,7 @@ static struct platform_driver sm6125_tlmm_driver = {
.of_match_table = sm6125_tlmm_of_match,
},
.probe = sm6125_tlmm_probe,
- .remove = msm_pinctrl_remove,
+ .remove_new = msm_pinctrl_remove,
};
static int __init sm6125_tlmm_init(void)
diff --git a/drivers/pinctrl/qcom/pinctrl-sm6350.c b/drivers/pinctrl/qcom/pinctrl-sm6350.c
index f3828c07b1..4aeb1ba43e 100644
--- a/drivers/pinctrl/qcom/pinctrl-sm6350.c
+++ b/drivers/pinctrl/qcom/pinctrl-sm6350.c
@@ -1373,7 +1373,7 @@ static struct platform_driver sm6350_tlmm_driver = {
.of_match_table = sm6350_tlmm_of_match,
},
.probe = sm6350_tlmm_probe,
- .remove = msm_pinctrl_remove,
+ .remove_new = msm_pinctrl_remove,
};
static int __init sm6350_tlmm_init(void)
diff --git a/drivers/pinctrl/qcom/pinctrl-sm6375.c b/drivers/pinctrl/qcom/pinctrl-sm6375.c
index c82c851693..d86630d712 100644
--- a/drivers/pinctrl/qcom/pinctrl-sm6375.c
+++ b/drivers/pinctrl/qcom/pinctrl-sm6375.c
@@ -1516,7 +1516,7 @@ static struct platform_driver sm6375_tlmm_driver = {
.of_match_table = sm6375_tlmm_of_match,
},
.probe = sm6375_tlmm_probe,
- .remove = msm_pinctrl_remove,
+ .remove_new = msm_pinctrl_remove,
};
static int __init sm6375_tlmm_init(void)
diff --git a/drivers/pinctrl/qcom/pinctrl-sm7150.c b/drivers/pinctrl/qcom/pinctrl-sm7150.c
index 33657cf98f..c25357ca19 100644
--- a/drivers/pinctrl/qcom/pinctrl-sm7150.c
+++ b/drivers/pinctrl/qcom/pinctrl-sm7150.c
@@ -1254,7 +1254,7 @@ static struct platform_driver sm7150_tlmm_driver = {
.of_match_table = sm7150_tlmm_of_match,
},
.probe = sm7150_tlmm_probe,
- .remove = msm_pinctrl_remove,
+ .remove_new = msm_pinctrl_remove,
};
static int __init sm7150_tlmm_init(void)
diff --git a/drivers/pinctrl/qcom/pinctrl-sm8150.c b/drivers/pinctrl/qcom/pinctrl-sm8150.c
index 01aea9c70b..f8f5bee74f 100644
--- a/drivers/pinctrl/qcom/pinctrl-sm8150.c
+++ b/drivers/pinctrl/qcom/pinctrl-sm8150.c
@@ -1542,7 +1542,7 @@ static struct platform_driver sm8150_pinctrl_driver = {
.of_match_table = sm8150_pinctrl_of_match,
},
.probe = sm8150_pinctrl_probe,
- .remove = msm_pinctrl_remove,
+ .remove_new = msm_pinctrl_remove,
};
static int __init sm8150_pinctrl_init(void)
diff --git a/drivers/pinctrl/qcom/pinctrl-sm8250-lpass-lpi.c b/drivers/pinctrl/qcom/pinctrl-sm8250-lpass-lpi.c
index ddbc6317f2..cb10ce8d5d 100644
--- a/drivers/pinctrl/qcom/pinctrl-sm8250-lpass-lpi.c
+++ b/drivers/pinctrl/qcom/pinctrl-sm8250-lpass-lpi.c
@@ -155,7 +155,7 @@ static struct platform_driver lpi_pinctrl_driver = {
.of_match_table = lpi_pinctrl_of_match,
},
.probe = lpi_pinctrl_probe,
- .remove = lpi_pinctrl_remove,
+ .remove_new = lpi_pinctrl_remove,
};
module_platform_driver(lpi_pinctrl_driver);
diff --git a/drivers/pinctrl/qcom/pinctrl-sm8250.c b/drivers/pinctrl/qcom/pinctrl-sm8250.c
index e9961a49ff..54fda77bf2 100644
--- a/drivers/pinctrl/qcom/pinctrl-sm8250.c
+++ b/drivers/pinctrl/qcom/pinctrl-sm8250.c
@@ -1351,7 +1351,7 @@ static struct platform_driver sm8250_pinctrl_driver = {
.of_match_table = sm8250_pinctrl_of_match,
},
.probe = sm8250_pinctrl_probe,
- .remove = msm_pinctrl_remove,
+ .remove_new = msm_pinctrl_remove,
};
static int __init sm8250_pinctrl_init(void)
diff --git a/drivers/pinctrl/qcom/pinctrl-sm8350-lpass-lpi.c b/drivers/pinctrl/qcom/pinctrl-sm8350-lpass-lpi.c
index f889c779bc..297cc95ac3 100644
--- a/drivers/pinctrl/qcom/pinctrl-sm8350-lpass-lpi.c
+++ b/drivers/pinctrl/qcom/pinctrl-sm8350-lpass-lpi.c
@@ -158,7 +158,7 @@ static struct platform_driver lpi_pinctrl_driver = {
.of_match_table = lpi_pinctrl_of_match,
},
.probe = lpi_pinctrl_probe,
- .remove = lpi_pinctrl_remove,
+ .remove_new = lpi_pinctrl_remove,
};
module_platform_driver(lpi_pinctrl_driver);
diff --git a/drivers/pinctrl/qcom/pinctrl-sm8350.c b/drivers/pinctrl/qcom/pinctrl-sm8350.c
index 9c69458bd9..ac7f2820f2 100644
--- a/drivers/pinctrl/qcom/pinctrl-sm8350.c
+++ b/drivers/pinctrl/qcom/pinctrl-sm8350.c
@@ -1642,7 +1642,7 @@ static struct platform_driver sm8350_tlmm_driver = {
.of_match_table = sm8350_tlmm_of_match,
},
.probe = sm8350_tlmm_probe,
- .remove = msm_pinctrl_remove,
+ .remove_new = msm_pinctrl_remove,
};
static int __init sm8350_tlmm_init(void)
diff --git a/drivers/pinctrl/qcom/pinctrl-sm8450-lpass-lpi.c b/drivers/pinctrl/qcom/pinctrl-sm8450-lpass-lpi.c
index e22d03ce29..2e7896791f 100644
--- a/drivers/pinctrl/qcom/pinctrl-sm8450-lpass-lpi.c
+++ b/drivers/pinctrl/qcom/pinctrl-sm8450-lpass-lpi.c
@@ -232,7 +232,7 @@ static struct platform_driver lpi_pinctrl_driver = {
.of_match_table = lpi_pinctrl_of_match,
},
.probe = lpi_pinctrl_probe,
- .remove = lpi_pinctrl_remove,
+ .remove_new = lpi_pinctrl_remove,
};
module_platform_driver(lpi_pinctrl_driver);
diff --git a/drivers/pinctrl/qcom/pinctrl-sm8450.c b/drivers/pinctrl/qcom/pinctrl-sm8450.c
index d11bb1ee9e..6172867116 100644
--- a/drivers/pinctrl/qcom/pinctrl-sm8450.c
+++ b/drivers/pinctrl/qcom/pinctrl-sm8450.c
@@ -1677,7 +1677,7 @@ static struct platform_driver sm8450_tlmm_driver = {
.of_match_table = sm8450_tlmm_of_match,
},
.probe = sm8450_tlmm_probe,
- .remove = msm_pinctrl_remove,
+ .remove_new = msm_pinctrl_remove,
};
static int __init sm8450_tlmm_init(void)
diff --git a/drivers/pinctrl/qcom/pinctrl-sm8550-lpass-lpi.c b/drivers/pinctrl/qcom/pinctrl-sm8550-lpass-lpi.c
index db1a46fee9..64458c3fbe 100644
--- a/drivers/pinctrl/qcom/pinctrl-sm8550-lpass-lpi.c
+++ b/drivers/pinctrl/qcom/pinctrl-sm8550-lpass-lpi.c
@@ -240,7 +240,7 @@ static struct platform_driver lpi_pinctrl_driver = {
.of_match_table = lpi_pinctrl_of_match,
},
.probe = lpi_pinctrl_probe,
- .remove = lpi_pinctrl_remove,
+ .remove_new = lpi_pinctrl_remove,
};
module_platform_driver(lpi_pinctrl_driver);
diff --git a/drivers/pinctrl/qcom/pinctrl-sm8550.c b/drivers/pinctrl/qcom/pinctrl-sm8550.c
index 3c847d9cb5..9184e01837 100644
--- a/drivers/pinctrl/qcom/pinctrl-sm8550.c
+++ b/drivers/pinctrl/qcom/pinctrl-sm8550.c
@@ -1762,7 +1762,7 @@ static struct platform_driver sm8550_tlmm_driver = {
.of_match_table = sm8550_tlmm_of_match,
},
.probe = sm8550_tlmm_probe,
- .remove = msm_pinctrl_remove,
+ .remove_new = msm_pinctrl_remove,
};
static int __init sm8550_tlmm_init(void)
diff --git a/drivers/pinctrl/qcom/pinctrl-spmi-gpio.c b/drivers/pinctrl/qcom/pinctrl-spmi-gpio.c
index deded9c6fd..f4e2c88a7c 100644
--- a/drivers/pinctrl/qcom/pinctrl-spmi-gpio.c
+++ b/drivers/pinctrl/qcom/pinctrl-spmi-gpio.c
@@ -1185,12 +1185,11 @@ err_range:
return ret;
}
-static int pmic_gpio_remove(struct platform_device *pdev)
+static void pmic_gpio_remove(struct platform_device *pdev)
{
struct pmic_gpio_state *state = platform_get_drvdata(pdev);
gpiochip_remove(&state->chip);
- return 0;
}
static const struct of_device_id pmic_gpio_of_match[] = {
@@ -1265,7 +1264,7 @@ static struct platform_driver pmic_gpio_driver = {
.of_match_table = pmic_gpio_of_match,
},
.probe = pmic_gpio_probe,
- .remove = pmic_gpio_remove,
+ .remove_new = pmic_gpio_remove,
};
module_platform_driver(pmic_gpio_driver);
diff --git a/drivers/pinctrl/qcom/pinctrl-spmi-mpp.c b/drivers/pinctrl/qcom/pinctrl-spmi-mpp.c
index fe0393829c..d16ece90d9 100644
--- a/drivers/pinctrl/qcom/pinctrl-spmi-mpp.c
+++ b/drivers/pinctrl/qcom/pinctrl-spmi-mpp.c
@@ -971,12 +971,11 @@ err_range:
return ret;
}
-static int pmic_mpp_remove(struct platform_device *pdev)
+static void pmic_mpp_remove(struct platform_device *pdev)
{
struct pmic_mpp_state *state = platform_get_drvdata(pdev);
gpiochip_remove(&state->chip);
- return 0;
}
static const struct of_device_id pmic_mpp_of_match[] = {
@@ -1001,7 +1000,7 @@ static struct platform_driver pmic_mpp_driver = {
.of_match_table = pmic_mpp_of_match,
},
.probe = pmic_mpp_probe,
- .remove = pmic_mpp_remove,
+ .remove_new = pmic_mpp_remove,
};
module_platform_driver(pmic_mpp_driver);
diff --git a/drivers/pinctrl/qcom/pinctrl-ssbi-gpio.c b/drivers/pinctrl/qcom/pinctrl-ssbi-gpio.c
index e0d43d076c..9cd5247ea5 100644
--- a/drivers/pinctrl/qcom/pinctrl-ssbi-gpio.c
+++ b/drivers/pinctrl/qcom/pinctrl-ssbi-gpio.c
@@ -853,13 +853,11 @@ unregister_gpiochip:
return ret;
}
-static int pm8xxx_gpio_remove(struct platform_device *pdev)
+static void pm8xxx_gpio_remove(struct platform_device *pdev)
{
struct pm8xxx_gpio *pctrl = platform_get_drvdata(pdev);
gpiochip_remove(&pctrl->chip);
-
- return 0;
}
static struct platform_driver pm8xxx_gpio_driver = {
@@ -868,7 +866,7 @@ static struct platform_driver pm8xxx_gpio_driver = {
.of_match_table = pm8xxx_gpio_of_match,
},
.probe = pm8xxx_gpio_probe,
- .remove = pm8xxx_gpio_remove,
+ .remove_new = pm8xxx_gpio_remove,
};
module_platform_driver(pm8xxx_gpio_driver);
diff --git a/drivers/pinctrl/qcom/pinctrl-ssbi-mpp.c b/drivers/pinctrl/qcom/pinctrl-ssbi-mpp.c
index 985d1a0ee8..3aee6835a2 100644
--- a/drivers/pinctrl/qcom/pinctrl-ssbi-mpp.c
+++ b/drivers/pinctrl/qcom/pinctrl-ssbi-mpp.c
@@ -936,13 +936,11 @@ unregister_gpiochip:
return ret;
}
-static int pm8xxx_mpp_remove(struct platform_device *pdev)
+static void pm8xxx_mpp_remove(struct platform_device *pdev)
{
struct pm8xxx_mpp *pctrl = platform_get_drvdata(pdev);
gpiochip_remove(&pctrl->chip);
-
- return 0;
}
static struct platform_driver pm8xxx_mpp_driver = {
@@ -951,7 +949,7 @@ static struct platform_driver pm8xxx_mpp_driver = {
.of_match_table = pm8xxx_mpp_of_match,
},
.probe = pm8xxx_mpp_probe,
- .remove = pm8xxx_mpp_remove,
+ .remove_new = pm8xxx_mpp_remove,
};
module_platform_driver(pm8xxx_mpp_driver);
diff --git a/drivers/pinctrl/realtek/Kconfig b/drivers/pinctrl/realtek/Kconfig
new file mode 100644
index 0000000000..0fc6bd4fcb
--- /dev/null
+++ b/drivers/pinctrl/realtek/Kconfig
@@ -0,0 +1,23 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+config PINCTRL_RTD
+ tristate "Realtek DHC core pin controller driver"
+ depends on ARCH_REALTEK
+ default y
+ select PINMUX
+ select GENERIC_PINCONF
+
+config PINCTRL_RTD1619B
+ tristate "Realtek DHC 1619B pin controller driver"
+ depends on PINCTRL_RTD
+ default y
+
+config PINCTRL_RTD1319D
+ tristate "Realtek DHC 1319D pin controller driver"
+ depends on PINCTRL_RTD
+ default y
+
+config PINCTRL_RTD1315E
+ tristate "Realtek DHC 1315E pin controller driver"
+ depends on PINCTRL_RTD
+ default y
diff --git a/drivers/pinctrl/realtek/Makefile b/drivers/pinctrl/realtek/Makefile
new file mode 100644
index 0000000000..c7bace0001
--- /dev/null
+++ b/drivers/pinctrl/realtek/Makefile
@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+# Realtek DHC pin control drivers
+obj-$(CONFIG_PINCTRL_RTD) += pinctrl-rtd.o
+obj-$(CONFIG_PINCTRL_RTD1619B) += pinctrl-rtd1619b.o
+obj-$(CONFIG_PINCTRL_RTD1319D) += pinctrl-rtd1319d.o
+obj-$(CONFIG_PINCTRL_RTD1315E) += pinctrl-rtd1315e.o
diff --git a/drivers/pinctrl/realtek/pinctrl-rtd.c b/drivers/pinctrl/realtek/pinctrl-rtd.c
new file mode 100644
index 0000000000..208896593b
--- /dev/null
+++ b/drivers/pinctrl/realtek/pinctrl-rtd.c
@@ -0,0 +1,596 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Realtek DHC pin controller driver
+ *
+ * Copyright (c) 2023 Realtek Semiconductor Corp.
+ */
+
+#include <linux/bitops.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/pinctrl/machine.h>
+#include <linux/pinctrl/pinconf.h>
+#include <linux/pinctrl/pinconf-generic.h>
+#include <linux/pinctrl/pinctrl.h>
+#include <linux/pinctrl/pinmux.h>
+#include <linux/platform_device.h>
+#include <linux/seq_file.h>
+#include <linux/regmap.h>
+#include <linux/slab.h>
+#include "../core.h"
+#include "../pinctrl-utils.h"
+#include "pinctrl-rtd.h"
+
+struct rtd_pinctrl {
+ struct device *dev;
+ struct pinctrl_dev *pcdev;
+ void __iomem *base;
+ struct pinctrl_desc desc;
+ const struct rtd_pinctrl_desc *info;
+ struct regmap *regmap_pinctrl;
+};
+
+/* custom pinconf parameters */
+#define RTD_DRIVE_STRENGH_P (PIN_CONFIG_END + 1)
+#define RTD_DRIVE_STRENGH_N (PIN_CONFIG_END + 2)
+#define RTD_DUTY_CYCLE (PIN_CONFIG_END + 3)
+
+static const struct pinconf_generic_params rtd_custom_bindings[] = {
+ {"realtek,drive-strength-p", RTD_DRIVE_STRENGH_P, 0},
+ {"realtek,drive-strength-n", RTD_DRIVE_STRENGH_N, 0},
+ {"realtek,duty-cycle", RTD_DUTY_CYCLE, 0},
+};
+
+static int rtd_pinctrl_get_groups_count(struct pinctrl_dev *pcdev)
+{
+ struct rtd_pinctrl *data = pinctrl_dev_get_drvdata(pcdev);
+
+ return data->info->num_groups;
+}
+
+static const char *rtd_pinctrl_get_group_name(struct pinctrl_dev *pcdev,
+ unsigned int selector)
+{
+ struct rtd_pinctrl *data = pinctrl_dev_get_drvdata(pcdev);
+
+ return data->info->groups[selector].name;
+}
+
+static int rtd_pinctrl_get_group_pins(struct pinctrl_dev *pcdev,
+ unsigned int selector,
+ const unsigned int **pins,
+ unsigned int *num_pins)
+{
+ struct rtd_pinctrl *data = pinctrl_dev_get_drvdata(pcdev);
+
+ *pins = data->info->groups[selector].pins;
+ *num_pins = data->info->groups[selector].num_pins;
+
+ return 0;
+}
+
+static void rtd_pinctrl_dbg_show(struct pinctrl_dev *pcdev,
+ struct seq_file *s,
+ unsigned int offset)
+{
+ struct rtd_pinctrl *data = pinctrl_dev_get_drvdata(pcdev);
+ const struct rtd_pin_desc *mux = &data->info->muxes[offset];
+ const struct rtd_pin_mux_desc *func;
+ u32 val;
+ u32 mask;
+ u32 pin_val;
+ int is_map;
+
+ if (!mux->name) {
+ seq_puts(s, "[not defined]");
+ return;
+ }
+ val = readl_relaxed(data->base + mux->mux_offset);
+ mask = mux->mux_mask;
+ pin_val = val & mask;
+
+ is_map = 0;
+ func = &mux->functions[0];
+ seq_puts(s, "function: ");
+ while (func->name) {
+ if (func->mux_value == pin_val) {
+ is_map = 1;
+ seq_printf(s, "[%s] ", func->name);
+ } else {
+ seq_printf(s, "%s ", func->name);
+ }
+ func++;
+ }
+ if (!is_map)
+ seq_puts(s, "[not defined]");
+}
+
+static const struct pinctrl_ops rtd_pinctrl_ops = {
+ .dt_node_to_map = pinconf_generic_dt_node_to_map_all,
+ .dt_free_map = pinctrl_utils_free_map,
+ .get_groups_count = rtd_pinctrl_get_groups_count,
+ .get_group_name = rtd_pinctrl_get_group_name,
+ .get_group_pins = rtd_pinctrl_get_group_pins,
+ .pin_dbg_show = rtd_pinctrl_dbg_show,
+};
+
+static int rtd_pinctrl_get_functions_count(struct pinctrl_dev *pcdev)
+{
+ struct rtd_pinctrl *data = pinctrl_dev_get_drvdata(pcdev);
+
+ return data->info->num_functions;
+}
+
+static const char *rtd_pinctrl_get_function_name(struct pinctrl_dev *pcdev,
+ unsigned int selector)
+{
+ struct rtd_pinctrl *data = pinctrl_dev_get_drvdata(pcdev);
+
+ return data->info->functions[selector].name;
+}
+
+static int rtd_pinctrl_get_function_groups(struct pinctrl_dev *pcdev,
+ unsigned int selector,
+ const char * const **groups,
+ unsigned int * const num_groups)
+{
+ struct rtd_pinctrl *data = pinctrl_dev_get_drvdata(pcdev);
+
+ *groups = data->info->functions[selector].groups;
+ *num_groups = data->info->functions[selector].num_groups;
+
+ return 0;
+}
+
+static const struct rtd_pin_desc *rtd_pinctrl_find_mux(struct rtd_pinctrl *data, unsigned int pin)
+{
+ if (data->info->muxes[pin].name)
+ return &data->info->muxes[pin];
+
+ return NULL;
+}
+
+static int rtd_pinctrl_set_one_mux(struct pinctrl_dev *pcdev,
+ unsigned int pin, const char *func_name)
+{
+ struct rtd_pinctrl *data = pinctrl_dev_get_drvdata(pcdev);
+ const struct rtd_pin_desc *mux;
+ int ret = 0;
+ int i;
+
+ mux = rtd_pinctrl_find_mux(data, pin);
+ if (!mux)
+ return 0;
+
+ if (!mux->functions) {
+ if (!mux->name)
+ dev_err(pcdev->dev, "NULL pin has no functions\n");
+ else
+ dev_err(pcdev->dev, "No functions available for pin %s\n", mux->name);
+ return -ENOTSUPP;
+ }
+
+ for (i = 0; mux->functions[i].name; i++) {
+ if (strcmp(mux->functions[i].name, func_name) != 0)
+ continue;
+ ret = regmap_update_bits(data->regmap_pinctrl, mux->mux_offset, mux->mux_mask,
+ mux->functions[i].mux_value);
+ return ret;
+ }
+
+ if (!mux->name) {
+ dev_err(pcdev->dev, "NULL pin provided for function %s\n", func_name);
+ return -EINVAL;
+ }
+
+ dev_err(pcdev->dev, "No function %s available for pin %s\n", func_name, mux->name);
+
+ return -EINVAL;
+}
+
+static int rtd_pinctrl_set_mux(struct pinctrl_dev *pcdev,
+ unsigned int function, unsigned int group)
+{
+ struct rtd_pinctrl *data = pinctrl_dev_get_drvdata(pcdev);
+ const unsigned int *pins;
+ unsigned int num_pins;
+ const char *func_name;
+ const char *group_name;
+ int i, ret;
+
+ func_name = data->info->functions[function].name;
+ group_name = data->info->groups[group].name;
+
+ ret = rtd_pinctrl_get_group_pins(pcdev, group, &pins, &num_pins);
+ if (ret) {
+ dev_err(pcdev->dev, "Getting pins for group %s failed\n", group_name);
+ return ret;
+ }
+
+ for (i = 0; i < num_pins; i++) {
+ ret = rtd_pinctrl_set_one_mux(pcdev, pins[i], func_name);
+ if (ret)
+ return ret;
+ }
+
+ return 0;
+}
+
+static int rtd_pinctrl_gpio_request_enable(struct pinctrl_dev *pcdev,
+ struct pinctrl_gpio_range *range,
+ unsigned int offset)
+{
+ return rtd_pinctrl_set_one_mux(pcdev, offset, "gpio");
+}
+
+static const struct pinmux_ops rtd_pinmux_ops = {
+ .get_functions_count = rtd_pinctrl_get_functions_count,
+ .get_function_name = rtd_pinctrl_get_function_name,
+ .get_function_groups = rtd_pinctrl_get_function_groups,
+ .set_mux = rtd_pinctrl_set_mux,
+ .gpio_request_enable = rtd_pinctrl_gpio_request_enable,
+};
+
+static const struct pinctrl_pin_desc
+ *rtd_pinctrl_get_pin_by_number(struct rtd_pinctrl *data, int number)
+{
+ int i;
+
+ for (i = 0; i < data->info->num_pins; i++) {
+ if (data->info->pins[i].number == number)
+ return &data->info->pins[i];
+ }
+
+ return NULL;
+}
+
+static const struct rtd_pin_config_desc
+ *rtd_pinctrl_find_config(struct rtd_pinctrl *data, unsigned int pin)
+{
+ if (data->info->configs[pin].name)
+ return &data->info->configs[pin];
+
+ return NULL;
+}
+
+static const struct rtd_pin_sconfig_desc *rtd_pinctrl_find_sconfig(struct rtd_pinctrl *data,
+ unsigned int pin)
+{
+ int i;
+ const struct pinctrl_pin_desc *pin_desc;
+ const char *pin_name;
+
+ pin_desc = rtd_pinctrl_get_pin_by_number(data, pin);
+ if (!pin_desc)
+ return NULL;
+
+ pin_name = pin_desc->name;
+
+ for (i = 0; i < data->info->num_sconfigs; i++) {
+ if (strcmp(data->info->sconfigs[i].name, pin_name) == 0)
+ return &data->info->sconfigs[i];
+ }
+
+ return NULL;
+}
+
+static int rtd_pconf_parse_conf(struct rtd_pinctrl *data,
+ unsigned int pinnr,
+ enum pin_config_param param,
+ enum pin_config_param arg)
+{
+ const struct rtd_pin_config_desc *config_desc;
+ const struct rtd_pin_sconfig_desc *sconfig_desc;
+ u8 set_val = 0;
+ u16 strength;
+ u32 val;
+ u32 mask;
+ u32 pulsel_off, pulen_off, smt_off, curr_off, pow_off, reg_off, p_off, n_off;
+ const char *name = data->info->pins[pinnr].name;
+ int ret = 0;
+
+ config_desc = rtd_pinctrl_find_config(data, pinnr);
+ if (!config_desc) {
+ dev_err(data->dev, "Not support pin config for pin: %s\n", name);
+ return -ENOTSUPP;
+ }
+ switch ((u32)param) {
+ case PIN_CONFIG_INPUT_SCHMITT:
+ case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
+ if (config_desc->smt_offset == NA) {
+ dev_err(data->dev, "Not support input schmitt for pin: %s\n", name);
+ return -ENOTSUPP;
+ }
+ smt_off = config_desc->base_bit + config_desc->smt_offset;
+ reg_off = config_desc->reg_offset;
+ set_val = arg;
+
+ mask = BIT(smt_off);
+ val = set_val ? BIT(smt_off) : 0;
+ break;
+
+ case PIN_CONFIG_DRIVE_PUSH_PULL:
+ if (config_desc->pud_en_offset == NA) {
+ dev_err(data->dev, "Not support push pull for pin: %s\n", name);
+ return -ENOTSUPP;
+ }
+ pulen_off = config_desc->base_bit + config_desc->pud_en_offset;
+ reg_off = config_desc->reg_offset;
+
+ mask = BIT(pulen_off);
+ val = 0;
+ break;
+
+ case PIN_CONFIG_BIAS_DISABLE:
+ if (config_desc->pud_en_offset == NA) {
+ dev_err(data->dev, "Not support bias disable for pin: %s\n", name);
+ return -ENOTSUPP;
+ }
+ pulen_off = config_desc->base_bit + config_desc->pud_en_offset;
+ reg_off = config_desc->reg_offset;
+
+ mask = BIT(pulen_off);
+ val = 0;
+ break;
+
+ case PIN_CONFIG_BIAS_PULL_UP:
+ if (config_desc->pud_en_offset == NA) {
+ dev_err(data->dev, "Not support bias pull up for pin:%s\n", name);
+ return -ENOTSUPP;
+ }
+ pulen_off = config_desc->base_bit + config_desc->pud_en_offset;
+ pulsel_off = config_desc->base_bit + config_desc->pud_sel_offset;
+ reg_off = config_desc->reg_offset;
+
+ mask = BIT(pulen_off) | BIT(pulsel_off);
+ val = mask;
+ break;
+
+ case PIN_CONFIG_BIAS_PULL_DOWN:
+ if (config_desc->pud_en_offset == NA) {
+ dev_err(data->dev, "Not support bias pull down for pin: %s\n", name);
+ return -ENOTSUPP;
+ }
+ pulen_off = config_desc->base_bit + config_desc->pud_en_offset;
+ pulsel_off = config_desc->base_bit + config_desc->pud_sel_offset;
+ reg_off = config_desc->reg_offset;
+
+ mask = BIT(pulen_off) | BIT(pulsel_off);
+ val = BIT(pulen_off);
+ break;
+
+ case PIN_CONFIG_DRIVE_STRENGTH:
+ curr_off = config_desc->base_bit + config_desc->curr_offset;
+ reg_off = config_desc->reg_offset;
+ strength = arg;
+ val = 0;
+ switch (config_desc->curr_type) {
+ case PADDRI_4_8:
+ if (strength == 4)
+ val = 0;
+ else if (strength == 8)
+ val = BIT(curr_off);
+ else
+ return -EINVAL;
+ break;
+ case PADDRI_2_4:
+ if (strength == 2)
+ val = 0;
+ else if (strength == 4)
+ val = BIT(curr_off);
+ else
+ return -EINVAL;
+ break;
+ case NA:
+ dev_err(data->dev, "Not support drive strength for pin: %s\n", name);
+ return -ENOTSUPP;
+ default:
+ return -EINVAL;
+ }
+ mask = BIT(curr_off);
+ break;
+
+ case PIN_CONFIG_POWER_SOURCE:
+ if (config_desc->power_offset == NA) {
+ dev_err(data->dev, "Not support power source for pin: %s\n", name);
+ return -ENOTSUPP;
+ }
+ reg_off = config_desc->reg_offset;
+ pow_off = config_desc->base_bit + config_desc->power_offset;
+ if (pow_off >= 32) {
+ reg_off += 0x4;
+ pow_off -= 32;
+ }
+ set_val = arg;
+ mask = BIT(pow_off);
+ val = set_val ? mask : 0;
+ break;
+
+ case RTD_DRIVE_STRENGH_P:
+ sconfig_desc = rtd_pinctrl_find_sconfig(data, pinnr);
+ if (!sconfig_desc) {
+ dev_err(data->dev, "Not support P driving for pin: %s\n", name);
+ return -ENOTSUPP;
+ }
+ set_val = arg;
+ reg_off = sconfig_desc->reg_offset;
+ p_off = sconfig_desc->pdrive_offset;
+ if (p_off >= 32) {
+ reg_off += 0x4;
+ p_off -= 32;
+ }
+ mask = GENMASK(p_off + sconfig_desc->pdrive_maskbits - 1, p_off);
+ val = set_val << p_off;
+ break;
+
+ case RTD_DRIVE_STRENGH_N:
+ sconfig_desc = rtd_pinctrl_find_sconfig(data, pinnr);
+ if (!sconfig_desc) {
+ dev_err(data->dev, "Not support N driving for pin: %s\n", name);
+ return -ENOTSUPP;
+ }
+ set_val = arg;
+ reg_off = sconfig_desc->reg_offset;
+ n_off = sconfig_desc->ndrive_offset;
+ if (n_off >= 32) {
+ reg_off += 0x4;
+ n_off -= 32;
+ }
+ mask = GENMASK(n_off + sconfig_desc->ndrive_maskbits - 1, n_off);
+ val = set_val << n_off;
+ break;
+
+ case RTD_DUTY_CYCLE:
+ sconfig_desc = rtd_pinctrl_find_sconfig(data, pinnr);
+ if (!sconfig_desc || sconfig_desc->dcycle_offset == NA) {
+ dev_err(data->dev, "Not support duty cycle for pin: %s\n", name);
+ return -ENOTSUPP;
+ }
+ set_val = arg;
+ reg_off = config_desc->reg_offset;
+ mask = GENMASK(sconfig_desc->dcycle_offset +
+ sconfig_desc->dcycle_maskbits - 1, sconfig_desc->dcycle_offset);
+ val = set_val << sconfig_desc->dcycle_offset;
+ break;
+
+ default:
+ dev_err(data->dev, "unsupported pinconf: %d\n", (u32)param);
+ return -EINVAL;
+ }
+
+ ret = regmap_update_bits(data->regmap_pinctrl, reg_off, mask, val);
+ if (ret)
+ dev_err(data->dev, "could not update pinconf(%d) for pin(%s)\n", (u32)param, name);
+
+ return ret;
+}
+
+static int rtd_pin_config_get(struct pinctrl_dev *pcdev, unsigned int pinnr,
+ unsigned long *config)
+{
+ unsigned int param = pinconf_to_config_param(*config);
+ unsigned int arg = 0;
+
+ switch (param) {
+ default:
+ return -ENOTSUPP;
+ }
+
+ *config = pinconf_to_config_packed(param, arg);
+ return 0;
+}
+
+static int rtd_pin_config_set(struct pinctrl_dev *pcdev, unsigned int pinnr,
+ unsigned long *configs, unsigned int num_configs)
+{
+ struct rtd_pinctrl *data = pinctrl_dev_get_drvdata(pcdev);
+ int i;
+ int ret = 0;
+
+ for (i = 0; i < num_configs; i++) {
+ ret = rtd_pconf_parse_conf(data, pinnr,
+ pinconf_to_config_param(configs[i]),
+ pinconf_to_config_argument(configs[i]));
+ if (ret < 0)
+ return ret;
+ }
+
+ return 0;
+}
+
+static int rtd_pin_config_group_set(struct pinctrl_dev *pcdev, unsigned int group,
+ unsigned long *configs, unsigned int num_configs)
+{
+ struct rtd_pinctrl *data = pinctrl_dev_get_drvdata(pcdev);
+ const unsigned int *pins;
+ unsigned int num_pins;
+ const char *group_name;
+ int i, ret;
+
+ group_name = data->info->groups[group].name;
+
+ ret = rtd_pinctrl_get_group_pins(pcdev, group, &pins, &num_pins);
+ if (ret) {
+ dev_err(pcdev->dev, "Getting pins for group %s failed\n", group_name);
+ return ret;
+ }
+
+ for (i = 0; i < num_pins; i++) {
+ ret = rtd_pin_config_set(pcdev, pins[i], configs, num_configs);
+ if (ret)
+ return ret;
+ }
+
+ return 0;
+}
+
+static const struct pinconf_ops rtd_pinconf_ops = {
+ .is_generic = true,
+ .pin_config_get = rtd_pin_config_get,
+ .pin_config_set = rtd_pin_config_set,
+ .pin_config_group_set = rtd_pin_config_group_set,
+};
+
+static struct regmap_config rtd_pinctrl_regmap_config = {
+ .reg_bits = 32,
+ .val_bits = 32,
+ .reg_stride = 4,
+ .use_relaxed_mmio = true,
+};
+
+int rtd_pinctrl_probe(struct platform_device *pdev, const struct rtd_pinctrl_desc *desc)
+{
+ struct rtd_pinctrl *data;
+ int ret;
+
+ data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL);
+ if (!data)
+ return -ENOMEM;
+
+ data->base = of_iomap(pdev->dev.of_node, 0);
+ if (!data->base)
+ return -ENOMEM;
+
+ data->dev = &pdev->dev;
+ data->info = desc;
+ data->desc.name = dev_name(&pdev->dev);
+ data->desc.pins = data->info->pins;
+ data->desc.npins = data->info->num_pins;
+ data->desc.pctlops = &rtd_pinctrl_ops;
+ data->desc.pmxops = &rtd_pinmux_ops;
+ data->desc.confops = &rtd_pinconf_ops;
+ data->desc.custom_params = rtd_custom_bindings;
+ data->desc.num_custom_params = ARRAY_SIZE(rtd_custom_bindings);
+ data->desc.owner = THIS_MODULE;
+ data->regmap_pinctrl = devm_regmap_init_mmio(data->dev, data->base,
+ &rtd_pinctrl_regmap_config);
+
+ if (IS_ERR(data->regmap_pinctrl)) {
+ dev_err(data->dev, "failed to init regmap: %ld\n",
+ PTR_ERR(data->regmap_pinctrl));
+ ret = PTR_ERR(data->regmap_pinctrl);
+ goto unmap;
+ }
+
+ data->pcdev = pinctrl_register(&data->desc, &pdev->dev, data);
+ if (IS_ERR(data->pcdev)) {
+ ret = PTR_ERR(data->pcdev);
+ goto unmap;
+ }
+
+ platform_set_drvdata(pdev, data);
+
+ dev_dbg(&pdev->dev, "probed\n");
+
+ return 0;
+
+unmap:
+ iounmap(data->base);
+ return ret;
+}
+EXPORT_SYMBOL(rtd_pinctrl_probe);
+
+MODULE_DESCRIPTION("Realtek DHC SoC pinctrl driver");
+MODULE_LICENSE("GPL v2");
diff --git a/drivers/pinctrl/realtek/pinctrl-rtd.h b/drivers/pinctrl/realtek/pinctrl-rtd.h
new file mode 100644
index 0000000000..e15130896a
--- /dev/null
+++ b/drivers/pinctrl/realtek/pinctrl-rtd.h
@@ -0,0 +1,124 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * Copyright (c) 2023 Realtek Semiconductor Corp.
+ */
+
+#define NA 0xffffffff
+#define PADDRI_4_8 1
+#define PADDRI_2_4 0
+
+struct rtd_pin_group_desc {
+ const char *name;
+ const unsigned int *pins;
+ unsigned int num_pins;
+};
+
+struct rtd_pin_func_desc {
+ const char *name;
+ const char * const *groups;
+ unsigned int num_groups;
+};
+
+struct rtd_pin_mux_desc {
+ const char *name;
+ u32 mux_value;
+};
+
+struct rtd_pin_config_desc {
+ const char *name;
+ unsigned int reg_offset;
+ unsigned int base_bit;
+ unsigned int pud_en_offset;
+ unsigned int pud_sel_offset;
+ unsigned int curr_offset;
+ unsigned int smt_offset;
+ unsigned int power_offset;
+ unsigned int curr_type;
+};
+
+struct rtd_pin_sconfig_desc {
+ const char *name;
+ unsigned int reg_offset;
+ unsigned int dcycle_offset;
+ unsigned int dcycle_maskbits;
+ unsigned int ndrive_offset;
+ unsigned int ndrive_maskbits;
+ unsigned int pdrive_offset;
+ unsigned int pdrive_maskbits;
+};
+
+struct rtd_pin_desc {
+ const char *name;
+ unsigned int mux_offset;
+ u32 mux_mask;
+ const struct rtd_pin_mux_desc *functions;
+};
+
+struct rtd_pin_reg_list {
+ unsigned int reg_offset;
+ unsigned int val;
+};
+
+#define SHIFT_LEFT(_val, _shift) ((_val) << (_shift))
+
+#define RTK_PIN_MUX(_name, _mux_off, _mux_mask, ...) \
+ { \
+ .name = # _name, \
+ .mux_offset = _mux_off, \
+ .mux_mask = _mux_mask, \
+ .functions = (const struct rtd_pin_mux_desc []) { \
+ __VA_ARGS__, { } \
+ }, \
+ }
+
+#define RTK_PIN_CONFIG(_name, _reg_off, _base_bit, _pud_en_off, \
+ _pud_sel_off, _curr_off, _smt_off, _pow_off, _curr_type) \
+ { \
+ .name = # _name, \
+ .reg_offset = _reg_off, \
+ .base_bit = _base_bit, \
+ .pud_en_offset = _pud_en_off, \
+ .pud_sel_offset = _pud_sel_off, \
+ .curr_offset = _curr_off, \
+ .smt_offset = _smt_off, \
+ .power_offset = _pow_off, \
+ .curr_type = _curr_type, \
+ }
+
+#define RTK_PIN_SCONFIG(_name, _reg_off, _d_offset, _d_mask, \
+ _n_offset, _n_mask, _p_offset, _p_mask) \
+ { \
+ .name = # _name, \
+ .reg_offset = _reg_off, \
+ .dcycle_offset = _d_offset, \
+ .dcycle_maskbits = _d_mask, \
+ .ndrive_offset = _n_offset, \
+ .ndrive_maskbits = _n_mask, \
+ .pdrive_offset = _p_offset, \
+ .pdrive_maskbits = _p_mask, \
+ }
+
+#define RTK_PIN_FUNC(_mux_val, _name) \
+ { \
+ .name = _name, \
+ .mux_value = _mux_val, \
+ }
+
+struct rtd_pinctrl_desc {
+ const struct pinctrl_pin_desc *pins;
+ unsigned int num_pins;
+ const struct rtd_pin_group_desc *groups;
+ unsigned int num_groups;
+ const struct rtd_pin_func_desc *functions;
+ unsigned int num_functions;
+ const struct rtd_pin_desc *muxes;
+ unsigned int num_muxes;
+ const struct rtd_pin_config_desc *configs;
+ unsigned int num_configs;
+ const struct rtd_pin_sconfig_desc *sconfigs;
+ unsigned int num_sconfigs;
+ struct rtd_pin_reg_list *lists;
+ unsigned int num_regs;
+};
+
+int rtd_pinctrl_probe(struct platform_device *pdev, const struct rtd_pinctrl_desc *desc);
diff --git a/drivers/pinctrl/realtek/pinctrl-rtd1315e.c b/drivers/pinctrl/realtek/pinctrl-rtd1315e.c
new file mode 100644
index 0000000000..10afc736a5
--- /dev/null
+++ b/drivers/pinctrl/realtek/pinctrl-rtd1315e.c
@@ -0,0 +1,1440 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Realtek DHC 1315E pin controller driver
+ *
+ * Copyright (c) 2023 Realtek Semiconductor Corp.
+ *
+ */
+
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/platform_device.h>
+#include <linux/pinctrl/pinctrl.h>
+
+#include "pinctrl-rtd.h"
+
+enum rtd13xxe_iso_pins {
+ RTD1315E_ISO_GPIO_0 = 0,
+ RTD1315E_ISO_GPIO_1,
+ RTD1315E_ISO_EMMC_RST_N,
+ RTD1315E_ISO_EMMC_DD_SB,
+ RTD1315E_ISO_EMMC_CLK,
+ RTD1315E_ISO_EMMC_CMD,
+ RTD1315E_ISO_GPIO_6,
+ RTD1315E_ISO_GPIO_7,
+ RTD1315E_ISO_GPIO_8,
+ RTD1315E_ISO_GPIO_9,
+ RTD1315E_ISO_GPIO_10,
+ RTD1315E_ISO_GPIO_11,
+ RTD1315E_ISO_GPIO_12,
+ RTD1315E_ISO_GPIO_13,
+ RTD1315E_ISO_GPIO_14,
+ RTD1315E_ISO_GPIO_15,
+ RTD1315E_ISO_GPIO_16,
+ RTD1315E_ISO_GPIO_17,
+ RTD1315E_ISO_GPIO_18,
+ RTD1315E_ISO_GPIO_19,
+ RTD1315E_ISO_GPIO_20,
+ RTD1315E_ISO_EMMC_DATA_0,
+ RTD1315E_ISO_EMMC_DATA_1,
+ RTD1315E_ISO_EMMC_DATA_2,
+ RTD1315E_ISO_USB_CC2,
+ RTD1315E_ISO_GPIO_25,
+ RTD1315E_ISO_GPIO_26,
+ RTD1315E_ISO_GPIO_27,
+ RTD1315E_ISO_GPIO_28,
+ RTD1315E_ISO_GPIO_29,
+ RTD1315E_ISO_GPIO_30,
+ RTD1315E_ISO_GPIO_31,
+ RTD1315E_ISO_GPIO_32,
+ RTD1315E_ISO_GPIO_33,
+ RTD1315E_ISO_GPIO_34,
+ RTD1315E_ISO_GPIO_35,
+ RTD1315E_ISO_HIF_DATA,
+ RTD1315E_ISO_HIF_EN,
+ RTD1315E_ISO_HIF_RDY,
+ RTD1315E_ISO_HIF_CLK,
+ RTD1315E_ISO_GPIO_DUMMY_40,
+ RTD1315E_ISO_GPIO_DUMMY_41,
+ RTD1315E_ISO_GPIO_DUMMY_42,
+ RTD1315E_ISO_GPIO_DUMMY_43,
+ RTD1315E_ISO_GPIO_DUMMY_44,
+ RTD1315E_ISO_GPIO_DUMMY_45,
+ RTD1315E_ISO_GPIO_46,
+ RTD1315E_ISO_GPIO_47,
+ RTD1315E_ISO_GPIO_48,
+ RTD1315E_ISO_GPIO_49,
+ RTD1315E_ISO_GPIO_50,
+ RTD1315E_ISO_USB_CC1,
+ RTD1315E_ISO_EMMC_DATA_3,
+ RTD1315E_ISO_EMMC_DATA_4,
+ RTD1315E_ISO_IR_RX,
+ RTD1315E_ISO_UR0_RX,
+ RTD1315E_ISO_UR0_TX,
+ RTD1315E_ISO_GPIO_57,
+ RTD1315E_ISO_GPIO_58,
+ RTD1315E_ISO_GPIO_59,
+ RTD1315E_ISO_GPIO_60,
+ RTD1315E_ISO_GPIO_61,
+ RTD1315E_ISO_GPIO_62,
+ RTD1315E_ISO_GPIO_DUMMY_63,
+ RTD1315E_ISO_GPIO_DUMMY_64,
+ RTD1315E_ISO_GPIO_DUMMY_65,
+ RTD1315E_ISO_GPIO_66,
+ RTD1315E_ISO_GPIO_67,
+ RTD1315E_ISO_GPIO_68,
+ RTD1315E_ISO_GPIO_69,
+ RTD1315E_ISO_GPIO_70,
+ RTD1315E_ISO_GPIO_71,
+ RTD1315E_ISO_GPIO_72,
+ RTD1315E_ISO_GPIO_DUMMY_73,
+ RTD1315E_ISO_EMMC_DATA_5,
+ RTD1315E_ISO_EMMC_DATA_6,
+ RTD1315E_ISO_EMMC_DATA_7,
+ RTD1315E_ISO_GPIO_DUMMY_77,
+ RTD1315E_ISO_GPIO_78,
+ RTD1315E_ISO_GPIO_79,
+ RTD1315E_ISO_GPIO_80,
+ RTD1315E_ISO_GPIO_81,
+ RTD1315E_ISO_UR2_LOC,
+ RTD1315E_ISO_GSPI_LOC,
+ RTD1315E_ISO_HI_WIDTH,
+ RTD1315E_ISO_SF_EN,
+ RTD1315E_ISO_ARM_TRACE_DBG_EN,
+ RTD1315E_ISO_EJTAG_AUCPU_LOC,
+ RTD1315E_ISO_EJTAG_ACPU_LOC,
+ RTD1315E_ISO_EJTAG_VCPU_LOC,
+ RTD1315E_ISO_EJTAG_SCPU_LOC,
+ RTD1315E_ISO_DMIC_LOC,
+ RTD1315E_ISO_VTC_DMIC_LOC,
+ RTD1315E_ISO_VTC_TDM_LOC,
+ RTD1315E_ISO_VTC_I2SI_LOC,
+ RTD1315E_ISO_TDM_AI_LOC,
+ RTD1315E_ISO_AI_LOC,
+ RTD1315E_ISO_SPDIF_LOC,
+ RTD1315E_ISO_HIF_EN_LOC,
+ RTD1315E_ISO_SCAN_SWITCH,
+ RTD1315E_ISO_WD_RSET,
+ RTD1315E_ISO_BOOT_SEL,
+ RTD1315E_ISO_RESET_N,
+ RTD1315E_ISO_TESTMODE,
+};
+
+static const struct pinctrl_pin_desc rtd1315e_iso_pins[] = {
+ PINCTRL_PIN(RTD1315E_ISO_GPIO_0, "gpio_0"),
+ PINCTRL_PIN(RTD1315E_ISO_GPIO_1, "gpio_1"),
+ PINCTRL_PIN(RTD1315E_ISO_EMMC_RST_N, "emmc_rst_n"),
+ PINCTRL_PIN(RTD1315E_ISO_EMMC_DD_SB, "emmc_dd_sb"),
+ PINCTRL_PIN(RTD1315E_ISO_EMMC_CLK, "emmc_clk"),
+ PINCTRL_PIN(RTD1315E_ISO_EMMC_CMD, "emmc_cmd"),
+ PINCTRL_PIN(RTD1315E_ISO_GPIO_6, "gpio_6"),
+ PINCTRL_PIN(RTD1315E_ISO_GPIO_7, "gpio_7"),
+ PINCTRL_PIN(RTD1315E_ISO_GPIO_8, "gpio_8"),
+ PINCTRL_PIN(RTD1315E_ISO_GPIO_9, "gpio_9"),
+ PINCTRL_PIN(RTD1315E_ISO_GPIO_10, "gpio_10"),
+ PINCTRL_PIN(RTD1315E_ISO_GPIO_11, "gpio_11"),
+ PINCTRL_PIN(RTD1315E_ISO_GPIO_12, "gpio_12"),
+ PINCTRL_PIN(RTD1315E_ISO_GPIO_13, "gpio_13"),
+ PINCTRL_PIN(RTD1315E_ISO_GPIO_14, "gpio_14"),
+ PINCTRL_PIN(RTD1315E_ISO_GPIO_15, "gpio_15"),
+ PINCTRL_PIN(RTD1315E_ISO_GPIO_16, "gpio_16"),
+ PINCTRL_PIN(RTD1315E_ISO_GPIO_17, "gpio_17"),
+ PINCTRL_PIN(RTD1315E_ISO_GPIO_18, "gpio_18"),
+ PINCTRL_PIN(RTD1315E_ISO_GPIO_19, "gpio_19"),
+ PINCTRL_PIN(RTD1315E_ISO_GPIO_20, "gpio_20"),
+ PINCTRL_PIN(RTD1315E_ISO_EMMC_DATA_0, "emmc_data_0"),
+ PINCTRL_PIN(RTD1315E_ISO_EMMC_DATA_1, "emmc_data_1"),
+ PINCTRL_PIN(RTD1315E_ISO_EMMC_DATA_2, "emmc_data_2"),
+ PINCTRL_PIN(RTD1315E_ISO_USB_CC2, "usb_cc2"),
+ PINCTRL_PIN(RTD1315E_ISO_GPIO_25, "gpio_25"),
+ PINCTRL_PIN(RTD1315E_ISO_GPIO_26, "gpio_26"),
+ PINCTRL_PIN(RTD1315E_ISO_GPIO_27, "gpio_27"),
+ PINCTRL_PIN(RTD1315E_ISO_GPIO_28, "gpio_28"),
+ PINCTRL_PIN(RTD1315E_ISO_GPIO_29, "gpio_29"),
+ PINCTRL_PIN(RTD1315E_ISO_GPIO_30, "gpio_30"),
+ PINCTRL_PIN(RTD1315E_ISO_GPIO_31, "gpio_31"),
+ PINCTRL_PIN(RTD1315E_ISO_GPIO_32, "gpio_32"),
+ PINCTRL_PIN(RTD1315E_ISO_GPIO_33, "gpio_33"),
+ PINCTRL_PIN(RTD1315E_ISO_GPIO_34, "gpio_34"),
+ PINCTRL_PIN(RTD1315E_ISO_GPIO_35, "gpio_35"),
+ PINCTRL_PIN(RTD1315E_ISO_HIF_DATA, "hif_data"),
+ PINCTRL_PIN(RTD1315E_ISO_HIF_EN, "hif_en"),
+ PINCTRL_PIN(RTD1315E_ISO_HIF_RDY, "hif_rdy"),
+ PINCTRL_PIN(RTD1315E_ISO_HIF_CLK, "hif_clk"),
+ PINCTRL_PIN(RTD1315E_ISO_GPIO_DUMMY_40, "gpio_dummy_40"),
+ PINCTRL_PIN(RTD1315E_ISO_GPIO_DUMMY_41, "gpio_dummy_41"),
+ PINCTRL_PIN(RTD1315E_ISO_GPIO_DUMMY_42, "gpio_dummy_42"),
+ PINCTRL_PIN(RTD1315E_ISO_GPIO_DUMMY_43, "gpio_dummy_43"),
+ PINCTRL_PIN(RTD1315E_ISO_GPIO_DUMMY_44, "gpio_dummy_44"),
+ PINCTRL_PIN(RTD1315E_ISO_GPIO_DUMMY_45, "gpio_dummy_45"),
+ PINCTRL_PIN(RTD1315E_ISO_GPIO_46, "gpio_46"),
+ PINCTRL_PIN(RTD1315E_ISO_GPIO_47, "gpio_47"),
+ PINCTRL_PIN(RTD1315E_ISO_GPIO_48, "gpio_48"),
+ PINCTRL_PIN(RTD1315E_ISO_GPIO_49, "gpio_49"),
+ PINCTRL_PIN(RTD1315E_ISO_GPIO_50, "gpio_50"),
+ PINCTRL_PIN(RTD1315E_ISO_USB_CC1, "usb_cc1"),
+ PINCTRL_PIN(RTD1315E_ISO_EMMC_DATA_3, "emmc_data_3"),
+ PINCTRL_PIN(RTD1315E_ISO_EMMC_DATA_4, "emmc_data_4"),
+ PINCTRL_PIN(RTD1315E_ISO_IR_RX, "ir_rx"),
+ PINCTRL_PIN(RTD1315E_ISO_UR0_RX, "ur0_rx"),
+ PINCTRL_PIN(RTD1315E_ISO_UR0_TX, "ur0_tx"),
+ PINCTRL_PIN(RTD1315E_ISO_GPIO_57, "gpio_57"),
+ PINCTRL_PIN(RTD1315E_ISO_GPIO_58, "gpio_58"),
+ PINCTRL_PIN(RTD1315E_ISO_GPIO_59, "gpio_59"),
+ PINCTRL_PIN(RTD1315E_ISO_GPIO_60, "gpio_60"),
+ PINCTRL_PIN(RTD1315E_ISO_GPIO_61, "gpio_61"),
+ PINCTRL_PIN(RTD1315E_ISO_GPIO_62, "gpio_62"),
+ PINCTRL_PIN(RTD1315E_ISO_GPIO_DUMMY_63, "gpio_dummy_63"),
+ PINCTRL_PIN(RTD1315E_ISO_GPIO_DUMMY_64, "gpio_dummy_64"),
+ PINCTRL_PIN(RTD1315E_ISO_GPIO_DUMMY_65, "gpio_dummy_65"),
+ PINCTRL_PIN(RTD1315E_ISO_GPIO_66, "gpio_66"),
+ PINCTRL_PIN(RTD1315E_ISO_GPIO_67, "gpio_67"),
+ PINCTRL_PIN(RTD1315E_ISO_GPIO_68, "gpio_68"),
+ PINCTRL_PIN(RTD1315E_ISO_GPIO_69, "gpio_69"),
+ PINCTRL_PIN(RTD1315E_ISO_GPIO_70, "gpio_70"),
+ PINCTRL_PIN(RTD1315E_ISO_GPIO_71, "gpio_71"),
+ PINCTRL_PIN(RTD1315E_ISO_GPIO_72, "gpio_72"),
+ PINCTRL_PIN(RTD1315E_ISO_GPIO_DUMMY_73, "gpio_dummy_73"),
+ PINCTRL_PIN(RTD1315E_ISO_EMMC_DATA_5, "emmc_data_5"),
+ PINCTRL_PIN(RTD1315E_ISO_EMMC_DATA_6, "emmc_data_6"),
+ PINCTRL_PIN(RTD1315E_ISO_EMMC_DATA_7, "emmc_data_7"),
+ PINCTRL_PIN(RTD1315E_ISO_GPIO_DUMMY_77, "gpio_dummy_77"),
+ PINCTRL_PIN(RTD1315E_ISO_GPIO_78, "gpio_78"),
+ PINCTRL_PIN(RTD1315E_ISO_GPIO_79, "gpio_79"),
+ PINCTRL_PIN(RTD1315E_ISO_GPIO_80, "gpio_80"),
+ PINCTRL_PIN(RTD1315E_ISO_GPIO_81, "gpio_81"),
+ PINCTRL_PIN(RTD1315E_ISO_UR2_LOC, "ur2_loc"),
+ PINCTRL_PIN(RTD1315E_ISO_GSPI_LOC, "gspi_loc"),
+ PINCTRL_PIN(RTD1315E_ISO_HI_WIDTH, "hi_width"),
+ PINCTRL_PIN(RTD1315E_ISO_SF_EN, "sf_en"),
+ PINCTRL_PIN(RTD1315E_ISO_ARM_TRACE_DBG_EN, "arm_trace_dbg_en"),
+ PINCTRL_PIN(RTD1315E_ISO_EJTAG_AUCPU_LOC, "ejtag_aucpu_loc"),
+ PINCTRL_PIN(RTD1315E_ISO_EJTAG_ACPU_LOC, "ejtag_acpu_loc"),
+ PINCTRL_PIN(RTD1315E_ISO_EJTAG_VCPU_LOC, "ejtag_vcpu_loc"),
+ PINCTRL_PIN(RTD1315E_ISO_EJTAG_SCPU_LOC, "ejtag_scpu_loc"),
+ PINCTRL_PIN(RTD1315E_ISO_DMIC_LOC, "dmic_loc"),
+ PINCTRL_PIN(RTD1315E_ISO_VTC_DMIC_LOC, "vtc_dmic_loc"),
+ PINCTRL_PIN(RTD1315E_ISO_VTC_TDM_LOC, "vtc_tdm_loc"),
+ PINCTRL_PIN(RTD1315E_ISO_VTC_I2SI_LOC, "vtc_i2si_loc"),
+ PINCTRL_PIN(RTD1315E_ISO_TDM_AI_LOC, "tdm_ai_loc"),
+ PINCTRL_PIN(RTD1315E_ISO_AI_LOC, "ai_loc"),
+ PINCTRL_PIN(RTD1315E_ISO_SPDIF_LOC, "spdif_loc"),
+ PINCTRL_PIN(RTD1315E_ISO_HIF_EN_LOC, "hif_en_loc"),
+ PINCTRL_PIN(RTD1315E_ISO_SCAN_SWITCH, "scan_switch"),
+ PINCTRL_PIN(RTD1315E_ISO_WD_RSET, "wd_rset"),
+ PINCTRL_PIN(RTD1315E_ISO_BOOT_SEL, "boot_sel"),
+ PINCTRL_PIN(RTD1315E_ISO_RESET_N, "reset_n"),
+ PINCTRL_PIN(RTD1315E_ISO_TESTMODE, "testmode"),
+};
+
+/* Tagged as __maybe_unused since there are pins we may use in the future */
+#define DECLARE_RTD1315E_PIN(_pin, _name) \
+ static const unsigned int rtd1315e_## _name ##_pins[] __maybe_unused = { _pin }
+
+DECLARE_RTD1315E_PIN(RTD1315E_ISO_GPIO_0, gpio_0);
+DECLARE_RTD1315E_PIN(RTD1315E_ISO_GPIO_1, gpio_1);
+DECLARE_RTD1315E_PIN(RTD1315E_ISO_EMMC_RST_N, emmc_rst_n);
+DECLARE_RTD1315E_PIN(RTD1315E_ISO_EMMC_DD_SB, emmc_dd_sb);
+DECLARE_RTD1315E_PIN(RTD1315E_ISO_EMMC_CLK, emmc_clk);
+DECLARE_RTD1315E_PIN(RTD1315E_ISO_EMMC_CMD, emmc_cmd);
+DECLARE_RTD1315E_PIN(RTD1315E_ISO_GPIO_6, gpio_6);
+DECLARE_RTD1315E_PIN(RTD1315E_ISO_GPIO_7, gpio_7);
+DECLARE_RTD1315E_PIN(RTD1315E_ISO_GPIO_8, gpio_8);
+DECLARE_RTD1315E_PIN(RTD1315E_ISO_GPIO_9, gpio_9);
+DECLARE_RTD1315E_PIN(RTD1315E_ISO_GPIO_10, gpio_10);
+DECLARE_RTD1315E_PIN(RTD1315E_ISO_GPIO_11, gpio_11);
+DECLARE_RTD1315E_PIN(RTD1315E_ISO_GPIO_12, gpio_12);
+DECLARE_RTD1315E_PIN(RTD1315E_ISO_GPIO_13, gpio_13);
+DECLARE_RTD1315E_PIN(RTD1315E_ISO_GPIO_14, gpio_14);
+DECLARE_RTD1315E_PIN(RTD1315E_ISO_GPIO_15, gpio_15);
+DECLARE_RTD1315E_PIN(RTD1315E_ISO_GPIO_16, gpio_16);
+DECLARE_RTD1315E_PIN(RTD1315E_ISO_GPIO_17, gpio_17);
+DECLARE_RTD1315E_PIN(RTD1315E_ISO_GPIO_18, gpio_18);
+DECLARE_RTD1315E_PIN(RTD1315E_ISO_GPIO_19, gpio_19);
+DECLARE_RTD1315E_PIN(RTD1315E_ISO_GPIO_20, gpio_20);
+DECLARE_RTD1315E_PIN(RTD1315E_ISO_EMMC_DATA_0, emmc_data_0);
+DECLARE_RTD1315E_PIN(RTD1315E_ISO_EMMC_DATA_1, emmc_data_1);
+DECLARE_RTD1315E_PIN(RTD1315E_ISO_EMMC_DATA_2, emmc_data_2);
+DECLARE_RTD1315E_PIN(RTD1315E_ISO_USB_CC2, usb_cc2);
+DECLARE_RTD1315E_PIN(RTD1315E_ISO_GPIO_25, gpio_25);
+DECLARE_RTD1315E_PIN(RTD1315E_ISO_GPIO_26, gpio_26);
+DECLARE_RTD1315E_PIN(RTD1315E_ISO_GPIO_27, gpio_27);
+DECLARE_RTD1315E_PIN(RTD1315E_ISO_GPIO_28, gpio_28);
+DECLARE_RTD1315E_PIN(RTD1315E_ISO_GPIO_29, gpio_29);
+DECLARE_RTD1315E_PIN(RTD1315E_ISO_GPIO_30, gpio_30);
+DECLARE_RTD1315E_PIN(RTD1315E_ISO_GPIO_31, gpio_31);
+DECLARE_RTD1315E_PIN(RTD1315E_ISO_GPIO_32, gpio_32);
+DECLARE_RTD1315E_PIN(RTD1315E_ISO_GPIO_33, gpio_33);
+DECLARE_RTD1315E_PIN(RTD1315E_ISO_GPIO_34, gpio_34);
+DECLARE_RTD1315E_PIN(RTD1315E_ISO_GPIO_35, gpio_35);
+DECLARE_RTD1315E_PIN(RTD1315E_ISO_HIF_DATA, hif_data);
+DECLARE_RTD1315E_PIN(RTD1315E_ISO_HIF_EN, hif_en);
+DECLARE_RTD1315E_PIN(RTD1315E_ISO_HIF_RDY, hif_rdy);
+DECLARE_RTD1315E_PIN(RTD1315E_ISO_HIF_CLK, hif_clk);
+DECLARE_RTD1315E_PIN(RTD1315E_ISO_GPIO_DUMMY_40, gpio_dummy_40);
+DECLARE_RTD1315E_PIN(RTD1315E_ISO_GPIO_DUMMY_41, gpio_dummy_41);
+DECLARE_RTD1315E_PIN(RTD1315E_ISO_GPIO_DUMMY_42, gpio_dummy_42);
+DECLARE_RTD1315E_PIN(RTD1315E_ISO_GPIO_DUMMY_43, gpio_dummy_43);
+DECLARE_RTD1315E_PIN(RTD1315E_ISO_GPIO_DUMMY_44, gpio_dummy_44);
+DECLARE_RTD1315E_PIN(RTD1315E_ISO_GPIO_DUMMY_45, gpio_dummy_45);
+DECLARE_RTD1315E_PIN(RTD1315E_ISO_GPIO_46, gpio_46);
+DECLARE_RTD1315E_PIN(RTD1315E_ISO_GPIO_47, gpio_47);
+DECLARE_RTD1315E_PIN(RTD1315E_ISO_GPIO_48, gpio_48);
+DECLARE_RTD1315E_PIN(RTD1315E_ISO_GPIO_49, gpio_49);
+DECLARE_RTD1315E_PIN(RTD1315E_ISO_GPIO_50, gpio_50);
+DECLARE_RTD1315E_PIN(RTD1315E_ISO_USB_CC1, usb_cc1);
+DECLARE_RTD1315E_PIN(RTD1315E_ISO_EMMC_DATA_3, emmc_data_3);
+DECLARE_RTD1315E_PIN(RTD1315E_ISO_EMMC_DATA_4, emmc_data_4);
+DECLARE_RTD1315E_PIN(RTD1315E_ISO_IR_RX, ir_rx);
+DECLARE_RTD1315E_PIN(RTD1315E_ISO_UR0_RX, ur0_rx);
+DECLARE_RTD1315E_PIN(RTD1315E_ISO_UR0_TX, ur0_tx);
+DECLARE_RTD1315E_PIN(RTD1315E_ISO_GPIO_57, gpio_57);
+DECLARE_RTD1315E_PIN(RTD1315E_ISO_GPIO_58, gpio_58);
+DECLARE_RTD1315E_PIN(RTD1315E_ISO_GPIO_59, gpio_59);
+DECLARE_RTD1315E_PIN(RTD1315E_ISO_GPIO_60, gpio_60);
+DECLARE_RTD1315E_PIN(RTD1315E_ISO_GPIO_61, gpio_61);
+DECLARE_RTD1315E_PIN(RTD1315E_ISO_GPIO_62, gpio_62);
+DECLARE_RTD1315E_PIN(RTD1315E_ISO_GPIO_DUMMY_63, gpio_dummy_63);
+DECLARE_RTD1315E_PIN(RTD1315E_ISO_GPIO_DUMMY_64, gpio_dummy_64);
+DECLARE_RTD1315E_PIN(RTD1315E_ISO_GPIO_DUMMY_65, gpio_dummy_65);
+DECLARE_RTD1315E_PIN(RTD1315E_ISO_GPIO_66, gpio_66);
+DECLARE_RTD1315E_PIN(RTD1315E_ISO_GPIO_67, gpio_67);
+DECLARE_RTD1315E_PIN(RTD1315E_ISO_GPIO_68, gpio_68);
+DECLARE_RTD1315E_PIN(RTD1315E_ISO_GPIO_69, gpio_69);
+DECLARE_RTD1315E_PIN(RTD1315E_ISO_GPIO_70, gpio_70);
+DECLARE_RTD1315E_PIN(RTD1315E_ISO_GPIO_71, gpio_71);
+DECLARE_RTD1315E_PIN(RTD1315E_ISO_GPIO_72, gpio_72);
+DECLARE_RTD1315E_PIN(RTD1315E_ISO_GPIO_DUMMY_73, gpio_dummy_73);
+DECLARE_RTD1315E_PIN(RTD1315E_ISO_EMMC_DATA_5, emmc_data_5);
+DECLARE_RTD1315E_PIN(RTD1315E_ISO_EMMC_DATA_6, emmc_data_6);
+DECLARE_RTD1315E_PIN(RTD1315E_ISO_EMMC_DATA_7, emmc_data_7);
+DECLARE_RTD1315E_PIN(RTD1315E_ISO_GPIO_DUMMY_77, gpio_dummy_77);
+DECLARE_RTD1315E_PIN(RTD1315E_ISO_GPIO_78, gpio_78);
+DECLARE_RTD1315E_PIN(RTD1315E_ISO_GPIO_79, gpio_79);
+DECLARE_RTD1315E_PIN(RTD1315E_ISO_GPIO_80, gpio_80);
+DECLARE_RTD1315E_PIN(RTD1315E_ISO_GPIO_81, gpio_81);
+DECLARE_RTD1315E_PIN(RTD1315E_ISO_UR2_LOC, ur2_loc);
+DECLARE_RTD1315E_PIN(RTD1315E_ISO_GSPI_LOC, gspi_loc);
+DECLARE_RTD1315E_PIN(RTD1315E_ISO_HI_WIDTH, hi_width);
+DECLARE_RTD1315E_PIN(RTD1315E_ISO_SF_EN, sf_en);
+DECLARE_RTD1315E_PIN(RTD1315E_ISO_ARM_TRACE_DBG_EN, arm_trace_dbg_en);
+DECLARE_RTD1315E_PIN(RTD1315E_ISO_EJTAG_AUCPU_LOC, ejtag_aucpu_loc);
+DECLARE_RTD1315E_PIN(RTD1315E_ISO_EJTAG_ACPU_LOC, ejtag_acpu_loc);
+DECLARE_RTD1315E_PIN(RTD1315E_ISO_EJTAG_VCPU_LOC, ejtag_vcpu_loc);
+DECLARE_RTD1315E_PIN(RTD1315E_ISO_EJTAG_SCPU_LOC, ejtag_scpu_loc);
+DECLARE_RTD1315E_PIN(RTD1315E_ISO_DMIC_LOC, dmic_loc);
+DECLARE_RTD1315E_PIN(RTD1315E_ISO_VTC_DMIC_LOC, vtc_dmic_loc);
+DECLARE_RTD1315E_PIN(RTD1315E_ISO_VTC_TDM_LOC, vtc_tdm_loc);
+DECLARE_RTD1315E_PIN(RTD1315E_ISO_VTC_I2SI_LOC, vtc_i2si_loc);
+DECLARE_RTD1315E_PIN(RTD1315E_ISO_TDM_AI_LOC, tdm_ai_loc);
+DECLARE_RTD1315E_PIN(RTD1315E_ISO_AI_LOC, ai_loc);
+DECLARE_RTD1315E_PIN(RTD1315E_ISO_SPDIF_LOC, spdif_loc);
+DECLARE_RTD1315E_PIN(RTD1315E_ISO_HIF_EN_LOC, hif_en_loc);
+DECLARE_RTD1315E_PIN(RTD1315E_ISO_SCAN_SWITCH, scan_switch);
+DECLARE_RTD1315E_PIN(RTD1315E_ISO_WD_RSET, wd_rset);
+DECLARE_RTD1315E_PIN(RTD1315E_ISO_BOOT_SEL, boot_sel);
+DECLARE_RTD1315E_PIN(RTD1315E_ISO_RESET_N, reset_n);
+DECLARE_RTD1315E_PIN(RTD1315E_ISO_TESTMODE, testmode);
+
+#define RTD1315E_GROUP(_name) \
+ { \
+ .name = # _name, \
+ .pins = rtd1315e_ ## _name ## _pins, \
+ .num_pins = ARRAY_SIZE(rtd1315e_ ## _name ## _pins), \
+ }
+
+static const struct rtd_pin_group_desc rtd1315e_pin_groups[] = {
+ RTD1315E_GROUP(gpio_0),
+ RTD1315E_GROUP(gpio_1),
+ RTD1315E_GROUP(emmc_rst_n),
+ RTD1315E_GROUP(emmc_dd_sb),
+ RTD1315E_GROUP(emmc_clk),
+ RTD1315E_GROUP(emmc_cmd),
+ RTD1315E_GROUP(gpio_6),
+ RTD1315E_GROUP(gpio_7),
+ RTD1315E_GROUP(gpio_8),
+ RTD1315E_GROUP(gpio_9),
+ RTD1315E_GROUP(gpio_10),
+ RTD1315E_GROUP(gpio_11),
+ RTD1315E_GROUP(gpio_12),
+ RTD1315E_GROUP(gpio_13),
+ RTD1315E_GROUP(gpio_14),
+ RTD1315E_GROUP(gpio_15),
+ RTD1315E_GROUP(gpio_16),
+ RTD1315E_GROUP(gpio_17),
+ RTD1315E_GROUP(gpio_18),
+ RTD1315E_GROUP(gpio_19),
+ RTD1315E_GROUP(gpio_20),
+ RTD1315E_GROUP(emmc_data_0),
+ RTD1315E_GROUP(emmc_data_1),
+ RTD1315E_GROUP(emmc_data_2),
+ RTD1315E_GROUP(usb_cc2),
+ RTD1315E_GROUP(gpio_25),
+ RTD1315E_GROUP(gpio_26),
+ RTD1315E_GROUP(gpio_27),
+ RTD1315E_GROUP(gpio_28),
+ RTD1315E_GROUP(gpio_29),
+ RTD1315E_GROUP(gpio_30),
+ RTD1315E_GROUP(gpio_31),
+ RTD1315E_GROUP(gpio_32),
+ RTD1315E_GROUP(gpio_33),
+ RTD1315E_GROUP(gpio_34),
+ RTD1315E_GROUP(gpio_35),
+ RTD1315E_GROUP(hif_data),
+ RTD1315E_GROUP(hif_en),
+ RTD1315E_GROUP(hif_rdy),
+ RTD1315E_GROUP(hif_clk),
+ RTD1315E_GROUP(gpio_dummy_40),
+ RTD1315E_GROUP(gpio_dummy_41),
+ RTD1315E_GROUP(gpio_dummy_42),
+ RTD1315E_GROUP(gpio_dummy_43),
+ RTD1315E_GROUP(gpio_dummy_44),
+ RTD1315E_GROUP(gpio_dummy_45),
+ RTD1315E_GROUP(gpio_46),
+ RTD1315E_GROUP(gpio_47),
+ RTD1315E_GROUP(gpio_48),
+ RTD1315E_GROUP(gpio_49),
+ RTD1315E_GROUP(gpio_50),
+ RTD1315E_GROUP(usb_cc1),
+ RTD1315E_GROUP(emmc_data_3),
+ RTD1315E_GROUP(emmc_data_4),
+ RTD1315E_GROUP(ir_rx),
+ RTD1315E_GROUP(ur0_rx),
+ RTD1315E_GROUP(ur0_tx),
+ RTD1315E_GROUP(gpio_57),
+ RTD1315E_GROUP(gpio_58),
+ RTD1315E_GROUP(gpio_59),
+ RTD1315E_GROUP(gpio_60),
+ RTD1315E_GROUP(gpio_61),
+ RTD1315E_GROUP(gpio_62),
+ RTD1315E_GROUP(gpio_dummy_63),
+ RTD1315E_GROUP(gpio_dummy_64),
+ RTD1315E_GROUP(gpio_dummy_65),
+ RTD1315E_GROUP(gpio_66),
+ RTD1315E_GROUP(gpio_67),
+ RTD1315E_GROUP(gpio_68),
+ RTD1315E_GROUP(gpio_69),
+ RTD1315E_GROUP(gpio_70),
+ RTD1315E_GROUP(gpio_71),
+ RTD1315E_GROUP(gpio_72),
+ RTD1315E_GROUP(gpio_dummy_73),
+ RTD1315E_GROUP(emmc_data_5),
+ RTD1315E_GROUP(emmc_data_6),
+ RTD1315E_GROUP(emmc_data_7),
+ RTD1315E_GROUP(gpio_dummy_77),
+ RTD1315E_GROUP(gpio_78),
+ RTD1315E_GROUP(gpio_79),
+ RTD1315E_GROUP(gpio_80),
+ RTD1315E_GROUP(gpio_81),
+ RTD1315E_GROUP(ur2_loc),
+ RTD1315E_GROUP(gspi_loc),
+ RTD1315E_GROUP(hi_width),
+ RTD1315E_GROUP(sf_en),
+ RTD1315E_GROUP(arm_trace_dbg_en),
+ RTD1315E_GROUP(ejtag_aucpu_loc),
+ RTD1315E_GROUP(ejtag_acpu_loc),
+ RTD1315E_GROUP(ejtag_vcpu_loc),
+ RTD1315E_GROUP(ejtag_scpu_loc),
+ RTD1315E_GROUP(dmic_loc),
+ RTD1315E_GROUP(vtc_dmic_loc),
+ RTD1315E_GROUP(vtc_tdm_loc),
+ RTD1315E_GROUP(vtc_i2si_loc),
+ RTD1315E_GROUP(tdm_ai_loc),
+ RTD1315E_GROUP(ai_loc),
+ RTD1315E_GROUP(spdif_loc),
+ RTD1315E_GROUP(hif_en_loc),
+
+};
+
+static const char * const rtd1315e_gpio_groups[] = {
+ "gpio_0", "gpio_1", "emmc_rst_n", "emmc_dd_sb", "emmc_clk",
+ "emmc_cmd", "gpio_6", "gpio_7", "gpio_8", "gpio_9",
+ "gpio_10", "gpio_11", "gpio_12", "gpio_13", "gpio_14",
+ "gpio_15", "gpio_16", "gpio_17", "gpio_18", "gpio_19",
+ "gpio_20", "emmc_data_0", "emmc_data_1", "emmc_data_2", "usb_cc2",
+ "gpio_25", "gpio_26", "gpio_27", "gpio_28", "gpio_29",
+ "gpio_30", "gpio_31", "gpio_32", "gpio_33", "gpio_34",
+ "gpio_35", "hif_data", "hif_en", "hif_rdy", "hif_clk",
+ "gpio_46", "gpio_47", "gpio_48", "gpio_49",
+ "gpio_50", "usb_cc1", "emmc_data_3", "emmc_data_4", "ir_rx",
+ "ur0_rx", "ur0_tx", "gpio_57", "gpio_58", "gpio_59",
+ "gpio_60", "gpio_61", "gpio_62", "gpio_66", "gpio_67",
+ "gpio_68", "gpio_69", "gpio_70", "gpio_71", "gpio_72",
+ "emmc_data_5", "emmc_data_6", "emmc_data_7",
+ "gpio_78", "gpio_79", "gpio_80", "gpio_81" };
+static const char * const rtd1315e_nf_groups[] = {
+ "emmc_rst_n", "emmc_clk", "emmc_cmd", "emmc_data_0",
+ "emmc_data_1", "emmc_data_2", "emmc_data_3", "emmc_data_4",
+ "emmc_data_5", "emmc_data_6", "emmc_data_7",
+ "gpio_78", "gpio_79", "gpio_80", "gpio_81" };
+static const char * const rtd1315e_emmc_groups[] = {
+ "emmc_rst_n", "emmc_dd_sb", "emmc_clk", "emmc_cmd",
+ "emmc_data_0", "emmc_data_1", "emmc_data_2", "emmc_data_3",
+ "emmc_data_4", "emmc_data_5", "emmc_data_6", "emmc_data_7" };
+
+static const char * const rtd1315e_ao_groups[] = {
+ "gpio_66", "gpio_67", "gpio_68", "gpio_69", "gpio_70",
+ "gpio_71", "gpio_72" };
+static const char * const rtd1315e_gspi_loc0_groups[] = {
+ "gpio_18", "gpio_19", "gpio_20", "gpio_31", "gspi_loc" };
+static const char * const rtd1315e_gspi_loc1_groups[] = {
+ "gpio_8", "gpio_9", "gpio_10", "gpio_11", "gspi_loc" };
+static const char * const rtd1315e_uart0_groups[] = { "ur0_rx", "ur0_tx"};
+static const char * const rtd1315e_uart1_groups[] = {
+ "gpio_8", "gpio_9", "gpio_10", "gpio_11" };
+static const char * const rtd1315e_uart2_loc0_groups[] = {
+ "gpio_18", "gpio_19", "gpio_20", "gpio_31", "ur2_loc" };
+static const char * const rtd1315e_uart2_loc1_groups[] = {
+ "gpio_25", "gpio_26", "gpio_27", "gpio_28", "ur2_loc" };
+static const char * const rtd1315e_i2c0_groups[] = { "gpio_12", "gpio_13" };
+static const char * const rtd1315e_i2c1_groups[] = { "gpio_16", "gpio_17" };
+static const char * const rtd1315e_i2c4_groups[] = { "gpio_34", "gpio_35" };
+static const char * const rtd1315e_i2c5_groups[] = { "gpio_29", "gpio_46" };
+static const char * const rtd1315e_pcie1_groups[] = { "gpio_25" };
+static const char * const rtd1315e_etn_led_groups[] = { "gpio_14", "gpio_15" };
+static const char * const rtd1315e_etn_phy_groups[] = { "gpio_14", "gpio_15" };
+static const char * const rtd1315e_spi_groups[] = {
+ "gpio_78", "gpio_79", "gpio_80", "gpio_81" };
+static const char * const rtd1315e_pwm0_loc0_groups[] = { "gpio_26" };
+static const char * const rtd1315e_pwm0_loc1_groups[] = { "gpio_20" };
+static const char * const rtd1315e_pwm1_loc0_groups[] = { "gpio_27" };
+static const char * const rtd1315e_pwm1_loc1_groups[] = { "gpio_29" };
+
+static const char * const rtd1315e_pwm2_loc0_groups[] = { "gpio_28" };
+static const char * const rtd1315e_pwm2_loc1_groups[] = { "gpio_30" };
+static const char * const rtd1315e_pwm3_loc0_groups[] = { "gpio_47" };
+static const char * const rtd1315e_pwm3_loc1_groups[] = { "gpio_31" };
+static const char * const rtd1315e_spdif_optical_loc0_groups[] = { "gpio_20", "spdif_loc" };
+static const char * const rtd1315e_spdif_optical_loc1_groups[] = { "gpio_6", "spdif_loc" };
+static const char * const rtd1315e_usb_cc1_groups[] = { "usb_cc1" };
+static const char * const rtd1315e_usb_cc2_groups[] = { "usb_cc2" };
+
+static const char * const rtd1315e_sd_groups[] = {
+ "gpio_32", "gpio_33", "gpio_34", "gpio_35",
+ "hif_data", "hif_en", "hif_rdy", "hif_clk" };
+static const char * const rtd1315e_dmic_loc0_groups[] = {
+ "gpio_57", "gpio_58", "gpio_59", "gpio_60", "gpio_61",
+ "gpio_62", "gpio_1", "gpio_6", "dmic_loc" };
+static const char * const rtd1315e_dmic_loc1_groups[] = {
+ "gpio_32", "gpio_33", "gpio_34", "gpio_35",
+ "hif_data", "hif_en", "hif_rdy", "hif_clk",
+ "dmic_loc" };
+static const char * const rtd1315e_ai_loc0_groups[] = {
+ "gpio_57", "gpio_58", "gpio_59", "gpio_60", "gpio_61",
+ "gpio_62", "gpio_1", "ai_loc" };
+static const char * const rtd1315e_ai_loc1_groups[] = {
+ "gpio_32", "gpio_33", "gpio_34", "hif_data",
+ "hif_en", "hif_rdy", "hif_clk", "ai_loc" };
+static const char * const rtd1315e_tdm_ai_loc0_groups[] = {
+ "gpio_57", "gpio_58", "gpio_59",
+ "gpio_60", "tdm_ai_loc" };
+static const char * const rtd1315e_tdm_ai_loc1_groups[] = {
+ "hif_data", "hif_en", "hif_rdy", "hif_clk", "tdm_ai_loc" };
+static const char * const rtd1315e_hi_loc0_groups[] = {
+ "hif_data", "hif_en", "hif_rdy", "hif_clk" };
+static const char * const rtd1315e_hi_m_groups[] = {
+ "hif_data", "hif_en", "hif_rdy", "hif_clk" };
+static const char * const rtd1315e_vtc_i2so_groups[] = {
+ "gpio_67", "gpio_68", "gpio_69", "gpio_70"};
+static const char * const rtd1315e_vtc_i2si_loc0_groups[] = {
+ "gpio_57", "gpio_58", "gpio_59", "gpio_60", "gpio_61",
+ "vtc_i2si_loc" };
+static const char * const rtd1315e_vtc_i2si_loc1_groups[] = {
+ "gpio_32", "hif_data", "hif_en", "hif_rdy", "hif_clk",
+ "vtc_i2si_loc" };
+static const char * const rtd1315e_vtc_dmic_loc0_groups[] = {
+ "gpio_57", "gpio_58", "gpio_59", "gpio_60",
+ "vtc_dmic_loc" };
+static const char * const rtd1315e_vtc_dmic_loc1_groups[] = {
+ "hif_data", "hif_en", "hif_rdy", "hif_clk",
+ "vtc_dmic_loc" };
+static const char * const rtd1315e_vtc_tdm_loc0_groups[] = {
+ "gpio_57", "gpio_58", "gpio_59", "gpio_60",
+ "vtc_tdm_loc" };
+static const char * const rtd1315e_vtc_tdm_loc1_groups[] = {
+ "hif_data", "hif_en", "hif_rdy", "hif_clk",
+ "vtc_tdm_loc" };
+static const char * const rtd1315e_dc_fan_groups[] = { "gpio_47" };
+static const char * const rtd1315e_pll_test_loc0_groups[] = { "gpio_0", "gpio_1" };
+static const char * const rtd1315e_pll_test_loc1_groups[] = { "gpio_48", "gpio_49" };
+static const char * const rtd1315e_spdif_groups[] = { "gpio_50" };
+static const char * const rtd1315e_ir_rx_groups[] = { "ir_rx" };
+static const char * const rtd1315e_uart2_disable_groups[] = { "ur2_loc" };
+static const char * const rtd1315e_gspi_disable_groups[] = { "gspi_loc" };
+static const char * const rtd1315e_hi_width_disable_groups[] = { "hi_width" };
+static const char * const rtd1315e_hi_width_1bit_groups[] = { "hi_width" };
+static const char * const rtd1315e_sf_disable_groups[] = { "sf_en" };
+static const char * const rtd1315e_sf_enable_groups[] = { "sf_en" };
+static const char * const rtd1315e_scpu_ejtag_loc0_groups[] = {
+ "gpio_68", "gpio_69", "gpio_70", "gpio_71", "gpio_72",
+ "ejtag_scpu_loc" };
+static const char * const rtd1315e_scpu_ejtag_loc1_groups[] = {
+ "gpio_32", "gpio_33", "hif_data", "hif_en", "hif_clk",
+ "ejtag_scpu_loc" };
+static const char * const rtd1315e_scpu_ejtag_loc2_groups[] = {
+ "gpio_57", "gpio_58", "gpio_59", "gpio_60", "gpio_61",
+ "ejtag_scpu_loc" };
+static const char * const rtd1315e_scpu_ejtag_loc3_groups[] = {
+ "hif_data" };
+static const char * const rtd1315e_acpu_ejtag_loc0_groups[] = {
+ "gpio_68", "gpio_69", "gpio_70", "gpio_71", "gpio_72",
+ "ejtag_acpu_loc" };
+static const char * const rtd1315e_acpu_ejtag_loc1_groups[] = {
+ "gpio_32", "gpio_33", "hif_data", "hif_en", "hif_clk",
+ "ejtag_acpu_loc" };
+static const char * const rtd1315e_acpu_ejtag_loc2_groups[] = {
+ "gpio_57", "gpio_58", "gpio_59", "gpio_60", "gpio_61",
+ "ejtag_acpu_loc" };
+static const char * const rtd1315e_vcpu_ejtag_loc0_groups[] = {
+ "gpio_68", "gpio_69", "gpio_70", "gpio_71", "gpio_72",
+ "ejtag_vcpu_loc" };
+static const char * const rtd1315e_vcpu_ejtag_loc1_groups[] = {
+ "gpio_32", "gpio_33", "hif_data", "hif_en", "hif_clk",
+ "ejtag_vcpu_loc" };
+static const char * const rtd1315e_vcpu_ejtag_loc2_groups[] = {
+ "gpio_57", "gpio_58", "gpio_59", "gpio_60", "gpio_61",
+ "ejtag_vcpu_loc" };
+static const char * const rtd1315e_aucpu_ejtag_loc0_groups[] = {
+ "gpio_68", "gpio_69", "gpio_70", "gpio_71", "gpio_72",
+ "ejtag_aucpu_loc" };
+static const char * const rtd1315e_aucpu_ejtag_loc1_groups[] = {
+ "gpio_32", "gpio_33", "hif_data", "hif_en", "hif_clk",
+ "ejtag_aucpu_loc" };
+static const char * const rtd1315e_aucpu_ejtag_loc2_groups[] = {
+ "gpio_57", "gpio_58", "gpio_59", "gpio_60", "gpio_61",
+ "ejtag_aucpu_loc" };
+static const char * const rtd1315e_gpu_ejtag_groups[] = {
+ "gpio_68", "gpio_69", "gpio_70", "gpio_71", "gpio_72" };
+
+static const char * const rtd1315e_iso_tristate_groups[] = {
+ "emmc_rst_n", "emmc_dd_sb", "emmc_clk", "emmc_cmd",
+ "emmc_data_0", "emmc_data_1", "emmc_data_2", "emmc_data_3",
+ "emmc_data_4", "emmc_data_5", "emmc_data_6", "emmc_data_7",
+ "gpio_1", "gpio_7", "gpio_8", "gpio_9", "gpio_10",
+ "gpio_11", "usb_cc2", "gpio_32", "gpio_33", "hif_data",
+ "hif_en", "hif_rdy", "hif_clk", "ir_rx", "ur0_rx",
+ "ur0_tx", "gpio_66", "gpio_67", "gpio_68", "gpio_69", "gpio_70",
+ "gpio_71", "gpio_72", "gpio_78", "gpio_79", "gpio_80", "gpio_81" };
+static const char * const rtd1315e_dbg_out0_groups[] = {
+ "gpio_0", "gpio_12", "gpio_13", "gpio_16", "gpio_17", "gpio_26",
+ "gpio_27", "gpio_28", "gpio_29", "gpio_30", "gpio_34", "gpio_35",
+ "gpio_46", "gpio_48", "gpio_49", "usb_cc1", "gpio_57", "gpio_58", "gpio_59", "gpio_60" };
+static const char * const rtd1315e_dbg_out1_groups[] = {
+ "gpio_6", "gpio_14", "gpio_15", "gpio_18", "gpio_19", "gpio_20",
+ "gpio_25", "gpio_31", "gpio_47", "gpio_50", "gpio_59", "gpio_61",
+ "gpio_62" };
+static const char * const rtd1315e_standby_dbg_groups[] = {
+ "gpio_1", "gpio_6", "ir_rx" };
+static const char * const rtd1315e_arm_trace_debug_disable_groups[] = { "arm_trace_dbg_en" };
+static const char * const rtd1315e_arm_trace_debug_enable_groups[] = { "arm_trace_dbg_en" };
+static const char * const rtd1315e_aucpu_ejtag_disable_groups[] = { "ejtag_aucpu_loc" };
+static const char * const rtd1315e_acpu_ejtag_disable_groups[] = { "ejtag_acpu_loc" };
+static const char * const rtd1315e_vcpu_ejtag_disable_groups[] = { "ejtag_vcpu_loc" };
+static const char * const rtd1315e_scpu_ejtag_disable_groups[] = { "ejtag_scpu_loc" };
+static const char * const rtd1315e_vtc_dmic_loc_disable_groups[] = { "vtc_dmic_loc" };
+static const char * const rtd1315e_vtc_tdm_disable_groups[] = { "vtc_tdm_loc" };
+static const char * const rtd1315e_vtc_i2si_disable_groups[] = { "vtc_i2si_loc" };
+static const char * const rtd1315e_tdm_ai_disable_groups[] = { "tdm_ai_loc" };
+static const char * const rtd1315e_ai_disable_groups[] = { "ai_loc" };
+static const char * const rtd1315e_spdif_disable_groups[] = { "spdif_loc" };
+static const char * const rtd1315e_hif_disable_groups[] = { "hif_en_loc" };
+static const char * const rtd1315e_hif_enable_groups[] = { "hif_en_loc" };
+static const char * const rtd1315e_test_loop_groups[] = { "gpio_50" };
+static const char * const rtd1315e_pmic_pwrup_groups[] = { "gpio_78" };
+
+#define RTD1315E_FUNC(_name) \
+ { \
+ .name = # _name, \
+ .groups = rtd1315e_ ## _name ## _groups, \
+ .num_groups = ARRAY_SIZE(rtd1315e_ ## _name ## _groups), \
+ }
+
+static const struct rtd_pin_func_desc rtd1315e_pin_functions[] = {
+ RTD1315E_FUNC(gpio),
+ RTD1315E_FUNC(nf),
+ RTD1315E_FUNC(emmc),
+ RTD1315E_FUNC(ao),
+ RTD1315E_FUNC(gspi_loc0),
+ RTD1315E_FUNC(gspi_loc1),
+ RTD1315E_FUNC(uart0),
+ RTD1315E_FUNC(uart1),
+ RTD1315E_FUNC(uart2_loc0),
+ RTD1315E_FUNC(uart2_loc1),
+ RTD1315E_FUNC(i2c0),
+ RTD1315E_FUNC(i2c1),
+ RTD1315E_FUNC(i2c4),
+ RTD1315E_FUNC(i2c5),
+ RTD1315E_FUNC(pcie1),
+ RTD1315E_FUNC(etn_led),
+ RTD1315E_FUNC(etn_phy),
+ RTD1315E_FUNC(spi),
+ RTD1315E_FUNC(pwm0_loc0),
+ RTD1315E_FUNC(pwm0_loc1),
+ RTD1315E_FUNC(pwm1_loc0),
+ RTD1315E_FUNC(pwm1_loc1),
+ RTD1315E_FUNC(pwm2_loc0),
+ RTD1315E_FUNC(pwm2_loc1),
+ RTD1315E_FUNC(pwm3_loc0),
+ RTD1315E_FUNC(pwm3_loc1),
+ RTD1315E_FUNC(spdif_optical_loc0),
+ RTD1315E_FUNC(spdif_optical_loc1),
+ RTD1315E_FUNC(usb_cc1),
+ RTD1315E_FUNC(usb_cc2),
+ RTD1315E_FUNC(sd),
+ RTD1315E_FUNC(dmic_loc0),
+ RTD1315E_FUNC(dmic_loc1),
+ RTD1315E_FUNC(ai_loc0),
+ RTD1315E_FUNC(ai_loc1),
+ RTD1315E_FUNC(tdm_ai_loc0),
+ RTD1315E_FUNC(tdm_ai_loc1),
+ RTD1315E_FUNC(hi_loc0),
+ RTD1315E_FUNC(hi_m),
+ RTD1315E_FUNC(vtc_i2so),
+ RTD1315E_FUNC(vtc_i2si_loc0),
+ RTD1315E_FUNC(vtc_i2si_loc1),
+ RTD1315E_FUNC(vtc_dmic_loc0),
+ RTD1315E_FUNC(vtc_dmic_loc1),
+ RTD1315E_FUNC(vtc_tdm_loc0),
+ RTD1315E_FUNC(vtc_tdm_loc1),
+ RTD1315E_FUNC(dc_fan),
+ RTD1315E_FUNC(pll_test_loc0),
+ RTD1315E_FUNC(pll_test_loc1),
+ RTD1315E_FUNC(ir_rx),
+ RTD1315E_FUNC(uart2_disable),
+ RTD1315E_FUNC(gspi_disable),
+ RTD1315E_FUNC(hi_width_disable),
+ RTD1315E_FUNC(hi_width_1bit),
+ RTD1315E_FUNC(sf_disable),
+ RTD1315E_FUNC(sf_enable),
+ RTD1315E_FUNC(scpu_ejtag_loc0),
+ RTD1315E_FUNC(scpu_ejtag_loc1),
+ RTD1315E_FUNC(scpu_ejtag_loc2),
+ RTD1315E_FUNC(scpu_ejtag_loc3),
+ RTD1315E_FUNC(acpu_ejtag_loc0),
+ RTD1315E_FUNC(acpu_ejtag_loc1),
+ RTD1315E_FUNC(acpu_ejtag_loc2),
+ RTD1315E_FUNC(vcpu_ejtag_loc0),
+ RTD1315E_FUNC(vcpu_ejtag_loc1),
+ RTD1315E_FUNC(vcpu_ejtag_loc2),
+ RTD1315E_FUNC(aucpu_ejtag_loc0),
+ RTD1315E_FUNC(aucpu_ejtag_loc1),
+ RTD1315E_FUNC(aucpu_ejtag_loc2),
+ RTD1315E_FUNC(gpu_ejtag),
+ RTD1315E_FUNC(iso_tristate),
+ RTD1315E_FUNC(dbg_out0),
+ RTD1315E_FUNC(dbg_out1),
+ RTD1315E_FUNC(standby_dbg),
+ RTD1315E_FUNC(spdif),
+ RTD1315E_FUNC(arm_trace_debug_disable),
+ RTD1315E_FUNC(arm_trace_debug_enable),
+ RTD1315E_FUNC(aucpu_ejtag_disable),
+ RTD1315E_FUNC(acpu_ejtag_disable),
+ RTD1315E_FUNC(vcpu_ejtag_disable),
+ RTD1315E_FUNC(scpu_ejtag_disable),
+ RTD1315E_FUNC(vtc_dmic_loc_disable),
+ RTD1315E_FUNC(vtc_tdm_disable),
+ RTD1315E_FUNC(vtc_i2si_disable),
+ RTD1315E_FUNC(tdm_ai_disable),
+ RTD1315E_FUNC(ai_disable),
+ RTD1315E_FUNC(spdif_disable),
+ RTD1315E_FUNC(hif_disable),
+ RTD1315E_FUNC(hif_enable),
+ RTD1315E_FUNC(test_loop),
+ RTD1315E_FUNC(pmic_pwrup),
+};
+
+#undef RTD1315E_FUNC
+
+static const struct rtd_pin_desc rtd1315e_iso_muxes[ARRAY_SIZE(rtd1315e_iso_pins)] = {
+ [RTD1315E_ISO_EMMC_RST_N] = RTK_PIN_MUX(emmc_rst_n, 0x0, GENMASK(3, 0),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x0, 0), "gpio"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x1, 0), "nf"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x2, 0), "emmc"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0xf, 0), "iso_tristate")),
+ [RTD1315E_ISO_EMMC_DD_SB] = RTK_PIN_MUX(emmc_dd_sb, 0x0, GENMASK(7, 4),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x0, 4), "gpio"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x2, 4), "emmc"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0xf, 4), "iso_tristate")),
+ [RTD1315E_ISO_EMMC_CLK] = RTK_PIN_MUX(emmc_clk, 0x0, GENMASK(11, 8),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x0, 8), "gpio"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x1, 8), "nf"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x2, 8), "emmc"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0xf, 8), "iso_tristate")),
+ [RTD1315E_ISO_EMMC_CMD] = RTK_PIN_MUX(emmc_cmd, 0x0, GENMASK(15, 12),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x0, 12), "gpio"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x1, 12), "nf"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x2, 12), "emmc"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0xf, 12), "iso_tristate")),
+ [RTD1315E_ISO_EMMC_DATA_0] = RTK_PIN_MUX(emmc_data_0, 0x0, GENMASK(19, 16),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x0, 16), "gpio"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x1, 16), "nf"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x2, 16), "emmc"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0xf, 16), "iso_tristate")),
+ [RTD1315E_ISO_EMMC_DATA_1] = RTK_PIN_MUX(emmc_data_1, 0x0, GENMASK(23, 20),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x0, 20), "gpio"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x1, 20), "nf"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x2, 20), "emmc"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0xf, 20), "iso_tristate")),
+ [RTD1315E_ISO_EMMC_DATA_2] = RTK_PIN_MUX(emmc_data_2, 0x0, GENMASK(27, 24),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x0, 24), "gpio"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x1, 24), "nf"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x2, 24), "emmc"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0xf, 24), "iso_tristate")),
+ [RTD1315E_ISO_EMMC_DATA_3] = RTK_PIN_MUX(emmc_data_3, 0x0, GENMASK(31, 28),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x0, 28), "gpio"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x1, 28), "nf"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x2, 28), "emmc"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0xf, 28), "iso_tristate")),
+
+ [RTD1315E_ISO_EMMC_DATA_4] = RTK_PIN_MUX(emmc_data_4, 0x4, GENMASK(3, 0),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x0, 0), "gpio"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x1, 0), "nf"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x2, 0), "emmc"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0xf, 0), "iso_tristate")),
+ [RTD1315E_ISO_EMMC_DATA_5] = RTK_PIN_MUX(emmc_data_5, 0x4, GENMASK(7, 4),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x0, 4), "gpio"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x1, 4), "nf"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x2, 4), "emmc"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0xf, 4), "iso_tristate")),
+ [RTD1315E_ISO_EMMC_DATA_6] = RTK_PIN_MUX(emmc_data_6, 0x4, GENMASK(11, 8),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x0, 8), "gpio"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x1, 8), "nf"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x2, 8), "emmc"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0xf, 8), "iso_tristate")),
+ [RTD1315E_ISO_EMMC_DATA_7] = RTK_PIN_MUX(emmc_data_7, 0x4, GENMASK(15, 12),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x0, 12), "gpio"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x1, 12), "nf"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x2, 12), "emmc"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0xf, 12), "iso_tristate")),
+ [RTD1315E_ISO_GPIO_0] = RTK_PIN_MUX(gpio_0, 0x4, GENMASK(19, 16),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x0, 16), "gpio"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x2, 16), "pll_test_loc0"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0xf, 16), "dbg_out0")),
+ [RTD1315E_ISO_GPIO_1] = RTK_PIN_MUX(gpio_1, 0x4, GENMASK(23, 20),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x0, 20), "gpio"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x1, 20), "standby_dbg"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x2, 20), "pll_test_loc0"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x3, 20), "dmic_loc0"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x4, 20), "ai_loc0"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0xf, 20), "iso_tristate")),
+ [RTD1315E_ISO_GPIO_6] = RTK_PIN_MUX(gpio_6, 0x4, GENMASK(27, 24),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x0, 24), "gpio"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x1, 24), "standby_dbg"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x3, 24), "dmic_loc0"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x4, 24), "spdif_optical_loc1"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0xf, 24), "dbg_out1")),
+ [RTD1315E_ISO_GPIO_7] = RTK_PIN_MUX(gpio_7, 0x4, GENMASK(31, 28),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x0, 28), "gpio"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0xf, 28), "iso_tristate")),
+
+ [RTD1315E_ISO_GPIO_8] = RTK_PIN_MUX(gpio_8, 0x8, GENMASK(3, 0),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x0, 0), "gpio"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x1, 0), "uart1"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x3, 0), "gspi_loc1"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0xf, 0), "iso_tristate")),
+ [RTD1315E_ISO_GPIO_9] = RTK_PIN_MUX(gpio_9, 0x8, GENMASK(7, 4),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x0, 4), "gpio"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x1, 4), "uart1"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x3, 4), "gspi_loc1"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0xf, 4), "iso_tristate")),
+ [RTD1315E_ISO_GPIO_10] = RTK_PIN_MUX(gpio_10, 0x8, GENMASK(11, 8),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x0, 8), "gpio"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x1, 8), "uart1"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x3, 8), "gspi_loc1"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0xf, 8), "iso_tristate")),
+ [RTD1315E_ISO_GPIO_11] = RTK_PIN_MUX(gpio_11, 0x8, GENMASK(15, 12),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x0, 12), "gpio"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x1, 12), "uart1"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x3, 12), "gspi_loc1"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0xf, 12), "iso_tristate")),
+ [RTD1315E_ISO_GPIO_12] = RTK_PIN_MUX(gpio_12, 0x8, GENMASK(19, 16),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x0, 16), "gpio"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x1, 16), "i2c0"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0xf, 16), "dbg_out0")),
+ [RTD1315E_ISO_GPIO_13] = RTK_PIN_MUX(gpio_13, 0x8, GENMASK(23, 20),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x0, 20), "gpio"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x1, 20), "i2c0"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0xf, 20), "dbg_out0")),
+ [RTD1315E_ISO_GPIO_14] = RTK_PIN_MUX(gpio_14, 0x8, GENMASK(27, 24),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x0, 24), "gpio"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x1, 24), "etn_led"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x3, 24), "etn_phy"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0xf, 24), "dbg_out1")),
+ [RTD1315E_ISO_GPIO_15] = RTK_PIN_MUX(gpio_15, 0x8, GENMASK(31, 28),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x0, 28), "gpio"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x1, 28), "etn_led"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x3, 28), "etn_phy"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0xf, 28), "dbg_out1")),
+
+ [RTD1315E_ISO_GPIO_16] = RTK_PIN_MUX(gpio_16, 0xc, GENMASK(3, 0),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x0, 0), "gpio"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x1, 0), "i2c1"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0xf, 0), "dbg_out0")),
+ [RTD1315E_ISO_GPIO_17] = RTK_PIN_MUX(gpio_17, 0xc, GENMASK(7, 4),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x0, 4), "gpio"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x1, 4), "i2c1"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0xf, 4), "dbg_out0")),
+ [RTD1315E_ISO_GPIO_18] = RTK_PIN_MUX(gpio_18, 0xc, GENMASK(11, 8),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x0, 8), "gpio"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x1, 8), "uart2_loc0"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x3, 8), "gspi_loc0"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0xf, 8), "dbg_out1")),
+ [RTD1315E_ISO_GPIO_19] = RTK_PIN_MUX(gpio_19, 0xc, GENMASK(15, 12),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x0, 12), "gpio"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x1, 12), "uart2_loc0"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x3, 12), "gspi_loc0"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0xf, 12), "dbg_out1")),
+ [RTD1315E_ISO_GPIO_20] = RTK_PIN_MUX(gpio_20, 0xc, GENMASK(19, 16),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x0, 16), "gpio"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x1, 16), "uart2_loc0"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x2, 16), "pwm0_loc1"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x3, 16), "gspi_loc0"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x6, 16), "spdif_optical_loc0"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0xf, 16), "dbg_out1")),
+ [RTD1315E_ISO_USB_CC2] = RTK_PIN_MUX(usb_cc2, 0xc, GENMASK(23, 20),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x0, 20), "gpio"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x1, 20), "usb_cc2"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0xf, 20), "iso_tristate")),
+ [RTD1315E_ISO_GPIO_25] = RTK_PIN_MUX(gpio_25, 0xc, GENMASK(27, 24),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x0, 24), "gpio"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x1, 24), "uart2_loc1"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x4, 24), "pcie1"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0xf, 24), "dbg_out1")),
+ [RTD1315E_ISO_GPIO_26] = RTK_PIN_MUX(gpio_26, 0xc, GENMASK(31, 28),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x0, 28), "gpio"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x1, 28), "uart2_loc1"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x3, 28), "pwm0_loc0"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0xf, 28), "dbg_out0")),
+
+ [RTD1315E_ISO_GPIO_27] = RTK_PIN_MUX(gpio_27, 0x10, GENMASK(3, 0),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x0, 0), "gpio"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x1, 0), "uart2_loc1"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x3, 0), "pwm1_loc0"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0xf, 0), "dbg_out0")),
+ [RTD1315E_ISO_GPIO_28] = RTK_PIN_MUX(gpio_28, 0x10, GENMASK(7, 4),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x0, 4), "gpio"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x1, 4), "uart2_loc1"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x3, 4), "pwm2_loc0"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0xf, 4), "dbg_out0")),
+ [RTD1315E_ISO_GPIO_29] = RTK_PIN_MUX(gpio_29, 0x10, GENMASK(11, 8),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x0, 8), "gpio"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x1, 8), "i2c5"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x2, 8), "pwm1_loc1"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0xf, 8), "dbg_out0")),
+ [RTD1315E_ISO_GPIO_30] = RTK_PIN_MUX(gpio_30, 0x10, GENMASK(15, 12),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x0, 12), "gpio"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x2, 12), "pwm2_loc1"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0xf, 12), "dbg_out0")),
+ [RTD1315E_ISO_GPIO_31] = RTK_PIN_MUX(gpio_31, 0x10, GENMASK(19, 16),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x0, 16), "gpio"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x1, 16), "uart2_loc0"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x2, 16), "pwm3_loc1"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x3, 16), "gspi_loc0"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0xf, 16), "dbg_out1")),
+ [RTD1315E_ISO_GPIO_32] = RTK_PIN_MUX(gpio_32, 0x10, GENMASK(23, 20),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x0, 20), "gpio"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x1, 20), "sd"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x2, 20), "aucpu_ejtag_loc1"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x3, 20), "dmic_loc1"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x5, 20), "scpu_ejtag_loc1"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x6, 20), "acpu_ejtag_loc1"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x7, 20), "vcpu_ejtag_loc1"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x8, 20), "ai_loc1"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0xb, 20), "vtc_i2si_loc1"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0xf, 20), "iso_tristate")),
+ [RTD1315E_ISO_GPIO_33] = RTK_PIN_MUX(gpio_33, 0x10, GENMASK(27, 24),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x0, 24), "gpio"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x1, 24), "sd"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x2, 24), "aucpu_ejtag_loc1"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x3, 24), "dmic_loc1"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x5, 24), "scpu_ejtag_loc1"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x6, 24), "acpu_ejtag_loc1"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x7, 24), "vcpu_ejtag_loc1"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x8, 24), "ai_loc1"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0xf, 24), "iso_tristate")),
+ [RTD1315E_ISO_GPIO_34] = RTK_PIN_MUX(gpio_34, 0x10, GENMASK(31, 28),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x0, 28), "gpio"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x1, 28), "sd"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x3, 28), "dmic_loc1"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x5, 28), "i2c4"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x8, 28), "ai_loc1"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0xf, 28), "dbg_out0")),
+
+ [RTD1315E_ISO_GPIO_35] = RTK_PIN_MUX(gpio_35, 0x14, GENMASK(3, 0),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x0, 0), "gpio"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x1, 0), "sd"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x3, 0), "dmic_loc1"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x5, 0), "i2c4"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0xf, 0), "dbg_out0")),
+ [RTD1315E_ISO_HIF_DATA] = RTK_PIN_MUX(hif_data, 0x14, GENMASK(7, 4),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x0, 4), "gpio"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x1, 4), "sd"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x2, 4), "aucpu_ejtag_loc1"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x3, 4), "dmic_loc1"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x4, 4), "tdm_ai_loc1"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x5, 4), "scpu_ejtag_loc1"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x6, 4), "acpu_ejtag_loc1"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x7, 4), "vcpu_ejtag_loc1"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x8, 4), "ai_loc1"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x9, 4), "hi_loc0"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0xa, 4), "hi_m"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0xb, 4), "vtc_i2si_loc1"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0xc, 4), "vtc_tdm_loc1"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0xd, 4), "vtc_dmic_loc1"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0xe, 4), "scpu_ejtag_loc3"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0xf, 4), "iso_tristate")),
+ [RTD1315E_ISO_HIF_EN] = RTK_PIN_MUX(hif_en, 0x14, GENMASK(11, 8),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x0, 8), "gpio"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x1, 8), "sd"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x2, 8), "aucpu_ejtag_loc1"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x3, 8), "dmic_loc1"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x4, 8), "tdm_ai_loc1"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x5, 8), "scpu_ejtag_loc1"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x6, 8), "acpu_ejtag_loc1"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x7, 8), "vcpu_ejtag_loc1"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x8, 8), "ai_loc1"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x9, 8), "hi_loc0"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0xa, 8), "hi_m"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0xb, 8), "vtc_i2si_loc1"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0xc, 8), "vtc_tdm_loc1"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0xd, 8), "vtc_dmic_loc1"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0xf, 8), "iso_tristate")),
+ [RTD1315E_ISO_HIF_RDY] = RTK_PIN_MUX(hif_rdy, 0x14, GENMASK(15, 12),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x0, 12), "gpio"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x1, 12), "sd"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x3, 12), "dmic_loc1"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x4, 12), "tdm_ai_loc1"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x8, 12), "ai_loc1"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x9, 12), "hi_loc0"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0xa, 12), "hi_m"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0xb, 12), "vtc_i2si_loc1"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0xc, 12), "vtc_tdm_loc1"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0xd, 12), "vtc_dmic_loc1"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0xf, 12), "iso_tristate")),
+ [RTD1315E_ISO_HIF_CLK] = RTK_PIN_MUX(hif_clk, 0x14, GENMASK(19, 16),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x0, 16), "gpio"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x1, 16), "sd"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x2, 16), "aucpu_ejtag_loc1"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x3, 16), "dmic_loc1"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x4, 16), "tdm_ai_loc1"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x5, 16), "scpu_ejtag_loc1"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x6, 16), "acpu_ejtag_loc1"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x7, 16), "vcpu_ejtag_loc1"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x8, 16), "ai_loc1"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x9, 16), "hi_loc0"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0xa, 16), "hi_m"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0xb, 16), "vtc_i2si_loc1"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0xc, 16), "vtc_tdm_loc1"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0xd, 16), "vtc_dmic_loc1"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0xf, 16), "iso_tristate")),
+ [RTD1315E_ISO_GPIO_46] = RTK_PIN_MUX(gpio_46, 0x14, GENMASK(23, 20),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x0, 20), "gpio"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x1, 20), "i2c5"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0xf, 20), "dbg_out0")),
+ [RTD1315E_ISO_GPIO_47] = RTK_PIN_MUX(gpio_47, 0x14, GENMASK(27, 24),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x0, 24), "gpio"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x2, 24), "dc_fan"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x3, 24), "pwm3_loc0"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0xf, 24), "dbg_out1")),
+ [RTD1315E_ISO_GPIO_48] = RTK_PIN_MUX(gpio_48, 0x14, GENMASK(31, 28),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x0, 28), "gpio"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x1, 28), "pll_test_loc1"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0xf, 28), "dbg_out0")),
+
+ [RTD1315E_ISO_GPIO_49] = RTK_PIN_MUX(gpio_49, 0x18, GENMASK(3, 0),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x0, 0), "gpio"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x1, 0), "pll_test_loc1"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0xf, 0), "dbg_out0")),
+ [RTD1315E_ISO_GPIO_50] = RTK_PIN_MUX(gpio_50, 0x18, GENMASK(7, 4),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x0, 4), "gpio"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x1, 4), "spdif"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x5, 4), "test_loop"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0xf, 4), "dbg_out1")),
+ [RTD1315E_ISO_USB_CC1] = RTK_PIN_MUX(usb_cc1, 0x18, GENMASK(11, 8),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x0, 8), "gpio"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x1, 8), "usb_cc1"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0xf, 8), "dbg_out0")),
+ [RTD1315E_ISO_IR_RX] = RTK_PIN_MUX(ir_rx, 0x18, GENMASK(15, 12),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x0, 12), "gpio"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x1, 12), "ir_rx"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x2, 12), "standby_dbg"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0xf, 12), "iso_tristate")),
+ [RTD1315E_ISO_UR0_RX] = RTK_PIN_MUX(ur0_rx, 0x18, GENMASK(19, 16),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x0, 16), "gpio"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x1, 16), "uart0"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0xf, 16), "iso_tristate")),
+ [RTD1315E_ISO_UR0_TX] = RTK_PIN_MUX(ur0_tx, 0x18, GENMASK(23, 20),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x0, 20), "gpio"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x1, 20), "uart0"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0xf, 20), "iso_tristate")),
+ [RTD1315E_ISO_GPIO_57] = RTK_PIN_MUX(gpio_57, 0x18, GENMASK(27, 24),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x0, 24), "gpio"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x1, 24), "tdm_ai_loc0"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x2, 24), "ai_loc0"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x3, 24), "dmic_loc0"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x6, 24), "acpu_ejtag_loc2"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x7, 24), "vcpu_ejtag_loc2"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x9, 24), "aucpu_ejtag_loc2"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0xb, 24), "vtc_i2si_loc0"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0xc, 24), "vtc_tdm_loc0"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0xd, 24), "vtc_dmic_loc0"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0xe, 24), "scpu_ejtag_loc2"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0xf, 24), "dbg_out0")),
+ [RTD1315E_ISO_GPIO_58] = RTK_PIN_MUX(gpio_58, 0x18, GENMASK(31, 28),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x0, 28), "gpio"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x1, 28), "tdm_ai_loc0"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x2, 28), "ai_loc0"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x3, 28), "dmic_loc0"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x6, 28), "acpu_ejtag_loc2"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x7, 28), "vcpu_ejtag_loc2"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x9, 28), "aucpu_ejtag_loc2"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0xb, 28), "vtc_i2si_loc0"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0xc, 28), "vtc_tdm_loc0"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0xd, 28), "vtc_dmic_loc0"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0xe, 28), "scpu_ejtag_loc2"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0xf, 28), "dbg_out0")),
+
+ [RTD1315E_ISO_GPIO_59] = RTK_PIN_MUX(gpio_59, 0x1c, GENMASK(3, 0),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x0, 0), "gpio"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x1, 0), "tdm_ai_loc0"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x2, 0), "ai_loc0"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x3, 0), "dmic_loc0"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x6, 0), "acpu_ejtag_loc2"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x7, 0), "vcpu_ejtag_loc2"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x9, 0), "aucpu_ejtag_loc2"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0xb, 0), "vtc_i2si_loc0"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0xc, 0), "vtc_tdm_loc0"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0xd, 0), "vtc_dmic_loc0"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0xe, 0), "scpu_ejtag_loc2"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0xf, 0), "dbg_out1")),
+ [RTD1315E_ISO_GPIO_60] = RTK_PIN_MUX(gpio_60, 0x1c, GENMASK(7, 4),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x0, 4), "gpio"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x1, 4), "tdm_ai_loc0"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x2, 4), "ai_loc0"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x3, 4), "dmic_loc0"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x6, 4), "acpu_ejtag_loc2"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x7, 4), "vcpu_ejtag_loc2"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x9, 4), "aucpu_ejtag_loc2"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0xb, 4), "vtc_i2si_loc0"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0xc, 4), "vtc_tdm_loc0"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0xd, 4), "vtc_dmic_loc0"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0xe, 4), "scpu_ejtag_loc2"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0xf, 4), "dbg_out0")),
+ [RTD1315E_ISO_GPIO_61] = RTK_PIN_MUX(gpio_61, 0x1c, GENMASK(11, 8),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x0, 8), "gpio"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x2, 8), "ai_loc0"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x3, 8), "dmic_loc0"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x6, 8), "acpu_ejtag_loc2"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x7, 8), "vcpu_ejtag_loc2"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x9, 8), "aucpu_ejtag_loc2"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0xb, 8), "vtc_i2si_loc0"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0xe, 8), "scpu_ejtag_loc2"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0xf, 8), "dbg_out1")),
+ [RTD1315E_ISO_GPIO_62] = RTK_PIN_MUX(gpio_62, 0x1c, GENMASK(15, 12),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x0, 12), "gpio"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x2, 12), "ai_loc0"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x3, 12), "dmic_loc0"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0xf, 12), "dbg_out1")),
+ [RTD1315E_ISO_GPIO_66] = RTK_PIN_MUX(gpio_66, 0x1c, GENMASK(19, 16),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x0, 16), "gpio"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0xc, 16), "ao"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0xf, 16), "iso_tristate")),
+ [RTD1315E_ISO_GPIO_67] = RTK_PIN_MUX(gpio_67, 0x1c, GENMASK(23, 20),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x0, 20), "gpio"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0xb, 20), "vtc_i2so"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0xc, 20), "ao"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0xf, 20), "iso_tristate")),
+ [RTD1315E_ISO_GPIO_68] = RTK_PIN_MUX(gpio_68, 0x1c, GENMASK(27, 24),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x0, 24), "gpio"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x3, 24), "aucpu_ejtag_loc0"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x4, 24), "gpu_ejtag"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x5, 24), "scpu_ejtag_loc0"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x6, 24), "acpu_ejtag_loc0"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x7, 24), "vcpu_ejtag_loc0"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0xb, 24), "vtc_i2so"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0xc, 24), "ao"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0xf, 24), "iso_tristate")),
+ [RTD1315E_ISO_GPIO_69] = RTK_PIN_MUX(gpio_69, 0x1c, GENMASK(31, 28),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x0, 28), "gpio"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x3, 28), "aucpu_ejtag_loc0"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x4, 28), "gpu_ejtag"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x5, 28), "scpu_ejtag_loc0"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x6, 28), "acpu_ejtag_loc0"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x7, 28), "vcpu_ejtag_loc0"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0xb, 28), "vtc_i2so"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0xc, 28), "ao"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0xf, 28), "iso_tristate")),
+
+ [RTD1315E_ISO_GPIO_70] = RTK_PIN_MUX(gpio_70, 0x20, GENMASK(3, 0),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x0, 0), "gpio"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x3, 0), "aucpu_ejtag_loc0"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x4, 0), "gpu_ejtag"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x5, 0), "scpu_ejtag_loc0"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x6, 0), "acpu_ejtag_loc0"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x7, 0), "vcpu_ejtag_loc0"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0xb, 0), "vtc_i2so"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0xc, 0), "ao"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0xf, 0), "iso_tristate")),
+ [RTD1315E_ISO_GPIO_71] = RTK_PIN_MUX(gpio_71, 0x20, GENMASK(7, 4),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x0, 4), "gpio"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x3, 4), "aucpu_ejtag_loc0"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x4, 4), "gpu_ejtag"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x5, 4), "scpu_ejtag_loc0"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x6, 4), "acpu_ejtag_loc0"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x7, 4), "vcpu_ejtag_loc0"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0xc, 4), "ao"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0xf, 4), "iso_tristate")),
+ [RTD1315E_ISO_GPIO_72] = RTK_PIN_MUX(gpio_72, 0x20, GENMASK(11, 8),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x0, 8), "gpio"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x3, 8), "aucpu_ejtag_loc0"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x4, 8), "gpu_ejtag"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x5, 8), "scpu_ejtag_loc0"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x6, 8), "acpu_ejtag_loc0"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x7, 8), "vcpu_ejtag_loc0"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0xc, 8), "ao"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0xf, 8), "iso_tristate")),
+ [RTD1315E_ISO_GPIO_78] = RTK_PIN_MUX(gpio_78, 0x20, GENMASK(15, 12),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x0, 12), "gpio"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x1, 12), "nf"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x3, 12), "pmic_pwrup"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x5, 12), "spi"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0xf, 12), "iso_tristate")),
+ [RTD1315E_ISO_GPIO_79] = RTK_PIN_MUX(gpio_79, 0x20, GENMASK(19, 16),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x0, 16), "gpio"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x1, 16), "nf"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x5, 16), "spi"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0xf, 16), "iso_tristate")),
+ [RTD1315E_ISO_GPIO_80] = RTK_PIN_MUX(gpio_80, 0x20, GENMASK(23, 20),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x0, 20), "gpio"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x1, 20), "nf"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x5, 20), "spi"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0xf, 20), "iso_tristate")),
+ [RTD1315E_ISO_GPIO_81] = RTK_PIN_MUX(gpio_81, 0x20, GENMASK(27, 24),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x0, 24), "gpio"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x1, 24), "nf"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x5, 24), "spi"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0xf, 24), "iso_tristate")),
+
+ [RTD1315E_ISO_UR2_LOC] = RTK_PIN_MUX(ur2_loc, 0x120, GENMASK(1, 0),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x0, 0), "uart2_disable"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x1, 0), "uart2_loc0"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x2, 0), "uart2_loc1")),
+ [RTD1315E_ISO_GSPI_LOC] = RTK_PIN_MUX(gspi_loc, 0x120, GENMASK(3, 2),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x0, 2), "gspi_disable"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x1, 2), "gspi_loc0"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x2, 2), "gspi_loc1")),
+ [RTD1315E_ISO_HI_WIDTH] = RTK_PIN_MUX(hi_width, 0x120, GENMASK(9, 8),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x0, 8), "hi_width_disable"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x1, 8), "hi_width_1bit")),
+ [RTD1315E_ISO_SF_EN] = RTK_PIN_MUX(sf_en, 0x120, GENMASK(11, 11),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x0, 11), "sf_disable"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x1, 11), "sf_enable")),
+ [RTD1315E_ISO_ARM_TRACE_DBG_EN] = RTK_PIN_MUX(arm_trace_dbg_en, 0x120, GENMASK(12, 12),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x0, 12), "arm_trace_debug_disable"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x1, 12), "arm_trace_debug_enable")),
+ [RTD1315E_ISO_EJTAG_AUCPU_LOC] = RTK_PIN_MUX(ejtag_aucpu_loc, 0x120, GENMASK(16, 14),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x0, 14), "aucpu_ejtag_disable"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x1, 14), "aucpu_ejtag_loc0"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x2, 14), "aucpu_ejtag_loc1"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x4, 14), "aucpu_ejtag_loc2")),
+ [RTD1315E_ISO_EJTAG_ACPU_LOC] = RTK_PIN_MUX(ejtag_acpu_loc, 0x120, GENMASK(19, 17),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x0, 17), "acpu_ejtag_disable"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x1, 17), "acpu_ejtag_loc0"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x2, 17), "acpu_ejtag_loc1"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x4, 17), "acpu_ejtag_loc2")),
+ [RTD1315E_ISO_EJTAG_VCPU_LOC] = RTK_PIN_MUX(ejtag_vcpu_loc, 0x120, GENMASK(22, 20),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x0, 20), "vcpu_ejtag_disable"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x1, 20), "vcpu_ejtag_loc0"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x2, 20), "vcpu_ejtag_loc1"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x4, 20), "vcpu_ejtag_loc2")),
+ [RTD1315E_ISO_EJTAG_SCPU_LOC] = RTK_PIN_MUX(ejtag_scpu_loc, 0x120, GENMASK(25, 23),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x0, 23), "scpu_ejtag_disable"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x1, 23), "scpu_ejtag_loc0"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x2, 23), "scpu_ejtag_loc1"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x4, 23), "scpu_ejtag_loc2")),
+ [RTD1315E_ISO_DMIC_LOC] = RTK_PIN_MUX(dmic_loc, 0x120, GENMASK(27, 26),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x1, 26), "dmic_loc0"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x2, 26), "dmic_loc1")),
+
+ [RTD1315E_ISO_VTC_DMIC_LOC] = RTK_PIN_MUX(vtc_dmic_loc, 0x128, GENMASK(1, 0),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x0, 0), "vtc_dmic_loc_disable"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x1, 0), "vtc_dmic_loc0"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x2, 0), "vtc_dmic_loc1")),
+ [RTD1315E_ISO_VTC_TDM_LOC] = RTK_PIN_MUX(vtc_tdm_loc, 0x128, GENMASK(3, 2),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x0, 2), "vtc_tdm_disable"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x1, 2), "vtc_tdm_loc0"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x2, 2), "vtc_tdm_loc1")),
+ [RTD1315E_ISO_VTC_I2SI_LOC] = RTK_PIN_MUX(vtc_i2si_loc, 0x128, GENMASK(5, 4),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x0, 4), "vtc_i2si_disable"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x1, 4), "vtc_i2si_loc0"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x2, 4), "vtc_i2si_loc1")),
+ [RTD1315E_ISO_TDM_AI_LOC] = RTK_PIN_MUX(tdm_ai_loc, 0x128, GENMASK(7, 6),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x0, 6), "tdm_ai_disable"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x1, 6), "tdm_ai_loc0"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x2, 6), "tdm_ai_loc1")),
+ [RTD1315E_ISO_AI_LOC] = RTK_PIN_MUX(ai_loc, 0x128, GENMASK(9, 8),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x0, 8), "ai_disable"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x1, 8), "ai_loc0"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x2, 8), "ai_loc1")),
+ [RTD1315E_ISO_SPDIF_LOC] = RTK_PIN_MUX(spdif_loc, 0x128, GENMASK(11, 10),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x0, 10), "spdif_disable"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x1, 10), "spdif_optical_loc0"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x2, 10), "spdif_optical_loc1")),
+
+ [RTD1315E_ISO_HIF_EN_LOC] = RTK_PIN_MUX(hif_en_loc, 0x12c, GENMASK(2, 0),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x2, 0), "hif_disable"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x5, 0), "hif_enable")),
+};
+
+static const struct rtd_pin_config_desc rtd1315e_iso_configs[ARRAY_SIZE(rtd1315e_iso_pins)] = {
+ [RTD1315E_ISO_BOOT_SEL] = RTK_PIN_CONFIG(boot_sel, 0x24, 0, 0, 1, NA, 2, 3, NA),
+ [RTD1315E_ISO_EMMC_CLK] = RTK_PIN_CONFIG(emmc_clk, 0x24, 4, 0, 1, NA, 2, 12, NA),
+ [RTD1315E_ISO_EMMC_CMD] = RTK_PIN_CONFIG(emmc_cmd, 0x24, 17, 0, 1, NA, 2, 13, NA),
+ [RTD1315E_ISO_EMMC_DATA_0] = RTK_PIN_CONFIG(emmc_data_0, 0x28, 0, 0, 1, NA, 2, 12, NA),
+ [RTD1315E_ISO_EMMC_DATA_1] = RTK_PIN_CONFIG(emmc_data_1, 0x28, 13, 0, 1, NA, 2, 12, NA),
+ [RTD1315E_ISO_EMMC_DATA_2] = RTK_PIN_CONFIG(emmc_data_2, 0x2c, 0, 0, 1, NA, 2, 12, NA),
+ [RTD1315E_ISO_EMMC_DATA_3] = RTK_PIN_CONFIG(emmc_data_3, 0x2c, 13, 0, 1, NA, 2, 12, NA),
+ [RTD1315E_ISO_EMMC_DATA_4] = RTK_PIN_CONFIG(emmc_data_4, 0x30, 0, 0, 1, NA, 2, 12, NA),
+ [RTD1315E_ISO_EMMC_DATA_5] = RTK_PIN_CONFIG(emmc_data_5, 0x30, 13, 0, 1, NA, 2, 12, NA),
+ [RTD1315E_ISO_EMMC_DATA_6] = RTK_PIN_CONFIG(emmc_data_6, 0x34, 0, 0, 1, NA, 2, 12, NA),
+ [RTD1315E_ISO_EMMC_DATA_7] = RTK_PIN_CONFIG(emmc_data_7, 0x34, 13, 0, 1, NA, 2, 12, NA),
+ [RTD1315E_ISO_EMMC_DD_SB] = RTK_PIN_CONFIG(emmc_dd_sb, 0x38, 0, 0, 1, NA, 2, 12, NA),
+ [RTD1315E_ISO_EMMC_RST_N] = RTK_PIN_CONFIG(emmc_rst_n, 0x38, 13, 0, 1, NA, 2, 12, NA),
+ [RTD1315E_ISO_GPIO_1] = RTK_PIN_CONFIG(gpio_1, 0x3c, 0, 1, 2, 0, 3, 4, PADDRI_4_8),
+ [RTD1315E_ISO_GPIO_6] = RTK_PIN_CONFIG(gpio_6, 0x3c, 5, 1, 2, 0, 3, 4, PADDRI_4_8),
+ [RTD1315E_ISO_GPIO_7] = RTK_PIN_CONFIG(gpio_7, 0x3c, 10, 1, 2, 0, 3, 4, PADDRI_4_8),
+ [RTD1315E_ISO_GPIO_8] = RTK_PIN_CONFIG(gpio_8, 0x3c, 15, 1, 2, 0, 3, 4, PADDRI_4_8),
+ [RTD1315E_ISO_GPIO_9] = RTK_PIN_CONFIG(gpio_9, 0x3c, 20, 1, 2, 0, 3, 4, PADDRI_4_8),
+ [RTD1315E_ISO_GPIO_10] = RTK_PIN_CONFIG(gpio_10, 0x3c, 25, 1, 2, 0, 3, 4, PADDRI_4_8),
+ [RTD1315E_ISO_GPIO_11] = RTK_PIN_CONFIG(gpio_11, 0x40, 0, 1, 2, 0, 3, 4, PADDRI_4_8),
+ [RTD1315E_ISO_GPIO_12] = RTK_PIN_CONFIG(gpio_12, 0x40, 5, 1, 2, 0, 3, 4, PADDRI_4_8),
+ [RTD1315E_ISO_GPIO_13] = RTK_PIN_CONFIG(gpio_13, 0x40, 10, 1, 2, 0, 3, 4, PADDRI_4_8),
+ [RTD1315E_ISO_GPIO_14] = RTK_PIN_CONFIG(gpio_14, 0x40, 15, 1, 2, 0, 3, 4, PADDRI_4_8),
+ [RTD1315E_ISO_GPIO_15] = RTK_PIN_CONFIG(gpio_15, 0x40, 20, 1, 2, 0, 3, 4, PADDRI_4_8),
+ [RTD1315E_ISO_GPIO_16] = RTK_PIN_CONFIG(gpio_16, 0x40, 25, 1, 2, 0, 3, 4, PADDRI_4_8),
+ [RTD1315E_ISO_GPIO_17] = RTK_PIN_CONFIG(gpio_17, 0x44, 0, 1, 2, 0, 3, 4, PADDRI_4_8),
+ [RTD1315E_ISO_GPIO_18] = RTK_PIN_CONFIG(gpio_18, 0x44, 5, 1, 2, 0, 3, 4, PADDRI_4_8),
+ [RTD1315E_ISO_GPIO_19] = RTK_PIN_CONFIG(gpio_19, 0x44, 10, 1, 2, 0, 3, 4, PADDRI_4_8),
+ [RTD1315E_ISO_GPIO_20] = RTK_PIN_CONFIG(gpio_20, 0x44, 15, 1, 2, 0, 3, 4, PADDRI_4_8),
+ [RTD1315E_ISO_GPIO_25] = RTK_PIN_CONFIG(gpio_25, 0x44, 20, 1, 2, 0, 3, 4, PADDRI_4_8),
+ [RTD1315E_ISO_GPIO_26] = RTK_PIN_CONFIG(gpio_26, 0x44, 25, 1, 2, 0, 3, 4, PADDRI_4_8),
+ [RTD1315E_ISO_GPIO_27] = RTK_PIN_CONFIG(gpio_27, 0x48, 0, 1, 2, 0, 3, 4, PADDRI_4_8),
+ [RTD1315E_ISO_GPIO_28] = RTK_PIN_CONFIG(gpio_28, 0x48, 6, 1, 2, 0, 3, 4, PADDRI_4_8),
+ [RTD1315E_ISO_GPIO_29] = RTK_PIN_CONFIG(gpio_29, 0x48, 12, 1, 2, 0, 3, 4, PADDRI_4_8),
+ [RTD1315E_ISO_GPIO_30] = RTK_PIN_CONFIG(gpio_30, 0x48, 17, 1, 2, 0, 3, 4, PADDRI_4_8),
+ [RTD1315E_ISO_GPIO_31] = RTK_PIN_CONFIG(gpio_31, 0x4c, 0, 1, 2, 0, 3, 4, PADDRI_4_8),
+ [RTD1315E_ISO_GPIO_32] = RTK_PIN_CONFIG(gpio_32, 0x4c, 5, 0, 1, NA, 2, 12, NA),
+ [RTD1315E_ISO_GPIO_33] = RTK_PIN_CONFIG(gpio_33, 0x4c, 18, 0, 1, NA, 2, 12, NA),
+ [RTD1315E_ISO_GPIO_34] = RTK_PIN_CONFIG(gpio_34, 0x50, 0, 1, 2, 0, 3, 4, PADDRI_4_8),
+ [RTD1315E_ISO_GPIO_35] = RTK_PIN_CONFIG(gpio_35, 0x50, 5, 1, 2, 0, 3, 4, PADDRI_4_8),
+ [RTD1315E_ISO_GPIO_46] = RTK_PIN_CONFIG(gpio_46, 0x50, 10, 1, 2, 0, 3, 4, PADDRI_4_8),
+ [RTD1315E_ISO_GPIO_47] = RTK_PIN_CONFIG(gpio_47, 0x50, 15, 1, 2, 0, 3, 4, PADDRI_4_8),
+ [RTD1315E_ISO_GPIO_48] = RTK_PIN_CONFIG(gpio_48, 0x50, 20, 1, 2, 0, 3, 4, PADDRI_4_8),
+ [RTD1315E_ISO_GPIO_49] = RTK_PIN_CONFIG(gpio_49, 0x50, 25, 1, 2, 0, 3, 4, PADDRI_4_8),
+ [RTD1315E_ISO_GPIO_50] = RTK_PIN_CONFIG(gpio_50, 0x54, 0, 1, 2, 0, 3, 4, PADDRI_4_8),
+ [RTD1315E_ISO_GPIO_57] = RTK_PIN_CONFIG(gpio_57, 0x54, 5, 1, 2, 0, 3, 4, PADDRI_4_8),
+ [RTD1315E_ISO_GPIO_58] = RTK_PIN_CONFIG(gpio_58, 0x54, 10, 1, 2, 0, 3, 4, PADDRI_4_8),
+ [RTD1315E_ISO_GPIO_59] = RTK_PIN_CONFIG(gpio_59, 0x54, 15, 1, 2, 0, 3, 4, PADDRI_4_8),
+ [RTD1315E_ISO_GPIO_60] = RTK_PIN_CONFIG(gpio_60, 0x54, 20, 1, 2, 0, 3, 4, PADDRI_4_8),
+ [RTD1315E_ISO_GPIO_61] = RTK_PIN_CONFIG(gpio_61, 0x54, 25, 1, 2, 0, 3, 4, PADDRI_4_8),
+ [RTD1315E_ISO_GPIO_62] = RTK_PIN_CONFIG(gpio_62, 0x58, 0, 1, 2, 0, 3, 4, PADDRI_4_8),
+ [RTD1315E_ISO_GPIO_66] = RTK_PIN_CONFIG(gpio_66, 0x58, 5, 1, 2, 0, 3, 4, PADDRI_4_8),
+ [RTD1315E_ISO_GPIO_67] = RTK_PIN_CONFIG(gpio_67, 0x58, 10, 1, 2, 0, 3, 4, PADDRI_4_8),
+ [RTD1315E_ISO_GPIO_68] = RTK_PIN_CONFIG(gpio_68, 0x58, 15, 1, 2, 0, 3, 4, PADDRI_4_8),
+ [RTD1315E_ISO_GPIO_69] = RTK_PIN_CONFIG(gpio_69, 0x58, 20, 1, 2, 0, 3, 4, PADDRI_4_8),
+ [RTD1315E_ISO_GPIO_70] = RTK_PIN_CONFIG(gpio_70, 0x58, 25, 1, 2, 0, 3, 4, PADDRI_4_8),
+ [RTD1315E_ISO_GPIO_71] = RTK_PIN_CONFIG(gpio_71, 0x5c, 0, 1, 2, 0, 3, 4, PADDRI_4_8),
+ [RTD1315E_ISO_GPIO_72] = RTK_PIN_CONFIG(gpio_72, 0x5c, 5, 1, 2, 0, 3, 4, PADDRI_4_8),
+ [RTD1315E_ISO_GPIO_78] = RTK_PIN_CONFIG(gpio_78, 0x5c, 10, 0, 1, NA, 2, 12, NA),
+ [RTD1315E_ISO_GPIO_79] = RTK_PIN_CONFIG(gpio_79, 0x60, 0, 0, 1, NA, 2, 12, NA),
+ [RTD1315E_ISO_GPIO_80] = RTK_PIN_CONFIG(gpio_80, 0x60, 13, 0, 1, NA, 2, 12, NA),
+ [RTD1315E_ISO_GPIO_81] = RTK_PIN_CONFIG(gpio_81, 0x64, 0, 0, 1, NA, 2, 12, NA),
+ [RTD1315E_ISO_HIF_CLK] = RTK_PIN_CONFIG(hif_clk, 0x64, 13, 0, 1, NA, 2, 12, NA),
+ [RTD1315E_ISO_HIF_DATA] = RTK_PIN_CONFIG(hif_data, 0x68, 0, 0, 1, NA, 2, 12, NA),
+ [RTD1315E_ISO_HIF_EN] = RTK_PIN_CONFIG(hif_en, 0x68, 13, 0, 1, NA, 2, 12, NA),
+ [RTD1315E_ISO_HIF_RDY] = RTK_PIN_CONFIG(hif_rdy, 0x68, 26, 0, 1, NA, 2, 12, NA),
+ [RTD1315E_ISO_IR_RX] = RTK_PIN_CONFIG(ir_rx, 0x6c, 7, 1, 2, 0, 3, 4, PADDRI_4_8),
+ [RTD1315E_ISO_RESET_N] = RTK_PIN_CONFIG(reset_n, 0x6c, 12, 0, 1, NA, 2, 3, PADDRI_4_8),
+ [RTD1315E_ISO_SCAN_SWITCH] = RTK_PIN_CONFIG(scan_switch, 0x6c, 16, NA, NA, 0, 1, 2, PADDRI_4_8),
+ [RTD1315E_ISO_TESTMODE] = RTK_PIN_CONFIG(testmode, 0x6c, 19, 0, 1, NA, 2, 3, PADDRI_4_8),
+ [RTD1315E_ISO_UR0_RX] = RTK_PIN_CONFIG(ur0_rx, 0x6c, 23, 1, 2, 0, 3, 4, PADDRI_4_8),
+ [RTD1315E_ISO_UR0_TX] = RTK_PIN_CONFIG(ur0_tx, 0x6c, 28, 1, 2, 0, 3, 4, PADDRI_4_8),
+ [RTD1315E_ISO_USB_CC1] = RTK_PIN_CONFIG(usb_cc1, 0x70, 1, NA, NA, 0, 1, 2, PADDRI_4_8),
+ [RTD1315E_ISO_USB_CC2] = RTK_PIN_CONFIG(usb_cc2, 0x70, 4, NA, NA, 0, 1, 2, PADDRI_4_8),
+ [RTD1315E_ISO_WD_RSET] = RTK_PIN_CONFIG(wd_rset, 0x70, 7, 1, 2, 0, 3, 4, PADDRI_4_8),
+};
+
+static const struct rtd_pin_sconfig_desc rtd1315e_iso_sconfigs[] = {
+ RTK_PIN_SCONFIG(emmc_clk, 0x24, 7, 3, 10, 3, 13, 3),
+ RTK_PIN_SCONFIG(emmc_cmd, 0x24, 20, 3, 23, 3, 26, 3),
+ RTK_PIN_SCONFIG(emmc_data_0, 0x28, 3, 3, 6, 3, 9, 3),
+ RTK_PIN_SCONFIG(emmc_data_1, 0x28, 16, 3, 19, 3, 22, 3),
+ RTK_PIN_SCONFIG(emmc_data_2, 0x2c, 3, 3, 6, 3, 9, 3),
+ RTK_PIN_SCONFIG(emmc_data_3, 0x2c, 16, 3, 19, 3, 22, 3),
+ RTK_PIN_SCONFIG(emmc_data_4, 0x30, 3, 3, 6, 3, 9, 3),
+ RTK_PIN_SCONFIG(emmc_data_5, 0x30, 16, 3, 19, 3, 22, 3),
+ RTK_PIN_SCONFIG(emmc_data_6, 0x34, 3, 3, 6, 3, 9, 3),
+ RTK_PIN_SCONFIG(emmc_data_7, 0x34, 16, 3, 19, 3, 22, 3),
+ RTK_PIN_SCONFIG(emmc_dd_sb, 0x38, 3, 3, 6, 3, 9, 3),
+ RTK_PIN_SCONFIG(emmc_rst_n, 0x38, 16, 3, 19, 3, 22, 3),
+ RTK_PIN_SCONFIG(gpio_32, 0x4c, 8, 3, 11, 3, 14, 3),
+ RTK_PIN_SCONFIG(gpio_33, 0x4c, 21, 3, 24, 3, 27, 3),
+ RTK_PIN_SCONFIG(gpio_78, 0x5c, 13, 3, 16, 3, 19, 3),
+ RTK_PIN_SCONFIG(gpio_79, 0x60, 3, 3, 6, 3, 9, 3),
+ RTK_PIN_SCONFIG(gpio_80, 0x60, 16, 3, 19, 3, 22, 3),
+ RTK_PIN_SCONFIG(gpio_81, 0x64, 3, 3, 6, 3, 9, 3),
+ RTK_PIN_SCONFIG(hif_clk, 0x64, 16, 3, 19, 3, 22, 3),
+ RTK_PIN_SCONFIG(hif_data, 0x68, 3, 3, 6, 3, 9, 3),
+ RTK_PIN_SCONFIG(hif_en, 0x68, 16, 3, 19, 3, 22, 3),
+ RTK_PIN_SCONFIG(hif_rdy, 0x68, 29, 3, 32, 3, 35, 3),
+
+};
+
+static const struct rtd_pinctrl_desc rtd1315e_iso_pinctrl_desc = {
+ .pins = rtd1315e_iso_pins,
+ .num_pins = ARRAY_SIZE(rtd1315e_iso_pins),
+ .groups = rtd1315e_pin_groups,
+ .num_groups = ARRAY_SIZE(rtd1315e_pin_groups),
+ .functions = rtd1315e_pin_functions,
+ .num_functions = ARRAY_SIZE(rtd1315e_pin_functions),
+ .muxes = rtd1315e_iso_muxes,
+ .num_muxes = ARRAY_SIZE(rtd1315e_iso_muxes),
+ .configs = rtd1315e_iso_configs,
+ .num_configs = ARRAY_SIZE(rtd1315e_iso_configs),
+ .sconfigs = rtd1315e_iso_sconfigs,
+ .num_sconfigs = ARRAY_SIZE(rtd1315e_iso_sconfigs),
+};
+
+static int rtd1315e_pinctrl_probe(struct platform_device *pdev)
+{
+ return rtd_pinctrl_probe(pdev, &rtd1315e_iso_pinctrl_desc);
+}
+
+static const struct of_device_id rtd1315e_pinctrl_of_match[] = {
+ { .compatible = "realtek,rtd1315e-pinctrl", },
+ {},
+};
+
+static struct platform_driver rtd1315e_pinctrl_driver = {
+ .driver = {
+ .name = "rtd1315e-pinctrl",
+ .of_match_table = rtd1315e_pinctrl_of_match,
+ },
+ .probe = rtd1315e_pinctrl_probe,
+};
+
+static int __init rtd1315e_pinctrl_init(void)
+{
+ return platform_driver_register(&rtd1315e_pinctrl_driver);
+}
+arch_initcall(rtd1315e_pinctrl_init);
+
+static void __exit rtd1315e_pinctrl_exit(void)
+{
+ platform_driver_unregister(&rtd1315e_pinctrl_driver);
+}
+module_exit(rtd1315e_pinctrl_exit);
+
+MODULE_LICENSE("GPL");
+MODULE_AUTHOR("Realtek Semiconductor Corporation");
+MODULE_DESCRIPTION("Realtek DHC SoC RTD1315E pinctrl driver");
diff --git a/drivers/pinctrl/realtek/pinctrl-rtd1319d.c b/drivers/pinctrl/realtek/pinctrl-rtd1319d.c
new file mode 100644
index 0000000000..b1a654ac30
--- /dev/null
+++ b/drivers/pinctrl/realtek/pinctrl-rtd1319d.c
@@ -0,0 +1,1610 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Realtek DHC 1319D pin controller driver
+ *
+ * Copyright (c) 2023 Realtek Semiconductor Corp.
+ *
+ */
+
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/platform_device.h>
+#include <linux/pinctrl/pinctrl.h>
+
+#include "pinctrl-rtd.h"
+
+enum rtd13xxd_iso_pins {
+ RTD1319D_ISO_GPIO_0 = 0,
+ RTD1319D_ISO_GPIO_1,
+ RTD1319D_ISO_GPIO_2,
+ RTD1319D_ISO_GPIO_3,
+ RTD1319D_ISO_GPIO_4,
+ RTD1319D_ISO_GPIO_5,
+ RTD1319D_ISO_GPIO_6,
+ RTD1319D_ISO_GPIO_7,
+ RTD1319D_ISO_GPIO_8,
+ RTD1319D_ISO_GPIO_9,
+ RTD1319D_ISO_GPIO_10,
+ RTD1319D_ISO_GPIO_11,
+ RTD1319D_ISO_GPIO_12,
+ RTD1319D_ISO_GPIO_13,
+ RTD1319D_ISO_GPIO_14,
+ RTD1319D_ISO_GPIO_15,
+ RTD1319D_ISO_GPIO_16,
+ RTD1319D_ISO_GPIO_17,
+ RTD1319D_ISO_GPIO_18,
+ RTD1319D_ISO_GPIO_19,
+ RTD1319D_ISO_GPIO_20,
+ RTD1319D_ISO_GPIO_21,
+ RTD1319D_ISO_GPIO_22,
+ RTD1319D_ISO_GPIO_23,
+ RTD1319D_ISO_USB_CC2,
+ RTD1319D_ISO_GPIO_25,
+ RTD1319D_ISO_GPIO_26,
+ RTD1319D_ISO_GPIO_27,
+ RTD1319D_ISO_GPIO_28,
+ RTD1319D_ISO_GPIO_29,
+ RTD1319D_ISO_GPIO_30,
+ RTD1319D_ISO_GPIO_31,
+ RTD1319D_ISO_GPIO_32,
+ RTD1319D_ISO_GPIO_33,
+ RTD1319D_ISO_GPIO_34,
+ RTD1319D_ISO_GPIO_35,
+ RTD1319D_ISO_HIF_DATA,
+ RTD1319D_ISO_HIF_EN,
+ RTD1319D_ISO_HIF_RDY,
+ RTD1319D_ISO_HIF_CLK,
+ RTD1319D_ISO_GPIO_40,
+ RTD1319D_ISO_GPIO_41,
+ RTD1319D_ISO_GPIO_42,
+ RTD1319D_ISO_GPIO_43,
+ RTD1319D_ISO_GPIO_44,
+ RTD1319D_ISO_GPIO_45,
+ RTD1319D_ISO_GPIO_46,
+ RTD1319D_ISO_GPIO_47,
+ RTD1319D_ISO_GPIO_48,
+ RTD1319D_ISO_GPIO_49,
+ RTD1319D_ISO_GPIO_50,
+ RTD1319D_ISO_USB_CC1,
+ RTD1319D_ISO_GPIO_52,
+ RTD1319D_ISO_GPIO_53,
+ RTD1319D_ISO_IR_RX,
+ RTD1319D_ISO_UR0_RX,
+ RTD1319D_ISO_UR0_TX,
+ RTD1319D_ISO_GPIO_57,
+ RTD1319D_ISO_GPIO_58,
+ RTD1319D_ISO_GPIO_59,
+ RTD1319D_ISO_GPIO_60,
+ RTD1319D_ISO_GPIO_61,
+ RTD1319D_ISO_GPIO_62,
+ RTD1319D_ISO_GPIO_63,
+ RTD1319D_ISO_GPIO_64,
+ RTD1319D_ISO_EMMC_RST_N,
+ RTD1319D_ISO_EMMC_DD_SB,
+ RTD1319D_ISO_EMMC_CLK,
+ RTD1319D_ISO_EMMC_CMD,
+ RTD1319D_ISO_EMMC_DATA_0,
+ RTD1319D_ISO_EMMC_DATA_1,
+ RTD1319D_ISO_EMMC_DATA_2,
+ RTD1319D_ISO_EMMC_DATA_3,
+ RTD1319D_ISO_EMMC_DATA_4,
+ RTD1319D_ISO_EMMC_DATA_5,
+ RTD1319D_ISO_EMMC_DATA_6,
+ RTD1319D_ISO_EMMC_DATA_7,
+ RTD1319D_ISO_GPIO_DUMMY_77,
+ RTD1319D_ISO_GPIO_78,
+ RTD1319D_ISO_GPIO_79,
+ RTD1319D_ISO_GPIO_80,
+ RTD1319D_ISO_GPIO_81,
+ RTD1319D_ISO_UR2_LOC,
+ RTD1319D_ISO_GSPI_LOC,
+ RTD1319D_ISO_HI_WIDTH,
+ RTD1319D_ISO_SF_EN,
+ RTD1319D_ISO_ARM_TRACE_DBG_EN,
+ RTD1319D_ISO_EJTAG_AUCPU_LOC,
+ RTD1319D_ISO_EJTAG_ACPU_LOC,
+ RTD1319D_ISO_EJTAG_VCPU_LOC,
+ RTD1319D_ISO_EJTAG_SCPU_LOC,
+ RTD1319D_ISO_DMIC_LOC,
+ RTD1319D_ISO_EJTAG_SECPU_LOC,
+ RTD1319D_ISO_VTC_DMIC_LOC,
+ RTD1319D_ISO_VTC_TDM_LOC,
+ RTD1319D_ISO_VTC_I2SI_LOC,
+ RTD1319D_ISO_TDM_AI_LOC,
+ RTD1319D_ISO_AI_LOC,
+ RTD1319D_ISO_SPDIF_LOC,
+ RTD1319D_ISO_HIF_EN_LOC,
+ RTD1319D_ISO_SC0_LOC,
+ RTD1319D_ISO_SC1_LOC,
+ RTD1319D_ISO_SCAN_SWITCH,
+ RTD1319D_ISO_WD_RSET,
+ RTD1319D_ISO_BOOT_SEL,
+ RTD1319D_ISO_RESET_N,
+ RTD1319D_ISO_TESTMODE,
+};
+
+static const struct pinctrl_pin_desc rtd1319d_iso_pins[] = {
+ PINCTRL_PIN(RTD1319D_ISO_GPIO_0, "gpio_0"),
+ PINCTRL_PIN(RTD1319D_ISO_GPIO_1, "gpio_1"),
+ PINCTRL_PIN(RTD1319D_ISO_GPIO_2, "gpio_2"),
+ PINCTRL_PIN(RTD1319D_ISO_GPIO_3, "gpio_3"),
+ PINCTRL_PIN(RTD1319D_ISO_GPIO_4, "gpio_4"),
+ PINCTRL_PIN(RTD1319D_ISO_GPIO_5, "gpio_5"),
+ PINCTRL_PIN(RTD1319D_ISO_GPIO_6, "gpio_6"),
+ PINCTRL_PIN(RTD1319D_ISO_GPIO_7, "gpio_7"),
+ PINCTRL_PIN(RTD1319D_ISO_GPIO_8, "gpio_8"),
+ PINCTRL_PIN(RTD1319D_ISO_GPIO_9, "gpio_9"),
+ PINCTRL_PIN(RTD1319D_ISO_GPIO_10, "gpio_10"),
+ PINCTRL_PIN(RTD1319D_ISO_GPIO_11, "gpio_11"),
+ PINCTRL_PIN(RTD1319D_ISO_GPIO_12, "gpio_12"),
+ PINCTRL_PIN(RTD1319D_ISO_GPIO_13, "gpio_13"),
+ PINCTRL_PIN(RTD1319D_ISO_GPIO_14, "gpio_14"),
+ PINCTRL_PIN(RTD1319D_ISO_GPIO_15, "gpio_15"),
+ PINCTRL_PIN(RTD1319D_ISO_GPIO_16, "gpio_16"),
+ PINCTRL_PIN(RTD1319D_ISO_GPIO_17, "gpio_17"),
+ PINCTRL_PIN(RTD1319D_ISO_GPIO_18, "gpio_18"),
+ PINCTRL_PIN(RTD1319D_ISO_GPIO_19, "gpio_19"),
+ PINCTRL_PIN(RTD1319D_ISO_GPIO_20, "gpio_20"),
+ PINCTRL_PIN(RTD1319D_ISO_GPIO_21, "gpio_21"),
+ PINCTRL_PIN(RTD1319D_ISO_GPIO_22, "gpio_22"),
+ PINCTRL_PIN(RTD1319D_ISO_GPIO_23, "gpio_23"),
+ PINCTRL_PIN(RTD1319D_ISO_USB_CC2, "usb_cc2"),
+ PINCTRL_PIN(RTD1319D_ISO_GPIO_25, "gpio_25"),
+ PINCTRL_PIN(RTD1319D_ISO_GPIO_26, "gpio_26"),
+ PINCTRL_PIN(RTD1319D_ISO_GPIO_27, "gpio_27"),
+ PINCTRL_PIN(RTD1319D_ISO_GPIO_28, "gpio_28"),
+ PINCTRL_PIN(RTD1319D_ISO_GPIO_29, "gpio_29"),
+ PINCTRL_PIN(RTD1319D_ISO_GPIO_30, "gpio_30"),
+ PINCTRL_PIN(RTD1319D_ISO_GPIO_31, "gpio_31"),
+ PINCTRL_PIN(RTD1319D_ISO_GPIO_32, "gpio_32"),
+ PINCTRL_PIN(RTD1319D_ISO_GPIO_33, "gpio_33"),
+ PINCTRL_PIN(RTD1319D_ISO_GPIO_34, "gpio_34"),
+ PINCTRL_PIN(RTD1319D_ISO_GPIO_35, "gpio_35"),
+ PINCTRL_PIN(RTD1319D_ISO_HIF_DATA, "hif_data"),
+ PINCTRL_PIN(RTD1319D_ISO_HIF_EN, "hif_en"),
+ PINCTRL_PIN(RTD1319D_ISO_HIF_RDY, "hif_rdy"),
+ PINCTRL_PIN(RTD1319D_ISO_HIF_CLK, "hif_clk"),
+ PINCTRL_PIN(RTD1319D_ISO_GPIO_40, "gpio_40"),
+ PINCTRL_PIN(RTD1319D_ISO_GPIO_41, "gpio_41"),
+ PINCTRL_PIN(RTD1319D_ISO_GPIO_42, "gpio_42"),
+ PINCTRL_PIN(RTD1319D_ISO_GPIO_43, "gpio_43"),
+ PINCTRL_PIN(RTD1319D_ISO_GPIO_44, "gpio_44"),
+ PINCTRL_PIN(RTD1319D_ISO_GPIO_45, "gpio_45"),
+ PINCTRL_PIN(RTD1319D_ISO_GPIO_46, "gpio_46"),
+ PINCTRL_PIN(RTD1319D_ISO_GPIO_47, "gpio_47"),
+ PINCTRL_PIN(RTD1319D_ISO_GPIO_48, "gpio_48"),
+ PINCTRL_PIN(RTD1319D_ISO_GPIO_49, "gpio_49"),
+ PINCTRL_PIN(RTD1319D_ISO_GPIO_50, "gpio_50"),
+ PINCTRL_PIN(RTD1319D_ISO_USB_CC1, "usb_cc1"),
+ PINCTRL_PIN(RTD1319D_ISO_GPIO_52, "gpio_52"),
+ PINCTRL_PIN(RTD1319D_ISO_GPIO_53, "gpio_53"),
+ PINCTRL_PIN(RTD1319D_ISO_IR_RX, "ir_rx"),
+ PINCTRL_PIN(RTD1319D_ISO_UR0_RX, "ur0_rx"),
+ PINCTRL_PIN(RTD1319D_ISO_UR0_TX, "ur0_tx"),
+ PINCTRL_PIN(RTD1319D_ISO_GPIO_57, "gpio_57"),
+ PINCTRL_PIN(RTD1319D_ISO_GPIO_58, "gpio_58"),
+ PINCTRL_PIN(RTD1319D_ISO_GPIO_59, "gpio_59"),
+ PINCTRL_PIN(RTD1319D_ISO_GPIO_60, "gpio_60"),
+ PINCTRL_PIN(RTD1319D_ISO_GPIO_61, "gpio_61"),
+ PINCTRL_PIN(RTD1319D_ISO_GPIO_62, "gpio_62"),
+ PINCTRL_PIN(RTD1319D_ISO_GPIO_63, "gpio_63"),
+ PINCTRL_PIN(RTD1319D_ISO_GPIO_64, "gpio_64"),
+ PINCTRL_PIN(RTD1319D_ISO_EMMC_RST_N, "emmc_rst_n"),
+ PINCTRL_PIN(RTD1319D_ISO_EMMC_DD_SB, "emmc_dd_sb"),
+ PINCTRL_PIN(RTD1319D_ISO_EMMC_CLK, "emmc_clk"),
+ PINCTRL_PIN(RTD1319D_ISO_EMMC_CMD, "emmc_cmd"),
+ PINCTRL_PIN(RTD1319D_ISO_EMMC_DATA_0, "emmc_data_0"),
+ PINCTRL_PIN(RTD1319D_ISO_EMMC_DATA_1, "emmc_data_1"),
+ PINCTRL_PIN(RTD1319D_ISO_EMMC_DATA_2, "emmc_data_2"),
+ PINCTRL_PIN(RTD1319D_ISO_EMMC_DATA_3, "emmc_data_3"),
+ PINCTRL_PIN(RTD1319D_ISO_EMMC_DATA_4, "emmc_data_4"),
+ PINCTRL_PIN(RTD1319D_ISO_EMMC_DATA_5, "emmc_data_5"),
+ PINCTRL_PIN(RTD1319D_ISO_EMMC_DATA_6, "emmc_data_6"),
+ PINCTRL_PIN(RTD1319D_ISO_EMMC_DATA_7, "emmc_data_7"),
+ PINCTRL_PIN(RTD1319D_ISO_GPIO_DUMMY_77, "dummy"),
+ PINCTRL_PIN(RTD1319D_ISO_GPIO_78, "gpio_78"),
+ PINCTRL_PIN(RTD1319D_ISO_GPIO_79, "gpio_79"),
+ PINCTRL_PIN(RTD1319D_ISO_GPIO_80, "gpio_80"),
+ PINCTRL_PIN(RTD1319D_ISO_GPIO_81, "gpio_81"),
+ PINCTRL_PIN(RTD1319D_ISO_UR2_LOC, "ur2_loc"),
+ PINCTRL_PIN(RTD1319D_ISO_GSPI_LOC, "gspi_loc"),
+ PINCTRL_PIN(RTD1319D_ISO_HI_WIDTH, "hi_width"),
+ PINCTRL_PIN(RTD1319D_ISO_SF_EN, "sf_en"),
+ PINCTRL_PIN(RTD1319D_ISO_ARM_TRACE_DBG_EN, "arm_trace_dbg_en"),
+ PINCTRL_PIN(RTD1319D_ISO_EJTAG_AUCPU_LOC, "ejtag_aucpu_loc"),
+ PINCTRL_PIN(RTD1319D_ISO_EJTAG_ACPU_LOC, "ejtag_acpu_loc"),
+ PINCTRL_PIN(RTD1319D_ISO_EJTAG_VCPU_LOC, "ejtag_vcpu_loc"),
+ PINCTRL_PIN(RTD1319D_ISO_EJTAG_SCPU_LOC, "ejtag_scpu_loc"),
+ PINCTRL_PIN(RTD1319D_ISO_DMIC_LOC, "dmic_loc"),
+ PINCTRL_PIN(RTD1319D_ISO_EJTAG_SECPU_LOC, "ejtag_secpu_loc"),
+ PINCTRL_PIN(RTD1319D_ISO_VTC_DMIC_LOC, "vtc_dmic_loc"),
+ PINCTRL_PIN(RTD1319D_ISO_VTC_TDM_LOC, "vtc_tdm_loc"),
+ PINCTRL_PIN(RTD1319D_ISO_VTC_I2SI_LOC, "vtc_i2si_loc"),
+ PINCTRL_PIN(RTD1319D_ISO_TDM_AI_LOC, "tdm_ai_loc"),
+ PINCTRL_PIN(RTD1319D_ISO_AI_LOC, "ai_loc"),
+ PINCTRL_PIN(RTD1319D_ISO_SPDIF_LOC, "spdif_loc"),
+ PINCTRL_PIN(RTD1319D_ISO_HIF_EN_LOC, "hif_en_loc"),
+ PINCTRL_PIN(RTD1319D_ISO_SC0_LOC, "sc0_loc"),
+ PINCTRL_PIN(RTD1319D_ISO_SC1_LOC, "sc1_loc"),
+ PINCTRL_PIN(RTD1319D_ISO_SCAN_SWITCH, "scan_switch"),
+ PINCTRL_PIN(RTD1319D_ISO_WD_RSET, "wd_rset"),
+ PINCTRL_PIN(RTD1319D_ISO_BOOT_SEL, "boot_sel"),
+ PINCTRL_PIN(RTD1319D_ISO_RESET_N, "reset_n"),
+ PINCTRL_PIN(RTD1319D_ISO_TESTMODE, "testmode"),
+};
+
+/* Tagged as __maybe_unused since there are pins we may use in the future */
+#define DECLARE_RTD1319D_PIN(_pin, _name) \
+ static const unsigned int rtd1319d_## _name ##_pins[] __maybe_unused = { _pin }
+
+DECLARE_RTD1319D_PIN(RTD1319D_ISO_GPIO_0, gpio_0);
+DECLARE_RTD1319D_PIN(RTD1319D_ISO_GPIO_1, gpio_1);
+DECLARE_RTD1319D_PIN(RTD1319D_ISO_GPIO_2, gpio_2);
+DECLARE_RTD1319D_PIN(RTD1319D_ISO_GPIO_3, gpio_3);
+DECLARE_RTD1319D_PIN(RTD1319D_ISO_GPIO_4, gpio_4);
+DECLARE_RTD1319D_PIN(RTD1319D_ISO_GPIO_5, gpio_5);
+DECLARE_RTD1319D_PIN(RTD1319D_ISO_GPIO_6, gpio_6);
+DECLARE_RTD1319D_PIN(RTD1319D_ISO_GPIO_7, gpio_7);
+DECLARE_RTD1319D_PIN(RTD1319D_ISO_GPIO_8, gpio_8);
+DECLARE_RTD1319D_PIN(RTD1319D_ISO_GPIO_9, gpio_9);
+DECLARE_RTD1319D_PIN(RTD1319D_ISO_GPIO_10, gpio_10);
+DECLARE_RTD1319D_PIN(RTD1319D_ISO_GPIO_11, gpio_11);
+DECLARE_RTD1319D_PIN(RTD1319D_ISO_GPIO_12, gpio_12);
+DECLARE_RTD1319D_PIN(RTD1319D_ISO_GPIO_13, gpio_13);
+DECLARE_RTD1319D_PIN(RTD1319D_ISO_GPIO_14, gpio_14);
+DECLARE_RTD1319D_PIN(RTD1319D_ISO_GPIO_15, gpio_15);
+DECLARE_RTD1319D_PIN(RTD1319D_ISO_GPIO_16, gpio_16);
+DECLARE_RTD1319D_PIN(RTD1319D_ISO_GPIO_17, gpio_17);
+DECLARE_RTD1319D_PIN(RTD1319D_ISO_GPIO_18, gpio_18);
+DECLARE_RTD1319D_PIN(RTD1319D_ISO_GPIO_19, gpio_19);
+DECLARE_RTD1319D_PIN(RTD1319D_ISO_GPIO_20, gpio_20);
+DECLARE_RTD1319D_PIN(RTD1319D_ISO_GPIO_21, gpio_21);
+DECLARE_RTD1319D_PIN(RTD1319D_ISO_GPIO_22, gpio_22);
+DECLARE_RTD1319D_PIN(RTD1319D_ISO_GPIO_23, gpio_23);
+DECLARE_RTD1319D_PIN(RTD1319D_ISO_USB_CC2, usb_cc2);
+DECLARE_RTD1319D_PIN(RTD1319D_ISO_GPIO_25, gpio_25);
+DECLARE_RTD1319D_PIN(RTD1319D_ISO_GPIO_26, gpio_26);
+DECLARE_RTD1319D_PIN(RTD1319D_ISO_GPIO_27, gpio_27);
+DECLARE_RTD1319D_PIN(RTD1319D_ISO_GPIO_28, gpio_28);
+DECLARE_RTD1319D_PIN(RTD1319D_ISO_GPIO_29, gpio_29);
+DECLARE_RTD1319D_PIN(RTD1319D_ISO_GPIO_30, gpio_30);
+DECLARE_RTD1319D_PIN(RTD1319D_ISO_GPIO_31, gpio_31);
+DECLARE_RTD1319D_PIN(RTD1319D_ISO_GPIO_32, gpio_32);
+DECLARE_RTD1319D_PIN(RTD1319D_ISO_GPIO_33, gpio_33);
+DECLARE_RTD1319D_PIN(RTD1319D_ISO_GPIO_34, gpio_34);
+DECLARE_RTD1319D_PIN(RTD1319D_ISO_GPIO_35, gpio_35);
+DECLARE_RTD1319D_PIN(RTD1319D_ISO_HIF_DATA, hif_data);
+DECLARE_RTD1319D_PIN(RTD1319D_ISO_HIF_EN, hif_en);
+DECLARE_RTD1319D_PIN(RTD1319D_ISO_HIF_RDY, hif_rdy);
+DECLARE_RTD1319D_PIN(RTD1319D_ISO_HIF_CLK, hif_clk);
+DECLARE_RTD1319D_PIN(RTD1319D_ISO_GPIO_40, gpio_40);
+DECLARE_RTD1319D_PIN(RTD1319D_ISO_GPIO_41, gpio_41);
+DECLARE_RTD1319D_PIN(RTD1319D_ISO_GPIO_42, gpio_42);
+DECLARE_RTD1319D_PIN(RTD1319D_ISO_GPIO_43, gpio_43);
+DECLARE_RTD1319D_PIN(RTD1319D_ISO_GPIO_44, gpio_44);
+DECLARE_RTD1319D_PIN(RTD1319D_ISO_GPIO_45, gpio_45);
+DECLARE_RTD1319D_PIN(RTD1319D_ISO_GPIO_46, gpio_46);
+DECLARE_RTD1319D_PIN(RTD1319D_ISO_GPIO_47, gpio_47);
+DECLARE_RTD1319D_PIN(RTD1319D_ISO_GPIO_48, gpio_48);
+DECLARE_RTD1319D_PIN(RTD1319D_ISO_GPIO_49, gpio_49);
+DECLARE_RTD1319D_PIN(RTD1319D_ISO_GPIO_50, gpio_50);
+DECLARE_RTD1319D_PIN(RTD1319D_ISO_USB_CC1, usb_cc1);
+DECLARE_RTD1319D_PIN(RTD1319D_ISO_GPIO_52, gpio_52);
+DECLARE_RTD1319D_PIN(RTD1319D_ISO_GPIO_53, gpio_53);
+DECLARE_RTD1319D_PIN(RTD1319D_ISO_IR_RX, ir_rx);
+DECLARE_RTD1319D_PIN(RTD1319D_ISO_UR0_RX, ur0_rx);
+DECLARE_RTD1319D_PIN(RTD1319D_ISO_UR0_TX, ur0_tx);
+DECLARE_RTD1319D_PIN(RTD1319D_ISO_GPIO_57, gpio_57);
+DECLARE_RTD1319D_PIN(RTD1319D_ISO_GPIO_58, gpio_58);
+DECLARE_RTD1319D_PIN(RTD1319D_ISO_GPIO_59, gpio_59);
+DECLARE_RTD1319D_PIN(RTD1319D_ISO_GPIO_60, gpio_60);
+DECLARE_RTD1319D_PIN(RTD1319D_ISO_GPIO_61, gpio_61);
+DECLARE_RTD1319D_PIN(RTD1319D_ISO_GPIO_62, gpio_62);
+DECLARE_RTD1319D_PIN(RTD1319D_ISO_GPIO_63, gpio_63);
+DECLARE_RTD1319D_PIN(RTD1319D_ISO_GPIO_64, gpio_64);
+DECLARE_RTD1319D_PIN(RTD1319D_ISO_EMMC_RST_N, emmc_rst_n);
+DECLARE_RTD1319D_PIN(RTD1319D_ISO_EMMC_DD_SB, emmc_dd_sb);
+DECLARE_RTD1319D_PIN(RTD1319D_ISO_EMMC_CLK, emmc_clk);
+DECLARE_RTD1319D_PIN(RTD1319D_ISO_EMMC_CMD, emmc_cmd);
+DECLARE_RTD1319D_PIN(RTD1319D_ISO_EMMC_DATA_0, emmc_data_0);
+DECLARE_RTD1319D_PIN(RTD1319D_ISO_EMMC_DATA_1, emmc_data_1);
+DECLARE_RTD1319D_PIN(RTD1319D_ISO_EMMC_DATA_2, emmc_data_2);
+DECLARE_RTD1319D_PIN(RTD1319D_ISO_EMMC_DATA_3, emmc_data_3);
+DECLARE_RTD1319D_PIN(RTD1319D_ISO_EMMC_DATA_4, emmc_data_4);
+DECLARE_RTD1319D_PIN(RTD1319D_ISO_EMMC_DATA_5, emmc_data_5);
+DECLARE_RTD1319D_PIN(RTD1319D_ISO_EMMC_DATA_6, emmc_data_6);
+DECLARE_RTD1319D_PIN(RTD1319D_ISO_EMMC_DATA_7, emmc_data_7);
+DECLARE_RTD1319D_PIN(RTD1319D_ISO_GPIO_78, gpio_78);
+DECLARE_RTD1319D_PIN(RTD1319D_ISO_GPIO_79, gpio_79);
+DECLARE_RTD1319D_PIN(RTD1319D_ISO_GPIO_80, gpio_80);
+DECLARE_RTD1319D_PIN(RTD1319D_ISO_GPIO_81, gpio_81);
+DECLARE_RTD1319D_PIN(RTD1319D_ISO_UR2_LOC, ur2_loc);
+DECLARE_RTD1319D_PIN(RTD1319D_ISO_GSPI_LOC, gspi_loc);
+DECLARE_RTD1319D_PIN(RTD1319D_ISO_HI_WIDTH, hi_width);
+DECLARE_RTD1319D_PIN(RTD1319D_ISO_SF_EN, sf_en);
+DECLARE_RTD1319D_PIN(RTD1319D_ISO_ARM_TRACE_DBG_EN, arm_trace_dbg_en);
+DECLARE_RTD1319D_PIN(RTD1319D_ISO_EJTAG_AUCPU_LOC, ejtag_aucpu_loc);
+DECLARE_RTD1319D_PIN(RTD1319D_ISO_EJTAG_ACPU_LOC, ejtag_acpu_loc);
+DECLARE_RTD1319D_PIN(RTD1319D_ISO_EJTAG_VCPU_LOC, ejtag_vcpu_loc);
+DECLARE_RTD1319D_PIN(RTD1319D_ISO_EJTAG_SCPU_LOC, ejtag_scpu_loc);
+DECLARE_RTD1319D_PIN(RTD1319D_ISO_DMIC_LOC, dmic_loc);
+DECLARE_RTD1319D_PIN(RTD1319D_ISO_EJTAG_SECPU_LOC, ejtag_secpu_loc);
+DECLARE_RTD1319D_PIN(RTD1319D_ISO_VTC_DMIC_LOC, vtc_dmic_loc);
+DECLARE_RTD1319D_PIN(RTD1319D_ISO_VTC_TDM_LOC, vtc_tdm_loc);
+DECLARE_RTD1319D_PIN(RTD1319D_ISO_VTC_I2SI_LOC, vtc_i2si_loc);
+DECLARE_RTD1319D_PIN(RTD1319D_ISO_TDM_AI_LOC, tdm_ai_loc);
+DECLARE_RTD1319D_PIN(RTD1319D_ISO_AI_LOC, ai_loc);
+DECLARE_RTD1319D_PIN(RTD1319D_ISO_SPDIF_LOC, spdif_loc);
+DECLARE_RTD1319D_PIN(RTD1319D_ISO_HIF_EN_LOC, hif_en_loc);
+DECLARE_RTD1319D_PIN(RTD1319D_ISO_SC0_LOC, sc0_loc);
+DECLARE_RTD1319D_PIN(RTD1319D_ISO_SC1_LOC, sc1_loc);
+DECLARE_RTD1319D_PIN(RTD1319D_ISO_SCAN_SWITCH, scan_switch);
+DECLARE_RTD1319D_PIN(RTD1319D_ISO_WD_RSET, wd_rset);
+DECLARE_RTD1319D_PIN(RTD1319D_ISO_BOOT_SEL, boot_sel);
+DECLARE_RTD1319D_PIN(RTD1319D_ISO_RESET_N, reset_n);
+DECLARE_RTD1319D_PIN(RTD1319D_ISO_TESTMODE, testmode);
+
+#define RTD1319D_GROUP(_name) \
+ { \
+ .name = # _name, \
+ .pins = rtd1319d_ ## _name ## _pins, \
+ .num_pins = ARRAY_SIZE(rtd1319d_ ## _name ## _pins), \
+ }
+
+static const struct rtd_pin_group_desc rtd1319d_pin_groups[] = {
+ RTD1319D_GROUP(gpio_0),
+ RTD1319D_GROUP(gpio_1),
+ RTD1319D_GROUP(gpio_2),
+ RTD1319D_GROUP(gpio_3),
+ RTD1319D_GROUP(gpio_4),
+ RTD1319D_GROUP(gpio_5),
+ RTD1319D_GROUP(gpio_6),
+ RTD1319D_GROUP(gpio_7),
+ RTD1319D_GROUP(gpio_8),
+ RTD1319D_GROUP(gpio_9),
+ RTD1319D_GROUP(gpio_10),
+ RTD1319D_GROUP(gpio_11),
+ RTD1319D_GROUP(gpio_12),
+ RTD1319D_GROUP(gpio_13),
+ RTD1319D_GROUP(gpio_14),
+ RTD1319D_GROUP(gpio_15),
+ RTD1319D_GROUP(gpio_16),
+ RTD1319D_GROUP(gpio_17),
+ RTD1319D_GROUP(gpio_18),
+ RTD1319D_GROUP(gpio_19),
+ RTD1319D_GROUP(gpio_20),
+ RTD1319D_GROUP(gpio_21),
+ RTD1319D_GROUP(gpio_22),
+ RTD1319D_GROUP(gpio_23),
+ RTD1319D_GROUP(usb_cc2),
+ RTD1319D_GROUP(gpio_25),
+ RTD1319D_GROUP(gpio_26),
+ RTD1319D_GROUP(gpio_27),
+ RTD1319D_GROUP(gpio_28),
+ RTD1319D_GROUP(gpio_29),
+ RTD1319D_GROUP(gpio_30),
+ RTD1319D_GROUP(gpio_31),
+ RTD1319D_GROUP(gpio_32),
+ RTD1319D_GROUP(gpio_33),
+ RTD1319D_GROUP(gpio_34),
+ RTD1319D_GROUP(gpio_35),
+ RTD1319D_GROUP(hif_data),
+ RTD1319D_GROUP(hif_en),
+ RTD1319D_GROUP(hif_rdy),
+ RTD1319D_GROUP(hif_clk),
+ RTD1319D_GROUP(gpio_40),
+ RTD1319D_GROUP(gpio_41),
+ RTD1319D_GROUP(gpio_42),
+ RTD1319D_GROUP(gpio_43),
+ RTD1319D_GROUP(gpio_44),
+ RTD1319D_GROUP(gpio_45),
+ RTD1319D_GROUP(gpio_46),
+ RTD1319D_GROUP(gpio_47),
+ RTD1319D_GROUP(gpio_48),
+ RTD1319D_GROUP(gpio_49),
+ RTD1319D_GROUP(gpio_50),
+ RTD1319D_GROUP(usb_cc1),
+ RTD1319D_GROUP(gpio_52),
+ RTD1319D_GROUP(gpio_53),
+ RTD1319D_GROUP(ir_rx),
+ RTD1319D_GROUP(ur0_rx),
+ RTD1319D_GROUP(ur0_tx),
+ RTD1319D_GROUP(gpio_57),
+ RTD1319D_GROUP(gpio_58),
+ RTD1319D_GROUP(gpio_59),
+ RTD1319D_GROUP(gpio_60),
+ RTD1319D_GROUP(gpio_61),
+ RTD1319D_GROUP(gpio_62),
+ RTD1319D_GROUP(gpio_63),
+ RTD1319D_GROUP(gpio_64),
+ RTD1319D_GROUP(emmc_rst_n),
+ RTD1319D_GROUP(emmc_dd_sb),
+ RTD1319D_GROUP(emmc_clk),
+ RTD1319D_GROUP(emmc_cmd),
+ RTD1319D_GROUP(emmc_data_0),
+ RTD1319D_GROUP(emmc_data_1),
+ RTD1319D_GROUP(emmc_data_2),
+ RTD1319D_GROUP(emmc_data_3),
+ RTD1319D_GROUP(emmc_data_4),
+ RTD1319D_GROUP(emmc_data_5),
+ RTD1319D_GROUP(emmc_data_6),
+ RTD1319D_GROUP(emmc_data_7),
+ RTD1319D_GROUP(gpio_78),
+ RTD1319D_GROUP(gpio_79),
+ RTD1319D_GROUP(gpio_80),
+ RTD1319D_GROUP(gpio_81),
+ RTD1319D_GROUP(ur2_loc),
+ RTD1319D_GROUP(gspi_loc),
+ RTD1319D_GROUP(hi_width),
+ RTD1319D_GROUP(sf_en),
+ RTD1319D_GROUP(arm_trace_dbg_en),
+ RTD1319D_GROUP(ejtag_aucpu_loc),
+ RTD1319D_GROUP(ejtag_acpu_loc),
+ RTD1319D_GROUP(ejtag_vcpu_loc),
+ RTD1319D_GROUP(ejtag_scpu_loc),
+ RTD1319D_GROUP(dmic_loc),
+ RTD1319D_GROUP(ejtag_secpu_loc),
+ RTD1319D_GROUP(vtc_dmic_loc),
+ RTD1319D_GROUP(vtc_tdm_loc),
+ RTD1319D_GROUP(vtc_i2si_loc),
+ RTD1319D_GROUP(tdm_ai_loc),
+ RTD1319D_GROUP(ai_loc),
+ RTD1319D_GROUP(spdif_loc),
+ RTD1319D_GROUP(hif_en_loc),
+ RTD1319D_GROUP(sc0_loc),
+ RTD1319D_GROUP(sc1_loc),
+};
+
+static const char * const rtd1319d_gpio_groups[] = {
+ "gpio_0", "gpio_1", "gpio_2", "gpio_3", "gpio_4",
+ "gpio_5", "gpio_6", "gpio_7", "gpio_8", "gpio_9",
+ "gpio_10", "gpio_11", "gpio_12", "gpio_13", "gpio_14",
+ "gpio_15", "gpio_16", "gpio_17", "gpio_18", "gpio_19",
+ "gpio_20", "gpio_21", "gpio_22", "gpio_23", "usb_cc2",
+ "gpio_25", "gpio_26", "gpio_27", "gpio_28", "gpio_29",
+ "gpio_30", "gpio_31", "gpio_32", "gpio_33", "gpio_34",
+ "gpio_35", "hif_data", "hif_en", "hif_rdy", "hif_clk",
+ "gpio_40", "gpio_41", "gpio_42", "gpio_43", "gpio_44",
+ "gpio_45", "gpio_46", "gpio_47", "gpio_48", "gpio_49",
+ "gpio_50", "usb_cc1", "gpio_52", "gpio_53", "ir_rx",
+ "ur0_rx", "ur0_tx", "gpio_57", "gpio_58", "gpio_59",
+ "gpio_60", "gpio_61", "gpio_62", "gpio_63", "gpio_64",
+ "emmc_rst_n", "emmc_dd_sb", "emmc_clk", "emmc_cmd",
+ "emmc_data_0", "emmc_data_1", "emmc_data_2", "emmc_data_3",
+ "emmc_data_4", "emmc_data_5", "emmc_data_6", "emmc_data_7",
+ "gpio_78", "gpio_79", "gpio_80", "gpio_81" };
+static const char * const rtd1319d_nf_groups[] = {
+ "emmc_rst_n", "emmc_clk", "emmc_cmd", "emmc_data_0",
+ "emmc_data_1", "emmc_data_2", "emmc_data_3", "emmc_data_4",
+ "emmc_data_5", "emmc_data_6", "emmc_data_7",
+ "gpio_78", "gpio_79", "gpio_80", "gpio_81" };
+static const char * const rtd1319d_emmc_groups[] = {
+ "emmc_rst_n", "emmc_dd_sb", "emmc_clk", "emmc_cmd",
+ "emmc_data_0", "emmc_data_1", "emmc_data_2", "emmc_data_3",
+ "emmc_data_4", "emmc_data_5", "emmc_data_6", "emmc_data_7" };
+static const char * const rtd1319d_tp0_groups[] = {
+ "gpio_2", "gpio_3", "gpio_4", "gpio_57", "gpio_58",
+ "gpio_59", "gpio_60", "gpio_61", "gpio_62", "gpio_63",
+ "gpio_64" };
+static const char * const rtd1319d_tp1_groups[] = {
+ "gpio_61", "gpio_62", "gpio_63", "gpio_64" };
+static const char * const rtd1319d_sc0_groups[] = {
+ "gpio_18", "gpio_19", "gpio_31" };
+static const char * const rtd1319d_sc0_data0_groups[] = { "gpio_20", "sc0_loc" };
+static const char * const rtd1319d_sc0_data1_groups[] = { "gpio_30", "sc0_loc" };
+static const char * const rtd1319d_sc0_data2_groups[] = { "gpio_47", "sc0_loc" };
+static const char * const rtd1319d_sc1_groups[] = {
+ "gpio_2", "gpio_3", "gpio_5" };
+static const char * const rtd1319d_sc1_data0_groups[] = { "gpio_52", "sc1_loc" };
+static const char * const rtd1319d_sc1_data1_groups[] = { "gpio_34", "sc1_loc" };
+static const char * const rtd1319d_sc1_data2_groups[] = { "gpio_35", "sc1_loc" };
+static const char * const rtd1319d_ao_groups[] = {
+ "gpio_2", "gpio_3", "gpio_4", "gpio_61", "gpio_62",
+ "gpio_63", "gpio_64" };
+static const char * const rtd1319d_gspi_loc0_groups[] = {
+ "gpio_18", "gpio_19", "gpio_20", "gpio_31", "gspi_loc" };
+static const char * const rtd1319d_gspi_loc1_groups[] = {
+ "gpio_8", "gpio_9", "gpio_10", "gpio_11", "gspi_loc" };
+static const char * const rtd1319d_uart0_groups[] = { "ur0_rx", "ur0_tx"};
+static const char * const rtd1319d_uart1_groups[] = {
+ "gpio_8", "gpio_9", "gpio_10", "gpio_11" };
+static const char * const rtd1319d_uart2_loc0_groups[] = {
+ "gpio_18", "gpio_19", "gpio_20", "gpio_31", "ur2_loc" };
+static const char * const rtd1319d_uart2_loc1_groups[] = {
+ "gpio_25", "gpio_26", "gpio_27", "gpio_28", "ur2_loc" };
+static const char * const rtd1319d_i2c0_groups[] = { "gpio_12", "gpio_13" };
+static const char * const rtd1319d_i2c1_groups[] = { "gpio_16", "gpio_17" };
+static const char * const rtd1319d_i2c3_groups[] = { "gpio_26", "gpio_27" };
+static const char * const rtd1319d_i2c4_groups[] = { "gpio_34", "gpio_35" };
+static const char * const rtd1319d_i2c5_groups[] = { "gpio_29", "gpio_46" };
+static const char * const rtd1319d_pcie1_groups[] = { "gpio_22" };
+static const char * const rtd1319d_sdio_groups[] = {
+ "gpio_40", "gpio_41", "gpio_42", "gpio_43", "gpio_44",
+ "gpio_45" };
+static const char * const rtd1319d_etn_led_groups[] = { "gpio_14", "gpio_15" };
+static const char * const rtd1319d_etn_phy_groups[] = { "gpio_14", "gpio_15" };
+static const char * const rtd1319d_spi_groups[] = {
+ "gpio_18", "gpio_19", "gpio_20", "gpio_31" };
+static const char * const rtd1319d_pwm0_loc0_groups[] = { "gpio_26" };
+static const char * const rtd1319d_pwm0_loc1_groups[] = { "gpio_20" };
+static const char * const rtd1319d_pwm1_loc0_groups[] = { "gpio_27" };
+static const char * const rtd1319d_pwm1_loc1_groups[] = { "gpio_21" };
+
+static const char * const rtd1319d_pwm2_loc0_groups[] = { "gpio_28" };
+static const char * const rtd1319d_pwm2_loc1_groups[] = { "gpio_22" };
+static const char * const rtd1319d_pwm3_loc0_groups[] = { "gpio_47" };
+static const char * const rtd1319d_pwm3_loc1_groups[] = { "gpio_23" };
+static const char * const rtd1319d_qam_agc_if0_groups[] = { "gpio_21" };
+static const char * const rtd1319d_qam_agc_if1_groups[] = { "gpio_23" };
+static const char * const rtd1319d_spdif_optical_loc0_groups[] = { "gpio_21", "spdif_loc" };
+static const char * const rtd1319d_spdif_optical_loc1_groups[] = { "gpio_6", "spdif_loc" };
+static const char * const rtd1319d_usb_cc1_groups[] = { "usb_cc1" };
+static const char * const rtd1319d_usb_cc2_groups[] = { "usb_cc2" };
+static const char * const rtd1319d_vfd_groups[] = {
+ "gpio_26", "gpio_27", "gpio_28" };
+static const char * const rtd1319d_sd_groups[] = {
+ "gpio_32", "gpio_33", "gpio_34", "gpio_35",
+ "hif_data", "hif_en", "hif_rdy", "hif_clk" };
+static const char * const rtd1319d_dmic_loc0_groups[] = {
+ "gpio_57", "gpio_58", "gpio_59", "gpio_60", "gpio_61",
+ "gpio_62", "gpio_63", "gpio_64", "dmic_loc" };
+static const char * const rtd1319d_dmic_loc1_groups[] = {
+ "gpio_32", "gpio_33", "gpio_34", "gpio_35",
+ "hif_data", "hif_en", "hif_rdy", "hif_clk",
+ "dmic_loc" };
+static const char * const rtd1319d_ai_loc0_groups[] = {
+ "gpio_57", "gpio_58", "gpio_59", "gpio_60", "gpio_61",
+ "gpio_62", "gpio_63", "ai_loc" };
+static const char * const rtd1319d_ai_loc1_groups[] = {
+ "gpio_32", "gpio_33", "gpio_34", "hif_data",
+ "hif_en", "hif_rdy", "hif_clk", "ai_loc" };
+static const char * const rtd1319d_tdm_ai_loc0_groups[] = {
+ "gpio_57", "gpio_58", "gpio_59",
+ "gpio_60", "tdm_ai_loc" };
+static const char * const rtd1319d_tdm_ai_loc1_groups[] = {
+ "hif_data", "hif_en", "hif_rdy", "hif_clk", "tdm_ai_loc" };
+static const char * const rtd1319d_hi_loc0_groups[] = {
+ "hif_data", "hif_en", "hif_rdy", "hif_clk" };
+static const char * const rtd1319d_hi_m_groups[] = {
+ "hif_data", "hif_en", "hif_rdy", "hif_clk" };
+static const char * const rtd1319d_vtc_i2so_groups[] = {
+ "gpio_2", "gpio_3", "gpio_4", "gpio_64"};
+static const char * const rtd1319d_vtc_i2si_loc0_groups[] = {
+ "gpio_57", "gpio_58", "gpio_59", "gpio_60", "gpio_61",
+ "vtc_i2si_loc" };
+static const char * const rtd1319d_vtc_i2si_loc1_groups[] = {
+ "gpio_32", "hif_data", "hif_en", "hif_rdy", "hif_clk",
+ "vtc_i2si_loc" };
+static const char * const rtd1319d_vtc_dmic_loc0_groups[] = {
+ "gpio_57", "gpio_58", "gpio_59", "gpio_60",
+ "vtc_dmic_loc" };
+static const char * const rtd1319d_vtc_dmic_loc1_groups[] = {
+ "hif_data", "hif_en", "hif_rdy", "hif_clk",
+ "vtc_dmic_loc" };
+static const char * const rtd1319d_vtc_tdm_loc0_groups[] = {
+ "gpio_57", "gpio_58", "gpio_59", "gpio_60",
+ "vtc_tdm_loc" };
+static const char * const rtd1319d_vtc_tdm_loc1_groups[] = {
+ "hif_data", "hif_en", "hif_rdy", "hif_clk",
+ "vtc_tdm_loc" };
+static const char * const rtd1319d_dc_fan_groups[] = { "gpio_47" };
+static const char * const rtd1319d_pll_test_loc0_groups[] = { "gpio_52", "gpio_53" };
+static const char * const rtd1319d_pll_test_loc1_groups[] = { "gpio_48", "gpio_49" };
+static const char * const rtd1319d_spdif_groups[] = { "gpio_50" };
+static const char * const rtd1319d_ir_rx_groups[] = { "ir_rx" };
+static const char * const rtd1319d_uart2_disable_groups[] = { "ur2_loc" };
+static const char * const rtd1319d_gspi_disable_groups[] = { "gspi_loc" };
+static const char * const rtd1319d_hi_width_disable_groups[] = { "hi_width" };
+static const char * const rtd1319d_hi_width_1bit_groups[] = { "hi_width" };
+static const char * const rtd1319d_sf_disable_groups[] = { "sf_en" };
+static const char * const rtd1319d_sf_enable_groups[] = { "sf_en" };
+static const char * const rtd1319d_scpu_ejtag_loc0_groups[] = {
+ "gpio_2", "gpio_3", "gpio_4", "gpio_5", "gpio_6",
+ "ejtag_scpu_loc" };
+static const char * const rtd1319d_scpu_ejtag_loc1_groups[] = {
+ "gpio_32", "gpio_33", "hif_data", "hif_en", "hif_clk",
+ "ejtag_scpu_loc" };
+static const char * const rtd1319d_scpu_ejtag_loc2_groups[] = {
+ "gpio_57", "gpio_58", "gpio_59", "gpio_60", "gpio_61",
+ "ejtag_scpu_loc" };
+static const char * const rtd1319d_acpu_ejtag_loc0_groups[] = {
+ "gpio_2", "gpio_3", "gpio_4", "gpio_5", "gpio_6",
+ "ejtag_acpu_loc" };
+static const char * const rtd1319d_acpu_ejtag_loc1_groups[] = {
+ "gpio_32", "gpio_33", "hif_data", "hif_en", "hif_clk",
+ "ejtag_acpu_loc" };
+static const char * const rtd1319d_acpu_ejtag_loc2_groups[] = {
+ "gpio_57", "gpio_58", "gpio_59", "gpio_60", "gpio_61",
+ "ejtag_acpu_loc" };
+static const char * const rtd1319d_vcpu_ejtag_loc0_groups[] = {
+ "gpio_2", "gpio_3", "gpio_4", "gpio_5", "gpio_6",
+ "ejtag_vcpu_loc" };
+static const char * const rtd1319d_vcpu_ejtag_loc1_groups[] = {
+ "gpio_32", "gpio_33", "hif_data", "hif_en", "hif_clk",
+ "ejtag_vcpu_loc" };
+static const char * const rtd1319d_vcpu_ejtag_loc2_groups[] = {
+ "gpio_57", "gpio_58", "gpio_59", "gpio_60", "gpio_61",
+ "ejtag_vcpu_loc" };
+static const char * const rtd1319d_secpu_ejtag_loc0_groups[] = {
+ "gpio_2", "gpio_3", "gpio_4", "gpio_5", "gpio_6",
+ "ejtag_secpu_loc" };
+static const char * const rtd1319d_secpu_ejtag_loc1_groups[] = {
+ "gpio_32", "gpio_33", "hif_data", "hif_en", "hif_clk",
+ "ejtag_secpu_loc" };
+static const char * const rtd1319d_secpu_ejtag_loc2_groups[] = {
+ "gpio_57", "gpio_58", "gpio_59", "gpio_60", "gpio_61",
+ "ejtag_secpu_loc" };
+static const char * const rtd1319d_aucpu_ejtag_loc0_groups[] = {
+ "gpio_2", "gpio_3", "gpio_4", "gpio_5", "gpio_6",
+ "ejtag_aucpu_loc" };
+static const char * const rtd1319d_aucpu_ejtag_loc1_groups[] = {
+ "gpio_32", "gpio_33", "hif_data", "hif_en", "hif_clk",
+ "ejtag_aucpu_loc" };
+static const char * const rtd1319d_aucpu_ejtag_loc2_groups[] = {
+ "gpio_57", "gpio_58", "gpio_59", "gpio_60", "gpio_61",
+ "ejtag_aucpu_loc" };
+static const char * const rtd1319d_iso_tristate_groups[] = {
+ "emmc_rst_n", "emmc_dd_sb", "emmc_clk", "emmc_cmd",
+ "emmc_data_0", "emmc_data_1", "emmc_data_2", "emmc_data_3",
+ "emmc_data_4", "emmc_data_5", "emmc_data_6", "emmc_data_7",
+ "gpio_78", "gpio_79", "gpio_80", "gpio_81", "gpio_1",
+ "gpio_8", "gpio_9", "gpio_10", "gpio_11", "gpio_22",
+ "gpio_23", "usb_cc2", "gpio_25", "gpio_28", "gpio_29",
+ "gpio_30", "gpio_32", "gpio_33", "hif_data", "hif_en",
+ "hif_rdy", "hif_clk", "gpio_40", "gpio_41", "gpio_42",
+ "gpio_43", "gpio_44", "gpio_45", "gpio_46", "usb_cc1",
+ "ir_rx", "ur0_rx", "ur0_tx", "gpio_62", "gpio_63", "gpio_64" };
+static const char * const rtd1319d_dbg_out0_groups[] = {
+ "gpio_12", "gpio_13", "gpio_16", "gpio_17", "gpio_26", "gpio_27",
+ "gpio_34", "gpio_35", "gpio_48", "gpio_49", "gpio_57", "gpio_58",
+ "gpio_59", "gpio_60", "gpio_61" };
+static const char * const rtd1319d_dbg_out1_groups[] = {
+ "gpio_0", "gpio_2", "gpio_3", "gpio_4", "gpio_5", "gpio_6",
+ "gpio_7", "gpio_14", "gpio_15", "gpio_18", "gpio_19", "gpio_20",
+ "gpio_21", "gpio_31", "gpio_47", "gpio_50", "gpio_52", "gpio_53" };
+static const char * const rtd1319d_standby_dbg_groups[] = {
+ "gpio_2", "gpio_3", "ir_rx" };
+static const char * const rtd1319d_arm_trace_debug_disable_groups[] = { "arm_trace_dbg_en" };
+static const char * const rtd1319d_arm_trace_debug_enable_groups[] = { "arm_trace_dbg_en" };
+static const char * const rtd1319d_aucpu_ejtag_disable_groups[] = { "ejtag_aucpu_loc" };
+static const char * const rtd1319d_acpu_ejtag_disable_groups[] = { "ejtag_acpu_loc" };
+static const char * const rtd1319d_vcpu_ejtag_disable_groups[] = { "ejtag_vcpu_loc" };
+static const char * const rtd1319d_scpu_ejtag_disable_groups[] = { "ejtag_scpu_loc" };
+static const char * const rtd1319d_secpu_ejtag_disable_groups[] = { "ejtag_secpu_loc" };
+static const char * const rtd1319d_vtc_dmic_loc_disable_groups[] = { "vtc_dmic_loc" };
+static const char * const rtd1319d_vtc_tdm_disable_groups[] = { "vtc_tdm_loc" };
+static const char * const rtd1319d_vtc_i2si_disable_groups[] = { "vtc_i2si_loc" };
+static const char * const rtd1319d_tdm_ai_disable_groups[] = { "tdm_ai_loc" };
+static const char * const rtd1319d_ai_disable_groups[] = { "ai_loc" };
+static const char * const rtd1319d_spdif_disable_groups[] = { "spdif_loc" };
+static const char * const rtd1319d_hif_disable_groups[] = { "hif_en_loc" };
+static const char * const rtd1319d_hif_enable_groups[] = { "hif_en_loc" };
+static const char * const rtd1319d_test_loop_groups[] = { "gpio_27" };
+static const char * const rtd1319d_pmic_pwrup_groups[] = { "gpio_78" };
+
+#define RTD1319D_FUNC(_name) \
+ { \
+ .name = # _name, \
+ .groups = rtd1319d_ ## _name ## _groups, \
+ .num_groups = ARRAY_SIZE(rtd1319d_ ## _name ## _groups), \
+ }
+
+static const struct rtd_pin_func_desc rtd1319d_pin_functions[] = {
+ RTD1319D_FUNC(gpio),
+ RTD1319D_FUNC(nf),
+ RTD1319D_FUNC(emmc),
+ RTD1319D_FUNC(tp0),
+ RTD1319D_FUNC(tp1),
+ RTD1319D_FUNC(sc0),
+ RTD1319D_FUNC(sc0_data0),
+ RTD1319D_FUNC(sc0_data1),
+ RTD1319D_FUNC(sc0_data2),
+ RTD1319D_FUNC(sc1),
+ RTD1319D_FUNC(sc1_data0),
+ RTD1319D_FUNC(sc1_data1),
+ RTD1319D_FUNC(sc1_data2),
+ RTD1319D_FUNC(ao),
+ RTD1319D_FUNC(gspi_loc0),
+ RTD1319D_FUNC(gspi_loc1),
+ RTD1319D_FUNC(uart0),
+ RTD1319D_FUNC(uart1),
+ RTD1319D_FUNC(uart2_loc0),
+ RTD1319D_FUNC(uart2_loc1),
+ RTD1319D_FUNC(i2c0),
+ RTD1319D_FUNC(i2c1),
+ RTD1319D_FUNC(i2c3),
+ RTD1319D_FUNC(i2c4),
+ RTD1319D_FUNC(i2c5),
+ RTD1319D_FUNC(pcie1),
+ RTD1319D_FUNC(sdio),
+ RTD1319D_FUNC(etn_led),
+ RTD1319D_FUNC(etn_phy),
+ RTD1319D_FUNC(spi),
+ RTD1319D_FUNC(pwm0_loc0),
+ RTD1319D_FUNC(pwm0_loc1),
+ RTD1319D_FUNC(pwm1_loc0),
+ RTD1319D_FUNC(pwm1_loc1),
+ RTD1319D_FUNC(pwm2_loc0),
+ RTD1319D_FUNC(pwm2_loc1),
+ RTD1319D_FUNC(pwm3_loc0),
+ RTD1319D_FUNC(pwm3_loc1),
+ RTD1319D_FUNC(qam_agc_if0),
+ RTD1319D_FUNC(qam_agc_if1),
+ RTD1319D_FUNC(spdif_optical_loc0),
+ RTD1319D_FUNC(spdif_optical_loc1),
+ RTD1319D_FUNC(usb_cc1),
+ RTD1319D_FUNC(usb_cc2),
+ RTD1319D_FUNC(vfd),
+ RTD1319D_FUNC(sd),
+ RTD1319D_FUNC(dmic_loc0),
+ RTD1319D_FUNC(dmic_loc1),
+ RTD1319D_FUNC(ai_loc0),
+ RTD1319D_FUNC(ai_loc1),
+ RTD1319D_FUNC(tdm_ai_loc0),
+ RTD1319D_FUNC(tdm_ai_loc1),
+ RTD1319D_FUNC(hi_loc0),
+ RTD1319D_FUNC(hi_m),
+ RTD1319D_FUNC(vtc_i2so),
+ RTD1319D_FUNC(vtc_i2si_loc0),
+ RTD1319D_FUNC(vtc_i2si_loc1),
+ RTD1319D_FUNC(vtc_dmic_loc0),
+ RTD1319D_FUNC(vtc_dmic_loc1),
+ RTD1319D_FUNC(vtc_tdm_loc0),
+ RTD1319D_FUNC(vtc_tdm_loc1),
+ RTD1319D_FUNC(dc_fan),
+ RTD1319D_FUNC(pll_test_loc0),
+ RTD1319D_FUNC(pll_test_loc1),
+ RTD1319D_FUNC(ir_rx),
+ RTD1319D_FUNC(uart2_disable),
+ RTD1319D_FUNC(gspi_disable),
+ RTD1319D_FUNC(hi_width_disable),
+ RTD1319D_FUNC(hi_width_1bit),
+ RTD1319D_FUNC(sf_disable),
+ RTD1319D_FUNC(sf_enable),
+ RTD1319D_FUNC(scpu_ejtag_loc0),
+ RTD1319D_FUNC(scpu_ejtag_loc1),
+ RTD1319D_FUNC(scpu_ejtag_loc2),
+ RTD1319D_FUNC(acpu_ejtag_loc0),
+ RTD1319D_FUNC(acpu_ejtag_loc1),
+ RTD1319D_FUNC(acpu_ejtag_loc2),
+ RTD1319D_FUNC(vcpu_ejtag_loc0),
+ RTD1319D_FUNC(vcpu_ejtag_loc1),
+ RTD1319D_FUNC(vcpu_ejtag_loc2),
+ RTD1319D_FUNC(secpu_ejtag_loc0),
+ RTD1319D_FUNC(secpu_ejtag_loc1),
+ RTD1319D_FUNC(secpu_ejtag_loc2),
+ RTD1319D_FUNC(aucpu_ejtag_loc0),
+ RTD1319D_FUNC(aucpu_ejtag_loc1),
+ RTD1319D_FUNC(aucpu_ejtag_loc2),
+ RTD1319D_FUNC(iso_tristate),
+ RTD1319D_FUNC(dbg_out0),
+ RTD1319D_FUNC(dbg_out1),
+ RTD1319D_FUNC(standby_dbg),
+ RTD1319D_FUNC(spdif),
+ RTD1319D_FUNC(arm_trace_debug_disable),
+ RTD1319D_FUNC(arm_trace_debug_enable),
+ RTD1319D_FUNC(aucpu_ejtag_disable),
+ RTD1319D_FUNC(acpu_ejtag_disable),
+ RTD1319D_FUNC(vcpu_ejtag_disable),
+ RTD1319D_FUNC(scpu_ejtag_disable),
+ RTD1319D_FUNC(secpu_ejtag_disable),
+ RTD1319D_FUNC(vtc_dmic_loc_disable),
+ RTD1319D_FUNC(vtc_tdm_disable),
+ RTD1319D_FUNC(vtc_i2si_disable),
+ RTD1319D_FUNC(tdm_ai_disable),
+ RTD1319D_FUNC(ai_disable),
+ RTD1319D_FUNC(spdif_disable),
+ RTD1319D_FUNC(hif_disable),
+ RTD1319D_FUNC(hif_enable),
+ RTD1319D_FUNC(test_loop),
+ RTD1319D_FUNC(pmic_pwrup),
+};
+
+#undef RTD1319D_FUNC
+
+static const struct rtd_pin_desc rtd1319d_iso_muxes[] = {
+ [RTD1319D_ISO_EMMC_RST_N] = RTK_PIN_MUX(emmc_rst_n, 0x0, GENMASK(3, 0),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x0, 0), "gpio"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x1, 0), "nf"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x2, 0), "emmc"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0xf, 0), "iso_tristate")),
+ [RTD1319D_ISO_EMMC_DD_SB] = RTK_PIN_MUX(emmc_dd_sb, 0x0, GENMASK(7, 4),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x0, 4), "gpio"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x2, 4), "emmc"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0xf, 4), "iso_tristate")),
+ [RTD1319D_ISO_EMMC_CLK] = RTK_PIN_MUX(emmc_clk, 0x0, GENMASK(11, 8),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x0, 8), "gpio"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x1, 8), "nf"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x2, 8), "emmc"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0xf, 8), "iso_tristate")),
+ [RTD1319D_ISO_EMMC_CMD] = RTK_PIN_MUX(emmc_cmd, 0x0, GENMASK(15, 12),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x0, 12), "gpio"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x1, 12), "nf"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x2, 12), "emmc"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0xf, 12), "iso_tristate")),
+ [RTD1319D_ISO_EMMC_DATA_0] = RTK_PIN_MUX(emmc_data_0, 0x0, GENMASK(19, 16),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x0, 16), "gpio"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x1, 16), "nf"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x2, 16), "emmc"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0xf, 16), "iso_tristate")),
+ [RTD1319D_ISO_EMMC_DATA_1] = RTK_PIN_MUX(emmc_data_1, 0x0, GENMASK(23, 20),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x0, 20), "gpio"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x1, 20), "nf"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x2, 20), "emmc"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0xf, 20), "iso_tristate")),
+ [RTD1319D_ISO_EMMC_DATA_2] = RTK_PIN_MUX(emmc_data_2, 0x0, GENMASK(27, 24),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x0, 24), "gpio"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x1, 24), "nf"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x2, 24), "emmc"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0xf, 24), "iso_tristate")),
+ [RTD1319D_ISO_EMMC_DATA_3] = RTK_PIN_MUX(emmc_data_3, 0x0, GENMASK(31, 28),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x0, 28), "gpio"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x1, 28), "nf"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x2, 28), "emmc"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0xf, 28), "iso_tristate")),
+
+ [RTD1319D_ISO_EMMC_DATA_4] = RTK_PIN_MUX(emmc_data_4, 0x4, GENMASK(3, 0),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x0, 0), "gpio"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x1, 0), "nf"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x2, 0), "emmc"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0xf, 0), "iso_tristate")),
+ [RTD1319D_ISO_EMMC_DATA_5] = RTK_PIN_MUX(emmc_data_5, 0x4, GENMASK(7, 4),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x0, 4), "gpio"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x1, 4), "nf"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x2, 4), "emmc"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0xf, 4), "iso_tristate")),
+ [RTD1319D_ISO_EMMC_DATA_6] = RTK_PIN_MUX(emmc_data_6, 0x4, GENMASK(11, 8),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x0, 8), "gpio"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x1, 8), "nf"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x2, 8), "emmc"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0xf, 8), "iso_tristate")),
+ [RTD1319D_ISO_EMMC_DATA_7] = RTK_PIN_MUX(emmc_data_7, 0x4, GENMASK(15, 12),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x0, 12), "gpio"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x1, 12), "nf"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x2, 12), "emmc"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0xf, 12), "iso_tristate")),
+ [RTD1319D_ISO_GPIO_78] = RTK_PIN_MUX(gpio_78, 0x4, GENMASK(19, 16),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x0, 16), "gpio"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x1, 16), "nf"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x3, 16), "pmic_pwrup"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0xf, 16), "iso_tristate")),
+ [RTD1319D_ISO_GPIO_79] = RTK_PIN_MUX(gpio_79, 0x4, GENMASK(23, 20),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x0, 20), "gpio"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x1, 20), "nf"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0xf, 20), "iso_tristate")),
+ [RTD1319D_ISO_GPIO_80] = RTK_PIN_MUX(gpio_80, 0x4, GENMASK(27, 24),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x0, 24), "gpio"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x1, 24), "nf"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0xf, 24), "iso_tristate")),
+ [RTD1319D_ISO_GPIO_81] = RTK_PIN_MUX(gpio_81, 0x4, GENMASK(31, 28),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x0, 28), "gpio"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x1, 28), "nf"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0xf, 28), "iso_tristate")),
+
+ [RTD1319D_ISO_GPIO_0] = RTK_PIN_MUX(gpio_0, 0x8, GENMASK(3, 0),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x0, 0), "gpio"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0xf, 0), "dbg_out1")),
+ [RTD1319D_ISO_GPIO_1] = RTK_PIN_MUX(gpio_1, 0x8, GENMASK(7, 4),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x0, 4), "gpio"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0xf, 4), "iso_tristate")),
+ [RTD1319D_ISO_GPIO_2] = RTK_PIN_MUX(gpio_2, 0x8, GENMASK(11, 8),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x0, 8), "gpio"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x1, 8), "standby_dbg"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x2, 8), "tp0"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x3, 8), "aucpu_ejtag_loc0"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x4, 8), "sc1"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x5, 8), "scpu_ejtag_loc0"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x6, 8), "acpu_ejtag_loc0"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x7, 8), "vcpu_ejtag_loc0"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x8, 8), "secpu_ejtag_loc0"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0xb, 8), "vtc_i2so"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0xc, 8), "ao"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0xf, 8), "dbg_out1")),
+ [RTD1319D_ISO_GPIO_3] = RTK_PIN_MUX(gpio_3, 0x8, GENMASK(15, 12),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x0, 12), "gpio"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x1, 12), "standby_dbg"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x2, 12), "tp0"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x3, 12), "aucpu_ejtag_loc0"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x4, 12), "sc1"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x5, 12), "scpu_ejtag_loc0"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x6, 12), "acpu_ejtag_loc0"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x7, 12), "vcpu_ejtag_loc0"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x8, 12), "secpu_ejtag_loc0"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0xb, 12), "vtc_i2so"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0xc, 12), "ao"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0xf, 12), "dbg_out1")),
+ [RTD1319D_ISO_GPIO_4] = RTK_PIN_MUX(gpio_4, 0x8, GENMASK(19, 16),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x0, 16), "gpio"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x2, 16), "tp0"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x3, 16), "aucpu_ejtag_loc0"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x5, 16), "scpu_ejtag_loc0"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x6, 16), "acpu_ejtag_loc0"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x7, 16), "vcpu_ejtag_loc0"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x8, 16), "secpu_ejtag_loc0"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0xb, 16), "vtc_i2so"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0xc, 16), "ao"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0xf, 16), "dbg_out1")),
+ [RTD1319D_ISO_GPIO_5] = RTK_PIN_MUX(gpio_5, 0x8, GENMASK(23, 20),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x0, 20), "gpio"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x3, 20), "aucpu_ejtag_loc0"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x4, 20), "sc1"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x5, 20), "scpu_ejtag_loc0"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x6, 20), "acpu_ejtag_loc0"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x7, 20), "vcpu_ejtag_loc0"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x8, 20), "secpu_ejtag_loc0"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0xf, 20), "dbg_out1")),
+ [RTD1319D_ISO_GPIO_6] = RTK_PIN_MUX(gpio_6, 0x8, GENMASK(27, 24),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x0, 24), "gpio"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x3, 24), "aucpu_ejtag_loc0"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x4, 24), "spdif_optical_loc1"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x5, 24), "scpu_ejtag_loc0"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x6, 24), "acpu_ejtag_loc0"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x7, 24), "vcpu_ejtag_loc0"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x8, 24), "secpu_ejtag_loc0"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0xf, 24), "dbg_out1")),
+ [RTD1319D_ISO_GPIO_7] = RTK_PIN_MUX(gpio_7, 0x8, GENMASK(31, 28),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x0, 28), "gpio"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0xf, 28), "dbg_out1")),
+
+ [RTD1319D_ISO_GPIO_8] = RTK_PIN_MUX(gpio_8, 0xc, GENMASK(3, 0),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x0, 0), "gpio"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x1, 0), "uart1"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x3, 0), "gspi_loc1"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0xf, 0), "iso_tristate")),
+ [RTD1319D_ISO_GPIO_9] = RTK_PIN_MUX(gpio_9, 0xc, GENMASK(7, 4),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x0, 4), "gpio"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x1, 4), "uart1"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x3, 4), "gspi_loc1"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0xf, 4), "iso_tristate")),
+ [RTD1319D_ISO_GPIO_10] = RTK_PIN_MUX(gpio_10, 0xc, GENMASK(11, 8),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x0, 8), "gpio"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x1, 8), "uart1"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x3, 8), "gspi_loc1"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0xf, 8), "iso_tristate")),
+ [RTD1319D_ISO_GPIO_11] = RTK_PIN_MUX(gpio_11, 0xc, GENMASK(15, 12),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x0, 12), "gpio"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x1, 12), "uart1"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x3, 12), "gspi_loc1"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0xf, 12), "iso_tristate")),
+ [RTD1319D_ISO_GPIO_12] = RTK_PIN_MUX(gpio_12, 0xc, GENMASK(19, 16),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x0, 16), "gpio"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x1, 16), "i2c0"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0xf, 16), "dbg_out0")),
+ [RTD1319D_ISO_GPIO_13] = RTK_PIN_MUX(gpio_13, 0xc, GENMASK(23, 20),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x0, 20), "gpio"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x1, 20), "i2c0"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0xf, 20), "dbg_out0")),
+ [RTD1319D_ISO_GPIO_14] = RTK_PIN_MUX(gpio_14, 0xc, GENMASK(27, 24),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x0, 24), "gpio"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x1, 24), "etn_led"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x3, 24), "etn_phy"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0xf, 24), "dbg_out1")),
+ [RTD1319D_ISO_GPIO_15] = RTK_PIN_MUX(gpio_15, 0xc, GENMASK(31, 28),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x0, 28), "gpio"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x1, 28), "etn_led"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x3, 28), "etn_phy"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0xf, 28), "dbg_out1")),
+
+ [RTD1319D_ISO_GPIO_16] = RTK_PIN_MUX(gpio_16, 0x10, GENMASK(3, 0),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x0, 0), "gpio"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x1, 0), "i2c1"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0xf, 0), "dbg_out0")),
+ [RTD1319D_ISO_GPIO_17] = RTK_PIN_MUX(gpio_17, 0x10, GENMASK(7, 4),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x0, 4), "gpio"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x1, 4), "i2c1"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0xf, 4), "dbg_out0")),
+ [RTD1319D_ISO_GPIO_18] = RTK_PIN_MUX(gpio_18, 0x10, GENMASK(11, 8),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x0, 8), "gpio"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x1, 8), "uart2_loc0"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x2, 8), "sc0"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x3, 8), "gspi_loc0"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x5, 8), "spi"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0xf, 8), "dbg_out1")),
+ [RTD1319D_ISO_GPIO_19] = RTK_PIN_MUX(gpio_19, 0x10, GENMASK(15, 12),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x0, 12), "gpio"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x1, 12), "uart2_loc0"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x2, 12), "sc0"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x3, 12), "gspi_loc0"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x5, 12), "spi"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0xf, 12), "dbg_out1")),
+ [RTD1319D_ISO_GPIO_20] = RTK_PIN_MUX(gpio_20, 0x10, GENMASK(19, 16),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x0, 16), "gpio"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x1, 16), "uart2_loc0"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x2, 16), "pwm0_loc1"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x3, 16), "gspi_loc0"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x4, 16), "sc0_data0"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x5, 16), "spi"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0xf, 16), "dbg_out1")),
+ [RTD1319D_ISO_GPIO_21] = RTK_PIN_MUX(gpio_21, 0x10, GENMASK(23, 20),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x0, 20), "gpio"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x2, 20), "pwm1_loc1"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x3, 20), "qam_agc_if0"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x6, 20), "spdif_optical_loc0"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0xf, 20), "dbg_out1")),
+ [RTD1319D_ISO_GPIO_22] = RTK_PIN_MUX(gpio_22, 0x10, GENMASK(27, 24),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x0, 24), "gpio"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x2, 24), "pwm2_loc1"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x4, 24), "pcie1"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0xf, 24), "iso_tristate")),
+ [RTD1319D_ISO_GPIO_23] = RTK_PIN_MUX(gpio_23, 0x10, GENMASK(31, 28),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x0, 28), "gpio"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x2, 28), "pwm3_loc1"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x3, 28), "qam_agc_if1"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0xf, 28), "iso_tristate")),
+
+ [RTD1319D_ISO_USB_CC2] = RTK_PIN_MUX(usb_cc2, 0x14, GENMASK(3, 0),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x0, 0), "gpio"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x1, 0), "usb_cc2"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0xf, 0), "iso_tristate")),
+ [RTD1319D_ISO_GPIO_25] = RTK_PIN_MUX(gpio_25, 0x14, GENMASK(7, 4),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x0, 4), "gpio"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x1, 4), "uart2_loc1"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0xf, 4), "iso_tristate")),
+ [RTD1319D_ISO_GPIO_26] = RTK_PIN_MUX(gpio_26, 0x14, GENMASK(11, 8),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x0, 8), "gpio"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x1, 8), "uart2_loc1"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x2, 8), "vfd"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x3, 8), "pwm0_loc0"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x4, 8), "i2c3"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0xf, 8), "dbg_out0")),
+ [RTD1319D_ISO_GPIO_27] = RTK_PIN_MUX(gpio_27, 0x14, GENMASK(15, 12),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x0, 12), "gpio"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x1, 12), "uart2_loc1"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x2, 12), "vfd"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x3, 12), "pwm1_loc0"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x4, 12), "i2c3"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x5, 12), "test_loop"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0xf, 12), "dbg_out0")),
+ [RTD1319D_ISO_GPIO_28] = RTK_PIN_MUX(gpio_28, 0x14, GENMASK(19, 16),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x0, 16), "gpio"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x1, 16), "uart2_loc1"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x2, 16), "vfd"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x3, 16), "pwm2_loc0"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0xf, 16), "iso_tristate")),
+ [RTD1319D_ISO_GPIO_29] = RTK_PIN_MUX(gpio_29, 0x14, GENMASK(23, 20),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x0, 20), "gpio"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x1, 20), "i2c5"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0xf, 20), "iso_tristate")),
+ [RTD1319D_ISO_GPIO_30] = RTK_PIN_MUX(gpio_30, 0x14, GENMASK(27, 24),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x0, 24), "gpio"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x4, 24), "sc0_data1"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0xf, 24), "iso_tristate")),
+ [RTD1319D_ISO_GPIO_31] = RTK_PIN_MUX(gpio_31, 0x14, GENMASK(31, 28),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x0, 28), "gpio"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x1, 28), "uart2_loc0"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x2, 28), "sc0"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x3, 28), "gspi_loc0"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x5, 28), "spi"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0xf, 28), "dbg_out1")),
+
+ [RTD1319D_ISO_GPIO_32] = RTK_PIN_MUX(gpio_32, 0x18, GENMASK(3, 0),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x0, 0), "gpio"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x1, 0), "sd"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x2, 0), "aucpu_ejtag_loc1"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x3, 0), "dmic_loc1"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x4, 0), "ai_loc1"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x5, 0), "scpu_ejtag_loc1"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x6, 0), "acpu_ejtag_loc1"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x7, 0), "vcpu_ejtag_loc1"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0xb, 0), "vtc_i2si_loc1"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0xe, 0), "secpu_ejtag_loc1"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0xf, 0), "iso_tristate")),
+ [RTD1319D_ISO_GPIO_33] = RTK_PIN_MUX(gpio_33, 0x18, GENMASK(7, 4),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x0, 4), "gpio"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x1, 4), "sd"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x2, 4), "aucpu_ejtag_loc1"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x3, 4), "dmic_loc1"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x4, 4), "ai_loc1"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x5, 4), "scpu_ejtag_loc1"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x6, 4), "acpu_ejtag_loc1"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x7, 4), "vcpu_ejtag_loc1"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0xe, 4), "secpu_ejtag_loc1"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0xf, 4), "iso_tristate")),
+ [RTD1319D_ISO_GPIO_34] = RTK_PIN_MUX(gpio_34, 0x18, GENMASK(11, 8),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x0, 8), "gpio"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x1, 8), "sd"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x3, 8), "dmic_loc1"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x4, 8), "ai_loc1"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x5, 8), "i2c4"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x6, 8), "sc1_data1"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0xf, 8), "dbg_out0")),
+ [RTD1319D_ISO_GPIO_35] = RTK_PIN_MUX(gpio_35, 0x18, GENMASK(15, 12),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x0, 12), "gpio"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x1, 12), "sd"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x3, 12), "dmic_loc1"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x5, 12), "i2c4"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x6, 12), "sc1_data2"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0xf, 12), "dbg_out0")),
+ [RTD1319D_ISO_HIF_DATA] = RTK_PIN_MUX(hif_data, 0x18, GENMASK(19, 16),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x0, 16), "gpio"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x1, 16), "sd"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x2, 16), "aucpu_ejtag_loc1"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x3, 16), "dmic_loc1"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x4, 16), "tdm_ai_loc1"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x5, 16), "scpu_ejtag_loc1"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x6, 16), "acpu_ejtag_loc1"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x7, 16), "vcpu_ejtag_loc1"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x8, 16), "ai_loc1"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x9, 16), "hi_loc0"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0xa, 16), "hi_m"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0xb, 16), "vtc_i2si_loc1"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0xc, 16), "vtc_tdm_loc1"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0xd, 16), "vtc_dmic_loc1"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0xe, 16), "secpu_ejtag_loc1"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0xf, 16), "iso_tristate")),
+ [RTD1319D_ISO_HIF_EN] = RTK_PIN_MUX(hif_en, 0x18, GENMASK(23, 20),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x0, 20), "gpio"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x1, 20), "sd"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x2, 20), "aucpu_ejtag_loc1"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x3, 20), "dmic_loc1"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x4, 20), "tdm_ai_loc1"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x5, 20), "scpu_ejtag_loc1"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x6, 20), "acpu_ejtag_loc1"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x7, 20), "vcpu_ejtag_loc1"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x8, 20), "ai_loc1"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x9, 20), "hi_loc0"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0xa, 20), "hi_m"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0xb, 20), "vtc_i2si_loc1"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0xc, 20), "vtc_tdm_loc1"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0xd, 20), "vtc_dmic_loc1"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0xe, 20), "secpu_ejtag_loc1"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0xf, 20), "iso_tristate")),
+ [RTD1319D_ISO_HIF_RDY] = RTK_PIN_MUX(hif_rdy, 0x18, GENMASK(27, 24),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x0, 24), "gpio"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x1, 24), "sd"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x3, 24), "dmic_loc1"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x4, 24), "tdm_ai_loc1"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x8, 24), "ai_loc1"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x9, 24), "hi_loc0"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0xa, 24), "hi_m"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0xb, 24), "vtc_i2si_loc1"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0xc, 24), "vtc_tdm_loc1"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0xd, 24), "vtc_dmic_loc1"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0xf, 24), "iso_tristate")),
+ [RTD1319D_ISO_HIF_CLK] = RTK_PIN_MUX(hif_clk, 0x18, GENMASK(31, 28),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x0, 28), "gpio"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x1, 28), "sd"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x2, 28), "aucpu_ejtag_loc1"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x3, 28), "dmic_loc1"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x4, 28), "tdm_ai_loc1"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x5, 28), "scpu_ejtag_loc1"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x6, 28), "acpu_ejtag_loc1"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x7, 28), "vcpu_ejtag_loc1"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x8, 28), "ai_loc1"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x9, 28), "hi_loc0"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0xa, 28), "hi_m"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0xb, 28), "vtc_i2si_loc1"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0xc, 28), "vtc_tdm_loc1"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0xd, 28), "vtc_dmic_loc1"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0xe, 28), "secpu_ejtag_loc1"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0xf, 28), "iso_tristate")),
+
+ [RTD1319D_ISO_GPIO_40] = RTK_PIN_MUX(gpio_40, 0x1c, GENMASK(3, 0),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x0, 0), "gpio"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x2, 0), "sdio"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0xf, 0), "iso_tristate")),
+ [RTD1319D_ISO_GPIO_41] = RTK_PIN_MUX(gpio_41, 0x1c, GENMASK(7, 4),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x0, 4), "gpio"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x2, 4), "sdio"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0xf, 4), "iso_tristate")),
+ [RTD1319D_ISO_GPIO_42] = RTK_PIN_MUX(gpio_42, 0x1c, GENMASK(11, 8),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x0, 8), "gpio"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x2, 8), "sdio"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0xf, 8), "iso_tristate")),
+ [RTD1319D_ISO_GPIO_43] = RTK_PIN_MUX(gpio_43, 0x1c, GENMASK(15, 12),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x0, 12), "gpio"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x2, 12), "sdio"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0xf, 12), "iso_tristate")),
+ [RTD1319D_ISO_GPIO_44] = RTK_PIN_MUX(gpio_44, 0x1c, GENMASK(19, 16),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x0, 16), "gpio"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x2, 16), "sdio"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0xf, 16), "iso_tristate")),
+ [RTD1319D_ISO_GPIO_45] = RTK_PIN_MUX(gpio_45, 0x1c, GENMASK(23, 20),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x0, 20), "gpio"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x2, 20), "sdio"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0xf, 20), "iso_tristate")),
+ [RTD1319D_ISO_GPIO_46] = RTK_PIN_MUX(gpio_46, 0x1c, GENMASK(27, 24),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x0, 24), "gpio"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x1, 24), "i2c5"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0xf, 24), "iso_tristate")),
+ [RTD1319D_ISO_GPIO_47] = RTK_PIN_MUX(gpio_47, 0x1c, GENMASK(31, 28),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x0, 28), "gpio"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x2, 28), "dc_fan"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x3, 28), "pwm3_loc0"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x4, 28), "sc0_data2"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0xf, 28), "dbg_out1")),
+
+ [RTD1319D_ISO_GPIO_48] = RTK_PIN_MUX(gpio_48, 0x20, GENMASK(3, 0),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x0, 0), "gpio"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x1, 0), "pll_test_loc1"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0xf, 0), "dbg_out0")),
+ [RTD1319D_ISO_GPIO_49] = RTK_PIN_MUX(gpio_49, 0x20, GENMASK(7, 4),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x0, 4), "gpio"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x1, 4), "pll_test_loc1"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0xf, 4), "dbg_out0")),
+ [RTD1319D_ISO_GPIO_50] = RTK_PIN_MUX(gpio_50, 0x20, GENMASK(11, 8),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x0, 8), "gpio"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x1, 8), "spdif"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0xf, 8), "dbg_out1")),
+ [RTD1319D_ISO_USB_CC1] = RTK_PIN_MUX(usb_cc1, 0x20, GENMASK(15, 12),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x0, 12), "gpio"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x1, 12), "usb_cc1"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0xf, 12), "iso_tristate")),
+ [RTD1319D_ISO_GPIO_52] = RTK_PIN_MUX(gpio_52, 0x20, GENMASK(19, 16),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x0, 16), "gpio"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x1, 16), "pll_test_loc0"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x4, 16), "sc1_data0"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0xf, 16), "dbg_out1")),
+ [RTD1319D_ISO_GPIO_53] = RTK_PIN_MUX(gpio_53, 0x20, GENMASK(23, 20),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x0, 20), "gpio"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x1, 20), "pll_test_loc0"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0xf, 20), "dbg_out1")),
+ [RTD1319D_ISO_IR_RX] = RTK_PIN_MUX(ir_rx, 0x20, GENMASK(27, 24),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x0, 24), "gpio"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x1, 24), "ir_rx"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x2, 24), "standby_dbg"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0xf, 24), "iso_tristate")),
+ [RTD1319D_ISO_UR0_RX] = RTK_PIN_MUX(ur0_rx, 0x20, GENMASK(31, 28),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x0, 28), "gpio"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x1, 28), "uart0"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0xf, 28), "iso_tristate")),
+
+ [RTD1319D_ISO_UR0_TX] = RTK_PIN_MUX(ur0_tx, 0x24, GENMASK(3, 0),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x0, 0), "gpio"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x1, 0), "uart0"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0xf, 0), "iso_tristate")),
+ [RTD1319D_ISO_GPIO_57] = RTK_PIN_MUX(gpio_57, 0x24, GENMASK(7, 4),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x0, 4), "gpio"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x1, 4), "tdm_ai_loc0"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x2, 4), "ai_loc0"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x3, 4), "dmic_loc0"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x4, 4), "tp0"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x6, 4), "acpu_ejtag_loc2"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x7, 4), "vcpu_ejtag_loc2"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x8, 4), "secpu_ejtag_loc2"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x9, 4), "aucpu_ejtag_loc2"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0xb, 4), "vtc_i2si_loc0"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0xc, 4), "vtc_tdm_loc0"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0xd, 4), "vtc_dmic_loc0"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0xe, 4), "scpu_ejtag_loc2"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0xf, 4), "dbg_out0")),
+ [RTD1319D_ISO_GPIO_58] = RTK_PIN_MUX(gpio_58, 0x24, GENMASK(11, 8),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x0, 8), "gpio"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x1, 8), "tdm_ai_loc0"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x2, 8), "ai_loc0"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x3, 8), "dmic_loc0"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x4, 8), "tp0"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x6, 8), "acpu_ejtag_loc2"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x7, 8), "vcpu_ejtag_loc2"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x8, 8), "secpu_ejtag_loc2"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x9, 8), "aucpu_ejtag_loc2"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0xb, 8), "vtc_i2si_loc0"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0xc, 8), "vtc_tdm_loc0"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0xd, 8), "vtc_dmic_loc0"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0xe, 8), "scpu_ejtag_loc2"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0xf, 8), "dbg_out0")),
+ [RTD1319D_ISO_GPIO_59] = RTK_PIN_MUX(gpio_59, 0x24, GENMASK(15, 12),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x0, 12), "gpio"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x1, 12), "tdm_ai_loc0"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x2, 12), "ai_loc0"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x3, 12), "dmic_loc0"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x4, 12), "tp0"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x6, 12), "acpu_ejtag_loc2"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x7, 12), "vcpu_ejtag_loc2"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x8, 12), "secpu_ejtag_loc2"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x9, 12), "aucpu_ejtag_loc2"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0xb, 12), "vtc_i2si_loc0"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0xc, 12), "vtc_tdm_loc0"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0xd, 12), "vtc_dmic_loc0"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0xe, 12), "scpu_ejtag_loc2"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0xf, 12), "dbg_out0")),
+ [RTD1319D_ISO_GPIO_60] = RTK_PIN_MUX(gpio_60, 0x24, GENMASK(19, 16),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x0, 16), "gpio"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x1, 16), "tdm_ai_loc0"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x2, 16), "ai_loc0"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x3, 16), "dmic_loc0"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x4, 16), "tp0"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x6, 16), "acpu_ejtag_loc2"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x7, 16), "vcpu_ejtag_loc2"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x8, 16), "secpu_ejtag_loc2"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x9, 16), "aucpu_ejtag_loc2"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0xb, 16), "vtc_i2si_loc0"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0xc, 16), "vtc_tdm_loc0"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0xd, 16), "vtc_dmic_loc0"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0xe, 16), "scpu_ejtag_loc2"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0xf, 16), "dbg_out0")),
+ [RTD1319D_ISO_GPIO_61] = RTK_PIN_MUX(gpio_61, 0x24, GENMASK(23, 20),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x0, 20), "gpio"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x1, 20), "ai_loc0"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x2, 20), "ao"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x3, 20), "dmic_loc0"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x4, 20), "tp0"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x5, 20), "tp1"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x6, 20), "acpu_ejtag_loc2"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x7, 20), "vcpu_ejtag_loc2"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x8, 20), "secpu_ejtag_loc2"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x9, 20), "aucpu_ejtag_loc2"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0xb, 20), "vtc_i2si_loc0"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0xe, 20), "scpu_ejtag_loc2"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0xf, 20), "dbg_out0")),
+ [RTD1319D_ISO_GPIO_62] = RTK_PIN_MUX(gpio_62, 0x24, GENMASK(27, 24),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x0, 24), "gpio"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x1, 24), "ai_loc0"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x2, 24), "ao"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x3, 24), "dmic_loc0"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x4, 24), "tp0"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x5, 24), "tp1"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0xf, 24), "iso_tristate")),
+ [RTD1319D_ISO_GPIO_63] = RTK_PIN_MUX(gpio_63, 0x24, GENMASK(31, 28),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x0, 28), "gpio"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x1, 28), "ai_loc0"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x2, 28), "ao"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x3, 28), "dmic_loc0"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x4, 28), "tp0"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x5, 28), "tp1"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0xf, 28), "iso_tristate")),
+
+ [RTD1319D_ISO_GPIO_64] = RTK_PIN_MUX(gpio_64, 0x28, GENMASK(3, 0),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x0, 0), "gpio"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x2, 0), "ao"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x3, 0), "dmic_loc0"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x4, 0), "tp0"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x5, 0), "tp1"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0xb, 0), "vtc_i2so"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0xf, 0), "iso_tristate")),
+
+ [RTD1319D_ISO_UR2_LOC] = RTK_PIN_MUX(ur2_loc, 0x120, GENMASK(1, 0),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x0, 0), "uart2_disable"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x1, 0), "uart2_loc0"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x2, 0), "uart2_loc1")),
+ [RTD1319D_ISO_GSPI_LOC] = RTK_PIN_MUX(gspi_loc, 0x120, GENMASK(3, 2),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x0, 2), "gspi_disable"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x1, 2), "gspi_loc0"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x2, 2), "gspi_loc1")),
+ [RTD1319D_ISO_HI_WIDTH] = RTK_PIN_MUX(hi_width, 0x120, GENMASK(9, 8),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x0, 8), "hi_width_disable"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x1, 8), "hi_width_1bit")),
+ [RTD1319D_ISO_SF_EN] = RTK_PIN_MUX(sf_en, 0x120, GENMASK(11, 11),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x0, 11), "sf_disable"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x1, 11), "sf_enable")),
+ [RTD1319D_ISO_ARM_TRACE_DBG_EN] = RTK_PIN_MUX(arm_trace_dbg_en, 0x120, GENMASK(12, 12),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x0, 12), "arm_trace_debug_disable"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x1, 12), "arm_trace_debug_enable")),
+ [RTD1319D_ISO_EJTAG_AUCPU_LOC] = RTK_PIN_MUX(ejtag_aucpu_loc, 0x120, GENMASK(16, 14),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x0, 14), "aucpu_ejtag_disable"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x1, 14), "aucpu_ejtag_loc0"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x2, 14), "aucpu_ejtag_loc1"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x4, 14), "aucpu_ejtag_loc2")),
+ [RTD1319D_ISO_EJTAG_ACPU_LOC] = RTK_PIN_MUX(ejtag_acpu_loc, 0x120, GENMASK(19, 17),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x0, 17), "acpu_ejtag_disable"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x1, 17), "acpu_ejtag_loc0"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x2, 17), "acpu_ejtag_loc1"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x4, 17), "acpu_ejtag_loc2")),
+ [RTD1319D_ISO_EJTAG_VCPU_LOC] = RTK_PIN_MUX(ejtag_vcpu_loc, 0x120, GENMASK(22, 20),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x0, 20), "vcpu_ejtag_disable"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x1, 20), "vcpu_ejtag_loc0"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x2, 20), "vcpu_ejtag_loc1"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x4, 20), "vcpu_ejtag_loc2")),
+ [RTD1319D_ISO_EJTAG_SCPU_LOC] = RTK_PIN_MUX(ejtag_scpu_loc, 0x120, GENMASK(25, 23),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x0, 23), "scpu_ejtag_disable"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x1, 23), "scpu_ejtag_loc0"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x2, 23), "scpu_ejtag_loc1"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x4, 23), "scpu_ejtag_loc2")),
+ [RTD1319D_ISO_DMIC_LOC] = RTK_PIN_MUX(dmic_loc, 0x120, GENMASK(27, 26),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x1, 26), "dmic_loc0"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x2, 26), "dmic_loc1")),
+
+ [RTD1319D_ISO_EJTAG_SECPU_LOC] = RTK_PIN_MUX(ejtag_secpu_loc, 0x124, GENMASK(20, 18),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x0, 18), "secpu_ejtag_disable"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x1, 18), "secpu_ejtag_loc0"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x2, 18), "secpu_ejtag_loc1"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x4, 18), "secpu_ejtag_loc2")),
+
+ [RTD1319D_ISO_VTC_DMIC_LOC] = RTK_PIN_MUX(vtc_dmic_loc, 0x128, GENMASK(1, 0),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x0, 0), "vtc_dmic_loc_disable"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x1, 0), "vtc_dmic_loc0"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x2, 0), "vtc_dmic_loc1")),
+ [RTD1319D_ISO_VTC_TDM_LOC] = RTK_PIN_MUX(vtc_tdm_loc, 0x128, GENMASK(3, 2),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x0, 2), "vtc_tdm_disable"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x1, 2), "vtc_tdm_loc0"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x2, 2), "vtc_tdm_loc1")),
+ [RTD1319D_ISO_VTC_I2SI_LOC] = RTK_PIN_MUX(vtc_i2si_loc, 0x128, GENMASK(5, 4),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x0, 4), "vtc_i2si_disable"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x1, 4), "vtc_i2si_loc0"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x2, 4), "vtc_i2si_loc1")),
+ [RTD1319D_ISO_TDM_AI_LOC] = RTK_PIN_MUX(tdm_ai_loc, 0x128, GENMASK(7, 6),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x0, 6), "tdm_ai_disable"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x1, 6), "tdm_ai_loc0"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x2, 6), "tdm_ai_loc1")),
+ [RTD1319D_ISO_AI_LOC] = RTK_PIN_MUX(ai_loc, 0x128, GENMASK(9, 8),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x0, 8), "ai_disable"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x1, 8), "ai_loc0"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x2, 8), "ai_loc1")),
+ [RTD1319D_ISO_SPDIF_LOC] = RTK_PIN_MUX(spdif_loc, 0x128, GENMASK(11, 10),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x0, 10), "spdif_disable"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x1, 10), "spdif_optical_loc0"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x2, 10), "spdif_optical_loc1")),
+
+ [RTD1319D_ISO_HIF_EN_LOC] = RTK_PIN_MUX(hif_en_loc, 0x12c, GENMASK(2, 0),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x2, 0), "hif_disable"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x5, 0), "hif_enable")),
+ [RTD1319D_ISO_SC0_LOC] = RTK_PIN_MUX(sc0_loc, 0x188, GENMASK(9, 8),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x0, 8), "sc0_data0"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x1, 8), "sc0_data1"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x2, 8), "sc0_data2")),
+ [RTD1319D_ISO_SC1_LOC] = RTK_PIN_MUX(sc1_loc, 0x188, GENMASK(11, 10),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x0, 10), "sc1_data0"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x1, 10), "sc1_data1"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x2, 10), "sc1_data2")),
+
+ [RTD1319D_ISO_TESTMODE] = {0},
+};
+
+static const struct rtd_pin_config_desc rtd1319d_iso_configs[] = {
+ [RTD1319D_ISO_SCAN_SWITCH] = RTK_PIN_CONFIG(scan_switch, 0x2c, 0, NA, NA, 0, 1, 2, PADDRI_4_8),
+ [RTD1319D_ISO_GPIO_18] = RTK_PIN_CONFIG(gpio_18, 0x2c, 3, 1, 2, 0, 3, 4, PADDRI_4_8),
+ [RTD1319D_ISO_GPIO_19] = RTK_PIN_CONFIG(gpio_19, 0x2c, 8, 1, 2, 0, 3, 4, PADDRI_4_8),
+ [RTD1319D_ISO_GPIO_20] = RTK_PIN_CONFIG(gpio_20, 0x2c, 13, 1, 2, 0, 3, 4, PADDRI_4_8),
+ [RTD1319D_ISO_GPIO_31] = RTK_PIN_CONFIG(gpio_31, 0x2c, 18, 1, 2, 0, 3, 4, PADDRI_4_8),
+ [RTD1319D_ISO_GPIO_8] = RTK_PIN_CONFIG(gpio_8, 0x2c, 23, 1, 2, 0, 3, 4, PADDRI_4_8),
+ [RTD1319D_ISO_GPIO_9] = RTK_PIN_CONFIG(gpio_9, 0x30, 0, 1, 2, 0, 3, 4, PADDRI_4_8),
+ [RTD1319D_ISO_GPIO_10] = RTK_PIN_CONFIG(gpio_10, 0x30, 5, 1, 2, 0, 3, 4, PADDRI_4_8),
+ [RTD1319D_ISO_GPIO_11] = RTK_PIN_CONFIG(gpio_11, 0x30, 10, 1, 2, 0, 3, 4, PADDRI_4_8),
+ [RTD1319D_ISO_GPIO_0] = RTK_PIN_CONFIG(gpio_0, 0x30, 15, 1, 2, 0, 3, 4, PADDRI_4_8),
+ [RTD1319D_ISO_GPIO_1] = RTK_PIN_CONFIG(gpio_1, 0x30, 20, 1, 2, 0, 3, 4, PADDRI_4_8),
+ [RTD1319D_ISO_GPIO_5] = RTK_PIN_CONFIG(gpio_5, 0x30, 25, 1, 2, 0, 3, 4, PADDRI_4_8),
+ [RTD1319D_ISO_GPIO_6] = RTK_PIN_CONFIG(gpio_6, 0x34, 0, 1, 2, 0, 3, 4, PADDRI_4_8),
+ [RTD1319D_ISO_GPIO_12] = RTK_PIN_CONFIG(gpio_12, 0x34, 5, 1, 2, 0, 3, 4, PADDRI_4_8),
+ [RTD1319D_ISO_GPIO_13] = RTK_PIN_CONFIG(gpio_13, 0x34, 10, 1, 2, 0, 3, 4, PADDRI_4_8),
+ [RTD1319D_ISO_GPIO_22] = RTK_PIN_CONFIG(gpio_22, 0x34, 15, 1, 2, 0, 3, 4, PADDRI_4_8),
+ [RTD1319D_ISO_USB_CC2] = RTK_PIN_CONFIG(usb_cc2, 0x34, 20, NA, NA, 0, 1, 2, PADDRI_4_8),
+ [RTD1319D_ISO_GPIO_29] = RTK_PIN_CONFIG(gpio_29, 0x34, 23, 1, 2, 0, 3, 4, PADDRI_4_8),
+ [RTD1319D_ISO_GPIO_46] = RTK_PIN_CONFIG(gpio_46, 0x38, 0, 1, 2, 0, 3, 4, PADDRI_4_8),
+ [RTD1319D_ISO_GPIO_47] = RTK_PIN_CONFIG(gpio_47, 0x38, 5, 1, 2, 0, 3, 4, PADDRI_4_8),
+ [RTD1319D_ISO_USB_CC1] = RTK_PIN_CONFIG(usb_cc1, 0x38, 10, NA, NA, 0, 1, 2, PADDRI_4_8),
+ [RTD1319D_ISO_WD_RSET] = RTK_PIN_CONFIG(wd_rset, 0x38, 13, 1, 2, 0, 3, 4, PADDRI_4_8),
+ [RTD1319D_ISO_IR_RX] = RTK_PIN_CONFIG(ir_rx, 0x38, 18, 1, 2, 0, 3, 4, PADDRI_4_8),
+ [RTD1319D_ISO_BOOT_SEL] = RTK_PIN_CONFIG(boot_sel, 0x38, 23, 0, 1, NA, 2, 3, PADDRI_4_8),
+ [RTD1319D_ISO_RESET_N] = RTK_PIN_CONFIG(reset_n, 0x38, 27, 0, 1, NA, 2, 3, PADDRI_4_8),
+ [RTD1319D_ISO_TESTMODE] = RTK_PIN_CONFIG(testmode, 0x3c, 0, 0, 1, NA, 2, 3, PADDRI_4_8),
+ [RTD1319D_ISO_GPIO_40] = RTK_PIN_CONFIG(gpio_40, 0x3c, 4, 0, 1, NA, 2, 12, NA),
+ [RTD1319D_ISO_GPIO_41] = RTK_PIN_CONFIG(gpio_41, 0x3c, 17, 0, 1, NA, 2, 12, NA),
+ [RTD1319D_ISO_GPIO_42] = RTK_PIN_CONFIG(gpio_42, 0x40, 0, 0, 1, NA, 2, 12, NA),
+ [RTD1319D_ISO_GPIO_43] = RTK_PIN_CONFIG(gpio_43, 0x40, 13, 0, 1, NA, 2, 12, NA),
+ [RTD1319D_ISO_GPIO_44] = RTK_PIN_CONFIG(gpio_44, 0x44, 0, 0, 1, NA, 2, 12, NA),
+ [RTD1319D_ISO_GPIO_45] = RTK_PIN_CONFIG(gpio_45, 0x44, 13, 0, 1, NA, 2, 12, NA),
+ [RTD1319D_ISO_EMMC_DATA_0] = RTK_PIN_CONFIG(emmc_data_0, 0x48, 0, 0, 1, NA, 2, 12, NA),
+ [RTD1319D_ISO_EMMC_DATA_1] = RTK_PIN_CONFIG(emmc_data_1, 0x48, 13, 0, 1, NA, 2, 12, NA),
+ [RTD1319D_ISO_EMMC_DATA_2] = RTK_PIN_CONFIG(emmc_data_2, 0x4c, 0, 0, 1, NA, 2, 12, NA),
+ [RTD1319D_ISO_EMMC_DATA_3] = RTK_PIN_CONFIG(emmc_data_3, 0x4c, 13, 0, 1, NA, 2, 12, NA),
+ [RTD1319D_ISO_EMMC_DATA_4] = RTK_PIN_CONFIG(emmc_data_4, 0x50, 0, 0, 1, NA, 2, 12, NA),
+ [RTD1319D_ISO_EMMC_DATA_5] = RTK_PIN_CONFIG(emmc_data_5, 0x50, 13, 0, 1, NA, 2, 12, NA),
+ [RTD1319D_ISO_EMMC_DATA_6] = RTK_PIN_CONFIG(emmc_data_6, 0x54, 0, 0, 1, NA, 2, 12, NA),
+ [RTD1319D_ISO_EMMC_DATA_7] = RTK_PIN_CONFIG(emmc_data_7, 0x54, 13, 0, 1, NA, 2, 12, NA),
+ [RTD1319D_ISO_EMMC_DD_SB] = RTK_PIN_CONFIG(emmc_dd_sb, 0x58, 0, 0, 1, NA, 2, 12, NA),
+ [RTD1319D_ISO_EMMC_RST_N] = RTK_PIN_CONFIG(emmc_rst_n, 0x58, 13, 0, 1, NA, 2, 12, NA),
+ [RTD1319D_ISO_EMMC_CMD] = RTK_PIN_CONFIG(emmc_cmd, 0x5c, 0, 0, 1, NA, 2, 13, NA),
+ [RTD1319D_ISO_EMMC_CLK] = RTK_PIN_CONFIG(emmc_clk, 0x5c, 14, 0, 1, NA, 2, 12, NA),
+ [RTD1319D_ISO_GPIO_80] = RTK_PIN_CONFIG(gpio_80, 0x60, 0, 0, 1, NA, 2, 12, NA),
+ [RTD1319D_ISO_GPIO_78] = RTK_PIN_CONFIG(gpio_78, 0x60, 13, 0, 1, NA, 2, 12, NA),
+ [RTD1319D_ISO_GPIO_79] = RTK_PIN_CONFIG(gpio_79, 0x64, 0, 0, 1, NA, 2, 12, NA),
+ [RTD1319D_ISO_GPIO_81] = RTK_PIN_CONFIG(gpio_81, 0x64, 13, 0, 1, NA, 2, 12, NA),
+ [RTD1319D_ISO_GPIO_2] = RTK_PIN_CONFIG(gpio_2, 0x64, 26, 1, 2, 0, 3, 4, PADDRI_4_8),
+ [RTD1319D_ISO_GPIO_3] = RTK_PIN_CONFIG(gpio_3, 0x68, 0, 1, 2, 0, 3, 4, PADDRI_4_8),
+ [RTD1319D_ISO_GPIO_4] = RTK_PIN_CONFIG(gpio_4, 0x68, 5, 1, 2, 0, 3, 4, PADDRI_4_8),
+ [RTD1319D_ISO_GPIO_57] = RTK_PIN_CONFIG(gpio_57, 0x68, 10, 1, 2, 0, 3, 4, PADDRI_4_8),
+ [RTD1319D_ISO_GPIO_58] = RTK_PIN_CONFIG(gpio_58, 0x68, 15, 1, 2, 0, 3, 4, PADDRI_4_8),
+ [RTD1319D_ISO_GPIO_59] = RTK_PIN_CONFIG(gpio_59, 0x68, 20, 1, 2, 0, 3, 4, PADDRI_4_8),
+ [RTD1319D_ISO_GPIO_60] = RTK_PIN_CONFIG(gpio_60, 0x68, 25, 1, 2, 0, 3, 4, PADDRI_4_8),
+ [RTD1319D_ISO_GPIO_61] = RTK_PIN_CONFIG(gpio_61, 0x6c, 0, 1, 2, 0, 3, 4, PADDRI_4_8),
+ [RTD1319D_ISO_GPIO_62] = RTK_PIN_CONFIG(gpio_62, 0x6c, 5, 1, 2, 0, 3, 4, PADDRI_4_8),
+ [RTD1319D_ISO_GPIO_63] = RTK_PIN_CONFIG(gpio_63, 0x6c, 10, 1, 2, 0, 3, 4, PADDRI_4_8),
+ [RTD1319D_ISO_GPIO_64] = RTK_PIN_CONFIG(gpio_64, 0x6c, 15, 1, 2, 0, 3, 4, PADDRI_4_8),
+ [RTD1319D_ISO_GPIO_7] = RTK_PIN_CONFIG(gpio_7, 0x6c, 20, 1, 2, 0, 3, 4, PADDRI_4_8),
+ [RTD1319D_ISO_GPIO_16] = RTK_PIN_CONFIG(gpio_16, 0x6c, 25, 1, 2, 0, 3, 4, PADDRI_4_8),
+ [RTD1319D_ISO_GPIO_17] = RTK_PIN_CONFIG(gpio_17, 0x70, 0, 1, 2, 0, 3, 4, PADDRI_4_8),
+ [RTD1319D_ISO_GPIO_21] = RTK_PIN_CONFIG(gpio_21, 0x70, 5, 1, 2, 0, 3, 4, PADDRI_4_8),
+ [RTD1319D_ISO_GPIO_23] = RTK_PIN_CONFIG(gpio_23, 0x70, 10, 1, 2, 0, 3, 4, PADDRI_4_8),
+ [RTD1319D_ISO_GPIO_50] = RTK_PIN_CONFIG(gpio_50, 0x70, 15, 1, 2, 0, 3, 4, PADDRI_4_8),
+ [RTD1319D_ISO_HIF_EN] = RTK_PIN_CONFIG(hif_en, 0x74, 0, 0, 1, NA, 2, 12, NA),
+ [RTD1319D_ISO_HIF_DATA] = RTK_PIN_CONFIG(hif_data, 0x74, 13, 0, 1, NA, 2, 12, NA),
+ [RTD1319D_ISO_GPIO_33] = RTK_PIN_CONFIG(gpio_33, 0x78, 0, 0, 1, NA, 2, 12, NA),
+ [RTD1319D_ISO_GPIO_32] = RTK_PIN_CONFIG(gpio_32, 0x78, 13, 0, 1, NA, 2, 12, NA),
+ [RTD1319D_ISO_HIF_CLK] = RTK_PIN_CONFIG(hif_clk, 0x7c, 0, 0, 1, NA, 2, 12, NA),
+ [RTD1319D_ISO_HIF_RDY] = RTK_PIN_CONFIG(hif_rdy, 0x7c, 13, 0, 1, NA, 2, 12, NA),
+ [RTD1319D_ISO_GPIO_14] = RTK_PIN_CONFIG(gpio_14, 0x7c, 26, 1, 2, 0, 3, 4, PADDRI_4_8),
+ [RTD1319D_ISO_GPIO_15] = RTK_PIN_CONFIG(gpio_15, 0x80, 0, 1, 2, 0, 3, 4, PADDRI_4_8),
+ [RTD1319D_ISO_GPIO_25] = RTK_PIN_CONFIG(gpio_25, 0x80, 5, 1, 2, 0, 3, 4, PADDRI_4_8),
+ [RTD1319D_ISO_GPIO_26] = RTK_PIN_CONFIG(gpio_26, 0x80, 10, 1, 2, 0, 3, 4, PADDRI_4_8),
+ [RTD1319D_ISO_GPIO_27] = RTK_PIN_CONFIG(gpio_27, 0x80, 16, 1, 2, 0, 3, 4, PADDRI_4_8),
+ [RTD1319D_ISO_GPIO_28] = RTK_PIN_CONFIG(gpio_28, 0x80, 22, 1, 2, 0, 3, 4, PADDRI_4_8),
+ [RTD1319D_ISO_GPIO_30] = RTK_PIN_CONFIG(gpio_30, 0x84, 0, 1, 2, 0, 3, 4, PADDRI_4_8),
+ [RTD1319D_ISO_GPIO_34] = RTK_PIN_CONFIG(gpio_34, 0x84, 5, 1, 2, 0, 3, 4, PADDRI_4_8),
+ [RTD1319D_ISO_GPIO_35] = RTK_PIN_CONFIG(gpio_35, 0x84, 10, 1, 2, 0, 3, 4, PADDRI_4_8),
+ [RTD1319D_ISO_UR0_TX] = RTK_PIN_CONFIG(ur0_tx, 0x84, 15, 1, 2, 0, 3, 4, PADDRI_4_8),
+ [RTD1319D_ISO_UR0_RX] = RTK_PIN_CONFIG(ur0_rx, 0x84, 20, 1, 2, 0, 3, 4, PADDRI_4_8),
+ [RTD1319D_ISO_GPIO_48] = RTK_PIN_CONFIG(gpio_48, 0x84, 25, 1, 2, 0, 3, 4, PADDRI_4_8),
+ [RTD1319D_ISO_GPIO_49] = RTK_PIN_CONFIG(gpio_49, 0x88, 0, 1, 2, 0, 3, 4, PADDRI_4_8),
+ [RTD1319D_ISO_GPIO_52] = RTK_PIN_CONFIG(gpio_52, 0x88, 5, 1, 2, 0, 3, 4, PADDRI_4_8),
+ [RTD1319D_ISO_GPIO_53] = RTK_PIN_CONFIG(gpio_53, 0x88, 10, 1, 2, 0, 3, 4, PADDRI_4_8),
+};
+
+static const struct rtd_pin_sconfig_desc rtd1319d_iso_sconfigs[] = {
+ RTK_PIN_SCONFIG(gpio_40, 0x3c, 7, 3, 10, 3, 13, 3),
+ RTK_PIN_SCONFIG(gpio_41, 0x3c, 20, 3, 23, 3, 26, 3),
+ RTK_PIN_SCONFIG(gpio_42, 0x40, 3, 3, 6, 3, 9, 3),
+ RTK_PIN_SCONFIG(gpio_43, 0x40, 16, 3, 19, 3, 22, 3),
+ RTK_PIN_SCONFIG(gpio_44, 0x44, 3, 3, 6, 3, 9, 3),
+ RTK_PIN_SCONFIG(gpio_45, 0x44, 16, 3, 19, 3, 22, 3),
+ RTK_PIN_SCONFIG(emmc_data_0, 0x48, 3, 3, 6, 3, 9, 3),
+ RTK_PIN_SCONFIG(emmc_data_1, 0x48, 16, 3, 19, 3, 22, 3),
+ RTK_PIN_SCONFIG(emmc_data_2, 0x4c, 3, 3, 6, 3, 9, 3),
+ RTK_PIN_SCONFIG(emmc_data_3, 0x4c, 16, 3, 19, 3, 22, 3),
+ RTK_PIN_SCONFIG(emmc_data_4, 0x50, 3, 3, 6, 3, 9, 3),
+ RTK_PIN_SCONFIG(emmc_data_5, 0x50, 16, 3, 19, 3, 22, 3),
+ RTK_PIN_SCONFIG(emmc_data_6, 0x54, 3, 3, 6, 3, 9, 3),
+ RTK_PIN_SCONFIG(emmc_data_7, 0x54, 16, 3, 19, 3, 22, 3),
+ RTK_PIN_SCONFIG(emmc_dd_sb, 0x58, 3, 3, 6, 3, 9, 3),
+ RTK_PIN_SCONFIG(emmc_rst_n, 0x58, 16, 3, 19, 3, 22, 3),
+ RTK_PIN_SCONFIG(emmc_cmd, 0x5c, 3, 3, 6, 3, 9, 3),
+ RTK_PIN_SCONFIG(emmc_clk, 0x5c, 17, 3, 20, 3, 23, 3),
+ RTK_PIN_SCONFIG(gpio_80, 0x60, 3, 3, 6, 3, 9, 3),
+ RTK_PIN_SCONFIG(gpio_78, 0x60, 16, 3, 19, 3, 22, 3),
+ RTK_PIN_SCONFIG(gpio_79, 0x64, 3, 3, 6, 3, 9, 3),
+ RTK_PIN_SCONFIG(gpio_81, 0x64, 16, 3, 19, 3, 22, 3),
+ RTK_PIN_SCONFIG(hif_en, 0x74, 3, 3, 6, 3, 9, 3),
+ RTK_PIN_SCONFIG(hif_data, 0x74, 16, 3, 19, 3, 22, 3),
+ RTK_PIN_SCONFIG(gpio_33, 0x78, 3, 3, 6, 3, 9, 3),
+ RTK_PIN_SCONFIG(gpio_32, 0x78, 16, 3, 19, 3, 22, 3),
+ RTK_PIN_SCONFIG(hif_clk, 0x7c, 3, 3, 6, 3, 9, 3),
+ RTK_PIN_SCONFIG(hif_rdy, 0x7c, 16, 3, 19, 3, 22, 3),
+};
+
+static const struct rtd_pinctrl_desc rtd1319d_iso_pinctrl_desc = {
+ .pins = rtd1319d_iso_pins,
+ .num_pins = ARRAY_SIZE(rtd1319d_iso_pins),
+ .groups = rtd1319d_pin_groups,
+ .num_groups = ARRAY_SIZE(rtd1319d_pin_groups),
+ .functions = rtd1319d_pin_functions,
+ .num_functions = ARRAY_SIZE(rtd1319d_pin_functions),
+ .muxes = rtd1319d_iso_muxes,
+ .num_muxes = ARRAY_SIZE(rtd1319d_iso_muxes),
+ .configs = rtd1319d_iso_configs,
+ .num_configs = ARRAY_SIZE(rtd1319d_iso_configs),
+ .sconfigs = rtd1319d_iso_sconfigs,
+ .num_sconfigs = ARRAY_SIZE(rtd1319d_iso_sconfigs),
+};
+
+static int rtd1319d_pinctrl_probe(struct platform_device *pdev)
+{
+ return rtd_pinctrl_probe(pdev, &rtd1319d_iso_pinctrl_desc);
+}
+
+static const struct of_device_id rtd1319d_pinctrl_of_match[] = {
+ { .compatible = "realtek,rtd1319d-pinctrl", },
+ {},
+};
+
+static struct platform_driver rtd1319d_pinctrl_driver = {
+ .driver = {
+ .name = "rtd1319d-pinctrl",
+ .of_match_table = rtd1319d_pinctrl_of_match,
+ },
+ .probe = rtd1319d_pinctrl_probe,
+};
+
+static int __init rtd1319d_pinctrl_init(void)
+{
+ return platform_driver_register(&rtd1319d_pinctrl_driver);
+}
+arch_initcall(rtd1319d_pinctrl_init);
+
+static void __exit rtd1319d_pinctrl_exit(void)
+{
+ platform_driver_unregister(&rtd1319d_pinctrl_driver);
+}
+module_exit(rtd1319d_pinctrl_exit);
+
+MODULE_LICENSE("GPL");
+MODULE_AUTHOR("Realtek Semiconductor Corporation");
+MODULE_DESCRIPTION("Realtek DHC SoC RTD1319D pinctrl driver");
diff --git a/drivers/pinctrl/realtek/pinctrl-rtd1619b.c b/drivers/pinctrl/realtek/pinctrl-rtd1619b.c
new file mode 100644
index 0000000000..b07e50d635
--- /dev/null
+++ b/drivers/pinctrl/realtek/pinctrl-rtd1619b.c
@@ -0,0 +1,1601 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Realtek DHC 1619B pin controller driver
+ *
+ * Copyright (c) 2023 Realtek Semiconductor Corp.
+ *
+ */
+
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/platform_device.h>
+#include <linux/pinctrl/pinctrl.h>
+
+#include "pinctrl-rtd.h"
+
+enum rtd16xxb_iso_pins {
+ RTD1619B_ISO_GPIO_0 = 0,
+ RTD1619B_ISO_GPIO_1,
+ RTD1619B_ISO_GPIO_2,
+ RTD1619B_ISO_GPIO_3,
+ RTD1619B_ISO_GPIO_4,
+ RTD1619B_ISO_GPIO_5,
+ RTD1619B_ISO_GPIO_6,
+ RTD1619B_ISO_GPIO_7,
+ RTD1619B_ISO_GPIO_8,
+ RTD1619B_ISO_GPIO_9,
+ RTD1619B_ISO_GPIO_10,
+ RTD1619B_ISO_GPIO_11,
+ RTD1619B_ISO_GPIO_12,
+ RTD1619B_ISO_GPIO_13,
+ RTD1619B_ISO_GPIO_14,
+ RTD1619B_ISO_GPIO_15,
+ RTD1619B_ISO_GPIO_16,
+ RTD1619B_ISO_GPIO_17,
+ RTD1619B_ISO_GPIO_18,
+ RTD1619B_ISO_GPIO_19,
+ RTD1619B_ISO_GPIO_20,
+ RTD1619B_ISO_GPIO_21,
+ RTD1619B_ISO_GPIO_22,
+ RTD1619B_ISO_GPIO_23,
+ RTD1619B_ISO_USB_CC2,
+ RTD1619B_ISO_GPIO_25,
+ RTD1619B_ISO_GPIO_26,
+ RTD1619B_ISO_GPIO_27,
+ RTD1619B_ISO_GPIO_28,
+ RTD1619B_ISO_GPIO_29,
+ RTD1619B_ISO_GPIO_30,
+ RTD1619B_ISO_GPIO_31,
+ RTD1619B_ISO_GPIO_32,
+ RTD1619B_ISO_GPIO_33,
+ RTD1619B_ISO_GPIO_34,
+ RTD1619B_ISO_GPIO_35,
+ RTD1619B_ISO_HIF_DATA,
+ RTD1619B_ISO_HIF_EN,
+ RTD1619B_ISO_HIF_RDY,
+ RTD1619B_ISO_HIF_CLK,
+ RTD1619B_ISO_GPIO_40,
+ RTD1619B_ISO_GPIO_41,
+ RTD1619B_ISO_GPIO_42,
+ RTD1619B_ISO_GPIO_43,
+ RTD1619B_ISO_GPIO_44,
+ RTD1619B_ISO_GPIO_45,
+ RTD1619B_ISO_GPIO_46,
+ RTD1619B_ISO_GPIO_47,
+ RTD1619B_ISO_GPIO_48,
+ RTD1619B_ISO_GPIO_49,
+ RTD1619B_ISO_GPIO_50,
+ RTD1619B_ISO_USB_CC1,
+ RTD1619B_ISO_GPIO_52,
+ RTD1619B_ISO_GPIO_53,
+ RTD1619B_ISO_IR_RX,
+ RTD1619B_ISO_UR0_RX,
+ RTD1619B_ISO_UR0_TX,
+ RTD1619B_ISO_GPIO_57,
+ RTD1619B_ISO_GPIO_58,
+ RTD1619B_ISO_GPIO_59,
+ RTD1619B_ISO_GPIO_60,
+ RTD1619B_ISO_GPIO_61,
+ RTD1619B_ISO_GPIO_62,
+ RTD1619B_ISO_GPIO_63,
+ RTD1619B_ISO_GPIO_64,
+ RTD1619B_ISO_GPIO_65,
+ RTD1619B_ISO_GPIO_66,
+ RTD1619B_ISO_GPIO_67,
+ RTD1619B_ISO_GPIO_68,
+ RTD1619B_ISO_GPIO_69,
+ RTD1619B_ISO_GPIO_70,
+ RTD1619B_ISO_GPIO_71,
+ RTD1619B_ISO_GPIO_72,
+ RTD1619B_ISO_GPIO_73,
+ RTD1619B_ISO_GPIO_74,
+ RTD1619B_ISO_GPIO_75,
+ RTD1619B_ISO_GPIO_76,
+ RTD1619B_ISO_EMMC_CMD,
+ RTD1619B_ISO_SPI_CE_N,
+ RTD1619B_ISO_SPI_SCK,
+ RTD1619B_ISO_SPI_SO,
+ RTD1619B_ISO_SPI_SI,
+ RTD1619B_ISO_EMMC_RST_N,
+ RTD1619B_ISO_EMMC_DD_SB,
+ RTD1619B_ISO_EMMC_CLK,
+ RTD1619B_ISO_EMMC_DATA_0,
+ RTD1619B_ISO_EMMC_DATA_1,
+ RTD1619B_ISO_EMMC_DATA_2,
+ RTD1619B_ISO_EMMC_DATA_3,
+ RTD1619B_ISO_EMMC_DATA_4,
+ RTD1619B_ISO_EMMC_DATA_5,
+ RTD1619B_ISO_EMMC_DATA_6,
+ RTD1619B_ISO_EMMC_DATA_7,
+ RTD1619B_ISO_UR2_LOC,
+ RTD1619B_ISO_GSPI_LOC,
+ RTD1619B_ISO_SDIO_LOC,
+ RTD1619B_ISO_HI_LOC,
+ RTD1619B_ISO_HI_WIDTH,
+ RTD1619B_ISO_SF_EN,
+ RTD1619B_ISO_ARM_TRACE_DBG_EN,
+ RTD1619B_ISO_PWM_01_OPEN_DRAIN_EN_LOC0,
+ RTD1619B_ISO_PWM_23_OPEN_DRAIN_EN_LOC0,
+ RTD1619B_ISO_PWM_01_OPEN_DRAIN_EN_LOC1,
+ RTD1619B_ISO_PWM_23_OPEN_DRAIN_EN_LOC1,
+ RTD1619B_ISO_EJTAG_ACPU_LOC,
+ RTD1619B_ISO_EJTAG_VCPU_LOC,
+ RTD1619B_ISO_EJTAG_SCPU_LOC,
+ RTD1619B_ISO_DMIC_LOC,
+ RTD1619B_ISO_ISO_GSPI_LOC,
+ RTD1619B_ISO_EJTAG_VE3_LOC,
+ RTD1619B_ISO_EJTAG_AUCPU0_LOC,
+ RTD1619B_ISO_EJTAG_AUCPU1_LOC,
+};
+
+static const struct pinctrl_pin_desc rtd1619b_iso_pins[] = {
+ PINCTRL_PIN(RTD1619B_ISO_GPIO_0, "gpio_0"),
+ PINCTRL_PIN(RTD1619B_ISO_GPIO_1, "gpio_1"),
+ PINCTRL_PIN(RTD1619B_ISO_GPIO_2, "gpio_2"),
+ PINCTRL_PIN(RTD1619B_ISO_GPIO_3, "gpio_3"),
+ PINCTRL_PIN(RTD1619B_ISO_GPIO_4, "gpio_4"),
+ PINCTRL_PIN(RTD1619B_ISO_GPIO_5, "gpio_5"),
+ PINCTRL_PIN(RTD1619B_ISO_GPIO_6, "gpio_6"),
+ PINCTRL_PIN(RTD1619B_ISO_GPIO_7, "gpio_7"),
+ PINCTRL_PIN(RTD1619B_ISO_GPIO_8, "gpio_8"),
+ PINCTRL_PIN(RTD1619B_ISO_GPIO_9, "gpio_9"),
+ PINCTRL_PIN(RTD1619B_ISO_GPIO_10, "gpio_10"),
+ PINCTRL_PIN(RTD1619B_ISO_GPIO_11, "gpio_11"),
+ PINCTRL_PIN(RTD1619B_ISO_GPIO_12, "gpio_12"),
+ PINCTRL_PIN(RTD1619B_ISO_GPIO_13, "gpio_13"),
+ PINCTRL_PIN(RTD1619B_ISO_GPIO_14, "gpio_14"),
+ PINCTRL_PIN(RTD1619B_ISO_GPIO_15, "gpio_15"),
+ PINCTRL_PIN(RTD1619B_ISO_GPIO_16, "gpio_16"),
+ PINCTRL_PIN(RTD1619B_ISO_GPIO_17, "gpio_17"),
+ PINCTRL_PIN(RTD1619B_ISO_GPIO_18, "gpio_18"),
+ PINCTRL_PIN(RTD1619B_ISO_GPIO_19, "gpio_19"),
+ PINCTRL_PIN(RTD1619B_ISO_GPIO_20, "gpio_20"),
+ PINCTRL_PIN(RTD1619B_ISO_GPIO_21, "gpio_21"),
+ PINCTRL_PIN(RTD1619B_ISO_GPIO_22, "gpio_22"),
+ PINCTRL_PIN(RTD1619B_ISO_GPIO_23, "gpio_23"),
+ PINCTRL_PIN(RTD1619B_ISO_USB_CC2, "usb_cc2"),
+ PINCTRL_PIN(RTD1619B_ISO_GPIO_25, "gpio_25"),
+ PINCTRL_PIN(RTD1619B_ISO_GPIO_26, "gpio_26"),
+ PINCTRL_PIN(RTD1619B_ISO_GPIO_27, "gpio_27"),
+ PINCTRL_PIN(RTD1619B_ISO_GPIO_28, "gpio_28"),
+ PINCTRL_PIN(RTD1619B_ISO_GPIO_29, "gpio_29"),
+ PINCTRL_PIN(RTD1619B_ISO_GPIO_30, "gpio_30"),
+ PINCTRL_PIN(RTD1619B_ISO_GPIO_31, "gpio_31"),
+ PINCTRL_PIN(RTD1619B_ISO_GPIO_32, "gpio_32"),
+ PINCTRL_PIN(RTD1619B_ISO_GPIO_33, "gpio_33"),
+ PINCTRL_PIN(RTD1619B_ISO_GPIO_34, "gpio_34"),
+ PINCTRL_PIN(RTD1619B_ISO_GPIO_35, "gpio_35"),
+ PINCTRL_PIN(RTD1619B_ISO_HIF_DATA, "hif_data"),
+ PINCTRL_PIN(RTD1619B_ISO_HIF_EN, "hif_en"),
+ PINCTRL_PIN(RTD1619B_ISO_HIF_RDY, "hif_rdy"),
+ PINCTRL_PIN(RTD1619B_ISO_HIF_CLK, "hif_clk"),
+ PINCTRL_PIN(RTD1619B_ISO_GPIO_40, "gpio_40"),
+ PINCTRL_PIN(RTD1619B_ISO_GPIO_41, "gpio_41"),
+ PINCTRL_PIN(RTD1619B_ISO_GPIO_42, "gpio_42"),
+ PINCTRL_PIN(RTD1619B_ISO_GPIO_43, "gpio_43"),
+ PINCTRL_PIN(RTD1619B_ISO_GPIO_44, "gpio_44"),
+ PINCTRL_PIN(RTD1619B_ISO_GPIO_45, "gpio_45"),
+ PINCTRL_PIN(RTD1619B_ISO_GPIO_46, "gpio_46"),
+ PINCTRL_PIN(RTD1619B_ISO_GPIO_47, "gpio_47"),
+ PINCTRL_PIN(RTD1619B_ISO_GPIO_48, "gpio_48"),
+ PINCTRL_PIN(RTD1619B_ISO_GPIO_49, "gpio_49"),
+ PINCTRL_PIN(RTD1619B_ISO_GPIO_50, "gpio_50"),
+ PINCTRL_PIN(RTD1619B_ISO_USB_CC1, "usb_cc1"),
+ PINCTRL_PIN(RTD1619B_ISO_GPIO_52, "gpio_52"),
+ PINCTRL_PIN(RTD1619B_ISO_GPIO_53, "gpio_53"),
+ PINCTRL_PIN(RTD1619B_ISO_IR_RX, "ir_rx"),
+ PINCTRL_PIN(RTD1619B_ISO_UR0_RX, "ur0_rx"),
+ PINCTRL_PIN(RTD1619B_ISO_UR0_TX, "ur0_tx"),
+ PINCTRL_PIN(RTD1619B_ISO_GPIO_57, "gpio_57"),
+ PINCTRL_PIN(RTD1619B_ISO_GPIO_58, "gpio_58"),
+ PINCTRL_PIN(RTD1619B_ISO_GPIO_59, "gpio_59"),
+ PINCTRL_PIN(RTD1619B_ISO_GPIO_60, "gpio_60"),
+ PINCTRL_PIN(RTD1619B_ISO_GPIO_61, "gpio_61"),
+ PINCTRL_PIN(RTD1619B_ISO_GPIO_62, "gpio_62"),
+ PINCTRL_PIN(RTD1619B_ISO_GPIO_63, "gpio_63"),
+ PINCTRL_PIN(RTD1619B_ISO_GPIO_64, "gpio_64"),
+ PINCTRL_PIN(RTD1619B_ISO_GPIO_65, "gpio_65"),
+ PINCTRL_PIN(RTD1619B_ISO_GPIO_66, "gpio_66"),
+ PINCTRL_PIN(RTD1619B_ISO_GPIO_67, "gpio_67"),
+ PINCTRL_PIN(RTD1619B_ISO_GPIO_68, "gpio_68"),
+ PINCTRL_PIN(RTD1619B_ISO_GPIO_69, "gpio_69"),
+ PINCTRL_PIN(RTD1619B_ISO_GPIO_70, "gpio_70"),
+ PINCTRL_PIN(RTD1619B_ISO_GPIO_71, "gpio_71"),
+ PINCTRL_PIN(RTD1619B_ISO_GPIO_72, "gpio_72"),
+ PINCTRL_PIN(RTD1619B_ISO_GPIO_73, "gpio_73"),
+ PINCTRL_PIN(RTD1619B_ISO_GPIO_74, "gpio_74"),
+ PINCTRL_PIN(RTD1619B_ISO_GPIO_75, "gpio_75"),
+ PINCTRL_PIN(RTD1619B_ISO_GPIO_76, "gpio_76"),
+ PINCTRL_PIN(RTD1619B_ISO_EMMC_CMD, "emmc_cmd"),
+ PINCTRL_PIN(RTD1619B_ISO_SPI_CE_N, "spi_ce_n"),
+ PINCTRL_PIN(RTD1619B_ISO_SPI_SCK, "spi_sck"),
+ PINCTRL_PIN(RTD1619B_ISO_SPI_SO, "spi_so"),
+ PINCTRL_PIN(RTD1619B_ISO_SPI_SI, "spi_si"),
+ PINCTRL_PIN(RTD1619B_ISO_EMMC_RST_N, "emmc_rst_n"),
+ PINCTRL_PIN(RTD1619B_ISO_EMMC_DD_SB, "emmc_dd_sb"),
+ PINCTRL_PIN(RTD1619B_ISO_EMMC_CLK, "emmc_clk"),
+ PINCTRL_PIN(RTD1619B_ISO_EMMC_DATA_0, "emmc_data_0"),
+ PINCTRL_PIN(RTD1619B_ISO_EMMC_DATA_1, "emmc_data_1"),
+ PINCTRL_PIN(RTD1619B_ISO_EMMC_DATA_2, "emmc_data_2"),
+ PINCTRL_PIN(RTD1619B_ISO_EMMC_DATA_3, "emmc_data_3"),
+ PINCTRL_PIN(RTD1619B_ISO_EMMC_DATA_4, "emmc_data_4"),
+ PINCTRL_PIN(RTD1619B_ISO_EMMC_DATA_5, "emmc_data_5"),
+ PINCTRL_PIN(RTD1619B_ISO_EMMC_DATA_6, "emmc_data_6"),
+ PINCTRL_PIN(RTD1619B_ISO_EMMC_DATA_7, "emmc_data_7"),
+ PINCTRL_PIN(RTD1619B_ISO_UR2_LOC, "ur2_loc"),
+ PINCTRL_PIN(RTD1619B_ISO_GSPI_LOC, "gspi_loc"),
+ PINCTRL_PIN(RTD1619B_ISO_SDIO_LOC, "sdio_loc"),
+ PINCTRL_PIN(RTD1619B_ISO_HI_LOC, "hi_loc"),
+ PINCTRL_PIN(RTD1619B_ISO_HI_WIDTH, "hi_width"),
+ PINCTRL_PIN(RTD1619B_ISO_SF_EN, "sf_en"),
+ PINCTRL_PIN(RTD1619B_ISO_ARM_TRACE_DBG_EN, "arm_trace_dbg_en"),
+ PINCTRL_PIN(RTD1619B_ISO_PWM_01_OPEN_DRAIN_EN_LOC0, "pwm_01_open_drain_en_loc0"),
+ PINCTRL_PIN(RTD1619B_ISO_PWM_23_OPEN_DRAIN_EN_LOC0, "pwm_23_open_drain_en_loc0"),
+ PINCTRL_PIN(RTD1619B_ISO_PWM_01_OPEN_DRAIN_EN_LOC1, "pwm_01_open_drain_en_loc1"),
+ PINCTRL_PIN(RTD1619B_ISO_PWM_23_OPEN_DRAIN_EN_LOC1, "pwm_23_open_drain_en_loc1"),
+ PINCTRL_PIN(RTD1619B_ISO_EJTAG_ACPU_LOC, "ejtag_acpu_loc"),
+ PINCTRL_PIN(RTD1619B_ISO_EJTAG_VCPU_LOC, "ejtag_vcpu_loc"),
+ PINCTRL_PIN(RTD1619B_ISO_EJTAG_SCPU_LOC, "ejtag_scpu_loc"),
+ PINCTRL_PIN(RTD1619B_ISO_DMIC_LOC, "dmic_loc"),
+ PINCTRL_PIN(RTD1619B_ISO_ISO_GSPI_LOC, "iso_gspi_loc"),
+ PINCTRL_PIN(RTD1619B_ISO_EJTAG_VE3_LOC, "ejtag_ve3_loc"),
+ PINCTRL_PIN(RTD1619B_ISO_EJTAG_AUCPU0_LOC, "ejtag_aucpu0_loc"),
+ PINCTRL_PIN(RTD1619B_ISO_EJTAG_AUCPU1_LOC, "ejtag_aucpu1_loc"),
+};
+
+#define DECLARE_RTD1619B_PIN(_pin, _name) \
+ static const unsigned int rtd1619b_## _name ##_pins[] = { _pin }
+
+DECLARE_RTD1619B_PIN(RTD1619B_ISO_GPIO_0, gpio_0);
+DECLARE_RTD1619B_PIN(RTD1619B_ISO_GPIO_1, gpio_1);
+DECLARE_RTD1619B_PIN(RTD1619B_ISO_GPIO_2, gpio_2);
+DECLARE_RTD1619B_PIN(RTD1619B_ISO_GPIO_3, gpio_3);
+DECLARE_RTD1619B_PIN(RTD1619B_ISO_GPIO_4, gpio_4);
+DECLARE_RTD1619B_PIN(RTD1619B_ISO_GPIO_5, gpio_5);
+DECLARE_RTD1619B_PIN(RTD1619B_ISO_GPIO_6, gpio_6);
+DECLARE_RTD1619B_PIN(RTD1619B_ISO_GPIO_7, gpio_7);
+DECLARE_RTD1619B_PIN(RTD1619B_ISO_GPIO_8, gpio_8);
+DECLARE_RTD1619B_PIN(RTD1619B_ISO_GPIO_9, gpio_9);
+DECLARE_RTD1619B_PIN(RTD1619B_ISO_GPIO_10, gpio_10);
+DECLARE_RTD1619B_PIN(RTD1619B_ISO_GPIO_11, gpio_11);
+DECLARE_RTD1619B_PIN(RTD1619B_ISO_GPIO_12, gpio_12);
+DECLARE_RTD1619B_PIN(RTD1619B_ISO_GPIO_13, gpio_13);
+DECLARE_RTD1619B_PIN(RTD1619B_ISO_GPIO_14, gpio_14);
+DECLARE_RTD1619B_PIN(RTD1619B_ISO_GPIO_15, gpio_15);
+DECLARE_RTD1619B_PIN(RTD1619B_ISO_GPIO_16, gpio_16);
+DECLARE_RTD1619B_PIN(RTD1619B_ISO_GPIO_17, gpio_17);
+DECLARE_RTD1619B_PIN(RTD1619B_ISO_GPIO_18, gpio_18);
+DECLARE_RTD1619B_PIN(RTD1619B_ISO_GPIO_19, gpio_19);
+DECLARE_RTD1619B_PIN(RTD1619B_ISO_GPIO_20, gpio_20);
+DECLARE_RTD1619B_PIN(RTD1619B_ISO_GPIO_21, gpio_21);
+DECLARE_RTD1619B_PIN(RTD1619B_ISO_GPIO_22, gpio_22);
+DECLARE_RTD1619B_PIN(RTD1619B_ISO_GPIO_23, gpio_23);
+DECLARE_RTD1619B_PIN(RTD1619B_ISO_USB_CC2, usb_cc2);
+DECLARE_RTD1619B_PIN(RTD1619B_ISO_GPIO_25, gpio_25);
+DECLARE_RTD1619B_PIN(RTD1619B_ISO_GPIO_26, gpio_26);
+DECLARE_RTD1619B_PIN(RTD1619B_ISO_GPIO_27, gpio_27);
+DECLARE_RTD1619B_PIN(RTD1619B_ISO_GPIO_28, gpio_28);
+DECLARE_RTD1619B_PIN(RTD1619B_ISO_GPIO_29, gpio_29);
+DECLARE_RTD1619B_PIN(RTD1619B_ISO_GPIO_30, gpio_30);
+DECLARE_RTD1619B_PIN(RTD1619B_ISO_GPIO_31, gpio_31);
+DECLARE_RTD1619B_PIN(RTD1619B_ISO_GPIO_32, gpio_32);
+DECLARE_RTD1619B_PIN(RTD1619B_ISO_GPIO_33, gpio_33);
+DECLARE_RTD1619B_PIN(RTD1619B_ISO_GPIO_34, gpio_34);
+DECLARE_RTD1619B_PIN(RTD1619B_ISO_GPIO_35, gpio_35);
+DECLARE_RTD1619B_PIN(RTD1619B_ISO_HIF_DATA, hif_data);
+DECLARE_RTD1619B_PIN(RTD1619B_ISO_HIF_EN, hif_en);
+DECLARE_RTD1619B_PIN(RTD1619B_ISO_HIF_RDY, hif_rdy);
+DECLARE_RTD1619B_PIN(RTD1619B_ISO_HIF_CLK, hif_clk);
+DECLARE_RTD1619B_PIN(RTD1619B_ISO_GPIO_40, gpio_40);
+DECLARE_RTD1619B_PIN(RTD1619B_ISO_GPIO_41, gpio_41);
+DECLARE_RTD1619B_PIN(RTD1619B_ISO_GPIO_42, gpio_42);
+DECLARE_RTD1619B_PIN(RTD1619B_ISO_GPIO_43, gpio_43);
+DECLARE_RTD1619B_PIN(RTD1619B_ISO_GPIO_44, gpio_44);
+DECLARE_RTD1619B_PIN(RTD1619B_ISO_GPIO_45, gpio_45);
+DECLARE_RTD1619B_PIN(RTD1619B_ISO_GPIO_46, gpio_46);
+DECLARE_RTD1619B_PIN(RTD1619B_ISO_GPIO_47, gpio_47);
+DECLARE_RTD1619B_PIN(RTD1619B_ISO_GPIO_48, gpio_48);
+DECLARE_RTD1619B_PIN(RTD1619B_ISO_GPIO_49, gpio_49);
+DECLARE_RTD1619B_PIN(RTD1619B_ISO_GPIO_50, gpio_50);
+DECLARE_RTD1619B_PIN(RTD1619B_ISO_USB_CC1, usb_cc1);
+DECLARE_RTD1619B_PIN(RTD1619B_ISO_GPIO_52, gpio_52);
+DECLARE_RTD1619B_PIN(RTD1619B_ISO_GPIO_53, gpio_53);
+DECLARE_RTD1619B_PIN(RTD1619B_ISO_IR_RX, ir_rx);
+DECLARE_RTD1619B_PIN(RTD1619B_ISO_UR0_RX, ur0_rx);
+DECLARE_RTD1619B_PIN(RTD1619B_ISO_UR0_TX, ur0_tx);
+DECLARE_RTD1619B_PIN(RTD1619B_ISO_GPIO_57, gpio_57);
+DECLARE_RTD1619B_PIN(RTD1619B_ISO_GPIO_58, gpio_58);
+DECLARE_RTD1619B_PIN(RTD1619B_ISO_GPIO_59, gpio_59);
+DECLARE_RTD1619B_PIN(RTD1619B_ISO_GPIO_60, gpio_60);
+DECLARE_RTD1619B_PIN(RTD1619B_ISO_GPIO_61, gpio_61);
+DECLARE_RTD1619B_PIN(RTD1619B_ISO_GPIO_62, gpio_62);
+DECLARE_RTD1619B_PIN(RTD1619B_ISO_GPIO_63, gpio_63);
+DECLARE_RTD1619B_PIN(RTD1619B_ISO_GPIO_64, gpio_64);
+DECLARE_RTD1619B_PIN(RTD1619B_ISO_GPIO_65, gpio_65);
+DECLARE_RTD1619B_PIN(RTD1619B_ISO_GPIO_66, gpio_66);
+DECLARE_RTD1619B_PIN(RTD1619B_ISO_GPIO_67, gpio_67);
+DECLARE_RTD1619B_PIN(RTD1619B_ISO_GPIO_68, gpio_68);
+DECLARE_RTD1619B_PIN(RTD1619B_ISO_GPIO_69, gpio_69);
+DECLARE_RTD1619B_PIN(RTD1619B_ISO_GPIO_70, gpio_70);
+DECLARE_RTD1619B_PIN(RTD1619B_ISO_GPIO_71, gpio_71);
+DECLARE_RTD1619B_PIN(RTD1619B_ISO_GPIO_72, gpio_72);
+DECLARE_RTD1619B_PIN(RTD1619B_ISO_GPIO_73, gpio_73);
+DECLARE_RTD1619B_PIN(RTD1619B_ISO_GPIO_74, gpio_74);
+DECLARE_RTD1619B_PIN(RTD1619B_ISO_GPIO_75, gpio_75);
+DECLARE_RTD1619B_PIN(RTD1619B_ISO_GPIO_76, gpio_76);
+DECLARE_RTD1619B_PIN(RTD1619B_ISO_EMMC_CMD, emmc_cmd);
+DECLARE_RTD1619B_PIN(RTD1619B_ISO_SPI_CE_N, spi_ce_n);
+DECLARE_RTD1619B_PIN(RTD1619B_ISO_SPI_SCK, spi_sck);
+DECLARE_RTD1619B_PIN(RTD1619B_ISO_SPI_SO, spi_so);
+DECLARE_RTD1619B_PIN(RTD1619B_ISO_SPI_SI, spi_si);
+DECLARE_RTD1619B_PIN(RTD1619B_ISO_EMMC_RST_N, emmc_rst_n);
+DECLARE_RTD1619B_PIN(RTD1619B_ISO_EMMC_DD_SB, emmc_dd_sb);
+DECLARE_RTD1619B_PIN(RTD1619B_ISO_EMMC_CLK, emmc_clk);
+DECLARE_RTD1619B_PIN(RTD1619B_ISO_EMMC_DATA_0, emmc_data_0);
+DECLARE_RTD1619B_PIN(RTD1619B_ISO_EMMC_DATA_1, emmc_data_1);
+DECLARE_RTD1619B_PIN(RTD1619B_ISO_EMMC_DATA_2, emmc_data_2);
+DECLARE_RTD1619B_PIN(RTD1619B_ISO_EMMC_DATA_3, emmc_data_3);
+DECLARE_RTD1619B_PIN(RTD1619B_ISO_EMMC_DATA_4, emmc_data_4);
+DECLARE_RTD1619B_PIN(RTD1619B_ISO_EMMC_DATA_5, emmc_data_5);
+DECLARE_RTD1619B_PIN(RTD1619B_ISO_EMMC_DATA_6, emmc_data_6);
+DECLARE_RTD1619B_PIN(RTD1619B_ISO_EMMC_DATA_7, emmc_data_7);
+DECLARE_RTD1619B_PIN(RTD1619B_ISO_UR2_LOC, ur2_loc);
+DECLARE_RTD1619B_PIN(RTD1619B_ISO_GSPI_LOC, gspi_loc);
+DECLARE_RTD1619B_PIN(RTD1619B_ISO_SDIO_LOC, sdio_loc);
+DECLARE_RTD1619B_PIN(RTD1619B_ISO_HI_LOC, hi_loc);
+DECLARE_RTD1619B_PIN(RTD1619B_ISO_HI_WIDTH, hi_width);
+DECLARE_RTD1619B_PIN(RTD1619B_ISO_SF_EN, sf_en);
+DECLARE_RTD1619B_PIN(RTD1619B_ISO_ARM_TRACE_DBG_EN, arm_trace_dbg_en);
+DECLARE_RTD1619B_PIN(RTD1619B_ISO_PWM_01_OPEN_DRAIN_EN_LOC0, pwm_01_open_drain_en_loc0);
+DECLARE_RTD1619B_PIN(RTD1619B_ISO_PWM_23_OPEN_DRAIN_EN_LOC0, pwm_23_open_drain_en_loc0);
+DECLARE_RTD1619B_PIN(RTD1619B_ISO_PWM_01_OPEN_DRAIN_EN_LOC1, pwm_01_open_drain_en_loc1);
+DECLARE_RTD1619B_PIN(RTD1619B_ISO_PWM_23_OPEN_DRAIN_EN_LOC1, pwm_23_open_drain_en_loc1);
+DECLARE_RTD1619B_PIN(RTD1619B_ISO_EJTAG_ACPU_LOC, ejtag_acpu_loc);
+DECLARE_RTD1619B_PIN(RTD1619B_ISO_EJTAG_VCPU_LOC, ejtag_vcpu_loc);
+DECLARE_RTD1619B_PIN(RTD1619B_ISO_EJTAG_SCPU_LOC, ejtag_scpu_loc);
+DECLARE_RTD1619B_PIN(RTD1619B_ISO_DMIC_LOC, dmic_loc);
+DECLARE_RTD1619B_PIN(RTD1619B_ISO_ISO_GSPI_LOC, iso_gspi_loc);
+DECLARE_RTD1619B_PIN(RTD1619B_ISO_EJTAG_VE3_LOC, ejtag_ve3_loc);
+DECLARE_RTD1619B_PIN(RTD1619B_ISO_EJTAG_AUCPU0_LOC, ejtag_aucpu0_loc);
+DECLARE_RTD1619B_PIN(RTD1619B_ISO_EJTAG_AUCPU1_LOC, ejtag_aucpu1_loc);
+
+#define RTD1619B_GROUP(_name) \
+ { \
+ .name = # _name, \
+ .pins = rtd1619b_ ## _name ## _pins, \
+ .num_pins = ARRAY_SIZE(rtd1619b_ ## _name ## _pins), \
+ }
+
+static const struct rtd_pin_group_desc rtd1619b_pin_groups[] = {
+ RTD1619B_GROUP(gpio_0),
+ RTD1619B_GROUP(gpio_1),
+ RTD1619B_GROUP(gpio_2),
+ RTD1619B_GROUP(gpio_3),
+ RTD1619B_GROUP(gpio_4),
+ RTD1619B_GROUP(gpio_5),
+ RTD1619B_GROUP(gpio_6),
+ RTD1619B_GROUP(gpio_7),
+ RTD1619B_GROUP(gpio_8),
+ RTD1619B_GROUP(gpio_9),
+ RTD1619B_GROUP(gpio_10),
+ RTD1619B_GROUP(gpio_11),
+ RTD1619B_GROUP(gpio_12),
+ RTD1619B_GROUP(gpio_13),
+ RTD1619B_GROUP(gpio_14),
+ RTD1619B_GROUP(gpio_15),
+ RTD1619B_GROUP(gpio_16),
+ RTD1619B_GROUP(gpio_17),
+ RTD1619B_GROUP(gpio_18),
+ RTD1619B_GROUP(gpio_19),
+ RTD1619B_GROUP(gpio_20),
+ RTD1619B_GROUP(gpio_21),
+ RTD1619B_GROUP(gpio_22),
+ RTD1619B_GROUP(gpio_23),
+ RTD1619B_GROUP(usb_cc2),
+ RTD1619B_GROUP(gpio_25),
+ RTD1619B_GROUP(gpio_26),
+ RTD1619B_GROUP(gpio_27),
+ RTD1619B_GROUP(gpio_28),
+ RTD1619B_GROUP(gpio_29),
+ RTD1619B_GROUP(gpio_30),
+ RTD1619B_GROUP(gpio_31),
+ RTD1619B_GROUP(gpio_32),
+ RTD1619B_GROUP(gpio_33),
+ RTD1619B_GROUP(gpio_34),
+ RTD1619B_GROUP(gpio_35),
+ RTD1619B_GROUP(hif_data),
+ RTD1619B_GROUP(hif_en),
+ RTD1619B_GROUP(hif_rdy),
+ RTD1619B_GROUP(hif_clk),
+ RTD1619B_GROUP(gpio_40),
+ RTD1619B_GROUP(gpio_41),
+ RTD1619B_GROUP(gpio_42),
+ RTD1619B_GROUP(gpio_43),
+ RTD1619B_GROUP(gpio_44),
+ RTD1619B_GROUP(gpio_45),
+ RTD1619B_GROUP(gpio_46),
+ RTD1619B_GROUP(gpio_47),
+ RTD1619B_GROUP(gpio_48),
+ RTD1619B_GROUP(gpio_49),
+ RTD1619B_GROUP(gpio_50),
+ RTD1619B_GROUP(usb_cc1),
+ RTD1619B_GROUP(gpio_52),
+ RTD1619B_GROUP(gpio_53),
+ RTD1619B_GROUP(ir_rx),
+ RTD1619B_GROUP(ur0_rx),
+ RTD1619B_GROUP(ur0_tx),
+ RTD1619B_GROUP(gpio_57),
+ RTD1619B_GROUP(gpio_58),
+ RTD1619B_GROUP(gpio_59),
+ RTD1619B_GROUP(gpio_60),
+ RTD1619B_GROUP(gpio_61),
+ RTD1619B_GROUP(gpio_62),
+ RTD1619B_GROUP(gpio_63),
+ RTD1619B_GROUP(gpio_64),
+ RTD1619B_GROUP(gpio_65),
+ RTD1619B_GROUP(gpio_66),
+ RTD1619B_GROUP(gpio_67),
+ RTD1619B_GROUP(gpio_68),
+ RTD1619B_GROUP(gpio_69),
+ RTD1619B_GROUP(gpio_70),
+ RTD1619B_GROUP(gpio_71),
+ RTD1619B_GROUP(gpio_72),
+ RTD1619B_GROUP(gpio_73),
+ RTD1619B_GROUP(gpio_74),
+ RTD1619B_GROUP(gpio_75),
+ RTD1619B_GROUP(gpio_76),
+ RTD1619B_GROUP(emmc_cmd),
+ RTD1619B_GROUP(spi_ce_n),
+ RTD1619B_GROUP(spi_sck),
+ RTD1619B_GROUP(spi_so),
+ RTD1619B_GROUP(spi_si),
+ RTD1619B_GROUP(emmc_rst_n),
+ RTD1619B_GROUP(emmc_dd_sb),
+ RTD1619B_GROUP(emmc_clk),
+ RTD1619B_GROUP(emmc_data_0),
+ RTD1619B_GROUP(emmc_data_1),
+ RTD1619B_GROUP(emmc_data_2),
+ RTD1619B_GROUP(emmc_data_3),
+ RTD1619B_GROUP(emmc_data_4),
+ RTD1619B_GROUP(emmc_data_5),
+ RTD1619B_GROUP(emmc_data_6),
+ RTD1619B_GROUP(emmc_data_7),
+ RTD1619B_GROUP(ur2_loc),
+ RTD1619B_GROUP(gspi_loc),
+ RTD1619B_GROUP(sdio_loc),
+ RTD1619B_GROUP(hi_loc),
+ RTD1619B_GROUP(hi_width),
+ RTD1619B_GROUP(sf_en),
+ RTD1619B_GROUP(arm_trace_dbg_en),
+ RTD1619B_GROUP(pwm_01_open_drain_en_loc0),
+ RTD1619B_GROUP(pwm_23_open_drain_en_loc0),
+ RTD1619B_GROUP(pwm_01_open_drain_en_loc1),
+ RTD1619B_GROUP(pwm_23_open_drain_en_loc1),
+ RTD1619B_GROUP(ejtag_acpu_loc),
+ RTD1619B_GROUP(ejtag_vcpu_loc),
+ RTD1619B_GROUP(ejtag_scpu_loc),
+ RTD1619B_GROUP(dmic_loc),
+ RTD1619B_GROUP(iso_gspi_loc),
+ RTD1619B_GROUP(ejtag_ve3_loc),
+ RTD1619B_GROUP(ejtag_aucpu0_loc),
+ RTD1619B_GROUP(ejtag_aucpu1_loc),
+};
+
+static const char * const rtd1619b_gpio_groups[] = {
+ "gpio_0", "gpio_1", "gpio_2", "gpio_3", "gpio_4",
+ "gpio_5", "gpio_6", "gpio_7", "gpio_8", "gpio_9",
+ "gpio_10", "gpio_11", "gpio_12", "gpio_13", "gpio_14",
+ "gpio_15", "gpio_16", "gpio_17", "gpio_18", "gpio_19",
+ "gpio_20", "gpio_21", "gpio_22", "gpio_23", "usb_cc2",
+ "gpio_25", "gpio_26", "gpio_27", "gpio_28", "gpio_29",
+ "gpio_30", "gpio_31", "gpio_32", "gpio_33", "gpio_34",
+ "gpio_35", "hif_data", "hif_en", "hif_rdy", "hif_clk",
+ "gpio_40", "gpio_41", "gpio_42", "gpio_43", "gpio_44",
+ "gpio_45", "gpio_46", "gpio_47", "gpio_48", "gpio_49",
+ "gpio_50", "usb_cc1", "gpio_52", "gpio_53", "ir_rx",
+ "ur0_rx", "ur0_tx", "gpio_57", "gpio_58", "gpio_59",
+ "gpio_60", "gpio_61", "gpio_62", "gpio_63", "gpio_64",
+ "gpio_65", "gpio_66", "gpio_67", "gpio_68", "gpio_69",
+ "gpio_70", "gpio_71", "gpio_72", "gpio_73", "gpio_74",
+ "gpio_75", "gpio_76", "emmc_cmd", "spi_ce_n", "spi_sck",
+ "spi_so", "spi_si"};
+static const char * const rtd1619b_nf_groups[] = {
+ "emmc_rst_n", "emmc_clk", "emmc_cmd", "emmc_data_0", "emmc_data_1",
+ "emmc_data_2", "emmc_data_3", "emmc_data_4",
+ "emmc_data_5", "emmc_data_6", "emmc_data_7", "spi_ce_n",
+ "spi_sck", "spi_so", "spi_si" };
+static const char * const rtd1619b_nf_spi_groups[] = {
+ "emmc_data_0", "emmc_data_1",
+ "emmc_data_2", "emmc_data_3", "emmc_data_4",
+ "emmc_data_5" };
+static const char * const rtd1619b_spi_groups[] = {
+ "spi_ce_n", "spi_sck", "spi_so", "spi_si" };
+static const char * const rtd1619b_emmc_groups[] = {
+ "emmc_rst_n", "emmc_clk", "emmc_data_0", "emmc_data_1",
+ "emmc_data_2", "emmc_data_3", "emmc_data_4",
+ "emmc_data_5", "emmc_data_6", "emmc_data_7",
+ "emmc_dd_sb", "emmc_cmd"};
+
+static const char * const rtd1619b_pmic_groups[] = { "spi_ce_n" };
+static const char * const rtd1619b_spdif_groups[] = { "gpio_50" };
+static const char * const rtd1619b_spdif_coaxial_groups[] = { "gpio_1" };
+static const char * const rtd1619b_spdif_optical_loc0_groups[] = { "gpio_6" };
+static const char * const rtd1619b_spdif_optical_loc1_groups[] = { "gpio_21" };
+
+static const char * const rtd1619b_emmc_spi_groups[] = {
+ "gpio_1", "gpio_2", "gpio_3", "gpio_4", "gpio_5", "gpio_6" };
+static const char * const rtd1619b_sc1_groups[] = {
+ "gpio_2", "gpio_3", "gpio_4", "gpio_5" };
+static const char * const rtd1619b_uart0_groups[] = { "ur0_rx", "ur0_tx" };
+static const char * const rtd1619b_uart1_groups[] = {
+ "gpio_8", "gpio_9", "gpio_10", "gpio_11" };
+static const char * const rtd1619b_uart2_loc0_groups[] = {
+ "gpio_18", "gpio_19", "gpio_20", "gpio_31", "ur2_loc" };
+static const char * const rtd1619b_uart2_loc1_groups[] = {
+ "gpio_25", "gpio_26", "gpio_27", "gpio_28", "ur2_loc" };
+static const char * const rtd1619b_gspi_loc1_groups[] = {
+ "gpio_8", "gpio_9", "gpio_10", "gpio_11", "gspi_loc" };
+static const char * const rtd1619b_iso_gspi_loc1_groups[] = {
+ "gpio_8", "gpio_9", "gpio_10", "gpio_11", "iso_gspi_loc" };
+static const char * const rtd1619b_i2c0_groups[] = { "gpio_12", "gpio_13" };
+static const char * const rtd1619b_i2c1_groups[] = { "gpio_16", "gpio_17" };
+static const char * const rtd1619b_i2c3_groups[] = { "gpio_63", "gpio_64" };
+static const char * const rtd1619b_i2c4_groups[] = { "gpio_34", "gpio_35" };
+static const char * const rtd1619b_i2c5_groups[] = { "gpio_29", "gpio_46" };
+static const char * const rtd1619b_pwm0_groups[] = { "gpio_20", "gpio_26" };
+static const char * const rtd1619b_pwm1_groups[] = { "gpio_21", "gpio_27" };
+static const char * const rtd1619b_pwm2_groups[] = { "gpio_22", "gpio_28" };
+static const char * const rtd1619b_pwm3_groups[] = { "gpio_23", "gpio_47" };
+static const char * const rtd1619b_etn_led_groups[] = { "gpio_14", "gpio_15", "gpio_23" };
+static const char * const rtd1619b_etn_phy_groups[] = { "gpio_14", "gpio_15" };
+static const char * const rtd1619b_etn_clk_groups[] = { "gpio_14" };
+static const char * const rtd1619b_sc0_groups[] = {
+ "gpio_18", "gpio_19", "gpio_20", "gpio_31" };
+static const char * const rtd1619b_vfd_groups[] = {
+ "gpio_26", "gpio_27", "gpio_28" };
+
+static const char * const rtd1619b_gspi_loc0_groups[] = {
+ "gpio_18", "gpio_19", "gpio_20", "gpio_31", "gspi_loc" };
+static const char * const rtd1619b_iso_gspi_loc0_groups[] = {
+ "gpio_18", "gpio_19", "gpio_20", "gpio_31", "iso_gspi_loc" };
+static const char * const rtd1619b_pcie1_groups[] = { "gpio_25" };
+static const char * const rtd1619b_pcie2_groups[] = { "gpio_52" };
+static const char * const rtd1619b_sd_groups[] = {
+ "gpio_32", "gpio_33", "gpio_34", "gpio_35", "hif_data",
+ "hif_en", "hif_rdy", "hif_clk" };
+static const char * const rtd1619b_sdio_loc0_groups[] = {
+ "gpio_32", "gpio_33", "hif_data", "hif_en",
+ "hif_rdy", "hif_clk", "sdio_loc" };
+static const char * const rtd1619b_sdio_loc1_groups[] = {
+ "gpio_40", "gpio_41", "gpio_42", "gpio_43", "gpio_44",
+ "gpio_45", "sdio_loc" };
+static const char * const rtd1619b_hi_groups[] = {
+ "hif_data", "hif_en", "hif_rdy", "hif_clk" };
+static const char * const rtd1619b_hi_m_groups[] = {
+ "hif_data", "hif_en", "hif_rdy", "hif_clk" };
+static const char * const rtd1619b_dc_fan_groups[] = { "gpio_47" };
+static const char * const rtd1619b_pll_test_loc0_groups[] = { "gpio_52", "gpio_53" };
+static const char * const rtd1619b_pll_test_loc1_groups[] = { "gpio_48", "gpio_49" };
+static const char * const rtd1619b_tdm_ai_loc0_groups[] = {
+ "gpio_57", "gpio_58", "gpio_59", "gpio_60" };
+static const char * const rtd1619b_tdm_ai_loc1_groups[] = {
+ "hif_data", "hif_en", "hif_rdy", "hif_clk" };
+static const char * const rtd1619b_dmic_loc0_groups[] = {
+ "gpio_57", "gpio_58", "gpio_59", "gpio_60", "gpio_61",
+ "gpio_62", "gpio_63", "gpio_64", "dmic_loc"};
+static const char * const rtd1619b_dmic_loc1_groups[] = {
+ "gpio_32", "gpio_33", "gpio_34", "gpio_35", "hif_data",
+ "hif_en", "hif_rdy", "hif_clk", "dmic_loc" };
+static const char * const rtd1619b_ai_loc0_groups[] = {
+ "gpio_57", "gpio_58", "gpio_59", "gpio_60", "gpio_61",
+ "gpio_62", "gpio_63" };
+static const char * const rtd1619b_ai_loc1_groups[] = {
+ "gpio_32", "gpio_33", "gpio_34", "hif_data",
+ "hif_en", "hif_rdy", "hif_clk"};
+static const char * const rtd1619b_tp0_groups[] = {
+ "gpio_66", "gpio_67", "gpio_68", "gpio_69",
+ "gpio_70", "gpio_71", "gpio_72", "gpio_73", "gpio_74",
+ "gpio_75", "gpio_76" };
+static const char * const rtd1619b_tp1_groups[] = {
+ "gpio_69", "gpio_70", "gpio_71", "gpio_72" };
+static const char * const rtd1619b_ao_groups[] = {
+ "gpio_66", "gpio_67", "gpio_68", "gpio_69",
+ "gpio_70", "gpio_71", "gpio_72" };
+static const char * const rtd1619b_uart2_disable_groups[] = { "ur2_loc" };
+static const char * const rtd1619b_gspi_disable_groups[] = { "gspi_loc" };
+static const char * const rtd1619b_sdio_disable_groups[] = { "sdio_loc" };
+static const char * const rtd1619b_hi_loc_disable_groups[] = { "hi_loc" };
+static const char * const rtd1619b_hi_loc0_groups[] = { "hi_loc" };
+static const char * const rtd1619b_hi_width_disable_groups[] = { "hi_width" };
+static const char * const rtd1619b_hi_width_1bit_groups[] = { "hi_width" };
+
+static const char * const rtd1619b_vtc_i2si_loc0_groups[] = {
+ "gpio_32", "hif_data", "hif_en", "hif_rdy", "hif_clk" };
+static const char * const rtd1619b_vtc_tdm_loc0_groups[] = {
+ "hif_data", "hif_en", "hif_rdy", "hif_clk" };
+static const char * const rtd1619b_vtc_dmic_loc0_groups[] = {
+ "hif_data", "hif_en", "hif_rdy", "hif_clk" };
+static const char * const rtd1619b_vtc_i2si_loc1_groups[] = {
+ "gpio_57", "gpio_58", "gpio_59", "gpio_60", "gpio_61" };
+static const char * const rtd1619b_vtc_tdm_loc1_groups[] = {
+ "gpio_57", "gpio_58", "gpio_59", "gpio_60" };
+static const char * const rtd1619b_vtc_dmic_loc1_groups[] = {
+ "gpio_57", "gpio_58", "gpio_59", "gpio_60" };
+static const char * const rtd1619b_vtc_i2so_groups[] = {
+ "gpio_66", "gpio_67", "gpio_68", "gpio_69" };
+static const char * const rtd1619b_ve3_ejtag_loc0_groups[] = {
+ "gpio_2", "gpio_3", "gpio_4",
+ "gpio_5", "gpio_6", "ejtag_ve3_loc" };
+static const char * const rtd1619b_aucpu0_ejtag_loc0_groups[] = {
+ "gpio_2", "gpio_3", "gpio_4",
+ "gpio_5", "gpio_6", "ejtag_aucpu0_loc" };
+static const char * const rtd1619b_aucpu1_ejtag_loc0_groups[] = {
+ "gpio_2", "gpio_3", "gpio_4",
+ "gpio_5", "gpio_6", "ejtag_aucpu1_loc" };
+static const char * const rtd1619b_ve3_ejtag_loc1_groups[] = {
+ "gpio_32", "gpio_33", "hif_data", "hif_en",
+ "hif_clk", "ejtag_ve3_loc" };
+static const char * const rtd1619b_aucpu0_ejtag_loc1_groups[] = {
+ "gpio_32", "gpio_33", "hif_data", "hif_en",
+ "hif_clk", "ejtag_aucpu0_loc" };
+static const char * const rtd1619b_aucpu1_ejtag_loc1_groups[] = {
+ "gpio_32", "gpio_33", "hif_data", "hif_en",
+ "hif_clk", "ejtag_aucpu1_loc" };
+
+static const char * const rtd1619b_ve3_ejtag_loc2_groups[] = {
+ "gpio_71", "gpio_72", "gpio_73", "gpio_74",
+ "gpio_75", "gpio_76", "ejtag_ve3_loc" };
+static const char * const rtd1619b_aucpu0_ejtag_loc2_groups[] = {
+ "gpio_71", "gpio_72", "gpio_73", "gpio_74",
+ "gpio_75", "gpio_76", "ejtag_aucpu0_loc" };
+static const char * const rtd1619b_aucpu1_ejtag_loc2_groups[] = {
+ "gpio_71", "gpio_72", "gpio_73", "gpio_74",
+ "gpio_75", "gpio_76", "ejtag_aucpu1_loc" };
+
+static const char * const rtd1619b_scpu_ejtag_loc0_groups[] = {
+ "gpio_2", "gpio_3", "gpio_4",
+ "gpio_5", "gpio_6", "ejtag_scpu_loc" };
+static const char * const rtd1619b_acpu_ejtag_loc0_groups[] = {
+ "gpio_2", "gpio_3", "gpio_4",
+ "gpio_5", "gpio_6", "ejtag_acpu_loc" };
+static const char * const rtd1619b_vcpu_ejtag_loc0_groups[] = {
+ "gpio_2", "gpio_3", "gpio_4",
+ "gpio_5", "gpio_6", "ejtag_vcpu_loc" };
+static const char * const rtd1619b_scpu_ejtag_loc1_groups[] = {
+ "gpio_32", "gpio_33", "hif_data", "hif_en",
+ "hif_clk", "ejtag_scpu_loc" };
+static const char * const rtd1619b_acpu_ejtag_loc1_groups[] = {
+ "gpio_32", "gpio_33", "hif_data", "hif_en",
+ "hif_clk", "ejtag_acpu_loc" };
+static const char * const rtd1619b_vcpu_ejtag_loc1_groups[] = {
+ "gpio_32", "gpio_33", "hif_data", "hif_en",
+ "hif_clk", "ejtag_vcpu_loc" };
+
+static const char * const rtd1619b_scpu_ejtag_loc2_groups[] = {
+ "gpio_71", "gpio_72", "gpio_73", "gpio_74",
+ "gpio_75", "gpio_76", "ejtag_scpu_loc" };
+static const char * const rtd1619b_acpu_ejtag_loc2_groups[] = {
+ "gpio_71", "gpio_72", "gpio_73", "gpio_74",
+ "gpio_75", "gpio_76", "ejtag_acpu_loc" };
+static const char * const rtd1619b_vcpu_ejtag_loc2_groups[] = {
+ "gpio_71", "gpio_72", "gpio_73", "gpio_74",
+ "gpio_75", "gpio_76", "ejtag_vcpu_loc"};
+static const char * const rtd1619b_ve3_ejtag_disable_groups[] = { "ejtag_ve3_loc" };
+static const char * const rtd1619b_aucpu0_ejtag_disable_groups[] = { "ejtag_aucpu0_loc" };
+static const char * const rtd1619b_aucpu1_ejtag_disable_groups[] = { "ejtag_aucpu1_loc" };
+
+static const char * const rtd1619b_acpu_ejtag_disable_groups[] = { "ejtag_acpu_loc" };
+static const char * const rtd1619b_vcpu_ejtag_disable_groups[] = { "ejtag_vcpu_loc" };
+static const char * const rtd1619b_scpu_ejtag_disable_groups[] = { "ejtag_scpu_loc" };
+static const char * const rtd1619b_sf_disable_groups[] = { "sf_en" };
+static const char * const rtd1619b_sf_enable_groups[] = { "sf_en" };
+static const char * const rtd1619b_iso_gspi_disable_groups[] = { "iso_gspi_loc" };
+static const char * const rtd1619b_arm_trace_debug_disable_groups[] = { "arm_trace_dbg_en" };
+static const char * const rtd1619b_arm_trace_debug_enable_groups[] = { "arm_trace_dbg_en" };
+static const char * const rtd1619b_pwm_normal_groups[] = {
+ "pwm_01_open_drain_en_loc0", "pwm_23_open_drain_en_loc0",
+ "pwm_01_open_drain_en_loc1", "pwm_23_open_drain_en_loc1" };
+static const char * const rtd1619b_pwm_open_drain_groups[] = {
+ "pwm_01_open_drain_en_loc0", "pwm_23_open_drain_en_loc0",
+ "pwm_01_open_drain_en_loc1", "pwm_23_open_drain_en_loc1" };
+static const char * const rtd1619b_standby_dbg_groups[] = {
+ "gpio_2", "gpio_3", "ir_rx" };
+
+static const char * const rtd1619b_usb_cc1_groups[] = { "usb_cc1" };
+static const char * const rtd1619b_usb_cc2_groups[] = { "usb_cc2" };
+static const char * const rtd1619b_ir_rx_groups[] = { "ir_rx" };
+static const char * const rtd1619b_test_loop_dis_groups[] = { "gpio_50" };
+
+#define RTD1619B_FUNC(_name) \
+ { \
+ .name = # _name, \
+ .groups = rtd1619b_ ## _name ## _groups, \
+ .num_groups = ARRAY_SIZE(rtd1619b_ ## _name ## _groups), \
+ }
+
+static const struct rtd_pin_func_desc rtd1619b_pin_functions[] = {
+ RTD1619B_FUNC(gpio),
+ RTD1619B_FUNC(nf),
+ RTD1619B_FUNC(nf_spi),
+ RTD1619B_FUNC(spi),
+ RTD1619B_FUNC(pmic),
+ RTD1619B_FUNC(spdif),
+ RTD1619B_FUNC(spdif_coaxial),
+ RTD1619B_FUNC(spdif_optical_loc0),
+ RTD1619B_FUNC(spdif_optical_loc1),
+ RTD1619B_FUNC(emmc_spi),
+ RTD1619B_FUNC(emmc),
+ RTD1619B_FUNC(sc1),
+ RTD1619B_FUNC(uart0),
+ RTD1619B_FUNC(uart1),
+ RTD1619B_FUNC(uart2_loc0),
+ RTD1619B_FUNC(uart2_loc1),
+ RTD1619B_FUNC(gspi_loc1),
+ RTD1619B_FUNC(iso_gspi_loc1),
+ RTD1619B_FUNC(i2c0),
+ RTD1619B_FUNC(i2c1),
+ RTD1619B_FUNC(i2c3),
+ RTD1619B_FUNC(i2c4),
+ RTD1619B_FUNC(i2c5),
+ RTD1619B_FUNC(pwm0),
+ RTD1619B_FUNC(pwm1),
+ RTD1619B_FUNC(pwm2),
+ RTD1619B_FUNC(pwm3),
+ RTD1619B_FUNC(etn_led),
+ RTD1619B_FUNC(etn_phy),
+ RTD1619B_FUNC(etn_clk),
+ RTD1619B_FUNC(sc0),
+ RTD1619B_FUNC(vfd),
+ RTD1619B_FUNC(gspi_loc0),
+ RTD1619B_FUNC(iso_gspi_loc0),
+ RTD1619B_FUNC(pcie1),
+ RTD1619B_FUNC(pcie2),
+ RTD1619B_FUNC(sd),
+ RTD1619B_FUNC(sdio_loc0),
+ RTD1619B_FUNC(sdio_loc1),
+ RTD1619B_FUNC(hi),
+ RTD1619B_FUNC(hi_m),
+ RTD1619B_FUNC(dc_fan),
+ RTD1619B_FUNC(pll_test_loc0),
+ RTD1619B_FUNC(pll_test_loc1),
+ RTD1619B_FUNC(usb_cc1),
+ RTD1619B_FUNC(usb_cc2),
+ RTD1619B_FUNC(ir_rx),
+ RTD1619B_FUNC(tdm_ai_loc0),
+ RTD1619B_FUNC(tdm_ai_loc1),
+ RTD1619B_FUNC(dmic_loc0),
+ RTD1619B_FUNC(dmic_loc1),
+ RTD1619B_FUNC(ai_loc0),
+ RTD1619B_FUNC(ai_loc1),
+ RTD1619B_FUNC(tp0),
+ RTD1619B_FUNC(tp1),
+ RTD1619B_FUNC(ao),
+ RTD1619B_FUNC(uart2_disable),
+ RTD1619B_FUNC(gspi_disable),
+ RTD1619B_FUNC(sdio_disable),
+ RTD1619B_FUNC(hi_loc_disable),
+ RTD1619B_FUNC(hi_loc0),
+ RTD1619B_FUNC(hi_width_disable),
+ RTD1619B_FUNC(hi_width_1bit),
+ RTD1619B_FUNC(vtc_i2si_loc0),
+ RTD1619B_FUNC(vtc_tdm_loc0),
+ RTD1619B_FUNC(vtc_dmic_loc0),
+ RTD1619B_FUNC(vtc_i2si_loc1),
+ RTD1619B_FUNC(vtc_tdm_loc1),
+ RTD1619B_FUNC(vtc_dmic_loc1),
+ RTD1619B_FUNC(vtc_i2so),
+ RTD1619B_FUNC(ve3_ejtag_loc0),
+ RTD1619B_FUNC(aucpu0_ejtag_loc0),
+ RTD1619B_FUNC(aucpu1_ejtag_loc0),
+ RTD1619B_FUNC(ve3_ejtag_loc1),
+ RTD1619B_FUNC(aucpu0_ejtag_loc1),
+ RTD1619B_FUNC(aucpu1_ejtag_loc1),
+ RTD1619B_FUNC(ve3_ejtag_loc2),
+ RTD1619B_FUNC(aucpu0_ejtag_loc2),
+ RTD1619B_FUNC(aucpu1_ejtag_loc2),
+ RTD1619B_FUNC(scpu_ejtag_loc0),
+ RTD1619B_FUNC(acpu_ejtag_loc0),
+ RTD1619B_FUNC(vcpu_ejtag_loc0),
+ RTD1619B_FUNC(scpu_ejtag_loc1),
+ RTD1619B_FUNC(acpu_ejtag_loc1),
+ RTD1619B_FUNC(vcpu_ejtag_loc1),
+ RTD1619B_FUNC(scpu_ejtag_loc2),
+ RTD1619B_FUNC(acpu_ejtag_loc2),
+ RTD1619B_FUNC(vcpu_ejtag_loc2),
+ RTD1619B_FUNC(ve3_ejtag_disable),
+ RTD1619B_FUNC(aucpu0_ejtag_disable),
+ RTD1619B_FUNC(aucpu1_ejtag_disable),
+ RTD1619B_FUNC(acpu_ejtag_disable),
+ RTD1619B_FUNC(vcpu_ejtag_disable),
+ RTD1619B_FUNC(scpu_ejtag_disable),
+ RTD1619B_FUNC(iso_gspi_disable),
+ RTD1619B_FUNC(sf_disable),
+ RTD1619B_FUNC(sf_enable),
+ RTD1619B_FUNC(arm_trace_debug_disable),
+ RTD1619B_FUNC(arm_trace_debug_enable),
+ RTD1619B_FUNC(pwm_normal),
+ RTD1619B_FUNC(pwm_open_drain),
+ RTD1619B_FUNC(standby_dbg),
+ RTD1619B_FUNC(test_loop_dis),
+};
+
+#undef RTD1619B_FUNC
+
+static const struct rtd_pin_desc rtd1619b_iso_muxes[] = {
+ [RTD1619B_ISO_EMMC_RST_N] = RTK_PIN_MUX(emmc_rst_n, 0x0, GENMASK(1, 0),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x1, 0), "nf"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x2, 0), "emmc")),
+ [RTD1619B_ISO_EMMC_DD_SB] = RTK_PIN_MUX(emmc_dd_sb, 0x0, GENMASK(3, 2),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x2, 2), "emmc")),
+ [RTD1619B_ISO_EMMC_CLK] = RTK_PIN_MUX(emmc_clk, 0x0, GENMASK(5, 4),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x1, 4), "nf"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x2, 4), "emmc")),
+ [RTD1619B_ISO_EMMC_CMD] = RTK_PIN_MUX(emmc_cmd, 0x0, GENMASK(7, 6),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x0, 6), "gpio"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x1, 6), "nf"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x2, 6), "emmc")),
+ [RTD1619B_ISO_EMMC_DATA_0] = RTK_PIN_MUX(emmc_data_0, 0x0, GENMASK(9, 8),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x1, 8), "nf"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x2, 8), "emmc"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x3, 8), "nf_spi")),
+ [RTD1619B_ISO_EMMC_DATA_1] = RTK_PIN_MUX(emmc_data_1, 0x0, GENMASK(11, 10),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x1, 10), "nf"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x2, 10), "emmc"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x3, 10), "nf_spi")),
+ [RTD1619B_ISO_EMMC_DATA_2] = RTK_PIN_MUX(emmc_data_2, 0x0, GENMASK(13, 12),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x1, 12), "nf"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x2, 12), "emmc"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x3, 12), "nf_spi")),
+ [RTD1619B_ISO_EMMC_DATA_3] = RTK_PIN_MUX(emmc_data_3, 0x0, GENMASK(15, 14),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x1, 14), "nf"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x2, 14), "emmc"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x3, 14), "nf_spi")),
+ [RTD1619B_ISO_EMMC_DATA_4] = RTK_PIN_MUX(emmc_data_4, 0x0, GENMASK(17, 16),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x1, 16), "nf"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x2, 16), "emmc"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x3, 16), "nf_spi")),
+ [RTD1619B_ISO_EMMC_DATA_5] = RTK_PIN_MUX(emmc_data_5, 0x0, GENMASK(19, 18),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x1, 18), "nf"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x2, 18), "emmc"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x3, 18), "nf_spi")),
+ [RTD1619B_ISO_EMMC_DATA_6] = RTK_PIN_MUX(emmc_data_6, 0x0, GENMASK(21, 20),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x1, 20), "nf"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x2, 20), "emmc")),
+ [RTD1619B_ISO_EMMC_DATA_7] = RTK_PIN_MUX(emmc_data_7, 0x0, GENMASK(23, 22),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x1, 22), "nf"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x2, 22), "emmc")),
+ [RTD1619B_ISO_SPI_CE_N] = RTK_PIN_MUX(spi_ce_n, 0x0, GENMASK(25, 24),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x0, 24), "gpio"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x1, 24), "nf"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x2, 24), "spi"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x3, 24), "pmic")),
+ [RTD1619B_ISO_SPI_SCK] = RTK_PIN_MUX(spi_sck, 0x0, GENMASK(27, 26),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x0, 26), "gpio"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x1, 26), "nf"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x2, 26), "spi")),
+ [RTD1619B_ISO_SPI_SO] = RTK_PIN_MUX(spi_so, 0x0, GENMASK(29, 28),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x0, 28), "gpio"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x1, 28), "nf"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x2, 28), "spi")),
+ [RTD1619B_ISO_SPI_SI] = RTK_PIN_MUX(spi_si, 0x0, GENMASK(31, 30),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x0, 30), "gpio"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x1, 30), "nf"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x2, 30), "spi")),
+
+ [RTD1619B_ISO_GPIO_0] = RTK_PIN_MUX(gpio_0, 0x4, GENMASK(0, 0),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x0, 0), "gpio")),
+ [RTD1619B_ISO_GPIO_1] = RTK_PIN_MUX(gpio_1, 0x4, GENMASK(3, 1),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x0, 1), "gpio"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x3, 1), "emmc_spi"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x5, 1), "spdif_coaxial")),
+ [RTD1619B_ISO_GPIO_2] = RTK_PIN_MUX(gpio_2, 0x4, GENMASK(7, 4),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x0, 4), "gpio"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x1, 4), "standby_dbg"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x3, 4), "emmc_spi"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x4, 4), "sc1"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x5, 4), "scpu_ejtag_loc0"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x6, 4), "acpu_ejtag_loc0"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x7, 4), "vcpu_ejtag_loc0"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x8, 4), "ve3_ejtag_loc0"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x9, 4), "aucpu0_ejtag_loc0"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x10, 4), "aucpu1_ejtag_loc0")),
+ [RTD1619B_ISO_GPIO_3] = RTK_PIN_MUX(gpio_3, 0x4, GENMASK(11, 8),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x0, 8), "gpio"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x1, 8), "standby_dbg"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x3, 8), "emmc_spi"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x4, 8), "sc1"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x5, 8), "scpu_ejtag_loc0"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x6, 8), "acpu_ejtag_loc0"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x7, 8), "vcpu_ejtag_loc0"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x8, 8), "ve3_ejtag_loc0"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x9, 8), "aucpu0_ejtag_loc0"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x10, 8), "aucpu1_ejtag_loc0")),
+ [RTD1619B_ISO_GPIO_4] = RTK_PIN_MUX(gpio_4, 0x4, GENMASK(15, 12),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x0, 12), "gpio"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x3, 12), "emmc_spi"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x4, 12), "sc1"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x5, 12), "scpu_ejtag_loc0"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x6, 12), "acpu_ejtag_loc0"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x7, 12), "vcpu_ejtag_loc0"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x8, 12), "ve3_ejtag_loc0"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x9, 12), "aucpu0_ejtag_loc0"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x10, 12), "aucpu1_ejtag_loc0")),
+ [RTD1619B_ISO_GPIO_5] = RTK_PIN_MUX(gpio_5, 0x4, GENMASK(19, 16),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x0, 16), "gpio"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x3, 16), "emmc_spi"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x4, 16), "sc1"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x5, 16), "scpu_ejtag_loc0"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x6, 16), "acpu_ejtag_loc0"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x7, 16), "vcpu_ejtag_loc0"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x8, 16), "ve3_ejtag_loc0"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x9, 16), "aucpu0_ejtag_loc0"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x10, 16), "aucpu1_ejtag_loc0")),
+ [RTD1619B_ISO_GPIO_6] = RTK_PIN_MUX(gpio_6, 0x4, GENMASK(23, 20),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x0, 20), "gpio"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x3, 20), "emmc_spi"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x4, 20), "spdif_optical_loc0"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x5, 20), "scpu_ejtag_loc0"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x6, 20), "acpu_ejtag_loc0"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x7, 20), "vcpu_ejtag_loc0"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x8, 20), "ve3_ejtag_loc0"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x9, 20), "aucpu0_ejtag_loc0"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x10, 20), "aucpu1_ejtag_loc0")),
+ [RTD1619B_ISO_GPIO_7] = RTK_PIN_MUX(gpio_7, 0x4, GENMASK(24, 24),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x0, 24), "gpio")),
+ [RTD1619B_ISO_GPIO_8] = RTK_PIN_MUX(gpio_8, 0x4, GENMASK(27, 25),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x0, 25), "gpio"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x1, 25), "uart1"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x3, 25), "gspi_loc1"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x5, 25), "iso_gspi_loc1")),
+ [RTD1619B_ISO_GPIO_9] = RTK_PIN_MUX(gpio_9, 0x4, GENMASK(30, 28),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x0, 28), "gpio"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x1, 28), "uart1"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x3, 28), "gspi_loc1"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x5, 28), "iso_gspi_loc1")),
+ [RTD1619B_ISO_GPIO_10] = RTK_PIN_MUX(gpio_10, 0x8, GENMASK(2, 0),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x0, 0), "gpio"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x1, 0), "uart1"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x3, 0), "gspi_loc1"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x5, 0), "iso_gspi_loc1")),
+ [RTD1619B_ISO_GPIO_11] = RTK_PIN_MUX(gpio_11, 0x8, GENMASK(5, 3),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x0, 3), "gpio"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x1, 3), "uart1"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x3, 3), "gspi_loc1"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x5, 3), "iso_gspi_loc1")),
+
+ [RTD1619B_ISO_GPIO_12] = RTK_PIN_MUX(gpio_12, 0x8, GENMASK(6, 6),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x0, 6), "gpio"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x1, 6), "i2c0")),
+ [RTD1619B_ISO_GPIO_13] = RTK_PIN_MUX(gpio_13, 0x8, GENMASK(7, 7),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x0, 7), "gpio"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x1, 7), "i2c0")),
+ [RTD1619B_ISO_GPIO_14] = RTK_PIN_MUX(gpio_14, 0x8, GENMASK(10, 8),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x0, 8), "gpio"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x1, 8), "etn_led"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x3, 8), "etn_phy"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x5, 8), "etn_clk")),
+ [RTD1619B_ISO_GPIO_15] = RTK_PIN_MUX(gpio_15, 0x8, GENMASK(12, 11),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x0, 11), "gpio"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x1, 11), "etn_led"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x3, 11), "etn_phy")),
+ [RTD1619B_ISO_GPIO_16] = RTK_PIN_MUX(gpio_16, 0x8, GENMASK(13, 13),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x0, 13), "gpio"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x1, 13), "i2c1")),
+ [RTD1619B_ISO_GPIO_17] = RTK_PIN_MUX(gpio_17, 0x8, GENMASK(14, 14),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x0, 14), "gpio"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x1, 14), "i2c1")),
+ [RTD1619B_ISO_GPIO_18] = RTK_PIN_MUX(gpio_18, 0x8, GENMASK(17, 15),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x0, 15), "gpio"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x1, 15), "uart2_loc0"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x2, 15), "sc0"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x3, 15), "gspi_loc0"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x5, 15), "iso_gspi_loc0")),
+ [RTD1619B_ISO_GPIO_19] = RTK_PIN_MUX(gpio_19, 0x8, GENMASK(20, 18),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x0, 18), "gpio"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x1, 18), "uart2_loc0"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x2, 18), "sc0"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x3, 18), "gspi_loc0"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x5, 18), "iso_gspi_loc0")),
+ [RTD1619B_ISO_GPIO_20] = RTK_PIN_MUX(gpio_20, 0x8, GENMASK(23, 21),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x0, 21), "gpio"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x1, 21), "uart2_loc0"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x2, 21), "pwm0"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x3, 21), "gspi_loc0"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x4, 21), "sc0"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x5, 21), "iso_gspi_loc0")),
+ [RTD1619B_ISO_GPIO_21] = RTK_PIN_MUX(gpio_21, 0x8, GENMASK(26, 24),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x0, 24), "gpio"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x2, 24), "pwm1"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x5, 24), "spdif_optical_loc1")),
+ [RTD1619B_ISO_GPIO_22] = RTK_PIN_MUX(gpio_22, 0x8, GENMASK(28, 27),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x0, 27), "gpio"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x2, 27), "pwm2")),
+ [RTD1619B_ISO_GPIO_23] = RTK_PIN_MUX(gpio_23, 0x8, GENMASK(30, 29),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x0, 29), "gpio"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x1, 29), "etn_led"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x2, 29), "pwm3")),
+ [RTD1619B_ISO_USB_CC2] = RTK_PIN_MUX(usb_cc2, 0x8, GENMASK(31, 31),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x0, 31), "gpio"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x1, 31), "usb_cc2")),
+ [RTD1619B_ISO_GPIO_25] = RTK_PIN_MUX(gpio_25, 0xc, GENMASK(1, 0),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x0, 0), "gpio"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x1, 0), "uart2_loc1"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x2, 0), "pcie1")),
+ [RTD1619B_ISO_GPIO_26] = RTK_PIN_MUX(gpio_26, 0xc, GENMASK(3, 2),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x0, 2), "gpio"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x1, 2), "uart2_loc1"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x2, 2), "vfd"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x3, 2), "pwm0")),
+ [RTD1619B_ISO_GPIO_27] = RTK_PIN_MUX(gpio_27, 0xc, GENMASK(5, 4),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x0, 4), "gpio"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x1, 4), "uart2_loc1"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x2, 4), "vfd"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x3, 4), "pwm1")),
+
+ [RTD1619B_ISO_GPIO_28] = RTK_PIN_MUX(gpio_28, 0xc, GENMASK(7, 6),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x0, 6), "gpio"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x1, 6), "uart2_loc1"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x2, 6), "vfd"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x3, 6), "pwm2")),
+ [RTD1619B_ISO_GPIO_29] = RTK_PIN_MUX(gpio_29, 0xc, GENMASK(8, 8),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x0, 8), "gpio"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x1, 8), "i2c5")),
+ [RTD1619B_ISO_GPIO_30] = RTK_PIN_MUX(gpio_30, 0xc, GENMASK(9, 9),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x0, 9), "gpio")),
+ [RTD1619B_ISO_GPIO_31] = RTK_PIN_MUX(gpio_31, 0xc, GENMASK(12, 10),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x0, 10), "gpio"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x1, 10), "uart2_loc0"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x2, 10), "sc0"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x3, 10), "gspi_loc0"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x5, 10), "iso_gspi_loc0")),
+ [RTD1619B_ISO_GPIO_32] = RTK_PIN_MUX(gpio_32, 0xc, GENMASK(17, 13),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x0, 13), "gpio"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x1, 13), "sd"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x2, 13), "sdio_loc0"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x3, 13), "dmic_loc1"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x4, 13), "ai_loc1"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x5, 13), "scpu_ejtag_loc1"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x6, 13), "acpu_ejtag_loc1"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x7, 13), "vcpu_ejtag_loc1"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x11, 13), "vtc_i2si_loc0"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x14, 13), "ve3_ejtag_loc1"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x15, 13), "aucpu0_ejtag_loc1"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x16, 13), "aucpu1_ejtag_loc1")),
+ [RTD1619B_ISO_GPIO_33] = RTK_PIN_MUX(gpio_33, 0xc, GENMASK(22, 18),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x0, 18), "gpio"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x1, 18), "sd"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x2, 18), "sdio_loc0"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x3, 18), "dmic_loc1"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x4, 18), "ai_loc1"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x5, 18), "scpu_ejtag_loc1"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x6, 18), "acpu_ejtag_loc1"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x7, 18), "vcpu_ejtag_loc1"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x14, 18), "ve3_ejtag_loc1"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x15, 18), "aucpu0_ejtag_loc1"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x16, 18), "aucpu1_ejtag_loc1")),
+ [RTD1619B_ISO_GPIO_34] = RTK_PIN_MUX(gpio_34, 0xc, GENMASK(25, 23),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x0, 23), "gpio"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x1, 23), "sd"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x3, 23), "dmic_loc1"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x4, 23), "ai_loc1"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x5, 23), "i2c4")),
+ [RTD1619B_ISO_GPIO_35] = RTK_PIN_MUX(gpio_35, 0xc, GENMASK(28, 26),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x0, 26), "gpio"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x1, 26), "sd"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x3, 26), "dmic_loc1"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x5, 26), "i2c4")),
+ [RTD1619B_ISO_HIF_DATA] = RTK_PIN_MUX(hif_data, 0x10, GENMASK(4, 0),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x0, 0), "gpio"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x1, 0), "sd"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x2, 0), "sdio_loc0"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x3, 0), "dmic_loc1"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x4, 0), "tdm_ai_loc1"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x5, 0), "scpu_ejtag_loc1"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x6, 0), "acpu_ejtag_loc1"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x7, 0), "vcpu_ejtag_loc1"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x8, 0), "ai_loc1"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x9, 0), "hi"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x10, 0), "hi_m"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x11, 0), "vtc_i2si_loc0"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x12, 0), "vtc_tdm_loc0"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x13, 0), "vtc_dmic_loc0"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x14, 0), "ve3_ejtag_loc1"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x15, 0), "aucpu0_ejtag_loc1"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x16, 0), "aucpu1_ejtag_loc1")),
+ [RTD1619B_ISO_HIF_EN] = RTK_PIN_MUX(hif_en, 0x10, GENMASK(9, 5),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x0, 5), "gpio"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x1, 5), "sd"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x2, 5), "sdio_loc0"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x3, 5), "dmic_loc1"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x4, 5), "tdm_ai_loc1"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x5, 5), "scpu_ejtag_loc1"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x6, 5), "acpu_ejtag_loc1"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x7, 5), "vcpu_ejtag_loc1"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x8, 5), "ai_loc1"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x9, 5), "hi"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x10, 5), "hi_m"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x11, 5), "vtc_i2si_loc0"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x12, 5), "vtc_tdm_loc0"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x13, 5), "vtc_dmic_loc0"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x14, 5), "ve3_ejtag_loc1"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x15, 5), "aucpu0_ejtag_loc1"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x16, 5), "aucpu1_ejtag_loc1")),
+ [RTD1619B_ISO_HIF_RDY] = RTK_PIN_MUX(hif_rdy, 0x10, GENMASK(13, 10),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x0, 10), "gpio"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x1, 10), "sd"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x2, 10), "sdio_loc0"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x3, 10), "dmic_loc1"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x4, 10), "tdm_ai_loc1"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x8, 10), "ai_loc1"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x9, 10), "hi"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x10, 10), "hi_m"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x11, 10), "vtc_i2si_loc0"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x12, 10), "vtc_tdm_loc0"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x13, 10), "vtc_dmic_loc0")),
+
+ [RTD1619B_ISO_HIF_CLK] = RTK_PIN_MUX(hif_clk, 0x10, GENMASK(18, 14),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x0, 14), "gpio"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x1, 14), "sd"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x2, 14), "sdio_loc0"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x3, 14), "dmic_loc1"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x4, 14), "tdm_ai_loc1"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x5, 14), "scpu_ejtag_loc1"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x6, 14), "acpu_ejtag_loc1"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x7, 14), "vcpu_ejtag_loc1"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x8, 14), "ai_loc1"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x9, 14), "hi"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x10, 14), "hi_m"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x11, 14), "vtc_i2si_loc0"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x12, 14), "vtc_tdm_loc0"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x13, 14), "vtc_dmic_loc0"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x14, 14), "ve3_ejtag_loc1"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x15, 14), "aucpu0_ejtag_loc1"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x16, 14), "aucpu1_ejtag_loc1")),
+ [RTD1619B_ISO_GPIO_40] = RTK_PIN_MUX(gpio_40, 0x10, GENMASK(20, 19),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x0, 19), "gpio"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x2, 19), "sdio_loc1")),
+ [RTD1619B_ISO_GPIO_41] = RTK_PIN_MUX(gpio_41, 0x10, GENMASK(22, 21),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x0, 21), "gpio"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x2, 21), "sdio_loc1")),
+ [RTD1619B_ISO_GPIO_42] = RTK_PIN_MUX(gpio_42, 0x10, GENMASK(24, 23),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x0, 23), "gpio"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x2, 23), "sdio_loc1")),
+ [RTD1619B_ISO_GPIO_43] = RTK_PIN_MUX(gpio_43, 0x10, GENMASK(26, 25),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x0, 25), "gpio"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x2, 25), "sdio_loc1")),
+ [RTD1619B_ISO_GPIO_44] = RTK_PIN_MUX(gpio_44, 0x10, GENMASK(28, 27),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x0, 27), "gpio"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x2, 27), "sdio_loc1")),
+ [RTD1619B_ISO_GPIO_45] = RTK_PIN_MUX(gpio_45, 0x10, GENMASK(30, 29),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x0, 29), "gpio"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x2, 29), "sdio_loc1")),
+ [RTD1619B_ISO_GPIO_46] = RTK_PIN_MUX(gpio_46, 0x10, GENMASK(31, 31),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x0, 31), "gpio"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x1, 31), "i2c5")),
+ [RTD1619B_ISO_GPIO_47] = RTK_PIN_MUX(gpio_47, 0x14, GENMASK(1, 0),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x0, 0), "gpio"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x2, 0), "dc_fan"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x3, 0), "pwm3")),
+ [RTD1619B_ISO_GPIO_48] = RTK_PIN_MUX(gpio_48, 0x14, GENMASK(2, 2),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x0, 2), "gpio"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x1, 2), "pll_test_loc1")),
+ [RTD1619B_ISO_GPIO_49] = RTK_PIN_MUX(gpio_49, 0x14, GENMASK(3, 3),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x0, 3), "gpio"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x1, 3), "pll_test_loc1")),
+ [RTD1619B_ISO_GPIO_50] = RTK_PIN_MUX(gpio_50, 0x14, GENMASK(5, 4),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x0, 4), "gpio"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x1, 4), "spdif"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x2, 4), "test_loop_dis")),
+ [RTD1619B_ISO_USB_CC1] = RTK_PIN_MUX(usb_cc1, 0x14, GENMASK(6, 6),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x0, 6), "gpio"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x1, 6), "usb_cc1")),
+ [RTD1619B_ISO_GPIO_52] = RTK_PIN_MUX(gpio_52, 0x14, GENMASK(8, 7),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x0, 7), "gpio"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x1, 7), "pll_test_loc0"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x3, 7), "pcie2")),
+ [RTD1619B_ISO_GPIO_53] = RTK_PIN_MUX(gpio_53, 0x14, GENMASK(9, 9),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x0, 9), "gpio"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x1, 9), "pll_test_loc0")),
+ [RTD1619B_ISO_IR_RX] = RTK_PIN_MUX(ir_rx, 0x14, GENMASK(11, 10),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x0, 10), "gpio"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x1, 10), "ir_rx"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x2, 10), "standby_dbg")),
+ [RTD1619B_ISO_UR0_RX] = RTK_PIN_MUX(ur0_rx, 0x14, GENMASK(12, 12),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x0, 12), "gpio"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x1, 12), "uart0")),
+
+ [RTD1619B_ISO_UR0_TX] = RTK_PIN_MUX(ur0_tx, 0x14, GENMASK(13, 13),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x0, 13), "gpio"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x1, 13), "uart0")),
+ [RTD1619B_ISO_GPIO_57] = RTK_PIN_MUX(gpio_57, 0x14, GENMASK(17, 14),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x0, 14), "gpio"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x1, 14), "tdm_ai_loc0"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x2, 14), "ai_loc0"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x3, 14), "dmic_loc0"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x11, 14), "vtc_i2si_loc1"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x12, 14), "vtc_tdm_loc1"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x13, 14), "vtc_dmic_loc1")),
+ [RTD1619B_ISO_GPIO_58] = RTK_PIN_MUX(gpio_58, 0x14, GENMASK(21, 18),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x0, 18), "gpio"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x1, 18), "tdm_ai_loc0"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x2, 18), "ai_loc0"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x3, 18), "dmic_loc0"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x11, 18), "vtc_i2si_loc1"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x12, 18), "vtc_tdm_loc1"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x13, 18), "vtc_dmic_loc1")),
+ [RTD1619B_ISO_GPIO_59] = RTK_PIN_MUX(gpio_59, 0x14, GENMASK(25, 22),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x0, 22), "gpio"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x1, 22), "tdm_ai_loc0"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x2, 22), "ai_loc0"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x3, 22), "dmic_loc0"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x11, 22), "vtc_i2si_loc1"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x12, 22), "vtc_tdm_loc1"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x13, 22), "vtc_dmic_loc1")),
+ [RTD1619B_ISO_GPIO_60] = RTK_PIN_MUX(gpio_60, 0x14, GENMASK(29, 26),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x0, 26), "gpio"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x1, 26), "tdm_ai_loc0"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x2, 26), "ai_loc0"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x3, 26), "dmic_loc0"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x11, 26), "vtc_i2si_loc1"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x12, 26), "vtc_tdm_loc1"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x13, 26), "vtc_dmic_loc1")),
+ [RTD1619B_ISO_GPIO_61] = RTK_PIN_MUX(gpio_61, 0x18, GENMASK(3, 0),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x0, 0), "gpio"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x1, 0), "ai_loc0"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x3, 0), "dmic_loc0"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x11, 0), "vtc_i2si_loc1")),
+ [RTD1619B_ISO_GPIO_62] = RTK_PIN_MUX(gpio_62, 0x18, GENMASK(5, 4),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x0, 4), "gpio"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x1, 4), "ai_loc0"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x3, 4), "dmic_loc0")),
+ [RTD1619B_ISO_GPIO_63] = RTK_PIN_MUX(gpio_63, 0x18, GENMASK(7, 6),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x0, 6), "gpio"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x1, 6), "ai_loc0"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x2, 6), "i2c3"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x3, 6), "dmic_loc0")),
+ [RTD1619B_ISO_GPIO_64] = RTK_PIN_MUX(gpio_64, 0x18, GENMASK(9, 8),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x0, 8), "gpio"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x2, 8), "i2c3"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x3, 8), "dmic_loc0")),
+ [RTD1619B_ISO_GPIO_65] = RTK_PIN_MUX(gpio_65, 0x18, GENMASK(10, 10),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x0, 10), "gpio")),
+ [RTD1619B_ISO_GPIO_66] = RTK_PIN_MUX(gpio_66, 0x18, GENMASK(14, 11),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x0, 11), "gpio"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x2, 11), "tp0"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x4, 11), "ao"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x11, 11), "vtc_i2so")),
+ [RTD1619B_ISO_GPIO_67] = RTK_PIN_MUX(gpio_67, 0x18, GENMASK(18, 15),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x0, 15), "gpio"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x2, 15), "tp0"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x4, 15), "ao"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x11, 15), "vtc_i2so")),
+ [RTD1619B_ISO_GPIO_68] = RTK_PIN_MUX(gpio_68, 0x18, GENMASK(22, 19),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x0, 19), "gpio"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x2, 19), "tp0"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x4, 19), "ao"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x11, 19), "vtc_i2so")),
+ [RTD1619B_ISO_GPIO_69] = RTK_PIN_MUX(gpio_69, 0x18, GENMASK(26, 23),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x0, 23), "gpio"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x2, 23), "tp0"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x3, 23), "tp1"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x4, 23), "ao"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x11, 23), "vtc_i2so")),
+
+ [RTD1619B_ISO_GPIO_70] = RTK_PIN_MUX(gpio_70, 0x18, GENMASK(29, 27),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x0, 27), "gpio"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x2, 27), "tp0"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x3, 27), "tp1"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x4, 27), "ao")),
+ [RTD1619B_ISO_GPIO_71] = RTK_PIN_MUX(gpio_71, 0x1c, GENMASK(2, 0),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x0, 0), "gpio"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x2, 0), "tp0"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x3, 0), "tp1"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x4, 0), "ao"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x5, 0), "scpu_ejtag_loc2"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x6, 0), "acpu_ejtag_loc2"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x7, 0), "vcpu_ejtag_loc2"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x8, 0), "ve3_ejtag_loc2"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x9, 0), "aucpu0_ejtag_loc2"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x10, 0), "aucpu1_ejtag_loc2")),
+ [RTD1619B_ISO_GPIO_72] = RTK_PIN_MUX(gpio_72, 0x1c, GENMASK(6, 3),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x0, 3), "gpio"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x2, 3), "tp0"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x3, 3), "tp1"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x4, 3), "ao"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x5, 3), "scpu_ejtag_loc2"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x6, 3), "acpu_ejtag_loc2"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x7, 3), "vcpu_ejtag_loc2"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x8, 3), "ve3_ejtag_loc2"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x9, 3), "aucpu0_ejtag_loc2"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x10, 3), "aucpu1_ejtag_loc2")),
+ [RTD1619B_ISO_GPIO_73] = RTK_PIN_MUX(gpio_73, 0x1c, GENMASK(10, 7),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x0, 7), "gpio"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x2, 7), "tp0"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x5, 7), "scpu_ejtag_loc2"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x6, 7), "acpu_ejtag_loc2"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x7, 7), "vcpu_ejtag_loc2"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x8, 7), "ve3_ejtag_loc2"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x9, 7), "aucpu0_ejtag_loc2"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x10, 7), "aucpu1_ejtag_loc2")),
+ [RTD1619B_ISO_GPIO_74] = RTK_PIN_MUX(gpio_74, 0x1c, GENMASK(14, 11),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x0, 11), "gpio"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x2, 11), "tp0"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x5, 11), "scpu_ejtag_loc2"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x6, 11), "acpu_ejtag_loc2"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x7, 11), "vcpu_ejtag_loc2"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x8, 11), "ve3_ejtag_loc2"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x9, 11), "aucpu0_ejtag_loc2"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x10, 11), "aucpu1_ejtag_loc2")),
+ [RTD1619B_ISO_GPIO_75] = RTK_PIN_MUX(gpio_75, 0x1c, GENMASK(18, 15),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x0, 15), "gpio"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x2, 15), "tp0"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x5, 15), "scpu_ejtag_loc2"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x6, 15), "acpu_ejtag_loc2"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x7, 15), "vcpu_ejtag_loc2"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x8, 15), "ve3_ejtag_loc2"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x9, 15), "aucpu0_ejtag_loc2"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x10, 15), "aucpu1_ejtag_loc2")),
+ [RTD1619B_ISO_GPIO_76] = RTK_PIN_MUX(gpio_76, 0x1c, GENMASK(22, 19),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x0, 19), "gpio"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x2, 19), "tp0"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x5, 19), "scpu_ejtag_loc2"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x6, 19), "acpu_ejtag_loc2"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x7, 19), "vcpu_ejtag_loc2"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x8, 19), "ve3_ejtag_loc2"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x9, 19), "aucpu0_ejtag_loc2"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x10, 19), "aucpu1_ejtag_loc2")),
+
+ [RTD1619B_ISO_UR2_LOC] = RTK_PIN_MUX(ur2_loc, 0x120, GENMASK(1, 0),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x0, 0), "uart2_disable"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x1, 0), "uart2_loc0"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x2, 0), "uart2_loc1")),
+ [RTD1619B_ISO_GSPI_LOC] = RTK_PIN_MUX(gspi_loc, 0x120, GENMASK(3, 2),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x0, 2), "gspi_disable"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x1, 2), "gspi_loc0"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x2, 2), "gspi_loc1")),
+ [RTD1619B_ISO_SDIO_LOC] = RTK_PIN_MUX(sdio_loc, 0x120, GENMASK(5, 4),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x0, 4), "sdio_disable"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x1, 4), "sdio_loc0"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x2, 4), "sdio_loc1")),
+ [RTD1619B_ISO_HI_LOC] = RTK_PIN_MUX(hi_loc, 0x120, GENMASK(7, 6),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x0, 6), "hi_loc_disable"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x1, 6), "hi_loc0")),
+ [RTD1619B_ISO_HI_WIDTH] = RTK_PIN_MUX(hi_width, 0x120, GENMASK(9, 8),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x0, 8), "hi_width_disable"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x1, 8), "hi_width_1bit")),
+ [RTD1619B_ISO_SF_EN] = RTK_PIN_MUX(sf_en, 0x120, GENMASK(11, 11),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x0, 11), "sf_disable"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x1, 11), "sf_enable")),
+ [RTD1619B_ISO_ARM_TRACE_DBG_EN] = RTK_PIN_MUX(arm_trace_dbg_en, 0x120, GENMASK(12, 12),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x0, 12), "arm_trace_debug_disable"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x1, 12), "arm_trace_debug_enable")),
+ [RTD1619B_ISO_PWM_01_OPEN_DRAIN_EN_LOC0] = RTK_PIN_MUX(pwm_01_open_drain_en_loc0, 0x120,
+ GENMASK(13, 13),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x0, 13), "pwm_normal"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x1, 13), "pwm_open_drain")),
+ [RTD1619B_ISO_PWM_23_OPEN_DRAIN_EN_LOC0] = RTK_PIN_MUX(pwm_23_open_drain_en_loc0, 0x120,
+ GENMASK(14, 14),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x0, 14), "pwm_normal"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x1, 14), "pwm_open_drain")),
+ [RTD1619B_ISO_PWM_01_OPEN_DRAIN_EN_LOC1] = RTK_PIN_MUX(pwm_01_open_drain_en_loc1, 0x120,
+ GENMASK(15, 15),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x0, 15), "pwm_normal"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x1, 15), "pwm_open_drain")),
+ [RTD1619B_ISO_PWM_23_OPEN_DRAIN_EN_LOC1] = RTK_PIN_MUX(pwm_23_open_drain_en_loc1, 0x120,
+ GENMASK(16, 16),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x0, 16), "pwm_normal"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x1, 16), "pwm_open_drain")),
+ [RTD1619B_ISO_EJTAG_ACPU_LOC] = RTK_PIN_MUX(ejtag_acpu_loc, 0x120, GENMASK(19, 17),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x0, 17), "acpu_ejtag_disable"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x1, 17), "acpu_ejtag_loc0"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x2, 17), "acpu_ejtag_loc1"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x4, 17), "acpu_ejtag_loc2")),
+ [RTD1619B_ISO_EJTAG_VCPU_LOC] = RTK_PIN_MUX(ejtag_vcpu_loc, 0x120, GENMASK(22, 20),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x0, 20), "vcpu_ejtag_disable"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x1, 20), "vcpu_ejtag_loc0"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x2, 20), "vcpu_ejtag_loc1"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x4, 20), "vcpu_ejtag_loc2")),
+ [RTD1619B_ISO_EJTAG_SCPU_LOC] = RTK_PIN_MUX(ejtag_scpu_loc, 0x120, GENMASK(25, 23),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x0, 23), "scpu_ejtag_disable"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x1, 23), "scpu_ejtag_loc0"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x2, 23), "scpu_ejtag_loc1"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x4, 23), "scpu_ejtag_loc2")),
+ [RTD1619B_ISO_DMIC_LOC] = RTK_PIN_MUX(dmic_loc, 0x120, GENMASK(27, 26),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x1, 26), "dmic_loc0"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x2, 26), "dmic_loc1")),
+ [RTD1619B_ISO_ISO_GSPI_LOC] = RTK_PIN_MUX(iso_gspi_loc, 0x120, GENMASK(29, 28),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x0, 28), "iso_gspi_disable"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x1, 28), "iso_gspi_loc0"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x2, 28), "iso_gspi_loc1")),
+ [RTD1619B_ISO_EJTAG_VE3_LOC] = RTK_PIN_MUX(ejtag_ve3_loc, 0x124, GENMASK(20, 18),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x0, 18), "ve3_ejtag_disable"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x1, 18), "ve3_ejtag_loc0"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x2, 18), "ve3_ejtag_loc1"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x4, 18), "ve3_ejtag_loc2")),
+ [RTD1619B_ISO_EJTAG_AUCPU1_LOC] = RTK_PIN_MUX(ejtag_aucpu1_loc, 0x124, GENMASK(23, 21),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x0, 21), "aucpu1_ejtag_disable"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x1, 21), "aucpu1_ejtag_loc0"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x2, 21), "aucpu1_ejtag_loc1"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x4, 21), "aucpu1_ejtag_loc2")),
+ [RTD1619B_ISO_EJTAG_AUCPU0_LOC] = RTK_PIN_MUX(ejtag_aucpu0_loc, 0x124, GENMASK(26, 24),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x0, 24), "aucpu0_ejtag_disable"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x1, 24), "aucpu0_ejtag_loc0"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x2, 24), "aucpu0_ejtag_loc1"),
+ RTK_PIN_FUNC(SHIFT_LEFT(0x4, 24), "aucpu0_ejtag_loc2")),
+};
+
+static const struct rtd_pin_config_desc rtd1619b_iso_configs[] = {
+ [RTD1619B_ISO_GPIO_17] = RTK_PIN_CONFIG(gpio_17, 0x20, 0, 1, 2, 0, 3, 4, PADDRI_4_8),
+ [RTD1619B_ISO_GPIO_19] = RTK_PIN_CONFIG(gpio_19, 0x20, 5, 1, 2, 0, 3, 4, PADDRI_4_8),
+ [RTD1619B_ISO_GPIO_50] = RTK_PIN_CONFIG(gpio_50, 0x20, 10, 1, 2, 0, 3, 4, PADDRI_4_8),
+ [RTD1619B_ISO_GPIO_21] = RTK_PIN_CONFIG(gpio_21, 0x20, 15, 1, 2, 0, 3, 4, PADDRI_4_8),
+ [RTD1619B_ISO_GPIO_66] = RTK_PIN_CONFIG(gpio_66, 0x20, 20, 1, 2, 0, 3, 4, PADDRI_4_8),
+ [RTD1619B_ISO_GPIO_67] = RTK_PIN_CONFIG(gpio_67, 0x20, 25, 1, 2, 0, 3, 4, PADDRI_4_8),
+ [RTD1619B_ISO_GPIO_68] = RTK_PIN_CONFIG(gpio_68, 0x24, 0, 1, 2, 0, 3, 4, PADDRI_4_8),
+ [RTD1619B_ISO_GPIO_69] = RTK_PIN_CONFIG(gpio_69, 0x24, 5, 1, 2, 0, 3, 4, PADDRI_4_8),
+ [RTD1619B_ISO_GPIO_70] = RTK_PIN_CONFIG(gpio_70, 0x24, 10, 1, 2, 0, 3, 4, PADDRI_4_8),
+ [RTD1619B_ISO_GPIO_71] = RTK_PIN_CONFIG(gpio_71, 0x24, 15, 1, 2, 0, 3, 4, PADDRI_4_8),
+ [RTD1619B_ISO_GPIO_72] = RTK_PIN_CONFIG(gpio_72, 0x24, 20, 1, 2, 0, 3, 4, PADDRI_4_8),
+ [RTD1619B_ISO_GPIO_73] = RTK_PIN_CONFIG(gpio_73, 0x24, 25, 1, 2, 0, 3, 4, PADDRI_4_8),
+ [RTD1619B_ISO_GPIO_74] = RTK_PIN_CONFIG(gpio_74, 0x28, 0, 1, 2, 0, 3, 4, PADDRI_4_8),
+ [RTD1619B_ISO_GPIO_75] = RTK_PIN_CONFIG(gpio_75, 0x28, 5, 1, 2, 0, 3, 4, PADDRI_4_8),
+ [RTD1619B_ISO_GPIO_76] = RTK_PIN_CONFIG(gpio_76, 0x28, 10, 1, 2, 0, 3, 4, PADDRI_4_8),
+ [RTD1619B_ISO_SPI_SI] = RTK_PIN_CONFIG(spi_si, 0x28, 15, 0, 1, 3, 2, 12, NA),
+ [RTD1619B_ISO_SPI_SCK] = RTK_PIN_CONFIG(spi_sck, 0x2c, 0, 0, 1, 3, 2, 12, NA),
+ [RTD1619B_ISO_SPI_CE_N] = RTK_PIN_CONFIG(spi_ce_n, 0x2c, 13, 0, 1, 3, 2, 12, NA),
+ [RTD1619B_ISO_SPI_SO] = RTK_PIN_CONFIG(spi_so, 0x2c, 26, 0, 1, 3, 2, 12, NA),
+ [RTD1619B_ISO_EMMC_CLK] = RTK_PIN_CONFIG(emmc_clk, 0x30, 7, 0, 1, 3, 2, 12, NA),
+ [RTD1619B_ISO_EMMC_CMD] = RTK_PIN_CONFIG(emmc_cmd, 0x34, 0, 0, 1, 3, 2, 13, NA),
+ [RTD1619B_ISO_EMMC_RST_N] = RTK_PIN_CONFIG(emmc_rst_n, 0x34, 14, 0, 1, 3, 2, 12, NA),
+ [RTD1619B_ISO_EMMC_DD_SB] = RTK_PIN_CONFIG(emmc_dd_sb, 0x34, 27, 0, 1, 3, 2, 12, NA),
+ [RTD1619B_ISO_EMMC_DATA_5] = RTK_PIN_CONFIG(emmc_data_5, 0x38, 8, 0, 1, 3, 2, 12, NA),
+ [RTD1619B_ISO_EMMC_DATA_3] = RTK_PIN_CONFIG(emmc_data_3, 0x3c, 0, 0, 1, 3, 2, 12, NA),
+ [RTD1619B_ISO_EMMC_DATA_4] = RTK_PIN_CONFIG(emmc_data_4, 0x3c, 13, 0, 1, 3, 2, 12, NA),
+ [RTD1619B_ISO_EMMC_DATA_0] = RTK_PIN_CONFIG(emmc_data_0, 0x3c, 26, 0, 1, 3, 2, 12, NA),
+ [RTD1619B_ISO_EMMC_DATA_1] = RTK_PIN_CONFIG(emmc_data_1, 0x40, 7, 0, 1, 3, 2, 12, NA),
+ [RTD1619B_ISO_EMMC_DATA_2] = RTK_PIN_CONFIG(emmc_data_2, 0x44, 0, 0, 1, 3, 2, 12, NA),
+ [RTD1619B_ISO_EMMC_DATA_7] = RTK_PIN_CONFIG(emmc_data_7, 0x44, 13, 0, 1, 3, 2, 12, NA),
+ [RTD1619B_ISO_EMMC_DATA_6] = RTK_PIN_CONFIG(emmc_data_6, 0x44, 26, 0, 1, 3, 2, 12, NA),
+ [RTD1619B_ISO_USB_CC1] = RTK_PIN_CONFIG(usb_cc1, 0x48, 7, NA, NA, 0, 1, 9, PADDRI_4_8),
+ [RTD1619B_ISO_USB_CC2] = RTK_PIN_CONFIG(usb_cc2, 0x48, 10, NA, NA, 0, 1, 9, PADDRI_4_8),
+ [RTD1619B_ISO_GPIO_26] = RTK_PIN_CONFIG(gpio_26, 0x48, 13, 1, 2, 0, 3, 4, PADDRI_4_8),
+ [RTD1619B_ISO_GPIO_27] = RTK_PIN_CONFIG(gpio_27, 0x48, 18, 1, 2, 0, 3, 4, PADDRI_4_8),
+ [RTD1619B_ISO_GPIO_28] = RTK_PIN_CONFIG(gpio_28, 0x48, 23, 1, 2, 0, 3, 4, PADDRI_4_8),
+ [RTD1619B_ISO_GPIO_29] = RTK_PIN_CONFIG(gpio_29, 0x4c, 0, 1, 2, 0, 3, 4, PADDRI_4_8),
+ [RTD1619B_ISO_GPIO_46] = RTK_PIN_CONFIG(gpio_46, 0x4c, 5, 1, 2, 0, 3, 4, PADDRI_4_8),
+ [RTD1619B_ISO_GPIO_48] = RTK_PIN_CONFIG(gpio_48, 0x4c, 10, 1, 2, 0, 3, 4, PADDRI_4_8),
+ [RTD1619B_ISO_GPIO_49] = RTK_PIN_CONFIG(gpio_49, 0x4c, 15, 1, 2, 0, 3, 4, PADDRI_4_8),
+ [RTD1619B_ISO_GPIO_53] = RTK_PIN_CONFIG(gpio_53, 0x4c, 20, 1, 2, 0, 3, 4, PADDRI_4_8),
+ [RTD1619B_ISO_GPIO_65] = RTK_PIN_CONFIG(gpio_65, 0x4c, 25, 1, 2, 0, 3, 4, PADDRI_4_8),
+ [RTD1619B_ISO_GPIO_14] = RTK_PIN_CONFIG(gpio_14, 0x50, 0, 1, 2, 0, 3, 4, PADDRI_4_8),
+ [RTD1619B_ISO_GPIO_15] = RTK_PIN_CONFIG(gpio_15, 0x50, 5, 1, 2, 0, 3, 4, PADDRI_4_8),
+ [RTD1619B_ISO_GPIO_23] = RTK_PIN_CONFIG(gpio_23, 0x50, 10, 1, 2, 0, 3, 4, PADDRI_4_8),
+ [RTD1619B_ISO_IR_RX] = RTK_PIN_CONFIG(ir_rx, 0x50, 20, 1, 2, 0, 3, 4, PADDRI_4_8),
+ [RTD1619B_ISO_GPIO_57] = RTK_PIN_CONFIG(gpio_57, 0x50, 25, 1, 2, 0, 3, 4, PADDRI_4_8),
+ [RTD1619B_ISO_GPIO_58] = RTK_PIN_CONFIG(gpio_58, 0x50, 30, 1, 2, 0, 3, 4, PADDRI_4_8),
+ [RTD1619B_ISO_GPIO_59] = RTK_PIN_CONFIG(gpio_59, 0x54, 3, 1, 2, 0, 3, 4, PADDRI_4_8),
+ [RTD1619B_ISO_GPIO_60] = RTK_PIN_CONFIG(gpio_60, 0x54, 8, 1, 2, 0, 3, 4, PADDRI_4_8),
+ [RTD1619B_ISO_GPIO_61] = RTK_PIN_CONFIG(gpio_61, 0x54, 13, 1, 2, 0, 3, 4, PADDRI_4_8),
+ [RTD1619B_ISO_GPIO_62] = RTK_PIN_CONFIG(gpio_62, 0x54, 18, 1, 2, 0, 3, 4, PADDRI_4_8),
+ [RTD1619B_ISO_GPIO_63] = RTK_PIN_CONFIG(gpio_63, 0x54, 23, 1, 2, 0, 3, 4, PADDRI_4_8),
+ [RTD1619B_ISO_GPIO_64] = RTK_PIN_CONFIG(gpio_64, 0x58, 0, 1, 2, 0, 3, 4, PADDRI_4_8),
+ [RTD1619B_ISO_UR0_TX] = RTK_PIN_CONFIG(ur0_tx, 0x58, 5, 1, 2, 0, 3, 4, PADDRI_4_8),
+ [RTD1619B_ISO_UR0_RX] = RTK_PIN_CONFIG(ur0_rx, 0x58, 13, 1, 2, 0, 3, 4, PADDRI_4_8),
+ [RTD1619B_ISO_GPIO_12] = RTK_PIN_CONFIG(gpio_12, 0x58, 18, 1, 2, 0, 3, 4, PADDRI_4_8),
+ [RTD1619B_ISO_GPIO_13] = RTK_PIN_CONFIG(gpio_13, 0x58, 23, 1, 2, 0, 3, 4, PADDRI_4_8),
+ [RTD1619B_ISO_GPIO_30] = RTK_PIN_CONFIG(gpio_30, 0x58, 28, 1, 2, 0, 3, 4, PADDRI_4_8),
+ [RTD1619B_ISO_GPIO_7] = RTK_PIN_CONFIG(gpio_7, 0x5c, 1, 1, 2, 0, 3, 4, PADDRI_4_8),
+ [RTD1619B_ISO_GPIO_16] = RTK_PIN_CONFIG(gpio_16, 0x5c, 6, 1, 2, 0, 3, 4, PADDRI_4_8),
+ [RTD1619B_ISO_GPIO_18] = RTK_PIN_CONFIG(gpio_18, 0x5c, 11, 1, 2, 0, 3, 4, PADDRI_4_8),
+ [RTD1619B_ISO_GPIO_20] = RTK_PIN_CONFIG(gpio_20, 0x5c, 16, 1, 2, 0, 3, 4, PADDRI_4_8),
+ [RTD1619B_ISO_GPIO_22] = RTK_PIN_CONFIG(gpio_22, 0x5c, 21, 1, 2, 0, 3, 4, PADDRI_4_8),
+ [RTD1619B_ISO_GPIO_31] = RTK_PIN_CONFIG(gpio_31, 0x5c, 26, 1, 2, 0, 3, 4, PADDRI_4_8),
+ [RTD1619B_ISO_GPIO_47] = RTK_PIN_CONFIG(gpio_47, 0x60, 12, 1, 2, 0, 3, 4, PADDRI_4_8),
+ [RTD1619B_ISO_GPIO_25] = RTK_PIN_CONFIG(gpio_25, 0x60, 17, 1, 2, 0, 3, 4, PADDRI_4_8),
+ [RTD1619B_ISO_GPIO_6] = RTK_PIN_CONFIG(gpio_6, 0x60, 22, 1, 2, 0, 3, 4, PADDRI_4_8),
+ [RTD1619B_ISO_GPIO_5] = RTK_PIN_CONFIG(gpio_5, 0x60, 27, 1, 2, 0, 3, 4, PADDRI_4_8),
+ [RTD1619B_ISO_GPIO_4] = RTK_PIN_CONFIG(gpio_4, 0x64, 0, 1, 2, 0, 3, 4, PADDRI_4_8),
+ [RTD1619B_ISO_GPIO_3] = RTK_PIN_CONFIG(gpio_3, 0x64, 5, 1, 2, 0, 3, 4, PADDRI_4_8),
+ [RTD1619B_ISO_GPIO_2] = RTK_PIN_CONFIG(gpio_2, 0x64, 10, 1, 2, 0, 3, 4, PADDRI_4_8),
+ [RTD1619B_ISO_GPIO_1] = RTK_PIN_CONFIG(gpio_1, 0x64, 15, 1, 2, 0, 3, 4, PADDRI_4_8),
+ [RTD1619B_ISO_GPIO_0] = RTK_PIN_CONFIG(gpio_0, 0x64, 20, 1, 2, 0, 3, 4, PADDRI_4_8),
+ [RTD1619B_ISO_GPIO_52] = RTK_PIN_CONFIG(gpio_52, 0x64, 25, 1, 2, 0, 3, 4, PADDRI_4_8),
+ [RTD1619B_ISO_GPIO_35] = RTK_PIN_CONFIG(gpio_35, 0x68, 0, 1, 2, 0, 3, 4, PADDRI_4_8),
+ [RTD1619B_ISO_GPIO_34] = RTK_PIN_CONFIG(gpio_34, 0x68, 5, 1, 2, 0, 3, 4, PADDRI_4_8),
+ [RTD1619B_ISO_GPIO_40] = RTK_PIN_CONFIG(gpio_40, 0x68, 10, 0, 1, 3, 2, 12, NA),
+ [RTD1619B_ISO_GPIO_41] = RTK_PIN_CONFIG(gpio_41, 0x6c, 0, 0, 1, 3, 2, 12, NA),
+ [RTD1619B_ISO_GPIO_42] = RTK_PIN_CONFIG(gpio_42, 0x6c, 13, 0, 1, 3, 2, 12, NA),
+ [RTD1619B_ISO_GPIO_43] = RTK_PIN_CONFIG(gpio_43, 0x70, 0, 0, 1, 3, 2, 12, NA),
+ [RTD1619B_ISO_GPIO_44] = RTK_PIN_CONFIG(gpio_44, 0x70, 13, 0, 1, 3, 2, 12, NA),
+ [RTD1619B_ISO_GPIO_45] = RTK_PIN_CONFIG(gpio_45, 0x70, 26, 0, 1, 3, 2, 12, NA),
+ [RTD1619B_ISO_GPIO_8] = RTK_PIN_CONFIG(gpio_8, 0x74, 7, 1, 2, 0, 3, 4, PADDRI_4_8),
+ [RTD1619B_ISO_GPIO_9] = RTK_PIN_CONFIG(gpio_9, 0x74, 12, 1, 2, 0, 3, 4, PADDRI_4_8),
+ [RTD1619B_ISO_GPIO_10] = RTK_PIN_CONFIG(gpio_10, 0x74, 17, 1, 2, 0, 3, 4, PADDRI_4_8),
+ [RTD1619B_ISO_GPIO_11] = RTK_PIN_CONFIG(gpio_11, 0x74, 22, 1, 2, 0, 3, 4, PADDRI_4_8),
+ [RTD1619B_ISO_HIF_RDY] = RTK_PIN_CONFIG(hif_rdy, 0x78, 0, 0, 1, 3, 2, 12, NA),
+ [RTD1619B_ISO_HIF_CLK] = RTK_PIN_CONFIG(hif_clk, 0x78, 13, 0, 1, 3, 2, 12, NA),
+ [RTD1619B_ISO_GPIO_32] = RTK_PIN_CONFIG(gpio_32, 0x78, 26, 0, 1, 3, 2, 12, NA),
+ [RTD1619B_ISO_GPIO_33] = RTK_PIN_CONFIG(gpio_33, 0x7c, 7, 0, 1, 3, 2, 12, NA),
+ [RTD1619B_ISO_HIF_DATA] = RTK_PIN_CONFIG(hif_data, 0x80, 0, 0, 1, 3, 2, 12, NA),
+ [RTD1619B_ISO_HIF_EN] = RTK_PIN_CONFIG(hif_en, 0x80, 13, 0, 1, 3, 2, 12, NA),
+};
+
+static const struct rtd_pin_sconfig_desc rtd1619b_iso_sconfigs[] = {
+ RTK_PIN_SCONFIG(spi_si, 0x28, 18, 3, 21, 3, 24, 3),
+ RTK_PIN_SCONFIG(spi_sck, 0x2c, 3, 3, 6, 3, 9, 3),
+ RTK_PIN_SCONFIG(spi_ce_n, 0x2c, 16, 3, 19, 3, 22, 3),
+ RTK_PIN_SCONFIG(spi_so, 0x2c, 29, 3, 32, 3, 35, 3),
+ RTK_PIN_SCONFIG(emmc_clk, 0x30, 10, 3, 13, 3, 16, 3),
+ RTK_PIN_SCONFIG(emmc_cmd, 0x34, 3, 3, 6, 3, 9, 3),
+ RTK_PIN_SCONFIG(emmc_rst_n, 0x34, 17, 3, 20, 3, 23, 3),
+ RTK_PIN_SCONFIG(emmc_dd_sb, 0x34, 30, 3, 33, 3, 36, 3),
+ RTK_PIN_SCONFIG(emmc_data_5, 0x38, 11, 3, 14, 3, 17, 3),
+ RTK_PIN_SCONFIG(emmc_data_3, 0x3c, 3, 3, 6, 3, 9, 3),
+ RTK_PIN_SCONFIG(emmc_data_4, 0x3c, 16, 3, 19, 3, 22, 3),
+ RTK_PIN_SCONFIG(emmc_data_0, 0x3c, 29, 3, 32, 3, 35, 3),
+ RTK_PIN_SCONFIG(emmc_data_1, 0x40, 10, 3, 13, 3, 16, 3),
+ RTK_PIN_SCONFIG(emmc_data_2, 0x44, 3, 3, 6, 3, 9, 3),
+ RTK_PIN_SCONFIG(emmc_data_7, 0x44, 16, 3, 19, 3, 22, 3),
+ RTK_PIN_SCONFIG(emmc_data_6, 0x44, 29, 3, 32, 3, 35, 3),
+ RTK_PIN_SCONFIG(gpio_40, 0x68, 13, 3, 16, 3, 19, 3),
+ RTK_PIN_SCONFIG(gpio_41, 0x6c, 3, 3, 6, 3, 9, 3),
+ RTK_PIN_SCONFIG(gpio_42, 0x6c, 16, 3, 19, 3, 22, 3),
+ RTK_PIN_SCONFIG(gpio_43, 0x70, 3, 3, 6, 3, 9, 3),
+ RTK_PIN_SCONFIG(gpio_44, 0x70, 16, 3, 19, 3, 22, 3),
+ RTK_PIN_SCONFIG(gpio_45, 0x70, 29, 3, 32, 3, 35, 3),
+ RTK_PIN_SCONFIG(hif_rdy, 0x78, 3, 3, 6, 3, 9, 3),
+ RTK_PIN_SCONFIG(hif_clk, 0x78, 16, 3, 19, 3, 22, 3),
+ RTK_PIN_SCONFIG(gpio_32, 0x78, 29, 3, 32, 3, 35, 3),
+ RTK_PIN_SCONFIG(gpio_33, 0x7c, 10, 3, 13, 3, 16, 3),
+ RTK_PIN_SCONFIG(hif_data, 0x80, 3, 3, 6, 3, 9, 3),
+ RTK_PIN_SCONFIG(hif_en, 0x80, 16, 3, 19, 3, 22, 3),
+};
+
+static const struct rtd_pinctrl_desc rtd1619b_iso_pinctrl_desc = {
+ .pins = rtd1619b_iso_pins,
+ .num_pins = ARRAY_SIZE(rtd1619b_iso_pins),
+ .groups = rtd1619b_pin_groups,
+ .num_groups = ARRAY_SIZE(rtd1619b_pin_groups),
+ .functions = rtd1619b_pin_functions,
+ .num_functions = ARRAY_SIZE(rtd1619b_pin_functions),
+ .muxes = rtd1619b_iso_muxes,
+ .num_muxes = ARRAY_SIZE(rtd1619b_iso_muxes),
+ .configs = rtd1619b_iso_configs,
+ .num_configs = ARRAY_SIZE(rtd1619b_iso_configs),
+ .sconfigs = rtd1619b_iso_sconfigs,
+ .num_sconfigs = ARRAY_SIZE(rtd1619b_iso_sconfigs),
+};
+
+static int rtd1619b_pinctrl_probe(struct platform_device *pdev)
+{
+ return rtd_pinctrl_probe(pdev, &rtd1619b_iso_pinctrl_desc);
+}
+
+static const struct of_device_id rtd1619b_pinctrl_of_match[] = {
+ { .compatible = "realtek,rtd1619b-pinctrl", },
+ {},
+};
+
+static struct platform_driver rtd1619b_pinctrl_driver = {
+ .driver = {
+ .name = "rtd1619b-pinctrl",
+ .of_match_table = rtd1619b_pinctrl_of_match,
+ },
+ .probe = rtd1619b_pinctrl_probe,
+};
+
+static int __init rtd1619b_pinctrl_init(void)
+{
+ return platform_driver_register(&rtd1619b_pinctrl_driver);
+}
+arch_initcall(rtd1619b_pinctrl_init);
+
+static void __exit rtd1619b_pinctrl_exit(void)
+{
+ platform_driver_unregister(&rtd1619b_pinctrl_driver);
+}
+module_exit(rtd1619b_pinctrl_exit);
+
+MODULE_LICENSE("GPL");
+MODULE_AUTHOR("Realtek Semiconductor Corporation");
+MODULE_DESCRIPTION("Realtek DHC SoC RTD1619B pinctrl driver");
diff --git a/drivers/pinctrl/renesas/gpio.c b/drivers/pinctrl/renesas/gpio.c
index 5758daf94f..a5136dacaa 100644
--- a/drivers/pinctrl/renesas/gpio.c
+++ b/drivers/pinctrl/renesas/gpio.c
@@ -135,12 +135,12 @@ static int gpio_pin_request(struct gpio_chip *gc, unsigned offset)
if (idx < 0 || pfc->info->pins[idx].enum_id == 0)
return -EINVAL;
- return pinctrl_gpio_request(gc->base + offset);
+ return pinctrl_gpio_request(gc, offset);
}
static void gpio_pin_free(struct gpio_chip *gc, unsigned offset)
{
- return pinctrl_gpio_free(gc->base + offset);
+ return pinctrl_gpio_free(gc, offset);
}
static void gpio_pin_set_value(struct sh_pfc_chip *chip, unsigned offset,
@@ -164,7 +164,7 @@ static void gpio_pin_set_value(struct sh_pfc_chip *chip, unsigned offset,
static int gpio_pin_direction_input(struct gpio_chip *gc, unsigned offset)
{
- return pinctrl_gpio_direction_input(gc->base + offset);
+ return pinctrl_gpio_direction_input(gc, offset);
}
static int gpio_pin_direction_output(struct gpio_chip *gc, unsigned offset,
@@ -172,7 +172,7 @@ static int gpio_pin_direction_output(struct gpio_chip *gc, unsigned offset,
{
gpio_pin_set_value(gpiochip_get_data(gc), offset, value);
- return pinctrl_gpio_direction_output(gc->base + offset);
+ return pinctrl_gpio_direction_output(gc, offset);
}
static int gpio_pin_get(struct gpio_chip *gc, unsigned offset)
diff --git a/drivers/pinctrl/renesas/pfc-r8a7778.c b/drivers/pinctrl/renesas/pfc-r8a7778.c
index c52761d80f..db92d6d91d 100644
--- a/drivers/pinctrl/renesas/pfc-r8a7778.c
+++ b/drivers/pinctrl/renesas/pfc-r8a7778.c
@@ -1424,6 +1424,24 @@ I2C_PFC_MUX(i2c3_b, SDA3_B, SCL3_B);
I2C_PFC_PIN(i2c3_c, RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 23));
I2C_PFC_MUX(i2c3_c, SDA3_C, SCL3_C);
+/* - LBSC ------------------------------------------------------------------- */
+SH_PFC_PINS(lbsc_cs0, PIN_CS0);
+SH_PFC_MUX1(lbsc_cs0, CS0);
+SH_PFC_PINS(lbsc_cs1, PIN_CS1_A26);
+SH_PFC_MUX1(lbsc_cs1, CS1_A26);
+SH_PFC_PINS(lbsc_ex_cs0, RCAR_GP_PIN(1, 3));
+SH_PFC_MUX1(lbsc_ex_cs0, EX_CS0);
+SH_PFC_PINS(lbsc_ex_cs1, RCAR_GP_PIN(1, 4));
+SH_PFC_MUX1(lbsc_ex_cs1, EX_CS1);
+SH_PFC_PINS(lbsc_ex_cs2, RCAR_GP_PIN(1, 5));
+SH_PFC_MUX1(lbsc_ex_cs2, EX_CS2);
+SH_PFC_PINS(lbsc_ex_cs3, RCAR_GP_PIN(1, 6));
+SH_PFC_MUX1(lbsc_ex_cs3, EX_CS3);
+SH_PFC_PINS(lbsc_ex_cs4, RCAR_GP_PIN(1, 7));
+SH_PFC_MUX1(lbsc_ex_cs4, EX_CS4);
+SH_PFC_PINS(lbsc_ex_cs5, RCAR_GP_PIN(1, 8));
+SH_PFC_MUX1(lbsc_ex_cs5, EX_CS5);
+
/* - MMC macro -------------------------------------------------------------- */
#define MMC_PFC_PINS(name, args...) SH_PFC_PINS(name, args)
#define MMC_PFC_CTRL(name, clk, cmd) SH_PFC_MUX2(name, clk, cmd)
@@ -1724,6 +1742,14 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
SH_PFC_PIN_GROUP(i2c3_a),
SH_PFC_PIN_GROUP(i2c3_b),
SH_PFC_PIN_GROUP(i2c3_c),
+ SH_PFC_PIN_GROUP(lbsc_cs0),
+ SH_PFC_PIN_GROUP(lbsc_cs1),
+ SH_PFC_PIN_GROUP(lbsc_ex_cs0),
+ SH_PFC_PIN_GROUP(lbsc_ex_cs1),
+ SH_PFC_PIN_GROUP(lbsc_ex_cs2),
+ SH_PFC_PIN_GROUP(lbsc_ex_cs3),
+ SH_PFC_PIN_GROUP(lbsc_ex_cs4),
+ SH_PFC_PIN_GROUP(lbsc_ex_cs5),
SH_PFC_PIN_GROUP(mmc_ctrl),
BUS_DATA_PIN_GROUP(mmc_data, 1),
BUS_DATA_PIN_GROUP(mmc_data, 4),
@@ -1897,6 +1923,17 @@ static const char * const i2c3_groups[] = {
"i2c3_c",
};
+static const char * const lbsc_groups[] = {
+ "lbsc_cs0",
+ "lbsc_cs1",
+ "lbsc_ex_cs0",
+ "lbsc_ex_cs1",
+ "lbsc_ex_cs2",
+ "lbsc_ex_cs3",
+ "lbsc_ex_cs4",
+ "lbsc_ex_cs5",
+};
+
static const char * const mmc_groups[] = {
"mmc_ctrl",
"mmc_data1",
@@ -2049,6 +2086,7 @@ static const struct sh_pfc_function pinmux_functions[] = {
SH_PFC_FUNCTION(i2c1),
SH_PFC_FUNCTION(i2c2),
SH_PFC_FUNCTION(i2c3),
+ SH_PFC_FUNCTION(lbsc),
SH_PFC_FUNCTION(mmc),
SH_PFC_FUNCTION(scif_clk),
SH_PFC_FUNCTION(scif0),
diff --git a/drivers/pinctrl/renesas/pfc-r8a7779.c b/drivers/pinctrl/renesas/pfc-r8a7779.c
index 1172a35938..e1a8cb6691 100644
--- a/drivers/pinctrl/renesas/pfc-r8a7779.c
+++ b/drivers/pinctrl/renesas/pfc-r8a7779.c
@@ -1942,7 +1942,7 @@ static const unsigned int intc_irq3_b_pins[] = {
static const unsigned int intc_irq3_b_mux[] = {
IRQ3_B_MARK,
};
-/* - LSBC ------------------------------------------------------------------- */
+/* - LBSC ------------------------------------------------------------------- */
static const unsigned int lbsc_cs0_pins[] = {
/* CS */
RCAR_GP_PIN(0, 13),
diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/renesas/pinctrl-rzg2l.c
index 2ea6ef99cc..9de350ad7e 100644
--- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c
+++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c
@@ -55,14 +55,22 @@
#define PIN_CFG_FILONOFF BIT(10)
#define PIN_CFG_FILNUM BIT(11)
#define PIN_CFG_FILCLKSEL BIT(12)
+#define PIN_CFG_IOLH_C BIT(13)
+#define PIN_CFG_SOFT_PS BIT(14)
-#define RZG2L_MPXED_PIN_FUNCS (PIN_CFG_IOLH_A | \
- PIN_CFG_SR | \
+#define RZG2L_MPXED_COMMON_PIN_FUNCS(group) \
+ (PIN_CFG_IOLH_##group | \
PIN_CFG_PUPD | \
PIN_CFG_FILONOFF | \
PIN_CFG_FILNUM | \
PIN_CFG_FILCLKSEL)
+#define RZG2L_MPXED_PIN_FUNCS (RZG2L_MPXED_COMMON_PIN_FUNCS(A) | \
+ PIN_CFG_SR)
+
+#define RZG3S_MPXED_PIN_FUNCS(group) (RZG2L_MPXED_COMMON_PIN_FUNCS(group) | \
+ PIN_CFG_SOFT_PS)
+
#define RZG2L_MPXED_ETH_PIN_FUNCS(x) ((x) | \
PIN_CFG_FILONOFF | \
PIN_CFG_FILNUM | \
@@ -74,8 +82,6 @@
*/
#define RZG2L_GPIO_PORT_PACK(n, a, f) (((n) << 28) | ((a) << 20) | (f))
#define RZG2L_GPIO_PORT_GET_PINCNT(x) (((x) & GENMASK(30, 28)) >> 28)
-#define RZG2L_GPIO_PORT_GET_INDEX(x) (((x) & GENMASK(26, 20)) >> 20)
-#define RZG2L_GPIO_PORT_GET_CFGS(x) ((x) & GENMASK(19, 0))
/*
* BIT(31) indicates dedicated pin, p is the register index while
@@ -85,20 +91,22 @@
#define RZG2L_SINGLE_PIN BIT(31)
#define RZG2L_SINGLE_PIN_PACK(p, b, f) (RZG2L_SINGLE_PIN | \
((p) << 24) | ((b) << 20) | (f))
-#define RZG2L_SINGLE_PIN_GET_PORT_OFFSET(x) (((x) & GENMASK(30, 24)) >> 24)
#define RZG2L_SINGLE_PIN_GET_BIT(x) (((x) & GENMASK(22, 20)) >> 20)
-#define RZG2L_SINGLE_PIN_GET_CFGS(x) ((x) & GENMASK(19, 0))
-
-#define P(n) (0x0000 + 0x10 + (n))
-#define PM(n) (0x0100 + 0x20 + (n) * 2)
-#define PMC(n) (0x0200 + 0x10 + (n))
-#define PFC(n) (0x0400 + 0x40 + (n) * 4)
-#define PIN(n) (0x0800 + 0x10 + (n))
-#define IOLH(n) (0x1000 + (n) * 8)
-#define IEN(n) (0x1800 + (n) * 8)
-#define ISEL(n) (0x2c80 + (n) * 8)
-#define PWPR (0x3014)
-#define SD_CH(n) (0x3000 + (n) * 4)
+
+#define RZG2L_PIN_CFG_TO_CAPS(cfg) ((cfg) & GENMASK(19, 0))
+#define RZG2L_PIN_CFG_TO_PORT_OFFSET(cfg) ((cfg) & RZG2L_SINGLE_PIN ? \
+ (((cfg) & GENMASK(30, 24)) >> 24) : \
+ (((cfg) & GENMASK(26, 20)) >> 20))
+
+#define P(off) (0x0000 + (off))
+#define PM(off) (0x0100 + (off) * 2)
+#define PMC(off) (0x0200 + (off))
+#define PFC(off) (0x0400 + (off) * 4)
+#define PIN(off) (0x0800 + (off))
+#define IOLH(off) (0x1000 + (off) * 8)
+#define IEN(off) (0x1800 + (off) * 8)
+#define ISEL(off) (0x2C00 + (off) * 8)
+#define SD_CH(off, ch) ((off) + (ch) * 4)
#define QSPI (0x3008)
#define PVDD_1800 1 /* I/O domain voltage <= 1.8V */
@@ -117,13 +125,59 @@
#define PM_OUTPUT 0x2
#define RZG2L_PIN_ID_TO_PORT(id) ((id) / RZG2L_PINS_PER_PORT)
-#define RZG2L_PIN_ID_TO_PORT_OFFSET(id) (RZG2L_PIN_ID_TO_PORT(id) + 0x10)
#define RZG2L_PIN_ID_TO_PIN(id) ((id) % RZG2L_PINS_PER_PORT)
#define RZG2L_TINT_MAX_INTERRUPT 32
#define RZG2L_TINT_IRQ_START_INDEX 9
#define RZG2L_PACK_HWIRQ(t, i) (((t) << 16) | (i))
+/**
+ * struct rzg2l_register_offsets - specific register offsets
+ * @pwpr: PWPR register offset
+ * @sd_ch: SD_CH register offset
+ */
+struct rzg2l_register_offsets {
+ u16 pwpr;
+ u16 sd_ch;
+};
+
+/**
+ * enum rzg2l_iolh_index - starting indices in IOLH specific arrays
+ * @RZG2L_IOLH_IDX_1V8: starting index for 1V8 power source
+ * @RZG2L_IOLH_IDX_2V5: starting index for 2V5 power source
+ * @RZG2L_IOLH_IDX_3V3: starting index for 3V3 power source
+ * @RZG2L_IOLH_IDX_MAX: maximum index
+ */
+enum rzg2l_iolh_index {
+ RZG2L_IOLH_IDX_1V8 = 0,
+ RZG2L_IOLH_IDX_2V5 = 4,
+ RZG2L_IOLH_IDX_3V3 = 8,
+ RZG2L_IOLH_IDX_MAX = 12,
+};
+
+/* Maximum number of driver strength entries per power source. */
+#define RZG2L_IOLH_MAX_DS_ENTRIES (4)
+
+/**
+ * struct rzg2l_hwcfg - hardware configuration data structure
+ * @regs: hardware specific register offsets
+ * @iolh_groupa_ua: IOLH group A uA specific values
+ * @iolh_groupb_ua: IOLH group B uA specific values
+ * @iolh_groupc_ua: IOLH group C uA specific values
+ * @iolh_groupb_oi: IOLH group B output impedance specific values
+ * @drive_strength_ua: drive strength in uA is supported (otherwise mA is supported)
+ * @func_base: base number for port function (see register PFC)
+ */
+struct rzg2l_hwcfg {
+ const struct rzg2l_register_offsets regs;
+ u16 iolh_groupa_ua[RZG2L_IOLH_IDX_MAX];
+ u16 iolh_groupb_ua[RZG2L_IOLH_IDX_MAX];
+ u16 iolh_groupc_ua[RZG2L_IOLH_IDX_MAX];
+ u16 iolh_groupb_oi[4];
+ bool drive_strength_ua;
+ u8 func_base;
+};
+
struct rzg2l_dedicated_configs {
const char *name;
u32 config;
@@ -133,9 +187,20 @@ struct rzg2l_pinctrl_data {
const char * const *port_pins;
const u32 *port_pin_configs;
unsigned int n_ports;
- struct rzg2l_dedicated_configs *dedicated_pins;
+ const struct rzg2l_dedicated_configs *dedicated_pins;
unsigned int n_port_pins;
unsigned int n_dedicated_pins;
+ const struct rzg2l_hwcfg *hwcfg;
+};
+
+/**
+ * struct rzg2l_pinctrl_pin_settings - pin data
+ * @power_source: power source
+ * @drive_strength_ua: drive strength (in micro amps)
+ */
+struct rzg2l_pinctrl_pin_settings {
+ u16 power_source;
+ u16 drive_strength_ua;
};
struct rzg2l_pinctrl {
@@ -155,44 +220,46 @@ struct rzg2l_pinctrl {
spinlock_t lock; /* lock read/write registers */
struct mutex mutex; /* serialize adding groups and functions */
+
+ struct rzg2l_pinctrl_pin_settings *settings;
};
-static const unsigned int iolh_groupa_mA[] = { 2, 4, 8, 12 };
-static const unsigned int iolh_groupb_oi[] = { 100, 66, 50, 33 };
+static const u16 available_ps[] = { 1800, 2500, 3300 };
static void rzg2l_pinctrl_set_pfc_mode(struct rzg2l_pinctrl *pctrl,
- u8 port, u8 pin, u8 func)
+ u8 pin, u8 off, u8 func)
{
+ const struct rzg2l_register_offsets *regs = &pctrl->data->hwcfg->regs;
unsigned long flags;
u32 reg;
spin_lock_irqsave(&pctrl->lock, flags);
/* Set pin to 'Non-use (Hi-Z input protection)' */
- reg = readw(pctrl->base + PM(port));
+ reg = readw(pctrl->base + PM(off));
reg &= ~(PM_MASK << (pin * 2));
- writew(reg, pctrl->base + PM(port));
+ writew(reg, pctrl->base + PM(off));
/* Temporarily switch to GPIO mode with PMC register */
- reg = readb(pctrl->base + PMC(port));
- writeb(reg & ~BIT(pin), pctrl->base + PMC(port));
+ reg = readb(pctrl->base + PMC(off));
+ writeb(reg & ~BIT(pin), pctrl->base + PMC(off));
/* Set the PWPR register to allow PFC register to write */
- writel(0x0, pctrl->base + PWPR); /* B0WI=0, PFCWE=0 */
- writel(PWPR_PFCWE, pctrl->base + PWPR); /* B0WI=0, PFCWE=1 */
+ writel(0x0, pctrl->base + regs->pwpr); /* B0WI=0, PFCWE=0 */
+ writel(PWPR_PFCWE, pctrl->base + regs->pwpr); /* B0WI=0, PFCWE=1 */
/* Select Pin function mode with PFC register */
- reg = readl(pctrl->base + PFC(port));
+ reg = readl(pctrl->base + PFC(off));
reg &= ~(PFC_MASK << (pin * 4));
- writel(reg | (func << (pin * 4)), pctrl->base + PFC(port));
+ writel(reg | (func << (pin * 4)), pctrl->base + PFC(off));
/* Set the PWPR register to be write-protected */
- writel(0x0, pctrl->base + PWPR); /* B0WI=0, PFCWE=0 */
- writel(PWPR_B0WI, pctrl->base + PWPR); /* B0WI=1, PFCWE=0 */
+ writel(0x0, pctrl->base + regs->pwpr); /* B0WI=0, PFCWE=0 */
+ writel(PWPR_B0WI, pctrl->base + regs->pwpr); /* B0WI=1, PFCWE=0 */
/* Switch to Peripheral pin function with PMC register */
- reg = readb(pctrl->base + PMC(port));
- writeb(reg | BIT(pin), pctrl->base + PMC(port));
+ reg = readb(pctrl->base + PMC(off));
+ writeb(reg | BIT(pin), pctrl->base + PMC(off));
spin_unlock_irqrestore(&pctrl->lock, flags);
};
@@ -202,6 +269,7 @@ static int rzg2l_pinctrl_set_mux(struct pinctrl_dev *pctldev,
unsigned int group_selector)
{
struct rzg2l_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
+ const struct rzg2l_hwcfg *hwcfg = pctrl->data->hwcfg;
struct function_desc *func;
unsigned int i, *psel_val;
struct group_desc *group;
@@ -218,11 +286,14 @@ static int rzg2l_pinctrl_set_mux(struct pinctrl_dev *pctldev,
pins = group->pins;
for (i = 0; i < group->num_pins; i++) {
- dev_dbg(pctrl->dev, "port:%u pin: %u PSEL:%u\n",
- RZG2L_PIN_ID_TO_PORT(pins[i]), RZG2L_PIN_ID_TO_PIN(pins[i]),
- psel_val[i]);
- rzg2l_pinctrl_set_pfc_mode(pctrl, RZG2L_PIN_ID_TO_PORT(pins[i]),
- RZG2L_PIN_ID_TO_PIN(pins[i]), psel_val[i]);
+ unsigned int *pin_data = pctrl->desc.pins[pins[i]].drv_data;
+ u32 off = RZG2L_PIN_CFG_TO_PORT_OFFSET(*pin_data);
+ u32 pin = RZG2L_PIN_ID_TO_PIN(pins[i]);
+
+ dev_dbg(pctrl->dev, "port:%u pin: %u off:%x PSEL:%u\n",
+ RZG2L_PIN_ID_TO_PORT(pins[i]), pin, off, psel_val[i] - hwcfg->func_base);
+
+ rzg2l_pinctrl_set_pfc_mode(pctrl, pin, off, psel_val[i] - hwcfg->func_base);
}
return 0;
@@ -468,14 +539,14 @@ static int rzg2l_validate_gpio_pin(struct rzg2l_pinctrl *pctrl,
u32 cfg, u32 port, u8 bit)
{
u8 pincount = RZG2L_GPIO_PORT_GET_PINCNT(cfg);
- u32 port_index = RZG2L_GPIO_PORT_GET_INDEX(cfg);
+ u32 off = RZG2L_PIN_CFG_TO_PORT_OFFSET(cfg);
u32 data;
if (bit >= pincount || port >= pctrl->data->n_port_pins)
return -EINVAL;
data = pctrl->data->port_pin_configs[port];
- if (port_index != RZG2L_GPIO_PORT_GET_INDEX(data))
+ if (off != RZG2L_PIN_CFG_TO_PORT_OFFSET(data))
return -EINVAL;
return 0;
@@ -514,31 +585,178 @@ static void rzg2l_rmw_pin_config(struct rzg2l_pinctrl *pctrl, u32 offset,
spin_unlock_irqrestore(&pctrl->lock, flags);
}
+static int rzg2l_caps_to_pwr_reg(const struct rzg2l_register_offsets *regs, u32 caps)
+{
+ if (caps & PIN_CFG_IO_VMC_SD0)
+ return SD_CH(regs->sd_ch, 0);
+ if (caps & PIN_CFG_IO_VMC_SD1)
+ return SD_CH(regs->sd_ch, 1);
+ if (caps & PIN_CFG_IO_VMC_QSPI)
+ return QSPI;
+
+ return -EINVAL;
+}
+
+static int rzg2l_get_power_source(struct rzg2l_pinctrl *pctrl, u32 pin, u32 caps)
+{
+ const struct rzg2l_hwcfg *hwcfg = pctrl->data->hwcfg;
+ const struct rzg2l_register_offsets *regs = &hwcfg->regs;
+ int pwr_reg;
+
+ if (caps & PIN_CFG_SOFT_PS)
+ return pctrl->settings[pin].power_source;
+
+ pwr_reg = rzg2l_caps_to_pwr_reg(regs, caps);
+ if (pwr_reg < 0)
+ return pwr_reg;
+
+ return (readl(pctrl->base + pwr_reg) & PVDD_MASK) ? 1800 : 3300;
+}
+
+static int rzg2l_set_power_source(struct rzg2l_pinctrl *pctrl, u32 pin, u32 caps, u32 ps)
+{
+ const struct rzg2l_hwcfg *hwcfg = pctrl->data->hwcfg;
+ const struct rzg2l_register_offsets *regs = &hwcfg->regs;
+ int pwr_reg;
+
+ if (caps & PIN_CFG_SOFT_PS) {
+ pctrl->settings[pin].power_source = ps;
+ return 0;
+ }
+
+ pwr_reg = rzg2l_caps_to_pwr_reg(regs, caps);
+ if (pwr_reg < 0)
+ return pwr_reg;
+
+ writel((ps == 1800) ? PVDD_1800 : PVDD_3300, pctrl->base + pwr_reg);
+ pctrl->settings[pin].power_source = ps;
+
+ return 0;
+}
+
+static bool rzg2l_ps_is_supported(u16 ps)
+{
+ unsigned int i;
+
+ for (i = 0; i < ARRAY_SIZE(available_ps); i++) {
+ if (available_ps[i] == ps)
+ return true;
+ }
+
+ return false;
+}
+
+static enum rzg2l_iolh_index rzg2l_ps_to_iolh_idx(u16 ps)
+{
+ unsigned int i;
+
+ for (i = 0; i < ARRAY_SIZE(available_ps); i++) {
+ if (available_ps[i] == ps)
+ break;
+ }
+
+ /*
+ * We multiply with RZG2L_IOLH_MAX_DS_ENTRIES as we have
+ * RZG2L_IOLH_MAX_DS_ENTRIES DS values per power source
+ */
+ return i * RZG2L_IOLH_MAX_DS_ENTRIES;
+}
+
+static u16 rzg2l_iolh_val_to_ua(const struct rzg2l_hwcfg *hwcfg, u32 caps, u8 val)
+{
+ if (caps & PIN_CFG_IOLH_A)
+ return hwcfg->iolh_groupa_ua[val];
+
+ if (caps & PIN_CFG_IOLH_B)
+ return hwcfg->iolh_groupb_ua[val];
+
+ if (caps & PIN_CFG_IOLH_C)
+ return hwcfg->iolh_groupc_ua[val];
+
+ /* Should not happen. */
+ return 0;
+}
+
+static int rzg2l_iolh_ua_to_val(const struct rzg2l_hwcfg *hwcfg, u32 caps,
+ enum rzg2l_iolh_index ps_index, u16 ua)
+{
+ const u16 *array = NULL;
+ unsigned int i;
+
+ if (caps & PIN_CFG_IOLH_A)
+ array = &hwcfg->iolh_groupa_ua[ps_index];
+
+ if (caps & PIN_CFG_IOLH_B)
+ array = &hwcfg->iolh_groupb_ua[ps_index];
+
+ if (caps & PIN_CFG_IOLH_C)
+ array = &hwcfg->iolh_groupc_ua[ps_index];
+
+ if (!array)
+ return -EINVAL;
+
+ for (i = 0; i < RZG2L_IOLH_MAX_DS_ENTRIES; i++) {
+ if (array[i] == ua)
+ return i;
+ }
+
+ return -EINVAL;
+}
+
+static bool rzg2l_ds_is_supported(struct rzg2l_pinctrl *pctrl, u32 caps,
+ enum rzg2l_iolh_index iolh_idx,
+ u16 ds)
+{
+ const struct rzg2l_hwcfg *hwcfg = pctrl->data->hwcfg;
+ const u16 *array = NULL;
+ unsigned int i;
+
+ if (caps & PIN_CFG_IOLH_A)
+ array = hwcfg->iolh_groupa_ua;
+
+ if (caps & PIN_CFG_IOLH_B)
+ array = hwcfg->iolh_groupb_ua;
+
+ if (caps & PIN_CFG_IOLH_C)
+ array = hwcfg->iolh_groupc_ua;
+
+ /* Should not happen. */
+ if (!array)
+ return false;
+
+ if (!array[iolh_idx])
+ return false;
+
+ for (i = 0; i < RZG2L_IOLH_MAX_DS_ENTRIES; i++) {
+ if (array[iolh_idx + i] == ds)
+ return true;
+ }
+
+ return false;
+}
+
static int rzg2l_pinctrl_pinconf_get(struct pinctrl_dev *pctldev,
unsigned int _pin,
unsigned long *config)
{
struct rzg2l_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
enum pin_config_param param = pinconf_to_config_param(*config);
+ const struct rzg2l_hwcfg *hwcfg = pctrl->data->hwcfg;
const struct pinctrl_pin_desc *pin = &pctrl->desc.pins[_pin];
unsigned int *pin_data = pin->drv_data;
unsigned int arg = 0;
- unsigned long flags;
- void __iomem *addr;
- u32 port_offset;
- u32 cfg = 0;
- u8 bit = 0;
+ u32 off, cfg;
+ int ret;
+ u8 bit;
if (!pin_data)
return -EINVAL;
+ off = RZG2L_PIN_CFG_TO_PORT_OFFSET(*pin_data);
+ cfg = RZG2L_PIN_CFG_TO_CAPS(*pin_data);
if (*pin_data & RZG2L_SINGLE_PIN) {
- port_offset = RZG2L_SINGLE_PIN_GET_PORT_OFFSET(*pin_data);
- cfg = RZG2L_SINGLE_PIN_GET_CFGS(*pin_data);
bit = RZG2L_SINGLE_PIN_GET_BIT(*pin_data);
} else {
- cfg = RZG2L_GPIO_PORT_GET_CFGS(*pin_data);
- port_offset = RZG2L_PIN_ID_TO_PORT_OFFSET(_pin);
bit = RZG2L_PIN_ID_TO_PIN(_pin);
if (rzg2l_validate_gpio_pin(pctrl, *pin_data, RZG2L_PIN_ID_TO_PORT(_pin), bit))
@@ -549,49 +767,58 @@ static int rzg2l_pinctrl_pinconf_get(struct pinctrl_dev *pctldev,
case PIN_CONFIG_INPUT_ENABLE:
if (!(cfg & PIN_CFG_IEN))
return -EINVAL;
- arg = rzg2l_read_pin_config(pctrl, IEN(port_offset), bit, IEN_MASK);
+ arg = rzg2l_read_pin_config(pctrl, IEN(off), bit, IEN_MASK);
if (!arg)
return -EINVAL;
break;
- case PIN_CONFIG_POWER_SOURCE: {
- u32 pwr_reg = 0x0;
+ case PIN_CONFIG_POWER_SOURCE:
+ ret = rzg2l_get_power_source(pctrl, _pin, cfg);
+ if (ret < 0)
+ return ret;
+ arg = ret;
+ break;
+
+ case PIN_CONFIG_DRIVE_STRENGTH: {
+ unsigned int index;
- if (cfg & PIN_CFG_IO_VMC_SD0)
- pwr_reg = SD_CH(0);
- else if (cfg & PIN_CFG_IO_VMC_SD1)
- pwr_reg = SD_CH(1);
- else if (cfg & PIN_CFG_IO_VMC_QSPI)
- pwr_reg = QSPI;
- else
+ if (!(cfg & PIN_CFG_IOLH_A) || hwcfg->drive_strength_ua)
return -EINVAL;
- spin_lock_irqsave(&pctrl->lock, flags);
- addr = pctrl->base + pwr_reg;
- arg = (readl(addr) & PVDD_MASK) ? 1800 : 3300;
- spin_unlock_irqrestore(&pctrl->lock, flags);
+ index = rzg2l_read_pin_config(pctrl, IOLH(off), bit, IOLH_MASK);
+ /*
+ * Drive strenght mA is supported only by group A and only
+ * for 3V3 port source.
+ */
+ arg = hwcfg->iolh_groupa_ua[index + RZG2L_IOLH_IDX_3V3] / 1000;
break;
}
- case PIN_CONFIG_DRIVE_STRENGTH: {
- unsigned int index;
+ case PIN_CONFIG_DRIVE_STRENGTH_UA: {
+ enum rzg2l_iolh_index iolh_idx;
+ u8 val;
- if (!(cfg & PIN_CFG_IOLH_A))
+ if (!(cfg & (PIN_CFG_IOLH_A | PIN_CFG_IOLH_B | PIN_CFG_IOLH_C)) ||
+ !hwcfg->drive_strength_ua)
return -EINVAL;
- index = rzg2l_read_pin_config(pctrl, IOLH(port_offset), bit, IOLH_MASK);
- arg = iolh_groupa_mA[index];
+ ret = rzg2l_get_power_source(pctrl, _pin, cfg);
+ if (ret < 0)
+ return ret;
+ iolh_idx = rzg2l_ps_to_iolh_idx(ret);
+ val = rzg2l_read_pin_config(pctrl, IOLH(off), bit, IOLH_MASK);
+ arg = rzg2l_iolh_val_to_ua(hwcfg, cfg, iolh_idx + val);
break;
}
case PIN_CONFIG_OUTPUT_IMPEDANCE_OHMS: {
unsigned int index;
- if (!(cfg & PIN_CFG_IOLH_B))
+ if (!(cfg & PIN_CFG_IOLH_B) || !hwcfg->iolh_groupb_oi[0])
return -EINVAL;
- index = rzg2l_read_pin_config(pctrl, IOLH(port_offset), bit, IOLH_MASK);
- arg = iolh_groupb_oi[index];
+ index = rzg2l_read_pin_config(pctrl, IOLH(off), bit, IOLH_MASK);
+ arg = hwcfg->iolh_groupb_oi[index];
break;
}
@@ -611,25 +838,23 @@ static int rzg2l_pinctrl_pinconf_set(struct pinctrl_dev *pctldev,
{
struct rzg2l_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
const struct pinctrl_pin_desc *pin = &pctrl->desc.pins[_pin];
+ const struct rzg2l_hwcfg *hwcfg = pctrl->data->hwcfg;
+ struct rzg2l_pinctrl_pin_settings settings = pctrl->settings[_pin];
unsigned int *pin_data = pin->drv_data;
enum pin_config_param param;
- unsigned long flags;
- void __iomem *addr;
- u32 port_offset;
unsigned int i;
- u32 cfg = 0;
- u8 bit = 0;
+ u32 cfg, off;
+ int ret;
+ u8 bit;
if (!pin_data)
return -EINVAL;
+ off = RZG2L_PIN_CFG_TO_PORT_OFFSET(*pin_data);
+ cfg = RZG2L_PIN_CFG_TO_CAPS(*pin_data);
if (*pin_data & RZG2L_SINGLE_PIN) {
- port_offset = RZG2L_SINGLE_PIN_GET_PORT_OFFSET(*pin_data);
- cfg = RZG2L_SINGLE_PIN_GET_CFGS(*pin_data);
bit = RZG2L_SINGLE_PIN_GET_BIT(*pin_data);
} else {
- cfg = RZG2L_GPIO_PORT_GET_CFGS(*pin_data);
- port_offset = RZG2L_PIN_ID_TO_PORT_OFFSET(_pin);
bit = RZG2L_PIN_ID_TO_PIN(_pin);
if (rzg2l_validate_gpio_pin(pctrl, *pin_data, RZG2L_PIN_ID_TO_PORT(_pin), bit))
@@ -646,66 +871,56 @@ static int rzg2l_pinctrl_pinconf_set(struct pinctrl_dev *pctldev,
if (!(cfg & PIN_CFG_IEN))
return -EINVAL;
- rzg2l_rmw_pin_config(pctrl, IEN(port_offset), bit, IEN_MASK, !!arg);
+ rzg2l_rmw_pin_config(pctrl, IEN(off), bit, IEN_MASK, !!arg);
break;
}
- case PIN_CONFIG_POWER_SOURCE: {
- unsigned int mV = pinconf_to_config_argument(_configs[i]);
- u32 pwr_reg = 0x0;
-
- if (mV != 1800 && mV != 3300)
- return -EINVAL;
-
- if (cfg & PIN_CFG_IO_VMC_SD0)
- pwr_reg = SD_CH(0);
- else if (cfg & PIN_CFG_IO_VMC_SD1)
- pwr_reg = SD_CH(1);
- else if (cfg & PIN_CFG_IO_VMC_QSPI)
- pwr_reg = QSPI;
- else
- return -EINVAL;
-
- addr = pctrl->base + pwr_reg;
- spin_lock_irqsave(&pctrl->lock, flags);
- writel((mV == 1800) ? PVDD_1800 : PVDD_3300, addr);
- spin_unlock_irqrestore(&pctrl->lock, flags);
+ case PIN_CONFIG_POWER_SOURCE:
+ settings.power_source = pinconf_to_config_argument(_configs[i]);
break;
- }
case PIN_CONFIG_DRIVE_STRENGTH: {
unsigned int arg = pinconf_to_config_argument(_configs[i]);
unsigned int index;
- if (!(cfg & PIN_CFG_IOLH_A))
+ if (!(cfg & PIN_CFG_IOLH_A) || hwcfg->drive_strength_ua)
return -EINVAL;
- for (index = 0; index < ARRAY_SIZE(iolh_groupa_mA); index++) {
- if (arg == iolh_groupa_mA[index])
+ for (index = RZG2L_IOLH_IDX_3V3;
+ index < RZG2L_IOLH_IDX_3V3 + RZG2L_IOLH_MAX_DS_ENTRIES; index++) {
+ if (arg == (hwcfg->iolh_groupa_ua[index] / 1000))
break;
}
- if (index >= ARRAY_SIZE(iolh_groupa_mA))
+ if (index == (RZG2L_IOLH_IDX_3V3 + RZG2L_IOLH_MAX_DS_ENTRIES))
return -EINVAL;
- rzg2l_rmw_pin_config(pctrl, IOLH(port_offset), bit, IOLH_MASK, index);
+ rzg2l_rmw_pin_config(pctrl, IOLH(off), bit, IOLH_MASK, index);
break;
}
+ case PIN_CONFIG_DRIVE_STRENGTH_UA:
+ if (!(cfg & (PIN_CFG_IOLH_A | PIN_CFG_IOLH_B | PIN_CFG_IOLH_C)) ||
+ !hwcfg->drive_strength_ua)
+ return -EINVAL;
+
+ settings.drive_strength_ua = pinconf_to_config_argument(_configs[i]);
+ break;
+
case PIN_CONFIG_OUTPUT_IMPEDANCE_OHMS: {
unsigned int arg = pinconf_to_config_argument(_configs[i]);
unsigned int index;
- if (!(cfg & PIN_CFG_IOLH_B))
+ if (!(cfg & PIN_CFG_IOLH_B) || !hwcfg->iolh_groupb_oi[0])
return -EINVAL;
- for (index = 0; index < ARRAY_SIZE(iolh_groupb_oi); index++) {
- if (arg == iolh_groupb_oi[index])
+ for (index = 0; index < ARRAY_SIZE(hwcfg->iolh_groupb_oi); index++) {
+ if (arg == hwcfg->iolh_groupb_oi[index])
break;
}
- if (index >= ARRAY_SIZE(iolh_groupb_oi))
+ if (index == ARRAY_SIZE(hwcfg->iolh_groupb_oi))
return -EINVAL;
- rzg2l_rmw_pin_config(pctrl, IOLH(port_offset), bit, IOLH_MASK, index);
+ rzg2l_rmw_pin_config(pctrl, IOLH(off), bit, IOLH_MASK, index);
break;
}
@@ -714,6 +929,39 @@ static int rzg2l_pinctrl_pinconf_set(struct pinctrl_dev *pctldev,
}
}
+ /* Apply power source. */
+ if (settings.power_source != pctrl->settings[_pin].power_source) {
+ ret = rzg2l_ps_is_supported(settings.power_source);
+ if (!ret)
+ return -EINVAL;
+
+ /* Apply power source. */
+ ret = rzg2l_set_power_source(pctrl, _pin, cfg, settings.power_source);
+ if (ret)
+ return ret;
+ }
+
+ /* Apply drive strength. */
+ if (settings.drive_strength_ua != pctrl->settings[_pin].drive_strength_ua) {
+ enum rzg2l_iolh_index iolh_idx;
+ int val;
+
+ iolh_idx = rzg2l_ps_to_iolh_idx(settings.power_source);
+ ret = rzg2l_ds_is_supported(pctrl, cfg, iolh_idx,
+ settings.drive_strength_ua);
+ if (!ret)
+ return -EINVAL;
+
+ /* Get register value for this PS/DS tuple. */
+ val = rzg2l_iolh_ua_to_val(hwcfg, cfg, iolh_idx, settings.drive_strength_ua);
+ if (val < 0)
+ return val;
+
+ /* Apply drive strength. */
+ rzg2l_rmw_pin_config(pctrl, IOLH(off), bit, IOLH_MASK, val);
+ pctrl->settings[_pin].drive_strength_ua = settings.drive_strength_ua;
+ }
+
return 0;
}
@@ -795,41 +1043,52 @@ static const struct pinconf_ops rzg2l_pinctrl_confops = {
static int rzg2l_gpio_request(struct gpio_chip *chip, unsigned int offset)
{
struct rzg2l_pinctrl *pctrl = gpiochip_get_data(chip);
+ const struct pinctrl_pin_desc *pin_desc = &pctrl->desc.pins[offset];
+ u32 *pin_data = pin_desc->drv_data;
+ u32 off = RZG2L_PIN_CFG_TO_PORT_OFFSET(*pin_data);
u32 port = RZG2L_PIN_ID_TO_PORT(offset);
u8 bit = RZG2L_PIN_ID_TO_PIN(offset);
unsigned long flags;
u8 reg8;
int ret;
- ret = pinctrl_gpio_request(chip->base + offset);
+ ret = rzg2l_validate_gpio_pin(pctrl, *pin_data, port, bit);
+ if (ret)
+ return ret;
+
+ ret = pinctrl_gpio_request(chip, offset);
if (ret)
return ret;
spin_lock_irqsave(&pctrl->lock, flags);
/* Select GPIO mode in PMC Register */
- reg8 = readb(pctrl->base + PMC(port));
+ reg8 = readb(pctrl->base + PMC(off));
reg8 &= ~BIT(bit);
- writeb(reg8, pctrl->base + PMC(port));
+ writeb(reg8, pctrl->base + PMC(off));
spin_unlock_irqrestore(&pctrl->lock, flags);
return 0;
}
-static void rzg2l_gpio_set_direction(struct rzg2l_pinctrl *pctrl, u32 port,
- u8 bit, bool output)
+static void rzg2l_gpio_set_direction(struct rzg2l_pinctrl *pctrl, u32 offset,
+ bool output)
{
+ const struct pinctrl_pin_desc *pin_desc = &pctrl->desc.pins[offset];
+ unsigned int *pin_data = pin_desc->drv_data;
+ u32 off = RZG2L_PIN_CFG_TO_PORT_OFFSET(*pin_data);
+ u8 bit = RZG2L_PIN_ID_TO_PIN(offset);
unsigned long flags;
u16 reg16;
spin_lock_irqsave(&pctrl->lock, flags);
- reg16 = readw(pctrl->base + PM(port));
+ reg16 = readw(pctrl->base + PM(off));
reg16 &= ~(PM_MASK << (bit * 2));
reg16 |= (output ? PM_OUTPUT : PM_INPUT) << (bit * 2);
- writew(reg16, pctrl->base + PM(port));
+ writew(reg16, pctrl->base + PM(off));
spin_unlock_irqrestore(&pctrl->lock, flags);
}
@@ -837,13 +1096,15 @@ static void rzg2l_gpio_set_direction(struct rzg2l_pinctrl *pctrl, u32 port,
static int rzg2l_gpio_get_direction(struct gpio_chip *chip, unsigned int offset)
{
struct rzg2l_pinctrl *pctrl = gpiochip_get_data(chip);
- u32 port = RZG2L_PIN_ID_TO_PORT(offset);
+ const struct pinctrl_pin_desc *pin_desc = &pctrl->desc.pins[offset];
+ unsigned int *pin_data = pin_desc->drv_data;
+ u32 off = RZG2L_PIN_CFG_TO_PORT_OFFSET(*pin_data);
u8 bit = RZG2L_PIN_ID_TO_PIN(offset);
- if (!(readb(pctrl->base + PMC(port)) & BIT(bit))) {
+ if (!(readb(pctrl->base + PMC(off)) & BIT(bit))) {
u16 reg16;
- reg16 = readw(pctrl->base + PM(port));
+ reg16 = readw(pctrl->base + PM(off));
reg16 = (reg16 >> (bit * 2)) & PM_MASK;
if (reg16 == PM_OUTPUT)
return GPIO_LINE_DIRECTION_OUT;
@@ -856,10 +1117,8 @@ static int rzg2l_gpio_direction_input(struct gpio_chip *chip,
unsigned int offset)
{
struct rzg2l_pinctrl *pctrl = gpiochip_get_data(chip);
- u32 port = RZG2L_PIN_ID_TO_PORT(offset);
- u8 bit = RZG2L_PIN_ID_TO_PIN(offset);
- rzg2l_gpio_set_direction(pctrl, port, bit, false);
+ rzg2l_gpio_set_direction(pctrl, offset, false);
return 0;
}
@@ -868,19 +1127,21 @@ static void rzg2l_gpio_set(struct gpio_chip *chip, unsigned int offset,
int value)
{
struct rzg2l_pinctrl *pctrl = gpiochip_get_data(chip);
- u32 port = RZG2L_PIN_ID_TO_PORT(offset);
+ const struct pinctrl_pin_desc *pin_desc = &pctrl->desc.pins[offset];
+ unsigned int *pin_data = pin_desc->drv_data;
+ u32 off = RZG2L_PIN_CFG_TO_PORT_OFFSET(*pin_data);
u8 bit = RZG2L_PIN_ID_TO_PIN(offset);
unsigned long flags;
u8 reg8;
spin_lock_irqsave(&pctrl->lock, flags);
- reg8 = readb(pctrl->base + P(port));
+ reg8 = readb(pctrl->base + P(off));
if (value)
- writeb(reg8 | BIT(bit), pctrl->base + P(port));
+ writeb(reg8 | BIT(bit), pctrl->base + P(off));
else
- writeb(reg8 & ~BIT(bit), pctrl->base + P(port));
+ writeb(reg8 & ~BIT(bit), pctrl->base + P(off));
spin_unlock_irqrestore(&pctrl->lock, flags);
}
@@ -889,11 +1150,9 @@ static int rzg2l_gpio_direction_output(struct gpio_chip *chip,
unsigned int offset, int value)
{
struct rzg2l_pinctrl *pctrl = gpiochip_get_data(chip);
- u32 port = RZG2L_PIN_ID_TO_PORT(offset);
- u8 bit = RZG2L_PIN_ID_TO_PIN(offset);
rzg2l_gpio_set(chip, offset, value);
- rzg2l_gpio_set_direction(pctrl, port, bit, true);
+ rzg2l_gpio_set_direction(pctrl, offset, true);
return 0;
}
@@ -901,17 +1160,19 @@ static int rzg2l_gpio_direction_output(struct gpio_chip *chip,
static int rzg2l_gpio_get(struct gpio_chip *chip, unsigned int offset)
{
struct rzg2l_pinctrl *pctrl = gpiochip_get_data(chip);
- u32 port = RZG2L_PIN_ID_TO_PORT(offset);
+ const struct pinctrl_pin_desc *pin_desc = &pctrl->desc.pins[offset];
+ unsigned int *pin_data = pin_desc->drv_data;
+ u32 off = RZG2L_PIN_CFG_TO_PORT_OFFSET(*pin_data);
u8 bit = RZG2L_PIN_ID_TO_PIN(offset);
u16 reg16;
- reg16 = readw(pctrl->base + PM(port));
+ reg16 = readw(pctrl->base + PM(off));
reg16 = (reg16 >> (bit * 2)) & PM_MASK;
if (reg16 == PM_INPUT)
- return !!(readb(pctrl->base + PIN(port)) & BIT(bit));
+ return !!(readb(pctrl->base + PIN(off)) & BIT(bit));
else if (reg16 == PM_OUTPUT)
- return !!(readb(pctrl->base + P(port)) & BIT(bit));
+ return !!(readb(pctrl->base + P(off)) & BIT(bit));
else
return -EINVAL;
}
@@ -920,7 +1181,7 @@ static void rzg2l_gpio_free(struct gpio_chip *chip, unsigned int offset)
{
unsigned int virq;
- pinctrl_gpio_free(chip->base + offset);
+ pinctrl_gpio_free(chip, offset);
virq = irq_find_mapping(chip->irq.domain, offset);
if (virq)
@@ -985,7 +1246,7 @@ static const char * const rzg2l_gpio_names[] = {
"P48_0", "P48_1", "P48_2", "P48_3", "P48_4", "P48_5", "P48_6", "P48_7",
};
-static const u32 rzg2l_gpio_configs[] = {
+static const u32 r9a07g044_gpio_configs[] = {
RZG2L_GPIO_PORT_PACK(2, 0x10, RZG2L_MPXED_PIN_FUNCS),
RZG2L_GPIO_PORT_PACK(2, 0x11, RZG2L_MPXED_PIN_FUNCS),
RZG2L_GPIO_PORT_PACK(2, 0x12, RZG2L_MPXED_PIN_FUNCS),
@@ -1059,7 +1320,37 @@ static const u32 r9a07g043_gpio_configs[] = {
RZG2L_GPIO_PORT_PACK(6, 0x22, RZG2L_MPXED_PIN_FUNCS),
};
-static struct {
+static const u32 r9a08g045_gpio_configs[] = {
+ RZG2L_GPIO_PORT_PACK(4, 0x20, RZG3S_MPXED_PIN_FUNCS(A)), /* P0 */
+ RZG2L_GPIO_PORT_PACK(5, 0x30, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IOLH_C |
+ PIN_CFG_IO_VMC_ETH0)), /* P1 */
+ RZG2L_GPIO_PORT_PACK(4, 0x31, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IOLH_C |
+ PIN_CFG_IO_VMC_ETH0)), /* P2 */
+ RZG2L_GPIO_PORT_PACK(4, 0x32, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IOLH_C |
+ PIN_CFG_IO_VMC_ETH0)), /* P3 */
+ RZG2L_GPIO_PORT_PACK(6, 0x33, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IOLH_C |
+ PIN_CFG_IO_VMC_ETH0)), /* P4 */
+ RZG2L_GPIO_PORT_PACK(5, 0x21, RZG3S_MPXED_PIN_FUNCS(A)), /* P5 */
+ RZG2L_GPIO_PORT_PACK(5, 0x22, RZG3S_MPXED_PIN_FUNCS(A)), /* P6 */
+ RZG2L_GPIO_PORT_PACK(5, 0x34, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IOLH_C |
+ PIN_CFG_IO_VMC_ETH1)), /* P7 */
+ RZG2L_GPIO_PORT_PACK(5, 0x35, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IOLH_C |
+ PIN_CFG_IO_VMC_ETH1)), /* P8 */
+ RZG2L_GPIO_PORT_PACK(4, 0x36, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IOLH_C |
+ PIN_CFG_IO_VMC_ETH1)), /* P9 */
+ RZG2L_GPIO_PORT_PACK(5, 0x37, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IOLH_C |
+ PIN_CFG_IO_VMC_ETH1)), /* P10 */
+ RZG2L_GPIO_PORT_PACK(4, 0x23, RZG3S_MPXED_PIN_FUNCS(B) | PIN_CFG_IEN), /* P11 */
+ RZG2L_GPIO_PORT_PACK(2, 0x24, RZG3S_MPXED_PIN_FUNCS(B) | PIN_CFG_IEN), /* P12 */
+ RZG2L_GPIO_PORT_PACK(5, 0x25, RZG3S_MPXED_PIN_FUNCS(A)), /* P13 */
+ RZG2L_GPIO_PORT_PACK(3, 0x26, RZG3S_MPXED_PIN_FUNCS(A)), /* P14 */
+ RZG2L_GPIO_PORT_PACK(4, 0x27, RZG3S_MPXED_PIN_FUNCS(A)), /* P15 */
+ RZG2L_GPIO_PORT_PACK(2, 0x28, RZG3S_MPXED_PIN_FUNCS(A)), /* P16 */
+ RZG2L_GPIO_PORT_PACK(4, 0x29, RZG3S_MPXED_PIN_FUNCS(A)), /* P17 */
+ RZG2L_GPIO_PORT_PACK(6, 0x2a, RZG3S_MPXED_PIN_FUNCS(A)), /* P18 */
+};
+
+static const struct {
struct rzg2l_dedicated_configs common[35];
struct rzg2l_dedicated_configs rzg2l_pins[7];
} rzg2l_dedicated_pins = {
@@ -1145,6 +1436,46 @@ static struct {
}
};
+static const struct rzg2l_dedicated_configs rzg3s_dedicated_pins[] = {
+ { "NMI", RZG2L_SINGLE_PIN_PACK(0x0, 0, (PIN_CFG_FILONOFF | PIN_CFG_FILNUM |
+ PIN_CFG_FILCLKSEL)) },
+ { "TMS/SWDIO", RZG2L_SINGLE_PIN_PACK(0x1, 0, (PIN_CFG_IOLH_A | PIN_CFG_IEN |
+ PIN_CFG_SOFT_PS)) },
+ { "TDO", RZG2L_SINGLE_PIN_PACK(0x1, 1, (PIN_CFG_IOLH_A | PIN_CFG_SOFT_PS)) },
+ { "WDTOVF_PERROUT#", RZG2L_SINGLE_PIN_PACK(0x6, 0, PIN_CFG_IOLH_A | PIN_CFG_SOFT_PS) },
+ { "SD0_CLK", RZG2L_SINGLE_PIN_PACK(0x10, 0, (PIN_CFG_IOLH_B | PIN_CFG_IO_VMC_SD0)) },
+ { "SD0_CMD", RZG2L_SINGLE_PIN_PACK(0x10, 1, (PIN_CFG_IOLH_B | PIN_CFG_IEN |
+ PIN_CFG_IO_VMC_SD0)) },
+ { "SD0_RST#", RZG2L_SINGLE_PIN_PACK(0x10, 2, (PIN_CFG_IOLH_B | PIN_CFG_IO_VMC_SD0)) },
+ { "SD0_DATA0", RZG2L_SINGLE_PIN_PACK(0x11, 0, (PIN_CFG_IOLH_B | PIN_CFG_IEN |
+ PIN_CFG_IO_VMC_SD0)) },
+ { "SD0_DATA1", RZG2L_SINGLE_PIN_PACK(0x11, 1, (PIN_CFG_IOLH_B | PIN_CFG_IEN |
+ PIN_CFG_IO_VMC_SD0)) },
+ { "SD0_DATA2", RZG2L_SINGLE_PIN_PACK(0x11, 2, (PIN_CFG_IOLH_B | PIN_CFG_IEN |
+ PIN_CFG_IO_VMC_SD0)) },
+ { "SD0_DATA3", RZG2L_SINGLE_PIN_PACK(0x11, 3, (PIN_CFG_IOLH_B | PIN_CFG_IEN |
+ PIN_CFG_IO_VMC_SD0)) },
+ { "SD0_DATA4", RZG2L_SINGLE_PIN_PACK(0x11, 4, (PIN_CFG_IOLH_B | PIN_CFG_IEN |
+ PIN_CFG_IO_VMC_SD0)) },
+ { "SD0_DATA5", RZG2L_SINGLE_PIN_PACK(0x11, 5, (PIN_CFG_IOLH_B | PIN_CFG_IEN |
+ PIN_CFG_IO_VMC_SD0)) },
+ { "SD0_DATA6", RZG2L_SINGLE_PIN_PACK(0x11, 6, (PIN_CFG_IOLH_B | PIN_CFG_IEN |
+ PIN_CFG_IO_VMC_SD0)) },
+ { "SD0_DATA7", RZG2L_SINGLE_PIN_PACK(0x11, 7, (PIN_CFG_IOLH_B | PIN_CFG_IEN |
+ PIN_CFG_IO_VMC_SD0)) },
+ { "SD1_CLK", RZG2L_SINGLE_PIN_PACK(0x12, 0, (PIN_CFG_IOLH_B | PIN_CFG_IO_VMC_SD1)) },
+ { "SD1_CMD", RZG2L_SINGLE_PIN_PACK(0x12, 1, (PIN_CFG_IOLH_B | PIN_CFG_IEN |
+ PIN_CFG_IO_VMC_SD1)) },
+ { "SD1_DATA0", RZG2L_SINGLE_PIN_PACK(0x13, 0, (PIN_CFG_IOLH_B | PIN_CFG_IEN |
+ PIN_CFG_IO_VMC_SD1)) },
+ { "SD1_DATA1", RZG2L_SINGLE_PIN_PACK(0x13, 1, (PIN_CFG_IOLH_B | PIN_CFG_IEN |
+ PIN_CFG_IO_VMC_SD1)) },
+ { "SD1_DATA2", RZG2L_SINGLE_PIN_PACK(0x13, 2, (PIN_CFG_IOLH_B | PIN_CFG_IEN |
+ PIN_CFG_IO_VMC_SD1)) },
+ { "SD1_DATA3", RZG2L_SINGLE_PIN_PACK(0x13, 3, (PIN_CFG_IOLH_B | PIN_CFG_IEN |
+ PIN_CFG_IO_VMC_SD1)) },
+};
+
static int rzg2l_gpio_get_gpioint(unsigned int virq, const struct rzg2l_pinctrl_data *data)
{
unsigned int gpioint;
@@ -1170,17 +1501,16 @@ static void rzg2l_gpio_irq_disable(struct irq_data *d)
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
struct rzg2l_pinctrl *pctrl = container_of(gc, struct rzg2l_pinctrl, gpio_chip);
unsigned int hwirq = irqd_to_hwirq(d);
+ const struct pinctrl_pin_desc *pin_desc = &pctrl->desc.pins[hwirq];
+ unsigned int *pin_data = pin_desc->drv_data;
+ u32 off = RZG2L_PIN_CFG_TO_PORT_OFFSET(*pin_data);
+ u8 bit = RZG2L_PIN_ID_TO_PIN(hwirq);
unsigned long flags;
void __iomem *addr;
- u32 port;
- u8 bit;
irq_chip_disable_parent(d);
- port = RZG2L_PIN_ID_TO_PORT(hwirq);
- bit = RZG2L_PIN_ID_TO_PIN(hwirq);
-
- addr = pctrl->base + ISEL(port);
+ addr = pctrl->base + ISEL(off);
if (bit >= 4) {
bit -= 4;
addr += 4;
@@ -1198,17 +1528,16 @@ static void rzg2l_gpio_irq_enable(struct irq_data *d)
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
struct rzg2l_pinctrl *pctrl = container_of(gc, struct rzg2l_pinctrl, gpio_chip);
unsigned int hwirq = irqd_to_hwirq(d);
+ const struct pinctrl_pin_desc *pin_desc = &pctrl->desc.pins[hwirq];
+ unsigned int *pin_data = pin_desc->drv_data;
+ u32 off = RZG2L_PIN_CFG_TO_PORT_OFFSET(*pin_data);
+ u8 bit = RZG2L_PIN_ID_TO_PIN(hwirq);
unsigned long flags;
void __iomem *addr;
- u32 port;
- u8 bit;
gpiochip_enable_irq(gc, hwirq);
- port = RZG2L_PIN_ID_TO_PORT(hwirq);
- bit = RZG2L_PIN_ID_TO_PIN(hwirq);
-
- addr = pctrl->base + ISEL(port);
+ addr = pctrl->base + ISEL(off);
if (bit >= 4) {
bit -= 4;
addr += 4;
@@ -1415,6 +1744,7 @@ static int rzg2l_gpio_register(struct rzg2l_pinctrl *pctrl)
static int rzg2l_pinctrl_register(struct rzg2l_pinctrl *pctrl)
{
+ const struct rzg2l_hwcfg *hwcfg = pctrl->data->hwcfg;
struct pinctrl_pin_desc *pins;
unsigned int i, j;
u32 *pin_data;
@@ -1457,6 +1787,22 @@ static int rzg2l_pinctrl_register(struct rzg2l_pinctrl *pctrl)
pins[index].drv_data = &pin_data[index];
}
+ pctrl->settings = devm_kcalloc(pctrl->dev, pctrl->desc.npins, sizeof(*pctrl->settings),
+ GFP_KERNEL);
+ if (!pctrl->settings)
+ return -ENOMEM;
+
+ for (i = 0; hwcfg->drive_strength_ua && i < pctrl->desc.npins; i++) {
+ if (pin_data[i] & PIN_CFG_SOFT_PS) {
+ pctrl->settings[i].power_source = 3300;
+ } else {
+ ret = rzg2l_get_power_source(pctrl, i, pin_data[i]);
+ if (ret < 0)
+ continue;
+ pctrl->settings[i].power_source = ret;
+ }
+ }
+
ret = devm_pinctrl_register_and_init(pctrl->dev, &pctrl->desc, pctrl,
&pctrl->pctl);
if (ret) {
@@ -1485,12 +1831,15 @@ static int rzg2l_pinctrl_probe(struct platform_device *pdev)
struct clk *clk;
int ret;
- BUILD_BUG_ON(ARRAY_SIZE(rzg2l_gpio_configs) * RZG2L_PINS_PER_PORT >
+ BUILD_BUG_ON(ARRAY_SIZE(r9a07g044_gpio_configs) * RZG2L_PINS_PER_PORT >
ARRAY_SIZE(rzg2l_gpio_names));
BUILD_BUG_ON(ARRAY_SIZE(r9a07g043_gpio_configs) * RZG2L_PINS_PER_PORT >
ARRAY_SIZE(rzg2l_gpio_names));
+ BUILD_BUG_ON(ARRAY_SIZE(r9a08g045_gpio_configs) * RZG2L_PINS_PER_PORT >
+ ARRAY_SIZE(rzg2l_gpio_names));
+
pctrl = devm_kzalloc(&pdev->dev, sizeof(*pctrl), GFP_KERNEL);
if (!pctrl)
return -ENOMEM;
@@ -1524,6 +1873,47 @@ static int rzg2l_pinctrl_probe(struct platform_device *pdev)
return 0;
}
+static const struct rzg2l_hwcfg rzg2l_hwcfg = {
+ .regs = {
+ .pwpr = 0x3014,
+ .sd_ch = 0x3000,
+ },
+ .iolh_groupa_ua = {
+ /* 3v3 power source */
+ [RZG2L_IOLH_IDX_3V3] = 2000, 4000, 8000, 12000,
+ },
+ .iolh_groupb_oi = { 100, 66, 50, 33, },
+};
+
+static const struct rzg2l_hwcfg rzg3s_hwcfg = {
+ .regs = {
+ .pwpr = 0x3000,
+ .sd_ch = 0x3004,
+ },
+ .iolh_groupa_ua = {
+ /* 1v8 power source */
+ [RZG2L_IOLH_IDX_1V8] = 2200, 4400, 9000, 10000,
+ /* 3v3 power source */
+ [RZG2L_IOLH_IDX_3V3] = 1900, 4000, 8000, 9000,
+ },
+ .iolh_groupb_ua = {
+ /* 1v8 power source */
+ [RZG2L_IOLH_IDX_1V8] = 7000, 8000, 9000, 10000,
+ /* 3v3 power source */
+ [RZG2L_IOLH_IDX_3V3] = 4000, 6000, 8000, 9000,
+ },
+ .iolh_groupc_ua = {
+ /* 1v8 power source */
+ [RZG2L_IOLH_IDX_1V8] = 5200, 6000, 6550, 6800,
+ /* 2v5 source */
+ [RZG2L_IOLH_IDX_2V5] = 4700, 5300, 5800, 6100,
+ /* 3v3 power source */
+ [RZG2L_IOLH_IDX_3V3] = 4500, 5200, 5700, 6050,
+ },
+ .drive_strength_ua = true,
+ .func_base = 1,
+};
+
static struct rzg2l_pinctrl_data r9a07g043_data = {
.port_pins = rzg2l_gpio_names,
.port_pin_configs = r9a07g043_gpio_configs,
@@ -1531,16 +1921,28 @@ static struct rzg2l_pinctrl_data r9a07g043_data = {
.dedicated_pins = rzg2l_dedicated_pins.common,
.n_port_pins = ARRAY_SIZE(r9a07g043_gpio_configs) * RZG2L_PINS_PER_PORT,
.n_dedicated_pins = ARRAY_SIZE(rzg2l_dedicated_pins.common),
+ .hwcfg = &rzg2l_hwcfg,
};
static struct rzg2l_pinctrl_data r9a07g044_data = {
.port_pins = rzg2l_gpio_names,
- .port_pin_configs = rzg2l_gpio_configs,
- .n_ports = ARRAY_SIZE(rzg2l_gpio_configs),
+ .port_pin_configs = r9a07g044_gpio_configs,
+ .n_ports = ARRAY_SIZE(r9a07g044_gpio_configs),
.dedicated_pins = rzg2l_dedicated_pins.common,
- .n_port_pins = ARRAY_SIZE(rzg2l_gpio_configs) * RZG2L_PINS_PER_PORT,
+ .n_port_pins = ARRAY_SIZE(r9a07g044_gpio_configs) * RZG2L_PINS_PER_PORT,
.n_dedicated_pins = ARRAY_SIZE(rzg2l_dedicated_pins.common) +
ARRAY_SIZE(rzg2l_dedicated_pins.rzg2l_pins),
+ .hwcfg = &rzg2l_hwcfg,
+};
+
+static struct rzg2l_pinctrl_data r9a08g045_data = {
+ .port_pins = rzg2l_gpio_names,
+ .port_pin_configs = r9a08g045_gpio_configs,
+ .n_ports = ARRAY_SIZE(r9a08g045_gpio_configs),
+ .dedicated_pins = rzg3s_dedicated_pins,
+ .n_port_pins = ARRAY_SIZE(r9a08g045_gpio_configs) * RZG2L_PINS_PER_PORT,
+ .n_dedicated_pins = ARRAY_SIZE(rzg3s_dedicated_pins),
+ .hwcfg = &rzg3s_hwcfg,
};
static const struct of_device_id rzg2l_pinctrl_of_table[] = {
@@ -1552,6 +1954,10 @@ static const struct of_device_id rzg2l_pinctrl_of_table[] = {
.compatible = "renesas,r9a07g044-pinctrl",
.data = &r9a07g044_data,
},
+ {
+ .compatible = "renesas,r9a08g045-pinctrl",
+ .data = &r9a08g045_data,
+ },
{ /* sentinel */ }
};
diff --git a/drivers/pinctrl/renesas/pinctrl-rzn1.c b/drivers/pinctrl/renesas/pinctrl-rzn1.c
index 374b9f2813..4b2f107824 100644
--- a/drivers/pinctrl/renesas/pinctrl-rzn1.c
+++ b/drivers/pinctrl/renesas/pinctrl-rzn1.c
@@ -920,13 +920,11 @@ err_clk:
return ret;
}
-static int rzn1_pinctrl_remove(struct platform_device *pdev)
+static void rzn1_pinctrl_remove(struct platform_device *pdev)
{
struct rzn1_pinctrl *ipctl = platform_get_drvdata(pdev);
clk_disable_unprepare(ipctl->clk);
-
- return 0;
}
static const struct of_device_id rzn1_pinctrl_match[] = {
@@ -937,7 +935,7 @@ MODULE_DEVICE_TABLE(of, rzn1_pinctrl_match);
static struct platform_driver rzn1_pinctrl_driver = {
.probe = rzn1_pinctrl_probe,
- .remove = rzn1_pinctrl_remove,
+ .remove_new = rzn1_pinctrl_remove,
.driver = {
.name = "rzn1-pinctrl",
.of_match_table = rzn1_pinctrl_match,
diff --git a/drivers/pinctrl/renesas/pinctrl-rzv2m.c b/drivers/pinctrl/renesas/pinctrl-rzv2m.c
index 52aeafaba4..21d7d5ac8c 100644
--- a/drivers/pinctrl/renesas/pinctrl-rzv2m.c
+++ b/drivers/pinctrl/renesas/pinctrl-rzv2m.c
@@ -754,7 +754,7 @@ static int rzv2m_gpio_request(struct gpio_chip *chip, unsigned int offset)
u8 bit = RZV2M_PIN_ID_TO_PIN(offset);
int ret;
- ret = pinctrl_gpio_request(chip->base + offset);
+ ret = pinctrl_gpio_request(chip, offset);
if (ret)
return ret;
@@ -832,7 +832,7 @@ static int rzv2m_gpio_get(struct gpio_chip *chip, unsigned int offset)
static void rzv2m_gpio_free(struct gpio_chip *chip, unsigned int offset)
{
- pinctrl_gpio_free(chip->base + offset);
+ pinctrl_gpio_free(chip, offset);
/*
* Set the GPIO as an input to ensure that the next GPIO request won't
diff --git a/drivers/pinctrl/samsung/pinctrl-exynos.c b/drivers/pinctrl/samsung/pinctrl-exynos.c
index a8212fc126..6b58ec84e3 100644
--- a/drivers/pinctrl/samsung/pinctrl-exynos.c
+++ b/drivers/pinctrl/samsung/pinctrl-exynos.c
@@ -616,6 +616,7 @@ __init int exynos_eint_wkup_init(struct samsung_pinctrl_drv_data *d)
+ muxed_banks*sizeof(struct samsung_pin_bank *), GFP_KERNEL);
if (!muxed_data)
return -ENOMEM;
+ muxed_data->nr_banks = muxed_banks;
irq_set_chained_handler_and_data(irq, exynos_irq_demux_eint16_31,
muxed_data);
@@ -628,7 +629,6 @@ __init int exynos_eint_wkup_init(struct samsung_pinctrl_drv_data *d)
muxed_data->banks[idx++] = bank;
}
- muxed_data->nr_banks = muxed_banks;
return 0;
}
diff --git a/drivers/pinctrl/samsung/pinctrl-exynos.h b/drivers/pinctrl/samsung/pinctrl-exynos.h
index 7bd6d82c9f..3ac52c2cf9 100644
--- a/drivers/pinctrl/samsung/pinctrl-exynos.h
+++ b/drivers/pinctrl/samsung/pinctrl-exynos.h
@@ -159,7 +159,7 @@ struct exynos_weint_data {
*/
struct exynos_muxed_weint_data {
unsigned int nr_banks;
- struct samsung_pin_bank *banks[];
+ struct samsung_pin_bank *banks[] __counted_by(nr_banks);
};
int exynos_eint_gpio_init(struct samsung_pinctrl_drv_data *d);
diff --git a/drivers/pinctrl/samsung/pinctrl-samsung.c b/drivers/pinctrl/samsung/pinctrl-samsung.c
index e54847040b..79babbb39c 100644
--- a/drivers/pinctrl/samsung/pinctrl-samsung.c
+++ b/drivers/pinctrl/samsung/pinctrl-samsung.c
@@ -45,8 +45,6 @@ static struct pin_config {
{ "samsung,pin-val", PINCFG_TYPE_DAT },
};
-static unsigned int pin_base;
-
static int samsung_get_group_count(struct pinctrl_dev *pctldev)
{
struct samsung_pinctrl_drv_data *pmx = pinctrl_dev_get_drvdata(pctldev);
@@ -389,8 +387,7 @@ static void samsung_pinmux_setup(struct pinctrl_dev *pctldev, unsigned selector,
func = &drvdata->pmx_functions[selector];
grp = &drvdata->pin_groups[group];
- pin_to_reg_bank(drvdata, grp->pins[0] - drvdata->pin_base,
- &reg, &pin_offset, &bank);
+ pin_to_reg_bank(drvdata, grp->pins[0], &reg, &pin_offset, &bank);
type = bank->type;
mask = (1 << type->fld_width[PINCFG_TYPE_FUNC]) - 1;
shift = pin_offset * type->fld_width[PINCFG_TYPE_FUNC];
@@ -441,8 +438,7 @@ static int samsung_pinconf_rw(struct pinctrl_dev *pctldev, unsigned int pin,
unsigned long flags;
drvdata = pinctrl_dev_get_drvdata(pctldev);
- pin_to_reg_bank(drvdata, pin - drvdata->pin_base, &reg_base,
- &pin_offset, &bank);
+ pin_to_reg_bank(drvdata, pin, &reg_base, &pin_offset, &bank);
type = bank->type;
if (cfg_type >= PINCFG_TYPE_NUM || !type->fld_width[cfg_type])
@@ -665,6 +661,21 @@ static int samsung_gpio_to_irq(struct gpio_chip *gc, unsigned offset)
return (virq) ? : -ENXIO;
}
+static int samsung_add_pin_ranges(struct gpio_chip *gc)
+{
+ struct samsung_pin_bank *bank = gpiochip_get_data(gc);
+
+ bank->grange.name = bank->name;
+ bank->grange.id = bank->id;
+ bank->grange.pin_base = bank->pin_base;
+ bank->grange.base = gc->base;
+ bank->grange.npins = bank->nr_pins;
+ bank->grange.gc = &bank->gpio_chip;
+ pinctrl_add_gpio_range(bank->drvdata->pctl_dev, &bank->grange);
+
+ return 0;
+}
+
static struct samsung_pin_group *samsung_pinctrl_create_groups(
struct device *dev,
struct samsung_pinctrl_drv_data *drvdata,
@@ -876,7 +887,7 @@ static int samsung_pinctrl_register(struct platform_device *pdev,
/* dynamically populate the pin number and pin name for pindesc */
for (pin = 0, pdesc = pindesc; pin < ctrldesc->npins; pin++, pdesc++)
- pdesc->number = pin + drvdata->pin_base;
+ pdesc->number = pin;
/*
* allocate space for storing the dynamically generated names for all
@@ -892,6 +903,7 @@ static int samsung_pinctrl_register(struct platform_device *pdev,
/* for each pin, the name of the pin is pin-bank name + pin number */
for (bank = 0; bank < drvdata->nr_banks; bank++) {
pin_bank = &drvdata->pin_banks[bank];
+ pin_bank->id = bank;
for (pin = 0; pin < pin_bank->nr_pins; pin++) {
sprintf(pin_names, "%s-%d", pin_bank->name, pin);
pdesc = pindesc + pin_bank->pin_base + pin;
@@ -904,23 +916,11 @@ static int samsung_pinctrl_register(struct platform_device *pdev,
if (ret)
return ret;
- drvdata->pctl_dev = devm_pinctrl_register(&pdev->dev, ctrldesc,
- drvdata);
- if (IS_ERR(drvdata->pctl_dev)) {
+ ret = devm_pinctrl_register_and_init(&pdev->dev, ctrldesc, drvdata,
+ &drvdata->pctl_dev);
+ if (ret) {
dev_err(&pdev->dev, "could not register pinctrl driver\n");
- return PTR_ERR(drvdata->pctl_dev);
- }
-
- for (bank = 0; bank < drvdata->nr_banks; ++bank) {
- pin_bank = &drvdata->pin_banks[bank];
- pin_bank->grange.name = pin_bank->name;
- pin_bank->grange.id = bank;
- pin_bank->grange.pin_base = drvdata->pin_base
- + pin_bank->pin_base;
- pin_bank->grange.base = pin_bank->grange.pin_base;
- pin_bank->grange.npins = pin_bank->nr_pins;
- pin_bank->grange.gc = &pin_bank->gpio_chip;
- pinctrl_add_gpio_range(drvdata->pctl_dev, &pin_bank->grange);
+ return ret;
}
return 0;
@@ -947,6 +947,7 @@ static const struct gpio_chip samsung_gpiolib_chip = {
.direction_input = samsung_gpio_direction_input,
.direction_output = samsung_gpio_direction_output,
.to_irq = samsung_gpio_to_irq,
+ .add_pin_ranges = samsung_add_pin_ranges,
.owner = THIS_MODULE,
};
@@ -963,7 +964,7 @@ static int samsung_gpiolib_register(struct platform_device *pdev,
bank->gpio_chip = samsung_gpiolib_chip;
gc = &bank->gpio_chip;
- gc->base = bank->grange.base;
+ gc->base = -1; /* Dynamic allocation */
gc->ngpio = bank->nr_pins;
gc->parent = &pdev->dev;
gc->fwnode = bank->fwnode;
@@ -1124,9 +1125,6 @@ samsung_pinctrl_get_soc_data(struct samsung_pinctrl_drv_data *d,
samsung_banks_node_get(&pdev->dev, d);
- d->pin_base = pin_base;
- pin_base += d->nr_pins;
-
return ctrl;
}
@@ -1176,6 +1174,10 @@ static int samsung_pinctrl_probe(struct platform_device *pdev)
if (ret)
goto err_unregister;
+ ret = pinctrl_enable(drvdata->pctl_dev);
+ if (ret)
+ goto err_unregister;
+
platform_set_drvdata(pdev, drvdata);
return 0;
diff --git a/drivers/pinctrl/samsung/pinctrl-samsung.h b/drivers/pinctrl/samsung/pinctrl-samsung.h
index 9af93e3d8d..9b3db50ade 100644
--- a/drivers/pinctrl/samsung/pinctrl-samsung.h
+++ b/drivers/pinctrl/samsung/pinctrl-samsung.h
@@ -148,6 +148,7 @@ struct samsung_pin_bank_data {
* @eint_mask: bit mask of pins which support EINT function.
* @eint_offset: SoC-specific EINT register or interrupt offset of bank.
* @name: name to be prefixed for each pin in this pin bank.
+ * @id: id of the bank, propagated to the pin range.
* @pin_base: starting pin number of the bank.
* @soc_priv: per-bank private data for SoC-specific code.
* @of_node: OF node of the bank.
@@ -170,6 +171,7 @@ struct samsung_pin_bank {
u32 eint_mask;
u32 eint_offset;
const char *name;
+ u32 id;
u32 pin_base;
void *soc_priv;
@@ -267,7 +269,6 @@ struct samsung_pin_ctrl {
* @nr_groups: number of such pin groups.
* @pmx_functions: list of pin functions available to the driver.
* @nr_function: number of such pin functions.
- * @pin_base: starting system wide pin number.
* @nr_pins: number of pins supported by the controller.
* @retention_ctrl: retention control runtime data.
* @suspend: platform specific suspend callback, executed during pin controller
@@ -291,7 +292,6 @@ struct samsung_pinctrl_drv_data {
struct samsung_pin_bank *pin_banks;
unsigned int nr_banks;
- unsigned int pin_base;
unsigned int nr_pins;
struct samsung_retention_ctrl *retention_ctrl;
diff --git a/drivers/pinctrl/spear/pinctrl-plgpio.c b/drivers/pinctrl/spear/pinctrl-plgpio.c
index 722681e0b8..a05570c7d8 100644
--- a/drivers/pinctrl/spear/pinctrl-plgpio.c
+++ b/drivers/pinctrl/spear/pinctrl-plgpio.c
@@ -204,14 +204,13 @@ static void plgpio_set_value(struct gpio_chip *chip, unsigned offset, int value)
static int plgpio_request(struct gpio_chip *chip, unsigned offset)
{
struct plgpio *plgpio = gpiochip_get_data(chip);
- int gpio = chip->base + offset;
unsigned long flags;
int ret = 0;
if (offset >= chip->ngpio)
return -EINVAL;
- ret = pinctrl_gpio_request(gpio);
+ ret = pinctrl_gpio_request(chip, offset);
if (ret)
return ret;
@@ -249,14 +248,13 @@ err1:
if (!IS_ERR(plgpio->clk))
clk_disable(plgpio->clk);
err0:
- pinctrl_gpio_free(gpio);
+ pinctrl_gpio_free(chip, offset);
return ret;
}
static void plgpio_free(struct gpio_chip *chip, unsigned offset)
{
struct plgpio *plgpio = gpiochip_get_data(chip);
- int gpio = chip->base + offset;
unsigned long flags;
if (offset >= chip->ngpio)
@@ -280,7 +278,7 @@ disable_clk:
if (!IS_ERR(plgpio->clk))
clk_disable(plgpio->clk);
- pinctrl_gpio_free(gpio);
+ pinctrl_gpio_free(chip, offset);
}
/* PLGPIO IRQ */
diff --git a/drivers/pinctrl/sprd/pinctrl-sprd-sc9860.c b/drivers/pinctrl/sprd/pinctrl-sprd-sc9860.c
index d14f382f23..9c3c39dc65 100644
--- a/drivers/pinctrl/sprd/pinctrl-sprd-sc9860.c
+++ b/drivers/pinctrl/sprd/pinctrl-sprd-sc9860.c
@@ -943,7 +943,7 @@ static struct platform_driver sprd_pinctrl_driver = {
.of_match_table = sprd_pinctrl_of_match,
},
.probe = sprd_pinctrl_probe,
- .remove = sprd_pinctrl_remove,
+ .remove_new = sprd_pinctrl_remove,
.shutdown = sprd_pinctrl_shutdown,
};
module_platform_driver(sprd_pinctrl_driver);
diff --git a/drivers/pinctrl/sprd/pinctrl-sprd.c b/drivers/pinctrl/sprd/pinctrl-sprd.c
index ccdcc91c7f..d0b6d3e655 100644
--- a/drivers/pinctrl/sprd/pinctrl-sprd.c
+++ b/drivers/pinctrl/sprd/pinctrl-sprd.c
@@ -1110,12 +1110,11 @@ int sprd_pinctrl_core_probe(struct platform_device *pdev,
}
EXPORT_SYMBOL_GPL(sprd_pinctrl_core_probe);
-int sprd_pinctrl_remove(struct platform_device *pdev)
+void sprd_pinctrl_remove(struct platform_device *pdev)
{
struct sprd_pinctrl *sprd_pctl = platform_get_drvdata(pdev);
pinctrl_unregister(sprd_pctl->pctl);
- return 0;
}
EXPORT_SYMBOL_GPL(sprd_pinctrl_remove);
diff --git a/drivers/pinctrl/sprd/pinctrl-sprd.h b/drivers/pinctrl/sprd/pinctrl-sprd.h
index 69544a3cd6..190bcdb3bb 100644
--- a/drivers/pinctrl/sprd/pinctrl-sprd.h
+++ b/drivers/pinctrl/sprd/pinctrl-sprd.h
@@ -53,7 +53,7 @@ struct sprd_pins_info {
int sprd_pinctrl_core_probe(struct platform_device *pdev,
struct sprd_pins_info *sprd_soc_pin_info,
int pins_cnt);
-int sprd_pinctrl_remove(struct platform_device *pdev);
+void sprd_pinctrl_remove(struct platform_device *pdev);
void sprd_pinctrl_shutdown(struct platform_device *pdev);
#endif /* __PINCTRL_SPRD_H__ */
diff --git a/drivers/pinctrl/starfive/pinctrl-starfive-jh7100.c b/drivers/pinctrl/starfive/pinctrl-starfive-jh7100.c
index 561fd0c6b9..b29b0ab989 100644
--- a/drivers/pinctrl/starfive/pinctrl-starfive-jh7100.c
+++ b/drivers/pinctrl/starfive/pinctrl-starfive-jh7100.c
@@ -916,16 +916,6 @@ static struct pinctrl_desc starfive_desc = {
.custom_conf_items = starfive_pinconf_custom_conf_items,
};
-static int starfive_gpio_request(struct gpio_chip *gc, unsigned int gpio)
-{
- return pinctrl_gpio_request(gc->base + gpio);
-}
-
-static void starfive_gpio_free(struct gpio_chip *gc, unsigned int gpio)
-{
- pinctrl_gpio_free(gc->base + gpio);
-}
-
static int starfive_gpio_get_direction(struct gpio_chip *gc, unsigned int gpio)
{
struct starfive_pinctrl *sfp = container_of(gc, struct starfive_pinctrl, gc);
@@ -1309,8 +1299,8 @@ static int starfive_probe(struct platform_device *pdev)
sfp->gc.label = dev_name(dev);
sfp->gc.owner = THIS_MODULE;
- sfp->gc.request = starfive_gpio_request;
- sfp->gc.free = starfive_gpio_free;
+ sfp->gc.request = pinctrl_gpio_request;
+ sfp->gc.free = pinctrl_gpio_free;
sfp->gc.get_direction = starfive_gpio_get_direction;
sfp->gc.direction_input = starfive_gpio_direction_input;
sfp->gc.direction_output = starfive_gpio_direction_output;
diff --git a/drivers/pinctrl/starfive/pinctrl-starfive-jh7110.c b/drivers/pinctrl/starfive/pinctrl-starfive-jh7110.c
index b4f7995726..6de11a4057 100644
--- a/drivers/pinctrl/starfive/pinctrl-starfive-jh7110.c
+++ b/drivers/pinctrl/starfive/pinctrl-starfive-jh7110.c
@@ -545,16 +545,6 @@ static const struct pinconf_ops jh7110_pinconf_ops = {
.is_generic = true,
};
-static int jh7110_gpio_request(struct gpio_chip *gc, unsigned int gpio)
-{
- return pinctrl_gpio_request(gc->base + gpio);
-}
-
-static void jh7110_gpio_free(struct gpio_chip *gc, unsigned int gpio)
-{
- pinctrl_gpio_free(gc->base + gpio);
-}
-
static int jh7110_gpio_get_direction(struct gpio_chip *gc,
unsigned int gpio)
{
@@ -940,8 +930,8 @@ int jh7110_pinctrl_probe(struct platform_device *pdev)
sfp->gc.label = dev_name(dev);
sfp->gc.owner = THIS_MODULE;
- sfp->gc.request = jh7110_gpio_request;
- sfp->gc.free = jh7110_gpio_free;
+ sfp->gc.request = pinctrl_gpio_request;
+ sfp->gc.free = pinctrl_gpio_free;
sfp->gc.get_direction = jh7110_gpio_get_direction;
sfp->gc.direction_input = jh7110_gpio_direction_input;
sfp->gc.direction_output = jh7110_gpio_direction_output;
diff --git a/drivers/pinctrl/stm32/pinctrl-stm32.c b/drivers/pinctrl/stm32/pinctrl-stm32.c
index 346a31f31b..603f900e88 100644
--- a/drivers/pinctrl/stm32/pinctrl-stm32.c
+++ b/drivers/pinctrl/stm32/pinctrl-stm32.c
@@ -217,12 +217,7 @@ static int stm32_gpio_request(struct gpio_chip *chip, unsigned offset)
return -EINVAL;
}
- return pinctrl_gpio_request(chip->base + offset);
-}
-
-static void stm32_gpio_free(struct gpio_chip *chip, unsigned offset)
-{
- pinctrl_gpio_free(chip->base + offset);
+ return pinctrl_gpio_request(chip, offset);
}
static int stm32_gpio_get(struct gpio_chip *chip, unsigned offset)
@@ -239,18 +234,13 @@ static void stm32_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
__stm32_gpio_set(bank, offset, value);
}
-static int stm32_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
-{
- return pinctrl_gpio_direction_input(chip->base + offset);
-}
-
static int stm32_gpio_direction_output(struct gpio_chip *chip,
unsigned offset, int value)
{
struct stm32_gpio_bank *bank = gpiochip_get_data(chip);
__stm32_gpio_set(bank, offset, value);
- pinctrl_gpio_direction_output(chip->base + offset);
+ pinctrl_gpio_direction_output(chip, offset);
return 0;
}
@@ -316,10 +306,10 @@ static int stm32_gpio_init_valid_mask(struct gpio_chip *chip,
static const struct gpio_chip stm32_gpio_template = {
.request = stm32_gpio_request,
- .free = stm32_gpio_free,
+ .free = pinctrl_gpio_free,
.get = stm32_gpio_get,
.set = stm32_gpio_set,
- .direction_input = stm32_gpio_direction_input,
+ .direction_input = pinctrl_gpio_direction_input,
.direction_output = stm32_gpio_direction_output,
.to_irq = stm32_gpio_to_irq,
.get_direction = stm32_gpio_get_direction,
@@ -381,7 +371,7 @@ static int stm32_gpio_irq_request_resources(struct irq_data *irq_data)
struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent);
int ret;
- ret = stm32_gpio_direction_input(&bank->gpio_chip, irq_data->hwirq);
+ ret = pinctrl_gpio_direction_input(&bank->gpio_chip, irq_data->hwirq);
if (ret)
return ret;
diff --git a/drivers/pinctrl/sunxi/pinctrl-sun50i-h616.c b/drivers/pinctrl/sunxi/pinctrl-sun50i-h616.c
index 73f012823a..ecf6d2438e 100644
--- a/drivers/pinctrl/sunxi/pinctrl-sun50i-h616.c
+++ b/drivers/pinctrl/sunxi/pinctrl-sun50i-h616.c
@@ -15,33 +15,81 @@
#include "pinctrl-sunxi.h"
static const struct sunxi_desc_pin h616_pins[] = {
- /* Internal connection to the AC200 part */
+ /* Internally connected to the AC200 part in the H616 SoC */
SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 0),
- SUNXI_FUNCTION(0x2, "emac1")), /* ERXD1 */
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "emac1"), /* ERXD1 */
+ SUNXI_FUNCTION(0x4, "i2c0"), /* SCK */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 0)), /* PA_EINT0 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 1),
- SUNXI_FUNCTION(0x2, "emac1")), /* ERXD0 */
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "emac1"), /* ERXD0 */
+ SUNXI_FUNCTION(0x4, "i2c0"), /* SDA */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 1)), /* PA_EINT1 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 2),
- SUNXI_FUNCTION(0x2, "emac1")), /* ECRS_DV */
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "emac1"), /* ECRS_DV */
+ SUNXI_FUNCTION(0x4, "i2c1"), /* SCK */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 2)), /* PA_EINT2 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 3),
- SUNXI_FUNCTION(0x2, "emac1")), /* ERXERR */
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "emac1"), /* ERXERR */
+ SUNXI_FUNCTION(0x4, "i2c1"), /* SDA */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 3)), /* PA_EINT3 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 4),
- SUNXI_FUNCTION(0x2, "emac1")), /* ETXD1 */
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "emac1"), /* ETXD1 */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 4)), /* PA_EINT4 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 5),
- SUNXI_FUNCTION(0x2, "emac1")), /* ETXD0 */
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "emac1"), /* ETXD0 */
+ SUNXI_FUNCTION(0x3, "i2s0"), /* DOUT0 */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 5)), /* PA_EINT5 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 6),
- SUNXI_FUNCTION(0x2, "emac1")), /* ETXCK */
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "emac1"), /* ETXCK */
+ SUNXI_FUNCTION(0x3, "i2s0"), /* MCLK */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 6)), /* PA_EINT6 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 7),
- SUNXI_FUNCTION(0x2, "emac1")), /* ETXEN */
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "emac1"), /* ETXEN */
+ SUNXI_FUNCTION(0x3, "i2s0"), /* BCLK */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 7)), /* PA_EINT7 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 8),
- SUNXI_FUNCTION(0x2, "emac1")), /* EMDC */
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "emac1"), /* EMDC */
+ SUNXI_FUNCTION(0x3, "i2s0"), /* LRCK */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 8)), /* PA_EINT8 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 9),
- SUNXI_FUNCTION(0x2, "emac1")), /* EMDIO */
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "emac1"), /* EMDIO */
+ SUNXI_FUNCTION(0x3, "i2s0"), /* DIN0 */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 9)), /* PA_EINT9 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 10),
- SUNXI_FUNCTION(0x2, "i2c3")), /* SCK */
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "i2c3"), /* SCK */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 10)), /* PA_EINT10 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 11),
- SUNXI_FUNCTION(0x2, "i2c3")), /* SDA */
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "i2c3"), /* SDA */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 11)), /* PA_EINT11 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 12),
- SUNXI_FUNCTION(0x2, "pwm5")),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "pwm5"),
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 12)), /* PA_EINT12 */
/* Hole */
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 0),
SUNXI_FUNCTION(0x0, "gpio_in"),
@@ -148,6 +196,310 @@ static const struct sunxi_desc_pin h616_pins[] = {
SUNXI_FUNCTION(0x4, "spi0"), /* HOLD */
SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 16)), /* PC_EINT16 */
/* Hole */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 0),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "lcd0"), /* D0 */
+ SUNXI_FUNCTION(0x3, "lvds0"), /* VP0 */
+ SUNXI_FUNCTION(0x4, "ts0"), /* CLK */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 0)), /* PD_EINT0 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 1),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "lcd0"), /* D1 */
+ SUNXI_FUNCTION(0x3, "lvds0"), /* VN0 */
+ SUNXI_FUNCTION(0x4, "ts0"), /* ERR */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 1)), /* PD_EINT1 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 2),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "lcd0"), /* D2 */
+ SUNXI_FUNCTION(0x3, "lvds0"), /* VP1 */
+ SUNXI_FUNCTION(0x4, "ts0"), /* SYNC */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 2)), /* PD_EINT2 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 3),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "lcd0"), /* D3 */
+ SUNXI_FUNCTION(0x3, "lvds0"), /* VN1 */
+ SUNXI_FUNCTION(0x4, "ts0"), /* DVLD */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 3)), /* PD_EINT3 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 4),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "lcd0"), /* D4 */
+ SUNXI_FUNCTION(0x3, "lvds0"), /* VP2 */
+ SUNXI_FUNCTION(0x4, "ts0"), /* D0 */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 4)), /* PD_EINT4 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 5),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "lcd0"), /* D5 */
+ SUNXI_FUNCTION(0x3, "lvds0"), /* VN2 */
+ SUNXI_FUNCTION(0x4, "ts0"), /* D1 */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 5)), /* PD_EINT5 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 6),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "lcd0"), /* D6 */
+ SUNXI_FUNCTION(0x3, "lvds0"), /* VPC */
+ SUNXI_FUNCTION(0x4, "ts0"), /* D2 */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 6)), /* PD_EINT6 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 7),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "lcd0"), /* D7 */
+ SUNXI_FUNCTION(0x3, "lvds0"), /* VNC */
+ SUNXI_FUNCTION(0x4, "ts0"), /* D3 */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 7)), /* PD_EINT7 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 8),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "lcd0"), /* D8 */
+ SUNXI_FUNCTION(0x3, "lvds0"), /* VP3 */
+ SUNXI_FUNCTION(0x4, "ts0"), /* D4 */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 8)), /* PD_EINT8 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 9),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "lcd0"), /* D9 */
+ SUNXI_FUNCTION(0x3, "lvds0"), /* VN3 */
+ SUNXI_FUNCTION(0x4, "ts0"), /* D5 */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 9)), /* PD_EINT9 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 10),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "lcd0"), /* D10 */
+ SUNXI_FUNCTION(0x3, "lvds1"), /* VP0 */
+ SUNXI_FUNCTION(0x4, "ts0"), /* D6 */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 10)), /* PD_EINT10 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 11),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "lcd0"), /* D11 */
+ SUNXI_FUNCTION(0x3, "lvds1"), /* VN0 */
+ SUNXI_FUNCTION(0x4, "ts0"), /* D7 */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 11)), /* PD_EINT11 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 12),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "lcd0"), /* D12 */
+ SUNXI_FUNCTION(0x3, "lvds1"), /* VP1 */
+ SUNXI_FUNCTION(0x4, "sim"), /* VPPEN */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 12)), /* PD_EINT12 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 13),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "lcd0"), /* D13 */
+ SUNXI_FUNCTION(0x3, "lvds1"), /* VN1 */
+ SUNXI_FUNCTION(0x4, "sim"), /* VPPPP */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 13)), /* PD_EINT13 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 14),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "lcd0"), /* D14 */
+ SUNXI_FUNCTION(0x3, "lvds1"), /* VP2 */
+ SUNXI_FUNCTION(0x4, "sim"), /* PWREN */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 14)), /* PD_EINT14 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 15),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "lcd0"), /* D15 */
+ SUNXI_FUNCTION(0x3, "lvds1"), /* VN2 */
+ SUNXI_FUNCTION(0x4, "sim"), /* CLK */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 15)), /* PD_EINT15 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 16),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "lcd0"), /* D16 */
+ SUNXI_FUNCTION(0x3, "lvds1"), /* VPC */
+ SUNXI_FUNCTION(0x4, "sim"), /* DATA */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 16)), /* PD_EINT16 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 17),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "lcd0"), /* D17 */
+ SUNXI_FUNCTION(0x3, "lvds1"), /* VNC */
+ SUNXI_FUNCTION(0x4, "sim"), /* RST */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 17)), /* PD_EINT17 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 18),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "lcd0"), /* D18 */
+ SUNXI_FUNCTION(0x3, "lvds1"), /* VP3 */
+ SUNXI_FUNCTION(0x4, "sim"), /* DET */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 18)), /* PD_EINT18 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 19),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "lcd0"), /* D19 */
+ SUNXI_FUNCTION(0x3, "lvds1"), /* VN3 */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 19)), /* PD_EINT19 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 20),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "lcd0"), /* D20 */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 20)), /* PD_EINT20 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 21),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "lcd0"), /* D21 */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 21)), /* PD_EINT21 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 22),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "lcd0"), /* D22 */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 22)), /* PD_EINT22 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 23),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "lcd0"), /* D23 */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 23)), /* PD_EINT23 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 24),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "lcd0"), /* CLK */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 24)), /* PD_EINT24 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 25),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "lcd0"), /* DE */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 25)), /* PD_EINT25 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 26),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "lcd0"), /* HSYNC */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 26)), /* PD_EINT26 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 27),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "lcd0"), /* VSYNC */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 27)), /* PD_EINT27 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 28),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "pwm0"),
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 28)), /* PD_EINT28 */
+ /* Hole */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 0),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "csi"), /* PCLK */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 0)), /* PE_EINT0 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 1),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "csi"), /* MCLK */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 1)), /* PE_EINT1 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 2),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "csi"), /* HSYNC */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 2)), /* PE_EINT2 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 3),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "csi"), /* VSYNC */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 3)), /* PE_EINT3 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 4),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "csi"), /* D0 */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 4)), /* PE_EINT4 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 5),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "csi"), /* D1 */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 5)), /* PE_EINT5 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 6),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "csi"), /* D2 */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 6)), /* PE_EINT6 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 7),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "csi"), /* D3 */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 7)), /* PE_EINT7 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 8),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "csi"), /* D4 */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 8)), /* PE_EINT8 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 9),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "csi"), /* D5 */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 9)), /* PE_EINT9 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 10),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "csi"), /* D6 */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 10)), /* PE_EINT10 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 11),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "csi"), /* D7 */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 11)), /* PE_EINT11 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 12),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "csi"), /* D8 */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 12)), /* PE_EINT12 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 13),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "csi"), /* D9 */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 13)), /* PE_EINT13 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 14),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "csi"), /* D10 */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 14)), /* PE_EINT14 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 15),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "csi"), /* D11 */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 15)), /* PE_EINT15 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 16),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "csi"), /* D12 */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 16)), /* PE_EINT16 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 17),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "csi"), /* D13 */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 17)), /* PE_EINT17 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 18),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "csi"), /* D14 */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 18)), /* PE_EINT18 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 19),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "csi"), /* D15 */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 19)), /* PE_EINT19 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 20),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "csi"), /* SCK */
+ SUNXI_FUNCTION(0x5, "i2c2"), /* SCK */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 20)), /* PE_EINT20 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 21),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "csi"), /* SDA */
+ SUNXI_FUNCTION(0x5, "i2c2"), /* SDA */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 21)), /* PE_EINT21 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 22),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "csi"), /* FSIN0 */
+ SUNXI_FUNCTION(0x4, "tcon0"), /* TRIG0 */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 22)), /* PE_EINT22 */
+ /* Hole */
SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 0),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
diff --git a/drivers/pinctrl/tegra/pinctrl-tegra.c b/drivers/pinctrl/tegra/pinctrl-tegra.c
index 734c71ef00..6bf8db424b 100644
--- a/drivers/pinctrl/tegra/pinctrl-tegra.c
+++ b/drivers/pinctrl/tegra/pinctrl-tegra.c
@@ -120,7 +120,7 @@ static int tegra_pinctrl_dt_subnode_to_map(struct pinctrl_dev *pctldev,
/* EINVAL=missing, which is fine since it's optional */
if (ret != -EINVAL)
dev_err(dev,
- "could not parse property nvidia,function\n");
+ "%pOF: could not parse property nvidia,function\n", np);
function = NULL;
}
@@ -134,8 +134,8 @@ static int tegra_pinctrl_dt_subnode_to_map(struct pinctrl_dev *pctldev,
goto exit;
/* EINVAL=missing, which is fine since it's optional */
} else if (ret != -EINVAL) {
- dev_err(dev, "could not parse property %s\n",
- cfg_params[i].property);
+ dev_err(dev, "%pOF: could not parse property %s\n",
+ np, cfg_params[i].property);
}
}
@@ -146,7 +146,7 @@ static int tegra_pinctrl_dt_subnode_to_map(struct pinctrl_dev *pctldev,
reserve++;
ret = of_property_count_strings(np, "nvidia,pins");
if (ret < 0) {
- dev_err(dev, "could not parse property nvidia,pins\n");
+ dev_err(dev, "%pOF: could not parse property nvidia,pins\n", np);
goto exit;
}
reserve *= ret;
diff --git a/drivers/pinctrl/ti/pinctrl-ti-iodelay.c b/drivers/pinctrl/ti/pinctrl-ti-iodelay.c
index c1477f6578..040f2c46a8 100644
--- a/drivers/pinctrl/ti/pinctrl-ti-iodelay.c
+++ b/drivers/pinctrl/ti/pinctrl-ti-iodelay.c
@@ -14,7 +14,8 @@
#include <linux/io.h>
#include <linux/module.h>
#include <linux/of.h>
-#include <linux/of_device.h>
+#include <linux/platform_device.h>
+#include <linux/property.h>
#include <linux/regmap.h>
#include <linux/seq_file.h>
#include <linux/slab.h>
@@ -822,7 +823,6 @@ static int ti_iodelay_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct device_node *np = of_node_get(dev->of_node);
- const struct of_device_id *match;
struct resource *res;
struct ti_iodelay_device *iod;
int ret = 0;
@@ -833,20 +833,18 @@ static int ti_iodelay_probe(struct platform_device *pdev)
goto exit_out;
}
- match = of_match_device(ti_iodelay_of_match, dev);
- if (!match) {
- ret = -EINVAL;
- dev_err(dev, "No DATA match\n");
- goto exit_out;
- }
-
iod = devm_kzalloc(dev, sizeof(*iod), GFP_KERNEL);
if (!iod) {
ret = -ENOMEM;
goto exit_out;
}
iod->dev = dev;
- iod->reg_data = match->data;
+ iod->reg_data = device_get_match_data(dev);
+ if (!iod->reg_data) {
+ ret = -EINVAL;
+ dev_err(dev, "No DATA match\n");
+ goto exit_out;
+ }
/* So far We can assume there is only 1 bank of registers */
iod->reg_base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
@@ -896,29 +894,22 @@ exit_out:
/**
* ti_iodelay_remove() - standard remove
* @pdev: platform device
- *
- * Return: 0 if all went fine, else appropriate error value.
*/
-static int ti_iodelay_remove(struct platform_device *pdev)
+static void ti_iodelay_remove(struct platform_device *pdev)
{
struct ti_iodelay_device *iod = platform_get_drvdata(pdev);
- if (!iod)
- return 0;
-
if (iod->pctl)
pinctrl_unregister(iod->pctl);
ti_iodelay_pinconf_deinit_dev(iod);
/* Expect other allocations to be freed by devm */
-
- return 0;
}
static struct platform_driver ti_iodelay_driver = {
.probe = ti_iodelay_probe,
- .remove = ti_iodelay_remove,
+ .remove_new = ti_iodelay_remove,
.driver = {
.name = DRIVER_NAME,
.of_match_table = ti_iodelay_of_match,
diff --git a/drivers/pinctrl/uniphier/pinctrl-uniphier-core.c b/drivers/pinctrl/uniphier/pinctrl-uniphier-core.c
index 18d3a4f69e..fbd0fcdb42 100644
--- a/drivers/pinctrl/uniphier/pinctrl-uniphier-core.c
+++ b/drivers/pinctrl/uniphier/pinctrl-uniphier-core.c
@@ -31,7 +31,7 @@ struct uniphier_pinctrl_reg_region {
struct list_head node;
unsigned int base;
unsigned int nregs;
- u32 vals[];
+ u32 vals[] __counted_by(nregs);
};
struct uniphier_pinctrl_priv {
diff --git a/drivers/pinctrl/vt8500/pinctrl-wmt.c b/drivers/pinctrl/vt8500/pinctrl-wmt.c
index 6fac30de1c..fce92111a3 100644
--- a/drivers/pinctrl/vt8500/pinctrl-wmt.c
+++ b/drivers/pinctrl/vt8500/pinctrl-wmt.c
@@ -526,16 +526,11 @@ static void wmt_gpio_set_value(struct gpio_chip *chip, unsigned offset,
wmt_clearbits(data, reg_data_out, BIT(bit));
}
-static int wmt_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
-{
- return pinctrl_gpio_direction_input(chip->base + offset);
-}
-
static int wmt_gpio_direction_output(struct gpio_chip *chip, unsigned offset,
int value)
{
wmt_gpio_set_value(chip, offset, value);
- return pinctrl_gpio_direction_output(chip->base + offset);
+ return pinctrl_gpio_direction_output(chip, offset);
}
static const struct gpio_chip wmt_gpio_chip = {
@@ -544,7 +539,7 @@ static const struct gpio_chip wmt_gpio_chip = {
.request = gpiochip_generic_request,
.free = gpiochip_generic_free,
.get_direction = wmt_gpio_get_direction,
- .direction_input = wmt_gpio_direction_input,
+ .direction_input = pinctrl_gpio_direction_input,
.direction_output = wmt_gpio_direction_output,
.get = wmt_gpio_get_value,
.set = wmt_gpio_set_value,