Adding upstream version 6.7.7.upstream/6.7.7

Signed-off-by: Daniel Baumann <daniel.baumann@progress-linux.org>

1 files changed, 126 insertions, 73 deletions

diff --git a/drivers/pmdomain/mediatek/mt8195-pm-domains.h b/drivers/pmdomain/mediatek/mt8195-pm-domains.h
index d7387ea1b9..59aa031ae6 100644
--- a/drivers/pmdomain/mediatek/mt8195-pm-domains.h
+++ b/drivers/pmdomain/mediatek/mt8195-pm-domains.h
@@ -23,12 +23,14 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8195[] = {
 		.pwr_sta2nd_offs = 0x178,
 		.sram_pdn_bits = GENMASK(8, 8),
 		.sram_pdn_ack_bits = GENMASK(12, 12),
-		.bp_infracfg = {
-			BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_VDNR_PCIE_MAC_P0,
+		.bp_cfg = {
+			BUS_PROT_WR(INFRA,
+				    MT8195_TOP_AXI_PROT_EN_VDNR_PCIE_MAC_P0,
 				    MT8195_TOP_AXI_PROT_EN_VDNR_SET,
 				    MT8195_TOP_AXI_PROT_EN_VDNR_CLR,
 				    MT8195_TOP_AXI_PROT_EN_VDNR_STA1),
-			BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_VDNR_1_PCIE_MAC_P0,
+			BUS_PROT_WR(INFRA,
+				    MT8195_TOP_AXI_PROT_EN_VDNR_1_PCIE_MAC_P0,
 				    MT8195_TOP_AXI_PROT_EN_VDNR_1_SET,
 				    MT8195_TOP_AXI_PROT_EN_VDNR_1_CLR,
 				    MT8195_TOP_AXI_PROT_EN_VDNR_1_STA1),
@@ -42,12 +44,14 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8195[] = {
 		.pwr_sta2nd_offs = 0x178,
 		.sram_pdn_bits = GENMASK(8, 8),
 		.sram_pdn_ack_bits = GENMASK(12, 12),
-		.bp_infracfg = {
-			BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_VDNR_PCIE_MAC_P1,
+		.bp_cfg = {
+			BUS_PROT_WR(INFRA,
+				    MT8195_TOP_AXI_PROT_EN_VDNR_PCIE_MAC_P1,
 				    MT8195_TOP_AXI_PROT_EN_VDNR_SET,
 				    MT8195_TOP_AXI_PROT_EN_VDNR_CLR,
 				    MT8195_TOP_AXI_PROT_EN_VDNR_STA1),
-			BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_VDNR_1_PCIE_MAC_P1,
+			BUS_PROT_WR(INFRA,
+				    MT8195_TOP_AXI_PROT_EN_VDNR_1_PCIE_MAC_P1,
 				    MT8195_TOP_AXI_PROT_EN_VDNR_1_SET,
 				    MT8195_TOP_AXI_PROT_EN_VDNR_1_CLR,
 				    MT8195_TOP_AXI_PROT_EN_VDNR_1_STA1),
@@ -95,8 +99,9 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8195[] = {
 		.pwr_sta2nd_offs = 0x170,
 		.sram_pdn_bits = GENMASK(8, 8),
 		.sram_pdn_ack_bits = GENMASK(12, 12),
-		.bp_infracfg = {
-			BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_2_ADSP,
+		.bp_cfg = {
+			BUS_PROT_WR(INFRA,
+				    MT8195_TOP_AXI_PROT_EN_2_ADSP,
 				    MT8195_TOP_AXI_PROT_EN_2_SET,
 				    MT8195_TOP_AXI_PROT_EN_2_CLR,
 				    MT8195_TOP_AXI_PROT_EN_2_STA1),
@@ -111,8 +116,9 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8195[] = {
 		.pwr_sta2nd_offs = 0x170,
 		.sram_pdn_bits = GENMASK(8, 8),
 		.sram_pdn_ack_bits = GENMASK(12, 12),
-		.bp_infracfg = {
-			BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_2_AUDIO,
+		.bp_cfg = {
+			BUS_PROT_WR(INFRA,
+				    MT8195_TOP_AXI_PROT_EN_2_AUDIO,
 				    MT8195_TOP_AXI_PROT_EN_2_SET,
 				    MT8195_TOP_AXI_PROT_EN_2_CLR,
 				    MT8195_TOP_AXI_PROT_EN_2_STA1),
@@ -136,28 +142,34 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8195[] = {
 		.pwr_sta2nd_offs = 0x178,
 		.sram_pdn_bits = GENMASK(8, 8),
 		.sram_pdn_ack_bits = GENMASK(12, 12),
-		.bp_infracfg = {
-			BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MFG1,
+		.bp_cfg = {
+			BUS_PROT_WR(INFRA,
+				    MT8195_TOP_AXI_PROT_EN_MFG1,
 				    MT8195_TOP_AXI_PROT_EN_SET,
 				    MT8195_TOP_AXI_PROT_EN_CLR,
 				    MT8195_TOP_AXI_PROT_EN_STA1),
-			BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_2_MFG1,
+			BUS_PROT_WR(INFRA,
+				    MT8195_TOP_AXI_PROT_EN_2_MFG1,
 				    MT8195_TOP_AXI_PROT_EN_2_SET,
 				    MT8195_TOP_AXI_PROT_EN_2_CLR,
 				    MT8195_TOP_AXI_PROT_EN_2_STA1),
-			BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_1_MFG1,
+			BUS_PROT_WR(INFRA,
+				    MT8195_TOP_AXI_PROT_EN_1_MFG1,
 				    MT8195_TOP_AXI_PROT_EN_1_SET,
 				    MT8195_TOP_AXI_PROT_EN_1_CLR,
 				    MT8195_TOP_AXI_PROT_EN_1_STA1),
-			BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_2_MFG1_2ND,
+			BUS_PROT_WR(INFRA,
+				    MT8195_TOP_AXI_PROT_EN_2_MFG1_2ND,
 				    MT8195_TOP_AXI_PROT_EN_2_SET,
 				    MT8195_TOP_AXI_PROT_EN_2_CLR,
 				    MT8195_TOP_AXI_PROT_EN_2_STA1),
-			BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MFG1_2ND,
+			BUS_PROT_WR(INFRA,
+				    MT8195_TOP_AXI_PROT_EN_MFG1_2ND,
 				    MT8195_TOP_AXI_PROT_EN_SET,
 				    MT8195_TOP_AXI_PROT_EN_CLR,
 				    MT8195_TOP_AXI_PROT_EN_STA1),
-			BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_MFG1,
+			BUS_PROT_WR(INFRA,
+				    MT8195_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_MFG1,
 				    MT8195_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_SET,
 				    MT8195_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_CLR,
 				    MT8195_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_STA1),
@@ -222,24 +234,29 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8195[] = {
 		.pwr_sta2nd_offs = 0x170,
 		.sram_pdn_bits = GENMASK(8, 8),
 		.sram_pdn_ack_bits = GENMASK(12, 12),
-		.bp_infracfg = {
-			BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_VPPSYS0,
+		.bp_cfg = {
+			BUS_PROT_WR(INFRA,
+				    MT8195_TOP_AXI_PROT_EN_VPPSYS0,
 				    MT8195_TOP_AXI_PROT_EN_SET,
 				    MT8195_TOP_AXI_PROT_EN_CLR,
 				    MT8195_TOP_AXI_PROT_EN_STA1),
-			BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_2_VPPSYS0,
+			BUS_PROT_WR(INFRA,
+				    MT8195_TOP_AXI_PROT_EN_MM_2_VPPSYS0,
 				    MT8195_TOP_AXI_PROT_EN_MM_2_SET,
 				    MT8195_TOP_AXI_PROT_EN_MM_2_CLR,
 				    MT8195_TOP_AXI_PROT_EN_MM_2_STA1),
-			BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_VPPSYS0_2ND,
+			BUS_PROT_WR(INFRA,
+				    MT8195_TOP_AXI_PROT_EN_VPPSYS0_2ND,
 				    MT8195_TOP_AXI_PROT_EN_SET,
 				    MT8195_TOP_AXI_PROT_EN_CLR,
 				    MT8195_TOP_AXI_PROT_EN_STA1),
-			BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_2_VPPSYS0_2ND,
+			BUS_PROT_WR(INFRA,
+				    MT8195_TOP_AXI_PROT_EN_MM_2_VPPSYS0_2ND,
 				    MT8195_TOP_AXI_PROT_EN_MM_2_SET,
 				    MT8195_TOP_AXI_PROT_EN_MM_2_CLR,
 				    MT8195_TOP_AXI_PROT_EN_MM_2_STA1),
-			BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_VPPSYS0,
+			BUS_PROT_WR(INFRA,
+				    MT8195_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_VPPSYS0,
 				    MT8195_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_SET,
 				    MT8195_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_CLR,
 				    MT8195_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_STA1),
@@ -253,16 +270,19 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8195[] = {
 		.pwr_sta2nd_offs = 0x170,
 		.sram_pdn_bits = GENMASK(8, 8),
 		.sram_pdn_ack_bits = GENMASK(12, 12),
-		.bp_infracfg = {
-			BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_VDOSYS0,
+		.bp_cfg = {
+			BUS_PROT_WR(INFRA,
+				    MT8195_TOP_AXI_PROT_EN_MM_VDOSYS0,
 				    MT8195_TOP_AXI_PROT_EN_MM_SET,
 				    MT8195_TOP_AXI_PROT_EN_MM_CLR,
 				    MT8195_TOP_AXI_PROT_EN_MM_STA1),
-			BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_VDOSYS0,
+			BUS_PROT_WR(INFRA,
+				    MT8195_TOP_AXI_PROT_EN_VDOSYS0,
 				    MT8195_TOP_AXI_PROT_EN_SET,
 				    MT8195_TOP_AXI_PROT_EN_CLR,
 				    MT8195_TOP_AXI_PROT_EN_STA1),
-			BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_VDOSYS0,
+			BUS_PROT_WR(INFRA,
+				    MT8195_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_VDOSYS0,
 				    MT8195_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_SET,
 				    MT8195_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_CLR,
 				    MT8195_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_STA1),
@@ -276,16 +296,19 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8195[] = {
 		.pwr_sta2nd_offs = 0x170,
 		.sram_pdn_bits = GENMASK(8, 8),
 		.sram_pdn_ack_bits = GENMASK(12, 12),
-		.bp_infracfg = {
-			BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_VPPSYS1,
+		.bp_cfg = {
+			BUS_PROT_WR(INFRA,
+				    MT8195_TOP_AXI_PROT_EN_MM_VPPSYS1,
 				    MT8195_TOP_AXI_PROT_EN_MM_SET,
 				    MT8195_TOP_AXI_PROT_EN_MM_CLR,
 				    MT8195_TOP_AXI_PROT_EN_MM_STA1),
-			BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_VPPSYS1_2ND,
+			BUS_PROT_WR(INFRA,
+				    MT8195_TOP_AXI_PROT_EN_MM_VPPSYS1_2ND,
 				    MT8195_TOP_AXI_PROT_EN_MM_SET,
 				    MT8195_TOP_AXI_PROT_EN_MM_CLR,
 				    MT8195_TOP_AXI_PROT_EN_MM_STA1),
-			BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_2_VPPSYS1,
+			BUS_PROT_WR(INFRA,
+				    MT8195_TOP_AXI_PROT_EN_MM_2_VPPSYS1,
 				    MT8195_TOP_AXI_PROT_EN_MM_2_SET,
 				    MT8195_TOP_AXI_PROT_EN_MM_2_CLR,
 				    MT8195_TOP_AXI_PROT_EN_MM_2_STA1),
@@ -299,16 +322,19 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8195[] = {
 		.pwr_sta2nd_offs = 0x170,
 		.sram_pdn_bits = GENMASK(8, 8),
 		.sram_pdn_ack_bits = GENMASK(12, 12),
-		.bp_infracfg = {
-			BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_VDOSYS1,
+		.bp_cfg = {
+			BUS_PROT_WR(INFRA,
+				    MT8195_TOP_AXI_PROT_EN_MM_VDOSYS1,
 				    MT8195_TOP_AXI_PROT_EN_MM_SET,
 				    MT8195_TOP_AXI_PROT_EN_MM_CLR,
 				    MT8195_TOP_AXI_PROT_EN_MM_STA1),
-			BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_VDOSYS1_2ND,
+			BUS_PROT_WR(INFRA,
+				    MT8195_TOP_AXI_PROT_EN_MM_VDOSYS1_2ND,
 				    MT8195_TOP_AXI_PROT_EN_MM_SET,
 				    MT8195_TOP_AXI_PROT_EN_MM_CLR,
 				    MT8195_TOP_AXI_PROT_EN_MM_STA1),
-			BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_2_VDOSYS1,
+			BUS_PROT_WR(INFRA,
+				    MT8195_TOP_AXI_PROT_EN_MM_2_VDOSYS1,
 				    MT8195_TOP_AXI_PROT_EN_MM_2_SET,
 				    MT8195_TOP_AXI_PROT_EN_MM_2_CLR,
 				    MT8195_TOP_AXI_PROT_EN_MM_2_STA1),
@@ -322,8 +348,9 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8195[] = {
 		.pwr_sta2nd_offs = 0x170,
 		.sram_pdn_bits = GENMASK(8, 8),
 		.sram_pdn_ack_bits = GENMASK(12, 12),
-		.bp_infracfg = {
-			BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_VDNR_1_DP_TX,
+		.bp_cfg = {
+			BUS_PROT_WR(INFRA,
+				    MT8195_TOP_AXI_PROT_EN_VDNR_1_DP_TX,
 				    MT8195_TOP_AXI_PROT_EN_VDNR_1_SET,
 				    MT8195_TOP_AXI_PROT_EN_VDNR_1_CLR,
 				    MT8195_TOP_AXI_PROT_EN_VDNR_1_STA1),
@@ -338,8 +365,9 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8195[] = {
 		.pwr_sta2nd_offs = 0x170,
 		.sram_pdn_bits = GENMASK(8, 8),
 		.sram_pdn_ack_bits = GENMASK(12, 12),
-		.bp_infracfg = {
-			BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_VDNR_1_EPD_TX,
+		.bp_cfg = {
+			BUS_PROT_WR(INFRA,
+				    MT8195_TOP_AXI_PROT_EN_VDNR_1_EPD_TX,
 				    MT8195_TOP_AXI_PROT_EN_VDNR_1_SET,
 				    MT8195_TOP_AXI_PROT_EN_VDNR_1_CLR,
 				    MT8195_TOP_AXI_PROT_EN_VDNR_1_STA1),
@@ -364,16 +392,19 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8195[] = {
 		.pwr_sta2nd_offs = 0x170,
 		.sram_pdn_bits = GENMASK(8, 8),
 		.sram_pdn_ack_bits = GENMASK(12, 12),
-		.bp_infracfg = {
-			BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_2_WPESYS,
+		.bp_cfg = {
+			BUS_PROT_WR(INFRA,
+				    MT8195_TOP_AXI_PROT_EN_MM_2_WPESYS,
 				    MT8195_TOP_AXI_PROT_EN_MM_2_SET,
 				    MT8195_TOP_AXI_PROT_EN_MM_2_CLR,
 				    MT8195_TOP_AXI_PROT_EN_MM_2_STA1),
-			BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_WPESYS,
+			BUS_PROT_WR(INFRA,
+				    MT8195_TOP_AXI_PROT_EN_MM_WPESYS,
 				    MT8195_TOP_AXI_PROT_EN_MM_SET,
 				    MT8195_TOP_AXI_PROT_EN_MM_CLR,
 				    MT8195_TOP_AXI_PROT_EN_MM_STA1),
-			BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_2_WPESYS_2ND,
+			BUS_PROT_WR(INFRA,
+				    MT8195_TOP_AXI_PROT_EN_MM_2_WPESYS_2ND,
 				    MT8195_TOP_AXI_PROT_EN_MM_2_SET,
 				    MT8195_TOP_AXI_PROT_EN_MM_2_CLR,
 				    MT8195_TOP_AXI_PROT_EN_MM_2_STA1),
@@ -387,20 +418,24 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8195[] = {
 		.pwr_sta2nd_offs = 0x170,
 		.sram_pdn_bits = GENMASK(8, 8),
 		.sram_pdn_ack_bits = GENMASK(12, 12),
-		.bp_infracfg = {
-			BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_VDEC0,
+		.bp_cfg = {
+			BUS_PROT_WR(INFRA,
+				    MT8195_TOP_AXI_PROT_EN_MM_VDEC0,
 				    MT8195_TOP_AXI_PROT_EN_MM_SET,
 				    MT8195_TOP_AXI_PROT_EN_MM_CLR,
 				    MT8195_TOP_AXI_PROT_EN_MM_STA1),
-			BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_2_VDEC0,
+			BUS_PROT_WR(INFRA,
+				    MT8195_TOP_AXI_PROT_EN_MM_2_VDEC0,
 				    MT8195_TOP_AXI_PROT_EN_MM_2_SET,
 				    MT8195_TOP_AXI_PROT_EN_MM_2_CLR,
 				    MT8195_TOP_AXI_PROT_EN_MM_2_STA1),
-			BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_VDEC0_2ND,
+			BUS_PROT_WR(INFRA,
+				    MT8195_TOP_AXI_PROT_EN_MM_VDEC0_2ND,
 				    MT8195_TOP_AXI_PROT_EN_MM_SET,
 				    MT8195_TOP_AXI_PROT_EN_MM_CLR,
 				    MT8195_TOP_AXI_PROT_EN_MM_STA1),
-			BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_2_VDEC0_2ND,
+			BUS_PROT_WR(INFRA,
+				    MT8195_TOP_AXI_PROT_EN_MM_2_VDEC0_2ND,
 				    MT8195_TOP_AXI_PROT_EN_MM_2_SET,
 				    MT8195_TOP_AXI_PROT_EN_MM_2_CLR,
 				    MT8195_TOP_AXI_PROT_EN_MM_2_STA1),
@@ -415,12 +450,14 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8195[] = {
 		.pwr_sta2nd_offs = 0x170,
 		.sram_pdn_bits = GENMASK(8, 8),
 		.sram_pdn_ack_bits = GENMASK(12, 12),
-		.bp_infracfg = {
-			BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_VDEC1,
+		.bp_cfg = {
+			BUS_PROT_WR(INFRA,
+				    MT8195_TOP_AXI_PROT_EN_MM_VDEC1,
 				    MT8195_TOP_AXI_PROT_EN_MM_SET,
 				    MT8195_TOP_AXI_PROT_EN_MM_CLR,
 				    MT8195_TOP_AXI_PROT_EN_MM_STA1),
-			BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_VDEC1_2ND,
+			BUS_PROT_WR(INFRA,
+				    MT8195_TOP_AXI_PROT_EN_MM_VDEC1_2ND,
 				    MT8195_TOP_AXI_PROT_EN_MM_SET,
 				    MT8195_TOP_AXI_PROT_EN_MM_CLR,
 				    MT8195_TOP_AXI_PROT_EN_MM_STA1),
@@ -435,12 +472,14 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8195[] = {
 		.pwr_sta2nd_offs = 0x170,
 		.sram_pdn_bits = GENMASK(8, 8),
 		.sram_pdn_ack_bits = GENMASK(12, 12),
-		.bp_infracfg = {
-			BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_2_VDEC2,
+		.bp_cfg = {
+			BUS_PROT_WR(INFRA,
+				    MT8195_TOP_AXI_PROT_EN_MM_2_VDEC2,
 				    MT8195_TOP_AXI_PROT_EN_MM_2_SET,
 				    MT8195_TOP_AXI_PROT_EN_MM_2_CLR,
 				    MT8195_TOP_AXI_PROT_EN_MM_2_STA1),
-			BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_2_VDEC2_2ND,
+			BUS_PROT_WR(INFRA,
+				    MT8195_TOP_AXI_PROT_EN_MM_2_VDEC2_2ND,
 				    MT8195_TOP_AXI_PROT_EN_MM_2_SET,
 				    MT8195_TOP_AXI_PROT_EN_MM_2_CLR,
 				    MT8195_TOP_AXI_PROT_EN_MM_2_STA1),
@@ -455,16 +494,19 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8195[] = {
 		.pwr_sta2nd_offs = 0x170,
 		.sram_pdn_bits = GENMASK(8, 8),
 		.sram_pdn_ack_bits = GENMASK(12, 12),
-		.bp_infracfg = {
-			BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_VENC,
+		.bp_cfg = {
+			BUS_PROT_WR(INFRA,
+				    MT8195_TOP_AXI_PROT_EN_MM_VENC,
 				    MT8195_TOP_AXI_PROT_EN_MM_SET,
 				    MT8195_TOP_AXI_PROT_EN_MM_CLR,
 				    MT8195_TOP_AXI_PROT_EN_MM_STA1),
-			BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_VENC_2ND,
+			BUS_PROT_WR(INFRA,
+				    MT8195_TOP_AXI_PROT_EN_MM_VENC_2ND,
 				    MT8195_TOP_AXI_PROT_EN_MM_SET,
 				    MT8195_TOP_AXI_PROT_EN_MM_CLR,
 				    MT8195_TOP_AXI_PROT_EN_MM_STA1),
-			BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_2_VENC,
+			BUS_PROT_WR(INFRA,
+				    MT8195_TOP_AXI_PROT_EN_MM_2_VENC,
 				    MT8195_TOP_AXI_PROT_EN_MM_2_SET,
 				    MT8195_TOP_AXI_PROT_EN_MM_2_CLR,
 				    MT8195_TOP_AXI_PROT_EN_MM_2_STA1),
@@ -479,12 +521,14 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8195[] = {
 		.pwr_sta2nd_offs = 0x170,
 		.sram_pdn_bits = GENMASK(8, 8),
 		.sram_pdn_ack_bits = GENMASK(12, 12),
-		.bp_infracfg = {
-			BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_VENC_CORE1,
+		.bp_cfg = {
+			BUS_PROT_WR(INFRA,
+				    MT8195_TOP_AXI_PROT_EN_MM_VENC_CORE1,
 				    MT8195_TOP_AXI_PROT_EN_MM_SET,
 				    MT8195_TOP_AXI_PROT_EN_MM_CLR,
 				    MT8195_TOP_AXI_PROT_EN_MM_STA1),
-			BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_2_VENC_CORE1,
+			BUS_PROT_WR(INFRA,
+				    MT8195_TOP_AXI_PROT_EN_MM_2_VENC_CORE1,
 				    MT8195_TOP_AXI_PROT_EN_MM_2_SET,
 				    MT8195_TOP_AXI_PROT_EN_MM_2_CLR,
 				    MT8195_TOP_AXI_PROT_EN_MM_2_STA1),
@@ -499,12 +543,14 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8195[] = {
 		.pwr_sta2nd_offs = 0x170,
 		.sram_pdn_bits = GENMASK(8, 8),
 		.sram_pdn_ack_bits = GENMASK(12, 12),
-		.bp_infracfg = {
-			BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_IMG,
+		.bp_cfg = {
+			BUS_PROT_WR(INFRA,
+				    MT8195_TOP_AXI_PROT_EN_MM_IMG,
 				    MT8195_TOP_AXI_PROT_EN_MM_SET,
 				    MT8195_TOP_AXI_PROT_EN_MM_CLR,
 				    MT8195_TOP_AXI_PROT_EN_MM_STA1),
-			BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_IMG_2ND,
+			BUS_PROT_WR(INFRA,
+				    MT8195_TOP_AXI_PROT_EN_MM_IMG_2ND,
 				    MT8195_TOP_AXI_PROT_EN_MM_SET,
 				    MT8195_TOP_AXI_PROT_EN_MM_CLR,
 				    MT8195_TOP_AXI_PROT_EN_MM_STA1),
@@ -529,12 +575,14 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8195[] = {
 		.pwr_sta2nd_offs = 0x170,
 		.sram_pdn_bits = GENMASK(8, 8),
 		.sram_pdn_ack_bits = GENMASK(12, 12),
-		.bp_infracfg = {
-			BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_IPE,
+		.bp_cfg = {
+			BUS_PROT_WR(INFRA,
+				    MT8195_TOP_AXI_PROT_EN_MM_IPE,
 				    MT8195_TOP_AXI_PROT_EN_MM_SET,
 				    MT8195_TOP_AXI_PROT_EN_MM_CLR,
 				    MT8195_TOP_AXI_PROT_EN_MM_STA1),
-			BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_2_IPE,
+			BUS_PROT_WR(INFRA,
+				    MT8195_TOP_AXI_PROT_EN_MM_2_IPE,
 				    MT8195_TOP_AXI_PROT_EN_MM_2_SET,
 				    MT8195_TOP_AXI_PROT_EN_MM_2_CLR,
 				    MT8195_TOP_AXI_PROT_EN_MM_2_STA1),
@@ -549,24 +597,29 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8195[] = {
 		.pwr_sta2nd_offs = 0x170,
 		.sram_pdn_bits = GENMASK(8, 8),
 		.sram_pdn_ack_bits = GENMASK(12, 12),
-		.bp_infracfg = {
-			BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_2_CAM,
+		.bp_cfg = {
+			BUS_PROT_WR(INFRA,
+				    MT8195_TOP_AXI_PROT_EN_2_CAM,
 				    MT8195_TOP_AXI_PROT_EN_2_SET,
 				    MT8195_TOP_AXI_PROT_EN_2_CLR,
 				    MT8195_TOP_AXI_PROT_EN_2_STA1),
-			BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_CAM,
+			BUS_PROT_WR(INFRA,
+				    MT8195_TOP_AXI_PROT_EN_MM_CAM,
 				    MT8195_TOP_AXI_PROT_EN_MM_SET,
 				    MT8195_TOP_AXI_PROT_EN_MM_CLR,
 				    MT8195_TOP_AXI_PROT_EN_MM_STA1),
-			BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_1_CAM,
+			BUS_PROT_WR(INFRA,
+				    MT8195_TOP_AXI_PROT_EN_1_CAM,
 				    MT8195_TOP_AXI_PROT_EN_1_SET,
 				    MT8195_TOP_AXI_PROT_EN_1_CLR,
 				    MT8195_TOP_AXI_PROT_EN_1_STA1),
-			BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_CAM_2ND,
+			BUS_PROT_WR(INFRA,
+				    MT8195_TOP_AXI_PROT_EN_MM_CAM_2ND,
 				    MT8195_TOP_AXI_PROT_EN_MM_SET,
 				    MT8195_TOP_AXI_PROT_EN_MM_CLR,
 				    MT8195_TOP_AXI_PROT_EN_MM_STA1),
-			BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_2_CAM,
+			BUS_PROT_WR(INFRA,
+				    MT8195_TOP_AXI_PROT_EN_MM_2_CAM,
 				    MT8195_TOP_AXI_PROT_EN_MM_2_SET,
 				    MT8195_TOP_AXI_PROT_EN_MM_2_CLR,
 				    MT8195_TOP_AXI_PROT_EN_MM_2_STA1),