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| author | Daniel Baumann <daniel.baumann@progress-linux.org> | 2024-05-18 17:35:05 +0000 |
|---|---|---|
| committer | Daniel Baumann <daniel.baumann@progress-linux.org> | 2024-05-18 17:39:31 +0000 |
| commit | 85c675d0d09a45a135bddd15d7b385f8758c32fb (patch) | |
| tree | 76267dbc9b9a130337be3640948fe397b04ac629 /drivers/pwm/Kconfig | |
| parent | Adding upstream version 6.6.15. (diff) | |
| download | linux-85c675d0d09a45a135bddd15d7b385f8758c32fb.tar.xz linux-85c675d0d09a45a135bddd15d7b385f8758c32fb.zip | |
Adding upstream version 6.7.7.upstream/6.7.7
Signed-off-by: Daniel Baumann <daniel.baumann@progress-linux.org>
Diffstat (limited to '')
| -rw-r--r-- | drivers/pwm/Kconfig | 20 |
1 files changed, 15 insertions, 5 deletions
diff --git a/drivers/pwm/Kconfig b/drivers/pwm/Kconfig index 8ebcddf91f..4b956d6617 100644 --- a/drivers/pwm/Kconfig +++ b/drivers/pwm/Kconfig @@ -173,8 +173,8 @@ config PWM_CLPS711X will be called pwm-clps711x. config PWM_CRC - bool "Intel Crystalcove (CRC) PWM support" - depends on X86 && INTEL_SOC_PMIC + tristate "Intel Crystalcove (CRC) PWM support" + depends on INTEL_SOC_PMIC help Generic PWM framework driver for Crystalcove (CRC) PMIC based PWM control. @@ -186,9 +186,19 @@ config PWM_CROS_EC PWM driver for exposing a PWM attached to the ChromeOS Embedded Controller. +config PWM_DWC_CORE + tristate + depends on HAS_IOMEM + help + PWM driver for Synopsys DWC PWM Controller. + + To compile this driver as a module, build the dependecies as + modules, this will be called pwm-dwc-core. + config PWM_DWC - tristate "DesignWare PWM Controller" - depends on PCI + tristate "DesignWare PWM Controller (PCI bus)" + depends on HAS_IOMEM && PCI + select PWM_DWC_CORE help PWM driver for Synopsys DWC PWM Controller attached to a PCI bus. @@ -407,7 +417,7 @@ config PWM_MEDIATEK config PWM_MICROCHIP_CORE tristate "Microchip corePWM PWM support" - depends on SOC_MICROCHIP_POLARFIRE || COMPILE_TEST + depends on ARCH_MICROCHIP_POLARFIRE || COMPILE_TEST depends on HAS_IOMEM && OF help PWM driver for Microchip FPGA soft IP core. |