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| author | Daniel Baumann <daniel.baumann@progress-linux.org> | 2024-04-11 08:27:49 +0000 |
|---|---|---|
| committer | Daniel Baumann <daniel.baumann@progress-linux.org> | 2024-04-11 08:27:49 +0000 |
| commit | ace9429bb58fd418f0c81d4c2835699bddf6bde6 (patch) | |
| tree | b2d64bc10158fdd5497876388cd68142ca374ed3 /include/dt-bindings/clock/r7s72100-clock.h | |
| parent | Initial commit. (diff) | |
| download | linux-ace9429bb58fd418f0c81d4c2835699bddf6bde6.tar.xz linux-ace9429bb58fd418f0c81d4c2835699bddf6bde6.zip | |
Adding upstream version 6.6.15.upstream/6.6.15
Signed-off-by: Daniel Baumann <daniel.baumann@progress-linux.org>
Diffstat (limited to 'include/dt-bindings/clock/r7s72100-clock.h')
| -rw-r--r-- | include/dt-bindings/clock/r7s72100-clock.h | 112 |
1 files changed, 112 insertions, 0 deletions
diff --git a/include/dt-bindings/clock/r7s72100-clock.h b/include/dt-bindings/clock/r7s72100-clock.h new file mode 100644 index 0000000000..a267ac2501 --- /dev/null +++ b/include/dt-bindings/clock/r7s72100-clock.h @@ -0,0 +1,112 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright (C) 2014 Renesas Solutions Corp. + * Copyright (C) 2014 Wolfram Sang, Sang Engineering <wsa@sang-engineering.com> + */ + +#ifndef __DT_BINDINGS_CLOCK_R7S72100_H__ +#define __DT_BINDINGS_CLOCK_R7S72100_H__ + +#define R7S72100_CLK_PLL 0 +#define R7S72100_CLK_I 1 +#define R7S72100_CLK_G 2 + +/* MSTP2 */ +#define R7S72100_CLK_CORESIGHT 0 + +/* MSTP3 */ +#define R7S72100_CLK_IEBUS 7 +#define R7S72100_CLK_IRDA 6 +#define R7S72100_CLK_LIN0 5 +#define R7S72100_CLK_LIN1 4 +#define R7S72100_CLK_MTU2 3 +#define R7S72100_CLK_CAN 2 +#define R7S72100_CLK_ADCPWR 1 +#define R7S72100_CLK_PWM 0 + +/* MSTP4 */ +#define R7S72100_CLK_SCIF0 7 +#define R7S72100_CLK_SCIF1 6 +#define R7S72100_CLK_SCIF2 5 +#define R7S72100_CLK_SCIF3 4 +#define R7S72100_CLK_SCIF4 3 +#define R7S72100_CLK_SCIF5 2 +#define R7S72100_CLK_SCIF6 1 +#define R7S72100_CLK_SCIF7 0 + +/* MSTP5 */ +#define R7S72100_CLK_SCI0 7 +#define R7S72100_CLK_SCI1 6 +#define R7S72100_CLK_SG0 5 +#define R7S72100_CLK_SG1 4 +#define R7S72100_CLK_SG2 3 +#define R7S72100_CLK_SG3 2 +#define R7S72100_CLK_OSTM0 1 +#define R7S72100_CLK_OSTM1 0 + +/* MSTP6 */ +#define R7S72100_CLK_ADC 7 +#define R7S72100_CLK_CEU 6 +#define R7S72100_CLK_DOC0 5 +#define R7S72100_CLK_DOC1 4 +#define R7S72100_CLK_DRC0 3 +#define R7S72100_CLK_DRC1 2 +#define R7S72100_CLK_JCU 1 +#define R7S72100_CLK_RTC 0 + +/* MSTP7 */ +#define R7S72100_CLK_VDEC0 7 +#define R7S72100_CLK_VDEC1 6 +#define R7S72100_CLK_ETHER 4 +#define R7S72100_CLK_NAND 3 +#define R7S72100_CLK_USB0 1 +#define R7S72100_CLK_USB1 0 + +/* MSTP8 */ +#define R7S72100_CLK_IMR0 7 +#define R7S72100_CLK_IMR1 6 +#define R7S72100_CLK_IMRDISP 5 +#define R7S72100_CLK_MMCIF 4 +#define R7S72100_CLK_MLB 3 +#define R7S72100_CLK_ETHAVB 2 +#define R7S72100_CLK_SCUX 1 + +/* MSTP9 */ +#define R7S72100_CLK_I2C0 7 +#define R7S72100_CLK_I2C1 6 +#define R7S72100_CLK_I2C2 5 +#define R7S72100_CLK_I2C3 4 +#define R7S72100_CLK_SPIBSC0 3 +#define R7S72100_CLK_SPIBSC1 2 +#define R7S72100_CLK_VDC50 1 /* and LVDS */ +#define R7S72100_CLK_VDC51 0 + +/* MSTP10 */ +#define R7S72100_CLK_SPI0 7 +#define R7S72100_CLK_SPI1 6 +#define R7S72100_CLK_SPI2 5 +#define R7S72100_CLK_SPI3 4 +#define R7S72100_CLK_SPI4 3 +#define R7S72100_CLK_CDROM 2 +#define R7S72100_CLK_SPDIF 1 +#define R7S72100_CLK_RGPVG2 0 + +/* MSTP11 */ +#define R7S72100_CLK_SSI0 5 +#define R7S72100_CLK_SSI1 4 +#define R7S72100_CLK_SSI2 3 +#define R7S72100_CLK_SSI3 2 +#define R7S72100_CLK_SSI4 1 +#define R7S72100_CLK_SSI5 0 + +/* MSTP12 */ +#define R7S72100_CLK_SDHI00 3 +#define R7S72100_CLK_SDHI01 2 +#define R7S72100_CLK_SDHI10 1 +#define R7S72100_CLK_SDHI11 0 + +/* MSTP13 */ +#define R7S72100_CLK_PIX1 2 +#define R7S72100_CLK_PIX0 1 + +#endif /* __DT_BINDINGS_CLOCK_R7S72100_H__ */ |