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| author | Daniel Baumann <daniel.baumann@progress-linux.org> | 2024-04-11 08:27:49 +0000 |
|---|---|---|
| committer | Daniel Baumann <daniel.baumann@progress-linux.org> | 2024-04-11 08:27:49 +0000 |
| commit | ace9429bb58fd418f0c81d4c2835699bddf6bde6 (patch) | |
| tree | b2d64bc10158fdd5497876388cd68142ca374ed3 /include/dt-bindings/clock/sh73a0-clock.h | |
| parent | Initial commit. (diff) | |
| download | linux-ace9429bb58fd418f0c81d4c2835699bddf6bde6.tar.xz linux-ace9429bb58fd418f0c81d4c2835699bddf6bde6.zip | |
Adding upstream version 6.6.15.upstream/6.6.15
Signed-off-by: Daniel Baumann <daniel.baumann@progress-linux.org>
Diffstat (limited to 'include/dt-bindings/clock/sh73a0-clock.h')
| -rw-r--r-- | include/dt-bindings/clock/sh73a0-clock.h | 82 |
1 files changed, 82 insertions, 0 deletions
diff --git a/include/dt-bindings/clock/sh73a0-clock.h b/include/dt-bindings/clock/sh73a0-clock.h new file mode 100644 index 0000000000..5b544ad7f9 --- /dev/null +++ b/include/dt-bindings/clock/sh73a0-clock.h @@ -0,0 +1,82 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * Copyright 2014 Ulrich Hecht + */ + +#ifndef __DT_BINDINGS_CLOCK_SH73A0_H__ +#define __DT_BINDINGS_CLOCK_SH73A0_H__ + +/* CPG */ +#define SH73A0_CLK_MAIN 0 +#define SH73A0_CLK_PLL0 1 +#define SH73A0_CLK_PLL1 2 +#define SH73A0_CLK_PLL2 3 +#define SH73A0_CLK_PLL3 4 +#define SH73A0_CLK_DSI0PHY 5 +#define SH73A0_CLK_DSI1PHY 6 +#define SH73A0_CLK_ZG 7 +#define SH73A0_CLK_M3 8 +#define SH73A0_CLK_B 9 +#define SH73A0_CLK_M1 10 +#define SH73A0_CLK_M2 11 +#define SH73A0_CLK_Z 12 +#define SH73A0_CLK_ZX 13 +#define SH73A0_CLK_HP 14 + +/* MSTP0 */ +#define SH73A0_CLK_IIC2 1 +#define SH73A0_CLK_MSIOF0 0 + +/* MSTP1 */ +#define SH73A0_CLK_CEU1 29 +#define SH73A0_CLK_CSI2_RX1 28 +#define SH73A0_CLK_CEU0 27 +#define SH73A0_CLK_CSI2_RX0 26 +#define SH73A0_CLK_TMU0 25 +#define SH73A0_CLK_DSITX0 18 +#define SH73A0_CLK_IIC0 16 +#define SH73A0_CLK_SGX 12 +#define SH73A0_CLK_LCDC0 0 + +/* MSTP2 */ +#define SH73A0_CLK_SCIFA7 19 +#define SH73A0_CLK_SY_DMAC 18 +#define SH73A0_CLK_MP_DMAC 17 +#define SH73A0_CLK_MSIOF3 15 +#define SH73A0_CLK_MSIOF1 8 +#define SH73A0_CLK_SCIFA5 7 +#define SH73A0_CLK_SCIFB 6 +#define SH73A0_CLK_MSIOF2 5 +#define SH73A0_CLK_SCIFA0 4 +#define SH73A0_CLK_SCIFA1 3 +#define SH73A0_CLK_SCIFA2 2 +#define SH73A0_CLK_SCIFA3 1 +#define SH73A0_CLK_SCIFA4 0 + +/* MSTP3 */ +#define SH73A0_CLK_SCIFA6 31 +#define SH73A0_CLK_CMT1 29 +#define SH73A0_CLK_FSI 28 +#define SH73A0_CLK_IRDA 25 +#define SH73A0_CLK_IIC1 23 +#define SH73A0_CLK_USB 22 +#define SH73A0_CLK_FLCTL 15 +#define SH73A0_CLK_SDHI0 14 +#define SH73A0_CLK_SDHI1 13 +#define SH73A0_CLK_MMCIF0 12 +#define SH73A0_CLK_SDHI2 11 +#define SH73A0_CLK_TPU0 4 +#define SH73A0_CLK_TPU1 3 +#define SH73A0_CLK_TPU2 2 +#define SH73A0_CLK_TPU3 1 +#define SH73A0_CLK_TPU4 0 + +/* MSTP4 */ +#define SH73A0_CLK_IIC3 11 +#define SH73A0_CLK_IIC4 10 +#define SH73A0_CLK_KEYSC 3 + +/* MSTP5 */ +#define SH73A0_CLK_INTCA0 8 + +#endif |