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author | Daniel Baumann <daniel.baumann@progress-linux.org> | 2024-06-19 21:00:30 +0000 |
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committer | Daniel Baumann <daniel.baumann@progress-linux.org> | 2024-06-19 21:00:30 +0000 |
commit | e54def4ad8144ab15f826416e2e0f290ef1901b4 (patch) | |
tree | 583f8d4bd95cd67c44ff37b878a7eddfca9ab97a /sound/soc/sof/intel/mtl.c | |
parent | Adding upstream version 6.8.12. (diff) | |
download | linux-e54def4ad8144ab15f826416e2e0f290ef1901b4.tar.xz linux-e54def4ad8144ab15f826416e2e0f290ef1901b4.zip |
Adding upstream version 6.9.2.
Signed-off-by: Daniel Baumann <daniel.baumann@progress-linux.org>
Diffstat (limited to 'sound/soc/sof/intel/mtl.c')
-rw-r--r-- | sound/soc/sof/intel/mtl.c | 42 |
1 files changed, 7 insertions, 35 deletions
diff --git a/sound/soc/sof/intel/mtl.c b/sound/soc/sof/intel/mtl.c index 0502376308..060c34988e 100644 --- a/sound/soc/sof/intel/mtl.c +++ b/sound/soc/sof/intel/mtl.c @@ -439,7 +439,7 @@ int mtl_dsp_cl_init(struct snd_sof_dev *sdev, int stream_tag, bool imr_boot) { struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata; const struct sof_intel_dsp_desc *chip = hda->desc; - unsigned int status, target_status; + unsigned int status; u32 ipc_hdr, flags; char *dump_msg; int ret; @@ -485,40 +485,13 @@ int mtl_dsp_cl_init(struct snd_sof_dev *sdev, int stream_tag, bool imr_boot) mtl_enable_ipc_interrupts(sdev); - if (chip->rom_status_reg == MTL_DSP_ROM_STS) { - /* - * Workaround: when the ROM status register is pointing to - * the SRAM window (MTL_DSP_ROM_STS) the platform cannot catch - * ROM_INIT_DONE because of a very short timing window. - * Follow the recommendations and skip target state waiting. - */ - return 0; - } - /* - * step 7: - * - Cold/Full boot: wait for ROM init to proceed to download the firmware - * - IMR boot: wait for ROM firmware entered (firmware booted up from IMR) + * ACE workaround: don't wait for ROM INIT. + * The platform cannot catch ROM_INIT_DONE because of a very short + * timing window. Follow the recommendations and skip this part. */ - if (imr_boot) - target_status = FSR_STATE_FW_ENTERED; - else - target_status = FSR_STATE_INIT_DONE; - ret = snd_sof_dsp_read_poll_timeout(sdev, HDA_DSP_BAR, - chip->rom_status_reg, status, - (FSR_TO_STATE_CODE(status) == target_status), - HDA_DSP_REG_POLL_INTERVAL_US, - chip->rom_init_timeout * - USEC_PER_MSEC); - - if (!ret) - return 0; - - if (hda->boot_iteration == HDA_FW_BOOT_ATTEMPTS) - dev_err(sdev->dev, - "%s: timeout with rom_status_reg (%#x) read\n", - __func__, chip->rom_status_reg); + return 0; err: flags = SOF_DBG_DUMP_PCI | SOF_DBG_DUMP_MBOX | SOF_DBG_DUMP_OPTIONAL; @@ -530,7 +503,6 @@ err: dump_msg = kasprintf(GFP_KERNEL, "Boot iteration failed: %d/%d", hda->boot_iteration, HDA_FW_BOOT_ATTEMPTS); snd_sof_dsp_dbg_dump(sdev, dump_msg, flags); - mtl_enable_interrupts(sdev, false); mtl_dsp_core_power_down(sdev, SOF_DSP_PRIMARY_CORE); kfree(dump_msg); @@ -755,7 +727,7 @@ const struct sof_intel_dsp_desc mtl_chip_info = { .ipc_ack = MTL_DSP_REG_HFIPCXIDA, .ipc_ack_mask = MTL_DSP_REG_HFIPCXIDA_DONE, .ipc_ctl = MTL_DSP_REG_HFIPCXCTL, - .rom_status_reg = MTL_DSP_REG_HFFLGPXQWY, + .rom_status_reg = MTL_DSP_ROM_STS, .rom_init_timeout = 300, .ssp_count = MTL_SSP_COUNT, .ssp_base_offset = CNL_SSP_BASE_OFFSET, @@ -783,7 +755,7 @@ const struct sof_intel_dsp_desc arl_s_chip_info = { .ipc_ack = MTL_DSP_REG_HFIPCXIDA, .ipc_ack_mask = MTL_DSP_REG_HFIPCXIDA_DONE, .ipc_ctl = MTL_DSP_REG_HFIPCXCTL, - .rom_status_reg = MTL_DSP_REG_HFFLGPXQWY, + .rom_status_reg = MTL_DSP_ROM_STS, .rom_init_timeout = 300, .ssp_count = MTL_SSP_COUNT, .ssp_base_offset = CNL_SSP_BASE_OFFSET, |