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authorDaniel Baumann <daniel.baumann@progress-linux.org>2024-04-11 08:27:49 +0000
committerDaniel Baumann <daniel.baumann@progress-linux.org>2024-04-11 08:27:49 +0000
commitace9429bb58fd418f0c81d4c2835699bddf6bde6 (patch)
treeb2d64bc10158fdd5497876388cd68142ca374ed3 /sound/soc/stm
parentInitial commit. (diff)
downloadlinux-ace9429bb58fd418f0c81d4c2835699bddf6bde6.tar.xz
linux-ace9429bb58fd418f0c81d4c2835699bddf6bde6.zip
Adding upstream version 6.6.15.upstream/6.6.15
Signed-off-by: Daniel Baumann <daniel.baumann@progress-linux.org>
Diffstat (limited to '')
-rw-r--r--sound/soc/stm/Kconfig47
-rw-r--r--sound/soc/stm/Makefile18
-rw-r--r--sound/soc/stm/stm32_adfsdm.c409
-rw-r--r--sound/soc/stm/stm32_i2s.c1230
-rw-r--r--sound/soc/stm/stm32_sai.c294
-rw-r--r--sound/soc/stm/stm32_sai.h302
-rw-r--r--sound/soc/stm/stm32_sai_sub.c1634
-rw-r--r--sound/soc/stm/stm32_spdifrx.c1087
8 files changed, 5021 insertions, 0 deletions
diff --git a/sound/soc/stm/Kconfig b/sound/soc/stm/Kconfig
new file mode 100644
index 0000000000..da1f7a1660
--- /dev/null
+++ b/sound/soc/stm/Kconfig
@@ -0,0 +1,47 @@
+# SPDX-License-Identifier: GPL-2.0-only
+menu "STMicroelectronics STM32 SOC audio support"
+
+config SND_SOC_STM32_SAI
+ tristate "STM32 SAI interface (Serial Audio Interface) support"
+ depends on (ARCH_STM32 && OF) || COMPILE_TEST
+ depends on COMMON_CLK
+ depends on SND_SOC
+ select SND_SOC_GENERIC_DMAENGINE_PCM
+ select REGMAP_MMIO
+ select SND_PCM_IEC958
+ help
+ Say Y if you want to enable SAI for STM32
+
+config SND_SOC_STM32_I2S
+ tristate "STM32 I2S interface (SPI/I2S block) support"
+ depends on (ARCH_STM32 && OF) || COMPILE_TEST
+ depends on COMMON_CLK
+ depends on SND_SOC
+ select SND_SOC_GENERIC_DMAENGINE_PCM
+ select REGMAP_MMIO
+ help
+ Say Y if you want to enable I2S for STM32
+
+config SND_SOC_STM32_SPDIFRX
+ tristate "STM32 S/PDIF receiver (SPDIFRX) support"
+ depends on (ARCH_STM32 && OF) || COMPILE_TEST
+ depends on SND_SOC
+ select SND_SOC_GENERIC_DMAENGINE_PCM
+ select REGMAP_MMIO
+ select SND_SOC_SPDIF
+ help
+ Say Y if you want to enable S/PDIF capture for STM32
+
+config SND_SOC_STM32_DFSDM
+ tristate "SoC Audio support for STM32 DFSDM"
+ depends on ARCH_STM32 || COMPILE_TEST
+ depends on SND_SOC
+ depends on STM32_DFSDM_ADC
+ select SND_SOC_GENERIC_DMAENGINE_PCM
+ select SND_SOC_DMIC
+ select IIO_BUFFER_CB
+ help
+ Select this option to enable the STM32 Digital Filter
+ for Sigma Delta Modulators (DFSDM) driver used
+ in various STM32 series for digital microphone capture.
+endmenu
diff --git a/sound/soc/stm/Makefile b/sound/soc/stm/Makefile
new file mode 100644
index 0000000000..3143c0b470
--- /dev/null
+++ b/sound/soc/stm/Makefile
@@ -0,0 +1,18 @@
+# SPDX-License-Identifier: GPL-2.0
+# SAI
+snd-soc-stm32-sai-sub-objs := stm32_sai_sub.o
+obj-$(CONFIG_SND_SOC_STM32_SAI) += snd-soc-stm32-sai-sub.o
+
+snd-soc-stm32-sai-objs := stm32_sai.o
+obj-$(CONFIG_SND_SOC_STM32_SAI) += snd-soc-stm32-sai.o
+
+# I2S
+snd-soc-stm32-i2s-objs := stm32_i2s.o
+obj-$(CONFIG_SND_SOC_STM32_I2S) += snd-soc-stm32-i2s.o
+
+# SPDIFRX
+snd-soc-stm32-spdifrx-objs := stm32_spdifrx.o
+obj-$(CONFIG_SND_SOC_STM32_SPDIFRX) += snd-soc-stm32-spdifrx.o
+
+#DFSDM
+obj-$(CONFIG_SND_SOC_STM32_DFSDM) += stm32_adfsdm.o
diff --git a/sound/soc/stm/stm32_adfsdm.c b/sound/soc/stm/stm32_adfsdm.c
new file mode 100644
index 0000000000..a8fff73786
--- /dev/null
+++ b/sound/soc/stm/stm32_adfsdm.c
@@ -0,0 +1,409 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * This file is part of STM32 DFSDM ASoC DAI driver
+ *
+ * Copyright (C) 2017, STMicroelectronics - All Rights Reserved
+ * Authors: Arnaud Pouliquen <arnaud.pouliquen@st.com>
+ * Olivier Moysan <olivier.moysan@st.com>
+ */
+
+#include <linux/clk.h>
+#include <linux/module.h>
+#include <linux/mutex.h>
+#include <linux/platform_device.h>
+#include <linux/slab.h>
+#include <linux/pm_runtime.h>
+#include <linux/iio/iio.h>
+#include <linux/iio/consumer.h>
+#include <linux/iio/adc/stm32-dfsdm-adc.h>
+
+#include <sound/pcm.h>
+#include <sound/soc.h>
+
+#define STM32_ADFSDM_DRV_NAME "stm32-adfsdm"
+
+#define DFSDM_MAX_PERIOD_SIZE (PAGE_SIZE / 2)
+#define DFSDM_MAX_PERIODS 6
+
+struct stm32_adfsdm_priv {
+ struct snd_soc_dai_driver dai_drv;
+ struct snd_pcm_substream *substream;
+ struct device *dev;
+
+ /* IIO */
+ struct iio_channel *iio_ch;
+ struct iio_cb_buffer *iio_cb;
+ bool iio_active;
+
+ /* PCM buffer */
+ unsigned char *pcm_buff;
+ unsigned int pos;
+
+ struct mutex lock; /* protect against race condition on iio state */
+};
+
+static const struct snd_pcm_hardware stm32_adfsdm_pcm_hw = {
+ .info = SNDRV_PCM_INFO_INTERLEAVED | SNDRV_PCM_INFO_BLOCK_TRANSFER |
+ SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_PAUSE,
+ .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE,
+
+ .channels_min = 1,
+ .channels_max = 1,
+
+ .periods_min = 2,
+ .periods_max = DFSDM_MAX_PERIODS,
+
+ .period_bytes_max = DFSDM_MAX_PERIOD_SIZE,
+ .buffer_bytes_max = DFSDM_MAX_PERIODS * DFSDM_MAX_PERIOD_SIZE
+};
+
+static void stm32_adfsdm_shutdown(struct snd_pcm_substream *substream,
+ struct snd_soc_dai *dai)
+{
+ struct stm32_adfsdm_priv *priv = snd_soc_dai_get_drvdata(dai);
+
+ mutex_lock(&priv->lock);
+ if (priv->iio_active) {
+ iio_channel_stop_all_cb(priv->iio_cb);
+ priv->iio_active = false;
+ }
+ mutex_unlock(&priv->lock);
+}
+
+static int stm32_adfsdm_dai_prepare(struct snd_pcm_substream *substream,
+ struct snd_soc_dai *dai)
+{
+ struct stm32_adfsdm_priv *priv = snd_soc_dai_get_drvdata(dai);
+ int ret;
+
+ mutex_lock(&priv->lock);
+ if (priv->iio_active) {
+ iio_channel_stop_all_cb(priv->iio_cb);
+ priv->iio_active = false;
+ }
+
+ ret = iio_write_channel_attribute(priv->iio_ch,
+ substream->runtime->rate, 0,
+ IIO_CHAN_INFO_SAMP_FREQ);
+ if (ret < 0) {
+ dev_err(dai->dev, "%s: Failed to set %d sampling rate\n",
+ __func__, substream->runtime->rate);
+ goto out;
+ }
+
+ if (!priv->iio_active) {
+ ret = iio_channel_start_all_cb(priv->iio_cb);
+ if (!ret)
+ priv->iio_active = true;
+ else
+ dev_err(dai->dev, "%s: IIO channel start failed (%d)\n",
+ __func__, ret);
+ }
+
+out:
+ mutex_unlock(&priv->lock);
+
+ return ret;
+}
+
+static int stm32_adfsdm_set_sysclk(struct snd_soc_dai *dai, int clk_id,
+ unsigned int freq, int dir)
+{
+ struct stm32_adfsdm_priv *priv = snd_soc_dai_get_drvdata(dai);
+ ssize_t size;
+ char str_freq[10];
+
+ dev_dbg(dai->dev, "%s: Enter for freq %d\n", __func__, freq);
+
+ /* Set IIO frequency if CODEC is master as clock comes from SPI_IN */
+
+ snprintf(str_freq, sizeof(str_freq), "%u\n", freq);
+ size = iio_write_channel_ext_info(priv->iio_ch, "spi_clk_freq",
+ str_freq, sizeof(str_freq));
+ if (size != sizeof(str_freq)) {
+ dev_err(dai->dev, "%s: Failed to set SPI clock\n",
+ __func__);
+ return -EINVAL;
+ }
+ return 0;
+}
+
+static const struct snd_soc_dai_ops stm32_adfsdm_dai_ops = {
+ .shutdown = stm32_adfsdm_shutdown,
+ .prepare = stm32_adfsdm_dai_prepare,
+ .set_sysclk = stm32_adfsdm_set_sysclk,
+};
+
+static const struct snd_soc_dai_driver stm32_adfsdm_dai = {
+ .capture = {
+ .channels_min = 1,
+ .channels_max = 1,
+ .formats = SNDRV_PCM_FMTBIT_S16_LE |
+ SNDRV_PCM_FMTBIT_S32_LE,
+ .rates = SNDRV_PCM_RATE_CONTINUOUS,
+ .rate_min = 8000,
+ .rate_max = 48000,
+ },
+ .ops = &stm32_adfsdm_dai_ops,
+};
+
+static const struct snd_soc_component_driver stm32_adfsdm_dai_component = {
+ .name = "stm32_dfsdm_audio",
+ .legacy_dai_naming = 1,
+};
+
+static void stm32_memcpy_32to16(void *dest, const void *src, size_t n)
+{
+ unsigned int i = 0;
+ u16 *d = (u16 *)dest, *s = (u16 *)src;
+
+ s++;
+ for (i = n >> 1; i > 0; i--) {
+ *d++ = *s++;
+ s++;
+ }
+}
+
+static int stm32_afsdm_pcm_cb(const void *data, size_t size, void *private)
+{
+ struct stm32_adfsdm_priv *priv = private;
+ struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(priv->substream);
+ u8 *pcm_buff = priv->pcm_buff;
+ u8 *src_buff = (u8 *)data;
+ unsigned int old_pos = priv->pos;
+ size_t buff_size = snd_pcm_lib_buffer_bytes(priv->substream);
+ size_t period_size = snd_pcm_lib_period_bytes(priv->substream);
+ size_t cur_size, src_size = size;
+ snd_pcm_format_t format = priv->substream->runtime->format;
+
+ if (format == SNDRV_PCM_FORMAT_S16_LE)
+ src_size >>= 1;
+ cur_size = src_size;
+
+ dev_dbg(rtd->dev, "%s: buff_add :%pK, pos = %d, size = %zu\n",
+ __func__, &pcm_buff[priv->pos], priv->pos, src_size);
+
+ if ((priv->pos + src_size) > buff_size) {
+ if (format == SNDRV_PCM_FORMAT_S16_LE)
+ stm32_memcpy_32to16(&pcm_buff[priv->pos], src_buff,
+ buff_size - priv->pos);
+ else
+ memcpy(&pcm_buff[priv->pos], src_buff,
+ buff_size - priv->pos);
+ cur_size -= buff_size - priv->pos;
+ priv->pos = 0;
+ }
+
+ if (format == SNDRV_PCM_FORMAT_S16_LE)
+ stm32_memcpy_32to16(&pcm_buff[priv->pos],
+ &src_buff[src_size - cur_size], cur_size);
+ else
+ memcpy(&pcm_buff[priv->pos], &src_buff[src_size - cur_size],
+ cur_size);
+
+ priv->pos = (priv->pos + cur_size) % buff_size;
+
+ if (cur_size != src_size || (old_pos && (old_pos % period_size < size)))
+ snd_pcm_period_elapsed(priv->substream);
+
+ return 0;
+}
+
+static int stm32_adfsdm_trigger(struct snd_soc_component *component,
+ struct snd_pcm_substream *substream, int cmd)
+{
+ struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
+ struct stm32_adfsdm_priv *priv =
+ snd_soc_dai_get_drvdata(asoc_rtd_to_cpu(rtd, 0));
+
+ switch (cmd) {
+ case SNDRV_PCM_TRIGGER_START:
+ case SNDRV_PCM_TRIGGER_RESUME:
+ priv->pos = 0;
+ return stm32_dfsdm_get_buff_cb(priv->iio_ch->indio_dev,
+ stm32_afsdm_pcm_cb, priv);
+ case SNDRV_PCM_TRIGGER_SUSPEND:
+ case SNDRV_PCM_TRIGGER_STOP:
+ return stm32_dfsdm_release_buff_cb(priv->iio_ch->indio_dev);
+ }
+
+ return -EINVAL;
+}
+
+static int stm32_adfsdm_pcm_open(struct snd_soc_component *component,
+ struct snd_pcm_substream *substream)
+{
+ struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
+ struct stm32_adfsdm_priv *priv = snd_soc_dai_get_drvdata(asoc_rtd_to_cpu(rtd, 0));
+ int ret;
+
+ ret = snd_soc_set_runtime_hwparams(substream, &stm32_adfsdm_pcm_hw);
+ if (!ret)
+ priv->substream = substream;
+
+ return ret;
+}
+
+static int stm32_adfsdm_pcm_close(struct snd_soc_component *component,
+ struct snd_pcm_substream *substream)
+{
+ struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
+ struct stm32_adfsdm_priv *priv =
+ snd_soc_dai_get_drvdata(asoc_rtd_to_cpu(rtd, 0));
+
+ priv->substream = NULL;
+
+ return 0;
+}
+
+static snd_pcm_uframes_t stm32_adfsdm_pcm_pointer(
+ struct snd_soc_component *component,
+ struct snd_pcm_substream *substream)
+{
+ struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
+ struct stm32_adfsdm_priv *priv =
+ snd_soc_dai_get_drvdata(asoc_rtd_to_cpu(rtd, 0));
+
+ return bytes_to_frames(substream->runtime, priv->pos);
+}
+
+static int stm32_adfsdm_pcm_hw_params(struct snd_soc_component *component,
+ struct snd_pcm_substream *substream,
+ struct snd_pcm_hw_params *params)
+{
+ struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
+ struct stm32_adfsdm_priv *priv =
+ snd_soc_dai_get_drvdata(asoc_rtd_to_cpu(rtd, 0));
+
+ priv->pcm_buff = substream->runtime->dma_area;
+
+ return iio_channel_cb_set_buffer_watermark(priv->iio_cb,
+ params_period_size(params));
+}
+
+static int stm32_adfsdm_pcm_new(struct snd_soc_component *component,
+ struct snd_soc_pcm_runtime *rtd)
+{
+ struct snd_pcm *pcm = rtd->pcm;
+ struct stm32_adfsdm_priv *priv =
+ snd_soc_dai_get_drvdata(asoc_rtd_to_cpu(rtd, 0));
+ unsigned int size = DFSDM_MAX_PERIODS * DFSDM_MAX_PERIOD_SIZE;
+
+ snd_pcm_set_managed_buffer_all(pcm, SNDRV_DMA_TYPE_DEV,
+ priv->dev, size, size);
+ return 0;
+}
+
+static int stm32_adfsdm_dummy_cb(const void *data, void *private)
+{
+ /*
+ * This dummy callback is requested by iio_channel_get_all_cb() API,
+ * but the stm32_dfsdm_get_buff_cb() API is used instead, to optimize
+ * DMA transfers.
+ */
+ return 0;
+}
+
+static void stm32_adfsdm_cleanup(void *data)
+{
+ iio_channel_release_all_cb(data);
+}
+
+static struct snd_soc_component_driver stm32_adfsdm_soc_platform = {
+ .open = stm32_adfsdm_pcm_open,
+ .close = stm32_adfsdm_pcm_close,
+ .hw_params = stm32_adfsdm_pcm_hw_params,
+ .trigger = stm32_adfsdm_trigger,
+ .pointer = stm32_adfsdm_pcm_pointer,
+ .pcm_construct = stm32_adfsdm_pcm_new,
+};
+
+static const struct of_device_id stm32_adfsdm_of_match[] = {
+ {.compatible = "st,stm32h7-dfsdm-dai"},
+ {}
+};
+MODULE_DEVICE_TABLE(of, stm32_adfsdm_of_match);
+
+static int stm32_adfsdm_probe(struct platform_device *pdev)
+{
+ struct stm32_adfsdm_priv *priv;
+ struct snd_soc_component *component;
+ int ret;
+
+ priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
+ if (!priv)
+ return -ENOMEM;
+
+ priv->dev = &pdev->dev;
+ priv->dai_drv = stm32_adfsdm_dai;
+ mutex_init(&priv->lock);
+
+ dev_set_drvdata(&pdev->dev, priv);
+
+ ret = devm_snd_soc_register_component(&pdev->dev,
+ &stm32_adfsdm_dai_component,
+ &priv->dai_drv, 1);
+ if (ret < 0)
+ return ret;
+
+ /* Associate iio channel */
+ priv->iio_ch = devm_iio_channel_get_all(&pdev->dev);
+ if (IS_ERR(priv->iio_ch))
+ return PTR_ERR(priv->iio_ch);
+
+ priv->iio_cb = iio_channel_get_all_cb(&pdev->dev, &stm32_adfsdm_dummy_cb, NULL);
+ if (IS_ERR(priv->iio_cb))
+ return PTR_ERR(priv->iio_cb);
+
+ ret = devm_add_action_or_reset(&pdev->dev, stm32_adfsdm_cleanup, priv->iio_cb);
+ if (ret < 0) {
+ dev_err(&pdev->dev, "Unable to add action\n");
+ return ret;
+ }
+
+ component = devm_kzalloc(&pdev->dev, sizeof(*component), GFP_KERNEL);
+ if (!component)
+ return -ENOMEM;
+
+ ret = snd_soc_component_initialize(component,
+ &stm32_adfsdm_soc_platform,
+ &pdev->dev);
+ if (ret < 0)
+ return ret;
+#ifdef CONFIG_DEBUG_FS
+ component->debugfs_prefix = "pcm";
+#endif
+
+ ret = snd_soc_add_component(component, NULL, 0);
+ if (ret < 0) {
+ dev_err(&pdev->dev, "%s: Failed to register PCM platform\n",
+ __func__);
+ return ret;
+ }
+
+ pm_runtime_enable(&pdev->dev);
+
+ return ret;
+}
+
+static void stm32_adfsdm_remove(struct platform_device *pdev)
+{
+ snd_soc_unregister_component(&pdev->dev);
+ pm_runtime_disable(&pdev->dev);
+}
+
+static struct platform_driver stm32_adfsdm_driver = {
+ .driver = {
+ .name = STM32_ADFSDM_DRV_NAME,
+ .of_match_table = stm32_adfsdm_of_match,
+ },
+ .probe = stm32_adfsdm_probe,
+ .remove_new = stm32_adfsdm_remove,
+};
+
+module_platform_driver(stm32_adfsdm_driver);
+
+MODULE_DESCRIPTION("stm32 DFSDM DAI driver");
+MODULE_AUTHOR("Arnaud Pouliquen <arnaud.pouliquen@st.com>");
+MODULE_LICENSE("GPL v2");
+MODULE_ALIAS("platform:" STM32_ADFSDM_DRV_NAME);
diff --git a/sound/soc/stm/stm32_i2s.c b/sound/soc/stm/stm32_i2s.c
new file mode 100644
index 0000000000..06a42130f5
--- /dev/null
+++ b/sound/soc/stm/stm32_i2s.c
@@ -0,0 +1,1230 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * STM32 ALSA SoC Digital Audio Interface (I2S) driver.
+ *
+ * Copyright (C) 2017, STMicroelectronics - All Rights Reserved
+ * Author(s): Olivier Moysan <olivier.moysan@st.com> for STMicroelectronics.
+ */
+
+#include <linux/bitfield.h>
+#include <linux/clk.h>
+#include <linux/clk-provider.h>
+#include <linux/delay.h>
+#include <linux/module.h>
+#include <linux/of_irq.h>
+#include <linux/of_platform.h>
+#include <linux/pm_runtime.h>
+#include <linux/regmap.h>
+#include <linux/reset.h>
+#include <linux/spinlock.h>
+
+#include <sound/dmaengine_pcm.h>
+#include <sound/pcm_params.h>
+
+#define STM32_I2S_CR1_REG 0x0
+#define STM32_I2S_CFG1_REG 0x08
+#define STM32_I2S_CFG2_REG 0x0C
+#define STM32_I2S_IER_REG 0x10
+#define STM32_I2S_SR_REG 0x14
+#define STM32_I2S_IFCR_REG 0x18
+#define STM32_I2S_TXDR_REG 0X20
+#define STM32_I2S_RXDR_REG 0x30
+#define STM32_I2S_CGFR_REG 0X50
+#define STM32_I2S_HWCFGR_REG 0x3F0
+#define STM32_I2S_VERR_REG 0x3F4
+#define STM32_I2S_IPIDR_REG 0x3F8
+#define STM32_I2S_SIDR_REG 0x3FC
+
+/* Bit definition for SPI2S_CR1 register */
+#define I2S_CR1_SPE BIT(0)
+#define I2S_CR1_CSTART BIT(9)
+#define I2S_CR1_CSUSP BIT(10)
+#define I2S_CR1_HDDIR BIT(11)
+#define I2S_CR1_SSI BIT(12)
+#define I2S_CR1_CRC33_17 BIT(13)
+#define I2S_CR1_RCRCI BIT(14)
+#define I2S_CR1_TCRCI BIT(15)
+
+/* Bit definition for SPI_CFG2 register */
+#define I2S_CFG2_IOSWP_SHIFT 15
+#define I2S_CFG2_IOSWP BIT(I2S_CFG2_IOSWP_SHIFT)
+#define I2S_CFG2_LSBFRST BIT(23)
+#define I2S_CFG2_AFCNTR BIT(31)
+
+/* Bit definition for SPI_CFG1 register */
+#define I2S_CFG1_FTHVL_SHIFT 5
+#define I2S_CFG1_FTHVL_MASK GENMASK(8, I2S_CFG1_FTHVL_SHIFT)
+#define I2S_CFG1_FTHVL_SET(x) ((x) << I2S_CFG1_FTHVL_SHIFT)
+
+#define I2S_CFG1_TXDMAEN BIT(15)
+#define I2S_CFG1_RXDMAEN BIT(14)
+
+/* Bit definition for SPI2S_IER register */
+#define I2S_IER_RXPIE BIT(0)
+#define I2S_IER_TXPIE BIT(1)
+#define I2S_IER_DPXPIE BIT(2)
+#define I2S_IER_EOTIE BIT(3)
+#define I2S_IER_TXTFIE BIT(4)
+#define I2S_IER_UDRIE BIT(5)
+#define I2S_IER_OVRIE BIT(6)
+#define I2S_IER_CRCEIE BIT(7)
+#define I2S_IER_TIFREIE BIT(8)
+#define I2S_IER_MODFIE BIT(9)
+#define I2S_IER_TSERFIE BIT(10)
+
+/* Bit definition for SPI2S_SR register */
+#define I2S_SR_RXP BIT(0)
+#define I2S_SR_TXP BIT(1)
+#define I2S_SR_DPXP BIT(2)
+#define I2S_SR_EOT BIT(3)
+#define I2S_SR_TXTF BIT(4)
+#define I2S_SR_UDR BIT(5)
+#define I2S_SR_OVR BIT(6)
+#define I2S_SR_CRCERR BIT(7)
+#define I2S_SR_TIFRE BIT(8)
+#define I2S_SR_MODF BIT(9)
+#define I2S_SR_TSERF BIT(10)
+#define I2S_SR_SUSP BIT(11)
+#define I2S_SR_TXC BIT(12)
+#define I2S_SR_RXPLVL GENMASK(14, 13)
+#define I2S_SR_RXWNE BIT(15)
+
+#define I2S_SR_MASK GENMASK(15, 0)
+
+/* Bit definition for SPI_IFCR register */
+#define I2S_IFCR_EOTC BIT(3)
+#define I2S_IFCR_TXTFC BIT(4)
+#define I2S_IFCR_UDRC BIT(5)
+#define I2S_IFCR_OVRC BIT(6)
+#define I2S_IFCR_CRCEC BIT(7)
+#define I2S_IFCR_TIFREC BIT(8)
+#define I2S_IFCR_MODFC BIT(9)
+#define I2S_IFCR_TSERFC BIT(10)
+#define I2S_IFCR_SUSPC BIT(11)
+
+#define I2S_IFCR_MASK GENMASK(11, 3)
+
+/* Bit definition for SPI_I2SCGFR register */
+#define I2S_CGFR_I2SMOD BIT(0)
+
+#define I2S_CGFR_I2SCFG_SHIFT 1
+#define I2S_CGFR_I2SCFG_MASK GENMASK(3, I2S_CGFR_I2SCFG_SHIFT)
+#define I2S_CGFR_I2SCFG_SET(x) ((x) << I2S_CGFR_I2SCFG_SHIFT)
+
+#define I2S_CGFR_I2SSTD_SHIFT 4
+#define I2S_CGFR_I2SSTD_MASK GENMASK(5, I2S_CGFR_I2SSTD_SHIFT)
+#define I2S_CGFR_I2SSTD_SET(x) ((x) << I2S_CGFR_I2SSTD_SHIFT)
+
+#define I2S_CGFR_PCMSYNC BIT(7)
+
+#define I2S_CGFR_DATLEN_SHIFT 8
+#define I2S_CGFR_DATLEN_MASK GENMASK(9, I2S_CGFR_DATLEN_SHIFT)
+#define I2S_CGFR_DATLEN_SET(x) ((x) << I2S_CGFR_DATLEN_SHIFT)
+
+#define I2S_CGFR_CHLEN_SHIFT 10
+#define I2S_CGFR_CHLEN BIT(I2S_CGFR_CHLEN_SHIFT)
+#define I2S_CGFR_CKPOL BIT(11)
+#define I2S_CGFR_FIXCH BIT(12)
+#define I2S_CGFR_WSINV BIT(13)
+#define I2S_CGFR_DATFMT BIT(14)
+
+#define I2S_CGFR_I2SDIV_SHIFT 16
+#define I2S_CGFR_I2SDIV_BIT_H 23
+#define I2S_CGFR_I2SDIV_MASK GENMASK(I2S_CGFR_I2SDIV_BIT_H,\
+ I2S_CGFR_I2SDIV_SHIFT)
+#define I2S_CGFR_I2SDIV_SET(x) ((x) << I2S_CGFR_I2SDIV_SHIFT)
+#define I2S_CGFR_I2SDIV_MAX ((1 << (I2S_CGFR_I2SDIV_BIT_H -\
+ I2S_CGFR_I2SDIV_SHIFT)) - 1)
+
+#define I2S_CGFR_ODD_SHIFT 24
+#define I2S_CGFR_ODD BIT(I2S_CGFR_ODD_SHIFT)
+#define I2S_CGFR_MCKOE BIT(25)
+
+/* Registers below apply to I2S version 1.1 and more */
+
+/* Bit definition for SPI_HWCFGR register */
+#define I2S_HWCFGR_I2S_SUPPORT_MASK GENMASK(15, 12)
+
+/* Bit definition for SPI_VERR register */
+#define I2S_VERR_MIN_MASK GENMASK(3, 0)
+#define I2S_VERR_MAJ_MASK GENMASK(7, 4)
+
+/* Bit definition for SPI_IPIDR register */
+#define I2S_IPIDR_ID_MASK GENMASK(31, 0)
+
+/* Bit definition for SPI_SIDR register */
+#define I2S_SIDR_ID_MASK GENMASK(31, 0)
+
+#define I2S_IPIDR_NUMBER 0x00130022
+
+enum i2s_master_mode {
+ I2S_MS_NOT_SET,
+ I2S_MS_MASTER,
+ I2S_MS_SLAVE,
+};
+
+enum i2s_mode {
+ I2S_I2SMOD_TX_SLAVE,
+ I2S_I2SMOD_RX_SLAVE,
+ I2S_I2SMOD_TX_MASTER,
+ I2S_I2SMOD_RX_MASTER,
+ I2S_I2SMOD_FD_SLAVE,
+ I2S_I2SMOD_FD_MASTER,
+};
+
+enum i2s_fifo_th {
+ I2S_FIFO_TH_NONE,
+ I2S_FIFO_TH_ONE_QUARTER,
+ I2S_FIFO_TH_HALF,
+ I2S_FIFO_TH_THREE_QUARTER,
+ I2S_FIFO_TH_FULL,
+};
+
+enum i2s_std {
+ I2S_STD_I2S,
+ I2S_STD_LEFT_J,
+ I2S_STD_RIGHT_J,
+ I2S_STD_DSP,
+};
+
+enum i2s_datlen {
+ I2S_I2SMOD_DATLEN_16,
+ I2S_I2SMOD_DATLEN_24,
+ I2S_I2SMOD_DATLEN_32,
+};
+
+#define STM32_I2S_FIFO_SIZE 16
+
+#define STM32_I2S_IS_MASTER(x) ((x)->ms_flg == I2S_MS_MASTER)
+#define STM32_I2S_IS_SLAVE(x) ((x)->ms_flg == I2S_MS_SLAVE)
+
+#define STM32_I2S_NAME_LEN 32
+#define STM32_I2S_RATE_11K 11025
+
+/**
+ * struct stm32_i2s_data - private data of I2S
+ * @regmap_conf: I2S register map configuration pointer
+ * @regmap: I2S register map pointer
+ * @pdev: device data pointer
+ * @dai_drv: DAI driver pointer
+ * @dma_data_tx: dma configuration data for tx channel
+ * @dma_data_rx: dma configuration data for tx channel
+ * @substream: PCM substream data pointer
+ * @i2sclk: kernel clock feeding the I2S clock generator
+ * @i2smclk: master clock from I2S mclk provider
+ * @pclk: peripheral clock driving bus interface
+ * @x8kclk: I2S parent clock for sampling frequencies multiple of 8kHz
+ * @x11kclk: I2S parent clock for sampling frequencies multiple of 11kHz
+ * @base: mmio register base virtual address
+ * @phys_addr: I2S registers physical base address
+ * @lock_fd: lock to manage race conditions in full duplex mode
+ * @irq_lock: prevent race condition with IRQ
+ * @mclk_rate: master clock frequency (Hz)
+ * @fmt: DAI protocol
+ * @divider: prescaler division ratio
+ * @div: prescaler div field
+ * @odd: prescaler odd field
+ * @refcount: keep count of opened streams on I2S
+ * @ms_flg: master mode flag.
+ */
+struct stm32_i2s_data {
+ const struct regmap_config *regmap_conf;
+ struct regmap *regmap;
+ struct platform_device *pdev;
+ struct snd_soc_dai_driver *dai_drv;
+ struct snd_dmaengine_dai_dma_data dma_data_tx;
+ struct snd_dmaengine_dai_dma_data dma_data_rx;
+ struct snd_pcm_substream *substream;
+ struct clk *i2sclk;
+ struct clk *i2smclk;
+ struct clk *pclk;
+ struct clk *x8kclk;
+ struct clk *x11kclk;
+ void __iomem *base;
+ dma_addr_t phys_addr;
+ spinlock_t lock_fd; /* Manage race conditions for full duplex */
+ spinlock_t irq_lock; /* used to prevent race condition with IRQ */
+ unsigned int mclk_rate;
+ unsigned int fmt;
+ unsigned int divider;
+ unsigned int div;
+ bool odd;
+ int refcount;
+ int ms_flg;
+};
+
+struct stm32_i2smclk_data {
+ struct clk_hw hw;
+ unsigned long freq;
+ struct stm32_i2s_data *i2s_data;
+};
+
+#define to_mclk_data(_hw) container_of(_hw, struct stm32_i2smclk_data, hw)
+
+static int stm32_i2s_calc_clk_div(struct stm32_i2s_data *i2s,
+ unsigned long input_rate,
+ unsigned long output_rate)
+{
+ unsigned int ratio, div, divider = 1;
+ bool odd;
+
+ ratio = DIV_ROUND_CLOSEST(input_rate, output_rate);
+
+ /* Check the parity of the divider */
+ odd = ratio & 0x1;
+
+ /* Compute the div prescaler */
+ div = ratio >> 1;
+
+ /* If div is 0 actual divider is 1 */
+ if (div) {
+ divider = ((2 * div) + odd);
+ dev_dbg(&i2s->pdev->dev, "Divider: 2*%d(div)+%d(odd) = %d\n",
+ div, odd, divider);
+ }
+
+ /* Division by three is not allowed by I2S prescaler */
+ if ((div == 1 && odd) || div > I2S_CGFR_I2SDIV_MAX) {
+ dev_err(&i2s->pdev->dev, "Wrong divider setting\n");
+ return -EINVAL;
+ }
+
+ if (input_rate % divider)
+ dev_dbg(&i2s->pdev->dev,
+ "Rate not accurate. requested (%ld), actual (%ld)\n",
+ output_rate, input_rate / divider);
+
+ i2s->div = div;
+ i2s->odd = odd;
+ i2s->divider = divider;
+
+ return 0;
+}
+
+static int stm32_i2s_set_clk_div(struct stm32_i2s_data *i2s)
+{
+ u32 cgfr, cgfr_mask;
+
+ cgfr = I2S_CGFR_I2SDIV_SET(i2s->div) | (i2s->odd << I2S_CGFR_ODD_SHIFT);
+ cgfr_mask = I2S_CGFR_I2SDIV_MASK | I2S_CGFR_ODD;
+
+ return regmap_update_bits(i2s->regmap, STM32_I2S_CGFR_REG,
+ cgfr_mask, cgfr);
+}
+
+static int stm32_i2s_set_parent_clock(struct stm32_i2s_data *i2s,
+ unsigned int rate)
+{
+ struct platform_device *pdev = i2s->pdev;
+ struct clk *parent_clk;
+ int ret;
+
+ if (!(rate % STM32_I2S_RATE_11K))
+ parent_clk = i2s->x11kclk;
+ else
+ parent_clk = i2s->x8kclk;
+
+ ret = clk_set_parent(i2s->i2sclk, parent_clk);
+ if (ret)
+ dev_err(&pdev->dev,
+ "Error %d setting i2sclk parent clock\n", ret);
+
+ return ret;
+}
+
+static long stm32_i2smclk_round_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long *prate)
+{
+ struct stm32_i2smclk_data *mclk = to_mclk_data(hw);
+ struct stm32_i2s_data *i2s = mclk->i2s_data;
+ int ret;
+
+ ret = stm32_i2s_calc_clk_div(i2s, *prate, rate);
+ if (ret)
+ return ret;
+
+ mclk->freq = *prate / i2s->divider;
+
+ return mclk->freq;
+}
+
+static unsigned long stm32_i2smclk_recalc_rate(struct clk_hw *hw,
+ unsigned long parent_rate)
+{
+ struct stm32_i2smclk_data *mclk = to_mclk_data(hw);
+
+ return mclk->freq;
+}
+
+static int stm32_i2smclk_set_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long parent_rate)
+{
+ struct stm32_i2smclk_data *mclk = to_mclk_data(hw);
+ struct stm32_i2s_data *i2s = mclk->i2s_data;
+ int ret;
+
+ ret = stm32_i2s_calc_clk_div(i2s, parent_rate, rate);
+ if (ret)
+ return ret;
+
+ ret = stm32_i2s_set_clk_div(i2s);
+ if (ret)
+ return ret;
+
+ mclk->freq = rate;
+
+ return 0;
+}
+
+static int stm32_i2smclk_enable(struct clk_hw *hw)
+{
+ struct stm32_i2smclk_data *mclk = to_mclk_data(hw);
+ struct stm32_i2s_data *i2s = mclk->i2s_data;
+
+ dev_dbg(&i2s->pdev->dev, "Enable master clock\n");
+
+ return regmap_update_bits(i2s->regmap, STM32_I2S_CGFR_REG,
+ I2S_CGFR_MCKOE, I2S_CGFR_MCKOE);
+}
+
+static void stm32_i2smclk_disable(struct clk_hw *hw)
+{
+ struct stm32_i2smclk_data *mclk = to_mclk_data(hw);
+ struct stm32_i2s_data *i2s = mclk->i2s_data;
+
+ dev_dbg(&i2s->pdev->dev, "Disable master clock\n");
+
+ regmap_update_bits(i2s->regmap, STM32_I2S_CGFR_REG, I2S_CGFR_MCKOE, 0);
+}
+
+static const struct clk_ops mclk_ops = {
+ .enable = stm32_i2smclk_enable,
+ .disable = stm32_i2smclk_disable,
+ .recalc_rate = stm32_i2smclk_recalc_rate,
+ .round_rate = stm32_i2smclk_round_rate,
+ .set_rate = stm32_i2smclk_set_rate,
+};
+
+static int stm32_i2s_add_mclk_provider(struct stm32_i2s_data *i2s)
+{
+ struct clk_hw *hw;
+ struct stm32_i2smclk_data *mclk;
+ struct device *dev = &i2s->pdev->dev;
+ const char *pname = __clk_get_name(i2s->i2sclk);
+ char *mclk_name, *p, *s = (char *)pname;
+ int ret, i = 0;
+
+ mclk = devm_kzalloc(dev, sizeof(*mclk), GFP_KERNEL);
+ if (!mclk)
+ return -ENOMEM;
+
+ mclk_name = devm_kcalloc(dev, sizeof(char),
+ STM32_I2S_NAME_LEN, GFP_KERNEL);
+ if (!mclk_name)
+ return -ENOMEM;
+
+ /*
+ * Forge mclk clock name from parent clock name and suffix.
+ * String after "_" char is stripped in parent name.
+ */
+ p = mclk_name;
+ while (*s && *s != '_' && (i < (STM32_I2S_NAME_LEN - 7))) {
+ *p++ = *s++;
+ i++;
+ }
+ strcat(p, "_mclk");
+
+ mclk->hw.init = CLK_HW_INIT(mclk_name, pname, &mclk_ops, 0);
+ mclk->i2s_data = i2s;
+ hw = &mclk->hw;
+
+ dev_dbg(dev, "Register master clock %s\n", mclk_name);
+ ret = devm_clk_hw_register(&i2s->pdev->dev, hw);
+ if (ret) {
+ dev_err(dev, "mclk register fails with error %d\n", ret);
+ return ret;
+ }
+ i2s->i2smclk = hw->clk;
+
+ /* register mclk provider */
+ return devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get, hw);
+}
+
+static irqreturn_t stm32_i2s_isr(int irq, void *devid)
+{
+ struct stm32_i2s_data *i2s = (struct stm32_i2s_data *)devid;
+ struct platform_device *pdev = i2s->pdev;
+ u32 sr, ier;
+ unsigned long flags;
+ int err = 0;
+
+ regmap_read(i2s->regmap, STM32_I2S_SR_REG, &sr);
+ regmap_read(i2s->regmap, STM32_I2S_IER_REG, &ier);
+
+ flags = sr & ier;
+ if (!flags) {
+ dev_dbg(&pdev->dev, "Spurious IRQ sr=0x%08x, ier=0x%08x\n",
+ sr, ier);
+ return IRQ_NONE;
+ }
+
+ regmap_write_bits(i2s->regmap, STM32_I2S_IFCR_REG,
+ I2S_IFCR_MASK, flags);
+
+ if (flags & I2S_SR_OVR) {
+ dev_dbg(&pdev->dev, "Overrun\n");
+ err = 1;
+ }
+
+ if (flags & I2S_SR_UDR) {
+ dev_dbg(&pdev->dev, "Underrun\n");
+ err = 1;
+ }
+
+ if (flags & I2S_SR_TIFRE)
+ dev_dbg(&pdev->dev, "Frame error\n");
+
+ spin_lock(&i2s->irq_lock);
+ if (err && i2s->substream)
+ snd_pcm_stop_xrun(i2s->substream);
+ spin_unlock(&i2s->irq_lock);
+
+ return IRQ_HANDLED;
+}
+
+static bool stm32_i2s_readable_reg(struct device *dev, unsigned int reg)
+{
+ switch (reg) {
+ case STM32_I2S_CR1_REG:
+ case STM32_I2S_CFG1_REG:
+ case STM32_I2S_CFG2_REG:
+ case STM32_I2S_IER_REG:
+ case STM32_I2S_SR_REG:
+ case STM32_I2S_RXDR_REG:
+ case STM32_I2S_CGFR_REG:
+ case STM32_I2S_HWCFGR_REG:
+ case STM32_I2S_VERR_REG:
+ case STM32_I2S_IPIDR_REG:
+ case STM32_I2S_SIDR_REG:
+ return true;
+ default:
+ return false;
+ }
+}
+
+static bool stm32_i2s_volatile_reg(struct device *dev, unsigned int reg)
+{
+ switch (reg) {
+ case STM32_I2S_SR_REG:
+ case STM32_I2S_RXDR_REG:
+ return true;
+ default:
+ return false;
+ }
+}
+
+static bool stm32_i2s_writeable_reg(struct device *dev, unsigned int reg)
+{
+ switch (reg) {
+ case STM32_I2S_CR1_REG:
+ case STM32_I2S_CFG1_REG:
+ case STM32_I2S_CFG2_REG:
+ case STM32_I2S_IER_REG:
+ case STM32_I2S_IFCR_REG:
+ case STM32_I2S_TXDR_REG:
+ case STM32_I2S_CGFR_REG:
+ return true;
+ default:
+ return false;
+ }
+}
+
+static int stm32_i2s_set_dai_fmt(struct snd_soc_dai *cpu_dai, unsigned int fmt)
+{
+ struct stm32_i2s_data *i2s = snd_soc_dai_get_drvdata(cpu_dai);
+ u32 cgfr;
+ u32 cgfr_mask = I2S_CGFR_I2SSTD_MASK | I2S_CGFR_CKPOL |
+ I2S_CGFR_WSINV | I2S_CGFR_I2SCFG_MASK;
+
+ dev_dbg(cpu_dai->dev, "fmt %x\n", fmt);
+
+ /*
+ * winv = 0 : default behavior (high/low) for all standards
+ * ckpol = 0 for all standards.
+ */
+ switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
+ case SND_SOC_DAIFMT_I2S:
+ cgfr = I2S_CGFR_I2SSTD_SET(I2S_STD_I2S);
+ break;
+ case SND_SOC_DAIFMT_MSB:
+ cgfr = I2S_CGFR_I2SSTD_SET(I2S_STD_LEFT_J);
+ break;
+ case SND_SOC_DAIFMT_LSB:
+ cgfr = I2S_CGFR_I2SSTD_SET(I2S_STD_RIGHT_J);
+ break;
+ case SND_SOC_DAIFMT_DSP_A:
+ cgfr = I2S_CGFR_I2SSTD_SET(I2S_STD_DSP);
+ break;
+ /* DSP_B not mapped on I2S PCM long format. 1 bit offset does not fit */
+ default:
+ dev_err(cpu_dai->dev, "Unsupported protocol %#x\n",
+ fmt & SND_SOC_DAIFMT_FORMAT_MASK);
+ return -EINVAL;
+ }
+
+ /* DAI clock strobing */
+ switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
+ case SND_SOC_DAIFMT_NB_NF:
+ break;
+ case SND_SOC_DAIFMT_IB_NF:
+ cgfr |= I2S_CGFR_CKPOL;
+ break;
+ case SND_SOC_DAIFMT_NB_IF:
+ cgfr |= I2S_CGFR_WSINV;
+ break;
+ case SND_SOC_DAIFMT_IB_IF:
+ cgfr |= I2S_CGFR_CKPOL;
+ cgfr |= I2S_CGFR_WSINV;
+ break;
+ default:
+ dev_err(cpu_dai->dev, "Unsupported strobing %#x\n",
+ fmt & SND_SOC_DAIFMT_INV_MASK);
+ return -EINVAL;
+ }
+
+ /* DAI clock master masks */
+ switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) {
+ case SND_SOC_DAIFMT_BC_FC:
+ i2s->ms_flg = I2S_MS_SLAVE;
+ break;
+ case SND_SOC_DAIFMT_BP_FP:
+ i2s->ms_flg = I2S_MS_MASTER;
+ break;
+ default:
+ dev_err(cpu_dai->dev, "Unsupported mode %#x\n",
+ fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK);
+ return -EINVAL;
+ }
+
+ i2s->fmt = fmt;
+ return regmap_update_bits(i2s->regmap, STM32_I2S_CGFR_REG,
+ cgfr_mask, cgfr);
+}
+
+static int stm32_i2s_set_sysclk(struct snd_soc_dai *cpu_dai,
+ int clk_id, unsigned int freq, int dir)
+{
+ struct stm32_i2s_data *i2s = snd_soc_dai_get_drvdata(cpu_dai);
+ int ret = 0;
+
+ dev_dbg(cpu_dai->dev, "I2S MCLK frequency is %uHz. mode: %s, dir: %s\n",
+ freq, STM32_I2S_IS_MASTER(i2s) ? "master" : "slave",
+ dir ? "output" : "input");
+
+ /* MCLK generation is available only in master mode */
+ if (dir == SND_SOC_CLOCK_OUT && STM32_I2S_IS_MASTER(i2s)) {
+ if (!i2s->i2smclk) {
+ dev_dbg(cpu_dai->dev, "No MCLK registered\n");
+ return 0;
+ }
+
+ /* Assume shutdown if requested frequency is 0Hz */
+ if (!freq) {
+ /* Release mclk rate only if rate was actually set */
+ if (i2s->mclk_rate) {
+ clk_rate_exclusive_put(i2s->i2smclk);
+ i2s->mclk_rate = 0;
+ }
+ return regmap_update_bits(i2s->regmap,
+ STM32_I2S_CGFR_REG,
+ I2S_CGFR_MCKOE, 0);
+ }
+ /* If master clock is used, set parent clock now */
+ ret = stm32_i2s_set_parent_clock(i2s, freq);
+ if (ret)
+ return ret;
+ ret = clk_set_rate_exclusive(i2s->i2smclk, freq);
+ if (ret) {
+ dev_err(cpu_dai->dev, "Could not set mclk rate\n");
+ return ret;
+ }
+ ret = regmap_update_bits(i2s->regmap, STM32_I2S_CGFR_REG,
+ I2S_CGFR_MCKOE, I2S_CGFR_MCKOE);
+ if (!ret)
+ i2s->mclk_rate = freq;
+ }
+
+ return ret;
+}
+
+static int stm32_i2s_configure_clock(struct snd_soc_dai *cpu_dai,
+ struct snd_pcm_hw_params *params)
+{
+ struct stm32_i2s_data *i2s = snd_soc_dai_get_drvdata(cpu_dai);
+ unsigned long i2s_clock_rate;
+ unsigned int nb_bits, frame_len;
+ unsigned int rate = params_rate(params);
+ u32 cgfr;
+ int ret;
+
+ if (!(rate % 11025))
+ clk_set_parent(i2s->i2sclk, i2s->x11kclk);
+ else
+ clk_set_parent(i2s->i2sclk, i2s->x8kclk);
+ i2s_clock_rate = clk_get_rate(i2s->i2sclk);
+
+ /*
+ * mckl = mclk_ratio x ws
+ * i2s mode : mclk_ratio = 256
+ * dsp mode : mclk_ratio = 128
+ *
+ * mclk on
+ * i2s mode : div = i2s_clk / (mclk_ratio * ws)
+ * dsp mode : div = i2s_clk / (mclk_ratio * ws)
+ * mclk off
+ * i2s mode : div = i2s_clk / (nb_bits x ws)
+ * dsp mode : div = i2s_clk / (nb_bits x ws)
+ */
+ if (i2s->mclk_rate) {
+ ret = stm32_i2s_calc_clk_div(i2s, i2s_clock_rate,
+ i2s->mclk_rate);
+ if (ret)
+ return ret;
+ } else {
+ frame_len = 32;
+ if ((i2s->fmt & SND_SOC_DAIFMT_FORMAT_MASK) ==
+ SND_SOC_DAIFMT_DSP_A)
+ frame_len = 16;
+
+ /* master clock not enabled */
+ ret = regmap_read(i2s->regmap, STM32_I2S_CGFR_REG, &cgfr);
+ if (ret < 0)
+ return ret;
+
+ nb_bits = frame_len * (FIELD_GET(I2S_CGFR_CHLEN, cgfr) + 1);
+ ret = stm32_i2s_calc_clk_div(i2s, i2s_clock_rate,
+ (nb_bits * rate));
+ if (ret)
+ return ret;
+ }
+
+ ret = stm32_i2s_set_clk_div(i2s);
+ if (ret < 0)
+ return ret;
+
+ /* Set bitclock and frameclock to their inactive state */
+ return regmap_update_bits(i2s->regmap, STM32_I2S_CFG2_REG,
+ I2S_CFG2_AFCNTR, I2S_CFG2_AFCNTR);
+}
+
+static int stm32_i2s_configure(struct snd_soc_dai *cpu_dai,
+ struct snd_pcm_hw_params *params,
+ struct snd_pcm_substream *substream)
+{
+ struct stm32_i2s_data *i2s = snd_soc_dai_get_drvdata(cpu_dai);
+ int format = params_width(params);
+ u32 cfgr, cfgr_mask, cfg1;
+ unsigned int fthlv;
+ int ret;
+
+ switch (format) {
+ case 16:
+ cfgr = I2S_CGFR_DATLEN_SET(I2S_I2SMOD_DATLEN_16);
+ cfgr_mask = I2S_CGFR_DATLEN_MASK | I2S_CGFR_CHLEN;
+ break;
+ case 32:
+ cfgr = I2S_CGFR_DATLEN_SET(I2S_I2SMOD_DATLEN_32) |
+ I2S_CGFR_CHLEN;
+ cfgr_mask = I2S_CGFR_DATLEN_MASK | I2S_CGFR_CHLEN;
+ break;
+ default:
+ dev_err(cpu_dai->dev, "Unexpected format %d", format);
+ return -EINVAL;
+ }
+
+ if (STM32_I2S_IS_SLAVE(i2s)) {
+ cfgr |= I2S_CGFR_I2SCFG_SET(I2S_I2SMOD_FD_SLAVE);
+
+ /* As data length is either 16 or 32 bits, fixch always set */
+ cfgr |= I2S_CGFR_FIXCH;
+ cfgr_mask |= I2S_CGFR_FIXCH;
+ } else {
+ cfgr |= I2S_CGFR_I2SCFG_SET(I2S_I2SMOD_FD_MASTER);
+ }
+ cfgr_mask |= I2S_CGFR_I2SCFG_MASK;
+
+ ret = regmap_update_bits(i2s->regmap, STM32_I2S_CGFR_REG,
+ cfgr_mask, cfgr);
+ if (ret < 0)
+ return ret;
+
+ fthlv = STM32_I2S_FIFO_SIZE * I2S_FIFO_TH_ONE_QUARTER / 4;
+ cfg1 = I2S_CFG1_FTHVL_SET(fthlv - 1);
+
+ return regmap_update_bits(i2s->regmap, STM32_I2S_CFG1_REG,
+ I2S_CFG1_FTHVL_MASK, cfg1);
+}
+
+static int stm32_i2s_startup(struct snd_pcm_substream *substream,
+ struct snd_soc_dai *cpu_dai)
+{
+ struct stm32_i2s_data *i2s = snd_soc_dai_get_drvdata(cpu_dai);
+ unsigned long flags;
+ int ret;
+
+ spin_lock_irqsave(&i2s->irq_lock, flags);
+ i2s->substream = substream;
+ spin_unlock_irqrestore(&i2s->irq_lock, flags);
+
+ if ((i2s->fmt & SND_SOC_DAIFMT_FORMAT_MASK) != SND_SOC_DAIFMT_DSP_A)
+ snd_pcm_hw_constraint_single(substream->runtime,
+ SNDRV_PCM_HW_PARAM_CHANNELS, 2);
+
+ ret = clk_prepare_enable(i2s->i2sclk);
+ if (ret < 0) {
+ dev_err(cpu_dai->dev, "Failed to enable clock: %d\n", ret);
+ return ret;
+ }
+
+ return regmap_write_bits(i2s->regmap, STM32_I2S_IFCR_REG,
+ I2S_IFCR_MASK, I2S_IFCR_MASK);
+}
+
+static int stm32_i2s_hw_params(struct snd_pcm_substream *substream,
+ struct snd_pcm_hw_params *params,
+ struct snd_soc_dai *cpu_dai)
+{
+ struct stm32_i2s_data *i2s = snd_soc_dai_get_drvdata(cpu_dai);
+ int ret;
+
+ ret = stm32_i2s_configure(cpu_dai, params, substream);
+ if (ret < 0) {
+ dev_err(cpu_dai->dev, "Configuration returned error %d\n", ret);
+ return ret;
+ }
+
+ if (STM32_I2S_IS_MASTER(i2s))
+ ret = stm32_i2s_configure_clock(cpu_dai, params);
+
+ return ret;
+}
+
+static int stm32_i2s_trigger(struct snd_pcm_substream *substream, int cmd,
+ struct snd_soc_dai *cpu_dai)
+{
+ struct stm32_i2s_data *i2s = snd_soc_dai_get_drvdata(cpu_dai);
+ bool playback_flg = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK);
+ u32 cfg1_mask, ier;
+ int ret;
+
+ switch (cmd) {
+ case SNDRV_PCM_TRIGGER_START:
+ case SNDRV_PCM_TRIGGER_RESUME:
+ case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
+ /* Enable i2s */
+ dev_dbg(cpu_dai->dev, "start I2S %s\n",
+ playback_flg ? "playback" : "capture");
+
+ cfg1_mask = I2S_CFG1_RXDMAEN | I2S_CFG1_TXDMAEN;
+ regmap_update_bits(i2s->regmap, STM32_I2S_CFG1_REG,
+ cfg1_mask, cfg1_mask);
+
+ ret = regmap_update_bits(i2s->regmap, STM32_I2S_CR1_REG,
+ I2S_CR1_SPE, I2S_CR1_SPE);
+ if (ret < 0) {
+ dev_err(cpu_dai->dev, "Error %d enabling I2S\n", ret);
+ return ret;
+ }
+
+ ret = regmap_write_bits(i2s->regmap, STM32_I2S_CR1_REG,
+ I2S_CR1_CSTART, I2S_CR1_CSTART);
+ if (ret < 0) {
+ dev_err(cpu_dai->dev, "Error %d starting I2S\n", ret);
+ return ret;
+ }
+
+ regmap_write_bits(i2s->regmap, STM32_I2S_IFCR_REG,
+ I2S_IFCR_MASK, I2S_IFCR_MASK);
+
+ spin_lock(&i2s->lock_fd);
+ i2s->refcount++;
+ if (playback_flg) {
+ ier = I2S_IER_UDRIE;
+ } else {
+ ier = I2S_IER_OVRIE;
+
+ if (STM32_I2S_IS_MASTER(i2s) && i2s->refcount == 1)
+ /* dummy write to gate bus clocks */
+ regmap_write(i2s->regmap,
+ STM32_I2S_TXDR_REG, 0);
+ }
+ spin_unlock(&i2s->lock_fd);
+
+ if (STM32_I2S_IS_SLAVE(i2s))
+ ier |= I2S_IER_TIFREIE;
+
+ regmap_update_bits(i2s->regmap, STM32_I2S_IER_REG, ier, ier);
+ break;
+ case SNDRV_PCM_TRIGGER_STOP:
+ case SNDRV_PCM_TRIGGER_SUSPEND:
+ case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
+ dev_dbg(cpu_dai->dev, "stop I2S %s\n",
+ playback_flg ? "playback" : "capture");
+
+ if (playback_flg)
+ regmap_update_bits(i2s->regmap, STM32_I2S_IER_REG,
+ I2S_IER_UDRIE,
+ (unsigned int)~I2S_IER_UDRIE);
+ else
+ regmap_update_bits(i2s->regmap, STM32_I2S_IER_REG,
+ I2S_IER_OVRIE,
+ (unsigned int)~I2S_IER_OVRIE);
+
+ spin_lock(&i2s->lock_fd);
+ i2s->refcount--;
+ if (i2s->refcount) {
+ spin_unlock(&i2s->lock_fd);
+ break;
+ }
+
+ ret = regmap_update_bits(i2s->regmap, STM32_I2S_CR1_REG,
+ I2S_CR1_SPE, 0);
+ if (ret < 0) {
+ dev_err(cpu_dai->dev, "Error %d disabling I2S\n", ret);
+ spin_unlock(&i2s->lock_fd);
+ return ret;
+ }
+ spin_unlock(&i2s->lock_fd);
+
+ cfg1_mask = I2S_CFG1_RXDMAEN | I2S_CFG1_TXDMAEN;
+ regmap_update_bits(i2s->regmap, STM32_I2S_CFG1_REG,
+ cfg1_mask, 0);
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+static void stm32_i2s_shutdown(struct snd_pcm_substream *substream,
+ struct snd_soc_dai *cpu_dai)
+{
+ struct stm32_i2s_data *i2s = snd_soc_dai_get_drvdata(cpu_dai);
+ unsigned long flags;
+
+ clk_disable_unprepare(i2s->i2sclk);
+
+ spin_lock_irqsave(&i2s->irq_lock, flags);
+ i2s->substream = NULL;
+ spin_unlock_irqrestore(&i2s->irq_lock, flags);
+}
+
+static int stm32_i2s_dai_probe(struct snd_soc_dai *cpu_dai)
+{
+ struct stm32_i2s_data *i2s = dev_get_drvdata(cpu_dai->dev);
+ struct snd_dmaengine_dai_dma_data *dma_data_tx = &i2s->dma_data_tx;
+ struct snd_dmaengine_dai_dma_data *dma_data_rx = &i2s->dma_data_rx;
+
+ /* Buswidth will be set by framework */
+ dma_data_tx->addr_width = DMA_SLAVE_BUSWIDTH_UNDEFINED;
+ dma_data_tx->addr = (dma_addr_t)(i2s->phys_addr) + STM32_I2S_TXDR_REG;
+ dma_data_tx->maxburst = 1;
+ dma_data_rx->addr_width = DMA_SLAVE_BUSWIDTH_UNDEFINED;
+ dma_data_rx->addr = (dma_addr_t)(i2s->phys_addr) + STM32_I2S_RXDR_REG;
+ dma_data_rx->maxburst = 1;
+
+ snd_soc_dai_init_dma_data(cpu_dai, dma_data_tx, dma_data_rx);
+
+ return 0;
+}
+
+static const struct regmap_config stm32_h7_i2s_regmap_conf = {
+ .reg_bits = 32,
+ .reg_stride = 4,
+ .val_bits = 32,
+ .max_register = STM32_I2S_SIDR_REG,
+ .readable_reg = stm32_i2s_readable_reg,
+ .volatile_reg = stm32_i2s_volatile_reg,
+ .writeable_reg = stm32_i2s_writeable_reg,
+ .num_reg_defaults_raw = STM32_I2S_SIDR_REG / sizeof(u32) + 1,
+ .fast_io = true,
+ .cache_type = REGCACHE_FLAT,
+};
+
+static const struct snd_soc_dai_ops stm32_i2s_pcm_dai_ops = {
+ .probe = stm32_i2s_dai_probe,
+ .set_sysclk = stm32_i2s_set_sysclk,
+ .set_fmt = stm32_i2s_set_dai_fmt,
+ .startup = stm32_i2s_startup,
+ .hw_params = stm32_i2s_hw_params,
+ .trigger = stm32_i2s_trigger,
+ .shutdown = stm32_i2s_shutdown,
+};
+
+static const struct snd_pcm_hardware stm32_i2s_pcm_hw = {
+ .info = SNDRV_PCM_INFO_INTERLEAVED | SNDRV_PCM_INFO_MMAP,
+ .buffer_bytes_max = 8 * PAGE_SIZE,
+ .period_bytes_min = 1024,
+ .period_bytes_max = 4 * PAGE_SIZE,
+ .periods_min = 2,
+ .periods_max = 8,
+};
+
+static const struct snd_dmaengine_pcm_config stm32_i2s_pcm_config = {
+ .pcm_hardware = &stm32_i2s_pcm_hw,
+ .prepare_slave_config = snd_dmaengine_pcm_prepare_slave_config,
+ .prealloc_buffer_size = PAGE_SIZE * 8,
+};
+
+static const struct snd_soc_component_driver stm32_i2s_component = {
+ .name = "stm32-i2s",
+ .legacy_dai_naming = 1,
+};
+
+static void stm32_i2s_dai_init(struct snd_soc_pcm_stream *stream,
+ char *stream_name)
+{
+ stream->stream_name = stream_name;
+ stream->channels_min = 1;
+ stream->channels_max = 2;
+ stream->rates = SNDRV_PCM_RATE_8000_192000;
+ stream->formats = SNDRV_PCM_FMTBIT_S16_LE |
+ SNDRV_PCM_FMTBIT_S32_LE;
+}
+
+static int stm32_i2s_dais_init(struct platform_device *pdev,
+ struct stm32_i2s_data *i2s)
+{
+ struct snd_soc_dai_driver *dai_ptr;
+
+ dai_ptr = devm_kzalloc(&pdev->dev, sizeof(struct snd_soc_dai_driver),
+ GFP_KERNEL);
+ if (!dai_ptr)
+ return -ENOMEM;
+
+ dai_ptr->ops = &stm32_i2s_pcm_dai_ops;
+ dai_ptr->id = 1;
+ stm32_i2s_dai_init(&dai_ptr->playback, "playback");
+ stm32_i2s_dai_init(&dai_ptr->capture, "capture");
+ i2s->dai_drv = dai_ptr;
+
+ return 0;
+}
+
+static const struct of_device_id stm32_i2s_ids[] = {
+ {
+ .compatible = "st,stm32h7-i2s",
+ .data = &stm32_h7_i2s_regmap_conf
+ },
+ {},
+};
+
+static int stm32_i2s_parse_dt(struct platform_device *pdev,
+ struct stm32_i2s_data *i2s)
+{
+ struct device_node *np = pdev->dev.of_node;
+ const struct of_device_id *of_id;
+ struct reset_control *rst;
+ struct resource *res;
+ int irq, ret;
+
+ if (!np)
+ return -ENODEV;
+
+ of_id = of_match_device(stm32_i2s_ids, &pdev->dev);
+ if (of_id)
+ i2s->regmap_conf = (const struct regmap_config *)of_id->data;
+ else
+ return -EINVAL;
+
+ i2s->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
+ if (IS_ERR(i2s->base))
+ return PTR_ERR(i2s->base);
+
+ i2s->phys_addr = res->start;
+
+ /* Get clocks */
+ i2s->pclk = devm_clk_get(&pdev->dev, "pclk");
+ if (IS_ERR(i2s->pclk))
+ return dev_err_probe(&pdev->dev, PTR_ERR(i2s->pclk),
+ "Could not get pclk\n");
+
+ i2s->i2sclk = devm_clk_get(&pdev->dev, "i2sclk");
+ if (IS_ERR(i2s->i2sclk))
+ return dev_err_probe(&pdev->dev, PTR_ERR(i2s->i2sclk),
+ "Could not get i2sclk\n");
+
+ i2s->x8kclk = devm_clk_get(&pdev->dev, "x8k");
+ if (IS_ERR(i2s->x8kclk))
+ return dev_err_probe(&pdev->dev, PTR_ERR(i2s->x8kclk),
+ "Could not get x8k parent clock\n");
+
+ i2s->x11kclk = devm_clk_get(&pdev->dev, "x11k");
+ if (IS_ERR(i2s->x11kclk))
+ return dev_err_probe(&pdev->dev, PTR_ERR(i2s->x11kclk),
+ "Could not get x11k parent clock\n");
+
+ /* Register mclk provider if requested */
+ if (of_property_present(np, "#clock-cells")) {
+ ret = stm32_i2s_add_mclk_provider(i2s);
+ if (ret < 0)
+ return ret;
+ }
+
+ /* Get irqs */
+ irq = platform_get_irq(pdev, 0);
+ if (irq < 0)
+ return irq;
+
+ ret = devm_request_irq(&pdev->dev, irq, stm32_i2s_isr, 0,
+ dev_name(&pdev->dev), i2s);
+ if (ret) {
+ dev_err(&pdev->dev, "irq request returned %d\n", ret);
+ return ret;
+ }
+
+ /* Reset */
+ rst = devm_reset_control_get_optional_exclusive(&pdev->dev, NULL);
+ if (IS_ERR(rst))
+ return dev_err_probe(&pdev->dev, PTR_ERR(rst),
+ "Reset controller error\n");
+
+ reset_control_assert(rst);
+ udelay(2);
+ reset_control_deassert(rst);
+
+ return 0;
+}
+
+static void stm32_i2s_remove(struct platform_device *pdev)
+{
+ snd_dmaengine_pcm_unregister(&pdev->dev);
+ snd_soc_unregister_component(&pdev->dev);
+ pm_runtime_disable(&pdev->dev);
+}
+
+static int stm32_i2s_probe(struct platform_device *pdev)
+{
+ struct stm32_i2s_data *i2s;
+ u32 val;
+ int ret;
+
+ i2s = devm_kzalloc(&pdev->dev, sizeof(*i2s), GFP_KERNEL);
+ if (!i2s)
+ return -ENOMEM;
+
+ i2s->pdev = pdev;
+ i2s->ms_flg = I2S_MS_NOT_SET;
+ spin_lock_init(&i2s->lock_fd);
+ spin_lock_init(&i2s->irq_lock);
+ platform_set_drvdata(pdev, i2s);
+
+ ret = stm32_i2s_parse_dt(pdev, i2s);
+ if (ret)
+ return ret;
+
+ ret = stm32_i2s_dais_init(pdev, i2s);
+ if (ret)
+ return ret;
+
+ i2s->regmap = devm_regmap_init_mmio_clk(&pdev->dev, "pclk",
+ i2s->base, i2s->regmap_conf);
+ if (IS_ERR(i2s->regmap))
+ return dev_err_probe(&pdev->dev, PTR_ERR(i2s->regmap),
+ "Regmap init error\n");
+
+ ret = snd_dmaengine_pcm_register(&pdev->dev, &stm32_i2s_pcm_config, 0);
+ if (ret)
+ return dev_err_probe(&pdev->dev, ret, "PCM DMA register error\n");
+
+ ret = snd_soc_register_component(&pdev->dev, &stm32_i2s_component,
+ i2s->dai_drv, 1);
+ if (ret) {
+ snd_dmaengine_pcm_unregister(&pdev->dev);
+ return ret;
+ }
+
+ /* Set SPI/I2S in i2s mode */
+ ret = regmap_update_bits(i2s->regmap, STM32_I2S_CGFR_REG,
+ I2S_CGFR_I2SMOD, I2S_CGFR_I2SMOD);
+ if (ret)
+ goto error;
+
+ ret = regmap_read(i2s->regmap, STM32_I2S_IPIDR_REG, &val);
+ if (ret)
+ goto error;
+
+ if (val == I2S_IPIDR_NUMBER) {
+ ret = regmap_read(i2s->regmap, STM32_I2S_HWCFGR_REG, &val);
+ if (ret)
+ goto error;
+
+ if (!FIELD_GET(I2S_HWCFGR_I2S_SUPPORT_MASK, val)) {
+ dev_err(&pdev->dev,
+ "Device does not support i2s mode\n");
+ ret = -EPERM;
+ goto error;
+ }
+
+ ret = regmap_read(i2s->regmap, STM32_I2S_VERR_REG, &val);
+ if (ret)
+ goto error;
+
+ dev_dbg(&pdev->dev, "I2S version: %lu.%lu registered\n",
+ FIELD_GET(I2S_VERR_MAJ_MASK, val),
+ FIELD_GET(I2S_VERR_MIN_MASK, val));
+ }
+
+ pm_runtime_enable(&pdev->dev);
+
+ return ret;
+
+error:
+ stm32_i2s_remove(pdev);
+
+ return ret;
+}
+
+MODULE_DEVICE_TABLE(of, stm32_i2s_ids);
+
+#ifdef CONFIG_PM_SLEEP
+static int stm32_i2s_suspend(struct device *dev)
+{
+ struct stm32_i2s_data *i2s = dev_get_drvdata(dev);
+
+ regcache_cache_only(i2s->regmap, true);
+ regcache_mark_dirty(i2s->regmap);
+
+ return 0;
+}
+
+static int stm32_i2s_resume(struct device *dev)
+{
+ struct stm32_i2s_data *i2s = dev_get_drvdata(dev);
+
+ regcache_cache_only(i2s->regmap, false);
+ return regcache_sync(i2s->regmap);
+}
+#endif /* CONFIG_PM_SLEEP */
+
+static const struct dev_pm_ops stm32_i2s_pm_ops = {
+ SET_SYSTEM_SLEEP_PM_OPS(stm32_i2s_suspend, stm32_i2s_resume)
+};
+
+static struct platform_driver stm32_i2s_driver = {
+ .driver = {
+ .name = "st,stm32-i2s",
+ .of_match_table = stm32_i2s_ids,
+ .pm = &stm32_i2s_pm_ops,
+ },
+ .probe = stm32_i2s_probe,
+ .remove_new = stm32_i2s_remove,
+};
+
+module_platform_driver(stm32_i2s_driver);
+
+MODULE_DESCRIPTION("STM32 Soc i2s Interface");
+MODULE_AUTHOR("Olivier Moysan, <olivier.moysan@st.com>");
+MODULE_ALIAS("platform:stm32-i2s");
+MODULE_LICENSE("GPL v2");
diff --git a/sound/soc/stm/stm32_sai.c b/sound/soc/stm/stm32_sai.c
new file mode 100644
index 0000000000..8e21e6f886
--- /dev/null
+++ b/sound/soc/stm/stm32_sai.c
@@ -0,0 +1,294 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * STM32 ALSA SoC Digital Audio Interface (SAI) driver.
+ *
+ * Copyright (C) 2016, STMicroelectronics - All Rights Reserved
+ * Author(s): Olivier Moysan <olivier.moysan@st.com> for STMicroelectronics.
+ */
+
+#include <linux/bitfield.h>
+#include <linux/clk.h>
+#include <linux/delay.h>
+#include <linux/module.h>
+#include <linux/of_platform.h>
+#include <linux/pinctrl/consumer.h>
+#include <linux/reset.h>
+
+#include <sound/dmaengine_pcm.h>
+#include <sound/core.h>
+
+#include "stm32_sai.h"
+
+static const struct stm32_sai_conf stm32_sai_conf_f4 = {
+ .version = STM_SAI_STM32F4,
+ .fifo_size = 8,
+ .has_spdif_pdm = false,
+};
+
+/*
+ * Default settings for stm32 H7 socs and next.
+ * These default settings will be overridden if the soc provides
+ * support of hardware configuration registers.
+ */
+static const struct stm32_sai_conf stm32_sai_conf_h7 = {
+ .version = STM_SAI_STM32H7,
+ .fifo_size = 8,
+ .has_spdif_pdm = true,
+};
+
+static const struct of_device_id stm32_sai_ids[] = {
+ { .compatible = "st,stm32f4-sai", .data = (void *)&stm32_sai_conf_f4 },
+ { .compatible = "st,stm32h7-sai", .data = (void *)&stm32_sai_conf_h7 },
+ {}
+};
+
+static int stm32_sai_pclk_disable(struct device *dev)
+{
+ struct stm32_sai_data *sai = dev_get_drvdata(dev);
+
+ clk_disable_unprepare(sai->pclk);
+
+ return 0;
+}
+
+static int stm32_sai_pclk_enable(struct device *dev)
+{
+ struct stm32_sai_data *sai = dev_get_drvdata(dev);
+ int ret;
+
+ ret = clk_prepare_enable(sai->pclk);
+ if (ret) {
+ dev_err(&sai->pdev->dev, "failed to enable clock: %d\n", ret);
+ return ret;
+ }
+
+ return 0;
+}
+
+static int stm32_sai_sync_conf_client(struct stm32_sai_data *sai, int synci)
+{
+ int ret;
+
+ /* Enable peripheral clock to allow GCR register access */
+ ret = stm32_sai_pclk_enable(&sai->pdev->dev);
+ if (ret)
+ return ret;
+
+ writel_relaxed(FIELD_PREP(SAI_GCR_SYNCIN_MASK, (synci - 1)), sai->base);
+
+ stm32_sai_pclk_disable(&sai->pdev->dev);
+
+ return 0;
+}
+
+static int stm32_sai_sync_conf_provider(struct stm32_sai_data *sai, int synco)
+{
+ u32 prev_synco;
+ int ret;
+
+ /* Enable peripheral clock to allow GCR register access */
+ ret = stm32_sai_pclk_enable(&sai->pdev->dev);
+ if (ret)
+ return ret;
+
+ dev_dbg(&sai->pdev->dev, "Set %pOFn%s as synchro provider\n",
+ sai->pdev->dev.of_node,
+ synco == STM_SAI_SYNC_OUT_A ? "A" : "B");
+
+ prev_synco = FIELD_GET(SAI_GCR_SYNCOUT_MASK, readl_relaxed(sai->base));
+ if (prev_synco != STM_SAI_SYNC_OUT_NONE && synco != prev_synco) {
+ dev_err(&sai->pdev->dev, "%pOFn%s already set as sync provider\n",
+ sai->pdev->dev.of_node,
+ prev_synco == STM_SAI_SYNC_OUT_A ? "A" : "B");
+ stm32_sai_pclk_disable(&sai->pdev->dev);
+ return -EINVAL;
+ }
+
+ writel_relaxed(FIELD_PREP(SAI_GCR_SYNCOUT_MASK, synco), sai->base);
+
+ stm32_sai_pclk_disable(&sai->pdev->dev);
+
+ return 0;
+}
+
+static int stm32_sai_set_sync(struct stm32_sai_data *sai_client,
+ struct device_node *np_provider,
+ int synco, int synci)
+{
+ struct platform_device *pdev = of_find_device_by_node(np_provider);
+ struct stm32_sai_data *sai_provider;
+ int ret;
+
+ if (!pdev) {
+ dev_err(&sai_client->pdev->dev,
+ "Device not found for node %pOFn\n", np_provider);
+ of_node_put(np_provider);
+ return -ENODEV;
+ }
+
+ sai_provider = platform_get_drvdata(pdev);
+ if (!sai_provider) {
+ dev_err(&sai_client->pdev->dev,
+ "SAI sync provider data not found\n");
+ ret = -EINVAL;
+ goto error;
+ }
+
+ /* Configure sync client */
+ ret = stm32_sai_sync_conf_client(sai_client, synci);
+ if (ret < 0)
+ goto error;
+
+ /* Configure sync provider */
+ ret = stm32_sai_sync_conf_provider(sai_provider, synco);
+
+error:
+ put_device(&pdev->dev);
+ of_node_put(np_provider);
+ return ret;
+}
+
+static int stm32_sai_probe(struct platform_device *pdev)
+{
+ struct stm32_sai_data *sai;
+ struct reset_control *rst;
+ const struct of_device_id *of_id;
+ u32 val;
+ int ret;
+
+ sai = devm_kzalloc(&pdev->dev, sizeof(*sai), GFP_KERNEL);
+ if (!sai)
+ return -ENOMEM;
+
+ sai->base = devm_platform_ioremap_resource(pdev, 0);
+ if (IS_ERR(sai->base))
+ return PTR_ERR(sai->base);
+
+ of_id = of_match_device(stm32_sai_ids, &pdev->dev);
+ if (of_id)
+ memcpy(&sai->conf, (const struct stm32_sai_conf *)of_id->data,
+ sizeof(struct stm32_sai_conf));
+ else
+ return -EINVAL;
+
+ if (!STM_SAI_IS_F4(sai)) {
+ sai->pclk = devm_clk_get(&pdev->dev, "pclk");
+ if (IS_ERR(sai->pclk))
+ return dev_err_probe(&pdev->dev, PTR_ERR(sai->pclk),
+ "missing bus clock pclk\n");
+ }
+
+ sai->clk_x8k = devm_clk_get(&pdev->dev, "x8k");
+ if (IS_ERR(sai->clk_x8k))
+ return dev_err_probe(&pdev->dev, PTR_ERR(sai->clk_x8k),
+ "missing x8k parent clock\n");
+
+ sai->clk_x11k = devm_clk_get(&pdev->dev, "x11k");
+ if (IS_ERR(sai->clk_x11k))
+ return dev_err_probe(&pdev->dev, PTR_ERR(sai->clk_x11k),
+ "missing x11k parent clock\n");
+
+ /* init irqs */
+ sai->irq = platform_get_irq(pdev, 0);
+ if (sai->irq < 0)
+ return sai->irq;
+
+ /* reset */
+ rst = devm_reset_control_get_optional_exclusive(&pdev->dev, NULL);
+ if (IS_ERR(rst))
+ return dev_err_probe(&pdev->dev, PTR_ERR(rst),
+ "Reset controller error\n");
+
+ reset_control_assert(rst);
+ udelay(2);
+ reset_control_deassert(rst);
+
+ /* Enable peripheral clock to allow register access */
+ ret = clk_prepare_enable(sai->pclk);
+ if (ret) {
+ dev_err(&pdev->dev, "failed to enable clock: %d\n", ret);
+ return ret;
+ }
+
+ val = FIELD_GET(SAI_IDR_ID_MASK,
+ readl_relaxed(sai->base + STM_SAI_IDR));
+ if (val == SAI_IPIDR_NUMBER) {
+ val = readl_relaxed(sai->base + STM_SAI_HWCFGR);
+ sai->conf.fifo_size = FIELD_GET(SAI_HWCFGR_FIFO_SIZE, val);
+ sai->conf.has_spdif_pdm = !!FIELD_GET(SAI_HWCFGR_SPDIF_PDM,
+ val);
+
+ val = readl_relaxed(sai->base + STM_SAI_VERR);
+ sai->conf.version = val;
+
+ dev_dbg(&pdev->dev, "SAI version: %lu.%lu registered\n",
+ FIELD_GET(SAI_VERR_MAJ_MASK, val),
+ FIELD_GET(SAI_VERR_MIN_MASK, val));
+ }
+ clk_disable_unprepare(sai->pclk);
+
+ sai->pdev = pdev;
+ sai->set_sync = &stm32_sai_set_sync;
+ platform_set_drvdata(pdev, sai);
+
+ return devm_of_platform_populate(&pdev->dev);
+}
+
+#ifdef CONFIG_PM_SLEEP
+/*
+ * When pins are shared by two sai sub instances, pins have to be defined
+ * in sai parent node. In this case, pins state is not managed by alsa fw.
+ * These pins are managed in suspend/resume callbacks.
+ */
+static int stm32_sai_suspend(struct device *dev)
+{
+ struct stm32_sai_data *sai = dev_get_drvdata(dev);
+ int ret;
+
+ ret = stm32_sai_pclk_enable(dev);
+ if (ret)
+ return ret;
+
+ sai->gcr = readl_relaxed(sai->base);
+ stm32_sai_pclk_disable(dev);
+
+ return pinctrl_pm_select_sleep_state(dev);
+}
+
+static int stm32_sai_resume(struct device *dev)
+{
+ struct stm32_sai_data *sai = dev_get_drvdata(dev);
+ int ret;
+
+ ret = stm32_sai_pclk_enable(dev);
+ if (ret)
+ return ret;
+
+ writel_relaxed(sai->gcr, sai->base);
+ stm32_sai_pclk_disable(dev);
+
+ return pinctrl_pm_select_default_state(dev);
+}
+#endif /* CONFIG_PM_SLEEP */
+
+static const struct dev_pm_ops stm32_sai_pm_ops = {
+ SET_SYSTEM_SLEEP_PM_OPS(stm32_sai_suspend, stm32_sai_resume)
+};
+
+MODULE_DEVICE_TABLE(of, stm32_sai_ids);
+
+static struct platform_driver stm32_sai_driver = {
+ .driver = {
+ .name = "st,stm32-sai",
+ .of_match_table = stm32_sai_ids,
+ .pm = &stm32_sai_pm_ops,
+ },
+ .probe = stm32_sai_probe,
+};
+
+module_platform_driver(stm32_sai_driver);
+
+MODULE_DESCRIPTION("STM32 Soc SAI Interface");
+MODULE_AUTHOR("Olivier Moysan <olivier.moysan@st.com>");
+MODULE_ALIAS("platform:st,stm32-sai");
+MODULE_LICENSE("GPL v2");
diff --git a/sound/soc/stm/stm32_sai.h b/sound/soc/stm/stm32_sai.h
new file mode 100644
index 0000000000..33e4bff8c2
--- /dev/null
+++ b/sound/soc/stm/stm32_sai.h
@@ -0,0 +1,302 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * STM32 ALSA SoC Digital Audio Interface (SAI) driver.
+ *
+ * Copyright (C) 2016, STMicroelectronics - All Rights Reserved
+ * Author(s): Olivier Moysan <olivier.moysan@st.com> for STMicroelectronics.
+ */
+
+#include <linux/bitfield.h>
+
+/******************** SAI Register Map **************************************/
+
+/* Global configuration register */
+#define STM_SAI_GCR 0x00
+
+/* Sub-block A&B registers offsets, relative to A&B sub-block addresses */
+#define STM_SAI_CR1_REGX 0x00 /* A offset: 0x04. B offset: 0x24 */
+#define STM_SAI_CR2_REGX 0x04
+#define STM_SAI_FRCR_REGX 0x08
+#define STM_SAI_SLOTR_REGX 0x0C
+#define STM_SAI_IMR_REGX 0x10
+#define STM_SAI_SR_REGX 0x14
+#define STM_SAI_CLRFR_REGX 0x18
+#define STM_SAI_DR_REGX 0x1C
+
+/* Sub-block A registers, relative to sub-block A address */
+#define STM_SAI_PDMCR_REGX 0x40
+#define STM_SAI_PDMLY_REGX 0x44
+
+/* Hardware configuration registers */
+#define STM_SAI_HWCFGR 0x3F0
+#define STM_SAI_VERR 0x3F4
+#define STM_SAI_IDR 0x3F8
+#define STM_SAI_SIDR 0x3FC
+
+/******************** Bit definition for SAI_GCR register *******************/
+#define SAI_GCR_SYNCIN_SHIFT 0
+#define SAI_GCR_SYNCIN_WDTH 2
+#define SAI_GCR_SYNCIN_MASK GENMASK(1, SAI_GCR_SYNCIN_SHIFT)
+#define SAI_GCR_SYNCIN_MAX FIELD_GET(SAI_GCR_SYNCIN_MASK,\
+ SAI_GCR_SYNCIN_MASK)
+
+#define SAI_GCR_SYNCOUT_SHIFT 4
+#define SAI_GCR_SYNCOUT_MASK GENMASK(5, SAI_GCR_SYNCOUT_SHIFT)
+
+/******************* Bit definition for SAI_XCR1 register *******************/
+#define SAI_XCR1_RX_TX_SHIFT 0
+#define SAI_XCR1_RX_TX BIT(SAI_XCR1_RX_TX_SHIFT)
+#define SAI_XCR1_SLAVE_SHIFT 1
+#define SAI_XCR1_SLAVE BIT(SAI_XCR1_SLAVE_SHIFT)
+
+#define SAI_XCR1_PRTCFG_SHIFT 2
+#define SAI_XCR1_PRTCFG_MASK GENMASK(3, SAI_XCR1_PRTCFG_SHIFT)
+#define SAI_XCR1_PRTCFG_SET(x) ((x) << SAI_XCR1_PRTCFG_SHIFT)
+
+#define SAI_XCR1_DS_SHIFT 5
+#define SAI_XCR1_DS_MASK GENMASK(7, SAI_XCR1_DS_SHIFT)
+#define SAI_XCR1_DS_SET(x) ((x) << SAI_XCR1_DS_SHIFT)
+
+#define SAI_XCR1_LSBFIRST_SHIFT 8
+#define SAI_XCR1_LSBFIRST BIT(SAI_XCR1_LSBFIRST_SHIFT)
+#define SAI_XCR1_CKSTR_SHIFT 9
+#define SAI_XCR1_CKSTR BIT(SAI_XCR1_CKSTR_SHIFT)
+
+#define SAI_XCR1_SYNCEN_SHIFT 10
+#define SAI_XCR1_SYNCEN_MASK GENMASK(11, SAI_XCR1_SYNCEN_SHIFT)
+#define SAI_XCR1_SYNCEN_SET(x) ((x) << SAI_XCR1_SYNCEN_SHIFT)
+
+#define SAI_XCR1_MONO_SHIFT 12
+#define SAI_XCR1_MONO BIT(SAI_XCR1_MONO_SHIFT)
+#define SAI_XCR1_OUTDRIV_SHIFT 13
+#define SAI_XCR1_OUTDRIV BIT(SAI_XCR1_OUTDRIV_SHIFT)
+#define SAI_XCR1_SAIEN_SHIFT 16
+#define SAI_XCR1_SAIEN BIT(SAI_XCR1_SAIEN_SHIFT)
+#define SAI_XCR1_DMAEN_SHIFT 17
+#define SAI_XCR1_DMAEN BIT(SAI_XCR1_DMAEN_SHIFT)
+#define SAI_XCR1_NODIV_SHIFT 19
+#define SAI_XCR1_NODIV BIT(SAI_XCR1_NODIV_SHIFT)
+
+#define SAI_XCR1_MCKDIV_SHIFT 20
+#define SAI_XCR1_MCKDIV_WIDTH(x) (((x) == STM_SAI_STM32F4) ? 4 : 6)
+#define SAI_XCR1_MCKDIV_MASK(x) GENMASK((SAI_XCR1_MCKDIV_SHIFT + (x) - 1),\
+ SAI_XCR1_MCKDIV_SHIFT)
+#define SAI_XCR1_MCKDIV_SET(x) ((x) << SAI_XCR1_MCKDIV_SHIFT)
+#define SAI_XCR1_MCKDIV_MAX(x) ((1 << SAI_XCR1_MCKDIV_WIDTH(x)) - 1)
+
+#define SAI_XCR1_OSR_SHIFT 26
+#define SAI_XCR1_OSR BIT(SAI_XCR1_OSR_SHIFT)
+
+#define SAI_XCR1_MCKEN_SHIFT 27
+#define SAI_XCR1_MCKEN BIT(SAI_XCR1_MCKEN_SHIFT)
+
+/******************* Bit definition for SAI_XCR2 register *******************/
+#define SAI_XCR2_FTH_SHIFT 0
+#define SAI_XCR2_FTH_MASK GENMASK(2, SAI_XCR2_FTH_SHIFT)
+#define SAI_XCR2_FTH_SET(x) ((x) << SAI_XCR2_FTH_SHIFT)
+
+#define SAI_XCR2_FFLUSH_SHIFT 3
+#define SAI_XCR2_FFLUSH BIT(SAI_XCR2_FFLUSH_SHIFT)
+#define SAI_XCR2_TRIS_SHIFT 4
+#define SAI_XCR2_TRIS BIT(SAI_XCR2_TRIS_SHIFT)
+#define SAI_XCR2_MUTE_SHIFT 5
+#define SAI_XCR2_MUTE BIT(SAI_XCR2_MUTE_SHIFT)
+#define SAI_XCR2_MUTEVAL_SHIFT 6
+#define SAI_XCR2_MUTEVAL BIT(SAI_XCR2_MUTEVAL_SHIFT)
+
+#define SAI_XCR2_MUTECNT_SHIFT 7
+#define SAI_XCR2_MUTECNT_MASK GENMASK(12, SAI_XCR2_MUTECNT_SHIFT)
+#define SAI_XCR2_MUTECNT_SET(x) ((x) << SAI_XCR2_MUTECNT_SHIFT)
+
+#define SAI_XCR2_CPL_SHIFT 13
+#define SAI_XCR2_CPL BIT(SAI_XCR2_CPL_SHIFT)
+
+#define SAI_XCR2_COMP_SHIFT 14
+#define SAI_XCR2_COMP_MASK GENMASK(15, SAI_XCR2_COMP_SHIFT)
+#define SAI_XCR2_COMP_SET(x) ((x) << SAI_XCR2_COMP_SHIFT)
+
+/****************** Bit definition for SAI_XFRCR register *******************/
+#define SAI_XFRCR_FRL_SHIFT 0
+#define SAI_XFRCR_FRL_MASK GENMASK(7, SAI_XFRCR_FRL_SHIFT)
+#define SAI_XFRCR_FRL_SET(x) ((x) << SAI_XFRCR_FRL_SHIFT)
+
+#define SAI_XFRCR_FSALL_SHIFT 8
+#define SAI_XFRCR_FSALL_MASK GENMASK(14, SAI_XFRCR_FSALL_SHIFT)
+#define SAI_XFRCR_FSALL_SET(x) ((x) << SAI_XFRCR_FSALL_SHIFT)
+
+#define SAI_XFRCR_FSDEF_SHIFT 16
+#define SAI_XFRCR_FSDEF BIT(SAI_XFRCR_FSDEF_SHIFT)
+#define SAI_XFRCR_FSPOL_SHIFT 17
+#define SAI_XFRCR_FSPOL BIT(SAI_XFRCR_FSPOL_SHIFT)
+#define SAI_XFRCR_FSOFF_SHIFT 18
+#define SAI_XFRCR_FSOFF BIT(SAI_XFRCR_FSOFF_SHIFT)
+
+/****************** Bit definition for SAI_XSLOTR register ******************/
+#define SAI_XSLOTR_FBOFF_SHIFT 0
+#define SAI_XSLOTR_FBOFF_MASK GENMASK(4, SAI_XSLOTR_FBOFF_SHIFT)
+#define SAI_XSLOTR_FBOFF_SET(x) ((x) << SAI_XSLOTR_FBOFF_SHIFT)
+
+#define SAI_XSLOTR_SLOTSZ_SHIFT 6
+#define SAI_XSLOTR_SLOTSZ_MASK GENMASK(7, SAI_XSLOTR_SLOTSZ_SHIFT)
+#define SAI_XSLOTR_SLOTSZ_SET(x) ((x) << SAI_XSLOTR_SLOTSZ_SHIFT)
+
+#define SAI_XSLOTR_NBSLOT_SHIFT 8
+#define SAI_XSLOTR_NBSLOT_MASK GENMASK(11, SAI_XSLOTR_NBSLOT_SHIFT)
+#define SAI_XSLOTR_NBSLOT_SET(x) ((x) << SAI_XSLOTR_NBSLOT_SHIFT)
+
+#define SAI_XSLOTR_SLOTEN_SHIFT 16
+#define SAI_XSLOTR_SLOTEN_WIDTH 16
+#define SAI_XSLOTR_SLOTEN_MASK GENMASK(31, SAI_XSLOTR_SLOTEN_SHIFT)
+#define SAI_XSLOTR_SLOTEN_SET(x) ((x) << SAI_XSLOTR_SLOTEN_SHIFT)
+
+/******************* Bit definition for SAI_XIMR register *******************/
+#define SAI_XIMR_OVRUDRIE BIT(0)
+#define SAI_XIMR_MUTEDETIE BIT(1)
+#define SAI_XIMR_WCKCFGIE BIT(2)
+#define SAI_XIMR_FREQIE BIT(3)
+#define SAI_XIMR_CNRDYIE BIT(4)
+#define SAI_XIMR_AFSDETIE BIT(5)
+#define SAI_XIMR_LFSDETIE BIT(6)
+
+#define SAI_XIMR_SHIFT 0
+#define SAI_XIMR_MASK GENMASK(6, SAI_XIMR_SHIFT)
+
+/******************** Bit definition for SAI_XSR register *******************/
+#define SAI_XSR_OVRUDR BIT(0)
+#define SAI_XSR_MUTEDET BIT(1)
+#define SAI_XSR_WCKCFG BIT(2)
+#define SAI_XSR_FREQ BIT(3)
+#define SAI_XSR_CNRDY BIT(4)
+#define SAI_XSR_AFSDET BIT(5)
+#define SAI_XSR_LFSDET BIT(6)
+
+#define SAI_XSR_SHIFT 0
+#define SAI_XSR_MASK GENMASK(6, SAI_XSR_SHIFT)
+
+/****************** Bit definition for SAI_XCLRFR register ******************/
+#define SAI_XCLRFR_COVRUDR BIT(0)
+#define SAI_XCLRFR_CMUTEDET BIT(1)
+#define SAI_XCLRFR_CWCKCFG BIT(2)
+#define SAI_XCLRFR_CFREQ BIT(3)
+#define SAI_XCLRFR_CCNRDY BIT(4)
+#define SAI_XCLRFR_CAFSDET BIT(5)
+#define SAI_XCLRFR_CLFSDET BIT(6)
+
+#define SAI_XCLRFR_SHIFT 0
+#define SAI_XCLRFR_MASK GENMASK(6, SAI_XCLRFR_SHIFT)
+
+/****************** Bit definition for SAI_PDMCR register ******************/
+#define SAI_PDMCR_PDMEN BIT(0)
+
+#define SAI_PDMCR_MICNBR_SHIFT 4
+#define SAI_PDMCR_MICNBR_MASK GENMASK(5, SAI_PDMCR_MICNBR_SHIFT)
+#define SAI_PDMCR_MICNBR_SET(x) ((x) << SAI_PDMCR_MICNBR_SHIFT)
+
+#define SAI_PDMCR_CKEN1 BIT(8)
+#define SAI_PDMCR_CKEN2 BIT(9)
+#define SAI_PDMCR_CKEN3 BIT(10)
+#define SAI_PDMCR_CKEN4 BIT(11)
+
+/****************** Bit definition for (SAI_PDMDLY register ****************/
+#define SAI_PDMDLY_1L_SHIFT 0
+#define SAI_PDMDLY_1L_MASK GENMASK(2, SAI_PDMDLY_1L_SHIFT)
+#define SAI_PDMDLY_1L_WIDTH 3
+
+#define SAI_PDMDLY_1R_SHIFT 4
+#define SAI_PDMDLY_1R_MASK GENMASK(6, SAI_PDMDLY_1R_SHIFT)
+#define SAI_PDMDLY_1R_WIDTH 3
+
+#define SAI_PDMDLY_2L_SHIFT 8
+#define SAI_PDMDLY_2L_MASK GENMASK(10, SAI_PDMDLY_2L_SHIFT)
+#define SAI_PDMDLY_2L_WIDTH 3
+
+#define SAI_PDMDLY_2R_SHIFT 12
+#define SAI_PDMDLY_2R_MASK GENMASK(14, SAI_PDMDLY_2R_SHIFT)
+#define SAI_PDMDLY_2R_WIDTH 3
+
+#define SAI_PDMDLY_3L_SHIFT 16
+#define SAI_PDMDLY_3L_MASK GENMASK(18, SAI_PDMDLY_3L_SHIFT)
+#define SAI_PDMDLY_3L_WIDTH 3
+
+#define SAI_PDMDLY_3R_SHIFT 20
+#define SAI_PDMDLY_3R_MASK GENMASK(22, SAI_PDMDLY_3R_SHIFT)
+#define SAI_PDMDLY_3R_WIDTH 3
+
+#define SAI_PDMDLY_4L_SHIFT 24
+#define SAI_PDMDLY_4L_MASK GENMASK(26, SAI_PDMDLY_4L_SHIFT)
+#define SAI_PDMDLY_4L_WIDTH 3
+
+#define SAI_PDMDLY_4R_SHIFT 28
+#define SAI_PDMDLY_4R_MASK GENMASK(30, SAI_PDMDLY_4R_SHIFT)
+#define SAI_PDMDLY_4R_WIDTH 3
+
+/* Registers below apply to SAI version 2.1 and more */
+
+/* Bit definition for SAI_HWCFGR register */
+#define SAI_HWCFGR_FIFO_SIZE GENMASK(7, 0)
+#define SAI_HWCFGR_SPDIF_PDM GENMASK(11, 8)
+#define SAI_HWCFGR_REGOUT GENMASK(19, 12)
+
+/* Bit definition for SAI_VERR register */
+#define SAI_VERR_MIN_MASK GENMASK(3, 0)
+#define SAI_VERR_MAJ_MASK GENMASK(7, 4)
+
+/* Bit definition for SAI_IDR register */
+#define SAI_IDR_ID_MASK GENMASK(31, 0)
+
+/* Bit definition for SAI_SIDR register */
+#define SAI_SIDR_ID_MASK GENMASK(31, 0)
+
+#define SAI_IPIDR_NUMBER 0x00130031
+
+/* SAI version numbers are 1.x for F4. Major version number set to 1 for F4 */
+#define STM_SAI_STM32F4 BIT(4)
+/* Dummy version number for H7 socs and next */
+#define STM_SAI_STM32H7 0x0
+
+#define STM_SAI_IS_F4(ip) ((ip)->conf.version == STM_SAI_STM32F4)
+#define STM_SAI_HAS_SPDIF_PDM(ip)\
+ ((ip)->pdata->conf.has_spdif_pdm)
+
+enum stm32_sai_syncout {
+ STM_SAI_SYNC_OUT_NONE,
+ STM_SAI_SYNC_OUT_A,
+ STM_SAI_SYNC_OUT_B,
+};
+
+/**
+ * struct stm32_sai_conf - SAI configuration
+ * @version: SAI version
+ * @fifo_size: SAI fifo size as words number
+ * @has_spdif_pdm: SAI S/PDIF and PDM features support flag
+ */
+struct stm32_sai_conf {
+ u32 version;
+ u32 fifo_size;
+ bool has_spdif_pdm;
+};
+
+/**
+ * struct stm32_sai_data - private data of SAI instance driver
+ * @pdev: device data pointer
+ * @base: common register bank virtual base address
+ * @pclk: SAI bus clock
+ * @clk_x8k: SAI parent clock for sampling frequencies multiple of 8kHz
+ * @clk_x11k: SAI parent clock for sampling frequencies multiple of 11kHz
+ * @conf: SAI hardware capabitilites
+ * @irq: SAI interrupt line
+ * @set_sync: pointer to synchro mode configuration callback
+ * @gcr: SAI Global Configuration Register
+ */
+struct stm32_sai_data {
+ struct platform_device *pdev;
+ void __iomem *base;
+ struct clk *pclk;
+ struct clk *clk_x8k;
+ struct clk *clk_x11k;
+ struct stm32_sai_conf conf;
+ int irq;
+ int (*set_sync)(struct stm32_sai_data *sai,
+ struct device_node *np_provider, int synco, int synci);
+ u32 gcr;
+};
diff --git a/sound/soc/stm/stm32_sai_sub.c b/sound/soc/stm/stm32_sai_sub.c
new file mode 100644
index 0000000000..0acc848c1f
--- /dev/null
+++ b/sound/soc/stm/stm32_sai_sub.c
@@ -0,0 +1,1634 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * STM32 ALSA SoC Digital Audio Interface (SAI) driver.
+ *
+ * Copyright (C) 2016, STMicroelectronics - All Rights Reserved
+ * Author(s): Olivier Moysan <olivier.moysan@st.com> for STMicroelectronics.
+ */
+
+#include <linux/clk.h>
+#include <linux/clk-provider.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/of_irq.h>
+#include <linux/of_platform.h>
+#include <linux/pm_runtime.h>
+#include <linux/regmap.h>
+
+#include <sound/asoundef.h>
+#include <sound/core.h>
+#include <sound/dmaengine_pcm.h>
+#include <sound/pcm_params.h>
+
+#include "stm32_sai.h"
+
+#define SAI_FREE_PROTOCOL 0x0
+#define SAI_SPDIF_PROTOCOL 0x1
+
+#define SAI_SLOT_SIZE_AUTO 0x0
+#define SAI_SLOT_SIZE_16 0x1
+#define SAI_SLOT_SIZE_32 0x2
+
+#define SAI_DATASIZE_8 0x2
+#define SAI_DATASIZE_10 0x3
+#define SAI_DATASIZE_16 0x4
+#define SAI_DATASIZE_20 0x5
+#define SAI_DATASIZE_24 0x6
+#define SAI_DATASIZE_32 0x7
+
+#define STM_SAI_DAI_NAME_SIZE 15
+
+#define STM_SAI_IS_PLAYBACK(ip) ((ip)->dir == SNDRV_PCM_STREAM_PLAYBACK)
+#define STM_SAI_IS_CAPTURE(ip) ((ip)->dir == SNDRV_PCM_STREAM_CAPTURE)
+
+#define STM_SAI_A_ID 0x0
+#define STM_SAI_B_ID 0x1
+
+#define STM_SAI_IS_SUB_A(x) ((x)->id == STM_SAI_A_ID)
+
+#define SAI_SYNC_NONE 0x0
+#define SAI_SYNC_INTERNAL 0x1
+#define SAI_SYNC_EXTERNAL 0x2
+
+#define STM_SAI_PROTOCOL_IS_SPDIF(ip) ((ip)->spdif)
+#define STM_SAI_HAS_SPDIF(x) ((x)->pdata->conf.has_spdif_pdm)
+#define STM_SAI_HAS_PDM(x) ((x)->pdata->conf.has_spdif_pdm)
+#define STM_SAI_HAS_EXT_SYNC(x) (!STM_SAI_IS_F4(sai->pdata))
+
+#define SAI_IEC60958_BLOCK_FRAMES 192
+#define SAI_IEC60958_STATUS_BYTES 24
+
+#define SAI_MCLK_NAME_LEN 32
+#define SAI_RATE_11K 11025
+
+/**
+ * struct stm32_sai_sub_data - private data of SAI sub block (block A or B)
+ * @pdev: device data pointer
+ * @regmap: SAI register map pointer
+ * @regmap_config: SAI sub block register map configuration pointer
+ * @dma_params: dma configuration data for rx or tx channel
+ * @cpu_dai_drv: DAI driver data pointer
+ * @cpu_dai: DAI runtime data pointer
+ * @substream: PCM substream data pointer
+ * @pdata: SAI block parent data pointer
+ * @np_sync_provider: synchronization provider node
+ * @sai_ck: kernel clock feeding the SAI clock generator
+ * @sai_mclk: master clock from SAI mclk provider
+ * @phys_addr: SAI registers physical base address
+ * @mclk_rate: SAI block master clock frequency (Hz). set at init
+ * @id: SAI sub block id corresponding to sub-block A or B
+ * @dir: SAI block direction (playback or capture). set at init
+ * @master: SAI block mode flag. (true=master, false=slave) set at init
+ * @spdif: SAI S/PDIF iec60958 mode flag. set at init
+ * @fmt: SAI block format. relevant only for custom protocols. set at init
+ * @sync: SAI block synchronization mode. (none, internal or external)
+ * @synco: SAI block ext sync source (provider setting). (none, sub-block A/B)
+ * @synci: SAI block ext sync source (client setting). (SAI sync provider index)
+ * @fs_length: frame synchronization length. depends on protocol settings
+ * @slots: rx or tx slot number
+ * @slot_width: rx or tx slot width in bits
+ * @slot_mask: rx or tx active slots mask. set at init or at runtime
+ * @data_size: PCM data width. corresponds to PCM substream width.
+ * @spdif_frm_cnt: S/PDIF playback frame counter
+ * @iec958: iec958 data
+ * @ctrl_lock: control lock
+ * @irq_lock: prevent race condition with IRQ
+ */
+struct stm32_sai_sub_data {
+ struct platform_device *pdev;
+ struct regmap *regmap;
+ const struct regmap_config *regmap_config;
+ struct snd_dmaengine_dai_dma_data dma_params;
+ struct snd_soc_dai_driver cpu_dai_drv;
+ struct snd_soc_dai *cpu_dai;
+ struct snd_pcm_substream *substream;
+ struct stm32_sai_data *pdata;
+ struct device_node *np_sync_provider;
+ struct clk *sai_ck;
+ struct clk *sai_mclk;
+ dma_addr_t phys_addr;
+ unsigned int mclk_rate;
+ unsigned int id;
+ int dir;
+ bool master;
+ bool spdif;
+ int fmt;
+ int sync;
+ int synco;
+ int synci;
+ int fs_length;
+ int slots;
+ int slot_width;
+ int slot_mask;
+ int data_size;
+ unsigned int spdif_frm_cnt;
+ struct snd_aes_iec958 iec958;
+ struct mutex ctrl_lock; /* protect resources accessed by controls */
+ spinlock_t irq_lock; /* used to prevent race condition with IRQ */
+};
+
+enum stm32_sai_fifo_th {
+ STM_SAI_FIFO_TH_EMPTY,
+ STM_SAI_FIFO_TH_QUARTER,
+ STM_SAI_FIFO_TH_HALF,
+ STM_SAI_FIFO_TH_3_QUARTER,
+ STM_SAI_FIFO_TH_FULL,
+};
+
+static bool stm32_sai_sub_readable_reg(struct device *dev, unsigned int reg)
+{
+ switch (reg) {
+ case STM_SAI_CR1_REGX:
+ case STM_SAI_CR2_REGX:
+ case STM_SAI_FRCR_REGX:
+ case STM_SAI_SLOTR_REGX:
+ case STM_SAI_IMR_REGX:
+ case STM_SAI_SR_REGX:
+ case STM_SAI_CLRFR_REGX:
+ case STM_SAI_DR_REGX:
+ case STM_SAI_PDMCR_REGX:
+ case STM_SAI_PDMLY_REGX:
+ return true;
+ default:
+ return false;
+ }
+}
+
+static bool stm32_sai_sub_volatile_reg(struct device *dev, unsigned int reg)
+{
+ switch (reg) {
+ case STM_SAI_DR_REGX:
+ case STM_SAI_SR_REGX:
+ return true;
+ default:
+ return false;
+ }
+}
+
+static bool stm32_sai_sub_writeable_reg(struct device *dev, unsigned int reg)
+{
+ switch (reg) {
+ case STM_SAI_CR1_REGX:
+ case STM_SAI_CR2_REGX:
+ case STM_SAI_FRCR_REGX:
+ case STM_SAI_SLOTR_REGX:
+ case STM_SAI_IMR_REGX:
+ case STM_SAI_CLRFR_REGX:
+ case STM_SAI_DR_REGX:
+ case STM_SAI_PDMCR_REGX:
+ case STM_SAI_PDMLY_REGX:
+ return true;
+ default:
+ return false;
+ }
+}
+
+static int stm32_sai_sub_reg_up(struct stm32_sai_sub_data *sai,
+ unsigned int reg, unsigned int mask,
+ unsigned int val)
+{
+ int ret;
+
+ ret = clk_enable(sai->pdata->pclk);
+ if (ret < 0)
+ return ret;
+
+ ret = regmap_update_bits(sai->regmap, reg, mask, val);
+
+ clk_disable(sai->pdata->pclk);
+
+ return ret;
+}
+
+static int stm32_sai_sub_reg_wr(struct stm32_sai_sub_data *sai,
+ unsigned int reg, unsigned int mask,
+ unsigned int val)
+{
+ int ret;
+
+ ret = clk_enable(sai->pdata->pclk);
+ if (ret < 0)
+ return ret;
+
+ ret = regmap_write_bits(sai->regmap, reg, mask, val);
+
+ clk_disable(sai->pdata->pclk);
+
+ return ret;
+}
+
+static int stm32_sai_sub_reg_rd(struct stm32_sai_sub_data *sai,
+ unsigned int reg, unsigned int *val)
+{
+ int ret;
+
+ ret = clk_enable(sai->pdata->pclk);
+ if (ret < 0)
+ return ret;
+
+ ret = regmap_read(sai->regmap, reg, val);
+
+ clk_disable(sai->pdata->pclk);
+
+ return ret;
+}
+
+static const struct regmap_config stm32_sai_sub_regmap_config_f4 = {
+ .reg_bits = 32,
+ .reg_stride = 4,
+ .val_bits = 32,
+ .max_register = STM_SAI_DR_REGX,
+ .readable_reg = stm32_sai_sub_readable_reg,
+ .volatile_reg = stm32_sai_sub_volatile_reg,
+ .writeable_reg = stm32_sai_sub_writeable_reg,
+ .fast_io = true,
+ .cache_type = REGCACHE_FLAT,
+};
+
+static const struct regmap_config stm32_sai_sub_regmap_config_h7 = {
+ .reg_bits = 32,
+ .reg_stride = 4,
+ .val_bits = 32,
+ .max_register = STM_SAI_PDMLY_REGX,
+ .readable_reg = stm32_sai_sub_readable_reg,
+ .volatile_reg = stm32_sai_sub_volatile_reg,
+ .writeable_reg = stm32_sai_sub_writeable_reg,
+ .fast_io = true,
+ .cache_type = REGCACHE_FLAT,
+};
+
+static int snd_pcm_iec958_info(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_info *uinfo)
+{
+ uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
+ uinfo->count = 1;
+
+ return 0;
+}
+
+static int snd_pcm_iec958_get(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *uctl)
+{
+ struct stm32_sai_sub_data *sai = snd_kcontrol_chip(kcontrol);
+
+ mutex_lock(&sai->ctrl_lock);
+ memcpy(uctl->value.iec958.status, sai->iec958.status, 4);
+ mutex_unlock(&sai->ctrl_lock);
+
+ return 0;
+}
+
+static int snd_pcm_iec958_put(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *uctl)
+{
+ struct stm32_sai_sub_data *sai = snd_kcontrol_chip(kcontrol);
+
+ mutex_lock(&sai->ctrl_lock);
+ memcpy(sai->iec958.status, uctl->value.iec958.status, 4);
+ mutex_unlock(&sai->ctrl_lock);
+
+ return 0;
+}
+
+static const struct snd_kcontrol_new iec958_ctls = {
+ .access = (SNDRV_CTL_ELEM_ACCESS_READWRITE |
+ SNDRV_CTL_ELEM_ACCESS_VOLATILE),
+ .iface = SNDRV_CTL_ELEM_IFACE_PCM,
+ .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, DEFAULT),
+ .info = snd_pcm_iec958_info,
+ .get = snd_pcm_iec958_get,
+ .put = snd_pcm_iec958_put,
+};
+
+struct stm32_sai_mclk_data {
+ struct clk_hw hw;
+ unsigned long freq;
+ struct stm32_sai_sub_data *sai_data;
+};
+
+#define to_mclk_data(_hw) container_of(_hw, struct stm32_sai_mclk_data, hw)
+#define STM32_SAI_MAX_CLKS 1
+
+static int stm32_sai_get_clk_div(struct stm32_sai_sub_data *sai,
+ unsigned long input_rate,
+ unsigned long output_rate)
+{
+ int version = sai->pdata->conf.version;
+ int div;
+
+ div = DIV_ROUND_CLOSEST(input_rate, output_rate);
+ if (div > SAI_XCR1_MCKDIV_MAX(version)) {
+ dev_err(&sai->pdev->dev, "Divider %d out of range\n", div);
+ return -EINVAL;
+ }
+ dev_dbg(&sai->pdev->dev, "SAI divider %d\n", div);
+
+ if (input_rate % div)
+ dev_dbg(&sai->pdev->dev,
+ "Rate not accurate. requested (%ld), actual (%ld)\n",
+ output_rate, input_rate / div);
+
+ return div;
+}
+
+static int stm32_sai_set_clk_div(struct stm32_sai_sub_data *sai,
+ unsigned int div)
+{
+ int version = sai->pdata->conf.version;
+ int ret, cr1, mask;
+
+ if (div > SAI_XCR1_MCKDIV_MAX(version)) {
+ dev_err(&sai->pdev->dev, "Divider %d out of range\n", div);
+ return -EINVAL;
+ }
+
+ mask = SAI_XCR1_MCKDIV_MASK(SAI_XCR1_MCKDIV_WIDTH(version));
+ cr1 = SAI_XCR1_MCKDIV_SET(div);
+ ret = stm32_sai_sub_reg_up(sai, STM_SAI_CR1_REGX, mask, cr1);
+ if (ret < 0)
+ dev_err(&sai->pdev->dev, "Failed to update CR1 register\n");
+
+ return ret;
+}
+
+static int stm32_sai_set_parent_clock(struct stm32_sai_sub_data *sai,
+ unsigned int rate)
+{
+ struct platform_device *pdev = sai->pdev;
+ struct clk *parent_clk = sai->pdata->clk_x8k;
+ int ret;
+
+ if (!(rate % SAI_RATE_11K))
+ parent_clk = sai->pdata->clk_x11k;
+
+ ret = clk_set_parent(sai->sai_ck, parent_clk);
+ if (ret)
+ dev_err(&pdev->dev, " Error %d setting sai_ck parent clock. %s",
+ ret, ret == -EBUSY ?
+ "Active stream rates conflict\n" : "\n");
+
+ return ret;
+}
+
+static long stm32_sai_mclk_round_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long *prate)
+{
+ struct stm32_sai_mclk_data *mclk = to_mclk_data(hw);
+ struct stm32_sai_sub_data *sai = mclk->sai_data;
+ int div;
+
+ div = stm32_sai_get_clk_div(sai, *prate, rate);
+ if (div < 0)
+ return div;
+
+ mclk->freq = *prate / div;
+
+ return mclk->freq;
+}
+
+static unsigned long stm32_sai_mclk_recalc_rate(struct clk_hw *hw,
+ unsigned long parent_rate)
+{
+ struct stm32_sai_mclk_data *mclk = to_mclk_data(hw);
+
+ return mclk->freq;
+}
+
+static int stm32_sai_mclk_set_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long parent_rate)
+{
+ struct stm32_sai_mclk_data *mclk = to_mclk_data(hw);
+ struct stm32_sai_sub_data *sai = mclk->sai_data;
+ int div, ret;
+
+ div = stm32_sai_get_clk_div(sai, parent_rate, rate);
+ if (div < 0)
+ return div;
+
+ ret = stm32_sai_set_clk_div(sai, div);
+ if (ret)
+ return ret;
+
+ mclk->freq = rate;
+
+ return 0;
+}
+
+static int stm32_sai_mclk_enable(struct clk_hw *hw)
+{
+ struct stm32_sai_mclk_data *mclk = to_mclk_data(hw);
+ struct stm32_sai_sub_data *sai = mclk->sai_data;
+
+ dev_dbg(&sai->pdev->dev, "Enable master clock\n");
+
+ return stm32_sai_sub_reg_up(sai, STM_SAI_CR1_REGX,
+ SAI_XCR1_MCKEN, SAI_XCR1_MCKEN);
+}
+
+static void stm32_sai_mclk_disable(struct clk_hw *hw)
+{
+ struct stm32_sai_mclk_data *mclk = to_mclk_data(hw);
+ struct stm32_sai_sub_data *sai = mclk->sai_data;
+
+ dev_dbg(&sai->pdev->dev, "Disable master clock\n");
+
+ stm32_sai_sub_reg_up(sai, STM_SAI_CR1_REGX, SAI_XCR1_MCKEN, 0);
+}
+
+static const struct clk_ops mclk_ops = {
+ .enable = stm32_sai_mclk_enable,
+ .disable = stm32_sai_mclk_disable,
+ .recalc_rate = stm32_sai_mclk_recalc_rate,
+ .round_rate = stm32_sai_mclk_round_rate,
+ .set_rate = stm32_sai_mclk_set_rate,
+};
+
+static int stm32_sai_add_mclk_provider(struct stm32_sai_sub_data *sai)
+{
+ struct clk_hw *hw;
+ struct stm32_sai_mclk_data *mclk;
+ struct device *dev = &sai->pdev->dev;
+ const char *pname = __clk_get_name(sai->sai_ck);
+ char *mclk_name, *p, *s = (char *)pname;
+ int ret, i = 0;
+
+ mclk = devm_kzalloc(dev, sizeof(*mclk), GFP_KERNEL);
+ if (!mclk)
+ return -ENOMEM;
+
+ mclk_name = devm_kcalloc(dev, sizeof(char),
+ SAI_MCLK_NAME_LEN, GFP_KERNEL);
+ if (!mclk_name)
+ return -ENOMEM;
+
+ /*
+ * Forge mclk clock name from parent clock name and suffix.
+ * String after "_" char is stripped in parent name.
+ */
+ p = mclk_name;
+ while (*s && *s != '_' && (i < (SAI_MCLK_NAME_LEN - 7))) {
+ *p++ = *s++;
+ i++;
+ }
+ STM_SAI_IS_SUB_A(sai) ? strcat(p, "a_mclk") : strcat(p, "b_mclk");
+
+ mclk->hw.init = CLK_HW_INIT(mclk_name, pname, &mclk_ops, 0);
+ mclk->sai_data = sai;
+ hw = &mclk->hw;
+
+ dev_dbg(dev, "Register master clock %s\n", mclk_name);
+ ret = devm_clk_hw_register(&sai->pdev->dev, hw);
+ if (ret) {
+ dev_err(dev, "mclk register returned %d\n", ret);
+ return ret;
+ }
+ sai->sai_mclk = hw->clk;
+
+ /* register mclk provider */
+ return devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get, hw);
+}
+
+static irqreturn_t stm32_sai_isr(int irq, void *devid)
+{
+ struct stm32_sai_sub_data *sai = (struct stm32_sai_sub_data *)devid;
+ struct platform_device *pdev = sai->pdev;
+ unsigned int sr, imr, flags;
+ snd_pcm_state_t status = SNDRV_PCM_STATE_RUNNING;
+
+ stm32_sai_sub_reg_rd(sai, STM_SAI_IMR_REGX, &imr);
+ stm32_sai_sub_reg_rd(sai, STM_SAI_SR_REGX, &sr);
+
+ flags = sr & imr;
+ if (!flags)
+ return IRQ_NONE;
+
+ stm32_sai_sub_reg_wr(sai, STM_SAI_CLRFR_REGX, SAI_XCLRFR_MASK,
+ SAI_XCLRFR_MASK);
+
+ if (!sai->substream) {
+ dev_err(&pdev->dev, "Device stopped. Spurious IRQ 0x%x\n", sr);
+ return IRQ_NONE;
+ }
+
+ if (flags & SAI_XIMR_OVRUDRIE) {
+ dev_err(&pdev->dev, "IRQ %s\n",
+ STM_SAI_IS_PLAYBACK(sai) ? "underrun" : "overrun");
+ status = SNDRV_PCM_STATE_XRUN;
+ }
+
+ if (flags & SAI_XIMR_MUTEDETIE)
+ dev_dbg(&pdev->dev, "IRQ mute detected\n");
+
+ if (flags & SAI_XIMR_WCKCFGIE) {
+ dev_err(&pdev->dev, "IRQ wrong clock configuration\n");
+ status = SNDRV_PCM_STATE_DISCONNECTED;
+ }
+
+ if (flags & SAI_XIMR_CNRDYIE)
+ dev_err(&pdev->dev, "IRQ Codec not ready\n");
+
+ if (flags & SAI_XIMR_AFSDETIE) {
+ dev_err(&pdev->dev, "IRQ Anticipated frame synchro\n");
+ status = SNDRV_PCM_STATE_XRUN;
+ }
+
+ if (flags & SAI_XIMR_LFSDETIE) {
+ dev_err(&pdev->dev, "IRQ Late frame synchro\n");
+ status = SNDRV_PCM_STATE_XRUN;
+ }
+
+ spin_lock(&sai->irq_lock);
+ if (status != SNDRV_PCM_STATE_RUNNING && sai->substream)
+ snd_pcm_stop_xrun(sai->substream);
+ spin_unlock(&sai->irq_lock);
+
+ return IRQ_HANDLED;
+}
+
+static int stm32_sai_set_sysclk(struct snd_soc_dai *cpu_dai,
+ int clk_id, unsigned int freq, int dir)
+{
+ struct stm32_sai_sub_data *sai = snd_soc_dai_get_drvdata(cpu_dai);
+ int ret;
+
+ if (dir == SND_SOC_CLOCK_OUT && sai->sai_mclk) {
+ ret = stm32_sai_sub_reg_up(sai, STM_SAI_CR1_REGX,
+ SAI_XCR1_NODIV,
+ freq ? 0 : SAI_XCR1_NODIV);
+ if (ret < 0)
+ return ret;
+
+ /* Assume shutdown if requested frequency is 0Hz */
+ if (!freq) {
+ /* Release mclk rate only if rate was actually set */
+ if (sai->mclk_rate) {
+ clk_rate_exclusive_put(sai->sai_mclk);
+ sai->mclk_rate = 0;
+ }
+ return 0;
+ }
+
+ /* If master clock is used, set parent clock now */
+ ret = stm32_sai_set_parent_clock(sai, freq);
+ if (ret)
+ return ret;
+
+ ret = clk_set_rate_exclusive(sai->sai_mclk, freq);
+ if (ret) {
+ dev_err(cpu_dai->dev,
+ ret == -EBUSY ?
+ "Active streams have incompatible rates" :
+ "Could not set mclk rate\n");
+ return ret;
+ }
+
+ dev_dbg(cpu_dai->dev, "SAI MCLK frequency is %uHz\n", freq);
+ sai->mclk_rate = freq;
+ }
+
+ return 0;
+}
+
+static int stm32_sai_set_dai_tdm_slot(struct snd_soc_dai *cpu_dai, u32 tx_mask,
+ u32 rx_mask, int slots, int slot_width)
+{
+ struct stm32_sai_sub_data *sai = snd_soc_dai_get_drvdata(cpu_dai);
+ int slotr, slotr_mask, slot_size;
+
+ if (STM_SAI_PROTOCOL_IS_SPDIF(sai)) {
+ dev_warn(cpu_dai->dev, "Slot setting relevant only for TDM\n");
+ return 0;
+ }
+
+ dev_dbg(cpu_dai->dev, "Masks tx/rx:%#x/%#x, slots:%d, width:%d\n",
+ tx_mask, rx_mask, slots, slot_width);
+
+ switch (slot_width) {
+ case 16:
+ slot_size = SAI_SLOT_SIZE_16;
+ break;
+ case 32:
+ slot_size = SAI_SLOT_SIZE_32;
+ break;
+ default:
+ slot_size = SAI_SLOT_SIZE_AUTO;
+ break;
+ }
+
+ slotr = SAI_XSLOTR_SLOTSZ_SET(slot_size) |
+ SAI_XSLOTR_NBSLOT_SET(slots - 1);
+ slotr_mask = SAI_XSLOTR_SLOTSZ_MASK | SAI_XSLOTR_NBSLOT_MASK;
+
+ /* tx/rx mask set in machine init, if slot number defined in DT */
+ if (STM_SAI_IS_PLAYBACK(sai)) {
+ sai->slot_mask = tx_mask;
+ slotr |= SAI_XSLOTR_SLOTEN_SET(tx_mask);
+ }
+
+ if (STM_SAI_IS_CAPTURE(sai)) {
+ sai->slot_mask = rx_mask;
+ slotr |= SAI_XSLOTR_SLOTEN_SET(rx_mask);
+ }
+
+ slotr_mask |= SAI_XSLOTR_SLOTEN_MASK;
+
+ stm32_sai_sub_reg_up(sai, STM_SAI_SLOTR_REGX, slotr_mask, slotr);
+
+ sai->slot_width = slot_width;
+ sai->slots = slots;
+
+ return 0;
+}
+
+static int stm32_sai_set_dai_fmt(struct snd_soc_dai *cpu_dai, unsigned int fmt)
+{
+ struct stm32_sai_sub_data *sai = snd_soc_dai_get_drvdata(cpu_dai);
+ int cr1, frcr = 0;
+ int cr1_mask, frcr_mask = 0;
+ int ret;
+
+ dev_dbg(cpu_dai->dev, "fmt %x\n", fmt);
+
+ /* Do not generate master by default */
+ cr1 = SAI_XCR1_NODIV;
+ cr1_mask = SAI_XCR1_NODIV;
+
+ cr1_mask |= SAI_XCR1_PRTCFG_MASK;
+ if (STM_SAI_PROTOCOL_IS_SPDIF(sai)) {
+ cr1 |= SAI_XCR1_PRTCFG_SET(SAI_SPDIF_PROTOCOL);
+ goto conf_update;
+ }
+
+ cr1 |= SAI_XCR1_PRTCFG_SET(SAI_FREE_PROTOCOL);
+
+ switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
+ /* SCK active high for all protocols */
+ case SND_SOC_DAIFMT_I2S:
+ cr1 |= SAI_XCR1_CKSTR;
+ frcr |= SAI_XFRCR_FSOFF | SAI_XFRCR_FSDEF;
+ break;
+ /* Left justified */
+ case SND_SOC_DAIFMT_MSB:
+ frcr |= SAI_XFRCR_FSPOL | SAI_XFRCR_FSDEF;
+ break;
+ /* Right justified */
+ case SND_SOC_DAIFMT_LSB:
+ frcr |= SAI_XFRCR_FSPOL | SAI_XFRCR_FSDEF;
+ break;
+ case SND_SOC_DAIFMT_DSP_A:
+ frcr |= SAI_XFRCR_FSPOL | SAI_XFRCR_FSOFF;
+ break;
+ case SND_SOC_DAIFMT_DSP_B:
+ frcr |= SAI_XFRCR_FSPOL;
+ break;
+ default:
+ dev_err(cpu_dai->dev, "Unsupported protocol %#x\n",
+ fmt & SND_SOC_DAIFMT_FORMAT_MASK);
+ return -EINVAL;
+ }
+
+ cr1_mask |= SAI_XCR1_CKSTR;
+ frcr_mask |= SAI_XFRCR_FSPOL | SAI_XFRCR_FSOFF |
+ SAI_XFRCR_FSDEF;
+
+ /* DAI clock strobing. Invert setting previously set */
+ switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
+ case SND_SOC_DAIFMT_NB_NF:
+ break;
+ case SND_SOC_DAIFMT_IB_NF:
+ cr1 ^= SAI_XCR1_CKSTR;
+ break;
+ case SND_SOC_DAIFMT_NB_IF:
+ frcr ^= SAI_XFRCR_FSPOL;
+ break;
+ case SND_SOC_DAIFMT_IB_IF:
+ /* Invert fs & sck */
+ cr1 ^= SAI_XCR1_CKSTR;
+ frcr ^= SAI_XFRCR_FSPOL;
+ break;
+ default:
+ dev_err(cpu_dai->dev, "Unsupported strobing %#x\n",
+ fmt & SND_SOC_DAIFMT_INV_MASK);
+ return -EINVAL;
+ }
+ cr1_mask |= SAI_XCR1_CKSTR;
+ frcr_mask |= SAI_XFRCR_FSPOL;
+
+ stm32_sai_sub_reg_up(sai, STM_SAI_FRCR_REGX, frcr_mask, frcr);
+
+ /* DAI clock master masks */
+ switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) {
+ case SND_SOC_DAIFMT_BC_FC:
+ /* codec is master */
+ cr1 |= SAI_XCR1_SLAVE;
+ sai->master = false;
+ break;
+ case SND_SOC_DAIFMT_BP_FP:
+ sai->master = true;
+ break;
+ default:
+ dev_err(cpu_dai->dev, "Unsupported mode %#x\n",
+ fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK);
+ return -EINVAL;
+ }
+
+ /* Set slave mode if sub-block is synchronized with another SAI */
+ if (sai->sync) {
+ dev_dbg(cpu_dai->dev, "Synchronized SAI configured as slave\n");
+ cr1 |= SAI_XCR1_SLAVE;
+ sai->master = false;
+ }
+
+ cr1_mask |= SAI_XCR1_SLAVE;
+
+conf_update:
+ ret = stm32_sai_sub_reg_up(sai, STM_SAI_CR1_REGX, cr1_mask, cr1);
+ if (ret < 0) {
+ dev_err(cpu_dai->dev, "Failed to update CR1 register\n");
+ return ret;
+ }
+
+ sai->fmt = fmt;
+
+ return 0;
+}
+
+static int stm32_sai_startup(struct snd_pcm_substream *substream,
+ struct snd_soc_dai *cpu_dai)
+{
+ struct stm32_sai_sub_data *sai = snd_soc_dai_get_drvdata(cpu_dai);
+ int imr, cr2, ret;
+ unsigned long flags;
+
+ spin_lock_irqsave(&sai->irq_lock, flags);
+ sai->substream = substream;
+ spin_unlock_irqrestore(&sai->irq_lock, flags);
+
+ if (STM_SAI_PROTOCOL_IS_SPDIF(sai)) {
+ snd_pcm_hw_constraint_mask64(substream->runtime,
+ SNDRV_PCM_HW_PARAM_FORMAT,
+ SNDRV_PCM_FMTBIT_S32_LE);
+ snd_pcm_hw_constraint_single(substream->runtime,
+ SNDRV_PCM_HW_PARAM_CHANNELS, 2);
+ }
+
+ ret = clk_prepare_enable(sai->sai_ck);
+ if (ret < 0) {
+ dev_err(cpu_dai->dev, "Failed to enable clock: %d\n", ret);
+ return ret;
+ }
+
+ /* Enable ITs */
+ stm32_sai_sub_reg_wr(sai, STM_SAI_CLRFR_REGX,
+ SAI_XCLRFR_MASK, SAI_XCLRFR_MASK);
+
+ imr = SAI_XIMR_OVRUDRIE;
+ if (STM_SAI_IS_CAPTURE(sai)) {
+ stm32_sai_sub_reg_rd(sai, STM_SAI_CR2_REGX, &cr2);
+ if (cr2 & SAI_XCR2_MUTECNT_MASK)
+ imr |= SAI_XIMR_MUTEDETIE;
+ }
+
+ if (sai->master)
+ imr |= SAI_XIMR_WCKCFGIE;
+ else
+ imr |= SAI_XIMR_AFSDETIE | SAI_XIMR_LFSDETIE;
+
+ stm32_sai_sub_reg_up(sai, STM_SAI_IMR_REGX,
+ SAI_XIMR_MASK, imr);
+
+ return 0;
+}
+
+static int stm32_sai_set_config(struct snd_soc_dai *cpu_dai,
+ struct snd_pcm_substream *substream,
+ struct snd_pcm_hw_params *params)
+{
+ struct stm32_sai_sub_data *sai = snd_soc_dai_get_drvdata(cpu_dai);
+ int cr1, cr1_mask, ret;
+
+ /*
+ * DMA bursts increment is set to 4 words.
+ * SAI fifo threshold is set to half fifo, to keep enough space
+ * for DMA incoming bursts.
+ */
+ stm32_sai_sub_reg_wr(sai, STM_SAI_CR2_REGX,
+ SAI_XCR2_FFLUSH | SAI_XCR2_FTH_MASK,
+ SAI_XCR2_FFLUSH |
+ SAI_XCR2_FTH_SET(STM_SAI_FIFO_TH_HALF));
+
+ /* DS bits in CR1 not set for SPDIF (size forced to 24 bits).*/
+ if (STM_SAI_PROTOCOL_IS_SPDIF(sai)) {
+ sai->spdif_frm_cnt = 0;
+ return 0;
+ }
+
+ /* Mode, data format and channel config */
+ cr1_mask = SAI_XCR1_DS_MASK;
+ switch (params_format(params)) {
+ case SNDRV_PCM_FORMAT_S8:
+ cr1 = SAI_XCR1_DS_SET(SAI_DATASIZE_8);
+ break;
+ case SNDRV_PCM_FORMAT_S16_LE:
+ cr1 = SAI_XCR1_DS_SET(SAI_DATASIZE_16);
+ break;
+ case SNDRV_PCM_FORMAT_S32_LE:
+ cr1 = SAI_XCR1_DS_SET(SAI_DATASIZE_32);
+ break;
+ default:
+ dev_err(cpu_dai->dev, "Data format not supported\n");
+ return -EINVAL;
+ }
+
+ cr1_mask |= SAI_XCR1_MONO;
+ if ((sai->slots == 2) && (params_channels(params) == 1))
+ cr1 |= SAI_XCR1_MONO;
+
+ ret = stm32_sai_sub_reg_up(sai, STM_SAI_CR1_REGX, cr1_mask, cr1);
+ if (ret < 0) {
+ dev_err(cpu_dai->dev, "Failed to update CR1 register\n");
+ return ret;
+ }
+
+ return 0;
+}
+
+static int stm32_sai_set_slots(struct snd_soc_dai *cpu_dai)
+{
+ struct stm32_sai_sub_data *sai = snd_soc_dai_get_drvdata(cpu_dai);
+ int slotr, slot_sz;
+
+ stm32_sai_sub_reg_rd(sai, STM_SAI_SLOTR_REGX, &slotr);
+
+ /*
+ * If SLOTSZ is set to auto in SLOTR, align slot width on data size
+ * By default slot width = data size, if not forced from DT
+ */
+ slot_sz = slotr & SAI_XSLOTR_SLOTSZ_MASK;
+ if (slot_sz == SAI_XSLOTR_SLOTSZ_SET(SAI_SLOT_SIZE_AUTO))
+ sai->slot_width = sai->data_size;
+
+ if (sai->slot_width < sai->data_size) {
+ dev_err(cpu_dai->dev,
+ "Data size %d larger than slot width\n",
+ sai->data_size);
+ return -EINVAL;
+ }
+
+ /* Slot number is set to 2, if not specified in DT */
+ if (!sai->slots)
+ sai->slots = 2;
+
+ /* The number of slots in the audio frame is equal to NBSLOT[3:0] + 1*/
+ stm32_sai_sub_reg_up(sai, STM_SAI_SLOTR_REGX,
+ SAI_XSLOTR_NBSLOT_MASK,
+ SAI_XSLOTR_NBSLOT_SET((sai->slots - 1)));
+
+ /* Set default slots mask if not already set from DT */
+ if (!(slotr & SAI_XSLOTR_SLOTEN_MASK)) {
+ sai->slot_mask = (1 << sai->slots) - 1;
+ stm32_sai_sub_reg_up(sai,
+ STM_SAI_SLOTR_REGX, SAI_XSLOTR_SLOTEN_MASK,
+ SAI_XSLOTR_SLOTEN_SET(sai->slot_mask));
+ }
+
+ dev_dbg(cpu_dai->dev, "Slots %d, slot width %d\n",
+ sai->slots, sai->slot_width);
+
+ return 0;
+}
+
+static void stm32_sai_set_frame(struct snd_soc_dai *cpu_dai)
+{
+ struct stm32_sai_sub_data *sai = snd_soc_dai_get_drvdata(cpu_dai);
+ int fs_active, offset, format;
+ int frcr, frcr_mask;
+
+ format = sai->fmt & SND_SOC_DAIFMT_FORMAT_MASK;
+ sai->fs_length = sai->slot_width * sai->slots;
+
+ fs_active = sai->fs_length / 2;
+ if ((format == SND_SOC_DAIFMT_DSP_A) ||
+ (format == SND_SOC_DAIFMT_DSP_B))
+ fs_active = 1;
+
+ frcr = SAI_XFRCR_FRL_SET((sai->fs_length - 1));
+ frcr |= SAI_XFRCR_FSALL_SET((fs_active - 1));
+ frcr_mask = SAI_XFRCR_FRL_MASK | SAI_XFRCR_FSALL_MASK;
+
+ dev_dbg(cpu_dai->dev, "Frame length %d, frame active %d\n",
+ sai->fs_length, fs_active);
+
+ stm32_sai_sub_reg_up(sai, STM_SAI_FRCR_REGX, frcr_mask, frcr);
+
+ if ((sai->fmt & SND_SOC_DAIFMT_FORMAT_MASK) == SND_SOC_DAIFMT_LSB) {
+ offset = sai->slot_width - sai->data_size;
+
+ stm32_sai_sub_reg_up(sai, STM_SAI_SLOTR_REGX,
+ SAI_XSLOTR_FBOFF_MASK,
+ SAI_XSLOTR_FBOFF_SET(offset));
+ }
+}
+
+static void stm32_sai_init_iec958_status(struct stm32_sai_sub_data *sai)
+{
+ unsigned char *cs = sai->iec958.status;
+
+ cs[0] = IEC958_AES0_CON_NOT_COPYRIGHT | IEC958_AES0_CON_EMPHASIS_NONE;
+ cs[1] = IEC958_AES1_CON_GENERAL;
+ cs[2] = IEC958_AES2_CON_SOURCE_UNSPEC | IEC958_AES2_CON_CHANNEL_UNSPEC;
+ cs[3] = IEC958_AES3_CON_CLOCK_1000PPM | IEC958_AES3_CON_FS_NOTID;
+}
+
+static void stm32_sai_set_iec958_status(struct stm32_sai_sub_data *sai,
+ struct snd_pcm_runtime *runtime)
+{
+ if (!runtime)
+ return;
+
+ /* Force the sample rate according to runtime rate */
+ mutex_lock(&sai->ctrl_lock);
+ switch (runtime->rate) {
+ case 22050:
+ sai->iec958.status[3] = IEC958_AES3_CON_FS_22050;
+ break;
+ case 44100:
+ sai->iec958.status[3] = IEC958_AES3_CON_FS_44100;
+ break;
+ case 88200:
+ sai->iec958.status[3] = IEC958_AES3_CON_FS_88200;
+ break;
+ case 176400:
+ sai->iec958.status[3] = IEC958_AES3_CON_FS_176400;
+ break;
+ case 24000:
+ sai->iec958.status[3] = IEC958_AES3_CON_FS_24000;
+ break;
+ case 48000:
+ sai->iec958.status[3] = IEC958_AES3_CON_FS_48000;
+ break;
+ case 96000:
+ sai->iec958.status[3] = IEC958_AES3_CON_FS_96000;
+ break;
+ case 192000:
+ sai->iec958.status[3] = IEC958_AES3_CON_FS_192000;
+ break;
+ case 32000:
+ sai->iec958.status[3] = IEC958_AES3_CON_FS_32000;
+ break;
+ default:
+ sai->iec958.status[3] = IEC958_AES3_CON_FS_NOTID;
+ break;
+ }
+ mutex_unlock(&sai->ctrl_lock);
+}
+
+static int stm32_sai_configure_clock(struct snd_soc_dai *cpu_dai,
+ struct snd_pcm_hw_params *params)
+{
+ struct stm32_sai_sub_data *sai = snd_soc_dai_get_drvdata(cpu_dai);
+ int div = 0, cr1 = 0;
+ int sai_clk_rate, mclk_ratio, den;
+ unsigned int rate = params_rate(params);
+ int ret;
+
+ if (!sai->sai_mclk) {
+ ret = stm32_sai_set_parent_clock(sai, rate);
+ if (ret)
+ return ret;
+ }
+ sai_clk_rate = clk_get_rate(sai->sai_ck);
+
+ if (STM_SAI_IS_F4(sai->pdata)) {
+ /* mclk on (NODIV=0)
+ * mclk_rate = 256 * fs
+ * MCKDIV = 0 if sai_ck < 3/2 * mclk_rate
+ * MCKDIV = sai_ck / (2 * mclk_rate) otherwise
+ * mclk off (NODIV=1)
+ * MCKDIV ignored. sck = sai_ck
+ */
+ if (!sai->mclk_rate)
+ return 0;
+
+ if (2 * sai_clk_rate >= 3 * sai->mclk_rate) {
+ div = stm32_sai_get_clk_div(sai, sai_clk_rate,
+ 2 * sai->mclk_rate);
+ if (div < 0)
+ return div;
+ }
+ } else {
+ /*
+ * TDM mode :
+ * mclk on
+ * MCKDIV = sai_ck / (ws x 256) (NOMCK=0. OSR=0)
+ * MCKDIV = sai_ck / (ws x 512) (NOMCK=0. OSR=1)
+ * mclk off
+ * MCKDIV = sai_ck / (frl x ws) (NOMCK=1)
+ * Note: NOMCK/NODIV correspond to same bit.
+ */
+ if (STM_SAI_PROTOCOL_IS_SPDIF(sai)) {
+ div = stm32_sai_get_clk_div(sai, sai_clk_rate,
+ rate * 128);
+ if (div < 0)
+ return div;
+ } else {
+ if (sai->mclk_rate) {
+ mclk_ratio = sai->mclk_rate / rate;
+ if (mclk_ratio == 512) {
+ cr1 = SAI_XCR1_OSR;
+ } else if (mclk_ratio != 256) {
+ dev_err(cpu_dai->dev,
+ "Wrong mclk ratio %d\n",
+ mclk_ratio);
+ return -EINVAL;
+ }
+
+ stm32_sai_sub_reg_up(sai,
+ STM_SAI_CR1_REGX,
+ SAI_XCR1_OSR, cr1);
+
+ div = stm32_sai_get_clk_div(sai, sai_clk_rate,
+ sai->mclk_rate);
+ if (div < 0)
+ return div;
+ } else {
+ /* mclk-fs not set, master clock not active */
+ den = sai->fs_length * params_rate(params);
+ div = stm32_sai_get_clk_div(sai, sai_clk_rate,
+ den);
+ if (div < 0)
+ return div;
+ }
+ }
+ }
+
+ return stm32_sai_set_clk_div(sai, div);
+}
+
+static int stm32_sai_hw_params(struct snd_pcm_substream *substream,
+ struct snd_pcm_hw_params *params,
+ struct snd_soc_dai *cpu_dai)
+{
+ struct stm32_sai_sub_data *sai = snd_soc_dai_get_drvdata(cpu_dai);
+ int ret;
+
+ sai->data_size = params_width(params);
+
+ if (STM_SAI_PROTOCOL_IS_SPDIF(sai)) {
+ /* Rate not already set in runtime structure */
+ substream->runtime->rate = params_rate(params);
+ stm32_sai_set_iec958_status(sai, substream->runtime);
+ } else {
+ ret = stm32_sai_set_slots(cpu_dai);
+ if (ret < 0)
+ return ret;
+ stm32_sai_set_frame(cpu_dai);
+ }
+
+ ret = stm32_sai_set_config(cpu_dai, substream, params);
+ if (ret)
+ return ret;
+
+ if (sai->master)
+ ret = stm32_sai_configure_clock(cpu_dai, params);
+
+ return ret;
+}
+
+static int stm32_sai_trigger(struct snd_pcm_substream *substream, int cmd,
+ struct snd_soc_dai *cpu_dai)
+{
+ struct stm32_sai_sub_data *sai = snd_soc_dai_get_drvdata(cpu_dai);
+ int ret;
+
+ switch (cmd) {
+ case SNDRV_PCM_TRIGGER_START:
+ case SNDRV_PCM_TRIGGER_RESUME:
+ case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
+ dev_dbg(cpu_dai->dev, "Enable DMA and SAI\n");
+
+ stm32_sai_sub_reg_up(sai, STM_SAI_CR1_REGX,
+ SAI_XCR1_DMAEN, SAI_XCR1_DMAEN);
+
+ /* Enable SAI */
+ ret = stm32_sai_sub_reg_up(sai, STM_SAI_CR1_REGX,
+ SAI_XCR1_SAIEN, SAI_XCR1_SAIEN);
+ if (ret < 0)
+ dev_err(cpu_dai->dev, "Failed to update CR1 register\n");
+ break;
+ case SNDRV_PCM_TRIGGER_SUSPEND:
+ case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
+ case SNDRV_PCM_TRIGGER_STOP:
+ dev_dbg(cpu_dai->dev, "Disable DMA and SAI\n");
+
+ stm32_sai_sub_reg_up(sai, STM_SAI_IMR_REGX,
+ SAI_XIMR_MASK, 0);
+
+ stm32_sai_sub_reg_up(sai, STM_SAI_CR1_REGX,
+ SAI_XCR1_SAIEN,
+ (unsigned int)~SAI_XCR1_SAIEN);
+
+ ret = stm32_sai_sub_reg_up(sai, STM_SAI_CR1_REGX,
+ SAI_XCR1_DMAEN,
+ (unsigned int)~SAI_XCR1_DMAEN);
+ if (ret < 0)
+ dev_err(cpu_dai->dev, "Failed to update CR1 register\n");
+
+ if (STM_SAI_PROTOCOL_IS_SPDIF(sai))
+ sai->spdif_frm_cnt = 0;
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ return ret;
+}
+
+static void stm32_sai_shutdown(struct snd_pcm_substream *substream,
+ struct snd_soc_dai *cpu_dai)
+{
+ struct stm32_sai_sub_data *sai = snd_soc_dai_get_drvdata(cpu_dai);
+ unsigned long flags;
+
+ stm32_sai_sub_reg_up(sai, STM_SAI_IMR_REGX, SAI_XIMR_MASK, 0);
+
+ clk_disable_unprepare(sai->sai_ck);
+
+ spin_lock_irqsave(&sai->irq_lock, flags);
+ sai->substream = NULL;
+ spin_unlock_irqrestore(&sai->irq_lock, flags);
+}
+
+static int stm32_sai_pcm_new(struct snd_soc_pcm_runtime *rtd,
+ struct snd_soc_dai *cpu_dai)
+{
+ struct stm32_sai_sub_data *sai = dev_get_drvdata(cpu_dai->dev);
+ struct snd_kcontrol_new knew = iec958_ctls;
+
+ if (STM_SAI_PROTOCOL_IS_SPDIF(sai)) {
+ dev_dbg(&sai->pdev->dev, "%s: register iec controls", __func__);
+ knew.device = rtd->pcm->device;
+ return snd_ctl_add(rtd->pcm->card, snd_ctl_new1(&knew, sai));
+ }
+
+ return 0;
+}
+
+static int stm32_sai_dai_probe(struct snd_soc_dai *cpu_dai)
+{
+ struct stm32_sai_sub_data *sai = dev_get_drvdata(cpu_dai->dev);
+ int cr1 = 0, cr1_mask, ret;
+
+ sai->cpu_dai = cpu_dai;
+
+ sai->dma_params.addr = (dma_addr_t)(sai->phys_addr + STM_SAI_DR_REGX);
+ /*
+ * DMA supports 4, 8 or 16 burst sizes. Burst size 4 is the best choice,
+ * as it allows bytes, half-word and words transfers. (See DMA fifos
+ * constraints).
+ */
+ sai->dma_params.maxburst = 4;
+ if (sai->pdata->conf.fifo_size < 8)
+ sai->dma_params.maxburst = 1;
+ /* Buswidth will be set by framework at runtime */
+ sai->dma_params.addr_width = DMA_SLAVE_BUSWIDTH_UNDEFINED;
+
+ if (STM_SAI_IS_PLAYBACK(sai))
+ snd_soc_dai_init_dma_data(cpu_dai, &sai->dma_params, NULL);
+ else
+ snd_soc_dai_init_dma_data(cpu_dai, NULL, &sai->dma_params);
+
+ /* Next settings are not relevant for spdif mode */
+ if (STM_SAI_PROTOCOL_IS_SPDIF(sai))
+ return 0;
+
+ cr1_mask = SAI_XCR1_RX_TX;
+ if (STM_SAI_IS_CAPTURE(sai))
+ cr1 |= SAI_XCR1_RX_TX;
+
+ /* Configure synchronization */
+ if (sai->sync == SAI_SYNC_EXTERNAL) {
+ /* Configure synchro client and provider */
+ ret = sai->pdata->set_sync(sai->pdata, sai->np_sync_provider,
+ sai->synco, sai->synci);
+ if (ret)
+ return ret;
+ }
+
+ cr1_mask |= SAI_XCR1_SYNCEN_MASK;
+ cr1 |= SAI_XCR1_SYNCEN_SET(sai->sync);
+
+ return stm32_sai_sub_reg_up(sai, STM_SAI_CR1_REGX, cr1_mask, cr1);
+}
+
+static const struct snd_soc_dai_ops stm32_sai_pcm_dai_ops = {
+ .probe = stm32_sai_dai_probe,
+ .set_sysclk = stm32_sai_set_sysclk,
+ .set_fmt = stm32_sai_set_dai_fmt,
+ .set_tdm_slot = stm32_sai_set_dai_tdm_slot,
+ .startup = stm32_sai_startup,
+ .hw_params = stm32_sai_hw_params,
+ .trigger = stm32_sai_trigger,
+ .shutdown = stm32_sai_shutdown,
+ .pcm_new = stm32_sai_pcm_new,
+};
+
+static const struct snd_soc_dai_ops stm32_sai_pcm_dai_ops2 = {
+ .probe = stm32_sai_dai_probe,
+ .set_sysclk = stm32_sai_set_sysclk,
+ .set_fmt = stm32_sai_set_dai_fmt,
+ .set_tdm_slot = stm32_sai_set_dai_tdm_slot,
+ .startup = stm32_sai_startup,
+ .hw_params = stm32_sai_hw_params,
+ .trigger = stm32_sai_trigger,
+ .shutdown = stm32_sai_shutdown,
+};
+
+static int stm32_sai_pcm_process_spdif(struct snd_pcm_substream *substream,
+ int channel, unsigned long hwoff,
+ unsigned long bytes)
+{
+ struct snd_pcm_runtime *runtime = substream->runtime;
+ struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
+ struct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(rtd, 0);
+ struct stm32_sai_sub_data *sai = dev_get_drvdata(cpu_dai->dev);
+ int *ptr = (int *)(runtime->dma_area + hwoff +
+ channel * (runtime->dma_bytes / runtime->channels));
+ ssize_t cnt = bytes_to_samples(runtime, bytes);
+ unsigned int frm_cnt = sai->spdif_frm_cnt;
+ unsigned int byte;
+ unsigned int mask;
+
+ do {
+ *ptr = ((*ptr >> 8) & 0x00ffffff);
+
+ /* Set channel status bit */
+ byte = frm_cnt >> 3;
+ mask = 1 << (frm_cnt - (byte << 3));
+ if (sai->iec958.status[byte] & mask)
+ *ptr |= 0x04000000;
+ ptr++;
+
+ if (!(cnt % 2))
+ frm_cnt++;
+
+ if (frm_cnt == SAI_IEC60958_BLOCK_FRAMES)
+ frm_cnt = 0;
+ } while (--cnt);
+ sai->spdif_frm_cnt = frm_cnt;
+
+ return 0;
+}
+
+/* No support of mmap in S/PDIF mode */
+static const struct snd_pcm_hardware stm32_sai_pcm_hw_spdif = {
+ .info = SNDRV_PCM_INFO_INTERLEAVED,
+ .buffer_bytes_max = 8 * PAGE_SIZE,
+ .period_bytes_min = 1024,
+ .period_bytes_max = PAGE_SIZE,
+ .periods_min = 2,
+ .periods_max = 8,
+};
+
+static const struct snd_pcm_hardware stm32_sai_pcm_hw = {
+ .info = SNDRV_PCM_INFO_INTERLEAVED | SNDRV_PCM_INFO_MMAP,
+ .buffer_bytes_max = 8 * PAGE_SIZE,
+ .period_bytes_min = 1024, /* 5ms at 48kHz */
+ .period_bytes_max = PAGE_SIZE,
+ .periods_min = 2,
+ .periods_max = 8,
+};
+
+static struct snd_soc_dai_driver stm32_sai_playback_dai = {
+ .id = 1, /* avoid call to fmt_single_name() */
+ .playback = {
+ .channels_min = 1,
+ .channels_max = 16,
+ .rate_min = 8000,
+ .rate_max = 192000,
+ .rates = SNDRV_PCM_RATE_CONTINUOUS,
+ /* DMA does not support 24 bits transfers */
+ .formats =
+ SNDRV_PCM_FMTBIT_S8 |
+ SNDRV_PCM_FMTBIT_S16_LE |
+ SNDRV_PCM_FMTBIT_S32_LE,
+ },
+ .ops = &stm32_sai_pcm_dai_ops,
+};
+
+static struct snd_soc_dai_driver stm32_sai_capture_dai = {
+ .id = 1, /* avoid call to fmt_single_name() */
+ .capture = {
+ .channels_min = 1,
+ .channels_max = 16,
+ .rate_min = 8000,
+ .rate_max = 192000,
+ .rates = SNDRV_PCM_RATE_CONTINUOUS,
+ /* DMA does not support 24 bits transfers */
+ .formats =
+ SNDRV_PCM_FMTBIT_S8 |
+ SNDRV_PCM_FMTBIT_S16_LE |
+ SNDRV_PCM_FMTBIT_S32_LE,
+ },
+ .ops = &stm32_sai_pcm_dai_ops2,
+};
+
+static const struct snd_dmaengine_pcm_config stm32_sai_pcm_config = {
+ .pcm_hardware = &stm32_sai_pcm_hw,
+ .prepare_slave_config = snd_dmaengine_pcm_prepare_slave_config,
+};
+
+static const struct snd_dmaengine_pcm_config stm32_sai_pcm_config_spdif = {
+ .pcm_hardware = &stm32_sai_pcm_hw_spdif,
+ .prepare_slave_config = snd_dmaengine_pcm_prepare_slave_config,
+ .process = stm32_sai_pcm_process_spdif,
+};
+
+static const struct snd_soc_component_driver stm32_component = {
+ .name = "stm32-sai",
+ .legacy_dai_naming = 1,
+};
+
+static const struct of_device_id stm32_sai_sub_ids[] = {
+ { .compatible = "st,stm32-sai-sub-a",
+ .data = (void *)STM_SAI_A_ID},
+ { .compatible = "st,stm32-sai-sub-b",
+ .data = (void *)STM_SAI_B_ID},
+ {}
+};
+MODULE_DEVICE_TABLE(of, stm32_sai_sub_ids);
+
+static int stm32_sai_sub_parse_of(struct platform_device *pdev,
+ struct stm32_sai_sub_data *sai)
+{
+ struct device_node *np = pdev->dev.of_node;
+ struct resource *res;
+ void __iomem *base;
+ struct of_phandle_args args;
+ int ret;
+
+ if (!np)
+ return -ENODEV;
+
+ base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
+ if (IS_ERR(base))
+ return PTR_ERR(base);
+
+ sai->phys_addr = res->start;
+
+ sai->regmap_config = &stm32_sai_sub_regmap_config_f4;
+ /* Note: PDM registers not available for sub-block B */
+ if (STM_SAI_HAS_PDM(sai) && STM_SAI_IS_SUB_A(sai))
+ sai->regmap_config = &stm32_sai_sub_regmap_config_h7;
+
+ /*
+ * Do not manage peripheral clock through regmap framework as this
+ * can lead to circular locking issue with sai master clock provider.
+ * Manage peripheral clock directly in driver instead.
+ */
+ sai->regmap = devm_regmap_init_mmio(&pdev->dev, base,
+ sai->regmap_config);
+ if (IS_ERR(sai->regmap))
+ return dev_err_probe(&pdev->dev, PTR_ERR(sai->regmap),
+ "Regmap init error\n");
+
+ /* Get direction property */
+ if (of_property_match_string(np, "dma-names", "tx") >= 0) {
+ sai->dir = SNDRV_PCM_STREAM_PLAYBACK;
+ } else if (of_property_match_string(np, "dma-names", "rx") >= 0) {
+ sai->dir = SNDRV_PCM_STREAM_CAPTURE;
+ } else {
+ dev_err(&pdev->dev, "Unsupported direction\n");
+ return -EINVAL;
+ }
+
+ /* Get spdif iec60958 property */
+ sai->spdif = false;
+ if (of_property_present(np, "st,iec60958")) {
+ if (!STM_SAI_HAS_SPDIF(sai) ||
+ sai->dir == SNDRV_PCM_STREAM_CAPTURE) {
+ dev_err(&pdev->dev, "S/PDIF IEC60958 not supported\n");
+ return -EINVAL;
+ }
+ stm32_sai_init_iec958_status(sai);
+ sai->spdif = true;
+ sai->master = true;
+ }
+
+ /* Get synchronization property */
+ args.np = NULL;
+ ret = of_parse_phandle_with_fixed_args(np, "st,sync", 1, 0, &args);
+ if (ret < 0 && ret != -ENOENT) {
+ dev_err(&pdev->dev, "Failed to get st,sync property\n");
+ return ret;
+ }
+
+ sai->sync = SAI_SYNC_NONE;
+ if (args.np) {
+ if (args.np == np) {
+ dev_err(&pdev->dev, "%pOFn sync own reference\n", np);
+ of_node_put(args.np);
+ return -EINVAL;
+ }
+
+ sai->np_sync_provider = of_get_parent(args.np);
+ if (!sai->np_sync_provider) {
+ dev_err(&pdev->dev, "%pOFn parent node not found\n",
+ np);
+ of_node_put(args.np);
+ return -ENODEV;
+ }
+
+ sai->sync = SAI_SYNC_INTERNAL;
+ if (sai->np_sync_provider != sai->pdata->pdev->dev.of_node) {
+ if (!STM_SAI_HAS_EXT_SYNC(sai)) {
+ dev_err(&pdev->dev,
+ "External synchro not supported\n");
+ of_node_put(args.np);
+ return -EINVAL;
+ }
+ sai->sync = SAI_SYNC_EXTERNAL;
+
+ sai->synci = args.args[0];
+ if (sai->synci < 1 ||
+ (sai->synci > (SAI_GCR_SYNCIN_MAX + 1))) {
+ dev_err(&pdev->dev, "Wrong SAI index\n");
+ of_node_put(args.np);
+ return -EINVAL;
+ }
+
+ if (of_property_match_string(args.np, "compatible",
+ "st,stm32-sai-sub-a") >= 0)
+ sai->synco = STM_SAI_SYNC_OUT_A;
+
+ if (of_property_match_string(args.np, "compatible",
+ "st,stm32-sai-sub-b") >= 0)
+ sai->synco = STM_SAI_SYNC_OUT_B;
+
+ if (!sai->synco) {
+ dev_err(&pdev->dev, "Unknown SAI sub-block\n");
+ of_node_put(args.np);
+ return -EINVAL;
+ }
+ }
+
+ dev_dbg(&pdev->dev, "%s synchronized with %s\n",
+ pdev->name, args.np->full_name);
+ }
+
+ of_node_put(args.np);
+ sai->sai_ck = devm_clk_get(&pdev->dev, "sai_ck");
+ if (IS_ERR(sai->sai_ck))
+ return dev_err_probe(&pdev->dev, PTR_ERR(sai->sai_ck),
+ "Missing kernel clock sai_ck\n");
+
+ ret = clk_prepare(sai->pdata->pclk);
+ if (ret < 0)
+ return ret;
+
+ if (STM_SAI_IS_F4(sai->pdata))
+ return 0;
+
+ /* Register mclk provider if requested */
+ if (of_property_present(np, "#clock-cells")) {
+ ret = stm32_sai_add_mclk_provider(sai);
+ if (ret < 0)
+ return ret;
+ } else {
+ sai->sai_mclk = devm_clk_get_optional(&pdev->dev, "MCLK");
+ if (IS_ERR(sai->sai_mclk))
+ return PTR_ERR(sai->sai_mclk);
+ }
+
+ return 0;
+}
+
+static int stm32_sai_sub_probe(struct platform_device *pdev)
+{
+ struct stm32_sai_sub_data *sai;
+ const struct of_device_id *of_id;
+ const struct snd_dmaengine_pcm_config *conf = &stm32_sai_pcm_config;
+ int ret;
+
+ sai = devm_kzalloc(&pdev->dev, sizeof(*sai), GFP_KERNEL);
+ if (!sai)
+ return -ENOMEM;
+
+ of_id = of_match_device(stm32_sai_sub_ids, &pdev->dev);
+ if (!of_id)
+ return -EINVAL;
+ sai->id = (uintptr_t)of_id->data;
+
+ sai->pdev = pdev;
+ mutex_init(&sai->ctrl_lock);
+ spin_lock_init(&sai->irq_lock);
+ platform_set_drvdata(pdev, sai);
+
+ sai->pdata = dev_get_drvdata(pdev->dev.parent);
+ if (!sai->pdata) {
+ dev_err(&pdev->dev, "Parent device data not available\n");
+ return -EINVAL;
+ }
+
+ ret = stm32_sai_sub_parse_of(pdev, sai);
+ if (ret)
+ return ret;
+
+ if (STM_SAI_IS_PLAYBACK(sai))
+ sai->cpu_dai_drv = stm32_sai_playback_dai;
+ else
+ sai->cpu_dai_drv = stm32_sai_capture_dai;
+ sai->cpu_dai_drv.name = dev_name(&pdev->dev);
+
+ ret = devm_request_irq(&pdev->dev, sai->pdata->irq, stm32_sai_isr,
+ IRQF_SHARED, dev_name(&pdev->dev), sai);
+ if (ret) {
+ dev_err(&pdev->dev, "IRQ request returned %d\n", ret);
+ return ret;
+ }
+
+ if (STM_SAI_PROTOCOL_IS_SPDIF(sai))
+ conf = &stm32_sai_pcm_config_spdif;
+
+ ret = snd_dmaengine_pcm_register(&pdev->dev, conf, 0);
+ if (ret)
+ return dev_err_probe(&pdev->dev, ret, "Could not register pcm dma\n");
+
+ ret = snd_soc_register_component(&pdev->dev, &stm32_component,
+ &sai->cpu_dai_drv, 1);
+ if (ret) {
+ snd_dmaengine_pcm_unregister(&pdev->dev);
+ return ret;
+ }
+
+ pm_runtime_enable(&pdev->dev);
+
+ return 0;
+}
+
+static void stm32_sai_sub_remove(struct platform_device *pdev)
+{
+ struct stm32_sai_sub_data *sai = dev_get_drvdata(&pdev->dev);
+
+ clk_unprepare(sai->pdata->pclk);
+ snd_dmaengine_pcm_unregister(&pdev->dev);
+ snd_soc_unregister_component(&pdev->dev);
+ pm_runtime_disable(&pdev->dev);
+}
+
+#ifdef CONFIG_PM_SLEEP
+static int stm32_sai_sub_suspend(struct device *dev)
+{
+ struct stm32_sai_sub_data *sai = dev_get_drvdata(dev);
+ int ret;
+
+ ret = clk_enable(sai->pdata->pclk);
+ if (ret < 0)
+ return ret;
+
+ regcache_cache_only(sai->regmap, true);
+ regcache_mark_dirty(sai->regmap);
+
+ clk_disable(sai->pdata->pclk);
+
+ return 0;
+}
+
+static int stm32_sai_sub_resume(struct device *dev)
+{
+ struct stm32_sai_sub_data *sai = dev_get_drvdata(dev);
+ int ret;
+
+ ret = clk_enable(sai->pdata->pclk);
+ if (ret < 0)
+ return ret;
+
+ regcache_cache_only(sai->regmap, false);
+ ret = regcache_sync(sai->regmap);
+
+ clk_disable(sai->pdata->pclk);
+
+ return ret;
+}
+#endif /* CONFIG_PM_SLEEP */
+
+static const struct dev_pm_ops stm32_sai_sub_pm_ops = {
+ SET_SYSTEM_SLEEP_PM_OPS(stm32_sai_sub_suspend, stm32_sai_sub_resume)
+};
+
+static struct platform_driver stm32_sai_sub_driver = {
+ .driver = {
+ .name = "st,stm32-sai-sub",
+ .of_match_table = stm32_sai_sub_ids,
+ .pm = &stm32_sai_sub_pm_ops,
+ },
+ .probe = stm32_sai_sub_probe,
+ .remove_new = stm32_sai_sub_remove,
+};
+
+module_platform_driver(stm32_sai_sub_driver);
+
+MODULE_DESCRIPTION("STM32 Soc SAI sub-block Interface");
+MODULE_AUTHOR("Olivier Moysan <olivier.moysan@st.com>");
+MODULE_ALIAS("platform:st,stm32-sai-sub");
+MODULE_LICENSE("GPL v2");
diff --git a/sound/soc/stm/stm32_spdifrx.c b/sound/soc/stm/stm32_spdifrx.c
new file mode 100644
index 0000000000..a359b528b2
--- /dev/null
+++ b/sound/soc/stm/stm32_spdifrx.c
@@ -0,0 +1,1087 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * STM32 ALSA SoC Digital Audio Interface (SPDIF-rx) driver.
+ *
+ * Copyright (C) 2017, STMicroelectronics - All Rights Reserved
+ * Author(s): Olivier Moysan <olivier.moysan@st.com> for STMicroelectronics.
+ */
+
+#include <linux/bitfield.h>
+#include <linux/clk.h>
+#include <linux/completion.h>
+#include <linux/delay.h>
+#include <linux/module.h>
+#include <linux/of_platform.h>
+#include <linux/pm_runtime.h>
+#include <linux/regmap.h>
+#include <linux/reset.h>
+
+#include <sound/dmaengine_pcm.h>
+#include <sound/pcm_params.h>
+
+/* SPDIF-rx Register Map */
+#define STM32_SPDIFRX_CR 0x00
+#define STM32_SPDIFRX_IMR 0x04
+#define STM32_SPDIFRX_SR 0x08
+#define STM32_SPDIFRX_IFCR 0x0C
+#define STM32_SPDIFRX_DR 0x10
+#define STM32_SPDIFRX_CSR 0x14
+#define STM32_SPDIFRX_DIR 0x18
+#define STM32_SPDIFRX_VERR 0x3F4
+#define STM32_SPDIFRX_IDR 0x3F8
+#define STM32_SPDIFRX_SIDR 0x3FC
+
+/* Bit definition for SPDIF_CR register */
+#define SPDIFRX_CR_SPDIFEN_SHIFT 0
+#define SPDIFRX_CR_SPDIFEN_MASK GENMASK(1, SPDIFRX_CR_SPDIFEN_SHIFT)
+#define SPDIFRX_CR_SPDIFENSET(x) ((x) << SPDIFRX_CR_SPDIFEN_SHIFT)
+
+#define SPDIFRX_CR_RXDMAEN BIT(2)
+#define SPDIFRX_CR_RXSTEO BIT(3)
+
+#define SPDIFRX_CR_DRFMT_SHIFT 4
+#define SPDIFRX_CR_DRFMT_MASK GENMASK(5, SPDIFRX_CR_DRFMT_SHIFT)
+#define SPDIFRX_CR_DRFMTSET(x) ((x) << SPDIFRX_CR_DRFMT_SHIFT)
+
+#define SPDIFRX_CR_PMSK BIT(6)
+#define SPDIFRX_CR_VMSK BIT(7)
+#define SPDIFRX_CR_CUMSK BIT(8)
+#define SPDIFRX_CR_PTMSK BIT(9)
+#define SPDIFRX_CR_CBDMAEN BIT(10)
+#define SPDIFRX_CR_CHSEL_SHIFT 11
+#define SPDIFRX_CR_CHSEL BIT(SPDIFRX_CR_CHSEL_SHIFT)
+
+#define SPDIFRX_CR_NBTR_SHIFT 12
+#define SPDIFRX_CR_NBTR_MASK GENMASK(13, SPDIFRX_CR_NBTR_SHIFT)
+#define SPDIFRX_CR_NBTRSET(x) ((x) << SPDIFRX_CR_NBTR_SHIFT)
+
+#define SPDIFRX_CR_WFA BIT(14)
+
+#define SPDIFRX_CR_INSEL_SHIFT 16
+#define SPDIFRX_CR_INSEL_MASK GENMASK(18, PDIFRX_CR_INSEL_SHIFT)
+#define SPDIFRX_CR_INSELSET(x) ((x) << SPDIFRX_CR_INSEL_SHIFT)
+
+#define SPDIFRX_CR_CKSEN_SHIFT 20
+#define SPDIFRX_CR_CKSEN BIT(20)
+#define SPDIFRX_CR_CKSBKPEN BIT(21)
+
+/* Bit definition for SPDIFRX_IMR register */
+#define SPDIFRX_IMR_RXNEI BIT(0)
+#define SPDIFRX_IMR_CSRNEIE BIT(1)
+#define SPDIFRX_IMR_PERRIE BIT(2)
+#define SPDIFRX_IMR_OVRIE BIT(3)
+#define SPDIFRX_IMR_SBLKIE BIT(4)
+#define SPDIFRX_IMR_SYNCDIE BIT(5)
+#define SPDIFRX_IMR_IFEIE BIT(6)
+
+#define SPDIFRX_XIMR_MASK GENMASK(6, 0)
+
+/* Bit definition for SPDIFRX_SR register */
+#define SPDIFRX_SR_RXNE BIT(0)
+#define SPDIFRX_SR_CSRNE BIT(1)
+#define SPDIFRX_SR_PERR BIT(2)
+#define SPDIFRX_SR_OVR BIT(3)
+#define SPDIFRX_SR_SBD BIT(4)
+#define SPDIFRX_SR_SYNCD BIT(5)
+#define SPDIFRX_SR_FERR BIT(6)
+#define SPDIFRX_SR_SERR BIT(7)
+#define SPDIFRX_SR_TERR BIT(8)
+
+#define SPDIFRX_SR_WIDTH5_SHIFT 16
+#define SPDIFRX_SR_WIDTH5_MASK GENMASK(30, PDIFRX_SR_WIDTH5_SHIFT)
+#define SPDIFRX_SR_WIDTH5SET(x) ((x) << SPDIFRX_SR_WIDTH5_SHIFT)
+
+/* Bit definition for SPDIFRX_IFCR register */
+#define SPDIFRX_IFCR_PERRCF BIT(2)
+#define SPDIFRX_IFCR_OVRCF BIT(3)
+#define SPDIFRX_IFCR_SBDCF BIT(4)
+#define SPDIFRX_IFCR_SYNCDCF BIT(5)
+
+#define SPDIFRX_XIFCR_MASK GENMASK(5, 2)
+
+/* Bit definition for SPDIFRX_DR register (DRFMT = 0b00) */
+#define SPDIFRX_DR0_DR_SHIFT 0
+#define SPDIFRX_DR0_DR_MASK GENMASK(23, SPDIFRX_DR0_DR_SHIFT)
+#define SPDIFRX_DR0_DRSET(x) ((x) << SPDIFRX_DR0_DR_SHIFT)
+
+#define SPDIFRX_DR0_PE BIT(24)
+
+#define SPDIFRX_DR0_V BIT(25)
+#define SPDIFRX_DR0_U BIT(26)
+#define SPDIFRX_DR0_C BIT(27)
+
+#define SPDIFRX_DR0_PT_SHIFT 28
+#define SPDIFRX_DR0_PT_MASK GENMASK(29, SPDIFRX_DR0_PT_SHIFT)
+#define SPDIFRX_DR0_PTSET(x) ((x) << SPDIFRX_DR0_PT_SHIFT)
+
+/* Bit definition for SPDIFRX_DR register (DRFMT = 0b01) */
+#define SPDIFRX_DR1_PE BIT(0)
+#define SPDIFRX_DR1_V BIT(1)
+#define SPDIFRX_DR1_U BIT(2)
+#define SPDIFRX_DR1_C BIT(3)
+
+#define SPDIFRX_DR1_PT_SHIFT 4
+#define SPDIFRX_DR1_PT_MASK GENMASK(5, SPDIFRX_DR1_PT_SHIFT)
+#define SPDIFRX_DR1_PTSET(x) ((x) << SPDIFRX_DR1_PT_SHIFT)
+
+#define SPDIFRX_DR1_DR_SHIFT 8
+#define SPDIFRX_DR1_DR_MASK GENMASK(31, SPDIFRX_DR1_DR_SHIFT)
+#define SPDIFRX_DR1_DRSET(x) ((x) << SPDIFRX_DR1_DR_SHIFT)
+
+/* Bit definition for SPDIFRX_DR register (DRFMT = 0b10) */
+#define SPDIFRX_DR1_DRNL1_SHIFT 0
+#define SPDIFRX_DR1_DRNL1_MASK GENMASK(15, SPDIFRX_DR1_DRNL1_SHIFT)
+#define SPDIFRX_DR1_DRNL1SET(x) ((x) << SPDIFRX_DR1_DRNL1_SHIFT)
+
+#define SPDIFRX_DR1_DRNL2_SHIFT 16
+#define SPDIFRX_DR1_DRNL2_MASK GENMASK(31, SPDIFRX_DR1_DRNL2_SHIFT)
+#define SPDIFRX_DR1_DRNL2SET(x) ((x) << SPDIFRX_DR1_DRNL2_SHIFT)
+
+/* Bit definition for SPDIFRX_CSR register */
+#define SPDIFRX_CSR_USR_SHIFT 0
+#define SPDIFRX_CSR_USR_MASK GENMASK(15, SPDIFRX_CSR_USR_SHIFT)
+#define SPDIFRX_CSR_USRGET(x) (((x) & SPDIFRX_CSR_USR_MASK)\
+ >> SPDIFRX_CSR_USR_SHIFT)
+
+#define SPDIFRX_CSR_CS_SHIFT 16
+#define SPDIFRX_CSR_CS_MASK GENMASK(23, SPDIFRX_CSR_CS_SHIFT)
+#define SPDIFRX_CSR_CSGET(x) (((x) & SPDIFRX_CSR_CS_MASK)\
+ >> SPDIFRX_CSR_CS_SHIFT)
+
+#define SPDIFRX_CSR_SOB BIT(24)
+
+/* Bit definition for SPDIFRX_DIR register */
+#define SPDIFRX_DIR_THI_SHIFT 0
+#define SPDIFRX_DIR_THI_MASK GENMASK(12, SPDIFRX_DIR_THI_SHIFT)
+#define SPDIFRX_DIR_THI_SET(x) ((x) << SPDIFRX_DIR_THI_SHIFT)
+
+#define SPDIFRX_DIR_TLO_SHIFT 16
+#define SPDIFRX_DIR_TLO_MASK GENMASK(28, SPDIFRX_DIR_TLO_SHIFT)
+#define SPDIFRX_DIR_TLO_SET(x) ((x) << SPDIFRX_DIR_TLO_SHIFT)
+
+#define SPDIFRX_SPDIFEN_DISABLE 0x0
+#define SPDIFRX_SPDIFEN_SYNC 0x1
+#define SPDIFRX_SPDIFEN_ENABLE 0x3
+
+/* Bit definition for SPDIFRX_VERR register */
+#define SPDIFRX_VERR_MIN_MASK GENMASK(3, 0)
+#define SPDIFRX_VERR_MAJ_MASK GENMASK(7, 4)
+
+/* Bit definition for SPDIFRX_IDR register */
+#define SPDIFRX_IDR_ID_MASK GENMASK(31, 0)
+
+/* Bit definition for SPDIFRX_SIDR register */
+#define SPDIFRX_SIDR_SID_MASK GENMASK(31, 0)
+
+#define SPDIFRX_IPIDR_NUMBER 0x00130041
+
+#define SPDIFRX_IN1 0x1
+#define SPDIFRX_IN2 0x2
+#define SPDIFRX_IN3 0x3
+#define SPDIFRX_IN4 0x4
+#define SPDIFRX_IN5 0x5
+#define SPDIFRX_IN6 0x6
+#define SPDIFRX_IN7 0x7
+#define SPDIFRX_IN8 0x8
+
+#define SPDIFRX_NBTR_NONE 0x0
+#define SPDIFRX_NBTR_3 0x1
+#define SPDIFRX_NBTR_15 0x2
+#define SPDIFRX_NBTR_63 0x3
+
+#define SPDIFRX_DRFMT_RIGHT 0x0
+#define SPDIFRX_DRFMT_LEFT 0x1
+#define SPDIFRX_DRFMT_PACKED 0x2
+
+/* 192 CS bits in S/PDIF frame. i.e 24 CS bytes */
+#define SPDIFRX_CS_BYTES_NB 24
+#define SPDIFRX_UB_BYTES_NB 48
+
+/*
+ * CSR register is retrieved as a 32 bits word
+ * It contains 1 channel status byte and 2 user data bytes
+ * 2 S/PDIF frames are acquired to get all CS/UB bits
+ */
+#define SPDIFRX_CSR_BUF_LENGTH (SPDIFRX_CS_BYTES_NB * 4 * 2)
+
+/**
+ * struct stm32_spdifrx_data - private data of SPDIFRX
+ * @pdev: device data pointer
+ * @base: mmio register base virtual address
+ * @regmap: SPDIFRX register map pointer
+ * @regmap_conf: SPDIFRX register map configuration pointer
+ * @cs_completion: channel status retrieving completion
+ * @kclk: kernel clock feeding the SPDIFRX clock generator
+ * @dma_params: dma configuration data for rx channel
+ * @substream: PCM substream data pointer
+ * @dmab: dma buffer info pointer
+ * @ctrl_chan: dma channel for S/PDIF control bits
+ * @desc:dma async transaction descriptor
+ * @slave_config: dma slave channel runtime config pointer
+ * @phys_addr: SPDIFRX registers physical base address
+ * @lock: synchronization enabling lock
+ * @irq_lock: prevent race condition with IRQ on stream state
+ * @cs: channel status buffer
+ * @ub: user data buffer
+ * @irq: SPDIFRX interrupt line
+ * @refcount: keep count of opened DMA channels
+ */
+struct stm32_spdifrx_data {
+ struct platform_device *pdev;
+ void __iomem *base;
+ struct regmap *regmap;
+ const struct regmap_config *regmap_conf;
+ struct completion cs_completion;
+ struct clk *kclk;
+ struct snd_dmaengine_dai_dma_data dma_params;
+ struct snd_pcm_substream *substream;
+ struct snd_dma_buffer *dmab;
+ struct dma_chan *ctrl_chan;
+ struct dma_async_tx_descriptor *desc;
+ struct dma_slave_config slave_config;
+ dma_addr_t phys_addr;
+ spinlock_t lock; /* Sync enabling lock */
+ spinlock_t irq_lock; /* Prevent race condition on stream state */
+ unsigned char cs[SPDIFRX_CS_BYTES_NB];
+ unsigned char ub[SPDIFRX_UB_BYTES_NB];
+ int irq;
+ int refcount;
+};
+
+static void stm32_spdifrx_dma_complete(void *data)
+{
+ struct stm32_spdifrx_data *spdifrx = (struct stm32_spdifrx_data *)data;
+ struct platform_device *pdev = spdifrx->pdev;
+ u32 *p_start = (u32 *)spdifrx->dmab->area;
+ u32 *p_end = p_start + (2 * SPDIFRX_CS_BYTES_NB) - 1;
+ u32 *ptr = p_start;
+ u16 *ub_ptr = (short *)spdifrx->ub;
+ int i = 0;
+
+ regmap_update_bits(spdifrx->regmap, STM32_SPDIFRX_CR,
+ SPDIFRX_CR_CBDMAEN,
+ (unsigned int)~SPDIFRX_CR_CBDMAEN);
+
+ if (!spdifrx->dmab->area)
+ return;
+
+ while (ptr <= p_end) {
+ if (*ptr & SPDIFRX_CSR_SOB)
+ break;
+ ptr++;
+ }
+
+ if (ptr > p_end) {
+ dev_err(&pdev->dev, "Start of S/PDIF block not found\n");
+ return;
+ }
+
+ while (i < SPDIFRX_CS_BYTES_NB) {
+ spdifrx->cs[i] = (unsigned char)SPDIFRX_CSR_CSGET(*ptr);
+ *ub_ptr++ = SPDIFRX_CSR_USRGET(*ptr++);
+ if (ptr > p_end) {
+ dev_err(&pdev->dev, "Failed to get channel status\n");
+ return;
+ }
+ i++;
+ }
+
+ complete(&spdifrx->cs_completion);
+}
+
+static int stm32_spdifrx_dma_ctrl_start(struct stm32_spdifrx_data *spdifrx)
+{
+ dma_cookie_t cookie;
+ int err;
+
+ spdifrx->desc = dmaengine_prep_slave_single(spdifrx->ctrl_chan,
+ spdifrx->dmab->addr,
+ SPDIFRX_CSR_BUF_LENGTH,
+ DMA_DEV_TO_MEM,
+ DMA_CTRL_ACK);
+ if (!spdifrx->desc)
+ return -EINVAL;
+
+ spdifrx->desc->callback = stm32_spdifrx_dma_complete;
+ spdifrx->desc->callback_param = spdifrx;
+ cookie = dmaengine_submit(spdifrx->desc);
+ err = dma_submit_error(cookie);
+ if (err)
+ return -EINVAL;
+
+ dma_async_issue_pending(spdifrx->ctrl_chan);
+
+ return 0;
+}
+
+static void stm32_spdifrx_dma_ctrl_stop(struct stm32_spdifrx_data *spdifrx)
+{
+ dmaengine_terminate_async(spdifrx->ctrl_chan);
+}
+
+static int stm32_spdifrx_start_sync(struct stm32_spdifrx_data *spdifrx)
+{
+ int cr, cr_mask, imr, ret;
+ unsigned long flags;
+
+ /* Enable IRQs */
+ imr = SPDIFRX_IMR_IFEIE | SPDIFRX_IMR_SYNCDIE | SPDIFRX_IMR_PERRIE;
+ ret = regmap_update_bits(spdifrx->regmap, STM32_SPDIFRX_IMR, imr, imr);
+ if (ret)
+ return ret;
+
+ spin_lock_irqsave(&spdifrx->lock, flags);
+
+ spdifrx->refcount++;
+
+ regmap_read(spdifrx->regmap, STM32_SPDIFRX_CR, &cr);
+
+ if (!(cr & SPDIFRX_CR_SPDIFEN_MASK)) {
+ /*
+ * Start sync if SPDIFRX is still in idle state.
+ * SPDIFRX reception enabled when sync done
+ */
+ dev_dbg(&spdifrx->pdev->dev, "start synchronization\n");
+
+ /*
+ * SPDIFRX configuration:
+ * Wait for activity before starting sync process. This avoid
+ * to issue sync errors when spdif signal is missing on input.
+ * Preamble, CS, user, validity and parity error bits not copied
+ * to DR register.
+ */
+ cr = SPDIFRX_CR_WFA | SPDIFRX_CR_PMSK | SPDIFRX_CR_VMSK |
+ SPDIFRX_CR_CUMSK | SPDIFRX_CR_PTMSK | SPDIFRX_CR_RXSTEO;
+ cr_mask = cr;
+
+ cr |= SPDIFRX_CR_NBTRSET(SPDIFRX_NBTR_63);
+ cr_mask |= SPDIFRX_CR_NBTR_MASK;
+ cr |= SPDIFRX_CR_SPDIFENSET(SPDIFRX_SPDIFEN_SYNC);
+ cr_mask |= SPDIFRX_CR_SPDIFEN_MASK;
+ ret = regmap_update_bits(spdifrx->regmap, STM32_SPDIFRX_CR,
+ cr_mask, cr);
+ if (ret < 0)
+ dev_err(&spdifrx->pdev->dev,
+ "Failed to start synchronization\n");
+ }
+
+ spin_unlock_irqrestore(&spdifrx->lock, flags);
+
+ return ret;
+}
+
+static void stm32_spdifrx_stop(struct stm32_spdifrx_data *spdifrx)
+{
+ int cr, cr_mask, reg;
+ unsigned long flags;
+
+ spin_lock_irqsave(&spdifrx->lock, flags);
+
+ if (--spdifrx->refcount) {
+ spin_unlock_irqrestore(&spdifrx->lock, flags);
+ return;
+ }
+
+ cr = SPDIFRX_CR_SPDIFENSET(SPDIFRX_SPDIFEN_DISABLE);
+ cr_mask = SPDIFRX_CR_SPDIFEN_MASK | SPDIFRX_CR_RXDMAEN;
+
+ regmap_update_bits(spdifrx->regmap, STM32_SPDIFRX_CR, cr_mask, cr);
+
+ regmap_update_bits(spdifrx->regmap, STM32_SPDIFRX_IMR,
+ SPDIFRX_XIMR_MASK, 0);
+
+ regmap_update_bits(spdifrx->regmap, STM32_SPDIFRX_IFCR,
+ SPDIFRX_XIFCR_MASK, SPDIFRX_XIFCR_MASK);
+
+ /* dummy read to clear CSRNE and RXNE in status register */
+ regmap_read(spdifrx->regmap, STM32_SPDIFRX_DR, &reg);
+ regmap_read(spdifrx->regmap, STM32_SPDIFRX_CSR, &reg);
+
+ spin_unlock_irqrestore(&spdifrx->lock, flags);
+}
+
+static int stm32_spdifrx_dma_ctrl_register(struct device *dev,
+ struct stm32_spdifrx_data *spdifrx)
+{
+ int ret;
+
+ spdifrx->ctrl_chan = dma_request_chan(dev, "rx-ctrl");
+ if (IS_ERR(spdifrx->ctrl_chan))
+ return dev_err_probe(dev, PTR_ERR(spdifrx->ctrl_chan),
+ "dma_request_slave_channel error\n");
+
+ spdifrx->dmab = devm_kzalloc(dev, sizeof(struct snd_dma_buffer),
+ GFP_KERNEL);
+ if (!spdifrx->dmab)
+ return -ENOMEM;
+
+ spdifrx->dmab->dev.type = SNDRV_DMA_TYPE_DEV_IRAM;
+ spdifrx->dmab->dev.dev = dev;
+ ret = snd_dma_alloc_pages(spdifrx->dmab->dev.type, dev,
+ SPDIFRX_CSR_BUF_LENGTH, spdifrx->dmab);
+ if (ret < 0) {
+ dev_err(dev, "snd_dma_alloc_pages returned error %d\n", ret);
+ return ret;
+ }
+
+ spdifrx->slave_config.direction = DMA_DEV_TO_MEM;
+ spdifrx->slave_config.src_addr = (dma_addr_t)(spdifrx->phys_addr +
+ STM32_SPDIFRX_CSR);
+ spdifrx->slave_config.dst_addr = spdifrx->dmab->addr;
+ spdifrx->slave_config.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
+ spdifrx->slave_config.src_maxburst = 1;
+
+ ret = dmaengine_slave_config(spdifrx->ctrl_chan,
+ &spdifrx->slave_config);
+ if (ret < 0) {
+ dev_err(dev, "dmaengine_slave_config returned error %d\n", ret);
+ spdifrx->ctrl_chan = NULL;
+ }
+
+ return ret;
+};
+
+static const char * const spdifrx_enum_input[] = {
+ "in0", "in1", "in2", "in3"
+};
+
+/* By default CS bits are retrieved from channel A */
+static const char * const spdifrx_enum_cs_channel[] = {
+ "A", "B"
+};
+
+static SOC_ENUM_SINGLE_DECL(ctrl_enum_input,
+ STM32_SPDIFRX_CR, SPDIFRX_CR_INSEL_SHIFT,
+ spdifrx_enum_input);
+
+static SOC_ENUM_SINGLE_DECL(ctrl_enum_cs_channel,
+ STM32_SPDIFRX_CR, SPDIFRX_CR_CHSEL_SHIFT,
+ spdifrx_enum_cs_channel);
+
+static int stm32_spdifrx_info(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_info *uinfo)
+{
+ uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
+ uinfo->count = 1;
+
+ return 0;
+}
+
+static int stm32_spdifrx_ub_info(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_info *uinfo)
+{
+ uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
+ uinfo->count = 1;
+
+ return 0;
+}
+
+static int stm32_spdifrx_get_ctrl_data(struct stm32_spdifrx_data *spdifrx)
+{
+ int ret = 0;
+
+ memset(spdifrx->cs, 0, SPDIFRX_CS_BYTES_NB);
+ memset(spdifrx->ub, 0, SPDIFRX_UB_BYTES_NB);
+
+ ret = stm32_spdifrx_dma_ctrl_start(spdifrx);
+ if (ret < 0)
+ return ret;
+
+ ret = clk_prepare_enable(spdifrx->kclk);
+ if (ret) {
+ dev_err(&spdifrx->pdev->dev, "Enable kclk failed: %d\n", ret);
+ return ret;
+ }
+
+ ret = regmap_update_bits(spdifrx->regmap, STM32_SPDIFRX_CR,
+ SPDIFRX_CR_CBDMAEN, SPDIFRX_CR_CBDMAEN);
+ if (ret < 0)
+ goto end;
+
+ ret = stm32_spdifrx_start_sync(spdifrx);
+ if (ret < 0)
+ goto end;
+
+ if (wait_for_completion_interruptible_timeout(&spdifrx->cs_completion,
+ msecs_to_jiffies(100))
+ <= 0) {
+ dev_dbg(&spdifrx->pdev->dev, "Failed to get control data\n");
+ ret = -EAGAIN;
+ }
+
+ stm32_spdifrx_stop(spdifrx);
+ stm32_spdifrx_dma_ctrl_stop(spdifrx);
+
+end:
+ clk_disable_unprepare(spdifrx->kclk);
+
+ return ret;
+}
+
+static int stm32_spdifrx_capture_get(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+{
+ struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);
+ struct stm32_spdifrx_data *spdifrx = snd_soc_dai_get_drvdata(cpu_dai);
+
+ stm32_spdifrx_get_ctrl_data(spdifrx);
+
+ ucontrol->value.iec958.status[0] = spdifrx->cs[0];
+ ucontrol->value.iec958.status[1] = spdifrx->cs[1];
+ ucontrol->value.iec958.status[2] = spdifrx->cs[2];
+ ucontrol->value.iec958.status[3] = spdifrx->cs[3];
+ ucontrol->value.iec958.status[4] = spdifrx->cs[4];
+
+ return 0;
+}
+
+static int stm32_spdif_user_bits_get(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+{
+ struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);
+ struct stm32_spdifrx_data *spdifrx = snd_soc_dai_get_drvdata(cpu_dai);
+
+ stm32_spdifrx_get_ctrl_data(spdifrx);
+
+ ucontrol->value.iec958.status[0] = spdifrx->ub[0];
+ ucontrol->value.iec958.status[1] = spdifrx->ub[1];
+ ucontrol->value.iec958.status[2] = spdifrx->ub[2];
+ ucontrol->value.iec958.status[3] = spdifrx->ub[3];
+ ucontrol->value.iec958.status[4] = spdifrx->ub[4];
+
+ return 0;
+}
+
+static struct snd_kcontrol_new stm32_spdifrx_iec_ctrls[] = {
+ /* Channel status control */
+ {
+ .iface = SNDRV_CTL_ELEM_IFACE_PCM,
+ .name = SNDRV_CTL_NAME_IEC958("", CAPTURE, DEFAULT),
+ .access = SNDRV_CTL_ELEM_ACCESS_READ |
+ SNDRV_CTL_ELEM_ACCESS_VOLATILE,
+ .info = stm32_spdifrx_info,
+ .get = stm32_spdifrx_capture_get,
+ },
+ /* User bits control */
+ {
+ .iface = SNDRV_CTL_ELEM_IFACE_PCM,
+ .name = "IEC958 User Bit Capture Default",
+ .access = SNDRV_CTL_ELEM_ACCESS_READ |
+ SNDRV_CTL_ELEM_ACCESS_VOLATILE,
+ .info = stm32_spdifrx_ub_info,
+ .get = stm32_spdif_user_bits_get,
+ },
+};
+
+static struct snd_kcontrol_new stm32_spdifrx_ctrls[] = {
+ SOC_ENUM("SPDIFRX input", ctrl_enum_input),
+ SOC_ENUM("SPDIFRX CS channel", ctrl_enum_cs_channel),
+};
+
+static int stm32_spdifrx_dai_register_ctrls(struct snd_soc_dai *cpu_dai)
+{
+ int ret;
+
+ ret = snd_soc_add_dai_controls(cpu_dai, stm32_spdifrx_iec_ctrls,
+ ARRAY_SIZE(stm32_spdifrx_iec_ctrls));
+ if (ret < 0)
+ return ret;
+
+ return snd_soc_add_component_controls(cpu_dai->component,
+ stm32_spdifrx_ctrls,
+ ARRAY_SIZE(stm32_spdifrx_ctrls));
+}
+
+static int stm32_spdifrx_dai_probe(struct snd_soc_dai *cpu_dai)
+{
+ struct stm32_spdifrx_data *spdifrx = dev_get_drvdata(cpu_dai->dev);
+
+ spdifrx->dma_params.addr = (dma_addr_t)(spdifrx->phys_addr +
+ STM32_SPDIFRX_DR);
+ spdifrx->dma_params.maxburst = 1;
+
+ snd_soc_dai_init_dma_data(cpu_dai, NULL, &spdifrx->dma_params);
+
+ return stm32_spdifrx_dai_register_ctrls(cpu_dai);
+}
+
+static bool stm32_spdifrx_readable_reg(struct device *dev, unsigned int reg)
+{
+ switch (reg) {
+ case STM32_SPDIFRX_CR:
+ case STM32_SPDIFRX_IMR:
+ case STM32_SPDIFRX_SR:
+ case STM32_SPDIFRX_IFCR:
+ case STM32_SPDIFRX_DR:
+ case STM32_SPDIFRX_CSR:
+ case STM32_SPDIFRX_DIR:
+ case STM32_SPDIFRX_VERR:
+ case STM32_SPDIFRX_IDR:
+ case STM32_SPDIFRX_SIDR:
+ return true;
+ default:
+ return false;
+ }
+}
+
+static bool stm32_spdifrx_volatile_reg(struct device *dev, unsigned int reg)
+{
+ switch (reg) {
+ case STM32_SPDIFRX_DR:
+ case STM32_SPDIFRX_CSR:
+ case STM32_SPDIFRX_SR:
+ case STM32_SPDIFRX_DIR:
+ return true;
+ default:
+ return false;
+ }
+}
+
+static bool stm32_spdifrx_writeable_reg(struct device *dev, unsigned int reg)
+{
+ switch (reg) {
+ case STM32_SPDIFRX_CR:
+ case STM32_SPDIFRX_IMR:
+ case STM32_SPDIFRX_IFCR:
+ return true;
+ default:
+ return false;
+ }
+}
+
+static const struct regmap_config stm32_h7_spdifrx_regmap_conf = {
+ .reg_bits = 32,
+ .reg_stride = 4,
+ .val_bits = 32,
+ .max_register = STM32_SPDIFRX_SIDR,
+ .readable_reg = stm32_spdifrx_readable_reg,
+ .volatile_reg = stm32_spdifrx_volatile_reg,
+ .writeable_reg = stm32_spdifrx_writeable_reg,
+ .num_reg_defaults_raw = STM32_SPDIFRX_SIDR / sizeof(u32) + 1,
+ .fast_io = true,
+ .cache_type = REGCACHE_FLAT,
+};
+
+static irqreturn_t stm32_spdifrx_isr(int irq, void *devid)
+{
+ struct stm32_spdifrx_data *spdifrx = (struct stm32_spdifrx_data *)devid;
+ struct platform_device *pdev = spdifrx->pdev;
+ unsigned int cr, mask, sr, imr;
+ unsigned int flags, sync_state;
+ int err = 0, err_xrun = 0;
+
+ regmap_read(spdifrx->regmap, STM32_SPDIFRX_SR, &sr);
+ regmap_read(spdifrx->regmap, STM32_SPDIFRX_IMR, &imr);
+
+ mask = imr & SPDIFRX_XIMR_MASK;
+ /* SERR, TERR, FERR IRQs are generated if IFEIE is set */
+ if (mask & SPDIFRX_IMR_IFEIE)
+ mask |= (SPDIFRX_IMR_IFEIE << 1) | (SPDIFRX_IMR_IFEIE << 2);
+
+ flags = sr & mask;
+ if (!flags) {
+ dev_err(&pdev->dev, "Unexpected IRQ. rflags=%#x, imr=%#x\n",
+ sr, imr);
+ return IRQ_NONE;
+ }
+
+ /* Clear IRQs */
+ regmap_update_bits(spdifrx->regmap, STM32_SPDIFRX_IFCR,
+ SPDIFRX_XIFCR_MASK, flags);
+
+ if (flags & SPDIFRX_SR_PERR) {
+ dev_dbg(&pdev->dev, "Parity error\n");
+ err_xrun = 1;
+ }
+
+ if (flags & SPDIFRX_SR_OVR) {
+ dev_dbg(&pdev->dev, "Overrun error\n");
+ err_xrun = 1;
+ }
+
+ if (flags & SPDIFRX_SR_SBD)
+ dev_dbg(&pdev->dev, "Synchronization block detected\n");
+
+ if (flags & SPDIFRX_SR_SYNCD) {
+ dev_dbg(&pdev->dev, "Synchronization done\n");
+
+ /* Enable spdifrx */
+ cr = SPDIFRX_CR_SPDIFENSET(SPDIFRX_SPDIFEN_ENABLE);
+ regmap_update_bits(spdifrx->regmap, STM32_SPDIFRX_CR,
+ SPDIFRX_CR_SPDIFEN_MASK, cr);
+ }
+
+ if (flags & SPDIFRX_SR_FERR) {
+ dev_dbg(&pdev->dev, "Frame error\n");
+ err = 1;
+ }
+
+ if (flags & SPDIFRX_SR_SERR) {
+ dev_dbg(&pdev->dev, "Synchronization error\n");
+ err = 1;
+ }
+
+ if (flags & SPDIFRX_SR_TERR) {
+ dev_dbg(&pdev->dev, "Timeout error\n");
+ err = 1;
+ }
+
+ if (err) {
+ regmap_read(spdifrx->regmap, STM32_SPDIFRX_CR, &cr);
+ sync_state = FIELD_GET(SPDIFRX_CR_SPDIFEN_MASK, cr) &&
+ SPDIFRX_SPDIFEN_SYNC;
+
+ /* SPDIFRX is in STATE_STOP. Disable SPDIFRX to clear errors */
+ cr = SPDIFRX_CR_SPDIFENSET(SPDIFRX_SPDIFEN_DISABLE);
+ regmap_update_bits(spdifrx->regmap, STM32_SPDIFRX_CR,
+ SPDIFRX_CR_SPDIFEN_MASK, cr);
+
+ /* If SPDIFRX was in STATE_SYNC, retry synchro */
+ if (sync_state) {
+ cr = SPDIFRX_CR_SPDIFENSET(SPDIFRX_SPDIFEN_SYNC);
+ regmap_update_bits(spdifrx->regmap, STM32_SPDIFRX_CR,
+ SPDIFRX_CR_SPDIFEN_MASK, cr);
+ return IRQ_HANDLED;
+ }
+
+ spin_lock(&spdifrx->irq_lock);
+ if (spdifrx->substream)
+ snd_pcm_stop(spdifrx->substream,
+ SNDRV_PCM_STATE_DISCONNECTED);
+ spin_unlock(&spdifrx->irq_lock);
+
+ return IRQ_HANDLED;
+ }
+
+ spin_lock(&spdifrx->irq_lock);
+ if (err_xrun && spdifrx->substream)
+ snd_pcm_stop_xrun(spdifrx->substream);
+ spin_unlock(&spdifrx->irq_lock);
+
+ return IRQ_HANDLED;
+}
+
+static int stm32_spdifrx_startup(struct snd_pcm_substream *substream,
+ struct snd_soc_dai *cpu_dai)
+{
+ struct stm32_spdifrx_data *spdifrx = snd_soc_dai_get_drvdata(cpu_dai);
+ unsigned long flags;
+ int ret;
+
+ spin_lock_irqsave(&spdifrx->irq_lock, flags);
+ spdifrx->substream = substream;
+ spin_unlock_irqrestore(&spdifrx->irq_lock, flags);
+
+ ret = clk_prepare_enable(spdifrx->kclk);
+ if (ret)
+ dev_err(&spdifrx->pdev->dev, "Enable kclk failed: %d\n", ret);
+
+ return ret;
+}
+
+static int stm32_spdifrx_hw_params(struct snd_pcm_substream *substream,
+ struct snd_pcm_hw_params *params,
+ struct snd_soc_dai *cpu_dai)
+{
+ struct stm32_spdifrx_data *spdifrx = snd_soc_dai_get_drvdata(cpu_dai);
+ int data_size = params_width(params);
+ int fmt;
+
+ switch (data_size) {
+ case 16:
+ fmt = SPDIFRX_DRFMT_PACKED;
+ break;
+ case 32:
+ fmt = SPDIFRX_DRFMT_LEFT;
+ break;
+ default:
+ dev_err(&spdifrx->pdev->dev, "Unexpected data format\n");
+ return -EINVAL;
+ }
+
+ /*
+ * Set buswidth to 4 bytes for all data formats.
+ * Packed format: transfer 2 x 2 bytes samples
+ * Left format: transfer 1 x 3 bytes samples + 1 dummy byte
+ */
+ spdifrx->dma_params.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
+ snd_soc_dai_init_dma_data(cpu_dai, NULL, &spdifrx->dma_params);
+
+ return regmap_update_bits(spdifrx->regmap, STM32_SPDIFRX_CR,
+ SPDIFRX_CR_DRFMT_MASK,
+ SPDIFRX_CR_DRFMTSET(fmt));
+}
+
+static int stm32_spdifrx_trigger(struct snd_pcm_substream *substream, int cmd,
+ struct snd_soc_dai *cpu_dai)
+{
+ struct stm32_spdifrx_data *spdifrx = snd_soc_dai_get_drvdata(cpu_dai);
+ int ret = 0;
+
+ switch (cmd) {
+ case SNDRV_PCM_TRIGGER_START:
+ case SNDRV_PCM_TRIGGER_RESUME:
+ case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
+ regmap_update_bits(spdifrx->regmap, STM32_SPDIFRX_IMR,
+ SPDIFRX_IMR_OVRIE, SPDIFRX_IMR_OVRIE);
+
+ regmap_update_bits(spdifrx->regmap, STM32_SPDIFRX_CR,
+ SPDIFRX_CR_RXDMAEN, SPDIFRX_CR_RXDMAEN);
+
+ ret = stm32_spdifrx_start_sync(spdifrx);
+ break;
+ case SNDRV_PCM_TRIGGER_SUSPEND:
+ case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
+ case SNDRV_PCM_TRIGGER_STOP:
+ stm32_spdifrx_stop(spdifrx);
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ return ret;
+}
+
+static void stm32_spdifrx_shutdown(struct snd_pcm_substream *substream,
+ struct snd_soc_dai *cpu_dai)
+{
+ struct stm32_spdifrx_data *spdifrx = snd_soc_dai_get_drvdata(cpu_dai);
+ unsigned long flags;
+
+ spin_lock_irqsave(&spdifrx->irq_lock, flags);
+ spdifrx->substream = NULL;
+ spin_unlock_irqrestore(&spdifrx->irq_lock, flags);
+
+ clk_disable_unprepare(spdifrx->kclk);
+}
+
+static const struct snd_soc_dai_ops stm32_spdifrx_pcm_dai_ops = {
+ .probe = stm32_spdifrx_dai_probe,
+ .startup = stm32_spdifrx_startup,
+ .hw_params = stm32_spdifrx_hw_params,
+ .trigger = stm32_spdifrx_trigger,
+ .shutdown = stm32_spdifrx_shutdown,
+};
+
+static struct snd_soc_dai_driver stm32_spdifrx_dai[] = {
+ {
+ .capture = {
+ .stream_name = "CPU-Capture",
+ .channels_min = 1,
+ .channels_max = 2,
+ .rates = SNDRV_PCM_RATE_8000_192000,
+ .formats = SNDRV_PCM_FMTBIT_S32_LE |
+ SNDRV_PCM_FMTBIT_S16_LE,
+ },
+ .ops = &stm32_spdifrx_pcm_dai_ops,
+ }
+};
+
+static const struct snd_pcm_hardware stm32_spdifrx_pcm_hw = {
+ .info = SNDRV_PCM_INFO_INTERLEAVED | SNDRV_PCM_INFO_MMAP,
+ .buffer_bytes_max = 8 * PAGE_SIZE,
+ .period_bytes_min = 1024,
+ .period_bytes_max = 4 * PAGE_SIZE,
+ .periods_min = 2,
+ .periods_max = 8,
+};
+
+static const struct snd_soc_component_driver stm32_spdifrx_component = {
+ .name = "stm32-spdifrx",
+ .legacy_dai_naming = 1,
+};
+
+static const struct snd_dmaengine_pcm_config stm32_spdifrx_pcm_config = {
+ .pcm_hardware = &stm32_spdifrx_pcm_hw,
+ .prepare_slave_config = snd_dmaengine_pcm_prepare_slave_config,
+};
+
+static const struct of_device_id stm32_spdifrx_ids[] = {
+ {
+ .compatible = "st,stm32h7-spdifrx",
+ .data = &stm32_h7_spdifrx_regmap_conf
+ },
+ {}
+};
+
+static int stm32_spdifrx_parse_of(struct platform_device *pdev,
+ struct stm32_spdifrx_data *spdifrx)
+{
+ struct device_node *np = pdev->dev.of_node;
+ const struct of_device_id *of_id;
+ struct resource *res;
+
+ if (!np)
+ return -ENODEV;
+
+ of_id = of_match_device(stm32_spdifrx_ids, &pdev->dev);
+ if (of_id)
+ spdifrx->regmap_conf =
+ (const struct regmap_config *)of_id->data;
+ else
+ return -EINVAL;
+
+ spdifrx->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
+ if (IS_ERR(spdifrx->base))
+ return PTR_ERR(spdifrx->base);
+
+ spdifrx->phys_addr = res->start;
+
+ spdifrx->kclk = devm_clk_get(&pdev->dev, "kclk");
+ if (IS_ERR(spdifrx->kclk))
+ return dev_err_probe(&pdev->dev, PTR_ERR(spdifrx->kclk),
+ "Could not get kclk\n");
+
+ spdifrx->irq = platform_get_irq(pdev, 0);
+ if (spdifrx->irq < 0)
+ return spdifrx->irq;
+
+ return 0;
+}
+
+static void stm32_spdifrx_remove(struct platform_device *pdev)
+{
+ struct stm32_spdifrx_data *spdifrx = platform_get_drvdata(pdev);
+
+ if (spdifrx->ctrl_chan)
+ dma_release_channel(spdifrx->ctrl_chan);
+
+ if (spdifrx->dmab)
+ snd_dma_free_pages(spdifrx->dmab);
+
+ snd_dmaengine_pcm_unregister(&pdev->dev);
+ snd_soc_unregister_component(&pdev->dev);
+ pm_runtime_disable(&pdev->dev);
+}
+
+static int stm32_spdifrx_probe(struct platform_device *pdev)
+{
+ struct stm32_spdifrx_data *spdifrx;
+ struct reset_control *rst;
+ const struct snd_dmaengine_pcm_config *pcm_config = NULL;
+ u32 ver, idr;
+ int ret;
+
+ spdifrx = devm_kzalloc(&pdev->dev, sizeof(*spdifrx), GFP_KERNEL);
+ if (!spdifrx)
+ return -ENOMEM;
+
+ spdifrx->pdev = pdev;
+ init_completion(&spdifrx->cs_completion);
+ spin_lock_init(&spdifrx->lock);
+ spin_lock_init(&spdifrx->irq_lock);
+
+ platform_set_drvdata(pdev, spdifrx);
+
+ ret = stm32_spdifrx_parse_of(pdev, spdifrx);
+ if (ret)
+ return ret;
+
+ spdifrx->regmap = devm_regmap_init_mmio_clk(&pdev->dev, "kclk",
+ spdifrx->base,
+ spdifrx->regmap_conf);
+ if (IS_ERR(spdifrx->regmap))
+ return dev_err_probe(&pdev->dev, PTR_ERR(spdifrx->regmap),
+ "Regmap init error\n");
+
+ ret = devm_request_irq(&pdev->dev, spdifrx->irq, stm32_spdifrx_isr, 0,
+ dev_name(&pdev->dev), spdifrx);
+ if (ret) {
+ dev_err(&pdev->dev, "IRQ request returned %d\n", ret);
+ return ret;
+ }
+
+ rst = devm_reset_control_get_optional_exclusive(&pdev->dev, NULL);
+ if (IS_ERR(rst))
+ return dev_err_probe(&pdev->dev, PTR_ERR(rst),
+ "Reset controller error\n");
+
+ reset_control_assert(rst);
+ udelay(2);
+ reset_control_deassert(rst);
+
+ pcm_config = &stm32_spdifrx_pcm_config;
+ ret = snd_dmaengine_pcm_register(&pdev->dev, pcm_config, 0);
+ if (ret)
+ return dev_err_probe(&pdev->dev, ret, "PCM DMA register error\n");
+
+ ret = snd_soc_register_component(&pdev->dev,
+ &stm32_spdifrx_component,
+ stm32_spdifrx_dai,
+ ARRAY_SIZE(stm32_spdifrx_dai));
+ if (ret) {
+ snd_dmaengine_pcm_unregister(&pdev->dev);
+ return ret;
+ }
+
+ ret = stm32_spdifrx_dma_ctrl_register(&pdev->dev, spdifrx);
+ if (ret)
+ goto error;
+
+ ret = regmap_read(spdifrx->regmap, STM32_SPDIFRX_IDR, &idr);
+ if (ret)
+ goto error;
+
+ if (idr == SPDIFRX_IPIDR_NUMBER) {
+ ret = regmap_read(spdifrx->regmap, STM32_SPDIFRX_VERR, &ver);
+ if (ret)
+ goto error;
+
+ dev_dbg(&pdev->dev, "SPDIFRX version: %lu.%lu registered\n",
+ FIELD_GET(SPDIFRX_VERR_MAJ_MASK, ver),
+ FIELD_GET(SPDIFRX_VERR_MIN_MASK, ver));
+ }
+
+ pm_runtime_enable(&pdev->dev);
+
+ return ret;
+
+error:
+ stm32_spdifrx_remove(pdev);
+
+ return ret;
+}
+
+MODULE_DEVICE_TABLE(of, stm32_spdifrx_ids);
+
+#ifdef CONFIG_PM_SLEEP
+static int stm32_spdifrx_suspend(struct device *dev)
+{
+ struct stm32_spdifrx_data *spdifrx = dev_get_drvdata(dev);
+
+ regcache_cache_only(spdifrx->regmap, true);
+ regcache_mark_dirty(spdifrx->regmap);
+
+ return 0;
+}
+
+static int stm32_spdifrx_resume(struct device *dev)
+{
+ struct stm32_spdifrx_data *spdifrx = dev_get_drvdata(dev);
+
+ regcache_cache_only(spdifrx->regmap, false);
+
+ return regcache_sync(spdifrx->regmap);
+}
+#endif /* CONFIG_PM_SLEEP */
+
+static const struct dev_pm_ops stm32_spdifrx_pm_ops = {
+ SET_SYSTEM_SLEEP_PM_OPS(stm32_spdifrx_suspend, stm32_spdifrx_resume)
+};
+
+static struct platform_driver stm32_spdifrx_driver = {
+ .driver = {
+ .name = "st,stm32-spdifrx",
+ .of_match_table = stm32_spdifrx_ids,
+ .pm = &stm32_spdifrx_pm_ops,
+ },
+ .probe = stm32_spdifrx_probe,
+ .remove_new = stm32_spdifrx_remove,
+};
+
+module_platform_driver(stm32_spdifrx_driver);
+
+MODULE_DESCRIPTION("STM32 Soc spdifrx Interface");
+MODULE_AUTHOR("Olivier Moysan, <olivier.moysan@st.com>");
+MODULE_ALIAS("platform:stm32-spdifrx");
+MODULE_LICENSE("GPL v2");