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author | Daniel Baumann <daniel.baumann@progress-linux.org> | 2024-04-11 08:27:49 +0000 |
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committer | Daniel Baumann <daniel.baumann@progress-linux.org> | 2024-04-11 08:27:49 +0000 |
commit | ace9429bb58fd418f0c81d4c2835699bddf6bde6 (patch) | |
tree | b2d64bc10158fdd5497876388cd68142ca374ed3 /tools/perf/pmu-events/arch/x86/westmereep-dp/floating-point.json | |
parent | Initial commit. (diff) | |
download | linux-ace9429bb58fd418f0c81d4c2835699bddf6bde6.tar.xz linux-ace9429bb58fd418f0c81d4c2835699bddf6bde6.zip |
Adding upstream version 6.6.15.upstream/6.6.15
Signed-off-by: Daniel Baumann <daniel.baumann@progress-linux.org>
Diffstat (limited to 'tools/perf/pmu-events/arch/x86/westmereep-dp/floating-point.json')
-rw-r--r-- | tools/perf/pmu-events/arch/x86/westmereep-dp/floating-point.json | 201 |
1 files changed, 201 insertions, 0 deletions
diff --git a/tools/perf/pmu-events/arch/x86/westmereep-dp/floating-point.json b/tools/perf/pmu-events/arch/x86/westmereep-dp/floating-point.json new file mode 100644 index 0000000000..c03f8990fa --- /dev/null +++ b/tools/perf/pmu-events/arch/x86/westmereep-dp/floating-point.json @@ -0,0 +1,201 @@ +[ + { + "BriefDescription": "X87 Floating point assists (Precise Event)", + "EventCode": "0xF7", + "EventName": "FP_ASSIST.ALL", + "PEBS": "1", + "SampleAfterValue": "20000", + "UMask": "0x1" + }, + { + "BriefDescription": "X87 Floating poiint assists for invalid input value (Precise Event)", + "EventCode": "0xF7", + "EventName": "FP_ASSIST.INPUT", + "PEBS": "1", + "SampleAfterValue": "20000", + "UMask": "0x4" + }, + { + "BriefDescription": "X87 Floating point assists for invalid output value (Precise Event)", + "EventCode": "0xF7", + "EventName": "FP_ASSIST.OUTPUT", + "PEBS": "1", + "SampleAfterValue": "20000", + "UMask": "0x2" + }, + { + "BriefDescription": "MMX Uops", + "EventCode": "0x10", + "EventName": "FP_COMP_OPS_EXE.MMX", + "SampleAfterValue": "2000000", + "UMask": "0x2" + }, + { + "BriefDescription": "SSE2 integer Uops", + "EventCode": "0x10", + "EventName": "FP_COMP_OPS_EXE.SSE2_INTEGER", + "SampleAfterValue": "2000000", + "UMask": "0x8" + }, + { + "BriefDescription": "SSE* FP double precision Uops", + "EventCode": "0x10", + "EventName": "FP_COMP_OPS_EXE.SSE_DOUBLE_PRECISION", + "SampleAfterValue": "2000000", + "UMask": "0x80" + }, + { + "BriefDescription": "SSE and SSE2 FP Uops", + "EventCode": "0x10", + "EventName": "FP_COMP_OPS_EXE.SSE_FP", + "SampleAfterValue": "2000000", + "UMask": "0x4" + }, + { + "BriefDescription": "SSE FP packed Uops", + "EventCode": "0x10", + "EventName": "FP_COMP_OPS_EXE.SSE_FP_PACKED", + "SampleAfterValue": "2000000", + "UMask": "0x10" + }, + { + "BriefDescription": "SSE FP scalar Uops", + "EventCode": "0x10", + "EventName": "FP_COMP_OPS_EXE.SSE_FP_SCALAR", + "SampleAfterValue": "2000000", + "UMask": "0x20" + }, + { + "BriefDescription": "SSE* FP single precision Uops", + "EventCode": "0x10", + "EventName": "FP_COMP_OPS_EXE.SSE_SINGLE_PRECISION", + "SampleAfterValue": "2000000", + "UMask": "0x40" + }, + { + "BriefDescription": "Computational floating-point operations executed", + "EventCode": "0x10", + "EventName": "FP_COMP_OPS_EXE.X87", + "SampleAfterValue": "2000000", + "UMask": "0x1" + }, + { + "BriefDescription": "All Floating Point to and from MMX transitions", + "EventCode": "0xCC", + "EventName": "FP_MMX_TRANS.ANY", + "SampleAfterValue": "2000000", + "UMask": "0x3" + }, + { + "BriefDescription": "Transitions from MMX to Floating Point instructions", + "EventCode": "0xCC", + "EventName": "FP_MMX_TRANS.TO_FP", + "SampleAfterValue": "2000000", + "UMask": "0x1" + }, + { + "BriefDescription": "Transitions from Floating Point to MMX instructions", + "EventCode": "0xCC", + "EventName": "FP_MMX_TRANS.TO_MMX", + "SampleAfterValue": "2000000", + "UMask": "0x2" + }, + { + "BriefDescription": "128 bit SIMD integer pack operations", + "EventCode": "0x12", + "EventName": "SIMD_INT_128.PACK", + "SampleAfterValue": "200000", + "UMask": "0x4" + }, + { + "BriefDescription": "128 bit SIMD integer arithmetic operations", + "EventCode": "0x12", + "EventName": "SIMD_INT_128.PACKED_ARITH", + "SampleAfterValue": "200000", + "UMask": "0x20" + }, + { + "BriefDescription": "128 bit SIMD integer logical operations", + "EventCode": "0x12", + "EventName": "SIMD_INT_128.PACKED_LOGICAL", + "SampleAfterValue": "200000", + "UMask": "0x10" + }, + { + "BriefDescription": "128 bit SIMD integer multiply operations", + "EventCode": "0x12", + "EventName": "SIMD_INT_128.PACKED_MPY", + "SampleAfterValue": "200000", + "UMask": "0x1" + }, + { + "BriefDescription": "128 bit SIMD integer shift operations", + "EventCode": "0x12", + "EventName": "SIMD_INT_128.PACKED_SHIFT", + "SampleAfterValue": "200000", + "UMask": "0x2" + }, + { + "BriefDescription": "128 bit SIMD integer shuffle/move operations", + "EventCode": "0x12", + "EventName": "SIMD_INT_128.SHUFFLE_MOVE", + "SampleAfterValue": "200000", + "UMask": "0x40" + }, + { + "BriefDescription": "128 bit SIMD integer unpack operations", + "EventCode": "0x12", + "EventName": "SIMD_INT_128.UNPACK", + "SampleAfterValue": "200000", + "UMask": "0x8" + }, + { + "BriefDescription": "SIMD integer 64 bit pack operations", + "EventCode": "0xFD", + "EventName": "SIMD_INT_64.PACK", + "SampleAfterValue": "200000", + "UMask": "0x4" + }, + { + "BriefDescription": "SIMD integer 64 bit arithmetic operations", + "EventCode": "0xFD", + "EventName": "SIMD_INT_64.PACKED_ARITH", + "SampleAfterValue": "200000", + "UMask": "0x20" + }, + { + "BriefDescription": "SIMD integer 64 bit logical operations", + "EventCode": "0xFD", + "EventName": "SIMD_INT_64.PACKED_LOGICAL", + "SampleAfterValue": "200000", + "UMask": "0x10" + }, + { + "BriefDescription": "SIMD integer 64 bit packed multiply operations", + "EventCode": "0xFD", + "EventName": "SIMD_INT_64.PACKED_MPY", + "SampleAfterValue": "200000", + "UMask": "0x1" + }, + { + "BriefDescription": "SIMD integer 64 bit shift operations", + "EventCode": "0xFD", + "EventName": "SIMD_INT_64.PACKED_SHIFT", + "SampleAfterValue": "200000", + "UMask": "0x2" + }, + { + "BriefDescription": "SIMD integer 64 bit shuffle/move operations", + "EventCode": "0xFD", + "EventName": "SIMD_INT_64.SHUFFLE_MOVE", + "SampleAfterValue": "200000", + "UMask": "0x40" + }, + { + "BriefDescription": "SIMD integer 64 bit unpack operations", + "EventCode": "0xFD", + "EventName": "SIMD_INT_64.UNPACK", + "SampleAfterValue": "200000", + "UMask": "0x8" + } +] |