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Diffstat (limited to '')
-rw-r--r-- | Documentation/arch/riscv/acpi.rst (renamed from Documentation/riscv/acpi.rst) | 0 | ||||
-rw-r--r-- | Documentation/arch/riscv/boot-image-header.rst (renamed from Documentation/riscv/boot-image-header.rst) | 0 | ||||
-rw-r--r-- | Documentation/arch/riscv/boot.rst (renamed from Documentation/riscv/boot.rst) | 0 | ||||
-rw-r--r-- | Documentation/arch/riscv/features.rst (renamed from Documentation/riscv/features.rst) | 0 | ||||
-rw-r--r-- | Documentation/arch/riscv/hwprobe.rst (renamed from Documentation/riscv/hwprobe.rst) | 6 | ||||
-rw-r--r-- | Documentation/arch/riscv/index.rst (renamed from Documentation/riscv/index.rst) | 0 | ||||
-rw-r--r-- | Documentation/arch/riscv/patch-acceptance.rst (renamed from Documentation/riscv/patch-acceptance.rst) | 0 | ||||
-rw-r--r-- | Documentation/arch/riscv/uabi.rst (renamed from Documentation/riscv/uabi.rst) | 20 | ||||
-rw-r--r-- | Documentation/arch/riscv/vector.rst (renamed from Documentation/riscv/vector.rst) | 0 | ||||
-rw-r--r-- | Documentation/arch/riscv/vm-layout.rst (renamed from Documentation/riscv/vm-layout.rst) | 0 |
10 files changed, 26 insertions, 0 deletions
diff --git a/Documentation/riscv/acpi.rst b/Documentation/arch/riscv/acpi.rst index 9870a28281..9870a28281 100644 --- a/Documentation/riscv/acpi.rst +++ b/Documentation/arch/riscv/acpi.rst diff --git a/Documentation/riscv/boot-image-header.rst b/Documentation/arch/riscv/boot-image-header.rst index df2ffc173e..df2ffc173e 100644 --- a/Documentation/riscv/boot-image-header.rst +++ b/Documentation/arch/riscv/boot-image-header.rst diff --git a/Documentation/riscv/boot.rst b/Documentation/arch/riscv/boot.rst index 6077b587a8..6077b587a8 100644 --- a/Documentation/riscv/boot.rst +++ b/Documentation/arch/riscv/boot.rst diff --git a/Documentation/riscv/features.rst b/Documentation/arch/riscv/features.rst index 36e90144ad..36e90144ad 100644 --- a/Documentation/riscv/features.rst +++ b/Documentation/arch/riscv/features.rst diff --git a/Documentation/riscv/hwprobe.rst b/Documentation/arch/riscv/hwprobe.rst index a52996b22f..7b2384de47 100644 --- a/Documentation/riscv/hwprobe.rst +++ b/Documentation/arch/riscv/hwprobe.rst @@ -77,6 +77,9 @@ The following keys are defined: * :c:macro:`RISCV_HWPROBE_EXT_ZBS`: The Zbs extension is supported, as defined in version 1.0 of the Bit-Manipulation ISA extensions. + * :c:macro:`RISCV_HWPROBE_EXT_ZICBOZ`: The Zicboz extension is supported, as + ratified in commit 3dd606f ("Create cmobase-v1.0.pdf") of riscv-CMOs. + * :c:macro:`RISCV_HWPROBE_KEY_CPUPERF_0`: A bitmask that contains performance information about the selected set of processors. @@ -96,3 +99,6 @@ The following keys are defined: * :c:macro:`RISCV_HWPROBE_MISALIGNED_UNSUPPORTED`: Misaligned accesses are not supported at all and will generate a misaligned address fault. + +* :c:macro:`RISCV_HWPROBE_KEY_ZICBOZ_BLOCK_SIZE`: An unsigned int which + represents the size of the Zicboz block in bytes. diff --git a/Documentation/riscv/index.rst b/Documentation/arch/riscv/index.rst index 4dab0cb4b9..4dab0cb4b9 100644 --- a/Documentation/riscv/index.rst +++ b/Documentation/arch/riscv/index.rst diff --git a/Documentation/riscv/patch-acceptance.rst b/Documentation/arch/riscv/patch-acceptance.rst index 634aa222b4..634aa222b4 100644 --- a/Documentation/riscv/patch-acceptance.rst +++ b/Documentation/arch/riscv/patch-acceptance.rst diff --git a/Documentation/riscv/uabi.rst b/Documentation/arch/riscv/uabi.rst index 8960fac42c..54d199dce7 100644 --- a/Documentation/riscv/uabi.rst +++ b/Documentation/arch/riscv/uabi.rst @@ -42,6 +42,26 @@ An example string following the order is:: rv64imadc_zifoo_zigoo_zafoo_sbar_scar_zxmbaz_xqux_xrux +"isa" and "hart isa" lines in /proc/cpuinfo +------------------------------------------- + +The "isa" line in /proc/cpuinfo describes the lowest common denominator of +RISC-V ISA extensions recognized by the kernel and implemented on all harts. The +"hart isa" line, in contrast, describes the set of extensions recognized by the +kernel on the particular hart being described, even if those extensions may not +be present on all harts in the system. + +In both lines, the presence of an extension guarantees only that the hardware +has the described capability. Additional kernel support or policy changes may be +required before an extension's capability is fully usable by userspace programs. +Similarly, for S-mode extensions, presence in one of these lines does not +guarantee that the kernel is taking advantage of the extension, or that the +feature will be visible in guest VMs managed by this kernel. + +Inversely, the absence of an extension in these lines does not necessarily mean +the hardware does not support that feature. The running kernel may not recognize +the extension, or may have deliberately removed it from the listing. + Misaligned accesses ------------------- diff --git a/Documentation/riscv/vector.rst b/Documentation/arch/riscv/vector.rst index 75dd88a62e..75dd88a62e 100644 --- a/Documentation/riscv/vector.rst +++ b/Documentation/arch/riscv/vector.rst diff --git a/Documentation/riscv/vm-layout.rst b/Documentation/arch/riscv/vm-layout.rst index 69ff6da1db..69ff6da1db 100644 --- a/Documentation/riscv/vm-layout.rst +++ b/Documentation/arch/riscv/vm-layout.rst |