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Diffstat (limited to 'Documentation/devicetree/bindings/cpu/idle-states.yaml')
| -rw-r--r-- | Documentation/devicetree/bindings/cpu/idle-states.yaml | 81 |
1 files changed, 77 insertions, 4 deletions
diff --git a/Documentation/devicetree/bindings/cpu/idle-states.yaml b/Documentation/devicetree/bindings/cpu/idle-states.yaml index b3a5356f99..239480ef7c 100644 --- a/Documentation/devicetree/bindings/cpu/idle-states.yaml +++ b/Documentation/devicetree/bindings/cpu/idle-states.yaml @@ -243,7 +243,64 @@ description: |+ just supports idle_standby, an idle-states node is not required. =========================================== - 6 - References + 6 - Qualcomm specific STATES + =========================================== + + Idle states have different enter/exit latency and residency values. + The idle states supported by the QCOM SoC are defined as - + + * Standby + * Retention + * Standalone Power Collapse (Standalone PC or SPC) + * Power Collapse (PC) + + Standby: Standby does a little more in addition to architectural clock gating. + When the WFI instruction is executed the ARM core would gate its internal + clocks. In addition to gating the clocks, QCOM cpus use this instruction as a + trigger to execute the SPM state machine. The SPM state machine waits for the + interrupt to trigger the core back in to active. This triggers the cache + hierarchy to enter standby states, when all cpus are idle. An interrupt brings + the SPM state machine out of its wait, the next step is to ensure that the + cache hierarchy is also out of standby, and then the cpu is allowed to resume + execution. This state is defined as a generic ARM WFI state by the ARM cpuidle + driver and is not defined in the DT. The SPM state machine should be + configured to execute this state by default and after executing every other + state below. + + Retention: Retention is a low power state where the core is clock gated and + the memory and the registers associated with the core are retained. The + voltage may be reduced to the minimum value needed to keep the processor + registers active. The SPM should be configured to execute the retention + sequence and would wait for interrupt, before restoring the cpu to execution + state. Retention may have a slightly higher latency than Standby. + + Standalone PC: A cpu can power down and warmboot if there is a sufficient time + between the time it enters idle and the next known wake up. SPC mode is used + to indicate a core entering a power down state without consulting any other + cpu or the system resources. This helps save power only on that core. The SPM + sequence for this idle state is programmed to power down the supply to the + core, wait for the interrupt, restore power to the core, and ensure the + system state including cache hierarchy is ready before allowing core to + resume. Applying power and resetting the core causes the core to warmboot + back into Elevation Level (EL) which trampolines the control back to the + kernel. Entering a power down state for the cpu, needs to be done by trapping + into a EL. Failing to do so, would result in a crash enforced by the warm boot + code in the EL for the SoC. On SoCs with write-back L1 cache, the cache has to + be flushed in s/w, before powering down the core. + + Power Collapse: This state is similar to the SPC mode, but distinguishes + itself in that the cpu acknowledges and permits the SoC to enter deeper sleep + modes. In a hierarchical power domain SoC, this means L2 and other caches can + be flushed, system bus, clocks - lowered, and SoC main XO clock gated and + voltages reduced, provided all cpus enter this state. Since the span of low + power modes possible at this state is vast, the exit latency and the residency + of this low power mode would be considered high even though at a cpu level, + this essentially is cpu power down. The SPM in this state also may handshake + with the Resource power manager (RPM) processor in the SoC to indicate a + complete application processor subsystem shut down. + + =========================================== + 7 - References =========================================== [1] ARM Linux Kernel documentation - CPUs bindings @@ -301,9 +358,16 @@ patternProperties: properties: compatible: - enum: - - arm,idle-state - - riscv,idle-state + oneOf: + - items: + - enum: + - qcom,idle-state-ret + - qcom,idle-state-spc + - qcom,idle-state-pc + - const: arm,idle-state + - enum: + - arm,idle-state + - riscv,idle-state arm,psci-suspend-param: $ref: /schemas/types.yaml#/definitions/uint32 @@ -852,4 +916,13 @@ examples: }; }; + // Example 4 - Qualcomm SPC + idle-states { + cpu_spc: cpu-spc { + compatible = "qcom,idle-state-spc", "arm,idle-state"; + entry-latency-us = <150>; + exit-latency-us = <200>; + min-residency-us = <2000>; + }; + }; ... |