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+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/phy/microchip,lan966x-serdes.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Microchip Lan966x Serdes controller
+
+maintainers:
+ - Horatiu Vultur <horatiu.vultur@microchip.com>
+
+description: |
+ Lan966x has 7 interfaces, consisting of 2 copper transceivers(CU),
+ 3 SERDES6G and 2 RGMII interfaces. Two of the SERDES6G support QSGMII.
+ Also it has 8 logical Ethernet ports which can be connected to these
+ interfaces. The Serdes controller will allow to configure these interfaces
+ and allows to "mux" the interfaces to different ports.
+
+ For simple selection of the interface that is used with a port, the
+ following macros are defined CU(X), SERDES6G(X), RGMII(X). Where X is a
+ number that represents the index of that interface type. For example
+ CU(1) means use interface copper transceivers 1. SERDES6G(2) means use
+ interface SerDes 2.
+
+properties:
+ $nodename:
+ pattern: "^serdes@[0-9a-f]+$"
+
+ compatible:
+ const: microchip,lan966x-serdes
+
+ reg:
+ items:
+ - description: HSIO registers
+ - description: HW_STAT register
+
+ '#phy-cells':
+ const: 2
+ description: |
+ - Input port to use for a given macro.
+ - The macro to be used. The macros are defined in
+ dt-bindings/phy/phy-lan966x-serdes.
+
+required:
+ - compatible
+ - reg
+ - '#phy-cells'
+
+additionalProperties: false
+
+examples:
+ - |
+ serdes: serdes@e2004010 {
+ compatible = "microchip,lan966x-serdes";
+ reg = <0xe202c000 0x9c>, <0xe2004010 0x4>;
+ #phy-cells = <2>;
+ };
+
+...