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-rw-r--r--Documentation/devicetree/bindings/riscv/cpus.yaml10
-rw-r--r--Documentation/devicetree/bindings/riscv/extensions.yaml7
2 files changed, 16 insertions, 1 deletions
diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml
index 9d8670c00e..d87dd50f1a 100644
--- a/Documentation/devicetree/bindings/riscv/cpus.yaml
+++ b/Documentation/devicetree/bindings/riscv/cpus.yaml
@@ -75,6 +75,10 @@ properties:
- riscv,sv57
- riscv,none
+ reg:
+ description:
+ The hart ID of this CPU node.
+
riscv,cbom-block-size:
$ref: /schemas/types.yaml#/definitions/uint32
description:
@@ -106,7 +110,11 @@ properties:
const: 1
compatible:
- const: riscv,cpu-intc
+ oneOf:
+ - items:
+ - const: andestech,cpu-intc
+ - const: riscv,cpu-intc
+ - const: riscv,cpu-intc
interrupt-controller: true
diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Documentation/devicetree/bindings/riscv/extensions.yaml
index 63d81dc895..468c646247 100644
--- a/Documentation/devicetree/bindings/riscv/extensions.yaml
+++ b/Documentation/devicetree/bindings/riscv/extensions.yaml
@@ -477,5 +477,12 @@ properties:
latency, as ratified in commit 56ed795 ("Update
riscv-crypto-spec-vector.adoc") of riscv-crypto.
+ - const: xandespmu
+ description:
+ The Andes Technology performance monitor extension for counter overflow
+ and privilege mode filtering. For more details, see Counter Related
+ Registers in the AX45MP datasheet.
+ https://www.andestech.com/wp-content/uploads/AX45MP-1C-Rev.-5.0.0-Datasheet.pdf
+
additionalProperties: true
...