diff options
Diffstat (limited to 'arch/arm/boot/dts/hisilicon/hip01-ca9x2.dts')
-rw-r--r-- | arch/arm/boot/dts/hisilicon/hip01-ca9x2.dts | 48 |
1 files changed, 48 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/hisilicon/hip01-ca9x2.dts b/arch/arm/boot/dts/hisilicon/hip01-ca9x2.dts new file mode 100644 index 0000000000..f3faf247cd --- /dev/null +++ b/arch/arm/boot/dts/hisilicon/hip01-ca9x2.dts @@ -0,0 +1,48 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * HiSilicon Ltd. HiP01 SoC + * + * Copyright (C) 2014 HiSilicon Ltd. + * Copyright (C) 2014 Huawei Ltd. + * + * Author: Wang Long <long.wanglong@huawei.com> + */ + +/dts-v1/; + +/* First 8KB reserved for secondary core boot */ +/memreserve/ 0x80000000 0x00002000; + +#include "hip01.dtsi" + +/ { + model = "Hisilicon HIP01 Development Board"; + compatible = "hisilicon,hip01-ca9x2", "hisilicon,hip01"; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + enable-method = "hisilicon,hip01-smp"; + + cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + reg = <0>; + }; + + cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + reg = <1>; + }; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x80000000 0x80000000>; + }; +}; + +&uart0 { + status = "okay"; +}; |